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drm/i915: Simplify PSR debugfs
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
3dec0095 44static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 45static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 46
f1f644dc
JB		 47static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
48 struct intel_crtc_config *pipe_config);
18442d08
VS		 49static void ironlake_pch_clock_get(struct intel_crtc *crtc,
50 struct intel_crtc_config *pipe_config);
f1f644dc 51
e7457a9a
DL		 52static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
53 int x, int y, struct drm_framebuffer *old_fb);
54
55
79e53945 56typedef struct {
0206e353 57 int min, max;
79e53945
JB		 58} intel_range_t;
59
60typedef struct {
0206e353
AJ		 61 int dot_limit;
62 int p2_slow, p2_fast;
79e53945
JB		 63} intel_p2_t;
64
d4906093
ML		 65typedef struct intel_limit intel_limit_t;
66struct intel_limit {
0206e353
AJ		 67 intel_range_t dot, vco, n, m, m1, m2, p, p1;
68 intel_p2_t p2;
d4906093 69};
79e53945 70
d2acd215
DV		 71int
72intel_pch_rawclk(struct drm_device *dev)
73{
74 struct drm_i915_private *dev_priv = dev->dev_private;
75
76 WARN_ON(!HAS_PCH_SPLIT(dev));
77
78 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
79}
80
021357ac
CW		 81static inline u32 /* units of 100MHz */
82intel_fdi_link_freq(struct drm_device *dev)
83{
8b99e68c
CW		 84 if (IS_GEN5(dev)) {
85 struct drm_i915_private *dev_priv = dev->dev_private;
86 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
87 } else
88 return 27;
021357ac
CW		 89}
90
5d536e28 91static const intel_limit_t intel_limits_i8xx_dac = {
0206e353
AJ		 92 .dot = { .min = 25000, .max = 350000 },
93 .vco = { .min = 930000, .max = 1400000 },
94 .n = { .min = 3, .max = 16 },
95 .m = { .min = 96, .max = 140 },
96 .m1 = { .min = 18, .max = 26 },
97 .m2 = { .min = 6, .max = 16 },
98 .p = { .min = 4, .max = 128 },
99 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 100 .p2 = { .dot_limit = 165000,
101 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 102};
103
5d536e28
DV		 104static const intel_limit_t intel_limits_i8xx_dvo = {
105 .dot = { .min = 25000, .max = 350000 },
106 .vco = { .min = 930000, .max = 1400000 },
107 .n = { .min = 3, .max = 16 },
108 .m = { .min = 96, .max = 140 },
109 .m1 = { .min = 18, .max = 26 },
110 .m2 = { .min = 6, .max = 16 },
111 .p = { .min = 4, .max = 128 },
112 .p1 = { .min = 2, .max = 33 },
113 .p2 = { .dot_limit = 165000,
114 .p2_slow = 4, .p2_fast = 4 },
115};
116
e4b36699 117static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 118 .dot = { .min = 25000, .max = 350000 },
119 .vco = { .min = 930000, .max = 1400000 },
120 .n = { .min = 3, .max = 16 },
121 .m = { .min = 96, .max = 140 },
122 .m1 = { .min = 18, .max = 26 },
123 .m2 = { .min = 6, .max = 16 },
124 .p = { .min = 4, .max = 128 },
125 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 126 .p2 = { .dot_limit = 165000,
127 .p2_slow = 14, .p2_fast = 7 },
e4b36699 128};
273e27ca 129
e4b36699 130static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 131 .dot = { .min = 20000, .max = 400000 },
132 .vco = { .min = 1400000, .max = 2800000 },
133 .n = { .min = 1, .max = 6 },
134 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 135 .m1 = { .min = 8, .max = 18 },
136 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 137 .p = { .min = 5, .max = 80 },
138 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 139 .p2 = { .dot_limit = 200000,
140 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 141};
142
143static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 144 .dot = { .min = 20000, .max = 400000 },
145 .vco = { .min = 1400000, .max = 2800000 },
146 .n = { .min = 1, .max = 6 },
147 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 148 .m1 = { .min = 8, .max = 18 },
149 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 150 .p = { .min = 7, .max = 98 },
151 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 152 .p2 = { .dot_limit = 112000,
153 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 154};
155
273e27ca 156
e4b36699 157static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 158 .dot = { .min = 25000, .max = 270000 },
159 .vco = { .min = 1750000, .max = 3500000},
160 .n = { .min = 1, .max = 4 },
161 .m = { .min = 104, .max = 138 },
162 .m1 = { .min = 17, .max = 23 },
163 .m2 = { .min = 5, .max = 11 },
164 .p = { .min = 10, .max = 30 },
165 .p1 = { .min = 1, .max = 3},
166 .p2 = { .dot_limit = 270000,
167 .p2_slow = 10,
168 .p2_fast = 10
044c7c41 169 },
e4b36699
KP		 170};
171
172static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 173 .dot = { .min = 22000, .max = 400000 },
174 .vco = { .min = 1750000, .max = 3500000},
175 .n = { .min = 1, .max = 4 },
176 .m = { .min = 104, .max = 138 },
177 .m1 = { .min = 16, .max = 23 },
178 .m2 = { .min = 5, .max = 11 },
179 .p = { .min = 5, .max = 80 },
180 .p1 = { .min = 1, .max = 8},
181 .p2 = { .dot_limit = 165000,
182 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 183};
184
185static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 186 .dot = { .min = 20000, .max = 115000 },
187 .vco = { .min = 1750000, .max = 3500000 },
188 .n = { .min = 1, .max = 3 },
189 .m = { .min = 104, .max = 138 },
190 .m1 = { .min = 17, .max = 23 },
191 .m2 = { .min = 5, .max = 11 },
192 .p = { .min = 28, .max = 112 },
193 .p1 = { .min = 2, .max = 8 },
194 .p2 = { .dot_limit = 0,
195 .p2_slow = 14, .p2_fast = 14
044c7c41 196 },
e4b36699
KP		 197};
198
199static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 200 .dot = { .min = 80000, .max = 224000 },
201 .vco = { .min = 1750000, .max = 3500000 },
202 .n = { .min = 1, .max = 3 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 17, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 14, .max = 42 },
207 .p1 = { .min = 2, .max = 6 },
208 .p2 = { .dot_limit = 0,
209 .p2_slow = 7, .p2_fast = 7
044c7c41 210 },
e4b36699
KP		 211};
212
f2b115e6 213static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 214 .dot = { .min = 20000, .max = 400000},
215 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 216 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 217 .n = { .min = 3, .max = 6 },
218 .m = { .min = 2, .max = 256 },
273e27ca 219 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 220 .m1 = { .min = 0, .max = 0 },
221 .m2 = { .min = 0, .max = 254 },
222 .p = { .min = 5, .max = 80 },
223 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 224 .p2 = { .dot_limit = 200000,
225 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 226};
227
f2b115e6 228static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 229 .dot = { .min = 20000, .max = 400000 },
230 .vco = { .min = 1700000, .max = 3500000 },
231 .n = { .min = 3, .max = 6 },
232 .m = { .min = 2, .max = 256 },
233 .m1 = { .min = 0, .max = 0 },
234 .m2 = { .min = 0, .max = 254 },
235 .p = { .min = 7, .max = 112 },
236 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 237 .p2 = { .dot_limit = 112000,
238 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 239};
240
273e27ca
EA		 241/* Ironlake / Sandybridge
242 *
243 * We calculate clock using (register_value + 2) for N/M1/M2, so here
244 * the range value for them is (actual_value - 2).
245 */
b91ad0ec 246static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 247 .dot = { .min = 25000, .max = 350000 },
248 .vco = { .min = 1760000, .max = 3510000 },
249 .n = { .min = 1, .max = 5 },
250 .m = { .min = 79, .max = 127 },
251 .m1 = { .min = 12, .max = 22 },
252 .m2 = { .min = 5, .max = 9 },
253 .p = { .min = 5, .max = 80 },
254 .p1 = { .min = 1, .max = 8 },
255 .p2 = { .dot_limit = 225000,
256 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 257};
258
b91ad0ec 259static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 260 .dot = { .min = 25000, .max = 350000 },
261 .vco = { .min = 1760000, .max = 3510000 },
262 .n = { .min = 1, .max = 3 },
263 .m = { .min = 79, .max = 118 },
264 .m1 = { .min = 12, .max = 22 },
265 .m2 = { .min = 5, .max = 9 },
266 .p = { .min = 28, .max = 112 },
267 .p1 = { .min = 2, .max = 8 },
268 .p2 = { .dot_limit = 225000,
269 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 270};
271
272static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 273 .dot = { .min = 25000, .max = 350000 },
274 .vco = { .min = 1760000, .max = 3510000 },
275 .n = { .min = 1, .max = 3 },
276 .m = { .min = 79, .max = 127 },
277 .m1 = { .min = 12, .max = 22 },
278 .m2 = { .min = 5, .max = 9 },
279 .p = { .min = 14, .max = 56 },
280 .p1 = { .min = 2, .max = 8 },
281 .p2 = { .dot_limit = 225000,
282 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 283};
284
273e27ca 285/* LVDS 100mhz refclk limits. */
b91ad0ec 286static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 287 .dot = { .min = 25000, .max = 350000 },
288 .vco = { .min = 1760000, .max = 3510000 },
289 .n = { .min = 1, .max = 2 },
290 .m = { .min = 79, .max = 126 },
291 .m1 = { .min = 12, .max = 22 },
292 .m2 = { .min = 5, .max = 9 },
293 .p = { .min = 28, .max = 112 },
0206e353 294 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 295 .p2 = { .dot_limit = 225000,
296 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 297};
298
299static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 300 .dot = { .min = 25000, .max = 350000 },
301 .vco = { .min = 1760000, .max = 3510000 },
302 .n = { .min = 1, .max = 3 },
303 .m = { .min = 79, .max = 126 },
304 .m1 = { .min = 12, .max = 22 },
305 .m2 = { .min = 5, .max = 9 },
306 .p = { .min = 14, .max = 42 },
0206e353 307 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 308 .p2 = { .dot_limit = 225000,
309 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 310};
311
a0c4da24
JB		 312static const intel_limit_t intel_limits_vlv_dac = {
313 .dot = { .min = 25000, .max = 270000 },
314 .vco = { .min = 4000000, .max = 6000000 },
315 .n = { .min = 1, .max = 7 },
316 .m = { .min = 22, .max = 450 }, /* guess */
317 .m1 = { .min = 2, .max = 3 },
318 .m2 = { .min = 11, .max = 156 },
319 .p = { .min = 10, .max = 30 },
75e53986 320 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 321 .p2 = { .dot_limit = 270000,
322 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 323};
324
325static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 326 .dot = { .min = 25000, .max = 270000 },
327 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 328 .n = { .min = 1, .max = 7 },
329 .m = { .min = 60, .max = 300 }, /* guess */
330 .m1 = { .min = 2, .max = 3 },
331 .m2 = { .min = 11, .max = 156 },
332 .p = { .min = 10, .max = 30 },
333 .p1 = { .min = 2, .max = 3 },
334 .p2 = { .dot_limit = 270000,
335 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 336};
337
e0638cdf
PZ		 338/**
339 * Returns whether any output on the specified pipe is of the specified type
340 */
341static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
342{
343 struct drm_device *dev = crtc->dev;
344 struct intel_encoder *encoder;
345
346 for_each_encoder_on_crtc(dev, crtc, encoder)
347 if (encoder->type == type)
348 return true;
349
350 return false;
351}
352
1b894b59
CW		 353static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
354 int refclk)
2c07245f 355{
b91ad0ec 356 struct drm_device *dev = crtc->dev;
2c07245f 357 const intel_limit_t *limit;
b91ad0ec
ZW		 358
359 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 360 if (intel_is_dual_link_lvds(dev)) {
1b894b59 361 if (refclk == 100000)
b91ad0ec
ZW		 362 limit = &intel_limits_ironlake_dual_lvds_100m;
363 else
364 limit = &intel_limits_ironlake_dual_lvds;
365 } else {
1b894b59 366 if (refclk == 100000)
b91ad0ec
ZW		 367 limit = &intel_limits_ironlake_single_lvds_100m;
368 else
369 limit = &intel_limits_ironlake_single_lvds;
370 }
c6bb3538 371 } else
b91ad0ec 372 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 373
374 return limit;
375}
376
044c7c41
ML		 377static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
378{
379 struct drm_device *dev = crtc->dev;
044c7c41
ML		 380 const intel_limit_t *limit;
381
382 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 383 if (intel_is_dual_link_lvds(dev))
e4b36699 384 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 385 else
e4b36699 386 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 387 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
388 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 389 limit = &intel_limits_g4x_hdmi;
044c7c41 390 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 391 limit = &intel_limits_g4x_sdvo;
044c7c41 392 } else /* The option is for other outputs */
e4b36699 393 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 394
395 return limit;
396}
397
1b894b59 398static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 399{
400 struct drm_device *dev = crtc->dev;
401 const intel_limit_t *limit;
402
bad720ff 403 if (HAS_PCH_SPLIT(dev))
1b894b59 404 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 405 else if (IS_G4X(dev)) {
044c7c41 406 limit = intel_g4x_limit(crtc);
f2b115e6 407 } else if (IS_PINEVIEW(dev)) {
2177832f 408 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 409 limit = &intel_limits_pineview_lvds;
2177832f 410 else
f2b115e6 411 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 412 } else if (IS_VALLEYVIEW(dev)) {
413 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
414 limit = &intel_limits_vlv_dac;
a0c4da24 415 else
65ce4bf5 416 limit = &intel_limits_vlv_hdmi;
a6c45cf0
CW		 417 } else if (!IS_GEN2(dev)) {
418 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
419 limit = &intel_limits_i9xx_lvds;
420 else
421 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 422 } else {
423 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 424 limit = &intel_limits_i8xx_lvds;
5d536e28 425 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
e4b36699 426 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 427 else
428 limit = &intel_limits_i8xx_dac;
79e53945
JB		 429 }
430 return limit;
431}
432
f2b115e6
AJ		 433/* m1 is reserved as 0 in Pineview, n is a ring counter */
434static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 435{
2177832f
SL		 436 clock->m = clock->m2 + 2;
437 clock->p = clock->p1 * clock->p2;
438 clock->vco = refclk * clock->m / clock->n;
439 clock->dot = clock->vco / clock->p;
440}
441
7429e9d4
DV		 442static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
443{
444 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
445}
446
ac58c3f0 447static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 448{
7429e9d4 449 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 450 clock->p = clock->p1 * clock->p2;
451 clock->vco = refclk * clock->m / (clock->n + 2);
452 clock->dot = clock->vco / clock->p;
453}
454
7c04d1d9 455#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 456/**
457 * Returns whether the given set of divisors are valid for a given refclk with
458 * the given connectors.
459 */
460
1b894b59
CW		 461static bool intel_PLL_is_valid(struct drm_device *dev,
462 const intel_limit_t *limit,
463 const intel_clock_t *clock)
79e53945 464{
79e53945 465 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 466 INTELPllInvalid("p1 out of range\n");
79e53945 467 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 468 INTELPllInvalid("p out of range\n");
79e53945 469 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 470 INTELPllInvalid("m2 out of range\n");
79e53945 471 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 472 INTELPllInvalid("m1 out of range\n");
f2b115e6 473 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 474 INTELPllInvalid("m1 <= m2\n");
79e53945 475 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 476 INTELPllInvalid("m out of range\n");
79e53945 477 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 478 INTELPllInvalid("n out of range\n");
79e53945 479 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 480 INTELPllInvalid("vco out of range\n");
79e53945
JB		 481 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
482 * connector, etc., rather than just a single range.
483 */
484 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 485 INTELPllInvalid("dot out of range\n");
79e53945
JB		 486
487 return true;
488}
489
d4906093 490static bool
ee9300bb 491i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 492 int target, int refclk, intel_clock_t *match_clock,
493 intel_clock_t *best_clock)
79e53945
JB		 494{
495 struct drm_device *dev = crtc->dev;
79e53945 496 intel_clock_t clock;
79e53945
JB		 497 int err = target;
498
a210b028 499 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 500 /*
a210b028
DV		 501 * For LVDS just rely on its current settings for dual-channel.
502 * We haven't figured out how to reliably set up different
503 * single/dual channel state, if we even can.
79e53945 504 */
1974cad0 505 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 506 clock.p2 = limit->p2.p2_fast;
507 else
508 clock.p2 = limit->p2.p2_slow;
509 } else {
510 if (target < limit->p2.dot_limit)
511 clock.p2 = limit->p2.p2_slow;
512 else
513 clock.p2 = limit->p2.p2_fast;
514 }
515
0206e353 516 memset(best_clock, 0, sizeof(*best_clock));
79e53945 517
42158660
ZY		 518 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
519 clock.m1++) {
520 for (clock.m2 = limit->m2.min;
521 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 522 if (clock.m2 >= clock.m1)
42158660
ZY		 523 break;
524 for (clock.n = limit->n.min;
525 clock.n <= limit->n.max; clock.n++) {
526 for (clock.p1 = limit->p1.min;
527 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 528 int this_err;
529
ac58c3f0
DV		 530 i9xx_clock(refclk, &clock);
531 if (!intel_PLL_is_valid(dev, limit,
532 &clock))
533 continue;
534 if (match_clock &&
535 clock.p != match_clock->p)
536 continue;
537
538 this_err = abs(clock.dot - target);
539 if (this_err < err) {
540 *best_clock = clock;
541 err = this_err;
542 }
543 }
544 }
545 }
546 }
547
548 return (err != target);
549}
550
551static bool
ee9300bb
DV		 552pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
553 int target, int refclk, intel_clock_t *match_clock,
554 intel_clock_t *best_clock)
79e53945
JB		 555{
556 struct drm_device *dev = crtc->dev;
79e53945 557 intel_clock_t clock;
79e53945
JB		 558 int err = target;
559
a210b028 560 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 561 /*
a210b028
DV		 562 * For LVDS just rely on its current settings for dual-channel.
563 * We haven't figured out how to reliably set up different
564 * single/dual channel state, if we even can.
79e53945 565 */
1974cad0 566 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 567 clock.p2 = limit->p2.p2_fast;
568 else
569 clock.p2 = limit->p2.p2_slow;
570 } else {
571 if (target < limit->p2.dot_limit)
572 clock.p2 = limit->p2.p2_slow;
573 else
574 clock.p2 = limit->p2.p2_fast;
575 }
576
0206e353 577 memset(best_clock, 0, sizeof(*best_clock));
79e53945 578
42158660
ZY		 579 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
580 clock.m1++) {
581 for (clock.m2 = limit->m2.min;
582 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 583 for (clock.n = limit->n.min;
584 clock.n <= limit->n.max; clock.n++) {
585 for (clock.p1 = limit->p1.min;
586 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 587 int this_err;
588
ac58c3f0 589 pineview_clock(refclk, &clock);
1b894b59
CW		 590 if (!intel_PLL_is_valid(dev, limit,
591 &clock))
79e53945 592 continue;
cec2f356
SP		 593 if (match_clock &&
594 clock.p != match_clock->p)
595 continue;
79e53945
JB		 596
597 this_err = abs(clock.dot - target);
598 if (this_err < err) {
599 *best_clock = clock;
600 err = this_err;
601 }
602 }
603 }
604 }
605 }
606
607 return (err != target);
608}
609
d4906093 610static bool
ee9300bb
DV		 611g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
612 int target, int refclk, intel_clock_t *match_clock,
613 intel_clock_t *best_clock)
d4906093
ML		 614{
615 struct drm_device *dev = crtc->dev;
d4906093
ML		 616 intel_clock_t clock;
617 int max_n;
618 bool found;
6ba770dc
AJ		 619 /* approximately equals target * 0.00585 */
620 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 621 found = false;
622
623 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 624 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 625 clock.p2 = limit->p2.p2_fast;
626 else
627 clock.p2 = limit->p2.p2_slow;
628 } else {
629 if (target < limit->p2.dot_limit)
630 clock.p2 = limit->p2.p2_slow;
631 else
632 clock.p2 = limit->p2.p2_fast;
633 }
634
635 memset(best_clock, 0, sizeof(*best_clock));
636 max_n = limit->n.max;
f77f13e2 637 /* based on hardware requirement, prefer smaller n to precision */
d4906093 638 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 639 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 640 for (clock.m1 = limit->m1.max;
641 clock.m1 >= limit->m1.min; clock.m1--) {
642 for (clock.m2 = limit->m2.max;
643 clock.m2 >= limit->m2.min; clock.m2--) {
644 for (clock.p1 = limit->p1.max;
645 clock.p1 >= limit->p1.min; clock.p1--) {
646 int this_err;
647
ac58c3f0 648 i9xx_clock(refclk, &clock);
1b894b59
CW		 649 if (!intel_PLL_is_valid(dev, limit,
650 &clock))
d4906093 651 continue;
1b894b59
CW		 652
653 this_err = abs(clock.dot - target);
d4906093
ML		 654 if (this_err < err_most) {
655 *best_clock = clock;
656 err_most = this_err;
657 max_n = clock.n;
658 found = true;
659 }
660 }
661 }
662 }
663 }
2c07245f
ZW		 664 return found;
665}
666
a0c4da24 667static bool
ee9300bb
DV		 668vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
669 int target, int refclk, intel_clock_t *match_clock,
670 intel_clock_t *best_clock)
a0c4da24
JB		 671{
672 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
673 u32 m, n, fastclk;
f3f08572 674 u32 updrate, minupdate, p;
a0c4da24
JB		 675 unsigned long bestppm, ppm, absppm;
676 int dotclk, flag;
677
af447bd3 678 flag = 0;
a0c4da24
JB		 679 dotclk = target * 1000;
680 bestppm = 1000000;
681 ppm = absppm = 0;
682 fastclk = dotclk / (2*100);
683 updrate = 0;
684 minupdate = 19200;
a0c4da24
JB		 685 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
686 bestm1 = bestm2 = bestp1 = bestp2 = 0;
687
688 /* based on hardware requirement, prefer smaller n to precision */
689 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
690 updrate = refclk / n;
691 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
692 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
693 if (p2 > 10)
694 p2 = p2 - 1;
695 p = p1 * p2;
696 /* based on hardware requirement, prefer bigger m1,m2 values */
697 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
5de56df5 698 m2 = DIV_ROUND_CLOSEST(fastclk * p * n, refclk * m1);
a0c4da24
JB		 699 m = m1 * m2;
700 vco = updrate * m;
43b0ac53
VS		 701
702 if (vco < limit->vco.min || vco >= limit->vco.max)
703 continue;
704
705 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
706 absppm = (ppm > 0) ? ppm : (-ppm);
707 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
708 bestppm = 0;
709 flag = 1;
710 }
711 if (absppm < bestppm - 10) {
712 bestppm = absppm;
713 flag = 1;
714 }
715 if (flag) {
716 bestn = n;
717 bestm1 = m1;
718 bestm2 = m2;
719 bestp1 = p1;
720 bestp2 = p2;
721 flag = 0;
a0c4da24
JB		 722 }
723 }
724 }
725 }
726 }
727 best_clock->n = bestn;
728 best_clock->m1 = bestm1;
729 best_clock->m2 = bestm2;
730 best_clock->p1 = bestp1;
731 best_clock->p2 = bestp2;
732
733 return true;
734}
a4fc5ed6 735
20ddf665
VS		 736bool intel_crtc_active(struct drm_crtc *crtc)
737{
738 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
739
740 /* Be paranoid as we can arrive here with only partial
741 * state retrieved from the hardware during setup.
742 *
241bfc38 743 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 744 * as Haswell has gained clock readout/fastboot support.
745 *
746 * We can ditch the crtc->fb check as soon as we can
747 * properly reconstruct framebuffers.
748 */
749 return intel_crtc->active && crtc->fb &&
241bfc38 750 intel_crtc->config.adjusted_mode.crtc_clock;
20ddf665
VS		 751}
752
a5c961d1
PZ		 753enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
754 enum pipe pipe)
755{
756 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
757 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
758
3b117c8f 759 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 760}
761
a928d536
PZ		 762static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
763{
764 struct drm_i915_private *dev_priv = dev->dev_private;
765 u32 frame, frame_reg = PIPEFRAME(pipe);
766
767 frame = I915_READ(frame_reg);
768
769 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
770 DRM_DEBUG_KMS("vblank wait timed out\n");
771}
772
9d0498a2
JB		 773/**
774 * intel_wait_for_vblank - wait for vblank on a given pipe
775 * @dev: drm device
776 * @pipe: pipe to wait for
777 *
778 * Wait for vblank to occur on a given pipe. Needed for various bits of
779 * mode setting code.
780 */
781void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 782{
9d0498a2 783 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 784 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 785
a928d536
PZ		 786 if (INTEL_INFO(dev)->gen >= 5) {
787 ironlake_wait_for_vblank(dev, pipe);
788 return;
789 }
790
300387c0
CW		 791 /* Clear existing vblank status. Note this will clear any other
792 * sticky status fields as well.
793 *
794 * This races with i915_driver_irq_handler() with the result
795 * that either function could miss a vblank event. Here it is not
796 * fatal, as we will either wait upon the next vblank interrupt or
797 * timeout. Generally speaking intel_wait_for_vblank() is only
798 * called during modeset at which time the GPU should be idle and
799 * should *not* be performing page flips and thus not waiting on
800 * vblanks...
801 * Currently, the result of us stealing a vblank from the irq
802 * handler is that a single frame will be skipped during swapbuffers.
803 */
804 I915_WRITE(pipestat_reg,
805 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
806
9d0498a2 807 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 808 if (wait_for(I915_READ(pipestat_reg) &
809 PIPE_VBLANK_INTERRUPT_STATUS,
810 50))
9d0498a2
JB		 811 DRM_DEBUG_KMS("vblank wait timed out\n");
812}
813
ab7ad7f6
KP		 814/*
815 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 816 * @dev: drm device
817 * @pipe: pipe to wait for
818 *
819 * After disabling a pipe, we can't wait for vblank in the usual way,
820 * spinning on the vblank interrupt status bit, since we won't actually
821 * see an interrupt when the pipe is disabled.
822 *
ab7ad7f6
KP		 823 * On Gen4 and above:
824 * wait for the pipe register state bit to turn off
825 *
826 * Otherwise:
827 * wait for the display line value to settle (it usually
828 * ends up stopping at the start of the next frame).
58e10eb9 829 *
9d0498a2 830 */
58e10eb9 831void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 832{
833 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 834 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
835 pipe);
ab7ad7f6
KP		 836
837 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 838 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 839
840 /* Wait for the Pipe State to go off */
58e10eb9
CW		 841 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
842 100))
284637d9 843 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 844 } else {
837ba00f 845 u32 last_line, line_mask;
58e10eb9 846 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 847 unsigned long timeout = jiffies + msecs_to_jiffies(100);
848
837ba00f
PZ		 849 if (IS_GEN2(dev))
850 line_mask = DSL_LINEMASK_GEN2;
851 else
852 line_mask = DSL_LINEMASK_GEN3;
853
ab7ad7f6
KP		 854 /* Wait for the display line to settle */
855 do {
837ba00f 856 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 857 mdelay(5);
837ba00f 858 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 859 time_after(timeout, jiffies));
860 if (time_after(jiffies, timeout))
284637d9 861 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 862 }
79e53945
JB		 863}
864
b0ea7d37
DL		 865/*
866 * ibx_digital_port_connected - is the specified port connected?
867 * @dev_priv: i915 private structure
868 * @port: the port to test
869 *
870 * Returns true if @port is connected, false otherwise.
871 */
872bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
873 struct intel_digital_port *port)
874{
875 u32 bit;
876
c36346e3
DL		 877 if (HAS_PCH_IBX(dev_priv->dev)) {
878 switch(port->port) {
879 case PORT_B:
880 bit = SDE_PORTB_HOTPLUG;
881 break;
882 case PORT_C:
883 bit = SDE_PORTC_HOTPLUG;
884 break;
885 case PORT_D:
886 bit = SDE_PORTD_HOTPLUG;
887 break;
888 default:
889 return true;
890 }
891 } else {
892 switch(port->port) {
893 case PORT_B:
894 bit = SDE_PORTB_HOTPLUG_CPT;
895 break;
896 case PORT_C:
897 bit = SDE_PORTC_HOTPLUG_CPT;
898 break;
899 case PORT_D:
900 bit = SDE_PORTD_HOTPLUG_CPT;
901 break;
902 default:
903 return true;
904 }
b0ea7d37
DL		 905 }
906
907 return I915_READ(SDEISR) & bit;
908}
909
b24e7179
JB		 910static const char *state_string(bool enabled)
911{
912 return enabled ? "on" : "off";
913}
914
915/* Only for pre-ILK configs */
55607e8a
DV		 916void assert_pll(struct drm_i915_private *dev_priv,
917 enum pipe pipe, bool state)
b24e7179
JB		 918{
919 int reg;
920 u32 val;
921 bool cur_state;
922
923 reg = DPLL(pipe);
924 val = I915_READ(reg);
925 cur_state = !!(val & DPLL_VCO_ENABLE);
926 WARN(cur_state != state,
927 "PLL state assertion failure (expected %s, current %s)\n",
928 state_string(state), state_string(cur_state));
929}
b24e7179 930
23538ef1
JN		 931/* XXX: the dsi pll is shared between MIPI DSI ports */
932static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
933{
934 u32 val;
935 bool cur_state;
936
937 mutex_lock(&dev_priv->dpio_lock);
938 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
939 mutex_unlock(&dev_priv->dpio_lock);
940
941 cur_state = val & DSI_PLL_VCO_EN;
942 WARN(cur_state != state,
943 "DSI PLL state assertion failure (expected %s, current %s)\n",
944 state_string(state), state_string(cur_state));
945}
946#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
947#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
948
55607e8a 949struct intel_shared_dpll *
e2b78267
DV		 950intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
951{
952 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
953
a43f6e0f 954 if (crtc->config.shared_dpll < 0)
e2b78267
DV		 955 return NULL;
956
a43f6e0f 957 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
e2b78267
DV		 958}
959
040484af 960/* For ILK+ */
55607e8a
DV		 961void assert_shared_dpll(struct drm_i915_private *dev_priv,
962 struct intel_shared_dpll *pll,
963 bool state)
040484af 964{
040484af 965 bool cur_state;
5358901f 966 struct intel_dpll_hw_state hw_state;
040484af 967
9d82aa17
ED		 968 if (HAS_PCH_LPT(dev_priv->dev)) {
969 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
970 return;
971 }
972
92b27b08 973 if (WARN (!pll,
46edb027 974 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 975 return;
ee7b9f93 976
5358901f 977 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
92b27b08 978 WARN(cur_state != state,
5358901f
DV		 979 "%s assertion failure (expected %s, current %s)\n",
980 pll->name, state_string(state), state_string(cur_state));
040484af 981}
040484af
JB		 982
983static void assert_fdi_tx(struct drm_i915_private *dev_priv,
984 enum pipe pipe, bool state)
985{
986 int reg;
987 u32 val;
988 bool cur_state;
ad80a810
PZ		 989 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
990 pipe);
040484af 991
affa9354
PZ		 992 if (HAS_DDI(dev_priv->dev)) {
993 /* DDI does not have a specific FDI_TX register */
ad80a810 994 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 995 val = I915_READ(reg);
ad80a810 996 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 997 } else {
998 reg = FDI_TX_CTL(pipe);
999 val = I915_READ(reg);
1000 cur_state = !!(val & FDI_TX_ENABLE);
1001 }
040484af
JB		 1002 WARN(cur_state != state,
1003 "FDI TX state assertion failure (expected %s, current %s)\n",
1004 state_string(state), state_string(cur_state));
1005}
1006#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1007#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1008
1009static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1010 enum pipe pipe, bool state)
1011{
1012 int reg;
1013 u32 val;
1014 bool cur_state;
1015
d63fa0dc
PZ		 1016 reg = FDI_RX_CTL(pipe);
1017 val = I915_READ(reg);
1018 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1019 WARN(cur_state != state,
1020 "FDI RX state assertion failure (expected %s, current %s)\n",
1021 state_string(state), state_string(cur_state));
1022}
1023#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1024#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1025
1026static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1027 enum pipe pipe)
1028{
1029 int reg;
1030 u32 val;
1031
1032 /* ILK FDI PLL is always enabled */
1033 if (dev_priv->info->gen == 5)
1034 return;
1035
bf507ef7 1036 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1037 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1038 return;
1039
040484af
JB		 1040 reg = FDI_TX_CTL(pipe);
1041 val = I915_READ(reg);
1042 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1043}
1044
55607e8a
DV		 1045void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1046 enum pipe pipe, bool state)
040484af
JB		 1047{
1048 int reg;
1049 u32 val;
55607e8a 1050 bool cur_state;
040484af
JB		 1051
1052 reg = FDI_RX_CTL(pipe);
1053 val = I915_READ(reg);
55607e8a
DV		 1054 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1055 WARN(cur_state != state,
1056 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1057 state_string(state), state_string(cur_state));
040484af
JB		 1058}
1059
ea0760cf
JB		 1060static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1061 enum pipe pipe)
1062{
1063 int pp_reg, lvds_reg;
1064 u32 val;
1065 enum pipe panel_pipe = PIPE_A;
0de3b485 1066 bool locked = true;
ea0760cf
JB		 1067
1068 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1069 pp_reg = PCH_PP_CONTROL;
1070 lvds_reg = PCH_LVDS;
1071 } else {
1072 pp_reg = PP_CONTROL;
1073 lvds_reg = LVDS;
1074 }
1075
1076 val = I915_READ(pp_reg);
1077 if (!(val & PANEL_POWER_ON) ||
1078 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1079 locked = false;
1080
1081 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1082 panel_pipe = PIPE_B;
1083
1084 WARN(panel_pipe == pipe && locked,
1085 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1086 pipe_name(pipe));
ea0760cf
JB		 1087}
1088
93ce0ba6
JN		 1089static void assert_cursor(struct drm_i915_private *dev_priv,
1090 enum pipe pipe, bool state)
1091{
1092 struct drm_device *dev = dev_priv->dev;
1093 bool cur_state;
1094
1095 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1096 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1097 else if (IS_845G(dev) || IS_I865G(dev))
1098 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1099 else
1100 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1101
1102 WARN(cur_state != state,
1103 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1104 pipe_name(pipe), state_string(state), state_string(cur_state));
1105}
1106#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1107#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1108
b840d907
JB		 1109void assert_pipe(struct drm_i915_private *dev_priv,
1110 enum pipe pipe, bool state)
b24e7179
JB		 1111{
1112 int reg;
1113 u32 val;
63d7bbe9 1114 bool cur_state;
702e7a56
PZ		 1115 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1116 pipe);
b24e7179 1117
8e636784
DV		 1118 /* if we need the pipe A quirk it must be always on */
1119 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1120 state = true;
1121
b97186f0
PZ		 1122 if (!intel_display_power_enabled(dev_priv->dev,
1123 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1124 cur_state = false;
1125 } else {
1126 reg = PIPECONF(cpu_transcoder);
1127 val = I915_READ(reg);
1128 cur_state = !!(val & PIPECONF_ENABLE);
1129 }
1130
63d7bbe9
JB		 1131 WARN(cur_state != state,
1132 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1133 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1134}
1135
931872fc
CW		 1136static void assert_plane(struct drm_i915_private *dev_priv,
1137 enum plane plane, bool state)
b24e7179
JB		 1138{
1139 int reg;
1140 u32 val;
931872fc 1141 bool cur_state;
b24e7179
JB		 1142
1143 reg = DSPCNTR(plane);
1144 val = I915_READ(reg);
931872fc
CW		 1145 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1146 WARN(cur_state != state,
1147 "plane %c assertion failure (expected %s, current %s)\n",
1148 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1149}
1150
931872fc
CW		 1151#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1152#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1153
b24e7179
JB		 1154static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1155 enum pipe pipe)
1156{
653e1026 1157 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1158 int reg, i;
1159 u32 val;
1160 int cur_pipe;
1161
653e1026
VS		 1162 /* Primary planes are fixed to pipes on gen4+ */
1163 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1164 reg = DSPCNTR(pipe);
1165 val = I915_READ(reg);
1166 WARN((val & DISPLAY_PLANE_ENABLE),
1167 "plane %c assertion failure, should be disabled but not\n",
1168 plane_name(pipe));
19ec1358 1169 return;
28c05794 1170 }
19ec1358 1171
b24e7179 1172 /* Need to check both planes against the pipe */
08e2a7de 1173 for_each_pipe(i) {
b24e7179
JB		 1174 reg = DSPCNTR(i);
1175 val = I915_READ(reg);
1176 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1177 DISPPLANE_SEL_PIPE_SHIFT;
1178 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1179 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1180 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1181 }
1182}
1183
19332d7a
JB		 1184static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1185 enum pipe pipe)
1186{
20674eef 1187 struct drm_device *dev = dev_priv->dev;
19332d7a
JB		 1188 int reg, i;
1189 u32 val;
1190
20674eef
VS		 1191 if (IS_VALLEYVIEW(dev)) {
1192 for (i = 0; i < dev_priv->num_plane; i++) {
1193 reg = SPCNTR(pipe, i);
1194 val = I915_READ(reg);
1195 WARN((val & SP_ENABLE),
1196 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1197 sprite_name(pipe, i), pipe_name(pipe));
1198 }
1199 } else if (INTEL_INFO(dev)->gen >= 7) {
1200 reg = SPRCTL(pipe);
19332d7a 1201 val = I915_READ(reg);
20674eef 1202 WARN((val & SPRITE_ENABLE),
06da8da2 1203 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1204 plane_name(pipe), pipe_name(pipe));
1205 } else if (INTEL_INFO(dev)->gen >= 5) {
1206 reg = DVSCNTR(pipe);
19332d7a 1207 val = I915_READ(reg);
20674eef 1208 WARN((val & DVS_ENABLE),
06da8da2 1209 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1210 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1211 }
1212}
1213
92f2584a
JB		 1214static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1215{
1216 u32 val;
1217 bool enabled;
1218
9d82aa17
ED		 1219 if (HAS_PCH_LPT(dev_priv->dev)) {
1220 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1221 return;
1222 }
1223
92f2584a
JB		 1224 val = I915_READ(PCH_DREF_CONTROL);
1225 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1226 DREF_SUPERSPREAD_SOURCE_MASK));
1227 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1228}
1229
ab9412ba
DV		 1230static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1231 enum pipe pipe)
92f2584a
JB		 1232{
1233 int reg;
1234 u32 val;
1235 bool enabled;
1236
ab9412ba 1237 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1238 val = I915_READ(reg);
1239 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1240 WARN(enabled,
1241 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1242 pipe_name(pipe));
92f2584a
JB		 1243}
1244
4e634389
KP		 1245static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1246 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1247{
1248 if ((val & DP_PORT_EN) == 0)
1249 return false;
1250
1251 if (HAS_PCH_CPT(dev_priv->dev)) {
1252 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1253 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1254 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1255 return false;
1256 } else {
1257 if ((val & DP_PIPE_MASK) != (pipe << 30))
1258 return false;
1259 }
1260 return true;
1261}
1262
1519b995
KP		 1263static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1264 enum pipe pipe, u32 val)
1265{
dc0fa718 1266 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1267 return false;
1268
1269 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1270 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1271 return false;
1272 } else {
dc0fa718 1273 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1274 return false;
1275 }
1276 return true;
1277}
1278
1279static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1280 enum pipe pipe, u32 val)
1281{
1282 if ((val & LVDS_PORT_EN) == 0)
1283 return false;
1284
1285 if (HAS_PCH_CPT(dev_priv->dev)) {
1286 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1287 return false;
1288 } else {
1289 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1290 return false;
1291 }
1292 return true;
1293}
1294
1295static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1296 enum pipe pipe, u32 val)
1297{
1298 if ((val & ADPA_DAC_ENABLE) == 0)
1299 return false;
1300 if (HAS_PCH_CPT(dev_priv->dev)) {
1301 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1302 return false;
1303 } else {
1304 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1305 return false;
1306 }
1307 return true;
1308}
1309
291906f1 1310static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1311 enum pipe pipe, int reg, u32 port_sel)
291906f1 1312{
47a05eca 1313 u32 val = I915_READ(reg);
4e634389 1314 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1315 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1316 reg, pipe_name(pipe));
de9a35ab 1317
75c5da27
DV		 1318 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1319 && (val & DP_PIPEB_SELECT),
de9a35ab 1320 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1321}
1322
1323static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1324 enum pipe pipe, int reg)
1325{
47a05eca 1326 u32 val = I915_READ(reg);
b70ad586 1327 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1328 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1329 reg, pipe_name(pipe));
de9a35ab 1330
dc0fa718 1331 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1332 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1333 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1334}
1335
1336static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1337 enum pipe pipe)
1338{
1339 int reg;
1340 u32 val;
291906f1 1341
f0575e92
KP		 1342 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1343 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1344 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1345
1346 reg = PCH_ADPA;
1347 val = I915_READ(reg);
b70ad586 1348 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1349 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1350 pipe_name(pipe));
291906f1
JB		 1351
1352 reg = PCH_LVDS;
1353 val = I915_READ(reg);
b70ad586 1354 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1355 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1356 pipe_name(pipe));
291906f1 1357
e2debe91
PZ		 1358 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1359 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1360 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1361}
1362
426115cf 1363static void vlv_enable_pll(struct intel_crtc *crtc)
87442f73 1364{
426115cf
DV		 1365 struct drm_device *dev = crtc->base.dev;
1366 struct drm_i915_private *dev_priv = dev->dev_private;
1367 int reg = DPLL(crtc->pipe);
1368 u32 dpll = crtc->config.dpll_hw_state.dpll;
87442f73 1369
426115cf 1370 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1371
1372 /* No really, not for ILK+ */
1373 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1374
1375 /* PLL is protected by panel, make sure we can write it */
1376 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
426115cf 1377 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1378
426115cf
DV		 1379 I915_WRITE(reg, dpll);
1380 POSTING_READ(reg);
1381 udelay(150);
1382
1383 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1384 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1385
1386 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1387 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1388
1389 /* We do this three times for luck */
426115cf 1390 I915_WRITE(reg, dpll);
87442f73
DV		 1391 POSTING_READ(reg);
1392 udelay(150); /* wait for warmup */
426115cf 1393 I915_WRITE(reg, dpll);
87442f73
DV		 1394 POSTING_READ(reg);
1395 udelay(150); /* wait for warmup */
426115cf 1396 I915_WRITE(reg, dpll);
87442f73
DV		 1397 POSTING_READ(reg);
1398 udelay(150); /* wait for warmup */
1399}
1400
66e3d5c0 1401static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1402{
66e3d5c0
DV		 1403 struct drm_device *dev = crtc->base.dev;
1404 struct drm_i915_private *dev_priv = dev->dev_private;
1405 int reg = DPLL(crtc->pipe);
1406 u32 dpll = crtc->config.dpll_hw_state.dpll;
63d7bbe9 1407
66e3d5c0 1408 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1409
63d7bbe9 1410 /* No really, not for ILK+ */
87442f73 1411 BUG_ON(dev_priv->info->gen >= 5);
63d7bbe9
JB		 1412
1413 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1414 if (IS_MOBILE(dev) && !IS_I830(dev))
1415 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1416
66e3d5c0
DV		 1417 I915_WRITE(reg, dpll);
1418
1419 /* Wait for the clocks to stabilize. */
1420 POSTING_READ(reg);
1421 udelay(150);
1422
1423 if (INTEL_INFO(dev)->gen >= 4) {
1424 I915_WRITE(DPLL_MD(crtc->pipe),
1425 crtc->config.dpll_hw_state.dpll_md);
1426 } else {
1427 /* The pixel multiplier can only be updated once the
1428 * DPLL is enabled and the clocks are stable.
1429 *
1430 * So write it again.
1431 */
1432 I915_WRITE(reg, dpll);
1433 }
63d7bbe9
JB		 1434
1435 /* We do this three times for luck */
66e3d5c0 1436 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1437 POSTING_READ(reg);
1438 udelay(150); /* wait for warmup */
66e3d5c0 1439 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1440 POSTING_READ(reg);
1441 udelay(150); /* wait for warmup */
66e3d5c0 1442 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1443 POSTING_READ(reg);
1444 udelay(150); /* wait for warmup */
1445}
1446
1447/**
50b44a44 1448 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1449 * @dev_priv: i915 private structure
1450 * @pipe: pipe PLL to disable
1451 *
1452 * Disable the PLL for @pipe, making sure the pipe is off first.
1453 *
1454 * Note! This is for pre-ILK only.
1455 */
50b44a44 1456static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9 1457{
63d7bbe9
JB		 1458 /* Don't disable pipe A or pipe A PLLs if needed */
1459 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1460 return;
1461
1462 /* Make sure the pipe isn't still relying on us */
1463 assert_pipe_disabled(dev_priv, pipe);
1464
50b44a44
DV		 1465 I915_WRITE(DPLL(pipe), 0);
1466 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1467}
1468
f6071166
JB		 1469static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1470{
1471 u32 val = 0;
1472
1473 /* Make sure the pipe isn't still relying on us */
1474 assert_pipe_disabled(dev_priv, pipe);
1475
1476 /* Leave integrated clock source enabled */
1477 if (pipe == PIPE_B)
1478 val = DPLL_INTEGRATED_CRI_CLK_VLV;
1479 I915_WRITE(DPLL(pipe), val);
1480 POSTING_READ(DPLL(pipe));
1481}
1482
89b667f8
JB		 1483void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1484{
1485 u32 port_mask;
1486
1487 if (!port)
1488 port_mask = DPLL_PORTB_READY_MASK;
1489 else
1490 port_mask = DPLL_PORTC_READY_MASK;
1491
1492 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1493 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1494 'B' + port, I915_READ(DPLL(0)));
1495}
1496
92f2584a 1497/**
e72f9fbf 1498 * ironlake_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1499 * @dev_priv: i915 private structure
1500 * @pipe: pipe PLL to enable
1501 *
1502 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1503 * drives the transcoder clock.
1504 */
e2b78267 1505static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1506{
e2b78267
DV		 1507 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1508 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1509
48da64a8 1510 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1511 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1512 if (WARN_ON(pll == NULL))
48da64a8
CW		 1513 return;
1514
1515 if (WARN_ON(pll->refcount == 0))
1516 return;
ee7b9f93 1517
46edb027
DV		 1518 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1519 pll->name, pll->active, pll->on,
e2b78267 1520 crtc->base.base.id);
92f2584a 1521
cdbd2316
DV		 1522 if (pll->active++) {
1523 WARN_ON(!pll->on);
e9d6944e 1524 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1525 return;
1526 }
f4a091c7 1527 WARN_ON(pll->on);
ee7b9f93 1528
46edb027 1529 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1530 pll->enable(dev_priv, pll);
ee7b9f93 1531 pll->on = true;
92f2584a
JB		 1532}
1533
e2b78267 1534static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1535{
e2b78267
DV		 1536 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1537 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1538
92f2584a
JB		 1539 /* PCH only available on ILK+ */
1540 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1541 if (WARN_ON(pll == NULL))
ee7b9f93 1542 return;
92f2584a 1543
48da64a8
CW		 1544 if (WARN_ON(pll->refcount == 0))
1545 return;
7a419866 1546
46edb027
DV		 1547 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1548 pll->name, pll->active, pll->on,
e2b78267 1549 crtc->base.base.id);
7a419866 1550
48da64a8 1551 if (WARN_ON(pll->active == 0)) {
e9d6944e 1552 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1553 return;
1554 }
1555
e9d6944e 1556 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1557 WARN_ON(!pll->on);
cdbd2316 1558 if (--pll->active)
7a419866 1559 return;
ee7b9f93 1560
46edb027 1561 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1562 pll->disable(dev_priv, pll);
ee7b9f93 1563 pll->on = false;
92f2584a
JB		 1564}
1565
b8a4f404
PZ		 1566static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1567 enum pipe pipe)
040484af 1568{
23670b32 1569 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1570 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1571 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1572 uint32_t reg, val, pipeconf_val;
040484af
JB		 1573
1574 /* PCH only available on ILK+ */
1575 BUG_ON(dev_priv->info->gen < 5);
1576
1577 /* Make sure PCH DPLL is enabled */
e72f9fbf 1578 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1579 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1580
1581 /* FDI must be feeding us bits for PCH ports */
1582 assert_fdi_tx_enabled(dev_priv, pipe);
1583 assert_fdi_rx_enabled(dev_priv, pipe);
1584
23670b32
DV		 1585 if (HAS_PCH_CPT(dev)) {
1586 /* Workaround: Set the timing override bit before enabling the
1587 * pch transcoder. */
1588 reg = TRANS_CHICKEN2(pipe);
1589 val = I915_READ(reg);
1590 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1591 I915_WRITE(reg, val);
59c859d6 1592 }
23670b32 1593
ab9412ba 1594 reg = PCH_TRANSCONF(pipe);
040484af 1595 val = I915_READ(reg);
5f7f726d 1596 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1597
1598 if (HAS_PCH_IBX(dev_priv->dev)) {
1599 /*
1600 * make the BPC in transcoder be consistent with
1601 * that in pipeconf reg.
1602 */
dfd07d72
DV		 1603 val &= ~PIPECONF_BPC_MASK;
1604 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1605 }
5f7f726d
PZ		 1606
1607 val &= ~TRANS_INTERLACE_MASK;
1608 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1609 if (HAS_PCH_IBX(dev_priv->dev) &&
1610 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1611 val |= TRANS_LEGACY_INTERLACED_ILK;
1612 else
1613 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1614 else
1615 val |= TRANS_PROGRESSIVE;
1616
040484af
JB		 1617 I915_WRITE(reg, val | TRANS_ENABLE);
1618 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1619 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1620}
1621
8fb033d7 1622static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1623 enum transcoder cpu_transcoder)
040484af 1624{
8fb033d7 1625 u32 val, pipeconf_val;
8fb033d7
PZ		 1626
1627 /* PCH only available on ILK+ */
1628 BUG_ON(dev_priv->info->gen < 5);
1629
8fb033d7 1630 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1631 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1632 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1633
223a6fdf
PZ		 1634 /* Workaround: set timing override bit. */
1635 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1636 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1637 I915_WRITE(_TRANSA_CHICKEN2, val);
1638
25f3ef11 1639 val = TRANS_ENABLE;
937bb610 1640 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1641
9a76b1c6
PZ		 1642 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1643 PIPECONF_INTERLACED_ILK)
a35f2679 1644 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1645 else
1646 val |= TRANS_PROGRESSIVE;
1647
ab9412ba
DV		 1648 I915_WRITE(LPT_TRANSCONF, val);
1649 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1650 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1651}
1652
b8a4f404
PZ		 1653static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1654 enum pipe pipe)
040484af 1655{
23670b32
DV		 1656 struct drm_device *dev = dev_priv->dev;
1657 uint32_t reg, val;
040484af
JB		 1658
1659 /* FDI relies on the transcoder */
1660 assert_fdi_tx_disabled(dev_priv, pipe);
1661 assert_fdi_rx_disabled(dev_priv, pipe);
1662
291906f1
JB		 1663 /* Ports must be off as well */
1664 assert_pch_ports_disabled(dev_priv, pipe);
1665
ab9412ba 1666 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1667 val = I915_READ(reg);
1668 val &= ~TRANS_ENABLE;
1669 I915_WRITE(reg, val);
1670 /* wait for PCH transcoder off, transcoder state */
1671 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1672 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1673
1674 if (!HAS_PCH_IBX(dev)) {
1675 /* Workaround: Clear the timing override chicken bit again. */
1676 reg = TRANS_CHICKEN2(pipe);
1677 val = I915_READ(reg);
1678 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1679 I915_WRITE(reg, val);
1680 }
040484af
JB		 1681}
1682
ab4d966c 1683static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1684{
8fb033d7
PZ		 1685 u32 val;
1686
ab9412ba 1687 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1688 val &= ~TRANS_ENABLE;
ab9412ba 1689 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1690 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1691 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1692 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1693
1694 /* Workaround: clear timing override bit. */
1695 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1696 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1697 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1698}
1699
b24e7179 1700/**
309cfea8 1701 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1702 * @dev_priv: i915 private structure
1703 * @pipe: pipe to enable
040484af 1704 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1705 *
1706 * Enable @pipe, making sure that various hardware specific requirements
1707 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1708 *
1709 * @pipe should be %PIPE_A or %PIPE_B.
1710 *
1711 * Will wait until the pipe is actually running (i.e. first vblank) before
1712 * returning.
1713 */
040484af 1714static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
23538ef1 1715 bool pch_port, bool dsi)
b24e7179 1716{
702e7a56
PZ		 1717 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1718 pipe);
1a240d4d 1719 enum pipe pch_transcoder;
b24e7179
JB		 1720 int reg;
1721 u32 val;
1722
58c6eaa2 1723 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 1724 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 1725 assert_sprites_disabled(dev_priv, pipe);
1726
681e5811 1727 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1728 pch_transcoder = TRANSCODER_A;
1729 else
1730 pch_transcoder = pipe;
1731
b24e7179
JB		 1732 /*
1733 * A pipe without a PLL won't actually be able to drive bits from
1734 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1735 * need the check.
1736 */
1737 if (!HAS_PCH_SPLIT(dev_priv->dev))
23538ef1
JN		 1738 if (dsi)
1739 assert_dsi_pll_enabled(dev_priv);
1740 else
1741 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1742 else {
1743 if (pch_port) {
1744 /* if driving the PCH, we need FDI enabled */
cc391bbb 1745 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1746 assert_fdi_tx_pll_enabled(dev_priv,
1747 (enum pipe) cpu_transcoder);
040484af
JB		 1748 }
1749 /* FIXME: assert CPU port conditions for SNB+ */
1750 }
b24e7179 1751
702e7a56 1752 reg = PIPECONF(cpu_transcoder);
b24e7179 1753 val = I915_READ(reg);
00d70b15
CW		 1754 if (val & PIPECONF_ENABLE)
1755 return;
1756
1757 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1758 intel_wait_for_vblank(dev_priv->dev, pipe);
1759}
1760
1761/**
309cfea8 1762 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1763 * @dev_priv: i915 private structure
1764 * @pipe: pipe to disable
1765 *
1766 * Disable @pipe, making sure that various hardware specific requirements
1767 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1768 *
1769 * @pipe should be %PIPE_A or %PIPE_B.
1770 *
1771 * Will wait until the pipe has shut down before returning.
1772 */
1773static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1774 enum pipe pipe)
1775{
702e7a56
PZ		 1776 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1777 pipe);
b24e7179
JB		 1778 int reg;
1779 u32 val;
1780
1781 /*
1782 * Make sure planes won't keep trying to pump pixels to us,
1783 * or we might hang the display.
1784 */
1785 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 1786 assert_cursor_disabled(dev_priv, pipe);
19332d7a 1787 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1788
1789 /* Don't disable pipe A or pipe A PLLs if needed */
1790 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1791 return;
1792
702e7a56 1793 reg = PIPECONF(cpu_transcoder);
b24e7179 1794 val = I915_READ(reg);
00d70b15
CW		 1795 if ((val & PIPECONF_ENABLE) == 0)
1796 return;
1797
1798 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1799 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1800}
1801
d74362c9
KP		 1802/*
1803 * Plane regs are double buffered, going from enabled->disabled needs a
1804 * trigger in order to latch. The display address reg provides this.
1805 */
6f1d69b0 1806void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1807 enum plane plane)
1808{
14f86147
DL		 1809 if (dev_priv->info->gen >= 4)
1810 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1811 else
1812 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1813}
1814
b24e7179
JB		 1815/**
1816 * intel_enable_plane - enable a display plane on a given pipe
1817 * @dev_priv: i915 private structure
1818 * @plane: plane to enable
1819 * @pipe: pipe being fed
1820 *
1821 * Enable @plane on @pipe, making sure that @pipe is running first.
1822 */
1823static void intel_enable_plane(struct drm_i915_private *dev_priv,
1824 enum plane plane, enum pipe pipe)
1825{
1826 int reg;
1827 u32 val;
1828
1829 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1830 assert_pipe_enabled(dev_priv, pipe);
1831
1832 reg = DSPCNTR(plane);
1833 val = I915_READ(reg);
00d70b15
CW		 1834 if (val & DISPLAY_PLANE_ENABLE)
1835 return;
1836
1837 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1838 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1839 intel_wait_for_vblank(dev_priv->dev, pipe);
1840}
1841
b24e7179
JB		 1842/**
1843 * intel_disable_plane - disable a display plane
1844 * @dev_priv: i915 private structure
1845 * @plane: plane to disable
1846 * @pipe: pipe consuming the data
1847 *
1848 * Disable @plane; should be an independent operation.
1849 */
1850static void intel_disable_plane(struct drm_i915_private *dev_priv,
1851 enum plane plane, enum pipe pipe)
1852{
1853 int reg;
1854 u32 val;
1855
1856 reg = DSPCNTR(plane);
1857 val = I915_READ(reg);
00d70b15
CW		 1858 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1859 return;
1860
1861 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1862 intel_flush_display_plane(dev_priv, plane);
1863 intel_wait_for_vblank(dev_priv->dev, pipe);
1864}
1865
693db184
CW		 1866static bool need_vtd_wa(struct drm_device *dev)
1867{
1868#ifdef CONFIG_INTEL_IOMMU
1869 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1870 return true;
1871#endif
1872 return false;
1873}
1874
127bd2ac 1875int
48b956c5 1876intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1877 struct drm_i915_gem_object *obj,
919926ae 1878 struct intel_ring_buffer *pipelined)
6b95a207 1879{
ce453d81 1880 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1881 u32 alignment;
1882 int ret;
1883
05394f39 1884 switch (obj->tiling_mode) {
6b95a207 1885 case I915_TILING_NONE:
534843da
CW		 1886 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1887 alignment = 128 * 1024;
a6c45cf0 1888 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1889 alignment = 4 * 1024;
1890 else
1891 alignment = 64 * 1024;
6b95a207
KH		 1892 break;
1893 case I915_TILING_X:
1894 /* pin() will align the object as required by fence */
1895 alignment = 0;
1896 break;
1897 case I915_TILING_Y:
8bb6e959
DV		 1898 /* Despite that we check this in framebuffer_init userspace can
1899 * screw us over and change the tiling after the fact. Only
1900 * pinned buffers can't change their tiling. */
1901 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1902 return -EINVAL;
1903 default:
1904 BUG();
1905 }
1906
693db184
CW		 1907 /* Note that the w/a also requires 64 PTE of padding following the
1908 * bo. We currently fill all unused PTE with the shadow page and so
1909 * we should always have valid PTE following the scanout preventing
1910 * the VT-d warning.
1911 */
1912 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1913 alignment = 256 * 1024;
1914
ce453d81 1915 dev_priv->mm.interruptible = false;
2da3b9b9 1916 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1917 if (ret)
ce453d81 1918 goto err_interruptible;
6b95a207
KH		 1919
1920 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1921 * fence, whereas 965+ only requires a fence if using
1922 * framebuffer compression. For simplicity, we always install
1923 * a fence as the cost is not that onerous.
1924 */
06d98131 1925 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1926 if (ret)
1927 goto err_unpin;
1690e1eb 1928
9a5a53b3 1929 i915_gem_object_pin_fence(obj);
6b95a207 1930
ce453d81 1931 dev_priv->mm.interruptible = true;
6b95a207 1932 return 0;
48b956c5
CW		 1933
1934err_unpin:
cc98b413 1935 i915_gem_object_unpin_from_display_plane(obj);
ce453d81
CW		 1936err_interruptible:
1937 dev_priv->mm.interruptible = true;
48b956c5 1938 return ret;
6b95a207
KH		 1939}
1940
1690e1eb
CW		 1941void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1942{
1943 i915_gem_object_unpin_fence(obj);
cc98b413 1944 i915_gem_object_unpin_from_display_plane(obj);
1690e1eb
CW		 1945}
1946
c2c75131
DV		 1947/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1948 * is assumed to be a power-of-two. */
bc752862
CW		 1949unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1950 unsigned int tiling_mode,
1951 unsigned int cpp,
1952 unsigned int pitch)
c2c75131 1953{
bc752862
CW		 1954 if (tiling_mode != I915_TILING_NONE) {
1955 unsigned int tile_rows, tiles;
c2c75131 1956
bc752862
CW		 1957 tile_rows = *y / 8;
1958 *y %= 8;
c2c75131 1959
bc752862
CW		 1960 tiles = *x / (512/cpp);
1961 *x %= 512/cpp;
1962
1963 return tile_rows * pitch * 8 + tiles * 4096;
1964 } else {
1965 unsigned int offset;
1966
1967 offset = *y * pitch + *x * cpp;
1968 *y = 0;
1969 *x = (offset & 4095) / cpp;
1970 return offset & -4096;
1971 }
c2c75131
DV		 1972}
1973
17638cd6
JB		 1974static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1975 int x, int y)
81255565
JB		 1976{
1977 struct drm_device *dev = crtc->dev;
1978 struct drm_i915_private *dev_priv = dev->dev_private;
1979 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1980 struct intel_framebuffer *intel_fb;
05394f39 1981 struct drm_i915_gem_object *obj;
81255565 1982 int plane = intel_crtc->plane;
e506a0c6 1983 unsigned long linear_offset;
81255565 1984 u32 dspcntr;
5eddb70b 1985 u32 reg;
81255565
JB		 1986
1987 switch (plane) {
1988 case 0:
1989 case 1:
1990 break;
1991 default:
84f44ce7 1992 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 1993 return -EINVAL;
1994 }
1995
1996 intel_fb = to_intel_framebuffer(fb);
1997 obj = intel_fb->obj;
81255565 1998
5eddb70b
CW		 1999 reg = DSPCNTR(plane);
2000 dspcntr = I915_READ(reg);
81255565
JB		 2001 /* Mask out pixel format bits in case we change it */
2002 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2003 switch (fb->pixel_format) {
2004 case DRM_FORMAT_C8:
81255565
JB		 2005 dspcntr |= DISPPLANE_8BPP;
2006 break;
57779d06
VS		 2007 case DRM_FORMAT_XRGB1555:
2008 case DRM_FORMAT_ARGB1555:
2009 dspcntr |= DISPPLANE_BGRX555;
81255565 2010 break;
57779d06
VS		 2011 case DRM_FORMAT_RGB565:
2012 dspcntr |= DISPPLANE_BGRX565;
2013 break;
2014 case DRM_FORMAT_XRGB8888:
2015 case DRM_FORMAT_ARGB8888:
2016 dspcntr |= DISPPLANE_BGRX888;
2017 break;
2018 case DRM_FORMAT_XBGR8888:
2019 case DRM_FORMAT_ABGR8888:
2020 dspcntr |= DISPPLANE_RGBX888;
2021 break;
2022 case DRM_FORMAT_XRGB2101010:
2023 case DRM_FORMAT_ARGB2101010:
2024 dspcntr |= DISPPLANE_BGRX101010;
2025 break;
2026 case DRM_FORMAT_XBGR2101010:
2027 case DRM_FORMAT_ABGR2101010:
2028 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2029 break;
2030 default:
baba133a 2031 BUG();
81255565 2032 }
57779d06 2033
a6c45cf0 2034 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2035 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2036 dspcntr |= DISPPLANE_TILED;
2037 else
2038 dspcntr &= ~DISPPLANE_TILED;
2039 }
2040
de1aa629
VS		 2041 if (IS_G4X(dev))
2042 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2043
5eddb70b 2044 I915_WRITE(reg, dspcntr);
81255565 2045
e506a0c6 2046 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2047
c2c75131
DV		 2048 if (INTEL_INFO(dev)->gen >= 4) {
2049 intel_crtc->dspaddr_offset =
bc752862
CW		 2050 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2051 fb->bits_per_pixel / 8,
2052 fb->pitches[0]);
c2c75131
DV		 2053 linear_offset -= intel_crtc->dspaddr_offset;
2054 } else {
e506a0c6 2055 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2056 }
e506a0c6 2057
f343c5f6
BW		 2058 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2059 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2060 fb->pitches[0]);
01f2c773 2061 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2062 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131 2063 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2064 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2065 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2066 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2067 } else
f343c5f6 2068 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2069 POSTING_READ(reg);
81255565 2070
17638cd6
JB		 2071 return 0;
2072}
2073
2074static int ironlake_update_plane(struct drm_crtc *crtc,
2075 struct drm_framebuffer *fb, int x, int y)
2076{
2077 struct drm_device *dev = crtc->dev;
2078 struct drm_i915_private *dev_priv = dev->dev_private;
2079 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2080 struct intel_framebuffer *intel_fb;
2081 struct drm_i915_gem_object *obj;
2082 int plane = intel_crtc->plane;
e506a0c6 2083 unsigned long linear_offset;
17638cd6
JB		 2084 u32 dspcntr;
2085 u32 reg;
2086
2087 switch (plane) {
2088 case 0:
2089 case 1:
27f8227b 2090 case 2:
17638cd6
JB		 2091 break;
2092 default:
84f44ce7 2093 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2094 return -EINVAL;
2095 }
2096
2097 intel_fb = to_intel_framebuffer(fb);
2098 obj = intel_fb->obj;
2099
2100 reg = DSPCNTR(plane);
2101 dspcntr = I915_READ(reg);
2102 /* Mask out pixel format bits in case we change it */
2103 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2104 switch (fb->pixel_format) {
2105 case DRM_FORMAT_C8:
17638cd6
JB		 2106 dspcntr |= DISPPLANE_8BPP;
2107 break;
57779d06
VS		 2108 case DRM_FORMAT_RGB565:
2109 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2110 break;
57779d06
VS		 2111 case DRM_FORMAT_XRGB8888:
2112 case DRM_FORMAT_ARGB8888:
2113 dspcntr |= DISPPLANE_BGRX888;
2114 break;
2115 case DRM_FORMAT_XBGR8888:
2116 case DRM_FORMAT_ABGR8888:
2117 dspcntr |= DISPPLANE_RGBX888;
2118 break;
2119 case DRM_FORMAT_XRGB2101010:
2120 case DRM_FORMAT_ARGB2101010:
2121 dspcntr |= DISPPLANE_BGRX101010;
2122 break;
2123 case DRM_FORMAT_XBGR2101010:
2124 case DRM_FORMAT_ABGR2101010:
2125 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2126 break;
2127 default:
baba133a 2128 BUG();
17638cd6
JB		 2129 }
2130
2131 if (obj->tiling_mode != I915_TILING_NONE)
2132 dspcntr |= DISPPLANE_TILED;
2133 else
2134 dspcntr &= ~DISPPLANE_TILED;
2135
1f5d76db
PZ		 2136 if (IS_HASWELL(dev))
2137 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2138 else
2139 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6
JB		 2140
2141 I915_WRITE(reg, dspcntr);
2142
e506a0c6 2143 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2144 intel_crtc->dspaddr_offset =
bc752862
CW		 2145 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2146 fb->bits_per_pixel / 8,
2147 fb->pitches[0]);
c2c75131 2148 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2149
f343c5f6
BW		 2150 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2151 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2152 fb->pitches[0]);
01f2c773 2153 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131 2154 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2155 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2156 if (IS_HASWELL(dev)) {
2157 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2158 } else {
2159 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2160 I915_WRITE(DSPLINOFF(plane), linear_offset);
2161 }
17638cd6
JB		 2162 POSTING_READ(reg);
2163
2164 return 0;
2165}
2166
2167/* Assume fb object is pinned & idle & fenced and just update base pointers */
2168static int
2169intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2170 int x, int y, enum mode_set_atomic state)
2171{
2172 struct drm_device *dev = crtc->dev;
2173 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2174
6b8e6ed0
CW		 2175 if (dev_priv->display.disable_fbc)
2176 dev_priv->display.disable_fbc(dev);
3dec0095 2177 intel_increase_pllclock(crtc);
81255565 2178
6b8e6ed0 2179 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2180}
2181
96a02917
VS		 2182void intel_display_handle_reset(struct drm_device *dev)
2183{
2184 struct drm_i915_private *dev_priv = dev->dev_private;
2185 struct drm_crtc *crtc;
2186
2187 /*
2188 * Flips in the rings have been nuked by the reset,
2189 * so complete all pending flips so that user space
2190 * will get its events and not get stuck.
2191 *
2192 * Also update the base address of all primary
2193 * planes to the the last fb to make sure we're
2194 * showing the correct fb after a reset.
2195 *
2196 * Need to make two loops over the crtcs so that we
2197 * don't try to grab a crtc mutex before the
2198 * pending_flip_queue really got woken up.
2199 */
2200
2201 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2202 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2203 enum plane plane = intel_crtc->plane;
2204
2205 intel_prepare_page_flip(dev, plane);
2206 intel_finish_page_flip_plane(dev, plane);
2207 }
2208
2209 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2210 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2211
2212 mutex_lock(&crtc->mutex);
2213 if (intel_crtc->active)
2214 dev_priv->display.update_plane(crtc, crtc->fb,
2215 crtc->x, crtc->y);
2216 mutex_unlock(&crtc->mutex);
2217 }
2218}
2219
14667a4b
CW		 2220static int
2221intel_finish_fb(struct drm_framebuffer *old_fb)
2222{
2223 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2224 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2225 bool was_interruptible = dev_priv->mm.interruptible;
2226 int ret;
2227
14667a4b
CW		 2228 /* Big Hammer, we also need to ensure that any pending
2229 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2230 * current scanout is retired before unpinning the old
2231 * framebuffer.
2232 *
2233 * This should only fail upon a hung GPU, in which case we
2234 * can safely continue.
2235 */
2236 dev_priv->mm.interruptible = false;
2237 ret = i915_gem_object_finish_gpu(obj);
2238 dev_priv->mm.interruptible = was_interruptible;
2239
2240 return ret;
2241}
2242
198598d0
VS		 2243static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2244{
2245 struct drm_device *dev = crtc->dev;
2246 struct drm_i915_master_private *master_priv;
2247 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2248
2249 if (!dev->primary->master)
2250 return;
2251
2252 master_priv = dev->primary->master->driver_priv;
2253 if (!master_priv->sarea_priv)
2254 return;
2255
2256 switch (intel_crtc->pipe) {
2257 case 0:
2258 master_priv->sarea_priv->pipeA_x = x;
2259 master_priv->sarea_priv->pipeA_y = y;
2260 break;
2261 case 1:
2262 master_priv->sarea_priv->pipeB_x = x;
2263 master_priv->sarea_priv->pipeB_y = y;
2264 break;
2265 default:
2266 break;
2267 }
2268}
2269
5c3b82e2 2270static int
3c4fdcfb 2271intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2272 struct drm_framebuffer *fb)
79e53945
JB		 2273{
2274 struct drm_device *dev = crtc->dev;
6b8e6ed0 2275 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2276 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2277 struct drm_framebuffer *old_fb;
5c3b82e2 2278 int ret;
79e53945
JB		 2279
2280 /* no fb bound */
94352cf9 2281 if (!fb) {
a5071c2f 2282 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2283 return 0;
2284 }
2285
7eb552ae 2286 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2287 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2288 plane_name(intel_crtc->plane),
2289 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2290 return -EINVAL;
79e53945
JB		 2291 }
2292
5c3b82e2 2293 mutex_lock(&dev->struct_mutex);
265db958 2294 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2295 to_intel_framebuffer(fb)->obj,
919926ae 2296 NULL);
5c3b82e2
CW		 2297 if (ret != 0) {
2298 mutex_unlock(&dev->struct_mutex);
a5071c2f 2299 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2300 return ret;
2301 }
79e53945 2302
4d6a3e63
JB		 2303 /* Update pipe size and adjust fitter if needed */
2304 if (i915_fastboot) {
2305 I915_WRITE(PIPESRC(intel_crtc->pipe),
2306 ((crtc->mode.hdisplay - 1) << 16) |
2307 (crtc->mode.vdisplay - 1));
fd4daa9c 2308 if (!intel_crtc->config.pch_pfit.enabled &&
4d6a3e63
JB		 2309 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2310 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2311 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2312 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2313 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2314 }
2315 }
2316
94352cf9 2317 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2318 if (ret) {
94352cf9 2319 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2320 mutex_unlock(&dev->struct_mutex);
a5071c2f 2321 DRM_ERROR("failed to update base address\n");
4e6cfefc 2322 return ret;
79e53945 2323 }
3c4fdcfb 2324
94352cf9
DV		 2325 old_fb = crtc->fb;
2326 crtc->fb = fb;
6c4c86f5
DV		 2327 crtc->x = x;
2328 crtc->y = y;
94352cf9 2329
b7f1de28 2330 if (old_fb) {
d7697eea
DV		 2331 if (intel_crtc->active && old_fb != fb)
2332 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2333 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2334 }
652c393a 2335
6b8e6ed0 2336 intel_update_fbc(dev);
4906557e 2337 intel_edp_psr_update(dev);
5c3b82e2 2338 mutex_unlock(&dev->struct_mutex);
79e53945 2339
198598d0 2340 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2341
2342 return 0;
79e53945
JB		 2343}
2344
5e84e1a4
ZW		 2345static void intel_fdi_normal_train(struct drm_crtc *crtc)
2346{
2347 struct drm_device *dev = crtc->dev;
2348 struct drm_i915_private *dev_priv = dev->dev_private;
2349 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2350 int pipe = intel_crtc->pipe;
2351 u32 reg, temp;
2352
2353 /* enable normal train */
2354 reg = FDI_TX_CTL(pipe);
2355 temp = I915_READ(reg);
61e499bf 2356 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2357 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2358 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2359 } else {
2360 temp &= ~FDI_LINK_TRAIN_NONE;
2361 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2362 }
5e84e1a4
ZW		 2363 I915_WRITE(reg, temp);
2364
2365 reg = FDI_RX_CTL(pipe);
2366 temp = I915_READ(reg);
2367 if (HAS_PCH_CPT(dev)) {
2368 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2369 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2370 } else {
2371 temp &= ~FDI_LINK_TRAIN_NONE;
2372 temp |= FDI_LINK_TRAIN_NONE;
2373 }
2374 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2375
2376 /* wait one idle pattern time */
2377 POSTING_READ(reg);
2378 udelay(1000);
357555c0
JB		 2379
2380 /* IVB wants error correction enabled */
2381 if (IS_IVYBRIDGE(dev))
2382 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2383 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2384}
2385
1e833f40
DV		 2386static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2387{
2388 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2389}
2390
01a415fd
DV		 2391static void ivb_modeset_global_resources(struct drm_device *dev)
2392{
2393 struct drm_i915_private *dev_priv = dev->dev_private;
2394 struct intel_crtc *pipe_B_crtc =
2395 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2396 struct intel_crtc *pipe_C_crtc =
2397 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2398 uint32_t temp;
2399
1e833f40
DV		 2400 /*
2401 * When everything is off disable fdi C so that we could enable fdi B
2402 * with all lanes. Note that we don't care about enabled pipes without
2403 * an enabled pch encoder.
2404 */
2405 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2406 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2407 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2408 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2409
2410 temp = I915_READ(SOUTH_CHICKEN1);
2411 temp &= ~FDI_BC_BIFURCATION_SELECT;
2412 DRM_DEBUG_KMS("disabling fdi C rx\n");
2413 I915_WRITE(SOUTH_CHICKEN1, temp);
2414 }
2415}
2416
8db9d77b
ZW		 2417/* The FDI link training functions for ILK/Ibexpeak. */
2418static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2419{
2420 struct drm_device *dev = crtc->dev;
2421 struct drm_i915_private *dev_priv = dev->dev_private;
2422 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2423 int pipe = intel_crtc->pipe;
0fc932b8 2424 int plane = intel_crtc->plane;
5eddb70b 2425 u32 reg, temp, tries;
8db9d77b 2426
0fc932b8
JB		 2427 /* FDI needs bits from pipe & plane first */
2428 assert_pipe_enabled(dev_priv, pipe);
2429 assert_plane_enabled(dev_priv, plane);
2430
e1a44743
AJ		 2431 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2432 for train result */
5eddb70b
CW		 2433 reg = FDI_RX_IMR(pipe);
2434 temp = I915_READ(reg);
e1a44743
AJ		 2435 temp &= ~FDI_RX_SYMBOL_LOCK;
2436 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2437 I915_WRITE(reg, temp);
2438 I915_READ(reg);
e1a44743
AJ		 2439 udelay(150);
2440
8db9d77b 2441 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2442 reg = FDI_TX_CTL(pipe);
2443 temp = I915_READ(reg);
627eb5a3
DV		 2444 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2445 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2446 temp &= ~FDI_LINK_TRAIN_NONE;
2447 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2448 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2449
5eddb70b
CW		 2450 reg = FDI_RX_CTL(pipe);
2451 temp = I915_READ(reg);
8db9d77b
ZW		 2452 temp &= ~FDI_LINK_TRAIN_NONE;
2453 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2454 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2455
2456 POSTING_READ(reg);
8db9d77b
ZW		 2457 udelay(150);
2458
5b2adf89 2459 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2460 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2461 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2462 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2463
5eddb70b 2464 reg = FDI_RX_IIR(pipe);
e1a44743 2465 for (tries = 0; tries < 5; tries++) {
5eddb70b 2466 temp = I915_READ(reg);
8db9d77b
ZW		 2467 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2468
2469 if ((temp & FDI_RX_BIT_LOCK)) {
2470 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2471 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2472 break;
2473 }
8db9d77b 2474 }
e1a44743 2475 if (tries == 5)
5eddb70b 2476 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2477
2478 /* Train 2 */
5eddb70b
CW		 2479 reg = FDI_TX_CTL(pipe);
2480 temp = I915_READ(reg);
8db9d77b
ZW		 2481 temp &= ~FDI_LINK_TRAIN_NONE;
2482 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2483 I915_WRITE(reg, temp);
8db9d77b 2484
5eddb70b
CW		 2485 reg = FDI_RX_CTL(pipe);
2486 temp = I915_READ(reg);
8db9d77b
ZW		 2487 temp &= ~FDI_LINK_TRAIN_NONE;
2488 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2489 I915_WRITE(reg, temp);
8db9d77b 2490
5eddb70b
CW		 2491 POSTING_READ(reg);
2492 udelay(150);
8db9d77b 2493
5eddb70b 2494 reg = FDI_RX_IIR(pipe);
e1a44743 2495 for (tries = 0; tries < 5; tries++) {
5eddb70b 2496 temp = I915_READ(reg);
8db9d77b
ZW		 2497 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2498
2499 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2500 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2501 DRM_DEBUG_KMS("FDI train 2 done.\n");
2502 break;
2503 }
8db9d77b 2504 }
e1a44743 2505 if (tries == 5)
5eddb70b 2506 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2507
2508 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2509
8db9d77b
ZW		 2510}
2511
0206e353 2512static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2513 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2514 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2515 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2516 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2517};
2518
2519/* The FDI link training functions for SNB/Cougarpoint. */
2520static void gen6_fdi_link_train(struct drm_crtc *crtc)
2521{
2522 struct drm_device *dev = crtc->dev;
2523 struct drm_i915_private *dev_priv = dev->dev_private;
2524 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2525 int pipe = intel_crtc->pipe;
fa37d39e 2526 u32 reg, temp, i, retry;
8db9d77b 2527
e1a44743
AJ		 2528 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2529 for train result */
5eddb70b
CW		 2530 reg = FDI_RX_IMR(pipe);
2531 temp = I915_READ(reg);
e1a44743
AJ		 2532 temp &= ~FDI_RX_SYMBOL_LOCK;
2533 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2534 I915_WRITE(reg, temp);
2535
2536 POSTING_READ(reg);
e1a44743
AJ		 2537 udelay(150);
2538
8db9d77b 2539 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2540 reg = FDI_TX_CTL(pipe);
2541 temp = I915_READ(reg);
627eb5a3
DV		 2542 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2543 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2544 temp &= ~FDI_LINK_TRAIN_NONE;
2545 temp |= FDI_LINK_TRAIN_PATTERN_1;
2546 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2547 /* SNB-B */
2548 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2549 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2550
d74cf324
DV		 2551 I915_WRITE(FDI_RX_MISC(pipe),
2552 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2553
5eddb70b
CW		 2554 reg = FDI_RX_CTL(pipe);
2555 temp = I915_READ(reg);
8db9d77b
ZW		 2556 if (HAS_PCH_CPT(dev)) {
2557 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2558 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2559 } else {
2560 temp &= ~FDI_LINK_TRAIN_NONE;
2561 temp |= FDI_LINK_TRAIN_PATTERN_1;
2562 }
5eddb70b
CW		 2563 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2564
2565 POSTING_READ(reg);
8db9d77b
ZW		 2566 udelay(150);
2567
0206e353 2568 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2569 reg = FDI_TX_CTL(pipe);
2570 temp = I915_READ(reg);
8db9d77b
ZW		 2571 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2572 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2573 I915_WRITE(reg, temp);
2574
2575 POSTING_READ(reg);
8db9d77b
ZW		 2576 udelay(500);
2577
fa37d39e
SP		 2578 for (retry = 0; retry < 5; retry++) {
2579 reg = FDI_RX_IIR(pipe);
2580 temp = I915_READ(reg);
2581 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2582 if (temp & FDI_RX_BIT_LOCK) {
2583 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2584 DRM_DEBUG_KMS("FDI train 1 done.\n");
2585 break;
2586 }
2587 udelay(50);
8db9d77b 2588 }
fa37d39e
SP		 2589 if (retry < 5)
2590 break;
8db9d77b
ZW		 2591 }
2592 if (i == 4)
5eddb70b 2593 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2594
2595 /* Train 2 */
5eddb70b
CW		 2596 reg = FDI_TX_CTL(pipe);
2597 temp = I915_READ(reg);
8db9d77b
ZW		 2598 temp &= ~FDI_LINK_TRAIN_NONE;
2599 temp |= FDI_LINK_TRAIN_PATTERN_2;
2600 if (IS_GEN6(dev)) {
2601 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2602 /* SNB-B */
2603 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2604 }
5eddb70b 2605 I915_WRITE(reg, temp);
8db9d77b 2606
5eddb70b
CW		 2607 reg = FDI_RX_CTL(pipe);
2608 temp = I915_READ(reg);
8db9d77b
ZW		 2609 if (HAS_PCH_CPT(dev)) {
2610 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2611 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2612 } else {
2613 temp &= ~FDI_LINK_TRAIN_NONE;
2614 temp |= FDI_LINK_TRAIN_PATTERN_2;
2615 }
5eddb70b
CW		 2616 I915_WRITE(reg, temp);
2617
2618 POSTING_READ(reg);
8db9d77b
ZW		 2619 udelay(150);
2620
0206e353 2621 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2622 reg = FDI_TX_CTL(pipe);
2623 temp = I915_READ(reg);
8db9d77b
ZW		 2624 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2625 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2626 I915_WRITE(reg, temp);
2627
2628 POSTING_READ(reg);
8db9d77b
ZW		 2629 udelay(500);
2630
fa37d39e
SP		 2631 for (retry = 0; retry < 5; retry++) {
2632 reg = FDI_RX_IIR(pipe);
2633 temp = I915_READ(reg);
2634 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2635 if (temp & FDI_RX_SYMBOL_LOCK) {
2636 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2637 DRM_DEBUG_KMS("FDI train 2 done.\n");
2638 break;
2639 }
2640 udelay(50);
8db9d77b 2641 }
fa37d39e
SP		 2642 if (retry < 5)
2643 break;
8db9d77b
ZW		 2644 }
2645 if (i == 4)
5eddb70b 2646 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2647
2648 DRM_DEBUG_KMS("FDI train done.\n");
2649}
2650
357555c0
JB		 2651/* Manual link training for Ivy Bridge A0 parts */
2652static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2653{
2654 struct drm_device *dev = crtc->dev;
2655 struct drm_i915_private *dev_priv = dev->dev_private;
2656 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2657 int pipe = intel_crtc->pipe;
139ccd3f 2658 u32 reg, temp, i, j;
357555c0
JB		 2659
2660 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2661 for train result */
2662 reg = FDI_RX_IMR(pipe);
2663 temp = I915_READ(reg);
2664 temp &= ~FDI_RX_SYMBOL_LOCK;
2665 temp &= ~FDI_RX_BIT_LOCK;
2666 I915_WRITE(reg, temp);
2667
2668 POSTING_READ(reg);
2669 udelay(150);
2670
01a415fd
DV		 2671 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2672 I915_READ(FDI_RX_IIR(pipe)));
2673
139ccd3f
JB		 2674 /* Try each vswing and preemphasis setting twice before moving on */
2675 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2676 /* disable first in case we need to retry */
2677 reg = FDI_TX_CTL(pipe);
2678 temp = I915_READ(reg);
2679 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2680 temp &= ~FDI_TX_ENABLE;
2681 I915_WRITE(reg, temp);
357555c0 2682
139ccd3f
JB		 2683 reg = FDI_RX_CTL(pipe);
2684 temp = I915_READ(reg);
2685 temp &= ~FDI_LINK_TRAIN_AUTO;
2686 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2687 temp &= ~FDI_RX_ENABLE;
2688 I915_WRITE(reg, temp);
357555c0 2689
139ccd3f 2690 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 2691 reg = FDI_TX_CTL(pipe);
2692 temp = I915_READ(reg);
139ccd3f
JB		 2693 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2694 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2695 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 2696 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 2697 temp |= snb_b_fdi_train_param[j/2];
2698 temp |= FDI_COMPOSITE_SYNC;
2699 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 2700
139ccd3f
JB		 2701 I915_WRITE(FDI_RX_MISC(pipe),
2702 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 2703
139ccd3f 2704 reg = FDI_RX_CTL(pipe);
357555c0 2705 temp = I915_READ(reg);
139ccd3f
JB		 2706 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2707 temp |= FDI_COMPOSITE_SYNC;
2708 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 2709
139ccd3f
JB		 2710 POSTING_READ(reg);
2711 udelay(1); /* should be 0.5us */
357555c0 2712
139ccd3f
JB		 2713 for (i = 0; i < 4; i++) {
2714 reg = FDI_RX_IIR(pipe);
2715 temp = I915_READ(reg);
2716 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2717
139ccd3f
JB		 2718 if (temp & FDI_RX_BIT_LOCK ||
2719 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2720 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2721 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2722 i);
2723 break;
2724 }
2725 udelay(1); /* should be 0.5us */
2726 }
2727 if (i == 4) {
2728 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2729 continue;
2730 }
357555c0 2731
139ccd3f 2732 /* Train 2 */
357555c0
JB		 2733 reg = FDI_TX_CTL(pipe);
2734 temp = I915_READ(reg);
139ccd3f
JB		 2735 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2736 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2737 I915_WRITE(reg, temp);
2738
2739 reg = FDI_RX_CTL(pipe);
2740 temp = I915_READ(reg);
2741 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2742 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 2743 I915_WRITE(reg, temp);
2744
2745 POSTING_READ(reg);
139ccd3f 2746 udelay(2); /* should be 1.5us */
357555c0 2747
139ccd3f
JB		 2748 for (i = 0; i < 4; i++) {
2749 reg = FDI_RX_IIR(pipe);
2750 temp = I915_READ(reg);
2751 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2752
139ccd3f
JB		 2753 if (temp & FDI_RX_SYMBOL_LOCK ||
2754 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2755 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2756 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2757 i);
2758 goto train_done;
2759 }
2760 udelay(2); /* should be 1.5us */
357555c0 2761 }
139ccd3f
JB		 2762 if (i == 4)
2763 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 2764 }
357555c0 2765
139ccd3f 2766train_done:
357555c0
JB		 2767 DRM_DEBUG_KMS("FDI train done.\n");
2768}
2769
88cefb6c 2770static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2771{
88cefb6c 2772 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2773 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2774 int pipe = intel_crtc->pipe;
5eddb70b 2775 u32 reg, temp;
79e53945 2776
c64e311e 2777
c98e9dcf 2778 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2779 reg = FDI_RX_CTL(pipe);
2780 temp = I915_READ(reg);
627eb5a3
DV		 2781 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2782 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2783 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2784 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2785
2786 POSTING_READ(reg);
c98e9dcf
JB		 2787 udelay(200);
2788
2789 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2790 temp = I915_READ(reg);
2791 I915_WRITE(reg, temp | FDI_PCDCLK);
2792
2793 POSTING_READ(reg);
c98e9dcf
JB		 2794 udelay(200);
2795
20749730
PZ		 2796 /* Enable CPU FDI TX PLL, always on for Ironlake */
2797 reg = FDI_TX_CTL(pipe);
2798 temp = I915_READ(reg);
2799 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2800 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2801
20749730
PZ		 2802 POSTING_READ(reg);
2803 udelay(100);
6be4a607 2804 }
0e23b99d
JB		 2805}
2806
88cefb6c
DV		 2807static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2808{
2809 struct drm_device *dev = intel_crtc->base.dev;
2810 struct drm_i915_private *dev_priv = dev->dev_private;
2811 int pipe = intel_crtc->pipe;
2812 u32 reg, temp;
2813
2814 /* Switch from PCDclk to Rawclk */
2815 reg = FDI_RX_CTL(pipe);
2816 temp = I915_READ(reg);
2817 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2818
2819 /* Disable CPU FDI TX PLL */
2820 reg = FDI_TX_CTL(pipe);
2821 temp = I915_READ(reg);
2822 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2823
2824 POSTING_READ(reg);
2825 udelay(100);
2826
2827 reg = FDI_RX_CTL(pipe);
2828 temp = I915_READ(reg);
2829 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2830
2831 /* Wait for the clocks to turn off. */
2832 POSTING_READ(reg);
2833 udelay(100);
2834}
2835
0fc932b8
JB		 2836static void ironlake_fdi_disable(struct drm_crtc *crtc)
2837{
2838 struct drm_device *dev = crtc->dev;
2839 struct drm_i915_private *dev_priv = dev->dev_private;
2840 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2841 int pipe = intel_crtc->pipe;
2842 u32 reg, temp;
2843
2844 /* disable CPU FDI tx and PCH FDI rx */
2845 reg = FDI_TX_CTL(pipe);
2846 temp = I915_READ(reg);
2847 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2848 POSTING_READ(reg);
2849
2850 reg = FDI_RX_CTL(pipe);
2851 temp = I915_READ(reg);
2852 temp &= ~(0x7 << 16);
dfd07d72 2853 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2854 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2855
2856 POSTING_READ(reg);
2857 udelay(100);
2858
2859 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2860 if (HAS_PCH_IBX(dev)) {
2861 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2862 }
0fc932b8
JB		 2863
2864 /* still set train pattern 1 */
2865 reg = FDI_TX_CTL(pipe);
2866 temp = I915_READ(reg);
2867 temp &= ~FDI_LINK_TRAIN_NONE;
2868 temp |= FDI_LINK_TRAIN_PATTERN_1;
2869 I915_WRITE(reg, temp);
2870
2871 reg = FDI_RX_CTL(pipe);
2872 temp = I915_READ(reg);
2873 if (HAS_PCH_CPT(dev)) {
2874 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2875 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2876 } else {
2877 temp &= ~FDI_LINK_TRAIN_NONE;
2878 temp |= FDI_LINK_TRAIN_PATTERN_1;
2879 }
2880 /* BPC in FDI rx is consistent with that in PIPECONF */
2881 temp &= ~(0x07 << 16);
dfd07d72 2882 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2883 I915_WRITE(reg, temp);
2884
2885 POSTING_READ(reg);
2886 udelay(100);
2887}
2888
5bb61643
CW		 2889static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2890{
2891 struct drm_device *dev = crtc->dev;
2892 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2893 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2894 unsigned long flags;
2895 bool pending;
2896
10d83730
VS		 2897 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2898 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2899 return false;
2900
2901 spin_lock_irqsave(&dev->event_lock, flags);
2902 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2903 spin_unlock_irqrestore(&dev->event_lock, flags);
2904
2905 return pending;
2906}
2907
e6c3a2a6
CW		 2908static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2909{
0f91128d 2910 struct drm_device *dev = crtc->dev;
5bb61643 2911 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2912
2913 if (crtc->fb == NULL)
2914 return;
2915
2c10d571
DV		 2916 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2917
5bb61643
CW		 2918 wait_event(dev_priv->pending_flip_queue,
2919 !intel_crtc_has_pending_flip(crtc));
2920
0f91128d
CW		 2921 mutex_lock(&dev->struct_mutex);
2922 intel_finish_fb(crtc->fb);
2923 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2924}
2925
e615efe4
ED		 2926/* Program iCLKIP clock to the desired frequency */
2927static void lpt_program_iclkip(struct drm_crtc *crtc)
2928{
2929 struct drm_device *dev = crtc->dev;
2930 struct drm_i915_private *dev_priv = dev->dev_private;
241bfc38 2931 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
e615efe4
ED		 2932 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2933 u32 temp;
2934
09153000
DV		 2935 mutex_lock(&dev_priv->dpio_lock);
2936
e615efe4
ED		 2937 /* It is necessary to ungate the pixclk gate prior to programming
2938 * the divisors, and gate it back when it is done.
2939 */
2940 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2941
2942 /* Disable SSCCTL */
2943 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2944 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2945 SBI_SSCCTL_DISABLE,
2946 SBI_ICLK);
e615efe4
ED		 2947
2948 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 2949 if (clock == 20000) {
e615efe4
ED		 2950 auxdiv = 1;
2951 divsel = 0x41;
2952 phaseinc = 0x20;
2953 } else {
2954 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 2955 * but the adjusted_mode->crtc_clock in in KHz. To get the
2956 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 2957 * convert the virtual clock precision to KHz here for higher
2958 * precision.
2959 */
2960 u32 iclk_virtual_root_freq = 172800 * 1000;
2961 u32 iclk_pi_range = 64;
2962 u32 desired_divisor, msb_divisor_value, pi_value;
2963
12d7ceed 2964 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 2965 msb_divisor_value = desired_divisor / iclk_pi_range;
2966 pi_value = desired_divisor % iclk_pi_range;
2967
2968 auxdiv = 0;
2969 divsel = msb_divisor_value - 2;
2970 phaseinc = pi_value;
2971 }
2972
2973 /* This should not happen with any sane values */
2974 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2975 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2976 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2977 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2978
2979 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 2980 clock,
e615efe4
ED		 2981 auxdiv,
2982 divsel,
2983 phasedir,
2984 phaseinc);
2985
2986 /* Program SSCDIVINTPHASE6 */
988d6ee8 2987 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2988 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2989 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2990 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2991 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2992 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2993 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2994 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2995
2996 /* Program SSCAUXDIV */
988d6ee8 2997 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2998 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2999 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3000 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3001
3002 /* Enable modulator and associated divider */
988d6ee8 3003 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3004 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3005 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3006
3007 /* Wait for initialization time */
3008 udelay(24);
3009
3010 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 3011
3012 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 3013}
3014
275f01b2
DV		 3015static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3016 enum pipe pch_transcoder)
3017{
3018 struct drm_device *dev = crtc->base.dev;
3019 struct drm_i915_private *dev_priv = dev->dev_private;
3020 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3021
3022 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3023 I915_READ(HTOTAL(cpu_transcoder)));
3024 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3025 I915_READ(HBLANK(cpu_transcoder)));
3026 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3027 I915_READ(HSYNC(cpu_transcoder)));
3028
3029 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3030 I915_READ(VTOTAL(cpu_transcoder)));
3031 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3032 I915_READ(VBLANK(cpu_transcoder)));
3033 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3034 I915_READ(VSYNC(cpu_transcoder)));
3035 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3036 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3037}
3038
f67a559d
JB		 3039/*
3040 * Enable PCH resources required for PCH ports:
3041 * - PCH PLLs
3042 * - FDI training & RX/TX
3043 * - update transcoder timings
3044 * - DP transcoding bits
3045 * - transcoder
3046 */
3047static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3048{
3049 struct drm_device *dev = crtc->dev;
3050 struct drm_i915_private *dev_priv = dev->dev_private;
3051 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3052 int pipe = intel_crtc->pipe;
ee7b9f93 3053 u32 reg, temp;
2c07245f 3054
ab9412ba 3055 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 3056
cd986abb
DV		 3057 /* Write the TU size bits before fdi link training, so that error
3058 * detection works. */
3059 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3060 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3061
c98e9dcf 3062 /* For PCH output, training FDI link */
674cf967 3063 dev_priv->display.fdi_link_train(crtc);
2c07245f 3064
3ad8a208
DV		 3065 /* We need to program the right clock selection before writing the pixel
3066 * mutliplier into the DPLL. */
303b81e0 3067 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3068 u32 sel;
4b645f14 3069
c98e9dcf 3070 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 3071 temp |= TRANS_DPLL_ENABLE(pipe);
3072 sel = TRANS_DPLLB_SEL(pipe);
a43f6e0f 3073 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 3074 temp |= sel;
3075 else
3076 temp &= ~sel;
c98e9dcf 3077 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3078 }
5eddb70b 3079
3ad8a208
DV		 3080 /* XXX: pch pll's can be enabled any time before we enable the PCH
3081 * transcoder, and we actually should do this to not upset any PCH
3082 * transcoder that already use the clock when we share it.
3083 *
3084 * Note that enable_shared_dpll tries to do the right thing, but
3085 * get_shared_dpll unconditionally resets the pll - we need that to have
3086 * the right LVDS enable sequence. */
3087 ironlake_enable_shared_dpll(intel_crtc);
3088
d9b6cb56
JB		 3089 /* set transcoder timing, panel must allow it */
3090 assert_panel_unlocked(dev_priv, pipe);
275f01b2 3091 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 3092
303b81e0 3093 intel_fdi_normal_train(crtc);
5e84e1a4 3094
c98e9dcf
JB		 3095 /* For PCH DP, enable TRANS_DP_CTL */
3096 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3097 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3098 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3099 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3100 reg = TRANS_DP_CTL(pipe);
3101 temp = I915_READ(reg);
3102 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3103 TRANS_DP_SYNC_MASK |
3104 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3105 temp |= (TRANS_DP_OUTPUT_ENABLE |
3106 TRANS_DP_ENH_FRAMING);
9325c9f0 3107 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3108
3109 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3110 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3111 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3112 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3113
3114 switch (intel_trans_dp_port_sel(crtc)) {
3115 case PCH_DP_B:
5eddb70b 3116 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3117 break;
3118 case PCH_DP_C:
5eddb70b 3119 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3120 break;
3121 case PCH_DP_D:
5eddb70b 3122 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3123 break;
3124 default:
e95d41e1 3125 BUG();
32f9d658 3126 }
2c07245f 3127
5eddb70b 3128 I915_WRITE(reg, temp);
6be4a607 3129 }
b52eb4dc 3130
b8a4f404 3131 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3132}
3133
1507e5bd
PZ		 3134static void lpt_pch_enable(struct drm_crtc *crtc)
3135{
3136 struct drm_device *dev = crtc->dev;
3137 struct drm_i915_private *dev_priv = dev->dev_private;
3138 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3139 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3140
ab9412ba 3141 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3142
8c52b5e8 3143 lpt_program_iclkip(crtc);
1507e5bd 3144
0540e488 3145 /* Set transcoder timing. */
275f01b2 3146 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3147
937bb610 3148 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3149}
3150
e2b78267 3151static void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3152{
e2b78267 3153 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 3154
3155 if (pll == NULL)
3156 return;
3157
3158 if (pll->refcount == 0) {
46edb027 3159 WARN(1, "bad %s refcount\n", pll->name);
ee7b9f93
JB		 3160 return;
3161 }
3162
f4a091c7
DV		 3163 if (--pll->refcount == 0) {
3164 WARN_ON(pll->on);
3165 WARN_ON(pll->active);
3166 }
3167
a43f6e0f 3168 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 3169}
3170
b89a1d39 3171static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3172{
e2b78267
DV		 3173 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3174 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3175 enum intel_dpll_id i;
ee7b9f93 3176
ee7b9f93 3177 if (pll) {
46edb027
DV		 3178 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3179 crtc->base.base.id, pll->name);
e2b78267 3180 intel_put_shared_dpll(crtc);
ee7b9f93
JB		 3181 }
3182
98b6bd99
DV		 3183 if (HAS_PCH_IBX(dev_priv->dev)) {
3184 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 3185 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 3186 pll = &dev_priv->shared_dplls[i];
98b6bd99 3187
46edb027
DV		 3188 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3189 crtc->base.base.id, pll->name);
98b6bd99
DV		 3190
3191 goto found;
3192 }
3193
e72f9fbf
DV		 3194 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3195 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 3196
3197 /* Only want to check enabled timings first */
3198 if (pll->refcount == 0)
3199 continue;
3200
b89a1d39
DV		 3201 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3202 sizeof(pll->hw_state)) == 0) {
46edb027 3203 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
e2b78267 3204 crtc->base.base.id,
46edb027 3205 pll->name, pll->refcount, pll->active);
ee7b9f93
JB		 3206
3207 goto found;
3208 }
3209 }
3210
3211 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 3212 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3213 pll = &dev_priv->shared_dplls[i];
ee7b9f93 3214 if (pll->refcount == 0) {
46edb027
DV		 3215 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3216 crtc->base.base.id, pll->name);
ee7b9f93
JB		 3217 goto found;
3218 }
3219 }
3220
3221 return NULL;
3222
3223found:
a43f6e0f 3224 crtc->config.shared_dpll = i;
46edb027
DV		 3225 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3226 pipe_name(crtc->pipe));
ee7b9f93 3227
cdbd2316 3228 if (pll->active == 0) {
66e985c0
DV		 3229 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3230 sizeof(pll->hw_state));
3231
46edb027 3232 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
cdbd2316 3233 WARN_ON(pll->on);
e9d6944e 3234 assert_shared_dpll_disabled(dev_priv, pll);
ee7b9f93 3235
15bdd4cf 3236 pll->mode_set(dev_priv, pll);
cdbd2316
DV		 3237 }
3238 pll->refcount++;
e04c7350 3239
ee7b9f93
JB		 3240 return pll;
3241}
3242
a1520318 3243static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3244{
3245 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3246 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3247 u32 temp;
3248
3249 temp = I915_READ(dslreg);
3250 udelay(500);
3251 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3252 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3253 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3254 }
3255}
3256
b074cec8
JB		 3257static void ironlake_pfit_enable(struct intel_crtc *crtc)
3258{
3259 struct drm_device *dev = crtc->base.dev;
3260 struct drm_i915_private *dev_priv = dev->dev_private;
3261 int pipe = crtc->pipe;
3262
fd4daa9c 3263 if (crtc->config.pch_pfit.enabled) {
b074cec8
JB		 3264 /* Force use of hard-coded filter coefficients
3265 * as some pre-programmed values are broken,
3266 * e.g. x201.
3267 */
3268 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3269 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3270 PF_PIPE_SEL_IVB(pipe));
3271 else
3272 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3273 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3274 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
d4270e57
JB		 3275 }
3276}
3277
bb53d4ae
VS		 3278static void intel_enable_planes(struct drm_crtc *crtc)
3279{
3280 struct drm_device *dev = crtc->dev;
3281 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3282 struct intel_plane *intel_plane;
3283
3284 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3285 if (intel_plane->pipe == pipe)
3286 intel_plane_restore(&intel_plane->base);
3287}
3288
3289static void intel_disable_planes(struct drm_crtc *crtc)
3290{
3291 struct drm_device *dev = crtc->dev;
3292 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3293 struct intel_plane *intel_plane;
3294
3295 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3296 if (intel_plane->pipe == pipe)
3297 intel_plane_disable(&intel_plane->base);
3298}
3299
d77e4531
PZ		 3300static void hsw_enable_ips(struct intel_crtc *crtc)
3301{
3302 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3303
3304 if (!crtc->config.ips_enabled)
3305 return;
3306
3307 /* We can only enable IPS after we enable a plane and wait for a vblank.
3308 * We guarantee that the plane is enabled by calling intel_enable_ips
3309 * only after intel_enable_plane. And intel_enable_plane already waits
3310 * for a vblank, so all we need to do here is to enable the IPS bit. */
3311 assert_plane_enabled(dev_priv, crtc->plane);
3312 I915_WRITE(IPS_CTL, IPS_ENABLE);
3313}
3314
3315static void hsw_disable_ips(struct intel_crtc *crtc)
3316{
3317 struct drm_device *dev = crtc->base.dev;
3318 struct drm_i915_private *dev_priv = dev->dev_private;
3319
3320 if (!crtc->config.ips_enabled)
3321 return;
3322
3323 assert_plane_enabled(dev_priv, crtc->plane);
3324 I915_WRITE(IPS_CTL, 0);
3325 POSTING_READ(IPS_CTL);
3326
3327 /* We need to wait for a vblank before we can disable the plane. */
3328 intel_wait_for_vblank(dev, crtc->pipe);
3329}
3330
3331/** Loads the palette/gamma unit for the CRTC with the prepared values */
3332static void intel_crtc_load_lut(struct drm_crtc *crtc)
3333{
3334 struct drm_device *dev = crtc->dev;
3335 struct drm_i915_private *dev_priv = dev->dev_private;
3336 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3337 enum pipe pipe = intel_crtc->pipe;
3338 int palreg = PALETTE(pipe);
3339 int i;
3340 bool reenable_ips = false;
3341
3342 /* The clocks have to be on to load the palette. */
3343 if (!crtc->enabled || !intel_crtc->active)
3344 return;
3345
3346 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3347 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3348 assert_dsi_pll_enabled(dev_priv);
3349 else
3350 assert_pll_enabled(dev_priv, pipe);
3351 }
3352
3353 /* use legacy palette for Ironlake */
3354 if (HAS_PCH_SPLIT(dev))
3355 palreg = LGC_PALETTE(pipe);
3356
3357 /* Workaround : Do not read or write the pipe palette/gamma data while
3358 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3359 */
3360 if (intel_crtc->config.ips_enabled &&
3361 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3362 GAMMA_MODE_MODE_SPLIT)) {
3363 hsw_disable_ips(intel_crtc);
3364 reenable_ips = true;
3365 }
3366
3367 for (i = 0; i < 256; i++) {
3368 I915_WRITE(palreg + 4 * i,
3369 (intel_crtc->lut_r[i] << 16) |
3370 (intel_crtc->lut_g[i] << 8) |
3371 intel_crtc->lut_b[i]);
3372 }
3373
3374 if (reenable_ips)
3375 hsw_enable_ips(intel_crtc);
3376}
3377
f67a559d
JB		 3378static void ironlake_crtc_enable(struct drm_crtc *crtc)
3379{
3380 struct drm_device *dev = crtc->dev;
3381 struct drm_i915_private *dev_priv = dev->dev_private;
3382 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3383 struct intel_encoder *encoder;
f67a559d
JB		 3384 int pipe = intel_crtc->pipe;
3385 int plane = intel_crtc->plane;
f67a559d 3386
08a48469
DV		 3387 WARN_ON(!crtc->enabled);
3388
f67a559d
JB		 3389 if (intel_crtc->active)
3390 return;
3391
3392 intel_crtc->active = true;
8664281b
PZ		 3393
3394 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3395 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3396
f6736a1a 3397 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 3398 if (encoder->pre_enable)
3399 encoder->pre_enable(encoder);
f67a559d 3400
5bfe2ac0 3401 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3402 /* Note: FDI PLL enabling _must_ be done before we enable the
3403 * cpu pipes, hence this is separate from all the other fdi/pch
3404 * enabling. */
88cefb6c 3405 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3406 } else {
3407 assert_fdi_tx_disabled(dev_priv, pipe);
3408 assert_fdi_rx_disabled(dev_priv, pipe);
3409 }
f67a559d 3410
b074cec8 3411 ironlake_pfit_enable(intel_crtc);
f67a559d 3412
9c54c0dd
JB		 3413 /*
3414 * On ILK+ LUT must be loaded before the pipe is running but with
3415 * clocks enabled
3416 */
3417 intel_crtc_load_lut(crtc);
3418
f37fcc2a 3419 intel_update_watermarks(crtc);
5bfe2ac0 3420 intel_enable_pipe(dev_priv, pipe,
23538ef1 3421 intel_crtc->config.has_pch_encoder, false);
f67a559d 3422 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3423 intel_enable_planes(crtc);
5c38d48c 3424 intel_crtc_update_cursor(crtc, true);
f67a559d 3425
5bfe2ac0 3426 if (intel_crtc->config.has_pch_encoder)
f67a559d 3427 ironlake_pch_enable(crtc);
c98e9dcf 3428
d1ebd816 3429 mutex_lock(&dev->struct_mutex);
bed4a673 3430 intel_update_fbc(dev);
d1ebd816
BW		 3431 mutex_unlock(&dev->struct_mutex);
3432
fa5c73b1
DV		 3433 for_each_encoder_on_crtc(dev, crtc, encoder)
3434 encoder->enable(encoder);
61b77ddd
DV		 3435
3436 if (HAS_PCH_CPT(dev))
a1520318 3437 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3438
3439 /*
3440 * There seems to be a race in PCH platform hw (at least on some
3441 * outputs) where an enabled pipe still completes any pageflip right
3442 * away (as if the pipe is off) instead of waiting for vblank. As soon
3443 * as the first vblank happend, everything works as expected. Hence just
3444 * wait for one vblank before returning to avoid strange things
3445 * happening.
3446 */
3447 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3448}
3449
42db64ef
PZ		 3450/* IPS only exists on ULT machines and is tied to pipe A. */
3451static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3452{
f5adf94e 3453 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 3454}
3455
dda9a66a
VS		 3456static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
3457{
3458 struct drm_device *dev = crtc->dev;
3459 struct drm_i915_private *dev_priv = dev->dev_private;
3460 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3461 int pipe = intel_crtc->pipe;
3462 int plane = intel_crtc->plane;
3463
3464 intel_enable_plane(dev_priv, plane, pipe);
3465 intel_enable_planes(crtc);
3466 intel_crtc_update_cursor(crtc, true);
3467
3468 hsw_enable_ips(intel_crtc);
3469
3470 mutex_lock(&dev->struct_mutex);
3471 intel_update_fbc(dev);
3472 mutex_unlock(&dev->struct_mutex);
3473}
3474
3475static void haswell_crtc_disable_planes(struct drm_crtc *crtc)
3476{
3477 struct drm_device *dev = crtc->dev;
3478 struct drm_i915_private *dev_priv = dev->dev_private;
3479 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3480 int pipe = intel_crtc->pipe;
3481 int plane = intel_crtc->plane;
3482
3483 intel_crtc_wait_for_pending_flips(crtc);
3484 drm_vblank_off(dev, pipe);
3485
3486 /* FBC must be disabled before disabling the plane on HSW. */
3487 if (dev_priv->fbc.plane == plane)
3488 intel_disable_fbc(dev);
3489
3490 hsw_disable_ips(intel_crtc);
3491
3492 intel_crtc_update_cursor(crtc, false);
3493 intel_disable_planes(crtc);
3494 intel_disable_plane(dev_priv, plane, pipe);
3495}
3496
e4916946
PZ		 3497/*
3498 * This implements the workaround described in the "notes" section of the mode
3499 * set sequence documentation. When going from no pipes or single pipe to
3500 * multiple pipes, and planes are enabled after the pipe, we need to wait at
3501 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3502 */
3503static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3504{
3505 struct drm_device *dev = crtc->base.dev;
3506 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3507
3508 /* We want to get the other_active_crtc only if there's only 1 other
3509 * active crtc. */
3510 list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3511 if (!crtc_it->active || crtc_it == crtc)
3512 continue;
3513
3514 if (other_active_crtc)
3515 return;
3516
3517 other_active_crtc = crtc_it;
3518 }
3519 if (!other_active_crtc)
3520 return;
3521
3522 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3523 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3524}
3525
4f771f10
PZ		 3526static void haswell_crtc_enable(struct drm_crtc *crtc)
3527{
3528 struct drm_device *dev = crtc->dev;
3529 struct drm_i915_private *dev_priv = dev->dev_private;
3530 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3531 struct intel_encoder *encoder;
3532 int pipe = intel_crtc->pipe;
4f771f10
PZ		 3533
3534 WARN_ON(!crtc->enabled);
3535
3536 if (intel_crtc->active)
3537 return;
3538
3539 intel_crtc->active = true;
8664281b
PZ		 3540
3541 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3542 if (intel_crtc->config.has_pch_encoder)
3543 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3544
5bfe2ac0 3545 if (intel_crtc->config.has_pch_encoder)
04945641 3546 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3547
3548 for_each_encoder_on_crtc(dev, crtc, encoder)
3549 if (encoder->pre_enable)
3550 encoder->pre_enable(encoder);
3551
1f544388 3552 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3553
b074cec8 3554 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3555
3556 /*
3557 * On ILK+ LUT must be loaded before the pipe is running but with
3558 * clocks enabled
3559 */
3560 intel_crtc_load_lut(crtc);
3561
1f544388 3562 intel_ddi_set_pipe_settings(crtc);
8228c251 3563 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3564
f37fcc2a 3565 intel_update_watermarks(crtc);
5bfe2ac0 3566 intel_enable_pipe(dev_priv, pipe,
23538ef1 3567 intel_crtc->config.has_pch_encoder, false);
42db64ef 3568
5bfe2ac0 3569 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3570 lpt_pch_enable(crtc);
4f771f10 3571
8807e55b 3572 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 3573 encoder->enable(encoder);
8807e55b
JN		 3574 intel_opregion_notify_encoder(encoder, true);
3575 }
4f771f10 3576
e4916946
PZ		 3577 /* If we change the relative order between pipe/planes enabling, we need
3578 * to change the workaround. */
3579 haswell_mode_set_planes_workaround(intel_crtc);
dda9a66a
VS		 3580 haswell_crtc_enable_planes(crtc);
3581
4f771f10
PZ		 3582 /*
3583 * There seems to be a race in PCH platform hw (at least on some
3584 * outputs) where an enabled pipe still completes any pageflip right
3585 * away (as if the pipe is off) instead of waiting for vblank. As soon
3586 * as the first vblank happend, everything works as expected. Hence just
3587 * wait for one vblank before returning to avoid strange things
3588 * happening.
3589 */
3590 intel_wait_for_vblank(dev, intel_crtc->pipe);
3591}
3592
3f8dce3a
DV		 3593static void ironlake_pfit_disable(struct intel_crtc *crtc)
3594{
3595 struct drm_device *dev = crtc->base.dev;
3596 struct drm_i915_private *dev_priv = dev->dev_private;
3597 int pipe = crtc->pipe;
3598
3599 /* To avoid upsetting the power well on haswell only disable the pfit if
3600 * it's in use. The hw state code will make sure we get this right. */
fd4daa9c 3601 if (crtc->config.pch_pfit.enabled) {
3f8dce3a
DV		 3602 I915_WRITE(PF_CTL(pipe), 0);
3603 I915_WRITE(PF_WIN_POS(pipe), 0);
3604 I915_WRITE(PF_WIN_SZ(pipe), 0);
3605 }
3606}
3607
6be4a607
JB		 3608static void ironlake_crtc_disable(struct drm_crtc *crtc)
3609{
3610 struct drm_device *dev = crtc->dev;
3611 struct drm_i915_private *dev_priv = dev->dev_private;
3612 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3613 struct intel_encoder *encoder;
6be4a607
JB		 3614 int pipe = intel_crtc->pipe;
3615 int plane = intel_crtc->plane;
5eddb70b 3616 u32 reg, temp;
b52eb4dc 3617
ef9c3aee 3618
f7abfe8b
CW		 3619 if (!intel_crtc->active)
3620 return;
3621
ea9d758d
DV		 3622 for_each_encoder_on_crtc(dev, crtc, encoder)
3623 encoder->disable(encoder);
3624
e6c3a2a6 3625 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3626 drm_vblank_off(dev, pipe);
913d8d11 3627
5c3fe8b0 3628 if (dev_priv->fbc.plane == plane)
973d04f9 3629 intel_disable_fbc(dev);
2c07245f 3630
0d5b8c61 3631 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3632 intel_disable_planes(crtc);
0d5b8c61
VS		 3633 intel_disable_plane(dev_priv, plane, pipe);
3634
d925c59a
DV		 3635 if (intel_crtc->config.has_pch_encoder)
3636 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3637
b24e7179 3638 intel_disable_pipe(dev_priv, pipe);
32f9d658 3639
3f8dce3a 3640 ironlake_pfit_disable(intel_crtc);
2c07245f 3641
bf49ec8c
DV		 3642 for_each_encoder_on_crtc(dev, crtc, encoder)
3643 if (encoder->post_disable)
3644 encoder->post_disable(encoder);
2c07245f 3645
d925c59a
DV		 3646 if (intel_crtc->config.has_pch_encoder) {
3647 ironlake_fdi_disable(crtc);
913d8d11 3648
d925c59a
DV		 3649 ironlake_disable_pch_transcoder(dev_priv, pipe);
3650 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
6be4a607 3651
d925c59a
DV		 3652 if (HAS_PCH_CPT(dev)) {
3653 /* disable TRANS_DP_CTL */
3654 reg = TRANS_DP_CTL(pipe);
3655 temp = I915_READ(reg);
3656 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3657 TRANS_DP_PORT_SEL_MASK);
3658 temp |= TRANS_DP_PORT_SEL_NONE;
3659 I915_WRITE(reg, temp);
3660
3661 /* disable DPLL_SEL */
3662 temp = I915_READ(PCH_DPLL_SEL);
11887397 3663 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 3664 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 3665 }
e3421a18 3666
d925c59a 3667 /* disable PCH DPLL */
e72f9fbf 3668 intel_disable_shared_dpll(intel_crtc);
8db9d77b 3669
d925c59a
DV		 3670 ironlake_fdi_pll_disable(intel_crtc);
3671 }
6b383a7f 3672
f7abfe8b 3673 intel_crtc->active = false;
46ba614c 3674 intel_update_watermarks(crtc);
d1ebd816
BW		 3675
3676 mutex_lock(&dev->struct_mutex);
6b383a7f 3677 intel_update_fbc(dev);
d1ebd816 3678 mutex_unlock(&dev->struct_mutex);
6be4a607 3679}
1b3c7a47 3680
4f771f10 3681static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3682{
4f771f10
PZ		 3683 struct drm_device *dev = crtc->dev;
3684 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3685 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3686 struct intel_encoder *encoder;
3687 int pipe = intel_crtc->pipe;
3b117c8f 3688 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3689
4f771f10
PZ		 3690 if (!intel_crtc->active)
3691 return;
3692
dda9a66a
VS		 3693 haswell_crtc_disable_planes(crtc);
3694
8807e55b
JN		 3695 for_each_encoder_on_crtc(dev, crtc, encoder) {
3696 intel_opregion_notify_encoder(encoder, false);
4f771f10 3697 encoder->disable(encoder);
8807e55b 3698 }
4f771f10 3699
8664281b
PZ		 3700 if (intel_crtc->config.has_pch_encoder)
3701 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3702 intel_disable_pipe(dev_priv, pipe);
3703
ad80a810 3704 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3705
3f8dce3a 3706 ironlake_pfit_disable(intel_crtc);
4f771f10 3707
1f544388 3708 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3709
3710 for_each_encoder_on_crtc(dev, crtc, encoder)
3711 if (encoder->post_disable)
3712 encoder->post_disable(encoder);
3713
88adfff1 3714 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3715 lpt_disable_pch_transcoder(dev_priv);
8664281b 3716 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3717 intel_ddi_fdi_disable(crtc);
83616634 3718 }
4f771f10
PZ		 3719
3720 intel_crtc->active = false;
46ba614c 3721 intel_update_watermarks(crtc);
4f771f10
PZ		 3722
3723 mutex_lock(&dev->struct_mutex);
3724 intel_update_fbc(dev);
3725 mutex_unlock(&dev->struct_mutex);
3726}
3727
ee7b9f93
JB		 3728static void ironlake_crtc_off(struct drm_crtc *crtc)
3729{
3730 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 3731 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 3732}
3733
6441ab5f
PZ		 3734static void haswell_crtc_off(struct drm_crtc *crtc)
3735{
3736 intel_ddi_put_crtc_pll(crtc);
3737}
3738
02e792fb
DV		 3739static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3740{
02e792fb 3741 if (!enable && intel_crtc->overlay) {
23f09ce3 3742 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3743 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3744
23f09ce3 3745 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3746 dev_priv->mm.interruptible = false;
3747 (void) intel_overlay_switch_off(intel_crtc->overlay);
3748 dev_priv->mm.interruptible = true;
23f09ce3 3749 mutex_unlock(&dev->struct_mutex);
02e792fb 3750 }
02e792fb 3751
5dcdbcb0
CW		 3752 /* Let userspace switch the overlay on again. In most cases userspace
3753 * has to recompute where to put it anyway.
3754 */
02e792fb
DV		 3755}
3756
61bc95c1
EE		 3757/**
3758 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3759 * cursor plane briefly if not already running after enabling the display
3760 * plane.
3761 * This workaround avoids occasional blank screens when self refresh is
3762 * enabled.
3763 */
3764static void
3765g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3766{
3767 u32 cntl = I915_READ(CURCNTR(pipe));
3768
3769 if ((cntl & CURSOR_MODE) == 0) {
3770 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3771
3772 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3773 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3774 intel_wait_for_vblank(dev_priv->dev, pipe);
3775 I915_WRITE(CURCNTR(pipe), cntl);
3776 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3777 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3778 }
3779}
3780
2dd24552
JB		 3781static void i9xx_pfit_enable(struct intel_crtc *crtc)
3782{
3783 struct drm_device *dev = crtc->base.dev;
3784 struct drm_i915_private *dev_priv = dev->dev_private;
3785 struct intel_crtc_config *pipe_config = &crtc->config;
3786
328d8e82 3787 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3788 return;
3789
2dd24552 3790 /*
c0b03411
DV		 3791 * The panel fitter should only be adjusted whilst the pipe is disabled,
3792 * according to register description and PRM.
2dd24552 3793 */
c0b03411
DV		 3794 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3795 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3796
b074cec8
JB		 3797 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3798 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3799
3800 /* Border color in case we don't scale up to the full screen. Black by
3801 * default, change to something else for debugging. */
3802 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3803}
3804
89b667f8
JB		 3805static void valleyview_crtc_enable(struct drm_crtc *crtc)
3806{
3807 struct drm_device *dev = crtc->dev;
3808 struct drm_i915_private *dev_priv = dev->dev_private;
3809 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3810 struct intel_encoder *encoder;
3811 int pipe = intel_crtc->pipe;
3812 int plane = intel_crtc->plane;
23538ef1 3813 bool is_dsi;
89b667f8
JB		 3814
3815 WARN_ON(!crtc->enabled);
3816
3817 if (intel_crtc->active)
3818 return;
3819
3820 intel_crtc->active = true;
89b667f8 3821
89b667f8
JB		 3822 for_each_encoder_on_crtc(dev, crtc, encoder)
3823 if (encoder->pre_pll_enable)
3824 encoder->pre_pll_enable(encoder);
3825
23538ef1
JN		 3826 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
3827
e9fd1c02
JN		 3828 if (!is_dsi)
3829 vlv_enable_pll(intel_crtc);
89b667f8
JB		 3830
3831 for_each_encoder_on_crtc(dev, crtc, encoder)
3832 if (encoder->pre_enable)
3833 encoder->pre_enable(encoder);
3834
2dd24552
JB		 3835 i9xx_pfit_enable(intel_crtc);
3836
63cbb074
VS		 3837 intel_crtc_load_lut(crtc);
3838
f37fcc2a 3839 intel_update_watermarks(crtc);
23538ef1 3840 intel_enable_pipe(dev_priv, pipe, false, is_dsi);
89b667f8 3841 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3842 intel_enable_planes(crtc);
5c38d48c 3843 intel_crtc_update_cursor(crtc, true);
89b667f8 3844
89b667f8 3845 intel_update_fbc(dev);
5004945f
JN		 3846
3847 for_each_encoder_on_crtc(dev, crtc, encoder)
3848 encoder->enable(encoder);
89b667f8
JB		 3849}
3850
0b8765c6 3851static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3852{
3853 struct drm_device *dev = crtc->dev;
79e53945
JB		 3854 struct drm_i915_private *dev_priv = dev->dev_private;
3855 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3856 struct intel_encoder *encoder;
79e53945 3857 int pipe = intel_crtc->pipe;
80824003 3858 int plane = intel_crtc->plane;
79e53945 3859
08a48469
DV		 3860 WARN_ON(!crtc->enabled);
3861
f7abfe8b
CW		 3862 if (intel_crtc->active)
3863 return;
3864
3865 intel_crtc->active = true;
6b383a7f 3866
9d6d9f19
MK		 3867 for_each_encoder_on_crtc(dev, crtc, encoder)
3868 if (encoder->pre_enable)
3869 encoder->pre_enable(encoder);
3870
f6736a1a
DV		 3871 i9xx_enable_pll(intel_crtc);
3872
2dd24552
JB		 3873 i9xx_pfit_enable(intel_crtc);
3874
63cbb074
VS		 3875 intel_crtc_load_lut(crtc);
3876
f37fcc2a 3877 intel_update_watermarks(crtc);
23538ef1 3878 intel_enable_pipe(dev_priv, pipe, false, false);
b24e7179 3879 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3880 intel_enable_planes(crtc);
22e407d7 3881 /* The fixup needs to happen before cursor is enabled */
61bc95c1
EE		 3882 if (IS_G4X(dev))
3883 g4x_fixup_plane(dev_priv, pipe);
22e407d7 3884 intel_crtc_update_cursor(crtc, true);
79e53945 3885
0b8765c6
JB		 3886 /* Give the overlay scaler a chance to enable if it's on this pipe */
3887 intel_crtc_dpms_overlay(intel_crtc, true);
ef9c3aee 3888
f440eb13 3889 intel_update_fbc(dev);
ef9c3aee 3890
fa5c73b1
DV		 3891 for_each_encoder_on_crtc(dev, crtc, encoder)
3892 encoder->enable(encoder);
0b8765c6 3893}
79e53945 3894
87476d63
DV		 3895static void i9xx_pfit_disable(struct intel_crtc *crtc)
3896{
3897 struct drm_device *dev = crtc->base.dev;
3898 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3899
328d8e82
DV		 3900 if (!crtc->config.gmch_pfit.control)
3901 return;
87476d63 3902
328d8e82 3903 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3904
328d8e82
DV		 3905 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3906 I915_READ(PFIT_CONTROL));
3907 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3908}
3909
0b8765c6
JB		 3910static void i9xx_crtc_disable(struct drm_crtc *crtc)
3911{
3912 struct drm_device *dev = crtc->dev;
3913 struct drm_i915_private *dev_priv = dev->dev_private;
3914 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3915 struct intel_encoder *encoder;
0b8765c6
JB		 3916 int pipe = intel_crtc->pipe;
3917 int plane = intel_crtc->plane;
ef9c3aee 3918
f7abfe8b
CW		 3919 if (!intel_crtc->active)
3920 return;
3921
ea9d758d
DV		 3922 for_each_encoder_on_crtc(dev, crtc, encoder)
3923 encoder->disable(encoder);
3924
0b8765c6 3925 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3926 intel_crtc_wait_for_pending_flips(crtc);
3927 drm_vblank_off(dev, pipe);
0b8765c6 3928
5c3fe8b0 3929 if (dev_priv->fbc.plane == plane)
973d04f9 3930 intel_disable_fbc(dev);
79e53945 3931
0d5b8c61
VS		 3932 intel_crtc_dpms_overlay(intel_crtc, false);
3933 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3934 intel_disable_planes(crtc);
b24e7179 3935 intel_disable_plane(dev_priv, plane, pipe);
0d5b8c61 3936
b24e7179 3937 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3938
87476d63 3939 i9xx_pfit_disable(intel_crtc);
24a1f16d 3940
89b667f8
JB		 3941 for_each_encoder_on_crtc(dev, crtc, encoder)
3942 if (encoder->post_disable)
3943 encoder->post_disable(encoder);
3944
f6071166
JB		 3945 if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3946 vlv_disable_pll(dev_priv, pipe);
3947 else if (!IS_VALLEYVIEW(dev))
e9fd1c02 3948 i9xx_disable_pll(dev_priv, pipe);
0b8765c6 3949
f7abfe8b 3950 intel_crtc->active = false;
46ba614c 3951 intel_update_watermarks(crtc);
f37fcc2a 3952
6b383a7f 3953 intel_update_fbc(dev);
0b8765c6
JB		 3954}
3955
ee7b9f93
JB		 3956static void i9xx_crtc_off(struct drm_crtc *crtc)
3957{
3958}
3959
976f8a20
DV		 3960static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3961 bool enabled)
2c07245f
ZW		 3962{
3963 struct drm_device *dev = crtc->dev;
3964 struct drm_i915_master_private *master_priv;
3965 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3966 int pipe = intel_crtc->pipe;
79e53945
JB		 3967
3968 if (!dev->primary->master)
3969 return;
3970
3971 master_priv = dev->primary->master->driver_priv;
3972 if (!master_priv->sarea_priv)
3973 return;
3974
79e53945
JB		 3975 switch (pipe) {
3976 case 0:
3977 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3978 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3979 break;
3980 case 1:
3981 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3982 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3983 break;
3984 default:
9db4a9c7 3985 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3986 break;
3987 }
79e53945
JB		 3988}
3989
976f8a20
DV		 3990/**
3991 * Sets the power management mode of the pipe and plane.
3992 */
3993void intel_crtc_update_dpms(struct drm_crtc *crtc)
3994{
3995 struct drm_device *dev = crtc->dev;
3996 struct drm_i915_private *dev_priv = dev->dev_private;
3997 struct intel_encoder *intel_encoder;
3998 bool enable = false;
3999
4000 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4001 enable |= intel_encoder->connectors_active;
4002
4003 if (enable)
4004 dev_priv->display.crtc_enable(crtc);
4005 else
4006 dev_priv->display.crtc_disable(crtc);
4007
4008 intel_crtc_update_sarea(crtc, enable);
4009}
4010
cdd59983
CW		 4011static void intel_crtc_disable(struct drm_crtc *crtc)
4012{
cdd59983 4013 struct drm_device *dev = crtc->dev;
976f8a20 4014 struct drm_connector *connector;
ee7b9f93 4015 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 4016 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 4017
976f8a20
DV		 4018 /* crtc should still be enabled when we disable it. */
4019 WARN_ON(!crtc->enabled);
4020
4021 dev_priv->display.crtc_disable(crtc);
c77bf565 4022 intel_crtc->eld_vld = false;
976f8a20 4023 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 4024 dev_priv->display.off(crtc);
4025
931872fc 4026 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
93ce0ba6 4027 assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
931872fc 4028 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 4029
4030 if (crtc->fb) {
4031 mutex_lock(&dev->struct_mutex);
1690e1eb 4032 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 4033 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 4034 crtc->fb = NULL;
4035 }
4036
4037 /* Update computed state. */
4038 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4039 if (!connector->encoder || !connector->encoder->crtc)
4040 continue;
4041
4042 if (connector->encoder->crtc != crtc)
4043 continue;
4044
4045 connector->dpms = DRM_MODE_DPMS_OFF;
4046 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 4047 }
4048}
4049
ea5b213a 4050void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 4051{
4ef69c7a 4052 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 4053
ea5b213a
CW		 4054 drm_encoder_cleanup(encoder);
4055 kfree(intel_encoder);
7e7d76c3
JB		 4056}
4057
9237329d 4058/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 4059 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4060 * state of the entire output pipe. */
9237329d 4061static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 4062{
5ab432ef
DV		 4063 if (mode == DRM_MODE_DPMS_ON) {
4064 encoder->connectors_active = true;
4065
b2cabb0e 4066 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 4067 } else {
4068 encoder->connectors_active = false;
4069
b2cabb0e 4070 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 4071 }
79e53945
JB		 4072}
4073
0a91ca29
DV		 4074/* Cross check the actual hw state with our own modeset state tracking (and it's
4075 * internal consistency). */
b980514c 4076static void intel_connector_check_state(struct intel_connector *connector)
79e53945 4077{
0a91ca29
DV		 4078 if (connector->get_hw_state(connector)) {
4079 struct intel_encoder *encoder = connector->encoder;
4080 struct drm_crtc *crtc;
4081 bool encoder_enabled;
4082 enum pipe pipe;
4083
4084 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4085 connector->base.base.id,
4086 drm_get_connector_name(&connector->base));
4087
4088 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4089 "wrong connector dpms state\n");
4090 WARN(connector->base.encoder != &encoder->base,
4091 "active connector not linked to encoder\n");
4092 WARN(!encoder->connectors_active,
4093 "encoder->connectors_active not set\n");
4094
4095 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4096 WARN(!encoder_enabled, "encoder not enabled\n");
4097 if (WARN_ON(!encoder->base.crtc))
4098 return;
4099
4100 crtc = encoder->base.crtc;
4101
4102 WARN(!crtc->enabled, "crtc not enabled\n");
4103 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4104 WARN(pipe != to_intel_crtc(crtc)->pipe,
4105 "encoder active on the wrong pipe\n");
4106 }
79e53945
JB		 4107}
4108
5ab432ef
DV		 4109/* Even simpler default implementation, if there's really no special case to
4110 * consider. */
4111void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 4112{
5ab432ef 4113 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 4114
5ab432ef
DV		 4115 /* All the simple cases only support two dpms states. */
4116 if (mode != DRM_MODE_DPMS_ON)
4117 mode = DRM_MODE_DPMS_OFF;
d4270e57 4118
5ab432ef
DV		 4119 if (mode == connector->dpms)
4120 return;
4121
4122 connector->dpms = mode;
4123
4124 /* Only need to change hw state when actually enabled */
4125 if (encoder->base.crtc)
4126 intel_encoder_dpms(encoder, mode);
4127 else
8af6cf88 4128 WARN_ON(encoder->connectors_active != false);
0a91ca29 4129
b980514c 4130 intel_modeset_check_state(connector->dev);
79e53945
JB		 4131}
4132
f0947c37
DV		 4133/* Simple connector->get_hw_state implementation for encoders that support only
4134 * one connector and no cloning and hence the encoder state determines the state
4135 * of the connector. */
4136bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 4137{
24929352 4138 enum pipe pipe = 0;
f0947c37 4139 struct intel_encoder *encoder = connector->encoder;
ea5b213a 4140
f0947c37 4141 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 4142}
4143
1857e1da
DV		 4144static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4145 struct intel_crtc_config *pipe_config)
4146{
4147 struct drm_i915_private *dev_priv = dev->dev_private;
4148 struct intel_crtc *pipe_B_crtc =
4149 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4150
4151 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4152 pipe_name(pipe), pipe_config->fdi_lanes);
4153 if (pipe_config->fdi_lanes > 4) {
4154 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4155 pipe_name(pipe), pipe_config->fdi_lanes);
4156 return false;
4157 }
4158
4159 if (IS_HASWELL(dev)) {
4160 if (pipe_config->fdi_lanes > 2) {
4161 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4162 pipe_config->fdi_lanes);
4163 return false;
4164 } else {
4165 return true;
4166 }
4167 }
4168
4169 if (INTEL_INFO(dev)->num_pipes == 2)
4170 return true;
4171
4172 /* Ivybridge 3 pipe is really complicated */
4173 switch (pipe) {
4174 case PIPE_A:
4175 return true;
4176 case PIPE_B:
4177 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4178 pipe_config->fdi_lanes > 2) {
4179 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4180 pipe_name(pipe), pipe_config->fdi_lanes);
4181 return false;
4182 }
4183 return true;
4184 case PIPE_C:
1e833f40 4185 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 4186 pipe_B_crtc->config.fdi_lanes <= 2) {
4187 if (pipe_config->fdi_lanes > 2) {
4188 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4189 pipe_name(pipe), pipe_config->fdi_lanes);
4190 return false;
4191 }
4192 } else {
4193 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4194 return false;
4195 }
4196 return true;
4197 default:
4198 BUG();
4199 }
4200}
4201
e29c22c0
DV		 4202#define RETRY 1
4203static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4204 struct intel_crtc_config *pipe_config)
877d48d5 4205{
1857e1da 4206 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 4207 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 4208 int lane, link_bw, fdi_dotclock;
e29c22c0 4209 bool setup_ok, needs_recompute = false;
877d48d5 4210
e29c22c0 4211retry:
877d48d5
DV		 4212 /* FDI is a binary signal running at ~2.7GHz, encoding
4213 * each output octet as 10 bits. The actual frequency
4214 * is stored as a divider into a 100MHz clock, and the
4215 * mode pixel clock is stored in units of 1KHz.
4216 * Hence the bw of each lane in terms of the mode signal
4217 * is:
4218 */
4219 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4220
241bfc38 4221 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 4222
2bd89a07 4223 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 4224 pipe_config->pipe_bpp);
4225
4226 pipe_config->fdi_lanes = lane;
4227
2bd89a07 4228 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4229 link_bw, &pipe_config->fdi_m_n);
1857e1da 4230
e29c22c0
DV		 4231 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4232 intel_crtc->pipe, pipe_config);
4233 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4234 pipe_config->pipe_bpp -= 2*3;
4235 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4236 pipe_config->pipe_bpp);
4237 needs_recompute = true;
4238 pipe_config->bw_constrained = true;
4239
4240 goto retry;
4241 }
4242
4243 if (needs_recompute)
4244 return RETRY;
4245
4246 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4247}
4248
42db64ef
PZ		 4249static void hsw_compute_ips_config(struct intel_crtc *crtc,
4250 struct intel_crtc_config *pipe_config)
4251{
3c4ca58c
PZ		 4252 pipe_config->ips_enabled = i915_enable_ips &&
4253 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 4254 pipe_config->pipe_bpp <= 24;
42db64ef
PZ		 4255}
4256
a43f6e0f 4257static int intel_crtc_compute_config(struct intel_crtc *crtc,
e29c22c0 4258 struct intel_crtc_config *pipe_config)
79e53945 4259{
a43f6e0f 4260 struct drm_device *dev = crtc->base.dev;
b8cecdf5 4261 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4262
ad3a4479 4263 /* FIXME should check pixel clock limits on all platforms */
cf532bb2
VS		 4264 if (INTEL_INFO(dev)->gen < 4) {
4265 struct drm_i915_private *dev_priv = dev->dev_private;
4266 int clock_limit =
4267 dev_priv->display.get_display_clock_speed(dev);
4268
4269 /*
4270 * Enable pixel doubling when the dot clock
4271 * is > 90% of the (display) core speed.
4272 *
b397c96b
VS		 4273 * GDG double wide on either pipe,
4274 * otherwise pipe A only.
cf532bb2 4275 */
b397c96b 4276 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 4277 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 4278 clock_limit *= 2;
cf532bb2 4279 pipe_config->double_wide = true;
ad3a4479
VS		 4280 }
4281
241bfc38 4282 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 4283 return -EINVAL;
2c07245f 4284 }
89749350 4285
1d1d0e27
VS		 4286 /*
4287 * Pipe horizontal size must be even in:
4288 * - DVO ganged mode
4289 * - LVDS dual channel mode
4290 * - Double wide pipe
4291 */
4292 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4293 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4294 pipe_config->pipe_src_w &= ~1;
4295
8693a824
DL		 4296 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4297 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4298 */
4299 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4300 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4301 return -EINVAL;
44f46b42 4302
bd080ee5 4303 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4304 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4305 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4306 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4307 * for lvds. */
4308 pipe_config->pipe_bpp = 8*3;
4309 }
4310
f5adf94e 4311 if (HAS_IPS(dev))
a43f6e0f
DV		 4312 hsw_compute_ips_config(crtc, pipe_config);
4313
4314 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4315 * clock survives for now. */
4316 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4317 pipe_config->shared_dpll = crtc->config.shared_dpll;
42db64ef 4318
877d48d5 4319 if (pipe_config->has_pch_encoder)
a43f6e0f 4320 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 4321
e29c22c0 4322 return 0;
79e53945
JB		 4323}
4324
25eb05fc
JB		 4325static int valleyview_get_display_clock_speed(struct drm_device *dev)
4326{
4327 return 400000; /* FIXME */
4328}
4329
e70236a8
JB		 4330static int i945_get_display_clock_speed(struct drm_device *dev)
4331{
4332 return 400000;
4333}
79e53945 4334
e70236a8 4335static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4336{
e70236a8
JB		 4337 return 333000;
4338}
79e53945 4339
e70236a8
JB		 4340static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4341{
4342 return 200000;
4343}
79e53945 4344
257a7ffc
DV		 4345static int pnv_get_display_clock_speed(struct drm_device *dev)
4346{
4347 u16 gcfgc = 0;
4348
4349 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4350
4351 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4352 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4353 return 267000;
4354 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4355 return 333000;
4356 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4357 return 444000;
4358 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4359 return 200000;
4360 default:
4361 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4362 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4363 return 133000;
4364 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4365 return 167000;
4366 }
4367}
4368
e70236a8
JB		 4369static int i915gm_get_display_clock_speed(struct drm_device *dev)
4370{
4371 u16 gcfgc = 0;
79e53945 4372
e70236a8
JB		 4373 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4374
4375 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4376 return 133000;
4377 else {
4378 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4379 case GC_DISPLAY_CLOCK_333_MHZ:
4380 return 333000;
4381 default:
4382 case GC_DISPLAY_CLOCK_190_200_MHZ:
4383 return 190000;
79e53945 4384 }
e70236a8
JB		 4385 }
4386}
4387
4388static int i865_get_display_clock_speed(struct drm_device *dev)
4389{
4390 return 266000;
4391}
4392
4393static int i855_get_display_clock_speed(struct drm_device *dev)
4394{
4395 u16 hpllcc = 0;
4396 /* Assume that the hardware is in the high speed state. This
4397 * should be the default.
4398 */
4399 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4400 case GC_CLOCK_133_200:
4401 case GC_CLOCK_100_200:
4402 return 200000;
4403 case GC_CLOCK_166_250:
4404 return 250000;
4405 case GC_CLOCK_100_133:
79e53945 4406 return 133000;
e70236a8 4407 }
79e53945 4408
e70236a8
JB		 4409 /* Shouldn't happen */
4410 return 0;
4411}
79e53945 4412
e70236a8
JB		 4413static int i830_get_display_clock_speed(struct drm_device *dev)
4414{
4415 return 133000;
79e53945
JB		 4416}
4417
2c07245f 4418static void
a65851af 4419intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4420{
a65851af
VS		 4421 while (*num > DATA_LINK_M_N_MASK ||
4422 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4423 *num >>= 1;
4424 *den >>= 1;
4425 }
4426}
4427
a65851af
VS		 4428static void compute_m_n(unsigned int m, unsigned int n,
4429 uint32_t *ret_m, uint32_t *ret_n)
4430{
4431 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4432 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4433 intel_reduce_m_n_ratio(ret_m, ret_n);
4434}
4435
e69d0bc1
DV		 4436void
4437intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4438 int pixel_clock, int link_clock,
4439 struct intel_link_m_n *m_n)
2c07245f 4440{
e69d0bc1 4441 m_n->tu = 64;
a65851af
VS		 4442
4443 compute_m_n(bits_per_pixel * pixel_clock,
4444 link_clock * nlanes * 8,
4445 &m_n->gmch_m, &m_n->gmch_n);
4446
4447 compute_m_n(pixel_clock, link_clock,
4448 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4449}
4450
a7615030
CW		 4451static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4452{
72bbe58c
KP		 4453 if (i915_panel_use_ssc >= 0)
4454 return i915_panel_use_ssc != 0;
41aa3448 4455 return dev_priv->vbt.lvds_use_ssc
435793df 4456 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4457}
4458
c65d77d8
JB		 4459static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4460{
4461 struct drm_device *dev = crtc->dev;
4462 struct drm_i915_private *dev_priv = dev->dev_private;
4463 int refclk;
4464
a0c4da24 4465 if (IS_VALLEYVIEW(dev)) {
9a0ea498 4466 refclk = 100000;
a0c4da24 4467 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4468 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4469 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4470 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4471 refclk / 1000);
4472 } else if (!IS_GEN2(dev)) {
4473 refclk = 96000;
4474 } else {
4475 refclk = 48000;
4476 }
4477
4478 return refclk;
4479}
4480
7429e9d4 4481static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 4482{
7df00d7a 4483 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 4484}
f47709a9 4485
7429e9d4
DV		 4486static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4487{
4488 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 4489}
4490
f47709a9 4491static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4492 intel_clock_t *reduced_clock)
4493{
f47709a9 4494 struct drm_device *dev = crtc->base.dev;
a7516a05 4495 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4496 int pipe = crtc->pipe;
a7516a05
JB		 4497 u32 fp, fp2 = 0;
4498
4499 if (IS_PINEVIEW(dev)) {
7429e9d4 4500 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4501 if (reduced_clock)
7429e9d4 4502 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4503 } else {
7429e9d4 4504 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4505 if (reduced_clock)
7429e9d4 4506 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4507 }
4508
4509 I915_WRITE(FP0(pipe), fp);
8bcc2795 4510 crtc->config.dpll_hw_state.fp0 = fp;
a7516a05 4511
f47709a9
DV		 4512 crtc->lowfreq_avail = false;
4513 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4514 reduced_clock && i915_powersave) {
4515 I915_WRITE(FP1(pipe), fp2);
8bcc2795 4516 crtc->config.dpll_hw_state.fp1 = fp2;
f47709a9 4517 crtc->lowfreq_avail = true;
a7516a05
JB		 4518 } else {
4519 I915_WRITE(FP1(pipe), fp);
8bcc2795 4520 crtc->config.dpll_hw_state.fp1 = fp;
a7516a05
JB		 4521 }
4522}
4523
5e69f97f
CML		 4524static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4525 pipe)
89b667f8
JB		 4526{
4527 u32 reg_val;
4528
4529 /*
4530 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4531 * and set it to a reasonable value instead.
4532 */
5e69f97f 4533 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
89b667f8
JB		 4534 reg_val &= 0xffffff00;
4535 reg_val |= 0x00000030;
5e69f97f 4536 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
89b667f8 4537
5e69f97f 4538 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
89b667f8
JB		 4539 reg_val &= 0x8cffffff;
4540 reg_val = 0x8c000000;
5e69f97f 4541 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
89b667f8 4542
5e69f97f 4543 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
89b667f8 4544 reg_val &= 0xffffff00;
5e69f97f 4545 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
89b667f8 4546
5e69f97f 4547 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
89b667f8
JB		 4548 reg_val &= 0x00ffffff;
4549 reg_val |= 0xb0000000;
5e69f97f 4550 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4551}
4552
b551842d
DV		 4553static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4554 struct intel_link_m_n *m_n)
4555{
4556 struct drm_device *dev = crtc->base.dev;
4557 struct drm_i915_private *dev_priv = dev->dev_private;
4558 int pipe = crtc->pipe;
4559
e3b95f1e
DV		 4560 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4561 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4562 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4563 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4564}
4565
4566static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4567 struct intel_link_m_n *m_n)
4568{
4569 struct drm_device *dev = crtc->base.dev;
4570 struct drm_i915_private *dev_priv = dev->dev_private;
4571 int pipe = crtc->pipe;
4572 enum transcoder transcoder = crtc->config.cpu_transcoder;
4573
4574 if (INTEL_INFO(dev)->gen >= 5) {
4575 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4576 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4577 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4578 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4579 } else {
e3b95f1e
DV		 4580 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4581 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4582 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4583 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4584 }
4585}
4586
03afc4a2
DV		 4587static void intel_dp_set_m_n(struct intel_crtc *crtc)
4588{
4589 if (crtc->config.has_pch_encoder)
4590 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4591 else
4592 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4593}
4594
f47709a9 4595static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4596{
f47709a9 4597 struct drm_device *dev = crtc->base.dev;
a0c4da24 4598 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4599 int pipe = crtc->pipe;
89b667f8 4600 u32 dpll, mdiv;
a0c4da24 4601 u32 bestn, bestm1, bestm2, bestp1, bestp2;
198a037f 4602 u32 coreclk, reg_val, dpll_md;
a0c4da24 4603
09153000
DV		 4604 mutex_lock(&dev_priv->dpio_lock);
4605
f47709a9
DV		 4606 bestn = crtc->config.dpll.n;
4607 bestm1 = crtc->config.dpll.m1;
4608 bestm2 = crtc->config.dpll.m2;
4609 bestp1 = crtc->config.dpll.p1;
4610 bestp2 = crtc->config.dpll.p2;
a0c4da24 4611
89b667f8
JB		 4612 /* See eDP HDMI DPIO driver vbios notes doc */
4613
4614 /* PLL B needs special handling */
4615 if (pipe)
5e69f97f 4616 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 4617
4618 /* Set up Tx target for periodic Rcomp update */
5e69f97f 4619 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4620
4621 /* Disable target IRef on PLL */
5e69f97f 4622 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe));
89b667f8 4623 reg_val &= 0x00ffffff;
5e69f97f 4624 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4625
4626 /* Disable fast lock */
5e69f97f 4627 vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4628
4629 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4630 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4631 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4632 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4633 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4634
4635 /*
4636 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4637 * but we don't support that).
4638 * Note: don't use the DAC post divider as it seems unstable.
4639 */
4640 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5e69f97f 4641 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
a0c4da24 4642
a0c4da24 4643 mdiv |= DPIO_ENABLE_CALIBRATION;
5e69f97f 4644 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
a0c4da24 4645
89b667f8 4646 /* Set HBR and RBR LPF coefficients */
ff9a6750 4647 if (crtc->config.port_clock == 162000 ||
99750bd4 4648 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
89b667f8 4649 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5e69f97f 4650 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
885b0120 4651 0x009f0003);
89b667f8 4652 else
5e69f97f 4653 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
89b667f8
JB		 4654 0x00d0000f);
4655
4656 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4657 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4658 /* Use SSC source */
4659 if (!pipe)
5e69f97f 4660 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4661 0x0df40000);
4662 else
5e69f97f 4663 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4664 0x0df70000);
4665 } else { /* HDMI or VGA */
4666 /* Use bend source */
4667 if (!pipe)
5e69f97f 4668 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4669 0x0df70000);
4670 else
5e69f97f 4671 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4672 0x0df40000);
4673 }
a0c4da24 4674
5e69f97f 4675 coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4676 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4677 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4678 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4679 coreclk |= 0x01000000;
5e69f97f 4680 vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4681
5e69f97f 4682 vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4683
89b667f8
JB		 4684 /* Enable DPIO clock input */
4685 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4686 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
f6071166
JB		 4687 /* We should never disable this, set it here for state tracking */
4688 if (pipe == PIPE_B)
89b667f8 4689 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
a0c4da24 4690 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4691 crtc->config.dpll_hw_state.dpll = dpll;
4692
ef1b460d
DV		 4693 dpll_md = (crtc->config.pixel_multiplier - 1)
4694 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795
DV		 4695 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4696
89b667f8
JB		 4697 if (crtc->config.has_dp_encoder)
4698 intel_dp_set_m_n(crtc);
09153000
DV		 4699
4700 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4701}
4702
f47709a9
DV		 4703static void i9xx_update_pll(struct intel_crtc *crtc,
4704 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4705 int num_connectors)
4706{
f47709a9 4707 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4708 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 4709 u32 dpll;
4710 bool is_sdvo;
f47709a9 4711 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4712
f47709a9 4713 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4714
f47709a9
DV		 4715 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4716 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4717
4718 dpll = DPLL_VGA_MODE_DIS;
4719
f47709a9 4720 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4721 dpll |= DPLLB_MODE_LVDS;
4722 else
4723 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4724
ef1b460d 4725 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
198a037f
DV		 4726 dpll |= (crtc->config.pixel_multiplier - 1)
4727 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4728 }
198a037f
DV		 4729
4730 if (is_sdvo)
4a33e48d 4731 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 4732
f47709a9 4733 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4a33e48d 4734 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 4735
4736 /* compute bitmask from p1 value */
4737 if (IS_PINEVIEW(dev))
4738 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4739 else {
4740 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4741 if (IS_G4X(dev) && reduced_clock)
4742 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4743 }
4744 switch (clock->p2) {
4745 case 5:
4746 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4747 break;
4748 case 7:
4749 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4750 break;
4751 case 10:
4752 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4753 break;
4754 case 14:
4755 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4756 break;
4757 }
4758 if (INTEL_INFO(dev)->gen >= 4)
4759 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4760
09ede541 4761 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4762 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4763 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4764 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4765 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4766 else
4767 dpll |= PLL_REF_INPUT_DREFCLK;
4768
4769 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4770 crtc->config.dpll_hw_state.dpll = dpll;
4771
eb1cbe48 4772 if (INTEL_INFO(dev)->gen >= 4) {
ef1b460d
DV		 4773 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4774 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795 4775 crtc->config.dpll_hw_state.dpll_md = dpll_md;
eb1cbe48 4776 }
66e3d5c0
DV		 4777
4778 if (crtc->config.has_dp_encoder)
4779 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4780}
4781
f47709a9 4782static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 4783 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4784 int num_connectors)
4785{
f47709a9 4786 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4787 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 4788 u32 dpll;
f47709a9 4789 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4790
f47709a9 4791 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4792
eb1cbe48
DV		 4793 dpll = DPLL_VGA_MODE_DIS;
4794
f47709a9 4795 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4796 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4797 } else {
4798 if (clock->p1 == 2)
4799 dpll |= PLL_P1_DIVIDE_BY_TWO;
4800 else
4801 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4802 if (clock->p2 == 4)
4803 dpll |= PLL_P2_DIVIDE_BY_4;
4804 }
4805
4a33e48d
DV		 4806 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4807 dpll |= DPLL_DVO_2X_MODE;
4808
f47709a9 4809 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4810 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4811 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4812 else
4813 dpll |= PLL_REF_INPUT_DREFCLK;
4814
4815 dpll |= DPLL_VCO_ENABLE;
8bcc2795 4816 crtc->config.dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 4817}
4818
8a654f3b 4819static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 4820{
4821 struct drm_device *dev = intel_crtc->base.dev;
4822 struct drm_i915_private *dev_priv = dev->dev_private;
4823 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4824 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV		 4825 struct drm_display_mode *adjusted_mode =
4826 &intel_crtc->config.adjusted_mode;
4d8a62ea
DV		 4827 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4828
4829 /* We need to be careful not to changed the adjusted mode, for otherwise
4830 * the hw state checker will get angry at the mismatch. */
4831 crtc_vtotal = adjusted_mode->crtc_vtotal;
4832 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4833
4834 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4835 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4836 crtc_vtotal -= 1;
4837 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4838 vsyncshift = adjusted_mode->crtc_hsync_start
4839 - adjusted_mode->crtc_htotal / 2;
4840 } else {
4841 vsyncshift = 0;
4842 }
4843
4844 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4845 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4846
fe2b8f9d 4847 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4848 (adjusted_mode->crtc_hdisplay - 1) |
4849 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4850 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4851 (adjusted_mode->crtc_hblank_start - 1) |
4852 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4853 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4854 (adjusted_mode->crtc_hsync_start - 1) |
4855 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4856
fe2b8f9d 4857 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4858 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4859 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4860 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4861 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4862 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4863 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4864 (adjusted_mode->crtc_vsync_start - 1) |
4865 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4866
b5e508d4
PZ		 4867 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4868 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4869 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4870 * bits. */
4871 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4872 (pipe == PIPE_B || pipe == PIPE_C))
4873 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4874
b0e77b9c
PZ		 4875 /* pipesrc controls the size that is scaled from, which should
4876 * always be the user's requested size.
4877 */
4878 I915_WRITE(PIPESRC(pipe),
37327abd
VS		 4879 ((intel_crtc->config.pipe_src_w - 1) << 16) |
4880 (intel_crtc->config.pipe_src_h - 1));
b0e77b9c
PZ		 4881}
4882
1bd1bd80
DV		 4883static void intel_get_pipe_timings(struct intel_crtc *crtc,
4884 struct intel_crtc_config *pipe_config)
4885{
4886 struct drm_device *dev = crtc->base.dev;
4887 struct drm_i915_private *dev_priv = dev->dev_private;
4888 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4889 uint32_t tmp;
4890
4891 tmp = I915_READ(HTOTAL(cpu_transcoder));
4892 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4893 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4894 tmp = I915_READ(HBLANK(cpu_transcoder));
4895 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4896 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4897 tmp = I915_READ(HSYNC(cpu_transcoder));
4898 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4899 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4900
4901 tmp = I915_READ(VTOTAL(cpu_transcoder));
4902 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4903 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4904 tmp = I915_READ(VBLANK(cpu_transcoder));
4905 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4906 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4907 tmp = I915_READ(VSYNC(cpu_transcoder));
4908 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4909 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4910
4911 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4912 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4913 pipe_config->adjusted_mode.crtc_vtotal += 1;
4914 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4915 }
4916
4917 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 4918 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
4919 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
4920
4921 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
4922 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 4923}
4924
babea61d
JB		 4925static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4926 struct intel_crtc_config *pipe_config)
4927{
4928 struct drm_crtc *crtc = &intel_crtc->base;
4929
4930 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4931 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4932 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4933 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4934
4935 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4936 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4937 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4938 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4939
4940 crtc->mode.flags = pipe_config->adjusted_mode.flags;
4941
241bfc38 4942 crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock;
babea61d
JB		 4943 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4944}
4945
84b046f3
DV		 4946static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4947{
4948 struct drm_device *dev = intel_crtc->base.dev;
4949 struct drm_i915_private *dev_priv = dev->dev_private;
4950 uint32_t pipeconf;
4951
9f11a9e4 4952 pipeconf = 0;
84b046f3 4953
67c72a12
DV		 4954 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
4955 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
4956 pipeconf |= PIPECONF_ENABLE;
4957
cf532bb2
VS		 4958 if (intel_crtc->config.double_wide)
4959 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 4960
ff9ce46e
DV		 4961 /* only g4x and later have fancy bpc/dither controls */
4962 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e
DV		 4963 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4964 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4965 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4966 PIPECONF_DITHER_TYPE_SP;
84b046f3 4967
ff9ce46e
DV		 4968 switch (intel_crtc->config.pipe_bpp) {
4969 case 18:
4970 pipeconf |= PIPECONF_6BPC;
4971 break;
4972 case 24:
4973 pipeconf |= PIPECONF_8BPC;
4974 break;
4975 case 30:
4976 pipeconf |= PIPECONF_10BPC;
4977 break;
4978 default:
4979 /* Case prevented by intel_choose_pipe_bpp_dither. */
4980 BUG();
84b046f3
DV		 4981 }
4982 }
4983
4984 if (HAS_PIPE_CXSR(dev)) {
4985 if (intel_crtc->lowfreq_avail) {
4986 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4987 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4988 } else {
4989 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 4990 }
4991 }
4992
84b046f3
DV		 4993 if (!IS_GEN2(dev) &&
4994 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4995 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4996 else
4997 pipeconf |= PIPECONF_PROGRESSIVE;
4998
9f11a9e4
DV		 4999 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5000 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 5001
84b046f3
DV		 5002 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5003 POSTING_READ(PIPECONF(intel_crtc->pipe));
5004}
5005
f564048e 5006static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 5007 int x, int y,
94352cf9 5008 struct drm_framebuffer *fb)
79e53945
JB		 5009{
5010 struct drm_device *dev = crtc->dev;
5011 struct drm_i915_private *dev_priv = dev->dev_private;
5012 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5013 int pipe = intel_crtc->pipe;
80824003 5014 int plane = intel_crtc->plane;
c751ce4f 5015 int refclk, num_connectors = 0;
652c393a 5016 intel_clock_t clock, reduced_clock;
84b046f3 5017 u32 dspcntr;
a16af721 5018 bool ok, has_reduced_clock = false;
e9fd1c02 5019 bool is_lvds = false, is_dsi = false;
5eddb70b 5020 struct intel_encoder *encoder;
d4906093 5021 const intel_limit_t *limit;
5c3b82e2 5022 int ret;
79e53945 5023
6c2b7c12 5024 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 5025 switch (encoder->type) {
79e53945
JB		 5026 case INTEL_OUTPUT_LVDS:
5027 is_lvds = true;
5028 break;
e9fd1c02
JN		 5029 case INTEL_OUTPUT_DSI:
5030 is_dsi = true;
5031 break;
79e53945 5032 }
43565a06 5033
c751ce4f 5034 num_connectors++;
79e53945
JB		 5035 }
5036
f2335330
JN		 5037 if (is_dsi)
5038 goto skip_dpll;
5039
5040 if (!intel_crtc->config.clock_set) {
5041 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 5042
e9fd1c02
JN		 5043 /*
5044 * Returns a set of divisors for the desired target clock with
5045 * the given refclk, or FALSE. The returned values represent
5046 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5047 * 2) / p1 / p2.
5048 */
5049 limit = intel_limit(crtc, refclk);
5050 ok = dev_priv->display.find_dpll(limit, crtc,
5051 intel_crtc->config.port_clock,
5052 refclk, NULL, &clock);
f2335330 5053 if (!ok) {
e9fd1c02
JN		 5054 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5055 return -EINVAL;
5056 }
79e53945 5057
f2335330
JN		 5058 if (is_lvds && dev_priv->lvds_downclock_avail) {
5059 /*
5060 * Ensure we match the reduced clock's P to the target
5061 * clock. If the clocks don't match, we can't switch
5062 * the display clock by using the FP0/FP1. In such case
5063 * we will disable the LVDS downclock feature.
5064 */
5065 has_reduced_clock =
5066 dev_priv->display.find_dpll(limit, crtc,
5067 dev_priv->lvds_downclock,
5068 refclk, &clock,
5069 &reduced_clock);
5070 }
5071 /* Compat-code for transition, will disappear. */
f47709a9
DV		 5072 intel_crtc->config.dpll.n = clock.n;
5073 intel_crtc->config.dpll.m1 = clock.m1;
5074 intel_crtc->config.dpll.m2 = clock.m2;
5075 intel_crtc->config.dpll.p1 = clock.p1;
5076 intel_crtc->config.dpll.p2 = clock.p2;
5077 }
7026d4ac 5078
e9fd1c02 5079 if (IS_GEN2(dev)) {
8a654f3b 5080 i8xx_update_pll(intel_crtc,
2a8f64ca
VP		 5081 has_reduced_clock ? &reduced_clock : NULL,
5082 num_connectors);
e9fd1c02 5083 } else if (IS_VALLEYVIEW(dev)) {
f2335330 5084 vlv_update_pll(intel_crtc);
e9fd1c02 5085 } else {
f47709a9 5086 i9xx_update_pll(intel_crtc,
eb1cbe48 5087 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 5088 num_connectors);
e9fd1c02 5089 }
79e53945 5090
f2335330 5091skip_dpll:
79e53945
JB		 5092 /* Set up the display plane register */
5093 dspcntr = DISPPLANE_GAMMA_ENABLE;
5094
da6ecc5d
JB		 5095 if (!IS_VALLEYVIEW(dev)) {
5096 if (pipe == 0)
5097 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5098 else
5099 dspcntr |= DISPPLANE_SEL_PIPE_B;
5100 }
79e53945 5101
8a654f3b 5102 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW		 5103
5104 /* pipesrc and dspsize control the size that is scaled from,
5105 * which should always be the user's requested size.
79e53945 5106 */
929c77fb 5107 I915_WRITE(DSPSIZE(plane),
37327abd
VS		 5108 ((intel_crtc->config.pipe_src_h - 1) << 16) |
5109 (intel_crtc->config.pipe_src_w - 1));
929c77fb 5110 I915_WRITE(DSPPOS(plane), 0);
2c07245f 5111
84b046f3
DV		 5112 i9xx_set_pipeconf(intel_crtc);
5113
f564048e
EA		 5114 I915_WRITE(DSPCNTR(plane), dspcntr);
5115 POSTING_READ(DSPCNTR(plane));
5116
94352cf9 5117 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e 5118
f564048e
EA		 5119 return ret;
5120}
5121
2fa2fe9a
DV		 5122static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5123 struct intel_crtc_config *pipe_config)
5124{
5125 struct drm_device *dev = crtc->base.dev;
5126 struct drm_i915_private *dev_priv = dev->dev_private;
5127 uint32_t tmp;
5128
5129 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 5130 if (!(tmp & PFIT_ENABLE))
5131 return;
2fa2fe9a 5132
06922821 5133 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 5134 if (INTEL_INFO(dev)->gen < 4) {
5135 if (crtc->pipe != PIPE_B)
5136 return;
2fa2fe9a
DV		 5137 } else {
5138 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5139 return;
5140 }
5141
06922821 5142 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 5143 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5144 if (INTEL_INFO(dev)->gen < 5)
5145 pipe_config->gmch_pfit.lvds_border_bits =
5146 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5147}
5148
acbec814
JB		 5149static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5150 struct intel_crtc_config *pipe_config)
5151{
5152 struct drm_device *dev = crtc->base.dev;
5153 struct drm_i915_private *dev_priv = dev->dev_private;
5154 int pipe = pipe_config->cpu_transcoder;
5155 intel_clock_t clock;
5156 u32 mdiv;
662c6ecb 5157 int refclk = 100000;
acbec814
JB		 5158
5159 mutex_lock(&dev_priv->dpio_lock);
5160 mdiv = vlv_dpio_read(dev_priv, pipe, DPIO_DIV(pipe));
5161 mutex_unlock(&dev_priv->dpio_lock);
5162
5163 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5164 clock.m2 = mdiv & DPIO_M2DIV_MASK;
5165 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5166 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5167 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5168
662c6ecb
CW		 5169 clock.vco = refclk * clock.m1 * clock.m2 / clock.n;
5170 clock.dot = 2 * clock.vco / (clock.p1 * clock.p2);
acbec814
JB		 5171
5172 pipe_config->port_clock = clock.dot / 10;
5173}
5174
0e8ffe1b
DV		 5175static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5176 struct intel_crtc_config *pipe_config)
5177{
5178 struct drm_device *dev = crtc->base.dev;
5179 struct drm_i915_private *dev_priv = dev->dev_private;
5180 uint32_t tmp;
5181
e143a21c 5182 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 5183 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5184
0e8ffe1b
DV		 5185 tmp = I915_READ(PIPECONF(crtc->pipe));
5186 if (!(tmp & PIPECONF_ENABLE))
5187 return false;
5188
42571aef
VS		 5189 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5190 switch (tmp & PIPECONF_BPC_MASK) {
5191 case PIPECONF_6BPC:
5192 pipe_config->pipe_bpp = 18;
5193 break;
5194 case PIPECONF_8BPC:
5195 pipe_config->pipe_bpp = 24;
5196 break;
5197 case PIPECONF_10BPC:
5198 pipe_config->pipe_bpp = 30;
5199 break;
5200 default:
5201 break;
5202 }
5203 }
5204
282740f7
VS		 5205 if (INTEL_INFO(dev)->gen < 4)
5206 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5207
1bd1bd80
DV		 5208 intel_get_pipe_timings(crtc, pipe_config);
5209
2fa2fe9a
DV		 5210 i9xx_get_pfit_config(crtc, pipe_config);
5211
6c49f241
DV		 5212 if (INTEL_INFO(dev)->gen >= 4) {
5213 tmp = I915_READ(DPLL_MD(crtc->pipe));
5214 pipe_config->pixel_multiplier =
5215 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5216 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 5217 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 5218 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5219 tmp = I915_READ(DPLL(crtc->pipe));
5220 pipe_config->pixel_multiplier =
5221 ((tmp & SDVO_MULTIPLIER_MASK)
5222 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5223 } else {
5224 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5225 * port and will be fixed up in the encoder->get_config
5226 * function. */
5227 pipe_config->pixel_multiplier = 1;
5228 }
8bcc2795
DV		 5229 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5230 if (!IS_VALLEYVIEW(dev)) {
5231 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5232 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 5233 } else {
5234 /* Mask out read-only status bits. */
5235 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5236 DPLL_PORTC_READY_MASK |
5237 DPLL_PORTB_READY_MASK);
8bcc2795 5238 }
6c49f241 5239
acbec814
JB		 5240 if (IS_VALLEYVIEW(dev))
5241 vlv_crtc_clock_get(crtc, pipe_config);
5242 else
5243 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 5244
0e8ffe1b
DV		 5245 return true;
5246}
5247
dde86e2d 5248static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5249{
5250 struct drm_i915_private *dev_priv = dev->dev_private;
5251 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5252 struct intel_encoder *encoder;
74cfd7ac 5253 u32 val, final;
13d83a67 5254 bool has_lvds = false;
199e5d79 5255 bool has_cpu_edp = false;
199e5d79 5256 bool has_panel = false;
99eb6a01
KP		 5257 bool has_ck505 = false;
5258 bool can_ssc = false;
13d83a67
JB		 5259
5260 /* We need to take the global config into account */
199e5d79
KP		 5261 list_for_each_entry(encoder, &mode_config->encoder_list,
5262 base.head) {
5263 switch (encoder->type) {
5264 case INTEL_OUTPUT_LVDS:
5265 has_panel = true;
5266 has_lvds = true;
5267 break;
5268 case INTEL_OUTPUT_EDP:
5269 has_panel = true;
2de6905f 5270 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5271 has_cpu_edp = true;
5272 break;
13d83a67
JB		 5273 }
5274 }
5275
99eb6a01 5276 if (HAS_PCH_IBX(dev)) {
41aa3448 5277 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5278 can_ssc = has_ck505;
5279 } else {
5280 has_ck505 = false;
5281 can_ssc = true;
5282 }
5283
2de6905f
ID		 5284 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5285 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5286
5287 /* Ironlake: try to setup display ref clock before DPLL
5288 * enabling. This is only under driver's control after
5289 * PCH B stepping, previous chipset stepping should be
5290 * ignoring this setting.
5291 */
74cfd7ac
CW		 5292 val = I915_READ(PCH_DREF_CONTROL);
5293
5294 /* As we must carefully and slowly disable/enable each source in turn,
5295 * compute the final state we want first and check if we need to
5296 * make any changes at all.
5297 */
5298 final = val;
5299 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5300 if (has_ck505)
5301 final |= DREF_NONSPREAD_CK505_ENABLE;
5302 else
5303 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5304
5305 final &= ~DREF_SSC_SOURCE_MASK;
5306 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5307 final &= ~DREF_SSC1_ENABLE;
5308
5309 if (has_panel) {
5310 final |= DREF_SSC_SOURCE_ENABLE;
5311
5312 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5313 final |= DREF_SSC1_ENABLE;
5314
5315 if (has_cpu_edp) {
5316 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5317 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5318 else
5319 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5320 } else
5321 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5322 } else {
5323 final |= DREF_SSC_SOURCE_DISABLE;
5324 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5325 }
5326
5327 if (final == val)
5328 return;
5329
13d83a67 5330 /* Always enable nonspread source */
74cfd7ac 5331 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5332
99eb6a01 5333 if (has_ck505)
74cfd7ac 5334 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5335 else
74cfd7ac 5336 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5337
199e5d79 5338 if (has_panel) {
74cfd7ac
CW		 5339 val &= ~DREF_SSC_SOURCE_MASK;
5340 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5341
199e5d79 5342 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5343 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5344 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5345 val |= DREF_SSC1_ENABLE;
e77166b5 5346 } else
74cfd7ac 5347 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5348
5349 /* Get SSC going before enabling the outputs */
74cfd7ac 5350 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5351 POSTING_READ(PCH_DREF_CONTROL);
5352 udelay(200);
5353
74cfd7ac 5354 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5355
5356 /* Enable CPU source on CPU attached eDP */
199e5d79 5357 if (has_cpu_edp) {
99eb6a01 5358 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5359 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5360 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5361 }
13d83a67 5362 else
74cfd7ac 5363 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5364 } else
74cfd7ac 5365 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5366
74cfd7ac 5367 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5368 POSTING_READ(PCH_DREF_CONTROL);
5369 udelay(200);
5370 } else {
5371 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5372
74cfd7ac 5373 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5374
5375 /* Turn off CPU output */
74cfd7ac 5376 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5377
74cfd7ac 5378 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5379 POSTING_READ(PCH_DREF_CONTROL);
5380 udelay(200);
5381
5382 /* Turn off the SSC source */
74cfd7ac
CW		 5383 val &= ~DREF_SSC_SOURCE_MASK;
5384 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5385
5386 /* Turn off SSC1 */
74cfd7ac 5387 val &= ~DREF_SSC1_ENABLE;
199e5d79 5388
74cfd7ac 5389 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5390 POSTING_READ(PCH_DREF_CONTROL);
5391 udelay(200);
5392 }
74cfd7ac
CW		 5393
5394 BUG_ON(val != final);
13d83a67
JB		 5395}
5396
f31f2d55 5397static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 5398{
f31f2d55 5399 uint32_t tmp;
dde86e2d 5400
0ff066a9
PZ		 5401 tmp = I915_READ(SOUTH_CHICKEN2);
5402 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5403 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5404
0ff066a9
PZ		 5405 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5406 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5407 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 5408
0ff066a9
PZ		 5409 tmp = I915_READ(SOUTH_CHICKEN2);
5410 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5411 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5412
0ff066a9
PZ		 5413 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5414 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5415 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 5416}
5417
5418/* WaMPhyProgramming:hsw */
5419static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5420{
5421 uint32_t tmp;
dde86e2d
PZ		 5422
5423 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5424 tmp &= ~(0xFF << 24);
5425 tmp |= (0x12 << 24);
5426 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5427
dde86e2d
PZ		 5428 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5429 tmp |= (1 << 11);
5430 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5431
5432 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5433 tmp |= (1 << 11);
5434 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5435
dde86e2d
PZ		 5436 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5437 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5438 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5439
5440 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5441 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5442 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5443
0ff066a9
PZ		 5444 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5445 tmp &= ~(7 << 13);
5446 tmp |= (5 << 13);
5447 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 5448
0ff066a9
PZ		 5449 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5450 tmp &= ~(7 << 13);
5451 tmp |= (5 << 13);
5452 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 5453
5454 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5455 tmp &= ~0xFF;
5456 tmp |= 0x1C;
5457 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5458
5459 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5460 tmp &= ~0xFF;
5461 tmp |= 0x1C;
5462 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5463
5464 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5465 tmp &= ~(0xFF << 16);
5466 tmp |= (0x1C << 16);
5467 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5468
5469 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5470 tmp &= ~(0xFF << 16);
5471 tmp |= (0x1C << 16);
5472 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5473
0ff066a9
PZ		 5474 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5475 tmp |= (1 << 27);
5476 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 5477
0ff066a9
PZ		 5478 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5479 tmp |= (1 << 27);
5480 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 5481
0ff066a9
PZ		 5482 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5483 tmp &= ~(0xF << 28);
5484 tmp |= (4 << 28);
5485 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 5486
0ff066a9
PZ		 5487 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5488 tmp &= ~(0xF << 28);
5489 tmp |= (4 << 28);
5490 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 5491}
5492
2fa86a1f
PZ		 5493/* Implements 3 different sequences from BSpec chapter "Display iCLK
5494 * Programming" based on the parameters passed:
5495 * - Sequence to enable CLKOUT_DP
5496 * - Sequence to enable CLKOUT_DP without spread
5497 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5498 */
5499static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5500 bool with_fdi)
f31f2d55
PZ		 5501{
5502 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 5503 uint32_t reg, tmp;
5504
5505 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5506 with_spread = true;
5507 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5508 with_fdi, "LP PCH doesn't have FDI\n"))
5509 with_fdi = false;
f31f2d55
PZ		 5510
5511 mutex_lock(&dev_priv->dpio_lock);
5512
5513 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5514 tmp &= ~SBI_SSCCTL_DISABLE;
5515 tmp |= SBI_SSCCTL_PATHALT;
5516 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5517
5518 udelay(24);
5519
2fa86a1f
PZ		 5520 if (with_spread) {
5521 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5522 tmp &= ~SBI_SSCCTL_PATHALT;
5523 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 5524
2fa86a1f
PZ		 5525 if (with_fdi) {
5526 lpt_reset_fdi_mphy(dev_priv);
5527 lpt_program_fdi_mphy(dev_priv);
5528 }
5529 }
dde86e2d 5530
2fa86a1f
PZ		 5531 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5532 SBI_GEN0 : SBI_DBUFF0;
5533 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5534 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5535 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
DV		 5536
5537 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5538}
5539
47701c3b
PZ		 5540/* Sequence to disable CLKOUT_DP */
5541static void lpt_disable_clkout_dp(struct drm_device *dev)
5542{
5543 struct drm_i915_private *dev_priv = dev->dev_private;
5544 uint32_t reg, tmp;
5545
5546 mutex_lock(&dev_priv->dpio_lock);
5547
5548 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5549 SBI_GEN0 : SBI_DBUFF0;
5550 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5551 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5552 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5553
5554 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5555 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5556 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5557 tmp |= SBI_SSCCTL_PATHALT;
5558 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5559 udelay(32);
5560 }
5561 tmp |= SBI_SSCCTL_DISABLE;
5562 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5563 }
5564
5565 mutex_unlock(&dev_priv->dpio_lock);
5566}
5567
bf8fa3d3
PZ		 5568static void lpt_init_pch_refclk(struct drm_device *dev)
5569{
5570 struct drm_mode_config *mode_config = &dev->mode_config;
5571 struct intel_encoder *encoder;
5572 bool has_vga = false;
5573
5574 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5575 switch (encoder->type) {
5576 case INTEL_OUTPUT_ANALOG:
5577 has_vga = true;
5578 break;
5579 }
5580 }
5581
47701c3b
PZ		 5582 if (has_vga)
5583 lpt_enable_clkout_dp(dev, true, true);
5584 else
5585 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 5586}
5587
dde86e2d
PZ		 5588/*
5589 * Initialize reference clocks when the driver loads
5590 */
5591void intel_init_pch_refclk(struct drm_device *dev)
5592{
5593 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5594 ironlake_init_pch_refclk(dev);
5595 else if (HAS_PCH_LPT(dev))
5596 lpt_init_pch_refclk(dev);
5597}
5598
d9d444cb
JB		 5599static int ironlake_get_refclk(struct drm_crtc *crtc)
5600{
5601 struct drm_device *dev = crtc->dev;
5602 struct drm_i915_private *dev_priv = dev->dev_private;
5603 struct intel_encoder *encoder;
d9d444cb
JB		 5604 int num_connectors = 0;
5605 bool is_lvds = false;
5606
6c2b7c12 5607 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5608 switch (encoder->type) {
5609 case INTEL_OUTPUT_LVDS:
5610 is_lvds = true;
5611 break;
d9d444cb
JB		 5612 }
5613 num_connectors++;
5614 }
5615
5616 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5617 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5618 dev_priv->vbt.lvds_ssc_freq);
5619 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5620 }
5621
5622 return 120000;
5623}
5624
6ff93609 5625static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5626{
c8203565 5627 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5628 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5629 int pipe = intel_crtc->pipe;
c8203565
PZ		 5630 uint32_t val;
5631
78114071 5632 val = 0;
c8203565 5633
965e0c48 5634 switch (intel_crtc->config.pipe_bpp) {
c8203565 5635 case 18:
dfd07d72 5636 val |= PIPECONF_6BPC;
c8203565
PZ		 5637 break;
5638 case 24:
dfd07d72 5639 val |= PIPECONF_8BPC;
c8203565
PZ		 5640 break;
5641 case 30:
dfd07d72 5642 val |= PIPECONF_10BPC;
c8203565
PZ		 5643 break;
5644 case 36:
dfd07d72 5645 val |= PIPECONF_12BPC;
c8203565
PZ		 5646 break;
5647 default:
cc769b62
PZ		 5648 /* Case prevented by intel_choose_pipe_bpp_dither. */
5649 BUG();
c8203565
PZ		 5650 }
5651
d8b32247 5652 if (intel_crtc->config.dither)
c8203565
PZ		 5653 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5654
6ff93609 5655 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5656 val |= PIPECONF_INTERLACED_ILK;
5657 else
5658 val |= PIPECONF_PROGRESSIVE;
5659
50f3b016 5660 if (intel_crtc->config.limited_color_range)
3685a8f3 5661 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 5662
c8203565
PZ		 5663 I915_WRITE(PIPECONF(pipe), val);
5664 POSTING_READ(PIPECONF(pipe));
5665}
5666
86d3efce
VS		 5667/*
5668 * Set up the pipe CSC unit.
5669 *
5670 * Currently only full range RGB to limited range RGB conversion
5671 * is supported, but eventually this should handle various
5672 * RGB<->YCbCr scenarios as well.
5673 */
50f3b016 5674static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5675{
5676 struct drm_device *dev = crtc->dev;
5677 struct drm_i915_private *dev_priv = dev->dev_private;
5678 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5679 int pipe = intel_crtc->pipe;
5680 uint16_t coeff = 0x7800; /* 1.0 */
5681
5682 /*
5683 * TODO: Check what kind of values actually come out of the pipe
5684 * with these coeff/postoff values and adjust to get the best
5685 * accuracy. Perhaps we even need to take the bpc value into
5686 * consideration.
5687 */
5688
50f3b016 5689 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5690 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5691
5692 /*
5693 * GY/GU and RY/RU should be the other way around according
5694 * to BSpec, but reality doesn't agree. Just set them up in
5695 * a way that results in the correct picture.
5696 */
5697 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5698 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5699
5700 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5701 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5702
5703 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5704 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5705
5706 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5707 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5708 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5709
5710 if (INTEL_INFO(dev)->gen > 6) {
5711 uint16_t postoff = 0;
5712
50f3b016 5713 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5714 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5715
5716 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5717 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5718 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5719
5720 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5721 } else {
5722 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5723
50f3b016 5724 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5725 mode |= CSC_BLACK_SCREEN_OFFSET;
5726
5727 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5728 }
5729}
5730
6ff93609 5731static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5732{
5733 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5734 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5735 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5736 uint32_t val;
5737
3eff4faa 5738 val = 0;
ee2b0b38 5739
d8b32247 5740 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5741 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5742
6ff93609 5743 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5744 val |= PIPECONF_INTERLACED_ILK;
5745 else
5746 val |= PIPECONF_PROGRESSIVE;
5747
702e7a56
PZ		 5748 I915_WRITE(PIPECONF(cpu_transcoder), val);
5749 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 5750
5751 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5752 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
ee2b0b38
PZ		 5753}
5754
6591c6e4 5755static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ		 5756 intel_clock_t *clock,
5757 bool *has_reduced_clock,
5758 intel_clock_t *reduced_clock)
5759{
5760 struct drm_device *dev = crtc->dev;
5761 struct drm_i915_private *dev_priv = dev->dev_private;
5762 struct intel_encoder *intel_encoder;
5763 int refclk;
d4906093 5764 const intel_limit_t *limit;
a16af721 5765 bool ret, is_lvds = false;
79e53945 5766
6591c6e4
PZ		 5767 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5768 switch (intel_encoder->type) {
79e53945
JB		 5769 case INTEL_OUTPUT_LVDS:
5770 is_lvds = true;
5771 break;
79e53945
JB		 5772 }
5773 }
5774
d9d444cb 5775 refclk = ironlake_get_refclk(crtc);
79e53945 5776
d4906093
ML		 5777 /*
5778 * Returns a set of divisors for the desired target clock with the given
5779 * refclk, or FALSE. The returned values represent the clock equation:
5780 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5781 */
1b894b59 5782 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 5783 ret = dev_priv->display.find_dpll(limit, crtc,
5784 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 5785 refclk, NULL, clock);
6591c6e4
PZ		 5786 if (!ret)
5787 return false;
cda4b7d3 5788
ddc9003c 5789 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5790 /*
5791 * Ensure we match the reduced clock's P to the target clock.
5792 * If the clocks don't match, we can't switch the display clock
5793 * by using the FP0/FP1. In such case we will disable the LVDS
5794 * downclock feature.
5795 */
ee9300bb
DV		 5796 *has_reduced_clock =
5797 dev_priv->display.find_dpll(limit, crtc,
5798 dev_priv->lvds_downclock,
5799 refclk, clock,
5800 reduced_clock);
652c393a 5801 }
61e9653f 5802
6591c6e4
PZ		 5803 return true;
5804}
5805
01a415fd
DV		 5806static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5807{
5808 struct drm_i915_private *dev_priv = dev->dev_private;
5809 uint32_t temp;
5810
5811 temp = I915_READ(SOUTH_CHICKEN1);
5812 if (temp & FDI_BC_BIFURCATION_SELECT)
5813 return;
5814
5815 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5816 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5817
5818 temp |= FDI_BC_BIFURCATION_SELECT;
5819 DRM_DEBUG_KMS("enabling fdi C rx\n");
5820 I915_WRITE(SOUTH_CHICKEN1, temp);
5821 POSTING_READ(SOUTH_CHICKEN1);
5822}
5823
ebfd86fd 5824static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
01a415fd
DV		 5825{
5826 struct drm_device *dev = intel_crtc->base.dev;
5827 struct drm_i915_private *dev_priv = dev->dev_private;
01a415fd
DV		 5828
5829 switch (intel_crtc->pipe) {
5830 case PIPE_A:
ebfd86fd 5831 break;
01a415fd 5832 case PIPE_B:
ebfd86fd 5833 if (intel_crtc->config.fdi_lanes > 2)
01a415fd
DV		 5834 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5835 else
5836 cpt_enable_fdi_bc_bifurcation(dev);
5837
ebfd86fd 5838 break;
01a415fd 5839 case PIPE_C:
01a415fd
DV		 5840 cpt_enable_fdi_bc_bifurcation(dev);
5841
ebfd86fd 5842 break;
01a415fd
DV		 5843 default:
5844 BUG();
5845 }
5846}
5847
d4b1931c
PZ		 5848int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5849{
5850 /*
5851 * Account for spread spectrum to avoid
5852 * oversubscribing the link. Max center spread
5853 * is 2.5%; use 5% for safety's sake.
5854 */
5855 u32 bps = target_clock * bpp * 21 / 20;
5856 return bps / (link_bw * 8) + 1;
5857}
5858
7429e9d4 5859static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 5860{
7429e9d4 5861 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 5862}
5863
de13a2e3 5864static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5865 u32 *fp,
9a7c7890 5866 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5867{
de13a2e3 5868 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5869 struct drm_device *dev = crtc->dev;
5870 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5871 struct intel_encoder *intel_encoder;
5872 uint32_t dpll;
6cc5f341 5873 int factor, num_connectors = 0;
09ede541 5874 bool is_lvds = false, is_sdvo = false;
79e53945 5875
de13a2e3
PZ		 5876 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5877 switch (intel_encoder->type) {
79e53945
JB		 5878 case INTEL_OUTPUT_LVDS:
5879 is_lvds = true;
5880 break;
5881 case INTEL_OUTPUT_SDVO:
7d57382e 5882 case INTEL_OUTPUT_HDMI:
79e53945 5883 is_sdvo = true;
79e53945 5884 break;
79e53945 5885 }
43565a06 5886
c751ce4f 5887 num_connectors++;
79e53945 5888 }
79e53945 5889
c1858123 5890 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5891 factor = 21;
5892 if (is_lvds) {
5893 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5894 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5895 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5896 factor = 25;
09ede541 5897 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5898 factor = 20;
c1858123 5899
7429e9d4 5900 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5901 *fp |= FP_CB_TUNE;
2c07245f 5902
9a7c7890
DV		 5903 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5904 *fp2 |= FP_CB_TUNE;
5905
5eddb70b 5906 dpll = 0;
2c07245f 5907
a07d6787
EA		 5908 if (is_lvds)
5909 dpll |= DPLLB_MODE_LVDS;
5910 else
5911 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 5912
ef1b460d
DV		 5913 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5914 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 5915
5916 if (is_sdvo)
4a33e48d 5917 dpll |= DPLL_SDVO_HIGH_SPEED;
9566e9af 5918 if (intel_crtc->config.has_dp_encoder)
4a33e48d 5919 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 5920
a07d6787 5921 /* compute bitmask from p1 value */
7429e9d4 5922 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5923 /* also FPA1 */
7429e9d4 5924 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5925
7429e9d4 5926 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5927 case 5:
5928 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5929 break;
5930 case 7:
5931 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5932 break;
5933 case 10:
5934 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5935 break;
5936 case 14:
5937 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5938 break;
79e53945
JB		 5939 }
5940
b4c09f3b 5941 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5942 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5943 else
5944 dpll |= PLL_REF_INPUT_DREFCLK;
5945
959e16d6 5946 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 5947}
5948
5949static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5950 int x, int y,
5951 struct drm_framebuffer *fb)
5952{
5953 struct drm_device *dev = crtc->dev;
5954 struct drm_i915_private *dev_priv = dev->dev_private;
5955 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5956 int pipe = intel_crtc->pipe;
5957 int plane = intel_crtc->plane;
5958 int num_connectors = 0;
5959 intel_clock_t clock, reduced_clock;
cbbab5bd 5960 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5961 bool ok, has_reduced_clock = false;
8b47047b 5962 bool is_lvds = false;
de13a2e3 5963 struct intel_encoder *encoder;
e2b78267 5964 struct intel_shared_dpll *pll;
de13a2e3 5965 int ret;
de13a2e3
PZ		 5966
5967 for_each_encoder_on_crtc(dev, crtc, encoder) {
5968 switch (encoder->type) {
5969 case INTEL_OUTPUT_LVDS:
5970 is_lvds = true;
5971 break;
de13a2e3
PZ		 5972 }
5973
5974 num_connectors++;
a07d6787 5975 }
79e53945 5976
5dc5298b
PZ		 5977 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5978 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5979
ff9a6750 5980 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 5981 &has_reduced_clock, &reduced_clock);
ee9300bb 5982 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 5983 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5984 return -EINVAL;
79e53945 5985 }
f47709a9
DV		 5986 /* Compat-code for transition, will disappear. */
5987 if (!intel_crtc->config.clock_set) {
5988 intel_crtc->config.dpll.n = clock.n;
5989 intel_crtc->config.dpll.m1 = clock.m1;
5990 intel_crtc->config.dpll.m2 = clock.m2;
5991 intel_crtc->config.dpll.p1 = clock.p1;
5992 intel_crtc->config.dpll.p2 = clock.p2;
5993 }
79e53945 5994
5dc5298b 5995 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5996 if (intel_crtc->config.has_pch_encoder) {
7429e9d4 5997 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5998 if (has_reduced_clock)
7429e9d4 5999 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 6000
7429e9d4 6001 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 6002 &fp, &reduced_clock,
6003 has_reduced_clock ? &fp2 : NULL);
6004
959e16d6 6005 intel_crtc->config.dpll_hw_state.dpll = dpll;
66e985c0
DV		 6006 intel_crtc->config.dpll_hw_state.fp0 = fp;
6007 if (has_reduced_clock)
6008 intel_crtc->config.dpll_hw_state.fp1 = fp2;
6009 else
6010 intel_crtc->config.dpll_hw_state.fp1 = fp;
6011
b89a1d39 6012 pll = intel_get_shared_dpll(intel_crtc);
ee7b9f93 6013 if (pll == NULL) {
84f44ce7
VS		 6014 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6015 pipe_name(pipe));
4b645f14
JB		 6016 return -EINVAL;
6017 }
ee7b9f93 6018 } else
e72f9fbf 6019 intel_put_shared_dpll(intel_crtc);
79e53945 6020
03afc4a2
DV		 6021 if (intel_crtc->config.has_dp_encoder)
6022 intel_dp_set_m_n(intel_crtc);
79e53945 6023
bcd644e0
DV		 6024 if (is_lvds && has_reduced_clock && i915_powersave)
6025 intel_crtc->lowfreq_avail = true;
6026 else
6027 intel_crtc->lowfreq_avail = false;
e2b78267
DV		 6028
6029 if (intel_crtc->config.has_pch_encoder) {
6030 pll = intel_crtc_to_shared_dpll(intel_crtc);
6031
652c393a
JB		 6032 }
6033
8a654f3b 6034 intel_set_pipe_timings(intel_crtc);
5eddb70b 6035
ca3a0ff8 6036 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 6037 intel_cpu_transcoder_set_m_n(intel_crtc,
6038 &intel_crtc->config.fdi_m_n);
6039 }
2c07245f 6040
ebfd86fd
DV		 6041 if (IS_IVYBRIDGE(dev))
6042 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
79e53945 6043
6ff93609 6044 ironlake_set_pipeconf(crtc);
79e53945 6045
a1f9e77e
PZ		 6046 /* Set up the display plane register */
6047 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 6048 POSTING_READ(DSPCNTR(plane));
79e53945 6049
94352cf9 6050 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd 6051
1857e1da 6052 return ret;
79e53945
JB		 6053}
6054
eb14cb74
VS		 6055static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6056 struct intel_link_m_n *m_n)
6057{
6058 struct drm_device *dev = crtc->base.dev;
6059 struct drm_i915_private *dev_priv = dev->dev_private;
6060 enum pipe pipe = crtc->pipe;
6061
6062 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6063 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6064 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6065 & ~TU_SIZE_MASK;
6066 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6067 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6068 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6069}
6070
6071static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6072 enum transcoder transcoder,
6073 struct intel_link_m_n *m_n)
72419203
DV		 6074{
6075 struct drm_device *dev = crtc->base.dev;
6076 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 6077 enum pipe pipe = crtc->pipe;
72419203 6078
eb14cb74
VS		 6079 if (INTEL_INFO(dev)->gen >= 5) {
6080 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6081 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6082 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6083 & ~TU_SIZE_MASK;
6084 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6085 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6086 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6087 } else {
6088 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6089 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6090 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6091 & ~TU_SIZE_MASK;
6092 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6093 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6094 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6095 }
6096}
6097
6098void intel_dp_get_m_n(struct intel_crtc *crtc,
6099 struct intel_crtc_config *pipe_config)
6100{
6101 if (crtc->config.has_pch_encoder)
6102 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6103 else
6104 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6105 &pipe_config->dp_m_n);
6106}
72419203 6107
eb14cb74
VS		 6108static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6109 struct intel_crtc_config *pipe_config)
6110{
6111 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6112 &pipe_config->fdi_m_n);
72419203
DV		 6113}
6114
2fa2fe9a
DV		 6115static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6116 struct intel_crtc_config *pipe_config)
6117{
6118 struct drm_device *dev = crtc->base.dev;
6119 struct drm_i915_private *dev_priv = dev->dev_private;
6120 uint32_t tmp;
6121
6122 tmp = I915_READ(PF_CTL(crtc->pipe));
6123
6124 if (tmp & PF_ENABLE) {
fd4daa9c 6125 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 6126 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6127 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 6128
6129 /* We currently do not free assignements of panel fitters on
6130 * ivb/hsw (since we don't use the higher upscaling modes which
6131 * differentiates them) so just WARN about this case for now. */
6132 if (IS_GEN7(dev)) {
6133 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6134 PF_PIPE_SEL_IVB(crtc->pipe));
6135 }
2fa2fe9a 6136 }
79e53945
JB		 6137}
6138
0e8ffe1b
DV		 6139static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6140 struct intel_crtc_config *pipe_config)
6141{
6142 struct drm_device *dev = crtc->base.dev;
6143 struct drm_i915_private *dev_priv = dev->dev_private;
6144 uint32_t tmp;
6145
e143a21c 6146 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 6147 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 6148
0e8ffe1b
DV		 6149 tmp = I915_READ(PIPECONF(crtc->pipe));
6150 if (!(tmp & PIPECONF_ENABLE))
6151 return false;
6152
42571aef
VS		 6153 switch (tmp & PIPECONF_BPC_MASK) {
6154 case PIPECONF_6BPC:
6155 pipe_config->pipe_bpp = 18;
6156 break;
6157 case PIPECONF_8BPC:
6158 pipe_config->pipe_bpp = 24;
6159 break;
6160 case PIPECONF_10BPC:
6161 pipe_config->pipe_bpp = 30;
6162 break;
6163 case PIPECONF_12BPC:
6164 pipe_config->pipe_bpp = 36;
6165 break;
6166 default:
6167 break;
6168 }
6169
ab9412ba 6170 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 6171 struct intel_shared_dpll *pll;
6172
88adfff1
DV		 6173 pipe_config->has_pch_encoder = true;
6174
627eb5a3
DV		 6175 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6176 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6177 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6178
6179 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 6180
c0d43d62 6181 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 6182 pipe_config->shared_dpll =
6183 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 6184 } else {
6185 tmp = I915_READ(PCH_DPLL_SEL);
6186 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6187 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6188 else
6189 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6190 }
66e985c0
DV		 6191
6192 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6193
6194 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6195 &pipe_config->dpll_hw_state));
c93f54cf
DV		 6196
6197 tmp = pipe_config->dpll_hw_state.dpll;
6198 pipe_config->pixel_multiplier =
6199 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6200 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 6201
6202 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 6203 } else {
6204 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 6205 }
6206
1bd1bd80
DV		 6207 intel_get_pipe_timings(crtc, pipe_config);
6208
2fa2fe9a
DV		 6209 ironlake_get_pfit_config(crtc, pipe_config);
6210
0e8ffe1b
DV		 6211 return true;
6212}
6213
be256dc7
PZ		 6214static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6215{
6216 struct drm_device *dev = dev_priv->dev;
6217 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6218 struct intel_crtc *crtc;
6219 unsigned long irqflags;
bd633a7c 6220 uint32_t val;
be256dc7
PZ		 6221
6222 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6223 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
6224 pipe_name(crtc->pipe));
6225
6226 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6227 WARN(plls->spll_refcount, "SPLL enabled\n");
6228 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6229 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6230 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6231 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6232 "CPU PWM1 enabled\n");
6233 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6234 "CPU PWM2 enabled\n");
6235 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6236 "PCH PWM1 enabled\n");
6237 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6238 "Utility pin enabled\n");
6239 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6240
6241 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6242 val = I915_READ(DEIMR);
6243 WARN((val & ~DE_PCH_EVENT_IVB) != val,
6244 "Unexpected DEIMR bits enabled: 0x%x\n", val);
6245 val = I915_READ(SDEIMR);
bd633a7c 6246 WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
be256dc7
PZ		 6247 "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6248 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6249}
6250
6251/*
6252 * This function implements pieces of two sequences from BSpec:
6253 * - Sequence for display software to disable LCPLL
6254 * - Sequence for display software to allow package C8+
6255 * The steps implemented here are just the steps that actually touch the LCPLL
6256 * register. Callers should take care of disabling all the display engine
6257 * functions, doing the mode unset, fixing interrupts, etc.
6258 */
6ff58d53
PZ		 6259static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6260 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 6261{
6262 uint32_t val;
6263
6264 assert_can_disable_lcpll(dev_priv);
6265
6266 val = I915_READ(LCPLL_CTL);
6267
6268 if (switch_to_fclk) {
6269 val |= LCPLL_CD_SOURCE_FCLK;
6270 I915_WRITE(LCPLL_CTL, val);
6271
6272 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6273 LCPLL_CD_SOURCE_FCLK_DONE, 1))
6274 DRM_ERROR("Switching to FCLK failed\n");
6275
6276 val = I915_READ(LCPLL_CTL);
6277 }
6278
6279 val |= LCPLL_PLL_DISABLE;
6280 I915_WRITE(LCPLL_CTL, val);
6281 POSTING_READ(LCPLL_CTL);
6282
6283 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6284 DRM_ERROR("LCPLL still locked\n");
6285
6286 val = I915_READ(D_COMP);
6287 val |= D_COMP_COMP_DISABLE;
515b2392
PZ		 6288 mutex_lock(&dev_priv->rps.hw_lock);
6289 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6290 DRM_ERROR("Failed to disable D_COMP\n");
6291 mutex_unlock(&dev_priv->rps.hw_lock);
be256dc7
PZ		 6292 POSTING_READ(D_COMP);
6293 ndelay(100);
6294
6295 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6296 DRM_ERROR("D_COMP RCOMP still in progress\n");
6297
6298 if (allow_power_down) {
6299 val = I915_READ(LCPLL_CTL);
6300 val |= LCPLL_POWER_DOWN_ALLOW;
6301 I915_WRITE(LCPLL_CTL, val);
6302 POSTING_READ(LCPLL_CTL);
6303 }
6304}
6305
6306/*
6307 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6308 * source.
6309 */
6ff58d53 6310static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 6311{
6312 uint32_t val;
6313
6314 val = I915_READ(LCPLL_CTL);
6315
6316 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6317 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6318 return;
6319
215733fa
PZ		 6320 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6321 * we'll hang the machine! */
6322 dev_priv->uncore.funcs.force_wake_get(dev_priv);
6323
be256dc7
PZ		 6324 if (val & LCPLL_POWER_DOWN_ALLOW) {
6325 val &= ~LCPLL_POWER_DOWN_ALLOW;
6326 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 6327 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 6328 }
6329
6330 val = I915_READ(D_COMP);
6331 val |= D_COMP_COMP_FORCE;
6332 val &= ~D_COMP_COMP_DISABLE;
515b2392
PZ		 6333 mutex_lock(&dev_priv->rps.hw_lock);
6334 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6335 DRM_ERROR("Failed to enable D_COMP\n");
6336 mutex_unlock(&dev_priv->rps.hw_lock);
35d8f2eb 6337 POSTING_READ(D_COMP);
be256dc7
PZ		 6338
6339 val = I915_READ(LCPLL_CTL);
6340 val &= ~LCPLL_PLL_DISABLE;
6341 I915_WRITE(LCPLL_CTL, val);
6342
6343 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6344 DRM_ERROR("LCPLL not locked yet\n");
6345
6346 if (val & LCPLL_CD_SOURCE_FCLK) {
6347 val = I915_READ(LCPLL_CTL);
6348 val &= ~LCPLL_CD_SOURCE_FCLK;
6349 I915_WRITE(LCPLL_CTL, val);
6350
6351 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6352 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6353 DRM_ERROR("Switching back to LCPLL failed\n");
6354 }
215733fa
PZ		 6355
6356 dev_priv->uncore.funcs.force_wake_put(dev_priv);
be256dc7
PZ		 6357}
6358
c67a470b
PZ		 6359void hsw_enable_pc8_work(struct work_struct *__work)
6360{
6361 struct drm_i915_private *dev_priv =
6362 container_of(to_delayed_work(__work), struct drm_i915_private,
6363 pc8.enable_work);
6364 struct drm_device *dev = dev_priv->dev;
6365 uint32_t val;
6366
6367 if (dev_priv->pc8.enabled)
6368 return;
6369
6370 DRM_DEBUG_KMS("Enabling package C8+\n");
6371
6372 dev_priv->pc8.enabled = true;
6373
6374 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6375 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6376 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6377 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6378 }
6379
6380 lpt_disable_clkout_dp(dev);
6381 hsw_pc8_disable_interrupts(dev);
6382 hsw_disable_lcpll(dev_priv, true, true);
6383}
6384
6385static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6386{
6387 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6388 WARN(dev_priv->pc8.disable_count < 1,
6389 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6390
6391 dev_priv->pc8.disable_count--;
6392 if (dev_priv->pc8.disable_count != 0)
6393 return;
6394
6395 schedule_delayed_work(&dev_priv->pc8.enable_work,
90058745 6396 msecs_to_jiffies(i915_pc8_timeout));
c67a470b
PZ		 6397}
6398
6399static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6400{
6401 struct drm_device *dev = dev_priv->dev;
6402 uint32_t val;
6403
6404 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6405 WARN(dev_priv->pc8.disable_count < 0,
6406 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6407
6408 dev_priv->pc8.disable_count++;
6409 if (dev_priv->pc8.disable_count != 1)
6410 return;
6411
6412 cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6413 if (!dev_priv->pc8.enabled)
6414 return;
6415
6416 DRM_DEBUG_KMS("Disabling package C8+\n");
6417
6418 hsw_restore_lcpll(dev_priv);
6419 hsw_pc8_restore_interrupts(dev);
6420 lpt_init_pch_refclk(dev);
6421
6422 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6423 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6424 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6425 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6426 }
6427
6428 intel_prepare_ddi(dev);
6429 i915_gem_init_swizzling(dev);
6430 mutex_lock(&dev_priv->rps.hw_lock);
6431 gen6_update_ring_freq(dev);
6432 mutex_unlock(&dev_priv->rps.hw_lock);
6433 dev_priv->pc8.enabled = false;
6434}
6435
6436void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6437{
6438 mutex_lock(&dev_priv->pc8.lock);
6439 __hsw_enable_package_c8(dev_priv);
6440 mutex_unlock(&dev_priv->pc8.lock);
6441}
6442
6443void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6444{
6445 mutex_lock(&dev_priv->pc8.lock);
6446 __hsw_disable_package_c8(dev_priv);
6447 mutex_unlock(&dev_priv->pc8.lock);
6448}
6449
6450static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6451{
6452 struct drm_device *dev = dev_priv->dev;
6453 struct intel_crtc *crtc;
6454 uint32_t val;
6455
6456 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6457 if (crtc->base.enabled)
6458 return false;
6459
6460 /* This case is still possible since we have the i915.disable_power_well
6461 * parameter and also the KVMr or something else might be requesting the
6462 * power well. */
6463 val = I915_READ(HSW_PWR_WELL_DRIVER);
6464 if (val != 0) {
6465 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6466 return false;
6467 }
6468
6469 return true;
6470}
6471
6472/* Since we're called from modeset_global_resources there's no way to
6473 * symmetrically increase and decrease the refcount, so we use
6474 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6475 * or not.
6476 */
6477static void hsw_update_package_c8(struct drm_device *dev)
6478{
6479 struct drm_i915_private *dev_priv = dev->dev_private;
6480 bool allow;
6481
6482 if (!i915_enable_pc8)
6483 return;
6484
6485 mutex_lock(&dev_priv->pc8.lock);
6486
6487 allow = hsw_can_enable_package_c8(dev_priv);
6488
6489 if (allow == dev_priv->pc8.requirements_met)
6490 goto done;
6491
6492 dev_priv->pc8.requirements_met = allow;
6493
6494 if (allow)
6495 __hsw_enable_package_c8(dev_priv);
6496 else
6497 __hsw_disable_package_c8(dev_priv);
6498
6499done:
6500 mutex_unlock(&dev_priv->pc8.lock);
6501}
6502
6503static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6504{
6505 if (!dev_priv->pc8.gpu_idle) {
6506 dev_priv->pc8.gpu_idle = true;
6507 hsw_enable_package_c8(dev_priv);
6508 }
6509}
6510
6511static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6512{
6513 if (dev_priv->pc8.gpu_idle) {
6514 dev_priv->pc8.gpu_idle = false;
6515 hsw_disable_package_c8(dev_priv);
6516 }
be256dc7
PZ		 6517}
6518
d6dd9eb1
DV		 6519static void haswell_modeset_global_resources(struct drm_device *dev)
6520{
d6dd9eb1
DV		 6521 bool enable = false;
6522 struct intel_crtc *crtc;
d6dd9eb1
DV		 6523
6524 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 6525 if (!crtc->base.enabled)
6526 continue;
d6dd9eb1 6527
fd4daa9c 6528 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.enabled ||
e7a639c4 6529 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 6530 enable = true;
6531 }
6532
d6dd9eb1 6533 intel_set_power_well(dev, enable);
c67a470b
PZ		 6534
6535 hsw_update_package_c8(dev);
d6dd9eb1
DV		 6536}
6537
09b4ddf9 6538static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 6539 int x, int y,
6540 struct drm_framebuffer *fb)
6541{
6542 struct drm_device *dev = crtc->dev;
6543 struct drm_i915_private *dev_priv = dev->dev_private;
6544 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 6545 int plane = intel_crtc->plane;
09b4ddf9 6546 int ret;
09b4ddf9 6547
ff9a6750 6548 if (!intel_ddi_pll_mode_set(crtc))
6441ab5f
PZ		 6549 return -EINVAL;
6550
03afc4a2
DV		 6551 if (intel_crtc->config.has_dp_encoder)
6552 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 6553
6554 intel_crtc->lowfreq_avail = false;
09b4ddf9 6555
8a654f3b 6556 intel_set_pipe_timings(intel_crtc);
09b4ddf9 6557
ca3a0ff8 6558 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 6559 intel_cpu_transcoder_set_m_n(intel_crtc,
6560 &intel_crtc->config.fdi_m_n);
6561 }
09b4ddf9 6562
6ff93609 6563 haswell_set_pipeconf(crtc);
09b4ddf9 6564
50f3b016 6565 intel_set_pipe_csc(crtc);
86d3efce 6566
09b4ddf9 6567 /* Set up the display plane register */
86d3efce 6568 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 6569 POSTING_READ(DSPCNTR(plane));
6570
6571 ret = intel_pipe_set_base(crtc, x, y, fb);
6572
1f803ee5 6573 return ret;
79e53945
JB		 6574}
6575
0e8ffe1b
DV		 6576static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6577 struct intel_crtc_config *pipe_config)
6578{
6579 struct drm_device *dev = crtc->base.dev;
6580 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 6581 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 6582 uint32_t tmp;
6583
e143a21c 6584 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 6585 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6586
eccb140b
DV		 6587 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6588 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6589 enum pipe trans_edp_pipe;
6590 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6591 default:
6592 WARN(1, "unknown pipe linked to edp transcoder\n");
6593 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6594 case TRANS_DDI_EDP_INPUT_A_ON:
6595 trans_edp_pipe = PIPE_A;
6596 break;
6597 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6598 trans_edp_pipe = PIPE_B;
6599 break;
6600 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6601 trans_edp_pipe = PIPE_C;
6602 break;
6603 }
6604
6605 if (trans_edp_pipe == crtc->pipe)
6606 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6607 }
6608
b97186f0 6609 if (!intel_display_power_enabled(dev,
eccb140b 6610 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 6611 return false;
6612
eccb140b 6613 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 6614 if (!(tmp & PIPECONF_ENABLE))
6615 return false;
6616
88adfff1 6617 /*
f196e6be 6618 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 6619 * DDI E. So just check whether this pipe is wired to DDI E and whether
6620 * the PCH transcoder is on.
6621 */
eccb140b 6622 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 6623 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 6624 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 6625 pipe_config->has_pch_encoder = true;
6626
627eb5a3
DV		 6627 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6628 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6629 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6630
6631 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 6632 }
6633
1bd1bd80
DV		 6634 intel_get_pipe_timings(crtc, pipe_config);
6635
2fa2fe9a
DV		 6636 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6637 if (intel_display_power_enabled(dev, pfit_domain))
6638 ironlake_get_pfit_config(crtc, pipe_config);
88adfff1 6639
42db64ef
PZ		 6640 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6641 (I915_READ(IPS_CTL) & IPS_ENABLE);
6642
6c49f241
DV		 6643 pipe_config->pixel_multiplier = 1;
6644
0e8ffe1b
DV		 6645 return true;
6646}
6647
f564048e 6648static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6649 int x, int y,
94352cf9 6650 struct drm_framebuffer *fb)
f564048e
EA		 6651{
6652 struct drm_device *dev = crtc->dev;
6653 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19 6654 struct intel_encoder *encoder;
0b701d27 6655 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 6656 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6657 int pipe = intel_crtc->pipe;
f564048e
EA		 6658 int ret;
6659
0b701d27 6660 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6661
b8cecdf5
DV		 6662 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6663
79e53945 6664 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6665
9256aa19
DV		 6666 if (ret != 0)
6667 return ret;
6668
6669 for_each_encoder_on_crtc(dev, crtc, encoder) {
6670 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6671 encoder->base.base.id,
6672 drm_get_encoder_name(&encoder->base),
6673 mode->base.id, mode->name);
36f2d1f1 6674 encoder->mode_set(encoder);
9256aa19
DV		 6675 }
6676
6677 return 0;
79e53945
JB		 6678}
6679
3a9627f4
WF		 6680static bool intel_eld_uptodate(struct drm_connector *connector,
6681 int reg_eldv, uint32_t bits_eldv,
6682 int reg_elda, uint32_t bits_elda,
6683 int reg_edid)
6684{
6685 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6686 uint8_t *eld = connector->eld;
6687 uint32_t i;
6688
6689 i = I915_READ(reg_eldv);
6690 i &= bits_eldv;
6691
6692 if (!eld[0])
6693 return !i;
6694
6695 if (!i)
6696 return false;
6697
6698 i = I915_READ(reg_elda);
6699 i &= ~bits_elda;
6700 I915_WRITE(reg_elda, i);
6701
6702 for (i = 0; i < eld[2]; i++)
6703 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6704 return false;
6705
6706 return true;
6707}
6708
e0dac65e
WF		 6709static void g4x_write_eld(struct drm_connector *connector,
6710 struct drm_crtc *crtc)
6711{
6712 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6713 uint8_t *eld = connector->eld;
6714 uint32_t eldv;
6715 uint32_t len;
6716 uint32_t i;
6717
6718 i = I915_READ(G4X_AUD_VID_DID);
6719
6720 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6721 eldv = G4X_ELDV_DEVCL_DEVBLC;
6722 else
6723 eldv = G4X_ELDV_DEVCTG;
6724
3a9627f4
WF		 6725 if (intel_eld_uptodate(connector,
6726 G4X_AUD_CNTL_ST, eldv,
6727 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6728 G4X_HDMIW_HDMIEDID))
6729 return;
6730
e0dac65e
WF		 6731 i = I915_READ(G4X_AUD_CNTL_ST);
6732 i &= ~(eldv | G4X_ELD_ADDR);
6733 len = (i >> 9) & 0x1f; /* ELD buffer size */
6734 I915_WRITE(G4X_AUD_CNTL_ST, i);
6735
6736 if (!eld[0])
6737 return;
6738
6739 len = min_t(uint8_t, eld[2], len);
6740 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6741 for (i = 0; i < len; i++)
6742 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6743
6744 i = I915_READ(G4X_AUD_CNTL_ST);
6745 i |= eldv;
6746 I915_WRITE(G4X_AUD_CNTL_ST, i);
6747}
6748
83358c85
WX		 6749static void haswell_write_eld(struct drm_connector *connector,
6750 struct drm_crtc *crtc)
6751{
6752 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6753 uint8_t *eld = connector->eld;
6754 struct drm_device *dev = crtc->dev;
7b9f35a6 6755 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6756 uint32_t eldv;
6757 uint32_t i;
6758 int len;
6759 int pipe = to_intel_crtc(crtc)->pipe;
6760 int tmp;
6761
6762 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6763 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6764 int aud_config = HSW_AUD_CFG(pipe);
6765 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6766
6767
6768 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6769
6770 /* Audio output enable */
6771 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6772 tmp = I915_READ(aud_cntrl_st2);
6773 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6774 I915_WRITE(aud_cntrl_st2, tmp);
6775
6776 /* Wait for 1 vertical blank */
6777 intel_wait_for_vblank(dev, pipe);
6778
6779 /* Set ELD valid state */
6780 tmp = I915_READ(aud_cntrl_st2);
7e7cb34f 6781 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
83358c85
WX		 6782 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6783 I915_WRITE(aud_cntrl_st2, tmp);
6784 tmp = I915_READ(aud_cntrl_st2);
7e7cb34f 6785 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
83358c85
WX		 6786
6787 /* Enable HDMI mode */
6788 tmp = I915_READ(aud_config);
7e7cb34f 6789 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
83358c85
WX		 6790 /* clear N_programing_enable and N_value_index */
6791 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6792 I915_WRITE(aud_config, tmp);
6793
6794 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6795
6796 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6797 intel_crtc->eld_vld = true;
83358c85
WX		 6798
6799 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6800 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6801 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6802 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6803 } else
6804 I915_WRITE(aud_config, 0);
6805
6806 if (intel_eld_uptodate(connector,
6807 aud_cntrl_st2, eldv,
6808 aud_cntl_st, IBX_ELD_ADDRESS,
6809 hdmiw_hdmiedid))
6810 return;
6811
6812 i = I915_READ(aud_cntrl_st2);
6813 i &= ~eldv;
6814 I915_WRITE(aud_cntrl_st2, i);
6815
6816 if (!eld[0])
6817 return;
6818
6819 i = I915_READ(aud_cntl_st);
6820 i &= ~IBX_ELD_ADDRESS;
6821 I915_WRITE(aud_cntl_st, i);
6822 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6823 DRM_DEBUG_DRIVER("port num:%d\n", i);
6824
6825 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6826 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6827 for (i = 0; i < len; i++)
6828 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6829
6830 i = I915_READ(aud_cntrl_st2);
6831 i |= eldv;
6832 I915_WRITE(aud_cntrl_st2, i);
6833
6834}
6835
e0dac65e
WF		 6836static void ironlake_write_eld(struct drm_connector *connector,
6837 struct drm_crtc *crtc)
6838{
6839 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6840 uint8_t *eld = connector->eld;
6841 uint32_t eldv;
6842 uint32_t i;
6843 int len;
6844 int hdmiw_hdmiedid;
b6daa025 6845 int aud_config;
e0dac65e
WF		 6846 int aud_cntl_st;
6847 int aud_cntrl_st2;
9b138a83 6848 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6849
b3f33cbf 6850 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6851 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6852 aud_config = IBX_AUD_CFG(pipe);
6853 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6854 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6855 } else {
9b138a83
WX		 6856 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6857 aud_config = CPT_AUD_CFG(pipe);
6858 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6859 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6860 }
6861
9b138a83 6862 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6863
6864 i = I915_READ(aud_cntl_st);
9b138a83 6865 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6866 if (!i) {
6867 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6868 /* operate blindly on all ports */
1202b4c6
WF		 6869 eldv = IBX_ELD_VALIDB;
6870 eldv |= IBX_ELD_VALIDB << 4;
6871 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6872 } else {
2582a850 6873 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6874 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6875 }
6876
3a9627f4
WF		 6877 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6878 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6879 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6880 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6881 } else
6882 I915_WRITE(aud_config, 0);
e0dac65e 6883
3a9627f4
WF		 6884 if (intel_eld_uptodate(connector,
6885 aud_cntrl_st2, eldv,
6886 aud_cntl_st, IBX_ELD_ADDRESS,
6887 hdmiw_hdmiedid))
6888 return;
6889
e0dac65e
WF		 6890 i = I915_READ(aud_cntrl_st2);
6891 i &= ~eldv;
6892 I915_WRITE(aud_cntrl_st2, i);
6893
6894 if (!eld[0])
6895 return;
6896
e0dac65e 6897 i = I915_READ(aud_cntl_st);
1202b4c6 6898 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6899 I915_WRITE(aud_cntl_st, i);
6900
6901 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6902 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6903 for (i = 0; i < len; i++)
6904 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6905
6906 i = I915_READ(aud_cntrl_st2);
6907 i |= eldv;
6908 I915_WRITE(aud_cntrl_st2, i);
6909}
6910
6911void intel_write_eld(struct drm_encoder *encoder,
6912 struct drm_display_mode *mode)
6913{
6914 struct drm_crtc *crtc = encoder->crtc;
6915 struct drm_connector *connector;
6916 struct drm_device *dev = encoder->dev;
6917 struct drm_i915_private *dev_priv = dev->dev_private;
6918
6919 connector = drm_select_eld(encoder, mode);
6920 if (!connector)
6921 return;
6922
6923 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6924 connector->base.id,
6925 drm_get_connector_name(connector),
6926 connector->encoder->base.id,
6927 drm_get_encoder_name(connector->encoder));
6928
6929 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6930
6931 if (dev_priv->display.write_eld)
6932 dev_priv->display.write_eld(connector, crtc);
6933}
6934
560b85bb
CW		 6935static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6936{
6937 struct drm_device *dev = crtc->dev;
6938 struct drm_i915_private *dev_priv = dev->dev_private;
6939 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6940 bool visible = base != 0;
6941 u32 cntl;
6942
6943 if (intel_crtc->cursor_visible == visible)
6944 return;
6945
9db4a9c7 6946 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6947 if (visible) {
6948 /* On these chipsets we can only modify the base whilst
6949 * the cursor is disabled.
6950 */
9db4a9c7 6951 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6952
6953 cntl &= ~(CURSOR_FORMAT_MASK);
6954 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6955 cntl |= CURSOR_ENABLE |
6956 CURSOR_GAMMA_ENABLE |
6957 CURSOR_FORMAT_ARGB;
6958 } else
6959 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6960 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6961
6962 intel_crtc->cursor_visible = visible;
6963}
6964
6965static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6966{
6967 struct drm_device *dev = crtc->dev;
6968 struct drm_i915_private *dev_priv = dev->dev_private;
6969 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6970 int pipe = intel_crtc->pipe;
6971 bool visible = base != 0;
6972
6973 if (intel_crtc->cursor_visible != visible) {
548f245b 6974 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6975 if (base) {
6976 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6977 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6978 cntl |= pipe << 28; /* Connect to correct pipe */
6979 } else {
6980 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6981 cntl |= CURSOR_MODE_DISABLE;
6982 }
9db4a9c7 6983 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6984
6985 intel_crtc->cursor_visible = visible;
6986 }
6987 /* and commit changes on next vblank */
9db4a9c7 6988 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6989}
6990
65a21cd6
JB		 6991static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6992{
6993 struct drm_device *dev = crtc->dev;
6994 struct drm_i915_private *dev_priv = dev->dev_private;
6995 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6996 int pipe = intel_crtc->pipe;
6997 bool visible = base != 0;
6998
6999 if (intel_crtc->cursor_visible != visible) {
7000 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7001 if (base) {
7002 cntl &= ~CURSOR_MODE;
7003 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7004 } else {
7005 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7006 cntl |= CURSOR_MODE_DISABLE;
7007 }
1f5d76db 7008 if (IS_HASWELL(dev)) {
86d3efce 7009 cntl |= CURSOR_PIPE_CSC_ENABLE;
1f5d76db
PZ		 7010 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7011 }
65a21cd6
JB		 7012 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7013
7014 intel_crtc->cursor_visible = visible;
7015 }
7016 /* and commit changes on next vblank */
7017 I915_WRITE(CURBASE_IVB(pipe), base);
7018}
7019
cda4b7d3 7020/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 7021static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7022 bool on)
cda4b7d3
CW		 7023{
7024 struct drm_device *dev = crtc->dev;
7025 struct drm_i915_private *dev_priv = dev->dev_private;
7026 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7027 int pipe = intel_crtc->pipe;
7028 int x = intel_crtc->cursor_x;
7029 int y = intel_crtc->cursor_y;
d6e4db15 7030 u32 base = 0, pos = 0;
cda4b7d3
CW		 7031 bool visible;
7032
d6e4db15 7033 if (on)
cda4b7d3 7034 base = intel_crtc->cursor_addr;
cda4b7d3 7035
d6e4db15
VS		 7036 if (x >= intel_crtc->config.pipe_src_w)
7037 base = 0;
7038
7039 if (y >= intel_crtc->config.pipe_src_h)
cda4b7d3
CW		 7040 base = 0;
7041
7042 if (x < 0) {
efc9064e 7043 if (x + intel_crtc->cursor_width <= 0)
cda4b7d3
CW		 7044 base = 0;
7045
7046 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7047 x = -x;
7048 }
7049 pos |= x << CURSOR_X_SHIFT;
7050
7051 if (y < 0) {
efc9064e 7052 if (y + intel_crtc->cursor_height <= 0)
cda4b7d3
CW		 7053 base = 0;
7054
7055 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7056 y = -y;
7057 }
7058 pos |= y << CURSOR_Y_SHIFT;
7059
7060 visible = base != 0;
560b85bb 7061 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 7062 return;
7063
0cd83aa9 7064 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 7065 I915_WRITE(CURPOS_IVB(pipe), pos);
7066 ivb_update_cursor(crtc, base);
7067 } else {
7068 I915_WRITE(CURPOS(pipe), pos);
7069 if (IS_845G(dev) || IS_I865G(dev))
7070 i845_update_cursor(crtc, base);
7071 else
7072 i9xx_update_cursor(crtc, base);
7073 }
cda4b7d3
CW		 7074}
7075
79e53945 7076static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 7077 struct drm_file *file,
79e53945
JB		 7078 uint32_t handle,
7079 uint32_t width, uint32_t height)
7080{
7081 struct drm_device *dev = crtc->dev;
7082 struct drm_i915_private *dev_priv = dev->dev_private;
7083 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 7084 struct drm_i915_gem_object *obj;
cda4b7d3 7085 uint32_t addr;
3f8bc370 7086 int ret;
79e53945 7087
79e53945
JB		 7088 /* if we want to turn off the cursor ignore width and height */
7089 if (!handle) {
28c97730 7090 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 7091 addr = 0;
05394f39 7092 obj = NULL;
5004417d 7093 mutex_lock(&dev->struct_mutex);
3f8bc370 7094 goto finish;
79e53945
JB		 7095 }
7096
7097 /* Currently we only support 64x64 cursors */
7098 if (width != 64 || height != 64) {
7099 DRM_ERROR("we currently only support 64x64 cursors\n");
7100 return -EINVAL;
7101 }
7102
05394f39 7103 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 7104 if (&obj->base == NULL)
79e53945
JB		 7105 return -ENOENT;
7106
05394f39 7107 if (obj->base.size < width * height * 4) {
79e53945 7108 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 7109 ret = -ENOMEM;
7110 goto fail;
79e53945
JB		 7111 }
7112
71acb5eb 7113 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 7114 mutex_lock(&dev->struct_mutex);
b295d1b6 7115 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 7116 unsigned alignment;
7117
d9e86c0e
CW		 7118 if (obj->tiling_mode) {
7119 DRM_ERROR("cursor cannot be tiled\n");
7120 ret = -EINVAL;
7121 goto fail_locked;
7122 }
7123
693db184
CW		 7124 /* Note that the w/a also requires 2 PTE of padding following
7125 * the bo. We currently fill all unused PTE with the shadow
7126 * page and so we should always have valid PTE following the
7127 * cursor preventing the VT-d warning.
7128 */
7129 alignment = 0;
7130 if (need_vtd_wa(dev))
7131 alignment = 64*1024;
7132
7133 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 7134 if (ret) {
7135 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 7136 goto fail_locked;
e7b526bb
CW		 7137 }
7138
d9e86c0e
CW		 7139 ret = i915_gem_object_put_fence(obj);
7140 if (ret) {
2da3b9b9 7141 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 7142 goto fail_unpin;
7143 }
7144
f343c5f6 7145 addr = i915_gem_obj_ggtt_offset(obj);
71acb5eb 7146 } else {
6eeefaf3 7147 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 7148 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 7149 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7150 align);
71acb5eb
DA		 7151 if (ret) {
7152 DRM_ERROR("failed to attach phys object\n");
7f9872e0 7153 goto fail_locked;
71acb5eb 7154 }
05394f39 7155 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 7156 }
7157
a6c45cf0 7158 if (IS_GEN2(dev))
14b60391
JB		 7159 I915_WRITE(CURSIZE, (height << 12) | width);
7160
3f8bc370 7161 finish:
3f8bc370 7162 if (intel_crtc->cursor_bo) {
b295d1b6 7163 if (dev_priv->info->cursor_needs_physical) {
05394f39 7164 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 7165 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7166 } else
cc98b413 7167 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
05394f39 7168 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 7169 }
80824003 7170
7f9872e0 7171 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 7172
7173 intel_crtc->cursor_addr = addr;
05394f39 7174 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 7175 intel_crtc->cursor_width = width;
7176 intel_crtc->cursor_height = height;
7177
f2f5f771
VS		 7178 if (intel_crtc->active)
7179 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 7180
79e53945 7181 return 0;
e7b526bb 7182fail_unpin:
cc98b413 7183 i915_gem_object_unpin_from_display_plane(obj);
7f9872e0 7184fail_locked:
34b8686e 7185 mutex_unlock(&dev->struct_mutex);
bc9025bd 7186fail:
05394f39 7187 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 7188 return ret;
79e53945
JB		 7189}
7190
7191static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7192{
79e53945 7193 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7194
cda4b7d3
CW		 7195 intel_crtc->cursor_x = x;
7196 intel_crtc->cursor_y = y;
652c393a 7197
f2f5f771
VS		 7198 if (intel_crtc->active)
7199 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 7200
7201 return 0;
b8c00ac5
DA		 7202}
7203
79e53945 7204static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 7205 u16 *blue, uint32_t start, uint32_t size)
79e53945 7206{
7203425a 7207 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 7208 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7209
7203425a 7210 for (i = start; i < end; i++) {
79e53945
JB		 7211 intel_crtc->lut_r[i] = red[i] >> 8;
7212 intel_crtc->lut_g[i] = green[i] >> 8;
7213 intel_crtc->lut_b[i] = blue[i] >> 8;
7214 }
7215
7216 intel_crtc_load_lut(crtc);
7217}
7218
79e53945
JB		 7219/* VESA 640x480x72Hz mode to set on the pipe */
7220static struct drm_display_mode load_detect_mode = {
7221 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7222 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7223};
7224
d2dff872
CW		 7225static struct drm_framebuffer *
7226intel_framebuffer_create(struct drm_device *dev,
308e5bcb 7227 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 7228 struct drm_i915_gem_object *obj)
7229{
7230 struct intel_framebuffer *intel_fb;
7231 int ret;
7232
7233 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7234 if (!intel_fb) {
7235 drm_gem_object_unreference_unlocked(&obj->base);
7236 return ERR_PTR(-ENOMEM);
7237 }
7238
7239 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7240 if (ret) {
7241 drm_gem_object_unreference_unlocked(&obj->base);
7242 kfree(intel_fb);
7243 return ERR_PTR(ret);
7244 }
7245
7246 return &intel_fb->base;
7247}
7248
7249static u32
7250intel_framebuffer_pitch_for_width(int width, int bpp)
7251{
7252 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7253 return ALIGN(pitch, 64);
7254}
7255
7256static u32
7257intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7258{
7259 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7260 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7261}
7262
7263static struct drm_framebuffer *
7264intel_framebuffer_create_for_mode(struct drm_device *dev,
7265 struct drm_display_mode *mode,
7266 int depth, int bpp)
7267{
7268 struct drm_i915_gem_object *obj;
0fed39bd 7269 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 7270
7271 obj = i915_gem_alloc_object(dev,
7272 intel_framebuffer_size_for_mode(mode, bpp));
7273 if (obj == NULL)
7274 return ERR_PTR(-ENOMEM);
7275
7276 mode_cmd.width = mode->hdisplay;
7277 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 7278 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7279 bpp);
5ca0c34a 7280 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 7281
7282 return intel_framebuffer_create(dev, &mode_cmd, obj);
7283}
7284
7285static struct drm_framebuffer *
7286mode_fits_in_fbdev(struct drm_device *dev,
7287 struct drm_display_mode *mode)
7288{
7289 struct drm_i915_private *dev_priv = dev->dev_private;
7290 struct drm_i915_gem_object *obj;
7291 struct drm_framebuffer *fb;
7292
7293 if (dev_priv->fbdev == NULL)
7294 return NULL;
7295
7296 obj = dev_priv->fbdev->ifb.obj;
7297 if (obj == NULL)
7298 return NULL;
7299
7300 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 7301 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7302 fb->bits_per_pixel))
d2dff872
CW		 7303 return NULL;
7304
01f2c773 7305 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 7306 return NULL;
7307
7308 return fb;
7309}
7310
d2434ab7 7311bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 7312 struct drm_display_mode *mode,
8261b191 7313 struct intel_load_detect_pipe *old)
79e53945
JB		 7314{
7315 struct intel_crtc *intel_crtc;
d2434ab7
DV		 7316 struct intel_encoder *intel_encoder =
7317 intel_attached_encoder(connector);
79e53945 7318 struct drm_crtc *possible_crtc;
4ef69c7a 7319 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 7320 struct drm_crtc *crtc = NULL;
7321 struct drm_device *dev = encoder->dev;
94352cf9 7322 struct drm_framebuffer *fb;
79e53945
JB		 7323 int i = -1;
7324
d2dff872
CW		 7325 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7326 connector->base.id, drm_get_connector_name(connector),
7327 encoder->base.id, drm_get_encoder_name(encoder));
7328
79e53945
JB		 7329 /*
7330 * Algorithm gets a little messy:
7a5e4805 7331 *
79e53945
JB		 7332 * - if the connector already has an assigned crtc, use it (but make
7333 * sure it's on first)
7a5e4805 7334 *
79e53945
JB		 7335 * - try to find the first unused crtc that can drive this connector,
7336 * and use that if we find one
79e53945
JB		 7337 */
7338
7339 /* See if we already have a CRTC for this connector */
7340 if (encoder->crtc) {
7341 crtc = encoder->crtc;
8261b191 7342
7b24056b
DV		 7343 mutex_lock(&crtc->mutex);
7344
24218aac 7345 old->dpms_mode = connector->dpms;
8261b191
CW		 7346 old->load_detect_temp = false;
7347
7348 /* Make sure the crtc and connector are running */
24218aac
DV		 7349 if (connector->dpms != DRM_MODE_DPMS_ON)
7350 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 7351
7173188d 7352 return true;
79e53945
JB		 7353 }
7354
7355 /* Find an unused one (if possible) */
7356 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7357 i++;
7358 if (!(encoder->possible_crtcs & (1 << i)))
7359 continue;
7360 if (!possible_crtc->enabled) {
7361 crtc = possible_crtc;
7362 break;
7363 }
79e53945
JB		 7364 }
7365
7366 /*
7367 * If we didn't find an unused CRTC, don't use any.
7368 */
7369 if (!crtc) {
7173188d
CW		 7370 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7371 return false;
79e53945
JB		 7372 }
7373
7b24056b 7374 mutex_lock(&crtc->mutex);
fc303101
DV		 7375 intel_encoder->new_crtc = to_intel_crtc(crtc);
7376 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 7377
7378 intel_crtc = to_intel_crtc(crtc);
24218aac 7379 old->dpms_mode = connector->dpms;
8261b191 7380 old->load_detect_temp = true;
d2dff872 7381 old->release_fb = NULL;
79e53945 7382
6492711d
CW		 7383 if (!mode)
7384 mode = &load_detect_mode;
79e53945 7385
d2dff872
CW		 7386 /* We need a framebuffer large enough to accommodate all accesses
7387 * that the plane may generate whilst we perform load detection.
7388 * We can not rely on the fbcon either being present (we get called
7389 * during its initialisation to detect all boot displays, or it may
7390 * not even exist) or that it is large enough to satisfy the
7391 * requested mode.
7392 */
94352cf9
DV		 7393 fb = mode_fits_in_fbdev(dev, mode);
7394 if (fb == NULL) {
d2dff872 7395 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 7396 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7397 old->release_fb = fb;
d2dff872
CW		 7398 } else
7399 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 7400 if (IS_ERR(fb)) {
d2dff872 7401 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 7402 mutex_unlock(&crtc->mutex);
0e8b3d3e 7403 return false;
79e53945 7404 }
79e53945 7405
c0c36b94 7406 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 7407 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 7408 if (old->release_fb)
7409 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 7410 mutex_unlock(&crtc->mutex);
0e8b3d3e 7411 return false;
79e53945 7412 }
7173188d 7413
79e53945 7414 /* let the connector get through one full cycle before testing */
9d0498a2 7415 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 7416 return true;
79e53945
JB		 7417}
7418
d2434ab7 7419void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 7420 struct intel_load_detect_pipe *old)
79e53945 7421{
d2434ab7
DV		 7422 struct intel_encoder *intel_encoder =
7423 intel_attached_encoder(connector);
4ef69c7a 7424 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 7425 struct drm_crtc *crtc = encoder->crtc;
79e53945 7426
d2dff872
CW		 7427 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7428 connector->base.id, drm_get_connector_name(connector),
7429 encoder->base.id, drm_get_encoder_name(encoder));
7430
8261b191 7431 if (old->load_detect_temp) {
fc303101
DV		 7432 to_intel_connector(connector)->new_encoder = NULL;
7433 intel_encoder->new_crtc = NULL;
7434 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 7435
36206361
DV		 7436 if (old->release_fb) {
7437 drm_framebuffer_unregister_private(old->release_fb);
7438 drm_framebuffer_unreference(old->release_fb);
7439 }
d2dff872 7440
67c96400 7441 mutex_unlock(&crtc->mutex);
0622a53c 7442 return;
79e53945
JB		 7443 }
7444
c751ce4f 7445 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 7446 if (old->dpms_mode != DRM_MODE_DPMS_ON)
7447 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 7448
7449 mutex_unlock(&crtc->mutex);
79e53945
JB		 7450}
7451
da4a1efa
VS		 7452static int i9xx_pll_refclk(struct drm_device *dev,
7453 const struct intel_crtc_config *pipe_config)
7454{
7455 struct drm_i915_private *dev_priv = dev->dev_private;
7456 u32 dpll = pipe_config->dpll_hw_state.dpll;
7457
7458 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7459 return dev_priv->vbt.lvds_ssc_freq * 1000;
7460 else if (HAS_PCH_SPLIT(dev))
7461 return 120000;
7462 else if (!IS_GEN2(dev))
7463 return 96000;
7464 else
7465 return 48000;
7466}
7467
79e53945 7468/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc
JB		 7469static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7470 struct intel_crtc_config *pipe_config)
79e53945 7471{
f1f644dc 7472 struct drm_device *dev = crtc->base.dev;
79e53945 7473 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 7474 int pipe = pipe_config->cpu_transcoder;
293623f7 7475 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 7476 u32 fp;
7477 intel_clock_t clock;
da4a1efa 7478 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 7479
7480 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 7481 fp = pipe_config->dpll_hw_state.fp0;
79e53945 7482 else
293623f7 7483 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 7484
7485 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 7486 if (IS_PINEVIEW(dev)) {
7487 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7488 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 7489 } else {
7490 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7491 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7492 }
7493
a6c45cf0 7494 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 7495 if (IS_PINEVIEW(dev))
7496 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7497 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 7498 else
7499 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 7500 DPLL_FPA01_P1_POST_DIV_SHIFT);
7501
7502 switch (dpll & DPLL_MODE_MASK) {
7503 case DPLLB_MODE_DAC_SERIAL:
7504 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7505 5 : 10;
7506 break;
7507 case DPLLB_MODE_LVDS:
7508 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7509 7 : 14;
7510 break;
7511 default:
28c97730 7512 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 7513 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 7514 return;
79e53945
JB		 7515 }
7516
ac58c3f0 7517 if (IS_PINEVIEW(dev))
da4a1efa 7518 pineview_clock(refclk, &clock);
ac58c3f0 7519 else
da4a1efa 7520 i9xx_clock(refclk, &clock);
79e53945
JB		 7521 } else {
7522 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7523
7524 if (is_lvds) {
7525 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7526 DPLL_FPA01_P1_POST_DIV_SHIFT);
7527 clock.p2 = 14;
79e53945
JB		 7528 } else {
7529 if (dpll & PLL_P1_DIVIDE_BY_TWO)
7530 clock.p1 = 2;
7531 else {
7532 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7533 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7534 }
7535 if (dpll & PLL_P2_DIVIDE_BY_4)
7536 clock.p2 = 4;
7537 else
7538 clock.p2 = 2;
79e53945 7539 }
da4a1efa
VS		 7540
7541 i9xx_clock(refclk, &clock);
79e53945
JB		 7542 }
7543
18442d08
VS		 7544 /*
7545 * This value includes pixel_multiplier. We will use
241bfc38 7546 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 7547 * encoder's get_config() function.
7548 */
7549 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 7550}
7551
6878da05
VS		 7552int intel_dotclock_calculate(int link_freq,
7553 const struct intel_link_m_n *m_n)
f1f644dc 7554{
f1f644dc
JB		 7555 /*
7556 * The calculation for the data clock is:
1041a02f 7557 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 7558 * But we want to avoid losing precison if possible, so:
1041a02f 7559 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 7560 *
7561 * and the link clock is simpler:
1041a02f 7562 * link_clock = (m * link_clock) / n
f1f644dc
JB		 7563 */
7564
6878da05
VS		 7565 if (!m_n->link_n)
7566 return 0;
f1f644dc 7567
6878da05
VS		 7568 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
7569}
f1f644dc 7570
18442d08
VS		 7571static void ironlake_pch_clock_get(struct intel_crtc *crtc,
7572 struct intel_crtc_config *pipe_config)
6878da05
VS		 7573{
7574 struct drm_device *dev = crtc->base.dev;
79e53945 7575
18442d08
VS		 7576 /* read out port_clock from the DPLL */
7577 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 7578
f1f644dc 7579 /*
18442d08 7580 * This value does not include pixel_multiplier.
241bfc38 7581 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 7582 * agree once we know their relationship in the encoder's
7583 * get_config() function.
79e53945 7584 */
241bfc38 7585 pipe_config->adjusted_mode.crtc_clock =
18442d08
VS		 7586 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
7587 &pipe_config->fdi_m_n);
79e53945
JB		 7588}
7589
7590/** Returns the currently programmed mode of the given pipe. */
7591struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7592 struct drm_crtc *crtc)
7593{
548f245b 7594 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 7595 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 7596 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 7597 struct drm_display_mode *mode;
f1f644dc 7598 struct intel_crtc_config pipe_config;
fe2b8f9d
PZ		 7599 int htot = I915_READ(HTOTAL(cpu_transcoder));
7600 int hsync = I915_READ(HSYNC(cpu_transcoder));
7601 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7602 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 7603 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 7604
7605 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7606 if (!mode)
7607 return NULL;
7608
f1f644dc
JB		 7609 /*
7610 * Construct a pipe_config sufficient for getting the clock info
7611 * back out of crtc_clock_get.
7612 *
7613 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7614 * to use a real value here instead.
7615 */
293623f7 7616 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 7617 pipe_config.pixel_multiplier = 1;
293623f7
VS		 7618 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
7619 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
7620 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 7621 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7622
773ae034 7623 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 7624 mode->hdisplay = (htot & 0xffff) + 1;
7625 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7626 mode->hsync_start = (hsync & 0xffff) + 1;
7627 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7628 mode->vdisplay = (vtot & 0xffff) + 1;
7629 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7630 mode->vsync_start = (vsync & 0xffff) + 1;
7631 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7632
7633 drm_mode_set_name(mode);
79e53945
JB		 7634
7635 return mode;
7636}
7637
3dec0095 7638static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7639{
7640 struct drm_device *dev = crtc->dev;
7641 drm_i915_private_t *dev_priv = dev->dev_private;
7642 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7643 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7644 int dpll_reg = DPLL(pipe);
7645 int dpll;
652c393a 7646
bad720ff 7647 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7648 return;
7649
7650 if (!dev_priv->lvds_downclock_avail)
7651 return;
7652
dbdc6479 7653 dpll = I915_READ(dpll_reg);
652c393a 7654 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7655 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7656
8ac5a6d5 7657 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7658
7659 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7660 I915_WRITE(dpll_reg, dpll);
9d0498a2 7661 intel_wait_for_vblank(dev, pipe);
dbdc6479 7662
652c393a
JB		 7663 dpll = I915_READ(dpll_reg);
7664 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7665 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7666 }
652c393a
JB		 7667}
7668
7669static void intel_decrease_pllclock(struct drm_crtc *crtc)
7670{
7671 struct drm_device *dev = crtc->dev;
7672 drm_i915_private_t *dev_priv = dev->dev_private;
7673 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7674
bad720ff 7675 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7676 return;
7677
7678 if (!dev_priv->lvds_downclock_avail)
7679 return;
7680
7681 /*
7682 * Since this is called by a timer, we should never get here in
7683 * the manual case.
7684 */
7685 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7686 int pipe = intel_crtc->pipe;
7687 int dpll_reg = DPLL(pipe);
7688 int dpll;
f6e5b160 7689
44d98a61 7690 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7691
8ac5a6d5 7692 assert_panel_unlocked(dev_priv, pipe);
652c393a 7693
dc257cf1 7694 dpll = I915_READ(dpll_reg);
652c393a
JB		 7695 dpll |= DISPLAY_RATE_SELECT_FPA1;
7696 I915_WRITE(dpll_reg, dpll);
9d0498a2 7697 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7698 dpll = I915_READ(dpll_reg);
7699 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7700 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7701 }
7702
7703}
7704
f047e395
CW		 7705void intel_mark_busy(struct drm_device *dev)
7706{
c67a470b
PZ		 7707 struct drm_i915_private *dev_priv = dev->dev_private;
7708
7709 hsw_package_c8_gpu_busy(dev_priv);
7710 i915_update_gfx_val(dev_priv);
f047e395
CW		 7711}
7712
7713void intel_mark_idle(struct drm_device *dev)
652c393a 7714{
c67a470b 7715 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 7716 struct drm_crtc *crtc;
652c393a 7717
c67a470b
PZ		 7718 hsw_package_c8_gpu_idle(dev_priv);
7719
652c393a
JB		 7720 if (!i915_powersave)
7721 return;
7722
652c393a 7723 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7724 if (!crtc->fb)
7725 continue;
7726
725a5b54 7727 intel_decrease_pllclock(crtc);
652c393a 7728 }
b29c19b6
CW		 7729
7730 if (dev_priv->info->gen >= 6)
7731 gen6_rps_idle(dev->dev_private);
652c393a
JB		 7732}
7733
c65355bb
CW		 7734void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7735 struct intel_ring_buffer *ring)
652c393a 7736{
f047e395
CW		 7737 struct drm_device *dev = obj->base.dev;
7738 struct drm_crtc *crtc;
652c393a 7739
f047e395 7740 if (!i915_powersave)
acb87dfb
CW		 7741 return;
7742
652c393a
JB		 7743 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7744 if (!crtc->fb)
7745 continue;
7746
c65355bb
CW		 7747 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7748 continue;
7749
7750 intel_increase_pllclock(crtc);
7751 if (ring && intel_fbc_enabled(dev))
7752 ring->fbc_dirty = true;
652c393a
JB		 7753 }
7754}
7755
79e53945
JB		 7756static void intel_crtc_destroy(struct drm_crtc *crtc)
7757{
7758 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7759 struct drm_device *dev = crtc->dev;
7760 struct intel_unpin_work *work;
7761 unsigned long flags;
7762
7763 spin_lock_irqsave(&dev->event_lock, flags);
7764 work = intel_crtc->unpin_work;
7765 intel_crtc->unpin_work = NULL;
7766 spin_unlock_irqrestore(&dev->event_lock, flags);
7767
7768 if (work) {
7769 cancel_work_sync(&work->work);
7770 kfree(work);
7771 }
79e53945 7772
40ccc72b
MK		 7773 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7774
79e53945 7775 drm_crtc_cleanup(crtc);
67e77c5a 7776
79e53945
JB		 7777 kfree(intel_crtc);
7778}
7779
6b95a207
KH		 7780static void intel_unpin_work_fn(struct work_struct *__work)
7781{
7782 struct intel_unpin_work *work =
7783 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7784 struct drm_device *dev = work->crtc->dev;
6b95a207 7785
b4a98e57 7786 mutex_lock(&dev->struct_mutex);
1690e1eb 7787 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7788 drm_gem_object_unreference(&work->pending_flip_obj->base);
7789 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7790
b4a98e57
CW		 7791 intel_update_fbc(dev);
7792 mutex_unlock(&dev->struct_mutex);
7793
7794 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7795 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7796
6b95a207
KH		 7797 kfree(work);
7798}
7799
1afe3e9d 7800static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7801 struct drm_crtc *crtc)
6b95a207
KH		 7802{
7803 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7804 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7805 struct intel_unpin_work *work;
6b95a207
KH		 7806 unsigned long flags;
7807
7808 /* Ignore early vblank irqs */
7809 if (intel_crtc == NULL)
7810 return;
7811
7812 spin_lock_irqsave(&dev->event_lock, flags);
7813 work = intel_crtc->unpin_work;
e7d841ca
CW		 7814
7815 /* Ensure we don't miss a work->pending update ... */
7816 smp_rmb();
7817
7818 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7819 spin_unlock_irqrestore(&dev->event_lock, flags);
7820 return;
7821 }
7822
e7d841ca
CW		 7823 /* and that the unpin work is consistent wrt ->pending. */
7824 smp_rmb();
7825
6b95a207 7826 intel_crtc->unpin_work = NULL;
6b95a207 7827
45a066eb
RC		 7828 if (work->event)
7829 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7830
0af7e4df
MK		 7831 drm_vblank_put(dev, intel_crtc->pipe);
7832
6b95a207
KH		 7833 spin_unlock_irqrestore(&dev->event_lock, flags);
7834
2c10d571 7835 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7836
7837 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7838
7839 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7840}
7841
1afe3e9d
JB		 7842void intel_finish_page_flip(struct drm_device *dev, int pipe)
7843{
7844 drm_i915_private_t *dev_priv = dev->dev_private;
7845 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7846
49b14a5c 7847 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7848}
7849
7850void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7851{
7852 drm_i915_private_t *dev_priv = dev->dev_private;
7853 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7854
49b14a5c 7855 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7856}
7857
6b95a207
KH		 7858void intel_prepare_page_flip(struct drm_device *dev, int plane)
7859{
7860 drm_i915_private_t *dev_priv = dev->dev_private;
7861 struct intel_crtc *intel_crtc =
7862 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7863 unsigned long flags;
7864
e7d841ca
CW		 7865 /* NB: An MMIO update of the plane base pointer will also
7866 * generate a page-flip completion irq, i.e. every modeset
7867 * is also accompanied by a spurious intel_prepare_page_flip().
7868 */
6b95a207 7869 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7870 if (intel_crtc->unpin_work)
7871 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7872 spin_unlock_irqrestore(&dev->event_lock, flags);
7873}
7874
e7d841ca
CW		 7875inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7876{
7877 /* Ensure that the work item is consistent when activating it ... */
7878 smp_wmb();
7879 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7880 /* and that it is marked active as soon as the irq could fire. */
7881 smp_wmb();
7882}
7883
8c9f3aaf
JB		 7884static int intel_gen2_queue_flip(struct drm_device *dev,
7885 struct drm_crtc *crtc,
7886 struct drm_framebuffer *fb,
ed8d1975
KP		 7887 struct drm_i915_gem_object *obj,
7888 uint32_t flags)
8c9f3aaf
JB		 7889{
7890 struct drm_i915_private *dev_priv = dev->dev_private;
7891 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7892 u32 flip_mask;
6d90c952 7893 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7894 int ret;
7895
6d90c952 7896 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7897 if (ret)
83d4092b 7898 goto err;
8c9f3aaf 7899
6d90c952 7900 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7901 if (ret)
83d4092b 7902 goto err_unpin;
8c9f3aaf
JB		 7903
7904 /* Can't queue multiple flips, so wait for the previous
7905 * one to finish before executing the next.
7906 */
7907 if (intel_crtc->plane)
7908 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7909 else
7910 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7911 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7912 intel_ring_emit(ring, MI_NOOP);
7913 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7914 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7915 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7916 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952 7917 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7918
7919 intel_mark_page_flip_active(intel_crtc);
09246732 7920 __intel_ring_advance(ring);
83d4092b
CW		 7921 return 0;
7922
7923err_unpin:
7924 intel_unpin_fb_obj(obj);
7925err:
8c9f3aaf
JB		 7926 return ret;
7927}
7928
7929static int intel_gen3_queue_flip(struct drm_device *dev,
7930 struct drm_crtc *crtc,
7931 struct drm_framebuffer *fb,
ed8d1975
KP		 7932 struct drm_i915_gem_object *obj,
7933 uint32_t flags)
8c9f3aaf
JB		 7934{
7935 struct drm_i915_private *dev_priv = dev->dev_private;
7936 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7937 u32 flip_mask;
6d90c952 7938 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7939 int ret;
7940
6d90c952 7941 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7942 if (ret)
83d4092b 7943 goto err;
8c9f3aaf 7944
6d90c952 7945 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7946 if (ret)
83d4092b 7947 goto err_unpin;
8c9f3aaf
JB		 7948
7949 if (intel_crtc->plane)
7950 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7951 else
7952 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7953 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7954 intel_ring_emit(ring, MI_NOOP);
7955 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7956 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7957 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7958 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952
DV		 7959 intel_ring_emit(ring, MI_NOOP);
7960
e7d841ca 7961 intel_mark_page_flip_active(intel_crtc);
09246732 7962 __intel_ring_advance(ring);
83d4092b
CW		 7963 return 0;
7964
7965err_unpin:
7966 intel_unpin_fb_obj(obj);
7967err:
8c9f3aaf
JB		 7968 return ret;
7969}
7970
7971static int intel_gen4_queue_flip(struct drm_device *dev,
7972 struct drm_crtc *crtc,
7973 struct drm_framebuffer *fb,
ed8d1975
KP		 7974 struct drm_i915_gem_object *obj,
7975 uint32_t flags)
8c9f3aaf
JB		 7976{
7977 struct drm_i915_private *dev_priv = dev->dev_private;
7978 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7979 uint32_t pf, pipesrc;
6d90c952 7980 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7981 int ret;
7982
6d90c952 7983 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7984 if (ret)
83d4092b 7985 goto err;
8c9f3aaf 7986
6d90c952 7987 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7988 if (ret)
83d4092b 7989 goto err_unpin;
8c9f3aaf
JB		 7990
7991 /* i965+ uses the linear or tiled offsets from the
7992 * Display Registers (which do not change across a page-flip)
7993 * so we need only reprogram the base address.
7994 */
6d90c952
DV		 7995 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7996 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7997 intel_ring_emit(ring, fb->pitches[0]);
c2c75131 7998 intel_ring_emit(ring,
f343c5f6 7999 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
c2c75131 8000 obj->tiling_mode);
8c9f3aaf
JB		 8001
8002 /* XXX Enabling the panel-fitter across page-flip is so far
8003 * untested on non-native modes, so ignore it for now.
8004 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8005 */
8006 pf = 0;
8007 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 8008 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 8009
8010 intel_mark_page_flip_active(intel_crtc);
09246732 8011 __intel_ring_advance(ring);
83d4092b
CW		 8012 return 0;
8013
8014err_unpin:
8015 intel_unpin_fb_obj(obj);
8016err:
8c9f3aaf
JB		 8017 return ret;
8018}
8019
8020static int intel_gen6_queue_flip(struct drm_device *dev,
8021 struct drm_crtc *crtc,
8022 struct drm_framebuffer *fb,
ed8d1975
KP		 8023 struct drm_i915_gem_object *obj,
8024 uint32_t flags)
8c9f3aaf
JB		 8025{
8026 struct drm_i915_private *dev_priv = dev->dev_private;
8027 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 8028 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 8029 uint32_t pf, pipesrc;
8030 int ret;
8031
6d90c952 8032 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 8033 if (ret)
83d4092b 8034 goto err;
8c9f3aaf 8035
6d90c952 8036 ret = intel_ring_begin(ring, 4);
8c9f3aaf 8037 if (ret)
83d4092b 8038 goto err_unpin;
8c9f3aaf 8039
6d90c952
DV		 8040 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8041 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8042 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
f343c5f6 8043 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8c9f3aaf 8044
dc257cf1
DV		 8045 /* Contrary to the suggestions in the documentation,
8046 * "Enable Panel Fitter" does not seem to be required when page
8047 * flipping with a non-native mode, and worse causes a normal
8048 * modeset to fail.
8049 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8050 */
8051 pf = 0;
8c9f3aaf 8052 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 8053 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 8054
8055 intel_mark_page_flip_active(intel_crtc);
09246732 8056 __intel_ring_advance(ring);
83d4092b
CW		 8057 return 0;
8058
8059err_unpin:
8060 intel_unpin_fb_obj(obj);
8061err:
8c9f3aaf
JB		 8062 return ret;
8063}
8064
7c9017e5
JB		 8065static int intel_gen7_queue_flip(struct drm_device *dev,
8066 struct drm_crtc *crtc,
8067 struct drm_framebuffer *fb,
ed8d1975
KP		 8068 struct drm_i915_gem_object *obj,
8069 uint32_t flags)
7c9017e5
JB		 8070{
8071 struct drm_i915_private *dev_priv = dev->dev_private;
8072 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ffe74d75 8073 struct intel_ring_buffer *ring;
cb05d8de 8074 uint32_t plane_bit = 0;
ffe74d75
CW		 8075 int len, ret;
8076
8077 ring = obj->ring;
1c5fd085 8078 if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
ffe74d75 8079 ring = &dev_priv->ring[BCS];
7c9017e5
JB		 8080
8081 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8082 if (ret)
83d4092b 8083 goto err;
7c9017e5 8084
cb05d8de
DV		 8085 switch(intel_crtc->plane) {
8086 case PLANE_A:
8087 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8088 break;
8089 case PLANE_B:
8090 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8091 break;
8092 case PLANE_C:
8093 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8094 break;
8095 default:
8096 WARN_ONCE(1, "unknown plane in flip command\n");
8097 ret = -ENODEV;
ab3951eb 8098 goto err_unpin;
cb05d8de
DV		 8099 }
8100
ffe74d75
CW		 8101 len = 4;
8102 if (ring->id == RCS)
8103 len += 6;
8104
8105 ret = intel_ring_begin(ring, len);
7c9017e5 8106 if (ret)
83d4092b 8107 goto err_unpin;
7c9017e5 8108
ffe74d75
CW		 8109 /* Unmask the flip-done completion message. Note that the bspec says that
8110 * we should do this for both the BCS and RCS, and that we must not unmask
8111 * more than one flip event at any time (or ensure that one flip message
8112 * can be sent by waiting for flip-done prior to queueing new flips).
8113 * Experimentation says that BCS works despite DERRMR masking all
8114 * flip-done completion events and that unmasking all planes at once
8115 * for the RCS also doesn't appear to drop events. Setting the DERRMR
8116 * to zero does lead to lockups within MI_DISPLAY_FLIP.
8117 */
8118 if (ring->id == RCS) {
8119 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8120 intel_ring_emit(ring, DERRMR);
8121 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8122 DERRMR_PIPEB_PRI_FLIP_DONE |
8123 DERRMR_PIPEC_PRI_FLIP_DONE));
8124 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
8125 intel_ring_emit(ring, DERRMR);
8126 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8127 }
8128
cb05d8de 8129 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 8130 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
f343c5f6 8131 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7c9017e5 8132 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 8133
8134 intel_mark_page_flip_active(intel_crtc);
09246732 8135 __intel_ring_advance(ring);
83d4092b
CW		 8136 return 0;
8137
8138err_unpin:
8139 intel_unpin_fb_obj(obj);
8140err:
7c9017e5
JB		 8141 return ret;
8142}
8143
8c9f3aaf
JB		 8144static int intel_default_queue_flip(struct drm_device *dev,
8145 struct drm_crtc *crtc,
8146 struct drm_framebuffer *fb,
ed8d1975
KP		 8147 struct drm_i915_gem_object *obj,
8148 uint32_t flags)
8c9f3aaf
JB		 8149{
8150 return -ENODEV;
8151}
8152
6b95a207
KH		 8153static int intel_crtc_page_flip(struct drm_crtc *crtc,
8154 struct drm_framebuffer *fb,
ed8d1975
KP		 8155 struct drm_pending_vblank_event *event,
8156 uint32_t page_flip_flags)
6b95a207
KH		 8157{
8158 struct drm_device *dev = crtc->dev;
8159 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 8160 struct drm_framebuffer *old_fb = crtc->fb;
8161 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 8162 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8163 struct intel_unpin_work *work;
8c9f3aaf 8164 unsigned long flags;
52e68630 8165 int ret;
6b95a207 8166
e6a595d2
VS		 8167 /* Can't change pixel format via MI display flips. */
8168 if (fb->pixel_format != crtc->fb->pixel_format)
8169 return -EINVAL;
8170
8171 /*
8172 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8173 * Note that pitch changes could also affect these register.
8174 */
8175 if (INTEL_INFO(dev)->gen > 3 &&
8176 (fb->offsets[0] != crtc->fb->offsets[0] ||
8177 fb->pitches[0] != crtc->fb->pitches[0]))
8178 return -EINVAL;
8179
b14c5679 8180 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 8181 if (work == NULL)
8182 return -ENOMEM;
8183
6b95a207 8184 work->event = event;
b4a98e57 8185 work->crtc = crtc;
4a35f83b 8186 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 8187 INIT_WORK(&work->work, intel_unpin_work_fn);
8188
7317c75e
JB		 8189 ret = drm_vblank_get(dev, intel_crtc->pipe);
8190 if (ret)
8191 goto free_work;
8192
6b95a207
KH		 8193 /* We borrow the event spin lock for protecting unpin_work */
8194 spin_lock_irqsave(&dev->event_lock, flags);
8195 if (intel_crtc->unpin_work) {
8196 spin_unlock_irqrestore(&dev->event_lock, flags);
8197 kfree(work);
7317c75e 8198 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 8199
8200 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 8201 return -EBUSY;
8202 }
8203 intel_crtc->unpin_work = work;
8204 spin_unlock_irqrestore(&dev->event_lock, flags);
8205
b4a98e57
CW		 8206 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8207 flush_workqueue(dev_priv->wq);
8208
79158103
CW		 8209 ret = i915_mutex_lock_interruptible(dev);
8210 if (ret)
8211 goto cleanup;
6b95a207 8212
75dfca80 8213 /* Reference the objects for the scheduled work. */
05394f39
CW		 8214 drm_gem_object_reference(&work->old_fb_obj->base);
8215 drm_gem_object_reference(&obj->base);
6b95a207
KH		 8216
8217 crtc->fb = fb;
96b099fd 8218
e1f99ce6 8219 work->pending_flip_obj = obj;
e1f99ce6 8220
4e5359cd
SF		 8221 work->enable_stall_check = true;
8222
b4a98e57 8223 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 8224 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 8225
ed8d1975 8226 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8c9f3aaf
JB		 8227 if (ret)
8228 goto cleanup_pending;
6b95a207 8229
7782de3b 8230 intel_disable_fbc(dev);
c65355bb 8231 intel_mark_fb_busy(obj, NULL);
6b95a207
KH		 8232 mutex_unlock(&dev->struct_mutex);
8233
e5510fac
JB		 8234 trace_i915_flip_request(intel_crtc->plane, obj);
8235
6b95a207 8236 return 0;
96b099fd 8237
8c9f3aaf 8238cleanup_pending:
b4a98e57 8239 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 8240 crtc->fb = old_fb;
05394f39
CW		 8241 drm_gem_object_unreference(&work->old_fb_obj->base);
8242 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 8243 mutex_unlock(&dev->struct_mutex);
8244
79158103 8245cleanup:
96b099fd
CW		 8246 spin_lock_irqsave(&dev->event_lock, flags);
8247 intel_crtc->unpin_work = NULL;
8248 spin_unlock_irqrestore(&dev->event_lock, flags);
8249
7317c75e
JB		 8250 drm_vblank_put(dev, intel_crtc->pipe);
8251free_work:
96b099fd
CW		 8252 kfree(work);
8253
8254 return ret;
6b95a207
KH		 8255}
8256
f6e5b160 8257static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 8258 .mode_set_base_atomic = intel_pipe_set_base_atomic,
8259 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 8260};
8261
50f56119
DV		 8262static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8263 struct drm_crtc *crtc)
8264{
8265 struct drm_device *dev;
8266 struct drm_crtc *tmp;
8267 int crtc_mask = 1;
47f1c6c9 8268
50f56119 8269 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 8270
50f56119 8271 dev = crtc->dev;
47f1c6c9 8272
50f56119
DV		 8273 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8274 if (tmp == crtc)
8275 break;
8276 crtc_mask <<= 1;
8277 }
47f1c6c9 8278
50f56119
DV		 8279 if (encoder->possible_crtcs & crtc_mask)
8280 return true;
8281 return false;
47f1c6c9 8282}
79e53945 8283
9a935856
DV		 8284/**
8285 * intel_modeset_update_staged_output_state
8286 *
8287 * Updates the staged output configuration state, e.g. after we've read out the
8288 * current hw state.
8289 */
8290static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 8291{
9a935856
DV		 8292 struct intel_encoder *encoder;
8293 struct intel_connector *connector;
f6e5b160 8294
9a935856
DV		 8295 list_for_each_entry(connector, &dev->mode_config.connector_list,
8296 base.head) {
8297 connector->new_encoder =
8298 to_intel_encoder(connector->base.encoder);
8299 }
f6e5b160 8300
9a935856
DV		 8301 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8302 base.head) {
8303 encoder->new_crtc =
8304 to_intel_crtc(encoder->base.crtc);
8305 }
f6e5b160
CW		 8306}
8307
9a935856
DV		 8308/**
8309 * intel_modeset_commit_output_state
8310 *
8311 * This function copies the stage display pipe configuration to the real one.
8312 */
8313static void intel_modeset_commit_output_state(struct drm_device *dev)
8314{
8315 struct intel_encoder *encoder;
8316 struct intel_connector *connector;
f6e5b160 8317
9a935856
DV		 8318 list_for_each_entry(connector, &dev->mode_config.connector_list,
8319 base.head) {
8320 connector->base.encoder = &connector->new_encoder->base;
8321 }
f6e5b160 8322
9a935856
DV		 8323 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8324 base.head) {
8325 encoder->base.crtc = &encoder->new_crtc->base;
8326 }
8327}
8328
050f7aeb
DV		 8329static void
8330connected_sink_compute_bpp(struct intel_connector * connector,
8331 struct intel_crtc_config *pipe_config)
8332{
8333 int bpp = pipe_config->pipe_bpp;
8334
8335 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8336 connector->base.base.id,
8337 drm_get_connector_name(&connector->base));
8338
8339 /* Don't use an invalid EDID bpc value */
8340 if (connector->base.display_info.bpc &&
8341 connector->base.display_info.bpc * 3 < bpp) {
8342 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8343 bpp, connector->base.display_info.bpc*3);
8344 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8345 }
8346
8347 /* Clamp bpp to 8 on screens without EDID 1.4 */
8348 if (connector->base.display_info.bpc == 0 && bpp > 24) {
8349 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8350 bpp);
8351 pipe_config->pipe_bpp = 24;
8352 }
8353}
8354
4e53c2e0 8355static int
050f7aeb
DV		 8356compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8357 struct drm_framebuffer *fb,
8358 struct intel_crtc_config *pipe_config)
4e53c2e0 8359{
050f7aeb
DV		 8360 struct drm_device *dev = crtc->base.dev;
8361 struct intel_connector *connector;
4e53c2e0
DV		 8362 int bpp;
8363
d42264b1
DV		 8364 switch (fb->pixel_format) {
8365 case DRM_FORMAT_C8:
4e53c2e0
DV		 8366 bpp = 8*3; /* since we go through a colormap */
8367 break;
d42264b1
DV		 8368 case DRM_FORMAT_XRGB1555:
8369 case DRM_FORMAT_ARGB1555:
8370 /* checked in intel_framebuffer_init already */
8371 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8372 return -EINVAL;
8373 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 8374 bpp = 6*3; /* min is 18bpp */
8375 break;
d42264b1
DV		 8376 case DRM_FORMAT_XBGR8888:
8377 case DRM_FORMAT_ABGR8888:
8378 /* checked in intel_framebuffer_init already */
8379 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8380 return -EINVAL;
8381 case DRM_FORMAT_XRGB8888:
8382 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 8383 bpp = 8*3;
8384 break;
d42264b1
DV		 8385 case DRM_FORMAT_XRGB2101010:
8386 case DRM_FORMAT_ARGB2101010:
8387 case DRM_FORMAT_XBGR2101010:
8388 case DRM_FORMAT_ABGR2101010:
8389 /* checked in intel_framebuffer_init already */
8390 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 8391 return -EINVAL;
4e53c2e0
DV		 8392 bpp = 10*3;
8393 break;
baba133a 8394 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 8395 default:
8396 DRM_DEBUG_KMS("unsupported depth\n");
8397 return -EINVAL;
8398 }
8399
4e53c2e0
DV		 8400 pipe_config->pipe_bpp = bpp;
8401
8402 /* Clamp display bpp to EDID value */
8403 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 8404 base.head) {
1b829e05
DV		 8405 if (!connector->new_encoder ||
8406 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 8407 continue;
8408
050f7aeb 8409 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 8410 }
8411
8412 return bpp;
8413}
8414
644db711
DV		 8415static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
8416{
8417 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8418 "type: 0x%x flags: 0x%x\n",
1342830c 8419 mode->crtc_clock,
644db711
DV		 8420 mode->crtc_hdisplay, mode->crtc_hsync_start,
8421 mode->crtc_hsync_end, mode->crtc_htotal,
8422 mode->crtc_vdisplay, mode->crtc_vsync_start,
8423 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
8424}
8425
c0b03411
DV		 8426static void intel_dump_pipe_config(struct intel_crtc *crtc,
8427 struct intel_crtc_config *pipe_config,
8428 const char *context)
8429{
8430 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8431 context, pipe_name(crtc->pipe));
8432
8433 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8434 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8435 pipe_config->pipe_bpp, pipe_config->dither);
8436 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8437 pipe_config->has_pch_encoder,
8438 pipe_config->fdi_lanes,
8439 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8440 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8441 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 8442 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8443 pipe_config->has_dp_encoder,
8444 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8445 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8446 pipe_config->dp_m_n.tu);
c0b03411
DV		 8447 DRM_DEBUG_KMS("requested mode:\n");
8448 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8449 DRM_DEBUG_KMS("adjusted mode:\n");
8450 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
644db711 8451 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
d71b8d4a 8452 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 8453 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8454 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
c0b03411
DV		 8455 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8456 pipe_config->gmch_pfit.control,
8457 pipe_config->gmch_pfit.pgm_ratios,
8458 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 8459 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 8460 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 8461 pipe_config->pch_pfit.size,
8462 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 8463 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 8464 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
c0b03411
DV		 8465}
8466
accfc0c5
DV		 8467static bool check_encoder_cloning(struct drm_crtc *crtc)
8468{
8469 int num_encoders = 0;
8470 bool uncloneable_encoders = false;
8471 struct intel_encoder *encoder;
8472
8473 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8474 base.head) {
8475 if (&encoder->new_crtc->base != crtc)
8476 continue;
8477
8478 num_encoders++;
8479 if (!encoder->cloneable)
8480 uncloneable_encoders = true;
8481 }
8482
8483 return !(num_encoders > 1 && uncloneable_encoders);
8484}
8485
b8cecdf5
DV		 8486static struct intel_crtc_config *
8487intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 8488 struct drm_framebuffer *fb,
b8cecdf5 8489 struct drm_display_mode *mode)
ee7b9f93 8490{
7758a113 8491 struct drm_device *dev = crtc->dev;
7758a113 8492 struct intel_encoder *encoder;
b8cecdf5 8493 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 8494 int plane_bpp, ret = -EINVAL;
8495 bool retry = true;
ee7b9f93 8496
accfc0c5
DV		 8497 if (!check_encoder_cloning(crtc)) {
8498 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8499 return ERR_PTR(-EINVAL);
8500 }
8501
b8cecdf5
DV		 8502 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8503 if (!pipe_config)
7758a113
DV		 8504 return ERR_PTR(-ENOMEM);
8505
b8cecdf5
DV		 8506 drm_mode_copy(&pipe_config->adjusted_mode, mode);
8507 drm_mode_copy(&pipe_config->requested_mode, mode);
37327abd 8508
e143a21c
DV		 8509 pipe_config->cpu_transcoder =
8510 (enum transcoder) to_intel_crtc(crtc)->pipe;
c0d43d62 8511 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 8512
2960bc9c
ID		 8513 /*
8514 * Sanitize sync polarity flags based on requested ones. If neither
8515 * positive or negative polarity is requested, treat this as meaning
8516 * negative polarity.
8517 */
8518 if (!(pipe_config->adjusted_mode.flags &
8519 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8520 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8521
8522 if (!(pipe_config->adjusted_mode.flags &
8523 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8524 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8525
050f7aeb
DV		 8526 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8527 * plane pixel format and any sink constraints into account. Returns the
8528 * source plane bpp so that dithering can be selected on mismatches
8529 * after encoders and crtc also have had their say. */
8530 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8531 fb, pipe_config);
4e53c2e0
DV		 8532 if (plane_bpp < 0)
8533 goto fail;
8534
e41a56be
VS		 8535 /*
8536 * Determine the real pipe dimensions. Note that stereo modes can
8537 * increase the actual pipe size due to the frame doubling and
8538 * insertion of additional space for blanks between the frame. This
8539 * is stored in the crtc timings. We use the requested mode to do this
8540 * computation to clearly distinguish it from the adjusted mode, which
8541 * can be changed by the connectors in the below retry loop.
8542 */
8543 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
8544 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
8545 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
8546
e29c22c0 8547encoder_retry:
ef1b460d 8548 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 8549 pipe_config->port_clock = 0;
ef1b460d 8550 pipe_config->pixel_multiplier = 1;
ff9a6750 8551
135c81b8 8552 /* Fill in default crtc timings, allow encoders to overwrite them. */
6ce70f5e 8553 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
135c81b8 8554
7758a113
DV		 8555 /* Pass our mode to the connectors and the CRTC to give them a chance to
8556 * adjust it according to limitations or connector properties, and also
8557 * a chance to reject the mode entirely.
47f1c6c9 8558 */
7758a113
DV		 8559 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8560 base.head) {
47f1c6c9 8561
7758a113
DV		 8562 if (&encoder->new_crtc->base != crtc)
8563 continue;
7ae89233 8564
efea6e8e
DV		 8565 if (!(encoder->compute_config(encoder, pipe_config))) {
8566 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 8567 goto fail;
8568 }
ee7b9f93 8569 }
47f1c6c9 8570
ff9a6750
DV		 8571 /* Set default port clock if not overwritten by the encoder. Needs to be
8572 * done afterwards in case the encoder adjusts the mode. */
8573 if (!pipe_config->port_clock)
241bfc38
DL		 8574 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
8575 * pipe_config->pixel_multiplier;
ff9a6750 8576
a43f6e0f 8577 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 8578 if (ret < 0) {
7758a113
DV		 8579 DRM_DEBUG_KMS("CRTC fixup failed\n");
8580 goto fail;
ee7b9f93 8581 }
e29c22c0
DV		 8582
8583 if (ret == RETRY) {
8584 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8585 ret = -EINVAL;
8586 goto fail;
8587 }
8588
8589 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8590 retry = false;
8591 goto encoder_retry;
8592 }
8593
4e53c2e0
DV		 8594 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8595 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8596 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8597
b8cecdf5 8598 return pipe_config;
7758a113 8599fail:
b8cecdf5 8600 kfree(pipe_config);
e29c22c0 8601 return ERR_PTR(ret);
ee7b9f93 8602}
47f1c6c9 8603
e2e1ed41
DV		 8604/* Computes which crtcs are affected and sets the relevant bits in the mask. For
8605 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8606static void
8607intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8608 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 8609{
8610 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 8611 struct drm_device *dev = crtc->dev;
8612 struct intel_encoder *encoder;
8613 struct intel_connector *connector;
8614 struct drm_crtc *tmp_crtc;
79e53945 8615
e2e1ed41 8616 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 8617
e2e1ed41
DV		 8618 /* Check which crtcs have changed outputs connected to them, these need
8619 * to be part of the prepare_pipes mask. We don't (yet) support global
8620 * modeset across multiple crtcs, so modeset_pipes will only have one
8621 * bit set at most. */
8622 list_for_each_entry(connector, &dev->mode_config.connector_list,
8623 base.head) {
8624 if (connector->base.encoder == &connector->new_encoder->base)
8625 continue;
79e53945 8626
e2e1ed41
DV		 8627 if (connector->base.encoder) {
8628 tmp_crtc = connector->base.encoder->crtc;
8629
8630 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8631 }
8632
8633 if (connector->new_encoder)
8634 *prepare_pipes |=
8635 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 8636 }
8637
e2e1ed41
DV		 8638 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8639 base.head) {
8640 if (encoder->base.crtc == &encoder->new_crtc->base)
8641 continue;
8642
8643 if (encoder->base.crtc) {
8644 tmp_crtc = encoder->base.crtc;
8645
8646 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8647 }
8648
8649 if (encoder->new_crtc)
8650 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 8651 }
8652
e2e1ed41
DV		 8653 /* Check for any pipes that will be fully disabled ... */
8654 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8655 base.head) {
8656 bool used = false;
22fd0fab 8657
e2e1ed41
DV		 8658 /* Don't try to disable disabled crtcs. */
8659 if (!intel_crtc->base.enabled)
8660 continue;
7e7d76c3 8661
e2e1ed41
DV		 8662 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8663 base.head) {
8664 if (encoder->new_crtc == intel_crtc)
8665 used = true;
8666 }
8667
8668 if (!used)
8669 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 8670 }
8671
e2e1ed41
DV		 8672
8673 /* set_mode is also used to update properties on life display pipes. */
8674 intel_crtc = to_intel_crtc(crtc);
8675 if (crtc->enabled)
8676 *prepare_pipes |= 1 << intel_crtc->pipe;
8677
b6c5164d
DV		 8678 /*
8679 * For simplicity do a full modeset on any pipe where the output routing
8680 * changed. We could be more clever, but that would require us to be
8681 * more careful with calling the relevant encoder->mode_set functions.
8682 */
e2e1ed41
DV		 8683 if (*prepare_pipes)
8684 *modeset_pipes = *prepare_pipes;
8685
8686 /* ... and mask these out. */
8687 *modeset_pipes &= ~(*disable_pipes);
8688 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 8689
8690 /*
8691 * HACK: We don't (yet) fully support global modesets. intel_set_config
8692 * obies this rule, but the modeset restore mode of
8693 * intel_modeset_setup_hw_state does not.
8694 */
8695 *modeset_pipes &= 1 << intel_crtc->pipe;
8696 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 8697
8698 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8699 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 8700}
79e53945 8701
ea9d758d 8702static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 8703{
ea9d758d 8704 struct drm_encoder *encoder;
f6e5b160 8705 struct drm_device *dev = crtc->dev;
f6e5b160 8706
ea9d758d
DV		 8707 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8708 if (encoder->crtc == crtc)
8709 return true;
8710
8711 return false;
8712}
8713
8714static void
8715intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8716{
8717 struct intel_encoder *intel_encoder;
8718 struct intel_crtc *intel_crtc;
8719 struct drm_connector *connector;
8720
8721 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8722 base.head) {
8723 if (!intel_encoder->base.crtc)
8724 continue;
8725
8726 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8727
8728 if (prepare_pipes & (1 << intel_crtc->pipe))
8729 intel_encoder->connectors_active = false;
8730 }
8731
8732 intel_modeset_commit_output_state(dev);
8733
8734 /* Update computed state. */
8735 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8736 base.head) {
8737 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8738 }
8739
8740 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8741 if (!connector->encoder || !connector->encoder->crtc)
8742 continue;
8743
8744 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8745
8746 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8747 struct drm_property *dpms_property =
8748 dev->mode_config.dpms_property;
8749
ea9d758d 8750 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8751 drm_object_property_set_value(&connector->base,
68d34720
DV		 8752 dpms_property,
8753 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8754
8755 intel_encoder = to_intel_encoder(connector->encoder);
8756 intel_encoder->connectors_active = true;
8757 }
8758 }
8759
8760}
8761
3bd26263 8762static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 8763{
3bd26263 8764 int diff;
f1f644dc
JB		 8765
8766 if (clock1 == clock2)
8767 return true;
8768
8769 if (!clock1 || !clock2)
8770 return false;
8771
8772 diff = abs(clock1 - clock2);
8773
8774 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8775 return true;
8776
8777 return false;
8778}
8779
25c5b266
DV		 8780#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8781 list_for_each_entry((intel_crtc), \
8782 &(dev)->mode_config.crtc_list, \
8783 base.head) \
0973f18f 8784 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8785
0e8ffe1b 8786static bool
2fa2fe9a
DV		 8787intel_pipe_config_compare(struct drm_device *dev,
8788 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8789 struct intel_crtc_config *pipe_config)
8790{
66e985c0
DV		 8791#define PIPE_CONF_CHECK_X(name) \
8792 if (current_config->name != pipe_config->name) { \
8793 DRM_ERROR("mismatch in " #name " " \
8794 "(expected 0x%08x, found 0x%08x)\n", \
8795 current_config->name, \
8796 pipe_config->name); \
8797 return false; \
8798 }
8799
08a24034
DV		 8800#define PIPE_CONF_CHECK_I(name) \
8801 if (current_config->name != pipe_config->name) { \
8802 DRM_ERROR("mismatch in " #name " " \
8803 "(expected %i, found %i)\n", \
8804 current_config->name, \
8805 pipe_config->name); \
8806 return false; \
88adfff1
DV		 8807 }
8808
1bd1bd80
DV		 8809#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8810 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 8811 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 8812 "(expected %i, found %i)\n", \
8813 current_config->name & (mask), \
8814 pipe_config->name & (mask)); \
8815 return false; \
8816 }
8817
5e550656
VS		 8818#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
8819 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
8820 DRM_ERROR("mismatch in " #name " " \
8821 "(expected %i, found %i)\n", \
8822 current_config->name, \
8823 pipe_config->name); \
8824 return false; \
8825 }
8826
bb760063
DV		 8827#define PIPE_CONF_QUIRK(quirk) \
8828 ((current_config->quirks | pipe_config->quirks) & (quirk))
8829
eccb140b
DV		 8830 PIPE_CONF_CHECK_I(cpu_transcoder);
8831
08a24034
DV		 8832 PIPE_CONF_CHECK_I(has_pch_encoder);
8833 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8834 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8835 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8836 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8837 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8838 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8839
eb14cb74
VS		 8840 PIPE_CONF_CHECK_I(has_dp_encoder);
8841 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
8842 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
8843 PIPE_CONF_CHECK_I(dp_m_n.link_m);
8844 PIPE_CONF_CHECK_I(dp_m_n.link_n);
8845 PIPE_CONF_CHECK_I(dp_m_n.tu);
8846
1bd1bd80
DV		 8847 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8848 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8849 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8850 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8851 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8852 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8853
8854 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8855 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8856 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8857 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8858 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8859 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8860
c93f54cf 8861 PIPE_CONF_CHECK_I(pixel_multiplier);
6c49f241 8862
1bd1bd80
DV		 8863 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8864 DRM_MODE_FLAG_INTERLACE);
8865
bb760063
DV		 8866 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8867 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8868 DRM_MODE_FLAG_PHSYNC);
8869 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8870 DRM_MODE_FLAG_NHSYNC);
8871 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8872 DRM_MODE_FLAG_PVSYNC);
8873 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8874 DRM_MODE_FLAG_NVSYNC);
8875 }
045ac3b5 8876
37327abd
VS		 8877 PIPE_CONF_CHECK_I(pipe_src_w);
8878 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 8879
2fa2fe9a
DV		 8880 PIPE_CONF_CHECK_I(gmch_pfit.control);
8881 /* pfit ratios are autocomputed by the hw on gen4+ */
8882 if (INTEL_INFO(dev)->gen < 4)
8883 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8884 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
fd4daa9c
CW		 8885 PIPE_CONF_CHECK_I(pch_pfit.enabled);
8886 if (current_config->pch_pfit.enabled) {
8887 PIPE_CONF_CHECK_I(pch_pfit.pos);
8888 PIPE_CONF_CHECK_I(pch_pfit.size);
8889 }
2fa2fe9a 8890
42db64ef
PZ		 8891 PIPE_CONF_CHECK_I(ips_enabled);
8892
282740f7
VS		 8893 PIPE_CONF_CHECK_I(double_wide);
8894
c0d43d62 8895 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 8896 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 8897 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 8898 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8899 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
c0d43d62 8900
42571aef
VS		 8901 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
8902 PIPE_CONF_CHECK_I(pipe_bpp);
8903
d71b8d4a 8904 if (!IS_HASWELL(dev)) {
241bfc38 8905 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
d71b8d4a
VS		 8906 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
8907 }
5e550656 8908
66e985c0 8909#undef PIPE_CONF_CHECK_X
08a24034 8910#undef PIPE_CONF_CHECK_I
1bd1bd80 8911#undef PIPE_CONF_CHECK_FLAGS
5e550656 8912#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 8913#undef PIPE_CONF_QUIRK
88adfff1 8914
0e8ffe1b
DV		 8915 return true;
8916}
8917
91d1b4bd
DV		 8918static void
8919check_connector_state(struct drm_device *dev)
8af6cf88 8920{
8af6cf88
DV		 8921 struct intel_connector *connector;
8922
8923 list_for_each_entry(connector, &dev->mode_config.connector_list,
8924 base.head) {
8925 /* This also checks the encoder/connector hw state with the
8926 * ->get_hw_state callbacks. */
8927 intel_connector_check_state(connector);
8928
8929 WARN(&connector->new_encoder->base != connector->base.encoder,
8930 "connector's staged encoder doesn't match current encoder\n");
8931 }
91d1b4bd
DV		 8932}
8933
8934static void
8935check_encoder_state(struct drm_device *dev)
8936{
8937 struct intel_encoder *encoder;
8938 struct intel_connector *connector;
8af6cf88
DV		 8939
8940 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8941 base.head) {
8942 bool enabled = false;
8943 bool active = false;
8944 enum pipe pipe, tracked_pipe;
8945
8946 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8947 encoder->base.base.id,
8948 drm_get_encoder_name(&encoder->base));
8949
8950 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8951 "encoder's stage crtc doesn't match current crtc\n");
8952 WARN(encoder->connectors_active && !encoder->base.crtc,
8953 "encoder's active_connectors set, but no crtc\n");
8954
8955 list_for_each_entry(connector, &dev->mode_config.connector_list,
8956 base.head) {
8957 if (connector->base.encoder != &encoder->base)
8958 continue;
8959 enabled = true;
8960 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8961 active = true;
8962 }
8963 WARN(!!encoder->base.crtc != enabled,
8964 "encoder's enabled state mismatch "
8965 "(expected %i, found %i)\n",
8966 !!encoder->base.crtc, enabled);
8967 WARN(active && !encoder->base.crtc,
8968 "active encoder with no crtc\n");
8969
8970 WARN(encoder->connectors_active != active,
8971 "encoder's computed active state doesn't match tracked active state "
8972 "(expected %i, found %i)\n", active, encoder->connectors_active);
8973
8974 active = encoder->get_hw_state(encoder, &pipe);
8975 WARN(active != encoder->connectors_active,
8976 "encoder's hw state doesn't match sw tracking "
8977 "(expected %i, found %i)\n",
8978 encoder->connectors_active, active);
8979
8980 if (!encoder->base.crtc)
8981 continue;
8982
8983 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8984 WARN(active && pipe != tracked_pipe,
8985 "active encoder's pipe doesn't match"
8986 "(expected %i, found %i)\n",
8987 tracked_pipe, pipe);
8988
8989 }
91d1b4bd
DV		 8990}
8991
8992static void
8993check_crtc_state(struct drm_device *dev)
8994{
8995 drm_i915_private_t *dev_priv = dev->dev_private;
8996 struct intel_crtc *crtc;
8997 struct intel_encoder *encoder;
8998 struct intel_crtc_config pipe_config;
8af6cf88
DV		 8999
9000 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9001 base.head) {
9002 bool enabled = false;
9003 bool active = false;
9004
045ac3b5
JB		 9005 memset(&pipe_config, 0, sizeof(pipe_config));
9006
8af6cf88
DV		 9007 DRM_DEBUG_KMS("[CRTC:%d]\n",
9008 crtc->base.base.id);
9009
9010 WARN(crtc->active && !crtc->base.enabled,
9011 "active crtc, but not enabled in sw tracking\n");
9012
9013 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9014 base.head) {
9015 if (encoder->base.crtc != &crtc->base)
9016 continue;
9017 enabled = true;
9018 if (encoder->connectors_active)
9019 active = true;
9020 }
6c49f241 9021
8af6cf88
DV		 9022 WARN(active != crtc->active,
9023 "crtc's computed active state doesn't match tracked active state "
9024 "(expected %i, found %i)\n", active, crtc->active);
9025 WARN(enabled != crtc->base.enabled,
9026 "crtc's computed enabled state doesn't match tracked enabled state "
9027 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
9028
0e8ffe1b
DV		 9029 active = dev_priv->display.get_pipe_config(crtc,
9030 &pipe_config);
d62cf62a
DV		 9031
9032 /* hw state is inconsistent with the pipe A quirk */
9033 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
9034 active = crtc->active;
9035
6c49f241
DV		 9036 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9037 base.head) {
3eaba51c 9038 enum pipe pipe;
6c49f241
DV		 9039 if (encoder->base.crtc != &crtc->base)
9040 continue;
3eaba51c
VS		 9041 if (encoder->get_config &&
9042 encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 9043 encoder->get_config(encoder, &pipe_config);
9044 }
9045
0e8ffe1b
DV		 9046 WARN(crtc->active != active,
9047 "crtc active state doesn't match with hw state "
9048 "(expected %i, found %i)\n", crtc->active, active);
9049
c0b03411
DV		 9050 if (active &&
9051 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9052 WARN(1, "pipe state doesn't match!\n");
9053 intel_dump_pipe_config(crtc, &pipe_config,
9054 "[hw state]");
9055 intel_dump_pipe_config(crtc, &crtc->config,
9056 "[sw state]");
9057 }
8af6cf88
DV		 9058 }
9059}
9060
91d1b4bd
DV		 9061static void
9062check_shared_dpll_state(struct drm_device *dev)
9063{
9064 drm_i915_private_t *dev_priv = dev->dev_private;
9065 struct intel_crtc *crtc;
9066 struct intel_dpll_hw_state dpll_hw_state;
9067 int i;
5358901f
DV		 9068
9069 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9070 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9071 int enabled_crtcs = 0, active_crtcs = 0;
9072 bool active;
9073
9074 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9075
9076 DRM_DEBUG_KMS("%s\n", pll->name);
9077
9078 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9079
9080 WARN(pll->active > pll->refcount,
9081 "more active pll users than references: %i vs %i\n",
9082 pll->active, pll->refcount);
9083 WARN(pll->active && !pll->on,
9084 "pll in active use but not on in sw tracking\n");
35c95375
DV		 9085 WARN(pll->on && !pll->active,
9086 "pll in on but not on in use in sw tracking\n");
5358901f
DV		 9087 WARN(pll->on != active,
9088 "pll on state mismatch (expected %i, found %i)\n",
9089 pll->on, active);
9090
9091 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9092 base.head) {
9093 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9094 enabled_crtcs++;
9095 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9096 active_crtcs++;
9097 }
9098 WARN(pll->active != active_crtcs,
9099 "pll active crtcs mismatch (expected %i, found %i)\n",
9100 pll->active, active_crtcs);
9101 WARN(pll->refcount != enabled_crtcs,
9102 "pll enabled crtcs mismatch (expected %i, found %i)\n",
9103 pll->refcount, enabled_crtcs);
66e985c0
DV		 9104
9105 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9106 sizeof(dpll_hw_state)),
9107 "pll hw state mismatch\n");
5358901f 9108 }
8af6cf88
DV		 9109}
9110
91d1b4bd
DV		 9111void
9112intel_modeset_check_state(struct drm_device *dev)
9113{
9114 check_connector_state(dev);
9115 check_encoder_state(dev);
9116 check_crtc_state(dev);
9117 check_shared_dpll_state(dev);
9118}
9119
18442d08
VS		 9120void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9121 int dotclock)
9122{
9123 /*
9124 * FDI already provided one idea for the dotclock.
9125 * Yell if the encoder disagrees.
9126 */
241bfc38 9127 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
18442d08 9128 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
241bfc38 9129 pipe_config->adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 9130}
9131
f30da187
DV		 9132static int __intel_set_mode(struct drm_crtc *crtc,
9133 struct drm_display_mode *mode,
9134 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 9135{
9136 struct drm_device *dev = crtc->dev;
dbf2b54e 9137 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 9138 struct drm_display_mode *saved_mode, *saved_hwmode;
9139 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 9140 struct intel_crtc *intel_crtc;
9141 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 9142 int ret = 0;
a6778b3c 9143
a1e22653 9144 saved_mode = kcalloc(2, sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 9145 if (!saved_mode)
9146 return -ENOMEM;
3ac18232 9147 saved_hwmode = saved_mode + 1;
a6778b3c 9148
e2e1ed41 9149 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 9150 &prepare_pipes, &disable_pipes);
9151
3ac18232
TG		 9152 *saved_hwmode = crtc->hwmode;
9153 *saved_mode = crtc->mode;
a6778b3c 9154
25c5b266
DV		 9155 /* Hack: Because we don't (yet) support global modeset on multiple
9156 * crtcs, we don't keep track of the new mode for more than one crtc.
9157 * Hence simply check whether any bit is set in modeset_pipes in all the
9158 * pieces of code that are not yet converted to deal with mutliple crtcs
9159 * changing their mode at the same time. */
25c5b266 9160 if (modeset_pipes) {
4e53c2e0 9161 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 9162 if (IS_ERR(pipe_config)) {
9163 ret = PTR_ERR(pipe_config);
9164 pipe_config = NULL;
9165
3ac18232 9166 goto out;
25c5b266 9167 }
c0b03411
DV		 9168 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9169 "[modeset]");
25c5b266 9170 }
a6778b3c 9171
460da916
DV		 9172 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9173 intel_crtc_disable(&intel_crtc->base);
9174
ea9d758d
DV		 9175 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9176 if (intel_crtc->base.enabled)
9177 dev_priv->display.crtc_disable(&intel_crtc->base);
9178 }
a6778b3c 9179
6c4c86f5
DV		 9180 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9181 * to set it here already despite that we pass it down the callchain.
f6e5b160 9182 */
b8cecdf5 9183 if (modeset_pipes) {
25c5b266 9184 crtc->mode = *mode;
b8cecdf5
DV		 9185 /* mode_set/enable/disable functions rely on a correct pipe
9186 * config. */
9187 to_intel_crtc(crtc)->config = *pipe_config;
9188 }
7758a113 9189
ea9d758d
DV		 9190 /* Only after disabling all output pipelines that will be changed can we
9191 * update the the output configuration. */
9192 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 9193
47fab737
DV		 9194 if (dev_priv->display.modeset_global_resources)
9195 dev_priv->display.modeset_global_resources(dev);
9196
a6778b3c
DV		 9197 /* Set up the DPLL and any encoders state that needs to adjust or depend
9198 * on the DPLL.
f6e5b160 9199 */
25c5b266 9200 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 9201 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 9202 x, y, fb);
9203 if (ret)
9204 goto done;
a6778b3c
DV		 9205 }
9206
9207 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 9208 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9209 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 9210
25c5b266
DV		 9211 if (modeset_pipes) {
9212 /* Store real post-adjustment hardware mode. */
b8cecdf5 9213 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 9214
25c5b266
DV		 9215 /* Calculate and store various constants which
9216 * are later needed by vblank and swap-completion
9217 * timestamping. They are derived from true hwmode.
9218 */
9219 drm_calc_timestamping_constants(crtc);
9220 }
a6778b3c
DV		 9221
9222 /* FIXME: add subpixel order */
9223done:
c0c36b94 9224 if (ret && crtc->enabled) {
3ac18232
TG		 9225 crtc->hwmode = *saved_hwmode;
9226 crtc->mode = *saved_mode;
a6778b3c
DV		 9227 }
9228
3ac18232 9229out:
b8cecdf5 9230 kfree(pipe_config);
3ac18232 9231 kfree(saved_mode);
a6778b3c 9232 return ret;
f6e5b160
CW		 9233}
9234
e7457a9a
DL		 9235static int intel_set_mode(struct drm_crtc *crtc,
9236 struct drm_display_mode *mode,
9237 int x, int y, struct drm_framebuffer *fb)
f30da187
DV		 9238{
9239 int ret;
9240
9241 ret = __intel_set_mode(crtc, mode, x, y, fb);
9242
9243 if (ret == 0)
9244 intel_modeset_check_state(crtc->dev);
9245
9246 return ret;
9247}
9248
c0c36b94
CW		 9249void intel_crtc_restore_mode(struct drm_crtc *crtc)
9250{
9251 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9252}
9253
25c5b266
DV		 9254#undef for_each_intel_crtc_masked
9255
d9e55608
DV		 9256static void intel_set_config_free(struct intel_set_config *config)
9257{
9258 if (!config)
9259 return;
9260
1aa4b628
DV		 9261 kfree(config->save_connector_encoders);
9262 kfree(config->save_encoder_crtcs);
d9e55608
DV		 9263 kfree(config);
9264}
9265
85f9eb71
DV		 9266static int intel_set_config_save_state(struct drm_device *dev,
9267 struct intel_set_config *config)
9268{
85f9eb71
DV		 9269 struct drm_encoder *encoder;
9270 struct drm_connector *connector;
9271 int count;
9272
1aa4b628
DV		 9273 config->save_encoder_crtcs =
9274 kcalloc(dev->mode_config.num_encoder,
9275 sizeof(struct drm_crtc *), GFP_KERNEL);
9276 if (!config->save_encoder_crtcs)
85f9eb71
DV		 9277 return -ENOMEM;
9278
1aa4b628
DV		 9279 config->save_connector_encoders =
9280 kcalloc(dev->mode_config.num_connector,
9281 sizeof(struct drm_encoder *), GFP_KERNEL);
9282 if (!config->save_connector_encoders)
85f9eb71
DV		 9283 return -ENOMEM;
9284
9285 /* Copy data. Note that driver private data is not affected.
9286 * Should anything bad happen only the expected state is
9287 * restored, not the drivers personal bookkeeping.
9288 */
85f9eb71
DV		 9289 count = 0;
9290 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 9291 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 9292 }
9293
9294 count = 0;
9295 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 9296 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 9297 }
9298
9299 return 0;
9300}
9301
9302static void intel_set_config_restore_state(struct drm_device *dev,
9303 struct intel_set_config *config)
9304{
9a935856
DV		 9305 struct intel_encoder *encoder;
9306 struct intel_connector *connector;
85f9eb71
DV		 9307 int count;
9308
85f9eb71 9309 count = 0;
9a935856
DV		 9310 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9311 encoder->new_crtc =
9312 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 9313 }
9314
9315 count = 0;
9a935856
DV		 9316 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9317 connector->new_encoder =
9318 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 9319 }
9320}
9321
e3de42b6 9322static bool
2e57f47d 9323is_crtc_connector_off(struct drm_mode_set *set)
e3de42b6
ID		 9324{
9325 int i;
9326
2e57f47d
CW		 9327 if (set->num_connectors == 0)
9328 return false;
9329
9330 if (WARN_ON(set->connectors == NULL))
9331 return false;
9332
9333 for (i = 0; i < set->num_connectors; i++)
9334 if (set->connectors[i]->encoder &&
9335 set->connectors[i]->encoder->crtc == set->crtc &&
9336 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
e3de42b6
ID		 9337 return true;
9338
9339 return false;
9340}
9341
5e2b584e
DV		 9342static void
9343intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9344 struct intel_set_config *config)
9345{
9346
9347 /* We should be able to check here if the fb has the same properties
9348 * and then just flip_or_move it */
2e57f47d
CW		 9349 if (is_crtc_connector_off(set)) {
9350 config->mode_changed = true;
e3de42b6 9351 } else if (set->crtc->fb != set->fb) {
5e2b584e
DV		 9352 /* If we have no fb then treat it as a full mode set */
9353 if (set->crtc->fb == NULL) {
319d9827
JB		 9354 struct intel_crtc *intel_crtc =
9355 to_intel_crtc(set->crtc);
9356
9357 if (intel_crtc->active && i915_fastboot) {
9358 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9359 config->fb_changed = true;
9360 } else {
9361 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9362 config->mode_changed = true;
9363 }
5e2b584e
DV		 9364 } else if (set->fb == NULL) {
9365 config->mode_changed = true;
72f4901e
DV		 9366 } else if (set->fb->pixel_format !=
9367 set->crtc->fb->pixel_format) {
5e2b584e 9368 config->mode_changed = true;
e3de42b6 9369 } else {
5e2b584e 9370 config->fb_changed = true;
e3de42b6 9371 }
5e2b584e
DV		 9372 }
9373
835c5873 9374 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 9375 config->fb_changed = true;
9376
9377 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9378 DRM_DEBUG_KMS("modes are different, full mode set\n");
9379 drm_mode_debug_printmodeline(&set->crtc->mode);
9380 drm_mode_debug_printmodeline(set->mode);
9381 config->mode_changed = true;
9382 }
a1d95703
CW		 9383
9384 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9385 set->crtc->base.id, config->mode_changed, config->fb_changed);
5e2b584e
DV		 9386}
9387
2e431051 9388static int
9a935856
DV		 9389intel_modeset_stage_output_state(struct drm_device *dev,
9390 struct drm_mode_set *set,
9391 struct intel_set_config *config)
50f56119 9392{
85f9eb71 9393 struct drm_crtc *new_crtc;
9a935856
DV		 9394 struct intel_connector *connector;
9395 struct intel_encoder *encoder;
f3f08572 9396 int ro;
50f56119 9397
9abdda74 9398 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 9399 * of connectors. For paranoia, double-check this. */
9400 WARN_ON(!set->fb && (set->num_connectors != 0));
9401 WARN_ON(set->fb && (set->num_connectors == 0));
9402
9a935856
DV		 9403 list_for_each_entry(connector, &dev->mode_config.connector_list,
9404 base.head) {
9405 /* Otherwise traverse passed in connector list and get encoders
9406 * for them. */
50f56119 9407 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 9408 if (set->connectors[ro] == &connector->base) {
9409 connector->new_encoder = connector->encoder;
50f56119
DV		 9410 break;
9411 }
9412 }
9413
9a935856
DV		 9414 /* If we disable the crtc, disable all its connectors. Also, if
9415 * the connector is on the changing crtc but not on the new
9416 * connector list, disable it. */
9417 if ((!set->fb || ro == set->num_connectors) &&
9418 connector->base.encoder &&
9419 connector->base.encoder->crtc == set->crtc) {
9420 connector->new_encoder = NULL;
9421
9422 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9423 connector->base.base.id,
9424 drm_get_connector_name(&connector->base));
9425 }
9426
9427
9428 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 9429 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 9430 config->mode_changed = true;
50f56119
DV		 9431 }
9432 }
9a935856 9433 /* connector->new_encoder is now updated for all connectors. */
50f56119 9434
9a935856 9435 /* Update crtc of enabled connectors. */
9a935856
DV		 9436 list_for_each_entry(connector, &dev->mode_config.connector_list,
9437 base.head) {
9438 if (!connector->new_encoder)
50f56119
DV		 9439 continue;
9440
9a935856 9441 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 9442
9443 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 9444 if (set->connectors[ro] == &connector->base)
50f56119
DV		 9445 new_crtc = set->crtc;
9446 }
9447
9448 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 9449 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9450 new_crtc)) {
5e2b584e 9451 return -EINVAL;
50f56119 9452 }
9a935856
DV		 9453 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9454
9455 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9456 connector->base.base.id,
9457 drm_get_connector_name(&connector->base),
9458 new_crtc->base.id);
9459 }
9460
9461 /* Check for any encoders that needs to be disabled. */
9462 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9463 base.head) {
9464 list_for_each_entry(connector,
9465 &dev->mode_config.connector_list,
9466 base.head) {
9467 if (connector->new_encoder == encoder) {
9468 WARN_ON(!connector->new_encoder->new_crtc);
9469
9470 goto next_encoder;
9471 }
9472 }
9473 encoder->new_crtc = NULL;
9474next_encoder:
9475 /* Only now check for crtc changes so we don't miss encoders
9476 * that will be disabled. */
9477 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 9478 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 9479 config->mode_changed = true;
50f56119
DV		 9480 }
9481 }
9a935856 9482 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 9483
2e431051
DV		 9484 return 0;
9485}
9486
9487static int intel_crtc_set_config(struct drm_mode_set *set)
9488{
9489 struct drm_device *dev;
2e431051
DV		 9490 struct drm_mode_set save_set;
9491 struct intel_set_config *config;
9492 int ret;
2e431051 9493
8d3e375e
DV		 9494 BUG_ON(!set);
9495 BUG_ON(!set->crtc);
9496 BUG_ON(!set->crtc->helper_private);
2e431051 9497
7e53f3a4
DV		 9498 /* Enforce sane interface api - has been abused by the fb helper. */
9499 BUG_ON(!set->mode && set->fb);
9500 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 9501
2e431051
DV		 9502 if (set->fb) {
9503 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9504 set->crtc->base.id, set->fb->base.id,
9505 (int)set->num_connectors, set->x, set->y);
9506 } else {
9507 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 9508 }
9509
9510 dev = set->crtc->dev;
9511
9512 ret = -ENOMEM;
9513 config = kzalloc(sizeof(*config), GFP_KERNEL);
9514 if (!config)
9515 goto out_config;
9516
9517 ret = intel_set_config_save_state(dev, config);
9518 if (ret)
9519 goto out_config;
9520
9521 save_set.crtc = set->crtc;
9522 save_set.mode = &set->crtc->mode;
9523 save_set.x = set->crtc->x;
9524 save_set.y = set->crtc->y;
9525 save_set.fb = set->crtc->fb;
9526
9527 /* Compute whether we need a full modeset, only an fb base update or no
9528 * change at all. In the future we might also check whether only the
9529 * mode changed, e.g. for LVDS where we only change the panel fitter in
9530 * such cases. */
9531 intel_set_config_compute_mode_changes(set, config);
9532
9a935856 9533 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 9534 if (ret)
9535 goto fail;
9536
5e2b584e 9537 if (config->mode_changed) {
c0c36b94
CW		 9538 ret = intel_set_mode(set->crtc, set->mode,
9539 set->x, set->y, set->fb);
5e2b584e 9540 } else if (config->fb_changed) {
4878cae2
VS		 9541 intel_crtc_wait_for_pending_flips(set->crtc);
9542
4f660f49 9543 ret = intel_pipe_set_base(set->crtc,
94352cf9 9544 set->x, set->y, set->fb);
50f56119
DV		 9545 }
9546
2d05eae1 9547 if (ret) {
bf67dfeb
DV		 9548 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9549 set->crtc->base.id, ret);
50f56119 9550fail:
2d05eae1 9551 intel_set_config_restore_state(dev, config);
50f56119 9552
2d05eae1
CW		 9553 /* Try to restore the config */
9554 if (config->mode_changed &&
9555 intel_set_mode(save_set.crtc, save_set.mode,
9556 save_set.x, save_set.y, save_set.fb))
9557 DRM_ERROR("failed to restore config after modeset failure\n");
9558 }
50f56119 9559
d9e55608
DV		 9560out_config:
9561 intel_set_config_free(config);
50f56119
DV		 9562 return ret;
9563}
f6e5b160
CW		 9564
9565static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 9566 .cursor_set = intel_crtc_cursor_set,
9567 .cursor_move = intel_crtc_cursor_move,
9568 .gamma_set = intel_crtc_gamma_set,
50f56119 9569 .set_config = intel_crtc_set_config,
f6e5b160
CW		 9570 .destroy = intel_crtc_destroy,
9571 .page_flip = intel_crtc_page_flip,
9572};
9573
79f689aa
PZ		 9574static void intel_cpu_pll_init(struct drm_device *dev)
9575{
affa9354 9576 if (HAS_DDI(dev))
79f689aa
PZ		 9577 intel_ddi_pll_init(dev);
9578}
9579
5358901f
DV		 9580static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9581 struct intel_shared_dpll *pll,
9582 struct intel_dpll_hw_state *hw_state)
ee7b9f93 9583{
5358901f 9584 uint32_t val;
ee7b9f93 9585
5358901f 9586 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 9587 hw_state->dpll = val;
9588 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9589 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 9590
9591 return val & DPLL_VCO_ENABLE;
9592}
9593
15bdd4cf
DV		 9594static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9595 struct intel_shared_dpll *pll)
9596{
9597 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9598 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9599}
9600
e7b903d2
DV		 9601static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9602 struct intel_shared_dpll *pll)
9603{
e7b903d2
DV		 9604 /* PCH refclock must be enabled first */
9605 assert_pch_refclk_enabled(dev_priv);
9606
15bdd4cf
DV		 9607 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9608
9609 /* Wait for the clocks to stabilize. */
9610 POSTING_READ(PCH_DPLL(pll->id));
9611 udelay(150);
9612
9613 /* The pixel multiplier can only be updated once the
9614 * DPLL is enabled and the clocks are stable.
9615 *
9616 * So write it again.
9617 */
9618 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9619 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9620 udelay(200);
9621}
9622
9623static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9624 struct intel_shared_dpll *pll)
9625{
9626 struct drm_device *dev = dev_priv->dev;
9627 struct intel_crtc *crtc;
e7b903d2
DV		 9628
9629 /* Make sure no transcoder isn't still depending on us. */
9630 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9631 if (intel_crtc_to_shared_dpll(crtc) == pll)
9632 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 9633 }
9634
15bdd4cf
DV		 9635 I915_WRITE(PCH_DPLL(pll->id), 0);
9636 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9637 udelay(200);
9638}
9639
46edb027
DV		 9640static char *ibx_pch_dpll_names[] = {
9641 "PCH DPLL A",
9642 "PCH DPLL B",
9643};
9644
7c74ade1 9645static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 9646{
e7b903d2 9647 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 9648 int i;
9649
7c74ade1 9650 dev_priv->num_shared_dpll = 2;
ee7b9f93 9651
e72f9fbf 9652 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 9653 dev_priv->shared_dplls[i].id = i;
9654 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 9655 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 9656 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9657 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 9658 dev_priv->shared_dplls[i].get_hw_state =
9659 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 9660 }
9661}
9662
7c74ade1
DV		 9663static void intel_shared_dpll_init(struct drm_device *dev)
9664{
e7b903d2 9665 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1
DV		 9666
9667 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9668 ibx_pch_dpll_init(dev);
9669 else
9670 dev_priv->num_shared_dpll = 0;
9671
9672 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9673 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9674 dev_priv->num_shared_dpll);
9675}
9676
b358d0a6 9677static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 9678{
22fd0fab 9679 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 9680 struct intel_crtc *intel_crtc;
9681 int i;
9682
955382f3 9683 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 9684 if (intel_crtc == NULL)
9685 return;
9686
9687 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9688
9689 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 9690 for (i = 0; i < 256; i++) {
9691 intel_crtc->lut_r[i] = i;
9692 intel_crtc->lut_g[i] = i;
9693 intel_crtc->lut_b[i] = i;
9694 }
9695
80824003
JB		 9696 /* Swap pipes & planes for FBC on pre-965 */
9697 intel_crtc->pipe = pipe;
9698 intel_crtc->plane = pipe;
e2e767ab 9699 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 9700 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 9701 intel_crtc->plane = !pipe;
80824003
JB		 9702 }
9703
22fd0fab
JB		 9704 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9705 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9706 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9707 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9708
79e53945 9709 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 9710}
9711
08d7b3d1 9712int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 9713 struct drm_file *file)
08d7b3d1 9714{
08d7b3d1 9715 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 9716 struct drm_mode_object *drmmode_obj;
9717 struct intel_crtc *crtc;
08d7b3d1 9718
1cff8f6b
DV		 9719 if (!drm_core_check_feature(dev, DRIVER_MODESET))
9720 return -ENODEV;
08d7b3d1 9721
c05422d5
DV		 9722 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9723 DRM_MODE_OBJECT_CRTC);
08d7b3d1 9724
c05422d5 9725 if (!drmmode_obj) {
08d7b3d1
CW		 9726 DRM_ERROR("no such CRTC id\n");
9727 return -EINVAL;
9728 }
9729
c05422d5
DV		 9730 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9731 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 9732
c05422d5 9733 return 0;
08d7b3d1
CW		 9734}
9735
66a9278e 9736static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 9737{
66a9278e
DV		 9738 struct drm_device *dev = encoder->base.dev;
9739 struct intel_encoder *source_encoder;
79e53945 9740 int index_mask = 0;
79e53945
JB		 9741 int entry = 0;
9742
66a9278e
DV		 9743 list_for_each_entry(source_encoder,
9744 &dev->mode_config.encoder_list, base.head) {
9745
9746 if (encoder == source_encoder)
79e53945 9747 index_mask |= (1 << entry);
66a9278e
DV		 9748
9749 /* Intel hw has only one MUX where enocoders could be cloned. */
9750 if (encoder->cloneable && source_encoder->cloneable)
9751 index_mask |= (1 << entry);
9752
79e53945
JB		 9753 entry++;
9754 }
4ef69c7a 9755
79e53945
JB		 9756 return index_mask;
9757}
9758
4d302442
CW		 9759static bool has_edp_a(struct drm_device *dev)
9760{
9761 struct drm_i915_private *dev_priv = dev->dev_private;
9762
9763 if (!IS_MOBILE(dev))
9764 return false;
9765
9766 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9767 return false;
9768
9769 if (IS_GEN5(dev) &&
9770 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9771 return false;
9772
9773 return true;
9774}
9775
79e53945
JB		 9776static void intel_setup_outputs(struct drm_device *dev)
9777{
725e30ad 9778 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 9779 struct intel_encoder *encoder;
cb0953d7 9780 bool dpd_is_edp = false;
79e53945 9781
c9093354 9782 intel_lvds_init(dev);
79e53945 9783
c40c0f5b 9784 if (!IS_ULT(dev))
79935fca 9785 intel_crt_init(dev);
cb0953d7 9786
affa9354 9787 if (HAS_DDI(dev)) {
0e72a5b5
ED		 9788 int found;
9789
9790 /* Haswell uses DDI functions to detect digital outputs */
9791 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9792 /* DDI A only supports eDP */
9793 if (found)
9794 intel_ddi_init(dev, PORT_A);
9795
9796 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9797 * register */
9798 found = I915_READ(SFUSE_STRAP);
9799
9800 if (found & SFUSE_STRAP_DDIB_DETECTED)
9801 intel_ddi_init(dev, PORT_B);
9802 if (found & SFUSE_STRAP_DDIC_DETECTED)
9803 intel_ddi_init(dev, PORT_C);
9804 if (found & SFUSE_STRAP_DDID_DETECTED)
9805 intel_ddi_init(dev, PORT_D);
9806 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 9807 int found;
270b3042
DV		 9808 dpd_is_edp = intel_dpd_is_edp(dev);
9809
9810 if (has_edp_a(dev))
9811 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 9812
dc0fa718 9813 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 9814 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 9815 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 9816 if (!found)
e2debe91 9817 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 9818 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 9819 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 9820 }
9821
dc0fa718 9822 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 9823 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 9824
dc0fa718 9825 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 9826 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 9827
5eb08b69 9828 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 9829 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 9830
270b3042 9831 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 9832 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 9833 } else if (IS_VALLEYVIEW(dev)) {
19c03924 9834 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
6f6005a5
JB		 9835 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
9836 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
9837 PORT_C);
9838 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9839 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
9840 PORT_C);
9841 }
19c03924 9842
dc0fa718 9843 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 9844 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9845 PORT_B);
67cfc203
VS		 9846 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9847 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 9848 }
3cfca973
JN		 9849
9850 intel_dsi_init(dev);
103a196f 9851 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 9852 bool found = false;
7d57382e 9853
e2debe91 9854 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9855 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 9856 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 9857 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9858 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 9859 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 9860 }
27185ae1 9861
e7281eab 9862 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9863 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 9864 }
13520b05
KH		 9865
9866 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 9867
e2debe91 9868 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9869 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 9870 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 9871 }
27185ae1 9872
e2debe91 9873 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 9874
b01f2c3a
JB		 9875 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9876 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 9877 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 9878 }
e7281eab 9879 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9880 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 9881 }
27185ae1 9882
b01f2c3a 9883 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 9884 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 9885 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 9886 } else if (IS_GEN2(dev))
79e53945
JB		 9887 intel_dvo_init(dev);
9888
103a196f 9889 if (SUPPORTS_TV(dev))
79e53945
JB		 9890 intel_tv_init(dev);
9891
4ef69c7a
CW		 9892 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9893 encoder->base.possible_crtcs = encoder->crtc_mask;
9894 encoder->base.possible_clones =
66a9278e 9895 intel_encoder_clones(encoder);
79e53945 9896 }
47356eb6 9897
dde86e2d 9898 intel_init_pch_refclk(dev);
270b3042
DV		 9899
9900 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 9901}
9902
ddfe1567
CW		 9903void intel_framebuffer_fini(struct intel_framebuffer *fb)
9904{
9905 drm_framebuffer_cleanup(&fb->base);
9906 drm_gem_object_unreference_unlocked(&fb->obj->base);
9907}
9908
79e53945
JB		 9909static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9910{
9911 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 9912
ddfe1567 9913 intel_framebuffer_fini(intel_fb);
79e53945
JB		 9914 kfree(intel_fb);
9915}
9916
9917static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 9918 struct drm_file *file,
79e53945
JB		 9919 unsigned int *handle)
9920{
9921 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 9922 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 9923
05394f39 9924 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 9925}
9926
9927static const struct drm_framebuffer_funcs intel_fb_funcs = {
9928 .destroy = intel_user_framebuffer_destroy,
9929 .create_handle = intel_user_framebuffer_create_handle,
9930};
9931
38651674
DA		 9932int intel_framebuffer_init(struct drm_device *dev,
9933 struct intel_framebuffer *intel_fb,
308e5bcb 9934 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 9935 struct drm_i915_gem_object *obj)
79e53945 9936{
a35cdaa0 9937 int pitch_limit;
79e53945
JB		 9938 int ret;
9939
c16ed4be
CW		 9940 if (obj->tiling_mode == I915_TILING_Y) {
9941 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 9942 return -EINVAL;
c16ed4be 9943 }
57cd6508 9944
c16ed4be
CW		 9945 if (mode_cmd->pitches[0] & 63) {
9946 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9947 mode_cmd->pitches[0]);
57cd6508 9948 return -EINVAL;
c16ed4be 9949 }
57cd6508 9950
a35cdaa0
CW		 9951 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9952 pitch_limit = 32*1024;
9953 } else if (INTEL_INFO(dev)->gen >= 4) {
9954 if (obj->tiling_mode)
9955 pitch_limit = 16*1024;
9956 else
9957 pitch_limit = 32*1024;
9958 } else if (INTEL_INFO(dev)->gen >= 3) {
9959 if (obj->tiling_mode)
9960 pitch_limit = 8*1024;
9961 else
9962 pitch_limit = 16*1024;
9963 } else
9964 /* XXX DSPC is limited to 4k tiled */
9965 pitch_limit = 8*1024;
9966
9967 if (mode_cmd->pitches[0] > pitch_limit) {
9968 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9969 obj->tiling_mode ? "tiled" : "linear",
9970 mode_cmd->pitches[0], pitch_limit);
5d7bd705 9971 return -EINVAL;
c16ed4be 9972 }
5d7bd705
VS		 9973
9974 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 9975 mode_cmd->pitches[0] != obj->stride) {
9976 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9977 mode_cmd->pitches[0], obj->stride);
5d7bd705 9978 return -EINVAL;
c16ed4be 9979 }
5d7bd705 9980
57779d06 9981 /* Reject formats not supported by any plane early. */
308e5bcb 9982 switch (mode_cmd->pixel_format) {
57779d06 9983 case DRM_FORMAT_C8:
04b3924d
VS		 9984 case DRM_FORMAT_RGB565:
9985 case DRM_FORMAT_XRGB8888:
9986 case DRM_FORMAT_ARGB8888:
57779d06
VS		 9987 break;
9988 case DRM_FORMAT_XRGB1555:
9989 case DRM_FORMAT_ARGB1555:
c16ed4be 9990 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 9991 DRM_DEBUG("unsupported pixel format: %s\n",
9992 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9993 return -EINVAL;
c16ed4be 9994 }
57779d06
VS		 9995 break;
9996 case DRM_FORMAT_XBGR8888:
9997 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 9998 case DRM_FORMAT_XRGB2101010:
9999 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 10000 case DRM_FORMAT_XBGR2101010:
10001 case DRM_FORMAT_ABGR2101010:
c16ed4be 10002 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 10003 DRM_DEBUG("unsupported pixel format: %s\n",
10004 drm_get_format_name(mode_cmd->pixel_format));
57779d06 10005 return -EINVAL;
c16ed4be 10006 }
b5626747 10007 break;
04b3924d
VS		 10008 case DRM_FORMAT_YUYV:
10009 case DRM_FORMAT_UYVY:
10010 case DRM_FORMAT_YVYU:
10011 case DRM_FORMAT_VYUY:
c16ed4be 10012 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 10013 DRM_DEBUG("unsupported pixel format: %s\n",
10014 drm_get_format_name(mode_cmd->pixel_format));
57779d06 10015 return -EINVAL;
c16ed4be 10016 }
57cd6508
CW		 10017 break;
10018 default:
4ee62c76
VS		 10019 DRM_DEBUG("unsupported pixel format: %s\n",
10020 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 10021 return -EINVAL;
10022 }
10023
90f9a336
VS		 10024 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10025 if (mode_cmd->offsets[0] != 0)
10026 return -EINVAL;
10027
c7d73f6a
DV		 10028 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
10029 intel_fb->obj = obj;
10030
79e53945
JB		 10031 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
10032 if (ret) {
10033 DRM_ERROR("framebuffer init failed %d\n", ret);
10034 return ret;
10035 }
10036
79e53945
JB		 10037 return 0;
10038}
10039
79e53945
JB		 10040static struct drm_framebuffer *
10041intel_user_framebuffer_create(struct drm_device *dev,
10042 struct drm_file *filp,
308e5bcb 10043 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 10044{
05394f39 10045 struct drm_i915_gem_object *obj;
79e53945 10046
308e5bcb
JB		 10047 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
10048 mode_cmd->handles[0]));
c8725226 10049 if (&obj->base == NULL)
cce13ff7 10050 return ERR_PTR(-ENOENT);
79e53945 10051
d2dff872 10052 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 10053}
10054
79e53945 10055static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 10056 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 10057 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 10058};
10059
e70236a8
JB		 10060/* Set up chip specific display functions */
10061static void intel_init_display(struct drm_device *dev)
10062{
10063 struct drm_i915_private *dev_priv = dev->dev_private;
10064
ee9300bb
DV		 10065 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
10066 dev_priv->display.find_dpll = g4x_find_best_dpll;
10067 else if (IS_VALLEYVIEW(dev))
10068 dev_priv->display.find_dpll = vlv_find_best_dpll;
10069 else if (IS_PINEVIEW(dev))
10070 dev_priv->display.find_dpll = pnv_find_best_dpll;
10071 else
10072 dev_priv->display.find_dpll = i9xx_find_best_dpll;
10073
affa9354 10074 if (HAS_DDI(dev)) {
0e8ffe1b 10075 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 10076 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 10077 dev_priv->display.crtc_enable = haswell_crtc_enable;
10078 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 10079 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 10080 dev_priv->display.update_plane = ironlake_update_plane;
10081 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 10082 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 10083 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 10084 dev_priv->display.crtc_enable = ironlake_crtc_enable;
10085 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 10086 dev_priv->display.off = ironlake_crtc_off;
17638cd6 10087 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 10088 } else if (IS_VALLEYVIEW(dev)) {
10089 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10090 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10091 dev_priv->display.crtc_enable = valleyview_crtc_enable;
10092 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10093 dev_priv->display.off = i9xx_crtc_off;
10094 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 10095 } else {
0e8ffe1b 10096 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 10097 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 10098 dev_priv->display.crtc_enable = i9xx_crtc_enable;
10099 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 10100 dev_priv->display.off = i9xx_crtc_off;
17638cd6 10101 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 10102 }
e70236a8 10103
e70236a8 10104 /* Returns the core display clock speed */
25eb05fc
JB		 10105 if (IS_VALLEYVIEW(dev))
10106 dev_priv->display.get_display_clock_speed =
10107 valleyview_get_display_clock_speed;
10108 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 10109 dev_priv->display.get_display_clock_speed =
10110 i945_get_display_clock_speed;
10111 else if (IS_I915G(dev))
10112 dev_priv->display.get_display_clock_speed =
10113 i915_get_display_clock_speed;
257a7ffc 10114 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 10115 dev_priv->display.get_display_clock_speed =
10116 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 10117 else if (IS_PINEVIEW(dev))
10118 dev_priv->display.get_display_clock_speed =
10119 pnv_get_display_clock_speed;
e70236a8
JB		 10120 else if (IS_I915GM(dev))
10121 dev_priv->display.get_display_clock_speed =
10122 i915gm_get_display_clock_speed;
10123 else if (IS_I865G(dev))
10124 dev_priv->display.get_display_clock_speed =
10125 i865_get_display_clock_speed;
f0f8a9ce 10126 else if (IS_I85X(dev))
e70236a8
JB		 10127 dev_priv->display.get_display_clock_speed =
10128 i855_get_display_clock_speed;
10129 else /* 852, 830 */
10130 dev_priv->display.get_display_clock_speed =
10131 i830_get_display_clock_speed;
10132
7f8a8569 10133 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 10134 if (IS_GEN5(dev)) {
674cf967 10135 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 10136 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 10137 } else if (IS_GEN6(dev)) {
674cf967 10138 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 10139 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 10140 } else if (IS_IVYBRIDGE(dev)) {
10141 /* FIXME: detect B0+ stepping and use auto training */
10142 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 10143 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 10144 dev_priv->display.modeset_global_resources =
10145 ivb_modeset_global_resources;
c82e4d26
ED		 10146 } else if (IS_HASWELL(dev)) {
10147 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 10148 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 10149 dev_priv->display.modeset_global_resources =
10150 haswell_modeset_global_resources;
a0e63c22 10151 }
6067aaea 10152 } else if (IS_G4X(dev)) {
e0dac65e 10153 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 10154 }
8c9f3aaf
JB		 10155
10156 /* Default just returns -ENODEV to indicate unsupported */
10157 dev_priv->display.queue_flip = intel_default_queue_flip;
10158
10159 switch (INTEL_INFO(dev)->gen) {
10160 case 2:
10161 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10162 break;
10163
10164 case 3:
10165 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10166 break;
10167
10168 case 4:
10169 case 5:
10170 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10171 break;
10172
10173 case 6:
10174 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10175 break;
7c9017e5
JB		 10176 case 7:
10177 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10178 break;
8c9f3aaf 10179 }
e70236a8
JB		 10180}
10181
b690e96c
JB		 10182/*
10183 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10184 * resume, or other times. This quirk makes sure that's the case for
10185 * affected systems.
10186 */
0206e353 10187static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 10188{
10189 struct drm_i915_private *dev_priv = dev->dev_private;
10190
10191 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 10192 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 10193}
10194
435793df
KP		 10195/*
10196 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10197 */
10198static void quirk_ssc_force_disable(struct drm_device *dev)
10199{
10200 struct drm_i915_private *dev_priv = dev->dev_private;
10201 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 10202 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 10203}
10204
4dca20ef 10205/*
5a15ab5b
CE		 10206 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10207 * brightness value
4dca20ef
CE		 10208 */
10209static void quirk_invert_brightness(struct drm_device *dev)
10210{
10211 struct drm_i915_private *dev_priv = dev->dev_private;
10212 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 10213 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 10214}
10215
e85843be
KM		 10216/*
10217 * Some machines (Dell XPS13) suffer broken backlight controls if
10218 * BLM_PCH_PWM_ENABLE is set.
10219 */
10220static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
10221{
10222 struct drm_i915_private *dev_priv = dev->dev_private;
10223 dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
10224 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
10225}
10226
b690e96c
JB		 10227struct intel_quirk {
10228 int device;
10229 int subsystem_vendor;
10230 int subsystem_device;
10231 void (*hook)(struct drm_device *dev);
10232};
10233
5f85f176
EE		 10234/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10235struct intel_dmi_quirk {
10236 void (*hook)(struct drm_device *dev);
10237 const struct dmi_system_id (*dmi_id_list)[];
10238};
10239
10240static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10241{
10242 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10243 return 1;
10244}
10245
10246static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10247 {
10248 .dmi_id_list = &(const struct dmi_system_id[]) {
10249 {
10250 .callback = intel_dmi_reverse_brightness,
10251 .ident = "NCR Corporation",
10252 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10253 DMI_MATCH(DMI_PRODUCT_NAME, ""),
10254 },
10255 },
10256 { } /* terminating entry */
10257 },
10258 .hook = quirk_invert_brightness,
10259 },
10260};
10261
c43b5634 10262static struct intel_quirk intel_quirks[] = {
b690e96c 10263 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 10264 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 10265
b690e96c
JB		 10266 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10267 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10268
b690e96c
JB		 10269 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10270 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10271
ccd0d36e 10272 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 10273 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 10274 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 10275
10276 /* Lenovo U160 cannot use SSC on LVDS */
10277 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 10278
10279 /* Sony Vaio Y cannot use SSC on LVDS */
10280 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 10281
ee1452d7
JN		 10282 /*
10283 * All GM45 Acer (and its brands eMachines and Packard Bell) laptops
10284 * seem to use inverted backlight PWM.
10285 */
10286 { 0x2a42, 0x1025, PCI_ANY_ID, quirk_invert_brightness },
e85843be
KM		 10287
10288 /* Dell XPS13 HD Sandy Bridge */
10289 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10290 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10291 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
b690e96c
JB		 10292};
10293
10294static void intel_init_quirks(struct drm_device *dev)
10295{
10296 struct pci_dev *d = dev->pdev;
10297 int i;
10298
10299 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10300 struct intel_quirk *q = &intel_quirks[i];
10301
10302 if (d->device == q->device &&
10303 (d->subsystem_vendor == q->subsystem_vendor ||
10304 q->subsystem_vendor == PCI_ANY_ID) &&
10305 (d->subsystem_device == q->subsystem_device ||
10306 q->subsystem_device == PCI_ANY_ID))
10307 q->hook(dev);
10308 }
5f85f176
EE		 10309 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10310 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10311 intel_dmi_quirks[i].hook(dev);
10312 }
b690e96c
JB		 10313}
10314
9cce37f4
JB		 10315/* Disable the VGA plane that we never use */
10316static void i915_disable_vga(struct drm_device *dev)
10317{
10318 struct drm_i915_private *dev_priv = dev->dev_private;
10319 u8 sr1;
766aa1c4 10320 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 10321
10322 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 10323 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 10324 sr1 = inb(VGA_SR_DATA);
10325 outb(sr1 | 1<<5, VGA_SR_DATA);
10326 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10327 udelay(300);
10328
10329 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10330 POSTING_READ(vga_reg);
10331}
10332
6e1b4fda 10333static void i915_enable_vga_mem(struct drm_device *dev)
81b5c7bc
AW		 10334{
10335 /* Enable VGA memory on Intel HD */
10336 if (HAS_PCH_SPLIT(dev)) {
10337 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10338 outb(inb(VGA_MSR_READ) | VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10339 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10340 VGA_RSRC_LEGACY_MEM |
10341 VGA_RSRC_NORMAL_IO |
10342 VGA_RSRC_NORMAL_MEM);
10343 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10344 }
10345}
10346
6e1b4fda
VS		 10347void i915_disable_vga_mem(struct drm_device *dev)
10348{
10349 /* Disable VGA memory on Intel HD */
10350 if (HAS_PCH_SPLIT(dev)) {
10351 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10352 outb(inb(VGA_MSR_READ) & ~VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10353 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10354 VGA_RSRC_NORMAL_IO |
10355 VGA_RSRC_NORMAL_MEM);
10356 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10357 }
10358}
10359
f817586c
DV		 10360void intel_modeset_init_hw(struct drm_device *dev)
10361{
f6071166
JB		 10362 struct drm_i915_private *dev_priv = dev->dev_private;
10363
a8f78b58
ED		 10364 intel_prepare_ddi(dev);
10365
f817586c
DV		 10366 intel_init_clock_gating(dev);
10367
f6071166
JB		 10368 /* Enable the CRI clock source so we can get at the display */
10369 if (IS_VALLEYVIEW(dev))
10370 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
10371 DPLL_INTEGRATED_CRI_CLK_VLV);
10372
79f5b2c7 10373 mutex_lock(&dev->struct_mutex);
8090c6b9 10374 intel_enable_gt_powersave(dev);
79f5b2c7 10375 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 10376}
10377
7d708ee4
ID		 10378void intel_modeset_suspend_hw(struct drm_device *dev)
10379{
10380 intel_suspend_hw(dev);
10381}
10382
79e53945
JB		 10383void intel_modeset_init(struct drm_device *dev)
10384{
652c393a 10385 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 10386 int i, j, ret;
79e53945
JB		 10387
10388 drm_mode_config_init(dev);
10389
10390 dev->mode_config.min_width = 0;
10391 dev->mode_config.min_height = 0;
10392
019d96cb
DA		 10393 dev->mode_config.preferred_depth = 24;
10394 dev->mode_config.prefer_shadow = 1;
10395
e6ecefaa 10396 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 10397
b690e96c
JB		 10398 intel_init_quirks(dev);
10399
1fa61106
ED		 10400 intel_init_pm(dev);
10401
e3c74757
BW		 10402 if (INTEL_INFO(dev)->num_pipes == 0)
10403 return;
10404
e70236a8
JB		 10405 intel_init_display(dev);
10406
a6c45cf0
CW		 10407 if (IS_GEN2(dev)) {
10408 dev->mode_config.max_width = 2048;
10409 dev->mode_config.max_height = 2048;
10410 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 10411 dev->mode_config.max_width = 4096;
10412 dev->mode_config.max_height = 4096;
79e53945 10413 } else {
a6c45cf0
CW		 10414 dev->mode_config.max_width = 8192;
10415 dev->mode_config.max_height = 8192;
79e53945 10416 }
5d4545ae 10417 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 10418
28c97730 10419 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 10420 INTEL_INFO(dev)->num_pipes,
10421 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 10422
08e2a7de 10423 for_each_pipe(i) {
79e53945 10424 intel_crtc_init(dev, i);
7f1f3851
JB		 10425 for (j = 0; j < dev_priv->num_plane; j++) {
10426 ret = intel_plane_init(dev, i, j);
10427 if (ret)
06da8da2
VS		 10428 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10429 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 10430 }
79e53945
JB		 10431 }
10432
79f689aa 10433 intel_cpu_pll_init(dev);
e72f9fbf 10434 intel_shared_dpll_init(dev);
ee7b9f93 10435
9cce37f4
JB		 10436 /* Just disable it once at startup */
10437 i915_disable_vga(dev);
79e53945 10438 intel_setup_outputs(dev);
11be49eb
CW		 10439
10440 /* Just in case the BIOS is doing something questionable. */
10441 intel_disable_fbc(dev);
2c7111db
CW		 10442}
10443
24929352
DV		 10444static void
10445intel_connector_break_all_links(struct intel_connector *connector)
10446{
10447 connector->base.dpms = DRM_MODE_DPMS_OFF;
10448 connector->base.encoder = NULL;
10449 connector->encoder->connectors_active = false;
10450 connector->encoder->base.crtc = NULL;
10451}
10452
7fad798e
DV		 10453static void intel_enable_pipe_a(struct drm_device *dev)
10454{
10455 struct intel_connector *connector;
10456 struct drm_connector *crt = NULL;
10457 struct intel_load_detect_pipe load_detect_temp;
10458
10459 /* We can't just switch on the pipe A, we need to set things up with a
10460 * proper mode and output configuration. As a gross hack, enable pipe A
10461 * by enabling the load detect pipe once. */
10462 list_for_each_entry(connector,
10463 &dev->mode_config.connector_list,
10464 base.head) {
10465 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10466 crt = &connector->base;
10467 break;
10468 }
10469 }
10470
10471 if (!crt)
10472 return;
10473
10474 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10475 intel_release_load_detect_pipe(crt, &load_detect_temp);
10476
652c393a 10477
7fad798e
DV		 10478}
10479
fa555837
DV		 10480static bool
10481intel_check_plane_mapping(struct intel_crtc *crtc)
10482{
7eb552ae
BW		 10483 struct drm_device *dev = crtc->base.dev;
10484 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 10485 u32 reg, val;
10486
7eb552ae 10487 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 10488 return true;
10489
10490 reg = DSPCNTR(!crtc->plane);
10491 val = I915_READ(reg);
10492
10493 if ((val & DISPLAY_PLANE_ENABLE) &&
10494 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10495 return false;
10496
10497 return true;
10498}
10499
24929352
DV		 10500static void intel_sanitize_crtc(struct intel_crtc *crtc)
10501{
10502 struct drm_device *dev = crtc->base.dev;
10503 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 10504 u32 reg;
24929352 10505
24929352 10506 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 10507 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 10508 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10509
10510 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 10511 * disable the crtc (and hence change the state) if it is wrong. Note
10512 * that gen4+ has a fixed plane -> pipe mapping. */
10513 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 10514 struct intel_connector *connector;
10515 bool plane;
10516
24929352
DV		 10517 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10518 crtc->base.base.id);
10519
10520 /* Pipe has the wrong plane attached and the plane is active.
10521 * Temporarily change the plane mapping and disable everything
10522 * ... */
10523 plane = crtc->plane;
10524 crtc->plane = !plane;
10525 dev_priv->display.crtc_disable(&crtc->base);
10526 crtc->plane = plane;
10527
10528 /* ... and break all links. */
10529 list_for_each_entry(connector, &dev->mode_config.connector_list,
10530 base.head) {
10531 if (connector->encoder->base.crtc != &crtc->base)
10532 continue;
10533
10534 intel_connector_break_all_links(connector);
10535 }
10536
10537 WARN_ON(crtc->active);
10538 crtc->base.enabled = false;
10539 }
24929352 10540
7fad798e
DV		 10541 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10542 crtc->pipe == PIPE_A && !crtc->active) {
10543 /* BIOS forgot to enable pipe A, this mostly happens after
10544 * resume. Force-enable the pipe to fix this, the update_dpms
10545 * call below we restore the pipe to the right state, but leave
10546 * the required bits on. */
10547 intel_enable_pipe_a(dev);
10548 }
10549
24929352
DV		 10550 /* Adjust the state of the output pipe according to whether we
10551 * have active connectors/encoders. */
10552 intel_crtc_update_dpms(&crtc->base);
10553
10554 if (crtc->active != crtc->base.enabled) {
10555 struct intel_encoder *encoder;
10556
10557 /* This can happen either due to bugs in the get_hw_state
10558 * functions or because the pipe is force-enabled due to the
10559 * pipe A quirk. */
10560 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10561 crtc->base.base.id,
10562 crtc->base.enabled ? "enabled" : "disabled",
10563 crtc->active ? "enabled" : "disabled");
10564
10565 crtc->base.enabled = crtc->active;
10566
10567 /* Because we only establish the connector -> encoder ->
10568 * crtc links if something is active, this means the
10569 * crtc is now deactivated. Break the links. connector
10570 * -> encoder links are only establish when things are
10571 * actually up, hence no need to break them. */
10572 WARN_ON(crtc->active);
10573
10574 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10575 WARN_ON(encoder->connectors_active);
10576 encoder->base.crtc = NULL;
10577 }
10578 }
10579}
10580
10581static void intel_sanitize_encoder(struct intel_encoder *encoder)
10582{
10583 struct intel_connector *connector;
10584 struct drm_device *dev = encoder->base.dev;
10585
10586 /* We need to check both for a crtc link (meaning that the
10587 * encoder is active and trying to read from a pipe) and the
10588 * pipe itself being active. */
10589 bool has_active_crtc = encoder->base.crtc &&
10590 to_intel_crtc(encoder->base.crtc)->active;
10591
10592 if (encoder->connectors_active && !has_active_crtc) {
10593 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10594 encoder->base.base.id,
10595 drm_get_encoder_name(&encoder->base));
10596
10597 /* Connector is active, but has no active pipe. This is
10598 * fallout from our resume register restoring. Disable
10599 * the encoder manually again. */
10600 if (encoder->base.crtc) {
10601 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10602 encoder->base.base.id,
10603 drm_get_encoder_name(&encoder->base));
10604 encoder->disable(encoder);
10605 }
10606
10607 /* Inconsistent output/port/pipe state happens presumably due to
10608 * a bug in one of the get_hw_state functions. Or someplace else
10609 * in our code, like the register restore mess on resume. Clamp
10610 * things to off as a safer default. */
10611 list_for_each_entry(connector,
10612 &dev->mode_config.connector_list,
10613 base.head) {
10614 if (connector->encoder != encoder)
10615 continue;
10616
10617 intel_connector_break_all_links(connector);
10618 }
10619 }
10620 /* Enabled encoders without active connectors will be fixed in
10621 * the crtc fixup. */
10622}
10623
44cec740 10624void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 10625{
10626 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 10627 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 10628
8dc8a27c
PZ		 10629 /* This function can be called both from intel_modeset_setup_hw_state or
10630 * at a very early point in our resume sequence, where the power well
10631 * structures are not yet restored. Since this function is at a very
10632 * paranoid "someone might have enabled VGA while we were not looking"
10633 * level, just check if the power well is enabled instead of trying to
10634 * follow the "don't touch the power well if we don't need it" policy
10635 * the rest of the driver uses. */
10636 if (HAS_POWER_WELL(dev) &&
6aedd1f5 10637 (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
8dc8a27c
PZ		 10638 return;
10639
0fde901f
KM		 10640 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
10641 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 10642 i915_disable_vga(dev);
6e1b4fda 10643 i915_disable_vga_mem(dev);
0fde901f
KM		 10644 }
10645}
10646
30e984df 10647static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 10648{
10649 struct drm_i915_private *dev_priv = dev->dev_private;
10650 enum pipe pipe;
24929352
DV		 10651 struct intel_crtc *crtc;
10652 struct intel_encoder *encoder;
10653 struct intel_connector *connector;
5358901f 10654 int i;
24929352 10655
0e8ffe1b
DV		 10656 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10657 base.head) {
88adfff1 10658 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 10659
0e8ffe1b
DV		 10660 crtc->active = dev_priv->display.get_pipe_config(crtc,
10661 &crtc->config);
24929352
DV		 10662
10663 crtc->base.enabled = crtc->active;
10664
10665 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10666 crtc->base.base.id,
10667 crtc->active ? "enabled" : "disabled");
10668 }
10669
5358901f 10670 /* FIXME: Smash this into the new shared dpll infrastructure. */
affa9354 10671 if (HAS_DDI(dev))
6441ab5f
PZ		 10672 intel_ddi_setup_hw_pll_state(dev);
10673
5358901f
DV		 10674 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10675 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10676
10677 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10678 pll->active = 0;
10679 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10680 base.head) {
10681 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10682 pll->active++;
10683 }
10684 pll->refcount = pll->active;
10685
35c95375
DV		 10686 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10687 pll->name, pll->refcount, pll->on);
5358901f
DV		 10688 }
10689
24929352
DV		 10690 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10691 base.head) {
10692 pipe = 0;
10693
10694 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 10695 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10696 encoder->base.crtc = &crtc->base;
510d5f2f 10697 if (encoder->get_config)
045ac3b5 10698 encoder->get_config(encoder, &crtc->config);
24929352
DV		 10699 } else {
10700 encoder->base.crtc = NULL;
10701 }
10702
10703 encoder->connectors_active = false;
10704 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10705 encoder->base.base.id,
10706 drm_get_encoder_name(&encoder->base),
10707 encoder->base.crtc ? "enabled" : "disabled",
10708 pipe);
10709 }
10710
10711 list_for_each_entry(connector, &dev->mode_config.connector_list,
10712 base.head) {
10713 if (connector->get_hw_state(connector)) {
10714 connector->base.dpms = DRM_MODE_DPMS_ON;
10715 connector->encoder->connectors_active = true;
10716 connector->base.encoder = &connector->encoder->base;
10717 } else {
10718 connector->base.dpms = DRM_MODE_DPMS_OFF;
10719 connector->base.encoder = NULL;
10720 }
10721 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10722 connector->base.base.id,
10723 drm_get_connector_name(&connector->base),
10724 connector->base.encoder ? "enabled" : "disabled");
10725 }
30e984df
DV		 10726}
10727
10728/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10729 * and i915 state tracking structures. */
10730void intel_modeset_setup_hw_state(struct drm_device *dev,
10731 bool force_restore)
10732{
10733 struct drm_i915_private *dev_priv = dev->dev_private;
10734 enum pipe pipe;
30e984df
DV		 10735 struct intel_crtc *crtc;
10736 struct intel_encoder *encoder;
35c95375 10737 int i;
30e984df
DV		 10738
10739 intel_modeset_readout_hw_state(dev);
24929352 10740
babea61d
JB		 10741 /*
10742 * Now that we have the config, copy it to each CRTC struct
10743 * Note that this could go away if we move to using crtc_config
10744 * checking everywhere.
10745 */
10746 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10747 base.head) {
10748 if (crtc->active && i915_fastboot) {
10749 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10750
10751 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10752 crtc->base.base.id);
10753 drm_mode_debug_printmodeline(&crtc->base.mode);
10754 }
10755 }
10756
24929352
DV		 10757 /* HW state is read out, now we need to sanitize this mess. */
10758 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10759 base.head) {
10760 intel_sanitize_encoder(encoder);
10761 }
10762
10763 for_each_pipe(pipe) {
10764 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10765 intel_sanitize_crtc(crtc);
c0b03411 10766 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 10767 }
9a935856 10768
35c95375
DV		 10769 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10770 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10771
10772 if (!pll->on || pll->active)
10773 continue;
10774
10775 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10776
10777 pll->disable(dev_priv, pll);
10778 pll->on = false;
10779 }
10780
45e2b5f6 10781 if (force_restore) {
7d0bc1ea
VS		 10782 i915_redisable_vga(dev);
10783
f30da187
DV		 10784 /*
10785 * We need to use raw interfaces for restoring state to avoid
10786 * checking (bogus) intermediate states.
10787 */
45e2b5f6 10788 for_each_pipe(pipe) {
b5644d05
JB		 10789 struct drm_crtc *crtc =
10790 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 10791
10792 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10793 crtc->fb);
45e2b5f6
DV		 10794 }
10795 } else {
10796 intel_modeset_update_staged_output_state(dev);
10797 }
8af6cf88
DV		 10798
10799 intel_modeset_check_state(dev);
2e938892
DV		 10800
10801 drm_mode_config_reset(dev);
2c7111db
CW		 10802}
10803
10804void intel_modeset_gem_init(struct drm_device *dev)
10805{
1833b134 10806 intel_modeset_init_hw(dev);
02e792fb
DV		 10807
10808 intel_setup_overlay(dev);
24929352 10809
45e2b5f6 10810 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 10811}
10812
10813void intel_modeset_cleanup(struct drm_device *dev)
10814{
652c393a
JB		 10815 struct drm_i915_private *dev_priv = dev->dev_private;
10816 struct drm_crtc *crtc;
d9255d57 10817 struct drm_connector *connector;
652c393a 10818
fd0c0642
DV		 10819 /*
10820 * Interrupts and polling as the first thing to avoid creating havoc.
10821 * Too much stuff here (turning of rps, connectors, ...) would
10822 * experience fancy races otherwise.
10823 */
10824 drm_irq_uninstall(dev);
10825 cancel_work_sync(&dev_priv->hotplug_work);
10826 /*
10827 * Due to the hpd irq storm handling the hotplug work can re-arm the
10828 * poll handlers. Hence disable polling after hpd handling is shut down.
10829 */
f87ea761 10830 drm_kms_helper_poll_fini(dev);
fd0c0642 10831
652c393a
JB		 10832 mutex_lock(&dev->struct_mutex);
10833
723bfd70
JB		 10834 intel_unregister_dsm_handler();
10835
652c393a
JB		 10836 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10837 /* Skip inactive CRTCs */
10838 if (!crtc->fb)
10839 continue;
10840
3dec0095 10841 intel_increase_pllclock(crtc);
652c393a
JB		 10842 }
10843
973d04f9 10844 intel_disable_fbc(dev);
e70236a8 10845
6e1b4fda 10846 i915_enable_vga_mem(dev);
81b5c7bc 10847
8090c6b9 10848 intel_disable_gt_powersave(dev);
0cdab21f 10849
930ebb46
DV		 10850 ironlake_teardown_rc6(dev);
10851
69341a5e
KH		 10852 mutex_unlock(&dev->struct_mutex);
10853
1630fe75
CW		 10854 /* flush any delayed tasks or pending work */
10855 flush_scheduled_work();
10856
dc652f90
JN		 10857 /* destroy backlight, if any, before the connectors */
10858 intel_panel_destroy_backlight(dev);
10859
d9255d57
PZ		 10860 /* destroy the sysfs files before encoders/connectors */
10861 list_for_each_entry(connector, &dev->mode_config.connector_list, head)
10862 drm_sysfs_connector_remove(connector);
10863
79e53945 10864 drm_mode_config_cleanup(dev);
4d7bb011
DV		 10865
10866 intel_cleanup_overlay(dev);
79e53945
JB		 10867}
10868
f1c79df3
ZW		 10869/*
10870 * Return which encoder is currently attached for connector.
10871 */
df0e9248 10872struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 10873{
df0e9248
CW		 10874 return &intel_attached_encoder(connector)->base;
10875}
f1c79df3 10876
df0e9248
CW		 10877void intel_connector_attach_encoder(struct intel_connector *connector,
10878 struct intel_encoder *encoder)
10879{
10880 connector->encoder = encoder;
10881 drm_mode_connector_attach_encoder(&connector->base,
10882 &encoder->base);
79e53945 10883}
28d52043
DA		 10884
10885/*
10886 * set vga decode state - true == enable VGA decode
10887 */
10888int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10889{
10890 struct drm_i915_private *dev_priv = dev->dev_private;
10891 u16 gmch_ctrl;
10892
10893 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10894 if (state)
10895 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10896 else
10897 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10898 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10899 return 0;
10900}
c4a1d9e4 10901
c4a1d9e4 10902struct intel_display_error_state {
ff57f1b0
PZ		 10903
10904 u32 power_well_driver;
10905
63b66e5b
CW		 10906 int num_transcoders;
10907
c4a1d9e4
CW		 10908 struct intel_cursor_error_state {
10909 u32 control;
10910 u32 position;
10911 u32 base;
10912 u32 size;
52331309 10913 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 10914
10915 struct intel_pipe_error_state {
c4a1d9e4 10916 u32 source;
52331309 10917 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 10918
10919 struct intel_plane_error_state {
10920 u32 control;
10921 u32 stride;
10922 u32 size;
10923 u32 pos;
10924 u32 addr;
10925 u32 surface;
10926 u32 tile_offset;
52331309 10927 } plane[I915_MAX_PIPES];
63b66e5b
CW		 10928
10929 struct intel_transcoder_error_state {
10930 enum transcoder cpu_transcoder;
10931
10932 u32 conf;
10933
10934 u32 htotal;
10935 u32 hblank;
10936 u32 hsync;
10937 u32 vtotal;
10938 u32 vblank;
10939 u32 vsync;
10940 } transcoder[4];
c4a1d9e4
CW		 10941};
10942
10943struct intel_display_error_state *
10944intel_display_capture_error_state(struct drm_device *dev)
10945{
0206e353 10946 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 10947 struct intel_display_error_state *error;
63b66e5b
CW		 10948 int transcoders[] = {
10949 TRANSCODER_A,
10950 TRANSCODER_B,
10951 TRANSCODER_C,
10952 TRANSCODER_EDP,
10953 };
c4a1d9e4
CW		 10954 int i;
10955
63b66e5b
CW		 10956 if (INTEL_INFO(dev)->num_pipes == 0)
10957 return NULL;
10958
c4a1d9e4
CW		 10959 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10960 if (error == NULL)
10961 return NULL;
10962
ff57f1b0
PZ		 10963 if (HAS_POWER_WELL(dev))
10964 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10965
52331309 10966 for_each_pipe(i) {
a18c4c3d
PZ		 10967 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10968 error->cursor[i].control = I915_READ(CURCNTR(i));
10969 error->cursor[i].position = I915_READ(CURPOS(i));
10970 error->cursor[i].base = I915_READ(CURBASE(i));
10971 } else {
10972 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10973 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10974 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10975 }
c4a1d9e4
CW		 10976
10977 error->plane[i].control = I915_READ(DSPCNTR(i));
10978 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 10979 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 10980 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 10981 error->plane[i].pos = I915_READ(DSPPOS(i));
10982 }
ca291363
PZ		 10983 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10984 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 10985 if (INTEL_INFO(dev)->gen >= 4) {
10986 error->plane[i].surface = I915_READ(DSPSURF(i));
10987 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10988 }
10989
c4a1d9e4 10990 error->pipe[i].source = I915_READ(PIPESRC(i));
63b66e5b
CW		 10991 }
10992
10993 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
10994 if (HAS_DDI(dev_priv->dev))
10995 error->num_transcoders++; /* Account for eDP. */
10996
10997 for (i = 0; i < error->num_transcoders; i++) {
10998 enum transcoder cpu_transcoder = transcoders[i];
10999
11000 error->transcoder[i].cpu_transcoder = cpu_transcoder;
11001
11002 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
11003 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
11004 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
11005 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
11006 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
11007 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
11008 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 11009 }
11010
12d217c7
PZ		 11011 /* In the code above we read the registers without checking if the power
11012 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
11013 * prevent the next I915_WRITE from detecting it and printing an error
11014 * message. */
907b28c5 11015 intel_uncore_clear_errors(dev);
12d217c7 11016
c4a1d9e4
CW		 11017 return error;
11018}
11019
edc3d884
MK		 11020#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
11021
c4a1d9e4 11022void
edc3d884 11023intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 11024 struct drm_device *dev,
11025 struct intel_display_error_state *error)
11026{
11027 int i;
11028
63b66e5b
CW		 11029 if (!error)
11030 return;
11031
edc3d884 11032 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 11033 if (HAS_POWER_WELL(dev))
edc3d884 11034 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 11035 error->power_well_driver);
52331309 11036 for_each_pipe(i) {
edc3d884 11037 err_printf(m, "Pipe [%d]:\n", i);
edc3d884 11038 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
edc3d884
MK		 11039
11040 err_printf(m, "Plane [%d]:\n", i);
11041 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
11042 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 11043 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 11044 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
11045 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 11046 }
4b71a570 11047 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 11048 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 11049 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 11050 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
11051 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 11052 }
11053
edc3d884
MK		 11054 err_printf(m, "Cursor [%d]:\n", i);
11055 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
11056 err_printf(m, " POS: %08x\n", error->cursor[i].position);
11057 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 11058 }
63b66e5b
CW		 11059
11060 for (i = 0; i < error->num_transcoders; i++) {
11061 err_printf(m, " CPU transcoder: %c\n",
11062 transcoder_name(error->transcoder[i].cpu_transcoder));
11063 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
11064 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
11065 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
11066 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
11067 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
11068 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
11069 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
11070 }
c4a1d9e4 11071}
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