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drm/i915/dvo: switch ->mode_fixup to ->compute_config
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
f1f644dc
JB		 48static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
49 struct intel_crtc_config *pipe_config);
50static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
51 struct intel_crtc_config *pipe_config);
52
79e53945 53typedef struct {
0206e353 54 int min, max;
79e53945
JB		 55} intel_range_t;
56
57typedef struct {
0206e353
AJ		 58 int dot_limit;
59 int p2_slow, p2_fast;
79e53945
JB		 60} intel_p2_t;
61
62#define INTEL_P2_NUM 2
d4906093
ML		 63typedef struct intel_limit intel_limit_t;
64struct intel_limit {
0206e353
AJ		 65 intel_range_t dot, vco, n, m, m1, m2, p, p1;
66 intel_p2_t p2;
d4906093 67};
79e53945 68
2377b741
JB		 69/* FDI */
70#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
71
d2acd215
DV		 72int
73intel_pch_rawclk(struct drm_device *dev)
74{
75 struct drm_i915_private *dev_priv = dev->dev_private;
76
77 WARN_ON(!HAS_PCH_SPLIT(dev));
78
79 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
80}
81
021357ac
CW		 82static inline u32 /* units of 100MHz */
83intel_fdi_link_freq(struct drm_device *dev)
84{
8b99e68c
CW		 85 if (IS_GEN5(dev)) {
86 struct drm_i915_private *dev_priv = dev->dev_private;
87 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
88 } else
89 return 27;
021357ac
CW		 90}
91
5d536e28 92static const intel_limit_t intel_limits_i8xx_dac = {
0206e353
AJ		 93 .dot = { .min = 25000, .max = 350000 },
94 .vco = { .min = 930000, .max = 1400000 },
95 .n = { .min = 3, .max = 16 },
96 .m = { .min = 96, .max = 140 },
97 .m1 = { .min = 18, .max = 26 },
98 .m2 = { .min = 6, .max = 16 },
99 .p = { .min = 4, .max = 128 },
100 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 101 .p2 = { .dot_limit = 165000,
102 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 103};
104
5d536e28
DV		 105static const intel_limit_t intel_limits_i8xx_dvo = {
106 .dot = { .min = 25000, .max = 350000 },
107 .vco = { .min = 930000, .max = 1400000 },
108 .n = { .min = 3, .max = 16 },
109 .m = { .min = 96, .max = 140 },
110 .m1 = { .min = 18, .max = 26 },
111 .m2 = { .min = 6, .max = 16 },
112 .p = { .min = 4, .max = 128 },
113 .p1 = { .min = 2, .max = 33 },
114 .p2 = { .dot_limit = 165000,
115 .p2_slow = 4, .p2_fast = 4 },
116};
117
e4b36699 118static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 119 .dot = { .min = 25000, .max = 350000 },
120 .vco = { .min = 930000, .max = 1400000 },
121 .n = { .min = 3, .max = 16 },
122 .m = { .min = 96, .max = 140 },
123 .m1 = { .min = 18, .max = 26 },
124 .m2 = { .min = 6, .max = 16 },
125 .p = { .min = 4, .max = 128 },
126 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 127 .p2 = { .dot_limit = 165000,
128 .p2_slow = 14, .p2_fast = 7 },
e4b36699 129};
273e27ca 130
e4b36699 131static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 132 .dot = { .min = 20000, .max = 400000 },
133 .vco = { .min = 1400000, .max = 2800000 },
134 .n = { .min = 1, .max = 6 },
135 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 136 .m1 = { .min = 8, .max = 18 },
137 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 138 .p = { .min = 5, .max = 80 },
139 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 140 .p2 = { .dot_limit = 200000,
141 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 142};
143
144static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 145 .dot = { .min = 20000, .max = 400000 },
146 .vco = { .min = 1400000, .max = 2800000 },
147 .n = { .min = 1, .max = 6 },
148 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 149 .m1 = { .min = 8, .max = 18 },
150 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 151 .p = { .min = 7, .max = 98 },
152 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 153 .p2 = { .dot_limit = 112000,
154 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 155};
156
273e27ca 157
e4b36699 158static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 159 .dot = { .min = 25000, .max = 270000 },
160 .vco = { .min = 1750000, .max = 3500000},
161 .n = { .min = 1, .max = 4 },
162 .m = { .min = 104, .max = 138 },
163 .m1 = { .min = 17, .max = 23 },
164 .m2 = { .min = 5, .max = 11 },
165 .p = { .min = 10, .max = 30 },
166 .p1 = { .min = 1, .max = 3},
167 .p2 = { .dot_limit = 270000,
168 .p2_slow = 10,
169 .p2_fast = 10
044c7c41 170 },
e4b36699
KP		 171};
172
173static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 174 .dot = { .min = 22000, .max = 400000 },
175 .vco = { .min = 1750000, .max = 3500000},
176 .n = { .min = 1, .max = 4 },
177 .m = { .min = 104, .max = 138 },
178 .m1 = { .min = 16, .max = 23 },
179 .m2 = { .min = 5, .max = 11 },
180 .p = { .min = 5, .max = 80 },
181 .p1 = { .min = 1, .max = 8},
182 .p2 = { .dot_limit = 165000,
183 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 184};
185
186static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 187 .dot = { .min = 20000, .max = 115000 },
188 .vco = { .min = 1750000, .max = 3500000 },
189 .n = { .min = 1, .max = 3 },
190 .m = { .min = 104, .max = 138 },
191 .m1 = { .min = 17, .max = 23 },
192 .m2 = { .min = 5, .max = 11 },
193 .p = { .min = 28, .max = 112 },
194 .p1 = { .min = 2, .max = 8 },
195 .p2 = { .dot_limit = 0,
196 .p2_slow = 14, .p2_fast = 14
044c7c41 197 },
e4b36699
KP		 198};
199
200static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 201 .dot = { .min = 80000, .max = 224000 },
202 .vco = { .min = 1750000, .max = 3500000 },
203 .n = { .min = 1, .max = 3 },
204 .m = { .min = 104, .max = 138 },
205 .m1 = { .min = 17, .max = 23 },
206 .m2 = { .min = 5, .max = 11 },
207 .p = { .min = 14, .max = 42 },
208 .p1 = { .min = 2, .max = 6 },
209 .p2 = { .dot_limit = 0,
210 .p2_slow = 7, .p2_fast = 7
044c7c41 211 },
e4b36699
KP		 212};
213
f2b115e6 214static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 215 .dot = { .min = 20000, .max = 400000},
216 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 217 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 218 .n = { .min = 3, .max = 6 },
219 .m = { .min = 2, .max = 256 },
273e27ca 220 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 221 .m1 = { .min = 0, .max = 0 },
222 .m2 = { .min = 0, .max = 254 },
223 .p = { .min = 5, .max = 80 },
224 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 225 .p2 = { .dot_limit = 200000,
226 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 227};
228
f2b115e6 229static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 230 .dot = { .min = 20000, .max = 400000 },
231 .vco = { .min = 1700000, .max = 3500000 },
232 .n = { .min = 3, .max = 6 },
233 .m = { .min = 2, .max = 256 },
234 .m1 = { .min = 0, .max = 0 },
235 .m2 = { .min = 0, .max = 254 },
236 .p = { .min = 7, .max = 112 },
237 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 238 .p2 = { .dot_limit = 112000,
239 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 240};
241
273e27ca
EA		 242/* Ironlake / Sandybridge
243 *
244 * We calculate clock using (register_value + 2) for N/M1/M2, so here
245 * the range value for them is (actual_value - 2).
246 */
b91ad0ec 247static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 248 .dot = { .min = 25000, .max = 350000 },
249 .vco = { .min = 1760000, .max = 3510000 },
250 .n = { .min = 1, .max = 5 },
251 .m = { .min = 79, .max = 127 },
252 .m1 = { .min = 12, .max = 22 },
253 .m2 = { .min = 5, .max = 9 },
254 .p = { .min = 5, .max = 80 },
255 .p1 = { .min = 1, .max = 8 },
256 .p2 = { .dot_limit = 225000,
257 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 258};
259
b91ad0ec 260static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 261 .dot = { .min = 25000, .max = 350000 },
262 .vco = { .min = 1760000, .max = 3510000 },
263 .n = { .min = 1, .max = 3 },
264 .m = { .min = 79, .max = 118 },
265 .m1 = { .min = 12, .max = 22 },
266 .m2 = { .min = 5, .max = 9 },
267 .p = { .min = 28, .max = 112 },
268 .p1 = { .min = 2, .max = 8 },
269 .p2 = { .dot_limit = 225000,
270 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 271};
272
273static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 274 .dot = { .min = 25000, .max = 350000 },
275 .vco = { .min = 1760000, .max = 3510000 },
276 .n = { .min = 1, .max = 3 },
277 .m = { .min = 79, .max = 127 },
278 .m1 = { .min = 12, .max = 22 },
279 .m2 = { .min = 5, .max = 9 },
280 .p = { .min = 14, .max = 56 },
281 .p1 = { .min = 2, .max = 8 },
282 .p2 = { .dot_limit = 225000,
283 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 284};
285
273e27ca 286/* LVDS 100mhz refclk limits. */
b91ad0ec 287static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 288 .dot = { .min = 25000, .max = 350000 },
289 .vco = { .min = 1760000, .max = 3510000 },
290 .n = { .min = 1, .max = 2 },
291 .m = { .min = 79, .max = 126 },
292 .m1 = { .min = 12, .max = 22 },
293 .m2 = { .min = 5, .max = 9 },
294 .p = { .min = 28, .max = 112 },
0206e353 295 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 296 .p2 = { .dot_limit = 225000,
297 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 298};
299
300static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 301 .dot = { .min = 25000, .max = 350000 },
302 .vco = { .min = 1760000, .max = 3510000 },
303 .n = { .min = 1, .max = 3 },
304 .m = { .min = 79, .max = 126 },
305 .m1 = { .min = 12, .max = 22 },
306 .m2 = { .min = 5, .max = 9 },
307 .p = { .min = 14, .max = 42 },
0206e353 308 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 309 .p2 = { .dot_limit = 225000,
310 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 311};
312
a0c4da24
JB		 313static const intel_limit_t intel_limits_vlv_dac = {
314 .dot = { .min = 25000, .max = 270000 },
315 .vco = { .min = 4000000, .max = 6000000 },
316 .n = { .min = 1, .max = 7 },
317 .m = { .min = 22, .max = 450 }, /* guess */
318 .m1 = { .min = 2, .max = 3 },
319 .m2 = { .min = 11, .max = 156 },
320 .p = { .min = 10, .max = 30 },
75e53986 321 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 322 .p2 = { .dot_limit = 270000,
323 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 324};
325
326static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 327 .dot = { .min = 25000, .max = 270000 },
328 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 329 .n = { .min = 1, .max = 7 },
330 .m = { .min = 60, .max = 300 }, /* guess */
331 .m1 = { .min = 2, .max = 3 },
332 .m2 = { .min = 11, .max = 156 },
333 .p = { .min = 10, .max = 30 },
334 .p1 = { .min = 2, .max = 3 },
335 .p2 = { .dot_limit = 270000,
336 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 337};
338
339static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 340 .dot = { .min = 25000, .max = 270000 },
341 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 342 .n = { .min = 1, .max = 7 },
74a4dd2e 343 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 344 .m1 = { .min = 2, .max = 3 },
345 .m2 = { .min = 11, .max = 156 },
346 .p = { .min = 10, .max = 30 },
75e53986 347 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 348 .p2 = { .dot_limit = 270000,
349 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 350};
351
1b894b59
CW		 352static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
353 int refclk)
2c07245f 354{
b91ad0ec 355 struct drm_device *dev = crtc->dev;
2c07245f 356 const intel_limit_t *limit;
b91ad0ec
ZW		 357
358 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 359 if (intel_is_dual_link_lvds(dev)) {
1b894b59 360 if (refclk == 100000)
b91ad0ec
ZW		 361 limit = &intel_limits_ironlake_dual_lvds_100m;
362 else
363 limit = &intel_limits_ironlake_dual_lvds;
364 } else {
1b894b59 365 if (refclk == 100000)
b91ad0ec
ZW		 366 limit = &intel_limits_ironlake_single_lvds_100m;
367 else
368 limit = &intel_limits_ironlake_single_lvds;
369 }
c6bb3538 370 } else
b91ad0ec 371 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 372
373 return limit;
374}
375
044c7c41
ML		 376static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
377{
378 struct drm_device *dev = crtc->dev;
044c7c41
ML		 379 const intel_limit_t *limit;
380
381 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 382 if (intel_is_dual_link_lvds(dev))
e4b36699 383 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 384 else
e4b36699 385 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 386 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
387 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 388 limit = &intel_limits_g4x_hdmi;
044c7c41 389 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 390 limit = &intel_limits_g4x_sdvo;
044c7c41 391 } else /* The option is for other outputs */
e4b36699 392 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 393
394 return limit;
395}
396
1b894b59 397static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 398{
399 struct drm_device *dev = crtc->dev;
400 const intel_limit_t *limit;
401
bad720ff 402 if (HAS_PCH_SPLIT(dev))
1b894b59 403 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 404 else if (IS_G4X(dev)) {
044c7c41 405 limit = intel_g4x_limit(crtc);
f2b115e6 406 } else if (IS_PINEVIEW(dev)) {
2177832f 407 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 408 limit = &intel_limits_pineview_lvds;
2177832f 409 else
f2b115e6 410 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 411 } else if (IS_VALLEYVIEW(dev)) {
412 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
413 limit = &intel_limits_vlv_dac;
414 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
415 limit = &intel_limits_vlv_hdmi;
416 else
417 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 418 } else if (!IS_GEN2(dev)) {
419 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
420 limit = &intel_limits_i9xx_lvds;
421 else
422 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 423 } else {
424 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 425 limit = &intel_limits_i8xx_lvds;
5d536e28 426 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
e4b36699 427 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 428 else
429 limit = &intel_limits_i8xx_dac;
79e53945
JB		 430 }
431 return limit;
432}
433
f2b115e6
AJ		 434/* m1 is reserved as 0 in Pineview, n is a ring counter */
435static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 436{
2177832f
SL		 437 clock->m = clock->m2 + 2;
438 clock->p = clock->p1 * clock->p2;
439 clock->vco = refclk * clock->m / clock->n;
440 clock->dot = clock->vco / clock->p;
441}
442
7429e9d4
DV		 443static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
444{
445 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
446}
447
ac58c3f0 448static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 449{
7429e9d4 450 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 451 clock->p = clock->p1 * clock->p2;
452 clock->vco = refclk * clock->m / (clock->n + 2);
453 clock->dot = clock->vco / clock->p;
454}
455
79e53945
JB		 456/**
457 * Returns whether any output on the specified pipe is of the specified type
458 */
4ef69c7a 459bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 460{
4ef69c7a 461 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 462 struct intel_encoder *encoder;
463
6c2b7c12
DV		 464 for_each_encoder_on_crtc(dev, crtc, encoder)
465 if (encoder->type == type)
4ef69c7a
CW		 466 return true;
467
468 return false;
79e53945
JB		 469}
470
7c04d1d9 471#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 472/**
473 * Returns whether the given set of divisors are valid for a given refclk with
474 * the given connectors.
475 */
476
1b894b59
CW		 477static bool intel_PLL_is_valid(struct drm_device *dev,
478 const intel_limit_t *limit,
479 const intel_clock_t *clock)
79e53945 480{
79e53945 481 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 482 INTELPllInvalid("p1 out of range\n");
79e53945 483 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 484 INTELPllInvalid("p out of range\n");
79e53945 485 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 486 INTELPllInvalid("m2 out of range\n");
79e53945 487 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 488 INTELPllInvalid("m1 out of range\n");
f2b115e6 489 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 490 INTELPllInvalid("m1 <= m2\n");
79e53945 491 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 492 INTELPllInvalid("m out of range\n");
79e53945 493 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 494 INTELPllInvalid("n out of range\n");
79e53945 495 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 496 INTELPllInvalid("vco out of range\n");
79e53945
JB		 497 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
498 * connector, etc., rather than just a single range.
499 */
500 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 501 INTELPllInvalid("dot out of range\n");
79e53945
JB		 502
503 return true;
504}
505
d4906093 506static bool
ee9300bb 507i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 508 int target, int refclk, intel_clock_t *match_clock,
509 intel_clock_t *best_clock)
79e53945
JB		 510{
511 struct drm_device *dev = crtc->dev;
79e53945 512 intel_clock_t clock;
79e53945
JB		 513 int err = target;
514
a210b028 515 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 516 /*
a210b028
DV		 517 * For LVDS just rely on its current settings for dual-channel.
518 * We haven't figured out how to reliably set up different
519 * single/dual channel state, if we even can.
79e53945 520 */
1974cad0 521 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 522 clock.p2 = limit->p2.p2_fast;
523 else
524 clock.p2 = limit->p2.p2_slow;
525 } else {
526 if (target < limit->p2.dot_limit)
527 clock.p2 = limit->p2.p2_slow;
528 else
529 clock.p2 = limit->p2.p2_fast;
530 }
531
0206e353 532 memset(best_clock, 0, sizeof(*best_clock));
79e53945 533
42158660
ZY		 534 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
535 clock.m1++) {
536 for (clock.m2 = limit->m2.min;
537 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 538 if (clock.m2 >= clock.m1)
42158660
ZY		 539 break;
540 for (clock.n = limit->n.min;
541 clock.n <= limit->n.max; clock.n++) {
542 for (clock.p1 = limit->p1.min;
543 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 544 int this_err;
545
ac58c3f0
DV		 546 i9xx_clock(refclk, &clock);
547 if (!intel_PLL_is_valid(dev, limit,
548 &clock))
549 continue;
550 if (match_clock &&
551 clock.p != match_clock->p)
552 continue;
553
554 this_err = abs(clock.dot - target);
555 if (this_err < err) {
556 *best_clock = clock;
557 err = this_err;
558 }
559 }
560 }
561 }
562 }
563
564 return (err != target);
565}
566
567static bool
ee9300bb
DV		 568pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
569 int target, int refclk, intel_clock_t *match_clock,
570 intel_clock_t *best_clock)
79e53945
JB		 571{
572 struct drm_device *dev = crtc->dev;
79e53945 573 intel_clock_t clock;
79e53945
JB		 574 int err = target;
575
a210b028 576 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 577 /*
a210b028
DV		 578 * For LVDS just rely on its current settings for dual-channel.
579 * We haven't figured out how to reliably set up different
580 * single/dual channel state, if we even can.
79e53945 581 */
1974cad0 582 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 583 clock.p2 = limit->p2.p2_fast;
584 else
585 clock.p2 = limit->p2.p2_slow;
586 } else {
587 if (target < limit->p2.dot_limit)
588 clock.p2 = limit->p2.p2_slow;
589 else
590 clock.p2 = limit->p2.p2_fast;
591 }
592
0206e353 593 memset(best_clock, 0, sizeof(*best_clock));
79e53945 594
42158660
ZY		 595 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
596 clock.m1++) {
597 for (clock.m2 = limit->m2.min;
598 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 599 for (clock.n = limit->n.min;
600 clock.n <= limit->n.max; clock.n++) {
601 for (clock.p1 = limit->p1.min;
602 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 603 int this_err;
604
ac58c3f0 605 pineview_clock(refclk, &clock);
1b894b59
CW		 606 if (!intel_PLL_is_valid(dev, limit,
607 &clock))
79e53945 608 continue;
cec2f356
SP		 609 if (match_clock &&
610 clock.p != match_clock->p)
611 continue;
79e53945
JB		 612
613 this_err = abs(clock.dot - target);
614 if (this_err < err) {
615 *best_clock = clock;
616 err = this_err;
617 }
618 }
619 }
620 }
621 }
622
623 return (err != target);
624}
625
d4906093 626static bool
ee9300bb
DV		 627g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
628 int target, int refclk, intel_clock_t *match_clock,
629 intel_clock_t *best_clock)
d4906093
ML		 630{
631 struct drm_device *dev = crtc->dev;
d4906093
ML		 632 intel_clock_t clock;
633 int max_n;
634 bool found;
6ba770dc
AJ		 635 /* approximately equals target * 0.00585 */
636 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 637 found = false;
638
639 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 640 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 641 clock.p2 = limit->p2.p2_fast;
642 else
643 clock.p2 = limit->p2.p2_slow;
644 } else {
645 if (target < limit->p2.dot_limit)
646 clock.p2 = limit->p2.p2_slow;
647 else
648 clock.p2 = limit->p2.p2_fast;
649 }
650
651 memset(best_clock, 0, sizeof(*best_clock));
652 max_n = limit->n.max;
f77f13e2 653 /* based on hardware requirement, prefer smaller n to precision */
d4906093 654 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 655 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 656 for (clock.m1 = limit->m1.max;
657 clock.m1 >= limit->m1.min; clock.m1--) {
658 for (clock.m2 = limit->m2.max;
659 clock.m2 >= limit->m2.min; clock.m2--) {
660 for (clock.p1 = limit->p1.max;
661 clock.p1 >= limit->p1.min; clock.p1--) {
662 int this_err;
663
ac58c3f0 664 i9xx_clock(refclk, &clock);
1b894b59
CW		 665 if (!intel_PLL_is_valid(dev, limit,
666 &clock))
d4906093 667 continue;
1b894b59
CW		 668
669 this_err = abs(clock.dot - target);
d4906093
ML		 670 if (this_err < err_most) {
671 *best_clock = clock;
672 err_most = this_err;
673 max_n = clock.n;
674 found = true;
675 }
676 }
677 }
678 }
679 }
2c07245f
ZW		 680 return found;
681}
682
a0c4da24 683static bool
ee9300bb
DV		 684vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
685 int target, int refclk, intel_clock_t *match_clock,
686 intel_clock_t *best_clock)
a0c4da24
JB		 687{
688 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
689 u32 m, n, fastclk;
690 u32 updrate, minupdate, fracbits, p;
691 unsigned long bestppm, ppm, absppm;
692 int dotclk, flag;
693
af447bd3 694 flag = 0;
a0c4da24
JB		 695 dotclk = target * 1000;
696 bestppm = 1000000;
697 ppm = absppm = 0;
698 fastclk = dotclk / (2*100);
699 updrate = 0;
700 minupdate = 19200;
701 fracbits = 1;
702 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
703 bestm1 = bestm2 = bestp1 = bestp2 = 0;
704
705 /* based on hardware requirement, prefer smaller n to precision */
706 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
707 updrate = refclk / n;
708 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
709 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
710 if (p2 > 10)
711 p2 = p2 - 1;
712 p = p1 * p2;
713 /* based on hardware requirement, prefer bigger m1,m2 values */
714 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
715 m2 = (((2*(fastclk * p * n / m1 )) +
716 refclk) / (2*refclk));
717 m = m1 * m2;
718 vco = updrate * m;
719 if (vco >= limit->vco.min && vco < limit->vco.max) {
720 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
721 absppm = (ppm > 0) ? ppm : (-ppm);
722 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
723 bestppm = 0;
724 flag = 1;
725 }
726 if (absppm < bestppm - 10) {
727 bestppm = absppm;
728 flag = 1;
729 }
730 if (flag) {
731 bestn = n;
732 bestm1 = m1;
733 bestm2 = m2;
734 bestp1 = p1;
735 bestp2 = p2;
736 flag = 0;
737 }
738 }
739 }
740 }
741 }
742 }
743 best_clock->n = bestn;
744 best_clock->m1 = bestm1;
745 best_clock->m2 = bestm2;
746 best_clock->p1 = bestp1;
747 best_clock->p2 = bestp2;
748
749 return true;
750}
a4fc5ed6 751
a5c961d1
PZ		 752enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
753 enum pipe pipe)
754{
755 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
756 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
757
3b117c8f 758 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 759}
760
a928d536
PZ		 761static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
762{
763 struct drm_i915_private *dev_priv = dev->dev_private;
764 u32 frame, frame_reg = PIPEFRAME(pipe);
765
766 frame = I915_READ(frame_reg);
767
768 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
769 DRM_DEBUG_KMS("vblank wait timed out\n");
770}
771
9d0498a2
JB		 772/**
773 * intel_wait_for_vblank - wait for vblank on a given pipe
774 * @dev: drm device
775 * @pipe: pipe to wait for
776 *
777 * Wait for vblank to occur on a given pipe. Needed for various bits of
778 * mode setting code.
779 */
780void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 781{
9d0498a2 782 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 783 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 784
a928d536
PZ		 785 if (INTEL_INFO(dev)->gen >= 5) {
786 ironlake_wait_for_vblank(dev, pipe);
787 return;
788 }
789
300387c0
CW		 790 /* Clear existing vblank status. Note this will clear any other
791 * sticky status fields as well.
792 *
793 * This races with i915_driver_irq_handler() with the result
794 * that either function could miss a vblank event. Here it is not
795 * fatal, as we will either wait upon the next vblank interrupt or
796 * timeout. Generally speaking intel_wait_for_vblank() is only
797 * called during modeset at which time the GPU should be idle and
798 * should *not* be performing page flips and thus not waiting on
799 * vblanks...
800 * Currently, the result of us stealing a vblank from the irq
801 * handler is that a single frame will be skipped during swapbuffers.
802 */
803 I915_WRITE(pipestat_reg,
804 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
805
9d0498a2 806 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 807 if (wait_for(I915_READ(pipestat_reg) &
808 PIPE_VBLANK_INTERRUPT_STATUS,
809 50))
9d0498a2
JB		 810 DRM_DEBUG_KMS("vblank wait timed out\n");
811}
812
ab7ad7f6
KP		 813/*
814 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 815 * @dev: drm device
816 * @pipe: pipe to wait for
817 *
818 * After disabling a pipe, we can't wait for vblank in the usual way,
819 * spinning on the vblank interrupt status bit, since we won't actually
820 * see an interrupt when the pipe is disabled.
821 *
ab7ad7f6
KP		 822 * On Gen4 and above:
823 * wait for the pipe register state bit to turn off
824 *
825 * Otherwise:
826 * wait for the display line value to settle (it usually
827 * ends up stopping at the start of the next frame).
58e10eb9 828 *
9d0498a2 829 */
58e10eb9 830void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 831{
832 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 833 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
834 pipe);
ab7ad7f6
KP		 835
836 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 837 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 838
839 /* Wait for the Pipe State to go off */
58e10eb9
CW		 840 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
841 100))
284637d9 842 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 843 } else {
837ba00f 844 u32 last_line, line_mask;
58e10eb9 845 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 846 unsigned long timeout = jiffies + msecs_to_jiffies(100);
847
837ba00f
PZ		 848 if (IS_GEN2(dev))
849 line_mask = DSL_LINEMASK_GEN2;
850 else
851 line_mask = DSL_LINEMASK_GEN3;
852
ab7ad7f6
KP		 853 /* Wait for the display line to settle */
854 do {
837ba00f 855 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 856 mdelay(5);
837ba00f 857 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 858 time_after(timeout, jiffies));
859 if (time_after(jiffies, timeout))
284637d9 860 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 861 }
79e53945
JB		 862}
863
b0ea7d37
DL		 864/*
865 * ibx_digital_port_connected - is the specified port connected?
866 * @dev_priv: i915 private structure
867 * @port: the port to test
868 *
869 * Returns true if @port is connected, false otherwise.
870 */
871bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
872 struct intel_digital_port *port)
873{
874 u32 bit;
875
c36346e3
DL		 876 if (HAS_PCH_IBX(dev_priv->dev)) {
877 switch(port->port) {
878 case PORT_B:
879 bit = SDE_PORTB_HOTPLUG;
880 break;
881 case PORT_C:
882 bit = SDE_PORTC_HOTPLUG;
883 break;
884 case PORT_D:
885 bit = SDE_PORTD_HOTPLUG;
886 break;
887 default:
888 return true;
889 }
890 } else {
891 switch(port->port) {
892 case PORT_B:
893 bit = SDE_PORTB_HOTPLUG_CPT;
894 break;
895 case PORT_C:
896 bit = SDE_PORTC_HOTPLUG_CPT;
897 break;
898 case PORT_D:
899 bit = SDE_PORTD_HOTPLUG_CPT;
900 break;
901 default:
902 return true;
903 }
b0ea7d37
DL		 904 }
905
906 return I915_READ(SDEISR) & bit;
907}
908
b24e7179
JB		 909static const char *state_string(bool enabled)
910{
911 return enabled ? "on" : "off";
912}
913
914/* Only for pre-ILK configs */
55607e8a
DV		 915void assert_pll(struct drm_i915_private *dev_priv,
916 enum pipe pipe, bool state)
b24e7179
JB		 917{
918 int reg;
919 u32 val;
920 bool cur_state;
921
922 reg = DPLL(pipe);
923 val = I915_READ(reg);
924 cur_state = !!(val & DPLL_VCO_ENABLE);
925 WARN(cur_state != state,
926 "PLL state assertion failure (expected %s, current %s)\n",
927 state_string(state), state_string(cur_state));
928}
b24e7179 929
55607e8a 930struct intel_shared_dpll *
e2b78267
DV		 931intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
932{
933 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
934
a43f6e0f 935 if (crtc->config.shared_dpll < 0)
e2b78267
DV		 936 return NULL;
937
a43f6e0f 938 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
e2b78267
DV		 939}
940
040484af 941/* For ILK+ */
55607e8a
DV		 942void assert_shared_dpll(struct drm_i915_private *dev_priv,
943 struct intel_shared_dpll *pll,
944 bool state)
040484af 945{
040484af 946 bool cur_state;
5358901f 947 struct intel_dpll_hw_state hw_state;
040484af 948
9d82aa17
ED		 949 if (HAS_PCH_LPT(dev_priv->dev)) {
950 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
951 return;
952 }
953
92b27b08 954 if (WARN (!pll,
46edb027 955 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 956 return;
ee7b9f93 957
5358901f 958 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
92b27b08 959 WARN(cur_state != state,
5358901f
DV		 960 "%s assertion failure (expected %s, current %s)\n",
961 pll->name, state_string(state), state_string(cur_state));
040484af 962}
040484af
JB		 963
964static void assert_fdi_tx(struct drm_i915_private *dev_priv,
965 enum pipe pipe, bool state)
966{
967 int reg;
968 u32 val;
969 bool cur_state;
ad80a810
PZ		 970 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
971 pipe);
040484af 972
affa9354
PZ		 973 if (HAS_DDI(dev_priv->dev)) {
974 /* DDI does not have a specific FDI_TX register */
ad80a810 975 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 976 val = I915_READ(reg);
ad80a810 977 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 978 } else {
979 reg = FDI_TX_CTL(pipe);
980 val = I915_READ(reg);
981 cur_state = !!(val & FDI_TX_ENABLE);
982 }
040484af
JB		 983 WARN(cur_state != state,
984 "FDI TX state assertion failure (expected %s, current %s)\n",
985 state_string(state), state_string(cur_state));
986}
987#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
988#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
989
990static void assert_fdi_rx(struct drm_i915_private *dev_priv,
991 enum pipe pipe, bool state)
992{
993 int reg;
994 u32 val;
995 bool cur_state;
996
d63fa0dc
PZ		 997 reg = FDI_RX_CTL(pipe);
998 val = I915_READ(reg);
999 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1000 WARN(cur_state != state,
1001 "FDI RX state assertion failure (expected %s, current %s)\n",
1002 state_string(state), state_string(cur_state));
1003}
1004#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1005#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1006
1007static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1008 enum pipe pipe)
1009{
1010 int reg;
1011 u32 val;
1012
1013 /* ILK FDI PLL is always enabled */
1014 if (dev_priv->info->gen == 5)
1015 return;
1016
bf507ef7 1017 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1018 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1019 return;
1020
040484af
JB		 1021 reg = FDI_TX_CTL(pipe);
1022 val = I915_READ(reg);
1023 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1024}
1025
55607e8a
DV		 1026void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1027 enum pipe pipe, bool state)
040484af
JB		 1028{
1029 int reg;
1030 u32 val;
55607e8a 1031 bool cur_state;
040484af
JB		 1032
1033 reg = FDI_RX_CTL(pipe);
1034 val = I915_READ(reg);
55607e8a
DV		 1035 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1036 WARN(cur_state != state,
1037 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1038 state_string(state), state_string(cur_state));
040484af
JB		 1039}
1040
ea0760cf
JB		 1041static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1042 enum pipe pipe)
1043{
1044 int pp_reg, lvds_reg;
1045 u32 val;
1046 enum pipe panel_pipe = PIPE_A;
0de3b485 1047 bool locked = true;
ea0760cf
JB		 1048
1049 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1050 pp_reg = PCH_PP_CONTROL;
1051 lvds_reg = PCH_LVDS;
1052 } else {
1053 pp_reg = PP_CONTROL;
1054 lvds_reg = LVDS;
1055 }
1056
1057 val = I915_READ(pp_reg);
1058 if (!(val & PANEL_POWER_ON) ||
1059 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1060 locked = false;
1061
1062 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1063 panel_pipe = PIPE_B;
1064
1065 WARN(panel_pipe == pipe && locked,
1066 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1067 pipe_name(pipe));
ea0760cf
JB		 1068}
1069
b840d907
JB		 1070void assert_pipe(struct drm_i915_private *dev_priv,
1071 enum pipe pipe, bool state)
b24e7179
JB		 1072{
1073 int reg;
1074 u32 val;
63d7bbe9 1075 bool cur_state;
702e7a56
PZ		 1076 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1077 pipe);
b24e7179 1078
8e636784
DV		 1079 /* if we need the pipe A quirk it must be always on */
1080 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1081 state = true;
1082
b97186f0
PZ		 1083 if (!intel_display_power_enabled(dev_priv->dev,
1084 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1085 cur_state = false;
1086 } else {
1087 reg = PIPECONF(cpu_transcoder);
1088 val = I915_READ(reg);
1089 cur_state = !!(val & PIPECONF_ENABLE);
1090 }
1091
63d7bbe9
JB		 1092 WARN(cur_state != state,
1093 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1094 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1095}
1096
931872fc
CW		 1097static void assert_plane(struct drm_i915_private *dev_priv,
1098 enum plane plane, bool state)
b24e7179
JB		 1099{
1100 int reg;
1101 u32 val;
931872fc 1102 bool cur_state;
b24e7179
JB		 1103
1104 reg = DSPCNTR(plane);
1105 val = I915_READ(reg);
931872fc
CW		 1106 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1107 WARN(cur_state != state,
1108 "plane %c assertion failure (expected %s, current %s)\n",
1109 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1110}
1111
931872fc
CW		 1112#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1113#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1114
b24e7179
JB		 1115static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1116 enum pipe pipe)
1117{
653e1026 1118 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1119 int reg, i;
1120 u32 val;
1121 int cur_pipe;
1122
653e1026
VS		 1123 /* Primary planes are fixed to pipes on gen4+ */
1124 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1125 reg = DSPCNTR(pipe);
1126 val = I915_READ(reg);
1127 WARN((val & DISPLAY_PLANE_ENABLE),
1128 "plane %c assertion failure, should be disabled but not\n",
1129 plane_name(pipe));
19ec1358 1130 return;
28c05794 1131 }
19ec1358 1132
b24e7179 1133 /* Need to check both planes against the pipe */
08e2a7de 1134 for_each_pipe(i) {
b24e7179
JB		 1135 reg = DSPCNTR(i);
1136 val = I915_READ(reg);
1137 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1138 DISPPLANE_SEL_PIPE_SHIFT;
1139 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1140 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1141 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1142 }
1143}
1144
19332d7a
JB		 1145static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1146 enum pipe pipe)
1147{
20674eef 1148 struct drm_device *dev = dev_priv->dev;
19332d7a
JB		 1149 int reg, i;
1150 u32 val;
1151
20674eef
VS		 1152 if (IS_VALLEYVIEW(dev)) {
1153 for (i = 0; i < dev_priv->num_plane; i++) {
1154 reg = SPCNTR(pipe, i);
1155 val = I915_READ(reg);
1156 WARN((val & SP_ENABLE),
1157 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1158 sprite_name(pipe, i), pipe_name(pipe));
1159 }
1160 } else if (INTEL_INFO(dev)->gen >= 7) {
1161 reg = SPRCTL(pipe);
19332d7a 1162 val = I915_READ(reg);
20674eef 1163 WARN((val & SPRITE_ENABLE),
06da8da2 1164 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1165 plane_name(pipe), pipe_name(pipe));
1166 } else if (INTEL_INFO(dev)->gen >= 5) {
1167 reg = DVSCNTR(pipe);
19332d7a 1168 val = I915_READ(reg);
20674eef 1169 WARN((val & DVS_ENABLE),
06da8da2 1170 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1171 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1172 }
1173}
1174
92f2584a
JB		 1175static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1176{
1177 u32 val;
1178 bool enabled;
1179
9d82aa17
ED		 1180 if (HAS_PCH_LPT(dev_priv->dev)) {
1181 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1182 return;
1183 }
1184
92f2584a
JB		 1185 val = I915_READ(PCH_DREF_CONTROL);
1186 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1187 DREF_SUPERSPREAD_SOURCE_MASK));
1188 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1189}
1190
ab9412ba
DV		 1191static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1192 enum pipe pipe)
92f2584a
JB		 1193{
1194 int reg;
1195 u32 val;
1196 bool enabled;
1197
ab9412ba 1198 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1199 val = I915_READ(reg);
1200 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1201 WARN(enabled,
1202 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1203 pipe_name(pipe));
92f2584a
JB		 1204}
1205
4e634389
KP		 1206static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1207 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1208{
1209 if ((val & DP_PORT_EN) == 0)
1210 return false;
1211
1212 if (HAS_PCH_CPT(dev_priv->dev)) {
1213 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1214 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1215 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1216 return false;
1217 } else {
1218 if ((val & DP_PIPE_MASK) != (pipe << 30))
1219 return false;
1220 }
1221 return true;
1222}
1223
1519b995
KP		 1224static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1225 enum pipe pipe, u32 val)
1226{
dc0fa718 1227 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1228 return false;
1229
1230 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1231 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1232 return false;
1233 } else {
dc0fa718 1234 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1235 return false;
1236 }
1237 return true;
1238}
1239
1240static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1241 enum pipe pipe, u32 val)
1242{
1243 if ((val & LVDS_PORT_EN) == 0)
1244 return false;
1245
1246 if (HAS_PCH_CPT(dev_priv->dev)) {
1247 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1248 return false;
1249 } else {
1250 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1251 return false;
1252 }
1253 return true;
1254}
1255
1256static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1257 enum pipe pipe, u32 val)
1258{
1259 if ((val & ADPA_DAC_ENABLE) == 0)
1260 return false;
1261 if (HAS_PCH_CPT(dev_priv->dev)) {
1262 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1263 return false;
1264 } else {
1265 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1266 return false;
1267 }
1268 return true;
1269}
1270
291906f1 1271static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1272 enum pipe pipe, int reg, u32 port_sel)
291906f1 1273{
47a05eca 1274 u32 val = I915_READ(reg);
4e634389 1275 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1276 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1277 reg, pipe_name(pipe));
de9a35ab 1278
75c5da27
DV		 1279 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1280 && (val & DP_PIPEB_SELECT),
de9a35ab 1281 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1282}
1283
1284static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1285 enum pipe pipe, int reg)
1286{
47a05eca 1287 u32 val = I915_READ(reg);
b70ad586 1288 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1289 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1290 reg, pipe_name(pipe));
de9a35ab 1291
dc0fa718 1292 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1293 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1294 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1295}
1296
1297static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1298 enum pipe pipe)
1299{
1300 int reg;
1301 u32 val;
291906f1 1302
f0575e92
KP		 1303 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1304 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1305 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1306
1307 reg = PCH_ADPA;
1308 val = I915_READ(reg);
b70ad586 1309 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1310 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1311 pipe_name(pipe));
291906f1
JB		 1312
1313 reg = PCH_LVDS;
1314 val = I915_READ(reg);
b70ad586 1315 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1316 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1317 pipe_name(pipe));
291906f1 1318
e2debe91
PZ		 1319 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1320 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1321 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1322}
1323
426115cf 1324static void vlv_enable_pll(struct intel_crtc *crtc)
87442f73 1325{
426115cf
DV		 1326 struct drm_device *dev = crtc->base.dev;
1327 struct drm_i915_private *dev_priv = dev->dev_private;
1328 int reg = DPLL(crtc->pipe);
1329 u32 dpll = crtc->config.dpll_hw_state.dpll;
87442f73 1330
426115cf 1331 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1332
1333 /* No really, not for ILK+ */
1334 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1335
1336 /* PLL is protected by panel, make sure we can write it */
1337 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
426115cf 1338 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1339
426115cf
DV		 1340 I915_WRITE(reg, dpll);
1341 POSTING_READ(reg);
1342 udelay(150);
1343
1344 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1345 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1346
1347 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1348 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1349
1350 /* We do this three times for luck */
426115cf 1351 I915_WRITE(reg, dpll);
87442f73
DV		 1352 POSTING_READ(reg);
1353 udelay(150); /* wait for warmup */
426115cf 1354 I915_WRITE(reg, dpll);
87442f73
DV		 1355 POSTING_READ(reg);
1356 udelay(150); /* wait for warmup */
426115cf 1357 I915_WRITE(reg, dpll);
87442f73
DV		 1358 POSTING_READ(reg);
1359 udelay(150); /* wait for warmup */
1360}
1361
66e3d5c0 1362static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1363{
66e3d5c0
DV		 1364 struct drm_device *dev = crtc->base.dev;
1365 struct drm_i915_private *dev_priv = dev->dev_private;
1366 int reg = DPLL(crtc->pipe);
1367 u32 dpll = crtc->config.dpll_hw_state.dpll;
63d7bbe9 1368
66e3d5c0 1369 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1370
63d7bbe9 1371 /* No really, not for ILK+ */
87442f73 1372 BUG_ON(dev_priv->info->gen >= 5);
63d7bbe9
JB		 1373
1374 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1375 if (IS_MOBILE(dev) && !IS_I830(dev))
1376 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1377
66e3d5c0
DV		 1378 I915_WRITE(reg, dpll);
1379
1380 /* Wait for the clocks to stabilize. */
1381 POSTING_READ(reg);
1382 udelay(150);
1383
1384 if (INTEL_INFO(dev)->gen >= 4) {
1385 I915_WRITE(DPLL_MD(crtc->pipe),
1386 crtc->config.dpll_hw_state.dpll_md);
1387 } else {
1388 /* The pixel multiplier can only be updated once the
1389 * DPLL is enabled and the clocks are stable.
1390 *
1391 * So write it again.
1392 */
1393 I915_WRITE(reg, dpll);
1394 }
63d7bbe9
JB		 1395
1396 /* We do this three times for luck */
66e3d5c0 1397 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1398 POSTING_READ(reg);
1399 udelay(150); /* wait for warmup */
66e3d5c0 1400 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1401 POSTING_READ(reg);
1402 udelay(150); /* wait for warmup */
66e3d5c0 1403 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1404 POSTING_READ(reg);
1405 udelay(150); /* wait for warmup */
1406}
1407
1408/**
50b44a44 1409 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1410 * @dev_priv: i915 private structure
1411 * @pipe: pipe PLL to disable
1412 *
1413 * Disable the PLL for @pipe, making sure the pipe is off first.
1414 *
1415 * Note! This is for pre-ILK only.
1416 */
50b44a44 1417static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9 1418{
63d7bbe9
JB		 1419 /* Don't disable pipe A or pipe A PLLs if needed */
1420 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1421 return;
1422
1423 /* Make sure the pipe isn't still relying on us */
1424 assert_pipe_disabled(dev_priv, pipe);
1425
50b44a44
DV		 1426 I915_WRITE(DPLL(pipe), 0);
1427 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1428}
1429
89b667f8
JB		 1430void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1431{
1432 u32 port_mask;
1433
1434 if (!port)
1435 port_mask = DPLL_PORTB_READY_MASK;
1436 else
1437 port_mask = DPLL_PORTC_READY_MASK;
1438
1439 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1440 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1441 'B' + port, I915_READ(DPLL(0)));
1442}
1443
92f2584a 1444/**
e72f9fbf 1445 * ironlake_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1446 * @dev_priv: i915 private structure
1447 * @pipe: pipe PLL to enable
1448 *
1449 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1450 * drives the transcoder clock.
1451 */
e2b78267 1452static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1453{
e2b78267
DV		 1454 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1455 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1456
48da64a8 1457 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1458 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1459 if (WARN_ON(pll == NULL))
48da64a8
CW		 1460 return;
1461
1462 if (WARN_ON(pll->refcount == 0))
1463 return;
ee7b9f93 1464
46edb027
DV		 1465 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1466 pll->name, pll->active, pll->on,
e2b78267 1467 crtc->base.base.id);
92f2584a 1468
cdbd2316
DV		 1469 if (pll->active++) {
1470 WARN_ON(!pll->on);
e9d6944e 1471 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1472 return;
1473 }
f4a091c7 1474 WARN_ON(pll->on);
ee7b9f93 1475
46edb027 1476 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1477 pll->enable(dev_priv, pll);
ee7b9f93 1478 pll->on = true;
92f2584a
JB		 1479}
1480
e2b78267 1481static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1482{
e2b78267
DV		 1483 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1484 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1485
92f2584a
JB		 1486 /* PCH only available on ILK+ */
1487 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1488 if (WARN_ON(pll == NULL))
ee7b9f93 1489 return;
92f2584a 1490
48da64a8
CW		 1491 if (WARN_ON(pll->refcount == 0))
1492 return;
7a419866 1493
46edb027
DV		 1494 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1495 pll->name, pll->active, pll->on,
e2b78267 1496 crtc->base.base.id);
7a419866 1497
48da64a8 1498 if (WARN_ON(pll->active == 0)) {
e9d6944e 1499 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1500 return;
1501 }
1502
e9d6944e 1503 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1504 WARN_ON(!pll->on);
cdbd2316 1505 if (--pll->active)
7a419866 1506 return;
ee7b9f93 1507
46edb027 1508 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1509 pll->disable(dev_priv, pll);
ee7b9f93 1510 pll->on = false;
92f2584a
JB		 1511}
1512
b8a4f404
PZ		 1513static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1514 enum pipe pipe)
040484af 1515{
23670b32 1516 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1517 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1518 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1519 uint32_t reg, val, pipeconf_val;
040484af
JB		 1520
1521 /* PCH only available on ILK+ */
1522 BUG_ON(dev_priv->info->gen < 5);
1523
1524 /* Make sure PCH DPLL is enabled */
e72f9fbf 1525 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1526 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1527
1528 /* FDI must be feeding us bits for PCH ports */
1529 assert_fdi_tx_enabled(dev_priv, pipe);
1530 assert_fdi_rx_enabled(dev_priv, pipe);
1531
23670b32
DV		 1532 if (HAS_PCH_CPT(dev)) {
1533 /* Workaround: Set the timing override bit before enabling the
1534 * pch transcoder. */
1535 reg = TRANS_CHICKEN2(pipe);
1536 val = I915_READ(reg);
1537 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1538 I915_WRITE(reg, val);
59c859d6 1539 }
23670b32 1540
ab9412ba 1541 reg = PCH_TRANSCONF(pipe);
040484af 1542 val = I915_READ(reg);
5f7f726d 1543 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1544
1545 if (HAS_PCH_IBX(dev_priv->dev)) {
1546 /*
1547 * make the BPC in transcoder be consistent with
1548 * that in pipeconf reg.
1549 */
dfd07d72
DV		 1550 val &= ~PIPECONF_BPC_MASK;
1551 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1552 }
5f7f726d
PZ		 1553
1554 val &= ~TRANS_INTERLACE_MASK;
1555 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1556 if (HAS_PCH_IBX(dev_priv->dev) &&
1557 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1558 val |= TRANS_LEGACY_INTERLACED_ILK;
1559 else
1560 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1561 else
1562 val |= TRANS_PROGRESSIVE;
1563
040484af
JB		 1564 I915_WRITE(reg, val | TRANS_ENABLE);
1565 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1566 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1567}
1568
8fb033d7 1569static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1570 enum transcoder cpu_transcoder)
040484af 1571{
8fb033d7 1572 u32 val, pipeconf_val;
8fb033d7
PZ		 1573
1574 /* PCH only available on ILK+ */
1575 BUG_ON(dev_priv->info->gen < 5);
1576
8fb033d7 1577 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1578 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1579 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1580
223a6fdf
PZ		 1581 /* Workaround: set timing override bit. */
1582 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1583 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1584 I915_WRITE(_TRANSA_CHICKEN2, val);
1585
25f3ef11 1586 val = TRANS_ENABLE;
937bb610 1587 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1588
9a76b1c6
PZ		 1589 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1590 PIPECONF_INTERLACED_ILK)
a35f2679 1591 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1592 else
1593 val |= TRANS_PROGRESSIVE;
1594
ab9412ba
DV		 1595 I915_WRITE(LPT_TRANSCONF, val);
1596 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1597 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1598}
1599
b8a4f404
PZ		 1600static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1601 enum pipe pipe)
040484af 1602{
23670b32
DV		 1603 struct drm_device *dev = dev_priv->dev;
1604 uint32_t reg, val;
040484af
JB		 1605
1606 /* FDI relies on the transcoder */
1607 assert_fdi_tx_disabled(dev_priv, pipe);
1608 assert_fdi_rx_disabled(dev_priv, pipe);
1609
291906f1
JB		 1610 /* Ports must be off as well */
1611 assert_pch_ports_disabled(dev_priv, pipe);
1612
ab9412ba 1613 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1614 val = I915_READ(reg);
1615 val &= ~TRANS_ENABLE;
1616 I915_WRITE(reg, val);
1617 /* wait for PCH transcoder off, transcoder state */
1618 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1619 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1620
1621 if (!HAS_PCH_IBX(dev)) {
1622 /* Workaround: Clear the timing override chicken bit again. */
1623 reg = TRANS_CHICKEN2(pipe);
1624 val = I915_READ(reg);
1625 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1626 I915_WRITE(reg, val);
1627 }
040484af
JB		 1628}
1629
ab4d966c 1630static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1631{
8fb033d7
PZ		 1632 u32 val;
1633
ab9412ba 1634 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1635 val &= ~TRANS_ENABLE;
ab9412ba 1636 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1637 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1638 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1639 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1640
1641 /* Workaround: clear timing override bit. */
1642 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1643 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1644 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1645}
1646
b24e7179 1647/**
309cfea8 1648 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1649 * @dev_priv: i915 private structure
1650 * @pipe: pipe to enable
040484af 1651 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1652 *
1653 * Enable @pipe, making sure that various hardware specific requirements
1654 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1655 *
1656 * @pipe should be %PIPE_A or %PIPE_B.
1657 *
1658 * Will wait until the pipe is actually running (i.e. first vblank) before
1659 * returning.
1660 */
040484af
JB		 1661static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1662 bool pch_port)
b24e7179 1663{
702e7a56
PZ		 1664 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1665 pipe);
1a240d4d 1666 enum pipe pch_transcoder;
b24e7179
JB		 1667 int reg;
1668 u32 val;
1669
58c6eaa2
DV		 1670 assert_planes_disabled(dev_priv, pipe);
1671 assert_sprites_disabled(dev_priv, pipe);
1672
681e5811 1673 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1674 pch_transcoder = TRANSCODER_A;
1675 else
1676 pch_transcoder = pipe;
1677
b24e7179
JB		 1678 /*
1679 * A pipe without a PLL won't actually be able to drive bits from
1680 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1681 * need the check.
1682 */
1683 if (!HAS_PCH_SPLIT(dev_priv->dev))
1684 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1685 else {
1686 if (pch_port) {
1687 /* if driving the PCH, we need FDI enabled */
cc391bbb 1688 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1689 assert_fdi_tx_pll_enabled(dev_priv,
1690 (enum pipe) cpu_transcoder);
040484af
JB		 1691 }
1692 /* FIXME: assert CPU port conditions for SNB+ */
1693 }
b24e7179 1694
702e7a56 1695 reg = PIPECONF(cpu_transcoder);
b24e7179 1696 val = I915_READ(reg);
00d70b15
CW		 1697 if (val & PIPECONF_ENABLE)
1698 return;
1699
1700 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1701 intel_wait_for_vblank(dev_priv->dev, pipe);
1702}
1703
1704/**
309cfea8 1705 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1706 * @dev_priv: i915 private structure
1707 * @pipe: pipe to disable
1708 *
1709 * Disable @pipe, making sure that various hardware specific requirements
1710 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1711 *
1712 * @pipe should be %PIPE_A or %PIPE_B.
1713 *
1714 * Will wait until the pipe has shut down before returning.
1715 */
1716static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1717 enum pipe pipe)
1718{
702e7a56
PZ		 1719 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1720 pipe);
b24e7179
JB		 1721 int reg;
1722 u32 val;
1723
1724 /*
1725 * Make sure planes won't keep trying to pump pixels to us,
1726 * or we might hang the display.
1727 */
1728 assert_planes_disabled(dev_priv, pipe);
19332d7a 1729 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1730
1731 /* Don't disable pipe A or pipe A PLLs if needed */
1732 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1733 return;
1734
702e7a56 1735 reg = PIPECONF(cpu_transcoder);
b24e7179 1736 val = I915_READ(reg);
00d70b15
CW		 1737 if ((val & PIPECONF_ENABLE) == 0)
1738 return;
1739
1740 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1741 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1742}
1743
d74362c9
KP		 1744/*
1745 * Plane regs are double buffered, going from enabled->disabled needs a
1746 * trigger in order to latch. The display address reg provides this.
1747 */
6f1d69b0 1748void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1749 enum plane plane)
1750{
14f86147
DL		 1751 if (dev_priv->info->gen >= 4)
1752 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1753 else
1754 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1755}
1756
b24e7179
JB		 1757/**
1758 * intel_enable_plane - enable a display plane on a given pipe
1759 * @dev_priv: i915 private structure
1760 * @plane: plane to enable
1761 * @pipe: pipe being fed
1762 *
1763 * Enable @plane on @pipe, making sure that @pipe is running first.
1764 */
1765static void intel_enable_plane(struct drm_i915_private *dev_priv,
1766 enum plane plane, enum pipe pipe)
1767{
1768 int reg;
1769 u32 val;
1770
1771 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1772 assert_pipe_enabled(dev_priv, pipe);
1773
1774 reg = DSPCNTR(plane);
1775 val = I915_READ(reg);
00d70b15
CW		 1776 if (val & DISPLAY_PLANE_ENABLE)
1777 return;
1778
1779 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1780 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1781 intel_wait_for_vblank(dev_priv->dev, pipe);
1782}
1783
b24e7179
JB		 1784/**
1785 * intel_disable_plane - disable a display plane
1786 * @dev_priv: i915 private structure
1787 * @plane: plane to disable
1788 * @pipe: pipe consuming the data
1789 *
1790 * Disable @plane; should be an independent operation.
1791 */
1792static void intel_disable_plane(struct drm_i915_private *dev_priv,
1793 enum plane plane, enum pipe pipe)
1794{
1795 int reg;
1796 u32 val;
1797
1798 reg = DSPCNTR(plane);
1799 val = I915_READ(reg);
00d70b15
CW		 1800 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1801 return;
1802
1803 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1804 intel_flush_display_plane(dev_priv, plane);
1805 intel_wait_for_vblank(dev_priv->dev, pipe);
1806}
1807
693db184
CW		 1808static bool need_vtd_wa(struct drm_device *dev)
1809{
1810#ifdef CONFIG_INTEL_IOMMU
1811 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1812 return true;
1813#endif
1814 return false;
1815}
1816
127bd2ac 1817int
48b956c5 1818intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1819 struct drm_i915_gem_object *obj,
919926ae 1820 struct intel_ring_buffer *pipelined)
6b95a207 1821{
ce453d81 1822 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1823 u32 alignment;
1824 int ret;
1825
05394f39 1826 switch (obj->tiling_mode) {
6b95a207 1827 case I915_TILING_NONE:
534843da
CW		 1828 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1829 alignment = 128 * 1024;
a6c45cf0 1830 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1831 alignment = 4 * 1024;
1832 else
1833 alignment = 64 * 1024;
6b95a207
KH		 1834 break;
1835 case I915_TILING_X:
1836 /* pin() will align the object as required by fence */
1837 alignment = 0;
1838 break;
1839 case I915_TILING_Y:
8bb6e959
DV		 1840 /* Despite that we check this in framebuffer_init userspace can
1841 * screw us over and change the tiling after the fact. Only
1842 * pinned buffers can't change their tiling. */
1843 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1844 return -EINVAL;
1845 default:
1846 BUG();
1847 }
1848
693db184
CW		 1849 /* Note that the w/a also requires 64 PTE of padding following the
1850 * bo. We currently fill all unused PTE with the shadow page and so
1851 * we should always have valid PTE following the scanout preventing
1852 * the VT-d warning.
1853 */
1854 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1855 alignment = 256 * 1024;
1856
ce453d81 1857 dev_priv->mm.interruptible = false;
2da3b9b9 1858 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1859 if (ret)
ce453d81 1860 goto err_interruptible;
6b95a207
KH		 1861
1862 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1863 * fence, whereas 965+ only requires a fence if using
1864 * framebuffer compression. For simplicity, we always install
1865 * a fence as the cost is not that onerous.
1866 */
06d98131 1867 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1868 if (ret)
1869 goto err_unpin;
1690e1eb 1870
9a5a53b3 1871 i915_gem_object_pin_fence(obj);
6b95a207 1872
ce453d81 1873 dev_priv->mm.interruptible = true;
6b95a207 1874 return 0;
48b956c5
CW		 1875
1876err_unpin:
1877 i915_gem_object_unpin(obj);
ce453d81
CW		 1878err_interruptible:
1879 dev_priv->mm.interruptible = true;
48b956c5 1880 return ret;
6b95a207
KH		 1881}
1882
1690e1eb
CW		 1883void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1884{
1885 i915_gem_object_unpin_fence(obj);
1886 i915_gem_object_unpin(obj);
1887}
1888
c2c75131
DV		 1889/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1890 * is assumed to be a power-of-two. */
bc752862
CW		 1891unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1892 unsigned int tiling_mode,
1893 unsigned int cpp,
1894 unsigned int pitch)
c2c75131 1895{
bc752862
CW		 1896 if (tiling_mode != I915_TILING_NONE) {
1897 unsigned int tile_rows, tiles;
c2c75131 1898
bc752862
CW		 1899 tile_rows = *y / 8;
1900 *y %= 8;
c2c75131 1901
bc752862
CW		 1902 tiles = *x / (512/cpp);
1903 *x %= 512/cpp;
1904
1905 return tile_rows * pitch * 8 + tiles * 4096;
1906 } else {
1907 unsigned int offset;
1908
1909 offset = *y * pitch + *x * cpp;
1910 *y = 0;
1911 *x = (offset & 4095) / cpp;
1912 return offset & -4096;
1913 }
c2c75131
DV		 1914}
1915
17638cd6
JB		 1916static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1917 int x, int y)
81255565
JB		 1918{
1919 struct drm_device *dev = crtc->dev;
1920 struct drm_i915_private *dev_priv = dev->dev_private;
1921 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1922 struct intel_framebuffer *intel_fb;
05394f39 1923 struct drm_i915_gem_object *obj;
81255565 1924 int plane = intel_crtc->plane;
e506a0c6 1925 unsigned long linear_offset;
81255565 1926 u32 dspcntr;
5eddb70b 1927 u32 reg;
81255565
JB		 1928
1929 switch (plane) {
1930 case 0:
1931 case 1:
1932 break;
1933 default:
84f44ce7 1934 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 1935 return -EINVAL;
1936 }
1937
1938 intel_fb = to_intel_framebuffer(fb);
1939 obj = intel_fb->obj;
81255565 1940
5eddb70b
CW		 1941 reg = DSPCNTR(plane);
1942 dspcntr = I915_READ(reg);
81255565
JB		 1943 /* Mask out pixel format bits in case we change it */
1944 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 1945 switch (fb->pixel_format) {
1946 case DRM_FORMAT_C8:
81255565
JB		 1947 dspcntr |= DISPPLANE_8BPP;
1948 break;
57779d06
VS		 1949 case DRM_FORMAT_XRGB1555:
1950 case DRM_FORMAT_ARGB1555:
1951 dspcntr |= DISPPLANE_BGRX555;
81255565 1952 break;
57779d06
VS		 1953 case DRM_FORMAT_RGB565:
1954 dspcntr |= DISPPLANE_BGRX565;
1955 break;
1956 case DRM_FORMAT_XRGB8888:
1957 case DRM_FORMAT_ARGB8888:
1958 dspcntr |= DISPPLANE_BGRX888;
1959 break;
1960 case DRM_FORMAT_XBGR8888:
1961 case DRM_FORMAT_ABGR8888:
1962 dspcntr |= DISPPLANE_RGBX888;
1963 break;
1964 case DRM_FORMAT_XRGB2101010:
1965 case DRM_FORMAT_ARGB2101010:
1966 dspcntr |= DISPPLANE_BGRX101010;
1967 break;
1968 case DRM_FORMAT_XBGR2101010:
1969 case DRM_FORMAT_ABGR2101010:
1970 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 1971 break;
1972 default:
baba133a 1973 BUG();
81255565 1974 }
57779d06 1975
a6c45cf0 1976 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1977 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1978 dspcntr |= DISPPLANE_TILED;
1979 else
1980 dspcntr &= ~DISPPLANE_TILED;
1981 }
1982
de1aa629
VS		 1983 if (IS_G4X(dev))
1984 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1985
5eddb70b 1986 I915_WRITE(reg, dspcntr);
81255565 1987
e506a0c6 1988 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 1989
c2c75131
DV		 1990 if (INTEL_INFO(dev)->gen >= 4) {
1991 intel_crtc->dspaddr_offset =
bc752862
CW		 1992 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1993 fb->bits_per_pixel / 8,
1994 fb->pitches[0]);
c2c75131
DV		 1995 linear_offset -= intel_crtc->dspaddr_offset;
1996 } else {
e506a0c6 1997 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 1998 }
e506a0c6 1999
f343c5f6
BW		 2000 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2001 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2002 fb->pitches[0]);
01f2c773 2003 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2004 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131 2005 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2006 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2007 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2008 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2009 } else
f343c5f6 2010 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2011 POSTING_READ(reg);
81255565 2012
17638cd6
JB		 2013 return 0;
2014}
2015
2016static int ironlake_update_plane(struct drm_crtc *crtc,
2017 struct drm_framebuffer *fb, int x, int y)
2018{
2019 struct drm_device *dev = crtc->dev;
2020 struct drm_i915_private *dev_priv = dev->dev_private;
2021 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2022 struct intel_framebuffer *intel_fb;
2023 struct drm_i915_gem_object *obj;
2024 int plane = intel_crtc->plane;
e506a0c6 2025 unsigned long linear_offset;
17638cd6
JB		 2026 u32 dspcntr;
2027 u32 reg;
2028
2029 switch (plane) {
2030 case 0:
2031 case 1:
27f8227b 2032 case 2:
17638cd6
JB		 2033 break;
2034 default:
84f44ce7 2035 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2036 return -EINVAL;
2037 }
2038
2039 intel_fb = to_intel_framebuffer(fb);
2040 obj = intel_fb->obj;
2041
2042 reg = DSPCNTR(plane);
2043 dspcntr = I915_READ(reg);
2044 /* Mask out pixel format bits in case we change it */
2045 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2046 switch (fb->pixel_format) {
2047 case DRM_FORMAT_C8:
17638cd6
JB		 2048 dspcntr |= DISPPLANE_8BPP;
2049 break;
57779d06
VS		 2050 case DRM_FORMAT_RGB565:
2051 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2052 break;
57779d06
VS		 2053 case DRM_FORMAT_XRGB8888:
2054 case DRM_FORMAT_ARGB8888:
2055 dspcntr |= DISPPLANE_BGRX888;
2056 break;
2057 case DRM_FORMAT_XBGR8888:
2058 case DRM_FORMAT_ABGR8888:
2059 dspcntr |= DISPPLANE_RGBX888;
2060 break;
2061 case DRM_FORMAT_XRGB2101010:
2062 case DRM_FORMAT_ARGB2101010:
2063 dspcntr |= DISPPLANE_BGRX101010;
2064 break;
2065 case DRM_FORMAT_XBGR2101010:
2066 case DRM_FORMAT_ABGR2101010:
2067 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2068 break;
2069 default:
baba133a 2070 BUG();
17638cd6
JB		 2071 }
2072
2073 if (obj->tiling_mode != I915_TILING_NONE)
2074 dspcntr |= DISPPLANE_TILED;
2075 else
2076 dspcntr &= ~DISPPLANE_TILED;
2077
2078 /* must disable */
2079 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2080
2081 I915_WRITE(reg, dspcntr);
2082
e506a0c6 2083 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2084 intel_crtc->dspaddr_offset =
bc752862
CW		 2085 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2086 fb->bits_per_pixel / 8,
2087 fb->pitches[0]);
c2c75131 2088 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2089
f343c5f6
BW		 2090 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2091 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2092 fb->pitches[0]);
01f2c773 2093 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131 2094 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2095 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2096 if (IS_HASWELL(dev)) {
2097 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2098 } else {
2099 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2100 I915_WRITE(DSPLINOFF(plane), linear_offset);
2101 }
17638cd6
JB		 2102 POSTING_READ(reg);
2103
2104 return 0;
2105}
2106
2107/* Assume fb object is pinned & idle & fenced and just update base pointers */
2108static int
2109intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2110 int x, int y, enum mode_set_atomic state)
2111{
2112 struct drm_device *dev = crtc->dev;
2113 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2114
6b8e6ed0
CW		 2115 if (dev_priv->display.disable_fbc)
2116 dev_priv->display.disable_fbc(dev);
3dec0095 2117 intel_increase_pllclock(crtc);
81255565 2118
6b8e6ed0 2119 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2120}
2121
96a02917
VS		 2122void intel_display_handle_reset(struct drm_device *dev)
2123{
2124 struct drm_i915_private *dev_priv = dev->dev_private;
2125 struct drm_crtc *crtc;
2126
2127 /*
2128 * Flips in the rings have been nuked by the reset,
2129 * so complete all pending flips so that user space
2130 * will get its events and not get stuck.
2131 *
2132 * Also update the base address of all primary
2133 * planes to the the last fb to make sure we're
2134 * showing the correct fb after a reset.
2135 *
2136 * Need to make two loops over the crtcs so that we
2137 * don't try to grab a crtc mutex before the
2138 * pending_flip_queue really got woken up.
2139 */
2140
2141 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2142 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2143 enum plane plane = intel_crtc->plane;
2144
2145 intel_prepare_page_flip(dev, plane);
2146 intel_finish_page_flip_plane(dev, plane);
2147 }
2148
2149 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2150 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2151
2152 mutex_lock(&crtc->mutex);
2153 if (intel_crtc->active)
2154 dev_priv->display.update_plane(crtc, crtc->fb,
2155 crtc->x, crtc->y);
2156 mutex_unlock(&crtc->mutex);
2157 }
2158}
2159
14667a4b
CW		 2160static int
2161intel_finish_fb(struct drm_framebuffer *old_fb)
2162{
2163 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2164 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2165 bool was_interruptible = dev_priv->mm.interruptible;
2166 int ret;
2167
14667a4b
CW		 2168 /* Big Hammer, we also need to ensure that any pending
2169 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2170 * current scanout is retired before unpinning the old
2171 * framebuffer.
2172 *
2173 * This should only fail upon a hung GPU, in which case we
2174 * can safely continue.
2175 */
2176 dev_priv->mm.interruptible = false;
2177 ret = i915_gem_object_finish_gpu(obj);
2178 dev_priv->mm.interruptible = was_interruptible;
2179
2180 return ret;
2181}
2182
198598d0
VS		 2183static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2184{
2185 struct drm_device *dev = crtc->dev;
2186 struct drm_i915_master_private *master_priv;
2187 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2188
2189 if (!dev->primary->master)
2190 return;
2191
2192 master_priv = dev->primary->master->driver_priv;
2193 if (!master_priv->sarea_priv)
2194 return;
2195
2196 switch (intel_crtc->pipe) {
2197 case 0:
2198 master_priv->sarea_priv->pipeA_x = x;
2199 master_priv->sarea_priv->pipeA_y = y;
2200 break;
2201 case 1:
2202 master_priv->sarea_priv->pipeB_x = x;
2203 master_priv->sarea_priv->pipeB_y = y;
2204 break;
2205 default:
2206 break;
2207 }
2208}
2209
5c3b82e2 2210static int
3c4fdcfb 2211intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2212 struct drm_framebuffer *fb)
79e53945
JB		 2213{
2214 struct drm_device *dev = crtc->dev;
6b8e6ed0 2215 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2216 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2217 struct drm_framebuffer *old_fb;
5c3b82e2 2218 int ret;
79e53945
JB		 2219
2220 /* no fb bound */
94352cf9 2221 if (!fb) {
a5071c2f 2222 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2223 return 0;
2224 }
2225
7eb552ae 2226 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2227 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2228 plane_name(intel_crtc->plane),
2229 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2230 return -EINVAL;
79e53945
JB		 2231 }
2232
5c3b82e2 2233 mutex_lock(&dev->struct_mutex);
265db958 2234 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2235 to_intel_framebuffer(fb)->obj,
919926ae 2236 NULL);
5c3b82e2
CW		 2237 if (ret != 0) {
2238 mutex_unlock(&dev->struct_mutex);
a5071c2f 2239 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2240 return ret;
2241 }
79e53945 2242
4d6a3e63
JB		 2243 /* Update pipe size and adjust fitter if needed */
2244 if (i915_fastboot) {
2245 I915_WRITE(PIPESRC(intel_crtc->pipe),
2246 ((crtc->mode.hdisplay - 1) << 16) |
2247 (crtc->mode.vdisplay - 1));
2248 if (!intel_crtc->config.pch_pfit.size &&
2249 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2250 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2251 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2252 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2253 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2254 }
2255 }
2256
94352cf9 2257 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2258 if (ret) {
94352cf9 2259 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2260 mutex_unlock(&dev->struct_mutex);
a5071c2f 2261 DRM_ERROR("failed to update base address\n");
4e6cfefc 2262 return ret;
79e53945 2263 }
3c4fdcfb 2264
94352cf9
DV		 2265 old_fb = crtc->fb;
2266 crtc->fb = fb;
6c4c86f5
DV		 2267 crtc->x = x;
2268 crtc->y = y;
94352cf9 2269
b7f1de28 2270 if (old_fb) {
d7697eea
DV		 2271 if (intel_crtc->active && old_fb != fb)
2272 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2273 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2274 }
652c393a 2275
6b8e6ed0 2276 intel_update_fbc(dev);
4906557e 2277 intel_edp_psr_update(dev);
5c3b82e2 2278 mutex_unlock(&dev->struct_mutex);
79e53945 2279
198598d0 2280 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2281
2282 return 0;
79e53945
JB		 2283}
2284
5e84e1a4
ZW		 2285static void intel_fdi_normal_train(struct drm_crtc *crtc)
2286{
2287 struct drm_device *dev = crtc->dev;
2288 struct drm_i915_private *dev_priv = dev->dev_private;
2289 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2290 int pipe = intel_crtc->pipe;
2291 u32 reg, temp;
2292
2293 /* enable normal train */
2294 reg = FDI_TX_CTL(pipe);
2295 temp = I915_READ(reg);
61e499bf 2296 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2297 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2298 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2299 } else {
2300 temp &= ~FDI_LINK_TRAIN_NONE;
2301 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2302 }
5e84e1a4
ZW		 2303 I915_WRITE(reg, temp);
2304
2305 reg = FDI_RX_CTL(pipe);
2306 temp = I915_READ(reg);
2307 if (HAS_PCH_CPT(dev)) {
2308 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2309 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2310 } else {
2311 temp &= ~FDI_LINK_TRAIN_NONE;
2312 temp |= FDI_LINK_TRAIN_NONE;
2313 }
2314 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2315
2316 /* wait one idle pattern time */
2317 POSTING_READ(reg);
2318 udelay(1000);
357555c0
JB		 2319
2320 /* IVB wants error correction enabled */
2321 if (IS_IVYBRIDGE(dev))
2322 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2323 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2324}
2325
1e833f40
DV		 2326static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2327{
2328 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2329}
2330
01a415fd
DV		 2331static void ivb_modeset_global_resources(struct drm_device *dev)
2332{
2333 struct drm_i915_private *dev_priv = dev->dev_private;
2334 struct intel_crtc *pipe_B_crtc =
2335 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2336 struct intel_crtc *pipe_C_crtc =
2337 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2338 uint32_t temp;
2339
1e833f40
DV		 2340 /*
2341 * When everything is off disable fdi C so that we could enable fdi B
2342 * with all lanes. Note that we don't care about enabled pipes without
2343 * an enabled pch encoder.
2344 */
2345 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2346 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2347 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2348 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2349
2350 temp = I915_READ(SOUTH_CHICKEN1);
2351 temp &= ~FDI_BC_BIFURCATION_SELECT;
2352 DRM_DEBUG_KMS("disabling fdi C rx\n");
2353 I915_WRITE(SOUTH_CHICKEN1, temp);
2354 }
2355}
2356
8db9d77b
ZW		 2357/* The FDI link training functions for ILK/Ibexpeak. */
2358static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2359{
2360 struct drm_device *dev = crtc->dev;
2361 struct drm_i915_private *dev_priv = dev->dev_private;
2362 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2363 int pipe = intel_crtc->pipe;
0fc932b8 2364 int plane = intel_crtc->plane;
5eddb70b 2365 u32 reg, temp, tries;
8db9d77b 2366
0fc932b8
JB		 2367 /* FDI needs bits from pipe & plane first */
2368 assert_pipe_enabled(dev_priv, pipe);
2369 assert_plane_enabled(dev_priv, plane);
2370
e1a44743
AJ		 2371 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2372 for train result */
5eddb70b
CW		 2373 reg = FDI_RX_IMR(pipe);
2374 temp = I915_READ(reg);
e1a44743
AJ		 2375 temp &= ~FDI_RX_SYMBOL_LOCK;
2376 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2377 I915_WRITE(reg, temp);
2378 I915_READ(reg);
e1a44743
AJ		 2379 udelay(150);
2380
8db9d77b 2381 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2382 reg = FDI_TX_CTL(pipe);
2383 temp = I915_READ(reg);
627eb5a3
DV		 2384 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2385 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2386 temp &= ~FDI_LINK_TRAIN_NONE;
2387 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2388 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2389
5eddb70b
CW		 2390 reg = FDI_RX_CTL(pipe);
2391 temp = I915_READ(reg);
8db9d77b
ZW		 2392 temp &= ~FDI_LINK_TRAIN_NONE;
2393 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2394 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2395
2396 POSTING_READ(reg);
8db9d77b
ZW		 2397 udelay(150);
2398
5b2adf89 2399 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2400 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2401 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2402 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2403
5eddb70b 2404 reg = FDI_RX_IIR(pipe);
e1a44743 2405 for (tries = 0; tries < 5; tries++) {
5eddb70b 2406 temp = I915_READ(reg);
8db9d77b
ZW		 2407 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2408
2409 if ((temp & FDI_RX_BIT_LOCK)) {
2410 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2411 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2412 break;
2413 }
8db9d77b 2414 }
e1a44743 2415 if (tries == 5)
5eddb70b 2416 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2417
2418 /* Train 2 */
5eddb70b
CW		 2419 reg = FDI_TX_CTL(pipe);
2420 temp = I915_READ(reg);
8db9d77b
ZW		 2421 temp &= ~FDI_LINK_TRAIN_NONE;
2422 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2423 I915_WRITE(reg, temp);
8db9d77b 2424
5eddb70b
CW		 2425 reg = FDI_RX_CTL(pipe);
2426 temp = I915_READ(reg);
8db9d77b
ZW		 2427 temp &= ~FDI_LINK_TRAIN_NONE;
2428 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2429 I915_WRITE(reg, temp);
8db9d77b 2430
5eddb70b
CW		 2431 POSTING_READ(reg);
2432 udelay(150);
8db9d77b 2433
5eddb70b 2434 reg = FDI_RX_IIR(pipe);
e1a44743 2435 for (tries = 0; tries < 5; tries++) {
5eddb70b 2436 temp = I915_READ(reg);
8db9d77b
ZW		 2437 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2438
2439 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2440 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2441 DRM_DEBUG_KMS("FDI train 2 done.\n");
2442 break;
2443 }
8db9d77b 2444 }
e1a44743 2445 if (tries == 5)
5eddb70b 2446 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2447
2448 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2449
8db9d77b
ZW		 2450}
2451
0206e353 2452static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2453 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2454 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2455 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2456 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2457};
2458
2459/* The FDI link training functions for SNB/Cougarpoint. */
2460static void gen6_fdi_link_train(struct drm_crtc *crtc)
2461{
2462 struct drm_device *dev = crtc->dev;
2463 struct drm_i915_private *dev_priv = dev->dev_private;
2464 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2465 int pipe = intel_crtc->pipe;
fa37d39e 2466 u32 reg, temp, i, retry;
8db9d77b 2467
e1a44743
AJ		 2468 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2469 for train result */
5eddb70b
CW		 2470 reg = FDI_RX_IMR(pipe);
2471 temp = I915_READ(reg);
e1a44743
AJ		 2472 temp &= ~FDI_RX_SYMBOL_LOCK;
2473 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2474 I915_WRITE(reg, temp);
2475
2476 POSTING_READ(reg);
e1a44743
AJ		 2477 udelay(150);
2478
8db9d77b 2479 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2480 reg = FDI_TX_CTL(pipe);
2481 temp = I915_READ(reg);
627eb5a3
DV		 2482 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2483 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2484 temp &= ~FDI_LINK_TRAIN_NONE;
2485 temp |= FDI_LINK_TRAIN_PATTERN_1;
2486 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2487 /* SNB-B */
2488 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2489 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2490
d74cf324
DV		 2491 I915_WRITE(FDI_RX_MISC(pipe),
2492 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2493
5eddb70b
CW		 2494 reg = FDI_RX_CTL(pipe);
2495 temp = I915_READ(reg);
8db9d77b
ZW		 2496 if (HAS_PCH_CPT(dev)) {
2497 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2498 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2499 } else {
2500 temp &= ~FDI_LINK_TRAIN_NONE;
2501 temp |= FDI_LINK_TRAIN_PATTERN_1;
2502 }
5eddb70b
CW		 2503 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2504
2505 POSTING_READ(reg);
8db9d77b
ZW		 2506 udelay(150);
2507
0206e353 2508 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2509 reg = FDI_TX_CTL(pipe);
2510 temp = I915_READ(reg);
8db9d77b
ZW		 2511 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2512 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2513 I915_WRITE(reg, temp);
2514
2515 POSTING_READ(reg);
8db9d77b
ZW		 2516 udelay(500);
2517
fa37d39e
SP		 2518 for (retry = 0; retry < 5; retry++) {
2519 reg = FDI_RX_IIR(pipe);
2520 temp = I915_READ(reg);
2521 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2522 if (temp & FDI_RX_BIT_LOCK) {
2523 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2524 DRM_DEBUG_KMS("FDI train 1 done.\n");
2525 break;
2526 }
2527 udelay(50);
8db9d77b 2528 }
fa37d39e
SP		 2529 if (retry < 5)
2530 break;
8db9d77b
ZW		 2531 }
2532 if (i == 4)
5eddb70b 2533 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2534
2535 /* Train 2 */
5eddb70b
CW		 2536 reg = FDI_TX_CTL(pipe);
2537 temp = I915_READ(reg);
8db9d77b
ZW		 2538 temp &= ~FDI_LINK_TRAIN_NONE;
2539 temp |= FDI_LINK_TRAIN_PATTERN_2;
2540 if (IS_GEN6(dev)) {
2541 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2542 /* SNB-B */
2543 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2544 }
5eddb70b 2545 I915_WRITE(reg, temp);
8db9d77b 2546
5eddb70b
CW		 2547 reg = FDI_RX_CTL(pipe);
2548 temp = I915_READ(reg);
8db9d77b
ZW		 2549 if (HAS_PCH_CPT(dev)) {
2550 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2551 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2552 } else {
2553 temp &= ~FDI_LINK_TRAIN_NONE;
2554 temp |= FDI_LINK_TRAIN_PATTERN_2;
2555 }
5eddb70b
CW		 2556 I915_WRITE(reg, temp);
2557
2558 POSTING_READ(reg);
8db9d77b
ZW		 2559 udelay(150);
2560
0206e353 2561 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2562 reg = FDI_TX_CTL(pipe);
2563 temp = I915_READ(reg);
8db9d77b
ZW		 2564 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2565 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2566 I915_WRITE(reg, temp);
2567
2568 POSTING_READ(reg);
8db9d77b
ZW		 2569 udelay(500);
2570
fa37d39e
SP		 2571 for (retry = 0; retry < 5; retry++) {
2572 reg = FDI_RX_IIR(pipe);
2573 temp = I915_READ(reg);
2574 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2575 if (temp & FDI_RX_SYMBOL_LOCK) {
2576 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2577 DRM_DEBUG_KMS("FDI train 2 done.\n");
2578 break;
2579 }
2580 udelay(50);
8db9d77b 2581 }
fa37d39e
SP		 2582 if (retry < 5)
2583 break;
8db9d77b
ZW		 2584 }
2585 if (i == 4)
5eddb70b 2586 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2587
2588 DRM_DEBUG_KMS("FDI train done.\n");
2589}
2590
357555c0
JB		 2591/* Manual link training for Ivy Bridge A0 parts */
2592static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2593{
2594 struct drm_device *dev = crtc->dev;
2595 struct drm_i915_private *dev_priv = dev->dev_private;
2596 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2597 int pipe = intel_crtc->pipe;
2598 u32 reg, temp, i;
2599
2600 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2601 for train result */
2602 reg = FDI_RX_IMR(pipe);
2603 temp = I915_READ(reg);
2604 temp &= ~FDI_RX_SYMBOL_LOCK;
2605 temp &= ~FDI_RX_BIT_LOCK;
2606 I915_WRITE(reg, temp);
2607
2608 POSTING_READ(reg);
2609 udelay(150);
2610
01a415fd
DV		 2611 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2612 I915_READ(FDI_RX_IIR(pipe)));
2613
357555c0
JB		 2614 /* enable CPU FDI TX and PCH FDI RX */
2615 reg = FDI_TX_CTL(pipe);
2616 temp = I915_READ(reg);
627eb5a3
DV		 2617 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2618 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
357555c0
JB		 2619 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2620 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2621 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2622 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2623 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2624 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2625
d74cf324
DV		 2626 I915_WRITE(FDI_RX_MISC(pipe),
2627 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2628
357555c0
JB		 2629 reg = FDI_RX_CTL(pipe);
2630 temp = I915_READ(reg);
2631 temp &= ~FDI_LINK_TRAIN_AUTO;
2632 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2633 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2634 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2635 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2636
2637 POSTING_READ(reg);
2638 udelay(150);
2639
0206e353 2640 for (i = 0; i < 4; i++) {
357555c0
JB		 2641 reg = FDI_TX_CTL(pipe);
2642 temp = I915_READ(reg);
2643 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2644 temp |= snb_b_fdi_train_param[i];
2645 I915_WRITE(reg, temp);
2646
2647 POSTING_READ(reg);
2648 udelay(500);
2649
2650 reg = FDI_RX_IIR(pipe);
2651 temp = I915_READ(reg);
2652 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2653
2654 if (temp & FDI_RX_BIT_LOCK ||
2655 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2656 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2657 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2658 break;
2659 }
2660 }
2661 if (i == 4)
2662 DRM_ERROR("FDI train 1 fail!\n");
2663
2664 /* Train 2 */
2665 reg = FDI_TX_CTL(pipe);
2666 temp = I915_READ(reg);
2667 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2668 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2669 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2670 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2671 I915_WRITE(reg, temp);
2672
2673 reg = FDI_RX_CTL(pipe);
2674 temp = I915_READ(reg);
2675 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2676 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2677 I915_WRITE(reg, temp);
2678
2679 POSTING_READ(reg);
2680 udelay(150);
2681
0206e353 2682 for (i = 0; i < 4; i++) {
357555c0
JB		 2683 reg = FDI_TX_CTL(pipe);
2684 temp = I915_READ(reg);
2685 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2686 temp |= snb_b_fdi_train_param[i];
2687 I915_WRITE(reg, temp);
2688
2689 POSTING_READ(reg);
2690 udelay(500);
2691
2692 reg = FDI_RX_IIR(pipe);
2693 temp = I915_READ(reg);
2694 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2695
2696 if (temp & FDI_RX_SYMBOL_LOCK) {
2697 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2698 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2699 break;
2700 }
2701 }
2702 if (i == 4)
2703 DRM_ERROR("FDI train 2 fail!\n");
2704
2705 DRM_DEBUG_KMS("FDI train done.\n");
2706}
2707
88cefb6c 2708static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2709{
88cefb6c 2710 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2711 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2712 int pipe = intel_crtc->pipe;
5eddb70b 2713 u32 reg, temp;
79e53945 2714
c64e311e 2715
c98e9dcf 2716 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2717 reg = FDI_RX_CTL(pipe);
2718 temp = I915_READ(reg);
627eb5a3
DV		 2719 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2720 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2721 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2722 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2723
2724 POSTING_READ(reg);
c98e9dcf
JB		 2725 udelay(200);
2726
2727 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2728 temp = I915_READ(reg);
2729 I915_WRITE(reg, temp | FDI_PCDCLK);
2730
2731 POSTING_READ(reg);
c98e9dcf
JB		 2732 udelay(200);
2733
20749730
PZ		 2734 /* Enable CPU FDI TX PLL, always on for Ironlake */
2735 reg = FDI_TX_CTL(pipe);
2736 temp = I915_READ(reg);
2737 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2738 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2739
20749730
PZ		 2740 POSTING_READ(reg);
2741 udelay(100);
6be4a607 2742 }
0e23b99d
JB		 2743}
2744
88cefb6c
DV		 2745static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2746{
2747 struct drm_device *dev = intel_crtc->base.dev;
2748 struct drm_i915_private *dev_priv = dev->dev_private;
2749 int pipe = intel_crtc->pipe;
2750 u32 reg, temp;
2751
2752 /* Switch from PCDclk to Rawclk */
2753 reg = FDI_RX_CTL(pipe);
2754 temp = I915_READ(reg);
2755 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2756
2757 /* Disable CPU FDI TX PLL */
2758 reg = FDI_TX_CTL(pipe);
2759 temp = I915_READ(reg);
2760 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2761
2762 POSTING_READ(reg);
2763 udelay(100);
2764
2765 reg = FDI_RX_CTL(pipe);
2766 temp = I915_READ(reg);
2767 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2768
2769 /* Wait for the clocks to turn off. */
2770 POSTING_READ(reg);
2771 udelay(100);
2772}
2773
0fc932b8
JB		 2774static void ironlake_fdi_disable(struct drm_crtc *crtc)
2775{
2776 struct drm_device *dev = crtc->dev;
2777 struct drm_i915_private *dev_priv = dev->dev_private;
2778 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2779 int pipe = intel_crtc->pipe;
2780 u32 reg, temp;
2781
2782 /* disable CPU FDI tx and PCH FDI rx */
2783 reg = FDI_TX_CTL(pipe);
2784 temp = I915_READ(reg);
2785 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2786 POSTING_READ(reg);
2787
2788 reg = FDI_RX_CTL(pipe);
2789 temp = I915_READ(reg);
2790 temp &= ~(0x7 << 16);
dfd07d72 2791 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2792 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2793
2794 POSTING_READ(reg);
2795 udelay(100);
2796
2797 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2798 if (HAS_PCH_IBX(dev)) {
2799 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2800 }
0fc932b8
JB		 2801
2802 /* still set train pattern 1 */
2803 reg = FDI_TX_CTL(pipe);
2804 temp = I915_READ(reg);
2805 temp &= ~FDI_LINK_TRAIN_NONE;
2806 temp |= FDI_LINK_TRAIN_PATTERN_1;
2807 I915_WRITE(reg, temp);
2808
2809 reg = FDI_RX_CTL(pipe);
2810 temp = I915_READ(reg);
2811 if (HAS_PCH_CPT(dev)) {
2812 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2813 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2814 } else {
2815 temp &= ~FDI_LINK_TRAIN_NONE;
2816 temp |= FDI_LINK_TRAIN_PATTERN_1;
2817 }
2818 /* BPC in FDI rx is consistent with that in PIPECONF */
2819 temp &= ~(0x07 << 16);
dfd07d72 2820 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2821 I915_WRITE(reg, temp);
2822
2823 POSTING_READ(reg);
2824 udelay(100);
2825}
2826
5bb61643
CW		 2827static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2828{
2829 struct drm_device *dev = crtc->dev;
2830 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2831 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2832 unsigned long flags;
2833 bool pending;
2834
10d83730
VS		 2835 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2836 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2837 return false;
2838
2839 spin_lock_irqsave(&dev->event_lock, flags);
2840 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2841 spin_unlock_irqrestore(&dev->event_lock, flags);
2842
2843 return pending;
2844}
2845
e6c3a2a6
CW		 2846static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2847{
0f91128d 2848 struct drm_device *dev = crtc->dev;
5bb61643 2849 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2850
2851 if (crtc->fb == NULL)
2852 return;
2853
2c10d571
DV		 2854 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2855
5bb61643
CW		 2856 wait_event(dev_priv->pending_flip_queue,
2857 !intel_crtc_has_pending_flip(crtc));
2858
0f91128d
CW		 2859 mutex_lock(&dev->struct_mutex);
2860 intel_finish_fb(crtc->fb);
2861 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2862}
2863
e615efe4
ED		 2864/* Program iCLKIP clock to the desired frequency */
2865static void lpt_program_iclkip(struct drm_crtc *crtc)
2866{
2867 struct drm_device *dev = crtc->dev;
2868 struct drm_i915_private *dev_priv = dev->dev_private;
2869 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2870 u32 temp;
2871
09153000
DV		 2872 mutex_lock(&dev_priv->dpio_lock);
2873
e615efe4
ED		 2874 /* It is necessary to ungate the pixclk gate prior to programming
2875 * the divisors, and gate it back when it is done.
2876 */
2877 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2878
2879 /* Disable SSCCTL */
2880 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2881 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2882 SBI_SSCCTL_DISABLE,
2883 SBI_ICLK);
e615efe4
ED		 2884
2885 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2886 if (crtc->mode.clock == 20000) {
2887 auxdiv = 1;
2888 divsel = 0x41;
2889 phaseinc = 0x20;
2890 } else {
2891 /* The iCLK virtual clock root frequency is in MHz,
2892 * but the crtc->mode.clock in in KHz. To get the divisors,
2893 * it is necessary to divide one by another, so we
2894 * convert the virtual clock precision to KHz here for higher
2895 * precision.
2896 */
2897 u32 iclk_virtual_root_freq = 172800 * 1000;
2898 u32 iclk_pi_range = 64;
2899 u32 desired_divisor, msb_divisor_value, pi_value;
2900
2901 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2902 msb_divisor_value = desired_divisor / iclk_pi_range;
2903 pi_value = desired_divisor % iclk_pi_range;
2904
2905 auxdiv = 0;
2906 divsel = msb_divisor_value - 2;
2907 phaseinc = pi_value;
2908 }
2909
2910 /* This should not happen with any sane values */
2911 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2912 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2913 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2914 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2915
2916 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2917 crtc->mode.clock,
2918 auxdiv,
2919 divsel,
2920 phasedir,
2921 phaseinc);
2922
2923 /* Program SSCDIVINTPHASE6 */
988d6ee8 2924 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2925 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2926 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2927 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2928 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2929 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2930 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2931 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2932
2933 /* Program SSCAUXDIV */
988d6ee8 2934 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2935 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2936 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2937 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2938
2939 /* Enable modulator and associated divider */
988d6ee8 2940 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2941 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2942 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2943
2944 /* Wait for initialization time */
2945 udelay(24);
2946
2947 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2948
2949 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2950}
2951
275f01b2
DV		 2952static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2953 enum pipe pch_transcoder)
2954{
2955 struct drm_device *dev = crtc->base.dev;
2956 struct drm_i915_private *dev_priv = dev->dev_private;
2957 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2958
2959 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2960 I915_READ(HTOTAL(cpu_transcoder)));
2961 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2962 I915_READ(HBLANK(cpu_transcoder)));
2963 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2964 I915_READ(HSYNC(cpu_transcoder)));
2965
2966 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2967 I915_READ(VTOTAL(cpu_transcoder)));
2968 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2969 I915_READ(VBLANK(cpu_transcoder)));
2970 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2971 I915_READ(VSYNC(cpu_transcoder)));
2972 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2973 I915_READ(VSYNCSHIFT(cpu_transcoder)));
2974}
2975
f67a559d
JB		 2976/*
2977 * Enable PCH resources required for PCH ports:
2978 * - PCH PLLs
2979 * - FDI training & RX/TX
2980 * - update transcoder timings
2981 * - DP transcoding bits
2982 * - transcoder
2983 */
2984static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2985{
2986 struct drm_device *dev = crtc->dev;
2987 struct drm_i915_private *dev_priv = dev->dev_private;
2988 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2989 int pipe = intel_crtc->pipe;
ee7b9f93 2990 u32 reg, temp;
2c07245f 2991
ab9412ba 2992 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 2993
cd986abb
DV		 2994 /* Write the TU size bits before fdi link training, so that error
2995 * detection works. */
2996 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2997 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2998
c98e9dcf 2999 /* For PCH output, training FDI link */
674cf967 3000 dev_priv->display.fdi_link_train(crtc);
2c07245f 3001
3ad8a208
DV		 3002 /* We need to program the right clock selection before writing the pixel
3003 * mutliplier into the DPLL. */
303b81e0 3004 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3005 u32 sel;
4b645f14 3006
c98e9dcf 3007 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 3008 temp |= TRANS_DPLL_ENABLE(pipe);
3009 sel = TRANS_DPLLB_SEL(pipe);
a43f6e0f 3010 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 3011 temp |= sel;
3012 else
3013 temp &= ~sel;
c98e9dcf 3014 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3015 }
5eddb70b 3016
3ad8a208
DV		 3017 /* XXX: pch pll's can be enabled any time before we enable the PCH
3018 * transcoder, and we actually should do this to not upset any PCH
3019 * transcoder that already use the clock when we share it.
3020 *
3021 * Note that enable_shared_dpll tries to do the right thing, but
3022 * get_shared_dpll unconditionally resets the pll - we need that to have
3023 * the right LVDS enable sequence. */
3024 ironlake_enable_shared_dpll(intel_crtc);
3025
d9b6cb56
JB		 3026 /* set transcoder timing, panel must allow it */
3027 assert_panel_unlocked(dev_priv, pipe);
275f01b2 3028 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 3029
303b81e0 3030 intel_fdi_normal_train(crtc);
5e84e1a4 3031
c98e9dcf
JB		 3032 /* For PCH DP, enable TRANS_DP_CTL */
3033 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3034 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3035 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3036 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3037 reg = TRANS_DP_CTL(pipe);
3038 temp = I915_READ(reg);
3039 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3040 TRANS_DP_SYNC_MASK |
3041 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3042 temp |= (TRANS_DP_OUTPUT_ENABLE |
3043 TRANS_DP_ENH_FRAMING);
9325c9f0 3044 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3045
3046 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3047 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3048 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3049 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3050
3051 switch (intel_trans_dp_port_sel(crtc)) {
3052 case PCH_DP_B:
5eddb70b 3053 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3054 break;
3055 case PCH_DP_C:
5eddb70b 3056 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3057 break;
3058 case PCH_DP_D:
5eddb70b 3059 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3060 break;
3061 default:
e95d41e1 3062 BUG();
32f9d658 3063 }
2c07245f 3064
5eddb70b 3065 I915_WRITE(reg, temp);
6be4a607 3066 }
b52eb4dc 3067
b8a4f404 3068 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3069}
3070
1507e5bd
PZ		 3071static void lpt_pch_enable(struct drm_crtc *crtc)
3072{
3073 struct drm_device *dev = crtc->dev;
3074 struct drm_i915_private *dev_priv = dev->dev_private;
3075 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3076 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3077
ab9412ba 3078 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3079
8c52b5e8 3080 lpt_program_iclkip(crtc);
1507e5bd 3081
0540e488 3082 /* Set transcoder timing. */
275f01b2 3083 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3084
937bb610 3085 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3086}
3087
e2b78267 3088static void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3089{
e2b78267 3090 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 3091
3092 if (pll == NULL)
3093 return;
3094
3095 if (pll->refcount == 0) {
46edb027 3096 WARN(1, "bad %s refcount\n", pll->name);
ee7b9f93
JB		 3097 return;
3098 }
3099
f4a091c7
DV		 3100 if (--pll->refcount == 0) {
3101 WARN_ON(pll->on);
3102 WARN_ON(pll->active);
3103 }
3104
a43f6e0f 3105 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 3106}
3107
b89a1d39 3108static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3109{
e2b78267
DV		 3110 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3111 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3112 enum intel_dpll_id i;
ee7b9f93 3113
ee7b9f93 3114 if (pll) {
46edb027
DV		 3115 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3116 crtc->base.base.id, pll->name);
e2b78267 3117 intel_put_shared_dpll(crtc);
ee7b9f93
JB		 3118 }
3119
98b6bd99
DV		 3120 if (HAS_PCH_IBX(dev_priv->dev)) {
3121 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 3122 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 3123 pll = &dev_priv->shared_dplls[i];
98b6bd99 3124
46edb027
DV		 3125 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3126 crtc->base.base.id, pll->name);
98b6bd99
DV		 3127
3128 goto found;
3129 }
3130
e72f9fbf
DV		 3131 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3132 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 3133
3134 /* Only want to check enabled timings first */
3135 if (pll->refcount == 0)
3136 continue;
3137
b89a1d39
DV		 3138 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3139 sizeof(pll->hw_state)) == 0) {
46edb027 3140 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
e2b78267 3141 crtc->base.base.id,
46edb027 3142 pll->name, pll->refcount, pll->active);
ee7b9f93
JB		 3143
3144 goto found;
3145 }
3146 }
3147
3148 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 3149 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3150 pll = &dev_priv->shared_dplls[i];
ee7b9f93 3151 if (pll->refcount == 0) {
46edb027
DV		 3152 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3153 crtc->base.base.id, pll->name);
ee7b9f93
JB		 3154 goto found;
3155 }
3156 }
3157
3158 return NULL;
3159
3160found:
a43f6e0f 3161 crtc->config.shared_dpll = i;
46edb027
DV		 3162 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3163 pipe_name(crtc->pipe));
ee7b9f93 3164
cdbd2316 3165 if (pll->active == 0) {
66e985c0
DV		 3166 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3167 sizeof(pll->hw_state));
3168
46edb027 3169 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
cdbd2316 3170 WARN_ON(pll->on);
e9d6944e 3171 assert_shared_dpll_disabled(dev_priv, pll);
ee7b9f93 3172
15bdd4cf 3173 pll->mode_set(dev_priv, pll);
cdbd2316
DV		 3174 }
3175 pll->refcount++;
e04c7350 3176
ee7b9f93
JB		 3177 return pll;
3178}
3179
a1520318 3180static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3181{
3182 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3183 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3184 u32 temp;
3185
3186 temp = I915_READ(dslreg);
3187 udelay(500);
3188 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3189 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3190 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3191 }
3192}
3193
b074cec8
JB		 3194static void ironlake_pfit_enable(struct intel_crtc *crtc)
3195{
3196 struct drm_device *dev = crtc->base.dev;
3197 struct drm_i915_private *dev_priv = dev->dev_private;
3198 int pipe = crtc->pipe;
3199
0ef37f3f 3200 if (crtc->config.pch_pfit.size) {
b074cec8
JB		 3201 /* Force use of hard-coded filter coefficients
3202 * as some pre-programmed values are broken,
3203 * e.g. x201.
3204 */
3205 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3206 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3207 PF_PIPE_SEL_IVB(pipe));
3208 else
3209 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3210 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3211 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
d4270e57
JB		 3212 }
3213}
3214
bb53d4ae
VS		 3215static void intel_enable_planes(struct drm_crtc *crtc)
3216{
3217 struct drm_device *dev = crtc->dev;
3218 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3219 struct intel_plane *intel_plane;
3220
3221 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3222 if (intel_plane->pipe == pipe)
3223 intel_plane_restore(&intel_plane->base);
3224}
3225
3226static void intel_disable_planes(struct drm_crtc *crtc)
3227{
3228 struct drm_device *dev = crtc->dev;
3229 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3230 struct intel_plane *intel_plane;
3231
3232 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3233 if (intel_plane->pipe == pipe)
3234 intel_plane_disable(&intel_plane->base);
3235}
3236
f67a559d
JB		 3237static void ironlake_crtc_enable(struct drm_crtc *crtc)
3238{
3239 struct drm_device *dev = crtc->dev;
3240 struct drm_i915_private *dev_priv = dev->dev_private;
3241 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3242 struct intel_encoder *encoder;
f67a559d
JB		 3243 int pipe = intel_crtc->pipe;
3244 int plane = intel_crtc->plane;
f67a559d 3245
08a48469
DV		 3246 WARN_ON(!crtc->enabled);
3247
f67a559d
JB		 3248 if (intel_crtc->active)
3249 return;
3250
3251 intel_crtc->active = true;
8664281b
PZ		 3252
3253 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3254 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3255
f67a559d
JB		 3256 intel_update_watermarks(dev);
3257
f6736a1a 3258 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 3259 if (encoder->pre_enable)
3260 encoder->pre_enable(encoder);
f67a559d 3261
5bfe2ac0 3262 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3263 /* Note: FDI PLL enabling _must_ be done before we enable the
3264 * cpu pipes, hence this is separate from all the other fdi/pch
3265 * enabling. */
88cefb6c 3266 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3267 } else {
3268 assert_fdi_tx_disabled(dev_priv, pipe);
3269 assert_fdi_rx_disabled(dev_priv, pipe);
3270 }
f67a559d 3271
b074cec8 3272 ironlake_pfit_enable(intel_crtc);
f67a559d 3273
9c54c0dd
JB		 3274 /*
3275 * On ILK+ LUT must be loaded before the pipe is running but with
3276 * clocks enabled
3277 */
3278 intel_crtc_load_lut(crtc);
3279
5bfe2ac0
DV		 3280 intel_enable_pipe(dev_priv, pipe,
3281 intel_crtc->config.has_pch_encoder);
f67a559d 3282 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3283 intel_enable_planes(crtc);
5c38d48c 3284 intel_crtc_update_cursor(crtc, true);
f67a559d 3285
5bfe2ac0 3286 if (intel_crtc->config.has_pch_encoder)
f67a559d 3287 ironlake_pch_enable(crtc);
c98e9dcf 3288
d1ebd816 3289 mutex_lock(&dev->struct_mutex);
bed4a673 3290 intel_update_fbc(dev);
d1ebd816
BW		 3291 mutex_unlock(&dev->struct_mutex);
3292
fa5c73b1
DV		 3293 for_each_encoder_on_crtc(dev, crtc, encoder)
3294 encoder->enable(encoder);
61b77ddd
DV		 3295
3296 if (HAS_PCH_CPT(dev))
a1520318 3297 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3298
3299 /*
3300 * There seems to be a race in PCH platform hw (at least on some
3301 * outputs) where an enabled pipe still completes any pageflip right
3302 * away (as if the pipe is off) instead of waiting for vblank. As soon
3303 * as the first vblank happend, everything works as expected. Hence just
3304 * wait for one vblank before returning to avoid strange things
3305 * happening.
3306 */
3307 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3308}
3309
42db64ef
PZ		 3310/* IPS only exists on ULT machines and is tied to pipe A. */
3311static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3312{
f5adf94e 3313 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 3314}
3315
3316static void hsw_enable_ips(struct intel_crtc *crtc)
3317{
3318 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3319
3320 if (!crtc->config.ips_enabled)
3321 return;
3322
3323 /* We can only enable IPS after we enable a plane and wait for a vblank.
3324 * We guarantee that the plane is enabled by calling intel_enable_ips
3325 * only after intel_enable_plane. And intel_enable_plane already waits
3326 * for a vblank, so all we need to do here is to enable the IPS bit. */
3327 assert_plane_enabled(dev_priv, crtc->plane);
3328 I915_WRITE(IPS_CTL, IPS_ENABLE);
3329}
3330
3331static void hsw_disable_ips(struct intel_crtc *crtc)
3332{
3333 struct drm_device *dev = crtc->base.dev;
3334 struct drm_i915_private *dev_priv = dev->dev_private;
3335
3336 if (!crtc->config.ips_enabled)
3337 return;
3338
3339 assert_plane_enabled(dev_priv, crtc->plane);
3340 I915_WRITE(IPS_CTL, 0);
3341
3342 /* We need to wait for a vblank before we can disable the plane. */
3343 intel_wait_for_vblank(dev, crtc->pipe);
3344}
3345
4f771f10
PZ		 3346static void haswell_crtc_enable(struct drm_crtc *crtc)
3347{
3348 struct drm_device *dev = crtc->dev;
3349 struct drm_i915_private *dev_priv = dev->dev_private;
3350 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3351 struct intel_encoder *encoder;
3352 int pipe = intel_crtc->pipe;
3353 int plane = intel_crtc->plane;
4f771f10
PZ		 3354
3355 WARN_ON(!crtc->enabled);
3356
3357 if (intel_crtc->active)
3358 return;
3359
3360 intel_crtc->active = true;
8664281b
PZ		 3361
3362 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3363 if (intel_crtc->config.has_pch_encoder)
3364 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3365
4f771f10
PZ		 3366 intel_update_watermarks(dev);
3367
5bfe2ac0 3368 if (intel_crtc->config.has_pch_encoder)
04945641 3369 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3370
3371 for_each_encoder_on_crtc(dev, crtc, encoder)
3372 if (encoder->pre_enable)
3373 encoder->pre_enable(encoder);
3374
1f544388 3375 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3376
b074cec8 3377 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3378
3379 /*
3380 * On ILK+ LUT must be loaded before the pipe is running but with
3381 * clocks enabled
3382 */
3383 intel_crtc_load_lut(crtc);
3384
1f544388 3385 intel_ddi_set_pipe_settings(crtc);
8228c251 3386 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3387
5bfe2ac0
DV		 3388 intel_enable_pipe(dev_priv, pipe,
3389 intel_crtc->config.has_pch_encoder);
4f771f10 3390 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3391 intel_enable_planes(crtc);
5c38d48c 3392 intel_crtc_update_cursor(crtc, true);
4f771f10 3393
42db64ef
PZ		 3394 hsw_enable_ips(intel_crtc);
3395
5bfe2ac0 3396 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3397 lpt_pch_enable(crtc);
4f771f10
PZ		 3398
3399 mutex_lock(&dev->struct_mutex);
3400 intel_update_fbc(dev);
3401 mutex_unlock(&dev->struct_mutex);
3402
4f771f10
PZ		 3403 for_each_encoder_on_crtc(dev, crtc, encoder)
3404 encoder->enable(encoder);
3405
4f771f10
PZ		 3406 /*
3407 * There seems to be a race in PCH platform hw (at least on some
3408 * outputs) where an enabled pipe still completes any pageflip right
3409 * away (as if the pipe is off) instead of waiting for vblank. As soon
3410 * as the first vblank happend, everything works as expected. Hence just
3411 * wait for one vblank before returning to avoid strange things
3412 * happening.
3413 */
3414 intel_wait_for_vblank(dev, intel_crtc->pipe);
3415}
3416
3f8dce3a
DV		 3417static void ironlake_pfit_disable(struct intel_crtc *crtc)
3418{
3419 struct drm_device *dev = crtc->base.dev;
3420 struct drm_i915_private *dev_priv = dev->dev_private;
3421 int pipe = crtc->pipe;
3422
3423 /* To avoid upsetting the power well on haswell only disable the pfit if
3424 * it's in use. The hw state code will make sure we get this right. */
3425 if (crtc->config.pch_pfit.size) {
3426 I915_WRITE(PF_CTL(pipe), 0);
3427 I915_WRITE(PF_WIN_POS(pipe), 0);
3428 I915_WRITE(PF_WIN_SZ(pipe), 0);
3429 }
3430}
3431
6be4a607
JB		 3432static void ironlake_crtc_disable(struct drm_crtc *crtc)
3433{
3434 struct drm_device *dev = crtc->dev;
3435 struct drm_i915_private *dev_priv = dev->dev_private;
3436 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3437 struct intel_encoder *encoder;
6be4a607
JB		 3438 int pipe = intel_crtc->pipe;
3439 int plane = intel_crtc->plane;
5eddb70b 3440 u32 reg, temp;
b52eb4dc 3441
ef9c3aee 3442
f7abfe8b
CW		 3443 if (!intel_crtc->active)
3444 return;
3445
ea9d758d
DV		 3446 for_each_encoder_on_crtc(dev, crtc, encoder)
3447 encoder->disable(encoder);
3448
e6c3a2a6 3449 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3450 drm_vblank_off(dev, pipe);
913d8d11 3451
5c3fe8b0 3452 if (dev_priv->fbc.plane == plane)
973d04f9 3453 intel_disable_fbc(dev);
2c07245f 3454
0d5b8c61 3455 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3456 intel_disable_planes(crtc);
0d5b8c61
VS		 3457 intel_disable_plane(dev_priv, plane, pipe);
3458
d925c59a
DV		 3459 if (intel_crtc->config.has_pch_encoder)
3460 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3461
b24e7179 3462 intel_disable_pipe(dev_priv, pipe);
32f9d658 3463
3f8dce3a 3464 ironlake_pfit_disable(intel_crtc);
2c07245f 3465
bf49ec8c
DV		 3466 for_each_encoder_on_crtc(dev, crtc, encoder)
3467 if (encoder->post_disable)
3468 encoder->post_disable(encoder);
2c07245f 3469
d925c59a
DV		 3470 if (intel_crtc->config.has_pch_encoder) {
3471 ironlake_fdi_disable(crtc);
913d8d11 3472
d925c59a
DV		 3473 ironlake_disable_pch_transcoder(dev_priv, pipe);
3474 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
6be4a607 3475
d925c59a
DV		 3476 if (HAS_PCH_CPT(dev)) {
3477 /* disable TRANS_DP_CTL */
3478 reg = TRANS_DP_CTL(pipe);
3479 temp = I915_READ(reg);
3480 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3481 TRANS_DP_PORT_SEL_MASK);
3482 temp |= TRANS_DP_PORT_SEL_NONE;
3483 I915_WRITE(reg, temp);
3484
3485 /* disable DPLL_SEL */
3486 temp = I915_READ(PCH_DPLL_SEL);
11887397 3487 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 3488 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 3489 }
e3421a18 3490
d925c59a 3491 /* disable PCH DPLL */
e72f9fbf 3492 intel_disable_shared_dpll(intel_crtc);
8db9d77b 3493
d925c59a
DV		 3494 ironlake_fdi_pll_disable(intel_crtc);
3495 }
6b383a7f 3496
f7abfe8b 3497 intel_crtc->active = false;
6b383a7f 3498 intel_update_watermarks(dev);
d1ebd816
BW		 3499
3500 mutex_lock(&dev->struct_mutex);
6b383a7f 3501 intel_update_fbc(dev);
d1ebd816 3502 mutex_unlock(&dev->struct_mutex);
6be4a607 3503}
1b3c7a47 3504
4f771f10 3505static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3506{
4f771f10
PZ		 3507 struct drm_device *dev = crtc->dev;
3508 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3509 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3510 struct intel_encoder *encoder;
3511 int pipe = intel_crtc->pipe;
3512 int plane = intel_crtc->plane;
3b117c8f 3513 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3514
4f771f10
PZ		 3515 if (!intel_crtc->active)
3516 return;
3517
3518 for_each_encoder_on_crtc(dev, crtc, encoder)
3519 encoder->disable(encoder);
3520
3521 intel_crtc_wait_for_pending_flips(crtc);
3522 drm_vblank_off(dev, pipe);
4f771f10 3523
891348b2 3524 /* FBC must be disabled before disabling the plane on HSW. */
5c3fe8b0 3525 if (dev_priv->fbc.plane == plane)
4f771f10
PZ		 3526 intel_disable_fbc(dev);
3527
42db64ef
PZ		 3528 hsw_disable_ips(intel_crtc);
3529
0d5b8c61 3530 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3531 intel_disable_planes(crtc);
891348b2
RV		 3532 intel_disable_plane(dev_priv, plane, pipe);
3533
8664281b
PZ		 3534 if (intel_crtc->config.has_pch_encoder)
3535 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3536 intel_disable_pipe(dev_priv, pipe);
3537
ad80a810 3538 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3539
3f8dce3a 3540 ironlake_pfit_disable(intel_crtc);
4f771f10 3541
1f544388 3542 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3543
3544 for_each_encoder_on_crtc(dev, crtc, encoder)
3545 if (encoder->post_disable)
3546 encoder->post_disable(encoder);
3547
88adfff1 3548 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3549 lpt_disable_pch_transcoder(dev_priv);
8664281b 3550 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3551 intel_ddi_fdi_disable(crtc);
83616634 3552 }
4f771f10
PZ		 3553
3554 intel_crtc->active = false;
3555 intel_update_watermarks(dev);
3556
3557 mutex_lock(&dev->struct_mutex);
3558 intel_update_fbc(dev);
3559 mutex_unlock(&dev->struct_mutex);
3560}
3561
ee7b9f93
JB		 3562static void ironlake_crtc_off(struct drm_crtc *crtc)
3563{
3564 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 3565 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 3566}
3567
6441ab5f
PZ		 3568static void haswell_crtc_off(struct drm_crtc *crtc)
3569{
3570 intel_ddi_put_crtc_pll(crtc);
3571}
3572
02e792fb
DV		 3573static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3574{
02e792fb 3575 if (!enable && intel_crtc->overlay) {
23f09ce3 3576 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3577 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3578
23f09ce3 3579 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3580 dev_priv->mm.interruptible = false;
3581 (void) intel_overlay_switch_off(intel_crtc->overlay);
3582 dev_priv->mm.interruptible = true;
23f09ce3 3583 mutex_unlock(&dev->struct_mutex);
02e792fb 3584 }
02e792fb 3585
5dcdbcb0
CW		 3586 /* Let userspace switch the overlay on again. In most cases userspace
3587 * has to recompute where to put it anyway.
3588 */
02e792fb
DV		 3589}
3590
61bc95c1
EE		 3591/**
3592 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3593 * cursor plane briefly if not already running after enabling the display
3594 * plane.
3595 * This workaround avoids occasional blank screens when self refresh is
3596 * enabled.
3597 */
3598static void
3599g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3600{
3601 u32 cntl = I915_READ(CURCNTR(pipe));
3602
3603 if ((cntl & CURSOR_MODE) == 0) {
3604 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3605
3606 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3607 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3608 intel_wait_for_vblank(dev_priv->dev, pipe);
3609 I915_WRITE(CURCNTR(pipe), cntl);
3610 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3611 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3612 }
3613}
3614
2dd24552
JB		 3615static void i9xx_pfit_enable(struct intel_crtc *crtc)
3616{
3617 struct drm_device *dev = crtc->base.dev;
3618 struct drm_i915_private *dev_priv = dev->dev_private;
3619 struct intel_crtc_config *pipe_config = &crtc->config;
3620
328d8e82 3621 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3622 return;
3623
2dd24552 3624 /*
c0b03411
DV		 3625 * The panel fitter should only be adjusted whilst the pipe is disabled,
3626 * according to register description and PRM.
2dd24552 3627 */
c0b03411
DV		 3628 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3629 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3630
b074cec8
JB		 3631 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3632 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3633
3634 /* Border color in case we don't scale up to the full screen. Black by
3635 * default, change to something else for debugging. */
3636 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3637}
3638
89b667f8
JB		 3639static void valleyview_crtc_enable(struct drm_crtc *crtc)
3640{
3641 struct drm_device *dev = crtc->dev;
3642 struct drm_i915_private *dev_priv = dev->dev_private;
3643 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3644 struct intel_encoder *encoder;
3645 int pipe = intel_crtc->pipe;
3646 int plane = intel_crtc->plane;
3647
3648 WARN_ON(!crtc->enabled);
3649
3650 if (intel_crtc->active)
3651 return;
3652
3653 intel_crtc->active = true;
3654 intel_update_watermarks(dev);
3655
3656 mutex_lock(&dev_priv->dpio_lock);
3657
3658 for_each_encoder_on_crtc(dev, crtc, encoder)
3659 if (encoder->pre_pll_enable)
3660 encoder->pre_pll_enable(encoder);
3661
426115cf 3662 vlv_enable_pll(intel_crtc);
89b667f8
JB		 3663
3664 for_each_encoder_on_crtc(dev, crtc, encoder)
3665 if (encoder->pre_enable)
3666 encoder->pre_enable(encoder);
3667
3668 /* VLV wants encoder enabling _before_ the pipe is up. */
3669 for_each_encoder_on_crtc(dev, crtc, encoder)
3670 encoder->enable(encoder);
3671
2dd24552
JB		 3672 i9xx_pfit_enable(intel_crtc);
3673
63cbb074
VS		 3674 intel_crtc_load_lut(crtc);
3675
89b667f8
JB		 3676 intel_enable_pipe(dev_priv, pipe, false);
3677 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3678 intel_enable_planes(crtc);
5c38d48c 3679 intel_crtc_update_cursor(crtc, true);
89b667f8 3680
89b667f8
JB		 3681 intel_update_fbc(dev);
3682
89b667f8
JB		 3683 mutex_unlock(&dev_priv->dpio_lock);
3684}
3685
0b8765c6 3686static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3687{
3688 struct drm_device *dev = crtc->dev;
79e53945
JB		 3689 struct drm_i915_private *dev_priv = dev->dev_private;
3690 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3691 struct intel_encoder *encoder;
79e53945 3692 int pipe = intel_crtc->pipe;
80824003 3693 int plane = intel_crtc->plane;
79e53945 3694
08a48469
DV		 3695 WARN_ON(!crtc->enabled);
3696
f7abfe8b
CW		 3697 if (intel_crtc->active)
3698 return;
3699
3700 intel_crtc->active = true;
6b383a7f
CW		 3701 intel_update_watermarks(dev);
3702
9d6d9f19
MK		 3703 for_each_encoder_on_crtc(dev, crtc, encoder)
3704 if (encoder->pre_enable)
3705 encoder->pre_enable(encoder);
3706
f6736a1a
DV		 3707 i9xx_enable_pll(intel_crtc);
3708
2dd24552
JB		 3709 i9xx_pfit_enable(intel_crtc);
3710
63cbb074
VS		 3711 intel_crtc_load_lut(crtc);
3712
040484af 3713 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3714 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3715 intel_enable_planes(crtc);
22e407d7 3716 /* The fixup needs to happen before cursor is enabled */
61bc95c1
EE		 3717 if (IS_G4X(dev))
3718 g4x_fixup_plane(dev_priv, pipe);
22e407d7 3719 intel_crtc_update_cursor(crtc, true);
79e53945 3720
0b8765c6
JB		 3721 /* Give the overlay scaler a chance to enable if it's on this pipe */
3722 intel_crtc_dpms_overlay(intel_crtc, true);
ef9c3aee 3723
f440eb13 3724 intel_update_fbc(dev);
ef9c3aee 3725
fa5c73b1
DV		 3726 for_each_encoder_on_crtc(dev, crtc, encoder)
3727 encoder->enable(encoder);
0b8765c6 3728}
79e53945 3729
87476d63
DV		 3730static void i9xx_pfit_disable(struct intel_crtc *crtc)
3731{
3732 struct drm_device *dev = crtc->base.dev;
3733 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3734
328d8e82
DV		 3735 if (!crtc->config.gmch_pfit.control)
3736 return;
87476d63 3737
328d8e82 3738 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3739
328d8e82
DV		 3740 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3741 I915_READ(PFIT_CONTROL));
3742 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3743}
3744
0b8765c6
JB		 3745static void i9xx_crtc_disable(struct drm_crtc *crtc)
3746{
3747 struct drm_device *dev = crtc->dev;
3748 struct drm_i915_private *dev_priv = dev->dev_private;
3749 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3750 struct intel_encoder *encoder;
0b8765c6
JB		 3751 int pipe = intel_crtc->pipe;
3752 int plane = intel_crtc->plane;
ef9c3aee 3753
f7abfe8b
CW		 3754 if (!intel_crtc->active)
3755 return;
3756
ea9d758d
DV		 3757 for_each_encoder_on_crtc(dev, crtc, encoder)
3758 encoder->disable(encoder);
3759
0b8765c6 3760 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3761 intel_crtc_wait_for_pending_flips(crtc);
3762 drm_vblank_off(dev, pipe);
0b8765c6 3763
5c3fe8b0 3764 if (dev_priv->fbc.plane == plane)
973d04f9 3765 intel_disable_fbc(dev);
79e53945 3766
0d5b8c61
VS		 3767 intel_crtc_dpms_overlay(intel_crtc, false);
3768 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3769 intel_disable_planes(crtc);
b24e7179 3770 intel_disable_plane(dev_priv, plane, pipe);
0d5b8c61 3771
b24e7179 3772 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3773
87476d63 3774 i9xx_pfit_disable(intel_crtc);
24a1f16d 3775
89b667f8
JB		 3776 for_each_encoder_on_crtc(dev, crtc, encoder)
3777 if (encoder->post_disable)
3778 encoder->post_disable(encoder);
3779
50b44a44 3780 i9xx_disable_pll(dev_priv, pipe);
0b8765c6 3781
f7abfe8b 3782 intel_crtc->active = false;
6b383a7f
CW		 3783 intel_update_fbc(dev);
3784 intel_update_watermarks(dev);
0b8765c6
JB		 3785}
3786
ee7b9f93
JB		 3787static void i9xx_crtc_off(struct drm_crtc *crtc)
3788{
3789}
3790
976f8a20
DV		 3791static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3792 bool enabled)
2c07245f
ZW		 3793{
3794 struct drm_device *dev = crtc->dev;
3795 struct drm_i915_master_private *master_priv;
3796 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3797 int pipe = intel_crtc->pipe;
79e53945
JB		 3798
3799 if (!dev->primary->master)
3800 return;
3801
3802 master_priv = dev->primary->master->driver_priv;
3803 if (!master_priv->sarea_priv)
3804 return;
3805
79e53945
JB		 3806 switch (pipe) {
3807 case 0:
3808 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3809 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3810 break;
3811 case 1:
3812 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3813 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3814 break;
3815 default:
9db4a9c7 3816 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3817 break;
3818 }
79e53945
JB		 3819}
3820
976f8a20
DV		 3821/**
3822 * Sets the power management mode of the pipe and plane.
3823 */
3824void intel_crtc_update_dpms(struct drm_crtc *crtc)
3825{
3826 struct drm_device *dev = crtc->dev;
3827 struct drm_i915_private *dev_priv = dev->dev_private;
3828 struct intel_encoder *intel_encoder;
3829 bool enable = false;
3830
3831 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3832 enable |= intel_encoder->connectors_active;
3833
3834 if (enable)
3835 dev_priv->display.crtc_enable(crtc);
3836 else
3837 dev_priv->display.crtc_disable(crtc);
3838
3839 intel_crtc_update_sarea(crtc, enable);
3840}
3841
cdd59983
CW		 3842static void intel_crtc_disable(struct drm_crtc *crtc)
3843{
cdd59983 3844 struct drm_device *dev = crtc->dev;
976f8a20 3845 struct drm_connector *connector;
ee7b9f93 3846 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3847 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3848
976f8a20
DV		 3849 /* crtc should still be enabled when we disable it. */
3850 WARN_ON(!crtc->enabled);
3851
3852 dev_priv->display.crtc_disable(crtc);
c77bf565 3853 intel_crtc->eld_vld = false;
976f8a20 3854 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3855 dev_priv->display.off(crtc);
3856
931872fc
CW		 3857 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3858 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3859
3860 if (crtc->fb) {
3861 mutex_lock(&dev->struct_mutex);
1690e1eb 3862 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3863 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3864 crtc->fb = NULL;
3865 }
3866
3867 /* Update computed state. */
3868 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3869 if (!connector->encoder || !connector->encoder->crtc)
3870 continue;
3871
3872 if (connector->encoder->crtc != crtc)
3873 continue;
3874
3875 connector->dpms = DRM_MODE_DPMS_OFF;
3876 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3877 }
3878}
3879
a261b246 3880void intel_modeset_disable(struct drm_device *dev)
79e53945 3881{
a261b246
DV		 3882 struct drm_crtc *crtc;
3883
3884 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3885 if (crtc->enabled)
3886 intel_crtc_disable(crtc);
3887 }
79e53945
JB		 3888}
3889
ea5b213a 3890void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3891{
4ef69c7a 3892 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3893
ea5b213a
CW		 3894 drm_encoder_cleanup(encoder);
3895 kfree(intel_encoder);
7e7d76c3
JB		 3896}
3897
5ab432ef
DV		 3898/* Simple dpms helper for encodres with just one connector, no cloning and only
3899 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3900 * state of the entire output pipe. */
3901void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3902{
5ab432ef
DV		 3903 if (mode == DRM_MODE_DPMS_ON) {
3904 encoder->connectors_active = true;
3905
b2cabb0e 3906 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3907 } else {
3908 encoder->connectors_active = false;
3909
b2cabb0e 3910 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3911 }
79e53945
JB		 3912}
3913
0a91ca29
DV		 3914/* Cross check the actual hw state with our own modeset state tracking (and it's
3915 * internal consistency). */
b980514c 3916static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3917{
0a91ca29
DV		 3918 if (connector->get_hw_state(connector)) {
3919 struct intel_encoder *encoder = connector->encoder;
3920 struct drm_crtc *crtc;
3921 bool encoder_enabled;
3922 enum pipe pipe;
3923
3924 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3925 connector->base.base.id,
3926 drm_get_connector_name(&connector->base));
3927
3928 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3929 "wrong connector dpms state\n");
3930 WARN(connector->base.encoder != &encoder->base,
3931 "active connector not linked to encoder\n");
3932 WARN(!encoder->connectors_active,
3933 "encoder->connectors_active not set\n");
3934
3935 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3936 WARN(!encoder_enabled, "encoder not enabled\n");
3937 if (WARN_ON(!encoder->base.crtc))
3938 return;
3939
3940 crtc = encoder->base.crtc;
3941
3942 WARN(!crtc->enabled, "crtc not enabled\n");
3943 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3944 WARN(pipe != to_intel_crtc(crtc)->pipe,
3945 "encoder active on the wrong pipe\n");
3946 }
79e53945
JB		 3947}
3948
5ab432ef
DV		 3949/* Even simpler default implementation, if there's really no special case to
3950 * consider. */
3951void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3952{
5ab432ef 3953 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3954
5ab432ef
DV		 3955 /* All the simple cases only support two dpms states. */
3956 if (mode != DRM_MODE_DPMS_ON)
3957 mode = DRM_MODE_DPMS_OFF;
d4270e57 3958
5ab432ef
DV		 3959 if (mode == connector->dpms)
3960 return;
3961
3962 connector->dpms = mode;
3963
3964 /* Only need to change hw state when actually enabled */
3965 if (encoder->base.crtc)
3966 intel_encoder_dpms(encoder, mode);
3967 else
8af6cf88 3968 WARN_ON(encoder->connectors_active != false);
0a91ca29 3969
b980514c 3970 intel_modeset_check_state(connector->dev);
79e53945
JB		 3971}
3972
f0947c37
DV		 3973/* Simple connector->get_hw_state implementation for encoders that support only
3974 * one connector and no cloning and hence the encoder state determines the state
3975 * of the connector. */
3976bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3977{
24929352 3978 enum pipe pipe = 0;
f0947c37 3979 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3980
f0947c37 3981 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3982}
3983
1857e1da
DV		 3984static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3985 struct intel_crtc_config *pipe_config)
3986{
3987 struct drm_i915_private *dev_priv = dev->dev_private;
3988 struct intel_crtc *pipe_B_crtc =
3989 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3990
3991 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3992 pipe_name(pipe), pipe_config->fdi_lanes);
3993 if (pipe_config->fdi_lanes > 4) {
3994 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3995 pipe_name(pipe), pipe_config->fdi_lanes);
3996 return false;
3997 }
3998
3999 if (IS_HASWELL(dev)) {
4000 if (pipe_config->fdi_lanes > 2) {
4001 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4002 pipe_config->fdi_lanes);
4003 return false;
4004 } else {
4005 return true;
4006 }
4007 }
4008
4009 if (INTEL_INFO(dev)->num_pipes == 2)
4010 return true;
4011
4012 /* Ivybridge 3 pipe is really complicated */
4013 switch (pipe) {
4014 case PIPE_A:
4015 return true;
4016 case PIPE_B:
4017 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4018 pipe_config->fdi_lanes > 2) {
4019 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4020 pipe_name(pipe), pipe_config->fdi_lanes);
4021 return false;
4022 }
4023 return true;
4024 case PIPE_C:
1e833f40 4025 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 4026 pipe_B_crtc->config.fdi_lanes <= 2) {
4027 if (pipe_config->fdi_lanes > 2) {
4028 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4029 pipe_name(pipe), pipe_config->fdi_lanes);
4030 return false;
4031 }
4032 } else {
4033 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4034 return false;
4035 }
4036 return true;
4037 default:
4038 BUG();
4039 }
4040}
4041
e29c22c0
DV		 4042#define RETRY 1
4043static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4044 struct intel_crtc_config *pipe_config)
877d48d5 4045{
1857e1da 4046 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 4047 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 4048 int lane, link_bw, fdi_dotclock;
e29c22c0 4049 bool setup_ok, needs_recompute = false;
877d48d5 4050
e29c22c0 4051retry:
877d48d5
DV		 4052 /* FDI is a binary signal running at ~2.7GHz, encoding
4053 * each output octet as 10 bits. The actual frequency
4054 * is stored as a divider into a 100MHz clock, and the
4055 * mode pixel clock is stored in units of 1KHz.
4056 * Hence the bw of each lane in terms of the mode signal
4057 * is:
4058 */
4059 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4060
ff9a6750 4061 fdi_dotclock = adjusted_mode->clock;
ef1b460d 4062 fdi_dotclock /= pipe_config->pixel_multiplier;
877d48d5 4063
2bd89a07 4064 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 4065 pipe_config->pipe_bpp);
4066
4067 pipe_config->fdi_lanes = lane;
4068
2bd89a07 4069 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4070 link_bw, &pipe_config->fdi_m_n);
1857e1da 4071
e29c22c0
DV		 4072 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4073 intel_crtc->pipe, pipe_config);
4074 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4075 pipe_config->pipe_bpp -= 2*3;
4076 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4077 pipe_config->pipe_bpp);
4078 needs_recompute = true;
4079 pipe_config->bw_constrained = true;
4080
4081 goto retry;
4082 }
4083
4084 if (needs_recompute)
4085 return RETRY;
4086
4087 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4088}
4089
42db64ef
PZ		 4090static void hsw_compute_ips_config(struct intel_crtc *crtc,
4091 struct intel_crtc_config *pipe_config)
4092{
3c4ca58c
PZ		 4093 pipe_config->ips_enabled = i915_enable_ips &&
4094 hsw_crtc_supports_ips(crtc) &&
42db64ef
PZ		 4095 pipe_config->pipe_bpp == 24;
4096}
4097
a43f6e0f 4098static int intel_crtc_compute_config(struct intel_crtc *crtc,
e29c22c0 4099 struct intel_crtc_config *pipe_config)
79e53945 4100{
a43f6e0f 4101 struct drm_device *dev = crtc->base.dev;
b8cecdf5 4102 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4103
bad720ff 4104 if (HAS_PCH_SPLIT(dev)) {
2c07245f 4105 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 4106 if (pipe_config->requested_mode.clock * 3
4107 > IRONLAKE_FDI_FREQ * 4)
e29c22c0 4108 return -EINVAL;
2c07245f 4109 }
89749350 4110
f9bef081
DV		 4111 /* All interlaced capable intel hw wants timings in frames. Note though
4112 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4113 * timings, so we need to be careful not to clobber these.*/
7ae89233 4114 if (!pipe_config->timings_set)
f9bef081 4115 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 4116
8693a824
DL		 4117 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4118 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4119 */
4120 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4121 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4122 return -EINVAL;
44f46b42 4123
bd080ee5 4124 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4125 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4126 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4127 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4128 * for lvds. */
4129 pipe_config->pipe_bpp = 8*3;
4130 }
4131
f5adf94e 4132 if (HAS_IPS(dev))
a43f6e0f
DV		 4133 hsw_compute_ips_config(crtc, pipe_config);
4134
4135 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4136 * clock survives for now. */
4137 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4138 pipe_config->shared_dpll = crtc->config.shared_dpll;
42db64ef 4139
877d48d5 4140 if (pipe_config->has_pch_encoder)
a43f6e0f 4141 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 4142
e29c22c0 4143 return 0;
79e53945
JB		 4144}
4145
25eb05fc
JB		 4146static int valleyview_get_display_clock_speed(struct drm_device *dev)
4147{
4148 return 400000; /* FIXME */
4149}
4150
e70236a8
JB		 4151static int i945_get_display_clock_speed(struct drm_device *dev)
4152{
4153 return 400000;
4154}
79e53945 4155
e70236a8 4156static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4157{
e70236a8
JB		 4158 return 333000;
4159}
79e53945 4160
e70236a8
JB		 4161static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4162{
4163 return 200000;
4164}
79e53945 4165
257a7ffc
DV		 4166static int pnv_get_display_clock_speed(struct drm_device *dev)
4167{
4168 u16 gcfgc = 0;
4169
4170 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4171
4172 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4173 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4174 return 267000;
4175 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4176 return 333000;
4177 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4178 return 444000;
4179 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4180 return 200000;
4181 default:
4182 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4183 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4184 return 133000;
4185 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4186 return 167000;
4187 }
4188}
4189
e70236a8
JB		 4190static int i915gm_get_display_clock_speed(struct drm_device *dev)
4191{
4192 u16 gcfgc = 0;
79e53945 4193
e70236a8
JB		 4194 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4195
4196 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4197 return 133000;
4198 else {
4199 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4200 case GC_DISPLAY_CLOCK_333_MHZ:
4201 return 333000;
4202 default:
4203 case GC_DISPLAY_CLOCK_190_200_MHZ:
4204 return 190000;
79e53945 4205 }
e70236a8
JB		 4206 }
4207}
4208
4209static int i865_get_display_clock_speed(struct drm_device *dev)
4210{
4211 return 266000;
4212}
4213
4214static int i855_get_display_clock_speed(struct drm_device *dev)
4215{
4216 u16 hpllcc = 0;
4217 /* Assume that the hardware is in the high speed state. This
4218 * should be the default.
4219 */
4220 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4221 case GC_CLOCK_133_200:
4222 case GC_CLOCK_100_200:
4223 return 200000;
4224 case GC_CLOCK_166_250:
4225 return 250000;
4226 case GC_CLOCK_100_133:
79e53945 4227 return 133000;
e70236a8 4228 }
79e53945 4229
e70236a8
JB		 4230 /* Shouldn't happen */
4231 return 0;
4232}
79e53945 4233
e70236a8
JB		 4234static int i830_get_display_clock_speed(struct drm_device *dev)
4235{
4236 return 133000;
79e53945
JB		 4237}
4238
2c07245f 4239static void
a65851af 4240intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4241{
a65851af
VS		 4242 while (*num > DATA_LINK_M_N_MASK ||
4243 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4244 *num >>= 1;
4245 *den >>= 1;
4246 }
4247}
4248
a65851af
VS		 4249static void compute_m_n(unsigned int m, unsigned int n,
4250 uint32_t *ret_m, uint32_t *ret_n)
4251{
4252 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4253 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4254 intel_reduce_m_n_ratio(ret_m, ret_n);
4255}
4256
e69d0bc1
DV		 4257void
4258intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4259 int pixel_clock, int link_clock,
4260 struct intel_link_m_n *m_n)
2c07245f 4261{
e69d0bc1 4262 m_n->tu = 64;
a65851af
VS		 4263
4264 compute_m_n(bits_per_pixel * pixel_clock,
4265 link_clock * nlanes * 8,
4266 &m_n->gmch_m, &m_n->gmch_n);
4267
4268 compute_m_n(pixel_clock, link_clock,
4269 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4270}
4271
a7615030
CW		 4272static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4273{
72bbe58c
KP		 4274 if (i915_panel_use_ssc >= 0)
4275 return i915_panel_use_ssc != 0;
41aa3448 4276 return dev_priv->vbt.lvds_use_ssc
435793df 4277 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4278}
4279
a0c4da24
JB		 4280static int vlv_get_refclk(struct drm_crtc *crtc)
4281{
4282 struct drm_device *dev = crtc->dev;
4283 struct drm_i915_private *dev_priv = dev->dev_private;
4284 int refclk = 27000; /* for DP & HDMI */
4285
4286 return 100000; /* only one validated so far */
4287
4288 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4289 refclk = 96000;
4290 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4291 if (intel_panel_use_ssc(dev_priv))
4292 refclk = 100000;
4293 else
4294 refclk = 96000;
4295 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4296 refclk = 100000;
4297 }
4298
4299 return refclk;
4300}
4301
c65d77d8
JB		 4302static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4303{
4304 struct drm_device *dev = crtc->dev;
4305 struct drm_i915_private *dev_priv = dev->dev_private;
4306 int refclk;
4307
a0c4da24
JB		 4308 if (IS_VALLEYVIEW(dev)) {
4309 refclk = vlv_get_refclk(crtc);
4310 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4311 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4312 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4313 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4314 refclk / 1000);
4315 } else if (!IS_GEN2(dev)) {
4316 refclk = 96000;
4317 } else {
4318 refclk = 48000;
4319 }
4320
4321 return refclk;
4322}
4323
7429e9d4 4324static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 4325{
7df00d7a 4326 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 4327}
f47709a9 4328
7429e9d4
DV		 4329static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4330{
4331 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 4332}
4333
f47709a9 4334static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4335 intel_clock_t *reduced_clock)
4336{
f47709a9 4337 struct drm_device *dev = crtc->base.dev;
a7516a05 4338 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4339 int pipe = crtc->pipe;
a7516a05
JB		 4340 u32 fp, fp2 = 0;
4341
4342 if (IS_PINEVIEW(dev)) {
7429e9d4 4343 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4344 if (reduced_clock)
7429e9d4 4345 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4346 } else {
7429e9d4 4347 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4348 if (reduced_clock)
7429e9d4 4349 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4350 }
4351
4352 I915_WRITE(FP0(pipe), fp);
8bcc2795 4353 crtc->config.dpll_hw_state.fp0 = fp;
a7516a05 4354
f47709a9
DV		 4355 crtc->lowfreq_avail = false;
4356 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4357 reduced_clock && i915_powersave) {
4358 I915_WRITE(FP1(pipe), fp2);
8bcc2795 4359 crtc->config.dpll_hw_state.fp1 = fp2;
f47709a9 4360 crtc->lowfreq_avail = true;
a7516a05
JB		 4361 } else {
4362 I915_WRITE(FP1(pipe), fp);
8bcc2795 4363 crtc->config.dpll_hw_state.fp1 = fp;
a7516a05
JB		 4364 }
4365}
4366
89b667f8
JB		 4367static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4368{
4369 u32 reg_val;
4370
4371 /*
4372 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4373 * and set it to a reasonable value instead.
4374 */
ae99258f 4375 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8
JB		 4376 reg_val &= 0xffffff00;
4377 reg_val |= 0x00000030;
ae99258f 4378 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4379
ae99258f 4380 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4381 reg_val &= 0x8cffffff;
4382 reg_val = 0x8c000000;
ae99258f 4383 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8 4384
ae99258f 4385 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8 4386 reg_val &= 0xffffff00;
ae99258f 4387 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4388
ae99258f 4389 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4390 reg_val &= 0x00ffffff;
4391 reg_val |= 0xb0000000;
ae99258f 4392 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4393}
4394
b551842d
DV		 4395static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4396 struct intel_link_m_n *m_n)
4397{
4398 struct drm_device *dev = crtc->base.dev;
4399 struct drm_i915_private *dev_priv = dev->dev_private;
4400 int pipe = crtc->pipe;
4401
e3b95f1e
DV		 4402 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4403 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4404 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4405 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4406}
4407
4408static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4409 struct intel_link_m_n *m_n)
4410{
4411 struct drm_device *dev = crtc->base.dev;
4412 struct drm_i915_private *dev_priv = dev->dev_private;
4413 int pipe = crtc->pipe;
4414 enum transcoder transcoder = crtc->config.cpu_transcoder;
4415
4416 if (INTEL_INFO(dev)->gen >= 5) {
4417 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4418 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4419 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4420 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4421 } else {
e3b95f1e
DV		 4422 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4423 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4424 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4425 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4426 }
4427}
4428
03afc4a2
DV		 4429static void intel_dp_set_m_n(struct intel_crtc *crtc)
4430{
4431 if (crtc->config.has_pch_encoder)
4432 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4433 else
4434 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4435}
4436
f47709a9 4437static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4438{
f47709a9 4439 struct drm_device *dev = crtc->base.dev;
a0c4da24 4440 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4441 int pipe = crtc->pipe;
89b667f8 4442 u32 dpll, mdiv;
a0c4da24 4443 u32 bestn, bestm1, bestm2, bestp1, bestp2;
89b667f8 4444 bool is_hdmi;
198a037f 4445 u32 coreclk, reg_val, dpll_md;
a0c4da24 4446
09153000
DV		 4447 mutex_lock(&dev_priv->dpio_lock);
4448
89b667f8 4449 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
a0c4da24 4450
f47709a9
DV		 4451 bestn = crtc->config.dpll.n;
4452 bestm1 = crtc->config.dpll.m1;
4453 bestm2 = crtc->config.dpll.m2;
4454 bestp1 = crtc->config.dpll.p1;
4455 bestp2 = crtc->config.dpll.p2;
a0c4da24 4456
89b667f8
JB		 4457 /* See eDP HDMI DPIO driver vbios notes doc */
4458
4459 /* PLL B needs special handling */
4460 if (pipe)
4461 vlv_pllb_recal_opamp(dev_priv);
4462
4463 /* Set up Tx target for periodic Rcomp update */
ae99258f 4464 vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4465
4466 /* Disable target IRef on PLL */
ae99258f 4467 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
89b667f8 4468 reg_val &= 0x00ffffff;
ae99258f 4469 vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4470
4471 /* Disable fast lock */
ae99258f 4472 vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4473
4474 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4475 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4476 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4477 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4478 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4479
4480 /*
4481 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4482 * but we don't support that).
4483 * Note: don't use the DAC post divider as it seems unstable.
4484 */
4485 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ae99258f 4486 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4487
a0c4da24 4488 mdiv |= DPIO_ENABLE_CALIBRATION;
ae99258f 4489 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4490
89b667f8 4491 /* Set HBR and RBR LPF coefficients */
ff9a6750 4492 if (crtc->config.port_clock == 162000 ||
99750bd4 4493 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
89b667f8 4494 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4abb2c39 4495 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
885b0120 4496 0x009f0003);
89b667f8 4497 else
4abb2c39 4498 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
89b667f8
JB		 4499 0x00d0000f);
4500
4501 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4502 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4503 /* Use SSC source */
4504 if (!pipe)
ae99258f 4505 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4506 0x0df40000);
4507 else
ae99258f 4508 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4509 0x0df70000);
4510 } else { /* HDMI or VGA */
4511 /* Use bend source */
4512 if (!pipe)
ae99258f 4513 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4514 0x0df70000);
4515 else
ae99258f 4516 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4517 0x0df40000);
4518 }
a0c4da24 4519
ae99258f 4520 coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4521 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4522 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4523 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4524 coreclk |= 0x01000000;
ae99258f 4525 vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4526
ae99258f 4527 vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4528
89b667f8
JB		 4529 /* Enable DPIO clock input */
4530 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4531 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4532 if (pipe)
4533 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
a0c4da24
JB		 4534
4535 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4536 crtc->config.dpll_hw_state.dpll = dpll;
4537
ef1b460d
DV		 4538 dpll_md = (crtc->config.pixel_multiplier - 1)
4539 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795
DV		 4540 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4541
89b667f8
JB		 4542 if (crtc->config.has_dp_encoder)
4543 intel_dp_set_m_n(crtc);
09153000
DV		 4544
4545 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4546}
4547
f47709a9
DV		 4548static void i9xx_update_pll(struct intel_crtc *crtc,
4549 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4550 int num_connectors)
4551{
f47709a9 4552 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4553 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 4554 u32 dpll;
4555 bool is_sdvo;
f47709a9 4556 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4557
f47709a9 4558 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4559
f47709a9
DV		 4560 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4561 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4562
4563 dpll = DPLL_VGA_MODE_DIS;
4564
f47709a9 4565 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4566 dpll |= DPLLB_MODE_LVDS;
4567 else
4568 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4569
ef1b460d 4570 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
198a037f
DV		 4571 dpll |= (crtc->config.pixel_multiplier - 1)
4572 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4573 }
198a037f
DV		 4574
4575 if (is_sdvo)
4a33e48d 4576 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 4577
f47709a9 4578 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4a33e48d 4579 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 4580
4581 /* compute bitmask from p1 value */
4582 if (IS_PINEVIEW(dev))
4583 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4584 else {
4585 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4586 if (IS_G4X(dev) && reduced_clock)
4587 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4588 }
4589 switch (clock->p2) {
4590 case 5:
4591 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4592 break;
4593 case 7:
4594 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4595 break;
4596 case 10:
4597 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4598 break;
4599 case 14:
4600 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4601 break;
4602 }
4603 if (INTEL_INFO(dev)->gen >= 4)
4604 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4605
09ede541 4606 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4607 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4608 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4609 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4610 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4611 else
4612 dpll |= PLL_REF_INPUT_DREFCLK;
4613
4614 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4615 crtc->config.dpll_hw_state.dpll = dpll;
4616
eb1cbe48 4617 if (INTEL_INFO(dev)->gen >= 4) {
ef1b460d
DV		 4618 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4619 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795 4620 crtc->config.dpll_hw_state.dpll_md = dpll_md;
eb1cbe48 4621 }
66e3d5c0
DV		 4622
4623 if (crtc->config.has_dp_encoder)
4624 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4625}
4626
f47709a9 4627static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 4628 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4629 int num_connectors)
4630{
f47709a9 4631 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4632 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 4633 u32 dpll;
f47709a9 4634 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4635
f47709a9 4636 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4637
eb1cbe48
DV		 4638 dpll = DPLL_VGA_MODE_DIS;
4639
f47709a9 4640 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4641 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4642 } else {
4643 if (clock->p1 == 2)
4644 dpll |= PLL_P1_DIVIDE_BY_TWO;
4645 else
4646 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4647 if (clock->p2 == 4)
4648 dpll |= PLL_P2_DIVIDE_BY_4;
4649 }
4650
4a33e48d
DV		 4651 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4652 dpll |= DPLL_DVO_2X_MODE;
4653
f47709a9 4654 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4655 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4656 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4657 else
4658 dpll |= PLL_REF_INPUT_DREFCLK;
4659
4660 dpll |= DPLL_VCO_ENABLE;
8bcc2795 4661 crtc->config.dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 4662}
4663
8a654f3b 4664static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 4665{
4666 struct drm_device *dev = intel_crtc->base.dev;
4667 struct drm_i915_private *dev_priv = dev->dev_private;
4668 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4669 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV		 4670 struct drm_display_mode *adjusted_mode =
4671 &intel_crtc->config.adjusted_mode;
4672 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4d8a62ea
DV		 4673 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4674
4675 /* We need to be careful not to changed the adjusted mode, for otherwise
4676 * the hw state checker will get angry at the mismatch. */
4677 crtc_vtotal = adjusted_mode->crtc_vtotal;
4678 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4679
4680 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4681 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4682 crtc_vtotal -= 1;
4683 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4684 vsyncshift = adjusted_mode->crtc_hsync_start
4685 - adjusted_mode->crtc_htotal / 2;
4686 } else {
4687 vsyncshift = 0;
4688 }
4689
4690 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4691 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4692
fe2b8f9d 4693 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4694 (adjusted_mode->crtc_hdisplay - 1) |
4695 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4696 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4697 (adjusted_mode->crtc_hblank_start - 1) |
4698 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4699 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4700 (adjusted_mode->crtc_hsync_start - 1) |
4701 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4702
fe2b8f9d 4703 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4704 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4705 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4706 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4707 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4708 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4709 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4710 (adjusted_mode->crtc_vsync_start - 1) |
4711 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4712
b5e508d4
PZ		 4713 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4714 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4715 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4716 * bits. */
4717 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4718 (pipe == PIPE_B || pipe == PIPE_C))
4719 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4720
b0e77b9c
PZ		 4721 /* pipesrc controls the size that is scaled from, which should
4722 * always be the user's requested size.
4723 */
4724 I915_WRITE(PIPESRC(pipe),
4725 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4726}
4727
1bd1bd80
DV		 4728static void intel_get_pipe_timings(struct intel_crtc *crtc,
4729 struct intel_crtc_config *pipe_config)
4730{
4731 struct drm_device *dev = crtc->base.dev;
4732 struct drm_i915_private *dev_priv = dev->dev_private;
4733 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4734 uint32_t tmp;
4735
4736 tmp = I915_READ(HTOTAL(cpu_transcoder));
4737 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4738 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4739 tmp = I915_READ(HBLANK(cpu_transcoder));
4740 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4741 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4742 tmp = I915_READ(HSYNC(cpu_transcoder));
4743 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4744 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4745
4746 tmp = I915_READ(VTOTAL(cpu_transcoder));
4747 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4748 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4749 tmp = I915_READ(VBLANK(cpu_transcoder));
4750 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4751 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4752 tmp = I915_READ(VSYNC(cpu_transcoder));
4753 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4754 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4755
4756 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4757 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4758 pipe_config->adjusted_mode.crtc_vtotal += 1;
4759 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4760 }
4761
4762 tmp = I915_READ(PIPESRC(crtc->pipe));
4763 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4764 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4765}
4766
babea61d
JB		 4767static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4768 struct intel_crtc_config *pipe_config)
4769{
4770 struct drm_crtc *crtc = &intel_crtc->base;
4771
4772 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4773 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4774 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4775 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4776
4777 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4778 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4779 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4780 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4781
4782 crtc->mode.flags = pipe_config->adjusted_mode.flags;
4783
4784 crtc->mode.clock = pipe_config->adjusted_mode.clock;
4785 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4786}
4787
84b046f3
DV		 4788static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4789{
4790 struct drm_device *dev = intel_crtc->base.dev;
4791 struct drm_i915_private *dev_priv = dev->dev_private;
4792 uint32_t pipeconf;
4793
9f11a9e4 4794 pipeconf = 0;
84b046f3
DV		 4795
4796 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4797 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4798 * core speed.
4799 *
4800 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4801 * pipe == 0 check?
4802 */
4803 if (intel_crtc->config.requested_mode.clock >
4804 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4805 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3
DV		 4806 }
4807
ff9ce46e
DV		 4808 /* only g4x and later have fancy bpc/dither controls */
4809 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e
DV		 4810 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4811 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4812 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4813 PIPECONF_DITHER_TYPE_SP;
84b046f3 4814
ff9ce46e
DV		 4815 switch (intel_crtc->config.pipe_bpp) {
4816 case 18:
4817 pipeconf |= PIPECONF_6BPC;
4818 break;
4819 case 24:
4820 pipeconf |= PIPECONF_8BPC;
4821 break;
4822 case 30:
4823 pipeconf |= PIPECONF_10BPC;
4824 break;
4825 default:
4826 /* Case prevented by intel_choose_pipe_bpp_dither. */
4827 BUG();
84b046f3
DV		 4828 }
4829 }
4830
4831 if (HAS_PIPE_CXSR(dev)) {
4832 if (intel_crtc->lowfreq_avail) {
4833 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4834 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4835 } else {
4836 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 4837 }
4838 }
4839
84b046f3
DV		 4840 if (!IS_GEN2(dev) &&
4841 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4842 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4843 else
4844 pipeconf |= PIPECONF_PROGRESSIVE;
4845
9f11a9e4
DV		 4846 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4847 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 4848
84b046f3
DV		 4849 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4850 POSTING_READ(PIPECONF(intel_crtc->pipe));
4851}
4852
f564048e 4853static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4854 int x, int y,
94352cf9 4855 struct drm_framebuffer *fb)
79e53945
JB		 4856{
4857 struct drm_device *dev = crtc->dev;
4858 struct drm_i915_private *dev_priv = dev->dev_private;
4859 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 4860 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4861 int pipe = intel_crtc->pipe;
80824003 4862 int plane = intel_crtc->plane;
c751ce4f 4863 int refclk, num_connectors = 0;
652c393a 4864 intel_clock_t clock, reduced_clock;
84b046f3 4865 u32 dspcntr;
a16af721
DV		 4866 bool ok, has_reduced_clock = false;
4867 bool is_lvds = false;
5eddb70b 4868 struct intel_encoder *encoder;
d4906093 4869 const intel_limit_t *limit;
5c3b82e2 4870 int ret;
79e53945 4871
6c2b7c12 4872 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4873 switch (encoder->type) {
79e53945
JB		 4874 case INTEL_OUTPUT_LVDS:
4875 is_lvds = true;
4876 break;
79e53945 4877 }
43565a06 4878
c751ce4f 4879 num_connectors++;
79e53945
JB		 4880 }
4881
c65d77d8 4882 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4883
d4906093
ML		 4884 /*
4885 * Returns a set of divisors for the desired target clock with the given
4886 * refclk, or FALSE. The returned values represent the clock equation:
4887 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4888 */
1b894b59 4889 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 4890 ok = dev_priv->display.find_dpll(limit, crtc,
4891 intel_crtc->config.port_clock,
ee9300bb
DV		 4892 refclk, NULL, &clock);
4893 if (!ok && !intel_crtc->config.clock_set) {
79e53945 4894 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4895 return -EINVAL;
79e53945
JB		 4896 }
4897
cda4b7d3 4898 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4899 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4900
ddc9003c 4901 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4902 /*
4903 * Ensure we match the reduced clock's P to the target clock.
4904 * If the clocks don't match, we can't switch the display clock
4905 * by using the FP0/FP1. In such case we will disable the LVDS
4906 * downclock feature.
4907 */
ee9300bb
DV		 4908 has_reduced_clock =
4909 dev_priv->display.find_dpll(limit, crtc,
5eddb70b 4910 dev_priv->lvds_downclock,
ee9300bb 4911 refclk, &clock,
5eddb70b 4912 &reduced_clock);
7026d4ac 4913 }
f47709a9
DV		 4914 /* Compat-code for transition, will disappear. */
4915 if (!intel_crtc->config.clock_set) {
4916 intel_crtc->config.dpll.n = clock.n;
4917 intel_crtc->config.dpll.m1 = clock.m1;
4918 intel_crtc->config.dpll.m2 = clock.m2;
4919 intel_crtc->config.dpll.p1 = clock.p1;
4920 intel_crtc->config.dpll.p2 = clock.p2;
4921 }
7026d4ac 4922
eb1cbe48 4923 if (IS_GEN2(dev))
8a654f3b 4924 i8xx_update_pll(intel_crtc,
2a8f64ca
VP		 4925 has_reduced_clock ? &reduced_clock : NULL,
4926 num_connectors);
a0c4da24 4927 else if (IS_VALLEYVIEW(dev))
f47709a9 4928 vlv_update_pll(intel_crtc);
79e53945 4929 else
f47709a9 4930 i9xx_update_pll(intel_crtc,
eb1cbe48 4931 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4932 num_connectors);
79e53945 4933
79e53945
JB		 4934 /* Set up the display plane register */
4935 dspcntr = DISPPLANE_GAMMA_ENABLE;
4936
da6ecc5d
JB		 4937 if (!IS_VALLEYVIEW(dev)) {
4938 if (pipe == 0)
4939 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4940 else
4941 dspcntr |= DISPPLANE_SEL_PIPE_B;
4942 }
79e53945 4943
8a654f3b 4944 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW		 4945
4946 /* pipesrc and dspsize control the size that is scaled from,
4947 * which should always be the user's requested size.
79e53945 4948 */
929c77fb
EA		 4949 I915_WRITE(DSPSIZE(plane),
4950 ((mode->vdisplay - 1) << 16) |
4951 (mode->hdisplay - 1));
4952 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4953
84b046f3
DV		 4954 i9xx_set_pipeconf(intel_crtc);
4955
f564048e
EA		 4956 I915_WRITE(DSPCNTR(plane), dspcntr);
4957 POSTING_READ(DSPCNTR(plane));
4958
94352cf9 4959 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4960
4961 intel_update_watermarks(dev);
4962
f564048e
EA		 4963 return ret;
4964}
4965
2fa2fe9a
DV		 4966static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4967 struct intel_crtc_config *pipe_config)
4968{
4969 struct drm_device *dev = crtc->base.dev;
4970 struct drm_i915_private *dev_priv = dev->dev_private;
4971 uint32_t tmp;
4972
4973 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 4974 if (!(tmp & PFIT_ENABLE))
4975 return;
2fa2fe9a 4976
06922821 4977 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 4978 if (INTEL_INFO(dev)->gen < 4) {
4979 if (crtc->pipe != PIPE_B)
4980 return;
2fa2fe9a
DV		 4981 } else {
4982 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4983 return;
4984 }
4985
06922821 4986 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 4987 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4988 if (INTEL_INFO(dev)->gen < 5)
4989 pipe_config->gmch_pfit.lvds_border_bits =
4990 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4991}
4992
0e8ffe1b
DV		 4993static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4994 struct intel_crtc_config *pipe_config)
4995{
4996 struct drm_device *dev = crtc->base.dev;
4997 struct drm_i915_private *dev_priv = dev->dev_private;
4998 uint32_t tmp;
4999
e143a21c 5000 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 5001 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5002
0e8ffe1b
DV		 5003 tmp = I915_READ(PIPECONF(crtc->pipe));
5004 if (!(tmp & PIPECONF_ENABLE))
5005 return false;
5006
1bd1bd80
DV		 5007 intel_get_pipe_timings(crtc, pipe_config);
5008
2fa2fe9a
DV		 5009 i9xx_get_pfit_config(crtc, pipe_config);
5010
6c49f241
DV		 5011 if (INTEL_INFO(dev)->gen >= 4) {
5012 tmp = I915_READ(DPLL_MD(crtc->pipe));
5013 pipe_config->pixel_multiplier =
5014 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5015 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 5016 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 5017 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5018 tmp = I915_READ(DPLL(crtc->pipe));
5019 pipe_config->pixel_multiplier =
5020 ((tmp & SDVO_MULTIPLIER_MASK)
5021 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5022 } else {
5023 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5024 * port and will be fixed up in the encoder->get_config
5025 * function. */
5026 pipe_config->pixel_multiplier = 1;
5027 }
8bcc2795
DV		 5028 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5029 if (!IS_VALLEYVIEW(dev)) {
5030 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5031 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 5032 } else {
5033 /* Mask out read-only status bits. */
5034 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5035 DPLL_PORTC_READY_MASK |
5036 DPLL_PORTB_READY_MASK);
8bcc2795 5037 }
6c49f241 5038
0e8ffe1b
DV		 5039 return true;
5040}
5041
dde86e2d 5042static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5043{
5044 struct drm_i915_private *dev_priv = dev->dev_private;
5045 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5046 struct intel_encoder *encoder;
74cfd7ac 5047 u32 val, final;
13d83a67 5048 bool has_lvds = false;
199e5d79 5049 bool has_cpu_edp = false;
199e5d79 5050 bool has_panel = false;
99eb6a01
KP		 5051 bool has_ck505 = false;
5052 bool can_ssc = false;
13d83a67
JB		 5053
5054 /* We need to take the global config into account */
199e5d79
KP		 5055 list_for_each_entry(encoder, &mode_config->encoder_list,
5056 base.head) {
5057 switch (encoder->type) {
5058 case INTEL_OUTPUT_LVDS:
5059 has_panel = true;
5060 has_lvds = true;
5061 break;
5062 case INTEL_OUTPUT_EDP:
5063 has_panel = true;
2de6905f 5064 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5065 has_cpu_edp = true;
5066 break;
13d83a67
JB		 5067 }
5068 }
5069
99eb6a01 5070 if (HAS_PCH_IBX(dev)) {
41aa3448 5071 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5072 can_ssc = has_ck505;
5073 } else {
5074 has_ck505 = false;
5075 can_ssc = true;
5076 }
5077
2de6905f
ID		 5078 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5079 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5080
5081 /* Ironlake: try to setup display ref clock before DPLL
5082 * enabling. This is only under driver's control after
5083 * PCH B stepping, previous chipset stepping should be
5084 * ignoring this setting.
5085 */
74cfd7ac
CW		 5086 val = I915_READ(PCH_DREF_CONTROL);
5087
5088 /* As we must carefully and slowly disable/enable each source in turn,
5089 * compute the final state we want first and check if we need to
5090 * make any changes at all.
5091 */
5092 final = val;
5093 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5094 if (has_ck505)
5095 final |= DREF_NONSPREAD_CK505_ENABLE;
5096 else
5097 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5098
5099 final &= ~DREF_SSC_SOURCE_MASK;
5100 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5101 final &= ~DREF_SSC1_ENABLE;
5102
5103 if (has_panel) {
5104 final |= DREF_SSC_SOURCE_ENABLE;
5105
5106 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5107 final |= DREF_SSC1_ENABLE;
5108
5109 if (has_cpu_edp) {
5110 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5111 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5112 else
5113 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5114 } else
5115 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5116 } else {
5117 final |= DREF_SSC_SOURCE_DISABLE;
5118 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5119 }
5120
5121 if (final == val)
5122 return;
5123
13d83a67 5124 /* Always enable nonspread source */
74cfd7ac 5125 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5126
99eb6a01 5127 if (has_ck505)
74cfd7ac 5128 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5129 else
74cfd7ac 5130 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5131
199e5d79 5132 if (has_panel) {
74cfd7ac
CW		 5133 val &= ~DREF_SSC_SOURCE_MASK;
5134 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5135
199e5d79 5136 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5137 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5138 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5139 val |= DREF_SSC1_ENABLE;
e77166b5 5140 } else
74cfd7ac 5141 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5142
5143 /* Get SSC going before enabling the outputs */
74cfd7ac 5144 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5145 POSTING_READ(PCH_DREF_CONTROL);
5146 udelay(200);
5147
74cfd7ac 5148 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5149
5150 /* Enable CPU source on CPU attached eDP */
199e5d79 5151 if (has_cpu_edp) {
99eb6a01 5152 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5153 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5154 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5155 }
13d83a67 5156 else
74cfd7ac 5157 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5158 } else
74cfd7ac 5159 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5160
74cfd7ac 5161 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5162 POSTING_READ(PCH_DREF_CONTROL);
5163 udelay(200);
5164 } else {
5165 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5166
74cfd7ac 5167 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5168
5169 /* Turn off CPU output */
74cfd7ac 5170 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5171
74cfd7ac 5172 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5173 POSTING_READ(PCH_DREF_CONTROL);
5174 udelay(200);
5175
5176 /* Turn off the SSC source */
74cfd7ac
CW		 5177 val &= ~DREF_SSC_SOURCE_MASK;
5178 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5179
5180 /* Turn off SSC1 */
74cfd7ac 5181 val &= ~DREF_SSC1_ENABLE;
199e5d79 5182
74cfd7ac 5183 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5184 POSTING_READ(PCH_DREF_CONTROL);
5185 udelay(200);
5186 }
74cfd7ac
CW		 5187
5188 BUG_ON(val != final);
13d83a67
JB		 5189}
5190
f31f2d55 5191static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 5192{
f31f2d55 5193 uint32_t tmp;
dde86e2d 5194
0ff066a9
PZ		 5195 tmp = I915_READ(SOUTH_CHICKEN2);
5196 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5197 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5198
0ff066a9
PZ		 5199 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5200 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5201 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 5202
0ff066a9
PZ		 5203 tmp = I915_READ(SOUTH_CHICKEN2);
5204 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5205 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5206
0ff066a9
PZ		 5207 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5208 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5209 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 5210}
5211
5212/* WaMPhyProgramming:hsw */
5213static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5214{
5215 uint32_t tmp;
dde86e2d
PZ		 5216
5217 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5218 tmp &= ~(0xFF << 24);
5219 tmp |= (0x12 << 24);
5220 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5221
dde86e2d
PZ		 5222 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5223 tmp |= (1 << 11);
5224 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5225
5226 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5227 tmp |= (1 << 11);
5228 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5229
dde86e2d
PZ		 5230 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5231 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5232 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5233
5234 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5235 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5236 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5237
0ff066a9
PZ		 5238 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5239 tmp &= ~(7 << 13);
5240 tmp |= (5 << 13);
5241 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 5242
0ff066a9
PZ		 5243 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5244 tmp &= ~(7 << 13);
5245 tmp |= (5 << 13);
5246 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 5247
5248 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5249 tmp &= ~0xFF;
5250 tmp |= 0x1C;
5251 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5252
5253 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5254 tmp &= ~0xFF;
5255 tmp |= 0x1C;
5256 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5257
5258 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5259 tmp &= ~(0xFF << 16);
5260 tmp |= (0x1C << 16);
5261 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5262
5263 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5264 tmp &= ~(0xFF << 16);
5265 tmp |= (0x1C << 16);
5266 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5267
0ff066a9
PZ		 5268 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5269 tmp |= (1 << 27);
5270 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 5271
0ff066a9
PZ		 5272 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5273 tmp |= (1 << 27);
5274 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 5275
0ff066a9
PZ		 5276 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5277 tmp &= ~(0xF << 28);
5278 tmp |= (4 << 28);
5279 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 5280
0ff066a9
PZ		 5281 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5282 tmp &= ~(0xF << 28);
5283 tmp |= (4 << 28);
5284 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 5285}
5286
2fa86a1f
PZ		 5287/* Implements 3 different sequences from BSpec chapter "Display iCLK
5288 * Programming" based on the parameters passed:
5289 * - Sequence to enable CLKOUT_DP
5290 * - Sequence to enable CLKOUT_DP without spread
5291 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5292 */
5293static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5294 bool with_fdi)
f31f2d55
PZ		 5295{
5296 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 5297 uint32_t reg, tmp;
5298
5299 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5300 with_spread = true;
5301 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5302 with_fdi, "LP PCH doesn't have FDI\n"))
5303 with_fdi = false;
f31f2d55
PZ		 5304
5305 mutex_lock(&dev_priv->dpio_lock);
5306
5307 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5308 tmp &= ~SBI_SSCCTL_DISABLE;
5309 tmp |= SBI_SSCCTL_PATHALT;
5310 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5311
5312 udelay(24);
5313
2fa86a1f
PZ		 5314 if (with_spread) {
5315 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5316 tmp &= ~SBI_SSCCTL_PATHALT;
5317 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 5318
2fa86a1f
PZ		 5319 if (with_fdi) {
5320 lpt_reset_fdi_mphy(dev_priv);
5321 lpt_program_fdi_mphy(dev_priv);
5322 }
5323 }
dde86e2d 5324
2fa86a1f
PZ		 5325 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5326 SBI_GEN0 : SBI_DBUFF0;
5327 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5328 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5329 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
DV		 5330
5331 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5332}
5333
47701c3b
PZ		 5334/* Sequence to disable CLKOUT_DP */
5335static void lpt_disable_clkout_dp(struct drm_device *dev)
5336{
5337 struct drm_i915_private *dev_priv = dev->dev_private;
5338 uint32_t reg, tmp;
5339
5340 mutex_lock(&dev_priv->dpio_lock);
5341
5342 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5343 SBI_GEN0 : SBI_DBUFF0;
5344 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5345 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5346 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5347
5348 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5349 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5350 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5351 tmp |= SBI_SSCCTL_PATHALT;
5352 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5353 udelay(32);
5354 }
5355 tmp |= SBI_SSCCTL_DISABLE;
5356 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5357 }
5358
5359 mutex_unlock(&dev_priv->dpio_lock);
5360}
5361
bf8fa3d3
PZ		 5362static void lpt_init_pch_refclk(struct drm_device *dev)
5363{
5364 struct drm_mode_config *mode_config = &dev->mode_config;
5365 struct intel_encoder *encoder;
5366 bool has_vga = false;
5367
5368 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5369 switch (encoder->type) {
5370 case INTEL_OUTPUT_ANALOG:
5371 has_vga = true;
5372 break;
5373 }
5374 }
5375
47701c3b
PZ		 5376 if (has_vga)
5377 lpt_enable_clkout_dp(dev, true, true);
5378 else
5379 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 5380}
5381
dde86e2d
PZ		 5382/*
5383 * Initialize reference clocks when the driver loads
5384 */
5385void intel_init_pch_refclk(struct drm_device *dev)
5386{
5387 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5388 ironlake_init_pch_refclk(dev);
5389 else if (HAS_PCH_LPT(dev))
5390 lpt_init_pch_refclk(dev);
5391}
5392
d9d444cb
JB		 5393static int ironlake_get_refclk(struct drm_crtc *crtc)
5394{
5395 struct drm_device *dev = crtc->dev;
5396 struct drm_i915_private *dev_priv = dev->dev_private;
5397 struct intel_encoder *encoder;
d9d444cb
JB		 5398 int num_connectors = 0;
5399 bool is_lvds = false;
5400
6c2b7c12 5401 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5402 switch (encoder->type) {
5403 case INTEL_OUTPUT_LVDS:
5404 is_lvds = true;
5405 break;
d9d444cb
JB		 5406 }
5407 num_connectors++;
5408 }
5409
5410 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5411 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5412 dev_priv->vbt.lvds_ssc_freq);
5413 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5414 }
5415
5416 return 120000;
5417}
5418
6ff93609 5419static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5420{
c8203565 5421 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5422 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5423 int pipe = intel_crtc->pipe;
c8203565
PZ		 5424 uint32_t val;
5425
78114071 5426 val = 0;
c8203565 5427
965e0c48 5428 switch (intel_crtc->config.pipe_bpp) {
c8203565 5429 case 18:
dfd07d72 5430 val |= PIPECONF_6BPC;
c8203565
PZ		 5431 break;
5432 case 24:
dfd07d72 5433 val |= PIPECONF_8BPC;
c8203565
PZ		 5434 break;
5435 case 30:
dfd07d72 5436 val |= PIPECONF_10BPC;
c8203565
PZ		 5437 break;
5438 case 36:
dfd07d72 5439 val |= PIPECONF_12BPC;
c8203565
PZ		 5440 break;
5441 default:
cc769b62
PZ		 5442 /* Case prevented by intel_choose_pipe_bpp_dither. */
5443 BUG();
c8203565
PZ		 5444 }
5445
d8b32247 5446 if (intel_crtc->config.dither)
c8203565
PZ		 5447 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5448
6ff93609 5449 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5450 val |= PIPECONF_INTERLACED_ILK;
5451 else
5452 val |= PIPECONF_PROGRESSIVE;
5453
50f3b016 5454 if (intel_crtc->config.limited_color_range)
3685a8f3 5455 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 5456
c8203565
PZ		 5457 I915_WRITE(PIPECONF(pipe), val);
5458 POSTING_READ(PIPECONF(pipe));
5459}
5460
86d3efce
VS		 5461/*
5462 * Set up the pipe CSC unit.
5463 *
5464 * Currently only full range RGB to limited range RGB conversion
5465 * is supported, but eventually this should handle various
5466 * RGB<->YCbCr scenarios as well.
5467 */
50f3b016 5468static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5469{
5470 struct drm_device *dev = crtc->dev;
5471 struct drm_i915_private *dev_priv = dev->dev_private;
5472 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5473 int pipe = intel_crtc->pipe;
5474 uint16_t coeff = 0x7800; /* 1.0 */
5475
5476 /*
5477 * TODO: Check what kind of values actually come out of the pipe
5478 * with these coeff/postoff values and adjust to get the best
5479 * accuracy. Perhaps we even need to take the bpc value into
5480 * consideration.
5481 */
5482
50f3b016 5483 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5484 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5485
5486 /*
5487 * GY/GU and RY/RU should be the other way around according
5488 * to BSpec, but reality doesn't agree. Just set them up in
5489 * a way that results in the correct picture.
5490 */
5491 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5492 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5493
5494 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5495 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5496
5497 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5498 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5499
5500 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5501 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5502 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5503
5504 if (INTEL_INFO(dev)->gen > 6) {
5505 uint16_t postoff = 0;
5506
50f3b016 5507 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5508 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5509
5510 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5511 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5512 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5513
5514 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5515 } else {
5516 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5517
50f3b016 5518 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5519 mode |= CSC_BLACK_SCREEN_OFFSET;
5520
5521 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5522 }
5523}
5524
6ff93609 5525static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5526{
5527 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5528 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5529 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5530 uint32_t val;
5531
3eff4faa 5532 val = 0;
ee2b0b38 5533
d8b32247 5534 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5535 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5536
6ff93609 5537 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5538 val |= PIPECONF_INTERLACED_ILK;
5539 else
5540 val |= PIPECONF_PROGRESSIVE;
5541
702e7a56
PZ		 5542 I915_WRITE(PIPECONF(cpu_transcoder), val);
5543 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 5544
5545 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5546 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
ee2b0b38
PZ		 5547}
5548
6591c6e4 5549static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ		 5550 intel_clock_t *clock,
5551 bool *has_reduced_clock,
5552 intel_clock_t *reduced_clock)
5553{
5554 struct drm_device *dev = crtc->dev;
5555 struct drm_i915_private *dev_priv = dev->dev_private;
5556 struct intel_encoder *intel_encoder;
5557 int refclk;
d4906093 5558 const intel_limit_t *limit;
a16af721 5559 bool ret, is_lvds = false;
79e53945 5560
6591c6e4
PZ		 5561 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5562 switch (intel_encoder->type) {
79e53945
JB		 5563 case INTEL_OUTPUT_LVDS:
5564 is_lvds = true;
5565 break;
79e53945
JB		 5566 }
5567 }
5568
d9d444cb 5569 refclk = ironlake_get_refclk(crtc);
79e53945 5570
d4906093
ML		 5571 /*
5572 * Returns a set of divisors for the desired target clock with the given
5573 * refclk, or FALSE. The returned values represent the clock equation:
5574 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5575 */
1b894b59 5576 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 5577 ret = dev_priv->display.find_dpll(limit, crtc,
5578 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 5579 refclk, NULL, clock);
6591c6e4
PZ		 5580 if (!ret)
5581 return false;
cda4b7d3 5582
ddc9003c 5583 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5584 /*
5585 * Ensure we match the reduced clock's P to the target clock.
5586 * If the clocks don't match, we can't switch the display clock
5587 * by using the FP0/FP1. In such case we will disable the LVDS
5588 * downclock feature.
5589 */
ee9300bb
DV		 5590 *has_reduced_clock =
5591 dev_priv->display.find_dpll(limit, crtc,
5592 dev_priv->lvds_downclock,
5593 refclk, clock,
5594 reduced_clock);
652c393a 5595 }
61e9653f 5596
6591c6e4
PZ		 5597 return true;
5598}
5599
01a415fd
DV		 5600static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5601{
5602 struct drm_i915_private *dev_priv = dev->dev_private;
5603 uint32_t temp;
5604
5605 temp = I915_READ(SOUTH_CHICKEN1);
5606 if (temp & FDI_BC_BIFURCATION_SELECT)
5607 return;
5608
5609 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5610 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5611
5612 temp |= FDI_BC_BIFURCATION_SELECT;
5613 DRM_DEBUG_KMS("enabling fdi C rx\n");
5614 I915_WRITE(SOUTH_CHICKEN1, temp);
5615 POSTING_READ(SOUTH_CHICKEN1);
5616}
5617
ebfd86fd 5618static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
01a415fd
DV		 5619{
5620 struct drm_device *dev = intel_crtc->base.dev;
5621 struct drm_i915_private *dev_priv = dev->dev_private;
01a415fd
DV		 5622
5623 switch (intel_crtc->pipe) {
5624 case PIPE_A:
ebfd86fd 5625 break;
01a415fd 5626 case PIPE_B:
ebfd86fd 5627 if (intel_crtc->config.fdi_lanes > 2)
01a415fd
DV		 5628 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5629 else
5630 cpt_enable_fdi_bc_bifurcation(dev);
5631
ebfd86fd 5632 break;
01a415fd 5633 case PIPE_C:
01a415fd
DV		 5634 cpt_enable_fdi_bc_bifurcation(dev);
5635
ebfd86fd 5636 break;
01a415fd
DV		 5637 default:
5638 BUG();
5639 }
5640}
5641
d4b1931c
PZ		 5642int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5643{
5644 /*
5645 * Account for spread spectrum to avoid
5646 * oversubscribing the link. Max center spread
5647 * is 2.5%; use 5% for safety's sake.
5648 */
5649 u32 bps = target_clock * bpp * 21 / 20;
5650 return bps / (link_bw * 8) + 1;
5651}
5652
7429e9d4 5653static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 5654{
7429e9d4 5655 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 5656}
5657
de13a2e3 5658static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5659 u32 *fp,
9a7c7890 5660 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5661{
de13a2e3 5662 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5663 struct drm_device *dev = crtc->dev;
5664 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5665 struct intel_encoder *intel_encoder;
5666 uint32_t dpll;
6cc5f341 5667 int factor, num_connectors = 0;
09ede541 5668 bool is_lvds = false, is_sdvo = false;
79e53945 5669
de13a2e3
PZ		 5670 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5671 switch (intel_encoder->type) {
79e53945
JB		 5672 case INTEL_OUTPUT_LVDS:
5673 is_lvds = true;
5674 break;
5675 case INTEL_OUTPUT_SDVO:
7d57382e 5676 case INTEL_OUTPUT_HDMI:
79e53945 5677 is_sdvo = true;
79e53945 5678 break;
79e53945 5679 }
43565a06 5680
c751ce4f 5681 num_connectors++;
79e53945 5682 }
79e53945 5683
c1858123 5684 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5685 factor = 21;
5686 if (is_lvds) {
5687 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5688 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5689 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5690 factor = 25;
09ede541 5691 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5692 factor = 20;
c1858123 5693
7429e9d4 5694 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5695 *fp |= FP_CB_TUNE;
2c07245f 5696
9a7c7890
DV		 5697 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5698 *fp2 |= FP_CB_TUNE;
5699
5eddb70b 5700 dpll = 0;
2c07245f 5701
a07d6787
EA		 5702 if (is_lvds)
5703 dpll |= DPLLB_MODE_LVDS;
5704 else
5705 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 5706
ef1b460d
DV		 5707 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5708 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 5709
5710 if (is_sdvo)
4a33e48d 5711 dpll |= DPLL_SDVO_HIGH_SPEED;
9566e9af 5712 if (intel_crtc->config.has_dp_encoder)
4a33e48d 5713 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 5714
a07d6787 5715 /* compute bitmask from p1 value */
7429e9d4 5716 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5717 /* also FPA1 */
7429e9d4 5718 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5719
7429e9d4 5720 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5721 case 5:
5722 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5723 break;
5724 case 7:
5725 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5726 break;
5727 case 10:
5728 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5729 break;
5730 case 14:
5731 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5732 break;
79e53945
JB		 5733 }
5734
b4c09f3b 5735 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5736 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5737 else
5738 dpll |= PLL_REF_INPUT_DREFCLK;
5739
959e16d6 5740 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 5741}
5742
5743static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5744 int x, int y,
5745 struct drm_framebuffer *fb)
5746{
5747 struct drm_device *dev = crtc->dev;
5748 struct drm_i915_private *dev_priv = dev->dev_private;
5749 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5750 int pipe = intel_crtc->pipe;
5751 int plane = intel_crtc->plane;
5752 int num_connectors = 0;
5753 intel_clock_t clock, reduced_clock;
cbbab5bd 5754 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5755 bool ok, has_reduced_clock = false;
8b47047b 5756 bool is_lvds = false;
de13a2e3 5757 struct intel_encoder *encoder;
e2b78267 5758 struct intel_shared_dpll *pll;
de13a2e3 5759 int ret;
de13a2e3
PZ		 5760
5761 for_each_encoder_on_crtc(dev, crtc, encoder) {
5762 switch (encoder->type) {
5763 case INTEL_OUTPUT_LVDS:
5764 is_lvds = true;
5765 break;
de13a2e3
PZ		 5766 }
5767
5768 num_connectors++;
a07d6787 5769 }
79e53945 5770
5dc5298b
PZ		 5771 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5772 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5773
ff9a6750 5774 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 5775 &has_reduced_clock, &reduced_clock);
ee9300bb 5776 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 5777 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5778 return -EINVAL;
79e53945 5779 }
f47709a9
DV		 5780 /* Compat-code for transition, will disappear. */
5781 if (!intel_crtc->config.clock_set) {
5782 intel_crtc->config.dpll.n = clock.n;
5783 intel_crtc->config.dpll.m1 = clock.m1;
5784 intel_crtc->config.dpll.m2 = clock.m2;
5785 intel_crtc->config.dpll.p1 = clock.p1;
5786 intel_crtc->config.dpll.p2 = clock.p2;
5787 }
79e53945 5788
de13a2e3
PZ		 5789 /* Ensure that the cursor is valid for the new mode before changing... */
5790 intel_crtc_update_cursor(crtc, true);
5791
5dc5298b 5792 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5793 if (intel_crtc->config.has_pch_encoder) {
7429e9d4 5794 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5795 if (has_reduced_clock)
7429e9d4 5796 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5797
7429e9d4 5798 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5799 &fp, &reduced_clock,
5800 has_reduced_clock ? &fp2 : NULL);
5801
959e16d6 5802 intel_crtc->config.dpll_hw_state.dpll = dpll;
66e985c0
DV		 5803 intel_crtc->config.dpll_hw_state.fp0 = fp;
5804 if (has_reduced_clock)
5805 intel_crtc->config.dpll_hw_state.fp1 = fp2;
5806 else
5807 intel_crtc->config.dpll_hw_state.fp1 = fp;
5808
b89a1d39 5809 pll = intel_get_shared_dpll(intel_crtc);
ee7b9f93 5810 if (pll == NULL) {
84f44ce7
VS		 5811 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5812 pipe_name(pipe));
4b645f14
JB		 5813 return -EINVAL;
5814 }
ee7b9f93 5815 } else
e72f9fbf 5816 intel_put_shared_dpll(intel_crtc);
79e53945 5817
03afc4a2
DV		 5818 if (intel_crtc->config.has_dp_encoder)
5819 intel_dp_set_m_n(intel_crtc);
79e53945 5820
bcd644e0
DV		 5821 if (is_lvds && has_reduced_clock && i915_powersave)
5822 intel_crtc->lowfreq_avail = true;
5823 else
5824 intel_crtc->lowfreq_avail = false;
e2b78267
DV		 5825
5826 if (intel_crtc->config.has_pch_encoder) {
5827 pll = intel_crtc_to_shared_dpll(intel_crtc);
5828
652c393a
JB		 5829 }
5830
8a654f3b 5831 intel_set_pipe_timings(intel_crtc);
5eddb70b 5832
ca3a0ff8 5833 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5834 intel_cpu_transcoder_set_m_n(intel_crtc,
5835 &intel_crtc->config.fdi_m_n);
5836 }
2c07245f 5837
ebfd86fd
DV		 5838 if (IS_IVYBRIDGE(dev))
5839 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
79e53945 5840
6ff93609 5841 ironlake_set_pipeconf(crtc);
79e53945 5842
a1f9e77e
PZ		 5843 /* Set up the display plane register */
5844 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5845 POSTING_READ(DSPCNTR(plane));
79e53945 5846
94352cf9 5847 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5848
5849 intel_update_watermarks(dev);
5850
1857e1da 5851 return ret;
79e53945
JB		 5852}
5853
72419203
DV		 5854static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5855 struct intel_crtc_config *pipe_config)
5856{
5857 struct drm_device *dev = crtc->base.dev;
5858 struct drm_i915_private *dev_priv = dev->dev_private;
5859 enum transcoder transcoder = pipe_config->cpu_transcoder;
5860
5861 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5862 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5863 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5864 & ~TU_SIZE_MASK;
5865 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5866 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5867 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5868}
5869
2fa2fe9a
DV		 5870static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5871 struct intel_crtc_config *pipe_config)
5872{
5873 struct drm_device *dev = crtc->base.dev;
5874 struct drm_i915_private *dev_priv = dev->dev_private;
5875 uint32_t tmp;
5876
5877 tmp = I915_READ(PF_CTL(crtc->pipe));
5878
5879 if (tmp & PF_ENABLE) {
5880 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5881 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 5882
5883 /* We currently do not free assignements of panel fitters on
5884 * ivb/hsw (since we don't use the higher upscaling modes which
5885 * differentiates them) so just WARN about this case for now. */
5886 if (IS_GEN7(dev)) {
5887 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5888 PF_PIPE_SEL_IVB(crtc->pipe));
5889 }
2fa2fe9a 5890 }
79e53945
JB		 5891}
5892
0e8ffe1b
DV		 5893static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5894 struct intel_crtc_config *pipe_config)
5895{
5896 struct drm_device *dev = crtc->base.dev;
5897 struct drm_i915_private *dev_priv = dev->dev_private;
5898 uint32_t tmp;
5899
e143a21c 5900 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 5901 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5902
0e8ffe1b
DV		 5903 tmp = I915_READ(PIPECONF(crtc->pipe));
5904 if (!(tmp & PIPECONF_ENABLE))
5905 return false;
5906
ab9412ba 5907 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 5908 struct intel_shared_dpll *pll;
5909
88adfff1
DV		 5910 pipe_config->has_pch_encoder = true;
5911
627eb5a3
DV		 5912 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5913 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5914 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5915
5916 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 5917
c0d43d62 5918 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 5919 pipe_config->shared_dpll =
5920 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 5921 } else {
5922 tmp = I915_READ(PCH_DPLL_SEL);
5923 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5924 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5925 else
5926 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5927 }
66e985c0
DV		 5928
5929 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
5930
5931 WARN_ON(!pll->get_hw_state(dev_priv, pll,
5932 &pipe_config->dpll_hw_state));
c93f54cf
DV		 5933
5934 tmp = pipe_config->dpll_hw_state.dpll;
5935 pipe_config->pixel_multiplier =
5936 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
5937 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6c49f241
DV		 5938 } else {
5939 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 5940 }
5941
1bd1bd80
DV		 5942 intel_get_pipe_timings(crtc, pipe_config);
5943
2fa2fe9a
DV		 5944 ironlake_get_pfit_config(crtc, pipe_config);
5945
0e8ffe1b
DV		 5946 return true;
5947}
5948
be256dc7
PZ		 5949static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
5950{
5951 struct drm_device *dev = dev_priv->dev;
5952 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
5953 struct intel_crtc *crtc;
5954 unsigned long irqflags;
5955 uint32_t val, pch_hpd_mask;
5956
5957 pch_hpd_mask = SDE_PORTB_HOTPLUG_CPT | SDE_PORTC_HOTPLUG_CPT;
5958 if (!(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE))
5959 pch_hpd_mask |= SDE_PORTD_HOTPLUG_CPT | SDE_CRT_HOTPLUG_CPT;
5960
5961 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
5962 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
5963 pipe_name(crtc->pipe));
5964
5965 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
5966 WARN(plls->spll_refcount, "SPLL enabled\n");
5967 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
5968 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
5969 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
5970 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
5971 "CPU PWM1 enabled\n");
5972 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
5973 "CPU PWM2 enabled\n");
5974 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
5975 "PCH PWM1 enabled\n");
5976 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
5977 "Utility pin enabled\n");
5978 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
5979
5980 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5981 val = I915_READ(DEIMR);
5982 WARN((val & ~DE_PCH_EVENT_IVB) != val,
5983 "Unexpected DEIMR bits enabled: 0x%x\n", val);
5984 val = I915_READ(SDEIMR);
5985 WARN((val & ~pch_hpd_mask) != val,
5986 "Unexpected SDEIMR bits enabled: 0x%x\n", val);
5987 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
5988}
5989
5990/*
5991 * This function implements pieces of two sequences from BSpec:
5992 * - Sequence for display software to disable LCPLL
5993 * - Sequence for display software to allow package C8+
5994 * The steps implemented here are just the steps that actually touch the LCPLL
5995 * register. Callers should take care of disabling all the display engine
5996 * functions, doing the mode unset, fixing interrupts, etc.
5997 */
5998void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
5999 bool switch_to_fclk, bool allow_power_down)
6000{
6001 uint32_t val;
6002
6003 assert_can_disable_lcpll(dev_priv);
6004
6005 val = I915_READ(LCPLL_CTL);
6006
6007 if (switch_to_fclk) {
6008 val |= LCPLL_CD_SOURCE_FCLK;
6009 I915_WRITE(LCPLL_CTL, val);
6010
6011 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6012 LCPLL_CD_SOURCE_FCLK_DONE, 1))
6013 DRM_ERROR("Switching to FCLK failed\n");
6014
6015 val = I915_READ(LCPLL_CTL);
6016 }
6017
6018 val |= LCPLL_PLL_DISABLE;
6019 I915_WRITE(LCPLL_CTL, val);
6020 POSTING_READ(LCPLL_CTL);
6021
6022 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6023 DRM_ERROR("LCPLL still locked\n");
6024
6025 val = I915_READ(D_COMP);
6026 val |= D_COMP_COMP_DISABLE;
6027 I915_WRITE(D_COMP, val);
6028 POSTING_READ(D_COMP);
6029 ndelay(100);
6030
6031 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6032 DRM_ERROR("D_COMP RCOMP still in progress\n");
6033
6034 if (allow_power_down) {
6035 val = I915_READ(LCPLL_CTL);
6036 val |= LCPLL_POWER_DOWN_ALLOW;
6037 I915_WRITE(LCPLL_CTL, val);
6038 POSTING_READ(LCPLL_CTL);
6039 }
6040}
6041
6042/*
6043 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6044 * source.
6045 */
6046void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6047{
6048 uint32_t val;
6049
6050 val = I915_READ(LCPLL_CTL);
6051
6052 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6053 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6054 return;
6055
6056 if (val & LCPLL_POWER_DOWN_ALLOW) {
6057 val &= ~LCPLL_POWER_DOWN_ALLOW;
6058 I915_WRITE(LCPLL_CTL, val);
6059 }
6060
6061 val = I915_READ(D_COMP);
6062 val |= D_COMP_COMP_FORCE;
6063 val &= ~D_COMP_COMP_DISABLE;
6064 I915_WRITE(D_COMP, val);
6065 I915_READ(D_COMP);
6066
6067 val = I915_READ(LCPLL_CTL);
6068 val &= ~LCPLL_PLL_DISABLE;
6069 I915_WRITE(LCPLL_CTL, val);
6070
6071 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6072 DRM_ERROR("LCPLL not locked yet\n");
6073
6074 if (val & LCPLL_CD_SOURCE_FCLK) {
6075 val = I915_READ(LCPLL_CTL);
6076 val &= ~LCPLL_CD_SOURCE_FCLK;
6077 I915_WRITE(LCPLL_CTL, val);
6078
6079 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6080 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6081 DRM_ERROR("Switching back to LCPLL failed\n");
6082 }
6083}
6084
d6dd9eb1
DV		 6085static void haswell_modeset_global_resources(struct drm_device *dev)
6086{
d6dd9eb1
DV		 6087 bool enable = false;
6088 struct intel_crtc *crtc;
d6dd9eb1
DV		 6089
6090 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 6091 if (!crtc->base.enabled)
6092 continue;
d6dd9eb1 6093
e7a639c4
DV		 6094 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
6095 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 6096 enable = true;
6097 }
6098
d6dd9eb1
DV		 6099 intel_set_power_well(dev, enable);
6100}
6101
09b4ddf9 6102static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 6103 int x, int y,
6104 struct drm_framebuffer *fb)
6105{
6106 struct drm_device *dev = crtc->dev;
6107 struct drm_i915_private *dev_priv = dev->dev_private;
6108 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 6109 int plane = intel_crtc->plane;
09b4ddf9 6110 int ret;
09b4ddf9 6111
ff9a6750 6112 if (!intel_ddi_pll_mode_set(crtc))
6441ab5f
PZ		 6113 return -EINVAL;
6114
09b4ddf9
PZ		 6115 /* Ensure that the cursor is valid for the new mode before changing... */
6116 intel_crtc_update_cursor(crtc, true);
6117
03afc4a2
DV		 6118 if (intel_crtc->config.has_dp_encoder)
6119 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 6120
6121 intel_crtc->lowfreq_avail = false;
09b4ddf9 6122
8a654f3b 6123 intel_set_pipe_timings(intel_crtc);
09b4ddf9 6124
ca3a0ff8 6125 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 6126 intel_cpu_transcoder_set_m_n(intel_crtc,
6127 &intel_crtc->config.fdi_m_n);
6128 }
09b4ddf9 6129
6ff93609 6130 haswell_set_pipeconf(crtc);
09b4ddf9 6131
50f3b016 6132 intel_set_pipe_csc(crtc);
86d3efce 6133
09b4ddf9 6134 /* Set up the display plane register */
86d3efce 6135 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 6136 POSTING_READ(DSPCNTR(plane));
6137
6138 ret = intel_pipe_set_base(crtc, x, y, fb);
6139
6140 intel_update_watermarks(dev);
6141
1f803ee5 6142 return ret;
79e53945
JB		 6143}
6144
0e8ffe1b
DV		 6145static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6146 struct intel_crtc_config *pipe_config)
6147{
6148 struct drm_device *dev = crtc->base.dev;
6149 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 6150 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 6151 uint32_t tmp;
6152
e143a21c 6153 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 6154 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6155
eccb140b
DV		 6156 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6157 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6158 enum pipe trans_edp_pipe;
6159 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6160 default:
6161 WARN(1, "unknown pipe linked to edp transcoder\n");
6162 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6163 case TRANS_DDI_EDP_INPUT_A_ON:
6164 trans_edp_pipe = PIPE_A;
6165 break;
6166 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6167 trans_edp_pipe = PIPE_B;
6168 break;
6169 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6170 trans_edp_pipe = PIPE_C;
6171 break;
6172 }
6173
6174 if (trans_edp_pipe == crtc->pipe)
6175 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6176 }
6177
b97186f0 6178 if (!intel_display_power_enabled(dev,
eccb140b 6179 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 6180 return false;
6181
eccb140b 6182 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 6183 if (!(tmp & PIPECONF_ENABLE))
6184 return false;
6185
88adfff1 6186 /*
f196e6be 6187 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 6188 * DDI E. So just check whether this pipe is wired to DDI E and whether
6189 * the PCH transcoder is on.
6190 */
eccb140b 6191 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 6192 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 6193 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 6194 pipe_config->has_pch_encoder = true;
6195
627eb5a3
DV		 6196 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6197 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6198 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6199
6200 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 6201 }
6202
1bd1bd80
DV		 6203 intel_get_pipe_timings(crtc, pipe_config);
6204
2fa2fe9a
DV		 6205 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6206 if (intel_display_power_enabled(dev, pfit_domain))
6207 ironlake_get_pfit_config(crtc, pipe_config);
88adfff1 6208
42db64ef
PZ		 6209 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6210 (I915_READ(IPS_CTL) & IPS_ENABLE);
6211
6c49f241
DV		 6212 pipe_config->pixel_multiplier = 1;
6213
0e8ffe1b
DV		 6214 return true;
6215}
6216
f564048e 6217static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6218 int x, int y,
94352cf9 6219 struct drm_framebuffer *fb)
f564048e
EA		 6220{
6221 struct drm_device *dev = crtc->dev;
6222 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 6223 struct drm_encoder_helper_funcs *encoder_funcs;
6224 struct intel_encoder *encoder;
0b701d27 6225 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 6226 struct drm_display_mode *adjusted_mode =
6227 &intel_crtc->config.adjusted_mode;
6228 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6229 int pipe = intel_crtc->pipe;
f564048e
EA		 6230 int ret;
6231
0b701d27 6232 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6233
b8cecdf5
DV		 6234 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6235
79e53945 6236 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6237
9256aa19
DV		 6238 if (ret != 0)
6239 return ret;
6240
6241 for_each_encoder_on_crtc(dev, crtc, encoder) {
6242 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6243 encoder->base.base.id,
6244 drm_get_encoder_name(&encoder->base),
6245 mode->base.id, mode->name);
6cc5f341
DV		 6246 if (encoder->mode_set) {
6247 encoder->mode_set(encoder);
6248 } else {
6249 encoder_funcs = encoder->base.helper_private;
6250 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6251 }
9256aa19
DV		 6252 }
6253
6254 return 0;
79e53945
JB		 6255}
6256
3a9627f4
WF		 6257static bool intel_eld_uptodate(struct drm_connector *connector,
6258 int reg_eldv, uint32_t bits_eldv,
6259 int reg_elda, uint32_t bits_elda,
6260 int reg_edid)
6261{
6262 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6263 uint8_t *eld = connector->eld;
6264 uint32_t i;
6265
6266 i = I915_READ(reg_eldv);
6267 i &= bits_eldv;
6268
6269 if (!eld[0])
6270 return !i;
6271
6272 if (!i)
6273 return false;
6274
6275 i = I915_READ(reg_elda);
6276 i &= ~bits_elda;
6277 I915_WRITE(reg_elda, i);
6278
6279 for (i = 0; i < eld[2]; i++)
6280 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6281 return false;
6282
6283 return true;
6284}
6285
e0dac65e
WF		 6286static void g4x_write_eld(struct drm_connector *connector,
6287 struct drm_crtc *crtc)
6288{
6289 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6290 uint8_t *eld = connector->eld;
6291 uint32_t eldv;
6292 uint32_t len;
6293 uint32_t i;
6294
6295 i = I915_READ(G4X_AUD_VID_DID);
6296
6297 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6298 eldv = G4X_ELDV_DEVCL_DEVBLC;
6299 else
6300 eldv = G4X_ELDV_DEVCTG;
6301
3a9627f4
WF		 6302 if (intel_eld_uptodate(connector,
6303 G4X_AUD_CNTL_ST, eldv,
6304 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6305 G4X_HDMIW_HDMIEDID))
6306 return;
6307
e0dac65e
WF		 6308 i = I915_READ(G4X_AUD_CNTL_ST);
6309 i &= ~(eldv | G4X_ELD_ADDR);
6310 len = (i >> 9) & 0x1f; /* ELD buffer size */
6311 I915_WRITE(G4X_AUD_CNTL_ST, i);
6312
6313 if (!eld[0])
6314 return;
6315
6316 len = min_t(uint8_t, eld[2], len);
6317 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6318 for (i = 0; i < len; i++)
6319 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6320
6321 i = I915_READ(G4X_AUD_CNTL_ST);
6322 i |= eldv;
6323 I915_WRITE(G4X_AUD_CNTL_ST, i);
6324}
6325
83358c85
WX		 6326static void haswell_write_eld(struct drm_connector *connector,
6327 struct drm_crtc *crtc)
6328{
6329 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6330 uint8_t *eld = connector->eld;
6331 struct drm_device *dev = crtc->dev;
7b9f35a6 6332 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6333 uint32_t eldv;
6334 uint32_t i;
6335 int len;
6336 int pipe = to_intel_crtc(crtc)->pipe;
6337 int tmp;
6338
6339 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6340 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6341 int aud_config = HSW_AUD_CFG(pipe);
6342 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6343
6344
6345 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6346
6347 /* Audio output enable */
6348 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6349 tmp = I915_READ(aud_cntrl_st2);
6350 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6351 I915_WRITE(aud_cntrl_st2, tmp);
6352
6353 /* Wait for 1 vertical blank */
6354 intel_wait_for_vblank(dev, pipe);
6355
6356 /* Set ELD valid state */
6357 tmp = I915_READ(aud_cntrl_st2);
6358 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6359 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6360 I915_WRITE(aud_cntrl_st2, tmp);
6361 tmp = I915_READ(aud_cntrl_st2);
6362 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6363
6364 /* Enable HDMI mode */
6365 tmp = I915_READ(aud_config);
6366 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6367 /* clear N_programing_enable and N_value_index */
6368 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6369 I915_WRITE(aud_config, tmp);
6370
6371 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6372
6373 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6374 intel_crtc->eld_vld = true;
83358c85
WX		 6375
6376 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6377 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6378 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6379 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6380 } else
6381 I915_WRITE(aud_config, 0);
6382
6383 if (intel_eld_uptodate(connector,
6384 aud_cntrl_st2, eldv,
6385 aud_cntl_st, IBX_ELD_ADDRESS,
6386 hdmiw_hdmiedid))
6387 return;
6388
6389 i = I915_READ(aud_cntrl_st2);
6390 i &= ~eldv;
6391 I915_WRITE(aud_cntrl_st2, i);
6392
6393 if (!eld[0])
6394 return;
6395
6396 i = I915_READ(aud_cntl_st);
6397 i &= ~IBX_ELD_ADDRESS;
6398 I915_WRITE(aud_cntl_st, i);
6399 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6400 DRM_DEBUG_DRIVER("port num:%d\n", i);
6401
6402 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6403 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6404 for (i = 0; i < len; i++)
6405 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6406
6407 i = I915_READ(aud_cntrl_st2);
6408 i |= eldv;
6409 I915_WRITE(aud_cntrl_st2, i);
6410
6411}
6412
e0dac65e
WF		 6413static void ironlake_write_eld(struct drm_connector *connector,
6414 struct drm_crtc *crtc)
6415{
6416 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6417 uint8_t *eld = connector->eld;
6418 uint32_t eldv;
6419 uint32_t i;
6420 int len;
6421 int hdmiw_hdmiedid;
b6daa025 6422 int aud_config;
e0dac65e
WF		 6423 int aud_cntl_st;
6424 int aud_cntrl_st2;
9b138a83 6425 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6426
b3f33cbf 6427 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6428 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6429 aud_config = IBX_AUD_CFG(pipe);
6430 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6431 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6432 } else {
9b138a83
WX		 6433 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6434 aud_config = CPT_AUD_CFG(pipe);
6435 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6436 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6437 }
6438
9b138a83 6439 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6440
6441 i = I915_READ(aud_cntl_st);
9b138a83 6442 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6443 if (!i) {
6444 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6445 /* operate blindly on all ports */
1202b4c6
WF		 6446 eldv = IBX_ELD_VALIDB;
6447 eldv |= IBX_ELD_VALIDB << 4;
6448 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6449 } else {
2582a850 6450 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6451 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6452 }
6453
3a9627f4
WF		 6454 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6455 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6456 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6457 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6458 } else
6459 I915_WRITE(aud_config, 0);
e0dac65e 6460
3a9627f4
WF		 6461 if (intel_eld_uptodate(connector,
6462 aud_cntrl_st2, eldv,
6463 aud_cntl_st, IBX_ELD_ADDRESS,
6464 hdmiw_hdmiedid))
6465 return;
6466
e0dac65e
WF		 6467 i = I915_READ(aud_cntrl_st2);
6468 i &= ~eldv;
6469 I915_WRITE(aud_cntrl_st2, i);
6470
6471 if (!eld[0])
6472 return;
6473
e0dac65e 6474 i = I915_READ(aud_cntl_st);
1202b4c6 6475 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6476 I915_WRITE(aud_cntl_st, i);
6477
6478 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6479 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6480 for (i = 0; i < len; i++)
6481 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6482
6483 i = I915_READ(aud_cntrl_st2);
6484 i |= eldv;
6485 I915_WRITE(aud_cntrl_st2, i);
6486}
6487
6488void intel_write_eld(struct drm_encoder *encoder,
6489 struct drm_display_mode *mode)
6490{
6491 struct drm_crtc *crtc = encoder->crtc;
6492 struct drm_connector *connector;
6493 struct drm_device *dev = encoder->dev;
6494 struct drm_i915_private *dev_priv = dev->dev_private;
6495
6496 connector = drm_select_eld(encoder, mode);
6497 if (!connector)
6498 return;
6499
6500 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6501 connector->base.id,
6502 drm_get_connector_name(connector),
6503 connector->encoder->base.id,
6504 drm_get_encoder_name(connector->encoder));
6505
6506 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6507
6508 if (dev_priv->display.write_eld)
6509 dev_priv->display.write_eld(connector, crtc);
6510}
6511
79e53945
JB		 6512/** Loads the palette/gamma unit for the CRTC with the prepared values */
6513void intel_crtc_load_lut(struct drm_crtc *crtc)
6514{
6515 struct drm_device *dev = crtc->dev;
6516 struct drm_i915_private *dev_priv = dev->dev_private;
6517 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
42db64ef
PZ		 6518 enum pipe pipe = intel_crtc->pipe;
6519 int palreg = PALETTE(pipe);
79e53945 6520 int i;
42db64ef 6521 bool reenable_ips = false;
79e53945
JB		 6522
6523 /* The clocks have to be on to load the palette. */
aed3f09d 6524 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6525 return;
6526
14420bd0
VS		 6527 if (!HAS_PCH_SPLIT(dev_priv->dev))
6528 assert_pll_enabled(dev_priv, pipe);
6529
f2b115e6 6530 /* use legacy palette for Ironlake */
bad720ff 6531 if (HAS_PCH_SPLIT(dev))
42db64ef
PZ		 6532 palreg = LGC_PALETTE(pipe);
6533
6534 /* Workaround : Do not read or write the pipe palette/gamma data while
6535 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6536 */
6537 if (intel_crtc->config.ips_enabled &&
6538 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6539 GAMMA_MODE_MODE_SPLIT)) {
6540 hsw_disable_ips(intel_crtc);
6541 reenable_ips = true;
6542 }
2c07245f 6543
79e53945
JB		 6544 for (i = 0; i < 256; i++) {
6545 I915_WRITE(palreg + 4 * i,
6546 (intel_crtc->lut_r[i] << 16) |
6547 (intel_crtc->lut_g[i] << 8) |
6548 intel_crtc->lut_b[i]);
6549 }
42db64ef
PZ		 6550
6551 if (reenable_ips)
6552 hsw_enable_ips(intel_crtc);
79e53945
JB		 6553}
6554
560b85bb
CW		 6555static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6556{
6557 struct drm_device *dev = crtc->dev;
6558 struct drm_i915_private *dev_priv = dev->dev_private;
6559 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6560 bool visible = base != 0;
6561 u32 cntl;
6562
6563 if (intel_crtc->cursor_visible == visible)
6564 return;
6565
9db4a9c7 6566 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6567 if (visible) {
6568 /* On these chipsets we can only modify the base whilst
6569 * the cursor is disabled.
6570 */
9db4a9c7 6571 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6572
6573 cntl &= ~(CURSOR_FORMAT_MASK);
6574 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6575 cntl |= CURSOR_ENABLE |
6576 CURSOR_GAMMA_ENABLE |
6577 CURSOR_FORMAT_ARGB;
6578 } else
6579 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6580 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6581
6582 intel_crtc->cursor_visible = visible;
6583}
6584
6585static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6586{
6587 struct drm_device *dev = crtc->dev;
6588 struct drm_i915_private *dev_priv = dev->dev_private;
6589 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6590 int pipe = intel_crtc->pipe;
6591 bool visible = base != 0;
6592
6593 if (intel_crtc->cursor_visible != visible) {
548f245b 6594 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6595 if (base) {
6596 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6597 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6598 cntl |= pipe << 28; /* Connect to correct pipe */
6599 } else {
6600 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6601 cntl |= CURSOR_MODE_DISABLE;
6602 }
9db4a9c7 6603 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6604
6605 intel_crtc->cursor_visible = visible;
6606 }
6607 /* and commit changes on next vblank */
9db4a9c7 6608 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6609}
6610
65a21cd6
JB		 6611static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6612{
6613 struct drm_device *dev = crtc->dev;
6614 struct drm_i915_private *dev_priv = dev->dev_private;
6615 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6616 int pipe = intel_crtc->pipe;
6617 bool visible = base != 0;
6618
6619 if (intel_crtc->cursor_visible != visible) {
6620 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6621 if (base) {
6622 cntl &= ~CURSOR_MODE;
6623 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6624 } else {
6625 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6626 cntl |= CURSOR_MODE_DISABLE;
6627 }
86d3efce
VS		 6628 if (IS_HASWELL(dev))
6629 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6630 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6631
6632 intel_crtc->cursor_visible = visible;
6633 }
6634 /* and commit changes on next vblank */
6635 I915_WRITE(CURBASE_IVB(pipe), base);
6636}
6637
cda4b7d3 6638/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6639static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6640 bool on)
cda4b7d3
CW		 6641{
6642 struct drm_device *dev = crtc->dev;
6643 struct drm_i915_private *dev_priv = dev->dev_private;
6644 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6645 int pipe = intel_crtc->pipe;
6646 int x = intel_crtc->cursor_x;
6647 int y = intel_crtc->cursor_y;
560b85bb 6648 u32 base, pos;
cda4b7d3
CW		 6649 bool visible;
6650
6651 pos = 0;
6652
6b383a7f 6653 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6654 base = intel_crtc->cursor_addr;
6655 if (x > (int) crtc->fb->width)
6656 base = 0;
6657
6658 if (y > (int) crtc->fb->height)
6659 base = 0;
6660 } else
6661 base = 0;
6662
6663 if (x < 0) {
6664 if (x + intel_crtc->cursor_width < 0)
6665 base = 0;
6666
6667 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6668 x = -x;
6669 }
6670 pos |= x << CURSOR_X_SHIFT;
6671
6672 if (y < 0) {
6673 if (y + intel_crtc->cursor_height < 0)
6674 base = 0;
6675
6676 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6677 y = -y;
6678 }
6679 pos |= y << CURSOR_Y_SHIFT;
6680
6681 visible = base != 0;
560b85bb 6682 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6683 return;
6684
0cd83aa9 6685 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6686 I915_WRITE(CURPOS_IVB(pipe), pos);
6687 ivb_update_cursor(crtc, base);
6688 } else {
6689 I915_WRITE(CURPOS(pipe), pos);
6690 if (IS_845G(dev) || IS_I865G(dev))
6691 i845_update_cursor(crtc, base);
6692 else
6693 i9xx_update_cursor(crtc, base);
6694 }
cda4b7d3
CW		 6695}
6696
79e53945 6697static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6698 struct drm_file *file,
79e53945
JB		 6699 uint32_t handle,
6700 uint32_t width, uint32_t height)
6701{
6702 struct drm_device *dev = crtc->dev;
6703 struct drm_i915_private *dev_priv = dev->dev_private;
6704 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6705 struct drm_i915_gem_object *obj;
cda4b7d3 6706 uint32_t addr;
3f8bc370 6707 int ret;
79e53945 6708
79e53945
JB		 6709 /* if we want to turn off the cursor ignore width and height */
6710 if (!handle) {
28c97730 6711 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6712 addr = 0;
05394f39 6713 obj = NULL;
5004417d 6714 mutex_lock(&dev->struct_mutex);
3f8bc370 6715 goto finish;
79e53945
JB		 6716 }
6717
6718 /* Currently we only support 64x64 cursors */
6719 if (width != 64 || height != 64) {
6720 DRM_ERROR("we currently only support 64x64 cursors\n");
6721 return -EINVAL;
6722 }
6723
05394f39 6724 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6725 if (&obj->base == NULL)
79e53945
JB		 6726 return -ENOENT;
6727
05394f39 6728 if (obj->base.size < width * height * 4) {
79e53945 6729 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6730 ret = -ENOMEM;
6731 goto fail;
79e53945
JB		 6732 }
6733
71acb5eb 6734 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6735 mutex_lock(&dev->struct_mutex);
b295d1b6 6736 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6737 unsigned alignment;
6738
d9e86c0e
CW		 6739 if (obj->tiling_mode) {
6740 DRM_ERROR("cursor cannot be tiled\n");
6741 ret = -EINVAL;
6742 goto fail_locked;
6743 }
6744
693db184
CW		 6745 /* Note that the w/a also requires 2 PTE of padding following
6746 * the bo. We currently fill all unused PTE with the shadow
6747 * page and so we should always have valid PTE following the
6748 * cursor preventing the VT-d warning.
6749 */
6750 alignment = 0;
6751 if (need_vtd_wa(dev))
6752 alignment = 64*1024;
6753
6754 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6755 if (ret) {
6756 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6757 goto fail_locked;
e7b526bb
CW		 6758 }
6759
d9e86c0e
CW		 6760 ret = i915_gem_object_put_fence(obj);
6761 if (ret) {
2da3b9b9 6762 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6763 goto fail_unpin;
6764 }
6765
f343c5f6 6766 addr = i915_gem_obj_ggtt_offset(obj);
71acb5eb 6767 } else {
6eeefaf3 6768 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6769 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6770 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6771 align);
71acb5eb
DA		 6772 if (ret) {
6773 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6774 goto fail_locked;
71acb5eb 6775 }
05394f39 6776 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6777 }
6778
a6c45cf0 6779 if (IS_GEN2(dev))
14b60391
JB		 6780 I915_WRITE(CURSIZE, (height << 12) | width);
6781
3f8bc370 6782 finish:
3f8bc370 6783 if (intel_crtc->cursor_bo) {
b295d1b6 6784 if (dev_priv->info->cursor_needs_physical) {
05394f39 6785 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6786 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6787 } else
6788 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6789 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6790 }
80824003 6791
7f9872e0 6792 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6793
6794 intel_crtc->cursor_addr = addr;
05394f39 6795 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6796 intel_crtc->cursor_width = width;
6797 intel_crtc->cursor_height = height;
6798
40ccc72b 6799 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 6800
79e53945 6801 return 0;
e7b526bb 6802fail_unpin:
05394f39 6803 i915_gem_object_unpin(obj);
7f9872e0 6804fail_locked:
34b8686e 6805 mutex_unlock(&dev->struct_mutex);
bc9025bd 6806fail:
05394f39 6807 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6808 return ret;
79e53945
JB		 6809}
6810
6811static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6812{
79e53945 6813 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6814
cda4b7d3
CW		 6815 intel_crtc->cursor_x = x;
6816 intel_crtc->cursor_y = y;
652c393a 6817
40ccc72b 6818 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 6819
6820 return 0;
6821}
6822
6823/** Sets the color ramps on behalf of RandR */
6824void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6825 u16 blue, int regno)
6826{
6827 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6828
6829 intel_crtc->lut_r[regno] = red >> 8;
6830 intel_crtc->lut_g[regno] = green >> 8;
6831 intel_crtc->lut_b[regno] = blue >> 8;
6832}
6833
b8c00ac5
DA		 6834void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6835 u16 *blue, int regno)
6836{
6837 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6838
6839 *red = intel_crtc->lut_r[regno] << 8;
6840 *green = intel_crtc->lut_g[regno] << 8;
6841 *blue = intel_crtc->lut_b[regno] << 8;
6842}
6843
79e53945 6844static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6845 u16 *blue, uint32_t start, uint32_t size)
79e53945 6846{
7203425a 6847 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6848 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6849
7203425a 6850 for (i = start; i < end; i++) {
79e53945
JB		 6851 intel_crtc->lut_r[i] = red[i] >> 8;
6852 intel_crtc->lut_g[i] = green[i] >> 8;
6853 intel_crtc->lut_b[i] = blue[i] >> 8;
6854 }
6855
6856 intel_crtc_load_lut(crtc);
6857}
6858
79e53945
JB		 6859/* VESA 640x480x72Hz mode to set on the pipe */
6860static struct drm_display_mode load_detect_mode = {
6861 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6862 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6863};
6864
d2dff872
CW		 6865static struct drm_framebuffer *
6866intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6867 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6868 struct drm_i915_gem_object *obj)
6869{
6870 struct intel_framebuffer *intel_fb;
6871 int ret;
6872
6873 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6874 if (!intel_fb) {
6875 drm_gem_object_unreference_unlocked(&obj->base);
6876 return ERR_PTR(-ENOMEM);
6877 }
6878
6879 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6880 if (ret) {
6881 drm_gem_object_unreference_unlocked(&obj->base);
6882 kfree(intel_fb);
6883 return ERR_PTR(ret);
6884 }
6885
6886 return &intel_fb->base;
6887}
6888
6889static u32
6890intel_framebuffer_pitch_for_width(int width, int bpp)
6891{
6892 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6893 return ALIGN(pitch, 64);
6894}
6895
6896static u32
6897intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6898{
6899 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6900 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6901}
6902
6903static struct drm_framebuffer *
6904intel_framebuffer_create_for_mode(struct drm_device *dev,
6905 struct drm_display_mode *mode,
6906 int depth, int bpp)
6907{
6908 struct drm_i915_gem_object *obj;
0fed39bd 6909 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6910
6911 obj = i915_gem_alloc_object(dev,
6912 intel_framebuffer_size_for_mode(mode, bpp));
6913 if (obj == NULL)
6914 return ERR_PTR(-ENOMEM);
6915
6916 mode_cmd.width = mode->hdisplay;
6917 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6918 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6919 bpp);
5ca0c34a 6920 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6921
6922 return intel_framebuffer_create(dev, &mode_cmd, obj);
6923}
6924
6925static struct drm_framebuffer *
6926mode_fits_in_fbdev(struct drm_device *dev,
6927 struct drm_display_mode *mode)
6928{
6929 struct drm_i915_private *dev_priv = dev->dev_private;
6930 struct drm_i915_gem_object *obj;
6931 struct drm_framebuffer *fb;
6932
6933 if (dev_priv->fbdev == NULL)
6934 return NULL;
6935
6936 obj = dev_priv->fbdev->ifb.obj;
6937 if (obj == NULL)
6938 return NULL;
6939
6940 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6941 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6942 fb->bits_per_pixel))
d2dff872
CW		 6943 return NULL;
6944
01f2c773 6945 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6946 return NULL;
6947
6948 return fb;
6949}
6950
d2434ab7 6951bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6952 struct drm_display_mode *mode,
8261b191 6953 struct intel_load_detect_pipe *old)
79e53945
JB		 6954{
6955 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6956 struct intel_encoder *intel_encoder =
6957 intel_attached_encoder(connector);
79e53945 6958 struct drm_crtc *possible_crtc;
4ef69c7a 6959 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6960 struct drm_crtc *crtc = NULL;
6961 struct drm_device *dev = encoder->dev;
94352cf9 6962 struct drm_framebuffer *fb;
79e53945
JB		 6963 int i = -1;
6964
d2dff872
CW		 6965 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6966 connector->base.id, drm_get_connector_name(connector),
6967 encoder->base.id, drm_get_encoder_name(encoder));
6968
79e53945
JB		 6969 /*
6970 * Algorithm gets a little messy:
7a5e4805 6971 *
79e53945
JB		 6972 * - if the connector already has an assigned crtc, use it (but make
6973 * sure it's on first)
7a5e4805 6974 *
79e53945
JB		 6975 * - try to find the first unused crtc that can drive this connector,
6976 * and use that if we find one
79e53945
JB		 6977 */
6978
6979 /* See if we already have a CRTC for this connector */
6980 if (encoder->crtc) {
6981 crtc = encoder->crtc;
8261b191 6982
7b24056b
DV		 6983 mutex_lock(&crtc->mutex);
6984
24218aac 6985 old->dpms_mode = connector->dpms;
8261b191
CW		 6986 old->load_detect_temp = false;
6987
6988 /* Make sure the crtc and connector are running */
24218aac
DV		 6989 if (connector->dpms != DRM_MODE_DPMS_ON)
6990 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6991
7173188d 6992 return true;
79e53945
JB		 6993 }
6994
6995 /* Find an unused one (if possible) */
6996 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6997 i++;
6998 if (!(encoder->possible_crtcs & (1 << i)))
6999 continue;
7000 if (!possible_crtc->enabled) {
7001 crtc = possible_crtc;
7002 break;
7003 }
79e53945
JB		 7004 }
7005
7006 /*
7007 * If we didn't find an unused CRTC, don't use any.
7008 */
7009 if (!crtc) {
7173188d
CW		 7010 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7011 return false;
79e53945
JB		 7012 }
7013
7b24056b 7014 mutex_lock(&crtc->mutex);
fc303101
DV		 7015 intel_encoder->new_crtc = to_intel_crtc(crtc);
7016 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 7017
7018 intel_crtc = to_intel_crtc(crtc);
24218aac 7019 old->dpms_mode = connector->dpms;
8261b191 7020 old->load_detect_temp = true;
d2dff872 7021 old->release_fb = NULL;
79e53945 7022
6492711d
CW		 7023 if (!mode)
7024 mode = &load_detect_mode;
79e53945 7025
d2dff872
CW		 7026 /* We need a framebuffer large enough to accommodate all accesses
7027 * that the plane may generate whilst we perform load detection.
7028 * We can not rely on the fbcon either being present (we get called
7029 * during its initialisation to detect all boot displays, or it may
7030 * not even exist) or that it is large enough to satisfy the
7031 * requested mode.
7032 */
94352cf9
DV		 7033 fb = mode_fits_in_fbdev(dev, mode);
7034 if (fb == NULL) {
d2dff872 7035 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 7036 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7037 old->release_fb = fb;
d2dff872
CW		 7038 } else
7039 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 7040 if (IS_ERR(fb)) {
d2dff872 7041 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 7042 mutex_unlock(&crtc->mutex);
0e8b3d3e 7043 return false;
79e53945 7044 }
79e53945 7045
c0c36b94 7046 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 7047 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 7048 if (old->release_fb)
7049 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 7050 mutex_unlock(&crtc->mutex);
0e8b3d3e 7051 return false;
79e53945 7052 }
7173188d 7053
79e53945 7054 /* let the connector get through one full cycle before testing */
9d0498a2 7055 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 7056 return true;
79e53945
JB		 7057}
7058
d2434ab7 7059void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 7060 struct intel_load_detect_pipe *old)
79e53945 7061{
d2434ab7
DV		 7062 struct intel_encoder *intel_encoder =
7063 intel_attached_encoder(connector);
4ef69c7a 7064 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 7065 struct drm_crtc *crtc = encoder->crtc;
79e53945 7066
d2dff872
CW		 7067 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7068 connector->base.id, drm_get_connector_name(connector),
7069 encoder->base.id, drm_get_encoder_name(encoder));
7070
8261b191 7071 if (old->load_detect_temp) {
fc303101
DV		 7072 to_intel_connector(connector)->new_encoder = NULL;
7073 intel_encoder->new_crtc = NULL;
7074 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 7075
36206361
DV		 7076 if (old->release_fb) {
7077 drm_framebuffer_unregister_private(old->release_fb);
7078 drm_framebuffer_unreference(old->release_fb);
7079 }
d2dff872 7080
67c96400 7081 mutex_unlock(&crtc->mutex);
0622a53c 7082 return;
79e53945
JB		 7083 }
7084
c751ce4f 7085 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 7086 if (old->dpms_mode != DRM_MODE_DPMS_ON)
7087 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 7088
7089 mutex_unlock(&crtc->mutex);
79e53945
JB		 7090}
7091
7092/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc
JB		 7093static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7094 struct intel_crtc_config *pipe_config)
79e53945 7095{
f1f644dc 7096 struct drm_device *dev = crtc->base.dev;
79e53945 7097 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 7098 int pipe = pipe_config->cpu_transcoder;
548f245b 7099 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 7100 u32 fp;
7101 intel_clock_t clock;
7102
7103 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 7104 fp = I915_READ(FP0(pipe));
79e53945 7105 else
39adb7a5 7106 fp = I915_READ(FP1(pipe));
79e53945
JB		 7107
7108 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 7109 if (IS_PINEVIEW(dev)) {
7110 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7111 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 7112 } else {
7113 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7114 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7115 }
7116
a6c45cf0 7117 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 7118 if (IS_PINEVIEW(dev))
7119 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7120 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 7121 else
7122 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 7123 DPLL_FPA01_P1_POST_DIV_SHIFT);
7124
7125 switch (dpll & DPLL_MODE_MASK) {
7126 case DPLLB_MODE_DAC_SERIAL:
7127 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7128 5 : 10;
7129 break;
7130 case DPLLB_MODE_LVDS:
7131 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7132 7 : 14;
7133 break;
7134 default:
28c97730 7135 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 7136 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc
JB		 7137 pipe_config->adjusted_mode.clock = 0;
7138 return;
79e53945
JB		 7139 }
7140
ac58c3f0
DV		 7141 if (IS_PINEVIEW(dev))
7142 pineview_clock(96000, &clock);
7143 else
7144 i9xx_clock(96000, &clock);
79e53945
JB		 7145 } else {
7146 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7147
7148 if (is_lvds) {
7149 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7150 DPLL_FPA01_P1_POST_DIV_SHIFT);
7151 clock.p2 = 14;
7152
7153 if ((dpll & PLL_REF_INPUT_MASK) ==
7154 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7155 /* XXX: might not be 66MHz */
ac58c3f0 7156 i9xx_clock(66000, &clock);
79e53945 7157 } else
ac58c3f0 7158 i9xx_clock(48000, &clock);
79e53945
JB		 7159 } else {
7160 if (dpll & PLL_P1_DIVIDE_BY_TWO)
7161 clock.p1 = 2;
7162 else {
7163 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7164 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7165 }
7166 if (dpll & PLL_P2_DIVIDE_BY_4)
7167 clock.p2 = 4;
7168 else
7169 clock.p2 = 2;
7170
ac58c3f0 7171 i9xx_clock(48000, &clock);
79e53945
JB		 7172 }
7173 }
7174
f1f644dc
JB		 7175 pipe_config->adjusted_mode.clock = clock.dot *
7176 pipe_config->pixel_multiplier;
7177}
7178
7179static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
7180 struct intel_crtc_config *pipe_config)
7181{
7182 struct drm_device *dev = crtc->base.dev;
7183 struct drm_i915_private *dev_priv = dev->dev_private;
7184 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7185 int link_freq, repeat;
7186 u64 clock;
7187 u32 link_m, link_n;
7188
7189 repeat = pipe_config->pixel_multiplier;
7190
7191 /*
7192 * The calculation for the data clock is:
7193 * pixel_clock = ((m/n)*(link_clock * nr_lanes * repeat))/bpp
7194 * But we want to avoid losing precison if possible, so:
7195 * pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp))
7196 *
7197 * and the link clock is simpler:
7198 * link_clock = (m * link_clock * repeat) / n
7199 */
7200
7201 /*
7202 * We need to get the FDI or DP link clock here to derive
7203 * the M/N dividers.
7204 *
7205 * For FDI, we read it from the BIOS or use a fixed 2.7GHz.
7206 * For DP, it's either 1.62GHz or 2.7GHz.
7207 * We do our calculations in 10*MHz since we don't need much precison.
79e53945 7208 */
f1f644dc
JB		 7209 if (pipe_config->has_pch_encoder)
7210 link_freq = intel_fdi_link_freq(dev) * 10000;
7211 else
7212 link_freq = pipe_config->port_clock;
7213
7214 link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
7215 link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder));
7216
7217 if (!link_m || !link_n)
7218 return;
79e53945 7219
f1f644dc
JB		 7220 clock = ((u64)link_m * (u64)link_freq * (u64)repeat);
7221 do_div(clock, link_n);
7222
7223 pipe_config->adjusted_mode.clock = clock;
79e53945
JB		 7224}
7225
7226/** Returns the currently programmed mode of the given pipe. */
7227struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7228 struct drm_crtc *crtc)
7229{
548f245b 7230 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 7231 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 7232 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 7233 struct drm_display_mode *mode;
f1f644dc 7234 struct intel_crtc_config pipe_config;
fe2b8f9d
PZ		 7235 int htot = I915_READ(HTOTAL(cpu_transcoder));
7236 int hsync = I915_READ(HSYNC(cpu_transcoder));
7237 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7238 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 7239
7240 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7241 if (!mode)
7242 return NULL;
7243
f1f644dc
JB		 7244 /*
7245 * Construct a pipe_config sufficient for getting the clock info
7246 * back out of crtc_clock_get.
7247 *
7248 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7249 * to use a real value here instead.
7250 */
e143a21c 7251 pipe_config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
f1f644dc
JB		 7252 pipe_config.pixel_multiplier = 1;
7253 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7254
7255 mode->clock = pipe_config.adjusted_mode.clock;
79e53945
JB		 7256 mode->hdisplay = (htot & 0xffff) + 1;
7257 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7258 mode->hsync_start = (hsync & 0xffff) + 1;
7259 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7260 mode->vdisplay = (vtot & 0xffff) + 1;
7261 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7262 mode->vsync_start = (vsync & 0xffff) + 1;
7263 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7264
7265 drm_mode_set_name(mode);
79e53945
JB		 7266
7267 return mode;
7268}
7269
3dec0095 7270static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7271{
7272 struct drm_device *dev = crtc->dev;
7273 drm_i915_private_t *dev_priv = dev->dev_private;
7274 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7275 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7276 int dpll_reg = DPLL(pipe);
7277 int dpll;
652c393a 7278
bad720ff 7279 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7280 return;
7281
7282 if (!dev_priv->lvds_downclock_avail)
7283 return;
7284
dbdc6479 7285 dpll = I915_READ(dpll_reg);
652c393a 7286 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7287 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7288
8ac5a6d5 7289 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7290
7291 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7292 I915_WRITE(dpll_reg, dpll);
9d0498a2 7293 intel_wait_for_vblank(dev, pipe);
dbdc6479 7294
652c393a
JB		 7295 dpll = I915_READ(dpll_reg);
7296 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7297 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7298 }
652c393a
JB		 7299}
7300
7301static void intel_decrease_pllclock(struct drm_crtc *crtc)
7302{
7303 struct drm_device *dev = crtc->dev;
7304 drm_i915_private_t *dev_priv = dev->dev_private;
7305 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7306
bad720ff 7307 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7308 return;
7309
7310 if (!dev_priv->lvds_downclock_avail)
7311 return;
7312
7313 /*
7314 * Since this is called by a timer, we should never get here in
7315 * the manual case.
7316 */
7317 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7318 int pipe = intel_crtc->pipe;
7319 int dpll_reg = DPLL(pipe);
7320 int dpll;
f6e5b160 7321
44d98a61 7322 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7323
8ac5a6d5 7324 assert_panel_unlocked(dev_priv, pipe);
652c393a 7325
dc257cf1 7326 dpll = I915_READ(dpll_reg);
652c393a
JB		 7327 dpll |= DISPLAY_RATE_SELECT_FPA1;
7328 I915_WRITE(dpll_reg, dpll);
9d0498a2 7329 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7330 dpll = I915_READ(dpll_reg);
7331 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7332 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7333 }
7334
7335}
7336
f047e395
CW		 7337void intel_mark_busy(struct drm_device *dev)
7338{
f047e395
CW		 7339 i915_update_gfx_val(dev->dev_private);
7340}
7341
7342void intel_mark_idle(struct drm_device *dev)
652c393a 7343{
652c393a 7344 struct drm_crtc *crtc;
652c393a
JB		 7345
7346 if (!i915_powersave)
7347 return;
7348
652c393a 7349 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7350 if (!crtc->fb)
7351 continue;
7352
725a5b54 7353 intel_decrease_pllclock(crtc);
652c393a 7354 }
652c393a
JB		 7355}
7356
c65355bb
CW		 7357void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7358 struct intel_ring_buffer *ring)
652c393a 7359{
f047e395
CW		 7360 struct drm_device *dev = obj->base.dev;
7361 struct drm_crtc *crtc;
652c393a 7362
f047e395 7363 if (!i915_powersave)
acb87dfb
CW		 7364 return;
7365
652c393a
JB		 7366 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7367 if (!crtc->fb)
7368 continue;
7369
c65355bb
CW		 7370 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7371 continue;
7372
7373 intel_increase_pllclock(crtc);
7374 if (ring && intel_fbc_enabled(dev))
7375 ring->fbc_dirty = true;
652c393a
JB		 7376 }
7377}
7378
79e53945
JB		 7379static void intel_crtc_destroy(struct drm_crtc *crtc)
7380{
7381 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7382 struct drm_device *dev = crtc->dev;
7383 struct intel_unpin_work *work;
7384 unsigned long flags;
7385
7386 spin_lock_irqsave(&dev->event_lock, flags);
7387 work = intel_crtc->unpin_work;
7388 intel_crtc->unpin_work = NULL;
7389 spin_unlock_irqrestore(&dev->event_lock, flags);
7390
7391 if (work) {
7392 cancel_work_sync(&work->work);
7393 kfree(work);
7394 }
79e53945 7395
40ccc72b
MK		 7396 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7397
79e53945 7398 drm_crtc_cleanup(crtc);
67e77c5a 7399
79e53945
JB		 7400 kfree(intel_crtc);
7401}
7402
6b95a207
KH		 7403static void intel_unpin_work_fn(struct work_struct *__work)
7404{
7405 struct intel_unpin_work *work =
7406 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7407 struct drm_device *dev = work->crtc->dev;
6b95a207 7408
b4a98e57 7409 mutex_lock(&dev->struct_mutex);
1690e1eb 7410 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7411 drm_gem_object_unreference(&work->pending_flip_obj->base);
7412 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7413
b4a98e57
CW		 7414 intel_update_fbc(dev);
7415 mutex_unlock(&dev->struct_mutex);
7416
7417 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7418 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7419
6b95a207
KH		 7420 kfree(work);
7421}
7422
1afe3e9d 7423static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7424 struct drm_crtc *crtc)
6b95a207
KH		 7425{
7426 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7427 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7428 struct intel_unpin_work *work;
6b95a207
KH		 7429 unsigned long flags;
7430
7431 /* Ignore early vblank irqs */
7432 if (intel_crtc == NULL)
7433 return;
7434
7435 spin_lock_irqsave(&dev->event_lock, flags);
7436 work = intel_crtc->unpin_work;
e7d841ca
CW		 7437
7438 /* Ensure we don't miss a work->pending update ... */
7439 smp_rmb();
7440
7441 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7442 spin_unlock_irqrestore(&dev->event_lock, flags);
7443 return;
7444 }
7445
e7d841ca
CW		 7446 /* and that the unpin work is consistent wrt ->pending. */
7447 smp_rmb();
7448
6b95a207 7449 intel_crtc->unpin_work = NULL;
6b95a207 7450
45a066eb
RC		 7451 if (work->event)
7452 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7453
0af7e4df
MK		 7454 drm_vblank_put(dev, intel_crtc->pipe);
7455
6b95a207
KH		 7456 spin_unlock_irqrestore(&dev->event_lock, flags);
7457
2c10d571 7458 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7459
7460 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7461
7462 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7463}
7464
1afe3e9d
JB		 7465void intel_finish_page_flip(struct drm_device *dev, int pipe)
7466{
7467 drm_i915_private_t *dev_priv = dev->dev_private;
7468 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7469
49b14a5c 7470 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7471}
7472
7473void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7474{
7475 drm_i915_private_t *dev_priv = dev->dev_private;
7476 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7477
49b14a5c 7478 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7479}
7480
6b95a207
KH		 7481void intel_prepare_page_flip(struct drm_device *dev, int plane)
7482{
7483 drm_i915_private_t *dev_priv = dev->dev_private;
7484 struct intel_crtc *intel_crtc =
7485 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7486 unsigned long flags;
7487
e7d841ca
CW		 7488 /* NB: An MMIO update of the plane base pointer will also
7489 * generate a page-flip completion irq, i.e. every modeset
7490 * is also accompanied by a spurious intel_prepare_page_flip().
7491 */
6b95a207 7492 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7493 if (intel_crtc->unpin_work)
7494 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7495 spin_unlock_irqrestore(&dev->event_lock, flags);
7496}
7497
e7d841ca
CW		 7498inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7499{
7500 /* Ensure that the work item is consistent when activating it ... */
7501 smp_wmb();
7502 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7503 /* and that it is marked active as soon as the irq could fire. */
7504 smp_wmb();
7505}
7506
8c9f3aaf
JB		 7507static int intel_gen2_queue_flip(struct drm_device *dev,
7508 struct drm_crtc *crtc,
7509 struct drm_framebuffer *fb,
7510 struct drm_i915_gem_object *obj)
7511{
7512 struct drm_i915_private *dev_priv = dev->dev_private;
7513 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7514 u32 flip_mask;
6d90c952 7515 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7516 int ret;
7517
6d90c952 7518 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7519 if (ret)
83d4092b 7520 goto err;
8c9f3aaf 7521
6d90c952 7522 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7523 if (ret)
83d4092b 7524 goto err_unpin;
8c9f3aaf
JB		 7525
7526 /* Can't queue multiple flips, so wait for the previous
7527 * one to finish before executing the next.
7528 */
7529 if (intel_crtc->plane)
7530 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7531 else
7532 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7533 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7534 intel_ring_emit(ring, MI_NOOP);
7535 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7536 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7537 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7538 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952 7539 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7540
7541 intel_mark_page_flip_active(intel_crtc);
6d90c952 7542 intel_ring_advance(ring);
83d4092b
CW		 7543 return 0;
7544
7545err_unpin:
7546 intel_unpin_fb_obj(obj);
7547err:
8c9f3aaf
JB		 7548 return ret;
7549}
7550
7551static int intel_gen3_queue_flip(struct drm_device *dev,
7552 struct drm_crtc *crtc,
7553 struct drm_framebuffer *fb,
7554 struct drm_i915_gem_object *obj)
7555{
7556 struct drm_i915_private *dev_priv = dev->dev_private;
7557 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7558 u32 flip_mask;
6d90c952 7559 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7560 int ret;
7561
6d90c952 7562 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7563 if (ret)
83d4092b 7564 goto err;
8c9f3aaf 7565
6d90c952 7566 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7567 if (ret)
83d4092b 7568 goto err_unpin;
8c9f3aaf
JB		 7569
7570 if (intel_crtc->plane)
7571 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7572 else
7573 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7574 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7575 intel_ring_emit(ring, MI_NOOP);
7576 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7577 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7578 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7579 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952
DV		 7580 intel_ring_emit(ring, MI_NOOP);
7581
e7d841ca 7582 intel_mark_page_flip_active(intel_crtc);
6d90c952 7583 intel_ring_advance(ring);
83d4092b
CW		 7584 return 0;
7585
7586err_unpin:
7587 intel_unpin_fb_obj(obj);
7588err:
8c9f3aaf
JB		 7589 return ret;
7590}
7591
7592static int intel_gen4_queue_flip(struct drm_device *dev,
7593 struct drm_crtc *crtc,
7594 struct drm_framebuffer *fb,
7595 struct drm_i915_gem_object *obj)
7596{
7597 struct drm_i915_private *dev_priv = dev->dev_private;
7598 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7599 uint32_t pf, pipesrc;
6d90c952 7600 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7601 int ret;
7602
6d90c952 7603 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7604 if (ret)
83d4092b 7605 goto err;
8c9f3aaf 7606
6d90c952 7607 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7608 if (ret)
83d4092b 7609 goto err_unpin;
8c9f3aaf
JB		 7610
7611 /* i965+ uses the linear or tiled offsets from the
7612 * Display Registers (which do not change across a page-flip)
7613 * so we need only reprogram the base address.
7614 */
6d90c952
DV		 7615 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7616 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7617 intel_ring_emit(ring, fb->pitches[0]);
c2c75131 7618 intel_ring_emit(ring,
f343c5f6 7619 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
c2c75131 7620 obj->tiling_mode);
8c9f3aaf
JB		 7621
7622 /* XXX Enabling the panel-fitter across page-flip is so far
7623 * untested on non-native modes, so ignore it for now.
7624 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7625 */
7626 pf = 0;
7627 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7628 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7629
7630 intel_mark_page_flip_active(intel_crtc);
6d90c952 7631 intel_ring_advance(ring);
83d4092b
CW		 7632 return 0;
7633
7634err_unpin:
7635 intel_unpin_fb_obj(obj);
7636err:
8c9f3aaf
JB		 7637 return ret;
7638}
7639
7640static int intel_gen6_queue_flip(struct drm_device *dev,
7641 struct drm_crtc *crtc,
7642 struct drm_framebuffer *fb,
7643 struct drm_i915_gem_object *obj)
7644{
7645 struct drm_i915_private *dev_priv = dev->dev_private;
7646 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7647 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7648 uint32_t pf, pipesrc;
7649 int ret;
7650
6d90c952 7651 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7652 if (ret)
83d4092b 7653 goto err;
8c9f3aaf 7654
6d90c952 7655 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7656 if (ret)
83d4092b 7657 goto err_unpin;
8c9f3aaf 7658
6d90c952
DV		 7659 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7660 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7661 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
f343c5f6 7662 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8c9f3aaf 7663
dc257cf1
DV		 7664 /* Contrary to the suggestions in the documentation,
7665 * "Enable Panel Fitter" does not seem to be required when page
7666 * flipping with a non-native mode, and worse causes a normal
7667 * modeset to fail.
7668 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7669 */
7670 pf = 0;
8c9f3aaf 7671 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7672 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7673
7674 intel_mark_page_flip_active(intel_crtc);
6d90c952 7675 intel_ring_advance(ring);
83d4092b
CW		 7676 return 0;
7677
7678err_unpin:
7679 intel_unpin_fb_obj(obj);
7680err:
8c9f3aaf
JB		 7681 return ret;
7682}
7683
7c9017e5
JB		 7684/*
7685 * On gen7 we currently use the blit ring because (in early silicon at least)
7686 * the render ring doesn't give us interrpts for page flip completion, which
7687 * means clients will hang after the first flip is queued. Fortunately the
7688 * blit ring generates interrupts properly, so use it instead.
7689 */
7690static int intel_gen7_queue_flip(struct drm_device *dev,
7691 struct drm_crtc *crtc,
7692 struct drm_framebuffer *fb,
7693 struct drm_i915_gem_object *obj)
7694{
7695 struct drm_i915_private *dev_priv = dev->dev_private;
7696 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7697 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7698 uint32_t plane_bit = 0;
7c9017e5
JB		 7699 int ret;
7700
7701 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7702 if (ret)
83d4092b 7703 goto err;
7c9017e5 7704
cb05d8de
DV		 7705 switch(intel_crtc->plane) {
7706 case PLANE_A:
7707 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7708 break;
7709 case PLANE_B:
7710 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7711 break;
7712 case PLANE_C:
7713 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7714 break;
7715 default:
7716 WARN_ONCE(1, "unknown plane in flip command\n");
7717 ret = -ENODEV;
ab3951eb 7718 goto err_unpin;
cb05d8de
DV		 7719 }
7720
7c9017e5
JB		 7721 ret = intel_ring_begin(ring, 4);
7722 if (ret)
83d4092b 7723 goto err_unpin;
7c9017e5 7724
cb05d8de 7725 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7726 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
f343c5f6 7727 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7c9017e5 7728 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7729
7730 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7731 intel_ring_advance(ring);
83d4092b
CW		 7732 return 0;
7733
7734err_unpin:
7735 intel_unpin_fb_obj(obj);
7736err:
7c9017e5
JB		 7737 return ret;
7738}
7739
8c9f3aaf
JB		 7740static int intel_default_queue_flip(struct drm_device *dev,
7741 struct drm_crtc *crtc,
7742 struct drm_framebuffer *fb,
7743 struct drm_i915_gem_object *obj)
7744{
7745 return -ENODEV;
7746}
7747
6b95a207
KH		 7748static int intel_crtc_page_flip(struct drm_crtc *crtc,
7749 struct drm_framebuffer *fb,
7750 struct drm_pending_vblank_event *event)
7751{
7752 struct drm_device *dev = crtc->dev;
7753 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7754 struct drm_framebuffer *old_fb = crtc->fb;
7755 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7756 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7757 struct intel_unpin_work *work;
8c9f3aaf 7758 unsigned long flags;
52e68630 7759 int ret;
6b95a207 7760
e6a595d2
VS		 7761 /* Can't change pixel format via MI display flips. */
7762 if (fb->pixel_format != crtc->fb->pixel_format)
7763 return -EINVAL;
7764
7765 /*
7766 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7767 * Note that pitch changes could also affect these register.
7768 */
7769 if (INTEL_INFO(dev)->gen > 3 &&
7770 (fb->offsets[0] != crtc->fb->offsets[0] ||
7771 fb->pitches[0] != crtc->fb->pitches[0]))
7772 return -EINVAL;
7773
6b95a207
KH		 7774 work = kzalloc(sizeof *work, GFP_KERNEL);
7775 if (work == NULL)
7776 return -ENOMEM;
7777
6b95a207 7778 work->event = event;
b4a98e57 7779 work->crtc = crtc;
4a35f83b 7780 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7781 INIT_WORK(&work->work, intel_unpin_work_fn);
7782
7317c75e
JB		 7783 ret = drm_vblank_get(dev, intel_crtc->pipe);
7784 if (ret)
7785 goto free_work;
7786
6b95a207
KH		 7787 /* We borrow the event spin lock for protecting unpin_work */
7788 spin_lock_irqsave(&dev->event_lock, flags);
7789 if (intel_crtc->unpin_work) {
7790 spin_unlock_irqrestore(&dev->event_lock, flags);
7791 kfree(work);
7317c75e 7792 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7793
7794 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7795 return -EBUSY;
7796 }
7797 intel_crtc->unpin_work = work;
7798 spin_unlock_irqrestore(&dev->event_lock, flags);
7799
b4a98e57
CW		 7800 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7801 flush_workqueue(dev_priv->wq);
7802
79158103
CW		 7803 ret = i915_mutex_lock_interruptible(dev);
7804 if (ret)
7805 goto cleanup;
6b95a207 7806
75dfca80 7807 /* Reference the objects for the scheduled work. */
05394f39
CW		 7808 drm_gem_object_reference(&work->old_fb_obj->base);
7809 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7810
7811 crtc->fb = fb;
96b099fd 7812
e1f99ce6 7813 work->pending_flip_obj = obj;
e1f99ce6 7814
4e5359cd
SF		 7815 work->enable_stall_check = true;
7816
b4a98e57 7817 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7818 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7819
8c9f3aaf
JB		 7820 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7821 if (ret)
7822 goto cleanup_pending;
6b95a207 7823
7782de3b 7824 intel_disable_fbc(dev);
c65355bb 7825 intel_mark_fb_busy(obj, NULL);
6b95a207
KH		 7826 mutex_unlock(&dev->struct_mutex);
7827
e5510fac
JB		 7828 trace_i915_flip_request(intel_crtc->plane, obj);
7829
6b95a207 7830 return 0;
96b099fd 7831
8c9f3aaf 7832cleanup_pending:
b4a98e57 7833 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7834 crtc->fb = old_fb;
05394f39
CW		 7835 drm_gem_object_unreference(&work->old_fb_obj->base);
7836 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7837 mutex_unlock(&dev->struct_mutex);
7838
79158103 7839cleanup:
96b099fd
CW		 7840 spin_lock_irqsave(&dev->event_lock, flags);
7841 intel_crtc->unpin_work = NULL;
7842 spin_unlock_irqrestore(&dev->event_lock, flags);
7843
7317c75e
JB		 7844 drm_vblank_put(dev, intel_crtc->pipe);
7845free_work:
96b099fd
CW		 7846 kfree(work);
7847
7848 return ret;
6b95a207
KH		 7849}
7850
f6e5b160 7851static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7852 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7853 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7854};
7855
50f56119
DV		 7856static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7857 struct drm_crtc *crtc)
7858{
7859 struct drm_device *dev;
7860 struct drm_crtc *tmp;
7861 int crtc_mask = 1;
47f1c6c9 7862
50f56119 7863 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7864
50f56119 7865 dev = crtc->dev;
47f1c6c9 7866
50f56119
DV		 7867 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7868 if (tmp == crtc)
7869 break;
7870 crtc_mask <<= 1;
7871 }
47f1c6c9 7872
50f56119
DV		 7873 if (encoder->possible_crtcs & crtc_mask)
7874 return true;
7875 return false;
47f1c6c9 7876}
79e53945 7877
9a935856
DV		 7878/**
7879 * intel_modeset_update_staged_output_state
7880 *
7881 * Updates the staged output configuration state, e.g. after we've read out the
7882 * current hw state.
7883 */
7884static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7885{
9a935856
DV		 7886 struct intel_encoder *encoder;
7887 struct intel_connector *connector;
f6e5b160 7888
9a935856
DV		 7889 list_for_each_entry(connector, &dev->mode_config.connector_list,
7890 base.head) {
7891 connector->new_encoder =
7892 to_intel_encoder(connector->base.encoder);
7893 }
f6e5b160 7894
9a935856
DV		 7895 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7896 base.head) {
7897 encoder->new_crtc =
7898 to_intel_crtc(encoder->base.crtc);
7899 }
f6e5b160
CW		 7900}
7901
9a935856
DV		 7902/**
7903 * intel_modeset_commit_output_state
7904 *
7905 * This function copies the stage display pipe configuration to the real one.
7906 */
7907static void intel_modeset_commit_output_state(struct drm_device *dev)
7908{
7909 struct intel_encoder *encoder;
7910 struct intel_connector *connector;
f6e5b160 7911
9a935856
DV		 7912 list_for_each_entry(connector, &dev->mode_config.connector_list,
7913 base.head) {
7914 connector->base.encoder = &connector->new_encoder->base;
7915 }
f6e5b160 7916
9a935856
DV		 7917 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7918 base.head) {
7919 encoder->base.crtc = &encoder->new_crtc->base;
7920 }
7921}
7922
050f7aeb
DV		 7923static void
7924connected_sink_compute_bpp(struct intel_connector * connector,
7925 struct intel_crtc_config *pipe_config)
7926{
7927 int bpp = pipe_config->pipe_bpp;
7928
7929 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7930 connector->base.base.id,
7931 drm_get_connector_name(&connector->base));
7932
7933 /* Don't use an invalid EDID bpc value */
7934 if (connector->base.display_info.bpc &&
7935 connector->base.display_info.bpc * 3 < bpp) {
7936 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7937 bpp, connector->base.display_info.bpc*3);
7938 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7939 }
7940
7941 /* Clamp bpp to 8 on screens without EDID 1.4 */
7942 if (connector->base.display_info.bpc == 0 && bpp > 24) {
7943 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7944 bpp);
7945 pipe_config->pipe_bpp = 24;
7946 }
7947}
7948
4e53c2e0 7949static int
050f7aeb
DV		 7950compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7951 struct drm_framebuffer *fb,
7952 struct intel_crtc_config *pipe_config)
4e53c2e0 7953{
050f7aeb
DV		 7954 struct drm_device *dev = crtc->base.dev;
7955 struct intel_connector *connector;
4e53c2e0
DV		 7956 int bpp;
7957
d42264b1
DV		 7958 switch (fb->pixel_format) {
7959 case DRM_FORMAT_C8:
4e53c2e0
DV		 7960 bpp = 8*3; /* since we go through a colormap */
7961 break;
d42264b1
DV		 7962 case DRM_FORMAT_XRGB1555:
7963 case DRM_FORMAT_ARGB1555:
7964 /* checked in intel_framebuffer_init already */
7965 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7966 return -EINVAL;
7967 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 7968 bpp = 6*3; /* min is 18bpp */
7969 break;
d42264b1
DV		 7970 case DRM_FORMAT_XBGR8888:
7971 case DRM_FORMAT_ABGR8888:
7972 /* checked in intel_framebuffer_init already */
7973 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7974 return -EINVAL;
7975 case DRM_FORMAT_XRGB8888:
7976 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 7977 bpp = 8*3;
7978 break;
d42264b1
DV		 7979 case DRM_FORMAT_XRGB2101010:
7980 case DRM_FORMAT_ARGB2101010:
7981 case DRM_FORMAT_XBGR2101010:
7982 case DRM_FORMAT_ABGR2101010:
7983 /* checked in intel_framebuffer_init already */
7984 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 7985 return -EINVAL;
4e53c2e0
DV		 7986 bpp = 10*3;
7987 break;
baba133a 7988 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 7989 default:
7990 DRM_DEBUG_KMS("unsupported depth\n");
7991 return -EINVAL;
7992 }
7993
4e53c2e0
DV		 7994 pipe_config->pipe_bpp = bpp;
7995
7996 /* Clamp display bpp to EDID value */
7997 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 7998 base.head) {
1b829e05
DV		 7999 if (!connector->new_encoder ||
8000 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 8001 continue;
8002
050f7aeb 8003 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 8004 }
8005
8006 return bpp;
8007}
8008
c0b03411
DV		 8009static void intel_dump_pipe_config(struct intel_crtc *crtc,
8010 struct intel_crtc_config *pipe_config,
8011 const char *context)
8012{
8013 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8014 context, pipe_name(crtc->pipe));
8015
8016 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8017 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8018 pipe_config->pipe_bpp, pipe_config->dither);
8019 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8020 pipe_config->has_pch_encoder,
8021 pipe_config->fdi_lanes,
8022 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8023 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8024 pipe_config->fdi_m_n.tu);
8025 DRM_DEBUG_KMS("requested mode:\n");
8026 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8027 DRM_DEBUG_KMS("adjusted mode:\n");
8028 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8029 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8030 pipe_config->gmch_pfit.control,
8031 pipe_config->gmch_pfit.pgm_ratios,
8032 pipe_config->gmch_pfit.lvds_border_bits);
8033 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
8034 pipe_config->pch_pfit.pos,
8035 pipe_config->pch_pfit.size);
42db64ef 8036 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
c0b03411
DV		 8037}
8038
accfc0c5
DV		 8039static bool check_encoder_cloning(struct drm_crtc *crtc)
8040{
8041 int num_encoders = 0;
8042 bool uncloneable_encoders = false;
8043 struct intel_encoder *encoder;
8044
8045 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8046 base.head) {
8047 if (&encoder->new_crtc->base != crtc)
8048 continue;
8049
8050 num_encoders++;
8051 if (!encoder->cloneable)
8052 uncloneable_encoders = true;
8053 }
8054
8055 return !(num_encoders > 1 && uncloneable_encoders);
8056}
8057
b8cecdf5
DV		 8058static struct intel_crtc_config *
8059intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 8060 struct drm_framebuffer *fb,
b8cecdf5 8061 struct drm_display_mode *mode)
ee7b9f93 8062{
7758a113 8063 struct drm_device *dev = crtc->dev;
7758a113
DV		 8064 struct drm_encoder_helper_funcs *encoder_funcs;
8065 struct intel_encoder *encoder;
b8cecdf5 8066 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 8067 int plane_bpp, ret = -EINVAL;
8068 bool retry = true;
ee7b9f93 8069
accfc0c5
DV		 8070 if (!check_encoder_cloning(crtc)) {
8071 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8072 return ERR_PTR(-EINVAL);
8073 }
8074
b8cecdf5
DV		 8075 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8076 if (!pipe_config)
7758a113
DV		 8077 return ERR_PTR(-ENOMEM);
8078
b8cecdf5
DV		 8079 drm_mode_copy(&pipe_config->adjusted_mode, mode);
8080 drm_mode_copy(&pipe_config->requested_mode, mode);
e143a21c
DV		 8081 pipe_config->cpu_transcoder =
8082 (enum transcoder) to_intel_crtc(crtc)->pipe;
c0d43d62 8083 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 8084
050f7aeb
DV		 8085 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8086 * plane pixel format and any sink constraints into account. Returns the
8087 * source plane bpp so that dithering can be selected on mismatches
8088 * after encoders and crtc also have had their say. */
8089 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8090 fb, pipe_config);
4e53c2e0
DV		 8091 if (plane_bpp < 0)
8092 goto fail;
8093
e29c22c0 8094encoder_retry:
ef1b460d 8095 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 8096 pipe_config->port_clock = 0;
ef1b460d 8097 pipe_config->pixel_multiplier = 1;
ff9a6750 8098
7758a113
DV		 8099 /* Pass our mode to the connectors and the CRTC to give them a chance to
8100 * adjust it according to limitations or connector properties, and also
8101 * a chance to reject the mode entirely.
47f1c6c9 8102 */
7758a113
DV		 8103 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8104 base.head) {
47f1c6c9 8105
7758a113
DV		 8106 if (&encoder->new_crtc->base != crtc)
8107 continue;
7ae89233
DV		 8108
8109 if (encoder->compute_config) {
8110 if (!(encoder->compute_config(encoder, pipe_config))) {
8111 DRM_DEBUG_KMS("Encoder config failure\n");
8112 goto fail;
8113 }
8114
8115 continue;
8116 }
8117
7758a113 8118 encoder_funcs = encoder->base.helper_private;
b8cecdf5
DV		 8119 if (!(encoder_funcs->mode_fixup(&encoder->base,
8120 &pipe_config->requested_mode,
8121 &pipe_config->adjusted_mode))) {
7758a113
DV		 8122 DRM_DEBUG_KMS("Encoder fixup failed\n");
8123 goto fail;
8124 }
ee7b9f93 8125 }
47f1c6c9 8126
ff9a6750
DV		 8127 /* Set default port clock if not overwritten by the encoder. Needs to be
8128 * done afterwards in case the encoder adjusts the mode. */
8129 if (!pipe_config->port_clock)
8130 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
8131
a43f6e0f 8132 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 8133 if (ret < 0) {
7758a113
DV		 8134 DRM_DEBUG_KMS("CRTC fixup failed\n");
8135 goto fail;
ee7b9f93 8136 }
e29c22c0
DV		 8137
8138 if (ret == RETRY) {
8139 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8140 ret = -EINVAL;
8141 goto fail;
8142 }
8143
8144 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8145 retry = false;
8146 goto encoder_retry;
8147 }
8148
4e53c2e0
DV		 8149 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8150 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8151 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8152
b8cecdf5 8153 return pipe_config;
7758a113 8154fail:
b8cecdf5 8155 kfree(pipe_config);
e29c22c0 8156 return ERR_PTR(ret);
ee7b9f93 8157}
47f1c6c9 8158
e2e1ed41
DV		 8159/* Computes which crtcs are affected and sets the relevant bits in the mask. For
8160 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8161static void
8162intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8163 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 8164{
8165 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 8166 struct drm_device *dev = crtc->dev;
8167 struct intel_encoder *encoder;
8168 struct intel_connector *connector;
8169 struct drm_crtc *tmp_crtc;
79e53945 8170
e2e1ed41 8171 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 8172
e2e1ed41
DV		 8173 /* Check which crtcs have changed outputs connected to them, these need
8174 * to be part of the prepare_pipes mask. We don't (yet) support global
8175 * modeset across multiple crtcs, so modeset_pipes will only have one
8176 * bit set at most. */
8177 list_for_each_entry(connector, &dev->mode_config.connector_list,
8178 base.head) {
8179 if (connector->base.encoder == &connector->new_encoder->base)
8180 continue;
79e53945 8181
e2e1ed41
DV		 8182 if (connector->base.encoder) {
8183 tmp_crtc = connector->base.encoder->crtc;
8184
8185 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8186 }
8187
8188 if (connector->new_encoder)
8189 *prepare_pipes |=
8190 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 8191 }
8192
e2e1ed41
DV		 8193 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8194 base.head) {
8195 if (encoder->base.crtc == &encoder->new_crtc->base)
8196 continue;
8197
8198 if (encoder->base.crtc) {
8199 tmp_crtc = encoder->base.crtc;
8200
8201 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8202 }
8203
8204 if (encoder->new_crtc)
8205 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 8206 }
8207
e2e1ed41
DV		 8208 /* Check for any pipes that will be fully disabled ... */
8209 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8210 base.head) {
8211 bool used = false;
22fd0fab 8212
e2e1ed41
DV		 8213 /* Don't try to disable disabled crtcs. */
8214 if (!intel_crtc->base.enabled)
8215 continue;
7e7d76c3 8216
e2e1ed41
DV		 8217 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8218 base.head) {
8219 if (encoder->new_crtc == intel_crtc)
8220 used = true;
8221 }
8222
8223 if (!used)
8224 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 8225 }
8226
e2e1ed41
DV		 8227
8228 /* set_mode is also used to update properties on life display pipes. */
8229 intel_crtc = to_intel_crtc(crtc);
8230 if (crtc->enabled)
8231 *prepare_pipes |= 1 << intel_crtc->pipe;
8232
b6c5164d
DV		 8233 /*
8234 * For simplicity do a full modeset on any pipe where the output routing
8235 * changed. We could be more clever, but that would require us to be
8236 * more careful with calling the relevant encoder->mode_set functions.
8237 */
e2e1ed41
DV		 8238 if (*prepare_pipes)
8239 *modeset_pipes = *prepare_pipes;
8240
8241 /* ... and mask these out. */
8242 *modeset_pipes &= ~(*disable_pipes);
8243 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 8244
8245 /*
8246 * HACK: We don't (yet) fully support global modesets. intel_set_config
8247 * obies this rule, but the modeset restore mode of
8248 * intel_modeset_setup_hw_state does not.
8249 */
8250 *modeset_pipes &= 1 << intel_crtc->pipe;
8251 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 8252
8253 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8254 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 8255}
79e53945 8256
ea9d758d 8257static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 8258{
ea9d758d 8259 struct drm_encoder *encoder;
f6e5b160 8260 struct drm_device *dev = crtc->dev;
f6e5b160 8261
ea9d758d
DV		 8262 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8263 if (encoder->crtc == crtc)
8264 return true;
8265
8266 return false;
8267}
8268
8269static void
8270intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8271{
8272 struct intel_encoder *intel_encoder;
8273 struct intel_crtc *intel_crtc;
8274 struct drm_connector *connector;
8275
8276 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8277 base.head) {
8278 if (!intel_encoder->base.crtc)
8279 continue;
8280
8281 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8282
8283 if (prepare_pipes & (1 << intel_crtc->pipe))
8284 intel_encoder->connectors_active = false;
8285 }
8286
8287 intel_modeset_commit_output_state(dev);
8288
8289 /* Update computed state. */
8290 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8291 base.head) {
8292 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8293 }
8294
8295 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8296 if (!connector->encoder || !connector->encoder->crtc)
8297 continue;
8298
8299 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8300
8301 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8302 struct drm_property *dpms_property =
8303 dev->mode_config.dpms_property;
8304
ea9d758d 8305 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8306 drm_object_property_set_value(&connector->base,
68d34720
DV		 8307 dpms_property,
8308 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8309
8310 intel_encoder = to_intel_encoder(connector->encoder);
8311 intel_encoder->connectors_active = true;
8312 }
8313 }
8314
8315}
8316
f1f644dc
JB		 8317static bool intel_fuzzy_clock_check(struct intel_crtc_config *cur,
8318 struct intel_crtc_config *new)
8319{
8320 int clock1, clock2, diff;
8321
8322 clock1 = cur->adjusted_mode.clock;
8323 clock2 = new->adjusted_mode.clock;
8324
8325 if (clock1 == clock2)
8326 return true;
8327
8328 if (!clock1 || !clock2)
8329 return false;
8330
8331 diff = abs(clock1 - clock2);
8332
8333 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8334 return true;
8335
8336 return false;
8337}
8338
25c5b266
DV		 8339#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8340 list_for_each_entry((intel_crtc), \
8341 &(dev)->mode_config.crtc_list, \
8342 base.head) \
0973f18f 8343 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8344
0e8ffe1b 8345static bool
2fa2fe9a
DV		 8346intel_pipe_config_compare(struct drm_device *dev,
8347 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8348 struct intel_crtc_config *pipe_config)
8349{
66e985c0
DV		 8350#define PIPE_CONF_CHECK_X(name) \
8351 if (current_config->name != pipe_config->name) { \
8352 DRM_ERROR("mismatch in " #name " " \
8353 "(expected 0x%08x, found 0x%08x)\n", \
8354 current_config->name, \
8355 pipe_config->name); \
8356 return false; \
8357 }
8358
08a24034
DV		 8359#define PIPE_CONF_CHECK_I(name) \
8360 if (current_config->name != pipe_config->name) { \
8361 DRM_ERROR("mismatch in " #name " " \
8362 "(expected %i, found %i)\n", \
8363 current_config->name, \
8364 pipe_config->name); \
8365 return false; \
88adfff1
DV		 8366 }
8367
1bd1bd80
DV		 8368#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8369 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 8370 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 8371 "(expected %i, found %i)\n", \
8372 current_config->name & (mask), \
8373 pipe_config->name & (mask)); \
8374 return false; \
8375 }
8376
bb760063
DV		 8377#define PIPE_CONF_QUIRK(quirk) \
8378 ((current_config->quirks | pipe_config->quirks) & (quirk))
8379
eccb140b
DV		 8380 PIPE_CONF_CHECK_I(cpu_transcoder);
8381
08a24034
DV		 8382 PIPE_CONF_CHECK_I(has_pch_encoder);
8383 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8384 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8385 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8386 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8387 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8388 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8389
1bd1bd80
DV		 8390 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8391 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8392 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8393 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8394 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8395 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8396
8397 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8398 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8399 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8400 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8401 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8402 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8403
c93f54cf 8404 PIPE_CONF_CHECK_I(pixel_multiplier);
6c49f241 8405
1bd1bd80
DV		 8406 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8407 DRM_MODE_FLAG_INTERLACE);
8408
bb760063
DV		 8409 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8410 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8411 DRM_MODE_FLAG_PHSYNC);
8412 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8413 DRM_MODE_FLAG_NHSYNC);
8414 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8415 DRM_MODE_FLAG_PVSYNC);
8416 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8417 DRM_MODE_FLAG_NVSYNC);
8418 }
045ac3b5 8419
1bd1bd80
DV		 8420 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8421 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8422
2fa2fe9a
DV		 8423 PIPE_CONF_CHECK_I(gmch_pfit.control);
8424 /* pfit ratios are autocomputed by the hw on gen4+ */
8425 if (INTEL_INFO(dev)->gen < 4)
8426 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8427 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8428 PIPE_CONF_CHECK_I(pch_pfit.pos);
8429 PIPE_CONF_CHECK_I(pch_pfit.size);
8430
42db64ef
PZ		 8431 PIPE_CONF_CHECK_I(ips_enabled);
8432
c0d43d62 8433 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 8434 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 8435 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 8436 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8437 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
c0d43d62 8438
66e985c0 8439#undef PIPE_CONF_CHECK_X
08a24034 8440#undef PIPE_CONF_CHECK_I
1bd1bd80 8441#undef PIPE_CONF_CHECK_FLAGS
bb760063 8442#undef PIPE_CONF_QUIRK
88adfff1 8443
f1f644dc
JB		 8444 if (!IS_HASWELL(dev)) {
8445 if (!intel_fuzzy_clock_check(current_config, pipe_config)) {
6f02488e 8446 DRM_ERROR("mismatch in clock (expected %d, found %d)\n",
f1f644dc
JB		 8447 current_config->adjusted_mode.clock,
8448 pipe_config->adjusted_mode.clock);
8449 return false;
8450 }
8451 }
8452
0e8ffe1b
DV		 8453 return true;
8454}
8455
91d1b4bd
DV		 8456static void
8457check_connector_state(struct drm_device *dev)
8af6cf88 8458{
8af6cf88
DV		 8459 struct intel_connector *connector;
8460
8461 list_for_each_entry(connector, &dev->mode_config.connector_list,
8462 base.head) {
8463 /* This also checks the encoder/connector hw state with the
8464 * ->get_hw_state callbacks. */
8465 intel_connector_check_state(connector);
8466
8467 WARN(&connector->new_encoder->base != connector->base.encoder,
8468 "connector's staged encoder doesn't match current encoder\n");
8469 }
91d1b4bd
DV		 8470}
8471
8472static void
8473check_encoder_state(struct drm_device *dev)
8474{
8475 struct intel_encoder *encoder;
8476 struct intel_connector *connector;
8af6cf88
DV		 8477
8478 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8479 base.head) {
8480 bool enabled = false;
8481 bool active = false;
8482 enum pipe pipe, tracked_pipe;
8483
8484 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8485 encoder->base.base.id,
8486 drm_get_encoder_name(&encoder->base));
8487
8488 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8489 "encoder's stage crtc doesn't match current crtc\n");
8490 WARN(encoder->connectors_active && !encoder->base.crtc,
8491 "encoder's active_connectors set, but no crtc\n");
8492
8493 list_for_each_entry(connector, &dev->mode_config.connector_list,
8494 base.head) {
8495 if (connector->base.encoder != &encoder->base)
8496 continue;
8497 enabled = true;
8498 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8499 active = true;
8500 }
8501 WARN(!!encoder->base.crtc != enabled,
8502 "encoder's enabled state mismatch "
8503 "(expected %i, found %i)\n",
8504 !!encoder->base.crtc, enabled);
8505 WARN(active && !encoder->base.crtc,
8506 "active encoder with no crtc\n");
8507
8508 WARN(encoder->connectors_active != active,
8509 "encoder's computed active state doesn't match tracked active state "
8510 "(expected %i, found %i)\n", active, encoder->connectors_active);
8511
8512 active = encoder->get_hw_state(encoder, &pipe);
8513 WARN(active != encoder->connectors_active,
8514 "encoder's hw state doesn't match sw tracking "
8515 "(expected %i, found %i)\n",
8516 encoder->connectors_active, active);
8517
8518 if (!encoder->base.crtc)
8519 continue;
8520
8521 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8522 WARN(active && pipe != tracked_pipe,
8523 "active encoder's pipe doesn't match"
8524 "(expected %i, found %i)\n",
8525 tracked_pipe, pipe);
8526
8527 }
91d1b4bd
DV		 8528}
8529
8530static void
8531check_crtc_state(struct drm_device *dev)
8532{
8533 drm_i915_private_t *dev_priv = dev->dev_private;
8534 struct intel_crtc *crtc;
8535 struct intel_encoder *encoder;
8536 struct intel_crtc_config pipe_config;
8af6cf88
DV		 8537
8538 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8539 base.head) {
8540 bool enabled = false;
8541 bool active = false;
8542
045ac3b5
JB		 8543 memset(&pipe_config, 0, sizeof(pipe_config));
8544
8af6cf88
DV		 8545 DRM_DEBUG_KMS("[CRTC:%d]\n",
8546 crtc->base.base.id);
8547
8548 WARN(crtc->active && !crtc->base.enabled,
8549 "active crtc, but not enabled in sw tracking\n");
8550
8551 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8552 base.head) {
8553 if (encoder->base.crtc != &crtc->base)
8554 continue;
8555 enabled = true;
8556 if (encoder->connectors_active)
8557 active = true;
8558 }
6c49f241 8559
8af6cf88
DV		 8560 WARN(active != crtc->active,
8561 "crtc's computed active state doesn't match tracked active state "
8562 "(expected %i, found %i)\n", active, crtc->active);
8563 WARN(enabled != crtc->base.enabled,
8564 "crtc's computed enabled state doesn't match tracked enabled state "
8565 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8566
0e8ffe1b
DV		 8567 active = dev_priv->display.get_pipe_config(crtc,
8568 &pipe_config);
d62cf62a
DV		 8569
8570 /* hw state is inconsistent with the pipe A quirk */
8571 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8572 active = crtc->active;
8573
6c49f241
DV		 8574 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8575 base.head) {
8576 if (encoder->base.crtc != &crtc->base)
8577 continue;
510d5f2f 8578 if (encoder->get_config)
6c49f241
DV		 8579 encoder->get_config(encoder, &pipe_config);
8580 }
8581
510d5f2f
JB		 8582 if (dev_priv->display.get_clock)
8583 dev_priv->display.get_clock(crtc, &pipe_config);
8584
0e8ffe1b
DV		 8585 WARN(crtc->active != active,
8586 "crtc active state doesn't match with hw state "
8587 "(expected %i, found %i)\n", crtc->active, active);
8588
c0b03411
DV		 8589 if (active &&
8590 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8591 WARN(1, "pipe state doesn't match!\n");
8592 intel_dump_pipe_config(crtc, &pipe_config,
8593 "[hw state]");
8594 intel_dump_pipe_config(crtc, &crtc->config,
8595 "[sw state]");
8596 }
8af6cf88
DV		 8597 }
8598}
8599
91d1b4bd
DV		 8600static void
8601check_shared_dpll_state(struct drm_device *dev)
8602{
8603 drm_i915_private_t *dev_priv = dev->dev_private;
8604 struct intel_crtc *crtc;
8605 struct intel_dpll_hw_state dpll_hw_state;
8606 int i;
5358901f
DV		 8607
8608 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8609 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8610 int enabled_crtcs = 0, active_crtcs = 0;
8611 bool active;
8612
8613 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8614
8615 DRM_DEBUG_KMS("%s\n", pll->name);
8616
8617 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8618
8619 WARN(pll->active > pll->refcount,
8620 "more active pll users than references: %i vs %i\n",
8621 pll->active, pll->refcount);
8622 WARN(pll->active && !pll->on,
8623 "pll in active use but not on in sw tracking\n");
35c95375
DV		 8624 WARN(pll->on && !pll->active,
8625 "pll in on but not on in use in sw tracking\n");
5358901f
DV		 8626 WARN(pll->on != active,
8627 "pll on state mismatch (expected %i, found %i)\n",
8628 pll->on, active);
8629
8630 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8631 base.head) {
8632 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8633 enabled_crtcs++;
8634 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8635 active_crtcs++;
8636 }
8637 WARN(pll->active != active_crtcs,
8638 "pll active crtcs mismatch (expected %i, found %i)\n",
8639 pll->active, active_crtcs);
8640 WARN(pll->refcount != enabled_crtcs,
8641 "pll enabled crtcs mismatch (expected %i, found %i)\n",
8642 pll->refcount, enabled_crtcs);
66e985c0
DV		 8643
8644 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8645 sizeof(dpll_hw_state)),
8646 "pll hw state mismatch\n");
5358901f 8647 }
8af6cf88
DV		 8648}
8649
91d1b4bd
DV		 8650void
8651intel_modeset_check_state(struct drm_device *dev)
8652{
8653 check_connector_state(dev);
8654 check_encoder_state(dev);
8655 check_crtc_state(dev);
8656 check_shared_dpll_state(dev);
8657}
8658
f30da187
DV		 8659static int __intel_set_mode(struct drm_crtc *crtc,
8660 struct drm_display_mode *mode,
8661 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 8662{
8663 struct drm_device *dev = crtc->dev;
dbf2b54e 8664 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 8665 struct drm_display_mode *saved_mode, *saved_hwmode;
8666 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 8667 struct intel_crtc *intel_crtc;
8668 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 8669 int ret = 0;
a6778b3c 8670
3ac18232 8671 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 8672 if (!saved_mode)
8673 return -ENOMEM;
3ac18232 8674 saved_hwmode = saved_mode + 1;
a6778b3c 8675
e2e1ed41 8676 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 8677 &prepare_pipes, &disable_pipes);
8678
3ac18232
TG		 8679 *saved_hwmode = crtc->hwmode;
8680 *saved_mode = crtc->mode;
a6778b3c 8681
25c5b266
DV		 8682 /* Hack: Because we don't (yet) support global modeset on multiple
8683 * crtcs, we don't keep track of the new mode for more than one crtc.
8684 * Hence simply check whether any bit is set in modeset_pipes in all the
8685 * pieces of code that are not yet converted to deal with mutliple crtcs
8686 * changing their mode at the same time. */
25c5b266 8687 if (modeset_pipes) {
4e53c2e0 8688 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 8689 if (IS_ERR(pipe_config)) {
8690 ret = PTR_ERR(pipe_config);
8691 pipe_config = NULL;
8692
3ac18232 8693 goto out;
25c5b266 8694 }
c0b03411
DV		 8695 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8696 "[modeset]");
25c5b266 8697 }
a6778b3c 8698
460da916
DV		 8699 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8700 intel_crtc_disable(&intel_crtc->base);
8701
ea9d758d
DV		 8702 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8703 if (intel_crtc->base.enabled)
8704 dev_priv->display.crtc_disable(&intel_crtc->base);
8705 }
a6778b3c 8706
6c4c86f5
DV		 8707 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8708 * to set it here already despite that we pass it down the callchain.
f6e5b160 8709 */
b8cecdf5 8710 if (modeset_pipes) {
25c5b266 8711 crtc->mode = *mode;
b8cecdf5
DV		 8712 /* mode_set/enable/disable functions rely on a correct pipe
8713 * config. */
8714 to_intel_crtc(crtc)->config = *pipe_config;
8715 }
7758a113 8716
ea9d758d
DV		 8717 /* Only after disabling all output pipelines that will be changed can we
8718 * update the the output configuration. */
8719 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 8720
47fab737
DV		 8721 if (dev_priv->display.modeset_global_resources)
8722 dev_priv->display.modeset_global_resources(dev);
8723
a6778b3c
DV		 8724 /* Set up the DPLL and any encoders state that needs to adjust or depend
8725 * on the DPLL.
f6e5b160 8726 */
25c5b266 8727 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 8728 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 8729 x, y, fb);
8730 if (ret)
8731 goto done;
a6778b3c
DV		 8732 }
8733
8734 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 8735 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8736 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 8737
25c5b266
DV		 8738 if (modeset_pipes) {
8739 /* Store real post-adjustment hardware mode. */
b8cecdf5 8740 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 8741
25c5b266
DV		 8742 /* Calculate and store various constants which
8743 * are later needed by vblank and swap-completion
8744 * timestamping. They are derived from true hwmode.
8745 */
8746 drm_calc_timestamping_constants(crtc);
8747 }
a6778b3c
DV		 8748
8749 /* FIXME: add subpixel order */
8750done:
c0c36b94 8751 if (ret && crtc->enabled) {
3ac18232
TG		 8752 crtc->hwmode = *saved_hwmode;
8753 crtc->mode = *saved_mode;
a6778b3c
DV		 8754 }
8755
3ac18232 8756out:
b8cecdf5 8757 kfree(pipe_config);
3ac18232 8758 kfree(saved_mode);
a6778b3c 8759 return ret;
f6e5b160
CW		 8760}
8761
f30da187
DV		 8762int intel_set_mode(struct drm_crtc *crtc,
8763 struct drm_display_mode *mode,
8764 int x, int y, struct drm_framebuffer *fb)
8765{
8766 int ret;
8767
8768 ret = __intel_set_mode(crtc, mode, x, y, fb);
8769
8770 if (ret == 0)
8771 intel_modeset_check_state(crtc->dev);
8772
8773 return ret;
8774}
8775
c0c36b94
CW		 8776void intel_crtc_restore_mode(struct drm_crtc *crtc)
8777{
8778 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8779}
8780
25c5b266
DV		 8781#undef for_each_intel_crtc_masked
8782
d9e55608
DV		 8783static void intel_set_config_free(struct intel_set_config *config)
8784{
8785 if (!config)
8786 return;
8787
1aa4b628
DV		 8788 kfree(config->save_connector_encoders);
8789 kfree(config->save_encoder_crtcs);
d9e55608
DV		 8790 kfree(config);
8791}
8792
85f9eb71
DV		 8793static int intel_set_config_save_state(struct drm_device *dev,
8794 struct intel_set_config *config)
8795{
85f9eb71
DV		 8796 struct drm_encoder *encoder;
8797 struct drm_connector *connector;
8798 int count;
8799
1aa4b628
DV		 8800 config->save_encoder_crtcs =
8801 kcalloc(dev->mode_config.num_encoder,
8802 sizeof(struct drm_crtc *), GFP_KERNEL);
8803 if (!config->save_encoder_crtcs)
85f9eb71
DV		 8804 return -ENOMEM;
8805
1aa4b628
DV		 8806 config->save_connector_encoders =
8807 kcalloc(dev->mode_config.num_connector,
8808 sizeof(struct drm_encoder *), GFP_KERNEL);
8809 if (!config->save_connector_encoders)
85f9eb71
DV		 8810 return -ENOMEM;
8811
8812 /* Copy data. Note that driver private data is not affected.
8813 * Should anything bad happen only the expected state is
8814 * restored, not the drivers personal bookkeeping.
8815 */
85f9eb71
DV		 8816 count = 0;
8817 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 8818 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 8819 }
8820
8821 count = 0;
8822 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 8823 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 8824 }
8825
8826 return 0;
8827}
8828
8829static void intel_set_config_restore_state(struct drm_device *dev,
8830 struct intel_set_config *config)
8831{
9a935856
DV		 8832 struct intel_encoder *encoder;
8833 struct intel_connector *connector;
85f9eb71
DV		 8834 int count;
8835
85f9eb71 8836 count = 0;
9a935856
DV		 8837 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8838 encoder->new_crtc =
8839 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 8840 }
8841
8842 count = 0;
9a935856
DV		 8843 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8844 connector->new_encoder =
8845 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 8846 }
8847}
8848
e3de42b6 8849static bool
2e57f47d 8850is_crtc_connector_off(struct drm_mode_set *set)
e3de42b6
ID		 8851{
8852 int i;
8853
2e57f47d
CW		 8854 if (set->num_connectors == 0)
8855 return false;
8856
8857 if (WARN_ON(set->connectors == NULL))
8858 return false;
8859
8860 for (i = 0; i < set->num_connectors; i++)
8861 if (set->connectors[i]->encoder &&
8862 set->connectors[i]->encoder->crtc == set->crtc &&
8863 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
e3de42b6
ID		 8864 return true;
8865
8866 return false;
8867}
8868
5e2b584e
DV		 8869static void
8870intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8871 struct intel_set_config *config)
8872{
8873
8874 /* We should be able to check here if the fb has the same properties
8875 * and then just flip_or_move it */
2e57f47d
CW		 8876 if (is_crtc_connector_off(set)) {
8877 config->mode_changed = true;
e3de42b6 8878 } else if (set->crtc->fb != set->fb) {
5e2b584e
DV		 8879 /* If we have no fb then treat it as a full mode set */
8880 if (set->crtc->fb == NULL) {
319d9827
JB		 8881 struct intel_crtc *intel_crtc =
8882 to_intel_crtc(set->crtc);
8883
8884 if (intel_crtc->active && i915_fastboot) {
8885 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
8886 config->fb_changed = true;
8887 } else {
8888 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
8889 config->mode_changed = true;
8890 }
5e2b584e
DV		 8891 } else if (set->fb == NULL) {
8892 config->mode_changed = true;
72f4901e
DV		 8893 } else if (set->fb->pixel_format !=
8894 set->crtc->fb->pixel_format) {
5e2b584e 8895 config->mode_changed = true;
e3de42b6 8896 } else {
5e2b584e 8897 config->fb_changed = true;
e3de42b6 8898 }
5e2b584e
DV		 8899 }
8900
835c5873 8901 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 8902 config->fb_changed = true;
8903
8904 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8905 DRM_DEBUG_KMS("modes are different, full mode set\n");
8906 drm_mode_debug_printmodeline(&set->crtc->mode);
8907 drm_mode_debug_printmodeline(set->mode);
8908 config->mode_changed = true;
8909 }
8910}
8911
2e431051 8912static int
9a935856
DV		 8913intel_modeset_stage_output_state(struct drm_device *dev,
8914 struct drm_mode_set *set,
8915 struct intel_set_config *config)
50f56119 8916{
85f9eb71 8917 struct drm_crtc *new_crtc;
9a935856
DV		 8918 struct intel_connector *connector;
8919 struct intel_encoder *encoder;
2e431051 8920 int count, ro;
50f56119 8921
9abdda74 8922 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 8923 * of connectors. For paranoia, double-check this. */
8924 WARN_ON(!set->fb && (set->num_connectors != 0));
8925 WARN_ON(set->fb && (set->num_connectors == 0));
8926
50f56119 8927 count = 0;
9a935856
DV		 8928 list_for_each_entry(connector, &dev->mode_config.connector_list,
8929 base.head) {
8930 /* Otherwise traverse passed in connector list and get encoders
8931 * for them. */
50f56119 8932 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 8933 if (set->connectors[ro] == &connector->base) {
8934 connector->new_encoder = connector->encoder;
50f56119
DV		 8935 break;
8936 }
8937 }
8938
9a935856
DV		 8939 /* If we disable the crtc, disable all its connectors. Also, if
8940 * the connector is on the changing crtc but not on the new
8941 * connector list, disable it. */
8942 if ((!set->fb || ro == set->num_connectors) &&
8943 connector->base.encoder &&
8944 connector->base.encoder->crtc == set->crtc) {
8945 connector->new_encoder = NULL;
8946
8947 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8948 connector->base.base.id,
8949 drm_get_connector_name(&connector->base));
8950 }
8951
8952
8953 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8954 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8955 config->mode_changed = true;
50f56119
DV		 8956 }
8957 }
9a935856 8958 /* connector->new_encoder is now updated for all connectors. */
50f56119 8959
9a935856 8960 /* Update crtc of enabled connectors. */
50f56119 8961 count = 0;
9a935856
DV		 8962 list_for_each_entry(connector, &dev->mode_config.connector_list,
8963 base.head) {
8964 if (!connector->new_encoder)
50f56119
DV		 8965 continue;
8966
9a935856 8967 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8968
8969 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8970 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8971 new_crtc = set->crtc;
8972 }
8973
8974 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8975 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8976 new_crtc)) {
5e2b584e 8977 return -EINVAL;
50f56119 8978 }
9a935856
DV		 8979 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8980
8981 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8982 connector->base.base.id,
8983 drm_get_connector_name(&connector->base),
8984 new_crtc->base.id);
8985 }
8986
8987 /* Check for any encoders that needs to be disabled. */
8988 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8989 base.head) {
8990 list_for_each_entry(connector,
8991 &dev->mode_config.connector_list,
8992 base.head) {
8993 if (connector->new_encoder == encoder) {
8994 WARN_ON(!connector->new_encoder->new_crtc);
8995
8996 goto next_encoder;
8997 }
8998 }
8999 encoder->new_crtc = NULL;
9000next_encoder:
9001 /* Only now check for crtc changes so we don't miss encoders
9002 * that will be disabled. */
9003 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 9004 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 9005 config->mode_changed = true;
50f56119
DV		 9006 }
9007 }
9a935856 9008 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 9009
2e431051
DV		 9010 return 0;
9011}
9012
9013static int intel_crtc_set_config(struct drm_mode_set *set)
9014{
9015 struct drm_device *dev;
2e431051
DV		 9016 struct drm_mode_set save_set;
9017 struct intel_set_config *config;
9018 int ret;
2e431051 9019
8d3e375e
DV		 9020 BUG_ON(!set);
9021 BUG_ON(!set->crtc);
9022 BUG_ON(!set->crtc->helper_private);
2e431051 9023
7e53f3a4
DV		 9024 /* Enforce sane interface api - has been abused by the fb helper. */
9025 BUG_ON(!set->mode && set->fb);
9026 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 9027
2e431051
DV		 9028 if (set->fb) {
9029 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9030 set->crtc->base.id, set->fb->base.id,
9031 (int)set->num_connectors, set->x, set->y);
9032 } else {
9033 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 9034 }
9035
9036 dev = set->crtc->dev;
9037
9038 ret = -ENOMEM;
9039 config = kzalloc(sizeof(*config), GFP_KERNEL);
9040 if (!config)
9041 goto out_config;
9042
9043 ret = intel_set_config_save_state(dev, config);
9044 if (ret)
9045 goto out_config;
9046
9047 save_set.crtc = set->crtc;
9048 save_set.mode = &set->crtc->mode;
9049 save_set.x = set->crtc->x;
9050 save_set.y = set->crtc->y;
9051 save_set.fb = set->crtc->fb;
9052
9053 /* Compute whether we need a full modeset, only an fb base update or no
9054 * change at all. In the future we might also check whether only the
9055 * mode changed, e.g. for LVDS where we only change the panel fitter in
9056 * such cases. */
9057 intel_set_config_compute_mode_changes(set, config);
9058
9a935856 9059 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 9060 if (ret)
9061 goto fail;
9062
5e2b584e 9063 if (config->mode_changed) {
c0c36b94
CW		 9064 ret = intel_set_mode(set->crtc, set->mode,
9065 set->x, set->y, set->fb);
5e2b584e 9066 } else if (config->fb_changed) {
4878cae2
VS		 9067 intel_crtc_wait_for_pending_flips(set->crtc);
9068
4f660f49 9069 ret = intel_pipe_set_base(set->crtc,
94352cf9 9070 set->x, set->y, set->fb);
50f56119
DV		 9071 }
9072
2d05eae1 9073 if (ret) {
bf67dfeb
DV		 9074 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9075 set->crtc->base.id, ret);
50f56119 9076fail:
2d05eae1 9077 intel_set_config_restore_state(dev, config);
50f56119 9078
2d05eae1
CW		 9079 /* Try to restore the config */
9080 if (config->mode_changed &&
9081 intel_set_mode(save_set.crtc, save_set.mode,
9082 save_set.x, save_set.y, save_set.fb))
9083 DRM_ERROR("failed to restore config after modeset failure\n");
9084 }
50f56119 9085
d9e55608
DV		 9086out_config:
9087 intel_set_config_free(config);
50f56119
DV		 9088 return ret;
9089}
f6e5b160
CW		 9090
9091static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 9092 .cursor_set = intel_crtc_cursor_set,
9093 .cursor_move = intel_crtc_cursor_move,
9094 .gamma_set = intel_crtc_gamma_set,
50f56119 9095 .set_config = intel_crtc_set_config,
f6e5b160
CW		 9096 .destroy = intel_crtc_destroy,
9097 .page_flip = intel_crtc_page_flip,
9098};
9099
79f689aa
PZ		 9100static void intel_cpu_pll_init(struct drm_device *dev)
9101{
affa9354 9102 if (HAS_DDI(dev))
79f689aa
PZ		 9103 intel_ddi_pll_init(dev);
9104}
9105
5358901f
DV		 9106static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9107 struct intel_shared_dpll *pll,
9108 struct intel_dpll_hw_state *hw_state)
ee7b9f93 9109{
5358901f 9110 uint32_t val;
ee7b9f93 9111
5358901f 9112 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 9113 hw_state->dpll = val;
9114 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9115 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 9116
9117 return val & DPLL_VCO_ENABLE;
9118}
9119
15bdd4cf
DV		 9120static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9121 struct intel_shared_dpll *pll)
9122{
9123 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9124 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9125}
9126
e7b903d2
DV		 9127static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9128 struct intel_shared_dpll *pll)
9129{
e7b903d2
DV		 9130 /* PCH refclock must be enabled first */
9131 assert_pch_refclk_enabled(dev_priv);
9132
15bdd4cf
DV		 9133 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9134
9135 /* Wait for the clocks to stabilize. */
9136 POSTING_READ(PCH_DPLL(pll->id));
9137 udelay(150);
9138
9139 /* The pixel multiplier can only be updated once the
9140 * DPLL is enabled and the clocks are stable.
9141 *
9142 * So write it again.
9143 */
9144 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9145 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9146 udelay(200);
9147}
9148
9149static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9150 struct intel_shared_dpll *pll)
9151{
9152 struct drm_device *dev = dev_priv->dev;
9153 struct intel_crtc *crtc;
e7b903d2
DV		 9154
9155 /* Make sure no transcoder isn't still depending on us. */
9156 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9157 if (intel_crtc_to_shared_dpll(crtc) == pll)
9158 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 9159 }
9160
15bdd4cf
DV		 9161 I915_WRITE(PCH_DPLL(pll->id), 0);
9162 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9163 udelay(200);
9164}
9165
46edb027
DV		 9166static char *ibx_pch_dpll_names[] = {
9167 "PCH DPLL A",
9168 "PCH DPLL B",
9169};
9170
7c74ade1 9171static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 9172{
e7b903d2 9173 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 9174 int i;
9175
7c74ade1 9176 dev_priv->num_shared_dpll = 2;
ee7b9f93 9177
e72f9fbf 9178 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 9179 dev_priv->shared_dplls[i].id = i;
9180 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 9181 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 9182 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9183 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 9184 dev_priv->shared_dplls[i].get_hw_state =
9185 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 9186 }
9187}
9188
7c74ade1
DV		 9189static void intel_shared_dpll_init(struct drm_device *dev)
9190{
e7b903d2 9191 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1
DV		 9192
9193 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9194 ibx_pch_dpll_init(dev);
9195 else
9196 dev_priv->num_shared_dpll = 0;
9197
9198 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9199 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9200 dev_priv->num_shared_dpll);
9201}
9202
b358d0a6 9203static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 9204{
22fd0fab 9205 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 9206 struct intel_crtc *intel_crtc;
9207 int i;
9208
9209 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
9210 if (intel_crtc == NULL)
9211 return;
9212
9213 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9214
9215 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 9216 for (i = 0; i < 256; i++) {
9217 intel_crtc->lut_r[i] = i;
9218 intel_crtc->lut_g[i] = i;
9219 intel_crtc->lut_b[i] = i;
9220 }
9221
80824003
JB		 9222 /* Swap pipes & planes for FBC on pre-965 */
9223 intel_crtc->pipe = pipe;
9224 intel_crtc->plane = pipe;
e2e767ab 9225 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 9226 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 9227 intel_crtc->plane = !pipe;
80824003
JB		 9228 }
9229
22fd0fab
JB		 9230 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9231 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9232 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9233 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9234
79e53945 9235 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 9236}
9237
08d7b3d1 9238int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 9239 struct drm_file *file)
08d7b3d1 9240{
08d7b3d1 9241 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 9242 struct drm_mode_object *drmmode_obj;
9243 struct intel_crtc *crtc;
08d7b3d1 9244
1cff8f6b
DV		 9245 if (!drm_core_check_feature(dev, DRIVER_MODESET))
9246 return -ENODEV;
08d7b3d1 9247
c05422d5
DV		 9248 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9249 DRM_MODE_OBJECT_CRTC);
08d7b3d1 9250
c05422d5 9251 if (!drmmode_obj) {
08d7b3d1
CW		 9252 DRM_ERROR("no such CRTC id\n");
9253 return -EINVAL;
9254 }
9255
c05422d5
DV		 9256 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9257 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 9258
c05422d5 9259 return 0;
08d7b3d1
CW		 9260}
9261
66a9278e 9262static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 9263{
66a9278e
DV		 9264 struct drm_device *dev = encoder->base.dev;
9265 struct intel_encoder *source_encoder;
79e53945 9266 int index_mask = 0;
79e53945
JB		 9267 int entry = 0;
9268
66a9278e
DV		 9269 list_for_each_entry(source_encoder,
9270 &dev->mode_config.encoder_list, base.head) {
9271
9272 if (encoder == source_encoder)
79e53945 9273 index_mask |= (1 << entry);
66a9278e
DV		 9274
9275 /* Intel hw has only one MUX where enocoders could be cloned. */
9276 if (encoder->cloneable && source_encoder->cloneable)
9277 index_mask |= (1 << entry);
9278
79e53945
JB		 9279 entry++;
9280 }
4ef69c7a 9281
79e53945
JB		 9282 return index_mask;
9283}
9284
4d302442
CW		 9285static bool has_edp_a(struct drm_device *dev)
9286{
9287 struct drm_i915_private *dev_priv = dev->dev_private;
9288
9289 if (!IS_MOBILE(dev))
9290 return false;
9291
9292 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9293 return false;
9294
9295 if (IS_GEN5(dev) &&
9296 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9297 return false;
9298
9299 return true;
9300}
9301
79e53945
JB		 9302static void intel_setup_outputs(struct drm_device *dev)
9303{
725e30ad 9304 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 9305 struct intel_encoder *encoder;
cb0953d7 9306 bool dpd_is_edp = false;
79e53945 9307
c9093354 9308 intel_lvds_init(dev);
79e53945 9309
c40c0f5b 9310 if (!IS_ULT(dev))
79935fca 9311 intel_crt_init(dev);
cb0953d7 9312
affa9354 9313 if (HAS_DDI(dev)) {
0e72a5b5
ED		 9314 int found;
9315
9316 /* Haswell uses DDI functions to detect digital outputs */
9317 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9318 /* DDI A only supports eDP */
9319 if (found)
9320 intel_ddi_init(dev, PORT_A);
9321
9322 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9323 * register */
9324 found = I915_READ(SFUSE_STRAP);
9325
9326 if (found & SFUSE_STRAP_DDIB_DETECTED)
9327 intel_ddi_init(dev, PORT_B);
9328 if (found & SFUSE_STRAP_DDIC_DETECTED)
9329 intel_ddi_init(dev, PORT_C);
9330 if (found & SFUSE_STRAP_DDID_DETECTED)
9331 intel_ddi_init(dev, PORT_D);
9332 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 9333 int found;
270b3042
DV		 9334 dpd_is_edp = intel_dpd_is_edp(dev);
9335
9336 if (has_edp_a(dev))
9337 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 9338
dc0fa718 9339 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 9340 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 9341 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 9342 if (!found)
e2debe91 9343 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 9344 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 9345 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 9346 }
9347
dc0fa718 9348 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 9349 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 9350
dc0fa718 9351 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 9352 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 9353
5eb08b69 9354 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 9355 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 9356
270b3042 9357 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 9358 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 9359 } else if (IS_VALLEYVIEW(dev)) {
19c03924 9360 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 9361 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9362 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 9363
dc0fa718 9364 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 9365 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9366 PORT_B);
67cfc203
VS		 9367 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9368 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 9369 }
103a196f 9370 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 9371 bool found = false;
7d57382e 9372
e2debe91 9373 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9374 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 9375 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 9376 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9377 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 9378 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 9379 }
27185ae1 9380
e7281eab 9381 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9382 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 9383 }
13520b05
KH		 9384
9385 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 9386
e2debe91 9387 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9388 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 9389 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 9390 }
27185ae1 9391
e2debe91 9392 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 9393
b01f2c3a
JB		 9394 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9395 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 9396 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 9397 }
e7281eab 9398 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9399 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 9400 }
27185ae1 9401
b01f2c3a 9402 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 9403 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 9404 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 9405 } else if (IS_GEN2(dev))
79e53945
JB		 9406 intel_dvo_init(dev);
9407
103a196f 9408 if (SUPPORTS_TV(dev))
79e53945
JB		 9409 intel_tv_init(dev);
9410
4ef69c7a
CW		 9411 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9412 encoder->base.possible_crtcs = encoder->crtc_mask;
9413 encoder->base.possible_clones =
66a9278e 9414 intel_encoder_clones(encoder);
79e53945 9415 }
47356eb6 9416
dde86e2d 9417 intel_init_pch_refclk(dev);
270b3042
DV		 9418
9419 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 9420}
9421
9422static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9423{
9424 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 9425
9426 drm_framebuffer_cleanup(fb);
05394f39 9427 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 9428
9429 kfree(intel_fb);
9430}
9431
9432static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 9433 struct drm_file *file,
79e53945
JB		 9434 unsigned int *handle)
9435{
9436 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 9437 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 9438
05394f39 9439 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 9440}
9441
9442static const struct drm_framebuffer_funcs intel_fb_funcs = {
9443 .destroy = intel_user_framebuffer_destroy,
9444 .create_handle = intel_user_framebuffer_create_handle,
9445};
9446
38651674
DA		 9447int intel_framebuffer_init(struct drm_device *dev,
9448 struct intel_framebuffer *intel_fb,
308e5bcb 9449 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 9450 struct drm_i915_gem_object *obj)
79e53945 9451{
a35cdaa0 9452 int pitch_limit;
79e53945
JB		 9453 int ret;
9454
c16ed4be
CW		 9455 if (obj->tiling_mode == I915_TILING_Y) {
9456 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 9457 return -EINVAL;
c16ed4be 9458 }
57cd6508 9459
c16ed4be
CW		 9460 if (mode_cmd->pitches[0] & 63) {
9461 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9462 mode_cmd->pitches[0]);
57cd6508 9463 return -EINVAL;
c16ed4be 9464 }
57cd6508 9465
a35cdaa0
CW		 9466 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9467 pitch_limit = 32*1024;
9468 } else if (INTEL_INFO(dev)->gen >= 4) {
9469 if (obj->tiling_mode)
9470 pitch_limit = 16*1024;
9471 else
9472 pitch_limit = 32*1024;
9473 } else if (INTEL_INFO(dev)->gen >= 3) {
9474 if (obj->tiling_mode)
9475 pitch_limit = 8*1024;
9476 else
9477 pitch_limit = 16*1024;
9478 } else
9479 /* XXX DSPC is limited to 4k tiled */
9480 pitch_limit = 8*1024;
9481
9482 if (mode_cmd->pitches[0] > pitch_limit) {
9483 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9484 obj->tiling_mode ? "tiled" : "linear",
9485 mode_cmd->pitches[0], pitch_limit);
5d7bd705 9486 return -EINVAL;
c16ed4be 9487 }
5d7bd705
VS		 9488
9489 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 9490 mode_cmd->pitches[0] != obj->stride) {
9491 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9492 mode_cmd->pitches[0], obj->stride);
5d7bd705 9493 return -EINVAL;
c16ed4be 9494 }
5d7bd705 9495
57779d06 9496 /* Reject formats not supported by any plane early. */
308e5bcb 9497 switch (mode_cmd->pixel_format) {
57779d06 9498 case DRM_FORMAT_C8:
04b3924d
VS		 9499 case DRM_FORMAT_RGB565:
9500 case DRM_FORMAT_XRGB8888:
9501 case DRM_FORMAT_ARGB8888:
57779d06
VS		 9502 break;
9503 case DRM_FORMAT_XRGB1555:
9504 case DRM_FORMAT_ARGB1555:
c16ed4be 9505 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 9506 DRM_DEBUG("unsupported pixel format: %s\n",
9507 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9508 return -EINVAL;
c16ed4be 9509 }
57779d06
VS		 9510 break;
9511 case DRM_FORMAT_XBGR8888:
9512 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 9513 case DRM_FORMAT_XRGB2101010:
9514 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 9515 case DRM_FORMAT_XBGR2101010:
9516 case DRM_FORMAT_ABGR2101010:
c16ed4be 9517 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 9518 DRM_DEBUG("unsupported pixel format: %s\n",
9519 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9520 return -EINVAL;
c16ed4be 9521 }
b5626747 9522 break;
04b3924d
VS		 9523 case DRM_FORMAT_YUYV:
9524 case DRM_FORMAT_UYVY:
9525 case DRM_FORMAT_YVYU:
9526 case DRM_FORMAT_VYUY:
c16ed4be 9527 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 9528 DRM_DEBUG("unsupported pixel format: %s\n",
9529 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9530 return -EINVAL;
c16ed4be 9531 }
57cd6508
CW		 9532 break;
9533 default:
4ee62c76
VS		 9534 DRM_DEBUG("unsupported pixel format: %s\n",
9535 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 9536 return -EINVAL;
9537 }
9538
90f9a336
VS		 9539 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9540 if (mode_cmd->offsets[0] != 0)
9541 return -EINVAL;
9542
c7d73f6a
DV		 9543 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9544 intel_fb->obj = obj;
9545
79e53945
JB		 9546 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9547 if (ret) {
9548 DRM_ERROR("framebuffer init failed %d\n", ret);
9549 return ret;
9550 }
9551
79e53945
JB		 9552 return 0;
9553}
9554
79e53945
JB		 9555static struct drm_framebuffer *
9556intel_user_framebuffer_create(struct drm_device *dev,
9557 struct drm_file *filp,
308e5bcb 9558 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 9559{
05394f39 9560 struct drm_i915_gem_object *obj;
79e53945 9561
308e5bcb
JB		 9562 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9563 mode_cmd->handles[0]));
c8725226 9564 if (&obj->base == NULL)
cce13ff7 9565 return ERR_PTR(-ENOENT);
79e53945 9566
d2dff872 9567 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 9568}
9569
79e53945 9570static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 9571 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 9572 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 9573};
9574
e70236a8
JB		 9575/* Set up chip specific display functions */
9576static void intel_init_display(struct drm_device *dev)
9577{
9578 struct drm_i915_private *dev_priv = dev->dev_private;
9579
ee9300bb
DV		 9580 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9581 dev_priv->display.find_dpll = g4x_find_best_dpll;
9582 else if (IS_VALLEYVIEW(dev))
9583 dev_priv->display.find_dpll = vlv_find_best_dpll;
9584 else if (IS_PINEVIEW(dev))
9585 dev_priv->display.find_dpll = pnv_find_best_dpll;
9586 else
9587 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9588
affa9354 9589 if (HAS_DDI(dev)) {
0e8ffe1b 9590 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 9591 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 9592 dev_priv->display.crtc_enable = haswell_crtc_enable;
9593 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 9594 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 9595 dev_priv->display.update_plane = ironlake_update_plane;
9596 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 9597 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f1f644dc 9598 dev_priv->display.get_clock = ironlake_crtc_clock_get;
f564048e 9599 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 9600 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9601 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 9602 dev_priv->display.off = ironlake_crtc_off;
17638cd6 9603 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 9604 } else if (IS_VALLEYVIEW(dev)) {
9605 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f1f644dc 9606 dev_priv->display.get_clock = i9xx_crtc_clock_get;
89b667f8
JB		 9607 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9608 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9609 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9610 dev_priv->display.off = i9xx_crtc_off;
9611 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9612 } else {
0e8ffe1b 9613 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f1f644dc 9614 dev_priv->display.get_clock = i9xx_crtc_clock_get;
f564048e 9615 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 9616 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9617 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 9618 dev_priv->display.off = i9xx_crtc_off;
17638cd6 9619 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9620 }
e70236a8 9621
e70236a8 9622 /* Returns the core display clock speed */
25eb05fc
JB		 9623 if (IS_VALLEYVIEW(dev))
9624 dev_priv->display.get_display_clock_speed =
9625 valleyview_get_display_clock_speed;
9626 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 9627 dev_priv->display.get_display_clock_speed =
9628 i945_get_display_clock_speed;
9629 else if (IS_I915G(dev))
9630 dev_priv->display.get_display_clock_speed =
9631 i915_get_display_clock_speed;
257a7ffc 9632 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 9633 dev_priv->display.get_display_clock_speed =
9634 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 9635 else if (IS_PINEVIEW(dev))
9636 dev_priv->display.get_display_clock_speed =
9637 pnv_get_display_clock_speed;
e70236a8
JB		 9638 else if (IS_I915GM(dev))
9639 dev_priv->display.get_display_clock_speed =
9640 i915gm_get_display_clock_speed;
9641 else if (IS_I865G(dev))
9642 dev_priv->display.get_display_clock_speed =
9643 i865_get_display_clock_speed;
f0f8a9ce 9644 else if (IS_I85X(dev))
e70236a8
JB		 9645 dev_priv->display.get_display_clock_speed =
9646 i855_get_display_clock_speed;
9647 else /* 852, 830 */
9648 dev_priv->display.get_display_clock_speed =
9649 i830_get_display_clock_speed;
9650
7f8a8569 9651 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 9652 if (IS_GEN5(dev)) {
674cf967 9653 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 9654 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 9655 } else if (IS_GEN6(dev)) {
674cf967 9656 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 9657 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 9658 } else if (IS_IVYBRIDGE(dev)) {
9659 /* FIXME: detect B0+ stepping and use auto training */
9660 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 9661 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 9662 dev_priv->display.modeset_global_resources =
9663 ivb_modeset_global_resources;
c82e4d26
ED		 9664 } else if (IS_HASWELL(dev)) {
9665 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 9666 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 9667 dev_priv->display.modeset_global_resources =
9668 haswell_modeset_global_resources;
a0e63c22 9669 }
6067aaea 9670 } else if (IS_G4X(dev)) {
e0dac65e 9671 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 9672 }
8c9f3aaf
JB		 9673
9674 /* Default just returns -ENODEV to indicate unsupported */
9675 dev_priv->display.queue_flip = intel_default_queue_flip;
9676
9677 switch (INTEL_INFO(dev)->gen) {
9678 case 2:
9679 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9680 break;
9681
9682 case 3:
9683 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9684 break;
9685
9686 case 4:
9687 case 5:
9688 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9689 break;
9690
9691 case 6:
9692 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9693 break;
7c9017e5
JB		 9694 case 7:
9695 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9696 break;
8c9f3aaf 9697 }
e70236a8
JB		 9698}
9699
b690e96c
JB		 9700/*
9701 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9702 * resume, or other times. This quirk makes sure that's the case for
9703 * affected systems.
9704 */
0206e353 9705static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 9706{
9707 struct drm_i915_private *dev_priv = dev->dev_private;
9708
9709 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 9710 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 9711}
9712
435793df
KP		 9713/*
9714 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9715 */
9716static void quirk_ssc_force_disable(struct drm_device *dev)
9717{
9718 struct drm_i915_private *dev_priv = dev->dev_private;
9719 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 9720 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 9721}
9722
4dca20ef 9723/*
5a15ab5b
CE		 9724 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9725 * brightness value
4dca20ef
CE		 9726 */
9727static void quirk_invert_brightness(struct drm_device *dev)
9728{
9729 struct drm_i915_private *dev_priv = dev->dev_private;
9730 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 9731 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 9732}
9733
e85843be
KM		 9734/*
9735 * Some machines (Dell XPS13) suffer broken backlight controls if
9736 * BLM_PCH_PWM_ENABLE is set.
9737 */
9738static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
9739{
9740 struct drm_i915_private *dev_priv = dev->dev_private;
9741 dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
9742 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
9743}
9744
b690e96c
JB		 9745struct intel_quirk {
9746 int device;
9747 int subsystem_vendor;
9748 int subsystem_device;
9749 void (*hook)(struct drm_device *dev);
9750};
9751
5f85f176
EE		 9752/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9753struct intel_dmi_quirk {
9754 void (*hook)(struct drm_device *dev);
9755 const struct dmi_system_id (*dmi_id_list)[];
9756};
9757
9758static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9759{
9760 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9761 return 1;
9762}
9763
9764static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9765 {
9766 .dmi_id_list = &(const struct dmi_system_id[]) {
9767 {
9768 .callback = intel_dmi_reverse_brightness,
9769 .ident = "NCR Corporation",
9770 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9771 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9772 },
9773 },
9774 { } /* terminating entry */
9775 },
9776 .hook = quirk_invert_brightness,
9777 },
9778};
9779
c43b5634 9780static struct intel_quirk intel_quirks[] = {
b690e96c 9781 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 9782 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 9783
b690e96c
JB		 9784 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9785 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9786
b690e96c
JB		 9787 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9788 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9789
ccd0d36e 9790 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 9791 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 9792 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 9793
9794 /* Lenovo U160 cannot use SSC on LVDS */
9795 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 9796
9797 /* Sony Vaio Y cannot use SSC on LVDS */
9798 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 9799
9800 /* Acer Aspire 5734Z must invert backlight brightness */
9801 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 9802
9803 /* Acer/eMachines G725 */
9804 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 9805
9806 /* Acer/eMachines e725 */
9807 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 9808
9809 /* Acer/Packard Bell NCL20 */
9810 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 9811
9812 /* Acer Aspire 4736Z */
9813 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
e85843be
KM		 9814
9815 /* Dell XPS13 HD Sandy Bridge */
9816 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
9817 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
9818 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
b690e96c
JB		 9819};
9820
9821static void intel_init_quirks(struct drm_device *dev)
9822{
9823 struct pci_dev *d = dev->pdev;
9824 int i;
9825
9826 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9827 struct intel_quirk *q = &intel_quirks[i];
9828
9829 if (d->device == q->device &&
9830 (d->subsystem_vendor == q->subsystem_vendor ||
9831 q->subsystem_vendor == PCI_ANY_ID) &&
9832 (d->subsystem_device == q->subsystem_device ||
9833 q->subsystem_device == PCI_ANY_ID))
9834 q->hook(dev);
9835 }
5f85f176
EE		 9836 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9837 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9838 intel_dmi_quirks[i].hook(dev);
9839 }
b690e96c
JB		 9840}
9841
9cce37f4
JB		 9842/* Disable the VGA plane that we never use */
9843static void i915_disable_vga(struct drm_device *dev)
9844{
9845 struct drm_i915_private *dev_priv = dev->dev_private;
9846 u8 sr1;
766aa1c4 9847 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 9848
9849 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 9850 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 9851 sr1 = inb(VGA_SR_DATA);
9852 outb(sr1 | 1<<5, VGA_SR_DATA);
9853 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9854 udelay(300);
9855
9856 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9857 POSTING_READ(vga_reg);
9858}
9859
f817586c
DV		 9860void intel_modeset_init_hw(struct drm_device *dev)
9861{
fa42e23c 9862 intel_init_power_well(dev);
0232e927 9863
a8f78b58
ED		 9864 intel_prepare_ddi(dev);
9865
f817586c
DV		 9866 intel_init_clock_gating(dev);
9867
79f5b2c7 9868 mutex_lock(&dev->struct_mutex);
8090c6b9 9869 intel_enable_gt_powersave(dev);
79f5b2c7 9870 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 9871}
9872
7d708ee4
ID		 9873void intel_modeset_suspend_hw(struct drm_device *dev)
9874{
9875 intel_suspend_hw(dev);
9876}
9877
79e53945
JB		 9878void intel_modeset_init(struct drm_device *dev)
9879{
652c393a 9880 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 9881 int i, j, ret;
79e53945
JB		 9882
9883 drm_mode_config_init(dev);
9884
9885 dev->mode_config.min_width = 0;
9886 dev->mode_config.min_height = 0;
9887
019d96cb
DA		 9888 dev->mode_config.preferred_depth = 24;
9889 dev->mode_config.prefer_shadow = 1;
9890
e6ecefaa 9891 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 9892
b690e96c
JB		 9893 intel_init_quirks(dev);
9894
1fa61106
ED		 9895 intel_init_pm(dev);
9896
e3c74757
BW		 9897 if (INTEL_INFO(dev)->num_pipes == 0)
9898 return;
9899
e70236a8
JB		 9900 intel_init_display(dev);
9901
a6c45cf0
CW		 9902 if (IS_GEN2(dev)) {
9903 dev->mode_config.max_width = 2048;
9904 dev->mode_config.max_height = 2048;
9905 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9906 dev->mode_config.max_width = 4096;
9907 dev->mode_config.max_height = 4096;
79e53945 9908 } else {
a6c45cf0
CW		 9909 dev->mode_config.max_width = 8192;
9910 dev->mode_config.max_height = 8192;
79e53945 9911 }
5d4545ae 9912 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 9913
28c97730 9914 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 9915 INTEL_INFO(dev)->num_pipes,
9916 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 9917
08e2a7de 9918 for_each_pipe(i) {
79e53945 9919 intel_crtc_init(dev, i);
7f1f3851
JB		 9920 for (j = 0; j < dev_priv->num_plane; j++) {
9921 ret = intel_plane_init(dev, i, j);
9922 if (ret)
06da8da2
VS		 9923 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9924 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 9925 }
79e53945
JB		 9926 }
9927
79f689aa 9928 intel_cpu_pll_init(dev);
e72f9fbf 9929 intel_shared_dpll_init(dev);
ee7b9f93 9930
9cce37f4
JB		 9931 /* Just disable it once at startup */
9932 i915_disable_vga(dev);
79e53945 9933 intel_setup_outputs(dev);
11be49eb
CW		 9934
9935 /* Just in case the BIOS is doing something questionable. */
9936 intel_disable_fbc(dev);
2c7111db
CW		 9937}
9938
24929352
DV		 9939static void
9940intel_connector_break_all_links(struct intel_connector *connector)
9941{
9942 connector->base.dpms = DRM_MODE_DPMS_OFF;
9943 connector->base.encoder = NULL;
9944 connector->encoder->connectors_active = false;
9945 connector->encoder->base.crtc = NULL;
9946}
9947
7fad798e
DV		 9948static void intel_enable_pipe_a(struct drm_device *dev)
9949{
9950 struct intel_connector *connector;
9951 struct drm_connector *crt = NULL;
9952 struct intel_load_detect_pipe load_detect_temp;
9953
9954 /* We can't just switch on the pipe A, we need to set things up with a
9955 * proper mode and output configuration. As a gross hack, enable pipe A
9956 * by enabling the load detect pipe once. */
9957 list_for_each_entry(connector,
9958 &dev->mode_config.connector_list,
9959 base.head) {
9960 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9961 crt = &connector->base;
9962 break;
9963 }
9964 }
9965
9966 if (!crt)
9967 return;
9968
9969 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9970 intel_release_load_detect_pipe(crt, &load_detect_temp);
9971
652c393a 9972
7fad798e
DV		 9973}
9974
fa555837
DV		 9975static bool
9976intel_check_plane_mapping(struct intel_crtc *crtc)
9977{
7eb552ae
BW		 9978 struct drm_device *dev = crtc->base.dev;
9979 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 9980 u32 reg, val;
9981
7eb552ae 9982 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 9983 return true;
9984
9985 reg = DSPCNTR(!crtc->plane);
9986 val = I915_READ(reg);
9987
9988 if ((val & DISPLAY_PLANE_ENABLE) &&
9989 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9990 return false;
9991
9992 return true;
9993}
9994
24929352
DV		 9995static void intel_sanitize_crtc(struct intel_crtc *crtc)
9996{
9997 struct drm_device *dev = crtc->base.dev;
9998 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 9999 u32 reg;
24929352 10000
24929352 10001 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 10002 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 10003 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10004
10005 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 10006 * disable the crtc (and hence change the state) if it is wrong. Note
10007 * that gen4+ has a fixed plane -> pipe mapping. */
10008 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 10009 struct intel_connector *connector;
10010 bool plane;
10011
24929352
DV		 10012 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10013 crtc->base.base.id);
10014
10015 /* Pipe has the wrong plane attached and the plane is active.
10016 * Temporarily change the plane mapping and disable everything
10017 * ... */
10018 plane = crtc->plane;
10019 crtc->plane = !plane;
10020 dev_priv->display.crtc_disable(&crtc->base);
10021 crtc->plane = plane;
10022
10023 /* ... and break all links. */
10024 list_for_each_entry(connector, &dev->mode_config.connector_list,
10025 base.head) {
10026 if (connector->encoder->base.crtc != &crtc->base)
10027 continue;
10028
10029 intel_connector_break_all_links(connector);
10030 }
10031
10032 WARN_ON(crtc->active);
10033 crtc->base.enabled = false;
10034 }
24929352 10035
7fad798e
DV		 10036 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10037 crtc->pipe == PIPE_A && !crtc->active) {
10038 /* BIOS forgot to enable pipe A, this mostly happens after
10039 * resume. Force-enable the pipe to fix this, the update_dpms
10040 * call below we restore the pipe to the right state, but leave
10041 * the required bits on. */
10042 intel_enable_pipe_a(dev);
10043 }
10044
24929352
DV		 10045 /* Adjust the state of the output pipe according to whether we
10046 * have active connectors/encoders. */
10047 intel_crtc_update_dpms(&crtc->base);
10048
10049 if (crtc->active != crtc->base.enabled) {
10050 struct intel_encoder *encoder;
10051
10052 /* This can happen either due to bugs in the get_hw_state
10053 * functions or because the pipe is force-enabled due to the
10054 * pipe A quirk. */
10055 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10056 crtc->base.base.id,
10057 crtc->base.enabled ? "enabled" : "disabled",
10058 crtc->active ? "enabled" : "disabled");
10059
10060 crtc->base.enabled = crtc->active;
10061
10062 /* Because we only establish the connector -> encoder ->
10063 * crtc links if something is active, this means the
10064 * crtc is now deactivated. Break the links. connector
10065 * -> encoder links are only establish when things are
10066 * actually up, hence no need to break them. */
10067 WARN_ON(crtc->active);
10068
10069 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10070 WARN_ON(encoder->connectors_active);
10071 encoder->base.crtc = NULL;
10072 }
10073 }
10074}
10075
10076static void intel_sanitize_encoder(struct intel_encoder *encoder)
10077{
10078 struct intel_connector *connector;
10079 struct drm_device *dev = encoder->base.dev;
10080
10081 /* We need to check both for a crtc link (meaning that the
10082 * encoder is active and trying to read from a pipe) and the
10083 * pipe itself being active. */
10084 bool has_active_crtc = encoder->base.crtc &&
10085 to_intel_crtc(encoder->base.crtc)->active;
10086
10087 if (encoder->connectors_active && !has_active_crtc) {
10088 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10089 encoder->base.base.id,
10090 drm_get_encoder_name(&encoder->base));
10091
10092 /* Connector is active, but has no active pipe. This is
10093 * fallout from our resume register restoring. Disable
10094 * the encoder manually again. */
10095 if (encoder->base.crtc) {
10096 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10097 encoder->base.base.id,
10098 drm_get_encoder_name(&encoder->base));
10099 encoder->disable(encoder);
10100 }
10101
10102 /* Inconsistent output/port/pipe state happens presumably due to
10103 * a bug in one of the get_hw_state functions. Or someplace else
10104 * in our code, like the register restore mess on resume. Clamp
10105 * things to off as a safer default. */
10106 list_for_each_entry(connector,
10107 &dev->mode_config.connector_list,
10108 base.head) {
10109 if (connector->encoder != encoder)
10110 continue;
10111
10112 intel_connector_break_all_links(connector);
10113 }
10114 }
10115 /* Enabled encoders without active connectors will be fixed in
10116 * the crtc fixup. */
10117}
10118
44cec740 10119void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 10120{
10121 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 10122 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 10123
10124 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
10125 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 10126 i915_disable_vga(dev);
0fde901f
KM		 10127 }
10128}
10129
30e984df 10130static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 10131{
10132 struct drm_i915_private *dev_priv = dev->dev_private;
10133 enum pipe pipe;
24929352
DV		 10134 struct intel_crtc *crtc;
10135 struct intel_encoder *encoder;
10136 struct intel_connector *connector;
5358901f 10137 int i;
24929352 10138
0e8ffe1b
DV		 10139 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10140 base.head) {
88adfff1 10141 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 10142
0e8ffe1b
DV		 10143 crtc->active = dev_priv->display.get_pipe_config(crtc,
10144 &crtc->config);
24929352
DV		 10145
10146 crtc->base.enabled = crtc->active;
10147
10148 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10149 crtc->base.base.id,
10150 crtc->active ? "enabled" : "disabled");
10151 }
10152
5358901f 10153 /* FIXME: Smash this into the new shared dpll infrastructure. */
affa9354 10154 if (HAS_DDI(dev))
6441ab5f
PZ		 10155 intel_ddi_setup_hw_pll_state(dev);
10156
5358901f
DV		 10157 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10158 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10159
10160 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10161 pll->active = 0;
10162 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10163 base.head) {
10164 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10165 pll->active++;
10166 }
10167 pll->refcount = pll->active;
10168
35c95375
DV		 10169 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10170 pll->name, pll->refcount, pll->on);
5358901f
DV		 10171 }
10172
24929352
DV		 10173 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10174 base.head) {
10175 pipe = 0;
10176
10177 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 10178 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10179 encoder->base.crtc = &crtc->base;
510d5f2f 10180 if (encoder->get_config)
045ac3b5 10181 encoder->get_config(encoder, &crtc->config);
24929352
DV		 10182 } else {
10183 encoder->base.crtc = NULL;
10184 }
10185
10186 encoder->connectors_active = false;
10187 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10188 encoder->base.base.id,
10189 drm_get_encoder_name(&encoder->base),
10190 encoder->base.crtc ? "enabled" : "disabled",
10191 pipe);
10192 }
10193
510d5f2f
JB		 10194 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10195 base.head) {
10196 if (!crtc->active)
10197 continue;
10198 if (dev_priv->display.get_clock)
10199 dev_priv->display.get_clock(crtc,
10200 &crtc->config);
10201 }
10202
24929352
DV		 10203 list_for_each_entry(connector, &dev->mode_config.connector_list,
10204 base.head) {
10205 if (connector->get_hw_state(connector)) {
10206 connector->base.dpms = DRM_MODE_DPMS_ON;
10207 connector->encoder->connectors_active = true;
10208 connector->base.encoder = &connector->encoder->base;
10209 } else {
10210 connector->base.dpms = DRM_MODE_DPMS_OFF;
10211 connector->base.encoder = NULL;
10212 }
10213 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10214 connector->base.base.id,
10215 drm_get_connector_name(&connector->base),
10216 connector->base.encoder ? "enabled" : "disabled");
10217 }
30e984df
DV		 10218}
10219
10220/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10221 * and i915 state tracking structures. */
10222void intel_modeset_setup_hw_state(struct drm_device *dev,
10223 bool force_restore)
10224{
10225 struct drm_i915_private *dev_priv = dev->dev_private;
10226 enum pipe pipe;
10227 struct drm_plane *plane;
10228 struct intel_crtc *crtc;
10229 struct intel_encoder *encoder;
35c95375 10230 int i;
30e984df
DV		 10231
10232 intel_modeset_readout_hw_state(dev);
24929352 10233
babea61d
JB		 10234 /*
10235 * Now that we have the config, copy it to each CRTC struct
10236 * Note that this could go away if we move to using crtc_config
10237 * checking everywhere.
10238 */
10239 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10240 base.head) {
10241 if (crtc->active && i915_fastboot) {
10242 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10243
10244 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10245 crtc->base.base.id);
10246 drm_mode_debug_printmodeline(&crtc->base.mode);
10247 }
10248 }
10249
24929352
DV		 10250 /* HW state is read out, now we need to sanitize this mess. */
10251 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10252 base.head) {
10253 intel_sanitize_encoder(encoder);
10254 }
10255
10256 for_each_pipe(pipe) {
10257 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10258 intel_sanitize_crtc(crtc);
c0b03411 10259 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 10260 }
9a935856 10261
35c95375
DV		 10262 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10263 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10264
10265 if (!pll->on || pll->active)
10266 continue;
10267
10268 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10269
10270 pll->disable(dev_priv, pll);
10271 pll->on = false;
10272 }
10273
45e2b5f6 10274 if (force_restore) {
f30da187
DV		 10275 /*
10276 * We need to use raw interfaces for restoring state to avoid
10277 * checking (bogus) intermediate states.
10278 */
45e2b5f6 10279 for_each_pipe(pipe) {
b5644d05
JB		 10280 struct drm_crtc *crtc =
10281 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 10282
10283 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10284 crtc->fb);
45e2b5f6 10285 }
b5644d05
JB		 10286 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
10287 intel_plane_restore(plane);
0fde901f
KM		 10288
10289 i915_redisable_vga(dev);
45e2b5f6
DV		 10290 } else {
10291 intel_modeset_update_staged_output_state(dev);
10292 }
8af6cf88
DV		 10293
10294 intel_modeset_check_state(dev);
2e938892
DV		 10295
10296 drm_mode_config_reset(dev);
2c7111db
CW		 10297}
10298
10299void intel_modeset_gem_init(struct drm_device *dev)
10300{
1833b134 10301 intel_modeset_init_hw(dev);
02e792fb
DV		 10302
10303 intel_setup_overlay(dev);
24929352 10304
45e2b5f6 10305 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 10306}
10307
10308void intel_modeset_cleanup(struct drm_device *dev)
10309{
652c393a
JB		 10310 struct drm_i915_private *dev_priv = dev->dev_private;
10311 struct drm_crtc *crtc;
10312 struct intel_crtc *intel_crtc;
10313
fd0c0642
DV		 10314 /*
10315 * Interrupts and polling as the first thing to avoid creating havoc.
10316 * Too much stuff here (turning of rps, connectors, ...) would
10317 * experience fancy races otherwise.
10318 */
10319 drm_irq_uninstall(dev);
10320 cancel_work_sync(&dev_priv->hotplug_work);
10321 /*
10322 * Due to the hpd irq storm handling the hotplug work can re-arm the
10323 * poll handlers. Hence disable polling after hpd handling is shut down.
10324 */
f87ea761 10325 drm_kms_helper_poll_fini(dev);
fd0c0642 10326
652c393a
JB		 10327 mutex_lock(&dev->struct_mutex);
10328
723bfd70
JB		 10329 intel_unregister_dsm_handler();
10330
652c393a
JB		 10331 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10332 /* Skip inactive CRTCs */
10333 if (!crtc->fb)
10334 continue;
10335
10336 intel_crtc = to_intel_crtc(crtc);
3dec0095 10337 intel_increase_pllclock(crtc);
652c393a
JB		 10338 }
10339
973d04f9 10340 intel_disable_fbc(dev);
e70236a8 10341
8090c6b9 10342 intel_disable_gt_powersave(dev);
0cdab21f 10343
930ebb46
DV		 10344 ironlake_teardown_rc6(dev);
10345
69341a5e
KH		 10346 mutex_unlock(&dev->struct_mutex);
10347
1630fe75
CW		 10348 /* flush any delayed tasks or pending work */
10349 flush_scheduled_work();
10350
dc652f90
JN		 10351 /* destroy backlight, if any, before the connectors */
10352 intel_panel_destroy_backlight(dev);
10353
79e53945 10354 drm_mode_config_cleanup(dev);
4d7bb011
DV		 10355
10356 intel_cleanup_overlay(dev);
79e53945
JB		 10357}
10358
f1c79df3
ZW		 10359/*
10360 * Return which encoder is currently attached for connector.
10361 */
df0e9248 10362struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 10363{
df0e9248
CW		 10364 return &intel_attached_encoder(connector)->base;
10365}
f1c79df3 10366
df0e9248
CW		 10367void intel_connector_attach_encoder(struct intel_connector *connector,
10368 struct intel_encoder *encoder)
10369{
10370 connector->encoder = encoder;
10371 drm_mode_connector_attach_encoder(&connector->base,
10372 &encoder->base);
79e53945 10373}
28d52043
DA		 10374
10375/*
10376 * set vga decode state - true == enable VGA decode
10377 */
10378int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10379{
10380 struct drm_i915_private *dev_priv = dev->dev_private;
10381 u16 gmch_ctrl;
10382
10383 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10384 if (state)
10385 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10386 else
10387 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10388 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10389 return 0;
10390}
c4a1d9e4 10391
c4a1d9e4 10392struct intel_display_error_state {
ff57f1b0
PZ		 10393
10394 u32 power_well_driver;
10395
c4a1d9e4
CW		 10396 struct intel_cursor_error_state {
10397 u32 control;
10398 u32 position;
10399 u32 base;
10400 u32 size;
52331309 10401 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 10402
10403 struct intel_pipe_error_state {
ff57f1b0 10404 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 10405 u32 conf;
10406 u32 source;
10407
10408 u32 htotal;
10409 u32 hblank;
10410 u32 hsync;
10411 u32 vtotal;
10412 u32 vblank;
10413 u32 vsync;
52331309 10414 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 10415
10416 struct intel_plane_error_state {
10417 u32 control;
10418 u32 stride;
10419 u32 size;
10420 u32 pos;
10421 u32 addr;
10422 u32 surface;
10423 u32 tile_offset;
52331309 10424 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 10425};
10426
10427struct intel_display_error_state *
10428intel_display_capture_error_state(struct drm_device *dev)
10429{
0206e353 10430 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 10431 struct intel_display_error_state *error;
702e7a56 10432 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 10433 int i;
10434
10435 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10436 if (error == NULL)
10437 return NULL;
10438
ff57f1b0
PZ		 10439 if (HAS_POWER_WELL(dev))
10440 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10441
52331309 10442 for_each_pipe(i) {
702e7a56 10443 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
ff57f1b0 10444 error->pipe[i].cpu_transcoder = cpu_transcoder;
702e7a56 10445
a18c4c3d
PZ		 10446 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10447 error->cursor[i].control = I915_READ(CURCNTR(i));
10448 error->cursor[i].position = I915_READ(CURPOS(i));
10449 error->cursor[i].base = I915_READ(CURBASE(i));
10450 } else {
10451 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10452 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10453 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10454 }
c4a1d9e4
CW		 10455
10456 error->plane[i].control = I915_READ(DSPCNTR(i));
10457 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 10458 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 10459 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 10460 error->plane[i].pos = I915_READ(DSPPOS(i));
10461 }
ca291363
PZ		 10462 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10463 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 10464 if (INTEL_INFO(dev)->gen >= 4) {
10465 error->plane[i].surface = I915_READ(DSPSURF(i));
10466 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10467 }
10468
702e7a56 10469 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 10470 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 10471 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10472 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10473 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10474 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10475 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10476 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 10477 }
10478
12d217c7
PZ		 10479 /* In the code above we read the registers without checking if the power
10480 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10481 * prevent the next I915_WRITE from detecting it and printing an error
10482 * message. */
907b28c5 10483 intel_uncore_clear_errors(dev);
12d217c7 10484
c4a1d9e4
CW		 10485 return error;
10486}
10487
edc3d884
MK		 10488#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10489
c4a1d9e4 10490void
edc3d884 10491intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 10492 struct drm_device *dev,
10493 struct intel_display_error_state *error)
10494{
10495 int i;
10496
edc3d884 10497 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 10498 if (HAS_POWER_WELL(dev))
edc3d884 10499 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 10500 error->power_well_driver);
52331309 10501 for_each_pipe(i) {
edc3d884
MK		 10502 err_printf(m, "Pipe [%d]:\n", i);
10503 err_printf(m, " CPU transcoder: %c\n",
ff57f1b0 10504 transcoder_name(error->pipe[i].cpu_transcoder));
edc3d884
MK		 10505 err_printf(m, " CONF: %08x\n", error->pipe[i].conf);
10506 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
10507 err_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
10508 err_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
10509 err_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
10510 err_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
10511 err_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
10512 err_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
10513
10514 err_printf(m, "Plane [%d]:\n", i);
10515 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
10516 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 10517 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 10518 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
10519 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 10520 }
4b71a570 10521 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 10522 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 10523 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 10524 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
10525 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 10526 }
10527
edc3d884
MK		 10528 err_printf(m, "Cursor [%d]:\n", i);
10529 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
10530 err_printf(m, " POS: %08x\n", error->cursor[i].position);
10531 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4
CW		 10532 }
10533}
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