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drm/i915: Cleanup if the EDP transcoder has a bobug input value
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 47
48typedef struct {
0206e353
AJ		 49 /* given values */
50 int n;
51 int m1, m2;
52 int p1, p2;
53 /* derived values */
54 int dot;
55 int vco;
56 int m;
57 int p;
79e53945
JB		 58} intel_clock_t;
59
60typedef struct {
0206e353 61 int min, max;
79e53945
JB		 62} intel_range_t;
63
64typedef struct {
0206e353
AJ		 65 int dot_limit;
66 int p2_slow, p2_fast;
79e53945
JB		 67} intel_p2_t;
68
69#define INTEL_P2_NUM 2
d4906093
ML		 70typedef struct intel_limit intel_limit_t;
71struct intel_limit {
0206e353
AJ		 72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
73 intel_p2_t p2;
f4808ab8
VS		 74 /**
75 * find_pll() - Find the best values for the PLL
76 * @limit: limits for the PLL
77 * @crtc: current CRTC
78 * @target: target frequency in kHz
79 * @refclk: reference clock frequency in kHz
80 * @match_clock: if provided, @best_clock P divider must
81 * match the P divider from @match_clock
82 * used for LVDS downclocking
83 * @best_clock: best PLL values found
84 *
85 * Returns true on success, false on failure.
86 */
87 bool (*find_pll)(const intel_limit_t *limit,
88 struct drm_crtc *crtc,
89 int target, int refclk,
90 intel_clock_t *match_clock,
91 intel_clock_t *best_clock);
d4906093 92};
79e53945 93
2377b741
JB		 94/* FDI */
95#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
96
d2acd215
DV		 97int
98intel_pch_rawclk(struct drm_device *dev)
99{
100 struct drm_i915_private *dev_priv = dev->dev_private;
101
102 WARN_ON(!HAS_PCH_SPLIT(dev));
103
104 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
105}
106
d4906093
ML		 107static bool
108intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 109 int target, int refclk, intel_clock_t *match_clock,
110 intel_clock_t *best_clock);
d4906093
ML		 111static bool
112intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 113 int target, int refclk, intel_clock_t *match_clock,
114 intel_clock_t *best_clock);
79e53945 115
a4fc5ed6
KP		 116static bool
117intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 118 int target, int refclk, intel_clock_t *match_clock,
119 intel_clock_t *best_clock);
5eb08b69 120static bool
f2b115e6 121intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 122 int target, int refclk, intel_clock_t *match_clock,
123 intel_clock_t *best_clock);
a4fc5ed6 124
a0c4da24
JB		 125static bool
126intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
127 int target, int refclk, intel_clock_t *match_clock,
128 intel_clock_t *best_clock);
129
021357ac
CW		 130static inline u32 /* units of 100MHz */
131intel_fdi_link_freq(struct drm_device *dev)
132{
8b99e68c
CW		 133 if (IS_GEN5(dev)) {
134 struct drm_i915_private *dev_priv = dev->dev_private;
135 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
136 } else
137 return 27;
021357ac
CW		 138}
139
e4b36699 140static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 141 .dot = { .min = 25000, .max = 350000 },
142 .vco = { .min = 930000, .max = 1400000 },
143 .n = { .min = 3, .max = 16 },
144 .m = { .min = 96, .max = 140 },
145 .m1 = { .min = 18, .max = 26 },
146 .m2 = { .min = 6, .max = 16 },
147 .p = { .min = 4, .max = 128 },
148 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 149 .p2 = { .dot_limit = 165000,
150 .p2_slow = 4, .p2_fast = 2 },
d4906093 151 .find_pll = intel_find_best_PLL,
e4b36699
KP		 152};
153
154static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 155 .dot = { .min = 25000, .max = 350000 },
156 .vco = { .min = 930000, .max = 1400000 },
157 .n = { .min = 3, .max = 16 },
158 .m = { .min = 96, .max = 140 },
159 .m1 = { .min = 18, .max = 26 },
160 .m2 = { .min = 6, .max = 16 },
161 .p = { .min = 4, .max = 128 },
162 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 163 .p2 = { .dot_limit = 165000,
164 .p2_slow = 14, .p2_fast = 7 },
d4906093 165 .find_pll = intel_find_best_PLL,
e4b36699 166};
273e27ca 167
e4b36699 168static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 169 .dot = { .min = 20000, .max = 400000 },
170 .vco = { .min = 1400000, .max = 2800000 },
171 .n = { .min = 1, .max = 6 },
172 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 173 .m1 = { .min = 8, .max = 18 },
174 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 175 .p = { .min = 5, .max = 80 },
176 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 177 .p2 = { .dot_limit = 200000,
178 .p2_slow = 10, .p2_fast = 5 },
d4906093 179 .find_pll = intel_find_best_PLL,
e4b36699
KP		 180};
181
182static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 183 .dot = { .min = 20000, .max = 400000 },
184 .vco = { .min = 1400000, .max = 2800000 },
185 .n = { .min = 1, .max = 6 },
186 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 187 .m1 = { .min = 8, .max = 18 },
188 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 189 .p = { .min = 7, .max = 98 },
190 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 191 .p2 = { .dot_limit = 112000,
192 .p2_slow = 14, .p2_fast = 7 },
d4906093 193 .find_pll = intel_find_best_PLL,
e4b36699
KP		 194};
195
273e27ca 196
e4b36699 197static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 198 .dot = { .min = 25000, .max = 270000 },
199 .vco = { .min = 1750000, .max = 3500000},
200 .n = { .min = 1, .max = 4 },
201 .m = { .min = 104, .max = 138 },
202 .m1 = { .min = 17, .max = 23 },
203 .m2 = { .min = 5, .max = 11 },
204 .p = { .min = 10, .max = 30 },
205 .p1 = { .min = 1, .max = 3},
206 .p2 = { .dot_limit = 270000,
207 .p2_slow = 10,
208 .p2_fast = 10
044c7c41 209 },
d4906093 210 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 211};
212
213static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 214 .dot = { .min = 22000, .max = 400000 },
215 .vco = { .min = 1750000, .max = 3500000},
216 .n = { .min = 1, .max = 4 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 16, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 5, .max = 80 },
221 .p1 = { .min = 1, .max = 8},
222 .p2 = { .dot_limit = 165000,
223 .p2_slow = 10, .p2_fast = 5 },
d4906093 224 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 225};
226
227static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 228 .dot = { .min = 20000, .max = 115000 },
229 .vco = { .min = 1750000, .max = 3500000 },
230 .n = { .min = 1, .max = 3 },
231 .m = { .min = 104, .max = 138 },
232 .m1 = { .min = 17, .max = 23 },
233 .m2 = { .min = 5, .max = 11 },
234 .p = { .min = 28, .max = 112 },
235 .p1 = { .min = 2, .max = 8 },
236 .p2 = { .dot_limit = 0,
237 .p2_slow = 14, .p2_fast = 14
044c7c41 238 },
d4906093 239 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 240};
241
242static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 243 .dot = { .min = 80000, .max = 224000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 14, .max = 42 },
250 .p1 = { .min = 2, .max = 6 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 7, .p2_fast = 7
044c7c41 253 },
d4906093 254 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 255};
256
257static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 258 .dot = { .min = 161670, .max = 227000 },
259 .vco = { .min = 1750000, .max = 3500000},
260 .n = { .min = 1, .max = 2 },
261 .m = { .min = 97, .max = 108 },
262 .m1 = { .min = 0x10, .max = 0x12 },
263 .m2 = { .min = 0x05, .max = 0x06 },
264 .p = { .min = 10, .max = 20 },
265 .p1 = { .min = 1, .max = 2},
266 .p2 = { .dot_limit = 0,
273e27ca 267 .p2_slow = 10, .p2_fast = 10 },
0206e353 268 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 269};
270
f2b115e6 271static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 272 .dot = { .min = 20000, .max = 400000},
273 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 274 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 275 .n = { .min = 3, .max = 6 },
276 .m = { .min = 2, .max = 256 },
273e27ca 277 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 278 .m1 = { .min = 0, .max = 0 },
279 .m2 = { .min = 0, .max = 254 },
280 .p = { .min = 5, .max = 80 },
281 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 282 .p2 = { .dot_limit = 200000,
283 .p2_slow = 10, .p2_fast = 5 },
6115707b 284 .find_pll = intel_find_best_PLL,
e4b36699
KP		 285};
286
f2b115e6 287static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 288 .dot = { .min = 20000, .max = 400000 },
289 .vco = { .min = 1700000, .max = 3500000 },
290 .n = { .min = 3, .max = 6 },
291 .m = { .min = 2, .max = 256 },
292 .m1 = { .min = 0, .max = 0 },
293 .m2 = { .min = 0, .max = 254 },
294 .p = { .min = 7, .max = 112 },
295 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 296 .p2 = { .dot_limit = 112000,
297 .p2_slow = 14, .p2_fast = 14 },
6115707b 298 .find_pll = intel_find_best_PLL,
e4b36699
KP		 299};
300
273e27ca
EA		 301/* Ironlake / Sandybridge
302 *
303 * We calculate clock using (register_value + 2) for N/M1/M2, so here
304 * the range value for them is (actual_value - 2).
305 */
b91ad0ec 306static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 5 },
310 .m = { .min = 79, .max = 127 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 5, .max = 80 },
314 .p1 = { .min = 1, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 10, .p2_fast = 5 },
4547668a 317 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 318};
319
b91ad0ec 320static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 79, .max = 118 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 28, .max = 112 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 331 .find_pll = intel_g4x_find_best_PLL,
332};
333
334static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 335 .dot = { .min = 25000, .max = 350000 },
336 .vco = { .min = 1760000, .max = 3510000 },
337 .n = { .min = 1, .max = 3 },
338 .m = { .min = 79, .max = 127 },
339 .m1 = { .min = 12, .max = 22 },
340 .m2 = { .min = 5, .max = 9 },
341 .p = { .min = 14, .max = 56 },
342 .p1 = { .min = 2, .max = 8 },
343 .p2 = { .dot_limit = 225000,
344 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 345 .find_pll = intel_g4x_find_best_PLL,
346};
347
273e27ca 348/* LVDS 100mhz refclk limits. */
b91ad0ec 349static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000 },
352 .n = { .min = 1, .max = 2 },
353 .m = { .min = 79, .max = 126 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 28, .max = 112 },
0206e353 357 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 358 .p2 = { .dot_limit = 225000,
359 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 360 .find_pll = intel_g4x_find_best_PLL,
361};
362
363static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 364 .dot = { .min = 25000, .max = 350000 },
365 .vco = { .min = 1760000, .max = 3510000 },
366 .n = { .min = 1, .max = 3 },
367 .m = { .min = 79, .max = 126 },
368 .m1 = { .min = 12, .max = 22 },
369 .m2 = { .min = 5, .max = 9 },
370 .p = { .min = 14, .max = 42 },
0206e353 371 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 372 .p2 = { .dot_limit = 225000,
373 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 374 .find_pll = intel_g4x_find_best_PLL,
375};
376
377static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 378 .dot = { .min = 25000, .max = 350000 },
379 .vco = { .min = 1760000, .max = 3510000},
380 .n = { .min = 1, .max = 2 },
381 .m = { .min = 81, .max = 90 },
382 .m1 = { .min = 12, .max = 22 },
383 .m2 = { .min = 5, .max = 9 },
384 .p = { .min = 10, .max = 20 },
385 .p1 = { .min = 1, .max = 2},
386 .p2 = { .dot_limit = 0,
273e27ca 387 .p2_slow = 10, .p2_fast = 10 },
0206e353 388 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 389};
390
a0c4da24
JB		 391static const intel_limit_t intel_limits_vlv_dac = {
392 .dot = { .min = 25000, .max = 270000 },
393 .vco = { .min = 4000000, .max = 6000000 },
394 .n = { .min = 1, .max = 7 },
395 .m = { .min = 22, .max = 450 }, /* guess */
396 .m1 = { .min = 2, .max = 3 },
397 .m2 = { .min = 11, .max = 156 },
398 .p = { .min = 10, .max = 30 },
399 .p1 = { .min = 2, .max = 3 },
400 .p2 = { .dot_limit = 270000,
401 .p2_slow = 2, .p2_fast = 20 },
402 .find_pll = intel_vlv_find_best_pll,
403};
404
405static const intel_limit_t intel_limits_vlv_hdmi = {
406 .dot = { .min = 20000, .max = 165000 },
17dc9257 407 .vco = { .min = 4000000, .max = 5994000},
a0c4da24
JB		 408 .n = { .min = 1, .max = 7 },
409 .m = { .min = 60, .max = 300 }, /* guess */
410 .m1 = { .min = 2, .max = 3 },
411 .m2 = { .min = 11, .max = 156 },
412 .p = { .min = 10, .max = 30 },
413 .p1 = { .min = 2, .max = 3 },
414 .p2 = { .dot_limit = 270000,
415 .p2_slow = 2, .p2_fast = 20 },
416 .find_pll = intel_vlv_find_best_pll,
417};
418
419static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 420 .dot = { .min = 25000, .max = 270000 },
421 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 422 .n = { .min = 1, .max = 7 },
74a4dd2e 423 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 424 .m1 = { .min = 2, .max = 3 },
425 .m2 = { .min = 11, .max = 156 },
426 .p = { .min = 10, .max = 30 },
427 .p1 = { .min = 2, .max = 3 },
428 .p2 = { .dot_limit = 270000,
429 .p2_slow = 2, .p2_fast = 20 },
430 .find_pll = intel_vlv_find_best_pll,
431};
432
57f350b6
JB		 433u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
434{
09153000 435 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
57f350b6 436
57f350b6
JB		 437 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
438 DRM_ERROR("DPIO idle wait timed out\n");
09153000 439 return 0;
57f350b6
JB		 440 }
441
442 I915_WRITE(DPIO_REG, reg);
443 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
444 DPIO_BYTE);
445 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
446 DRM_ERROR("DPIO read wait timed out\n");
09153000 447 return 0;
57f350b6 448 }
57f350b6 449
09153000 450 return I915_READ(DPIO_DATA);
57f350b6
JB		 451}
452
a0c4da24
JB		 453static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
454 u32 val)
455{
09153000 456 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a0c4da24 457
a0c4da24
JB		 458 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
459 DRM_ERROR("DPIO idle wait timed out\n");
09153000 460 return;
a0c4da24
JB		 461 }
462
463 I915_WRITE(DPIO_DATA, val);
464 I915_WRITE(DPIO_REG, reg);
465 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
466 DPIO_BYTE);
467 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
468 DRM_ERROR("DPIO write wait timed out\n");
a0c4da24
JB		 469}
470
57f350b6
JB		 471static void vlv_init_dpio(struct drm_device *dev)
472{
473 struct drm_i915_private *dev_priv = dev->dev_private;
474
475 /* Reset the DPIO config */
476 I915_WRITE(DPIO_CTL, 0);
477 POSTING_READ(DPIO_CTL);
478 I915_WRITE(DPIO_CTL, 1);
479 POSTING_READ(DPIO_CTL);
480}
481
1b894b59
CW		 482static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
483 int refclk)
2c07245f 484{
b91ad0ec 485 struct drm_device *dev = crtc->dev;
2c07245f 486 const intel_limit_t *limit;
b91ad0ec
ZW		 487
488 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 489 if (intel_is_dual_link_lvds(dev)) {
1b894b59 490 if (refclk == 100000)
b91ad0ec
ZW		 491 limit = &intel_limits_ironlake_dual_lvds_100m;
492 else
493 limit = &intel_limits_ironlake_dual_lvds;
494 } else {
1b894b59 495 if (refclk == 100000)
b91ad0ec
ZW		 496 limit = &intel_limits_ironlake_single_lvds_100m;
497 else
498 limit = &intel_limits_ironlake_single_lvds;
499 }
500 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
547dc041 501 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
4547668a 502 limit = &intel_limits_ironlake_display_port;
2c07245f 503 else
b91ad0ec 504 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 505
506 return limit;
507}
508
044c7c41
ML		 509static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
510{
511 struct drm_device *dev = crtc->dev;
044c7c41
ML		 512 const intel_limit_t *limit;
513
514 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 515 if (intel_is_dual_link_lvds(dev))
e4b36699 516 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 517 else
e4b36699 518 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 519 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
520 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 521 limit = &intel_limits_g4x_hdmi;
044c7c41 522 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 523 limit = &intel_limits_g4x_sdvo;
0206e353 524 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 525 limit = &intel_limits_g4x_display_port;
044c7c41 526 } else /* The option is for other outputs */
e4b36699 527 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 528
529 return limit;
530}
531
1b894b59 532static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 533{
534 struct drm_device *dev = crtc->dev;
535 const intel_limit_t *limit;
536
bad720ff 537 if (HAS_PCH_SPLIT(dev))
1b894b59 538 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 539 else if (IS_G4X(dev)) {
044c7c41 540 limit = intel_g4x_limit(crtc);
f2b115e6 541 } else if (IS_PINEVIEW(dev)) {
2177832f 542 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 543 limit = &intel_limits_pineview_lvds;
2177832f 544 else
f2b115e6 545 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 546 } else if (IS_VALLEYVIEW(dev)) {
547 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
548 limit = &intel_limits_vlv_dac;
549 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
550 limit = &intel_limits_vlv_hdmi;
551 else
552 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 553 } else if (!IS_GEN2(dev)) {
554 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
555 limit = &intel_limits_i9xx_lvds;
556 else
557 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 558 } else {
559 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 560 limit = &intel_limits_i8xx_lvds;
79e53945 561 else
e4b36699 562 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 563 }
564 return limit;
565}
566
f2b115e6
AJ		 567/* m1 is reserved as 0 in Pineview, n is a ring counter */
568static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 569{
2177832f
SL		 570 clock->m = clock->m2 + 2;
571 clock->p = clock->p1 * clock->p2;
572 clock->vco = refclk * clock->m / clock->n;
573 clock->dot = clock->vco / clock->p;
574}
575
576static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
577{
f2b115e6
AJ		 578 if (IS_PINEVIEW(dev)) {
579 pineview_clock(refclk, clock);
2177832f
SL		 580 return;
581 }
79e53945
JB		 582 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
583 clock->p = clock->p1 * clock->p2;
584 clock->vco = refclk * clock->m / (clock->n + 2);
585 clock->dot = clock->vco / clock->p;
586}
587
79e53945
JB		 588/**
589 * Returns whether any output on the specified pipe is of the specified type
590 */
4ef69c7a 591bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 592{
4ef69c7a 593 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 594 struct intel_encoder *encoder;
595
6c2b7c12
DV		 596 for_each_encoder_on_crtc(dev, crtc, encoder)
597 if (encoder->type == type)
4ef69c7a
CW		 598 return true;
599
600 return false;
79e53945
JB		 601}
602
7c04d1d9 603#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 604/**
605 * Returns whether the given set of divisors are valid for a given refclk with
606 * the given connectors.
607 */
608
1b894b59
CW		 609static bool intel_PLL_is_valid(struct drm_device *dev,
610 const intel_limit_t *limit,
611 const intel_clock_t *clock)
79e53945 612{
79e53945 613 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 614 INTELPllInvalid("p1 out of range\n");
79e53945 615 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 616 INTELPllInvalid("p out of range\n");
79e53945 617 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 618 INTELPllInvalid("m2 out of range\n");
79e53945 619 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 620 INTELPllInvalid("m1 out of range\n");
f2b115e6 621 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 622 INTELPllInvalid("m1 <= m2\n");
79e53945 623 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 624 INTELPllInvalid("m out of range\n");
79e53945 625 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 626 INTELPllInvalid("n out of range\n");
79e53945 627 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 628 INTELPllInvalid("vco out of range\n");
79e53945
JB		 629 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
630 * connector, etc., rather than just a single range.
631 */
632 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 633 INTELPllInvalid("dot out of range\n");
79e53945
JB		 634
635 return true;
636}
637
d4906093
ML		 638static bool
639intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 640 int target, int refclk, intel_clock_t *match_clock,
641 intel_clock_t *best_clock)
d4906093 642
79e53945
JB		 643{
644 struct drm_device *dev = crtc->dev;
79e53945 645 intel_clock_t clock;
79e53945
JB		 646 int err = target;
647
a210b028 648 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 649 /*
a210b028
DV		 650 * For LVDS just rely on its current settings for dual-channel.
651 * We haven't figured out how to reliably set up different
652 * single/dual channel state, if we even can.
79e53945 653 */
1974cad0 654 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 655 clock.p2 = limit->p2.p2_fast;
656 else
657 clock.p2 = limit->p2.p2_slow;
658 } else {
659 if (target < limit->p2.dot_limit)
660 clock.p2 = limit->p2.p2_slow;
661 else
662 clock.p2 = limit->p2.p2_fast;
663 }
664
0206e353 665 memset(best_clock, 0, sizeof(*best_clock));
79e53945 666
42158660
ZY		 667 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
668 clock.m1++) {
669 for (clock.m2 = limit->m2.min;
670 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 671 /* m1 is always 0 in Pineview */
672 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 673 break;
674 for (clock.n = limit->n.min;
675 clock.n <= limit->n.max; clock.n++) {
676 for (clock.p1 = limit->p1.min;
677 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 678 int this_err;
679
2177832f 680 intel_clock(dev, refclk, &clock);
1b894b59
CW		 681 if (!intel_PLL_is_valid(dev, limit,
682 &clock))
79e53945 683 continue;
cec2f356
SP		 684 if (match_clock &&
685 clock.p != match_clock->p)
686 continue;
79e53945
JB		 687
688 this_err = abs(clock.dot - target);
689 if (this_err < err) {
690 *best_clock = clock;
691 err = this_err;
692 }
693 }
694 }
695 }
696 }
697
698 return (err != target);
699}
700
d4906093
ML		 701static bool
702intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 703 int target, int refclk, intel_clock_t *match_clock,
704 intel_clock_t *best_clock)
d4906093
ML		 705{
706 struct drm_device *dev = crtc->dev;
d4906093
ML		 707 intel_clock_t clock;
708 int max_n;
709 bool found;
6ba770dc
AJ		 710 /* approximately equals target * 0.00585 */
711 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 712 found = false;
713
714 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 715 int lvds_reg;
716
c619eed4 717 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 718 lvds_reg = PCH_LVDS;
719 else
720 lvds_reg = LVDS;
1974cad0 721 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 722 clock.p2 = limit->p2.p2_fast;
723 else
724 clock.p2 = limit->p2.p2_slow;
725 } else {
726 if (target < limit->p2.dot_limit)
727 clock.p2 = limit->p2.p2_slow;
728 else
729 clock.p2 = limit->p2.p2_fast;
730 }
731
732 memset(best_clock, 0, sizeof(*best_clock));
733 max_n = limit->n.max;
f77f13e2 734 /* based on hardware requirement, prefer smaller n to precision */
d4906093 735 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 736 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 737 for (clock.m1 = limit->m1.max;
738 clock.m1 >= limit->m1.min; clock.m1--) {
739 for (clock.m2 = limit->m2.max;
740 clock.m2 >= limit->m2.min; clock.m2--) {
741 for (clock.p1 = limit->p1.max;
742 clock.p1 >= limit->p1.min; clock.p1--) {
743 int this_err;
744
2177832f 745 intel_clock(dev, refclk, &clock);
1b894b59
CW		 746 if (!intel_PLL_is_valid(dev, limit,
747 &clock))
d4906093 748 continue;
cec2f356
SP		 749 if (match_clock &&
750 clock.p != match_clock->p)
751 continue;
1b894b59
CW		 752
753 this_err = abs(clock.dot - target);
d4906093
ML		 754 if (this_err < err_most) {
755 *best_clock = clock;
756 err_most = this_err;
757 max_n = clock.n;
758 found = true;
759 }
760 }
761 }
762 }
763 }
2c07245f
ZW		 764 return found;
765}
766
5eb08b69 767static bool
f2b115e6 768intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 769 int target, int refclk, intel_clock_t *match_clock,
770 intel_clock_t *best_clock)
5eb08b69
ZW		 771{
772 struct drm_device *dev = crtc->dev;
773 intel_clock_t clock;
4547668a 774
5eb08b69
ZW		 775 if (target < 200000) {
776 clock.n = 1;
777 clock.p1 = 2;
778 clock.p2 = 10;
779 clock.m1 = 12;
780 clock.m2 = 9;
781 } else {
782 clock.n = 2;
783 clock.p1 = 1;
784 clock.p2 = 10;
785 clock.m1 = 14;
786 clock.m2 = 8;
787 }
788 intel_clock(dev, refclk, &clock);
789 memcpy(best_clock, &clock, sizeof(intel_clock_t));
790 return true;
791}
792
a4fc5ed6
KP		 793/* DisplayPort has only two frequencies, 162MHz and 270MHz */
794static bool
795intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 796 int target, int refclk, intel_clock_t *match_clock,
797 intel_clock_t *best_clock)
a4fc5ed6 798{
5eddb70b
CW		 799 intel_clock_t clock;
800 if (target < 200000) {
801 clock.p1 = 2;
802 clock.p2 = 10;
803 clock.n = 2;
804 clock.m1 = 23;
805 clock.m2 = 8;
806 } else {
807 clock.p1 = 1;
808 clock.p2 = 10;
809 clock.n = 1;
810 clock.m1 = 14;
811 clock.m2 = 2;
812 }
813 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
814 clock.p = (clock.p1 * clock.p2);
815 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
816 clock.vco = 0;
817 memcpy(best_clock, &clock, sizeof(intel_clock_t));
818 return true;
a4fc5ed6 819}
a0c4da24
JB		 820static bool
821intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
822 int target, int refclk, intel_clock_t *match_clock,
823 intel_clock_t *best_clock)
824{
825 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
826 u32 m, n, fastclk;
827 u32 updrate, minupdate, fracbits, p;
828 unsigned long bestppm, ppm, absppm;
829 int dotclk, flag;
830
af447bd3 831 flag = 0;
a0c4da24
JB		 832 dotclk = target * 1000;
833 bestppm = 1000000;
834 ppm = absppm = 0;
835 fastclk = dotclk / (2*100);
836 updrate = 0;
837 minupdate = 19200;
838 fracbits = 1;
839 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
840 bestm1 = bestm2 = bestp1 = bestp2 = 0;
841
842 /* based on hardware requirement, prefer smaller n to precision */
843 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
844 updrate = refclk / n;
845 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
846 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
847 if (p2 > 10)
848 p2 = p2 - 1;
849 p = p1 * p2;
850 /* based on hardware requirement, prefer bigger m1,m2 values */
851 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
852 m2 = (((2*(fastclk * p * n / m1 )) +
853 refclk) / (2*refclk));
854 m = m1 * m2;
855 vco = updrate * m;
856 if (vco >= limit->vco.min && vco < limit->vco.max) {
857 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
858 absppm = (ppm > 0) ? ppm : (-ppm);
859 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
860 bestppm = 0;
861 flag = 1;
862 }
863 if (absppm < bestppm - 10) {
864 bestppm = absppm;
865 flag = 1;
866 }
867 if (flag) {
868 bestn = n;
869 bestm1 = m1;
870 bestm2 = m2;
871 bestp1 = p1;
872 bestp2 = p2;
873 flag = 0;
874 }
875 }
876 }
877 }
878 }
879 }
880 best_clock->n = bestn;
881 best_clock->m1 = bestm1;
882 best_clock->m2 = bestm2;
883 best_clock->p1 = bestp1;
884 best_clock->p2 = bestp2;
885
886 return true;
887}
a4fc5ed6 888
a5c961d1
PZ		 889enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
890 enum pipe pipe)
891{
892 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
893 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
894
895 return intel_crtc->cpu_transcoder;
896}
897
a928d536
PZ		 898static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
899{
900 struct drm_i915_private *dev_priv = dev->dev_private;
901 u32 frame, frame_reg = PIPEFRAME(pipe);
902
903 frame = I915_READ(frame_reg);
904
905 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
906 DRM_DEBUG_KMS("vblank wait timed out\n");
907}
908
9d0498a2
JB		 909/**
910 * intel_wait_for_vblank - wait for vblank on a given pipe
911 * @dev: drm device
912 * @pipe: pipe to wait for
913 *
914 * Wait for vblank to occur on a given pipe. Needed for various bits of
915 * mode setting code.
916 */
917void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 918{
9d0498a2 919 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 920 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 921
a928d536
PZ		 922 if (INTEL_INFO(dev)->gen >= 5) {
923 ironlake_wait_for_vblank(dev, pipe);
924 return;
925 }
926
300387c0
CW		 927 /* Clear existing vblank status. Note this will clear any other
928 * sticky status fields as well.
929 *
930 * This races with i915_driver_irq_handler() with the result
931 * that either function could miss a vblank event. Here it is not
932 * fatal, as we will either wait upon the next vblank interrupt or
933 * timeout. Generally speaking intel_wait_for_vblank() is only
934 * called during modeset at which time the GPU should be idle and
935 * should *not* be performing page flips and thus not waiting on
936 * vblanks...
937 * Currently, the result of us stealing a vblank from the irq
938 * handler is that a single frame will be skipped during swapbuffers.
939 */
940 I915_WRITE(pipestat_reg,
941 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
942
9d0498a2 943 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 944 if (wait_for(I915_READ(pipestat_reg) &
945 PIPE_VBLANK_INTERRUPT_STATUS,
946 50))
9d0498a2
JB		 947 DRM_DEBUG_KMS("vblank wait timed out\n");
948}
949
ab7ad7f6
KP		 950/*
951 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 952 * @dev: drm device
953 * @pipe: pipe to wait for
954 *
955 * After disabling a pipe, we can't wait for vblank in the usual way,
956 * spinning on the vblank interrupt status bit, since we won't actually
957 * see an interrupt when the pipe is disabled.
958 *
ab7ad7f6
KP		 959 * On Gen4 and above:
960 * wait for the pipe register state bit to turn off
961 *
962 * Otherwise:
963 * wait for the display line value to settle (it usually
964 * ends up stopping at the start of the next frame).
58e10eb9 965 *
9d0498a2 966 */
58e10eb9 967void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 968{
969 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 970 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
971 pipe);
ab7ad7f6
KP		 972
973 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 974 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 975
976 /* Wait for the Pipe State to go off */
58e10eb9
CW		 977 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
978 100))
284637d9 979 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 980 } else {
837ba00f 981 u32 last_line, line_mask;
58e10eb9 982 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 983 unsigned long timeout = jiffies + msecs_to_jiffies(100);
984
837ba00f
PZ		 985 if (IS_GEN2(dev))
986 line_mask = DSL_LINEMASK_GEN2;
987 else
988 line_mask = DSL_LINEMASK_GEN3;
989
ab7ad7f6
KP		 990 /* Wait for the display line to settle */
991 do {
837ba00f 992 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 993 mdelay(5);
837ba00f 994 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 995 time_after(timeout, jiffies));
996 if (time_after(jiffies, timeout))
284637d9 997 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 998 }
79e53945
JB		 999}
1000
b0ea7d37
DL		 1001/*
1002 * ibx_digital_port_connected - is the specified port connected?
1003 * @dev_priv: i915 private structure
1004 * @port: the port to test
1005 *
1006 * Returns true if @port is connected, false otherwise.
1007 */
1008bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1009 struct intel_digital_port *port)
1010{
1011 u32 bit;
1012
c36346e3
DL		 1013 if (HAS_PCH_IBX(dev_priv->dev)) {
1014 switch(port->port) {
1015 case PORT_B:
1016 bit = SDE_PORTB_HOTPLUG;
1017 break;
1018 case PORT_C:
1019 bit = SDE_PORTC_HOTPLUG;
1020 break;
1021 case PORT_D:
1022 bit = SDE_PORTD_HOTPLUG;
1023 break;
1024 default:
1025 return true;
1026 }
1027 } else {
1028 switch(port->port) {
1029 case PORT_B:
1030 bit = SDE_PORTB_HOTPLUG_CPT;
1031 break;
1032 case PORT_C:
1033 bit = SDE_PORTC_HOTPLUG_CPT;
1034 break;
1035 case PORT_D:
1036 bit = SDE_PORTD_HOTPLUG_CPT;
1037 break;
1038 default:
1039 return true;
1040 }
b0ea7d37
DL		 1041 }
1042
1043 return I915_READ(SDEISR) & bit;
1044}
1045
b24e7179
JB		 1046static const char *state_string(bool enabled)
1047{
1048 return enabled ? "on" : "off";
1049}
1050
1051/* Only for pre-ILK configs */
1052static void assert_pll(struct drm_i915_private *dev_priv,
1053 enum pipe pipe, bool state)
1054{
1055 int reg;
1056 u32 val;
1057 bool cur_state;
1058
1059 reg = DPLL(pipe);
1060 val = I915_READ(reg);
1061 cur_state = !!(val & DPLL_VCO_ENABLE);
1062 WARN(cur_state != state,
1063 "PLL state assertion failure (expected %s, current %s)\n",
1064 state_string(state), state_string(cur_state));
1065}
1066#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1067#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1068
040484af
JB		 1069/* For ILK+ */
1070static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1071 struct intel_pch_pll *pll,
1072 struct intel_crtc *crtc,
1073 bool state)
040484af 1074{
040484af
JB		 1075 u32 val;
1076 bool cur_state;
1077
9d82aa17
ED		 1078 if (HAS_PCH_LPT(dev_priv->dev)) {
1079 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1080 return;
1081 }
1082
92b27b08
CW		 1083 if (WARN (!pll,
1084 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1085 return;
ee7b9f93 1086
92b27b08
CW		 1087 val = I915_READ(pll->pll_reg);
1088 cur_state = !!(val & DPLL_VCO_ENABLE);
1089 WARN(cur_state != state,
1090 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1091 pll->pll_reg, state_string(state), state_string(cur_state), val);
1092
1093 /* Make sure the selected PLL is correctly attached to the transcoder */
1094 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1095 u32 pch_dpll;
1096
1097 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1098 cur_state = pll->pll_reg == _PCH_DPLL_B;
1099 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1100 "PLL[%d] not attached to this transcoder %d: %08x\n",
1101 cur_state, crtc->pipe, pch_dpll)) {
1102 cur_state = !!(val >> (4*crtc->pipe + 3));
1103 WARN(cur_state != state,
1104 "PLL[%d] not %s on this transcoder %d: %08x\n",
1105 pll->pll_reg == _PCH_DPLL_B,
1106 state_string(state),
1107 crtc->pipe,
1108 val);
1109 }
d3ccbe86 1110 }
040484af 1111}
92b27b08
CW		 1112#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1113#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1114
1115static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1116 enum pipe pipe, bool state)
1117{
1118 int reg;
1119 u32 val;
1120 bool cur_state;
ad80a810
PZ		 1121 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1122 pipe);
040484af 1123
affa9354
PZ		 1124 if (HAS_DDI(dev_priv->dev)) {
1125 /* DDI does not have a specific FDI_TX register */
ad80a810 1126 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1127 val = I915_READ(reg);
ad80a810 1128 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1129 } else {
1130 reg = FDI_TX_CTL(pipe);
1131 val = I915_READ(reg);
1132 cur_state = !!(val & FDI_TX_ENABLE);
1133 }
040484af
JB		 1134 WARN(cur_state != state,
1135 "FDI TX state assertion failure (expected %s, current %s)\n",
1136 state_string(state), state_string(cur_state));
1137}
1138#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1139#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1140
1141static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1142 enum pipe pipe, bool state)
1143{
1144 int reg;
1145 u32 val;
1146 bool cur_state;
1147
d63fa0dc
PZ		 1148 reg = FDI_RX_CTL(pipe);
1149 val = I915_READ(reg);
1150 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1151 WARN(cur_state != state,
1152 "FDI RX state assertion failure (expected %s, current %s)\n",
1153 state_string(state), state_string(cur_state));
1154}
1155#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1156#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1157
1158static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1159 enum pipe pipe)
1160{
1161 int reg;
1162 u32 val;
1163
1164 /* ILK FDI PLL is always enabled */
1165 if (dev_priv->info->gen == 5)
1166 return;
1167
bf507ef7 1168 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1169 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1170 return;
1171
040484af
JB		 1172 reg = FDI_TX_CTL(pipe);
1173 val = I915_READ(reg);
1174 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1175}
1176
1177static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1178 enum pipe pipe)
1179{
1180 int reg;
1181 u32 val;
1182
1183 reg = FDI_RX_CTL(pipe);
1184 val = I915_READ(reg);
1185 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1186}
1187
ea0760cf
JB		 1188static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1189 enum pipe pipe)
1190{
1191 int pp_reg, lvds_reg;
1192 u32 val;
1193 enum pipe panel_pipe = PIPE_A;
0de3b485 1194 bool locked = true;
ea0760cf
JB		 1195
1196 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1197 pp_reg = PCH_PP_CONTROL;
1198 lvds_reg = PCH_LVDS;
1199 } else {
1200 pp_reg = PP_CONTROL;
1201 lvds_reg = LVDS;
1202 }
1203
1204 val = I915_READ(pp_reg);
1205 if (!(val & PANEL_POWER_ON) ||
1206 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1207 locked = false;
1208
1209 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1210 panel_pipe = PIPE_B;
1211
1212 WARN(panel_pipe == pipe && locked,
1213 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1214 pipe_name(pipe));
ea0760cf
JB		 1215}
1216
b840d907
JB		 1217void assert_pipe(struct drm_i915_private *dev_priv,
1218 enum pipe pipe, bool state)
b24e7179
JB		 1219{
1220 int reg;
1221 u32 val;
63d7bbe9 1222 bool cur_state;
702e7a56
PZ		 1223 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1224 pipe);
b24e7179 1225
8e636784
DV		 1226 /* if we need the pipe A quirk it must be always on */
1227 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1228 state = true;
1229
69310161
PZ		 1230 if (IS_HASWELL(dev_priv->dev) && cpu_transcoder != TRANSCODER_EDP &&
1231 !(I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_ENABLE)) {
1232 cur_state = false;
1233 } else {
1234 reg = PIPECONF(cpu_transcoder);
1235 val = I915_READ(reg);
1236 cur_state = !!(val & PIPECONF_ENABLE);
1237 }
1238
63d7bbe9
JB		 1239 WARN(cur_state != state,
1240 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1241 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1242}
1243
931872fc
CW		 1244static void assert_plane(struct drm_i915_private *dev_priv,
1245 enum plane plane, bool state)
b24e7179
JB		 1246{
1247 int reg;
1248 u32 val;
931872fc 1249 bool cur_state;
b24e7179
JB		 1250
1251 reg = DSPCNTR(plane);
1252 val = I915_READ(reg);
931872fc
CW		 1253 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1254 WARN(cur_state != state,
1255 "plane %c assertion failure (expected %s, current %s)\n",
1256 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1257}
1258
931872fc
CW		 1259#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1260#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1261
b24e7179
JB		 1262static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1263 enum pipe pipe)
1264{
1265 int reg, i;
1266 u32 val;
1267 int cur_pipe;
1268
19ec1358 1269 /* Planes are fixed to pipes on ILK+ */
da6ecc5d 1270 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
28c05794
AJ		 1271 reg = DSPCNTR(pipe);
1272 val = I915_READ(reg);
1273 WARN((val & DISPLAY_PLANE_ENABLE),
1274 "plane %c assertion failure, should be disabled but not\n",
1275 plane_name(pipe));
19ec1358 1276 return;
28c05794 1277 }
19ec1358 1278
b24e7179
JB		 1279 /* Need to check both planes against the pipe */
1280 for (i = 0; i < 2; i++) {
1281 reg = DSPCNTR(i);
1282 val = I915_READ(reg);
1283 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1284 DISPPLANE_SEL_PIPE_SHIFT;
1285 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1286 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1287 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1288 }
1289}
1290
92f2584a
JB		 1291static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1292{
1293 u32 val;
1294 bool enabled;
1295
9d82aa17
ED		 1296 if (HAS_PCH_LPT(dev_priv->dev)) {
1297 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1298 return;
1299 }
1300
92f2584a
JB		 1301 val = I915_READ(PCH_DREF_CONTROL);
1302 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1303 DREF_SUPERSPREAD_SOURCE_MASK));
1304 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1305}
1306
1307static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1308 enum pipe pipe)
1309{
1310 int reg;
1311 u32 val;
1312 bool enabled;
1313
1314 reg = TRANSCONF(pipe);
1315 val = I915_READ(reg);
1316 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1317 WARN(enabled,
1318 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1319 pipe_name(pipe));
92f2584a
JB		 1320}
1321
4e634389
KP		 1322static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1323 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1324{
1325 if ((val & DP_PORT_EN) == 0)
1326 return false;
1327
1328 if (HAS_PCH_CPT(dev_priv->dev)) {
1329 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1330 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1331 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1332 return false;
1333 } else {
1334 if ((val & DP_PIPE_MASK) != (pipe << 30))
1335 return false;
1336 }
1337 return true;
1338}
1339
1519b995
KP		 1340static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1341 enum pipe pipe, u32 val)
1342{
dc0fa718 1343 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1344 return false;
1345
1346 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1347 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1348 return false;
1349 } else {
dc0fa718 1350 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1351 return false;
1352 }
1353 return true;
1354}
1355
1356static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1357 enum pipe pipe, u32 val)
1358{
1359 if ((val & LVDS_PORT_EN) == 0)
1360 return false;
1361
1362 if (HAS_PCH_CPT(dev_priv->dev)) {
1363 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1364 return false;
1365 } else {
1366 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1367 return false;
1368 }
1369 return true;
1370}
1371
1372static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1373 enum pipe pipe, u32 val)
1374{
1375 if ((val & ADPA_DAC_ENABLE) == 0)
1376 return false;
1377 if (HAS_PCH_CPT(dev_priv->dev)) {
1378 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1379 return false;
1380 } else {
1381 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1382 return false;
1383 }
1384 return true;
1385}
1386
291906f1 1387static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1388 enum pipe pipe, int reg, u32 port_sel)
291906f1 1389{
47a05eca 1390 u32 val = I915_READ(reg);
4e634389 1391 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1392 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1393 reg, pipe_name(pipe));
de9a35ab 1394
75c5da27
DV		 1395 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1396 && (val & DP_PIPEB_SELECT),
de9a35ab 1397 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1398}
1399
1400static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1401 enum pipe pipe, int reg)
1402{
47a05eca 1403 u32 val = I915_READ(reg);
b70ad586 1404 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1405 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1406 reg, pipe_name(pipe));
de9a35ab 1407
dc0fa718 1408 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1409 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1410 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1411}
1412
1413static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1414 enum pipe pipe)
1415{
1416 int reg;
1417 u32 val;
291906f1 1418
f0575e92
KP		 1419 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1420 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1421 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1422
1423 reg = PCH_ADPA;
1424 val = I915_READ(reg);
b70ad586 1425 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1426 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1427 pipe_name(pipe));
291906f1
JB		 1428
1429 reg = PCH_LVDS;
1430 val = I915_READ(reg);
b70ad586 1431 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1432 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1433 pipe_name(pipe));
291906f1 1434
e2debe91
PZ		 1435 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1436 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1437 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1438}
1439
63d7bbe9
JB		 1440/**
1441 * intel_enable_pll - enable a PLL
1442 * @dev_priv: i915 private structure
1443 * @pipe: pipe PLL to enable
1444 *
1445 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1446 * make sure the PLL reg is writable first though, since the panel write
1447 * protect mechanism may be enabled.
1448 *
1449 * Note! This is for pre-ILK only.
7434a255
TR		 1450 *
1451 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1452 */
1453static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1454{
1455 int reg;
1456 u32 val;
1457
1458 /* No really, not for ILK+ */
a0c4da24 1459 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1460
1461 /* PLL is protected by panel, make sure we can write it */
1462 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1463 assert_panel_unlocked(dev_priv, pipe);
1464
1465 reg = DPLL(pipe);
1466 val = I915_READ(reg);
1467 val |= DPLL_VCO_ENABLE;
1468
1469 /* We do this three times for luck */
1470 I915_WRITE(reg, val);
1471 POSTING_READ(reg);
1472 udelay(150); /* wait for warmup */
1473 I915_WRITE(reg, val);
1474 POSTING_READ(reg);
1475 udelay(150); /* wait for warmup */
1476 I915_WRITE(reg, val);
1477 POSTING_READ(reg);
1478 udelay(150); /* wait for warmup */
1479}
1480
1481/**
1482 * intel_disable_pll - disable a PLL
1483 * @dev_priv: i915 private structure
1484 * @pipe: pipe PLL to disable
1485 *
1486 * Disable the PLL for @pipe, making sure the pipe is off first.
1487 *
1488 * Note! This is for pre-ILK only.
1489 */
1490static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1491{
1492 int reg;
1493 u32 val;
1494
1495 /* Don't disable pipe A or pipe A PLLs if needed */
1496 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1497 return;
1498
1499 /* Make sure the pipe isn't still relying on us */
1500 assert_pipe_disabled(dev_priv, pipe);
1501
1502 reg = DPLL(pipe);
1503 val = I915_READ(reg);
1504 val &= ~DPLL_VCO_ENABLE;
1505 I915_WRITE(reg, val);
1506 POSTING_READ(reg);
1507}
1508
a416edef
ED		 1509/* SBI access */
1510static void
988d6ee8
PZ		 1511intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1512 enum intel_sbi_destination destination)
a416edef 1513{
988d6ee8 1514 u32 tmp;
a416edef 1515
09153000 1516 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1517
39fb50f6 1518 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1519 100)) {
1520 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1521 return;
a416edef
ED		 1522 }
1523
988d6ee8
PZ		 1524 I915_WRITE(SBI_ADDR, (reg << 16));
1525 I915_WRITE(SBI_DATA, value);
1526
1527 if (destination == SBI_ICLK)
1528 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1529 else
1530 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1531 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
a416edef 1532
39fb50f6 1533 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1534 100)) {
1535 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
09153000 1536 return;
a416edef 1537 }
a416edef
ED		 1538}
1539
1540static u32
988d6ee8
PZ		 1541intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1542 enum intel_sbi_destination destination)
a416edef 1543{
39fb50f6 1544 u32 value = 0;
09153000 1545 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1546
39fb50f6 1547 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1548 100)) {
1549 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1550 return 0;
a416edef
ED		 1551 }
1552
988d6ee8
PZ		 1553 I915_WRITE(SBI_ADDR, (reg << 16));
1554
1555 if (destination == SBI_ICLK)
1556 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1557 else
1558 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1559 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
a416edef 1560
39fb50f6 1561 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1562 100)) {
1563 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
09153000 1564 return 0;
a416edef
ED		 1565 }
1566
09153000 1567 return I915_READ(SBI_DATA);
a416edef
ED		 1568}
1569
92f2584a 1570/**
b6b4e185 1571 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1572 * @dev_priv: i915 private structure
1573 * @pipe: pipe PLL to enable
1574 *
1575 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1576 * drives the transcoder clock.
1577 */
b6b4e185 1578static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1579{
ee7b9f93 1580 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1581 struct intel_pch_pll *pll;
92f2584a
JB		 1582 int reg;
1583 u32 val;
1584
48da64a8 1585 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1586 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1587 pll = intel_crtc->pch_pll;
1588 if (pll == NULL)
1589 return;
1590
1591 if (WARN_ON(pll->refcount == 0))
1592 return;
ee7b9f93
JB		 1593
1594 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1595 pll->pll_reg, pll->active, pll->on,
1596 intel_crtc->base.base.id);
92f2584a
JB		 1597
1598 /* PCH refclock must be enabled first */
1599 assert_pch_refclk_enabled(dev_priv);
1600
ee7b9f93 1601 if (pll->active++ && pll->on) {
92b27b08 1602 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1603 return;
1604 }
1605
1606 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1607
1608 reg = pll->pll_reg;
92f2584a
JB		 1609 val = I915_READ(reg);
1610 val |= DPLL_VCO_ENABLE;
1611 I915_WRITE(reg, val);
1612 POSTING_READ(reg);
1613 udelay(200);
ee7b9f93
JB		 1614
1615 pll->on = true;
92f2584a
JB		 1616}
1617
ee7b9f93 1618static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1619{
ee7b9f93
JB		 1620 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1621 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1622 int reg;
ee7b9f93 1623 u32 val;
4c609cb8 1624
92f2584a
JB		 1625 /* PCH only available on ILK+ */
1626 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1627 if (pll == NULL)
1628 return;
92f2584a 1629
48da64a8
CW		 1630 if (WARN_ON(pll->refcount == 0))
1631 return;
7a419866 1632
ee7b9f93
JB		 1633 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1634 pll->pll_reg, pll->active, pll->on,
1635 intel_crtc->base.base.id);
7a419866 1636
48da64a8 1637 if (WARN_ON(pll->active == 0)) {
92b27b08 1638 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1639 return;
1640 }
1641
ee7b9f93 1642 if (--pll->active) {
92b27b08 1643 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1644 return;
ee7b9f93
JB		 1645 }
1646
1647 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1648
1649 /* Make sure transcoder isn't still depending on us */
1650 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1651
ee7b9f93 1652 reg = pll->pll_reg;
92f2584a
JB		 1653 val = I915_READ(reg);
1654 val &= ~DPLL_VCO_ENABLE;
1655 I915_WRITE(reg, val);
1656 POSTING_READ(reg);
1657 udelay(200);
ee7b9f93
JB		 1658
1659 pll->on = false;
92f2584a
JB		 1660}
1661
b8a4f404
PZ		 1662static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1663 enum pipe pipe)
040484af 1664{
23670b32 1665 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1666 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1667 uint32_t reg, val, pipeconf_val;
040484af
JB		 1668
1669 /* PCH only available on ILK+ */
1670 BUG_ON(dev_priv->info->gen < 5);
1671
1672 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1673 assert_pch_pll_enabled(dev_priv,
1674 to_intel_crtc(crtc)->pch_pll,
1675 to_intel_crtc(crtc));
040484af
JB		 1676
1677 /* FDI must be feeding us bits for PCH ports */
1678 assert_fdi_tx_enabled(dev_priv, pipe);
1679 assert_fdi_rx_enabled(dev_priv, pipe);
1680
23670b32
DV		 1681 if (HAS_PCH_CPT(dev)) {
1682 /* Workaround: Set the timing override bit before enabling the
1683 * pch transcoder. */
1684 reg = TRANS_CHICKEN2(pipe);
1685 val = I915_READ(reg);
1686 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1687 I915_WRITE(reg, val);
59c859d6 1688 }
23670b32 1689
040484af
JB		 1690 reg = TRANSCONF(pipe);
1691 val = I915_READ(reg);
5f7f726d 1692 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1693
1694 if (HAS_PCH_IBX(dev_priv->dev)) {
1695 /*
1696 * make the BPC in transcoder be consistent with
1697 * that in pipeconf reg.
1698 */
dfd07d72
DV		 1699 val &= ~PIPECONF_BPC_MASK;
1700 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1701 }
5f7f726d
PZ		 1702
1703 val &= ~TRANS_INTERLACE_MASK;
1704 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1705 if (HAS_PCH_IBX(dev_priv->dev) &&
1706 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1707 val |= TRANS_LEGACY_INTERLACED_ILK;
1708 else
1709 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1710 else
1711 val |= TRANS_PROGRESSIVE;
1712
040484af
JB		 1713 I915_WRITE(reg, val | TRANS_ENABLE);
1714 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1715 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1716}
1717
8fb033d7 1718static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1719 enum transcoder cpu_transcoder)
040484af 1720{
8fb033d7 1721 u32 val, pipeconf_val;
8fb033d7
PZ		 1722
1723 /* PCH only available on ILK+ */
1724 BUG_ON(dev_priv->info->gen < 5);
1725
8fb033d7 1726 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1727 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1728 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1729
223a6fdf
PZ		 1730 /* Workaround: set timing override bit. */
1731 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1732 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1733 I915_WRITE(_TRANSA_CHICKEN2, val);
1734
25f3ef11 1735 val = TRANS_ENABLE;
937bb610 1736 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1737
9a76b1c6
PZ		 1738 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1739 PIPECONF_INTERLACED_ILK)
a35f2679 1740 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1741 else
1742 val |= TRANS_PROGRESSIVE;
1743
25f3ef11 1744 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
937bb610
PZ		 1745 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1746 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1747}
1748
b8a4f404
PZ		 1749static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1750 enum pipe pipe)
040484af 1751{
23670b32
DV		 1752 struct drm_device *dev = dev_priv->dev;
1753 uint32_t reg, val;
040484af
JB		 1754
1755 /* FDI relies on the transcoder */
1756 assert_fdi_tx_disabled(dev_priv, pipe);
1757 assert_fdi_rx_disabled(dev_priv, pipe);
1758
291906f1
JB		 1759 /* Ports must be off as well */
1760 assert_pch_ports_disabled(dev_priv, pipe);
1761
040484af
JB		 1762 reg = TRANSCONF(pipe);
1763 val = I915_READ(reg);
1764 val &= ~TRANS_ENABLE;
1765 I915_WRITE(reg, val);
1766 /* wait for PCH transcoder off, transcoder state */
1767 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1768 DRM_ERROR("failed to disable transcoder %d\n", pipe);
23670b32
DV		 1769
1770 if (!HAS_PCH_IBX(dev)) {
1771 /* Workaround: Clear the timing override chicken bit again. */
1772 reg = TRANS_CHICKEN2(pipe);
1773 val = I915_READ(reg);
1774 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1775 I915_WRITE(reg, val);
1776 }
040484af
JB		 1777}
1778
ab4d966c 1779static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1780{
8fb033d7
PZ		 1781 u32 val;
1782
8a52fd9f 1783 val = I915_READ(_TRANSACONF);
8fb033d7 1784 val &= ~TRANS_ENABLE;
8a52fd9f 1785 I915_WRITE(_TRANSACONF, val);
8fb033d7 1786 /* wait for PCH transcoder off, transcoder state */
8a52fd9f
PZ		 1787 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1788 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1789
1790 /* Workaround: clear timing override bit. */
1791 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1792 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1793 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1794}
1795
b24e7179 1796/**
309cfea8 1797 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1798 * @dev_priv: i915 private structure
1799 * @pipe: pipe to enable
040484af 1800 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1801 *
1802 * Enable @pipe, making sure that various hardware specific requirements
1803 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1804 *
1805 * @pipe should be %PIPE_A or %PIPE_B.
1806 *
1807 * Will wait until the pipe is actually running (i.e. first vblank) before
1808 * returning.
1809 */
040484af
JB		 1810static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1811 bool pch_port)
b24e7179 1812{
702e7a56
PZ		 1813 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1814 pipe);
1a240d4d 1815 enum pipe pch_transcoder;
b24e7179
JB		 1816 int reg;
1817 u32 val;
1818
681e5811 1819 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1820 pch_transcoder = TRANSCODER_A;
1821 else
1822 pch_transcoder = pipe;
1823
b24e7179
JB		 1824 /*
1825 * A pipe without a PLL won't actually be able to drive bits from
1826 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1827 * need the check.
1828 */
1829 if (!HAS_PCH_SPLIT(dev_priv->dev))
1830 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1831 else {
1832 if (pch_port) {
1833 /* if driving the PCH, we need FDI enabled */
cc391bbb 1834 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1835 assert_fdi_tx_pll_enabled(dev_priv,
1836 (enum pipe) cpu_transcoder);
040484af
JB		 1837 }
1838 /* FIXME: assert CPU port conditions for SNB+ */
1839 }
b24e7179 1840
702e7a56 1841 reg = PIPECONF(cpu_transcoder);
b24e7179 1842 val = I915_READ(reg);
00d70b15
CW		 1843 if (val & PIPECONF_ENABLE)
1844 return;
1845
1846 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1847 intel_wait_for_vblank(dev_priv->dev, pipe);
1848}
1849
1850/**
309cfea8 1851 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1852 * @dev_priv: i915 private structure
1853 * @pipe: pipe to disable
1854 *
1855 * Disable @pipe, making sure that various hardware specific requirements
1856 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1857 *
1858 * @pipe should be %PIPE_A or %PIPE_B.
1859 *
1860 * Will wait until the pipe has shut down before returning.
1861 */
1862static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1863 enum pipe pipe)
1864{
702e7a56
PZ		 1865 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1866 pipe);
b24e7179
JB		 1867 int reg;
1868 u32 val;
1869
1870 /*
1871 * Make sure planes won't keep trying to pump pixels to us,
1872 * or we might hang the display.
1873 */
1874 assert_planes_disabled(dev_priv, pipe);
1875
1876 /* Don't disable pipe A or pipe A PLLs if needed */
1877 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1878 return;
1879
702e7a56 1880 reg = PIPECONF(cpu_transcoder);
b24e7179 1881 val = I915_READ(reg);
00d70b15
CW		 1882 if ((val & PIPECONF_ENABLE) == 0)
1883 return;
1884
1885 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1886 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1887}
1888
d74362c9
KP		 1889/*
1890 * Plane regs are double buffered, going from enabled->disabled needs a
1891 * trigger in order to latch. The display address reg provides this.
1892 */
6f1d69b0 1893void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1894 enum plane plane)
1895{
14f86147
DL		 1896 if (dev_priv->info->gen >= 4)
1897 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1898 else
1899 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1900}
1901
b24e7179
JB		 1902/**
1903 * intel_enable_plane - enable a display plane on a given pipe
1904 * @dev_priv: i915 private structure
1905 * @plane: plane to enable
1906 * @pipe: pipe being fed
1907 *
1908 * Enable @plane on @pipe, making sure that @pipe is running first.
1909 */
1910static void intel_enable_plane(struct drm_i915_private *dev_priv,
1911 enum plane plane, enum pipe pipe)
1912{
1913 int reg;
1914 u32 val;
1915
1916 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1917 assert_pipe_enabled(dev_priv, pipe);
1918
1919 reg = DSPCNTR(plane);
1920 val = I915_READ(reg);
00d70b15
CW		 1921 if (val & DISPLAY_PLANE_ENABLE)
1922 return;
1923
1924 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1925 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1926 intel_wait_for_vblank(dev_priv->dev, pipe);
1927}
1928
b24e7179
JB		 1929/**
1930 * intel_disable_plane - disable a display plane
1931 * @dev_priv: i915 private structure
1932 * @plane: plane to disable
1933 * @pipe: pipe consuming the data
1934 *
1935 * Disable @plane; should be an independent operation.
1936 */
1937static void intel_disable_plane(struct drm_i915_private *dev_priv,
1938 enum plane plane, enum pipe pipe)
1939{
1940 int reg;
1941 u32 val;
1942
1943 reg = DSPCNTR(plane);
1944 val = I915_READ(reg);
00d70b15
CW		 1945 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1946 return;
1947
1948 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1949 intel_flush_display_plane(dev_priv, plane);
1950 intel_wait_for_vblank(dev_priv->dev, pipe);
1951}
1952
127bd2ac 1953int
48b956c5 1954intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1955 struct drm_i915_gem_object *obj,
919926ae 1956 struct intel_ring_buffer *pipelined)
6b95a207 1957{
ce453d81 1958 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1959 u32 alignment;
1960 int ret;
1961
05394f39 1962 switch (obj->tiling_mode) {
6b95a207 1963 case I915_TILING_NONE:
534843da
CW		 1964 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1965 alignment = 128 * 1024;
a6c45cf0 1966 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1967 alignment = 4 * 1024;
1968 else
1969 alignment = 64 * 1024;
6b95a207
KH		 1970 break;
1971 case I915_TILING_X:
1972 /* pin() will align the object as required by fence */
1973 alignment = 0;
1974 break;
1975 case I915_TILING_Y:
1976 /* FIXME: Is this true? */
1977 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1978 return -EINVAL;
1979 default:
1980 BUG();
1981 }
1982
ce453d81 1983 dev_priv->mm.interruptible = false;
2da3b9b9 1984 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1985 if (ret)
ce453d81 1986 goto err_interruptible;
6b95a207
KH		 1987
1988 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1989 * fence, whereas 965+ only requires a fence if using
1990 * framebuffer compression. For simplicity, we always install
1991 * a fence as the cost is not that onerous.
1992 */
06d98131 1993 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1994 if (ret)
1995 goto err_unpin;
1690e1eb 1996
9a5a53b3 1997 i915_gem_object_pin_fence(obj);
6b95a207 1998
ce453d81 1999 dev_priv->mm.interruptible = true;
6b95a207 2000 return 0;
48b956c5
CW		 2001
2002err_unpin:
2003 i915_gem_object_unpin(obj);
ce453d81
CW		 2004err_interruptible:
2005 dev_priv->mm.interruptible = true;
48b956c5 2006 return ret;
6b95a207
KH		 2007}
2008
1690e1eb
CW		 2009void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2010{
2011 i915_gem_object_unpin_fence(obj);
2012 i915_gem_object_unpin(obj);
2013}
2014
c2c75131
DV		 2015/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2016 * is assumed to be a power-of-two. */
bc752862
CW		 2017unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2018 unsigned int tiling_mode,
2019 unsigned int cpp,
2020 unsigned int pitch)
c2c75131 2021{
bc752862
CW		 2022 if (tiling_mode != I915_TILING_NONE) {
2023 unsigned int tile_rows, tiles;
c2c75131 2024
bc752862
CW		 2025 tile_rows = *y / 8;
2026 *y %= 8;
c2c75131 2027
bc752862
CW		 2028 tiles = *x / (512/cpp);
2029 *x %= 512/cpp;
2030
2031 return tile_rows * pitch * 8 + tiles * 4096;
2032 } else {
2033 unsigned int offset;
2034
2035 offset = *y * pitch + *x * cpp;
2036 *y = 0;
2037 *x = (offset & 4095) / cpp;
2038 return offset & -4096;
2039 }
c2c75131
DV		 2040}
2041
17638cd6
JB		 2042static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2043 int x, int y)
81255565
JB		 2044{
2045 struct drm_device *dev = crtc->dev;
2046 struct drm_i915_private *dev_priv = dev->dev_private;
2047 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2048 struct intel_framebuffer *intel_fb;
05394f39 2049 struct drm_i915_gem_object *obj;
81255565 2050 int plane = intel_crtc->plane;
e506a0c6 2051 unsigned long linear_offset;
81255565 2052 u32 dspcntr;
5eddb70b 2053 u32 reg;
81255565
JB		 2054
2055 switch (plane) {
2056 case 0:
2057 case 1:
2058 break;
2059 default:
2060 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2061 return -EINVAL;
2062 }
2063
2064 intel_fb = to_intel_framebuffer(fb);
2065 obj = intel_fb->obj;
81255565 2066
5eddb70b
CW		 2067 reg = DSPCNTR(plane);
2068 dspcntr = I915_READ(reg);
81255565
JB		 2069 /* Mask out pixel format bits in case we change it */
2070 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2071 switch (fb->pixel_format) {
2072 case DRM_FORMAT_C8:
81255565
JB		 2073 dspcntr |= DISPPLANE_8BPP;
2074 break;
57779d06
VS		 2075 case DRM_FORMAT_XRGB1555:
2076 case DRM_FORMAT_ARGB1555:
2077 dspcntr |= DISPPLANE_BGRX555;
81255565 2078 break;
57779d06
VS		 2079 case DRM_FORMAT_RGB565:
2080 dspcntr |= DISPPLANE_BGRX565;
2081 break;
2082 case DRM_FORMAT_XRGB8888:
2083 case DRM_FORMAT_ARGB8888:
2084 dspcntr |= DISPPLANE_BGRX888;
2085 break;
2086 case DRM_FORMAT_XBGR8888:
2087 case DRM_FORMAT_ABGR8888:
2088 dspcntr |= DISPPLANE_RGBX888;
2089 break;
2090 case DRM_FORMAT_XRGB2101010:
2091 case DRM_FORMAT_ARGB2101010:
2092 dspcntr |= DISPPLANE_BGRX101010;
2093 break;
2094 case DRM_FORMAT_XBGR2101010:
2095 case DRM_FORMAT_ABGR2101010:
2096 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2097 break;
2098 default:
57779d06 2099 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
81255565
JB		 2100 return -EINVAL;
2101 }
57779d06 2102
a6c45cf0 2103 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2104 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2105 dspcntr |= DISPPLANE_TILED;
2106 else
2107 dspcntr &= ~DISPPLANE_TILED;
2108 }
2109
5eddb70b 2110 I915_WRITE(reg, dspcntr);
81255565 2111
e506a0c6 2112 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2113
c2c75131
DV		 2114 if (INTEL_INFO(dev)->gen >= 4) {
2115 intel_crtc->dspaddr_offset =
bc752862
CW		 2116 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2117 fb->bits_per_pixel / 8,
2118 fb->pitches[0]);
c2c75131
DV		 2119 linear_offset -= intel_crtc->dspaddr_offset;
2120 } else {
e506a0c6 2121 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2122 }
e506a0c6
DV		 2123
2124 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2125 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2126 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2127 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2128 I915_MODIFY_DISPBASE(DSPSURF(plane),
2129 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2130 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2131 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2132 } else
e506a0c6 2133 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2134 POSTING_READ(reg);
81255565 2135
17638cd6
JB		 2136 return 0;
2137}
2138
2139static int ironlake_update_plane(struct drm_crtc *crtc,
2140 struct drm_framebuffer *fb, int x, int y)
2141{
2142 struct drm_device *dev = crtc->dev;
2143 struct drm_i915_private *dev_priv = dev->dev_private;
2144 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2145 struct intel_framebuffer *intel_fb;
2146 struct drm_i915_gem_object *obj;
2147 int plane = intel_crtc->plane;
e506a0c6 2148 unsigned long linear_offset;
17638cd6
JB		 2149 u32 dspcntr;
2150 u32 reg;
2151
2152 switch (plane) {
2153 case 0:
2154 case 1:
27f8227b 2155 case 2:
17638cd6
JB		 2156 break;
2157 default:
2158 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2159 return -EINVAL;
2160 }
2161
2162 intel_fb = to_intel_framebuffer(fb);
2163 obj = intel_fb->obj;
2164
2165 reg = DSPCNTR(plane);
2166 dspcntr = I915_READ(reg);
2167 /* Mask out pixel format bits in case we change it */
2168 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2169 switch (fb->pixel_format) {
2170 case DRM_FORMAT_C8:
17638cd6
JB		 2171 dspcntr |= DISPPLANE_8BPP;
2172 break;
57779d06
VS		 2173 case DRM_FORMAT_RGB565:
2174 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2175 break;
57779d06
VS		 2176 case DRM_FORMAT_XRGB8888:
2177 case DRM_FORMAT_ARGB8888:
2178 dspcntr |= DISPPLANE_BGRX888;
2179 break;
2180 case DRM_FORMAT_XBGR8888:
2181 case DRM_FORMAT_ABGR8888:
2182 dspcntr |= DISPPLANE_RGBX888;
2183 break;
2184 case DRM_FORMAT_XRGB2101010:
2185 case DRM_FORMAT_ARGB2101010:
2186 dspcntr |= DISPPLANE_BGRX101010;
2187 break;
2188 case DRM_FORMAT_XBGR2101010:
2189 case DRM_FORMAT_ABGR2101010:
2190 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2191 break;
2192 default:
57779d06 2193 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
17638cd6
JB		 2194 return -EINVAL;
2195 }
2196
2197 if (obj->tiling_mode != I915_TILING_NONE)
2198 dspcntr |= DISPPLANE_TILED;
2199 else
2200 dspcntr &= ~DISPPLANE_TILED;
2201
2202 /* must disable */
2203 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2204
2205 I915_WRITE(reg, dspcntr);
2206
e506a0c6 2207 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2208 intel_crtc->dspaddr_offset =
bc752862
CW		 2209 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2210 fb->bits_per_pixel / 8,
2211 fb->pitches[0]);
c2c75131 2212 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2213
e506a0c6
DV		 2214 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2215 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2216 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2217 I915_MODIFY_DISPBASE(DSPSURF(plane),
2218 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2219 if (IS_HASWELL(dev)) {
2220 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2221 } else {
2222 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2223 I915_WRITE(DSPLINOFF(plane), linear_offset);
2224 }
17638cd6
JB		 2225 POSTING_READ(reg);
2226
2227 return 0;
2228}
2229
2230/* Assume fb object is pinned & idle & fenced and just update base pointers */
2231static int
2232intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2233 int x, int y, enum mode_set_atomic state)
2234{
2235 struct drm_device *dev = crtc->dev;
2236 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2237
6b8e6ed0
CW		 2238 if (dev_priv->display.disable_fbc)
2239 dev_priv->display.disable_fbc(dev);
3dec0095 2240 intel_increase_pllclock(crtc);
81255565 2241
6b8e6ed0 2242 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2243}
2244
96a02917
VS		 2245void intel_display_handle_reset(struct drm_device *dev)
2246{
2247 struct drm_i915_private *dev_priv = dev->dev_private;
2248 struct drm_crtc *crtc;
2249
2250 /*
2251 * Flips in the rings have been nuked by the reset,
2252 * so complete all pending flips so that user space
2253 * will get its events and not get stuck.
2254 *
2255 * Also update the base address of all primary
2256 * planes to the the last fb to make sure we're
2257 * showing the correct fb after a reset.
2258 *
2259 * Need to make two loops over the crtcs so that we
2260 * don't try to grab a crtc mutex before the
2261 * pending_flip_queue really got woken up.
2262 */
2263
2264 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2265 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2266 enum plane plane = intel_crtc->plane;
2267
2268 intel_prepare_page_flip(dev, plane);
2269 intel_finish_page_flip_plane(dev, plane);
2270 }
2271
2272 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2273 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2274
2275 mutex_lock(&crtc->mutex);
2276 if (intel_crtc->active)
2277 dev_priv->display.update_plane(crtc, crtc->fb,
2278 crtc->x, crtc->y);
2279 mutex_unlock(&crtc->mutex);
2280 }
2281}
2282
14667a4b
CW		 2283static int
2284intel_finish_fb(struct drm_framebuffer *old_fb)
2285{
2286 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2287 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2288 bool was_interruptible = dev_priv->mm.interruptible;
2289 int ret;
2290
14667a4b
CW		 2291 /* Big Hammer, we also need to ensure that any pending
2292 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2293 * current scanout is retired before unpinning the old
2294 * framebuffer.
2295 *
2296 * This should only fail upon a hung GPU, in which case we
2297 * can safely continue.
2298 */
2299 dev_priv->mm.interruptible = false;
2300 ret = i915_gem_object_finish_gpu(obj);
2301 dev_priv->mm.interruptible = was_interruptible;
2302
2303 return ret;
2304}
2305
198598d0
VS		 2306static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2307{
2308 struct drm_device *dev = crtc->dev;
2309 struct drm_i915_master_private *master_priv;
2310 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2311
2312 if (!dev->primary->master)
2313 return;
2314
2315 master_priv = dev->primary->master->driver_priv;
2316 if (!master_priv->sarea_priv)
2317 return;
2318
2319 switch (intel_crtc->pipe) {
2320 case 0:
2321 master_priv->sarea_priv->pipeA_x = x;
2322 master_priv->sarea_priv->pipeA_y = y;
2323 break;
2324 case 1:
2325 master_priv->sarea_priv->pipeB_x = x;
2326 master_priv->sarea_priv->pipeB_y = y;
2327 break;
2328 default:
2329 break;
2330 }
2331}
2332
5c3b82e2 2333static int
3c4fdcfb 2334intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2335 struct drm_framebuffer *fb)
79e53945
JB		 2336{
2337 struct drm_device *dev = crtc->dev;
6b8e6ed0 2338 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2339 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2340 struct drm_framebuffer *old_fb;
5c3b82e2 2341 int ret;
79e53945
JB		 2342
2343 /* no fb bound */
94352cf9 2344 if (!fb) {
a5071c2f 2345 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2346 return 0;
2347 }
2348
7eb552ae 2349 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
5826eca5
ED		 2350 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2351 intel_crtc->plane,
7eb552ae 2352 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2353 return -EINVAL;
79e53945
JB		 2354 }
2355
5c3b82e2 2356 mutex_lock(&dev->struct_mutex);
265db958 2357 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2358 to_intel_framebuffer(fb)->obj,
919926ae 2359 NULL);
5c3b82e2
CW		 2360 if (ret != 0) {
2361 mutex_unlock(&dev->struct_mutex);
a5071c2f 2362 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2363 return ret;
2364 }
79e53945 2365
94352cf9 2366 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2367 if (ret) {
94352cf9 2368 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2369 mutex_unlock(&dev->struct_mutex);
a5071c2f 2370 DRM_ERROR("failed to update base address\n");
4e6cfefc 2371 return ret;
79e53945 2372 }
3c4fdcfb 2373
94352cf9
DV		 2374 old_fb = crtc->fb;
2375 crtc->fb = fb;
6c4c86f5
DV		 2376 crtc->x = x;
2377 crtc->y = y;
94352cf9 2378
b7f1de28
CW		 2379 if (old_fb) {
2380 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2381 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2382 }
652c393a 2383
6b8e6ed0 2384 intel_update_fbc(dev);
5c3b82e2 2385 mutex_unlock(&dev->struct_mutex);
79e53945 2386
198598d0 2387 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2388
2389 return 0;
79e53945
JB		 2390}
2391
5e84e1a4
ZW		 2392static void intel_fdi_normal_train(struct drm_crtc *crtc)
2393{
2394 struct drm_device *dev = crtc->dev;
2395 struct drm_i915_private *dev_priv = dev->dev_private;
2396 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2397 int pipe = intel_crtc->pipe;
2398 u32 reg, temp;
2399
2400 /* enable normal train */
2401 reg = FDI_TX_CTL(pipe);
2402 temp = I915_READ(reg);
61e499bf 2403 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2404 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2405 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2406 } else {
2407 temp &= ~FDI_LINK_TRAIN_NONE;
2408 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2409 }
5e84e1a4
ZW		 2410 I915_WRITE(reg, temp);
2411
2412 reg = FDI_RX_CTL(pipe);
2413 temp = I915_READ(reg);
2414 if (HAS_PCH_CPT(dev)) {
2415 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2416 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2417 } else {
2418 temp &= ~FDI_LINK_TRAIN_NONE;
2419 temp |= FDI_LINK_TRAIN_NONE;
2420 }
2421 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2422
2423 /* wait one idle pattern time */
2424 POSTING_READ(reg);
2425 udelay(1000);
357555c0
JB		 2426
2427 /* IVB wants error correction enabled */
2428 if (IS_IVYBRIDGE(dev))
2429 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2430 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2431}
2432
01a415fd
DV		 2433static void ivb_modeset_global_resources(struct drm_device *dev)
2434{
2435 struct drm_i915_private *dev_priv = dev->dev_private;
2436 struct intel_crtc *pipe_B_crtc =
2437 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2438 struct intel_crtc *pipe_C_crtc =
2439 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2440 uint32_t temp;
2441
2442 /* When everything is off disable fdi C so that we could enable fdi B
2443 * with all lanes. XXX: This misses the case where a pipe is not using
2444 * any pch resources and so doesn't need any fdi lanes. */
2445 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2446 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2447 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2448
2449 temp = I915_READ(SOUTH_CHICKEN1);
2450 temp &= ~FDI_BC_BIFURCATION_SELECT;
2451 DRM_DEBUG_KMS("disabling fdi C rx\n");
2452 I915_WRITE(SOUTH_CHICKEN1, temp);
2453 }
2454}
2455
8db9d77b
ZW		 2456/* The FDI link training functions for ILK/Ibexpeak. */
2457static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2458{
2459 struct drm_device *dev = crtc->dev;
2460 struct drm_i915_private *dev_priv = dev->dev_private;
2461 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2462 int pipe = intel_crtc->pipe;
0fc932b8 2463 int plane = intel_crtc->plane;
5eddb70b 2464 u32 reg, temp, tries;
8db9d77b 2465
0fc932b8
JB		 2466 /* FDI needs bits from pipe & plane first */
2467 assert_pipe_enabled(dev_priv, pipe);
2468 assert_plane_enabled(dev_priv, plane);
2469
e1a44743
AJ		 2470 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2471 for train result */
5eddb70b
CW		 2472 reg = FDI_RX_IMR(pipe);
2473 temp = I915_READ(reg);
e1a44743
AJ		 2474 temp &= ~FDI_RX_SYMBOL_LOCK;
2475 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2476 I915_WRITE(reg, temp);
2477 I915_READ(reg);
e1a44743
AJ		 2478 udelay(150);
2479
8db9d77b 2480 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2481 reg = FDI_TX_CTL(pipe);
2482 temp = I915_READ(reg);
77ffb597
AJ		 2483 temp &= ~(7 << 19);
2484 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2485 temp &= ~FDI_LINK_TRAIN_NONE;
2486 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2487 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2488
5eddb70b
CW		 2489 reg = FDI_RX_CTL(pipe);
2490 temp = I915_READ(reg);
8db9d77b
ZW		 2491 temp &= ~FDI_LINK_TRAIN_NONE;
2492 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2493 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2494
2495 POSTING_READ(reg);
8db9d77b
ZW		 2496 udelay(150);
2497
5b2adf89 2498 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2499 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2500 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2501 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2502
5eddb70b 2503 reg = FDI_RX_IIR(pipe);
e1a44743 2504 for (tries = 0; tries < 5; tries++) {
5eddb70b 2505 temp = I915_READ(reg);
8db9d77b
ZW		 2506 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2507
2508 if ((temp & FDI_RX_BIT_LOCK)) {
2509 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2510 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2511 break;
2512 }
8db9d77b 2513 }
e1a44743 2514 if (tries == 5)
5eddb70b 2515 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2516
2517 /* Train 2 */
5eddb70b
CW		 2518 reg = FDI_TX_CTL(pipe);
2519 temp = I915_READ(reg);
8db9d77b
ZW		 2520 temp &= ~FDI_LINK_TRAIN_NONE;
2521 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2522 I915_WRITE(reg, temp);
8db9d77b 2523
5eddb70b
CW		 2524 reg = FDI_RX_CTL(pipe);
2525 temp = I915_READ(reg);
8db9d77b
ZW		 2526 temp &= ~FDI_LINK_TRAIN_NONE;
2527 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2528 I915_WRITE(reg, temp);
8db9d77b 2529
5eddb70b
CW		 2530 POSTING_READ(reg);
2531 udelay(150);
8db9d77b 2532
5eddb70b 2533 reg = FDI_RX_IIR(pipe);
e1a44743 2534 for (tries = 0; tries < 5; tries++) {
5eddb70b 2535 temp = I915_READ(reg);
8db9d77b
ZW		 2536 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2537
2538 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2539 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2540 DRM_DEBUG_KMS("FDI train 2 done.\n");
2541 break;
2542 }
8db9d77b 2543 }
e1a44743 2544 if (tries == 5)
5eddb70b 2545 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2546
2547 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2548
8db9d77b
ZW		 2549}
2550
0206e353 2551static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2552 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2553 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2554 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2555 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2556};
2557
2558/* The FDI link training functions for SNB/Cougarpoint. */
2559static void gen6_fdi_link_train(struct drm_crtc *crtc)
2560{
2561 struct drm_device *dev = crtc->dev;
2562 struct drm_i915_private *dev_priv = dev->dev_private;
2563 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2564 int pipe = intel_crtc->pipe;
fa37d39e 2565 u32 reg, temp, i, retry;
8db9d77b 2566
e1a44743
AJ		 2567 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2568 for train result */
5eddb70b
CW		 2569 reg = FDI_RX_IMR(pipe);
2570 temp = I915_READ(reg);
e1a44743
AJ		 2571 temp &= ~FDI_RX_SYMBOL_LOCK;
2572 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2573 I915_WRITE(reg, temp);
2574
2575 POSTING_READ(reg);
e1a44743
AJ		 2576 udelay(150);
2577
8db9d77b 2578 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2579 reg = FDI_TX_CTL(pipe);
2580 temp = I915_READ(reg);
77ffb597
AJ		 2581 temp &= ~(7 << 19);
2582 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2583 temp &= ~FDI_LINK_TRAIN_NONE;
2584 temp |= FDI_LINK_TRAIN_PATTERN_1;
2585 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2586 /* SNB-B */
2587 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2588 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2589
d74cf324
DV		 2590 I915_WRITE(FDI_RX_MISC(pipe),
2591 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2592
5eddb70b
CW		 2593 reg = FDI_RX_CTL(pipe);
2594 temp = I915_READ(reg);
8db9d77b
ZW		 2595 if (HAS_PCH_CPT(dev)) {
2596 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2597 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2598 } else {
2599 temp &= ~FDI_LINK_TRAIN_NONE;
2600 temp |= FDI_LINK_TRAIN_PATTERN_1;
2601 }
5eddb70b
CW		 2602 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2603
2604 POSTING_READ(reg);
8db9d77b
ZW		 2605 udelay(150);
2606
0206e353 2607 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2608 reg = FDI_TX_CTL(pipe);
2609 temp = I915_READ(reg);
8db9d77b
ZW		 2610 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2611 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2612 I915_WRITE(reg, temp);
2613
2614 POSTING_READ(reg);
8db9d77b
ZW		 2615 udelay(500);
2616
fa37d39e
SP		 2617 for (retry = 0; retry < 5; retry++) {
2618 reg = FDI_RX_IIR(pipe);
2619 temp = I915_READ(reg);
2620 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2621 if (temp & FDI_RX_BIT_LOCK) {
2622 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2623 DRM_DEBUG_KMS("FDI train 1 done.\n");
2624 break;
2625 }
2626 udelay(50);
8db9d77b 2627 }
fa37d39e
SP		 2628 if (retry < 5)
2629 break;
8db9d77b
ZW		 2630 }
2631 if (i == 4)
5eddb70b 2632 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2633
2634 /* Train 2 */
5eddb70b
CW		 2635 reg = FDI_TX_CTL(pipe);
2636 temp = I915_READ(reg);
8db9d77b
ZW		 2637 temp &= ~FDI_LINK_TRAIN_NONE;
2638 temp |= FDI_LINK_TRAIN_PATTERN_2;
2639 if (IS_GEN6(dev)) {
2640 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2641 /* SNB-B */
2642 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2643 }
5eddb70b 2644 I915_WRITE(reg, temp);
8db9d77b 2645
5eddb70b
CW		 2646 reg = FDI_RX_CTL(pipe);
2647 temp = I915_READ(reg);
8db9d77b
ZW		 2648 if (HAS_PCH_CPT(dev)) {
2649 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2650 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2651 } else {
2652 temp &= ~FDI_LINK_TRAIN_NONE;
2653 temp |= FDI_LINK_TRAIN_PATTERN_2;
2654 }
5eddb70b
CW		 2655 I915_WRITE(reg, temp);
2656
2657 POSTING_READ(reg);
8db9d77b
ZW		 2658 udelay(150);
2659
0206e353 2660 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2661 reg = FDI_TX_CTL(pipe);
2662 temp = I915_READ(reg);
8db9d77b
ZW		 2663 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2664 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2665 I915_WRITE(reg, temp);
2666
2667 POSTING_READ(reg);
8db9d77b
ZW		 2668 udelay(500);
2669
fa37d39e
SP		 2670 for (retry = 0; retry < 5; retry++) {
2671 reg = FDI_RX_IIR(pipe);
2672 temp = I915_READ(reg);
2673 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2674 if (temp & FDI_RX_SYMBOL_LOCK) {
2675 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2676 DRM_DEBUG_KMS("FDI train 2 done.\n");
2677 break;
2678 }
2679 udelay(50);
8db9d77b 2680 }
fa37d39e
SP		 2681 if (retry < 5)
2682 break;
8db9d77b
ZW		 2683 }
2684 if (i == 4)
5eddb70b 2685 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2686
2687 DRM_DEBUG_KMS("FDI train done.\n");
2688}
2689
357555c0
JB		 2690/* Manual link training for Ivy Bridge A0 parts */
2691static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2692{
2693 struct drm_device *dev = crtc->dev;
2694 struct drm_i915_private *dev_priv = dev->dev_private;
2695 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2696 int pipe = intel_crtc->pipe;
2697 u32 reg, temp, i;
2698
2699 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2700 for train result */
2701 reg = FDI_RX_IMR(pipe);
2702 temp = I915_READ(reg);
2703 temp &= ~FDI_RX_SYMBOL_LOCK;
2704 temp &= ~FDI_RX_BIT_LOCK;
2705 I915_WRITE(reg, temp);
2706
2707 POSTING_READ(reg);
2708 udelay(150);
2709
01a415fd
DV		 2710 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2711 I915_READ(FDI_RX_IIR(pipe)));
2712
357555c0
JB		 2713 /* enable CPU FDI TX and PCH FDI RX */
2714 reg = FDI_TX_CTL(pipe);
2715 temp = I915_READ(reg);
2716 temp &= ~(7 << 19);
2717 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2718 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2719 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2720 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2721 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2722 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2723 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2724
d74cf324
DV		 2725 I915_WRITE(FDI_RX_MISC(pipe),
2726 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2727
357555c0
JB		 2728 reg = FDI_RX_CTL(pipe);
2729 temp = I915_READ(reg);
2730 temp &= ~FDI_LINK_TRAIN_AUTO;
2731 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2732 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2733 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2734 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2735
2736 POSTING_READ(reg);
2737 udelay(150);
2738
0206e353 2739 for (i = 0; i < 4; i++) {
357555c0
JB		 2740 reg = FDI_TX_CTL(pipe);
2741 temp = I915_READ(reg);
2742 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2743 temp |= snb_b_fdi_train_param[i];
2744 I915_WRITE(reg, temp);
2745
2746 POSTING_READ(reg);
2747 udelay(500);
2748
2749 reg = FDI_RX_IIR(pipe);
2750 temp = I915_READ(reg);
2751 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2752
2753 if (temp & FDI_RX_BIT_LOCK ||
2754 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2755 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2756 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2757 break;
2758 }
2759 }
2760 if (i == 4)
2761 DRM_ERROR("FDI train 1 fail!\n");
2762
2763 /* Train 2 */
2764 reg = FDI_TX_CTL(pipe);
2765 temp = I915_READ(reg);
2766 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2767 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2768 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2769 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2770 I915_WRITE(reg, temp);
2771
2772 reg = FDI_RX_CTL(pipe);
2773 temp = I915_READ(reg);
2774 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2775 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2776 I915_WRITE(reg, temp);
2777
2778 POSTING_READ(reg);
2779 udelay(150);
2780
0206e353 2781 for (i = 0; i < 4; i++) {
357555c0
JB		 2782 reg = FDI_TX_CTL(pipe);
2783 temp = I915_READ(reg);
2784 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2785 temp |= snb_b_fdi_train_param[i];
2786 I915_WRITE(reg, temp);
2787
2788 POSTING_READ(reg);
2789 udelay(500);
2790
2791 reg = FDI_RX_IIR(pipe);
2792 temp = I915_READ(reg);
2793 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2794
2795 if (temp & FDI_RX_SYMBOL_LOCK) {
2796 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2797 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2798 break;
2799 }
2800 }
2801 if (i == 4)
2802 DRM_ERROR("FDI train 2 fail!\n");
2803
2804 DRM_DEBUG_KMS("FDI train done.\n");
2805}
2806
88cefb6c 2807static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2808{
88cefb6c 2809 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2810 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2811 int pipe = intel_crtc->pipe;
5eddb70b 2812 u32 reg, temp;
79e53945 2813
c64e311e 2814
c98e9dcf 2815 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2816 reg = FDI_RX_CTL(pipe);
2817 temp = I915_READ(reg);
2818 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2819 temp |= (intel_crtc->fdi_lanes - 1) << 19;
dfd07d72 2820 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2821 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2822
2823 POSTING_READ(reg);
c98e9dcf
JB		 2824 udelay(200);
2825
2826 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2827 temp = I915_READ(reg);
2828 I915_WRITE(reg, temp | FDI_PCDCLK);
2829
2830 POSTING_READ(reg);
c98e9dcf
JB		 2831 udelay(200);
2832
20749730
PZ		 2833 /* Enable CPU FDI TX PLL, always on for Ironlake */
2834 reg = FDI_TX_CTL(pipe);
2835 temp = I915_READ(reg);
2836 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2837 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2838
20749730
PZ		 2839 POSTING_READ(reg);
2840 udelay(100);
6be4a607 2841 }
0e23b99d
JB		 2842}
2843
88cefb6c
DV		 2844static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2845{
2846 struct drm_device *dev = intel_crtc->base.dev;
2847 struct drm_i915_private *dev_priv = dev->dev_private;
2848 int pipe = intel_crtc->pipe;
2849 u32 reg, temp;
2850
2851 /* Switch from PCDclk to Rawclk */
2852 reg = FDI_RX_CTL(pipe);
2853 temp = I915_READ(reg);
2854 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2855
2856 /* Disable CPU FDI TX PLL */
2857 reg = FDI_TX_CTL(pipe);
2858 temp = I915_READ(reg);
2859 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2860
2861 POSTING_READ(reg);
2862 udelay(100);
2863
2864 reg = FDI_RX_CTL(pipe);
2865 temp = I915_READ(reg);
2866 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2867
2868 /* Wait for the clocks to turn off. */
2869 POSTING_READ(reg);
2870 udelay(100);
2871}
2872
0fc932b8
JB		 2873static void ironlake_fdi_disable(struct drm_crtc *crtc)
2874{
2875 struct drm_device *dev = crtc->dev;
2876 struct drm_i915_private *dev_priv = dev->dev_private;
2877 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2878 int pipe = intel_crtc->pipe;
2879 u32 reg, temp;
2880
2881 /* disable CPU FDI tx and PCH FDI rx */
2882 reg = FDI_TX_CTL(pipe);
2883 temp = I915_READ(reg);
2884 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2885 POSTING_READ(reg);
2886
2887 reg = FDI_RX_CTL(pipe);
2888 temp = I915_READ(reg);
2889 temp &= ~(0x7 << 16);
dfd07d72 2890 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2891 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2892
2893 POSTING_READ(reg);
2894 udelay(100);
2895
2896 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2897 if (HAS_PCH_IBX(dev)) {
2898 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2899 }
0fc932b8
JB		 2900
2901 /* still set train pattern 1 */
2902 reg = FDI_TX_CTL(pipe);
2903 temp = I915_READ(reg);
2904 temp &= ~FDI_LINK_TRAIN_NONE;
2905 temp |= FDI_LINK_TRAIN_PATTERN_1;
2906 I915_WRITE(reg, temp);
2907
2908 reg = FDI_RX_CTL(pipe);
2909 temp = I915_READ(reg);
2910 if (HAS_PCH_CPT(dev)) {
2911 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2912 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2913 } else {
2914 temp &= ~FDI_LINK_TRAIN_NONE;
2915 temp |= FDI_LINK_TRAIN_PATTERN_1;
2916 }
2917 /* BPC in FDI rx is consistent with that in PIPECONF */
2918 temp &= ~(0x07 << 16);
dfd07d72 2919 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2920 I915_WRITE(reg, temp);
2921
2922 POSTING_READ(reg);
2923 udelay(100);
2924}
2925
5bb61643
CW		 2926static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2927{
2928 struct drm_device *dev = crtc->dev;
2929 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2930 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2931 unsigned long flags;
2932 bool pending;
2933
10d83730
VS		 2934 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2935 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2936 return false;
2937
2938 spin_lock_irqsave(&dev->event_lock, flags);
2939 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2940 spin_unlock_irqrestore(&dev->event_lock, flags);
2941
2942 return pending;
2943}
2944
e6c3a2a6
CW		 2945static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2946{
0f91128d 2947 struct drm_device *dev = crtc->dev;
5bb61643 2948 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2949
2950 if (crtc->fb == NULL)
2951 return;
2952
2c10d571
DV		 2953 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2954
5bb61643
CW		 2955 wait_event(dev_priv->pending_flip_queue,
2956 !intel_crtc_has_pending_flip(crtc));
2957
0f91128d
CW		 2958 mutex_lock(&dev->struct_mutex);
2959 intel_finish_fb(crtc->fb);
2960 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2961}
2962
fc316cbe 2963static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
040484af
JB		 2964{
2965 struct drm_device *dev = crtc->dev;
228d3e36 2966 struct intel_encoder *intel_encoder;
040484af
JB		 2967
2968 /*
2969 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2970 * must be driven by its own crtc; no sharing is possible.
2971 */
228d3e36 2972 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
228d3e36 2973 switch (intel_encoder->type) {
040484af 2974 case INTEL_OUTPUT_EDP:
228d3e36 2975 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
040484af
JB		 2976 return false;
2977 continue;
2978 }
2979 }
2980
2981 return true;
2982}
2983
fc316cbe
PZ		 2984static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2985{
2986 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2987}
2988
e615efe4
ED		 2989/* Program iCLKIP clock to the desired frequency */
2990static void lpt_program_iclkip(struct drm_crtc *crtc)
2991{
2992 struct drm_device *dev = crtc->dev;
2993 struct drm_i915_private *dev_priv = dev->dev_private;
2994 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2995 u32 temp;
2996
09153000
DV		 2997 mutex_lock(&dev_priv->dpio_lock);
2998
e615efe4
ED		 2999 /* It is necessary to ungate the pixclk gate prior to programming
3000 * the divisors, and gate it back when it is done.
3001 */
3002 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3003
3004 /* Disable SSCCTL */
3005 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3006 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3007 SBI_SSCCTL_DISABLE,
3008 SBI_ICLK);
e615efe4
ED		 3009
3010 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3011 if (crtc->mode.clock == 20000) {
3012 auxdiv = 1;
3013 divsel = 0x41;
3014 phaseinc = 0x20;
3015 } else {
3016 /* The iCLK virtual clock root frequency is in MHz,
3017 * but the crtc->mode.clock in in KHz. To get the divisors,
3018 * it is necessary to divide one by another, so we
3019 * convert the virtual clock precision to KHz here for higher
3020 * precision.
3021 */
3022 u32 iclk_virtual_root_freq = 172800 * 1000;
3023 u32 iclk_pi_range = 64;
3024 u32 desired_divisor, msb_divisor_value, pi_value;
3025
3026 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3027 msb_divisor_value = desired_divisor / iclk_pi_range;
3028 pi_value = desired_divisor % iclk_pi_range;
3029
3030 auxdiv = 0;
3031 divsel = msb_divisor_value - 2;
3032 phaseinc = pi_value;
3033 }
3034
3035 /* This should not happen with any sane values */
3036 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3037 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3038 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3039 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3040
3041 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3042 crtc->mode.clock,
3043 auxdiv,
3044 divsel,
3045 phasedir,
3046 phaseinc);
3047
3048 /* Program SSCDIVINTPHASE6 */
988d6ee8 3049 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3050 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3051 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3052 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3053 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3054 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3055 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3056 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3057
3058 /* Program SSCAUXDIV */
988d6ee8 3059 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3060 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3061 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3062 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3063
3064 /* Enable modulator and associated divider */
988d6ee8 3065 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3066 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3067 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3068
3069 /* Wait for initialization time */
3070 udelay(24);
3071
3072 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 3073
3074 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 3075}
3076
f67a559d
JB		 3077/*
3078 * Enable PCH resources required for PCH ports:
3079 * - PCH PLLs
3080 * - FDI training & RX/TX
3081 * - update transcoder timings
3082 * - DP transcoding bits
3083 * - transcoder
3084 */
3085static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3086{
3087 struct drm_device *dev = crtc->dev;
3088 struct drm_i915_private *dev_priv = dev->dev_private;
3089 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3090 int pipe = intel_crtc->pipe;
ee7b9f93 3091 u32 reg, temp;
2c07245f 3092
e7e164db
CW		 3093 assert_transcoder_disabled(dev_priv, pipe);
3094
cd986abb
DV		 3095 /* Write the TU size bits before fdi link training, so that error
3096 * detection works. */
3097 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3098 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3099
c98e9dcf 3100 /* For PCH output, training FDI link */
674cf967 3101 dev_priv->display.fdi_link_train(crtc);
2c07245f 3102
572deb37
DV		 3103 /* XXX: pch pll's can be enabled any time before we enable the PCH
3104 * transcoder, and we actually should do this to not upset any PCH
3105 * transcoder that already use the clock when we share it.
3106 *
3107 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3108 * unconditionally resets the pll - we need that to have the right LVDS
3109 * enable sequence. */
b6b4e185 3110 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 3111
303b81e0 3112 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3113 u32 sel;
4b645f14 3114
c98e9dcf 3115 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3116 switch (pipe) {
3117 default:
3118 case 0:
3119 temp |= TRANSA_DPLL_ENABLE;
3120 sel = TRANSA_DPLLB_SEL;
3121 break;
3122 case 1:
3123 temp |= TRANSB_DPLL_ENABLE;
3124 sel = TRANSB_DPLLB_SEL;
3125 break;
3126 case 2:
3127 temp |= TRANSC_DPLL_ENABLE;
3128 sel = TRANSC_DPLLB_SEL;
3129 break;
d64311ab 3130 }
ee7b9f93
JB		 3131 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3132 temp |= sel;
3133 else
3134 temp &= ~sel;
c98e9dcf 3135 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3136 }
5eddb70b 3137
d9b6cb56
JB		 3138 /* set transcoder timing, panel must allow it */
3139 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3140 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3141 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3142 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3143
5eddb70b
CW		 3144 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3145 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3146 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3147 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3148
303b81e0 3149 intel_fdi_normal_train(crtc);
5e84e1a4 3150
c98e9dcf
JB		 3151 /* For PCH DP, enable TRANS_DP_CTL */
3152 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3153 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3154 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3155 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3156 reg = TRANS_DP_CTL(pipe);
3157 temp = I915_READ(reg);
3158 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3159 TRANS_DP_SYNC_MASK |
3160 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3161 temp |= (TRANS_DP_OUTPUT_ENABLE |
3162 TRANS_DP_ENH_FRAMING);
9325c9f0 3163 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3164
3165 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3166 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3167 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3168 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3169
3170 switch (intel_trans_dp_port_sel(crtc)) {
3171 case PCH_DP_B:
5eddb70b 3172 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3173 break;
3174 case PCH_DP_C:
5eddb70b 3175 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3176 break;
3177 case PCH_DP_D:
5eddb70b 3178 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3179 break;
3180 default:
e95d41e1 3181 BUG();
32f9d658 3182 }
2c07245f 3183
5eddb70b 3184 I915_WRITE(reg, temp);
6be4a607 3185 }
b52eb4dc 3186
b8a4f404 3187 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3188}
3189
1507e5bd
PZ		 3190static void lpt_pch_enable(struct drm_crtc *crtc)
3191{
3192 struct drm_device *dev = crtc->dev;
3193 struct drm_i915_private *dev_priv = dev->dev_private;
3194 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
daed2dbb 3195 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
1507e5bd 3196
daed2dbb 3197 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3198
8c52b5e8 3199 lpt_program_iclkip(crtc);
1507e5bd 3200
0540e488 3201 /* Set transcoder timing. */
daed2dbb
PZ		 3202 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3203 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3204 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
1507e5bd 3205
daed2dbb
PZ		 3206 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3207 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3208 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3209 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
1507e5bd 3210
937bb610 3211 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3212}
3213
ee7b9f93
JB		 3214static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3215{
3216 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3217
3218 if (pll == NULL)
3219 return;
3220
3221 if (pll->refcount == 0) {
3222 WARN(1, "bad PCH PLL refcount\n");
3223 return;
3224 }
3225
3226 --pll->refcount;
3227 intel_crtc->pch_pll = NULL;
3228}
3229
3230static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3231{
3232 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3233 struct intel_pch_pll *pll;
3234 int i;
3235
3236 pll = intel_crtc->pch_pll;
3237 if (pll) {
3238 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3239 intel_crtc->base.base.id, pll->pll_reg);
3240 goto prepare;
3241 }
3242
98b6bd99
DV		 3243 if (HAS_PCH_IBX(dev_priv->dev)) {
3244 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3245 i = intel_crtc->pipe;
3246 pll = &dev_priv->pch_plls[i];
3247
3248 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3249 intel_crtc->base.base.id, pll->pll_reg);
3250
3251 goto found;
3252 }
3253
ee7b9f93
JB		 3254 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3255 pll = &dev_priv->pch_plls[i];
3256
3257 /* Only want to check enabled timings first */
3258 if (pll->refcount == 0)
3259 continue;
3260
3261 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3262 fp == I915_READ(pll->fp0_reg)) {
3263 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3264 intel_crtc->base.base.id,
3265 pll->pll_reg, pll->refcount, pll->active);
3266
3267 goto found;
3268 }
3269 }
3270
3271 /* Ok no matching timings, maybe there's a free one? */
3272 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3273 pll = &dev_priv->pch_plls[i];
3274 if (pll->refcount == 0) {
3275 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3276 intel_crtc->base.base.id, pll->pll_reg);
3277 goto found;
3278 }
3279 }
3280
3281 return NULL;
3282
3283found:
3284 intel_crtc->pch_pll = pll;
3285 pll->refcount++;
3286 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3287prepare: /* separate function? */
3288 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3289
e04c7350
CW		 3290 /* Wait for the clocks to stabilize before rewriting the regs */
3291 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3292 POSTING_READ(pll->pll_reg);
3293 udelay(150);
e04c7350
CW		 3294
3295 I915_WRITE(pll->fp0_reg, fp);
3296 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3297 pll->on = false;
3298 return pll;
3299}
3300
d4270e57
JB		 3301void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3302{
3303 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3304 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3305 u32 temp;
3306
3307 temp = I915_READ(dslreg);
3308 udelay(500);
3309 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57
JB		 3310 if (wait_for(I915_READ(dslreg) != temp, 5))
3311 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3312 }
3313}
3314
f67a559d
JB		 3315static void ironlake_crtc_enable(struct drm_crtc *crtc)
3316{
3317 struct drm_device *dev = crtc->dev;
3318 struct drm_i915_private *dev_priv = dev->dev_private;
3319 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3320 struct intel_encoder *encoder;
f67a559d
JB		 3321 int pipe = intel_crtc->pipe;
3322 int plane = intel_crtc->plane;
3323 u32 temp;
3324 bool is_pch_port;
3325
08a48469
DV		 3326 WARN_ON(!crtc->enabled);
3327
f67a559d
JB		 3328 if (intel_crtc->active)
3329 return;
3330
3331 intel_crtc->active = true;
3332 intel_update_watermarks(dev);
3333
3334 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3335 temp = I915_READ(PCH_LVDS);
3336 if ((temp & LVDS_PORT_EN) == 0)
3337 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3338 }
3339
fc316cbe 3340 is_pch_port = ironlake_crtc_driving_pch(crtc);
f67a559d 3341
46b6f814 3342 if (is_pch_port) {
fff367c7
DV		 3343 /* Note: FDI PLL enabling _must_ be done before we enable the
3344 * cpu pipes, hence this is separate from all the other fdi/pch
3345 * enabling. */
88cefb6c 3346 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3347 } else {
3348 assert_fdi_tx_disabled(dev_priv, pipe);
3349 assert_fdi_rx_disabled(dev_priv, pipe);
3350 }
f67a559d 3351
bf49ec8c
DV		 3352 for_each_encoder_on_crtc(dev, crtc, encoder)
3353 if (encoder->pre_enable)
3354 encoder->pre_enable(encoder);
f67a559d
JB		 3355
3356 /* Enable panel fitting for LVDS */
3357 if (dev_priv->pch_pf_size &&
547dc041
JN		 3358 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3359 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
f67a559d
JB		 3360 /* Force use of hard-coded filter coefficients
3361 * as some pre-programmed values are broken,
3362 * e.g. x201.
3363 */
13888d78
PZ		 3364 if (IS_IVYBRIDGE(dev))
3365 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3366 PF_PIPE_SEL_IVB(pipe));
3367 else
3368 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
9db4a9c7
JB		 3369 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3370 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3371 }
3372
9c54c0dd
JB		 3373 /*
3374 * On ILK+ LUT must be loaded before the pipe is running but with
3375 * clocks enabled
3376 */
3377 intel_crtc_load_lut(crtc);
3378
f67a559d
JB		 3379 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3380 intel_enable_plane(dev_priv, plane, pipe);
3381
3382 if (is_pch_port)
3383 ironlake_pch_enable(crtc);
c98e9dcf 3384
d1ebd816 3385 mutex_lock(&dev->struct_mutex);
bed4a673 3386 intel_update_fbc(dev);
d1ebd816
BW		 3387 mutex_unlock(&dev->struct_mutex);
3388
6b383a7f 3389 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3390
fa5c73b1
DV		 3391 for_each_encoder_on_crtc(dev, crtc, encoder)
3392 encoder->enable(encoder);
61b77ddd
DV		 3393
3394 if (HAS_PCH_CPT(dev))
3395 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3396
3397 /*
3398 * There seems to be a race in PCH platform hw (at least on some
3399 * outputs) where an enabled pipe still completes any pageflip right
3400 * away (as if the pipe is off) instead of waiting for vblank. As soon
3401 * as the first vblank happend, everything works as expected. Hence just
3402 * wait for one vblank before returning to avoid strange things
3403 * happening.
3404 */
3405 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3406}
3407
4f771f10
PZ		 3408static void haswell_crtc_enable(struct drm_crtc *crtc)
3409{
3410 struct drm_device *dev = crtc->dev;
3411 struct drm_i915_private *dev_priv = dev->dev_private;
3412 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3413 struct intel_encoder *encoder;
3414 int pipe = intel_crtc->pipe;
3415 int plane = intel_crtc->plane;
4f771f10
PZ		 3416 bool is_pch_port;
3417
3418 WARN_ON(!crtc->enabled);
3419
3420 if (intel_crtc->active)
3421 return;
3422
3423 intel_crtc->active = true;
3424 intel_update_watermarks(dev);
3425
fc316cbe 3426 is_pch_port = haswell_crtc_driving_pch(crtc);
4f771f10 3427
83616634 3428 if (is_pch_port)
04945641 3429 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3430
3431 for_each_encoder_on_crtc(dev, crtc, encoder)
3432 if (encoder->pre_enable)
3433 encoder->pre_enable(encoder);
3434
1f544388 3435 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3436
1f544388 3437 /* Enable panel fitting for eDP */
547dc041
JN		 3438 if (dev_priv->pch_pf_size &&
3439 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4f771f10
PZ		 3440 /* Force use of hard-coded filter coefficients
3441 * as some pre-programmed values are broken,
3442 * e.g. x201.
3443 */
54075a7d
PZ		 3444 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3445 PF_PIPE_SEL_IVB(pipe));
4f771f10
PZ		 3446 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3447 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3448 }
3449
3450 /*
3451 * On ILK+ LUT must be loaded before the pipe is running but with
3452 * clocks enabled
3453 */
3454 intel_crtc_load_lut(crtc);
3455
1f544388
PZ		 3456 intel_ddi_set_pipe_settings(crtc);
3457 intel_ddi_enable_pipe_func(crtc);
4f771f10
PZ		 3458
3459 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3460 intel_enable_plane(dev_priv, plane, pipe);
3461
3462 if (is_pch_port)
1507e5bd 3463 lpt_pch_enable(crtc);
4f771f10
PZ		 3464
3465 mutex_lock(&dev->struct_mutex);
3466 intel_update_fbc(dev);
3467 mutex_unlock(&dev->struct_mutex);
3468
3469 intel_crtc_update_cursor(crtc, true);
3470
3471 for_each_encoder_on_crtc(dev, crtc, encoder)
3472 encoder->enable(encoder);
3473
4f771f10
PZ		 3474 /*
3475 * There seems to be a race in PCH platform hw (at least on some
3476 * outputs) where an enabled pipe still completes any pageflip right
3477 * away (as if the pipe is off) instead of waiting for vblank. As soon
3478 * as the first vblank happend, everything works as expected. Hence just
3479 * wait for one vblank before returning to avoid strange things
3480 * happening.
3481 */
3482 intel_wait_for_vblank(dev, intel_crtc->pipe);
3483}
3484
6be4a607
JB		 3485static void ironlake_crtc_disable(struct drm_crtc *crtc)
3486{
3487 struct drm_device *dev = crtc->dev;
3488 struct drm_i915_private *dev_priv = dev->dev_private;
3489 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3490 struct intel_encoder *encoder;
6be4a607
JB		 3491 int pipe = intel_crtc->pipe;
3492 int plane = intel_crtc->plane;
5eddb70b 3493 u32 reg, temp;
b52eb4dc 3494
ef9c3aee 3495
f7abfe8b
CW		 3496 if (!intel_crtc->active)
3497 return;
3498
ea9d758d
DV		 3499 for_each_encoder_on_crtc(dev, crtc, encoder)
3500 encoder->disable(encoder);
3501
e6c3a2a6 3502 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3503 drm_vblank_off(dev, pipe);
6b383a7f 3504 intel_crtc_update_cursor(crtc, false);
5eddb70b 3505
b24e7179 3506 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3507
973d04f9
CW		 3508 if (dev_priv->cfb_plane == plane)
3509 intel_disable_fbc(dev);
2c07245f 3510
b24e7179 3511 intel_disable_pipe(dev_priv, pipe);
32f9d658 3512
6be4a607 3513 /* Disable PF */
9db4a9c7
JB		 3514 I915_WRITE(PF_CTL(pipe), 0);
3515 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3516
bf49ec8c
DV		 3517 for_each_encoder_on_crtc(dev, crtc, encoder)
3518 if (encoder->post_disable)
3519 encoder->post_disable(encoder);
2c07245f 3520
0fc932b8 3521 ironlake_fdi_disable(crtc);
249c0e64 3522
b8a4f404 3523 ironlake_disable_pch_transcoder(dev_priv, pipe);
913d8d11 3524
6be4a607
JB		 3525 if (HAS_PCH_CPT(dev)) {
3526 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3527 reg = TRANS_DP_CTL(pipe);
3528 temp = I915_READ(reg);
3529 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3530 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3531 I915_WRITE(reg, temp);
6be4a607
JB		 3532
3533 /* disable DPLL_SEL */
3534 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3535 switch (pipe) {
3536 case 0:
d64311ab 3537 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3538 break;
3539 case 1:
6be4a607 3540 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3541 break;
3542 case 2:
4b645f14 3543 /* C shares PLL A or B */
d64311ab 3544 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3545 break;
3546 default:
3547 BUG(); /* wtf */
3548 }
6be4a607 3549 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3550 }
e3421a18 3551
6be4a607 3552 /* disable PCH DPLL */
ee7b9f93 3553 intel_disable_pch_pll(intel_crtc);
8db9d77b 3554
88cefb6c 3555 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3556
f7abfe8b 3557 intel_crtc->active = false;
6b383a7f 3558 intel_update_watermarks(dev);
d1ebd816
BW		 3559
3560 mutex_lock(&dev->struct_mutex);
6b383a7f 3561 intel_update_fbc(dev);
d1ebd816 3562 mutex_unlock(&dev->struct_mutex);
6be4a607 3563}
1b3c7a47 3564
4f771f10 3565static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3566{
4f771f10
PZ		 3567 struct drm_device *dev = crtc->dev;
3568 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3569 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3570 struct intel_encoder *encoder;
3571 int pipe = intel_crtc->pipe;
3572 int plane = intel_crtc->plane;
ad80a810 3573 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
83616634 3574 bool is_pch_port;
ee7b9f93 3575
4f771f10
PZ		 3576 if (!intel_crtc->active)
3577 return;
3578
83616634
PZ		 3579 is_pch_port = haswell_crtc_driving_pch(crtc);
3580
4f771f10
PZ		 3581 for_each_encoder_on_crtc(dev, crtc, encoder)
3582 encoder->disable(encoder);
3583
3584 intel_crtc_wait_for_pending_flips(crtc);
3585 drm_vblank_off(dev, pipe);
3586 intel_crtc_update_cursor(crtc, false);
3587
3588 intel_disable_plane(dev_priv, plane, pipe);
3589
3590 if (dev_priv->cfb_plane == plane)
3591 intel_disable_fbc(dev);
3592
3593 intel_disable_pipe(dev_priv, pipe);
3594
ad80a810 3595 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10
PZ		 3596
3597 /* Disable PF */
3598 I915_WRITE(PF_CTL(pipe), 0);
3599 I915_WRITE(PF_WIN_SZ(pipe), 0);
3600
1f544388 3601 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3602
3603 for_each_encoder_on_crtc(dev, crtc, encoder)
3604 if (encoder->post_disable)
3605 encoder->post_disable(encoder);
3606
83616634 3607 if (is_pch_port) {
ab4d966c 3608 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 3609 intel_ddi_fdi_disable(crtc);
83616634 3610 }
4f771f10
PZ		 3611
3612 intel_crtc->active = false;
3613 intel_update_watermarks(dev);
3614
3615 mutex_lock(&dev->struct_mutex);
3616 intel_update_fbc(dev);
3617 mutex_unlock(&dev->struct_mutex);
3618}
3619
ee7b9f93
JB		 3620static void ironlake_crtc_off(struct drm_crtc *crtc)
3621{
3622 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3623 intel_put_pch_pll(intel_crtc);
3624}
3625
6441ab5f
PZ		 3626static void haswell_crtc_off(struct drm_crtc *crtc)
3627{
a5c961d1
PZ		 3628 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3629
3630 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3631 * start using it. */
1a240d4d 3632 intel_crtc->cpu_transcoder = (enum transcoder) intel_crtc->pipe;
a5c961d1 3633
6441ab5f
PZ		 3634 intel_ddi_put_crtc_pll(crtc);
3635}
3636
02e792fb
DV		 3637static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3638{
02e792fb 3639 if (!enable && intel_crtc->overlay) {
23f09ce3 3640 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3641 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3642
23f09ce3 3643 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3644 dev_priv->mm.interruptible = false;
3645 (void) intel_overlay_switch_off(intel_crtc->overlay);
3646 dev_priv->mm.interruptible = true;
23f09ce3 3647 mutex_unlock(&dev->struct_mutex);
02e792fb 3648 }
02e792fb 3649
5dcdbcb0
CW		 3650 /* Let userspace switch the overlay on again. In most cases userspace
3651 * has to recompute where to put it anyway.
3652 */
02e792fb
DV		 3653}
3654
61bc95c1
EE		 3655/**
3656 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3657 * cursor plane briefly if not already running after enabling the display
3658 * plane.
3659 * This workaround avoids occasional blank screens when self refresh is
3660 * enabled.
3661 */
3662static void
3663g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3664{
3665 u32 cntl = I915_READ(CURCNTR(pipe));
3666
3667 if ((cntl & CURSOR_MODE) == 0) {
3668 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3669
3670 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3671 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3672 intel_wait_for_vblank(dev_priv->dev, pipe);
3673 I915_WRITE(CURCNTR(pipe), cntl);
3674 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3675 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3676 }
3677}
3678
0b8765c6 3679static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3680{
3681 struct drm_device *dev = crtc->dev;
79e53945
JB		 3682 struct drm_i915_private *dev_priv = dev->dev_private;
3683 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3684 struct intel_encoder *encoder;
79e53945 3685 int pipe = intel_crtc->pipe;
80824003 3686 int plane = intel_crtc->plane;
79e53945 3687
08a48469
DV		 3688 WARN_ON(!crtc->enabled);
3689
f7abfe8b
CW		 3690 if (intel_crtc->active)
3691 return;
3692
3693 intel_crtc->active = true;
6b383a7f
CW		 3694 intel_update_watermarks(dev);
3695
63d7bbe9 3696 intel_enable_pll(dev_priv, pipe);
9d6d9f19
MK		 3697
3698 for_each_encoder_on_crtc(dev, crtc, encoder)
3699 if (encoder->pre_enable)
3700 encoder->pre_enable(encoder);
3701
040484af 3702 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3703 intel_enable_plane(dev_priv, plane, pipe);
61bc95c1
EE		 3704 if (IS_G4X(dev))
3705 g4x_fixup_plane(dev_priv, pipe);
79e53945 3706
0b8765c6 3707 intel_crtc_load_lut(crtc);
bed4a673 3708 intel_update_fbc(dev);
79e53945 3709
0b8765c6
JB		 3710 /* Give the overlay scaler a chance to enable if it's on this pipe */
3711 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3712 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3713
fa5c73b1
DV		 3714 for_each_encoder_on_crtc(dev, crtc, encoder)
3715 encoder->enable(encoder);
0b8765c6 3716}
79e53945 3717
0b8765c6
JB		 3718static void i9xx_crtc_disable(struct drm_crtc *crtc)
3719{
3720 struct drm_device *dev = crtc->dev;
3721 struct drm_i915_private *dev_priv = dev->dev_private;
3722 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3723 struct intel_encoder *encoder;
0b8765c6
JB		 3724 int pipe = intel_crtc->pipe;
3725 int plane = intel_crtc->plane;
24a1f16d 3726 u32 pctl;
b690e96c 3727
ef9c3aee 3728
f7abfe8b
CW		 3729 if (!intel_crtc->active)
3730 return;
3731
ea9d758d
DV		 3732 for_each_encoder_on_crtc(dev, crtc, encoder)
3733 encoder->disable(encoder);
3734
0b8765c6 3735 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3736 intel_crtc_wait_for_pending_flips(crtc);
3737 drm_vblank_off(dev, pipe);
0b8765c6 3738 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3739 intel_crtc_update_cursor(crtc, false);
0b8765c6 3740
973d04f9
CW		 3741 if (dev_priv->cfb_plane == plane)
3742 intel_disable_fbc(dev);
79e53945 3743
b24e7179 3744 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3745 intel_disable_pipe(dev_priv, pipe);
24a1f16d
MK		 3746
3747 /* Disable pannel fitter if it is on this pipe. */
3748 pctl = I915_READ(PFIT_CONTROL);
3749 if ((pctl & PFIT_ENABLE) &&
3750 ((pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT) == pipe)
3751 I915_WRITE(PFIT_CONTROL, 0);
3752
63d7bbe9 3753 intel_disable_pll(dev_priv, pipe);
0b8765c6 3754
f7abfe8b 3755 intel_crtc->active = false;
6b383a7f
CW		 3756 intel_update_fbc(dev);
3757 intel_update_watermarks(dev);
0b8765c6
JB		 3758}
3759
ee7b9f93
JB		 3760static void i9xx_crtc_off(struct drm_crtc *crtc)
3761{
3762}
3763
976f8a20
DV		 3764static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3765 bool enabled)
2c07245f
ZW		 3766{
3767 struct drm_device *dev = crtc->dev;
3768 struct drm_i915_master_private *master_priv;
3769 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3770 int pipe = intel_crtc->pipe;
79e53945
JB		 3771
3772 if (!dev->primary->master)
3773 return;
3774
3775 master_priv = dev->primary->master->driver_priv;
3776 if (!master_priv->sarea_priv)
3777 return;
3778
79e53945
JB		 3779 switch (pipe) {
3780 case 0:
3781 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3782 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3783 break;
3784 case 1:
3785 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3786 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3787 break;
3788 default:
9db4a9c7 3789 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3790 break;
3791 }
79e53945
JB		 3792}
3793
976f8a20
DV		 3794/**
3795 * Sets the power management mode of the pipe and plane.
3796 */
3797void intel_crtc_update_dpms(struct drm_crtc *crtc)
3798{
3799 struct drm_device *dev = crtc->dev;
3800 struct drm_i915_private *dev_priv = dev->dev_private;
3801 struct intel_encoder *intel_encoder;
3802 bool enable = false;
3803
3804 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3805 enable |= intel_encoder->connectors_active;
3806
3807 if (enable)
3808 dev_priv->display.crtc_enable(crtc);
3809 else
3810 dev_priv->display.crtc_disable(crtc);
3811
3812 intel_crtc_update_sarea(crtc, enable);
3813}
3814
cdd59983
CW		 3815static void intel_crtc_disable(struct drm_crtc *crtc)
3816{
cdd59983 3817 struct drm_device *dev = crtc->dev;
976f8a20 3818 struct drm_connector *connector;
ee7b9f93 3819 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3820 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3821
976f8a20
DV		 3822 /* crtc should still be enabled when we disable it. */
3823 WARN_ON(!crtc->enabled);
3824
7b9f35a6 3825 intel_crtc->eld_vld = false;
976f8a20
DV		 3826 dev_priv->display.crtc_disable(crtc);
3827 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3828 dev_priv->display.off(crtc);
3829
931872fc
CW		 3830 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3831 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3832
3833 if (crtc->fb) {
3834 mutex_lock(&dev->struct_mutex);
1690e1eb 3835 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3836 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3837 crtc->fb = NULL;
3838 }
3839
3840 /* Update computed state. */
3841 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3842 if (!connector->encoder || !connector->encoder->crtc)
3843 continue;
3844
3845 if (connector->encoder->crtc != crtc)
3846 continue;
3847
3848 connector->dpms = DRM_MODE_DPMS_OFF;
3849 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3850 }
3851}
3852
a261b246 3853void intel_modeset_disable(struct drm_device *dev)
79e53945 3854{
a261b246
DV		 3855 struct drm_crtc *crtc;
3856
3857 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3858 if (crtc->enabled)
3859 intel_crtc_disable(crtc);
3860 }
79e53945
JB		 3861}
3862
ea5b213a 3863void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3864{
4ef69c7a 3865 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3866
ea5b213a
CW		 3867 drm_encoder_cleanup(encoder);
3868 kfree(intel_encoder);
7e7d76c3
JB		 3869}
3870
5ab432ef
DV		 3871/* Simple dpms helper for encodres with just one connector, no cloning and only
3872 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3873 * state of the entire output pipe. */
3874void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3875{
5ab432ef
DV		 3876 if (mode == DRM_MODE_DPMS_ON) {
3877 encoder->connectors_active = true;
3878
b2cabb0e 3879 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3880 } else {
3881 encoder->connectors_active = false;
3882
b2cabb0e 3883 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3884 }
79e53945
JB		 3885}
3886
0a91ca29
DV		 3887/* Cross check the actual hw state with our own modeset state tracking (and it's
3888 * internal consistency). */
b980514c 3889static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3890{
0a91ca29
DV		 3891 if (connector->get_hw_state(connector)) {
3892 struct intel_encoder *encoder = connector->encoder;
3893 struct drm_crtc *crtc;
3894 bool encoder_enabled;
3895 enum pipe pipe;
3896
3897 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3898 connector->base.base.id,
3899 drm_get_connector_name(&connector->base));
3900
3901 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3902 "wrong connector dpms state\n");
3903 WARN(connector->base.encoder != &encoder->base,
3904 "active connector not linked to encoder\n");
3905 WARN(!encoder->connectors_active,
3906 "encoder->connectors_active not set\n");
3907
3908 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3909 WARN(!encoder_enabled, "encoder not enabled\n");
3910 if (WARN_ON(!encoder->base.crtc))
3911 return;
3912
3913 crtc = encoder->base.crtc;
3914
3915 WARN(!crtc->enabled, "crtc not enabled\n");
3916 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3917 WARN(pipe != to_intel_crtc(crtc)->pipe,
3918 "encoder active on the wrong pipe\n");
3919 }
79e53945
JB		 3920}
3921
5ab432ef
DV		 3922/* Even simpler default implementation, if there's really no special case to
3923 * consider. */
3924void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3925{
5ab432ef 3926 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3927
5ab432ef
DV		 3928 /* All the simple cases only support two dpms states. */
3929 if (mode != DRM_MODE_DPMS_ON)
3930 mode = DRM_MODE_DPMS_OFF;
d4270e57 3931
5ab432ef
DV		 3932 if (mode == connector->dpms)
3933 return;
3934
3935 connector->dpms = mode;
3936
3937 /* Only need to change hw state when actually enabled */
3938 if (encoder->base.crtc)
3939 intel_encoder_dpms(encoder, mode);
3940 else
8af6cf88 3941 WARN_ON(encoder->connectors_active != false);
0a91ca29 3942
b980514c 3943 intel_modeset_check_state(connector->dev);
79e53945
JB		 3944}
3945
f0947c37
DV		 3946/* Simple connector->get_hw_state implementation for encoders that support only
3947 * one connector and no cloning and hence the encoder state determines the state
3948 * of the connector. */
3949bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3950{
24929352 3951 enum pipe pipe = 0;
f0947c37 3952 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3953
f0947c37 3954 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3955}
3956
79e53945 3957static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
35313cde 3958 const struct drm_display_mode *mode,
79e53945
JB		 3959 struct drm_display_mode *adjusted_mode)
3960{
2c07245f 3961 struct drm_device *dev = crtc->dev;
89749350 3962
bad720ff 3963 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3964 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3965 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3966 return false;
2c07245f 3967 }
89749350 3968
f9bef081
DV		 3969 /* All interlaced capable intel hw wants timings in frames. Note though
3970 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3971 * timings, so we need to be careful not to clobber these.*/
3972 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3973 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3974
44f46b42
CW		 3975 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3976 * with a hsync front porch of 0.
3977 */
3978 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3979 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3980 return false;
3981
79e53945
JB		 3982 return true;
3983}
3984
25eb05fc
JB		 3985static int valleyview_get_display_clock_speed(struct drm_device *dev)
3986{
3987 return 400000; /* FIXME */
3988}
3989
e70236a8
JB		 3990static int i945_get_display_clock_speed(struct drm_device *dev)
3991{
3992 return 400000;
3993}
79e53945 3994
e70236a8 3995static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3996{
e70236a8
JB		 3997 return 333000;
3998}
79e53945 3999
e70236a8
JB		 4000static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4001{
4002 return 200000;
4003}
79e53945 4004
e70236a8
JB		 4005static int i915gm_get_display_clock_speed(struct drm_device *dev)
4006{
4007 u16 gcfgc = 0;
79e53945 4008
e70236a8
JB		 4009 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4010
4011 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4012 return 133000;
4013 else {
4014 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4015 case GC_DISPLAY_CLOCK_333_MHZ:
4016 return 333000;
4017 default:
4018 case GC_DISPLAY_CLOCK_190_200_MHZ:
4019 return 190000;
79e53945 4020 }
e70236a8
JB		 4021 }
4022}
4023
4024static int i865_get_display_clock_speed(struct drm_device *dev)
4025{
4026 return 266000;
4027}
4028
4029static int i855_get_display_clock_speed(struct drm_device *dev)
4030{
4031 u16 hpllcc = 0;
4032 /* Assume that the hardware is in the high speed state. This
4033 * should be the default.
4034 */
4035 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4036 case GC_CLOCK_133_200:
4037 case GC_CLOCK_100_200:
4038 return 200000;
4039 case GC_CLOCK_166_250:
4040 return 250000;
4041 case GC_CLOCK_100_133:
79e53945 4042 return 133000;
e70236a8 4043 }
79e53945 4044
e70236a8
JB		 4045 /* Shouldn't happen */
4046 return 0;
4047}
79e53945 4048
e70236a8
JB		 4049static int i830_get_display_clock_speed(struct drm_device *dev)
4050{
4051 return 133000;
79e53945
JB		 4052}
4053
2c07245f 4054static void
e69d0bc1 4055intel_reduce_ratio(uint32_t *num, uint32_t *den)
2c07245f
ZW		 4056{
4057 while (*num > 0xffffff || *den > 0xffffff) {
4058 *num >>= 1;
4059 *den >>= 1;
4060 }
4061}
4062
e69d0bc1
DV		 4063void
4064intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4065 int pixel_clock, int link_clock,
4066 struct intel_link_m_n *m_n)
2c07245f 4067{
e69d0bc1 4068 m_n->tu = 64;
22ed1113
CW		 4069 m_n->gmch_m = bits_per_pixel * pixel_clock;
4070 m_n->gmch_n = link_clock * nlanes * 8;
e69d0bc1 4071 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
22ed1113
CW		 4072 m_n->link_m = pixel_clock;
4073 m_n->link_n = link_clock;
e69d0bc1 4074 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4075}
4076
a7615030
CW		 4077static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4078{
72bbe58c
KP		 4079 if (i915_panel_use_ssc >= 0)
4080 return i915_panel_use_ssc != 0;
4081 return dev_priv->lvds_use_ssc
435793df 4082 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4083}
4084
5a354204
JB		 4085/**
4086 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4087 * @crtc: CRTC structure
3b5c78a3 4088 * @mode: requested mode
5a354204
JB		 4089 *
4090 * A pipe may be connected to one or more outputs. Based on the depth of the
4091 * attached framebuffer, choose a good color depth to use on the pipe.
4092 *
4093 * If possible, match the pipe depth to the fb depth. In some cases, this
4094 * isn't ideal, because the connected output supports a lesser or restricted
4095 * set of depths. Resolve that here:
4096 * LVDS typically supports only 6bpc, so clamp down in that case
4097 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4098 * Displays may support a restricted set as well, check EDID and clamp as
4099 * appropriate.
3b5c78a3 4100 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 4101 *
4102 * RETURNS:
4103 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4104 * true if they don't match).
4105 */
4106static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
94352cf9 4107 struct drm_framebuffer *fb,
3b5c78a3
AJ		 4108 unsigned int *pipe_bpp,
4109 struct drm_display_mode *mode)
5a354204
JB		 4110{
4111 struct drm_device *dev = crtc->dev;
4112 struct drm_i915_private *dev_priv = dev->dev_private;
5a354204 4113 struct drm_connector *connector;
6c2b7c12 4114 struct intel_encoder *intel_encoder;
5a354204
JB		 4115 unsigned int display_bpc = UINT_MAX, bpc;
4116
4117 /* Walk the encoders & connectors on this crtc, get min bpc */
6c2b7c12 4118 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5a354204
JB		 4119
4120 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4121 unsigned int lvds_bpc;
4122
4123 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4124 LVDS_A3_POWER_UP)
4125 lvds_bpc = 8;
4126 else
4127 lvds_bpc = 6;
4128
4129 if (lvds_bpc < display_bpc) {
82820490 4130 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 4131 display_bpc = lvds_bpc;
4132 }
4133 continue;
4134 }
4135
5a354204
JB		 4136 /* Not one of the known troublemakers, check the EDID */
4137 list_for_each_entry(connector, &dev->mode_config.connector_list,
4138 head) {
6c2b7c12 4139 if (connector->encoder != &intel_encoder->base)
5a354204
JB		 4140 continue;
4141
62ac41a6
JB		 4142 /* Don't use an invalid EDID bpc value */
4143 if (connector->display_info.bpc &&
4144 connector->display_info.bpc < display_bpc) {
82820490 4145 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 4146 display_bpc = connector->display_info.bpc;
4147 }
4148 }
4149
2f4f649a
JN		 4150 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4151 /* Use VBT settings if we have an eDP panel */
4152 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4153
9a30a61f 4154 if (edp_bpc && edp_bpc < display_bpc) {
2f4f649a
JN		 4155 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4156 display_bpc = edp_bpc;
4157 }
4158 continue;
4159 }
4160
5a354204
JB		 4161 /*
4162 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4163 * through, clamp it down. (Note: >12bpc will be caught below.)
4164 */
4165 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4166 if (display_bpc > 8 && display_bpc < 12) {
82820490 4167 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 4168 display_bpc = 12;
4169 } else {
82820490 4170 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 4171 display_bpc = 8;
4172 }
4173 }
4174 }
4175
3b5c78a3
AJ		 4176 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4177 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4178 display_bpc = 6;
4179 }
4180
5a354204
JB		 4181 /*
4182 * We could just drive the pipe at the highest bpc all the time and
4183 * enable dithering as needed, but that costs bandwidth. So choose
4184 * the minimum value that expresses the full color range of the fb but
4185 * also stays within the max display bpc discovered above.
4186 */
4187
94352cf9 4188 switch (fb->depth) {
5a354204
JB		 4189 case 8:
4190 bpc = 8; /* since we go through a colormap */
4191 break;
4192 case 15:
4193 case 16:
4194 bpc = 6; /* min is 18bpp */
4195 break;
4196 case 24:
578393cd 4197 bpc = 8;
5a354204
JB		 4198 break;
4199 case 30:
578393cd 4200 bpc = 10;
5a354204
JB		 4201 break;
4202 case 48:
578393cd 4203 bpc = 12;
5a354204
JB		 4204 break;
4205 default:
4206 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4207 bpc = min((unsigned int)8, display_bpc);
4208 break;
4209 }
4210
578393cd
KP		 4211 display_bpc = min(display_bpc, bpc);
4212
82820490
AJ		 4213 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4214 bpc, display_bpc);
5a354204 4215
578393cd 4216 *pipe_bpp = display_bpc * 3;
5a354204
JB		 4217
4218 return display_bpc != bpc;
4219}
4220
a0c4da24
JB		 4221static int vlv_get_refclk(struct drm_crtc *crtc)
4222{
4223 struct drm_device *dev = crtc->dev;
4224 struct drm_i915_private *dev_priv = dev->dev_private;
4225 int refclk = 27000; /* for DP & HDMI */
4226
4227 return 100000; /* only one validated so far */
4228
4229 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4230 refclk = 96000;
4231 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4232 if (intel_panel_use_ssc(dev_priv))
4233 refclk = 100000;
4234 else
4235 refclk = 96000;
4236 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4237 refclk = 100000;
4238 }
4239
4240 return refclk;
4241}
4242
c65d77d8
JB		 4243static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4244{
4245 struct drm_device *dev = crtc->dev;
4246 struct drm_i915_private *dev_priv = dev->dev_private;
4247 int refclk;
4248
a0c4da24
JB		 4249 if (IS_VALLEYVIEW(dev)) {
4250 refclk = vlv_get_refclk(crtc);
4251 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 4252 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4253 refclk = dev_priv->lvds_ssc_freq * 1000;
4254 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4255 refclk / 1000);
4256 } else if (!IS_GEN2(dev)) {
4257 refclk = 96000;
4258 } else {
4259 refclk = 48000;
4260 }
4261
4262 return refclk;
4263}
4264
4265static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4266 intel_clock_t *clock)
4267{
4268 /* SDVO TV has fixed PLL values depend on its clock range,
4269 this mirrors vbios setting. */
4270 if (adjusted_mode->clock >= 100000
4271 && adjusted_mode->clock < 140500) {
4272 clock->p1 = 2;
4273 clock->p2 = 10;
4274 clock->n = 3;
4275 clock->m1 = 16;
4276 clock->m2 = 8;
4277 } else if (adjusted_mode->clock >= 140500
4278 && adjusted_mode->clock <= 200000) {
4279 clock->p1 = 1;
4280 clock->p2 = 10;
4281 clock->n = 6;
4282 clock->m1 = 12;
4283 clock->m2 = 8;
4284 }
4285}
4286
a7516a05
JB		 4287static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4288 intel_clock_t *clock,
4289 intel_clock_t *reduced_clock)
4290{
4291 struct drm_device *dev = crtc->dev;
4292 struct drm_i915_private *dev_priv = dev->dev_private;
4293 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4294 int pipe = intel_crtc->pipe;
4295 u32 fp, fp2 = 0;
4296
4297 if (IS_PINEVIEW(dev)) {
4298 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4299 if (reduced_clock)
4300 fp2 = (1 << reduced_clock->n) << 16 |
4301 reduced_clock->m1 << 8 | reduced_clock->m2;
4302 } else {
4303 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4304 if (reduced_clock)
4305 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4306 reduced_clock->m2;
4307 }
4308
4309 I915_WRITE(FP0(pipe), fp);
4310
4311 intel_crtc->lowfreq_avail = false;
4312 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4313 reduced_clock && i915_powersave) {
4314 I915_WRITE(FP1(pipe), fp2);
4315 intel_crtc->lowfreq_avail = true;
4316 } else {
4317 I915_WRITE(FP1(pipe), fp);
4318 }
4319}
4320
a0c4da24
JB		 4321static void vlv_update_pll(struct drm_crtc *crtc,
4322 struct drm_display_mode *mode,
4323 struct drm_display_mode *adjusted_mode,
4324 intel_clock_t *clock, intel_clock_t *reduced_clock,
2a8f64ca 4325 int num_connectors)
a0c4da24
JB		 4326{
4327 struct drm_device *dev = crtc->dev;
4328 struct drm_i915_private *dev_priv = dev->dev_private;
4329 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4330 int pipe = intel_crtc->pipe;
4331 u32 dpll, mdiv, pdiv;
4332 u32 bestn, bestm1, bestm2, bestp1, bestp2;
2a8f64ca
VP		 4333 bool is_sdvo;
4334 u32 temp;
a0c4da24 4335
09153000
DV		 4336 mutex_lock(&dev_priv->dpio_lock);
4337
2a8f64ca
VP		 4338 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4339 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
a0c4da24 4340
2a8f64ca
VP		 4341 dpll = DPLL_VGA_MODE_DIS;
4342 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4343 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4344 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4345
4346 I915_WRITE(DPLL(pipe), dpll);
4347 POSTING_READ(DPLL(pipe));
a0c4da24
JB		 4348
4349 bestn = clock->n;
4350 bestm1 = clock->m1;
4351 bestm2 = clock->m2;
4352 bestp1 = clock->p1;
4353 bestp2 = clock->p2;
4354
2a8f64ca
VP		 4355 /*
4356 * In Valleyview PLL and program lane counter registers are exposed
4357 * through DPIO interface
4358 */
a0c4da24
JB		 4359 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4360 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4361 mdiv |= ((bestn << DPIO_N_SHIFT));
4362 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4363 mdiv |= (1 << DPIO_K_SHIFT);
4364 mdiv |= DPIO_ENABLE_CALIBRATION;
4365 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4366
4367 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4368
2a8f64ca 4369 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
a0c4da24 4370 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
2a8f64ca
VP		 4371 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4372 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
a0c4da24
JB		 4373 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4374
2a8f64ca 4375 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
a0c4da24
JB		 4376
4377 dpll |= DPLL_VCO_ENABLE;
4378 I915_WRITE(DPLL(pipe), dpll);
4379 POSTING_READ(DPLL(pipe));
4380 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4381 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4382
2a8f64ca
VP		 4383 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4384
4385 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4386 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4387
4388 I915_WRITE(DPLL(pipe), dpll);
4389
4390 /* Wait for the clocks to stabilize. */
4391 POSTING_READ(DPLL(pipe));
4392 udelay(150);
a0c4da24 4393
2a8f64ca
VP		 4394 temp = 0;
4395 if (is_sdvo) {
4396 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
a0c4da24
JB		 4397 if (temp > 1)
4398 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4399 else
4400 temp = 0;
a0c4da24 4401 }
2a8f64ca
VP		 4402 I915_WRITE(DPLL_MD(pipe), temp);
4403 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4404
2a8f64ca
VP		 4405 /* Now program lane control registers */
4406 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4407 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4408 {
4409 temp = 0x1000C4;
4410 if(pipe == 1)
4411 temp |= (1 << 21);
4412 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4413 }
4414 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4415 {
4416 temp = 0x1000C4;
4417 if(pipe == 1)
4418 temp |= (1 << 21);
4419 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4420 }
09153000
DV		 4421
4422 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4423}
4424
eb1cbe48
DV		 4425static void i9xx_update_pll(struct drm_crtc *crtc,
4426 struct drm_display_mode *mode,
4427 struct drm_display_mode *adjusted_mode,
4428 intel_clock_t *clock, intel_clock_t *reduced_clock,
4429 int num_connectors)
4430{
4431 struct drm_device *dev = crtc->dev;
4432 struct drm_i915_private *dev_priv = dev->dev_private;
4433 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dafd226c 4434 struct intel_encoder *encoder;
eb1cbe48
DV		 4435 int pipe = intel_crtc->pipe;
4436 u32 dpll;
4437 bool is_sdvo;
4438
2a8f64ca
VP		 4439 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4440
eb1cbe48
DV		 4441 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4442 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4443
4444 dpll = DPLL_VGA_MODE_DIS;
4445
4446 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4447 dpll |= DPLLB_MODE_LVDS;
4448 else
4449 dpll |= DPLLB_MODE_DAC_SERIAL;
4450 if (is_sdvo) {
4451 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4452 if (pixel_multiplier > 1) {
4453 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4454 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4455 }
4456 dpll |= DPLL_DVO_HIGH_SPEED;
4457 }
4458 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4459 dpll |= DPLL_DVO_HIGH_SPEED;
4460
4461 /* compute bitmask from p1 value */
4462 if (IS_PINEVIEW(dev))
4463 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4464 else {
4465 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4466 if (IS_G4X(dev) && reduced_clock)
4467 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4468 }
4469 switch (clock->p2) {
4470 case 5:
4471 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4472 break;
4473 case 7:
4474 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4475 break;
4476 case 10:
4477 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4478 break;
4479 case 14:
4480 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4481 break;
4482 }
4483 if (INTEL_INFO(dev)->gen >= 4)
4484 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4485
4486 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4487 dpll |= PLL_REF_INPUT_TVCLKINBC;
4488 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4489 /* XXX: just matching BIOS for now */
4490 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4491 dpll |= 3;
4492 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4493 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4494 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4495 else
4496 dpll |= PLL_REF_INPUT_DREFCLK;
4497
4498 dpll |= DPLL_VCO_ENABLE;
4499 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4500 POSTING_READ(DPLL(pipe));
4501 udelay(150);
4502
dafd226c
DV		 4503 for_each_encoder_on_crtc(dev, crtc, encoder)
4504 if (encoder->pre_pll_enable)
4505 encoder->pre_pll_enable(encoder);
eb1cbe48
DV		 4506
4507 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4508 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4509
4510 I915_WRITE(DPLL(pipe), dpll);
4511
4512 /* Wait for the clocks to stabilize. */
4513 POSTING_READ(DPLL(pipe));
4514 udelay(150);
4515
4516 if (INTEL_INFO(dev)->gen >= 4) {
4517 u32 temp = 0;
4518 if (is_sdvo) {
4519 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4520 if (temp > 1)
4521 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4522 else
4523 temp = 0;
4524 }
4525 I915_WRITE(DPLL_MD(pipe), temp);
4526 } else {
4527 /* The pixel multiplier can only be updated once the
4528 * DPLL is enabled and the clocks are stable.
4529 *
4530 * So write it again.
4531 */
4532 I915_WRITE(DPLL(pipe), dpll);
4533 }
4534}
4535
4536static void i8xx_update_pll(struct drm_crtc *crtc,
4537 struct drm_display_mode *adjusted_mode,
2a8f64ca 4538 intel_clock_t *clock, intel_clock_t *reduced_clock,
eb1cbe48
DV		 4539 int num_connectors)
4540{
4541 struct drm_device *dev = crtc->dev;
4542 struct drm_i915_private *dev_priv = dev->dev_private;
4543 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dafd226c 4544 struct intel_encoder *encoder;
eb1cbe48
DV		 4545 int pipe = intel_crtc->pipe;
4546 u32 dpll;
4547
2a8f64ca
VP		 4548 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4549
eb1cbe48
DV		 4550 dpll = DPLL_VGA_MODE_DIS;
4551
4552 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4553 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4554 } else {
4555 if (clock->p1 == 2)
4556 dpll |= PLL_P1_DIVIDE_BY_TWO;
4557 else
4558 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4559 if (clock->p2 == 4)
4560 dpll |= PLL_P2_DIVIDE_BY_4;
4561 }
4562
83f377ab 4563 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4564 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4565 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4566 else
4567 dpll |= PLL_REF_INPUT_DREFCLK;
4568
4569 dpll |= DPLL_VCO_ENABLE;
4570 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4571 POSTING_READ(DPLL(pipe));
4572 udelay(150);
4573
dafd226c
DV		 4574 for_each_encoder_on_crtc(dev, crtc, encoder)
4575 if (encoder->pre_pll_enable)
4576 encoder->pre_pll_enable(encoder);
eb1cbe48 4577
5b5896e4
DV		 4578 I915_WRITE(DPLL(pipe), dpll);
4579
4580 /* Wait for the clocks to stabilize. */
4581 POSTING_READ(DPLL(pipe));
4582 udelay(150);
4583
eb1cbe48
DV		 4584 /* The pixel multiplier can only be updated once the
4585 * DPLL is enabled and the clocks are stable.
4586 *
4587 * So write it again.
4588 */
4589 I915_WRITE(DPLL(pipe), dpll);
4590}
4591
b0e77b9c
PZ		 4592static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4593 struct drm_display_mode *mode,
4594 struct drm_display_mode *adjusted_mode)
4595{
4596 struct drm_device *dev = intel_crtc->base.dev;
4597 struct drm_i915_private *dev_priv = dev->dev_private;
4598 enum pipe pipe = intel_crtc->pipe;
fe2b8f9d 4599 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
b0e77b9c
PZ		 4600 uint32_t vsyncshift;
4601
4602 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4603 /* the chip adds 2 halflines automatically */
4604 adjusted_mode->crtc_vtotal -= 1;
4605 adjusted_mode->crtc_vblank_end -= 1;
4606 vsyncshift = adjusted_mode->crtc_hsync_start
4607 - adjusted_mode->crtc_htotal / 2;
4608 } else {
4609 vsyncshift = 0;
4610 }
4611
4612 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4613 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4614
fe2b8f9d 4615 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4616 (adjusted_mode->crtc_hdisplay - 1) |
4617 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4618 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4619 (adjusted_mode->crtc_hblank_start - 1) |
4620 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4621 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4622 (adjusted_mode->crtc_hsync_start - 1) |
4623 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4624
fe2b8f9d 4625 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4626 (adjusted_mode->crtc_vdisplay - 1) |
4627 ((adjusted_mode->crtc_vtotal - 1) << 16));
fe2b8f9d 4628 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c
PZ		 4629 (adjusted_mode->crtc_vblank_start - 1) |
4630 ((adjusted_mode->crtc_vblank_end - 1) << 16));
fe2b8f9d 4631 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4632 (adjusted_mode->crtc_vsync_start - 1) |
4633 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4634
b5e508d4
PZ		 4635 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4636 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4637 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4638 * bits. */
4639 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4640 (pipe == PIPE_B || pipe == PIPE_C))
4641 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4642
b0e77b9c
PZ		 4643 /* pipesrc controls the size that is scaled from, which should
4644 * always be the user's requested size.
4645 */
4646 I915_WRITE(PIPESRC(pipe),
4647 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4648}
4649
f564048e
EA		 4650static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4651 struct drm_display_mode *mode,
4652 struct drm_display_mode *adjusted_mode,
4653 int x, int y,
94352cf9 4654 struct drm_framebuffer *fb)
79e53945
JB		 4655{
4656 struct drm_device *dev = crtc->dev;
4657 struct drm_i915_private *dev_priv = dev->dev_private;
4658 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4659 int pipe = intel_crtc->pipe;
80824003 4660 int plane = intel_crtc->plane;
c751ce4f 4661 int refclk, num_connectors = 0;
652c393a 4662 intel_clock_t clock, reduced_clock;
b0e77b9c 4663 u32 dspcntr, pipeconf;
eb1cbe48
DV		 4664 bool ok, has_reduced_clock = false, is_sdvo = false;
4665 bool is_lvds = false, is_tv = false, is_dp = false;
5eddb70b 4666 struct intel_encoder *encoder;
d4906093 4667 const intel_limit_t *limit;
5c3b82e2 4668 int ret;
79e53945 4669
6c2b7c12 4670 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4671 switch (encoder->type) {
79e53945
JB		 4672 case INTEL_OUTPUT_LVDS:
4673 is_lvds = true;
4674 break;
4675 case INTEL_OUTPUT_SDVO:
7d57382e 4676 case INTEL_OUTPUT_HDMI:
79e53945 4677 is_sdvo = true;
5eddb70b 4678 if (encoder->needs_tv_clock)
e2f0ba97 4679 is_tv = true;
79e53945 4680 break;
79e53945
JB		 4681 case INTEL_OUTPUT_TVOUT:
4682 is_tv = true;
4683 break;
a4fc5ed6
KP		 4684 case INTEL_OUTPUT_DISPLAYPORT:
4685 is_dp = true;
4686 break;
79e53945 4687 }
43565a06 4688
c751ce4f 4689 num_connectors++;
79e53945
JB		 4690 }
4691
c65d77d8 4692 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4693
d4906093
ML		 4694 /*
4695 * Returns a set of divisors for the desired target clock with the given
4696 * refclk, or FALSE. The returned values represent the clock equation:
4697 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4698 */
1b894b59 4699 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4700 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4701 &clock);
79e53945
JB		 4702 if (!ok) {
4703 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4704 return -EINVAL;
79e53945
JB		 4705 }
4706
cda4b7d3 4707 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4708 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4709
ddc9003c 4710 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4711 /*
4712 * Ensure we match the reduced clock's P to the target clock.
4713 * If the clocks don't match, we can't switch the display clock
4714 * by using the FP0/FP1. In such case we will disable the LVDS
4715 * downclock feature.
4716 */
ddc9003c 4717 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4718 dev_priv->lvds_downclock,
4719 refclk,
cec2f356 4720 &clock,
5eddb70b 4721 &reduced_clock);
7026d4ac
ZW		 4722 }
4723
c65d77d8
JB		 4724 if (is_sdvo && is_tv)
4725 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 4726
eb1cbe48 4727 if (IS_GEN2(dev))
2a8f64ca
VP		 4728 i8xx_update_pll(crtc, adjusted_mode, &clock,
4729 has_reduced_clock ? &reduced_clock : NULL,
4730 num_connectors);
a0c4da24 4731 else if (IS_VALLEYVIEW(dev))
2a8f64ca
VP		 4732 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4733 has_reduced_clock ? &reduced_clock : NULL,
4734 num_connectors);
79e53945 4735 else
eb1cbe48
DV		 4736 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4737 has_reduced_clock ? &reduced_clock : NULL,
4738 num_connectors);
79e53945
JB		 4739
4740 /* setup pipeconf */
5eddb70b 4741 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4742
4743 /* Set up the display plane register */
4744 dspcntr = DISPPLANE_GAMMA_ENABLE;
4745
da6ecc5d
JB		 4746 if (!IS_VALLEYVIEW(dev)) {
4747 if (pipe == 0)
4748 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4749 else
4750 dspcntr |= DISPPLANE_SEL_PIPE_B;
4751 }
79e53945 4752
a6c45cf0 4753 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4754 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4755 * core speed.
4756 *
4757 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4758 * pipe == 0 check?
4759 */
e70236a8
JB		 4760 if (mode->clock >
4761 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4762 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4763 else
5eddb70b 4764 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4765 }
4766
3b5c78a3 4767 /* default to 8bpc */
dfd07d72 4768 pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
3b5c78a3 4769 if (is_dp) {
0c96c65b 4770 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
dfd07d72 4771 pipeconf |= PIPECONF_6BPC |
3b5c78a3
AJ		 4772 PIPECONF_DITHER_EN |
4773 PIPECONF_DITHER_TYPE_SP;
4774 }
4775 }
4776
19c03924
GB		 4777 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4778 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
dfd07d72 4779 pipeconf |= PIPECONF_6BPC |
19c03924
GB		 4780 PIPECONF_ENABLE |
4781 I965_PIPECONF_ACTIVE;
4782 }
4783 }
4784
28c97730 4785 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4786 drm_mode_debug_printmodeline(mode);
4787
a7516a05
JB		 4788 if (HAS_PIPE_CXSR(dev)) {
4789 if (intel_crtc->lowfreq_avail) {
28c97730 4790 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 4791 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 4792 } else {
28c97730 4793 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4794 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4795 }
4796 }
4797
617cf884 4798 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575 4799 if (!IS_GEN2(dev) &&
b0e77b9c 4800 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
734b4157 4801 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
b0e77b9c 4802 else
617cf884 4803 pipeconf |= PIPECONF_PROGRESSIVE;
734b4157 4804
b0e77b9c 4805 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4806
4807 /* pipesrc and dspsize control the size that is scaled from,
4808 * which should always be the user's requested size.
79e53945 4809 */
929c77fb
EA		 4810 I915_WRITE(DSPSIZE(plane),
4811 ((mode->vdisplay - 1) << 16) |
4812 (mode->hdisplay - 1));
4813 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4814
f564048e
EA		 4815 I915_WRITE(PIPECONF(pipe), pipeconf);
4816 POSTING_READ(PIPECONF(pipe));
929c77fb 4817 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4818
4819 intel_wait_for_vblank(dev, pipe);
4820
f564048e
EA		 4821 I915_WRITE(DSPCNTR(plane), dspcntr);
4822 POSTING_READ(DSPCNTR(plane));
4823
94352cf9 4824 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4825
4826 intel_update_watermarks(dev);
4827
f564048e
EA		 4828 return ret;
4829}
4830
dde86e2d 4831static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4832{
4833 struct drm_i915_private *dev_priv = dev->dev_private;
4834 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4835 struct intel_encoder *encoder;
13d83a67
JB		 4836 u32 temp;
4837 bool has_lvds = false;
199e5d79
KP		 4838 bool has_cpu_edp = false;
4839 bool has_pch_edp = false;
4840 bool has_panel = false;
99eb6a01
KP		 4841 bool has_ck505 = false;
4842 bool can_ssc = false;
13d83a67
JB		 4843
4844 /* We need to take the global config into account */
199e5d79
KP		 4845 list_for_each_entry(encoder, &mode_config->encoder_list,
4846 base.head) {
4847 switch (encoder->type) {
4848 case INTEL_OUTPUT_LVDS:
4849 has_panel = true;
4850 has_lvds = true;
4851 break;
4852 case INTEL_OUTPUT_EDP:
4853 has_panel = true;
4854 if (intel_encoder_is_pch_edp(&encoder->base))
4855 has_pch_edp = true;
4856 else
4857 has_cpu_edp = true;
4858 break;
13d83a67
JB		 4859 }
4860 }
4861
99eb6a01
KP		 4862 if (HAS_PCH_IBX(dev)) {
4863 has_ck505 = dev_priv->display_clock_mode;
4864 can_ssc = has_ck505;
4865 } else {
4866 has_ck505 = false;
4867 can_ssc = true;
4868 }
4869
4870 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4871 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4872 has_ck505);
13d83a67
JB		 4873
4874 /* Ironlake: try to setup display ref clock before DPLL
4875 * enabling. This is only under driver's control after
4876 * PCH B stepping, previous chipset stepping should be
4877 * ignoring this setting.
4878 */
4879 temp = I915_READ(PCH_DREF_CONTROL);
4880 /* Always enable nonspread source */
4881 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4882
99eb6a01
KP		 4883 if (has_ck505)
4884 temp |= DREF_NONSPREAD_CK505_ENABLE;
4885 else
4886 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4887
199e5d79
KP		 4888 if (has_panel) {
4889 temp &= ~DREF_SSC_SOURCE_MASK;
4890 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4891
199e5d79 4892 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4893 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4894 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4895 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4896 } else
4897 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4898
4899 /* Get SSC going before enabling the outputs */
4900 I915_WRITE(PCH_DREF_CONTROL, temp);
4901 POSTING_READ(PCH_DREF_CONTROL);
4902 udelay(200);
4903
13d83a67
JB		 4904 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4905
4906 /* Enable CPU source on CPU attached eDP */
199e5d79 4907 if (has_cpu_edp) {
99eb6a01 4908 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4909 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4910 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4911 }
13d83a67
JB		 4912 else
4913 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4914 } else
4915 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4916
4917 I915_WRITE(PCH_DREF_CONTROL, temp);
4918 POSTING_READ(PCH_DREF_CONTROL);
4919 udelay(200);
4920 } else {
4921 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4922
4923 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4924
4925 /* Turn off CPU output */
4926 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4927
4928 I915_WRITE(PCH_DREF_CONTROL, temp);
4929 POSTING_READ(PCH_DREF_CONTROL);
4930 udelay(200);
4931
4932 /* Turn off the SSC source */
4933 temp &= ~DREF_SSC_SOURCE_MASK;
4934 temp |= DREF_SSC_SOURCE_DISABLE;
4935
4936 /* Turn off SSC1 */
4937 temp &= ~ DREF_SSC1_ENABLE;
4938
13d83a67
JB		 4939 I915_WRITE(PCH_DREF_CONTROL, temp);
4940 POSTING_READ(PCH_DREF_CONTROL);
4941 udelay(200);
4942 }
4943}
4944
dde86e2d
PZ		 4945/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4946static void lpt_init_pch_refclk(struct drm_device *dev)
4947{
4948 struct drm_i915_private *dev_priv = dev->dev_private;
4949 struct drm_mode_config *mode_config = &dev->mode_config;
4950 struct intel_encoder *encoder;
4951 bool has_vga = false;
4952 bool is_sdv = false;
4953 u32 tmp;
4954
4955 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4956 switch (encoder->type) {
4957 case INTEL_OUTPUT_ANALOG:
4958 has_vga = true;
4959 break;
4960 }
4961 }
4962
4963 if (!has_vga)
4964 return;
4965
c00db246
DV		 4966 mutex_lock(&dev_priv->dpio_lock);
4967
dde86e2d
PZ		 4968 /* XXX: Rip out SDV support once Haswell ships for real. */
4969 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
4970 is_sdv = true;
4971
4972 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4973 tmp &= ~SBI_SSCCTL_DISABLE;
4974 tmp |= SBI_SSCCTL_PATHALT;
4975 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4976
4977 udelay(24);
4978
4979 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4980 tmp &= ~SBI_SSCCTL_PATHALT;
4981 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4982
4983 if (!is_sdv) {
4984 tmp = I915_READ(SOUTH_CHICKEN2);
4985 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
4986 I915_WRITE(SOUTH_CHICKEN2, tmp);
4987
4988 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
4989 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
4990 DRM_ERROR("FDI mPHY reset assert timeout\n");
4991
4992 tmp = I915_READ(SOUTH_CHICKEN2);
4993 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
4994 I915_WRITE(SOUTH_CHICKEN2, tmp);
4995
4996 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
4997 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
4998 100))
4999 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5000 }
5001
5002 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5003 tmp &= ~(0xFF << 24);
5004 tmp |= (0x12 << 24);
5005 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5006
5007 if (!is_sdv) {
5008 tmp = intel_sbi_read(dev_priv, 0x808C, SBI_MPHY);
5009 tmp &= ~(0x3 << 6);
5010 tmp |= (1 << 6) | (1 << 0);
5011 intel_sbi_write(dev_priv, 0x808C, tmp, SBI_MPHY);
5012 }
5013
5014 if (is_sdv) {
5015 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5016 tmp |= 0x7FFF;
5017 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5018 }
5019
5020 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5021 tmp |= (1 << 11);
5022 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5023
5024 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5025 tmp |= (1 << 11);
5026 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5027
5028 if (is_sdv) {
5029 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5030 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5031 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5032
5033 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5034 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5035 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5036
5037 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5038 tmp |= (0x3F << 8);
5039 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5040
5041 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5042 tmp |= (0x3F << 8);
5043 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5044 }
5045
5046 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5047 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5048 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5049
5050 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5051 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5052 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5053
5054 if (!is_sdv) {
5055 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5056 tmp &= ~(7 << 13);
5057 tmp |= (5 << 13);
5058 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5059
5060 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5061 tmp &= ~(7 << 13);
5062 tmp |= (5 << 13);
5063 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5064 }
5065
5066 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5067 tmp &= ~0xFF;
5068 tmp |= 0x1C;
5069 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5070
5071 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5072 tmp &= ~0xFF;
5073 tmp |= 0x1C;
5074 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5075
5076 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5077 tmp &= ~(0xFF << 16);
5078 tmp |= (0x1C << 16);
5079 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5080
5081 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5082 tmp &= ~(0xFF << 16);
5083 tmp |= (0x1C << 16);
5084 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5085
5086 if (!is_sdv) {
5087 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5088 tmp |= (1 << 27);
5089 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5090
5091 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5092 tmp |= (1 << 27);
5093 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5094
5095 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5096 tmp &= ~(0xF << 28);
5097 tmp |= (4 << 28);
5098 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5099
5100 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5101 tmp &= ~(0xF << 28);
5102 tmp |= (4 << 28);
5103 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5104 }
5105
5106 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5107 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5108 tmp |= SBI_DBUFF0_ENABLE;
5109 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5110
5111 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5112}
5113
5114/*
5115 * Initialize reference clocks when the driver loads
5116 */
5117void intel_init_pch_refclk(struct drm_device *dev)
5118{
5119 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5120 ironlake_init_pch_refclk(dev);
5121 else if (HAS_PCH_LPT(dev))
5122 lpt_init_pch_refclk(dev);
5123}
5124
d9d444cb
JB		 5125static int ironlake_get_refclk(struct drm_crtc *crtc)
5126{
5127 struct drm_device *dev = crtc->dev;
5128 struct drm_i915_private *dev_priv = dev->dev_private;
5129 struct intel_encoder *encoder;
d9d444cb
JB		 5130 struct intel_encoder *edp_encoder = NULL;
5131 int num_connectors = 0;
5132 bool is_lvds = false;
5133
6c2b7c12 5134 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5135 switch (encoder->type) {
5136 case INTEL_OUTPUT_LVDS:
5137 is_lvds = true;
5138 break;
5139 case INTEL_OUTPUT_EDP:
5140 edp_encoder = encoder;
5141 break;
5142 }
5143 num_connectors++;
5144 }
5145
5146 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5147 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5148 dev_priv->lvds_ssc_freq);
5149 return dev_priv->lvds_ssc_freq * 1000;
5150 }
5151
5152 return 120000;
5153}
5154
c8203565 5155static void ironlake_set_pipeconf(struct drm_crtc *crtc,
f564048e 5156 struct drm_display_mode *adjusted_mode,
c8203565 5157 bool dither)
79e53945 5158{
c8203565 5159 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5160 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5161 int pipe = intel_crtc->pipe;
c8203565
PZ		 5162 uint32_t val;
5163
5164 val = I915_READ(PIPECONF(pipe));
5165
dfd07d72 5166 val &= ~PIPECONF_BPC_MASK;
c8203565
PZ		 5167 switch (intel_crtc->bpp) {
5168 case 18:
dfd07d72 5169 val |= PIPECONF_6BPC;
c8203565
PZ		 5170 break;
5171 case 24:
dfd07d72 5172 val |= PIPECONF_8BPC;
c8203565
PZ		 5173 break;
5174 case 30:
dfd07d72 5175 val |= PIPECONF_10BPC;
c8203565
PZ		 5176 break;
5177 case 36:
dfd07d72 5178 val |= PIPECONF_12BPC;
c8203565
PZ		 5179 break;
5180 default:
cc769b62
PZ		 5181 /* Case prevented by intel_choose_pipe_bpp_dither. */
5182 BUG();
c8203565
PZ		 5183 }
5184
5185 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5186 if (dither)
5187 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5188
5189 val &= ~PIPECONF_INTERLACE_MASK;
5190 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5191 val |= PIPECONF_INTERLACED_ILK;
5192 else
5193 val |= PIPECONF_PROGRESSIVE;
5194
3685a8f3
VS		 5195 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5196 val |= PIPECONF_COLOR_RANGE_SELECT;
5197 else
5198 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5199
c8203565
PZ		 5200 I915_WRITE(PIPECONF(pipe), val);
5201 POSTING_READ(PIPECONF(pipe));
5202}
5203
86d3efce
VS		 5204/*
5205 * Set up the pipe CSC unit.
5206 *
5207 * Currently only full range RGB to limited range RGB conversion
5208 * is supported, but eventually this should handle various
5209 * RGB<->YCbCr scenarios as well.
5210 */
5211static void intel_set_pipe_csc(struct drm_crtc *crtc,
5212 const struct drm_display_mode *adjusted_mode)
5213{
5214 struct drm_device *dev = crtc->dev;
5215 struct drm_i915_private *dev_priv = dev->dev_private;
5216 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5217 int pipe = intel_crtc->pipe;
5218 uint16_t coeff = 0x7800; /* 1.0 */
5219
5220 /*
5221 * TODO: Check what kind of values actually come out of the pipe
5222 * with these coeff/postoff values and adjust to get the best
5223 * accuracy. Perhaps we even need to take the bpc value into
5224 * consideration.
5225 */
5226
5227 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5228 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5229
5230 /*
5231 * GY/GU and RY/RU should be the other way around according
5232 * to BSpec, but reality doesn't agree. Just set them up in
5233 * a way that results in the correct picture.
5234 */
5235 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5236 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5237
5238 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5239 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5240
5241 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5242 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5243
5244 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5245 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5246 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5247
5248 if (INTEL_INFO(dev)->gen > 6) {
5249 uint16_t postoff = 0;
5250
5251 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5252 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5253
5254 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5255 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5256 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5257
5258 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5259 } else {
5260 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5261
5262 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5263 mode |= CSC_BLACK_SCREEN_OFFSET;
5264
5265 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5266 }
5267}
5268
ee2b0b38
PZ		 5269static void haswell_set_pipeconf(struct drm_crtc *crtc,
5270 struct drm_display_mode *adjusted_mode,
5271 bool dither)
5272{
5273 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5274 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
702e7a56 5275 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
ee2b0b38
PZ		 5276 uint32_t val;
5277
702e7a56 5278 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5279
5280 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5281 if (dither)
5282 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5283
5284 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5285 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5286 val |= PIPECONF_INTERLACED_ILK;
5287 else
5288 val |= PIPECONF_PROGRESSIVE;
5289
702e7a56
PZ		 5290 I915_WRITE(PIPECONF(cpu_transcoder), val);
5291 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5292}
5293
6591c6e4
PZ		 5294static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5295 struct drm_display_mode *adjusted_mode,
5296 intel_clock_t *clock,
5297 bool *has_reduced_clock,
5298 intel_clock_t *reduced_clock)
5299{
5300 struct drm_device *dev = crtc->dev;
5301 struct drm_i915_private *dev_priv = dev->dev_private;
5302 struct intel_encoder *intel_encoder;
5303 int refclk;
d4906093 5304 const intel_limit_t *limit;
6591c6e4 5305 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
79e53945 5306
6591c6e4
PZ		 5307 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5308 switch (intel_encoder->type) {
79e53945
JB		 5309 case INTEL_OUTPUT_LVDS:
5310 is_lvds = true;
5311 break;
5312 case INTEL_OUTPUT_SDVO:
7d57382e 5313 case INTEL_OUTPUT_HDMI:
79e53945 5314 is_sdvo = true;
6591c6e4 5315 if (intel_encoder->needs_tv_clock)
e2f0ba97 5316 is_tv = true;
79e53945 5317 break;
79e53945
JB		 5318 case INTEL_OUTPUT_TVOUT:
5319 is_tv = true;
5320 break;
79e53945
JB		 5321 }
5322 }
5323
d9d444cb 5324 refclk = ironlake_get_refclk(crtc);
79e53945 5325
d4906093
ML		 5326 /*
5327 * Returns a set of divisors for the desired target clock with the given
5328 * refclk, or FALSE. The returned values represent the clock equation:
5329 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5330 */
1b894b59 5331 limit = intel_limit(crtc, refclk);
6591c6e4
PZ		 5332 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5333 clock);
5334 if (!ret)
5335 return false;
cda4b7d3 5336
ddc9003c 5337 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5338 /*
5339 * Ensure we match the reduced clock's P to the target clock.
5340 * If the clocks don't match, we can't switch the display clock
5341 * by using the FP0/FP1. In such case we will disable the LVDS
5342 * downclock feature.
5343 */
6591c6e4
PZ		 5344 *has_reduced_clock = limit->find_pll(limit, crtc,
5345 dev_priv->lvds_downclock,
5346 refclk,
5347 clock,
5348 reduced_clock);
652c393a 5349 }
61e9653f
DV		 5350
5351 if (is_sdvo && is_tv)
6591c6e4
PZ		 5352 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5353
5354 return true;
5355}
5356
01a415fd
DV		 5357static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5358{
5359 struct drm_i915_private *dev_priv = dev->dev_private;
5360 uint32_t temp;
5361
5362 temp = I915_READ(SOUTH_CHICKEN1);
5363 if (temp & FDI_BC_BIFURCATION_SELECT)
5364 return;
5365
5366 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5367 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5368
5369 temp |= FDI_BC_BIFURCATION_SELECT;
5370 DRM_DEBUG_KMS("enabling fdi C rx\n");
5371 I915_WRITE(SOUTH_CHICKEN1, temp);
5372 POSTING_READ(SOUTH_CHICKEN1);
5373}
5374
5375static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5376{
5377 struct drm_device *dev = intel_crtc->base.dev;
5378 struct drm_i915_private *dev_priv = dev->dev_private;
5379 struct intel_crtc *pipe_B_crtc =
5380 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5381
5382 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5383 intel_crtc->pipe, intel_crtc->fdi_lanes);
5384 if (intel_crtc->fdi_lanes > 4) {
5385 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5386 intel_crtc->pipe, intel_crtc->fdi_lanes);
5387 /* Clamp lanes to avoid programming the hw with bogus values. */
5388 intel_crtc->fdi_lanes = 4;
5389
5390 return false;
5391 }
5392
7eb552ae 5393 if (INTEL_INFO(dev)->num_pipes == 2)
01a415fd
DV		 5394 return true;
5395
5396 switch (intel_crtc->pipe) {
5397 case PIPE_A:
5398 return true;
5399 case PIPE_B:
5400 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5401 intel_crtc->fdi_lanes > 2) {
5402 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5403 intel_crtc->pipe, intel_crtc->fdi_lanes);
5404 /* Clamp lanes to avoid programming the hw with bogus values. */
5405 intel_crtc->fdi_lanes = 2;
5406
5407 return false;
5408 }
5409
5410 if (intel_crtc->fdi_lanes > 2)
5411 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5412 else
5413 cpt_enable_fdi_bc_bifurcation(dev);
5414
5415 return true;
5416 case PIPE_C:
5417 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5418 if (intel_crtc->fdi_lanes > 2) {
5419 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5420 intel_crtc->pipe, intel_crtc->fdi_lanes);
5421 /* Clamp lanes to avoid programming the hw with bogus values. */
5422 intel_crtc->fdi_lanes = 2;
5423
5424 return false;
5425 }
5426 } else {
5427 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5428 return false;
5429 }
5430
5431 cpt_enable_fdi_bc_bifurcation(dev);
5432
5433 return true;
5434 default:
5435 BUG();
5436 }
5437}
5438
d4b1931c
PZ		 5439int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5440{
5441 /*
5442 * Account for spread spectrum to avoid
5443 * oversubscribing the link. Max center spread
5444 * is 2.5%; use 5% for safety's sake.
5445 */
5446 u32 bps = target_clock * bpp * 21 / 20;
5447 return bps / (link_bw * 8) + 1;
5448}
5449
f48d8f23
PZ		 5450static void ironlake_set_m_n(struct drm_crtc *crtc,
5451 struct drm_display_mode *mode,
5452 struct drm_display_mode *adjusted_mode)
79e53945
JB		 5453{
5454 struct drm_device *dev = crtc->dev;
5455 struct drm_i915_private *dev_priv = dev->dev_private;
5456 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
afe2fcf5 5457 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
f48d8f23 5458 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
e69d0bc1 5459 struct intel_link_m_n m_n = {0};
f48d8f23
PZ		 5460 int target_clock, pixel_multiplier, lane, link_bw;
5461 bool is_dp = false, is_cpu_edp = false;
79e53945 5462
f48d8f23
PZ		 5463 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5464 switch (intel_encoder->type) {
a4fc5ed6
KP		 5465 case INTEL_OUTPUT_DISPLAYPORT:
5466 is_dp = true;
5467 break;
32f9d658 5468 case INTEL_OUTPUT_EDP:
e3aef172 5469 is_dp = true;
f48d8f23 5470 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5471 is_cpu_edp = true;
f48d8f23 5472 edp_encoder = intel_encoder;
32f9d658 5473 break;
79e53945 5474 }
79e53945 5475 }
61e9653f 5476
2c07245f 5477 /* FDI link */
8febb297
EA		 5478 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5479 lane = 0;
5480 /* CPU eDP doesn't require FDI link, so just set DP M/N
5481 according to current link config */
e3aef172 5482 if (is_cpu_edp) {
e3aef172 5483 intel_edp_link_config(edp_encoder, &lane, &link_bw);
8febb297 5484 } else {
8febb297
EA		 5485 /* FDI is a binary signal running at ~2.7GHz, encoding
5486 * each output octet as 10 bits. The actual frequency
5487 * is stored as a divider into a 100MHz clock, and the
5488 * mode pixel clock is stored in units of 1KHz.
5489 * Hence the bw of each lane in terms of the mode signal
5490 * is:
5491 */
5492 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5493 }
58a27471 5494
94bf2ced
DV		 5495 /* [e]DP over FDI requires target mode clock instead of link clock. */
5496 if (edp_encoder)
5497 target_clock = intel_edp_target_clock(edp_encoder, mode);
5498 else if (is_dp)
5499 target_clock = mode->clock;
5500 else
5501 target_clock = adjusted_mode->clock;
5502
d4b1931c
PZ		 5503 if (!lane)
5504 lane = ironlake_get_lanes_required(target_clock, link_bw,
5505 intel_crtc->bpp);
2c07245f 5506
8febb297
EA		 5507 intel_crtc->fdi_lanes = lane;
5508
5509 if (pixel_multiplier > 1)
5510 link_bw *= pixel_multiplier;
e69d0bc1 5511 intel_link_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw, &m_n);
8febb297 5512
afe2fcf5
PZ		 5513 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5514 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5515 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5516 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
f48d8f23
PZ		 5517}
5518
de13a2e3
PZ		 5519static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5520 struct drm_display_mode *adjusted_mode,
5521 intel_clock_t *clock, u32 fp)
79e53945 5522{
de13a2e3 5523 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5524 struct drm_device *dev = crtc->dev;
5525 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5526 struct intel_encoder *intel_encoder;
5527 uint32_t dpll;
5528 int factor, pixel_multiplier, num_connectors = 0;
5529 bool is_lvds = false, is_sdvo = false, is_tv = false;
5530 bool is_dp = false, is_cpu_edp = false;
79e53945 5531
de13a2e3
PZ		 5532 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5533 switch (intel_encoder->type) {
79e53945
JB		 5534 case INTEL_OUTPUT_LVDS:
5535 is_lvds = true;
5536 break;
5537 case INTEL_OUTPUT_SDVO:
7d57382e 5538 case INTEL_OUTPUT_HDMI:
79e53945 5539 is_sdvo = true;
de13a2e3 5540 if (intel_encoder->needs_tv_clock)
e2f0ba97 5541 is_tv = true;
79e53945 5542 break;
79e53945
JB		 5543 case INTEL_OUTPUT_TVOUT:
5544 is_tv = true;
5545 break;
a4fc5ed6
KP		 5546 case INTEL_OUTPUT_DISPLAYPORT:
5547 is_dp = true;
5548 break;
32f9d658 5549 case INTEL_OUTPUT_EDP:
e3aef172 5550 is_dp = true;
de13a2e3 5551 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5552 is_cpu_edp = true;
32f9d658 5553 break;
79e53945 5554 }
43565a06 5555
c751ce4f 5556 num_connectors++;
79e53945 5557 }
79e53945 5558
c1858123 5559 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5560 factor = 21;
5561 if (is_lvds) {
5562 if ((intel_panel_use_ssc(dev_priv) &&
5563 dev_priv->lvds_ssc_freq == 100) ||
1974cad0 5564 intel_is_dual_link_lvds(dev))
8febb297
EA		 5565 factor = 25;
5566 } else if (is_sdvo && is_tv)
5567 factor = 20;
c1858123 5568
de13a2e3 5569 if (clock->m < factor * clock->n)
8febb297 5570 fp |= FP_CB_TUNE;
2c07245f 5571
5eddb70b 5572 dpll = 0;
2c07245f 5573
a07d6787
EA		 5574 if (is_lvds)
5575 dpll |= DPLLB_MODE_LVDS;
5576 else
5577 dpll |= DPLLB_MODE_DAC_SERIAL;
5578 if (is_sdvo) {
de13a2e3 5579 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
a07d6787
EA		 5580 if (pixel_multiplier > 1) {
5581 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5582 }
a07d6787
EA		 5583 dpll |= DPLL_DVO_HIGH_SPEED;
5584 }
e3aef172 5585 if (is_dp && !is_cpu_edp)
a07d6787 5586 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5587
a07d6787 5588 /* compute bitmask from p1 value */
de13a2e3 5589 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5590 /* also FPA1 */
de13a2e3 5591 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5592
de13a2e3 5593 switch (clock->p2) {
a07d6787
EA		 5594 case 5:
5595 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5596 break;
5597 case 7:
5598 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5599 break;
5600 case 10:
5601 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5602 break;
5603 case 14:
5604 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5605 break;
79e53945
JB		 5606 }
5607
43565a06
KH		 5608 if (is_sdvo && is_tv)
5609 dpll |= PLL_REF_INPUT_TVCLKINBC;
5610 else if (is_tv)
79e53945 5611 /* XXX: just matching BIOS for now */
43565a06 5612 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5613 dpll |= 3;
a7615030 5614 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5615 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5616 else
5617 dpll |= PLL_REF_INPUT_DREFCLK;
5618
de13a2e3
PZ		 5619 return dpll;
5620}
5621
5622static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5623 struct drm_display_mode *mode,
5624 struct drm_display_mode *adjusted_mode,
5625 int x, int y,
5626 struct drm_framebuffer *fb)
5627{
5628 struct drm_device *dev = crtc->dev;
5629 struct drm_i915_private *dev_priv = dev->dev_private;
5630 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5631 int pipe = intel_crtc->pipe;
5632 int plane = intel_crtc->plane;
5633 int num_connectors = 0;
5634 intel_clock_t clock, reduced_clock;
5635 u32 dpll, fp = 0, fp2 = 0;
e2f12b07
PZ		 5636 bool ok, has_reduced_clock = false;
5637 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
de13a2e3 5638 struct intel_encoder *encoder;
de13a2e3 5639 int ret;
01a415fd 5640 bool dither, fdi_config_ok;
de13a2e3
PZ		 5641
5642 for_each_encoder_on_crtc(dev, crtc, encoder) {
5643 switch (encoder->type) {
5644 case INTEL_OUTPUT_LVDS:
5645 is_lvds = true;
5646 break;
de13a2e3
PZ		 5647 case INTEL_OUTPUT_DISPLAYPORT:
5648 is_dp = true;
5649 break;
5650 case INTEL_OUTPUT_EDP:
5651 is_dp = true;
e2f12b07 5652 if (!intel_encoder_is_pch_edp(&encoder->base))
de13a2e3
PZ		 5653 is_cpu_edp = true;
5654 break;
5655 }
5656
5657 num_connectors++;
a07d6787 5658 }
79e53945 5659
5dc5298b
PZ		 5660 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5661 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5662
de13a2e3
PZ		 5663 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5664 &has_reduced_clock, &reduced_clock);
5665 if (!ok) {
5666 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5667 return -EINVAL;
79e53945
JB		 5668 }
5669
de13a2e3
PZ		 5670 /* Ensure that the cursor is valid for the new mode before changing... */
5671 intel_crtc_update_cursor(crtc, true);
5672
5673 /* determine panel color depth */
c8241969
JN		 5674 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5675 adjusted_mode);
de13a2e3
PZ		 5676 if (is_lvds && dev_priv->lvds_dither)
5677 dither = true;
5678
5679 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5680 if (has_reduced_clock)
5681 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5682 reduced_clock.m2;
5683
5684 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
79e53945 5685
f7cb34d4 5686 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5687 drm_mode_debug_printmodeline(mode);
5688
5dc5298b
PZ		 5689 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5690 if (!is_cpu_edp) {
ee7b9f93 5691 struct intel_pch_pll *pll;
4b645f14 5692
ee7b9f93
JB		 5693 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5694 if (pll == NULL) {
5695 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5696 pipe);
4b645f14
JB		 5697 return -EINVAL;
5698 }
ee7b9f93
JB		 5699 } else
5700 intel_put_pch_pll(intel_crtc);
79e53945 5701
2f0c2ad1 5702 if (is_dp && !is_cpu_edp)
a4fc5ed6 5703 intel_dp_set_m_n(crtc, mode, adjusted_mode);
79e53945 5704
dafd226c
DV		 5705 for_each_encoder_on_crtc(dev, crtc, encoder)
5706 if (encoder->pre_pll_enable)
5707 encoder->pre_pll_enable(encoder);
79e53945 5708
ee7b9f93
JB		 5709 if (intel_crtc->pch_pll) {
5710 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5711
32f9d658 5712 /* Wait for the clocks to stabilize. */
ee7b9f93 5713 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5714 udelay(150);
5715
8febb297
EA		 5716 /* The pixel multiplier can only be updated once the
5717 * DPLL is enabled and the clocks are stable.
5718 *
5719 * So write it again.
5720 */
ee7b9f93 5721 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5722 }
79e53945 5723
5eddb70b 5724 intel_crtc->lowfreq_avail = false;
ee7b9f93 5725 if (intel_crtc->pch_pll) {
4b645f14 5726 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5727 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5728 intel_crtc->lowfreq_avail = true;
4b645f14 5729 } else {
ee7b9f93 5730 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5731 }
5732 }
5733
b0e77b9c 5734 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b 5735
01a415fd
DV		 5736 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5737 * ironlake_check_fdi_lanes. */
f48d8f23 5738 ironlake_set_m_n(crtc, mode, adjusted_mode);
2c07245f 5739
01a415fd 5740 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
2c07245f 5741
c8203565 5742 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
79e53945 5743
9d0498a2 5744 intel_wait_for_vblank(dev, pipe);
79e53945 5745
a1f9e77e
PZ		 5746 /* Set up the display plane register */
5747 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5748 POSTING_READ(DSPCNTR(plane));
79e53945 5749
94352cf9 5750 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5751
5752 intel_update_watermarks(dev);
5753
1f8eeabf
ED		 5754 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5755
01a415fd 5756 return fdi_config_ok ? ret : -EINVAL;
79e53945
JB		 5757}
5758
d6dd9eb1
DV		 5759static void haswell_modeset_global_resources(struct drm_device *dev)
5760{
5761 struct drm_i915_private *dev_priv = dev->dev_private;
5762 bool enable = false;
5763 struct intel_crtc *crtc;
5764 struct intel_encoder *encoder;
5765
5766 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5767 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5768 enable = true;
5769 /* XXX: Should check for edp transcoder here, but thanks to init
5770 * sequence that's not yet available. Just in case desktop eDP
5771 * on PORT D is possible on haswell, too. */
5772 }
5773
5774 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5775 base.head) {
5776 if (encoder->type != INTEL_OUTPUT_EDP &&
5777 encoder->connectors_active)
5778 enable = true;
5779 }
5780
5781 /* Even the eDP panel fitter is outside the always-on well. */
5782 if (dev_priv->pch_pf_size)
5783 enable = true;
5784
5785 intel_set_power_well(dev, enable);
5786}
5787
09b4ddf9
PZ		 5788static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5789 struct drm_display_mode *mode,
5790 struct drm_display_mode *adjusted_mode,
5791 int x, int y,
5792 struct drm_framebuffer *fb)
5793{
5794 struct drm_device *dev = crtc->dev;
5795 struct drm_i915_private *dev_priv = dev->dev_private;
5796 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5797 int pipe = intel_crtc->pipe;
5798 int plane = intel_crtc->plane;
5799 int num_connectors = 0;
ed7ef439 5800 bool is_dp = false, is_cpu_edp = false;
09b4ddf9 5801 struct intel_encoder *encoder;
09b4ddf9
PZ		 5802 int ret;
5803 bool dither;
5804
5805 for_each_encoder_on_crtc(dev, crtc, encoder) {
5806 switch (encoder->type) {
09b4ddf9
PZ		 5807 case INTEL_OUTPUT_DISPLAYPORT:
5808 is_dp = true;
5809 break;
5810 case INTEL_OUTPUT_EDP:
5811 is_dp = true;
5812 if (!intel_encoder_is_pch_edp(&encoder->base))
5813 is_cpu_edp = true;
5814 break;
5815 }
5816
5817 num_connectors++;
5818 }
5819
5dc5298b
PZ		 5820 /* We are not sure yet this won't happen. */
5821 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5822 INTEL_PCH_TYPE(dev));
5823
5824 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5825 num_connectors, pipe_name(pipe));
5826
702e7a56 5827 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
1ce42920
PZ		 5828 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5829
5830 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5831
6441ab5f
PZ		 5832 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5833 return -EINVAL;
5834
09b4ddf9
PZ		 5835 /* Ensure that the cursor is valid for the new mode before changing... */
5836 intel_crtc_update_cursor(crtc, true);
5837
5838 /* determine panel color depth */
c8241969
JN		 5839 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5840 adjusted_mode);
09b4ddf9 5841
09b4ddf9
PZ		 5842 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5843 drm_mode_debug_printmodeline(mode);
5844
ed7ef439 5845 if (is_dp && !is_cpu_edp)
09b4ddf9 5846 intel_dp_set_m_n(crtc, mode, adjusted_mode);
09b4ddf9
PZ		 5847
5848 intel_crtc->lowfreq_avail = false;
09b4ddf9
PZ		 5849
5850 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5851
1eb8dfec
PZ		 5852 if (!is_dp || is_cpu_edp)
5853 ironlake_set_m_n(crtc, mode, adjusted_mode);
09b4ddf9 5854
ee2b0b38 5855 haswell_set_pipeconf(crtc, adjusted_mode, dither);
09b4ddf9 5856
86d3efce
VS		 5857 intel_set_pipe_csc(crtc, adjusted_mode);
5858
09b4ddf9 5859 /* Set up the display plane register */
86d3efce 5860 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5861 POSTING_READ(DSPCNTR(plane));
5862
5863 ret = intel_pipe_set_base(crtc, x, y, fb);
5864
5865 intel_update_watermarks(dev);
5866
5867 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5868
1f803ee5 5869 return ret;
79e53945
JB		 5870}
5871
f564048e
EA		 5872static int intel_crtc_mode_set(struct drm_crtc *crtc,
5873 struct drm_display_mode *mode,
5874 struct drm_display_mode *adjusted_mode,
5875 int x, int y,
94352cf9 5876 struct drm_framebuffer *fb)
f564048e
EA		 5877{
5878 struct drm_device *dev = crtc->dev;
5879 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 5880 struct drm_encoder_helper_funcs *encoder_funcs;
5881 struct intel_encoder *encoder;
0b701d27
EA		 5882 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5883 int pipe = intel_crtc->pipe;
f564048e
EA		 5884 int ret;
5885
cc464b2a
PZ		 5886 if (IS_HASWELL(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
5887 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5888 else
5889 intel_crtc->cpu_transcoder = pipe;
5890
0b701d27 5891 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5892
f564048e 5893 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
94352cf9 5894 x, y, fb);
79e53945 5895 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5896
9256aa19
DV		 5897 if (ret != 0)
5898 return ret;
5899
5900 for_each_encoder_on_crtc(dev, crtc, encoder) {
5901 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5902 encoder->base.base.id,
5903 drm_get_encoder_name(&encoder->base),
5904 mode->base.id, mode->name);
5905 encoder_funcs = encoder->base.helper_private;
5906 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5907 }
5908
5909 return 0;
79e53945
JB		 5910}
5911
3a9627f4
WF		 5912static bool intel_eld_uptodate(struct drm_connector *connector,
5913 int reg_eldv, uint32_t bits_eldv,
5914 int reg_elda, uint32_t bits_elda,
5915 int reg_edid)
5916{
5917 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5918 uint8_t *eld = connector->eld;
5919 uint32_t i;
5920
5921 i = I915_READ(reg_eldv);
5922 i &= bits_eldv;
5923
5924 if (!eld[0])
5925 return !i;
5926
5927 if (!i)
5928 return false;
5929
5930 i = I915_READ(reg_elda);
5931 i &= ~bits_elda;
5932 I915_WRITE(reg_elda, i);
5933
5934 for (i = 0; i < eld[2]; i++)
5935 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5936 return false;
5937
5938 return true;
5939}
5940
e0dac65e
WF		 5941static void g4x_write_eld(struct drm_connector *connector,
5942 struct drm_crtc *crtc)
5943{
5944 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5945 uint8_t *eld = connector->eld;
5946 uint32_t eldv;
5947 uint32_t len;
5948 uint32_t i;
5949
5950 i = I915_READ(G4X_AUD_VID_DID);
5951
5952 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5953 eldv = G4X_ELDV_DEVCL_DEVBLC;
5954 else
5955 eldv = G4X_ELDV_DEVCTG;
5956
3a9627f4
WF		 5957 if (intel_eld_uptodate(connector,
5958 G4X_AUD_CNTL_ST, eldv,
5959 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5960 G4X_HDMIW_HDMIEDID))
5961 return;
5962
e0dac65e
WF		 5963 i = I915_READ(G4X_AUD_CNTL_ST);
5964 i &= ~(eldv | G4X_ELD_ADDR);
5965 len = (i >> 9) & 0x1f; /* ELD buffer size */
5966 I915_WRITE(G4X_AUD_CNTL_ST, i);
5967
5968 if (!eld[0])
5969 return;
5970
5971 len = min_t(uint8_t, eld[2], len);
5972 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5973 for (i = 0; i < len; i++)
5974 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5975
5976 i = I915_READ(G4X_AUD_CNTL_ST);
5977 i |= eldv;
5978 I915_WRITE(G4X_AUD_CNTL_ST, i);
5979}
5980
83358c85
WX		 5981static void haswell_write_eld(struct drm_connector *connector,
5982 struct drm_crtc *crtc)
5983{
5984 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5985 uint8_t *eld = connector->eld;
5986 struct drm_device *dev = crtc->dev;
7b9f35a6 5987 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 5988 uint32_t eldv;
5989 uint32_t i;
5990 int len;
5991 int pipe = to_intel_crtc(crtc)->pipe;
5992 int tmp;
5993
5994 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5995 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5996 int aud_config = HSW_AUD_CFG(pipe);
5997 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5998
5999
6000 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6001
6002 /* Audio output enable */
6003 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6004 tmp = I915_READ(aud_cntrl_st2);
6005 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6006 I915_WRITE(aud_cntrl_st2, tmp);
6007
6008 /* Wait for 1 vertical blank */
6009 intel_wait_for_vblank(dev, pipe);
6010
6011 /* Set ELD valid state */
6012 tmp = I915_READ(aud_cntrl_st2);
6013 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6014 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6015 I915_WRITE(aud_cntrl_st2, tmp);
6016 tmp = I915_READ(aud_cntrl_st2);
6017 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6018
6019 /* Enable HDMI mode */
6020 tmp = I915_READ(aud_config);
6021 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6022 /* clear N_programing_enable and N_value_index */
6023 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6024 I915_WRITE(aud_config, tmp);
6025
6026 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6027
6028 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6029 intel_crtc->eld_vld = true;
83358c85
WX		 6030
6031 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6032 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6033 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6034 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6035 } else
6036 I915_WRITE(aud_config, 0);
6037
6038 if (intel_eld_uptodate(connector,
6039 aud_cntrl_st2, eldv,
6040 aud_cntl_st, IBX_ELD_ADDRESS,
6041 hdmiw_hdmiedid))
6042 return;
6043
6044 i = I915_READ(aud_cntrl_st2);
6045 i &= ~eldv;
6046 I915_WRITE(aud_cntrl_st2, i);
6047
6048 if (!eld[0])
6049 return;
6050
6051 i = I915_READ(aud_cntl_st);
6052 i &= ~IBX_ELD_ADDRESS;
6053 I915_WRITE(aud_cntl_st, i);
6054 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6055 DRM_DEBUG_DRIVER("port num:%d\n", i);
6056
6057 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6058 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6059 for (i = 0; i < len; i++)
6060 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6061
6062 i = I915_READ(aud_cntrl_st2);
6063 i |= eldv;
6064 I915_WRITE(aud_cntrl_st2, i);
6065
6066}
6067
e0dac65e
WF		 6068static void ironlake_write_eld(struct drm_connector *connector,
6069 struct drm_crtc *crtc)
6070{
6071 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6072 uint8_t *eld = connector->eld;
6073 uint32_t eldv;
6074 uint32_t i;
6075 int len;
6076 int hdmiw_hdmiedid;
b6daa025 6077 int aud_config;
e0dac65e
WF		 6078 int aud_cntl_st;
6079 int aud_cntrl_st2;
9b138a83 6080 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6081
b3f33cbf 6082 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6083 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6084 aud_config = IBX_AUD_CFG(pipe);
6085 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6086 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6087 } else {
9b138a83
WX		 6088 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6089 aud_config = CPT_AUD_CFG(pipe);
6090 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6091 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6092 }
6093
9b138a83 6094 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6095
6096 i = I915_READ(aud_cntl_st);
9b138a83 6097 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6098 if (!i) {
6099 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6100 /* operate blindly on all ports */
1202b4c6
WF		 6101 eldv = IBX_ELD_VALIDB;
6102 eldv |= IBX_ELD_VALIDB << 4;
6103 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 6104 } else {
6105 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 6106 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6107 }
6108
3a9627f4
WF		 6109 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6110 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6111 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6112 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6113 } else
6114 I915_WRITE(aud_config, 0);
e0dac65e 6115
3a9627f4
WF		 6116 if (intel_eld_uptodate(connector,
6117 aud_cntrl_st2, eldv,
6118 aud_cntl_st, IBX_ELD_ADDRESS,
6119 hdmiw_hdmiedid))
6120 return;
6121
e0dac65e
WF		 6122 i = I915_READ(aud_cntrl_st2);
6123 i &= ~eldv;
6124 I915_WRITE(aud_cntrl_st2, i);
6125
6126 if (!eld[0])
6127 return;
6128
e0dac65e 6129 i = I915_READ(aud_cntl_st);
1202b4c6 6130 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6131 I915_WRITE(aud_cntl_st, i);
6132
6133 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6134 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6135 for (i = 0; i < len; i++)
6136 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6137
6138 i = I915_READ(aud_cntrl_st2);
6139 i |= eldv;
6140 I915_WRITE(aud_cntrl_st2, i);
6141}
6142
6143void intel_write_eld(struct drm_encoder *encoder,
6144 struct drm_display_mode *mode)
6145{
6146 struct drm_crtc *crtc = encoder->crtc;
6147 struct drm_connector *connector;
6148 struct drm_device *dev = encoder->dev;
6149 struct drm_i915_private *dev_priv = dev->dev_private;
6150
6151 connector = drm_select_eld(encoder, mode);
6152 if (!connector)
6153 return;
6154
6155 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6156 connector->base.id,
6157 drm_get_connector_name(connector),
6158 connector->encoder->base.id,
6159 drm_get_encoder_name(connector->encoder));
6160
6161 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6162
6163 if (dev_priv->display.write_eld)
6164 dev_priv->display.write_eld(connector, crtc);
6165}
6166
79e53945
JB		 6167/** Loads the palette/gamma unit for the CRTC with the prepared values */
6168void intel_crtc_load_lut(struct drm_crtc *crtc)
6169{
6170 struct drm_device *dev = crtc->dev;
6171 struct drm_i915_private *dev_priv = dev->dev_private;
6172 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6173 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6174 int i;
6175
6176 /* The clocks have to be on to load the palette. */
aed3f09d 6177 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6178 return;
6179
f2b115e6 6180 /* use legacy palette for Ironlake */
bad720ff 6181 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6182 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6183
79e53945
JB		 6184 for (i = 0; i < 256; i++) {
6185 I915_WRITE(palreg + 4 * i,
6186 (intel_crtc->lut_r[i] << 16) |
6187 (intel_crtc->lut_g[i] << 8) |
6188 intel_crtc->lut_b[i]);
6189 }
6190}
6191
560b85bb
CW		 6192static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6193{
6194 struct drm_device *dev = crtc->dev;
6195 struct drm_i915_private *dev_priv = dev->dev_private;
6196 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6197 bool visible = base != 0;
6198 u32 cntl;
6199
6200 if (intel_crtc->cursor_visible == visible)
6201 return;
6202
9db4a9c7 6203 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6204 if (visible) {
6205 /* On these chipsets we can only modify the base whilst
6206 * the cursor is disabled.
6207 */
9db4a9c7 6208 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6209
6210 cntl &= ~(CURSOR_FORMAT_MASK);
6211 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6212 cntl |= CURSOR_ENABLE |
6213 CURSOR_GAMMA_ENABLE |
6214 CURSOR_FORMAT_ARGB;
6215 } else
6216 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6217 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6218
6219 intel_crtc->cursor_visible = visible;
6220}
6221
6222static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6223{
6224 struct drm_device *dev = crtc->dev;
6225 struct drm_i915_private *dev_priv = dev->dev_private;
6226 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6227 int pipe = intel_crtc->pipe;
6228 bool visible = base != 0;
6229
6230 if (intel_crtc->cursor_visible != visible) {
548f245b 6231 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6232 if (base) {
6233 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6234 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6235 cntl |= pipe << 28; /* Connect to correct pipe */
6236 } else {
6237 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6238 cntl |= CURSOR_MODE_DISABLE;
6239 }
9db4a9c7 6240 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6241
6242 intel_crtc->cursor_visible = visible;
6243 }
6244 /* and commit changes on next vblank */
9db4a9c7 6245 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6246}
6247
65a21cd6
JB		 6248static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6249{
6250 struct drm_device *dev = crtc->dev;
6251 struct drm_i915_private *dev_priv = dev->dev_private;
6252 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6253 int pipe = intel_crtc->pipe;
6254 bool visible = base != 0;
6255
6256 if (intel_crtc->cursor_visible != visible) {
6257 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6258 if (base) {
6259 cntl &= ~CURSOR_MODE;
6260 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6261 } else {
6262 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6263 cntl |= CURSOR_MODE_DISABLE;
6264 }
86d3efce
VS		 6265 if (IS_HASWELL(dev))
6266 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6267 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6268
6269 intel_crtc->cursor_visible = visible;
6270 }
6271 /* and commit changes on next vblank */
6272 I915_WRITE(CURBASE_IVB(pipe), base);
6273}
6274
cda4b7d3 6275/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6276static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6277 bool on)
cda4b7d3
CW		 6278{
6279 struct drm_device *dev = crtc->dev;
6280 struct drm_i915_private *dev_priv = dev->dev_private;
6281 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6282 int pipe = intel_crtc->pipe;
6283 int x = intel_crtc->cursor_x;
6284 int y = intel_crtc->cursor_y;
560b85bb 6285 u32 base, pos;
cda4b7d3
CW		 6286 bool visible;
6287
6288 pos = 0;
6289
6b383a7f 6290 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6291 base = intel_crtc->cursor_addr;
6292 if (x > (int) crtc->fb->width)
6293 base = 0;
6294
6295 if (y > (int) crtc->fb->height)
6296 base = 0;
6297 } else
6298 base = 0;
6299
6300 if (x < 0) {
6301 if (x + intel_crtc->cursor_width < 0)
6302 base = 0;
6303
6304 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6305 x = -x;
6306 }
6307 pos |= x << CURSOR_X_SHIFT;
6308
6309 if (y < 0) {
6310 if (y + intel_crtc->cursor_height < 0)
6311 base = 0;
6312
6313 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6314 y = -y;
6315 }
6316 pos |= y << CURSOR_Y_SHIFT;
6317
6318 visible = base != 0;
560b85bb 6319 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6320 return;
6321
0cd83aa9 6322 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6323 I915_WRITE(CURPOS_IVB(pipe), pos);
6324 ivb_update_cursor(crtc, base);
6325 } else {
6326 I915_WRITE(CURPOS(pipe), pos);
6327 if (IS_845G(dev) || IS_I865G(dev))
6328 i845_update_cursor(crtc, base);
6329 else
6330 i9xx_update_cursor(crtc, base);
6331 }
cda4b7d3
CW		 6332}
6333
79e53945 6334static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6335 struct drm_file *file,
79e53945
JB		 6336 uint32_t handle,
6337 uint32_t width, uint32_t height)
6338{
6339 struct drm_device *dev = crtc->dev;
6340 struct drm_i915_private *dev_priv = dev->dev_private;
6341 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6342 struct drm_i915_gem_object *obj;
cda4b7d3 6343 uint32_t addr;
3f8bc370 6344 int ret;
79e53945 6345
79e53945
JB		 6346 /* if we want to turn off the cursor ignore width and height */
6347 if (!handle) {
28c97730 6348 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6349 addr = 0;
05394f39 6350 obj = NULL;
5004417d 6351 mutex_lock(&dev->struct_mutex);
3f8bc370 6352 goto finish;
79e53945
JB		 6353 }
6354
6355 /* Currently we only support 64x64 cursors */
6356 if (width != 64 || height != 64) {
6357 DRM_ERROR("we currently only support 64x64 cursors\n");
6358 return -EINVAL;
6359 }
6360
05394f39 6361 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6362 if (&obj->base == NULL)
79e53945
JB		 6363 return -ENOENT;
6364
05394f39 6365 if (obj->base.size < width * height * 4) {
79e53945 6366 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6367 ret = -ENOMEM;
6368 goto fail;
79e53945
JB		 6369 }
6370
71acb5eb 6371 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6372 mutex_lock(&dev->struct_mutex);
b295d1b6 6373 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 6374 if (obj->tiling_mode) {
6375 DRM_ERROR("cursor cannot be tiled\n");
6376 ret = -EINVAL;
6377 goto fail_locked;
6378 }
6379
2da3b9b9 6380 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 6381 if (ret) {
6382 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6383 goto fail_locked;
e7b526bb
CW		 6384 }
6385
d9e86c0e
CW		 6386 ret = i915_gem_object_put_fence(obj);
6387 if (ret) {
2da3b9b9 6388 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6389 goto fail_unpin;
6390 }
6391
05394f39 6392 addr = obj->gtt_offset;
71acb5eb 6393 } else {
6eeefaf3 6394 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6395 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6396 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6397 align);
71acb5eb
DA		 6398 if (ret) {
6399 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6400 goto fail_locked;
71acb5eb 6401 }
05394f39 6402 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6403 }
6404
a6c45cf0 6405 if (IS_GEN2(dev))
14b60391
JB		 6406 I915_WRITE(CURSIZE, (height << 12) | width);
6407
3f8bc370 6408 finish:
3f8bc370 6409 if (intel_crtc->cursor_bo) {
b295d1b6 6410 if (dev_priv->info->cursor_needs_physical) {
05394f39 6411 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6412 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6413 } else
6414 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6415 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6416 }
80824003 6417
7f9872e0 6418 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6419
6420 intel_crtc->cursor_addr = addr;
05394f39 6421 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6422 intel_crtc->cursor_width = width;
6423 intel_crtc->cursor_height = height;
6424
6b383a7f 6425 intel_crtc_update_cursor(crtc, true);
3f8bc370 6426
79e53945 6427 return 0;
e7b526bb 6428fail_unpin:
05394f39 6429 i915_gem_object_unpin(obj);
7f9872e0 6430fail_locked:
34b8686e 6431 mutex_unlock(&dev->struct_mutex);
bc9025bd 6432fail:
05394f39 6433 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6434 return ret;
79e53945
JB		 6435}
6436
6437static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6438{
79e53945 6439 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6440
cda4b7d3
CW		 6441 intel_crtc->cursor_x = x;
6442 intel_crtc->cursor_y = y;
652c393a 6443
6b383a7f 6444 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6445
6446 return 0;
6447}
6448
6449/** Sets the color ramps on behalf of RandR */
6450void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6451 u16 blue, int regno)
6452{
6453 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6454
6455 intel_crtc->lut_r[regno] = red >> 8;
6456 intel_crtc->lut_g[regno] = green >> 8;
6457 intel_crtc->lut_b[regno] = blue >> 8;
6458}
6459
b8c00ac5
DA		 6460void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6461 u16 *blue, int regno)
6462{
6463 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6464
6465 *red = intel_crtc->lut_r[regno] << 8;
6466 *green = intel_crtc->lut_g[regno] << 8;
6467 *blue = intel_crtc->lut_b[regno] << 8;
6468}
6469
79e53945 6470static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6471 u16 *blue, uint32_t start, uint32_t size)
79e53945 6472{
7203425a 6473 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6474 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6475
7203425a 6476 for (i = start; i < end; i++) {
79e53945
JB		 6477 intel_crtc->lut_r[i] = red[i] >> 8;
6478 intel_crtc->lut_g[i] = green[i] >> 8;
6479 intel_crtc->lut_b[i] = blue[i] >> 8;
6480 }
6481
6482 intel_crtc_load_lut(crtc);
6483}
6484
79e53945
JB		 6485/* VESA 640x480x72Hz mode to set on the pipe */
6486static struct drm_display_mode load_detect_mode = {
6487 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6488 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6489};
6490
d2dff872
CW		 6491static struct drm_framebuffer *
6492intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6493 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6494 struct drm_i915_gem_object *obj)
6495{
6496 struct intel_framebuffer *intel_fb;
6497 int ret;
6498
6499 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6500 if (!intel_fb) {
6501 drm_gem_object_unreference_unlocked(&obj->base);
6502 return ERR_PTR(-ENOMEM);
6503 }
6504
6505 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6506 if (ret) {
6507 drm_gem_object_unreference_unlocked(&obj->base);
6508 kfree(intel_fb);
6509 return ERR_PTR(ret);
6510 }
6511
6512 return &intel_fb->base;
6513}
6514
6515static u32
6516intel_framebuffer_pitch_for_width(int width, int bpp)
6517{
6518 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6519 return ALIGN(pitch, 64);
6520}
6521
6522static u32
6523intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6524{
6525 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6526 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6527}
6528
6529static struct drm_framebuffer *
6530intel_framebuffer_create_for_mode(struct drm_device *dev,
6531 struct drm_display_mode *mode,
6532 int depth, int bpp)
6533{
6534 struct drm_i915_gem_object *obj;
0fed39bd 6535 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6536
6537 obj = i915_gem_alloc_object(dev,
6538 intel_framebuffer_size_for_mode(mode, bpp));
6539 if (obj == NULL)
6540 return ERR_PTR(-ENOMEM);
6541
6542 mode_cmd.width = mode->hdisplay;
6543 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6544 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6545 bpp);
5ca0c34a 6546 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6547
6548 return intel_framebuffer_create(dev, &mode_cmd, obj);
6549}
6550
6551static struct drm_framebuffer *
6552mode_fits_in_fbdev(struct drm_device *dev,
6553 struct drm_display_mode *mode)
6554{
6555 struct drm_i915_private *dev_priv = dev->dev_private;
6556 struct drm_i915_gem_object *obj;
6557 struct drm_framebuffer *fb;
6558
6559 if (dev_priv->fbdev == NULL)
6560 return NULL;
6561
6562 obj = dev_priv->fbdev->ifb.obj;
6563 if (obj == NULL)
6564 return NULL;
6565
6566 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6567 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6568 fb->bits_per_pixel))
d2dff872
CW		 6569 return NULL;
6570
01f2c773 6571 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6572 return NULL;
6573
6574 return fb;
6575}
6576
d2434ab7 6577bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6578 struct drm_display_mode *mode,
8261b191 6579 struct intel_load_detect_pipe *old)
79e53945
JB		 6580{
6581 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6582 struct intel_encoder *intel_encoder =
6583 intel_attached_encoder(connector);
79e53945 6584 struct drm_crtc *possible_crtc;
4ef69c7a 6585 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6586 struct drm_crtc *crtc = NULL;
6587 struct drm_device *dev = encoder->dev;
94352cf9 6588 struct drm_framebuffer *fb;
79e53945
JB		 6589 int i = -1;
6590
d2dff872
CW		 6591 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6592 connector->base.id, drm_get_connector_name(connector),
6593 encoder->base.id, drm_get_encoder_name(encoder));
6594
79e53945
JB		 6595 /*
6596 * Algorithm gets a little messy:
7a5e4805 6597 *
79e53945
JB		 6598 * - if the connector already has an assigned crtc, use it (but make
6599 * sure it's on first)
7a5e4805 6600 *
79e53945
JB		 6601 * - try to find the first unused crtc that can drive this connector,
6602 * and use that if we find one
79e53945
JB		 6603 */
6604
6605 /* See if we already have a CRTC for this connector */
6606 if (encoder->crtc) {
6607 crtc = encoder->crtc;
8261b191 6608
7b24056b
DV		 6609 mutex_lock(&crtc->mutex);
6610
24218aac 6611 old->dpms_mode = connector->dpms;
8261b191
CW		 6612 old->load_detect_temp = false;
6613
6614 /* Make sure the crtc and connector are running */
24218aac
DV		 6615 if (connector->dpms != DRM_MODE_DPMS_ON)
6616 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6617
7173188d 6618 return true;
79e53945
JB		 6619 }
6620
6621 /* Find an unused one (if possible) */
6622 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6623 i++;
6624 if (!(encoder->possible_crtcs & (1 << i)))
6625 continue;
6626 if (!possible_crtc->enabled) {
6627 crtc = possible_crtc;
6628 break;
6629 }
79e53945
JB		 6630 }
6631
6632 /*
6633 * If we didn't find an unused CRTC, don't use any.
6634 */
6635 if (!crtc) {
7173188d
CW		 6636 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6637 return false;
79e53945
JB		 6638 }
6639
7b24056b 6640 mutex_lock(&crtc->mutex);
fc303101
DV		 6641 intel_encoder->new_crtc = to_intel_crtc(crtc);
6642 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6643
6644 intel_crtc = to_intel_crtc(crtc);
24218aac 6645 old->dpms_mode = connector->dpms;
8261b191 6646 old->load_detect_temp = true;
d2dff872 6647 old->release_fb = NULL;
79e53945 6648
6492711d
CW		 6649 if (!mode)
6650 mode = &load_detect_mode;
79e53945 6651
d2dff872
CW		 6652 /* We need a framebuffer large enough to accommodate all accesses
6653 * that the plane may generate whilst we perform load detection.
6654 * We can not rely on the fbcon either being present (we get called
6655 * during its initialisation to detect all boot displays, or it may
6656 * not even exist) or that it is large enough to satisfy the
6657 * requested mode.
6658 */
94352cf9
DV		 6659 fb = mode_fits_in_fbdev(dev, mode);
6660 if (fb == NULL) {
d2dff872 6661 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6662 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6663 old->release_fb = fb;
d2dff872
CW		 6664 } else
6665 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6666 if (IS_ERR(fb)) {
d2dff872 6667 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6668 mutex_unlock(&crtc->mutex);
0e8b3d3e 6669 return false;
79e53945 6670 }
79e53945 6671
c0c36b94 6672 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6673 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6674 if (old->release_fb)
6675 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6676 mutex_unlock(&crtc->mutex);
0e8b3d3e 6677 return false;
79e53945 6678 }
7173188d 6679
79e53945 6680 /* let the connector get through one full cycle before testing */
9d0498a2 6681 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6682 return true;
79e53945
JB		 6683}
6684
d2434ab7 6685void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6686 struct intel_load_detect_pipe *old)
79e53945 6687{
d2434ab7
DV		 6688 struct intel_encoder *intel_encoder =
6689 intel_attached_encoder(connector);
4ef69c7a 6690 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6691 struct drm_crtc *crtc = encoder->crtc;
79e53945 6692
d2dff872
CW		 6693 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6694 connector->base.id, drm_get_connector_name(connector),
6695 encoder->base.id, drm_get_encoder_name(encoder));
6696
8261b191 6697 if (old->load_detect_temp) {
fc303101
DV		 6698 to_intel_connector(connector)->new_encoder = NULL;
6699 intel_encoder->new_crtc = NULL;
6700 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6701
36206361
DV		 6702 if (old->release_fb) {
6703 drm_framebuffer_unregister_private(old->release_fb);
6704 drm_framebuffer_unreference(old->release_fb);
6705 }
d2dff872 6706
67c96400 6707 mutex_unlock(&crtc->mutex);
0622a53c 6708 return;
79e53945
JB		 6709 }
6710
c751ce4f 6711 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6712 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6713 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6714
6715 mutex_unlock(&crtc->mutex);
79e53945
JB		 6716}
6717
6718/* Returns the clock of the currently programmed mode of the given pipe. */
6719static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6720{
6721 struct drm_i915_private *dev_priv = dev->dev_private;
6722 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6723 int pipe = intel_crtc->pipe;
548f245b 6724 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6725 u32 fp;
6726 intel_clock_t clock;
6727
6728 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6729 fp = I915_READ(FP0(pipe));
79e53945 6730 else
39adb7a5 6731 fp = I915_READ(FP1(pipe));
79e53945
JB		 6732
6733 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6734 if (IS_PINEVIEW(dev)) {
6735 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6736 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6737 } else {
6738 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6739 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6740 }
6741
a6c45cf0 6742 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6743 if (IS_PINEVIEW(dev))
6744 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6745 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6746 else
6747 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6748 DPLL_FPA01_P1_POST_DIV_SHIFT);
6749
6750 switch (dpll & DPLL_MODE_MASK) {
6751 case DPLLB_MODE_DAC_SERIAL:
6752 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6753 5 : 10;
6754 break;
6755 case DPLLB_MODE_LVDS:
6756 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6757 7 : 14;
6758 break;
6759 default:
28c97730 6760 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6761 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6762 return 0;
6763 }
6764
6765 /* XXX: Handle the 100Mhz refclk */
2177832f 6766 intel_clock(dev, 96000, &clock);
79e53945
JB		 6767 } else {
6768 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6769
6770 if (is_lvds) {
6771 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6772 DPLL_FPA01_P1_POST_DIV_SHIFT);
6773 clock.p2 = 14;
6774
6775 if ((dpll & PLL_REF_INPUT_MASK) ==
6776 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6777 /* XXX: might not be 66MHz */
2177832f 6778 intel_clock(dev, 66000, &clock);
79e53945 6779 } else
2177832f 6780 intel_clock(dev, 48000, &clock);
79e53945
JB		 6781 } else {
6782 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6783 clock.p1 = 2;
6784 else {
6785 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6786 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6787 }
6788 if (dpll & PLL_P2_DIVIDE_BY_4)
6789 clock.p2 = 4;
6790 else
6791 clock.p2 = 2;
6792
2177832f 6793 intel_clock(dev, 48000, &clock);
79e53945
JB		 6794 }
6795 }
6796
6797 /* XXX: It would be nice to validate the clocks, but we can't reuse
6798 * i830PllIsValid() because it relies on the xf86_config connector
6799 * configuration being accurate, which it isn't necessarily.
6800 */
6801
6802 return clock.dot;
6803}
6804
6805/** Returns the currently programmed mode of the given pipe. */
6806struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6807 struct drm_crtc *crtc)
6808{
548f245b 6809 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6810 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fe2b8f9d 6811 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
79e53945 6812 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6813 int htot = I915_READ(HTOTAL(cpu_transcoder));
6814 int hsync = I915_READ(HSYNC(cpu_transcoder));
6815 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6816 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6817
6818 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6819 if (!mode)
6820 return NULL;
6821
6822 mode->clock = intel_crtc_clock_get(dev, crtc);
6823 mode->hdisplay = (htot & 0xffff) + 1;
6824 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6825 mode->hsync_start = (hsync & 0xffff) + 1;
6826 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6827 mode->vdisplay = (vtot & 0xffff) + 1;
6828 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6829 mode->vsync_start = (vsync & 0xffff) + 1;
6830 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6831
6832 drm_mode_set_name(mode);
79e53945
JB		 6833
6834 return mode;
6835}
6836
3dec0095 6837static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6838{
6839 struct drm_device *dev = crtc->dev;
6840 drm_i915_private_t *dev_priv = dev->dev_private;
6841 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6842 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6843 int dpll_reg = DPLL(pipe);
6844 int dpll;
652c393a 6845
bad720ff 6846 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6847 return;
6848
6849 if (!dev_priv->lvds_downclock_avail)
6850 return;
6851
dbdc6479 6852 dpll = I915_READ(dpll_reg);
652c393a 6853 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6854 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6855
8ac5a6d5 6856 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6857
6858 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6859 I915_WRITE(dpll_reg, dpll);
9d0498a2 6860 intel_wait_for_vblank(dev, pipe);
dbdc6479 6861
652c393a
JB		 6862 dpll = I915_READ(dpll_reg);
6863 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6864 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6865 }
652c393a
JB		 6866}
6867
6868static void intel_decrease_pllclock(struct drm_crtc *crtc)
6869{
6870 struct drm_device *dev = crtc->dev;
6871 drm_i915_private_t *dev_priv = dev->dev_private;
6872 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6873
bad720ff 6874 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6875 return;
6876
6877 if (!dev_priv->lvds_downclock_avail)
6878 return;
6879
6880 /*
6881 * Since this is called by a timer, we should never get here in
6882 * the manual case.
6883 */
6884 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6885 int pipe = intel_crtc->pipe;
6886 int dpll_reg = DPLL(pipe);
6887 int dpll;
f6e5b160 6888
44d98a61 6889 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6890
8ac5a6d5 6891 assert_panel_unlocked(dev_priv, pipe);
652c393a 6892
dc257cf1 6893 dpll = I915_READ(dpll_reg);
652c393a
JB		 6894 dpll |= DISPLAY_RATE_SELECT_FPA1;
6895 I915_WRITE(dpll_reg, dpll);
9d0498a2 6896 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6897 dpll = I915_READ(dpll_reg);
6898 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6899 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6900 }
6901
6902}
6903
f047e395
CW		 6904void intel_mark_busy(struct drm_device *dev)
6905{
f047e395
CW		 6906 i915_update_gfx_val(dev->dev_private);
6907}
6908
6909void intel_mark_idle(struct drm_device *dev)
652c393a 6910{
652c393a 6911 struct drm_crtc *crtc;
652c393a
JB		 6912
6913 if (!i915_powersave)
6914 return;
6915
652c393a 6916 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6917 if (!crtc->fb)
6918 continue;
6919
725a5b54 6920 intel_decrease_pllclock(crtc);
652c393a 6921 }
652c393a
JB		 6922}
6923
725a5b54 6924void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
652c393a 6925{
f047e395
CW		 6926 struct drm_device *dev = obj->base.dev;
6927 struct drm_crtc *crtc;
652c393a 6928
f047e395 6929 if (!i915_powersave)
acb87dfb
CW		 6930 return;
6931
652c393a
JB		 6932 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6933 if (!crtc->fb)
6934 continue;
6935
f047e395 6936 if (to_intel_framebuffer(crtc->fb)->obj == obj)
725a5b54 6937 intel_increase_pllclock(crtc);
652c393a
JB		 6938 }
6939}
6940
79e53945
JB		 6941static void intel_crtc_destroy(struct drm_crtc *crtc)
6942{
6943 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6944 struct drm_device *dev = crtc->dev;
6945 struct intel_unpin_work *work;
6946 unsigned long flags;
6947
6948 spin_lock_irqsave(&dev->event_lock, flags);
6949 work = intel_crtc->unpin_work;
6950 intel_crtc->unpin_work = NULL;
6951 spin_unlock_irqrestore(&dev->event_lock, flags);
6952
6953 if (work) {
6954 cancel_work_sync(&work->work);
6955 kfree(work);
6956 }
79e53945
JB		 6957
6958 drm_crtc_cleanup(crtc);
67e77c5a 6959
79e53945
JB		 6960 kfree(intel_crtc);
6961}
6962
6b95a207
KH		 6963static void intel_unpin_work_fn(struct work_struct *__work)
6964{
6965 struct intel_unpin_work *work =
6966 container_of(__work, struct intel_unpin_work, work);
b4a98e57 6967 struct drm_device *dev = work->crtc->dev;
6b95a207 6968
b4a98e57 6969 mutex_lock(&dev->struct_mutex);
1690e1eb 6970 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 6971 drm_gem_object_unreference(&work->pending_flip_obj->base);
6972 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6973
b4a98e57
CW		 6974 intel_update_fbc(dev);
6975 mutex_unlock(&dev->struct_mutex);
6976
6977 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
6978 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
6979
6b95a207
KH		 6980 kfree(work);
6981}
6982
1afe3e9d 6983static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6984 struct drm_crtc *crtc)
6b95a207
KH		 6985{
6986 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6987 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6988 struct intel_unpin_work *work;
6b95a207
KH		 6989 unsigned long flags;
6990
6991 /* Ignore early vblank irqs */
6992 if (intel_crtc == NULL)
6993 return;
6994
6995 spin_lock_irqsave(&dev->event_lock, flags);
6996 work = intel_crtc->unpin_work;
e7d841ca
CW		 6997
6998 /* Ensure we don't miss a work->pending update ... */
6999 smp_rmb();
7000
7001 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7002 spin_unlock_irqrestore(&dev->event_lock, flags);
7003 return;
7004 }
7005
e7d841ca
CW		 7006 /* and that the unpin work is consistent wrt ->pending. */
7007 smp_rmb();
7008
6b95a207 7009 intel_crtc->unpin_work = NULL;
6b95a207 7010
45a066eb
RC		 7011 if (work->event)
7012 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7013
0af7e4df
MK		 7014 drm_vblank_put(dev, intel_crtc->pipe);
7015
6b95a207
KH		 7016 spin_unlock_irqrestore(&dev->event_lock, flags);
7017
2c10d571 7018 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7019
7020 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7021
7022 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7023}
7024
1afe3e9d
JB		 7025void intel_finish_page_flip(struct drm_device *dev, int pipe)
7026{
7027 drm_i915_private_t *dev_priv = dev->dev_private;
7028 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7029
49b14a5c 7030 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7031}
7032
7033void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7034{
7035 drm_i915_private_t *dev_priv = dev->dev_private;
7036 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7037
49b14a5c 7038 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7039}
7040
6b95a207
KH		 7041void intel_prepare_page_flip(struct drm_device *dev, int plane)
7042{
7043 drm_i915_private_t *dev_priv = dev->dev_private;
7044 struct intel_crtc *intel_crtc =
7045 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7046 unsigned long flags;
7047
e7d841ca
CW		 7048 /* NB: An MMIO update of the plane base pointer will also
7049 * generate a page-flip completion irq, i.e. every modeset
7050 * is also accompanied by a spurious intel_prepare_page_flip().
7051 */
6b95a207 7052 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7053 if (intel_crtc->unpin_work)
7054 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7055 spin_unlock_irqrestore(&dev->event_lock, flags);
7056}
7057
e7d841ca
CW		 7058inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7059{
7060 /* Ensure that the work item is consistent when activating it ... */
7061 smp_wmb();
7062 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7063 /* and that it is marked active as soon as the irq could fire. */
7064 smp_wmb();
7065}
7066
8c9f3aaf
JB		 7067static int intel_gen2_queue_flip(struct drm_device *dev,
7068 struct drm_crtc *crtc,
7069 struct drm_framebuffer *fb,
7070 struct drm_i915_gem_object *obj)
7071{
7072 struct drm_i915_private *dev_priv = dev->dev_private;
7073 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7074 u32 flip_mask;
6d90c952 7075 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7076 int ret;
7077
6d90c952 7078 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7079 if (ret)
83d4092b 7080 goto err;
8c9f3aaf 7081
6d90c952 7082 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7083 if (ret)
83d4092b 7084 goto err_unpin;
8c9f3aaf
JB		 7085
7086 /* Can't queue multiple flips, so wait for the previous
7087 * one to finish before executing the next.
7088 */
7089 if (intel_crtc->plane)
7090 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7091 else
7092 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7093 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7094 intel_ring_emit(ring, MI_NOOP);
7095 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7096 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7097 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7098 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 7099 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7100
7101 intel_mark_page_flip_active(intel_crtc);
6d90c952 7102 intel_ring_advance(ring);
83d4092b
CW		 7103 return 0;
7104
7105err_unpin:
7106 intel_unpin_fb_obj(obj);
7107err:
8c9f3aaf
JB		 7108 return ret;
7109}
7110
7111static int intel_gen3_queue_flip(struct drm_device *dev,
7112 struct drm_crtc *crtc,
7113 struct drm_framebuffer *fb,
7114 struct drm_i915_gem_object *obj)
7115{
7116 struct drm_i915_private *dev_priv = dev->dev_private;
7117 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7118 u32 flip_mask;
6d90c952 7119 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7120 int ret;
7121
6d90c952 7122 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7123 if (ret)
83d4092b 7124 goto err;
8c9f3aaf 7125
6d90c952 7126 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7127 if (ret)
83d4092b 7128 goto err_unpin;
8c9f3aaf
JB		 7129
7130 if (intel_crtc->plane)
7131 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7132 else
7133 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7134 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7135 intel_ring_emit(ring, MI_NOOP);
7136 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7137 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7138 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7139 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7140 intel_ring_emit(ring, MI_NOOP);
7141
e7d841ca 7142 intel_mark_page_flip_active(intel_crtc);
6d90c952 7143 intel_ring_advance(ring);
83d4092b
CW		 7144 return 0;
7145
7146err_unpin:
7147 intel_unpin_fb_obj(obj);
7148err:
8c9f3aaf
JB		 7149 return ret;
7150}
7151
7152static int intel_gen4_queue_flip(struct drm_device *dev,
7153 struct drm_crtc *crtc,
7154 struct drm_framebuffer *fb,
7155 struct drm_i915_gem_object *obj)
7156{
7157 struct drm_i915_private *dev_priv = dev->dev_private;
7158 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7159 uint32_t pf, pipesrc;
6d90c952 7160 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7161 int ret;
7162
6d90c952 7163 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7164 if (ret)
83d4092b 7165 goto err;
8c9f3aaf 7166
6d90c952 7167 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7168 if (ret)
83d4092b 7169 goto err_unpin;
8c9f3aaf
JB		 7170
7171 /* i965+ uses the linear or tiled offsets from the
7172 * Display Registers (which do not change across a page-flip)
7173 * so we need only reprogram the base address.
7174 */
6d90c952
DV		 7175 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7176 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7177 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7178 intel_ring_emit(ring,
7179 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7180 obj->tiling_mode);
8c9f3aaf
JB		 7181
7182 /* XXX Enabling the panel-fitter across page-flip is so far
7183 * untested on non-native modes, so ignore it for now.
7184 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7185 */
7186 pf = 0;
7187 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7188 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7189
7190 intel_mark_page_flip_active(intel_crtc);
6d90c952 7191 intel_ring_advance(ring);
83d4092b
CW		 7192 return 0;
7193
7194err_unpin:
7195 intel_unpin_fb_obj(obj);
7196err:
8c9f3aaf
JB		 7197 return ret;
7198}
7199
7200static int intel_gen6_queue_flip(struct drm_device *dev,
7201 struct drm_crtc *crtc,
7202 struct drm_framebuffer *fb,
7203 struct drm_i915_gem_object *obj)
7204{
7205 struct drm_i915_private *dev_priv = dev->dev_private;
7206 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7207 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7208 uint32_t pf, pipesrc;
7209 int ret;
7210
6d90c952 7211 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7212 if (ret)
83d4092b 7213 goto err;
8c9f3aaf 7214
6d90c952 7215 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7216 if (ret)
83d4092b 7217 goto err_unpin;
8c9f3aaf 7218
6d90c952
DV		 7219 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7220 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7221 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7222 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7223
dc257cf1
DV		 7224 /* Contrary to the suggestions in the documentation,
7225 * "Enable Panel Fitter" does not seem to be required when page
7226 * flipping with a non-native mode, and worse causes a normal
7227 * modeset to fail.
7228 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7229 */
7230 pf = 0;
8c9f3aaf 7231 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7232 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7233
7234 intel_mark_page_flip_active(intel_crtc);
6d90c952 7235 intel_ring_advance(ring);
83d4092b
CW		 7236 return 0;
7237
7238err_unpin:
7239 intel_unpin_fb_obj(obj);
7240err:
8c9f3aaf
JB		 7241 return ret;
7242}
7243
7c9017e5
JB		 7244/*
7245 * On gen7 we currently use the blit ring because (in early silicon at least)
7246 * the render ring doesn't give us interrpts for page flip completion, which
7247 * means clients will hang after the first flip is queued. Fortunately the
7248 * blit ring generates interrupts properly, so use it instead.
7249 */
7250static int intel_gen7_queue_flip(struct drm_device *dev,
7251 struct drm_crtc *crtc,
7252 struct drm_framebuffer *fb,
7253 struct drm_i915_gem_object *obj)
7254{
7255 struct drm_i915_private *dev_priv = dev->dev_private;
7256 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7257 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7258 uint32_t plane_bit = 0;
7c9017e5
JB		 7259 int ret;
7260
7261 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7262 if (ret)
83d4092b 7263 goto err;
7c9017e5 7264
cb05d8de
DV		 7265 switch(intel_crtc->plane) {
7266 case PLANE_A:
7267 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7268 break;
7269 case PLANE_B:
7270 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7271 break;
7272 case PLANE_C:
7273 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7274 break;
7275 default:
7276 WARN_ONCE(1, "unknown plane in flip command\n");
7277 ret = -ENODEV;
ab3951eb 7278 goto err_unpin;
cb05d8de
DV		 7279 }
7280
7c9017e5
JB		 7281 ret = intel_ring_begin(ring, 4);
7282 if (ret)
83d4092b 7283 goto err_unpin;
7c9017e5 7284
cb05d8de 7285 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7286 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7287 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7288 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7289
7290 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7291 intel_ring_advance(ring);
83d4092b
CW		 7292 return 0;
7293
7294err_unpin:
7295 intel_unpin_fb_obj(obj);
7296err:
7c9017e5
JB		 7297 return ret;
7298}
7299
8c9f3aaf
JB		 7300static int intel_default_queue_flip(struct drm_device *dev,
7301 struct drm_crtc *crtc,
7302 struct drm_framebuffer *fb,
7303 struct drm_i915_gem_object *obj)
7304{
7305 return -ENODEV;
7306}
7307
6b95a207
KH		 7308static int intel_crtc_page_flip(struct drm_crtc *crtc,
7309 struct drm_framebuffer *fb,
7310 struct drm_pending_vblank_event *event)
7311{
7312 struct drm_device *dev = crtc->dev;
7313 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7314 struct drm_framebuffer *old_fb = crtc->fb;
7315 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7316 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7317 struct intel_unpin_work *work;
8c9f3aaf 7318 unsigned long flags;
52e68630 7319 int ret;
6b95a207 7320
e6a595d2
VS		 7321 /* Can't change pixel format via MI display flips. */
7322 if (fb->pixel_format != crtc->fb->pixel_format)
7323 return -EINVAL;
7324
7325 /*
7326 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7327 * Note that pitch changes could also affect these register.
7328 */
7329 if (INTEL_INFO(dev)->gen > 3 &&
7330 (fb->offsets[0] != crtc->fb->offsets[0] ||
7331 fb->pitches[0] != crtc->fb->pitches[0]))
7332 return -EINVAL;
7333
6b95a207
KH		 7334 work = kzalloc(sizeof *work, GFP_KERNEL);
7335 if (work == NULL)
7336 return -ENOMEM;
7337
6b95a207 7338 work->event = event;
b4a98e57 7339 work->crtc = crtc;
4a35f83b 7340 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7341 INIT_WORK(&work->work, intel_unpin_work_fn);
7342
7317c75e
JB		 7343 ret = drm_vblank_get(dev, intel_crtc->pipe);
7344 if (ret)
7345 goto free_work;
7346
6b95a207
KH		 7347 /* We borrow the event spin lock for protecting unpin_work */
7348 spin_lock_irqsave(&dev->event_lock, flags);
7349 if (intel_crtc->unpin_work) {
7350 spin_unlock_irqrestore(&dev->event_lock, flags);
7351 kfree(work);
7317c75e 7352 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7353
7354 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7355 return -EBUSY;
7356 }
7357 intel_crtc->unpin_work = work;
7358 spin_unlock_irqrestore(&dev->event_lock, flags);
7359
b4a98e57
CW		 7360 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7361 flush_workqueue(dev_priv->wq);
7362
79158103
CW		 7363 ret = i915_mutex_lock_interruptible(dev);
7364 if (ret)
7365 goto cleanup;
6b95a207 7366
75dfca80 7367 /* Reference the objects for the scheduled work. */
05394f39
CW		 7368 drm_gem_object_reference(&work->old_fb_obj->base);
7369 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7370
7371 crtc->fb = fb;
96b099fd 7372
e1f99ce6 7373 work->pending_flip_obj = obj;
e1f99ce6 7374
4e5359cd
SF		 7375 work->enable_stall_check = true;
7376
b4a98e57 7377 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7378 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7379
8c9f3aaf
JB		 7380 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7381 if (ret)
7382 goto cleanup_pending;
6b95a207 7383
7782de3b 7384 intel_disable_fbc(dev);
f047e395 7385 intel_mark_fb_busy(obj);
6b95a207
KH		 7386 mutex_unlock(&dev->struct_mutex);
7387
e5510fac
JB		 7388 trace_i915_flip_request(intel_crtc->plane, obj);
7389
6b95a207 7390 return 0;
96b099fd 7391
8c9f3aaf 7392cleanup_pending:
b4a98e57 7393 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7394 crtc->fb = old_fb;
05394f39
CW		 7395 drm_gem_object_unreference(&work->old_fb_obj->base);
7396 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7397 mutex_unlock(&dev->struct_mutex);
7398
79158103 7399cleanup:
96b099fd
CW		 7400 spin_lock_irqsave(&dev->event_lock, flags);
7401 intel_crtc->unpin_work = NULL;
7402 spin_unlock_irqrestore(&dev->event_lock, flags);
7403
7317c75e
JB		 7404 drm_vblank_put(dev, intel_crtc->pipe);
7405free_work:
96b099fd
CW		 7406 kfree(work);
7407
7408 return ret;
6b95a207
KH		 7409}
7410
f6e5b160 7411static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7412 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7413 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7414};
7415
6ed0f796 7416bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7417{
6ed0f796
DV		 7418 struct intel_encoder *other_encoder;
7419 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7420
6ed0f796
DV		 7421 if (WARN_ON(!crtc))
7422 return false;
7423
7424 list_for_each_entry(other_encoder,
7425 &crtc->dev->mode_config.encoder_list,
7426 base.head) {
7427
7428 if (&other_encoder->new_crtc->base != crtc ||
7429 encoder == other_encoder)
7430 continue;
7431 else
7432 return true;
f47166d2
CW		 7433 }
7434
6ed0f796
DV		 7435 return false;
7436}
47f1c6c9 7437
50f56119
DV		 7438static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7439 struct drm_crtc *crtc)
7440{
7441 struct drm_device *dev;
7442 struct drm_crtc *tmp;
7443 int crtc_mask = 1;
47f1c6c9 7444
50f56119 7445 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7446
50f56119 7447 dev = crtc->dev;
47f1c6c9 7448
50f56119
DV		 7449 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7450 if (tmp == crtc)
7451 break;
7452 crtc_mask <<= 1;
7453 }
47f1c6c9 7454
50f56119
DV		 7455 if (encoder->possible_crtcs & crtc_mask)
7456 return true;
7457 return false;
47f1c6c9 7458}
79e53945 7459
9a935856
DV		 7460/**
7461 * intel_modeset_update_staged_output_state
7462 *
7463 * Updates the staged output configuration state, e.g. after we've read out the
7464 * current hw state.
7465 */
7466static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7467{
9a935856
DV		 7468 struct intel_encoder *encoder;
7469 struct intel_connector *connector;
f6e5b160 7470
9a935856
DV		 7471 list_for_each_entry(connector, &dev->mode_config.connector_list,
7472 base.head) {
7473 connector->new_encoder =
7474 to_intel_encoder(connector->base.encoder);
7475 }
f6e5b160 7476
9a935856
DV		 7477 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7478 base.head) {
7479 encoder->new_crtc =
7480 to_intel_crtc(encoder->base.crtc);
7481 }
f6e5b160
CW		 7482}
7483
9a935856
DV		 7484/**
7485 * intel_modeset_commit_output_state
7486 *
7487 * This function copies the stage display pipe configuration to the real one.
7488 */
7489static void intel_modeset_commit_output_state(struct drm_device *dev)
7490{
7491 struct intel_encoder *encoder;
7492 struct intel_connector *connector;
f6e5b160 7493
9a935856
DV		 7494 list_for_each_entry(connector, &dev->mode_config.connector_list,
7495 base.head) {
7496 connector->base.encoder = &connector->new_encoder->base;
7497 }
f6e5b160 7498
9a935856
DV		 7499 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7500 base.head) {
7501 encoder->base.crtc = &encoder->new_crtc->base;
7502 }
7503}
7504
7758a113
DV		 7505static struct drm_display_mode *
7506intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7507 struct drm_display_mode *mode)
ee7b9f93 7508{
7758a113
DV		 7509 struct drm_device *dev = crtc->dev;
7510 struct drm_display_mode *adjusted_mode;
7511 struct drm_encoder_helper_funcs *encoder_funcs;
7512 struct intel_encoder *encoder;
ee7b9f93 7513
7758a113
DV		 7514 adjusted_mode = drm_mode_duplicate(dev, mode);
7515 if (!adjusted_mode)
7516 return ERR_PTR(-ENOMEM);
7517
7518 /* Pass our mode to the connectors and the CRTC to give them a chance to
7519 * adjust it according to limitations or connector properties, and also
7520 * a chance to reject the mode entirely.
47f1c6c9 7521 */
7758a113
DV		 7522 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7523 base.head) {
47f1c6c9 7524
7758a113
DV		 7525 if (&encoder->new_crtc->base != crtc)
7526 continue;
7527 encoder_funcs = encoder->base.helper_private;
7528 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7529 adjusted_mode))) {
7530 DRM_DEBUG_KMS("Encoder fixup failed\n");
7531 goto fail;
7532 }
ee7b9f93 7533 }
47f1c6c9 7534
7758a113
DV		 7535 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7536 DRM_DEBUG_KMS("CRTC fixup failed\n");
7537 goto fail;
ee7b9f93 7538 }
7758a113 7539 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
47f1c6c9 7540
7758a113
DV		 7541 return adjusted_mode;
7542fail:
7543 drm_mode_destroy(dev, adjusted_mode);
7544 return ERR_PTR(-EINVAL);
ee7b9f93 7545}
47f1c6c9 7546
e2e1ed41
DV		 7547/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7548 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7549static void
7550intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7551 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7552{
7553 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7554 struct drm_device *dev = crtc->dev;
7555 struct intel_encoder *encoder;
7556 struct intel_connector *connector;
7557 struct drm_crtc *tmp_crtc;
79e53945 7558
e2e1ed41 7559 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7560
e2e1ed41
DV		 7561 /* Check which crtcs have changed outputs connected to them, these need
7562 * to be part of the prepare_pipes mask. We don't (yet) support global
7563 * modeset across multiple crtcs, so modeset_pipes will only have one
7564 * bit set at most. */
7565 list_for_each_entry(connector, &dev->mode_config.connector_list,
7566 base.head) {
7567 if (connector->base.encoder == &connector->new_encoder->base)
7568 continue;
79e53945 7569
e2e1ed41
DV		 7570 if (connector->base.encoder) {
7571 tmp_crtc = connector->base.encoder->crtc;
7572
7573 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7574 }
7575
7576 if (connector->new_encoder)
7577 *prepare_pipes |=
7578 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7579 }
7580
e2e1ed41
DV		 7581 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7582 base.head) {
7583 if (encoder->base.crtc == &encoder->new_crtc->base)
7584 continue;
7585
7586 if (encoder->base.crtc) {
7587 tmp_crtc = encoder->base.crtc;
7588
7589 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7590 }
7591
7592 if (encoder->new_crtc)
7593 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7594 }
7595
e2e1ed41
DV		 7596 /* Check for any pipes that will be fully disabled ... */
7597 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7598 base.head) {
7599 bool used = false;
22fd0fab 7600
e2e1ed41
DV		 7601 /* Don't try to disable disabled crtcs. */
7602 if (!intel_crtc->base.enabled)
7603 continue;
7e7d76c3 7604
e2e1ed41
DV		 7605 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7606 base.head) {
7607 if (encoder->new_crtc == intel_crtc)
7608 used = true;
7609 }
7610
7611 if (!used)
7612 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7613 }
7614
e2e1ed41
DV		 7615
7616 /* set_mode is also used to update properties on life display pipes. */
7617 intel_crtc = to_intel_crtc(crtc);
7618 if (crtc->enabled)
7619 *prepare_pipes |= 1 << intel_crtc->pipe;
7620
7621 /* We only support modeset on one single crtc, hence we need to do that
7622 * only for the passed in crtc iff we change anything else than just
7623 * disable crtcs.
7624 *
7625 * This is actually not true, to be fully compatible with the old crtc
7626 * helper we automatically disable _any_ output (i.e. doesn't need to be
7627 * connected to the crtc we're modesetting on) if it's disconnected.
7628 * Which is a rather nutty api (since changed the output configuration
7629 * without userspace's explicit request can lead to confusion), but
7630 * alas. Hence we currently need to modeset on all pipes we prepare. */
7631 if (*prepare_pipes)
7632 *modeset_pipes = *prepare_pipes;
7633
7634 /* ... and mask these out. */
7635 *modeset_pipes &= ~(*disable_pipes);
7636 *prepare_pipes &= ~(*disable_pipes);
47f1c6c9 7637}
79e53945 7638
ea9d758d 7639static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7640{
ea9d758d 7641 struct drm_encoder *encoder;
f6e5b160 7642 struct drm_device *dev = crtc->dev;
f6e5b160 7643
ea9d758d
DV		 7644 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7645 if (encoder->crtc == crtc)
7646 return true;
7647
7648 return false;
7649}
7650
7651static void
7652intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7653{
7654 struct intel_encoder *intel_encoder;
7655 struct intel_crtc *intel_crtc;
7656 struct drm_connector *connector;
7657
7658 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7659 base.head) {
7660 if (!intel_encoder->base.crtc)
7661 continue;
7662
7663 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7664
7665 if (prepare_pipes & (1 << intel_crtc->pipe))
7666 intel_encoder->connectors_active = false;
7667 }
7668
7669 intel_modeset_commit_output_state(dev);
7670
7671 /* Update computed state. */
7672 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7673 base.head) {
7674 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7675 }
7676
7677 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7678 if (!connector->encoder || !connector->encoder->crtc)
7679 continue;
7680
7681 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7682
7683 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7684 struct drm_property *dpms_property =
7685 dev->mode_config.dpms_property;
7686
ea9d758d 7687 connector->dpms = DRM_MODE_DPMS_ON;
662595df 7688 drm_object_property_set_value(&connector->base,
68d34720
DV		 7689 dpms_property,
7690 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7691
7692 intel_encoder = to_intel_encoder(connector->encoder);
7693 intel_encoder->connectors_active = true;
7694 }
7695 }
7696
7697}
7698
25c5b266
DV		 7699#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7700 list_for_each_entry((intel_crtc), \
7701 &(dev)->mode_config.crtc_list, \
7702 base.head) \
7703 if (mask & (1 <<(intel_crtc)->pipe)) \
7704
b980514c 7705void
8af6cf88
DV		 7706intel_modeset_check_state(struct drm_device *dev)
7707{
7708 struct intel_crtc *crtc;
7709 struct intel_encoder *encoder;
7710 struct intel_connector *connector;
7711
7712 list_for_each_entry(connector, &dev->mode_config.connector_list,
7713 base.head) {
7714 /* This also checks the encoder/connector hw state with the
7715 * ->get_hw_state callbacks. */
7716 intel_connector_check_state(connector);
7717
7718 WARN(&connector->new_encoder->base != connector->base.encoder,
7719 "connector's staged encoder doesn't match current encoder\n");
7720 }
7721
7722 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7723 base.head) {
7724 bool enabled = false;
7725 bool active = false;
7726 enum pipe pipe, tracked_pipe;
7727
7728 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7729 encoder->base.base.id,
7730 drm_get_encoder_name(&encoder->base));
7731
7732 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7733 "encoder's stage crtc doesn't match current crtc\n");
7734 WARN(encoder->connectors_active && !encoder->base.crtc,
7735 "encoder's active_connectors set, but no crtc\n");
7736
7737 list_for_each_entry(connector, &dev->mode_config.connector_list,
7738 base.head) {
7739 if (connector->base.encoder != &encoder->base)
7740 continue;
7741 enabled = true;
7742 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7743 active = true;
7744 }
7745 WARN(!!encoder->base.crtc != enabled,
7746 "encoder's enabled state mismatch "
7747 "(expected %i, found %i)\n",
7748 !!encoder->base.crtc, enabled);
7749 WARN(active && !encoder->base.crtc,
7750 "active encoder with no crtc\n");
7751
7752 WARN(encoder->connectors_active != active,
7753 "encoder's computed active state doesn't match tracked active state "
7754 "(expected %i, found %i)\n", active, encoder->connectors_active);
7755
7756 active = encoder->get_hw_state(encoder, &pipe);
7757 WARN(active != encoder->connectors_active,
7758 "encoder's hw state doesn't match sw tracking "
7759 "(expected %i, found %i)\n",
7760 encoder->connectors_active, active);
7761
7762 if (!encoder->base.crtc)
7763 continue;
7764
7765 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7766 WARN(active && pipe != tracked_pipe,
7767 "active encoder's pipe doesn't match"
7768 "(expected %i, found %i)\n",
7769 tracked_pipe, pipe);
7770
7771 }
7772
7773 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7774 base.head) {
7775 bool enabled = false;
7776 bool active = false;
7777
7778 DRM_DEBUG_KMS("[CRTC:%d]\n",
7779 crtc->base.base.id);
7780
7781 WARN(crtc->active && !crtc->base.enabled,
7782 "active crtc, but not enabled in sw tracking\n");
7783
7784 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7785 base.head) {
7786 if (encoder->base.crtc != &crtc->base)
7787 continue;
7788 enabled = true;
7789 if (encoder->connectors_active)
7790 active = true;
7791 }
7792 WARN(active != crtc->active,
7793 "crtc's computed active state doesn't match tracked active state "
7794 "(expected %i, found %i)\n", active, crtc->active);
7795 WARN(enabled != crtc->base.enabled,
7796 "crtc's computed enabled state doesn't match tracked enabled state "
7797 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7798
7799 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7800 }
7801}
7802
c0c36b94
CW		 7803int intel_set_mode(struct drm_crtc *crtc,
7804 struct drm_display_mode *mode,
7805 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 7806{
7807 struct drm_device *dev = crtc->dev;
dbf2b54e 7808 drm_i915_private_t *dev_priv = dev->dev_private;
3ac18232 7809 struct drm_display_mode *adjusted_mode, *saved_mode, *saved_hwmode;
25c5b266
DV		 7810 struct intel_crtc *intel_crtc;
7811 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 7812 int ret = 0;
a6778b3c 7813
3ac18232 7814 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 7815 if (!saved_mode)
7816 return -ENOMEM;
3ac18232 7817 saved_hwmode = saved_mode + 1;
a6778b3c 7818
e2e1ed41 7819 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 7820 &prepare_pipes, &disable_pipes);
7821
7822 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7823 modeset_pipes, prepare_pipes, disable_pipes);
e2e1ed41 7824
976f8a20
DV		 7825 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7826 intel_crtc_disable(&intel_crtc->base);
87f1faa6 7827
3ac18232
TG		 7828 *saved_hwmode = crtc->hwmode;
7829 *saved_mode = crtc->mode;
a6778b3c 7830
25c5b266
DV		 7831 /* Hack: Because we don't (yet) support global modeset on multiple
7832 * crtcs, we don't keep track of the new mode for more than one crtc.
7833 * Hence simply check whether any bit is set in modeset_pipes in all the
7834 * pieces of code that are not yet converted to deal with mutliple crtcs
7835 * changing their mode at the same time. */
7836 adjusted_mode = NULL;
7837 if (modeset_pipes) {
7838 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7839 if (IS_ERR(adjusted_mode)) {
c0c36b94 7840 ret = PTR_ERR(adjusted_mode);
3ac18232 7841 goto out;
25c5b266 7842 }
25c5b266 7843 }
a6778b3c 7844
ea9d758d
DV		 7845 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7846 if (intel_crtc->base.enabled)
7847 dev_priv->display.crtc_disable(&intel_crtc->base);
7848 }
a6778b3c 7849
6c4c86f5
DV		 7850 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7851 * to set it here already despite that we pass it down the callchain.
f6e5b160 7852 */
6c4c86f5 7853 if (modeset_pipes)
25c5b266 7854 crtc->mode = *mode;
7758a113 7855
ea9d758d
DV		 7856 /* Only after disabling all output pipelines that will be changed can we
7857 * update the the output configuration. */
7858 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 7859
47fab737
DV		 7860 if (dev_priv->display.modeset_global_resources)
7861 dev_priv->display.modeset_global_resources(dev);
7862
a6778b3c
DV		 7863 /* Set up the DPLL and any encoders state that needs to adjust or depend
7864 * on the DPLL.
f6e5b160 7865 */
25c5b266 7866 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94
CW		 7867 ret = intel_crtc_mode_set(&intel_crtc->base,
7868 mode, adjusted_mode,
7869 x, y, fb);
7870 if (ret)
7871 goto done;
a6778b3c
DV		 7872 }
7873
7874 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 7875 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7876 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 7877
25c5b266
DV		 7878 if (modeset_pipes) {
7879 /* Store real post-adjustment hardware mode. */
7880 crtc->hwmode = *adjusted_mode;
a6778b3c 7881
25c5b266
DV		 7882 /* Calculate and store various constants which
7883 * are later needed by vblank and swap-completion
7884 * timestamping. They are derived from true hwmode.
7885 */
7886 drm_calc_timestamping_constants(crtc);
7887 }
a6778b3c
DV		 7888
7889 /* FIXME: add subpixel order */
7890done:
7891 drm_mode_destroy(dev, adjusted_mode);
c0c36b94 7892 if (ret && crtc->enabled) {
3ac18232
TG		 7893 crtc->hwmode = *saved_hwmode;
7894 crtc->mode = *saved_mode;
8af6cf88
DV		 7895 } else {
7896 intel_modeset_check_state(dev);
a6778b3c
DV		 7897 }
7898
3ac18232
TG		 7899out:
7900 kfree(saved_mode);
a6778b3c 7901 return ret;
f6e5b160
CW		 7902}
7903
c0c36b94
CW		 7904void intel_crtc_restore_mode(struct drm_crtc *crtc)
7905{
7906 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
7907}
7908
25c5b266
DV		 7909#undef for_each_intel_crtc_masked
7910
d9e55608
DV		 7911static void intel_set_config_free(struct intel_set_config *config)
7912{
7913 if (!config)
7914 return;
7915
1aa4b628
DV		 7916 kfree(config->save_connector_encoders);
7917 kfree(config->save_encoder_crtcs);
d9e55608
DV		 7918 kfree(config);
7919}
7920
85f9eb71
DV		 7921static int intel_set_config_save_state(struct drm_device *dev,
7922 struct intel_set_config *config)
7923{
85f9eb71
DV		 7924 struct drm_encoder *encoder;
7925 struct drm_connector *connector;
7926 int count;
7927
1aa4b628
DV		 7928 config->save_encoder_crtcs =
7929 kcalloc(dev->mode_config.num_encoder,
7930 sizeof(struct drm_crtc *), GFP_KERNEL);
7931 if (!config->save_encoder_crtcs)
85f9eb71
DV		 7932 return -ENOMEM;
7933
1aa4b628
DV		 7934 config->save_connector_encoders =
7935 kcalloc(dev->mode_config.num_connector,
7936 sizeof(struct drm_encoder *), GFP_KERNEL);
7937 if (!config->save_connector_encoders)
85f9eb71
DV		 7938 return -ENOMEM;
7939
7940 /* Copy data. Note that driver private data is not affected.
7941 * Should anything bad happen only the expected state is
7942 * restored, not the drivers personal bookkeeping.
7943 */
85f9eb71
DV		 7944 count = 0;
7945 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 7946 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 7947 }
7948
7949 count = 0;
7950 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 7951 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 7952 }
7953
7954 return 0;
7955}
7956
7957static void intel_set_config_restore_state(struct drm_device *dev,
7958 struct intel_set_config *config)
7959{
9a935856
DV		 7960 struct intel_encoder *encoder;
7961 struct intel_connector *connector;
85f9eb71
DV		 7962 int count;
7963
85f9eb71 7964 count = 0;
9a935856
DV		 7965 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7966 encoder->new_crtc =
7967 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 7968 }
7969
7970 count = 0;
9a935856
DV		 7971 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7972 connector->new_encoder =
7973 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 7974 }
7975}
7976
5e2b584e
DV		 7977static void
7978intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7979 struct intel_set_config *config)
7980{
7981
7982 /* We should be able to check here if the fb has the same properties
7983 * and then just flip_or_move it */
7984 if (set->crtc->fb != set->fb) {
7985 /* If we have no fb then treat it as a full mode set */
7986 if (set->crtc->fb == NULL) {
7987 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7988 config->mode_changed = true;
7989 } else if (set->fb == NULL) {
7990 config->mode_changed = true;
7991 } else if (set->fb->depth != set->crtc->fb->depth) {
7992 config->mode_changed = true;
7993 } else if (set->fb->bits_per_pixel !=
7994 set->crtc->fb->bits_per_pixel) {
7995 config->mode_changed = true;
7996 } else
7997 config->fb_changed = true;
7998 }
7999
835c5873 8000 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 8001 config->fb_changed = true;
8002
8003 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8004 DRM_DEBUG_KMS("modes are different, full mode set\n");
8005 drm_mode_debug_printmodeline(&set->crtc->mode);
8006 drm_mode_debug_printmodeline(set->mode);
8007 config->mode_changed = true;
8008 }
8009}
8010
2e431051 8011static int
9a935856
DV		 8012intel_modeset_stage_output_state(struct drm_device *dev,
8013 struct drm_mode_set *set,
8014 struct intel_set_config *config)
50f56119 8015{
85f9eb71 8016 struct drm_crtc *new_crtc;
9a935856
DV		 8017 struct intel_connector *connector;
8018 struct intel_encoder *encoder;
2e431051 8019 int count, ro;
50f56119 8020
9abdda74 8021 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 8022 * of connectors. For paranoia, double-check this. */
8023 WARN_ON(!set->fb && (set->num_connectors != 0));
8024 WARN_ON(set->fb && (set->num_connectors == 0));
8025
50f56119 8026 count = 0;
9a935856
DV		 8027 list_for_each_entry(connector, &dev->mode_config.connector_list,
8028 base.head) {
8029 /* Otherwise traverse passed in connector list and get encoders
8030 * for them. */
50f56119 8031 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 8032 if (set->connectors[ro] == &connector->base) {
8033 connector->new_encoder = connector->encoder;
50f56119
DV		 8034 break;
8035 }
8036 }
8037
9a935856
DV		 8038 /* If we disable the crtc, disable all its connectors. Also, if
8039 * the connector is on the changing crtc but not on the new
8040 * connector list, disable it. */
8041 if ((!set->fb || ro == set->num_connectors) &&
8042 connector->base.encoder &&
8043 connector->base.encoder->crtc == set->crtc) {
8044 connector->new_encoder = NULL;
8045
8046 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8047 connector->base.base.id,
8048 drm_get_connector_name(&connector->base));
8049 }
8050
8051
8052 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8053 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8054 config->mode_changed = true;
50f56119
DV		 8055 }
8056 }
9a935856 8057 /* connector->new_encoder is now updated for all connectors. */
50f56119 8058
9a935856 8059 /* Update crtc of enabled connectors. */
50f56119 8060 count = 0;
9a935856
DV		 8061 list_for_each_entry(connector, &dev->mode_config.connector_list,
8062 base.head) {
8063 if (!connector->new_encoder)
50f56119
DV		 8064 continue;
8065
9a935856 8066 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8067
8068 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8069 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8070 new_crtc = set->crtc;
8071 }
8072
8073 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8074 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8075 new_crtc)) {
5e2b584e 8076 return -EINVAL;
50f56119 8077 }
9a935856
DV		 8078 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8079
8080 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8081 connector->base.base.id,
8082 drm_get_connector_name(&connector->base),
8083 new_crtc->base.id);
8084 }
8085
8086 /* Check for any encoders that needs to be disabled. */
8087 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8088 base.head) {
8089 list_for_each_entry(connector,
8090 &dev->mode_config.connector_list,
8091 base.head) {
8092 if (connector->new_encoder == encoder) {
8093 WARN_ON(!connector->new_encoder->new_crtc);
8094
8095 goto next_encoder;
8096 }
8097 }
8098 encoder->new_crtc = NULL;
8099next_encoder:
8100 /* Only now check for crtc changes so we don't miss encoders
8101 * that will be disabled. */
8102 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8103 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8104 config->mode_changed = true;
50f56119
DV		 8105 }
8106 }
9a935856 8107 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8108
2e431051
DV		 8109 return 0;
8110}
8111
8112static int intel_crtc_set_config(struct drm_mode_set *set)
8113{
8114 struct drm_device *dev;
2e431051
DV		 8115 struct drm_mode_set save_set;
8116 struct intel_set_config *config;
8117 int ret;
2e431051 8118
8d3e375e
DV		 8119 BUG_ON(!set);
8120 BUG_ON(!set->crtc);
8121 BUG_ON(!set->crtc->helper_private);
2e431051 8122
7e53f3a4
DV		 8123 /* Enforce sane interface api - has been abused by the fb helper. */
8124 BUG_ON(!set->mode && set->fb);
8125 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 8126
2e431051
DV		 8127 if (set->fb) {
8128 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8129 set->crtc->base.id, set->fb->base.id,
8130 (int)set->num_connectors, set->x, set->y);
8131 } else {
8132 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8133 }
8134
8135 dev = set->crtc->dev;
8136
8137 ret = -ENOMEM;
8138 config = kzalloc(sizeof(*config), GFP_KERNEL);
8139 if (!config)
8140 goto out_config;
8141
8142 ret = intel_set_config_save_state(dev, config);
8143 if (ret)
8144 goto out_config;
8145
8146 save_set.crtc = set->crtc;
8147 save_set.mode = &set->crtc->mode;
8148 save_set.x = set->crtc->x;
8149 save_set.y = set->crtc->y;
8150 save_set.fb = set->crtc->fb;
8151
8152 /* Compute whether we need a full modeset, only an fb base update or no
8153 * change at all. In the future we might also check whether only the
8154 * mode changed, e.g. for LVDS where we only change the panel fitter in
8155 * such cases. */
8156 intel_set_config_compute_mode_changes(set, config);
8157
9a935856 8158 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8159 if (ret)
8160 goto fail;
8161
5e2b584e 8162 if (config->mode_changed) {
87f1faa6 8163 if (set->mode) {
50f56119
DV		 8164 DRM_DEBUG_KMS("attempting to set mode from"
8165 " userspace\n");
8166 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 8167 }
8168
c0c36b94
CW		 8169 ret = intel_set_mode(set->crtc, set->mode,
8170 set->x, set->y, set->fb);
8171 if (ret) {
8172 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8173 set->crtc->base.id, ret);
87f1faa6
DV		 8174 goto fail;
8175 }
5e2b584e 8176 } else if (config->fb_changed) {
4878cae2
VS		 8177 intel_crtc_wait_for_pending_flips(set->crtc);
8178
4f660f49 8179 ret = intel_pipe_set_base(set->crtc,
94352cf9 8180 set->x, set->y, set->fb);
50f56119
DV		 8181 }
8182
d9e55608
DV		 8183 intel_set_config_free(config);
8184
50f56119
DV		 8185 return 0;
8186
8187fail:
85f9eb71 8188 intel_set_config_restore_state(dev, config);
50f56119
DV		 8189
8190 /* Try to restore the config */
5e2b584e 8191 if (config->mode_changed &&
c0c36b94
CW		 8192 intel_set_mode(save_set.crtc, save_set.mode,
8193 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8194 DRM_ERROR("failed to restore config after modeset failure\n");
8195
d9e55608
DV		 8196out_config:
8197 intel_set_config_free(config);
50f56119
DV		 8198 return ret;
8199}
f6e5b160
CW		 8200
8201static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8202 .cursor_set = intel_crtc_cursor_set,
8203 .cursor_move = intel_crtc_cursor_move,
8204 .gamma_set = intel_crtc_gamma_set,
50f56119 8205 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8206 .destroy = intel_crtc_destroy,
8207 .page_flip = intel_crtc_page_flip,
8208};
8209
79f689aa
PZ		 8210static void intel_cpu_pll_init(struct drm_device *dev)
8211{
affa9354 8212 if (HAS_DDI(dev))
79f689aa
PZ		 8213 intel_ddi_pll_init(dev);
8214}
8215
ee7b9f93
JB		 8216static void intel_pch_pll_init(struct drm_device *dev)
8217{
8218 drm_i915_private_t *dev_priv = dev->dev_private;
8219 int i;
8220
8221 if (dev_priv->num_pch_pll == 0) {
8222 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8223 return;
8224 }
8225
8226 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8227 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8228 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8229 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8230 }
8231}
8232
b358d0a6 8233static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8234{
22fd0fab 8235 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8236 struct intel_crtc *intel_crtc;
8237 int i;
8238
8239 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8240 if (intel_crtc == NULL)
8241 return;
8242
8243 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8244
8245 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8246 for (i = 0; i < 256; i++) {
8247 intel_crtc->lut_r[i] = i;
8248 intel_crtc->lut_g[i] = i;
8249 intel_crtc->lut_b[i] = i;
8250 }
8251
80824003
JB		 8252 /* Swap pipes & planes for FBC on pre-965 */
8253 intel_crtc->pipe = pipe;
8254 intel_crtc->plane = pipe;
a5c961d1 8255 intel_crtc->cpu_transcoder = pipe;
e2e767ab 8256 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8257 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8258 intel_crtc->plane = !pipe;
80824003
JB		 8259 }
8260
22fd0fab
JB		 8261 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8262 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8263 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8264 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8265
5a354204 8266 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3 8267
79e53945 8268 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8269}
8270
08d7b3d1 8271int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8272 struct drm_file *file)
08d7b3d1 8273{
08d7b3d1 8274 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8275 struct drm_mode_object *drmmode_obj;
8276 struct intel_crtc *crtc;
08d7b3d1 8277
1cff8f6b
DV		 8278 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8279 return -ENODEV;
08d7b3d1 8280
c05422d5
DV		 8281 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8282 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8283
c05422d5 8284 if (!drmmode_obj) {
08d7b3d1
CW		 8285 DRM_ERROR("no such CRTC id\n");
8286 return -EINVAL;
8287 }
8288
c05422d5
DV		 8289 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8290 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8291
c05422d5 8292 return 0;
08d7b3d1
CW		 8293}
8294
66a9278e 8295static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8296{
66a9278e
DV		 8297 struct drm_device *dev = encoder->base.dev;
8298 struct intel_encoder *source_encoder;
79e53945 8299 int index_mask = 0;
79e53945
JB		 8300 int entry = 0;
8301
66a9278e
DV		 8302 list_for_each_entry(source_encoder,
8303 &dev->mode_config.encoder_list, base.head) {
8304
8305 if (encoder == source_encoder)
79e53945 8306 index_mask |= (1 << entry);
66a9278e
DV		 8307
8308 /* Intel hw has only one MUX where enocoders could be cloned. */
8309 if (encoder->cloneable && source_encoder->cloneable)
8310 index_mask |= (1 << entry);
8311
79e53945
JB		 8312 entry++;
8313 }
4ef69c7a 8314
79e53945
JB		 8315 return index_mask;
8316}
8317
4d302442
CW		 8318static bool has_edp_a(struct drm_device *dev)
8319{
8320 struct drm_i915_private *dev_priv = dev->dev_private;
8321
8322 if (!IS_MOBILE(dev))
8323 return false;
8324
8325 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8326 return false;
8327
8328 if (IS_GEN5(dev) &&
8329 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8330 return false;
8331
8332 return true;
8333}
8334
79e53945
JB		 8335static void intel_setup_outputs(struct drm_device *dev)
8336{
725e30ad 8337 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8338 struct intel_encoder *encoder;
cb0953d7 8339 bool dpd_is_edp = false;
f3cfcba6 8340 bool has_lvds;
79e53945 8341
f3cfcba6 8342 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8343 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8344 /* disable the panel fitter on everything but LVDS */
8345 I915_WRITE(PFIT_CONTROL, 0);
8346 }
79e53945 8347
affa9354 8348 if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
79935fca 8349 intel_crt_init(dev);
cb0953d7 8350
affa9354 8351 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8352 int found;
8353
8354 /* Haswell uses DDI functions to detect digital outputs */
8355 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8356 /* DDI A only supports eDP */
8357 if (found)
8358 intel_ddi_init(dev, PORT_A);
8359
8360 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8361 * register */
8362 found = I915_READ(SFUSE_STRAP);
8363
8364 if (found & SFUSE_STRAP_DDIB_DETECTED)
8365 intel_ddi_init(dev, PORT_B);
8366 if (found & SFUSE_STRAP_DDIC_DETECTED)
8367 intel_ddi_init(dev, PORT_C);
8368 if (found & SFUSE_STRAP_DDID_DETECTED)
8369 intel_ddi_init(dev, PORT_D);
8370 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8371 int found;
270b3042
DV		 8372 dpd_is_edp = intel_dpd_is_edp(dev);
8373
8374 if (has_edp_a(dev))
8375 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8376
dc0fa718 8377 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 8378 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8379 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8380 if (!found)
e2debe91 8381 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 8382 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8383 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8384 }
8385
dc0fa718 8386 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 8387 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 8388
dc0fa718 8389 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 8390 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 8391
5eb08b69 8392 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8393 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8394
270b3042 8395 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8396 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 8397 } else if (IS_VALLEYVIEW(dev)) {
19c03924 8398 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 8399 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8400 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 8401
dc0fa718 8402 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 8403 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8404 PORT_B);
67cfc203
VS		 8405 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8406 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 8407 }
103a196f 8408 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8409 bool found = false;
7d57382e 8410
e2debe91 8411 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8412 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 8413 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 8414 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8415 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 8416 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 8417 }
27185ae1 8418
b01f2c3a
JB		 8419 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8420 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 8421 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 8422 }
725e30ad 8423 }
13520b05
KH		 8424
8425 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8426
e2debe91 8427 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8428 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 8429 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 8430 }
27185ae1 8431
e2debe91 8432 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 8433
b01f2c3a
JB		 8434 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8435 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 8436 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a
JB		 8437 }
8438 if (SUPPORTS_INTEGRATED_DP(dev)) {
8439 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 8440 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 8441 }
725e30ad 8442 }
27185ae1 8443
b01f2c3a
JB		 8444 if (SUPPORTS_INTEGRATED_DP(dev) &&
8445 (I915_READ(DP_D) & DP_DETECTED)) {
8446 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 8447 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 8448 }
bad720ff 8449 } else if (IS_GEN2(dev))
79e53945
JB		 8450 intel_dvo_init(dev);
8451
103a196f 8452 if (SUPPORTS_TV(dev))
79e53945
JB		 8453 intel_tv_init(dev);
8454
4ef69c7a
CW		 8455 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8456 encoder->base.possible_crtcs = encoder->crtc_mask;
8457 encoder->base.possible_clones =
66a9278e 8458 intel_encoder_clones(encoder);
79e53945 8459 }
47356eb6 8460
dde86e2d 8461 intel_init_pch_refclk(dev);
270b3042
DV		 8462
8463 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8464}
8465
8466static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8467{
8468 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8469
8470 drm_framebuffer_cleanup(fb);
05394f39 8471 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8472
8473 kfree(intel_fb);
8474}
8475
8476static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8477 struct drm_file *file,
79e53945
JB		 8478 unsigned int *handle)
8479{
8480 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8481 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8482
05394f39 8483 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8484}
8485
8486static const struct drm_framebuffer_funcs intel_fb_funcs = {
8487 .destroy = intel_user_framebuffer_destroy,
8488 .create_handle = intel_user_framebuffer_create_handle,
8489};
8490
38651674
DA		 8491int intel_framebuffer_init(struct drm_device *dev,
8492 struct intel_framebuffer *intel_fb,
308e5bcb 8493 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8494 struct drm_i915_gem_object *obj)
79e53945 8495{
79e53945
JB		 8496 int ret;
8497
c16ed4be
CW		 8498 if (obj->tiling_mode == I915_TILING_Y) {
8499 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 8500 return -EINVAL;
c16ed4be 8501 }
57cd6508 8502
c16ed4be
CW		 8503 if (mode_cmd->pitches[0] & 63) {
8504 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8505 mode_cmd->pitches[0]);
57cd6508 8506 return -EINVAL;
c16ed4be 8507 }
57cd6508 8508
5d7bd705 8509 /* FIXME <= Gen4 stride limits are bit unclear */
c16ed4be
CW		 8510 if (mode_cmd->pitches[0] > 32768) {
8511 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8512 mode_cmd->pitches[0]);
5d7bd705 8513 return -EINVAL;
c16ed4be 8514 }
5d7bd705
VS		 8515
8516 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 8517 mode_cmd->pitches[0] != obj->stride) {
8518 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8519 mode_cmd->pitches[0], obj->stride);
5d7bd705 8520 return -EINVAL;
c16ed4be 8521 }
5d7bd705 8522
57779d06 8523 /* Reject formats not supported by any plane early. */
308e5bcb 8524 switch (mode_cmd->pixel_format) {
57779d06 8525 case DRM_FORMAT_C8:
04b3924d
VS		 8526 case DRM_FORMAT_RGB565:
8527 case DRM_FORMAT_XRGB8888:
8528 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8529 break;
8530 case DRM_FORMAT_XRGB1555:
8531 case DRM_FORMAT_ARGB1555:
c16ed4be
CW		 8532 if (INTEL_INFO(dev)->gen > 3) {
8533 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8534 return -EINVAL;
c16ed4be 8535 }
57779d06
VS		 8536 break;
8537 case DRM_FORMAT_XBGR8888:
8538 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8539 case DRM_FORMAT_XRGB2101010:
8540 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8541 case DRM_FORMAT_XBGR2101010:
8542 case DRM_FORMAT_ABGR2101010:
c16ed4be
CW		 8543 if (INTEL_INFO(dev)->gen < 4) {
8544 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8545 return -EINVAL;
c16ed4be 8546 }
b5626747 8547 break;
04b3924d
VS		 8548 case DRM_FORMAT_YUYV:
8549 case DRM_FORMAT_UYVY:
8550 case DRM_FORMAT_YVYU:
8551 case DRM_FORMAT_VYUY:
c16ed4be
CW		 8552 if (INTEL_INFO(dev)->gen < 5) {
8553 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8554 return -EINVAL;
c16ed4be 8555 }
57cd6508
CW		 8556 break;
8557 default:
c16ed4be 8558 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8559 return -EINVAL;
8560 }
8561
90f9a336
VS		 8562 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8563 if (mode_cmd->offsets[0] != 0)
8564 return -EINVAL;
8565
c7d73f6a
DV		 8566 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8567 intel_fb->obj = obj;
8568
79e53945
JB		 8569 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8570 if (ret) {
8571 DRM_ERROR("framebuffer init failed %d\n", ret);
8572 return ret;
8573 }
8574
79e53945
JB		 8575 return 0;
8576}
8577
79e53945
JB		 8578static struct drm_framebuffer *
8579intel_user_framebuffer_create(struct drm_device *dev,
8580 struct drm_file *filp,
308e5bcb 8581 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8582{
05394f39 8583 struct drm_i915_gem_object *obj;
79e53945 8584
308e5bcb
JB		 8585 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8586 mode_cmd->handles[0]));
c8725226 8587 if (&obj->base == NULL)
cce13ff7 8588 return ERR_PTR(-ENOENT);
79e53945 8589
d2dff872 8590 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8591}
8592
79e53945 8593static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8594 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8595 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8596};
8597
e70236a8
JB		 8598/* Set up chip specific display functions */
8599static void intel_init_display(struct drm_device *dev)
8600{
8601 struct drm_i915_private *dev_priv = dev->dev_private;
8602
affa9354 8603 if (HAS_DDI(dev)) {
09b4ddf9 8604 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8605 dev_priv->display.crtc_enable = haswell_crtc_enable;
8606 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 8607 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 8608 dev_priv->display.update_plane = ironlake_update_plane;
8609 } else if (HAS_PCH_SPLIT(dev)) {
f564048e 8610 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 8611 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8612 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8613 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8614 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8615 } else {
f564048e 8616 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 8617 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8618 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8619 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8620 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8621 }
e70236a8 8622
e70236a8 8623 /* Returns the core display clock speed */
25eb05fc
JB		 8624 if (IS_VALLEYVIEW(dev))
8625 dev_priv->display.get_display_clock_speed =
8626 valleyview_get_display_clock_speed;
8627 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8628 dev_priv->display.get_display_clock_speed =
8629 i945_get_display_clock_speed;
8630 else if (IS_I915G(dev))
8631 dev_priv->display.get_display_clock_speed =
8632 i915_get_display_clock_speed;
f2b115e6 8633 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8634 dev_priv->display.get_display_clock_speed =
8635 i9xx_misc_get_display_clock_speed;
8636 else if (IS_I915GM(dev))
8637 dev_priv->display.get_display_clock_speed =
8638 i915gm_get_display_clock_speed;
8639 else if (IS_I865G(dev))
8640 dev_priv->display.get_display_clock_speed =
8641 i865_get_display_clock_speed;
f0f8a9ce 8642 else if (IS_I85X(dev))
e70236a8
JB		 8643 dev_priv->display.get_display_clock_speed =
8644 i855_get_display_clock_speed;
8645 else /* 852, 830 */
8646 dev_priv->display.get_display_clock_speed =
8647 i830_get_display_clock_speed;
8648
7f8a8569 8649 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8650 if (IS_GEN5(dev)) {
674cf967 8651 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8652 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8653 } else if (IS_GEN6(dev)) {
674cf967 8654 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8655 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8656 } else if (IS_IVYBRIDGE(dev)) {
8657 /* FIXME: detect B0+ stepping and use auto training */
8658 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 8659 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 8660 dev_priv->display.modeset_global_resources =
8661 ivb_modeset_global_resources;
c82e4d26
ED		 8662 } else if (IS_HASWELL(dev)) {
8663 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 8664 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 8665 dev_priv->display.modeset_global_resources =
8666 haswell_modeset_global_resources;
a0e63c22 8667 }
6067aaea 8668 } else if (IS_G4X(dev)) {
e0dac65e 8669 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8670 }
8c9f3aaf
JB		 8671
8672 /* Default just returns -ENODEV to indicate unsupported */
8673 dev_priv->display.queue_flip = intel_default_queue_flip;
8674
8675 switch (INTEL_INFO(dev)->gen) {
8676 case 2:
8677 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8678 break;
8679
8680 case 3:
8681 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8682 break;
8683
8684 case 4:
8685 case 5:
8686 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8687 break;
8688
8689 case 6:
8690 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8691 break;
7c9017e5
JB		 8692 case 7:
8693 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8694 break;
8c9f3aaf 8695 }
e70236a8
JB		 8696}
8697
b690e96c
JB		 8698/*
8699 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8700 * resume, or other times. This quirk makes sure that's the case for
8701 * affected systems.
8702 */
0206e353 8703static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8704{
8705 struct drm_i915_private *dev_priv = dev->dev_private;
8706
8707 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 8708 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 8709}
8710
435793df
KP		 8711/*
8712 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8713 */
8714static void quirk_ssc_force_disable(struct drm_device *dev)
8715{
8716 struct drm_i915_private *dev_priv = dev->dev_private;
8717 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 8718 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 8719}
8720
4dca20ef 8721/*
5a15ab5b
CE		 8722 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8723 * brightness value
4dca20ef
CE		 8724 */
8725static void quirk_invert_brightness(struct drm_device *dev)
8726{
8727 struct drm_i915_private *dev_priv = dev->dev_private;
8728 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 8729 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 8730}
8731
b690e96c
JB		 8732struct intel_quirk {
8733 int device;
8734 int subsystem_vendor;
8735 int subsystem_device;
8736 void (*hook)(struct drm_device *dev);
8737};
8738
5f85f176
EE		 8739/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8740struct intel_dmi_quirk {
8741 void (*hook)(struct drm_device *dev);
8742 const struct dmi_system_id (*dmi_id_list)[];
8743};
8744
8745static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8746{
8747 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8748 return 1;
8749}
8750
8751static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8752 {
8753 .dmi_id_list = &(const struct dmi_system_id[]) {
8754 {
8755 .callback = intel_dmi_reverse_brightness,
8756 .ident = "NCR Corporation",
8757 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8758 DMI_MATCH(DMI_PRODUCT_NAME, ""),
8759 },
8760 },
8761 { } /* terminating entry */
8762 },
8763 .hook = quirk_invert_brightness,
8764 },
8765};
8766
c43b5634 8767static struct intel_quirk intel_quirks[] = {
b690e96c 8768 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8769 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 8770
b690e96c
JB		 8771 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8772 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8773
b690e96c
JB		 8774 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8775 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8776
ccd0d36e 8777 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 8778 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 8779 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 8780
8781 /* Lenovo U160 cannot use SSC on LVDS */
8782 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 8783
8784 /* Sony Vaio Y cannot use SSC on LVDS */
8785 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 8786
8787 /* Acer Aspire 5734Z must invert backlight brightness */
8788 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 8789
8790 /* Acer/eMachines G725 */
8791 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 8792
8793 /* Acer/eMachines e725 */
8794 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 8795
8796 /* Acer/Packard Bell NCL20 */
8797 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 8798
8799 /* Acer Aspire 4736Z */
8800 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 8801};
8802
8803static void intel_init_quirks(struct drm_device *dev)
8804{
8805 struct pci_dev *d = dev->pdev;
8806 int i;
8807
8808 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8809 struct intel_quirk *q = &intel_quirks[i];
8810
8811 if (d->device == q->device &&
8812 (d->subsystem_vendor == q->subsystem_vendor ||
8813 q->subsystem_vendor == PCI_ANY_ID) &&
8814 (d->subsystem_device == q->subsystem_device ||
8815 q->subsystem_device == PCI_ANY_ID))
8816 q->hook(dev);
8817 }
5f85f176
EE		 8818 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8819 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8820 intel_dmi_quirks[i].hook(dev);
8821 }
b690e96c
JB		 8822}
8823
9cce37f4
JB		 8824/* Disable the VGA plane that we never use */
8825static void i915_disable_vga(struct drm_device *dev)
8826{
8827 struct drm_i915_private *dev_priv = dev->dev_private;
8828 u8 sr1;
766aa1c4 8829 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 8830
8831 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 8832 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 8833 sr1 = inb(VGA_SR_DATA);
8834 outb(sr1 | 1<<5, VGA_SR_DATA);
8835 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8836 udelay(300);
8837
8838 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8839 POSTING_READ(vga_reg);
8840}
8841
f817586c
DV		 8842void intel_modeset_init_hw(struct drm_device *dev)
8843{
fa42e23c 8844 intel_init_power_well(dev);
0232e927 8845
a8f78b58
ED		 8846 intel_prepare_ddi(dev);
8847
f817586c
DV		 8848 intel_init_clock_gating(dev);
8849
79f5b2c7 8850 mutex_lock(&dev->struct_mutex);
8090c6b9 8851 intel_enable_gt_powersave(dev);
79f5b2c7 8852 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 8853}
8854
79e53945
JB		 8855void intel_modeset_init(struct drm_device *dev)
8856{
652c393a 8857 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 8858 int i, ret;
79e53945
JB		 8859
8860 drm_mode_config_init(dev);
8861
8862 dev->mode_config.min_width = 0;
8863 dev->mode_config.min_height = 0;
8864
019d96cb
DA		 8865 dev->mode_config.preferred_depth = 24;
8866 dev->mode_config.prefer_shadow = 1;
8867
e6ecefaa 8868 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 8869
b690e96c
JB		 8870 intel_init_quirks(dev);
8871
1fa61106
ED		 8872 intel_init_pm(dev);
8873
e70236a8
JB		 8874 intel_init_display(dev);
8875
a6c45cf0
CW		 8876 if (IS_GEN2(dev)) {
8877 dev->mode_config.max_width = 2048;
8878 dev->mode_config.max_height = 2048;
8879 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 8880 dev->mode_config.max_width = 4096;
8881 dev->mode_config.max_height = 4096;
79e53945 8882 } else {
a6c45cf0
CW		 8883 dev->mode_config.max_width = 8192;
8884 dev->mode_config.max_height = 8192;
79e53945 8885 }
5d4545ae 8886 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 8887
28c97730 8888 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 8889 INTEL_INFO(dev)->num_pipes,
8890 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 8891
7eb552ae 8892 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
79e53945 8893 intel_crtc_init(dev, i);
00c2064b
JB		 8894 ret = intel_plane_init(dev, i);
8895 if (ret)
8896 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 8897 }
8898
79f689aa 8899 intel_cpu_pll_init(dev);
ee7b9f93
JB		 8900 intel_pch_pll_init(dev);
8901
9cce37f4
JB		 8902 /* Just disable it once at startup */
8903 i915_disable_vga(dev);
79e53945 8904 intel_setup_outputs(dev);
11be49eb
CW		 8905
8906 /* Just in case the BIOS is doing something questionable. */
8907 intel_disable_fbc(dev);
2c7111db
CW		 8908}
8909
24929352
DV		 8910static void
8911intel_connector_break_all_links(struct intel_connector *connector)
8912{
8913 connector->base.dpms = DRM_MODE_DPMS_OFF;
8914 connector->base.encoder = NULL;
8915 connector->encoder->connectors_active = false;
8916 connector->encoder->base.crtc = NULL;
8917}
8918
7fad798e
DV		 8919static void intel_enable_pipe_a(struct drm_device *dev)
8920{
8921 struct intel_connector *connector;
8922 struct drm_connector *crt = NULL;
8923 struct intel_load_detect_pipe load_detect_temp;
8924
8925 /* We can't just switch on the pipe A, we need to set things up with a
8926 * proper mode and output configuration. As a gross hack, enable pipe A
8927 * by enabling the load detect pipe once. */
8928 list_for_each_entry(connector,
8929 &dev->mode_config.connector_list,
8930 base.head) {
8931 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8932 crt = &connector->base;
8933 break;
8934 }
8935 }
8936
8937 if (!crt)
8938 return;
8939
8940 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8941 intel_release_load_detect_pipe(crt, &load_detect_temp);
8942
652c393a 8943
7fad798e
DV		 8944}
8945
fa555837
DV		 8946static bool
8947intel_check_plane_mapping(struct intel_crtc *crtc)
8948{
7eb552ae
BW		 8949 struct drm_device *dev = crtc->base.dev;
8950 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 8951 u32 reg, val;
8952
7eb552ae 8953 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 8954 return true;
8955
8956 reg = DSPCNTR(!crtc->plane);
8957 val = I915_READ(reg);
8958
8959 if ((val & DISPLAY_PLANE_ENABLE) &&
8960 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8961 return false;
8962
8963 return true;
8964}
8965
24929352
DV		 8966static void intel_sanitize_crtc(struct intel_crtc *crtc)
8967{
8968 struct drm_device *dev = crtc->base.dev;
8969 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 8970 u32 reg;
24929352 8971
24929352 8972 /* Clear any frame start delays used for debugging left by the BIOS */
702e7a56 8973 reg = PIPECONF(crtc->cpu_transcoder);
24929352
DV		 8974 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8975
8976 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 8977 * disable the crtc (and hence change the state) if it is wrong. Note
8978 * that gen4+ has a fixed plane -> pipe mapping. */
8979 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 8980 struct intel_connector *connector;
8981 bool plane;
8982
24929352
DV		 8983 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8984 crtc->base.base.id);
8985
8986 /* Pipe has the wrong plane attached and the plane is active.
8987 * Temporarily change the plane mapping and disable everything
8988 * ... */
8989 plane = crtc->plane;
8990 crtc->plane = !plane;
8991 dev_priv->display.crtc_disable(&crtc->base);
8992 crtc->plane = plane;
8993
8994 /* ... and break all links. */
8995 list_for_each_entry(connector, &dev->mode_config.connector_list,
8996 base.head) {
8997 if (connector->encoder->base.crtc != &crtc->base)
8998 continue;
8999
9000 intel_connector_break_all_links(connector);
9001 }
9002
9003 WARN_ON(crtc->active);
9004 crtc->base.enabled = false;
9005 }
24929352 9006
7fad798e
DV		 9007 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9008 crtc->pipe == PIPE_A && !crtc->active) {
9009 /* BIOS forgot to enable pipe A, this mostly happens after
9010 * resume. Force-enable the pipe to fix this, the update_dpms
9011 * call below we restore the pipe to the right state, but leave
9012 * the required bits on. */
9013 intel_enable_pipe_a(dev);
9014 }
9015
24929352
DV		 9016 /* Adjust the state of the output pipe according to whether we
9017 * have active connectors/encoders. */
9018 intel_crtc_update_dpms(&crtc->base);
9019
9020 if (crtc->active != crtc->base.enabled) {
9021 struct intel_encoder *encoder;
9022
9023 /* This can happen either due to bugs in the get_hw_state
9024 * functions or because the pipe is force-enabled due to the
9025 * pipe A quirk. */
9026 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9027 crtc->base.base.id,
9028 crtc->base.enabled ? "enabled" : "disabled",
9029 crtc->active ? "enabled" : "disabled");
9030
9031 crtc->base.enabled = crtc->active;
9032
9033 /* Because we only establish the connector -> encoder ->
9034 * crtc links if something is active, this means the
9035 * crtc is now deactivated. Break the links. connector
9036 * -> encoder links are only establish when things are
9037 * actually up, hence no need to break them. */
9038 WARN_ON(crtc->active);
9039
9040 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9041 WARN_ON(encoder->connectors_active);
9042 encoder->base.crtc = NULL;
9043 }
9044 }
9045}
9046
9047static void intel_sanitize_encoder(struct intel_encoder *encoder)
9048{
9049 struct intel_connector *connector;
9050 struct drm_device *dev = encoder->base.dev;
9051
9052 /* We need to check both for a crtc link (meaning that the
9053 * encoder is active and trying to read from a pipe) and the
9054 * pipe itself being active. */
9055 bool has_active_crtc = encoder->base.crtc &&
9056 to_intel_crtc(encoder->base.crtc)->active;
9057
9058 if (encoder->connectors_active && !has_active_crtc) {
9059 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9060 encoder->base.base.id,
9061 drm_get_encoder_name(&encoder->base));
9062
9063 /* Connector is active, but has no active pipe. This is
9064 * fallout from our resume register restoring. Disable
9065 * the encoder manually again. */
9066 if (encoder->base.crtc) {
9067 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9068 encoder->base.base.id,
9069 drm_get_encoder_name(&encoder->base));
9070 encoder->disable(encoder);
9071 }
9072
9073 /* Inconsistent output/port/pipe state happens presumably due to
9074 * a bug in one of the get_hw_state functions. Or someplace else
9075 * in our code, like the register restore mess on resume. Clamp
9076 * things to off as a safer default. */
9077 list_for_each_entry(connector,
9078 &dev->mode_config.connector_list,
9079 base.head) {
9080 if (connector->encoder != encoder)
9081 continue;
9082
9083 intel_connector_break_all_links(connector);
9084 }
9085 }
9086 /* Enabled encoders without active connectors will be fixed in
9087 * the crtc fixup. */
9088}
9089
44cec740 9090void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9091{
9092 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9093 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9094
9095 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9096 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9097 i915_disable_vga(dev);
0fde901f
KM		 9098 }
9099}
9100
24929352
DV		 9101/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9102 * and i915 state tracking structures. */
45e2b5f6
DV		 9103void intel_modeset_setup_hw_state(struct drm_device *dev,
9104 bool force_restore)
24929352
DV		 9105{
9106 struct drm_i915_private *dev_priv = dev->dev_private;
9107 enum pipe pipe;
9108 u32 tmp;
9109 struct intel_crtc *crtc;
9110 struct intel_encoder *encoder;
9111 struct intel_connector *connector;
9112
affa9354 9113 if (HAS_DDI(dev)) {
e28d54cb
PZ		 9114 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9115
9116 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9117 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9118 case TRANS_DDI_EDP_INPUT_A_ON:
9119 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9120 pipe = PIPE_A;
9121 break;
9122 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9123 pipe = PIPE_B;
9124 break;
9125 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9126 pipe = PIPE_C;
9127 break;
aaa148ec
DL		 9128 default:
9129 /* A bogus value has been programmed, disable
9130 * the transcoder */
9131 WARN(1, "Bogus eDP source %08x\n", tmp);
9132 intel_ddi_disable_transcoder_func(dev_priv,
9133 TRANSCODER_EDP);
9134 goto setup_pipes;
e28d54cb
PZ		 9135 }
9136
9137 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9138 crtc->cpu_transcoder = TRANSCODER_EDP;
9139
9140 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9141 pipe_name(pipe));
9142 }
9143 }
9144
aaa148ec 9145setup_pipes:
24929352
DV		 9146 for_each_pipe(pipe) {
9147 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9148
702e7a56 9149 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
24929352
DV		 9150 if (tmp & PIPECONF_ENABLE)
9151 crtc->active = true;
9152 else
9153 crtc->active = false;
9154
9155 crtc->base.enabled = crtc->active;
9156
9157 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9158 crtc->base.base.id,
9159 crtc->active ? "enabled" : "disabled");
9160 }
9161
affa9354 9162 if (HAS_DDI(dev))
6441ab5f
PZ		 9163 intel_ddi_setup_hw_pll_state(dev);
9164
24929352
DV		 9165 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9166 base.head) {
9167 pipe = 0;
9168
9169 if (encoder->get_hw_state(encoder, &pipe)) {
9170 encoder->base.crtc =
9171 dev_priv->pipe_to_crtc_mapping[pipe];
9172 } else {
9173 encoder->base.crtc = NULL;
9174 }
9175
9176 encoder->connectors_active = false;
9177 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9178 encoder->base.base.id,
9179 drm_get_encoder_name(&encoder->base),
9180 encoder->base.crtc ? "enabled" : "disabled",
9181 pipe);
9182 }
9183
9184 list_for_each_entry(connector, &dev->mode_config.connector_list,
9185 base.head) {
9186 if (connector->get_hw_state(connector)) {
9187 connector->base.dpms = DRM_MODE_DPMS_ON;
9188 connector->encoder->connectors_active = true;
9189 connector->base.encoder = &connector->encoder->base;
9190 } else {
9191 connector->base.dpms = DRM_MODE_DPMS_OFF;
9192 connector->base.encoder = NULL;
9193 }
9194 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9195 connector->base.base.id,
9196 drm_get_connector_name(&connector->base),
9197 connector->base.encoder ? "enabled" : "disabled");
9198 }
9199
9200 /* HW state is read out, now we need to sanitize this mess. */
9201 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9202 base.head) {
9203 intel_sanitize_encoder(encoder);
9204 }
9205
9206 for_each_pipe(pipe) {
9207 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9208 intel_sanitize_crtc(crtc);
9209 }
9a935856 9210
45e2b5f6
DV		 9211 if (force_restore) {
9212 for_each_pipe(pipe) {
c0c36b94 9213 intel_crtc_restore_mode(dev_priv->pipe_to_crtc_mapping[pipe]);
45e2b5f6 9214 }
0fde901f
KM		 9215
9216 i915_redisable_vga(dev);
45e2b5f6
DV		 9217 } else {
9218 intel_modeset_update_staged_output_state(dev);
9219 }
8af6cf88
DV		 9220
9221 intel_modeset_check_state(dev);
2e938892
DV		 9222
9223 drm_mode_config_reset(dev);
2c7111db
CW		 9224}
9225
9226void intel_modeset_gem_init(struct drm_device *dev)
9227{
1833b134 9228 intel_modeset_init_hw(dev);
02e792fb
DV		 9229
9230 intel_setup_overlay(dev);
24929352 9231
45e2b5f6 9232 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9233}
9234
9235void intel_modeset_cleanup(struct drm_device *dev)
9236{
652c393a
JB		 9237 struct drm_i915_private *dev_priv = dev->dev_private;
9238 struct drm_crtc *crtc;
9239 struct intel_crtc *intel_crtc;
9240
f87ea761 9241 drm_kms_helper_poll_fini(dev);
652c393a
JB		 9242 mutex_lock(&dev->struct_mutex);
9243
723bfd70
JB		 9244 intel_unregister_dsm_handler();
9245
9246
652c393a
JB		 9247 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9248 /* Skip inactive CRTCs */
9249 if (!crtc->fb)
9250 continue;
9251
9252 intel_crtc = to_intel_crtc(crtc);
3dec0095 9253 intel_increase_pllclock(crtc);
652c393a
JB		 9254 }
9255
973d04f9 9256 intel_disable_fbc(dev);
e70236a8 9257
8090c6b9 9258 intel_disable_gt_powersave(dev);
0cdab21f 9259
930ebb46
DV		 9260 ironlake_teardown_rc6(dev);
9261
57f350b6
JB		 9262 if (IS_VALLEYVIEW(dev))
9263 vlv_init_dpio(dev);
9264
69341a5e
KH		 9265 mutex_unlock(&dev->struct_mutex);
9266
6c0d9350
DV		 9267 /* Disable the irq before mode object teardown, for the irq might
9268 * enqueue unpin/hotplug work. */
9269 drm_irq_uninstall(dev);
9270 cancel_work_sync(&dev_priv->hotplug_work);
c6a828d3 9271 cancel_work_sync(&dev_priv->rps.work);
6c0d9350 9272
1630fe75
CW		 9273 /* flush any delayed tasks or pending work */
9274 flush_scheduled_work();
9275
79e53945 9276 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9277
9278 intel_cleanup_overlay(dev);
79e53945
JB		 9279}
9280
f1c79df3
ZW		 9281/*
9282 * Return which encoder is currently attached for connector.
9283 */
df0e9248 9284struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9285{
df0e9248
CW		 9286 return &intel_attached_encoder(connector)->base;
9287}
f1c79df3 9288
df0e9248
CW		 9289void intel_connector_attach_encoder(struct intel_connector *connector,
9290 struct intel_encoder *encoder)
9291{
9292 connector->encoder = encoder;
9293 drm_mode_connector_attach_encoder(&connector->base,
9294 &encoder->base);
79e53945 9295}
28d52043
DA		 9296
9297/*
9298 * set vga decode state - true == enable VGA decode
9299 */
9300int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9301{
9302 struct drm_i915_private *dev_priv = dev->dev_private;
9303 u16 gmch_ctrl;
9304
9305 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9306 if (state)
9307 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9308 else
9309 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9310 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9311 return 0;
9312}
c4a1d9e4
CW		 9313
9314#ifdef CONFIG_DEBUG_FS
9315#include <linux/seq_file.h>
9316
9317struct intel_display_error_state {
9318 struct intel_cursor_error_state {
9319 u32 control;
9320 u32 position;
9321 u32 base;
9322 u32 size;
52331309 9323 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9324
9325 struct intel_pipe_error_state {
9326 u32 conf;
9327 u32 source;
9328
9329 u32 htotal;
9330 u32 hblank;
9331 u32 hsync;
9332 u32 vtotal;
9333 u32 vblank;
9334 u32 vsync;
52331309 9335 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9336
9337 struct intel_plane_error_state {
9338 u32 control;
9339 u32 stride;
9340 u32 size;
9341 u32 pos;
9342 u32 addr;
9343 u32 surface;
9344 u32 tile_offset;
52331309 9345 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9346};
9347
9348struct intel_display_error_state *
9349intel_display_capture_error_state(struct drm_device *dev)
9350{
0206e353 9351 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9352 struct intel_display_error_state *error;
702e7a56 9353 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9354 int i;
9355
9356 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9357 if (error == NULL)
9358 return NULL;
9359
52331309 9360 for_each_pipe(i) {
702e7a56
PZ		 9361 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9362
a18c4c3d
PZ		 9363 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9364 error->cursor[i].control = I915_READ(CURCNTR(i));
9365 error->cursor[i].position = I915_READ(CURPOS(i));
9366 error->cursor[i].base = I915_READ(CURBASE(i));
9367 } else {
9368 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9369 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9370 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9371 }
c4a1d9e4
CW		 9372
9373 error->plane[i].control = I915_READ(DSPCNTR(i));
9374 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
51889b35
PZ		 9375 if (INTEL_INFO(dev)->gen <= 3)
9376 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 9377 error->plane[i].pos = I915_READ(DSPPOS(i));
ca291363
PZ		 9378 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9379 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 9380 if (INTEL_INFO(dev)->gen >= 4) {
9381 error->plane[i].surface = I915_READ(DSPSURF(i));
9382 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9383 }
9384
702e7a56 9385 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9386 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9387 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9388 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9389 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9390 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9391 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9392 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9393 }
9394
9395 return error;
9396}
9397
9398void
9399intel_display_print_error_state(struct seq_file *m,
9400 struct drm_device *dev,
9401 struct intel_display_error_state *error)
9402{
9403 int i;
9404
7eb552ae 9405 seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
52331309 9406 for_each_pipe(i) {
c4a1d9e4
CW		 9407 seq_printf(m, "Pipe [%d]:\n", i);
9408 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9409 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9410 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9411 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9412 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9413 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9414 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9415 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9416
9417 seq_printf(m, "Plane [%d]:\n", i);
9418 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9419 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
51889b35
PZ		 9420 if (INTEL_INFO(dev)->gen <= 3)
9421 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
c4a1d9e4 9422 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
ca291363
PZ		 9423 if (!IS_HASWELL(dev))
9424 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4
CW		 9425 if (INTEL_INFO(dev)->gen >= 4) {
9426 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9427 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9428 }
9429
9430 seq_printf(m, "Cursor [%d]:\n", i);
9431 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9432 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9433 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9434 }
9435}
9436#endif
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