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[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
79e53945 48typedef struct {
0206e353 49 int min, max;
79e53945
JB		 50} intel_range_t;
51
52typedef struct {
0206e353
AJ		 53 int dot_limit;
54 int p2_slow, p2_fast;
79e53945
JB		 55} intel_p2_t;
56
57#define INTEL_P2_NUM 2
d4906093
ML		 58typedef struct intel_limit intel_limit_t;
59struct intel_limit {
0206e353
AJ		 60 intel_range_t dot, vco, n, m, m1, m2, p, p1;
61 intel_p2_t p2;
f4808ab8
VS		 62 /**
63 * find_pll() - Find the best values for the PLL
64 * @limit: limits for the PLL
65 * @crtc: current CRTC
66 * @target: target frequency in kHz
67 * @refclk: reference clock frequency in kHz
68 * @match_clock: if provided, @best_clock P divider must
69 * match the P divider from @match_clock
70 * used for LVDS downclocking
71 * @best_clock: best PLL values found
72 *
73 * Returns true on success, false on failure.
74 */
75 bool (*find_pll)(const intel_limit_t *limit,
76 struct drm_crtc *crtc,
77 int target, int refclk,
78 intel_clock_t *match_clock,
79 intel_clock_t *best_clock);
d4906093 80};
79e53945 81
2377b741
JB		 82/* FDI */
83#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
84
d2acd215
DV		 85int
86intel_pch_rawclk(struct drm_device *dev)
87{
88 struct drm_i915_private *dev_priv = dev->dev_private;
89
90 WARN_ON(!HAS_PCH_SPLIT(dev));
91
92 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
93}
94
d4906093
ML		 95static bool
96intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 97 int target, int refclk, intel_clock_t *match_clock,
98 intel_clock_t *best_clock);
d4906093
ML		 99static bool
100intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 101 int target, int refclk, intel_clock_t *match_clock,
102 intel_clock_t *best_clock);
79e53945 103
a0c4da24
JB		 104static bool
105intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
106 int target, int refclk, intel_clock_t *match_clock,
107 intel_clock_t *best_clock);
108
021357ac
CW		 109static inline u32 /* units of 100MHz */
110intel_fdi_link_freq(struct drm_device *dev)
111{
8b99e68c
CW		 112 if (IS_GEN5(dev)) {
113 struct drm_i915_private *dev_priv = dev->dev_private;
114 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
115 } else
116 return 27;
021357ac
CW		 117}
118
e4b36699 119static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 120 .dot = { .min = 25000, .max = 350000 },
121 .vco = { .min = 930000, .max = 1400000 },
122 .n = { .min = 3, .max = 16 },
123 .m = { .min = 96, .max = 140 },
124 .m1 = { .min = 18, .max = 26 },
125 .m2 = { .min = 6, .max = 16 },
126 .p = { .min = 4, .max = 128 },
127 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 128 .p2 = { .dot_limit = 165000,
129 .p2_slow = 4, .p2_fast = 2 },
d4906093 130 .find_pll = intel_find_best_PLL,
e4b36699
KP		 131};
132
133static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 134 .dot = { .min = 25000, .max = 350000 },
135 .vco = { .min = 930000, .max = 1400000 },
136 .n = { .min = 3, .max = 16 },
137 .m = { .min = 96, .max = 140 },
138 .m1 = { .min = 18, .max = 26 },
139 .m2 = { .min = 6, .max = 16 },
140 .p = { .min = 4, .max = 128 },
141 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 142 .p2 = { .dot_limit = 165000,
143 .p2_slow = 14, .p2_fast = 7 },
d4906093 144 .find_pll = intel_find_best_PLL,
e4b36699 145};
273e27ca 146
e4b36699 147static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 148 .dot = { .min = 20000, .max = 400000 },
149 .vco = { .min = 1400000, .max = 2800000 },
150 .n = { .min = 1, .max = 6 },
151 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 152 .m1 = { .min = 8, .max = 18 },
153 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 154 .p = { .min = 5, .max = 80 },
155 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 156 .p2 = { .dot_limit = 200000,
157 .p2_slow = 10, .p2_fast = 5 },
d4906093 158 .find_pll = intel_find_best_PLL,
e4b36699
KP		 159};
160
161static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 162 .dot = { .min = 20000, .max = 400000 },
163 .vco = { .min = 1400000, .max = 2800000 },
164 .n = { .min = 1, .max = 6 },
165 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 166 .m1 = { .min = 8, .max = 18 },
167 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 168 .p = { .min = 7, .max = 98 },
169 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 170 .p2 = { .dot_limit = 112000,
171 .p2_slow = 14, .p2_fast = 7 },
d4906093 172 .find_pll = intel_find_best_PLL,
e4b36699
KP		 173};
174
273e27ca 175
e4b36699 176static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 177 .dot = { .min = 25000, .max = 270000 },
178 .vco = { .min = 1750000, .max = 3500000},
179 .n = { .min = 1, .max = 4 },
180 .m = { .min = 104, .max = 138 },
181 .m1 = { .min = 17, .max = 23 },
182 .m2 = { .min = 5, .max = 11 },
183 .p = { .min = 10, .max = 30 },
184 .p1 = { .min = 1, .max = 3},
185 .p2 = { .dot_limit = 270000,
186 .p2_slow = 10,
187 .p2_fast = 10
044c7c41 188 },
d4906093 189 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 190};
191
192static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 193 .dot = { .min = 22000, .max = 400000 },
194 .vco = { .min = 1750000, .max = 3500000},
195 .n = { .min = 1, .max = 4 },
196 .m = { .min = 104, .max = 138 },
197 .m1 = { .min = 16, .max = 23 },
198 .m2 = { .min = 5, .max = 11 },
199 .p = { .min = 5, .max = 80 },
200 .p1 = { .min = 1, .max = 8},
201 .p2 = { .dot_limit = 165000,
202 .p2_slow = 10, .p2_fast = 5 },
d4906093 203 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 204};
205
206static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 207 .dot = { .min = 20000, .max = 115000 },
208 .vco = { .min = 1750000, .max = 3500000 },
209 .n = { .min = 1, .max = 3 },
210 .m = { .min = 104, .max = 138 },
211 .m1 = { .min = 17, .max = 23 },
212 .m2 = { .min = 5, .max = 11 },
213 .p = { .min = 28, .max = 112 },
214 .p1 = { .min = 2, .max = 8 },
215 .p2 = { .dot_limit = 0,
216 .p2_slow = 14, .p2_fast = 14
044c7c41 217 },
d4906093 218 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 219};
220
221static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 222 .dot = { .min = 80000, .max = 224000 },
223 .vco = { .min = 1750000, .max = 3500000 },
224 .n = { .min = 1, .max = 3 },
225 .m = { .min = 104, .max = 138 },
226 .m1 = { .min = 17, .max = 23 },
227 .m2 = { .min = 5, .max = 11 },
228 .p = { .min = 14, .max = 42 },
229 .p1 = { .min = 2, .max = 6 },
230 .p2 = { .dot_limit = 0,
231 .p2_slow = 7, .p2_fast = 7
044c7c41 232 },
d4906093 233 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 234};
235
f2b115e6 236static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 237 .dot = { .min = 20000, .max = 400000},
238 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 239 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 240 .n = { .min = 3, .max = 6 },
241 .m = { .min = 2, .max = 256 },
273e27ca 242 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 243 .m1 = { .min = 0, .max = 0 },
244 .m2 = { .min = 0, .max = 254 },
245 .p = { .min = 5, .max = 80 },
246 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 247 .p2 = { .dot_limit = 200000,
248 .p2_slow = 10, .p2_fast = 5 },
6115707b 249 .find_pll = intel_find_best_PLL,
e4b36699
KP		 250};
251
f2b115e6 252static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 253 .dot = { .min = 20000, .max = 400000 },
254 .vco = { .min = 1700000, .max = 3500000 },
255 .n = { .min = 3, .max = 6 },
256 .m = { .min = 2, .max = 256 },
257 .m1 = { .min = 0, .max = 0 },
258 .m2 = { .min = 0, .max = 254 },
259 .p = { .min = 7, .max = 112 },
260 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 261 .p2 = { .dot_limit = 112000,
262 .p2_slow = 14, .p2_fast = 14 },
6115707b 263 .find_pll = intel_find_best_PLL,
e4b36699
KP		 264};
265
273e27ca
EA		 266/* Ironlake / Sandybridge
267 *
268 * We calculate clock using (register_value + 2) for N/M1/M2, so here
269 * the range value for them is (actual_value - 2).
270 */
b91ad0ec 271static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 272 .dot = { .min = 25000, .max = 350000 },
273 .vco = { .min = 1760000, .max = 3510000 },
274 .n = { .min = 1, .max = 5 },
275 .m = { .min = 79, .max = 127 },
276 .m1 = { .min = 12, .max = 22 },
277 .m2 = { .min = 5, .max = 9 },
278 .p = { .min = 5, .max = 80 },
279 .p1 = { .min = 1, .max = 8 },
280 .p2 = { .dot_limit = 225000,
281 .p2_slow = 10, .p2_fast = 5 },
4547668a 282 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 283};
284
b91ad0ec 285static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 286 .dot = { .min = 25000, .max = 350000 },
287 .vco = { .min = 1760000, .max = 3510000 },
288 .n = { .min = 1, .max = 3 },
289 .m = { .min = 79, .max = 118 },
290 .m1 = { .min = 12, .max = 22 },
291 .m2 = { .min = 5, .max = 9 },
292 .p = { .min = 28, .max = 112 },
293 .p1 = { .min = 2, .max = 8 },
294 .p2 = { .dot_limit = 225000,
295 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 296 .find_pll = intel_g4x_find_best_PLL,
297};
298
299static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 300 .dot = { .min = 25000, .max = 350000 },
301 .vco = { .min = 1760000, .max = 3510000 },
302 .n = { .min = 1, .max = 3 },
303 .m = { .min = 79, .max = 127 },
304 .m1 = { .min = 12, .max = 22 },
305 .m2 = { .min = 5, .max = 9 },
306 .p = { .min = 14, .max = 56 },
307 .p1 = { .min = 2, .max = 8 },
308 .p2 = { .dot_limit = 225000,
309 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 310 .find_pll = intel_g4x_find_best_PLL,
311};
312
273e27ca 313/* LVDS 100mhz refclk limits. */
b91ad0ec 314static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 315 .dot = { .min = 25000, .max = 350000 },
316 .vco = { .min = 1760000, .max = 3510000 },
317 .n = { .min = 1, .max = 2 },
318 .m = { .min = 79, .max = 126 },
319 .m1 = { .min = 12, .max = 22 },
320 .m2 = { .min = 5, .max = 9 },
321 .p = { .min = 28, .max = 112 },
0206e353 322 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 323 .p2 = { .dot_limit = 225000,
324 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 325 .find_pll = intel_g4x_find_best_PLL,
326};
327
328static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 329 .dot = { .min = 25000, .max = 350000 },
330 .vco = { .min = 1760000, .max = 3510000 },
331 .n = { .min = 1, .max = 3 },
332 .m = { .min = 79, .max = 126 },
333 .m1 = { .min = 12, .max = 22 },
334 .m2 = { .min = 5, .max = 9 },
335 .p = { .min = 14, .max = 42 },
0206e353 336 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 337 .p2 = { .dot_limit = 225000,
338 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 339 .find_pll = intel_g4x_find_best_PLL,
340};
341
a0c4da24
JB		 342static const intel_limit_t intel_limits_vlv_dac = {
343 .dot = { .min = 25000, .max = 270000 },
344 .vco = { .min = 4000000, .max = 6000000 },
345 .n = { .min = 1, .max = 7 },
346 .m = { .min = 22, .max = 450 }, /* guess */
347 .m1 = { .min = 2, .max = 3 },
348 .m2 = { .min = 11, .max = 156 },
349 .p = { .min = 10, .max = 30 },
75e53986 350 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 351 .p2 = { .dot_limit = 270000,
352 .p2_slow = 2, .p2_fast = 20 },
353 .find_pll = intel_vlv_find_best_pll,
354};
355
356static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 357 .dot = { .min = 25000, .max = 270000 },
358 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 359 .n = { .min = 1, .max = 7 },
360 .m = { .min = 60, .max = 300 }, /* guess */
361 .m1 = { .min = 2, .max = 3 },
362 .m2 = { .min = 11, .max = 156 },
363 .p = { .min = 10, .max = 30 },
364 .p1 = { .min = 2, .max = 3 },
365 .p2 = { .dot_limit = 270000,
366 .p2_slow = 2, .p2_fast = 20 },
367 .find_pll = intel_vlv_find_best_pll,
368};
369
370static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 371 .dot = { .min = 25000, .max = 270000 },
372 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 373 .n = { .min = 1, .max = 7 },
74a4dd2e 374 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 375 .m1 = { .min = 2, .max = 3 },
376 .m2 = { .min = 11, .max = 156 },
377 .p = { .min = 10, .max = 30 },
75e53986 378 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 379 .p2 = { .dot_limit = 270000,
380 .p2_slow = 2, .p2_fast = 20 },
381 .find_pll = intel_vlv_find_best_pll,
382};
383
57f350b6
JB		 384u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
385{
09153000 386 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
57f350b6 387
57f350b6
JB		 388 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
389 DRM_ERROR("DPIO idle wait timed out\n");
09153000 390 return 0;
57f350b6
JB		 391 }
392
393 I915_WRITE(DPIO_REG, reg);
394 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
395 DPIO_BYTE);
396 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
397 DRM_ERROR("DPIO read wait timed out\n");
09153000 398 return 0;
57f350b6 399 }
57f350b6 400
09153000 401 return I915_READ(DPIO_DATA);
57f350b6
JB		 402}
403
e2fa6fba 404void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val)
a0c4da24 405{
09153000 406 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a0c4da24 407
a0c4da24
JB		 408 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
409 DRM_ERROR("DPIO idle wait timed out\n");
09153000 410 return;
a0c4da24
JB		 411 }
412
413 I915_WRITE(DPIO_DATA, val);
414 I915_WRITE(DPIO_REG, reg);
415 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
416 DPIO_BYTE);
417 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
418 DRM_ERROR("DPIO write wait timed out\n");
a0c4da24
JB		 419}
420
1b894b59
CW		 421static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
422 int refclk)
2c07245f 423{
b91ad0ec 424 struct drm_device *dev = crtc->dev;
2c07245f 425 const intel_limit_t *limit;
b91ad0ec
ZW		 426
427 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 428 if (intel_is_dual_link_lvds(dev)) {
1b894b59 429 if (refclk == 100000)
b91ad0ec
ZW		 430 limit = &intel_limits_ironlake_dual_lvds_100m;
431 else
432 limit = &intel_limits_ironlake_dual_lvds;
433 } else {
1b894b59 434 if (refclk == 100000)
b91ad0ec
ZW		 435 limit = &intel_limits_ironlake_single_lvds_100m;
436 else
437 limit = &intel_limits_ironlake_single_lvds;
438 }
c6bb3538 439 } else
b91ad0ec 440 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 441
442 return limit;
443}
444
044c7c41
ML		 445static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
446{
447 struct drm_device *dev = crtc->dev;
044c7c41
ML		 448 const intel_limit_t *limit;
449
450 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 451 if (intel_is_dual_link_lvds(dev))
e4b36699 452 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 453 else
e4b36699 454 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 455 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
456 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 457 limit = &intel_limits_g4x_hdmi;
044c7c41 458 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 459 limit = &intel_limits_g4x_sdvo;
044c7c41 460 } else /* The option is for other outputs */
e4b36699 461 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 462
463 return limit;
464}
465
1b894b59 466static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 467{
468 struct drm_device *dev = crtc->dev;
469 const intel_limit_t *limit;
470
bad720ff 471 if (HAS_PCH_SPLIT(dev))
1b894b59 472 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 473 else if (IS_G4X(dev)) {
044c7c41 474 limit = intel_g4x_limit(crtc);
f2b115e6 475 } else if (IS_PINEVIEW(dev)) {
2177832f 476 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 477 limit = &intel_limits_pineview_lvds;
2177832f 478 else
f2b115e6 479 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 480 } else if (IS_VALLEYVIEW(dev)) {
481 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
482 limit = &intel_limits_vlv_dac;
483 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
484 limit = &intel_limits_vlv_hdmi;
485 else
486 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 487 } else if (!IS_GEN2(dev)) {
488 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
489 limit = &intel_limits_i9xx_lvds;
490 else
491 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 492 } else {
493 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 494 limit = &intel_limits_i8xx_lvds;
79e53945 495 else
e4b36699 496 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 497 }
498 return limit;
499}
500
f2b115e6
AJ		 501/* m1 is reserved as 0 in Pineview, n is a ring counter */
502static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 503{
2177832f
SL		 504 clock->m = clock->m2 + 2;
505 clock->p = clock->p1 * clock->p2;
506 clock->vco = refclk * clock->m / clock->n;
507 clock->dot = clock->vco / clock->p;
508}
509
7429e9d4
DV		 510static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
511{
512 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
513}
514
2177832f
SL		 515static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
516{
f2b115e6
AJ		 517 if (IS_PINEVIEW(dev)) {
518 pineview_clock(refclk, clock);
2177832f
SL		 519 return;
520 }
7429e9d4 521 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 522 clock->p = clock->p1 * clock->p2;
523 clock->vco = refclk * clock->m / (clock->n + 2);
524 clock->dot = clock->vco / clock->p;
525}
526
79e53945
JB		 527/**
528 * Returns whether any output on the specified pipe is of the specified type
529 */
4ef69c7a 530bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 531{
4ef69c7a 532 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 533 struct intel_encoder *encoder;
534
6c2b7c12
DV		 535 for_each_encoder_on_crtc(dev, crtc, encoder)
536 if (encoder->type == type)
4ef69c7a
CW		 537 return true;
538
539 return false;
79e53945
JB		 540}
541
7c04d1d9 542#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 543/**
544 * Returns whether the given set of divisors are valid for a given refclk with
545 * the given connectors.
546 */
547
1b894b59
CW		 548static bool intel_PLL_is_valid(struct drm_device *dev,
549 const intel_limit_t *limit,
550 const intel_clock_t *clock)
79e53945 551{
79e53945 552 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 553 INTELPllInvalid("p1 out of range\n");
79e53945 554 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 555 INTELPllInvalid("p out of range\n");
79e53945 556 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 557 INTELPllInvalid("m2 out of range\n");
79e53945 558 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 559 INTELPllInvalid("m1 out of range\n");
f2b115e6 560 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 561 INTELPllInvalid("m1 <= m2\n");
79e53945 562 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 563 INTELPllInvalid("m out of range\n");
79e53945 564 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 565 INTELPllInvalid("n out of range\n");
79e53945 566 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 567 INTELPllInvalid("vco out of range\n");
79e53945
JB		 568 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
569 * connector, etc., rather than just a single range.
570 */
571 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 572 INTELPllInvalid("dot out of range\n");
79e53945
JB		 573
574 return true;
575}
576
d4906093
ML		 577static bool
578intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 579 int target, int refclk, intel_clock_t *match_clock,
580 intel_clock_t *best_clock)
d4906093 581
79e53945
JB		 582{
583 struct drm_device *dev = crtc->dev;
79e53945 584 intel_clock_t clock;
79e53945
JB		 585 int err = target;
586
a210b028 587 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 588 /*
a210b028
DV		 589 * For LVDS just rely on its current settings for dual-channel.
590 * We haven't figured out how to reliably set up different
591 * single/dual channel state, if we even can.
79e53945 592 */
1974cad0 593 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 594 clock.p2 = limit->p2.p2_fast;
595 else
596 clock.p2 = limit->p2.p2_slow;
597 } else {
598 if (target < limit->p2.dot_limit)
599 clock.p2 = limit->p2.p2_slow;
600 else
601 clock.p2 = limit->p2.p2_fast;
602 }
603
0206e353 604 memset(best_clock, 0, sizeof(*best_clock));
79e53945 605
42158660
ZY		 606 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
607 clock.m1++) {
608 for (clock.m2 = limit->m2.min;
609 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 610 /* m1 is always 0 in Pineview */
611 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 612 break;
613 for (clock.n = limit->n.min;
614 clock.n <= limit->n.max; clock.n++) {
615 for (clock.p1 = limit->p1.min;
616 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 617 int this_err;
618
2177832f 619 intel_clock(dev, refclk, &clock);
1b894b59
CW		 620 if (!intel_PLL_is_valid(dev, limit,
621 &clock))
79e53945 622 continue;
cec2f356
SP		 623 if (match_clock &&
624 clock.p != match_clock->p)
625 continue;
79e53945
JB		 626
627 this_err = abs(clock.dot - target);
628 if (this_err < err) {
629 *best_clock = clock;
630 err = this_err;
631 }
632 }
633 }
634 }
635 }
636
637 return (err != target);
638}
639
d4906093
ML		 640static bool
641intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 642 int target, int refclk, intel_clock_t *match_clock,
643 intel_clock_t *best_clock)
d4906093
ML		 644{
645 struct drm_device *dev = crtc->dev;
d4906093
ML		 646 intel_clock_t clock;
647 int max_n;
648 bool found;
6ba770dc
AJ		 649 /* approximately equals target * 0.00585 */
650 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 651 found = false;
652
653 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 654 int lvds_reg;
655
c619eed4 656 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 657 lvds_reg = PCH_LVDS;
658 else
659 lvds_reg = LVDS;
1974cad0 660 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 661 clock.p2 = limit->p2.p2_fast;
662 else
663 clock.p2 = limit->p2.p2_slow;
664 } else {
665 if (target < limit->p2.dot_limit)
666 clock.p2 = limit->p2.p2_slow;
667 else
668 clock.p2 = limit->p2.p2_fast;
669 }
670
671 memset(best_clock, 0, sizeof(*best_clock));
672 max_n = limit->n.max;
f77f13e2 673 /* based on hardware requirement, prefer smaller n to precision */
d4906093 674 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 675 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 676 for (clock.m1 = limit->m1.max;
677 clock.m1 >= limit->m1.min; clock.m1--) {
678 for (clock.m2 = limit->m2.max;
679 clock.m2 >= limit->m2.min; clock.m2--) {
680 for (clock.p1 = limit->p1.max;
681 clock.p1 >= limit->p1.min; clock.p1--) {
682 int this_err;
683
2177832f 684 intel_clock(dev, refclk, &clock);
1b894b59
CW		 685 if (!intel_PLL_is_valid(dev, limit,
686 &clock))
d4906093 687 continue;
1b894b59
CW		 688
689 this_err = abs(clock.dot - target);
d4906093
ML		 690 if (this_err < err_most) {
691 *best_clock = clock;
692 err_most = this_err;
693 max_n = clock.n;
694 found = true;
695 }
696 }
697 }
698 }
699 }
2c07245f
ZW		 700 return found;
701}
702
a0c4da24
JB		 703static bool
704intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
705 int target, int refclk, intel_clock_t *match_clock,
706 intel_clock_t *best_clock)
707{
708 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
709 u32 m, n, fastclk;
710 u32 updrate, minupdate, fracbits, p;
711 unsigned long bestppm, ppm, absppm;
712 int dotclk, flag;
713
af447bd3 714 flag = 0;
a0c4da24
JB		 715 dotclk = target * 1000;
716 bestppm = 1000000;
717 ppm = absppm = 0;
718 fastclk = dotclk / (2*100);
719 updrate = 0;
720 minupdate = 19200;
721 fracbits = 1;
722 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
723 bestm1 = bestm2 = bestp1 = bestp2 = 0;
724
725 /* based on hardware requirement, prefer smaller n to precision */
726 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
727 updrate = refclk / n;
728 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
729 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
730 if (p2 > 10)
731 p2 = p2 - 1;
732 p = p1 * p2;
733 /* based on hardware requirement, prefer bigger m1,m2 values */
734 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
735 m2 = (((2*(fastclk * p * n / m1 )) +
736 refclk) / (2*refclk));
737 m = m1 * m2;
738 vco = updrate * m;
739 if (vco >= limit->vco.min && vco < limit->vco.max) {
740 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
741 absppm = (ppm > 0) ? ppm : (-ppm);
742 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
743 bestppm = 0;
744 flag = 1;
745 }
746 if (absppm < bestppm - 10) {
747 bestppm = absppm;
748 flag = 1;
749 }
750 if (flag) {
751 bestn = n;
752 bestm1 = m1;
753 bestm2 = m2;
754 bestp1 = p1;
755 bestp2 = p2;
756 flag = 0;
757 }
758 }
759 }
760 }
761 }
762 }
763 best_clock->n = bestn;
764 best_clock->m1 = bestm1;
765 best_clock->m2 = bestm2;
766 best_clock->p1 = bestp1;
767 best_clock->p2 = bestp2;
768
769 return true;
770}
a4fc5ed6 771
a5c961d1
PZ		 772enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
773 enum pipe pipe)
774{
775 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
776 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
777
3b117c8f 778 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 779}
780
a928d536
PZ		 781static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
782{
783 struct drm_i915_private *dev_priv = dev->dev_private;
784 u32 frame, frame_reg = PIPEFRAME(pipe);
785
786 frame = I915_READ(frame_reg);
787
788 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
789 DRM_DEBUG_KMS("vblank wait timed out\n");
790}
791
9d0498a2
JB		 792/**
793 * intel_wait_for_vblank - wait for vblank on a given pipe
794 * @dev: drm device
795 * @pipe: pipe to wait for
796 *
797 * Wait for vblank to occur on a given pipe. Needed for various bits of
798 * mode setting code.
799 */
800void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 801{
9d0498a2 802 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 803 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 804
a928d536
PZ		 805 if (INTEL_INFO(dev)->gen >= 5) {
806 ironlake_wait_for_vblank(dev, pipe);
807 return;
808 }
809
300387c0
CW		 810 /* Clear existing vblank status. Note this will clear any other
811 * sticky status fields as well.
812 *
813 * This races with i915_driver_irq_handler() with the result
814 * that either function could miss a vblank event. Here it is not
815 * fatal, as we will either wait upon the next vblank interrupt or
816 * timeout. Generally speaking intel_wait_for_vblank() is only
817 * called during modeset at which time the GPU should be idle and
818 * should *not* be performing page flips and thus not waiting on
819 * vblanks...
820 * Currently, the result of us stealing a vblank from the irq
821 * handler is that a single frame will be skipped during swapbuffers.
822 */
823 I915_WRITE(pipestat_reg,
824 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
825
9d0498a2 826 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 827 if (wait_for(I915_READ(pipestat_reg) &
828 PIPE_VBLANK_INTERRUPT_STATUS,
829 50))
9d0498a2
JB		 830 DRM_DEBUG_KMS("vblank wait timed out\n");
831}
832
ab7ad7f6
KP		 833/*
834 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 835 * @dev: drm device
836 * @pipe: pipe to wait for
837 *
838 * After disabling a pipe, we can't wait for vblank in the usual way,
839 * spinning on the vblank interrupt status bit, since we won't actually
840 * see an interrupt when the pipe is disabled.
841 *
ab7ad7f6
KP		 842 * On Gen4 and above:
843 * wait for the pipe register state bit to turn off
844 *
845 * Otherwise:
846 * wait for the display line value to settle (it usually
847 * ends up stopping at the start of the next frame).
58e10eb9 848 *
9d0498a2 849 */
58e10eb9 850void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 851{
852 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 853 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
854 pipe);
ab7ad7f6
KP		 855
856 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 857 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 858
859 /* Wait for the Pipe State to go off */
58e10eb9
CW		 860 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
861 100))
284637d9 862 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 863 } else {
837ba00f 864 u32 last_line, line_mask;
58e10eb9 865 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 866 unsigned long timeout = jiffies + msecs_to_jiffies(100);
867
837ba00f
PZ		 868 if (IS_GEN2(dev))
869 line_mask = DSL_LINEMASK_GEN2;
870 else
871 line_mask = DSL_LINEMASK_GEN3;
872
ab7ad7f6
KP		 873 /* Wait for the display line to settle */
874 do {
837ba00f 875 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 876 mdelay(5);
837ba00f 877 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 878 time_after(timeout, jiffies));
879 if (time_after(jiffies, timeout))
284637d9 880 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 881 }
79e53945
JB		 882}
883
b0ea7d37
DL		 884/*
885 * ibx_digital_port_connected - is the specified port connected?
886 * @dev_priv: i915 private structure
887 * @port: the port to test
888 *
889 * Returns true if @port is connected, false otherwise.
890 */
891bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
892 struct intel_digital_port *port)
893{
894 u32 bit;
895
c36346e3
DL		 896 if (HAS_PCH_IBX(dev_priv->dev)) {
897 switch(port->port) {
898 case PORT_B:
899 bit = SDE_PORTB_HOTPLUG;
900 break;
901 case PORT_C:
902 bit = SDE_PORTC_HOTPLUG;
903 break;
904 case PORT_D:
905 bit = SDE_PORTD_HOTPLUG;
906 break;
907 default:
908 return true;
909 }
910 } else {
911 switch(port->port) {
912 case PORT_B:
913 bit = SDE_PORTB_HOTPLUG_CPT;
914 break;
915 case PORT_C:
916 bit = SDE_PORTC_HOTPLUG_CPT;
917 break;
918 case PORT_D:
919 bit = SDE_PORTD_HOTPLUG_CPT;
920 break;
921 default:
922 return true;
923 }
b0ea7d37
DL		 924 }
925
926 return I915_READ(SDEISR) & bit;
927}
928
b24e7179
JB		 929static const char *state_string(bool enabled)
930{
931 return enabled ? "on" : "off";
932}
933
934/* Only for pre-ILK configs */
935static void assert_pll(struct drm_i915_private *dev_priv,
936 enum pipe pipe, bool state)
937{
938 int reg;
939 u32 val;
940 bool cur_state;
941
942 reg = DPLL(pipe);
943 val = I915_READ(reg);
944 cur_state = !!(val & DPLL_VCO_ENABLE);
945 WARN(cur_state != state,
946 "PLL state assertion failure (expected %s, current %s)\n",
947 state_string(state), state_string(cur_state));
948}
949#define assert_pll_enabled(d, p) assert_pll(d, p, true)
950#define assert_pll_disabled(d, p) assert_pll(d, p, false)
951
040484af
JB		 952/* For ILK+ */
953static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 954 struct intel_pch_pll *pll,
955 struct intel_crtc *crtc,
956 bool state)
040484af 957{
040484af
JB		 958 u32 val;
959 bool cur_state;
960
9d82aa17
ED		 961 if (HAS_PCH_LPT(dev_priv->dev)) {
962 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
963 return;
964 }
965
92b27b08
CW		 966 if (WARN (!pll,
967 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 968 return;
ee7b9f93 969
92b27b08
CW		 970 val = I915_READ(pll->pll_reg);
971 cur_state = !!(val & DPLL_VCO_ENABLE);
972 WARN(cur_state != state,
973 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
974 pll->pll_reg, state_string(state), state_string(cur_state), val);
975
976 /* Make sure the selected PLL is correctly attached to the transcoder */
977 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 978 u32 pch_dpll;
979
980 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 981 cur_state = pll->pll_reg == _PCH_DPLL_B;
982 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
4bb6f1f3
VS		 983 "PLL[%d] not attached to this transcoder %c: %08x\n",
984 cur_state, pipe_name(crtc->pipe), pch_dpll)) {
92b27b08
CW		 985 cur_state = !!(val >> (4*crtc->pipe + 3));
986 WARN(cur_state != state,
4bb6f1f3 987 "PLL[%d] not %s on this transcoder %c: %08x\n",
92b27b08
CW		 988 pll->pll_reg == _PCH_DPLL_B,
989 state_string(state),
4bb6f1f3 990 pipe_name(crtc->pipe),
92b27b08
CW		 991 val);
992 }
d3ccbe86 993 }
040484af 994}
92b27b08
CW		 995#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
996#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 997
998static void assert_fdi_tx(struct drm_i915_private *dev_priv,
999 enum pipe pipe, bool state)
1000{
1001 int reg;
1002 u32 val;
1003 bool cur_state;
ad80a810
PZ		 1004 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1005 pipe);
040484af 1006
affa9354
PZ		 1007 if (HAS_DDI(dev_priv->dev)) {
1008 /* DDI does not have a specific FDI_TX register */
ad80a810 1009 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1010 val = I915_READ(reg);
ad80a810 1011 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1012 } else {
1013 reg = FDI_TX_CTL(pipe);
1014 val = I915_READ(reg);
1015 cur_state = !!(val & FDI_TX_ENABLE);
1016 }
040484af
JB		 1017 WARN(cur_state != state,
1018 "FDI TX state assertion failure (expected %s, current %s)\n",
1019 state_string(state), state_string(cur_state));
1020}
1021#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1022#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1023
1024static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1025 enum pipe pipe, bool state)
1026{
1027 int reg;
1028 u32 val;
1029 bool cur_state;
1030
d63fa0dc
PZ		 1031 reg = FDI_RX_CTL(pipe);
1032 val = I915_READ(reg);
1033 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1034 WARN(cur_state != state,
1035 "FDI RX state assertion failure (expected %s, current %s)\n",
1036 state_string(state), state_string(cur_state));
1037}
1038#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1039#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1040
1041static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1042 enum pipe pipe)
1043{
1044 int reg;
1045 u32 val;
1046
1047 /* ILK FDI PLL is always enabled */
1048 if (dev_priv->info->gen == 5)
1049 return;
1050
bf507ef7 1051 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1052 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1053 return;
1054
040484af
JB		 1055 reg = FDI_TX_CTL(pipe);
1056 val = I915_READ(reg);
1057 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1058}
1059
1060static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1061 enum pipe pipe)
1062{
1063 int reg;
1064 u32 val;
1065
1066 reg = FDI_RX_CTL(pipe);
1067 val = I915_READ(reg);
1068 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1069}
1070
ea0760cf
JB		 1071static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1072 enum pipe pipe)
1073{
1074 int pp_reg, lvds_reg;
1075 u32 val;
1076 enum pipe panel_pipe = PIPE_A;
0de3b485 1077 bool locked = true;
ea0760cf
JB		 1078
1079 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1080 pp_reg = PCH_PP_CONTROL;
1081 lvds_reg = PCH_LVDS;
1082 } else {
1083 pp_reg = PP_CONTROL;
1084 lvds_reg = LVDS;
1085 }
1086
1087 val = I915_READ(pp_reg);
1088 if (!(val & PANEL_POWER_ON) ||
1089 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1090 locked = false;
1091
1092 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1093 panel_pipe = PIPE_B;
1094
1095 WARN(panel_pipe == pipe && locked,
1096 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1097 pipe_name(pipe));
ea0760cf
JB		 1098}
1099
b840d907
JB		 1100void assert_pipe(struct drm_i915_private *dev_priv,
1101 enum pipe pipe, bool state)
b24e7179
JB		 1102{
1103 int reg;
1104 u32 val;
63d7bbe9 1105 bool cur_state;
702e7a56
PZ		 1106 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1107 pipe);
b24e7179 1108
8e636784
DV		 1109 /* if we need the pipe A quirk it must be always on */
1110 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1111 state = true;
1112
15d199ea
PZ		 1113 if (!intel_using_power_well(dev_priv->dev) &&
1114 cpu_transcoder != TRANSCODER_EDP) {
69310161
PZ		 1115 cur_state = false;
1116 } else {
1117 reg = PIPECONF(cpu_transcoder);
1118 val = I915_READ(reg);
1119 cur_state = !!(val & PIPECONF_ENABLE);
1120 }
1121
63d7bbe9
JB		 1122 WARN(cur_state != state,
1123 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1124 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1125}
1126
931872fc
CW		 1127static void assert_plane(struct drm_i915_private *dev_priv,
1128 enum plane plane, bool state)
b24e7179
JB		 1129{
1130 int reg;
1131 u32 val;
931872fc 1132 bool cur_state;
b24e7179
JB		 1133
1134 reg = DSPCNTR(plane);
1135 val = I915_READ(reg);
931872fc
CW		 1136 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1137 WARN(cur_state != state,
1138 "plane %c assertion failure (expected %s, current %s)\n",
1139 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1140}
1141
931872fc
CW		 1142#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1143#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1144
b24e7179
JB		 1145static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1146 enum pipe pipe)
1147{
1148 int reg, i;
1149 u32 val;
1150 int cur_pipe;
1151
19ec1358 1152 /* Planes are fixed to pipes on ILK+ */
da6ecc5d 1153 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
28c05794
AJ		 1154 reg = DSPCNTR(pipe);
1155 val = I915_READ(reg);
1156 WARN((val & DISPLAY_PLANE_ENABLE),
1157 "plane %c assertion failure, should be disabled but not\n",
1158 plane_name(pipe));
19ec1358 1159 return;
28c05794 1160 }
19ec1358 1161
b24e7179
JB		 1162 /* Need to check both planes against the pipe */
1163 for (i = 0; i < 2; i++) {
1164 reg = DSPCNTR(i);
1165 val = I915_READ(reg);
1166 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1167 DISPPLANE_SEL_PIPE_SHIFT;
1168 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1169 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1170 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1171 }
1172}
1173
19332d7a
JB		 1174static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1175 enum pipe pipe)
1176{
1177 int reg, i;
1178 u32 val;
1179
1180 if (!IS_VALLEYVIEW(dev_priv->dev))
1181 return;
1182
1183 /* Need to check both planes against the pipe */
1184 for (i = 0; i < dev_priv->num_plane; i++) {
1185 reg = SPCNTR(pipe, i);
1186 val = I915_READ(reg);
1187 WARN((val & SP_ENABLE),
06da8da2
VS		 1188 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1189 sprite_name(pipe, i), pipe_name(pipe));
19332d7a
JB		 1190 }
1191}
1192
92f2584a
JB		 1193static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1194{
1195 u32 val;
1196 bool enabled;
1197
9d82aa17
ED		 1198 if (HAS_PCH_LPT(dev_priv->dev)) {
1199 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1200 return;
1201 }
1202
92f2584a
JB		 1203 val = I915_READ(PCH_DREF_CONTROL);
1204 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1205 DREF_SUPERSPREAD_SOURCE_MASK));
1206 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1207}
1208
ab9412ba
DV		 1209static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1210 enum pipe pipe)
92f2584a
JB		 1211{
1212 int reg;
1213 u32 val;
1214 bool enabled;
1215
ab9412ba 1216 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1217 val = I915_READ(reg);
1218 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1219 WARN(enabled,
1220 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1221 pipe_name(pipe));
92f2584a
JB		 1222}
1223
4e634389
KP		 1224static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1225 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1226{
1227 if ((val & DP_PORT_EN) == 0)
1228 return false;
1229
1230 if (HAS_PCH_CPT(dev_priv->dev)) {
1231 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1232 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1233 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1234 return false;
1235 } else {
1236 if ((val & DP_PIPE_MASK) != (pipe << 30))
1237 return false;
1238 }
1239 return true;
1240}
1241
1519b995
KP		 1242static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1243 enum pipe pipe, u32 val)
1244{
dc0fa718 1245 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1246 return false;
1247
1248 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1249 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1250 return false;
1251 } else {
dc0fa718 1252 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1253 return false;
1254 }
1255 return true;
1256}
1257
1258static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1259 enum pipe pipe, u32 val)
1260{
1261 if ((val & LVDS_PORT_EN) == 0)
1262 return false;
1263
1264 if (HAS_PCH_CPT(dev_priv->dev)) {
1265 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1266 return false;
1267 } else {
1268 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1269 return false;
1270 }
1271 return true;
1272}
1273
1274static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1275 enum pipe pipe, u32 val)
1276{
1277 if ((val & ADPA_DAC_ENABLE) == 0)
1278 return false;
1279 if (HAS_PCH_CPT(dev_priv->dev)) {
1280 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1281 return false;
1282 } else {
1283 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1284 return false;
1285 }
1286 return true;
1287}
1288
291906f1 1289static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1290 enum pipe pipe, int reg, u32 port_sel)
291906f1 1291{
47a05eca 1292 u32 val = I915_READ(reg);
4e634389 1293 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1294 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1295 reg, pipe_name(pipe));
de9a35ab 1296
75c5da27
DV		 1297 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1298 && (val & DP_PIPEB_SELECT),
de9a35ab 1299 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1300}
1301
1302static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1303 enum pipe pipe, int reg)
1304{
47a05eca 1305 u32 val = I915_READ(reg);
b70ad586 1306 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1307 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1308 reg, pipe_name(pipe));
de9a35ab 1309
dc0fa718 1310 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1311 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1312 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1313}
1314
1315static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1316 enum pipe pipe)
1317{
1318 int reg;
1319 u32 val;
291906f1 1320
f0575e92
KP		 1321 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1322 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1323 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1324
1325 reg = PCH_ADPA;
1326 val = I915_READ(reg);
b70ad586 1327 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1328 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1329 pipe_name(pipe));
291906f1
JB		 1330
1331 reg = PCH_LVDS;
1332 val = I915_READ(reg);
b70ad586 1333 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1334 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1335 pipe_name(pipe));
291906f1 1336
e2debe91
PZ		 1337 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1338 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1339 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1340}
1341
63d7bbe9
JB		 1342/**
1343 * intel_enable_pll - enable a PLL
1344 * @dev_priv: i915 private structure
1345 * @pipe: pipe PLL to enable
1346 *
1347 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1348 * make sure the PLL reg is writable first though, since the panel write
1349 * protect mechanism may be enabled.
1350 *
1351 * Note! This is for pre-ILK only.
7434a255
TR		 1352 *
1353 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1354 */
1355static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1356{
1357 int reg;
1358 u32 val;
1359
58c6eaa2
DV		 1360 assert_pipe_disabled(dev_priv, pipe);
1361
63d7bbe9 1362 /* No really, not for ILK+ */
a0c4da24 1363 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1364
1365 /* PLL is protected by panel, make sure we can write it */
1366 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1367 assert_panel_unlocked(dev_priv, pipe);
1368
1369 reg = DPLL(pipe);
1370 val = I915_READ(reg);
1371 val |= DPLL_VCO_ENABLE;
1372
1373 /* We do this three times for luck */
1374 I915_WRITE(reg, val);
1375 POSTING_READ(reg);
1376 udelay(150); /* wait for warmup */
1377 I915_WRITE(reg, val);
1378 POSTING_READ(reg);
1379 udelay(150); /* wait for warmup */
1380 I915_WRITE(reg, val);
1381 POSTING_READ(reg);
1382 udelay(150); /* wait for warmup */
1383}
1384
1385/**
1386 * intel_disable_pll - disable a PLL
1387 * @dev_priv: i915 private structure
1388 * @pipe: pipe PLL to disable
1389 *
1390 * Disable the PLL for @pipe, making sure the pipe is off first.
1391 *
1392 * Note! This is for pre-ILK only.
1393 */
1394static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1395{
1396 int reg;
1397 u32 val;
1398
1399 /* Don't disable pipe A or pipe A PLLs if needed */
1400 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1401 return;
1402
1403 /* Make sure the pipe isn't still relying on us */
1404 assert_pipe_disabled(dev_priv, pipe);
1405
1406 reg = DPLL(pipe);
1407 val = I915_READ(reg);
1408 val &= ~DPLL_VCO_ENABLE;
1409 I915_WRITE(reg, val);
1410 POSTING_READ(reg);
1411}
1412
a416edef
ED		 1413/* SBI access */
1414static void
988d6ee8
PZ		 1415intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1416 enum intel_sbi_destination destination)
a416edef 1417{
988d6ee8 1418 u32 tmp;
a416edef 1419
09153000 1420 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1421
39fb50f6 1422 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1423 100)) {
1424 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1425 return;
a416edef
ED		 1426 }
1427
988d6ee8
PZ		 1428 I915_WRITE(SBI_ADDR, (reg << 16));
1429 I915_WRITE(SBI_DATA, value);
1430
1431 if (destination == SBI_ICLK)
1432 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1433 else
1434 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1435 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
a416edef 1436
39fb50f6 1437 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1438 100)) {
1439 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
09153000 1440 return;
a416edef 1441 }
a416edef
ED		 1442}
1443
1444static u32
988d6ee8
PZ		 1445intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1446 enum intel_sbi_destination destination)
a416edef 1447{
39fb50f6 1448 u32 value = 0;
09153000 1449 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1450
39fb50f6 1451 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1452 100)) {
1453 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1454 return 0;
a416edef
ED		 1455 }
1456
988d6ee8
PZ		 1457 I915_WRITE(SBI_ADDR, (reg << 16));
1458
1459 if (destination == SBI_ICLK)
1460 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1461 else
1462 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1463 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
a416edef 1464
39fb50f6 1465 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1466 100)) {
1467 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
09153000 1468 return 0;
a416edef
ED		 1469 }
1470
09153000 1471 return I915_READ(SBI_DATA);
a416edef
ED		 1472}
1473
89b667f8
JB		 1474void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1475{
1476 u32 port_mask;
1477
1478 if (!port)
1479 port_mask = DPLL_PORTB_READY_MASK;
1480 else
1481 port_mask = DPLL_PORTC_READY_MASK;
1482
1483 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1484 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1485 'B' + port, I915_READ(DPLL(0)));
1486}
1487
92f2584a 1488/**
b6b4e185 1489 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1490 * @dev_priv: i915 private structure
1491 * @pipe: pipe PLL to enable
1492 *
1493 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1494 * drives the transcoder clock.
1495 */
b6b4e185 1496static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1497{
ee7b9f93 1498 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1499 struct intel_pch_pll *pll;
92f2584a
JB		 1500 int reg;
1501 u32 val;
1502
48da64a8 1503 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1504 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1505 pll = intel_crtc->pch_pll;
1506 if (pll == NULL)
1507 return;
1508
1509 if (WARN_ON(pll->refcount == 0))
1510 return;
ee7b9f93
JB		 1511
1512 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1513 pll->pll_reg, pll->active, pll->on,
1514 intel_crtc->base.base.id);
92f2584a
JB		 1515
1516 /* PCH refclock must be enabled first */
1517 assert_pch_refclk_enabled(dev_priv);
1518
ee7b9f93 1519 if (pll->active++ && pll->on) {
92b27b08 1520 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1521 return;
1522 }
1523
1524 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1525
1526 reg = pll->pll_reg;
92f2584a
JB		 1527 val = I915_READ(reg);
1528 val |= DPLL_VCO_ENABLE;
1529 I915_WRITE(reg, val);
1530 POSTING_READ(reg);
1531 udelay(200);
ee7b9f93
JB		 1532
1533 pll->on = true;
92f2584a
JB		 1534}
1535
ee7b9f93 1536static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1537{
ee7b9f93
JB		 1538 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1539 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1540 int reg;
ee7b9f93 1541 u32 val;
4c609cb8 1542
92f2584a
JB		 1543 /* PCH only available on ILK+ */
1544 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1545 if (pll == NULL)
1546 return;
92f2584a 1547
48da64a8
CW		 1548 if (WARN_ON(pll->refcount == 0))
1549 return;
7a419866 1550
ee7b9f93
JB		 1551 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1552 pll->pll_reg, pll->active, pll->on,
1553 intel_crtc->base.base.id);
7a419866 1554
48da64a8 1555 if (WARN_ON(pll->active == 0)) {
92b27b08 1556 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1557 return;
1558 }
1559
ee7b9f93 1560 if (--pll->active) {
92b27b08 1561 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1562 return;
ee7b9f93
JB		 1563 }
1564
1565 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1566
1567 /* Make sure transcoder isn't still depending on us */
ab9412ba 1568 assert_pch_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1569
ee7b9f93 1570 reg = pll->pll_reg;
92f2584a
JB		 1571 val = I915_READ(reg);
1572 val &= ~DPLL_VCO_ENABLE;
1573 I915_WRITE(reg, val);
1574 POSTING_READ(reg);
1575 udelay(200);
ee7b9f93
JB		 1576
1577 pll->on = false;
92f2584a
JB		 1578}
1579
b8a4f404
PZ		 1580static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1581 enum pipe pipe)
040484af 1582{
23670b32 1583 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1584 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1585 uint32_t reg, val, pipeconf_val;
040484af
JB		 1586
1587 /* PCH only available on ILK+ */
1588 BUG_ON(dev_priv->info->gen < 5);
1589
1590 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1591 assert_pch_pll_enabled(dev_priv,
1592 to_intel_crtc(crtc)->pch_pll,
1593 to_intel_crtc(crtc));
040484af
JB		 1594
1595 /* FDI must be feeding us bits for PCH ports */
1596 assert_fdi_tx_enabled(dev_priv, pipe);
1597 assert_fdi_rx_enabled(dev_priv, pipe);
1598
23670b32
DV		 1599 if (HAS_PCH_CPT(dev)) {
1600 /* Workaround: Set the timing override bit before enabling the
1601 * pch transcoder. */
1602 reg = TRANS_CHICKEN2(pipe);
1603 val = I915_READ(reg);
1604 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1605 I915_WRITE(reg, val);
59c859d6 1606 }
23670b32 1607
ab9412ba 1608 reg = PCH_TRANSCONF(pipe);
040484af 1609 val = I915_READ(reg);
5f7f726d 1610 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1611
1612 if (HAS_PCH_IBX(dev_priv->dev)) {
1613 /*
1614 * make the BPC in transcoder be consistent with
1615 * that in pipeconf reg.
1616 */
dfd07d72
DV		 1617 val &= ~PIPECONF_BPC_MASK;
1618 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1619 }
5f7f726d
PZ		 1620
1621 val &= ~TRANS_INTERLACE_MASK;
1622 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1623 if (HAS_PCH_IBX(dev_priv->dev) &&
1624 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1625 val |= TRANS_LEGACY_INTERLACED_ILK;
1626 else
1627 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1628 else
1629 val |= TRANS_PROGRESSIVE;
1630
040484af
JB		 1631 I915_WRITE(reg, val | TRANS_ENABLE);
1632 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1633 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1634}
1635
8fb033d7 1636static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1637 enum transcoder cpu_transcoder)
040484af 1638{
8fb033d7 1639 u32 val, pipeconf_val;
8fb033d7
PZ		 1640
1641 /* PCH only available on ILK+ */
1642 BUG_ON(dev_priv->info->gen < 5);
1643
8fb033d7 1644 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1645 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1646 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1647
223a6fdf
PZ		 1648 /* Workaround: set timing override bit. */
1649 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1650 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1651 I915_WRITE(_TRANSA_CHICKEN2, val);
1652
25f3ef11 1653 val = TRANS_ENABLE;
937bb610 1654 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1655
9a76b1c6
PZ		 1656 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1657 PIPECONF_INTERLACED_ILK)
a35f2679 1658 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1659 else
1660 val |= TRANS_PROGRESSIVE;
1661
ab9412ba
DV		 1662 I915_WRITE(LPT_TRANSCONF, val);
1663 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1664 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1665}
1666
b8a4f404
PZ		 1667static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1668 enum pipe pipe)
040484af 1669{
23670b32
DV		 1670 struct drm_device *dev = dev_priv->dev;
1671 uint32_t reg, val;
040484af
JB		 1672
1673 /* FDI relies on the transcoder */
1674 assert_fdi_tx_disabled(dev_priv, pipe);
1675 assert_fdi_rx_disabled(dev_priv, pipe);
1676
291906f1
JB		 1677 /* Ports must be off as well */
1678 assert_pch_ports_disabled(dev_priv, pipe);
1679
ab9412ba 1680 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1681 val = I915_READ(reg);
1682 val &= ~TRANS_ENABLE;
1683 I915_WRITE(reg, val);
1684 /* wait for PCH transcoder off, transcoder state */
1685 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1686 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1687
1688 if (!HAS_PCH_IBX(dev)) {
1689 /* Workaround: Clear the timing override chicken bit again. */
1690 reg = TRANS_CHICKEN2(pipe);
1691 val = I915_READ(reg);
1692 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1693 I915_WRITE(reg, val);
1694 }
040484af
JB		 1695}
1696
ab4d966c 1697static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1698{
8fb033d7
PZ		 1699 u32 val;
1700
ab9412ba 1701 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1702 val &= ~TRANS_ENABLE;
ab9412ba 1703 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1704 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1705 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1706 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1707
1708 /* Workaround: clear timing override bit. */
1709 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1710 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1711 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1712}
1713
b24e7179 1714/**
309cfea8 1715 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1716 * @dev_priv: i915 private structure
1717 * @pipe: pipe to enable
040484af 1718 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1719 *
1720 * Enable @pipe, making sure that various hardware specific requirements
1721 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1722 *
1723 * @pipe should be %PIPE_A or %PIPE_B.
1724 *
1725 * Will wait until the pipe is actually running (i.e. first vblank) before
1726 * returning.
1727 */
040484af
JB		 1728static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1729 bool pch_port)
b24e7179 1730{
702e7a56
PZ		 1731 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1732 pipe);
1a240d4d 1733 enum pipe pch_transcoder;
b24e7179
JB		 1734 int reg;
1735 u32 val;
1736
58c6eaa2
DV		 1737 assert_planes_disabled(dev_priv, pipe);
1738 assert_sprites_disabled(dev_priv, pipe);
1739
681e5811 1740 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1741 pch_transcoder = TRANSCODER_A;
1742 else
1743 pch_transcoder = pipe;
1744
b24e7179
JB		 1745 /*
1746 * A pipe without a PLL won't actually be able to drive bits from
1747 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1748 * need the check.
1749 */
1750 if (!HAS_PCH_SPLIT(dev_priv->dev))
1751 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1752 else {
1753 if (pch_port) {
1754 /* if driving the PCH, we need FDI enabled */
cc391bbb 1755 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1756 assert_fdi_tx_pll_enabled(dev_priv,
1757 (enum pipe) cpu_transcoder);
040484af
JB		 1758 }
1759 /* FIXME: assert CPU port conditions for SNB+ */
1760 }
b24e7179 1761
702e7a56 1762 reg = PIPECONF(cpu_transcoder);
b24e7179 1763 val = I915_READ(reg);
00d70b15
CW		 1764 if (val & PIPECONF_ENABLE)
1765 return;
1766
1767 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1768 intel_wait_for_vblank(dev_priv->dev, pipe);
1769}
1770
1771/**
309cfea8 1772 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1773 * @dev_priv: i915 private structure
1774 * @pipe: pipe to disable
1775 *
1776 * Disable @pipe, making sure that various hardware specific requirements
1777 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1778 *
1779 * @pipe should be %PIPE_A or %PIPE_B.
1780 *
1781 * Will wait until the pipe has shut down before returning.
1782 */
1783static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1784 enum pipe pipe)
1785{
702e7a56
PZ		 1786 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1787 pipe);
b24e7179
JB		 1788 int reg;
1789 u32 val;
1790
1791 /*
1792 * Make sure planes won't keep trying to pump pixels to us,
1793 * or we might hang the display.
1794 */
1795 assert_planes_disabled(dev_priv, pipe);
19332d7a 1796 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1797
1798 /* Don't disable pipe A or pipe A PLLs if needed */
1799 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1800 return;
1801
702e7a56 1802 reg = PIPECONF(cpu_transcoder);
b24e7179 1803 val = I915_READ(reg);
00d70b15
CW		 1804 if ((val & PIPECONF_ENABLE) == 0)
1805 return;
1806
1807 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1808 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1809}
1810
d74362c9
KP		 1811/*
1812 * Plane regs are double buffered, going from enabled->disabled needs a
1813 * trigger in order to latch. The display address reg provides this.
1814 */
6f1d69b0 1815void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1816 enum plane plane)
1817{
14f86147
DL		 1818 if (dev_priv->info->gen >= 4)
1819 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1820 else
1821 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1822}
1823
b24e7179
JB		 1824/**
1825 * intel_enable_plane - enable a display plane on a given pipe
1826 * @dev_priv: i915 private structure
1827 * @plane: plane to enable
1828 * @pipe: pipe being fed
1829 *
1830 * Enable @plane on @pipe, making sure that @pipe is running first.
1831 */
1832static void intel_enable_plane(struct drm_i915_private *dev_priv,
1833 enum plane plane, enum pipe pipe)
1834{
1835 int reg;
1836 u32 val;
1837
1838 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1839 assert_pipe_enabled(dev_priv, pipe);
1840
1841 reg = DSPCNTR(plane);
1842 val = I915_READ(reg);
00d70b15
CW		 1843 if (val & DISPLAY_PLANE_ENABLE)
1844 return;
1845
1846 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1847 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1848 intel_wait_for_vblank(dev_priv->dev, pipe);
1849}
1850
b24e7179
JB		 1851/**
1852 * intel_disable_plane - disable a display plane
1853 * @dev_priv: i915 private structure
1854 * @plane: plane to disable
1855 * @pipe: pipe consuming the data
1856 *
1857 * Disable @plane; should be an independent operation.
1858 */
1859static void intel_disable_plane(struct drm_i915_private *dev_priv,
1860 enum plane plane, enum pipe pipe)
1861{
1862 int reg;
1863 u32 val;
1864
1865 reg = DSPCNTR(plane);
1866 val = I915_READ(reg);
00d70b15
CW		 1867 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1868 return;
1869
1870 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1871 intel_flush_display_plane(dev_priv, plane);
1872 intel_wait_for_vblank(dev_priv->dev, pipe);
1873}
1874
693db184
CW		 1875static bool need_vtd_wa(struct drm_device *dev)
1876{
1877#ifdef CONFIG_INTEL_IOMMU
1878 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1879 return true;
1880#endif
1881 return false;
1882}
1883
127bd2ac 1884int
48b956c5 1885intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1886 struct drm_i915_gem_object *obj,
919926ae 1887 struct intel_ring_buffer *pipelined)
6b95a207 1888{
ce453d81 1889 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1890 u32 alignment;
1891 int ret;
1892
05394f39 1893 switch (obj->tiling_mode) {
6b95a207 1894 case I915_TILING_NONE:
534843da
CW		 1895 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1896 alignment = 128 * 1024;
a6c45cf0 1897 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1898 alignment = 4 * 1024;
1899 else
1900 alignment = 64 * 1024;
6b95a207
KH		 1901 break;
1902 case I915_TILING_X:
1903 /* pin() will align the object as required by fence */
1904 alignment = 0;
1905 break;
1906 case I915_TILING_Y:
8bb6e959
DV		 1907 /* Despite that we check this in framebuffer_init userspace can
1908 * screw us over and change the tiling after the fact. Only
1909 * pinned buffers can't change their tiling. */
1910 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1911 return -EINVAL;
1912 default:
1913 BUG();
1914 }
1915
693db184
CW		 1916 /* Note that the w/a also requires 64 PTE of padding following the
1917 * bo. We currently fill all unused PTE with the shadow page and so
1918 * we should always have valid PTE following the scanout preventing
1919 * the VT-d warning.
1920 */
1921 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1922 alignment = 256 * 1024;
1923
ce453d81 1924 dev_priv->mm.interruptible = false;
2da3b9b9 1925 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1926 if (ret)
ce453d81 1927 goto err_interruptible;
6b95a207
KH		 1928
1929 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1930 * fence, whereas 965+ only requires a fence if using
1931 * framebuffer compression. For simplicity, we always install
1932 * a fence as the cost is not that onerous.
1933 */
06d98131 1934 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1935 if (ret)
1936 goto err_unpin;
1690e1eb 1937
9a5a53b3 1938 i915_gem_object_pin_fence(obj);
6b95a207 1939
ce453d81 1940 dev_priv->mm.interruptible = true;
6b95a207 1941 return 0;
48b956c5
CW		 1942
1943err_unpin:
1944 i915_gem_object_unpin(obj);
ce453d81
CW		 1945err_interruptible:
1946 dev_priv->mm.interruptible = true;
48b956c5 1947 return ret;
6b95a207
KH		 1948}
1949
1690e1eb
CW		 1950void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1951{
1952 i915_gem_object_unpin_fence(obj);
1953 i915_gem_object_unpin(obj);
1954}
1955
c2c75131
DV		 1956/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1957 * is assumed to be a power-of-two. */
bc752862
CW		 1958unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1959 unsigned int tiling_mode,
1960 unsigned int cpp,
1961 unsigned int pitch)
c2c75131 1962{
bc752862
CW		 1963 if (tiling_mode != I915_TILING_NONE) {
1964 unsigned int tile_rows, tiles;
c2c75131 1965
bc752862
CW		 1966 tile_rows = *y / 8;
1967 *y %= 8;
c2c75131 1968
bc752862
CW		 1969 tiles = *x / (512/cpp);
1970 *x %= 512/cpp;
1971
1972 return tile_rows * pitch * 8 + tiles * 4096;
1973 } else {
1974 unsigned int offset;
1975
1976 offset = *y * pitch + *x * cpp;
1977 *y = 0;
1978 *x = (offset & 4095) / cpp;
1979 return offset & -4096;
1980 }
c2c75131
DV		 1981}
1982
17638cd6
JB		 1983static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1984 int x, int y)
81255565
JB		 1985{
1986 struct drm_device *dev = crtc->dev;
1987 struct drm_i915_private *dev_priv = dev->dev_private;
1988 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1989 struct intel_framebuffer *intel_fb;
05394f39 1990 struct drm_i915_gem_object *obj;
81255565 1991 int plane = intel_crtc->plane;
e506a0c6 1992 unsigned long linear_offset;
81255565 1993 u32 dspcntr;
5eddb70b 1994 u32 reg;
81255565
JB		 1995
1996 switch (plane) {
1997 case 0:
1998 case 1:
1999 break;
2000 default:
84f44ce7 2001 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 2002 return -EINVAL;
2003 }
2004
2005 intel_fb = to_intel_framebuffer(fb);
2006 obj = intel_fb->obj;
81255565 2007
5eddb70b
CW		 2008 reg = DSPCNTR(plane);
2009 dspcntr = I915_READ(reg);
81255565
JB		 2010 /* Mask out pixel format bits in case we change it */
2011 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2012 switch (fb->pixel_format) {
2013 case DRM_FORMAT_C8:
81255565
JB		 2014 dspcntr |= DISPPLANE_8BPP;
2015 break;
57779d06
VS		 2016 case DRM_FORMAT_XRGB1555:
2017 case DRM_FORMAT_ARGB1555:
2018 dspcntr |= DISPPLANE_BGRX555;
81255565 2019 break;
57779d06
VS		 2020 case DRM_FORMAT_RGB565:
2021 dspcntr |= DISPPLANE_BGRX565;
2022 break;
2023 case DRM_FORMAT_XRGB8888:
2024 case DRM_FORMAT_ARGB8888:
2025 dspcntr |= DISPPLANE_BGRX888;
2026 break;
2027 case DRM_FORMAT_XBGR8888:
2028 case DRM_FORMAT_ABGR8888:
2029 dspcntr |= DISPPLANE_RGBX888;
2030 break;
2031 case DRM_FORMAT_XRGB2101010:
2032 case DRM_FORMAT_ARGB2101010:
2033 dspcntr |= DISPPLANE_BGRX101010;
2034 break;
2035 case DRM_FORMAT_XBGR2101010:
2036 case DRM_FORMAT_ABGR2101010:
2037 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2038 break;
2039 default:
baba133a 2040 BUG();
81255565 2041 }
57779d06 2042
a6c45cf0 2043 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2044 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2045 dspcntr |= DISPPLANE_TILED;
2046 else
2047 dspcntr &= ~DISPPLANE_TILED;
2048 }
2049
5eddb70b 2050 I915_WRITE(reg, dspcntr);
81255565 2051
e506a0c6 2052 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2053
c2c75131
DV		 2054 if (INTEL_INFO(dev)->gen >= 4) {
2055 intel_crtc->dspaddr_offset =
bc752862
CW		 2056 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2057 fb->bits_per_pixel / 8,
2058 fb->pitches[0]);
c2c75131
DV		 2059 linear_offset -= intel_crtc->dspaddr_offset;
2060 } else {
e506a0c6 2061 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2062 }
e506a0c6
DV		 2063
2064 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2065 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2066 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2067 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2068 I915_MODIFY_DISPBASE(DSPSURF(plane),
2069 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2070 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2071 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2072 } else
e506a0c6 2073 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2074 POSTING_READ(reg);
81255565 2075
17638cd6
JB		 2076 return 0;
2077}
2078
2079static int ironlake_update_plane(struct drm_crtc *crtc,
2080 struct drm_framebuffer *fb, int x, int y)
2081{
2082 struct drm_device *dev = crtc->dev;
2083 struct drm_i915_private *dev_priv = dev->dev_private;
2084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2085 struct intel_framebuffer *intel_fb;
2086 struct drm_i915_gem_object *obj;
2087 int plane = intel_crtc->plane;
e506a0c6 2088 unsigned long linear_offset;
17638cd6
JB		 2089 u32 dspcntr;
2090 u32 reg;
2091
2092 switch (plane) {
2093 case 0:
2094 case 1:
27f8227b 2095 case 2:
17638cd6
JB		 2096 break;
2097 default:
84f44ce7 2098 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2099 return -EINVAL;
2100 }
2101
2102 intel_fb = to_intel_framebuffer(fb);
2103 obj = intel_fb->obj;
2104
2105 reg = DSPCNTR(plane);
2106 dspcntr = I915_READ(reg);
2107 /* Mask out pixel format bits in case we change it */
2108 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2109 switch (fb->pixel_format) {
2110 case DRM_FORMAT_C8:
17638cd6
JB		 2111 dspcntr |= DISPPLANE_8BPP;
2112 break;
57779d06
VS		 2113 case DRM_FORMAT_RGB565:
2114 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2115 break;
57779d06
VS		 2116 case DRM_FORMAT_XRGB8888:
2117 case DRM_FORMAT_ARGB8888:
2118 dspcntr |= DISPPLANE_BGRX888;
2119 break;
2120 case DRM_FORMAT_XBGR8888:
2121 case DRM_FORMAT_ABGR8888:
2122 dspcntr |= DISPPLANE_RGBX888;
2123 break;
2124 case DRM_FORMAT_XRGB2101010:
2125 case DRM_FORMAT_ARGB2101010:
2126 dspcntr |= DISPPLANE_BGRX101010;
2127 break;
2128 case DRM_FORMAT_XBGR2101010:
2129 case DRM_FORMAT_ABGR2101010:
2130 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2131 break;
2132 default:
baba133a 2133 BUG();
17638cd6
JB		 2134 }
2135
2136 if (obj->tiling_mode != I915_TILING_NONE)
2137 dspcntr |= DISPPLANE_TILED;
2138 else
2139 dspcntr &= ~DISPPLANE_TILED;
2140
2141 /* must disable */
2142 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2143
2144 I915_WRITE(reg, dspcntr);
2145
e506a0c6 2146 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2147 intel_crtc->dspaddr_offset =
bc752862
CW		 2148 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2149 fb->bits_per_pixel / 8,
2150 fb->pitches[0]);
c2c75131 2151 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2152
e506a0c6
DV		 2153 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2154 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2155 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2156 I915_MODIFY_DISPBASE(DSPSURF(plane),
2157 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2158 if (IS_HASWELL(dev)) {
2159 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2160 } else {
2161 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2162 I915_WRITE(DSPLINOFF(plane), linear_offset);
2163 }
17638cd6
JB		 2164 POSTING_READ(reg);
2165
2166 return 0;
2167}
2168
2169/* Assume fb object is pinned & idle & fenced and just update base pointers */
2170static int
2171intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2172 int x, int y, enum mode_set_atomic state)
2173{
2174 struct drm_device *dev = crtc->dev;
2175 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2176
6b8e6ed0
CW		 2177 if (dev_priv->display.disable_fbc)
2178 dev_priv->display.disable_fbc(dev);
3dec0095 2179 intel_increase_pllclock(crtc);
81255565 2180
6b8e6ed0 2181 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2182}
2183
96a02917
VS		 2184void intel_display_handle_reset(struct drm_device *dev)
2185{
2186 struct drm_i915_private *dev_priv = dev->dev_private;
2187 struct drm_crtc *crtc;
2188
2189 /*
2190 * Flips in the rings have been nuked by the reset,
2191 * so complete all pending flips so that user space
2192 * will get its events and not get stuck.
2193 *
2194 * Also update the base address of all primary
2195 * planes to the the last fb to make sure we're
2196 * showing the correct fb after a reset.
2197 *
2198 * Need to make two loops over the crtcs so that we
2199 * don't try to grab a crtc mutex before the
2200 * pending_flip_queue really got woken up.
2201 */
2202
2203 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2204 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2205 enum plane plane = intel_crtc->plane;
2206
2207 intel_prepare_page_flip(dev, plane);
2208 intel_finish_page_flip_plane(dev, plane);
2209 }
2210
2211 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2212 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2213
2214 mutex_lock(&crtc->mutex);
2215 if (intel_crtc->active)
2216 dev_priv->display.update_plane(crtc, crtc->fb,
2217 crtc->x, crtc->y);
2218 mutex_unlock(&crtc->mutex);
2219 }
2220}
2221
14667a4b
CW		 2222static int
2223intel_finish_fb(struct drm_framebuffer *old_fb)
2224{
2225 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2226 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2227 bool was_interruptible = dev_priv->mm.interruptible;
2228 int ret;
2229
14667a4b
CW		 2230 /* Big Hammer, we also need to ensure that any pending
2231 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2232 * current scanout is retired before unpinning the old
2233 * framebuffer.
2234 *
2235 * This should only fail upon a hung GPU, in which case we
2236 * can safely continue.
2237 */
2238 dev_priv->mm.interruptible = false;
2239 ret = i915_gem_object_finish_gpu(obj);
2240 dev_priv->mm.interruptible = was_interruptible;
2241
2242 return ret;
2243}
2244
198598d0
VS		 2245static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2246{
2247 struct drm_device *dev = crtc->dev;
2248 struct drm_i915_master_private *master_priv;
2249 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2250
2251 if (!dev->primary->master)
2252 return;
2253
2254 master_priv = dev->primary->master->driver_priv;
2255 if (!master_priv->sarea_priv)
2256 return;
2257
2258 switch (intel_crtc->pipe) {
2259 case 0:
2260 master_priv->sarea_priv->pipeA_x = x;
2261 master_priv->sarea_priv->pipeA_y = y;
2262 break;
2263 case 1:
2264 master_priv->sarea_priv->pipeB_x = x;
2265 master_priv->sarea_priv->pipeB_y = y;
2266 break;
2267 default:
2268 break;
2269 }
2270}
2271
5c3b82e2 2272static int
3c4fdcfb 2273intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2274 struct drm_framebuffer *fb)
79e53945
JB		 2275{
2276 struct drm_device *dev = crtc->dev;
6b8e6ed0 2277 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2278 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2279 struct drm_framebuffer *old_fb;
5c3b82e2 2280 int ret;
79e53945
JB		 2281
2282 /* no fb bound */
94352cf9 2283 if (!fb) {
a5071c2f 2284 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2285 return 0;
2286 }
2287
7eb552ae 2288 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2289 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2290 plane_name(intel_crtc->plane),
2291 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2292 return -EINVAL;
79e53945
JB		 2293 }
2294
5c3b82e2 2295 mutex_lock(&dev->struct_mutex);
265db958 2296 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2297 to_intel_framebuffer(fb)->obj,
919926ae 2298 NULL);
5c3b82e2
CW		 2299 if (ret != 0) {
2300 mutex_unlock(&dev->struct_mutex);
a5071c2f 2301 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2302 return ret;
2303 }
79e53945 2304
94352cf9 2305 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2306 if (ret) {
94352cf9 2307 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2308 mutex_unlock(&dev->struct_mutex);
a5071c2f 2309 DRM_ERROR("failed to update base address\n");
4e6cfefc 2310 return ret;
79e53945 2311 }
3c4fdcfb 2312
94352cf9
DV		 2313 old_fb = crtc->fb;
2314 crtc->fb = fb;
6c4c86f5
DV		 2315 crtc->x = x;
2316 crtc->y = y;
94352cf9 2317
b7f1de28
CW		 2318 if (old_fb) {
2319 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2320 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2321 }
652c393a 2322
6b8e6ed0 2323 intel_update_fbc(dev);
5c3b82e2 2324 mutex_unlock(&dev->struct_mutex);
79e53945 2325
198598d0 2326 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2327
2328 return 0;
79e53945
JB		 2329}
2330
5e84e1a4
ZW		 2331static void intel_fdi_normal_train(struct drm_crtc *crtc)
2332{
2333 struct drm_device *dev = crtc->dev;
2334 struct drm_i915_private *dev_priv = dev->dev_private;
2335 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2336 int pipe = intel_crtc->pipe;
2337 u32 reg, temp;
2338
2339 /* enable normal train */
2340 reg = FDI_TX_CTL(pipe);
2341 temp = I915_READ(reg);
61e499bf 2342 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2343 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2344 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2345 } else {
2346 temp &= ~FDI_LINK_TRAIN_NONE;
2347 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2348 }
5e84e1a4
ZW		 2349 I915_WRITE(reg, temp);
2350
2351 reg = FDI_RX_CTL(pipe);
2352 temp = I915_READ(reg);
2353 if (HAS_PCH_CPT(dev)) {
2354 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2355 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2356 } else {
2357 temp &= ~FDI_LINK_TRAIN_NONE;
2358 temp |= FDI_LINK_TRAIN_NONE;
2359 }
2360 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2361
2362 /* wait one idle pattern time */
2363 POSTING_READ(reg);
2364 udelay(1000);
357555c0
JB		 2365
2366 /* IVB wants error correction enabled */
2367 if (IS_IVYBRIDGE(dev))
2368 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2369 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2370}
2371
1e833f40
DV		 2372static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2373{
2374 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2375}
2376
01a415fd
DV		 2377static void ivb_modeset_global_resources(struct drm_device *dev)
2378{
2379 struct drm_i915_private *dev_priv = dev->dev_private;
2380 struct intel_crtc *pipe_B_crtc =
2381 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2382 struct intel_crtc *pipe_C_crtc =
2383 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2384 uint32_t temp;
2385
1e833f40
DV		 2386 /*
2387 * When everything is off disable fdi C so that we could enable fdi B
2388 * with all lanes. Note that we don't care about enabled pipes without
2389 * an enabled pch encoder.
2390 */
2391 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2392 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2393 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2394 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2395
2396 temp = I915_READ(SOUTH_CHICKEN1);
2397 temp &= ~FDI_BC_BIFURCATION_SELECT;
2398 DRM_DEBUG_KMS("disabling fdi C rx\n");
2399 I915_WRITE(SOUTH_CHICKEN1, temp);
2400 }
2401}
2402
8db9d77b
ZW		 2403/* The FDI link training functions for ILK/Ibexpeak. */
2404static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2405{
2406 struct drm_device *dev = crtc->dev;
2407 struct drm_i915_private *dev_priv = dev->dev_private;
2408 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2409 int pipe = intel_crtc->pipe;
0fc932b8 2410 int plane = intel_crtc->plane;
5eddb70b 2411 u32 reg, temp, tries;
8db9d77b 2412
0fc932b8
JB		 2413 /* FDI needs bits from pipe & plane first */
2414 assert_pipe_enabled(dev_priv, pipe);
2415 assert_plane_enabled(dev_priv, plane);
2416
e1a44743
AJ		 2417 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2418 for train result */
5eddb70b
CW		 2419 reg = FDI_RX_IMR(pipe);
2420 temp = I915_READ(reg);
e1a44743
AJ		 2421 temp &= ~FDI_RX_SYMBOL_LOCK;
2422 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2423 I915_WRITE(reg, temp);
2424 I915_READ(reg);
e1a44743
AJ		 2425 udelay(150);
2426
8db9d77b 2427 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2428 reg = FDI_TX_CTL(pipe);
2429 temp = I915_READ(reg);
627eb5a3
DV		 2430 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2431 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2432 temp &= ~FDI_LINK_TRAIN_NONE;
2433 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2434 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2435
5eddb70b
CW		 2436 reg = FDI_RX_CTL(pipe);
2437 temp = I915_READ(reg);
8db9d77b
ZW		 2438 temp &= ~FDI_LINK_TRAIN_NONE;
2439 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2440 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2441
2442 POSTING_READ(reg);
8db9d77b
ZW		 2443 udelay(150);
2444
5b2adf89 2445 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2446 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2447 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2448 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2449
5eddb70b 2450 reg = FDI_RX_IIR(pipe);
e1a44743 2451 for (tries = 0; tries < 5; tries++) {
5eddb70b 2452 temp = I915_READ(reg);
8db9d77b
ZW		 2453 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2454
2455 if ((temp & FDI_RX_BIT_LOCK)) {
2456 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2457 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2458 break;
2459 }
8db9d77b 2460 }
e1a44743 2461 if (tries == 5)
5eddb70b 2462 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2463
2464 /* Train 2 */
5eddb70b
CW		 2465 reg = FDI_TX_CTL(pipe);
2466 temp = I915_READ(reg);
8db9d77b
ZW		 2467 temp &= ~FDI_LINK_TRAIN_NONE;
2468 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2469 I915_WRITE(reg, temp);
8db9d77b 2470
5eddb70b
CW		 2471 reg = FDI_RX_CTL(pipe);
2472 temp = I915_READ(reg);
8db9d77b
ZW		 2473 temp &= ~FDI_LINK_TRAIN_NONE;
2474 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2475 I915_WRITE(reg, temp);
8db9d77b 2476
5eddb70b
CW		 2477 POSTING_READ(reg);
2478 udelay(150);
8db9d77b 2479
5eddb70b 2480 reg = FDI_RX_IIR(pipe);
e1a44743 2481 for (tries = 0; tries < 5; tries++) {
5eddb70b 2482 temp = I915_READ(reg);
8db9d77b
ZW		 2483 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2484
2485 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2486 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2487 DRM_DEBUG_KMS("FDI train 2 done.\n");
2488 break;
2489 }
8db9d77b 2490 }
e1a44743 2491 if (tries == 5)
5eddb70b 2492 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2493
2494 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2495
8db9d77b
ZW		 2496}
2497
0206e353 2498static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2499 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2500 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2501 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2502 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2503};
2504
2505/* The FDI link training functions for SNB/Cougarpoint. */
2506static void gen6_fdi_link_train(struct drm_crtc *crtc)
2507{
2508 struct drm_device *dev = crtc->dev;
2509 struct drm_i915_private *dev_priv = dev->dev_private;
2510 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2511 int pipe = intel_crtc->pipe;
fa37d39e 2512 u32 reg, temp, i, retry;
8db9d77b 2513
e1a44743
AJ		 2514 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2515 for train result */
5eddb70b
CW		 2516 reg = FDI_RX_IMR(pipe);
2517 temp = I915_READ(reg);
e1a44743
AJ		 2518 temp &= ~FDI_RX_SYMBOL_LOCK;
2519 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2520 I915_WRITE(reg, temp);
2521
2522 POSTING_READ(reg);
e1a44743
AJ		 2523 udelay(150);
2524
8db9d77b 2525 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2526 reg = FDI_TX_CTL(pipe);
2527 temp = I915_READ(reg);
627eb5a3
DV		 2528 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2529 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2530 temp &= ~FDI_LINK_TRAIN_NONE;
2531 temp |= FDI_LINK_TRAIN_PATTERN_1;
2532 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2533 /* SNB-B */
2534 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2535 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2536
d74cf324
DV		 2537 I915_WRITE(FDI_RX_MISC(pipe),
2538 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2539
5eddb70b
CW		 2540 reg = FDI_RX_CTL(pipe);
2541 temp = I915_READ(reg);
8db9d77b
ZW		 2542 if (HAS_PCH_CPT(dev)) {
2543 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2544 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2545 } else {
2546 temp &= ~FDI_LINK_TRAIN_NONE;
2547 temp |= FDI_LINK_TRAIN_PATTERN_1;
2548 }
5eddb70b
CW		 2549 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2550
2551 POSTING_READ(reg);
8db9d77b
ZW		 2552 udelay(150);
2553
0206e353 2554 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2555 reg = FDI_TX_CTL(pipe);
2556 temp = I915_READ(reg);
8db9d77b
ZW		 2557 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2558 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2559 I915_WRITE(reg, temp);
2560
2561 POSTING_READ(reg);
8db9d77b
ZW		 2562 udelay(500);
2563
fa37d39e
SP		 2564 for (retry = 0; retry < 5; retry++) {
2565 reg = FDI_RX_IIR(pipe);
2566 temp = I915_READ(reg);
2567 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2568 if (temp & FDI_RX_BIT_LOCK) {
2569 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2570 DRM_DEBUG_KMS("FDI train 1 done.\n");
2571 break;
2572 }
2573 udelay(50);
8db9d77b 2574 }
fa37d39e
SP		 2575 if (retry < 5)
2576 break;
8db9d77b
ZW		 2577 }
2578 if (i == 4)
5eddb70b 2579 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2580
2581 /* Train 2 */
5eddb70b
CW		 2582 reg = FDI_TX_CTL(pipe);
2583 temp = I915_READ(reg);
8db9d77b
ZW		 2584 temp &= ~FDI_LINK_TRAIN_NONE;
2585 temp |= FDI_LINK_TRAIN_PATTERN_2;
2586 if (IS_GEN6(dev)) {
2587 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2588 /* SNB-B */
2589 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2590 }
5eddb70b 2591 I915_WRITE(reg, temp);
8db9d77b 2592
5eddb70b
CW		 2593 reg = FDI_RX_CTL(pipe);
2594 temp = I915_READ(reg);
8db9d77b
ZW		 2595 if (HAS_PCH_CPT(dev)) {
2596 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2597 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2598 } else {
2599 temp &= ~FDI_LINK_TRAIN_NONE;
2600 temp |= FDI_LINK_TRAIN_PATTERN_2;
2601 }
5eddb70b
CW		 2602 I915_WRITE(reg, temp);
2603
2604 POSTING_READ(reg);
8db9d77b
ZW		 2605 udelay(150);
2606
0206e353 2607 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2608 reg = FDI_TX_CTL(pipe);
2609 temp = I915_READ(reg);
8db9d77b
ZW		 2610 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2611 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2612 I915_WRITE(reg, temp);
2613
2614 POSTING_READ(reg);
8db9d77b
ZW		 2615 udelay(500);
2616
fa37d39e
SP		 2617 for (retry = 0; retry < 5; retry++) {
2618 reg = FDI_RX_IIR(pipe);
2619 temp = I915_READ(reg);
2620 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2621 if (temp & FDI_RX_SYMBOL_LOCK) {
2622 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2623 DRM_DEBUG_KMS("FDI train 2 done.\n");
2624 break;
2625 }
2626 udelay(50);
8db9d77b 2627 }
fa37d39e
SP		 2628 if (retry < 5)
2629 break;
8db9d77b
ZW		 2630 }
2631 if (i == 4)
5eddb70b 2632 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2633
2634 DRM_DEBUG_KMS("FDI train done.\n");
2635}
2636
357555c0
JB		 2637/* Manual link training for Ivy Bridge A0 parts */
2638static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2639{
2640 struct drm_device *dev = crtc->dev;
2641 struct drm_i915_private *dev_priv = dev->dev_private;
2642 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2643 int pipe = intel_crtc->pipe;
2644 u32 reg, temp, i;
2645
2646 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2647 for train result */
2648 reg = FDI_RX_IMR(pipe);
2649 temp = I915_READ(reg);
2650 temp &= ~FDI_RX_SYMBOL_LOCK;
2651 temp &= ~FDI_RX_BIT_LOCK;
2652 I915_WRITE(reg, temp);
2653
2654 POSTING_READ(reg);
2655 udelay(150);
2656
01a415fd
DV		 2657 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2658 I915_READ(FDI_RX_IIR(pipe)));
2659
357555c0
JB		 2660 /* enable CPU FDI TX and PCH FDI RX */
2661 reg = FDI_TX_CTL(pipe);
2662 temp = I915_READ(reg);
627eb5a3
DV		 2663 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2664 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
357555c0
JB		 2665 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2666 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2667 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2668 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2669 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2670 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2671
d74cf324
DV		 2672 I915_WRITE(FDI_RX_MISC(pipe),
2673 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2674
357555c0
JB		 2675 reg = FDI_RX_CTL(pipe);
2676 temp = I915_READ(reg);
2677 temp &= ~FDI_LINK_TRAIN_AUTO;
2678 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2679 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2680 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2681 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2682
2683 POSTING_READ(reg);
2684 udelay(150);
2685
0206e353 2686 for (i = 0; i < 4; i++) {
357555c0
JB		 2687 reg = FDI_TX_CTL(pipe);
2688 temp = I915_READ(reg);
2689 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2690 temp |= snb_b_fdi_train_param[i];
2691 I915_WRITE(reg, temp);
2692
2693 POSTING_READ(reg);
2694 udelay(500);
2695
2696 reg = FDI_RX_IIR(pipe);
2697 temp = I915_READ(reg);
2698 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2699
2700 if (temp & FDI_RX_BIT_LOCK ||
2701 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2702 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2703 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2704 break;
2705 }
2706 }
2707 if (i == 4)
2708 DRM_ERROR("FDI train 1 fail!\n");
2709
2710 /* Train 2 */
2711 reg = FDI_TX_CTL(pipe);
2712 temp = I915_READ(reg);
2713 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2714 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2715 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2716 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2717 I915_WRITE(reg, temp);
2718
2719 reg = FDI_RX_CTL(pipe);
2720 temp = I915_READ(reg);
2721 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2722 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2723 I915_WRITE(reg, temp);
2724
2725 POSTING_READ(reg);
2726 udelay(150);
2727
0206e353 2728 for (i = 0; i < 4; i++) {
357555c0
JB		 2729 reg = FDI_TX_CTL(pipe);
2730 temp = I915_READ(reg);
2731 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2732 temp |= snb_b_fdi_train_param[i];
2733 I915_WRITE(reg, temp);
2734
2735 POSTING_READ(reg);
2736 udelay(500);
2737
2738 reg = FDI_RX_IIR(pipe);
2739 temp = I915_READ(reg);
2740 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2741
2742 if (temp & FDI_RX_SYMBOL_LOCK) {
2743 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2744 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2745 break;
2746 }
2747 }
2748 if (i == 4)
2749 DRM_ERROR("FDI train 2 fail!\n");
2750
2751 DRM_DEBUG_KMS("FDI train done.\n");
2752}
2753
88cefb6c 2754static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2755{
88cefb6c 2756 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2757 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2758 int pipe = intel_crtc->pipe;
5eddb70b 2759 u32 reg, temp;
79e53945 2760
c64e311e 2761
c98e9dcf 2762 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2763 reg = FDI_RX_CTL(pipe);
2764 temp = I915_READ(reg);
627eb5a3
DV		 2765 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2766 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2767 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2768 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2769
2770 POSTING_READ(reg);
c98e9dcf
JB		 2771 udelay(200);
2772
2773 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2774 temp = I915_READ(reg);
2775 I915_WRITE(reg, temp | FDI_PCDCLK);
2776
2777 POSTING_READ(reg);
c98e9dcf
JB		 2778 udelay(200);
2779
20749730
PZ		 2780 /* Enable CPU FDI TX PLL, always on for Ironlake */
2781 reg = FDI_TX_CTL(pipe);
2782 temp = I915_READ(reg);
2783 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2784 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2785
20749730
PZ		 2786 POSTING_READ(reg);
2787 udelay(100);
6be4a607 2788 }
0e23b99d
JB		 2789}
2790
88cefb6c
DV		 2791static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2792{
2793 struct drm_device *dev = intel_crtc->base.dev;
2794 struct drm_i915_private *dev_priv = dev->dev_private;
2795 int pipe = intel_crtc->pipe;
2796 u32 reg, temp;
2797
2798 /* Switch from PCDclk to Rawclk */
2799 reg = FDI_RX_CTL(pipe);
2800 temp = I915_READ(reg);
2801 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2802
2803 /* Disable CPU FDI TX PLL */
2804 reg = FDI_TX_CTL(pipe);
2805 temp = I915_READ(reg);
2806 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2807
2808 POSTING_READ(reg);
2809 udelay(100);
2810
2811 reg = FDI_RX_CTL(pipe);
2812 temp = I915_READ(reg);
2813 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2814
2815 /* Wait for the clocks to turn off. */
2816 POSTING_READ(reg);
2817 udelay(100);
2818}
2819
0fc932b8
JB		 2820static void ironlake_fdi_disable(struct drm_crtc *crtc)
2821{
2822 struct drm_device *dev = crtc->dev;
2823 struct drm_i915_private *dev_priv = dev->dev_private;
2824 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2825 int pipe = intel_crtc->pipe;
2826 u32 reg, temp;
2827
2828 /* disable CPU FDI tx and PCH FDI rx */
2829 reg = FDI_TX_CTL(pipe);
2830 temp = I915_READ(reg);
2831 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2832 POSTING_READ(reg);
2833
2834 reg = FDI_RX_CTL(pipe);
2835 temp = I915_READ(reg);
2836 temp &= ~(0x7 << 16);
dfd07d72 2837 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2838 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2839
2840 POSTING_READ(reg);
2841 udelay(100);
2842
2843 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2844 if (HAS_PCH_IBX(dev)) {
2845 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2846 }
0fc932b8
JB		 2847
2848 /* still set train pattern 1 */
2849 reg = FDI_TX_CTL(pipe);
2850 temp = I915_READ(reg);
2851 temp &= ~FDI_LINK_TRAIN_NONE;
2852 temp |= FDI_LINK_TRAIN_PATTERN_1;
2853 I915_WRITE(reg, temp);
2854
2855 reg = FDI_RX_CTL(pipe);
2856 temp = I915_READ(reg);
2857 if (HAS_PCH_CPT(dev)) {
2858 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2859 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2860 } else {
2861 temp &= ~FDI_LINK_TRAIN_NONE;
2862 temp |= FDI_LINK_TRAIN_PATTERN_1;
2863 }
2864 /* BPC in FDI rx is consistent with that in PIPECONF */
2865 temp &= ~(0x07 << 16);
dfd07d72 2866 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2867 I915_WRITE(reg, temp);
2868
2869 POSTING_READ(reg);
2870 udelay(100);
2871}
2872
5bb61643
CW		 2873static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2874{
2875 struct drm_device *dev = crtc->dev;
2876 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2877 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2878 unsigned long flags;
2879 bool pending;
2880
10d83730
VS		 2881 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2882 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2883 return false;
2884
2885 spin_lock_irqsave(&dev->event_lock, flags);
2886 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2887 spin_unlock_irqrestore(&dev->event_lock, flags);
2888
2889 return pending;
2890}
2891
e6c3a2a6
CW		 2892static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2893{
0f91128d 2894 struct drm_device *dev = crtc->dev;
5bb61643 2895 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2896
2897 if (crtc->fb == NULL)
2898 return;
2899
2c10d571
DV		 2900 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2901
5bb61643
CW		 2902 wait_event(dev_priv->pending_flip_queue,
2903 !intel_crtc_has_pending_flip(crtc));
2904
0f91128d
CW		 2905 mutex_lock(&dev->struct_mutex);
2906 intel_finish_fb(crtc->fb);
2907 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2908}
2909
e615efe4
ED		 2910/* Program iCLKIP clock to the desired frequency */
2911static void lpt_program_iclkip(struct drm_crtc *crtc)
2912{
2913 struct drm_device *dev = crtc->dev;
2914 struct drm_i915_private *dev_priv = dev->dev_private;
2915 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2916 u32 temp;
2917
09153000
DV		 2918 mutex_lock(&dev_priv->dpio_lock);
2919
e615efe4
ED		 2920 /* It is necessary to ungate the pixclk gate prior to programming
2921 * the divisors, and gate it back when it is done.
2922 */
2923 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2924
2925 /* Disable SSCCTL */
2926 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2927 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2928 SBI_SSCCTL_DISABLE,
2929 SBI_ICLK);
e615efe4
ED		 2930
2931 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2932 if (crtc->mode.clock == 20000) {
2933 auxdiv = 1;
2934 divsel = 0x41;
2935 phaseinc = 0x20;
2936 } else {
2937 /* The iCLK virtual clock root frequency is in MHz,
2938 * but the crtc->mode.clock in in KHz. To get the divisors,
2939 * it is necessary to divide one by another, so we
2940 * convert the virtual clock precision to KHz here for higher
2941 * precision.
2942 */
2943 u32 iclk_virtual_root_freq = 172800 * 1000;
2944 u32 iclk_pi_range = 64;
2945 u32 desired_divisor, msb_divisor_value, pi_value;
2946
2947 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2948 msb_divisor_value = desired_divisor / iclk_pi_range;
2949 pi_value = desired_divisor % iclk_pi_range;
2950
2951 auxdiv = 0;
2952 divsel = msb_divisor_value - 2;
2953 phaseinc = pi_value;
2954 }
2955
2956 /* This should not happen with any sane values */
2957 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2958 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2959 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2960 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2961
2962 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2963 crtc->mode.clock,
2964 auxdiv,
2965 divsel,
2966 phasedir,
2967 phaseinc);
2968
2969 /* Program SSCDIVINTPHASE6 */
988d6ee8 2970 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2971 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2972 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2973 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2974 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2975 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2976 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2977 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2978
2979 /* Program SSCAUXDIV */
988d6ee8 2980 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2981 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2982 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2983 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2984
2985 /* Enable modulator and associated divider */
988d6ee8 2986 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2987 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2988 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2989
2990 /* Wait for initialization time */
2991 udelay(24);
2992
2993 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2994
2995 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2996}
2997
f67a559d
JB		 2998/*
2999 * Enable PCH resources required for PCH ports:
3000 * - PCH PLLs
3001 * - FDI training & RX/TX
3002 * - update transcoder timings
3003 * - DP transcoding bits
3004 * - transcoder
3005 */
3006static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3007{
3008 struct drm_device *dev = crtc->dev;
3009 struct drm_i915_private *dev_priv = dev->dev_private;
3010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3011 int pipe = intel_crtc->pipe;
ee7b9f93 3012 u32 reg, temp;
2c07245f 3013
ab9412ba 3014 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 3015
cd986abb
DV		 3016 /* Write the TU size bits before fdi link training, so that error
3017 * detection works. */
3018 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3019 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3020
c98e9dcf 3021 /* For PCH output, training FDI link */
674cf967 3022 dev_priv->display.fdi_link_train(crtc);
2c07245f 3023
572deb37
DV		 3024 /* XXX: pch pll's can be enabled any time before we enable the PCH
3025 * transcoder, and we actually should do this to not upset any PCH
3026 * transcoder that already use the clock when we share it.
3027 *
3028 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3029 * unconditionally resets the pll - we need that to have the right LVDS
3030 * enable sequence. */
b6b4e185 3031 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 3032
303b81e0 3033 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3034 u32 sel;
4b645f14 3035
c98e9dcf 3036 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3037 switch (pipe) {
3038 default:
3039 case 0:
3040 temp |= TRANSA_DPLL_ENABLE;
3041 sel = TRANSA_DPLLB_SEL;
3042 break;
3043 case 1:
3044 temp |= TRANSB_DPLL_ENABLE;
3045 sel = TRANSB_DPLLB_SEL;
3046 break;
3047 case 2:
3048 temp |= TRANSC_DPLL_ENABLE;
3049 sel = TRANSC_DPLLB_SEL;
3050 break;
d64311ab 3051 }
ee7b9f93
JB		 3052 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3053 temp |= sel;
3054 else
3055 temp &= ~sel;
c98e9dcf 3056 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3057 }
5eddb70b 3058
d9b6cb56
JB		 3059 /* set transcoder timing, panel must allow it */
3060 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3061 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3062 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3063 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3064
5eddb70b
CW		 3065 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3066 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3067 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3068 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3069
303b81e0 3070 intel_fdi_normal_train(crtc);
5e84e1a4 3071
c98e9dcf
JB		 3072 /* For PCH DP, enable TRANS_DP_CTL */
3073 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3074 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3075 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3076 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3077 reg = TRANS_DP_CTL(pipe);
3078 temp = I915_READ(reg);
3079 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3080 TRANS_DP_SYNC_MASK |
3081 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3082 temp |= (TRANS_DP_OUTPUT_ENABLE |
3083 TRANS_DP_ENH_FRAMING);
9325c9f0 3084 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3085
3086 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3087 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3088 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3089 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3090
3091 switch (intel_trans_dp_port_sel(crtc)) {
3092 case PCH_DP_B:
5eddb70b 3093 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3094 break;
3095 case PCH_DP_C:
5eddb70b 3096 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3097 break;
3098 case PCH_DP_D:
5eddb70b 3099 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3100 break;
3101 default:
e95d41e1 3102 BUG();
32f9d658 3103 }
2c07245f 3104
5eddb70b 3105 I915_WRITE(reg, temp);
6be4a607 3106 }
b52eb4dc 3107
b8a4f404 3108 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3109}
3110
1507e5bd
PZ		 3111static void lpt_pch_enable(struct drm_crtc *crtc)
3112{
3113 struct drm_device *dev = crtc->dev;
3114 struct drm_i915_private *dev_priv = dev->dev_private;
3115 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3116 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3117
ab9412ba 3118 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3119
8c52b5e8 3120 lpt_program_iclkip(crtc);
1507e5bd 3121
0540e488 3122 /* Set transcoder timing. */
daed2dbb
PZ		 3123 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3124 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3125 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
1507e5bd 3126
daed2dbb
PZ		 3127 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3128 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3129 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3130 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
1507e5bd 3131
937bb610 3132 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3133}
3134
ee7b9f93
JB		 3135static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3136{
3137 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3138
3139 if (pll == NULL)
3140 return;
3141
3142 if (pll->refcount == 0) {
3143 WARN(1, "bad PCH PLL refcount\n");
3144 return;
3145 }
3146
3147 --pll->refcount;
3148 intel_crtc->pch_pll = NULL;
3149}
3150
3151static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3152{
3153 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3154 struct intel_pch_pll *pll;
3155 int i;
3156
3157 pll = intel_crtc->pch_pll;
3158 if (pll) {
3159 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3160 intel_crtc->base.base.id, pll->pll_reg);
3161 goto prepare;
3162 }
3163
98b6bd99
DV		 3164 if (HAS_PCH_IBX(dev_priv->dev)) {
3165 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3166 i = intel_crtc->pipe;
3167 pll = &dev_priv->pch_plls[i];
3168
3169 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3170 intel_crtc->base.base.id, pll->pll_reg);
3171
3172 goto found;
3173 }
3174
ee7b9f93
JB		 3175 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3176 pll = &dev_priv->pch_plls[i];
3177
3178 /* Only want to check enabled timings first */
3179 if (pll->refcount == 0)
3180 continue;
3181
3182 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3183 fp == I915_READ(pll->fp0_reg)) {
3184 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3185 intel_crtc->base.base.id,
3186 pll->pll_reg, pll->refcount, pll->active);
3187
3188 goto found;
3189 }
3190 }
3191
3192 /* Ok no matching timings, maybe there's a free one? */
3193 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3194 pll = &dev_priv->pch_plls[i];
3195 if (pll->refcount == 0) {
3196 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3197 intel_crtc->base.base.id, pll->pll_reg);
3198 goto found;
3199 }
3200 }
3201
3202 return NULL;
3203
3204found:
3205 intel_crtc->pch_pll = pll;
3206 pll->refcount++;
84f44ce7 3207 DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
ee7b9f93
JB		 3208prepare: /* separate function? */
3209 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3210
e04c7350
CW		 3211 /* Wait for the clocks to stabilize before rewriting the regs */
3212 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3213 POSTING_READ(pll->pll_reg);
3214 udelay(150);
e04c7350
CW		 3215
3216 I915_WRITE(pll->fp0_reg, fp);
3217 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3218 pll->on = false;
3219 return pll;
3220}
3221
d4270e57
JB		 3222void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3223{
3224 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3225 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3226 u32 temp;
3227
3228 temp = I915_READ(dslreg);
3229 udelay(500);
3230 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3231 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3232 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3233 }
3234}
3235
b074cec8
JB		 3236static void ironlake_pfit_enable(struct intel_crtc *crtc)
3237{
3238 struct drm_device *dev = crtc->base.dev;
3239 struct drm_i915_private *dev_priv = dev->dev_private;
3240 int pipe = crtc->pipe;
3241
3242 if (crtc->config.pch_pfit.size &&
3243 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) {
3244 /* Force use of hard-coded filter coefficients
3245 * as some pre-programmed values are broken,
3246 * e.g. x201.
3247 */
3248 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3249 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3250 PF_PIPE_SEL_IVB(pipe));
3251 else
3252 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3253 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3254 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3255 }
3256}
3257
f67a559d
JB		 3258static void ironlake_crtc_enable(struct drm_crtc *crtc)
3259{
3260 struct drm_device *dev = crtc->dev;
3261 struct drm_i915_private *dev_priv = dev->dev_private;
3262 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3263 struct intel_encoder *encoder;
f67a559d
JB		 3264 int pipe = intel_crtc->pipe;
3265 int plane = intel_crtc->plane;
3266 u32 temp;
f67a559d 3267
08a48469
DV		 3268 WARN_ON(!crtc->enabled);
3269
f67a559d
JB		 3270 if (intel_crtc->active)
3271 return;
3272
3273 intel_crtc->active = true;
8664281b
PZ		 3274
3275 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3276 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3277
f67a559d
JB		 3278 intel_update_watermarks(dev);
3279
3280 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3281 temp = I915_READ(PCH_LVDS);
3282 if ((temp & LVDS_PORT_EN) == 0)
3283 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3284 }
3285
f67a559d 3286
5bfe2ac0 3287 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3288 /* Note: FDI PLL enabling _must_ be done before we enable the
3289 * cpu pipes, hence this is separate from all the other fdi/pch
3290 * enabling. */
88cefb6c 3291 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3292 } else {
3293 assert_fdi_tx_disabled(dev_priv, pipe);
3294 assert_fdi_rx_disabled(dev_priv, pipe);
3295 }
f67a559d 3296
bf49ec8c
DV		 3297 for_each_encoder_on_crtc(dev, crtc, encoder)
3298 if (encoder->pre_enable)
3299 encoder->pre_enable(encoder);
f67a559d
JB		 3300
3301 /* Enable panel fitting for LVDS */
b074cec8 3302 ironlake_pfit_enable(intel_crtc);
f67a559d 3303
9c54c0dd
JB		 3304 /*
3305 * On ILK+ LUT must be loaded before the pipe is running but with
3306 * clocks enabled
3307 */
3308 intel_crtc_load_lut(crtc);
3309
5bfe2ac0
DV		 3310 intel_enable_pipe(dev_priv, pipe,
3311 intel_crtc->config.has_pch_encoder);
f67a559d
JB		 3312 intel_enable_plane(dev_priv, plane, pipe);
3313
5bfe2ac0 3314 if (intel_crtc->config.has_pch_encoder)
f67a559d 3315 ironlake_pch_enable(crtc);
c98e9dcf 3316
d1ebd816 3317 mutex_lock(&dev->struct_mutex);
bed4a673 3318 intel_update_fbc(dev);
d1ebd816
BW		 3319 mutex_unlock(&dev->struct_mutex);
3320
6b383a7f 3321 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3322
fa5c73b1
DV		 3323 for_each_encoder_on_crtc(dev, crtc, encoder)
3324 encoder->enable(encoder);
61b77ddd
DV		 3325
3326 if (HAS_PCH_CPT(dev))
3327 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3328
3329 /*
3330 * There seems to be a race in PCH platform hw (at least on some
3331 * outputs) where an enabled pipe still completes any pageflip right
3332 * away (as if the pipe is off) instead of waiting for vblank. As soon
3333 * as the first vblank happend, everything works as expected. Hence just
3334 * wait for one vblank before returning to avoid strange things
3335 * happening.
3336 */
3337 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3338}
3339
4f771f10
PZ		 3340static void haswell_crtc_enable(struct drm_crtc *crtc)
3341{
3342 struct drm_device *dev = crtc->dev;
3343 struct drm_i915_private *dev_priv = dev->dev_private;
3344 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3345 struct intel_encoder *encoder;
3346 int pipe = intel_crtc->pipe;
3347 int plane = intel_crtc->plane;
4f771f10
PZ		 3348
3349 WARN_ON(!crtc->enabled);
3350
3351 if (intel_crtc->active)
3352 return;
3353
3354 intel_crtc->active = true;
8664281b
PZ		 3355
3356 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3357 if (intel_crtc->config.has_pch_encoder)
3358 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3359
4f771f10
PZ		 3360 intel_update_watermarks(dev);
3361
5bfe2ac0 3362 if (intel_crtc->config.has_pch_encoder)
04945641 3363 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3364
3365 for_each_encoder_on_crtc(dev, crtc, encoder)
3366 if (encoder->pre_enable)
3367 encoder->pre_enable(encoder);
3368
1f544388 3369 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3370
1f544388 3371 /* Enable panel fitting for eDP */
b074cec8 3372 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3373
3374 /*
3375 * On ILK+ LUT must be loaded before the pipe is running but with
3376 * clocks enabled
3377 */
3378 intel_crtc_load_lut(crtc);
3379
1f544388 3380 intel_ddi_set_pipe_settings(crtc);
8228c251 3381 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3382
5bfe2ac0
DV		 3383 intel_enable_pipe(dev_priv, pipe,
3384 intel_crtc->config.has_pch_encoder);
4f771f10
PZ		 3385 intel_enable_plane(dev_priv, plane, pipe);
3386
5bfe2ac0 3387 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3388 lpt_pch_enable(crtc);
4f771f10
PZ		 3389
3390 mutex_lock(&dev->struct_mutex);
3391 intel_update_fbc(dev);
3392 mutex_unlock(&dev->struct_mutex);
3393
3394 intel_crtc_update_cursor(crtc, true);
3395
3396 for_each_encoder_on_crtc(dev, crtc, encoder)
3397 encoder->enable(encoder);
3398
4f771f10
PZ		 3399 /*
3400 * There seems to be a race in PCH platform hw (at least on some
3401 * outputs) where an enabled pipe still completes any pageflip right
3402 * away (as if the pipe is off) instead of waiting for vblank. As soon
3403 * as the first vblank happend, everything works as expected. Hence just
3404 * wait for one vblank before returning to avoid strange things
3405 * happening.
3406 */
3407 intel_wait_for_vblank(dev, intel_crtc->pipe);
3408}
3409
6be4a607
JB		 3410static void ironlake_crtc_disable(struct drm_crtc *crtc)
3411{
3412 struct drm_device *dev = crtc->dev;
3413 struct drm_i915_private *dev_priv = dev->dev_private;
3414 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3415 struct intel_encoder *encoder;
6be4a607
JB		 3416 int pipe = intel_crtc->pipe;
3417 int plane = intel_crtc->plane;
5eddb70b 3418 u32 reg, temp;
b52eb4dc 3419
ef9c3aee 3420
f7abfe8b
CW		 3421 if (!intel_crtc->active)
3422 return;
3423
ea9d758d
DV		 3424 for_each_encoder_on_crtc(dev, crtc, encoder)
3425 encoder->disable(encoder);
3426
e6c3a2a6 3427 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3428 drm_vblank_off(dev, pipe);
6b383a7f 3429 intel_crtc_update_cursor(crtc, false);
5eddb70b 3430
b24e7179 3431 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3432
973d04f9
CW		 3433 if (dev_priv->cfb_plane == plane)
3434 intel_disable_fbc(dev);
2c07245f 3435
8664281b 3436 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
b24e7179 3437 intel_disable_pipe(dev_priv, pipe);
32f9d658 3438
6be4a607 3439 /* Disable PF */
9db4a9c7
JB		 3440 I915_WRITE(PF_CTL(pipe), 0);
3441 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3442
bf49ec8c
DV		 3443 for_each_encoder_on_crtc(dev, crtc, encoder)
3444 if (encoder->post_disable)
3445 encoder->post_disable(encoder);
2c07245f 3446
0fc932b8 3447 ironlake_fdi_disable(crtc);
249c0e64 3448
b8a4f404 3449 ironlake_disable_pch_transcoder(dev_priv, pipe);
8664281b 3450 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
913d8d11 3451
6be4a607
JB		 3452 if (HAS_PCH_CPT(dev)) {
3453 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3454 reg = TRANS_DP_CTL(pipe);
3455 temp = I915_READ(reg);
3456 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3457 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3458 I915_WRITE(reg, temp);
6be4a607
JB		 3459
3460 /* disable DPLL_SEL */
3461 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3462 switch (pipe) {
3463 case 0:
d64311ab 3464 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3465 break;
3466 case 1:
6be4a607 3467 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3468 break;
3469 case 2:
4b645f14 3470 /* C shares PLL A or B */
d64311ab 3471 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3472 break;
3473 default:
3474 BUG(); /* wtf */
3475 }
6be4a607 3476 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3477 }
e3421a18 3478
6be4a607 3479 /* disable PCH DPLL */
ee7b9f93 3480 intel_disable_pch_pll(intel_crtc);
8db9d77b 3481
88cefb6c 3482 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3483
f7abfe8b 3484 intel_crtc->active = false;
6b383a7f 3485 intel_update_watermarks(dev);
d1ebd816
BW		 3486
3487 mutex_lock(&dev->struct_mutex);
6b383a7f 3488 intel_update_fbc(dev);
d1ebd816 3489 mutex_unlock(&dev->struct_mutex);
6be4a607 3490}
1b3c7a47 3491
4f771f10 3492static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3493{
4f771f10
PZ		 3494 struct drm_device *dev = crtc->dev;
3495 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3496 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3497 struct intel_encoder *encoder;
3498 int pipe = intel_crtc->pipe;
3499 int plane = intel_crtc->plane;
3b117c8f 3500 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3501
4f771f10
PZ		 3502 if (!intel_crtc->active)
3503 return;
3504
3505 for_each_encoder_on_crtc(dev, crtc, encoder)
3506 encoder->disable(encoder);
3507
3508 intel_crtc_wait_for_pending_flips(crtc);
3509 drm_vblank_off(dev, pipe);
3510 intel_crtc_update_cursor(crtc, false);
3511
3512 intel_disable_plane(dev_priv, plane, pipe);
3513
3514 if (dev_priv->cfb_plane == plane)
3515 intel_disable_fbc(dev);
3516
8664281b
PZ		 3517 if (intel_crtc->config.has_pch_encoder)
3518 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3519 intel_disable_pipe(dev_priv, pipe);
3520
ad80a810 3521 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3522
f7708f78
PZ		 3523 /* XXX: Once we have proper panel fitter state tracking implemented with
3524 * hardware state read/check support we should switch to only disable
3525 * the panel fitter when we know it's used. */
3526 if (intel_using_power_well(dev)) {
3527 I915_WRITE(PF_CTL(pipe), 0);
3528 I915_WRITE(PF_WIN_SZ(pipe), 0);
3529 }
4f771f10 3530
1f544388 3531 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3532
3533 for_each_encoder_on_crtc(dev, crtc, encoder)
3534 if (encoder->post_disable)
3535 encoder->post_disable(encoder);
3536
88adfff1 3537 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3538 lpt_disable_pch_transcoder(dev_priv);
8664281b 3539 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3540 intel_ddi_fdi_disable(crtc);
83616634 3541 }
4f771f10
PZ		 3542
3543 intel_crtc->active = false;
3544 intel_update_watermarks(dev);
3545
3546 mutex_lock(&dev->struct_mutex);
3547 intel_update_fbc(dev);
3548 mutex_unlock(&dev->struct_mutex);
3549}
3550
ee7b9f93
JB		 3551static void ironlake_crtc_off(struct drm_crtc *crtc)
3552{
3553 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3554 intel_put_pch_pll(intel_crtc);
3555}
3556
6441ab5f
PZ		 3557static void haswell_crtc_off(struct drm_crtc *crtc)
3558{
a5c961d1
PZ		 3559 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3560
3561 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3562 * start using it. */
3b117c8f 3563 intel_crtc->config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
a5c961d1 3564
6441ab5f
PZ		 3565 intel_ddi_put_crtc_pll(crtc);
3566}
3567
02e792fb
DV		 3568static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3569{
02e792fb 3570 if (!enable && intel_crtc->overlay) {
23f09ce3 3571 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3572 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3573
23f09ce3 3574 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3575 dev_priv->mm.interruptible = false;
3576 (void) intel_overlay_switch_off(intel_crtc->overlay);
3577 dev_priv->mm.interruptible = true;
23f09ce3 3578 mutex_unlock(&dev->struct_mutex);
02e792fb 3579 }
02e792fb 3580
5dcdbcb0
CW		 3581 /* Let userspace switch the overlay on again. In most cases userspace
3582 * has to recompute where to put it anyway.
3583 */
02e792fb
DV		 3584}
3585
61bc95c1
EE		 3586/**
3587 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3588 * cursor plane briefly if not already running after enabling the display
3589 * plane.
3590 * This workaround avoids occasional blank screens when self refresh is
3591 * enabled.
3592 */
3593static void
3594g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3595{
3596 u32 cntl = I915_READ(CURCNTR(pipe));
3597
3598 if ((cntl & CURSOR_MODE) == 0) {
3599 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3600
3601 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3602 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3603 intel_wait_for_vblank(dev_priv->dev, pipe);
3604 I915_WRITE(CURCNTR(pipe), cntl);
3605 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3606 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3607 }
3608}
3609
2dd24552
JB		 3610static void i9xx_pfit_enable(struct intel_crtc *crtc)
3611{
3612 struct drm_device *dev = crtc->base.dev;
3613 struct drm_i915_private *dev_priv = dev->dev_private;
3614 struct intel_crtc_config *pipe_config = &crtc->config;
3615
3616 if (!(intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
3617 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)))
3618 return;
3619
3620 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3621 assert_pipe_disabled(dev_priv, crtc->pipe);
3622
3623 /*
3624 * Enable automatic panel scaling so that non-native modes
3625 * fill the screen. The panel fitter should only be
3626 * adjusted whilst the pipe is disabled, according to
3627 * register description and PRM.
3628 */
3629 DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n",
b074cec8
JB		 3630 pipe_config->gmch_pfit.control,
3631 pipe_config->gmch_pfit.pgm_ratios);
2dd24552 3632
b074cec8
JB		 3633 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3634 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3635
3636 /* Border color in case we don't scale up to the full screen. Black by
3637 * default, change to something else for debugging. */
3638 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3639}
3640
89b667f8
JB		 3641static void valleyview_crtc_enable(struct drm_crtc *crtc)
3642{
3643 struct drm_device *dev = crtc->dev;
3644 struct drm_i915_private *dev_priv = dev->dev_private;
3645 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3646 struct intel_encoder *encoder;
3647 int pipe = intel_crtc->pipe;
3648 int plane = intel_crtc->plane;
3649
3650 WARN_ON(!crtc->enabled);
3651
3652 if (intel_crtc->active)
3653 return;
3654
3655 intel_crtc->active = true;
3656 intel_update_watermarks(dev);
3657
3658 mutex_lock(&dev_priv->dpio_lock);
3659
3660 for_each_encoder_on_crtc(dev, crtc, encoder)
3661 if (encoder->pre_pll_enable)
3662 encoder->pre_pll_enable(encoder);
3663
3664 intel_enable_pll(dev_priv, pipe);
3665
3666 for_each_encoder_on_crtc(dev, crtc, encoder)
3667 if (encoder->pre_enable)
3668 encoder->pre_enable(encoder);
3669
3670 /* VLV wants encoder enabling _before_ the pipe is up. */
3671 for_each_encoder_on_crtc(dev, crtc, encoder)
3672 encoder->enable(encoder);
3673
2dd24552
JB		 3674 /* Enable panel fitting for eDP */
3675 i9xx_pfit_enable(intel_crtc);
3676
89b667f8
JB		 3677 intel_enable_pipe(dev_priv, pipe, false);
3678 intel_enable_plane(dev_priv, plane, pipe);
3679
3680 intel_crtc_load_lut(crtc);
3681 intel_update_fbc(dev);
3682
3683 /* Give the overlay scaler a chance to enable if it's on this pipe */
3684 intel_crtc_dpms_overlay(intel_crtc, true);
3685 intel_crtc_update_cursor(crtc, true);
3686
3687 mutex_unlock(&dev_priv->dpio_lock);
3688}
3689
0b8765c6 3690static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3691{
3692 struct drm_device *dev = crtc->dev;
79e53945
JB		 3693 struct drm_i915_private *dev_priv = dev->dev_private;
3694 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3695 struct intel_encoder *encoder;
79e53945 3696 int pipe = intel_crtc->pipe;
80824003 3697 int plane = intel_crtc->plane;
79e53945 3698
08a48469
DV		 3699 WARN_ON(!crtc->enabled);
3700
f7abfe8b
CW		 3701 if (intel_crtc->active)
3702 return;
3703
3704 intel_crtc->active = true;
6b383a7f
CW		 3705 intel_update_watermarks(dev);
3706
63d7bbe9 3707 intel_enable_pll(dev_priv, pipe);
9d6d9f19
MK		 3708
3709 for_each_encoder_on_crtc(dev, crtc, encoder)
3710 if (encoder->pre_enable)
3711 encoder->pre_enable(encoder);
3712
2dd24552
JB		 3713 /* Enable panel fitting for LVDS */
3714 i9xx_pfit_enable(intel_crtc);
3715
040484af 3716 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3717 intel_enable_plane(dev_priv, plane, pipe);
61bc95c1
EE		 3718 if (IS_G4X(dev))
3719 g4x_fixup_plane(dev_priv, pipe);
79e53945 3720
0b8765c6 3721 intel_crtc_load_lut(crtc);
bed4a673 3722 intel_update_fbc(dev);
79e53945 3723
0b8765c6
JB		 3724 /* Give the overlay scaler a chance to enable if it's on this pipe */
3725 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3726 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3727
fa5c73b1
DV		 3728 for_each_encoder_on_crtc(dev, crtc, encoder)
3729 encoder->enable(encoder);
0b8765c6 3730}
79e53945 3731
87476d63
DV		 3732static void i9xx_pfit_disable(struct intel_crtc *crtc)
3733{
3734 struct drm_device *dev = crtc->base.dev;
3735 struct drm_i915_private *dev_priv = dev->dev_private;
3736 enum pipe pipe;
3737 uint32_t pctl = I915_READ(PFIT_CONTROL);
3738
3739 assert_pipe_disabled(dev_priv, crtc->pipe);
3740
3741 if (INTEL_INFO(dev)->gen >= 4)
3742 pipe = (pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT;
3743 else
3744 pipe = PIPE_B;
3745
3746 if (pipe == crtc->pipe) {
3747 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", pctl);
3748 I915_WRITE(PFIT_CONTROL, 0);
3749 }
3750}
3751
0b8765c6
JB		 3752static void i9xx_crtc_disable(struct drm_crtc *crtc)
3753{
3754 struct drm_device *dev = crtc->dev;
3755 struct drm_i915_private *dev_priv = dev->dev_private;
3756 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3757 struct intel_encoder *encoder;
0b8765c6
JB		 3758 int pipe = intel_crtc->pipe;
3759 int plane = intel_crtc->plane;
ef9c3aee 3760
f7abfe8b
CW		 3761 if (!intel_crtc->active)
3762 return;
3763
ea9d758d
DV		 3764 for_each_encoder_on_crtc(dev, crtc, encoder)
3765 encoder->disable(encoder);
3766
0b8765c6 3767 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3768 intel_crtc_wait_for_pending_flips(crtc);
3769 drm_vblank_off(dev, pipe);
0b8765c6 3770 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3771 intel_crtc_update_cursor(crtc, false);
0b8765c6 3772
973d04f9
CW		 3773 if (dev_priv->cfb_plane == plane)
3774 intel_disable_fbc(dev);
79e53945 3775
b24e7179 3776 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3777 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3778
87476d63 3779 i9xx_pfit_disable(intel_crtc);
24a1f16d 3780
89b667f8
JB		 3781 for_each_encoder_on_crtc(dev, crtc, encoder)
3782 if (encoder->post_disable)
3783 encoder->post_disable(encoder);
3784
63d7bbe9 3785 intel_disable_pll(dev_priv, pipe);
0b8765c6 3786
f7abfe8b 3787 intel_crtc->active = false;
6b383a7f
CW		 3788 intel_update_fbc(dev);
3789 intel_update_watermarks(dev);
0b8765c6
JB		 3790}
3791
ee7b9f93
JB		 3792static void i9xx_crtc_off(struct drm_crtc *crtc)
3793{
3794}
3795
976f8a20
DV		 3796static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3797 bool enabled)
2c07245f
ZW		 3798{
3799 struct drm_device *dev = crtc->dev;
3800 struct drm_i915_master_private *master_priv;
3801 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3802 int pipe = intel_crtc->pipe;
79e53945
JB		 3803
3804 if (!dev->primary->master)
3805 return;
3806
3807 master_priv = dev->primary->master->driver_priv;
3808 if (!master_priv->sarea_priv)
3809 return;
3810
79e53945
JB		 3811 switch (pipe) {
3812 case 0:
3813 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3814 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3815 break;
3816 case 1:
3817 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3818 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3819 break;
3820 default:
9db4a9c7 3821 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3822 break;
3823 }
79e53945
JB		 3824}
3825
976f8a20
DV		 3826/**
3827 * Sets the power management mode of the pipe and plane.
3828 */
3829void intel_crtc_update_dpms(struct drm_crtc *crtc)
3830{
3831 struct drm_device *dev = crtc->dev;
3832 struct drm_i915_private *dev_priv = dev->dev_private;
3833 struct intel_encoder *intel_encoder;
3834 bool enable = false;
3835
3836 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3837 enable |= intel_encoder->connectors_active;
3838
3839 if (enable)
3840 dev_priv->display.crtc_enable(crtc);
3841 else
3842 dev_priv->display.crtc_disable(crtc);
3843
3844 intel_crtc_update_sarea(crtc, enable);
3845}
3846
cdd59983
CW		 3847static void intel_crtc_disable(struct drm_crtc *crtc)
3848{
cdd59983 3849 struct drm_device *dev = crtc->dev;
976f8a20 3850 struct drm_connector *connector;
ee7b9f93 3851 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3852 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3853
976f8a20
DV		 3854 /* crtc should still be enabled when we disable it. */
3855 WARN_ON(!crtc->enabled);
3856
7b9f35a6 3857 intel_crtc->eld_vld = false;
976f8a20
DV		 3858 dev_priv->display.crtc_disable(crtc);
3859 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3860 dev_priv->display.off(crtc);
3861
931872fc
CW		 3862 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3863 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3864
3865 if (crtc->fb) {
3866 mutex_lock(&dev->struct_mutex);
1690e1eb 3867 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3868 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3869 crtc->fb = NULL;
3870 }
3871
3872 /* Update computed state. */
3873 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3874 if (!connector->encoder || !connector->encoder->crtc)
3875 continue;
3876
3877 if (connector->encoder->crtc != crtc)
3878 continue;
3879
3880 connector->dpms = DRM_MODE_DPMS_OFF;
3881 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3882 }
3883}
3884
a261b246 3885void intel_modeset_disable(struct drm_device *dev)
79e53945 3886{
a261b246
DV		 3887 struct drm_crtc *crtc;
3888
3889 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3890 if (crtc->enabled)
3891 intel_crtc_disable(crtc);
3892 }
79e53945
JB		 3893}
3894
ea5b213a 3895void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3896{
4ef69c7a 3897 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3898
ea5b213a
CW		 3899 drm_encoder_cleanup(encoder);
3900 kfree(intel_encoder);
7e7d76c3
JB		 3901}
3902
5ab432ef
DV		 3903/* Simple dpms helper for encodres with just one connector, no cloning and only
3904 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3905 * state of the entire output pipe. */
3906void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3907{
5ab432ef
DV		 3908 if (mode == DRM_MODE_DPMS_ON) {
3909 encoder->connectors_active = true;
3910
b2cabb0e 3911 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3912 } else {
3913 encoder->connectors_active = false;
3914
b2cabb0e 3915 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3916 }
79e53945
JB		 3917}
3918
0a91ca29
DV		 3919/* Cross check the actual hw state with our own modeset state tracking (and it's
3920 * internal consistency). */
b980514c 3921static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3922{
0a91ca29
DV		 3923 if (connector->get_hw_state(connector)) {
3924 struct intel_encoder *encoder = connector->encoder;
3925 struct drm_crtc *crtc;
3926 bool encoder_enabled;
3927 enum pipe pipe;
3928
3929 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3930 connector->base.base.id,
3931 drm_get_connector_name(&connector->base));
3932
3933 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3934 "wrong connector dpms state\n");
3935 WARN(connector->base.encoder != &encoder->base,
3936 "active connector not linked to encoder\n");
3937 WARN(!encoder->connectors_active,
3938 "encoder->connectors_active not set\n");
3939
3940 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3941 WARN(!encoder_enabled, "encoder not enabled\n");
3942 if (WARN_ON(!encoder->base.crtc))
3943 return;
3944
3945 crtc = encoder->base.crtc;
3946
3947 WARN(!crtc->enabled, "crtc not enabled\n");
3948 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3949 WARN(pipe != to_intel_crtc(crtc)->pipe,
3950 "encoder active on the wrong pipe\n");
3951 }
79e53945
JB		 3952}
3953
5ab432ef
DV		 3954/* Even simpler default implementation, if there's really no special case to
3955 * consider. */
3956void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3957{
5ab432ef 3958 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3959
5ab432ef
DV		 3960 /* All the simple cases only support two dpms states. */
3961 if (mode != DRM_MODE_DPMS_ON)
3962 mode = DRM_MODE_DPMS_OFF;
d4270e57 3963
5ab432ef
DV		 3964 if (mode == connector->dpms)
3965 return;
3966
3967 connector->dpms = mode;
3968
3969 /* Only need to change hw state when actually enabled */
3970 if (encoder->base.crtc)
3971 intel_encoder_dpms(encoder, mode);
3972 else
8af6cf88 3973 WARN_ON(encoder->connectors_active != false);
0a91ca29 3974
b980514c 3975 intel_modeset_check_state(connector->dev);
79e53945
JB		 3976}
3977
f0947c37
DV		 3978/* Simple connector->get_hw_state implementation for encoders that support only
3979 * one connector and no cloning and hence the encoder state determines the state
3980 * of the connector. */
3981bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3982{
24929352 3983 enum pipe pipe = 0;
f0947c37 3984 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3985
f0947c37 3986 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3987}
3988
1857e1da
DV		 3989static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3990 struct intel_crtc_config *pipe_config)
3991{
3992 struct drm_i915_private *dev_priv = dev->dev_private;
3993 struct intel_crtc *pipe_B_crtc =
3994 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3995
3996 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3997 pipe_name(pipe), pipe_config->fdi_lanes);
3998 if (pipe_config->fdi_lanes > 4) {
3999 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4000 pipe_name(pipe), pipe_config->fdi_lanes);
4001 return false;
4002 }
4003
4004 if (IS_HASWELL(dev)) {
4005 if (pipe_config->fdi_lanes > 2) {
4006 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4007 pipe_config->fdi_lanes);
4008 return false;
4009 } else {
4010 return true;
4011 }
4012 }
4013
4014 if (INTEL_INFO(dev)->num_pipes == 2)
4015 return true;
4016
4017 /* Ivybridge 3 pipe is really complicated */
4018 switch (pipe) {
4019 case PIPE_A:
4020 return true;
4021 case PIPE_B:
4022 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4023 pipe_config->fdi_lanes > 2) {
4024 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4025 pipe_name(pipe), pipe_config->fdi_lanes);
4026 return false;
4027 }
4028 return true;
4029 case PIPE_C:
1e833f40 4030 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 4031 pipe_B_crtc->config.fdi_lanes <= 2) {
4032 if (pipe_config->fdi_lanes > 2) {
4033 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4034 pipe_name(pipe), pipe_config->fdi_lanes);
4035 return false;
4036 }
4037 } else {
4038 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4039 return false;
4040 }
4041 return true;
4042 default:
4043 BUG();
4044 }
4045}
4046
e29c22c0
DV		 4047#define RETRY 1
4048static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4049 struct intel_crtc_config *pipe_config)
877d48d5 4050{
1857e1da 4051 struct drm_device *dev = intel_crtc->base.dev;
877d48d5
DV		 4052 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4053 int target_clock, lane, link_bw;
e29c22c0 4054 bool setup_ok, needs_recompute = false;
877d48d5 4055
e29c22c0 4056retry:
877d48d5
DV		 4057 /* FDI is a binary signal running at ~2.7GHz, encoding
4058 * each output octet as 10 bits. The actual frequency
4059 * is stored as a divider into a 100MHz clock, and the
4060 * mode pixel clock is stored in units of 1KHz.
4061 * Hence the bw of each lane in terms of the mode signal
4062 * is:
4063 */
4064 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4065
4066 if (pipe_config->pixel_target_clock)
4067 target_clock = pipe_config->pixel_target_clock;
4068 else
4069 target_clock = adjusted_mode->clock;
4070
4071 lane = ironlake_get_lanes_required(target_clock, link_bw,
4072 pipe_config->pipe_bpp);
4073
4074 pipe_config->fdi_lanes = lane;
4075
4076 if (pipe_config->pixel_multiplier > 1)
4077 link_bw *= pipe_config->pixel_multiplier;
4078 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, target_clock,
4079 link_bw, &pipe_config->fdi_m_n);
1857e1da 4080
e29c22c0
DV		 4081 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4082 intel_crtc->pipe, pipe_config);
4083 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4084 pipe_config->pipe_bpp -= 2*3;
4085 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4086 pipe_config->pipe_bpp);
4087 needs_recompute = true;
4088 pipe_config->bw_constrained = true;
4089
4090 goto retry;
4091 }
4092
4093 if (needs_recompute)
4094 return RETRY;
4095
4096 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4097}
4098
e29c22c0
DV		 4099static int intel_crtc_compute_config(struct drm_crtc *crtc,
4100 struct intel_crtc_config *pipe_config)
79e53945 4101{
2c07245f 4102 struct drm_device *dev = crtc->dev;
b8cecdf5 4103 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4104
bad720ff 4105 if (HAS_PCH_SPLIT(dev)) {
2c07245f 4106 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 4107 if (pipe_config->requested_mode.clock * 3
4108 > IRONLAKE_FDI_FREQ * 4)
e29c22c0 4109 return -EINVAL;
2c07245f 4110 }
89749350 4111
f9bef081
DV		 4112 /* All interlaced capable intel hw wants timings in frames. Note though
4113 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4114 * timings, so we need to be careful not to clobber these.*/
7ae89233 4115 if (!pipe_config->timings_set)
f9bef081 4116 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 4117
44f46b42
CW		 4118 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
4119 * with a hsync front porch of 0.
4120 */
4121 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4122 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4123 return -EINVAL;
44f46b42 4124
bd080ee5 4125 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4126 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4127 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4128 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4129 * for lvds. */
4130 pipe_config->pipe_bpp = 8*3;
4131 }
4132
877d48d5 4133 if (pipe_config->has_pch_encoder)
1857e1da 4134 return ironlake_fdi_compute_config(to_intel_crtc(crtc), pipe_config);
877d48d5 4135
e29c22c0 4136 return 0;
79e53945
JB		 4137}
4138
25eb05fc
JB		 4139static int valleyview_get_display_clock_speed(struct drm_device *dev)
4140{
4141 return 400000; /* FIXME */
4142}
4143
e70236a8
JB		 4144static int i945_get_display_clock_speed(struct drm_device *dev)
4145{
4146 return 400000;
4147}
79e53945 4148
e70236a8 4149static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4150{
e70236a8
JB		 4151 return 333000;
4152}
79e53945 4153
e70236a8
JB		 4154static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4155{
4156 return 200000;
4157}
79e53945 4158
e70236a8
JB		 4159static int i915gm_get_display_clock_speed(struct drm_device *dev)
4160{
4161 u16 gcfgc = 0;
79e53945 4162
e70236a8
JB		 4163 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4164
4165 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4166 return 133000;
4167 else {
4168 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4169 case GC_DISPLAY_CLOCK_333_MHZ:
4170 return 333000;
4171 default:
4172 case GC_DISPLAY_CLOCK_190_200_MHZ:
4173 return 190000;
79e53945 4174 }
e70236a8
JB		 4175 }
4176}
4177
4178static int i865_get_display_clock_speed(struct drm_device *dev)
4179{
4180 return 266000;
4181}
4182
4183static int i855_get_display_clock_speed(struct drm_device *dev)
4184{
4185 u16 hpllcc = 0;
4186 /* Assume that the hardware is in the high speed state. This
4187 * should be the default.
4188 */
4189 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4190 case GC_CLOCK_133_200:
4191 case GC_CLOCK_100_200:
4192 return 200000;
4193 case GC_CLOCK_166_250:
4194 return 250000;
4195 case GC_CLOCK_100_133:
79e53945 4196 return 133000;
e70236a8 4197 }
79e53945 4198
e70236a8
JB		 4199 /* Shouldn't happen */
4200 return 0;
4201}
79e53945 4202
e70236a8
JB		 4203static int i830_get_display_clock_speed(struct drm_device *dev)
4204{
4205 return 133000;
79e53945
JB		 4206}
4207
2c07245f 4208static void
e69d0bc1 4209intel_reduce_ratio(uint32_t *num, uint32_t *den)
2c07245f
ZW		 4210{
4211 while (*num > 0xffffff || *den > 0xffffff) {
4212 *num >>= 1;
4213 *den >>= 1;
4214 }
4215}
4216
e69d0bc1
DV		 4217void
4218intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4219 int pixel_clock, int link_clock,
4220 struct intel_link_m_n *m_n)
2c07245f 4221{
e69d0bc1 4222 m_n->tu = 64;
22ed1113
CW		 4223 m_n->gmch_m = bits_per_pixel * pixel_clock;
4224 m_n->gmch_n = link_clock * nlanes * 8;
e69d0bc1 4225 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
22ed1113
CW		 4226 m_n->link_m = pixel_clock;
4227 m_n->link_n = link_clock;
e69d0bc1 4228 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4229}
4230
a7615030
CW		 4231static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4232{
72bbe58c
KP		 4233 if (i915_panel_use_ssc >= 0)
4234 return i915_panel_use_ssc != 0;
4235 return dev_priv->lvds_use_ssc
435793df 4236 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4237}
4238
a0c4da24
JB		 4239static int vlv_get_refclk(struct drm_crtc *crtc)
4240{
4241 struct drm_device *dev = crtc->dev;
4242 struct drm_i915_private *dev_priv = dev->dev_private;
4243 int refclk = 27000; /* for DP & HDMI */
4244
4245 return 100000; /* only one validated so far */
4246
4247 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4248 refclk = 96000;
4249 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4250 if (intel_panel_use_ssc(dev_priv))
4251 refclk = 100000;
4252 else
4253 refclk = 96000;
4254 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4255 refclk = 100000;
4256 }
4257
4258 return refclk;
4259}
4260
c65d77d8
JB		 4261static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4262{
4263 struct drm_device *dev = crtc->dev;
4264 struct drm_i915_private *dev_priv = dev->dev_private;
4265 int refclk;
4266
a0c4da24
JB		 4267 if (IS_VALLEYVIEW(dev)) {
4268 refclk = vlv_get_refclk(crtc);
4269 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 4270 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4271 refclk = dev_priv->lvds_ssc_freq * 1000;
4272 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4273 refclk / 1000);
4274 } else if (!IS_GEN2(dev)) {
4275 refclk = 96000;
4276 } else {
4277 refclk = 48000;
4278 }
4279
4280 return refclk;
4281}
4282
f47709a9 4283static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc *crtc)
c65d77d8 4284{
f47709a9
DV		 4285 unsigned dotclock = crtc->config.adjusted_mode.clock;
4286 struct dpll *clock = &crtc->config.dpll;
4287
c65d77d8
JB		 4288 /* SDVO TV has fixed PLL values depend on its clock range,
4289 this mirrors vbios setting. */
f47709a9 4290 if (dotclock >= 100000 && dotclock < 140500) {
c65d77d8
JB		 4291 clock->p1 = 2;
4292 clock->p2 = 10;
4293 clock->n = 3;
4294 clock->m1 = 16;
4295 clock->m2 = 8;
f47709a9 4296 } else if (dotclock >= 140500 && dotclock <= 200000) {
c65d77d8
JB		 4297 clock->p1 = 1;
4298 clock->p2 = 10;
4299 clock->n = 6;
4300 clock->m1 = 12;
4301 clock->m2 = 8;
4302 }
f47709a9
DV		 4303
4304 crtc->config.clock_set = true;
c65d77d8
JB		 4305}
4306
7429e9d4
DV		 4307static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4308{
4309 return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2;
4310}
4311
4312static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4313{
4314 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4315}
4316
f47709a9 4317static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4318 intel_clock_t *reduced_clock)
4319{
f47709a9 4320 struct drm_device *dev = crtc->base.dev;
a7516a05 4321 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4322 int pipe = crtc->pipe;
a7516a05
JB		 4323 u32 fp, fp2 = 0;
4324
4325 if (IS_PINEVIEW(dev)) {
7429e9d4 4326 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4327 if (reduced_clock)
7429e9d4 4328 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4329 } else {
7429e9d4 4330 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4331 if (reduced_clock)
7429e9d4 4332 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4333 }
4334
4335 I915_WRITE(FP0(pipe), fp);
4336
f47709a9
DV		 4337 crtc->lowfreq_avail = false;
4338 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4339 reduced_clock && i915_powersave) {
4340 I915_WRITE(FP1(pipe), fp2);
f47709a9 4341 crtc->lowfreq_avail = true;
a7516a05
JB		 4342 } else {
4343 I915_WRITE(FP1(pipe), fp);
4344 }
4345}
4346
89b667f8
JB		 4347static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4348{
4349 u32 reg_val;
4350
4351 /*
4352 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4353 * and set it to a reasonable value instead.
4354 */
4355 reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4356 reg_val &= 0xffffff00;
4357 reg_val |= 0x00000030;
4358 intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4359
4360 reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4361 reg_val &= 0x8cffffff;
4362 reg_val = 0x8c000000;
4363 intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4364
4365 reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4366 reg_val &= 0xffffff00;
4367 intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4368
4369 reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4370 reg_val &= 0x00ffffff;
4371 reg_val |= 0xb0000000;
4372 intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4373}
4374
03afc4a2
DV		 4375static void intel_dp_set_m_n(struct intel_crtc *crtc)
4376{
4377 if (crtc->config.has_pch_encoder)
4378 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4379 else
4380 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4381}
4382
f47709a9 4383static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4384{
f47709a9 4385 struct drm_device *dev = crtc->base.dev;
a0c4da24 4386 struct drm_i915_private *dev_priv = dev->dev_private;
89b667f8
JB		 4387 struct drm_display_mode *adjusted_mode =
4388 &crtc->config.adjusted_mode;
4389 struct intel_encoder *encoder;
f47709a9 4390 int pipe = crtc->pipe;
89b667f8 4391 u32 dpll, mdiv;
a0c4da24 4392 u32 bestn, bestm1, bestm2, bestp1, bestp2;
89b667f8 4393 bool is_hdmi;
198a037f 4394 u32 coreclk, reg_val, dpll_md;
a0c4da24 4395
09153000
DV		 4396 mutex_lock(&dev_priv->dpio_lock);
4397
89b667f8 4398 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
a0c4da24 4399
f47709a9
DV		 4400 bestn = crtc->config.dpll.n;
4401 bestm1 = crtc->config.dpll.m1;
4402 bestm2 = crtc->config.dpll.m2;
4403 bestp1 = crtc->config.dpll.p1;
4404 bestp2 = crtc->config.dpll.p2;
a0c4da24 4405
89b667f8
JB		 4406 /* See eDP HDMI DPIO driver vbios notes doc */
4407
4408 /* PLL B needs special handling */
4409 if (pipe)
4410 vlv_pllb_recal_opamp(dev_priv);
4411
4412 /* Set up Tx target for periodic Rcomp update */
4413 intel_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4414
4415 /* Disable target IRef on PLL */
4416 reg_val = intel_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4417 reg_val &= 0x00ffffff;
4418 intel_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4419
4420 /* Disable fast lock */
4421 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4422
4423 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4424 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4425 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4426 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4427 mdiv |= (1 << DPIO_K_SHIFT);
89b667f8
JB		 4428 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI) ||
4429 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4430 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4431 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
a0c4da24
JB		 4432 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4433
89b667f8
JB		 4434 mdiv |= DPIO_ENABLE_CALIBRATION;
4435 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4436
89b667f8
JB		 4437 /* Set HBR and RBR LPF coefficients */
4438 if (adjusted_mode->clock == 162000 ||
4439 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4440 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4441 0x005f0021);
4442 else
4443 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4444 0x00d0000f);
4445
4446 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4447 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4448 /* Use SSC source */
4449 if (!pipe)
4450 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4451 0x0df40000);
4452 else
4453 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4454 0x0df70000);
4455 } else { /* HDMI or VGA */
4456 /* Use bend source */
4457 if (!pipe)
4458 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4459 0x0df70000);
4460 else
4461 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4462 0x0df40000);
4463 }
a0c4da24 4464
89b667f8
JB		 4465 coreclk = intel_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4466 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4467 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4468 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4469 coreclk |= 0x01000000;
4470 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4471
89b667f8 4472 intel_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4473
89b667f8
JB		 4474 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4475 if (encoder->pre_pll_enable)
4476 encoder->pre_pll_enable(encoder);
2a8f64ca 4477
89b667f8
JB		 4478 /* Enable DPIO clock input */
4479 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4480 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4481 if (pipe)
4482 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
2a8f64ca 4483
89b667f8 4484 dpll |= DPLL_VCO_ENABLE;
2a8f64ca 4485 I915_WRITE(DPLL(pipe), dpll);
2a8f64ca
VP		 4486 POSTING_READ(DPLL(pipe));
4487 udelay(150);
a0c4da24 4488
89b667f8
JB		 4489 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4490 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4491
198a037f
DV		 4492 dpll_md = 0;
4493 if (crtc->config.pixel_multiplier > 1) {
4494 dpll_md = (crtc->config.pixel_multiplier - 1)
4495 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
2a8f64ca 4496 }
198a037f
DV		 4497 I915_WRITE(DPLL_MD(pipe), dpll_md);
4498 POSTING_READ(DPLL_MD(pipe));
f47709a9 4499
89b667f8
JB		 4500 if (crtc->config.has_dp_encoder)
4501 intel_dp_set_m_n(crtc);
09153000
DV		 4502
4503 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4504}
4505
f47709a9
DV		 4506static void i9xx_update_pll(struct intel_crtc *crtc,
4507 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4508 int num_connectors)
4509{
f47709a9 4510 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4511 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4512 struct intel_encoder *encoder;
f47709a9 4513 int pipe = crtc->pipe;
eb1cbe48
DV		 4514 u32 dpll;
4515 bool is_sdvo;
f47709a9 4516 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4517
f47709a9 4518 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4519
f47709a9
DV		 4520 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4521 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4522
4523 dpll = DPLL_VGA_MODE_DIS;
4524
f47709a9 4525 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4526 dpll |= DPLLB_MODE_LVDS;
4527 else
4528 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4529
198a037f
DV		 4530 if ((crtc->config.pixel_multiplier > 1) &&
4531 (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
4532 dpll |= (crtc->config.pixel_multiplier - 1)
4533 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4534 }
198a037f
DV		 4535
4536 if (is_sdvo)
4537 dpll |= DPLL_DVO_HIGH_SPEED;
4538
f47709a9 4539 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
eb1cbe48
DV		 4540 dpll |= DPLL_DVO_HIGH_SPEED;
4541
4542 /* compute bitmask from p1 value */
4543 if (IS_PINEVIEW(dev))
4544 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4545 else {
4546 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4547 if (IS_G4X(dev) && reduced_clock)
4548 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4549 }
4550 switch (clock->p2) {
4551 case 5:
4552 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4553 break;
4554 case 7:
4555 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4556 break;
4557 case 10:
4558 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4559 break;
4560 case 14:
4561 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4562 break;
4563 }
4564 if (INTEL_INFO(dev)->gen >= 4)
4565 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4566
f47709a9 4567 if (is_sdvo && intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
eb1cbe48 4568 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4569 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
eb1cbe48
DV		 4570 /* XXX: just matching BIOS for now */
4571 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4572 dpll |= 3;
f47709a9 4573 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4574 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4575 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4576 else
4577 dpll |= PLL_REF_INPUT_DREFCLK;
4578
4579 dpll |= DPLL_VCO_ENABLE;
4580 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4581 POSTING_READ(DPLL(pipe));
4582 udelay(150);
4583
f47709a9 4584 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4585 if (encoder->pre_pll_enable)
4586 encoder->pre_pll_enable(encoder);
eb1cbe48 4587
f47709a9
DV		 4588 if (crtc->config.has_dp_encoder)
4589 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4590
4591 I915_WRITE(DPLL(pipe), dpll);
4592
4593 /* Wait for the clocks to stabilize. */
4594 POSTING_READ(DPLL(pipe));
4595 udelay(150);
4596
4597 if (INTEL_INFO(dev)->gen >= 4) {
198a037f
DV		 4598 u32 dpll_md = 0;
4599 if (crtc->config.pixel_multiplier > 1) {
4600 dpll_md = (crtc->config.pixel_multiplier - 1)
4601 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
eb1cbe48 4602 }
198a037f 4603 I915_WRITE(DPLL_MD(pipe), dpll_md);
eb1cbe48
DV		 4604 } else {
4605 /* The pixel multiplier can only be updated once the
4606 * DPLL is enabled and the clocks are stable.
4607 *
4608 * So write it again.
4609 */
4610 I915_WRITE(DPLL(pipe), dpll);
4611 }
4612}
4613
f47709a9 4614static void i8xx_update_pll(struct intel_crtc *crtc,
eb1cbe48 4615 struct drm_display_mode *adjusted_mode,
f47709a9 4616 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4617 int num_connectors)
4618{
f47709a9 4619 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4620 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4621 struct intel_encoder *encoder;
f47709a9 4622 int pipe = crtc->pipe;
eb1cbe48 4623 u32 dpll;
f47709a9 4624 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4625
f47709a9 4626 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4627
eb1cbe48
DV		 4628 dpll = DPLL_VGA_MODE_DIS;
4629
f47709a9 4630 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4631 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4632 } else {
4633 if (clock->p1 == 2)
4634 dpll |= PLL_P1_DIVIDE_BY_TWO;
4635 else
4636 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4637 if (clock->p2 == 4)
4638 dpll |= PLL_P2_DIVIDE_BY_4;
4639 }
4640
f47709a9 4641 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4642 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4643 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4644 else
4645 dpll |= PLL_REF_INPUT_DREFCLK;
4646
4647 dpll |= DPLL_VCO_ENABLE;
4648 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4649 POSTING_READ(DPLL(pipe));
4650 udelay(150);
4651
f47709a9 4652 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4653 if (encoder->pre_pll_enable)
4654 encoder->pre_pll_enable(encoder);
eb1cbe48 4655
5b5896e4
DV		 4656 I915_WRITE(DPLL(pipe), dpll);
4657
4658 /* Wait for the clocks to stabilize. */
4659 POSTING_READ(DPLL(pipe));
4660 udelay(150);
4661
eb1cbe48
DV		 4662 /* The pixel multiplier can only be updated once the
4663 * DPLL is enabled and the clocks are stable.
4664 *
4665 * So write it again.
4666 */
4667 I915_WRITE(DPLL(pipe), dpll);
4668}
4669
b0e77b9c
PZ		 4670static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4671 struct drm_display_mode *mode,
4672 struct drm_display_mode *adjusted_mode)
4673{
4674 struct drm_device *dev = intel_crtc->base.dev;
4675 struct drm_i915_private *dev_priv = dev->dev_private;
4676 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4677 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4d8a62ea
DV		 4678 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4679
4680 /* We need to be careful not to changed the adjusted mode, for otherwise
4681 * the hw state checker will get angry at the mismatch. */
4682 crtc_vtotal = adjusted_mode->crtc_vtotal;
4683 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4684
4685 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4686 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4687 crtc_vtotal -= 1;
4688 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4689 vsyncshift = adjusted_mode->crtc_hsync_start
4690 - adjusted_mode->crtc_htotal / 2;
4691 } else {
4692 vsyncshift = 0;
4693 }
4694
4695 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4696 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4697
fe2b8f9d 4698 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4699 (adjusted_mode->crtc_hdisplay - 1) |
4700 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4701 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4702 (adjusted_mode->crtc_hblank_start - 1) |
4703 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4704 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4705 (adjusted_mode->crtc_hsync_start - 1) |
4706 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4707
fe2b8f9d 4708 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4709 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4710 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4711 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4712 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4713 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4714 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4715 (adjusted_mode->crtc_vsync_start - 1) |
4716 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4717
b5e508d4
PZ		 4718 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4719 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4720 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4721 * bits. */
4722 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4723 (pipe == PIPE_B || pipe == PIPE_C))
4724 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4725
b0e77b9c
PZ		 4726 /* pipesrc controls the size that is scaled from, which should
4727 * always be the user's requested size.
4728 */
4729 I915_WRITE(PIPESRC(pipe),
4730 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4731}
4732
1bd1bd80
DV		 4733static void intel_get_pipe_timings(struct intel_crtc *crtc,
4734 struct intel_crtc_config *pipe_config)
4735{
4736 struct drm_device *dev = crtc->base.dev;
4737 struct drm_i915_private *dev_priv = dev->dev_private;
4738 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4739 uint32_t tmp;
4740
4741 tmp = I915_READ(HTOTAL(cpu_transcoder));
4742 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4743 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4744 tmp = I915_READ(HBLANK(cpu_transcoder));
4745 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4746 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4747 tmp = I915_READ(HSYNC(cpu_transcoder));
4748 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4749 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4750
4751 tmp = I915_READ(VTOTAL(cpu_transcoder));
4752 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4753 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4754 tmp = I915_READ(VBLANK(cpu_transcoder));
4755 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4756 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4757 tmp = I915_READ(VSYNC(cpu_transcoder));
4758 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4759 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4760
4761 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4762 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4763 pipe_config->adjusted_mode.crtc_vtotal += 1;
4764 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4765 }
4766
4767 tmp = I915_READ(PIPESRC(crtc->pipe));
4768 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4769 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4770}
4771
84b046f3
DV		 4772static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4773{
4774 struct drm_device *dev = intel_crtc->base.dev;
4775 struct drm_i915_private *dev_priv = dev->dev_private;
4776 uint32_t pipeconf;
4777
4778 pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4779
4780 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4781 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4782 * core speed.
4783 *
4784 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4785 * pipe == 0 check?
4786 */
4787 if (intel_crtc->config.requested_mode.clock >
4788 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4789 pipeconf |= PIPECONF_DOUBLE_WIDE;
4790 else
4791 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4792 }
4793
ff9ce46e
DV		 4794 /* only g4x and later have fancy bpc/dither controls */
4795 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4796 pipeconf &= ~(PIPECONF_BPC_MASK |
4797 PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4798
4799 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4800 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4801 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4802 PIPECONF_DITHER_TYPE_SP;
84b046f3 4803
ff9ce46e
DV		 4804 switch (intel_crtc->config.pipe_bpp) {
4805 case 18:
4806 pipeconf |= PIPECONF_6BPC;
4807 break;
4808 case 24:
4809 pipeconf |= PIPECONF_8BPC;
4810 break;
4811 case 30:
4812 pipeconf |= PIPECONF_10BPC;
4813 break;
4814 default:
4815 /* Case prevented by intel_choose_pipe_bpp_dither. */
4816 BUG();
84b046f3
DV		 4817 }
4818 }
4819
4820 if (HAS_PIPE_CXSR(dev)) {
4821 if (intel_crtc->lowfreq_avail) {
4822 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4823 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4824 } else {
4825 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4826 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4827 }
4828 }
4829
4830 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4831 if (!IS_GEN2(dev) &&
4832 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4833 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4834 else
4835 pipeconf |= PIPECONF_PROGRESSIVE;
4836
9c8e09b7
VS		 4837 if (IS_VALLEYVIEW(dev)) {
4838 if (intel_crtc->config.limited_color_range)
4839 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4840 else
4841 pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4842 }
4843
84b046f3
DV		 4844 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4845 POSTING_READ(PIPECONF(intel_crtc->pipe));
4846}
4847
f564048e 4848static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4849 int x, int y,
94352cf9 4850 struct drm_framebuffer *fb)
79e53945
JB		 4851{
4852 struct drm_device *dev = crtc->dev;
4853 struct drm_i915_private *dev_priv = dev->dev_private;
4854 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 4855 struct drm_display_mode *adjusted_mode =
4856 &intel_crtc->config.adjusted_mode;
4857 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4858 int pipe = intel_crtc->pipe;
80824003 4859 int plane = intel_crtc->plane;
c751ce4f 4860 int refclk, num_connectors = 0;
652c393a 4861 intel_clock_t clock, reduced_clock;
84b046f3 4862 u32 dspcntr;
eb1cbe48 4863 bool ok, has_reduced_clock = false, is_sdvo = false;
8b47047b 4864 bool is_lvds = false, is_tv = false;
5eddb70b 4865 struct intel_encoder *encoder;
d4906093 4866 const intel_limit_t *limit;
5c3b82e2 4867 int ret;
79e53945 4868
6c2b7c12 4869 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4870 switch (encoder->type) {
79e53945
JB		 4871 case INTEL_OUTPUT_LVDS:
4872 is_lvds = true;
4873 break;
4874 case INTEL_OUTPUT_SDVO:
7d57382e 4875 case INTEL_OUTPUT_HDMI:
79e53945 4876 is_sdvo = true;
5eddb70b 4877 if (encoder->needs_tv_clock)
e2f0ba97 4878 is_tv = true;
79e53945 4879 break;
79e53945
JB		 4880 case INTEL_OUTPUT_TVOUT:
4881 is_tv = true;
4882 break;
79e53945 4883 }
43565a06 4884
c751ce4f 4885 num_connectors++;
79e53945
JB		 4886 }
4887
c65d77d8 4888 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4889
d4906093
ML		 4890 /*
4891 * Returns a set of divisors for the desired target clock with the given
4892 * refclk, or FALSE. The returned values represent the clock equation:
4893 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4894 */
1b894b59 4895 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4896 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4897 &clock);
79e53945
JB		 4898 if (!ok) {
4899 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4900 return -EINVAL;
79e53945
JB		 4901 }
4902
cda4b7d3 4903 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4904 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4905
ddc9003c 4906 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4907 /*
4908 * Ensure we match the reduced clock's P to the target clock.
4909 * If the clocks don't match, we can't switch the display clock
4910 * by using the FP0/FP1. In such case we will disable the LVDS
4911 * downclock feature.
4912 */
ddc9003c 4913 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4914 dev_priv->lvds_downclock,
4915 refclk,
cec2f356 4916 &clock,
5eddb70b 4917 &reduced_clock);
7026d4ac 4918 }
f47709a9
DV		 4919 /* Compat-code for transition, will disappear. */
4920 if (!intel_crtc->config.clock_set) {
4921 intel_crtc->config.dpll.n = clock.n;
4922 intel_crtc->config.dpll.m1 = clock.m1;
4923 intel_crtc->config.dpll.m2 = clock.m2;
4924 intel_crtc->config.dpll.p1 = clock.p1;
4925 intel_crtc->config.dpll.p2 = clock.p2;
4926 }
7026d4ac 4927
c65d77d8 4928 if (is_sdvo && is_tv)
f47709a9 4929 i9xx_adjust_sdvo_tv_clock(intel_crtc);
7026d4ac 4930
eb1cbe48 4931 if (IS_GEN2(dev))
f47709a9 4932 i8xx_update_pll(intel_crtc, adjusted_mode,
2a8f64ca
VP		 4933 has_reduced_clock ? &reduced_clock : NULL,
4934 num_connectors);
a0c4da24 4935 else if (IS_VALLEYVIEW(dev))
f47709a9 4936 vlv_update_pll(intel_crtc);
79e53945 4937 else
f47709a9 4938 i9xx_update_pll(intel_crtc,
eb1cbe48 4939 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4940 num_connectors);
79e53945 4941
79e53945
JB		 4942 /* Set up the display plane register */
4943 dspcntr = DISPPLANE_GAMMA_ENABLE;
4944
da6ecc5d
JB		 4945 if (!IS_VALLEYVIEW(dev)) {
4946 if (pipe == 0)
4947 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4948 else
4949 dspcntr |= DISPPLANE_SEL_PIPE_B;
4950 }
79e53945 4951
2582a850 4952 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
79e53945
JB		 4953 drm_mode_debug_printmodeline(mode);
4954
b0e77b9c 4955 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4956
4957 /* pipesrc and dspsize control the size that is scaled from,
4958 * which should always be the user's requested size.
79e53945 4959 */
929c77fb
EA		 4960 I915_WRITE(DSPSIZE(plane),
4961 ((mode->vdisplay - 1) << 16) |
4962 (mode->hdisplay - 1));
4963 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4964
84b046f3
DV		 4965 i9xx_set_pipeconf(intel_crtc);
4966
f564048e
EA		 4967 I915_WRITE(DSPCNTR(plane), dspcntr);
4968 POSTING_READ(DSPCNTR(plane));
4969
94352cf9 4970 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4971
4972 intel_update_watermarks(dev);
4973
f564048e
EA		 4974 return ret;
4975}
4976
0e8ffe1b
DV		 4977static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4978 struct intel_crtc_config *pipe_config)
4979{
4980 struct drm_device *dev = crtc->base.dev;
4981 struct drm_i915_private *dev_priv = dev->dev_private;
4982 uint32_t tmp;
4983
4984 tmp = I915_READ(PIPECONF(crtc->pipe));
4985 if (!(tmp & PIPECONF_ENABLE))
4986 return false;
4987
1bd1bd80
DV		 4988 intel_get_pipe_timings(crtc, pipe_config);
4989
0e8ffe1b
DV		 4990 return true;
4991}
4992
dde86e2d 4993static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4994{
4995 struct drm_i915_private *dev_priv = dev->dev_private;
4996 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4997 struct intel_encoder *encoder;
74cfd7ac 4998 u32 val, final;
13d83a67 4999 bool has_lvds = false;
199e5d79
KP		 5000 bool has_cpu_edp = false;
5001 bool has_pch_edp = false;
5002 bool has_panel = false;
99eb6a01
KP		 5003 bool has_ck505 = false;
5004 bool can_ssc = false;
13d83a67
JB		 5005
5006 /* We need to take the global config into account */
199e5d79
KP		 5007 list_for_each_entry(encoder, &mode_config->encoder_list,
5008 base.head) {
5009 switch (encoder->type) {
5010 case INTEL_OUTPUT_LVDS:
5011 has_panel = true;
5012 has_lvds = true;
5013 break;
5014 case INTEL_OUTPUT_EDP:
5015 has_panel = true;
5016 if (intel_encoder_is_pch_edp(&encoder->base))
5017 has_pch_edp = true;
5018 else
5019 has_cpu_edp = true;
5020 break;
13d83a67
JB		 5021 }
5022 }
5023
99eb6a01
KP		 5024 if (HAS_PCH_IBX(dev)) {
5025 has_ck505 = dev_priv->display_clock_mode;
5026 can_ssc = has_ck505;
5027 } else {
5028 has_ck505 = false;
5029 can_ssc = true;
5030 }
5031
5032 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5033 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
5034 has_ck505);
13d83a67
JB		 5035
5036 /* Ironlake: try to setup display ref clock before DPLL
5037 * enabling. This is only under driver's control after
5038 * PCH B stepping, previous chipset stepping should be
5039 * ignoring this setting.
5040 */
74cfd7ac
CW		 5041 val = I915_READ(PCH_DREF_CONTROL);
5042
5043 /* As we must carefully and slowly disable/enable each source in turn,
5044 * compute the final state we want first and check if we need to
5045 * make any changes at all.
5046 */
5047 final = val;
5048 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5049 if (has_ck505)
5050 final |= DREF_NONSPREAD_CK505_ENABLE;
5051 else
5052 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5053
5054 final &= ~DREF_SSC_SOURCE_MASK;
5055 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5056 final &= ~DREF_SSC1_ENABLE;
5057
5058 if (has_panel) {
5059 final |= DREF_SSC_SOURCE_ENABLE;
5060
5061 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5062 final |= DREF_SSC1_ENABLE;
5063
5064 if (has_cpu_edp) {
5065 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5066 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5067 else
5068 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5069 } else
5070 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5071 } else {
5072 final |= DREF_SSC_SOURCE_DISABLE;
5073 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5074 }
5075
5076 if (final == val)
5077 return;
5078
13d83a67 5079 /* Always enable nonspread source */
74cfd7ac 5080 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5081
99eb6a01 5082 if (has_ck505)
74cfd7ac 5083 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5084 else
74cfd7ac 5085 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5086
199e5d79 5087 if (has_panel) {
74cfd7ac
CW		 5088 val &= ~DREF_SSC_SOURCE_MASK;
5089 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5090
199e5d79 5091 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5092 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5093 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5094 val |= DREF_SSC1_ENABLE;
e77166b5 5095 } else
74cfd7ac 5096 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5097
5098 /* Get SSC going before enabling the outputs */
74cfd7ac 5099 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5100 POSTING_READ(PCH_DREF_CONTROL);
5101 udelay(200);
5102
74cfd7ac 5103 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5104
5105 /* Enable CPU source on CPU attached eDP */
199e5d79 5106 if (has_cpu_edp) {
99eb6a01 5107 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5108 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5109 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5110 }
13d83a67 5111 else
74cfd7ac 5112 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5113 } else
74cfd7ac 5114 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5115
74cfd7ac 5116 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5117 POSTING_READ(PCH_DREF_CONTROL);
5118 udelay(200);
5119 } else {
5120 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5121
74cfd7ac 5122 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5123
5124 /* Turn off CPU output */
74cfd7ac 5125 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5126
74cfd7ac 5127 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5128 POSTING_READ(PCH_DREF_CONTROL);
5129 udelay(200);
5130
5131 /* Turn off the SSC source */
74cfd7ac
CW		 5132 val &= ~DREF_SSC_SOURCE_MASK;
5133 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5134
5135 /* Turn off SSC1 */
74cfd7ac 5136 val &= ~DREF_SSC1_ENABLE;
199e5d79 5137
74cfd7ac 5138 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5139 POSTING_READ(PCH_DREF_CONTROL);
5140 udelay(200);
5141 }
74cfd7ac
CW		 5142
5143 BUG_ON(val != final);
13d83a67
JB		 5144}
5145
dde86e2d
PZ		 5146/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5147static void lpt_init_pch_refclk(struct drm_device *dev)
5148{
5149 struct drm_i915_private *dev_priv = dev->dev_private;
5150 struct drm_mode_config *mode_config = &dev->mode_config;
5151 struct intel_encoder *encoder;
5152 bool has_vga = false;
5153 bool is_sdv = false;
5154 u32 tmp;
5155
5156 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5157 switch (encoder->type) {
5158 case INTEL_OUTPUT_ANALOG:
5159 has_vga = true;
5160 break;
5161 }
5162 }
5163
5164 if (!has_vga)
5165 return;
5166
c00db246
DV		 5167 mutex_lock(&dev_priv->dpio_lock);
5168
dde86e2d
PZ		 5169 /* XXX: Rip out SDV support once Haswell ships for real. */
5170 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5171 is_sdv = true;
5172
5173 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5174 tmp &= ~SBI_SSCCTL_DISABLE;
5175 tmp |= SBI_SSCCTL_PATHALT;
5176 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5177
5178 udelay(24);
5179
5180 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5181 tmp &= ~SBI_SSCCTL_PATHALT;
5182 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5183
5184 if (!is_sdv) {
5185 tmp = I915_READ(SOUTH_CHICKEN2);
5186 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5187 I915_WRITE(SOUTH_CHICKEN2, tmp);
5188
5189 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5190 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5191 DRM_ERROR("FDI mPHY reset assert timeout\n");
5192
5193 tmp = I915_READ(SOUTH_CHICKEN2);
5194 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5195 I915_WRITE(SOUTH_CHICKEN2, tmp);
5196
5197 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5198 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5199 100))
5200 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5201 }
5202
5203 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5204 tmp &= ~(0xFF << 24);
5205 tmp |= (0x12 << 24);
5206 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5207
dde86e2d
PZ		 5208 if (is_sdv) {
5209 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5210 tmp |= 0x7FFF;
5211 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5212 }
5213
5214 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5215 tmp |= (1 << 11);
5216 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5217
5218 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5219 tmp |= (1 << 11);
5220 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5221
5222 if (is_sdv) {
5223 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5224 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5225 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5226
5227 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5228 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5229 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5230
5231 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5232 tmp |= (0x3F << 8);
5233 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5234
5235 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5236 tmp |= (0x3F << 8);
5237 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5238 }
5239
5240 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5241 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5242 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5243
5244 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5245 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5246 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5247
5248 if (!is_sdv) {
5249 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5250 tmp &= ~(7 << 13);
5251 tmp |= (5 << 13);
5252 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5253
5254 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5255 tmp &= ~(7 << 13);
5256 tmp |= (5 << 13);
5257 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5258 }
5259
5260 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5261 tmp &= ~0xFF;
5262 tmp |= 0x1C;
5263 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5264
5265 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5266 tmp &= ~0xFF;
5267 tmp |= 0x1C;
5268 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5269
5270 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5271 tmp &= ~(0xFF << 16);
5272 tmp |= (0x1C << 16);
5273 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5274
5275 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5276 tmp &= ~(0xFF << 16);
5277 tmp |= (0x1C << 16);
5278 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5279
5280 if (!is_sdv) {
5281 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5282 tmp |= (1 << 27);
5283 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5284
5285 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5286 tmp |= (1 << 27);
5287 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5288
5289 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5290 tmp &= ~(0xF << 28);
5291 tmp |= (4 << 28);
5292 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5293
5294 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5295 tmp &= ~(0xF << 28);
5296 tmp |= (4 << 28);
5297 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5298 }
5299
5300 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5301 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5302 tmp |= SBI_DBUFF0_ENABLE;
5303 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5304
5305 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5306}
5307
5308/*
5309 * Initialize reference clocks when the driver loads
5310 */
5311void intel_init_pch_refclk(struct drm_device *dev)
5312{
5313 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5314 ironlake_init_pch_refclk(dev);
5315 else if (HAS_PCH_LPT(dev))
5316 lpt_init_pch_refclk(dev);
5317}
5318
d9d444cb
JB		 5319static int ironlake_get_refclk(struct drm_crtc *crtc)
5320{
5321 struct drm_device *dev = crtc->dev;
5322 struct drm_i915_private *dev_priv = dev->dev_private;
5323 struct intel_encoder *encoder;
d9d444cb
JB		 5324 struct intel_encoder *edp_encoder = NULL;
5325 int num_connectors = 0;
5326 bool is_lvds = false;
5327
6c2b7c12 5328 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5329 switch (encoder->type) {
5330 case INTEL_OUTPUT_LVDS:
5331 is_lvds = true;
5332 break;
5333 case INTEL_OUTPUT_EDP:
5334 edp_encoder = encoder;
5335 break;
5336 }
5337 num_connectors++;
5338 }
5339
5340 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5341 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5342 dev_priv->lvds_ssc_freq);
5343 return dev_priv->lvds_ssc_freq * 1000;
5344 }
5345
5346 return 120000;
5347}
5348
6ff93609 5349static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5350{
c8203565 5351 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5352 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5353 int pipe = intel_crtc->pipe;
c8203565
PZ		 5354 uint32_t val;
5355
5356 val = I915_READ(PIPECONF(pipe));
5357
dfd07d72 5358 val &= ~PIPECONF_BPC_MASK;
965e0c48 5359 switch (intel_crtc->config.pipe_bpp) {
c8203565 5360 case 18:
dfd07d72 5361 val |= PIPECONF_6BPC;
c8203565
PZ		 5362 break;
5363 case 24:
dfd07d72 5364 val |= PIPECONF_8BPC;
c8203565
PZ		 5365 break;
5366 case 30:
dfd07d72 5367 val |= PIPECONF_10BPC;
c8203565
PZ		 5368 break;
5369 case 36:
dfd07d72 5370 val |= PIPECONF_12BPC;
c8203565
PZ		 5371 break;
5372 default:
cc769b62
PZ		 5373 /* Case prevented by intel_choose_pipe_bpp_dither. */
5374 BUG();
c8203565
PZ		 5375 }
5376
5377 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
d8b32247 5378 if (intel_crtc->config.dither)
c8203565
PZ		 5379 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5380
5381 val &= ~PIPECONF_INTERLACE_MASK;
6ff93609 5382 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5383 val |= PIPECONF_INTERLACED_ILK;
5384 else
5385 val |= PIPECONF_PROGRESSIVE;
5386
50f3b016 5387 if (intel_crtc->config.limited_color_range)
3685a8f3
VS		 5388 val |= PIPECONF_COLOR_RANGE_SELECT;
5389 else
5390 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5391
c8203565
PZ		 5392 I915_WRITE(PIPECONF(pipe), val);
5393 POSTING_READ(PIPECONF(pipe));
5394}
5395
86d3efce
VS		 5396/*
5397 * Set up the pipe CSC unit.
5398 *
5399 * Currently only full range RGB to limited range RGB conversion
5400 * is supported, but eventually this should handle various
5401 * RGB<->YCbCr scenarios as well.
5402 */
50f3b016 5403static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5404{
5405 struct drm_device *dev = crtc->dev;
5406 struct drm_i915_private *dev_priv = dev->dev_private;
5407 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5408 int pipe = intel_crtc->pipe;
5409 uint16_t coeff = 0x7800; /* 1.0 */
5410
5411 /*
5412 * TODO: Check what kind of values actually come out of the pipe
5413 * with these coeff/postoff values and adjust to get the best
5414 * accuracy. Perhaps we even need to take the bpc value into
5415 * consideration.
5416 */
5417
50f3b016 5418 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5419 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5420
5421 /*
5422 * GY/GU and RY/RU should be the other way around according
5423 * to BSpec, but reality doesn't agree. Just set them up in
5424 * a way that results in the correct picture.
5425 */
5426 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5427 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5428
5429 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5430 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5431
5432 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5433 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5434
5435 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5436 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5437 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5438
5439 if (INTEL_INFO(dev)->gen > 6) {
5440 uint16_t postoff = 0;
5441
50f3b016 5442 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5443 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5444
5445 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5446 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5447 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5448
5449 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5450 } else {
5451 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5452
50f3b016 5453 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5454 mode |= CSC_BLACK_SCREEN_OFFSET;
5455
5456 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5457 }
5458}
5459
6ff93609 5460static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5461{
5462 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5463 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5464 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5465 uint32_t val;
5466
702e7a56 5467 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5468
5469 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
d8b32247 5470 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5471 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5472
5473 val &= ~PIPECONF_INTERLACE_MASK_HSW;
6ff93609 5474 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5475 val |= PIPECONF_INTERLACED_ILK;
5476 else
5477 val |= PIPECONF_PROGRESSIVE;
5478
702e7a56
PZ		 5479 I915_WRITE(PIPECONF(cpu_transcoder), val);
5480 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5481}
5482
6591c6e4
PZ		 5483static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5484 struct drm_display_mode *adjusted_mode,
5485 intel_clock_t *clock,
5486 bool *has_reduced_clock,
5487 intel_clock_t *reduced_clock)
5488{
5489 struct drm_device *dev = crtc->dev;
5490 struct drm_i915_private *dev_priv = dev->dev_private;
5491 struct intel_encoder *intel_encoder;
5492 int refclk;
d4906093 5493 const intel_limit_t *limit;
6591c6e4 5494 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
79e53945 5495
6591c6e4
PZ		 5496 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5497 switch (intel_encoder->type) {
79e53945
JB		 5498 case INTEL_OUTPUT_LVDS:
5499 is_lvds = true;
5500 break;
5501 case INTEL_OUTPUT_SDVO:
7d57382e 5502 case INTEL_OUTPUT_HDMI:
79e53945 5503 is_sdvo = true;
6591c6e4 5504 if (intel_encoder->needs_tv_clock)
e2f0ba97 5505 is_tv = true;
79e53945 5506 break;
79e53945
JB		 5507 case INTEL_OUTPUT_TVOUT:
5508 is_tv = true;
5509 break;
79e53945
JB		 5510 }
5511 }
5512
d9d444cb 5513 refclk = ironlake_get_refclk(crtc);
79e53945 5514
d4906093
ML		 5515 /*
5516 * Returns a set of divisors for the desired target clock with the given
5517 * refclk, or FALSE. The returned values represent the clock equation:
5518 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5519 */
1b894b59 5520 limit = intel_limit(crtc, refclk);
6591c6e4
PZ		 5521 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5522 clock);
5523 if (!ret)
5524 return false;
cda4b7d3 5525
ddc9003c 5526 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5527 /*
5528 * Ensure we match the reduced clock's P to the target clock.
5529 * If the clocks don't match, we can't switch the display clock
5530 * by using the FP0/FP1. In such case we will disable the LVDS
5531 * downclock feature.
5532 */
6591c6e4
PZ		 5533 *has_reduced_clock = limit->find_pll(limit, crtc,
5534 dev_priv->lvds_downclock,
5535 refclk,
5536 clock,
5537 reduced_clock);
652c393a 5538 }
61e9653f
DV		 5539
5540 if (is_sdvo && is_tv)
f47709a9 5541 i9xx_adjust_sdvo_tv_clock(to_intel_crtc(crtc));
6591c6e4
PZ		 5542
5543 return true;
5544}
5545
01a415fd
DV		 5546static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5547{
5548 struct drm_i915_private *dev_priv = dev->dev_private;
5549 uint32_t temp;
5550
5551 temp = I915_READ(SOUTH_CHICKEN1);
5552 if (temp & FDI_BC_BIFURCATION_SELECT)
5553 return;
5554
5555 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5556 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5557
5558 temp |= FDI_BC_BIFURCATION_SELECT;
5559 DRM_DEBUG_KMS("enabling fdi C rx\n");
5560 I915_WRITE(SOUTH_CHICKEN1, temp);
5561 POSTING_READ(SOUTH_CHICKEN1);
5562}
5563
ebfd86fd
DV		 5564static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5565{
5566 struct drm_device *dev = intel_crtc->base.dev;
5567 struct drm_i915_private *dev_priv = dev->dev_private;
5568
5569 switch (intel_crtc->pipe) {
5570 case PIPE_A:
5571 break;
5572 case PIPE_B:
5573 if (intel_crtc->config.fdi_lanes > 2)
5574 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5575 else
5576 cpt_enable_fdi_bc_bifurcation(dev);
5577
5578 break;
5579 case PIPE_C:
01a415fd
DV		 5580 cpt_enable_fdi_bc_bifurcation(dev);
5581
ebfd86fd 5582 break;
01a415fd
DV		 5583 default:
5584 BUG();
5585 }
5586}
5587
d4b1931c
PZ		 5588int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5589{
5590 /*
5591 * Account for spread spectrum to avoid
5592 * oversubscribing the link. Max center spread
5593 * is 2.5%; use 5% for safety's sake.
5594 */
5595 u32 bps = target_clock * bpp * 21 / 20;
5596 return bps / (link_bw * 8) + 1;
5597}
5598
6cf86a5e
DV		 5599void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5600 struct intel_link_m_n *m_n)
79e53945 5601{
6cf86a5e
DV		 5602 struct drm_device *dev = crtc->base.dev;
5603 struct drm_i915_private *dev_priv = dev->dev_private;
5604 int pipe = crtc->pipe;
5605
5606 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5607 I915_WRITE(TRANSDATA_N1(pipe), m_n->gmch_n);
5608 I915_WRITE(TRANSDPLINK_M1(pipe), m_n->link_m);
5609 I915_WRITE(TRANSDPLINK_N1(pipe), m_n->link_n);
5610}
5611
5612void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5613 struct intel_link_m_n *m_n)
5614{
5615 struct drm_device *dev = crtc->base.dev;
79e53945 5616 struct drm_i915_private *dev_priv = dev->dev_private;
6cf86a5e 5617 int pipe = crtc->pipe;
3b117c8f 5618 enum transcoder transcoder = crtc->config.cpu_transcoder;
6cf86a5e
DV		 5619
5620 if (INTEL_INFO(dev)->gen >= 5) {
5621 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5622 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5623 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5624 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5625 } else {
5626 I915_WRITE(PIPE_GMCH_DATA_M(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5627 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n->gmch_n);
5628 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n->link_m);
5629 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n->link_n);
5630 }
5631}
5632
7429e9d4
DV		 5633static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5634{
5635 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5636}
5637
de13a2e3 5638static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5639 u32 *fp,
9a7c7890 5640 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5641{
de13a2e3 5642 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5643 struct drm_device *dev = crtc->dev;
5644 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5645 struct intel_encoder *intel_encoder;
5646 uint32_t dpll;
6cc5f341 5647 int factor, num_connectors = 0;
de13a2e3 5648 bool is_lvds = false, is_sdvo = false, is_tv = false;
79e53945 5649
de13a2e3
PZ		 5650 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5651 switch (intel_encoder->type) {
79e53945
JB		 5652 case INTEL_OUTPUT_LVDS:
5653 is_lvds = true;
5654 break;
5655 case INTEL_OUTPUT_SDVO:
7d57382e 5656 case INTEL_OUTPUT_HDMI:
79e53945 5657 is_sdvo = true;
de13a2e3 5658 if (intel_encoder->needs_tv_clock)
e2f0ba97 5659 is_tv = true;
79e53945 5660 break;
79e53945
JB		 5661 case INTEL_OUTPUT_TVOUT:
5662 is_tv = true;
5663 break;
79e53945 5664 }
43565a06 5665
c751ce4f 5666 num_connectors++;
79e53945 5667 }
79e53945 5668
c1858123 5669 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5670 factor = 21;
5671 if (is_lvds) {
5672 if ((intel_panel_use_ssc(dev_priv) &&
5673 dev_priv->lvds_ssc_freq == 100) ||
f0b44056 5674 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297
EA		 5675 factor = 25;
5676 } else if (is_sdvo && is_tv)
5677 factor = 20;
c1858123 5678
7429e9d4 5679 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5680 *fp |= FP_CB_TUNE;
2c07245f 5681
9a7c7890
DV		 5682 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5683 *fp2 |= FP_CB_TUNE;
5684
5eddb70b 5685 dpll = 0;
2c07245f 5686
a07d6787
EA		 5687 if (is_lvds)
5688 dpll |= DPLLB_MODE_LVDS;
5689 else
5690 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f
DV		 5691
5692 if (intel_crtc->config.pixel_multiplier > 1) {
5693 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5694 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
a07d6787 5695 }
198a037f
DV		 5696
5697 if (is_sdvo)
5698 dpll |= DPLL_DVO_HIGH_SPEED;
9566e9af 5699 if (intel_crtc->config.has_dp_encoder)
a07d6787 5700 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5701
a07d6787 5702 /* compute bitmask from p1 value */
7429e9d4 5703 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5704 /* also FPA1 */
7429e9d4 5705 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5706
7429e9d4 5707 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5708 case 5:
5709 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5710 break;
5711 case 7:
5712 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5713 break;
5714 case 10:
5715 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5716 break;
5717 case 14:
5718 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5719 break;
79e53945
JB		 5720 }
5721
43565a06
KH		 5722 if (is_sdvo && is_tv)
5723 dpll |= PLL_REF_INPUT_TVCLKINBC;
5724 else if (is_tv)
79e53945 5725 /* XXX: just matching BIOS for now */
43565a06 5726 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5727 dpll |= 3;
a7615030 5728 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5729 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5730 else
5731 dpll |= PLL_REF_INPUT_DREFCLK;
5732
de13a2e3
PZ		 5733 return dpll;
5734}
5735
5736static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5737 int x, int y,
5738 struct drm_framebuffer *fb)
5739{
5740 struct drm_device *dev = crtc->dev;
5741 struct drm_i915_private *dev_priv = dev->dev_private;
5742 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5743 struct drm_display_mode *adjusted_mode =
5744 &intel_crtc->config.adjusted_mode;
5745 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
de13a2e3
PZ		 5746 int pipe = intel_crtc->pipe;
5747 int plane = intel_crtc->plane;
5748 int num_connectors = 0;
5749 intel_clock_t clock, reduced_clock;
cbbab5bd 5750 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5751 bool ok, has_reduced_clock = false;
8b47047b 5752 bool is_lvds = false;
de13a2e3 5753 struct intel_encoder *encoder;
de13a2e3 5754 int ret;
de13a2e3
PZ		 5755
5756 for_each_encoder_on_crtc(dev, crtc, encoder) {
5757 switch (encoder->type) {
5758 case INTEL_OUTPUT_LVDS:
5759 is_lvds = true;
5760 break;
de13a2e3
PZ		 5761 }
5762
5763 num_connectors++;
a07d6787 5764 }
79e53945 5765
5dc5298b
PZ		 5766 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5767 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5768
3b117c8f 5769 intel_crtc->config.cpu_transcoder = pipe;
6cf86a5e 5770
de13a2e3
PZ		 5771 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5772 &has_reduced_clock, &reduced_clock);
5773 if (!ok) {
5774 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5775 return -EINVAL;
79e53945 5776 }
f47709a9
DV		 5777 /* Compat-code for transition, will disappear. */
5778 if (!intel_crtc->config.clock_set) {
5779 intel_crtc->config.dpll.n = clock.n;
5780 intel_crtc->config.dpll.m1 = clock.m1;
5781 intel_crtc->config.dpll.m2 = clock.m2;
5782 intel_crtc->config.dpll.p1 = clock.p1;
5783 intel_crtc->config.dpll.p2 = clock.p2;
5784 }
79e53945 5785
de13a2e3
PZ		 5786 /* Ensure that the cursor is valid for the new mode before changing... */
5787 intel_crtc_update_cursor(crtc, true);
5788
84f44ce7 5789 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
79e53945
JB		 5790 drm_mode_debug_printmodeline(mode);
5791
5dc5298b 5792 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5793 if (intel_crtc->config.has_pch_encoder) {
ee7b9f93 5794 struct intel_pch_pll *pll;
4b645f14 5795
7429e9d4 5796 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5797 if (has_reduced_clock)
7429e9d4 5798 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5799
7429e9d4 5800 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5801 &fp, &reduced_clock,
5802 has_reduced_clock ? &fp2 : NULL);
5803
ee7b9f93
JB		 5804 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5805 if (pll == NULL) {
84f44ce7
VS		 5806 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5807 pipe_name(pipe));
4b645f14
JB		 5808 return -EINVAL;
5809 }
ee7b9f93
JB		 5810 } else
5811 intel_put_pch_pll(intel_crtc);
79e53945 5812
03afc4a2
DV		 5813 if (intel_crtc->config.has_dp_encoder)
5814 intel_dp_set_m_n(intel_crtc);
79e53945 5815
dafd226c
DV		 5816 for_each_encoder_on_crtc(dev, crtc, encoder)
5817 if (encoder->pre_pll_enable)
5818 encoder->pre_pll_enable(encoder);
79e53945 5819
ee7b9f93
JB		 5820 if (intel_crtc->pch_pll) {
5821 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5822
32f9d658 5823 /* Wait for the clocks to stabilize. */
ee7b9f93 5824 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5825 udelay(150);
5826
8febb297
EA		 5827 /* The pixel multiplier can only be updated once the
5828 * DPLL is enabled and the clocks are stable.
5829 *
5830 * So write it again.
5831 */
ee7b9f93 5832 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5833 }
79e53945 5834
5eddb70b 5835 intel_crtc->lowfreq_avail = false;
ee7b9f93 5836 if (intel_crtc->pch_pll) {
4b645f14 5837 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5838 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5839 intel_crtc->lowfreq_avail = true;
4b645f14 5840 } else {
ee7b9f93 5841 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5842 }
5843 }
5844
b0e77b9c 5845 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b 5846
ca3a0ff8 5847 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5848 intel_cpu_transcoder_set_m_n(intel_crtc,
5849 &intel_crtc->config.fdi_m_n);
5850 }
2c07245f 5851
ebfd86fd
DV		 5852 if (IS_IVYBRIDGE(dev))
5853 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
2c07245f 5854
6ff93609 5855 ironlake_set_pipeconf(crtc);
79e53945 5856
a1f9e77e
PZ		 5857 /* Set up the display plane register */
5858 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5859 POSTING_READ(DSPCNTR(plane));
79e53945 5860
94352cf9 5861 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5862
5863 intel_update_watermarks(dev);
5864
1f8eeabf
ED		 5865 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5866
1857e1da 5867 return ret;
79e53945
JB		 5868}
5869
72419203
DV		 5870static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5871 struct intel_crtc_config *pipe_config)
5872{
5873 struct drm_device *dev = crtc->base.dev;
5874 struct drm_i915_private *dev_priv = dev->dev_private;
5875 enum transcoder transcoder = pipe_config->cpu_transcoder;
5876
5877 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5878 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5879 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5880 & ~TU_SIZE_MASK;
5881 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5882 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5883 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5884}
5885
0e8ffe1b
DV		 5886static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5887 struct intel_crtc_config *pipe_config)
5888{
5889 struct drm_device *dev = crtc->base.dev;
5890 struct drm_i915_private *dev_priv = dev->dev_private;
5891 uint32_t tmp;
5892
5893 tmp = I915_READ(PIPECONF(crtc->pipe));
5894 if (!(tmp & PIPECONF_ENABLE))
5895 return false;
5896
ab9412ba 5897 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
88adfff1
DV		 5898 pipe_config->has_pch_encoder = true;
5899
627eb5a3
DV		 5900 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5901 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5902 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5903
5904 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 5905 }
5906
1bd1bd80
DV		 5907 intel_get_pipe_timings(crtc, pipe_config);
5908
0e8ffe1b
DV		 5909 return true;
5910}
5911
d6dd9eb1
DV		 5912static void haswell_modeset_global_resources(struct drm_device *dev)
5913{
d6dd9eb1
DV		 5914 bool enable = false;
5915 struct intel_crtc *crtc;
5916 struct intel_encoder *encoder;
5917
5918 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5919 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5920 enable = true;
5921 /* XXX: Should check for edp transcoder here, but thanks to init
5922 * sequence that's not yet available. Just in case desktop eDP
5923 * on PORT D is possible on haswell, too. */
b074cec8 5924 /* Even the eDP panel fitter is outside the always-on well. */
2b87f3b1 5925 if (crtc->config.pch_pfit.size && crtc->base.enabled)
b074cec8 5926 enable = true;
d6dd9eb1
DV		 5927 }
5928
5929 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5930 base.head) {
5931 if (encoder->type != INTEL_OUTPUT_EDP &&
5932 encoder->connectors_active)
5933 enable = true;
5934 }
5935
d6dd9eb1
DV		 5936 intel_set_power_well(dev, enable);
5937}
5938
09b4ddf9 5939static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 5940 int x, int y,
5941 struct drm_framebuffer *fb)
5942{
5943 struct drm_device *dev = crtc->dev;
5944 struct drm_i915_private *dev_priv = dev->dev_private;
5945 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5946 struct drm_display_mode *adjusted_mode =
5947 &intel_crtc->config.adjusted_mode;
5948 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
09b4ddf9
PZ		 5949 int pipe = intel_crtc->pipe;
5950 int plane = intel_crtc->plane;
5951 int num_connectors = 0;
8b47047b 5952 bool is_cpu_edp = false;
09b4ddf9 5953 struct intel_encoder *encoder;
09b4ddf9 5954 int ret;
09b4ddf9
PZ		 5955
5956 for_each_encoder_on_crtc(dev, crtc, encoder) {
5957 switch (encoder->type) {
09b4ddf9 5958 case INTEL_OUTPUT_EDP:
09b4ddf9
PZ		 5959 if (!intel_encoder_is_pch_edp(&encoder->base))
5960 is_cpu_edp = true;
5961 break;
5962 }
5963
5964 num_connectors++;
5965 }
5966
bba2181c 5967 if (is_cpu_edp)
3b117c8f 5968 intel_crtc->config.cpu_transcoder = TRANSCODER_EDP;
bba2181c 5969 else
3b117c8f 5970 intel_crtc->config.cpu_transcoder = pipe;
bba2181c 5971
5dc5298b
PZ		 5972 /* We are not sure yet this won't happen. */
5973 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5974 INTEL_PCH_TYPE(dev));
5975
5976 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5977 num_connectors, pipe_name(pipe));
5978
3b117c8f 5979 WARN_ON(I915_READ(PIPECONF(intel_crtc->config.cpu_transcoder)) &
1ce42920
PZ		 5980 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5981
5982 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5983
6441ab5f
PZ		 5984 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5985 return -EINVAL;
5986
09b4ddf9
PZ		 5987 /* Ensure that the cursor is valid for the new mode before changing... */
5988 intel_crtc_update_cursor(crtc, true);
5989
84f44ce7 5990 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
09b4ddf9
PZ		 5991 drm_mode_debug_printmodeline(mode);
5992
03afc4a2
DV		 5993 if (intel_crtc->config.has_dp_encoder)
5994 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 5995
5996 intel_crtc->lowfreq_avail = false;
09b4ddf9
PZ		 5997
5998 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5999
ca3a0ff8 6000 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 6001 intel_cpu_transcoder_set_m_n(intel_crtc,
6002 &intel_crtc->config.fdi_m_n);
6003 }
09b4ddf9 6004
6ff93609 6005 haswell_set_pipeconf(crtc);
09b4ddf9 6006
50f3b016 6007 intel_set_pipe_csc(crtc);
86d3efce 6008
09b4ddf9 6009 /* Set up the display plane register */
86d3efce 6010 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 6011 POSTING_READ(DSPCNTR(plane));
6012
6013 ret = intel_pipe_set_base(crtc, x, y, fb);
6014
6015 intel_update_watermarks(dev);
6016
6017 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
6018
1f803ee5 6019 return ret;
79e53945
JB		 6020}
6021
0e8ffe1b
DV		 6022static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6023 struct intel_crtc_config *pipe_config)
6024{
6025 struct drm_device *dev = crtc->base.dev;
6026 struct drm_i915_private *dev_priv = dev->dev_private;
2bfce950 6027 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
0e8ffe1b
DV		 6028 uint32_t tmp;
6029
2bfce950
PZ		 6030 if (!intel_using_power_well(dev_priv->dev) &&
6031 cpu_transcoder != TRANSCODER_EDP)
6032 return false;
6033
6034 tmp = I915_READ(PIPECONF(cpu_transcoder));
0e8ffe1b
DV		 6035 if (!(tmp & PIPECONF_ENABLE))
6036 return false;
6037
88adfff1 6038 /*
f196e6be 6039 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 6040 * DDI E. So just check whether this pipe is wired to DDI E and whether
6041 * the PCH transcoder is on.
6042 */
f196e6be 6043 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
88adfff1 6044 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 6045 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 6046 pipe_config->has_pch_encoder = true;
6047
627eb5a3
DV		 6048 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6049 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6050 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6051
6052 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 6053 }
6054
1bd1bd80
DV		 6055 intel_get_pipe_timings(crtc, pipe_config);
6056
0e8ffe1b
DV		 6057 return true;
6058}
6059
f564048e 6060static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6061 int x, int y,
94352cf9 6062 struct drm_framebuffer *fb)
f564048e
EA		 6063{
6064 struct drm_device *dev = crtc->dev;
6065 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 6066 struct drm_encoder_helper_funcs *encoder_funcs;
6067 struct intel_encoder *encoder;
0b701d27 6068 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 6069 struct drm_display_mode *adjusted_mode =
6070 &intel_crtc->config.adjusted_mode;
6071 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6072 int pipe = intel_crtc->pipe;
f564048e
EA		 6073 int ret;
6074
0b701d27 6075 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6076
b8cecdf5
DV		 6077 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6078
79e53945 6079 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6080
9256aa19
DV		 6081 if (ret != 0)
6082 return ret;
6083
6084 for_each_encoder_on_crtc(dev, crtc, encoder) {
6085 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6086 encoder->base.base.id,
6087 drm_get_encoder_name(&encoder->base),
6088 mode->base.id, mode->name);
6cc5f341
DV		 6089 if (encoder->mode_set) {
6090 encoder->mode_set(encoder);
6091 } else {
6092 encoder_funcs = encoder->base.helper_private;
6093 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6094 }
9256aa19
DV		 6095 }
6096
6097 return 0;
79e53945
JB		 6098}
6099
3a9627f4
WF		 6100static bool intel_eld_uptodate(struct drm_connector *connector,
6101 int reg_eldv, uint32_t bits_eldv,
6102 int reg_elda, uint32_t bits_elda,
6103 int reg_edid)
6104{
6105 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6106 uint8_t *eld = connector->eld;
6107 uint32_t i;
6108
6109 i = I915_READ(reg_eldv);
6110 i &= bits_eldv;
6111
6112 if (!eld[0])
6113 return !i;
6114
6115 if (!i)
6116 return false;
6117
6118 i = I915_READ(reg_elda);
6119 i &= ~bits_elda;
6120 I915_WRITE(reg_elda, i);
6121
6122 for (i = 0; i < eld[2]; i++)
6123 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6124 return false;
6125
6126 return true;
6127}
6128
e0dac65e
WF		 6129static void g4x_write_eld(struct drm_connector *connector,
6130 struct drm_crtc *crtc)
6131{
6132 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6133 uint8_t *eld = connector->eld;
6134 uint32_t eldv;
6135 uint32_t len;
6136 uint32_t i;
6137
6138 i = I915_READ(G4X_AUD_VID_DID);
6139
6140 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6141 eldv = G4X_ELDV_DEVCL_DEVBLC;
6142 else
6143 eldv = G4X_ELDV_DEVCTG;
6144
3a9627f4
WF		 6145 if (intel_eld_uptodate(connector,
6146 G4X_AUD_CNTL_ST, eldv,
6147 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6148 G4X_HDMIW_HDMIEDID))
6149 return;
6150
e0dac65e
WF		 6151 i = I915_READ(G4X_AUD_CNTL_ST);
6152 i &= ~(eldv | G4X_ELD_ADDR);
6153 len = (i >> 9) & 0x1f; /* ELD buffer size */
6154 I915_WRITE(G4X_AUD_CNTL_ST, i);
6155
6156 if (!eld[0])
6157 return;
6158
6159 len = min_t(uint8_t, eld[2], len);
6160 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6161 for (i = 0; i < len; i++)
6162 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6163
6164 i = I915_READ(G4X_AUD_CNTL_ST);
6165 i |= eldv;
6166 I915_WRITE(G4X_AUD_CNTL_ST, i);
6167}
6168
83358c85
WX		 6169static void haswell_write_eld(struct drm_connector *connector,
6170 struct drm_crtc *crtc)
6171{
6172 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6173 uint8_t *eld = connector->eld;
6174 struct drm_device *dev = crtc->dev;
7b9f35a6 6175 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6176 uint32_t eldv;
6177 uint32_t i;
6178 int len;
6179 int pipe = to_intel_crtc(crtc)->pipe;
6180 int tmp;
6181
6182 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6183 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6184 int aud_config = HSW_AUD_CFG(pipe);
6185 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6186
6187
6188 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6189
6190 /* Audio output enable */
6191 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6192 tmp = I915_READ(aud_cntrl_st2);
6193 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6194 I915_WRITE(aud_cntrl_st2, tmp);
6195
6196 /* Wait for 1 vertical blank */
6197 intel_wait_for_vblank(dev, pipe);
6198
6199 /* Set ELD valid state */
6200 tmp = I915_READ(aud_cntrl_st2);
6201 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6202 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6203 I915_WRITE(aud_cntrl_st2, tmp);
6204 tmp = I915_READ(aud_cntrl_st2);
6205 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6206
6207 /* Enable HDMI mode */
6208 tmp = I915_READ(aud_config);
6209 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6210 /* clear N_programing_enable and N_value_index */
6211 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6212 I915_WRITE(aud_config, tmp);
6213
6214 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6215
6216 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6217 intel_crtc->eld_vld = true;
83358c85
WX		 6218
6219 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6220 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6221 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6222 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6223 } else
6224 I915_WRITE(aud_config, 0);
6225
6226 if (intel_eld_uptodate(connector,
6227 aud_cntrl_st2, eldv,
6228 aud_cntl_st, IBX_ELD_ADDRESS,
6229 hdmiw_hdmiedid))
6230 return;
6231
6232 i = I915_READ(aud_cntrl_st2);
6233 i &= ~eldv;
6234 I915_WRITE(aud_cntrl_st2, i);
6235
6236 if (!eld[0])
6237 return;
6238
6239 i = I915_READ(aud_cntl_st);
6240 i &= ~IBX_ELD_ADDRESS;
6241 I915_WRITE(aud_cntl_st, i);
6242 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6243 DRM_DEBUG_DRIVER("port num:%d\n", i);
6244
6245 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6246 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6247 for (i = 0; i < len; i++)
6248 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6249
6250 i = I915_READ(aud_cntrl_st2);
6251 i |= eldv;
6252 I915_WRITE(aud_cntrl_st2, i);
6253
6254}
6255
e0dac65e
WF		 6256static void ironlake_write_eld(struct drm_connector *connector,
6257 struct drm_crtc *crtc)
6258{
6259 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6260 uint8_t *eld = connector->eld;
6261 uint32_t eldv;
6262 uint32_t i;
6263 int len;
6264 int hdmiw_hdmiedid;
b6daa025 6265 int aud_config;
e0dac65e
WF		 6266 int aud_cntl_st;
6267 int aud_cntrl_st2;
9b138a83 6268 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6269
b3f33cbf 6270 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6271 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6272 aud_config = IBX_AUD_CFG(pipe);
6273 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6274 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6275 } else {
9b138a83
WX		 6276 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6277 aud_config = CPT_AUD_CFG(pipe);
6278 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6279 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6280 }
6281
9b138a83 6282 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6283
6284 i = I915_READ(aud_cntl_st);
9b138a83 6285 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6286 if (!i) {
6287 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6288 /* operate blindly on all ports */
1202b4c6
WF		 6289 eldv = IBX_ELD_VALIDB;
6290 eldv |= IBX_ELD_VALIDB << 4;
6291 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6292 } else {
2582a850 6293 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6294 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6295 }
6296
3a9627f4
WF		 6297 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6298 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6299 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6300 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6301 } else
6302 I915_WRITE(aud_config, 0);
e0dac65e 6303
3a9627f4
WF		 6304 if (intel_eld_uptodate(connector,
6305 aud_cntrl_st2, eldv,
6306 aud_cntl_st, IBX_ELD_ADDRESS,
6307 hdmiw_hdmiedid))
6308 return;
6309
e0dac65e
WF		 6310 i = I915_READ(aud_cntrl_st2);
6311 i &= ~eldv;
6312 I915_WRITE(aud_cntrl_st2, i);
6313
6314 if (!eld[0])
6315 return;
6316
e0dac65e 6317 i = I915_READ(aud_cntl_st);
1202b4c6 6318 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6319 I915_WRITE(aud_cntl_st, i);
6320
6321 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6322 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6323 for (i = 0; i < len; i++)
6324 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6325
6326 i = I915_READ(aud_cntrl_st2);
6327 i |= eldv;
6328 I915_WRITE(aud_cntrl_st2, i);
6329}
6330
6331void intel_write_eld(struct drm_encoder *encoder,
6332 struct drm_display_mode *mode)
6333{
6334 struct drm_crtc *crtc = encoder->crtc;
6335 struct drm_connector *connector;
6336 struct drm_device *dev = encoder->dev;
6337 struct drm_i915_private *dev_priv = dev->dev_private;
6338
6339 connector = drm_select_eld(encoder, mode);
6340 if (!connector)
6341 return;
6342
6343 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6344 connector->base.id,
6345 drm_get_connector_name(connector),
6346 connector->encoder->base.id,
6347 drm_get_encoder_name(connector->encoder));
6348
6349 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6350
6351 if (dev_priv->display.write_eld)
6352 dev_priv->display.write_eld(connector, crtc);
6353}
6354
79e53945
JB		 6355/** Loads the palette/gamma unit for the CRTC with the prepared values */
6356void intel_crtc_load_lut(struct drm_crtc *crtc)
6357{
6358 struct drm_device *dev = crtc->dev;
6359 struct drm_i915_private *dev_priv = dev->dev_private;
6360 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6361 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6362 int i;
6363
6364 /* The clocks have to be on to load the palette. */
aed3f09d 6365 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6366 return;
6367
f2b115e6 6368 /* use legacy palette for Ironlake */
bad720ff 6369 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6370 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6371
79e53945
JB		 6372 for (i = 0; i < 256; i++) {
6373 I915_WRITE(palreg + 4 * i,
6374 (intel_crtc->lut_r[i] << 16) |
6375 (intel_crtc->lut_g[i] << 8) |
6376 intel_crtc->lut_b[i]);
6377 }
6378}
6379
560b85bb
CW		 6380static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6381{
6382 struct drm_device *dev = crtc->dev;
6383 struct drm_i915_private *dev_priv = dev->dev_private;
6384 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6385 bool visible = base != 0;
6386 u32 cntl;
6387
6388 if (intel_crtc->cursor_visible == visible)
6389 return;
6390
9db4a9c7 6391 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6392 if (visible) {
6393 /* On these chipsets we can only modify the base whilst
6394 * the cursor is disabled.
6395 */
9db4a9c7 6396 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6397
6398 cntl &= ~(CURSOR_FORMAT_MASK);
6399 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6400 cntl |= CURSOR_ENABLE |
6401 CURSOR_GAMMA_ENABLE |
6402 CURSOR_FORMAT_ARGB;
6403 } else
6404 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6405 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6406
6407 intel_crtc->cursor_visible = visible;
6408}
6409
6410static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6411{
6412 struct drm_device *dev = crtc->dev;
6413 struct drm_i915_private *dev_priv = dev->dev_private;
6414 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6415 int pipe = intel_crtc->pipe;
6416 bool visible = base != 0;
6417
6418 if (intel_crtc->cursor_visible != visible) {
548f245b 6419 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6420 if (base) {
6421 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6422 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6423 cntl |= pipe << 28; /* Connect to correct pipe */
6424 } else {
6425 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6426 cntl |= CURSOR_MODE_DISABLE;
6427 }
9db4a9c7 6428 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6429
6430 intel_crtc->cursor_visible = visible;
6431 }
6432 /* and commit changes on next vblank */
9db4a9c7 6433 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6434}
6435
65a21cd6
JB		 6436static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6437{
6438 struct drm_device *dev = crtc->dev;
6439 struct drm_i915_private *dev_priv = dev->dev_private;
6440 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6441 int pipe = intel_crtc->pipe;
6442 bool visible = base != 0;
6443
6444 if (intel_crtc->cursor_visible != visible) {
6445 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6446 if (base) {
6447 cntl &= ~CURSOR_MODE;
6448 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6449 } else {
6450 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6451 cntl |= CURSOR_MODE_DISABLE;
6452 }
86d3efce
VS		 6453 if (IS_HASWELL(dev))
6454 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6455 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6456
6457 intel_crtc->cursor_visible = visible;
6458 }
6459 /* and commit changes on next vblank */
6460 I915_WRITE(CURBASE_IVB(pipe), base);
6461}
6462
cda4b7d3 6463/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6464static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6465 bool on)
cda4b7d3
CW		 6466{
6467 struct drm_device *dev = crtc->dev;
6468 struct drm_i915_private *dev_priv = dev->dev_private;
6469 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6470 int pipe = intel_crtc->pipe;
6471 int x = intel_crtc->cursor_x;
6472 int y = intel_crtc->cursor_y;
560b85bb 6473 u32 base, pos;
cda4b7d3
CW		 6474 bool visible;
6475
6476 pos = 0;
6477
6b383a7f 6478 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6479 base = intel_crtc->cursor_addr;
6480 if (x > (int) crtc->fb->width)
6481 base = 0;
6482
6483 if (y > (int) crtc->fb->height)
6484 base = 0;
6485 } else
6486 base = 0;
6487
6488 if (x < 0) {
6489 if (x + intel_crtc->cursor_width < 0)
6490 base = 0;
6491
6492 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6493 x = -x;
6494 }
6495 pos |= x << CURSOR_X_SHIFT;
6496
6497 if (y < 0) {
6498 if (y + intel_crtc->cursor_height < 0)
6499 base = 0;
6500
6501 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6502 y = -y;
6503 }
6504 pos |= y << CURSOR_Y_SHIFT;
6505
6506 visible = base != 0;
560b85bb 6507 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6508 return;
6509
0cd83aa9 6510 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6511 I915_WRITE(CURPOS_IVB(pipe), pos);
6512 ivb_update_cursor(crtc, base);
6513 } else {
6514 I915_WRITE(CURPOS(pipe), pos);
6515 if (IS_845G(dev) || IS_I865G(dev))
6516 i845_update_cursor(crtc, base);
6517 else
6518 i9xx_update_cursor(crtc, base);
6519 }
cda4b7d3
CW		 6520}
6521
79e53945 6522static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6523 struct drm_file *file,
79e53945
JB		 6524 uint32_t handle,
6525 uint32_t width, uint32_t height)
6526{
6527 struct drm_device *dev = crtc->dev;
6528 struct drm_i915_private *dev_priv = dev->dev_private;
6529 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6530 struct drm_i915_gem_object *obj;
cda4b7d3 6531 uint32_t addr;
3f8bc370 6532 int ret;
79e53945 6533
79e53945
JB		 6534 /* if we want to turn off the cursor ignore width and height */
6535 if (!handle) {
28c97730 6536 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6537 addr = 0;
05394f39 6538 obj = NULL;
5004417d 6539 mutex_lock(&dev->struct_mutex);
3f8bc370 6540 goto finish;
79e53945
JB		 6541 }
6542
6543 /* Currently we only support 64x64 cursors */
6544 if (width != 64 || height != 64) {
6545 DRM_ERROR("we currently only support 64x64 cursors\n");
6546 return -EINVAL;
6547 }
6548
05394f39 6549 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6550 if (&obj->base == NULL)
79e53945
JB		 6551 return -ENOENT;
6552
05394f39 6553 if (obj->base.size < width * height * 4) {
79e53945 6554 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6555 ret = -ENOMEM;
6556 goto fail;
79e53945
JB		 6557 }
6558
71acb5eb 6559 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6560 mutex_lock(&dev->struct_mutex);
b295d1b6 6561 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6562 unsigned alignment;
6563
d9e86c0e
CW		 6564 if (obj->tiling_mode) {
6565 DRM_ERROR("cursor cannot be tiled\n");
6566 ret = -EINVAL;
6567 goto fail_locked;
6568 }
6569
693db184
CW		 6570 /* Note that the w/a also requires 2 PTE of padding following
6571 * the bo. We currently fill all unused PTE with the shadow
6572 * page and so we should always have valid PTE following the
6573 * cursor preventing the VT-d warning.
6574 */
6575 alignment = 0;
6576 if (need_vtd_wa(dev))
6577 alignment = 64*1024;
6578
6579 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6580 if (ret) {
6581 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6582 goto fail_locked;
e7b526bb
CW		 6583 }
6584
d9e86c0e
CW		 6585 ret = i915_gem_object_put_fence(obj);
6586 if (ret) {
2da3b9b9 6587 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6588 goto fail_unpin;
6589 }
6590
05394f39 6591 addr = obj->gtt_offset;
71acb5eb 6592 } else {
6eeefaf3 6593 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6594 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6595 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6596 align);
71acb5eb
DA		 6597 if (ret) {
6598 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6599 goto fail_locked;
71acb5eb 6600 }
05394f39 6601 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6602 }
6603
a6c45cf0 6604 if (IS_GEN2(dev))
14b60391
JB		 6605 I915_WRITE(CURSIZE, (height << 12) | width);
6606
3f8bc370 6607 finish:
3f8bc370 6608 if (intel_crtc->cursor_bo) {
b295d1b6 6609 if (dev_priv->info->cursor_needs_physical) {
05394f39 6610 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6611 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6612 } else
6613 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6614 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6615 }
80824003 6616
7f9872e0 6617 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6618
6619 intel_crtc->cursor_addr = addr;
05394f39 6620 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6621 intel_crtc->cursor_width = width;
6622 intel_crtc->cursor_height = height;
6623
6b383a7f 6624 intel_crtc_update_cursor(crtc, true);
3f8bc370 6625
79e53945 6626 return 0;
e7b526bb 6627fail_unpin:
05394f39 6628 i915_gem_object_unpin(obj);
7f9872e0 6629fail_locked:
34b8686e 6630 mutex_unlock(&dev->struct_mutex);
bc9025bd 6631fail:
05394f39 6632 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6633 return ret;
79e53945
JB		 6634}
6635
6636static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6637{
79e53945 6638 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6639
cda4b7d3
CW		 6640 intel_crtc->cursor_x = x;
6641 intel_crtc->cursor_y = y;
652c393a 6642
6b383a7f 6643 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6644
6645 return 0;
6646}
6647
6648/** Sets the color ramps on behalf of RandR */
6649void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6650 u16 blue, int regno)
6651{
6652 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6653
6654 intel_crtc->lut_r[regno] = red >> 8;
6655 intel_crtc->lut_g[regno] = green >> 8;
6656 intel_crtc->lut_b[regno] = blue >> 8;
6657}
6658
b8c00ac5
DA		 6659void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6660 u16 *blue, int regno)
6661{
6662 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6663
6664 *red = intel_crtc->lut_r[regno] << 8;
6665 *green = intel_crtc->lut_g[regno] << 8;
6666 *blue = intel_crtc->lut_b[regno] << 8;
6667}
6668
79e53945 6669static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6670 u16 *blue, uint32_t start, uint32_t size)
79e53945 6671{
7203425a 6672 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6673 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6674
7203425a 6675 for (i = start; i < end; i++) {
79e53945
JB		 6676 intel_crtc->lut_r[i] = red[i] >> 8;
6677 intel_crtc->lut_g[i] = green[i] >> 8;
6678 intel_crtc->lut_b[i] = blue[i] >> 8;
6679 }
6680
6681 intel_crtc_load_lut(crtc);
6682}
6683
79e53945
JB		 6684/* VESA 640x480x72Hz mode to set on the pipe */
6685static struct drm_display_mode load_detect_mode = {
6686 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6687 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6688};
6689
d2dff872
CW		 6690static struct drm_framebuffer *
6691intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6692 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6693 struct drm_i915_gem_object *obj)
6694{
6695 struct intel_framebuffer *intel_fb;
6696 int ret;
6697
6698 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6699 if (!intel_fb) {
6700 drm_gem_object_unreference_unlocked(&obj->base);
6701 return ERR_PTR(-ENOMEM);
6702 }
6703
6704 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6705 if (ret) {
6706 drm_gem_object_unreference_unlocked(&obj->base);
6707 kfree(intel_fb);
6708 return ERR_PTR(ret);
6709 }
6710
6711 return &intel_fb->base;
6712}
6713
6714static u32
6715intel_framebuffer_pitch_for_width(int width, int bpp)
6716{
6717 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6718 return ALIGN(pitch, 64);
6719}
6720
6721static u32
6722intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6723{
6724 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6725 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6726}
6727
6728static struct drm_framebuffer *
6729intel_framebuffer_create_for_mode(struct drm_device *dev,
6730 struct drm_display_mode *mode,
6731 int depth, int bpp)
6732{
6733 struct drm_i915_gem_object *obj;
0fed39bd 6734 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6735
6736 obj = i915_gem_alloc_object(dev,
6737 intel_framebuffer_size_for_mode(mode, bpp));
6738 if (obj == NULL)
6739 return ERR_PTR(-ENOMEM);
6740
6741 mode_cmd.width = mode->hdisplay;
6742 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6743 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6744 bpp);
5ca0c34a 6745 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6746
6747 return intel_framebuffer_create(dev, &mode_cmd, obj);
6748}
6749
6750static struct drm_framebuffer *
6751mode_fits_in_fbdev(struct drm_device *dev,
6752 struct drm_display_mode *mode)
6753{
6754 struct drm_i915_private *dev_priv = dev->dev_private;
6755 struct drm_i915_gem_object *obj;
6756 struct drm_framebuffer *fb;
6757
6758 if (dev_priv->fbdev == NULL)
6759 return NULL;
6760
6761 obj = dev_priv->fbdev->ifb.obj;
6762 if (obj == NULL)
6763 return NULL;
6764
6765 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6766 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6767 fb->bits_per_pixel))
d2dff872
CW		 6768 return NULL;
6769
01f2c773 6770 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6771 return NULL;
6772
6773 return fb;
6774}
6775
d2434ab7 6776bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6777 struct drm_display_mode *mode,
8261b191 6778 struct intel_load_detect_pipe *old)
79e53945
JB		 6779{
6780 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6781 struct intel_encoder *intel_encoder =
6782 intel_attached_encoder(connector);
79e53945 6783 struct drm_crtc *possible_crtc;
4ef69c7a 6784 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6785 struct drm_crtc *crtc = NULL;
6786 struct drm_device *dev = encoder->dev;
94352cf9 6787 struct drm_framebuffer *fb;
79e53945
JB		 6788 int i = -1;
6789
d2dff872
CW		 6790 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6791 connector->base.id, drm_get_connector_name(connector),
6792 encoder->base.id, drm_get_encoder_name(encoder));
6793
79e53945
JB		 6794 /*
6795 * Algorithm gets a little messy:
7a5e4805 6796 *
79e53945
JB		 6797 * - if the connector already has an assigned crtc, use it (but make
6798 * sure it's on first)
7a5e4805 6799 *
79e53945
JB		 6800 * - try to find the first unused crtc that can drive this connector,
6801 * and use that if we find one
79e53945
JB		 6802 */
6803
6804 /* See if we already have a CRTC for this connector */
6805 if (encoder->crtc) {
6806 crtc = encoder->crtc;
8261b191 6807
7b24056b
DV		 6808 mutex_lock(&crtc->mutex);
6809
24218aac 6810 old->dpms_mode = connector->dpms;
8261b191
CW		 6811 old->load_detect_temp = false;
6812
6813 /* Make sure the crtc and connector are running */
24218aac
DV		 6814 if (connector->dpms != DRM_MODE_DPMS_ON)
6815 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6816
7173188d 6817 return true;
79e53945
JB		 6818 }
6819
6820 /* Find an unused one (if possible) */
6821 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6822 i++;
6823 if (!(encoder->possible_crtcs & (1 << i)))
6824 continue;
6825 if (!possible_crtc->enabled) {
6826 crtc = possible_crtc;
6827 break;
6828 }
79e53945
JB		 6829 }
6830
6831 /*
6832 * If we didn't find an unused CRTC, don't use any.
6833 */
6834 if (!crtc) {
7173188d
CW		 6835 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6836 return false;
79e53945
JB		 6837 }
6838
7b24056b 6839 mutex_lock(&crtc->mutex);
fc303101
DV		 6840 intel_encoder->new_crtc = to_intel_crtc(crtc);
6841 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6842
6843 intel_crtc = to_intel_crtc(crtc);
24218aac 6844 old->dpms_mode = connector->dpms;
8261b191 6845 old->load_detect_temp = true;
d2dff872 6846 old->release_fb = NULL;
79e53945 6847
6492711d
CW		 6848 if (!mode)
6849 mode = &load_detect_mode;
79e53945 6850
d2dff872
CW		 6851 /* We need a framebuffer large enough to accommodate all accesses
6852 * that the plane may generate whilst we perform load detection.
6853 * We can not rely on the fbcon either being present (we get called
6854 * during its initialisation to detect all boot displays, or it may
6855 * not even exist) or that it is large enough to satisfy the
6856 * requested mode.
6857 */
94352cf9
DV		 6858 fb = mode_fits_in_fbdev(dev, mode);
6859 if (fb == NULL) {
d2dff872 6860 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6861 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6862 old->release_fb = fb;
d2dff872
CW		 6863 } else
6864 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6865 if (IS_ERR(fb)) {
d2dff872 6866 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6867 mutex_unlock(&crtc->mutex);
0e8b3d3e 6868 return false;
79e53945 6869 }
79e53945 6870
c0c36b94 6871 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6872 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6873 if (old->release_fb)
6874 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6875 mutex_unlock(&crtc->mutex);
0e8b3d3e 6876 return false;
79e53945 6877 }
7173188d 6878
79e53945 6879 /* let the connector get through one full cycle before testing */
9d0498a2 6880 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6881 return true;
79e53945
JB		 6882}
6883
d2434ab7 6884void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6885 struct intel_load_detect_pipe *old)
79e53945 6886{
d2434ab7
DV		 6887 struct intel_encoder *intel_encoder =
6888 intel_attached_encoder(connector);
4ef69c7a 6889 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6890 struct drm_crtc *crtc = encoder->crtc;
79e53945 6891
d2dff872
CW		 6892 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6893 connector->base.id, drm_get_connector_name(connector),
6894 encoder->base.id, drm_get_encoder_name(encoder));
6895
8261b191 6896 if (old->load_detect_temp) {
fc303101
DV		 6897 to_intel_connector(connector)->new_encoder = NULL;
6898 intel_encoder->new_crtc = NULL;
6899 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6900
36206361
DV		 6901 if (old->release_fb) {
6902 drm_framebuffer_unregister_private(old->release_fb);
6903 drm_framebuffer_unreference(old->release_fb);
6904 }
d2dff872 6905
67c96400 6906 mutex_unlock(&crtc->mutex);
0622a53c 6907 return;
79e53945
JB		 6908 }
6909
c751ce4f 6910 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6911 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6912 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6913
6914 mutex_unlock(&crtc->mutex);
79e53945
JB		 6915}
6916
6917/* Returns the clock of the currently programmed mode of the given pipe. */
6918static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6919{
6920 struct drm_i915_private *dev_priv = dev->dev_private;
6921 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6922 int pipe = intel_crtc->pipe;
548f245b 6923 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6924 u32 fp;
6925 intel_clock_t clock;
6926
6927 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6928 fp = I915_READ(FP0(pipe));
79e53945 6929 else
39adb7a5 6930 fp = I915_READ(FP1(pipe));
79e53945
JB		 6931
6932 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6933 if (IS_PINEVIEW(dev)) {
6934 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6935 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6936 } else {
6937 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6938 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6939 }
6940
a6c45cf0 6941 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6942 if (IS_PINEVIEW(dev))
6943 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6944 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6945 else
6946 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6947 DPLL_FPA01_P1_POST_DIV_SHIFT);
6948
6949 switch (dpll & DPLL_MODE_MASK) {
6950 case DPLLB_MODE_DAC_SERIAL:
6951 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6952 5 : 10;
6953 break;
6954 case DPLLB_MODE_LVDS:
6955 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6956 7 : 14;
6957 break;
6958 default:
28c97730 6959 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6960 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6961 return 0;
6962 }
6963
6964 /* XXX: Handle the 100Mhz refclk */
2177832f 6965 intel_clock(dev, 96000, &clock);
79e53945
JB		 6966 } else {
6967 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6968
6969 if (is_lvds) {
6970 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6971 DPLL_FPA01_P1_POST_DIV_SHIFT);
6972 clock.p2 = 14;
6973
6974 if ((dpll & PLL_REF_INPUT_MASK) ==
6975 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6976 /* XXX: might not be 66MHz */
2177832f 6977 intel_clock(dev, 66000, &clock);
79e53945 6978 } else
2177832f 6979 intel_clock(dev, 48000, &clock);
79e53945
JB		 6980 } else {
6981 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6982 clock.p1 = 2;
6983 else {
6984 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6985 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6986 }
6987 if (dpll & PLL_P2_DIVIDE_BY_4)
6988 clock.p2 = 4;
6989 else
6990 clock.p2 = 2;
6991
2177832f 6992 intel_clock(dev, 48000, &clock);
79e53945
JB		 6993 }
6994 }
6995
6996 /* XXX: It would be nice to validate the clocks, but we can't reuse
6997 * i830PllIsValid() because it relies on the xf86_config connector
6998 * configuration being accurate, which it isn't necessarily.
6999 */
7000
7001 return clock.dot;
7002}
7003
7004/** Returns the currently programmed mode of the given pipe. */
7005struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7006 struct drm_crtc *crtc)
7007{
548f245b 7008 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 7009 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 7010 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 7011 struct drm_display_mode *mode;
fe2b8f9d
PZ		 7012 int htot = I915_READ(HTOTAL(cpu_transcoder));
7013 int hsync = I915_READ(HSYNC(cpu_transcoder));
7014 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7015 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 7016
7017 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7018 if (!mode)
7019 return NULL;
7020
7021 mode->clock = intel_crtc_clock_get(dev, crtc);
7022 mode->hdisplay = (htot & 0xffff) + 1;
7023 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7024 mode->hsync_start = (hsync & 0xffff) + 1;
7025 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7026 mode->vdisplay = (vtot & 0xffff) + 1;
7027 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7028 mode->vsync_start = (vsync & 0xffff) + 1;
7029 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7030
7031 drm_mode_set_name(mode);
79e53945
JB		 7032
7033 return mode;
7034}
7035
3dec0095 7036static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7037{
7038 struct drm_device *dev = crtc->dev;
7039 drm_i915_private_t *dev_priv = dev->dev_private;
7040 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7041 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7042 int dpll_reg = DPLL(pipe);
7043 int dpll;
652c393a 7044
bad720ff 7045 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7046 return;
7047
7048 if (!dev_priv->lvds_downclock_avail)
7049 return;
7050
dbdc6479 7051 dpll = I915_READ(dpll_reg);
652c393a 7052 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7053 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7054
8ac5a6d5 7055 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7056
7057 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7058 I915_WRITE(dpll_reg, dpll);
9d0498a2 7059 intel_wait_for_vblank(dev, pipe);
dbdc6479 7060
652c393a
JB		 7061 dpll = I915_READ(dpll_reg);
7062 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7063 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7064 }
652c393a
JB		 7065}
7066
7067static void intel_decrease_pllclock(struct drm_crtc *crtc)
7068{
7069 struct drm_device *dev = crtc->dev;
7070 drm_i915_private_t *dev_priv = dev->dev_private;
7071 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7072
bad720ff 7073 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7074 return;
7075
7076 if (!dev_priv->lvds_downclock_avail)
7077 return;
7078
7079 /*
7080 * Since this is called by a timer, we should never get here in
7081 * the manual case.
7082 */
7083 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7084 int pipe = intel_crtc->pipe;
7085 int dpll_reg = DPLL(pipe);
7086 int dpll;
f6e5b160 7087
44d98a61 7088 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7089
8ac5a6d5 7090 assert_panel_unlocked(dev_priv, pipe);
652c393a 7091
dc257cf1 7092 dpll = I915_READ(dpll_reg);
652c393a
JB		 7093 dpll |= DISPLAY_RATE_SELECT_FPA1;
7094 I915_WRITE(dpll_reg, dpll);
9d0498a2 7095 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7096 dpll = I915_READ(dpll_reg);
7097 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7098 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7099 }
7100
7101}
7102
f047e395
CW		 7103void intel_mark_busy(struct drm_device *dev)
7104{
f047e395
CW		 7105 i915_update_gfx_val(dev->dev_private);
7106}
7107
7108void intel_mark_idle(struct drm_device *dev)
652c393a 7109{
652c393a 7110 struct drm_crtc *crtc;
652c393a
JB		 7111
7112 if (!i915_powersave)
7113 return;
7114
652c393a 7115 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7116 if (!crtc->fb)
7117 continue;
7118
725a5b54 7119 intel_decrease_pllclock(crtc);
652c393a 7120 }
652c393a
JB		 7121}
7122
725a5b54 7123void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
652c393a 7124{
f047e395
CW		 7125 struct drm_device *dev = obj->base.dev;
7126 struct drm_crtc *crtc;
652c393a 7127
f047e395 7128 if (!i915_powersave)
acb87dfb
CW		 7129 return;
7130
652c393a
JB		 7131 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7132 if (!crtc->fb)
7133 continue;
7134
f047e395 7135 if (to_intel_framebuffer(crtc->fb)->obj == obj)
725a5b54 7136 intel_increase_pllclock(crtc);
652c393a
JB		 7137 }
7138}
7139
79e53945
JB		 7140static void intel_crtc_destroy(struct drm_crtc *crtc)
7141{
7142 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7143 struct drm_device *dev = crtc->dev;
7144 struct intel_unpin_work *work;
7145 unsigned long flags;
7146
7147 spin_lock_irqsave(&dev->event_lock, flags);
7148 work = intel_crtc->unpin_work;
7149 intel_crtc->unpin_work = NULL;
7150 spin_unlock_irqrestore(&dev->event_lock, flags);
7151
7152 if (work) {
7153 cancel_work_sync(&work->work);
7154 kfree(work);
7155 }
79e53945
JB		 7156
7157 drm_crtc_cleanup(crtc);
67e77c5a 7158
79e53945
JB		 7159 kfree(intel_crtc);
7160}
7161
6b95a207
KH		 7162static void intel_unpin_work_fn(struct work_struct *__work)
7163{
7164 struct intel_unpin_work *work =
7165 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7166 struct drm_device *dev = work->crtc->dev;
6b95a207 7167
b4a98e57 7168 mutex_lock(&dev->struct_mutex);
1690e1eb 7169 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7170 drm_gem_object_unreference(&work->pending_flip_obj->base);
7171 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7172
b4a98e57
CW		 7173 intel_update_fbc(dev);
7174 mutex_unlock(&dev->struct_mutex);
7175
7176 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7177 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7178
6b95a207
KH		 7179 kfree(work);
7180}
7181
1afe3e9d 7182static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7183 struct drm_crtc *crtc)
6b95a207
KH		 7184{
7185 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7186 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7187 struct intel_unpin_work *work;
6b95a207
KH		 7188 unsigned long flags;
7189
7190 /* Ignore early vblank irqs */
7191 if (intel_crtc == NULL)
7192 return;
7193
7194 spin_lock_irqsave(&dev->event_lock, flags);
7195 work = intel_crtc->unpin_work;
e7d841ca
CW		 7196
7197 /* Ensure we don't miss a work->pending update ... */
7198 smp_rmb();
7199
7200 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7201 spin_unlock_irqrestore(&dev->event_lock, flags);
7202 return;
7203 }
7204
e7d841ca
CW		 7205 /* and that the unpin work is consistent wrt ->pending. */
7206 smp_rmb();
7207
6b95a207 7208 intel_crtc->unpin_work = NULL;
6b95a207 7209
45a066eb
RC		 7210 if (work->event)
7211 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7212
0af7e4df
MK		 7213 drm_vblank_put(dev, intel_crtc->pipe);
7214
6b95a207
KH		 7215 spin_unlock_irqrestore(&dev->event_lock, flags);
7216
2c10d571 7217 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7218
7219 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7220
7221 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7222}
7223
1afe3e9d
JB		 7224void intel_finish_page_flip(struct drm_device *dev, int pipe)
7225{
7226 drm_i915_private_t *dev_priv = dev->dev_private;
7227 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7228
49b14a5c 7229 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7230}
7231
7232void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7233{
7234 drm_i915_private_t *dev_priv = dev->dev_private;
7235 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7236
49b14a5c 7237 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7238}
7239
6b95a207
KH		 7240void intel_prepare_page_flip(struct drm_device *dev, int plane)
7241{
7242 drm_i915_private_t *dev_priv = dev->dev_private;
7243 struct intel_crtc *intel_crtc =
7244 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7245 unsigned long flags;
7246
e7d841ca
CW		 7247 /* NB: An MMIO update of the plane base pointer will also
7248 * generate a page-flip completion irq, i.e. every modeset
7249 * is also accompanied by a spurious intel_prepare_page_flip().
7250 */
6b95a207 7251 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7252 if (intel_crtc->unpin_work)
7253 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7254 spin_unlock_irqrestore(&dev->event_lock, flags);
7255}
7256
e7d841ca
CW		 7257inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7258{
7259 /* Ensure that the work item is consistent when activating it ... */
7260 smp_wmb();
7261 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7262 /* and that it is marked active as soon as the irq could fire. */
7263 smp_wmb();
7264}
7265
8c9f3aaf
JB		 7266static int intel_gen2_queue_flip(struct drm_device *dev,
7267 struct drm_crtc *crtc,
7268 struct drm_framebuffer *fb,
7269 struct drm_i915_gem_object *obj)
7270{
7271 struct drm_i915_private *dev_priv = dev->dev_private;
7272 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7273 u32 flip_mask;
6d90c952 7274 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7275 int ret;
7276
6d90c952 7277 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7278 if (ret)
83d4092b 7279 goto err;
8c9f3aaf 7280
6d90c952 7281 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7282 if (ret)
83d4092b 7283 goto err_unpin;
8c9f3aaf
JB		 7284
7285 /* Can't queue multiple flips, so wait for the previous
7286 * one to finish before executing the next.
7287 */
7288 if (intel_crtc->plane)
7289 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7290 else
7291 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7292 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7293 intel_ring_emit(ring, MI_NOOP);
7294 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7295 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7296 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7297 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 7298 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7299
7300 intel_mark_page_flip_active(intel_crtc);
6d90c952 7301 intel_ring_advance(ring);
83d4092b
CW		 7302 return 0;
7303
7304err_unpin:
7305 intel_unpin_fb_obj(obj);
7306err:
8c9f3aaf
JB		 7307 return ret;
7308}
7309
7310static int intel_gen3_queue_flip(struct drm_device *dev,
7311 struct drm_crtc *crtc,
7312 struct drm_framebuffer *fb,
7313 struct drm_i915_gem_object *obj)
7314{
7315 struct drm_i915_private *dev_priv = dev->dev_private;
7316 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7317 u32 flip_mask;
6d90c952 7318 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7319 int ret;
7320
6d90c952 7321 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7322 if (ret)
83d4092b 7323 goto err;
8c9f3aaf 7324
6d90c952 7325 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7326 if (ret)
83d4092b 7327 goto err_unpin;
8c9f3aaf
JB		 7328
7329 if (intel_crtc->plane)
7330 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7331 else
7332 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7333 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7334 intel_ring_emit(ring, MI_NOOP);
7335 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7336 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7337 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7338 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7339 intel_ring_emit(ring, MI_NOOP);
7340
e7d841ca 7341 intel_mark_page_flip_active(intel_crtc);
6d90c952 7342 intel_ring_advance(ring);
83d4092b
CW		 7343 return 0;
7344
7345err_unpin:
7346 intel_unpin_fb_obj(obj);
7347err:
8c9f3aaf
JB		 7348 return ret;
7349}
7350
7351static int intel_gen4_queue_flip(struct drm_device *dev,
7352 struct drm_crtc *crtc,
7353 struct drm_framebuffer *fb,
7354 struct drm_i915_gem_object *obj)
7355{
7356 struct drm_i915_private *dev_priv = dev->dev_private;
7357 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7358 uint32_t pf, pipesrc;
6d90c952 7359 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7360 int ret;
7361
6d90c952 7362 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7363 if (ret)
83d4092b 7364 goto err;
8c9f3aaf 7365
6d90c952 7366 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7367 if (ret)
83d4092b 7368 goto err_unpin;
8c9f3aaf
JB		 7369
7370 /* i965+ uses the linear or tiled offsets from the
7371 * Display Registers (which do not change across a page-flip)
7372 * so we need only reprogram the base address.
7373 */
6d90c952
DV		 7374 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7375 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7376 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7377 intel_ring_emit(ring,
7378 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7379 obj->tiling_mode);
8c9f3aaf
JB		 7380
7381 /* XXX Enabling the panel-fitter across page-flip is so far
7382 * untested on non-native modes, so ignore it for now.
7383 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7384 */
7385 pf = 0;
7386 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7387 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7388
7389 intel_mark_page_flip_active(intel_crtc);
6d90c952 7390 intel_ring_advance(ring);
83d4092b
CW		 7391 return 0;
7392
7393err_unpin:
7394 intel_unpin_fb_obj(obj);
7395err:
8c9f3aaf
JB		 7396 return ret;
7397}
7398
7399static int intel_gen6_queue_flip(struct drm_device *dev,
7400 struct drm_crtc *crtc,
7401 struct drm_framebuffer *fb,
7402 struct drm_i915_gem_object *obj)
7403{
7404 struct drm_i915_private *dev_priv = dev->dev_private;
7405 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7406 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7407 uint32_t pf, pipesrc;
7408 int ret;
7409
6d90c952 7410 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7411 if (ret)
83d4092b 7412 goto err;
8c9f3aaf 7413
6d90c952 7414 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7415 if (ret)
83d4092b 7416 goto err_unpin;
8c9f3aaf 7417
6d90c952
DV		 7418 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7419 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7420 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7421 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7422
dc257cf1
DV		 7423 /* Contrary to the suggestions in the documentation,
7424 * "Enable Panel Fitter" does not seem to be required when page
7425 * flipping with a non-native mode, and worse causes a normal
7426 * modeset to fail.
7427 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7428 */
7429 pf = 0;
8c9f3aaf 7430 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7431 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7432
7433 intel_mark_page_flip_active(intel_crtc);
6d90c952 7434 intel_ring_advance(ring);
83d4092b
CW		 7435 return 0;
7436
7437err_unpin:
7438 intel_unpin_fb_obj(obj);
7439err:
8c9f3aaf
JB		 7440 return ret;
7441}
7442
7c9017e5
JB		 7443/*
7444 * On gen7 we currently use the blit ring because (in early silicon at least)
7445 * the render ring doesn't give us interrpts for page flip completion, which
7446 * means clients will hang after the first flip is queued. Fortunately the
7447 * blit ring generates interrupts properly, so use it instead.
7448 */
7449static int intel_gen7_queue_flip(struct drm_device *dev,
7450 struct drm_crtc *crtc,
7451 struct drm_framebuffer *fb,
7452 struct drm_i915_gem_object *obj)
7453{
7454 struct drm_i915_private *dev_priv = dev->dev_private;
7455 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7456 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7457 uint32_t plane_bit = 0;
7c9017e5
JB		 7458 int ret;
7459
7460 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7461 if (ret)
83d4092b 7462 goto err;
7c9017e5 7463
cb05d8de
DV		 7464 switch(intel_crtc->plane) {
7465 case PLANE_A:
7466 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7467 break;
7468 case PLANE_B:
7469 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7470 break;
7471 case PLANE_C:
7472 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7473 break;
7474 default:
7475 WARN_ONCE(1, "unknown plane in flip command\n");
7476 ret = -ENODEV;
ab3951eb 7477 goto err_unpin;
cb05d8de
DV		 7478 }
7479
7c9017e5
JB		 7480 ret = intel_ring_begin(ring, 4);
7481 if (ret)
83d4092b 7482 goto err_unpin;
7c9017e5 7483
cb05d8de 7484 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7485 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7486 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7487 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7488
7489 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7490 intel_ring_advance(ring);
83d4092b
CW		 7491 return 0;
7492
7493err_unpin:
7494 intel_unpin_fb_obj(obj);
7495err:
7c9017e5
JB		 7496 return ret;
7497}
7498
8c9f3aaf
JB		 7499static int intel_default_queue_flip(struct drm_device *dev,
7500 struct drm_crtc *crtc,
7501 struct drm_framebuffer *fb,
7502 struct drm_i915_gem_object *obj)
7503{
7504 return -ENODEV;
7505}
7506
6b95a207
KH		 7507static int intel_crtc_page_flip(struct drm_crtc *crtc,
7508 struct drm_framebuffer *fb,
7509 struct drm_pending_vblank_event *event)
7510{
7511 struct drm_device *dev = crtc->dev;
7512 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7513 struct drm_framebuffer *old_fb = crtc->fb;
7514 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7515 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7516 struct intel_unpin_work *work;
8c9f3aaf 7517 unsigned long flags;
52e68630 7518 int ret;
6b95a207 7519
e6a595d2
VS		 7520 /* Can't change pixel format via MI display flips. */
7521 if (fb->pixel_format != crtc->fb->pixel_format)
7522 return -EINVAL;
7523
7524 /*
7525 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7526 * Note that pitch changes could also affect these register.
7527 */
7528 if (INTEL_INFO(dev)->gen > 3 &&
7529 (fb->offsets[0] != crtc->fb->offsets[0] ||
7530 fb->pitches[0] != crtc->fb->pitches[0]))
7531 return -EINVAL;
7532
6b95a207
KH		 7533 work = kzalloc(sizeof *work, GFP_KERNEL);
7534 if (work == NULL)
7535 return -ENOMEM;
7536
6b95a207 7537 work->event = event;
b4a98e57 7538 work->crtc = crtc;
4a35f83b 7539 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7540 INIT_WORK(&work->work, intel_unpin_work_fn);
7541
7317c75e
JB		 7542 ret = drm_vblank_get(dev, intel_crtc->pipe);
7543 if (ret)
7544 goto free_work;
7545
6b95a207
KH		 7546 /* We borrow the event spin lock for protecting unpin_work */
7547 spin_lock_irqsave(&dev->event_lock, flags);
7548 if (intel_crtc->unpin_work) {
7549 spin_unlock_irqrestore(&dev->event_lock, flags);
7550 kfree(work);
7317c75e 7551 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7552
7553 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7554 return -EBUSY;
7555 }
7556 intel_crtc->unpin_work = work;
7557 spin_unlock_irqrestore(&dev->event_lock, flags);
7558
b4a98e57
CW		 7559 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7560 flush_workqueue(dev_priv->wq);
7561
79158103
CW		 7562 ret = i915_mutex_lock_interruptible(dev);
7563 if (ret)
7564 goto cleanup;
6b95a207 7565
75dfca80 7566 /* Reference the objects for the scheduled work. */
05394f39
CW		 7567 drm_gem_object_reference(&work->old_fb_obj->base);
7568 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7569
7570 crtc->fb = fb;
96b099fd 7571
e1f99ce6 7572 work->pending_flip_obj = obj;
e1f99ce6 7573
4e5359cd
SF		 7574 work->enable_stall_check = true;
7575
b4a98e57 7576 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7577 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7578
8c9f3aaf
JB		 7579 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7580 if (ret)
7581 goto cleanup_pending;
6b95a207 7582
7782de3b 7583 intel_disable_fbc(dev);
f047e395 7584 intel_mark_fb_busy(obj);
6b95a207
KH		 7585 mutex_unlock(&dev->struct_mutex);
7586
e5510fac
JB		 7587 trace_i915_flip_request(intel_crtc->plane, obj);
7588
6b95a207 7589 return 0;
96b099fd 7590
8c9f3aaf 7591cleanup_pending:
b4a98e57 7592 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7593 crtc->fb = old_fb;
05394f39
CW		 7594 drm_gem_object_unreference(&work->old_fb_obj->base);
7595 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7596 mutex_unlock(&dev->struct_mutex);
7597
79158103 7598cleanup:
96b099fd
CW		 7599 spin_lock_irqsave(&dev->event_lock, flags);
7600 intel_crtc->unpin_work = NULL;
7601 spin_unlock_irqrestore(&dev->event_lock, flags);
7602
7317c75e
JB		 7603 drm_vblank_put(dev, intel_crtc->pipe);
7604free_work:
96b099fd
CW		 7605 kfree(work);
7606
7607 return ret;
6b95a207
KH		 7608}
7609
f6e5b160 7610static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7611 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7612 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7613};
7614
6ed0f796 7615bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7616{
6ed0f796
DV		 7617 struct intel_encoder *other_encoder;
7618 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7619
6ed0f796
DV		 7620 if (WARN_ON(!crtc))
7621 return false;
7622
7623 list_for_each_entry(other_encoder,
7624 &crtc->dev->mode_config.encoder_list,
7625 base.head) {
7626
7627 if (&other_encoder->new_crtc->base != crtc ||
7628 encoder == other_encoder)
7629 continue;
7630 else
7631 return true;
f47166d2
CW		 7632 }
7633
6ed0f796
DV		 7634 return false;
7635}
47f1c6c9 7636
50f56119
DV		 7637static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7638 struct drm_crtc *crtc)
7639{
7640 struct drm_device *dev;
7641 struct drm_crtc *tmp;
7642 int crtc_mask = 1;
47f1c6c9 7643
50f56119 7644 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7645
50f56119 7646 dev = crtc->dev;
47f1c6c9 7647
50f56119
DV		 7648 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7649 if (tmp == crtc)
7650 break;
7651 crtc_mask <<= 1;
7652 }
47f1c6c9 7653
50f56119
DV		 7654 if (encoder->possible_crtcs & crtc_mask)
7655 return true;
7656 return false;
47f1c6c9 7657}
79e53945 7658
9a935856
DV		 7659/**
7660 * intel_modeset_update_staged_output_state
7661 *
7662 * Updates the staged output configuration state, e.g. after we've read out the
7663 * current hw state.
7664 */
7665static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7666{
9a935856
DV		 7667 struct intel_encoder *encoder;
7668 struct intel_connector *connector;
f6e5b160 7669
9a935856
DV		 7670 list_for_each_entry(connector, &dev->mode_config.connector_list,
7671 base.head) {
7672 connector->new_encoder =
7673 to_intel_encoder(connector->base.encoder);
7674 }
f6e5b160 7675
9a935856
DV		 7676 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7677 base.head) {
7678 encoder->new_crtc =
7679 to_intel_crtc(encoder->base.crtc);
7680 }
f6e5b160
CW		 7681}
7682
9a935856
DV		 7683/**
7684 * intel_modeset_commit_output_state
7685 *
7686 * This function copies the stage display pipe configuration to the real one.
7687 */
7688static void intel_modeset_commit_output_state(struct drm_device *dev)
7689{
7690 struct intel_encoder *encoder;
7691 struct intel_connector *connector;
f6e5b160 7692
9a935856
DV		 7693 list_for_each_entry(connector, &dev->mode_config.connector_list,
7694 base.head) {
7695 connector->base.encoder = &connector->new_encoder->base;
7696 }
f6e5b160 7697
9a935856
DV		 7698 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7699 base.head) {
7700 encoder->base.crtc = &encoder->new_crtc->base;
7701 }
7702}
7703
4e53c2e0
DV		 7704static int
7705pipe_config_set_bpp(struct drm_crtc *crtc,
7706 struct drm_framebuffer *fb,
7707 struct intel_crtc_config *pipe_config)
7708{
7709 struct drm_device *dev = crtc->dev;
7710 struct drm_connector *connector;
7711 int bpp;
7712
d42264b1
DV		 7713 switch (fb->pixel_format) {
7714 case DRM_FORMAT_C8:
4e53c2e0
DV		 7715 bpp = 8*3; /* since we go through a colormap */
7716 break;
d42264b1
DV		 7717 case DRM_FORMAT_XRGB1555:
7718 case DRM_FORMAT_ARGB1555:
7719 /* checked in intel_framebuffer_init already */
7720 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7721 return -EINVAL;
7722 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 7723 bpp = 6*3; /* min is 18bpp */
7724 break;
d42264b1
DV		 7725 case DRM_FORMAT_XBGR8888:
7726 case DRM_FORMAT_ABGR8888:
7727 /* checked in intel_framebuffer_init already */
7728 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7729 return -EINVAL;
7730 case DRM_FORMAT_XRGB8888:
7731 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 7732 bpp = 8*3;
7733 break;
d42264b1
DV		 7734 case DRM_FORMAT_XRGB2101010:
7735 case DRM_FORMAT_ARGB2101010:
7736 case DRM_FORMAT_XBGR2101010:
7737 case DRM_FORMAT_ABGR2101010:
7738 /* checked in intel_framebuffer_init already */
7739 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 7740 return -EINVAL;
4e53c2e0
DV		 7741 bpp = 10*3;
7742 break;
baba133a 7743 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 7744 default:
7745 DRM_DEBUG_KMS("unsupported depth\n");
7746 return -EINVAL;
7747 }
7748
4e53c2e0
DV		 7749 pipe_config->pipe_bpp = bpp;
7750
7751 /* Clamp display bpp to EDID value */
7752 list_for_each_entry(connector, &dev->mode_config.connector_list,
7753 head) {
7754 if (connector->encoder && connector->encoder->crtc != crtc)
7755 continue;
7756
7757 /* Don't use an invalid EDID bpc value */
7758 if (connector->display_info.bpc &&
7759 connector->display_info.bpc * 3 < bpp) {
7760 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7761 bpp, connector->display_info.bpc*3);
7762 pipe_config->pipe_bpp = connector->display_info.bpc*3;
7763 }
996a2239
DV		 7764
7765 /* Clamp bpp to 8 on screens without EDID 1.4 */
7766 if (connector->display_info.bpc == 0 && bpp > 24) {
7767 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7768 bpp);
7769 pipe_config->pipe_bpp = 24;
7770 }
4e53c2e0
DV		 7771 }
7772
7773 return bpp;
7774}
7775
b8cecdf5
DV		 7776static struct intel_crtc_config *
7777intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 7778 struct drm_framebuffer *fb,
b8cecdf5 7779 struct drm_display_mode *mode)
ee7b9f93 7780{
7758a113 7781 struct drm_device *dev = crtc->dev;
7758a113
DV		 7782 struct drm_encoder_helper_funcs *encoder_funcs;
7783 struct intel_encoder *encoder;
b8cecdf5 7784 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 7785 int plane_bpp, ret = -EINVAL;
7786 bool retry = true;
ee7b9f93 7787
b8cecdf5
DV		 7788 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7789 if (!pipe_config)
7758a113
DV		 7790 return ERR_PTR(-ENOMEM);
7791
b8cecdf5
DV		 7792 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7793 drm_mode_copy(&pipe_config->requested_mode, mode);
7794
4e53c2e0
DV		 7795 plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
7796 if (plane_bpp < 0)
7797 goto fail;
7798
e29c22c0 7799encoder_retry:
7758a113
DV		 7800 /* Pass our mode to the connectors and the CRTC to give them a chance to
7801 * adjust it according to limitations or connector properties, and also
7802 * a chance to reject the mode entirely.
47f1c6c9 7803 */
7758a113
DV		 7804 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7805 base.head) {
47f1c6c9 7806
7758a113
DV		 7807 if (&encoder->new_crtc->base != crtc)
7808 continue;
7ae89233
DV		 7809
7810 if (encoder->compute_config) {
7811 if (!(encoder->compute_config(encoder, pipe_config))) {
7812 DRM_DEBUG_KMS("Encoder config failure\n");
7813 goto fail;
7814 }
7815
7816 continue;
7817 }
7818
7758a113 7819 encoder_funcs = encoder->base.helper_private;
b8cecdf5
DV		 7820 if (!(encoder_funcs->mode_fixup(&encoder->base,
7821 &pipe_config->requested_mode,
7822 &pipe_config->adjusted_mode))) {
7758a113
DV		 7823 DRM_DEBUG_KMS("Encoder fixup failed\n");
7824 goto fail;
7825 }
ee7b9f93 7826 }
47f1c6c9 7827
e29c22c0
DV		 7828 ret = intel_crtc_compute_config(crtc, pipe_config);
7829 if (ret < 0) {
7758a113
DV		 7830 DRM_DEBUG_KMS("CRTC fixup failed\n");
7831 goto fail;
ee7b9f93 7832 }
e29c22c0
DV		 7833
7834 if (ret == RETRY) {
7835 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7836 ret = -EINVAL;
7837 goto fail;
7838 }
7839
7840 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7841 retry = false;
7842 goto encoder_retry;
7843 }
7844
7758a113 7845 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
47f1c6c9 7846
4e53c2e0
DV		 7847 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7848 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7849 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7850
b8cecdf5 7851 return pipe_config;
7758a113 7852fail:
b8cecdf5 7853 kfree(pipe_config);
e29c22c0 7854 return ERR_PTR(ret);
ee7b9f93 7855}
47f1c6c9 7856
e2e1ed41
DV		 7857/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7858 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7859static void
7860intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7861 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7862{
7863 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7864 struct drm_device *dev = crtc->dev;
7865 struct intel_encoder *encoder;
7866 struct intel_connector *connector;
7867 struct drm_crtc *tmp_crtc;
79e53945 7868
e2e1ed41 7869 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7870
e2e1ed41
DV		 7871 /* Check which crtcs have changed outputs connected to them, these need
7872 * to be part of the prepare_pipes mask. We don't (yet) support global
7873 * modeset across multiple crtcs, so modeset_pipes will only have one
7874 * bit set at most. */
7875 list_for_each_entry(connector, &dev->mode_config.connector_list,
7876 base.head) {
7877 if (connector->base.encoder == &connector->new_encoder->base)
7878 continue;
79e53945 7879
e2e1ed41
DV		 7880 if (connector->base.encoder) {
7881 tmp_crtc = connector->base.encoder->crtc;
7882
7883 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7884 }
7885
7886 if (connector->new_encoder)
7887 *prepare_pipes |=
7888 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7889 }
7890
e2e1ed41
DV		 7891 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7892 base.head) {
7893 if (encoder->base.crtc == &encoder->new_crtc->base)
7894 continue;
7895
7896 if (encoder->base.crtc) {
7897 tmp_crtc = encoder->base.crtc;
7898
7899 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7900 }
7901
7902 if (encoder->new_crtc)
7903 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7904 }
7905
e2e1ed41
DV		 7906 /* Check for any pipes that will be fully disabled ... */
7907 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7908 base.head) {
7909 bool used = false;
22fd0fab 7910
e2e1ed41
DV		 7911 /* Don't try to disable disabled crtcs. */
7912 if (!intel_crtc->base.enabled)
7913 continue;
7e7d76c3 7914
e2e1ed41
DV		 7915 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7916 base.head) {
7917 if (encoder->new_crtc == intel_crtc)
7918 used = true;
7919 }
7920
7921 if (!used)
7922 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7923 }
7924
e2e1ed41
DV		 7925
7926 /* set_mode is also used to update properties on life display pipes. */
7927 intel_crtc = to_intel_crtc(crtc);
7928 if (crtc->enabled)
7929 *prepare_pipes |= 1 << intel_crtc->pipe;
7930
b6c5164d
DV		 7931 /*
7932 * For simplicity do a full modeset on any pipe where the output routing
7933 * changed. We could be more clever, but that would require us to be
7934 * more careful with calling the relevant encoder->mode_set functions.
7935 */
e2e1ed41
DV		 7936 if (*prepare_pipes)
7937 *modeset_pipes = *prepare_pipes;
7938
7939 /* ... and mask these out. */
7940 *modeset_pipes &= ~(*disable_pipes);
7941 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 7942
7943 /*
7944 * HACK: We don't (yet) fully support global modesets. intel_set_config
7945 * obies this rule, but the modeset restore mode of
7946 * intel_modeset_setup_hw_state does not.
7947 */
7948 *modeset_pipes &= 1 << intel_crtc->pipe;
7949 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 7950
7951 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7952 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 7953}
79e53945 7954
ea9d758d 7955static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7956{
ea9d758d 7957 struct drm_encoder *encoder;
f6e5b160 7958 struct drm_device *dev = crtc->dev;
f6e5b160 7959
ea9d758d
DV		 7960 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7961 if (encoder->crtc == crtc)
7962 return true;
7963
7964 return false;
7965}
7966
7967static void
7968intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7969{
7970 struct intel_encoder *intel_encoder;
7971 struct intel_crtc *intel_crtc;
7972 struct drm_connector *connector;
7973
7974 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7975 base.head) {
7976 if (!intel_encoder->base.crtc)
7977 continue;
7978
7979 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7980
7981 if (prepare_pipes & (1 << intel_crtc->pipe))
7982 intel_encoder->connectors_active = false;
7983 }
7984
7985 intel_modeset_commit_output_state(dev);
7986
7987 /* Update computed state. */
7988 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7989 base.head) {
7990 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7991 }
7992
7993 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7994 if (!connector->encoder || !connector->encoder->crtc)
7995 continue;
7996
7997 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7998
7999 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8000 struct drm_property *dpms_property =
8001 dev->mode_config.dpms_property;
8002
ea9d758d 8003 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8004 drm_object_property_set_value(&connector->base,
68d34720
DV		 8005 dpms_property,
8006 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8007
8008 intel_encoder = to_intel_encoder(connector->encoder);
8009 intel_encoder->connectors_active = true;
8010 }
8011 }
8012
8013}
8014
25c5b266
DV		 8015#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8016 list_for_each_entry((intel_crtc), \
8017 &(dev)->mode_config.crtc_list, \
8018 base.head) \
0973f18f 8019 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8020
0e8ffe1b
DV		 8021static bool
8022intel_pipe_config_compare(struct intel_crtc_config *current_config,
8023 struct intel_crtc_config *pipe_config)
8024{
08a24034
DV		 8025#define PIPE_CONF_CHECK_I(name) \
8026 if (current_config->name != pipe_config->name) { \
8027 DRM_ERROR("mismatch in " #name " " \
8028 "(expected %i, found %i)\n", \
8029 current_config->name, \
8030 pipe_config->name); \
8031 return false; \
88adfff1
DV		 8032 }
8033
1bd1bd80
DV		 8034#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8035 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8036 DRM_ERROR("mismatch in " #name " " \
8037 "(expected %i, found %i)\n", \
8038 current_config->name & (mask), \
8039 pipe_config->name & (mask)); \
8040 return false; \
8041 }
8042
08a24034
DV		 8043 PIPE_CONF_CHECK_I(has_pch_encoder);
8044 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8045 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8046 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8047 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8048 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8049 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8050
1bd1bd80
DV		 8051 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8052 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8053 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8054 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8055 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8056 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8057
8058 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8059 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8060 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8061 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8062 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8063 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8064
8065 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8066 DRM_MODE_FLAG_INTERLACE);
8067
8068 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8069 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8070
08a24034 8071#undef PIPE_CONF_CHECK_I
1bd1bd80 8072#undef PIPE_CONF_CHECK_FLAGS
627eb5a3 8073
0e8ffe1b
DV		 8074 return true;
8075}
8076
b980514c 8077void
8af6cf88
DV		 8078intel_modeset_check_state(struct drm_device *dev)
8079{
0e8ffe1b 8080 drm_i915_private_t *dev_priv = dev->dev_private;
8af6cf88
DV		 8081 struct intel_crtc *crtc;
8082 struct intel_encoder *encoder;
8083 struct intel_connector *connector;
0e8ffe1b 8084 struct intel_crtc_config pipe_config;
8af6cf88
DV		 8085
8086 list_for_each_entry(connector, &dev->mode_config.connector_list,
8087 base.head) {
8088 /* This also checks the encoder/connector hw state with the
8089 * ->get_hw_state callbacks. */
8090 intel_connector_check_state(connector);
8091
8092 WARN(&connector->new_encoder->base != connector->base.encoder,
8093 "connector's staged encoder doesn't match current encoder\n");
8094 }
8095
8096 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8097 base.head) {
8098 bool enabled = false;
8099 bool active = false;
8100 enum pipe pipe, tracked_pipe;
8101
8102 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8103 encoder->base.base.id,
8104 drm_get_encoder_name(&encoder->base));
8105
8106 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8107 "encoder's stage crtc doesn't match current crtc\n");
8108 WARN(encoder->connectors_active && !encoder->base.crtc,
8109 "encoder's active_connectors set, but no crtc\n");
8110
8111 list_for_each_entry(connector, &dev->mode_config.connector_list,
8112 base.head) {
8113 if (connector->base.encoder != &encoder->base)
8114 continue;
8115 enabled = true;
8116 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8117 active = true;
8118 }
8119 WARN(!!encoder->base.crtc != enabled,
8120 "encoder's enabled state mismatch "
8121 "(expected %i, found %i)\n",
8122 !!encoder->base.crtc, enabled);
8123 WARN(active && !encoder->base.crtc,
8124 "active encoder with no crtc\n");
8125
8126 WARN(encoder->connectors_active != active,
8127 "encoder's computed active state doesn't match tracked active state "
8128 "(expected %i, found %i)\n", active, encoder->connectors_active);
8129
8130 active = encoder->get_hw_state(encoder, &pipe);
8131 WARN(active != encoder->connectors_active,
8132 "encoder's hw state doesn't match sw tracking "
8133 "(expected %i, found %i)\n",
8134 encoder->connectors_active, active);
8135
8136 if (!encoder->base.crtc)
8137 continue;
8138
8139 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8140 WARN(active && pipe != tracked_pipe,
8141 "active encoder's pipe doesn't match"
8142 "(expected %i, found %i)\n",
8143 tracked_pipe, pipe);
8144
8145 }
8146
8147 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8148 base.head) {
8149 bool enabled = false;
8150 bool active = false;
8151
8152 DRM_DEBUG_KMS("[CRTC:%d]\n",
8153 crtc->base.base.id);
8154
8155 WARN(crtc->active && !crtc->base.enabled,
8156 "active crtc, but not enabled in sw tracking\n");
8157
8158 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8159 base.head) {
8160 if (encoder->base.crtc != &crtc->base)
8161 continue;
8162 enabled = true;
8163 if (encoder->connectors_active)
8164 active = true;
8165 }
8166 WARN(active != crtc->active,
8167 "crtc's computed active state doesn't match tracked active state "
8168 "(expected %i, found %i)\n", active, crtc->active);
8169 WARN(enabled != crtc->base.enabled,
8170 "crtc's computed enabled state doesn't match tracked enabled state "
8171 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8172
88adfff1 8173 memset(&pipe_config, 0, sizeof(pipe_config));
60c4ae10 8174 pipe_config.cpu_transcoder = crtc->config.cpu_transcoder;
0e8ffe1b
DV		 8175 active = dev_priv->display.get_pipe_config(crtc,
8176 &pipe_config);
8177 WARN(crtc->active != active,
8178 "crtc active state doesn't match with hw state "
8179 "(expected %i, found %i)\n", crtc->active, active);
8180
8181 WARN(active &&
8182 !intel_pipe_config_compare(&crtc->config, &pipe_config),
8183 "pipe state doesn't match!\n");
8af6cf88
DV		 8184 }
8185}
8186
f30da187
DV		 8187static int __intel_set_mode(struct drm_crtc *crtc,
8188 struct drm_display_mode *mode,
8189 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 8190{
8191 struct drm_device *dev = crtc->dev;
dbf2b54e 8192 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 8193 struct drm_display_mode *saved_mode, *saved_hwmode;
8194 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 8195 struct intel_crtc *intel_crtc;
8196 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 8197 int ret = 0;
a6778b3c 8198
3ac18232 8199 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 8200 if (!saved_mode)
8201 return -ENOMEM;
3ac18232 8202 saved_hwmode = saved_mode + 1;
a6778b3c 8203
e2e1ed41 8204 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 8205 &prepare_pipes, &disable_pipes);
8206
3ac18232
TG		 8207 *saved_hwmode = crtc->hwmode;
8208 *saved_mode = crtc->mode;
a6778b3c 8209
25c5b266
DV		 8210 /* Hack: Because we don't (yet) support global modeset on multiple
8211 * crtcs, we don't keep track of the new mode for more than one crtc.
8212 * Hence simply check whether any bit is set in modeset_pipes in all the
8213 * pieces of code that are not yet converted to deal with mutliple crtcs
8214 * changing their mode at the same time. */
25c5b266 8215 if (modeset_pipes) {
4e53c2e0 8216 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 8217 if (IS_ERR(pipe_config)) {
8218 ret = PTR_ERR(pipe_config);
8219 pipe_config = NULL;
8220
3ac18232 8221 goto out;
25c5b266 8222 }
25c5b266 8223 }
a6778b3c 8224
460da916
DV		 8225 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8226 intel_crtc_disable(&intel_crtc->base);
8227
ea9d758d
DV		 8228 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8229 if (intel_crtc->base.enabled)
8230 dev_priv->display.crtc_disable(&intel_crtc->base);
8231 }
a6778b3c 8232
6c4c86f5
DV		 8233 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8234 * to set it here already despite that we pass it down the callchain.
f6e5b160 8235 */
b8cecdf5 8236 if (modeset_pipes) {
3b117c8f 8237 enum transcoder tmp = to_intel_crtc(crtc)->config.cpu_transcoder;
25c5b266 8238 crtc->mode = *mode;
b8cecdf5
DV		 8239 /* mode_set/enable/disable functions rely on a correct pipe
8240 * config. */
8241 to_intel_crtc(crtc)->config = *pipe_config;
3b117c8f 8242 to_intel_crtc(crtc)->config.cpu_transcoder = tmp;
b8cecdf5 8243 }
7758a113 8244
ea9d758d
DV		 8245 /* Only after disabling all output pipelines that will be changed can we
8246 * update the the output configuration. */
8247 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 8248
47fab737
DV		 8249 if (dev_priv->display.modeset_global_resources)
8250 dev_priv->display.modeset_global_resources(dev);
8251
a6778b3c
DV		 8252 /* Set up the DPLL and any encoders state that needs to adjust or depend
8253 * on the DPLL.
f6e5b160 8254 */
25c5b266 8255 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 8256 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 8257 x, y, fb);
8258 if (ret)
8259 goto done;
a6778b3c
DV		 8260 }
8261
8262 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 8263 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8264 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 8265
25c5b266
DV		 8266 if (modeset_pipes) {
8267 /* Store real post-adjustment hardware mode. */
b8cecdf5 8268 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 8269
25c5b266
DV		 8270 /* Calculate and store various constants which
8271 * are later needed by vblank and swap-completion
8272 * timestamping. They are derived from true hwmode.
8273 */
8274 drm_calc_timestamping_constants(crtc);
8275 }
a6778b3c
DV		 8276
8277 /* FIXME: add subpixel order */
8278done:
c0c36b94 8279 if (ret && crtc->enabled) {
3ac18232
TG		 8280 crtc->hwmode = *saved_hwmode;
8281 crtc->mode = *saved_mode;
a6778b3c
DV		 8282 }
8283
3ac18232 8284out:
b8cecdf5 8285 kfree(pipe_config);
3ac18232 8286 kfree(saved_mode);
a6778b3c 8287 return ret;
f6e5b160
CW		 8288}
8289
f30da187
DV		 8290int intel_set_mode(struct drm_crtc *crtc,
8291 struct drm_display_mode *mode,
8292 int x, int y, struct drm_framebuffer *fb)
8293{
8294 int ret;
8295
8296 ret = __intel_set_mode(crtc, mode, x, y, fb);
8297
8298 if (ret == 0)
8299 intel_modeset_check_state(crtc->dev);
8300
8301 return ret;
8302}
8303
c0c36b94
CW		 8304void intel_crtc_restore_mode(struct drm_crtc *crtc)
8305{
8306 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8307}
8308
25c5b266
DV		 8309#undef for_each_intel_crtc_masked
8310
d9e55608
DV		 8311static void intel_set_config_free(struct intel_set_config *config)
8312{
8313 if (!config)
8314 return;
8315
1aa4b628
DV		 8316 kfree(config->save_connector_encoders);
8317 kfree(config->save_encoder_crtcs);
d9e55608
DV		 8318 kfree(config);
8319}
8320
85f9eb71
DV		 8321static int intel_set_config_save_state(struct drm_device *dev,
8322 struct intel_set_config *config)
8323{
85f9eb71
DV		 8324 struct drm_encoder *encoder;
8325 struct drm_connector *connector;
8326 int count;
8327
1aa4b628
DV		 8328 config->save_encoder_crtcs =
8329 kcalloc(dev->mode_config.num_encoder,
8330 sizeof(struct drm_crtc *), GFP_KERNEL);
8331 if (!config->save_encoder_crtcs)
85f9eb71
DV		 8332 return -ENOMEM;
8333
1aa4b628
DV		 8334 config->save_connector_encoders =
8335 kcalloc(dev->mode_config.num_connector,
8336 sizeof(struct drm_encoder *), GFP_KERNEL);
8337 if (!config->save_connector_encoders)
85f9eb71
DV		 8338 return -ENOMEM;
8339
8340 /* Copy data. Note that driver private data is not affected.
8341 * Should anything bad happen only the expected state is
8342 * restored, not the drivers personal bookkeeping.
8343 */
85f9eb71
DV		 8344 count = 0;
8345 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 8346 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 8347 }
8348
8349 count = 0;
8350 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 8351 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 8352 }
8353
8354 return 0;
8355}
8356
8357static void intel_set_config_restore_state(struct drm_device *dev,
8358 struct intel_set_config *config)
8359{
9a935856
DV		 8360 struct intel_encoder *encoder;
8361 struct intel_connector *connector;
85f9eb71
DV		 8362 int count;
8363
85f9eb71 8364 count = 0;
9a935856
DV		 8365 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8366 encoder->new_crtc =
8367 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 8368 }
8369
8370 count = 0;
9a935856
DV		 8371 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8372 connector->new_encoder =
8373 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 8374 }
8375}
8376
5e2b584e
DV		 8377static void
8378intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8379 struct intel_set_config *config)
8380{
8381
8382 /* We should be able to check here if the fb has the same properties
8383 * and then just flip_or_move it */
8384 if (set->crtc->fb != set->fb) {
8385 /* If we have no fb then treat it as a full mode set */
8386 if (set->crtc->fb == NULL) {
8387 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8388 config->mode_changed = true;
8389 } else if (set->fb == NULL) {
8390 config->mode_changed = true;
72f4901e
DV		 8391 } else if (set->fb->pixel_format !=
8392 set->crtc->fb->pixel_format) {
5e2b584e
DV		 8393 config->mode_changed = true;
8394 } else
8395 config->fb_changed = true;
8396 }
8397
835c5873 8398 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 8399 config->fb_changed = true;
8400
8401 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8402 DRM_DEBUG_KMS("modes are different, full mode set\n");
8403 drm_mode_debug_printmodeline(&set->crtc->mode);
8404 drm_mode_debug_printmodeline(set->mode);
8405 config->mode_changed = true;
8406 }
8407}
8408
2e431051 8409static int
9a935856
DV		 8410intel_modeset_stage_output_state(struct drm_device *dev,
8411 struct drm_mode_set *set,
8412 struct intel_set_config *config)
50f56119 8413{
85f9eb71 8414 struct drm_crtc *new_crtc;
9a935856
DV		 8415 struct intel_connector *connector;
8416 struct intel_encoder *encoder;
2e431051 8417 int count, ro;
50f56119 8418
9abdda74 8419 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 8420 * of connectors. For paranoia, double-check this. */
8421 WARN_ON(!set->fb && (set->num_connectors != 0));
8422 WARN_ON(set->fb && (set->num_connectors == 0));
8423
50f56119 8424 count = 0;
9a935856
DV		 8425 list_for_each_entry(connector, &dev->mode_config.connector_list,
8426 base.head) {
8427 /* Otherwise traverse passed in connector list and get encoders
8428 * for them. */
50f56119 8429 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 8430 if (set->connectors[ro] == &connector->base) {
8431 connector->new_encoder = connector->encoder;
50f56119
DV		 8432 break;
8433 }
8434 }
8435
9a935856
DV		 8436 /* If we disable the crtc, disable all its connectors. Also, if
8437 * the connector is on the changing crtc but not on the new
8438 * connector list, disable it. */
8439 if ((!set->fb || ro == set->num_connectors) &&
8440 connector->base.encoder &&
8441 connector->base.encoder->crtc == set->crtc) {
8442 connector->new_encoder = NULL;
8443
8444 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8445 connector->base.base.id,
8446 drm_get_connector_name(&connector->base));
8447 }
8448
8449
8450 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8451 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8452 config->mode_changed = true;
50f56119
DV		 8453 }
8454 }
9a935856 8455 /* connector->new_encoder is now updated for all connectors. */
50f56119 8456
9a935856 8457 /* Update crtc of enabled connectors. */
50f56119 8458 count = 0;
9a935856
DV		 8459 list_for_each_entry(connector, &dev->mode_config.connector_list,
8460 base.head) {
8461 if (!connector->new_encoder)
50f56119
DV		 8462 continue;
8463
9a935856 8464 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8465
8466 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8467 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8468 new_crtc = set->crtc;
8469 }
8470
8471 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8472 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8473 new_crtc)) {
5e2b584e 8474 return -EINVAL;
50f56119 8475 }
9a935856
DV		 8476 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8477
8478 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8479 connector->base.base.id,
8480 drm_get_connector_name(&connector->base),
8481 new_crtc->base.id);
8482 }
8483
8484 /* Check for any encoders that needs to be disabled. */
8485 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8486 base.head) {
8487 list_for_each_entry(connector,
8488 &dev->mode_config.connector_list,
8489 base.head) {
8490 if (connector->new_encoder == encoder) {
8491 WARN_ON(!connector->new_encoder->new_crtc);
8492
8493 goto next_encoder;
8494 }
8495 }
8496 encoder->new_crtc = NULL;
8497next_encoder:
8498 /* Only now check for crtc changes so we don't miss encoders
8499 * that will be disabled. */
8500 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8501 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8502 config->mode_changed = true;
50f56119
DV		 8503 }
8504 }
9a935856 8505 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8506
2e431051
DV		 8507 return 0;
8508}
8509
8510static int intel_crtc_set_config(struct drm_mode_set *set)
8511{
8512 struct drm_device *dev;
2e431051
DV		 8513 struct drm_mode_set save_set;
8514 struct intel_set_config *config;
8515 int ret;
2e431051 8516
8d3e375e
DV		 8517 BUG_ON(!set);
8518 BUG_ON(!set->crtc);
8519 BUG_ON(!set->crtc->helper_private);
2e431051 8520
7e53f3a4
DV		 8521 /* Enforce sane interface api - has been abused by the fb helper. */
8522 BUG_ON(!set->mode && set->fb);
8523 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 8524
2e431051
DV		 8525 if (set->fb) {
8526 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8527 set->crtc->base.id, set->fb->base.id,
8528 (int)set->num_connectors, set->x, set->y);
8529 } else {
8530 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8531 }
8532
8533 dev = set->crtc->dev;
8534
8535 ret = -ENOMEM;
8536 config = kzalloc(sizeof(*config), GFP_KERNEL);
8537 if (!config)
8538 goto out_config;
8539
8540 ret = intel_set_config_save_state(dev, config);
8541 if (ret)
8542 goto out_config;
8543
8544 save_set.crtc = set->crtc;
8545 save_set.mode = &set->crtc->mode;
8546 save_set.x = set->crtc->x;
8547 save_set.y = set->crtc->y;
8548 save_set.fb = set->crtc->fb;
8549
8550 /* Compute whether we need a full modeset, only an fb base update or no
8551 * change at all. In the future we might also check whether only the
8552 * mode changed, e.g. for LVDS where we only change the panel fitter in
8553 * such cases. */
8554 intel_set_config_compute_mode_changes(set, config);
8555
9a935856 8556 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8557 if (ret)
8558 goto fail;
8559
5e2b584e 8560 if (config->mode_changed) {
87f1faa6 8561 if (set->mode) {
50f56119
DV		 8562 DRM_DEBUG_KMS("attempting to set mode from"
8563 " userspace\n");
8564 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 8565 }
8566
c0c36b94
CW		 8567 ret = intel_set_mode(set->crtc, set->mode,
8568 set->x, set->y, set->fb);
8569 if (ret) {
8570 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8571 set->crtc->base.id, ret);
87f1faa6
DV		 8572 goto fail;
8573 }
5e2b584e 8574 } else if (config->fb_changed) {
4878cae2
VS		 8575 intel_crtc_wait_for_pending_flips(set->crtc);
8576
4f660f49 8577 ret = intel_pipe_set_base(set->crtc,
94352cf9 8578 set->x, set->y, set->fb);
50f56119
DV		 8579 }
8580
d9e55608
DV		 8581 intel_set_config_free(config);
8582
50f56119
DV		 8583 return 0;
8584
8585fail:
85f9eb71 8586 intel_set_config_restore_state(dev, config);
50f56119
DV		 8587
8588 /* Try to restore the config */
5e2b584e 8589 if (config->mode_changed &&
c0c36b94
CW		 8590 intel_set_mode(save_set.crtc, save_set.mode,
8591 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8592 DRM_ERROR("failed to restore config after modeset failure\n");
8593
d9e55608
DV		 8594out_config:
8595 intel_set_config_free(config);
50f56119
DV		 8596 return ret;
8597}
f6e5b160
CW		 8598
8599static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8600 .cursor_set = intel_crtc_cursor_set,
8601 .cursor_move = intel_crtc_cursor_move,
8602 .gamma_set = intel_crtc_gamma_set,
50f56119 8603 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8604 .destroy = intel_crtc_destroy,
8605 .page_flip = intel_crtc_page_flip,
8606};
8607
79f689aa
PZ		 8608static void intel_cpu_pll_init(struct drm_device *dev)
8609{
affa9354 8610 if (HAS_DDI(dev))
79f689aa
PZ		 8611 intel_ddi_pll_init(dev);
8612}
8613
ee7b9f93
JB		 8614static void intel_pch_pll_init(struct drm_device *dev)
8615{
8616 drm_i915_private_t *dev_priv = dev->dev_private;
8617 int i;
8618
8619 if (dev_priv->num_pch_pll == 0) {
8620 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8621 return;
8622 }
8623
8624 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8625 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8626 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8627 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8628 }
8629}
8630
b358d0a6 8631static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8632{
22fd0fab 8633 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8634 struct intel_crtc *intel_crtc;
8635 int i;
8636
8637 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8638 if (intel_crtc == NULL)
8639 return;
8640
8641 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8642
8643 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8644 for (i = 0; i < 256; i++) {
8645 intel_crtc->lut_r[i] = i;
8646 intel_crtc->lut_g[i] = i;
8647 intel_crtc->lut_b[i] = i;
8648 }
8649
80824003
JB		 8650 /* Swap pipes & planes for FBC on pre-965 */
8651 intel_crtc->pipe = pipe;
8652 intel_crtc->plane = pipe;
3b117c8f 8653 intel_crtc->config.cpu_transcoder = pipe;
e2e767ab 8654 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8655 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8656 intel_crtc->plane = !pipe;
80824003
JB		 8657 }
8658
22fd0fab
JB		 8659 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8660 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8661 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8662 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8663
79e53945 8664 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8665}
8666
08d7b3d1 8667int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8668 struct drm_file *file)
08d7b3d1 8669{
08d7b3d1 8670 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8671 struct drm_mode_object *drmmode_obj;
8672 struct intel_crtc *crtc;
08d7b3d1 8673
1cff8f6b
DV		 8674 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8675 return -ENODEV;
08d7b3d1 8676
c05422d5
DV		 8677 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8678 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8679
c05422d5 8680 if (!drmmode_obj) {
08d7b3d1
CW		 8681 DRM_ERROR("no such CRTC id\n");
8682 return -EINVAL;
8683 }
8684
c05422d5
DV		 8685 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8686 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8687
c05422d5 8688 return 0;
08d7b3d1
CW		 8689}
8690
66a9278e 8691static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8692{
66a9278e
DV		 8693 struct drm_device *dev = encoder->base.dev;
8694 struct intel_encoder *source_encoder;
79e53945 8695 int index_mask = 0;
79e53945
JB		 8696 int entry = 0;
8697
66a9278e
DV		 8698 list_for_each_entry(source_encoder,
8699 &dev->mode_config.encoder_list, base.head) {
8700
8701 if (encoder == source_encoder)
79e53945 8702 index_mask |= (1 << entry);
66a9278e
DV		 8703
8704 /* Intel hw has only one MUX where enocoders could be cloned. */
8705 if (encoder->cloneable && source_encoder->cloneable)
8706 index_mask |= (1 << entry);
8707
79e53945
JB		 8708 entry++;
8709 }
4ef69c7a 8710
79e53945
JB		 8711 return index_mask;
8712}
8713
4d302442
CW		 8714static bool has_edp_a(struct drm_device *dev)
8715{
8716 struct drm_i915_private *dev_priv = dev->dev_private;
8717
8718 if (!IS_MOBILE(dev))
8719 return false;
8720
8721 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8722 return false;
8723
8724 if (IS_GEN5(dev) &&
8725 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8726 return false;
8727
8728 return true;
8729}
8730
79e53945
JB		 8731static void intel_setup_outputs(struct drm_device *dev)
8732{
725e30ad 8733 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8734 struct intel_encoder *encoder;
cb0953d7 8735 bool dpd_is_edp = false;
f3cfcba6 8736 bool has_lvds;
79e53945 8737
f3cfcba6 8738 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8739 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8740 /* disable the panel fitter on everything but LVDS */
8741 I915_WRITE(PFIT_CONTROL, 0);
8742 }
79e53945 8743
c40c0f5b 8744 if (!IS_ULT(dev))
79935fca 8745 intel_crt_init(dev);
cb0953d7 8746
affa9354 8747 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8748 int found;
8749
8750 /* Haswell uses DDI functions to detect digital outputs */
8751 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8752 /* DDI A only supports eDP */
8753 if (found)
8754 intel_ddi_init(dev, PORT_A);
8755
8756 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8757 * register */
8758 found = I915_READ(SFUSE_STRAP);
8759
8760 if (found & SFUSE_STRAP_DDIB_DETECTED)
8761 intel_ddi_init(dev, PORT_B);
8762 if (found & SFUSE_STRAP_DDIC_DETECTED)
8763 intel_ddi_init(dev, PORT_C);
8764 if (found & SFUSE_STRAP_DDID_DETECTED)
8765 intel_ddi_init(dev, PORT_D);
8766 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8767 int found;
270b3042
DV		 8768 dpd_is_edp = intel_dpd_is_edp(dev);
8769
8770 if (has_edp_a(dev))
8771 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8772
dc0fa718 8773 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 8774 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8775 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8776 if (!found)
e2debe91 8777 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 8778 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8779 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8780 }
8781
dc0fa718 8782 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 8783 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 8784
dc0fa718 8785 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 8786 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 8787
5eb08b69 8788 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8789 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8790
270b3042 8791 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8792 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 8793 } else if (IS_VALLEYVIEW(dev)) {
19c03924 8794 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 8795 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8796 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 8797
dc0fa718 8798 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 8799 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8800 PORT_B);
67cfc203
VS		 8801 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8802 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 8803 }
103a196f 8804 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8805 bool found = false;
7d57382e 8806
e2debe91 8807 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8808 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 8809 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 8810 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8811 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 8812 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 8813 }
27185ae1 8814
b01f2c3a
JB		 8815 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8816 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 8817 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 8818 }
725e30ad 8819 }
13520b05
KH		 8820
8821 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8822
e2debe91 8823 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8824 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 8825 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 8826 }
27185ae1 8827
e2debe91 8828 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 8829
b01f2c3a
JB		 8830 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8831 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 8832 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a
JB		 8833 }
8834 if (SUPPORTS_INTEGRATED_DP(dev)) {
8835 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 8836 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 8837 }
725e30ad 8838 }
27185ae1 8839
b01f2c3a
JB		 8840 if (SUPPORTS_INTEGRATED_DP(dev) &&
8841 (I915_READ(DP_D) & DP_DETECTED)) {
8842 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 8843 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 8844 }
bad720ff 8845 } else if (IS_GEN2(dev))
79e53945
JB		 8846 intel_dvo_init(dev);
8847
103a196f 8848 if (SUPPORTS_TV(dev))
79e53945
JB		 8849 intel_tv_init(dev);
8850
4ef69c7a
CW		 8851 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8852 encoder->base.possible_crtcs = encoder->crtc_mask;
8853 encoder->base.possible_clones =
66a9278e 8854 intel_encoder_clones(encoder);
79e53945 8855 }
47356eb6 8856
dde86e2d 8857 intel_init_pch_refclk(dev);
270b3042
DV		 8858
8859 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8860}
8861
8862static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8863{
8864 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8865
8866 drm_framebuffer_cleanup(fb);
05394f39 8867 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8868
8869 kfree(intel_fb);
8870}
8871
8872static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8873 struct drm_file *file,
79e53945
JB		 8874 unsigned int *handle)
8875{
8876 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8877 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8878
05394f39 8879 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8880}
8881
8882static const struct drm_framebuffer_funcs intel_fb_funcs = {
8883 .destroy = intel_user_framebuffer_destroy,
8884 .create_handle = intel_user_framebuffer_create_handle,
8885};
8886
38651674
DA		 8887int intel_framebuffer_init(struct drm_device *dev,
8888 struct intel_framebuffer *intel_fb,
308e5bcb 8889 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8890 struct drm_i915_gem_object *obj)
79e53945 8891{
79e53945
JB		 8892 int ret;
8893
c16ed4be
CW		 8894 if (obj->tiling_mode == I915_TILING_Y) {
8895 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 8896 return -EINVAL;
c16ed4be 8897 }
57cd6508 8898
c16ed4be
CW		 8899 if (mode_cmd->pitches[0] & 63) {
8900 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8901 mode_cmd->pitches[0]);
57cd6508 8902 return -EINVAL;
c16ed4be 8903 }
57cd6508 8904
5d7bd705 8905 /* FIXME <= Gen4 stride limits are bit unclear */
c16ed4be
CW		 8906 if (mode_cmd->pitches[0] > 32768) {
8907 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8908 mode_cmd->pitches[0]);
5d7bd705 8909 return -EINVAL;
c16ed4be 8910 }
5d7bd705
VS		 8911
8912 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 8913 mode_cmd->pitches[0] != obj->stride) {
8914 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8915 mode_cmd->pitches[0], obj->stride);
5d7bd705 8916 return -EINVAL;
c16ed4be 8917 }
5d7bd705 8918
57779d06 8919 /* Reject formats not supported by any plane early. */
308e5bcb 8920 switch (mode_cmd->pixel_format) {
57779d06 8921 case DRM_FORMAT_C8:
04b3924d
VS		 8922 case DRM_FORMAT_RGB565:
8923 case DRM_FORMAT_XRGB8888:
8924 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8925 break;
8926 case DRM_FORMAT_XRGB1555:
8927 case DRM_FORMAT_ARGB1555:
c16ed4be
CW		 8928 if (INTEL_INFO(dev)->gen > 3) {
8929 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8930 return -EINVAL;
c16ed4be 8931 }
57779d06
VS		 8932 break;
8933 case DRM_FORMAT_XBGR8888:
8934 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8935 case DRM_FORMAT_XRGB2101010:
8936 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8937 case DRM_FORMAT_XBGR2101010:
8938 case DRM_FORMAT_ABGR2101010:
c16ed4be
CW		 8939 if (INTEL_INFO(dev)->gen < 4) {
8940 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8941 return -EINVAL;
c16ed4be 8942 }
b5626747 8943 break;
04b3924d
VS		 8944 case DRM_FORMAT_YUYV:
8945 case DRM_FORMAT_UYVY:
8946 case DRM_FORMAT_YVYU:
8947 case DRM_FORMAT_VYUY:
c16ed4be
CW		 8948 if (INTEL_INFO(dev)->gen < 5) {
8949 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8950 return -EINVAL;
c16ed4be 8951 }
57cd6508
CW		 8952 break;
8953 default:
c16ed4be 8954 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8955 return -EINVAL;
8956 }
8957
90f9a336
VS		 8958 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8959 if (mode_cmd->offsets[0] != 0)
8960 return -EINVAL;
8961
c7d73f6a
DV		 8962 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8963 intel_fb->obj = obj;
8964
79e53945
JB		 8965 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8966 if (ret) {
8967 DRM_ERROR("framebuffer init failed %d\n", ret);
8968 return ret;
8969 }
8970
79e53945
JB		 8971 return 0;
8972}
8973
79e53945
JB		 8974static struct drm_framebuffer *
8975intel_user_framebuffer_create(struct drm_device *dev,
8976 struct drm_file *filp,
308e5bcb 8977 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8978{
05394f39 8979 struct drm_i915_gem_object *obj;
79e53945 8980
308e5bcb
JB		 8981 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8982 mode_cmd->handles[0]));
c8725226 8983 if (&obj->base == NULL)
cce13ff7 8984 return ERR_PTR(-ENOENT);
79e53945 8985
d2dff872 8986 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8987}
8988
79e53945 8989static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8990 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8991 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8992};
8993
e70236a8
JB		 8994/* Set up chip specific display functions */
8995static void intel_init_display(struct drm_device *dev)
8996{
8997 struct drm_i915_private *dev_priv = dev->dev_private;
8998
affa9354 8999 if (HAS_DDI(dev)) {
0e8ffe1b 9000 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 9001 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 9002 dev_priv->display.crtc_enable = haswell_crtc_enable;
9003 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 9004 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 9005 dev_priv->display.update_plane = ironlake_update_plane;
9006 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 9007 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 9008 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 9009 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9010 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 9011 dev_priv->display.off = ironlake_crtc_off;
17638cd6 9012 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 9013 } else if (IS_VALLEYVIEW(dev)) {
9014 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9015 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9016 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9017 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9018 dev_priv->display.off = i9xx_crtc_off;
9019 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9020 } else {
0e8ffe1b 9021 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 9022 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 9023 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9024 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 9025 dev_priv->display.off = i9xx_crtc_off;
17638cd6 9026 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9027 }
e70236a8 9028
e70236a8 9029 /* Returns the core display clock speed */
25eb05fc
JB		 9030 if (IS_VALLEYVIEW(dev))
9031 dev_priv->display.get_display_clock_speed =
9032 valleyview_get_display_clock_speed;
9033 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 9034 dev_priv->display.get_display_clock_speed =
9035 i945_get_display_clock_speed;
9036 else if (IS_I915G(dev))
9037 dev_priv->display.get_display_clock_speed =
9038 i915_get_display_clock_speed;
f2b115e6 9039 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 9040 dev_priv->display.get_display_clock_speed =
9041 i9xx_misc_get_display_clock_speed;
9042 else if (IS_I915GM(dev))
9043 dev_priv->display.get_display_clock_speed =
9044 i915gm_get_display_clock_speed;
9045 else if (IS_I865G(dev))
9046 dev_priv->display.get_display_clock_speed =
9047 i865_get_display_clock_speed;
f0f8a9ce 9048 else if (IS_I85X(dev))
e70236a8
JB		 9049 dev_priv->display.get_display_clock_speed =
9050 i855_get_display_clock_speed;
9051 else /* 852, 830 */
9052 dev_priv->display.get_display_clock_speed =
9053 i830_get_display_clock_speed;
9054
7f8a8569 9055 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 9056 if (IS_GEN5(dev)) {
674cf967 9057 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 9058 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 9059 } else if (IS_GEN6(dev)) {
674cf967 9060 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 9061 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 9062 } else if (IS_IVYBRIDGE(dev)) {
9063 /* FIXME: detect B0+ stepping and use auto training */
9064 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 9065 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 9066 dev_priv->display.modeset_global_resources =
9067 ivb_modeset_global_resources;
c82e4d26
ED		 9068 } else if (IS_HASWELL(dev)) {
9069 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 9070 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 9071 dev_priv->display.modeset_global_resources =
9072 haswell_modeset_global_resources;
a0e63c22 9073 }
6067aaea 9074 } else if (IS_G4X(dev)) {
e0dac65e 9075 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 9076 }
8c9f3aaf
JB		 9077
9078 /* Default just returns -ENODEV to indicate unsupported */
9079 dev_priv->display.queue_flip = intel_default_queue_flip;
9080
9081 switch (INTEL_INFO(dev)->gen) {
9082 case 2:
9083 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9084 break;
9085
9086 case 3:
9087 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9088 break;
9089
9090 case 4:
9091 case 5:
9092 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9093 break;
9094
9095 case 6:
9096 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9097 break;
7c9017e5
JB		 9098 case 7:
9099 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9100 break;
8c9f3aaf 9101 }
e70236a8
JB		 9102}
9103
b690e96c
JB		 9104/*
9105 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9106 * resume, or other times. This quirk makes sure that's the case for
9107 * affected systems.
9108 */
0206e353 9109static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 9110{
9111 struct drm_i915_private *dev_priv = dev->dev_private;
9112
9113 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 9114 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 9115}
9116
435793df
KP		 9117/*
9118 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9119 */
9120static void quirk_ssc_force_disable(struct drm_device *dev)
9121{
9122 struct drm_i915_private *dev_priv = dev->dev_private;
9123 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 9124 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 9125}
9126
4dca20ef 9127/*
5a15ab5b
CE		 9128 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9129 * brightness value
4dca20ef
CE		 9130 */
9131static void quirk_invert_brightness(struct drm_device *dev)
9132{
9133 struct drm_i915_private *dev_priv = dev->dev_private;
9134 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 9135 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 9136}
9137
b690e96c
JB		 9138struct intel_quirk {
9139 int device;
9140 int subsystem_vendor;
9141 int subsystem_device;
9142 void (*hook)(struct drm_device *dev);
9143};
9144
5f85f176
EE		 9145/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9146struct intel_dmi_quirk {
9147 void (*hook)(struct drm_device *dev);
9148 const struct dmi_system_id (*dmi_id_list)[];
9149};
9150
9151static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9152{
9153 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9154 return 1;
9155}
9156
9157static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9158 {
9159 .dmi_id_list = &(const struct dmi_system_id[]) {
9160 {
9161 .callback = intel_dmi_reverse_brightness,
9162 .ident = "NCR Corporation",
9163 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9164 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9165 },
9166 },
9167 { } /* terminating entry */
9168 },
9169 .hook = quirk_invert_brightness,
9170 },
9171};
9172
c43b5634 9173static struct intel_quirk intel_quirks[] = {
b690e96c 9174 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 9175 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 9176
b690e96c
JB		 9177 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9178 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9179
b690e96c
JB		 9180 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9181 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9182
ccd0d36e 9183 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 9184 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 9185 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 9186
9187 /* Lenovo U160 cannot use SSC on LVDS */
9188 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 9189
9190 /* Sony Vaio Y cannot use SSC on LVDS */
9191 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 9192
9193 /* Acer Aspire 5734Z must invert backlight brightness */
9194 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 9195
9196 /* Acer/eMachines G725 */
9197 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 9198
9199 /* Acer/eMachines e725 */
9200 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 9201
9202 /* Acer/Packard Bell NCL20 */
9203 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 9204
9205 /* Acer Aspire 4736Z */
9206 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 9207};
9208
9209static void intel_init_quirks(struct drm_device *dev)
9210{
9211 struct pci_dev *d = dev->pdev;
9212 int i;
9213
9214 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9215 struct intel_quirk *q = &intel_quirks[i];
9216
9217 if (d->device == q->device &&
9218 (d->subsystem_vendor == q->subsystem_vendor ||
9219 q->subsystem_vendor == PCI_ANY_ID) &&
9220 (d->subsystem_device == q->subsystem_device ||
9221 q->subsystem_device == PCI_ANY_ID))
9222 q->hook(dev);
9223 }
5f85f176
EE		 9224 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9225 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9226 intel_dmi_quirks[i].hook(dev);
9227 }
b690e96c
JB		 9228}
9229
9cce37f4
JB		 9230/* Disable the VGA plane that we never use */
9231static void i915_disable_vga(struct drm_device *dev)
9232{
9233 struct drm_i915_private *dev_priv = dev->dev_private;
9234 u8 sr1;
766aa1c4 9235 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 9236
9237 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 9238 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 9239 sr1 = inb(VGA_SR_DATA);
9240 outb(sr1 | 1<<5, VGA_SR_DATA);
9241 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9242 udelay(300);
9243
9244 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9245 POSTING_READ(vga_reg);
9246}
9247
f817586c
DV		 9248void intel_modeset_init_hw(struct drm_device *dev)
9249{
fa42e23c 9250 intel_init_power_well(dev);
0232e927 9251
a8f78b58
ED		 9252 intel_prepare_ddi(dev);
9253
f817586c
DV		 9254 intel_init_clock_gating(dev);
9255
79f5b2c7 9256 mutex_lock(&dev->struct_mutex);
8090c6b9 9257 intel_enable_gt_powersave(dev);
79f5b2c7 9258 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 9259}
9260
79e53945
JB		 9261void intel_modeset_init(struct drm_device *dev)
9262{
652c393a 9263 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 9264 int i, j, ret;
79e53945
JB		 9265
9266 drm_mode_config_init(dev);
9267
9268 dev->mode_config.min_width = 0;
9269 dev->mode_config.min_height = 0;
9270
019d96cb
DA		 9271 dev->mode_config.preferred_depth = 24;
9272 dev->mode_config.prefer_shadow = 1;
9273
e6ecefaa 9274 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 9275
b690e96c
JB		 9276 intel_init_quirks(dev);
9277
1fa61106
ED		 9278 intel_init_pm(dev);
9279
e3c74757
BW		 9280 if (INTEL_INFO(dev)->num_pipes == 0)
9281 return;
9282
e70236a8
JB		 9283 intel_init_display(dev);
9284
a6c45cf0
CW		 9285 if (IS_GEN2(dev)) {
9286 dev->mode_config.max_width = 2048;
9287 dev->mode_config.max_height = 2048;
9288 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9289 dev->mode_config.max_width = 4096;
9290 dev->mode_config.max_height = 4096;
79e53945 9291 } else {
a6c45cf0
CW		 9292 dev->mode_config.max_width = 8192;
9293 dev->mode_config.max_height = 8192;
79e53945 9294 }
5d4545ae 9295 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 9296
28c97730 9297 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 9298 INTEL_INFO(dev)->num_pipes,
9299 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 9300
7eb552ae 9301 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
79e53945 9302 intel_crtc_init(dev, i);
7f1f3851
JB		 9303 for (j = 0; j < dev_priv->num_plane; j++) {
9304 ret = intel_plane_init(dev, i, j);
9305 if (ret)
06da8da2
VS		 9306 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9307 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 9308 }
79e53945
JB		 9309 }
9310
79f689aa 9311 intel_cpu_pll_init(dev);
ee7b9f93
JB		 9312 intel_pch_pll_init(dev);
9313
9cce37f4
JB		 9314 /* Just disable it once at startup */
9315 i915_disable_vga(dev);
79e53945 9316 intel_setup_outputs(dev);
11be49eb
CW		 9317
9318 /* Just in case the BIOS is doing something questionable. */
9319 intel_disable_fbc(dev);
2c7111db
CW		 9320}
9321
24929352
DV		 9322static void
9323intel_connector_break_all_links(struct intel_connector *connector)
9324{
9325 connector->base.dpms = DRM_MODE_DPMS_OFF;
9326 connector->base.encoder = NULL;
9327 connector->encoder->connectors_active = false;
9328 connector->encoder->base.crtc = NULL;
9329}
9330
7fad798e
DV		 9331static void intel_enable_pipe_a(struct drm_device *dev)
9332{
9333 struct intel_connector *connector;
9334 struct drm_connector *crt = NULL;
9335 struct intel_load_detect_pipe load_detect_temp;
9336
9337 /* We can't just switch on the pipe A, we need to set things up with a
9338 * proper mode and output configuration. As a gross hack, enable pipe A
9339 * by enabling the load detect pipe once. */
9340 list_for_each_entry(connector,
9341 &dev->mode_config.connector_list,
9342 base.head) {
9343 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9344 crt = &connector->base;
9345 break;
9346 }
9347 }
9348
9349 if (!crt)
9350 return;
9351
9352 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9353 intel_release_load_detect_pipe(crt, &load_detect_temp);
9354
652c393a 9355
7fad798e
DV		 9356}
9357
fa555837
DV		 9358static bool
9359intel_check_plane_mapping(struct intel_crtc *crtc)
9360{
7eb552ae
BW		 9361 struct drm_device *dev = crtc->base.dev;
9362 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 9363 u32 reg, val;
9364
7eb552ae 9365 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 9366 return true;
9367
9368 reg = DSPCNTR(!crtc->plane);
9369 val = I915_READ(reg);
9370
9371 if ((val & DISPLAY_PLANE_ENABLE) &&
9372 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9373 return false;
9374
9375 return true;
9376}
9377
24929352
DV		 9378static void intel_sanitize_crtc(struct intel_crtc *crtc)
9379{
9380 struct drm_device *dev = crtc->base.dev;
9381 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 9382 u32 reg;
24929352 9383
24929352 9384 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 9385 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 9386 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9387
9388 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 9389 * disable the crtc (and hence change the state) if it is wrong. Note
9390 * that gen4+ has a fixed plane -> pipe mapping. */
9391 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 9392 struct intel_connector *connector;
9393 bool plane;
9394
24929352
DV		 9395 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9396 crtc->base.base.id);
9397
9398 /* Pipe has the wrong plane attached and the plane is active.
9399 * Temporarily change the plane mapping and disable everything
9400 * ... */
9401 plane = crtc->plane;
9402 crtc->plane = !plane;
9403 dev_priv->display.crtc_disable(&crtc->base);
9404 crtc->plane = plane;
9405
9406 /* ... and break all links. */
9407 list_for_each_entry(connector, &dev->mode_config.connector_list,
9408 base.head) {
9409 if (connector->encoder->base.crtc != &crtc->base)
9410 continue;
9411
9412 intel_connector_break_all_links(connector);
9413 }
9414
9415 WARN_ON(crtc->active);
9416 crtc->base.enabled = false;
9417 }
24929352 9418
7fad798e
DV		 9419 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9420 crtc->pipe == PIPE_A && !crtc->active) {
9421 /* BIOS forgot to enable pipe A, this mostly happens after
9422 * resume. Force-enable the pipe to fix this, the update_dpms
9423 * call below we restore the pipe to the right state, but leave
9424 * the required bits on. */
9425 intel_enable_pipe_a(dev);
9426 }
9427
24929352
DV		 9428 /* Adjust the state of the output pipe according to whether we
9429 * have active connectors/encoders. */
9430 intel_crtc_update_dpms(&crtc->base);
9431
9432 if (crtc->active != crtc->base.enabled) {
9433 struct intel_encoder *encoder;
9434
9435 /* This can happen either due to bugs in the get_hw_state
9436 * functions or because the pipe is force-enabled due to the
9437 * pipe A quirk. */
9438 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9439 crtc->base.base.id,
9440 crtc->base.enabled ? "enabled" : "disabled",
9441 crtc->active ? "enabled" : "disabled");
9442
9443 crtc->base.enabled = crtc->active;
9444
9445 /* Because we only establish the connector -> encoder ->
9446 * crtc links if something is active, this means the
9447 * crtc is now deactivated. Break the links. connector
9448 * -> encoder links are only establish when things are
9449 * actually up, hence no need to break them. */
9450 WARN_ON(crtc->active);
9451
9452 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9453 WARN_ON(encoder->connectors_active);
9454 encoder->base.crtc = NULL;
9455 }
9456 }
9457}
9458
9459static void intel_sanitize_encoder(struct intel_encoder *encoder)
9460{
9461 struct intel_connector *connector;
9462 struct drm_device *dev = encoder->base.dev;
9463
9464 /* We need to check both for a crtc link (meaning that the
9465 * encoder is active and trying to read from a pipe) and the
9466 * pipe itself being active. */
9467 bool has_active_crtc = encoder->base.crtc &&
9468 to_intel_crtc(encoder->base.crtc)->active;
9469
9470 if (encoder->connectors_active && !has_active_crtc) {
9471 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9472 encoder->base.base.id,
9473 drm_get_encoder_name(&encoder->base));
9474
9475 /* Connector is active, but has no active pipe. This is
9476 * fallout from our resume register restoring. Disable
9477 * the encoder manually again. */
9478 if (encoder->base.crtc) {
9479 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9480 encoder->base.base.id,
9481 drm_get_encoder_name(&encoder->base));
9482 encoder->disable(encoder);
9483 }
9484
9485 /* Inconsistent output/port/pipe state happens presumably due to
9486 * a bug in one of the get_hw_state functions. Or someplace else
9487 * in our code, like the register restore mess on resume. Clamp
9488 * things to off as a safer default. */
9489 list_for_each_entry(connector,
9490 &dev->mode_config.connector_list,
9491 base.head) {
9492 if (connector->encoder != encoder)
9493 continue;
9494
9495 intel_connector_break_all_links(connector);
9496 }
9497 }
9498 /* Enabled encoders without active connectors will be fixed in
9499 * the crtc fixup. */
9500}
9501
44cec740 9502void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9503{
9504 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9505 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9506
9507 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9508 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9509 i915_disable_vga(dev);
0fde901f
KM		 9510 }
9511}
9512
24929352
DV		 9513/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9514 * and i915 state tracking structures. */
45e2b5f6
DV		 9515void intel_modeset_setup_hw_state(struct drm_device *dev,
9516 bool force_restore)
24929352
DV		 9517{
9518 struct drm_i915_private *dev_priv = dev->dev_private;
9519 enum pipe pipe;
9520 u32 tmp;
b5644d05 9521 struct drm_plane *plane;
24929352
DV		 9522 struct intel_crtc *crtc;
9523 struct intel_encoder *encoder;
9524 struct intel_connector *connector;
9525
affa9354 9526 if (HAS_DDI(dev)) {
e28d54cb
PZ		 9527 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9528
9529 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9530 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9531 case TRANS_DDI_EDP_INPUT_A_ON:
9532 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9533 pipe = PIPE_A;
9534 break;
9535 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9536 pipe = PIPE_B;
9537 break;
9538 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9539 pipe = PIPE_C;
9540 break;
aaa148ec
DL		 9541 default:
9542 /* A bogus value has been programmed, disable
9543 * the transcoder */
9544 WARN(1, "Bogus eDP source %08x\n", tmp);
9545 intel_ddi_disable_transcoder_func(dev_priv,
9546 TRANSCODER_EDP);
9547 goto setup_pipes;
e28d54cb
PZ		 9548 }
9549
9550 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
3b117c8f 9551 crtc->config.cpu_transcoder = TRANSCODER_EDP;
e28d54cb
PZ		 9552
9553 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9554 pipe_name(pipe));
9555 }
9556 }
9557
aaa148ec 9558setup_pipes:
0e8ffe1b
DV		 9559 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9560 base.head) {
3b117c8f 9561 enum transcoder tmp = crtc->config.cpu_transcoder;
88adfff1 9562 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f
DV		 9563 crtc->config.cpu_transcoder = tmp;
9564
0e8ffe1b
DV		 9565 crtc->active = dev_priv->display.get_pipe_config(crtc,
9566 &crtc->config);
24929352
DV		 9567
9568 crtc->base.enabled = crtc->active;
9569
9570 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9571 crtc->base.base.id,
9572 crtc->active ? "enabled" : "disabled");
9573 }
9574
affa9354 9575 if (HAS_DDI(dev))
6441ab5f
PZ		 9576 intel_ddi_setup_hw_pll_state(dev);
9577
24929352
DV		 9578 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9579 base.head) {
9580 pipe = 0;
9581
9582 if (encoder->get_hw_state(encoder, &pipe)) {
9583 encoder->base.crtc =
9584 dev_priv->pipe_to_crtc_mapping[pipe];
9585 } else {
9586 encoder->base.crtc = NULL;
9587 }
9588
9589 encoder->connectors_active = false;
9590 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9591 encoder->base.base.id,
9592 drm_get_encoder_name(&encoder->base),
9593 encoder->base.crtc ? "enabled" : "disabled",
9594 pipe);
9595 }
9596
9597 list_for_each_entry(connector, &dev->mode_config.connector_list,
9598 base.head) {
9599 if (connector->get_hw_state(connector)) {
9600 connector->base.dpms = DRM_MODE_DPMS_ON;
9601 connector->encoder->connectors_active = true;
9602 connector->base.encoder = &connector->encoder->base;
9603 } else {
9604 connector->base.dpms = DRM_MODE_DPMS_OFF;
9605 connector->base.encoder = NULL;
9606 }
9607 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9608 connector->base.base.id,
9609 drm_get_connector_name(&connector->base),
9610 connector->base.encoder ? "enabled" : "disabled");
9611 }
9612
9613 /* HW state is read out, now we need to sanitize this mess. */
9614 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9615 base.head) {
9616 intel_sanitize_encoder(encoder);
9617 }
9618
9619 for_each_pipe(pipe) {
9620 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9621 intel_sanitize_crtc(crtc);
9622 }
9a935856 9623
45e2b5f6 9624 if (force_restore) {
f30da187
DV		 9625 /*
9626 * We need to use raw interfaces for restoring state to avoid
9627 * checking (bogus) intermediate states.
9628 */
45e2b5f6 9629 for_each_pipe(pipe) {
b5644d05
JB		 9630 struct drm_crtc *crtc =
9631 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 9632
9633 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9634 crtc->fb);
45e2b5f6 9635 }
b5644d05
JB		 9636 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9637 intel_plane_restore(plane);
0fde901f
KM		 9638
9639 i915_redisable_vga(dev);
45e2b5f6
DV		 9640 } else {
9641 intel_modeset_update_staged_output_state(dev);
9642 }
8af6cf88
DV		 9643
9644 intel_modeset_check_state(dev);
2e938892
DV		 9645
9646 drm_mode_config_reset(dev);
2c7111db
CW		 9647}
9648
9649void intel_modeset_gem_init(struct drm_device *dev)
9650{
1833b134 9651 intel_modeset_init_hw(dev);
02e792fb
DV		 9652
9653 intel_setup_overlay(dev);
24929352 9654
45e2b5f6 9655 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9656}
9657
9658void intel_modeset_cleanup(struct drm_device *dev)
9659{
652c393a
JB		 9660 struct drm_i915_private *dev_priv = dev->dev_private;
9661 struct drm_crtc *crtc;
9662 struct intel_crtc *intel_crtc;
9663
fd0c0642
DV		 9664 /*
9665 * Interrupts and polling as the first thing to avoid creating havoc.
9666 * Too much stuff here (turning of rps, connectors, ...) would
9667 * experience fancy races otherwise.
9668 */
9669 drm_irq_uninstall(dev);
9670 cancel_work_sync(&dev_priv->hotplug_work);
9671 /*
9672 * Due to the hpd irq storm handling the hotplug work can re-arm the
9673 * poll handlers. Hence disable polling after hpd handling is shut down.
9674 */
f87ea761 9675 drm_kms_helper_poll_fini(dev);
fd0c0642 9676
652c393a
JB		 9677 mutex_lock(&dev->struct_mutex);
9678
723bfd70
JB		 9679 intel_unregister_dsm_handler();
9680
652c393a
JB		 9681 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9682 /* Skip inactive CRTCs */
9683 if (!crtc->fb)
9684 continue;
9685
9686 intel_crtc = to_intel_crtc(crtc);
3dec0095 9687 intel_increase_pllclock(crtc);
652c393a
JB		 9688 }
9689
973d04f9 9690 intel_disable_fbc(dev);
e70236a8 9691
8090c6b9 9692 intel_disable_gt_powersave(dev);
0cdab21f 9693
930ebb46
DV		 9694 ironlake_teardown_rc6(dev);
9695
69341a5e
KH		 9696 mutex_unlock(&dev->struct_mutex);
9697
1630fe75
CW		 9698 /* flush any delayed tasks or pending work */
9699 flush_scheduled_work();
9700
dc652f90
JN		 9701 /* destroy backlight, if any, before the connectors */
9702 intel_panel_destroy_backlight(dev);
9703
79e53945 9704 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9705
9706 intel_cleanup_overlay(dev);
79e53945
JB		 9707}
9708
f1c79df3
ZW		 9709/*
9710 * Return which encoder is currently attached for connector.
9711 */
df0e9248 9712struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9713{
df0e9248
CW		 9714 return &intel_attached_encoder(connector)->base;
9715}
f1c79df3 9716
df0e9248
CW		 9717void intel_connector_attach_encoder(struct intel_connector *connector,
9718 struct intel_encoder *encoder)
9719{
9720 connector->encoder = encoder;
9721 drm_mode_connector_attach_encoder(&connector->base,
9722 &encoder->base);
79e53945 9723}
28d52043
DA		 9724
9725/*
9726 * set vga decode state - true == enable VGA decode
9727 */
9728int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9729{
9730 struct drm_i915_private *dev_priv = dev->dev_private;
9731 u16 gmch_ctrl;
9732
9733 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9734 if (state)
9735 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9736 else
9737 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9738 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9739 return 0;
9740}
c4a1d9e4
CW		 9741
9742#ifdef CONFIG_DEBUG_FS
9743#include <linux/seq_file.h>
9744
9745struct intel_display_error_state {
9746 struct intel_cursor_error_state {
9747 u32 control;
9748 u32 position;
9749 u32 base;
9750 u32 size;
52331309 9751 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9752
9753 struct intel_pipe_error_state {
9754 u32 conf;
9755 u32 source;
9756
9757 u32 htotal;
9758 u32 hblank;
9759 u32 hsync;
9760 u32 vtotal;
9761 u32 vblank;
9762 u32 vsync;
52331309 9763 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9764
9765 struct intel_plane_error_state {
9766 u32 control;
9767 u32 stride;
9768 u32 size;
9769 u32 pos;
9770 u32 addr;
9771 u32 surface;
9772 u32 tile_offset;
52331309 9773 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9774};
9775
9776struct intel_display_error_state *
9777intel_display_capture_error_state(struct drm_device *dev)
9778{
0206e353 9779 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9780 struct intel_display_error_state *error;
702e7a56 9781 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9782 int i;
9783
9784 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9785 if (error == NULL)
9786 return NULL;
9787
52331309 9788 for_each_pipe(i) {
702e7a56
PZ		 9789 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9790
a18c4c3d
PZ		 9791 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9792 error->cursor[i].control = I915_READ(CURCNTR(i));
9793 error->cursor[i].position = I915_READ(CURPOS(i));
9794 error->cursor[i].base = I915_READ(CURBASE(i));
9795 } else {
9796 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9797 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9798 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9799 }
c4a1d9e4
CW		 9800
9801 error->plane[i].control = I915_READ(DSPCNTR(i));
9802 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 9803 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9804 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 9805 error->plane[i].pos = I915_READ(DSPPOS(i));
9806 }
ca291363
PZ		 9807 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9808 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 9809 if (INTEL_INFO(dev)->gen >= 4) {
9810 error->plane[i].surface = I915_READ(DSPSURF(i));
9811 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9812 }
9813
702e7a56 9814 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9815 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9816 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9817 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9818 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9819 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9820 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9821 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9822 }
9823
9824 return error;
9825}
9826
9827void
9828intel_display_print_error_state(struct seq_file *m,
9829 struct drm_device *dev,
9830 struct intel_display_error_state *error)
9831{
9832 int i;
9833
7eb552ae 9834 seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
52331309 9835 for_each_pipe(i) {
c4a1d9e4
CW		 9836 seq_printf(m, "Pipe [%d]:\n", i);
9837 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9838 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9839 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9840 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9841 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9842 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9843 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9844 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9845
9846 seq_printf(m, "Plane [%d]:\n", i);
9847 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9848 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 9849 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9850 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
80ca378b
PZ		 9851 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9852 }
4b71a570 9853 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
ca291363 9854 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4
CW		 9855 if (INTEL_INFO(dev)->gen >= 4) {
9856 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9857 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9858 }
9859
9860 seq_printf(m, "Cursor [%d]:\n", i);
9861 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9862 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9863 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9864 }
9865}
9866#endif
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