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drm/i915: split out intel_pnv_find_best_PLL
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
79e53945 48typedef struct {
0206e353 49 int min, max;
79e53945
JB		 50} intel_range_t;
51
52typedef struct {
0206e353
AJ		 53 int dot_limit;
54 int p2_slow, p2_fast;
79e53945
JB		 55} intel_p2_t;
56
57#define INTEL_P2_NUM 2
d4906093
ML		 58typedef struct intel_limit intel_limit_t;
59struct intel_limit {
0206e353
AJ		 60 intel_range_t dot, vco, n, m, m1, m2, p, p1;
61 intel_p2_t p2;
f4808ab8
VS		 62 /**
63 * find_pll() - Find the best values for the PLL
64 * @limit: limits for the PLL
65 * @crtc: current CRTC
66 * @target: target frequency in kHz
67 * @refclk: reference clock frequency in kHz
68 * @match_clock: if provided, @best_clock P divider must
69 * match the P divider from @match_clock
70 * used for LVDS downclocking
71 * @best_clock: best PLL values found
72 *
73 * Returns true on success, false on failure.
74 */
75 bool (*find_pll)(const intel_limit_t *limit,
76 struct drm_crtc *crtc,
77 int target, int refclk,
78 intel_clock_t *match_clock,
79 intel_clock_t *best_clock);
d4906093 80};
79e53945 81
2377b741
JB		 82/* FDI */
83#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
84
d2acd215
DV		 85int
86intel_pch_rawclk(struct drm_device *dev)
87{
88 struct drm_i915_private *dev_priv = dev->dev_private;
89
90 WARN_ON(!HAS_PCH_SPLIT(dev));
91
92 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
93}
94
d4906093
ML		 95static bool
96intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 97 int target, int refclk, intel_clock_t *match_clock,
98 intel_clock_t *best_clock);
d4906093 99static bool
ac58c3f0
DV		 100intel_pnv_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
101 int target, int refclk, intel_clock_t *match_clock,
102 intel_clock_t *best_clock);
103static bool
d4906093 104intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 105 int target, int refclk, intel_clock_t *match_clock,
106 intel_clock_t *best_clock);
a0c4da24
JB		 107static bool
108intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
109 int target, int refclk, intel_clock_t *match_clock,
110 intel_clock_t *best_clock);
111
021357ac
CW		 112static inline u32 /* units of 100MHz */
113intel_fdi_link_freq(struct drm_device *dev)
114{
8b99e68c
CW		 115 if (IS_GEN5(dev)) {
116 struct drm_i915_private *dev_priv = dev->dev_private;
117 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
118 } else
119 return 27;
021357ac
CW		 120}
121
e4b36699 122static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 123 .dot = { .min = 25000, .max = 350000 },
124 .vco = { .min = 930000, .max = 1400000 },
125 .n = { .min = 3, .max = 16 },
126 .m = { .min = 96, .max = 140 },
127 .m1 = { .min = 18, .max = 26 },
128 .m2 = { .min = 6, .max = 16 },
129 .p = { .min = 4, .max = 128 },
130 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 131 .p2 = { .dot_limit = 165000,
132 .p2_slow = 4, .p2_fast = 2 },
d4906093 133 .find_pll = intel_find_best_PLL,
e4b36699
KP		 134};
135
136static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 137 .dot = { .min = 25000, .max = 350000 },
138 .vco = { .min = 930000, .max = 1400000 },
139 .n = { .min = 3, .max = 16 },
140 .m = { .min = 96, .max = 140 },
141 .m1 = { .min = 18, .max = 26 },
142 .m2 = { .min = 6, .max = 16 },
143 .p = { .min = 4, .max = 128 },
144 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 145 .p2 = { .dot_limit = 165000,
146 .p2_slow = 14, .p2_fast = 7 },
d4906093 147 .find_pll = intel_find_best_PLL,
e4b36699 148};
273e27ca 149
e4b36699 150static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 151 .dot = { .min = 20000, .max = 400000 },
152 .vco = { .min = 1400000, .max = 2800000 },
153 .n = { .min = 1, .max = 6 },
154 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 155 .m1 = { .min = 8, .max = 18 },
156 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 157 .p = { .min = 5, .max = 80 },
158 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 159 .p2 = { .dot_limit = 200000,
160 .p2_slow = 10, .p2_fast = 5 },
d4906093 161 .find_pll = intel_find_best_PLL,
e4b36699
KP		 162};
163
164static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 165 .dot = { .min = 20000, .max = 400000 },
166 .vco = { .min = 1400000, .max = 2800000 },
167 .n = { .min = 1, .max = 6 },
168 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 169 .m1 = { .min = 8, .max = 18 },
170 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 171 .p = { .min = 7, .max = 98 },
172 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 173 .p2 = { .dot_limit = 112000,
174 .p2_slow = 14, .p2_fast = 7 },
d4906093 175 .find_pll = intel_find_best_PLL,
e4b36699
KP		 176};
177
273e27ca 178
e4b36699 179static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 180 .dot = { .min = 25000, .max = 270000 },
181 .vco = { .min = 1750000, .max = 3500000},
182 .n = { .min = 1, .max = 4 },
183 .m = { .min = 104, .max = 138 },
184 .m1 = { .min = 17, .max = 23 },
185 .m2 = { .min = 5, .max = 11 },
186 .p = { .min = 10, .max = 30 },
187 .p1 = { .min = 1, .max = 3},
188 .p2 = { .dot_limit = 270000,
189 .p2_slow = 10,
190 .p2_fast = 10
044c7c41 191 },
d4906093 192 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 193};
194
195static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 196 .dot = { .min = 22000, .max = 400000 },
197 .vco = { .min = 1750000, .max = 3500000},
198 .n = { .min = 1, .max = 4 },
199 .m = { .min = 104, .max = 138 },
200 .m1 = { .min = 16, .max = 23 },
201 .m2 = { .min = 5, .max = 11 },
202 .p = { .min = 5, .max = 80 },
203 .p1 = { .min = 1, .max = 8},
204 .p2 = { .dot_limit = 165000,
205 .p2_slow = 10, .p2_fast = 5 },
d4906093 206 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 207};
208
209static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 210 .dot = { .min = 20000, .max = 115000 },
211 .vco = { .min = 1750000, .max = 3500000 },
212 .n = { .min = 1, .max = 3 },
213 .m = { .min = 104, .max = 138 },
214 .m1 = { .min = 17, .max = 23 },
215 .m2 = { .min = 5, .max = 11 },
216 .p = { .min = 28, .max = 112 },
217 .p1 = { .min = 2, .max = 8 },
218 .p2 = { .dot_limit = 0,
219 .p2_slow = 14, .p2_fast = 14
044c7c41 220 },
d4906093 221 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 222};
223
224static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 225 .dot = { .min = 80000, .max = 224000 },
226 .vco = { .min = 1750000, .max = 3500000 },
227 .n = { .min = 1, .max = 3 },
228 .m = { .min = 104, .max = 138 },
229 .m1 = { .min = 17, .max = 23 },
230 .m2 = { .min = 5, .max = 11 },
231 .p = { .min = 14, .max = 42 },
232 .p1 = { .min = 2, .max = 6 },
233 .p2 = { .dot_limit = 0,
234 .p2_slow = 7, .p2_fast = 7
044c7c41 235 },
d4906093 236 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 237};
238
f2b115e6 239static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 240 .dot = { .min = 20000, .max = 400000},
241 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 242 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 243 .n = { .min = 3, .max = 6 },
244 .m = { .min = 2, .max = 256 },
273e27ca 245 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 246 .m1 = { .min = 0, .max = 0 },
247 .m2 = { .min = 0, .max = 254 },
248 .p = { .min = 5, .max = 80 },
249 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 250 .p2 = { .dot_limit = 200000,
251 .p2_slow = 10, .p2_fast = 5 },
ac58c3f0 252 .find_pll = intel_pnv_find_best_PLL,
e4b36699
KP		 253};
254
f2b115e6 255static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 256 .dot = { .min = 20000, .max = 400000 },
257 .vco = { .min = 1700000, .max = 3500000 },
258 .n = { .min = 3, .max = 6 },
259 .m = { .min = 2, .max = 256 },
260 .m1 = { .min = 0, .max = 0 },
261 .m2 = { .min = 0, .max = 254 },
262 .p = { .min = 7, .max = 112 },
263 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 264 .p2 = { .dot_limit = 112000,
265 .p2_slow = 14, .p2_fast = 14 },
ac58c3f0 266 .find_pll = intel_pnv_find_best_PLL,
e4b36699
KP		 267};
268
273e27ca
EA		 269/* Ironlake / Sandybridge
270 *
271 * We calculate clock using (register_value + 2) for N/M1/M2, so here
272 * the range value for them is (actual_value - 2).
273 */
b91ad0ec 274static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 275 .dot = { .min = 25000, .max = 350000 },
276 .vco = { .min = 1760000, .max = 3510000 },
277 .n = { .min = 1, .max = 5 },
278 .m = { .min = 79, .max = 127 },
279 .m1 = { .min = 12, .max = 22 },
280 .m2 = { .min = 5, .max = 9 },
281 .p = { .min = 5, .max = 80 },
282 .p1 = { .min = 1, .max = 8 },
283 .p2 = { .dot_limit = 225000,
284 .p2_slow = 10, .p2_fast = 5 },
4547668a 285 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 286};
287
b91ad0ec 288static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 289 .dot = { .min = 25000, .max = 350000 },
290 .vco = { .min = 1760000, .max = 3510000 },
291 .n = { .min = 1, .max = 3 },
292 .m = { .min = 79, .max = 118 },
293 .m1 = { .min = 12, .max = 22 },
294 .m2 = { .min = 5, .max = 9 },
295 .p = { .min = 28, .max = 112 },
296 .p1 = { .min = 2, .max = 8 },
297 .p2 = { .dot_limit = 225000,
298 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 299 .find_pll = intel_g4x_find_best_PLL,
300};
301
302static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 303 .dot = { .min = 25000, .max = 350000 },
304 .vco = { .min = 1760000, .max = 3510000 },
305 .n = { .min = 1, .max = 3 },
306 .m = { .min = 79, .max = 127 },
307 .m1 = { .min = 12, .max = 22 },
308 .m2 = { .min = 5, .max = 9 },
309 .p = { .min = 14, .max = 56 },
310 .p1 = { .min = 2, .max = 8 },
311 .p2 = { .dot_limit = 225000,
312 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 313 .find_pll = intel_g4x_find_best_PLL,
314};
315
273e27ca 316/* LVDS 100mhz refclk limits. */
b91ad0ec 317static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 318 .dot = { .min = 25000, .max = 350000 },
319 .vco = { .min = 1760000, .max = 3510000 },
320 .n = { .min = 1, .max = 2 },
321 .m = { .min = 79, .max = 126 },
322 .m1 = { .min = 12, .max = 22 },
323 .m2 = { .min = 5, .max = 9 },
324 .p = { .min = 28, .max = 112 },
0206e353 325 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 326 .p2 = { .dot_limit = 225000,
327 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 328 .find_pll = intel_g4x_find_best_PLL,
329};
330
331static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 332 .dot = { .min = 25000, .max = 350000 },
333 .vco = { .min = 1760000, .max = 3510000 },
334 .n = { .min = 1, .max = 3 },
335 .m = { .min = 79, .max = 126 },
336 .m1 = { .min = 12, .max = 22 },
337 .m2 = { .min = 5, .max = 9 },
338 .p = { .min = 14, .max = 42 },
0206e353 339 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 340 .p2 = { .dot_limit = 225000,
341 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 342 .find_pll = intel_g4x_find_best_PLL,
343};
344
a0c4da24
JB		 345static const intel_limit_t intel_limits_vlv_dac = {
346 .dot = { .min = 25000, .max = 270000 },
347 .vco = { .min = 4000000, .max = 6000000 },
348 .n = { .min = 1, .max = 7 },
349 .m = { .min = 22, .max = 450 }, /* guess */
350 .m1 = { .min = 2, .max = 3 },
351 .m2 = { .min = 11, .max = 156 },
352 .p = { .min = 10, .max = 30 },
75e53986 353 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 354 .p2 = { .dot_limit = 270000,
355 .p2_slow = 2, .p2_fast = 20 },
356 .find_pll = intel_vlv_find_best_pll,
357};
358
359static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 360 .dot = { .min = 25000, .max = 270000 },
361 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 362 .n = { .min = 1, .max = 7 },
363 .m = { .min = 60, .max = 300 }, /* guess */
364 .m1 = { .min = 2, .max = 3 },
365 .m2 = { .min = 11, .max = 156 },
366 .p = { .min = 10, .max = 30 },
367 .p1 = { .min = 2, .max = 3 },
368 .p2 = { .dot_limit = 270000,
369 .p2_slow = 2, .p2_fast = 20 },
370 .find_pll = intel_vlv_find_best_pll,
371};
372
373static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 374 .dot = { .min = 25000, .max = 270000 },
375 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 376 .n = { .min = 1, .max = 7 },
74a4dd2e 377 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 378 .m1 = { .min = 2, .max = 3 },
379 .m2 = { .min = 11, .max = 156 },
380 .p = { .min = 10, .max = 30 },
75e53986 381 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 382 .p2 = { .dot_limit = 270000,
383 .p2_slow = 2, .p2_fast = 20 },
384 .find_pll = intel_vlv_find_best_pll,
385};
386
1b894b59
CW		 387static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
388 int refclk)
2c07245f 389{
b91ad0ec 390 struct drm_device *dev = crtc->dev;
2c07245f 391 const intel_limit_t *limit;
b91ad0ec
ZW		 392
393 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 394 if (intel_is_dual_link_lvds(dev)) {
1b894b59 395 if (refclk == 100000)
b91ad0ec
ZW		 396 limit = &intel_limits_ironlake_dual_lvds_100m;
397 else
398 limit = &intel_limits_ironlake_dual_lvds;
399 } else {
1b894b59 400 if (refclk == 100000)
b91ad0ec
ZW		 401 limit = &intel_limits_ironlake_single_lvds_100m;
402 else
403 limit = &intel_limits_ironlake_single_lvds;
404 }
c6bb3538 405 } else
b91ad0ec 406 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 407
408 return limit;
409}
410
044c7c41
ML		 411static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
412{
413 struct drm_device *dev = crtc->dev;
044c7c41
ML		 414 const intel_limit_t *limit;
415
416 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 417 if (intel_is_dual_link_lvds(dev))
e4b36699 418 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 419 else
e4b36699 420 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 421 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
422 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 423 limit = &intel_limits_g4x_hdmi;
044c7c41 424 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 425 limit = &intel_limits_g4x_sdvo;
044c7c41 426 } else /* The option is for other outputs */
e4b36699 427 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 428
429 return limit;
430}
431
1b894b59 432static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 433{
434 struct drm_device *dev = crtc->dev;
435 const intel_limit_t *limit;
436
bad720ff 437 if (HAS_PCH_SPLIT(dev))
1b894b59 438 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 439 else if (IS_G4X(dev)) {
044c7c41 440 limit = intel_g4x_limit(crtc);
f2b115e6 441 } else if (IS_PINEVIEW(dev)) {
2177832f 442 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 443 limit = &intel_limits_pineview_lvds;
2177832f 444 else
f2b115e6 445 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 446 } else if (IS_VALLEYVIEW(dev)) {
447 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
448 limit = &intel_limits_vlv_dac;
449 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
450 limit = &intel_limits_vlv_hdmi;
451 else
452 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 453 } else if (!IS_GEN2(dev)) {
454 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
455 limit = &intel_limits_i9xx_lvds;
456 else
457 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 458 } else {
459 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 460 limit = &intel_limits_i8xx_lvds;
79e53945 461 else
e4b36699 462 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 463 }
464 return limit;
465}
466
f2b115e6
AJ		 467/* m1 is reserved as 0 in Pineview, n is a ring counter */
468static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 469{
2177832f
SL		 470 clock->m = clock->m2 + 2;
471 clock->p = clock->p1 * clock->p2;
472 clock->vco = refclk * clock->m / clock->n;
473 clock->dot = clock->vco / clock->p;
474}
475
7429e9d4
DV		 476static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
477{
478 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
479}
480
ac58c3f0 481static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 482{
7429e9d4 483 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 484 clock->p = clock->p1 * clock->p2;
485 clock->vco = refclk * clock->m / (clock->n + 2);
486 clock->dot = clock->vco / clock->p;
487}
488
79e53945
JB		 489/**
490 * Returns whether any output on the specified pipe is of the specified type
491 */
4ef69c7a 492bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 493{
4ef69c7a 494 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 495 struct intel_encoder *encoder;
496
6c2b7c12
DV		 497 for_each_encoder_on_crtc(dev, crtc, encoder)
498 if (encoder->type == type)
4ef69c7a
CW		 499 return true;
500
501 return false;
79e53945
JB		 502}
503
7c04d1d9 504#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 505/**
506 * Returns whether the given set of divisors are valid for a given refclk with
507 * the given connectors.
508 */
509
1b894b59
CW		 510static bool intel_PLL_is_valid(struct drm_device *dev,
511 const intel_limit_t *limit,
512 const intel_clock_t *clock)
79e53945 513{
79e53945 514 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 515 INTELPllInvalid("p1 out of range\n");
79e53945 516 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 517 INTELPllInvalid("p out of range\n");
79e53945 518 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 519 INTELPllInvalid("m2 out of range\n");
79e53945 520 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 521 INTELPllInvalid("m1 out of range\n");
f2b115e6 522 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 523 INTELPllInvalid("m1 <= m2\n");
79e53945 524 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 525 INTELPllInvalid("m out of range\n");
79e53945 526 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 527 INTELPllInvalid("n out of range\n");
79e53945 528 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 529 INTELPllInvalid("vco out of range\n");
79e53945
JB		 530 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
531 * connector, etc., rather than just a single range.
532 */
533 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 534 INTELPllInvalid("dot out of range\n");
79e53945
JB		 535
536 return true;
537}
538
d4906093
ML		 539static bool
540intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 541 int target, int refclk, intel_clock_t *match_clock,
542 intel_clock_t *best_clock)
ac58c3f0
DV		 543{
544 struct drm_device *dev = crtc->dev;
545 intel_clock_t clock;
546 int err = target;
547
548 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
549 /*
550 * For LVDS just rely on its current settings for dual-channel.
551 * We haven't figured out how to reliably set up different
552 * single/dual channel state, if we even can.
553 */
554 if (intel_is_dual_link_lvds(dev))
555 clock.p2 = limit->p2.p2_fast;
556 else
557 clock.p2 = limit->p2.p2_slow;
558 } else {
559 if (target < limit->p2.dot_limit)
560 clock.p2 = limit->p2.p2_slow;
561 else
562 clock.p2 = limit->p2.p2_fast;
563 }
564
565 memset(best_clock, 0, sizeof(*best_clock));
566
567 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
568 clock.m1++) {
569 for (clock.m2 = limit->m2.min;
570 clock.m2 <= limit->m2.max; clock.m2++) {
571 /* m1 is always 0 in Pineview */
572 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
573 break;
574 for (clock.n = limit->n.min;
575 clock.n <= limit->n.max; clock.n++) {
576 for (clock.p1 = limit->p1.min;
577 clock.p1 <= limit->p1.max; clock.p1++) {
578 int this_err;
d4906093 579
ac58c3f0
DV		 580 i9xx_clock(refclk, &clock);
581 if (!intel_PLL_is_valid(dev, limit,
582 &clock))
583 continue;
584 if (match_clock &&
585 clock.p != match_clock->p)
586 continue;
587
588 this_err = abs(clock.dot - target);
589 if (this_err < err) {
590 *best_clock = clock;
591 err = this_err;
592 }
593 }
594 }
595 }
596 }
597
598 return (err != target);
599}
600
601static bool
602intel_pnv_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
603 int target, int refclk, intel_clock_t *match_clock,
604 intel_clock_t *best_clock)
79e53945
JB		 605{
606 struct drm_device *dev = crtc->dev;
79e53945 607 intel_clock_t clock;
79e53945
JB		 608 int err = target;
609
a210b028 610 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 611 /*
a210b028
DV		 612 * For LVDS just rely on its current settings for dual-channel.
613 * We haven't figured out how to reliably set up different
614 * single/dual channel state, if we even can.
79e53945 615 */
1974cad0 616 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 617 clock.p2 = limit->p2.p2_fast;
618 else
619 clock.p2 = limit->p2.p2_slow;
620 } else {
621 if (target < limit->p2.dot_limit)
622 clock.p2 = limit->p2.p2_slow;
623 else
624 clock.p2 = limit->p2.p2_fast;
625 }
626
0206e353 627 memset(best_clock, 0, sizeof(*best_clock));
79e53945 628
42158660
ZY		 629 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
630 clock.m1++) {
631 for (clock.m2 = limit->m2.min;
632 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 633 /* m1 is always 0 in Pineview */
634 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 635 break;
636 for (clock.n = limit->n.min;
637 clock.n <= limit->n.max; clock.n++) {
638 for (clock.p1 = limit->p1.min;
639 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 640 int this_err;
641
ac58c3f0 642 pineview_clock(refclk, &clock);
1b894b59
CW		 643 if (!intel_PLL_is_valid(dev, limit,
644 &clock))
79e53945 645 continue;
cec2f356
SP		 646 if (match_clock &&
647 clock.p != match_clock->p)
648 continue;
79e53945
JB		 649
650 this_err = abs(clock.dot - target);
651 if (this_err < err) {
652 *best_clock = clock;
653 err = this_err;
654 }
655 }
656 }
657 }
658 }
659
660 return (err != target);
661}
662
d4906093
ML		 663static bool
664intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 665 int target, int refclk, intel_clock_t *match_clock,
666 intel_clock_t *best_clock)
d4906093
ML		 667{
668 struct drm_device *dev = crtc->dev;
d4906093
ML		 669 intel_clock_t clock;
670 int max_n;
671 bool found;
6ba770dc
AJ		 672 /* approximately equals target * 0.00585 */
673 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 674 found = false;
675
676 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 677 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 678 clock.p2 = limit->p2.p2_fast;
679 else
680 clock.p2 = limit->p2.p2_slow;
681 } else {
682 if (target < limit->p2.dot_limit)
683 clock.p2 = limit->p2.p2_slow;
684 else
685 clock.p2 = limit->p2.p2_fast;
686 }
687
688 memset(best_clock, 0, sizeof(*best_clock));
689 max_n = limit->n.max;
f77f13e2 690 /* based on hardware requirement, prefer smaller n to precision */
d4906093 691 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 692 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 693 for (clock.m1 = limit->m1.max;
694 clock.m1 >= limit->m1.min; clock.m1--) {
695 for (clock.m2 = limit->m2.max;
696 clock.m2 >= limit->m2.min; clock.m2--) {
697 for (clock.p1 = limit->p1.max;
698 clock.p1 >= limit->p1.min; clock.p1--) {
699 int this_err;
700
ac58c3f0 701 i9xx_clock(refclk, &clock);
1b894b59
CW		 702 if (!intel_PLL_is_valid(dev, limit,
703 &clock))
d4906093 704 continue;
1b894b59
CW		 705
706 this_err = abs(clock.dot - target);
d4906093
ML		 707 if (this_err < err_most) {
708 *best_clock = clock;
709 err_most = this_err;
710 max_n = clock.n;
711 found = true;
712 }
713 }
714 }
715 }
716 }
2c07245f
ZW		 717 return found;
718}
719
a0c4da24
JB		 720static bool
721intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
722 int target, int refclk, intel_clock_t *match_clock,
723 intel_clock_t *best_clock)
724{
725 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
726 u32 m, n, fastclk;
727 u32 updrate, minupdate, fracbits, p;
728 unsigned long bestppm, ppm, absppm;
729 int dotclk, flag;
730
af447bd3 731 flag = 0;
a0c4da24
JB		 732 dotclk = target * 1000;
733 bestppm = 1000000;
734 ppm = absppm = 0;
735 fastclk = dotclk / (2*100);
736 updrate = 0;
737 minupdate = 19200;
738 fracbits = 1;
739 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
740 bestm1 = bestm2 = bestp1 = bestp2 = 0;
741
742 /* based on hardware requirement, prefer smaller n to precision */
743 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
744 updrate = refclk / n;
745 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
746 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
747 if (p2 > 10)
748 p2 = p2 - 1;
749 p = p1 * p2;
750 /* based on hardware requirement, prefer bigger m1,m2 values */
751 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
752 m2 = (((2*(fastclk * p * n / m1 )) +
753 refclk) / (2*refclk));
754 m = m1 * m2;
755 vco = updrate * m;
756 if (vco >= limit->vco.min && vco < limit->vco.max) {
757 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
758 absppm = (ppm > 0) ? ppm : (-ppm);
759 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
760 bestppm = 0;
761 flag = 1;
762 }
763 if (absppm < bestppm - 10) {
764 bestppm = absppm;
765 flag = 1;
766 }
767 if (flag) {
768 bestn = n;
769 bestm1 = m1;
770 bestm2 = m2;
771 bestp1 = p1;
772 bestp2 = p2;
773 flag = 0;
774 }
775 }
776 }
777 }
778 }
779 }
780 best_clock->n = bestn;
781 best_clock->m1 = bestm1;
782 best_clock->m2 = bestm2;
783 best_clock->p1 = bestp1;
784 best_clock->p2 = bestp2;
785
786 return true;
787}
a4fc5ed6 788
a5c961d1
PZ		 789enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
790 enum pipe pipe)
791{
792 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
793 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
794
3b117c8f 795 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 796}
797
a928d536
PZ		 798static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
799{
800 struct drm_i915_private *dev_priv = dev->dev_private;
801 u32 frame, frame_reg = PIPEFRAME(pipe);
802
803 frame = I915_READ(frame_reg);
804
805 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
806 DRM_DEBUG_KMS("vblank wait timed out\n");
807}
808
9d0498a2
JB		 809/**
810 * intel_wait_for_vblank - wait for vblank on a given pipe
811 * @dev: drm device
812 * @pipe: pipe to wait for
813 *
814 * Wait for vblank to occur on a given pipe. Needed for various bits of
815 * mode setting code.
816 */
817void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 818{
9d0498a2 819 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 820 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 821
a928d536
PZ		 822 if (INTEL_INFO(dev)->gen >= 5) {
823 ironlake_wait_for_vblank(dev, pipe);
824 return;
825 }
826
300387c0
CW		 827 /* Clear existing vblank status. Note this will clear any other
828 * sticky status fields as well.
829 *
830 * This races with i915_driver_irq_handler() with the result
831 * that either function could miss a vblank event. Here it is not
832 * fatal, as we will either wait upon the next vblank interrupt or
833 * timeout. Generally speaking intel_wait_for_vblank() is only
834 * called during modeset at which time the GPU should be idle and
835 * should *not* be performing page flips and thus not waiting on
836 * vblanks...
837 * Currently, the result of us stealing a vblank from the irq
838 * handler is that a single frame will be skipped during swapbuffers.
839 */
840 I915_WRITE(pipestat_reg,
841 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
842
9d0498a2 843 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 844 if (wait_for(I915_READ(pipestat_reg) &
845 PIPE_VBLANK_INTERRUPT_STATUS,
846 50))
9d0498a2
JB		 847 DRM_DEBUG_KMS("vblank wait timed out\n");
848}
849
ab7ad7f6
KP		 850/*
851 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 852 * @dev: drm device
853 * @pipe: pipe to wait for
854 *
855 * After disabling a pipe, we can't wait for vblank in the usual way,
856 * spinning on the vblank interrupt status bit, since we won't actually
857 * see an interrupt when the pipe is disabled.
858 *
ab7ad7f6
KP		 859 * On Gen4 and above:
860 * wait for the pipe register state bit to turn off
861 *
862 * Otherwise:
863 * wait for the display line value to settle (it usually
864 * ends up stopping at the start of the next frame).
58e10eb9 865 *
9d0498a2 866 */
58e10eb9 867void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 868{
869 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 870 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
871 pipe);
ab7ad7f6
KP		 872
873 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 874 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 875
876 /* Wait for the Pipe State to go off */
58e10eb9
CW		 877 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
878 100))
284637d9 879 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 880 } else {
837ba00f 881 u32 last_line, line_mask;
58e10eb9 882 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 883 unsigned long timeout = jiffies + msecs_to_jiffies(100);
884
837ba00f
PZ		 885 if (IS_GEN2(dev))
886 line_mask = DSL_LINEMASK_GEN2;
887 else
888 line_mask = DSL_LINEMASK_GEN3;
889
ab7ad7f6
KP		 890 /* Wait for the display line to settle */
891 do {
837ba00f 892 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 893 mdelay(5);
837ba00f 894 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 895 time_after(timeout, jiffies));
896 if (time_after(jiffies, timeout))
284637d9 897 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 898 }
79e53945
JB		 899}
900
b0ea7d37
DL		 901/*
902 * ibx_digital_port_connected - is the specified port connected?
903 * @dev_priv: i915 private structure
904 * @port: the port to test
905 *
906 * Returns true if @port is connected, false otherwise.
907 */
908bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
909 struct intel_digital_port *port)
910{
911 u32 bit;
912
c36346e3
DL		 913 if (HAS_PCH_IBX(dev_priv->dev)) {
914 switch(port->port) {
915 case PORT_B:
916 bit = SDE_PORTB_HOTPLUG;
917 break;
918 case PORT_C:
919 bit = SDE_PORTC_HOTPLUG;
920 break;
921 case PORT_D:
922 bit = SDE_PORTD_HOTPLUG;
923 break;
924 default:
925 return true;
926 }
927 } else {
928 switch(port->port) {
929 case PORT_B:
930 bit = SDE_PORTB_HOTPLUG_CPT;
931 break;
932 case PORT_C:
933 bit = SDE_PORTC_HOTPLUG_CPT;
934 break;
935 case PORT_D:
936 bit = SDE_PORTD_HOTPLUG_CPT;
937 break;
938 default:
939 return true;
940 }
b0ea7d37
DL		 941 }
942
943 return I915_READ(SDEISR) & bit;
944}
945
b24e7179
JB		 946static const char *state_string(bool enabled)
947{
948 return enabled ? "on" : "off";
949}
950
951/* Only for pre-ILK configs */
952static void assert_pll(struct drm_i915_private *dev_priv,
953 enum pipe pipe, bool state)
954{
955 int reg;
956 u32 val;
957 bool cur_state;
958
959 reg = DPLL(pipe);
960 val = I915_READ(reg);
961 cur_state = !!(val & DPLL_VCO_ENABLE);
962 WARN(cur_state != state,
963 "PLL state assertion failure (expected %s, current %s)\n",
964 state_string(state), state_string(cur_state));
965}
966#define assert_pll_enabled(d, p) assert_pll(d, p, true)
967#define assert_pll_disabled(d, p) assert_pll(d, p, false)
968
040484af
JB		 969/* For ILK+ */
970static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 971 struct intel_pch_pll *pll,
972 struct intel_crtc *crtc,
973 bool state)
040484af 974{
040484af
JB		 975 u32 val;
976 bool cur_state;
977
9d82aa17
ED		 978 if (HAS_PCH_LPT(dev_priv->dev)) {
979 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
980 return;
981 }
982
92b27b08
CW		 983 if (WARN (!pll,
984 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 985 return;
ee7b9f93 986
92b27b08
CW		 987 val = I915_READ(pll->pll_reg);
988 cur_state = !!(val & DPLL_VCO_ENABLE);
989 WARN(cur_state != state,
990 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
991 pll->pll_reg, state_string(state), state_string(cur_state), val);
992
993 /* Make sure the selected PLL is correctly attached to the transcoder */
994 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 995 u32 pch_dpll;
996
997 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 998 cur_state = pll->pll_reg == _PCH_DPLL_B;
999 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
4bb6f1f3
VS		 1000 "PLL[%d] not attached to this transcoder %c: %08x\n",
1001 cur_state, pipe_name(crtc->pipe), pch_dpll)) {
92b27b08
CW		 1002 cur_state = !!(val >> (4*crtc->pipe + 3));
1003 WARN(cur_state != state,
4bb6f1f3 1004 "PLL[%d] not %s on this transcoder %c: %08x\n",
92b27b08
CW		 1005 pll->pll_reg == _PCH_DPLL_B,
1006 state_string(state),
4bb6f1f3 1007 pipe_name(crtc->pipe),
92b27b08
CW		 1008 val);
1009 }
d3ccbe86 1010 }
040484af 1011}
92b27b08
CW		 1012#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1013#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1014
1015static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1016 enum pipe pipe, bool state)
1017{
1018 int reg;
1019 u32 val;
1020 bool cur_state;
ad80a810
PZ		 1021 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1022 pipe);
040484af 1023
affa9354
PZ		 1024 if (HAS_DDI(dev_priv->dev)) {
1025 /* DDI does not have a specific FDI_TX register */
ad80a810 1026 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1027 val = I915_READ(reg);
ad80a810 1028 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1029 } else {
1030 reg = FDI_TX_CTL(pipe);
1031 val = I915_READ(reg);
1032 cur_state = !!(val & FDI_TX_ENABLE);
1033 }
040484af
JB		 1034 WARN(cur_state != state,
1035 "FDI TX state assertion failure (expected %s, current %s)\n",
1036 state_string(state), state_string(cur_state));
1037}
1038#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1039#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1040
1041static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1042 enum pipe pipe, bool state)
1043{
1044 int reg;
1045 u32 val;
1046 bool cur_state;
1047
d63fa0dc
PZ		 1048 reg = FDI_RX_CTL(pipe);
1049 val = I915_READ(reg);
1050 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1051 WARN(cur_state != state,
1052 "FDI RX state assertion failure (expected %s, current %s)\n",
1053 state_string(state), state_string(cur_state));
1054}
1055#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1056#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1057
1058static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1059 enum pipe pipe)
1060{
1061 int reg;
1062 u32 val;
1063
1064 /* ILK FDI PLL is always enabled */
1065 if (dev_priv->info->gen == 5)
1066 return;
1067
bf507ef7 1068 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1069 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1070 return;
1071
040484af
JB		 1072 reg = FDI_TX_CTL(pipe);
1073 val = I915_READ(reg);
1074 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1075}
1076
1077static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1078 enum pipe pipe)
1079{
1080 int reg;
1081 u32 val;
1082
1083 reg = FDI_RX_CTL(pipe);
1084 val = I915_READ(reg);
1085 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1086}
1087
ea0760cf
JB		 1088static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1089 enum pipe pipe)
1090{
1091 int pp_reg, lvds_reg;
1092 u32 val;
1093 enum pipe panel_pipe = PIPE_A;
0de3b485 1094 bool locked = true;
ea0760cf
JB		 1095
1096 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1097 pp_reg = PCH_PP_CONTROL;
1098 lvds_reg = PCH_LVDS;
1099 } else {
1100 pp_reg = PP_CONTROL;
1101 lvds_reg = LVDS;
1102 }
1103
1104 val = I915_READ(pp_reg);
1105 if (!(val & PANEL_POWER_ON) ||
1106 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1107 locked = false;
1108
1109 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1110 panel_pipe = PIPE_B;
1111
1112 WARN(panel_pipe == pipe && locked,
1113 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1114 pipe_name(pipe));
ea0760cf
JB		 1115}
1116
b840d907
JB		 1117void assert_pipe(struct drm_i915_private *dev_priv,
1118 enum pipe pipe, bool state)
b24e7179
JB		 1119{
1120 int reg;
1121 u32 val;
63d7bbe9 1122 bool cur_state;
702e7a56
PZ		 1123 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1124 pipe);
b24e7179 1125
8e636784
DV		 1126 /* if we need the pipe A quirk it must be always on */
1127 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1128 state = true;
1129
b97186f0
PZ		 1130 if (!intel_display_power_enabled(dev_priv->dev,
1131 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1132 cur_state = false;
1133 } else {
1134 reg = PIPECONF(cpu_transcoder);
1135 val = I915_READ(reg);
1136 cur_state = !!(val & PIPECONF_ENABLE);
1137 }
1138
63d7bbe9
JB		 1139 WARN(cur_state != state,
1140 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1141 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1142}
1143
931872fc
CW		 1144static void assert_plane(struct drm_i915_private *dev_priv,
1145 enum plane plane, bool state)
b24e7179
JB		 1146{
1147 int reg;
1148 u32 val;
931872fc 1149 bool cur_state;
b24e7179
JB		 1150
1151 reg = DSPCNTR(plane);
1152 val = I915_READ(reg);
931872fc
CW		 1153 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1154 WARN(cur_state != state,
1155 "plane %c assertion failure (expected %s, current %s)\n",
1156 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1157}
1158
931872fc
CW		 1159#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1160#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1161
b24e7179
JB		 1162static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1163 enum pipe pipe)
1164{
1165 int reg, i;
1166 u32 val;
1167 int cur_pipe;
1168
19ec1358 1169 /* Planes are fixed to pipes on ILK+ */
da6ecc5d 1170 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
28c05794
AJ		 1171 reg = DSPCNTR(pipe);
1172 val = I915_READ(reg);
1173 WARN((val & DISPLAY_PLANE_ENABLE),
1174 "plane %c assertion failure, should be disabled but not\n",
1175 plane_name(pipe));
19ec1358 1176 return;
28c05794 1177 }
19ec1358 1178
b24e7179
JB		 1179 /* Need to check both planes against the pipe */
1180 for (i = 0; i < 2; i++) {
1181 reg = DSPCNTR(i);
1182 val = I915_READ(reg);
1183 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1184 DISPPLANE_SEL_PIPE_SHIFT;
1185 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1186 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1187 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1188 }
1189}
1190
19332d7a
JB		 1191static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1192 enum pipe pipe)
1193{
1194 int reg, i;
1195 u32 val;
1196
1197 if (!IS_VALLEYVIEW(dev_priv->dev))
1198 return;
1199
1200 /* Need to check both planes against the pipe */
1201 for (i = 0; i < dev_priv->num_plane; i++) {
1202 reg = SPCNTR(pipe, i);
1203 val = I915_READ(reg);
1204 WARN((val & SP_ENABLE),
06da8da2
VS		 1205 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1206 sprite_name(pipe, i), pipe_name(pipe));
19332d7a
JB		 1207 }
1208}
1209
92f2584a
JB		 1210static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1211{
1212 u32 val;
1213 bool enabled;
1214
9d82aa17
ED		 1215 if (HAS_PCH_LPT(dev_priv->dev)) {
1216 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1217 return;
1218 }
1219
92f2584a
JB		 1220 val = I915_READ(PCH_DREF_CONTROL);
1221 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1222 DREF_SUPERSPREAD_SOURCE_MASK));
1223 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1224}
1225
ab9412ba
DV		 1226static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1227 enum pipe pipe)
92f2584a
JB		 1228{
1229 int reg;
1230 u32 val;
1231 bool enabled;
1232
ab9412ba 1233 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1234 val = I915_READ(reg);
1235 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1236 WARN(enabled,
1237 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1238 pipe_name(pipe));
92f2584a
JB		 1239}
1240
4e634389
KP		 1241static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1242 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1243{
1244 if ((val & DP_PORT_EN) == 0)
1245 return false;
1246
1247 if (HAS_PCH_CPT(dev_priv->dev)) {
1248 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1249 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1250 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1251 return false;
1252 } else {
1253 if ((val & DP_PIPE_MASK) != (pipe << 30))
1254 return false;
1255 }
1256 return true;
1257}
1258
1519b995
KP		 1259static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1260 enum pipe pipe, u32 val)
1261{
dc0fa718 1262 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1263 return false;
1264
1265 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1266 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1267 return false;
1268 } else {
dc0fa718 1269 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1270 return false;
1271 }
1272 return true;
1273}
1274
1275static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1276 enum pipe pipe, u32 val)
1277{
1278 if ((val & LVDS_PORT_EN) == 0)
1279 return false;
1280
1281 if (HAS_PCH_CPT(dev_priv->dev)) {
1282 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1283 return false;
1284 } else {
1285 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1286 return false;
1287 }
1288 return true;
1289}
1290
1291static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1292 enum pipe pipe, u32 val)
1293{
1294 if ((val & ADPA_DAC_ENABLE) == 0)
1295 return false;
1296 if (HAS_PCH_CPT(dev_priv->dev)) {
1297 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1298 return false;
1299 } else {
1300 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1301 return false;
1302 }
1303 return true;
1304}
1305
291906f1 1306static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1307 enum pipe pipe, int reg, u32 port_sel)
291906f1 1308{
47a05eca 1309 u32 val = I915_READ(reg);
4e634389 1310 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1311 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1312 reg, pipe_name(pipe));
de9a35ab 1313
75c5da27
DV		 1314 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1315 && (val & DP_PIPEB_SELECT),
de9a35ab 1316 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1317}
1318
1319static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1320 enum pipe pipe, int reg)
1321{
47a05eca 1322 u32 val = I915_READ(reg);
b70ad586 1323 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1324 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1325 reg, pipe_name(pipe));
de9a35ab 1326
dc0fa718 1327 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1328 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1329 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1330}
1331
1332static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1333 enum pipe pipe)
1334{
1335 int reg;
1336 u32 val;
291906f1 1337
f0575e92
KP		 1338 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1339 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1340 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1341
1342 reg = PCH_ADPA;
1343 val = I915_READ(reg);
b70ad586 1344 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1345 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1346 pipe_name(pipe));
291906f1
JB		 1347
1348 reg = PCH_LVDS;
1349 val = I915_READ(reg);
b70ad586 1350 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1351 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1352 pipe_name(pipe));
291906f1 1353
e2debe91
PZ		 1354 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1355 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1356 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1357}
1358
63d7bbe9
JB		 1359/**
1360 * intel_enable_pll - enable a PLL
1361 * @dev_priv: i915 private structure
1362 * @pipe: pipe PLL to enable
1363 *
1364 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1365 * make sure the PLL reg is writable first though, since the panel write
1366 * protect mechanism may be enabled.
1367 *
1368 * Note! This is for pre-ILK only.
7434a255
TR		 1369 *
1370 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1371 */
1372static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1373{
1374 int reg;
1375 u32 val;
1376
58c6eaa2
DV		 1377 assert_pipe_disabled(dev_priv, pipe);
1378
63d7bbe9 1379 /* No really, not for ILK+ */
a0c4da24 1380 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1381
1382 /* PLL is protected by panel, make sure we can write it */
1383 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1384 assert_panel_unlocked(dev_priv, pipe);
1385
1386 reg = DPLL(pipe);
1387 val = I915_READ(reg);
1388 val |= DPLL_VCO_ENABLE;
1389
1390 /* We do this three times for luck */
1391 I915_WRITE(reg, val);
1392 POSTING_READ(reg);
1393 udelay(150); /* wait for warmup */
1394 I915_WRITE(reg, val);
1395 POSTING_READ(reg);
1396 udelay(150); /* wait for warmup */
1397 I915_WRITE(reg, val);
1398 POSTING_READ(reg);
1399 udelay(150); /* wait for warmup */
1400}
1401
1402/**
1403 * intel_disable_pll - disable a PLL
1404 * @dev_priv: i915 private structure
1405 * @pipe: pipe PLL to disable
1406 *
1407 * Disable the PLL for @pipe, making sure the pipe is off first.
1408 *
1409 * Note! This is for pre-ILK only.
1410 */
1411static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1412{
1413 int reg;
1414 u32 val;
1415
1416 /* Don't disable pipe A or pipe A PLLs if needed */
1417 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1418 return;
1419
1420 /* Make sure the pipe isn't still relying on us */
1421 assert_pipe_disabled(dev_priv, pipe);
1422
1423 reg = DPLL(pipe);
1424 val = I915_READ(reg);
1425 val &= ~DPLL_VCO_ENABLE;
1426 I915_WRITE(reg, val);
1427 POSTING_READ(reg);
1428}
1429
89b667f8
JB		 1430void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1431{
1432 u32 port_mask;
1433
1434 if (!port)
1435 port_mask = DPLL_PORTB_READY_MASK;
1436 else
1437 port_mask = DPLL_PORTC_READY_MASK;
1438
1439 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1440 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1441 'B' + port, I915_READ(DPLL(0)));
1442}
1443
92f2584a 1444/**
b6b4e185 1445 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1446 * @dev_priv: i915 private structure
1447 * @pipe: pipe PLL to enable
1448 *
1449 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1450 * drives the transcoder clock.
1451 */
b6b4e185 1452static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1453{
ee7b9f93 1454 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1455 struct intel_pch_pll *pll;
92f2584a
JB		 1456 int reg;
1457 u32 val;
1458
48da64a8 1459 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1460 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1461 pll = intel_crtc->pch_pll;
1462 if (pll == NULL)
1463 return;
1464
1465 if (WARN_ON(pll->refcount == 0))
1466 return;
ee7b9f93
JB		 1467
1468 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1469 pll->pll_reg, pll->active, pll->on,
1470 intel_crtc->base.base.id);
92f2584a
JB		 1471
1472 /* PCH refclock must be enabled first */
1473 assert_pch_refclk_enabled(dev_priv);
1474
ee7b9f93 1475 if (pll->active++ && pll->on) {
92b27b08 1476 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1477 return;
1478 }
1479
1480 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1481
1482 reg = pll->pll_reg;
92f2584a
JB		 1483 val = I915_READ(reg);
1484 val |= DPLL_VCO_ENABLE;
1485 I915_WRITE(reg, val);
1486 POSTING_READ(reg);
1487 udelay(200);
ee7b9f93
JB		 1488
1489 pll->on = true;
92f2584a
JB		 1490}
1491
ee7b9f93 1492static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1493{
ee7b9f93
JB		 1494 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1495 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1496 int reg;
ee7b9f93 1497 u32 val;
4c609cb8 1498
92f2584a
JB		 1499 /* PCH only available on ILK+ */
1500 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1501 if (pll == NULL)
1502 return;
92f2584a 1503
48da64a8
CW		 1504 if (WARN_ON(pll->refcount == 0))
1505 return;
7a419866 1506
ee7b9f93
JB		 1507 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1508 pll->pll_reg, pll->active, pll->on,
1509 intel_crtc->base.base.id);
7a419866 1510
48da64a8 1511 if (WARN_ON(pll->active == 0)) {
92b27b08 1512 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1513 return;
1514 }
1515
ee7b9f93 1516 if (--pll->active) {
92b27b08 1517 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1518 return;
ee7b9f93
JB		 1519 }
1520
1521 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1522
1523 /* Make sure transcoder isn't still depending on us */
ab9412ba 1524 assert_pch_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1525
ee7b9f93 1526 reg = pll->pll_reg;
92f2584a
JB		 1527 val = I915_READ(reg);
1528 val &= ~DPLL_VCO_ENABLE;
1529 I915_WRITE(reg, val);
1530 POSTING_READ(reg);
1531 udelay(200);
ee7b9f93
JB		 1532
1533 pll->on = false;
92f2584a
JB		 1534}
1535
b8a4f404
PZ		 1536static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1537 enum pipe pipe)
040484af 1538{
23670b32 1539 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1540 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1541 uint32_t reg, val, pipeconf_val;
040484af
JB		 1542
1543 /* PCH only available on ILK+ */
1544 BUG_ON(dev_priv->info->gen < 5);
1545
1546 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1547 assert_pch_pll_enabled(dev_priv,
1548 to_intel_crtc(crtc)->pch_pll,
1549 to_intel_crtc(crtc));
040484af
JB		 1550
1551 /* FDI must be feeding us bits for PCH ports */
1552 assert_fdi_tx_enabled(dev_priv, pipe);
1553 assert_fdi_rx_enabled(dev_priv, pipe);
1554
23670b32
DV		 1555 if (HAS_PCH_CPT(dev)) {
1556 /* Workaround: Set the timing override bit before enabling the
1557 * pch transcoder. */
1558 reg = TRANS_CHICKEN2(pipe);
1559 val = I915_READ(reg);
1560 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1561 I915_WRITE(reg, val);
59c859d6 1562 }
23670b32 1563
ab9412ba 1564 reg = PCH_TRANSCONF(pipe);
040484af 1565 val = I915_READ(reg);
5f7f726d 1566 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1567
1568 if (HAS_PCH_IBX(dev_priv->dev)) {
1569 /*
1570 * make the BPC in transcoder be consistent with
1571 * that in pipeconf reg.
1572 */
dfd07d72
DV		 1573 val &= ~PIPECONF_BPC_MASK;
1574 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1575 }
5f7f726d
PZ		 1576
1577 val &= ~TRANS_INTERLACE_MASK;
1578 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1579 if (HAS_PCH_IBX(dev_priv->dev) &&
1580 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1581 val |= TRANS_LEGACY_INTERLACED_ILK;
1582 else
1583 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1584 else
1585 val |= TRANS_PROGRESSIVE;
1586
040484af
JB		 1587 I915_WRITE(reg, val | TRANS_ENABLE);
1588 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1589 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1590}
1591
8fb033d7 1592static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1593 enum transcoder cpu_transcoder)
040484af 1594{
8fb033d7 1595 u32 val, pipeconf_val;
8fb033d7
PZ		 1596
1597 /* PCH only available on ILK+ */
1598 BUG_ON(dev_priv->info->gen < 5);
1599
8fb033d7 1600 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1601 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1602 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1603
223a6fdf
PZ		 1604 /* Workaround: set timing override bit. */
1605 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1606 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1607 I915_WRITE(_TRANSA_CHICKEN2, val);
1608
25f3ef11 1609 val = TRANS_ENABLE;
937bb610 1610 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1611
9a76b1c6
PZ		 1612 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1613 PIPECONF_INTERLACED_ILK)
a35f2679 1614 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1615 else
1616 val |= TRANS_PROGRESSIVE;
1617
ab9412ba
DV		 1618 I915_WRITE(LPT_TRANSCONF, val);
1619 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1620 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1621}
1622
b8a4f404
PZ		 1623static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1624 enum pipe pipe)
040484af 1625{
23670b32
DV		 1626 struct drm_device *dev = dev_priv->dev;
1627 uint32_t reg, val;
040484af
JB		 1628
1629 /* FDI relies on the transcoder */
1630 assert_fdi_tx_disabled(dev_priv, pipe);
1631 assert_fdi_rx_disabled(dev_priv, pipe);
1632
291906f1
JB		 1633 /* Ports must be off as well */
1634 assert_pch_ports_disabled(dev_priv, pipe);
1635
ab9412ba 1636 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1637 val = I915_READ(reg);
1638 val &= ~TRANS_ENABLE;
1639 I915_WRITE(reg, val);
1640 /* wait for PCH transcoder off, transcoder state */
1641 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1642 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1643
1644 if (!HAS_PCH_IBX(dev)) {
1645 /* Workaround: Clear the timing override chicken bit again. */
1646 reg = TRANS_CHICKEN2(pipe);
1647 val = I915_READ(reg);
1648 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1649 I915_WRITE(reg, val);
1650 }
040484af
JB		 1651}
1652
ab4d966c 1653static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1654{
8fb033d7
PZ		 1655 u32 val;
1656
ab9412ba 1657 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1658 val &= ~TRANS_ENABLE;
ab9412ba 1659 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1660 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1661 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1662 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1663
1664 /* Workaround: clear timing override bit. */
1665 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1666 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1667 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1668}
1669
b24e7179 1670/**
309cfea8 1671 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1672 * @dev_priv: i915 private structure
1673 * @pipe: pipe to enable
040484af 1674 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1675 *
1676 * Enable @pipe, making sure that various hardware specific requirements
1677 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1678 *
1679 * @pipe should be %PIPE_A or %PIPE_B.
1680 *
1681 * Will wait until the pipe is actually running (i.e. first vblank) before
1682 * returning.
1683 */
040484af
JB		 1684static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1685 bool pch_port)
b24e7179 1686{
702e7a56
PZ		 1687 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1688 pipe);
1a240d4d 1689 enum pipe pch_transcoder;
b24e7179
JB		 1690 int reg;
1691 u32 val;
1692
58c6eaa2
DV		 1693 assert_planes_disabled(dev_priv, pipe);
1694 assert_sprites_disabled(dev_priv, pipe);
1695
681e5811 1696 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1697 pch_transcoder = TRANSCODER_A;
1698 else
1699 pch_transcoder = pipe;
1700
b24e7179
JB		 1701 /*
1702 * A pipe without a PLL won't actually be able to drive bits from
1703 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1704 * need the check.
1705 */
1706 if (!HAS_PCH_SPLIT(dev_priv->dev))
1707 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1708 else {
1709 if (pch_port) {
1710 /* if driving the PCH, we need FDI enabled */
cc391bbb 1711 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1712 assert_fdi_tx_pll_enabled(dev_priv,
1713 (enum pipe) cpu_transcoder);
040484af
JB		 1714 }
1715 /* FIXME: assert CPU port conditions for SNB+ */
1716 }
b24e7179 1717
702e7a56 1718 reg = PIPECONF(cpu_transcoder);
b24e7179 1719 val = I915_READ(reg);
00d70b15
CW		 1720 if (val & PIPECONF_ENABLE)
1721 return;
1722
1723 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1724 intel_wait_for_vblank(dev_priv->dev, pipe);
1725}
1726
1727/**
309cfea8 1728 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1729 * @dev_priv: i915 private structure
1730 * @pipe: pipe to disable
1731 *
1732 * Disable @pipe, making sure that various hardware specific requirements
1733 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1734 *
1735 * @pipe should be %PIPE_A or %PIPE_B.
1736 *
1737 * Will wait until the pipe has shut down before returning.
1738 */
1739static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1740 enum pipe pipe)
1741{
702e7a56
PZ		 1742 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1743 pipe);
b24e7179
JB		 1744 int reg;
1745 u32 val;
1746
1747 /*
1748 * Make sure planes won't keep trying to pump pixels to us,
1749 * or we might hang the display.
1750 */
1751 assert_planes_disabled(dev_priv, pipe);
19332d7a 1752 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1753
1754 /* Don't disable pipe A or pipe A PLLs if needed */
1755 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1756 return;
1757
702e7a56 1758 reg = PIPECONF(cpu_transcoder);
b24e7179 1759 val = I915_READ(reg);
00d70b15
CW		 1760 if ((val & PIPECONF_ENABLE) == 0)
1761 return;
1762
1763 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1764 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1765}
1766
d74362c9
KP		 1767/*
1768 * Plane regs are double buffered, going from enabled->disabled needs a
1769 * trigger in order to latch. The display address reg provides this.
1770 */
6f1d69b0 1771void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1772 enum plane plane)
1773{
14f86147
DL		 1774 if (dev_priv->info->gen >= 4)
1775 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1776 else
1777 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1778}
1779
b24e7179
JB		 1780/**
1781 * intel_enable_plane - enable a display plane on a given pipe
1782 * @dev_priv: i915 private structure
1783 * @plane: plane to enable
1784 * @pipe: pipe being fed
1785 *
1786 * Enable @plane on @pipe, making sure that @pipe is running first.
1787 */
1788static void intel_enable_plane(struct drm_i915_private *dev_priv,
1789 enum plane plane, enum pipe pipe)
1790{
1791 int reg;
1792 u32 val;
1793
1794 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1795 assert_pipe_enabled(dev_priv, pipe);
1796
1797 reg = DSPCNTR(plane);
1798 val = I915_READ(reg);
00d70b15
CW		 1799 if (val & DISPLAY_PLANE_ENABLE)
1800 return;
1801
1802 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1803 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1804 intel_wait_for_vblank(dev_priv->dev, pipe);
1805}
1806
b24e7179
JB		 1807/**
1808 * intel_disable_plane - disable a display plane
1809 * @dev_priv: i915 private structure
1810 * @plane: plane to disable
1811 * @pipe: pipe consuming the data
1812 *
1813 * Disable @plane; should be an independent operation.
1814 */
1815static void intel_disable_plane(struct drm_i915_private *dev_priv,
1816 enum plane plane, enum pipe pipe)
1817{
1818 int reg;
1819 u32 val;
1820
1821 reg = DSPCNTR(plane);
1822 val = I915_READ(reg);
00d70b15
CW		 1823 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1824 return;
1825
1826 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1827 intel_flush_display_plane(dev_priv, plane);
1828 intel_wait_for_vblank(dev_priv->dev, pipe);
1829}
1830
693db184
CW		 1831static bool need_vtd_wa(struct drm_device *dev)
1832{
1833#ifdef CONFIG_INTEL_IOMMU
1834 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1835 return true;
1836#endif
1837 return false;
1838}
1839
127bd2ac 1840int
48b956c5 1841intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1842 struct drm_i915_gem_object *obj,
919926ae 1843 struct intel_ring_buffer *pipelined)
6b95a207 1844{
ce453d81 1845 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1846 u32 alignment;
1847 int ret;
1848
05394f39 1849 switch (obj->tiling_mode) {
6b95a207 1850 case I915_TILING_NONE:
534843da
CW		 1851 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1852 alignment = 128 * 1024;
a6c45cf0 1853 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1854 alignment = 4 * 1024;
1855 else
1856 alignment = 64 * 1024;
6b95a207
KH		 1857 break;
1858 case I915_TILING_X:
1859 /* pin() will align the object as required by fence */
1860 alignment = 0;
1861 break;
1862 case I915_TILING_Y:
8bb6e959
DV		 1863 /* Despite that we check this in framebuffer_init userspace can
1864 * screw us over and change the tiling after the fact. Only
1865 * pinned buffers can't change their tiling. */
1866 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1867 return -EINVAL;
1868 default:
1869 BUG();
1870 }
1871
693db184
CW		 1872 /* Note that the w/a also requires 64 PTE of padding following the
1873 * bo. We currently fill all unused PTE with the shadow page and so
1874 * we should always have valid PTE following the scanout preventing
1875 * the VT-d warning.
1876 */
1877 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1878 alignment = 256 * 1024;
1879
ce453d81 1880 dev_priv->mm.interruptible = false;
2da3b9b9 1881 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1882 if (ret)
ce453d81 1883 goto err_interruptible;
6b95a207
KH		 1884
1885 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1886 * fence, whereas 965+ only requires a fence if using
1887 * framebuffer compression. For simplicity, we always install
1888 * a fence as the cost is not that onerous.
1889 */
06d98131 1890 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1891 if (ret)
1892 goto err_unpin;
1690e1eb 1893
9a5a53b3 1894 i915_gem_object_pin_fence(obj);
6b95a207 1895
ce453d81 1896 dev_priv->mm.interruptible = true;
6b95a207 1897 return 0;
48b956c5
CW		 1898
1899err_unpin:
1900 i915_gem_object_unpin(obj);
ce453d81
CW		 1901err_interruptible:
1902 dev_priv->mm.interruptible = true;
48b956c5 1903 return ret;
6b95a207
KH		 1904}
1905
1690e1eb
CW		 1906void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1907{
1908 i915_gem_object_unpin_fence(obj);
1909 i915_gem_object_unpin(obj);
1910}
1911
c2c75131
DV		 1912/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1913 * is assumed to be a power-of-two. */
bc752862
CW		 1914unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1915 unsigned int tiling_mode,
1916 unsigned int cpp,
1917 unsigned int pitch)
c2c75131 1918{
bc752862
CW		 1919 if (tiling_mode != I915_TILING_NONE) {
1920 unsigned int tile_rows, tiles;
c2c75131 1921
bc752862
CW		 1922 tile_rows = *y / 8;
1923 *y %= 8;
c2c75131 1924
bc752862
CW		 1925 tiles = *x / (512/cpp);
1926 *x %= 512/cpp;
1927
1928 return tile_rows * pitch * 8 + tiles * 4096;
1929 } else {
1930 unsigned int offset;
1931
1932 offset = *y * pitch + *x * cpp;
1933 *y = 0;
1934 *x = (offset & 4095) / cpp;
1935 return offset & -4096;
1936 }
c2c75131
DV		 1937}
1938
17638cd6
JB		 1939static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1940 int x, int y)
81255565
JB		 1941{
1942 struct drm_device *dev = crtc->dev;
1943 struct drm_i915_private *dev_priv = dev->dev_private;
1944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1945 struct intel_framebuffer *intel_fb;
05394f39 1946 struct drm_i915_gem_object *obj;
81255565 1947 int plane = intel_crtc->plane;
e506a0c6 1948 unsigned long linear_offset;
81255565 1949 u32 dspcntr;
5eddb70b 1950 u32 reg;
81255565
JB		 1951
1952 switch (plane) {
1953 case 0:
1954 case 1:
1955 break;
1956 default:
84f44ce7 1957 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 1958 return -EINVAL;
1959 }
1960
1961 intel_fb = to_intel_framebuffer(fb);
1962 obj = intel_fb->obj;
81255565 1963
5eddb70b
CW		 1964 reg = DSPCNTR(plane);
1965 dspcntr = I915_READ(reg);
81255565
JB		 1966 /* Mask out pixel format bits in case we change it */
1967 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 1968 switch (fb->pixel_format) {
1969 case DRM_FORMAT_C8:
81255565
JB		 1970 dspcntr |= DISPPLANE_8BPP;
1971 break;
57779d06
VS		 1972 case DRM_FORMAT_XRGB1555:
1973 case DRM_FORMAT_ARGB1555:
1974 dspcntr |= DISPPLANE_BGRX555;
81255565 1975 break;
57779d06
VS		 1976 case DRM_FORMAT_RGB565:
1977 dspcntr |= DISPPLANE_BGRX565;
1978 break;
1979 case DRM_FORMAT_XRGB8888:
1980 case DRM_FORMAT_ARGB8888:
1981 dspcntr |= DISPPLANE_BGRX888;
1982 break;
1983 case DRM_FORMAT_XBGR8888:
1984 case DRM_FORMAT_ABGR8888:
1985 dspcntr |= DISPPLANE_RGBX888;
1986 break;
1987 case DRM_FORMAT_XRGB2101010:
1988 case DRM_FORMAT_ARGB2101010:
1989 dspcntr |= DISPPLANE_BGRX101010;
1990 break;
1991 case DRM_FORMAT_XBGR2101010:
1992 case DRM_FORMAT_ABGR2101010:
1993 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 1994 break;
1995 default:
baba133a 1996 BUG();
81255565 1997 }
57779d06 1998
a6c45cf0 1999 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2000 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2001 dspcntr |= DISPPLANE_TILED;
2002 else
2003 dspcntr &= ~DISPPLANE_TILED;
2004 }
2005
5eddb70b 2006 I915_WRITE(reg, dspcntr);
81255565 2007
e506a0c6 2008 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2009
c2c75131
DV		 2010 if (INTEL_INFO(dev)->gen >= 4) {
2011 intel_crtc->dspaddr_offset =
bc752862
CW		 2012 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2013 fb->bits_per_pixel / 8,
2014 fb->pitches[0]);
c2c75131
DV		 2015 linear_offset -= intel_crtc->dspaddr_offset;
2016 } else {
e506a0c6 2017 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2018 }
e506a0c6
DV		 2019
2020 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2021 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2022 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2023 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2024 I915_MODIFY_DISPBASE(DSPSURF(plane),
2025 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2026 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2027 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2028 } else
e506a0c6 2029 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2030 POSTING_READ(reg);
81255565 2031
17638cd6
JB		 2032 return 0;
2033}
2034
2035static int ironlake_update_plane(struct drm_crtc *crtc,
2036 struct drm_framebuffer *fb, int x, int y)
2037{
2038 struct drm_device *dev = crtc->dev;
2039 struct drm_i915_private *dev_priv = dev->dev_private;
2040 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2041 struct intel_framebuffer *intel_fb;
2042 struct drm_i915_gem_object *obj;
2043 int plane = intel_crtc->plane;
e506a0c6 2044 unsigned long linear_offset;
17638cd6
JB		 2045 u32 dspcntr;
2046 u32 reg;
2047
2048 switch (plane) {
2049 case 0:
2050 case 1:
27f8227b 2051 case 2:
17638cd6
JB		 2052 break;
2053 default:
84f44ce7 2054 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2055 return -EINVAL;
2056 }
2057
2058 intel_fb = to_intel_framebuffer(fb);
2059 obj = intel_fb->obj;
2060
2061 reg = DSPCNTR(plane);
2062 dspcntr = I915_READ(reg);
2063 /* Mask out pixel format bits in case we change it */
2064 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2065 switch (fb->pixel_format) {
2066 case DRM_FORMAT_C8:
17638cd6
JB		 2067 dspcntr |= DISPPLANE_8BPP;
2068 break;
57779d06
VS		 2069 case DRM_FORMAT_RGB565:
2070 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2071 break;
57779d06
VS		 2072 case DRM_FORMAT_XRGB8888:
2073 case DRM_FORMAT_ARGB8888:
2074 dspcntr |= DISPPLANE_BGRX888;
2075 break;
2076 case DRM_FORMAT_XBGR8888:
2077 case DRM_FORMAT_ABGR8888:
2078 dspcntr |= DISPPLANE_RGBX888;
2079 break;
2080 case DRM_FORMAT_XRGB2101010:
2081 case DRM_FORMAT_ARGB2101010:
2082 dspcntr |= DISPPLANE_BGRX101010;
2083 break;
2084 case DRM_FORMAT_XBGR2101010:
2085 case DRM_FORMAT_ABGR2101010:
2086 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2087 break;
2088 default:
baba133a 2089 BUG();
17638cd6
JB		 2090 }
2091
2092 if (obj->tiling_mode != I915_TILING_NONE)
2093 dspcntr |= DISPPLANE_TILED;
2094 else
2095 dspcntr &= ~DISPPLANE_TILED;
2096
2097 /* must disable */
2098 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2099
2100 I915_WRITE(reg, dspcntr);
2101
e506a0c6 2102 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2103 intel_crtc->dspaddr_offset =
bc752862
CW		 2104 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2105 fb->bits_per_pixel / 8,
2106 fb->pitches[0]);
c2c75131 2107 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2108
e506a0c6
DV		 2109 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2110 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2111 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2112 I915_MODIFY_DISPBASE(DSPSURF(plane),
2113 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2114 if (IS_HASWELL(dev)) {
2115 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2116 } else {
2117 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2118 I915_WRITE(DSPLINOFF(plane), linear_offset);
2119 }
17638cd6
JB		 2120 POSTING_READ(reg);
2121
2122 return 0;
2123}
2124
2125/* Assume fb object is pinned & idle & fenced and just update base pointers */
2126static int
2127intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2128 int x, int y, enum mode_set_atomic state)
2129{
2130 struct drm_device *dev = crtc->dev;
2131 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2132
6b8e6ed0
CW		 2133 if (dev_priv->display.disable_fbc)
2134 dev_priv->display.disable_fbc(dev);
3dec0095 2135 intel_increase_pllclock(crtc);
81255565 2136
6b8e6ed0 2137 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2138}
2139
96a02917
VS		 2140void intel_display_handle_reset(struct drm_device *dev)
2141{
2142 struct drm_i915_private *dev_priv = dev->dev_private;
2143 struct drm_crtc *crtc;
2144
2145 /*
2146 * Flips in the rings have been nuked by the reset,
2147 * so complete all pending flips so that user space
2148 * will get its events and not get stuck.
2149 *
2150 * Also update the base address of all primary
2151 * planes to the the last fb to make sure we're
2152 * showing the correct fb after a reset.
2153 *
2154 * Need to make two loops over the crtcs so that we
2155 * don't try to grab a crtc mutex before the
2156 * pending_flip_queue really got woken up.
2157 */
2158
2159 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2160 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2161 enum plane plane = intel_crtc->plane;
2162
2163 intel_prepare_page_flip(dev, plane);
2164 intel_finish_page_flip_plane(dev, plane);
2165 }
2166
2167 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2168 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2169
2170 mutex_lock(&crtc->mutex);
2171 if (intel_crtc->active)
2172 dev_priv->display.update_plane(crtc, crtc->fb,
2173 crtc->x, crtc->y);
2174 mutex_unlock(&crtc->mutex);
2175 }
2176}
2177
14667a4b
CW		 2178static int
2179intel_finish_fb(struct drm_framebuffer *old_fb)
2180{
2181 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2182 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2183 bool was_interruptible = dev_priv->mm.interruptible;
2184 int ret;
2185
14667a4b
CW		 2186 /* Big Hammer, we also need to ensure that any pending
2187 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2188 * current scanout is retired before unpinning the old
2189 * framebuffer.
2190 *
2191 * This should only fail upon a hung GPU, in which case we
2192 * can safely continue.
2193 */
2194 dev_priv->mm.interruptible = false;
2195 ret = i915_gem_object_finish_gpu(obj);
2196 dev_priv->mm.interruptible = was_interruptible;
2197
2198 return ret;
2199}
2200
198598d0
VS		 2201static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2202{
2203 struct drm_device *dev = crtc->dev;
2204 struct drm_i915_master_private *master_priv;
2205 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2206
2207 if (!dev->primary->master)
2208 return;
2209
2210 master_priv = dev->primary->master->driver_priv;
2211 if (!master_priv->sarea_priv)
2212 return;
2213
2214 switch (intel_crtc->pipe) {
2215 case 0:
2216 master_priv->sarea_priv->pipeA_x = x;
2217 master_priv->sarea_priv->pipeA_y = y;
2218 break;
2219 case 1:
2220 master_priv->sarea_priv->pipeB_x = x;
2221 master_priv->sarea_priv->pipeB_y = y;
2222 break;
2223 default:
2224 break;
2225 }
2226}
2227
5c3b82e2 2228static int
3c4fdcfb 2229intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2230 struct drm_framebuffer *fb)
79e53945
JB		 2231{
2232 struct drm_device *dev = crtc->dev;
6b8e6ed0 2233 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2234 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2235 struct drm_framebuffer *old_fb;
5c3b82e2 2236 int ret;
79e53945
JB		 2237
2238 /* no fb bound */
94352cf9 2239 if (!fb) {
a5071c2f 2240 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2241 return 0;
2242 }
2243
7eb552ae 2244 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2245 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2246 plane_name(intel_crtc->plane),
2247 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2248 return -EINVAL;
79e53945
JB		 2249 }
2250
5c3b82e2 2251 mutex_lock(&dev->struct_mutex);
265db958 2252 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2253 to_intel_framebuffer(fb)->obj,
919926ae 2254 NULL);
5c3b82e2
CW		 2255 if (ret != 0) {
2256 mutex_unlock(&dev->struct_mutex);
a5071c2f 2257 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2258 return ret;
2259 }
79e53945 2260
94352cf9 2261 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2262 if (ret) {
94352cf9 2263 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2264 mutex_unlock(&dev->struct_mutex);
a5071c2f 2265 DRM_ERROR("failed to update base address\n");
4e6cfefc 2266 return ret;
79e53945 2267 }
3c4fdcfb 2268
94352cf9
DV		 2269 old_fb = crtc->fb;
2270 crtc->fb = fb;
6c4c86f5
DV		 2271 crtc->x = x;
2272 crtc->y = y;
94352cf9 2273
b7f1de28 2274 if (old_fb) {
d7697eea
DV		 2275 if (intel_crtc->active && old_fb != fb)
2276 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2277 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2278 }
652c393a 2279
6b8e6ed0 2280 intel_update_fbc(dev);
5c3b82e2 2281 mutex_unlock(&dev->struct_mutex);
79e53945 2282
198598d0 2283 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2284
2285 return 0;
79e53945
JB		 2286}
2287
5e84e1a4
ZW		 2288static void intel_fdi_normal_train(struct drm_crtc *crtc)
2289{
2290 struct drm_device *dev = crtc->dev;
2291 struct drm_i915_private *dev_priv = dev->dev_private;
2292 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2293 int pipe = intel_crtc->pipe;
2294 u32 reg, temp;
2295
2296 /* enable normal train */
2297 reg = FDI_TX_CTL(pipe);
2298 temp = I915_READ(reg);
61e499bf 2299 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2300 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2301 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2302 } else {
2303 temp &= ~FDI_LINK_TRAIN_NONE;
2304 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2305 }
5e84e1a4
ZW		 2306 I915_WRITE(reg, temp);
2307
2308 reg = FDI_RX_CTL(pipe);
2309 temp = I915_READ(reg);
2310 if (HAS_PCH_CPT(dev)) {
2311 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2312 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2313 } else {
2314 temp &= ~FDI_LINK_TRAIN_NONE;
2315 temp |= FDI_LINK_TRAIN_NONE;
2316 }
2317 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2318
2319 /* wait one idle pattern time */
2320 POSTING_READ(reg);
2321 udelay(1000);
357555c0
JB		 2322
2323 /* IVB wants error correction enabled */
2324 if (IS_IVYBRIDGE(dev))
2325 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2326 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2327}
2328
1e833f40
DV		 2329static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2330{
2331 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2332}
2333
01a415fd
DV		 2334static void ivb_modeset_global_resources(struct drm_device *dev)
2335{
2336 struct drm_i915_private *dev_priv = dev->dev_private;
2337 struct intel_crtc *pipe_B_crtc =
2338 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2339 struct intel_crtc *pipe_C_crtc =
2340 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2341 uint32_t temp;
2342
1e833f40
DV		 2343 /*
2344 * When everything is off disable fdi C so that we could enable fdi B
2345 * with all lanes. Note that we don't care about enabled pipes without
2346 * an enabled pch encoder.
2347 */
2348 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2349 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2350 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2351 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2352
2353 temp = I915_READ(SOUTH_CHICKEN1);
2354 temp &= ~FDI_BC_BIFURCATION_SELECT;
2355 DRM_DEBUG_KMS("disabling fdi C rx\n");
2356 I915_WRITE(SOUTH_CHICKEN1, temp);
2357 }
2358}
2359
8db9d77b
ZW		 2360/* The FDI link training functions for ILK/Ibexpeak. */
2361static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2362{
2363 struct drm_device *dev = crtc->dev;
2364 struct drm_i915_private *dev_priv = dev->dev_private;
2365 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2366 int pipe = intel_crtc->pipe;
0fc932b8 2367 int plane = intel_crtc->plane;
5eddb70b 2368 u32 reg, temp, tries;
8db9d77b 2369
0fc932b8
JB		 2370 /* FDI needs bits from pipe & plane first */
2371 assert_pipe_enabled(dev_priv, pipe);
2372 assert_plane_enabled(dev_priv, plane);
2373
e1a44743
AJ		 2374 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2375 for train result */
5eddb70b
CW		 2376 reg = FDI_RX_IMR(pipe);
2377 temp = I915_READ(reg);
e1a44743
AJ		 2378 temp &= ~FDI_RX_SYMBOL_LOCK;
2379 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2380 I915_WRITE(reg, temp);
2381 I915_READ(reg);
e1a44743
AJ		 2382 udelay(150);
2383
8db9d77b 2384 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2385 reg = FDI_TX_CTL(pipe);
2386 temp = I915_READ(reg);
627eb5a3
DV		 2387 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2388 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2389 temp &= ~FDI_LINK_TRAIN_NONE;
2390 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2391 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2392
5eddb70b
CW		 2393 reg = FDI_RX_CTL(pipe);
2394 temp = I915_READ(reg);
8db9d77b
ZW		 2395 temp &= ~FDI_LINK_TRAIN_NONE;
2396 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2397 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2398
2399 POSTING_READ(reg);
8db9d77b
ZW		 2400 udelay(150);
2401
5b2adf89 2402 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2403 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2404 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2405 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2406
5eddb70b 2407 reg = FDI_RX_IIR(pipe);
e1a44743 2408 for (tries = 0; tries < 5; tries++) {
5eddb70b 2409 temp = I915_READ(reg);
8db9d77b
ZW		 2410 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2411
2412 if ((temp & FDI_RX_BIT_LOCK)) {
2413 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2414 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2415 break;
2416 }
8db9d77b 2417 }
e1a44743 2418 if (tries == 5)
5eddb70b 2419 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2420
2421 /* Train 2 */
5eddb70b
CW		 2422 reg = FDI_TX_CTL(pipe);
2423 temp = I915_READ(reg);
8db9d77b
ZW		 2424 temp &= ~FDI_LINK_TRAIN_NONE;
2425 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2426 I915_WRITE(reg, temp);
8db9d77b 2427
5eddb70b
CW		 2428 reg = FDI_RX_CTL(pipe);
2429 temp = I915_READ(reg);
8db9d77b
ZW		 2430 temp &= ~FDI_LINK_TRAIN_NONE;
2431 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2432 I915_WRITE(reg, temp);
8db9d77b 2433
5eddb70b
CW		 2434 POSTING_READ(reg);
2435 udelay(150);
8db9d77b 2436
5eddb70b 2437 reg = FDI_RX_IIR(pipe);
e1a44743 2438 for (tries = 0; tries < 5; tries++) {
5eddb70b 2439 temp = I915_READ(reg);
8db9d77b
ZW		 2440 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2441
2442 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2443 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2444 DRM_DEBUG_KMS("FDI train 2 done.\n");
2445 break;
2446 }
8db9d77b 2447 }
e1a44743 2448 if (tries == 5)
5eddb70b 2449 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2450
2451 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2452
8db9d77b
ZW		 2453}
2454
0206e353 2455static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2456 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2457 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2458 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2459 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2460};
2461
2462/* The FDI link training functions for SNB/Cougarpoint. */
2463static void gen6_fdi_link_train(struct drm_crtc *crtc)
2464{
2465 struct drm_device *dev = crtc->dev;
2466 struct drm_i915_private *dev_priv = dev->dev_private;
2467 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2468 int pipe = intel_crtc->pipe;
fa37d39e 2469 u32 reg, temp, i, retry;
8db9d77b 2470
e1a44743
AJ		 2471 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2472 for train result */
5eddb70b
CW		 2473 reg = FDI_RX_IMR(pipe);
2474 temp = I915_READ(reg);
e1a44743
AJ		 2475 temp &= ~FDI_RX_SYMBOL_LOCK;
2476 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2477 I915_WRITE(reg, temp);
2478
2479 POSTING_READ(reg);
e1a44743
AJ		 2480 udelay(150);
2481
8db9d77b 2482 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2483 reg = FDI_TX_CTL(pipe);
2484 temp = I915_READ(reg);
627eb5a3
DV		 2485 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2486 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2487 temp &= ~FDI_LINK_TRAIN_NONE;
2488 temp |= FDI_LINK_TRAIN_PATTERN_1;
2489 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2490 /* SNB-B */
2491 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2492 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2493
d74cf324
DV		 2494 I915_WRITE(FDI_RX_MISC(pipe),
2495 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2496
5eddb70b
CW		 2497 reg = FDI_RX_CTL(pipe);
2498 temp = I915_READ(reg);
8db9d77b
ZW		 2499 if (HAS_PCH_CPT(dev)) {
2500 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2501 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2502 } else {
2503 temp &= ~FDI_LINK_TRAIN_NONE;
2504 temp |= FDI_LINK_TRAIN_PATTERN_1;
2505 }
5eddb70b
CW		 2506 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2507
2508 POSTING_READ(reg);
8db9d77b
ZW		 2509 udelay(150);
2510
0206e353 2511 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2512 reg = FDI_TX_CTL(pipe);
2513 temp = I915_READ(reg);
8db9d77b
ZW		 2514 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2515 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2516 I915_WRITE(reg, temp);
2517
2518 POSTING_READ(reg);
8db9d77b
ZW		 2519 udelay(500);
2520
fa37d39e
SP		 2521 for (retry = 0; retry < 5; retry++) {
2522 reg = FDI_RX_IIR(pipe);
2523 temp = I915_READ(reg);
2524 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2525 if (temp & FDI_RX_BIT_LOCK) {
2526 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2527 DRM_DEBUG_KMS("FDI train 1 done.\n");
2528 break;
2529 }
2530 udelay(50);
8db9d77b 2531 }
fa37d39e
SP		 2532 if (retry < 5)
2533 break;
8db9d77b
ZW		 2534 }
2535 if (i == 4)
5eddb70b 2536 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2537
2538 /* Train 2 */
5eddb70b
CW		 2539 reg = FDI_TX_CTL(pipe);
2540 temp = I915_READ(reg);
8db9d77b
ZW		 2541 temp &= ~FDI_LINK_TRAIN_NONE;
2542 temp |= FDI_LINK_TRAIN_PATTERN_2;
2543 if (IS_GEN6(dev)) {
2544 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2545 /* SNB-B */
2546 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2547 }
5eddb70b 2548 I915_WRITE(reg, temp);
8db9d77b 2549
5eddb70b
CW		 2550 reg = FDI_RX_CTL(pipe);
2551 temp = I915_READ(reg);
8db9d77b
ZW		 2552 if (HAS_PCH_CPT(dev)) {
2553 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2554 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2555 } else {
2556 temp &= ~FDI_LINK_TRAIN_NONE;
2557 temp |= FDI_LINK_TRAIN_PATTERN_2;
2558 }
5eddb70b
CW		 2559 I915_WRITE(reg, temp);
2560
2561 POSTING_READ(reg);
8db9d77b
ZW		 2562 udelay(150);
2563
0206e353 2564 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2565 reg = FDI_TX_CTL(pipe);
2566 temp = I915_READ(reg);
8db9d77b
ZW		 2567 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2568 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2569 I915_WRITE(reg, temp);
2570
2571 POSTING_READ(reg);
8db9d77b
ZW		 2572 udelay(500);
2573
fa37d39e
SP		 2574 for (retry = 0; retry < 5; retry++) {
2575 reg = FDI_RX_IIR(pipe);
2576 temp = I915_READ(reg);
2577 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2578 if (temp & FDI_RX_SYMBOL_LOCK) {
2579 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2580 DRM_DEBUG_KMS("FDI train 2 done.\n");
2581 break;
2582 }
2583 udelay(50);
8db9d77b 2584 }
fa37d39e
SP		 2585 if (retry < 5)
2586 break;
8db9d77b
ZW		 2587 }
2588 if (i == 4)
5eddb70b 2589 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2590
2591 DRM_DEBUG_KMS("FDI train done.\n");
2592}
2593
357555c0
JB		 2594/* Manual link training for Ivy Bridge A0 parts */
2595static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2596{
2597 struct drm_device *dev = crtc->dev;
2598 struct drm_i915_private *dev_priv = dev->dev_private;
2599 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2600 int pipe = intel_crtc->pipe;
2601 u32 reg, temp, i;
2602
2603 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2604 for train result */
2605 reg = FDI_RX_IMR(pipe);
2606 temp = I915_READ(reg);
2607 temp &= ~FDI_RX_SYMBOL_LOCK;
2608 temp &= ~FDI_RX_BIT_LOCK;
2609 I915_WRITE(reg, temp);
2610
2611 POSTING_READ(reg);
2612 udelay(150);
2613
01a415fd
DV		 2614 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2615 I915_READ(FDI_RX_IIR(pipe)));
2616
357555c0
JB		 2617 /* enable CPU FDI TX and PCH FDI RX */
2618 reg = FDI_TX_CTL(pipe);
2619 temp = I915_READ(reg);
627eb5a3
DV		 2620 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2621 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
357555c0
JB		 2622 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2623 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2624 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2625 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2626 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2627 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2628
d74cf324
DV		 2629 I915_WRITE(FDI_RX_MISC(pipe),
2630 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2631
357555c0
JB		 2632 reg = FDI_RX_CTL(pipe);
2633 temp = I915_READ(reg);
2634 temp &= ~FDI_LINK_TRAIN_AUTO;
2635 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2636 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2637 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2638 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2639
2640 POSTING_READ(reg);
2641 udelay(150);
2642
0206e353 2643 for (i = 0; i < 4; i++) {
357555c0
JB		 2644 reg = FDI_TX_CTL(pipe);
2645 temp = I915_READ(reg);
2646 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2647 temp |= snb_b_fdi_train_param[i];
2648 I915_WRITE(reg, temp);
2649
2650 POSTING_READ(reg);
2651 udelay(500);
2652
2653 reg = FDI_RX_IIR(pipe);
2654 temp = I915_READ(reg);
2655 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2656
2657 if (temp & FDI_RX_BIT_LOCK ||
2658 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2659 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2660 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2661 break;
2662 }
2663 }
2664 if (i == 4)
2665 DRM_ERROR("FDI train 1 fail!\n");
2666
2667 /* Train 2 */
2668 reg = FDI_TX_CTL(pipe);
2669 temp = I915_READ(reg);
2670 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2671 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2672 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2673 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2674 I915_WRITE(reg, temp);
2675
2676 reg = FDI_RX_CTL(pipe);
2677 temp = I915_READ(reg);
2678 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2679 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2680 I915_WRITE(reg, temp);
2681
2682 POSTING_READ(reg);
2683 udelay(150);
2684
0206e353 2685 for (i = 0; i < 4; i++) {
357555c0
JB		 2686 reg = FDI_TX_CTL(pipe);
2687 temp = I915_READ(reg);
2688 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2689 temp |= snb_b_fdi_train_param[i];
2690 I915_WRITE(reg, temp);
2691
2692 POSTING_READ(reg);
2693 udelay(500);
2694
2695 reg = FDI_RX_IIR(pipe);
2696 temp = I915_READ(reg);
2697 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2698
2699 if (temp & FDI_RX_SYMBOL_LOCK) {
2700 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2701 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2702 break;
2703 }
2704 }
2705 if (i == 4)
2706 DRM_ERROR("FDI train 2 fail!\n");
2707
2708 DRM_DEBUG_KMS("FDI train done.\n");
2709}
2710
88cefb6c 2711static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2712{
88cefb6c 2713 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2714 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2715 int pipe = intel_crtc->pipe;
5eddb70b 2716 u32 reg, temp;
79e53945 2717
c64e311e 2718
c98e9dcf 2719 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2720 reg = FDI_RX_CTL(pipe);
2721 temp = I915_READ(reg);
627eb5a3
DV		 2722 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2723 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2724 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2725 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2726
2727 POSTING_READ(reg);
c98e9dcf
JB		 2728 udelay(200);
2729
2730 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2731 temp = I915_READ(reg);
2732 I915_WRITE(reg, temp | FDI_PCDCLK);
2733
2734 POSTING_READ(reg);
c98e9dcf
JB		 2735 udelay(200);
2736
20749730
PZ		 2737 /* Enable CPU FDI TX PLL, always on for Ironlake */
2738 reg = FDI_TX_CTL(pipe);
2739 temp = I915_READ(reg);
2740 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2741 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2742
20749730
PZ		 2743 POSTING_READ(reg);
2744 udelay(100);
6be4a607 2745 }
0e23b99d
JB		 2746}
2747
88cefb6c
DV		 2748static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2749{
2750 struct drm_device *dev = intel_crtc->base.dev;
2751 struct drm_i915_private *dev_priv = dev->dev_private;
2752 int pipe = intel_crtc->pipe;
2753 u32 reg, temp;
2754
2755 /* Switch from PCDclk to Rawclk */
2756 reg = FDI_RX_CTL(pipe);
2757 temp = I915_READ(reg);
2758 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2759
2760 /* Disable CPU FDI TX PLL */
2761 reg = FDI_TX_CTL(pipe);
2762 temp = I915_READ(reg);
2763 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2764
2765 POSTING_READ(reg);
2766 udelay(100);
2767
2768 reg = FDI_RX_CTL(pipe);
2769 temp = I915_READ(reg);
2770 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2771
2772 /* Wait for the clocks to turn off. */
2773 POSTING_READ(reg);
2774 udelay(100);
2775}
2776
0fc932b8
JB		 2777static void ironlake_fdi_disable(struct drm_crtc *crtc)
2778{
2779 struct drm_device *dev = crtc->dev;
2780 struct drm_i915_private *dev_priv = dev->dev_private;
2781 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2782 int pipe = intel_crtc->pipe;
2783 u32 reg, temp;
2784
2785 /* disable CPU FDI tx and PCH FDI rx */
2786 reg = FDI_TX_CTL(pipe);
2787 temp = I915_READ(reg);
2788 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2789 POSTING_READ(reg);
2790
2791 reg = FDI_RX_CTL(pipe);
2792 temp = I915_READ(reg);
2793 temp &= ~(0x7 << 16);
dfd07d72 2794 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2795 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2796
2797 POSTING_READ(reg);
2798 udelay(100);
2799
2800 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2801 if (HAS_PCH_IBX(dev)) {
2802 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2803 }
0fc932b8
JB		 2804
2805 /* still set train pattern 1 */
2806 reg = FDI_TX_CTL(pipe);
2807 temp = I915_READ(reg);
2808 temp &= ~FDI_LINK_TRAIN_NONE;
2809 temp |= FDI_LINK_TRAIN_PATTERN_1;
2810 I915_WRITE(reg, temp);
2811
2812 reg = FDI_RX_CTL(pipe);
2813 temp = I915_READ(reg);
2814 if (HAS_PCH_CPT(dev)) {
2815 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2816 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2817 } else {
2818 temp &= ~FDI_LINK_TRAIN_NONE;
2819 temp |= FDI_LINK_TRAIN_PATTERN_1;
2820 }
2821 /* BPC in FDI rx is consistent with that in PIPECONF */
2822 temp &= ~(0x07 << 16);
dfd07d72 2823 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2824 I915_WRITE(reg, temp);
2825
2826 POSTING_READ(reg);
2827 udelay(100);
2828}
2829
5bb61643
CW		 2830static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2831{
2832 struct drm_device *dev = crtc->dev;
2833 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2834 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2835 unsigned long flags;
2836 bool pending;
2837
10d83730
VS		 2838 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2839 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2840 return false;
2841
2842 spin_lock_irqsave(&dev->event_lock, flags);
2843 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2844 spin_unlock_irqrestore(&dev->event_lock, flags);
2845
2846 return pending;
2847}
2848
e6c3a2a6
CW		 2849static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2850{
0f91128d 2851 struct drm_device *dev = crtc->dev;
5bb61643 2852 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2853
2854 if (crtc->fb == NULL)
2855 return;
2856
2c10d571
DV		 2857 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2858
5bb61643
CW		 2859 wait_event(dev_priv->pending_flip_queue,
2860 !intel_crtc_has_pending_flip(crtc));
2861
0f91128d
CW		 2862 mutex_lock(&dev->struct_mutex);
2863 intel_finish_fb(crtc->fb);
2864 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2865}
2866
e615efe4
ED		 2867/* Program iCLKIP clock to the desired frequency */
2868static void lpt_program_iclkip(struct drm_crtc *crtc)
2869{
2870 struct drm_device *dev = crtc->dev;
2871 struct drm_i915_private *dev_priv = dev->dev_private;
2872 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2873 u32 temp;
2874
09153000
DV		 2875 mutex_lock(&dev_priv->dpio_lock);
2876
e615efe4
ED		 2877 /* It is necessary to ungate the pixclk gate prior to programming
2878 * the divisors, and gate it back when it is done.
2879 */
2880 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2881
2882 /* Disable SSCCTL */
2883 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2884 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2885 SBI_SSCCTL_DISABLE,
2886 SBI_ICLK);
e615efe4
ED		 2887
2888 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2889 if (crtc->mode.clock == 20000) {
2890 auxdiv = 1;
2891 divsel = 0x41;
2892 phaseinc = 0x20;
2893 } else {
2894 /* The iCLK virtual clock root frequency is in MHz,
2895 * but the crtc->mode.clock in in KHz. To get the divisors,
2896 * it is necessary to divide one by another, so we
2897 * convert the virtual clock precision to KHz here for higher
2898 * precision.
2899 */
2900 u32 iclk_virtual_root_freq = 172800 * 1000;
2901 u32 iclk_pi_range = 64;
2902 u32 desired_divisor, msb_divisor_value, pi_value;
2903
2904 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2905 msb_divisor_value = desired_divisor / iclk_pi_range;
2906 pi_value = desired_divisor % iclk_pi_range;
2907
2908 auxdiv = 0;
2909 divsel = msb_divisor_value - 2;
2910 phaseinc = pi_value;
2911 }
2912
2913 /* This should not happen with any sane values */
2914 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2915 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2916 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2917 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2918
2919 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2920 crtc->mode.clock,
2921 auxdiv,
2922 divsel,
2923 phasedir,
2924 phaseinc);
2925
2926 /* Program SSCDIVINTPHASE6 */
988d6ee8 2927 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2928 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2929 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2930 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2931 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2932 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2933 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2934 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2935
2936 /* Program SSCAUXDIV */
988d6ee8 2937 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2938 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2939 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2940 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2941
2942 /* Enable modulator and associated divider */
988d6ee8 2943 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2944 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2945 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2946
2947 /* Wait for initialization time */
2948 udelay(24);
2949
2950 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2951
2952 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2953}
2954
275f01b2
DV		 2955static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2956 enum pipe pch_transcoder)
2957{
2958 struct drm_device *dev = crtc->base.dev;
2959 struct drm_i915_private *dev_priv = dev->dev_private;
2960 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2961
2962 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2963 I915_READ(HTOTAL(cpu_transcoder)));
2964 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2965 I915_READ(HBLANK(cpu_transcoder)));
2966 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2967 I915_READ(HSYNC(cpu_transcoder)));
2968
2969 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2970 I915_READ(VTOTAL(cpu_transcoder)));
2971 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2972 I915_READ(VBLANK(cpu_transcoder)));
2973 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2974 I915_READ(VSYNC(cpu_transcoder)));
2975 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2976 I915_READ(VSYNCSHIFT(cpu_transcoder)));
2977}
2978
f67a559d
JB		 2979/*
2980 * Enable PCH resources required for PCH ports:
2981 * - PCH PLLs
2982 * - FDI training & RX/TX
2983 * - update transcoder timings
2984 * - DP transcoding bits
2985 * - transcoder
2986 */
2987static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2988{
2989 struct drm_device *dev = crtc->dev;
2990 struct drm_i915_private *dev_priv = dev->dev_private;
2991 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2992 int pipe = intel_crtc->pipe;
ee7b9f93 2993 u32 reg, temp;
2c07245f 2994
ab9412ba 2995 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 2996
cd986abb
DV		 2997 /* Write the TU size bits before fdi link training, so that error
2998 * detection works. */
2999 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3000 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3001
c98e9dcf 3002 /* For PCH output, training FDI link */
674cf967 3003 dev_priv->display.fdi_link_train(crtc);
2c07245f 3004
572deb37
DV		 3005 /* XXX: pch pll's can be enabled any time before we enable the PCH
3006 * transcoder, and we actually should do this to not upset any PCH
3007 * transcoder that already use the clock when we share it.
3008 *
3009 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3010 * unconditionally resets the pll - we need that to have the right LVDS
3011 * enable sequence. */
b6b4e185 3012 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 3013
303b81e0 3014 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3015 u32 sel;
4b645f14 3016
c98e9dcf 3017 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3018 switch (pipe) {
3019 default:
3020 case 0:
3021 temp |= TRANSA_DPLL_ENABLE;
3022 sel = TRANSA_DPLLB_SEL;
3023 break;
3024 case 1:
3025 temp |= TRANSB_DPLL_ENABLE;
3026 sel = TRANSB_DPLLB_SEL;
3027 break;
3028 case 2:
3029 temp |= TRANSC_DPLL_ENABLE;
3030 sel = TRANSC_DPLLB_SEL;
3031 break;
d64311ab 3032 }
ee7b9f93
JB		 3033 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3034 temp |= sel;
3035 else
3036 temp &= ~sel;
c98e9dcf 3037 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3038 }
5eddb70b 3039
d9b6cb56
JB		 3040 /* set transcoder timing, panel must allow it */
3041 assert_panel_unlocked(dev_priv, pipe);
275f01b2 3042 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 3043
303b81e0 3044 intel_fdi_normal_train(crtc);
5e84e1a4 3045
c98e9dcf
JB		 3046 /* For PCH DP, enable TRANS_DP_CTL */
3047 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3048 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3049 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3050 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3051 reg = TRANS_DP_CTL(pipe);
3052 temp = I915_READ(reg);
3053 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3054 TRANS_DP_SYNC_MASK |
3055 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3056 temp |= (TRANS_DP_OUTPUT_ENABLE |
3057 TRANS_DP_ENH_FRAMING);
9325c9f0 3058 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3059
3060 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3061 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3062 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3063 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3064
3065 switch (intel_trans_dp_port_sel(crtc)) {
3066 case PCH_DP_B:
5eddb70b 3067 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3068 break;
3069 case PCH_DP_C:
5eddb70b 3070 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3071 break;
3072 case PCH_DP_D:
5eddb70b 3073 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3074 break;
3075 default:
e95d41e1 3076 BUG();
32f9d658 3077 }
2c07245f 3078
5eddb70b 3079 I915_WRITE(reg, temp);
6be4a607 3080 }
b52eb4dc 3081
b8a4f404 3082 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3083}
3084
1507e5bd
PZ		 3085static void lpt_pch_enable(struct drm_crtc *crtc)
3086{
3087 struct drm_device *dev = crtc->dev;
3088 struct drm_i915_private *dev_priv = dev->dev_private;
3089 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3090 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3091
ab9412ba 3092 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3093
8c52b5e8 3094 lpt_program_iclkip(crtc);
1507e5bd 3095
0540e488 3096 /* Set transcoder timing. */
275f01b2 3097 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3098
937bb610 3099 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3100}
3101
ee7b9f93
JB		 3102static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3103{
3104 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3105
3106 if (pll == NULL)
3107 return;
3108
3109 if (pll->refcount == 0) {
3110 WARN(1, "bad PCH PLL refcount\n");
3111 return;
3112 }
3113
3114 --pll->refcount;
3115 intel_crtc->pch_pll = NULL;
3116}
3117
3118static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3119{
3120 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3121 struct intel_pch_pll *pll;
3122 int i;
3123
3124 pll = intel_crtc->pch_pll;
3125 if (pll) {
3126 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3127 intel_crtc->base.base.id, pll->pll_reg);
3128 goto prepare;
3129 }
3130
98b6bd99
DV		 3131 if (HAS_PCH_IBX(dev_priv->dev)) {
3132 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3133 i = intel_crtc->pipe;
3134 pll = &dev_priv->pch_plls[i];
3135
3136 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3137 intel_crtc->base.base.id, pll->pll_reg);
3138
3139 goto found;
3140 }
3141
ee7b9f93
JB		 3142 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3143 pll = &dev_priv->pch_plls[i];
3144
3145 /* Only want to check enabled timings first */
3146 if (pll->refcount == 0)
3147 continue;
3148
3149 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3150 fp == I915_READ(pll->fp0_reg)) {
3151 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3152 intel_crtc->base.base.id,
3153 pll->pll_reg, pll->refcount, pll->active);
3154
3155 goto found;
3156 }
3157 }
3158
3159 /* Ok no matching timings, maybe there's a free one? */
3160 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3161 pll = &dev_priv->pch_plls[i];
3162 if (pll->refcount == 0) {
3163 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3164 intel_crtc->base.base.id, pll->pll_reg);
3165 goto found;
3166 }
3167 }
3168
3169 return NULL;
3170
3171found:
3172 intel_crtc->pch_pll = pll;
3173 pll->refcount++;
84f44ce7 3174 DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
ee7b9f93
JB		 3175prepare: /* separate function? */
3176 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3177
e04c7350
CW		 3178 /* Wait for the clocks to stabilize before rewriting the regs */
3179 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3180 POSTING_READ(pll->pll_reg);
3181 udelay(150);
e04c7350
CW		 3182
3183 I915_WRITE(pll->fp0_reg, fp);
3184 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3185 pll->on = false;
3186 return pll;
3187}
3188
a1520318 3189static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3190{
3191 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3192 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3193 u32 temp;
3194
3195 temp = I915_READ(dslreg);
3196 udelay(500);
3197 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3198 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3199 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3200 }
3201}
3202
b074cec8
JB		 3203static void ironlake_pfit_enable(struct intel_crtc *crtc)
3204{
3205 struct drm_device *dev = crtc->base.dev;
3206 struct drm_i915_private *dev_priv = dev->dev_private;
3207 int pipe = crtc->pipe;
3208
0ef37f3f 3209 if (crtc->config.pch_pfit.size) {
b074cec8
JB		 3210 /* Force use of hard-coded filter coefficients
3211 * as some pre-programmed values are broken,
3212 * e.g. x201.
3213 */
3214 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3215 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3216 PF_PIPE_SEL_IVB(pipe));
3217 else
3218 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3219 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3220 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3221 }
3222}
3223
f67a559d
JB		 3224static void ironlake_crtc_enable(struct drm_crtc *crtc)
3225{
3226 struct drm_device *dev = crtc->dev;
3227 struct drm_i915_private *dev_priv = dev->dev_private;
3228 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3229 struct intel_encoder *encoder;
f67a559d
JB		 3230 int pipe = intel_crtc->pipe;
3231 int plane = intel_crtc->plane;
3232 u32 temp;
f67a559d 3233
08a48469
DV		 3234 WARN_ON(!crtc->enabled);
3235
f67a559d
JB		 3236 if (intel_crtc->active)
3237 return;
3238
3239 intel_crtc->active = true;
8664281b
PZ		 3240
3241 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3242 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3243
f67a559d
JB		 3244 intel_update_watermarks(dev);
3245
3246 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3247 temp = I915_READ(PCH_LVDS);
3248 if ((temp & LVDS_PORT_EN) == 0)
3249 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3250 }
3251
f67a559d 3252
5bfe2ac0 3253 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3254 /* Note: FDI PLL enabling _must_ be done before we enable the
3255 * cpu pipes, hence this is separate from all the other fdi/pch
3256 * enabling. */
88cefb6c 3257 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3258 } else {
3259 assert_fdi_tx_disabled(dev_priv, pipe);
3260 assert_fdi_rx_disabled(dev_priv, pipe);
3261 }
f67a559d 3262
bf49ec8c
DV		 3263 for_each_encoder_on_crtc(dev, crtc, encoder)
3264 if (encoder->pre_enable)
3265 encoder->pre_enable(encoder);
f67a559d
JB		 3266
3267 /* Enable panel fitting for LVDS */
b074cec8 3268 ironlake_pfit_enable(intel_crtc);
f67a559d 3269
9c54c0dd
JB		 3270 /*
3271 * On ILK+ LUT must be loaded before the pipe is running but with
3272 * clocks enabled
3273 */
3274 intel_crtc_load_lut(crtc);
3275
5bfe2ac0
DV		 3276 intel_enable_pipe(dev_priv, pipe,
3277 intel_crtc->config.has_pch_encoder);
f67a559d
JB		 3278 intel_enable_plane(dev_priv, plane, pipe);
3279
5bfe2ac0 3280 if (intel_crtc->config.has_pch_encoder)
f67a559d 3281 ironlake_pch_enable(crtc);
c98e9dcf 3282
d1ebd816 3283 mutex_lock(&dev->struct_mutex);
bed4a673 3284 intel_update_fbc(dev);
d1ebd816
BW		 3285 mutex_unlock(&dev->struct_mutex);
3286
6b383a7f 3287 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3288
fa5c73b1
DV		 3289 for_each_encoder_on_crtc(dev, crtc, encoder)
3290 encoder->enable(encoder);
61b77ddd
DV		 3291
3292 if (HAS_PCH_CPT(dev))
a1520318 3293 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3294
3295 /*
3296 * There seems to be a race in PCH platform hw (at least on some
3297 * outputs) where an enabled pipe still completes any pageflip right
3298 * away (as if the pipe is off) instead of waiting for vblank. As soon
3299 * as the first vblank happend, everything works as expected. Hence just
3300 * wait for one vblank before returning to avoid strange things
3301 * happening.
3302 */
3303 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3304}
3305
42db64ef
PZ		 3306/* IPS only exists on ULT machines and is tied to pipe A. */
3307static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3308{
3309 return IS_ULT(crtc->base.dev) && crtc->pipe == PIPE_A;
3310}
3311
3312static void hsw_enable_ips(struct intel_crtc *crtc)
3313{
3314 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3315
3316 if (!crtc->config.ips_enabled)
3317 return;
3318
3319 /* We can only enable IPS after we enable a plane and wait for a vblank.
3320 * We guarantee that the plane is enabled by calling intel_enable_ips
3321 * only after intel_enable_plane. And intel_enable_plane already waits
3322 * for a vblank, so all we need to do here is to enable the IPS bit. */
3323 assert_plane_enabled(dev_priv, crtc->plane);
3324 I915_WRITE(IPS_CTL, IPS_ENABLE);
3325}
3326
3327static void hsw_disable_ips(struct intel_crtc *crtc)
3328{
3329 struct drm_device *dev = crtc->base.dev;
3330 struct drm_i915_private *dev_priv = dev->dev_private;
3331
3332 if (!crtc->config.ips_enabled)
3333 return;
3334
3335 assert_plane_enabled(dev_priv, crtc->plane);
3336 I915_WRITE(IPS_CTL, 0);
3337
3338 /* We need to wait for a vblank before we can disable the plane. */
3339 intel_wait_for_vblank(dev, crtc->pipe);
3340}
3341
4f771f10
PZ		 3342static void haswell_crtc_enable(struct drm_crtc *crtc)
3343{
3344 struct drm_device *dev = crtc->dev;
3345 struct drm_i915_private *dev_priv = dev->dev_private;
3346 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3347 struct intel_encoder *encoder;
3348 int pipe = intel_crtc->pipe;
3349 int plane = intel_crtc->plane;
4f771f10
PZ		 3350
3351 WARN_ON(!crtc->enabled);
3352
3353 if (intel_crtc->active)
3354 return;
3355
3356 intel_crtc->active = true;
8664281b
PZ		 3357
3358 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3359 if (intel_crtc->config.has_pch_encoder)
3360 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3361
4f771f10
PZ		 3362 intel_update_watermarks(dev);
3363
5bfe2ac0 3364 if (intel_crtc->config.has_pch_encoder)
04945641 3365 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3366
3367 for_each_encoder_on_crtc(dev, crtc, encoder)
3368 if (encoder->pre_enable)
3369 encoder->pre_enable(encoder);
3370
1f544388 3371 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3372
1f544388 3373 /* Enable panel fitting for eDP */
b074cec8 3374 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3375
3376 /*
3377 * On ILK+ LUT must be loaded before the pipe is running but with
3378 * clocks enabled
3379 */
3380 intel_crtc_load_lut(crtc);
3381
1f544388 3382 intel_ddi_set_pipe_settings(crtc);
8228c251 3383 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3384
5bfe2ac0
DV		 3385 intel_enable_pipe(dev_priv, pipe,
3386 intel_crtc->config.has_pch_encoder);
4f771f10
PZ		 3387 intel_enable_plane(dev_priv, plane, pipe);
3388
42db64ef
PZ		 3389 hsw_enable_ips(intel_crtc);
3390
5bfe2ac0 3391 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3392 lpt_pch_enable(crtc);
4f771f10
PZ		 3393
3394 mutex_lock(&dev->struct_mutex);
3395 intel_update_fbc(dev);
3396 mutex_unlock(&dev->struct_mutex);
3397
3398 intel_crtc_update_cursor(crtc, true);
3399
3400 for_each_encoder_on_crtc(dev, crtc, encoder)
3401 encoder->enable(encoder);
3402
4f771f10
PZ		 3403 /*
3404 * There seems to be a race in PCH platform hw (at least on some
3405 * outputs) where an enabled pipe still completes any pageflip right
3406 * away (as if the pipe is off) instead of waiting for vblank. As soon
3407 * as the first vblank happend, everything works as expected. Hence just
3408 * wait for one vblank before returning to avoid strange things
3409 * happening.
3410 */
3411 intel_wait_for_vblank(dev, intel_crtc->pipe);
3412}
3413
3f8dce3a
DV		 3414static void ironlake_pfit_disable(struct intel_crtc *crtc)
3415{
3416 struct drm_device *dev = crtc->base.dev;
3417 struct drm_i915_private *dev_priv = dev->dev_private;
3418 int pipe = crtc->pipe;
3419
3420 /* To avoid upsetting the power well on haswell only disable the pfit if
3421 * it's in use. The hw state code will make sure we get this right. */
3422 if (crtc->config.pch_pfit.size) {
3423 I915_WRITE(PF_CTL(pipe), 0);
3424 I915_WRITE(PF_WIN_POS(pipe), 0);
3425 I915_WRITE(PF_WIN_SZ(pipe), 0);
3426 }
3427}
3428
6be4a607
JB		 3429static void ironlake_crtc_disable(struct drm_crtc *crtc)
3430{
3431 struct drm_device *dev = crtc->dev;
3432 struct drm_i915_private *dev_priv = dev->dev_private;
3433 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3434 struct intel_encoder *encoder;
6be4a607
JB		 3435 int pipe = intel_crtc->pipe;
3436 int plane = intel_crtc->plane;
5eddb70b 3437 u32 reg, temp;
b52eb4dc 3438
ef9c3aee 3439
f7abfe8b
CW		 3440 if (!intel_crtc->active)
3441 return;
3442
ea9d758d
DV		 3443 for_each_encoder_on_crtc(dev, crtc, encoder)
3444 encoder->disable(encoder);
3445
e6c3a2a6 3446 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3447 drm_vblank_off(dev, pipe);
6b383a7f 3448 intel_crtc_update_cursor(crtc, false);
5eddb70b 3449
b24e7179 3450 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3451
973d04f9
CW		 3452 if (dev_priv->cfb_plane == plane)
3453 intel_disable_fbc(dev);
2c07245f 3454
8664281b 3455 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
b24e7179 3456 intel_disable_pipe(dev_priv, pipe);
32f9d658 3457
3f8dce3a 3458 ironlake_pfit_disable(intel_crtc);
2c07245f 3459
bf49ec8c
DV		 3460 for_each_encoder_on_crtc(dev, crtc, encoder)
3461 if (encoder->post_disable)
3462 encoder->post_disable(encoder);
2c07245f 3463
0fc932b8 3464 ironlake_fdi_disable(crtc);
249c0e64 3465
b8a4f404 3466 ironlake_disable_pch_transcoder(dev_priv, pipe);
8664281b 3467 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
913d8d11 3468
6be4a607
JB		 3469 if (HAS_PCH_CPT(dev)) {
3470 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3471 reg = TRANS_DP_CTL(pipe);
3472 temp = I915_READ(reg);
3473 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3474 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3475 I915_WRITE(reg, temp);
6be4a607
JB		 3476
3477 /* disable DPLL_SEL */
3478 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3479 switch (pipe) {
3480 case 0:
d64311ab 3481 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3482 break;
3483 case 1:
6be4a607 3484 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3485 break;
3486 case 2:
4b645f14 3487 /* C shares PLL A or B */
d64311ab 3488 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3489 break;
3490 default:
3491 BUG(); /* wtf */
3492 }
6be4a607 3493 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3494 }
e3421a18 3495
6be4a607 3496 /* disable PCH DPLL */
ee7b9f93 3497 intel_disable_pch_pll(intel_crtc);
8db9d77b 3498
88cefb6c 3499 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3500
f7abfe8b 3501 intel_crtc->active = false;
6b383a7f 3502 intel_update_watermarks(dev);
d1ebd816
BW		 3503
3504 mutex_lock(&dev->struct_mutex);
6b383a7f 3505 intel_update_fbc(dev);
d1ebd816 3506 mutex_unlock(&dev->struct_mutex);
6be4a607 3507}
1b3c7a47 3508
4f771f10 3509static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3510{
4f771f10
PZ		 3511 struct drm_device *dev = crtc->dev;
3512 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3513 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3514 struct intel_encoder *encoder;
3515 int pipe = intel_crtc->pipe;
3516 int plane = intel_crtc->plane;
3b117c8f 3517 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3518
4f771f10
PZ		 3519 if (!intel_crtc->active)
3520 return;
3521
3522 for_each_encoder_on_crtc(dev, crtc, encoder)
3523 encoder->disable(encoder);
3524
3525 intel_crtc_wait_for_pending_flips(crtc);
3526 drm_vblank_off(dev, pipe);
3527 intel_crtc_update_cursor(crtc, false);
3528
891348b2 3529 /* FBC must be disabled before disabling the plane on HSW. */
4f771f10
PZ		 3530 if (dev_priv->cfb_plane == plane)
3531 intel_disable_fbc(dev);
3532
42db64ef
PZ		 3533 hsw_disable_ips(intel_crtc);
3534
891348b2
RV		 3535 intel_disable_plane(dev_priv, plane, pipe);
3536
8664281b
PZ		 3537 if (intel_crtc->config.has_pch_encoder)
3538 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3539 intel_disable_pipe(dev_priv, pipe);
3540
ad80a810 3541 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3542
3f8dce3a 3543 ironlake_pfit_disable(intel_crtc);
4f771f10 3544
1f544388 3545 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3546
3547 for_each_encoder_on_crtc(dev, crtc, encoder)
3548 if (encoder->post_disable)
3549 encoder->post_disable(encoder);
3550
88adfff1 3551 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3552 lpt_disable_pch_transcoder(dev_priv);
8664281b 3553 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3554 intel_ddi_fdi_disable(crtc);
83616634 3555 }
4f771f10
PZ		 3556
3557 intel_crtc->active = false;
3558 intel_update_watermarks(dev);
3559
3560 mutex_lock(&dev->struct_mutex);
3561 intel_update_fbc(dev);
3562 mutex_unlock(&dev->struct_mutex);
3563}
3564
ee7b9f93
JB		 3565static void ironlake_crtc_off(struct drm_crtc *crtc)
3566{
3567 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3568 intel_put_pch_pll(intel_crtc);
3569}
3570
6441ab5f
PZ		 3571static void haswell_crtc_off(struct drm_crtc *crtc)
3572{
3573 intel_ddi_put_crtc_pll(crtc);
3574}
3575
02e792fb
DV		 3576static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3577{
02e792fb 3578 if (!enable && intel_crtc->overlay) {
23f09ce3 3579 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3580 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3581
23f09ce3 3582 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3583 dev_priv->mm.interruptible = false;
3584 (void) intel_overlay_switch_off(intel_crtc->overlay);
3585 dev_priv->mm.interruptible = true;
23f09ce3 3586 mutex_unlock(&dev->struct_mutex);
02e792fb 3587 }
02e792fb 3588
5dcdbcb0
CW		 3589 /* Let userspace switch the overlay on again. In most cases userspace
3590 * has to recompute where to put it anyway.
3591 */
02e792fb
DV		 3592}
3593
61bc95c1
EE		 3594/**
3595 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3596 * cursor plane briefly if not already running after enabling the display
3597 * plane.
3598 * This workaround avoids occasional blank screens when self refresh is
3599 * enabled.
3600 */
3601static void
3602g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3603{
3604 u32 cntl = I915_READ(CURCNTR(pipe));
3605
3606 if ((cntl & CURSOR_MODE) == 0) {
3607 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3608
3609 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3610 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3611 intel_wait_for_vblank(dev_priv->dev, pipe);
3612 I915_WRITE(CURCNTR(pipe), cntl);
3613 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3614 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3615 }
3616}
3617
2dd24552
JB		 3618static void i9xx_pfit_enable(struct intel_crtc *crtc)
3619{
3620 struct drm_device *dev = crtc->base.dev;
3621 struct drm_i915_private *dev_priv = dev->dev_private;
3622 struct intel_crtc_config *pipe_config = &crtc->config;
3623
328d8e82 3624 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3625 return;
3626
2dd24552 3627 /*
c0b03411
DV		 3628 * The panel fitter should only be adjusted whilst the pipe is disabled,
3629 * according to register description and PRM.
2dd24552 3630 */
c0b03411
DV		 3631 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3632 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3633
b074cec8
JB		 3634 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3635 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3636
3637 /* Border color in case we don't scale up to the full screen. Black by
3638 * default, change to something else for debugging. */
3639 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3640}
3641
89b667f8
JB		 3642static void valleyview_crtc_enable(struct drm_crtc *crtc)
3643{
3644 struct drm_device *dev = crtc->dev;
3645 struct drm_i915_private *dev_priv = dev->dev_private;
3646 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3647 struct intel_encoder *encoder;
3648 int pipe = intel_crtc->pipe;
3649 int plane = intel_crtc->plane;
3650
3651 WARN_ON(!crtc->enabled);
3652
3653 if (intel_crtc->active)
3654 return;
3655
3656 intel_crtc->active = true;
3657 intel_update_watermarks(dev);
3658
3659 mutex_lock(&dev_priv->dpio_lock);
3660
3661 for_each_encoder_on_crtc(dev, crtc, encoder)
3662 if (encoder->pre_pll_enable)
3663 encoder->pre_pll_enable(encoder);
3664
3665 intel_enable_pll(dev_priv, pipe);
3666
3667 for_each_encoder_on_crtc(dev, crtc, encoder)
3668 if (encoder->pre_enable)
3669 encoder->pre_enable(encoder);
3670
3671 /* VLV wants encoder enabling _before_ the pipe is up. */
3672 for_each_encoder_on_crtc(dev, crtc, encoder)
3673 encoder->enable(encoder);
3674
2dd24552
JB		 3675 /* Enable panel fitting for eDP */
3676 i9xx_pfit_enable(intel_crtc);
3677
89b667f8
JB		 3678 intel_enable_pipe(dev_priv, pipe, false);
3679 intel_enable_plane(dev_priv, plane, pipe);
3680
3681 intel_crtc_load_lut(crtc);
3682 intel_update_fbc(dev);
3683
3684 /* Give the overlay scaler a chance to enable if it's on this pipe */
3685 intel_crtc_dpms_overlay(intel_crtc, true);
3686 intel_crtc_update_cursor(crtc, true);
3687
3688 mutex_unlock(&dev_priv->dpio_lock);
3689}
3690
0b8765c6 3691static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3692{
3693 struct drm_device *dev = crtc->dev;
79e53945
JB		 3694 struct drm_i915_private *dev_priv = dev->dev_private;
3695 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3696 struct intel_encoder *encoder;
79e53945 3697 int pipe = intel_crtc->pipe;
80824003 3698 int plane = intel_crtc->plane;
79e53945 3699
08a48469
DV		 3700 WARN_ON(!crtc->enabled);
3701
f7abfe8b
CW		 3702 if (intel_crtc->active)
3703 return;
3704
3705 intel_crtc->active = true;
6b383a7f
CW		 3706 intel_update_watermarks(dev);
3707
63d7bbe9 3708 intel_enable_pll(dev_priv, pipe);
9d6d9f19
MK		 3709
3710 for_each_encoder_on_crtc(dev, crtc, encoder)
3711 if (encoder->pre_enable)
3712 encoder->pre_enable(encoder);
3713
2dd24552
JB		 3714 /* Enable panel fitting for LVDS */
3715 i9xx_pfit_enable(intel_crtc);
3716
040484af 3717 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3718 intel_enable_plane(dev_priv, plane, pipe);
61bc95c1
EE		 3719 if (IS_G4X(dev))
3720 g4x_fixup_plane(dev_priv, pipe);
79e53945 3721
0b8765c6 3722 intel_crtc_load_lut(crtc);
bed4a673 3723 intel_update_fbc(dev);
79e53945 3724
0b8765c6
JB		 3725 /* Give the overlay scaler a chance to enable if it's on this pipe */
3726 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3727 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3728
fa5c73b1
DV		 3729 for_each_encoder_on_crtc(dev, crtc, encoder)
3730 encoder->enable(encoder);
0b8765c6 3731}
79e53945 3732
87476d63
DV		 3733static void i9xx_pfit_disable(struct intel_crtc *crtc)
3734{
3735 struct drm_device *dev = crtc->base.dev;
3736 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3737
328d8e82
DV		 3738 if (!crtc->config.gmch_pfit.control)
3739 return;
87476d63 3740
328d8e82 3741 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3742
328d8e82
DV		 3743 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3744 I915_READ(PFIT_CONTROL));
3745 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3746}
3747
0b8765c6
JB		 3748static void i9xx_crtc_disable(struct drm_crtc *crtc)
3749{
3750 struct drm_device *dev = crtc->dev;
3751 struct drm_i915_private *dev_priv = dev->dev_private;
3752 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3753 struct intel_encoder *encoder;
0b8765c6
JB		 3754 int pipe = intel_crtc->pipe;
3755 int plane = intel_crtc->plane;
ef9c3aee 3756
f7abfe8b
CW		 3757 if (!intel_crtc->active)
3758 return;
3759
ea9d758d
DV		 3760 for_each_encoder_on_crtc(dev, crtc, encoder)
3761 encoder->disable(encoder);
3762
0b8765c6 3763 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3764 intel_crtc_wait_for_pending_flips(crtc);
3765 drm_vblank_off(dev, pipe);
0b8765c6 3766 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3767 intel_crtc_update_cursor(crtc, false);
0b8765c6 3768
973d04f9
CW		 3769 if (dev_priv->cfb_plane == plane)
3770 intel_disable_fbc(dev);
79e53945 3771
b24e7179 3772 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3773 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3774
87476d63 3775 i9xx_pfit_disable(intel_crtc);
24a1f16d 3776
89b667f8
JB		 3777 for_each_encoder_on_crtc(dev, crtc, encoder)
3778 if (encoder->post_disable)
3779 encoder->post_disable(encoder);
3780
63d7bbe9 3781 intel_disable_pll(dev_priv, pipe);
0b8765c6 3782
f7abfe8b 3783 intel_crtc->active = false;
6b383a7f
CW		 3784 intel_update_fbc(dev);
3785 intel_update_watermarks(dev);
0b8765c6
JB		 3786}
3787
ee7b9f93
JB		 3788static void i9xx_crtc_off(struct drm_crtc *crtc)
3789{
3790}
3791
976f8a20
DV		 3792static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3793 bool enabled)
2c07245f
ZW		 3794{
3795 struct drm_device *dev = crtc->dev;
3796 struct drm_i915_master_private *master_priv;
3797 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3798 int pipe = intel_crtc->pipe;
79e53945
JB		 3799
3800 if (!dev->primary->master)
3801 return;
3802
3803 master_priv = dev->primary->master->driver_priv;
3804 if (!master_priv->sarea_priv)
3805 return;
3806
79e53945
JB		 3807 switch (pipe) {
3808 case 0:
3809 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3810 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3811 break;
3812 case 1:
3813 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3814 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3815 break;
3816 default:
9db4a9c7 3817 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3818 break;
3819 }
79e53945
JB		 3820}
3821
976f8a20
DV		 3822/**
3823 * Sets the power management mode of the pipe and plane.
3824 */
3825void intel_crtc_update_dpms(struct drm_crtc *crtc)
3826{
3827 struct drm_device *dev = crtc->dev;
3828 struct drm_i915_private *dev_priv = dev->dev_private;
3829 struct intel_encoder *intel_encoder;
3830 bool enable = false;
3831
3832 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3833 enable |= intel_encoder->connectors_active;
3834
3835 if (enable)
3836 dev_priv->display.crtc_enable(crtc);
3837 else
3838 dev_priv->display.crtc_disable(crtc);
3839
3840 intel_crtc_update_sarea(crtc, enable);
3841}
3842
cdd59983
CW		 3843static void intel_crtc_disable(struct drm_crtc *crtc)
3844{
cdd59983 3845 struct drm_device *dev = crtc->dev;
976f8a20 3846 struct drm_connector *connector;
ee7b9f93 3847 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3848 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3849
976f8a20
DV		 3850 /* crtc should still be enabled when we disable it. */
3851 WARN_ON(!crtc->enabled);
3852
3853 dev_priv->display.crtc_disable(crtc);
c77bf565 3854 intel_crtc->eld_vld = false;
976f8a20 3855 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3856 dev_priv->display.off(crtc);
3857
931872fc
CW		 3858 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3859 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3860
3861 if (crtc->fb) {
3862 mutex_lock(&dev->struct_mutex);
1690e1eb 3863 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3864 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3865 crtc->fb = NULL;
3866 }
3867
3868 /* Update computed state. */
3869 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3870 if (!connector->encoder || !connector->encoder->crtc)
3871 continue;
3872
3873 if (connector->encoder->crtc != crtc)
3874 continue;
3875
3876 connector->dpms = DRM_MODE_DPMS_OFF;
3877 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3878 }
3879}
3880
a261b246 3881void intel_modeset_disable(struct drm_device *dev)
79e53945 3882{
a261b246
DV		 3883 struct drm_crtc *crtc;
3884
3885 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3886 if (crtc->enabled)
3887 intel_crtc_disable(crtc);
3888 }
79e53945
JB		 3889}
3890
ea5b213a 3891void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3892{
4ef69c7a 3893 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3894
ea5b213a
CW		 3895 drm_encoder_cleanup(encoder);
3896 kfree(intel_encoder);
7e7d76c3
JB		 3897}
3898
5ab432ef
DV		 3899/* Simple dpms helper for encodres with just one connector, no cloning and only
3900 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3901 * state of the entire output pipe. */
3902void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3903{
5ab432ef
DV		 3904 if (mode == DRM_MODE_DPMS_ON) {
3905 encoder->connectors_active = true;
3906
b2cabb0e 3907 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3908 } else {
3909 encoder->connectors_active = false;
3910
b2cabb0e 3911 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3912 }
79e53945
JB		 3913}
3914
0a91ca29
DV		 3915/* Cross check the actual hw state with our own modeset state tracking (and it's
3916 * internal consistency). */
b980514c 3917static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3918{
0a91ca29
DV		 3919 if (connector->get_hw_state(connector)) {
3920 struct intel_encoder *encoder = connector->encoder;
3921 struct drm_crtc *crtc;
3922 bool encoder_enabled;
3923 enum pipe pipe;
3924
3925 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3926 connector->base.base.id,
3927 drm_get_connector_name(&connector->base));
3928
3929 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3930 "wrong connector dpms state\n");
3931 WARN(connector->base.encoder != &encoder->base,
3932 "active connector not linked to encoder\n");
3933 WARN(!encoder->connectors_active,
3934 "encoder->connectors_active not set\n");
3935
3936 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3937 WARN(!encoder_enabled, "encoder not enabled\n");
3938 if (WARN_ON(!encoder->base.crtc))
3939 return;
3940
3941 crtc = encoder->base.crtc;
3942
3943 WARN(!crtc->enabled, "crtc not enabled\n");
3944 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3945 WARN(pipe != to_intel_crtc(crtc)->pipe,
3946 "encoder active on the wrong pipe\n");
3947 }
79e53945
JB		 3948}
3949
5ab432ef
DV		 3950/* Even simpler default implementation, if there's really no special case to
3951 * consider. */
3952void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3953{
5ab432ef 3954 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3955
5ab432ef
DV		 3956 /* All the simple cases only support two dpms states. */
3957 if (mode != DRM_MODE_DPMS_ON)
3958 mode = DRM_MODE_DPMS_OFF;
d4270e57 3959
5ab432ef
DV		 3960 if (mode == connector->dpms)
3961 return;
3962
3963 connector->dpms = mode;
3964
3965 /* Only need to change hw state when actually enabled */
3966 if (encoder->base.crtc)
3967 intel_encoder_dpms(encoder, mode);
3968 else
8af6cf88 3969 WARN_ON(encoder->connectors_active != false);
0a91ca29 3970
b980514c 3971 intel_modeset_check_state(connector->dev);
79e53945
JB		 3972}
3973
f0947c37
DV		 3974/* Simple connector->get_hw_state implementation for encoders that support only
3975 * one connector and no cloning and hence the encoder state determines the state
3976 * of the connector. */
3977bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3978{
24929352 3979 enum pipe pipe = 0;
f0947c37 3980 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3981
f0947c37 3982 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3983}
3984
1857e1da
DV		 3985static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3986 struct intel_crtc_config *pipe_config)
3987{
3988 struct drm_i915_private *dev_priv = dev->dev_private;
3989 struct intel_crtc *pipe_B_crtc =
3990 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3991
3992 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3993 pipe_name(pipe), pipe_config->fdi_lanes);
3994 if (pipe_config->fdi_lanes > 4) {
3995 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3996 pipe_name(pipe), pipe_config->fdi_lanes);
3997 return false;
3998 }
3999
4000 if (IS_HASWELL(dev)) {
4001 if (pipe_config->fdi_lanes > 2) {
4002 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4003 pipe_config->fdi_lanes);
4004 return false;
4005 } else {
4006 return true;
4007 }
4008 }
4009
4010 if (INTEL_INFO(dev)->num_pipes == 2)
4011 return true;
4012
4013 /* Ivybridge 3 pipe is really complicated */
4014 switch (pipe) {
4015 case PIPE_A:
4016 return true;
4017 case PIPE_B:
4018 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4019 pipe_config->fdi_lanes > 2) {
4020 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4021 pipe_name(pipe), pipe_config->fdi_lanes);
4022 return false;
4023 }
4024 return true;
4025 case PIPE_C:
1e833f40 4026 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 4027 pipe_B_crtc->config.fdi_lanes <= 2) {
4028 if (pipe_config->fdi_lanes > 2) {
4029 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4030 pipe_name(pipe), pipe_config->fdi_lanes);
4031 return false;
4032 }
4033 } else {
4034 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4035 return false;
4036 }
4037 return true;
4038 default:
4039 BUG();
4040 }
4041}
4042
e29c22c0
DV		 4043#define RETRY 1
4044static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4045 struct intel_crtc_config *pipe_config)
877d48d5 4046{
1857e1da 4047 struct drm_device *dev = intel_crtc->base.dev;
877d48d5
DV		 4048 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4049 int target_clock, lane, link_bw;
e29c22c0 4050 bool setup_ok, needs_recompute = false;
877d48d5 4051
e29c22c0 4052retry:
877d48d5
DV		 4053 /* FDI is a binary signal running at ~2.7GHz, encoding
4054 * each output octet as 10 bits. The actual frequency
4055 * is stored as a divider into a 100MHz clock, and the
4056 * mode pixel clock is stored in units of 1KHz.
4057 * Hence the bw of each lane in terms of the mode signal
4058 * is:
4059 */
4060 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4061
4062 if (pipe_config->pixel_target_clock)
4063 target_clock = pipe_config->pixel_target_clock;
4064 else
4065 target_clock = adjusted_mode->clock;
4066
4067 lane = ironlake_get_lanes_required(target_clock, link_bw,
4068 pipe_config->pipe_bpp);
4069
4070 pipe_config->fdi_lanes = lane;
4071
4072 if (pipe_config->pixel_multiplier > 1)
4073 link_bw *= pipe_config->pixel_multiplier;
4074 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, target_clock,
4075 link_bw, &pipe_config->fdi_m_n);
1857e1da 4076
e29c22c0
DV		 4077 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4078 intel_crtc->pipe, pipe_config);
4079 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4080 pipe_config->pipe_bpp -= 2*3;
4081 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4082 pipe_config->pipe_bpp);
4083 needs_recompute = true;
4084 pipe_config->bw_constrained = true;
4085
4086 goto retry;
4087 }
4088
4089 if (needs_recompute)
4090 return RETRY;
4091
4092 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4093}
4094
42db64ef
PZ		 4095static void hsw_compute_ips_config(struct intel_crtc *crtc,
4096 struct intel_crtc_config *pipe_config)
4097{
3c4ca58c
PZ		 4098 pipe_config->ips_enabled = i915_enable_ips &&
4099 hsw_crtc_supports_ips(crtc) &&
42db64ef
PZ		 4100 pipe_config->pipe_bpp == 24;
4101}
4102
e29c22c0
DV		 4103static int intel_crtc_compute_config(struct drm_crtc *crtc,
4104 struct intel_crtc_config *pipe_config)
79e53945 4105{
2c07245f 4106 struct drm_device *dev = crtc->dev;
b8cecdf5 4107 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
42db64ef 4108 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
89749350 4109
bad720ff 4110 if (HAS_PCH_SPLIT(dev)) {
2c07245f 4111 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 4112 if (pipe_config->requested_mode.clock * 3
4113 > IRONLAKE_FDI_FREQ * 4)
e29c22c0 4114 return -EINVAL;
2c07245f 4115 }
89749350 4116
f9bef081
DV		 4117 /* All interlaced capable intel hw wants timings in frames. Note though
4118 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4119 * timings, so we need to be careful not to clobber these.*/
7ae89233 4120 if (!pipe_config->timings_set)
f9bef081 4121 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 4122
8693a824
DL		 4123 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4124 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4125 */
4126 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4127 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4128 return -EINVAL;
44f46b42 4129
bd080ee5 4130 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4131 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4132 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4133 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4134 * for lvds. */
4135 pipe_config->pipe_bpp = 8*3;
4136 }
4137
42db64ef
PZ		 4138 if (IS_HASWELL(dev))
4139 hsw_compute_ips_config(intel_crtc, pipe_config);
4140
877d48d5 4141 if (pipe_config->has_pch_encoder)
42db64ef 4142 return ironlake_fdi_compute_config(intel_crtc, pipe_config);
877d48d5 4143
e29c22c0 4144 return 0;
79e53945
JB		 4145}
4146
25eb05fc
JB		 4147static int valleyview_get_display_clock_speed(struct drm_device *dev)
4148{
4149 return 400000; /* FIXME */
4150}
4151
e70236a8
JB		 4152static int i945_get_display_clock_speed(struct drm_device *dev)
4153{
4154 return 400000;
4155}
79e53945 4156
e70236a8 4157static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4158{
e70236a8
JB		 4159 return 333000;
4160}
79e53945 4161
e70236a8
JB		 4162static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4163{
4164 return 200000;
4165}
79e53945 4166
e70236a8
JB		 4167static int i915gm_get_display_clock_speed(struct drm_device *dev)
4168{
4169 u16 gcfgc = 0;
79e53945 4170
e70236a8
JB		 4171 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4172
4173 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4174 return 133000;
4175 else {
4176 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4177 case GC_DISPLAY_CLOCK_333_MHZ:
4178 return 333000;
4179 default:
4180 case GC_DISPLAY_CLOCK_190_200_MHZ:
4181 return 190000;
79e53945 4182 }
e70236a8
JB		 4183 }
4184}
4185
4186static int i865_get_display_clock_speed(struct drm_device *dev)
4187{
4188 return 266000;
4189}
4190
4191static int i855_get_display_clock_speed(struct drm_device *dev)
4192{
4193 u16 hpllcc = 0;
4194 /* Assume that the hardware is in the high speed state. This
4195 * should be the default.
4196 */
4197 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4198 case GC_CLOCK_133_200:
4199 case GC_CLOCK_100_200:
4200 return 200000;
4201 case GC_CLOCK_166_250:
4202 return 250000;
4203 case GC_CLOCK_100_133:
79e53945 4204 return 133000;
e70236a8 4205 }
79e53945 4206
e70236a8
JB		 4207 /* Shouldn't happen */
4208 return 0;
4209}
79e53945 4210
e70236a8
JB		 4211static int i830_get_display_clock_speed(struct drm_device *dev)
4212{
4213 return 133000;
79e53945
JB		 4214}
4215
2c07245f 4216static void
a65851af 4217intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4218{
a65851af
VS		 4219 while (*num > DATA_LINK_M_N_MASK ||
4220 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4221 *num >>= 1;
4222 *den >>= 1;
4223 }
4224}
4225
a65851af
VS		 4226static void compute_m_n(unsigned int m, unsigned int n,
4227 uint32_t *ret_m, uint32_t *ret_n)
4228{
4229 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4230 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4231 intel_reduce_m_n_ratio(ret_m, ret_n);
4232}
4233
e69d0bc1
DV		 4234void
4235intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4236 int pixel_clock, int link_clock,
4237 struct intel_link_m_n *m_n)
2c07245f 4238{
e69d0bc1 4239 m_n->tu = 64;
a65851af
VS		 4240
4241 compute_m_n(bits_per_pixel * pixel_clock,
4242 link_clock * nlanes * 8,
4243 &m_n->gmch_m, &m_n->gmch_n);
4244
4245 compute_m_n(pixel_clock, link_clock,
4246 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4247}
4248
a7615030
CW		 4249static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4250{
72bbe58c
KP		 4251 if (i915_panel_use_ssc >= 0)
4252 return i915_panel_use_ssc != 0;
41aa3448 4253 return dev_priv->vbt.lvds_use_ssc
435793df 4254 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4255}
4256
a0c4da24
JB		 4257static int vlv_get_refclk(struct drm_crtc *crtc)
4258{
4259 struct drm_device *dev = crtc->dev;
4260 struct drm_i915_private *dev_priv = dev->dev_private;
4261 int refclk = 27000; /* for DP & HDMI */
4262
4263 return 100000; /* only one validated so far */
4264
4265 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4266 refclk = 96000;
4267 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4268 if (intel_panel_use_ssc(dev_priv))
4269 refclk = 100000;
4270 else
4271 refclk = 96000;
4272 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4273 refclk = 100000;
4274 }
4275
4276 return refclk;
4277}
4278
c65d77d8
JB		 4279static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4280{
4281 struct drm_device *dev = crtc->dev;
4282 struct drm_i915_private *dev_priv = dev->dev_private;
4283 int refclk;
4284
a0c4da24
JB		 4285 if (IS_VALLEYVIEW(dev)) {
4286 refclk = vlv_get_refclk(crtc);
4287 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4288 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4289 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4290 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4291 refclk / 1000);
4292 } else if (!IS_GEN2(dev)) {
4293 refclk = 96000;
4294 } else {
4295 refclk = 48000;
4296 }
4297
4298 return refclk;
4299}
4300
7429e9d4
DV		 4301static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4302{
4303 return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2;
4304}
4305
4306static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4307{
4308 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4309}
4310
f47709a9 4311static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4312 intel_clock_t *reduced_clock)
4313{
f47709a9 4314 struct drm_device *dev = crtc->base.dev;
a7516a05 4315 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4316 int pipe = crtc->pipe;
a7516a05
JB		 4317 u32 fp, fp2 = 0;
4318
4319 if (IS_PINEVIEW(dev)) {
7429e9d4 4320 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4321 if (reduced_clock)
7429e9d4 4322 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4323 } else {
7429e9d4 4324 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4325 if (reduced_clock)
7429e9d4 4326 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4327 }
4328
4329 I915_WRITE(FP0(pipe), fp);
4330
f47709a9
DV		 4331 crtc->lowfreq_avail = false;
4332 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4333 reduced_clock && i915_powersave) {
4334 I915_WRITE(FP1(pipe), fp2);
f47709a9 4335 crtc->lowfreq_avail = true;
a7516a05
JB		 4336 } else {
4337 I915_WRITE(FP1(pipe), fp);
4338 }
4339}
4340
89b667f8
JB		 4341static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4342{
4343 u32 reg_val;
4344
4345 /*
4346 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4347 * and set it to a reasonable value instead.
4348 */
ae99258f 4349 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8
JB		 4350 reg_val &= 0xffffff00;
4351 reg_val |= 0x00000030;
ae99258f 4352 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4353
ae99258f 4354 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4355 reg_val &= 0x8cffffff;
4356 reg_val = 0x8c000000;
ae99258f 4357 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8 4358
ae99258f 4359 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8 4360 reg_val &= 0xffffff00;
ae99258f 4361 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4362
ae99258f 4363 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4364 reg_val &= 0x00ffffff;
4365 reg_val |= 0xb0000000;
ae99258f 4366 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4367}
4368
b551842d
DV		 4369static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4370 struct intel_link_m_n *m_n)
4371{
4372 struct drm_device *dev = crtc->base.dev;
4373 struct drm_i915_private *dev_priv = dev->dev_private;
4374 int pipe = crtc->pipe;
4375
e3b95f1e
DV		 4376 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4377 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4378 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4379 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4380}
4381
4382static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4383 struct intel_link_m_n *m_n)
4384{
4385 struct drm_device *dev = crtc->base.dev;
4386 struct drm_i915_private *dev_priv = dev->dev_private;
4387 int pipe = crtc->pipe;
4388 enum transcoder transcoder = crtc->config.cpu_transcoder;
4389
4390 if (INTEL_INFO(dev)->gen >= 5) {
4391 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4392 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4393 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4394 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4395 } else {
e3b95f1e
DV		 4396 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4397 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4398 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4399 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4400 }
4401}
4402
03afc4a2
DV		 4403static void intel_dp_set_m_n(struct intel_crtc *crtc)
4404{
4405 if (crtc->config.has_pch_encoder)
4406 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4407 else
4408 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4409}
4410
f47709a9 4411static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4412{
f47709a9 4413 struct drm_device *dev = crtc->base.dev;
a0c4da24 4414 struct drm_i915_private *dev_priv = dev->dev_private;
89b667f8
JB		 4415 struct drm_display_mode *adjusted_mode =
4416 &crtc->config.adjusted_mode;
4417 struct intel_encoder *encoder;
f47709a9 4418 int pipe = crtc->pipe;
89b667f8 4419 u32 dpll, mdiv;
a0c4da24 4420 u32 bestn, bestm1, bestm2, bestp1, bestp2;
89b667f8 4421 bool is_hdmi;
198a037f 4422 u32 coreclk, reg_val, dpll_md;
a0c4da24 4423
09153000
DV		 4424 mutex_lock(&dev_priv->dpio_lock);
4425
89b667f8 4426 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
a0c4da24 4427
f47709a9
DV		 4428 bestn = crtc->config.dpll.n;
4429 bestm1 = crtc->config.dpll.m1;
4430 bestm2 = crtc->config.dpll.m2;
4431 bestp1 = crtc->config.dpll.p1;
4432 bestp2 = crtc->config.dpll.p2;
a0c4da24 4433
89b667f8
JB		 4434 /* See eDP HDMI DPIO driver vbios notes doc */
4435
4436 /* PLL B needs special handling */
4437 if (pipe)
4438 vlv_pllb_recal_opamp(dev_priv);
4439
4440 /* Set up Tx target for periodic Rcomp update */
ae99258f 4441 vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4442
4443 /* Disable target IRef on PLL */
ae99258f 4444 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
89b667f8 4445 reg_val &= 0x00ffffff;
ae99258f 4446 vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4447
4448 /* Disable fast lock */
ae99258f 4449 vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4450
4451 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4452 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4453 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4454 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4455 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4456
4457 /*
4458 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4459 * but we don't support that).
4460 * Note: don't use the DAC post divider as it seems unstable.
4461 */
4462 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ae99258f 4463 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4464
89b667f8 4465 mdiv |= DPIO_ENABLE_CALIBRATION;
ae99258f 4466 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4467
89b667f8
JB		 4468 /* Set HBR and RBR LPF coefficients */
4469 if (adjusted_mode->clock == 162000 ||
4470 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
ae99258f 4471 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
89b667f8
JB		 4472 0x005f0021);
4473 else
ae99258f 4474 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
89b667f8
JB		 4475 0x00d0000f);
4476
4477 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4478 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4479 /* Use SSC source */
4480 if (!pipe)
ae99258f 4481 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4482 0x0df40000);
4483 else
ae99258f 4484 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4485 0x0df70000);
4486 } else { /* HDMI or VGA */
4487 /* Use bend source */
4488 if (!pipe)
ae99258f 4489 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4490 0x0df70000);
4491 else
ae99258f 4492 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4493 0x0df40000);
4494 }
a0c4da24 4495
ae99258f 4496 coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4497 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4498 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4499 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4500 coreclk |= 0x01000000;
ae99258f 4501 vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4502
ae99258f 4503 vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4504
89b667f8
JB		 4505 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4506 if (encoder->pre_pll_enable)
4507 encoder->pre_pll_enable(encoder);
2a8f64ca 4508
89b667f8
JB		 4509 /* Enable DPIO clock input */
4510 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4511 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4512 if (pipe)
4513 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
2a8f64ca 4514
89b667f8 4515 dpll |= DPLL_VCO_ENABLE;
2a8f64ca 4516 I915_WRITE(DPLL(pipe), dpll);
2a8f64ca
VP		 4517 POSTING_READ(DPLL(pipe));
4518 udelay(150);
a0c4da24 4519
89b667f8
JB		 4520 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4521 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4522
198a037f
DV		 4523 dpll_md = 0;
4524 if (crtc->config.pixel_multiplier > 1) {
4525 dpll_md = (crtc->config.pixel_multiplier - 1)
4526 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
2a8f64ca 4527 }
198a037f
DV		 4528 I915_WRITE(DPLL_MD(pipe), dpll_md);
4529 POSTING_READ(DPLL_MD(pipe));
f47709a9 4530
89b667f8
JB		 4531 if (crtc->config.has_dp_encoder)
4532 intel_dp_set_m_n(crtc);
09153000
DV		 4533
4534 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4535}
4536
f47709a9
DV		 4537static void i9xx_update_pll(struct intel_crtc *crtc,
4538 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4539 int num_connectors)
4540{
f47709a9 4541 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4542 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4543 struct intel_encoder *encoder;
f47709a9 4544 int pipe = crtc->pipe;
eb1cbe48
DV		 4545 u32 dpll;
4546 bool is_sdvo;
f47709a9 4547 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4548
f47709a9 4549 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4550
f47709a9
DV		 4551 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4552 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4553
4554 dpll = DPLL_VGA_MODE_DIS;
4555
f47709a9 4556 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4557 dpll |= DPLLB_MODE_LVDS;
4558 else
4559 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4560
198a037f
DV		 4561 if ((crtc->config.pixel_multiplier > 1) &&
4562 (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
4563 dpll |= (crtc->config.pixel_multiplier - 1)
4564 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4565 }
198a037f
DV		 4566
4567 if (is_sdvo)
4568 dpll |= DPLL_DVO_HIGH_SPEED;
4569
f47709a9 4570 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
eb1cbe48
DV		 4571 dpll |= DPLL_DVO_HIGH_SPEED;
4572
4573 /* compute bitmask from p1 value */
4574 if (IS_PINEVIEW(dev))
4575 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4576 else {
4577 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4578 if (IS_G4X(dev) && reduced_clock)
4579 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4580 }
4581 switch (clock->p2) {
4582 case 5:
4583 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4584 break;
4585 case 7:
4586 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4587 break;
4588 case 10:
4589 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4590 break;
4591 case 14:
4592 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4593 break;
4594 }
4595 if (INTEL_INFO(dev)->gen >= 4)
4596 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4597
09ede541 4598 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4599 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4600 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4601 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4602 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4603 else
4604 dpll |= PLL_REF_INPUT_DREFCLK;
4605
4606 dpll |= DPLL_VCO_ENABLE;
4607 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4608 POSTING_READ(DPLL(pipe));
4609 udelay(150);
4610
f47709a9 4611 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4612 if (encoder->pre_pll_enable)
4613 encoder->pre_pll_enable(encoder);
eb1cbe48 4614
f47709a9
DV		 4615 if (crtc->config.has_dp_encoder)
4616 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4617
4618 I915_WRITE(DPLL(pipe), dpll);
4619
4620 /* Wait for the clocks to stabilize. */
4621 POSTING_READ(DPLL(pipe));
4622 udelay(150);
4623
4624 if (INTEL_INFO(dev)->gen >= 4) {
198a037f
DV		 4625 u32 dpll_md = 0;
4626 if (crtc->config.pixel_multiplier > 1) {
4627 dpll_md = (crtc->config.pixel_multiplier - 1)
4628 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
eb1cbe48 4629 }
198a037f 4630 I915_WRITE(DPLL_MD(pipe), dpll_md);
eb1cbe48
DV		 4631 } else {
4632 /* The pixel multiplier can only be updated once the
4633 * DPLL is enabled and the clocks are stable.
4634 *
4635 * So write it again.
4636 */
4637 I915_WRITE(DPLL(pipe), dpll);
4638 }
4639}
4640
f47709a9 4641static void i8xx_update_pll(struct intel_crtc *crtc,
eb1cbe48 4642 struct drm_display_mode *adjusted_mode,
f47709a9 4643 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4644 int num_connectors)
4645{
f47709a9 4646 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4647 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4648 struct intel_encoder *encoder;
f47709a9 4649 int pipe = crtc->pipe;
eb1cbe48 4650 u32 dpll;
f47709a9 4651 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4652
f47709a9 4653 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4654
eb1cbe48
DV		 4655 dpll = DPLL_VGA_MODE_DIS;
4656
f47709a9 4657 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4658 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4659 } else {
4660 if (clock->p1 == 2)
4661 dpll |= PLL_P1_DIVIDE_BY_TWO;
4662 else
4663 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4664 if (clock->p2 == 4)
4665 dpll |= PLL_P2_DIVIDE_BY_4;
4666 }
4667
f47709a9 4668 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4669 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4670 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4671 else
4672 dpll |= PLL_REF_INPUT_DREFCLK;
4673
4674 dpll |= DPLL_VCO_ENABLE;
4675 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4676 POSTING_READ(DPLL(pipe));
4677 udelay(150);
4678
f47709a9 4679 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4680 if (encoder->pre_pll_enable)
4681 encoder->pre_pll_enable(encoder);
eb1cbe48 4682
5b5896e4
DV		 4683 I915_WRITE(DPLL(pipe), dpll);
4684
4685 /* Wait for the clocks to stabilize. */
4686 POSTING_READ(DPLL(pipe));
4687 udelay(150);
4688
eb1cbe48
DV		 4689 /* The pixel multiplier can only be updated once the
4690 * DPLL is enabled and the clocks are stable.
4691 *
4692 * So write it again.
4693 */
4694 I915_WRITE(DPLL(pipe), dpll);
4695}
4696
b0e77b9c
PZ		 4697static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4698 struct drm_display_mode *mode,
4699 struct drm_display_mode *adjusted_mode)
4700{
4701 struct drm_device *dev = intel_crtc->base.dev;
4702 struct drm_i915_private *dev_priv = dev->dev_private;
4703 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4704 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4d8a62ea
DV		 4705 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4706
4707 /* We need to be careful not to changed the adjusted mode, for otherwise
4708 * the hw state checker will get angry at the mismatch. */
4709 crtc_vtotal = adjusted_mode->crtc_vtotal;
4710 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4711
4712 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4713 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4714 crtc_vtotal -= 1;
4715 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4716 vsyncshift = adjusted_mode->crtc_hsync_start
4717 - adjusted_mode->crtc_htotal / 2;
4718 } else {
4719 vsyncshift = 0;
4720 }
4721
4722 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4723 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4724
fe2b8f9d 4725 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4726 (adjusted_mode->crtc_hdisplay - 1) |
4727 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4728 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4729 (adjusted_mode->crtc_hblank_start - 1) |
4730 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4731 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4732 (adjusted_mode->crtc_hsync_start - 1) |
4733 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4734
fe2b8f9d 4735 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4736 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4737 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4738 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4739 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4740 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4741 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4742 (adjusted_mode->crtc_vsync_start - 1) |
4743 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4744
b5e508d4
PZ		 4745 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4746 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4747 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4748 * bits. */
4749 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4750 (pipe == PIPE_B || pipe == PIPE_C))
4751 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4752
b0e77b9c
PZ		 4753 /* pipesrc controls the size that is scaled from, which should
4754 * always be the user's requested size.
4755 */
4756 I915_WRITE(PIPESRC(pipe),
4757 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4758}
4759
1bd1bd80
DV		 4760static void intel_get_pipe_timings(struct intel_crtc *crtc,
4761 struct intel_crtc_config *pipe_config)
4762{
4763 struct drm_device *dev = crtc->base.dev;
4764 struct drm_i915_private *dev_priv = dev->dev_private;
4765 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4766 uint32_t tmp;
4767
4768 tmp = I915_READ(HTOTAL(cpu_transcoder));
4769 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4770 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4771 tmp = I915_READ(HBLANK(cpu_transcoder));
4772 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4773 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4774 tmp = I915_READ(HSYNC(cpu_transcoder));
4775 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4776 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4777
4778 tmp = I915_READ(VTOTAL(cpu_transcoder));
4779 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4780 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4781 tmp = I915_READ(VBLANK(cpu_transcoder));
4782 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4783 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4784 tmp = I915_READ(VSYNC(cpu_transcoder));
4785 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4786 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4787
4788 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4789 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4790 pipe_config->adjusted_mode.crtc_vtotal += 1;
4791 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4792 }
4793
4794 tmp = I915_READ(PIPESRC(crtc->pipe));
4795 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4796 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4797}
4798
84b046f3
DV		 4799static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4800{
4801 struct drm_device *dev = intel_crtc->base.dev;
4802 struct drm_i915_private *dev_priv = dev->dev_private;
4803 uint32_t pipeconf;
4804
4805 pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4806
4807 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4808 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4809 * core speed.
4810 *
4811 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4812 * pipe == 0 check?
4813 */
4814 if (intel_crtc->config.requested_mode.clock >
4815 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4816 pipeconf |= PIPECONF_DOUBLE_WIDE;
4817 else
4818 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4819 }
4820
ff9ce46e
DV		 4821 /* only g4x and later have fancy bpc/dither controls */
4822 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4823 pipeconf &= ~(PIPECONF_BPC_MASK |
4824 PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4825
4826 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4827 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4828 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4829 PIPECONF_DITHER_TYPE_SP;
84b046f3 4830
ff9ce46e
DV		 4831 switch (intel_crtc->config.pipe_bpp) {
4832 case 18:
4833 pipeconf |= PIPECONF_6BPC;
4834 break;
4835 case 24:
4836 pipeconf |= PIPECONF_8BPC;
4837 break;
4838 case 30:
4839 pipeconf |= PIPECONF_10BPC;
4840 break;
4841 default:
4842 /* Case prevented by intel_choose_pipe_bpp_dither. */
4843 BUG();
84b046f3
DV		 4844 }
4845 }
4846
4847 if (HAS_PIPE_CXSR(dev)) {
4848 if (intel_crtc->lowfreq_avail) {
4849 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4850 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4851 } else {
4852 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4853 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4854 }
4855 }
4856
4857 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4858 if (!IS_GEN2(dev) &&
4859 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4860 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4861 else
4862 pipeconf |= PIPECONF_PROGRESSIVE;
4863
9c8e09b7
VS		 4864 if (IS_VALLEYVIEW(dev)) {
4865 if (intel_crtc->config.limited_color_range)
4866 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4867 else
4868 pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4869 }
4870
84b046f3
DV		 4871 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4872 POSTING_READ(PIPECONF(intel_crtc->pipe));
4873}
4874
f564048e 4875static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4876 int x, int y,
94352cf9 4877 struct drm_framebuffer *fb)
79e53945
JB		 4878{
4879 struct drm_device *dev = crtc->dev;
4880 struct drm_i915_private *dev_priv = dev->dev_private;
4881 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 4882 struct drm_display_mode *adjusted_mode =
4883 &intel_crtc->config.adjusted_mode;
4884 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4885 int pipe = intel_crtc->pipe;
80824003 4886 int plane = intel_crtc->plane;
c751ce4f 4887 int refclk, num_connectors = 0;
652c393a 4888 intel_clock_t clock, reduced_clock;
84b046f3 4889 u32 dspcntr;
a16af721
DV		 4890 bool ok, has_reduced_clock = false;
4891 bool is_lvds = false;
5eddb70b 4892 struct intel_encoder *encoder;
d4906093 4893 const intel_limit_t *limit;
5c3b82e2 4894 int ret;
79e53945 4895
6c2b7c12 4896 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4897 switch (encoder->type) {
79e53945
JB		 4898 case INTEL_OUTPUT_LVDS:
4899 is_lvds = true;
4900 break;
79e53945 4901 }
43565a06 4902
c751ce4f 4903 num_connectors++;
79e53945
JB		 4904 }
4905
c65d77d8 4906 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4907
d4906093
ML		 4908 /*
4909 * Returns a set of divisors for the desired target clock with the given
4910 * refclk, or FALSE. The returned values represent the clock equation:
4911 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4912 */
1b894b59 4913 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4914 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4915 &clock);
79e53945
JB		 4916 if (!ok) {
4917 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4918 return -EINVAL;
79e53945
JB		 4919 }
4920
cda4b7d3 4921 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4922 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4923
ddc9003c 4924 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4925 /*
4926 * Ensure we match the reduced clock's P to the target clock.
4927 * If the clocks don't match, we can't switch the display clock
4928 * by using the FP0/FP1. In such case we will disable the LVDS
4929 * downclock feature.
4930 */
ddc9003c 4931 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4932 dev_priv->lvds_downclock,
4933 refclk,
cec2f356 4934 &clock,
5eddb70b 4935 &reduced_clock);
7026d4ac 4936 }
f47709a9
DV		 4937 /* Compat-code for transition, will disappear. */
4938 if (!intel_crtc->config.clock_set) {
4939 intel_crtc->config.dpll.n = clock.n;
4940 intel_crtc->config.dpll.m1 = clock.m1;
4941 intel_crtc->config.dpll.m2 = clock.m2;
4942 intel_crtc->config.dpll.p1 = clock.p1;
4943 intel_crtc->config.dpll.p2 = clock.p2;
4944 }
7026d4ac 4945
eb1cbe48 4946 if (IS_GEN2(dev))
f47709a9 4947 i8xx_update_pll(intel_crtc, adjusted_mode,
2a8f64ca
VP		 4948 has_reduced_clock ? &reduced_clock : NULL,
4949 num_connectors);
a0c4da24 4950 else if (IS_VALLEYVIEW(dev))
f47709a9 4951 vlv_update_pll(intel_crtc);
79e53945 4952 else
f47709a9 4953 i9xx_update_pll(intel_crtc,
eb1cbe48 4954 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4955 num_connectors);
79e53945 4956
79e53945
JB		 4957 /* Set up the display plane register */
4958 dspcntr = DISPPLANE_GAMMA_ENABLE;
4959
da6ecc5d
JB		 4960 if (!IS_VALLEYVIEW(dev)) {
4961 if (pipe == 0)
4962 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4963 else
4964 dspcntr |= DISPPLANE_SEL_PIPE_B;
4965 }
79e53945 4966
b0e77b9c 4967 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4968
4969 /* pipesrc and dspsize control the size that is scaled from,
4970 * which should always be the user's requested size.
79e53945 4971 */
929c77fb
EA		 4972 I915_WRITE(DSPSIZE(plane),
4973 ((mode->vdisplay - 1) << 16) |
4974 (mode->hdisplay - 1));
4975 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4976
84b046f3
DV		 4977 i9xx_set_pipeconf(intel_crtc);
4978
f564048e
EA		 4979 I915_WRITE(DSPCNTR(plane), dspcntr);
4980 POSTING_READ(DSPCNTR(plane));
4981
94352cf9 4982 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4983
4984 intel_update_watermarks(dev);
4985
f564048e
EA		 4986 return ret;
4987}
4988
2fa2fe9a
DV		 4989static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4990 struct intel_crtc_config *pipe_config)
4991{
4992 struct drm_device *dev = crtc->base.dev;
4993 struct drm_i915_private *dev_priv = dev->dev_private;
4994 uint32_t tmp;
4995
4996 tmp = I915_READ(PFIT_CONTROL);
4997
4998 if (INTEL_INFO(dev)->gen < 4) {
4999 if (crtc->pipe != PIPE_B)
5000 return;
5001
5002 /* gen2/3 store dither state in pfit control, needs to match */
5003 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
5004 } else {
5005 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5006 return;
5007 }
5008
5009 if (!(tmp & PFIT_ENABLE))
5010 return;
5011
5012 pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
5013 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5014 if (INTEL_INFO(dev)->gen < 5)
5015 pipe_config->gmch_pfit.lvds_border_bits =
5016 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5017}
5018
0e8ffe1b
DV		 5019static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5020 struct intel_crtc_config *pipe_config)
5021{
5022 struct drm_device *dev = crtc->base.dev;
5023 struct drm_i915_private *dev_priv = dev->dev_private;
5024 uint32_t tmp;
5025
eccb140b
DV		 5026 pipe_config->cpu_transcoder = crtc->pipe;
5027
0e8ffe1b
DV		 5028 tmp = I915_READ(PIPECONF(crtc->pipe));
5029 if (!(tmp & PIPECONF_ENABLE))
5030 return false;
5031
1bd1bd80
DV		 5032 intel_get_pipe_timings(crtc, pipe_config);
5033
2fa2fe9a
DV		 5034 i9xx_get_pfit_config(crtc, pipe_config);
5035
0e8ffe1b
DV		 5036 return true;
5037}
5038
dde86e2d 5039static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5040{
5041 struct drm_i915_private *dev_priv = dev->dev_private;
5042 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5043 struct intel_encoder *encoder;
74cfd7ac 5044 u32 val, final;
13d83a67 5045 bool has_lvds = false;
199e5d79 5046 bool has_cpu_edp = false;
199e5d79 5047 bool has_panel = false;
99eb6a01
KP		 5048 bool has_ck505 = false;
5049 bool can_ssc = false;
13d83a67
JB		 5050
5051 /* We need to take the global config into account */
199e5d79
KP		 5052 list_for_each_entry(encoder, &mode_config->encoder_list,
5053 base.head) {
5054 switch (encoder->type) {
5055 case INTEL_OUTPUT_LVDS:
5056 has_panel = true;
5057 has_lvds = true;
5058 break;
5059 case INTEL_OUTPUT_EDP:
5060 has_panel = true;
2de6905f 5061 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5062 has_cpu_edp = true;
5063 break;
13d83a67
JB		 5064 }
5065 }
5066
99eb6a01 5067 if (HAS_PCH_IBX(dev)) {
41aa3448 5068 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5069 can_ssc = has_ck505;
5070 } else {
5071 has_ck505 = false;
5072 can_ssc = true;
5073 }
5074
2de6905f
ID		 5075 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5076 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5077
5078 /* Ironlake: try to setup display ref clock before DPLL
5079 * enabling. This is only under driver's control after
5080 * PCH B stepping, previous chipset stepping should be
5081 * ignoring this setting.
5082 */
74cfd7ac
CW		 5083 val = I915_READ(PCH_DREF_CONTROL);
5084
5085 /* As we must carefully and slowly disable/enable each source in turn,
5086 * compute the final state we want first and check if we need to
5087 * make any changes at all.
5088 */
5089 final = val;
5090 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5091 if (has_ck505)
5092 final |= DREF_NONSPREAD_CK505_ENABLE;
5093 else
5094 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5095
5096 final &= ~DREF_SSC_SOURCE_MASK;
5097 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5098 final &= ~DREF_SSC1_ENABLE;
5099
5100 if (has_panel) {
5101 final |= DREF_SSC_SOURCE_ENABLE;
5102
5103 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5104 final |= DREF_SSC1_ENABLE;
5105
5106 if (has_cpu_edp) {
5107 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5108 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5109 else
5110 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5111 } else
5112 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5113 } else {
5114 final |= DREF_SSC_SOURCE_DISABLE;
5115 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5116 }
5117
5118 if (final == val)
5119 return;
5120
13d83a67 5121 /* Always enable nonspread source */
74cfd7ac 5122 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5123
99eb6a01 5124 if (has_ck505)
74cfd7ac 5125 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5126 else
74cfd7ac 5127 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5128
199e5d79 5129 if (has_panel) {
74cfd7ac
CW		 5130 val &= ~DREF_SSC_SOURCE_MASK;
5131 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5132
199e5d79 5133 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5134 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5135 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5136 val |= DREF_SSC1_ENABLE;
e77166b5 5137 } else
74cfd7ac 5138 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5139
5140 /* Get SSC going before enabling the outputs */
74cfd7ac 5141 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5142 POSTING_READ(PCH_DREF_CONTROL);
5143 udelay(200);
5144
74cfd7ac 5145 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5146
5147 /* Enable CPU source on CPU attached eDP */
199e5d79 5148 if (has_cpu_edp) {
99eb6a01 5149 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5150 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5151 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5152 }
13d83a67 5153 else
74cfd7ac 5154 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5155 } else
74cfd7ac 5156 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5157
74cfd7ac 5158 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5159 POSTING_READ(PCH_DREF_CONTROL);
5160 udelay(200);
5161 } else {
5162 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5163
74cfd7ac 5164 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5165
5166 /* Turn off CPU output */
74cfd7ac 5167 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5168
74cfd7ac 5169 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5170 POSTING_READ(PCH_DREF_CONTROL);
5171 udelay(200);
5172
5173 /* Turn off the SSC source */
74cfd7ac
CW		 5174 val &= ~DREF_SSC_SOURCE_MASK;
5175 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5176
5177 /* Turn off SSC1 */
74cfd7ac 5178 val &= ~DREF_SSC1_ENABLE;
199e5d79 5179
74cfd7ac 5180 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5181 POSTING_READ(PCH_DREF_CONTROL);
5182 udelay(200);
5183 }
74cfd7ac
CW		 5184
5185 BUG_ON(val != final);
13d83a67
JB		 5186}
5187
dde86e2d
PZ		 5188/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5189static void lpt_init_pch_refclk(struct drm_device *dev)
5190{
5191 struct drm_i915_private *dev_priv = dev->dev_private;
5192 struct drm_mode_config *mode_config = &dev->mode_config;
5193 struct intel_encoder *encoder;
5194 bool has_vga = false;
5195 bool is_sdv = false;
5196 u32 tmp;
5197
5198 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5199 switch (encoder->type) {
5200 case INTEL_OUTPUT_ANALOG:
5201 has_vga = true;
5202 break;
5203 }
5204 }
5205
5206 if (!has_vga)
5207 return;
5208
c00db246
DV		 5209 mutex_lock(&dev_priv->dpio_lock);
5210
dde86e2d
PZ		 5211 /* XXX: Rip out SDV support once Haswell ships for real. */
5212 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5213 is_sdv = true;
5214
5215 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5216 tmp &= ~SBI_SSCCTL_DISABLE;
5217 tmp |= SBI_SSCCTL_PATHALT;
5218 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5219
5220 udelay(24);
5221
5222 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5223 tmp &= ~SBI_SSCCTL_PATHALT;
5224 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5225
5226 if (!is_sdv) {
5227 tmp = I915_READ(SOUTH_CHICKEN2);
5228 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5229 I915_WRITE(SOUTH_CHICKEN2, tmp);
5230
5231 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5232 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5233 DRM_ERROR("FDI mPHY reset assert timeout\n");
5234
5235 tmp = I915_READ(SOUTH_CHICKEN2);
5236 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5237 I915_WRITE(SOUTH_CHICKEN2, tmp);
5238
5239 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5240 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5241 100))
5242 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5243 }
5244
5245 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5246 tmp &= ~(0xFF << 24);
5247 tmp |= (0x12 << 24);
5248 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5249
dde86e2d
PZ		 5250 if (is_sdv) {
5251 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5252 tmp |= 0x7FFF;
5253 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5254 }
5255
5256 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5257 tmp |= (1 << 11);
5258 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5259
5260 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5261 tmp |= (1 << 11);
5262 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5263
5264 if (is_sdv) {
5265 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5266 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5267 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5268
5269 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5270 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5271 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5272
5273 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5274 tmp |= (0x3F << 8);
5275 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5276
5277 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5278 tmp |= (0x3F << 8);
5279 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5280 }
5281
5282 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5283 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5284 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5285
5286 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5287 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5288 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5289
5290 if (!is_sdv) {
5291 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5292 tmp &= ~(7 << 13);
5293 tmp |= (5 << 13);
5294 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5295
5296 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5297 tmp &= ~(7 << 13);
5298 tmp |= (5 << 13);
5299 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5300 }
5301
5302 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5303 tmp &= ~0xFF;
5304 tmp |= 0x1C;
5305 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5306
5307 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5308 tmp &= ~0xFF;
5309 tmp |= 0x1C;
5310 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5311
5312 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5313 tmp &= ~(0xFF << 16);
5314 tmp |= (0x1C << 16);
5315 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5316
5317 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5318 tmp &= ~(0xFF << 16);
5319 tmp |= (0x1C << 16);
5320 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5321
5322 if (!is_sdv) {
5323 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5324 tmp |= (1 << 27);
5325 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5326
5327 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5328 tmp |= (1 << 27);
5329 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5330
5331 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5332 tmp &= ~(0xF << 28);
5333 tmp |= (4 << 28);
5334 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5335
5336 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5337 tmp &= ~(0xF << 28);
5338 tmp |= (4 << 28);
5339 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5340 }
5341
5342 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5343 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5344 tmp |= SBI_DBUFF0_ENABLE;
5345 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5346
5347 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5348}
5349
5350/*
5351 * Initialize reference clocks when the driver loads
5352 */
5353void intel_init_pch_refclk(struct drm_device *dev)
5354{
5355 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5356 ironlake_init_pch_refclk(dev);
5357 else if (HAS_PCH_LPT(dev))
5358 lpt_init_pch_refclk(dev);
5359}
5360
d9d444cb
JB		 5361static int ironlake_get_refclk(struct drm_crtc *crtc)
5362{
5363 struct drm_device *dev = crtc->dev;
5364 struct drm_i915_private *dev_priv = dev->dev_private;
5365 struct intel_encoder *encoder;
d9d444cb
JB		 5366 int num_connectors = 0;
5367 bool is_lvds = false;
5368
6c2b7c12 5369 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5370 switch (encoder->type) {
5371 case INTEL_OUTPUT_LVDS:
5372 is_lvds = true;
5373 break;
d9d444cb
JB		 5374 }
5375 num_connectors++;
5376 }
5377
5378 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5379 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5380 dev_priv->vbt.lvds_ssc_freq);
5381 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5382 }
5383
5384 return 120000;
5385}
5386
6ff93609 5387static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5388{
c8203565 5389 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5390 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5391 int pipe = intel_crtc->pipe;
c8203565
PZ		 5392 uint32_t val;
5393
5394 val = I915_READ(PIPECONF(pipe));
5395
dfd07d72 5396 val &= ~PIPECONF_BPC_MASK;
965e0c48 5397 switch (intel_crtc->config.pipe_bpp) {
c8203565 5398 case 18:
dfd07d72 5399 val |= PIPECONF_6BPC;
c8203565
PZ		 5400 break;
5401 case 24:
dfd07d72 5402 val |= PIPECONF_8BPC;
c8203565
PZ		 5403 break;
5404 case 30:
dfd07d72 5405 val |= PIPECONF_10BPC;
c8203565
PZ		 5406 break;
5407 case 36:
dfd07d72 5408 val |= PIPECONF_12BPC;
c8203565
PZ		 5409 break;
5410 default:
cc769b62
PZ		 5411 /* Case prevented by intel_choose_pipe_bpp_dither. */
5412 BUG();
c8203565
PZ		 5413 }
5414
5415 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
d8b32247 5416 if (intel_crtc->config.dither)
c8203565
PZ		 5417 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5418
5419 val &= ~PIPECONF_INTERLACE_MASK;
6ff93609 5420 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5421 val |= PIPECONF_INTERLACED_ILK;
5422 else
5423 val |= PIPECONF_PROGRESSIVE;
5424
50f3b016 5425 if (intel_crtc->config.limited_color_range)
3685a8f3
VS		 5426 val |= PIPECONF_COLOR_RANGE_SELECT;
5427 else
5428 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5429
c8203565
PZ		 5430 I915_WRITE(PIPECONF(pipe), val);
5431 POSTING_READ(PIPECONF(pipe));
5432}
5433
86d3efce
VS		 5434/*
5435 * Set up the pipe CSC unit.
5436 *
5437 * Currently only full range RGB to limited range RGB conversion
5438 * is supported, but eventually this should handle various
5439 * RGB<->YCbCr scenarios as well.
5440 */
50f3b016 5441static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5442{
5443 struct drm_device *dev = crtc->dev;
5444 struct drm_i915_private *dev_priv = dev->dev_private;
5445 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5446 int pipe = intel_crtc->pipe;
5447 uint16_t coeff = 0x7800; /* 1.0 */
5448
5449 /*
5450 * TODO: Check what kind of values actually come out of the pipe
5451 * with these coeff/postoff values and adjust to get the best
5452 * accuracy. Perhaps we even need to take the bpc value into
5453 * consideration.
5454 */
5455
50f3b016 5456 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5457 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5458
5459 /*
5460 * GY/GU and RY/RU should be the other way around according
5461 * to BSpec, but reality doesn't agree. Just set them up in
5462 * a way that results in the correct picture.
5463 */
5464 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5465 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5466
5467 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5468 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5469
5470 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5471 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5472
5473 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5474 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5475 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5476
5477 if (INTEL_INFO(dev)->gen > 6) {
5478 uint16_t postoff = 0;
5479
50f3b016 5480 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5481 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5482
5483 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5484 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5485 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5486
5487 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5488 } else {
5489 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5490
50f3b016 5491 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5492 mode |= CSC_BLACK_SCREEN_OFFSET;
5493
5494 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5495 }
5496}
5497
6ff93609 5498static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5499{
5500 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5501 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5502 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5503 uint32_t val;
5504
702e7a56 5505 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5506
5507 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
d8b32247 5508 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5509 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5510
5511 val &= ~PIPECONF_INTERLACE_MASK_HSW;
6ff93609 5512 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5513 val |= PIPECONF_INTERLACED_ILK;
5514 else
5515 val |= PIPECONF_PROGRESSIVE;
5516
702e7a56
PZ		 5517 I915_WRITE(PIPECONF(cpu_transcoder), val);
5518 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5519}
5520
6591c6e4
PZ		 5521static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5522 struct drm_display_mode *adjusted_mode,
5523 intel_clock_t *clock,
5524 bool *has_reduced_clock,
5525 intel_clock_t *reduced_clock)
5526{
5527 struct drm_device *dev = crtc->dev;
5528 struct drm_i915_private *dev_priv = dev->dev_private;
5529 struct intel_encoder *intel_encoder;
5530 int refclk;
d4906093 5531 const intel_limit_t *limit;
a16af721 5532 bool ret, is_lvds = false;
79e53945 5533
6591c6e4
PZ		 5534 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5535 switch (intel_encoder->type) {
79e53945
JB		 5536 case INTEL_OUTPUT_LVDS:
5537 is_lvds = true;
5538 break;
79e53945
JB		 5539 }
5540 }
5541
d9d444cb 5542 refclk = ironlake_get_refclk(crtc);
79e53945 5543
d4906093
ML		 5544 /*
5545 * Returns a set of divisors for the desired target clock with the given
5546 * refclk, or FALSE. The returned values represent the clock equation:
5547 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5548 */
1b894b59 5549 limit = intel_limit(crtc, refclk);
6591c6e4
PZ		 5550 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5551 clock);
5552 if (!ret)
5553 return false;
cda4b7d3 5554
ddc9003c 5555 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5556 /*
5557 * Ensure we match the reduced clock's P to the target clock.
5558 * If the clocks don't match, we can't switch the display clock
5559 * by using the FP0/FP1. In such case we will disable the LVDS
5560 * downclock feature.
5561 */
6591c6e4
PZ		 5562 *has_reduced_clock = limit->find_pll(limit, crtc,
5563 dev_priv->lvds_downclock,
5564 refclk,
5565 clock,
5566 reduced_clock);
652c393a 5567 }
61e9653f 5568
6591c6e4
PZ		 5569 return true;
5570}
5571
01a415fd
DV		 5572static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5573{
5574 struct drm_i915_private *dev_priv = dev->dev_private;
5575 uint32_t temp;
5576
5577 temp = I915_READ(SOUTH_CHICKEN1);
5578 if (temp & FDI_BC_BIFURCATION_SELECT)
5579 return;
5580
5581 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5582 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5583
5584 temp |= FDI_BC_BIFURCATION_SELECT;
5585 DRM_DEBUG_KMS("enabling fdi C rx\n");
5586 I915_WRITE(SOUTH_CHICKEN1, temp);
5587 POSTING_READ(SOUTH_CHICKEN1);
5588}
5589
ebfd86fd
DV		 5590static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5591{
5592 struct drm_device *dev = intel_crtc->base.dev;
5593 struct drm_i915_private *dev_priv = dev->dev_private;
5594
5595 switch (intel_crtc->pipe) {
5596 case PIPE_A:
5597 break;
5598 case PIPE_B:
5599 if (intel_crtc->config.fdi_lanes > 2)
5600 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5601 else
5602 cpt_enable_fdi_bc_bifurcation(dev);
5603
5604 break;
5605 case PIPE_C:
01a415fd
DV		 5606 cpt_enable_fdi_bc_bifurcation(dev);
5607
ebfd86fd 5608 break;
01a415fd
DV		 5609 default:
5610 BUG();
5611 }
5612}
5613
d4b1931c
PZ		 5614int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5615{
5616 /*
5617 * Account for spread spectrum to avoid
5618 * oversubscribing the link. Max center spread
5619 * is 2.5%; use 5% for safety's sake.
5620 */
5621 u32 bps = target_clock * bpp * 21 / 20;
5622 return bps / (link_bw * 8) + 1;
5623}
5624
7429e9d4
DV		 5625static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5626{
5627 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5628}
5629
de13a2e3 5630static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5631 u32 *fp,
9a7c7890 5632 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5633{
de13a2e3 5634 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5635 struct drm_device *dev = crtc->dev;
5636 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5637 struct intel_encoder *intel_encoder;
5638 uint32_t dpll;
6cc5f341 5639 int factor, num_connectors = 0;
09ede541 5640 bool is_lvds = false, is_sdvo = false;
79e53945 5641
de13a2e3
PZ		 5642 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5643 switch (intel_encoder->type) {
79e53945
JB		 5644 case INTEL_OUTPUT_LVDS:
5645 is_lvds = true;
5646 break;
5647 case INTEL_OUTPUT_SDVO:
7d57382e 5648 case INTEL_OUTPUT_HDMI:
79e53945
JB		 5649 is_sdvo = true;
5650 break;
79e53945 5651 }
43565a06 5652
c751ce4f 5653 num_connectors++;
79e53945 5654 }
79e53945 5655
c1858123 5656 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5657 factor = 21;
5658 if (is_lvds) {
5659 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5660 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5661 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5662 factor = 25;
09ede541 5663 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5664 factor = 20;
c1858123 5665
7429e9d4 5666 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5667 *fp |= FP_CB_TUNE;
2c07245f 5668
9a7c7890
DV		 5669 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5670 *fp2 |= FP_CB_TUNE;
5671
5eddb70b 5672 dpll = 0;
2c07245f 5673
a07d6787
EA		 5674 if (is_lvds)
5675 dpll |= DPLLB_MODE_LVDS;
5676 else
5677 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f
DV		 5678
5679 if (intel_crtc->config.pixel_multiplier > 1) {
5680 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5681 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
a07d6787 5682 }
198a037f
DV		 5683
5684 if (is_sdvo)
5685 dpll |= DPLL_DVO_HIGH_SPEED;
9566e9af 5686 if (intel_crtc->config.has_dp_encoder)
a07d6787 5687 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5688
a07d6787 5689 /* compute bitmask from p1 value */
7429e9d4 5690 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5691 /* also FPA1 */
7429e9d4 5692 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5693
7429e9d4 5694 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5695 case 5:
5696 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5697 break;
5698 case 7:
5699 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5700 break;
5701 case 10:
5702 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5703 break;
5704 case 14:
5705 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5706 break;
79e53945
JB		 5707 }
5708
b4c09f3b 5709 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5710 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5711 else
5712 dpll |= PLL_REF_INPUT_DREFCLK;
5713
de13a2e3
PZ		 5714 return dpll;
5715}
5716
5717static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5718 int x, int y,
5719 struct drm_framebuffer *fb)
5720{
5721 struct drm_device *dev = crtc->dev;
5722 struct drm_i915_private *dev_priv = dev->dev_private;
5723 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5724 struct drm_display_mode *adjusted_mode =
5725 &intel_crtc->config.adjusted_mode;
5726 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
de13a2e3
PZ		 5727 int pipe = intel_crtc->pipe;
5728 int plane = intel_crtc->plane;
5729 int num_connectors = 0;
5730 intel_clock_t clock, reduced_clock;
cbbab5bd 5731 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5732 bool ok, has_reduced_clock = false;
8b47047b 5733 bool is_lvds = false;
de13a2e3 5734 struct intel_encoder *encoder;
de13a2e3 5735 int ret;
de13a2e3
PZ		 5736
5737 for_each_encoder_on_crtc(dev, crtc, encoder) {
5738 switch (encoder->type) {
5739 case INTEL_OUTPUT_LVDS:
5740 is_lvds = true;
5741 break;
de13a2e3
PZ		 5742 }
5743
5744 num_connectors++;
a07d6787 5745 }
79e53945 5746
5dc5298b
PZ		 5747 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5748 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5749
de13a2e3
PZ		 5750 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5751 &has_reduced_clock, &reduced_clock);
5752 if (!ok) {
5753 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5754 return -EINVAL;
79e53945 5755 }
f47709a9
DV		 5756 /* Compat-code for transition, will disappear. */
5757 if (!intel_crtc->config.clock_set) {
5758 intel_crtc->config.dpll.n = clock.n;
5759 intel_crtc->config.dpll.m1 = clock.m1;
5760 intel_crtc->config.dpll.m2 = clock.m2;
5761 intel_crtc->config.dpll.p1 = clock.p1;
5762 intel_crtc->config.dpll.p2 = clock.p2;
5763 }
79e53945 5764
de13a2e3
PZ		 5765 /* Ensure that the cursor is valid for the new mode before changing... */
5766 intel_crtc_update_cursor(crtc, true);
5767
5dc5298b 5768 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5769 if (intel_crtc->config.has_pch_encoder) {
ee7b9f93 5770 struct intel_pch_pll *pll;
4b645f14 5771
7429e9d4 5772 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5773 if (has_reduced_clock)
7429e9d4 5774 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5775
7429e9d4 5776 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5777 &fp, &reduced_clock,
5778 has_reduced_clock ? &fp2 : NULL);
5779
ee7b9f93
JB		 5780 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5781 if (pll == NULL) {
84f44ce7
VS		 5782 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5783 pipe_name(pipe));
4b645f14
JB		 5784 return -EINVAL;
5785 }
ee7b9f93
JB		 5786 } else
5787 intel_put_pch_pll(intel_crtc);
79e53945 5788
03afc4a2
DV		 5789 if (intel_crtc->config.has_dp_encoder)
5790 intel_dp_set_m_n(intel_crtc);
79e53945 5791
dafd226c
DV		 5792 for_each_encoder_on_crtc(dev, crtc, encoder)
5793 if (encoder->pre_pll_enable)
5794 encoder->pre_pll_enable(encoder);
79e53945 5795
ee7b9f93
JB		 5796 if (intel_crtc->pch_pll) {
5797 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5798
32f9d658 5799 /* Wait for the clocks to stabilize. */
ee7b9f93 5800 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5801 udelay(150);
5802
8febb297
EA		 5803 /* The pixel multiplier can only be updated once the
5804 * DPLL is enabled and the clocks are stable.
5805 *
5806 * So write it again.
5807 */
ee7b9f93 5808 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5809 }
79e53945 5810
5eddb70b 5811 intel_crtc->lowfreq_avail = false;
ee7b9f93 5812 if (intel_crtc->pch_pll) {
4b645f14 5813 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5814 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5815 intel_crtc->lowfreq_avail = true;
4b645f14 5816 } else {
ee7b9f93 5817 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5818 }
5819 }
5820
b0e77b9c 5821 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b 5822
ca3a0ff8 5823 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5824 intel_cpu_transcoder_set_m_n(intel_crtc,
5825 &intel_crtc->config.fdi_m_n);
5826 }
2c07245f 5827
ebfd86fd
DV		 5828 if (IS_IVYBRIDGE(dev))
5829 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
2c07245f 5830
6ff93609 5831 ironlake_set_pipeconf(crtc);
79e53945 5832
a1f9e77e
PZ		 5833 /* Set up the display plane register */
5834 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5835 POSTING_READ(DSPCNTR(plane));
79e53945 5836
94352cf9 5837 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5838
5839 intel_update_watermarks(dev);
5840
1857e1da 5841 return ret;
79e53945
JB		 5842}
5843
72419203
DV		 5844static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5845 struct intel_crtc_config *pipe_config)
5846{
5847 struct drm_device *dev = crtc->base.dev;
5848 struct drm_i915_private *dev_priv = dev->dev_private;
5849 enum transcoder transcoder = pipe_config->cpu_transcoder;
5850
5851 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5852 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5853 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5854 & ~TU_SIZE_MASK;
5855 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5856 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5857 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5858}
5859
2fa2fe9a
DV		 5860static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5861 struct intel_crtc_config *pipe_config)
5862{
5863 struct drm_device *dev = crtc->base.dev;
5864 struct drm_i915_private *dev_priv = dev->dev_private;
5865 uint32_t tmp;
5866
5867 tmp = I915_READ(PF_CTL(crtc->pipe));
5868
5869 if (tmp & PF_ENABLE) {
5870 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5871 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5872 }
5873}
5874
0e8ffe1b
DV		 5875static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5876 struct intel_crtc_config *pipe_config)
5877{
5878 struct drm_device *dev = crtc->base.dev;
5879 struct drm_i915_private *dev_priv = dev->dev_private;
5880 uint32_t tmp;
5881
eccb140b
DV		 5882 pipe_config->cpu_transcoder = crtc->pipe;
5883
0e8ffe1b
DV		 5884 tmp = I915_READ(PIPECONF(crtc->pipe));
5885 if (!(tmp & PIPECONF_ENABLE))
5886 return false;
5887
ab9412ba 5888 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
88adfff1
DV		 5889 pipe_config->has_pch_encoder = true;
5890
627eb5a3
DV		 5891 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5892 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5893 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5894
5895 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 5896 }
5897
1bd1bd80
DV		 5898 intel_get_pipe_timings(crtc, pipe_config);
5899
2fa2fe9a
DV		 5900 ironlake_get_pfit_config(crtc, pipe_config);
5901
0e8ffe1b
DV		 5902 return true;
5903}
5904
d6dd9eb1
DV		 5905static void haswell_modeset_global_resources(struct drm_device *dev)
5906{
d6dd9eb1
DV		 5907 bool enable = false;
5908 struct intel_crtc *crtc;
d6dd9eb1
DV		 5909
5910 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 5911 if (!crtc->base.enabled)
5912 continue;
d6dd9eb1 5913
e7a639c4
DV		 5914 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5915 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 5916 enable = true;
5917 }
5918
d6dd9eb1
DV		 5919 intel_set_power_well(dev, enable);
5920}
5921
09b4ddf9 5922static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 5923 int x, int y,
5924 struct drm_framebuffer *fb)
5925{
5926 struct drm_device *dev = crtc->dev;
5927 struct drm_i915_private *dev_priv = dev->dev_private;
5928 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5929 struct drm_display_mode *adjusted_mode =
5930 &intel_crtc->config.adjusted_mode;
5931 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
09b4ddf9
PZ		 5932 int pipe = intel_crtc->pipe;
5933 int plane = intel_crtc->plane;
5934 int num_connectors = 0;
8b47047b 5935 bool is_cpu_edp = false;
09b4ddf9 5936 struct intel_encoder *encoder;
09b4ddf9 5937 int ret;
09b4ddf9
PZ		 5938
5939 for_each_encoder_on_crtc(dev, crtc, encoder) {
5940 switch (encoder->type) {
09b4ddf9 5941 case INTEL_OUTPUT_EDP:
d8e8b582 5942 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
09b4ddf9
PZ		 5943 is_cpu_edp = true;
5944 break;
5945 }
5946
5947 num_connectors++;
5948 }
5949
5dc5298b
PZ		 5950 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5951 num_connectors, pipe_name(pipe));
5952
6441ab5f
PZ		 5953 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5954 return -EINVAL;
5955
09b4ddf9
PZ		 5956 /* Ensure that the cursor is valid for the new mode before changing... */
5957 intel_crtc_update_cursor(crtc, true);
5958
03afc4a2
DV		 5959 if (intel_crtc->config.has_dp_encoder)
5960 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 5961
5962 intel_crtc->lowfreq_avail = false;
09b4ddf9
PZ		 5963
5964 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5965
ca3a0ff8 5966 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5967 intel_cpu_transcoder_set_m_n(intel_crtc,
5968 &intel_crtc->config.fdi_m_n);
5969 }
09b4ddf9 5970
6ff93609 5971 haswell_set_pipeconf(crtc);
09b4ddf9 5972
50f3b016 5973 intel_set_pipe_csc(crtc);
86d3efce 5974
09b4ddf9 5975 /* Set up the display plane register */
86d3efce 5976 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5977 POSTING_READ(DSPCNTR(plane));
5978
5979 ret = intel_pipe_set_base(crtc, x, y, fb);
5980
5981 intel_update_watermarks(dev);
5982
1f803ee5 5983 return ret;
79e53945
JB		 5984}
5985
0e8ffe1b
DV		 5986static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5987 struct intel_crtc_config *pipe_config)
5988{
5989 struct drm_device *dev = crtc->base.dev;
5990 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 5991 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 5992 uint32_t tmp;
5993
eccb140b
DV		 5994 pipe_config->cpu_transcoder = crtc->pipe;
5995 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
5996 if (tmp & TRANS_DDI_FUNC_ENABLE) {
5997 enum pipe trans_edp_pipe;
5998 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
5999 default:
6000 WARN(1, "unknown pipe linked to edp transcoder\n");
6001 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6002 case TRANS_DDI_EDP_INPUT_A_ON:
6003 trans_edp_pipe = PIPE_A;
6004 break;
6005 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6006 trans_edp_pipe = PIPE_B;
6007 break;
6008 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6009 trans_edp_pipe = PIPE_C;
6010 break;
6011 }
6012
6013 if (trans_edp_pipe == crtc->pipe)
6014 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6015 }
6016
b97186f0 6017 if (!intel_display_power_enabled(dev,
eccb140b 6018 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 6019 return false;
6020
eccb140b 6021 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 6022 if (!(tmp & PIPECONF_ENABLE))
6023 return false;
6024
88adfff1 6025 /*
f196e6be 6026 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 6027 * DDI E. So just check whether this pipe is wired to DDI E and whether
6028 * the PCH transcoder is on.
6029 */
eccb140b 6030 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 6031 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 6032 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 6033 pipe_config->has_pch_encoder = true;
6034
627eb5a3
DV		 6035 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6036 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6037 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6038
6039 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 6040 }
6041
1bd1bd80
DV		 6042 intel_get_pipe_timings(crtc, pipe_config);
6043
2fa2fe9a
DV		 6044 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6045 if (intel_display_power_enabled(dev, pfit_domain))
6046 ironlake_get_pfit_config(crtc, pipe_config);
6047
42db64ef
PZ		 6048 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6049 (I915_READ(IPS_CTL) & IPS_ENABLE);
6050
0e8ffe1b
DV		 6051 return true;
6052}
6053
f564048e 6054static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6055 int x, int y,
94352cf9 6056 struct drm_framebuffer *fb)
f564048e
EA		 6057{
6058 struct drm_device *dev = crtc->dev;
6059 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 6060 struct drm_encoder_helper_funcs *encoder_funcs;
6061 struct intel_encoder *encoder;
0b701d27 6062 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 6063 struct drm_display_mode *adjusted_mode =
6064 &intel_crtc->config.adjusted_mode;
6065 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6066 int pipe = intel_crtc->pipe;
f564048e
EA		 6067 int ret;
6068
0b701d27 6069 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6070
b8cecdf5
DV		 6071 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6072
79e53945 6073 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6074
9256aa19
DV		 6075 if (ret != 0)
6076 return ret;
6077
6078 for_each_encoder_on_crtc(dev, crtc, encoder) {
6079 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6080 encoder->base.base.id,
6081 drm_get_encoder_name(&encoder->base),
6082 mode->base.id, mode->name);
6cc5f341
DV		 6083 if (encoder->mode_set) {
6084 encoder->mode_set(encoder);
6085 } else {
6086 encoder_funcs = encoder->base.helper_private;
6087 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6088 }
9256aa19
DV		 6089 }
6090
6091 return 0;
79e53945
JB		 6092}
6093
3a9627f4
WF		 6094static bool intel_eld_uptodate(struct drm_connector *connector,
6095 int reg_eldv, uint32_t bits_eldv,
6096 int reg_elda, uint32_t bits_elda,
6097 int reg_edid)
6098{
6099 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6100 uint8_t *eld = connector->eld;
6101 uint32_t i;
6102
6103 i = I915_READ(reg_eldv);
6104 i &= bits_eldv;
6105
6106 if (!eld[0])
6107 return !i;
6108
6109 if (!i)
6110 return false;
6111
6112 i = I915_READ(reg_elda);
6113 i &= ~bits_elda;
6114 I915_WRITE(reg_elda, i);
6115
6116 for (i = 0; i < eld[2]; i++)
6117 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6118 return false;
6119
6120 return true;
6121}
6122
e0dac65e
WF		 6123static void g4x_write_eld(struct drm_connector *connector,
6124 struct drm_crtc *crtc)
6125{
6126 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6127 uint8_t *eld = connector->eld;
6128 uint32_t eldv;
6129 uint32_t len;
6130 uint32_t i;
6131
6132 i = I915_READ(G4X_AUD_VID_DID);
6133
6134 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6135 eldv = G4X_ELDV_DEVCL_DEVBLC;
6136 else
6137 eldv = G4X_ELDV_DEVCTG;
6138
3a9627f4
WF		 6139 if (intel_eld_uptodate(connector,
6140 G4X_AUD_CNTL_ST, eldv,
6141 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6142 G4X_HDMIW_HDMIEDID))
6143 return;
6144
e0dac65e
WF		 6145 i = I915_READ(G4X_AUD_CNTL_ST);
6146 i &= ~(eldv | G4X_ELD_ADDR);
6147 len = (i >> 9) & 0x1f; /* ELD buffer size */
6148 I915_WRITE(G4X_AUD_CNTL_ST, i);
6149
6150 if (!eld[0])
6151 return;
6152
6153 len = min_t(uint8_t, eld[2], len);
6154 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6155 for (i = 0; i < len; i++)
6156 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6157
6158 i = I915_READ(G4X_AUD_CNTL_ST);
6159 i |= eldv;
6160 I915_WRITE(G4X_AUD_CNTL_ST, i);
6161}
6162
83358c85
WX		 6163static void haswell_write_eld(struct drm_connector *connector,
6164 struct drm_crtc *crtc)
6165{
6166 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6167 uint8_t *eld = connector->eld;
6168 struct drm_device *dev = crtc->dev;
7b9f35a6 6169 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6170 uint32_t eldv;
6171 uint32_t i;
6172 int len;
6173 int pipe = to_intel_crtc(crtc)->pipe;
6174 int tmp;
6175
6176 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6177 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6178 int aud_config = HSW_AUD_CFG(pipe);
6179 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6180
6181
6182 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6183
6184 /* Audio output enable */
6185 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6186 tmp = I915_READ(aud_cntrl_st2);
6187 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6188 I915_WRITE(aud_cntrl_st2, tmp);
6189
6190 /* Wait for 1 vertical blank */
6191 intel_wait_for_vblank(dev, pipe);
6192
6193 /* Set ELD valid state */
6194 tmp = I915_READ(aud_cntrl_st2);
6195 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6196 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6197 I915_WRITE(aud_cntrl_st2, tmp);
6198 tmp = I915_READ(aud_cntrl_st2);
6199 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6200
6201 /* Enable HDMI mode */
6202 tmp = I915_READ(aud_config);
6203 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6204 /* clear N_programing_enable and N_value_index */
6205 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6206 I915_WRITE(aud_config, tmp);
6207
6208 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6209
6210 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6211 intel_crtc->eld_vld = true;
83358c85
WX		 6212
6213 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6214 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6215 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6216 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6217 } else
6218 I915_WRITE(aud_config, 0);
6219
6220 if (intel_eld_uptodate(connector,
6221 aud_cntrl_st2, eldv,
6222 aud_cntl_st, IBX_ELD_ADDRESS,
6223 hdmiw_hdmiedid))
6224 return;
6225
6226 i = I915_READ(aud_cntrl_st2);
6227 i &= ~eldv;
6228 I915_WRITE(aud_cntrl_st2, i);
6229
6230 if (!eld[0])
6231 return;
6232
6233 i = I915_READ(aud_cntl_st);
6234 i &= ~IBX_ELD_ADDRESS;
6235 I915_WRITE(aud_cntl_st, i);
6236 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6237 DRM_DEBUG_DRIVER("port num:%d\n", i);
6238
6239 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6240 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6241 for (i = 0; i < len; i++)
6242 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6243
6244 i = I915_READ(aud_cntrl_st2);
6245 i |= eldv;
6246 I915_WRITE(aud_cntrl_st2, i);
6247
6248}
6249
e0dac65e
WF		 6250static void ironlake_write_eld(struct drm_connector *connector,
6251 struct drm_crtc *crtc)
6252{
6253 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6254 uint8_t *eld = connector->eld;
6255 uint32_t eldv;
6256 uint32_t i;
6257 int len;
6258 int hdmiw_hdmiedid;
b6daa025 6259 int aud_config;
e0dac65e
WF		 6260 int aud_cntl_st;
6261 int aud_cntrl_st2;
9b138a83 6262 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6263
b3f33cbf 6264 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6265 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6266 aud_config = IBX_AUD_CFG(pipe);
6267 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6268 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6269 } else {
9b138a83
WX		 6270 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6271 aud_config = CPT_AUD_CFG(pipe);
6272 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6273 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6274 }
6275
9b138a83 6276 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6277
6278 i = I915_READ(aud_cntl_st);
9b138a83 6279 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6280 if (!i) {
6281 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6282 /* operate blindly on all ports */
1202b4c6
WF		 6283 eldv = IBX_ELD_VALIDB;
6284 eldv |= IBX_ELD_VALIDB << 4;
6285 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6286 } else {
2582a850 6287 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6288 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6289 }
6290
3a9627f4
WF		 6291 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6292 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6293 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6294 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6295 } else
6296 I915_WRITE(aud_config, 0);
e0dac65e 6297
3a9627f4
WF		 6298 if (intel_eld_uptodate(connector,
6299 aud_cntrl_st2, eldv,
6300 aud_cntl_st, IBX_ELD_ADDRESS,
6301 hdmiw_hdmiedid))
6302 return;
6303
e0dac65e
WF		 6304 i = I915_READ(aud_cntrl_st2);
6305 i &= ~eldv;
6306 I915_WRITE(aud_cntrl_st2, i);
6307
6308 if (!eld[0])
6309 return;
6310
e0dac65e 6311 i = I915_READ(aud_cntl_st);
1202b4c6 6312 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6313 I915_WRITE(aud_cntl_st, i);
6314
6315 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6316 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6317 for (i = 0; i < len; i++)
6318 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6319
6320 i = I915_READ(aud_cntrl_st2);
6321 i |= eldv;
6322 I915_WRITE(aud_cntrl_st2, i);
6323}
6324
6325void intel_write_eld(struct drm_encoder *encoder,
6326 struct drm_display_mode *mode)
6327{
6328 struct drm_crtc *crtc = encoder->crtc;
6329 struct drm_connector *connector;
6330 struct drm_device *dev = encoder->dev;
6331 struct drm_i915_private *dev_priv = dev->dev_private;
6332
6333 connector = drm_select_eld(encoder, mode);
6334 if (!connector)
6335 return;
6336
6337 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6338 connector->base.id,
6339 drm_get_connector_name(connector),
6340 connector->encoder->base.id,
6341 drm_get_encoder_name(connector->encoder));
6342
6343 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6344
6345 if (dev_priv->display.write_eld)
6346 dev_priv->display.write_eld(connector, crtc);
6347}
6348
79e53945
JB		 6349/** Loads the palette/gamma unit for the CRTC with the prepared values */
6350void intel_crtc_load_lut(struct drm_crtc *crtc)
6351{
6352 struct drm_device *dev = crtc->dev;
6353 struct drm_i915_private *dev_priv = dev->dev_private;
6354 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
42db64ef
PZ		 6355 enum pipe pipe = intel_crtc->pipe;
6356 int palreg = PALETTE(pipe);
79e53945 6357 int i;
42db64ef 6358 bool reenable_ips = false;
79e53945
JB		 6359
6360 /* The clocks have to be on to load the palette. */
aed3f09d 6361 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6362 return;
6363
f2b115e6 6364 /* use legacy palette for Ironlake */
bad720ff 6365 if (HAS_PCH_SPLIT(dev))
42db64ef
PZ		 6366 palreg = LGC_PALETTE(pipe);
6367
6368 /* Workaround : Do not read or write the pipe palette/gamma data while
6369 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6370 */
6371 if (intel_crtc->config.ips_enabled &&
6372 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6373 GAMMA_MODE_MODE_SPLIT)) {
6374 hsw_disable_ips(intel_crtc);
6375 reenable_ips = true;
6376 }
2c07245f 6377
79e53945
JB		 6378 for (i = 0; i < 256; i++) {
6379 I915_WRITE(palreg + 4 * i,
6380 (intel_crtc->lut_r[i] << 16) |
6381 (intel_crtc->lut_g[i] << 8) |
6382 intel_crtc->lut_b[i]);
6383 }
42db64ef
PZ		 6384
6385 if (reenable_ips)
6386 hsw_enable_ips(intel_crtc);
79e53945
JB		 6387}
6388
560b85bb
CW		 6389static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6390{
6391 struct drm_device *dev = crtc->dev;
6392 struct drm_i915_private *dev_priv = dev->dev_private;
6393 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6394 bool visible = base != 0;
6395 u32 cntl;
6396
6397 if (intel_crtc->cursor_visible == visible)
6398 return;
6399
9db4a9c7 6400 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6401 if (visible) {
6402 /* On these chipsets we can only modify the base whilst
6403 * the cursor is disabled.
6404 */
9db4a9c7 6405 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6406
6407 cntl &= ~(CURSOR_FORMAT_MASK);
6408 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6409 cntl |= CURSOR_ENABLE |
6410 CURSOR_GAMMA_ENABLE |
6411 CURSOR_FORMAT_ARGB;
6412 } else
6413 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6414 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6415
6416 intel_crtc->cursor_visible = visible;
6417}
6418
6419static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6420{
6421 struct drm_device *dev = crtc->dev;
6422 struct drm_i915_private *dev_priv = dev->dev_private;
6423 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6424 int pipe = intel_crtc->pipe;
6425 bool visible = base != 0;
6426
6427 if (intel_crtc->cursor_visible != visible) {
548f245b 6428 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6429 if (base) {
6430 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6431 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6432 cntl |= pipe << 28; /* Connect to correct pipe */
6433 } else {
6434 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6435 cntl |= CURSOR_MODE_DISABLE;
6436 }
9db4a9c7 6437 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6438
6439 intel_crtc->cursor_visible = visible;
6440 }
6441 /* and commit changes on next vblank */
9db4a9c7 6442 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6443}
6444
65a21cd6
JB		 6445static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6446{
6447 struct drm_device *dev = crtc->dev;
6448 struct drm_i915_private *dev_priv = dev->dev_private;
6449 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6450 int pipe = intel_crtc->pipe;
6451 bool visible = base != 0;
6452
6453 if (intel_crtc->cursor_visible != visible) {
6454 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6455 if (base) {
6456 cntl &= ~CURSOR_MODE;
6457 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6458 } else {
6459 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6460 cntl |= CURSOR_MODE_DISABLE;
6461 }
86d3efce
VS		 6462 if (IS_HASWELL(dev))
6463 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6464 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6465
6466 intel_crtc->cursor_visible = visible;
6467 }
6468 /* and commit changes on next vblank */
6469 I915_WRITE(CURBASE_IVB(pipe), base);
6470}
6471
cda4b7d3 6472/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6473static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6474 bool on)
cda4b7d3
CW		 6475{
6476 struct drm_device *dev = crtc->dev;
6477 struct drm_i915_private *dev_priv = dev->dev_private;
6478 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6479 int pipe = intel_crtc->pipe;
6480 int x = intel_crtc->cursor_x;
6481 int y = intel_crtc->cursor_y;
560b85bb 6482 u32 base, pos;
cda4b7d3
CW		 6483 bool visible;
6484
6485 pos = 0;
6486
6b383a7f 6487 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6488 base = intel_crtc->cursor_addr;
6489 if (x > (int) crtc->fb->width)
6490 base = 0;
6491
6492 if (y > (int) crtc->fb->height)
6493 base = 0;
6494 } else
6495 base = 0;
6496
6497 if (x < 0) {
6498 if (x + intel_crtc->cursor_width < 0)
6499 base = 0;
6500
6501 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6502 x = -x;
6503 }
6504 pos |= x << CURSOR_X_SHIFT;
6505
6506 if (y < 0) {
6507 if (y + intel_crtc->cursor_height < 0)
6508 base = 0;
6509
6510 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6511 y = -y;
6512 }
6513 pos |= y << CURSOR_Y_SHIFT;
6514
6515 visible = base != 0;
560b85bb 6516 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6517 return;
6518
0cd83aa9 6519 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6520 I915_WRITE(CURPOS_IVB(pipe), pos);
6521 ivb_update_cursor(crtc, base);
6522 } else {
6523 I915_WRITE(CURPOS(pipe), pos);
6524 if (IS_845G(dev) || IS_I865G(dev))
6525 i845_update_cursor(crtc, base);
6526 else
6527 i9xx_update_cursor(crtc, base);
6528 }
cda4b7d3
CW		 6529}
6530
79e53945 6531static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6532 struct drm_file *file,
79e53945
JB		 6533 uint32_t handle,
6534 uint32_t width, uint32_t height)
6535{
6536 struct drm_device *dev = crtc->dev;
6537 struct drm_i915_private *dev_priv = dev->dev_private;
6538 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6539 struct drm_i915_gem_object *obj;
cda4b7d3 6540 uint32_t addr;
3f8bc370 6541 int ret;
79e53945 6542
79e53945
JB		 6543 /* if we want to turn off the cursor ignore width and height */
6544 if (!handle) {
28c97730 6545 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6546 addr = 0;
05394f39 6547 obj = NULL;
5004417d 6548 mutex_lock(&dev->struct_mutex);
3f8bc370 6549 goto finish;
79e53945
JB		 6550 }
6551
6552 /* Currently we only support 64x64 cursors */
6553 if (width != 64 || height != 64) {
6554 DRM_ERROR("we currently only support 64x64 cursors\n");
6555 return -EINVAL;
6556 }
6557
05394f39 6558 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6559 if (&obj->base == NULL)
79e53945
JB		 6560 return -ENOENT;
6561
05394f39 6562 if (obj->base.size < width * height * 4) {
79e53945 6563 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6564 ret = -ENOMEM;
6565 goto fail;
79e53945
JB		 6566 }
6567
71acb5eb 6568 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6569 mutex_lock(&dev->struct_mutex);
b295d1b6 6570 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6571 unsigned alignment;
6572
d9e86c0e
CW		 6573 if (obj->tiling_mode) {
6574 DRM_ERROR("cursor cannot be tiled\n");
6575 ret = -EINVAL;
6576 goto fail_locked;
6577 }
6578
693db184
CW		 6579 /* Note that the w/a also requires 2 PTE of padding following
6580 * the bo. We currently fill all unused PTE with the shadow
6581 * page and so we should always have valid PTE following the
6582 * cursor preventing the VT-d warning.
6583 */
6584 alignment = 0;
6585 if (need_vtd_wa(dev))
6586 alignment = 64*1024;
6587
6588 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6589 if (ret) {
6590 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6591 goto fail_locked;
e7b526bb
CW		 6592 }
6593
d9e86c0e
CW		 6594 ret = i915_gem_object_put_fence(obj);
6595 if (ret) {
2da3b9b9 6596 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6597 goto fail_unpin;
6598 }
6599
05394f39 6600 addr = obj->gtt_offset;
71acb5eb 6601 } else {
6eeefaf3 6602 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6603 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6604 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6605 align);
71acb5eb
DA		 6606 if (ret) {
6607 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6608 goto fail_locked;
71acb5eb 6609 }
05394f39 6610 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6611 }
6612
a6c45cf0 6613 if (IS_GEN2(dev))
14b60391
JB		 6614 I915_WRITE(CURSIZE, (height << 12) | width);
6615
3f8bc370 6616 finish:
3f8bc370 6617 if (intel_crtc->cursor_bo) {
b295d1b6 6618 if (dev_priv->info->cursor_needs_physical) {
05394f39 6619 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6620 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6621 } else
6622 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6623 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6624 }
80824003 6625
7f9872e0 6626 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6627
6628 intel_crtc->cursor_addr = addr;
05394f39 6629 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6630 intel_crtc->cursor_width = width;
6631 intel_crtc->cursor_height = height;
6632
40ccc72b 6633 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 6634
79e53945 6635 return 0;
e7b526bb 6636fail_unpin:
05394f39 6637 i915_gem_object_unpin(obj);
7f9872e0 6638fail_locked:
34b8686e 6639 mutex_unlock(&dev->struct_mutex);
bc9025bd 6640fail:
05394f39 6641 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6642 return ret;
79e53945
JB		 6643}
6644
6645static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6646{
79e53945 6647 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6648
cda4b7d3
CW		 6649 intel_crtc->cursor_x = x;
6650 intel_crtc->cursor_y = y;
652c393a 6651
40ccc72b 6652 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 6653
6654 return 0;
6655}
6656
6657/** Sets the color ramps on behalf of RandR */
6658void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6659 u16 blue, int regno)
6660{
6661 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6662
6663 intel_crtc->lut_r[regno] = red >> 8;
6664 intel_crtc->lut_g[regno] = green >> 8;
6665 intel_crtc->lut_b[regno] = blue >> 8;
6666}
6667
b8c00ac5
DA		 6668void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6669 u16 *blue, int regno)
6670{
6671 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6672
6673 *red = intel_crtc->lut_r[regno] << 8;
6674 *green = intel_crtc->lut_g[regno] << 8;
6675 *blue = intel_crtc->lut_b[regno] << 8;
6676}
6677
79e53945 6678static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6679 u16 *blue, uint32_t start, uint32_t size)
79e53945 6680{
7203425a 6681 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6682 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6683
7203425a 6684 for (i = start; i < end; i++) {
79e53945
JB		 6685 intel_crtc->lut_r[i] = red[i] >> 8;
6686 intel_crtc->lut_g[i] = green[i] >> 8;
6687 intel_crtc->lut_b[i] = blue[i] >> 8;
6688 }
6689
6690 intel_crtc_load_lut(crtc);
6691}
6692
79e53945
JB		 6693/* VESA 640x480x72Hz mode to set on the pipe */
6694static struct drm_display_mode load_detect_mode = {
6695 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6696 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6697};
6698
d2dff872
CW		 6699static struct drm_framebuffer *
6700intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6701 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6702 struct drm_i915_gem_object *obj)
6703{
6704 struct intel_framebuffer *intel_fb;
6705 int ret;
6706
6707 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6708 if (!intel_fb) {
6709 drm_gem_object_unreference_unlocked(&obj->base);
6710 return ERR_PTR(-ENOMEM);
6711 }
6712
6713 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6714 if (ret) {
6715 drm_gem_object_unreference_unlocked(&obj->base);
6716 kfree(intel_fb);
6717 return ERR_PTR(ret);
6718 }
6719
6720 return &intel_fb->base;
6721}
6722
6723static u32
6724intel_framebuffer_pitch_for_width(int width, int bpp)
6725{
6726 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6727 return ALIGN(pitch, 64);
6728}
6729
6730static u32
6731intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6732{
6733 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6734 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6735}
6736
6737static struct drm_framebuffer *
6738intel_framebuffer_create_for_mode(struct drm_device *dev,
6739 struct drm_display_mode *mode,
6740 int depth, int bpp)
6741{
6742 struct drm_i915_gem_object *obj;
0fed39bd 6743 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6744
6745 obj = i915_gem_alloc_object(dev,
6746 intel_framebuffer_size_for_mode(mode, bpp));
6747 if (obj == NULL)
6748 return ERR_PTR(-ENOMEM);
6749
6750 mode_cmd.width = mode->hdisplay;
6751 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6752 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6753 bpp);
5ca0c34a 6754 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6755
6756 return intel_framebuffer_create(dev, &mode_cmd, obj);
6757}
6758
6759static struct drm_framebuffer *
6760mode_fits_in_fbdev(struct drm_device *dev,
6761 struct drm_display_mode *mode)
6762{
6763 struct drm_i915_private *dev_priv = dev->dev_private;
6764 struct drm_i915_gem_object *obj;
6765 struct drm_framebuffer *fb;
6766
6767 if (dev_priv->fbdev == NULL)
6768 return NULL;
6769
6770 obj = dev_priv->fbdev->ifb.obj;
6771 if (obj == NULL)
6772 return NULL;
6773
6774 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6775 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6776 fb->bits_per_pixel))
d2dff872
CW		 6777 return NULL;
6778
01f2c773 6779 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6780 return NULL;
6781
6782 return fb;
6783}
6784
d2434ab7 6785bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6786 struct drm_display_mode *mode,
8261b191 6787 struct intel_load_detect_pipe *old)
79e53945
JB		 6788{
6789 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6790 struct intel_encoder *intel_encoder =
6791 intel_attached_encoder(connector);
79e53945 6792 struct drm_crtc *possible_crtc;
4ef69c7a 6793 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6794 struct drm_crtc *crtc = NULL;
6795 struct drm_device *dev = encoder->dev;
94352cf9 6796 struct drm_framebuffer *fb;
79e53945
JB		 6797 int i = -1;
6798
d2dff872
CW		 6799 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6800 connector->base.id, drm_get_connector_name(connector),
6801 encoder->base.id, drm_get_encoder_name(encoder));
6802
79e53945
JB		 6803 /*
6804 * Algorithm gets a little messy:
7a5e4805 6805 *
79e53945
JB		 6806 * - if the connector already has an assigned crtc, use it (but make
6807 * sure it's on first)
7a5e4805 6808 *
79e53945
JB		 6809 * - try to find the first unused crtc that can drive this connector,
6810 * and use that if we find one
79e53945
JB		 6811 */
6812
6813 /* See if we already have a CRTC for this connector */
6814 if (encoder->crtc) {
6815 crtc = encoder->crtc;
8261b191 6816
7b24056b
DV		 6817 mutex_lock(&crtc->mutex);
6818
24218aac 6819 old->dpms_mode = connector->dpms;
8261b191
CW		 6820 old->load_detect_temp = false;
6821
6822 /* Make sure the crtc and connector are running */
24218aac
DV		 6823 if (connector->dpms != DRM_MODE_DPMS_ON)
6824 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6825
7173188d 6826 return true;
79e53945
JB		 6827 }
6828
6829 /* Find an unused one (if possible) */
6830 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6831 i++;
6832 if (!(encoder->possible_crtcs & (1 << i)))
6833 continue;
6834 if (!possible_crtc->enabled) {
6835 crtc = possible_crtc;
6836 break;
6837 }
79e53945
JB		 6838 }
6839
6840 /*
6841 * If we didn't find an unused CRTC, don't use any.
6842 */
6843 if (!crtc) {
7173188d
CW		 6844 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6845 return false;
79e53945
JB		 6846 }
6847
7b24056b 6848 mutex_lock(&crtc->mutex);
fc303101
DV		 6849 intel_encoder->new_crtc = to_intel_crtc(crtc);
6850 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6851
6852 intel_crtc = to_intel_crtc(crtc);
24218aac 6853 old->dpms_mode = connector->dpms;
8261b191 6854 old->load_detect_temp = true;
d2dff872 6855 old->release_fb = NULL;
79e53945 6856
6492711d
CW		 6857 if (!mode)
6858 mode = &load_detect_mode;
79e53945 6859
d2dff872
CW		 6860 /* We need a framebuffer large enough to accommodate all accesses
6861 * that the plane may generate whilst we perform load detection.
6862 * We can not rely on the fbcon either being present (we get called
6863 * during its initialisation to detect all boot displays, or it may
6864 * not even exist) or that it is large enough to satisfy the
6865 * requested mode.
6866 */
94352cf9
DV		 6867 fb = mode_fits_in_fbdev(dev, mode);
6868 if (fb == NULL) {
d2dff872 6869 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6870 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6871 old->release_fb = fb;
d2dff872
CW		 6872 } else
6873 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6874 if (IS_ERR(fb)) {
d2dff872 6875 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6876 mutex_unlock(&crtc->mutex);
0e8b3d3e 6877 return false;
79e53945 6878 }
79e53945 6879
c0c36b94 6880 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6881 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6882 if (old->release_fb)
6883 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6884 mutex_unlock(&crtc->mutex);
0e8b3d3e 6885 return false;
79e53945 6886 }
7173188d 6887
79e53945 6888 /* let the connector get through one full cycle before testing */
9d0498a2 6889 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6890 return true;
79e53945
JB		 6891}
6892
d2434ab7 6893void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6894 struct intel_load_detect_pipe *old)
79e53945 6895{
d2434ab7
DV		 6896 struct intel_encoder *intel_encoder =
6897 intel_attached_encoder(connector);
4ef69c7a 6898 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6899 struct drm_crtc *crtc = encoder->crtc;
79e53945 6900
d2dff872
CW		 6901 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6902 connector->base.id, drm_get_connector_name(connector),
6903 encoder->base.id, drm_get_encoder_name(encoder));
6904
8261b191 6905 if (old->load_detect_temp) {
fc303101
DV		 6906 to_intel_connector(connector)->new_encoder = NULL;
6907 intel_encoder->new_crtc = NULL;
6908 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6909
36206361
DV		 6910 if (old->release_fb) {
6911 drm_framebuffer_unregister_private(old->release_fb);
6912 drm_framebuffer_unreference(old->release_fb);
6913 }
d2dff872 6914
67c96400 6915 mutex_unlock(&crtc->mutex);
0622a53c 6916 return;
79e53945
JB		 6917 }
6918
c751ce4f 6919 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6920 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6921 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6922
6923 mutex_unlock(&crtc->mutex);
79e53945
JB		 6924}
6925
6926/* Returns the clock of the currently programmed mode of the given pipe. */
6927static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6928{
6929 struct drm_i915_private *dev_priv = dev->dev_private;
6930 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6931 int pipe = intel_crtc->pipe;
548f245b 6932 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6933 u32 fp;
6934 intel_clock_t clock;
6935
6936 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6937 fp = I915_READ(FP0(pipe));
79e53945 6938 else
39adb7a5 6939 fp = I915_READ(FP1(pipe));
79e53945
JB		 6940
6941 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6942 if (IS_PINEVIEW(dev)) {
6943 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6944 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6945 } else {
6946 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6947 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6948 }
6949
a6c45cf0 6950 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6951 if (IS_PINEVIEW(dev))
6952 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6953 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6954 else
6955 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6956 DPLL_FPA01_P1_POST_DIV_SHIFT);
6957
6958 switch (dpll & DPLL_MODE_MASK) {
6959 case DPLLB_MODE_DAC_SERIAL:
6960 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6961 5 : 10;
6962 break;
6963 case DPLLB_MODE_LVDS:
6964 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6965 7 : 14;
6966 break;
6967 default:
28c97730 6968 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6969 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6970 return 0;
6971 }
6972
ac58c3f0
DV		 6973 if (IS_PINEVIEW(dev))
6974 pineview_clock(96000, &clock);
6975 else
6976 i9xx_clock(96000, &clock);
79e53945
JB		 6977 } else {
6978 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6979
6980 if (is_lvds) {
6981 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6982 DPLL_FPA01_P1_POST_DIV_SHIFT);
6983 clock.p2 = 14;
6984
6985 if ((dpll & PLL_REF_INPUT_MASK) ==
6986 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6987 /* XXX: might not be 66MHz */
ac58c3f0 6988 i9xx_clock(66000, &clock);
79e53945 6989 } else
ac58c3f0 6990 i9xx_clock(48000, &clock);
79e53945
JB		 6991 } else {
6992 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6993 clock.p1 = 2;
6994 else {
6995 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6996 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6997 }
6998 if (dpll & PLL_P2_DIVIDE_BY_4)
6999 clock.p2 = 4;
7000 else
7001 clock.p2 = 2;
7002
ac58c3f0 7003 i9xx_clock(48000, &clock);
79e53945
JB		 7004 }
7005 }
7006
7007 /* XXX: It would be nice to validate the clocks, but we can't reuse
7008 * i830PllIsValid() because it relies on the xf86_config connector
7009 * configuration being accurate, which it isn't necessarily.
7010 */
7011
7012 return clock.dot;
7013}
7014
7015/** Returns the currently programmed mode of the given pipe. */
7016struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7017 struct drm_crtc *crtc)
7018{
548f245b 7019 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 7020 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 7021 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 7022 struct drm_display_mode *mode;
fe2b8f9d
PZ		 7023 int htot = I915_READ(HTOTAL(cpu_transcoder));
7024 int hsync = I915_READ(HSYNC(cpu_transcoder));
7025 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7026 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 7027
7028 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7029 if (!mode)
7030 return NULL;
7031
7032 mode->clock = intel_crtc_clock_get(dev, crtc);
7033 mode->hdisplay = (htot & 0xffff) + 1;
7034 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7035 mode->hsync_start = (hsync & 0xffff) + 1;
7036 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7037 mode->vdisplay = (vtot & 0xffff) + 1;
7038 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7039 mode->vsync_start = (vsync & 0xffff) + 1;
7040 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7041
7042 drm_mode_set_name(mode);
79e53945
JB		 7043
7044 return mode;
7045}
7046
3dec0095 7047static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7048{
7049 struct drm_device *dev = crtc->dev;
7050 drm_i915_private_t *dev_priv = dev->dev_private;
7051 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7052 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7053 int dpll_reg = DPLL(pipe);
7054 int dpll;
652c393a 7055
bad720ff 7056 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7057 return;
7058
7059 if (!dev_priv->lvds_downclock_avail)
7060 return;
7061
dbdc6479 7062 dpll = I915_READ(dpll_reg);
652c393a 7063 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7064 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7065
8ac5a6d5 7066 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7067
7068 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7069 I915_WRITE(dpll_reg, dpll);
9d0498a2 7070 intel_wait_for_vblank(dev, pipe);
dbdc6479 7071
652c393a
JB		 7072 dpll = I915_READ(dpll_reg);
7073 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7074 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7075 }
652c393a
JB		 7076}
7077
7078static void intel_decrease_pllclock(struct drm_crtc *crtc)
7079{
7080 struct drm_device *dev = crtc->dev;
7081 drm_i915_private_t *dev_priv = dev->dev_private;
7082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7083
bad720ff 7084 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7085 return;
7086
7087 if (!dev_priv->lvds_downclock_avail)
7088 return;
7089
7090 /*
7091 * Since this is called by a timer, we should never get here in
7092 * the manual case.
7093 */
7094 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7095 int pipe = intel_crtc->pipe;
7096 int dpll_reg = DPLL(pipe);
7097 int dpll;
f6e5b160 7098
44d98a61 7099 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7100
8ac5a6d5 7101 assert_panel_unlocked(dev_priv, pipe);
652c393a 7102
dc257cf1 7103 dpll = I915_READ(dpll_reg);
652c393a
JB		 7104 dpll |= DISPLAY_RATE_SELECT_FPA1;
7105 I915_WRITE(dpll_reg, dpll);
9d0498a2 7106 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7107 dpll = I915_READ(dpll_reg);
7108 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7109 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7110 }
7111
7112}
7113
f047e395
CW		 7114void intel_mark_busy(struct drm_device *dev)
7115{
f047e395
CW		 7116 i915_update_gfx_val(dev->dev_private);
7117}
7118
7119void intel_mark_idle(struct drm_device *dev)
652c393a 7120{
652c393a 7121 struct drm_crtc *crtc;
652c393a
JB		 7122
7123 if (!i915_powersave)
7124 return;
7125
652c393a 7126 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7127 if (!crtc->fb)
7128 continue;
7129
725a5b54 7130 intel_decrease_pllclock(crtc);
652c393a 7131 }
652c393a
JB		 7132}
7133
725a5b54 7134void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
652c393a 7135{
f047e395
CW		 7136 struct drm_device *dev = obj->base.dev;
7137 struct drm_crtc *crtc;
652c393a 7138
f047e395 7139 if (!i915_powersave)
acb87dfb
CW		 7140 return;
7141
652c393a
JB		 7142 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7143 if (!crtc->fb)
7144 continue;
7145
f047e395 7146 if (to_intel_framebuffer(crtc->fb)->obj == obj)
725a5b54 7147 intel_increase_pllclock(crtc);
652c393a
JB		 7148 }
7149}
7150
79e53945
JB		 7151static void intel_crtc_destroy(struct drm_crtc *crtc)
7152{
7153 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7154 struct drm_device *dev = crtc->dev;
7155 struct intel_unpin_work *work;
7156 unsigned long flags;
7157
7158 spin_lock_irqsave(&dev->event_lock, flags);
7159 work = intel_crtc->unpin_work;
7160 intel_crtc->unpin_work = NULL;
7161 spin_unlock_irqrestore(&dev->event_lock, flags);
7162
7163 if (work) {
7164 cancel_work_sync(&work->work);
7165 kfree(work);
7166 }
79e53945 7167
40ccc72b
MK		 7168 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7169
79e53945 7170 drm_crtc_cleanup(crtc);
67e77c5a 7171
79e53945
JB		 7172 kfree(intel_crtc);
7173}
7174
6b95a207
KH		 7175static void intel_unpin_work_fn(struct work_struct *__work)
7176{
7177 struct intel_unpin_work *work =
7178 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7179 struct drm_device *dev = work->crtc->dev;
6b95a207 7180
b4a98e57 7181 mutex_lock(&dev->struct_mutex);
1690e1eb 7182 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7183 drm_gem_object_unreference(&work->pending_flip_obj->base);
7184 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7185
b4a98e57
CW		 7186 intel_update_fbc(dev);
7187 mutex_unlock(&dev->struct_mutex);
7188
7189 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7190 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7191
6b95a207
KH		 7192 kfree(work);
7193}
7194
1afe3e9d 7195static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7196 struct drm_crtc *crtc)
6b95a207
KH		 7197{
7198 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7199 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7200 struct intel_unpin_work *work;
6b95a207
KH		 7201 unsigned long flags;
7202
7203 /* Ignore early vblank irqs */
7204 if (intel_crtc == NULL)
7205 return;
7206
7207 spin_lock_irqsave(&dev->event_lock, flags);
7208 work = intel_crtc->unpin_work;
e7d841ca
CW		 7209
7210 /* Ensure we don't miss a work->pending update ... */
7211 smp_rmb();
7212
7213 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7214 spin_unlock_irqrestore(&dev->event_lock, flags);
7215 return;
7216 }
7217
e7d841ca
CW		 7218 /* and that the unpin work is consistent wrt ->pending. */
7219 smp_rmb();
7220
6b95a207 7221 intel_crtc->unpin_work = NULL;
6b95a207 7222
45a066eb
RC		 7223 if (work->event)
7224 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7225
0af7e4df
MK		 7226 drm_vblank_put(dev, intel_crtc->pipe);
7227
6b95a207
KH		 7228 spin_unlock_irqrestore(&dev->event_lock, flags);
7229
2c10d571 7230 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7231
7232 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7233
7234 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7235}
7236
1afe3e9d
JB		 7237void intel_finish_page_flip(struct drm_device *dev, int pipe)
7238{
7239 drm_i915_private_t *dev_priv = dev->dev_private;
7240 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7241
49b14a5c 7242 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7243}
7244
7245void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7246{
7247 drm_i915_private_t *dev_priv = dev->dev_private;
7248 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7249
49b14a5c 7250 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7251}
7252
6b95a207
KH		 7253void intel_prepare_page_flip(struct drm_device *dev, int plane)
7254{
7255 drm_i915_private_t *dev_priv = dev->dev_private;
7256 struct intel_crtc *intel_crtc =
7257 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7258 unsigned long flags;
7259
e7d841ca
CW		 7260 /* NB: An MMIO update of the plane base pointer will also
7261 * generate a page-flip completion irq, i.e. every modeset
7262 * is also accompanied by a spurious intel_prepare_page_flip().
7263 */
6b95a207 7264 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7265 if (intel_crtc->unpin_work)
7266 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7267 spin_unlock_irqrestore(&dev->event_lock, flags);
7268}
7269
e7d841ca
CW		 7270inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7271{
7272 /* Ensure that the work item is consistent when activating it ... */
7273 smp_wmb();
7274 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7275 /* and that it is marked active as soon as the irq could fire. */
7276 smp_wmb();
7277}
7278
8c9f3aaf
JB		 7279static int intel_gen2_queue_flip(struct drm_device *dev,
7280 struct drm_crtc *crtc,
7281 struct drm_framebuffer *fb,
7282 struct drm_i915_gem_object *obj)
7283{
7284 struct drm_i915_private *dev_priv = dev->dev_private;
7285 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7286 u32 flip_mask;
6d90c952 7287 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7288 int ret;
7289
6d90c952 7290 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7291 if (ret)
83d4092b 7292 goto err;
8c9f3aaf 7293
6d90c952 7294 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7295 if (ret)
83d4092b 7296 goto err_unpin;
8c9f3aaf
JB		 7297
7298 /* Can't queue multiple flips, so wait for the previous
7299 * one to finish before executing the next.
7300 */
7301 if (intel_crtc->plane)
7302 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7303 else
7304 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7305 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7306 intel_ring_emit(ring, MI_NOOP);
7307 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7308 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7309 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7310 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 7311 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7312
7313 intel_mark_page_flip_active(intel_crtc);
6d90c952 7314 intel_ring_advance(ring);
83d4092b
CW		 7315 return 0;
7316
7317err_unpin:
7318 intel_unpin_fb_obj(obj);
7319err:
8c9f3aaf
JB		 7320 return ret;
7321}
7322
7323static int intel_gen3_queue_flip(struct drm_device *dev,
7324 struct drm_crtc *crtc,
7325 struct drm_framebuffer *fb,
7326 struct drm_i915_gem_object *obj)
7327{
7328 struct drm_i915_private *dev_priv = dev->dev_private;
7329 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7330 u32 flip_mask;
6d90c952 7331 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7332 int ret;
7333
6d90c952 7334 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7335 if (ret)
83d4092b 7336 goto err;
8c9f3aaf 7337
6d90c952 7338 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7339 if (ret)
83d4092b 7340 goto err_unpin;
8c9f3aaf
JB		 7341
7342 if (intel_crtc->plane)
7343 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7344 else
7345 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7346 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7347 intel_ring_emit(ring, MI_NOOP);
7348 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7349 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7350 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7351 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7352 intel_ring_emit(ring, MI_NOOP);
7353
e7d841ca 7354 intel_mark_page_flip_active(intel_crtc);
6d90c952 7355 intel_ring_advance(ring);
83d4092b
CW		 7356 return 0;
7357
7358err_unpin:
7359 intel_unpin_fb_obj(obj);
7360err:
8c9f3aaf
JB		 7361 return ret;
7362}
7363
7364static int intel_gen4_queue_flip(struct drm_device *dev,
7365 struct drm_crtc *crtc,
7366 struct drm_framebuffer *fb,
7367 struct drm_i915_gem_object *obj)
7368{
7369 struct drm_i915_private *dev_priv = dev->dev_private;
7370 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7371 uint32_t pf, pipesrc;
6d90c952 7372 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7373 int ret;
7374
6d90c952 7375 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7376 if (ret)
83d4092b 7377 goto err;
8c9f3aaf 7378
6d90c952 7379 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7380 if (ret)
83d4092b 7381 goto err_unpin;
8c9f3aaf
JB		 7382
7383 /* i965+ uses the linear or tiled offsets from the
7384 * Display Registers (which do not change across a page-flip)
7385 * so we need only reprogram the base address.
7386 */
6d90c952
DV		 7387 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7388 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7389 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7390 intel_ring_emit(ring,
7391 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7392 obj->tiling_mode);
8c9f3aaf
JB		 7393
7394 /* XXX Enabling the panel-fitter across page-flip is so far
7395 * untested on non-native modes, so ignore it for now.
7396 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7397 */
7398 pf = 0;
7399 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7400 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7401
7402 intel_mark_page_flip_active(intel_crtc);
6d90c952 7403 intel_ring_advance(ring);
83d4092b
CW		 7404 return 0;
7405
7406err_unpin:
7407 intel_unpin_fb_obj(obj);
7408err:
8c9f3aaf
JB		 7409 return ret;
7410}
7411
7412static int intel_gen6_queue_flip(struct drm_device *dev,
7413 struct drm_crtc *crtc,
7414 struct drm_framebuffer *fb,
7415 struct drm_i915_gem_object *obj)
7416{
7417 struct drm_i915_private *dev_priv = dev->dev_private;
7418 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7419 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7420 uint32_t pf, pipesrc;
7421 int ret;
7422
6d90c952 7423 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7424 if (ret)
83d4092b 7425 goto err;
8c9f3aaf 7426
6d90c952 7427 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7428 if (ret)
83d4092b 7429 goto err_unpin;
8c9f3aaf 7430
6d90c952
DV		 7431 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7432 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7433 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7434 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7435
dc257cf1
DV		 7436 /* Contrary to the suggestions in the documentation,
7437 * "Enable Panel Fitter" does not seem to be required when page
7438 * flipping with a non-native mode, and worse causes a normal
7439 * modeset to fail.
7440 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7441 */
7442 pf = 0;
8c9f3aaf 7443 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7444 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7445
7446 intel_mark_page_flip_active(intel_crtc);
6d90c952 7447 intel_ring_advance(ring);
83d4092b
CW		 7448 return 0;
7449
7450err_unpin:
7451 intel_unpin_fb_obj(obj);
7452err:
8c9f3aaf
JB		 7453 return ret;
7454}
7455
7c9017e5
JB		 7456/*
7457 * On gen7 we currently use the blit ring because (in early silicon at least)
7458 * the render ring doesn't give us interrpts for page flip completion, which
7459 * means clients will hang after the first flip is queued. Fortunately the
7460 * blit ring generates interrupts properly, so use it instead.
7461 */
7462static int intel_gen7_queue_flip(struct drm_device *dev,
7463 struct drm_crtc *crtc,
7464 struct drm_framebuffer *fb,
7465 struct drm_i915_gem_object *obj)
7466{
7467 struct drm_i915_private *dev_priv = dev->dev_private;
7468 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7469 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7470 uint32_t plane_bit = 0;
7c9017e5
JB		 7471 int ret;
7472
7473 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7474 if (ret)
83d4092b 7475 goto err;
7c9017e5 7476
cb05d8de
DV		 7477 switch(intel_crtc->plane) {
7478 case PLANE_A:
7479 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7480 break;
7481 case PLANE_B:
7482 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7483 break;
7484 case PLANE_C:
7485 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7486 break;
7487 default:
7488 WARN_ONCE(1, "unknown plane in flip command\n");
7489 ret = -ENODEV;
ab3951eb 7490 goto err_unpin;
cb05d8de
DV		 7491 }
7492
7c9017e5
JB		 7493 ret = intel_ring_begin(ring, 4);
7494 if (ret)
83d4092b 7495 goto err_unpin;
7c9017e5 7496
cb05d8de 7497 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7498 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7499 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7500 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7501
7502 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7503 intel_ring_advance(ring);
83d4092b
CW		 7504 return 0;
7505
7506err_unpin:
7507 intel_unpin_fb_obj(obj);
7508err:
7c9017e5
JB		 7509 return ret;
7510}
7511
8c9f3aaf
JB		 7512static int intel_default_queue_flip(struct drm_device *dev,
7513 struct drm_crtc *crtc,
7514 struct drm_framebuffer *fb,
7515 struct drm_i915_gem_object *obj)
7516{
7517 return -ENODEV;
7518}
7519
6b95a207
KH		 7520static int intel_crtc_page_flip(struct drm_crtc *crtc,
7521 struct drm_framebuffer *fb,
7522 struct drm_pending_vblank_event *event)
7523{
7524 struct drm_device *dev = crtc->dev;
7525 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7526 struct drm_framebuffer *old_fb = crtc->fb;
7527 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7528 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7529 struct intel_unpin_work *work;
8c9f3aaf 7530 unsigned long flags;
52e68630 7531 int ret;
6b95a207 7532
e6a595d2
VS		 7533 /* Can't change pixel format via MI display flips. */
7534 if (fb->pixel_format != crtc->fb->pixel_format)
7535 return -EINVAL;
7536
7537 /*
7538 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7539 * Note that pitch changes could also affect these register.
7540 */
7541 if (INTEL_INFO(dev)->gen > 3 &&
7542 (fb->offsets[0] != crtc->fb->offsets[0] ||
7543 fb->pitches[0] != crtc->fb->pitches[0]))
7544 return -EINVAL;
7545
6b95a207
KH		 7546 work = kzalloc(sizeof *work, GFP_KERNEL);
7547 if (work == NULL)
7548 return -ENOMEM;
7549
6b95a207 7550 work->event = event;
b4a98e57 7551 work->crtc = crtc;
4a35f83b 7552 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7553 INIT_WORK(&work->work, intel_unpin_work_fn);
7554
7317c75e
JB		 7555 ret = drm_vblank_get(dev, intel_crtc->pipe);
7556 if (ret)
7557 goto free_work;
7558
6b95a207
KH		 7559 /* We borrow the event spin lock for protecting unpin_work */
7560 spin_lock_irqsave(&dev->event_lock, flags);
7561 if (intel_crtc->unpin_work) {
7562 spin_unlock_irqrestore(&dev->event_lock, flags);
7563 kfree(work);
7317c75e 7564 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7565
7566 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7567 return -EBUSY;
7568 }
7569 intel_crtc->unpin_work = work;
7570 spin_unlock_irqrestore(&dev->event_lock, flags);
7571
b4a98e57
CW		 7572 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7573 flush_workqueue(dev_priv->wq);
7574
79158103
CW		 7575 ret = i915_mutex_lock_interruptible(dev);
7576 if (ret)
7577 goto cleanup;
6b95a207 7578
75dfca80 7579 /* Reference the objects for the scheduled work. */
05394f39
CW		 7580 drm_gem_object_reference(&work->old_fb_obj->base);
7581 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7582
7583 crtc->fb = fb;
96b099fd 7584
e1f99ce6 7585 work->pending_flip_obj = obj;
e1f99ce6 7586
4e5359cd
SF		 7587 work->enable_stall_check = true;
7588
b4a98e57 7589 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7590 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7591
8c9f3aaf
JB		 7592 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7593 if (ret)
7594 goto cleanup_pending;
6b95a207 7595
7782de3b 7596 intel_disable_fbc(dev);
f047e395 7597 intel_mark_fb_busy(obj);
6b95a207
KH		 7598 mutex_unlock(&dev->struct_mutex);
7599
e5510fac
JB		 7600 trace_i915_flip_request(intel_crtc->plane, obj);
7601
6b95a207 7602 return 0;
96b099fd 7603
8c9f3aaf 7604cleanup_pending:
b4a98e57 7605 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7606 crtc->fb = old_fb;
05394f39
CW		 7607 drm_gem_object_unreference(&work->old_fb_obj->base);
7608 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7609 mutex_unlock(&dev->struct_mutex);
7610
79158103 7611cleanup:
96b099fd
CW		 7612 spin_lock_irqsave(&dev->event_lock, flags);
7613 intel_crtc->unpin_work = NULL;
7614 spin_unlock_irqrestore(&dev->event_lock, flags);
7615
7317c75e
JB		 7616 drm_vblank_put(dev, intel_crtc->pipe);
7617free_work:
96b099fd
CW		 7618 kfree(work);
7619
7620 return ret;
6b95a207
KH		 7621}
7622
f6e5b160 7623static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7624 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7625 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7626};
7627
6ed0f796 7628bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7629{
6ed0f796
DV		 7630 struct intel_encoder *other_encoder;
7631 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7632
6ed0f796
DV		 7633 if (WARN_ON(!crtc))
7634 return false;
7635
7636 list_for_each_entry(other_encoder,
7637 &crtc->dev->mode_config.encoder_list,
7638 base.head) {
7639
7640 if (&other_encoder->new_crtc->base != crtc ||
7641 encoder == other_encoder)
7642 continue;
7643 else
7644 return true;
f47166d2
CW		 7645 }
7646
6ed0f796
DV		 7647 return false;
7648}
47f1c6c9 7649
50f56119
DV		 7650static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7651 struct drm_crtc *crtc)
7652{
7653 struct drm_device *dev;
7654 struct drm_crtc *tmp;
7655 int crtc_mask = 1;
47f1c6c9 7656
50f56119 7657 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7658
50f56119 7659 dev = crtc->dev;
47f1c6c9 7660
50f56119
DV		 7661 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7662 if (tmp == crtc)
7663 break;
7664 crtc_mask <<= 1;
7665 }
47f1c6c9 7666
50f56119
DV		 7667 if (encoder->possible_crtcs & crtc_mask)
7668 return true;
7669 return false;
47f1c6c9 7670}
79e53945 7671
9a935856
DV		 7672/**
7673 * intel_modeset_update_staged_output_state
7674 *
7675 * Updates the staged output configuration state, e.g. after we've read out the
7676 * current hw state.
7677 */
7678static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7679{
9a935856
DV		 7680 struct intel_encoder *encoder;
7681 struct intel_connector *connector;
f6e5b160 7682
9a935856
DV		 7683 list_for_each_entry(connector, &dev->mode_config.connector_list,
7684 base.head) {
7685 connector->new_encoder =
7686 to_intel_encoder(connector->base.encoder);
7687 }
f6e5b160 7688
9a935856
DV		 7689 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7690 base.head) {
7691 encoder->new_crtc =
7692 to_intel_crtc(encoder->base.crtc);
7693 }
f6e5b160
CW		 7694}
7695
9a935856
DV		 7696/**
7697 * intel_modeset_commit_output_state
7698 *
7699 * This function copies the stage display pipe configuration to the real one.
7700 */
7701static void intel_modeset_commit_output_state(struct drm_device *dev)
7702{
7703 struct intel_encoder *encoder;
7704 struct intel_connector *connector;
f6e5b160 7705
9a935856
DV		 7706 list_for_each_entry(connector, &dev->mode_config.connector_list,
7707 base.head) {
7708 connector->base.encoder = &connector->new_encoder->base;
7709 }
f6e5b160 7710
9a935856
DV		 7711 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7712 base.head) {
7713 encoder->base.crtc = &encoder->new_crtc->base;
7714 }
7715}
7716
050f7aeb
DV		 7717static void
7718connected_sink_compute_bpp(struct intel_connector * connector,
7719 struct intel_crtc_config *pipe_config)
7720{
7721 int bpp = pipe_config->pipe_bpp;
7722
7723 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7724 connector->base.base.id,
7725 drm_get_connector_name(&connector->base));
7726
7727 /* Don't use an invalid EDID bpc value */
7728 if (connector->base.display_info.bpc &&
7729 connector->base.display_info.bpc * 3 < bpp) {
7730 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7731 bpp, connector->base.display_info.bpc*3);
7732 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7733 }
7734
7735 /* Clamp bpp to 8 on screens without EDID 1.4 */
7736 if (connector->base.display_info.bpc == 0 && bpp > 24) {
7737 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7738 bpp);
7739 pipe_config->pipe_bpp = 24;
7740 }
7741}
7742
4e53c2e0 7743static int
050f7aeb
DV		 7744compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7745 struct drm_framebuffer *fb,
7746 struct intel_crtc_config *pipe_config)
4e53c2e0 7747{
050f7aeb
DV		 7748 struct drm_device *dev = crtc->base.dev;
7749 struct intel_connector *connector;
4e53c2e0
DV		 7750 int bpp;
7751
d42264b1
DV		 7752 switch (fb->pixel_format) {
7753 case DRM_FORMAT_C8:
4e53c2e0
DV		 7754 bpp = 8*3; /* since we go through a colormap */
7755 break;
d42264b1
DV		 7756 case DRM_FORMAT_XRGB1555:
7757 case DRM_FORMAT_ARGB1555:
7758 /* checked in intel_framebuffer_init already */
7759 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7760 return -EINVAL;
7761 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 7762 bpp = 6*3; /* min is 18bpp */
7763 break;
d42264b1
DV		 7764 case DRM_FORMAT_XBGR8888:
7765 case DRM_FORMAT_ABGR8888:
7766 /* checked in intel_framebuffer_init already */
7767 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7768 return -EINVAL;
7769 case DRM_FORMAT_XRGB8888:
7770 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 7771 bpp = 8*3;
7772 break;
d42264b1
DV		 7773 case DRM_FORMAT_XRGB2101010:
7774 case DRM_FORMAT_ARGB2101010:
7775 case DRM_FORMAT_XBGR2101010:
7776 case DRM_FORMAT_ABGR2101010:
7777 /* checked in intel_framebuffer_init already */
7778 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 7779 return -EINVAL;
4e53c2e0
DV		 7780 bpp = 10*3;
7781 break;
baba133a 7782 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 7783 default:
7784 DRM_DEBUG_KMS("unsupported depth\n");
7785 return -EINVAL;
7786 }
7787
4e53c2e0
DV		 7788 pipe_config->pipe_bpp = bpp;
7789
7790 /* Clamp display bpp to EDID value */
7791 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 7792 base.head) {
1b829e05
DV		 7793 if (!connector->new_encoder ||
7794 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 7795 continue;
7796
050f7aeb 7797 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 7798 }
7799
7800 return bpp;
7801}
7802
c0b03411
DV		 7803static void intel_dump_pipe_config(struct intel_crtc *crtc,
7804 struct intel_crtc_config *pipe_config,
7805 const char *context)
7806{
7807 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7808 context, pipe_name(crtc->pipe));
7809
7810 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7811 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7812 pipe_config->pipe_bpp, pipe_config->dither);
7813 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7814 pipe_config->has_pch_encoder,
7815 pipe_config->fdi_lanes,
7816 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7817 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7818 pipe_config->fdi_m_n.tu);
7819 DRM_DEBUG_KMS("requested mode:\n");
7820 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7821 DRM_DEBUG_KMS("adjusted mode:\n");
7822 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7823 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7824 pipe_config->gmch_pfit.control,
7825 pipe_config->gmch_pfit.pgm_ratios,
7826 pipe_config->gmch_pfit.lvds_border_bits);
7827 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7828 pipe_config->pch_pfit.pos,
7829 pipe_config->pch_pfit.size);
42db64ef 7830 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
c0b03411
DV		 7831}
7832
b8cecdf5
DV		 7833static struct intel_crtc_config *
7834intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 7835 struct drm_framebuffer *fb,
b8cecdf5 7836 struct drm_display_mode *mode)
ee7b9f93 7837{
7758a113 7838 struct drm_device *dev = crtc->dev;
7758a113
DV		 7839 struct drm_encoder_helper_funcs *encoder_funcs;
7840 struct intel_encoder *encoder;
b8cecdf5 7841 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 7842 int plane_bpp, ret = -EINVAL;
7843 bool retry = true;
ee7b9f93 7844
b8cecdf5
DV		 7845 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7846 if (!pipe_config)
7758a113
DV		 7847 return ERR_PTR(-ENOMEM);
7848
b8cecdf5
DV		 7849 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7850 drm_mode_copy(&pipe_config->requested_mode, mode);
eccb140b 7851 pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe;
b8cecdf5 7852
050f7aeb
DV		 7853 /* Compute a starting value for pipe_config->pipe_bpp taking the source
7854 * plane pixel format and any sink constraints into account. Returns the
7855 * source plane bpp so that dithering can be selected on mismatches
7856 * after encoders and crtc also have had their say. */
7857 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7858 fb, pipe_config);
4e53c2e0
DV		 7859 if (plane_bpp < 0)
7860 goto fail;
7861
e29c22c0 7862encoder_retry:
7758a113
DV		 7863 /* Pass our mode to the connectors and the CRTC to give them a chance to
7864 * adjust it according to limitations or connector properties, and also
7865 * a chance to reject the mode entirely.
47f1c6c9 7866 */
7758a113
DV		 7867 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7868 base.head) {
47f1c6c9 7869
7758a113
DV		 7870 if (&encoder->new_crtc->base != crtc)
7871 continue;
7ae89233
DV		 7872
7873 if (encoder->compute_config) {
7874 if (!(encoder->compute_config(encoder, pipe_config))) {
7875 DRM_DEBUG_KMS("Encoder config failure\n");
7876 goto fail;
7877 }
7878
7879 continue;
7880 }
7881
7758a113 7882 encoder_funcs = encoder->base.helper_private;
b8cecdf5
DV		 7883 if (!(encoder_funcs->mode_fixup(&encoder->base,
7884 &pipe_config->requested_mode,
7885 &pipe_config->adjusted_mode))) {
7758a113
DV		 7886 DRM_DEBUG_KMS("Encoder fixup failed\n");
7887 goto fail;
7888 }
ee7b9f93 7889 }
47f1c6c9 7890
e29c22c0
DV		 7891 ret = intel_crtc_compute_config(crtc, pipe_config);
7892 if (ret < 0) {
7758a113
DV		 7893 DRM_DEBUG_KMS("CRTC fixup failed\n");
7894 goto fail;
ee7b9f93 7895 }
e29c22c0
DV		 7896
7897 if (ret == RETRY) {
7898 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7899 ret = -EINVAL;
7900 goto fail;
7901 }
7902
7903 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7904 retry = false;
7905 goto encoder_retry;
7906 }
7907
4e53c2e0
DV		 7908 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7909 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7910 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7911
b8cecdf5 7912 return pipe_config;
7758a113 7913fail:
b8cecdf5 7914 kfree(pipe_config);
e29c22c0 7915 return ERR_PTR(ret);
ee7b9f93 7916}
47f1c6c9 7917
e2e1ed41
DV		 7918/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7919 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7920static void
7921intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7922 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7923{
7924 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7925 struct drm_device *dev = crtc->dev;
7926 struct intel_encoder *encoder;
7927 struct intel_connector *connector;
7928 struct drm_crtc *tmp_crtc;
79e53945 7929
e2e1ed41 7930 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7931
e2e1ed41
DV		 7932 /* Check which crtcs have changed outputs connected to them, these need
7933 * to be part of the prepare_pipes mask. We don't (yet) support global
7934 * modeset across multiple crtcs, so modeset_pipes will only have one
7935 * bit set at most. */
7936 list_for_each_entry(connector, &dev->mode_config.connector_list,
7937 base.head) {
7938 if (connector->base.encoder == &connector->new_encoder->base)
7939 continue;
79e53945 7940
e2e1ed41
DV		 7941 if (connector->base.encoder) {
7942 tmp_crtc = connector->base.encoder->crtc;
7943
7944 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7945 }
7946
7947 if (connector->new_encoder)
7948 *prepare_pipes |=
7949 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7950 }
7951
e2e1ed41
DV		 7952 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7953 base.head) {
7954 if (encoder->base.crtc == &encoder->new_crtc->base)
7955 continue;
7956
7957 if (encoder->base.crtc) {
7958 tmp_crtc = encoder->base.crtc;
7959
7960 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7961 }
7962
7963 if (encoder->new_crtc)
7964 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7965 }
7966
e2e1ed41
DV		 7967 /* Check for any pipes that will be fully disabled ... */
7968 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7969 base.head) {
7970 bool used = false;
22fd0fab 7971
e2e1ed41
DV		 7972 /* Don't try to disable disabled crtcs. */
7973 if (!intel_crtc->base.enabled)
7974 continue;
7e7d76c3 7975
e2e1ed41
DV		 7976 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7977 base.head) {
7978 if (encoder->new_crtc == intel_crtc)
7979 used = true;
7980 }
7981
7982 if (!used)
7983 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7984 }
7985
e2e1ed41
DV		 7986
7987 /* set_mode is also used to update properties on life display pipes. */
7988 intel_crtc = to_intel_crtc(crtc);
7989 if (crtc->enabled)
7990 *prepare_pipes |= 1 << intel_crtc->pipe;
7991
b6c5164d
DV		 7992 /*
7993 * For simplicity do a full modeset on any pipe where the output routing
7994 * changed. We could be more clever, but that would require us to be
7995 * more careful with calling the relevant encoder->mode_set functions.
7996 */
e2e1ed41
DV		 7997 if (*prepare_pipes)
7998 *modeset_pipes = *prepare_pipes;
7999
8000 /* ... and mask these out. */
8001 *modeset_pipes &= ~(*disable_pipes);
8002 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 8003
8004 /*
8005 * HACK: We don't (yet) fully support global modesets. intel_set_config
8006 * obies this rule, but the modeset restore mode of
8007 * intel_modeset_setup_hw_state does not.
8008 */
8009 *modeset_pipes &= 1 << intel_crtc->pipe;
8010 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 8011
8012 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8013 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 8014}
79e53945 8015
ea9d758d 8016static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 8017{
ea9d758d 8018 struct drm_encoder *encoder;
f6e5b160 8019 struct drm_device *dev = crtc->dev;
f6e5b160 8020
ea9d758d
DV		 8021 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8022 if (encoder->crtc == crtc)
8023 return true;
8024
8025 return false;
8026}
8027
8028static void
8029intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8030{
8031 struct intel_encoder *intel_encoder;
8032 struct intel_crtc *intel_crtc;
8033 struct drm_connector *connector;
8034
8035 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8036 base.head) {
8037 if (!intel_encoder->base.crtc)
8038 continue;
8039
8040 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8041
8042 if (prepare_pipes & (1 << intel_crtc->pipe))
8043 intel_encoder->connectors_active = false;
8044 }
8045
8046 intel_modeset_commit_output_state(dev);
8047
8048 /* Update computed state. */
8049 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8050 base.head) {
8051 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8052 }
8053
8054 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8055 if (!connector->encoder || !connector->encoder->crtc)
8056 continue;
8057
8058 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8059
8060 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8061 struct drm_property *dpms_property =
8062 dev->mode_config.dpms_property;
8063
ea9d758d 8064 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8065 drm_object_property_set_value(&connector->base,
68d34720
DV		 8066 dpms_property,
8067 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8068
8069 intel_encoder = to_intel_encoder(connector->encoder);
8070 intel_encoder->connectors_active = true;
8071 }
8072 }
8073
8074}
8075
25c5b266
DV		 8076#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8077 list_for_each_entry((intel_crtc), \
8078 &(dev)->mode_config.crtc_list, \
8079 base.head) \
0973f18f 8080 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8081
0e8ffe1b 8082static bool
2fa2fe9a
DV		 8083intel_pipe_config_compare(struct drm_device *dev,
8084 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8085 struct intel_crtc_config *pipe_config)
8086{
08a24034
DV		 8087#define PIPE_CONF_CHECK_I(name) \
8088 if (current_config->name != pipe_config->name) { \
8089 DRM_ERROR("mismatch in " #name " " \
8090 "(expected %i, found %i)\n", \
8091 current_config->name, \
8092 pipe_config->name); \
8093 return false; \
88adfff1
DV		 8094 }
8095
1bd1bd80
DV		 8096#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8097 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8098 DRM_ERROR("mismatch in " #name " " \
8099 "(expected %i, found %i)\n", \
8100 current_config->name & (mask), \
8101 pipe_config->name & (mask)); \
8102 return false; \
8103 }
8104
eccb140b
DV		 8105 PIPE_CONF_CHECK_I(cpu_transcoder);
8106
08a24034
DV		 8107 PIPE_CONF_CHECK_I(has_pch_encoder);
8108 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8109 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8110 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8111 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8112 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8113 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8114
1bd1bd80
DV		 8115 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8116 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8117 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8118 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8119 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8120 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8121
8122 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8123 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8124 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8125 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8126 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8127 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8128
8129 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8130 DRM_MODE_FLAG_INTERLACE);
8131
045ac3b5
JB		 8132 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8133 DRM_MODE_FLAG_PHSYNC);
8134 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8135 DRM_MODE_FLAG_NHSYNC);
8136 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8137 DRM_MODE_FLAG_PVSYNC);
8138 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8139 DRM_MODE_FLAG_NVSYNC);
8140
1bd1bd80
DV		 8141 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8142 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8143
2fa2fe9a
DV		 8144 PIPE_CONF_CHECK_I(gmch_pfit.control);
8145 /* pfit ratios are autocomputed by the hw on gen4+ */
8146 if (INTEL_INFO(dev)->gen < 4)
8147 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8148 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8149 PIPE_CONF_CHECK_I(pch_pfit.pos);
8150 PIPE_CONF_CHECK_I(pch_pfit.size);
8151
42db64ef
PZ		 8152 PIPE_CONF_CHECK_I(ips_enabled);
8153
08a24034 8154#undef PIPE_CONF_CHECK_I
1bd1bd80 8155#undef PIPE_CONF_CHECK_FLAGS
627eb5a3 8156
0e8ffe1b
DV		 8157 return true;
8158}
8159
b980514c 8160void
8af6cf88
DV		 8161intel_modeset_check_state(struct drm_device *dev)
8162{
0e8ffe1b 8163 drm_i915_private_t *dev_priv = dev->dev_private;
8af6cf88
DV		 8164 struct intel_crtc *crtc;
8165 struct intel_encoder *encoder;
8166 struct intel_connector *connector;
0e8ffe1b 8167 struct intel_crtc_config pipe_config;
8af6cf88
DV		 8168
8169 list_for_each_entry(connector, &dev->mode_config.connector_list,
8170 base.head) {
8171 /* This also checks the encoder/connector hw state with the
8172 * ->get_hw_state callbacks. */
8173 intel_connector_check_state(connector);
8174
8175 WARN(&connector->new_encoder->base != connector->base.encoder,
8176 "connector's staged encoder doesn't match current encoder\n");
8177 }
8178
8179 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8180 base.head) {
8181 bool enabled = false;
8182 bool active = false;
8183 enum pipe pipe, tracked_pipe;
8184
8185 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8186 encoder->base.base.id,
8187 drm_get_encoder_name(&encoder->base));
8188
8189 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8190 "encoder's stage crtc doesn't match current crtc\n");
8191 WARN(encoder->connectors_active && !encoder->base.crtc,
8192 "encoder's active_connectors set, but no crtc\n");
8193
8194 list_for_each_entry(connector, &dev->mode_config.connector_list,
8195 base.head) {
8196 if (connector->base.encoder != &encoder->base)
8197 continue;
8198 enabled = true;
8199 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8200 active = true;
8201 }
8202 WARN(!!encoder->base.crtc != enabled,
8203 "encoder's enabled state mismatch "
8204 "(expected %i, found %i)\n",
8205 !!encoder->base.crtc, enabled);
8206 WARN(active && !encoder->base.crtc,
8207 "active encoder with no crtc\n");
8208
8209 WARN(encoder->connectors_active != active,
8210 "encoder's computed active state doesn't match tracked active state "
8211 "(expected %i, found %i)\n", active, encoder->connectors_active);
8212
8213 active = encoder->get_hw_state(encoder, &pipe);
8214 WARN(active != encoder->connectors_active,
8215 "encoder's hw state doesn't match sw tracking "
8216 "(expected %i, found %i)\n",
8217 encoder->connectors_active, active);
8218
8219 if (!encoder->base.crtc)
8220 continue;
8221
8222 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8223 WARN(active && pipe != tracked_pipe,
8224 "active encoder's pipe doesn't match"
8225 "(expected %i, found %i)\n",
8226 tracked_pipe, pipe);
8227
8228 }
8229
8230 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8231 base.head) {
8232 bool enabled = false;
8233 bool active = false;
8234
045ac3b5
JB		 8235 memset(&pipe_config, 0, sizeof(pipe_config));
8236
8af6cf88
DV		 8237 DRM_DEBUG_KMS("[CRTC:%d]\n",
8238 crtc->base.base.id);
8239
8240 WARN(crtc->active && !crtc->base.enabled,
8241 "active crtc, but not enabled in sw tracking\n");
8242
8243 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8244 base.head) {
8245 if (encoder->base.crtc != &crtc->base)
8246 continue;
8247 enabled = true;
8248 if (encoder->connectors_active)
8249 active = true;
045ac3b5
JB		 8250 if (encoder->get_config)
8251 encoder->get_config(encoder, &pipe_config);
8af6cf88
DV		 8252 }
8253 WARN(active != crtc->active,
8254 "crtc's computed active state doesn't match tracked active state "
8255 "(expected %i, found %i)\n", active, crtc->active);
8256 WARN(enabled != crtc->base.enabled,
8257 "crtc's computed enabled state doesn't match tracked enabled state "
8258 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8259
0e8ffe1b
DV		 8260 active = dev_priv->display.get_pipe_config(crtc,
8261 &pipe_config);
8262 WARN(crtc->active != active,
8263 "crtc active state doesn't match with hw state "
8264 "(expected %i, found %i)\n", crtc->active, active);
8265
c0b03411
DV		 8266 if (active &&
8267 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8268 WARN(1, "pipe state doesn't match!\n");
8269 intel_dump_pipe_config(crtc, &pipe_config,
8270 "[hw state]");
8271 intel_dump_pipe_config(crtc, &crtc->config,
8272 "[sw state]");
8273 }
8af6cf88
DV		 8274 }
8275}
8276
f30da187
DV		 8277static int __intel_set_mode(struct drm_crtc *crtc,
8278 struct drm_display_mode *mode,
8279 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 8280{
8281 struct drm_device *dev = crtc->dev;
dbf2b54e 8282 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 8283 struct drm_display_mode *saved_mode, *saved_hwmode;
8284 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 8285 struct intel_crtc *intel_crtc;
8286 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 8287 int ret = 0;
a6778b3c 8288
3ac18232 8289 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 8290 if (!saved_mode)
8291 return -ENOMEM;
3ac18232 8292 saved_hwmode = saved_mode + 1;
a6778b3c 8293
e2e1ed41 8294 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 8295 &prepare_pipes, &disable_pipes);
8296
3ac18232
TG		 8297 *saved_hwmode = crtc->hwmode;
8298 *saved_mode = crtc->mode;
a6778b3c 8299
25c5b266
DV		 8300 /* Hack: Because we don't (yet) support global modeset on multiple
8301 * crtcs, we don't keep track of the new mode for more than one crtc.
8302 * Hence simply check whether any bit is set in modeset_pipes in all the
8303 * pieces of code that are not yet converted to deal with mutliple crtcs
8304 * changing their mode at the same time. */
25c5b266 8305 if (modeset_pipes) {
4e53c2e0 8306 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 8307 if (IS_ERR(pipe_config)) {
8308 ret = PTR_ERR(pipe_config);
8309 pipe_config = NULL;
8310
3ac18232 8311 goto out;
25c5b266 8312 }
c0b03411
DV		 8313 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8314 "[modeset]");
25c5b266 8315 }
a6778b3c 8316
460da916
DV		 8317 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8318 intel_crtc_disable(&intel_crtc->base);
8319
ea9d758d
DV		 8320 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8321 if (intel_crtc->base.enabled)
8322 dev_priv->display.crtc_disable(&intel_crtc->base);
8323 }
a6778b3c 8324
6c4c86f5
DV		 8325 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8326 * to set it here already despite that we pass it down the callchain.
f6e5b160 8327 */
b8cecdf5 8328 if (modeset_pipes) {
25c5b266 8329 crtc->mode = *mode;
b8cecdf5
DV		 8330 /* mode_set/enable/disable functions rely on a correct pipe
8331 * config. */
8332 to_intel_crtc(crtc)->config = *pipe_config;
8333 }
7758a113 8334
ea9d758d
DV		 8335 /* Only after disabling all output pipelines that will be changed can we
8336 * update the the output configuration. */
8337 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 8338
47fab737
DV		 8339 if (dev_priv->display.modeset_global_resources)
8340 dev_priv->display.modeset_global_resources(dev);
8341
a6778b3c
DV		 8342 /* Set up the DPLL and any encoders state that needs to adjust or depend
8343 * on the DPLL.
f6e5b160 8344 */
25c5b266 8345 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 8346 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 8347 x, y, fb);
8348 if (ret)
8349 goto done;
a6778b3c
DV		 8350 }
8351
8352 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 8353 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8354 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 8355
25c5b266
DV		 8356 if (modeset_pipes) {
8357 /* Store real post-adjustment hardware mode. */
b8cecdf5 8358 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 8359
25c5b266
DV		 8360 /* Calculate and store various constants which
8361 * are later needed by vblank and swap-completion
8362 * timestamping. They are derived from true hwmode.
8363 */
8364 drm_calc_timestamping_constants(crtc);
8365 }
a6778b3c
DV		 8366
8367 /* FIXME: add subpixel order */
8368done:
c0c36b94 8369 if (ret && crtc->enabled) {
3ac18232
TG		 8370 crtc->hwmode = *saved_hwmode;
8371 crtc->mode = *saved_mode;
a6778b3c
DV		 8372 }
8373
3ac18232 8374out:
b8cecdf5 8375 kfree(pipe_config);
3ac18232 8376 kfree(saved_mode);
a6778b3c 8377 return ret;
f6e5b160
CW		 8378}
8379
f30da187
DV		 8380int intel_set_mode(struct drm_crtc *crtc,
8381 struct drm_display_mode *mode,
8382 int x, int y, struct drm_framebuffer *fb)
8383{
8384 int ret;
8385
8386 ret = __intel_set_mode(crtc, mode, x, y, fb);
8387
8388 if (ret == 0)
8389 intel_modeset_check_state(crtc->dev);
8390
8391 return ret;
8392}
8393
c0c36b94
CW		 8394void intel_crtc_restore_mode(struct drm_crtc *crtc)
8395{
8396 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8397}
8398
25c5b266
DV		 8399#undef for_each_intel_crtc_masked
8400
d9e55608
DV		 8401static void intel_set_config_free(struct intel_set_config *config)
8402{
8403 if (!config)
8404 return;
8405
1aa4b628
DV		 8406 kfree(config->save_connector_encoders);
8407 kfree(config->save_encoder_crtcs);
d9e55608
DV		 8408 kfree(config);
8409}
8410
85f9eb71
DV		 8411static int intel_set_config_save_state(struct drm_device *dev,
8412 struct intel_set_config *config)
8413{
85f9eb71
DV		 8414 struct drm_encoder *encoder;
8415 struct drm_connector *connector;
8416 int count;
8417
1aa4b628
DV		 8418 config->save_encoder_crtcs =
8419 kcalloc(dev->mode_config.num_encoder,
8420 sizeof(struct drm_crtc *), GFP_KERNEL);
8421 if (!config->save_encoder_crtcs)
85f9eb71
DV		 8422 return -ENOMEM;
8423
1aa4b628
DV		 8424 config->save_connector_encoders =
8425 kcalloc(dev->mode_config.num_connector,
8426 sizeof(struct drm_encoder *), GFP_KERNEL);
8427 if (!config->save_connector_encoders)
85f9eb71
DV		 8428 return -ENOMEM;
8429
8430 /* Copy data. Note that driver private data is not affected.
8431 * Should anything bad happen only the expected state is
8432 * restored, not the drivers personal bookkeeping.
8433 */
85f9eb71
DV		 8434 count = 0;
8435 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 8436 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 8437 }
8438
8439 count = 0;
8440 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 8441 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 8442 }
8443
8444 return 0;
8445}
8446
8447static void intel_set_config_restore_state(struct drm_device *dev,
8448 struct intel_set_config *config)
8449{
9a935856
DV		 8450 struct intel_encoder *encoder;
8451 struct intel_connector *connector;
85f9eb71
DV		 8452 int count;
8453
85f9eb71 8454 count = 0;
9a935856
DV		 8455 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8456 encoder->new_crtc =
8457 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 8458 }
8459
8460 count = 0;
9a935856
DV		 8461 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8462 connector->new_encoder =
8463 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 8464 }
8465}
8466
5e2b584e
DV		 8467static void
8468intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8469 struct intel_set_config *config)
8470{
8471
8472 /* We should be able to check here if the fb has the same properties
8473 * and then just flip_or_move it */
8474 if (set->crtc->fb != set->fb) {
8475 /* If we have no fb then treat it as a full mode set */
8476 if (set->crtc->fb == NULL) {
8477 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8478 config->mode_changed = true;
8479 } else if (set->fb == NULL) {
8480 config->mode_changed = true;
72f4901e
DV		 8481 } else if (set->fb->pixel_format !=
8482 set->crtc->fb->pixel_format) {
5e2b584e
DV		 8483 config->mode_changed = true;
8484 } else
8485 config->fb_changed = true;
8486 }
8487
835c5873 8488 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 8489 config->fb_changed = true;
8490
8491 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8492 DRM_DEBUG_KMS("modes are different, full mode set\n");
8493 drm_mode_debug_printmodeline(&set->crtc->mode);
8494 drm_mode_debug_printmodeline(set->mode);
8495 config->mode_changed = true;
8496 }
8497}
8498
2e431051 8499static int
9a935856
DV		 8500intel_modeset_stage_output_state(struct drm_device *dev,
8501 struct drm_mode_set *set,
8502 struct intel_set_config *config)
50f56119 8503{
85f9eb71 8504 struct drm_crtc *new_crtc;
9a935856
DV		 8505 struct intel_connector *connector;
8506 struct intel_encoder *encoder;
2e431051 8507 int count, ro;
50f56119 8508
9abdda74 8509 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 8510 * of connectors. For paranoia, double-check this. */
8511 WARN_ON(!set->fb && (set->num_connectors != 0));
8512 WARN_ON(set->fb && (set->num_connectors == 0));
8513
50f56119 8514 count = 0;
9a935856
DV		 8515 list_for_each_entry(connector, &dev->mode_config.connector_list,
8516 base.head) {
8517 /* Otherwise traverse passed in connector list and get encoders
8518 * for them. */
50f56119 8519 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 8520 if (set->connectors[ro] == &connector->base) {
8521 connector->new_encoder = connector->encoder;
50f56119
DV		 8522 break;
8523 }
8524 }
8525
9a935856
DV		 8526 /* If we disable the crtc, disable all its connectors. Also, if
8527 * the connector is on the changing crtc but not on the new
8528 * connector list, disable it. */
8529 if ((!set->fb || ro == set->num_connectors) &&
8530 connector->base.encoder &&
8531 connector->base.encoder->crtc == set->crtc) {
8532 connector->new_encoder = NULL;
8533
8534 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8535 connector->base.base.id,
8536 drm_get_connector_name(&connector->base));
8537 }
8538
8539
8540 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8541 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8542 config->mode_changed = true;
50f56119
DV		 8543 }
8544 }
9a935856 8545 /* connector->new_encoder is now updated for all connectors. */
50f56119 8546
9a935856 8547 /* Update crtc of enabled connectors. */
50f56119 8548 count = 0;
9a935856
DV		 8549 list_for_each_entry(connector, &dev->mode_config.connector_list,
8550 base.head) {
8551 if (!connector->new_encoder)
50f56119
DV		 8552 continue;
8553
9a935856 8554 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8555
8556 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8557 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8558 new_crtc = set->crtc;
8559 }
8560
8561 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8562 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8563 new_crtc)) {
5e2b584e 8564 return -EINVAL;
50f56119 8565 }
9a935856
DV		 8566 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8567
8568 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8569 connector->base.base.id,
8570 drm_get_connector_name(&connector->base),
8571 new_crtc->base.id);
8572 }
8573
8574 /* Check for any encoders that needs to be disabled. */
8575 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8576 base.head) {
8577 list_for_each_entry(connector,
8578 &dev->mode_config.connector_list,
8579 base.head) {
8580 if (connector->new_encoder == encoder) {
8581 WARN_ON(!connector->new_encoder->new_crtc);
8582
8583 goto next_encoder;
8584 }
8585 }
8586 encoder->new_crtc = NULL;
8587next_encoder:
8588 /* Only now check for crtc changes so we don't miss encoders
8589 * that will be disabled. */
8590 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8591 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8592 config->mode_changed = true;
50f56119
DV		 8593 }
8594 }
9a935856 8595 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8596
2e431051
DV		 8597 return 0;
8598}
8599
8600static int intel_crtc_set_config(struct drm_mode_set *set)
8601{
8602 struct drm_device *dev;
2e431051
DV		 8603 struct drm_mode_set save_set;
8604 struct intel_set_config *config;
8605 int ret;
2e431051 8606
8d3e375e
DV		 8607 BUG_ON(!set);
8608 BUG_ON(!set->crtc);
8609 BUG_ON(!set->crtc->helper_private);
2e431051 8610
7e53f3a4
DV		 8611 /* Enforce sane interface api - has been abused by the fb helper. */
8612 BUG_ON(!set->mode && set->fb);
8613 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 8614
2e431051
DV		 8615 if (set->fb) {
8616 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8617 set->crtc->base.id, set->fb->base.id,
8618 (int)set->num_connectors, set->x, set->y);
8619 } else {
8620 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8621 }
8622
8623 dev = set->crtc->dev;
8624
8625 ret = -ENOMEM;
8626 config = kzalloc(sizeof(*config), GFP_KERNEL);
8627 if (!config)
8628 goto out_config;
8629
8630 ret = intel_set_config_save_state(dev, config);
8631 if (ret)
8632 goto out_config;
8633
8634 save_set.crtc = set->crtc;
8635 save_set.mode = &set->crtc->mode;
8636 save_set.x = set->crtc->x;
8637 save_set.y = set->crtc->y;
8638 save_set.fb = set->crtc->fb;
8639
8640 /* Compute whether we need a full modeset, only an fb base update or no
8641 * change at all. In the future we might also check whether only the
8642 * mode changed, e.g. for LVDS where we only change the panel fitter in
8643 * such cases. */
8644 intel_set_config_compute_mode_changes(set, config);
8645
9a935856 8646 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8647 if (ret)
8648 goto fail;
8649
5e2b584e 8650 if (config->mode_changed) {
c0c36b94
CW		 8651 ret = intel_set_mode(set->crtc, set->mode,
8652 set->x, set->y, set->fb);
8653 if (ret) {
8654 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8655 set->crtc->base.id, ret);
87f1faa6
DV		 8656 goto fail;
8657 }
5e2b584e 8658 } else if (config->fb_changed) {
4878cae2
VS		 8659 intel_crtc_wait_for_pending_flips(set->crtc);
8660
4f660f49 8661 ret = intel_pipe_set_base(set->crtc,
94352cf9 8662 set->x, set->y, set->fb);
50f56119
DV		 8663 }
8664
d9e55608
DV		 8665 intel_set_config_free(config);
8666
50f56119
DV		 8667 return 0;
8668
8669fail:
85f9eb71 8670 intel_set_config_restore_state(dev, config);
50f56119
DV		 8671
8672 /* Try to restore the config */
5e2b584e 8673 if (config->mode_changed &&
c0c36b94
CW		 8674 intel_set_mode(save_set.crtc, save_set.mode,
8675 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8676 DRM_ERROR("failed to restore config after modeset failure\n");
8677
d9e55608
DV		 8678out_config:
8679 intel_set_config_free(config);
50f56119
DV		 8680 return ret;
8681}
f6e5b160
CW		 8682
8683static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8684 .cursor_set = intel_crtc_cursor_set,
8685 .cursor_move = intel_crtc_cursor_move,
8686 .gamma_set = intel_crtc_gamma_set,
50f56119 8687 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8688 .destroy = intel_crtc_destroy,
8689 .page_flip = intel_crtc_page_flip,
8690};
8691
79f689aa
PZ		 8692static void intel_cpu_pll_init(struct drm_device *dev)
8693{
affa9354 8694 if (HAS_DDI(dev))
79f689aa
PZ		 8695 intel_ddi_pll_init(dev);
8696}
8697
ee7b9f93
JB		 8698static void intel_pch_pll_init(struct drm_device *dev)
8699{
8700 drm_i915_private_t *dev_priv = dev->dev_private;
8701 int i;
8702
8703 if (dev_priv->num_pch_pll == 0) {
8704 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8705 return;
8706 }
8707
8708 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8709 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8710 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8711 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8712 }
8713}
8714
b358d0a6 8715static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8716{
22fd0fab 8717 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8718 struct intel_crtc *intel_crtc;
8719 int i;
8720
8721 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8722 if (intel_crtc == NULL)
8723 return;
8724
8725 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8726
8727 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8728 for (i = 0; i < 256; i++) {
8729 intel_crtc->lut_r[i] = i;
8730 intel_crtc->lut_g[i] = i;
8731 intel_crtc->lut_b[i] = i;
8732 }
8733
80824003
JB		 8734 /* Swap pipes & planes for FBC on pre-965 */
8735 intel_crtc->pipe = pipe;
8736 intel_crtc->plane = pipe;
e2e767ab 8737 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8738 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8739 intel_crtc->plane = !pipe;
80824003
JB		 8740 }
8741
22fd0fab
JB		 8742 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8743 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8744 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8745 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8746
79e53945 8747 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8748}
8749
08d7b3d1 8750int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8751 struct drm_file *file)
08d7b3d1 8752{
08d7b3d1 8753 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8754 struct drm_mode_object *drmmode_obj;
8755 struct intel_crtc *crtc;
08d7b3d1 8756
1cff8f6b
DV		 8757 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8758 return -ENODEV;
08d7b3d1 8759
c05422d5
DV		 8760 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8761 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8762
c05422d5 8763 if (!drmmode_obj) {
08d7b3d1
CW		 8764 DRM_ERROR("no such CRTC id\n");
8765 return -EINVAL;
8766 }
8767
c05422d5
DV		 8768 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8769 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8770
c05422d5 8771 return 0;
08d7b3d1
CW		 8772}
8773
66a9278e 8774static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8775{
66a9278e
DV		 8776 struct drm_device *dev = encoder->base.dev;
8777 struct intel_encoder *source_encoder;
79e53945 8778 int index_mask = 0;
79e53945
JB		 8779 int entry = 0;
8780
66a9278e
DV		 8781 list_for_each_entry(source_encoder,
8782 &dev->mode_config.encoder_list, base.head) {
8783
8784 if (encoder == source_encoder)
79e53945 8785 index_mask |= (1 << entry);
66a9278e
DV		 8786
8787 /* Intel hw has only one MUX where enocoders could be cloned. */
8788 if (encoder->cloneable && source_encoder->cloneable)
8789 index_mask |= (1 << entry);
8790
79e53945
JB		 8791 entry++;
8792 }
4ef69c7a 8793
79e53945
JB		 8794 return index_mask;
8795}
8796
4d302442
CW		 8797static bool has_edp_a(struct drm_device *dev)
8798{
8799 struct drm_i915_private *dev_priv = dev->dev_private;
8800
8801 if (!IS_MOBILE(dev))
8802 return false;
8803
8804 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8805 return false;
8806
8807 if (IS_GEN5(dev) &&
8808 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8809 return false;
8810
8811 return true;
8812}
8813
79e53945
JB		 8814static void intel_setup_outputs(struct drm_device *dev)
8815{
725e30ad 8816 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8817 struct intel_encoder *encoder;
cb0953d7 8818 bool dpd_is_edp = false;
f3cfcba6 8819 bool has_lvds;
79e53945 8820
f3cfcba6 8821 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8822 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8823 /* disable the panel fitter on everything but LVDS */
8824 I915_WRITE(PFIT_CONTROL, 0);
8825 }
79e53945 8826
c40c0f5b 8827 if (!IS_ULT(dev))
79935fca 8828 intel_crt_init(dev);
cb0953d7 8829
affa9354 8830 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8831 int found;
8832
8833 /* Haswell uses DDI functions to detect digital outputs */
8834 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8835 /* DDI A only supports eDP */
8836 if (found)
8837 intel_ddi_init(dev, PORT_A);
8838
8839 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8840 * register */
8841 found = I915_READ(SFUSE_STRAP);
8842
8843 if (found & SFUSE_STRAP_DDIB_DETECTED)
8844 intel_ddi_init(dev, PORT_B);
8845 if (found & SFUSE_STRAP_DDIC_DETECTED)
8846 intel_ddi_init(dev, PORT_C);
8847 if (found & SFUSE_STRAP_DDID_DETECTED)
8848 intel_ddi_init(dev, PORT_D);
8849 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8850 int found;
270b3042
DV		 8851 dpd_is_edp = intel_dpd_is_edp(dev);
8852
8853 if (has_edp_a(dev))
8854 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8855
dc0fa718 8856 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 8857 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8858 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8859 if (!found)
e2debe91 8860 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 8861 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8862 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8863 }
8864
dc0fa718 8865 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 8866 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 8867
dc0fa718 8868 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 8869 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 8870
5eb08b69 8871 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8872 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8873
270b3042 8874 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8875 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 8876 } else if (IS_VALLEYVIEW(dev)) {
19c03924 8877 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 8878 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8879 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 8880
dc0fa718 8881 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 8882 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8883 PORT_B);
67cfc203
VS		 8884 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8885 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 8886 }
103a196f 8887 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8888 bool found = false;
7d57382e 8889
e2debe91 8890 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8891 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 8892 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 8893 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8894 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 8895 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 8896 }
27185ae1 8897
e7281eab 8898 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 8899 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 8900 }
13520b05
KH		 8901
8902 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8903
e2debe91 8904 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8905 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 8906 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 8907 }
27185ae1 8908
e2debe91 8909 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 8910
b01f2c3a
JB		 8911 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8912 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 8913 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 8914 }
e7281eab 8915 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 8916 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 8917 }
27185ae1 8918
b01f2c3a 8919 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 8920 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 8921 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 8922 } else if (IS_GEN2(dev))
79e53945
JB		 8923 intel_dvo_init(dev);
8924
103a196f 8925 if (SUPPORTS_TV(dev))
79e53945
JB		 8926 intel_tv_init(dev);
8927
4ef69c7a
CW		 8928 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8929 encoder->base.possible_crtcs = encoder->crtc_mask;
8930 encoder->base.possible_clones =
66a9278e 8931 intel_encoder_clones(encoder);
79e53945 8932 }
47356eb6 8933
dde86e2d 8934 intel_init_pch_refclk(dev);
270b3042
DV		 8935
8936 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8937}
8938
8939static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8940{
8941 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8942
8943 drm_framebuffer_cleanup(fb);
05394f39 8944 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8945
8946 kfree(intel_fb);
8947}
8948
8949static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8950 struct drm_file *file,
79e53945
JB		 8951 unsigned int *handle)
8952{
8953 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8954 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8955
05394f39 8956 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8957}
8958
8959static const struct drm_framebuffer_funcs intel_fb_funcs = {
8960 .destroy = intel_user_framebuffer_destroy,
8961 .create_handle = intel_user_framebuffer_create_handle,
8962};
8963
38651674
DA		 8964int intel_framebuffer_init(struct drm_device *dev,
8965 struct intel_framebuffer *intel_fb,
308e5bcb 8966 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8967 struct drm_i915_gem_object *obj)
79e53945 8968{
79e53945
JB		 8969 int ret;
8970
c16ed4be
CW		 8971 if (obj->tiling_mode == I915_TILING_Y) {
8972 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 8973 return -EINVAL;
c16ed4be 8974 }
57cd6508 8975
c16ed4be
CW		 8976 if (mode_cmd->pitches[0] & 63) {
8977 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8978 mode_cmd->pitches[0]);
57cd6508 8979 return -EINVAL;
c16ed4be 8980 }
57cd6508 8981
5d7bd705 8982 /* FIXME <= Gen4 stride limits are bit unclear */
c16ed4be
CW		 8983 if (mode_cmd->pitches[0] > 32768) {
8984 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8985 mode_cmd->pitches[0]);
5d7bd705 8986 return -EINVAL;
c16ed4be 8987 }
5d7bd705
VS		 8988
8989 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 8990 mode_cmd->pitches[0] != obj->stride) {
8991 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8992 mode_cmd->pitches[0], obj->stride);
5d7bd705 8993 return -EINVAL;
c16ed4be 8994 }
5d7bd705 8995
57779d06 8996 /* Reject formats not supported by any plane early. */
308e5bcb 8997 switch (mode_cmd->pixel_format) {
57779d06 8998 case DRM_FORMAT_C8:
04b3924d
VS		 8999 case DRM_FORMAT_RGB565:
9000 case DRM_FORMAT_XRGB8888:
9001 case DRM_FORMAT_ARGB8888:
57779d06
VS		 9002 break;
9003 case DRM_FORMAT_XRGB1555:
9004 case DRM_FORMAT_ARGB1555:
c16ed4be
CW		 9005 if (INTEL_INFO(dev)->gen > 3) {
9006 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 9007 return -EINVAL;
c16ed4be 9008 }
57779d06
VS		 9009 break;
9010 case DRM_FORMAT_XBGR8888:
9011 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 9012 case DRM_FORMAT_XRGB2101010:
9013 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 9014 case DRM_FORMAT_XBGR2101010:
9015 case DRM_FORMAT_ABGR2101010:
c16ed4be
CW		 9016 if (INTEL_INFO(dev)->gen < 4) {
9017 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 9018 return -EINVAL;
c16ed4be 9019 }
b5626747 9020 break;
04b3924d
VS		 9021 case DRM_FORMAT_YUYV:
9022 case DRM_FORMAT_UYVY:
9023 case DRM_FORMAT_YVYU:
9024 case DRM_FORMAT_VYUY:
c16ed4be
CW		 9025 if (INTEL_INFO(dev)->gen < 5) {
9026 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 9027 return -EINVAL;
c16ed4be 9028 }
57cd6508
CW		 9029 break;
9030 default:
c16ed4be 9031 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 9032 return -EINVAL;
9033 }
9034
90f9a336
VS		 9035 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9036 if (mode_cmd->offsets[0] != 0)
9037 return -EINVAL;
9038
c7d73f6a
DV		 9039 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9040 intel_fb->obj = obj;
9041
79e53945
JB		 9042 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9043 if (ret) {
9044 DRM_ERROR("framebuffer init failed %d\n", ret);
9045 return ret;
9046 }
9047
79e53945
JB		 9048 return 0;
9049}
9050
79e53945
JB		 9051static struct drm_framebuffer *
9052intel_user_framebuffer_create(struct drm_device *dev,
9053 struct drm_file *filp,
308e5bcb 9054 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 9055{
05394f39 9056 struct drm_i915_gem_object *obj;
79e53945 9057
308e5bcb
JB		 9058 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9059 mode_cmd->handles[0]));
c8725226 9060 if (&obj->base == NULL)
cce13ff7 9061 return ERR_PTR(-ENOENT);
79e53945 9062
d2dff872 9063 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 9064}
9065
79e53945 9066static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 9067 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 9068 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 9069};
9070
e70236a8
JB		 9071/* Set up chip specific display functions */
9072static void intel_init_display(struct drm_device *dev)
9073{
9074 struct drm_i915_private *dev_priv = dev->dev_private;
9075
affa9354 9076 if (HAS_DDI(dev)) {
0e8ffe1b 9077 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 9078 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 9079 dev_priv->display.crtc_enable = haswell_crtc_enable;
9080 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 9081 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 9082 dev_priv->display.update_plane = ironlake_update_plane;
9083 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 9084 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 9085 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 9086 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9087 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 9088 dev_priv->display.off = ironlake_crtc_off;
17638cd6 9089 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 9090 } else if (IS_VALLEYVIEW(dev)) {
9091 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9092 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9093 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9094 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9095 dev_priv->display.off = i9xx_crtc_off;
9096 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9097 } else {
0e8ffe1b 9098 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 9099 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 9100 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9101 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 9102 dev_priv->display.off = i9xx_crtc_off;
17638cd6 9103 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9104 }
e70236a8 9105
e70236a8 9106 /* Returns the core display clock speed */
25eb05fc
JB		 9107 if (IS_VALLEYVIEW(dev))
9108 dev_priv->display.get_display_clock_speed =
9109 valleyview_get_display_clock_speed;
9110 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 9111 dev_priv->display.get_display_clock_speed =
9112 i945_get_display_clock_speed;
9113 else if (IS_I915G(dev))
9114 dev_priv->display.get_display_clock_speed =
9115 i915_get_display_clock_speed;
f2b115e6 9116 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 9117 dev_priv->display.get_display_clock_speed =
9118 i9xx_misc_get_display_clock_speed;
9119 else if (IS_I915GM(dev))
9120 dev_priv->display.get_display_clock_speed =
9121 i915gm_get_display_clock_speed;
9122 else if (IS_I865G(dev))
9123 dev_priv->display.get_display_clock_speed =
9124 i865_get_display_clock_speed;
f0f8a9ce 9125 else if (IS_I85X(dev))
e70236a8
JB		 9126 dev_priv->display.get_display_clock_speed =
9127 i855_get_display_clock_speed;
9128 else /* 852, 830 */
9129 dev_priv->display.get_display_clock_speed =
9130 i830_get_display_clock_speed;
9131
7f8a8569 9132 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 9133 if (IS_GEN5(dev)) {
674cf967 9134 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 9135 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 9136 } else if (IS_GEN6(dev)) {
674cf967 9137 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 9138 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 9139 } else if (IS_IVYBRIDGE(dev)) {
9140 /* FIXME: detect B0+ stepping and use auto training */
9141 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 9142 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 9143 dev_priv->display.modeset_global_resources =
9144 ivb_modeset_global_resources;
c82e4d26
ED		 9145 } else if (IS_HASWELL(dev)) {
9146 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 9147 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 9148 dev_priv->display.modeset_global_resources =
9149 haswell_modeset_global_resources;
a0e63c22 9150 }
6067aaea 9151 } else if (IS_G4X(dev)) {
e0dac65e 9152 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 9153 }
8c9f3aaf
JB		 9154
9155 /* Default just returns -ENODEV to indicate unsupported */
9156 dev_priv->display.queue_flip = intel_default_queue_flip;
9157
9158 switch (INTEL_INFO(dev)->gen) {
9159 case 2:
9160 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9161 break;
9162
9163 case 3:
9164 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9165 break;
9166
9167 case 4:
9168 case 5:
9169 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9170 break;
9171
9172 case 6:
9173 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9174 break;
7c9017e5
JB		 9175 case 7:
9176 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9177 break;
8c9f3aaf 9178 }
e70236a8
JB		 9179}
9180
b690e96c
JB		 9181/*
9182 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9183 * resume, or other times. This quirk makes sure that's the case for
9184 * affected systems.
9185 */
0206e353 9186static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 9187{
9188 struct drm_i915_private *dev_priv = dev->dev_private;
9189
9190 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 9191 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 9192}
9193
435793df
KP		 9194/*
9195 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9196 */
9197static void quirk_ssc_force_disable(struct drm_device *dev)
9198{
9199 struct drm_i915_private *dev_priv = dev->dev_private;
9200 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 9201 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 9202}
9203
4dca20ef 9204/*
5a15ab5b
CE		 9205 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9206 * brightness value
4dca20ef
CE		 9207 */
9208static void quirk_invert_brightness(struct drm_device *dev)
9209{
9210 struct drm_i915_private *dev_priv = dev->dev_private;
9211 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 9212 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 9213}
9214
b690e96c
JB		 9215struct intel_quirk {
9216 int device;
9217 int subsystem_vendor;
9218 int subsystem_device;
9219 void (*hook)(struct drm_device *dev);
9220};
9221
5f85f176
EE		 9222/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9223struct intel_dmi_quirk {
9224 void (*hook)(struct drm_device *dev);
9225 const struct dmi_system_id (*dmi_id_list)[];
9226};
9227
9228static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9229{
9230 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9231 return 1;
9232}
9233
9234static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9235 {
9236 .dmi_id_list = &(const struct dmi_system_id[]) {
9237 {
9238 .callback = intel_dmi_reverse_brightness,
9239 .ident = "NCR Corporation",
9240 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9241 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9242 },
9243 },
9244 { } /* terminating entry */
9245 },
9246 .hook = quirk_invert_brightness,
9247 },
9248};
9249
c43b5634 9250static struct intel_quirk intel_quirks[] = {
b690e96c 9251 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 9252 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 9253
b690e96c
JB		 9254 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9255 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9256
b690e96c
JB		 9257 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9258 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9259
ccd0d36e 9260 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 9261 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 9262 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 9263
9264 /* Lenovo U160 cannot use SSC on LVDS */
9265 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 9266
9267 /* Sony Vaio Y cannot use SSC on LVDS */
9268 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 9269
9270 /* Acer Aspire 5734Z must invert backlight brightness */
9271 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 9272
9273 /* Acer/eMachines G725 */
9274 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 9275
9276 /* Acer/eMachines e725 */
9277 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 9278
9279 /* Acer/Packard Bell NCL20 */
9280 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 9281
9282 /* Acer Aspire 4736Z */
9283 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 9284};
9285
9286static void intel_init_quirks(struct drm_device *dev)
9287{
9288 struct pci_dev *d = dev->pdev;
9289 int i;
9290
9291 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9292 struct intel_quirk *q = &intel_quirks[i];
9293
9294 if (d->device == q->device &&
9295 (d->subsystem_vendor == q->subsystem_vendor ||
9296 q->subsystem_vendor == PCI_ANY_ID) &&
9297 (d->subsystem_device == q->subsystem_device ||
9298 q->subsystem_device == PCI_ANY_ID))
9299 q->hook(dev);
9300 }
5f85f176
EE		 9301 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9302 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9303 intel_dmi_quirks[i].hook(dev);
9304 }
b690e96c
JB		 9305}
9306
9cce37f4
JB		 9307/* Disable the VGA plane that we never use */
9308static void i915_disable_vga(struct drm_device *dev)
9309{
9310 struct drm_i915_private *dev_priv = dev->dev_private;
9311 u8 sr1;
766aa1c4 9312 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 9313
9314 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 9315 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 9316 sr1 = inb(VGA_SR_DATA);
9317 outb(sr1 | 1<<5, VGA_SR_DATA);
9318 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9319 udelay(300);
9320
9321 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9322 POSTING_READ(vga_reg);
9323}
9324
f817586c
DV		 9325void intel_modeset_init_hw(struct drm_device *dev)
9326{
fa42e23c 9327 intel_init_power_well(dev);
0232e927 9328
a8f78b58
ED		 9329 intel_prepare_ddi(dev);
9330
f817586c
DV		 9331 intel_init_clock_gating(dev);
9332
79f5b2c7 9333 mutex_lock(&dev->struct_mutex);
8090c6b9 9334 intel_enable_gt_powersave(dev);
79f5b2c7 9335 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 9336}
9337
7d708ee4
ID		 9338void intel_modeset_suspend_hw(struct drm_device *dev)
9339{
9340 intel_suspend_hw(dev);
9341}
9342
79e53945
JB		 9343void intel_modeset_init(struct drm_device *dev)
9344{
652c393a 9345 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 9346 int i, j, ret;
79e53945
JB		 9347
9348 drm_mode_config_init(dev);
9349
9350 dev->mode_config.min_width = 0;
9351 dev->mode_config.min_height = 0;
9352
019d96cb
DA		 9353 dev->mode_config.preferred_depth = 24;
9354 dev->mode_config.prefer_shadow = 1;
9355
e6ecefaa 9356 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 9357
b690e96c
JB		 9358 intel_init_quirks(dev);
9359
1fa61106
ED		 9360 intel_init_pm(dev);
9361
e3c74757
BW		 9362 if (INTEL_INFO(dev)->num_pipes == 0)
9363 return;
9364
e70236a8
JB		 9365 intel_init_display(dev);
9366
a6c45cf0
CW		 9367 if (IS_GEN2(dev)) {
9368 dev->mode_config.max_width = 2048;
9369 dev->mode_config.max_height = 2048;
9370 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9371 dev->mode_config.max_width = 4096;
9372 dev->mode_config.max_height = 4096;
79e53945 9373 } else {
a6c45cf0
CW		 9374 dev->mode_config.max_width = 8192;
9375 dev->mode_config.max_height = 8192;
79e53945 9376 }
5d4545ae 9377 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 9378
28c97730 9379 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 9380 INTEL_INFO(dev)->num_pipes,
9381 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 9382
7eb552ae 9383 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
79e53945 9384 intel_crtc_init(dev, i);
7f1f3851
JB		 9385 for (j = 0; j < dev_priv->num_plane; j++) {
9386 ret = intel_plane_init(dev, i, j);
9387 if (ret)
06da8da2
VS		 9388 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9389 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 9390 }
79e53945
JB		 9391 }
9392
79f689aa 9393 intel_cpu_pll_init(dev);
ee7b9f93
JB		 9394 intel_pch_pll_init(dev);
9395
9cce37f4
JB		 9396 /* Just disable it once at startup */
9397 i915_disable_vga(dev);
79e53945 9398 intel_setup_outputs(dev);
11be49eb
CW		 9399
9400 /* Just in case the BIOS is doing something questionable. */
9401 intel_disable_fbc(dev);
2c7111db
CW		 9402}
9403
24929352
DV		 9404static void
9405intel_connector_break_all_links(struct intel_connector *connector)
9406{
9407 connector->base.dpms = DRM_MODE_DPMS_OFF;
9408 connector->base.encoder = NULL;
9409 connector->encoder->connectors_active = false;
9410 connector->encoder->base.crtc = NULL;
9411}
9412
7fad798e
DV		 9413static void intel_enable_pipe_a(struct drm_device *dev)
9414{
9415 struct intel_connector *connector;
9416 struct drm_connector *crt = NULL;
9417 struct intel_load_detect_pipe load_detect_temp;
9418
9419 /* We can't just switch on the pipe A, we need to set things up with a
9420 * proper mode and output configuration. As a gross hack, enable pipe A
9421 * by enabling the load detect pipe once. */
9422 list_for_each_entry(connector,
9423 &dev->mode_config.connector_list,
9424 base.head) {
9425 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9426 crt = &connector->base;
9427 break;
9428 }
9429 }
9430
9431 if (!crt)
9432 return;
9433
9434 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9435 intel_release_load_detect_pipe(crt, &load_detect_temp);
9436
652c393a 9437
7fad798e
DV		 9438}
9439
fa555837
DV		 9440static bool
9441intel_check_plane_mapping(struct intel_crtc *crtc)
9442{
7eb552ae
BW		 9443 struct drm_device *dev = crtc->base.dev;
9444 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 9445 u32 reg, val;
9446
7eb552ae 9447 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 9448 return true;
9449
9450 reg = DSPCNTR(!crtc->plane);
9451 val = I915_READ(reg);
9452
9453 if ((val & DISPLAY_PLANE_ENABLE) &&
9454 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9455 return false;
9456
9457 return true;
9458}
9459
24929352
DV		 9460static void intel_sanitize_crtc(struct intel_crtc *crtc)
9461{
9462 struct drm_device *dev = crtc->base.dev;
9463 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 9464 u32 reg;
24929352 9465
24929352 9466 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 9467 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 9468 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9469
9470 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 9471 * disable the crtc (and hence change the state) if it is wrong. Note
9472 * that gen4+ has a fixed plane -> pipe mapping. */
9473 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 9474 struct intel_connector *connector;
9475 bool plane;
9476
24929352
DV		 9477 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9478 crtc->base.base.id);
9479
9480 /* Pipe has the wrong plane attached and the plane is active.
9481 * Temporarily change the plane mapping and disable everything
9482 * ... */
9483 plane = crtc->plane;
9484 crtc->plane = !plane;
9485 dev_priv->display.crtc_disable(&crtc->base);
9486 crtc->plane = plane;
9487
9488 /* ... and break all links. */
9489 list_for_each_entry(connector, &dev->mode_config.connector_list,
9490 base.head) {
9491 if (connector->encoder->base.crtc != &crtc->base)
9492 continue;
9493
9494 intel_connector_break_all_links(connector);
9495 }
9496
9497 WARN_ON(crtc->active);
9498 crtc->base.enabled = false;
9499 }
24929352 9500
7fad798e
DV		 9501 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9502 crtc->pipe == PIPE_A && !crtc->active) {
9503 /* BIOS forgot to enable pipe A, this mostly happens after
9504 * resume. Force-enable the pipe to fix this, the update_dpms
9505 * call below we restore the pipe to the right state, but leave
9506 * the required bits on. */
9507 intel_enable_pipe_a(dev);
9508 }
9509
24929352
DV		 9510 /* Adjust the state of the output pipe according to whether we
9511 * have active connectors/encoders. */
9512 intel_crtc_update_dpms(&crtc->base);
9513
9514 if (crtc->active != crtc->base.enabled) {
9515 struct intel_encoder *encoder;
9516
9517 /* This can happen either due to bugs in the get_hw_state
9518 * functions or because the pipe is force-enabled due to the
9519 * pipe A quirk. */
9520 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9521 crtc->base.base.id,
9522 crtc->base.enabled ? "enabled" : "disabled",
9523 crtc->active ? "enabled" : "disabled");
9524
9525 crtc->base.enabled = crtc->active;
9526
9527 /* Because we only establish the connector -> encoder ->
9528 * crtc links if something is active, this means the
9529 * crtc is now deactivated. Break the links. connector
9530 * -> encoder links are only establish when things are
9531 * actually up, hence no need to break them. */
9532 WARN_ON(crtc->active);
9533
9534 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9535 WARN_ON(encoder->connectors_active);
9536 encoder->base.crtc = NULL;
9537 }
9538 }
9539}
9540
9541static void intel_sanitize_encoder(struct intel_encoder *encoder)
9542{
9543 struct intel_connector *connector;
9544 struct drm_device *dev = encoder->base.dev;
9545
9546 /* We need to check both for a crtc link (meaning that the
9547 * encoder is active and trying to read from a pipe) and the
9548 * pipe itself being active. */
9549 bool has_active_crtc = encoder->base.crtc &&
9550 to_intel_crtc(encoder->base.crtc)->active;
9551
9552 if (encoder->connectors_active && !has_active_crtc) {
9553 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9554 encoder->base.base.id,
9555 drm_get_encoder_name(&encoder->base));
9556
9557 /* Connector is active, but has no active pipe. This is
9558 * fallout from our resume register restoring. Disable
9559 * the encoder manually again. */
9560 if (encoder->base.crtc) {
9561 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9562 encoder->base.base.id,
9563 drm_get_encoder_name(&encoder->base));
9564 encoder->disable(encoder);
9565 }
9566
9567 /* Inconsistent output/port/pipe state happens presumably due to
9568 * a bug in one of the get_hw_state functions. Or someplace else
9569 * in our code, like the register restore mess on resume. Clamp
9570 * things to off as a safer default. */
9571 list_for_each_entry(connector,
9572 &dev->mode_config.connector_list,
9573 base.head) {
9574 if (connector->encoder != encoder)
9575 continue;
9576
9577 intel_connector_break_all_links(connector);
9578 }
9579 }
9580 /* Enabled encoders without active connectors will be fixed in
9581 * the crtc fixup. */
9582}
9583
44cec740 9584void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9585{
9586 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9587 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9588
9589 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9590 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9591 i915_disable_vga(dev);
0fde901f
KM		 9592 }
9593}
9594
24929352
DV		 9595/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9596 * and i915 state tracking structures. */
45e2b5f6
DV		 9597void intel_modeset_setup_hw_state(struct drm_device *dev,
9598 bool force_restore)
24929352
DV		 9599{
9600 struct drm_i915_private *dev_priv = dev->dev_private;
9601 enum pipe pipe;
b5644d05 9602 struct drm_plane *plane;
24929352
DV		 9603 struct intel_crtc *crtc;
9604 struct intel_encoder *encoder;
9605 struct intel_connector *connector;
9606
0e8ffe1b
DV		 9607 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9608 base.head) {
88adfff1 9609 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 9610
0e8ffe1b
DV		 9611 crtc->active = dev_priv->display.get_pipe_config(crtc,
9612 &crtc->config);
24929352
DV		 9613
9614 crtc->base.enabled = crtc->active;
9615
9616 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9617 crtc->base.base.id,
9618 crtc->active ? "enabled" : "disabled");
9619 }
9620
affa9354 9621 if (HAS_DDI(dev))
6441ab5f
PZ		 9622 intel_ddi_setup_hw_pll_state(dev);
9623
24929352
DV		 9624 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9625 base.head) {
9626 pipe = 0;
9627
9628 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 9629 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9630 encoder->base.crtc = &crtc->base;
9631 if (encoder->get_config)
9632 encoder->get_config(encoder, &crtc->config);
24929352
DV		 9633 } else {
9634 encoder->base.crtc = NULL;
9635 }
9636
9637 encoder->connectors_active = false;
9638 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9639 encoder->base.base.id,
9640 drm_get_encoder_name(&encoder->base),
9641 encoder->base.crtc ? "enabled" : "disabled",
9642 pipe);
9643 }
9644
9645 list_for_each_entry(connector, &dev->mode_config.connector_list,
9646 base.head) {
9647 if (connector->get_hw_state(connector)) {
9648 connector->base.dpms = DRM_MODE_DPMS_ON;
9649 connector->encoder->connectors_active = true;
9650 connector->base.encoder = &connector->encoder->base;
9651 } else {
9652 connector->base.dpms = DRM_MODE_DPMS_OFF;
9653 connector->base.encoder = NULL;
9654 }
9655 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9656 connector->base.base.id,
9657 drm_get_connector_name(&connector->base),
9658 connector->base.encoder ? "enabled" : "disabled");
9659 }
9660
9661 /* HW state is read out, now we need to sanitize this mess. */
9662 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9663 base.head) {
9664 intel_sanitize_encoder(encoder);
9665 }
9666
9667 for_each_pipe(pipe) {
9668 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9669 intel_sanitize_crtc(crtc);
c0b03411 9670 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 9671 }
9a935856 9672
45e2b5f6 9673 if (force_restore) {
f30da187
DV		 9674 /*
9675 * We need to use raw interfaces for restoring state to avoid
9676 * checking (bogus) intermediate states.
9677 */
45e2b5f6 9678 for_each_pipe(pipe) {
b5644d05
JB		 9679 struct drm_crtc *crtc =
9680 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 9681
9682 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9683 crtc->fb);
45e2b5f6 9684 }
b5644d05
JB		 9685 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9686 intel_plane_restore(plane);
0fde901f
KM		 9687
9688 i915_redisable_vga(dev);
45e2b5f6
DV		 9689 } else {
9690 intel_modeset_update_staged_output_state(dev);
9691 }
8af6cf88
DV		 9692
9693 intel_modeset_check_state(dev);
2e938892
DV		 9694
9695 drm_mode_config_reset(dev);
2c7111db
CW		 9696}
9697
9698void intel_modeset_gem_init(struct drm_device *dev)
9699{
1833b134 9700 intel_modeset_init_hw(dev);
02e792fb
DV		 9701
9702 intel_setup_overlay(dev);
24929352 9703
45e2b5f6 9704 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9705}
9706
9707void intel_modeset_cleanup(struct drm_device *dev)
9708{
652c393a
JB		 9709 struct drm_i915_private *dev_priv = dev->dev_private;
9710 struct drm_crtc *crtc;
9711 struct intel_crtc *intel_crtc;
9712
fd0c0642
DV		 9713 /*
9714 * Interrupts and polling as the first thing to avoid creating havoc.
9715 * Too much stuff here (turning of rps, connectors, ...) would
9716 * experience fancy races otherwise.
9717 */
9718 drm_irq_uninstall(dev);
9719 cancel_work_sync(&dev_priv->hotplug_work);
9720 /*
9721 * Due to the hpd irq storm handling the hotplug work can re-arm the
9722 * poll handlers. Hence disable polling after hpd handling is shut down.
9723 */
f87ea761 9724 drm_kms_helper_poll_fini(dev);
fd0c0642 9725
652c393a
JB		 9726 mutex_lock(&dev->struct_mutex);
9727
723bfd70
JB		 9728 intel_unregister_dsm_handler();
9729
652c393a
JB		 9730 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9731 /* Skip inactive CRTCs */
9732 if (!crtc->fb)
9733 continue;
9734
9735 intel_crtc = to_intel_crtc(crtc);
3dec0095 9736 intel_increase_pllclock(crtc);
652c393a
JB		 9737 }
9738
973d04f9 9739 intel_disable_fbc(dev);
e70236a8 9740
8090c6b9 9741 intel_disable_gt_powersave(dev);
0cdab21f 9742
930ebb46
DV		 9743 ironlake_teardown_rc6(dev);
9744
69341a5e
KH		 9745 mutex_unlock(&dev->struct_mutex);
9746
1630fe75
CW		 9747 /* flush any delayed tasks or pending work */
9748 flush_scheduled_work();
9749
dc652f90
JN		 9750 /* destroy backlight, if any, before the connectors */
9751 intel_panel_destroy_backlight(dev);
9752
79e53945 9753 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9754
9755 intel_cleanup_overlay(dev);
79e53945
JB		 9756}
9757
f1c79df3
ZW		 9758/*
9759 * Return which encoder is currently attached for connector.
9760 */
df0e9248 9761struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9762{
df0e9248
CW		 9763 return &intel_attached_encoder(connector)->base;
9764}
f1c79df3 9765
df0e9248
CW		 9766void intel_connector_attach_encoder(struct intel_connector *connector,
9767 struct intel_encoder *encoder)
9768{
9769 connector->encoder = encoder;
9770 drm_mode_connector_attach_encoder(&connector->base,
9771 &encoder->base);
79e53945 9772}
28d52043
DA		 9773
9774/*
9775 * set vga decode state - true == enable VGA decode
9776 */
9777int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9778{
9779 struct drm_i915_private *dev_priv = dev->dev_private;
9780 u16 gmch_ctrl;
9781
9782 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9783 if (state)
9784 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9785 else
9786 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9787 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9788 return 0;
9789}
c4a1d9e4
CW		 9790
9791#ifdef CONFIG_DEBUG_FS
9792#include <linux/seq_file.h>
9793
9794struct intel_display_error_state {
ff57f1b0
PZ		 9795
9796 u32 power_well_driver;
9797
c4a1d9e4
CW		 9798 struct intel_cursor_error_state {
9799 u32 control;
9800 u32 position;
9801 u32 base;
9802 u32 size;
52331309 9803 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9804
9805 struct intel_pipe_error_state {
ff57f1b0 9806 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9807 u32 conf;
9808 u32 source;
9809
9810 u32 htotal;
9811 u32 hblank;
9812 u32 hsync;
9813 u32 vtotal;
9814 u32 vblank;
9815 u32 vsync;
52331309 9816 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9817
9818 struct intel_plane_error_state {
9819 u32 control;
9820 u32 stride;
9821 u32 size;
9822 u32 pos;
9823 u32 addr;
9824 u32 surface;
9825 u32 tile_offset;
52331309 9826 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9827};
9828
9829struct intel_display_error_state *
9830intel_display_capture_error_state(struct drm_device *dev)
9831{
0206e353 9832 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9833 struct intel_display_error_state *error;
702e7a56 9834 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9835 int i;
9836
9837 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9838 if (error == NULL)
9839 return NULL;
9840
ff57f1b0
PZ		 9841 if (HAS_POWER_WELL(dev))
9842 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
9843
52331309 9844 for_each_pipe(i) {
702e7a56 9845 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
ff57f1b0 9846 error->pipe[i].cpu_transcoder = cpu_transcoder;
702e7a56 9847
a18c4c3d
PZ		 9848 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9849 error->cursor[i].control = I915_READ(CURCNTR(i));
9850 error->cursor[i].position = I915_READ(CURPOS(i));
9851 error->cursor[i].base = I915_READ(CURBASE(i));
9852 } else {
9853 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9854 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9855 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9856 }
c4a1d9e4
CW		 9857
9858 error->plane[i].control = I915_READ(DSPCNTR(i));
9859 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 9860 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9861 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 9862 error->plane[i].pos = I915_READ(DSPPOS(i));
9863 }
ca291363
PZ		 9864 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9865 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 9866 if (INTEL_INFO(dev)->gen >= 4) {
9867 error->plane[i].surface = I915_READ(DSPSURF(i));
9868 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9869 }
9870
702e7a56 9871 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9872 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9873 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9874 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9875 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9876 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9877 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9878 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9879 }
9880
12d217c7
PZ		 9881 /* In the code above we read the registers without checking if the power
9882 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
9883 * prevent the next I915_WRITE from detecting it and printing an error
9884 * message. */
9885 if (HAS_POWER_WELL(dev))
9886 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
9887
c4a1d9e4
CW		 9888 return error;
9889}
9890
edc3d884
MK		 9891#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
9892
c4a1d9e4 9893void
edc3d884 9894intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 9895 struct drm_device *dev,
9896 struct intel_display_error_state *error)
9897{
9898 int i;
9899
edc3d884 9900 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 9901 if (HAS_POWER_WELL(dev))
edc3d884 9902 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 9903 error->power_well_driver);
52331309 9904 for_each_pipe(i) {
edc3d884
MK		 9905 err_printf(m, "Pipe [%d]:\n", i);
9906 err_printf(m, " CPU transcoder: %c\n",
ff57f1b0 9907 transcoder_name(error->pipe[i].cpu_transcoder));
edc3d884
MK		 9908 err_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9909 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
9910 err_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9911 err_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9912 err_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9913 err_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9914 err_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9915 err_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9916
9917 err_printf(m, "Plane [%d]:\n", i);
9918 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
9919 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 9920 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 9921 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
9922 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 9923 }
4b71a570 9924 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 9925 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 9926 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 9927 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
9928 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 9929 }
9930
edc3d884
MK		 9931 err_printf(m, "Cursor [%d]:\n", i);
9932 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9933 err_printf(m, " POS: %08x\n", error->cursor[i].position);
9934 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4
CW		 9935 }
9936}
9937#endif
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