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Merge tag 'drm-intel-next-2012-12-21' of git://people.freedesktop.org/~danvet/drm...
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 47
48typedef struct {
0206e353
AJ		 49 /* given values */
50 int n;
51 int m1, m2;
52 int p1, p2;
53 /* derived values */
54 int dot;
55 int vco;
56 int m;
57 int p;
79e53945
JB		 58} intel_clock_t;
59
60typedef struct {
0206e353 61 int min, max;
79e53945
JB		 62} intel_range_t;
63
64typedef struct {
0206e353
AJ		 65 int dot_limit;
66 int p2_slow, p2_fast;
79e53945
JB		 67} intel_p2_t;
68
69#define INTEL_P2_NUM 2
d4906093
ML		 70typedef struct intel_limit intel_limit_t;
71struct intel_limit {
0206e353
AJ		 72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
73 intel_p2_t p2;
74 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 75 int, int, intel_clock_t *, intel_clock_t *);
d4906093 76};
79e53945 77
2377b741
JB		 78/* FDI */
79#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
80
d2acd215
DV		 81int
82intel_pch_rawclk(struct drm_device *dev)
83{
84 struct drm_i915_private *dev_priv = dev->dev_private;
85
86 WARN_ON(!HAS_PCH_SPLIT(dev));
87
88 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
89}
90
d4906093
ML		 91static bool
92intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 93 int target, int refclk, intel_clock_t *match_clock,
94 intel_clock_t *best_clock);
d4906093
ML		 95static bool
96intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 97 int target, int refclk, intel_clock_t *match_clock,
98 intel_clock_t *best_clock);
79e53945 99
a4fc5ed6
KP		 100static bool
101intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 102 int target, int refclk, intel_clock_t *match_clock,
103 intel_clock_t *best_clock);
5eb08b69 104static bool
f2b115e6 105intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 106 int target, int refclk, intel_clock_t *match_clock,
107 intel_clock_t *best_clock);
a4fc5ed6 108
a0c4da24
JB		 109static bool
110intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
111 int target, int refclk, intel_clock_t *match_clock,
112 intel_clock_t *best_clock);
113
021357ac
CW		 114static inline u32 /* units of 100MHz */
115intel_fdi_link_freq(struct drm_device *dev)
116{
8b99e68c
CW		 117 if (IS_GEN5(dev)) {
118 struct drm_i915_private *dev_priv = dev->dev_private;
119 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
120 } else
121 return 27;
021357ac
CW		 122}
123
e4b36699 124static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 125 .dot = { .min = 25000, .max = 350000 },
126 .vco = { .min = 930000, .max = 1400000 },
127 .n = { .min = 3, .max = 16 },
128 .m = { .min = 96, .max = 140 },
129 .m1 = { .min = 18, .max = 26 },
130 .m2 = { .min = 6, .max = 16 },
131 .p = { .min = 4, .max = 128 },
132 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 133 .p2 = { .dot_limit = 165000,
134 .p2_slow = 4, .p2_fast = 2 },
d4906093 135 .find_pll = intel_find_best_PLL,
e4b36699
KP		 136};
137
138static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 139 .dot = { .min = 25000, .max = 350000 },
140 .vco = { .min = 930000, .max = 1400000 },
141 .n = { .min = 3, .max = 16 },
142 .m = { .min = 96, .max = 140 },
143 .m1 = { .min = 18, .max = 26 },
144 .m2 = { .min = 6, .max = 16 },
145 .p = { .min = 4, .max = 128 },
146 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 147 .p2 = { .dot_limit = 165000,
148 .p2_slow = 14, .p2_fast = 7 },
d4906093 149 .find_pll = intel_find_best_PLL,
e4b36699 150};
273e27ca 151
e4b36699 152static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 153 .dot = { .min = 20000, .max = 400000 },
154 .vco = { .min = 1400000, .max = 2800000 },
155 .n = { .min = 1, .max = 6 },
156 .m = { .min = 70, .max = 120 },
157 .m1 = { .min = 10, .max = 22 },
158 .m2 = { .min = 5, .max = 9 },
159 .p = { .min = 5, .max = 80 },
160 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 161 .p2 = { .dot_limit = 200000,
162 .p2_slow = 10, .p2_fast = 5 },
d4906093 163 .find_pll = intel_find_best_PLL,
e4b36699
KP		 164};
165
166static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 167 .dot = { .min = 20000, .max = 400000 },
168 .vco = { .min = 1400000, .max = 2800000 },
169 .n = { .min = 1, .max = 6 },
170 .m = { .min = 70, .max = 120 },
171 .m1 = { .min = 10, .max = 22 },
172 .m2 = { .min = 5, .max = 9 },
173 .p = { .min = 7, .max = 98 },
174 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 175 .p2 = { .dot_limit = 112000,
176 .p2_slow = 14, .p2_fast = 7 },
d4906093 177 .find_pll = intel_find_best_PLL,
e4b36699
KP		 178};
179
273e27ca 180
e4b36699 181static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 182 .dot = { .min = 25000, .max = 270000 },
183 .vco = { .min = 1750000, .max = 3500000},
184 .n = { .min = 1, .max = 4 },
185 .m = { .min = 104, .max = 138 },
186 .m1 = { .min = 17, .max = 23 },
187 .m2 = { .min = 5, .max = 11 },
188 .p = { .min = 10, .max = 30 },
189 .p1 = { .min = 1, .max = 3},
190 .p2 = { .dot_limit = 270000,
191 .p2_slow = 10,
192 .p2_fast = 10
044c7c41 193 },
d4906093 194 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 195};
196
197static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 198 .dot = { .min = 22000, .max = 400000 },
199 .vco = { .min = 1750000, .max = 3500000},
200 .n = { .min = 1, .max = 4 },
201 .m = { .min = 104, .max = 138 },
202 .m1 = { .min = 16, .max = 23 },
203 .m2 = { .min = 5, .max = 11 },
204 .p = { .min = 5, .max = 80 },
205 .p1 = { .min = 1, .max = 8},
206 .p2 = { .dot_limit = 165000,
207 .p2_slow = 10, .p2_fast = 5 },
d4906093 208 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 209};
210
211static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 212 .dot = { .min = 20000, .max = 115000 },
213 .vco = { .min = 1750000, .max = 3500000 },
214 .n = { .min = 1, .max = 3 },
215 .m = { .min = 104, .max = 138 },
216 .m1 = { .min = 17, .max = 23 },
217 .m2 = { .min = 5, .max = 11 },
218 .p = { .min = 28, .max = 112 },
219 .p1 = { .min = 2, .max = 8 },
220 .p2 = { .dot_limit = 0,
221 .p2_slow = 14, .p2_fast = 14
044c7c41 222 },
d4906093 223 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 224};
225
226static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 227 .dot = { .min = 80000, .max = 224000 },
228 .vco = { .min = 1750000, .max = 3500000 },
229 .n = { .min = 1, .max = 3 },
230 .m = { .min = 104, .max = 138 },
231 .m1 = { .min = 17, .max = 23 },
232 .m2 = { .min = 5, .max = 11 },
233 .p = { .min = 14, .max = 42 },
234 .p1 = { .min = 2, .max = 6 },
235 .p2 = { .dot_limit = 0,
236 .p2_slow = 7, .p2_fast = 7
044c7c41 237 },
d4906093 238 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 239};
240
241static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 242 .dot = { .min = 161670, .max = 227000 },
243 .vco = { .min = 1750000, .max = 3500000},
244 .n = { .min = 1, .max = 2 },
245 .m = { .min = 97, .max = 108 },
246 .m1 = { .min = 0x10, .max = 0x12 },
247 .m2 = { .min = 0x05, .max = 0x06 },
248 .p = { .min = 10, .max = 20 },
249 .p1 = { .min = 1, .max = 2},
250 .p2 = { .dot_limit = 0,
273e27ca 251 .p2_slow = 10, .p2_fast = 10 },
0206e353 252 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 253};
254
f2b115e6 255static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 256 .dot = { .min = 20000, .max = 400000},
257 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 258 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 259 .n = { .min = 3, .max = 6 },
260 .m = { .min = 2, .max = 256 },
273e27ca 261 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 262 .m1 = { .min = 0, .max = 0 },
263 .m2 = { .min = 0, .max = 254 },
264 .p = { .min = 5, .max = 80 },
265 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 266 .p2 = { .dot_limit = 200000,
267 .p2_slow = 10, .p2_fast = 5 },
6115707b 268 .find_pll = intel_find_best_PLL,
e4b36699
KP		 269};
270
f2b115e6 271static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 272 .dot = { .min = 20000, .max = 400000 },
273 .vco = { .min = 1700000, .max = 3500000 },
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 .m1 = { .min = 0, .max = 0 },
277 .m2 = { .min = 0, .max = 254 },
278 .p = { .min = 7, .max = 112 },
279 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 280 .p2 = { .dot_limit = 112000,
281 .p2_slow = 14, .p2_fast = 14 },
6115707b 282 .find_pll = intel_find_best_PLL,
e4b36699
KP		 283};
284
273e27ca
EA		 285/* Ironlake / Sandybridge
286 *
287 * We calculate clock using (register_value + 2) for N/M1/M2, so here
288 * the range value for them is (actual_value - 2).
289 */
b91ad0ec 290static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 291 .dot = { .min = 25000, .max = 350000 },
292 .vco = { .min = 1760000, .max = 3510000 },
293 .n = { .min = 1, .max = 5 },
294 .m = { .min = 79, .max = 127 },
295 .m1 = { .min = 12, .max = 22 },
296 .m2 = { .min = 5, .max = 9 },
297 .p = { .min = 5, .max = 80 },
298 .p1 = { .min = 1, .max = 8 },
299 .p2 = { .dot_limit = 225000,
300 .p2_slow = 10, .p2_fast = 5 },
4547668a 301 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 302};
303
b91ad0ec 304static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 305 .dot = { .min = 25000, .max = 350000 },
306 .vco = { .min = 1760000, .max = 3510000 },
307 .n = { .min = 1, .max = 3 },
308 .m = { .min = 79, .max = 118 },
309 .m1 = { .min = 12, .max = 22 },
310 .m2 = { .min = 5, .max = 9 },
311 .p = { .min = 28, .max = 112 },
312 .p1 = { .min = 2, .max = 8 },
313 .p2 = { .dot_limit = 225000,
314 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 315 .find_pll = intel_g4x_find_best_PLL,
316};
317
318static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 319 .dot = { .min = 25000, .max = 350000 },
320 .vco = { .min = 1760000, .max = 3510000 },
321 .n = { .min = 1, .max = 3 },
322 .m = { .min = 79, .max = 127 },
323 .m1 = { .min = 12, .max = 22 },
324 .m2 = { .min = 5, .max = 9 },
325 .p = { .min = 14, .max = 56 },
326 .p1 = { .min = 2, .max = 8 },
327 .p2 = { .dot_limit = 225000,
328 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 329 .find_pll = intel_g4x_find_best_PLL,
330};
331
273e27ca 332/* LVDS 100mhz refclk limits. */
b91ad0ec 333static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 334 .dot = { .min = 25000, .max = 350000 },
335 .vco = { .min = 1760000, .max = 3510000 },
336 .n = { .min = 1, .max = 2 },
337 .m = { .min = 79, .max = 126 },
338 .m1 = { .min = 12, .max = 22 },
339 .m2 = { .min = 5, .max = 9 },
340 .p = { .min = 28, .max = 112 },
0206e353 341 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 342 .p2 = { .dot_limit = 225000,
343 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 344 .find_pll = intel_g4x_find_best_PLL,
345};
346
347static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 348 .dot = { .min = 25000, .max = 350000 },
349 .vco = { .min = 1760000, .max = 3510000 },
350 .n = { .min = 1, .max = 3 },
351 .m = { .min = 79, .max = 126 },
352 .m1 = { .min = 12, .max = 22 },
353 .m2 = { .min = 5, .max = 9 },
354 .p = { .min = 14, .max = 42 },
0206e353 355 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 356 .p2 = { .dot_limit = 225000,
357 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 358 .find_pll = intel_g4x_find_best_PLL,
359};
360
361static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 362 .dot = { .min = 25000, .max = 350000 },
363 .vco = { .min = 1760000, .max = 3510000},
364 .n = { .min = 1, .max = 2 },
365 .m = { .min = 81, .max = 90 },
366 .m1 = { .min = 12, .max = 22 },
367 .m2 = { .min = 5, .max = 9 },
368 .p = { .min = 10, .max = 20 },
369 .p1 = { .min = 1, .max = 2},
370 .p2 = { .dot_limit = 0,
273e27ca 371 .p2_slow = 10, .p2_fast = 10 },
0206e353 372 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 373};
374
a0c4da24
JB		 375static const intel_limit_t intel_limits_vlv_dac = {
376 .dot = { .min = 25000, .max = 270000 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m = { .min = 22, .max = 450 }, /* guess */
380 .m1 = { .min = 2, .max = 3 },
381 .m2 = { .min = 11, .max = 156 },
382 .p = { .min = 10, .max = 30 },
383 .p1 = { .min = 2, .max = 3 },
384 .p2 = { .dot_limit = 270000,
385 .p2_slow = 2, .p2_fast = 20 },
386 .find_pll = intel_vlv_find_best_pll,
387};
388
389static const intel_limit_t intel_limits_vlv_hdmi = {
390 .dot = { .min = 20000, .max = 165000 },
17dc9257 391 .vco = { .min = 4000000, .max = 5994000},
a0c4da24
JB		 392 .n = { .min = 1, .max = 7 },
393 .m = { .min = 60, .max = 300 }, /* guess */
394 .m1 = { .min = 2, .max = 3 },
395 .m2 = { .min = 11, .max = 156 },
396 .p = { .min = 10, .max = 30 },
397 .p1 = { .min = 2, .max = 3 },
398 .p2 = { .dot_limit = 270000,
399 .p2_slow = 2, .p2_fast = 20 },
400 .find_pll = intel_vlv_find_best_pll,
401};
402
403static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 404 .dot = { .min = 25000, .max = 270000 },
405 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 406 .n = { .min = 1, .max = 7 },
74a4dd2e 407 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 408 .m1 = { .min = 2, .max = 3 },
409 .m2 = { .min = 11, .max = 156 },
410 .p = { .min = 10, .max = 30 },
411 .p1 = { .min = 2, .max = 3 },
412 .p2 = { .dot_limit = 270000,
413 .p2_slow = 2, .p2_fast = 20 },
414 .find_pll = intel_vlv_find_best_pll,
415};
416
57f350b6
JB		 417u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
418{
09153000 419 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
57f350b6 420
57f350b6
JB		 421 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
422 DRM_ERROR("DPIO idle wait timed out\n");
09153000 423 return 0;
57f350b6
JB		 424 }
425
426 I915_WRITE(DPIO_REG, reg);
427 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
428 DPIO_BYTE);
429 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
430 DRM_ERROR("DPIO read wait timed out\n");
09153000 431 return 0;
57f350b6 432 }
57f350b6 433
09153000 434 return I915_READ(DPIO_DATA);
57f350b6
JB		 435}
436
a0c4da24
JB		 437static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
438 u32 val)
439{
09153000 440 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a0c4da24 441
a0c4da24
JB		 442 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
443 DRM_ERROR("DPIO idle wait timed out\n");
09153000 444 return;
a0c4da24
JB		 445 }
446
447 I915_WRITE(DPIO_DATA, val);
448 I915_WRITE(DPIO_REG, reg);
449 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
450 DPIO_BYTE);
451 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
452 DRM_ERROR("DPIO write wait timed out\n");
a0c4da24
JB		 453}
454
57f350b6
JB		 455static void vlv_init_dpio(struct drm_device *dev)
456{
457 struct drm_i915_private *dev_priv = dev->dev_private;
458
459 /* Reset the DPIO config */
460 I915_WRITE(DPIO_CTL, 0);
461 POSTING_READ(DPIO_CTL);
462 I915_WRITE(DPIO_CTL, 1);
463 POSTING_READ(DPIO_CTL);
464}
465
1b894b59
CW		 466static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
467 int refclk)
2c07245f 468{
b91ad0ec 469 struct drm_device *dev = crtc->dev;
2c07245f 470 const intel_limit_t *limit;
b91ad0ec
ZW		 471
472 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 473 if (intel_is_dual_link_lvds(dev)) {
b91ad0ec 474 /* LVDS dual channel */
1b894b59 475 if (refclk == 100000)
b91ad0ec
ZW		 476 limit = &intel_limits_ironlake_dual_lvds_100m;
477 else
478 limit = &intel_limits_ironlake_dual_lvds;
479 } else {
1b894b59 480 if (refclk == 100000)
b91ad0ec
ZW		 481 limit = &intel_limits_ironlake_single_lvds_100m;
482 else
483 limit = &intel_limits_ironlake_single_lvds;
484 }
485 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
547dc041 486 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
4547668a 487 limit = &intel_limits_ironlake_display_port;
2c07245f 488 else
b91ad0ec 489 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 490
491 return limit;
492}
493
044c7c41
ML		 494static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
495{
496 struct drm_device *dev = crtc->dev;
044c7c41
ML		 497 const intel_limit_t *limit;
498
499 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 500 if (intel_is_dual_link_lvds(dev))
044c7c41 501 /* LVDS with dual channel */
e4b36699 502 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 503 else
504 /* LVDS with dual channel */
e4b36699 505 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 506 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
507 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 508 limit = &intel_limits_g4x_hdmi;
044c7c41 509 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 510 limit = &intel_limits_g4x_sdvo;
0206e353 511 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 512 limit = &intel_limits_g4x_display_port;
044c7c41 513 } else /* The option is for other outputs */
e4b36699 514 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 515
516 return limit;
517}
518
1b894b59 519static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 520{
521 struct drm_device *dev = crtc->dev;
522 const intel_limit_t *limit;
523
bad720ff 524 if (HAS_PCH_SPLIT(dev))
1b894b59 525 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 526 else if (IS_G4X(dev)) {
044c7c41 527 limit = intel_g4x_limit(crtc);
f2b115e6 528 } else if (IS_PINEVIEW(dev)) {
2177832f 529 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 530 limit = &intel_limits_pineview_lvds;
2177832f 531 else
f2b115e6 532 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 533 } else if (IS_VALLEYVIEW(dev)) {
534 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
535 limit = &intel_limits_vlv_dac;
536 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
537 limit = &intel_limits_vlv_hdmi;
538 else
539 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 540 } else if (!IS_GEN2(dev)) {
541 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
542 limit = &intel_limits_i9xx_lvds;
543 else
544 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 545 } else {
546 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 547 limit = &intel_limits_i8xx_lvds;
79e53945 548 else
e4b36699 549 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 550 }
551 return limit;
552}
553
f2b115e6
AJ		 554/* m1 is reserved as 0 in Pineview, n is a ring counter */
555static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 556{
2177832f
SL		 557 clock->m = clock->m2 + 2;
558 clock->p = clock->p1 * clock->p2;
559 clock->vco = refclk * clock->m / clock->n;
560 clock->dot = clock->vco / clock->p;
561}
562
563static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
564{
f2b115e6
AJ		 565 if (IS_PINEVIEW(dev)) {
566 pineview_clock(refclk, clock);
2177832f
SL		 567 return;
568 }
79e53945
JB		 569 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
570 clock->p = clock->p1 * clock->p2;
571 clock->vco = refclk * clock->m / (clock->n + 2);
572 clock->dot = clock->vco / clock->p;
573}
574
79e53945
JB		 575/**
576 * Returns whether any output on the specified pipe is of the specified type
577 */
4ef69c7a 578bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 579{
4ef69c7a 580 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 581 struct intel_encoder *encoder;
582
6c2b7c12
DV		 583 for_each_encoder_on_crtc(dev, crtc, encoder)
584 if (encoder->type == type)
4ef69c7a
CW		 585 return true;
586
587 return false;
79e53945
JB		 588}
589
7c04d1d9 590#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 591/**
592 * Returns whether the given set of divisors are valid for a given refclk with
593 * the given connectors.
594 */
595
1b894b59
CW		 596static bool intel_PLL_is_valid(struct drm_device *dev,
597 const intel_limit_t *limit,
598 const intel_clock_t *clock)
79e53945 599{
79e53945 600 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 601 INTELPllInvalid("p1 out of range\n");
79e53945 602 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 603 INTELPllInvalid("p out of range\n");
79e53945 604 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 605 INTELPllInvalid("m2 out of range\n");
79e53945 606 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 607 INTELPllInvalid("m1 out of range\n");
f2b115e6 608 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 609 INTELPllInvalid("m1 <= m2\n");
79e53945 610 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 611 INTELPllInvalid("m out of range\n");
79e53945 612 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 613 INTELPllInvalid("n out of range\n");
79e53945 614 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 615 INTELPllInvalid("vco out of range\n");
79e53945
JB		 616 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
617 * connector, etc., rather than just a single range.
618 */
619 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 620 INTELPllInvalid("dot out of range\n");
79e53945
JB		 621
622 return true;
623}
624
d4906093
ML		 625static bool
626intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 627 int target, int refclk, intel_clock_t *match_clock,
628 intel_clock_t *best_clock)
d4906093 629
79e53945
JB		 630{
631 struct drm_device *dev = crtc->dev;
79e53945 632 intel_clock_t clock;
79e53945
JB		 633 int err = target;
634
a210b028 635 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 636 /*
a210b028
DV		 637 * For LVDS just rely on its current settings for dual-channel.
638 * We haven't figured out how to reliably set up different
639 * single/dual channel state, if we even can.
79e53945 640 */
1974cad0 641 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 642 clock.p2 = limit->p2.p2_fast;
643 else
644 clock.p2 = limit->p2.p2_slow;
645 } else {
646 if (target < limit->p2.dot_limit)
647 clock.p2 = limit->p2.p2_slow;
648 else
649 clock.p2 = limit->p2.p2_fast;
650 }
651
0206e353 652 memset(best_clock, 0, sizeof(*best_clock));
79e53945 653
42158660
ZY		 654 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
655 clock.m1++) {
656 for (clock.m2 = limit->m2.min;
657 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 658 /* m1 is always 0 in Pineview */
659 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 660 break;
661 for (clock.n = limit->n.min;
662 clock.n <= limit->n.max; clock.n++) {
663 for (clock.p1 = limit->p1.min;
664 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 665 int this_err;
666
2177832f 667 intel_clock(dev, refclk, &clock);
1b894b59
CW		 668 if (!intel_PLL_is_valid(dev, limit,
669 &clock))
79e53945 670 continue;
cec2f356
SP		 671 if (match_clock &&
672 clock.p != match_clock->p)
673 continue;
79e53945
JB		 674
675 this_err = abs(clock.dot - target);
676 if (this_err < err) {
677 *best_clock = clock;
678 err = this_err;
679 }
680 }
681 }
682 }
683 }
684
685 return (err != target);
686}
687
d4906093
ML		 688static bool
689intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 690 int target, int refclk, intel_clock_t *match_clock,
691 intel_clock_t *best_clock)
d4906093
ML		 692{
693 struct drm_device *dev = crtc->dev;
d4906093
ML		 694 intel_clock_t clock;
695 int max_n;
696 bool found;
6ba770dc
AJ		 697 /* approximately equals target * 0.00585 */
698 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 699 found = false;
700
701 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 702 int lvds_reg;
703
c619eed4 704 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 705 lvds_reg = PCH_LVDS;
706 else
707 lvds_reg = LVDS;
1974cad0 708 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 709 clock.p2 = limit->p2.p2_fast;
710 else
711 clock.p2 = limit->p2.p2_slow;
712 } else {
713 if (target < limit->p2.dot_limit)
714 clock.p2 = limit->p2.p2_slow;
715 else
716 clock.p2 = limit->p2.p2_fast;
717 }
718
719 memset(best_clock, 0, sizeof(*best_clock));
720 max_n = limit->n.max;
f77f13e2 721 /* based on hardware requirement, prefer smaller n to precision */
d4906093 722 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 723 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 724 for (clock.m1 = limit->m1.max;
725 clock.m1 >= limit->m1.min; clock.m1--) {
726 for (clock.m2 = limit->m2.max;
727 clock.m2 >= limit->m2.min; clock.m2--) {
728 for (clock.p1 = limit->p1.max;
729 clock.p1 >= limit->p1.min; clock.p1--) {
730 int this_err;
731
2177832f 732 intel_clock(dev, refclk, &clock);
1b894b59
CW		 733 if (!intel_PLL_is_valid(dev, limit,
734 &clock))
d4906093 735 continue;
cec2f356
SP		 736 if (match_clock &&
737 clock.p != match_clock->p)
738 continue;
1b894b59
CW		 739
740 this_err = abs(clock.dot - target);
d4906093
ML		 741 if (this_err < err_most) {
742 *best_clock = clock;
743 err_most = this_err;
744 max_n = clock.n;
745 found = true;
746 }
747 }
748 }
749 }
750 }
2c07245f
ZW		 751 return found;
752}
753
5eb08b69 754static bool
f2b115e6 755intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 756 int target, int refclk, intel_clock_t *match_clock,
757 intel_clock_t *best_clock)
5eb08b69
ZW		 758{
759 struct drm_device *dev = crtc->dev;
760 intel_clock_t clock;
4547668a 761
5eb08b69
ZW		 762 if (target < 200000) {
763 clock.n = 1;
764 clock.p1 = 2;
765 clock.p2 = 10;
766 clock.m1 = 12;
767 clock.m2 = 9;
768 } else {
769 clock.n = 2;
770 clock.p1 = 1;
771 clock.p2 = 10;
772 clock.m1 = 14;
773 clock.m2 = 8;
774 }
775 intel_clock(dev, refclk, &clock);
776 memcpy(best_clock, &clock, sizeof(intel_clock_t));
777 return true;
778}
779
a4fc5ed6
KP		 780/* DisplayPort has only two frequencies, 162MHz and 270MHz */
781static bool
782intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 783 int target, int refclk, intel_clock_t *match_clock,
784 intel_clock_t *best_clock)
a4fc5ed6 785{
5eddb70b
CW		 786 intel_clock_t clock;
787 if (target < 200000) {
788 clock.p1 = 2;
789 clock.p2 = 10;
790 clock.n = 2;
791 clock.m1 = 23;
792 clock.m2 = 8;
793 } else {
794 clock.p1 = 1;
795 clock.p2 = 10;
796 clock.n = 1;
797 clock.m1 = 14;
798 clock.m2 = 2;
799 }
800 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
801 clock.p = (clock.p1 * clock.p2);
802 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
803 clock.vco = 0;
804 memcpy(best_clock, &clock, sizeof(intel_clock_t));
805 return true;
a4fc5ed6 806}
a0c4da24
JB		 807static bool
808intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
809 int target, int refclk, intel_clock_t *match_clock,
810 intel_clock_t *best_clock)
811{
812 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
813 u32 m, n, fastclk;
814 u32 updrate, minupdate, fracbits, p;
815 unsigned long bestppm, ppm, absppm;
816 int dotclk, flag;
817
af447bd3 818 flag = 0;
a0c4da24
JB		 819 dotclk = target * 1000;
820 bestppm = 1000000;
821 ppm = absppm = 0;
822 fastclk = dotclk / (2*100);
823 updrate = 0;
824 minupdate = 19200;
825 fracbits = 1;
826 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
827 bestm1 = bestm2 = bestp1 = bestp2 = 0;
828
829 /* based on hardware requirement, prefer smaller n to precision */
830 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
831 updrate = refclk / n;
832 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
833 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
834 if (p2 > 10)
835 p2 = p2 - 1;
836 p = p1 * p2;
837 /* based on hardware requirement, prefer bigger m1,m2 values */
838 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
839 m2 = (((2*(fastclk * p * n / m1 )) +
840 refclk) / (2*refclk));
841 m = m1 * m2;
842 vco = updrate * m;
843 if (vco >= limit->vco.min && vco < limit->vco.max) {
844 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
845 absppm = (ppm > 0) ? ppm : (-ppm);
846 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
847 bestppm = 0;
848 flag = 1;
849 }
850 if (absppm < bestppm - 10) {
851 bestppm = absppm;
852 flag = 1;
853 }
854 if (flag) {
855 bestn = n;
856 bestm1 = m1;
857 bestm2 = m2;
858 bestp1 = p1;
859 bestp2 = p2;
860 flag = 0;
861 }
862 }
863 }
864 }
865 }
866 }
867 best_clock->n = bestn;
868 best_clock->m1 = bestm1;
869 best_clock->m2 = bestm2;
870 best_clock->p1 = bestp1;
871 best_clock->p2 = bestp2;
872
873 return true;
874}
a4fc5ed6 875
a5c961d1
PZ		 876enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
877 enum pipe pipe)
878{
879 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
880 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
881
882 return intel_crtc->cpu_transcoder;
883}
884
a928d536
PZ		 885static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
886{
887 struct drm_i915_private *dev_priv = dev->dev_private;
888 u32 frame, frame_reg = PIPEFRAME(pipe);
889
890 frame = I915_READ(frame_reg);
891
892 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
893 DRM_DEBUG_KMS("vblank wait timed out\n");
894}
895
9d0498a2
JB		 896/**
897 * intel_wait_for_vblank - wait for vblank on a given pipe
898 * @dev: drm device
899 * @pipe: pipe to wait for
900 *
901 * Wait for vblank to occur on a given pipe. Needed for various bits of
902 * mode setting code.
903 */
904void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 905{
9d0498a2 906 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 907 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 908
a928d536
PZ		 909 if (INTEL_INFO(dev)->gen >= 5) {
910 ironlake_wait_for_vblank(dev, pipe);
911 return;
912 }
913
300387c0
CW		 914 /* Clear existing vblank status. Note this will clear any other
915 * sticky status fields as well.
916 *
917 * This races with i915_driver_irq_handler() with the result
918 * that either function could miss a vblank event. Here it is not
919 * fatal, as we will either wait upon the next vblank interrupt or
920 * timeout. Generally speaking intel_wait_for_vblank() is only
921 * called during modeset at which time the GPU should be idle and
922 * should *not* be performing page flips and thus not waiting on
923 * vblanks...
924 * Currently, the result of us stealing a vblank from the irq
925 * handler is that a single frame will be skipped during swapbuffers.
926 */
927 I915_WRITE(pipestat_reg,
928 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
929
9d0498a2 930 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 931 if (wait_for(I915_READ(pipestat_reg) &
932 PIPE_VBLANK_INTERRUPT_STATUS,
933 50))
9d0498a2
JB		 934 DRM_DEBUG_KMS("vblank wait timed out\n");
935}
936
ab7ad7f6
KP		 937/*
938 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 939 * @dev: drm device
940 * @pipe: pipe to wait for
941 *
942 * After disabling a pipe, we can't wait for vblank in the usual way,
943 * spinning on the vblank interrupt status bit, since we won't actually
944 * see an interrupt when the pipe is disabled.
945 *
ab7ad7f6
KP		 946 * On Gen4 and above:
947 * wait for the pipe register state bit to turn off
948 *
949 * Otherwise:
950 * wait for the display line value to settle (it usually
951 * ends up stopping at the start of the next frame).
58e10eb9 952 *
9d0498a2 953 */
58e10eb9 954void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 955{
956 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 957 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
958 pipe);
ab7ad7f6
KP		 959
960 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 961 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 962
963 /* Wait for the Pipe State to go off */
58e10eb9
CW		 964 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
965 100))
284637d9 966 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 967 } else {
837ba00f 968 u32 last_line, line_mask;
58e10eb9 969 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 970 unsigned long timeout = jiffies + msecs_to_jiffies(100);
971
837ba00f
PZ		 972 if (IS_GEN2(dev))
973 line_mask = DSL_LINEMASK_GEN2;
974 else
975 line_mask = DSL_LINEMASK_GEN3;
976
ab7ad7f6
KP		 977 /* Wait for the display line to settle */
978 do {
837ba00f 979 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 980 mdelay(5);
837ba00f 981 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 982 time_after(timeout, jiffies));
983 if (time_after(jiffies, timeout))
284637d9 984 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 985 }
79e53945
JB		 986}
987
b0ea7d37
DL		 988/*
989 * ibx_digital_port_connected - is the specified port connected?
990 * @dev_priv: i915 private structure
991 * @port: the port to test
992 *
993 * Returns true if @port is connected, false otherwise.
994 */
995bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
996 struct intel_digital_port *port)
997{
998 u32 bit;
999
c36346e3
DL		 1000 if (HAS_PCH_IBX(dev_priv->dev)) {
1001 switch(port->port) {
1002 case PORT_B:
1003 bit = SDE_PORTB_HOTPLUG;
1004 break;
1005 case PORT_C:
1006 bit = SDE_PORTC_HOTPLUG;
1007 break;
1008 case PORT_D:
1009 bit = SDE_PORTD_HOTPLUG;
1010 break;
1011 default:
1012 return true;
1013 }
1014 } else {
1015 switch(port->port) {
1016 case PORT_B:
1017 bit = SDE_PORTB_HOTPLUG_CPT;
1018 break;
1019 case PORT_C:
1020 bit = SDE_PORTC_HOTPLUG_CPT;
1021 break;
1022 case PORT_D:
1023 bit = SDE_PORTD_HOTPLUG_CPT;
1024 break;
1025 default:
1026 return true;
1027 }
b0ea7d37
DL		 1028 }
1029
1030 return I915_READ(SDEISR) & bit;
1031}
1032
b24e7179
JB		 1033static const char *state_string(bool enabled)
1034{
1035 return enabled ? "on" : "off";
1036}
1037
1038/* Only for pre-ILK configs */
1039static void assert_pll(struct drm_i915_private *dev_priv,
1040 enum pipe pipe, bool state)
1041{
1042 int reg;
1043 u32 val;
1044 bool cur_state;
1045
1046 reg = DPLL(pipe);
1047 val = I915_READ(reg);
1048 cur_state = !!(val & DPLL_VCO_ENABLE);
1049 WARN(cur_state != state,
1050 "PLL state assertion failure (expected %s, current %s)\n",
1051 state_string(state), state_string(cur_state));
1052}
1053#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1054#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1055
040484af
JB		 1056/* For ILK+ */
1057static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1058 struct intel_pch_pll *pll,
1059 struct intel_crtc *crtc,
1060 bool state)
040484af 1061{
040484af
JB		 1062 u32 val;
1063 bool cur_state;
1064
9d82aa17
ED		 1065 if (HAS_PCH_LPT(dev_priv->dev)) {
1066 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1067 return;
1068 }
1069
92b27b08
CW		 1070 if (WARN (!pll,
1071 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1072 return;
ee7b9f93 1073
92b27b08
CW		 1074 val = I915_READ(pll->pll_reg);
1075 cur_state = !!(val & DPLL_VCO_ENABLE);
1076 WARN(cur_state != state,
1077 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1078 pll->pll_reg, state_string(state), state_string(cur_state), val);
1079
1080 /* Make sure the selected PLL is correctly attached to the transcoder */
1081 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1082 u32 pch_dpll;
1083
1084 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1085 cur_state = pll->pll_reg == _PCH_DPLL_B;
1086 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1087 "PLL[%d] not attached to this transcoder %d: %08x\n",
1088 cur_state, crtc->pipe, pch_dpll)) {
1089 cur_state = !!(val >> (4*crtc->pipe + 3));
1090 WARN(cur_state != state,
1091 "PLL[%d] not %s on this transcoder %d: %08x\n",
1092 pll->pll_reg == _PCH_DPLL_B,
1093 state_string(state),
1094 crtc->pipe,
1095 val);
1096 }
d3ccbe86 1097 }
040484af 1098}
92b27b08
CW		 1099#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1100#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1101
1102static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1103 enum pipe pipe, bool state)
1104{
1105 int reg;
1106 u32 val;
1107 bool cur_state;
ad80a810
PZ		 1108 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1109 pipe);
040484af 1110
affa9354
PZ		 1111 if (HAS_DDI(dev_priv->dev)) {
1112 /* DDI does not have a specific FDI_TX register */
ad80a810 1113 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1114 val = I915_READ(reg);
ad80a810 1115 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1116 } else {
1117 reg = FDI_TX_CTL(pipe);
1118 val = I915_READ(reg);
1119 cur_state = !!(val & FDI_TX_ENABLE);
1120 }
040484af
JB		 1121 WARN(cur_state != state,
1122 "FDI TX state assertion failure (expected %s, current %s)\n",
1123 state_string(state), state_string(cur_state));
1124}
1125#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1126#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1127
1128static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1129 enum pipe pipe, bool state)
1130{
1131 int reg;
1132 u32 val;
1133 bool cur_state;
1134
d63fa0dc
PZ		 1135 reg = FDI_RX_CTL(pipe);
1136 val = I915_READ(reg);
1137 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1138 WARN(cur_state != state,
1139 "FDI RX state assertion failure (expected %s, current %s)\n",
1140 state_string(state), state_string(cur_state));
1141}
1142#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1143#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1144
1145static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1146 enum pipe pipe)
1147{
1148 int reg;
1149 u32 val;
1150
1151 /* ILK FDI PLL is always enabled */
1152 if (dev_priv->info->gen == 5)
1153 return;
1154
bf507ef7 1155 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1156 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1157 return;
1158
040484af
JB		 1159 reg = FDI_TX_CTL(pipe);
1160 val = I915_READ(reg);
1161 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1162}
1163
1164static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1165 enum pipe pipe)
1166{
1167 int reg;
1168 u32 val;
1169
1170 reg = FDI_RX_CTL(pipe);
1171 val = I915_READ(reg);
1172 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1173}
1174
ea0760cf
JB		 1175static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1176 enum pipe pipe)
1177{
1178 int pp_reg, lvds_reg;
1179 u32 val;
1180 enum pipe panel_pipe = PIPE_A;
0de3b485 1181 bool locked = true;
ea0760cf
JB		 1182
1183 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1184 pp_reg = PCH_PP_CONTROL;
1185 lvds_reg = PCH_LVDS;
1186 } else {
1187 pp_reg = PP_CONTROL;
1188 lvds_reg = LVDS;
1189 }
1190
1191 val = I915_READ(pp_reg);
1192 if (!(val & PANEL_POWER_ON) ||
1193 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1194 locked = false;
1195
1196 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1197 panel_pipe = PIPE_B;
1198
1199 WARN(panel_pipe == pipe && locked,
1200 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1201 pipe_name(pipe));
ea0760cf
JB		 1202}
1203
b840d907
JB		 1204void assert_pipe(struct drm_i915_private *dev_priv,
1205 enum pipe pipe, bool state)
b24e7179
JB		 1206{
1207 int reg;
1208 u32 val;
63d7bbe9 1209 bool cur_state;
702e7a56
PZ		 1210 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1211 pipe);
b24e7179 1212
8e636784
DV		 1213 /* if we need the pipe A quirk it must be always on */
1214 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1215 state = true;
1216
702e7a56 1217 reg = PIPECONF(cpu_transcoder);
b24e7179 1218 val = I915_READ(reg);
63d7bbe9
JB		 1219 cur_state = !!(val & PIPECONF_ENABLE);
1220 WARN(cur_state != state,
1221 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1222 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1223}
1224
931872fc
CW		 1225static void assert_plane(struct drm_i915_private *dev_priv,
1226 enum plane plane, bool state)
b24e7179
JB		 1227{
1228 int reg;
1229 u32 val;
931872fc 1230 bool cur_state;
b24e7179
JB		 1231
1232 reg = DSPCNTR(plane);
1233 val = I915_READ(reg);
931872fc
CW		 1234 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1235 WARN(cur_state != state,
1236 "plane %c assertion failure (expected %s, current %s)\n",
1237 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1238}
1239
931872fc
CW		 1240#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1241#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1242
b24e7179
JB		 1243static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1244 enum pipe pipe)
1245{
1246 int reg, i;
1247 u32 val;
1248 int cur_pipe;
1249
19ec1358 1250 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 1251 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1252 reg = DSPCNTR(pipe);
1253 val = I915_READ(reg);
1254 WARN((val & DISPLAY_PLANE_ENABLE),
1255 "plane %c assertion failure, should be disabled but not\n",
1256 plane_name(pipe));
19ec1358 1257 return;
28c05794 1258 }
19ec1358 1259
b24e7179
JB		 1260 /* Need to check both planes against the pipe */
1261 for (i = 0; i < 2; i++) {
1262 reg = DSPCNTR(i);
1263 val = I915_READ(reg);
1264 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1265 DISPPLANE_SEL_PIPE_SHIFT;
1266 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1267 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1268 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1269 }
1270}
1271
92f2584a
JB		 1272static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1273{
1274 u32 val;
1275 bool enabled;
1276
9d82aa17
ED		 1277 if (HAS_PCH_LPT(dev_priv->dev)) {
1278 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1279 return;
1280 }
1281
92f2584a
JB		 1282 val = I915_READ(PCH_DREF_CONTROL);
1283 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1284 DREF_SUPERSPREAD_SOURCE_MASK));
1285 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1286}
1287
1288static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1289 enum pipe pipe)
1290{
1291 int reg;
1292 u32 val;
1293 bool enabled;
1294
1295 reg = TRANSCONF(pipe);
1296 val = I915_READ(reg);
1297 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1298 WARN(enabled,
1299 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1300 pipe_name(pipe));
92f2584a
JB		 1301}
1302
4e634389
KP		 1303static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1304 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1305{
1306 if ((val & DP_PORT_EN) == 0)
1307 return false;
1308
1309 if (HAS_PCH_CPT(dev_priv->dev)) {
1310 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1311 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1312 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1313 return false;
1314 } else {
1315 if ((val & DP_PIPE_MASK) != (pipe << 30))
1316 return false;
1317 }
1318 return true;
1319}
1320
1519b995
KP		 1321static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1322 enum pipe pipe, u32 val)
1323{
1324 if ((val & PORT_ENABLE) == 0)
1325 return false;
1326
1327 if (HAS_PCH_CPT(dev_priv->dev)) {
1328 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1329 return false;
1330 } else {
1331 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1332 return false;
1333 }
1334 return true;
1335}
1336
1337static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1338 enum pipe pipe, u32 val)
1339{
1340 if ((val & LVDS_PORT_EN) == 0)
1341 return false;
1342
1343 if (HAS_PCH_CPT(dev_priv->dev)) {
1344 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1345 return false;
1346 } else {
1347 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1348 return false;
1349 }
1350 return true;
1351}
1352
1353static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1354 enum pipe pipe, u32 val)
1355{
1356 if ((val & ADPA_DAC_ENABLE) == 0)
1357 return false;
1358 if (HAS_PCH_CPT(dev_priv->dev)) {
1359 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1360 return false;
1361 } else {
1362 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1363 return false;
1364 }
1365 return true;
1366}
1367
291906f1 1368static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1369 enum pipe pipe, int reg, u32 port_sel)
291906f1 1370{
47a05eca 1371 u32 val = I915_READ(reg);
4e634389 1372 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1373 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1374 reg, pipe_name(pipe));
de9a35ab 1375
75c5da27
DV		 1376 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1377 && (val & DP_PIPEB_SELECT),
de9a35ab 1378 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1379}
1380
1381static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1382 enum pipe pipe, int reg)
1383{
47a05eca 1384 u32 val = I915_READ(reg);
b70ad586 1385 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1386 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1387 reg, pipe_name(pipe));
de9a35ab 1388
75c5da27
DV		 1389 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1390 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1391 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1392}
1393
1394static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1395 enum pipe pipe)
1396{
1397 int reg;
1398 u32 val;
291906f1 1399
f0575e92
KP		 1400 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1401 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1402 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1403
1404 reg = PCH_ADPA;
1405 val = I915_READ(reg);
b70ad586 1406 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1407 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1408 pipe_name(pipe));
291906f1
JB		 1409
1410 reg = PCH_LVDS;
1411 val = I915_READ(reg);
b70ad586 1412 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1413 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1414 pipe_name(pipe));
291906f1
JB		 1415
1416 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1417 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1418 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1419}
1420
63d7bbe9
JB		 1421/**
1422 * intel_enable_pll - enable a PLL
1423 * @dev_priv: i915 private structure
1424 * @pipe: pipe PLL to enable
1425 *
1426 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1427 * make sure the PLL reg is writable first though, since the panel write
1428 * protect mechanism may be enabled.
1429 *
1430 * Note! This is for pre-ILK only.
7434a255
TR		 1431 *
1432 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1433 */
1434static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1435{
1436 int reg;
1437 u32 val;
1438
1439 /* No really, not for ILK+ */
a0c4da24 1440 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1441
1442 /* PLL is protected by panel, make sure we can write it */
1443 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1444 assert_panel_unlocked(dev_priv, pipe);
1445
1446 reg = DPLL(pipe);
1447 val = I915_READ(reg);
1448 val |= DPLL_VCO_ENABLE;
1449
1450 /* We do this three times for luck */
1451 I915_WRITE(reg, val);
1452 POSTING_READ(reg);
1453 udelay(150); /* wait for warmup */
1454 I915_WRITE(reg, val);
1455 POSTING_READ(reg);
1456 udelay(150); /* wait for warmup */
1457 I915_WRITE(reg, val);
1458 POSTING_READ(reg);
1459 udelay(150); /* wait for warmup */
1460}
1461
1462/**
1463 * intel_disable_pll - disable a PLL
1464 * @dev_priv: i915 private structure
1465 * @pipe: pipe PLL to disable
1466 *
1467 * Disable the PLL for @pipe, making sure the pipe is off first.
1468 *
1469 * Note! This is for pre-ILK only.
1470 */
1471static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1472{
1473 int reg;
1474 u32 val;
1475
1476 /* Don't disable pipe A or pipe A PLLs if needed */
1477 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1478 return;
1479
1480 /* Make sure the pipe isn't still relying on us */
1481 assert_pipe_disabled(dev_priv, pipe);
1482
1483 reg = DPLL(pipe);
1484 val = I915_READ(reg);
1485 val &= ~DPLL_VCO_ENABLE;
1486 I915_WRITE(reg, val);
1487 POSTING_READ(reg);
1488}
1489
a416edef
ED		 1490/* SBI access */
1491static void
988d6ee8
PZ		 1492intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1493 enum intel_sbi_destination destination)
a416edef 1494{
988d6ee8 1495 u32 tmp;
a416edef 1496
09153000 1497 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1498
39fb50f6 1499 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1500 100)) {
1501 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1502 return;
a416edef
ED		 1503 }
1504
988d6ee8
PZ		 1505 I915_WRITE(SBI_ADDR, (reg << 16));
1506 I915_WRITE(SBI_DATA, value);
1507
1508 if (destination == SBI_ICLK)
1509 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1510 else
1511 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1512 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
a416edef 1513
39fb50f6 1514 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1515 100)) {
1516 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
09153000 1517 return;
a416edef 1518 }
a416edef
ED		 1519}
1520
1521static u32
988d6ee8
PZ		 1522intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1523 enum intel_sbi_destination destination)
a416edef 1524{
39fb50f6 1525 u32 value = 0;
09153000 1526 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1527
39fb50f6 1528 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1529 100)) {
1530 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1531 return 0;
a416edef
ED		 1532 }
1533
988d6ee8
PZ		 1534 I915_WRITE(SBI_ADDR, (reg << 16));
1535
1536 if (destination == SBI_ICLK)
1537 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1538 else
1539 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1540 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
a416edef 1541
39fb50f6 1542 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1543 100)) {
1544 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
09153000 1545 return 0;
a416edef
ED		 1546 }
1547
09153000 1548 return I915_READ(SBI_DATA);
a416edef
ED		 1549}
1550
92f2584a 1551/**
b6b4e185 1552 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1553 * @dev_priv: i915 private structure
1554 * @pipe: pipe PLL to enable
1555 *
1556 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1557 * drives the transcoder clock.
1558 */
b6b4e185 1559static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1560{
ee7b9f93 1561 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1562 struct intel_pch_pll *pll;
92f2584a
JB		 1563 int reg;
1564 u32 val;
1565
48da64a8 1566 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1567 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1568 pll = intel_crtc->pch_pll;
1569 if (pll == NULL)
1570 return;
1571
1572 if (WARN_ON(pll->refcount == 0))
1573 return;
ee7b9f93
JB		 1574
1575 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1576 pll->pll_reg, pll->active, pll->on,
1577 intel_crtc->base.base.id);
92f2584a
JB		 1578
1579 /* PCH refclock must be enabled first */
1580 assert_pch_refclk_enabled(dev_priv);
1581
ee7b9f93 1582 if (pll->active++ && pll->on) {
92b27b08 1583 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1584 return;
1585 }
1586
1587 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1588
1589 reg = pll->pll_reg;
92f2584a
JB		 1590 val = I915_READ(reg);
1591 val |= DPLL_VCO_ENABLE;
1592 I915_WRITE(reg, val);
1593 POSTING_READ(reg);
1594 udelay(200);
ee7b9f93
JB		 1595
1596 pll->on = true;
92f2584a
JB		 1597}
1598
ee7b9f93 1599static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1600{
ee7b9f93
JB		 1601 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1602 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1603 int reg;
ee7b9f93 1604 u32 val;
4c609cb8 1605
92f2584a
JB		 1606 /* PCH only available on ILK+ */
1607 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1608 if (pll == NULL)
1609 return;
92f2584a 1610
48da64a8
CW		 1611 if (WARN_ON(pll->refcount == 0))
1612 return;
7a419866 1613
ee7b9f93
JB		 1614 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1615 pll->pll_reg, pll->active, pll->on,
1616 intel_crtc->base.base.id);
7a419866 1617
48da64a8 1618 if (WARN_ON(pll->active == 0)) {
92b27b08 1619 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1620 return;
1621 }
1622
ee7b9f93 1623 if (--pll->active) {
92b27b08 1624 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1625 return;
ee7b9f93
JB		 1626 }
1627
1628 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1629
1630 /* Make sure transcoder isn't still depending on us */
1631 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1632
ee7b9f93 1633 reg = pll->pll_reg;
92f2584a
JB		 1634 val = I915_READ(reg);
1635 val &= ~DPLL_VCO_ENABLE;
1636 I915_WRITE(reg, val);
1637 POSTING_READ(reg);
1638 udelay(200);
ee7b9f93
JB		 1639
1640 pll->on = false;
92f2584a
JB		 1641}
1642
b8a4f404
PZ		 1643static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1644 enum pipe pipe)
040484af 1645{
23670b32 1646 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1647 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1648 uint32_t reg, val, pipeconf_val;
040484af
JB		 1649
1650 /* PCH only available on ILK+ */
1651 BUG_ON(dev_priv->info->gen < 5);
1652
1653 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1654 assert_pch_pll_enabled(dev_priv,
1655 to_intel_crtc(crtc)->pch_pll,
1656 to_intel_crtc(crtc));
040484af
JB		 1657
1658 /* FDI must be feeding us bits for PCH ports */
1659 assert_fdi_tx_enabled(dev_priv, pipe);
1660 assert_fdi_rx_enabled(dev_priv, pipe);
1661
23670b32
DV		 1662 if (HAS_PCH_CPT(dev)) {
1663 /* Workaround: Set the timing override bit before enabling the
1664 * pch transcoder. */
1665 reg = TRANS_CHICKEN2(pipe);
1666 val = I915_READ(reg);
1667 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1668 I915_WRITE(reg, val);
59c859d6 1669 }
23670b32 1670
040484af
JB		 1671 reg = TRANSCONF(pipe);
1672 val = I915_READ(reg);
5f7f726d 1673 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1674
1675 if (HAS_PCH_IBX(dev_priv->dev)) {
1676 /*
1677 * make the BPC in transcoder be consistent with
1678 * that in pipeconf reg.
1679 */
dfd07d72
DV		 1680 val &= ~PIPECONF_BPC_MASK;
1681 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1682 }
5f7f726d
PZ		 1683
1684 val &= ~TRANS_INTERLACE_MASK;
1685 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1686 if (HAS_PCH_IBX(dev_priv->dev) &&
1687 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1688 val |= TRANS_LEGACY_INTERLACED_ILK;
1689 else
1690 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1691 else
1692 val |= TRANS_PROGRESSIVE;
1693
040484af
JB		 1694 I915_WRITE(reg, val | TRANS_ENABLE);
1695 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1696 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1697}
1698
8fb033d7 1699static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1700 enum transcoder cpu_transcoder)
040484af 1701{
8fb033d7 1702 u32 val, pipeconf_val;
8fb033d7
PZ		 1703
1704 /* PCH only available on ILK+ */
1705 BUG_ON(dev_priv->info->gen < 5);
1706
8fb033d7 1707 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1708 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1709 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1710
223a6fdf
PZ		 1711 /* Workaround: set timing override bit. */
1712 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1713 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1714 I915_WRITE(_TRANSA_CHICKEN2, val);
1715
25f3ef11 1716 val = TRANS_ENABLE;
937bb610 1717 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1718
9a76b1c6
PZ		 1719 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1720 PIPECONF_INTERLACED_ILK)
a35f2679 1721 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1722 else
1723 val |= TRANS_PROGRESSIVE;
1724
25f3ef11 1725 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
937bb610
PZ		 1726 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1727 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1728}
1729
b8a4f404
PZ		 1730static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1731 enum pipe pipe)
040484af 1732{
23670b32
DV		 1733 struct drm_device *dev = dev_priv->dev;
1734 uint32_t reg, val;
040484af
JB		 1735
1736 /* FDI relies on the transcoder */
1737 assert_fdi_tx_disabled(dev_priv, pipe);
1738 assert_fdi_rx_disabled(dev_priv, pipe);
1739
291906f1
JB		 1740 /* Ports must be off as well */
1741 assert_pch_ports_disabled(dev_priv, pipe);
1742
040484af
JB		 1743 reg = TRANSCONF(pipe);
1744 val = I915_READ(reg);
1745 val &= ~TRANS_ENABLE;
1746 I915_WRITE(reg, val);
1747 /* wait for PCH transcoder off, transcoder state */
1748 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1749 DRM_ERROR("failed to disable transcoder %d\n", pipe);
23670b32
DV		 1750
1751 if (!HAS_PCH_IBX(dev)) {
1752 /* Workaround: Clear the timing override chicken bit again. */
1753 reg = TRANS_CHICKEN2(pipe);
1754 val = I915_READ(reg);
1755 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1756 I915_WRITE(reg, val);
1757 }
040484af
JB		 1758}
1759
ab4d966c 1760static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1761{
8fb033d7
PZ		 1762 u32 val;
1763
8a52fd9f 1764 val = I915_READ(_TRANSACONF);
8fb033d7 1765 val &= ~TRANS_ENABLE;
8a52fd9f 1766 I915_WRITE(_TRANSACONF, val);
8fb033d7 1767 /* wait for PCH transcoder off, transcoder state */
8a52fd9f
PZ		 1768 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1769 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1770
1771 /* Workaround: clear timing override bit. */
1772 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1773 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1774 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1775}
1776
b24e7179 1777/**
309cfea8 1778 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1779 * @dev_priv: i915 private structure
1780 * @pipe: pipe to enable
040484af 1781 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1782 *
1783 * Enable @pipe, making sure that various hardware specific requirements
1784 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1785 *
1786 * @pipe should be %PIPE_A or %PIPE_B.
1787 *
1788 * Will wait until the pipe is actually running (i.e. first vblank) before
1789 * returning.
1790 */
040484af
JB		 1791static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1792 bool pch_port)
b24e7179 1793{
702e7a56
PZ		 1794 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1795 pipe);
1a240d4d 1796 enum pipe pch_transcoder;
b24e7179
JB		 1797 int reg;
1798 u32 val;
1799
681e5811 1800 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1801 pch_transcoder = TRANSCODER_A;
1802 else
1803 pch_transcoder = pipe;
1804
b24e7179
JB		 1805 /*
1806 * A pipe without a PLL won't actually be able to drive bits from
1807 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1808 * need the check.
1809 */
1810 if (!HAS_PCH_SPLIT(dev_priv->dev))
1811 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1812 else {
1813 if (pch_port) {
1814 /* if driving the PCH, we need FDI enabled */
cc391bbb 1815 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1816 assert_fdi_tx_pll_enabled(dev_priv,
1817 (enum pipe) cpu_transcoder);
040484af
JB		 1818 }
1819 /* FIXME: assert CPU port conditions for SNB+ */
1820 }
b24e7179 1821
702e7a56 1822 reg = PIPECONF(cpu_transcoder);
b24e7179 1823 val = I915_READ(reg);
00d70b15
CW		 1824 if (val & PIPECONF_ENABLE)
1825 return;
1826
1827 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1828 intel_wait_for_vblank(dev_priv->dev, pipe);
1829}
1830
1831/**
309cfea8 1832 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1833 * @dev_priv: i915 private structure
1834 * @pipe: pipe to disable
1835 *
1836 * Disable @pipe, making sure that various hardware specific requirements
1837 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1838 *
1839 * @pipe should be %PIPE_A or %PIPE_B.
1840 *
1841 * Will wait until the pipe has shut down before returning.
1842 */
1843static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1844 enum pipe pipe)
1845{
702e7a56
PZ		 1846 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1847 pipe);
b24e7179
JB		 1848 int reg;
1849 u32 val;
1850
1851 /*
1852 * Make sure planes won't keep trying to pump pixels to us,
1853 * or we might hang the display.
1854 */
1855 assert_planes_disabled(dev_priv, pipe);
1856
1857 /* Don't disable pipe A or pipe A PLLs if needed */
1858 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1859 return;
1860
702e7a56 1861 reg = PIPECONF(cpu_transcoder);
b24e7179 1862 val = I915_READ(reg);
00d70b15
CW		 1863 if ((val & PIPECONF_ENABLE) == 0)
1864 return;
1865
1866 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1867 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1868}
1869
d74362c9
KP		 1870/*
1871 * Plane regs are double buffered, going from enabled->disabled needs a
1872 * trigger in order to latch. The display address reg provides this.
1873 */
6f1d69b0 1874void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1875 enum plane plane)
1876{
14f86147
DL		 1877 if (dev_priv->info->gen >= 4)
1878 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1879 else
1880 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1881}
1882
b24e7179
JB		 1883/**
1884 * intel_enable_plane - enable a display plane on a given pipe
1885 * @dev_priv: i915 private structure
1886 * @plane: plane to enable
1887 * @pipe: pipe being fed
1888 *
1889 * Enable @plane on @pipe, making sure that @pipe is running first.
1890 */
1891static void intel_enable_plane(struct drm_i915_private *dev_priv,
1892 enum plane plane, enum pipe pipe)
1893{
1894 int reg;
1895 u32 val;
1896
1897 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1898 assert_pipe_enabled(dev_priv, pipe);
1899
1900 reg = DSPCNTR(plane);
1901 val = I915_READ(reg);
00d70b15
CW		 1902 if (val & DISPLAY_PLANE_ENABLE)
1903 return;
1904
1905 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1906 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1907 intel_wait_for_vblank(dev_priv->dev, pipe);
1908}
1909
b24e7179
JB		 1910/**
1911 * intel_disable_plane - disable a display plane
1912 * @dev_priv: i915 private structure
1913 * @plane: plane to disable
1914 * @pipe: pipe consuming the data
1915 *
1916 * Disable @plane; should be an independent operation.
1917 */
1918static void intel_disable_plane(struct drm_i915_private *dev_priv,
1919 enum plane plane, enum pipe pipe)
1920{
1921 int reg;
1922 u32 val;
1923
1924 reg = DSPCNTR(plane);
1925 val = I915_READ(reg);
00d70b15
CW		 1926 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1927 return;
1928
1929 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1930 intel_flush_display_plane(dev_priv, plane);
1931 intel_wait_for_vblank(dev_priv->dev, pipe);
1932}
1933
127bd2ac 1934int
48b956c5 1935intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1936 struct drm_i915_gem_object *obj,
919926ae 1937 struct intel_ring_buffer *pipelined)
6b95a207 1938{
ce453d81 1939 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1940 u32 alignment;
1941 int ret;
1942
05394f39 1943 switch (obj->tiling_mode) {
6b95a207 1944 case I915_TILING_NONE:
534843da
CW		 1945 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1946 alignment = 128 * 1024;
a6c45cf0 1947 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1948 alignment = 4 * 1024;
1949 else
1950 alignment = 64 * 1024;
6b95a207
KH		 1951 break;
1952 case I915_TILING_X:
1953 /* pin() will align the object as required by fence */
1954 alignment = 0;
1955 break;
1956 case I915_TILING_Y:
1957 /* FIXME: Is this true? */
1958 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1959 return -EINVAL;
1960 default:
1961 BUG();
1962 }
1963
ce453d81 1964 dev_priv->mm.interruptible = false;
2da3b9b9 1965 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1966 if (ret)
ce453d81 1967 goto err_interruptible;
6b95a207
KH		 1968
1969 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1970 * fence, whereas 965+ only requires a fence if using
1971 * framebuffer compression. For simplicity, we always install
1972 * a fence as the cost is not that onerous.
1973 */
06d98131 1974 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1975 if (ret)
1976 goto err_unpin;
1690e1eb 1977
9a5a53b3 1978 i915_gem_object_pin_fence(obj);
6b95a207 1979
ce453d81 1980 dev_priv->mm.interruptible = true;
6b95a207 1981 return 0;
48b956c5
CW		 1982
1983err_unpin:
1984 i915_gem_object_unpin(obj);
ce453d81
CW		 1985err_interruptible:
1986 dev_priv->mm.interruptible = true;
48b956c5 1987 return ret;
6b95a207
KH		 1988}
1989
1690e1eb
CW		 1990void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1991{
1992 i915_gem_object_unpin_fence(obj);
1993 i915_gem_object_unpin(obj);
1994}
1995
c2c75131
DV		 1996/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1997 * is assumed to be a power-of-two. */
5a35e99e
DL		 1998unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
1999 unsigned int bpp,
2000 unsigned int pitch)
c2c75131
DV		 2001{
2002 int tile_rows, tiles;
2003
2004 tile_rows = *y / 8;
2005 *y %= 8;
2006 tiles = *x / (512/bpp);
2007 *x %= 512/bpp;
2008
2009 return tile_rows * pitch * 8 + tiles * 4096;
2010}
2011
17638cd6
JB		 2012static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2013 int x, int y)
81255565
JB		 2014{
2015 struct drm_device *dev = crtc->dev;
2016 struct drm_i915_private *dev_priv = dev->dev_private;
2017 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2018 struct intel_framebuffer *intel_fb;
05394f39 2019 struct drm_i915_gem_object *obj;
81255565 2020 int plane = intel_crtc->plane;
e506a0c6 2021 unsigned long linear_offset;
81255565 2022 u32 dspcntr;
5eddb70b 2023 u32 reg;
81255565
JB		 2024
2025 switch (plane) {
2026 case 0:
2027 case 1:
2028 break;
2029 default:
2030 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2031 return -EINVAL;
2032 }
2033
2034 intel_fb = to_intel_framebuffer(fb);
2035 obj = intel_fb->obj;
81255565 2036
5eddb70b
CW		 2037 reg = DSPCNTR(plane);
2038 dspcntr = I915_READ(reg);
81255565
JB		 2039 /* Mask out pixel format bits in case we change it */
2040 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2041 switch (fb->pixel_format) {
2042 case DRM_FORMAT_C8:
81255565
JB		 2043 dspcntr |= DISPPLANE_8BPP;
2044 break;
57779d06
VS		 2045 case DRM_FORMAT_XRGB1555:
2046 case DRM_FORMAT_ARGB1555:
2047 dspcntr |= DISPPLANE_BGRX555;
81255565 2048 break;
57779d06
VS		 2049 case DRM_FORMAT_RGB565:
2050 dspcntr |= DISPPLANE_BGRX565;
2051 break;
2052 case DRM_FORMAT_XRGB8888:
2053 case DRM_FORMAT_ARGB8888:
2054 dspcntr |= DISPPLANE_BGRX888;
2055 break;
2056 case DRM_FORMAT_XBGR8888:
2057 case DRM_FORMAT_ABGR8888:
2058 dspcntr |= DISPPLANE_RGBX888;
2059 break;
2060 case DRM_FORMAT_XRGB2101010:
2061 case DRM_FORMAT_ARGB2101010:
2062 dspcntr |= DISPPLANE_BGRX101010;
2063 break;
2064 case DRM_FORMAT_XBGR2101010:
2065 case DRM_FORMAT_ABGR2101010:
2066 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2067 break;
2068 default:
57779d06 2069 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
81255565
JB		 2070 return -EINVAL;
2071 }
57779d06 2072
a6c45cf0 2073 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2074 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2075 dspcntr |= DISPPLANE_TILED;
2076 else
2077 dspcntr &= ~DISPPLANE_TILED;
2078 }
2079
5eddb70b 2080 I915_WRITE(reg, dspcntr);
81255565 2081
e506a0c6 2082 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2083
c2c75131
DV		 2084 if (INTEL_INFO(dev)->gen >= 4) {
2085 intel_crtc->dspaddr_offset =
5a35e99e
DL		 2086 intel_gen4_compute_offset_xtiled(&x, &y,
2087 fb->bits_per_pixel / 8,
2088 fb->pitches[0]);
c2c75131
DV		 2089 linear_offset -= intel_crtc->dspaddr_offset;
2090 } else {
e506a0c6 2091 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2092 }
e506a0c6
DV		 2093
2094 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2095 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2096 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2097 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2098 I915_MODIFY_DISPBASE(DSPSURF(plane),
2099 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2100 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2101 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2102 } else
e506a0c6 2103 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2104 POSTING_READ(reg);
81255565 2105
17638cd6
JB		 2106 return 0;
2107}
2108
2109static int ironlake_update_plane(struct drm_crtc *crtc,
2110 struct drm_framebuffer *fb, int x, int y)
2111{
2112 struct drm_device *dev = crtc->dev;
2113 struct drm_i915_private *dev_priv = dev->dev_private;
2114 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2115 struct intel_framebuffer *intel_fb;
2116 struct drm_i915_gem_object *obj;
2117 int plane = intel_crtc->plane;
e506a0c6 2118 unsigned long linear_offset;
17638cd6
JB		 2119 u32 dspcntr;
2120 u32 reg;
2121
2122 switch (plane) {
2123 case 0:
2124 case 1:
27f8227b 2125 case 2:
17638cd6
JB		 2126 break;
2127 default:
2128 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2129 return -EINVAL;
2130 }
2131
2132 intel_fb = to_intel_framebuffer(fb);
2133 obj = intel_fb->obj;
2134
2135 reg = DSPCNTR(plane);
2136 dspcntr = I915_READ(reg);
2137 /* Mask out pixel format bits in case we change it */
2138 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2139 switch (fb->pixel_format) {
2140 case DRM_FORMAT_C8:
17638cd6
JB		 2141 dspcntr |= DISPPLANE_8BPP;
2142 break;
57779d06
VS		 2143 case DRM_FORMAT_RGB565:
2144 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2145 break;
57779d06
VS		 2146 case DRM_FORMAT_XRGB8888:
2147 case DRM_FORMAT_ARGB8888:
2148 dspcntr |= DISPPLANE_BGRX888;
2149 break;
2150 case DRM_FORMAT_XBGR8888:
2151 case DRM_FORMAT_ABGR8888:
2152 dspcntr |= DISPPLANE_RGBX888;
2153 break;
2154 case DRM_FORMAT_XRGB2101010:
2155 case DRM_FORMAT_ARGB2101010:
2156 dspcntr |= DISPPLANE_BGRX101010;
2157 break;
2158 case DRM_FORMAT_XBGR2101010:
2159 case DRM_FORMAT_ABGR2101010:
2160 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2161 break;
2162 default:
57779d06 2163 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
17638cd6
JB		 2164 return -EINVAL;
2165 }
2166
2167 if (obj->tiling_mode != I915_TILING_NONE)
2168 dspcntr |= DISPPLANE_TILED;
2169 else
2170 dspcntr &= ~DISPPLANE_TILED;
2171
2172 /* must disable */
2173 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2174
2175 I915_WRITE(reg, dspcntr);
2176
e506a0c6 2177 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2178 intel_crtc->dspaddr_offset =
5a35e99e
DL		 2179 intel_gen4_compute_offset_xtiled(&x, &y,
2180 fb->bits_per_pixel / 8,
2181 fb->pitches[0]);
c2c75131 2182 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2183
e506a0c6
DV		 2184 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2185 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2186 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2187 I915_MODIFY_DISPBASE(DSPSURF(plane),
2188 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2189 if (IS_HASWELL(dev)) {
2190 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2191 } else {
2192 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2193 I915_WRITE(DSPLINOFF(plane), linear_offset);
2194 }
17638cd6
JB		 2195 POSTING_READ(reg);
2196
2197 return 0;
2198}
2199
2200/* Assume fb object is pinned & idle & fenced and just update base pointers */
2201static int
2202intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2203 int x, int y, enum mode_set_atomic state)
2204{
2205 struct drm_device *dev = crtc->dev;
2206 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2207
6b8e6ed0
CW		 2208 if (dev_priv->display.disable_fbc)
2209 dev_priv->display.disable_fbc(dev);
3dec0095 2210 intel_increase_pllclock(crtc);
81255565 2211
6b8e6ed0 2212 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2213}
2214
14667a4b
CW		 2215static int
2216intel_finish_fb(struct drm_framebuffer *old_fb)
2217{
2218 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2219 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2220 bool was_interruptible = dev_priv->mm.interruptible;
2221 int ret;
2222
2223 wait_event(dev_priv->pending_flip_queue,
2224 atomic_read(&dev_priv->mm.wedged) ||
2225 atomic_read(&obj->pending_flip) == 0);
2226
2227 /* Big Hammer, we also need to ensure that any pending
2228 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2229 * current scanout is retired before unpinning the old
2230 * framebuffer.
2231 *
2232 * This should only fail upon a hung GPU, in which case we
2233 * can safely continue.
2234 */
2235 dev_priv->mm.interruptible = false;
2236 ret = i915_gem_object_finish_gpu(obj);
2237 dev_priv->mm.interruptible = was_interruptible;
2238
2239 return ret;
2240}
2241
198598d0
VS		 2242static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2243{
2244 struct drm_device *dev = crtc->dev;
2245 struct drm_i915_master_private *master_priv;
2246 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2247
2248 if (!dev->primary->master)
2249 return;
2250
2251 master_priv = dev->primary->master->driver_priv;
2252 if (!master_priv->sarea_priv)
2253 return;
2254
2255 switch (intel_crtc->pipe) {
2256 case 0:
2257 master_priv->sarea_priv->pipeA_x = x;
2258 master_priv->sarea_priv->pipeA_y = y;
2259 break;
2260 case 1:
2261 master_priv->sarea_priv->pipeB_x = x;
2262 master_priv->sarea_priv->pipeB_y = y;
2263 break;
2264 default:
2265 break;
2266 }
2267}
2268
5c3b82e2 2269static int
3c4fdcfb 2270intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2271 struct drm_framebuffer *fb)
79e53945
JB		 2272{
2273 struct drm_device *dev = crtc->dev;
6b8e6ed0 2274 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2275 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2276 struct drm_framebuffer *old_fb;
5c3b82e2 2277 int ret;
79e53945
JB		 2278
2279 /* no fb bound */
94352cf9 2280 if (!fb) {
a5071c2f 2281 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2282 return 0;
2283 }
2284
5826eca5
ED		 2285 if(intel_crtc->plane > dev_priv->num_pipe) {
2286 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2287 intel_crtc->plane,
2288 dev_priv->num_pipe);
5c3b82e2 2289 return -EINVAL;
79e53945
JB		 2290 }
2291
5c3b82e2 2292 mutex_lock(&dev->struct_mutex);
265db958 2293 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2294 to_intel_framebuffer(fb)->obj,
919926ae 2295 NULL);
5c3b82e2
CW		 2296 if (ret != 0) {
2297 mutex_unlock(&dev->struct_mutex);
a5071c2f 2298 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2299 return ret;
2300 }
79e53945 2301
94352cf9
DV		 2302 if (crtc->fb)
2303 intel_finish_fb(crtc->fb);
265db958 2304
94352cf9 2305 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2306 if (ret) {
94352cf9 2307 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2308 mutex_unlock(&dev->struct_mutex);
a5071c2f 2309 DRM_ERROR("failed to update base address\n");
4e6cfefc 2310 return ret;
79e53945 2311 }
3c4fdcfb 2312
94352cf9
DV		 2313 old_fb = crtc->fb;
2314 crtc->fb = fb;
6c4c86f5
DV		 2315 crtc->x = x;
2316 crtc->y = y;
94352cf9 2317
b7f1de28
CW		 2318 if (old_fb) {
2319 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2320 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2321 }
652c393a 2322
6b8e6ed0 2323 intel_update_fbc(dev);
5c3b82e2 2324 mutex_unlock(&dev->struct_mutex);
79e53945 2325
198598d0 2326 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2327
2328 return 0;
79e53945
JB		 2329}
2330
5e84e1a4
ZW		 2331static void intel_fdi_normal_train(struct drm_crtc *crtc)
2332{
2333 struct drm_device *dev = crtc->dev;
2334 struct drm_i915_private *dev_priv = dev->dev_private;
2335 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2336 int pipe = intel_crtc->pipe;
2337 u32 reg, temp;
2338
2339 /* enable normal train */
2340 reg = FDI_TX_CTL(pipe);
2341 temp = I915_READ(reg);
61e499bf 2342 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2343 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2344 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2345 } else {
2346 temp &= ~FDI_LINK_TRAIN_NONE;
2347 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2348 }
5e84e1a4
ZW		 2349 I915_WRITE(reg, temp);
2350
2351 reg = FDI_RX_CTL(pipe);
2352 temp = I915_READ(reg);
2353 if (HAS_PCH_CPT(dev)) {
2354 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2355 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2356 } else {
2357 temp &= ~FDI_LINK_TRAIN_NONE;
2358 temp |= FDI_LINK_TRAIN_NONE;
2359 }
2360 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2361
2362 /* wait one idle pattern time */
2363 POSTING_READ(reg);
2364 udelay(1000);
357555c0
JB		 2365
2366 /* IVB wants error correction enabled */
2367 if (IS_IVYBRIDGE(dev))
2368 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2369 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2370}
2371
01a415fd
DV		 2372static void ivb_modeset_global_resources(struct drm_device *dev)
2373{
2374 struct drm_i915_private *dev_priv = dev->dev_private;
2375 struct intel_crtc *pipe_B_crtc =
2376 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2377 struct intel_crtc *pipe_C_crtc =
2378 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2379 uint32_t temp;
2380
2381 /* When everything is off disable fdi C so that we could enable fdi B
2382 * with all lanes. XXX: This misses the case where a pipe is not using
2383 * any pch resources and so doesn't need any fdi lanes. */
2384 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2385 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2386 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2387
2388 temp = I915_READ(SOUTH_CHICKEN1);
2389 temp &= ~FDI_BC_BIFURCATION_SELECT;
2390 DRM_DEBUG_KMS("disabling fdi C rx\n");
2391 I915_WRITE(SOUTH_CHICKEN1, temp);
2392 }
2393}
2394
8db9d77b
ZW		 2395/* The FDI link training functions for ILK/Ibexpeak. */
2396static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2397{
2398 struct drm_device *dev = crtc->dev;
2399 struct drm_i915_private *dev_priv = dev->dev_private;
2400 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2401 int pipe = intel_crtc->pipe;
0fc932b8 2402 int plane = intel_crtc->plane;
5eddb70b 2403 u32 reg, temp, tries;
8db9d77b 2404
0fc932b8
JB		 2405 /* FDI needs bits from pipe & plane first */
2406 assert_pipe_enabled(dev_priv, pipe);
2407 assert_plane_enabled(dev_priv, plane);
2408
e1a44743
AJ		 2409 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2410 for train result */
5eddb70b
CW		 2411 reg = FDI_RX_IMR(pipe);
2412 temp = I915_READ(reg);
e1a44743
AJ		 2413 temp &= ~FDI_RX_SYMBOL_LOCK;
2414 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2415 I915_WRITE(reg, temp);
2416 I915_READ(reg);
e1a44743
AJ		 2417 udelay(150);
2418
8db9d77b 2419 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2420 reg = FDI_TX_CTL(pipe);
2421 temp = I915_READ(reg);
77ffb597
AJ		 2422 temp &= ~(7 << 19);
2423 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2424 temp &= ~FDI_LINK_TRAIN_NONE;
2425 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2426 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2427
5eddb70b
CW		 2428 reg = FDI_RX_CTL(pipe);
2429 temp = I915_READ(reg);
8db9d77b
ZW		 2430 temp &= ~FDI_LINK_TRAIN_NONE;
2431 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2432 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2433
2434 POSTING_READ(reg);
8db9d77b
ZW		 2435 udelay(150);
2436
5b2adf89 2437 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2438 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2439 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2440 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2441
5eddb70b 2442 reg = FDI_RX_IIR(pipe);
e1a44743 2443 for (tries = 0; tries < 5; tries++) {
5eddb70b 2444 temp = I915_READ(reg);
8db9d77b
ZW		 2445 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2446
2447 if ((temp & FDI_RX_BIT_LOCK)) {
2448 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2449 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2450 break;
2451 }
8db9d77b 2452 }
e1a44743 2453 if (tries == 5)
5eddb70b 2454 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2455
2456 /* Train 2 */
5eddb70b
CW		 2457 reg = FDI_TX_CTL(pipe);
2458 temp = I915_READ(reg);
8db9d77b
ZW		 2459 temp &= ~FDI_LINK_TRAIN_NONE;
2460 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2461 I915_WRITE(reg, temp);
8db9d77b 2462
5eddb70b
CW		 2463 reg = FDI_RX_CTL(pipe);
2464 temp = I915_READ(reg);
8db9d77b
ZW		 2465 temp &= ~FDI_LINK_TRAIN_NONE;
2466 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2467 I915_WRITE(reg, temp);
8db9d77b 2468
5eddb70b
CW		 2469 POSTING_READ(reg);
2470 udelay(150);
8db9d77b 2471
5eddb70b 2472 reg = FDI_RX_IIR(pipe);
e1a44743 2473 for (tries = 0; tries < 5; tries++) {
5eddb70b 2474 temp = I915_READ(reg);
8db9d77b
ZW		 2475 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2476
2477 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2478 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2479 DRM_DEBUG_KMS("FDI train 2 done.\n");
2480 break;
2481 }
8db9d77b 2482 }
e1a44743 2483 if (tries == 5)
5eddb70b 2484 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2485
2486 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2487
8db9d77b
ZW		 2488}
2489
0206e353 2490static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2491 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2492 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2493 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2494 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2495};
2496
2497/* The FDI link training functions for SNB/Cougarpoint. */
2498static void gen6_fdi_link_train(struct drm_crtc *crtc)
2499{
2500 struct drm_device *dev = crtc->dev;
2501 struct drm_i915_private *dev_priv = dev->dev_private;
2502 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2503 int pipe = intel_crtc->pipe;
fa37d39e 2504 u32 reg, temp, i, retry;
8db9d77b 2505
e1a44743
AJ		 2506 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2507 for train result */
5eddb70b
CW		 2508 reg = FDI_RX_IMR(pipe);
2509 temp = I915_READ(reg);
e1a44743
AJ		 2510 temp &= ~FDI_RX_SYMBOL_LOCK;
2511 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2512 I915_WRITE(reg, temp);
2513
2514 POSTING_READ(reg);
e1a44743
AJ		 2515 udelay(150);
2516
8db9d77b 2517 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2518 reg = FDI_TX_CTL(pipe);
2519 temp = I915_READ(reg);
77ffb597
AJ		 2520 temp &= ~(7 << 19);
2521 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2522 temp &= ~FDI_LINK_TRAIN_NONE;
2523 temp |= FDI_LINK_TRAIN_PATTERN_1;
2524 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2525 /* SNB-B */
2526 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2527 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2528
d74cf324
DV		 2529 I915_WRITE(FDI_RX_MISC(pipe),
2530 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2531
5eddb70b
CW		 2532 reg = FDI_RX_CTL(pipe);
2533 temp = I915_READ(reg);
8db9d77b
ZW		 2534 if (HAS_PCH_CPT(dev)) {
2535 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2536 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2537 } else {
2538 temp &= ~FDI_LINK_TRAIN_NONE;
2539 temp |= FDI_LINK_TRAIN_PATTERN_1;
2540 }
5eddb70b
CW		 2541 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2542
2543 POSTING_READ(reg);
8db9d77b
ZW		 2544 udelay(150);
2545
0206e353 2546 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2547 reg = FDI_TX_CTL(pipe);
2548 temp = I915_READ(reg);
8db9d77b
ZW		 2549 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2550 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2551 I915_WRITE(reg, temp);
2552
2553 POSTING_READ(reg);
8db9d77b
ZW		 2554 udelay(500);
2555
fa37d39e
SP		 2556 for (retry = 0; retry < 5; retry++) {
2557 reg = FDI_RX_IIR(pipe);
2558 temp = I915_READ(reg);
2559 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2560 if (temp & FDI_RX_BIT_LOCK) {
2561 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2562 DRM_DEBUG_KMS("FDI train 1 done.\n");
2563 break;
2564 }
2565 udelay(50);
8db9d77b 2566 }
fa37d39e
SP		 2567 if (retry < 5)
2568 break;
8db9d77b
ZW		 2569 }
2570 if (i == 4)
5eddb70b 2571 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2572
2573 /* Train 2 */
5eddb70b
CW		 2574 reg = FDI_TX_CTL(pipe);
2575 temp = I915_READ(reg);
8db9d77b
ZW		 2576 temp &= ~FDI_LINK_TRAIN_NONE;
2577 temp |= FDI_LINK_TRAIN_PATTERN_2;
2578 if (IS_GEN6(dev)) {
2579 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2580 /* SNB-B */
2581 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2582 }
5eddb70b 2583 I915_WRITE(reg, temp);
8db9d77b 2584
5eddb70b
CW		 2585 reg = FDI_RX_CTL(pipe);
2586 temp = I915_READ(reg);
8db9d77b
ZW		 2587 if (HAS_PCH_CPT(dev)) {
2588 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2589 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2590 } else {
2591 temp &= ~FDI_LINK_TRAIN_NONE;
2592 temp |= FDI_LINK_TRAIN_PATTERN_2;
2593 }
5eddb70b
CW		 2594 I915_WRITE(reg, temp);
2595
2596 POSTING_READ(reg);
8db9d77b
ZW		 2597 udelay(150);
2598
0206e353 2599 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2600 reg = FDI_TX_CTL(pipe);
2601 temp = I915_READ(reg);
8db9d77b
ZW		 2602 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2603 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2604 I915_WRITE(reg, temp);
2605
2606 POSTING_READ(reg);
8db9d77b
ZW		 2607 udelay(500);
2608
fa37d39e
SP		 2609 for (retry = 0; retry < 5; retry++) {
2610 reg = FDI_RX_IIR(pipe);
2611 temp = I915_READ(reg);
2612 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2613 if (temp & FDI_RX_SYMBOL_LOCK) {
2614 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2615 DRM_DEBUG_KMS("FDI train 2 done.\n");
2616 break;
2617 }
2618 udelay(50);
8db9d77b 2619 }
fa37d39e
SP		 2620 if (retry < 5)
2621 break;
8db9d77b
ZW		 2622 }
2623 if (i == 4)
5eddb70b 2624 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2625
2626 DRM_DEBUG_KMS("FDI train done.\n");
2627}
2628
357555c0
JB		 2629/* Manual link training for Ivy Bridge A0 parts */
2630static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2631{
2632 struct drm_device *dev = crtc->dev;
2633 struct drm_i915_private *dev_priv = dev->dev_private;
2634 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2635 int pipe = intel_crtc->pipe;
2636 u32 reg, temp, i;
2637
2638 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2639 for train result */
2640 reg = FDI_RX_IMR(pipe);
2641 temp = I915_READ(reg);
2642 temp &= ~FDI_RX_SYMBOL_LOCK;
2643 temp &= ~FDI_RX_BIT_LOCK;
2644 I915_WRITE(reg, temp);
2645
2646 POSTING_READ(reg);
2647 udelay(150);
2648
01a415fd
DV		 2649 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2650 I915_READ(FDI_RX_IIR(pipe)));
2651
357555c0
JB		 2652 /* enable CPU FDI TX and PCH FDI RX */
2653 reg = FDI_TX_CTL(pipe);
2654 temp = I915_READ(reg);
2655 temp &= ~(7 << 19);
2656 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2657 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2658 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2659 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2660 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2661 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2662 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2663
d74cf324
DV		 2664 I915_WRITE(FDI_RX_MISC(pipe),
2665 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2666
357555c0
JB		 2667 reg = FDI_RX_CTL(pipe);
2668 temp = I915_READ(reg);
2669 temp &= ~FDI_LINK_TRAIN_AUTO;
2670 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2671 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2672 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2673 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2674
2675 POSTING_READ(reg);
2676 udelay(150);
2677
0206e353 2678 for (i = 0; i < 4; i++) {
357555c0
JB		 2679 reg = FDI_TX_CTL(pipe);
2680 temp = I915_READ(reg);
2681 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2682 temp |= snb_b_fdi_train_param[i];
2683 I915_WRITE(reg, temp);
2684
2685 POSTING_READ(reg);
2686 udelay(500);
2687
2688 reg = FDI_RX_IIR(pipe);
2689 temp = I915_READ(reg);
2690 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2691
2692 if (temp & FDI_RX_BIT_LOCK ||
2693 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2694 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2695 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2696 break;
2697 }
2698 }
2699 if (i == 4)
2700 DRM_ERROR("FDI train 1 fail!\n");
2701
2702 /* Train 2 */
2703 reg = FDI_TX_CTL(pipe);
2704 temp = I915_READ(reg);
2705 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2706 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2707 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2708 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2709 I915_WRITE(reg, temp);
2710
2711 reg = FDI_RX_CTL(pipe);
2712 temp = I915_READ(reg);
2713 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2714 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2715 I915_WRITE(reg, temp);
2716
2717 POSTING_READ(reg);
2718 udelay(150);
2719
0206e353 2720 for (i = 0; i < 4; i++) {
357555c0
JB		 2721 reg = FDI_TX_CTL(pipe);
2722 temp = I915_READ(reg);
2723 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2724 temp |= snb_b_fdi_train_param[i];
2725 I915_WRITE(reg, temp);
2726
2727 POSTING_READ(reg);
2728 udelay(500);
2729
2730 reg = FDI_RX_IIR(pipe);
2731 temp = I915_READ(reg);
2732 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2733
2734 if (temp & FDI_RX_SYMBOL_LOCK) {
2735 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2736 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2737 break;
2738 }
2739 }
2740 if (i == 4)
2741 DRM_ERROR("FDI train 2 fail!\n");
2742
2743 DRM_DEBUG_KMS("FDI train done.\n");
2744}
2745
88cefb6c 2746static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2747{
88cefb6c 2748 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2749 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2750 int pipe = intel_crtc->pipe;
5eddb70b 2751 u32 reg, temp;
79e53945 2752
c64e311e 2753
c98e9dcf 2754 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2755 reg = FDI_RX_CTL(pipe);
2756 temp = I915_READ(reg);
2757 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2758 temp |= (intel_crtc->fdi_lanes - 1) << 19;
dfd07d72 2759 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2760 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2761
2762 POSTING_READ(reg);
c98e9dcf
JB		 2763 udelay(200);
2764
2765 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2766 temp = I915_READ(reg);
2767 I915_WRITE(reg, temp | FDI_PCDCLK);
2768
2769 POSTING_READ(reg);
c98e9dcf
JB		 2770 udelay(200);
2771
20749730
PZ		 2772 /* Enable CPU FDI TX PLL, always on for Ironlake */
2773 reg = FDI_TX_CTL(pipe);
2774 temp = I915_READ(reg);
2775 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2776 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2777
20749730
PZ		 2778 POSTING_READ(reg);
2779 udelay(100);
6be4a607 2780 }
0e23b99d
JB		 2781}
2782
88cefb6c
DV		 2783static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2784{
2785 struct drm_device *dev = intel_crtc->base.dev;
2786 struct drm_i915_private *dev_priv = dev->dev_private;
2787 int pipe = intel_crtc->pipe;
2788 u32 reg, temp;
2789
2790 /* Switch from PCDclk to Rawclk */
2791 reg = FDI_RX_CTL(pipe);
2792 temp = I915_READ(reg);
2793 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2794
2795 /* Disable CPU FDI TX PLL */
2796 reg = FDI_TX_CTL(pipe);
2797 temp = I915_READ(reg);
2798 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2799
2800 POSTING_READ(reg);
2801 udelay(100);
2802
2803 reg = FDI_RX_CTL(pipe);
2804 temp = I915_READ(reg);
2805 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2806
2807 /* Wait for the clocks to turn off. */
2808 POSTING_READ(reg);
2809 udelay(100);
2810}
2811
0fc932b8
JB		 2812static void ironlake_fdi_disable(struct drm_crtc *crtc)
2813{
2814 struct drm_device *dev = crtc->dev;
2815 struct drm_i915_private *dev_priv = dev->dev_private;
2816 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2817 int pipe = intel_crtc->pipe;
2818 u32 reg, temp;
2819
2820 /* disable CPU FDI tx and PCH FDI rx */
2821 reg = FDI_TX_CTL(pipe);
2822 temp = I915_READ(reg);
2823 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2824 POSTING_READ(reg);
2825
2826 reg = FDI_RX_CTL(pipe);
2827 temp = I915_READ(reg);
2828 temp &= ~(0x7 << 16);
dfd07d72 2829 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2830 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2831
2832 POSTING_READ(reg);
2833 udelay(100);
2834
2835 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2836 if (HAS_PCH_IBX(dev)) {
2837 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2838 }
0fc932b8
JB		 2839
2840 /* still set train pattern 1 */
2841 reg = FDI_TX_CTL(pipe);
2842 temp = I915_READ(reg);
2843 temp &= ~FDI_LINK_TRAIN_NONE;
2844 temp |= FDI_LINK_TRAIN_PATTERN_1;
2845 I915_WRITE(reg, temp);
2846
2847 reg = FDI_RX_CTL(pipe);
2848 temp = I915_READ(reg);
2849 if (HAS_PCH_CPT(dev)) {
2850 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2851 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2852 } else {
2853 temp &= ~FDI_LINK_TRAIN_NONE;
2854 temp |= FDI_LINK_TRAIN_PATTERN_1;
2855 }
2856 /* BPC in FDI rx is consistent with that in PIPECONF */
2857 temp &= ~(0x07 << 16);
dfd07d72 2858 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2859 I915_WRITE(reg, temp);
2860
2861 POSTING_READ(reg);
2862 udelay(100);
2863}
2864
5bb61643
CW		 2865static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2866{
2867 struct drm_device *dev = crtc->dev;
2868 struct drm_i915_private *dev_priv = dev->dev_private;
2869 unsigned long flags;
2870 bool pending;
2871
2872 if (atomic_read(&dev_priv->mm.wedged))
2873 return false;
2874
2875 spin_lock_irqsave(&dev->event_lock, flags);
2876 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2877 spin_unlock_irqrestore(&dev->event_lock, flags);
2878
2879 return pending;
2880}
2881
e6c3a2a6
CW		 2882static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2883{
0f91128d 2884 struct drm_device *dev = crtc->dev;
5bb61643 2885 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2886
2887 if (crtc->fb == NULL)
2888 return;
2889
5bb61643
CW		 2890 wait_event(dev_priv->pending_flip_queue,
2891 !intel_crtc_has_pending_flip(crtc));
2892
0f91128d
CW		 2893 mutex_lock(&dev->struct_mutex);
2894 intel_finish_fb(crtc->fb);
2895 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2896}
2897
fc316cbe 2898static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
040484af
JB		 2899{
2900 struct drm_device *dev = crtc->dev;
228d3e36 2901 struct intel_encoder *intel_encoder;
040484af
JB		 2902
2903 /*
2904 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2905 * must be driven by its own crtc; no sharing is possible.
2906 */
228d3e36 2907 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
228d3e36 2908 switch (intel_encoder->type) {
040484af 2909 case INTEL_OUTPUT_EDP:
228d3e36 2910 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
040484af
JB		 2911 return false;
2912 continue;
2913 }
2914 }
2915
2916 return true;
2917}
2918
fc316cbe
PZ		 2919static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2920{
2921 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2922}
2923
e615efe4
ED		 2924/* Program iCLKIP clock to the desired frequency */
2925static void lpt_program_iclkip(struct drm_crtc *crtc)
2926{
2927 struct drm_device *dev = crtc->dev;
2928 struct drm_i915_private *dev_priv = dev->dev_private;
2929 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2930 u32 temp;
2931
09153000
DV		 2932 mutex_lock(&dev_priv->dpio_lock);
2933
e615efe4
ED		 2934 /* It is necessary to ungate the pixclk gate prior to programming
2935 * the divisors, and gate it back when it is done.
2936 */
2937 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2938
2939 /* Disable SSCCTL */
2940 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2941 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2942 SBI_SSCCTL_DISABLE,
2943 SBI_ICLK);
e615efe4
ED		 2944
2945 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2946 if (crtc->mode.clock == 20000) {
2947 auxdiv = 1;
2948 divsel = 0x41;
2949 phaseinc = 0x20;
2950 } else {
2951 /* The iCLK virtual clock root frequency is in MHz,
2952 * but the crtc->mode.clock in in KHz. To get the divisors,
2953 * it is necessary to divide one by another, so we
2954 * convert the virtual clock precision to KHz here for higher
2955 * precision.
2956 */
2957 u32 iclk_virtual_root_freq = 172800 * 1000;
2958 u32 iclk_pi_range = 64;
2959 u32 desired_divisor, msb_divisor_value, pi_value;
2960
2961 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2962 msb_divisor_value = desired_divisor / iclk_pi_range;
2963 pi_value = desired_divisor % iclk_pi_range;
2964
2965 auxdiv = 0;
2966 divsel = msb_divisor_value - 2;
2967 phaseinc = pi_value;
2968 }
2969
2970 /* This should not happen with any sane values */
2971 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2972 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2973 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2974 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2975
2976 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2977 crtc->mode.clock,
2978 auxdiv,
2979 divsel,
2980 phasedir,
2981 phaseinc);
2982
2983 /* Program SSCDIVINTPHASE6 */
988d6ee8 2984 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2985 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2986 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2987 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2988 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2989 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2990 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2991 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2992
2993 /* Program SSCAUXDIV */
988d6ee8 2994 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2995 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2996 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2997 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2998
2999 /* Enable modulator and associated divider */
988d6ee8 3000 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3001 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3002 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3003
3004 /* Wait for initialization time */
3005 udelay(24);
3006
3007 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 3008
3009 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 3010}
3011
f67a559d
JB		 3012/*
3013 * Enable PCH resources required for PCH ports:
3014 * - PCH PLLs
3015 * - FDI training & RX/TX
3016 * - update transcoder timings
3017 * - DP transcoding bits
3018 * - transcoder
3019 */
3020static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3021{
3022 struct drm_device *dev = crtc->dev;
3023 struct drm_i915_private *dev_priv = dev->dev_private;
3024 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3025 int pipe = intel_crtc->pipe;
ee7b9f93 3026 u32 reg, temp;
2c07245f 3027
e7e164db
CW		 3028 assert_transcoder_disabled(dev_priv, pipe);
3029
cd986abb
DV		 3030 /* Write the TU size bits before fdi link training, so that error
3031 * detection works. */
3032 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3033 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3034
c98e9dcf 3035 /* For PCH output, training FDI link */
674cf967 3036 dev_priv->display.fdi_link_train(crtc);
2c07245f 3037
572deb37
DV		 3038 /* XXX: pch pll's can be enabled any time before we enable the PCH
3039 * transcoder, and we actually should do this to not upset any PCH
3040 * transcoder that already use the clock when we share it.
3041 *
3042 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3043 * unconditionally resets the pll - we need that to have the right LVDS
3044 * enable sequence. */
b6b4e185 3045 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 3046
303b81e0 3047 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3048 u32 sel;
4b645f14 3049
c98e9dcf 3050 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3051 switch (pipe) {
3052 default:
3053 case 0:
3054 temp |= TRANSA_DPLL_ENABLE;
3055 sel = TRANSA_DPLLB_SEL;
3056 break;
3057 case 1:
3058 temp |= TRANSB_DPLL_ENABLE;
3059 sel = TRANSB_DPLLB_SEL;
3060 break;
3061 case 2:
3062 temp |= TRANSC_DPLL_ENABLE;
3063 sel = TRANSC_DPLLB_SEL;
3064 break;
d64311ab 3065 }
ee7b9f93
JB		 3066 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3067 temp |= sel;
3068 else
3069 temp &= ~sel;
c98e9dcf 3070 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3071 }
5eddb70b 3072
d9b6cb56
JB		 3073 /* set transcoder timing, panel must allow it */
3074 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3075 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3076 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3077 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3078
5eddb70b
CW		 3079 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3080 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3081 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3082 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3083
303b81e0 3084 intel_fdi_normal_train(crtc);
5e84e1a4 3085
c98e9dcf
JB		 3086 /* For PCH DP, enable TRANS_DP_CTL */
3087 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3088 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3089 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3090 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3091 reg = TRANS_DP_CTL(pipe);
3092 temp = I915_READ(reg);
3093 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3094 TRANS_DP_SYNC_MASK |
3095 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3096 temp |= (TRANS_DP_OUTPUT_ENABLE |
3097 TRANS_DP_ENH_FRAMING);
9325c9f0 3098 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3099
3100 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3101 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3102 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3103 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3104
3105 switch (intel_trans_dp_port_sel(crtc)) {
3106 case PCH_DP_B:
5eddb70b 3107 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3108 break;
3109 case PCH_DP_C:
5eddb70b 3110 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3111 break;
3112 case PCH_DP_D:
5eddb70b 3113 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3114 break;
3115 default:
e95d41e1 3116 BUG();
32f9d658 3117 }
2c07245f 3118
5eddb70b 3119 I915_WRITE(reg, temp);
6be4a607 3120 }
b52eb4dc 3121
b8a4f404 3122 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3123}
3124
1507e5bd
PZ		 3125static void lpt_pch_enable(struct drm_crtc *crtc)
3126{
3127 struct drm_device *dev = crtc->dev;
3128 struct drm_i915_private *dev_priv = dev->dev_private;
3129 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
daed2dbb 3130 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
1507e5bd 3131
daed2dbb 3132 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3133
8c52b5e8 3134 lpt_program_iclkip(crtc);
1507e5bd 3135
0540e488 3136 /* Set transcoder timing. */
daed2dbb
PZ		 3137 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3138 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3139 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
1507e5bd 3140
daed2dbb
PZ		 3141 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3142 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3143 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3144 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
1507e5bd 3145
937bb610 3146 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3147}
3148
ee7b9f93
JB		 3149static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3150{
3151 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3152
3153 if (pll == NULL)
3154 return;
3155
3156 if (pll->refcount == 0) {
3157 WARN(1, "bad PCH PLL refcount\n");
3158 return;
3159 }
3160
3161 --pll->refcount;
3162 intel_crtc->pch_pll = NULL;
3163}
3164
3165static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3166{
3167 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3168 struct intel_pch_pll *pll;
3169 int i;
3170
3171 pll = intel_crtc->pch_pll;
3172 if (pll) {
3173 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3174 intel_crtc->base.base.id, pll->pll_reg);
3175 goto prepare;
3176 }
3177
98b6bd99
DV		 3178 if (HAS_PCH_IBX(dev_priv->dev)) {
3179 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3180 i = intel_crtc->pipe;
3181 pll = &dev_priv->pch_plls[i];
3182
3183 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3184 intel_crtc->base.base.id, pll->pll_reg);
3185
3186 goto found;
3187 }
3188
ee7b9f93
JB		 3189 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3190 pll = &dev_priv->pch_plls[i];
3191
3192 /* Only want to check enabled timings first */
3193 if (pll->refcount == 0)
3194 continue;
3195
3196 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3197 fp == I915_READ(pll->fp0_reg)) {
3198 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3199 intel_crtc->base.base.id,
3200 pll->pll_reg, pll->refcount, pll->active);
3201
3202 goto found;
3203 }
3204 }
3205
3206 /* Ok no matching timings, maybe there's a free one? */
3207 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3208 pll = &dev_priv->pch_plls[i];
3209 if (pll->refcount == 0) {
3210 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3211 intel_crtc->base.base.id, pll->pll_reg);
3212 goto found;
3213 }
3214 }
3215
3216 return NULL;
3217
3218found:
3219 intel_crtc->pch_pll = pll;
3220 pll->refcount++;
3221 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3222prepare: /* separate function? */
3223 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3224
e04c7350
CW		 3225 /* Wait for the clocks to stabilize before rewriting the regs */
3226 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3227 POSTING_READ(pll->pll_reg);
3228 udelay(150);
e04c7350
CW		 3229
3230 I915_WRITE(pll->fp0_reg, fp);
3231 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3232 pll->on = false;
3233 return pll;
3234}
3235
d4270e57
JB		 3236void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3237{
3238 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3239 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3240 u32 temp;
3241
3242 temp = I915_READ(dslreg);
3243 udelay(500);
3244 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57
JB		 3245 if (wait_for(I915_READ(dslreg) != temp, 5))
3246 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3247 }
3248}
3249
f67a559d
JB		 3250static void ironlake_crtc_enable(struct drm_crtc *crtc)
3251{
3252 struct drm_device *dev = crtc->dev;
3253 struct drm_i915_private *dev_priv = dev->dev_private;
3254 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3255 struct intel_encoder *encoder;
f67a559d
JB		 3256 int pipe = intel_crtc->pipe;
3257 int plane = intel_crtc->plane;
3258 u32 temp;
3259 bool is_pch_port;
3260
08a48469
DV		 3261 WARN_ON(!crtc->enabled);
3262
f67a559d
JB		 3263 if (intel_crtc->active)
3264 return;
3265
3266 intel_crtc->active = true;
3267 intel_update_watermarks(dev);
3268
3269 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3270 temp = I915_READ(PCH_LVDS);
3271 if ((temp & LVDS_PORT_EN) == 0)
3272 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3273 }
3274
fc316cbe 3275 is_pch_port = ironlake_crtc_driving_pch(crtc);
f67a559d 3276
46b6f814 3277 if (is_pch_port) {
fff367c7
DV		 3278 /* Note: FDI PLL enabling _must_ be done before we enable the
3279 * cpu pipes, hence this is separate from all the other fdi/pch
3280 * enabling. */
88cefb6c 3281 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3282 } else {
3283 assert_fdi_tx_disabled(dev_priv, pipe);
3284 assert_fdi_rx_disabled(dev_priv, pipe);
3285 }
f67a559d 3286
bf49ec8c
DV		 3287 for_each_encoder_on_crtc(dev, crtc, encoder)
3288 if (encoder->pre_enable)
3289 encoder->pre_enable(encoder);
f67a559d
JB		 3290
3291 /* Enable panel fitting for LVDS */
3292 if (dev_priv->pch_pf_size &&
547dc041
JN		 3293 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3294 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
f67a559d
JB		 3295 /* Force use of hard-coded filter coefficients
3296 * as some pre-programmed values are broken,
3297 * e.g. x201.
3298 */
13888d78
PZ		 3299 if (IS_IVYBRIDGE(dev))
3300 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3301 PF_PIPE_SEL_IVB(pipe));
3302 else
3303 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
9db4a9c7
JB		 3304 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3305 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3306 }
3307
9c54c0dd
JB		 3308 /*
3309 * On ILK+ LUT must be loaded before the pipe is running but with
3310 * clocks enabled
3311 */
3312 intel_crtc_load_lut(crtc);
3313
f67a559d
JB		 3314 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3315 intel_enable_plane(dev_priv, plane, pipe);
3316
3317 if (is_pch_port)
3318 ironlake_pch_enable(crtc);
c98e9dcf 3319
d1ebd816 3320 mutex_lock(&dev->struct_mutex);
bed4a673 3321 intel_update_fbc(dev);
d1ebd816
BW		 3322 mutex_unlock(&dev->struct_mutex);
3323
6b383a7f 3324 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3325
fa5c73b1
DV		 3326 for_each_encoder_on_crtc(dev, crtc, encoder)
3327 encoder->enable(encoder);
61b77ddd
DV		 3328
3329 if (HAS_PCH_CPT(dev))
3330 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3331
3332 /*
3333 * There seems to be a race in PCH platform hw (at least on some
3334 * outputs) where an enabled pipe still completes any pageflip right
3335 * away (as if the pipe is off) instead of waiting for vblank. As soon
3336 * as the first vblank happend, everything works as expected. Hence just
3337 * wait for one vblank before returning to avoid strange things
3338 * happening.
3339 */
3340 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3341}
3342
4f771f10
PZ		 3343static void haswell_crtc_enable(struct drm_crtc *crtc)
3344{
3345 struct drm_device *dev = crtc->dev;
3346 struct drm_i915_private *dev_priv = dev->dev_private;
3347 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3348 struct intel_encoder *encoder;
3349 int pipe = intel_crtc->pipe;
3350 int plane = intel_crtc->plane;
4f771f10
PZ		 3351 bool is_pch_port;
3352
3353 WARN_ON(!crtc->enabled);
3354
3355 if (intel_crtc->active)
3356 return;
3357
3358 intel_crtc->active = true;
3359 intel_update_watermarks(dev);
3360
fc316cbe 3361 is_pch_port = haswell_crtc_driving_pch(crtc);
4f771f10 3362
83616634 3363 if (is_pch_port)
04945641 3364 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3365
3366 for_each_encoder_on_crtc(dev, crtc, encoder)
3367 if (encoder->pre_enable)
3368 encoder->pre_enable(encoder);
3369
1f544388 3370 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3371
1f544388 3372 /* Enable panel fitting for eDP */
547dc041
JN		 3373 if (dev_priv->pch_pf_size &&
3374 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4f771f10
PZ		 3375 /* Force use of hard-coded filter coefficients
3376 * as some pre-programmed values are broken,
3377 * e.g. x201.
3378 */
54075a7d
PZ		 3379 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3380 PF_PIPE_SEL_IVB(pipe));
4f771f10
PZ		 3381 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3382 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3383 }
3384
3385 /*
3386 * On ILK+ LUT must be loaded before the pipe is running but with
3387 * clocks enabled
3388 */
3389 intel_crtc_load_lut(crtc);
3390
1f544388
PZ		 3391 intel_ddi_set_pipe_settings(crtc);
3392 intel_ddi_enable_pipe_func(crtc);
4f771f10
PZ		 3393
3394 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3395 intel_enable_plane(dev_priv, plane, pipe);
3396
3397 if (is_pch_port)
1507e5bd 3398 lpt_pch_enable(crtc);
4f771f10
PZ		 3399
3400 mutex_lock(&dev->struct_mutex);
3401 intel_update_fbc(dev);
3402 mutex_unlock(&dev->struct_mutex);
3403
3404 intel_crtc_update_cursor(crtc, true);
3405
3406 for_each_encoder_on_crtc(dev, crtc, encoder)
3407 encoder->enable(encoder);
3408
4f771f10
PZ		 3409 /*
3410 * There seems to be a race in PCH platform hw (at least on some
3411 * outputs) where an enabled pipe still completes any pageflip right
3412 * away (as if the pipe is off) instead of waiting for vblank. As soon
3413 * as the first vblank happend, everything works as expected. Hence just
3414 * wait for one vblank before returning to avoid strange things
3415 * happening.
3416 */
3417 intel_wait_for_vblank(dev, intel_crtc->pipe);
3418}
3419
6be4a607
JB		 3420static void ironlake_crtc_disable(struct drm_crtc *crtc)
3421{
3422 struct drm_device *dev = crtc->dev;
3423 struct drm_i915_private *dev_priv = dev->dev_private;
3424 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3425 struct intel_encoder *encoder;
6be4a607
JB		 3426 int pipe = intel_crtc->pipe;
3427 int plane = intel_crtc->plane;
5eddb70b 3428 u32 reg, temp;
b52eb4dc 3429
ef9c3aee 3430
f7abfe8b
CW		 3431 if (!intel_crtc->active)
3432 return;
3433
ea9d758d
DV		 3434 for_each_encoder_on_crtc(dev, crtc, encoder)
3435 encoder->disable(encoder);
3436
e6c3a2a6 3437 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3438 drm_vblank_off(dev, pipe);
6b383a7f 3439 intel_crtc_update_cursor(crtc, false);
5eddb70b 3440
b24e7179 3441 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3442
973d04f9
CW		 3443 if (dev_priv->cfb_plane == plane)
3444 intel_disable_fbc(dev);
2c07245f 3445
b24e7179 3446 intel_disable_pipe(dev_priv, pipe);
32f9d658 3447
6be4a607 3448 /* Disable PF */
9db4a9c7
JB		 3449 I915_WRITE(PF_CTL(pipe), 0);
3450 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3451
bf49ec8c
DV		 3452 for_each_encoder_on_crtc(dev, crtc, encoder)
3453 if (encoder->post_disable)
3454 encoder->post_disable(encoder);
2c07245f 3455
0fc932b8 3456 ironlake_fdi_disable(crtc);
249c0e64 3457
b8a4f404 3458 ironlake_disable_pch_transcoder(dev_priv, pipe);
913d8d11 3459
6be4a607
JB		 3460 if (HAS_PCH_CPT(dev)) {
3461 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3462 reg = TRANS_DP_CTL(pipe);
3463 temp = I915_READ(reg);
3464 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3465 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3466 I915_WRITE(reg, temp);
6be4a607
JB		 3467
3468 /* disable DPLL_SEL */
3469 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3470 switch (pipe) {
3471 case 0:
d64311ab 3472 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3473 break;
3474 case 1:
6be4a607 3475 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3476 break;
3477 case 2:
4b645f14 3478 /* C shares PLL A or B */
d64311ab 3479 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3480 break;
3481 default:
3482 BUG(); /* wtf */
3483 }
6be4a607 3484 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3485 }
e3421a18 3486
6be4a607 3487 /* disable PCH DPLL */
ee7b9f93 3488 intel_disable_pch_pll(intel_crtc);
8db9d77b 3489
88cefb6c 3490 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3491
f7abfe8b 3492 intel_crtc->active = false;
6b383a7f 3493 intel_update_watermarks(dev);
d1ebd816
BW		 3494
3495 mutex_lock(&dev->struct_mutex);
6b383a7f 3496 intel_update_fbc(dev);
d1ebd816 3497 mutex_unlock(&dev->struct_mutex);
6be4a607 3498}
1b3c7a47 3499
4f771f10 3500static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3501{
4f771f10
PZ		 3502 struct drm_device *dev = crtc->dev;
3503 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3504 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3505 struct intel_encoder *encoder;
3506 int pipe = intel_crtc->pipe;
3507 int plane = intel_crtc->plane;
ad80a810 3508 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
83616634 3509 bool is_pch_port;
ee7b9f93 3510
4f771f10
PZ		 3511 if (!intel_crtc->active)
3512 return;
3513
83616634
PZ		 3514 is_pch_port = haswell_crtc_driving_pch(crtc);
3515
4f771f10
PZ		 3516 for_each_encoder_on_crtc(dev, crtc, encoder)
3517 encoder->disable(encoder);
3518
3519 intel_crtc_wait_for_pending_flips(crtc);
3520 drm_vblank_off(dev, pipe);
3521 intel_crtc_update_cursor(crtc, false);
3522
3523 intel_disable_plane(dev_priv, plane, pipe);
3524
3525 if (dev_priv->cfb_plane == plane)
3526 intel_disable_fbc(dev);
3527
3528 intel_disable_pipe(dev_priv, pipe);
3529
ad80a810 3530 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10
PZ		 3531
3532 /* Disable PF */
3533 I915_WRITE(PF_CTL(pipe), 0);
3534 I915_WRITE(PF_WIN_SZ(pipe), 0);
3535
1f544388 3536 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3537
3538 for_each_encoder_on_crtc(dev, crtc, encoder)
3539 if (encoder->post_disable)
3540 encoder->post_disable(encoder);
3541
83616634 3542 if (is_pch_port) {
ab4d966c 3543 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 3544 intel_ddi_fdi_disable(crtc);
83616634 3545 }
4f771f10
PZ		 3546
3547 intel_crtc->active = false;
3548 intel_update_watermarks(dev);
3549
3550 mutex_lock(&dev->struct_mutex);
3551 intel_update_fbc(dev);
3552 mutex_unlock(&dev->struct_mutex);
3553}
3554
ee7b9f93
JB		 3555static void ironlake_crtc_off(struct drm_crtc *crtc)
3556{
3557 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3558 intel_put_pch_pll(intel_crtc);
3559}
3560
6441ab5f
PZ		 3561static void haswell_crtc_off(struct drm_crtc *crtc)
3562{
a5c961d1
PZ		 3563 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3564
3565 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3566 * start using it. */
1a240d4d 3567 intel_crtc->cpu_transcoder = (enum transcoder) intel_crtc->pipe;
a5c961d1 3568
6441ab5f
PZ		 3569 intel_ddi_put_crtc_pll(crtc);
3570}
3571
02e792fb
DV		 3572static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3573{
02e792fb 3574 if (!enable && intel_crtc->overlay) {
23f09ce3 3575 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3576 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3577
23f09ce3 3578 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3579 dev_priv->mm.interruptible = false;
3580 (void) intel_overlay_switch_off(intel_crtc->overlay);
3581 dev_priv->mm.interruptible = true;
23f09ce3 3582 mutex_unlock(&dev->struct_mutex);
02e792fb 3583 }
02e792fb 3584
5dcdbcb0
CW		 3585 /* Let userspace switch the overlay on again. In most cases userspace
3586 * has to recompute where to put it anyway.
3587 */
02e792fb
DV		 3588}
3589
0b8765c6 3590static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3591{
3592 struct drm_device *dev = crtc->dev;
79e53945
JB		 3593 struct drm_i915_private *dev_priv = dev->dev_private;
3594 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3595 struct intel_encoder *encoder;
79e53945 3596 int pipe = intel_crtc->pipe;
80824003 3597 int plane = intel_crtc->plane;
79e53945 3598
08a48469
DV		 3599 WARN_ON(!crtc->enabled);
3600
f7abfe8b
CW		 3601 if (intel_crtc->active)
3602 return;
3603
3604 intel_crtc->active = true;
6b383a7f
CW		 3605 intel_update_watermarks(dev);
3606
63d7bbe9 3607 intel_enable_pll(dev_priv, pipe);
040484af 3608 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3609 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3610
0b8765c6 3611 intel_crtc_load_lut(crtc);
bed4a673 3612 intel_update_fbc(dev);
79e53945 3613
0b8765c6
JB		 3614 /* Give the overlay scaler a chance to enable if it's on this pipe */
3615 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3616 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3617
fa5c73b1
DV		 3618 for_each_encoder_on_crtc(dev, crtc, encoder)
3619 encoder->enable(encoder);
0b8765c6 3620}
79e53945 3621
0b8765c6
JB		 3622static void i9xx_crtc_disable(struct drm_crtc *crtc)
3623{
3624 struct drm_device *dev = crtc->dev;
3625 struct drm_i915_private *dev_priv = dev->dev_private;
3626 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3627 struct intel_encoder *encoder;
0b8765c6
JB		 3628 int pipe = intel_crtc->pipe;
3629 int plane = intel_crtc->plane;
b690e96c 3630
ef9c3aee 3631
f7abfe8b
CW		 3632 if (!intel_crtc->active)
3633 return;
3634
ea9d758d
DV		 3635 for_each_encoder_on_crtc(dev, crtc, encoder)
3636 encoder->disable(encoder);
3637
0b8765c6 3638 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3639 intel_crtc_wait_for_pending_flips(crtc);
3640 drm_vblank_off(dev, pipe);
0b8765c6 3641 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3642 intel_crtc_update_cursor(crtc, false);
0b8765c6 3643
973d04f9
CW		 3644 if (dev_priv->cfb_plane == plane)
3645 intel_disable_fbc(dev);
79e53945 3646
b24e7179 3647 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3648 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3649 intel_disable_pll(dev_priv, pipe);
0b8765c6 3650
f7abfe8b 3651 intel_crtc->active = false;
6b383a7f
CW		 3652 intel_update_fbc(dev);
3653 intel_update_watermarks(dev);
0b8765c6
JB		 3654}
3655
ee7b9f93
JB		 3656static void i9xx_crtc_off(struct drm_crtc *crtc)
3657{
3658}
3659
976f8a20
DV		 3660static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3661 bool enabled)
2c07245f
ZW		 3662{
3663 struct drm_device *dev = crtc->dev;
3664 struct drm_i915_master_private *master_priv;
3665 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3666 int pipe = intel_crtc->pipe;
79e53945
JB		 3667
3668 if (!dev->primary->master)
3669 return;
3670
3671 master_priv = dev->primary->master->driver_priv;
3672 if (!master_priv->sarea_priv)
3673 return;
3674
79e53945
JB		 3675 switch (pipe) {
3676 case 0:
3677 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3678 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3679 break;
3680 case 1:
3681 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3682 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3683 break;
3684 default:
9db4a9c7 3685 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3686 break;
3687 }
79e53945
JB		 3688}
3689
976f8a20
DV		 3690/**
3691 * Sets the power management mode of the pipe and plane.
3692 */
3693void intel_crtc_update_dpms(struct drm_crtc *crtc)
3694{
3695 struct drm_device *dev = crtc->dev;
3696 struct drm_i915_private *dev_priv = dev->dev_private;
3697 struct intel_encoder *intel_encoder;
3698 bool enable = false;
3699
3700 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3701 enable |= intel_encoder->connectors_active;
3702
3703 if (enable)
3704 dev_priv->display.crtc_enable(crtc);
3705 else
3706 dev_priv->display.crtc_disable(crtc);
3707
3708 intel_crtc_update_sarea(crtc, enable);
3709}
3710
3711static void intel_crtc_noop(struct drm_crtc *crtc)
3712{
3713}
3714
cdd59983
CW		 3715static void intel_crtc_disable(struct drm_crtc *crtc)
3716{
cdd59983 3717 struct drm_device *dev = crtc->dev;
976f8a20 3718 struct drm_connector *connector;
ee7b9f93 3719 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 3720
976f8a20
DV		 3721 /* crtc should still be enabled when we disable it. */
3722 WARN_ON(!crtc->enabled);
3723
3724 dev_priv->display.crtc_disable(crtc);
3725 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3726 dev_priv->display.off(crtc);
3727
931872fc
CW		 3728 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3729 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3730
3731 if (crtc->fb) {
3732 mutex_lock(&dev->struct_mutex);
1690e1eb 3733 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3734 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3735 crtc->fb = NULL;
3736 }
3737
3738 /* Update computed state. */
3739 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3740 if (!connector->encoder || !connector->encoder->crtc)
3741 continue;
3742
3743 if (connector->encoder->crtc != crtc)
3744 continue;
3745
3746 connector->dpms = DRM_MODE_DPMS_OFF;
3747 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3748 }
3749}
3750
a261b246 3751void intel_modeset_disable(struct drm_device *dev)
79e53945 3752{
a261b246
DV		 3753 struct drm_crtc *crtc;
3754
3755 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3756 if (crtc->enabled)
3757 intel_crtc_disable(crtc);
3758 }
79e53945
JB		 3759}
3760
1f703855 3761void intel_encoder_noop(struct drm_encoder *encoder)
79e53945 3762{
7e7d76c3
JB		 3763}
3764
ea5b213a 3765void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3766{
4ef69c7a 3767 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3768
ea5b213a
CW		 3769 drm_encoder_cleanup(encoder);
3770 kfree(intel_encoder);
7e7d76c3
JB		 3771}
3772
5ab432ef
DV		 3773/* Simple dpms helper for encodres with just one connector, no cloning and only
3774 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3775 * state of the entire output pipe. */
3776void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3777{
5ab432ef
DV		 3778 if (mode == DRM_MODE_DPMS_ON) {
3779 encoder->connectors_active = true;
3780
b2cabb0e 3781 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3782 } else {
3783 encoder->connectors_active = false;
3784
b2cabb0e 3785 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3786 }
79e53945
JB		 3787}
3788
0a91ca29
DV		 3789/* Cross check the actual hw state with our own modeset state tracking (and it's
3790 * internal consistency). */
b980514c 3791static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3792{
0a91ca29
DV		 3793 if (connector->get_hw_state(connector)) {
3794 struct intel_encoder *encoder = connector->encoder;
3795 struct drm_crtc *crtc;
3796 bool encoder_enabled;
3797 enum pipe pipe;
3798
3799 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3800 connector->base.base.id,
3801 drm_get_connector_name(&connector->base));
3802
3803 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3804 "wrong connector dpms state\n");
3805 WARN(connector->base.encoder != &encoder->base,
3806 "active connector not linked to encoder\n");
3807 WARN(!encoder->connectors_active,
3808 "encoder->connectors_active not set\n");
3809
3810 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3811 WARN(!encoder_enabled, "encoder not enabled\n");
3812 if (WARN_ON(!encoder->base.crtc))
3813 return;
3814
3815 crtc = encoder->base.crtc;
3816
3817 WARN(!crtc->enabled, "crtc not enabled\n");
3818 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3819 WARN(pipe != to_intel_crtc(crtc)->pipe,
3820 "encoder active on the wrong pipe\n");
3821 }
79e53945
JB		 3822}
3823
5ab432ef
DV		 3824/* Even simpler default implementation, if there's really no special case to
3825 * consider. */
3826void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3827{
5ab432ef 3828 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3829
5ab432ef
DV		 3830 /* All the simple cases only support two dpms states. */
3831 if (mode != DRM_MODE_DPMS_ON)
3832 mode = DRM_MODE_DPMS_OFF;
d4270e57 3833
5ab432ef
DV		 3834 if (mode == connector->dpms)
3835 return;
3836
3837 connector->dpms = mode;
3838
3839 /* Only need to change hw state when actually enabled */
3840 if (encoder->base.crtc)
3841 intel_encoder_dpms(encoder, mode);
3842 else
8af6cf88 3843 WARN_ON(encoder->connectors_active != false);
0a91ca29 3844
b980514c 3845 intel_modeset_check_state(connector->dev);
79e53945
JB		 3846}
3847
f0947c37
DV		 3848/* Simple connector->get_hw_state implementation for encoders that support only
3849 * one connector and no cloning and hence the encoder state determines the state
3850 * of the connector. */
3851bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3852{
24929352 3853 enum pipe pipe = 0;
f0947c37 3854 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3855
f0947c37 3856 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3857}
3858
79e53945 3859static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
35313cde 3860 const struct drm_display_mode *mode,
79e53945
JB		 3861 struct drm_display_mode *adjusted_mode)
3862{
2c07245f 3863 struct drm_device *dev = crtc->dev;
89749350 3864
bad720ff 3865 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3866 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3867 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3868 return false;
2c07245f 3869 }
89749350 3870
f9bef081
DV		 3871 /* All interlaced capable intel hw wants timings in frames. Note though
3872 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3873 * timings, so we need to be careful not to clobber these.*/
3874 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3875 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3876
44f46b42
CW		 3877 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3878 * with a hsync front porch of 0.
3879 */
3880 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3881 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3882 return false;
3883
79e53945
JB		 3884 return true;
3885}
3886
25eb05fc
JB		 3887static int valleyview_get_display_clock_speed(struct drm_device *dev)
3888{
3889 return 400000; /* FIXME */
3890}
3891
e70236a8
JB		 3892static int i945_get_display_clock_speed(struct drm_device *dev)
3893{
3894 return 400000;
3895}
79e53945 3896
e70236a8 3897static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3898{
e70236a8
JB		 3899 return 333000;
3900}
79e53945 3901
e70236a8
JB		 3902static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3903{
3904 return 200000;
3905}
79e53945 3906
e70236a8
JB		 3907static int i915gm_get_display_clock_speed(struct drm_device *dev)
3908{
3909 u16 gcfgc = 0;
79e53945 3910
e70236a8
JB		 3911 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3912
3913 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3914 return 133000;
3915 else {
3916 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3917 case GC_DISPLAY_CLOCK_333_MHZ:
3918 return 333000;
3919 default:
3920 case GC_DISPLAY_CLOCK_190_200_MHZ:
3921 return 190000;
79e53945 3922 }
e70236a8
JB		 3923 }
3924}
3925
3926static int i865_get_display_clock_speed(struct drm_device *dev)
3927{
3928 return 266000;
3929}
3930
3931static int i855_get_display_clock_speed(struct drm_device *dev)
3932{
3933 u16 hpllcc = 0;
3934 /* Assume that the hardware is in the high speed state. This
3935 * should be the default.
3936 */
3937 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3938 case GC_CLOCK_133_200:
3939 case GC_CLOCK_100_200:
3940 return 200000;
3941 case GC_CLOCK_166_250:
3942 return 250000;
3943 case GC_CLOCK_100_133:
79e53945 3944 return 133000;
e70236a8 3945 }
79e53945 3946
e70236a8
JB		 3947 /* Shouldn't happen */
3948 return 0;
3949}
79e53945 3950
e70236a8
JB		 3951static int i830_get_display_clock_speed(struct drm_device *dev)
3952{
3953 return 133000;
79e53945
JB		 3954}
3955
2c07245f 3956static void
e69d0bc1 3957intel_reduce_ratio(uint32_t *num, uint32_t *den)
2c07245f
ZW		 3958{
3959 while (*num > 0xffffff || *den > 0xffffff) {
3960 *num >>= 1;
3961 *den >>= 1;
3962 }
3963}
3964
e69d0bc1
DV		 3965void
3966intel_link_compute_m_n(int bits_per_pixel, int nlanes,
3967 int pixel_clock, int link_clock,
3968 struct intel_link_m_n *m_n)
2c07245f 3969{
e69d0bc1 3970 m_n->tu = 64;
22ed1113
CW		 3971 m_n->gmch_m = bits_per_pixel * pixel_clock;
3972 m_n->gmch_n = link_clock * nlanes * 8;
e69d0bc1 3973 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
22ed1113
CW		 3974 m_n->link_m = pixel_clock;
3975 m_n->link_n = link_clock;
e69d0bc1 3976 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
2c07245f
ZW		 3977}
3978
a7615030
CW		 3979static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3980{
72bbe58c
KP		 3981 if (i915_panel_use_ssc >= 0)
3982 return i915_panel_use_ssc != 0;
3983 return dev_priv->lvds_use_ssc
435793df 3984 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 3985}
3986
5a354204
JB		 3987/**
3988 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3989 * @crtc: CRTC structure
3b5c78a3 3990 * @mode: requested mode
5a354204
JB		 3991 *
3992 * A pipe may be connected to one or more outputs. Based on the depth of the
3993 * attached framebuffer, choose a good color depth to use on the pipe.
3994 *
3995 * If possible, match the pipe depth to the fb depth. In some cases, this
3996 * isn't ideal, because the connected output supports a lesser or restricted
3997 * set of depths. Resolve that here:
3998 * LVDS typically supports only 6bpc, so clamp down in that case
3999 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4000 * Displays may support a restricted set as well, check EDID and clamp as
4001 * appropriate.
3b5c78a3 4002 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 4003 *
4004 * RETURNS:
4005 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4006 * true if they don't match).
4007 */
4008static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
94352cf9 4009 struct drm_framebuffer *fb,
3b5c78a3
AJ		 4010 unsigned int *pipe_bpp,
4011 struct drm_display_mode *mode)
5a354204
JB		 4012{
4013 struct drm_device *dev = crtc->dev;
4014 struct drm_i915_private *dev_priv = dev->dev_private;
5a354204 4015 struct drm_connector *connector;
6c2b7c12 4016 struct intel_encoder *intel_encoder;
5a354204
JB		 4017 unsigned int display_bpc = UINT_MAX, bpc;
4018
4019 /* Walk the encoders & connectors on this crtc, get min bpc */
6c2b7c12 4020 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5a354204
JB		 4021
4022 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4023 unsigned int lvds_bpc;
4024
4025 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4026 LVDS_A3_POWER_UP)
4027 lvds_bpc = 8;
4028 else
4029 lvds_bpc = 6;
4030
4031 if (lvds_bpc < display_bpc) {
82820490 4032 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 4033 display_bpc = lvds_bpc;
4034 }
4035 continue;
4036 }
4037
5a354204
JB		 4038 /* Not one of the known troublemakers, check the EDID */
4039 list_for_each_entry(connector, &dev->mode_config.connector_list,
4040 head) {
6c2b7c12 4041 if (connector->encoder != &intel_encoder->base)
5a354204
JB		 4042 continue;
4043
62ac41a6
JB		 4044 /* Don't use an invalid EDID bpc value */
4045 if (connector->display_info.bpc &&
4046 connector->display_info.bpc < display_bpc) {
82820490 4047 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 4048 display_bpc = connector->display_info.bpc;
4049 }
4050 }
4051
2f4f649a
JN		 4052 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4053 /* Use VBT settings if we have an eDP panel */
4054 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4055
9a30a61f 4056 if (edp_bpc && edp_bpc < display_bpc) {
2f4f649a
JN		 4057 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4058 display_bpc = edp_bpc;
4059 }
4060 continue;
4061 }
4062
5a354204
JB		 4063 /*
4064 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4065 * through, clamp it down. (Note: >12bpc will be caught below.)
4066 */
4067 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4068 if (display_bpc > 8 && display_bpc < 12) {
82820490 4069 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 4070 display_bpc = 12;
4071 } else {
82820490 4072 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 4073 display_bpc = 8;
4074 }
4075 }
4076 }
4077
3b5c78a3
AJ		 4078 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4079 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4080 display_bpc = 6;
4081 }
4082
5a354204
JB		 4083 /*
4084 * We could just drive the pipe at the highest bpc all the time and
4085 * enable dithering as needed, but that costs bandwidth. So choose
4086 * the minimum value that expresses the full color range of the fb but
4087 * also stays within the max display bpc discovered above.
4088 */
4089
94352cf9 4090 switch (fb->depth) {
5a354204
JB		 4091 case 8:
4092 bpc = 8; /* since we go through a colormap */
4093 break;
4094 case 15:
4095 case 16:
4096 bpc = 6; /* min is 18bpp */
4097 break;
4098 case 24:
578393cd 4099 bpc = 8;
5a354204
JB		 4100 break;
4101 case 30:
578393cd 4102 bpc = 10;
5a354204
JB		 4103 break;
4104 case 48:
578393cd 4105 bpc = 12;
5a354204
JB		 4106 break;
4107 default:
4108 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4109 bpc = min((unsigned int)8, display_bpc);
4110 break;
4111 }
4112
578393cd
KP		 4113 display_bpc = min(display_bpc, bpc);
4114
82820490
AJ		 4115 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4116 bpc, display_bpc);
5a354204 4117
578393cd 4118 *pipe_bpp = display_bpc * 3;
5a354204
JB		 4119
4120 return display_bpc != bpc;
4121}
4122
a0c4da24
JB		 4123static int vlv_get_refclk(struct drm_crtc *crtc)
4124{
4125 struct drm_device *dev = crtc->dev;
4126 struct drm_i915_private *dev_priv = dev->dev_private;
4127 int refclk = 27000; /* for DP & HDMI */
4128
4129 return 100000; /* only one validated so far */
4130
4131 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4132 refclk = 96000;
4133 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4134 if (intel_panel_use_ssc(dev_priv))
4135 refclk = 100000;
4136 else
4137 refclk = 96000;
4138 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4139 refclk = 100000;
4140 }
4141
4142 return refclk;
4143}
4144
c65d77d8
JB		 4145static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4146{
4147 struct drm_device *dev = crtc->dev;
4148 struct drm_i915_private *dev_priv = dev->dev_private;
4149 int refclk;
4150
a0c4da24
JB		 4151 if (IS_VALLEYVIEW(dev)) {
4152 refclk = vlv_get_refclk(crtc);
4153 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 4154 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4155 refclk = dev_priv->lvds_ssc_freq * 1000;
4156 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4157 refclk / 1000);
4158 } else if (!IS_GEN2(dev)) {
4159 refclk = 96000;
4160 } else {
4161 refclk = 48000;
4162 }
4163
4164 return refclk;
4165}
4166
4167static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4168 intel_clock_t *clock)
4169{
4170 /* SDVO TV has fixed PLL values depend on its clock range,
4171 this mirrors vbios setting. */
4172 if (adjusted_mode->clock >= 100000
4173 && adjusted_mode->clock < 140500) {
4174 clock->p1 = 2;
4175 clock->p2 = 10;
4176 clock->n = 3;
4177 clock->m1 = 16;
4178 clock->m2 = 8;
4179 } else if (adjusted_mode->clock >= 140500
4180 && adjusted_mode->clock <= 200000) {
4181 clock->p1 = 1;
4182 clock->p2 = 10;
4183 clock->n = 6;
4184 clock->m1 = 12;
4185 clock->m2 = 8;
4186 }
4187}
4188
a7516a05
JB		 4189static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4190 intel_clock_t *clock,
4191 intel_clock_t *reduced_clock)
4192{
4193 struct drm_device *dev = crtc->dev;
4194 struct drm_i915_private *dev_priv = dev->dev_private;
4195 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4196 int pipe = intel_crtc->pipe;
4197 u32 fp, fp2 = 0;
4198
4199 if (IS_PINEVIEW(dev)) {
4200 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4201 if (reduced_clock)
4202 fp2 = (1 << reduced_clock->n) << 16 |
4203 reduced_clock->m1 << 8 | reduced_clock->m2;
4204 } else {
4205 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4206 if (reduced_clock)
4207 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4208 reduced_clock->m2;
4209 }
4210
4211 I915_WRITE(FP0(pipe), fp);
4212
4213 intel_crtc->lowfreq_avail = false;
4214 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4215 reduced_clock && i915_powersave) {
4216 I915_WRITE(FP1(pipe), fp2);
4217 intel_crtc->lowfreq_avail = true;
4218 } else {
4219 I915_WRITE(FP1(pipe), fp);
4220 }
4221}
4222
a0c4da24
JB		 4223static void vlv_update_pll(struct drm_crtc *crtc,
4224 struct drm_display_mode *mode,
4225 struct drm_display_mode *adjusted_mode,
4226 intel_clock_t *clock, intel_clock_t *reduced_clock,
2a8f64ca 4227 int num_connectors)
a0c4da24
JB		 4228{
4229 struct drm_device *dev = crtc->dev;
4230 struct drm_i915_private *dev_priv = dev->dev_private;
4231 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4232 int pipe = intel_crtc->pipe;
4233 u32 dpll, mdiv, pdiv;
4234 u32 bestn, bestm1, bestm2, bestp1, bestp2;
2a8f64ca
VP		 4235 bool is_sdvo;
4236 u32 temp;
a0c4da24 4237
09153000
DV		 4238 mutex_lock(&dev_priv->dpio_lock);
4239
2a8f64ca
VP		 4240 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4241 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
a0c4da24 4242
2a8f64ca
VP		 4243 dpll = DPLL_VGA_MODE_DIS;
4244 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4245 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4246 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4247
4248 I915_WRITE(DPLL(pipe), dpll);
4249 POSTING_READ(DPLL(pipe));
a0c4da24
JB		 4250
4251 bestn = clock->n;
4252 bestm1 = clock->m1;
4253 bestm2 = clock->m2;
4254 bestp1 = clock->p1;
4255 bestp2 = clock->p2;
4256
2a8f64ca
VP		 4257 /*
4258 * In Valleyview PLL and program lane counter registers are exposed
4259 * through DPIO interface
4260 */
a0c4da24
JB		 4261 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4262 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4263 mdiv |= ((bestn << DPIO_N_SHIFT));
4264 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4265 mdiv |= (1 << DPIO_K_SHIFT);
4266 mdiv |= DPIO_ENABLE_CALIBRATION;
4267 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4268
4269 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4270
2a8f64ca 4271 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
a0c4da24 4272 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
2a8f64ca
VP		 4273 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4274 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
a0c4da24
JB		 4275 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4276
2a8f64ca 4277 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
a0c4da24
JB		 4278
4279 dpll |= DPLL_VCO_ENABLE;
4280 I915_WRITE(DPLL(pipe), dpll);
4281 POSTING_READ(DPLL(pipe));
4282 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4283 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4284
2a8f64ca
VP		 4285 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4286
4287 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4288 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4289
4290 I915_WRITE(DPLL(pipe), dpll);
4291
4292 /* Wait for the clocks to stabilize. */
4293 POSTING_READ(DPLL(pipe));
4294 udelay(150);
a0c4da24 4295
2a8f64ca
VP		 4296 temp = 0;
4297 if (is_sdvo) {
4298 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
a0c4da24
JB		 4299 if (temp > 1)
4300 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4301 else
4302 temp = 0;
a0c4da24 4303 }
2a8f64ca
VP		 4304 I915_WRITE(DPLL_MD(pipe), temp);
4305 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4306
2a8f64ca
VP		 4307 /* Now program lane control registers */
4308 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4309 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4310 {
4311 temp = 0x1000C4;
4312 if(pipe == 1)
4313 temp |= (1 << 21);
4314 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4315 }
4316 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4317 {
4318 temp = 0x1000C4;
4319 if(pipe == 1)
4320 temp |= (1 << 21);
4321 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4322 }
09153000
DV		 4323
4324 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4325}
4326
eb1cbe48
DV		 4327static void i9xx_update_pll(struct drm_crtc *crtc,
4328 struct drm_display_mode *mode,
4329 struct drm_display_mode *adjusted_mode,
4330 intel_clock_t *clock, intel_clock_t *reduced_clock,
4331 int num_connectors)
4332{
4333 struct drm_device *dev = crtc->dev;
4334 struct drm_i915_private *dev_priv = dev->dev_private;
4335 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dafd226c 4336 struct intel_encoder *encoder;
eb1cbe48
DV		 4337 int pipe = intel_crtc->pipe;
4338 u32 dpll;
4339 bool is_sdvo;
4340
2a8f64ca
VP		 4341 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4342
eb1cbe48
DV		 4343 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4344 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4345
4346 dpll = DPLL_VGA_MODE_DIS;
4347
4348 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4349 dpll |= DPLLB_MODE_LVDS;
4350 else
4351 dpll |= DPLLB_MODE_DAC_SERIAL;
4352 if (is_sdvo) {
4353 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4354 if (pixel_multiplier > 1) {
4355 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4356 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4357 }
4358 dpll |= DPLL_DVO_HIGH_SPEED;
4359 }
4360 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4361 dpll |= DPLL_DVO_HIGH_SPEED;
4362
4363 /* compute bitmask from p1 value */
4364 if (IS_PINEVIEW(dev))
4365 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4366 else {
4367 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4368 if (IS_G4X(dev) && reduced_clock)
4369 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4370 }
4371 switch (clock->p2) {
4372 case 5:
4373 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4374 break;
4375 case 7:
4376 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4377 break;
4378 case 10:
4379 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4380 break;
4381 case 14:
4382 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4383 break;
4384 }
4385 if (INTEL_INFO(dev)->gen >= 4)
4386 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4387
4388 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4389 dpll |= PLL_REF_INPUT_TVCLKINBC;
4390 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4391 /* XXX: just matching BIOS for now */
4392 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4393 dpll |= 3;
4394 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4395 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4396 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4397 else
4398 dpll |= PLL_REF_INPUT_DREFCLK;
4399
4400 dpll |= DPLL_VCO_ENABLE;
4401 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4402 POSTING_READ(DPLL(pipe));
4403 udelay(150);
4404
dafd226c
DV		 4405 for_each_encoder_on_crtc(dev, crtc, encoder)
4406 if (encoder->pre_pll_enable)
4407 encoder->pre_pll_enable(encoder);
eb1cbe48
DV		 4408
4409 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4410 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4411
4412 I915_WRITE(DPLL(pipe), dpll);
4413
4414 /* Wait for the clocks to stabilize. */
4415 POSTING_READ(DPLL(pipe));
4416 udelay(150);
4417
4418 if (INTEL_INFO(dev)->gen >= 4) {
4419 u32 temp = 0;
4420 if (is_sdvo) {
4421 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4422 if (temp > 1)
4423 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4424 else
4425 temp = 0;
4426 }
4427 I915_WRITE(DPLL_MD(pipe), temp);
4428 } else {
4429 /* The pixel multiplier can only be updated once the
4430 * DPLL is enabled and the clocks are stable.
4431 *
4432 * So write it again.
4433 */
4434 I915_WRITE(DPLL(pipe), dpll);
4435 }
4436}
4437
4438static void i8xx_update_pll(struct drm_crtc *crtc,
4439 struct drm_display_mode *adjusted_mode,
2a8f64ca 4440 intel_clock_t *clock, intel_clock_t *reduced_clock,
eb1cbe48
DV		 4441 int num_connectors)
4442{
4443 struct drm_device *dev = crtc->dev;
4444 struct drm_i915_private *dev_priv = dev->dev_private;
4445 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dafd226c 4446 struct intel_encoder *encoder;
eb1cbe48
DV		 4447 int pipe = intel_crtc->pipe;
4448 u32 dpll;
4449
2a8f64ca
VP		 4450 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4451
eb1cbe48
DV		 4452 dpll = DPLL_VGA_MODE_DIS;
4453
4454 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4455 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4456 } else {
4457 if (clock->p1 == 2)
4458 dpll |= PLL_P1_DIVIDE_BY_TWO;
4459 else
4460 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4461 if (clock->p2 == 4)
4462 dpll |= PLL_P2_DIVIDE_BY_4;
4463 }
4464
4465 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4466 /* XXX: just matching BIOS for now */
4467 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4468 dpll |= 3;
4469 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4470 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4471 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4472 else
4473 dpll |= PLL_REF_INPUT_DREFCLK;
4474
4475 dpll |= DPLL_VCO_ENABLE;
4476 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4477 POSTING_READ(DPLL(pipe));
4478 udelay(150);
4479
dafd226c
DV		 4480 for_each_encoder_on_crtc(dev, crtc, encoder)
4481 if (encoder->pre_pll_enable)
4482 encoder->pre_pll_enable(encoder);
eb1cbe48 4483
5b5896e4
DV		 4484 I915_WRITE(DPLL(pipe), dpll);
4485
4486 /* Wait for the clocks to stabilize. */
4487 POSTING_READ(DPLL(pipe));
4488 udelay(150);
4489
eb1cbe48
DV		 4490 /* The pixel multiplier can only be updated once the
4491 * DPLL is enabled and the clocks are stable.
4492 *
4493 * So write it again.
4494 */
4495 I915_WRITE(DPLL(pipe), dpll);
4496}
4497
b0e77b9c
PZ		 4498static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4499 struct drm_display_mode *mode,
4500 struct drm_display_mode *adjusted_mode)
4501{
4502 struct drm_device *dev = intel_crtc->base.dev;
4503 struct drm_i915_private *dev_priv = dev->dev_private;
4504 enum pipe pipe = intel_crtc->pipe;
fe2b8f9d 4505 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
b0e77b9c
PZ		 4506 uint32_t vsyncshift;
4507
4508 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4509 /* the chip adds 2 halflines automatically */
4510 adjusted_mode->crtc_vtotal -= 1;
4511 adjusted_mode->crtc_vblank_end -= 1;
4512 vsyncshift = adjusted_mode->crtc_hsync_start
4513 - adjusted_mode->crtc_htotal / 2;
4514 } else {
4515 vsyncshift = 0;
4516 }
4517
4518 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4519 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4520
fe2b8f9d 4521 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4522 (adjusted_mode->crtc_hdisplay - 1) |
4523 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4524 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4525 (adjusted_mode->crtc_hblank_start - 1) |
4526 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4527 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4528 (adjusted_mode->crtc_hsync_start - 1) |
4529 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4530
fe2b8f9d 4531 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4532 (adjusted_mode->crtc_vdisplay - 1) |
4533 ((adjusted_mode->crtc_vtotal - 1) << 16));
fe2b8f9d 4534 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c
PZ		 4535 (adjusted_mode->crtc_vblank_start - 1) |
4536 ((adjusted_mode->crtc_vblank_end - 1) << 16));
fe2b8f9d 4537 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4538 (adjusted_mode->crtc_vsync_start - 1) |
4539 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4540
b5e508d4
PZ		 4541 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4542 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4543 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4544 * bits. */
4545 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4546 (pipe == PIPE_B || pipe == PIPE_C))
4547 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4548
b0e77b9c
PZ		 4549 /* pipesrc controls the size that is scaled from, which should
4550 * always be the user's requested size.
4551 */
4552 I915_WRITE(PIPESRC(pipe),
4553 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4554}
4555
f564048e
EA		 4556static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4557 struct drm_display_mode *mode,
4558 struct drm_display_mode *adjusted_mode,
4559 int x, int y,
94352cf9 4560 struct drm_framebuffer *fb)
79e53945
JB		 4561{
4562 struct drm_device *dev = crtc->dev;
4563 struct drm_i915_private *dev_priv = dev->dev_private;
4564 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4565 int pipe = intel_crtc->pipe;
80824003 4566 int plane = intel_crtc->plane;
c751ce4f 4567 int refclk, num_connectors = 0;
652c393a 4568 intel_clock_t clock, reduced_clock;
b0e77b9c 4569 u32 dspcntr, pipeconf;
eb1cbe48
DV		 4570 bool ok, has_reduced_clock = false, is_sdvo = false;
4571 bool is_lvds = false, is_tv = false, is_dp = false;
5eddb70b 4572 struct intel_encoder *encoder;
d4906093 4573 const intel_limit_t *limit;
5c3b82e2 4574 int ret;
79e53945 4575
6c2b7c12 4576 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4577 switch (encoder->type) {
79e53945
JB		 4578 case INTEL_OUTPUT_LVDS:
4579 is_lvds = true;
4580 break;
4581 case INTEL_OUTPUT_SDVO:
7d57382e 4582 case INTEL_OUTPUT_HDMI:
79e53945 4583 is_sdvo = true;
5eddb70b 4584 if (encoder->needs_tv_clock)
e2f0ba97 4585 is_tv = true;
79e53945 4586 break;
79e53945
JB		 4587 case INTEL_OUTPUT_TVOUT:
4588 is_tv = true;
4589 break;
a4fc5ed6
KP		 4590 case INTEL_OUTPUT_DISPLAYPORT:
4591 is_dp = true;
4592 break;
79e53945 4593 }
43565a06 4594
c751ce4f 4595 num_connectors++;
79e53945
JB		 4596 }
4597
c65d77d8 4598 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4599
d4906093
ML		 4600 /*
4601 * Returns a set of divisors for the desired target clock with the given
4602 * refclk, or FALSE. The returned values represent the clock equation:
4603 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4604 */
1b894b59 4605 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4606 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4607 &clock);
79e53945
JB		 4608 if (!ok) {
4609 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4610 return -EINVAL;
79e53945
JB		 4611 }
4612
cda4b7d3 4613 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4614 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4615
ddc9003c 4616 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4617 /*
4618 * Ensure we match the reduced clock's P to the target clock.
4619 * If the clocks don't match, we can't switch the display clock
4620 * by using the FP0/FP1. In such case we will disable the LVDS
4621 * downclock feature.
4622 */
ddc9003c 4623 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4624 dev_priv->lvds_downclock,
4625 refclk,
cec2f356 4626 &clock,
5eddb70b 4627 &reduced_clock);
7026d4ac
ZW		 4628 }
4629
c65d77d8
JB		 4630 if (is_sdvo && is_tv)
4631 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 4632
eb1cbe48 4633 if (IS_GEN2(dev))
2a8f64ca
VP		 4634 i8xx_update_pll(crtc, adjusted_mode, &clock,
4635 has_reduced_clock ? &reduced_clock : NULL,
4636 num_connectors);
a0c4da24 4637 else if (IS_VALLEYVIEW(dev))
2a8f64ca
VP		 4638 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4639 has_reduced_clock ? &reduced_clock : NULL,
4640 num_connectors);
79e53945 4641 else
eb1cbe48
DV		 4642 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4643 has_reduced_clock ? &reduced_clock : NULL,
4644 num_connectors);
79e53945
JB		 4645
4646 /* setup pipeconf */
5eddb70b 4647 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4648
4649 /* Set up the display plane register */
4650 dspcntr = DISPPLANE_GAMMA_ENABLE;
4651
929c77fb
EA		 4652 if (pipe == 0)
4653 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4654 else
4655 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4656
a6c45cf0 4657 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4658 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4659 * core speed.
4660 *
4661 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4662 * pipe == 0 check?
4663 */
e70236a8
JB		 4664 if (mode->clock >
4665 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4666 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4667 else
5eddb70b 4668 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4669 }
4670
3b5c78a3 4671 /* default to 8bpc */
dfd07d72 4672 pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
3b5c78a3 4673 if (is_dp) {
0c96c65b 4674 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
dfd07d72 4675 pipeconf |= PIPECONF_6BPC |
3b5c78a3
AJ		 4676 PIPECONF_DITHER_EN |
4677 PIPECONF_DITHER_TYPE_SP;
4678 }
4679 }
4680
19c03924
GB		 4681 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4682 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
dfd07d72 4683 pipeconf |= PIPECONF_6BPC |
19c03924
GB		 4684 PIPECONF_ENABLE |
4685 I965_PIPECONF_ACTIVE;
4686 }
4687 }
4688
28c97730 4689 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4690 drm_mode_debug_printmodeline(mode);
4691
a7516a05
JB		 4692 if (HAS_PIPE_CXSR(dev)) {
4693 if (intel_crtc->lowfreq_avail) {
28c97730 4694 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 4695 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 4696 } else {
28c97730 4697 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4698 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4699 }
4700 }
4701
617cf884 4702 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575 4703 if (!IS_GEN2(dev) &&
b0e77b9c 4704 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
734b4157 4705 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
b0e77b9c 4706 else
617cf884 4707 pipeconf |= PIPECONF_PROGRESSIVE;
734b4157 4708
b0e77b9c 4709 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4710
4711 /* pipesrc and dspsize control the size that is scaled from,
4712 * which should always be the user's requested size.
79e53945 4713 */
929c77fb
EA		 4714 I915_WRITE(DSPSIZE(plane),
4715 ((mode->vdisplay - 1) << 16) |
4716 (mode->hdisplay - 1));
4717 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4718
f564048e
EA		 4719 I915_WRITE(PIPECONF(pipe), pipeconf);
4720 POSTING_READ(PIPECONF(pipe));
929c77fb 4721 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4722
4723 intel_wait_for_vblank(dev, pipe);
4724
f564048e
EA		 4725 I915_WRITE(DSPCNTR(plane), dspcntr);
4726 POSTING_READ(DSPCNTR(plane));
4727
94352cf9 4728 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4729
4730 intel_update_watermarks(dev);
4731
f564048e
EA		 4732 return ret;
4733}
4734
dde86e2d 4735static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4736{
4737 struct drm_i915_private *dev_priv = dev->dev_private;
4738 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4739 struct intel_encoder *encoder;
13d83a67
JB		 4740 u32 temp;
4741 bool has_lvds = false;
199e5d79
KP		 4742 bool has_cpu_edp = false;
4743 bool has_pch_edp = false;
4744 bool has_panel = false;
99eb6a01
KP		 4745 bool has_ck505 = false;
4746 bool can_ssc = false;
13d83a67
JB		 4747
4748 /* We need to take the global config into account */
199e5d79
KP		 4749 list_for_each_entry(encoder, &mode_config->encoder_list,
4750 base.head) {
4751 switch (encoder->type) {
4752 case INTEL_OUTPUT_LVDS:
4753 has_panel = true;
4754 has_lvds = true;
4755 break;
4756 case INTEL_OUTPUT_EDP:
4757 has_panel = true;
4758 if (intel_encoder_is_pch_edp(&encoder->base))
4759 has_pch_edp = true;
4760 else
4761 has_cpu_edp = true;
4762 break;
13d83a67
JB		 4763 }
4764 }
4765
99eb6a01
KP		 4766 if (HAS_PCH_IBX(dev)) {
4767 has_ck505 = dev_priv->display_clock_mode;
4768 can_ssc = has_ck505;
4769 } else {
4770 has_ck505 = false;
4771 can_ssc = true;
4772 }
4773
4774 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4775 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4776 has_ck505);
13d83a67
JB		 4777
4778 /* Ironlake: try to setup display ref clock before DPLL
4779 * enabling. This is only under driver's control after
4780 * PCH B stepping, previous chipset stepping should be
4781 * ignoring this setting.
4782 */
4783 temp = I915_READ(PCH_DREF_CONTROL);
4784 /* Always enable nonspread source */
4785 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4786
99eb6a01
KP		 4787 if (has_ck505)
4788 temp |= DREF_NONSPREAD_CK505_ENABLE;
4789 else
4790 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4791
199e5d79
KP		 4792 if (has_panel) {
4793 temp &= ~DREF_SSC_SOURCE_MASK;
4794 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4795
199e5d79 4796 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4797 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4798 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4799 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4800 } else
4801 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4802
4803 /* Get SSC going before enabling the outputs */
4804 I915_WRITE(PCH_DREF_CONTROL, temp);
4805 POSTING_READ(PCH_DREF_CONTROL);
4806 udelay(200);
4807
13d83a67
JB		 4808 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4809
4810 /* Enable CPU source on CPU attached eDP */
199e5d79 4811 if (has_cpu_edp) {
99eb6a01 4812 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4813 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4814 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4815 }
13d83a67
JB		 4816 else
4817 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4818 } else
4819 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4820
4821 I915_WRITE(PCH_DREF_CONTROL, temp);
4822 POSTING_READ(PCH_DREF_CONTROL);
4823 udelay(200);
4824 } else {
4825 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4826
4827 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4828
4829 /* Turn off CPU output */
4830 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4831
4832 I915_WRITE(PCH_DREF_CONTROL, temp);
4833 POSTING_READ(PCH_DREF_CONTROL);
4834 udelay(200);
4835
4836 /* Turn off the SSC source */
4837 temp &= ~DREF_SSC_SOURCE_MASK;
4838 temp |= DREF_SSC_SOURCE_DISABLE;
4839
4840 /* Turn off SSC1 */
4841 temp &= ~ DREF_SSC1_ENABLE;
4842
13d83a67
JB		 4843 I915_WRITE(PCH_DREF_CONTROL, temp);
4844 POSTING_READ(PCH_DREF_CONTROL);
4845 udelay(200);
4846 }
4847}
4848
dde86e2d
PZ		 4849/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4850static void lpt_init_pch_refclk(struct drm_device *dev)
4851{
4852 struct drm_i915_private *dev_priv = dev->dev_private;
4853 struct drm_mode_config *mode_config = &dev->mode_config;
4854 struct intel_encoder *encoder;
4855 bool has_vga = false;
4856 bool is_sdv = false;
4857 u32 tmp;
4858
4859 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4860 switch (encoder->type) {
4861 case INTEL_OUTPUT_ANALOG:
4862 has_vga = true;
4863 break;
4864 }
4865 }
4866
4867 if (!has_vga)
4868 return;
4869
4870 /* XXX: Rip out SDV support once Haswell ships for real. */
4871 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
4872 is_sdv = true;
4873
4874 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4875 tmp &= ~SBI_SSCCTL_DISABLE;
4876 tmp |= SBI_SSCCTL_PATHALT;
4877 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4878
4879 udelay(24);
4880
4881 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4882 tmp &= ~SBI_SSCCTL_PATHALT;
4883 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4884
4885 if (!is_sdv) {
4886 tmp = I915_READ(SOUTH_CHICKEN2);
4887 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
4888 I915_WRITE(SOUTH_CHICKEN2, tmp);
4889
4890 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
4891 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
4892 DRM_ERROR("FDI mPHY reset assert timeout\n");
4893
4894 tmp = I915_READ(SOUTH_CHICKEN2);
4895 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
4896 I915_WRITE(SOUTH_CHICKEN2, tmp);
4897
4898 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
4899 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
4900 100))
4901 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
4902 }
4903
4904 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
4905 tmp &= ~(0xFF << 24);
4906 tmp |= (0x12 << 24);
4907 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
4908
4909 if (!is_sdv) {
4910 tmp = intel_sbi_read(dev_priv, 0x808C, SBI_MPHY);
4911 tmp &= ~(0x3 << 6);
4912 tmp |= (1 << 6) | (1 << 0);
4913 intel_sbi_write(dev_priv, 0x808C, tmp, SBI_MPHY);
4914 }
4915
4916 if (is_sdv) {
4917 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
4918 tmp |= 0x7FFF;
4919 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
4920 }
4921
4922 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
4923 tmp |= (1 << 11);
4924 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
4925
4926 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
4927 tmp |= (1 << 11);
4928 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
4929
4930 if (is_sdv) {
4931 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
4932 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4933 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
4934
4935 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
4936 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4937 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
4938
4939 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
4940 tmp |= (0x3F << 8);
4941 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
4942
4943 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
4944 tmp |= (0x3F << 8);
4945 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
4946 }
4947
4948 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
4949 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
4950 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
4951
4952 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
4953 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
4954 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
4955
4956 if (!is_sdv) {
4957 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
4958 tmp &= ~(7 << 13);
4959 tmp |= (5 << 13);
4960 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
4961
4962 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
4963 tmp &= ~(7 << 13);
4964 tmp |= (5 << 13);
4965 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
4966 }
4967
4968 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
4969 tmp &= ~0xFF;
4970 tmp |= 0x1C;
4971 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
4972
4973 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
4974 tmp &= ~0xFF;
4975 tmp |= 0x1C;
4976 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
4977
4978 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
4979 tmp &= ~(0xFF << 16);
4980 tmp |= (0x1C << 16);
4981 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
4982
4983 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
4984 tmp &= ~(0xFF << 16);
4985 tmp |= (0x1C << 16);
4986 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
4987
4988 if (!is_sdv) {
4989 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
4990 tmp |= (1 << 27);
4991 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
4992
4993 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
4994 tmp |= (1 << 27);
4995 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
4996
4997 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
4998 tmp &= ~(0xF << 28);
4999 tmp |= (4 << 28);
5000 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5001
5002 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5003 tmp &= ~(0xF << 28);
5004 tmp |= (4 << 28);
5005 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5006 }
5007
5008 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5009 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5010 tmp |= SBI_DBUFF0_ENABLE;
5011 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5012}
5013
5014/*
5015 * Initialize reference clocks when the driver loads
5016 */
5017void intel_init_pch_refclk(struct drm_device *dev)
5018{
5019 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5020 ironlake_init_pch_refclk(dev);
5021 else if (HAS_PCH_LPT(dev))
5022 lpt_init_pch_refclk(dev);
5023}
5024
d9d444cb
JB		 5025static int ironlake_get_refclk(struct drm_crtc *crtc)
5026{
5027 struct drm_device *dev = crtc->dev;
5028 struct drm_i915_private *dev_priv = dev->dev_private;
5029 struct intel_encoder *encoder;
d9d444cb
JB		 5030 struct intel_encoder *edp_encoder = NULL;
5031 int num_connectors = 0;
5032 bool is_lvds = false;
5033
6c2b7c12 5034 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5035 switch (encoder->type) {
5036 case INTEL_OUTPUT_LVDS:
5037 is_lvds = true;
5038 break;
5039 case INTEL_OUTPUT_EDP:
5040 edp_encoder = encoder;
5041 break;
5042 }
5043 num_connectors++;
5044 }
5045
5046 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5047 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5048 dev_priv->lvds_ssc_freq);
5049 return dev_priv->lvds_ssc_freq * 1000;
5050 }
5051
5052 return 120000;
5053}
5054
c8203565 5055static void ironlake_set_pipeconf(struct drm_crtc *crtc,
f564048e 5056 struct drm_display_mode *adjusted_mode,
c8203565 5057 bool dither)
79e53945 5058{
c8203565 5059 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5060 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5061 int pipe = intel_crtc->pipe;
c8203565
PZ		 5062 uint32_t val;
5063
5064 val = I915_READ(PIPECONF(pipe));
5065
dfd07d72 5066 val &= ~PIPECONF_BPC_MASK;
c8203565
PZ		 5067 switch (intel_crtc->bpp) {
5068 case 18:
dfd07d72 5069 val |= PIPECONF_6BPC;
c8203565
PZ		 5070 break;
5071 case 24:
dfd07d72 5072 val |= PIPECONF_8BPC;
c8203565
PZ		 5073 break;
5074 case 30:
dfd07d72 5075 val |= PIPECONF_10BPC;
c8203565
PZ		 5076 break;
5077 case 36:
dfd07d72 5078 val |= PIPECONF_12BPC;
c8203565
PZ		 5079 break;
5080 default:
cc769b62
PZ		 5081 /* Case prevented by intel_choose_pipe_bpp_dither. */
5082 BUG();
c8203565
PZ		 5083 }
5084
5085 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5086 if (dither)
5087 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5088
5089 val &= ~PIPECONF_INTERLACE_MASK;
5090 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5091 val |= PIPECONF_INTERLACED_ILK;
5092 else
5093 val |= PIPECONF_PROGRESSIVE;
5094
5095 I915_WRITE(PIPECONF(pipe), val);
5096 POSTING_READ(PIPECONF(pipe));
5097}
5098
ee2b0b38
PZ		 5099static void haswell_set_pipeconf(struct drm_crtc *crtc,
5100 struct drm_display_mode *adjusted_mode,
5101 bool dither)
5102{
5103 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5104 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
702e7a56 5105 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
ee2b0b38
PZ		 5106 uint32_t val;
5107
702e7a56 5108 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5109
5110 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5111 if (dither)
5112 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5113
5114 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5115 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5116 val |= PIPECONF_INTERLACED_ILK;
5117 else
5118 val |= PIPECONF_PROGRESSIVE;
5119
702e7a56
PZ		 5120 I915_WRITE(PIPECONF(cpu_transcoder), val);
5121 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5122}
5123
6591c6e4
PZ		 5124static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5125 struct drm_display_mode *adjusted_mode,
5126 intel_clock_t *clock,
5127 bool *has_reduced_clock,
5128 intel_clock_t *reduced_clock)
5129{
5130 struct drm_device *dev = crtc->dev;
5131 struct drm_i915_private *dev_priv = dev->dev_private;
5132 struct intel_encoder *intel_encoder;
5133 int refclk;
d4906093 5134 const intel_limit_t *limit;
6591c6e4 5135 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
79e53945 5136
6591c6e4
PZ		 5137 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5138 switch (intel_encoder->type) {
79e53945
JB		 5139 case INTEL_OUTPUT_LVDS:
5140 is_lvds = true;
5141 break;
5142 case INTEL_OUTPUT_SDVO:
7d57382e 5143 case INTEL_OUTPUT_HDMI:
79e53945 5144 is_sdvo = true;
6591c6e4 5145 if (intel_encoder->needs_tv_clock)
e2f0ba97 5146 is_tv = true;
79e53945 5147 break;
79e53945
JB		 5148 case INTEL_OUTPUT_TVOUT:
5149 is_tv = true;
5150 break;
79e53945
JB		 5151 }
5152 }
5153
d9d444cb 5154 refclk = ironlake_get_refclk(crtc);
79e53945 5155
d4906093
ML		 5156 /*
5157 * Returns a set of divisors for the desired target clock with the given
5158 * refclk, or FALSE. The returned values represent the clock equation:
5159 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5160 */
1b894b59 5161 limit = intel_limit(crtc, refclk);
6591c6e4
PZ		 5162 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5163 clock);
5164 if (!ret)
5165 return false;
cda4b7d3 5166
ddc9003c 5167 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5168 /*
5169 * Ensure we match the reduced clock's P to the target clock.
5170 * If the clocks don't match, we can't switch the display clock
5171 * by using the FP0/FP1. In such case we will disable the LVDS
5172 * downclock feature.
5173 */
6591c6e4
PZ		 5174 *has_reduced_clock = limit->find_pll(limit, crtc,
5175 dev_priv->lvds_downclock,
5176 refclk,
5177 clock,
5178 reduced_clock);
652c393a 5179 }
61e9653f
DV		 5180
5181 if (is_sdvo && is_tv)
6591c6e4
PZ		 5182 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5183
5184 return true;
5185}
5186
01a415fd
DV		 5187static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5188{
5189 struct drm_i915_private *dev_priv = dev->dev_private;
5190 uint32_t temp;
5191
5192 temp = I915_READ(SOUTH_CHICKEN1);
5193 if (temp & FDI_BC_BIFURCATION_SELECT)
5194 return;
5195
5196 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5197 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5198
5199 temp |= FDI_BC_BIFURCATION_SELECT;
5200 DRM_DEBUG_KMS("enabling fdi C rx\n");
5201 I915_WRITE(SOUTH_CHICKEN1, temp);
5202 POSTING_READ(SOUTH_CHICKEN1);
5203}
5204
5205static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5206{
5207 struct drm_device *dev = intel_crtc->base.dev;
5208 struct drm_i915_private *dev_priv = dev->dev_private;
5209 struct intel_crtc *pipe_B_crtc =
5210 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5211
5212 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5213 intel_crtc->pipe, intel_crtc->fdi_lanes);
5214 if (intel_crtc->fdi_lanes > 4) {
5215 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5216 intel_crtc->pipe, intel_crtc->fdi_lanes);
5217 /* Clamp lanes to avoid programming the hw with bogus values. */
5218 intel_crtc->fdi_lanes = 4;
5219
5220 return false;
5221 }
5222
5223 if (dev_priv->num_pipe == 2)
5224 return true;
5225
5226 switch (intel_crtc->pipe) {
5227 case PIPE_A:
5228 return true;
5229 case PIPE_B:
5230 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5231 intel_crtc->fdi_lanes > 2) {
5232 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5233 intel_crtc->pipe, intel_crtc->fdi_lanes);
5234 /* Clamp lanes to avoid programming the hw with bogus values. */
5235 intel_crtc->fdi_lanes = 2;
5236
5237 return false;
5238 }
5239
5240 if (intel_crtc->fdi_lanes > 2)
5241 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5242 else
5243 cpt_enable_fdi_bc_bifurcation(dev);
5244
5245 return true;
5246 case PIPE_C:
5247 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5248 if (intel_crtc->fdi_lanes > 2) {
5249 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5250 intel_crtc->pipe, intel_crtc->fdi_lanes);
5251 /* Clamp lanes to avoid programming the hw with bogus values. */
5252 intel_crtc->fdi_lanes = 2;
5253
5254 return false;
5255 }
5256 } else {
5257 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5258 return false;
5259 }
5260
5261 cpt_enable_fdi_bc_bifurcation(dev);
5262
5263 return true;
5264 default:
5265 BUG();
5266 }
5267}
5268
d4b1931c
PZ		 5269int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5270{
5271 /*
5272 * Account for spread spectrum to avoid
5273 * oversubscribing the link. Max center spread
5274 * is 2.5%; use 5% for safety's sake.
5275 */
5276 u32 bps = target_clock * bpp * 21 / 20;
5277 return bps / (link_bw * 8) + 1;
5278}
5279
f48d8f23
PZ		 5280static void ironlake_set_m_n(struct drm_crtc *crtc,
5281 struct drm_display_mode *mode,
5282 struct drm_display_mode *adjusted_mode)
79e53945
JB		 5283{
5284 struct drm_device *dev = crtc->dev;
5285 struct drm_i915_private *dev_priv = dev->dev_private;
5286 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
afe2fcf5 5287 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
f48d8f23 5288 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
e69d0bc1 5289 struct intel_link_m_n m_n = {0};
f48d8f23
PZ		 5290 int target_clock, pixel_multiplier, lane, link_bw;
5291 bool is_dp = false, is_cpu_edp = false;
79e53945 5292
f48d8f23
PZ		 5293 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5294 switch (intel_encoder->type) {
a4fc5ed6
KP		 5295 case INTEL_OUTPUT_DISPLAYPORT:
5296 is_dp = true;
5297 break;
32f9d658 5298 case INTEL_OUTPUT_EDP:
e3aef172 5299 is_dp = true;
f48d8f23 5300 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5301 is_cpu_edp = true;
f48d8f23 5302 edp_encoder = intel_encoder;
32f9d658 5303 break;
79e53945 5304 }
79e53945 5305 }
61e9653f 5306
2c07245f 5307 /* FDI link */
8febb297
EA		 5308 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5309 lane = 0;
5310 /* CPU eDP doesn't require FDI link, so just set DP M/N
5311 according to current link config */
e3aef172 5312 if (is_cpu_edp) {
e3aef172 5313 intel_edp_link_config(edp_encoder, &lane, &link_bw);
8febb297 5314 } else {
8febb297
EA		 5315 /* FDI is a binary signal running at ~2.7GHz, encoding
5316 * each output octet as 10 bits. The actual frequency
5317 * is stored as a divider into a 100MHz clock, and the
5318 * mode pixel clock is stored in units of 1KHz.
5319 * Hence the bw of each lane in terms of the mode signal
5320 * is:
5321 */
5322 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5323 }
58a27471 5324
94bf2ced
DV		 5325 /* [e]DP over FDI requires target mode clock instead of link clock. */
5326 if (edp_encoder)
5327 target_clock = intel_edp_target_clock(edp_encoder, mode);
5328 else if (is_dp)
5329 target_clock = mode->clock;
5330 else
5331 target_clock = adjusted_mode->clock;
5332
d4b1931c
PZ		 5333 if (!lane)
5334 lane = ironlake_get_lanes_required(target_clock, link_bw,
5335 intel_crtc->bpp);
2c07245f 5336
8febb297
EA		 5337 intel_crtc->fdi_lanes = lane;
5338
5339 if (pixel_multiplier > 1)
5340 link_bw *= pixel_multiplier;
e69d0bc1 5341 intel_link_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw, &m_n);
8febb297 5342
afe2fcf5
PZ		 5343 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5344 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5345 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5346 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
f48d8f23
PZ		 5347}
5348
de13a2e3
PZ		 5349static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5350 struct drm_display_mode *adjusted_mode,
5351 intel_clock_t *clock, u32 fp)
79e53945 5352{
de13a2e3 5353 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5354 struct drm_device *dev = crtc->dev;
5355 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5356 struct intel_encoder *intel_encoder;
5357 uint32_t dpll;
5358 int factor, pixel_multiplier, num_connectors = 0;
5359 bool is_lvds = false, is_sdvo = false, is_tv = false;
5360 bool is_dp = false, is_cpu_edp = false;
79e53945 5361
de13a2e3
PZ		 5362 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5363 switch (intel_encoder->type) {
79e53945
JB		 5364 case INTEL_OUTPUT_LVDS:
5365 is_lvds = true;
5366 break;
5367 case INTEL_OUTPUT_SDVO:
7d57382e 5368 case INTEL_OUTPUT_HDMI:
79e53945 5369 is_sdvo = true;
de13a2e3 5370 if (intel_encoder->needs_tv_clock)
e2f0ba97 5371 is_tv = true;
79e53945 5372 break;
79e53945
JB		 5373 case INTEL_OUTPUT_TVOUT:
5374 is_tv = true;
5375 break;
a4fc5ed6
KP		 5376 case INTEL_OUTPUT_DISPLAYPORT:
5377 is_dp = true;
5378 break;
32f9d658 5379 case INTEL_OUTPUT_EDP:
e3aef172 5380 is_dp = true;
de13a2e3 5381 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5382 is_cpu_edp = true;
32f9d658 5383 break;
79e53945 5384 }
43565a06 5385
c751ce4f 5386 num_connectors++;
79e53945 5387 }
79e53945 5388
c1858123 5389 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5390 factor = 21;
5391 if (is_lvds) {
5392 if ((intel_panel_use_ssc(dev_priv) &&
5393 dev_priv->lvds_ssc_freq == 100) ||
1974cad0 5394 intel_is_dual_link_lvds(dev))
8febb297
EA		 5395 factor = 25;
5396 } else if (is_sdvo && is_tv)
5397 factor = 20;
c1858123 5398
de13a2e3 5399 if (clock->m < factor * clock->n)
8febb297 5400 fp |= FP_CB_TUNE;
2c07245f 5401
5eddb70b 5402 dpll = 0;
2c07245f 5403
a07d6787
EA		 5404 if (is_lvds)
5405 dpll |= DPLLB_MODE_LVDS;
5406 else
5407 dpll |= DPLLB_MODE_DAC_SERIAL;
5408 if (is_sdvo) {
de13a2e3 5409 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
a07d6787
EA		 5410 if (pixel_multiplier > 1) {
5411 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5412 }
a07d6787
EA		 5413 dpll |= DPLL_DVO_HIGH_SPEED;
5414 }
e3aef172 5415 if (is_dp && !is_cpu_edp)
a07d6787 5416 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5417
a07d6787 5418 /* compute bitmask from p1 value */
de13a2e3 5419 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5420 /* also FPA1 */
de13a2e3 5421 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5422
de13a2e3 5423 switch (clock->p2) {
a07d6787
EA		 5424 case 5:
5425 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5426 break;
5427 case 7:
5428 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5429 break;
5430 case 10:
5431 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5432 break;
5433 case 14:
5434 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5435 break;
79e53945
JB		 5436 }
5437
43565a06
KH		 5438 if (is_sdvo && is_tv)
5439 dpll |= PLL_REF_INPUT_TVCLKINBC;
5440 else if (is_tv)
79e53945 5441 /* XXX: just matching BIOS for now */
43565a06 5442 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5443 dpll |= 3;
a7615030 5444 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5445 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5446 else
5447 dpll |= PLL_REF_INPUT_DREFCLK;
5448
de13a2e3
PZ		 5449 return dpll;
5450}
5451
5452static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5453 struct drm_display_mode *mode,
5454 struct drm_display_mode *adjusted_mode,
5455 int x, int y,
5456 struct drm_framebuffer *fb)
5457{
5458 struct drm_device *dev = crtc->dev;
5459 struct drm_i915_private *dev_priv = dev->dev_private;
5460 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5461 int pipe = intel_crtc->pipe;
5462 int plane = intel_crtc->plane;
5463 int num_connectors = 0;
5464 intel_clock_t clock, reduced_clock;
5465 u32 dpll, fp = 0, fp2 = 0;
e2f12b07
PZ		 5466 bool ok, has_reduced_clock = false;
5467 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
de13a2e3 5468 struct intel_encoder *encoder;
de13a2e3 5469 int ret;
01a415fd 5470 bool dither, fdi_config_ok;
de13a2e3
PZ		 5471
5472 for_each_encoder_on_crtc(dev, crtc, encoder) {
5473 switch (encoder->type) {
5474 case INTEL_OUTPUT_LVDS:
5475 is_lvds = true;
5476 break;
de13a2e3
PZ		 5477 case INTEL_OUTPUT_DISPLAYPORT:
5478 is_dp = true;
5479 break;
5480 case INTEL_OUTPUT_EDP:
5481 is_dp = true;
e2f12b07 5482 if (!intel_encoder_is_pch_edp(&encoder->base))
de13a2e3
PZ		 5483 is_cpu_edp = true;
5484 break;
5485 }
5486
5487 num_connectors++;
a07d6787 5488 }
79e53945 5489
5dc5298b
PZ		 5490 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5491 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5492
de13a2e3
PZ		 5493 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5494 &has_reduced_clock, &reduced_clock);
5495 if (!ok) {
5496 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5497 return -EINVAL;
79e53945
JB		 5498 }
5499
de13a2e3
PZ		 5500 /* Ensure that the cursor is valid for the new mode before changing... */
5501 intel_crtc_update_cursor(crtc, true);
5502
5503 /* determine panel color depth */
c8241969
JN		 5504 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5505 adjusted_mode);
de13a2e3
PZ		 5506 if (is_lvds && dev_priv->lvds_dither)
5507 dither = true;
5508
5509 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5510 if (has_reduced_clock)
5511 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5512 reduced_clock.m2;
5513
5514 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
79e53945 5515
f7cb34d4 5516 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5517 drm_mode_debug_printmodeline(mode);
5518
5dc5298b
PZ		 5519 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5520 if (!is_cpu_edp) {
ee7b9f93 5521 struct intel_pch_pll *pll;
4b645f14 5522
ee7b9f93
JB		 5523 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5524 if (pll == NULL) {
5525 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5526 pipe);
4b645f14
JB		 5527 return -EINVAL;
5528 }
ee7b9f93
JB		 5529 } else
5530 intel_put_pch_pll(intel_crtc);
79e53945 5531
2f0c2ad1 5532 if (is_dp && !is_cpu_edp)
a4fc5ed6 5533 intel_dp_set_m_n(crtc, mode, adjusted_mode);
79e53945 5534
dafd226c
DV		 5535 for_each_encoder_on_crtc(dev, crtc, encoder)
5536 if (encoder->pre_pll_enable)
5537 encoder->pre_pll_enable(encoder);
79e53945 5538
ee7b9f93
JB		 5539 if (intel_crtc->pch_pll) {
5540 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5541
32f9d658 5542 /* Wait for the clocks to stabilize. */
ee7b9f93 5543 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5544 udelay(150);
5545
8febb297
EA		 5546 /* The pixel multiplier can only be updated once the
5547 * DPLL is enabled and the clocks are stable.
5548 *
5549 * So write it again.
5550 */
ee7b9f93 5551 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5552 }
79e53945 5553
5eddb70b 5554 intel_crtc->lowfreq_avail = false;
ee7b9f93 5555 if (intel_crtc->pch_pll) {
4b645f14 5556 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5557 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5558 intel_crtc->lowfreq_avail = true;
4b645f14 5559 } else {
ee7b9f93 5560 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5561 }
5562 }
5563
b0e77b9c 5564 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b 5565
01a415fd
DV		 5566 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5567 * ironlake_check_fdi_lanes. */
f48d8f23 5568 ironlake_set_m_n(crtc, mode, adjusted_mode);
2c07245f 5569
01a415fd 5570 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
2c07245f 5571
c8203565 5572 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
79e53945 5573
9d0498a2 5574 intel_wait_for_vblank(dev, pipe);
79e53945 5575
a1f9e77e
PZ		 5576 /* Set up the display plane register */
5577 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5578 POSTING_READ(DSPCNTR(plane));
79e53945 5579
94352cf9 5580 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5581
5582 intel_update_watermarks(dev);
5583
1f8eeabf
ED		 5584 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5585
01a415fd 5586 return fdi_config_ok ? ret : -EINVAL;
79e53945
JB		 5587}
5588
09b4ddf9
PZ		 5589static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5590 struct drm_display_mode *mode,
5591 struct drm_display_mode *adjusted_mode,
5592 int x, int y,
5593 struct drm_framebuffer *fb)
5594{
5595 struct drm_device *dev = crtc->dev;
5596 struct drm_i915_private *dev_priv = dev->dev_private;
5597 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5598 int pipe = intel_crtc->pipe;
5599 int plane = intel_crtc->plane;
5600 int num_connectors = 0;
ed7ef439 5601 bool is_dp = false, is_cpu_edp = false;
09b4ddf9 5602 struct intel_encoder *encoder;
09b4ddf9
PZ		 5603 int ret;
5604 bool dither;
5605
5606 for_each_encoder_on_crtc(dev, crtc, encoder) {
5607 switch (encoder->type) {
09b4ddf9
PZ		 5608 case INTEL_OUTPUT_DISPLAYPORT:
5609 is_dp = true;
5610 break;
5611 case INTEL_OUTPUT_EDP:
5612 is_dp = true;
5613 if (!intel_encoder_is_pch_edp(&encoder->base))
5614 is_cpu_edp = true;
5615 break;
5616 }
5617
5618 num_connectors++;
5619 }
5620
a5c961d1
PZ		 5621 if (is_cpu_edp)
5622 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5623 else
5624 intel_crtc->cpu_transcoder = pipe;
5625
5dc5298b
PZ		 5626 /* We are not sure yet this won't happen. */
5627 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5628 INTEL_PCH_TYPE(dev));
5629
5630 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5631 num_connectors, pipe_name(pipe));
5632
702e7a56 5633 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
1ce42920
PZ		 5634 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5635
5636 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5637
6441ab5f
PZ		 5638 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5639 return -EINVAL;
5640
09b4ddf9
PZ		 5641 /* Ensure that the cursor is valid for the new mode before changing... */
5642 intel_crtc_update_cursor(crtc, true);
5643
5644 /* determine panel color depth */
c8241969
JN		 5645 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5646 adjusted_mode);
09b4ddf9 5647
09b4ddf9
PZ		 5648 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5649 drm_mode_debug_printmodeline(mode);
5650
ed7ef439 5651 if (is_dp && !is_cpu_edp)
09b4ddf9 5652 intel_dp_set_m_n(crtc, mode, adjusted_mode);
09b4ddf9
PZ		 5653
5654 intel_crtc->lowfreq_avail = false;
09b4ddf9
PZ		 5655
5656 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5657
1eb8dfec
PZ		 5658 if (!is_dp || is_cpu_edp)
5659 ironlake_set_m_n(crtc, mode, adjusted_mode);
09b4ddf9 5660
ee2b0b38 5661 haswell_set_pipeconf(crtc, adjusted_mode, dither);
09b4ddf9 5662
09b4ddf9
PZ		 5663 /* Set up the display plane register */
5664 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5665 POSTING_READ(DSPCNTR(plane));
5666
5667 ret = intel_pipe_set_base(crtc, x, y, fb);
5668
5669 intel_update_watermarks(dev);
5670
5671 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5672
1f803ee5 5673 return ret;
79e53945
JB		 5674}
5675
f564048e
EA		 5676static int intel_crtc_mode_set(struct drm_crtc *crtc,
5677 struct drm_display_mode *mode,
5678 struct drm_display_mode *adjusted_mode,
5679 int x, int y,
94352cf9 5680 struct drm_framebuffer *fb)
f564048e
EA		 5681{
5682 struct drm_device *dev = crtc->dev;
5683 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 5684 struct drm_encoder_helper_funcs *encoder_funcs;
5685 struct intel_encoder *encoder;
0b701d27
EA		 5686 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5687 int pipe = intel_crtc->pipe;
f564048e
EA		 5688 int ret;
5689
0b701d27 5690 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5691
f564048e 5692 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
94352cf9 5693 x, y, fb);
79e53945 5694 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5695
9256aa19
DV		 5696 if (ret != 0)
5697 return ret;
5698
5699 for_each_encoder_on_crtc(dev, crtc, encoder) {
5700 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5701 encoder->base.base.id,
5702 drm_get_encoder_name(&encoder->base),
5703 mode->base.id, mode->name);
5704 encoder_funcs = encoder->base.helper_private;
5705 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5706 }
5707
5708 return 0;
79e53945
JB		 5709}
5710
3a9627f4
WF		 5711static bool intel_eld_uptodate(struct drm_connector *connector,
5712 int reg_eldv, uint32_t bits_eldv,
5713 int reg_elda, uint32_t bits_elda,
5714 int reg_edid)
5715{
5716 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5717 uint8_t *eld = connector->eld;
5718 uint32_t i;
5719
5720 i = I915_READ(reg_eldv);
5721 i &= bits_eldv;
5722
5723 if (!eld[0])
5724 return !i;
5725
5726 if (!i)
5727 return false;
5728
5729 i = I915_READ(reg_elda);
5730 i &= ~bits_elda;
5731 I915_WRITE(reg_elda, i);
5732
5733 for (i = 0; i < eld[2]; i++)
5734 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5735 return false;
5736
5737 return true;
5738}
5739
e0dac65e
WF		 5740static void g4x_write_eld(struct drm_connector *connector,
5741 struct drm_crtc *crtc)
5742{
5743 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5744 uint8_t *eld = connector->eld;
5745 uint32_t eldv;
5746 uint32_t len;
5747 uint32_t i;
5748
5749 i = I915_READ(G4X_AUD_VID_DID);
5750
5751 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5752 eldv = G4X_ELDV_DEVCL_DEVBLC;
5753 else
5754 eldv = G4X_ELDV_DEVCTG;
5755
3a9627f4
WF		 5756 if (intel_eld_uptodate(connector,
5757 G4X_AUD_CNTL_ST, eldv,
5758 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5759 G4X_HDMIW_HDMIEDID))
5760 return;
5761
e0dac65e
WF		 5762 i = I915_READ(G4X_AUD_CNTL_ST);
5763 i &= ~(eldv | G4X_ELD_ADDR);
5764 len = (i >> 9) & 0x1f; /* ELD buffer size */
5765 I915_WRITE(G4X_AUD_CNTL_ST, i);
5766
5767 if (!eld[0])
5768 return;
5769
5770 len = min_t(uint8_t, eld[2], len);
5771 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5772 for (i = 0; i < len; i++)
5773 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5774
5775 i = I915_READ(G4X_AUD_CNTL_ST);
5776 i |= eldv;
5777 I915_WRITE(G4X_AUD_CNTL_ST, i);
5778}
5779
83358c85
WX		 5780static void haswell_write_eld(struct drm_connector *connector,
5781 struct drm_crtc *crtc)
5782{
5783 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5784 uint8_t *eld = connector->eld;
5785 struct drm_device *dev = crtc->dev;
5786 uint32_t eldv;
5787 uint32_t i;
5788 int len;
5789 int pipe = to_intel_crtc(crtc)->pipe;
5790 int tmp;
5791
5792 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5793 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5794 int aud_config = HSW_AUD_CFG(pipe);
5795 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5796
5797
5798 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5799
5800 /* Audio output enable */
5801 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5802 tmp = I915_READ(aud_cntrl_st2);
5803 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5804 I915_WRITE(aud_cntrl_st2, tmp);
5805
5806 /* Wait for 1 vertical blank */
5807 intel_wait_for_vblank(dev, pipe);
5808
5809 /* Set ELD valid state */
5810 tmp = I915_READ(aud_cntrl_st2);
5811 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5812 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5813 I915_WRITE(aud_cntrl_st2, tmp);
5814 tmp = I915_READ(aud_cntrl_st2);
5815 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5816
5817 /* Enable HDMI mode */
5818 tmp = I915_READ(aud_config);
5819 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5820 /* clear N_programing_enable and N_value_index */
5821 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5822 I915_WRITE(aud_config, tmp);
5823
5824 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5825
5826 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5827
5828 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5829 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5830 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5831 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5832 } else
5833 I915_WRITE(aud_config, 0);
5834
5835 if (intel_eld_uptodate(connector,
5836 aud_cntrl_st2, eldv,
5837 aud_cntl_st, IBX_ELD_ADDRESS,
5838 hdmiw_hdmiedid))
5839 return;
5840
5841 i = I915_READ(aud_cntrl_st2);
5842 i &= ~eldv;
5843 I915_WRITE(aud_cntrl_st2, i);
5844
5845 if (!eld[0])
5846 return;
5847
5848 i = I915_READ(aud_cntl_st);
5849 i &= ~IBX_ELD_ADDRESS;
5850 I915_WRITE(aud_cntl_st, i);
5851 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5852 DRM_DEBUG_DRIVER("port num:%d\n", i);
5853
5854 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5855 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5856 for (i = 0; i < len; i++)
5857 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5858
5859 i = I915_READ(aud_cntrl_st2);
5860 i |= eldv;
5861 I915_WRITE(aud_cntrl_st2, i);
5862
5863}
5864
e0dac65e
WF		 5865static void ironlake_write_eld(struct drm_connector *connector,
5866 struct drm_crtc *crtc)
5867{
5868 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5869 uint8_t *eld = connector->eld;
5870 uint32_t eldv;
5871 uint32_t i;
5872 int len;
5873 int hdmiw_hdmiedid;
b6daa025 5874 int aud_config;
e0dac65e
WF		 5875 int aud_cntl_st;
5876 int aud_cntrl_st2;
9b138a83 5877 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 5878
b3f33cbf 5879 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 5880 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5881 aud_config = IBX_AUD_CFG(pipe);
5882 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 5883 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 5884 } else {
9b138a83
WX		 5885 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5886 aud_config = CPT_AUD_CFG(pipe);
5887 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 5888 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 5889 }
5890
9b138a83 5891 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 5892
5893 i = I915_READ(aud_cntl_st);
9b138a83 5894 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 5895 if (!i) {
5896 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5897 /* operate blindly on all ports */
1202b4c6
WF		 5898 eldv = IBX_ELD_VALIDB;
5899 eldv |= IBX_ELD_VALIDB << 4;
5900 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 5901 } else {
5902 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 5903 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 5904 }
5905
3a9627f4
WF		 5906 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5907 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5908 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 5909 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5910 } else
5911 I915_WRITE(aud_config, 0);
e0dac65e 5912
3a9627f4
WF		 5913 if (intel_eld_uptodate(connector,
5914 aud_cntrl_st2, eldv,
5915 aud_cntl_st, IBX_ELD_ADDRESS,
5916 hdmiw_hdmiedid))
5917 return;
5918
e0dac65e
WF		 5919 i = I915_READ(aud_cntrl_st2);
5920 i &= ~eldv;
5921 I915_WRITE(aud_cntrl_st2, i);
5922
5923 if (!eld[0])
5924 return;
5925
e0dac65e 5926 i = I915_READ(aud_cntl_st);
1202b4c6 5927 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 5928 I915_WRITE(aud_cntl_st, i);
5929
5930 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5931 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5932 for (i = 0; i < len; i++)
5933 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5934
5935 i = I915_READ(aud_cntrl_st2);
5936 i |= eldv;
5937 I915_WRITE(aud_cntrl_st2, i);
5938}
5939
5940void intel_write_eld(struct drm_encoder *encoder,
5941 struct drm_display_mode *mode)
5942{
5943 struct drm_crtc *crtc = encoder->crtc;
5944 struct drm_connector *connector;
5945 struct drm_device *dev = encoder->dev;
5946 struct drm_i915_private *dev_priv = dev->dev_private;
5947
5948 connector = drm_select_eld(encoder, mode);
5949 if (!connector)
5950 return;
5951
5952 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5953 connector->base.id,
5954 drm_get_connector_name(connector),
5955 connector->encoder->base.id,
5956 drm_get_encoder_name(connector->encoder));
5957
5958 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5959
5960 if (dev_priv->display.write_eld)
5961 dev_priv->display.write_eld(connector, crtc);
5962}
5963
79e53945
JB		 5964/** Loads the palette/gamma unit for the CRTC with the prepared values */
5965void intel_crtc_load_lut(struct drm_crtc *crtc)
5966{
5967 struct drm_device *dev = crtc->dev;
5968 struct drm_i915_private *dev_priv = dev->dev_private;
5969 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 5970 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 5971 int i;
5972
5973 /* The clocks have to be on to load the palette. */
aed3f09d 5974 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 5975 return;
5976
f2b115e6 5977 /* use legacy palette for Ironlake */
bad720ff 5978 if (HAS_PCH_SPLIT(dev))
9db4a9c7 5979 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 5980
79e53945
JB		 5981 for (i = 0; i < 256; i++) {
5982 I915_WRITE(palreg + 4 * i,
5983 (intel_crtc->lut_r[i] << 16) |
5984 (intel_crtc->lut_g[i] << 8) |
5985 intel_crtc->lut_b[i]);
5986 }
5987}
5988
560b85bb
CW		 5989static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5990{
5991 struct drm_device *dev = crtc->dev;
5992 struct drm_i915_private *dev_priv = dev->dev_private;
5993 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5994 bool visible = base != 0;
5995 u32 cntl;
5996
5997 if (intel_crtc->cursor_visible == visible)
5998 return;
5999
9db4a9c7 6000 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6001 if (visible) {
6002 /* On these chipsets we can only modify the base whilst
6003 * the cursor is disabled.
6004 */
9db4a9c7 6005 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6006
6007 cntl &= ~(CURSOR_FORMAT_MASK);
6008 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6009 cntl |= CURSOR_ENABLE |
6010 CURSOR_GAMMA_ENABLE |
6011 CURSOR_FORMAT_ARGB;
6012 } else
6013 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6014 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6015
6016 intel_crtc->cursor_visible = visible;
6017}
6018
6019static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6020{
6021 struct drm_device *dev = crtc->dev;
6022 struct drm_i915_private *dev_priv = dev->dev_private;
6023 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6024 int pipe = intel_crtc->pipe;
6025 bool visible = base != 0;
6026
6027 if (intel_crtc->cursor_visible != visible) {
548f245b 6028 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6029 if (base) {
6030 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6031 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6032 cntl |= pipe << 28; /* Connect to correct pipe */
6033 } else {
6034 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6035 cntl |= CURSOR_MODE_DISABLE;
6036 }
9db4a9c7 6037 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6038
6039 intel_crtc->cursor_visible = visible;
6040 }
6041 /* and commit changes on next vblank */
9db4a9c7 6042 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6043}
6044
65a21cd6
JB		 6045static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6046{
6047 struct drm_device *dev = crtc->dev;
6048 struct drm_i915_private *dev_priv = dev->dev_private;
6049 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6050 int pipe = intel_crtc->pipe;
6051 bool visible = base != 0;
6052
6053 if (intel_crtc->cursor_visible != visible) {
6054 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6055 if (base) {
6056 cntl &= ~CURSOR_MODE;
6057 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6058 } else {
6059 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6060 cntl |= CURSOR_MODE_DISABLE;
6061 }
6062 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6063
6064 intel_crtc->cursor_visible = visible;
6065 }
6066 /* and commit changes on next vblank */
6067 I915_WRITE(CURBASE_IVB(pipe), base);
6068}
6069
cda4b7d3 6070/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6071static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6072 bool on)
cda4b7d3
CW		 6073{
6074 struct drm_device *dev = crtc->dev;
6075 struct drm_i915_private *dev_priv = dev->dev_private;
6076 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6077 int pipe = intel_crtc->pipe;
6078 int x = intel_crtc->cursor_x;
6079 int y = intel_crtc->cursor_y;
560b85bb 6080 u32 base, pos;
cda4b7d3
CW		 6081 bool visible;
6082
6083 pos = 0;
6084
6b383a7f 6085 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6086 base = intel_crtc->cursor_addr;
6087 if (x > (int) crtc->fb->width)
6088 base = 0;
6089
6090 if (y > (int) crtc->fb->height)
6091 base = 0;
6092 } else
6093 base = 0;
6094
6095 if (x < 0) {
6096 if (x + intel_crtc->cursor_width < 0)
6097 base = 0;
6098
6099 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6100 x = -x;
6101 }
6102 pos |= x << CURSOR_X_SHIFT;
6103
6104 if (y < 0) {
6105 if (y + intel_crtc->cursor_height < 0)
6106 base = 0;
6107
6108 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6109 y = -y;
6110 }
6111 pos |= y << CURSOR_Y_SHIFT;
6112
6113 visible = base != 0;
560b85bb 6114 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6115 return;
6116
0cd83aa9 6117 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6118 I915_WRITE(CURPOS_IVB(pipe), pos);
6119 ivb_update_cursor(crtc, base);
6120 } else {
6121 I915_WRITE(CURPOS(pipe), pos);
6122 if (IS_845G(dev) || IS_I865G(dev))
6123 i845_update_cursor(crtc, base);
6124 else
6125 i9xx_update_cursor(crtc, base);
6126 }
cda4b7d3
CW		 6127}
6128
79e53945 6129static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6130 struct drm_file *file,
79e53945
JB		 6131 uint32_t handle,
6132 uint32_t width, uint32_t height)
6133{
6134 struct drm_device *dev = crtc->dev;
6135 struct drm_i915_private *dev_priv = dev->dev_private;
6136 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6137 struct drm_i915_gem_object *obj;
cda4b7d3 6138 uint32_t addr;
3f8bc370 6139 int ret;
79e53945 6140
79e53945
JB		 6141 /* if we want to turn off the cursor ignore width and height */
6142 if (!handle) {
28c97730 6143 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6144 addr = 0;
05394f39 6145 obj = NULL;
5004417d 6146 mutex_lock(&dev->struct_mutex);
3f8bc370 6147 goto finish;
79e53945
JB		 6148 }
6149
6150 /* Currently we only support 64x64 cursors */
6151 if (width != 64 || height != 64) {
6152 DRM_ERROR("we currently only support 64x64 cursors\n");
6153 return -EINVAL;
6154 }
6155
05394f39 6156 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6157 if (&obj->base == NULL)
79e53945
JB		 6158 return -ENOENT;
6159
05394f39 6160 if (obj->base.size < width * height * 4) {
79e53945 6161 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6162 ret = -ENOMEM;
6163 goto fail;
79e53945
JB		 6164 }
6165
71acb5eb 6166 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6167 mutex_lock(&dev->struct_mutex);
b295d1b6 6168 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 6169 if (obj->tiling_mode) {
6170 DRM_ERROR("cursor cannot be tiled\n");
6171 ret = -EINVAL;
6172 goto fail_locked;
6173 }
6174
2da3b9b9 6175 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 6176 if (ret) {
6177 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6178 goto fail_locked;
e7b526bb
CW		 6179 }
6180
d9e86c0e
CW		 6181 ret = i915_gem_object_put_fence(obj);
6182 if (ret) {
2da3b9b9 6183 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6184 goto fail_unpin;
6185 }
6186
05394f39 6187 addr = obj->gtt_offset;
71acb5eb 6188 } else {
6eeefaf3 6189 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6190 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6191 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6192 align);
71acb5eb
DA		 6193 if (ret) {
6194 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6195 goto fail_locked;
71acb5eb 6196 }
05394f39 6197 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6198 }
6199
a6c45cf0 6200 if (IS_GEN2(dev))
14b60391
JB		 6201 I915_WRITE(CURSIZE, (height << 12) | width);
6202
3f8bc370 6203 finish:
3f8bc370 6204 if (intel_crtc->cursor_bo) {
b295d1b6 6205 if (dev_priv->info->cursor_needs_physical) {
05394f39 6206 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6207 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6208 } else
6209 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6210 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6211 }
80824003 6212
7f9872e0 6213 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6214
6215 intel_crtc->cursor_addr = addr;
05394f39 6216 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6217 intel_crtc->cursor_width = width;
6218 intel_crtc->cursor_height = height;
6219
6b383a7f 6220 intel_crtc_update_cursor(crtc, true);
3f8bc370 6221
79e53945 6222 return 0;
e7b526bb 6223fail_unpin:
05394f39 6224 i915_gem_object_unpin(obj);
7f9872e0 6225fail_locked:
34b8686e 6226 mutex_unlock(&dev->struct_mutex);
bc9025bd 6227fail:
05394f39 6228 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6229 return ret;
79e53945
JB		 6230}
6231
6232static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6233{
79e53945 6234 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6235
cda4b7d3
CW		 6236 intel_crtc->cursor_x = x;
6237 intel_crtc->cursor_y = y;
652c393a 6238
6b383a7f 6239 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6240
6241 return 0;
6242}
6243
6244/** Sets the color ramps on behalf of RandR */
6245void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6246 u16 blue, int regno)
6247{
6248 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6249
6250 intel_crtc->lut_r[regno] = red >> 8;
6251 intel_crtc->lut_g[regno] = green >> 8;
6252 intel_crtc->lut_b[regno] = blue >> 8;
6253}
6254
b8c00ac5
DA		 6255void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6256 u16 *blue, int regno)
6257{
6258 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6259
6260 *red = intel_crtc->lut_r[regno] << 8;
6261 *green = intel_crtc->lut_g[regno] << 8;
6262 *blue = intel_crtc->lut_b[regno] << 8;
6263}
6264
79e53945 6265static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6266 u16 *blue, uint32_t start, uint32_t size)
79e53945 6267{
7203425a 6268 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6269 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6270
7203425a 6271 for (i = start; i < end; i++) {
79e53945
JB		 6272 intel_crtc->lut_r[i] = red[i] >> 8;
6273 intel_crtc->lut_g[i] = green[i] >> 8;
6274 intel_crtc->lut_b[i] = blue[i] >> 8;
6275 }
6276
6277 intel_crtc_load_lut(crtc);
6278}
6279
6280/**
6281 * Get a pipe with a simple mode set on it for doing load-based monitor
6282 * detection.
6283 *
6284 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 6285 * its requirements. The pipe will be connected to no other encoders.
79e53945 6286 *
c751ce4f 6287 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 6288 * configured for it. In the future, it could choose to temporarily disable
6289 * some outputs to free up a pipe for its use.
6290 *
6291 * \return crtc, or NULL if no pipes are available.
6292 */
6293
6294/* VESA 640x480x72Hz mode to set on the pipe */
6295static struct drm_display_mode load_detect_mode = {
6296 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6297 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6298};
6299
d2dff872
CW		 6300static struct drm_framebuffer *
6301intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6302 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6303 struct drm_i915_gem_object *obj)
6304{
6305 struct intel_framebuffer *intel_fb;
6306 int ret;
6307
6308 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6309 if (!intel_fb) {
6310 drm_gem_object_unreference_unlocked(&obj->base);
6311 return ERR_PTR(-ENOMEM);
6312 }
6313
6314 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6315 if (ret) {
6316 drm_gem_object_unreference_unlocked(&obj->base);
6317 kfree(intel_fb);
6318 return ERR_PTR(ret);
6319 }
6320
6321 return &intel_fb->base;
6322}
6323
6324static u32
6325intel_framebuffer_pitch_for_width(int width, int bpp)
6326{
6327 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6328 return ALIGN(pitch, 64);
6329}
6330
6331static u32
6332intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6333{
6334 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6335 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6336}
6337
6338static struct drm_framebuffer *
6339intel_framebuffer_create_for_mode(struct drm_device *dev,
6340 struct drm_display_mode *mode,
6341 int depth, int bpp)
6342{
6343 struct drm_i915_gem_object *obj;
0fed39bd 6344 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6345
6346 obj = i915_gem_alloc_object(dev,
6347 intel_framebuffer_size_for_mode(mode, bpp));
6348 if (obj == NULL)
6349 return ERR_PTR(-ENOMEM);
6350
6351 mode_cmd.width = mode->hdisplay;
6352 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6353 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6354 bpp);
5ca0c34a 6355 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6356
6357 return intel_framebuffer_create(dev, &mode_cmd, obj);
6358}
6359
6360static struct drm_framebuffer *
6361mode_fits_in_fbdev(struct drm_device *dev,
6362 struct drm_display_mode *mode)
6363{
6364 struct drm_i915_private *dev_priv = dev->dev_private;
6365 struct drm_i915_gem_object *obj;
6366 struct drm_framebuffer *fb;
6367
6368 if (dev_priv->fbdev == NULL)
6369 return NULL;
6370
6371 obj = dev_priv->fbdev->ifb.obj;
6372 if (obj == NULL)
6373 return NULL;
6374
6375 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6376 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6377 fb->bits_per_pixel))
d2dff872
CW		 6378 return NULL;
6379
01f2c773 6380 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6381 return NULL;
6382
6383 return fb;
6384}
6385
d2434ab7 6386bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6387 struct drm_display_mode *mode,
8261b191 6388 struct intel_load_detect_pipe *old)
79e53945
JB		 6389{
6390 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6391 struct intel_encoder *intel_encoder =
6392 intel_attached_encoder(connector);
79e53945 6393 struct drm_crtc *possible_crtc;
4ef69c7a 6394 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6395 struct drm_crtc *crtc = NULL;
6396 struct drm_device *dev = encoder->dev;
94352cf9 6397 struct drm_framebuffer *fb;
79e53945
JB		 6398 int i = -1;
6399
d2dff872
CW		 6400 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6401 connector->base.id, drm_get_connector_name(connector),
6402 encoder->base.id, drm_get_encoder_name(encoder));
6403
79e53945
JB		 6404 /*
6405 * Algorithm gets a little messy:
7a5e4805 6406 *
79e53945
JB		 6407 * - if the connector already has an assigned crtc, use it (but make
6408 * sure it's on first)
7a5e4805 6409 *
79e53945
JB		 6410 * - try to find the first unused crtc that can drive this connector,
6411 * and use that if we find one
79e53945
JB		 6412 */
6413
6414 /* See if we already have a CRTC for this connector */
6415 if (encoder->crtc) {
6416 crtc = encoder->crtc;
8261b191 6417
24218aac 6418 old->dpms_mode = connector->dpms;
8261b191
CW		 6419 old->load_detect_temp = false;
6420
6421 /* Make sure the crtc and connector are running */
24218aac
DV		 6422 if (connector->dpms != DRM_MODE_DPMS_ON)
6423 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6424
7173188d 6425 return true;
79e53945
JB		 6426 }
6427
6428 /* Find an unused one (if possible) */
6429 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6430 i++;
6431 if (!(encoder->possible_crtcs & (1 << i)))
6432 continue;
6433 if (!possible_crtc->enabled) {
6434 crtc = possible_crtc;
6435 break;
6436 }
79e53945
JB		 6437 }
6438
6439 /*
6440 * If we didn't find an unused CRTC, don't use any.
6441 */
6442 if (!crtc) {
7173188d
CW		 6443 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6444 return false;
79e53945
JB		 6445 }
6446
fc303101
DV		 6447 intel_encoder->new_crtc = to_intel_crtc(crtc);
6448 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6449
6450 intel_crtc = to_intel_crtc(crtc);
24218aac 6451 old->dpms_mode = connector->dpms;
8261b191 6452 old->load_detect_temp = true;
d2dff872 6453 old->release_fb = NULL;
79e53945 6454
6492711d
CW		 6455 if (!mode)
6456 mode = &load_detect_mode;
79e53945 6457
d2dff872
CW		 6458 /* We need a framebuffer large enough to accommodate all accesses
6459 * that the plane may generate whilst we perform load detection.
6460 * We can not rely on the fbcon either being present (we get called
6461 * during its initialisation to detect all boot displays, or it may
6462 * not even exist) or that it is large enough to satisfy the
6463 * requested mode.
6464 */
94352cf9
DV		 6465 fb = mode_fits_in_fbdev(dev, mode);
6466 if (fb == NULL) {
d2dff872 6467 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6468 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6469 old->release_fb = fb;
d2dff872
CW		 6470 } else
6471 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6472 if (IS_ERR(fb)) {
d2dff872 6473 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
0e8b3d3e 6474 return false;
79e53945 6475 }
79e53945 6476
c0c36b94 6477 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6478 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6479 if (old->release_fb)
6480 old->release_fb->funcs->destroy(old->release_fb);
0e8b3d3e 6481 return false;
79e53945 6482 }
7173188d 6483
79e53945 6484 /* let the connector get through one full cycle before testing */
9d0498a2 6485 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6486 return true;
79e53945
JB		 6487}
6488
d2434ab7 6489void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6490 struct intel_load_detect_pipe *old)
79e53945 6491{
d2434ab7
DV		 6492 struct intel_encoder *intel_encoder =
6493 intel_attached_encoder(connector);
4ef69c7a 6494 struct drm_encoder *encoder = &intel_encoder->base;
79e53945 6495
d2dff872
CW		 6496 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6497 connector->base.id, drm_get_connector_name(connector),
6498 encoder->base.id, drm_get_encoder_name(encoder));
6499
8261b191 6500 if (old->load_detect_temp) {
fc303101
DV		 6501 struct drm_crtc *crtc = encoder->crtc;
6502
6503 to_intel_connector(connector)->new_encoder = NULL;
6504 intel_encoder->new_crtc = NULL;
6505 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872
CW		 6506
6507 if (old->release_fb)
6508 old->release_fb->funcs->destroy(old->release_fb);
6509
0622a53c 6510 return;
79e53945
JB		 6511 }
6512
c751ce4f 6513 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6514 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6515 connector->funcs->dpms(connector, old->dpms_mode);
79e53945
JB		 6516}
6517
6518/* Returns the clock of the currently programmed mode of the given pipe. */
6519static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6520{
6521 struct drm_i915_private *dev_priv = dev->dev_private;
6522 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6523 int pipe = intel_crtc->pipe;
548f245b 6524 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6525 u32 fp;
6526 intel_clock_t clock;
6527
6528 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6529 fp = I915_READ(FP0(pipe));
79e53945 6530 else
39adb7a5 6531 fp = I915_READ(FP1(pipe));
79e53945
JB		 6532
6533 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6534 if (IS_PINEVIEW(dev)) {
6535 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6536 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6537 } else {
6538 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6539 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6540 }
6541
a6c45cf0 6542 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6543 if (IS_PINEVIEW(dev))
6544 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6545 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6546 else
6547 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6548 DPLL_FPA01_P1_POST_DIV_SHIFT);
6549
6550 switch (dpll & DPLL_MODE_MASK) {
6551 case DPLLB_MODE_DAC_SERIAL:
6552 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6553 5 : 10;
6554 break;
6555 case DPLLB_MODE_LVDS:
6556 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6557 7 : 14;
6558 break;
6559 default:
28c97730 6560 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6561 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6562 return 0;
6563 }
6564
6565 /* XXX: Handle the 100Mhz refclk */
2177832f 6566 intel_clock(dev, 96000, &clock);
79e53945
JB		 6567 } else {
6568 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6569
6570 if (is_lvds) {
6571 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6572 DPLL_FPA01_P1_POST_DIV_SHIFT);
6573 clock.p2 = 14;
6574
6575 if ((dpll & PLL_REF_INPUT_MASK) ==
6576 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6577 /* XXX: might not be 66MHz */
2177832f 6578 intel_clock(dev, 66000, &clock);
79e53945 6579 } else
2177832f 6580 intel_clock(dev, 48000, &clock);
79e53945
JB		 6581 } else {
6582 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6583 clock.p1 = 2;
6584 else {
6585 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6586 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6587 }
6588 if (dpll & PLL_P2_DIVIDE_BY_4)
6589 clock.p2 = 4;
6590 else
6591 clock.p2 = 2;
6592
2177832f 6593 intel_clock(dev, 48000, &clock);
79e53945
JB		 6594 }
6595 }
6596
6597 /* XXX: It would be nice to validate the clocks, but we can't reuse
6598 * i830PllIsValid() because it relies on the xf86_config connector
6599 * configuration being accurate, which it isn't necessarily.
6600 */
6601
6602 return clock.dot;
6603}
6604
6605/** Returns the currently programmed mode of the given pipe. */
6606struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6607 struct drm_crtc *crtc)
6608{
548f245b 6609 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6610 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fe2b8f9d 6611 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
79e53945 6612 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6613 int htot = I915_READ(HTOTAL(cpu_transcoder));
6614 int hsync = I915_READ(HSYNC(cpu_transcoder));
6615 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6616 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6617
6618 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6619 if (!mode)
6620 return NULL;
6621
6622 mode->clock = intel_crtc_clock_get(dev, crtc);
6623 mode->hdisplay = (htot & 0xffff) + 1;
6624 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6625 mode->hsync_start = (hsync & 0xffff) + 1;
6626 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6627 mode->vdisplay = (vtot & 0xffff) + 1;
6628 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6629 mode->vsync_start = (vsync & 0xffff) + 1;
6630 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6631
6632 drm_mode_set_name(mode);
79e53945
JB		 6633
6634 return mode;
6635}
6636
3dec0095 6637static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6638{
6639 struct drm_device *dev = crtc->dev;
6640 drm_i915_private_t *dev_priv = dev->dev_private;
6641 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6642 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6643 int dpll_reg = DPLL(pipe);
6644 int dpll;
652c393a 6645
bad720ff 6646 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6647 return;
6648
6649 if (!dev_priv->lvds_downclock_avail)
6650 return;
6651
dbdc6479 6652 dpll = I915_READ(dpll_reg);
652c393a 6653 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6654 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6655
8ac5a6d5 6656 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6657
6658 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6659 I915_WRITE(dpll_reg, dpll);
9d0498a2 6660 intel_wait_for_vblank(dev, pipe);
dbdc6479 6661
652c393a
JB		 6662 dpll = I915_READ(dpll_reg);
6663 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6664 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6665 }
652c393a
JB		 6666}
6667
6668static void intel_decrease_pllclock(struct drm_crtc *crtc)
6669{
6670 struct drm_device *dev = crtc->dev;
6671 drm_i915_private_t *dev_priv = dev->dev_private;
6672 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6673
bad720ff 6674 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6675 return;
6676
6677 if (!dev_priv->lvds_downclock_avail)
6678 return;
6679
6680 /*
6681 * Since this is called by a timer, we should never get here in
6682 * the manual case.
6683 */
6684 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6685 int pipe = intel_crtc->pipe;
6686 int dpll_reg = DPLL(pipe);
6687 int dpll;
f6e5b160 6688
44d98a61 6689 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6690
8ac5a6d5 6691 assert_panel_unlocked(dev_priv, pipe);
652c393a 6692
dc257cf1 6693 dpll = I915_READ(dpll_reg);
652c393a
JB		 6694 dpll |= DISPLAY_RATE_SELECT_FPA1;
6695 I915_WRITE(dpll_reg, dpll);
9d0498a2 6696 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6697 dpll = I915_READ(dpll_reg);
6698 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6699 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6700 }
6701
6702}
6703
f047e395
CW		 6704void intel_mark_busy(struct drm_device *dev)
6705{
f047e395
CW		 6706 i915_update_gfx_val(dev->dev_private);
6707}
6708
6709void intel_mark_idle(struct drm_device *dev)
652c393a 6710{
f047e395
CW		 6711}
6712
6713void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6714{
6715 struct drm_device *dev = obj->base.dev;
652c393a 6716 struct drm_crtc *crtc;
652c393a
JB		 6717
6718 if (!i915_powersave)
6719 return;
6720
652c393a 6721 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6722 if (!crtc->fb)
6723 continue;
6724
f047e395
CW		 6725 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6726 intel_increase_pllclock(crtc);
652c393a 6727 }
652c393a
JB		 6728}
6729
f047e395 6730void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
652c393a 6731{
f047e395
CW		 6732 struct drm_device *dev = obj->base.dev;
6733 struct drm_crtc *crtc;
652c393a 6734
f047e395 6735 if (!i915_powersave)
acb87dfb
CW		 6736 return;
6737
652c393a
JB		 6738 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6739 if (!crtc->fb)
6740 continue;
6741
f047e395
CW		 6742 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6743 intel_decrease_pllclock(crtc);
652c393a
JB		 6744 }
6745}
6746
79e53945
JB		 6747static void intel_crtc_destroy(struct drm_crtc *crtc)
6748{
6749 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6750 struct drm_device *dev = crtc->dev;
6751 struct intel_unpin_work *work;
6752 unsigned long flags;
6753
6754 spin_lock_irqsave(&dev->event_lock, flags);
6755 work = intel_crtc->unpin_work;
6756 intel_crtc->unpin_work = NULL;
6757 spin_unlock_irqrestore(&dev->event_lock, flags);
6758
6759 if (work) {
6760 cancel_work_sync(&work->work);
6761 kfree(work);
6762 }
79e53945
JB		 6763
6764 drm_crtc_cleanup(crtc);
67e77c5a 6765
79e53945
JB		 6766 kfree(intel_crtc);
6767}
6768
6b95a207
KH		 6769static void intel_unpin_work_fn(struct work_struct *__work)
6770{
6771 struct intel_unpin_work *work =
6772 container_of(__work, struct intel_unpin_work, work);
b4a98e57 6773 struct drm_device *dev = work->crtc->dev;
6b95a207 6774
b4a98e57 6775 mutex_lock(&dev->struct_mutex);
1690e1eb 6776 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 6777 drm_gem_object_unreference(&work->pending_flip_obj->base);
6778 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6779
b4a98e57
CW		 6780 intel_update_fbc(dev);
6781 mutex_unlock(&dev->struct_mutex);
6782
6783 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
6784 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
6785
6b95a207
KH		 6786 kfree(work);
6787}
6788
1afe3e9d 6789static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6790 struct drm_crtc *crtc)
6b95a207
KH		 6791{
6792 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6793 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6794 struct intel_unpin_work *work;
05394f39 6795 struct drm_i915_gem_object *obj;
6b95a207
KH		 6796 unsigned long flags;
6797
6798 /* Ignore early vblank irqs */
6799 if (intel_crtc == NULL)
6800 return;
6801
6802 spin_lock_irqsave(&dev->event_lock, flags);
6803 work = intel_crtc->unpin_work;
e7d841ca
CW		 6804
6805 /* Ensure we don't miss a work->pending update ... */
6806 smp_rmb();
6807
6808 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 6809 spin_unlock_irqrestore(&dev->event_lock, flags);
6810 return;
6811 }
6812
e7d841ca
CW		 6813 /* and that the unpin work is consistent wrt ->pending. */
6814 smp_rmb();
6815
6b95a207 6816 intel_crtc->unpin_work = NULL;
6b95a207 6817
45a066eb
RC		 6818 if (work->event)
6819 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 6820
0af7e4df
MK		 6821 drm_vblank_put(dev, intel_crtc->pipe);
6822
6b95a207
KH		 6823 spin_unlock_irqrestore(&dev->event_lock, flags);
6824
05394f39 6825 obj = work->old_fb_obj;
d9e86c0e 6826
5bb61643 6827 wake_up(&dev_priv->pending_flip_queue);
b4a98e57
CW		 6828
6829 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 6830
6831 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6832}
6833
1afe3e9d
JB		 6834void intel_finish_page_flip(struct drm_device *dev, int pipe)
6835{
6836 drm_i915_private_t *dev_priv = dev->dev_private;
6837 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6838
49b14a5c 6839 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6840}
6841
6842void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6843{
6844 drm_i915_private_t *dev_priv = dev->dev_private;
6845 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6846
49b14a5c 6847 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6848}
6849
6b95a207
KH		 6850void intel_prepare_page_flip(struct drm_device *dev, int plane)
6851{
6852 drm_i915_private_t *dev_priv = dev->dev_private;
6853 struct intel_crtc *intel_crtc =
6854 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6855 unsigned long flags;
6856
e7d841ca
CW		 6857 /* NB: An MMIO update of the plane base pointer will also
6858 * generate a page-flip completion irq, i.e. every modeset
6859 * is also accompanied by a spurious intel_prepare_page_flip().
6860 */
6b95a207 6861 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 6862 if (intel_crtc->unpin_work)
6863 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 6864 spin_unlock_irqrestore(&dev->event_lock, flags);
6865}
6866
e7d841ca
CW		 6867inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
6868{
6869 /* Ensure that the work item is consistent when activating it ... */
6870 smp_wmb();
6871 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
6872 /* and that it is marked active as soon as the irq could fire. */
6873 smp_wmb();
6874}
6875
8c9f3aaf
JB		 6876static int intel_gen2_queue_flip(struct drm_device *dev,
6877 struct drm_crtc *crtc,
6878 struct drm_framebuffer *fb,
6879 struct drm_i915_gem_object *obj)
6880{
6881 struct drm_i915_private *dev_priv = dev->dev_private;
6882 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6883 u32 flip_mask;
6d90c952 6884 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6885 int ret;
6886
6d90c952 6887 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6888 if (ret)
83d4092b 6889 goto err;
8c9f3aaf 6890
6d90c952 6891 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6892 if (ret)
83d4092b 6893 goto err_unpin;
8c9f3aaf
JB		 6894
6895 /* Can't queue multiple flips, so wait for the previous
6896 * one to finish before executing the next.
6897 */
6898 if (intel_crtc->plane)
6899 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6900 else
6901 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6902 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6903 intel_ring_emit(ring, MI_NOOP);
6904 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6905 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6906 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6907 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 6908 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 6909
6910 intel_mark_page_flip_active(intel_crtc);
6d90c952 6911 intel_ring_advance(ring);
83d4092b
CW		 6912 return 0;
6913
6914err_unpin:
6915 intel_unpin_fb_obj(obj);
6916err:
8c9f3aaf
JB		 6917 return ret;
6918}
6919
6920static int intel_gen3_queue_flip(struct drm_device *dev,
6921 struct drm_crtc *crtc,
6922 struct drm_framebuffer *fb,
6923 struct drm_i915_gem_object *obj)
6924{
6925 struct drm_i915_private *dev_priv = dev->dev_private;
6926 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6927 u32 flip_mask;
6d90c952 6928 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6929 int ret;
6930
6d90c952 6931 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6932 if (ret)
83d4092b 6933 goto err;
8c9f3aaf 6934
6d90c952 6935 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6936 if (ret)
83d4092b 6937 goto err_unpin;
8c9f3aaf
JB		 6938
6939 if (intel_crtc->plane)
6940 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6941 else
6942 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6943 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6944 intel_ring_emit(ring, MI_NOOP);
6945 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6946 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6947 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6948 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 6949 intel_ring_emit(ring, MI_NOOP);
6950
e7d841ca 6951 intel_mark_page_flip_active(intel_crtc);
6d90c952 6952 intel_ring_advance(ring);
83d4092b
CW		 6953 return 0;
6954
6955err_unpin:
6956 intel_unpin_fb_obj(obj);
6957err:
8c9f3aaf
JB		 6958 return ret;
6959}
6960
6961static int intel_gen4_queue_flip(struct drm_device *dev,
6962 struct drm_crtc *crtc,
6963 struct drm_framebuffer *fb,
6964 struct drm_i915_gem_object *obj)
6965{
6966 struct drm_i915_private *dev_priv = dev->dev_private;
6967 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6968 uint32_t pf, pipesrc;
6d90c952 6969 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6970 int ret;
6971
6d90c952 6972 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6973 if (ret)
83d4092b 6974 goto err;
8c9f3aaf 6975
6d90c952 6976 ret = intel_ring_begin(ring, 4);
8c9f3aaf 6977 if (ret)
83d4092b 6978 goto err_unpin;
8c9f3aaf
JB		 6979
6980 /* i965+ uses the linear or tiled offsets from the
6981 * Display Registers (which do not change across a page-flip)
6982 * so we need only reprogram the base address.
6983 */
6d90c952
DV		 6984 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6985 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6986 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 6987 intel_ring_emit(ring,
6988 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6989 obj->tiling_mode);
8c9f3aaf
JB		 6990
6991 /* XXX Enabling the panel-fitter across page-flip is so far
6992 * untested on non-native modes, so ignore it for now.
6993 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6994 */
6995 pf = 0;
6996 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 6997 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 6998
6999 intel_mark_page_flip_active(intel_crtc);
6d90c952 7000 intel_ring_advance(ring);
83d4092b
CW		 7001 return 0;
7002
7003err_unpin:
7004 intel_unpin_fb_obj(obj);
7005err:
8c9f3aaf
JB		 7006 return ret;
7007}
7008
7009static int intel_gen6_queue_flip(struct drm_device *dev,
7010 struct drm_crtc *crtc,
7011 struct drm_framebuffer *fb,
7012 struct drm_i915_gem_object *obj)
7013{
7014 struct drm_i915_private *dev_priv = dev->dev_private;
7015 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7016 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7017 uint32_t pf, pipesrc;
7018 int ret;
7019
6d90c952 7020 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7021 if (ret)
83d4092b 7022 goto err;
8c9f3aaf 7023
6d90c952 7024 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7025 if (ret)
83d4092b 7026 goto err_unpin;
8c9f3aaf 7027
6d90c952
DV		 7028 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7029 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7030 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7031 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7032
dc257cf1
DV		 7033 /* Contrary to the suggestions in the documentation,
7034 * "Enable Panel Fitter" does not seem to be required when page
7035 * flipping with a non-native mode, and worse causes a normal
7036 * modeset to fail.
7037 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7038 */
7039 pf = 0;
8c9f3aaf 7040 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7041 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7042
7043 intel_mark_page_flip_active(intel_crtc);
6d90c952 7044 intel_ring_advance(ring);
83d4092b
CW		 7045 return 0;
7046
7047err_unpin:
7048 intel_unpin_fb_obj(obj);
7049err:
8c9f3aaf
JB		 7050 return ret;
7051}
7052
7c9017e5
JB		 7053/*
7054 * On gen7 we currently use the blit ring because (in early silicon at least)
7055 * the render ring doesn't give us interrpts for page flip completion, which
7056 * means clients will hang after the first flip is queued. Fortunately the
7057 * blit ring generates interrupts properly, so use it instead.
7058 */
7059static int intel_gen7_queue_flip(struct drm_device *dev,
7060 struct drm_crtc *crtc,
7061 struct drm_framebuffer *fb,
7062 struct drm_i915_gem_object *obj)
7063{
7064 struct drm_i915_private *dev_priv = dev->dev_private;
7065 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7066 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7067 uint32_t plane_bit = 0;
7c9017e5
JB		 7068 int ret;
7069
7070 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7071 if (ret)
83d4092b 7072 goto err;
7c9017e5 7073
cb05d8de
DV		 7074 switch(intel_crtc->plane) {
7075 case PLANE_A:
7076 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7077 break;
7078 case PLANE_B:
7079 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7080 break;
7081 case PLANE_C:
7082 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7083 break;
7084 default:
7085 WARN_ONCE(1, "unknown plane in flip command\n");
7086 ret = -ENODEV;
ab3951eb 7087 goto err_unpin;
cb05d8de
DV		 7088 }
7089
7c9017e5
JB		 7090 ret = intel_ring_begin(ring, 4);
7091 if (ret)
83d4092b 7092 goto err_unpin;
7c9017e5 7093
cb05d8de 7094 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7095 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7096 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7097 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7098
7099 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7100 intel_ring_advance(ring);
83d4092b
CW		 7101 return 0;
7102
7103err_unpin:
7104 intel_unpin_fb_obj(obj);
7105err:
7c9017e5
JB		 7106 return ret;
7107}
7108
8c9f3aaf
JB		 7109static int intel_default_queue_flip(struct drm_device *dev,
7110 struct drm_crtc *crtc,
7111 struct drm_framebuffer *fb,
7112 struct drm_i915_gem_object *obj)
7113{
7114 return -ENODEV;
7115}
7116
6b95a207
KH		 7117static int intel_crtc_page_flip(struct drm_crtc *crtc,
7118 struct drm_framebuffer *fb,
7119 struct drm_pending_vblank_event *event)
7120{
7121 struct drm_device *dev = crtc->dev;
7122 struct drm_i915_private *dev_priv = dev->dev_private;
7123 struct intel_framebuffer *intel_fb;
05394f39 7124 struct drm_i915_gem_object *obj;
6b95a207
KH		 7125 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7126 struct intel_unpin_work *work;
8c9f3aaf 7127 unsigned long flags;
52e68630 7128 int ret;
6b95a207 7129
e6a595d2
VS		 7130 /* Can't change pixel format via MI display flips. */
7131 if (fb->pixel_format != crtc->fb->pixel_format)
7132 return -EINVAL;
7133
7134 /*
7135 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7136 * Note that pitch changes could also affect these register.
7137 */
7138 if (INTEL_INFO(dev)->gen > 3 &&
7139 (fb->offsets[0] != crtc->fb->offsets[0] ||
7140 fb->pitches[0] != crtc->fb->pitches[0]))
7141 return -EINVAL;
7142
6b95a207
KH		 7143 work = kzalloc(sizeof *work, GFP_KERNEL);
7144 if (work == NULL)
7145 return -ENOMEM;
7146
6b95a207 7147 work->event = event;
b4a98e57 7148 work->crtc = crtc;
6b95a207 7149 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 7150 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 7151 INIT_WORK(&work->work, intel_unpin_work_fn);
7152
7317c75e
JB		 7153 ret = drm_vblank_get(dev, intel_crtc->pipe);
7154 if (ret)
7155 goto free_work;
7156
6b95a207
KH		 7157 /* We borrow the event spin lock for protecting unpin_work */
7158 spin_lock_irqsave(&dev->event_lock, flags);
7159 if (intel_crtc->unpin_work) {
7160 spin_unlock_irqrestore(&dev->event_lock, flags);
7161 kfree(work);
7317c75e 7162 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7163
7164 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7165 return -EBUSY;
7166 }
7167 intel_crtc->unpin_work = work;
7168 spin_unlock_irqrestore(&dev->event_lock, flags);
7169
7170 intel_fb = to_intel_framebuffer(fb);
7171 obj = intel_fb->obj;
7172
b4a98e57
CW		 7173 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7174 flush_workqueue(dev_priv->wq);
7175
79158103
CW		 7176 ret = i915_mutex_lock_interruptible(dev);
7177 if (ret)
7178 goto cleanup;
6b95a207 7179
75dfca80 7180 /* Reference the objects for the scheduled work. */
05394f39
CW		 7181 drm_gem_object_reference(&work->old_fb_obj->base);
7182 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7183
7184 crtc->fb = fb;
96b099fd 7185
e1f99ce6 7186 work->pending_flip_obj = obj;
e1f99ce6 7187
4e5359cd
SF		 7188 work->enable_stall_check = true;
7189
b4a98e57 7190 atomic_inc(&intel_crtc->unpin_work_count);
e1f99ce6 7191
8c9f3aaf
JB		 7192 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7193 if (ret)
7194 goto cleanup_pending;
6b95a207 7195
7782de3b 7196 intel_disable_fbc(dev);
f047e395 7197 intel_mark_fb_busy(obj);
6b95a207
KH		 7198 mutex_unlock(&dev->struct_mutex);
7199
e5510fac
JB		 7200 trace_i915_flip_request(intel_crtc->plane, obj);
7201
6b95a207 7202 return 0;
96b099fd 7203
8c9f3aaf 7204cleanup_pending:
b4a98e57 7205 atomic_dec(&intel_crtc->unpin_work_count);
05394f39
CW		 7206 drm_gem_object_unreference(&work->old_fb_obj->base);
7207 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7208 mutex_unlock(&dev->struct_mutex);
7209
79158103 7210cleanup:
96b099fd
CW		 7211 spin_lock_irqsave(&dev->event_lock, flags);
7212 intel_crtc->unpin_work = NULL;
7213 spin_unlock_irqrestore(&dev->event_lock, flags);
7214
7317c75e
JB		 7215 drm_vblank_put(dev, intel_crtc->pipe);
7216free_work:
96b099fd
CW		 7217 kfree(work);
7218
7219 return ret;
6b95a207
KH		 7220}
7221
f6e5b160 7222static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7223 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7224 .load_lut = intel_crtc_load_lut,
976f8a20 7225 .disable = intel_crtc_noop,
f6e5b160
CW		 7226};
7227
6ed0f796 7228bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7229{
6ed0f796
DV		 7230 struct intel_encoder *other_encoder;
7231 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7232
6ed0f796
DV		 7233 if (WARN_ON(!crtc))
7234 return false;
7235
7236 list_for_each_entry(other_encoder,
7237 &crtc->dev->mode_config.encoder_list,
7238 base.head) {
7239
7240 if (&other_encoder->new_crtc->base != crtc ||
7241 encoder == other_encoder)
7242 continue;
7243 else
7244 return true;
f47166d2
CW		 7245 }
7246
6ed0f796
DV		 7247 return false;
7248}
47f1c6c9 7249
50f56119
DV		 7250static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7251 struct drm_crtc *crtc)
7252{
7253 struct drm_device *dev;
7254 struct drm_crtc *tmp;
7255 int crtc_mask = 1;
47f1c6c9 7256
50f56119 7257 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7258
50f56119 7259 dev = crtc->dev;
47f1c6c9 7260
50f56119
DV		 7261 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7262 if (tmp == crtc)
7263 break;
7264 crtc_mask <<= 1;
7265 }
47f1c6c9 7266
50f56119
DV		 7267 if (encoder->possible_crtcs & crtc_mask)
7268 return true;
7269 return false;
47f1c6c9 7270}
79e53945 7271
9a935856
DV		 7272/**
7273 * intel_modeset_update_staged_output_state
7274 *
7275 * Updates the staged output configuration state, e.g. after we've read out the
7276 * current hw state.
7277 */
7278static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7279{
9a935856
DV		 7280 struct intel_encoder *encoder;
7281 struct intel_connector *connector;
f6e5b160 7282
9a935856
DV		 7283 list_for_each_entry(connector, &dev->mode_config.connector_list,
7284 base.head) {
7285 connector->new_encoder =
7286 to_intel_encoder(connector->base.encoder);
7287 }
f6e5b160 7288
9a935856
DV		 7289 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7290 base.head) {
7291 encoder->new_crtc =
7292 to_intel_crtc(encoder->base.crtc);
7293 }
f6e5b160
CW		 7294}
7295
9a935856
DV		 7296/**
7297 * intel_modeset_commit_output_state
7298 *
7299 * This function copies the stage display pipe configuration to the real one.
7300 */
7301static void intel_modeset_commit_output_state(struct drm_device *dev)
7302{
7303 struct intel_encoder *encoder;
7304 struct intel_connector *connector;
f6e5b160 7305
9a935856
DV		 7306 list_for_each_entry(connector, &dev->mode_config.connector_list,
7307 base.head) {
7308 connector->base.encoder = &connector->new_encoder->base;
7309 }
f6e5b160 7310
9a935856
DV		 7311 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7312 base.head) {
7313 encoder->base.crtc = &encoder->new_crtc->base;
7314 }
7315}
7316
7758a113
DV		 7317static struct drm_display_mode *
7318intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7319 struct drm_display_mode *mode)
ee7b9f93 7320{
7758a113
DV		 7321 struct drm_device *dev = crtc->dev;
7322 struct drm_display_mode *adjusted_mode;
7323 struct drm_encoder_helper_funcs *encoder_funcs;
7324 struct intel_encoder *encoder;
ee7b9f93 7325
7758a113
DV		 7326 adjusted_mode = drm_mode_duplicate(dev, mode);
7327 if (!adjusted_mode)
7328 return ERR_PTR(-ENOMEM);
7329
7330 /* Pass our mode to the connectors and the CRTC to give them a chance to
7331 * adjust it according to limitations or connector properties, and also
7332 * a chance to reject the mode entirely.
47f1c6c9 7333 */
7758a113
DV		 7334 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7335 base.head) {
47f1c6c9 7336
7758a113
DV		 7337 if (&encoder->new_crtc->base != crtc)
7338 continue;
7339 encoder_funcs = encoder->base.helper_private;
7340 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7341 adjusted_mode))) {
7342 DRM_DEBUG_KMS("Encoder fixup failed\n");
7343 goto fail;
7344 }
ee7b9f93 7345 }
47f1c6c9 7346
7758a113
DV		 7347 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7348 DRM_DEBUG_KMS("CRTC fixup failed\n");
7349 goto fail;
ee7b9f93 7350 }
7758a113 7351 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
47f1c6c9 7352
7758a113
DV		 7353 return adjusted_mode;
7354fail:
7355 drm_mode_destroy(dev, adjusted_mode);
7356 return ERR_PTR(-EINVAL);
ee7b9f93 7357}
47f1c6c9 7358
e2e1ed41
DV		 7359/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7360 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7361static void
7362intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7363 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7364{
7365 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7366 struct drm_device *dev = crtc->dev;
7367 struct intel_encoder *encoder;
7368 struct intel_connector *connector;
7369 struct drm_crtc *tmp_crtc;
79e53945 7370
e2e1ed41 7371 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7372
e2e1ed41
DV		 7373 /* Check which crtcs have changed outputs connected to them, these need
7374 * to be part of the prepare_pipes mask. We don't (yet) support global
7375 * modeset across multiple crtcs, so modeset_pipes will only have one
7376 * bit set at most. */
7377 list_for_each_entry(connector, &dev->mode_config.connector_list,
7378 base.head) {
7379 if (connector->base.encoder == &connector->new_encoder->base)
7380 continue;
79e53945 7381
e2e1ed41
DV		 7382 if (connector->base.encoder) {
7383 tmp_crtc = connector->base.encoder->crtc;
7384
7385 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7386 }
7387
7388 if (connector->new_encoder)
7389 *prepare_pipes |=
7390 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7391 }
7392
e2e1ed41
DV		 7393 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7394 base.head) {
7395 if (encoder->base.crtc == &encoder->new_crtc->base)
7396 continue;
7397
7398 if (encoder->base.crtc) {
7399 tmp_crtc = encoder->base.crtc;
7400
7401 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7402 }
7403
7404 if (encoder->new_crtc)
7405 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7406 }
7407
e2e1ed41
DV		 7408 /* Check for any pipes that will be fully disabled ... */
7409 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7410 base.head) {
7411 bool used = false;
22fd0fab 7412
e2e1ed41
DV		 7413 /* Don't try to disable disabled crtcs. */
7414 if (!intel_crtc->base.enabled)
7415 continue;
7e7d76c3 7416
e2e1ed41
DV		 7417 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7418 base.head) {
7419 if (encoder->new_crtc == intel_crtc)
7420 used = true;
7421 }
7422
7423 if (!used)
7424 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7425 }
7426
e2e1ed41
DV		 7427
7428 /* set_mode is also used to update properties on life display pipes. */
7429 intel_crtc = to_intel_crtc(crtc);
7430 if (crtc->enabled)
7431 *prepare_pipes |= 1 << intel_crtc->pipe;
7432
7433 /* We only support modeset on one single crtc, hence we need to do that
7434 * only for the passed in crtc iff we change anything else than just
7435 * disable crtcs.
7436 *
7437 * This is actually not true, to be fully compatible with the old crtc
7438 * helper we automatically disable _any_ output (i.e. doesn't need to be
7439 * connected to the crtc we're modesetting on) if it's disconnected.
7440 * Which is a rather nutty api (since changed the output configuration
7441 * without userspace's explicit request can lead to confusion), but
7442 * alas. Hence we currently need to modeset on all pipes we prepare. */
7443 if (*prepare_pipes)
7444 *modeset_pipes = *prepare_pipes;
7445
7446 /* ... and mask these out. */
7447 *modeset_pipes &= ~(*disable_pipes);
7448 *prepare_pipes &= ~(*disable_pipes);
47f1c6c9 7449}
79e53945 7450
ea9d758d 7451static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7452{
ea9d758d 7453 struct drm_encoder *encoder;
f6e5b160 7454 struct drm_device *dev = crtc->dev;
f6e5b160 7455
ea9d758d
DV		 7456 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7457 if (encoder->crtc == crtc)
7458 return true;
7459
7460 return false;
7461}
7462
7463static void
7464intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7465{
7466 struct intel_encoder *intel_encoder;
7467 struct intel_crtc *intel_crtc;
7468 struct drm_connector *connector;
7469
7470 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7471 base.head) {
7472 if (!intel_encoder->base.crtc)
7473 continue;
7474
7475 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7476
7477 if (prepare_pipes & (1 << intel_crtc->pipe))
7478 intel_encoder->connectors_active = false;
7479 }
7480
7481 intel_modeset_commit_output_state(dev);
7482
7483 /* Update computed state. */
7484 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7485 base.head) {
7486 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7487 }
7488
7489 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7490 if (!connector->encoder || !connector->encoder->crtc)
7491 continue;
7492
7493 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7494
7495 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7496 struct drm_property *dpms_property =
7497 dev->mode_config.dpms_property;
7498
ea9d758d 7499 connector->dpms = DRM_MODE_DPMS_ON;
662595df 7500 drm_object_property_set_value(&connector->base,
68d34720
DV		 7501 dpms_property,
7502 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7503
7504 intel_encoder = to_intel_encoder(connector->encoder);
7505 intel_encoder->connectors_active = true;
7506 }
7507 }
7508
7509}
7510
25c5b266
DV		 7511#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7512 list_for_each_entry((intel_crtc), \
7513 &(dev)->mode_config.crtc_list, \
7514 base.head) \
7515 if (mask & (1 <<(intel_crtc)->pipe)) \
7516
b980514c 7517void
8af6cf88
DV		 7518intel_modeset_check_state(struct drm_device *dev)
7519{
7520 struct intel_crtc *crtc;
7521 struct intel_encoder *encoder;
7522 struct intel_connector *connector;
7523
7524 list_for_each_entry(connector, &dev->mode_config.connector_list,
7525 base.head) {
7526 /* This also checks the encoder/connector hw state with the
7527 * ->get_hw_state callbacks. */
7528 intel_connector_check_state(connector);
7529
7530 WARN(&connector->new_encoder->base != connector->base.encoder,
7531 "connector's staged encoder doesn't match current encoder\n");
7532 }
7533
7534 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7535 base.head) {
7536 bool enabled = false;
7537 bool active = false;
7538 enum pipe pipe, tracked_pipe;
7539
7540 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7541 encoder->base.base.id,
7542 drm_get_encoder_name(&encoder->base));
7543
7544 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7545 "encoder's stage crtc doesn't match current crtc\n");
7546 WARN(encoder->connectors_active && !encoder->base.crtc,
7547 "encoder's active_connectors set, but no crtc\n");
7548
7549 list_for_each_entry(connector, &dev->mode_config.connector_list,
7550 base.head) {
7551 if (connector->base.encoder != &encoder->base)
7552 continue;
7553 enabled = true;
7554 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7555 active = true;
7556 }
7557 WARN(!!encoder->base.crtc != enabled,
7558 "encoder's enabled state mismatch "
7559 "(expected %i, found %i)\n",
7560 !!encoder->base.crtc, enabled);
7561 WARN(active && !encoder->base.crtc,
7562 "active encoder with no crtc\n");
7563
7564 WARN(encoder->connectors_active != active,
7565 "encoder's computed active state doesn't match tracked active state "
7566 "(expected %i, found %i)\n", active, encoder->connectors_active);
7567
7568 active = encoder->get_hw_state(encoder, &pipe);
7569 WARN(active != encoder->connectors_active,
7570 "encoder's hw state doesn't match sw tracking "
7571 "(expected %i, found %i)\n",
7572 encoder->connectors_active, active);
7573
7574 if (!encoder->base.crtc)
7575 continue;
7576
7577 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7578 WARN(active && pipe != tracked_pipe,
7579 "active encoder's pipe doesn't match"
7580 "(expected %i, found %i)\n",
7581 tracked_pipe, pipe);
7582
7583 }
7584
7585 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7586 base.head) {
7587 bool enabled = false;
7588 bool active = false;
7589
7590 DRM_DEBUG_KMS("[CRTC:%d]\n",
7591 crtc->base.base.id);
7592
7593 WARN(crtc->active && !crtc->base.enabled,
7594 "active crtc, but not enabled in sw tracking\n");
7595
7596 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7597 base.head) {
7598 if (encoder->base.crtc != &crtc->base)
7599 continue;
7600 enabled = true;
7601 if (encoder->connectors_active)
7602 active = true;
7603 }
7604 WARN(active != crtc->active,
7605 "crtc's computed active state doesn't match tracked active state "
7606 "(expected %i, found %i)\n", active, crtc->active);
7607 WARN(enabled != crtc->base.enabled,
7608 "crtc's computed enabled state doesn't match tracked enabled state "
7609 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7610
7611 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7612 }
7613}
7614
c0c36b94
CW		 7615int intel_set_mode(struct drm_crtc *crtc,
7616 struct drm_display_mode *mode,
7617 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 7618{
7619 struct drm_device *dev = crtc->dev;
dbf2b54e 7620 drm_i915_private_t *dev_priv = dev->dev_private;
3ac18232 7621 struct drm_display_mode *adjusted_mode, *saved_mode, *saved_hwmode;
25c5b266
DV		 7622 struct intel_crtc *intel_crtc;
7623 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 7624 int ret = 0;
a6778b3c 7625
3ac18232 7626 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 7627 if (!saved_mode)
7628 return -ENOMEM;
3ac18232 7629 saved_hwmode = saved_mode + 1;
a6778b3c 7630
e2e1ed41 7631 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 7632 &prepare_pipes, &disable_pipes);
7633
7634 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7635 modeset_pipes, prepare_pipes, disable_pipes);
e2e1ed41 7636
976f8a20
DV		 7637 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7638 intel_crtc_disable(&intel_crtc->base);
87f1faa6 7639
3ac18232
TG		 7640 *saved_hwmode = crtc->hwmode;
7641 *saved_mode = crtc->mode;
a6778b3c 7642
25c5b266
DV		 7643 /* Hack: Because we don't (yet) support global modeset on multiple
7644 * crtcs, we don't keep track of the new mode for more than one crtc.
7645 * Hence simply check whether any bit is set in modeset_pipes in all the
7646 * pieces of code that are not yet converted to deal with mutliple crtcs
7647 * changing their mode at the same time. */
7648 adjusted_mode = NULL;
7649 if (modeset_pipes) {
7650 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7651 if (IS_ERR(adjusted_mode)) {
c0c36b94 7652 ret = PTR_ERR(adjusted_mode);
3ac18232 7653 goto out;
25c5b266 7654 }
25c5b266 7655 }
a6778b3c 7656
ea9d758d
DV		 7657 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7658 if (intel_crtc->base.enabled)
7659 dev_priv->display.crtc_disable(&intel_crtc->base);
7660 }
a6778b3c 7661
6c4c86f5
DV		 7662 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7663 * to set it here already despite that we pass it down the callchain.
f6e5b160 7664 */
6c4c86f5 7665 if (modeset_pipes)
25c5b266 7666 crtc->mode = *mode;
7758a113 7667
ea9d758d
DV		 7668 /* Only after disabling all output pipelines that will be changed can we
7669 * update the the output configuration. */
7670 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 7671
47fab737
DV		 7672 if (dev_priv->display.modeset_global_resources)
7673 dev_priv->display.modeset_global_resources(dev);
7674
a6778b3c
DV		 7675 /* Set up the DPLL and any encoders state that needs to adjust or depend
7676 * on the DPLL.
f6e5b160 7677 */
25c5b266 7678 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94
CW		 7679 ret = intel_crtc_mode_set(&intel_crtc->base,
7680 mode, adjusted_mode,
7681 x, y, fb);
7682 if (ret)
7683 goto done;
a6778b3c
DV		 7684 }
7685
7686 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 7687 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7688 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 7689
25c5b266
DV		 7690 if (modeset_pipes) {
7691 /* Store real post-adjustment hardware mode. */
7692 crtc->hwmode = *adjusted_mode;
a6778b3c 7693
25c5b266
DV		 7694 /* Calculate and store various constants which
7695 * are later needed by vblank and swap-completion
7696 * timestamping. They are derived from true hwmode.
7697 */
7698 drm_calc_timestamping_constants(crtc);
7699 }
a6778b3c
DV		 7700
7701 /* FIXME: add subpixel order */
7702done:
7703 drm_mode_destroy(dev, adjusted_mode);
c0c36b94 7704 if (ret && crtc->enabled) {
3ac18232
TG		 7705 crtc->hwmode = *saved_hwmode;
7706 crtc->mode = *saved_mode;
8af6cf88
DV		 7707 } else {
7708 intel_modeset_check_state(dev);
a6778b3c
DV		 7709 }
7710
3ac18232
TG		 7711out:
7712 kfree(saved_mode);
a6778b3c 7713 return ret;
f6e5b160
CW		 7714}
7715
c0c36b94
CW		 7716void intel_crtc_restore_mode(struct drm_crtc *crtc)
7717{
7718 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
7719}
7720
25c5b266
DV		 7721#undef for_each_intel_crtc_masked
7722
d9e55608
DV		 7723static void intel_set_config_free(struct intel_set_config *config)
7724{
7725 if (!config)
7726 return;
7727
1aa4b628
DV		 7728 kfree(config->save_connector_encoders);
7729 kfree(config->save_encoder_crtcs);
d9e55608
DV		 7730 kfree(config);
7731}
7732
85f9eb71
DV		 7733static int intel_set_config_save_state(struct drm_device *dev,
7734 struct intel_set_config *config)
7735{
85f9eb71
DV		 7736 struct drm_encoder *encoder;
7737 struct drm_connector *connector;
7738 int count;
7739
1aa4b628
DV		 7740 config->save_encoder_crtcs =
7741 kcalloc(dev->mode_config.num_encoder,
7742 sizeof(struct drm_crtc *), GFP_KERNEL);
7743 if (!config->save_encoder_crtcs)
85f9eb71
DV		 7744 return -ENOMEM;
7745
1aa4b628
DV		 7746 config->save_connector_encoders =
7747 kcalloc(dev->mode_config.num_connector,
7748 sizeof(struct drm_encoder *), GFP_KERNEL);
7749 if (!config->save_connector_encoders)
85f9eb71
DV		 7750 return -ENOMEM;
7751
7752 /* Copy data. Note that driver private data is not affected.
7753 * Should anything bad happen only the expected state is
7754 * restored, not the drivers personal bookkeeping.
7755 */
85f9eb71
DV		 7756 count = 0;
7757 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 7758 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 7759 }
7760
7761 count = 0;
7762 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 7763 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 7764 }
7765
7766 return 0;
7767}
7768
7769static void intel_set_config_restore_state(struct drm_device *dev,
7770 struct intel_set_config *config)
7771{
9a935856
DV		 7772 struct intel_encoder *encoder;
7773 struct intel_connector *connector;
85f9eb71
DV		 7774 int count;
7775
85f9eb71 7776 count = 0;
9a935856
DV		 7777 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7778 encoder->new_crtc =
7779 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 7780 }
7781
7782 count = 0;
9a935856
DV		 7783 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7784 connector->new_encoder =
7785 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 7786 }
7787}
7788
5e2b584e
DV		 7789static void
7790intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7791 struct intel_set_config *config)
7792{
7793
7794 /* We should be able to check here if the fb has the same properties
7795 * and then just flip_or_move it */
7796 if (set->crtc->fb != set->fb) {
7797 /* If we have no fb then treat it as a full mode set */
7798 if (set->crtc->fb == NULL) {
7799 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7800 config->mode_changed = true;
7801 } else if (set->fb == NULL) {
7802 config->mode_changed = true;
7803 } else if (set->fb->depth != set->crtc->fb->depth) {
7804 config->mode_changed = true;
7805 } else if (set->fb->bits_per_pixel !=
7806 set->crtc->fb->bits_per_pixel) {
7807 config->mode_changed = true;
7808 } else
7809 config->fb_changed = true;
7810 }
7811
835c5873 7812 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 7813 config->fb_changed = true;
7814
7815 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7816 DRM_DEBUG_KMS("modes are different, full mode set\n");
7817 drm_mode_debug_printmodeline(&set->crtc->mode);
7818 drm_mode_debug_printmodeline(set->mode);
7819 config->mode_changed = true;
7820 }
7821}
7822
2e431051 7823static int
9a935856
DV		 7824intel_modeset_stage_output_state(struct drm_device *dev,
7825 struct drm_mode_set *set,
7826 struct intel_set_config *config)
50f56119 7827{
85f9eb71 7828 struct drm_crtc *new_crtc;
9a935856
DV		 7829 struct intel_connector *connector;
7830 struct intel_encoder *encoder;
2e431051 7831 int count, ro;
50f56119 7832
9a935856
DV		 7833 /* The upper layers ensure that we either disabl a crtc or have a list
7834 * of connectors. For paranoia, double-check this. */
7835 WARN_ON(!set->fb && (set->num_connectors != 0));
7836 WARN_ON(set->fb && (set->num_connectors == 0));
7837
50f56119 7838 count = 0;
9a935856
DV		 7839 list_for_each_entry(connector, &dev->mode_config.connector_list,
7840 base.head) {
7841 /* Otherwise traverse passed in connector list and get encoders
7842 * for them. */
50f56119 7843 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 7844 if (set->connectors[ro] == &connector->base) {
7845 connector->new_encoder = connector->encoder;
50f56119
DV		 7846 break;
7847 }
7848 }
7849
9a935856
DV		 7850 /* If we disable the crtc, disable all its connectors. Also, if
7851 * the connector is on the changing crtc but not on the new
7852 * connector list, disable it. */
7853 if ((!set->fb || ro == set->num_connectors) &&
7854 connector->base.encoder &&
7855 connector->base.encoder->crtc == set->crtc) {
7856 connector->new_encoder = NULL;
7857
7858 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7859 connector->base.base.id,
7860 drm_get_connector_name(&connector->base));
7861 }
7862
7863
7864 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 7865 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 7866 config->mode_changed = true;
50f56119
DV		 7867 }
7868 }
9a935856 7869 /* connector->new_encoder is now updated for all connectors. */
50f56119 7870
9a935856 7871 /* Update crtc of enabled connectors. */
50f56119 7872 count = 0;
9a935856
DV		 7873 list_for_each_entry(connector, &dev->mode_config.connector_list,
7874 base.head) {
7875 if (!connector->new_encoder)
50f56119
DV		 7876 continue;
7877
9a935856 7878 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 7879
7880 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 7881 if (set->connectors[ro] == &connector->base)
50f56119
DV		 7882 new_crtc = set->crtc;
7883 }
7884
7885 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 7886 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7887 new_crtc)) {
5e2b584e 7888 return -EINVAL;
50f56119 7889 }
9a935856
DV		 7890 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7891
7892 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7893 connector->base.base.id,
7894 drm_get_connector_name(&connector->base),
7895 new_crtc->base.id);
7896 }
7897
7898 /* Check for any encoders that needs to be disabled. */
7899 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7900 base.head) {
7901 list_for_each_entry(connector,
7902 &dev->mode_config.connector_list,
7903 base.head) {
7904 if (connector->new_encoder == encoder) {
7905 WARN_ON(!connector->new_encoder->new_crtc);
7906
7907 goto next_encoder;
7908 }
7909 }
7910 encoder->new_crtc = NULL;
7911next_encoder:
7912 /* Only now check for crtc changes so we don't miss encoders
7913 * that will be disabled. */
7914 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 7915 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 7916 config->mode_changed = true;
50f56119
DV		 7917 }
7918 }
9a935856 7919 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 7920
2e431051
DV		 7921 return 0;
7922}
7923
7924static int intel_crtc_set_config(struct drm_mode_set *set)
7925{
7926 struct drm_device *dev;
2e431051
DV		 7927 struct drm_mode_set save_set;
7928 struct intel_set_config *config;
7929 int ret;
2e431051 7930
8d3e375e
DV		 7931 BUG_ON(!set);
7932 BUG_ON(!set->crtc);
7933 BUG_ON(!set->crtc->helper_private);
2e431051
DV		 7934
7935 if (!set->mode)
7936 set->fb = NULL;
7937
431e50f7
DV		 7938 /* The fb helper likes to play gross jokes with ->mode_set_config.
7939 * Unfortunately the crtc helper doesn't do much at all for this case,
7940 * so we have to cope with this madness until the fb helper is fixed up. */
7941 if (set->fb && set->num_connectors == 0)
7942 return 0;
7943
2e431051
DV		 7944 if (set->fb) {
7945 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
7946 set->crtc->base.id, set->fb->base.id,
7947 (int)set->num_connectors, set->x, set->y);
7948 } else {
7949 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 7950 }
7951
7952 dev = set->crtc->dev;
7953
7954 ret = -ENOMEM;
7955 config = kzalloc(sizeof(*config), GFP_KERNEL);
7956 if (!config)
7957 goto out_config;
7958
7959 ret = intel_set_config_save_state(dev, config);
7960 if (ret)
7961 goto out_config;
7962
7963 save_set.crtc = set->crtc;
7964 save_set.mode = &set->crtc->mode;
7965 save_set.x = set->crtc->x;
7966 save_set.y = set->crtc->y;
7967 save_set.fb = set->crtc->fb;
7968
7969 /* Compute whether we need a full modeset, only an fb base update or no
7970 * change at all. In the future we might also check whether only the
7971 * mode changed, e.g. for LVDS where we only change the panel fitter in
7972 * such cases. */
7973 intel_set_config_compute_mode_changes(set, config);
7974
9a935856 7975 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 7976 if (ret)
7977 goto fail;
7978
5e2b584e 7979 if (config->mode_changed) {
87f1faa6 7980 if (set->mode) {
50f56119
DV		 7981 DRM_DEBUG_KMS("attempting to set mode from"
7982 " userspace\n");
7983 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 7984 }
7985
c0c36b94
CW		 7986 ret = intel_set_mode(set->crtc, set->mode,
7987 set->x, set->y, set->fb);
7988 if (ret) {
7989 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
7990 set->crtc->base.id, ret);
87f1faa6
DV		 7991 goto fail;
7992 }
5e2b584e 7993 } else if (config->fb_changed) {
4f660f49 7994 ret = intel_pipe_set_base(set->crtc,
94352cf9 7995 set->x, set->y, set->fb);
50f56119
DV		 7996 }
7997
d9e55608
DV		 7998 intel_set_config_free(config);
7999
50f56119
DV		 8000 return 0;
8001
8002fail:
85f9eb71 8003 intel_set_config_restore_state(dev, config);
50f56119
DV		 8004
8005 /* Try to restore the config */
5e2b584e 8006 if (config->mode_changed &&
c0c36b94
CW		 8007 intel_set_mode(save_set.crtc, save_set.mode,
8008 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8009 DRM_ERROR("failed to restore config after modeset failure\n");
8010
d9e55608
DV		 8011out_config:
8012 intel_set_config_free(config);
50f56119
DV		 8013 return ret;
8014}
f6e5b160
CW		 8015
8016static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8017 .cursor_set = intel_crtc_cursor_set,
8018 .cursor_move = intel_crtc_cursor_move,
8019 .gamma_set = intel_crtc_gamma_set,
50f56119 8020 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8021 .destroy = intel_crtc_destroy,
8022 .page_flip = intel_crtc_page_flip,
8023};
8024
79f689aa
PZ		 8025static void intel_cpu_pll_init(struct drm_device *dev)
8026{
affa9354 8027 if (HAS_DDI(dev))
79f689aa
PZ		 8028 intel_ddi_pll_init(dev);
8029}
8030
ee7b9f93
JB		 8031static void intel_pch_pll_init(struct drm_device *dev)
8032{
8033 drm_i915_private_t *dev_priv = dev->dev_private;
8034 int i;
8035
8036 if (dev_priv->num_pch_pll == 0) {
8037 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8038 return;
8039 }
8040
8041 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8042 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8043 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8044 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8045 }
8046}
8047
b358d0a6 8048static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8049{
22fd0fab 8050 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8051 struct intel_crtc *intel_crtc;
8052 int i;
8053
8054 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8055 if (intel_crtc == NULL)
8056 return;
8057
8058 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8059
8060 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8061 for (i = 0; i < 256; i++) {
8062 intel_crtc->lut_r[i] = i;
8063 intel_crtc->lut_g[i] = i;
8064 intel_crtc->lut_b[i] = i;
8065 }
8066
80824003
JB		 8067 /* Swap pipes & planes for FBC on pre-965 */
8068 intel_crtc->pipe = pipe;
8069 intel_crtc->plane = pipe;
a5c961d1 8070 intel_crtc->cpu_transcoder = pipe;
e2e767ab 8071 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8072 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8073 intel_crtc->plane = !pipe;
80824003
JB		 8074 }
8075
22fd0fab
JB		 8076 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8077 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8078 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8079 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8080
5a354204 8081 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3 8082
79e53945 8083 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8084}
8085
08d7b3d1 8086int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8087 struct drm_file *file)
08d7b3d1 8088{
08d7b3d1 8089 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8090 struct drm_mode_object *drmmode_obj;
8091 struct intel_crtc *crtc;
08d7b3d1 8092
1cff8f6b
DV		 8093 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8094 return -ENODEV;
08d7b3d1 8095
c05422d5
DV		 8096 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8097 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8098
c05422d5 8099 if (!drmmode_obj) {
08d7b3d1
CW		 8100 DRM_ERROR("no such CRTC id\n");
8101 return -EINVAL;
8102 }
8103
c05422d5
DV		 8104 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8105 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8106
c05422d5 8107 return 0;
08d7b3d1
CW		 8108}
8109
66a9278e 8110static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8111{
66a9278e
DV		 8112 struct drm_device *dev = encoder->base.dev;
8113 struct intel_encoder *source_encoder;
79e53945 8114 int index_mask = 0;
79e53945
JB		 8115 int entry = 0;
8116
66a9278e
DV		 8117 list_for_each_entry(source_encoder,
8118 &dev->mode_config.encoder_list, base.head) {
8119
8120 if (encoder == source_encoder)
79e53945 8121 index_mask |= (1 << entry);
66a9278e
DV		 8122
8123 /* Intel hw has only one MUX where enocoders could be cloned. */
8124 if (encoder->cloneable && source_encoder->cloneable)
8125 index_mask |= (1 << entry);
8126
79e53945
JB		 8127 entry++;
8128 }
4ef69c7a 8129
79e53945
JB		 8130 return index_mask;
8131}
8132
4d302442
CW		 8133static bool has_edp_a(struct drm_device *dev)
8134{
8135 struct drm_i915_private *dev_priv = dev->dev_private;
8136
8137 if (!IS_MOBILE(dev))
8138 return false;
8139
8140 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8141 return false;
8142
8143 if (IS_GEN5(dev) &&
8144 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8145 return false;
8146
8147 return true;
8148}
8149
79e53945
JB		 8150static void intel_setup_outputs(struct drm_device *dev)
8151{
725e30ad 8152 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8153 struct intel_encoder *encoder;
cb0953d7 8154 bool dpd_is_edp = false;
f3cfcba6 8155 bool has_lvds;
79e53945 8156
f3cfcba6 8157 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8158 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8159 /* disable the panel fitter on everything but LVDS */
8160 I915_WRITE(PFIT_CONTROL, 0);
8161 }
79e53945 8162
affa9354 8163 if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
79935fca 8164 intel_crt_init(dev);
cb0953d7 8165
affa9354 8166 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8167 int found;
8168
8169 /* Haswell uses DDI functions to detect digital outputs */
8170 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8171 /* DDI A only supports eDP */
8172 if (found)
8173 intel_ddi_init(dev, PORT_A);
8174
8175 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8176 * register */
8177 found = I915_READ(SFUSE_STRAP);
8178
8179 if (found & SFUSE_STRAP_DDIB_DETECTED)
8180 intel_ddi_init(dev, PORT_B);
8181 if (found & SFUSE_STRAP_DDIC_DETECTED)
8182 intel_ddi_init(dev, PORT_C);
8183 if (found & SFUSE_STRAP_DDID_DETECTED)
8184 intel_ddi_init(dev, PORT_D);
8185 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8186 int found;
270b3042
DV		 8187 dpd_is_edp = intel_dpd_is_edp(dev);
8188
8189 if (has_edp_a(dev))
8190 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8191
30ad48b7 8192 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca 8193 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8194 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8195 if (!found)
08d644ad 8196 intel_hdmi_init(dev, HDMIB, PORT_B);
5eb08b69 8197 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8198 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8199 }
8200
8201 if (I915_READ(HDMIC) & PORT_DETECTED)
08d644ad 8202 intel_hdmi_init(dev, HDMIC, PORT_C);
30ad48b7 8203
b708a1d5 8204 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
08d644ad 8205 intel_hdmi_init(dev, HDMID, PORT_D);
30ad48b7 8206
5eb08b69 8207 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8208 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8209
270b3042 8210 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8211 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d
JB		 8212 } else if (IS_VALLEYVIEW(dev)) {
8213 int found;
8214
19c03924
GB		 8215 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8216 if (I915_READ(DP_C) & DP_DETECTED)
8217 intel_dp_init(dev, DP_C, PORT_C);
8218
4a87d65d
JB		 8219 if (I915_READ(SDVOB) & PORT_DETECTED) {
8220 /* SDVOB multiplex with HDMIB */
8221 found = intel_sdvo_init(dev, SDVOB, true);
8222 if (!found)
08d644ad 8223 intel_hdmi_init(dev, SDVOB, PORT_B);
4a87d65d 8224 if (!found && (I915_READ(DP_B) & DP_DETECTED))
ab9d7c30 8225 intel_dp_init(dev, DP_B, PORT_B);
4a87d65d
JB		 8226 }
8227
8228 if (I915_READ(SDVOC) & PORT_DETECTED)
08d644ad 8229 intel_hdmi_init(dev, SDVOC, PORT_C);
5eb08b69 8230
103a196f 8231 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8232 bool found = false;
7d57382e 8233
725e30ad 8234 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 8235 DRM_DEBUG_KMS("probing SDVOB\n");
eef4eacb 8236 found = intel_sdvo_init(dev, SDVOB, true);
b01f2c3a
JB		 8237 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8238 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
08d644ad 8239 intel_hdmi_init(dev, SDVOB, PORT_B);
b01f2c3a 8240 }
27185ae1 8241
b01f2c3a
JB		 8242 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8243 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 8244 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 8245 }
725e30ad 8246 }
13520b05
KH		 8247
8248 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8249
b01f2c3a
JB		 8250 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8251 DRM_DEBUG_KMS("probing SDVOC\n");
eef4eacb 8252 found = intel_sdvo_init(dev, SDVOC, false);
b01f2c3a 8253 }
27185ae1
ML		 8254
8255 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8256
b01f2c3a
JB		 8257 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8258 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
08d644ad 8259 intel_hdmi_init(dev, SDVOC, PORT_C);
b01f2c3a
JB		 8260 }
8261 if (SUPPORTS_INTEGRATED_DP(dev)) {
8262 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 8263 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 8264 }
725e30ad 8265 }
27185ae1 8266
b01f2c3a
JB		 8267 if (SUPPORTS_INTEGRATED_DP(dev) &&
8268 (I915_READ(DP_D) & DP_DETECTED)) {
8269 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 8270 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 8271 }
bad720ff 8272 } else if (IS_GEN2(dev))
79e53945
JB		 8273 intel_dvo_init(dev);
8274
103a196f 8275 if (SUPPORTS_TV(dev))
79e53945
JB		 8276 intel_tv_init(dev);
8277
4ef69c7a
CW		 8278 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8279 encoder->base.possible_crtcs = encoder->crtc_mask;
8280 encoder->base.possible_clones =
66a9278e 8281 intel_encoder_clones(encoder);
79e53945 8282 }
47356eb6 8283
dde86e2d 8284 intel_init_pch_refclk(dev);
270b3042
DV		 8285
8286 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8287}
8288
8289static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8290{
8291 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8292
8293 drm_framebuffer_cleanup(fb);
05394f39 8294 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8295
8296 kfree(intel_fb);
8297}
8298
8299static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8300 struct drm_file *file,
79e53945
JB		 8301 unsigned int *handle)
8302{
8303 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8304 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8305
05394f39 8306 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8307}
8308
8309static const struct drm_framebuffer_funcs intel_fb_funcs = {
8310 .destroy = intel_user_framebuffer_destroy,
8311 .create_handle = intel_user_framebuffer_create_handle,
8312};
8313
38651674
DA		 8314int intel_framebuffer_init(struct drm_device *dev,
8315 struct intel_framebuffer *intel_fb,
308e5bcb 8316 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8317 struct drm_i915_gem_object *obj)
79e53945 8318{
79e53945
JB		 8319 int ret;
8320
05394f39 8321 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 8322 return -EINVAL;
8323
308e5bcb 8324 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 8325 return -EINVAL;
8326
5d7bd705
VS		 8327 /* FIXME <= Gen4 stride limits are bit unclear */
8328 if (mode_cmd->pitches[0] > 32768)
8329 return -EINVAL;
8330
8331 if (obj->tiling_mode != I915_TILING_NONE &&
8332 mode_cmd->pitches[0] != obj->stride)
8333 return -EINVAL;
8334
57779d06 8335 /* Reject formats not supported by any plane early. */
308e5bcb 8336 switch (mode_cmd->pixel_format) {
57779d06 8337 case DRM_FORMAT_C8:
04b3924d
VS		 8338 case DRM_FORMAT_RGB565:
8339 case DRM_FORMAT_XRGB8888:
8340 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8341 break;
8342 case DRM_FORMAT_XRGB1555:
8343 case DRM_FORMAT_ARGB1555:
8344 if (INTEL_INFO(dev)->gen > 3)
8345 return -EINVAL;
8346 break;
8347 case DRM_FORMAT_XBGR8888:
8348 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8349 case DRM_FORMAT_XRGB2101010:
8350 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8351 case DRM_FORMAT_XBGR2101010:
8352 case DRM_FORMAT_ABGR2101010:
8353 if (INTEL_INFO(dev)->gen < 4)
8354 return -EINVAL;
b5626747 8355 break;
04b3924d
VS		 8356 case DRM_FORMAT_YUYV:
8357 case DRM_FORMAT_UYVY:
8358 case DRM_FORMAT_YVYU:
8359 case DRM_FORMAT_VYUY:
57779d06
VS		 8360 if (INTEL_INFO(dev)->gen < 6)
8361 return -EINVAL;
57cd6508
CW		 8362 break;
8363 default:
57779d06 8364 DRM_DEBUG_KMS("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8365 return -EINVAL;
8366 }
8367
90f9a336
VS		 8368 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8369 if (mode_cmd->offsets[0] != 0)
8370 return -EINVAL;
8371
79e53945
JB		 8372 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8373 if (ret) {
8374 DRM_ERROR("framebuffer init failed %d\n", ret);
8375 return ret;
8376 }
8377
8378 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 8379 intel_fb->obj = obj;
79e53945
JB		 8380 return 0;
8381}
8382
79e53945
JB		 8383static struct drm_framebuffer *
8384intel_user_framebuffer_create(struct drm_device *dev,
8385 struct drm_file *filp,
308e5bcb 8386 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8387{
05394f39 8388 struct drm_i915_gem_object *obj;
79e53945 8389
308e5bcb
JB		 8390 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8391 mode_cmd->handles[0]));
c8725226 8392 if (&obj->base == NULL)
cce13ff7 8393 return ERR_PTR(-ENOENT);
79e53945 8394
d2dff872 8395 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8396}
8397
79e53945 8398static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8399 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8400 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8401};
8402
e70236a8
JB		 8403/* Set up chip specific display functions */
8404static void intel_init_display(struct drm_device *dev)
8405{
8406 struct drm_i915_private *dev_priv = dev->dev_private;
8407
8408 /* We always want a DPMS function */
affa9354 8409 if (HAS_DDI(dev)) {
09b4ddf9 8410 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8411 dev_priv->display.crtc_enable = haswell_crtc_enable;
8412 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 8413 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 8414 dev_priv->display.update_plane = ironlake_update_plane;
8415 } else if (HAS_PCH_SPLIT(dev)) {
f564048e 8416 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 8417 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8418 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8419 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8420 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8421 } else {
f564048e 8422 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 8423 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8424 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8425 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8426 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8427 }
e70236a8 8428
e70236a8 8429 /* Returns the core display clock speed */
25eb05fc
JB		 8430 if (IS_VALLEYVIEW(dev))
8431 dev_priv->display.get_display_clock_speed =
8432 valleyview_get_display_clock_speed;
8433 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8434 dev_priv->display.get_display_clock_speed =
8435 i945_get_display_clock_speed;
8436 else if (IS_I915G(dev))
8437 dev_priv->display.get_display_clock_speed =
8438 i915_get_display_clock_speed;
f2b115e6 8439 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8440 dev_priv->display.get_display_clock_speed =
8441 i9xx_misc_get_display_clock_speed;
8442 else if (IS_I915GM(dev))
8443 dev_priv->display.get_display_clock_speed =
8444 i915gm_get_display_clock_speed;
8445 else if (IS_I865G(dev))
8446 dev_priv->display.get_display_clock_speed =
8447 i865_get_display_clock_speed;
f0f8a9ce 8448 else if (IS_I85X(dev))
e70236a8
JB		 8449 dev_priv->display.get_display_clock_speed =
8450 i855_get_display_clock_speed;
8451 else /* 852, 830 */
8452 dev_priv->display.get_display_clock_speed =
8453 i830_get_display_clock_speed;
8454
7f8a8569 8455 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8456 if (IS_GEN5(dev)) {
674cf967 8457 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8458 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8459 } else if (IS_GEN6(dev)) {
674cf967 8460 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8461 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8462 } else if (IS_IVYBRIDGE(dev)) {
8463 /* FIXME: detect B0+ stepping and use auto training */
8464 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 8465 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 8466 dev_priv->display.modeset_global_resources =
8467 ivb_modeset_global_resources;
c82e4d26
ED		 8468 } else if (IS_HASWELL(dev)) {
8469 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 8470 dev_priv->display.write_eld = haswell_write_eld;
a0e63c22 8471 }
6067aaea 8472 } else if (IS_G4X(dev)) {
e0dac65e 8473 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8474 }
8c9f3aaf
JB		 8475
8476 /* Default just returns -ENODEV to indicate unsupported */
8477 dev_priv->display.queue_flip = intel_default_queue_flip;
8478
8479 switch (INTEL_INFO(dev)->gen) {
8480 case 2:
8481 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8482 break;
8483
8484 case 3:
8485 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8486 break;
8487
8488 case 4:
8489 case 5:
8490 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8491 break;
8492
8493 case 6:
8494 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8495 break;
7c9017e5
JB		 8496 case 7:
8497 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8498 break;
8c9f3aaf 8499 }
e70236a8
JB		 8500}
8501
b690e96c
JB		 8502/*
8503 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8504 * resume, or other times. This quirk makes sure that's the case for
8505 * affected systems.
8506 */
0206e353 8507static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8508{
8509 struct drm_i915_private *dev_priv = dev->dev_private;
8510
8511 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 8512 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 8513}
8514
435793df
KP		 8515/*
8516 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8517 */
8518static void quirk_ssc_force_disable(struct drm_device *dev)
8519{
8520 struct drm_i915_private *dev_priv = dev->dev_private;
8521 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 8522 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 8523}
8524
4dca20ef 8525/*
5a15ab5b
CE		 8526 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8527 * brightness value
4dca20ef
CE		 8528 */
8529static void quirk_invert_brightness(struct drm_device *dev)
8530{
8531 struct drm_i915_private *dev_priv = dev->dev_private;
8532 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 8533 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 8534}
8535
b690e96c
JB		 8536struct intel_quirk {
8537 int device;
8538 int subsystem_vendor;
8539 int subsystem_device;
8540 void (*hook)(struct drm_device *dev);
8541};
8542
5f85f176
EE		 8543/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8544struct intel_dmi_quirk {
8545 void (*hook)(struct drm_device *dev);
8546 const struct dmi_system_id (*dmi_id_list)[];
8547};
8548
8549static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8550{
8551 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8552 return 1;
8553}
8554
8555static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8556 {
8557 .dmi_id_list = &(const struct dmi_system_id[]) {
8558 {
8559 .callback = intel_dmi_reverse_brightness,
8560 .ident = "NCR Corporation",
8561 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8562 DMI_MATCH(DMI_PRODUCT_NAME, ""),
8563 },
8564 },
8565 { } /* terminating entry */
8566 },
8567 .hook = quirk_invert_brightness,
8568 },
8569};
8570
c43b5634 8571static struct intel_quirk intel_quirks[] = {
b690e96c 8572 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8573 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 8574
b690e96c
JB		 8575 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8576 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8577
b690e96c
JB		 8578 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8579 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8580
ccd0d36e 8581 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 8582 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 8583 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 8584
8585 /* Lenovo U160 cannot use SSC on LVDS */
8586 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 8587
8588 /* Sony Vaio Y cannot use SSC on LVDS */
8589 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 8590
8591 /* Acer Aspire 5734Z must invert backlight brightness */
8592 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
b690e96c
JB		 8593};
8594
8595static void intel_init_quirks(struct drm_device *dev)
8596{
8597 struct pci_dev *d = dev->pdev;
8598 int i;
8599
8600 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8601 struct intel_quirk *q = &intel_quirks[i];
8602
8603 if (d->device == q->device &&
8604 (d->subsystem_vendor == q->subsystem_vendor ||
8605 q->subsystem_vendor == PCI_ANY_ID) &&
8606 (d->subsystem_device == q->subsystem_device ||
8607 q->subsystem_device == PCI_ANY_ID))
8608 q->hook(dev);
8609 }
5f85f176
EE		 8610 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8611 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8612 intel_dmi_quirks[i].hook(dev);
8613 }
b690e96c
JB		 8614}
8615
9cce37f4
JB		 8616/* Disable the VGA plane that we never use */
8617static void i915_disable_vga(struct drm_device *dev)
8618{
8619 struct drm_i915_private *dev_priv = dev->dev_private;
8620 u8 sr1;
8621 u32 vga_reg;
8622
8623 if (HAS_PCH_SPLIT(dev))
8624 vga_reg = CPU_VGACNTRL;
8625 else
8626 vga_reg = VGACNTRL;
8627
8628 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 8629 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 8630 sr1 = inb(VGA_SR_DATA);
8631 outb(sr1 | 1<<5, VGA_SR_DATA);
8632 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8633 udelay(300);
8634
8635 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8636 POSTING_READ(vga_reg);
8637}
8638
f817586c
DV		 8639void intel_modeset_init_hw(struct drm_device *dev)
8640{
0232e927
ED		 8641 /* We attempt to init the necessary power wells early in the initialization
8642 * time, so the subsystems that expect power to be enabled can work.
8643 */
8644 intel_init_power_wells(dev);
8645
a8f78b58
ED		 8646 intel_prepare_ddi(dev);
8647
f817586c
DV		 8648 intel_init_clock_gating(dev);
8649
79f5b2c7 8650 mutex_lock(&dev->struct_mutex);
8090c6b9 8651 intel_enable_gt_powersave(dev);
79f5b2c7 8652 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 8653}
8654
79e53945
JB		 8655void intel_modeset_init(struct drm_device *dev)
8656{
652c393a 8657 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 8658 int i, ret;
79e53945
JB		 8659
8660 drm_mode_config_init(dev);
8661
8662 dev->mode_config.min_width = 0;
8663 dev->mode_config.min_height = 0;
8664
019d96cb
DA		 8665 dev->mode_config.preferred_depth = 24;
8666 dev->mode_config.prefer_shadow = 1;
8667
e6ecefaa 8668 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 8669
b690e96c
JB		 8670 intel_init_quirks(dev);
8671
1fa61106
ED		 8672 intel_init_pm(dev);
8673
e70236a8
JB		 8674 intel_init_display(dev);
8675
a6c45cf0
CW		 8676 if (IS_GEN2(dev)) {
8677 dev->mode_config.max_width = 2048;
8678 dev->mode_config.max_height = 2048;
8679 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 8680 dev->mode_config.max_width = 4096;
8681 dev->mode_config.max_height = 4096;
79e53945 8682 } else {
a6c45cf0
CW		 8683 dev->mode_config.max_width = 8192;
8684 dev->mode_config.max_height = 8192;
79e53945 8685 }
dd2757f8 8686 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
79e53945 8687
28c97730 8688 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 8689 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 8690
a3524f1b 8691 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 8692 intel_crtc_init(dev, i);
00c2064b
JB		 8693 ret = intel_plane_init(dev, i);
8694 if (ret)
8695 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 8696 }
8697
79f689aa 8698 intel_cpu_pll_init(dev);
ee7b9f93
JB		 8699 intel_pch_pll_init(dev);
8700
9cce37f4
JB		 8701 /* Just disable it once at startup */
8702 i915_disable_vga(dev);
79e53945 8703 intel_setup_outputs(dev);
11be49eb
CW		 8704
8705 /* Just in case the BIOS is doing something questionable. */
8706 intel_disable_fbc(dev);
2c7111db
CW		 8707}
8708
24929352
DV		 8709static void
8710intel_connector_break_all_links(struct intel_connector *connector)
8711{
8712 connector->base.dpms = DRM_MODE_DPMS_OFF;
8713 connector->base.encoder = NULL;
8714 connector->encoder->connectors_active = false;
8715 connector->encoder->base.crtc = NULL;
8716}
8717
7fad798e
DV		 8718static void intel_enable_pipe_a(struct drm_device *dev)
8719{
8720 struct intel_connector *connector;
8721 struct drm_connector *crt = NULL;
8722 struct intel_load_detect_pipe load_detect_temp;
8723
8724 /* We can't just switch on the pipe A, we need to set things up with a
8725 * proper mode and output configuration. As a gross hack, enable pipe A
8726 * by enabling the load detect pipe once. */
8727 list_for_each_entry(connector,
8728 &dev->mode_config.connector_list,
8729 base.head) {
8730 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8731 crt = &connector->base;
8732 break;
8733 }
8734 }
8735
8736 if (!crt)
8737 return;
8738
8739 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8740 intel_release_load_detect_pipe(crt, &load_detect_temp);
8741
652c393a 8742
7fad798e
DV		 8743}
8744
fa555837
DV		 8745static bool
8746intel_check_plane_mapping(struct intel_crtc *crtc)
8747{
8748 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8749 u32 reg, val;
8750
8751 if (dev_priv->num_pipe == 1)
8752 return true;
8753
8754 reg = DSPCNTR(!crtc->plane);
8755 val = I915_READ(reg);
8756
8757 if ((val & DISPLAY_PLANE_ENABLE) &&
8758 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8759 return false;
8760
8761 return true;
8762}
8763
24929352
DV		 8764static void intel_sanitize_crtc(struct intel_crtc *crtc)
8765{
8766 struct drm_device *dev = crtc->base.dev;
8767 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 8768 u32 reg;
24929352 8769
24929352 8770 /* Clear any frame start delays used for debugging left by the BIOS */
702e7a56 8771 reg = PIPECONF(crtc->cpu_transcoder);
24929352
DV		 8772 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8773
8774 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 8775 * disable the crtc (and hence change the state) if it is wrong. Note
8776 * that gen4+ has a fixed plane -> pipe mapping. */
8777 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 8778 struct intel_connector *connector;
8779 bool plane;
8780
24929352
DV		 8781 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8782 crtc->base.base.id);
8783
8784 /* Pipe has the wrong plane attached and the plane is active.
8785 * Temporarily change the plane mapping and disable everything
8786 * ... */
8787 plane = crtc->plane;
8788 crtc->plane = !plane;
8789 dev_priv->display.crtc_disable(&crtc->base);
8790 crtc->plane = plane;
8791
8792 /* ... and break all links. */
8793 list_for_each_entry(connector, &dev->mode_config.connector_list,
8794 base.head) {
8795 if (connector->encoder->base.crtc != &crtc->base)
8796 continue;
8797
8798 intel_connector_break_all_links(connector);
8799 }
8800
8801 WARN_ON(crtc->active);
8802 crtc->base.enabled = false;
8803 }
24929352 8804
7fad798e
DV		 8805 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8806 crtc->pipe == PIPE_A && !crtc->active) {
8807 /* BIOS forgot to enable pipe A, this mostly happens after
8808 * resume. Force-enable the pipe to fix this, the update_dpms
8809 * call below we restore the pipe to the right state, but leave
8810 * the required bits on. */
8811 intel_enable_pipe_a(dev);
8812 }
8813
24929352
DV		 8814 /* Adjust the state of the output pipe according to whether we
8815 * have active connectors/encoders. */
8816 intel_crtc_update_dpms(&crtc->base);
8817
8818 if (crtc->active != crtc->base.enabled) {
8819 struct intel_encoder *encoder;
8820
8821 /* This can happen either due to bugs in the get_hw_state
8822 * functions or because the pipe is force-enabled due to the
8823 * pipe A quirk. */
8824 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8825 crtc->base.base.id,
8826 crtc->base.enabled ? "enabled" : "disabled",
8827 crtc->active ? "enabled" : "disabled");
8828
8829 crtc->base.enabled = crtc->active;
8830
8831 /* Because we only establish the connector -> encoder ->
8832 * crtc links if something is active, this means the
8833 * crtc is now deactivated. Break the links. connector
8834 * -> encoder links are only establish when things are
8835 * actually up, hence no need to break them. */
8836 WARN_ON(crtc->active);
8837
8838 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8839 WARN_ON(encoder->connectors_active);
8840 encoder->base.crtc = NULL;
8841 }
8842 }
8843}
8844
8845static void intel_sanitize_encoder(struct intel_encoder *encoder)
8846{
8847 struct intel_connector *connector;
8848 struct drm_device *dev = encoder->base.dev;
8849
8850 /* We need to check both for a crtc link (meaning that the
8851 * encoder is active and trying to read from a pipe) and the
8852 * pipe itself being active. */
8853 bool has_active_crtc = encoder->base.crtc &&
8854 to_intel_crtc(encoder->base.crtc)->active;
8855
8856 if (encoder->connectors_active && !has_active_crtc) {
8857 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8858 encoder->base.base.id,
8859 drm_get_encoder_name(&encoder->base));
8860
8861 /* Connector is active, but has no active pipe. This is
8862 * fallout from our resume register restoring. Disable
8863 * the encoder manually again. */
8864 if (encoder->base.crtc) {
8865 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8866 encoder->base.base.id,
8867 drm_get_encoder_name(&encoder->base));
8868 encoder->disable(encoder);
8869 }
8870
8871 /* Inconsistent output/port/pipe state happens presumably due to
8872 * a bug in one of the get_hw_state functions. Or someplace else
8873 * in our code, like the register restore mess on resume. Clamp
8874 * things to off as a safer default. */
8875 list_for_each_entry(connector,
8876 &dev->mode_config.connector_list,
8877 base.head) {
8878 if (connector->encoder != encoder)
8879 continue;
8880
8881 intel_connector_break_all_links(connector);
8882 }
8883 }
8884 /* Enabled encoders without active connectors will be fixed in
8885 * the crtc fixup. */
8886}
8887
0fde901f
KM		 8888static void i915_redisable_vga(struct drm_device *dev)
8889{
8890 struct drm_i915_private *dev_priv = dev->dev_private;
8891 u32 vga_reg;
8892
8893 if (HAS_PCH_SPLIT(dev))
8894 vga_reg = CPU_VGACNTRL;
8895 else
8896 vga_reg = VGACNTRL;
8897
8898 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
8899 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
8900 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8901 POSTING_READ(vga_reg);
8902 }
8903}
8904
24929352
DV		 8905/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8906 * and i915 state tracking structures. */
45e2b5f6
DV		 8907void intel_modeset_setup_hw_state(struct drm_device *dev,
8908 bool force_restore)
24929352
DV		 8909{
8910 struct drm_i915_private *dev_priv = dev->dev_private;
8911 enum pipe pipe;
8912 u32 tmp;
8913 struct intel_crtc *crtc;
8914 struct intel_encoder *encoder;
8915 struct intel_connector *connector;
8916
affa9354 8917 if (HAS_DDI(dev)) {
e28d54cb
PZ		 8918 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8919
8920 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8921 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8922 case TRANS_DDI_EDP_INPUT_A_ON:
8923 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8924 pipe = PIPE_A;
8925 break;
8926 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8927 pipe = PIPE_B;
8928 break;
8929 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8930 pipe = PIPE_C;
8931 break;
8932 }
8933
8934 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8935 crtc->cpu_transcoder = TRANSCODER_EDP;
8936
8937 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
8938 pipe_name(pipe));
8939 }
8940 }
8941
24929352
DV		 8942 for_each_pipe(pipe) {
8943 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8944
702e7a56 8945 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
24929352
DV		 8946 if (tmp & PIPECONF_ENABLE)
8947 crtc->active = true;
8948 else
8949 crtc->active = false;
8950
8951 crtc->base.enabled = crtc->active;
8952
8953 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
8954 crtc->base.base.id,
8955 crtc->active ? "enabled" : "disabled");
8956 }
8957
affa9354 8958 if (HAS_DDI(dev))
6441ab5f
PZ		 8959 intel_ddi_setup_hw_pll_state(dev);
8960
24929352
DV		 8961 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8962 base.head) {
8963 pipe = 0;
8964
8965 if (encoder->get_hw_state(encoder, &pipe)) {
8966 encoder->base.crtc =
8967 dev_priv->pipe_to_crtc_mapping[pipe];
8968 } else {
8969 encoder->base.crtc = NULL;
8970 }
8971
8972 encoder->connectors_active = false;
8973 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
8974 encoder->base.base.id,
8975 drm_get_encoder_name(&encoder->base),
8976 encoder->base.crtc ? "enabled" : "disabled",
8977 pipe);
8978 }
8979
8980 list_for_each_entry(connector, &dev->mode_config.connector_list,
8981 base.head) {
8982 if (connector->get_hw_state(connector)) {
8983 connector->base.dpms = DRM_MODE_DPMS_ON;
8984 connector->encoder->connectors_active = true;
8985 connector->base.encoder = &connector->encoder->base;
8986 } else {
8987 connector->base.dpms = DRM_MODE_DPMS_OFF;
8988 connector->base.encoder = NULL;
8989 }
8990 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
8991 connector->base.base.id,
8992 drm_get_connector_name(&connector->base),
8993 connector->base.encoder ? "enabled" : "disabled");
8994 }
8995
8996 /* HW state is read out, now we need to sanitize this mess. */
8997 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8998 base.head) {
8999 intel_sanitize_encoder(encoder);
9000 }
9001
9002 for_each_pipe(pipe) {
9003 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9004 intel_sanitize_crtc(crtc);
9005 }
9a935856 9006
45e2b5f6
DV		 9007 if (force_restore) {
9008 for_each_pipe(pipe) {
c0c36b94 9009 intel_crtc_restore_mode(dev_priv->pipe_to_crtc_mapping[pipe]);
45e2b5f6 9010 }
0fde901f
KM		 9011
9012 i915_redisable_vga(dev);
45e2b5f6
DV		 9013 } else {
9014 intel_modeset_update_staged_output_state(dev);
9015 }
8af6cf88
DV		 9016
9017 intel_modeset_check_state(dev);
2e938892
DV		 9018
9019 drm_mode_config_reset(dev);
2c7111db
CW		 9020}
9021
9022void intel_modeset_gem_init(struct drm_device *dev)
9023{
1833b134 9024 intel_modeset_init_hw(dev);
02e792fb
DV		 9025
9026 intel_setup_overlay(dev);
24929352 9027
45e2b5f6 9028 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9029}
9030
9031void intel_modeset_cleanup(struct drm_device *dev)
9032{
652c393a
JB		 9033 struct drm_i915_private *dev_priv = dev->dev_private;
9034 struct drm_crtc *crtc;
9035 struct intel_crtc *intel_crtc;
9036
f87ea761 9037 drm_kms_helper_poll_fini(dev);
652c393a
JB		 9038 mutex_lock(&dev->struct_mutex);
9039
723bfd70
JB		 9040 intel_unregister_dsm_handler();
9041
9042
652c393a
JB		 9043 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9044 /* Skip inactive CRTCs */
9045 if (!crtc->fb)
9046 continue;
9047
9048 intel_crtc = to_intel_crtc(crtc);
3dec0095 9049 intel_increase_pllclock(crtc);
652c393a
JB		 9050 }
9051
973d04f9 9052 intel_disable_fbc(dev);
e70236a8 9053
8090c6b9 9054 intel_disable_gt_powersave(dev);
0cdab21f 9055
930ebb46
DV		 9056 ironlake_teardown_rc6(dev);
9057
57f350b6
JB		 9058 if (IS_VALLEYVIEW(dev))
9059 vlv_init_dpio(dev);
9060
69341a5e
KH		 9061 mutex_unlock(&dev->struct_mutex);
9062
6c0d9350
DV		 9063 /* Disable the irq before mode object teardown, for the irq might
9064 * enqueue unpin/hotplug work. */
9065 drm_irq_uninstall(dev);
9066 cancel_work_sync(&dev_priv->hotplug_work);
c6a828d3 9067 cancel_work_sync(&dev_priv->rps.work);
6c0d9350 9068
1630fe75
CW		 9069 /* flush any delayed tasks or pending work */
9070 flush_scheduled_work();
9071
79e53945 9072 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9073
9074 intel_cleanup_overlay(dev);
79e53945
JB		 9075}
9076
f1c79df3
ZW		 9077/*
9078 * Return which encoder is currently attached for connector.
9079 */
df0e9248 9080struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9081{
df0e9248
CW		 9082 return &intel_attached_encoder(connector)->base;
9083}
f1c79df3 9084
df0e9248
CW		 9085void intel_connector_attach_encoder(struct intel_connector *connector,
9086 struct intel_encoder *encoder)
9087{
9088 connector->encoder = encoder;
9089 drm_mode_connector_attach_encoder(&connector->base,
9090 &encoder->base);
79e53945 9091}
28d52043
DA		 9092
9093/*
9094 * set vga decode state - true == enable VGA decode
9095 */
9096int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9097{
9098 struct drm_i915_private *dev_priv = dev->dev_private;
9099 u16 gmch_ctrl;
9100
9101 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9102 if (state)
9103 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9104 else
9105 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9106 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9107 return 0;
9108}
c4a1d9e4
CW		 9109
9110#ifdef CONFIG_DEBUG_FS
9111#include <linux/seq_file.h>
9112
9113struct intel_display_error_state {
9114 struct intel_cursor_error_state {
9115 u32 control;
9116 u32 position;
9117 u32 base;
9118 u32 size;
52331309 9119 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9120
9121 struct intel_pipe_error_state {
9122 u32 conf;
9123 u32 source;
9124
9125 u32 htotal;
9126 u32 hblank;
9127 u32 hsync;
9128 u32 vtotal;
9129 u32 vblank;
9130 u32 vsync;
52331309 9131 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9132
9133 struct intel_plane_error_state {
9134 u32 control;
9135 u32 stride;
9136 u32 size;
9137 u32 pos;
9138 u32 addr;
9139 u32 surface;
9140 u32 tile_offset;
52331309 9141 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9142};
9143
9144struct intel_display_error_state *
9145intel_display_capture_error_state(struct drm_device *dev)
9146{
0206e353 9147 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9148 struct intel_display_error_state *error;
702e7a56 9149 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9150 int i;
9151
9152 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9153 if (error == NULL)
9154 return NULL;
9155
52331309 9156 for_each_pipe(i) {
702e7a56
PZ		 9157 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9158
c4a1d9e4
CW		 9159 error->cursor[i].control = I915_READ(CURCNTR(i));
9160 error->cursor[i].position = I915_READ(CURPOS(i));
9161 error->cursor[i].base = I915_READ(CURBASE(i));
9162
9163 error->plane[i].control = I915_READ(DSPCNTR(i));
9164 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9165 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 9166 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 9167 error->plane[i].addr = I915_READ(DSPADDR(i));
9168 if (INTEL_INFO(dev)->gen >= 4) {
9169 error->plane[i].surface = I915_READ(DSPSURF(i));
9170 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9171 }
9172
702e7a56 9173 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9174 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9175 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9176 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9177 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9178 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9179 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9180 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9181 }
9182
9183 return error;
9184}
9185
9186void
9187intel_display_print_error_state(struct seq_file *m,
9188 struct drm_device *dev,
9189 struct intel_display_error_state *error)
9190{
52331309 9191 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 9192 int i;
9193
52331309
DL		 9194 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9195 for_each_pipe(i) {
c4a1d9e4
CW		 9196 seq_printf(m, "Pipe [%d]:\n", i);
9197 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9198 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9199 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9200 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9201 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9202 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9203 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9204 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9205
9206 seq_printf(m, "Plane [%d]:\n", i);
9207 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9208 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9209 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9210 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9211 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9212 if (INTEL_INFO(dev)->gen >= 4) {
9213 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9214 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9215 }
9216
9217 seq_printf(m, "Cursor [%d]:\n", i);
9218 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9219 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9220 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9221 }
9222}
9223#endif
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