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drm/i915: Allow p1 divider 2 on VLV
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
3dec0095 44static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 45static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 46
f1f644dc
JB		 47static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
48 struct intel_crtc_config *pipe_config);
18442d08
VS		 49static void ironlake_pch_clock_get(struct intel_crtc *crtc,
50 struct intel_crtc_config *pipe_config);
f1f644dc 51
e7457a9a
DL		 52static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
53 int x, int y, struct drm_framebuffer *old_fb);
54
55
79e53945 56typedef struct {
0206e353 57 int min, max;
79e53945
JB		 58} intel_range_t;
59
60typedef struct {
0206e353
AJ		 61 int dot_limit;
62 int p2_slow, p2_fast;
79e53945
JB		 63} intel_p2_t;
64
d4906093
ML		 65typedef struct intel_limit intel_limit_t;
66struct intel_limit {
0206e353
AJ		 67 intel_range_t dot, vco, n, m, m1, m2, p, p1;
68 intel_p2_t p2;
d4906093 69};
79e53945 70
d2acd215
DV		 71int
72intel_pch_rawclk(struct drm_device *dev)
73{
74 struct drm_i915_private *dev_priv = dev->dev_private;
75
76 WARN_ON(!HAS_PCH_SPLIT(dev));
77
78 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
79}
80
021357ac
CW		 81static inline u32 /* units of 100MHz */
82intel_fdi_link_freq(struct drm_device *dev)
83{
8b99e68c
CW		 84 if (IS_GEN5(dev)) {
85 struct drm_i915_private *dev_priv = dev->dev_private;
86 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
87 } else
88 return 27;
021357ac
CW		 89}
90
5d536e28 91static const intel_limit_t intel_limits_i8xx_dac = {
0206e353
AJ		 92 .dot = { .min = 25000, .max = 350000 },
93 .vco = { .min = 930000, .max = 1400000 },
94 .n = { .min = 3, .max = 16 },
95 .m = { .min = 96, .max = 140 },
96 .m1 = { .min = 18, .max = 26 },
97 .m2 = { .min = 6, .max = 16 },
98 .p = { .min = 4, .max = 128 },
99 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 100 .p2 = { .dot_limit = 165000,
101 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 102};
103
5d536e28
DV		 104static const intel_limit_t intel_limits_i8xx_dvo = {
105 .dot = { .min = 25000, .max = 350000 },
106 .vco = { .min = 930000, .max = 1400000 },
107 .n = { .min = 3, .max = 16 },
108 .m = { .min = 96, .max = 140 },
109 .m1 = { .min = 18, .max = 26 },
110 .m2 = { .min = 6, .max = 16 },
111 .p = { .min = 4, .max = 128 },
112 .p1 = { .min = 2, .max = 33 },
113 .p2 = { .dot_limit = 165000,
114 .p2_slow = 4, .p2_fast = 4 },
115};
116
e4b36699 117static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 118 .dot = { .min = 25000, .max = 350000 },
119 .vco = { .min = 930000, .max = 1400000 },
120 .n = { .min = 3, .max = 16 },
121 .m = { .min = 96, .max = 140 },
122 .m1 = { .min = 18, .max = 26 },
123 .m2 = { .min = 6, .max = 16 },
124 .p = { .min = 4, .max = 128 },
125 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 126 .p2 = { .dot_limit = 165000,
127 .p2_slow = 14, .p2_fast = 7 },
e4b36699 128};
273e27ca 129
e4b36699 130static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 131 .dot = { .min = 20000, .max = 400000 },
132 .vco = { .min = 1400000, .max = 2800000 },
133 .n = { .min = 1, .max = 6 },
134 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 135 .m1 = { .min = 8, .max = 18 },
136 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 137 .p = { .min = 5, .max = 80 },
138 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 139 .p2 = { .dot_limit = 200000,
140 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 141};
142
143static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 144 .dot = { .min = 20000, .max = 400000 },
145 .vco = { .min = 1400000, .max = 2800000 },
146 .n = { .min = 1, .max = 6 },
147 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 148 .m1 = { .min = 8, .max = 18 },
149 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 150 .p = { .min = 7, .max = 98 },
151 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 152 .p2 = { .dot_limit = 112000,
153 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 154};
155
273e27ca 156
e4b36699 157static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 158 .dot = { .min = 25000, .max = 270000 },
159 .vco = { .min = 1750000, .max = 3500000},
160 .n = { .min = 1, .max = 4 },
161 .m = { .min = 104, .max = 138 },
162 .m1 = { .min = 17, .max = 23 },
163 .m2 = { .min = 5, .max = 11 },
164 .p = { .min = 10, .max = 30 },
165 .p1 = { .min = 1, .max = 3},
166 .p2 = { .dot_limit = 270000,
167 .p2_slow = 10,
168 .p2_fast = 10
044c7c41 169 },
e4b36699
KP		 170};
171
172static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 173 .dot = { .min = 22000, .max = 400000 },
174 .vco = { .min = 1750000, .max = 3500000},
175 .n = { .min = 1, .max = 4 },
176 .m = { .min = 104, .max = 138 },
177 .m1 = { .min = 16, .max = 23 },
178 .m2 = { .min = 5, .max = 11 },
179 .p = { .min = 5, .max = 80 },
180 .p1 = { .min = 1, .max = 8},
181 .p2 = { .dot_limit = 165000,
182 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 183};
184
185static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 186 .dot = { .min = 20000, .max = 115000 },
187 .vco = { .min = 1750000, .max = 3500000 },
188 .n = { .min = 1, .max = 3 },
189 .m = { .min = 104, .max = 138 },
190 .m1 = { .min = 17, .max = 23 },
191 .m2 = { .min = 5, .max = 11 },
192 .p = { .min = 28, .max = 112 },
193 .p1 = { .min = 2, .max = 8 },
194 .p2 = { .dot_limit = 0,
195 .p2_slow = 14, .p2_fast = 14
044c7c41 196 },
e4b36699
KP		 197};
198
199static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 200 .dot = { .min = 80000, .max = 224000 },
201 .vco = { .min = 1750000, .max = 3500000 },
202 .n = { .min = 1, .max = 3 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 17, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 14, .max = 42 },
207 .p1 = { .min = 2, .max = 6 },
208 .p2 = { .dot_limit = 0,
209 .p2_slow = 7, .p2_fast = 7
044c7c41 210 },
e4b36699
KP		 211};
212
f2b115e6 213static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 214 .dot = { .min = 20000, .max = 400000},
215 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 216 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 217 .n = { .min = 3, .max = 6 },
218 .m = { .min = 2, .max = 256 },
273e27ca 219 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 220 .m1 = { .min = 0, .max = 0 },
221 .m2 = { .min = 0, .max = 254 },
222 .p = { .min = 5, .max = 80 },
223 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 224 .p2 = { .dot_limit = 200000,
225 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 226};
227
f2b115e6 228static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 229 .dot = { .min = 20000, .max = 400000 },
230 .vco = { .min = 1700000, .max = 3500000 },
231 .n = { .min = 3, .max = 6 },
232 .m = { .min = 2, .max = 256 },
233 .m1 = { .min = 0, .max = 0 },
234 .m2 = { .min = 0, .max = 254 },
235 .p = { .min = 7, .max = 112 },
236 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 237 .p2 = { .dot_limit = 112000,
238 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 239};
240
273e27ca
EA		 241/* Ironlake / Sandybridge
242 *
243 * We calculate clock using (register_value + 2) for N/M1/M2, so here
244 * the range value for them is (actual_value - 2).
245 */
b91ad0ec 246static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 247 .dot = { .min = 25000, .max = 350000 },
248 .vco = { .min = 1760000, .max = 3510000 },
249 .n = { .min = 1, .max = 5 },
250 .m = { .min = 79, .max = 127 },
251 .m1 = { .min = 12, .max = 22 },
252 .m2 = { .min = 5, .max = 9 },
253 .p = { .min = 5, .max = 80 },
254 .p1 = { .min = 1, .max = 8 },
255 .p2 = { .dot_limit = 225000,
256 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 257};
258
b91ad0ec 259static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 260 .dot = { .min = 25000, .max = 350000 },
261 .vco = { .min = 1760000, .max = 3510000 },
262 .n = { .min = 1, .max = 3 },
263 .m = { .min = 79, .max = 118 },
264 .m1 = { .min = 12, .max = 22 },
265 .m2 = { .min = 5, .max = 9 },
266 .p = { .min = 28, .max = 112 },
267 .p1 = { .min = 2, .max = 8 },
268 .p2 = { .dot_limit = 225000,
269 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 270};
271
272static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 273 .dot = { .min = 25000, .max = 350000 },
274 .vco = { .min = 1760000, .max = 3510000 },
275 .n = { .min = 1, .max = 3 },
276 .m = { .min = 79, .max = 127 },
277 .m1 = { .min = 12, .max = 22 },
278 .m2 = { .min = 5, .max = 9 },
279 .p = { .min = 14, .max = 56 },
280 .p1 = { .min = 2, .max = 8 },
281 .p2 = { .dot_limit = 225000,
282 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 283};
284
273e27ca 285/* LVDS 100mhz refclk limits. */
b91ad0ec 286static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 287 .dot = { .min = 25000, .max = 350000 },
288 .vco = { .min = 1760000, .max = 3510000 },
289 .n = { .min = 1, .max = 2 },
290 .m = { .min = 79, .max = 126 },
291 .m1 = { .min = 12, .max = 22 },
292 .m2 = { .min = 5, .max = 9 },
293 .p = { .min = 28, .max = 112 },
0206e353 294 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 295 .p2 = { .dot_limit = 225000,
296 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 297};
298
299static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 300 .dot = { .min = 25000, .max = 350000 },
301 .vco = { .min = 1760000, .max = 3510000 },
302 .n = { .min = 1, .max = 3 },
303 .m = { .min = 79, .max = 126 },
304 .m1 = { .min = 12, .max = 22 },
305 .m2 = { .min = 5, .max = 9 },
306 .p = { .min = 14, .max = 42 },
0206e353 307 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 308 .p2 = { .dot_limit = 225000,
309 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 310};
311
a0c4da24
JB		 312static const intel_limit_t intel_limits_vlv_dac = {
313 .dot = { .min = 25000, .max = 270000 },
314 .vco = { .min = 4000000, .max = 6000000 },
315 .n = { .min = 1, .max = 7 },
316 .m = { .min = 22, .max = 450 }, /* guess */
317 .m1 = { .min = 2, .max = 3 },
318 .m2 = { .min = 11, .max = 156 },
319 .p = { .min = 10, .max = 30 },
811bbf05 320 .p1 = { .min = 2, .max = 3 },
a0c4da24
JB		 321 .p2 = { .dot_limit = 270000,
322 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 323};
324
325static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 326 .dot = { .min = 25000, .max = 270000 },
327 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 328 .n = { .min = 1, .max = 7 },
329 .m = { .min = 60, .max = 300 }, /* guess */
330 .m1 = { .min = 2, .max = 3 },
331 .m2 = { .min = 11, .max = 156 },
332 .p = { .min = 10, .max = 30 },
b99ab663 333 .p1 = { .min = 2, .max = 3 },
a0c4da24
JB		 334 .p2 = { .dot_limit = 270000,
335 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 336};
337
6b4bf1c4
VS		 338static void vlv_clock(int refclk, intel_clock_t *clock)
339{
340 clock->m = clock->m1 * clock->m2;
341 clock->p = clock->p1 * clock->p2;
342 clock->vco = refclk * clock->m / clock->n;
343 clock->dot = clock->vco / clock->p;
344}
345
e0638cdf
PZ		 346/**
347 * Returns whether any output on the specified pipe is of the specified type
348 */
349static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
350{
351 struct drm_device *dev = crtc->dev;
352 struct intel_encoder *encoder;
353
354 for_each_encoder_on_crtc(dev, crtc, encoder)
355 if (encoder->type == type)
356 return true;
357
358 return false;
359}
360
1b894b59
CW		 361static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
362 int refclk)
2c07245f 363{
b91ad0ec 364 struct drm_device *dev = crtc->dev;
2c07245f 365 const intel_limit_t *limit;
b91ad0ec
ZW		 366
367 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 368 if (intel_is_dual_link_lvds(dev)) {
1b894b59 369 if (refclk == 100000)
b91ad0ec
ZW		 370 limit = &intel_limits_ironlake_dual_lvds_100m;
371 else
372 limit = &intel_limits_ironlake_dual_lvds;
373 } else {
1b894b59 374 if (refclk == 100000)
b91ad0ec
ZW		 375 limit = &intel_limits_ironlake_single_lvds_100m;
376 else
377 limit = &intel_limits_ironlake_single_lvds;
378 }
c6bb3538 379 } else
b91ad0ec 380 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 381
382 return limit;
383}
384
044c7c41
ML		 385static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
386{
387 struct drm_device *dev = crtc->dev;
044c7c41
ML		 388 const intel_limit_t *limit;
389
390 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 391 if (intel_is_dual_link_lvds(dev))
e4b36699 392 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 393 else
e4b36699 394 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 395 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
396 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 397 limit = &intel_limits_g4x_hdmi;
044c7c41 398 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 399 limit = &intel_limits_g4x_sdvo;
044c7c41 400 } else /* The option is for other outputs */
e4b36699 401 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 402
403 return limit;
404}
405
1b894b59 406static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 407{
408 struct drm_device *dev = crtc->dev;
409 const intel_limit_t *limit;
410
bad720ff 411 if (HAS_PCH_SPLIT(dev))
1b894b59 412 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 413 else if (IS_G4X(dev)) {
044c7c41 414 limit = intel_g4x_limit(crtc);
f2b115e6 415 } else if (IS_PINEVIEW(dev)) {
2177832f 416 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 417 limit = &intel_limits_pineview_lvds;
2177832f 418 else
f2b115e6 419 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 420 } else if (IS_VALLEYVIEW(dev)) {
421 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
422 limit = &intel_limits_vlv_dac;
a0c4da24 423 else
65ce4bf5 424 limit = &intel_limits_vlv_hdmi;
a6c45cf0
CW		 425 } else if (!IS_GEN2(dev)) {
426 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
427 limit = &intel_limits_i9xx_lvds;
428 else
429 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 430 } else {
431 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 432 limit = &intel_limits_i8xx_lvds;
5d536e28 433 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
e4b36699 434 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 435 else
436 limit = &intel_limits_i8xx_dac;
79e53945
JB		 437 }
438 return limit;
439}
440
f2b115e6
AJ		 441/* m1 is reserved as 0 in Pineview, n is a ring counter */
442static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 443{
2177832f
SL		 444 clock->m = clock->m2 + 2;
445 clock->p = clock->p1 * clock->p2;
446 clock->vco = refclk * clock->m / clock->n;
447 clock->dot = clock->vco / clock->p;
448}
449
7429e9d4
DV		 450static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
451{
452 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
453}
454
ac58c3f0 455static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 456{
7429e9d4 457 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 458 clock->p = clock->p1 * clock->p2;
459 clock->vco = refclk * clock->m / (clock->n + 2);
460 clock->dot = clock->vco / clock->p;
461}
462
7c04d1d9 463#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 464/**
465 * Returns whether the given set of divisors are valid for a given refclk with
466 * the given connectors.
467 */
468
1b894b59
CW		 469static bool intel_PLL_is_valid(struct drm_device *dev,
470 const intel_limit_t *limit,
471 const intel_clock_t *clock)
79e53945 472{
79e53945 473 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 474 INTELPllInvalid("p1 out of range\n");
79e53945 475 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 476 INTELPllInvalid("p out of range\n");
79e53945 477 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 478 INTELPllInvalid("m2 out of range\n");
79e53945 479 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 480 INTELPllInvalid("m1 out of range\n");
f2b115e6 481 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 482 INTELPllInvalid("m1 <= m2\n");
79e53945 483 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 484 INTELPllInvalid("m out of range\n");
79e53945 485 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 486 INTELPllInvalid("n out of range\n");
79e53945 487 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 488 INTELPllInvalid("vco out of range\n");
79e53945
JB		 489 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
490 * connector, etc., rather than just a single range.
491 */
492 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 493 INTELPllInvalid("dot out of range\n");
79e53945
JB		 494
495 return true;
496}
497
d4906093 498static bool
ee9300bb 499i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 500 int target, int refclk, intel_clock_t *match_clock,
501 intel_clock_t *best_clock)
79e53945
JB		 502{
503 struct drm_device *dev = crtc->dev;
79e53945 504 intel_clock_t clock;
79e53945
JB		 505 int err = target;
506
a210b028 507 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 508 /*
a210b028
DV		 509 * For LVDS just rely on its current settings for dual-channel.
510 * We haven't figured out how to reliably set up different
511 * single/dual channel state, if we even can.
79e53945 512 */
1974cad0 513 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 514 clock.p2 = limit->p2.p2_fast;
515 else
516 clock.p2 = limit->p2.p2_slow;
517 } else {
518 if (target < limit->p2.dot_limit)
519 clock.p2 = limit->p2.p2_slow;
520 else
521 clock.p2 = limit->p2.p2_fast;
522 }
523
0206e353 524 memset(best_clock, 0, sizeof(*best_clock));
79e53945 525
42158660
ZY		 526 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
527 clock.m1++) {
528 for (clock.m2 = limit->m2.min;
529 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 530 if (clock.m2 >= clock.m1)
42158660
ZY		 531 break;
532 for (clock.n = limit->n.min;
533 clock.n <= limit->n.max; clock.n++) {
534 for (clock.p1 = limit->p1.min;
535 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 536 int this_err;
537
ac58c3f0
DV		 538 i9xx_clock(refclk, &clock);
539 if (!intel_PLL_is_valid(dev, limit,
540 &clock))
541 continue;
542 if (match_clock &&
543 clock.p != match_clock->p)
544 continue;
545
546 this_err = abs(clock.dot - target);
547 if (this_err < err) {
548 *best_clock = clock;
549 err = this_err;
550 }
551 }
552 }
553 }
554 }
555
556 return (err != target);
557}
558
559static bool
ee9300bb
DV		 560pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
561 int target, int refclk, intel_clock_t *match_clock,
562 intel_clock_t *best_clock)
79e53945
JB		 563{
564 struct drm_device *dev = crtc->dev;
79e53945 565 intel_clock_t clock;
79e53945
JB		 566 int err = target;
567
a210b028 568 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 569 /*
a210b028
DV		 570 * For LVDS just rely on its current settings for dual-channel.
571 * We haven't figured out how to reliably set up different
572 * single/dual channel state, if we even can.
79e53945 573 */
1974cad0 574 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 575 clock.p2 = limit->p2.p2_fast;
576 else
577 clock.p2 = limit->p2.p2_slow;
578 } else {
579 if (target < limit->p2.dot_limit)
580 clock.p2 = limit->p2.p2_slow;
581 else
582 clock.p2 = limit->p2.p2_fast;
583 }
584
0206e353 585 memset(best_clock, 0, sizeof(*best_clock));
79e53945 586
42158660
ZY		 587 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
588 clock.m1++) {
589 for (clock.m2 = limit->m2.min;
590 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 591 for (clock.n = limit->n.min;
592 clock.n <= limit->n.max; clock.n++) {
593 for (clock.p1 = limit->p1.min;
594 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 595 int this_err;
596
ac58c3f0 597 pineview_clock(refclk, &clock);
1b894b59
CW		 598 if (!intel_PLL_is_valid(dev, limit,
599 &clock))
79e53945 600 continue;
cec2f356
SP		 601 if (match_clock &&
602 clock.p != match_clock->p)
603 continue;
79e53945
JB		 604
605 this_err = abs(clock.dot - target);
606 if (this_err < err) {
607 *best_clock = clock;
608 err = this_err;
609 }
610 }
611 }
612 }
613 }
614
615 return (err != target);
616}
617
d4906093 618static bool
ee9300bb
DV		 619g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
620 int target, int refclk, intel_clock_t *match_clock,
621 intel_clock_t *best_clock)
d4906093
ML		 622{
623 struct drm_device *dev = crtc->dev;
d4906093
ML		 624 intel_clock_t clock;
625 int max_n;
626 bool found;
6ba770dc
AJ		 627 /* approximately equals target * 0.00585 */
628 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 629 found = false;
630
631 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 632 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 633 clock.p2 = limit->p2.p2_fast;
634 else
635 clock.p2 = limit->p2.p2_slow;
636 } else {
637 if (target < limit->p2.dot_limit)
638 clock.p2 = limit->p2.p2_slow;
639 else
640 clock.p2 = limit->p2.p2_fast;
641 }
642
643 memset(best_clock, 0, sizeof(*best_clock));
644 max_n = limit->n.max;
f77f13e2 645 /* based on hardware requirement, prefer smaller n to precision */
d4906093 646 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 647 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 648 for (clock.m1 = limit->m1.max;
649 clock.m1 >= limit->m1.min; clock.m1--) {
650 for (clock.m2 = limit->m2.max;
651 clock.m2 >= limit->m2.min; clock.m2--) {
652 for (clock.p1 = limit->p1.max;
653 clock.p1 >= limit->p1.min; clock.p1--) {
654 int this_err;
655
ac58c3f0 656 i9xx_clock(refclk, &clock);
1b894b59
CW		 657 if (!intel_PLL_is_valid(dev, limit,
658 &clock))
d4906093 659 continue;
1b894b59
CW		 660
661 this_err = abs(clock.dot - target);
d4906093
ML		 662 if (this_err < err_most) {
663 *best_clock = clock;
664 err_most = this_err;
665 max_n = clock.n;
666 found = true;
667 }
668 }
669 }
670 }
671 }
2c07245f
ZW		 672 return found;
673}
674
a0c4da24 675static bool
ee9300bb
DV		 676vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
677 int target, int refclk, intel_clock_t *match_clock,
678 intel_clock_t *best_clock)
a0c4da24 679{
6b4bf1c4 680 intel_clock_t clock;
69e4f900 681 unsigned int bestppm = 1000000;
27e639bf
VS		 682 /* min update 19.2 MHz */
683 int max_n = min(limit->n.max, refclk / 19200);
a0c4da24 684
6b4bf1c4
VS		 685 target *= 5; /* fast clock */
686
687 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 688
689 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 690 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 691 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
c1a9ae43
VS		 692 for (clock.p2 = limit->p2.p2_fast; clock.p2 > 0;
693 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 694 clock.p = clock.p1 * clock.p2;
a0c4da24 695 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 696 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
69e4f900
VS		 697 unsigned int ppm, diff;
698
6b4bf1c4
VS		 699 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
700 refclk * clock.m1);
701
702 vlv_clock(refclk, &clock);
43b0ac53 703
6b4bf1c4
VS		 704 if (clock.vco < limit->vco.min ||
705 clock.vco >= limit->vco.max)
43b0ac53
VS		 706 continue;
707
6b4bf1c4
VS		 708 diff = abs(clock.dot - target);
709 ppm = div_u64(1000000ULL * diff, target);
710
711 if (ppm < 100 && clock.p > best_clock->p) {
43b0ac53 712 bestppm = 0;
6b4bf1c4 713 *best_clock = clock;
43b0ac53 714 }
6b4bf1c4 715
c686122c 716 if (bestppm >= 10 && ppm < bestppm - 10) {
69e4f900 717 bestppm = ppm;
6b4bf1c4 718 *best_clock = clock;
a0c4da24
JB		 719 }
720 }
721 }
722 }
723 }
a0c4da24
JB		 724
725 return true;
726}
a4fc5ed6 727
20ddf665
VS		 728bool intel_crtc_active(struct drm_crtc *crtc)
729{
730 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
731
732 /* Be paranoid as we can arrive here with only partial
733 * state retrieved from the hardware during setup.
734 *
241bfc38 735 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 736 * as Haswell has gained clock readout/fastboot support.
737 *
738 * We can ditch the crtc->fb check as soon as we can
739 * properly reconstruct framebuffers.
740 */
741 return intel_crtc->active && crtc->fb &&
241bfc38 742 intel_crtc->config.adjusted_mode.crtc_clock;
20ddf665
VS		 743}
744
a5c961d1
PZ		 745enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
746 enum pipe pipe)
747{
748 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
749 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
750
3b117c8f 751 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 752}
753
a928d536
PZ		 754static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
755{
756 struct drm_i915_private *dev_priv = dev->dev_private;
757 u32 frame, frame_reg = PIPEFRAME(pipe);
758
759 frame = I915_READ(frame_reg);
760
761 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
762 DRM_DEBUG_KMS("vblank wait timed out\n");
763}
764
9d0498a2
JB		 765/**
766 * intel_wait_for_vblank - wait for vblank on a given pipe
767 * @dev: drm device
768 * @pipe: pipe to wait for
769 *
770 * Wait for vblank to occur on a given pipe. Needed for various bits of
771 * mode setting code.
772 */
773void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 774{
9d0498a2 775 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 776 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 777
a928d536
PZ		 778 if (INTEL_INFO(dev)->gen >= 5) {
779 ironlake_wait_for_vblank(dev, pipe);
780 return;
781 }
782
300387c0
CW		 783 /* Clear existing vblank status. Note this will clear any other
784 * sticky status fields as well.
785 *
786 * This races with i915_driver_irq_handler() with the result
787 * that either function could miss a vblank event. Here it is not
788 * fatal, as we will either wait upon the next vblank interrupt or
789 * timeout. Generally speaking intel_wait_for_vblank() is only
790 * called during modeset at which time the GPU should be idle and
791 * should *not* be performing page flips and thus not waiting on
792 * vblanks...
793 * Currently, the result of us stealing a vblank from the irq
794 * handler is that a single frame will be skipped during swapbuffers.
795 */
796 I915_WRITE(pipestat_reg,
797 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
798
9d0498a2 799 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 800 if (wait_for(I915_READ(pipestat_reg) &
801 PIPE_VBLANK_INTERRUPT_STATUS,
802 50))
9d0498a2
JB		 803 DRM_DEBUG_KMS("vblank wait timed out\n");
804}
805
ab7ad7f6
KP		 806/*
807 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 808 * @dev: drm device
809 * @pipe: pipe to wait for
810 *
811 * After disabling a pipe, we can't wait for vblank in the usual way,
812 * spinning on the vblank interrupt status bit, since we won't actually
813 * see an interrupt when the pipe is disabled.
814 *
ab7ad7f6
KP		 815 * On Gen4 and above:
816 * wait for the pipe register state bit to turn off
817 *
818 * Otherwise:
819 * wait for the display line value to settle (it usually
820 * ends up stopping at the start of the next frame).
58e10eb9 821 *
9d0498a2 822 */
58e10eb9 823void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 824{
825 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 826 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
827 pipe);
ab7ad7f6
KP		 828
829 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 830 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 831
832 /* Wait for the Pipe State to go off */
58e10eb9
CW		 833 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
834 100))
284637d9 835 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 836 } else {
837ba00f 837 u32 last_line, line_mask;
58e10eb9 838 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 839 unsigned long timeout = jiffies + msecs_to_jiffies(100);
840
837ba00f
PZ		 841 if (IS_GEN2(dev))
842 line_mask = DSL_LINEMASK_GEN2;
843 else
844 line_mask = DSL_LINEMASK_GEN3;
845
ab7ad7f6
KP		 846 /* Wait for the display line to settle */
847 do {
837ba00f 848 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 849 mdelay(5);
837ba00f 850 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 851 time_after(timeout, jiffies));
852 if (time_after(jiffies, timeout))
284637d9 853 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 854 }
79e53945
JB		 855}
856
b0ea7d37
DL		 857/*
858 * ibx_digital_port_connected - is the specified port connected?
859 * @dev_priv: i915 private structure
860 * @port: the port to test
861 *
862 * Returns true if @port is connected, false otherwise.
863 */
864bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
865 struct intel_digital_port *port)
866{
867 u32 bit;
868
c36346e3
DL		 869 if (HAS_PCH_IBX(dev_priv->dev)) {
870 switch(port->port) {
871 case PORT_B:
872 bit = SDE_PORTB_HOTPLUG;
873 break;
874 case PORT_C:
875 bit = SDE_PORTC_HOTPLUG;
876 break;
877 case PORT_D:
878 bit = SDE_PORTD_HOTPLUG;
879 break;
880 default:
881 return true;
882 }
883 } else {
884 switch(port->port) {
885 case PORT_B:
886 bit = SDE_PORTB_HOTPLUG_CPT;
887 break;
888 case PORT_C:
889 bit = SDE_PORTC_HOTPLUG_CPT;
890 break;
891 case PORT_D:
892 bit = SDE_PORTD_HOTPLUG_CPT;
893 break;
894 default:
895 return true;
896 }
b0ea7d37
DL		 897 }
898
899 return I915_READ(SDEISR) & bit;
900}
901
b24e7179
JB		 902static const char *state_string(bool enabled)
903{
904 return enabled ? "on" : "off";
905}
906
907/* Only for pre-ILK configs */
55607e8a
DV		 908void assert_pll(struct drm_i915_private *dev_priv,
909 enum pipe pipe, bool state)
b24e7179
JB		 910{
911 int reg;
912 u32 val;
913 bool cur_state;
914
915 reg = DPLL(pipe);
916 val = I915_READ(reg);
917 cur_state = !!(val & DPLL_VCO_ENABLE);
918 WARN(cur_state != state,
919 "PLL state assertion failure (expected %s, current %s)\n",
920 state_string(state), state_string(cur_state));
921}
b24e7179 922
23538ef1
JN		 923/* XXX: the dsi pll is shared between MIPI DSI ports */
924static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
925{
926 u32 val;
927 bool cur_state;
928
929 mutex_lock(&dev_priv->dpio_lock);
930 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
931 mutex_unlock(&dev_priv->dpio_lock);
932
933 cur_state = val & DSI_PLL_VCO_EN;
934 WARN(cur_state != state,
935 "DSI PLL state assertion failure (expected %s, current %s)\n",
936 state_string(state), state_string(cur_state));
937}
938#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
939#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
940
55607e8a 941struct intel_shared_dpll *
e2b78267
DV		 942intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
943{
944 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
945
a43f6e0f 946 if (crtc->config.shared_dpll < 0)
e2b78267
DV		 947 return NULL;
948
a43f6e0f 949 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
e2b78267
DV		 950}
951
040484af 952/* For ILK+ */
55607e8a
DV		 953void assert_shared_dpll(struct drm_i915_private *dev_priv,
954 struct intel_shared_dpll *pll,
955 bool state)
040484af 956{
040484af 957 bool cur_state;
5358901f 958 struct intel_dpll_hw_state hw_state;
040484af 959
9d82aa17
ED		 960 if (HAS_PCH_LPT(dev_priv->dev)) {
961 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
962 return;
963 }
964
92b27b08 965 if (WARN (!pll,
46edb027 966 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 967 return;
ee7b9f93 968
5358901f 969 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
92b27b08 970 WARN(cur_state != state,
5358901f
DV		 971 "%s assertion failure (expected %s, current %s)\n",
972 pll->name, state_string(state), state_string(cur_state));
040484af 973}
040484af
JB		 974
975static void assert_fdi_tx(struct drm_i915_private *dev_priv,
976 enum pipe pipe, bool state)
977{
978 int reg;
979 u32 val;
980 bool cur_state;
ad80a810
PZ		 981 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
982 pipe);
040484af 983
affa9354
PZ		 984 if (HAS_DDI(dev_priv->dev)) {
985 /* DDI does not have a specific FDI_TX register */
ad80a810 986 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 987 val = I915_READ(reg);
ad80a810 988 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 989 } else {
990 reg = FDI_TX_CTL(pipe);
991 val = I915_READ(reg);
992 cur_state = !!(val & FDI_TX_ENABLE);
993 }
040484af
JB		 994 WARN(cur_state != state,
995 "FDI TX state assertion failure (expected %s, current %s)\n",
996 state_string(state), state_string(cur_state));
997}
998#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
999#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1000
1001static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1002 enum pipe pipe, bool state)
1003{
1004 int reg;
1005 u32 val;
1006 bool cur_state;
1007
d63fa0dc
PZ		 1008 reg = FDI_RX_CTL(pipe);
1009 val = I915_READ(reg);
1010 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1011 WARN(cur_state != state,
1012 "FDI RX state assertion failure (expected %s, current %s)\n",
1013 state_string(state), state_string(cur_state));
1014}
1015#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1016#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1017
1018static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1019 enum pipe pipe)
1020{
1021 int reg;
1022 u32 val;
1023
1024 /* ILK FDI PLL is always enabled */
1025 if (dev_priv->info->gen == 5)
1026 return;
1027
bf507ef7 1028 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1029 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1030 return;
1031
040484af
JB		 1032 reg = FDI_TX_CTL(pipe);
1033 val = I915_READ(reg);
1034 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1035}
1036
55607e8a
DV		 1037void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1038 enum pipe pipe, bool state)
040484af
JB		 1039{
1040 int reg;
1041 u32 val;
55607e8a 1042 bool cur_state;
040484af
JB		 1043
1044 reg = FDI_RX_CTL(pipe);
1045 val = I915_READ(reg);
55607e8a
DV		 1046 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1047 WARN(cur_state != state,
1048 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1049 state_string(state), state_string(cur_state));
040484af
JB		 1050}
1051
ea0760cf
JB		 1052static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1053 enum pipe pipe)
1054{
1055 int pp_reg, lvds_reg;
1056 u32 val;
1057 enum pipe panel_pipe = PIPE_A;
0de3b485 1058 bool locked = true;
ea0760cf
JB		 1059
1060 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1061 pp_reg = PCH_PP_CONTROL;
1062 lvds_reg = PCH_LVDS;
1063 } else {
1064 pp_reg = PP_CONTROL;
1065 lvds_reg = LVDS;
1066 }
1067
1068 val = I915_READ(pp_reg);
1069 if (!(val & PANEL_POWER_ON) ||
1070 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1071 locked = false;
1072
1073 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1074 panel_pipe = PIPE_B;
1075
1076 WARN(panel_pipe == pipe && locked,
1077 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1078 pipe_name(pipe));
ea0760cf
JB		 1079}
1080
93ce0ba6
JN		 1081static void assert_cursor(struct drm_i915_private *dev_priv,
1082 enum pipe pipe, bool state)
1083{
1084 struct drm_device *dev = dev_priv->dev;
1085 bool cur_state;
1086
1087 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1088 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1089 else if (IS_845G(dev) || IS_I865G(dev))
1090 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1091 else
1092 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1093
1094 WARN(cur_state != state,
1095 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1096 pipe_name(pipe), state_string(state), state_string(cur_state));
1097}
1098#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1099#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1100
b840d907
JB		 1101void assert_pipe(struct drm_i915_private *dev_priv,
1102 enum pipe pipe, bool state)
b24e7179
JB		 1103{
1104 int reg;
1105 u32 val;
63d7bbe9 1106 bool cur_state;
702e7a56
PZ		 1107 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1108 pipe);
b24e7179 1109
8e636784
DV		 1110 /* if we need the pipe A quirk it must be always on */
1111 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1112 state = true;
1113
b97186f0
PZ		 1114 if (!intel_display_power_enabled(dev_priv->dev,
1115 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1116 cur_state = false;
1117 } else {
1118 reg = PIPECONF(cpu_transcoder);
1119 val = I915_READ(reg);
1120 cur_state = !!(val & PIPECONF_ENABLE);
1121 }
1122
63d7bbe9
JB		 1123 WARN(cur_state != state,
1124 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1125 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1126}
1127
931872fc
CW		 1128static void assert_plane(struct drm_i915_private *dev_priv,
1129 enum plane plane, bool state)
b24e7179
JB		 1130{
1131 int reg;
1132 u32 val;
931872fc 1133 bool cur_state;
b24e7179
JB		 1134
1135 reg = DSPCNTR(plane);
1136 val = I915_READ(reg);
931872fc
CW		 1137 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1138 WARN(cur_state != state,
1139 "plane %c assertion failure (expected %s, current %s)\n",
1140 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1141}
1142
931872fc
CW		 1143#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1144#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1145
b24e7179
JB		 1146static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1147 enum pipe pipe)
1148{
653e1026 1149 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1150 int reg, i;
1151 u32 val;
1152 int cur_pipe;
1153
653e1026
VS		 1154 /* Primary planes are fixed to pipes on gen4+ */
1155 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1156 reg = DSPCNTR(pipe);
1157 val = I915_READ(reg);
1158 WARN((val & DISPLAY_PLANE_ENABLE),
1159 "plane %c assertion failure, should be disabled but not\n",
1160 plane_name(pipe));
19ec1358 1161 return;
28c05794 1162 }
19ec1358 1163
b24e7179 1164 /* Need to check both planes against the pipe */
08e2a7de 1165 for_each_pipe(i) {
b24e7179
JB		 1166 reg = DSPCNTR(i);
1167 val = I915_READ(reg);
1168 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1169 DISPPLANE_SEL_PIPE_SHIFT;
1170 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1171 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1172 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1173 }
1174}
1175
19332d7a
JB		 1176static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1177 enum pipe pipe)
1178{
20674eef 1179 struct drm_device *dev = dev_priv->dev;
19332d7a
JB		 1180 int reg, i;
1181 u32 val;
1182
20674eef
VS		 1183 if (IS_VALLEYVIEW(dev)) {
1184 for (i = 0; i < dev_priv->num_plane; i++) {
1185 reg = SPCNTR(pipe, i);
1186 val = I915_READ(reg);
1187 WARN((val & SP_ENABLE),
1188 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1189 sprite_name(pipe, i), pipe_name(pipe));
1190 }
1191 } else if (INTEL_INFO(dev)->gen >= 7) {
1192 reg = SPRCTL(pipe);
19332d7a 1193 val = I915_READ(reg);
20674eef 1194 WARN((val & SPRITE_ENABLE),
06da8da2 1195 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1196 plane_name(pipe), pipe_name(pipe));
1197 } else if (INTEL_INFO(dev)->gen >= 5) {
1198 reg = DVSCNTR(pipe);
19332d7a 1199 val = I915_READ(reg);
20674eef 1200 WARN((val & DVS_ENABLE),
06da8da2 1201 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1202 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1203 }
1204}
1205
92f2584a
JB		 1206static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1207{
1208 u32 val;
1209 bool enabled;
1210
9d82aa17
ED		 1211 if (HAS_PCH_LPT(dev_priv->dev)) {
1212 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1213 return;
1214 }
1215
92f2584a
JB		 1216 val = I915_READ(PCH_DREF_CONTROL);
1217 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1218 DREF_SUPERSPREAD_SOURCE_MASK));
1219 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1220}
1221
ab9412ba
DV		 1222static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1223 enum pipe pipe)
92f2584a
JB		 1224{
1225 int reg;
1226 u32 val;
1227 bool enabled;
1228
ab9412ba 1229 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1230 val = I915_READ(reg);
1231 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1232 WARN(enabled,
1233 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1234 pipe_name(pipe));
92f2584a
JB		 1235}
1236
4e634389
KP		 1237static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1238 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1239{
1240 if ((val & DP_PORT_EN) == 0)
1241 return false;
1242
1243 if (HAS_PCH_CPT(dev_priv->dev)) {
1244 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1245 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1246 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1247 return false;
1248 } else {
1249 if ((val & DP_PIPE_MASK) != (pipe << 30))
1250 return false;
1251 }
1252 return true;
1253}
1254
1519b995
KP		 1255static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1256 enum pipe pipe, u32 val)
1257{
dc0fa718 1258 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1259 return false;
1260
1261 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1262 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1263 return false;
1264 } else {
dc0fa718 1265 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1266 return false;
1267 }
1268 return true;
1269}
1270
1271static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1272 enum pipe pipe, u32 val)
1273{
1274 if ((val & LVDS_PORT_EN) == 0)
1275 return false;
1276
1277 if (HAS_PCH_CPT(dev_priv->dev)) {
1278 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1279 return false;
1280 } else {
1281 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1282 return false;
1283 }
1284 return true;
1285}
1286
1287static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1288 enum pipe pipe, u32 val)
1289{
1290 if ((val & ADPA_DAC_ENABLE) == 0)
1291 return false;
1292 if (HAS_PCH_CPT(dev_priv->dev)) {
1293 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1294 return false;
1295 } else {
1296 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1297 return false;
1298 }
1299 return true;
1300}
1301
291906f1 1302static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1303 enum pipe pipe, int reg, u32 port_sel)
291906f1 1304{
47a05eca 1305 u32 val = I915_READ(reg);
4e634389 1306 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1307 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1308 reg, pipe_name(pipe));
de9a35ab 1309
75c5da27
DV		 1310 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1311 && (val & DP_PIPEB_SELECT),
de9a35ab 1312 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1313}
1314
1315static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1316 enum pipe pipe, int reg)
1317{
47a05eca 1318 u32 val = I915_READ(reg);
b70ad586 1319 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1320 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1321 reg, pipe_name(pipe));
de9a35ab 1322
dc0fa718 1323 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1324 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1325 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1326}
1327
1328static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1329 enum pipe pipe)
1330{
1331 int reg;
1332 u32 val;
291906f1 1333
f0575e92
KP		 1334 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1335 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1336 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1337
1338 reg = PCH_ADPA;
1339 val = I915_READ(reg);
b70ad586 1340 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1341 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1342 pipe_name(pipe));
291906f1
JB		 1343
1344 reg = PCH_LVDS;
1345 val = I915_READ(reg);
b70ad586 1346 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1347 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1348 pipe_name(pipe));
291906f1 1349
e2debe91
PZ		 1350 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1351 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1352 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1353}
1354
40e9cf64
JB		 1355static void intel_init_dpio(struct drm_device *dev)
1356{
1357 struct drm_i915_private *dev_priv = dev->dev_private;
1358
1359 if (!IS_VALLEYVIEW(dev))
1360 return;
1361
1362 /*
1363 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1364 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
1365 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
1366 * b. The other bits such as sfr settings / modesel may all be set
1367 * to 0.
1368 *
1369 * This should only be done on init and resume from S3 with both
1370 * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1371 */
1372 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1373}
1374
426115cf 1375static void vlv_enable_pll(struct intel_crtc *crtc)
87442f73 1376{
426115cf
DV		 1377 struct drm_device *dev = crtc->base.dev;
1378 struct drm_i915_private *dev_priv = dev->dev_private;
1379 int reg = DPLL(crtc->pipe);
1380 u32 dpll = crtc->config.dpll_hw_state.dpll;
87442f73 1381
426115cf 1382 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1383
1384 /* No really, not for ILK+ */
1385 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1386
1387 /* PLL is protected by panel, make sure we can write it */
1388 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
426115cf 1389 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1390
426115cf
DV		 1391 I915_WRITE(reg, dpll);
1392 POSTING_READ(reg);
1393 udelay(150);
1394
1395 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1396 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1397
1398 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1399 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1400
1401 /* We do this three times for luck */
426115cf 1402 I915_WRITE(reg, dpll);
87442f73
DV		 1403 POSTING_READ(reg);
1404 udelay(150); /* wait for warmup */
426115cf 1405 I915_WRITE(reg, dpll);
87442f73
DV		 1406 POSTING_READ(reg);
1407 udelay(150); /* wait for warmup */
426115cf 1408 I915_WRITE(reg, dpll);
87442f73
DV		 1409 POSTING_READ(reg);
1410 udelay(150); /* wait for warmup */
1411}
1412
66e3d5c0 1413static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1414{
66e3d5c0
DV		 1415 struct drm_device *dev = crtc->base.dev;
1416 struct drm_i915_private *dev_priv = dev->dev_private;
1417 int reg = DPLL(crtc->pipe);
1418 u32 dpll = crtc->config.dpll_hw_state.dpll;
63d7bbe9 1419
66e3d5c0 1420 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1421
63d7bbe9 1422 /* No really, not for ILK+ */
87442f73 1423 BUG_ON(dev_priv->info->gen >= 5);
63d7bbe9
JB		 1424
1425 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1426 if (IS_MOBILE(dev) && !IS_I830(dev))
1427 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1428
66e3d5c0
DV		 1429 I915_WRITE(reg, dpll);
1430
1431 /* Wait for the clocks to stabilize. */
1432 POSTING_READ(reg);
1433 udelay(150);
1434
1435 if (INTEL_INFO(dev)->gen >= 4) {
1436 I915_WRITE(DPLL_MD(crtc->pipe),
1437 crtc->config.dpll_hw_state.dpll_md);
1438 } else {
1439 /* The pixel multiplier can only be updated once the
1440 * DPLL is enabled and the clocks are stable.
1441 *
1442 * So write it again.
1443 */
1444 I915_WRITE(reg, dpll);
1445 }
63d7bbe9
JB		 1446
1447 /* We do this three times for luck */
66e3d5c0 1448 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1449 POSTING_READ(reg);
1450 udelay(150); /* wait for warmup */
66e3d5c0 1451 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1452 POSTING_READ(reg);
1453 udelay(150); /* wait for warmup */
66e3d5c0 1454 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1455 POSTING_READ(reg);
1456 udelay(150); /* wait for warmup */
1457}
1458
1459/**
50b44a44 1460 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1461 * @dev_priv: i915 private structure
1462 * @pipe: pipe PLL to disable
1463 *
1464 * Disable the PLL for @pipe, making sure the pipe is off first.
1465 *
1466 * Note! This is for pre-ILK only.
1467 */
50b44a44 1468static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9 1469{
63d7bbe9
JB		 1470 /* Don't disable pipe A or pipe A PLLs if needed */
1471 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1472 return;
1473
1474 /* Make sure the pipe isn't still relying on us */
1475 assert_pipe_disabled(dev_priv, pipe);
1476
50b44a44
DV		 1477 I915_WRITE(DPLL(pipe), 0);
1478 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1479}
1480
f6071166
JB		 1481static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1482{
1483 u32 val = 0;
1484
1485 /* Make sure the pipe isn't still relying on us */
1486 assert_pipe_disabled(dev_priv, pipe);
1487
1488 /* Leave integrated clock source enabled */
1489 if (pipe == PIPE_B)
1490 val = DPLL_INTEGRATED_CRI_CLK_VLV;
1491 I915_WRITE(DPLL(pipe), val);
1492 POSTING_READ(DPLL(pipe));
1493}
1494
89b667f8
JB		 1495void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1496{
1497 u32 port_mask;
1498
1499 if (!port)
1500 port_mask = DPLL_PORTB_READY_MASK;
1501 else
1502 port_mask = DPLL_PORTC_READY_MASK;
1503
1504 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1505 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1506 'B' + port, I915_READ(DPLL(0)));
1507}
1508
92f2584a 1509/**
e72f9fbf 1510 * ironlake_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1511 * @dev_priv: i915 private structure
1512 * @pipe: pipe PLL to enable
1513 *
1514 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1515 * drives the transcoder clock.
1516 */
e2b78267 1517static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1518{
e2b78267
DV		 1519 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1520 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1521
48da64a8 1522 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1523 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1524 if (WARN_ON(pll == NULL))
48da64a8
CW		 1525 return;
1526
1527 if (WARN_ON(pll->refcount == 0))
1528 return;
ee7b9f93 1529
46edb027
DV		 1530 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1531 pll->name, pll->active, pll->on,
e2b78267 1532 crtc->base.base.id);
92f2584a 1533
cdbd2316
DV		 1534 if (pll->active++) {
1535 WARN_ON(!pll->on);
e9d6944e 1536 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1537 return;
1538 }
f4a091c7 1539 WARN_ON(pll->on);
ee7b9f93 1540
46edb027 1541 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1542 pll->enable(dev_priv, pll);
ee7b9f93 1543 pll->on = true;
92f2584a
JB		 1544}
1545
e2b78267 1546static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1547{
e2b78267
DV		 1548 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1549 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1550
92f2584a
JB		 1551 /* PCH only available on ILK+ */
1552 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1553 if (WARN_ON(pll == NULL))
ee7b9f93 1554 return;
92f2584a 1555
48da64a8
CW		 1556 if (WARN_ON(pll->refcount == 0))
1557 return;
7a419866 1558
46edb027
DV		 1559 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1560 pll->name, pll->active, pll->on,
e2b78267 1561 crtc->base.base.id);
7a419866 1562
48da64a8 1563 if (WARN_ON(pll->active == 0)) {
e9d6944e 1564 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1565 return;
1566 }
1567
e9d6944e 1568 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1569 WARN_ON(!pll->on);
cdbd2316 1570 if (--pll->active)
7a419866 1571 return;
ee7b9f93 1572
46edb027 1573 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1574 pll->disable(dev_priv, pll);
ee7b9f93 1575 pll->on = false;
92f2584a
JB		 1576}
1577
b8a4f404
PZ		 1578static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1579 enum pipe pipe)
040484af 1580{
23670b32 1581 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1582 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1583 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1584 uint32_t reg, val, pipeconf_val;
040484af
JB		 1585
1586 /* PCH only available on ILK+ */
1587 BUG_ON(dev_priv->info->gen < 5);
1588
1589 /* Make sure PCH DPLL is enabled */
e72f9fbf 1590 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1591 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1592
1593 /* FDI must be feeding us bits for PCH ports */
1594 assert_fdi_tx_enabled(dev_priv, pipe);
1595 assert_fdi_rx_enabled(dev_priv, pipe);
1596
23670b32
DV		 1597 if (HAS_PCH_CPT(dev)) {
1598 /* Workaround: Set the timing override bit before enabling the
1599 * pch transcoder. */
1600 reg = TRANS_CHICKEN2(pipe);
1601 val = I915_READ(reg);
1602 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1603 I915_WRITE(reg, val);
59c859d6 1604 }
23670b32 1605
ab9412ba 1606 reg = PCH_TRANSCONF(pipe);
040484af 1607 val = I915_READ(reg);
5f7f726d 1608 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1609
1610 if (HAS_PCH_IBX(dev_priv->dev)) {
1611 /*
1612 * make the BPC in transcoder be consistent with
1613 * that in pipeconf reg.
1614 */
dfd07d72
DV		 1615 val &= ~PIPECONF_BPC_MASK;
1616 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1617 }
5f7f726d
PZ		 1618
1619 val &= ~TRANS_INTERLACE_MASK;
1620 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1621 if (HAS_PCH_IBX(dev_priv->dev) &&
1622 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1623 val |= TRANS_LEGACY_INTERLACED_ILK;
1624 else
1625 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1626 else
1627 val |= TRANS_PROGRESSIVE;
1628
040484af
JB		 1629 I915_WRITE(reg, val | TRANS_ENABLE);
1630 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1631 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1632}
1633
8fb033d7 1634static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1635 enum transcoder cpu_transcoder)
040484af 1636{
8fb033d7 1637 u32 val, pipeconf_val;
8fb033d7
PZ		 1638
1639 /* PCH only available on ILK+ */
1640 BUG_ON(dev_priv->info->gen < 5);
1641
8fb033d7 1642 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1643 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1644 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1645
223a6fdf
PZ		 1646 /* Workaround: set timing override bit. */
1647 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1648 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1649 I915_WRITE(_TRANSA_CHICKEN2, val);
1650
25f3ef11 1651 val = TRANS_ENABLE;
937bb610 1652 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1653
9a76b1c6
PZ		 1654 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1655 PIPECONF_INTERLACED_ILK)
a35f2679 1656 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1657 else
1658 val |= TRANS_PROGRESSIVE;
1659
ab9412ba
DV		 1660 I915_WRITE(LPT_TRANSCONF, val);
1661 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1662 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1663}
1664
b8a4f404
PZ		 1665static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1666 enum pipe pipe)
040484af 1667{
23670b32
DV		 1668 struct drm_device *dev = dev_priv->dev;
1669 uint32_t reg, val;
040484af
JB		 1670
1671 /* FDI relies on the transcoder */
1672 assert_fdi_tx_disabled(dev_priv, pipe);
1673 assert_fdi_rx_disabled(dev_priv, pipe);
1674
291906f1
JB		 1675 /* Ports must be off as well */
1676 assert_pch_ports_disabled(dev_priv, pipe);
1677
ab9412ba 1678 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1679 val = I915_READ(reg);
1680 val &= ~TRANS_ENABLE;
1681 I915_WRITE(reg, val);
1682 /* wait for PCH transcoder off, transcoder state */
1683 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1684 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1685
1686 if (!HAS_PCH_IBX(dev)) {
1687 /* Workaround: Clear the timing override chicken bit again. */
1688 reg = TRANS_CHICKEN2(pipe);
1689 val = I915_READ(reg);
1690 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1691 I915_WRITE(reg, val);
1692 }
040484af
JB		 1693}
1694
ab4d966c 1695static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1696{
8fb033d7
PZ		 1697 u32 val;
1698
ab9412ba 1699 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1700 val &= ~TRANS_ENABLE;
ab9412ba 1701 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1702 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1703 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1704 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1705
1706 /* Workaround: clear timing override bit. */
1707 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1708 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1709 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1710}
1711
b24e7179 1712/**
309cfea8 1713 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1714 * @dev_priv: i915 private structure
1715 * @pipe: pipe to enable
040484af 1716 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1717 *
1718 * Enable @pipe, making sure that various hardware specific requirements
1719 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1720 *
1721 * @pipe should be %PIPE_A or %PIPE_B.
1722 *
1723 * Will wait until the pipe is actually running (i.e. first vblank) before
1724 * returning.
1725 */
040484af 1726static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
23538ef1 1727 bool pch_port, bool dsi)
b24e7179 1728{
702e7a56
PZ		 1729 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1730 pipe);
1a240d4d 1731 enum pipe pch_transcoder;
b24e7179
JB		 1732 int reg;
1733 u32 val;
1734
58c6eaa2 1735 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 1736 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 1737 assert_sprites_disabled(dev_priv, pipe);
1738
681e5811 1739 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1740 pch_transcoder = TRANSCODER_A;
1741 else
1742 pch_transcoder = pipe;
1743
b24e7179
JB		 1744 /*
1745 * A pipe without a PLL won't actually be able to drive bits from
1746 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1747 * need the check.
1748 */
1749 if (!HAS_PCH_SPLIT(dev_priv->dev))
23538ef1
JN		 1750 if (dsi)
1751 assert_dsi_pll_enabled(dev_priv);
1752 else
1753 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1754 else {
1755 if (pch_port) {
1756 /* if driving the PCH, we need FDI enabled */
cc391bbb 1757 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1758 assert_fdi_tx_pll_enabled(dev_priv,
1759 (enum pipe) cpu_transcoder);
040484af
JB		 1760 }
1761 /* FIXME: assert CPU port conditions for SNB+ */
1762 }
b24e7179 1763
702e7a56 1764 reg = PIPECONF(cpu_transcoder);
b24e7179 1765 val = I915_READ(reg);
00d70b15
CW		 1766 if (val & PIPECONF_ENABLE)
1767 return;
1768
1769 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1770 intel_wait_for_vblank(dev_priv->dev, pipe);
1771}
1772
1773/**
309cfea8 1774 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1775 * @dev_priv: i915 private structure
1776 * @pipe: pipe to disable
1777 *
1778 * Disable @pipe, making sure that various hardware specific requirements
1779 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1780 *
1781 * @pipe should be %PIPE_A or %PIPE_B.
1782 *
1783 * Will wait until the pipe has shut down before returning.
1784 */
1785static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1786 enum pipe pipe)
1787{
702e7a56
PZ		 1788 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1789 pipe);
b24e7179
JB		 1790 int reg;
1791 u32 val;
1792
1793 /*
1794 * Make sure planes won't keep trying to pump pixels to us,
1795 * or we might hang the display.
1796 */
1797 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 1798 assert_cursor_disabled(dev_priv, pipe);
19332d7a 1799 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1800
1801 /* Don't disable pipe A or pipe A PLLs if needed */
1802 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1803 return;
1804
702e7a56 1805 reg = PIPECONF(cpu_transcoder);
b24e7179 1806 val = I915_READ(reg);
00d70b15
CW		 1807 if ((val & PIPECONF_ENABLE) == 0)
1808 return;
1809
1810 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1811 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1812}
1813
d74362c9
KP		 1814/*
1815 * Plane regs are double buffered, going from enabled->disabled needs a
1816 * trigger in order to latch. The display address reg provides this.
1817 */
6f1d69b0 1818void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1819 enum plane plane)
1820{
14f86147
DL		 1821 if (dev_priv->info->gen >= 4)
1822 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1823 else
1824 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1825}
1826
b24e7179
JB		 1827/**
1828 * intel_enable_plane - enable a display plane on a given pipe
1829 * @dev_priv: i915 private structure
1830 * @plane: plane to enable
1831 * @pipe: pipe being fed
1832 *
1833 * Enable @plane on @pipe, making sure that @pipe is running first.
1834 */
1835static void intel_enable_plane(struct drm_i915_private *dev_priv,
1836 enum plane plane, enum pipe pipe)
1837{
1838 int reg;
1839 u32 val;
1840
1841 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1842 assert_pipe_enabled(dev_priv, pipe);
1843
1844 reg = DSPCNTR(plane);
1845 val = I915_READ(reg);
00d70b15
CW		 1846 if (val & DISPLAY_PLANE_ENABLE)
1847 return;
1848
1849 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1850 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1851 intel_wait_for_vblank(dev_priv->dev, pipe);
1852}
1853
b24e7179
JB		 1854/**
1855 * intel_disable_plane - disable a display plane
1856 * @dev_priv: i915 private structure
1857 * @plane: plane to disable
1858 * @pipe: pipe consuming the data
1859 *
1860 * Disable @plane; should be an independent operation.
1861 */
1862static void intel_disable_plane(struct drm_i915_private *dev_priv,
1863 enum plane plane, enum pipe pipe)
1864{
1865 int reg;
1866 u32 val;
1867
1868 reg = DSPCNTR(plane);
1869 val = I915_READ(reg);
00d70b15
CW		 1870 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1871 return;
1872
1873 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1874 intel_flush_display_plane(dev_priv, plane);
1875 intel_wait_for_vblank(dev_priv->dev, pipe);
1876}
1877
693db184
CW		 1878static bool need_vtd_wa(struct drm_device *dev)
1879{
1880#ifdef CONFIG_INTEL_IOMMU
1881 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1882 return true;
1883#endif
1884 return false;
1885}
1886
127bd2ac 1887int
48b956c5 1888intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1889 struct drm_i915_gem_object *obj,
919926ae 1890 struct intel_ring_buffer *pipelined)
6b95a207 1891{
ce453d81 1892 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1893 u32 alignment;
1894 int ret;
1895
05394f39 1896 switch (obj->tiling_mode) {
6b95a207 1897 case I915_TILING_NONE:
534843da
CW		 1898 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1899 alignment = 128 * 1024;
a6c45cf0 1900 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1901 alignment = 4 * 1024;
1902 else
1903 alignment = 64 * 1024;
6b95a207
KH		 1904 break;
1905 case I915_TILING_X:
1906 /* pin() will align the object as required by fence */
1907 alignment = 0;
1908 break;
1909 case I915_TILING_Y:
8bb6e959
DV		 1910 /* Despite that we check this in framebuffer_init userspace can
1911 * screw us over and change the tiling after the fact. Only
1912 * pinned buffers can't change their tiling. */
1913 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1914 return -EINVAL;
1915 default:
1916 BUG();
1917 }
1918
693db184
CW		 1919 /* Note that the w/a also requires 64 PTE of padding following the
1920 * bo. We currently fill all unused PTE with the shadow page and so
1921 * we should always have valid PTE following the scanout preventing
1922 * the VT-d warning.
1923 */
1924 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1925 alignment = 256 * 1024;
1926
ce453d81 1927 dev_priv->mm.interruptible = false;
2da3b9b9 1928 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1929 if (ret)
ce453d81 1930 goto err_interruptible;
6b95a207
KH		 1931
1932 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1933 * fence, whereas 965+ only requires a fence if using
1934 * framebuffer compression. For simplicity, we always install
1935 * a fence as the cost is not that onerous.
1936 */
06d98131 1937 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1938 if (ret)
1939 goto err_unpin;
1690e1eb 1940
9a5a53b3 1941 i915_gem_object_pin_fence(obj);
6b95a207 1942
ce453d81 1943 dev_priv->mm.interruptible = true;
6b95a207 1944 return 0;
48b956c5
CW		 1945
1946err_unpin:
cc98b413 1947 i915_gem_object_unpin_from_display_plane(obj);
ce453d81
CW		 1948err_interruptible:
1949 dev_priv->mm.interruptible = true;
48b956c5 1950 return ret;
6b95a207
KH		 1951}
1952
1690e1eb
CW		 1953void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1954{
1955 i915_gem_object_unpin_fence(obj);
cc98b413 1956 i915_gem_object_unpin_from_display_plane(obj);
1690e1eb
CW		 1957}
1958
c2c75131
DV		 1959/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1960 * is assumed to be a power-of-two. */
bc752862
CW		 1961unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1962 unsigned int tiling_mode,
1963 unsigned int cpp,
1964 unsigned int pitch)
c2c75131 1965{
bc752862
CW		 1966 if (tiling_mode != I915_TILING_NONE) {
1967 unsigned int tile_rows, tiles;
c2c75131 1968
bc752862
CW		 1969 tile_rows = *y / 8;
1970 *y %= 8;
c2c75131 1971
bc752862
CW		 1972 tiles = *x / (512/cpp);
1973 *x %= 512/cpp;
1974
1975 return tile_rows * pitch * 8 + tiles * 4096;
1976 } else {
1977 unsigned int offset;
1978
1979 offset = *y * pitch + *x * cpp;
1980 *y = 0;
1981 *x = (offset & 4095) / cpp;
1982 return offset & -4096;
1983 }
c2c75131
DV		 1984}
1985
17638cd6
JB		 1986static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1987 int x, int y)
81255565
JB		 1988{
1989 struct drm_device *dev = crtc->dev;
1990 struct drm_i915_private *dev_priv = dev->dev_private;
1991 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1992 struct intel_framebuffer *intel_fb;
05394f39 1993 struct drm_i915_gem_object *obj;
81255565 1994 int plane = intel_crtc->plane;
e506a0c6 1995 unsigned long linear_offset;
81255565 1996 u32 dspcntr;
5eddb70b 1997 u32 reg;
81255565
JB		 1998
1999 switch (plane) {
2000 case 0:
2001 case 1:
2002 break;
2003 default:
84f44ce7 2004 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 2005 return -EINVAL;
2006 }
2007
2008 intel_fb = to_intel_framebuffer(fb);
2009 obj = intel_fb->obj;
81255565 2010
5eddb70b
CW		 2011 reg = DSPCNTR(plane);
2012 dspcntr = I915_READ(reg);
81255565
JB		 2013 /* Mask out pixel format bits in case we change it */
2014 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2015 switch (fb->pixel_format) {
2016 case DRM_FORMAT_C8:
81255565
JB		 2017 dspcntr |= DISPPLANE_8BPP;
2018 break;
57779d06
VS		 2019 case DRM_FORMAT_XRGB1555:
2020 case DRM_FORMAT_ARGB1555:
2021 dspcntr |= DISPPLANE_BGRX555;
81255565 2022 break;
57779d06
VS		 2023 case DRM_FORMAT_RGB565:
2024 dspcntr |= DISPPLANE_BGRX565;
2025 break;
2026 case DRM_FORMAT_XRGB8888:
2027 case DRM_FORMAT_ARGB8888:
2028 dspcntr |= DISPPLANE_BGRX888;
2029 break;
2030 case DRM_FORMAT_XBGR8888:
2031 case DRM_FORMAT_ABGR8888:
2032 dspcntr |= DISPPLANE_RGBX888;
2033 break;
2034 case DRM_FORMAT_XRGB2101010:
2035 case DRM_FORMAT_ARGB2101010:
2036 dspcntr |= DISPPLANE_BGRX101010;
2037 break;
2038 case DRM_FORMAT_XBGR2101010:
2039 case DRM_FORMAT_ABGR2101010:
2040 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2041 break;
2042 default:
baba133a 2043 BUG();
81255565 2044 }
57779d06 2045
a6c45cf0 2046 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2047 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2048 dspcntr |= DISPPLANE_TILED;
2049 else
2050 dspcntr &= ~DISPPLANE_TILED;
2051 }
2052
de1aa629
VS		 2053 if (IS_G4X(dev))
2054 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2055
5eddb70b 2056 I915_WRITE(reg, dspcntr);
81255565 2057
e506a0c6 2058 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2059
c2c75131
DV		 2060 if (INTEL_INFO(dev)->gen >= 4) {
2061 intel_crtc->dspaddr_offset =
bc752862
CW		 2062 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2063 fb->bits_per_pixel / 8,
2064 fb->pitches[0]);
c2c75131
DV		 2065 linear_offset -= intel_crtc->dspaddr_offset;
2066 } else {
e506a0c6 2067 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2068 }
e506a0c6 2069
f343c5f6
BW		 2070 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2071 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2072 fb->pitches[0]);
01f2c773 2073 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2074 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131 2075 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2076 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2077 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2078 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2079 } else
f343c5f6 2080 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2081 POSTING_READ(reg);
81255565 2082
17638cd6
JB		 2083 return 0;
2084}
2085
2086static int ironlake_update_plane(struct drm_crtc *crtc,
2087 struct drm_framebuffer *fb, int x, int y)
2088{
2089 struct drm_device *dev = crtc->dev;
2090 struct drm_i915_private *dev_priv = dev->dev_private;
2091 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2092 struct intel_framebuffer *intel_fb;
2093 struct drm_i915_gem_object *obj;
2094 int plane = intel_crtc->plane;
e506a0c6 2095 unsigned long linear_offset;
17638cd6
JB		 2096 u32 dspcntr;
2097 u32 reg;
2098
2099 switch (plane) {
2100 case 0:
2101 case 1:
27f8227b 2102 case 2:
17638cd6
JB		 2103 break;
2104 default:
84f44ce7 2105 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2106 return -EINVAL;
2107 }
2108
2109 intel_fb = to_intel_framebuffer(fb);
2110 obj = intel_fb->obj;
2111
2112 reg = DSPCNTR(plane);
2113 dspcntr = I915_READ(reg);
2114 /* Mask out pixel format bits in case we change it */
2115 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2116 switch (fb->pixel_format) {
2117 case DRM_FORMAT_C8:
17638cd6
JB		 2118 dspcntr |= DISPPLANE_8BPP;
2119 break;
57779d06
VS		 2120 case DRM_FORMAT_RGB565:
2121 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2122 break;
57779d06
VS		 2123 case DRM_FORMAT_XRGB8888:
2124 case DRM_FORMAT_ARGB8888:
2125 dspcntr |= DISPPLANE_BGRX888;
2126 break;
2127 case DRM_FORMAT_XBGR8888:
2128 case DRM_FORMAT_ABGR8888:
2129 dspcntr |= DISPPLANE_RGBX888;
2130 break;
2131 case DRM_FORMAT_XRGB2101010:
2132 case DRM_FORMAT_ARGB2101010:
2133 dspcntr |= DISPPLANE_BGRX101010;
2134 break;
2135 case DRM_FORMAT_XBGR2101010:
2136 case DRM_FORMAT_ABGR2101010:
2137 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2138 break;
2139 default:
baba133a 2140 BUG();
17638cd6
JB		 2141 }
2142
2143 if (obj->tiling_mode != I915_TILING_NONE)
2144 dspcntr |= DISPPLANE_TILED;
2145 else
2146 dspcntr &= ~DISPPLANE_TILED;
2147
1f5d76db
PZ		 2148 if (IS_HASWELL(dev))
2149 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2150 else
2151 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6
JB		 2152
2153 I915_WRITE(reg, dspcntr);
2154
e506a0c6 2155 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2156 intel_crtc->dspaddr_offset =
bc752862
CW		 2157 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2158 fb->bits_per_pixel / 8,
2159 fb->pitches[0]);
c2c75131 2160 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2161
f343c5f6
BW		 2162 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2163 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2164 fb->pitches[0]);
01f2c773 2165 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131 2166 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2167 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2168 if (IS_HASWELL(dev)) {
2169 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2170 } else {
2171 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2172 I915_WRITE(DSPLINOFF(plane), linear_offset);
2173 }
17638cd6
JB		 2174 POSTING_READ(reg);
2175
2176 return 0;
2177}
2178
2179/* Assume fb object is pinned & idle & fenced and just update base pointers */
2180static int
2181intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2182 int x, int y, enum mode_set_atomic state)
2183{
2184 struct drm_device *dev = crtc->dev;
2185 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2186
6b8e6ed0
CW		 2187 if (dev_priv->display.disable_fbc)
2188 dev_priv->display.disable_fbc(dev);
3dec0095 2189 intel_increase_pllclock(crtc);
81255565 2190
6b8e6ed0 2191 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2192}
2193
96a02917
VS		 2194void intel_display_handle_reset(struct drm_device *dev)
2195{
2196 struct drm_i915_private *dev_priv = dev->dev_private;
2197 struct drm_crtc *crtc;
2198
2199 /*
2200 * Flips in the rings have been nuked by the reset,
2201 * so complete all pending flips so that user space
2202 * will get its events and not get stuck.
2203 *
2204 * Also update the base address of all primary
2205 * planes to the the last fb to make sure we're
2206 * showing the correct fb after a reset.
2207 *
2208 * Need to make two loops over the crtcs so that we
2209 * don't try to grab a crtc mutex before the
2210 * pending_flip_queue really got woken up.
2211 */
2212
2213 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2214 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2215 enum plane plane = intel_crtc->plane;
2216
2217 intel_prepare_page_flip(dev, plane);
2218 intel_finish_page_flip_plane(dev, plane);
2219 }
2220
2221 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2222 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2223
2224 mutex_lock(&crtc->mutex);
2225 if (intel_crtc->active)
2226 dev_priv->display.update_plane(crtc, crtc->fb,
2227 crtc->x, crtc->y);
2228 mutex_unlock(&crtc->mutex);
2229 }
2230}
2231
14667a4b
CW		 2232static int
2233intel_finish_fb(struct drm_framebuffer *old_fb)
2234{
2235 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2236 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2237 bool was_interruptible = dev_priv->mm.interruptible;
2238 int ret;
2239
14667a4b
CW		 2240 /* Big Hammer, we also need to ensure that any pending
2241 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2242 * current scanout is retired before unpinning the old
2243 * framebuffer.
2244 *
2245 * This should only fail upon a hung GPU, in which case we
2246 * can safely continue.
2247 */
2248 dev_priv->mm.interruptible = false;
2249 ret = i915_gem_object_finish_gpu(obj);
2250 dev_priv->mm.interruptible = was_interruptible;
2251
2252 return ret;
2253}
2254
198598d0
VS		 2255static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2256{
2257 struct drm_device *dev = crtc->dev;
2258 struct drm_i915_master_private *master_priv;
2259 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2260
2261 if (!dev->primary->master)
2262 return;
2263
2264 master_priv = dev->primary->master->driver_priv;
2265 if (!master_priv->sarea_priv)
2266 return;
2267
2268 switch (intel_crtc->pipe) {
2269 case 0:
2270 master_priv->sarea_priv->pipeA_x = x;
2271 master_priv->sarea_priv->pipeA_y = y;
2272 break;
2273 case 1:
2274 master_priv->sarea_priv->pipeB_x = x;
2275 master_priv->sarea_priv->pipeB_y = y;
2276 break;
2277 default:
2278 break;
2279 }
2280}
2281
5c3b82e2 2282static int
3c4fdcfb 2283intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2284 struct drm_framebuffer *fb)
79e53945
JB		 2285{
2286 struct drm_device *dev = crtc->dev;
6b8e6ed0 2287 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2288 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2289 struct drm_framebuffer *old_fb;
5c3b82e2 2290 int ret;
79e53945
JB		 2291
2292 /* no fb bound */
94352cf9 2293 if (!fb) {
a5071c2f 2294 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2295 return 0;
2296 }
2297
7eb552ae 2298 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2299 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2300 plane_name(intel_crtc->plane),
2301 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2302 return -EINVAL;
79e53945
JB		 2303 }
2304
5c3b82e2 2305 mutex_lock(&dev->struct_mutex);
265db958 2306 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2307 to_intel_framebuffer(fb)->obj,
919926ae 2308 NULL);
5c3b82e2
CW		 2309 if (ret != 0) {
2310 mutex_unlock(&dev->struct_mutex);
a5071c2f 2311 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2312 return ret;
2313 }
79e53945 2314
bb2043de
DL		 2315 /*
2316 * Update pipe size and adjust fitter if needed: the reason for this is
2317 * that in compute_mode_changes we check the native mode (not the pfit
2318 * mode) to see if we can flip rather than do a full mode set. In the
2319 * fastboot case, we'll flip, but if we don't update the pipesrc and
2320 * pfit state, we'll end up with a big fb scanned out into the wrong
2321 * sized surface.
2322 *
2323 * To fix this properly, we need to hoist the checks up into
2324 * compute_mode_changes (or above), check the actual pfit state and
2325 * whether the platform allows pfit disable with pipe active, and only
2326 * then update the pipesrc and pfit state, even on the flip path.
2327 */
4d6a3e63 2328 if (i915_fastboot) {
d7bf63f2
DL		 2329 const struct drm_display_mode *adjusted_mode =
2330 &intel_crtc->config.adjusted_mode;
2331
4d6a3e63 2332 I915_WRITE(PIPESRC(intel_crtc->pipe),
d7bf63f2
DL		 2333 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2334 (adjusted_mode->crtc_vdisplay - 1));
fd4daa9c 2335 if (!intel_crtc->config.pch_pfit.enabled &&
4d6a3e63
JB		 2336 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2337 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2338 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2339 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2340 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2341 }
2342 }
2343
94352cf9 2344 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2345 if (ret) {
94352cf9 2346 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2347 mutex_unlock(&dev->struct_mutex);
a5071c2f 2348 DRM_ERROR("failed to update base address\n");
4e6cfefc 2349 return ret;
79e53945 2350 }
3c4fdcfb 2351
94352cf9
DV		 2352 old_fb = crtc->fb;
2353 crtc->fb = fb;
6c4c86f5
DV		 2354 crtc->x = x;
2355 crtc->y = y;
94352cf9 2356
b7f1de28 2357 if (old_fb) {
d7697eea
DV		 2358 if (intel_crtc->active && old_fb != fb)
2359 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2360 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2361 }
652c393a 2362
6b8e6ed0 2363 intel_update_fbc(dev);
4906557e 2364 intel_edp_psr_update(dev);
5c3b82e2 2365 mutex_unlock(&dev->struct_mutex);
79e53945 2366
198598d0 2367 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2368
2369 return 0;
79e53945
JB		 2370}
2371
5e84e1a4
ZW		 2372static void intel_fdi_normal_train(struct drm_crtc *crtc)
2373{
2374 struct drm_device *dev = crtc->dev;
2375 struct drm_i915_private *dev_priv = dev->dev_private;
2376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2377 int pipe = intel_crtc->pipe;
2378 u32 reg, temp;
2379
2380 /* enable normal train */
2381 reg = FDI_TX_CTL(pipe);
2382 temp = I915_READ(reg);
61e499bf 2383 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2384 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2385 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2386 } else {
2387 temp &= ~FDI_LINK_TRAIN_NONE;
2388 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2389 }
5e84e1a4
ZW		 2390 I915_WRITE(reg, temp);
2391
2392 reg = FDI_RX_CTL(pipe);
2393 temp = I915_READ(reg);
2394 if (HAS_PCH_CPT(dev)) {
2395 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2396 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2397 } else {
2398 temp &= ~FDI_LINK_TRAIN_NONE;
2399 temp |= FDI_LINK_TRAIN_NONE;
2400 }
2401 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2402
2403 /* wait one idle pattern time */
2404 POSTING_READ(reg);
2405 udelay(1000);
357555c0
JB		 2406
2407 /* IVB wants error correction enabled */
2408 if (IS_IVYBRIDGE(dev))
2409 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2410 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2411}
2412
1e833f40
DV		 2413static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2414{
2415 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2416}
2417
01a415fd
DV		 2418static void ivb_modeset_global_resources(struct drm_device *dev)
2419{
2420 struct drm_i915_private *dev_priv = dev->dev_private;
2421 struct intel_crtc *pipe_B_crtc =
2422 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2423 struct intel_crtc *pipe_C_crtc =
2424 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2425 uint32_t temp;
2426
1e833f40
DV		 2427 /*
2428 * When everything is off disable fdi C so that we could enable fdi B
2429 * with all lanes. Note that we don't care about enabled pipes without
2430 * an enabled pch encoder.
2431 */
2432 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2433 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2434 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2435 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2436
2437 temp = I915_READ(SOUTH_CHICKEN1);
2438 temp &= ~FDI_BC_BIFURCATION_SELECT;
2439 DRM_DEBUG_KMS("disabling fdi C rx\n");
2440 I915_WRITE(SOUTH_CHICKEN1, temp);
2441 }
2442}
2443
8db9d77b
ZW		 2444/* The FDI link training functions for ILK/Ibexpeak. */
2445static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2446{
2447 struct drm_device *dev = crtc->dev;
2448 struct drm_i915_private *dev_priv = dev->dev_private;
2449 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2450 int pipe = intel_crtc->pipe;
0fc932b8 2451 int plane = intel_crtc->plane;
5eddb70b 2452 u32 reg, temp, tries;
8db9d77b 2453
0fc932b8
JB		 2454 /* FDI needs bits from pipe & plane first */
2455 assert_pipe_enabled(dev_priv, pipe);
2456 assert_plane_enabled(dev_priv, plane);
2457
e1a44743
AJ		 2458 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2459 for train result */
5eddb70b
CW		 2460 reg = FDI_RX_IMR(pipe);
2461 temp = I915_READ(reg);
e1a44743
AJ		 2462 temp &= ~FDI_RX_SYMBOL_LOCK;
2463 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2464 I915_WRITE(reg, temp);
2465 I915_READ(reg);
e1a44743
AJ		 2466 udelay(150);
2467
8db9d77b 2468 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2469 reg = FDI_TX_CTL(pipe);
2470 temp = I915_READ(reg);
627eb5a3
DV		 2471 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2472 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2473 temp &= ~FDI_LINK_TRAIN_NONE;
2474 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2475 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2476
5eddb70b
CW		 2477 reg = FDI_RX_CTL(pipe);
2478 temp = I915_READ(reg);
8db9d77b
ZW		 2479 temp &= ~FDI_LINK_TRAIN_NONE;
2480 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2481 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2482
2483 POSTING_READ(reg);
8db9d77b
ZW		 2484 udelay(150);
2485
5b2adf89 2486 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2487 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2488 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2489 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2490
5eddb70b 2491 reg = FDI_RX_IIR(pipe);
e1a44743 2492 for (tries = 0; tries < 5; tries++) {
5eddb70b 2493 temp = I915_READ(reg);
8db9d77b
ZW		 2494 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2495
2496 if ((temp & FDI_RX_BIT_LOCK)) {
2497 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2498 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2499 break;
2500 }
8db9d77b 2501 }
e1a44743 2502 if (tries == 5)
5eddb70b 2503 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2504
2505 /* Train 2 */
5eddb70b
CW		 2506 reg = FDI_TX_CTL(pipe);
2507 temp = I915_READ(reg);
8db9d77b
ZW		 2508 temp &= ~FDI_LINK_TRAIN_NONE;
2509 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2510 I915_WRITE(reg, temp);
8db9d77b 2511
5eddb70b
CW		 2512 reg = FDI_RX_CTL(pipe);
2513 temp = I915_READ(reg);
8db9d77b
ZW		 2514 temp &= ~FDI_LINK_TRAIN_NONE;
2515 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2516 I915_WRITE(reg, temp);
8db9d77b 2517
5eddb70b
CW		 2518 POSTING_READ(reg);
2519 udelay(150);
8db9d77b 2520
5eddb70b 2521 reg = FDI_RX_IIR(pipe);
e1a44743 2522 for (tries = 0; tries < 5; tries++) {
5eddb70b 2523 temp = I915_READ(reg);
8db9d77b
ZW		 2524 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2525
2526 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2527 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2528 DRM_DEBUG_KMS("FDI train 2 done.\n");
2529 break;
2530 }
8db9d77b 2531 }
e1a44743 2532 if (tries == 5)
5eddb70b 2533 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2534
2535 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2536
8db9d77b
ZW		 2537}
2538
0206e353 2539static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2540 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2541 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2542 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2543 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2544};
2545
2546/* The FDI link training functions for SNB/Cougarpoint. */
2547static void gen6_fdi_link_train(struct drm_crtc *crtc)
2548{
2549 struct drm_device *dev = crtc->dev;
2550 struct drm_i915_private *dev_priv = dev->dev_private;
2551 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2552 int pipe = intel_crtc->pipe;
fa37d39e 2553 u32 reg, temp, i, retry;
8db9d77b 2554
e1a44743
AJ		 2555 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2556 for train result */
5eddb70b
CW		 2557 reg = FDI_RX_IMR(pipe);
2558 temp = I915_READ(reg);
e1a44743
AJ		 2559 temp &= ~FDI_RX_SYMBOL_LOCK;
2560 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2561 I915_WRITE(reg, temp);
2562
2563 POSTING_READ(reg);
e1a44743
AJ		 2564 udelay(150);
2565
8db9d77b 2566 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2567 reg = FDI_TX_CTL(pipe);
2568 temp = I915_READ(reg);
627eb5a3
DV		 2569 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2570 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2571 temp &= ~FDI_LINK_TRAIN_NONE;
2572 temp |= FDI_LINK_TRAIN_PATTERN_1;
2573 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2574 /* SNB-B */
2575 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2576 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2577
d74cf324
DV		 2578 I915_WRITE(FDI_RX_MISC(pipe),
2579 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2580
5eddb70b
CW		 2581 reg = FDI_RX_CTL(pipe);
2582 temp = I915_READ(reg);
8db9d77b
ZW		 2583 if (HAS_PCH_CPT(dev)) {
2584 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2585 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2586 } else {
2587 temp &= ~FDI_LINK_TRAIN_NONE;
2588 temp |= FDI_LINK_TRAIN_PATTERN_1;
2589 }
5eddb70b
CW		 2590 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2591
2592 POSTING_READ(reg);
8db9d77b
ZW		 2593 udelay(150);
2594
0206e353 2595 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2596 reg = FDI_TX_CTL(pipe);
2597 temp = I915_READ(reg);
8db9d77b
ZW		 2598 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2599 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2600 I915_WRITE(reg, temp);
2601
2602 POSTING_READ(reg);
8db9d77b
ZW		 2603 udelay(500);
2604
fa37d39e
SP		 2605 for (retry = 0; retry < 5; retry++) {
2606 reg = FDI_RX_IIR(pipe);
2607 temp = I915_READ(reg);
2608 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2609 if (temp & FDI_RX_BIT_LOCK) {
2610 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2611 DRM_DEBUG_KMS("FDI train 1 done.\n");
2612 break;
2613 }
2614 udelay(50);
8db9d77b 2615 }
fa37d39e
SP		 2616 if (retry < 5)
2617 break;
8db9d77b
ZW		 2618 }
2619 if (i == 4)
5eddb70b 2620 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2621
2622 /* Train 2 */
5eddb70b
CW		 2623 reg = FDI_TX_CTL(pipe);
2624 temp = I915_READ(reg);
8db9d77b
ZW		 2625 temp &= ~FDI_LINK_TRAIN_NONE;
2626 temp |= FDI_LINK_TRAIN_PATTERN_2;
2627 if (IS_GEN6(dev)) {
2628 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2629 /* SNB-B */
2630 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2631 }
5eddb70b 2632 I915_WRITE(reg, temp);
8db9d77b 2633
5eddb70b
CW		 2634 reg = FDI_RX_CTL(pipe);
2635 temp = I915_READ(reg);
8db9d77b
ZW		 2636 if (HAS_PCH_CPT(dev)) {
2637 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2638 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2639 } else {
2640 temp &= ~FDI_LINK_TRAIN_NONE;
2641 temp |= FDI_LINK_TRAIN_PATTERN_2;
2642 }
5eddb70b
CW		 2643 I915_WRITE(reg, temp);
2644
2645 POSTING_READ(reg);
8db9d77b
ZW		 2646 udelay(150);
2647
0206e353 2648 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2649 reg = FDI_TX_CTL(pipe);
2650 temp = I915_READ(reg);
8db9d77b
ZW		 2651 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2652 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2653 I915_WRITE(reg, temp);
2654
2655 POSTING_READ(reg);
8db9d77b
ZW		 2656 udelay(500);
2657
fa37d39e
SP		 2658 for (retry = 0; retry < 5; retry++) {
2659 reg = FDI_RX_IIR(pipe);
2660 temp = I915_READ(reg);
2661 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2662 if (temp & FDI_RX_SYMBOL_LOCK) {
2663 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2664 DRM_DEBUG_KMS("FDI train 2 done.\n");
2665 break;
2666 }
2667 udelay(50);
8db9d77b 2668 }
fa37d39e
SP		 2669 if (retry < 5)
2670 break;
8db9d77b
ZW		 2671 }
2672 if (i == 4)
5eddb70b 2673 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2674
2675 DRM_DEBUG_KMS("FDI train done.\n");
2676}
2677
357555c0
JB		 2678/* Manual link training for Ivy Bridge A0 parts */
2679static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2680{
2681 struct drm_device *dev = crtc->dev;
2682 struct drm_i915_private *dev_priv = dev->dev_private;
2683 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2684 int pipe = intel_crtc->pipe;
139ccd3f 2685 u32 reg, temp, i, j;
357555c0
JB		 2686
2687 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2688 for train result */
2689 reg = FDI_RX_IMR(pipe);
2690 temp = I915_READ(reg);
2691 temp &= ~FDI_RX_SYMBOL_LOCK;
2692 temp &= ~FDI_RX_BIT_LOCK;
2693 I915_WRITE(reg, temp);
2694
2695 POSTING_READ(reg);
2696 udelay(150);
2697
01a415fd
DV		 2698 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2699 I915_READ(FDI_RX_IIR(pipe)));
2700
139ccd3f
JB		 2701 /* Try each vswing and preemphasis setting twice before moving on */
2702 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2703 /* disable first in case we need to retry */
2704 reg = FDI_TX_CTL(pipe);
2705 temp = I915_READ(reg);
2706 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2707 temp &= ~FDI_TX_ENABLE;
2708 I915_WRITE(reg, temp);
357555c0 2709
139ccd3f
JB		 2710 reg = FDI_RX_CTL(pipe);
2711 temp = I915_READ(reg);
2712 temp &= ~FDI_LINK_TRAIN_AUTO;
2713 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2714 temp &= ~FDI_RX_ENABLE;
2715 I915_WRITE(reg, temp);
357555c0 2716
139ccd3f 2717 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 2718 reg = FDI_TX_CTL(pipe);
2719 temp = I915_READ(reg);
139ccd3f
JB		 2720 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2721 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2722 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 2723 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 2724 temp |= snb_b_fdi_train_param[j/2];
2725 temp |= FDI_COMPOSITE_SYNC;
2726 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 2727
139ccd3f
JB		 2728 I915_WRITE(FDI_RX_MISC(pipe),
2729 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 2730
139ccd3f 2731 reg = FDI_RX_CTL(pipe);
357555c0 2732 temp = I915_READ(reg);
139ccd3f
JB		 2733 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2734 temp |= FDI_COMPOSITE_SYNC;
2735 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 2736
139ccd3f
JB		 2737 POSTING_READ(reg);
2738 udelay(1); /* should be 0.5us */
357555c0 2739
139ccd3f
JB		 2740 for (i = 0; i < 4; i++) {
2741 reg = FDI_RX_IIR(pipe);
2742 temp = I915_READ(reg);
2743 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2744
139ccd3f
JB		 2745 if (temp & FDI_RX_BIT_LOCK ||
2746 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2747 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2748 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2749 i);
2750 break;
2751 }
2752 udelay(1); /* should be 0.5us */
2753 }
2754 if (i == 4) {
2755 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2756 continue;
2757 }
357555c0 2758
139ccd3f 2759 /* Train 2 */
357555c0
JB		 2760 reg = FDI_TX_CTL(pipe);
2761 temp = I915_READ(reg);
139ccd3f
JB		 2762 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2763 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2764 I915_WRITE(reg, temp);
2765
2766 reg = FDI_RX_CTL(pipe);
2767 temp = I915_READ(reg);
2768 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2769 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 2770 I915_WRITE(reg, temp);
2771
2772 POSTING_READ(reg);
139ccd3f 2773 udelay(2); /* should be 1.5us */
357555c0 2774
139ccd3f
JB		 2775 for (i = 0; i < 4; i++) {
2776 reg = FDI_RX_IIR(pipe);
2777 temp = I915_READ(reg);
2778 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2779
139ccd3f
JB		 2780 if (temp & FDI_RX_SYMBOL_LOCK ||
2781 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2782 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2783 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2784 i);
2785 goto train_done;
2786 }
2787 udelay(2); /* should be 1.5us */
357555c0 2788 }
139ccd3f
JB		 2789 if (i == 4)
2790 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 2791 }
357555c0 2792
139ccd3f 2793train_done:
357555c0
JB		 2794 DRM_DEBUG_KMS("FDI train done.\n");
2795}
2796
88cefb6c 2797static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2798{
88cefb6c 2799 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2800 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2801 int pipe = intel_crtc->pipe;
5eddb70b 2802 u32 reg, temp;
79e53945 2803
c64e311e 2804
c98e9dcf 2805 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2806 reg = FDI_RX_CTL(pipe);
2807 temp = I915_READ(reg);
627eb5a3
DV		 2808 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2809 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2810 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2811 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2812
2813 POSTING_READ(reg);
c98e9dcf
JB		 2814 udelay(200);
2815
2816 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2817 temp = I915_READ(reg);
2818 I915_WRITE(reg, temp | FDI_PCDCLK);
2819
2820 POSTING_READ(reg);
c98e9dcf
JB		 2821 udelay(200);
2822
20749730
PZ		 2823 /* Enable CPU FDI TX PLL, always on for Ironlake */
2824 reg = FDI_TX_CTL(pipe);
2825 temp = I915_READ(reg);
2826 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2827 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2828
20749730
PZ		 2829 POSTING_READ(reg);
2830 udelay(100);
6be4a607 2831 }
0e23b99d
JB		 2832}
2833
88cefb6c
DV		 2834static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2835{
2836 struct drm_device *dev = intel_crtc->base.dev;
2837 struct drm_i915_private *dev_priv = dev->dev_private;
2838 int pipe = intel_crtc->pipe;
2839 u32 reg, temp;
2840
2841 /* Switch from PCDclk to Rawclk */
2842 reg = FDI_RX_CTL(pipe);
2843 temp = I915_READ(reg);
2844 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2845
2846 /* Disable CPU FDI TX PLL */
2847 reg = FDI_TX_CTL(pipe);
2848 temp = I915_READ(reg);
2849 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2850
2851 POSTING_READ(reg);
2852 udelay(100);
2853
2854 reg = FDI_RX_CTL(pipe);
2855 temp = I915_READ(reg);
2856 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2857
2858 /* Wait for the clocks to turn off. */
2859 POSTING_READ(reg);
2860 udelay(100);
2861}
2862
0fc932b8
JB		 2863static void ironlake_fdi_disable(struct drm_crtc *crtc)
2864{
2865 struct drm_device *dev = crtc->dev;
2866 struct drm_i915_private *dev_priv = dev->dev_private;
2867 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2868 int pipe = intel_crtc->pipe;
2869 u32 reg, temp;
2870
2871 /* disable CPU FDI tx and PCH FDI rx */
2872 reg = FDI_TX_CTL(pipe);
2873 temp = I915_READ(reg);
2874 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2875 POSTING_READ(reg);
2876
2877 reg = FDI_RX_CTL(pipe);
2878 temp = I915_READ(reg);
2879 temp &= ~(0x7 << 16);
dfd07d72 2880 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2881 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2882
2883 POSTING_READ(reg);
2884 udelay(100);
2885
2886 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2887 if (HAS_PCH_IBX(dev)) {
2888 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2889 }
0fc932b8
JB		 2890
2891 /* still set train pattern 1 */
2892 reg = FDI_TX_CTL(pipe);
2893 temp = I915_READ(reg);
2894 temp &= ~FDI_LINK_TRAIN_NONE;
2895 temp |= FDI_LINK_TRAIN_PATTERN_1;
2896 I915_WRITE(reg, temp);
2897
2898 reg = FDI_RX_CTL(pipe);
2899 temp = I915_READ(reg);
2900 if (HAS_PCH_CPT(dev)) {
2901 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2902 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2903 } else {
2904 temp &= ~FDI_LINK_TRAIN_NONE;
2905 temp |= FDI_LINK_TRAIN_PATTERN_1;
2906 }
2907 /* BPC in FDI rx is consistent with that in PIPECONF */
2908 temp &= ~(0x07 << 16);
dfd07d72 2909 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2910 I915_WRITE(reg, temp);
2911
2912 POSTING_READ(reg);
2913 udelay(100);
2914}
2915
5bb61643
CW		 2916static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2917{
2918 struct drm_device *dev = crtc->dev;
2919 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2920 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2921 unsigned long flags;
2922 bool pending;
2923
10d83730
VS		 2924 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2925 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2926 return false;
2927
2928 spin_lock_irqsave(&dev->event_lock, flags);
2929 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2930 spin_unlock_irqrestore(&dev->event_lock, flags);
2931
2932 return pending;
2933}
2934
e6c3a2a6
CW		 2935static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2936{
0f91128d 2937 struct drm_device *dev = crtc->dev;
5bb61643 2938 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2939
2940 if (crtc->fb == NULL)
2941 return;
2942
2c10d571
DV		 2943 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2944
5bb61643
CW		 2945 wait_event(dev_priv->pending_flip_queue,
2946 !intel_crtc_has_pending_flip(crtc));
2947
0f91128d
CW		 2948 mutex_lock(&dev->struct_mutex);
2949 intel_finish_fb(crtc->fb);
2950 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2951}
2952
e615efe4
ED		 2953/* Program iCLKIP clock to the desired frequency */
2954static void lpt_program_iclkip(struct drm_crtc *crtc)
2955{
2956 struct drm_device *dev = crtc->dev;
2957 struct drm_i915_private *dev_priv = dev->dev_private;
241bfc38 2958 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
e615efe4
ED		 2959 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2960 u32 temp;
2961
09153000
DV		 2962 mutex_lock(&dev_priv->dpio_lock);
2963
e615efe4
ED		 2964 /* It is necessary to ungate the pixclk gate prior to programming
2965 * the divisors, and gate it back when it is done.
2966 */
2967 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2968
2969 /* Disable SSCCTL */
2970 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2971 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2972 SBI_SSCCTL_DISABLE,
2973 SBI_ICLK);
e615efe4
ED		 2974
2975 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 2976 if (clock == 20000) {
e615efe4
ED		 2977 auxdiv = 1;
2978 divsel = 0x41;
2979 phaseinc = 0x20;
2980 } else {
2981 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 2982 * but the adjusted_mode->crtc_clock in in KHz. To get the
2983 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 2984 * convert the virtual clock precision to KHz here for higher
2985 * precision.
2986 */
2987 u32 iclk_virtual_root_freq = 172800 * 1000;
2988 u32 iclk_pi_range = 64;
2989 u32 desired_divisor, msb_divisor_value, pi_value;
2990
12d7ceed 2991 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 2992 msb_divisor_value = desired_divisor / iclk_pi_range;
2993 pi_value = desired_divisor % iclk_pi_range;
2994
2995 auxdiv = 0;
2996 divsel = msb_divisor_value - 2;
2997 phaseinc = pi_value;
2998 }
2999
3000 /* This should not happen with any sane values */
3001 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3002 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3003 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3004 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3005
3006 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3007 clock,
e615efe4
ED		 3008 auxdiv,
3009 divsel,
3010 phasedir,
3011 phaseinc);
3012
3013 /* Program SSCDIVINTPHASE6 */
988d6ee8 3014 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3015 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3016 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3017 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3018 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3019 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3020 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3021 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3022
3023 /* Program SSCAUXDIV */
988d6ee8 3024 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3025 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3026 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3027 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3028
3029 /* Enable modulator and associated divider */
988d6ee8 3030 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3031 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3032 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3033
3034 /* Wait for initialization time */
3035 udelay(24);
3036
3037 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 3038
3039 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 3040}
3041
275f01b2
DV		 3042static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3043 enum pipe pch_transcoder)
3044{
3045 struct drm_device *dev = crtc->base.dev;
3046 struct drm_i915_private *dev_priv = dev->dev_private;
3047 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3048
3049 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3050 I915_READ(HTOTAL(cpu_transcoder)));
3051 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3052 I915_READ(HBLANK(cpu_transcoder)));
3053 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3054 I915_READ(HSYNC(cpu_transcoder)));
3055
3056 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3057 I915_READ(VTOTAL(cpu_transcoder)));
3058 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3059 I915_READ(VBLANK(cpu_transcoder)));
3060 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3061 I915_READ(VSYNC(cpu_transcoder)));
3062 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3063 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3064}
3065
f67a559d
JB		 3066/*
3067 * Enable PCH resources required for PCH ports:
3068 * - PCH PLLs
3069 * - FDI training & RX/TX
3070 * - update transcoder timings
3071 * - DP transcoding bits
3072 * - transcoder
3073 */
3074static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3075{
3076 struct drm_device *dev = crtc->dev;
3077 struct drm_i915_private *dev_priv = dev->dev_private;
3078 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3079 int pipe = intel_crtc->pipe;
ee7b9f93 3080 u32 reg, temp;
2c07245f 3081
ab9412ba 3082 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 3083
cd986abb
DV		 3084 /* Write the TU size bits before fdi link training, so that error
3085 * detection works. */
3086 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3087 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3088
c98e9dcf 3089 /* For PCH output, training FDI link */
674cf967 3090 dev_priv->display.fdi_link_train(crtc);
2c07245f 3091
3ad8a208
DV		 3092 /* We need to program the right clock selection before writing the pixel
3093 * mutliplier into the DPLL. */
303b81e0 3094 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3095 u32 sel;
4b645f14 3096
c98e9dcf 3097 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 3098 temp |= TRANS_DPLL_ENABLE(pipe);
3099 sel = TRANS_DPLLB_SEL(pipe);
a43f6e0f 3100 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 3101 temp |= sel;
3102 else
3103 temp &= ~sel;
c98e9dcf 3104 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3105 }
5eddb70b 3106
3ad8a208
DV		 3107 /* XXX: pch pll's can be enabled any time before we enable the PCH
3108 * transcoder, and we actually should do this to not upset any PCH
3109 * transcoder that already use the clock when we share it.
3110 *
3111 * Note that enable_shared_dpll tries to do the right thing, but
3112 * get_shared_dpll unconditionally resets the pll - we need that to have
3113 * the right LVDS enable sequence. */
3114 ironlake_enable_shared_dpll(intel_crtc);
3115
d9b6cb56
JB		 3116 /* set transcoder timing, panel must allow it */
3117 assert_panel_unlocked(dev_priv, pipe);
275f01b2 3118 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 3119
303b81e0 3120 intel_fdi_normal_train(crtc);
5e84e1a4 3121
c98e9dcf
JB		 3122 /* For PCH DP, enable TRANS_DP_CTL */
3123 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3124 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3125 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3126 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3127 reg = TRANS_DP_CTL(pipe);
3128 temp = I915_READ(reg);
3129 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3130 TRANS_DP_SYNC_MASK |
3131 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3132 temp |= (TRANS_DP_OUTPUT_ENABLE |
3133 TRANS_DP_ENH_FRAMING);
9325c9f0 3134 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3135
3136 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3137 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3138 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3139 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3140
3141 switch (intel_trans_dp_port_sel(crtc)) {
3142 case PCH_DP_B:
5eddb70b 3143 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3144 break;
3145 case PCH_DP_C:
5eddb70b 3146 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3147 break;
3148 case PCH_DP_D:
5eddb70b 3149 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3150 break;
3151 default:
e95d41e1 3152 BUG();
32f9d658 3153 }
2c07245f 3154
5eddb70b 3155 I915_WRITE(reg, temp);
6be4a607 3156 }
b52eb4dc 3157
b8a4f404 3158 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3159}
3160
1507e5bd
PZ		 3161static void lpt_pch_enable(struct drm_crtc *crtc)
3162{
3163 struct drm_device *dev = crtc->dev;
3164 struct drm_i915_private *dev_priv = dev->dev_private;
3165 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3166 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3167
ab9412ba 3168 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3169
8c52b5e8 3170 lpt_program_iclkip(crtc);
1507e5bd 3171
0540e488 3172 /* Set transcoder timing. */
275f01b2 3173 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3174
937bb610 3175 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3176}
3177
e2b78267 3178static void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3179{
e2b78267 3180 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 3181
3182 if (pll == NULL)
3183 return;
3184
3185 if (pll->refcount == 0) {
46edb027 3186 WARN(1, "bad %s refcount\n", pll->name);
ee7b9f93
JB		 3187 return;
3188 }
3189
f4a091c7
DV		 3190 if (--pll->refcount == 0) {
3191 WARN_ON(pll->on);
3192 WARN_ON(pll->active);
3193 }
3194
a43f6e0f 3195 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 3196}
3197
b89a1d39 3198static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3199{
e2b78267
DV		 3200 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3201 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3202 enum intel_dpll_id i;
ee7b9f93 3203
ee7b9f93 3204 if (pll) {
46edb027
DV		 3205 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3206 crtc->base.base.id, pll->name);
e2b78267 3207 intel_put_shared_dpll(crtc);
ee7b9f93
JB		 3208 }
3209
98b6bd99
DV		 3210 if (HAS_PCH_IBX(dev_priv->dev)) {
3211 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 3212 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 3213 pll = &dev_priv->shared_dplls[i];
98b6bd99 3214
46edb027
DV		 3215 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3216 crtc->base.base.id, pll->name);
98b6bd99
DV		 3217
3218 goto found;
3219 }
3220
e72f9fbf
DV		 3221 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3222 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 3223
3224 /* Only want to check enabled timings first */
3225 if (pll->refcount == 0)
3226 continue;
3227
b89a1d39
DV		 3228 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3229 sizeof(pll->hw_state)) == 0) {
46edb027 3230 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
e2b78267 3231 crtc->base.base.id,
46edb027 3232 pll->name, pll->refcount, pll->active);
ee7b9f93
JB		 3233
3234 goto found;
3235 }
3236 }
3237
3238 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 3239 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3240 pll = &dev_priv->shared_dplls[i];
ee7b9f93 3241 if (pll->refcount == 0) {
46edb027
DV		 3242 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3243 crtc->base.base.id, pll->name);
ee7b9f93
JB		 3244 goto found;
3245 }
3246 }
3247
3248 return NULL;
3249
3250found:
a43f6e0f 3251 crtc->config.shared_dpll = i;
46edb027
DV		 3252 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3253 pipe_name(crtc->pipe));
ee7b9f93 3254
cdbd2316 3255 if (pll->active == 0) {
66e985c0
DV		 3256 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3257 sizeof(pll->hw_state));
3258
46edb027 3259 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
cdbd2316 3260 WARN_ON(pll->on);
e9d6944e 3261 assert_shared_dpll_disabled(dev_priv, pll);
ee7b9f93 3262
15bdd4cf 3263 pll->mode_set(dev_priv, pll);
cdbd2316
DV		 3264 }
3265 pll->refcount++;
e04c7350 3266
ee7b9f93
JB		 3267 return pll;
3268}
3269
a1520318 3270static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3271{
3272 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3273 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3274 u32 temp;
3275
3276 temp = I915_READ(dslreg);
3277 udelay(500);
3278 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3279 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3280 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3281 }
3282}
3283
b074cec8
JB		 3284static void ironlake_pfit_enable(struct intel_crtc *crtc)
3285{
3286 struct drm_device *dev = crtc->base.dev;
3287 struct drm_i915_private *dev_priv = dev->dev_private;
3288 int pipe = crtc->pipe;
3289
fd4daa9c 3290 if (crtc->config.pch_pfit.enabled) {
b074cec8
JB		 3291 /* Force use of hard-coded filter coefficients
3292 * as some pre-programmed values are broken,
3293 * e.g. x201.
3294 */
3295 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3296 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3297 PF_PIPE_SEL_IVB(pipe));
3298 else
3299 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3300 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3301 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
d4270e57
JB		 3302 }
3303}
3304
bb53d4ae
VS		 3305static void intel_enable_planes(struct drm_crtc *crtc)
3306{
3307 struct drm_device *dev = crtc->dev;
3308 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3309 struct intel_plane *intel_plane;
3310
3311 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3312 if (intel_plane->pipe == pipe)
3313 intel_plane_restore(&intel_plane->base);
3314}
3315
3316static void intel_disable_planes(struct drm_crtc *crtc)
3317{
3318 struct drm_device *dev = crtc->dev;
3319 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3320 struct intel_plane *intel_plane;
3321
3322 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3323 if (intel_plane->pipe == pipe)
3324 intel_plane_disable(&intel_plane->base);
3325}
3326
d77e4531
PZ		 3327static void hsw_enable_ips(struct intel_crtc *crtc)
3328{
3329 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3330
3331 if (!crtc->config.ips_enabled)
3332 return;
3333
3334 /* We can only enable IPS after we enable a plane and wait for a vblank.
3335 * We guarantee that the plane is enabled by calling intel_enable_ips
3336 * only after intel_enable_plane. And intel_enable_plane already waits
3337 * for a vblank, so all we need to do here is to enable the IPS bit. */
3338 assert_plane_enabled(dev_priv, crtc->plane);
3339 I915_WRITE(IPS_CTL, IPS_ENABLE);
3340}
3341
3342static void hsw_disable_ips(struct intel_crtc *crtc)
3343{
3344 struct drm_device *dev = crtc->base.dev;
3345 struct drm_i915_private *dev_priv = dev->dev_private;
3346
3347 if (!crtc->config.ips_enabled)
3348 return;
3349
3350 assert_plane_enabled(dev_priv, crtc->plane);
3351 I915_WRITE(IPS_CTL, 0);
3352 POSTING_READ(IPS_CTL);
3353
3354 /* We need to wait for a vblank before we can disable the plane. */
3355 intel_wait_for_vblank(dev, crtc->pipe);
3356}
3357
3358/** Loads the palette/gamma unit for the CRTC with the prepared values */
3359static void intel_crtc_load_lut(struct drm_crtc *crtc)
3360{
3361 struct drm_device *dev = crtc->dev;
3362 struct drm_i915_private *dev_priv = dev->dev_private;
3363 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3364 enum pipe pipe = intel_crtc->pipe;
3365 int palreg = PALETTE(pipe);
3366 int i;
3367 bool reenable_ips = false;
3368
3369 /* The clocks have to be on to load the palette. */
3370 if (!crtc->enabled || !intel_crtc->active)
3371 return;
3372
3373 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3374 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3375 assert_dsi_pll_enabled(dev_priv);
3376 else
3377 assert_pll_enabled(dev_priv, pipe);
3378 }
3379
3380 /* use legacy palette for Ironlake */
3381 if (HAS_PCH_SPLIT(dev))
3382 palreg = LGC_PALETTE(pipe);
3383
3384 /* Workaround : Do not read or write the pipe palette/gamma data while
3385 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3386 */
3387 if (intel_crtc->config.ips_enabled &&
3388 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3389 GAMMA_MODE_MODE_SPLIT)) {
3390 hsw_disable_ips(intel_crtc);
3391 reenable_ips = true;
3392 }
3393
3394 for (i = 0; i < 256; i++) {
3395 I915_WRITE(palreg + 4 * i,
3396 (intel_crtc->lut_r[i] << 16) |
3397 (intel_crtc->lut_g[i] << 8) |
3398 intel_crtc->lut_b[i]);
3399 }
3400
3401 if (reenable_ips)
3402 hsw_enable_ips(intel_crtc);
3403}
3404
f67a559d
JB		 3405static void ironlake_crtc_enable(struct drm_crtc *crtc)
3406{
3407 struct drm_device *dev = crtc->dev;
3408 struct drm_i915_private *dev_priv = dev->dev_private;
3409 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3410 struct intel_encoder *encoder;
f67a559d
JB		 3411 int pipe = intel_crtc->pipe;
3412 int plane = intel_crtc->plane;
f67a559d 3413
08a48469
DV		 3414 WARN_ON(!crtc->enabled);
3415
f67a559d
JB		 3416 if (intel_crtc->active)
3417 return;
3418
3419 intel_crtc->active = true;
8664281b
PZ		 3420
3421 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3422 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3423
f6736a1a 3424 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 3425 if (encoder->pre_enable)
3426 encoder->pre_enable(encoder);
f67a559d 3427
5bfe2ac0 3428 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3429 /* Note: FDI PLL enabling _must_ be done before we enable the
3430 * cpu pipes, hence this is separate from all the other fdi/pch
3431 * enabling. */
88cefb6c 3432 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3433 } else {
3434 assert_fdi_tx_disabled(dev_priv, pipe);
3435 assert_fdi_rx_disabled(dev_priv, pipe);
3436 }
f67a559d 3437
b074cec8 3438 ironlake_pfit_enable(intel_crtc);
f67a559d 3439
9c54c0dd
JB		 3440 /*
3441 * On ILK+ LUT must be loaded before the pipe is running but with
3442 * clocks enabled
3443 */
3444 intel_crtc_load_lut(crtc);
3445
f37fcc2a 3446 intel_update_watermarks(crtc);
5bfe2ac0 3447 intel_enable_pipe(dev_priv, pipe,
23538ef1 3448 intel_crtc->config.has_pch_encoder, false);
f67a559d 3449 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3450 intel_enable_planes(crtc);
5c38d48c 3451 intel_crtc_update_cursor(crtc, true);
f67a559d 3452
5bfe2ac0 3453 if (intel_crtc->config.has_pch_encoder)
f67a559d 3454 ironlake_pch_enable(crtc);
c98e9dcf 3455
d1ebd816 3456 mutex_lock(&dev->struct_mutex);
bed4a673 3457 intel_update_fbc(dev);
d1ebd816
BW		 3458 mutex_unlock(&dev->struct_mutex);
3459
fa5c73b1
DV		 3460 for_each_encoder_on_crtc(dev, crtc, encoder)
3461 encoder->enable(encoder);
61b77ddd
DV		 3462
3463 if (HAS_PCH_CPT(dev))
a1520318 3464 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3465
3466 /*
3467 * There seems to be a race in PCH platform hw (at least on some
3468 * outputs) where an enabled pipe still completes any pageflip right
3469 * away (as if the pipe is off) instead of waiting for vblank. As soon
3470 * as the first vblank happend, everything works as expected. Hence just
3471 * wait for one vblank before returning to avoid strange things
3472 * happening.
3473 */
3474 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3475}
3476
42db64ef
PZ		 3477/* IPS only exists on ULT machines and is tied to pipe A. */
3478static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3479{
f5adf94e 3480 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 3481}
3482
dda9a66a
VS		 3483static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
3484{
3485 struct drm_device *dev = crtc->dev;
3486 struct drm_i915_private *dev_priv = dev->dev_private;
3487 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3488 int pipe = intel_crtc->pipe;
3489 int plane = intel_crtc->plane;
3490
3491 intel_enable_plane(dev_priv, plane, pipe);
3492 intel_enable_planes(crtc);
3493 intel_crtc_update_cursor(crtc, true);
3494
3495 hsw_enable_ips(intel_crtc);
3496
3497 mutex_lock(&dev->struct_mutex);
3498 intel_update_fbc(dev);
3499 mutex_unlock(&dev->struct_mutex);
3500}
3501
3502static void haswell_crtc_disable_planes(struct drm_crtc *crtc)
3503{
3504 struct drm_device *dev = crtc->dev;
3505 struct drm_i915_private *dev_priv = dev->dev_private;
3506 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3507 int pipe = intel_crtc->pipe;
3508 int plane = intel_crtc->plane;
3509
3510 intel_crtc_wait_for_pending_flips(crtc);
3511 drm_vblank_off(dev, pipe);
3512
3513 /* FBC must be disabled before disabling the plane on HSW. */
3514 if (dev_priv->fbc.plane == plane)
3515 intel_disable_fbc(dev);
3516
3517 hsw_disable_ips(intel_crtc);
3518
3519 intel_crtc_update_cursor(crtc, false);
3520 intel_disable_planes(crtc);
3521 intel_disable_plane(dev_priv, plane, pipe);
3522}
3523
e4916946
PZ		 3524/*
3525 * This implements the workaround described in the "notes" section of the mode
3526 * set sequence documentation. When going from no pipes or single pipe to
3527 * multiple pipes, and planes are enabled after the pipe, we need to wait at
3528 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3529 */
3530static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3531{
3532 struct drm_device *dev = crtc->base.dev;
3533 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3534
3535 /* We want to get the other_active_crtc only if there's only 1 other
3536 * active crtc. */
3537 list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3538 if (!crtc_it->active || crtc_it == crtc)
3539 continue;
3540
3541 if (other_active_crtc)
3542 return;
3543
3544 other_active_crtc = crtc_it;
3545 }
3546 if (!other_active_crtc)
3547 return;
3548
3549 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3550 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3551}
3552
4f771f10
PZ		 3553static void haswell_crtc_enable(struct drm_crtc *crtc)
3554{
3555 struct drm_device *dev = crtc->dev;
3556 struct drm_i915_private *dev_priv = dev->dev_private;
3557 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3558 struct intel_encoder *encoder;
3559 int pipe = intel_crtc->pipe;
4f771f10
PZ		 3560
3561 WARN_ON(!crtc->enabled);
3562
3563 if (intel_crtc->active)
3564 return;
3565
3566 intel_crtc->active = true;
8664281b
PZ		 3567
3568 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3569 if (intel_crtc->config.has_pch_encoder)
3570 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3571
5bfe2ac0 3572 if (intel_crtc->config.has_pch_encoder)
04945641 3573 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3574
3575 for_each_encoder_on_crtc(dev, crtc, encoder)
3576 if (encoder->pre_enable)
3577 encoder->pre_enable(encoder);
3578
1f544388 3579 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3580
b074cec8 3581 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3582
3583 /*
3584 * On ILK+ LUT must be loaded before the pipe is running but with
3585 * clocks enabled
3586 */
3587 intel_crtc_load_lut(crtc);
3588
1f544388 3589 intel_ddi_set_pipe_settings(crtc);
8228c251 3590 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3591
f37fcc2a 3592 intel_update_watermarks(crtc);
5bfe2ac0 3593 intel_enable_pipe(dev_priv, pipe,
23538ef1 3594 intel_crtc->config.has_pch_encoder, false);
42db64ef 3595
5bfe2ac0 3596 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3597 lpt_pch_enable(crtc);
4f771f10 3598
8807e55b 3599 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 3600 encoder->enable(encoder);
8807e55b
JN		 3601 intel_opregion_notify_encoder(encoder, true);
3602 }
4f771f10 3603
e4916946
PZ		 3604 /* If we change the relative order between pipe/planes enabling, we need
3605 * to change the workaround. */
3606 haswell_mode_set_planes_workaround(intel_crtc);
dda9a66a
VS		 3607 haswell_crtc_enable_planes(crtc);
3608
4f771f10
PZ		 3609 /*
3610 * There seems to be a race in PCH platform hw (at least on some
3611 * outputs) where an enabled pipe still completes any pageflip right
3612 * away (as if the pipe is off) instead of waiting for vblank. As soon
3613 * as the first vblank happend, everything works as expected. Hence just
3614 * wait for one vblank before returning to avoid strange things
3615 * happening.
3616 */
3617 intel_wait_for_vblank(dev, intel_crtc->pipe);
3618}
3619
3f8dce3a
DV		 3620static void ironlake_pfit_disable(struct intel_crtc *crtc)
3621{
3622 struct drm_device *dev = crtc->base.dev;
3623 struct drm_i915_private *dev_priv = dev->dev_private;
3624 int pipe = crtc->pipe;
3625
3626 /* To avoid upsetting the power well on haswell only disable the pfit if
3627 * it's in use. The hw state code will make sure we get this right. */
fd4daa9c 3628 if (crtc->config.pch_pfit.enabled) {
3f8dce3a
DV		 3629 I915_WRITE(PF_CTL(pipe), 0);
3630 I915_WRITE(PF_WIN_POS(pipe), 0);
3631 I915_WRITE(PF_WIN_SZ(pipe), 0);
3632 }
3633}
3634
6be4a607
JB		 3635static void ironlake_crtc_disable(struct drm_crtc *crtc)
3636{
3637 struct drm_device *dev = crtc->dev;
3638 struct drm_i915_private *dev_priv = dev->dev_private;
3639 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3640 struct intel_encoder *encoder;
6be4a607
JB		 3641 int pipe = intel_crtc->pipe;
3642 int plane = intel_crtc->plane;
5eddb70b 3643 u32 reg, temp;
b52eb4dc 3644
ef9c3aee 3645
f7abfe8b
CW		 3646 if (!intel_crtc->active)
3647 return;
3648
ea9d758d
DV		 3649 for_each_encoder_on_crtc(dev, crtc, encoder)
3650 encoder->disable(encoder);
3651
e6c3a2a6 3652 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3653 drm_vblank_off(dev, pipe);
913d8d11 3654
5c3fe8b0 3655 if (dev_priv->fbc.plane == plane)
973d04f9 3656 intel_disable_fbc(dev);
2c07245f 3657
0d5b8c61 3658 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3659 intel_disable_planes(crtc);
0d5b8c61
VS		 3660 intel_disable_plane(dev_priv, plane, pipe);
3661
d925c59a
DV		 3662 if (intel_crtc->config.has_pch_encoder)
3663 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3664
b24e7179 3665 intel_disable_pipe(dev_priv, pipe);
32f9d658 3666
3f8dce3a 3667 ironlake_pfit_disable(intel_crtc);
2c07245f 3668
bf49ec8c
DV		 3669 for_each_encoder_on_crtc(dev, crtc, encoder)
3670 if (encoder->post_disable)
3671 encoder->post_disable(encoder);
2c07245f 3672
d925c59a
DV		 3673 if (intel_crtc->config.has_pch_encoder) {
3674 ironlake_fdi_disable(crtc);
913d8d11 3675
d925c59a
DV		 3676 ironlake_disable_pch_transcoder(dev_priv, pipe);
3677 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
6be4a607 3678
d925c59a
DV		 3679 if (HAS_PCH_CPT(dev)) {
3680 /* disable TRANS_DP_CTL */
3681 reg = TRANS_DP_CTL(pipe);
3682 temp = I915_READ(reg);
3683 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3684 TRANS_DP_PORT_SEL_MASK);
3685 temp |= TRANS_DP_PORT_SEL_NONE;
3686 I915_WRITE(reg, temp);
3687
3688 /* disable DPLL_SEL */
3689 temp = I915_READ(PCH_DPLL_SEL);
11887397 3690 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 3691 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 3692 }
e3421a18 3693
d925c59a 3694 /* disable PCH DPLL */
e72f9fbf 3695 intel_disable_shared_dpll(intel_crtc);
8db9d77b 3696
d925c59a
DV		 3697 ironlake_fdi_pll_disable(intel_crtc);
3698 }
6b383a7f 3699
f7abfe8b 3700 intel_crtc->active = false;
46ba614c 3701 intel_update_watermarks(crtc);
d1ebd816
BW		 3702
3703 mutex_lock(&dev->struct_mutex);
6b383a7f 3704 intel_update_fbc(dev);
d1ebd816 3705 mutex_unlock(&dev->struct_mutex);
6be4a607 3706}
1b3c7a47 3707
4f771f10 3708static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3709{
4f771f10
PZ		 3710 struct drm_device *dev = crtc->dev;
3711 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3712 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3713 struct intel_encoder *encoder;
3714 int pipe = intel_crtc->pipe;
3b117c8f 3715 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3716
4f771f10
PZ		 3717 if (!intel_crtc->active)
3718 return;
3719
dda9a66a
VS		 3720 haswell_crtc_disable_planes(crtc);
3721
8807e55b
JN		 3722 for_each_encoder_on_crtc(dev, crtc, encoder) {
3723 intel_opregion_notify_encoder(encoder, false);
4f771f10 3724 encoder->disable(encoder);
8807e55b 3725 }
4f771f10 3726
8664281b
PZ		 3727 if (intel_crtc->config.has_pch_encoder)
3728 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3729 intel_disable_pipe(dev_priv, pipe);
3730
ad80a810 3731 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3732
3f8dce3a 3733 ironlake_pfit_disable(intel_crtc);
4f771f10 3734
1f544388 3735 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3736
3737 for_each_encoder_on_crtc(dev, crtc, encoder)
3738 if (encoder->post_disable)
3739 encoder->post_disable(encoder);
3740
88adfff1 3741 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3742 lpt_disable_pch_transcoder(dev_priv);
8664281b 3743 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3744 intel_ddi_fdi_disable(crtc);
83616634 3745 }
4f771f10
PZ		 3746
3747 intel_crtc->active = false;
46ba614c 3748 intel_update_watermarks(crtc);
4f771f10
PZ		 3749
3750 mutex_lock(&dev->struct_mutex);
3751 intel_update_fbc(dev);
3752 mutex_unlock(&dev->struct_mutex);
3753}
3754
ee7b9f93
JB		 3755static void ironlake_crtc_off(struct drm_crtc *crtc)
3756{
3757 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 3758 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 3759}
3760
6441ab5f
PZ		 3761static void haswell_crtc_off(struct drm_crtc *crtc)
3762{
3763 intel_ddi_put_crtc_pll(crtc);
3764}
3765
02e792fb
DV		 3766static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3767{
02e792fb 3768 if (!enable && intel_crtc->overlay) {
23f09ce3 3769 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3770 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3771
23f09ce3 3772 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3773 dev_priv->mm.interruptible = false;
3774 (void) intel_overlay_switch_off(intel_crtc->overlay);
3775 dev_priv->mm.interruptible = true;
23f09ce3 3776 mutex_unlock(&dev->struct_mutex);
02e792fb 3777 }
02e792fb 3778
5dcdbcb0
CW		 3779 /* Let userspace switch the overlay on again. In most cases userspace
3780 * has to recompute where to put it anyway.
3781 */
02e792fb
DV		 3782}
3783
61bc95c1
EE		 3784/**
3785 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3786 * cursor plane briefly if not already running after enabling the display
3787 * plane.
3788 * This workaround avoids occasional blank screens when self refresh is
3789 * enabled.
3790 */
3791static void
3792g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3793{
3794 u32 cntl = I915_READ(CURCNTR(pipe));
3795
3796 if ((cntl & CURSOR_MODE) == 0) {
3797 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3798
3799 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3800 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3801 intel_wait_for_vblank(dev_priv->dev, pipe);
3802 I915_WRITE(CURCNTR(pipe), cntl);
3803 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3804 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3805 }
3806}
3807
2dd24552
JB		 3808static void i9xx_pfit_enable(struct intel_crtc *crtc)
3809{
3810 struct drm_device *dev = crtc->base.dev;
3811 struct drm_i915_private *dev_priv = dev->dev_private;
3812 struct intel_crtc_config *pipe_config = &crtc->config;
3813
328d8e82 3814 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3815 return;
3816
2dd24552 3817 /*
c0b03411
DV		 3818 * The panel fitter should only be adjusted whilst the pipe is disabled,
3819 * according to register description and PRM.
2dd24552 3820 */
c0b03411
DV		 3821 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3822 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3823
b074cec8
JB		 3824 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3825 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3826
3827 /* Border color in case we don't scale up to the full screen. Black by
3828 * default, change to something else for debugging. */
3829 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3830}
3831
89b667f8
JB		 3832static void valleyview_crtc_enable(struct drm_crtc *crtc)
3833{
3834 struct drm_device *dev = crtc->dev;
3835 struct drm_i915_private *dev_priv = dev->dev_private;
3836 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3837 struct intel_encoder *encoder;
3838 int pipe = intel_crtc->pipe;
3839 int plane = intel_crtc->plane;
23538ef1 3840 bool is_dsi;
89b667f8
JB		 3841
3842 WARN_ON(!crtc->enabled);
3843
3844 if (intel_crtc->active)
3845 return;
3846
3847 intel_crtc->active = true;
89b667f8 3848
89b667f8
JB		 3849 for_each_encoder_on_crtc(dev, crtc, encoder)
3850 if (encoder->pre_pll_enable)
3851 encoder->pre_pll_enable(encoder);
3852
23538ef1
JN		 3853 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
3854
e9fd1c02
JN		 3855 if (!is_dsi)
3856 vlv_enable_pll(intel_crtc);
89b667f8
JB		 3857
3858 for_each_encoder_on_crtc(dev, crtc, encoder)
3859 if (encoder->pre_enable)
3860 encoder->pre_enable(encoder);
3861
2dd24552
JB		 3862 i9xx_pfit_enable(intel_crtc);
3863
63cbb074
VS		 3864 intel_crtc_load_lut(crtc);
3865
f37fcc2a 3866 intel_update_watermarks(crtc);
23538ef1 3867 intel_enable_pipe(dev_priv, pipe, false, is_dsi);
89b667f8 3868 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3869 intel_enable_planes(crtc);
5c38d48c 3870 intel_crtc_update_cursor(crtc, true);
89b667f8 3871
89b667f8 3872 intel_update_fbc(dev);
5004945f
JN		 3873
3874 for_each_encoder_on_crtc(dev, crtc, encoder)
3875 encoder->enable(encoder);
89b667f8
JB		 3876}
3877
0b8765c6 3878static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3879{
3880 struct drm_device *dev = crtc->dev;
79e53945
JB		 3881 struct drm_i915_private *dev_priv = dev->dev_private;
3882 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3883 struct intel_encoder *encoder;
79e53945 3884 int pipe = intel_crtc->pipe;
80824003 3885 int plane = intel_crtc->plane;
79e53945 3886
08a48469
DV		 3887 WARN_ON(!crtc->enabled);
3888
f7abfe8b
CW		 3889 if (intel_crtc->active)
3890 return;
3891
3892 intel_crtc->active = true;
6b383a7f 3893
9d6d9f19
MK		 3894 for_each_encoder_on_crtc(dev, crtc, encoder)
3895 if (encoder->pre_enable)
3896 encoder->pre_enable(encoder);
3897
f6736a1a
DV		 3898 i9xx_enable_pll(intel_crtc);
3899
2dd24552
JB		 3900 i9xx_pfit_enable(intel_crtc);
3901
63cbb074
VS		 3902 intel_crtc_load_lut(crtc);
3903
f37fcc2a 3904 intel_update_watermarks(crtc);
23538ef1 3905 intel_enable_pipe(dev_priv, pipe, false, false);
b24e7179 3906 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3907 intel_enable_planes(crtc);
22e407d7 3908 /* The fixup needs to happen before cursor is enabled */
61bc95c1
EE		 3909 if (IS_G4X(dev))
3910 g4x_fixup_plane(dev_priv, pipe);
22e407d7 3911 intel_crtc_update_cursor(crtc, true);
79e53945 3912
0b8765c6
JB		 3913 /* Give the overlay scaler a chance to enable if it's on this pipe */
3914 intel_crtc_dpms_overlay(intel_crtc, true);
ef9c3aee 3915
f440eb13 3916 intel_update_fbc(dev);
ef9c3aee 3917
fa5c73b1
DV		 3918 for_each_encoder_on_crtc(dev, crtc, encoder)
3919 encoder->enable(encoder);
0b8765c6 3920}
79e53945 3921
87476d63
DV		 3922static void i9xx_pfit_disable(struct intel_crtc *crtc)
3923{
3924 struct drm_device *dev = crtc->base.dev;
3925 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3926
328d8e82
DV		 3927 if (!crtc->config.gmch_pfit.control)
3928 return;
87476d63 3929
328d8e82 3930 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3931
328d8e82
DV		 3932 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3933 I915_READ(PFIT_CONTROL));
3934 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3935}
3936
0b8765c6
JB		 3937static void i9xx_crtc_disable(struct drm_crtc *crtc)
3938{
3939 struct drm_device *dev = crtc->dev;
3940 struct drm_i915_private *dev_priv = dev->dev_private;
3941 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3942 struct intel_encoder *encoder;
0b8765c6
JB		 3943 int pipe = intel_crtc->pipe;
3944 int plane = intel_crtc->plane;
ef9c3aee 3945
f7abfe8b
CW		 3946 if (!intel_crtc->active)
3947 return;
3948
ea9d758d
DV		 3949 for_each_encoder_on_crtc(dev, crtc, encoder)
3950 encoder->disable(encoder);
3951
0b8765c6 3952 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3953 intel_crtc_wait_for_pending_flips(crtc);
3954 drm_vblank_off(dev, pipe);
0b8765c6 3955
5c3fe8b0 3956 if (dev_priv->fbc.plane == plane)
973d04f9 3957 intel_disable_fbc(dev);
79e53945 3958
0d5b8c61
VS		 3959 intel_crtc_dpms_overlay(intel_crtc, false);
3960 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3961 intel_disable_planes(crtc);
b24e7179 3962 intel_disable_plane(dev_priv, plane, pipe);
0d5b8c61 3963
b24e7179 3964 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3965
87476d63 3966 i9xx_pfit_disable(intel_crtc);
24a1f16d 3967
89b667f8
JB		 3968 for_each_encoder_on_crtc(dev, crtc, encoder)
3969 if (encoder->post_disable)
3970 encoder->post_disable(encoder);
3971
f6071166
JB		 3972 if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3973 vlv_disable_pll(dev_priv, pipe);
3974 else if (!IS_VALLEYVIEW(dev))
e9fd1c02 3975 i9xx_disable_pll(dev_priv, pipe);
0b8765c6 3976
f7abfe8b 3977 intel_crtc->active = false;
46ba614c 3978 intel_update_watermarks(crtc);
f37fcc2a 3979
6b383a7f 3980 intel_update_fbc(dev);
0b8765c6
JB		 3981}
3982
ee7b9f93
JB		 3983static void i9xx_crtc_off(struct drm_crtc *crtc)
3984{
3985}
3986
976f8a20
DV		 3987static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3988 bool enabled)
2c07245f
ZW		 3989{
3990 struct drm_device *dev = crtc->dev;
3991 struct drm_i915_master_private *master_priv;
3992 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3993 int pipe = intel_crtc->pipe;
79e53945
JB		 3994
3995 if (!dev->primary->master)
3996 return;
3997
3998 master_priv = dev->primary->master->driver_priv;
3999 if (!master_priv->sarea_priv)
4000 return;
4001
79e53945
JB		 4002 switch (pipe) {
4003 case 0:
4004 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4005 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4006 break;
4007 case 1:
4008 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4009 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4010 break;
4011 default:
9db4a9c7 4012 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 4013 break;
4014 }
79e53945
JB		 4015}
4016
976f8a20
DV		 4017/**
4018 * Sets the power management mode of the pipe and plane.
4019 */
4020void intel_crtc_update_dpms(struct drm_crtc *crtc)
4021{
4022 struct drm_device *dev = crtc->dev;
4023 struct drm_i915_private *dev_priv = dev->dev_private;
4024 struct intel_encoder *intel_encoder;
4025 bool enable = false;
4026
4027 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4028 enable |= intel_encoder->connectors_active;
4029
4030 if (enable)
4031 dev_priv->display.crtc_enable(crtc);
4032 else
4033 dev_priv->display.crtc_disable(crtc);
4034
4035 intel_crtc_update_sarea(crtc, enable);
4036}
4037
cdd59983
CW		 4038static void intel_crtc_disable(struct drm_crtc *crtc)
4039{
cdd59983 4040 struct drm_device *dev = crtc->dev;
976f8a20 4041 struct drm_connector *connector;
ee7b9f93 4042 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 4043 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 4044
976f8a20
DV		 4045 /* crtc should still be enabled when we disable it. */
4046 WARN_ON(!crtc->enabled);
4047
4048 dev_priv->display.crtc_disable(crtc);
c77bf565 4049 intel_crtc->eld_vld = false;
976f8a20 4050 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 4051 dev_priv->display.off(crtc);
4052
931872fc 4053 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
93ce0ba6 4054 assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
931872fc 4055 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 4056
4057 if (crtc->fb) {
4058 mutex_lock(&dev->struct_mutex);
1690e1eb 4059 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 4060 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 4061 crtc->fb = NULL;
4062 }
4063
4064 /* Update computed state. */
4065 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4066 if (!connector->encoder || !connector->encoder->crtc)
4067 continue;
4068
4069 if (connector->encoder->crtc != crtc)
4070 continue;
4071
4072 connector->dpms = DRM_MODE_DPMS_OFF;
4073 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 4074 }
4075}
4076
ea5b213a 4077void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 4078{
4ef69c7a 4079 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 4080
ea5b213a
CW		 4081 drm_encoder_cleanup(encoder);
4082 kfree(intel_encoder);
7e7d76c3
JB		 4083}
4084
9237329d 4085/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 4086 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4087 * state of the entire output pipe. */
9237329d 4088static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 4089{
5ab432ef
DV		 4090 if (mode == DRM_MODE_DPMS_ON) {
4091 encoder->connectors_active = true;
4092
b2cabb0e 4093 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 4094 } else {
4095 encoder->connectors_active = false;
4096
b2cabb0e 4097 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 4098 }
79e53945
JB		 4099}
4100
0a91ca29
DV		 4101/* Cross check the actual hw state with our own modeset state tracking (and it's
4102 * internal consistency). */
b980514c 4103static void intel_connector_check_state(struct intel_connector *connector)
79e53945 4104{
0a91ca29
DV		 4105 if (connector->get_hw_state(connector)) {
4106 struct intel_encoder *encoder = connector->encoder;
4107 struct drm_crtc *crtc;
4108 bool encoder_enabled;
4109 enum pipe pipe;
4110
4111 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4112 connector->base.base.id,
4113 drm_get_connector_name(&connector->base));
4114
4115 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4116 "wrong connector dpms state\n");
4117 WARN(connector->base.encoder != &encoder->base,
4118 "active connector not linked to encoder\n");
4119 WARN(!encoder->connectors_active,
4120 "encoder->connectors_active not set\n");
4121
4122 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4123 WARN(!encoder_enabled, "encoder not enabled\n");
4124 if (WARN_ON(!encoder->base.crtc))
4125 return;
4126
4127 crtc = encoder->base.crtc;
4128
4129 WARN(!crtc->enabled, "crtc not enabled\n");
4130 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4131 WARN(pipe != to_intel_crtc(crtc)->pipe,
4132 "encoder active on the wrong pipe\n");
4133 }
79e53945
JB		 4134}
4135
5ab432ef
DV		 4136/* Even simpler default implementation, if there's really no special case to
4137 * consider. */
4138void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 4139{
5ab432ef 4140 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 4141
5ab432ef
DV		 4142 /* All the simple cases only support two dpms states. */
4143 if (mode != DRM_MODE_DPMS_ON)
4144 mode = DRM_MODE_DPMS_OFF;
d4270e57 4145
5ab432ef
DV		 4146 if (mode == connector->dpms)
4147 return;
4148
4149 connector->dpms = mode;
4150
4151 /* Only need to change hw state when actually enabled */
4152 if (encoder->base.crtc)
4153 intel_encoder_dpms(encoder, mode);
4154 else
8af6cf88 4155 WARN_ON(encoder->connectors_active != false);
0a91ca29 4156
b980514c 4157 intel_modeset_check_state(connector->dev);
79e53945
JB		 4158}
4159
f0947c37
DV		 4160/* Simple connector->get_hw_state implementation for encoders that support only
4161 * one connector and no cloning and hence the encoder state determines the state
4162 * of the connector. */
4163bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 4164{
24929352 4165 enum pipe pipe = 0;
f0947c37 4166 struct intel_encoder *encoder = connector->encoder;
ea5b213a 4167
f0947c37 4168 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 4169}
4170
1857e1da
DV		 4171static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4172 struct intel_crtc_config *pipe_config)
4173{
4174 struct drm_i915_private *dev_priv = dev->dev_private;
4175 struct intel_crtc *pipe_B_crtc =
4176 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4177
4178 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4179 pipe_name(pipe), pipe_config->fdi_lanes);
4180 if (pipe_config->fdi_lanes > 4) {
4181 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4182 pipe_name(pipe), pipe_config->fdi_lanes);
4183 return false;
4184 }
4185
4186 if (IS_HASWELL(dev)) {
4187 if (pipe_config->fdi_lanes > 2) {
4188 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4189 pipe_config->fdi_lanes);
4190 return false;
4191 } else {
4192 return true;
4193 }
4194 }
4195
4196 if (INTEL_INFO(dev)->num_pipes == 2)
4197 return true;
4198
4199 /* Ivybridge 3 pipe is really complicated */
4200 switch (pipe) {
4201 case PIPE_A:
4202 return true;
4203 case PIPE_B:
4204 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4205 pipe_config->fdi_lanes > 2) {
4206 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4207 pipe_name(pipe), pipe_config->fdi_lanes);
4208 return false;
4209 }
4210 return true;
4211 case PIPE_C:
1e833f40 4212 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 4213 pipe_B_crtc->config.fdi_lanes <= 2) {
4214 if (pipe_config->fdi_lanes > 2) {
4215 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4216 pipe_name(pipe), pipe_config->fdi_lanes);
4217 return false;
4218 }
4219 } else {
4220 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4221 return false;
4222 }
4223 return true;
4224 default:
4225 BUG();
4226 }
4227}
4228
e29c22c0
DV		 4229#define RETRY 1
4230static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4231 struct intel_crtc_config *pipe_config)
877d48d5 4232{
1857e1da 4233 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 4234 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 4235 int lane, link_bw, fdi_dotclock;
e29c22c0 4236 bool setup_ok, needs_recompute = false;
877d48d5 4237
e29c22c0 4238retry:
877d48d5
DV		 4239 /* FDI is a binary signal running at ~2.7GHz, encoding
4240 * each output octet as 10 bits. The actual frequency
4241 * is stored as a divider into a 100MHz clock, and the
4242 * mode pixel clock is stored in units of 1KHz.
4243 * Hence the bw of each lane in terms of the mode signal
4244 * is:
4245 */
4246 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4247
241bfc38 4248 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 4249
2bd89a07 4250 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 4251 pipe_config->pipe_bpp);
4252
4253 pipe_config->fdi_lanes = lane;
4254
2bd89a07 4255 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4256 link_bw, &pipe_config->fdi_m_n);
1857e1da 4257
e29c22c0
DV		 4258 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4259 intel_crtc->pipe, pipe_config);
4260 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4261 pipe_config->pipe_bpp -= 2*3;
4262 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4263 pipe_config->pipe_bpp);
4264 needs_recompute = true;
4265 pipe_config->bw_constrained = true;
4266
4267 goto retry;
4268 }
4269
4270 if (needs_recompute)
4271 return RETRY;
4272
4273 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4274}
4275
42db64ef
PZ		 4276static void hsw_compute_ips_config(struct intel_crtc *crtc,
4277 struct intel_crtc_config *pipe_config)
4278{
3c4ca58c
PZ		 4279 pipe_config->ips_enabled = i915_enable_ips &&
4280 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 4281 pipe_config->pipe_bpp <= 24;
42db64ef
PZ		 4282}
4283
a43f6e0f 4284static int intel_crtc_compute_config(struct intel_crtc *crtc,
e29c22c0 4285 struct intel_crtc_config *pipe_config)
79e53945 4286{
a43f6e0f 4287 struct drm_device *dev = crtc->base.dev;
b8cecdf5 4288 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4289
ad3a4479 4290 /* FIXME should check pixel clock limits on all platforms */
cf532bb2
VS		 4291 if (INTEL_INFO(dev)->gen < 4) {
4292 struct drm_i915_private *dev_priv = dev->dev_private;
4293 int clock_limit =
4294 dev_priv->display.get_display_clock_speed(dev);
4295
4296 /*
4297 * Enable pixel doubling when the dot clock
4298 * is > 90% of the (display) core speed.
4299 *
b397c96b
VS		 4300 * GDG double wide on either pipe,
4301 * otherwise pipe A only.
cf532bb2 4302 */
b397c96b 4303 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 4304 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 4305 clock_limit *= 2;
cf532bb2 4306 pipe_config->double_wide = true;
ad3a4479
VS		 4307 }
4308
241bfc38 4309 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 4310 return -EINVAL;
2c07245f 4311 }
89749350 4312
1d1d0e27
VS		 4313 /*
4314 * Pipe horizontal size must be even in:
4315 * - DVO ganged mode
4316 * - LVDS dual channel mode
4317 * - Double wide pipe
4318 */
4319 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4320 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4321 pipe_config->pipe_src_w &= ~1;
4322
8693a824
DL		 4323 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4324 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4325 */
4326 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4327 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4328 return -EINVAL;
44f46b42 4329
bd080ee5 4330 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4331 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4332 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4333 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4334 * for lvds. */
4335 pipe_config->pipe_bpp = 8*3;
4336 }
4337
f5adf94e 4338 if (HAS_IPS(dev))
a43f6e0f
DV		 4339 hsw_compute_ips_config(crtc, pipe_config);
4340
4341 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4342 * clock survives for now. */
4343 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4344 pipe_config->shared_dpll = crtc->config.shared_dpll;
42db64ef 4345
877d48d5 4346 if (pipe_config->has_pch_encoder)
a43f6e0f 4347 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 4348
e29c22c0 4349 return 0;
79e53945
JB		 4350}
4351
25eb05fc
JB		 4352static int valleyview_get_display_clock_speed(struct drm_device *dev)
4353{
4354 return 400000; /* FIXME */
4355}
4356
e70236a8
JB		 4357static int i945_get_display_clock_speed(struct drm_device *dev)
4358{
4359 return 400000;
4360}
79e53945 4361
e70236a8 4362static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4363{
e70236a8
JB		 4364 return 333000;
4365}
79e53945 4366
e70236a8
JB		 4367static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4368{
4369 return 200000;
4370}
79e53945 4371
257a7ffc
DV		 4372static int pnv_get_display_clock_speed(struct drm_device *dev)
4373{
4374 u16 gcfgc = 0;
4375
4376 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4377
4378 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4379 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4380 return 267000;
4381 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4382 return 333000;
4383 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4384 return 444000;
4385 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4386 return 200000;
4387 default:
4388 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4389 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4390 return 133000;
4391 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4392 return 167000;
4393 }
4394}
4395
e70236a8
JB		 4396static int i915gm_get_display_clock_speed(struct drm_device *dev)
4397{
4398 u16 gcfgc = 0;
79e53945 4399
e70236a8
JB		 4400 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4401
4402 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4403 return 133000;
4404 else {
4405 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4406 case GC_DISPLAY_CLOCK_333_MHZ:
4407 return 333000;
4408 default:
4409 case GC_DISPLAY_CLOCK_190_200_MHZ:
4410 return 190000;
79e53945 4411 }
e70236a8
JB		 4412 }
4413}
4414
4415static int i865_get_display_clock_speed(struct drm_device *dev)
4416{
4417 return 266000;
4418}
4419
4420static int i855_get_display_clock_speed(struct drm_device *dev)
4421{
4422 u16 hpllcc = 0;
4423 /* Assume that the hardware is in the high speed state. This
4424 * should be the default.
4425 */
4426 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4427 case GC_CLOCK_133_200:
4428 case GC_CLOCK_100_200:
4429 return 200000;
4430 case GC_CLOCK_166_250:
4431 return 250000;
4432 case GC_CLOCK_100_133:
79e53945 4433 return 133000;
e70236a8 4434 }
79e53945 4435
e70236a8
JB		 4436 /* Shouldn't happen */
4437 return 0;
4438}
79e53945 4439
e70236a8
JB		 4440static int i830_get_display_clock_speed(struct drm_device *dev)
4441{
4442 return 133000;
79e53945
JB		 4443}
4444
2c07245f 4445static void
a65851af 4446intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4447{
a65851af
VS		 4448 while (*num > DATA_LINK_M_N_MASK ||
4449 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4450 *num >>= 1;
4451 *den >>= 1;
4452 }
4453}
4454
a65851af
VS		 4455static void compute_m_n(unsigned int m, unsigned int n,
4456 uint32_t *ret_m, uint32_t *ret_n)
4457{
4458 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4459 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4460 intel_reduce_m_n_ratio(ret_m, ret_n);
4461}
4462
e69d0bc1
DV		 4463void
4464intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4465 int pixel_clock, int link_clock,
4466 struct intel_link_m_n *m_n)
2c07245f 4467{
e69d0bc1 4468 m_n->tu = 64;
a65851af
VS		 4469
4470 compute_m_n(bits_per_pixel * pixel_clock,
4471 link_clock * nlanes * 8,
4472 &m_n->gmch_m, &m_n->gmch_n);
4473
4474 compute_m_n(pixel_clock, link_clock,
4475 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4476}
4477
a7615030
CW		 4478static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4479{
72bbe58c
KP		 4480 if (i915_panel_use_ssc >= 0)
4481 return i915_panel_use_ssc != 0;
41aa3448 4482 return dev_priv->vbt.lvds_use_ssc
435793df 4483 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4484}
4485
c65d77d8
JB		 4486static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4487{
4488 struct drm_device *dev = crtc->dev;
4489 struct drm_i915_private *dev_priv = dev->dev_private;
4490 int refclk;
4491
a0c4da24 4492 if (IS_VALLEYVIEW(dev)) {
9a0ea498 4493 refclk = 100000;
a0c4da24 4494 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4495 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4496 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4497 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4498 refclk / 1000);
4499 } else if (!IS_GEN2(dev)) {
4500 refclk = 96000;
4501 } else {
4502 refclk = 48000;
4503 }
4504
4505 return refclk;
4506}
4507
7429e9d4 4508static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 4509{
7df00d7a 4510 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 4511}
f47709a9 4512
7429e9d4
DV		 4513static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4514{
4515 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 4516}
4517
f47709a9 4518static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4519 intel_clock_t *reduced_clock)
4520{
f47709a9 4521 struct drm_device *dev = crtc->base.dev;
a7516a05 4522 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4523 int pipe = crtc->pipe;
a7516a05
JB		 4524 u32 fp, fp2 = 0;
4525
4526 if (IS_PINEVIEW(dev)) {
7429e9d4 4527 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4528 if (reduced_clock)
7429e9d4 4529 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4530 } else {
7429e9d4 4531 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4532 if (reduced_clock)
7429e9d4 4533 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4534 }
4535
4536 I915_WRITE(FP0(pipe), fp);
8bcc2795 4537 crtc->config.dpll_hw_state.fp0 = fp;
a7516a05 4538
f47709a9
DV		 4539 crtc->lowfreq_avail = false;
4540 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4541 reduced_clock && i915_powersave) {
4542 I915_WRITE(FP1(pipe), fp2);
8bcc2795 4543 crtc->config.dpll_hw_state.fp1 = fp2;
f47709a9 4544 crtc->lowfreq_avail = true;
a7516a05
JB		 4545 } else {
4546 I915_WRITE(FP1(pipe), fp);
8bcc2795 4547 crtc->config.dpll_hw_state.fp1 = fp;
a7516a05
JB		 4548 }
4549}
4550
5e69f97f
CML		 4551static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4552 pipe)
89b667f8
JB		 4553{
4554 u32 reg_val;
4555
4556 /*
4557 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4558 * and set it to a reasonable value instead.
4559 */
5e69f97f 4560 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
89b667f8
JB		 4561 reg_val &= 0xffffff00;
4562 reg_val |= 0x00000030;
5e69f97f 4563 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
89b667f8 4564
5e69f97f 4565 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
89b667f8
JB		 4566 reg_val &= 0x8cffffff;
4567 reg_val = 0x8c000000;
5e69f97f 4568 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
89b667f8 4569
5e69f97f 4570 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
89b667f8 4571 reg_val &= 0xffffff00;
5e69f97f 4572 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
89b667f8 4573
5e69f97f 4574 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
89b667f8
JB		 4575 reg_val &= 0x00ffffff;
4576 reg_val |= 0xb0000000;
5e69f97f 4577 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4578}
4579
b551842d
DV		 4580static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4581 struct intel_link_m_n *m_n)
4582{
4583 struct drm_device *dev = crtc->base.dev;
4584 struct drm_i915_private *dev_priv = dev->dev_private;
4585 int pipe = crtc->pipe;
4586
e3b95f1e
DV		 4587 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4588 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4589 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4590 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4591}
4592
4593static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4594 struct intel_link_m_n *m_n)
4595{
4596 struct drm_device *dev = crtc->base.dev;
4597 struct drm_i915_private *dev_priv = dev->dev_private;
4598 int pipe = crtc->pipe;
4599 enum transcoder transcoder = crtc->config.cpu_transcoder;
4600
4601 if (INTEL_INFO(dev)->gen >= 5) {
4602 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4603 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4604 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4605 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4606 } else {
e3b95f1e
DV		 4607 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4608 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4609 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4610 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4611 }
4612}
4613
03afc4a2
DV		 4614static void intel_dp_set_m_n(struct intel_crtc *crtc)
4615{
4616 if (crtc->config.has_pch_encoder)
4617 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4618 else
4619 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4620}
4621
f47709a9 4622static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4623{
f47709a9 4624 struct drm_device *dev = crtc->base.dev;
a0c4da24 4625 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4626 int pipe = crtc->pipe;
89b667f8 4627 u32 dpll, mdiv;
a0c4da24 4628 u32 bestn, bestm1, bestm2, bestp1, bestp2;
198a037f 4629 u32 coreclk, reg_val, dpll_md;
a0c4da24 4630
09153000
DV		 4631 mutex_lock(&dev_priv->dpio_lock);
4632
f47709a9
DV		 4633 bestn = crtc->config.dpll.n;
4634 bestm1 = crtc->config.dpll.m1;
4635 bestm2 = crtc->config.dpll.m2;
4636 bestp1 = crtc->config.dpll.p1;
4637 bestp2 = crtc->config.dpll.p2;
a0c4da24 4638
89b667f8
JB		 4639 /* See eDP HDMI DPIO driver vbios notes doc */
4640
4641 /* PLL B needs special handling */
4642 if (pipe)
5e69f97f 4643 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 4644
4645 /* Set up Tx target for periodic Rcomp update */
5e69f97f 4646 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4647
4648 /* Disable target IRef on PLL */
5e69f97f 4649 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe));
89b667f8 4650 reg_val &= 0x00ffffff;
5e69f97f 4651 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4652
4653 /* Disable fast lock */
5e69f97f 4654 vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4655
4656 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4657 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4658 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4659 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4660 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4661
4662 /*
4663 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4664 * but we don't support that).
4665 * Note: don't use the DAC post divider as it seems unstable.
4666 */
4667 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5e69f97f 4668 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
a0c4da24 4669
a0c4da24 4670 mdiv |= DPIO_ENABLE_CALIBRATION;
5e69f97f 4671 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
a0c4da24 4672
89b667f8 4673 /* Set HBR and RBR LPF coefficients */
ff9a6750 4674 if (crtc->config.port_clock == 162000 ||
99750bd4 4675 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
89b667f8 4676 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5e69f97f 4677 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
885b0120 4678 0x009f0003);
89b667f8 4679 else
5e69f97f 4680 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
89b667f8
JB		 4681 0x00d0000f);
4682
4683 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4684 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4685 /* Use SSC source */
4686 if (!pipe)
5e69f97f 4687 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4688 0x0df40000);
4689 else
5e69f97f 4690 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4691 0x0df70000);
4692 } else { /* HDMI or VGA */
4693 /* Use bend source */
4694 if (!pipe)
5e69f97f 4695 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4696 0x0df70000);
4697 else
5e69f97f 4698 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4699 0x0df40000);
4700 }
a0c4da24 4701
5e69f97f 4702 coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4703 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4704 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4705 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4706 coreclk |= 0x01000000;
5e69f97f 4707 vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4708
5e69f97f 4709 vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4710
89b667f8
JB		 4711 /* Enable DPIO clock input */
4712 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4713 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
f6071166
JB		 4714 /* We should never disable this, set it here for state tracking */
4715 if (pipe == PIPE_B)
89b667f8 4716 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
a0c4da24 4717 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4718 crtc->config.dpll_hw_state.dpll = dpll;
4719
ef1b460d
DV		 4720 dpll_md = (crtc->config.pixel_multiplier - 1)
4721 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795
DV		 4722 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4723
89b667f8
JB		 4724 if (crtc->config.has_dp_encoder)
4725 intel_dp_set_m_n(crtc);
09153000
DV		 4726
4727 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4728}
4729
f47709a9
DV		 4730static void i9xx_update_pll(struct intel_crtc *crtc,
4731 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4732 int num_connectors)
4733{
f47709a9 4734 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4735 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 4736 u32 dpll;
4737 bool is_sdvo;
f47709a9 4738 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4739
f47709a9 4740 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4741
f47709a9
DV		 4742 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4743 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4744
4745 dpll = DPLL_VGA_MODE_DIS;
4746
f47709a9 4747 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4748 dpll |= DPLLB_MODE_LVDS;
4749 else
4750 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4751
ef1b460d 4752 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
198a037f
DV		 4753 dpll |= (crtc->config.pixel_multiplier - 1)
4754 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4755 }
198a037f
DV		 4756
4757 if (is_sdvo)
4a33e48d 4758 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 4759
f47709a9 4760 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4a33e48d 4761 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 4762
4763 /* compute bitmask from p1 value */
4764 if (IS_PINEVIEW(dev))
4765 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4766 else {
4767 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4768 if (IS_G4X(dev) && reduced_clock)
4769 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4770 }
4771 switch (clock->p2) {
4772 case 5:
4773 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4774 break;
4775 case 7:
4776 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4777 break;
4778 case 10:
4779 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4780 break;
4781 case 14:
4782 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4783 break;
4784 }
4785 if (INTEL_INFO(dev)->gen >= 4)
4786 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4787
09ede541 4788 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4789 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4790 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4791 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4792 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4793 else
4794 dpll |= PLL_REF_INPUT_DREFCLK;
4795
4796 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4797 crtc->config.dpll_hw_state.dpll = dpll;
4798
eb1cbe48 4799 if (INTEL_INFO(dev)->gen >= 4) {
ef1b460d
DV		 4800 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4801 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795 4802 crtc->config.dpll_hw_state.dpll_md = dpll_md;
eb1cbe48 4803 }
66e3d5c0
DV		 4804
4805 if (crtc->config.has_dp_encoder)
4806 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4807}
4808
f47709a9 4809static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 4810 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4811 int num_connectors)
4812{
f47709a9 4813 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4814 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 4815 u32 dpll;
f47709a9 4816 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4817
f47709a9 4818 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4819
eb1cbe48
DV		 4820 dpll = DPLL_VGA_MODE_DIS;
4821
f47709a9 4822 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4823 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4824 } else {
4825 if (clock->p1 == 2)
4826 dpll |= PLL_P1_DIVIDE_BY_TWO;
4827 else
4828 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4829 if (clock->p2 == 4)
4830 dpll |= PLL_P2_DIVIDE_BY_4;
4831 }
4832
4a33e48d
DV		 4833 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4834 dpll |= DPLL_DVO_2X_MODE;
4835
f47709a9 4836 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4837 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4838 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4839 else
4840 dpll |= PLL_REF_INPUT_DREFCLK;
4841
4842 dpll |= DPLL_VCO_ENABLE;
8bcc2795 4843 crtc->config.dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 4844}
4845
8a654f3b 4846static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 4847{
4848 struct drm_device *dev = intel_crtc->base.dev;
4849 struct drm_i915_private *dev_priv = dev->dev_private;
4850 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4851 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV		 4852 struct drm_display_mode *adjusted_mode =
4853 &intel_crtc->config.adjusted_mode;
4d8a62ea
DV		 4854 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4855
4856 /* We need to be careful not to changed the adjusted mode, for otherwise
4857 * the hw state checker will get angry at the mismatch. */
4858 crtc_vtotal = adjusted_mode->crtc_vtotal;
4859 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4860
4861 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4862 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4863 crtc_vtotal -= 1;
4864 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4865 vsyncshift = adjusted_mode->crtc_hsync_start
4866 - adjusted_mode->crtc_htotal / 2;
4867 } else {
4868 vsyncshift = 0;
4869 }
4870
4871 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4872 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4873
fe2b8f9d 4874 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4875 (adjusted_mode->crtc_hdisplay - 1) |
4876 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4877 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4878 (adjusted_mode->crtc_hblank_start - 1) |
4879 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4880 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4881 (adjusted_mode->crtc_hsync_start - 1) |
4882 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4883
fe2b8f9d 4884 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4885 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4886 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4887 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4888 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4889 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4890 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4891 (adjusted_mode->crtc_vsync_start - 1) |
4892 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4893
b5e508d4
PZ		 4894 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4895 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4896 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4897 * bits. */
4898 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4899 (pipe == PIPE_B || pipe == PIPE_C))
4900 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4901
b0e77b9c
PZ		 4902 /* pipesrc controls the size that is scaled from, which should
4903 * always be the user's requested size.
4904 */
4905 I915_WRITE(PIPESRC(pipe),
37327abd
VS		 4906 ((intel_crtc->config.pipe_src_w - 1) << 16) |
4907 (intel_crtc->config.pipe_src_h - 1));
b0e77b9c
PZ		 4908}
4909
1bd1bd80
DV		 4910static void intel_get_pipe_timings(struct intel_crtc *crtc,
4911 struct intel_crtc_config *pipe_config)
4912{
4913 struct drm_device *dev = crtc->base.dev;
4914 struct drm_i915_private *dev_priv = dev->dev_private;
4915 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4916 uint32_t tmp;
4917
4918 tmp = I915_READ(HTOTAL(cpu_transcoder));
4919 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4920 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4921 tmp = I915_READ(HBLANK(cpu_transcoder));
4922 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4923 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4924 tmp = I915_READ(HSYNC(cpu_transcoder));
4925 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4926 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4927
4928 tmp = I915_READ(VTOTAL(cpu_transcoder));
4929 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4930 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4931 tmp = I915_READ(VBLANK(cpu_transcoder));
4932 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4933 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4934 tmp = I915_READ(VSYNC(cpu_transcoder));
4935 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4936 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4937
4938 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4939 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4940 pipe_config->adjusted_mode.crtc_vtotal += 1;
4941 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4942 }
4943
4944 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 4945 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
4946 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
4947
4948 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
4949 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 4950}
4951
babea61d
JB		 4952static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4953 struct intel_crtc_config *pipe_config)
4954{
4955 struct drm_crtc *crtc = &intel_crtc->base;
4956
4957 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4958 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4959 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4960 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4961
4962 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4963 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4964 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4965 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4966
4967 crtc->mode.flags = pipe_config->adjusted_mode.flags;
4968
241bfc38 4969 crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock;
babea61d
JB		 4970 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4971}
4972
84b046f3
DV		 4973static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4974{
4975 struct drm_device *dev = intel_crtc->base.dev;
4976 struct drm_i915_private *dev_priv = dev->dev_private;
4977 uint32_t pipeconf;
4978
9f11a9e4 4979 pipeconf = 0;
84b046f3 4980
67c72a12
DV		 4981 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
4982 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
4983 pipeconf |= PIPECONF_ENABLE;
4984
cf532bb2
VS		 4985 if (intel_crtc->config.double_wide)
4986 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 4987
ff9ce46e
DV		 4988 /* only g4x and later have fancy bpc/dither controls */
4989 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e
DV		 4990 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4991 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4992 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4993 PIPECONF_DITHER_TYPE_SP;
84b046f3 4994
ff9ce46e
DV		 4995 switch (intel_crtc->config.pipe_bpp) {
4996 case 18:
4997 pipeconf |= PIPECONF_6BPC;
4998 break;
4999 case 24:
5000 pipeconf |= PIPECONF_8BPC;
5001 break;
5002 case 30:
5003 pipeconf |= PIPECONF_10BPC;
5004 break;
5005 default:
5006 /* Case prevented by intel_choose_pipe_bpp_dither. */
5007 BUG();
84b046f3
DV		 5008 }
5009 }
5010
5011 if (HAS_PIPE_CXSR(dev)) {
5012 if (intel_crtc->lowfreq_avail) {
5013 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5014 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5015 } else {
5016 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 5017 }
5018 }
5019
84b046f3
DV		 5020 if (!IS_GEN2(dev) &&
5021 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5022 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5023 else
5024 pipeconf |= PIPECONF_PROGRESSIVE;
5025
9f11a9e4
DV		 5026 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5027 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 5028
84b046f3
DV		 5029 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5030 POSTING_READ(PIPECONF(intel_crtc->pipe));
5031}
5032
f564048e 5033static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 5034 int x, int y,
94352cf9 5035 struct drm_framebuffer *fb)
79e53945
JB		 5036{
5037 struct drm_device *dev = crtc->dev;
5038 struct drm_i915_private *dev_priv = dev->dev_private;
5039 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5040 int pipe = intel_crtc->pipe;
80824003 5041 int plane = intel_crtc->plane;
c751ce4f 5042 int refclk, num_connectors = 0;
652c393a 5043 intel_clock_t clock, reduced_clock;
84b046f3 5044 u32 dspcntr;
a16af721 5045 bool ok, has_reduced_clock = false;
e9fd1c02 5046 bool is_lvds = false, is_dsi = false;
5eddb70b 5047 struct intel_encoder *encoder;
d4906093 5048 const intel_limit_t *limit;
5c3b82e2 5049 int ret;
79e53945 5050
6c2b7c12 5051 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 5052 switch (encoder->type) {
79e53945
JB		 5053 case INTEL_OUTPUT_LVDS:
5054 is_lvds = true;
5055 break;
e9fd1c02
JN		 5056 case INTEL_OUTPUT_DSI:
5057 is_dsi = true;
5058 break;
79e53945 5059 }
43565a06 5060
c751ce4f 5061 num_connectors++;
79e53945
JB		 5062 }
5063
f2335330
JN		 5064 if (is_dsi)
5065 goto skip_dpll;
5066
5067 if (!intel_crtc->config.clock_set) {
5068 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 5069
e9fd1c02
JN		 5070 /*
5071 * Returns a set of divisors for the desired target clock with
5072 * the given refclk, or FALSE. The returned values represent
5073 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5074 * 2) / p1 / p2.
5075 */
5076 limit = intel_limit(crtc, refclk);
5077 ok = dev_priv->display.find_dpll(limit, crtc,
5078 intel_crtc->config.port_clock,
5079 refclk, NULL, &clock);
f2335330 5080 if (!ok) {
e9fd1c02
JN		 5081 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5082 return -EINVAL;
5083 }
79e53945 5084
f2335330
JN		 5085 if (is_lvds && dev_priv->lvds_downclock_avail) {
5086 /*
5087 * Ensure we match the reduced clock's P to the target
5088 * clock. If the clocks don't match, we can't switch
5089 * the display clock by using the FP0/FP1. In such case
5090 * we will disable the LVDS downclock feature.
5091 */
5092 has_reduced_clock =
5093 dev_priv->display.find_dpll(limit, crtc,
5094 dev_priv->lvds_downclock,
5095 refclk, &clock,
5096 &reduced_clock);
5097 }
5098 /* Compat-code for transition, will disappear. */
f47709a9
DV		 5099 intel_crtc->config.dpll.n = clock.n;
5100 intel_crtc->config.dpll.m1 = clock.m1;
5101 intel_crtc->config.dpll.m2 = clock.m2;
5102 intel_crtc->config.dpll.p1 = clock.p1;
5103 intel_crtc->config.dpll.p2 = clock.p2;
5104 }
7026d4ac 5105
e9fd1c02 5106 if (IS_GEN2(dev)) {
8a654f3b 5107 i8xx_update_pll(intel_crtc,
2a8f64ca
VP		 5108 has_reduced_clock ? &reduced_clock : NULL,
5109 num_connectors);
e9fd1c02 5110 } else if (IS_VALLEYVIEW(dev)) {
f2335330 5111 vlv_update_pll(intel_crtc);
e9fd1c02 5112 } else {
f47709a9 5113 i9xx_update_pll(intel_crtc,
eb1cbe48 5114 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 5115 num_connectors);
e9fd1c02 5116 }
79e53945 5117
f2335330 5118skip_dpll:
79e53945
JB		 5119 /* Set up the display plane register */
5120 dspcntr = DISPPLANE_GAMMA_ENABLE;
5121
da6ecc5d
JB		 5122 if (!IS_VALLEYVIEW(dev)) {
5123 if (pipe == 0)
5124 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5125 else
5126 dspcntr |= DISPPLANE_SEL_PIPE_B;
5127 }
79e53945 5128
8a654f3b 5129 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW		 5130
5131 /* pipesrc and dspsize control the size that is scaled from,
5132 * which should always be the user's requested size.
79e53945 5133 */
929c77fb 5134 I915_WRITE(DSPSIZE(plane),
37327abd
VS		 5135 ((intel_crtc->config.pipe_src_h - 1) << 16) |
5136 (intel_crtc->config.pipe_src_w - 1));
929c77fb 5137 I915_WRITE(DSPPOS(plane), 0);
2c07245f 5138
84b046f3
DV		 5139 i9xx_set_pipeconf(intel_crtc);
5140
f564048e
EA		 5141 I915_WRITE(DSPCNTR(plane), dspcntr);
5142 POSTING_READ(DSPCNTR(plane));
5143
94352cf9 5144 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e 5145
f564048e
EA		 5146 return ret;
5147}
5148
2fa2fe9a
DV		 5149static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5150 struct intel_crtc_config *pipe_config)
5151{
5152 struct drm_device *dev = crtc->base.dev;
5153 struct drm_i915_private *dev_priv = dev->dev_private;
5154 uint32_t tmp;
5155
5156 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 5157 if (!(tmp & PFIT_ENABLE))
5158 return;
2fa2fe9a 5159
06922821 5160 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 5161 if (INTEL_INFO(dev)->gen < 4) {
5162 if (crtc->pipe != PIPE_B)
5163 return;
2fa2fe9a
DV		 5164 } else {
5165 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5166 return;
5167 }
5168
06922821 5169 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 5170 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5171 if (INTEL_INFO(dev)->gen < 5)
5172 pipe_config->gmch_pfit.lvds_border_bits =
5173 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5174}
5175
acbec814
JB		 5176static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5177 struct intel_crtc_config *pipe_config)
5178{
5179 struct drm_device *dev = crtc->base.dev;
5180 struct drm_i915_private *dev_priv = dev->dev_private;
5181 int pipe = pipe_config->cpu_transcoder;
5182 intel_clock_t clock;
5183 u32 mdiv;
662c6ecb 5184 int refclk = 100000;
acbec814
JB		 5185
5186 mutex_lock(&dev_priv->dpio_lock);
5187 mdiv = vlv_dpio_read(dev_priv, pipe, DPIO_DIV(pipe));
5188 mutex_unlock(&dev_priv->dpio_lock);
5189
5190 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5191 clock.m2 = mdiv & DPIO_M2DIV_MASK;
5192 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5193 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5194 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5195
662c6ecb
CW		 5196 clock.vco = refclk * clock.m1 * clock.m2 / clock.n;
5197 clock.dot = 2 * clock.vco / (clock.p1 * clock.p2);
acbec814
JB		 5198
5199 pipe_config->port_clock = clock.dot / 10;
5200}
5201
0e8ffe1b
DV		 5202static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5203 struct intel_crtc_config *pipe_config)
5204{
5205 struct drm_device *dev = crtc->base.dev;
5206 struct drm_i915_private *dev_priv = dev->dev_private;
5207 uint32_t tmp;
5208
e143a21c 5209 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 5210 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5211
0e8ffe1b
DV		 5212 tmp = I915_READ(PIPECONF(crtc->pipe));
5213 if (!(tmp & PIPECONF_ENABLE))
5214 return false;
5215
42571aef
VS		 5216 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5217 switch (tmp & PIPECONF_BPC_MASK) {
5218 case PIPECONF_6BPC:
5219 pipe_config->pipe_bpp = 18;
5220 break;
5221 case PIPECONF_8BPC:
5222 pipe_config->pipe_bpp = 24;
5223 break;
5224 case PIPECONF_10BPC:
5225 pipe_config->pipe_bpp = 30;
5226 break;
5227 default:
5228 break;
5229 }
5230 }
5231
282740f7
VS		 5232 if (INTEL_INFO(dev)->gen < 4)
5233 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5234
1bd1bd80
DV		 5235 intel_get_pipe_timings(crtc, pipe_config);
5236
2fa2fe9a
DV		 5237 i9xx_get_pfit_config(crtc, pipe_config);
5238
6c49f241
DV		 5239 if (INTEL_INFO(dev)->gen >= 4) {
5240 tmp = I915_READ(DPLL_MD(crtc->pipe));
5241 pipe_config->pixel_multiplier =
5242 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5243 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 5244 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 5245 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5246 tmp = I915_READ(DPLL(crtc->pipe));
5247 pipe_config->pixel_multiplier =
5248 ((tmp & SDVO_MULTIPLIER_MASK)
5249 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5250 } else {
5251 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5252 * port and will be fixed up in the encoder->get_config
5253 * function. */
5254 pipe_config->pixel_multiplier = 1;
5255 }
8bcc2795
DV		 5256 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5257 if (!IS_VALLEYVIEW(dev)) {
5258 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5259 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 5260 } else {
5261 /* Mask out read-only status bits. */
5262 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5263 DPLL_PORTC_READY_MASK |
5264 DPLL_PORTB_READY_MASK);
8bcc2795 5265 }
6c49f241 5266
acbec814
JB		 5267 if (IS_VALLEYVIEW(dev))
5268 vlv_crtc_clock_get(crtc, pipe_config);
5269 else
5270 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 5271
0e8ffe1b
DV		 5272 return true;
5273}
5274
dde86e2d 5275static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5276{
5277 struct drm_i915_private *dev_priv = dev->dev_private;
5278 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5279 struct intel_encoder *encoder;
74cfd7ac 5280 u32 val, final;
13d83a67 5281 bool has_lvds = false;
199e5d79 5282 bool has_cpu_edp = false;
199e5d79 5283 bool has_panel = false;
99eb6a01
KP		 5284 bool has_ck505 = false;
5285 bool can_ssc = false;
13d83a67
JB		 5286
5287 /* We need to take the global config into account */
199e5d79
KP		 5288 list_for_each_entry(encoder, &mode_config->encoder_list,
5289 base.head) {
5290 switch (encoder->type) {
5291 case INTEL_OUTPUT_LVDS:
5292 has_panel = true;
5293 has_lvds = true;
5294 break;
5295 case INTEL_OUTPUT_EDP:
5296 has_panel = true;
2de6905f 5297 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5298 has_cpu_edp = true;
5299 break;
13d83a67
JB		 5300 }
5301 }
5302
99eb6a01 5303 if (HAS_PCH_IBX(dev)) {
41aa3448 5304 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5305 can_ssc = has_ck505;
5306 } else {
5307 has_ck505 = false;
5308 can_ssc = true;
5309 }
5310
2de6905f
ID		 5311 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5312 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5313
5314 /* Ironlake: try to setup display ref clock before DPLL
5315 * enabling. This is only under driver's control after
5316 * PCH B stepping, previous chipset stepping should be
5317 * ignoring this setting.
5318 */
74cfd7ac
CW		 5319 val = I915_READ(PCH_DREF_CONTROL);
5320
5321 /* As we must carefully and slowly disable/enable each source in turn,
5322 * compute the final state we want first and check if we need to
5323 * make any changes at all.
5324 */
5325 final = val;
5326 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5327 if (has_ck505)
5328 final |= DREF_NONSPREAD_CK505_ENABLE;
5329 else
5330 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5331
5332 final &= ~DREF_SSC_SOURCE_MASK;
5333 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5334 final &= ~DREF_SSC1_ENABLE;
5335
5336 if (has_panel) {
5337 final |= DREF_SSC_SOURCE_ENABLE;
5338
5339 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5340 final |= DREF_SSC1_ENABLE;
5341
5342 if (has_cpu_edp) {
5343 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5344 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5345 else
5346 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5347 } else
5348 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5349 } else {
5350 final |= DREF_SSC_SOURCE_DISABLE;
5351 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5352 }
5353
5354 if (final == val)
5355 return;
5356
13d83a67 5357 /* Always enable nonspread source */
74cfd7ac 5358 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5359
99eb6a01 5360 if (has_ck505)
74cfd7ac 5361 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5362 else
74cfd7ac 5363 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5364
199e5d79 5365 if (has_panel) {
74cfd7ac
CW		 5366 val &= ~DREF_SSC_SOURCE_MASK;
5367 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5368
199e5d79 5369 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5370 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5371 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5372 val |= DREF_SSC1_ENABLE;
e77166b5 5373 } else
74cfd7ac 5374 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5375
5376 /* Get SSC going before enabling the outputs */
74cfd7ac 5377 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5378 POSTING_READ(PCH_DREF_CONTROL);
5379 udelay(200);
5380
74cfd7ac 5381 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5382
5383 /* Enable CPU source on CPU attached eDP */
199e5d79 5384 if (has_cpu_edp) {
99eb6a01 5385 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5386 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5387 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5388 }
13d83a67 5389 else
74cfd7ac 5390 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5391 } else
74cfd7ac 5392 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5393
74cfd7ac 5394 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5395 POSTING_READ(PCH_DREF_CONTROL);
5396 udelay(200);
5397 } else {
5398 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5399
74cfd7ac 5400 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5401
5402 /* Turn off CPU output */
74cfd7ac 5403 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5404
74cfd7ac 5405 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5406 POSTING_READ(PCH_DREF_CONTROL);
5407 udelay(200);
5408
5409 /* Turn off the SSC source */
74cfd7ac
CW		 5410 val &= ~DREF_SSC_SOURCE_MASK;
5411 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5412
5413 /* Turn off SSC1 */
74cfd7ac 5414 val &= ~DREF_SSC1_ENABLE;
199e5d79 5415
74cfd7ac 5416 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5417 POSTING_READ(PCH_DREF_CONTROL);
5418 udelay(200);
5419 }
74cfd7ac
CW		 5420
5421 BUG_ON(val != final);
13d83a67
JB		 5422}
5423
f31f2d55 5424static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 5425{
f31f2d55 5426 uint32_t tmp;
dde86e2d 5427
0ff066a9
PZ		 5428 tmp = I915_READ(SOUTH_CHICKEN2);
5429 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5430 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5431
0ff066a9
PZ		 5432 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5433 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5434 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 5435
0ff066a9
PZ		 5436 tmp = I915_READ(SOUTH_CHICKEN2);
5437 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5438 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5439
0ff066a9
PZ		 5440 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5441 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5442 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 5443}
5444
5445/* WaMPhyProgramming:hsw */
5446static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5447{
5448 uint32_t tmp;
dde86e2d
PZ		 5449
5450 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5451 tmp &= ~(0xFF << 24);
5452 tmp |= (0x12 << 24);
5453 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5454
dde86e2d
PZ		 5455 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5456 tmp |= (1 << 11);
5457 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5458
5459 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5460 tmp |= (1 << 11);
5461 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5462
dde86e2d
PZ		 5463 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5464 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5465 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5466
5467 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5468 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5469 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5470
0ff066a9
PZ		 5471 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5472 tmp &= ~(7 << 13);
5473 tmp |= (5 << 13);
5474 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 5475
0ff066a9
PZ		 5476 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5477 tmp &= ~(7 << 13);
5478 tmp |= (5 << 13);
5479 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 5480
5481 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5482 tmp &= ~0xFF;
5483 tmp |= 0x1C;
5484 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5485
5486 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5487 tmp &= ~0xFF;
5488 tmp |= 0x1C;
5489 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5490
5491 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5492 tmp &= ~(0xFF << 16);
5493 tmp |= (0x1C << 16);
5494 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5495
5496 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5497 tmp &= ~(0xFF << 16);
5498 tmp |= (0x1C << 16);
5499 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5500
0ff066a9
PZ		 5501 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5502 tmp |= (1 << 27);
5503 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 5504
0ff066a9
PZ		 5505 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5506 tmp |= (1 << 27);
5507 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 5508
0ff066a9
PZ		 5509 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5510 tmp &= ~(0xF << 28);
5511 tmp |= (4 << 28);
5512 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 5513
0ff066a9
PZ		 5514 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5515 tmp &= ~(0xF << 28);
5516 tmp |= (4 << 28);
5517 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 5518}
5519
2fa86a1f
PZ		 5520/* Implements 3 different sequences from BSpec chapter "Display iCLK
5521 * Programming" based on the parameters passed:
5522 * - Sequence to enable CLKOUT_DP
5523 * - Sequence to enable CLKOUT_DP without spread
5524 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5525 */
5526static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5527 bool with_fdi)
f31f2d55
PZ		 5528{
5529 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 5530 uint32_t reg, tmp;
5531
5532 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5533 with_spread = true;
5534 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5535 with_fdi, "LP PCH doesn't have FDI\n"))
5536 with_fdi = false;
f31f2d55
PZ		 5537
5538 mutex_lock(&dev_priv->dpio_lock);
5539
5540 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5541 tmp &= ~SBI_SSCCTL_DISABLE;
5542 tmp |= SBI_SSCCTL_PATHALT;
5543 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5544
5545 udelay(24);
5546
2fa86a1f
PZ		 5547 if (with_spread) {
5548 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5549 tmp &= ~SBI_SSCCTL_PATHALT;
5550 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 5551
2fa86a1f
PZ		 5552 if (with_fdi) {
5553 lpt_reset_fdi_mphy(dev_priv);
5554 lpt_program_fdi_mphy(dev_priv);
5555 }
5556 }
dde86e2d 5557
2fa86a1f
PZ		 5558 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5559 SBI_GEN0 : SBI_DBUFF0;
5560 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5561 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5562 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
DV		 5563
5564 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5565}
5566
47701c3b
PZ		 5567/* Sequence to disable CLKOUT_DP */
5568static void lpt_disable_clkout_dp(struct drm_device *dev)
5569{
5570 struct drm_i915_private *dev_priv = dev->dev_private;
5571 uint32_t reg, tmp;
5572
5573 mutex_lock(&dev_priv->dpio_lock);
5574
5575 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5576 SBI_GEN0 : SBI_DBUFF0;
5577 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5578 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5579 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5580
5581 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5582 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5583 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5584 tmp |= SBI_SSCCTL_PATHALT;
5585 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5586 udelay(32);
5587 }
5588 tmp |= SBI_SSCCTL_DISABLE;
5589 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5590 }
5591
5592 mutex_unlock(&dev_priv->dpio_lock);
5593}
5594
bf8fa3d3
PZ		 5595static void lpt_init_pch_refclk(struct drm_device *dev)
5596{
5597 struct drm_mode_config *mode_config = &dev->mode_config;
5598 struct intel_encoder *encoder;
5599 bool has_vga = false;
5600
5601 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5602 switch (encoder->type) {
5603 case INTEL_OUTPUT_ANALOG:
5604 has_vga = true;
5605 break;
5606 }
5607 }
5608
47701c3b
PZ		 5609 if (has_vga)
5610 lpt_enable_clkout_dp(dev, true, true);
5611 else
5612 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 5613}
5614
dde86e2d
PZ		 5615/*
5616 * Initialize reference clocks when the driver loads
5617 */
5618void intel_init_pch_refclk(struct drm_device *dev)
5619{
5620 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5621 ironlake_init_pch_refclk(dev);
5622 else if (HAS_PCH_LPT(dev))
5623 lpt_init_pch_refclk(dev);
5624}
5625
d9d444cb
JB		 5626static int ironlake_get_refclk(struct drm_crtc *crtc)
5627{
5628 struct drm_device *dev = crtc->dev;
5629 struct drm_i915_private *dev_priv = dev->dev_private;
5630 struct intel_encoder *encoder;
d9d444cb
JB		 5631 int num_connectors = 0;
5632 bool is_lvds = false;
5633
6c2b7c12 5634 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5635 switch (encoder->type) {
5636 case INTEL_OUTPUT_LVDS:
5637 is_lvds = true;
5638 break;
d9d444cb
JB		 5639 }
5640 num_connectors++;
5641 }
5642
5643 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5644 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5645 dev_priv->vbt.lvds_ssc_freq);
5646 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5647 }
5648
5649 return 120000;
5650}
5651
6ff93609 5652static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5653{
c8203565 5654 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5655 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5656 int pipe = intel_crtc->pipe;
c8203565
PZ		 5657 uint32_t val;
5658
78114071 5659 val = 0;
c8203565 5660
965e0c48 5661 switch (intel_crtc->config.pipe_bpp) {
c8203565 5662 case 18:
dfd07d72 5663 val |= PIPECONF_6BPC;
c8203565
PZ		 5664 break;
5665 case 24:
dfd07d72 5666 val |= PIPECONF_8BPC;
c8203565
PZ		 5667 break;
5668 case 30:
dfd07d72 5669 val |= PIPECONF_10BPC;
c8203565
PZ		 5670 break;
5671 case 36:
dfd07d72 5672 val |= PIPECONF_12BPC;
c8203565
PZ		 5673 break;
5674 default:
cc769b62
PZ		 5675 /* Case prevented by intel_choose_pipe_bpp_dither. */
5676 BUG();
c8203565
PZ		 5677 }
5678
d8b32247 5679 if (intel_crtc->config.dither)
c8203565
PZ		 5680 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5681
6ff93609 5682 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5683 val |= PIPECONF_INTERLACED_ILK;
5684 else
5685 val |= PIPECONF_PROGRESSIVE;
5686
50f3b016 5687 if (intel_crtc->config.limited_color_range)
3685a8f3 5688 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 5689
c8203565
PZ		 5690 I915_WRITE(PIPECONF(pipe), val);
5691 POSTING_READ(PIPECONF(pipe));
5692}
5693
86d3efce
VS		 5694/*
5695 * Set up the pipe CSC unit.
5696 *
5697 * Currently only full range RGB to limited range RGB conversion
5698 * is supported, but eventually this should handle various
5699 * RGB<->YCbCr scenarios as well.
5700 */
50f3b016 5701static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5702{
5703 struct drm_device *dev = crtc->dev;
5704 struct drm_i915_private *dev_priv = dev->dev_private;
5705 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5706 int pipe = intel_crtc->pipe;
5707 uint16_t coeff = 0x7800; /* 1.0 */
5708
5709 /*
5710 * TODO: Check what kind of values actually come out of the pipe
5711 * with these coeff/postoff values and adjust to get the best
5712 * accuracy. Perhaps we even need to take the bpc value into
5713 * consideration.
5714 */
5715
50f3b016 5716 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5717 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5718
5719 /*
5720 * GY/GU and RY/RU should be the other way around according
5721 * to BSpec, but reality doesn't agree. Just set them up in
5722 * a way that results in the correct picture.
5723 */
5724 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5725 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5726
5727 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5728 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5729
5730 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5731 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5732
5733 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5734 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5735 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5736
5737 if (INTEL_INFO(dev)->gen > 6) {
5738 uint16_t postoff = 0;
5739
50f3b016 5740 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5741 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5742
5743 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5744 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5745 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5746
5747 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5748 } else {
5749 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5750
50f3b016 5751 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5752 mode |= CSC_BLACK_SCREEN_OFFSET;
5753
5754 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5755 }
5756}
5757
6ff93609 5758static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5759{
5760 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5761 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5762 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5763 uint32_t val;
5764
3eff4faa 5765 val = 0;
ee2b0b38 5766
d8b32247 5767 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5768 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5769
6ff93609 5770 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5771 val |= PIPECONF_INTERLACED_ILK;
5772 else
5773 val |= PIPECONF_PROGRESSIVE;
5774
702e7a56
PZ		 5775 I915_WRITE(PIPECONF(cpu_transcoder), val);
5776 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 5777
5778 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5779 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
ee2b0b38
PZ		 5780}
5781
6591c6e4 5782static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ		 5783 intel_clock_t *clock,
5784 bool *has_reduced_clock,
5785 intel_clock_t *reduced_clock)
5786{
5787 struct drm_device *dev = crtc->dev;
5788 struct drm_i915_private *dev_priv = dev->dev_private;
5789 struct intel_encoder *intel_encoder;
5790 int refclk;
d4906093 5791 const intel_limit_t *limit;
a16af721 5792 bool ret, is_lvds = false;
79e53945 5793
6591c6e4
PZ		 5794 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5795 switch (intel_encoder->type) {
79e53945
JB		 5796 case INTEL_OUTPUT_LVDS:
5797 is_lvds = true;
5798 break;
79e53945
JB		 5799 }
5800 }
5801
d9d444cb 5802 refclk = ironlake_get_refclk(crtc);
79e53945 5803
d4906093
ML		 5804 /*
5805 * Returns a set of divisors for the desired target clock with the given
5806 * refclk, or FALSE. The returned values represent the clock equation:
5807 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5808 */
1b894b59 5809 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 5810 ret = dev_priv->display.find_dpll(limit, crtc,
5811 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 5812 refclk, NULL, clock);
6591c6e4
PZ		 5813 if (!ret)
5814 return false;
cda4b7d3 5815
ddc9003c 5816 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5817 /*
5818 * Ensure we match the reduced clock's P to the target clock.
5819 * If the clocks don't match, we can't switch the display clock
5820 * by using the FP0/FP1. In such case we will disable the LVDS
5821 * downclock feature.
5822 */
ee9300bb
DV		 5823 *has_reduced_clock =
5824 dev_priv->display.find_dpll(limit, crtc,
5825 dev_priv->lvds_downclock,
5826 refclk, clock,
5827 reduced_clock);
652c393a 5828 }
61e9653f 5829
6591c6e4
PZ		 5830 return true;
5831}
5832
01a415fd
DV		 5833static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5834{
5835 struct drm_i915_private *dev_priv = dev->dev_private;
5836 uint32_t temp;
5837
5838 temp = I915_READ(SOUTH_CHICKEN1);
5839 if (temp & FDI_BC_BIFURCATION_SELECT)
5840 return;
5841
5842 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5843 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5844
5845 temp |= FDI_BC_BIFURCATION_SELECT;
5846 DRM_DEBUG_KMS("enabling fdi C rx\n");
5847 I915_WRITE(SOUTH_CHICKEN1, temp);
5848 POSTING_READ(SOUTH_CHICKEN1);
5849}
5850
ebfd86fd 5851static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
01a415fd
DV		 5852{
5853 struct drm_device *dev = intel_crtc->base.dev;
5854 struct drm_i915_private *dev_priv = dev->dev_private;
01a415fd
DV		 5855
5856 switch (intel_crtc->pipe) {
5857 case PIPE_A:
ebfd86fd 5858 break;
01a415fd 5859 case PIPE_B:
ebfd86fd 5860 if (intel_crtc->config.fdi_lanes > 2)
01a415fd
DV		 5861 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5862 else
5863 cpt_enable_fdi_bc_bifurcation(dev);
5864
ebfd86fd 5865 break;
01a415fd 5866 case PIPE_C:
01a415fd
DV		 5867 cpt_enable_fdi_bc_bifurcation(dev);
5868
ebfd86fd 5869 break;
01a415fd
DV		 5870 default:
5871 BUG();
5872 }
5873}
5874
d4b1931c
PZ		 5875int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5876{
5877 /*
5878 * Account for spread spectrum to avoid
5879 * oversubscribing the link. Max center spread
5880 * is 2.5%; use 5% for safety's sake.
5881 */
5882 u32 bps = target_clock * bpp * 21 / 20;
5883 return bps / (link_bw * 8) + 1;
5884}
5885
7429e9d4 5886static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 5887{
7429e9d4 5888 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 5889}
5890
de13a2e3 5891static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5892 u32 *fp,
9a7c7890 5893 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5894{
de13a2e3 5895 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5896 struct drm_device *dev = crtc->dev;
5897 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5898 struct intel_encoder *intel_encoder;
5899 uint32_t dpll;
6cc5f341 5900 int factor, num_connectors = 0;
09ede541 5901 bool is_lvds = false, is_sdvo = false;
79e53945 5902
de13a2e3
PZ		 5903 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5904 switch (intel_encoder->type) {
79e53945
JB		 5905 case INTEL_OUTPUT_LVDS:
5906 is_lvds = true;
5907 break;
5908 case INTEL_OUTPUT_SDVO:
7d57382e 5909 case INTEL_OUTPUT_HDMI:
79e53945 5910 is_sdvo = true;
79e53945 5911 break;
79e53945 5912 }
43565a06 5913
c751ce4f 5914 num_connectors++;
79e53945 5915 }
79e53945 5916
c1858123 5917 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5918 factor = 21;
5919 if (is_lvds) {
5920 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5921 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5922 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5923 factor = 25;
09ede541 5924 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5925 factor = 20;
c1858123 5926
7429e9d4 5927 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5928 *fp |= FP_CB_TUNE;
2c07245f 5929
9a7c7890
DV		 5930 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5931 *fp2 |= FP_CB_TUNE;
5932
5eddb70b 5933 dpll = 0;
2c07245f 5934
a07d6787
EA		 5935 if (is_lvds)
5936 dpll |= DPLLB_MODE_LVDS;
5937 else
5938 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 5939
ef1b460d
DV		 5940 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5941 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 5942
5943 if (is_sdvo)
4a33e48d 5944 dpll |= DPLL_SDVO_HIGH_SPEED;
9566e9af 5945 if (intel_crtc->config.has_dp_encoder)
4a33e48d 5946 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 5947
a07d6787 5948 /* compute bitmask from p1 value */
7429e9d4 5949 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5950 /* also FPA1 */
7429e9d4 5951 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5952
7429e9d4 5953 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5954 case 5:
5955 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5956 break;
5957 case 7:
5958 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5959 break;
5960 case 10:
5961 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5962 break;
5963 case 14:
5964 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5965 break;
79e53945
JB		 5966 }
5967
b4c09f3b 5968 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5969 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5970 else
5971 dpll |= PLL_REF_INPUT_DREFCLK;
5972
959e16d6 5973 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 5974}
5975
5976static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5977 int x, int y,
5978 struct drm_framebuffer *fb)
5979{
5980 struct drm_device *dev = crtc->dev;
5981 struct drm_i915_private *dev_priv = dev->dev_private;
5982 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5983 int pipe = intel_crtc->pipe;
5984 int plane = intel_crtc->plane;
5985 int num_connectors = 0;
5986 intel_clock_t clock, reduced_clock;
cbbab5bd 5987 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5988 bool ok, has_reduced_clock = false;
8b47047b 5989 bool is_lvds = false;
de13a2e3 5990 struct intel_encoder *encoder;
e2b78267 5991 struct intel_shared_dpll *pll;
de13a2e3 5992 int ret;
de13a2e3
PZ		 5993
5994 for_each_encoder_on_crtc(dev, crtc, encoder) {
5995 switch (encoder->type) {
5996 case INTEL_OUTPUT_LVDS:
5997 is_lvds = true;
5998 break;
de13a2e3
PZ		 5999 }
6000
6001 num_connectors++;
a07d6787 6002 }
79e53945 6003
5dc5298b
PZ		 6004 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6005 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 6006
ff9a6750 6007 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 6008 &has_reduced_clock, &reduced_clock);
ee9300bb 6009 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 6010 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6011 return -EINVAL;
79e53945 6012 }
f47709a9
DV		 6013 /* Compat-code for transition, will disappear. */
6014 if (!intel_crtc->config.clock_set) {
6015 intel_crtc->config.dpll.n = clock.n;
6016 intel_crtc->config.dpll.m1 = clock.m1;
6017 intel_crtc->config.dpll.m2 = clock.m2;
6018 intel_crtc->config.dpll.p1 = clock.p1;
6019 intel_crtc->config.dpll.p2 = clock.p2;
6020 }
79e53945 6021
5dc5298b 6022 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 6023 if (intel_crtc->config.has_pch_encoder) {
7429e9d4 6024 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 6025 if (has_reduced_clock)
7429e9d4 6026 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 6027
7429e9d4 6028 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 6029 &fp, &reduced_clock,
6030 has_reduced_clock ? &fp2 : NULL);
6031
959e16d6 6032 intel_crtc->config.dpll_hw_state.dpll = dpll;
66e985c0
DV		 6033 intel_crtc->config.dpll_hw_state.fp0 = fp;
6034 if (has_reduced_clock)
6035 intel_crtc->config.dpll_hw_state.fp1 = fp2;
6036 else
6037 intel_crtc->config.dpll_hw_state.fp1 = fp;
6038
b89a1d39 6039 pll = intel_get_shared_dpll(intel_crtc);
ee7b9f93 6040 if (pll == NULL) {
84f44ce7
VS		 6041 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6042 pipe_name(pipe));
4b645f14
JB		 6043 return -EINVAL;
6044 }
ee7b9f93 6045 } else
e72f9fbf 6046 intel_put_shared_dpll(intel_crtc);
79e53945 6047
03afc4a2
DV		 6048 if (intel_crtc->config.has_dp_encoder)
6049 intel_dp_set_m_n(intel_crtc);
79e53945 6050
bcd644e0
DV		 6051 if (is_lvds && has_reduced_clock && i915_powersave)
6052 intel_crtc->lowfreq_avail = true;
6053 else
6054 intel_crtc->lowfreq_avail = false;
e2b78267
DV		 6055
6056 if (intel_crtc->config.has_pch_encoder) {
6057 pll = intel_crtc_to_shared_dpll(intel_crtc);
6058
652c393a
JB		 6059 }
6060
8a654f3b 6061 intel_set_pipe_timings(intel_crtc);
5eddb70b 6062
ca3a0ff8 6063 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 6064 intel_cpu_transcoder_set_m_n(intel_crtc,
6065 &intel_crtc->config.fdi_m_n);
6066 }
2c07245f 6067
ebfd86fd
DV		 6068 if (IS_IVYBRIDGE(dev))
6069 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
79e53945 6070
6ff93609 6071 ironlake_set_pipeconf(crtc);
79e53945 6072
a1f9e77e
PZ		 6073 /* Set up the display plane register */
6074 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 6075 POSTING_READ(DSPCNTR(plane));
79e53945 6076
94352cf9 6077 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd 6078
1857e1da 6079 return ret;
79e53945
JB		 6080}
6081
eb14cb74
VS		 6082static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6083 struct intel_link_m_n *m_n)
6084{
6085 struct drm_device *dev = crtc->base.dev;
6086 struct drm_i915_private *dev_priv = dev->dev_private;
6087 enum pipe pipe = crtc->pipe;
6088
6089 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6090 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6091 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6092 & ~TU_SIZE_MASK;
6093 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6094 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6095 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6096}
6097
6098static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6099 enum transcoder transcoder,
6100 struct intel_link_m_n *m_n)
72419203
DV		 6101{
6102 struct drm_device *dev = crtc->base.dev;
6103 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 6104 enum pipe pipe = crtc->pipe;
72419203 6105
eb14cb74
VS		 6106 if (INTEL_INFO(dev)->gen >= 5) {
6107 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6108 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6109 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6110 & ~TU_SIZE_MASK;
6111 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6112 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6113 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6114 } else {
6115 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6116 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6117 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6118 & ~TU_SIZE_MASK;
6119 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6120 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6121 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6122 }
6123}
6124
6125void intel_dp_get_m_n(struct intel_crtc *crtc,
6126 struct intel_crtc_config *pipe_config)
6127{
6128 if (crtc->config.has_pch_encoder)
6129 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6130 else
6131 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6132 &pipe_config->dp_m_n);
6133}
72419203 6134
eb14cb74
VS		 6135static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6136 struct intel_crtc_config *pipe_config)
6137{
6138 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6139 &pipe_config->fdi_m_n);
72419203
DV		 6140}
6141
2fa2fe9a
DV		 6142static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6143 struct intel_crtc_config *pipe_config)
6144{
6145 struct drm_device *dev = crtc->base.dev;
6146 struct drm_i915_private *dev_priv = dev->dev_private;
6147 uint32_t tmp;
6148
6149 tmp = I915_READ(PF_CTL(crtc->pipe));
6150
6151 if (tmp & PF_ENABLE) {
fd4daa9c 6152 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 6153 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6154 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 6155
6156 /* We currently do not free assignements of panel fitters on
6157 * ivb/hsw (since we don't use the higher upscaling modes which
6158 * differentiates them) so just WARN about this case for now. */
6159 if (IS_GEN7(dev)) {
6160 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6161 PF_PIPE_SEL_IVB(crtc->pipe));
6162 }
2fa2fe9a 6163 }
79e53945
JB		 6164}
6165
0e8ffe1b
DV		 6166static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6167 struct intel_crtc_config *pipe_config)
6168{
6169 struct drm_device *dev = crtc->base.dev;
6170 struct drm_i915_private *dev_priv = dev->dev_private;
6171 uint32_t tmp;
6172
e143a21c 6173 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 6174 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 6175
0e8ffe1b
DV		 6176 tmp = I915_READ(PIPECONF(crtc->pipe));
6177 if (!(tmp & PIPECONF_ENABLE))
6178 return false;
6179
42571aef
VS		 6180 switch (tmp & PIPECONF_BPC_MASK) {
6181 case PIPECONF_6BPC:
6182 pipe_config->pipe_bpp = 18;
6183 break;
6184 case PIPECONF_8BPC:
6185 pipe_config->pipe_bpp = 24;
6186 break;
6187 case PIPECONF_10BPC:
6188 pipe_config->pipe_bpp = 30;
6189 break;
6190 case PIPECONF_12BPC:
6191 pipe_config->pipe_bpp = 36;
6192 break;
6193 default:
6194 break;
6195 }
6196
ab9412ba 6197 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 6198 struct intel_shared_dpll *pll;
6199
88adfff1
DV		 6200 pipe_config->has_pch_encoder = true;
6201
627eb5a3
DV		 6202 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6203 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6204 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6205
6206 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 6207
c0d43d62 6208 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 6209 pipe_config->shared_dpll =
6210 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 6211 } else {
6212 tmp = I915_READ(PCH_DPLL_SEL);
6213 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6214 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6215 else
6216 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6217 }
66e985c0
DV		 6218
6219 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6220
6221 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6222 &pipe_config->dpll_hw_state));
c93f54cf
DV		 6223
6224 tmp = pipe_config->dpll_hw_state.dpll;
6225 pipe_config->pixel_multiplier =
6226 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6227 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 6228
6229 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 6230 } else {
6231 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 6232 }
6233
1bd1bd80
DV		 6234 intel_get_pipe_timings(crtc, pipe_config);
6235
2fa2fe9a
DV		 6236 ironlake_get_pfit_config(crtc, pipe_config);
6237
0e8ffe1b
DV		 6238 return true;
6239}
6240
be256dc7
PZ		 6241static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6242{
6243 struct drm_device *dev = dev_priv->dev;
6244 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6245 struct intel_crtc *crtc;
6246 unsigned long irqflags;
bd633a7c 6247 uint32_t val;
be256dc7
PZ		 6248
6249 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6250 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
6251 pipe_name(crtc->pipe));
6252
6253 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6254 WARN(plls->spll_refcount, "SPLL enabled\n");
6255 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6256 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6257 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6258 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6259 "CPU PWM1 enabled\n");
6260 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6261 "CPU PWM2 enabled\n");
6262 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6263 "PCH PWM1 enabled\n");
6264 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6265 "Utility pin enabled\n");
6266 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6267
6268 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6269 val = I915_READ(DEIMR);
6270 WARN((val & ~DE_PCH_EVENT_IVB) != val,
6271 "Unexpected DEIMR bits enabled: 0x%x\n", val);
6272 val = I915_READ(SDEIMR);
bd633a7c 6273 WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
be256dc7
PZ		 6274 "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6275 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6276}
6277
6278/*
6279 * This function implements pieces of two sequences from BSpec:
6280 * - Sequence for display software to disable LCPLL
6281 * - Sequence for display software to allow package C8+
6282 * The steps implemented here are just the steps that actually touch the LCPLL
6283 * register. Callers should take care of disabling all the display engine
6284 * functions, doing the mode unset, fixing interrupts, etc.
6285 */
6ff58d53
PZ		 6286static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6287 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 6288{
6289 uint32_t val;
6290
6291 assert_can_disable_lcpll(dev_priv);
6292
6293 val = I915_READ(LCPLL_CTL);
6294
6295 if (switch_to_fclk) {
6296 val |= LCPLL_CD_SOURCE_FCLK;
6297 I915_WRITE(LCPLL_CTL, val);
6298
6299 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6300 LCPLL_CD_SOURCE_FCLK_DONE, 1))
6301 DRM_ERROR("Switching to FCLK failed\n");
6302
6303 val = I915_READ(LCPLL_CTL);
6304 }
6305
6306 val |= LCPLL_PLL_DISABLE;
6307 I915_WRITE(LCPLL_CTL, val);
6308 POSTING_READ(LCPLL_CTL);
6309
6310 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6311 DRM_ERROR("LCPLL still locked\n");
6312
6313 val = I915_READ(D_COMP);
6314 val |= D_COMP_COMP_DISABLE;
515b2392
PZ		 6315 mutex_lock(&dev_priv->rps.hw_lock);
6316 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6317 DRM_ERROR("Failed to disable D_COMP\n");
6318 mutex_unlock(&dev_priv->rps.hw_lock);
be256dc7
PZ		 6319 POSTING_READ(D_COMP);
6320 ndelay(100);
6321
6322 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6323 DRM_ERROR("D_COMP RCOMP still in progress\n");
6324
6325 if (allow_power_down) {
6326 val = I915_READ(LCPLL_CTL);
6327 val |= LCPLL_POWER_DOWN_ALLOW;
6328 I915_WRITE(LCPLL_CTL, val);
6329 POSTING_READ(LCPLL_CTL);
6330 }
6331}
6332
6333/*
6334 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6335 * source.
6336 */
6ff58d53 6337static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 6338{
6339 uint32_t val;
6340
6341 val = I915_READ(LCPLL_CTL);
6342
6343 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6344 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6345 return;
6346
215733fa
PZ		 6347 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6348 * we'll hang the machine! */
6349 dev_priv->uncore.funcs.force_wake_get(dev_priv);
6350
be256dc7
PZ		 6351 if (val & LCPLL_POWER_DOWN_ALLOW) {
6352 val &= ~LCPLL_POWER_DOWN_ALLOW;
6353 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 6354 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 6355 }
6356
6357 val = I915_READ(D_COMP);
6358 val |= D_COMP_COMP_FORCE;
6359 val &= ~D_COMP_COMP_DISABLE;
515b2392
PZ		 6360 mutex_lock(&dev_priv->rps.hw_lock);
6361 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6362 DRM_ERROR("Failed to enable D_COMP\n");
6363 mutex_unlock(&dev_priv->rps.hw_lock);
35d8f2eb 6364 POSTING_READ(D_COMP);
be256dc7
PZ		 6365
6366 val = I915_READ(LCPLL_CTL);
6367 val &= ~LCPLL_PLL_DISABLE;
6368 I915_WRITE(LCPLL_CTL, val);
6369
6370 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6371 DRM_ERROR("LCPLL not locked yet\n");
6372
6373 if (val & LCPLL_CD_SOURCE_FCLK) {
6374 val = I915_READ(LCPLL_CTL);
6375 val &= ~LCPLL_CD_SOURCE_FCLK;
6376 I915_WRITE(LCPLL_CTL, val);
6377
6378 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6379 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6380 DRM_ERROR("Switching back to LCPLL failed\n");
6381 }
215733fa
PZ		 6382
6383 dev_priv->uncore.funcs.force_wake_put(dev_priv);
be256dc7
PZ		 6384}
6385
c67a470b
PZ		 6386void hsw_enable_pc8_work(struct work_struct *__work)
6387{
6388 struct drm_i915_private *dev_priv =
6389 container_of(to_delayed_work(__work), struct drm_i915_private,
6390 pc8.enable_work);
6391 struct drm_device *dev = dev_priv->dev;
6392 uint32_t val;
6393
6394 if (dev_priv->pc8.enabled)
6395 return;
6396
6397 DRM_DEBUG_KMS("Enabling package C8+\n");
6398
6399 dev_priv->pc8.enabled = true;
6400
6401 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6402 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6403 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6404 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6405 }
6406
6407 lpt_disable_clkout_dp(dev);
6408 hsw_pc8_disable_interrupts(dev);
6409 hsw_disable_lcpll(dev_priv, true, true);
6410}
6411
6412static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6413{
6414 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6415 WARN(dev_priv->pc8.disable_count < 1,
6416 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6417
6418 dev_priv->pc8.disable_count--;
6419 if (dev_priv->pc8.disable_count != 0)
6420 return;
6421
6422 schedule_delayed_work(&dev_priv->pc8.enable_work,
90058745 6423 msecs_to_jiffies(i915_pc8_timeout));
c67a470b
PZ		 6424}
6425
6426static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6427{
6428 struct drm_device *dev = dev_priv->dev;
6429 uint32_t val;
6430
6431 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6432 WARN(dev_priv->pc8.disable_count < 0,
6433 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6434
6435 dev_priv->pc8.disable_count++;
6436 if (dev_priv->pc8.disable_count != 1)
6437 return;
6438
6439 cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6440 if (!dev_priv->pc8.enabled)
6441 return;
6442
6443 DRM_DEBUG_KMS("Disabling package C8+\n");
6444
6445 hsw_restore_lcpll(dev_priv);
6446 hsw_pc8_restore_interrupts(dev);
6447 lpt_init_pch_refclk(dev);
6448
6449 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6450 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6451 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6452 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6453 }
6454
6455 intel_prepare_ddi(dev);
6456 i915_gem_init_swizzling(dev);
6457 mutex_lock(&dev_priv->rps.hw_lock);
6458 gen6_update_ring_freq(dev);
6459 mutex_unlock(&dev_priv->rps.hw_lock);
6460 dev_priv->pc8.enabled = false;
6461}
6462
6463void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6464{
6465 mutex_lock(&dev_priv->pc8.lock);
6466 __hsw_enable_package_c8(dev_priv);
6467 mutex_unlock(&dev_priv->pc8.lock);
6468}
6469
6470void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6471{
6472 mutex_lock(&dev_priv->pc8.lock);
6473 __hsw_disable_package_c8(dev_priv);
6474 mutex_unlock(&dev_priv->pc8.lock);
6475}
6476
6477static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6478{
6479 struct drm_device *dev = dev_priv->dev;
6480 struct intel_crtc *crtc;
6481 uint32_t val;
6482
6483 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6484 if (crtc->base.enabled)
6485 return false;
6486
6487 /* This case is still possible since we have the i915.disable_power_well
6488 * parameter and also the KVMr or something else might be requesting the
6489 * power well. */
6490 val = I915_READ(HSW_PWR_WELL_DRIVER);
6491 if (val != 0) {
6492 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6493 return false;
6494 }
6495
6496 return true;
6497}
6498
6499/* Since we're called from modeset_global_resources there's no way to
6500 * symmetrically increase and decrease the refcount, so we use
6501 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6502 * or not.
6503 */
6504static void hsw_update_package_c8(struct drm_device *dev)
6505{
6506 struct drm_i915_private *dev_priv = dev->dev_private;
6507 bool allow;
6508
6509 if (!i915_enable_pc8)
6510 return;
6511
6512 mutex_lock(&dev_priv->pc8.lock);
6513
6514 allow = hsw_can_enable_package_c8(dev_priv);
6515
6516 if (allow == dev_priv->pc8.requirements_met)
6517 goto done;
6518
6519 dev_priv->pc8.requirements_met = allow;
6520
6521 if (allow)
6522 __hsw_enable_package_c8(dev_priv);
6523 else
6524 __hsw_disable_package_c8(dev_priv);
6525
6526done:
6527 mutex_unlock(&dev_priv->pc8.lock);
6528}
6529
6530static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6531{
6532 if (!dev_priv->pc8.gpu_idle) {
6533 dev_priv->pc8.gpu_idle = true;
6534 hsw_enable_package_c8(dev_priv);
6535 }
6536}
6537
6538static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6539{
6540 if (dev_priv->pc8.gpu_idle) {
6541 dev_priv->pc8.gpu_idle = false;
6542 hsw_disable_package_c8(dev_priv);
6543 }
be256dc7
PZ		 6544}
6545
d6dd9eb1
DV		 6546static void haswell_modeset_global_resources(struct drm_device *dev)
6547{
d6dd9eb1
DV		 6548 bool enable = false;
6549 struct intel_crtc *crtc;
d6dd9eb1
DV		 6550
6551 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 6552 if (!crtc->base.enabled)
6553 continue;
d6dd9eb1 6554
fd4daa9c 6555 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.enabled ||
e7a639c4 6556 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 6557 enable = true;
6558 }
6559
d6dd9eb1 6560 intel_set_power_well(dev, enable);
c67a470b
PZ		 6561
6562 hsw_update_package_c8(dev);
d6dd9eb1
DV		 6563}
6564
09b4ddf9 6565static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 6566 int x, int y,
6567 struct drm_framebuffer *fb)
6568{
6569 struct drm_device *dev = crtc->dev;
6570 struct drm_i915_private *dev_priv = dev->dev_private;
6571 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 6572 int plane = intel_crtc->plane;
09b4ddf9 6573 int ret;
09b4ddf9 6574
ff9a6750 6575 if (!intel_ddi_pll_mode_set(crtc))
6441ab5f
PZ		 6576 return -EINVAL;
6577
03afc4a2
DV		 6578 if (intel_crtc->config.has_dp_encoder)
6579 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 6580
6581 intel_crtc->lowfreq_avail = false;
09b4ddf9 6582
8a654f3b 6583 intel_set_pipe_timings(intel_crtc);
09b4ddf9 6584
ca3a0ff8 6585 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 6586 intel_cpu_transcoder_set_m_n(intel_crtc,
6587 &intel_crtc->config.fdi_m_n);
6588 }
09b4ddf9 6589
6ff93609 6590 haswell_set_pipeconf(crtc);
09b4ddf9 6591
50f3b016 6592 intel_set_pipe_csc(crtc);
86d3efce 6593
09b4ddf9 6594 /* Set up the display plane register */
86d3efce 6595 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 6596 POSTING_READ(DSPCNTR(plane));
6597
6598 ret = intel_pipe_set_base(crtc, x, y, fb);
6599
1f803ee5 6600 return ret;
79e53945
JB		 6601}
6602
0e8ffe1b
DV		 6603static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6604 struct intel_crtc_config *pipe_config)
6605{
6606 struct drm_device *dev = crtc->base.dev;
6607 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 6608 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 6609 uint32_t tmp;
6610
e143a21c 6611 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 6612 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6613
eccb140b
DV		 6614 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6615 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6616 enum pipe trans_edp_pipe;
6617 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6618 default:
6619 WARN(1, "unknown pipe linked to edp transcoder\n");
6620 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6621 case TRANS_DDI_EDP_INPUT_A_ON:
6622 trans_edp_pipe = PIPE_A;
6623 break;
6624 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6625 trans_edp_pipe = PIPE_B;
6626 break;
6627 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6628 trans_edp_pipe = PIPE_C;
6629 break;
6630 }
6631
6632 if (trans_edp_pipe == crtc->pipe)
6633 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6634 }
6635
b97186f0 6636 if (!intel_display_power_enabled(dev,
eccb140b 6637 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 6638 return false;
6639
eccb140b 6640 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 6641 if (!(tmp & PIPECONF_ENABLE))
6642 return false;
6643
88adfff1 6644 /*
f196e6be 6645 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 6646 * DDI E. So just check whether this pipe is wired to DDI E and whether
6647 * the PCH transcoder is on.
6648 */
eccb140b 6649 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 6650 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 6651 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 6652 pipe_config->has_pch_encoder = true;
6653
627eb5a3
DV		 6654 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6655 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6656 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6657
6658 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 6659 }
6660
1bd1bd80
DV		 6661 intel_get_pipe_timings(crtc, pipe_config);
6662
2fa2fe9a
DV		 6663 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6664 if (intel_display_power_enabled(dev, pfit_domain))
6665 ironlake_get_pfit_config(crtc, pipe_config);
88adfff1 6666
42db64ef
PZ		 6667 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6668 (I915_READ(IPS_CTL) & IPS_ENABLE);
6669
6c49f241
DV		 6670 pipe_config->pixel_multiplier = 1;
6671
0e8ffe1b
DV		 6672 return true;
6673}
6674
f564048e 6675static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6676 int x, int y,
94352cf9 6677 struct drm_framebuffer *fb)
f564048e
EA		 6678{
6679 struct drm_device *dev = crtc->dev;
6680 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19 6681 struct intel_encoder *encoder;
0b701d27 6682 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 6683 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6684 int pipe = intel_crtc->pipe;
f564048e
EA		 6685 int ret;
6686
0b701d27 6687 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6688
b8cecdf5
DV		 6689 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6690
79e53945 6691 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6692
9256aa19
DV		 6693 if (ret != 0)
6694 return ret;
6695
6696 for_each_encoder_on_crtc(dev, crtc, encoder) {
6697 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6698 encoder->base.base.id,
6699 drm_get_encoder_name(&encoder->base),
6700 mode->base.id, mode->name);
36f2d1f1 6701 encoder->mode_set(encoder);
9256aa19
DV		 6702 }
6703
6704 return 0;
79e53945
JB		 6705}
6706
3a9627f4
WF		 6707static bool intel_eld_uptodate(struct drm_connector *connector,
6708 int reg_eldv, uint32_t bits_eldv,
6709 int reg_elda, uint32_t bits_elda,
6710 int reg_edid)
6711{
6712 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6713 uint8_t *eld = connector->eld;
6714 uint32_t i;
6715
6716 i = I915_READ(reg_eldv);
6717 i &= bits_eldv;
6718
6719 if (!eld[0])
6720 return !i;
6721
6722 if (!i)
6723 return false;
6724
6725 i = I915_READ(reg_elda);
6726 i &= ~bits_elda;
6727 I915_WRITE(reg_elda, i);
6728
6729 for (i = 0; i < eld[2]; i++)
6730 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6731 return false;
6732
6733 return true;
6734}
6735
e0dac65e
WF		 6736static void g4x_write_eld(struct drm_connector *connector,
6737 struct drm_crtc *crtc)
6738{
6739 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6740 uint8_t *eld = connector->eld;
6741 uint32_t eldv;
6742 uint32_t len;
6743 uint32_t i;
6744
6745 i = I915_READ(G4X_AUD_VID_DID);
6746
6747 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6748 eldv = G4X_ELDV_DEVCL_DEVBLC;
6749 else
6750 eldv = G4X_ELDV_DEVCTG;
6751
3a9627f4
WF		 6752 if (intel_eld_uptodate(connector,
6753 G4X_AUD_CNTL_ST, eldv,
6754 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6755 G4X_HDMIW_HDMIEDID))
6756 return;
6757
e0dac65e
WF		 6758 i = I915_READ(G4X_AUD_CNTL_ST);
6759 i &= ~(eldv | G4X_ELD_ADDR);
6760 len = (i >> 9) & 0x1f; /* ELD buffer size */
6761 I915_WRITE(G4X_AUD_CNTL_ST, i);
6762
6763 if (!eld[0])
6764 return;
6765
6766 len = min_t(uint8_t, eld[2], len);
6767 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6768 for (i = 0; i < len; i++)
6769 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6770
6771 i = I915_READ(G4X_AUD_CNTL_ST);
6772 i |= eldv;
6773 I915_WRITE(G4X_AUD_CNTL_ST, i);
6774}
6775
83358c85
WX		 6776static void haswell_write_eld(struct drm_connector *connector,
6777 struct drm_crtc *crtc)
6778{
6779 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6780 uint8_t *eld = connector->eld;
6781 struct drm_device *dev = crtc->dev;
7b9f35a6 6782 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6783 uint32_t eldv;
6784 uint32_t i;
6785 int len;
6786 int pipe = to_intel_crtc(crtc)->pipe;
6787 int tmp;
6788
6789 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6790 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6791 int aud_config = HSW_AUD_CFG(pipe);
6792 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6793
6794
6795 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6796
6797 /* Audio output enable */
6798 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6799 tmp = I915_READ(aud_cntrl_st2);
6800 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6801 I915_WRITE(aud_cntrl_st2, tmp);
6802
6803 /* Wait for 1 vertical blank */
6804 intel_wait_for_vblank(dev, pipe);
6805
6806 /* Set ELD valid state */
6807 tmp = I915_READ(aud_cntrl_st2);
7e7cb34f 6808 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
83358c85
WX		 6809 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6810 I915_WRITE(aud_cntrl_st2, tmp);
6811 tmp = I915_READ(aud_cntrl_st2);
7e7cb34f 6812 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
83358c85
WX		 6813
6814 /* Enable HDMI mode */
6815 tmp = I915_READ(aud_config);
7e7cb34f 6816 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
83358c85
WX		 6817 /* clear N_programing_enable and N_value_index */
6818 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6819 I915_WRITE(aud_config, tmp);
6820
6821 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6822
6823 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6824 intel_crtc->eld_vld = true;
83358c85
WX		 6825
6826 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6827 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6828 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6829 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6830 } else
6831 I915_WRITE(aud_config, 0);
6832
6833 if (intel_eld_uptodate(connector,
6834 aud_cntrl_st2, eldv,
6835 aud_cntl_st, IBX_ELD_ADDRESS,
6836 hdmiw_hdmiedid))
6837 return;
6838
6839 i = I915_READ(aud_cntrl_st2);
6840 i &= ~eldv;
6841 I915_WRITE(aud_cntrl_st2, i);
6842
6843 if (!eld[0])
6844 return;
6845
6846 i = I915_READ(aud_cntl_st);
6847 i &= ~IBX_ELD_ADDRESS;
6848 I915_WRITE(aud_cntl_st, i);
6849 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6850 DRM_DEBUG_DRIVER("port num:%d\n", i);
6851
6852 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6853 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6854 for (i = 0; i < len; i++)
6855 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6856
6857 i = I915_READ(aud_cntrl_st2);
6858 i |= eldv;
6859 I915_WRITE(aud_cntrl_st2, i);
6860
6861}
6862
e0dac65e
WF		 6863static void ironlake_write_eld(struct drm_connector *connector,
6864 struct drm_crtc *crtc)
6865{
6866 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6867 uint8_t *eld = connector->eld;
6868 uint32_t eldv;
6869 uint32_t i;
6870 int len;
6871 int hdmiw_hdmiedid;
b6daa025 6872 int aud_config;
e0dac65e
WF		 6873 int aud_cntl_st;
6874 int aud_cntrl_st2;
9b138a83 6875 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6876
b3f33cbf 6877 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6878 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6879 aud_config = IBX_AUD_CFG(pipe);
6880 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6881 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6882 } else {
9b138a83
WX		 6883 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6884 aud_config = CPT_AUD_CFG(pipe);
6885 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6886 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6887 }
6888
9b138a83 6889 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6890
6891 i = I915_READ(aud_cntl_st);
9b138a83 6892 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6893 if (!i) {
6894 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6895 /* operate blindly on all ports */
1202b4c6
WF		 6896 eldv = IBX_ELD_VALIDB;
6897 eldv |= IBX_ELD_VALIDB << 4;
6898 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6899 } else {
2582a850 6900 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6901 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6902 }
6903
3a9627f4
WF		 6904 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6905 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6906 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6907 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6908 } else
6909 I915_WRITE(aud_config, 0);
e0dac65e 6910
3a9627f4
WF		 6911 if (intel_eld_uptodate(connector,
6912 aud_cntrl_st2, eldv,
6913 aud_cntl_st, IBX_ELD_ADDRESS,
6914 hdmiw_hdmiedid))
6915 return;
6916
e0dac65e
WF		 6917 i = I915_READ(aud_cntrl_st2);
6918 i &= ~eldv;
6919 I915_WRITE(aud_cntrl_st2, i);
6920
6921 if (!eld[0])
6922 return;
6923
e0dac65e 6924 i = I915_READ(aud_cntl_st);
1202b4c6 6925 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6926 I915_WRITE(aud_cntl_st, i);
6927
6928 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6929 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6930 for (i = 0; i < len; i++)
6931 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6932
6933 i = I915_READ(aud_cntrl_st2);
6934 i |= eldv;
6935 I915_WRITE(aud_cntrl_st2, i);
6936}
6937
6938void intel_write_eld(struct drm_encoder *encoder,
6939 struct drm_display_mode *mode)
6940{
6941 struct drm_crtc *crtc = encoder->crtc;
6942 struct drm_connector *connector;
6943 struct drm_device *dev = encoder->dev;
6944 struct drm_i915_private *dev_priv = dev->dev_private;
6945
6946 connector = drm_select_eld(encoder, mode);
6947 if (!connector)
6948 return;
6949
6950 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6951 connector->base.id,
6952 drm_get_connector_name(connector),
6953 connector->encoder->base.id,
6954 drm_get_encoder_name(connector->encoder));
6955
6956 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6957
6958 if (dev_priv->display.write_eld)
6959 dev_priv->display.write_eld(connector, crtc);
6960}
6961
560b85bb
CW		 6962static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6963{
6964 struct drm_device *dev = crtc->dev;
6965 struct drm_i915_private *dev_priv = dev->dev_private;
6966 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6967 bool visible = base != 0;
6968 u32 cntl;
6969
6970 if (intel_crtc->cursor_visible == visible)
6971 return;
6972
9db4a9c7 6973 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6974 if (visible) {
6975 /* On these chipsets we can only modify the base whilst
6976 * the cursor is disabled.
6977 */
9db4a9c7 6978 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6979
6980 cntl &= ~(CURSOR_FORMAT_MASK);
6981 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6982 cntl |= CURSOR_ENABLE |
6983 CURSOR_GAMMA_ENABLE |
6984 CURSOR_FORMAT_ARGB;
6985 } else
6986 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6987 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6988
6989 intel_crtc->cursor_visible = visible;
6990}
6991
6992static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6993{
6994 struct drm_device *dev = crtc->dev;
6995 struct drm_i915_private *dev_priv = dev->dev_private;
6996 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6997 int pipe = intel_crtc->pipe;
6998 bool visible = base != 0;
6999
7000 if (intel_crtc->cursor_visible != visible) {
548f245b 7001 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 7002 if (base) {
7003 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7004 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7005 cntl |= pipe << 28; /* Connect to correct pipe */
7006 } else {
7007 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7008 cntl |= CURSOR_MODE_DISABLE;
7009 }
9db4a9c7 7010 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 7011
7012 intel_crtc->cursor_visible = visible;
7013 }
7014 /* and commit changes on next vblank */
9db4a9c7 7015 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 7016}
7017
65a21cd6
JB		 7018static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7019{
7020 struct drm_device *dev = crtc->dev;
7021 struct drm_i915_private *dev_priv = dev->dev_private;
7022 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7023 int pipe = intel_crtc->pipe;
7024 bool visible = base != 0;
7025
7026 if (intel_crtc->cursor_visible != visible) {
7027 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7028 if (base) {
7029 cntl &= ~CURSOR_MODE;
7030 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7031 } else {
7032 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7033 cntl |= CURSOR_MODE_DISABLE;
7034 }
1f5d76db 7035 if (IS_HASWELL(dev)) {
86d3efce 7036 cntl |= CURSOR_PIPE_CSC_ENABLE;
1f5d76db
PZ		 7037 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7038 }
65a21cd6
JB		 7039 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7040
7041 intel_crtc->cursor_visible = visible;
7042 }
7043 /* and commit changes on next vblank */
7044 I915_WRITE(CURBASE_IVB(pipe), base);
7045}
7046
cda4b7d3 7047/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 7048static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7049 bool on)
cda4b7d3
CW		 7050{
7051 struct drm_device *dev = crtc->dev;
7052 struct drm_i915_private *dev_priv = dev->dev_private;
7053 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7054 int pipe = intel_crtc->pipe;
7055 int x = intel_crtc->cursor_x;
7056 int y = intel_crtc->cursor_y;
d6e4db15 7057 u32 base = 0, pos = 0;
cda4b7d3
CW		 7058 bool visible;
7059
d6e4db15 7060 if (on)
cda4b7d3 7061 base = intel_crtc->cursor_addr;
cda4b7d3 7062
d6e4db15
VS		 7063 if (x >= intel_crtc->config.pipe_src_w)
7064 base = 0;
7065
7066 if (y >= intel_crtc->config.pipe_src_h)
cda4b7d3
CW		 7067 base = 0;
7068
7069 if (x < 0) {
efc9064e 7070 if (x + intel_crtc->cursor_width <= 0)
cda4b7d3
CW		 7071 base = 0;
7072
7073 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7074 x = -x;
7075 }
7076 pos |= x << CURSOR_X_SHIFT;
7077
7078 if (y < 0) {
efc9064e 7079 if (y + intel_crtc->cursor_height <= 0)
cda4b7d3
CW		 7080 base = 0;
7081
7082 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7083 y = -y;
7084 }
7085 pos |= y << CURSOR_Y_SHIFT;
7086
7087 visible = base != 0;
560b85bb 7088 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 7089 return;
7090
0cd83aa9 7091 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 7092 I915_WRITE(CURPOS_IVB(pipe), pos);
7093 ivb_update_cursor(crtc, base);
7094 } else {
7095 I915_WRITE(CURPOS(pipe), pos);
7096 if (IS_845G(dev) || IS_I865G(dev))
7097 i845_update_cursor(crtc, base);
7098 else
7099 i9xx_update_cursor(crtc, base);
7100 }
cda4b7d3
CW		 7101}
7102
79e53945 7103static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 7104 struct drm_file *file,
79e53945
JB		 7105 uint32_t handle,
7106 uint32_t width, uint32_t height)
7107{
7108 struct drm_device *dev = crtc->dev;
7109 struct drm_i915_private *dev_priv = dev->dev_private;
7110 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 7111 struct drm_i915_gem_object *obj;
cda4b7d3 7112 uint32_t addr;
3f8bc370 7113 int ret;
79e53945 7114
79e53945
JB		 7115 /* if we want to turn off the cursor ignore width and height */
7116 if (!handle) {
28c97730 7117 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 7118 addr = 0;
05394f39 7119 obj = NULL;
5004417d 7120 mutex_lock(&dev->struct_mutex);
3f8bc370 7121 goto finish;
79e53945
JB		 7122 }
7123
7124 /* Currently we only support 64x64 cursors */
7125 if (width != 64 || height != 64) {
7126 DRM_ERROR("we currently only support 64x64 cursors\n");
7127 return -EINVAL;
7128 }
7129
05394f39 7130 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 7131 if (&obj->base == NULL)
79e53945
JB		 7132 return -ENOENT;
7133
05394f39 7134 if (obj->base.size < width * height * 4) {
79e53945 7135 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 7136 ret = -ENOMEM;
7137 goto fail;
79e53945
JB		 7138 }
7139
71acb5eb 7140 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 7141 mutex_lock(&dev->struct_mutex);
b295d1b6 7142 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 7143 unsigned alignment;
7144
d9e86c0e
CW		 7145 if (obj->tiling_mode) {
7146 DRM_ERROR("cursor cannot be tiled\n");
7147 ret = -EINVAL;
7148 goto fail_locked;
7149 }
7150
693db184
CW		 7151 /* Note that the w/a also requires 2 PTE of padding following
7152 * the bo. We currently fill all unused PTE with the shadow
7153 * page and so we should always have valid PTE following the
7154 * cursor preventing the VT-d warning.
7155 */
7156 alignment = 0;
7157 if (need_vtd_wa(dev))
7158 alignment = 64*1024;
7159
7160 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 7161 if (ret) {
7162 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 7163 goto fail_locked;
e7b526bb
CW		 7164 }
7165
d9e86c0e
CW		 7166 ret = i915_gem_object_put_fence(obj);
7167 if (ret) {
2da3b9b9 7168 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 7169 goto fail_unpin;
7170 }
7171
f343c5f6 7172 addr = i915_gem_obj_ggtt_offset(obj);
71acb5eb 7173 } else {
6eeefaf3 7174 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 7175 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 7176 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7177 align);
71acb5eb
DA		 7178 if (ret) {
7179 DRM_ERROR("failed to attach phys object\n");
7f9872e0 7180 goto fail_locked;
71acb5eb 7181 }
05394f39 7182 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 7183 }
7184
a6c45cf0 7185 if (IS_GEN2(dev))
14b60391
JB		 7186 I915_WRITE(CURSIZE, (height << 12) | width);
7187
3f8bc370 7188 finish:
3f8bc370 7189 if (intel_crtc->cursor_bo) {
b295d1b6 7190 if (dev_priv->info->cursor_needs_physical) {
05394f39 7191 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 7192 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7193 } else
cc98b413 7194 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
05394f39 7195 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 7196 }
80824003 7197
7f9872e0 7198 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 7199
7200 intel_crtc->cursor_addr = addr;
05394f39 7201 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 7202 intel_crtc->cursor_width = width;
7203 intel_crtc->cursor_height = height;
7204
f2f5f771
VS		 7205 if (intel_crtc->active)
7206 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 7207
79e53945 7208 return 0;
e7b526bb 7209fail_unpin:
cc98b413 7210 i915_gem_object_unpin_from_display_plane(obj);
7f9872e0 7211fail_locked:
34b8686e 7212 mutex_unlock(&dev->struct_mutex);
bc9025bd 7213fail:
05394f39 7214 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 7215 return ret;
79e53945
JB		 7216}
7217
7218static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7219{
79e53945 7220 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7221
cda4b7d3
CW		 7222 intel_crtc->cursor_x = x;
7223 intel_crtc->cursor_y = y;
652c393a 7224
f2f5f771
VS		 7225 if (intel_crtc->active)
7226 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 7227
7228 return 0;
b8c00ac5
DA		 7229}
7230
79e53945 7231static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 7232 u16 *blue, uint32_t start, uint32_t size)
79e53945 7233{
7203425a 7234 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 7235 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7236
7203425a 7237 for (i = start; i < end; i++) {
79e53945
JB		 7238 intel_crtc->lut_r[i] = red[i] >> 8;
7239 intel_crtc->lut_g[i] = green[i] >> 8;
7240 intel_crtc->lut_b[i] = blue[i] >> 8;
7241 }
7242
7243 intel_crtc_load_lut(crtc);
7244}
7245
79e53945
JB		 7246/* VESA 640x480x72Hz mode to set on the pipe */
7247static struct drm_display_mode load_detect_mode = {
7248 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7249 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7250};
7251
d2dff872
CW		 7252static struct drm_framebuffer *
7253intel_framebuffer_create(struct drm_device *dev,
308e5bcb 7254 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 7255 struct drm_i915_gem_object *obj)
7256{
7257 struct intel_framebuffer *intel_fb;
7258 int ret;
7259
7260 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7261 if (!intel_fb) {
7262 drm_gem_object_unreference_unlocked(&obj->base);
7263 return ERR_PTR(-ENOMEM);
7264 }
7265
7266 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7267 if (ret) {
7268 drm_gem_object_unreference_unlocked(&obj->base);
7269 kfree(intel_fb);
7270 return ERR_PTR(ret);
7271 }
7272
7273 return &intel_fb->base;
7274}
7275
7276static u32
7277intel_framebuffer_pitch_for_width(int width, int bpp)
7278{
7279 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7280 return ALIGN(pitch, 64);
7281}
7282
7283static u32
7284intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7285{
7286 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7287 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7288}
7289
7290static struct drm_framebuffer *
7291intel_framebuffer_create_for_mode(struct drm_device *dev,
7292 struct drm_display_mode *mode,
7293 int depth, int bpp)
7294{
7295 struct drm_i915_gem_object *obj;
0fed39bd 7296 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 7297
7298 obj = i915_gem_alloc_object(dev,
7299 intel_framebuffer_size_for_mode(mode, bpp));
7300 if (obj == NULL)
7301 return ERR_PTR(-ENOMEM);
7302
7303 mode_cmd.width = mode->hdisplay;
7304 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 7305 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7306 bpp);
5ca0c34a 7307 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 7308
7309 return intel_framebuffer_create(dev, &mode_cmd, obj);
7310}
7311
7312static struct drm_framebuffer *
7313mode_fits_in_fbdev(struct drm_device *dev,
7314 struct drm_display_mode *mode)
7315{
7316 struct drm_i915_private *dev_priv = dev->dev_private;
7317 struct drm_i915_gem_object *obj;
7318 struct drm_framebuffer *fb;
7319
7320 if (dev_priv->fbdev == NULL)
7321 return NULL;
7322
7323 obj = dev_priv->fbdev->ifb.obj;
7324 if (obj == NULL)
7325 return NULL;
7326
7327 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 7328 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7329 fb->bits_per_pixel))
d2dff872
CW		 7330 return NULL;
7331
01f2c773 7332 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 7333 return NULL;
7334
7335 return fb;
7336}
7337
d2434ab7 7338bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 7339 struct drm_display_mode *mode,
8261b191 7340 struct intel_load_detect_pipe *old)
79e53945
JB		 7341{
7342 struct intel_crtc *intel_crtc;
d2434ab7
DV		 7343 struct intel_encoder *intel_encoder =
7344 intel_attached_encoder(connector);
79e53945 7345 struct drm_crtc *possible_crtc;
4ef69c7a 7346 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 7347 struct drm_crtc *crtc = NULL;
7348 struct drm_device *dev = encoder->dev;
94352cf9 7349 struct drm_framebuffer *fb;
79e53945
JB		 7350 int i = -1;
7351
d2dff872
CW		 7352 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7353 connector->base.id, drm_get_connector_name(connector),
7354 encoder->base.id, drm_get_encoder_name(encoder));
7355
79e53945
JB		 7356 /*
7357 * Algorithm gets a little messy:
7a5e4805 7358 *
79e53945
JB		 7359 * - if the connector already has an assigned crtc, use it (but make
7360 * sure it's on first)
7a5e4805 7361 *
79e53945
JB		 7362 * - try to find the first unused crtc that can drive this connector,
7363 * and use that if we find one
79e53945
JB		 7364 */
7365
7366 /* See if we already have a CRTC for this connector */
7367 if (encoder->crtc) {
7368 crtc = encoder->crtc;
8261b191 7369
7b24056b
DV		 7370 mutex_lock(&crtc->mutex);
7371
24218aac 7372 old->dpms_mode = connector->dpms;
8261b191
CW		 7373 old->load_detect_temp = false;
7374
7375 /* Make sure the crtc and connector are running */
24218aac
DV		 7376 if (connector->dpms != DRM_MODE_DPMS_ON)
7377 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 7378
7173188d 7379 return true;
79e53945
JB		 7380 }
7381
7382 /* Find an unused one (if possible) */
7383 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7384 i++;
7385 if (!(encoder->possible_crtcs & (1 << i)))
7386 continue;
7387 if (!possible_crtc->enabled) {
7388 crtc = possible_crtc;
7389 break;
7390 }
79e53945
JB		 7391 }
7392
7393 /*
7394 * If we didn't find an unused CRTC, don't use any.
7395 */
7396 if (!crtc) {
7173188d
CW		 7397 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7398 return false;
79e53945
JB		 7399 }
7400
7b24056b 7401 mutex_lock(&crtc->mutex);
fc303101
DV		 7402 intel_encoder->new_crtc = to_intel_crtc(crtc);
7403 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 7404
7405 intel_crtc = to_intel_crtc(crtc);
24218aac 7406 old->dpms_mode = connector->dpms;
8261b191 7407 old->load_detect_temp = true;
d2dff872 7408 old->release_fb = NULL;
79e53945 7409
6492711d
CW		 7410 if (!mode)
7411 mode = &load_detect_mode;
79e53945 7412
d2dff872
CW		 7413 /* We need a framebuffer large enough to accommodate all accesses
7414 * that the plane may generate whilst we perform load detection.
7415 * We can not rely on the fbcon either being present (we get called
7416 * during its initialisation to detect all boot displays, or it may
7417 * not even exist) or that it is large enough to satisfy the
7418 * requested mode.
7419 */
94352cf9
DV		 7420 fb = mode_fits_in_fbdev(dev, mode);
7421 if (fb == NULL) {
d2dff872 7422 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 7423 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7424 old->release_fb = fb;
d2dff872
CW		 7425 } else
7426 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 7427 if (IS_ERR(fb)) {
d2dff872 7428 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 7429 mutex_unlock(&crtc->mutex);
0e8b3d3e 7430 return false;
79e53945 7431 }
79e53945 7432
c0c36b94 7433 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 7434 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 7435 if (old->release_fb)
7436 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 7437 mutex_unlock(&crtc->mutex);
0e8b3d3e 7438 return false;
79e53945 7439 }
7173188d 7440
79e53945 7441 /* let the connector get through one full cycle before testing */
9d0498a2 7442 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 7443 return true;
79e53945
JB		 7444}
7445
d2434ab7 7446void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 7447 struct intel_load_detect_pipe *old)
79e53945 7448{
d2434ab7
DV		 7449 struct intel_encoder *intel_encoder =
7450 intel_attached_encoder(connector);
4ef69c7a 7451 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 7452 struct drm_crtc *crtc = encoder->crtc;
79e53945 7453
d2dff872
CW		 7454 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7455 connector->base.id, drm_get_connector_name(connector),
7456 encoder->base.id, drm_get_encoder_name(encoder));
7457
8261b191 7458 if (old->load_detect_temp) {
fc303101
DV		 7459 to_intel_connector(connector)->new_encoder = NULL;
7460 intel_encoder->new_crtc = NULL;
7461 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 7462
36206361
DV		 7463 if (old->release_fb) {
7464 drm_framebuffer_unregister_private(old->release_fb);
7465 drm_framebuffer_unreference(old->release_fb);
7466 }
d2dff872 7467
67c96400 7468 mutex_unlock(&crtc->mutex);
0622a53c 7469 return;
79e53945
JB		 7470 }
7471
c751ce4f 7472 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 7473 if (old->dpms_mode != DRM_MODE_DPMS_ON)
7474 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 7475
7476 mutex_unlock(&crtc->mutex);
79e53945
JB		 7477}
7478
da4a1efa
VS		 7479static int i9xx_pll_refclk(struct drm_device *dev,
7480 const struct intel_crtc_config *pipe_config)
7481{
7482 struct drm_i915_private *dev_priv = dev->dev_private;
7483 u32 dpll = pipe_config->dpll_hw_state.dpll;
7484
7485 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7486 return dev_priv->vbt.lvds_ssc_freq * 1000;
7487 else if (HAS_PCH_SPLIT(dev))
7488 return 120000;
7489 else if (!IS_GEN2(dev))
7490 return 96000;
7491 else
7492 return 48000;
7493}
7494
79e53945 7495/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc
JB		 7496static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7497 struct intel_crtc_config *pipe_config)
79e53945 7498{
f1f644dc 7499 struct drm_device *dev = crtc->base.dev;
79e53945 7500 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 7501 int pipe = pipe_config->cpu_transcoder;
293623f7 7502 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 7503 u32 fp;
7504 intel_clock_t clock;
da4a1efa 7505 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 7506
7507 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 7508 fp = pipe_config->dpll_hw_state.fp0;
79e53945 7509 else
293623f7 7510 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 7511
7512 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 7513 if (IS_PINEVIEW(dev)) {
7514 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7515 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 7516 } else {
7517 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7518 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7519 }
7520
a6c45cf0 7521 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 7522 if (IS_PINEVIEW(dev))
7523 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7524 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 7525 else
7526 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 7527 DPLL_FPA01_P1_POST_DIV_SHIFT);
7528
7529 switch (dpll & DPLL_MODE_MASK) {
7530 case DPLLB_MODE_DAC_SERIAL:
7531 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7532 5 : 10;
7533 break;
7534 case DPLLB_MODE_LVDS:
7535 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7536 7 : 14;
7537 break;
7538 default:
28c97730 7539 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 7540 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 7541 return;
79e53945
JB		 7542 }
7543
ac58c3f0 7544 if (IS_PINEVIEW(dev))
da4a1efa 7545 pineview_clock(refclk, &clock);
ac58c3f0 7546 else
da4a1efa 7547 i9xx_clock(refclk, &clock);
79e53945
JB		 7548 } else {
7549 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7550
7551 if (is_lvds) {
7552 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7553 DPLL_FPA01_P1_POST_DIV_SHIFT);
7554 clock.p2 = 14;
79e53945
JB		 7555 } else {
7556 if (dpll & PLL_P1_DIVIDE_BY_TWO)
7557 clock.p1 = 2;
7558 else {
7559 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7560 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7561 }
7562 if (dpll & PLL_P2_DIVIDE_BY_4)
7563 clock.p2 = 4;
7564 else
7565 clock.p2 = 2;
79e53945 7566 }
da4a1efa
VS		 7567
7568 i9xx_clock(refclk, &clock);
79e53945
JB		 7569 }
7570
18442d08
VS		 7571 /*
7572 * This value includes pixel_multiplier. We will use
241bfc38 7573 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 7574 * encoder's get_config() function.
7575 */
7576 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 7577}
7578
6878da05
VS		 7579int intel_dotclock_calculate(int link_freq,
7580 const struct intel_link_m_n *m_n)
f1f644dc 7581{
f1f644dc
JB		 7582 /*
7583 * The calculation for the data clock is:
1041a02f 7584 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 7585 * But we want to avoid losing precison if possible, so:
1041a02f 7586 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 7587 *
7588 * and the link clock is simpler:
1041a02f 7589 * link_clock = (m * link_clock) / n
f1f644dc
JB		 7590 */
7591
6878da05
VS		 7592 if (!m_n->link_n)
7593 return 0;
f1f644dc 7594
6878da05
VS		 7595 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
7596}
f1f644dc 7597
18442d08
VS		 7598static void ironlake_pch_clock_get(struct intel_crtc *crtc,
7599 struct intel_crtc_config *pipe_config)
6878da05
VS		 7600{
7601 struct drm_device *dev = crtc->base.dev;
79e53945 7602
18442d08
VS		 7603 /* read out port_clock from the DPLL */
7604 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 7605
f1f644dc 7606 /*
18442d08 7607 * This value does not include pixel_multiplier.
241bfc38 7608 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 7609 * agree once we know their relationship in the encoder's
7610 * get_config() function.
79e53945 7611 */
241bfc38 7612 pipe_config->adjusted_mode.crtc_clock =
18442d08
VS		 7613 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
7614 &pipe_config->fdi_m_n);
79e53945
JB		 7615}
7616
7617/** Returns the currently programmed mode of the given pipe. */
7618struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7619 struct drm_crtc *crtc)
7620{
548f245b 7621 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 7622 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 7623 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 7624 struct drm_display_mode *mode;
f1f644dc 7625 struct intel_crtc_config pipe_config;
fe2b8f9d
PZ		 7626 int htot = I915_READ(HTOTAL(cpu_transcoder));
7627 int hsync = I915_READ(HSYNC(cpu_transcoder));
7628 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7629 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 7630 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 7631
7632 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7633 if (!mode)
7634 return NULL;
7635
f1f644dc
JB		 7636 /*
7637 * Construct a pipe_config sufficient for getting the clock info
7638 * back out of crtc_clock_get.
7639 *
7640 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7641 * to use a real value here instead.
7642 */
293623f7 7643 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 7644 pipe_config.pixel_multiplier = 1;
293623f7
VS		 7645 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
7646 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
7647 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 7648 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7649
773ae034 7650 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 7651 mode->hdisplay = (htot & 0xffff) + 1;
7652 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7653 mode->hsync_start = (hsync & 0xffff) + 1;
7654 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7655 mode->vdisplay = (vtot & 0xffff) + 1;
7656 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7657 mode->vsync_start = (vsync & 0xffff) + 1;
7658 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7659
7660 drm_mode_set_name(mode);
79e53945
JB		 7661
7662 return mode;
7663}
7664
3dec0095 7665static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7666{
7667 struct drm_device *dev = crtc->dev;
7668 drm_i915_private_t *dev_priv = dev->dev_private;
7669 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7670 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7671 int dpll_reg = DPLL(pipe);
7672 int dpll;
652c393a 7673
bad720ff 7674 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7675 return;
7676
7677 if (!dev_priv->lvds_downclock_avail)
7678 return;
7679
dbdc6479 7680 dpll = I915_READ(dpll_reg);
652c393a 7681 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7682 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7683
8ac5a6d5 7684 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7685
7686 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7687 I915_WRITE(dpll_reg, dpll);
9d0498a2 7688 intel_wait_for_vblank(dev, pipe);
dbdc6479 7689
652c393a
JB		 7690 dpll = I915_READ(dpll_reg);
7691 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7692 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7693 }
652c393a
JB		 7694}
7695
7696static void intel_decrease_pllclock(struct drm_crtc *crtc)
7697{
7698 struct drm_device *dev = crtc->dev;
7699 drm_i915_private_t *dev_priv = dev->dev_private;
7700 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7701
bad720ff 7702 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7703 return;
7704
7705 if (!dev_priv->lvds_downclock_avail)
7706 return;
7707
7708 /*
7709 * Since this is called by a timer, we should never get here in
7710 * the manual case.
7711 */
7712 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7713 int pipe = intel_crtc->pipe;
7714 int dpll_reg = DPLL(pipe);
7715 int dpll;
f6e5b160 7716
44d98a61 7717 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7718
8ac5a6d5 7719 assert_panel_unlocked(dev_priv, pipe);
652c393a 7720
dc257cf1 7721 dpll = I915_READ(dpll_reg);
652c393a
JB		 7722 dpll |= DISPLAY_RATE_SELECT_FPA1;
7723 I915_WRITE(dpll_reg, dpll);
9d0498a2 7724 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7725 dpll = I915_READ(dpll_reg);
7726 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7727 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7728 }
7729
7730}
7731
f047e395
CW		 7732void intel_mark_busy(struct drm_device *dev)
7733{
c67a470b
PZ		 7734 struct drm_i915_private *dev_priv = dev->dev_private;
7735
7736 hsw_package_c8_gpu_busy(dev_priv);
7737 i915_update_gfx_val(dev_priv);
f047e395
CW		 7738}
7739
7740void intel_mark_idle(struct drm_device *dev)
652c393a 7741{
c67a470b 7742 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 7743 struct drm_crtc *crtc;
652c393a 7744
c67a470b
PZ		 7745 hsw_package_c8_gpu_idle(dev_priv);
7746
652c393a
JB		 7747 if (!i915_powersave)
7748 return;
7749
652c393a 7750 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7751 if (!crtc->fb)
7752 continue;
7753
725a5b54 7754 intel_decrease_pllclock(crtc);
652c393a 7755 }
b29c19b6
CW		 7756
7757 if (dev_priv->info->gen >= 6)
7758 gen6_rps_idle(dev->dev_private);
652c393a
JB		 7759}
7760
c65355bb
CW		 7761void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7762 struct intel_ring_buffer *ring)
652c393a 7763{
f047e395
CW		 7764 struct drm_device *dev = obj->base.dev;
7765 struct drm_crtc *crtc;
652c393a 7766
f047e395 7767 if (!i915_powersave)
acb87dfb
CW		 7768 return;
7769
652c393a
JB		 7770 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7771 if (!crtc->fb)
7772 continue;
7773
c65355bb
CW		 7774 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7775 continue;
7776
7777 intel_increase_pllclock(crtc);
7778 if (ring && intel_fbc_enabled(dev))
7779 ring->fbc_dirty = true;
652c393a
JB		 7780 }
7781}
7782
79e53945
JB		 7783static void intel_crtc_destroy(struct drm_crtc *crtc)
7784{
7785 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7786 struct drm_device *dev = crtc->dev;
7787 struct intel_unpin_work *work;
7788 unsigned long flags;
7789
7790 spin_lock_irqsave(&dev->event_lock, flags);
7791 work = intel_crtc->unpin_work;
7792 intel_crtc->unpin_work = NULL;
7793 spin_unlock_irqrestore(&dev->event_lock, flags);
7794
7795 if (work) {
7796 cancel_work_sync(&work->work);
7797 kfree(work);
7798 }
79e53945 7799
40ccc72b
MK		 7800 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7801
79e53945 7802 drm_crtc_cleanup(crtc);
67e77c5a 7803
79e53945
JB		 7804 kfree(intel_crtc);
7805}
7806
6b95a207
KH		 7807static void intel_unpin_work_fn(struct work_struct *__work)
7808{
7809 struct intel_unpin_work *work =
7810 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7811 struct drm_device *dev = work->crtc->dev;
6b95a207 7812
b4a98e57 7813 mutex_lock(&dev->struct_mutex);
1690e1eb 7814 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7815 drm_gem_object_unreference(&work->pending_flip_obj->base);
7816 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7817
b4a98e57
CW		 7818 intel_update_fbc(dev);
7819 mutex_unlock(&dev->struct_mutex);
7820
7821 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7822 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7823
6b95a207
KH		 7824 kfree(work);
7825}
7826
1afe3e9d 7827static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7828 struct drm_crtc *crtc)
6b95a207
KH		 7829{
7830 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7831 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7832 struct intel_unpin_work *work;
6b95a207
KH		 7833 unsigned long flags;
7834
7835 /* Ignore early vblank irqs */
7836 if (intel_crtc == NULL)
7837 return;
7838
7839 spin_lock_irqsave(&dev->event_lock, flags);
7840 work = intel_crtc->unpin_work;
e7d841ca
CW		 7841
7842 /* Ensure we don't miss a work->pending update ... */
7843 smp_rmb();
7844
7845 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7846 spin_unlock_irqrestore(&dev->event_lock, flags);
7847 return;
7848 }
7849
e7d841ca
CW		 7850 /* and that the unpin work is consistent wrt ->pending. */
7851 smp_rmb();
7852
6b95a207 7853 intel_crtc->unpin_work = NULL;
6b95a207 7854
45a066eb
RC		 7855 if (work->event)
7856 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7857
0af7e4df
MK		 7858 drm_vblank_put(dev, intel_crtc->pipe);
7859
6b95a207
KH		 7860 spin_unlock_irqrestore(&dev->event_lock, flags);
7861
2c10d571 7862 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7863
7864 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7865
7866 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7867}
7868
1afe3e9d
JB		 7869void intel_finish_page_flip(struct drm_device *dev, int pipe)
7870{
7871 drm_i915_private_t *dev_priv = dev->dev_private;
7872 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7873
49b14a5c 7874 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7875}
7876
7877void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7878{
7879 drm_i915_private_t *dev_priv = dev->dev_private;
7880 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7881
49b14a5c 7882 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7883}
7884
6b95a207
KH		 7885void intel_prepare_page_flip(struct drm_device *dev, int plane)
7886{
7887 drm_i915_private_t *dev_priv = dev->dev_private;
7888 struct intel_crtc *intel_crtc =
7889 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7890 unsigned long flags;
7891
e7d841ca
CW		 7892 /* NB: An MMIO update of the plane base pointer will also
7893 * generate a page-flip completion irq, i.e. every modeset
7894 * is also accompanied by a spurious intel_prepare_page_flip().
7895 */
6b95a207 7896 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7897 if (intel_crtc->unpin_work)
7898 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7899 spin_unlock_irqrestore(&dev->event_lock, flags);
7900}
7901
e7d841ca
CW		 7902inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7903{
7904 /* Ensure that the work item is consistent when activating it ... */
7905 smp_wmb();
7906 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7907 /* and that it is marked active as soon as the irq could fire. */
7908 smp_wmb();
7909}
7910
8c9f3aaf
JB		 7911static int intel_gen2_queue_flip(struct drm_device *dev,
7912 struct drm_crtc *crtc,
7913 struct drm_framebuffer *fb,
ed8d1975
KP		 7914 struct drm_i915_gem_object *obj,
7915 uint32_t flags)
8c9f3aaf
JB		 7916{
7917 struct drm_i915_private *dev_priv = dev->dev_private;
7918 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7919 u32 flip_mask;
6d90c952 7920 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7921 int ret;
7922
6d90c952 7923 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7924 if (ret)
83d4092b 7925 goto err;
8c9f3aaf 7926
6d90c952 7927 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7928 if (ret)
83d4092b 7929 goto err_unpin;
8c9f3aaf
JB		 7930
7931 /* Can't queue multiple flips, so wait for the previous
7932 * one to finish before executing the next.
7933 */
7934 if (intel_crtc->plane)
7935 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7936 else
7937 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7938 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7939 intel_ring_emit(ring, MI_NOOP);
7940 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7941 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7942 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7943 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952 7944 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7945
7946 intel_mark_page_flip_active(intel_crtc);
09246732 7947 __intel_ring_advance(ring);
83d4092b
CW		 7948 return 0;
7949
7950err_unpin:
7951 intel_unpin_fb_obj(obj);
7952err:
8c9f3aaf
JB		 7953 return ret;
7954}
7955
7956static int intel_gen3_queue_flip(struct drm_device *dev,
7957 struct drm_crtc *crtc,
7958 struct drm_framebuffer *fb,
ed8d1975
KP		 7959 struct drm_i915_gem_object *obj,
7960 uint32_t flags)
8c9f3aaf
JB		 7961{
7962 struct drm_i915_private *dev_priv = dev->dev_private;
7963 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7964 u32 flip_mask;
6d90c952 7965 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7966 int ret;
7967
6d90c952 7968 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7969 if (ret)
83d4092b 7970 goto err;
8c9f3aaf 7971
6d90c952 7972 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7973 if (ret)
83d4092b 7974 goto err_unpin;
8c9f3aaf
JB		 7975
7976 if (intel_crtc->plane)
7977 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7978 else
7979 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7980 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7981 intel_ring_emit(ring, MI_NOOP);
7982 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7983 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7984 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7985 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952
DV		 7986 intel_ring_emit(ring, MI_NOOP);
7987
e7d841ca 7988 intel_mark_page_flip_active(intel_crtc);
09246732 7989 __intel_ring_advance(ring);
83d4092b
CW		 7990 return 0;
7991
7992err_unpin:
7993 intel_unpin_fb_obj(obj);
7994err:
8c9f3aaf
JB		 7995 return ret;
7996}
7997
7998static int intel_gen4_queue_flip(struct drm_device *dev,
7999 struct drm_crtc *crtc,
8000 struct drm_framebuffer *fb,
ed8d1975
KP		 8001 struct drm_i915_gem_object *obj,
8002 uint32_t flags)
8c9f3aaf
JB		 8003{
8004 struct drm_i915_private *dev_priv = dev->dev_private;
8005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8006 uint32_t pf, pipesrc;
6d90c952 8007 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 8008 int ret;
8009
6d90c952 8010 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 8011 if (ret)
83d4092b 8012 goto err;
8c9f3aaf 8013
6d90c952 8014 ret = intel_ring_begin(ring, 4);
8c9f3aaf 8015 if (ret)
83d4092b 8016 goto err_unpin;
8c9f3aaf
JB		 8017
8018 /* i965+ uses the linear or tiled offsets from the
8019 * Display Registers (which do not change across a page-flip)
8020 * so we need only reprogram the base address.
8021 */
6d90c952
DV		 8022 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8023 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8024 intel_ring_emit(ring, fb->pitches[0]);
c2c75131 8025 intel_ring_emit(ring,
f343c5f6 8026 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
c2c75131 8027 obj->tiling_mode);
8c9f3aaf
JB		 8028
8029 /* XXX Enabling the panel-fitter across page-flip is so far
8030 * untested on non-native modes, so ignore it for now.
8031 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8032 */
8033 pf = 0;
8034 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 8035 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 8036
8037 intel_mark_page_flip_active(intel_crtc);
09246732 8038 __intel_ring_advance(ring);
83d4092b
CW		 8039 return 0;
8040
8041err_unpin:
8042 intel_unpin_fb_obj(obj);
8043err:
8c9f3aaf
JB		 8044 return ret;
8045}
8046
8047static int intel_gen6_queue_flip(struct drm_device *dev,
8048 struct drm_crtc *crtc,
8049 struct drm_framebuffer *fb,
ed8d1975
KP		 8050 struct drm_i915_gem_object *obj,
8051 uint32_t flags)
8c9f3aaf
JB		 8052{
8053 struct drm_i915_private *dev_priv = dev->dev_private;
8054 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 8055 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 8056 uint32_t pf, pipesrc;
8057 int ret;
8058
6d90c952 8059 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 8060 if (ret)
83d4092b 8061 goto err;
8c9f3aaf 8062
6d90c952 8063 ret = intel_ring_begin(ring, 4);
8c9f3aaf 8064 if (ret)
83d4092b 8065 goto err_unpin;
8c9f3aaf 8066
6d90c952
DV		 8067 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8068 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8069 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
f343c5f6 8070 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8c9f3aaf 8071
dc257cf1
DV		 8072 /* Contrary to the suggestions in the documentation,
8073 * "Enable Panel Fitter" does not seem to be required when page
8074 * flipping with a non-native mode, and worse causes a normal
8075 * modeset to fail.
8076 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8077 */
8078 pf = 0;
8c9f3aaf 8079 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 8080 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 8081
8082 intel_mark_page_flip_active(intel_crtc);
09246732 8083 __intel_ring_advance(ring);
83d4092b
CW		 8084 return 0;
8085
8086err_unpin:
8087 intel_unpin_fb_obj(obj);
8088err:
8c9f3aaf
JB		 8089 return ret;
8090}
8091
7c9017e5
JB		 8092static int intel_gen7_queue_flip(struct drm_device *dev,
8093 struct drm_crtc *crtc,
8094 struct drm_framebuffer *fb,
ed8d1975
KP		 8095 struct drm_i915_gem_object *obj,
8096 uint32_t flags)
7c9017e5
JB		 8097{
8098 struct drm_i915_private *dev_priv = dev->dev_private;
8099 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ffe74d75 8100 struct intel_ring_buffer *ring;
cb05d8de 8101 uint32_t plane_bit = 0;
ffe74d75
CW		 8102 int len, ret;
8103
8104 ring = obj->ring;
1c5fd085 8105 if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
ffe74d75 8106 ring = &dev_priv->ring[BCS];
7c9017e5
JB		 8107
8108 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8109 if (ret)
83d4092b 8110 goto err;
7c9017e5 8111
cb05d8de
DV		 8112 switch(intel_crtc->plane) {
8113 case PLANE_A:
8114 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8115 break;
8116 case PLANE_B:
8117 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8118 break;
8119 case PLANE_C:
8120 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8121 break;
8122 default:
8123 WARN_ONCE(1, "unknown plane in flip command\n");
8124 ret = -ENODEV;
ab3951eb 8125 goto err_unpin;
cb05d8de
DV		 8126 }
8127
ffe74d75
CW		 8128 len = 4;
8129 if (ring->id == RCS)
8130 len += 6;
8131
8132 ret = intel_ring_begin(ring, len);
7c9017e5 8133 if (ret)
83d4092b 8134 goto err_unpin;
7c9017e5 8135
ffe74d75
CW		 8136 /* Unmask the flip-done completion message. Note that the bspec says that
8137 * we should do this for both the BCS and RCS, and that we must not unmask
8138 * more than one flip event at any time (or ensure that one flip message
8139 * can be sent by waiting for flip-done prior to queueing new flips).
8140 * Experimentation says that BCS works despite DERRMR masking all
8141 * flip-done completion events and that unmasking all planes at once
8142 * for the RCS also doesn't appear to drop events. Setting the DERRMR
8143 * to zero does lead to lockups within MI_DISPLAY_FLIP.
8144 */
8145 if (ring->id == RCS) {
8146 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8147 intel_ring_emit(ring, DERRMR);
8148 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8149 DERRMR_PIPEB_PRI_FLIP_DONE |
8150 DERRMR_PIPEC_PRI_FLIP_DONE));
8151 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
8152 intel_ring_emit(ring, DERRMR);
8153 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8154 }
8155
cb05d8de 8156 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 8157 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
f343c5f6 8158 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7c9017e5 8159 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 8160
8161 intel_mark_page_flip_active(intel_crtc);
09246732 8162 __intel_ring_advance(ring);
83d4092b
CW		 8163 return 0;
8164
8165err_unpin:
8166 intel_unpin_fb_obj(obj);
8167err:
7c9017e5
JB		 8168 return ret;
8169}
8170
8c9f3aaf
JB		 8171static int intel_default_queue_flip(struct drm_device *dev,
8172 struct drm_crtc *crtc,
8173 struct drm_framebuffer *fb,
ed8d1975
KP		 8174 struct drm_i915_gem_object *obj,
8175 uint32_t flags)
8c9f3aaf
JB		 8176{
8177 return -ENODEV;
8178}
8179
6b95a207
KH		 8180static int intel_crtc_page_flip(struct drm_crtc *crtc,
8181 struct drm_framebuffer *fb,
ed8d1975
KP		 8182 struct drm_pending_vblank_event *event,
8183 uint32_t page_flip_flags)
6b95a207
KH		 8184{
8185 struct drm_device *dev = crtc->dev;
8186 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 8187 struct drm_framebuffer *old_fb = crtc->fb;
8188 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 8189 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8190 struct intel_unpin_work *work;
8c9f3aaf 8191 unsigned long flags;
52e68630 8192 int ret;
6b95a207 8193
e6a595d2
VS		 8194 /* Can't change pixel format via MI display flips. */
8195 if (fb->pixel_format != crtc->fb->pixel_format)
8196 return -EINVAL;
8197
8198 /*
8199 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8200 * Note that pitch changes could also affect these register.
8201 */
8202 if (INTEL_INFO(dev)->gen > 3 &&
8203 (fb->offsets[0] != crtc->fb->offsets[0] ||
8204 fb->pitches[0] != crtc->fb->pitches[0]))
8205 return -EINVAL;
8206
b14c5679 8207 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 8208 if (work == NULL)
8209 return -ENOMEM;
8210
6b95a207 8211 work->event = event;
b4a98e57 8212 work->crtc = crtc;
4a35f83b 8213 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 8214 INIT_WORK(&work->work, intel_unpin_work_fn);
8215
7317c75e
JB		 8216 ret = drm_vblank_get(dev, intel_crtc->pipe);
8217 if (ret)
8218 goto free_work;
8219
6b95a207
KH		 8220 /* We borrow the event spin lock for protecting unpin_work */
8221 spin_lock_irqsave(&dev->event_lock, flags);
8222 if (intel_crtc->unpin_work) {
8223 spin_unlock_irqrestore(&dev->event_lock, flags);
8224 kfree(work);
7317c75e 8225 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 8226
8227 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 8228 return -EBUSY;
8229 }
8230 intel_crtc->unpin_work = work;
8231 spin_unlock_irqrestore(&dev->event_lock, flags);
8232
b4a98e57
CW		 8233 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8234 flush_workqueue(dev_priv->wq);
8235
79158103
CW		 8236 ret = i915_mutex_lock_interruptible(dev);
8237 if (ret)
8238 goto cleanup;
6b95a207 8239
75dfca80 8240 /* Reference the objects for the scheduled work. */
05394f39
CW		 8241 drm_gem_object_reference(&work->old_fb_obj->base);
8242 drm_gem_object_reference(&obj->base);
6b95a207
KH		 8243
8244 crtc->fb = fb;
96b099fd 8245
e1f99ce6 8246 work->pending_flip_obj = obj;
e1f99ce6 8247
4e5359cd
SF		 8248 work->enable_stall_check = true;
8249
b4a98e57 8250 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 8251 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 8252
ed8d1975 8253 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8c9f3aaf
JB		 8254 if (ret)
8255 goto cleanup_pending;
6b95a207 8256
7782de3b 8257 intel_disable_fbc(dev);
c65355bb 8258 intel_mark_fb_busy(obj, NULL);
6b95a207
KH		 8259 mutex_unlock(&dev->struct_mutex);
8260
e5510fac
JB		 8261 trace_i915_flip_request(intel_crtc->plane, obj);
8262
6b95a207 8263 return 0;
96b099fd 8264
8c9f3aaf 8265cleanup_pending:
b4a98e57 8266 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 8267 crtc->fb = old_fb;
05394f39
CW		 8268 drm_gem_object_unreference(&work->old_fb_obj->base);
8269 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 8270 mutex_unlock(&dev->struct_mutex);
8271
79158103 8272cleanup:
96b099fd
CW		 8273 spin_lock_irqsave(&dev->event_lock, flags);
8274 intel_crtc->unpin_work = NULL;
8275 spin_unlock_irqrestore(&dev->event_lock, flags);
8276
7317c75e
JB		 8277 drm_vblank_put(dev, intel_crtc->pipe);
8278free_work:
96b099fd
CW		 8279 kfree(work);
8280
8281 return ret;
6b95a207
KH		 8282}
8283
f6e5b160 8284static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 8285 .mode_set_base_atomic = intel_pipe_set_base_atomic,
8286 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 8287};
8288
50f56119
DV		 8289static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8290 struct drm_crtc *crtc)
8291{
8292 struct drm_device *dev;
8293 struct drm_crtc *tmp;
8294 int crtc_mask = 1;
47f1c6c9 8295
50f56119 8296 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 8297
50f56119 8298 dev = crtc->dev;
47f1c6c9 8299
50f56119
DV		 8300 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8301 if (tmp == crtc)
8302 break;
8303 crtc_mask <<= 1;
8304 }
47f1c6c9 8305
50f56119
DV		 8306 if (encoder->possible_crtcs & crtc_mask)
8307 return true;
8308 return false;
47f1c6c9 8309}
79e53945 8310
9a935856
DV		 8311/**
8312 * intel_modeset_update_staged_output_state
8313 *
8314 * Updates the staged output configuration state, e.g. after we've read out the
8315 * current hw state.
8316 */
8317static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 8318{
9a935856
DV		 8319 struct intel_encoder *encoder;
8320 struct intel_connector *connector;
f6e5b160 8321
9a935856
DV		 8322 list_for_each_entry(connector, &dev->mode_config.connector_list,
8323 base.head) {
8324 connector->new_encoder =
8325 to_intel_encoder(connector->base.encoder);
8326 }
f6e5b160 8327
9a935856
DV		 8328 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8329 base.head) {
8330 encoder->new_crtc =
8331 to_intel_crtc(encoder->base.crtc);
8332 }
f6e5b160
CW		 8333}
8334
9a935856
DV		 8335/**
8336 * intel_modeset_commit_output_state
8337 *
8338 * This function copies the stage display pipe configuration to the real one.
8339 */
8340static void intel_modeset_commit_output_state(struct drm_device *dev)
8341{
8342 struct intel_encoder *encoder;
8343 struct intel_connector *connector;
f6e5b160 8344
9a935856
DV		 8345 list_for_each_entry(connector, &dev->mode_config.connector_list,
8346 base.head) {
8347 connector->base.encoder = &connector->new_encoder->base;
8348 }
f6e5b160 8349
9a935856
DV		 8350 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8351 base.head) {
8352 encoder->base.crtc = &encoder->new_crtc->base;
8353 }
8354}
8355
050f7aeb
DV		 8356static void
8357connected_sink_compute_bpp(struct intel_connector * connector,
8358 struct intel_crtc_config *pipe_config)
8359{
8360 int bpp = pipe_config->pipe_bpp;
8361
8362 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8363 connector->base.base.id,
8364 drm_get_connector_name(&connector->base));
8365
8366 /* Don't use an invalid EDID bpc value */
8367 if (connector->base.display_info.bpc &&
8368 connector->base.display_info.bpc * 3 < bpp) {
8369 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8370 bpp, connector->base.display_info.bpc*3);
8371 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8372 }
8373
8374 /* Clamp bpp to 8 on screens without EDID 1.4 */
8375 if (connector->base.display_info.bpc == 0 && bpp > 24) {
8376 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8377 bpp);
8378 pipe_config->pipe_bpp = 24;
8379 }
8380}
8381
4e53c2e0 8382static int
050f7aeb
DV		 8383compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8384 struct drm_framebuffer *fb,
8385 struct intel_crtc_config *pipe_config)
4e53c2e0 8386{
050f7aeb
DV		 8387 struct drm_device *dev = crtc->base.dev;
8388 struct intel_connector *connector;
4e53c2e0
DV		 8389 int bpp;
8390
d42264b1
DV		 8391 switch (fb->pixel_format) {
8392 case DRM_FORMAT_C8:
4e53c2e0
DV		 8393 bpp = 8*3; /* since we go through a colormap */
8394 break;
d42264b1
DV		 8395 case DRM_FORMAT_XRGB1555:
8396 case DRM_FORMAT_ARGB1555:
8397 /* checked in intel_framebuffer_init already */
8398 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8399 return -EINVAL;
8400 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 8401 bpp = 6*3; /* min is 18bpp */
8402 break;
d42264b1
DV		 8403 case DRM_FORMAT_XBGR8888:
8404 case DRM_FORMAT_ABGR8888:
8405 /* checked in intel_framebuffer_init already */
8406 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8407 return -EINVAL;
8408 case DRM_FORMAT_XRGB8888:
8409 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 8410 bpp = 8*3;
8411 break;
d42264b1
DV		 8412 case DRM_FORMAT_XRGB2101010:
8413 case DRM_FORMAT_ARGB2101010:
8414 case DRM_FORMAT_XBGR2101010:
8415 case DRM_FORMAT_ABGR2101010:
8416 /* checked in intel_framebuffer_init already */
8417 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 8418 return -EINVAL;
4e53c2e0
DV		 8419 bpp = 10*3;
8420 break;
baba133a 8421 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 8422 default:
8423 DRM_DEBUG_KMS("unsupported depth\n");
8424 return -EINVAL;
8425 }
8426
4e53c2e0
DV		 8427 pipe_config->pipe_bpp = bpp;
8428
8429 /* Clamp display bpp to EDID value */
8430 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 8431 base.head) {
1b829e05
DV		 8432 if (!connector->new_encoder ||
8433 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 8434 continue;
8435
050f7aeb 8436 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 8437 }
8438
8439 return bpp;
8440}
8441
644db711
DV		 8442static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
8443{
8444 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8445 "type: 0x%x flags: 0x%x\n",
1342830c 8446 mode->crtc_clock,
644db711
DV		 8447 mode->crtc_hdisplay, mode->crtc_hsync_start,
8448 mode->crtc_hsync_end, mode->crtc_htotal,
8449 mode->crtc_vdisplay, mode->crtc_vsync_start,
8450 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
8451}
8452
c0b03411
DV		 8453static void intel_dump_pipe_config(struct intel_crtc *crtc,
8454 struct intel_crtc_config *pipe_config,
8455 const char *context)
8456{
8457 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8458 context, pipe_name(crtc->pipe));
8459
8460 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8461 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8462 pipe_config->pipe_bpp, pipe_config->dither);
8463 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8464 pipe_config->has_pch_encoder,
8465 pipe_config->fdi_lanes,
8466 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8467 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8468 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 8469 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8470 pipe_config->has_dp_encoder,
8471 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8472 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8473 pipe_config->dp_m_n.tu);
c0b03411
DV		 8474 DRM_DEBUG_KMS("requested mode:\n");
8475 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8476 DRM_DEBUG_KMS("adjusted mode:\n");
8477 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
644db711 8478 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
d71b8d4a 8479 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 8480 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8481 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
c0b03411
DV		 8482 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8483 pipe_config->gmch_pfit.control,
8484 pipe_config->gmch_pfit.pgm_ratios,
8485 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 8486 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 8487 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 8488 pipe_config->pch_pfit.size,
8489 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 8490 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 8491 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
c0b03411
DV		 8492}
8493
accfc0c5
DV		 8494static bool check_encoder_cloning(struct drm_crtc *crtc)
8495{
8496 int num_encoders = 0;
8497 bool uncloneable_encoders = false;
8498 struct intel_encoder *encoder;
8499
8500 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8501 base.head) {
8502 if (&encoder->new_crtc->base != crtc)
8503 continue;
8504
8505 num_encoders++;
8506 if (!encoder->cloneable)
8507 uncloneable_encoders = true;
8508 }
8509
8510 return !(num_encoders > 1 && uncloneable_encoders);
8511}
8512
b8cecdf5
DV		 8513static struct intel_crtc_config *
8514intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 8515 struct drm_framebuffer *fb,
b8cecdf5 8516 struct drm_display_mode *mode)
ee7b9f93 8517{
7758a113 8518 struct drm_device *dev = crtc->dev;
7758a113 8519 struct intel_encoder *encoder;
b8cecdf5 8520 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 8521 int plane_bpp, ret = -EINVAL;
8522 bool retry = true;
ee7b9f93 8523
accfc0c5
DV		 8524 if (!check_encoder_cloning(crtc)) {
8525 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8526 return ERR_PTR(-EINVAL);
8527 }
8528
b8cecdf5
DV		 8529 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8530 if (!pipe_config)
7758a113
DV		 8531 return ERR_PTR(-ENOMEM);
8532
b8cecdf5
DV		 8533 drm_mode_copy(&pipe_config->adjusted_mode, mode);
8534 drm_mode_copy(&pipe_config->requested_mode, mode);
37327abd 8535
e143a21c
DV		 8536 pipe_config->cpu_transcoder =
8537 (enum transcoder) to_intel_crtc(crtc)->pipe;
c0d43d62 8538 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 8539
2960bc9c
ID		 8540 /*
8541 * Sanitize sync polarity flags based on requested ones. If neither
8542 * positive or negative polarity is requested, treat this as meaning
8543 * negative polarity.
8544 */
8545 if (!(pipe_config->adjusted_mode.flags &
8546 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8547 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8548
8549 if (!(pipe_config->adjusted_mode.flags &
8550 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8551 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8552
050f7aeb
DV		 8553 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8554 * plane pixel format and any sink constraints into account. Returns the
8555 * source plane bpp so that dithering can be selected on mismatches
8556 * after encoders and crtc also have had their say. */
8557 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8558 fb, pipe_config);
4e53c2e0
DV		 8559 if (plane_bpp < 0)
8560 goto fail;
8561
e41a56be
VS		 8562 /*
8563 * Determine the real pipe dimensions. Note that stereo modes can
8564 * increase the actual pipe size due to the frame doubling and
8565 * insertion of additional space for blanks between the frame. This
8566 * is stored in the crtc timings. We use the requested mode to do this
8567 * computation to clearly distinguish it from the adjusted mode, which
8568 * can be changed by the connectors in the below retry loop.
8569 */
8570 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
8571 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
8572 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
8573
e29c22c0 8574encoder_retry:
ef1b460d 8575 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 8576 pipe_config->port_clock = 0;
ef1b460d 8577 pipe_config->pixel_multiplier = 1;
ff9a6750 8578
135c81b8 8579 /* Fill in default crtc timings, allow encoders to overwrite them. */
6ce70f5e 8580 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
135c81b8 8581
7758a113
DV		 8582 /* Pass our mode to the connectors and the CRTC to give them a chance to
8583 * adjust it according to limitations or connector properties, and also
8584 * a chance to reject the mode entirely.
47f1c6c9 8585 */
7758a113
DV		 8586 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8587 base.head) {
47f1c6c9 8588
7758a113
DV		 8589 if (&encoder->new_crtc->base != crtc)
8590 continue;
7ae89233 8591
efea6e8e
DV		 8592 if (!(encoder->compute_config(encoder, pipe_config))) {
8593 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 8594 goto fail;
8595 }
ee7b9f93 8596 }
47f1c6c9 8597
ff9a6750
DV		 8598 /* Set default port clock if not overwritten by the encoder. Needs to be
8599 * done afterwards in case the encoder adjusts the mode. */
8600 if (!pipe_config->port_clock)
241bfc38
DL		 8601 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
8602 * pipe_config->pixel_multiplier;
ff9a6750 8603
a43f6e0f 8604 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 8605 if (ret < 0) {
7758a113
DV		 8606 DRM_DEBUG_KMS("CRTC fixup failed\n");
8607 goto fail;
ee7b9f93 8608 }
e29c22c0
DV		 8609
8610 if (ret == RETRY) {
8611 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8612 ret = -EINVAL;
8613 goto fail;
8614 }
8615
8616 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8617 retry = false;
8618 goto encoder_retry;
8619 }
8620
4e53c2e0
DV		 8621 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8622 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8623 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8624
b8cecdf5 8625 return pipe_config;
7758a113 8626fail:
b8cecdf5 8627 kfree(pipe_config);
e29c22c0 8628 return ERR_PTR(ret);
ee7b9f93 8629}
47f1c6c9 8630
e2e1ed41
DV		 8631/* Computes which crtcs are affected and sets the relevant bits in the mask. For
8632 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8633static void
8634intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8635 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 8636{
8637 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 8638 struct drm_device *dev = crtc->dev;
8639 struct intel_encoder *encoder;
8640 struct intel_connector *connector;
8641 struct drm_crtc *tmp_crtc;
79e53945 8642
e2e1ed41 8643 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 8644
e2e1ed41
DV		 8645 /* Check which crtcs have changed outputs connected to them, these need
8646 * to be part of the prepare_pipes mask. We don't (yet) support global
8647 * modeset across multiple crtcs, so modeset_pipes will only have one
8648 * bit set at most. */
8649 list_for_each_entry(connector, &dev->mode_config.connector_list,
8650 base.head) {
8651 if (connector->base.encoder == &connector->new_encoder->base)
8652 continue;
79e53945 8653
e2e1ed41
DV		 8654 if (connector->base.encoder) {
8655 tmp_crtc = connector->base.encoder->crtc;
8656
8657 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8658 }
8659
8660 if (connector->new_encoder)
8661 *prepare_pipes |=
8662 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 8663 }
8664
e2e1ed41
DV		 8665 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8666 base.head) {
8667 if (encoder->base.crtc == &encoder->new_crtc->base)
8668 continue;
8669
8670 if (encoder->base.crtc) {
8671 tmp_crtc = encoder->base.crtc;
8672
8673 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8674 }
8675
8676 if (encoder->new_crtc)
8677 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 8678 }
8679
e2e1ed41
DV		 8680 /* Check for any pipes that will be fully disabled ... */
8681 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8682 base.head) {
8683 bool used = false;
22fd0fab 8684
e2e1ed41
DV		 8685 /* Don't try to disable disabled crtcs. */
8686 if (!intel_crtc->base.enabled)
8687 continue;
7e7d76c3 8688
e2e1ed41
DV		 8689 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8690 base.head) {
8691 if (encoder->new_crtc == intel_crtc)
8692 used = true;
8693 }
8694
8695 if (!used)
8696 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 8697 }
8698
e2e1ed41
DV		 8699
8700 /* set_mode is also used to update properties on life display pipes. */
8701 intel_crtc = to_intel_crtc(crtc);
8702 if (crtc->enabled)
8703 *prepare_pipes |= 1 << intel_crtc->pipe;
8704
b6c5164d
DV		 8705 /*
8706 * For simplicity do a full modeset on any pipe where the output routing
8707 * changed. We could be more clever, but that would require us to be
8708 * more careful with calling the relevant encoder->mode_set functions.
8709 */
e2e1ed41
DV		 8710 if (*prepare_pipes)
8711 *modeset_pipes = *prepare_pipes;
8712
8713 /* ... and mask these out. */
8714 *modeset_pipes &= ~(*disable_pipes);
8715 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 8716
8717 /*
8718 * HACK: We don't (yet) fully support global modesets. intel_set_config
8719 * obies this rule, but the modeset restore mode of
8720 * intel_modeset_setup_hw_state does not.
8721 */
8722 *modeset_pipes &= 1 << intel_crtc->pipe;
8723 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 8724
8725 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8726 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 8727}
79e53945 8728
ea9d758d 8729static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 8730{
ea9d758d 8731 struct drm_encoder *encoder;
f6e5b160 8732 struct drm_device *dev = crtc->dev;
f6e5b160 8733
ea9d758d
DV		 8734 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8735 if (encoder->crtc == crtc)
8736 return true;
8737
8738 return false;
8739}
8740
8741static void
8742intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8743{
8744 struct intel_encoder *intel_encoder;
8745 struct intel_crtc *intel_crtc;
8746 struct drm_connector *connector;
8747
8748 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8749 base.head) {
8750 if (!intel_encoder->base.crtc)
8751 continue;
8752
8753 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8754
8755 if (prepare_pipes & (1 << intel_crtc->pipe))
8756 intel_encoder->connectors_active = false;
8757 }
8758
8759 intel_modeset_commit_output_state(dev);
8760
8761 /* Update computed state. */
8762 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8763 base.head) {
8764 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8765 }
8766
8767 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8768 if (!connector->encoder || !connector->encoder->crtc)
8769 continue;
8770
8771 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8772
8773 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8774 struct drm_property *dpms_property =
8775 dev->mode_config.dpms_property;
8776
ea9d758d 8777 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8778 drm_object_property_set_value(&connector->base,
68d34720
DV		 8779 dpms_property,
8780 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8781
8782 intel_encoder = to_intel_encoder(connector->encoder);
8783 intel_encoder->connectors_active = true;
8784 }
8785 }
8786
8787}
8788
3bd26263 8789static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 8790{
3bd26263 8791 int diff;
f1f644dc
JB		 8792
8793 if (clock1 == clock2)
8794 return true;
8795
8796 if (!clock1 || !clock2)
8797 return false;
8798
8799 diff = abs(clock1 - clock2);
8800
8801 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8802 return true;
8803
8804 return false;
8805}
8806
25c5b266
DV		 8807#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8808 list_for_each_entry((intel_crtc), \
8809 &(dev)->mode_config.crtc_list, \
8810 base.head) \
0973f18f 8811 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8812
0e8ffe1b 8813static bool
2fa2fe9a
DV		 8814intel_pipe_config_compare(struct drm_device *dev,
8815 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8816 struct intel_crtc_config *pipe_config)
8817{
66e985c0
DV		 8818#define PIPE_CONF_CHECK_X(name) \
8819 if (current_config->name != pipe_config->name) { \
8820 DRM_ERROR("mismatch in " #name " " \
8821 "(expected 0x%08x, found 0x%08x)\n", \
8822 current_config->name, \
8823 pipe_config->name); \
8824 return false; \
8825 }
8826
08a24034
DV		 8827#define PIPE_CONF_CHECK_I(name) \
8828 if (current_config->name != pipe_config->name) { \
8829 DRM_ERROR("mismatch in " #name " " \
8830 "(expected %i, found %i)\n", \
8831 current_config->name, \
8832 pipe_config->name); \
8833 return false; \
88adfff1
DV		 8834 }
8835
1bd1bd80
DV		 8836#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8837 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 8838 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 8839 "(expected %i, found %i)\n", \
8840 current_config->name & (mask), \
8841 pipe_config->name & (mask)); \
8842 return false; \
8843 }
8844
5e550656
VS		 8845#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
8846 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
8847 DRM_ERROR("mismatch in " #name " " \
8848 "(expected %i, found %i)\n", \
8849 current_config->name, \
8850 pipe_config->name); \
8851 return false; \
8852 }
8853
bb760063
DV		 8854#define PIPE_CONF_QUIRK(quirk) \
8855 ((current_config->quirks | pipe_config->quirks) & (quirk))
8856
eccb140b
DV		 8857 PIPE_CONF_CHECK_I(cpu_transcoder);
8858
08a24034
DV		 8859 PIPE_CONF_CHECK_I(has_pch_encoder);
8860 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8861 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8862 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8863 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8864 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8865 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8866
eb14cb74
VS		 8867 PIPE_CONF_CHECK_I(has_dp_encoder);
8868 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
8869 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
8870 PIPE_CONF_CHECK_I(dp_m_n.link_m);
8871 PIPE_CONF_CHECK_I(dp_m_n.link_n);
8872 PIPE_CONF_CHECK_I(dp_m_n.tu);
8873
1bd1bd80
DV		 8874 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8875 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8876 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8877 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8878 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8879 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8880
8881 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8882 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8883 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8884 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8885 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8886 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8887
c93f54cf 8888 PIPE_CONF_CHECK_I(pixel_multiplier);
6c49f241 8889
1bd1bd80
DV		 8890 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8891 DRM_MODE_FLAG_INTERLACE);
8892
bb760063
DV		 8893 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8894 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8895 DRM_MODE_FLAG_PHSYNC);
8896 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8897 DRM_MODE_FLAG_NHSYNC);
8898 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8899 DRM_MODE_FLAG_PVSYNC);
8900 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8901 DRM_MODE_FLAG_NVSYNC);
8902 }
045ac3b5 8903
37327abd
VS		 8904 PIPE_CONF_CHECK_I(pipe_src_w);
8905 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 8906
2fa2fe9a
DV		 8907 PIPE_CONF_CHECK_I(gmch_pfit.control);
8908 /* pfit ratios are autocomputed by the hw on gen4+ */
8909 if (INTEL_INFO(dev)->gen < 4)
8910 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8911 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
fd4daa9c
CW		 8912 PIPE_CONF_CHECK_I(pch_pfit.enabled);
8913 if (current_config->pch_pfit.enabled) {
8914 PIPE_CONF_CHECK_I(pch_pfit.pos);
8915 PIPE_CONF_CHECK_I(pch_pfit.size);
8916 }
2fa2fe9a 8917
42db64ef
PZ		 8918 PIPE_CONF_CHECK_I(ips_enabled);
8919
282740f7
VS		 8920 PIPE_CONF_CHECK_I(double_wide);
8921
c0d43d62 8922 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 8923 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 8924 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 8925 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8926 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
c0d43d62 8927
42571aef
VS		 8928 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
8929 PIPE_CONF_CHECK_I(pipe_bpp);
8930
d71b8d4a 8931 if (!IS_HASWELL(dev)) {
241bfc38 8932 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
d71b8d4a
VS		 8933 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
8934 }
5e550656 8935
66e985c0 8936#undef PIPE_CONF_CHECK_X
08a24034 8937#undef PIPE_CONF_CHECK_I
1bd1bd80 8938#undef PIPE_CONF_CHECK_FLAGS
5e550656 8939#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 8940#undef PIPE_CONF_QUIRK
88adfff1 8941
0e8ffe1b
DV		 8942 return true;
8943}
8944
91d1b4bd
DV		 8945static void
8946check_connector_state(struct drm_device *dev)
8af6cf88 8947{
8af6cf88
DV		 8948 struct intel_connector *connector;
8949
8950 list_for_each_entry(connector, &dev->mode_config.connector_list,
8951 base.head) {
8952 /* This also checks the encoder/connector hw state with the
8953 * ->get_hw_state callbacks. */
8954 intel_connector_check_state(connector);
8955
8956 WARN(&connector->new_encoder->base != connector->base.encoder,
8957 "connector's staged encoder doesn't match current encoder\n");
8958 }
91d1b4bd
DV		 8959}
8960
8961static void
8962check_encoder_state(struct drm_device *dev)
8963{
8964 struct intel_encoder *encoder;
8965 struct intel_connector *connector;
8af6cf88
DV		 8966
8967 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8968 base.head) {
8969 bool enabled = false;
8970 bool active = false;
8971 enum pipe pipe, tracked_pipe;
8972
8973 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8974 encoder->base.base.id,
8975 drm_get_encoder_name(&encoder->base));
8976
8977 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8978 "encoder's stage crtc doesn't match current crtc\n");
8979 WARN(encoder->connectors_active && !encoder->base.crtc,
8980 "encoder's active_connectors set, but no crtc\n");
8981
8982 list_for_each_entry(connector, &dev->mode_config.connector_list,
8983 base.head) {
8984 if (connector->base.encoder != &encoder->base)
8985 continue;
8986 enabled = true;
8987 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8988 active = true;
8989 }
8990 WARN(!!encoder->base.crtc != enabled,
8991 "encoder's enabled state mismatch "
8992 "(expected %i, found %i)\n",
8993 !!encoder->base.crtc, enabled);
8994 WARN(active && !encoder->base.crtc,
8995 "active encoder with no crtc\n");
8996
8997 WARN(encoder->connectors_active != active,
8998 "encoder's computed active state doesn't match tracked active state "
8999 "(expected %i, found %i)\n", active, encoder->connectors_active);
9000
9001 active = encoder->get_hw_state(encoder, &pipe);
9002 WARN(active != encoder->connectors_active,
9003 "encoder's hw state doesn't match sw tracking "
9004 "(expected %i, found %i)\n",
9005 encoder->connectors_active, active);
9006
9007 if (!encoder->base.crtc)
9008 continue;
9009
9010 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9011 WARN(active && pipe != tracked_pipe,
9012 "active encoder's pipe doesn't match"
9013 "(expected %i, found %i)\n",
9014 tracked_pipe, pipe);
9015
9016 }
91d1b4bd
DV		 9017}
9018
9019static void
9020check_crtc_state(struct drm_device *dev)
9021{
9022 drm_i915_private_t *dev_priv = dev->dev_private;
9023 struct intel_crtc *crtc;
9024 struct intel_encoder *encoder;
9025 struct intel_crtc_config pipe_config;
8af6cf88
DV		 9026
9027 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9028 base.head) {
9029 bool enabled = false;
9030 bool active = false;
9031
045ac3b5
JB		 9032 memset(&pipe_config, 0, sizeof(pipe_config));
9033
8af6cf88
DV		 9034 DRM_DEBUG_KMS("[CRTC:%d]\n",
9035 crtc->base.base.id);
9036
9037 WARN(crtc->active && !crtc->base.enabled,
9038 "active crtc, but not enabled in sw tracking\n");
9039
9040 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9041 base.head) {
9042 if (encoder->base.crtc != &crtc->base)
9043 continue;
9044 enabled = true;
9045 if (encoder->connectors_active)
9046 active = true;
9047 }
6c49f241 9048
8af6cf88
DV		 9049 WARN(active != crtc->active,
9050 "crtc's computed active state doesn't match tracked active state "
9051 "(expected %i, found %i)\n", active, crtc->active);
9052 WARN(enabled != crtc->base.enabled,
9053 "crtc's computed enabled state doesn't match tracked enabled state "
9054 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
9055
0e8ffe1b
DV		 9056 active = dev_priv->display.get_pipe_config(crtc,
9057 &pipe_config);
d62cf62a
DV		 9058
9059 /* hw state is inconsistent with the pipe A quirk */
9060 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
9061 active = crtc->active;
9062
6c49f241
DV		 9063 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9064 base.head) {
3eaba51c 9065 enum pipe pipe;
6c49f241
DV		 9066 if (encoder->base.crtc != &crtc->base)
9067 continue;
3eaba51c
VS		 9068 if (encoder->get_config &&
9069 encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 9070 encoder->get_config(encoder, &pipe_config);
9071 }
9072
0e8ffe1b
DV		 9073 WARN(crtc->active != active,
9074 "crtc active state doesn't match with hw state "
9075 "(expected %i, found %i)\n", crtc->active, active);
9076
c0b03411
DV		 9077 if (active &&
9078 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9079 WARN(1, "pipe state doesn't match!\n");
9080 intel_dump_pipe_config(crtc, &pipe_config,
9081 "[hw state]");
9082 intel_dump_pipe_config(crtc, &crtc->config,
9083 "[sw state]");
9084 }
8af6cf88
DV		 9085 }
9086}
9087
91d1b4bd
DV		 9088static void
9089check_shared_dpll_state(struct drm_device *dev)
9090{
9091 drm_i915_private_t *dev_priv = dev->dev_private;
9092 struct intel_crtc *crtc;
9093 struct intel_dpll_hw_state dpll_hw_state;
9094 int i;
5358901f
DV		 9095
9096 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9097 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9098 int enabled_crtcs = 0, active_crtcs = 0;
9099 bool active;
9100
9101 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9102
9103 DRM_DEBUG_KMS("%s\n", pll->name);
9104
9105 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9106
9107 WARN(pll->active > pll->refcount,
9108 "more active pll users than references: %i vs %i\n",
9109 pll->active, pll->refcount);
9110 WARN(pll->active && !pll->on,
9111 "pll in active use but not on in sw tracking\n");
35c95375
DV		 9112 WARN(pll->on && !pll->active,
9113 "pll in on but not on in use in sw tracking\n");
5358901f
DV		 9114 WARN(pll->on != active,
9115 "pll on state mismatch (expected %i, found %i)\n",
9116 pll->on, active);
9117
9118 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9119 base.head) {
9120 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9121 enabled_crtcs++;
9122 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9123 active_crtcs++;
9124 }
9125 WARN(pll->active != active_crtcs,
9126 "pll active crtcs mismatch (expected %i, found %i)\n",
9127 pll->active, active_crtcs);
9128 WARN(pll->refcount != enabled_crtcs,
9129 "pll enabled crtcs mismatch (expected %i, found %i)\n",
9130 pll->refcount, enabled_crtcs);
66e985c0
DV		 9131
9132 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9133 sizeof(dpll_hw_state)),
9134 "pll hw state mismatch\n");
5358901f 9135 }
8af6cf88
DV		 9136}
9137
91d1b4bd
DV		 9138void
9139intel_modeset_check_state(struct drm_device *dev)
9140{
9141 check_connector_state(dev);
9142 check_encoder_state(dev);
9143 check_crtc_state(dev);
9144 check_shared_dpll_state(dev);
9145}
9146
18442d08
VS		 9147void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9148 int dotclock)
9149{
9150 /*
9151 * FDI already provided one idea for the dotclock.
9152 * Yell if the encoder disagrees.
9153 */
241bfc38 9154 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
18442d08 9155 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
241bfc38 9156 pipe_config->adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 9157}
9158
f30da187
DV		 9159static int __intel_set_mode(struct drm_crtc *crtc,
9160 struct drm_display_mode *mode,
9161 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 9162{
9163 struct drm_device *dev = crtc->dev;
dbf2b54e 9164 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 9165 struct drm_display_mode *saved_mode, *saved_hwmode;
9166 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 9167 struct intel_crtc *intel_crtc;
9168 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 9169 int ret = 0;
a6778b3c 9170
a1e22653 9171 saved_mode = kcalloc(2, sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 9172 if (!saved_mode)
9173 return -ENOMEM;
3ac18232 9174 saved_hwmode = saved_mode + 1;
a6778b3c 9175
e2e1ed41 9176 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 9177 &prepare_pipes, &disable_pipes);
9178
3ac18232
TG		 9179 *saved_hwmode = crtc->hwmode;
9180 *saved_mode = crtc->mode;
a6778b3c 9181
25c5b266
DV		 9182 /* Hack: Because we don't (yet) support global modeset on multiple
9183 * crtcs, we don't keep track of the new mode for more than one crtc.
9184 * Hence simply check whether any bit is set in modeset_pipes in all the
9185 * pieces of code that are not yet converted to deal with mutliple crtcs
9186 * changing their mode at the same time. */
25c5b266 9187 if (modeset_pipes) {
4e53c2e0 9188 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 9189 if (IS_ERR(pipe_config)) {
9190 ret = PTR_ERR(pipe_config);
9191 pipe_config = NULL;
9192
3ac18232 9193 goto out;
25c5b266 9194 }
c0b03411
DV		 9195 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9196 "[modeset]");
25c5b266 9197 }
a6778b3c 9198
460da916
DV		 9199 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9200 intel_crtc_disable(&intel_crtc->base);
9201
ea9d758d
DV		 9202 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9203 if (intel_crtc->base.enabled)
9204 dev_priv->display.crtc_disable(&intel_crtc->base);
9205 }
a6778b3c 9206
6c4c86f5
DV		 9207 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9208 * to set it here already despite that we pass it down the callchain.
f6e5b160 9209 */
b8cecdf5 9210 if (modeset_pipes) {
25c5b266 9211 crtc->mode = *mode;
b8cecdf5
DV		 9212 /* mode_set/enable/disable functions rely on a correct pipe
9213 * config. */
9214 to_intel_crtc(crtc)->config = *pipe_config;
9215 }
7758a113 9216
ea9d758d
DV		 9217 /* Only after disabling all output pipelines that will be changed can we
9218 * update the the output configuration. */
9219 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 9220
47fab737
DV		 9221 if (dev_priv->display.modeset_global_resources)
9222 dev_priv->display.modeset_global_resources(dev);
9223
a6778b3c
DV		 9224 /* Set up the DPLL and any encoders state that needs to adjust or depend
9225 * on the DPLL.
f6e5b160 9226 */
25c5b266 9227 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 9228 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 9229 x, y, fb);
9230 if (ret)
9231 goto done;
a6778b3c
DV		 9232 }
9233
9234 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 9235 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9236 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 9237
25c5b266
DV		 9238 if (modeset_pipes) {
9239 /* Store real post-adjustment hardware mode. */
b8cecdf5 9240 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 9241
25c5b266
DV		 9242 /* Calculate and store various constants which
9243 * are later needed by vblank and swap-completion
9244 * timestamping. They are derived from true hwmode.
9245 */
9246 drm_calc_timestamping_constants(crtc);
9247 }
a6778b3c
DV		 9248
9249 /* FIXME: add subpixel order */
9250done:
c0c36b94 9251 if (ret && crtc->enabled) {
3ac18232
TG		 9252 crtc->hwmode = *saved_hwmode;
9253 crtc->mode = *saved_mode;
a6778b3c
DV		 9254 }
9255
3ac18232 9256out:
b8cecdf5 9257 kfree(pipe_config);
3ac18232 9258 kfree(saved_mode);
a6778b3c 9259 return ret;
f6e5b160
CW		 9260}
9261
e7457a9a
DL		 9262static int intel_set_mode(struct drm_crtc *crtc,
9263 struct drm_display_mode *mode,
9264 int x, int y, struct drm_framebuffer *fb)
f30da187
DV		 9265{
9266 int ret;
9267
9268 ret = __intel_set_mode(crtc, mode, x, y, fb);
9269
9270 if (ret == 0)
9271 intel_modeset_check_state(crtc->dev);
9272
9273 return ret;
9274}
9275
c0c36b94
CW		 9276void intel_crtc_restore_mode(struct drm_crtc *crtc)
9277{
9278 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9279}
9280
25c5b266
DV		 9281#undef for_each_intel_crtc_masked
9282
d9e55608
DV		 9283static void intel_set_config_free(struct intel_set_config *config)
9284{
9285 if (!config)
9286 return;
9287
1aa4b628
DV		 9288 kfree(config->save_connector_encoders);
9289 kfree(config->save_encoder_crtcs);
d9e55608
DV		 9290 kfree(config);
9291}
9292
85f9eb71
DV		 9293static int intel_set_config_save_state(struct drm_device *dev,
9294 struct intel_set_config *config)
9295{
85f9eb71
DV		 9296 struct drm_encoder *encoder;
9297 struct drm_connector *connector;
9298 int count;
9299
1aa4b628
DV		 9300 config->save_encoder_crtcs =
9301 kcalloc(dev->mode_config.num_encoder,
9302 sizeof(struct drm_crtc *), GFP_KERNEL);
9303 if (!config->save_encoder_crtcs)
85f9eb71
DV		 9304 return -ENOMEM;
9305
1aa4b628
DV		 9306 config->save_connector_encoders =
9307 kcalloc(dev->mode_config.num_connector,
9308 sizeof(struct drm_encoder *), GFP_KERNEL);
9309 if (!config->save_connector_encoders)
85f9eb71
DV		 9310 return -ENOMEM;
9311
9312 /* Copy data. Note that driver private data is not affected.
9313 * Should anything bad happen only the expected state is
9314 * restored, not the drivers personal bookkeeping.
9315 */
85f9eb71
DV		 9316 count = 0;
9317 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 9318 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 9319 }
9320
9321 count = 0;
9322 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 9323 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 9324 }
9325
9326 return 0;
9327}
9328
9329static void intel_set_config_restore_state(struct drm_device *dev,
9330 struct intel_set_config *config)
9331{
9a935856
DV		 9332 struct intel_encoder *encoder;
9333 struct intel_connector *connector;
85f9eb71
DV		 9334 int count;
9335
85f9eb71 9336 count = 0;
9a935856
DV		 9337 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9338 encoder->new_crtc =
9339 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 9340 }
9341
9342 count = 0;
9a935856
DV		 9343 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9344 connector->new_encoder =
9345 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 9346 }
9347}
9348
e3de42b6 9349static bool
2e57f47d 9350is_crtc_connector_off(struct drm_mode_set *set)
e3de42b6
ID		 9351{
9352 int i;
9353
2e57f47d
CW		 9354 if (set->num_connectors == 0)
9355 return false;
9356
9357 if (WARN_ON(set->connectors == NULL))
9358 return false;
9359
9360 for (i = 0; i < set->num_connectors; i++)
9361 if (set->connectors[i]->encoder &&
9362 set->connectors[i]->encoder->crtc == set->crtc &&
9363 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
e3de42b6
ID		 9364 return true;
9365
9366 return false;
9367}
9368
5e2b584e
DV		 9369static void
9370intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9371 struct intel_set_config *config)
9372{
9373
9374 /* We should be able to check here if the fb has the same properties
9375 * and then just flip_or_move it */
2e57f47d
CW		 9376 if (is_crtc_connector_off(set)) {
9377 config->mode_changed = true;
e3de42b6 9378 } else if (set->crtc->fb != set->fb) {
5e2b584e
DV		 9379 /* If we have no fb then treat it as a full mode set */
9380 if (set->crtc->fb == NULL) {
319d9827
JB		 9381 struct intel_crtc *intel_crtc =
9382 to_intel_crtc(set->crtc);
9383
9384 if (intel_crtc->active && i915_fastboot) {
9385 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9386 config->fb_changed = true;
9387 } else {
9388 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9389 config->mode_changed = true;
9390 }
5e2b584e
DV		 9391 } else if (set->fb == NULL) {
9392 config->mode_changed = true;
72f4901e
DV		 9393 } else if (set->fb->pixel_format !=
9394 set->crtc->fb->pixel_format) {
5e2b584e 9395 config->mode_changed = true;
e3de42b6 9396 } else {
5e2b584e 9397 config->fb_changed = true;
e3de42b6 9398 }
5e2b584e
DV		 9399 }
9400
835c5873 9401 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 9402 config->fb_changed = true;
9403
9404 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9405 DRM_DEBUG_KMS("modes are different, full mode set\n");
9406 drm_mode_debug_printmodeline(&set->crtc->mode);
9407 drm_mode_debug_printmodeline(set->mode);
9408 config->mode_changed = true;
9409 }
a1d95703
CW		 9410
9411 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9412 set->crtc->base.id, config->mode_changed, config->fb_changed);
5e2b584e
DV		 9413}
9414
2e431051 9415static int
9a935856
DV		 9416intel_modeset_stage_output_state(struct drm_device *dev,
9417 struct drm_mode_set *set,
9418 struct intel_set_config *config)
50f56119 9419{
85f9eb71 9420 struct drm_crtc *new_crtc;
9a935856
DV		 9421 struct intel_connector *connector;
9422 struct intel_encoder *encoder;
f3f08572 9423 int ro;
50f56119 9424
9abdda74 9425 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 9426 * of connectors. For paranoia, double-check this. */
9427 WARN_ON(!set->fb && (set->num_connectors != 0));
9428 WARN_ON(set->fb && (set->num_connectors == 0));
9429
9a935856
DV		 9430 list_for_each_entry(connector, &dev->mode_config.connector_list,
9431 base.head) {
9432 /* Otherwise traverse passed in connector list and get encoders
9433 * for them. */
50f56119 9434 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 9435 if (set->connectors[ro] == &connector->base) {
9436 connector->new_encoder = connector->encoder;
50f56119
DV		 9437 break;
9438 }
9439 }
9440
9a935856
DV		 9441 /* If we disable the crtc, disable all its connectors. Also, if
9442 * the connector is on the changing crtc but not on the new
9443 * connector list, disable it. */
9444 if ((!set->fb || ro == set->num_connectors) &&
9445 connector->base.encoder &&
9446 connector->base.encoder->crtc == set->crtc) {
9447 connector->new_encoder = NULL;
9448
9449 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9450 connector->base.base.id,
9451 drm_get_connector_name(&connector->base));
9452 }
9453
9454
9455 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 9456 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 9457 config->mode_changed = true;
50f56119
DV		 9458 }
9459 }
9a935856 9460 /* connector->new_encoder is now updated for all connectors. */
50f56119 9461
9a935856 9462 /* Update crtc of enabled connectors. */
9a935856
DV		 9463 list_for_each_entry(connector, &dev->mode_config.connector_list,
9464 base.head) {
9465 if (!connector->new_encoder)
50f56119
DV		 9466 continue;
9467
9a935856 9468 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 9469
9470 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 9471 if (set->connectors[ro] == &connector->base)
50f56119
DV		 9472 new_crtc = set->crtc;
9473 }
9474
9475 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 9476 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9477 new_crtc)) {
5e2b584e 9478 return -EINVAL;
50f56119 9479 }
9a935856
DV		 9480 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9481
9482 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9483 connector->base.base.id,
9484 drm_get_connector_name(&connector->base),
9485 new_crtc->base.id);
9486 }
9487
9488 /* Check for any encoders that needs to be disabled. */
9489 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9490 base.head) {
9491 list_for_each_entry(connector,
9492 &dev->mode_config.connector_list,
9493 base.head) {
9494 if (connector->new_encoder == encoder) {
9495 WARN_ON(!connector->new_encoder->new_crtc);
9496
9497 goto next_encoder;
9498 }
9499 }
9500 encoder->new_crtc = NULL;
9501next_encoder:
9502 /* Only now check for crtc changes so we don't miss encoders
9503 * that will be disabled. */
9504 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 9505 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 9506 config->mode_changed = true;
50f56119
DV		 9507 }
9508 }
9a935856 9509 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 9510
2e431051
DV		 9511 return 0;
9512}
9513
9514static int intel_crtc_set_config(struct drm_mode_set *set)
9515{
9516 struct drm_device *dev;
2e431051
DV		 9517 struct drm_mode_set save_set;
9518 struct intel_set_config *config;
9519 int ret;
2e431051 9520
8d3e375e
DV		 9521 BUG_ON(!set);
9522 BUG_ON(!set->crtc);
9523 BUG_ON(!set->crtc->helper_private);
2e431051 9524
7e53f3a4
DV		 9525 /* Enforce sane interface api - has been abused by the fb helper. */
9526 BUG_ON(!set->mode && set->fb);
9527 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 9528
2e431051
DV		 9529 if (set->fb) {
9530 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9531 set->crtc->base.id, set->fb->base.id,
9532 (int)set->num_connectors, set->x, set->y);
9533 } else {
9534 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 9535 }
9536
9537 dev = set->crtc->dev;
9538
9539 ret = -ENOMEM;
9540 config = kzalloc(sizeof(*config), GFP_KERNEL);
9541 if (!config)
9542 goto out_config;
9543
9544 ret = intel_set_config_save_state(dev, config);
9545 if (ret)
9546 goto out_config;
9547
9548 save_set.crtc = set->crtc;
9549 save_set.mode = &set->crtc->mode;
9550 save_set.x = set->crtc->x;
9551 save_set.y = set->crtc->y;
9552 save_set.fb = set->crtc->fb;
9553
9554 /* Compute whether we need a full modeset, only an fb base update or no
9555 * change at all. In the future we might also check whether only the
9556 * mode changed, e.g. for LVDS where we only change the panel fitter in
9557 * such cases. */
9558 intel_set_config_compute_mode_changes(set, config);
9559
9a935856 9560 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 9561 if (ret)
9562 goto fail;
9563
5e2b584e 9564 if (config->mode_changed) {
c0c36b94
CW		 9565 ret = intel_set_mode(set->crtc, set->mode,
9566 set->x, set->y, set->fb);
5e2b584e 9567 } else if (config->fb_changed) {
4878cae2
VS		 9568 intel_crtc_wait_for_pending_flips(set->crtc);
9569
4f660f49 9570 ret = intel_pipe_set_base(set->crtc,
94352cf9 9571 set->x, set->y, set->fb);
50f56119
DV		 9572 }
9573
2d05eae1 9574 if (ret) {
bf67dfeb
DV		 9575 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9576 set->crtc->base.id, ret);
50f56119 9577fail:
2d05eae1 9578 intel_set_config_restore_state(dev, config);
50f56119 9579
2d05eae1
CW		 9580 /* Try to restore the config */
9581 if (config->mode_changed &&
9582 intel_set_mode(save_set.crtc, save_set.mode,
9583 save_set.x, save_set.y, save_set.fb))
9584 DRM_ERROR("failed to restore config after modeset failure\n");
9585 }
50f56119 9586
d9e55608
DV		 9587out_config:
9588 intel_set_config_free(config);
50f56119
DV		 9589 return ret;
9590}
f6e5b160
CW		 9591
9592static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 9593 .cursor_set = intel_crtc_cursor_set,
9594 .cursor_move = intel_crtc_cursor_move,
9595 .gamma_set = intel_crtc_gamma_set,
50f56119 9596 .set_config = intel_crtc_set_config,
f6e5b160
CW		 9597 .destroy = intel_crtc_destroy,
9598 .page_flip = intel_crtc_page_flip,
9599};
9600
79f689aa
PZ		 9601static void intel_cpu_pll_init(struct drm_device *dev)
9602{
affa9354 9603 if (HAS_DDI(dev))
79f689aa
PZ		 9604 intel_ddi_pll_init(dev);
9605}
9606
5358901f
DV		 9607static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9608 struct intel_shared_dpll *pll,
9609 struct intel_dpll_hw_state *hw_state)
ee7b9f93 9610{
5358901f 9611 uint32_t val;
ee7b9f93 9612
5358901f 9613 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 9614 hw_state->dpll = val;
9615 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9616 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 9617
9618 return val & DPLL_VCO_ENABLE;
9619}
9620
15bdd4cf
DV		 9621static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9622 struct intel_shared_dpll *pll)
9623{
9624 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9625 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9626}
9627
e7b903d2
DV		 9628static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9629 struct intel_shared_dpll *pll)
9630{
e7b903d2
DV		 9631 /* PCH refclock must be enabled first */
9632 assert_pch_refclk_enabled(dev_priv);
9633
15bdd4cf
DV		 9634 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9635
9636 /* Wait for the clocks to stabilize. */
9637 POSTING_READ(PCH_DPLL(pll->id));
9638 udelay(150);
9639
9640 /* The pixel multiplier can only be updated once the
9641 * DPLL is enabled and the clocks are stable.
9642 *
9643 * So write it again.
9644 */
9645 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9646 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9647 udelay(200);
9648}
9649
9650static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9651 struct intel_shared_dpll *pll)
9652{
9653 struct drm_device *dev = dev_priv->dev;
9654 struct intel_crtc *crtc;
e7b903d2
DV		 9655
9656 /* Make sure no transcoder isn't still depending on us. */
9657 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9658 if (intel_crtc_to_shared_dpll(crtc) == pll)
9659 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 9660 }
9661
15bdd4cf
DV		 9662 I915_WRITE(PCH_DPLL(pll->id), 0);
9663 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9664 udelay(200);
9665}
9666
46edb027
DV		 9667static char *ibx_pch_dpll_names[] = {
9668 "PCH DPLL A",
9669 "PCH DPLL B",
9670};
9671
7c74ade1 9672static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 9673{
e7b903d2 9674 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 9675 int i;
9676
7c74ade1 9677 dev_priv->num_shared_dpll = 2;
ee7b9f93 9678
e72f9fbf 9679 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 9680 dev_priv->shared_dplls[i].id = i;
9681 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 9682 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 9683 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9684 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 9685 dev_priv->shared_dplls[i].get_hw_state =
9686 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 9687 }
9688}
9689
7c74ade1
DV		 9690static void intel_shared_dpll_init(struct drm_device *dev)
9691{
e7b903d2 9692 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1
DV		 9693
9694 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9695 ibx_pch_dpll_init(dev);
9696 else
9697 dev_priv->num_shared_dpll = 0;
9698
9699 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9700 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9701 dev_priv->num_shared_dpll);
9702}
9703
b358d0a6 9704static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 9705{
22fd0fab 9706 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 9707 struct intel_crtc *intel_crtc;
9708 int i;
9709
955382f3 9710 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 9711 if (intel_crtc == NULL)
9712 return;
9713
9714 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9715
9716 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 9717 for (i = 0; i < 256; i++) {
9718 intel_crtc->lut_r[i] = i;
9719 intel_crtc->lut_g[i] = i;
9720 intel_crtc->lut_b[i] = i;
9721 }
9722
80824003
JB		 9723 /* Swap pipes & planes for FBC on pre-965 */
9724 intel_crtc->pipe = pipe;
9725 intel_crtc->plane = pipe;
e2e767ab 9726 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 9727 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 9728 intel_crtc->plane = !pipe;
80824003
JB		 9729 }
9730
22fd0fab
JB		 9731 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9732 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9733 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9734 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9735
79e53945 9736 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 9737}
9738
08d7b3d1 9739int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 9740 struct drm_file *file)
08d7b3d1 9741{
08d7b3d1 9742 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 9743 struct drm_mode_object *drmmode_obj;
9744 struct intel_crtc *crtc;
08d7b3d1 9745
1cff8f6b
DV		 9746 if (!drm_core_check_feature(dev, DRIVER_MODESET))
9747 return -ENODEV;
08d7b3d1 9748
c05422d5
DV		 9749 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9750 DRM_MODE_OBJECT_CRTC);
08d7b3d1 9751
c05422d5 9752 if (!drmmode_obj) {
08d7b3d1
CW		 9753 DRM_ERROR("no such CRTC id\n");
9754 return -EINVAL;
9755 }
9756
c05422d5
DV		 9757 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9758 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 9759
c05422d5 9760 return 0;
08d7b3d1
CW		 9761}
9762
66a9278e 9763static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 9764{
66a9278e
DV		 9765 struct drm_device *dev = encoder->base.dev;
9766 struct intel_encoder *source_encoder;
79e53945 9767 int index_mask = 0;
79e53945
JB		 9768 int entry = 0;
9769
66a9278e
DV		 9770 list_for_each_entry(source_encoder,
9771 &dev->mode_config.encoder_list, base.head) {
9772
9773 if (encoder == source_encoder)
79e53945 9774 index_mask |= (1 << entry);
66a9278e
DV		 9775
9776 /* Intel hw has only one MUX where enocoders could be cloned. */
9777 if (encoder->cloneable && source_encoder->cloneable)
9778 index_mask |= (1 << entry);
9779
79e53945
JB		 9780 entry++;
9781 }
4ef69c7a 9782
79e53945
JB		 9783 return index_mask;
9784}
9785
4d302442
CW		 9786static bool has_edp_a(struct drm_device *dev)
9787{
9788 struct drm_i915_private *dev_priv = dev->dev_private;
9789
9790 if (!IS_MOBILE(dev))
9791 return false;
9792
9793 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9794 return false;
9795
9796 if (IS_GEN5(dev) &&
9797 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9798 return false;
9799
9800 return true;
9801}
9802
79e53945
JB		 9803static void intel_setup_outputs(struct drm_device *dev)
9804{
725e30ad 9805 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 9806 struct intel_encoder *encoder;
cb0953d7 9807 bool dpd_is_edp = false;
79e53945 9808
c9093354 9809 intel_lvds_init(dev);
79e53945 9810
c40c0f5b 9811 if (!IS_ULT(dev))
79935fca 9812 intel_crt_init(dev);
cb0953d7 9813
affa9354 9814 if (HAS_DDI(dev)) {
0e72a5b5
ED		 9815 int found;
9816
9817 /* Haswell uses DDI functions to detect digital outputs */
9818 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9819 /* DDI A only supports eDP */
9820 if (found)
9821 intel_ddi_init(dev, PORT_A);
9822
9823 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9824 * register */
9825 found = I915_READ(SFUSE_STRAP);
9826
9827 if (found & SFUSE_STRAP_DDIB_DETECTED)
9828 intel_ddi_init(dev, PORT_B);
9829 if (found & SFUSE_STRAP_DDIC_DETECTED)
9830 intel_ddi_init(dev, PORT_C);
9831 if (found & SFUSE_STRAP_DDID_DETECTED)
9832 intel_ddi_init(dev, PORT_D);
9833 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 9834 int found;
270b3042
DV		 9835 dpd_is_edp = intel_dpd_is_edp(dev);
9836
9837 if (has_edp_a(dev))
9838 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 9839
dc0fa718 9840 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 9841 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 9842 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 9843 if (!found)
e2debe91 9844 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 9845 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 9846 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 9847 }
9848
dc0fa718 9849 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 9850 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 9851
dc0fa718 9852 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 9853 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 9854
5eb08b69 9855 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 9856 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 9857
270b3042 9858 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 9859 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 9860 } else if (IS_VALLEYVIEW(dev)) {
19c03924 9861 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
6f6005a5
JB		 9862 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
9863 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
9864 PORT_C);
9865 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9866 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
9867 PORT_C);
9868 }
19c03924 9869
dc0fa718 9870 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 9871 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9872 PORT_B);
67cfc203
VS		 9873 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9874 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 9875 }
3cfca973
JN		 9876
9877 intel_dsi_init(dev);
103a196f 9878 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 9879 bool found = false;
7d57382e 9880
e2debe91 9881 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9882 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 9883 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 9884 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9885 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 9886 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 9887 }
27185ae1 9888
e7281eab 9889 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9890 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 9891 }
13520b05
KH		 9892
9893 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 9894
e2debe91 9895 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9896 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 9897 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 9898 }
27185ae1 9899
e2debe91 9900 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 9901
b01f2c3a
JB		 9902 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9903 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 9904 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 9905 }
e7281eab 9906 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9907 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 9908 }
27185ae1 9909
b01f2c3a 9910 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 9911 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 9912 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 9913 } else if (IS_GEN2(dev))
79e53945
JB		 9914 intel_dvo_init(dev);
9915
103a196f 9916 if (SUPPORTS_TV(dev))
79e53945
JB		 9917 intel_tv_init(dev);
9918
4ef69c7a
CW		 9919 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9920 encoder->base.possible_crtcs = encoder->crtc_mask;
9921 encoder->base.possible_clones =
66a9278e 9922 intel_encoder_clones(encoder);
79e53945 9923 }
47356eb6 9924
dde86e2d 9925 intel_init_pch_refclk(dev);
270b3042
DV		 9926
9927 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 9928}
9929
ddfe1567
CW		 9930void intel_framebuffer_fini(struct intel_framebuffer *fb)
9931{
9932 drm_framebuffer_cleanup(&fb->base);
9933 drm_gem_object_unreference_unlocked(&fb->obj->base);
9934}
9935
79e53945
JB		 9936static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9937{
9938 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 9939
ddfe1567 9940 intel_framebuffer_fini(intel_fb);
79e53945
JB		 9941 kfree(intel_fb);
9942}
9943
9944static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 9945 struct drm_file *file,
79e53945
JB		 9946 unsigned int *handle)
9947{
9948 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 9949 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 9950
05394f39 9951 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 9952}
9953
9954static const struct drm_framebuffer_funcs intel_fb_funcs = {
9955 .destroy = intel_user_framebuffer_destroy,
9956 .create_handle = intel_user_framebuffer_create_handle,
9957};
9958
38651674
DA		 9959int intel_framebuffer_init(struct drm_device *dev,
9960 struct intel_framebuffer *intel_fb,
308e5bcb 9961 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 9962 struct drm_i915_gem_object *obj)
79e53945 9963{
a35cdaa0 9964 int pitch_limit;
79e53945
JB		 9965 int ret;
9966
c16ed4be
CW		 9967 if (obj->tiling_mode == I915_TILING_Y) {
9968 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 9969 return -EINVAL;
c16ed4be 9970 }
57cd6508 9971
c16ed4be
CW		 9972 if (mode_cmd->pitches[0] & 63) {
9973 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9974 mode_cmd->pitches[0]);
57cd6508 9975 return -EINVAL;
c16ed4be 9976 }
57cd6508 9977
a35cdaa0
CW		 9978 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9979 pitch_limit = 32*1024;
9980 } else if (INTEL_INFO(dev)->gen >= 4) {
9981 if (obj->tiling_mode)
9982 pitch_limit = 16*1024;
9983 else
9984 pitch_limit = 32*1024;
9985 } else if (INTEL_INFO(dev)->gen >= 3) {
9986 if (obj->tiling_mode)
9987 pitch_limit = 8*1024;
9988 else
9989 pitch_limit = 16*1024;
9990 } else
9991 /* XXX DSPC is limited to 4k tiled */
9992 pitch_limit = 8*1024;
9993
9994 if (mode_cmd->pitches[0] > pitch_limit) {
9995 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9996 obj->tiling_mode ? "tiled" : "linear",
9997 mode_cmd->pitches[0], pitch_limit);
5d7bd705 9998 return -EINVAL;
c16ed4be 9999 }
5d7bd705
VS		 10000
10001 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 10002 mode_cmd->pitches[0] != obj->stride) {
10003 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10004 mode_cmd->pitches[0], obj->stride);
5d7bd705 10005 return -EINVAL;
c16ed4be 10006 }
5d7bd705 10007
57779d06 10008 /* Reject formats not supported by any plane early. */
308e5bcb 10009 switch (mode_cmd->pixel_format) {
57779d06 10010 case DRM_FORMAT_C8:
04b3924d
VS		 10011 case DRM_FORMAT_RGB565:
10012 case DRM_FORMAT_XRGB8888:
10013 case DRM_FORMAT_ARGB8888:
57779d06
VS		 10014 break;
10015 case DRM_FORMAT_XRGB1555:
10016 case DRM_FORMAT_ARGB1555:
c16ed4be 10017 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 10018 DRM_DEBUG("unsupported pixel format: %s\n",
10019 drm_get_format_name(mode_cmd->pixel_format));
57779d06 10020 return -EINVAL;
c16ed4be 10021 }
57779d06
VS		 10022 break;
10023 case DRM_FORMAT_XBGR8888:
10024 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 10025 case DRM_FORMAT_XRGB2101010:
10026 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 10027 case DRM_FORMAT_XBGR2101010:
10028 case DRM_FORMAT_ABGR2101010:
c16ed4be 10029 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 10030 DRM_DEBUG("unsupported pixel format: %s\n",
10031 drm_get_format_name(mode_cmd->pixel_format));
57779d06 10032 return -EINVAL;
c16ed4be 10033 }
b5626747 10034 break;
04b3924d
VS		 10035 case DRM_FORMAT_YUYV:
10036 case DRM_FORMAT_UYVY:
10037 case DRM_FORMAT_YVYU:
10038 case DRM_FORMAT_VYUY:
c16ed4be 10039 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 10040 DRM_DEBUG("unsupported pixel format: %s\n",
10041 drm_get_format_name(mode_cmd->pixel_format));
57779d06 10042 return -EINVAL;
c16ed4be 10043 }
57cd6508
CW		 10044 break;
10045 default:
4ee62c76
VS		 10046 DRM_DEBUG("unsupported pixel format: %s\n",
10047 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 10048 return -EINVAL;
10049 }
10050
90f9a336
VS		 10051 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10052 if (mode_cmd->offsets[0] != 0)
10053 return -EINVAL;
10054
c7d73f6a
DV		 10055 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
10056 intel_fb->obj = obj;
10057
79e53945
JB		 10058 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
10059 if (ret) {
10060 DRM_ERROR("framebuffer init failed %d\n", ret);
10061 return ret;
10062 }
10063
79e53945
JB		 10064 return 0;
10065}
10066
79e53945
JB		 10067static struct drm_framebuffer *
10068intel_user_framebuffer_create(struct drm_device *dev,
10069 struct drm_file *filp,
308e5bcb 10070 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 10071{
05394f39 10072 struct drm_i915_gem_object *obj;
79e53945 10073
308e5bcb
JB		 10074 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
10075 mode_cmd->handles[0]));
c8725226 10076 if (&obj->base == NULL)
cce13ff7 10077 return ERR_PTR(-ENOENT);
79e53945 10078
d2dff872 10079 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 10080}
10081
79e53945 10082static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 10083 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 10084 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 10085};
10086
e70236a8
JB		 10087/* Set up chip specific display functions */
10088static void intel_init_display(struct drm_device *dev)
10089{
10090 struct drm_i915_private *dev_priv = dev->dev_private;
10091
ee9300bb
DV		 10092 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
10093 dev_priv->display.find_dpll = g4x_find_best_dpll;
10094 else if (IS_VALLEYVIEW(dev))
10095 dev_priv->display.find_dpll = vlv_find_best_dpll;
10096 else if (IS_PINEVIEW(dev))
10097 dev_priv->display.find_dpll = pnv_find_best_dpll;
10098 else
10099 dev_priv->display.find_dpll = i9xx_find_best_dpll;
10100
affa9354 10101 if (HAS_DDI(dev)) {
0e8ffe1b 10102 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 10103 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 10104 dev_priv->display.crtc_enable = haswell_crtc_enable;
10105 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 10106 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 10107 dev_priv->display.update_plane = ironlake_update_plane;
10108 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 10109 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 10110 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 10111 dev_priv->display.crtc_enable = ironlake_crtc_enable;
10112 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 10113 dev_priv->display.off = ironlake_crtc_off;
17638cd6 10114 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 10115 } else if (IS_VALLEYVIEW(dev)) {
10116 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10117 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10118 dev_priv->display.crtc_enable = valleyview_crtc_enable;
10119 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10120 dev_priv->display.off = i9xx_crtc_off;
10121 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 10122 } else {
0e8ffe1b 10123 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 10124 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 10125 dev_priv->display.crtc_enable = i9xx_crtc_enable;
10126 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 10127 dev_priv->display.off = i9xx_crtc_off;
17638cd6 10128 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 10129 }
e70236a8 10130
e70236a8 10131 /* Returns the core display clock speed */
25eb05fc
JB		 10132 if (IS_VALLEYVIEW(dev))
10133 dev_priv->display.get_display_clock_speed =
10134 valleyview_get_display_clock_speed;
10135 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 10136 dev_priv->display.get_display_clock_speed =
10137 i945_get_display_clock_speed;
10138 else if (IS_I915G(dev))
10139 dev_priv->display.get_display_clock_speed =
10140 i915_get_display_clock_speed;
257a7ffc 10141 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 10142 dev_priv->display.get_display_clock_speed =
10143 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 10144 else if (IS_PINEVIEW(dev))
10145 dev_priv->display.get_display_clock_speed =
10146 pnv_get_display_clock_speed;
e70236a8
JB		 10147 else if (IS_I915GM(dev))
10148 dev_priv->display.get_display_clock_speed =
10149 i915gm_get_display_clock_speed;
10150 else if (IS_I865G(dev))
10151 dev_priv->display.get_display_clock_speed =
10152 i865_get_display_clock_speed;
f0f8a9ce 10153 else if (IS_I85X(dev))
e70236a8
JB		 10154 dev_priv->display.get_display_clock_speed =
10155 i855_get_display_clock_speed;
10156 else /* 852, 830 */
10157 dev_priv->display.get_display_clock_speed =
10158 i830_get_display_clock_speed;
10159
7f8a8569 10160 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 10161 if (IS_GEN5(dev)) {
674cf967 10162 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 10163 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 10164 } else if (IS_GEN6(dev)) {
674cf967 10165 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 10166 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 10167 } else if (IS_IVYBRIDGE(dev)) {
10168 /* FIXME: detect B0+ stepping and use auto training */
10169 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 10170 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 10171 dev_priv->display.modeset_global_resources =
10172 ivb_modeset_global_resources;
c82e4d26
ED		 10173 } else if (IS_HASWELL(dev)) {
10174 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 10175 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 10176 dev_priv->display.modeset_global_resources =
10177 haswell_modeset_global_resources;
a0e63c22 10178 }
6067aaea 10179 } else if (IS_G4X(dev)) {
e0dac65e 10180 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 10181 }
8c9f3aaf
JB		 10182
10183 /* Default just returns -ENODEV to indicate unsupported */
10184 dev_priv->display.queue_flip = intel_default_queue_flip;
10185
10186 switch (INTEL_INFO(dev)->gen) {
10187 case 2:
10188 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10189 break;
10190
10191 case 3:
10192 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10193 break;
10194
10195 case 4:
10196 case 5:
10197 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10198 break;
10199
10200 case 6:
10201 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10202 break;
7c9017e5
JB		 10203 case 7:
10204 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10205 break;
8c9f3aaf 10206 }
e70236a8
JB		 10207}
10208
b690e96c
JB		 10209/*
10210 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10211 * resume, or other times. This quirk makes sure that's the case for
10212 * affected systems.
10213 */
0206e353 10214static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 10215{
10216 struct drm_i915_private *dev_priv = dev->dev_private;
10217
10218 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 10219 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 10220}
10221
435793df
KP		 10222/*
10223 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10224 */
10225static void quirk_ssc_force_disable(struct drm_device *dev)
10226{
10227 struct drm_i915_private *dev_priv = dev->dev_private;
10228 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 10229 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 10230}
10231
4dca20ef 10232/*
5a15ab5b
CE		 10233 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10234 * brightness value
4dca20ef
CE		 10235 */
10236static void quirk_invert_brightness(struct drm_device *dev)
10237{
10238 struct drm_i915_private *dev_priv = dev->dev_private;
10239 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 10240 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 10241}
10242
e85843be
KM		 10243/*
10244 * Some machines (Dell XPS13) suffer broken backlight controls if
10245 * BLM_PCH_PWM_ENABLE is set.
10246 */
10247static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
10248{
10249 struct drm_i915_private *dev_priv = dev->dev_private;
10250 dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
10251 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
10252}
10253
b690e96c
JB		 10254struct intel_quirk {
10255 int device;
10256 int subsystem_vendor;
10257 int subsystem_device;
10258 void (*hook)(struct drm_device *dev);
10259};
10260
5f85f176
EE		 10261/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10262struct intel_dmi_quirk {
10263 void (*hook)(struct drm_device *dev);
10264 const struct dmi_system_id (*dmi_id_list)[];
10265};
10266
10267static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10268{
10269 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10270 return 1;
10271}
10272
10273static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10274 {
10275 .dmi_id_list = &(const struct dmi_system_id[]) {
10276 {
10277 .callback = intel_dmi_reverse_brightness,
10278 .ident = "NCR Corporation",
10279 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10280 DMI_MATCH(DMI_PRODUCT_NAME, ""),
10281 },
10282 },
10283 { } /* terminating entry */
10284 },
10285 .hook = quirk_invert_brightness,
10286 },
10287};
10288
c43b5634 10289static struct intel_quirk intel_quirks[] = {
b690e96c 10290 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 10291 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 10292
b690e96c
JB		 10293 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10294 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10295
b690e96c
JB		 10296 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10297 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10298
ccd0d36e 10299 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 10300 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 10301 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 10302
10303 /* Lenovo U160 cannot use SSC on LVDS */
10304 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 10305
10306 /* Sony Vaio Y cannot use SSC on LVDS */
10307 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 10308
ee1452d7
JN		 10309 /*
10310 * All GM45 Acer (and its brands eMachines and Packard Bell) laptops
10311 * seem to use inverted backlight PWM.
10312 */
10313 { 0x2a42, 0x1025, PCI_ANY_ID, quirk_invert_brightness },
e85843be
KM		 10314
10315 /* Dell XPS13 HD Sandy Bridge */
10316 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10317 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10318 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
b690e96c
JB		 10319};
10320
10321static void intel_init_quirks(struct drm_device *dev)
10322{
10323 struct pci_dev *d = dev->pdev;
10324 int i;
10325
10326 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10327 struct intel_quirk *q = &intel_quirks[i];
10328
10329 if (d->device == q->device &&
10330 (d->subsystem_vendor == q->subsystem_vendor ||
10331 q->subsystem_vendor == PCI_ANY_ID) &&
10332 (d->subsystem_device == q->subsystem_device ||
10333 q->subsystem_device == PCI_ANY_ID))
10334 q->hook(dev);
10335 }
5f85f176
EE		 10336 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10337 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10338 intel_dmi_quirks[i].hook(dev);
10339 }
b690e96c
JB		 10340}
10341
9cce37f4
JB		 10342/* Disable the VGA plane that we never use */
10343static void i915_disable_vga(struct drm_device *dev)
10344{
10345 struct drm_i915_private *dev_priv = dev->dev_private;
10346 u8 sr1;
766aa1c4 10347 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 10348
10349 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 10350 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 10351 sr1 = inb(VGA_SR_DATA);
10352 outb(sr1 | 1<<5, VGA_SR_DATA);
10353 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10354 udelay(300);
10355
10356 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10357 POSTING_READ(vga_reg);
10358}
10359
6e1b4fda 10360static void i915_enable_vga_mem(struct drm_device *dev)
81b5c7bc
AW		 10361{
10362 /* Enable VGA memory on Intel HD */
10363 if (HAS_PCH_SPLIT(dev)) {
10364 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10365 outb(inb(VGA_MSR_READ) | VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10366 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10367 VGA_RSRC_LEGACY_MEM |
10368 VGA_RSRC_NORMAL_IO |
10369 VGA_RSRC_NORMAL_MEM);
10370 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10371 }
10372}
10373
6e1b4fda
VS		 10374void i915_disable_vga_mem(struct drm_device *dev)
10375{
10376 /* Disable VGA memory on Intel HD */
10377 if (HAS_PCH_SPLIT(dev)) {
10378 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10379 outb(inb(VGA_MSR_READ) & ~VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10380 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10381 VGA_RSRC_NORMAL_IO |
10382 VGA_RSRC_NORMAL_MEM);
10383 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10384 }
10385}
10386
f817586c
DV		 10387void intel_modeset_init_hw(struct drm_device *dev)
10388{
f6071166
JB		 10389 struct drm_i915_private *dev_priv = dev->dev_private;
10390
a8f78b58
ED		 10391 intel_prepare_ddi(dev);
10392
f817586c
DV		 10393 intel_init_clock_gating(dev);
10394
f6071166
JB		 10395 /* Enable the CRI clock source so we can get at the display */
10396 if (IS_VALLEYVIEW(dev))
10397 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
10398 DPLL_INTEGRATED_CRI_CLK_VLV);
10399
40e9cf64
JB		 10400 intel_init_dpio(dev);
10401
79f5b2c7 10402 mutex_lock(&dev->struct_mutex);
8090c6b9 10403 intel_enable_gt_powersave(dev);
79f5b2c7 10404 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 10405}
10406
7d708ee4
ID		 10407void intel_modeset_suspend_hw(struct drm_device *dev)
10408{
10409 intel_suspend_hw(dev);
10410}
10411
79e53945
JB		 10412void intel_modeset_init(struct drm_device *dev)
10413{
652c393a 10414 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 10415 int i, j, ret;
79e53945
JB		 10416
10417 drm_mode_config_init(dev);
10418
10419 dev->mode_config.min_width = 0;
10420 dev->mode_config.min_height = 0;
10421
019d96cb
DA		 10422 dev->mode_config.preferred_depth = 24;
10423 dev->mode_config.prefer_shadow = 1;
10424
e6ecefaa 10425 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 10426
b690e96c
JB		 10427 intel_init_quirks(dev);
10428
1fa61106
ED		 10429 intel_init_pm(dev);
10430
e3c74757
BW		 10431 if (INTEL_INFO(dev)->num_pipes == 0)
10432 return;
10433
e70236a8
JB		 10434 intel_init_display(dev);
10435
a6c45cf0
CW		 10436 if (IS_GEN2(dev)) {
10437 dev->mode_config.max_width = 2048;
10438 dev->mode_config.max_height = 2048;
10439 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 10440 dev->mode_config.max_width = 4096;
10441 dev->mode_config.max_height = 4096;
79e53945 10442 } else {
a6c45cf0
CW		 10443 dev->mode_config.max_width = 8192;
10444 dev->mode_config.max_height = 8192;
79e53945 10445 }
5d4545ae 10446 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 10447
28c97730 10448 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 10449 INTEL_INFO(dev)->num_pipes,
10450 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 10451
08e2a7de 10452 for_each_pipe(i) {
79e53945 10453 intel_crtc_init(dev, i);
7f1f3851
JB		 10454 for (j = 0; j < dev_priv->num_plane; j++) {
10455 ret = intel_plane_init(dev, i, j);
10456 if (ret)
06da8da2
VS		 10457 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10458 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 10459 }
79e53945
JB		 10460 }
10461
79f689aa 10462 intel_cpu_pll_init(dev);
e72f9fbf 10463 intel_shared_dpll_init(dev);
ee7b9f93 10464
9cce37f4
JB		 10465 /* Just disable it once at startup */
10466 i915_disable_vga(dev);
79e53945 10467 intel_setup_outputs(dev);
11be49eb
CW		 10468
10469 /* Just in case the BIOS is doing something questionable. */
10470 intel_disable_fbc(dev);
2c7111db
CW		 10471}
10472
24929352
DV		 10473static void
10474intel_connector_break_all_links(struct intel_connector *connector)
10475{
10476 connector->base.dpms = DRM_MODE_DPMS_OFF;
10477 connector->base.encoder = NULL;
10478 connector->encoder->connectors_active = false;
10479 connector->encoder->base.crtc = NULL;
10480}
10481
7fad798e
DV		 10482static void intel_enable_pipe_a(struct drm_device *dev)
10483{
10484 struct intel_connector *connector;
10485 struct drm_connector *crt = NULL;
10486 struct intel_load_detect_pipe load_detect_temp;
10487
10488 /* We can't just switch on the pipe A, we need to set things up with a
10489 * proper mode and output configuration. As a gross hack, enable pipe A
10490 * by enabling the load detect pipe once. */
10491 list_for_each_entry(connector,
10492 &dev->mode_config.connector_list,
10493 base.head) {
10494 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10495 crt = &connector->base;
10496 break;
10497 }
10498 }
10499
10500 if (!crt)
10501 return;
10502
10503 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10504 intel_release_load_detect_pipe(crt, &load_detect_temp);
10505
652c393a 10506
7fad798e
DV		 10507}
10508
fa555837
DV		 10509static bool
10510intel_check_plane_mapping(struct intel_crtc *crtc)
10511{
7eb552ae
BW		 10512 struct drm_device *dev = crtc->base.dev;
10513 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 10514 u32 reg, val;
10515
7eb552ae 10516 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 10517 return true;
10518
10519 reg = DSPCNTR(!crtc->plane);
10520 val = I915_READ(reg);
10521
10522 if ((val & DISPLAY_PLANE_ENABLE) &&
10523 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10524 return false;
10525
10526 return true;
10527}
10528
24929352
DV		 10529static void intel_sanitize_crtc(struct intel_crtc *crtc)
10530{
10531 struct drm_device *dev = crtc->base.dev;
10532 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 10533 u32 reg;
24929352 10534
24929352 10535 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 10536 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 10537 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10538
10539 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 10540 * disable the crtc (and hence change the state) if it is wrong. Note
10541 * that gen4+ has a fixed plane -> pipe mapping. */
10542 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 10543 struct intel_connector *connector;
10544 bool plane;
10545
24929352
DV		 10546 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10547 crtc->base.base.id);
10548
10549 /* Pipe has the wrong plane attached and the plane is active.
10550 * Temporarily change the plane mapping and disable everything
10551 * ... */
10552 plane = crtc->plane;
10553 crtc->plane = !plane;
10554 dev_priv->display.crtc_disable(&crtc->base);
10555 crtc->plane = plane;
10556
10557 /* ... and break all links. */
10558 list_for_each_entry(connector, &dev->mode_config.connector_list,
10559 base.head) {
10560 if (connector->encoder->base.crtc != &crtc->base)
10561 continue;
10562
10563 intel_connector_break_all_links(connector);
10564 }
10565
10566 WARN_ON(crtc->active);
10567 crtc->base.enabled = false;
10568 }
24929352 10569
7fad798e
DV		 10570 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10571 crtc->pipe == PIPE_A && !crtc->active) {
10572 /* BIOS forgot to enable pipe A, this mostly happens after
10573 * resume. Force-enable the pipe to fix this, the update_dpms
10574 * call below we restore the pipe to the right state, but leave
10575 * the required bits on. */
10576 intel_enable_pipe_a(dev);
10577 }
10578
24929352
DV		 10579 /* Adjust the state of the output pipe according to whether we
10580 * have active connectors/encoders. */
10581 intel_crtc_update_dpms(&crtc->base);
10582
10583 if (crtc->active != crtc->base.enabled) {
10584 struct intel_encoder *encoder;
10585
10586 /* This can happen either due to bugs in the get_hw_state
10587 * functions or because the pipe is force-enabled due to the
10588 * pipe A quirk. */
10589 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10590 crtc->base.base.id,
10591 crtc->base.enabled ? "enabled" : "disabled",
10592 crtc->active ? "enabled" : "disabled");
10593
10594 crtc->base.enabled = crtc->active;
10595
10596 /* Because we only establish the connector -> encoder ->
10597 * crtc links if something is active, this means the
10598 * crtc is now deactivated. Break the links. connector
10599 * -> encoder links are only establish when things are
10600 * actually up, hence no need to break them. */
10601 WARN_ON(crtc->active);
10602
10603 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10604 WARN_ON(encoder->connectors_active);
10605 encoder->base.crtc = NULL;
10606 }
10607 }
10608}
10609
10610static void intel_sanitize_encoder(struct intel_encoder *encoder)
10611{
10612 struct intel_connector *connector;
10613 struct drm_device *dev = encoder->base.dev;
10614
10615 /* We need to check both for a crtc link (meaning that the
10616 * encoder is active and trying to read from a pipe) and the
10617 * pipe itself being active. */
10618 bool has_active_crtc = encoder->base.crtc &&
10619 to_intel_crtc(encoder->base.crtc)->active;
10620
10621 if (encoder->connectors_active && !has_active_crtc) {
10622 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10623 encoder->base.base.id,
10624 drm_get_encoder_name(&encoder->base));
10625
10626 /* Connector is active, but has no active pipe. This is
10627 * fallout from our resume register restoring. Disable
10628 * the encoder manually again. */
10629 if (encoder->base.crtc) {
10630 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10631 encoder->base.base.id,
10632 drm_get_encoder_name(&encoder->base));
10633 encoder->disable(encoder);
10634 }
10635
10636 /* Inconsistent output/port/pipe state happens presumably due to
10637 * a bug in one of the get_hw_state functions. Or someplace else
10638 * in our code, like the register restore mess on resume. Clamp
10639 * things to off as a safer default. */
10640 list_for_each_entry(connector,
10641 &dev->mode_config.connector_list,
10642 base.head) {
10643 if (connector->encoder != encoder)
10644 continue;
10645
10646 intel_connector_break_all_links(connector);
10647 }
10648 }
10649 /* Enabled encoders without active connectors will be fixed in
10650 * the crtc fixup. */
10651}
10652
44cec740 10653void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 10654{
10655 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 10656 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 10657
8dc8a27c
PZ		 10658 /* This function can be called both from intel_modeset_setup_hw_state or
10659 * at a very early point in our resume sequence, where the power well
10660 * structures are not yet restored. Since this function is at a very
10661 * paranoid "someone might have enabled VGA while we were not looking"
10662 * level, just check if the power well is enabled instead of trying to
10663 * follow the "don't touch the power well if we don't need it" policy
10664 * the rest of the driver uses. */
10665 if (HAS_POWER_WELL(dev) &&
6aedd1f5 10666 (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
8dc8a27c
PZ		 10667 return;
10668
0fde901f
KM		 10669 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
10670 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 10671 i915_disable_vga(dev);
6e1b4fda 10672 i915_disable_vga_mem(dev);
0fde901f
KM		 10673 }
10674}
10675
30e984df 10676static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 10677{
10678 struct drm_i915_private *dev_priv = dev->dev_private;
10679 enum pipe pipe;
24929352
DV		 10680 struct intel_crtc *crtc;
10681 struct intel_encoder *encoder;
10682 struct intel_connector *connector;
5358901f 10683 int i;
24929352 10684
0e8ffe1b
DV		 10685 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10686 base.head) {
88adfff1 10687 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 10688
0e8ffe1b
DV		 10689 crtc->active = dev_priv->display.get_pipe_config(crtc,
10690 &crtc->config);
24929352
DV		 10691
10692 crtc->base.enabled = crtc->active;
10693
10694 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10695 crtc->base.base.id,
10696 crtc->active ? "enabled" : "disabled");
10697 }
10698
5358901f 10699 /* FIXME: Smash this into the new shared dpll infrastructure. */
affa9354 10700 if (HAS_DDI(dev))
6441ab5f
PZ		 10701 intel_ddi_setup_hw_pll_state(dev);
10702
5358901f
DV		 10703 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10704 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10705
10706 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10707 pll->active = 0;
10708 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10709 base.head) {
10710 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10711 pll->active++;
10712 }
10713 pll->refcount = pll->active;
10714
35c95375
DV		 10715 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10716 pll->name, pll->refcount, pll->on);
5358901f
DV		 10717 }
10718
24929352
DV		 10719 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10720 base.head) {
10721 pipe = 0;
10722
10723 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 10724 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10725 encoder->base.crtc = &crtc->base;
510d5f2f 10726 if (encoder->get_config)
045ac3b5 10727 encoder->get_config(encoder, &crtc->config);
24929352
DV		 10728 } else {
10729 encoder->base.crtc = NULL;
10730 }
10731
10732 encoder->connectors_active = false;
10733 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10734 encoder->base.base.id,
10735 drm_get_encoder_name(&encoder->base),
10736 encoder->base.crtc ? "enabled" : "disabled",
10737 pipe);
10738 }
10739
10740 list_for_each_entry(connector, &dev->mode_config.connector_list,
10741 base.head) {
10742 if (connector->get_hw_state(connector)) {
10743 connector->base.dpms = DRM_MODE_DPMS_ON;
10744 connector->encoder->connectors_active = true;
10745 connector->base.encoder = &connector->encoder->base;
10746 } else {
10747 connector->base.dpms = DRM_MODE_DPMS_OFF;
10748 connector->base.encoder = NULL;
10749 }
10750 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10751 connector->base.base.id,
10752 drm_get_connector_name(&connector->base),
10753 connector->base.encoder ? "enabled" : "disabled");
10754 }
30e984df
DV		 10755}
10756
10757/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10758 * and i915 state tracking structures. */
10759void intel_modeset_setup_hw_state(struct drm_device *dev,
10760 bool force_restore)
10761{
10762 struct drm_i915_private *dev_priv = dev->dev_private;
10763 enum pipe pipe;
30e984df
DV		 10764 struct intel_crtc *crtc;
10765 struct intel_encoder *encoder;
35c95375 10766 int i;
30e984df
DV		 10767
10768 intel_modeset_readout_hw_state(dev);
24929352 10769
babea61d
JB		 10770 /*
10771 * Now that we have the config, copy it to each CRTC struct
10772 * Note that this could go away if we move to using crtc_config
10773 * checking everywhere.
10774 */
10775 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10776 base.head) {
10777 if (crtc->active && i915_fastboot) {
10778 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10779
10780 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10781 crtc->base.base.id);
10782 drm_mode_debug_printmodeline(&crtc->base.mode);
10783 }
10784 }
10785
24929352
DV		 10786 /* HW state is read out, now we need to sanitize this mess. */
10787 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10788 base.head) {
10789 intel_sanitize_encoder(encoder);
10790 }
10791
10792 for_each_pipe(pipe) {
10793 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10794 intel_sanitize_crtc(crtc);
c0b03411 10795 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 10796 }
9a935856 10797
35c95375
DV		 10798 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10799 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10800
10801 if (!pll->on || pll->active)
10802 continue;
10803
10804 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10805
10806 pll->disable(dev_priv, pll);
10807 pll->on = false;
10808 }
10809
45e2b5f6 10810 if (force_restore) {
7d0bc1ea
VS		 10811 i915_redisable_vga(dev);
10812
f30da187
DV		 10813 /*
10814 * We need to use raw interfaces for restoring state to avoid
10815 * checking (bogus) intermediate states.
10816 */
45e2b5f6 10817 for_each_pipe(pipe) {
b5644d05
JB		 10818 struct drm_crtc *crtc =
10819 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 10820
10821 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10822 crtc->fb);
45e2b5f6
DV		 10823 }
10824 } else {
10825 intel_modeset_update_staged_output_state(dev);
10826 }
8af6cf88
DV		 10827
10828 intel_modeset_check_state(dev);
2e938892
DV		 10829
10830 drm_mode_config_reset(dev);
2c7111db
CW		 10831}
10832
10833void intel_modeset_gem_init(struct drm_device *dev)
10834{
1833b134 10835 intel_modeset_init_hw(dev);
02e792fb
DV		 10836
10837 intel_setup_overlay(dev);
24929352 10838
45e2b5f6 10839 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 10840}
10841
10842void intel_modeset_cleanup(struct drm_device *dev)
10843{
652c393a
JB		 10844 struct drm_i915_private *dev_priv = dev->dev_private;
10845 struct drm_crtc *crtc;
d9255d57 10846 struct drm_connector *connector;
652c393a 10847
fd0c0642
DV		 10848 /*
10849 * Interrupts and polling as the first thing to avoid creating havoc.
10850 * Too much stuff here (turning of rps, connectors, ...) would
10851 * experience fancy races otherwise.
10852 */
10853 drm_irq_uninstall(dev);
10854 cancel_work_sync(&dev_priv->hotplug_work);
10855 /*
10856 * Due to the hpd irq storm handling the hotplug work can re-arm the
10857 * poll handlers. Hence disable polling after hpd handling is shut down.
10858 */
f87ea761 10859 drm_kms_helper_poll_fini(dev);
fd0c0642 10860
652c393a
JB		 10861 mutex_lock(&dev->struct_mutex);
10862
723bfd70
JB		 10863 intel_unregister_dsm_handler();
10864
652c393a
JB		 10865 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10866 /* Skip inactive CRTCs */
10867 if (!crtc->fb)
10868 continue;
10869
3dec0095 10870 intel_increase_pllclock(crtc);
652c393a
JB		 10871 }
10872
973d04f9 10873 intel_disable_fbc(dev);
e70236a8 10874
6e1b4fda 10875 i915_enable_vga_mem(dev);
81b5c7bc 10876
8090c6b9 10877 intel_disable_gt_powersave(dev);
0cdab21f 10878
930ebb46
DV		 10879 ironlake_teardown_rc6(dev);
10880
69341a5e
KH		 10881 mutex_unlock(&dev->struct_mutex);
10882
1630fe75
CW		 10883 /* flush any delayed tasks or pending work */
10884 flush_scheduled_work();
10885
dc652f90
JN		 10886 /* destroy backlight, if any, before the connectors */
10887 intel_panel_destroy_backlight(dev);
10888
d9255d57
PZ		 10889 /* destroy the sysfs files before encoders/connectors */
10890 list_for_each_entry(connector, &dev->mode_config.connector_list, head)
10891 drm_sysfs_connector_remove(connector);
10892
79e53945 10893 drm_mode_config_cleanup(dev);
4d7bb011
DV		 10894
10895 intel_cleanup_overlay(dev);
79e53945
JB		 10896}
10897
f1c79df3
ZW		 10898/*
10899 * Return which encoder is currently attached for connector.
10900 */
df0e9248 10901struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 10902{
df0e9248
CW		 10903 return &intel_attached_encoder(connector)->base;
10904}
f1c79df3 10905
df0e9248
CW		 10906void intel_connector_attach_encoder(struct intel_connector *connector,
10907 struct intel_encoder *encoder)
10908{
10909 connector->encoder = encoder;
10910 drm_mode_connector_attach_encoder(&connector->base,
10911 &encoder->base);
79e53945 10912}
28d52043
DA		 10913
10914/*
10915 * set vga decode state - true == enable VGA decode
10916 */
10917int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10918{
10919 struct drm_i915_private *dev_priv = dev->dev_private;
10920 u16 gmch_ctrl;
10921
10922 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10923 if (state)
10924 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10925 else
10926 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10927 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10928 return 0;
10929}
c4a1d9e4 10930
c4a1d9e4 10931struct intel_display_error_state {
ff57f1b0
PZ		 10932
10933 u32 power_well_driver;
10934
63b66e5b
CW		 10935 int num_transcoders;
10936
c4a1d9e4
CW		 10937 struct intel_cursor_error_state {
10938 u32 control;
10939 u32 position;
10940 u32 base;
10941 u32 size;
52331309 10942 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 10943
10944 struct intel_pipe_error_state {
c4a1d9e4 10945 u32 source;
52331309 10946 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 10947
10948 struct intel_plane_error_state {
10949 u32 control;
10950 u32 stride;
10951 u32 size;
10952 u32 pos;
10953 u32 addr;
10954 u32 surface;
10955 u32 tile_offset;
52331309 10956 } plane[I915_MAX_PIPES];
63b66e5b
CW		 10957
10958 struct intel_transcoder_error_state {
10959 enum transcoder cpu_transcoder;
10960
10961 u32 conf;
10962
10963 u32 htotal;
10964 u32 hblank;
10965 u32 hsync;
10966 u32 vtotal;
10967 u32 vblank;
10968 u32 vsync;
10969 } transcoder[4];
c4a1d9e4
CW		 10970};
10971
10972struct intel_display_error_state *
10973intel_display_capture_error_state(struct drm_device *dev)
10974{
0206e353 10975 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 10976 struct intel_display_error_state *error;
63b66e5b
CW		 10977 int transcoders[] = {
10978 TRANSCODER_A,
10979 TRANSCODER_B,
10980 TRANSCODER_C,
10981 TRANSCODER_EDP,
10982 };
c4a1d9e4
CW		 10983 int i;
10984
63b66e5b
CW		 10985 if (INTEL_INFO(dev)->num_pipes == 0)
10986 return NULL;
10987
c4a1d9e4
CW		 10988 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10989 if (error == NULL)
10990 return NULL;
10991
ff57f1b0
PZ		 10992 if (HAS_POWER_WELL(dev))
10993 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10994
52331309 10995 for_each_pipe(i) {
a18c4c3d
PZ		 10996 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10997 error->cursor[i].control = I915_READ(CURCNTR(i));
10998 error->cursor[i].position = I915_READ(CURPOS(i));
10999 error->cursor[i].base = I915_READ(CURBASE(i));
11000 } else {
11001 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
11002 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
11003 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
11004 }
c4a1d9e4
CW		 11005
11006 error->plane[i].control = I915_READ(DSPCNTR(i));
11007 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 11008 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 11009 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 11010 error->plane[i].pos = I915_READ(DSPPOS(i));
11011 }
ca291363
PZ		 11012 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11013 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 11014 if (INTEL_INFO(dev)->gen >= 4) {
11015 error->plane[i].surface = I915_READ(DSPSURF(i));
11016 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
11017 }
11018
c4a1d9e4 11019 error->pipe[i].source = I915_READ(PIPESRC(i));
63b66e5b
CW		 11020 }
11021
11022 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
11023 if (HAS_DDI(dev_priv->dev))
11024 error->num_transcoders++; /* Account for eDP. */
11025
11026 for (i = 0; i < error->num_transcoders; i++) {
11027 enum transcoder cpu_transcoder = transcoders[i];
11028
11029 error->transcoder[i].cpu_transcoder = cpu_transcoder;
11030
11031 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
11032 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
11033 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
11034 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
11035 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
11036 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
11037 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 11038 }
11039
12d217c7
PZ		 11040 /* In the code above we read the registers without checking if the power
11041 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
11042 * prevent the next I915_WRITE from detecting it and printing an error
11043 * message. */
907b28c5 11044 intel_uncore_clear_errors(dev);
12d217c7 11045
c4a1d9e4
CW		 11046 return error;
11047}
11048
edc3d884
MK		 11049#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
11050
c4a1d9e4 11051void
edc3d884 11052intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 11053 struct drm_device *dev,
11054 struct intel_display_error_state *error)
11055{
11056 int i;
11057
63b66e5b
CW		 11058 if (!error)
11059 return;
11060
edc3d884 11061 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 11062 if (HAS_POWER_WELL(dev))
edc3d884 11063 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 11064 error->power_well_driver);
52331309 11065 for_each_pipe(i) {
edc3d884 11066 err_printf(m, "Pipe [%d]:\n", i);
edc3d884 11067 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
edc3d884
MK		 11068
11069 err_printf(m, "Plane [%d]:\n", i);
11070 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
11071 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 11072 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 11073 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
11074 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 11075 }
4b71a570 11076 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 11077 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 11078 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 11079 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
11080 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 11081 }
11082
edc3d884
MK		 11083 err_printf(m, "Cursor [%d]:\n", i);
11084 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
11085 err_printf(m, " POS: %08x\n", error->cursor[i].position);
11086 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 11087 }
63b66e5b
CW		 11088
11089 for (i = 0; i < error->num_transcoders; i++) {
11090 err_printf(m, " CPU transcoder: %c\n",
11091 transcoder_name(error->transcoder[i].cpu_transcoder));
11092 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
11093 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
11094 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
11095 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
11096 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
11097 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
11098 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
11099 }
c4a1d9e4 11100}
ubuntu-bionic-kernel mirror