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drm/i915: Always calculate 8xx WM values based on a 32-bpp framebuffer
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 47
48typedef struct {
0206e353
AJ		 49 /* given values */
50 int n;
51 int m1, m2;
52 int p1, p2;
53 /* derived values */
54 int dot;
55 int vco;
56 int m;
57 int p;
79e53945
JB		 58} intel_clock_t;
59
60typedef struct {
0206e353 61 int min, max;
79e53945
JB		 62} intel_range_t;
63
64typedef struct {
0206e353
AJ		 65 int dot_limit;
66 int p2_slow, p2_fast;
79e53945
JB		 67} intel_p2_t;
68
69#define INTEL_P2_NUM 2
d4906093
ML		 70typedef struct intel_limit intel_limit_t;
71struct intel_limit {
0206e353
AJ		 72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
73 intel_p2_t p2;
74 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 75 int, int, intel_clock_t *, intel_clock_t *);
d4906093 76};
79e53945 77
2377b741
JB		 78/* FDI */
79#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
80
d2acd215
DV		 81int
82intel_pch_rawclk(struct drm_device *dev)
83{
84 struct drm_i915_private *dev_priv = dev->dev_private;
85
86 WARN_ON(!HAS_PCH_SPLIT(dev));
87
88 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
89}
90
d4906093
ML		 91static bool
92intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 93 int target, int refclk, intel_clock_t *match_clock,
94 intel_clock_t *best_clock);
d4906093
ML		 95static bool
96intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 97 int target, int refclk, intel_clock_t *match_clock,
98 intel_clock_t *best_clock);
79e53945 99
a4fc5ed6
KP		 100static bool
101intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 102 int target, int refclk, intel_clock_t *match_clock,
103 intel_clock_t *best_clock);
5eb08b69 104static bool
f2b115e6 105intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 106 int target, int refclk, intel_clock_t *match_clock,
107 intel_clock_t *best_clock);
a4fc5ed6 108
a0c4da24
JB		 109static bool
110intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
111 int target, int refclk, intel_clock_t *match_clock,
112 intel_clock_t *best_clock);
113
021357ac
CW		 114static inline u32 /* units of 100MHz */
115intel_fdi_link_freq(struct drm_device *dev)
116{
8b99e68c
CW		 117 if (IS_GEN5(dev)) {
118 struct drm_i915_private *dev_priv = dev->dev_private;
119 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
120 } else
121 return 27;
021357ac
CW		 122}
123
e4b36699 124static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 125 .dot = { .min = 25000, .max = 350000 },
126 .vco = { .min = 930000, .max = 1400000 },
127 .n = { .min = 3, .max = 16 },
128 .m = { .min = 96, .max = 140 },
129 .m1 = { .min = 18, .max = 26 },
130 .m2 = { .min = 6, .max = 16 },
131 .p = { .min = 4, .max = 128 },
132 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 133 .p2 = { .dot_limit = 165000,
134 .p2_slow = 4, .p2_fast = 2 },
d4906093 135 .find_pll = intel_find_best_PLL,
e4b36699
KP		 136};
137
138static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 139 .dot = { .min = 25000, .max = 350000 },
140 .vco = { .min = 930000, .max = 1400000 },
141 .n = { .min = 3, .max = 16 },
142 .m = { .min = 96, .max = 140 },
143 .m1 = { .min = 18, .max = 26 },
144 .m2 = { .min = 6, .max = 16 },
145 .p = { .min = 4, .max = 128 },
146 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 147 .p2 = { .dot_limit = 165000,
148 .p2_slow = 14, .p2_fast = 7 },
d4906093 149 .find_pll = intel_find_best_PLL,
e4b36699 150};
273e27ca 151
e4b36699 152static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 153 .dot = { .min = 20000, .max = 400000 },
154 .vco = { .min = 1400000, .max = 2800000 },
155 .n = { .min = 1, .max = 6 },
156 .m = { .min = 70, .max = 120 },
157 .m1 = { .min = 10, .max = 22 },
158 .m2 = { .min = 5, .max = 9 },
159 .p = { .min = 5, .max = 80 },
160 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 161 .p2 = { .dot_limit = 200000,
162 .p2_slow = 10, .p2_fast = 5 },
d4906093 163 .find_pll = intel_find_best_PLL,
e4b36699
KP		 164};
165
166static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 167 .dot = { .min = 20000, .max = 400000 },
168 .vco = { .min = 1400000, .max = 2800000 },
169 .n = { .min = 1, .max = 6 },
170 .m = { .min = 70, .max = 120 },
171 .m1 = { .min = 10, .max = 22 },
172 .m2 = { .min = 5, .max = 9 },
173 .p = { .min = 7, .max = 98 },
174 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 175 .p2 = { .dot_limit = 112000,
176 .p2_slow = 14, .p2_fast = 7 },
d4906093 177 .find_pll = intel_find_best_PLL,
e4b36699
KP		 178};
179
273e27ca 180
e4b36699 181static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 182 .dot = { .min = 25000, .max = 270000 },
183 .vco = { .min = 1750000, .max = 3500000},
184 .n = { .min = 1, .max = 4 },
185 .m = { .min = 104, .max = 138 },
186 .m1 = { .min = 17, .max = 23 },
187 .m2 = { .min = 5, .max = 11 },
188 .p = { .min = 10, .max = 30 },
189 .p1 = { .min = 1, .max = 3},
190 .p2 = { .dot_limit = 270000,
191 .p2_slow = 10,
192 .p2_fast = 10
044c7c41 193 },
d4906093 194 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 195};
196
197static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 198 .dot = { .min = 22000, .max = 400000 },
199 .vco = { .min = 1750000, .max = 3500000},
200 .n = { .min = 1, .max = 4 },
201 .m = { .min = 104, .max = 138 },
202 .m1 = { .min = 16, .max = 23 },
203 .m2 = { .min = 5, .max = 11 },
204 .p = { .min = 5, .max = 80 },
205 .p1 = { .min = 1, .max = 8},
206 .p2 = { .dot_limit = 165000,
207 .p2_slow = 10, .p2_fast = 5 },
d4906093 208 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 209};
210
211static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 212 .dot = { .min = 20000, .max = 115000 },
213 .vco = { .min = 1750000, .max = 3500000 },
214 .n = { .min = 1, .max = 3 },
215 .m = { .min = 104, .max = 138 },
216 .m1 = { .min = 17, .max = 23 },
217 .m2 = { .min = 5, .max = 11 },
218 .p = { .min = 28, .max = 112 },
219 .p1 = { .min = 2, .max = 8 },
220 .p2 = { .dot_limit = 0,
221 .p2_slow = 14, .p2_fast = 14
044c7c41 222 },
d4906093 223 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 224};
225
226static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 227 .dot = { .min = 80000, .max = 224000 },
228 .vco = { .min = 1750000, .max = 3500000 },
229 .n = { .min = 1, .max = 3 },
230 .m = { .min = 104, .max = 138 },
231 .m1 = { .min = 17, .max = 23 },
232 .m2 = { .min = 5, .max = 11 },
233 .p = { .min = 14, .max = 42 },
234 .p1 = { .min = 2, .max = 6 },
235 .p2 = { .dot_limit = 0,
236 .p2_slow = 7, .p2_fast = 7
044c7c41 237 },
d4906093 238 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 239};
240
241static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 242 .dot = { .min = 161670, .max = 227000 },
243 .vco = { .min = 1750000, .max = 3500000},
244 .n = { .min = 1, .max = 2 },
245 .m = { .min = 97, .max = 108 },
246 .m1 = { .min = 0x10, .max = 0x12 },
247 .m2 = { .min = 0x05, .max = 0x06 },
248 .p = { .min = 10, .max = 20 },
249 .p1 = { .min = 1, .max = 2},
250 .p2 = { .dot_limit = 0,
273e27ca 251 .p2_slow = 10, .p2_fast = 10 },
0206e353 252 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 253};
254
f2b115e6 255static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 256 .dot = { .min = 20000, .max = 400000},
257 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 258 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 259 .n = { .min = 3, .max = 6 },
260 .m = { .min = 2, .max = 256 },
273e27ca 261 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 262 .m1 = { .min = 0, .max = 0 },
263 .m2 = { .min = 0, .max = 254 },
264 .p = { .min = 5, .max = 80 },
265 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 266 .p2 = { .dot_limit = 200000,
267 .p2_slow = 10, .p2_fast = 5 },
6115707b 268 .find_pll = intel_find_best_PLL,
e4b36699
KP		 269};
270
f2b115e6 271static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 272 .dot = { .min = 20000, .max = 400000 },
273 .vco = { .min = 1700000, .max = 3500000 },
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 .m1 = { .min = 0, .max = 0 },
277 .m2 = { .min = 0, .max = 254 },
278 .p = { .min = 7, .max = 112 },
279 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 280 .p2 = { .dot_limit = 112000,
281 .p2_slow = 14, .p2_fast = 14 },
6115707b 282 .find_pll = intel_find_best_PLL,
e4b36699
KP		 283};
284
273e27ca
EA		 285/* Ironlake / Sandybridge
286 *
287 * We calculate clock using (register_value + 2) for N/M1/M2, so here
288 * the range value for them is (actual_value - 2).
289 */
b91ad0ec 290static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 291 .dot = { .min = 25000, .max = 350000 },
292 .vco = { .min = 1760000, .max = 3510000 },
293 .n = { .min = 1, .max = 5 },
294 .m = { .min = 79, .max = 127 },
295 .m1 = { .min = 12, .max = 22 },
296 .m2 = { .min = 5, .max = 9 },
297 .p = { .min = 5, .max = 80 },
298 .p1 = { .min = 1, .max = 8 },
299 .p2 = { .dot_limit = 225000,
300 .p2_slow = 10, .p2_fast = 5 },
4547668a 301 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 302};
303
b91ad0ec 304static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 305 .dot = { .min = 25000, .max = 350000 },
306 .vco = { .min = 1760000, .max = 3510000 },
307 .n = { .min = 1, .max = 3 },
308 .m = { .min = 79, .max = 118 },
309 .m1 = { .min = 12, .max = 22 },
310 .m2 = { .min = 5, .max = 9 },
311 .p = { .min = 28, .max = 112 },
312 .p1 = { .min = 2, .max = 8 },
313 .p2 = { .dot_limit = 225000,
314 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 315 .find_pll = intel_g4x_find_best_PLL,
316};
317
318static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 319 .dot = { .min = 25000, .max = 350000 },
320 .vco = { .min = 1760000, .max = 3510000 },
321 .n = { .min = 1, .max = 3 },
322 .m = { .min = 79, .max = 127 },
323 .m1 = { .min = 12, .max = 22 },
324 .m2 = { .min = 5, .max = 9 },
325 .p = { .min = 14, .max = 56 },
326 .p1 = { .min = 2, .max = 8 },
327 .p2 = { .dot_limit = 225000,
328 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 329 .find_pll = intel_g4x_find_best_PLL,
330};
331
273e27ca 332/* LVDS 100mhz refclk limits. */
b91ad0ec 333static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 334 .dot = { .min = 25000, .max = 350000 },
335 .vco = { .min = 1760000, .max = 3510000 },
336 .n = { .min = 1, .max = 2 },
337 .m = { .min = 79, .max = 126 },
338 .m1 = { .min = 12, .max = 22 },
339 .m2 = { .min = 5, .max = 9 },
340 .p = { .min = 28, .max = 112 },
0206e353 341 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 342 .p2 = { .dot_limit = 225000,
343 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 344 .find_pll = intel_g4x_find_best_PLL,
345};
346
347static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 348 .dot = { .min = 25000, .max = 350000 },
349 .vco = { .min = 1760000, .max = 3510000 },
350 .n = { .min = 1, .max = 3 },
351 .m = { .min = 79, .max = 126 },
352 .m1 = { .min = 12, .max = 22 },
353 .m2 = { .min = 5, .max = 9 },
354 .p = { .min = 14, .max = 42 },
0206e353 355 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 356 .p2 = { .dot_limit = 225000,
357 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 358 .find_pll = intel_g4x_find_best_PLL,
359};
360
361static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 362 .dot = { .min = 25000, .max = 350000 },
363 .vco = { .min = 1760000, .max = 3510000},
364 .n = { .min = 1, .max = 2 },
365 .m = { .min = 81, .max = 90 },
366 .m1 = { .min = 12, .max = 22 },
367 .m2 = { .min = 5, .max = 9 },
368 .p = { .min = 10, .max = 20 },
369 .p1 = { .min = 1, .max = 2},
370 .p2 = { .dot_limit = 0,
273e27ca 371 .p2_slow = 10, .p2_fast = 10 },
0206e353 372 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 373};
374
a0c4da24
JB		 375static const intel_limit_t intel_limits_vlv_dac = {
376 .dot = { .min = 25000, .max = 270000 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m = { .min = 22, .max = 450 }, /* guess */
380 .m1 = { .min = 2, .max = 3 },
381 .m2 = { .min = 11, .max = 156 },
382 .p = { .min = 10, .max = 30 },
383 .p1 = { .min = 2, .max = 3 },
384 .p2 = { .dot_limit = 270000,
385 .p2_slow = 2, .p2_fast = 20 },
386 .find_pll = intel_vlv_find_best_pll,
387};
388
389static const intel_limit_t intel_limits_vlv_hdmi = {
390 .dot = { .min = 20000, .max = 165000 },
17dc9257 391 .vco = { .min = 4000000, .max = 5994000},
a0c4da24
JB		 392 .n = { .min = 1, .max = 7 },
393 .m = { .min = 60, .max = 300 }, /* guess */
394 .m1 = { .min = 2, .max = 3 },
395 .m2 = { .min = 11, .max = 156 },
396 .p = { .min = 10, .max = 30 },
397 .p1 = { .min = 2, .max = 3 },
398 .p2 = { .dot_limit = 270000,
399 .p2_slow = 2, .p2_fast = 20 },
400 .find_pll = intel_vlv_find_best_pll,
401};
402
403static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 404 .dot = { .min = 25000, .max = 270000 },
405 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 406 .n = { .min = 1, .max = 7 },
74a4dd2e 407 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 408 .m1 = { .min = 2, .max = 3 },
409 .m2 = { .min = 11, .max = 156 },
410 .p = { .min = 10, .max = 30 },
411 .p1 = { .min = 2, .max = 3 },
412 .p2 = { .dot_limit = 270000,
413 .p2_slow = 2, .p2_fast = 20 },
414 .find_pll = intel_vlv_find_best_pll,
415};
416
57f350b6
JB		 417u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
418{
419 unsigned long flags;
420 u32 val = 0;
421
422 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
423 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
424 DRM_ERROR("DPIO idle wait timed out\n");
425 goto out_unlock;
426 }
427
428 I915_WRITE(DPIO_REG, reg);
429 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
430 DPIO_BYTE);
431 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
432 DRM_ERROR("DPIO read wait timed out\n");
433 goto out_unlock;
434 }
435 val = I915_READ(DPIO_DATA);
436
437out_unlock:
438 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
439 return val;
440}
441
a0c4da24
JB		 442static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
443 u32 val)
444{
445 unsigned long flags;
446
447 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
448 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
449 DRM_ERROR("DPIO idle wait timed out\n");
450 goto out_unlock;
451 }
452
453 I915_WRITE(DPIO_DATA, val);
454 I915_WRITE(DPIO_REG, reg);
455 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
456 DPIO_BYTE);
457 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
458 DRM_ERROR("DPIO write wait timed out\n");
459
460out_unlock:
461 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
462}
463
57f350b6
JB		 464static void vlv_init_dpio(struct drm_device *dev)
465{
466 struct drm_i915_private *dev_priv = dev->dev_private;
467
468 /* Reset the DPIO config */
469 I915_WRITE(DPIO_CTL, 0);
470 POSTING_READ(DPIO_CTL);
471 I915_WRITE(DPIO_CTL, 1);
472 POSTING_READ(DPIO_CTL);
473}
474
618563e3
DV		 475static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
476{
477 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
478 return 1;
479}
480
481static const struct dmi_system_id intel_dual_link_lvds[] = {
482 {
483 .callback = intel_dual_link_lvds_callback,
484 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
485 .matches = {
486 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
487 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
488 },
489 },
490 { } /* terminating entry */
491};
492
b0354385
TI		 493static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
494 unsigned int reg)
495{
496 unsigned int val;
497
121d527a
TI		 498 /* use the module option value if specified */
499 if (i915_lvds_channel_mode > 0)
500 return i915_lvds_channel_mode == 2;
501
618563e3
DV		 502 if (dmi_check_system(intel_dual_link_lvds))
503 return true;
504
b0354385
TI		 505 if (dev_priv->lvds_val)
506 val = dev_priv->lvds_val;
507 else {
508 /* BIOS should set the proper LVDS register value at boot, but
509 * in reality, it doesn't set the value when the lid is closed;
510 * we need to check "the value to be set" in VBT when LVDS
511 * register is uninitialized.
512 */
513 val = I915_READ(reg);
14d94a3d 514 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
b0354385
TI		 515 val = dev_priv->bios_lvds_val;
516 dev_priv->lvds_val = val;
517 }
518 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
519}
520
1b894b59
CW		 521static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
522 int refclk)
2c07245f 523{
b91ad0ec
ZW		 524 struct drm_device *dev = crtc->dev;
525 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 526 const intel_limit_t *limit;
b91ad0ec
ZW		 527
528 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 529 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
b91ad0ec 530 /* LVDS dual channel */
1b894b59 531 if (refclk == 100000)
b91ad0ec
ZW		 532 limit = &intel_limits_ironlake_dual_lvds_100m;
533 else
534 limit = &intel_limits_ironlake_dual_lvds;
535 } else {
1b894b59 536 if (refclk == 100000)
b91ad0ec
ZW		 537 limit = &intel_limits_ironlake_single_lvds_100m;
538 else
539 limit = &intel_limits_ironlake_single_lvds;
540 }
541 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
547dc041 542 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
4547668a 543 limit = &intel_limits_ironlake_display_port;
2c07245f 544 else
b91ad0ec 545 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 546
547 return limit;
548}
549
044c7c41
ML		 550static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
551{
552 struct drm_device *dev = crtc->dev;
553 struct drm_i915_private *dev_priv = dev->dev_private;
554 const intel_limit_t *limit;
555
556 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 557 if (is_dual_link_lvds(dev_priv, LVDS))
044c7c41 558 /* LVDS with dual channel */
e4b36699 559 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 560 else
561 /* LVDS with dual channel */
e4b36699 562 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 563 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
564 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 565 limit = &intel_limits_g4x_hdmi;
044c7c41 566 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 567 limit = &intel_limits_g4x_sdvo;
0206e353 568 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 569 limit = &intel_limits_g4x_display_port;
044c7c41 570 } else /* The option is for other outputs */
e4b36699 571 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 572
573 return limit;
574}
575
1b894b59 576static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 577{
578 struct drm_device *dev = crtc->dev;
579 const intel_limit_t *limit;
580
bad720ff 581 if (HAS_PCH_SPLIT(dev))
1b894b59 582 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 583 else if (IS_G4X(dev)) {
044c7c41 584 limit = intel_g4x_limit(crtc);
f2b115e6 585 } else if (IS_PINEVIEW(dev)) {
2177832f 586 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 587 limit = &intel_limits_pineview_lvds;
2177832f 588 else
f2b115e6 589 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 590 } else if (IS_VALLEYVIEW(dev)) {
591 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
592 limit = &intel_limits_vlv_dac;
593 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
594 limit = &intel_limits_vlv_hdmi;
595 else
596 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 597 } else if (!IS_GEN2(dev)) {
598 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
599 limit = &intel_limits_i9xx_lvds;
600 else
601 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 602 } else {
603 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 604 limit = &intel_limits_i8xx_lvds;
79e53945 605 else
e4b36699 606 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 607 }
608 return limit;
609}
610
f2b115e6
AJ		 611/* m1 is reserved as 0 in Pineview, n is a ring counter */
612static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 613{
2177832f
SL		 614 clock->m = clock->m2 + 2;
615 clock->p = clock->p1 * clock->p2;
616 clock->vco = refclk * clock->m / clock->n;
617 clock->dot = clock->vco / clock->p;
618}
619
620static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
621{
f2b115e6
AJ		 622 if (IS_PINEVIEW(dev)) {
623 pineview_clock(refclk, clock);
2177832f
SL		 624 return;
625 }
79e53945
JB		 626 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
627 clock->p = clock->p1 * clock->p2;
628 clock->vco = refclk * clock->m / (clock->n + 2);
629 clock->dot = clock->vco / clock->p;
630}
631
79e53945
JB		 632/**
633 * Returns whether any output on the specified pipe is of the specified type
634 */
4ef69c7a 635bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 636{
4ef69c7a 637 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 638 struct intel_encoder *encoder;
639
6c2b7c12
DV		 640 for_each_encoder_on_crtc(dev, crtc, encoder)
641 if (encoder->type == type)
4ef69c7a
CW		 642 return true;
643
644 return false;
79e53945
JB		 645}
646
7c04d1d9 647#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 648/**
649 * Returns whether the given set of divisors are valid for a given refclk with
650 * the given connectors.
651 */
652
1b894b59
CW		 653static bool intel_PLL_is_valid(struct drm_device *dev,
654 const intel_limit_t *limit,
655 const intel_clock_t *clock)
79e53945 656{
79e53945 657 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 658 INTELPllInvalid("p1 out of range\n");
79e53945 659 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 660 INTELPllInvalid("p out of range\n");
79e53945 661 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 662 INTELPllInvalid("m2 out of range\n");
79e53945 663 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 664 INTELPllInvalid("m1 out of range\n");
f2b115e6 665 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 666 INTELPllInvalid("m1 <= m2\n");
79e53945 667 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 668 INTELPllInvalid("m out of range\n");
79e53945 669 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 670 INTELPllInvalid("n out of range\n");
79e53945 671 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 672 INTELPllInvalid("vco out of range\n");
79e53945
JB		 673 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
674 * connector, etc., rather than just a single range.
675 */
676 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 677 INTELPllInvalid("dot out of range\n");
79e53945
JB		 678
679 return true;
680}
681
d4906093
ML		 682static bool
683intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 684 int target, int refclk, intel_clock_t *match_clock,
685 intel_clock_t *best_clock)
d4906093 686
79e53945
JB		 687{
688 struct drm_device *dev = crtc->dev;
689 struct drm_i915_private *dev_priv = dev->dev_private;
690 intel_clock_t clock;
79e53945
JB		 691 int err = target;
692
bc5e5718 693 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 694 (I915_READ(LVDS)) != 0) {
79e53945
JB		 695 /*
696 * For LVDS, if the panel is on, just rely on its current
697 * settings for dual-channel. We haven't figured out how to
698 * reliably set up different single/dual channel state, if we
699 * even can.
700 */
b0354385 701 if (is_dual_link_lvds(dev_priv, LVDS))
79e53945
JB		 702 clock.p2 = limit->p2.p2_fast;
703 else
704 clock.p2 = limit->p2.p2_slow;
705 } else {
706 if (target < limit->p2.dot_limit)
707 clock.p2 = limit->p2.p2_slow;
708 else
709 clock.p2 = limit->p2.p2_fast;
710 }
711
0206e353 712 memset(best_clock, 0, sizeof(*best_clock));
79e53945 713
42158660
ZY		 714 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
715 clock.m1++) {
716 for (clock.m2 = limit->m2.min;
717 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 718 /* m1 is always 0 in Pineview */
719 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 720 break;
721 for (clock.n = limit->n.min;
722 clock.n <= limit->n.max; clock.n++) {
723 for (clock.p1 = limit->p1.min;
724 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 725 int this_err;
726
2177832f 727 intel_clock(dev, refclk, &clock);
1b894b59
CW		 728 if (!intel_PLL_is_valid(dev, limit,
729 &clock))
79e53945 730 continue;
cec2f356
SP		 731 if (match_clock &&
732 clock.p != match_clock->p)
733 continue;
79e53945
JB		 734
735 this_err = abs(clock.dot - target);
736 if (this_err < err) {
737 *best_clock = clock;
738 err = this_err;
739 }
740 }
741 }
742 }
743 }
744
745 return (err != target);
746}
747
d4906093
ML		 748static bool
749intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 750 int target, int refclk, intel_clock_t *match_clock,
751 intel_clock_t *best_clock)
d4906093
ML		 752{
753 struct drm_device *dev = crtc->dev;
754 struct drm_i915_private *dev_priv = dev->dev_private;
755 intel_clock_t clock;
756 int max_n;
757 bool found;
6ba770dc
AJ		 758 /* approximately equals target * 0.00585 */
759 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 760 found = false;
761
762 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 763 int lvds_reg;
764
c619eed4 765 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 766 lvds_reg = PCH_LVDS;
767 else
768 lvds_reg = LVDS;
769 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 770 LVDS_CLKB_POWER_UP)
771 clock.p2 = limit->p2.p2_fast;
772 else
773 clock.p2 = limit->p2.p2_slow;
774 } else {
775 if (target < limit->p2.dot_limit)
776 clock.p2 = limit->p2.p2_slow;
777 else
778 clock.p2 = limit->p2.p2_fast;
779 }
780
781 memset(best_clock, 0, sizeof(*best_clock));
782 max_n = limit->n.max;
f77f13e2 783 /* based on hardware requirement, prefer smaller n to precision */
d4906093 784 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 785 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 786 for (clock.m1 = limit->m1.max;
787 clock.m1 >= limit->m1.min; clock.m1--) {
788 for (clock.m2 = limit->m2.max;
789 clock.m2 >= limit->m2.min; clock.m2--) {
790 for (clock.p1 = limit->p1.max;
791 clock.p1 >= limit->p1.min; clock.p1--) {
792 int this_err;
793
2177832f 794 intel_clock(dev, refclk, &clock);
1b894b59
CW		 795 if (!intel_PLL_is_valid(dev, limit,
796 &clock))
d4906093 797 continue;
cec2f356
SP		 798 if (match_clock &&
799 clock.p != match_clock->p)
800 continue;
1b894b59
CW		 801
802 this_err = abs(clock.dot - target);
d4906093
ML		 803 if (this_err < err_most) {
804 *best_clock = clock;
805 err_most = this_err;
806 max_n = clock.n;
807 found = true;
808 }
809 }
810 }
811 }
812 }
2c07245f
ZW		 813 return found;
814}
815
5eb08b69 816static bool
f2b115e6 817intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 818 int target, int refclk, intel_clock_t *match_clock,
819 intel_clock_t *best_clock)
5eb08b69
ZW		 820{
821 struct drm_device *dev = crtc->dev;
822 intel_clock_t clock;
4547668a 823
5eb08b69
ZW		 824 if (target < 200000) {
825 clock.n = 1;
826 clock.p1 = 2;
827 clock.p2 = 10;
828 clock.m1 = 12;
829 clock.m2 = 9;
830 } else {
831 clock.n = 2;
832 clock.p1 = 1;
833 clock.p2 = 10;
834 clock.m1 = 14;
835 clock.m2 = 8;
836 }
837 intel_clock(dev, refclk, &clock);
838 memcpy(best_clock, &clock, sizeof(intel_clock_t));
839 return true;
840}
841
a4fc5ed6
KP		 842/* DisplayPort has only two frequencies, 162MHz and 270MHz */
843static bool
844intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 845 int target, int refclk, intel_clock_t *match_clock,
846 intel_clock_t *best_clock)
a4fc5ed6 847{
5eddb70b
CW		 848 intel_clock_t clock;
849 if (target < 200000) {
850 clock.p1 = 2;
851 clock.p2 = 10;
852 clock.n = 2;
853 clock.m1 = 23;
854 clock.m2 = 8;
855 } else {
856 clock.p1 = 1;
857 clock.p2 = 10;
858 clock.n = 1;
859 clock.m1 = 14;
860 clock.m2 = 2;
861 }
862 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
863 clock.p = (clock.p1 * clock.p2);
864 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
865 clock.vco = 0;
866 memcpy(best_clock, &clock, sizeof(intel_clock_t));
867 return true;
a4fc5ed6 868}
a0c4da24
JB		 869static bool
870intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
871 int target, int refclk, intel_clock_t *match_clock,
872 intel_clock_t *best_clock)
873{
874 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
875 u32 m, n, fastclk;
876 u32 updrate, minupdate, fracbits, p;
877 unsigned long bestppm, ppm, absppm;
878 int dotclk, flag;
879
af447bd3 880 flag = 0;
a0c4da24
JB		 881 dotclk = target * 1000;
882 bestppm = 1000000;
883 ppm = absppm = 0;
884 fastclk = dotclk / (2*100);
885 updrate = 0;
886 minupdate = 19200;
887 fracbits = 1;
888 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
889 bestm1 = bestm2 = bestp1 = bestp2 = 0;
890
891 /* based on hardware requirement, prefer smaller n to precision */
892 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
893 updrate = refclk / n;
894 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
895 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
896 if (p2 > 10)
897 p2 = p2 - 1;
898 p = p1 * p2;
899 /* based on hardware requirement, prefer bigger m1,m2 values */
900 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
901 m2 = (((2*(fastclk * p * n / m1 )) +
902 refclk) / (2*refclk));
903 m = m1 * m2;
904 vco = updrate * m;
905 if (vco >= limit->vco.min && vco < limit->vco.max) {
906 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
907 absppm = (ppm > 0) ? ppm : (-ppm);
908 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
909 bestppm = 0;
910 flag = 1;
911 }
912 if (absppm < bestppm - 10) {
913 bestppm = absppm;
914 flag = 1;
915 }
916 if (flag) {
917 bestn = n;
918 bestm1 = m1;
919 bestm2 = m2;
920 bestp1 = p1;
921 bestp2 = p2;
922 flag = 0;
923 }
924 }
925 }
926 }
927 }
928 }
929 best_clock->n = bestn;
930 best_clock->m1 = bestm1;
931 best_clock->m2 = bestm2;
932 best_clock->p1 = bestp1;
933 best_clock->p2 = bestp2;
934
935 return true;
936}
a4fc5ed6 937
a5c961d1
PZ		 938enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
939 enum pipe pipe)
940{
941 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
942 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
943
944 return intel_crtc->cpu_transcoder;
945}
946
a928d536
PZ		 947static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
948{
949 struct drm_i915_private *dev_priv = dev->dev_private;
950 u32 frame, frame_reg = PIPEFRAME(pipe);
951
952 frame = I915_READ(frame_reg);
953
954 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
955 DRM_DEBUG_KMS("vblank wait timed out\n");
956}
957
9d0498a2
JB		 958/**
959 * intel_wait_for_vblank - wait for vblank on a given pipe
960 * @dev: drm device
961 * @pipe: pipe to wait for
962 *
963 * Wait for vblank to occur on a given pipe. Needed for various bits of
964 * mode setting code.
965 */
966void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 967{
9d0498a2 968 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 969 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 970
a928d536
PZ		 971 if (INTEL_INFO(dev)->gen >= 5) {
972 ironlake_wait_for_vblank(dev, pipe);
973 return;
974 }
975
300387c0
CW		 976 /* Clear existing vblank status. Note this will clear any other
977 * sticky status fields as well.
978 *
979 * This races with i915_driver_irq_handler() with the result
980 * that either function could miss a vblank event. Here it is not
981 * fatal, as we will either wait upon the next vblank interrupt or
982 * timeout. Generally speaking intel_wait_for_vblank() is only
983 * called during modeset at which time the GPU should be idle and
984 * should *not* be performing page flips and thus not waiting on
985 * vblanks...
986 * Currently, the result of us stealing a vblank from the irq
987 * handler is that a single frame will be skipped during swapbuffers.
988 */
989 I915_WRITE(pipestat_reg,
990 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
991
9d0498a2 992 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 993 if (wait_for(I915_READ(pipestat_reg) &
994 PIPE_VBLANK_INTERRUPT_STATUS,
995 50))
9d0498a2
JB		 996 DRM_DEBUG_KMS("vblank wait timed out\n");
997}
998
ab7ad7f6
KP		 999/*
1000 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 1001 * @dev: drm device
1002 * @pipe: pipe to wait for
1003 *
1004 * After disabling a pipe, we can't wait for vblank in the usual way,
1005 * spinning on the vblank interrupt status bit, since we won't actually
1006 * see an interrupt when the pipe is disabled.
1007 *
ab7ad7f6
KP		 1008 * On Gen4 and above:
1009 * wait for the pipe register state bit to turn off
1010 *
1011 * Otherwise:
1012 * wait for the display line value to settle (it usually
1013 * ends up stopping at the start of the next frame).
58e10eb9 1014 *
9d0498a2 1015 */
58e10eb9 1016void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 1017{
1018 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 1019 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1020 pipe);
ab7ad7f6
KP		 1021
1022 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1023 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1024
1025 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1026 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1027 100))
284637d9 1028 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1029 } else {
837ba00f 1030 u32 last_line, line_mask;
58e10eb9 1031 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 1032 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1033
837ba00f
PZ		 1034 if (IS_GEN2(dev))
1035 line_mask = DSL_LINEMASK_GEN2;
1036 else
1037 line_mask = DSL_LINEMASK_GEN3;
1038
ab7ad7f6
KP		 1039 /* Wait for the display line to settle */
1040 do {
837ba00f 1041 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 1042 mdelay(5);
837ba00f 1043 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 1044 time_after(timeout, jiffies));
1045 if (time_after(jiffies, timeout))
284637d9 1046 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1047 }
79e53945
JB		 1048}
1049
b24e7179
JB		 1050static const char *state_string(bool enabled)
1051{
1052 return enabled ? "on" : "off";
1053}
1054
1055/* Only for pre-ILK configs */
1056static void assert_pll(struct drm_i915_private *dev_priv,
1057 enum pipe pipe, bool state)
1058{
1059 int reg;
1060 u32 val;
1061 bool cur_state;
1062
1063 reg = DPLL(pipe);
1064 val = I915_READ(reg);
1065 cur_state = !!(val & DPLL_VCO_ENABLE);
1066 WARN(cur_state != state,
1067 "PLL state assertion failure (expected %s, current %s)\n",
1068 state_string(state), state_string(cur_state));
1069}
1070#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1071#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1072
040484af
JB		 1073/* For ILK+ */
1074static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1075 struct intel_pch_pll *pll,
1076 struct intel_crtc *crtc,
1077 bool state)
040484af 1078{
040484af
JB		 1079 u32 val;
1080 bool cur_state;
1081
9d82aa17
ED		 1082 if (HAS_PCH_LPT(dev_priv->dev)) {
1083 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1084 return;
1085 }
1086
92b27b08
CW		 1087 if (WARN (!pll,
1088 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1089 return;
ee7b9f93 1090
92b27b08
CW		 1091 val = I915_READ(pll->pll_reg);
1092 cur_state = !!(val & DPLL_VCO_ENABLE);
1093 WARN(cur_state != state,
1094 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1095 pll->pll_reg, state_string(state), state_string(cur_state), val);
1096
1097 /* Make sure the selected PLL is correctly attached to the transcoder */
1098 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1099 u32 pch_dpll;
1100
1101 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1102 cur_state = pll->pll_reg == _PCH_DPLL_B;
1103 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1104 "PLL[%d] not attached to this transcoder %d: %08x\n",
1105 cur_state, crtc->pipe, pch_dpll)) {
1106 cur_state = !!(val >> (4*crtc->pipe + 3));
1107 WARN(cur_state != state,
1108 "PLL[%d] not %s on this transcoder %d: %08x\n",
1109 pll->pll_reg == _PCH_DPLL_B,
1110 state_string(state),
1111 crtc->pipe,
1112 val);
1113 }
d3ccbe86 1114 }
040484af 1115}
92b27b08
CW		 1116#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1117#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1118
1119static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1120 enum pipe pipe, bool state)
1121{
1122 int reg;
1123 u32 val;
1124 bool cur_state;
ad80a810
PZ		 1125 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1126 pipe);
040484af 1127
bf507ef7
ED		 1128 if (IS_HASWELL(dev_priv->dev)) {
1129 /* On Haswell, DDI is used instead of FDI_TX_CTL */
ad80a810 1130 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1131 val = I915_READ(reg);
ad80a810 1132 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1133 } else {
1134 reg = FDI_TX_CTL(pipe);
1135 val = I915_READ(reg);
1136 cur_state = !!(val & FDI_TX_ENABLE);
1137 }
040484af
JB		 1138 WARN(cur_state != state,
1139 "FDI TX state assertion failure (expected %s, current %s)\n",
1140 state_string(state), state_string(cur_state));
1141}
1142#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1143#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1144
1145static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1146 enum pipe pipe, bool state)
1147{
1148 int reg;
1149 u32 val;
1150 bool cur_state;
1151
59c859d6
ED		 1152 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1153 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1154 return;
1155 } else {
1156 reg = FDI_RX_CTL(pipe);
1157 val = I915_READ(reg);
1158 cur_state = !!(val & FDI_RX_ENABLE);
1159 }
040484af
JB		 1160 WARN(cur_state != state,
1161 "FDI RX state assertion failure (expected %s, current %s)\n",
1162 state_string(state), state_string(cur_state));
1163}
1164#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1165#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1166
1167static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1168 enum pipe pipe)
1169{
1170 int reg;
1171 u32 val;
1172
1173 /* ILK FDI PLL is always enabled */
1174 if (dev_priv->info->gen == 5)
1175 return;
1176
bf507ef7
ED		 1177 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1178 if (IS_HASWELL(dev_priv->dev))
1179 return;
1180
040484af
JB		 1181 reg = FDI_TX_CTL(pipe);
1182 val = I915_READ(reg);
1183 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1184}
1185
1186static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1187 enum pipe pipe)
1188{
1189 int reg;
1190 u32 val;
1191
59c859d6
ED		 1192 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1193 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1194 return;
1195 }
040484af
JB		 1196 reg = FDI_RX_CTL(pipe);
1197 val = I915_READ(reg);
1198 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1199}
1200
ea0760cf
JB		 1201static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1202 enum pipe pipe)
1203{
1204 int pp_reg, lvds_reg;
1205 u32 val;
1206 enum pipe panel_pipe = PIPE_A;
0de3b485 1207 bool locked = true;
ea0760cf
JB		 1208
1209 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1210 pp_reg = PCH_PP_CONTROL;
1211 lvds_reg = PCH_LVDS;
1212 } else {
1213 pp_reg = PP_CONTROL;
1214 lvds_reg = LVDS;
1215 }
1216
1217 val = I915_READ(pp_reg);
1218 if (!(val & PANEL_POWER_ON) ||
1219 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1220 locked = false;
1221
1222 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1223 panel_pipe = PIPE_B;
1224
1225 WARN(panel_pipe == pipe && locked,
1226 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1227 pipe_name(pipe));
ea0760cf
JB		 1228}
1229
b840d907
JB		 1230void assert_pipe(struct drm_i915_private *dev_priv,
1231 enum pipe pipe, bool state)
b24e7179
JB		 1232{
1233 int reg;
1234 u32 val;
63d7bbe9 1235 bool cur_state;
702e7a56
PZ		 1236 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1237 pipe);
b24e7179 1238
8e636784
DV		 1239 /* if we need the pipe A quirk it must be always on */
1240 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1241 state = true;
1242
702e7a56 1243 reg = PIPECONF(cpu_transcoder);
b24e7179 1244 val = I915_READ(reg);
63d7bbe9
JB		 1245 cur_state = !!(val & PIPECONF_ENABLE);
1246 WARN(cur_state != state,
1247 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1248 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1249}
1250
931872fc
CW		 1251static void assert_plane(struct drm_i915_private *dev_priv,
1252 enum plane plane, bool state)
b24e7179
JB		 1253{
1254 int reg;
1255 u32 val;
931872fc 1256 bool cur_state;
b24e7179
JB		 1257
1258 reg = DSPCNTR(plane);
1259 val = I915_READ(reg);
931872fc
CW		 1260 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1261 WARN(cur_state != state,
1262 "plane %c assertion failure (expected %s, current %s)\n",
1263 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1264}
1265
931872fc
CW		 1266#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1267#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1268
b24e7179
JB		 1269static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1270 enum pipe pipe)
1271{
1272 int reg, i;
1273 u32 val;
1274 int cur_pipe;
1275
19ec1358 1276 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 1277 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1278 reg = DSPCNTR(pipe);
1279 val = I915_READ(reg);
1280 WARN((val & DISPLAY_PLANE_ENABLE),
1281 "plane %c assertion failure, should be disabled but not\n",
1282 plane_name(pipe));
19ec1358 1283 return;
28c05794 1284 }
19ec1358 1285
b24e7179
JB		 1286 /* Need to check both planes against the pipe */
1287 for (i = 0; i < 2; i++) {
1288 reg = DSPCNTR(i);
1289 val = I915_READ(reg);
1290 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1291 DISPPLANE_SEL_PIPE_SHIFT;
1292 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1293 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1294 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1295 }
1296}
1297
92f2584a
JB		 1298static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1299{
1300 u32 val;
1301 bool enabled;
1302
9d82aa17
ED		 1303 if (HAS_PCH_LPT(dev_priv->dev)) {
1304 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1305 return;
1306 }
1307
92f2584a
JB		 1308 val = I915_READ(PCH_DREF_CONTROL);
1309 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1310 DREF_SUPERSPREAD_SOURCE_MASK));
1311 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1312}
1313
1314static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1315 enum pipe pipe)
1316{
1317 int reg;
1318 u32 val;
1319 bool enabled;
1320
1321 reg = TRANSCONF(pipe);
1322 val = I915_READ(reg);
1323 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1324 WARN(enabled,
1325 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1326 pipe_name(pipe));
92f2584a
JB		 1327}
1328
4e634389
KP		 1329static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1330 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1331{
1332 if ((val & DP_PORT_EN) == 0)
1333 return false;
1334
1335 if (HAS_PCH_CPT(dev_priv->dev)) {
1336 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1337 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1338 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1339 return false;
1340 } else {
1341 if ((val & DP_PIPE_MASK) != (pipe << 30))
1342 return false;
1343 }
1344 return true;
1345}
1346
1519b995
KP		 1347static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1348 enum pipe pipe, u32 val)
1349{
1350 if ((val & PORT_ENABLE) == 0)
1351 return false;
1352
1353 if (HAS_PCH_CPT(dev_priv->dev)) {
1354 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1355 return false;
1356 } else {
1357 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1358 return false;
1359 }
1360 return true;
1361}
1362
1363static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1364 enum pipe pipe, u32 val)
1365{
1366 if ((val & LVDS_PORT_EN) == 0)
1367 return false;
1368
1369 if (HAS_PCH_CPT(dev_priv->dev)) {
1370 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1371 return false;
1372 } else {
1373 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1374 return false;
1375 }
1376 return true;
1377}
1378
1379static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1380 enum pipe pipe, u32 val)
1381{
1382 if ((val & ADPA_DAC_ENABLE) == 0)
1383 return false;
1384 if (HAS_PCH_CPT(dev_priv->dev)) {
1385 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1386 return false;
1387 } else {
1388 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1389 return false;
1390 }
1391 return true;
1392}
1393
291906f1 1394static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1395 enum pipe pipe, int reg, u32 port_sel)
291906f1 1396{
47a05eca 1397 u32 val = I915_READ(reg);
4e634389 1398 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1399 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1400 reg, pipe_name(pipe));
de9a35ab 1401
75c5da27
DV		 1402 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1403 && (val & DP_PIPEB_SELECT),
de9a35ab 1404 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1405}
1406
1407static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1408 enum pipe pipe, int reg)
1409{
47a05eca 1410 u32 val = I915_READ(reg);
e9a851ed 1411 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1412 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1413 reg, pipe_name(pipe));
de9a35ab 1414
75c5da27
DV		 1415 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1416 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1417 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1418}
1419
1420static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1421 enum pipe pipe)
1422{
1423 int reg;
1424 u32 val;
291906f1 1425
f0575e92
KP		 1426 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1427 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1428 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1429
1430 reg = PCH_ADPA;
1431 val = I915_READ(reg);
e9a851ed 1432 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1433 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1434 pipe_name(pipe));
291906f1
JB		 1435
1436 reg = PCH_LVDS;
1437 val = I915_READ(reg);
e9a851ed 1438 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1439 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1440 pipe_name(pipe));
291906f1
JB		 1441
1442 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1443 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1444 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1445}
1446
63d7bbe9
JB		 1447/**
1448 * intel_enable_pll - enable a PLL
1449 * @dev_priv: i915 private structure
1450 * @pipe: pipe PLL to enable
1451 *
1452 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1453 * make sure the PLL reg is writable first though, since the panel write
1454 * protect mechanism may be enabled.
1455 *
1456 * Note! This is for pre-ILK only.
7434a255
TR		 1457 *
1458 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9 1459 */
a37b9b34 1460static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9
JB		 1461{
1462 int reg;
1463 u32 val;
1464
1465 /* No really, not for ILK+ */
a0c4da24 1466 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1467
1468 /* PLL is protected by panel, make sure we can write it */
1469 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1470 assert_panel_unlocked(dev_priv, pipe);
1471
1472 reg = DPLL(pipe);
1473 val = I915_READ(reg);
1474 val |= DPLL_VCO_ENABLE;
1475
1476 /* We do this three times for luck */
1477 I915_WRITE(reg, val);
1478 POSTING_READ(reg);
1479 udelay(150); /* wait for warmup */
1480 I915_WRITE(reg, val);
1481 POSTING_READ(reg);
1482 udelay(150); /* wait for warmup */
1483 I915_WRITE(reg, val);
1484 POSTING_READ(reg);
1485 udelay(150); /* wait for warmup */
1486}
1487
1488/**
1489 * intel_disable_pll - disable a PLL
1490 * @dev_priv: i915 private structure
1491 * @pipe: pipe PLL to disable
1492 *
1493 * Disable the PLL for @pipe, making sure the pipe is off first.
1494 *
1495 * Note! This is for pre-ILK only.
1496 */
1497static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1498{
1499 int reg;
1500 u32 val;
1501
1502 /* Don't disable pipe A or pipe A PLLs if needed */
1503 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1504 return;
1505
1506 /* Make sure the pipe isn't still relying on us */
1507 assert_pipe_disabled(dev_priv, pipe);
1508
1509 reg = DPLL(pipe);
1510 val = I915_READ(reg);
1511 val &= ~DPLL_VCO_ENABLE;
1512 I915_WRITE(reg, val);
1513 POSTING_READ(reg);
1514}
1515
a416edef
ED		 1516/* SBI access */
1517static void
1518intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1519{
1520 unsigned long flags;
1521
1522 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1523 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1524 100)) {
1525 DRM_ERROR("timeout waiting for SBI to become ready\n");
1526 goto out_unlock;
1527 }
1528
1529 I915_WRITE(SBI_ADDR,
1530 (reg << 16));
1531 I915_WRITE(SBI_DATA,
1532 value);
1533 I915_WRITE(SBI_CTL_STAT,
1534 SBI_BUSY |
1535 SBI_CTL_OP_CRWR);
1536
39fb50f6 1537 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1538 100)) {
1539 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1540 goto out_unlock;
1541 }
1542
1543out_unlock:
1544 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1545}
1546
1547static u32
1548intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1549{
1550 unsigned long flags;
39fb50f6 1551 u32 value = 0;
a416edef
ED		 1552
1553 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1554 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1555 100)) {
1556 DRM_ERROR("timeout waiting for SBI to become ready\n");
1557 goto out_unlock;
1558 }
1559
1560 I915_WRITE(SBI_ADDR,
1561 (reg << 16));
1562 I915_WRITE(SBI_CTL_STAT,
1563 SBI_BUSY |
1564 SBI_CTL_OP_CRRD);
1565
39fb50f6 1566 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1567 100)) {
1568 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1569 goto out_unlock;
1570 }
1571
1572 value = I915_READ(SBI_DATA);
1573
1574out_unlock:
1575 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1576 return value;
1577}
1578
92f2584a 1579/**
b6b4e185 1580 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1581 * @dev_priv: i915 private structure
1582 * @pipe: pipe PLL to enable
1583 *
1584 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1585 * drives the transcoder clock.
1586 */
b6b4e185 1587static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1588{
ee7b9f93 1589 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1590 struct intel_pch_pll *pll;
92f2584a
JB		 1591 int reg;
1592 u32 val;
1593
48da64a8 1594 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1595 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1596 pll = intel_crtc->pch_pll;
1597 if (pll == NULL)
1598 return;
1599
1600 if (WARN_ON(pll->refcount == 0))
1601 return;
ee7b9f93
JB		 1602
1603 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1604 pll->pll_reg, pll->active, pll->on,
1605 intel_crtc->base.base.id);
92f2584a
JB		 1606
1607 /* PCH refclock must be enabled first */
1608 assert_pch_refclk_enabled(dev_priv);
1609
ee7b9f93 1610 if (pll->active++ && pll->on) {
92b27b08 1611 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1612 return;
1613 }
1614
1615 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1616
1617 reg = pll->pll_reg;
92f2584a
JB		 1618 val = I915_READ(reg);
1619 val |= DPLL_VCO_ENABLE;
1620 I915_WRITE(reg, val);
1621 POSTING_READ(reg);
1622 udelay(200);
ee7b9f93
JB		 1623
1624 pll->on = true;
92f2584a
JB		 1625}
1626
ee7b9f93 1627static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1628{
ee7b9f93
JB		 1629 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1630 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1631 int reg;
ee7b9f93 1632 u32 val;
4c609cb8 1633
92f2584a
JB		 1634 /* PCH only available on ILK+ */
1635 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1636 if (pll == NULL)
1637 return;
92f2584a 1638
48da64a8
CW		 1639 if (WARN_ON(pll->refcount == 0))
1640 return;
7a419866 1641
ee7b9f93
JB		 1642 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1643 pll->pll_reg, pll->active, pll->on,
1644 intel_crtc->base.base.id);
7a419866 1645
48da64a8 1646 if (WARN_ON(pll->active == 0)) {
92b27b08 1647 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1648 return;
1649 }
1650
ee7b9f93 1651 if (--pll->active) {
92b27b08 1652 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1653 return;
ee7b9f93
JB		 1654 }
1655
1656 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1657
1658 /* Make sure transcoder isn't still depending on us */
1659 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1660
ee7b9f93 1661 reg = pll->pll_reg;
92f2584a
JB		 1662 val = I915_READ(reg);
1663 val &= ~DPLL_VCO_ENABLE;
1664 I915_WRITE(reg, val);
1665 POSTING_READ(reg);
1666 udelay(200);
ee7b9f93
JB		 1667
1668 pll->on = false;
92f2584a
JB		 1669}
1670
b8a4f404
PZ		 1671static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1672 enum pipe pipe)
040484af 1673{
23670b32 1674 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1675 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1676 uint32_t reg, val, pipeconf_val;
040484af
JB		 1677
1678 /* PCH only available on ILK+ */
1679 BUG_ON(dev_priv->info->gen < 5);
1680
1681 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1682 assert_pch_pll_enabled(dev_priv,
1683 to_intel_crtc(crtc)->pch_pll,
1684 to_intel_crtc(crtc));
040484af
JB		 1685
1686 /* FDI must be feeding us bits for PCH ports */
1687 assert_fdi_tx_enabled(dev_priv, pipe);
1688 assert_fdi_rx_enabled(dev_priv, pipe);
1689
23670b32
DV		 1690 if (HAS_PCH_CPT(dev)) {
1691 /* Workaround: Set the timing override bit before enabling the
1692 * pch transcoder. */
1693 reg = TRANS_CHICKEN2(pipe);
1694 val = I915_READ(reg);
1695 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1696 I915_WRITE(reg, val);
1697 }
1698
040484af
JB		 1699 reg = TRANSCONF(pipe);
1700 val = I915_READ(reg);
5f7f726d 1701 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1702
1703 if (HAS_PCH_IBX(dev_priv->dev)) {
1704 /*
1705 * make the BPC in transcoder be consistent with
1706 * that in pipeconf reg.
1707 */
1708 val &= ~PIPE_BPC_MASK;
5f7f726d 1709 val |= pipeconf_val & PIPE_BPC_MASK;
e9bcff5c 1710 }
5f7f726d
PZ		 1711
1712 val &= ~TRANS_INTERLACE_MASK;
1713 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1714 if (HAS_PCH_IBX(dev_priv->dev) &&
1715 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1716 val |= TRANS_LEGACY_INTERLACED_ILK;
1717 else
1718 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1719 else
1720 val |= TRANS_PROGRESSIVE;
1721
040484af
JB		 1722 I915_WRITE(reg, val | TRANS_ENABLE);
1723 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1724 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1725}
1726
8fb033d7 1727static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1728 enum transcoder cpu_transcoder)
8fb033d7 1729{
8fb033d7 1730 u32 val, pipeconf_val;
8fb033d7
PZ		 1731
1732 /* PCH only available on ILK+ */
1733 BUG_ON(dev_priv->info->gen < 5);
1734
8fb033d7 1735 /* FDI must be feeding us bits for PCH ports */
937bb610
PZ		 1736 assert_fdi_tx_enabled(dev_priv, cpu_transcoder);
1737 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1738
223a6fdf
PZ		 1739 /* Workaround: set timing override bit. */
1740 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1741 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1742 I915_WRITE(_TRANSA_CHICKEN2, val);
1743
25f3ef11 1744 val = TRANS_ENABLE;
937bb610 1745 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1746
9a76b1c6
PZ		 1747 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1748 PIPECONF_INTERLACED_ILK)
a35f2679 1749 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1750 else
1751 val |= TRANS_PROGRESSIVE;
1752
25f3ef11 1753 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
937bb610
PZ		 1754 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1755 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1756}
1757
b8a4f404
PZ		 1758static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1759 enum pipe pipe)
040484af 1760{
23670b32
DV		 1761 struct drm_device *dev = dev_priv->dev;
1762 uint32_t reg, val;
040484af
JB		 1763
1764 /* FDI relies on the transcoder */
1765 assert_fdi_tx_disabled(dev_priv, pipe);
1766 assert_fdi_rx_disabled(dev_priv, pipe);
1767
291906f1
JB		 1768 /* Ports must be off as well */
1769 assert_pch_ports_disabled(dev_priv, pipe);
1770
040484af
JB		 1771 reg = TRANSCONF(pipe);
1772 val = I915_READ(reg);
1773 val &= ~TRANS_ENABLE;
1774 I915_WRITE(reg, val);
1775 /* wait for PCH transcoder off, transcoder state */
1776 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1777 DRM_ERROR("failed to disable transcoder %d\n", pipe);
23670b32
DV		 1778
1779 if (!HAS_PCH_IBX(dev)) {
1780 /* Workaround: Clear the timing override chicken bit again. */
1781 reg = TRANS_CHICKEN2(pipe);
1782 val = I915_READ(reg);
1783 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1784 I915_WRITE(reg, val);
1785 }
040484af
JB		 1786}
1787
ab4d966c 1788static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1789{
8fb033d7
PZ		 1790 u32 val;
1791
8a52fd9f 1792 val = I915_READ(_TRANSACONF);
8fb033d7 1793 val &= ~TRANS_ENABLE;
8a52fd9f 1794 I915_WRITE(_TRANSACONF, val);
8fb033d7 1795 /* wait for PCH transcoder off, transcoder state */
8a52fd9f
PZ		 1796 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1797 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1798
1799 /* Workaround: clear timing override bit. */
1800 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1801 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1802 I915_WRITE(_TRANSA_CHICKEN2, val);
8fb033d7
PZ		 1803}
1804
b24e7179 1805/**
309cfea8 1806 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1807 * @dev_priv: i915 private structure
1808 * @pipe: pipe to enable
040484af 1809 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1810 *
1811 * Enable @pipe, making sure that various hardware specific requirements
1812 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1813 *
1814 * @pipe should be %PIPE_A or %PIPE_B.
1815 *
1816 * Will wait until the pipe is actually running (i.e. first vblank) before
1817 * returning.
1818 */
040484af
JB		 1819static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1820 bool pch_port)
b24e7179 1821{
702e7a56
PZ		 1822 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1823 pipe);
b24e7179
JB		 1824 int reg;
1825 u32 val;
1826
1827 /*
1828 * A pipe without a PLL won't actually be able to drive bits from
1829 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1830 * need the check.
1831 */
1832 if (!HAS_PCH_SPLIT(dev_priv->dev))
1833 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1834 else {
1835 if (pch_port) {
1836 /* if driving the PCH, we need FDI enabled */
1837 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1838 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1839 }
1840 /* FIXME: assert CPU port conditions for SNB+ */
1841 }
b24e7179 1842
702e7a56 1843 reg = PIPECONF(cpu_transcoder);
b24e7179 1844 val = I915_READ(reg);
00d70b15
CW		 1845 if (val & PIPECONF_ENABLE)
1846 return;
1847
1848 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1849 intel_wait_for_vblank(dev_priv->dev, pipe);
1850}
1851
1852/**
309cfea8 1853 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1854 * @dev_priv: i915 private structure
1855 * @pipe: pipe to disable
1856 *
1857 * Disable @pipe, making sure that various hardware specific requirements
1858 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1859 *
1860 * @pipe should be %PIPE_A or %PIPE_B.
1861 *
1862 * Will wait until the pipe has shut down before returning.
1863 */
1864static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1865 enum pipe pipe)
1866{
702e7a56
PZ		 1867 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1868 pipe);
b24e7179
JB		 1869 int reg;
1870 u32 val;
1871
1872 /*
1873 * Make sure planes won't keep trying to pump pixels to us,
1874 * or we might hang the display.
1875 */
1876 assert_planes_disabled(dev_priv, pipe);
1877
1878 /* Don't disable pipe A or pipe A PLLs if needed */
1879 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1880 return;
1881
702e7a56 1882 reg = PIPECONF(cpu_transcoder);
b24e7179 1883 val = I915_READ(reg);
00d70b15
CW		 1884 if ((val & PIPECONF_ENABLE) == 0)
1885 return;
1886
1887 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1888 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1889}
1890
d74362c9
KP		 1891/*
1892 * Plane regs are double buffered, going from enabled->disabled needs a
1893 * trigger in order to latch. The display address reg provides this.
1894 */
6f1d69b0 1895void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1896 enum plane plane)
1897{
14f86147
DL		 1898 if (dev_priv->info->gen >= 4)
1899 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1900 else
1901 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1902}
1903
b24e7179
JB		 1904/**
1905 * intel_enable_plane - enable a display plane on a given pipe
1906 * @dev_priv: i915 private structure
1907 * @plane: plane to enable
1908 * @pipe: pipe being fed
1909 *
1910 * Enable @plane on @pipe, making sure that @pipe is running first.
1911 */
1912static void intel_enable_plane(struct drm_i915_private *dev_priv,
1913 enum plane plane, enum pipe pipe)
1914{
1915 int reg;
1916 u32 val;
1917
1918 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1919 assert_pipe_enabled(dev_priv, pipe);
1920
1921 reg = DSPCNTR(plane);
1922 val = I915_READ(reg);
00d70b15
CW		 1923 if (val & DISPLAY_PLANE_ENABLE)
1924 return;
1925
1926 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1927 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1928 intel_wait_for_vblank(dev_priv->dev, pipe);
1929}
1930
b24e7179
JB		 1931/**
1932 * intel_disable_plane - disable a display plane
1933 * @dev_priv: i915 private structure
1934 * @plane: plane to disable
1935 * @pipe: pipe consuming the data
1936 *
1937 * Disable @plane; should be an independent operation.
1938 */
1939static void intel_disable_plane(struct drm_i915_private *dev_priv,
1940 enum plane plane, enum pipe pipe)
1941{
1942 int reg;
1943 u32 val;
1944
1945 reg = DSPCNTR(plane);
1946 val = I915_READ(reg);
00d70b15
CW		 1947 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1948 return;
1949
1950 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1951 intel_flush_display_plane(dev_priv, plane);
1952 intel_wait_for_vblank(dev_priv->dev, pipe);
1953}
1954
127bd2ac 1955int
48b956c5 1956intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1957 struct drm_i915_gem_object *obj,
919926ae 1958 struct intel_ring_buffer *pipelined)
6b95a207 1959{
ce453d81 1960 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1961 u32 alignment;
1962 int ret;
1963
05394f39 1964 switch (obj->tiling_mode) {
6b95a207 1965 case I915_TILING_NONE:
534843da
CW		 1966 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1967 alignment = 128 * 1024;
a6c45cf0 1968 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1969 alignment = 4 * 1024;
1970 else
1971 alignment = 64 * 1024;
6b95a207
KH		 1972 break;
1973 case I915_TILING_X:
1974 /* pin() will align the object as required by fence */
1975 alignment = 0;
1976 break;
1977 case I915_TILING_Y:
1978 /* FIXME: Is this true? */
1979 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1980 return -EINVAL;
1981 default:
1982 BUG();
1983 }
1984
ce453d81 1985 dev_priv->mm.interruptible = false;
2da3b9b9 1986 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1987 if (ret)
ce453d81 1988 goto err_interruptible;
6b95a207
KH		 1989
1990 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1991 * fence, whereas 965+ only requires a fence if using
1992 * framebuffer compression. For simplicity, we always install
1993 * a fence as the cost is not that onerous.
1994 */
06d98131 1995 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1996 if (ret)
1997 goto err_unpin;
1690e1eb 1998
9a5a53b3 1999 i915_gem_object_pin_fence(obj);
6b95a207 2000
ce453d81 2001 dev_priv->mm.interruptible = true;
6b95a207 2002 return 0;
48b956c5
CW		 2003
2004err_unpin:
2005 i915_gem_object_unpin(obj);
ce453d81
CW		 2006err_interruptible:
2007 dev_priv->mm.interruptible = true;
48b956c5 2008 return ret;
6b95a207
KH		 2009}
2010
1690e1eb
CW		 2011void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2012{
2013 i915_gem_object_unpin_fence(obj);
2014 i915_gem_object_unpin(obj);
2015}
2016
c2c75131
DV		 2017/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2018 * is assumed to be a power-of-two. */
5a35e99e
DL		 2019unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
2020 unsigned int bpp,
2021 unsigned int pitch)
c2c75131
DV		 2022{
2023 int tile_rows, tiles;
2024
2025 tile_rows = *y / 8;
2026 *y %= 8;
2027 tiles = *x / (512/bpp);
2028 *x %= 512/bpp;
2029
2030 return tile_rows * pitch * 8 + tiles * 4096;
2031}
2032
17638cd6
JB		 2033static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2034 int x, int y)
81255565
JB		 2035{
2036 struct drm_device *dev = crtc->dev;
2037 struct drm_i915_private *dev_priv = dev->dev_private;
2038 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2039 struct intel_framebuffer *intel_fb;
05394f39 2040 struct drm_i915_gem_object *obj;
81255565 2041 int plane = intel_crtc->plane;
e506a0c6 2042 unsigned long linear_offset;
81255565 2043 u32 dspcntr;
5eddb70b 2044 u32 reg;
81255565
JB		 2045
2046 switch (plane) {
2047 case 0:
2048 case 1:
2049 break;
2050 default:
2051 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2052 return -EINVAL;
2053 }
2054
2055 intel_fb = to_intel_framebuffer(fb);
2056 obj = intel_fb->obj;
81255565 2057
5eddb70b
CW		 2058 reg = DSPCNTR(plane);
2059 dspcntr = I915_READ(reg);
81255565
JB		 2060 /* Mask out pixel format bits in case we change it */
2061 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2062 switch (fb->pixel_format) {
2063 case DRM_FORMAT_C8:
81255565
JB		 2064 dspcntr |= DISPPLANE_8BPP;
2065 break;
57779d06
VS		 2066 case DRM_FORMAT_XRGB1555:
2067 case DRM_FORMAT_ARGB1555:
2068 dspcntr |= DISPPLANE_BGRX555;
81255565 2069 break;
57779d06
VS		 2070 case DRM_FORMAT_RGB565:
2071 dspcntr |= DISPPLANE_BGRX565;
2072 break;
2073 case DRM_FORMAT_XRGB8888:
2074 case DRM_FORMAT_ARGB8888:
2075 dspcntr |= DISPPLANE_BGRX888;
2076 break;
2077 case DRM_FORMAT_XBGR8888:
2078 case DRM_FORMAT_ABGR8888:
2079 dspcntr |= DISPPLANE_RGBX888;
2080 break;
2081 case DRM_FORMAT_XRGB2101010:
2082 case DRM_FORMAT_ARGB2101010:
2083 dspcntr |= DISPPLANE_BGRX101010;
2084 break;
2085 case DRM_FORMAT_XBGR2101010:
2086 case DRM_FORMAT_ABGR2101010:
2087 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2088 break;
2089 default:
57779d06 2090 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
81255565
JB		 2091 return -EINVAL;
2092 }
57779d06 2093
a6c45cf0 2094 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2095 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2096 dspcntr |= DISPPLANE_TILED;
2097 else
2098 dspcntr &= ~DISPPLANE_TILED;
2099 }
2100
5eddb70b 2101 I915_WRITE(reg, dspcntr);
81255565 2102
e506a0c6 2103 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2104
c2c75131
DV		 2105 if (INTEL_INFO(dev)->gen >= 4) {
2106 intel_crtc->dspaddr_offset =
5a35e99e
DL		 2107 intel_gen4_compute_offset_xtiled(&x, &y,
2108 fb->bits_per_pixel / 8,
2109 fb->pitches[0]);
c2c75131
DV		 2110 linear_offset -= intel_crtc->dspaddr_offset;
2111 } else {
e506a0c6 2112 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2113 }
e506a0c6
DV		 2114
2115 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2116 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2117 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2118 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2119 I915_MODIFY_DISPBASE(DSPSURF(plane),
2120 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2121 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2122 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2123 } else
e506a0c6 2124 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2125 POSTING_READ(reg);
81255565 2126
17638cd6
JB		 2127 return 0;
2128}
2129
2130static int ironlake_update_plane(struct drm_crtc *crtc,
2131 struct drm_framebuffer *fb, int x, int y)
2132{
2133 struct drm_device *dev = crtc->dev;
2134 struct drm_i915_private *dev_priv = dev->dev_private;
2135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2136 struct intel_framebuffer *intel_fb;
2137 struct drm_i915_gem_object *obj;
2138 int plane = intel_crtc->plane;
e506a0c6 2139 unsigned long linear_offset;
17638cd6
JB		 2140 u32 dspcntr;
2141 u32 reg;
2142
2143 switch (plane) {
2144 case 0:
2145 case 1:
27f8227b 2146 case 2:
17638cd6
JB		 2147 break;
2148 default:
2149 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2150 return -EINVAL;
2151 }
2152
2153 intel_fb = to_intel_framebuffer(fb);
2154 obj = intel_fb->obj;
2155
2156 reg = DSPCNTR(plane);
2157 dspcntr = I915_READ(reg);
2158 /* Mask out pixel format bits in case we change it */
2159 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2160 switch (fb->pixel_format) {
2161 case DRM_FORMAT_C8:
17638cd6
JB		 2162 dspcntr |= DISPPLANE_8BPP;
2163 break;
57779d06
VS		 2164 case DRM_FORMAT_RGB565:
2165 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2166 break;
57779d06
VS		 2167 case DRM_FORMAT_XRGB8888:
2168 case DRM_FORMAT_ARGB8888:
2169 dspcntr |= DISPPLANE_BGRX888;
2170 break;
2171 case DRM_FORMAT_XBGR8888:
2172 case DRM_FORMAT_ABGR8888:
2173 dspcntr |= DISPPLANE_RGBX888;
2174 break;
2175 case DRM_FORMAT_XRGB2101010:
2176 case DRM_FORMAT_ARGB2101010:
2177 dspcntr |= DISPPLANE_BGRX101010;
2178 break;
2179 case DRM_FORMAT_XBGR2101010:
2180 case DRM_FORMAT_ABGR2101010:
2181 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2182 break;
2183 default:
57779d06 2184 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
17638cd6
JB		 2185 return -EINVAL;
2186 }
2187
2188 if (obj->tiling_mode != I915_TILING_NONE)
2189 dspcntr |= DISPPLANE_TILED;
2190 else
2191 dspcntr &= ~DISPPLANE_TILED;
2192
2193 /* must disable */
2194 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2195
2196 I915_WRITE(reg, dspcntr);
2197
e506a0c6 2198 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2199 intel_crtc->dspaddr_offset =
5a35e99e
DL		 2200 intel_gen4_compute_offset_xtiled(&x, &y,
2201 fb->bits_per_pixel / 8,
2202 fb->pitches[0]);
c2c75131 2203 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2204
e506a0c6
DV		 2205 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2206 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2207 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2208 I915_MODIFY_DISPBASE(DSPSURF(plane),
2209 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2210 if (IS_HASWELL(dev)) {
2211 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2212 } else {
2213 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2214 I915_WRITE(DSPLINOFF(plane), linear_offset);
2215 }
17638cd6
JB		 2216 POSTING_READ(reg);
2217
2218 return 0;
2219}
2220
2221/* Assume fb object is pinned & idle & fenced and just update base pointers */
2222static int
2223intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2224 int x, int y, enum mode_set_atomic state)
2225{
2226 struct drm_device *dev = crtc->dev;
2227 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2228
6b8e6ed0
CW		 2229 if (dev_priv->display.disable_fbc)
2230 dev_priv->display.disable_fbc(dev);
3dec0095 2231 intel_increase_pllclock(crtc);
81255565 2232
6b8e6ed0 2233 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2234}
2235
14667a4b
CW		 2236static int
2237intel_finish_fb(struct drm_framebuffer *old_fb)
2238{
2239 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2240 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2241 bool was_interruptible = dev_priv->mm.interruptible;
2242 int ret;
2243
2244 wait_event(dev_priv->pending_flip_queue,
2245 atomic_read(&dev_priv->mm.wedged) ||
2246 atomic_read(&obj->pending_flip) == 0);
2247
2248 /* Big Hammer, we also need to ensure that any pending
2249 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2250 * current scanout is retired before unpinning the old
2251 * framebuffer.
2252 *
2253 * This should only fail upon a hung GPU, in which case we
2254 * can safely continue.
2255 */
2256 dev_priv->mm.interruptible = false;
2257 ret = i915_gem_object_finish_gpu(obj);
2258 dev_priv->mm.interruptible = was_interruptible;
2259
2260 return ret;
2261}
2262
198598d0
VS		 2263static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2264{
2265 struct drm_device *dev = crtc->dev;
2266 struct drm_i915_master_private *master_priv;
2267 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2268
2269 if (!dev->primary->master)
2270 return;
2271
2272 master_priv = dev->primary->master->driver_priv;
2273 if (!master_priv->sarea_priv)
2274 return;
2275
2276 switch (intel_crtc->pipe) {
2277 case 0:
2278 master_priv->sarea_priv->pipeA_x = x;
2279 master_priv->sarea_priv->pipeA_y = y;
2280 break;
2281 case 1:
2282 master_priv->sarea_priv->pipeB_x = x;
2283 master_priv->sarea_priv->pipeB_y = y;
2284 break;
2285 default:
2286 break;
2287 }
2288}
2289
5c3b82e2 2290static int
3c4fdcfb 2291intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2292 struct drm_framebuffer *fb)
79e53945
JB		 2293{
2294 struct drm_device *dev = crtc->dev;
6b8e6ed0 2295 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2296 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2297 struct drm_framebuffer *old_fb;
5c3b82e2 2298 int ret;
79e53945
JB		 2299
2300 /* no fb bound */
94352cf9 2301 if (!fb) {
a5071c2f 2302 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2303 return 0;
2304 }
2305
5826eca5
ED		 2306 if(intel_crtc->plane > dev_priv->num_pipe) {
2307 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2308 intel_crtc->plane,
2309 dev_priv->num_pipe);
5c3b82e2 2310 return -EINVAL;
79e53945
JB		 2311 }
2312
5c3b82e2 2313 mutex_lock(&dev->struct_mutex);
265db958 2314 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2315 to_intel_framebuffer(fb)->obj,
919926ae 2316 NULL);
5c3b82e2
CW		 2317 if (ret != 0) {
2318 mutex_unlock(&dev->struct_mutex);
a5071c2f 2319 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2320 return ret;
2321 }
79e53945 2322
94352cf9
DV		 2323 if (crtc->fb)
2324 intel_finish_fb(crtc->fb);
265db958 2325
94352cf9 2326 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2327 if (ret) {
94352cf9 2328 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2329 mutex_unlock(&dev->struct_mutex);
a5071c2f 2330 DRM_ERROR("failed to update base address\n");
4e6cfefc 2331 return ret;
79e53945 2332 }
3c4fdcfb 2333
94352cf9
DV		 2334 old_fb = crtc->fb;
2335 crtc->fb = fb;
6c4c86f5
DV		 2336 crtc->x = x;
2337 crtc->y = y;
94352cf9 2338
b7f1de28
CW		 2339 if (old_fb) {
2340 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2341 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2342 }
652c393a 2343
6b8e6ed0 2344 intel_update_fbc(dev);
5c3b82e2 2345 mutex_unlock(&dev->struct_mutex);
79e53945 2346
198598d0 2347 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2348
2349 return 0;
79e53945
JB		 2350}
2351
5eddb70b 2352static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2353{
2354 struct drm_device *dev = crtc->dev;
2355 struct drm_i915_private *dev_priv = dev->dev_private;
2356 u32 dpa_ctl;
2357
28c97730 2358 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2359 dpa_ctl = I915_READ(DP_A);
2360 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2361
2362 if (clock < 200000) {
2363 u32 temp;
2364 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2365 /* workaround for 160Mhz:
2366 1) program 0x4600c bits 15:0 = 0x8124
2367 2) program 0x46010 bit 0 = 1
2368 3) program 0x46034 bit 24 = 1
2369 4) program 0x64000 bit 14 = 1
2370 */
2371 temp = I915_READ(0x4600c);
2372 temp &= 0xffff0000;
2373 I915_WRITE(0x4600c, temp | 0x8124);
2374
2375 temp = I915_READ(0x46010);
2376 I915_WRITE(0x46010, temp | 1);
2377
2378 temp = I915_READ(0x46034);
2379 I915_WRITE(0x46034, temp | (1 << 24));
2380 } else {
2381 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2382 }
2383 I915_WRITE(DP_A, dpa_ctl);
2384
5eddb70b 2385 POSTING_READ(DP_A);
32f9d658
ZW		 2386 udelay(500);
2387}
2388
5e84e1a4
ZW		 2389static void intel_fdi_normal_train(struct drm_crtc *crtc)
2390{
2391 struct drm_device *dev = crtc->dev;
2392 struct drm_i915_private *dev_priv = dev->dev_private;
2393 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2394 int pipe = intel_crtc->pipe;
2395 u32 reg, temp;
2396
2397 /* enable normal train */
2398 reg = FDI_TX_CTL(pipe);
2399 temp = I915_READ(reg);
61e499bf 2400 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2401 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2402 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2403 } else {
2404 temp &= ~FDI_LINK_TRAIN_NONE;
2405 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2406 }
5e84e1a4
ZW		 2407 I915_WRITE(reg, temp);
2408
2409 reg = FDI_RX_CTL(pipe);
2410 temp = I915_READ(reg);
2411 if (HAS_PCH_CPT(dev)) {
2412 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2413 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2414 } else {
2415 temp &= ~FDI_LINK_TRAIN_NONE;
2416 temp |= FDI_LINK_TRAIN_NONE;
2417 }
2418 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2419
2420 /* wait one idle pattern time */
2421 POSTING_READ(reg);
2422 udelay(1000);
357555c0
JB		 2423
2424 /* IVB wants error correction enabled */
2425 if (IS_IVYBRIDGE(dev))
2426 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2427 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2428}
2429
291427f5
JB		 2430static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2431{
2432 struct drm_i915_private *dev_priv = dev->dev_private;
2433 u32 flags = I915_READ(SOUTH_CHICKEN1);
2434
2435 flags |= FDI_PHASE_SYNC_OVR(pipe);
2436 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2437 flags |= FDI_PHASE_SYNC_EN(pipe);
2438 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2439 POSTING_READ(SOUTH_CHICKEN1);
2440}
2441
01a415fd
DV		 2442static void ivb_modeset_global_resources(struct drm_device *dev)
2443{
2444 struct drm_i915_private *dev_priv = dev->dev_private;
2445 struct intel_crtc *pipe_B_crtc =
2446 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2447 struct intel_crtc *pipe_C_crtc =
2448 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2449 uint32_t temp;
2450
2451 /* When everything is off disable fdi C so that we could enable fdi B
2452 * with all lanes. XXX: This misses the case where a pipe is not using
2453 * any pch resources and so doesn't need any fdi lanes. */
2454 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2455 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2456 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2457
2458 temp = I915_READ(SOUTH_CHICKEN1);
2459 temp &= ~FDI_BC_BIFURCATION_SELECT;
2460 DRM_DEBUG_KMS("disabling fdi C rx\n");
2461 I915_WRITE(SOUTH_CHICKEN1, temp);
2462 }
2463}
2464
8db9d77b
ZW		 2465/* The FDI link training functions for ILK/Ibexpeak. */
2466static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2467{
2468 struct drm_device *dev = crtc->dev;
2469 struct drm_i915_private *dev_priv = dev->dev_private;
2470 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2471 int pipe = intel_crtc->pipe;
0fc932b8 2472 int plane = intel_crtc->plane;
5eddb70b 2473 u32 reg, temp, tries;
8db9d77b 2474
0fc932b8
JB		 2475 /* FDI needs bits from pipe & plane first */
2476 assert_pipe_enabled(dev_priv, pipe);
2477 assert_plane_enabled(dev_priv, plane);
2478
e1a44743
AJ		 2479 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2480 for train result */
5eddb70b
CW		 2481 reg = FDI_RX_IMR(pipe);
2482 temp = I915_READ(reg);
e1a44743
AJ		 2483 temp &= ~FDI_RX_SYMBOL_LOCK;
2484 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2485 I915_WRITE(reg, temp);
2486 I915_READ(reg);
e1a44743
AJ		 2487 udelay(150);
2488
8db9d77b 2489 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2490 reg = FDI_TX_CTL(pipe);
2491 temp = I915_READ(reg);
77ffb597
AJ		 2492 temp &= ~(7 << 19);
2493 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2494 temp &= ~FDI_LINK_TRAIN_NONE;
2495 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2496 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2497
5eddb70b
CW		 2498 reg = FDI_RX_CTL(pipe);
2499 temp = I915_READ(reg);
8db9d77b
ZW		 2500 temp &= ~FDI_LINK_TRAIN_NONE;
2501 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2502 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2503
2504 POSTING_READ(reg);
8db9d77b
ZW		 2505 udelay(150);
2506
5b2adf89 2507 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2508 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2509 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2510 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2511
5eddb70b 2512 reg = FDI_RX_IIR(pipe);
e1a44743 2513 for (tries = 0; tries < 5; tries++) {
5eddb70b 2514 temp = I915_READ(reg);
8db9d77b
ZW		 2515 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2516
2517 if ((temp & FDI_RX_BIT_LOCK)) {
2518 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2519 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2520 break;
2521 }
8db9d77b 2522 }
e1a44743 2523 if (tries == 5)
5eddb70b 2524 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2525
2526 /* Train 2 */
5eddb70b
CW		 2527 reg = FDI_TX_CTL(pipe);
2528 temp = I915_READ(reg);
8db9d77b
ZW		 2529 temp &= ~FDI_LINK_TRAIN_NONE;
2530 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2531 I915_WRITE(reg, temp);
8db9d77b 2532
5eddb70b
CW		 2533 reg = FDI_RX_CTL(pipe);
2534 temp = I915_READ(reg);
8db9d77b
ZW		 2535 temp &= ~FDI_LINK_TRAIN_NONE;
2536 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2537 I915_WRITE(reg, temp);
8db9d77b 2538
5eddb70b
CW		 2539 POSTING_READ(reg);
2540 udelay(150);
8db9d77b 2541
5eddb70b 2542 reg = FDI_RX_IIR(pipe);
e1a44743 2543 for (tries = 0; tries < 5; tries++) {
5eddb70b 2544 temp = I915_READ(reg);
8db9d77b
ZW		 2545 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2546
2547 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2548 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2549 DRM_DEBUG_KMS("FDI train 2 done.\n");
2550 break;
2551 }
8db9d77b 2552 }
e1a44743 2553 if (tries == 5)
5eddb70b 2554 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2555
2556 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2557
8db9d77b
ZW		 2558}
2559
0206e353 2560static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2561 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2562 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2563 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2564 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2565};
2566
2567/* The FDI link training functions for SNB/Cougarpoint. */
2568static void gen6_fdi_link_train(struct drm_crtc *crtc)
2569{
2570 struct drm_device *dev = crtc->dev;
2571 struct drm_i915_private *dev_priv = dev->dev_private;
2572 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2573 int pipe = intel_crtc->pipe;
fa37d39e 2574 u32 reg, temp, i, retry;
8db9d77b 2575
e1a44743
AJ		 2576 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2577 for train result */
5eddb70b
CW		 2578 reg = FDI_RX_IMR(pipe);
2579 temp = I915_READ(reg);
e1a44743
AJ		 2580 temp &= ~FDI_RX_SYMBOL_LOCK;
2581 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2582 I915_WRITE(reg, temp);
2583
2584 POSTING_READ(reg);
e1a44743
AJ		 2585 udelay(150);
2586
8db9d77b 2587 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2588 reg = FDI_TX_CTL(pipe);
2589 temp = I915_READ(reg);
77ffb597
AJ		 2590 temp &= ~(7 << 19);
2591 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2592 temp &= ~FDI_LINK_TRAIN_NONE;
2593 temp |= FDI_LINK_TRAIN_PATTERN_1;
2594 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2595 /* SNB-B */
2596 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2597 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2598
d74cf324
DV		 2599 I915_WRITE(FDI_RX_MISC(pipe),
2600 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2601
5eddb70b
CW		 2602 reg = FDI_RX_CTL(pipe);
2603 temp = I915_READ(reg);
8db9d77b
ZW		 2604 if (HAS_PCH_CPT(dev)) {
2605 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2606 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2607 } else {
2608 temp &= ~FDI_LINK_TRAIN_NONE;
2609 temp |= FDI_LINK_TRAIN_PATTERN_1;
2610 }
5eddb70b
CW		 2611 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2612
2613 POSTING_READ(reg);
8db9d77b
ZW		 2614 udelay(150);
2615
8f5718a6 2616 cpt_phase_pointer_enable(dev, pipe);
291427f5 2617
0206e353 2618 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2619 reg = FDI_TX_CTL(pipe);
2620 temp = I915_READ(reg);
8db9d77b
ZW		 2621 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2622 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2623 I915_WRITE(reg, temp);
2624
2625 POSTING_READ(reg);
8db9d77b
ZW		 2626 udelay(500);
2627
fa37d39e
SP		 2628 for (retry = 0; retry < 5; retry++) {
2629 reg = FDI_RX_IIR(pipe);
2630 temp = I915_READ(reg);
2631 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2632 if (temp & FDI_RX_BIT_LOCK) {
2633 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2634 DRM_DEBUG_KMS("FDI train 1 done.\n");
2635 break;
2636 }
2637 udelay(50);
8db9d77b 2638 }
fa37d39e
SP		 2639 if (retry < 5)
2640 break;
8db9d77b
ZW		 2641 }
2642 if (i == 4)
5eddb70b 2643 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2644
2645 /* Train 2 */
5eddb70b
CW		 2646 reg = FDI_TX_CTL(pipe);
2647 temp = I915_READ(reg);
8db9d77b
ZW		 2648 temp &= ~FDI_LINK_TRAIN_NONE;
2649 temp |= FDI_LINK_TRAIN_PATTERN_2;
2650 if (IS_GEN6(dev)) {
2651 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2652 /* SNB-B */
2653 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2654 }
5eddb70b 2655 I915_WRITE(reg, temp);
8db9d77b 2656
5eddb70b
CW		 2657 reg = FDI_RX_CTL(pipe);
2658 temp = I915_READ(reg);
8db9d77b
ZW		 2659 if (HAS_PCH_CPT(dev)) {
2660 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2661 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2662 } else {
2663 temp &= ~FDI_LINK_TRAIN_NONE;
2664 temp |= FDI_LINK_TRAIN_PATTERN_2;
2665 }
5eddb70b
CW		 2666 I915_WRITE(reg, temp);
2667
2668 POSTING_READ(reg);
8db9d77b
ZW		 2669 udelay(150);
2670
0206e353 2671 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2672 reg = FDI_TX_CTL(pipe);
2673 temp = I915_READ(reg);
8db9d77b
ZW		 2674 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2675 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2676 I915_WRITE(reg, temp);
2677
2678 POSTING_READ(reg);
8db9d77b
ZW		 2679 udelay(500);
2680
fa37d39e
SP		 2681 for (retry = 0; retry < 5; retry++) {
2682 reg = FDI_RX_IIR(pipe);
2683 temp = I915_READ(reg);
2684 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2685 if (temp & FDI_RX_SYMBOL_LOCK) {
2686 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2687 DRM_DEBUG_KMS("FDI train 2 done.\n");
2688 break;
2689 }
2690 udelay(50);
8db9d77b 2691 }
fa37d39e
SP		 2692 if (retry < 5)
2693 break;
8db9d77b
ZW		 2694 }
2695 if (i == 4)
5eddb70b 2696 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2697
2698 DRM_DEBUG_KMS("FDI train done.\n");
2699}
2700
357555c0
JB		 2701/* Manual link training for Ivy Bridge A0 parts */
2702static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2703{
2704 struct drm_device *dev = crtc->dev;
2705 struct drm_i915_private *dev_priv = dev->dev_private;
2706 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2707 int pipe = intel_crtc->pipe;
2708 u32 reg, temp, i;
2709
2710 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2711 for train result */
2712 reg = FDI_RX_IMR(pipe);
2713 temp = I915_READ(reg);
2714 temp &= ~FDI_RX_SYMBOL_LOCK;
2715 temp &= ~FDI_RX_BIT_LOCK;
2716 I915_WRITE(reg, temp);
2717
2718 POSTING_READ(reg);
2719 udelay(150);
2720
01a415fd
DV		 2721 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2722 I915_READ(FDI_RX_IIR(pipe)));
2723
357555c0
JB		 2724 /* enable CPU FDI TX and PCH FDI RX */
2725 reg = FDI_TX_CTL(pipe);
2726 temp = I915_READ(reg);
2727 temp &= ~(7 << 19);
2728 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2729 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2730 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2731 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2732 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2733 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2734 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2735
d74cf324
DV		 2736 I915_WRITE(FDI_RX_MISC(pipe),
2737 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2738
357555c0
JB		 2739 reg = FDI_RX_CTL(pipe);
2740 temp = I915_READ(reg);
2741 temp &= ~FDI_LINK_TRAIN_AUTO;
2742 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2743 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2744 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2745 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2746
2747 POSTING_READ(reg);
2748 udelay(150);
2749
8f5718a6 2750 cpt_phase_pointer_enable(dev, pipe);
291427f5 2751
0206e353 2752 for (i = 0; i < 4; i++) {
357555c0
JB		 2753 reg = FDI_TX_CTL(pipe);
2754 temp = I915_READ(reg);
2755 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2756 temp |= snb_b_fdi_train_param[i];
2757 I915_WRITE(reg, temp);
2758
2759 POSTING_READ(reg);
2760 udelay(500);
2761
2762 reg = FDI_RX_IIR(pipe);
2763 temp = I915_READ(reg);
2764 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2765
2766 if (temp & FDI_RX_BIT_LOCK ||
2767 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2768 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2769 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2770 break;
2771 }
2772 }
2773 if (i == 4)
2774 DRM_ERROR("FDI train 1 fail!\n");
2775
2776 /* Train 2 */
2777 reg = FDI_TX_CTL(pipe);
2778 temp = I915_READ(reg);
2779 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2780 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2781 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2782 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2783 I915_WRITE(reg, temp);
2784
2785 reg = FDI_RX_CTL(pipe);
2786 temp = I915_READ(reg);
2787 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2788 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2789 I915_WRITE(reg, temp);
2790
2791 POSTING_READ(reg);
2792 udelay(150);
2793
0206e353 2794 for (i = 0; i < 4; i++) {
357555c0
JB		 2795 reg = FDI_TX_CTL(pipe);
2796 temp = I915_READ(reg);
2797 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2798 temp |= snb_b_fdi_train_param[i];
2799 I915_WRITE(reg, temp);
2800
2801 POSTING_READ(reg);
2802 udelay(500);
2803
2804 reg = FDI_RX_IIR(pipe);
2805 temp = I915_READ(reg);
2806 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2807
2808 if (temp & FDI_RX_SYMBOL_LOCK) {
2809 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2810 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2811 break;
2812 }
2813 }
2814 if (i == 4)
2815 DRM_ERROR("FDI train 2 fail!\n");
2816
2817 DRM_DEBUG_KMS("FDI train done.\n");
2818}
2819
88cefb6c 2820static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2821{
88cefb6c 2822 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2823 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2824 int pipe = intel_crtc->pipe;
5eddb70b 2825 u32 reg, temp;
79e53945 2826
c64e311e 2827
c98e9dcf 2828 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2829 reg = FDI_RX_CTL(pipe);
2830 temp = I915_READ(reg);
2831 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2832 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2833 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2834 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2835
2836 POSTING_READ(reg);
c98e9dcf
JB		 2837 udelay(200);
2838
2839 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2840 temp = I915_READ(reg);
2841 I915_WRITE(reg, temp | FDI_PCDCLK);
2842
2843 POSTING_READ(reg);
c98e9dcf
JB		 2844 udelay(200);
2845
bf507ef7
ED		 2846 /* On Haswell, the PLL configuration for ports and pipes is handled
2847 * separately, as part of DDI setup */
2848 if (!IS_HASWELL(dev)) {
2849 /* Enable CPU FDI TX PLL, always on for Ironlake */
2850 reg = FDI_TX_CTL(pipe);
2851 temp = I915_READ(reg);
2852 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2853 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2854
bf507ef7
ED		 2855 POSTING_READ(reg);
2856 udelay(100);
2857 }
6be4a607 2858 }
0e23b99d
JB		 2859}
2860
88cefb6c
DV		 2861static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2862{
2863 struct drm_device *dev = intel_crtc->base.dev;
2864 struct drm_i915_private *dev_priv = dev->dev_private;
2865 int pipe = intel_crtc->pipe;
2866 u32 reg, temp;
2867
2868 /* Switch from PCDclk to Rawclk */
2869 reg = FDI_RX_CTL(pipe);
2870 temp = I915_READ(reg);
2871 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2872
2873 /* Disable CPU FDI TX PLL */
2874 reg = FDI_TX_CTL(pipe);
2875 temp = I915_READ(reg);
2876 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2877
2878 POSTING_READ(reg);
2879 udelay(100);
2880
2881 reg = FDI_RX_CTL(pipe);
2882 temp = I915_READ(reg);
2883 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2884
2885 /* Wait for the clocks to turn off. */
2886 POSTING_READ(reg);
2887 udelay(100);
2888}
2889
291427f5
JB		 2890static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2891{
2892 struct drm_i915_private *dev_priv = dev->dev_private;
2893 u32 flags = I915_READ(SOUTH_CHICKEN1);
2894
2895 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2896 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2897 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2898 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2899 POSTING_READ(SOUTH_CHICKEN1);
2900}
0fc932b8
JB		 2901static void ironlake_fdi_disable(struct drm_crtc *crtc)
2902{
2903 struct drm_device *dev = crtc->dev;
2904 struct drm_i915_private *dev_priv = dev->dev_private;
2905 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2906 int pipe = intel_crtc->pipe;
2907 u32 reg, temp;
2908
2909 /* disable CPU FDI tx and PCH FDI rx */
2910 reg = FDI_TX_CTL(pipe);
2911 temp = I915_READ(reg);
2912 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2913 POSTING_READ(reg);
2914
2915 reg = FDI_RX_CTL(pipe);
2916 temp = I915_READ(reg);
2917 temp &= ~(0x7 << 16);
2918 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2919 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2920
2921 POSTING_READ(reg);
2922 udelay(100);
2923
2924 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2925 if (HAS_PCH_IBX(dev)) {
2926 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2927 I915_WRITE(FDI_RX_CHICKEN(pipe),
2928 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18 2929 ~FDI_RX_PHASE_SYNC_POINTER_EN));
291427f5
JB		 2930 } else if (HAS_PCH_CPT(dev)) {
2931 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2932 }
0fc932b8
JB		 2933
2934 /* still set train pattern 1 */
2935 reg = FDI_TX_CTL(pipe);
2936 temp = I915_READ(reg);
2937 temp &= ~FDI_LINK_TRAIN_NONE;
2938 temp |= FDI_LINK_TRAIN_PATTERN_1;
2939 I915_WRITE(reg, temp);
2940
2941 reg = FDI_RX_CTL(pipe);
2942 temp = I915_READ(reg);
2943 if (HAS_PCH_CPT(dev)) {
2944 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2945 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2946 } else {
2947 temp &= ~FDI_LINK_TRAIN_NONE;
2948 temp |= FDI_LINK_TRAIN_PATTERN_1;
2949 }
2950 /* BPC in FDI rx is consistent with that in PIPECONF */
2951 temp &= ~(0x07 << 16);
2952 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2953 I915_WRITE(reg, temp);
2954
2955 POSTING_READ(reg);
2956 udelay(100);
2957}
2958
5bb61643
CW		 2959static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2960{
2961 struct drm_device *dev = crtc->dev;
2962 struct drm_i915_private *dev_priv = dev->dev_private;
2963 unsigned long flags;
2964 bool pending;
2965
2966 if (atomic_read(&dev_priv->mm.wedged))
2967 return false;
2968
2969 spin_lock_irqsave(&dev->event_lock, flags);
2970 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2971 spin_unlock_irqrestore(&dev->event_lock, flags);
2972
2973 return pending;
2974}
2975
e6c3a2a6
CW		 2976static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2977{
0f91128d 2978 struct drm_device *dev = crtc->dev;
5bb61643 2979 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2980
2981 if (crtc->fb == NULL)
2982 return;
2983
5bb61643
CW		 2984 wait_event(dev_priv->pending_flip_queue,
2985 !intel_crtc_has_pending_flip(crtc));
2986
0f91128d
CW		 2987 mutex_lock(&dev->struct_mutex);
2988 intel_finish_fb(crtc->fb);
2989 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2990}
2991
fc316cbe 2992static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
040484af
JB		 2993{
2994 struct drm_device *dev = crtc->dev;
228d3e36 2995 struct intel_encoder *intel_encoder;
040484af
JB		 2996
2997 /*
2998 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2999 * must be driven by its own crtc; no sharing is possible.
3000 */
228d3e36 3001 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
228d3e36 3002 switch (intel_encoder->type) {
040484af 3003 case INTEL_OUTPUT_EDP:
228d3e36 3004 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
040484af
JB		 3005 return false;
3006 continue;
3007 }
3008 }
3009
3010 return true;
3011}
3012
fc316cbe
PZ		 3013static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
3014{
3015 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
3016}
3017
e615efe4
ED		 3018/* Program iCLKIP clock to the desired frequency */
3019static void lpt_program_iclkip(struct drm_crtc *crtc)
3020{
3021 struct drm_device *dev = crtc->dev;
3022 struct drm_i915_private *dev_priv = dev->dev_private;
3023 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3024 u32 temp;
3025
3026 /* It is necessary to ungate the pixclk gate prior to programming
3027 * the divisors, and gate it back when it is done.
3028 */
3029 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3030
3031 /* Disable SSCCTL */
3032 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3033 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
3034 SBI_SSCCTL_DISABLE);
3035
3036 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3037 if (crtc->mode.clock == 20000) {
3038 auxdiv = 1;
3039 divsel = 0x41;
3040 phaseinc = 0x20;
3041 } else {
3042 /* The iCLK virtual clock root frequency is in MHz,
3043 * but the crtc->mode.clock in in KHz. To get the divisors,
3044 * it is necessary to divide one by another, so we
3045 * convert the virtual clock precision to KHz here for higher
3046 * precision.
3047 */
3048 u32 iclk_virtual_root_freq = 172800 * 1000;
3049 u32 iclk_pi_range = 64;
3050 u32 desired_divisor, msb_divisor_value, pi_value;
3051
3052 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3053 msb_divisor_value = desired_divisor / iclk_pi_range;
3054 pi_value = desired_divisor % iclk_pi_range;
3055
3056 auxdiv = 0;
3057 divsel = msb_divisor_value - 2;
3058 phaseinc = pi_value;
3059 }
3060
3061 /* This should not happen with any sane values */
3062 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3063 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3064 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3065 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3066
3067 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3068 crtc->mode.clock,
3069 auxdiv,
3070 divsel,
3071 phasedir,
3072 phaseinc);
3073
3074 /* Program SSCDIVINTPHASE6 */
3075 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
3076 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3077 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3078 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3079 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3080 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3081 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3082
3083 intel_sbi_write(dev_priv,
3084 SBI_SSCDIVINTPHASE6,
3085 temp);
3086
3087 /* Program SSCAUXDIV */
3088 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
3089 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3090 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3091 intel_sbi_write(dev_priv,
3092 SBI_SSCAUXDIV6,
3093 temp);
3094
3095
3096 /* Enable modulator and associated divider */
3097 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
3098 temp &= ~SBI_SSCCTL_DISABLE;
3099 intel_sbi_write(dev_priv,
3100 SBI_SSCCTL6,
3101 temp);
3102
3103 /* Wait for initialization time */
3104 udelay(24);
3105
3106 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3107}
3108
f67a559d
JB		 3109/*
3110 * Enable PCH resources required for PCH ports:
3111 * - PCH PLLs
3112 * - FDI training & RX/TX
3113 * - update transcoder timings
3114 * - DP transcoding bits
3115 * - transcoder
3116 */
3117static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3118{
3119 struct drm_device *dev = crtc->dev;
3120 struct drm_i915_private *dev_priv = dev->dev_private;
3121 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3122 int pipe = intel_crtc->pipe;
ee7b9f93 3123 u32 reg, temp;
2c07245f 3124
e7e164db
CW		 3125 assert_transcoder_disabled(dev_priv, pipe);
3126
cd986abb
DV		 3127 /* Write the TU size bits before fdi link training, so that error
3128 * detection works. */
3129 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3130 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3131
c98e9dcf 3132 /* For PCH output, training FDI link */
674cf967 3133 dev_priv->display.fdi_link_train(crtc);
2c07245f 3134
572deb37
DV		 3135 /* XXX: pch pll's can be enabled any time before we enable the PCH
3136 * transcoder, and we actually should do this to not upset any PCH
3137 * transcoder that already use the clock when we share it.
3138 *
3139 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3140 * unconditionally resets the pll - we need that to have the right LVDS
3141 * enable sequence. */
b6b4e185 3142 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 3143
303b81e0 3144 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3145 u32 sel;
4b645f14 3146
c98e9dcf 3147 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3148 switch (pipe) {
3149 default:
3150 case 0:
3151 temp |= TRANSA_DPLL_ENABLE;
3152 sel = TRANSA_DPLLB_SEL;
3153 break;
3154 case 1:
3155 temp |= TRANSB_DPLL_ENABLE;
3156 sel = TRANSB_DPLLB_SEL;
3157 break;
3158 case 2:
3159 temp |= TRANSC_DPLL_ENABLE;
3160 sel = TRANSC_DPLLB_SEL;
3161 break;
d64311ab 3162 }
ee7b9f93
JB		 3163 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3164 temp |= sel;
3165 else
3166 temp &= ~sel;
c98e9dcf 3167 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3168 }
5eddb70b 3169
d9b6cb56
JB		 3170 /* set transcoder timing, panel must allow it */
3171 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3172 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3173 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3174 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3175
5eddb70b
CW		 3176 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3177 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3178 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3179 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3180
303b81e0 3181 intel_fdi_normal_train(crtc);
5e84e1a4 3182
c98e9dcf
JB		 3183 /* For PCH DP, enable TRANS_DP_CTL */
3184 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3185 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3186 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 3187 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 3188 reg = TRANS_DP_CTL(pipe);
3189 temp = I915_READ(reg);
3190 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3191 TRANS_DP_SYNC_MASK |
3192 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3193 temp |= (TRANS_DP_OUTPUT_ENABLE |
3194 TRANS_DP_ENH_FRAMING);
9325c9f0 3195 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3196
3197 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3198 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3199 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3200 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3201
3202 switch (intel_trans_dp_port_sel(crtc)) {
3203 case PCH_DP_B:
5eddb70b 3204 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3205 break;
3206 case PCH_DP_C:
5eddb70b 3207 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3208 break;
3209 case PCH_DP_D:
5eddb70b 3210 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3211 break;
3212 default:
e95d41e1 3213 BUG();
32f9d658 3214 }
2c07245f 3215
5eddb70b 3216 I915_WRITE(reg, temp);
6be4a607 3217 }
b52eb4dc 3218
b8a4f404 3219 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3220}
3221
1507e5bd
PZ		 3222static void lpt_pch_enable(struct drm_crtc *crtc)
3223{
3224 struct drm_device *dev = crtc->dev;
3225 struct drm_i915_private *dev_priv = dev->dev_private;
3226 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
daed2dbb 3227 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
1507e5bd 3228
daed2dbb 3229 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3230
8c52b5e8 3231 lpt_program_iclkip(crtc);
1507e5bd 3232
0540e488 3233 /* Set transcoder timing. */
daed2dbb
PZ		 3234 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3235 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3236 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
1507e5bd 3237
daed2dbb
PZ		 3238 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3239 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3240 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3241 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
1507e5bd 3242
937bb610 3243 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
1507e5bd
PZ		 3244}
3245
ee7b9f93
JB		 3246static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3247{
3248 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3249
3250 if (pll == NULL)
3251 return;
3252
3253 if (pll->refcount == 0) {
3254 WARN(1, "bad PCH PLL refcount\n");
3255 return;
3256 }
3257
3258 --pll->refcount;
3259 intel_crtc->pch_pll = NULL;
3260}
3261
3262static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3263{
3264 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3265 struct intel_pch_pll *pll;
3266 int i;
3267
3268 pll = intel_crtc->pch_pll;
3269 if (pll) {
3270 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3271 intel_crtc->base.base.id, pll->pll_reg);
3272 goto prepare;
3273 }
3274
98b6bd99
DV		 3275 if (HAS_PCH_IBX(dev_priv->dev)) {
3276 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3277 i = intel_crtc->pipe;
3278 pll = &dev_priv->pch_plls[i];
3279
3280 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3281 intel_crtc->base.base.id, pll->pll_reg);
3282
3283 goto found;
3284 }
3285
ee7b9f93
JB		 3286 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3287 pll = &dev_priv->pch_plls[i];
3288
3289 /* Only want to check enabled timings first */
3290 if (pll->refcount == 0)
3291 continue;
3292
3293 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3294 fp == I915_READ(pll->fp0_reg)) {
3295 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3296 intel_crtc->base.base.id,
3297 pll->pll_reg, pll->refcount, pll->active);
3298
3299 goto found;
3300 }
3301 }
3302
3303 /* Ok no matching timings, maybe there's a free one? */
3304 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3305 pll = &dev_priv->pch_plls[i];
3306 if (pll->refcount == 0) {
3307 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3308 intel_crtc->base.base.id, pll->pll_reg);
3309 goto found;
3310 }
3311 }
3312
3313 return NULL;
3314
3315found:
3316 intel_crtc->pch_pll = pll;
3317 pll->refcount++;
3318 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3319prepare: /* separate function? */
3320 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3321
e04c7350
CW		 3322 /* Wait for the clocks to stabilize before rewriting the regs */
3323 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3324 POSTING_READ(pll->pll_reg);
3325 udelay(150);
e04c7350
CW		 3326
3327 I915_WRITE(pll->fp0_reg, fp);
3328 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3329 pll->on = false;
3330 return pll;
3331}
3332
d4270e57
JB		 3333void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3334{
3335 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3336 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3337 u32 temp;
3338
3339 temp = I915_READ(dslreg);
3340 udelay(500);
3341 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57
JB		 3342 if (wait_for(I915_READ(dslreg) != temp, 5))
3343 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3344 }
3345}
3346
f67a559d
JB		 3347static void ironlake_crtc_enable(struct drm_crtc *crtc)
3348{
3349 struct drm_device *dev = crtc->dev;
3350 struct drm_i915_private *dev_priv = dev->dev_private;
3351 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3352 struct intel_encoder *encoder;
f67a559d
JB		 3353 int pipe = intel_crtc->pipe;
3354 int plane = intel_crtc->plane;
3355 u32 temp;
3356 bool is_pch_port;
3357
08a48469
DV		 3358 WARN_ON(!crtc->enabled);
3359
f67a559d
JB		 3360 if (intel_crtc->active)
3361 return;
3362
3363 intel_crtc->active = true;
3364 intel_update_watermarks(dev);
3365
3366 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3367 temp = I915_READ(PCH_LVDS);
3368 if ((temp & LVDS_PORT_EN) == 0)
3369 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3370 }
3371
fc316cbe 3372 is_pch_port = ironlake_crtc_driving_pch(crtc);
f67a559d 3373
46b6f814 3374 if (is_pch_port) {
fff367c7
DV		 3375 /* Note: FDI PLL enabling _must_ be done before we enable the
3376 * cpu pipes, hence this is separate from all the other fdi/pch
3377 * enabling. */
88cefb6c 3378 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3379 } else {
3380 assert_fdi_tx_disabled(dev_priv, pipe);
3381 assert_fdi_rx_disabled(dev_priv, pipe);
3382 }
f67a559d 3383
bf49ec8c
DV		 3384 for_each_encoder_on_crtc(dev, crtc, encoder)
3385 if (encoder->pre_enable)
3386 encoder->pre_enable(encoder);
3387
f67a559d
JB		 3388 /* Enable panel fitting for LVDS */
3389 if (dev_priv->pch_pf_size &&
547dc041
JN		 3390 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3391 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
f67a559d
JB		 3392 /* Force use of hard-coded filter coefficients
3393 * as some pre-programmed values are broken,
3394 * e.g. x201.
3395 */
9db4a9c7
JB		 3396 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3397 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3398 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3399 }
3400
9c54c0dd
JB		 3401 /*
3402 * On ILK+ LUT must be loaded before the pipe is running but with
3403 * clocks enabled
3404 */
3405 intel_crtc_load_lut(crtc);
3406
f67a559d
JB		 3407 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3408 intel_enable_plane(dev_priv, plane, pipe);
3409
3410 if (is_pch_port)
3411 ironlake_pch_enable(crtc);
c98e9dcf 3412
d1ebd816 3413 mutex_lock(&dev->struct_mutex);
bed4a673 3414 intel_update_fbc(dev);
d1ebd816
BW		 3415 mutex_unlock(&dev->struct_mutex);
3416
6b383a7f 3417 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3418
fa5c73b1
DV		 3419 for_each_encoder_on_crtc(dev, crtc, encoder)
3420 encoder->enable(encoder);
61b77ddd
DV		 3421
3422 if (HAS_PCH_CPT(dev))
3423 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3424
3425 /*
3426 * There seems to be a race in PCH platform hw (at least on some
3427 * outputs) where an enabled pipe still completes any pageflip right
3428 * away (as if the pipe is off) instead of waiting for vblank. As soon
3429 * as the first vblank happend, everything works as expected. Hence just
3430 * wait for one vblank before returning to avoid strange things
3431 * happening.
3432 */
3433 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3434}
3435
4f771f10
PZ		 3436static void haswell_crtc_enable(struct drm_crtc *crtc)
3437{
3438 struct drm_device *dev = crtc->dev;
3439 struct drm_i915_private *dev_priv = dev->dev_private;
3440 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3441 struct intel_encoder *encoder;
3442 int pipe = intel_crtc->pipe;
3443 int plane = intel_crtc->plane;
4f771f10
PZ		 3444 bool is_pch_port;
3445
3446 WARN_ON(!crtc->enabled);
3447
3448 if (intel_crtc->active)
3449 return;
3450
3451 intel_crtc->active = true;
3452 intel_update_watermarks(dev);
3453
fc316cbe 3454 is_pch_port = haswell_crtc_driving_pch(crtc);
4f771f10 3455
83616634 3456 if (is_pch_port)
04945641 3457 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3458
3459 for_each_encoder_on_crtc(dev, crtc, encoder)
3460 if (encoder->pre_enable)
3461 encoder->pre_enable(encoder);
3462
1f544388 3463 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3464
1f544388 3465 /* Enable panel fitting for eDP */
547dc041
JN		 3466 if (dev_priv->pch_pf_size &&
3467 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4f771f10
PZ		 3468 /* Force use of hard-coded filter coefficients
3469 * as some pre-programmed values are broken,
3470 * e.g. x201.
3471 */
3472 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3473 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3474 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3475 }
3476
3477 /*
3478 * On ILK+ LUT must be loaded before the pipe is running but with
3479 * clocks enabled
3480 */
3481 intel_crtc_load_lut(crtc);
3482
1f544388
PZ		 3483 intel_ddi_set_pipe_settings(crtc);
3484 intel_ddi_enable_pipe_func(crtc);
4f771f10
PZ		 3485
3486 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3487 intel_enable_plane(dev_priv, plane, pipe);
3488
3489 if (is_pch_port)
1507e5bd 3490 lpt_pch_enable(crtc);
4f771f10
PZ		 3491
3492 mutex_lock(&dev->struct_mutex);
3493 intel_update_fbc(dev);
3494 mutex_unlock(&dev->struct_mutex);
3495
3496 intel_crtc_update_cursor(crtc, true);
3497
3498 for_each_encoder_on_crtc(dev, crtc, encoder)
3499 encoder->enable(encoder);
3500
4f771f10
PZ		 3501 /*
3502 * There seems to be a race in PCH platform hw (at least on some
3503 * outputs) where an enabled pipe still completes any pageflip right
3504 * away (as if the pipe is off) instead of waiting for vblank. As soon
3505 * as the first vblank happend, everything works as expected. Hence just
3506 * wait for one vblank before returning to avoid strange things
3507 * happening.
3508 */
3509 intel_wait_for_vblank(dev, intel_crtc->pipe);
3510}
3511
6be4a607
JB		 3512static void ironlake_crtc_disable(struct drm_crtc *crtc)
3513{
3514 struct drm_device *dev = crtc->dev;
3515 struct drm_i915_private *dev_priv = dev->dev_private;
3516 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3517 struct intel_encoder *encoder;
6be4a607
JB		 3518 int pipe = intel_crtc->pipe;
3519 int plane = intel_crtc->plane;
5eddb70b 3520 u32 reg, temp;
b52eb4dc 3521
ef9c3aee 3522
f7abfe8b
CW		 3523 if (!intel_crtc->active)
3524 return;
3525
ea9d758d
DV		 3526 for_each_encoder_on_crtc(dev, crtc, encoder)
3527 encoder->disable(encoder);
3528
e6c3a2a6 3529 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3530 drm_vblank_off(dev, pipe);
6b383a7f 3531 intel_crtc_update_cursor(crtc, false);
5eddb70b 3532
b24e7179 3533 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3534
973d04f9
CW		 3535 if (dev_priv->cfb_plane == plane)
3536 intel_disable_fbc(dev);
2c07245f 3537
b24e7179 3538 intel_disable_pipe(dev_priv, pipe);
32f9d658 3539
6be4a607 3540 /* Disable PF */
9db4a9c7
JB		 3541 I915_WRITE(PF_CTL(pipe), 0);
3542 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3543
bf49ec8c
DV		 3544 for_each_encoder_on_crtc(dev, crtc, encoder)
3545 if (encoder->post_disable)
3546 encoder->post_disable(encoder);
3547
0fc932b8 3548 ironlake_fdi_disable(crtc);
2c07245f 3549
b8a4f404 3550 ironlake_disable_pch_transcoder(dev_priv, pipe);
913d8d11 3551
6be4a607
JB		 3552 if (HAS_PCH_CPT(dev)) {
3553 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3554 reg = TRANS_DP_CTL(pipe);
3555 temp = I915_READ(reg);
3556 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3557 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3558 I915_WRITE(reg, temp);
6be4a607
JB		 3559
3560 /* disable DPLL_SEL */
3561 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3562 switch (pipe) {
3563 case 0:
d64311ab 3564 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3565 break;
3566 case 1:
6be4a607 3567 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3568 break;
3569 case 2:
4b645f14 3570 /* C shares PLL A or B */
d64311ab 3571 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3572 break;
3573 default:
3574 BUG(); /* wtf */
3575 }
6be4a607 3576 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3577 }
e3421a18 3578
6be4a607 3579 /* disable PCH DPLL */
ee7b9f93 3580 intel_disable_pch_pll(intel_crtc);
8db9d77b 3581
88cefb6c 3582 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3583
f7abfe8b 3584 intel_crtc->active = false;
6b383a7f 3585 intel_update_watermarks(dev);
d1ebd816
BW		 3586
3587 mutex_lock(&dev->struct_mutex);
6b383a7f 3588 intel_update_fbc(dev);
d1ebd816 3589 mutex_unlock(&dev->struct_mutex);
6be4a607 3590}
1b3c7a47 3591
4f771f10
PZ		 3592static void haswell_crtc_disable(struct drm_crtc *crtc)
3593{
3594 struct drm_device *dev = crtc->dev;
3595 struct drm_i915_private *dev_priv = dev->dev_private;
3596 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3597 struct intel_encoder *encoder;
3598 int pipe = intel_crtc->pipe;
3599 int plane = intel_crtc->plane;
ad80a810 3600 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
83616634 3601 bool is_pch_port;
4f771f10
PZ		 3602
3603 if (!intel_crtc->active)
3604 return;
3605
83616634
PZ		 3606 is_pch_port = haswell_crtc_driving_pch(crtc);
3607
4f771f10
PZ		 3608 for_each_encoder_on_crtc(dev, crtc, encoder)
3609 encoder->disable(encoder);
3610
3611 intel_crtc_wait_for_pending_flips(crtc);
3612 drm_vblank_off(dev, pipe);
3613 intel_crtc_update_cursor(crtc, false);
3614
3615 intel_disable_plane(dev_priv, plane, pipe);
3616
3617 if (dev_priv->cfb_plane == plane)
3618 intel_disable_fbc(dev);
3619
3620 intel_disable_pipe(dev_priv, pipe);
3621
ad80a810 3622 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10
PZ		 3623
3624 /* Disable PF */
3625 I915_WRITE(PF_CTL(pipe), 0);
3626 I915_WRITE(PF_WIN_SZ(pipe), 0);
3627
1f544388 3628 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3629
3630 for_each_encoder_on_crtc(dev, crtc, encoder)
3631 if (encoder->post_disable)
3632 encoder->post_disable(encoder);
3633
83616634 3634 if (is_pch_port) {
ab4d966c 3635 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 3636 intel_ddi_fdi_disable(crtc);
83616634 3637 }
4f771f10
PZ		 3638
3639 intel_crtc->active = false;
3640 intel_update_watermarks(dev);
3641
3642 mutex_lock(&dev->struct_mutex);
3643 intel_update_fbc(dev);
3644 mutex_unlock(&dev->struct_mutex);
3645}
3646
ee7b9f93
JB		 3647static void ironlake_crtc_off(struct drm_crtc *crtc)
3648{
3649 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3650 intel_put_pch_pll(intel_crtc);
3651}
3652
6441ab5f
PZ		 3653static void haswell_crtc_off(struct drm_crtc *crtc)
3654{
a5c961d1
PZ		 3655 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3656
3657 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3658 * start using it. */
3659 intel_crtc->cpu_transcoder = intel_crtc->pipe;
3660
6441ab5f
PZ		 3661 intel_ddi_put_crtc_pll(crtc);
3662}
3663
02e792fb
DV		 3664static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3665{
02e792fb 3666 if (!enable && intel_crtc->overlay) {
23f09ce3 3667 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3668 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3669
23f09ce3 3670 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3671 dev_priv->mm.interruptible = false;
3672 (void) intel_overlay_switch_off(intel_crtc->overlay);
3673 dev_priv->mm.interruptible = true;
23f09ce3 3674 mutex_unlock(&dev->struct_mutex);
02e792fb 3675 }
02e792fb 3676
5dcdbcb0
CW		 3677 /* Let userspace switch the overlay on again. In most cases userspace
3678 * has to recompute where to put it anyway.
3679 */
02e792fb
DV		 3680}
3681
0b8765c6 3682static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3683{
3684 struct drm_device *dev = crtc->dev;
79e53945
JB		 3685 struct drm_i915_private *dev_priv = dev->dev_private;
3686 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3687 struct intel_encoder *encoder;
79e53945 3688 int pipe = intel_crtc->pipe;
80824003 3689 int plane = intel_crtc->plane;
79e53945 3690
08a48469
DV		 3691 WARN_ON(!crtc->enabled);
3692
f7abfe8b
CW		 3693 if (intel_crtc->active)
3694 return;
3695
3696 intel_crtc->active = true;
6b383a7f
CW		 3697 intel_update_watermarks(dev);
3698
63d7bbe9 3699 intel_enable_pll(dev_priv, pipe);
040484af 3700 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3701 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3702
0b8765c6 3703 intel_crtc_load_lut(crtc);
bed4a673 3704 intel_update_fbc(dev);
79e53945 3705
0b8765c6
JB		 3706 /* Give the overlay scaler a chance to enable if it's on this pipe */
3707 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3708 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3709
fa5c73b1
DV		 3710 for_each_encoder_on_crtc(dev, crtc, encoder)
3711 encoder->enable(encoder);
0b8765c6 3712}
79e53945 3713
0b8765c6
JB		 3714static void i9xx_crtc_disable(struct drm_crtc *crtc)
3715{
3716 struct drm_device *dev = crtc->dev;
3717 struct drm_i915_private *dev_priv = dev->dev_private;
3718 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3719 struct intel_encoder *encoder;
0b8765c6
JB		 3720 int pipe = intel_crtc->pipe;
3721 int plane = intel_crtc->plane;
b690e96c 3722
ef9c3aee 3723
f7abfe8b
CW		 3724 if (!intel_crtc->active)
3725 return;
3726
ea9d758d
DV		 3727 for_each_encoder_on_crtc(dev, crtc, encoder)
3728 encoder->disable(encoder);
3729
0b8765c6 3730 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3731 intel_crtc_wait_for_pending_flips(crtc);
3732 drm_vblank_off(dev, pipe);
0b8765c6 3733 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3734 intel_crtc_update_cursor(crtc, false);
0b8765c6 3735
973d04f9
CW		 3736 if (dev_priv->cfb_plane == plane)
3737 intel_disable_fbc(dev);
79e53945 3738
b24e7179 3739 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3740 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3741 intel_disable_pll(dev_priv, pipe);
0b8765c6 3742
f7abfe8b 3743 intel_crtc->active = false;
6b383a7f
CW		 3744 intel_update_fbc(dev);
3745 intel_update_watermarks(dev);
0b8765c6
JB		 3746}
3747
ee7b9f93
JB		 3748static void i9xx_crtc_off(struct drm_crtc *crtc)
3749{
3750}
3751
976f8a20
DV		 3752static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3753 bool enabled)
2c07245f
ZW		 3754{
3755 struct drm_device *dev = crtc->dev;
3756 struct drm_i915_master_private *master_priv;
3757 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3758 int pipe = intel_crtc->pipe;
79e53945
JB		 3759
3760 if (!dev->primary->master)
3761 return;
3762
3763 master_priv = dev->primary->master->driver_priv;
3764 if (!master_priv->sarea_priv)
3765 return;
3766
79e53945
JB		 3767 switch (pipe) {
3768 case 0:
3769 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3770 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3771 break;
3772 case 1:
3773 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3774 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3775 break;
3776 default:
9db4a9c7 3777 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3778 break;
3779 }
79e53945
JB		 3780}
3781
976f8a20
DV		 3782/**
3783 * Sets the power management mode of the pipe and plane.
3784 */
3785void intel_crtc_update_dpms(struct drm_crtc *crtc)
3786{
3787 struct drm_device *dev = crtc->dev;
3788 struct drm_i915_private *dev_priv = dev->dev_private;
3789 struct intel_encoder *intel_encoder;
3790 bool enable = false;
3791
3792 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3793 enable |= intel_encoder->connectors_active;
3794
3795 if (enable)
3796 dev_priv->display.crtc_enable(crtc);
3797 else
3798 dev_priv->display.crtc_disable(crtc);
3799
3800 intel_crtc_update_sarea(crtc, enable);
3801}
3802
3803static void intel_crtc_noop(struct drm_crtc *crtc)
3804{
3805}
3806
cdd59983
CW		 3807static void intel_crtc_disable(struct drm_crtc *crtc)
3808{
cdd59983 3809 struct drm_device *dev = crtc->dev;
976f8a20 3810 struct drm_connector *connector;
ee7b9f93 3811 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 3812
976f8a20
DV		 3813 /* crtc should still be enabled when we disable it. */
3814 WARN_ON(!crtc->enabled);
3815
3816 dev_priv->display.crtc_disable(crtc);
3817 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3818 dev_priv->display.off(crtc);
3819
931872fc
CW		 3820 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3821 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3822
3823 if (crtc->fb) {
3824 mutex_lock(&dev->struct_mutex);
1690e1eb 3825 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3826 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3827 crtc->fb = NULL;
3828 }
3829
3830 /* Update computed state. */
3831 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3832 if (!connector->encoder || !connector->encoder->crtc)
3833 continue;
3834
3835 if (connector->encoder->crtc != crtc)
3836 continue;
3837
3838 connector->dpms = DRM_MODE_DPMS_OFF;
3839 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3840 }
3841}
3842
a261b246 3843void intel_modeset_disable(struct drm_device *dev)
79e53945 3844{
a261b246
DV		 3845 struct drm_crtc *crtc;
3846
3847 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3848 if (crtc->enabled)
3849 intel_crtc_disable(crtc);
3850 }
79e53945
JB		 3851}
3852
1f703855 3853void intel_encoder_noop(struct drm_encoder *encoder)
79e53945 3854{
7e7d76c3
JB		 3855}
3856
ea5b213a 3857void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3858{
4ef69c7a 3859 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3860
ea5b213a
CW		 3861 drm_encoder_cleanup(encoder);
3862 kfree(intel_encoder);
7e7d76c3
JB		 3863}
3864
5ab432ef
DV		 3865/* Simple dpms helper for encodres with just one connector, no cloning and only
3866 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3867 * state of the entire output pipe. */
3868void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3869{
5ab432ef
DV		 3870 if (mode == DRM_MODE_DPMS_ON) {
3871 encoder->connectors_active = true;
3872
b2cabb0e 3873 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3874 } else {
3875 encoder->connectors_active = false;
3876
b2cabb0e 3877 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3878 }
79e53945
JB		 3879}
3880
0a91ca29
DV		 3881/* Cross check the actual hw state with our own modeset state tracking (and it's
3882 * internal consistency). */
b980514c 3883static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3884{
0a91ca29
DV		 3885 if (connector->get_hw_state(connector)) {
3886 struct intel_encoder *encoder = connector->encoder;
3887 struct drm_crtc *crtc;
3888 bool encoder_enabled;
3889 enum pipe pipe;
3890
3891 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3892 connector->base.base.id,
3893 drm_get_connector_name(&connector->base));
3894
3895 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3896 "wrong connector dpms state\n");
3897 WARN(connector->base.encoder != &encoder->base,
3898 "active connector not linked to encoder\n");
3899 WARN(!encoder->connectors_active,
3900 "encoder->connectors_active not set\n");
3901
3902 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3903 WARN(!encoder_enabled, "encoder not enabled\n");
3904 if (WARN_ON(!encoder->base.crtc))
3905 return;
3906
3907 crtc = encoder->base.crtc;
3908
3909 WARN(!crtc->enabled, "crtc not enabled\n");
3910 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3911 WARN(pipe != to_intel_crtc(crtc)->pipe,
3912 "encoder active on the wrong pipe\n");
3913 }
79e53945
JB		 3914}
3915
5ab432ef
DV		 3916/* Even simpler default implementation, if there's really no special case to
3917 * consider. */
3918void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3919{
5ab432ef 3920 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3921
5ab432ef
DV		 3922 /* All the simple cases only support two dpms states. */
3923 if (mode != DRM_MODE_DPMS_ON)
3924 mode = DRM_MODE_DPMS_OFF;
d4270e57 3925
5ab432ef
DV		 3926 if (mode == connector->dpms)
3927 return;
3928
3929 connector->dpms = mode;
3930
3931 /* Only need to change hw state when actually enabled */
3932 if (encoder->base.crtc)
3933 intel_encoder_dpms(encoder, mode);
3934 else
8af6cf88 3935 WARN_ON(encoder->connectors_active != false);
0a91ca29 3936
b980514c 3937 intel_modeset_check_state(connector->dev);
79e53945
JB		 3938}
3939
f0947c37
DV		 3940/* Simple connector->get_hw_state implementation for encoders that support only
3941 * one connector and no cloning and hence the encoder state determines the state
3942 * of the connector. */
3943bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3944{
24929352 3945 enum pipe pipe = 0;
f0947c37 3946 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3947
f0947c37 3948 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3949}
3950
79e53945 3951static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
35313cde 3952 const struct drm_display_mode *mode,
79e53945
JB		 3953 struct drm_display_mode *adjusted_mode)
3954{
2c07245f 3955 struct drm_device *dev = crtc->dev;
89749350 3956
bad720ff 3957 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3958 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3959 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3960 return false;
2c07245f 3961 }
89749350 3962
f9bef081
DV		 3963 /* All interlaced capable intel hw wants timings in frames. Note though
3964 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3965 * timings, so we need to be careful not to clobber these.*/
3966 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3967 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3968
44f46b42
CW		 3969 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3970 * with a hsync front porch of 0.
3971 */
3972 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3973 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3974 return false;
3975
79e53945
JB		 3976 return true;
3977}
3978
25eb05fc
JB		 3979static int valleyview_get_display_clock_speed(struct drm_device *dev)
3980{
3981 return 400000; /* FIXME */
3982}
3983
e70236a8
JB		 3984static int i945_get_display_clock_speed(struct drm_device *dev)
3985{
3986 return 400000;
3987}
79e53945 3988
e70236a8 3989static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3990{
e70236a8
JB		 3991 return 333000;
3992}
79e53945 3993
e70236a8
JB		 3994static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3995{
3996 return 200000;
3997}
79e53945 3998
e70236a8
JB		 3999static int i915gm_get_display_clock_speed(struct drm_device *dev)
4000{
4001 u16 gcfgc = 0;
79e53945 4002
e70236a8
JB		 4003 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4004
4005 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4006 return 133000;
4007 else {
4008 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4009 case GC_DISPLAY_CLOCK_333_MHZ:
4010 return 333000;
4011 default:
4012 case GC_DISPLAY_CLOCK_190_200_MHZ:
4013 return 190000;
79e53945 4014 }
e70236a8
JB		 4015 }
4016}
4017
4018static int i865_get_display_clock_speed(struct drm_device *dev)
4019{
4020 return 266000;
4021}
4022
4023static int i855_get_display_clock_speed(struct drm_device *dev)
4024{
4025 u16 hpllcc = 0;
4026 /* Assume that the hardware is in the high speed state. This
4027 * should be the default.
4028 */
4029 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4030 case GC_CLOCK_133_200:
4031 case GC_CLOCK_100_200:
4032 return 200000;
4033 case GC_CLOCK_166_250:
4034 return 250000;
4035 case GC_CLOCK_100_133:
79e53945 4036 return 133000;
e70236a8 4037 }
79e53945 4038
e70236a8
JB		 4039 /* Shouldn't happen */
4040 return 0;
4041}
79e53945 4042
e70236a8
JB		 4043static int i830_get_display_clock_speed(struct drm_device *dev)
4044{
4045 return 133000;
79e53945
JB		 4046}
4047
2c07245f
ZW		 4048struct fdi_m_n {
4049 u32 tu;
4050 u32 gmch_m;
4051 u32 gmch_n;
4052 u32 link_m;
4053 u32 link_n;
4054};
4055
4056static void
4057fdi_reduce_ratio(u32 *num, u32 *den)
4058{
4059 while (*num > 0xffffff || *den > 0xffffff) {
4060 *num >>= 1;
4061 *den >>= 1;
4062 }
4063}
4064
2c07245f 4065static void
f2b115e6
AJ		 4066ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
4067 int link_clock, struct fdi_m_n *m_n)
2c07245f 4068{
2c07245f
ZW		 4069 m_n->tu = 64; /* default size */
4070
22ed1113
CW		 4071 /* BUG_ON(pixel_clock > INT_MAX / 36); */
4072 m_n->gmch_m = bits_per_pixel * pixel_clock;
4073 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 4074 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4075
22ed1113
CW		 4076 m_n->link_m = pixel_clock;
4077 m_n->link_n = link_clock;
2c07245f
ZW		 4078 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
4079}
4080
a7615030
CW		 4081static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4082{
72bbe58c
KP		 4083 if (i915_panel_use_ssc >= 0)
4084 return i915_panel_use_ssc != 0;
4085 return dev_priv->lvds_use_ssc
435793df 4086 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4087}
4088
5a354204
JB		 4089/**
4090 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4091 * @crtc: CRTC structure
3b5c78a3 4092 * @mode: requested mode
5a354204
JB		 4093 *
4094 * A pipe may be connected to one or more outputs. Based on the depth of the
4095 * attached framebuffer, choose a good color depth to use on the pipe.
4096 *
4097 * If possible, match the pipe depth to the fb depth. In some cases, this
4098 * isn't ideal, because the connected output supports a lesser or restricted
4099 * set of depths. Resolve that here:
4100 * LVDS typically supports only 6bpc, so clamp down in that case
4101 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4102 * Displays may support a restricted set as well, check EDID and clamp as
4103 * appropriate.
3b5c78a3 4104 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 4105 *
4106 * RETURNS:
4107 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4108 * true if they don't match).
4109 */
4110static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
94352cf9 4111 struct drm_framebuffer *fb,
3b5c78a3
AJ		 4112 unsigned int *pipe_bpp,
4113 struct drm_display_mode *mode)
5a354204
JB		 4114{
4115 struct drm_device *dev = crtc->dev;
4116 struct drm_i915_private *dev_priv = dev->dev_private;
5a354204 4117 struct drm_connector *connector;
6c2b7c12 4118 struct intel_encoder *intel_encoder;
5a354204
JB		 4119 unsigned int display_bpc = UINT_MAX, bpc;
4120
4121 /* Walk the encoders & connectors on this crtc, get min bpc */
6c2b7c12 4122 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5a354204
JB		 4123
4124 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4125 unsigned int lvds_bpc;
4126
4127 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4128 LVDS_A3_POWER_UP)
4129 lvds_bpc = 8;
4130 else
4131 lvds_bpc = 6;
4132
4133 if (lvds_bpc < display_bpc) {
82820490 4134 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 4135 display_bpc = lvds_bpc;
4136 }
4137 continue;
4138 }
4139
5a354204
JB		 4140 /* Not one of the known troublemakers, check the EDID */
4141 list_for_each_entry(connector, &dev->mode_config.connector_list,
4142 head) {
6c2b7c12 4143 if (connector->encoder != &intel_encoder->base)
5a354204
JB		 4144 continue;
4145
62ac41a6
JB		 4146 /* Don't use an invalid EDID bpc value */
4147 if (connector->display_info.bpc &&
4148 connector->display_info.bpc < display_bpc) {
82820490 4149 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 4150 display_bpc = connector->display_info.bpc;
4151 }
4152 }
4153
4154 /*
4155 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4156 * through, clamp it down. (Note: >12bpc will be caught below.)
4157 */
4158 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4159 if (display_bpc > 8 && display_bpc < 12) {
82820490 4160 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 4161 display_bpc = 12;
4162 } else {
82820490 4163 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 4164 display_bpc = 8;
4165 }
4166 }
4167 }
4168
3b5c78a3
AJ		 4169 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4170 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4171 display_bpc = 6;
4172 }
4173
5a354204
JB		 4174 /*
4175 * We could just drive the pipe at the highest bpc all the time and
4176 * enable dithering as needed, but that costs bandwidth. So choose
4177 * the minimum value that expresses the full color range of the fb but
4178 * also stays within the max display bpc discovered above.
4179 */
4180
94352cf9 4181 switch (fb->depth) {
5a354204
JB		 4182 case 8:
4183 bpc = 8; /* since we go through a colormap */
4184 break;
4185 case 15:
4186 case 16:
4187 bpc = 6; /* min is 18bpp */
4188 break;
4189 case 24:
578393cd 4190 bpc = 8;
5a354204
JB		 4191 break;
4192 case 30:
578393cd 4193 bpc = 10;
5a354204
JB		 4194 break;
4195 case 48:
578393cd 4196 bpc = 12;
5a354204
JB		 4197 break;
4198 default:
4199 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4200 bpc = min((unsigned int)8, display_bpc);
4201 break;
4202 }
4203
578393cd
KP		 4204 display_bpc = min(display_bpc, bpc);
4205
82820490
AJ		 4206 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4207 bpc, display_bpc);
5a354204 4208
578393cd 4209 *pipe_bpp = display_bpc * 3;
5a354204
JB		 4210
4211 return display_bpc != bpc;
4212}
4213
a0c4da24
JB		 4214static int vlv_get_refclk(struct drm_crtc *crtc)
4215{
4216 struct drm_device *dev = crtc->dev;
4217 struct drm_i915_private *dev_priv = dev->dev_private;
4218 int refclk = 27000; /* for DP & HDMI */
4219
4220 return 100000; /* only one validated so far */
4221
4222 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4223 refclk = 96000;
4224 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4225 if (intel_panel_use_ssc(dev_priv))
4226 refclk = 100000;
4227 else
4228 refclk = 96000;
4229 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4230 refclk = 100000;
4231 }
4232
4233 return refclk;
4234}
4235
c65d77d8
JB		 4236static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4237{
4238 struct drm_device *dev = crtc->dev;
4239 struct drm_i915_private *dev_priv = dev->dev_private;
4240 int refclk;
4241
a0c4da24
JB		 4242 if (IS_VALLEYVIEW(dev)) {
4243 refclk = vlv_get_refclk(crtc);
4244 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 4245 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4246 refclk = dev_priv->lvds_ssc_freq * 1000;
4247 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4248 refclk / 1000);
4249 } else if (!IS_GEN2(dev)) {
4250 refclk = 96000;
4251 } else {
4252 refclk = 48000;
4253 }
4254
4255 return refclk;
4256}
4257
4258static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4259 intel_clock_t *clock)
4260{
4261 /* SDVO TV has fixed PLL values depend on its clock range,
4262 this mirrors vbios setting. */
4263 if (adjusted_mode->clock >= 100000
4264 && adjusted_mode->clock < 140500) {
4265 clock->p1 = 2;
4266 clock->p2 = 10;
4267 clock->n = 3;
4268 clock->m1 = 16;
4269 clock->m2 = 8;
4270 } else if (adjusted_mode->clock >= 140500
4271 && adjusted_mode->clock <= 200000) {
4272 clock->p1 = 1;
4273 clock->p2 = 10;
4274 clock->n = 6;
4275 clock->m1 = 12;
4276 clock->m2 = 8;
4277 }
4278}
4279
a7516a05
JB		 4280static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4281 intel_clock_t *clock,
4282 intel_clock_t *reduced_clock)
4283{
4284 struct drm_device *dev = crtc->dev;
4285 struct drm_i915_private *dev_priv = dev->dev_private;
4286 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4287 int pipe = intel_crtc->pipe;
4288 u32 fp, fp2 = 0;
4289
4290 if (IS_PINEVIEW(dev)) {
4291 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4292 if (reduced_clock)
4293 fp2 = (1 << reduced_clock->n) << 16 |
4294 reduced_clock->m1 << 8 | reduced_clock->m2;
4295 } else {
4296 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4297 if (reduced_clock)
4298 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4299 reduced_clock->m2;
4300 }
4301
4302 I915_WRITE(FP0(pipe), fp);
4303
4304 intel_crtc->lowfreq_avail = false;
4305 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4306 reduced_clock && i915_powersave) {
4307 I915_WRITE(FP1(pipe), fp2);
4308 intel_crtc->lowfreq_avail = true;
4309 } else {
4310 I915_WRITE(FP1(pipe), fp);
4311 }
4312}
4313
93e537a1
DV		 4314static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4315 struct drm_display_mode *adjusted_mode)
4316{
4317 struct drm_device *dev = crtc->dev;
4318 struct drm_i915_private *dev_priv = dev->dev_private;
4319 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4320 int pipe = intel_crtc->pipe;
284d5df5 4321 u32 temp;
93e537a1
DV		 4322
4323 temp = I915_READ(LVDS);
4324 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4325 if (pipe == 1) {
4326 temp |= LVDS_PIPEB_SELECT;
4327 } else {
4328 temp &= ~LVDS_PIPEB_SELECT;
4329 }
4330 /* set the corresponsding LVDS_BORDER bit */
4331 temp |= dev_priv->lvds_border_bits;
4332 /* Set the B0-B3 data pairs corresponding to whether we're going to
4333 * set the DPLLs for dual-channel mode or not.
4334 */
4335 if (clock->p2 == 7)
4336 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4337 else
4338 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4339
4340 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4341 * appropriately here, but we need to look more thoroughly into how
4342 * panels behave in the two modes.
4343 */
4344 /* set the dithering flag on LVDS as needed */
4345 if (INTEL_INFO(dev)->gen >= 4) {
4346 if (dev_priv->lvds_dither)
4347 temp |= LVDS_ENABLE_DITHER;
4348 else
4349 temp &= ~LVDS_ENABLE_DITHER;
4350 }
284d5df5 4351 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
93e537a1 4352 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 4353 temp |= LVDS_HSYNC_POLARITY;
93e537a1 4354 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 4355 temp |= LVDS_VSYNC_POLARITY;
93e537a1
DV		 4356 I915_WRITE(LVDS, temp);
4357}
4358
a0c4da24
JB		 4359static void vlv_update_pll(struct drm_crtc *crtc,
4360 struct drm_display_mode *mode,
4361 struct drm_display_mode *adjusted_mode,
4362 intel_clock_t *clock, intel_clock_t *reduced_clock,
2a8f64ca 4363 int num_connectors)
a0c4da24
JB		 4364{
4365 struct drm_device *dev = crtc->dev;
4366 struct drm_i915_private *dev_priv = dev->dev_private;
4367 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4368 int pipe = intel_crtc->pipe;
4369 u32 dpll, mdiv, pdiv;
4370 u32 bestn, bestm1, bestm2, bestp1, bestp2;
2a8f64ca
VP		 4371 bool is_sdvo;
4372 u32 temp;
4373
4374 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4375 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
a0c4da24 4376
2a8f64ca
VP		 4377 dpll = DPLL_VGA_MODE_DIS;
4378 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4379 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4380 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4381
4382 I915_WRITE(DPLL(pipe), dpll);
4383 POSTING_READ(DPLL(pipe));
a0c4da24
JB		 4384
4385 bestn = clock->n;
4386 bestm1 = clock->m1;
4387 bestm2 = clock->m2;
4388 bestp1 = clock->p1;
4389 bestp2 = clock->p2;
4390
2a8f64ca
VP		 4391 /*
4392 * In Valleyview PLL and program lane counter registers are exposed
4393 * through DPIO interface
4394 */
a0c4da24
JB		 4395 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4396 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4397 mdiv |= ((bestn << DPIO_N_SHIFT));
4398 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4399 mdiv |= (1 << DPIO_K_SHIFT);
4400 mdiv |= DPIO_ENABLE_CALIBRATION;
4401 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4402
4403 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4404
2a8f64ca 4405 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
a0c4da24 4406 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
2a8f64ca
VP		 4407 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4408 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
a0c4da24
JB		 4409 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4410
2a8f64ca 4411 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
a0c4da24
JB		 4412
4413 dpll |= DPLL_VCO_ENABLE;
4414 I915_WRITE(DPLL(pipe), dpll);
4415 POSTING_READ(DPLL(pipe));
4416 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4417 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4418
2a8f64ca
VP		 4419 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4420
4421 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4422 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4423
4424 I915_WRITE(DPLL(pipe), dpll);
4425
4426 /* Wait for the clocks to stabilize. */
4427 POSTING_READ(DPLL(pipe));
4428 udelay(150);
a0c4da24 4429
2a8f64ca
VP		 4430 temp = 0;
4431 if (is_sdvo) {
4432 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
a0c4da24
JB		 4433 if (temp > 1)
4434 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4435 else
4436 temp = 0;
a0c4da24 4437 }
2a8f64ca
VP		 4438 I915_WRITE(DPLL_MD(pipe), temp);
4439 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4440
2a8f64ca
VP		 4441 /* Now program lane control registers */
4442 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4443 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4444 {
4445 temp = 0x1000C4;
4446 if(pipe == 1)
4447 temp |= (1 << 21);
4448 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4449 }
4450 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4451 {
4452 temp = 0x1000C4;
4453 if(pipe == 1)
4454 temp |= (1 << 21);
4455 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4456 }
a0c4da24
JB		 4457}
4458
eb1cbe48
DV		 4459static void i9xx_update_pll(struct drm_crtc *crtc,
4460 struct drm_display_mode *mode,
4461 struct drm_display_mode *adjusted_mode,
4462 intel_clock_t *clock, intel_clock_t *reduced_clock,
4463 int num_connectors)
4464{
4465 struct drm_device *dev = crtc->dev;
4466 struct drm_i915_private *dev_priv = dev->dev_private;
4467 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4468 int pipe = intel_crtc->pipe;
4469 u32 dpll;
4470 bool is_sdvo;
4471
2a8f64ca
VP		 4472 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4473
eb1cbe48
DV		 4474 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4475 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4476
4477 dpll = DPLL_VGA_MODE_DIS;
4478
4479 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4480 dpll |= DPLLB_MODE_LVDS;
4481 else
4482 dpll |= DPLLB_MODE_DAC_SERIAL;
4483 if (is_sdvo) {
4484 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4485 if (pixel_multiplier > 1) {
4486 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4487 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4488 }
4489 dpll |= DPLL_DVO_HIGH_SPEED;
4490 }
4491 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4492 dpll |= DPLL_DVO_HIGH_SPEED;
4493
4494 /* compute bitmask from p1 value */
4495 if (IS_PINEVIEW(dev))
4496 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4497 else {
4498 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4499 if (IS_G4X(dev) && reduced_clock)
4500 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4501 }
4502 switch (clock->p2) {
4503 case 5:
4504 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4505 break;
4506 case 7:
4507 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4508 break;
4509 case 10:
4510 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4511 break;
4512 case 14:
4513 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4514 break;
4515 }
4516 if (INTEL_INFO(dev)->gen >= 4)
4517 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4518
4519 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4520 dpll |= PLL_REF_INPUT_TVCLKINBC;
4521 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4522 /* XXX: just matching BIOS for now */
4523 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4524 dpll |= 3;
4525 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4526 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4527 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4528 else
4529 dpll |= PLL_REF_INPUT_DREFCLK;
4530
4531 dpll |= DPLL_VCO_ENABLE;
4532 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4533 POSTING_READ(DPLL(pipe));
4534 udelay(150);
4535
4536 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4537 * This is an exception to the general rule that mode_set doesn't turn
4538 * things on.
4539 */
4540 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4541 intel_update_lvds(crtc, clock, adjusted_mode);
4542
4543 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4544 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4545
4546 I915_WRITE(DPLL(pipe), dpll);
4547
4548 /* Wait for the clocks to stabilize. */
4549 POSTING_READ(DPLL(pipe));
4550 udelay(150);
4551
4552 if (INTEL_INFO(dev)->gen >= 4) {
4553 u32 temp = 0;
4554 if (is_sdvo) {
4555 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4556 if (temp > 1)
4557 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4558 else
4559 temp = 0;
4560 }
4561 I915_WRITE(DPLL_MD(pipe), temp);
4562 } else {
4563 /* The pixel multiplier can only be updated once the
4564 * DPLL is enabled and the clocks are stable.
4565 *
4566 * So write it again.
4567 */
4568 I915_WRITE(DPLL(pipe), dpll);
4569 }
4570}
4571
4572static void i8xx_update_pll(struct drm_crtc *crtc,
4573 struct drm_display_mode *adjusted_mode,
2a8f64ca 4574 intel_clock_t *clock, intel_clock_t *reduced_clock,
eb1cbe48
DV		 4575 int num_connectors)
4576{
4577 struct drm_device *dev = crtc->dev;
4578 struct drm_i915_private *dev_priv = dev->dev_private;
4579 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4580 int pipe = intel_crtc->pipe;
4581 u32 dpll;
4582
2a8f64ca
VP		 4583 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4584
eb1cbe48
DV		 4585 dpll = DPLL_VGA_MODE_DIS;
4586
4587 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4588 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4589 } else {
4590 if (clock->p1 == 2)
4591 dpll |= PLL_P1_DIVIDE_BY_TWO;
4592 else
4593 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4594 if (clock->p2 == 4)
4595 dpll |= PLL_P2_DIVIDE_BY_4;
4596 }
4597
4598 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4599 /* XXX: just matching BIOS for now */
4600 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4601 dpll |= 3;
4602 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4603 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4604 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4605 else
4606 dpll |= PLL_REF_INPUT_DREFCLK;
4607
4608 dpll |= DPLL_VCO_ENABLE;
4609 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4610 POSTING_READ(DPLL(pipe));
4611 udelay(150);
4612
eb1cbe48
DV		 4613 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4614 * This is an exception to the general rule that mode_set doesn't turn
4615 * things on.
4616 */
4617 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4618 intel_update_lvds(crtc, clock, adjusted_mode);
4619
5b5896e4
DV		 4620 I915_WRITE(DPLL(pipe), dpll);
4621
4622 /* Wait for the clocks to stabilize. */
4623 POSTING_READ(DPLL(pipe));
4624 udelay(150);
4625
eb1cbe48
DV		 4626 /* The pixel multiplier can only be updated once the
4627 * DPLL is enabled and the clocks are stable.
4628 *
4629 * So write it again.
4630 */
4631 I915_WRITE(DPLL(pipe), dpll);
4632}
4633
b0e77b9c
PZ		 4634static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4635 struct drm_display_mode *mode,
4636 struct drm_display_mode *adjusted_mode)
4637{
4638 struct drm_device *dev = intel_crtc->base.dev;
4639 struct drm_i915_private *dev_priv = dev->dev_private;
4640 enum pipe pipe = intel_crtc->pipe;
fe2b8f9d 4641 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
b0e77b9c
PZ		 4642 uint32_t vsyncshift;
4643
4644 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4645 /* the chip adds 2 halflines automatically */
4646 adjusted_mode->crtc_vtotal -= 1;
4647 adjusted_mode->crtc_vblank_end -= 1;
4648 vsyncshift = adjusted_mode->crtc_hsync_start
4649 - adjusted_mode->crtc_htotal / 2;
4650 } else {
4651 vsyncshift = 0;
4652 }
4653
4654 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4655 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4656
fe2b8f9d 4657 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4658 (adjusted_mode->crtc_hdisplay - 1) |
4659 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4660 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4661 (adjusted_mode->crtc_hblank_start - 1) |
4662 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4663 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4664 (adjusted_mode->crtc_hsync_start - 1) |
4665 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4666
fe2b8f9d 4667 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4668 (adjusted_mode->crtc_vdisplay - 1) |
4669 ((adjusted_mode->crtc_vtotal - 1) << 16));
fe2b8f9d 4670 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c
PZ		 4671 (adjusted_mode->crtc_vblank_start - 1) |
4672 ((adjusted_mode->crtc_vblank_end - 1) << 16));
fe2b8f9d 4673 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4674 (adjusted_mode->crtc_vsync_start - 1) |
4675 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4676
b5e508d4
PZ		 4677 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4678 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4679 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4680 * bits. */
4681 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4682 (pipe == PIPE_B || pipe == PIPE_C))
4683 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4684
b0e77b9c
PZ		 4685 /* pipesrc controls the size that is scaled from, which should
4686 * always be the user's requested size.
4687 */
4688 I915_WRITE(PIPESRC(pipe),
4689 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4690}
4691
f564048e
EA		 4692static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4693 struct drm_display_mode *mode,
4694 struct drm_display_mode *adjusted_mode,
4695 int x, int y,
94352cf9 4696 struct drm_framebuffer *fb)
79e53945
JB		 4697{
4698 struct drm_device *dev = crtc->dev;
4699 struct drm_i915_private *dev_priv = dev->dev_private;
4700 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4701 int pipe = intel_crtc->pipe;
80824003 4702 int plane = intel_crtc->plane;
c751ce4f 4703 int refclk, num_connectors = 0;
652c393a 4704 intel_clock_t clock, reduced_clock;
b0e77b9c 4705 u32 dspcntr, pipeconf;
eb1cbe48
DV		 4706 bool ok, has_reduced_clock = false, is_sdvo = false;
4707 bool is_lvds = false, is_tv = false, is_dp = false;
5eddb70b 4708 struct intel_encoder *encoder;
d4906093 4709 const intel_limit_t *limit;
5c3b82e2 4710 int ret;
79e53945 4711
6c2b7c12 4712 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4713 switch (encoder->type) {
79e53945
JB		 4714 case INTEL_OUTPUT_LVDS:
4715 is_lvds = true;
4716 break;
4717 case INTEL_OUTPUT_SDVO:
7d57382e 4718 case INTEL_OUTPUT_HDMI:
79e53945 4719 is_sdvo = true;
5eddb70b 4720 if (encoder->needs_tv_clock)
e2f0ba97 4721 is_tv = true;
79e53945 4722 break;
79e53945
JB		 4723 case INTEL_OUTPUT_TVOUT:
4724 is_tv = true;
4725 break;
a4fc5ed6
KP		 4726 case INTEL_OUTPUT_DISPLAYPORT:
4727 is_dp = true;
4728 break;
79e53945 4729 }
43565a06 4730
c751ce4f 4731 num_connectors++;
79e53945
JB		 4732 }
4733
c65d77d8 4734 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4735
d4906093
ML		 4736 /*
4737 * Returns a set of divisors for the desired target clock with the given
4738 * refclk, or FALSE. The returned values represent the clock equation:
4739 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4740 */
1b894b59 4741 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4742 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4743 &clock);
79e53945
JB		 4744 if (!ok) {
4745 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4746 return -EINVAL;
79e53945
JB		 4747 }
4748
cda4b7d3 4749 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4750 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4751
ddc9003c 4752 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4753 /*
4754 * Ensure we match the reduced clock's P to the target clock.
4755 * If the clocks don't match, we can't switch the display clock
4756 * by using the FP0/FP1. In such case we will disable the LVDS
4757 * downclock feature.
4758 */
ddc9003c 4759 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4760 dev_priv->lvds_downclock,
4761 refclk,
cec2f356 4762 &clock,
5eddb70b 4763 &reduced_clock);
7026d4ac
ZW		 4764 }
4765
c65d77d8
JB		 4766 if (is_sdvo && is_tv)
4767 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 4768
eb1cbe48 4769 if (IS_GEN2(dev))
2a8f64ca
VP		 4770 i8xx_update_pll(crtc, adjusted_mode, &clock,
4771 has_reduced_clock ? &reduced_clock : NULL,
4772 num_connectors);
a0c4da24 4773 else if (IS_VALLEYVIEW(dev))
2a8f64ca
VP		 4774 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4775 has_reduced_clock ? &reduced_clock : NULL,
4776 num_connectors);
79e53945 4777 else
eb1cbe48
DV		 4778 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4779 has_reduced_clock ? &reduced_clock : NULL,
4780 num_connectors);
79e53945
JB		 4781
4782 /* setup pipeconf */
5eddb70b 4783 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4784
4785 /* Set up the display plane register */
4786 dspcntr = DISPPLANE_GAMMA_ENABLE;
4787
929c77fb
EA		 4788 if (pipe == 0)
4789 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4790 else
4791 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4792
a6c45cf0 4793 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4794 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4795 * core speed.
4796 *
4797 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4798 * pipe == 0 check?
4799 */
e70236a8
JB		 4800 if (mode->clock >
4801 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4802 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4803 else
5eddb70b 4804 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4805 }
4806
3b5c78a3
AJ		 4807 /* default to 8bpc */
4808 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4809 if (is_dp) {
0c96c65b 4810 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3b5c78a3
AJ		 4811 pipeconf |= PIPECONF_BPP_6 |
4812 PIPECONF_DITHER_EN |
4813 PIPECONF_DITHER_TYPE_SP;
4814 }
4815 }
4816
19c03924
GB		 4817 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4818 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4819 pipeconf |= PIPECONF_BPP_6 |
4820 PIPECONF_ENABLE |
4821 I965_PIPECONF_ACTIVE;
4822 }
4823 }
4824
28c97730 4825 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4826 drm_mode_debug_printmodeline(mode);
4827
a7516a05
JB		 4828 if (HAS_PIPE_CXSR(dev)) {
4829 if (intel_crtc->lowfreq_avail) {
28c97730 4830 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 4831 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 4832 } else {
28c97730 4833 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4834 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4835 }
4836 }
4837
617cf884 4838 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575 4839 if (!IS_GEN2(dev) &&
b0e77b9c 4840 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
734b4157 4841 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
b0e77b9c 4842 else
617cf884 4843 pipeconf |= PIPECONF_PROGRESSIVE;
734b4157 4844
b0e77b9c 4845 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4846
4847 /* pipesrc and dspsize control the size that is scaled from,
4848 * which should always be the user's requested size.
79e53945 4849 */
929c77fb
EA		 4850 I915_WRITE(DSPSIZE(plane),
4851 ((mode->vdisplay - 1) << 16) |
4852 (mode->hdisplay - 1));
4853 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4854
f564048e
EA		 4855 I915_WRITE(PIPECONF(pipe), pipeconf);
4856 POSTING_READ(PIPECONF(pipe));
929c77fb 4857 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4858
4859 intel_wait_for_vblank(dev, pipe);
4860
f564048e
EA		 4861 I915_WRITE(DSPCNTR(plane), dspcntr);
4862 POSTING_READ(DSPCNTR(plane));
4863
94352cf9 4864 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4865
4866 intel_update_watermarks(dev);
4867
f564048e
EA		 4868 return ret;
4869}
4870
9fb526db
KP		 4871/*
4872 * Initialize reference clocks when the driver loads
4873 */
4874void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4875{
4876 struct drm_i915_private *dev_priv = dev->dev_private;
4877 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4878 struct intel_encoder *encoder;
13d83a67
JB		 4879 u32 temp;
4880 bool has_lvds = false;
199e5d79
KP		 4881 bool has_cpu_edp = false;
4882 bool has_pch_edp = false;
4883 bool has_panel = false;
99eb6a01
KP		 4884 bool has_ck505 = false;
4885 bool can_ssc = false;
13d83a67
JB		 4886
4887 /* We need to take the global config into account */
199e5d79
KP		 4888 list_for_each_entry(encoder, &mode_config->encoder_list,
4889 base.head) {
4890 switch (encoder->type) {
4891 case INTEL_OUTPUT_LVDS:
4892 has_panel = true;
4893 has_lvds = true;
4894 break;
4895 case INTEL_OUTPUT_EDP:
4896 has_panel = true;
4897 if (intel_encoder_is_pch_edp(&encoder->base))
4898 has_pch_edp = true;
4899 else
4900 has_cpu_edp = true;
4901 break;
13d83a67
JB		 4902 }
4903 }
4904
99eb6a01
KP		 4905 if (HAS_PCH_IBX(dev)) {
4906 has_ck505 = dev_priv->display_clock_mode;
4907 can_ssc = has_ck505;
4908 } else {
4909 has_ck505 = false;
4910 can_ssc = true;
4911 }
4912
4913 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4914 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4915 has_ck505);
13d83a67
JB		 4916
4917 /* Ironlake: try to setup display ref clock before DPLL
4918 * enabling. This is only under driver's control after
4919 * PCH B stepping, previous chipset stepping should be
4920 * ignoring this setting.
4921 */
4922 temp = I915_READ(PCH_DREF_CONTROL);
4923 /* Always enable nonspread source */
4924 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4925
99eb6a01
KP		 4926 if (has_ck505)
4927 temp |= DREF_NONSPREAD_CK505_ENABLE;
4928 else
4929 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4930
199e5d79
KP		 4931 if (has_panel) {
4932 temp &= ~DREF_SSC_SOURCE_MASK;
4933 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4934
199e5d79 4935 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4936 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4937 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4938 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4939 } else
4940 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4941
4942 /* Get SSC going before enabling the outputs */
4943 I915_WRITE(PCH_DREF_CONTROL, temp);
4944 POSTING_READ(PCH_DREF_CONTROL);
4945 udelay(200);
4946
13d83a67
JB		 4947 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4948
4949 /* Enable CPU source on CPU attached eDP */
199e5d79 4950 if (has_cpu_edp) {
99eb6a01 4951 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4952 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4953 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4954 }
13d83a67
JB		 4955 else
4956 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4957 } else
4958 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4959
4960 I915_WRITE(PCH_DREF_CONTROL, temp);
4961 POSTING_READ(PCH_DREF_CONTROL);
4962 udelay(200);
4963 } else {
4964 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4965
4966 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4967
4968 /* Turn off CPU output */
4969 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4970
4971 I915_WRITE(PCH_DREF_CONTROL, temp);
4972 POSTING_READ(PCH_DREF_CONTROL);
4973 udelay(200);
4974
4975 /* Turn off the SSC source */
4976 temp &= ~DREF_SSC_SOURCE_MASK;
4977 temp |= DREF_SSC_SOURCE_DISABLE;
4978
4979 /* Turn off SSC1 */
4980 temp &= ~ DREF_SSC1_ENABLE;
4981
13d83a67
JB		 4982 I915_WRITE(PCH_DREF_CONTROL, temp);
4983 POSTING_READ(PCH_DREF_CONTROL);
4984 udelay(200);
4985 }
4986}
4987
d9d444cb
JB		 4988static int ironlake_get_refclk(struct drm_crtc *crtc)
4989{
4990 struct drm_device *dev = crtc->dev;
4991 struct drm_i915_private *dev_priv = dev->dev_private;
4992 struct intel_encoder *encoder;
d9d444cb
JB		 4993 struct intel_encoder *edp_encoder = NULL;
4994 int num_connectors = 0;
4995 bool is_lvds = false;
4996
6c2b7c12 4997 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 4998 switch (encoder->type) {
4999 case INTEL_OUTPUT_LVDS:
5000 is_lvds = true;
5001 break;
5002 case INTEL_OUTPUT_EDP:
5003 edp_encoder = encoder;
5004 break;
5005 }
5006 num_connectors++;
5007 }
5008
5009 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5010 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5011 dev_priv->lvds_ssc_freq);
5012 return dev_priv->lvds_ssc_freq * 1000;
5013 }
5014
5015 return 120000;
5016}
5017
c8203565
PZ		 5018static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5019 struct drm_display_mode *adjusted_mode,
5020 bool dither)
5021{
5022 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5023 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5024 int pipe = intel_crtc->pipe;
5025 uint32_t val;
5026
5027 val = I915_READ(PIPECONF(pipe));
5028
5029 val &= ~PIPE_BPC_MASK;
5030 switch (intel_crtc->bpp) {
5031 case 18:
5032 val |= PIPE_6BPC;
5033 break;
5034 case 24:
5035 val |= PIPE_8BPC;
5036 break;
5037 case 30:
5038 val |= PIPE_10BPC;
5039 break;
5040 case 36:
5041 val |= PIPE_12BPC;
5042 break;
5043 default:
cc769b62
PZ		 5044 /* Case prevented by intel_choose_pipe_bpp_dither. */
5045 BUG();
c8203565
PZ		 5046 }
5047
5048 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5049 if (dither)
5050 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5051
5052 val &= ~PIPECONF_INTERLACE_MASK;
5053 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5054 val |= PIPECONF_INTERLACED_ILK;
5055 else
5056 val |= PIPECONF_PROGRESSIVE;
5057
5058 I915_WRITE(PIPECONF(pipe), val);
5059 POSTING_READ(PIPECONF(pipe));
5060}
5061
ee2b0b38
PZ		 5062static void haswell_set_pipeconf(struct drm_crtc *crtc,
5063 struct drm_display_mode *adjusted_mode,
5064 bool dither)
5065{
5066 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5067 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
702e7a56 5068 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
ee2b0b38
PZ		 5069 uint32_t val;
5070
702e7a56 5071 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5072
5073 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5074 if (dither)
5075 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5076
5077 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5078 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5079 val |= PIPECONF_INTERLACED_ILK;
5080 else
5081 val |= PIPECONF_PROGRESSIVE;
5082
702e7a56
PZ		 5083 I915_WRITE(PIPECONF(cpu_transcoder), val);
5084 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5085}
5086
6591c6e4
PZ		 5087static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5088 struct drm_display_mode *adjusted_mode,
5089 intel_clock_t *clock,
5090 bool *has_reduced_clock,
5091 intel_clock_t *reduced_clock)
5092{
5093 struct drm_device *dev = crtc->dev;
5094 struct drm_i915_private *dev_priv = dev->dev_private;
5095 struct intel_encoder *intel_encoder;
5096 int refclk;
5097 const intel_limit_t *limit;
5098 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5099
5100 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5101 switch (intel_encoder->type) {
5102 case INTEL_OUTPUT_LVDS:
5103 is_lvds = true;
5104 break;
5105 case INTEL_OUTPUT_SDVO:
5106 case INTEL_OUTPUT_HDMI:
5107 is_sdvo = true;
5108 if (intel_encoder->needs_tv_clock)
5109 is_tv = true;
5110 break;
5111 case INTEL_OUTPUT_TVOUT:
5112 is_tv = true;
5113 break;
5114 }
5115 }
5116
5117 refclk = ironlake_get_refclk(crtc);
5118
5119 /*
5120 * Returns a set of divisors for the desired target clock with the given
5121 * refclk, or FALSE. The returned values represent the clock equation:
5122 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5123 */
5124 limit = intel_limit(crtc, refclk);
5125 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5126 clock);
5127 if (!ret)
5128 return false;
5129
5130 if (is_lvds && dev_priv->lvds_downclock_avail) {
5131 /*
5132 * Ensure we match the reduced clock's P to the target clock.
5133 * If the clocks don't match, we can't switch the display clock
5134 * by using the FP0/FP1. In such case we will disable the LVDS
5135 * downclock feature.
5136 */
5137 *has_reduced_clock = limit->find_pll(limit, crtc,
5138 dev_priv->lvds_downclock,
5139 refclk,
5140 clock,
5141 reduced_clock);
5142 }
5143
5144 if (is_sdvo && is_tv)
5145 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5146
5147 return true;
5148}
5149
01a415fd
DV		 5150static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5151{
5152 struct drm_i915_private *dev_priv = dev->dev_private;
5153 uint32_t temp;
5154
5155 temp = I915_READ(SOUTH_CHICKEN1);
5156 if (temp & FDI_BC_BIFURCATION_SELECT)
5157 return;
5158
5159 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5160 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5161
5162 temp |= FDI_BC_BIFURCATION_SELECT;
5163 DRM_DEBUG_KMS("enabling fdi C rx\n");
5164 I915_WRITE(SOUTH_CHICKEN1, temp);
5165 POSTING_READ(SOUTH_CHICKEN1);
5166}
5167
5168static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5169{
5170 struct drm_device *dev = intel_crtc->base.dev;
5171 struct drm_i915_private *dev_priv = dev->dev_private;
5172 struct intel_crtc *pipe_B_crtc =
5173 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5174
5175 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5176 intel_crtc->pipe, intel_crtc->fdi_lanes);
5177 if (intel_crtc->fdi_lanes > 4) {
5178 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5179 intel_crtc->pipe, intel_crtc->fdi_lanes);
5180 /* Clamp lanes to avoid programming the hw with bogus values. */
5181 intel_crtc->fdi_lanes = 4;
5182
5183 return false;
5184 }
5185
5186 if (dev_priv->num_pipe == 2)
5187 return true;
5188
5189 switch (intel_crtc->pipe) {
5190 case PIPE_A:
5191 return true;
5192 case PIPE_B:
5193 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5194 intel_crtc->fdi_lanes > 2) {
5195 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5196 intel_crtc->pipe, intel_crtc->fdi_lanes);
5197 /* Clamp lanes to avoid programming the hw with bogus values. */
5198 intel_crtc->fdi_lanes = 2;
5199
5200 return false;
5201 }
5202
5203 if (intel_crtc->fdi_lanes > 2)
5204 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5205 else
5206 cpt_enable_fdi_bc_bifurcation(dev);
5207
5208 return true;
5209 case PIPE_C:
5210 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5211 if (intel_crtc->fdi_lanes > 2) {
5212 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5213 intel_crtc->pipe, intel_crtc->fdi_lanes);
5214 /* Clamp lanes to avoid programming the hw with bogus values. */
5215 intel_crtc->fdi_lanes = 2;
5216
5217 return false;
5218 }
5219 } else {
5220 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5221 return false;
5222 }
5223
5224 cpt_enable_fdi_bc_bifurcation(dev);
5225
5226 return true;
5227 default:
5228 BUG();
5229 }
5230}
5231
f48d8f23
PZ		 5232static void ironlake_set_m_n(struct drm_crtc *crtc,
5233 struct drm_display_mode *mode,
5234 struct drm_display_mode *adjusted_mode)
5235{
5236 struct drm_device *dev = crtc->dev;
5237 struct drm_i915_private *dev_priv = dev->dev_private;
5238 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
afe2fcf5 5239 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
f48d8f23
PZ		 5240 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5241 struct fdi_m_n m_n = {0};
5242 int target_clock, pixel_multiplier, lane, link_bw;
5243 bool is_dp = false, is_cpu_edp = false;
5244
5245 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5246 switch (intel_encoder->type) {
5247 case INTEL_OUTPUT_DISPLAYPORT:
5248 is_dp = true;
5249 break;
5250 case INTEL_OUTPUT_EDP:
5251 is_dp = true;
5252 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5253 is_cpu_edp = true;
5254 edp_encoder = intel_encoder;
5255 break;
5256 }
5257 }
5258
5259 /* FDI link */
5260 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5261 lane = 0;
5262 /* CPU eDP doesn't require FDI link, so just set DP M/N
5263 according to current link config */
5264 if (is_cpu_edp) {
5265 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5266 } else {
5267 /* FDI is a binary signal running at ~2.7GHz, encoding
5268 * each output octet as 10 bits. The actual frequency
5269 * is stored as a divider into a 100MHz clock, and the
5270 * mode pixel clock is stored in units of 1KHz.
5271 * Hence the bw of each lane in terms of the mode signal
5272 * is:
5273 */
5274 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5275 }
5276
5277 /* [e]DP over FDI requires target mode clock instead of link clock. */
5278 if (edp_encoder)
5279 target_clock = intel_edp_target_clock(edp_encoder, mode);
5280 else if (is_dp)
5281 target_clock = mode->clock;
5282 else
5283 target_clock = adjusted_mode->clock;
5284
5285 if (!lane) {
5286 /*
5287 * Account for spread spectrum to avoid
5288 * oversubscribing the link. Max center spread
5289 * is 2.5%; use 5% for safety's sake.
5290 */
5291 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5292 lane = bps / (link_bw * 8) + 1;
5293 }
5294
5295 intel_crtc->fdi_lanes = lane;
5296
5297 if (pixel_multiplier > 1)
5298 link_bw *= pixel_multiplier;
5299 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5300 &m_n);
5301
afe2fcf5
PZ		 5302 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5303 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5304 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5305 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
f48d8f23
PZ		 5306}
5307
de13a2e3
PZ		 5308static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5309 struct drm_display_mode *adjusted_mode,
5310 intel_clock_t *clock, u32 fp)
79e53945 5311{
de13a2e3 5312 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5313 struct drm_device *dev = crtc->dev;
5314 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5315 struct intel_encoder *intel_encoder;
5316 uint32_t dpll;
5317 int factor, pixel_multiplier, num_connectors = 0;
5318 bool is_lvds = false, is_sdvo = false, is_tv = false;
5319 bool is_dp = false, is_cpu_edp = false;
79e53945 5320
de13a2e3
PZ		 5321 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5322 switch (intel_encoder->type) {
79e53945
JB		 5323 case INTEL_OUTPUT_LVDS:
5324 is_lvds = true;
5325 break;
5326 case INTEL_OUTPUT_SDVO:
7d57382e 5327 case INTEL_OUTPUT_HDMI:
79e53945 5328 is_sdvo = true;
de13a2e3 5329 if (intel_encoder->needs_tv_clock)
e2f0ba97 5330 is_tv = true;
79e53945 5331 break;
79e53945
JB		 5332 case INTEL_OUTPUT_TVOUT:
5333 is_tv = true;
5334 break;
a4fc5ed6
KP		 5335 case INTEL_OUTPUT_DISPLAYPORT:
5336 is_dp = true;
5337 break;
32f9d658 5338 case INTEL_OUTPUT_EDP:
e3aef172 5339 is_dp = true;
de13a2e3 5340 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5341 is_cpu_edp = true;
32f9d658 5342 break;
79e53945 5343 }
43565a06 5344
c751ce4f 5345 num_connectors++;
79e53945
JB		 5346 }
5347
c1858123 5348 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5349 factor = 21;
5350 if (is_lvds) {
5351 if ((intel_panel_use_ssc(dev_priv) &&
5352 dev_priv->lvds_ssc_freq == 100) ||
5353 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5354 factor = 25;
5355 } else if (is_sdvo && is_tv)
5356 factor = 20;
c1858123 5357
de13a2e3 5358 if (clock->m < factor * clock->n)
8febb297 5359 fp |= FP_CB_TUNE;
2c07245f 5360
5eddb70b 5361 dpll = 0;
2c07245f 5362
a07d6787
EA		 5363 if (is_lvds)
5364 dpll |= DPLLB_MODE_LVDS;
5365 else
5366 dpll |= DPLLB_MODE_DAC_SERIAL;
5367 if (is_sdvo) {
de13a2e3 5368 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
a07d6787
EA		 5369 if (pixel_multiplier > 1) {
5370 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5371 }
a07d6787
EA		 5372 dpll |= DPLL_DVO_HIGH_SPEED;
5373 }
e3aef172 5374 if (is_dp && !is_cpu_edp)
a07d6787 5375 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5376
a07d6787 5377 /* compute bitmask from p1 value */
de13a2e3 5378 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5379 /* also FPA1 */
de13a2e3 5380 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5381
de13a2e3 5382 switch (clock->p2) {
a07d6787
EA		 5383 case 5:
5384 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5385 break;
5386 case 7:
5387 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5388 break;
5389 case 10:
5390 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5391 break;
5392 case 14:
5393 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5394 break;
79e53945
JB		 5395 }
5396
43565a06
KH		 5397 if (is_sdvo && is_tv)
5398 dpll |= PLL_REF_INPUT_TVCLKINBC;
5399 else if (is_tv)
79e53945 5400 /* XXX: just matching BIOS for now */
43565a06 5401 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5402 dpll |= 3;
a7615030 5403 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5404 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5405 else
5406 dpll |= PLL_REF_INPUT_DREFCLK;
5407
de13a2e3
PZ		 5408 return dpll;
5409}
5410
5411static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5412 struct drm_display_mode *mode,
5413 struct drm_display_mode *adjusted_mode,
5414 int x, int y,
5415 struct drm_framebuffer *fb)
5416{
5417 struct drm_device *dev = crtc->dev;
5418 struct drm_i915_private *dev_priv = dev->dev_private;
5419 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5420 int pipe = intel_crtc->pipe;
5421 int plane = intel_crtc->plane;
5422 int num_connectors = 0;
5423 intel_clock_t clock, reduced_clock;
5424 u32 dpll, fp = 0, fp2 = 0;
e2f12b07
PZ		 5425 bool ok, has_reduced_clock = false;
5426 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
de13a2e3
PZ		 5427 struct intel_encoder *encoder;
5428 u32 temp;
5429 int ret;
01a415fd 5430 bool dither, fdi_config_ok;
de13a2e3
PZ		 5431
5432 for_each_encoder_on_crtc(dev, crtc, encoder) {
5433 switch (encoder->type) {
5434 case INTEL_OUTPUT_LVDS:
5435 is_lvds = true;
5436 break;
de13a2e3
PZ		 5437 case INTEL_OUTPUT_DISPLAYPORT:
5438 is_dp = true;
5439 break;
5440 case INTEL_OUTPUT_EDP:
5441 is_dp = true;
e2f12b07 5442 if (!intel_encoder_is_pch_edp(&encoder->base))
de13a2e3
PZ		 5443 is_cpu_edp = true;
5444 break;
5445 }
5446
5447 num_connectors++;
5448 }
5449
5dc5298b
PZ		 5450 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5451 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5452
de13a2e3
PZ		 5453 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5454 &has_reduced_clock, &reduced_clock);
5455 if (!ok) {
5456 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5457 return -EINVAL;
5458 }
5459
5460 /* Ensure that the cursor is valid for the new mode before changing... */
5461 intel_crtc_update_cursor(crtc, true);
5462
5463 /* determine panel color depth */
c8241969
JN		 5464 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5465 adjusted_mode);
de13a2e3
PZ		 5466 if (is_lvds && dev_priv->lvds_dither)
5467 dither = true;
5468
5469 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5470 if (has_reduced_clock)
5471 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5472 reduced_clock.m2;
5473
5474 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5475
f7cb34d4 5476 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5477 drm_mode_debug_printmodeline(mode);
5478
5dc5298b
PZ		 5479 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5480 if (!is_cpu_edp) {
ee7b9f93 5481 struct intel_pch_pll *pll;
4b645f14 5482
ee7b9f93
JB		 5483 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5484 if (pll == NULL) {
5485 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5486 pipe);
4b645f14
JB		 5487 return -EINVAL;
5488 }
ee7b9f93
JB		 5489 } else
5490 intel_put_pch_pll(intel_crtc);
79e53945
JB		 5491
5492 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5493 * This is an exception to the general rule that mode_set doesn't turn
5494 * things on.
5495 */
5496 if (is_lvds) {
fae14981 5497 temp = I915_READ(PCH_LVDS);
5eddb70b 5498 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
7885d205
JB		 5499 if (HAS_PCH_CPT(dev)) {
5500 temp &= ~PORT_TRANS_SEL_MASK;
4b645f14 5501 temp |= PORT_TRANS_SEL_CPT(pipe);
7885d205
JB		 5502 } else {
5503 if (pipe == 1)
5504 temp |= LVDS_PIPEB_SELECT;
5505 else
5506 temp &= ~LVDS_PIPEB_SELECT;
5507 }
4b645f14 5508
a3e17eb8 5509 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5510 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5511 /* Set the B0-B3 data pairs corresponding to whether we're going to
5512 * set the DPLLs for dual-channel mode or not.
5513 */
5514 if (clock.p2 == 7)
5eddb70b 5515 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5516 else
5eddb70b 5517 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5518
5519 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5520 * appropriately here, but we need to look more thoroughly into how
5521 * panels behave in the two modes.
5522 */
284d5df5 5523 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
aa9b500d 5524 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 5525 temp |= LVDS_HSYNC_POLARITY;
aa9b500d 5526 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 5527 temp |= LVDS_VSYNC_POLARITY;
fae14981 5528 I915_WRITE(PCH_LVDS, temp);
79e53945 5529 }
434ed097 5530
e3aef172 5531 if (is_dp && !is_cpu_edp) {
a4fc5ed6 5532 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 5533 } else {
8db9d77b 5534 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 5535 I915_WRITE(TRANSDATA_M1(pipe), 0);
5536 I915_WRITE(TRANSDATA_N1(pipe), 0);
5537 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5538 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 5539 }
79e53945 5540
ee7b9f93
JB		 5541 if (intel_crtc->pch_pll) {
5542 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5543
32f9d658 5544 /* Wait for the clocks to stabilize. */
ee7b9f93 5545 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5546 udelay(150);
5547
8febb297
EA		 5548 /* The pixel multiplier can only be updated once the
5549 * DPLL is enabled and the clocks are stable.
5550 *
5551 * So write it again.
5552 */
ee7b9f93 5553 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5554 }
79e53945 5555
5eddb70b 5556 intel_crtc->lowfreq_avail = false;
ee7b9f93 5557 if (intel_crtc->pch_pll) {
4b645f14 5558 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5559 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5560 intel_crtc->lowfreq_avail = true;
4b645f14 5561 } else {
ee7b9f93 5562 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5563 }
5564 }
5565
b0e77b9c 5566 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
2c07245f 5567
01a415fd
DV		 5568 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5569 * ironlake_check_fdi_lanes. */
f48d8f23 5570 ironlake_set_m_n(crtc, mode, adjusted_mode);
2c07245f 5571
01a415fd
DV		 5572 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5573
e3aef172 5574 if (is_cpu_edp)
8febb297 5575 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f 5576
c8203565 5577 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
79e53945 5578
9d0498a2 5579 intel_wait_for_vblank(dev, pipe);
79e53945 5580
a1f9e77e
PZ		 5581 /* Set up the display plane register */
5582 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5583 POSTING_READ(DSPCNTR(plane));
79e53945 5584
94352cf9 5585 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5586
5587 intel_update_watermarks(dev);
5588
1f8eeabf
ED		 5589 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5590
01a415fd 5591 return fdi_config_ok ? ret : -EINVAL;
79e53945
JB		 5592}
5593
09b4ddf9
PZ		 5594static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5595 struct drm_display_mode *mode,
5596 struct drm_display_mode *adjusted_mode,
5597 int x, int y,
5598 struct drm_framebuffer *fb)
5599{
5600 struct drm_device *dev = crtc->dev;
5601 struct drm_i915_private *dev_priv = dev->dev_private;
5602 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5603 int pipe = intel_crtc->pipe;
5604 int plane = intel_crtc->plane;
5605 int num_connectors = 0;
5606 intel_clock_t clock, reduced_clock;
5dc5298b 5607 u32 dpll = 0, fp = 0, fp2 = 0;
09b4ddf9
PZ		 5608 bool ok, has_reduced_clock = false;
5609 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5610 struct intel_encoder *encoder;
5611 u32 temp;
5612 int ret;
5613 bool dither;
5614
5615 for_each_encoder_on_crtc(dev, crtc, encoder) {
5616 switch (encoder->type) {
5617 case INTEL_OUTPUT_LVDS:
5618 is_lvds = true;
5619 break;
5620 case INTEL_OUTPUT_DISPLAYPORT:
5621 is_dp = true;
5622 break;
5623 case INTEL_OUTPUT_EDP:
5624 is_dp = true;
5625 if (!intel_encoder_is_pch_edp(&encoder->base))
5626 is_cpu_edp = true;
5627 break;
5628 }
5629
5630 num_connectors++;
5631 }
5632
a5c961d1
PZ		 5633 if (is_cpu_edp)
5634 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5635 else
5636 intel_crtc->cpu_transcoder = pipe;
5637
5dc5298b
PZ		 5638 /* We are not sure yet this won't happen. */
5639 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5640 INTEL_PCH_TYPE(dev));
5641
5642 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5643 num_connectors, pipe_name(pipe));
5644
702e7a56 5645 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
1ce42920
PZ		 5646 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5647
5648 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5649
6441ab5f
PZ		 5650 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5651 return -EINVAL;
5652
5dc5298b
PZ		 5653 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5654 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5655 &has_reduced_clock,
5656 &reduced_clock);
5657 if (!ok) {
5658 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5659 return -EINVAL;
5660 }
09b4ddf9
PZ		 5661 }
5662
5663 /* Ensure that the cursor is valid for the new mode before changing... */
5664 intel_crtc_update_cursor(crtc, true);
5665
5666 /* determine panel color depth */
c8241969
JN		 5667 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5668 adjusted_mode);
09b4ddf9
PZ		 5669 if (is_lvds && dev_priv->lvds_dither)
5670 dither = true;
5671
09b4ddf9
PZ		 5672 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5673 drm_mode_debug_printmodeline(mode);
5674
5dc5298b
PZ		 5675 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5676 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5677 if (has_reduced_clock)
5678 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5679 reduced_clock.m2;
5680
5681 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5682 fp);
5683
5684 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5685 * own on pre-Haswell/LPT generation */
5686 if (!is_cpu_edp) {
5687 struct intel_pch_pll *pll;
5688
5689 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5690 if (pll == NULL) {
5691 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5692 pipe);
5693 return -EINVAL;
5694 }
5695 } else
5696 intel_put_pch_pll(intel_crtc);
09b4ddf9 5697
5dc5298b
PZ		 5698 /* The LVDS pin pair needs to be on before the DPLLs are
5699 * enabled. This is an exception to the general rule that
5700 * mode_set doesn't turn things on.
5701 */
5702 if (is_lvds) {
5703 temp = I915_READ(PCH_LVDS);
5704 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5705 if (HAS_PCH_CPT(dev)) {
5706 temp &= ~PORT_TRANS_SEL_MASK;
5707 temp |= PORT_TRANS_SEL_CPT(pipe);
5708 } else {
5709 if (pipe == 1)
5710 temp |= LVDS_PIPEB_SELECT;
5711 else
5712 temp &= ~LVDS_PIPEB_SELECT;
5713 }
09b4ddf9 5714
5dc5298b
PZ		 5715 /* set the corresponsding LVDS_BORDER bit */
5716 temp |= dev_priv->lvds_border_bits;
5717 /* Set the B0-B3 data pairs corresponding to whether
5718 * we're going to set the DPLLs for dual-channel mode or
5719 * not.
5720 */
5721 if (clock.p2 == 7)
5722 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
09b4ddf9 5723 else
5dc5298b
PZ		 5724 temp &= ~(LVDS_B0B3_POWER_UP |
5725 LVDS_CLKB_POWER_UP);
5726
5727 /* It would be nice to set 24 vs 18-bit mode
5728 * (LVDS_A3_POWER_UP) appropriately here, but we need to
5729 * look more thoroughly into how panels behave in the
5730 * two modes.
5731 */
5732 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5733 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5734 temp |= LVDS_HSYNC_POLARITY;
5735 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5736 temp |= LVDS_VSYNC_POLARITY;
5737 I915_WRITE(PCH_LVDS, temp);
09b4ddf9 5738 }
09b4ddf9
PZ		 5739 }
5740
5741 if (is_dp && !is_cpu_edp) {
5742 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5743 } else {
5dc5298b
PZ		 5744 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5745 /* For non-DP output, clear any trans DP clock recovery
5746 * setting.*/
5747 I915_WRITE(TRANSDATA_M1(pipe), 0);
5748 I915_WRITE(TRANSDATA_N1(pipe), 0);
5749 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5750 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5751 }
09b4ddf9
PZ		 5752 }
5753
5754 intel_crtc->lowfreq_avail = false;
5dc5298b
PZ		 5755 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5756 if (intel_crtc->pch_pll) {
5757 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5758
5759 /* Wait for the clocks to stabilize. */
5760 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5761 udelay(150);
5762
5763 /* The pixel multiplier can only be updated once the
5764 * DPLL is enabled and the clocks are stable.
5765 *
5766 * So write it again.
5767 */
5768 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5769 }
5770
5771 if (intel_crtc->pch_pll) {
5772 if (is_lvds && has_reduced_clock && i915_powersave) {
5773 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5774 intel_crtc->lowfreq_avail = true;
5775 } else {
5776 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5777 }
09b4ddf9
PZ		 5778 }
5779 }
5780
5781 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5782
1eb8dfec
PZ		 5783 if (!is_dp || is_cpu_edp)
5784 ironlake_set_m_n(crtc, mode, adjusted_mode);
09b4ddf9 5785
5dc5298b
PZ		 5786 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5787 if (is_cpu_edp)
5788 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
09b4ddf9 5789
ee2b0b38 5790 haswell_set_pipeconf(crtc, adjusted_mode, dither);
09b4ddf9 5791
09b4ddf9
PZ		 5792 /* Set up the display plane register */
5793 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5794 POSTING_READ(DSPCNTR(plane));
5795
5796 ret = intel_pipe_set_base(crtc, x, y, fb);
5797
5798 intel_update_watermarks(dev);
5799
5800 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5801
5802 return ret;
5803}
5804
f564048e
EA		 5805static int intel_crtc_mode_set(struct drm_crtc *crtc,
5806 struct drm_display_mode *mode,
5807 struct drm_display_mode *adjusted_mode,
5808 int x, int y,
94352cf9 5809 struct drm_framebuffer *fb)
f564048e
EA		 5810{
5811 struct drm_device *dev = crtc->dev;
5812 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 5813 struct drm_encoder_helper_funcs *encoder_funcs;
5814 struct intel_encoder *encoder;
0b701d27
EA		 5815 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5816 int pipe = intel_crtc->pipe;
f564048e
EA		 5817 int ret;
5818
0b701d27 5819 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5820
f564048e 5821 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
94352cf9 5822 x, y, fb);
79e53945 5823 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5824
9256aa19
DV		 5825 if (ret != 0)
5826 return ret;
5827
5828 for_each_encoder_on_crtc(dev, crtc, encoder) {
5829 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5830 encoder->base.base.id,
5831 drm_get_encoder_name(&encoder->base),
5832 mode->base.id, mode->name);
5833 encoder_funcs = encoder->base.helper_private;
5834 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5835 }
5836
5837 return 0;
79e53945
JB		 5838}
5839
3a9627f4
WF		 5840static bool intel_eld_uptodate(struct drm_connector *connector,
5841 int reg_eldv, uint32_t bits_eldv,
5842 int reg_elda, uint32_t bits_elda,
5843 int reg_edid)
5844{
5845 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5846 uint8_t *eld = connector->eld;
5847 uint32_t i;
5848
5849 i = I915_READ(reg_eldv);
5850 i &= bits_eldv;
5851
5852 if (!eld[0])
5853 return !i;
5854
5855 if (!i)
5856 return false;
5857
5858 i = I915_READ(reg_elda);
5859 i &= ~bits_elda;
5860 I915_WRITE(reg_elda, i);
5861
5862 for (i = 0; i < eld[2]; i++)
5863 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5864 return false;
5865
5866 return true;
5867}
5868
e0dac65e
WF		 5869static void g4x_write_eld(struct drm_connector *connector,
5870 struct drm_crtc *crtc)
5871{
5872 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5873 uint8_t *eld = connector->eld;
5874 uint32_t eldv;
5875 uint32_t len;
5876 uint32_t i;
5877
5878 i = I915_READ(G4X_AUD_VID_DID);
5879
5880 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5881 eldv = G4X_ELDV_DEVCL_DEVBLC;
5882 else
5883 eldv = G4X_ELDV_DEVCTG;
5884
3a9627f4
WF		 5885 if (intel_eld_uptodate(connector,
5886 G4X_AUD_CNTL_ST, eldv,
5887 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5888 G4X_HDMIW_HDMIEDID))
5889 return;
5890
e0dac65e
WF		 5891 i = I915_READ(G4X_AUD_CNTL_ST);
5892 i &= ~(eldv | G4X_ELD_ADDR);
5893 len = (i >> 9) & 0x1f; /* ELD buffer size */
5894 I915_WRITE(G4X_AUD_CNTL_ST, i);
5895
5896 if (!eld[0])
5897 return;
5898
5899 len = min_t(uint8_t, eld[2], len);
5900 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5901 for (i = 0; i < len; i++)
5902 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5903
5904 i = I915_READ(G4X_AUD_CNTL_ST);
5905 i |= eldv;
5906 I915_WRITE(G4X_AUD_CNTL_ST, i);
5907}
5908
83358c85
WX		 5909static void haswell_write_eld(struct drm_connector *connector,
5910 struct drm_crtc *crtc)
5911{
5912 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5913 uint8_t *eld = connector->eld;
5914 struct drm_device *dev = crtc->dev;
5915 uint32_t eldv;
5916 uint32_t i;
5917 int len;
5918 int pipe = to_intel_crtc(crtc)->pipe;
5919 int tmp;
5920
5921 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5922 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5923 int aud_config = HSW_AUD_CFG(pipe);
5924 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5925
5926
5927 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5928
5929 /* Audio output enable */
5930 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5931 tmp = I915_READ(aud_cntrl_st2);
5932 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5933 I915_WRITE(aud_cntrl_st2, tmp);
5934
5935 /* Wait for 1 vertical blank */
5936 intel_wait_for_vblank(dev, pipe);
5937
5938 /* Set ELD valid state */
5939 tmp = I915_READ(aud_cntrl_st2);
5940 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5941 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5942 I915_WRITE(aud_cntrl_st2, tmp);
5943 tmp = I915_READ(aud_cntrl_st2);
5944 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5945
5946 /* Enable HDMI mode */
5947 tmp = I915_READ(aud_config);
5948 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5949 /* clear N_programing_enable and N_value_index */
5950 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5951 I915_WRITE(aud_config, tmp);
5952
5953 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5954
5955 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5956
5957 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5958 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5959 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5960 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5961 } else
5962 I915_WRITE(aud_config, 0);
5963
5964 if (intel_eld_uptodate(connector,
5965 aud_cntrl_st2, eldv,
5966 aud_cntl_st, IBX_ELD_ADDRESS,
5967 hdmiw_hdmiedid))
5968 return;
5969
5970 i = I915_READ(aud_cntrl_st2);
5971 i &= ~eldv;
5972 I915_WRITE(aud_cntrl_st2, i);
5973
5974 if (!eld[0])
5975 return;
5976
5977 i = I915_READ(aud_cntl_st);
5978 i &= ~IBX_ELD_ADDRESS;
5979 I915_WRITE(aud_cntl_st, i);
5980 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5981 DRM_DEBUG_DRIVER("port num:%d\n", i);
5982
5983 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5984 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5985 for (i = 0; i < len; i++)
5986 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5987
5988 i = I915_READ(aud_cntrl_st2);
5989 i |= eldv;
5990 I915_WRITE(aud_cntrl_st2, i);
5991
5992}
5993
e0dac65e
WF		 5994static void ironlake_write_eld(struct drm_connector *connector,
5995 struct drm_crtc *crtc)
5996{
5997 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5998 uint8_t *eld = connector->eld;
5999 uint32_t eldv;
6000 uint32_t i;
6001 int len;
6002 int hdmiw_hdmiedid;
b6daa025 6003 int aud_config;
e0dac65e
WF		 6004 int aud_cntl_st;
6005 int aud_cntrl_st2;
9b138a83 6006 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6007
b3f33cbf 6008 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6009 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6010 aud_config = IBX_AUD_CFG(pipe);
6011 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6012 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6013 } else {
9b138a83
WX		 6014 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6015 aud_config = CPT_AUD_CFG(pipe);
6016 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6017 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6018 }
6019
9b138a83 6020 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6021
6022 i = I915_READ(aud_cntl_st);
9b138a83 6023 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6024 if (!i) {
6025 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6026 /* operate blindly on all ports */
1202b4c6
WF		 6027 eldv = IBX_ELD_VALIDB;
6028 eldv |= IBX_ELD_VALIDB << 4;
6029 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 6030 } else {
6031 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 6032 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6033 }
6034
3a9627f4
WF		 6035 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6036 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6037 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6038 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6039 } else
6040 I915_WRITE(aud_config, 0);
e0dac65e 6041
3a9627f4
WF		 6042 if (intel_eld_uptodate(connector,
6043 aud_cntrl_st2, eldv,
6044 aud_cntl_st, IBX_ELD_ADDRESS,
6045 hdmiw_hdmiedid))
6046 return;
6047
e0dac65e
WF		 6048 i = I915_READ(aud_cntrl_st2);
6049 i &= ~eldv;
6050 I915_WRITE(aud_cntrl_st2, i);
6051
6052 if (!eld[0])
6053 return;
6054
e0dac65e 6055 i = I915_READ(aud_cntl_st);
1202b4c6 6056 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6057 I915_WRITE(aud_cntl_st, i);
6058
6059 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6060 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6061 for (i = 0; i < len; i++)
6062 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6063
6064 i = I915_READ(aud_cntrl_st2);
6065 i |= eldv;
6066 I915_WRITE(aud_cntrl_st2, i);
6067}
6068
6069void intel_write_eld(struct drm_encoder *encoder,
6070 struct drm_display_mode *mode)
6071{
6072 struct drm_crtc *crtc = encoder->crtc;
6073 struct drm_connector *connector;
6074 struct drm_device *dev = encoder->dev;
6075 struct drm_i915_private *dev_priv = dev->dev_private;
6076
6077 connector = drm_select_eld(encoder, mode);
6078 if (!connector)
6079 return;
6080
6081 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6082 connector->base.id,
6083 drm_get_connector_name(connector),
6084 connector->encoder->base.id,
6085 drm_get_encoder_name(connector->encoder));
6086
6087 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6088
6089 if (dev_priv->display.write_eld)
6090 dev_priv->display.write_eld(connector, crtc);
6091}
6092
79e53945
JB		 6093/** Loads the palette/gamma unit for the CRTC with the prepared values */
6094void intel_crtc_load_lut(struct drm_crtc *crtc)
6095{
6096 struct drm_device *dev = crtc->dev;
6097 struct drm_i915_private *dev_priv = dev->dev_private;
6098 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6099 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6100 int i;
6101
6102 /* The clocks have to be on to load the palette. */
aed3f09d 6103 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6104 return;
6105
f2b115e6 6106 /* use legacy palette for Ironlake */
bad720ff 6107 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6108 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6109
79e53945
JB		 6110 for (i = 0; i < 256; i++) {
6111 I915_WRITE(palreg + 4 * i,
6112 (intel_crtc->lut_r[i] << 16) |
6113 (intel_crtc->lut_g[i] << 8) |
6114 intel_crtc->lut_b[i]);
6115 }
6116}
6117
560b85bb
CW		 6118static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6119{
6120 struct drm_device *dev = crtc->dev;
6121 struct drm_i915_private *dev_priv = dev->dev_private;
6122 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6123 bool visible = base != 0;
6124 u32 cntl;
6125
6126 if (intel_crtc->cursor_visible == visible)
6127 return;
6128
9db4a9c7 6129 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6130 if (visible) {
6131 /* On these chipsets we can only modify the base whilst
6132 * the cursor is disabled.
6133 */
9db4a9c7 6134 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6135
6136 cntl &= ~(CURSOR_FORMAT_MASK);
6137 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6138 cntl |= CURSOR_ENABLE |
6139 CURSOR_GAMMA_ENABLE |
6140 CURSOR_FORMAT_ARGB;
6141 } else
6142 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6143 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6144
6145 intel_crtc->cursor_visible = visible;
6146}
6147
6148static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6149{
6150 struct drm_device *dev = crtc->dev;
6151 struct drm_i915_private *dev_priv = dev->dev_private;
6152 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6153 int pipe = intel_crtc->pipe;
6154 bool visible = base != 0;
6155
6156 if (intel_crtc->cursor_visible != visible) {
548f245b 6157 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6158 if (base) {
6159 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6160 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6161 cntl |= pipe << 28; /* Connect to correct pipe */
6162 } else {
6163 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6164 cntl |= CURSOR_MODE_DISABLE;
6165 }
9db4a9c7 6166 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6167
6168 intel_crtc->cursor_visible = visible;
6169 }
6170 /* and commit changes on next vblank */
9db4a9c7 6171 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6172}
6173
65a21cd6
JB		 6174static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6175{
6176 struct drm_device *dev = crtc->dev;
6177 struct drm_i915_private *dev_priv = dev->dev_private;
6178 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6179 int pipe = intel_crtc->pipe;
6180 bool visible = base != 0;
6181
6182 if (intel_crtc->cursor_visible != visible) {
6183 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6184 if (base) {
6185 cntl &= ~CURSOR_MODE;
6186 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6187 } else {
6188 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6189 cntl |= CURSOR_MODE_DISABLE;
6190 }
6191 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6192
6193 intel_crtc->cursor_visible = visible;
6194 }
6195 /* and commit changes on next vblank */
6196 I915_WRITE(CURBASE_IVB(pipe), base);
6197}
6198
cda4b7d3 6199/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6200static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6201 bool on)
cda4b7d3
CW		 6202{
6203 struct drm_device *dev = crtc->dev;
6204 struct drm_i915_private *dev_priv = dev->dev_private;
6205 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6206 int pipe = intel_crtc->pipe;
6207 int x = intel_crtc->cursor_x;
6208 int y = intel_crtc->cursor_y;
560b85bb 6209 u32 base, pos;
cda4b7d3
CW		 6210 bool visible;
6211
6212 pos = 0;
6213
6b383a7f 6214 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6215 base = intel_crtc->cursor_addr;
6216 if (x > (int) crtc->fb->width)
6217 base = 0;
6218
6219 if (y > (int) crtc->fb->height)
6220 base = 0;
6221 } else
6222 base = 0;
6223
6224 if (x < 0) {
6225 if (x + intel_crtc->cursor_width < 0)
6226 base = 0;
6227
6228 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6229 x = -x;
6230 }
6231 pos |= x << CURSOR_X_SHIFT;
6232
6233 if (y < 0) {
6234 if (y + intel_crtc->cursor_height < 0)
6235 base = 0;
6236
6237 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6238 y = -y;
6239 }
6240 pos |= y << CURSOR_Y_SHIFT;
6241
6242 visible = base != 0;
560b85bb 6243 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6244 return;
6245
0cd83aa9 6246 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6247 I915_WRITE(CURPOS_IVB(pipe), pos);
6248 ivb_update_cursor(crtc, base);
6249 } else {
6250 I915_WRITE(CURPOS(pipe), pos);
6251 if (IS_845G(dev) || IS_I865G(dev))
6252 i845_update_cursor(crtc, base);
6253 else
6254 i9xx_update_cursor(crtc, base);
6255 }
cda4b7d3
CW		 6256}
6257
79e53945 6258static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6259 struct drm_file *file,
79e53945
JB		 6260 uint32_t handle,
6261 uint32_t width, uint32_t height)
6262{
6263 struct drm_device *dev = crtc->dev;
6264 struct drm_i915_private *dev_priv = dev->dev_private;
6265 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6266 struct drm_i915_gem_object *obj;
cda4b7d3 6267 uint32_t addr;
3f8bc370 6268 int ret;
79e53945 6269
79e53945
JB		 6270 /* if we want to turn off the cursor ignore width and height */
6271 if (!handle) {
28c97730 6272 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6273 addr = 0;
05394f39 6274 obj = NULL;
5004417d 6275 mutex_lock(&dev->struct_mutex);
3f8bc370 6276 goto finish;
79e53945
JB		 6277 }
6278
6279 /* Currently we only support 64x64 cursors */
6280 if (width != 64 || height != 64) {
6281 DRM_ERROR("we currently only support 64x64 cursors\n");
6282 return -EINVAL;
6283 }
6284
05394f39 6285 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6286 if (&obj->base == NULL)
79e53945
JB		 6287 return -ENOENT;
6288
05394f39 6289 if (obj->base.size < width * height * 4) {
79e53945 6290 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6291 ret = -ENOMEM;
6292 goto fail;
79e53945
JB		 6293 }
6294
71acb5eb 6295 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6296 mutex_lock(&dev->struct_mutex);
b295d1b6 6297 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 6298 if (obj->tiling_mode) {
6299 DRM_ERROR("cursor cannot be tiled\n");
6300 ret = -EINVAL;
6301 goto fail_locked;
6302 }
6303
2da3b9b9 6304 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 6305 if (ret) {
6306 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6307 goto fail_locked;
e7b526bb
CW		 6308 }
6309
d9e86c0e
CW		 6310 ret = i915_gem_object_put_fence(obj);
6311 if (ret) {
2da3b9b9 6312 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6313 goto fail_unpin;
6314 }
6315
05394f39 6316 addr = obj->gtt_offset;
71acb5eb 6317 } else {
6eeefaf3 6318 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6319 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6320 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6321 align);
71acb5eb
DA		 6322 if (ret) {
6323 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6324 goto fail_locked;
71acb5eb 6325 }
05394f39 6326 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6327 }
6328
a6c45cf0 6329 if (IS_GEN2(dev))
14b60391
JB		 6330 I915_WRITE(CURSIZE, (height << 12) | width);
6331
3f8bc370 6332 finish:
3f8bc370 6333 if (intel_crtc->cursor_bo) {
b295d1b6 6334 if (dev_priv->info->cursor_needs_physical) {
05394f39 6335 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6336 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6337 } else
6338 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6339 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6340 }
80824003 6341
7f9872e0 6342 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6343
6344 intel_crtc->cursor_addr = addr;
05394f39 6345 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6346 intel_crtc->cursor_width = width;
6347 intel_crtc->cursor_height = height;
6348
6b383a7f 6349 intel_crtc_update_cursor(crtc, true);
3f8bc370 6350
79e53945 6351 return 0;
e7b526bb 6352fail_unpin:
05394f39 6353 i915_gem_object_unpin(obj);
7f9872e0 6354fail_locked:
34b8686e 6355 mutex_unlock(&dev->struct_mutex);
bc9025bd 6356fail:
05394f39 6357 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6358 return ret;
79e53945
JB		 6359}
6360
6361static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6362{
79e53945 6363 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6364
cda4b7d3
CW		 6365 intel_crtc->cursor_x = x;
6366 intel_crtc->cursor_y = y;
652c393a 6367
6b383a7f 6368 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6369
6370 return 0;
6371}
6372
6373/** Sets the color ramps on behalf of RandR */
6374void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6375 u16 blue, int regno)
6376{
6377 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6378
6379 intel_crtc->lut_r[regno] = red >> 8;
6380 intel_crtc->lut_g[regno] = green >> 8;
6381 intel_crtc->lut_b[regno] = blue >> 8;
6382}
6383
b8c00ac5
DA		 6384void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6385 u16 *blue, int regno)
6386{
6387 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6388
6389 *red = intel_crtc->lut_r[regno] << 8;
6390 *green = intel_crtc->lut_g[regno] << 8;
6391 *blue = intel_crtc->lut_b[regno] << 8;
6392}
6393
79e53945 6394static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6395 u16 *blue, uint32_t start, uint32_t size)
79e53945 6396{
7203425a 6397 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6398 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6399
7203425a 6400 for (i = start; i < end; i++) {
79e53945
JB		 6401 intel_crtc->lut_r[i] = red[i] >> 8;
6402 intel_crtc->lut_g[i] = green[i] >> 8;
6403 intel_crtc->lut_b[i] = blue[i] >> 8;
6404 }
6405
6406 intel_crtc_load_lut(crtc);
6407}
6408
6409/**
6410 * Get a pipe with a simple mode set on it for doing load-based monitor
6411 * detection.
6412 *
6413 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 6414 * its requirements. The pipe will be connected to no other encoders.
79e53945 6415 *
c751ce4f 6416 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 6417 * configured for it. In the future, it could choose to temporarily disable
6418 * some outputs to free up a pipe for its use.
6419 *
6420 * \return crtc, or NULL if no pipes are available.
6421 */
6422
6423/* VESA 640x480x72Hz mode to set on the pipe */
6424static struct drm_display_mode load_detect_mode = {
6425 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6426 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6427};
6428
d2dff872
CW		 6429static struct drm_framebuffer *
6430intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6431 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6432 struct drm_i915_gem_object *obj)
6433{
6434 struct intel_framebuffer *intel_fb;
6435 int ret;
6436
6437 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6438 if (!intel_fb) {
6439 drm_gem_object_unreference_unlocked(&obj->base);
6440 return ERR_PTR(-ENOMEM);
6441 }
6442
6443 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6444 if (ret) {
6445 drm_gem_object_unreference_unlocked(&obj->base);
6446 kfree(intel_fb);
6447 return ERR_PTR(ret);
6448 }
6449
6450 return &intel_fb->base;
6451}
6452
6453static u32
6454intel_framebuffer_pitch_for_width(int width, int bpp)
6455{
6456 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6457 return ALIGN(pitch, 64);
6458}
6459
6460static u32
6461intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6462{
6463 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6464 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6465}
6466
6467static struct drm_framebuffer *
6468intel_framebuffer_create_for_mode(struct drm_device *dev,
6469 struct drm_display_mode *mode,
6470 int depth, int bpp)
6471{
6472 struct drm_i915_gem_object *obj;
308e5bcb 6473 struct drm_mode_fb_cmd2 mode_cmd;
d2dff872
CW		 6474
6475 obj = i915_gem_alloc_object(dev,
6476 intel_framebuffer_size_for_mode(mode, bpp));
6477 if (obj == NULL)
6478 return ERR_PTR(-ENOMEM);
6479
6480 mode_cmd.width = mode->hdisplay;
6481 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6482 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6483 bpp);
5ca0c34a 6484 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6485
6486 return intel_framebuffer_create(dev, &mode_cmd, obj);
6487}
6488
6489static struct drm_framebuffer *
6490mode_fits_in_fbdev(struct drm_device *dev,
6491 struct drm_display_mode *mode)
6492{
6493 struct drm_i915_private *dev_priv = dev->dev_private;
6494 struct drm_i915_gem_object *obj;
6495 struct drm_framebuffer *fb;
6496
6497 if (dev_priv->fbdev == NULL)
6498 return NULL;
6499
6500 obj = dev_priv->fbdev->ifb.obj;
6501 if (obj == NULL)
6502 return NULL;
6503
6504 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6505 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6506 fb->bits_per_pixel))
d2dff872
CW		 6507 return NULL;
6508
01f2c773 6509 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6510 return NULL;
6511
6512 return fb;
6513}
6514
d2434ab7 6515bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6516 struct drm_display_mode *mode,
8261b191 6517 struct intel_load_detect_pipe *old)
79e53945
JB		 6518{
6519 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6520 struct intel_encoder *intel_encoder =
6521 intel_attached_encoder(connector);
79e53945 6522 struct drm_crtc *possible_crtc;
4ef69c7a 6523 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6524 struct drm_crtc *crtc = NULL;
6525 struct drm_device *dev = encoder->dev;
94352cf9 6526 struct drm_framebuffer *fb;
79e53945
JB		 6527 int i = -1;
6528
d2dff872
CW		 6529 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6530 connector->base.id, drm_get_connector_name(connector),
6531 encoder->base.id, drm_get_encoder_name(encoder));
6532
79e53945
JB		 6533 /*
6534 * Algorithm gets a little messy:
7a5e4805 6535 *
79e53945
JB		 6536 * - if the connector already has an assigned crtc, use it (but make
6537 * sure it's on first)
7a5e4805 6538 *
79e53945
JB		 6539 * - try to find the first unused crtc that can drive this connector,
6540 * and use that if we find one
79e53945
JB		 6541 */
6542
6543 /* See if we already have a CRTC for this connector */
6544 if (encoder->crtc) {
6545 crtc = encoder->crtc;
8261b191 6546
24218aac 6547 old->dpms_mode = connector->dpms;
8261b191
CW		 6548 old->load_detect_temp = false;
6549
6550 /* Make sure the crtc and connector are running */
24218aac
DV		 6551 if (connector->dpms != DRM_MODE_DPMS_ON)
6552 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6553
7173188d 6554 return true;
79e53945
JB		 6555 }
6556
6557 /* Find an unused one (if possible) */
6558 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6559 i++;
6560 if (!(encoder->possible_crtcs & (1 << i)))
6561 continue;
6562 if (!possible_crtc->enabled) {
6563 crtc = possible_crtc;
6564 break;
6565 }
79e53945
JB		 6566 }
6567
6568 /*
6569 * If we didn't find an unused CRTC, don't use any.
6570 */
6571 if (!crtc) {
7173188d
CW		 6572 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6573 return false;
79e53945
JB		 6574 }
6575
fc303101
DV		 6576 intel_encoder->new_crtc = to_intel_crtc(crtc);
6577 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6578
6579 intel_crtc = to_intel_crtc(crtc);
24218aac 6580 old->dpms_mode = connector->dpms;
8261b191 6581 old->load_detect_temp = true;
d2dff872 6582 old->release_fb = NULL;
79e53945 6583
6492711d
CW		 6584 if (!mode)
6585 mode = &load_detect_mode;
79e53945 6586
d2dff872
CW		 6587 /* We need a framebuffer large enough to accommodate all accesses
6588 * that the plane may generate whilst we perform load detection.
6589 * We can not rely on the fbcon either being present (we get called
6590 * during its initialisation to detect all boot displays, or it may
6591 * not even exist) or that it is large enough to satisfy the
6592 * requested mode.
6593 */
94352cf9
DV		 6594 fb = mode_fits_in_fbdev(dev, mode);
6595 if (fb == NULL) {
d2dff872 6596 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6597 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6598 old->release_fb = fb;
d2dff872
CW		 6599 } else
6600 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6601 if (IS_ERR(fb)) {
d2dff872 6602 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
24218aac 6603 goto fail;
79e53945 6604 }
79e53945 6605
94352cf9 6606 if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6607 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6608 if (old->release_fb)
6609 old->release_fb->funcs->destroy(old->release_fb);
24218aac 6610 goto fail;
79e53945 6611 }
7173188d 6612
79e53945 6613 /* let the connector get through one full cycle before testing */
9d0498a2 6614 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 6615
7173188d 6616 return true;
24218aac
DV		 6617fail:
6618 connector->encoder = NULL;
6619 encoder->crtc = NULL;
24218aac 6620 return false;
79e53945
JB		 6621}
6622
d2434ab7 6623void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6624 struct intel_load_detect_pipe *old)
79e53945 6625{
d2434ab7
DV		 6626 struct intel_encoder *intel_encoder =
6627 intel_attached_encoder(connector);
4ef69c7a 6628 struct drm_encoder *encoder = &intel_encoder->base;
79e53945 6629
d2dff872
CW		 6630 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6631 connector->base.id, drm_get_connector_name(connector),
6632 encoder->base.id, drm_get_encoder_name(encoder));
6633
8261b191 6634 if (old->load_detect_temp) {
fc303101
DV		 6635 struct drm_crtc *crtc = encoder->crtc;
6636
6637 to_intel_connector(connector)->new_encoder = NULL;
6638 intel_encoder->new_crtc = NULL;
6639 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872
CW		 6640
6641 if (old->release_fb)
6642 old->release_fb->funcs->destroy(old->release_fb);
6643
0622a53c 6644 return;
79e53945
JB		 6645 }
6646
c751ce4f 6647 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6648 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6649 connector->funcs->dpms(connector, old->dpms_mode);
79e53945
JB		 6650}
6651
6652/* Returns the clock of the currently programmed mode of the given pipe. */
6653static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6654{
6655 struct drm_i915_private *dev_priv = dev->dev_private;
6656 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6657 int pipe = intel_crtc->pipe;
548f245b 6658 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6659 u32 fp;
6660 intel_clock_t clock;
6661
6662 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6663 fp = I915_READ(FP0(pipe));
79e53945 6664 else
39adb7a5 6665 fp = I915_READ(FP1(pipe));
79e53945
JB		 6666
6667 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6668 if (IS_PINEVIEW(dev)) {
6669 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6670 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6671 } else {
6672 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6673 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6674 }
6675
a6c45cf0 6676 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6677 if (IS_PINEVIEW(dev))
6678 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6679 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6680 else
6681 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6682 DPLL_FPA01_P1_POST_DIV_SHIFT);
6683
6684 switch (dpll & DPLL_MODE_MASK) {
6685 case DPLLB_MODE_DAC_SERIAL:
6686 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6687 5 : 10;
6688 break;
6689 case DPLLB_MODE_LVDS:
6690 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6691 7 : 14;
6692 break;
6693 default:
28c97730 6694 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6695 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6696 return 0;
6697 }
6698
6699 /* XXX: Handle the 100Mhz refclk */
2177832f 6700 intel_clock(dev, 96000, &clock);
79e53945
JB		 6701 } else {
6702 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6703
6704 if (is_lvds) {
6705 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6706 DPLL_FPA01_P1_POST_DIV_SHIFT);
6707 clock.p2 = 14;
6708
6709 if ((dpll & PLL_REF_INPUT_MASK) ==
6710 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6711 /* XXX: might not be 66MHz */
2177832f 6712 intel_clock(dev, 66000, &clock);
79e53945 6713 } else
2177832f 6714 intel_clock(dev, 48000, &clock);
79e53945
JB		 6715 } else {
6716 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6717 clock.p1 = 2;
6718 else {
6719 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6720 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6721 }
6722 if (dpll & PLL_P2_DIVIDE_BY_4)
6723 clock.p2 = 4;
6724 else
6725 clock.p2 = 2;
6726
2177832f 6727 intel_clock(dev, 48000, &clock);
79e53945
JB		 6728 }
6729 }
6730
6731 /* XXX: It would be nice to validate the clocks, but we can't reuse
6732 * i830PllIsValid() because it relies on the xf86_config connector
6733 * configuration being accurate, which it isn't necessarily.
6734 */
6735
6736 return clock.dot;
6737}
6738
6739/** Returns the currently programmed mode of the given pipe. */
6740struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6741 struct drm_crtc *crtc)
6742{
548f245b 6743 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6744 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fe2b8f9d 6745 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
79e53945 6746 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6747 int htot = I915_READ(HTOTAL(cpu_transcoder));
6748 int hsync = I915_READ(HSYNC(cpu_transcoder));
6749 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6750 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6751
6752 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6753 if (!mode)
6754 return NULL;
6755
6756 mode->clock = intel_crtc_clock_get(dev, crtc);
6757 mode->hdisplay = (htot & 0xffff) + 1;
6758 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6759 mode->hsync_start = (hsync & 0xffff) + 1;
6760 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6761 mode->vdisplay = (vtot & 0xffff) + 1;
6762 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6763 mode->vsync_start = (vsync & 0xffff) + 1;
6764 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6765
6766 drm_mode_set_name(mode);
79e53945
JB		 6767
6768 return mode;
6769}
6770
3dec0095 6771static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6772{
6773 struct drm_device *dev = crtc->dev;
6774 drm_i915_private_t *dev_priv = dev->dev_private;
6775 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6776 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6777 int dpll_reg = DPLL(pipe);
6778 int dpll;
652c393a 6779
bad720ff 6780 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6781 return;
6782
6783 if (!dev_priv->lvds_downclock_avail)
6784 return;
6785
dbdc6479 6786 dpll = I915_READ(dpll_reg);
652c393a 6787 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6788 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6789
8ac5a6d5 6790 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6791
6792 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6793 I915_WRITE(dpll_reg, dpll);
9d0498a2 6794 intel_wait_for_vblank(dev, pipe);
dbdc6479 6795
652c393a
JB		 6796 dpll = I915_READ(dpll_reg);
6797 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6798 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6799 }
652c393a
JB		 6800}
6801
6802static void intel_decrease_pllclock(struct drm_crtc *crtc)
6803{
6804 struct drm_device *dev = crtc->dev;
6805 drm_i915_private_t *dev_priv = dev->dev_private;
6806 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6807
bad720ff 6808 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6809 return;
6810
6811 if (!dev_priv->lvds_downclock_avail)
6812 return;
6813
6814 /*
6815 * Since this is called by a timer, we should never get here in
6816 * the manual case.
6817 */
6818 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6819 int pipe = intel_crtc->pipe;
6820 int dpll_reg = DPLL(pipe);
6821 int dpll;
f6e5b160 6822
44d98a61 6823 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6824
8ac5a6d5 6825 assert_panel_unlocked(dev_priv, pipe);
652c393a 6826
dc257cf1 6827 dpll = I915_READ(dpll_reg);
652c393a
JB		 6828 dpll |= DISPLAY_RATE_SELECT_FPA1;
6829 I915_WRITE(dpll_reg, dpll);
9d0498a2 6830 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6831 dpll = I915_READ(dpll_reg);
6832 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6833 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6834 }
6835
6836}
6837
f047e395
CW		 6838void intel_mark_busy(struct drm_device *dev)
6839{
f047e395
CW		 6840 i915_update_gfx_val(dev->dev_private);
6841}
6842
6843void intel_mark_idle(struct drm_device *dev)
652c393a 6844{
f047e395
CW		 6845}
6846
6847void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6848{
6849 struct drm_device *dev = obj->base.dev;
652c393a 6850 struct drm_crtc *crtc;
652c393a
JB		 6851
6852 if (!i915_powersave)
6853 return;
6854
652c393a 6855 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6856 if (!crtc->fb)
6857 continue;
6858
f047e395
CW		 6859 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6860 intel_increase_pllclock(crtc);
652c393a 6861 }
652c393a
JB		 6862}
6863
f047e395 6864void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
652c393a 6865{
f047e395
CW		 6866 struct drm_device *dev = obj->base.dev;
6867 struct drm_crtc *crtc;
652c393a 6868
f047e395 6869 if (!i915_powersave)
acb87dfb
CW		 6870 return;
6871
652c393a
JB		 6872 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6873 if (!crtc->fb)
6874 continue;
6875
f047e395
CW		 6876 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6877 intel_decrease_pllclock(crtc);
652c393a
JB		 6878 }
6879}
6880
79e53945
JB		 6881static void intel_crtc_destroy(struct drm_crtc *crtc)
6882{
6883 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6884 struct drm_device *dev = crtc->dev;
6885 struct intel_unpin_work *work;
6886 unsigned long flags;
6887
6888 spin_lock_irqsave(&dev->event_lock, flags);
6889 work = intel_crtc->unpin_work;
6890 intel_crtc->unpin_work = NULL;
6891 spin_unlock_irqrestore(&dev->event_lock, flags);
6892
6893 if (work) {
6894 cancel_work_sync(&work->work);
6895 kfree(work);
6896 }
79e53945
JB		 6897
6898 drm_crtc_cleanup(crtc);
67e77c5a 6899
79e53945
JB		 6900 kfree(intel_crtc);
6901}
6902
6b95a207
KH		 6903static void intel_unpin_work_fn(struct work_struct *__work)
6904{
6905 struct intel_unpin_work *work =
6906 container_of(__work, struct intel_unpin_work, work);
6907
6908 mutex_lock(&work->dev->struct_mutex);
1690e1eb 6909 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 6910 drm_gem_object_unreference(&work->pending_flip_obj->base);
6911 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6912
7782de3b 6913 intel_update_fbc(work->dev);
6b95a207
KH		 6914 mutex_unlock(&work->dev->struct_mutex);
6915 kfree(work);
6916}
6917
1afe3e9d 6918static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6919 struct drm_crtc *crtc)
6b95a207
KH		 6920{
6921 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6922 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6923 struct intel_unpin_work *work;
05394f39 6924 struct drm_i915_gem_object *obj;
6b95a207 6925 struct drm_pending_vblank_event *e;
95cb1b02 6926 struct timeval tvbl;
6b95a207
KH		 6927 unsigned long flags;
6928
6929 /* Ignore early vblank irqs */
6930 if (intel_crtc == NULL)
6931 return;
6932
6933 spin_lock_irqsave(&dev->event_lock, flags);
6934 work = intel_crtc->unpin_work;
6935 if (work == NULL || !work->pending) {
6936 spin_unlock_irqrestore(&dev->event_lock, flags);
6937 return;
6938 }
6939
6940 intel_crtc->unpin_work = NULL;
6b95a207
KH		 6941
6942 if (work->event) {
6943 e = work->event;
49b14a5c 6944 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df 6945
49b14a5c
MK		 6946 e->event.tv_sec = tvbl.tv_sec;
6947 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 6948
6b95a207
KH		 6949 list_add_tail(&e->base.link,
6950 &e->base.file_priv->event_list);
6951 wake_up_interruptible(&e->base.file_priv->event_wait);
6952 }
6953
0af7e4df
MK		 6954 drm_vblank_put(dev, intel_crtc->pipe);
6955
6b95a207
KH		 6956 spin_unlock_irqrestore(&dev->event_lock, flags);
6957
05394f39 6958 obj = work->old_fb_obj;
d9e86c0e 6959
e59f2bac 6960 atomic_clear_mask(1 << intel_crtc->plane,
05394f39 6961 &obj->pending_flip.counter);
d9e86c0e 6962
5bb61643 6963 wake_up(&dev_priv->pending_flip_queue);
6b95a207 6964 schedule_work(&work->work);
e5510fac
JB		 6965
6966 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6967}
6968
1afe3e9d
JB		 6969void intel_finish_page_flip(struct drm_device *dev, int pipe)
6970{
6971 drm_i915_private_t *dev_priv = dev->dev_private;
6972 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6973
49b14a5c 6974 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6975}
6976
6977void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6978{
6979 drm_i915_private_t *dev_priv = dev->dev_private;
6980 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6981
49b14a5c 6982 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6983}
6984
6b95a207
KH		 6985void intel_prepare_page_flip(struct drm_device *dev, int plane)
6986{
6987 drm_i915_private_t *dev_priv = dev->dev_private;
6988 struct intel_crtc *intel_crtc =
6989 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6990 unsigned long flags;
6991
6992 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 6993 if (intel_crtc->unpin_work) {
4e5359cd
SF		 6994 if ((++intel_crtc->unpin_work->pending) > 1)
6995 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 6996 } else {
6997 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6998 }
6b95a207
KH		 6999 spin_unlock_irqrestore(&dev->event_lock, flags);
7000}
7001
8c9f3aaf
JB		 7002static int intel_gen2_queue_flip(struct drm_device *dev,
7003 struct drm_crtc *crtc,
7004 struct drm_framebuffer *fb,
7005 struct drm_i915_gem_object *obj)
7006{
7007 struct drm_i915_private *dev_priv = dev->dev_private;
7008 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7009 u32 flip_mask;
6d90c952 7010 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7011 int ret;
7012
6d90c952 7013 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7014 if (ret)
83d4092b 7015 goto err;
8c9f3aaf 7016
6d90c952 7017 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7018 if (ret)
83d4092b 7019 goto err_unpin;
8c9f3aaf
JB		 7020
7021 /* Can't queue multiple flips, so wait for the previous
7022 * one to finish before executing the next.
7023 */
7024 if (intel_crtc->plane)
7025 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7026 else
7027 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7028 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7029 intel_ring_emit(ring, MI_NOOP);
7030 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7031 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7032 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7033 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7034 intel_ring_emit(ring, 0); /* aux display base address, unused */
7035 intel_ring_advance(ring);
83d4092b
CW		 7036 return 0;
7037
7038err_unpin:
7039 intel_unpin_fb_obj(obj);
7040err:
8c9f3aaf
JB		 7041 return ret;
7042}
7043
7044static int intel_gen3_queue_flip(struct drm_device *dev,
7045 struct drm_crtc *crtc,
7046 struct drm_framebuffer *fb,
7047 struct drm_i915_gem_object *obj)
7048{
7049 struct drm_i915_private *dev_priv = dev->dev_private;
7050 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7051 u32 flip_mask;
6d90c952 7052 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7053 int ret;
7054
6d90c952 7055 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7056 if (ret)
83d4092b 7057 goto err;
8c9f3aaf 7058
6d90c952 7059 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7060 if (ret)
83d4092b 7061 goto err_unpin;
8c9f3aaf
JB		 7062
7063 if (intel_crtc->plane)
7064 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7065 else
7066 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7067 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7068 intel_ring_emit(ring, MI_NOOP);
7069 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7070 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7071 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7072 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7073 intel_ring_emit(ring, MI_NOOP);
7074
7075 intel_ring_advance(ring);
83d4092b
CW		 7076 return 0;
7077
7078err_unpin:
7079 intel_unpin_fb_obj(obj);
7080err:
8c9f3aaf
JB		 7081 return ret;
7082}
7083
7084static int intel_gen4_queue_flip(struct drm_device *dev,
7085 struct drm_crtc *crtc,
7086 struct drm_framebuffer *fb,
7087 struct drm_i915_gem_object *obj)
7088{
7089 struct drm_i915_private *dev_priv = dev->dev_private;
7090 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7091 uint32_t pf, pipesrc;
6d90c952 7092 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7093 int ret;
7094
6d90c952 7095 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7096 if (ret)
83d4092b 7097 goto err;
8c9f3aaf 7098
6d90c952 7099 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7100 if (ret)
83d4092b 7101 goto err_unpin;
8c9f3aaf
JB		 7102
7103 /* i965+ uses the linear or tiled offsets from the
7104 * Display Registers (which do not change across a page-flip)
7105 * so we need only reprogram the base address.
7106 */
6d90c952
DV		 7107 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7108 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7109 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7110 intel_ring_emit(ring,
7111 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7112 obj->tiling_mode);
8c9f3aaf
JB		 7113
7114 /* XXX Enabling the panel-fitter across page-flip is so far
7115 * untested on non-native modes, so ignore it for now.
7116 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7117 */
7118 pf = 0;
7119 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 7120 intel_ring_emit(ring, pf | pipesrc);
7121 intel_ring_advance(ring);
83d4092b
CW		 7122 return 0;
7123
7124err_unpin:
7125 intel_unpin_fb_obj(obj);
7126err:
8c9f3aaf
JB		 7127 return ret;
7128}
7129
7130static int intel_gen6_queue_flip(struct drm_device *dev,
7131 struct drm_crtc *crtc,
7132 struct drm_framebuffer *fb,
7133 struct drm_i915_gem_object *obj)
7134{
7135 struct drm_i915_private *dev_priv = dev->dev_private;
7136 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7137 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7138 uint32_t pf, pipesrc;
7139 int ret;
7140
6d90c952 7141 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7142 if (ret)
83d4092b 7143 goto err;
8c9f3aaf 7144
6d90c952 7145 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7146 if (ret)
83d4092b 7147 goto err_unpin;
8c9f3aaf 7148
6d90c952
DV		 7149 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7150 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7151 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7152 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7153
dc257cf1
DV		 7154 /* Contrary to the suggestions in the documentation,
7155 * "Enable Panel Fitter" does not seem to be required when page
7156 * flipping with a non-native mode, and worse causes a normal
7157 * modeset to fail.
7158 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7159 */
7160 pf = 0;
8c9f3aaf 7161 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 7162 intel_ring_emit(ring, pf | pipesrc);
7163 intel_ring_advance(ring);
83d4092b
CW		 7164 return 0;
7165
7166err_unpin:
7167 intel_unpin_fb_obj(obj);
7168err:
8c9f3aaf
JB		 7169 return ret;
7170}
7171
7c9017e5
JB		 7172/*
7173 * On gen7 we currently use the blit ring because (in early silicon at least)
7174 * the render ring doesn't give us interrpts for page flip completion, which
7175 * means clients will hang after the first flip is queued. Fortunately the
7176 * blit ring generates interrupts properly, so use it instead.
7177 */
7178static int intel_gen7_queue_flip(struct drm_device *dev,
7179 struct drm_crtc *crtc,
7180 struct drm_framebuffer *fb,
7181 struct drm_i915_gem_object *obj)
7182{
7183 struct drm_i915_private *dev_priv = dev->dev_private;
7184 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7185 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7186 uint32_t plane_bit = 0;
7c9017e5
JB		 7187 int ret;
7188
7189 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7190 if (ret)
83d4092b 7191 goto err;
7c9017e5 7192
cb05d8de
DV		 7193 switch(intel_crtc->plane) {
7194 case PLANE_A:
7195 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7196 break;
7197 case PLANE_B:
7198 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7199 break;
7200 case PLANE_C:
7201 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7202 break;
7203 default:
7204 WARN_ONCE(1, "unknown plane in flip command\n");
7205 ret = -ENODEV;
ab3951eb 7206 goto err_unpin;
cb05d8de
DV		 7207 }
7208
7c9017e5
JB		 7209 ret = intel_ring_begin(ring, 4);
7210 if (ret)
83d4092b 7211 goto err_unpin;
7c9017e5 7212
cb05d8de 7213 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7214 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7215 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5
JB		 7216 intel_ring_emit(ring, (MI_NOOP));
7217 intel_ring_advance(ring);
83d4092b
CW		 7218 return 0;
7219
7220err_unpin:
7221 intel_unpin_fb_obj(obj);
7222err:
7c9017e5
JB		 7223 return ret;
7224}
7225
8c9f3aaf
JB		 7226static int intel_default_queue_flip(struct drm_device *dev,
7227 struct drm_crtc *crtc,
7228 struct drm_framebuffer *fb,
7229 struct drm_i915_gem_object *obj)
7230{
7231 return -ENODEV;
7232}
7233
6b95a207
KH		 7234static int intel_crtc_page_flip(struct drm_crtc *crtc,
7235 struct drm_framebuffer *fb,
7236 struct drm_pending_vblank_event *event)
7237{
7238 struct drm_device *dev = crtc->dev;
7239 struct drm_i915_private *dev_priv = dev->dev_private;
7240 struct intel_framebuffer *intel_fb;
05394f39 7241 struct drm_i915_gem_object *obj;
6b95a207
KH		 7242 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7243 struct intel_unpin_work *work;
8c9f3aaf 7244 unsigned long flags;
52e68630 7245 int ret;
6b95a207 7246
e6a595d2
VS		 7247 /* Can't change pixel format via MI display flips. */
7248 if (fb->pixel_format != crtc->fb->pixel_format)
7249 return -EINVAL;
7250
7251 /*
7252 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7253 * Note that pitch changes could also affect these register.
7254 */
7255 if (INTEL_INFO(dev)->gen > 3 &&
7256 (fb->offsets[0] != crtc->fb->offsets[0] ||
7257 fb->pitches[0] != crtc->fb->pitches[0]))
7258 return -EINVAL;
7259
6b95a207
KH		 7260 work = kzalloc(sizeof *work, GFP_KERNEL);
7261 if (work == NULL)
7262 return -ENOMEM;
7263
6b95a207
KH		 7264 work->event = event;
7265 work->dev = crtc->dev;
7266 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 7267 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 7268 INIT_WORK(&work->work, intel_unpin_work_fn);
7269
7317c75e
JB		 7270 ret = drm_vblank_get(dev, intel_crtc->pipe);
7271 if (ret)
7272 goto free_work;
7273
6b95a207
KH		 7274 /* We borrow the event spin lock for protecting unpin_work */
7275 spin_lock_irqsave(&dev->event_lock, flags);
7276 if (intel_crtc->unpin_work) {
7277 spin_unlock_irqrestore(&dev->event_lock, flags);
7278 kfree(work);
7317c75e 7279 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7280
7281 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7282 return -EBUSY;
7283 }
7284 intel_crtc->unpin_work = work;
7285 spin_unlock_irqrestore(&dev->event_lock, flags);
7286
7287 intel_fb = to_intel_framebuffer(fb);
7288 obj = intel_fb->obj;
7289
79158103
CW		 7290 ret = i915_mutex_lock_interruptible(dev);
7291 if (ret)
7292 goto cleanup;
6b95a207 7293
75dfca80 7294 /* Reference the objects for the scheduled work. */
05394f39
CW		 7295 drm_gem_object_reference(&work->old_fb_obj->base);
7296 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7297
7298 crtc->fb = fb;
96b099fd 7299
e1f99ce6 7300 work->pending_flip_obj = obj;
e1f99ce6 7301
4e5359cd
SF		 7302 work->enable_stall_check = true;
7303
e1f99ce6
CW		 7304 /* Block clients from rendering to the new back buffer until
7305 * the flip occurs and the object is no longer visible.
7306 */
05394f39 7307 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 7308
8c9f3aaf
JB		 7309 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7310 if (ret)
7311 goto cleanup_pending;
6b95a207 7312
7782de3b 7313 intel_disable_fbc(dev);
f047e395 7314 intel_mark_fb_busy(obj);
6b95a207
KH		 7315 mutex_unlock(&dev->struct_mutex);
7316
e5510fac
JB		 7317 trace_i915_flip_request(intel_crtc->plane, obj);
7318
6b95a207 7319 return 0;
96b099fd 7320
8c9f3aaf
JB		 7321cleanup_pending:
7322 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
05394f39
CW		 7323 drm_gem_object_unreference(&work->old_fb_obj->base);
7324 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7325 mutex_unlock(&dev->struct_mutex);
7326
79158103 7327cleanup:
96b099fd
CW		 7328 spin_lock_irqsave(&dev->event_lock, flags);
7329 intel_crtc->unpin_work = NULL;
7330 spin_unlock_irqrestore(&dev->event_lock, flags);
7331
7317c75e
JB		 7332 drm_vblank_put(dev, intel_crtc->pipe);
7333free_work:
96b099fd
CW		 7334 kfree(work);
7335
7336 return ret;
6b95a207
KH		 7337}
7338
f6e5b160 7339static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7340 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7341 .load_lut = intel_crtc_load_lut,
976f8a20 7342 .disable = intel_crtc_noop,
f6e5b160
CW		 7343};
7344
6ed0f796 7345bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7346{
6ed0f796
DV		 7347 struct intel_encoder *other_encoder;
7348 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7349
6ed0f796
DV		 7350 if (WARN_ON(!crtc))
7351 return false;
7352
7353 list_for_each_entry(other_encoder,
7354 &crtc->dev->mode_config.encoder_list,
7355 base.head) {
7356
7357 if (&other_encoder->new_crtc->base != crtc ||
7358 encoder == other_encoder)
7359 continue;
7360 else
7361 return true;
f47166d2
CW		 7362 }
7363
6ed0f796
DV		 7364 return false;
7365}
47f1c6c9 7366
50f56119
DV		 7367static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7368 struct drm_crtc *crtc)
7369{
7370 struct drm_device *dev;
7371 struct drm_crtc *tmp;
7372 int crtc_mask = 1;
47f1c6c9 7373
50f56119 7374 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7375
50f56119 7376 dev = crtc->dev;
47f1c6c9 7377
50f56119
DV		 7378 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7379 if (tmp == crtc)
7380 break;
7381 crtc_mask <<= 1;
7382 }
47f1c6c9 7383
50f56119
DV		 7384 if (encoder->possible_crtcs & crtc_mask)
7385 return true;
7386 return false;
47f1c6c9 7387}
79e53945 7388
9a935856
DV		 7389/**
7390 * intel_modeset_update_staged_output_state
7391 *
7392 * Updates the staged output configuration state, e.g. after we've read out the
7393 * current hw state.
7394 */
7395static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7396{
9a935856
DV		 7397 struct intel_encoder *encoder;
7398 struct intel_connector *connector;
f6e5b160 7399
9a935856
DV		 7400 list_for_each_entry(connector, &dev->mode_config.connector_list,
7401 base.head) {
7402 connector->new_encoder =
7403 to_intel_encoder(connector->base.encoder);
7404 }
f6e5b160 7405
9a935856
DV		 7406 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7407 base.head) {
7408 encoder->new_crtc =
7409 to_intel_crtc(encoder->base.crtc);
7410 }
f6e5b160
CW		 7411}
7412
9a935856
DV		 7413/**
7414 * intel_modeset_commit_output_state
7415 *
7416 * This function copies the stage display pipe configuration to the real one.
7417 */
7418static void intel_modeset_commit_output_state(struct drm_device *dev)
7419{
7420 struct intel_encoder *encoder;
7421 struct intel_connector *connector;
f6e5b160 7422
9a935856
DV		 7423 list_for_each_entry(connector, &dev->mode_config.connector_list,
7424 base.head) {
7425 connector->base.encoder = &connector->new_encoder->base;
7426 }
f6e5b160 7427
9a935856
DV		 7428 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7429 base.head) {
7430 encoder->base.crtc = &encoder->new_crtc->base;
7431 }
7432}
7433
7758a113
DV		 7434static struct drm_display_mode *
7435intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7436 struct drm_display_mode *mode)
ee7b9f93 7437{
7758a113
DV		 7438 struct drm_device *dev = crtc->dev;
7439 struct drm_display_mode *adjusted_mode;
7440 struct drm_encoder_helper_funcs *encoder_funcs;
7441 struct intel_encoder *encoder;
ee7b9f93 7442
7758a113
DV		 7443 adjusted_mode = drm_mode_duplicate(dev, mode);
7444 if (!adjusted_mode)
7445 return ERR_PTR(-ENOMEM);
7446
7447 /* Pass our mode to the connectors and the CRTC to give them a chance to
7448 * adjust it according to limitations or connector properties, and also
7449 * a chance to reject the mode entirely.
7450 */
7451 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7452 base.head) {
7453
7454 if (&encoder->new_crtc->base != crtc)
7455 continue;
7456 encoder_funcs = encoder->base.helper_private;
7457 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7458 adjusted_mode))) {
7459 DRM_DEBUG_KMS("Encoder fixup failed\n");
7460 goto fail;
7461 }
ee7b9f93
JB		 7462 }
7463
7758a113
DV		 7464 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7465 DRM_DEBUG_KMS("CRTC fixup failed\n");
7466 goto fail;
ee7b9f93 7467 }
7758a113
DV		 7468 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7469
7470 return adjusted_mode;
7471fail:
7472 drm_mode_destroy(dev, adjusted_mode);
7473 return ERR_PTR(-EINVAL);
ee7b9f93
JB		 7474}
7475
e2e1ed41
DV		 7476/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7477 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7478static void
7479intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7480 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7481{
7482 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7483 struct drm_device *dev = crtc->dev;
7484 struct intel_encoder *encoder;
7485 struct intel_connector *connector;
7486 struct drm_crtc *tmp_crtc;
79e53945 7487
e2e1ed41 7488 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7489
e2e1ed41
DV		 7490 /* Check which crtcs have changed outputs connected to them, these need
7491 * to be part of the prepare_pipes mask. We don't (yet) support global
7492 * modeset across multiple crtcs, so modeset_pipes will only have one
7493 * bit set at most. */
7494 list_for_each_entry(connector, &dev->mode_config.connector_list,
7495 base.head) {
7496 if (connector->base.encoder == &connector->new_encoder->base)
7497 continue;
79e53945 7498
e2e1ed41
DV		 7499 if (connector->base.encoder) {
7500 tmp_crtc = connector->base.encoder->crtc;
7501
7502 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7503 }
7504
7505 if (connector->new_encoder)
7506 *prepare_pipes |=
7507 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7508 }
7509
e2e1ed41
DV		 7510 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7511 base.head) {
7512 if (encoder->base.crtc == &encoder->new_crtc->base)
7513 continue;
7514
7515 if (encoder->base.crtc) {
7516 tmp_crtc = encoder->base.crtc;
7517
7518 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7519 }
7520
7521 if (encoder->new_crtc)
7522 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7523 }
7524
e2e1ed41
DV		 7525 /* Check for any pipes that will be fully disabled ... */
7526 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7527 base.head) {
7528 bool used = false;
22fd0fab 7529
e2e1ed41
DV		 7530 /* Don't try to disable disabled crtcs. */
7531 if (!intel_crtc->base.enabled)
7532 continue;
7e7d76c3 7533
e2e1ed41
DV		 7534 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7535 base.head) {
7536 if (encoder->new_crtc == intel_crtc)
7537 used = true;
7538 }
7539
7540 if (!used)
7541 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7542 }
7543
e2e1ed41
DV		 7544
7545 /* set_mode is also used to update properties on life display pipes. */
7546 intel_crtc = to_intel_crtc(crtc);
7547 if (crtc->enabled)
7548 *prepare_pipes |= 1 << intel_crtc->pipe;
7549
7550 /* We only support modeset on one single crtc, hence we need to do that
7551 * only for the passed in crtc iff we change anything else than just
7552 * disable crtcs.
7553 *
7554 * This is actually not true, to be fully compatible with the old crtc
7555 * helper we automatically disable _any_ output (i.e. doesn't need to be
7556 * connected to the crtc we're modesetting on) if it's disconnected.
7557 * Which is a rather nutty api (since changed the output configuration
7558 * without userspace's explicit request can lead to confusion), but
7559 * alas. Hence we currently need to modeset on all pipes we prepare. */
7560 if (*prepare_pipes)
7561 *modeset_pipes = *prepare_pipes;
7562
7563 /* ... and mask these out. */
7564 *modeset_pipes &= ~(*disable_pipes);
7565 *prepare_pipes &= ~(*disable_pipes);
7566}
7567
ea9d758d
DV		 7568static bool intel_crtc_in_use(struct drm_crtc *crtc)
7569{
7570 struct drm_encoder *encoder;
7571 struct drm_device *dev = crtc->dev;
7572
7573 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7574 if (encoder->crtc == crtc)
7575 return true;
7576
7577 return false;
7578}
7579
7580static void
7581intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7582{
7583 struct intel_encoder *intel_encoder;
7584 struct intel_crtc *intel_crtc;
7585 struct drm_connector *connector;
7586
7587 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7588 base.head) {
7589 if (!intel_encoder->base.crtc)
7590 continue;
7591
7592 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7593
7594 if (prepare_pipes & (1 << intel_crtc->pipe))
7595 intel_encoder->connectors_active = false;
7596 }
7597
7598 intel_modeset_commit_output_state(dev);
7599
7600 /* Update computed state. */
7601 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7602 base.head) {
7603 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7604 }
7605
7606 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7607 if (!connector->encoder || !connector->encoder->crtc)
7608 continue;
7609
7610 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7611
7612 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7613 struct drm_property *dpms_property =
7614 dev->mode_config.dpms_property;
7615
ea9d758d 7616 connector->dpms = DRM_MODE_DPMS_ON;
68d34720
DV		 7617 drm_connector_property_set_value(connector,
7618 dpms_property,
7619 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7620
7621 intel_encoder = to_intel_encoder(connector->encoder);
7622 intel_encoder->connectors_active = true;
7623 }
7624 }
7625
7626}
7627
25c5b266
DV		 7628#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7629 list_for_each_entry((intel_crtc), \
7630 &(dev)->mode_config.crtc_list, \
7631 base.head) \
7632 if (mask & (1 <<(intel_crtc)->pipe)) \
7633
b980514c 7634void
8af6cf88
DV		 7635intel_modeset_check_state(struct drm_device *dev)
7636{
7637 struct intel_crtc *crtc;
7638 struct intel_encoder *encoder;
7639 struct intel_connector *connector;
7640
7641 list_for_each_entry(connector, &dev->mode_config.connector_list,
7642 base.head) {
7643 /* This also checks the encoder/connector hw state with the
7644 * ->get_hw_state callbacks. */
7645 intel_connector_check_state(connector);
7646
7647 WARN(&connector->new_encoder->base != connector->base.encoder,
7648 "connector's staged encoder doesn't match current encoder\n");
7649 }
7650
7651 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7652 base.head) {
7653 bool enabled = false;
7654 bool active = false;
7655 enum pipe pipe, tracked_pipe;
7656
7657 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7658 encoder->base.base.id,
7659 drm_get_encoder_name(&encoder->base));
7660
7661 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7662 "encoder's stage crtc doesn't match current crtc\n");
7663 WARN(encoder->connectors_active && !encoder->base.crtc,
7664 "encoder's active_connectors set, but no crtc\n");
7665
7666 list_for_each_entry(connector, &dev->mode_config.connector_list,
7667 base.head) {
7668 if (connector->base.encoder != &encoder->base)
7669 continue;
7670 enabled = true;
7671 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7672 active = true;
7673 }
7674 WARN(!!encoder->base.crtc != enabled,
7675 "encoder's enabled state mismatch "
7676 "(expected %i, found %i)\n",
7677 !!encoder->base.crtc, enabled);
7678 WARN(active && !encoder->base.crtc,
7679 "active encoder with no crtc\n");
7680
7681 WARN(encoder->connectors_active != active,
7682 "encoder's computed active state doesn't match tracked active state "
7683 "(expected %i, found %i)\n", active, encoder->connectors_active);
7684
7685 active = encoder->get_hw_state(encoder, &pipe);
7686 WARN(active != encoder->connectors_active,
7687 "encoder's hw state doesn't match sw tracking "
7688 "(expected %i, found %i)\n",
7689 encoder->connectors_active, active);
7690
7691 if (!encoder->base.crtc)
7692 continue;
7693
7694 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7695 WARN(active && pipe != tracked_pipe,
7696 "active encoder's pipe doesn't match"
7697 "(expected %i, found %i)\n",
7698 tracked_pipe, pipe);
7699
7700 }
7701
7702 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7703 base.head) {
7704 bool enabled = false;
7705 bool active = false;
7706
7707 DRM_DEBUG_KMS("[CRTC:%d]\n",
7708 crtc->base.base.id);
7709
7710 WARN(crtc->active && !crtc->base.enabled,
7711 "active crtc, but not enabled in sw tracking\n");
7712
7713 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7714 base.head) {
7715 if (encoder->base.crtc != &crtc->base)
7716 continue;
7717 enabled = true;
7718 if (encoder->connectors_active)
7719 active = true;
7720 }
7721 WARN(active != crtc->active,
7722 "crtc's computed active state doesn't match tracked active state "
7723 "(expected %i, found %i)\n", active, crtc->active);
7724 WARN(enabled != crtc->base.enabled,
7725 "crtc's computed enabled state doesn't match tracked enabled state "
7726 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7727
7728 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7729 }
7730}
7731
a6778b3c
DV		 7732bool intel_set_mode(struct drm_crtc *crtc,
7733 struct drm_display_mode *mode,
94352cf9 7734 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 7735{
7736 struct drm_device *dev = crtc->dev;
dbf2b54e 7737 drm_i915_private_t *dev_priv = dev->dev_private;
a6778b3c 7738 struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
25c5b266
DV		 7739 struct intel_crtc *intel_crtc;
7740 unsigned disable_pipes, prepare_pipes, modeset_pipes;
a6778b3c
DV		 7741 bool ret = true;
7742
e2e1ed41 7743 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 7744 &prepare_pipes, &disable_pipes);
7745
7746 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7747 modeset_pipes, prepare_pipes, disable_pipes);
e2e1ed41 7748
976f8a20
DV		 7749 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7750 intel_crtc_disable(&intel_crtc->base);
87f1faa6 7751
a6778b3c
DV		 7752 saved_hwmode = crtc->hwmode;
7753 saved_mode = crtc->mode;
a6778b3c 7754
25c5b266
DV		 7755 /* Hack: Because we don't (yet) support global modeset on multiple
7756 * crtcs, we don't keep track of the new mode for more than one crtc.
7757 * Hence simply check whether any bit is set in modeset_pipes in all the
7758 * pieces of code that are not yet converted to deal with mutliple crtcs
7759 * changing their mode at the same time. */
7760 adjusted_mode = NULL;
7761 if (modeset_pipes) {
7762 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7763 if (IS_ERR(adjusted_mode)) {
7764 return false;
7765 }
25c5b266 7766 }
a6778b3c 7767
ea9d758d
DV		 7768 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7769 if (intel_crtc->base.enabled)
7770 dev_priv->display.crtc_disable(&intel_crtc->base);
7771 }
a6778b3c 7772
6c4c86f5
DV		 7773 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7774 * to set it here already despite that we pass it down the callchain.
7775 */
7776 if (modeset_pipes)
25c5b266 7777 crtc->mode = *mode;
7758a113 7778
ea9d758d
DV		 7779 /* Only after disabling all output pipelines that will be changed can we
7780 * update the the output configuration. */
7781 intel_modeset_update_state(dev, prepare_pipes);
7782
47fab737
DV		 7783 if (dev_priv->display.modeset_global_resources)
7784 dev_priv->display.modeset_global_resources(dev);
7785
a6778b3c
DV		 7786 /* Set up the DPLL and any encoders state that needs to adjust or depend
7787 * on the DPLL.
7788 */
25c5b266
DV		 7789 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7790 ret = !intel_crtc_mode_set(&intel_crtc->base,
7791 mode, adjusted_mode,
7792 x, y, fb);
7793 if (!ret)
7794 goto done;
a6778b3c
DV		 7795 }
7796
7797 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 7798 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7799 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 7800
25c5b266
DV		 7801 if (modeset_pipes) {
7802 /* Store real post-adjustment hardware mode. */
7803 crtc->hwmode = *adjusted_mode;
a6778b3c 7804
25c5b266
DV		 7805 /* Calculate and store various constants which
7806 * are later needed by vblank and swap-completion
7807 * timestamping. They are derived from true hwmode.
7808 */
7809 drm_calc_timestamping_constants(crtc);
7810 }
a6778b3c
DV		 7811
7812 /* FIXME: add subpixel order */
7813done:
7814 drm_mode_destroy(dev, adjusted_mode);
25c5b266 7815 if (!ret && crtc->enabled) {
a6778b3c
DV		 7816 crtc->hwmode = saved_hwmode;
7817 crtc->mode = saved_mode;
8af6cf88
DV		 7818 } else {
7819 intel_modeset_check_state(dev);
a6778b3c
DV		 7820 }
7821
7822 return ret;
7823}
7824
25c5b266
DV		 7825#undef for_each_intel_crtc_masked
7826
d9e55608
DV		 7827static void intel_set_config_free(struct intel_set_config *config)
7828{
7829 if (!config)
7830 return;
7831
1aa4b628
DV		 7832 kfree(config->save_connector_encoders);
7833 kfree(config->save_encoder_crtcs);
d9e55608
DV		 7834 kfree(config);
7835}
7836
85f9eb71
DV		 7837static int intel_set_config_save_state(struct drm_device *dev,
7838 struct intel_set_config *config)
7839{
85f9eb71
DV		 7840 struct drm_encoder *encoder;
7841 struct drm_connector *connector;
7842 int count;
7843
1aa4b628
DV		 7844 config->save_encoder_crtcs =
7845 kcalloc(dev->mode_config.num_encoder,
7846 sizeof(struct drm_crtc *), GFP_KERNEL);
7847 if (!config->save_encoder_crtcs)
85f9eb71
DV		 7848 return -ENOMEM;
7849
1aa4b628
DV		 7850 config->save_connector_encoders =
7851 kcalloc(dev->mode_config.num_connector,
7852 sizeof(struct drm_encoder *), GFP_KERNEL);
7853 if (!config->save_connector_encoders)
85f9eb71
DV		 7854 return -ENOMEM;
7855
7856 /* Copy data. Note that driver private data is not affected.
7857 * Should anything bad happen only the expected state is
7858 * restored, not the drivers personal bookkeeping.
7859 */
85f9eb71
DV		 7860 count = 0;
7861 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 7862 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 7863 }
7864
7865 count = 0;
7866 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 7867 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 7868 }
7869
7870 return 0;
7871}
7872
7873static void intel_set_config_restore_state(struct drm_device *dev,
7874 struct intel_set_config *config)
7875{
9a935856
DV		 7876 struct intel_encoder *encoder;
7877 struct intel_connector *connector;
85f9eb71
DV		 7878 int count;
7879
85f9eb71 7880 count = 0;
9a935856
DV		 7881 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7882 encoder->new_crtc =
7883 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 7884 }
7885
7886 count = 0;
9a935856
DV		 7887 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7888 connector->new_encoder =
7889 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 7890 }
7891}
7892
5e2b584e
DV		 7893static void
7894intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7895 struct intel_set_config *config)
7896{
7897
7898 /* We should be able to check here if the fb has the same properties
7899 * and then just flip_or_move it */
7900 if (set->crtc->fb != set->fb) {
7901 /* If we have no fb then treat it as a full mode set */
7902 if (set->crtc->fb == NULL) {
7903 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7904 config->mode_changed = true;
7905 } else if (set->fb == NULL) {
7906 config->mode_changed = true;
7907 } else if (set->fb->depth != set->crtc->fb->depth) {
7908 config->mode_changed = true;
7909 } else if (set->fb->bits_per_pixel !=
7910 set->crtc->fb->bits_per_pixel) {
7911 config->mode_changed = true;
7912 } else
7913 config->fb_changed = true;
7914 }
7915
835c5873 7916 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 7917 config->fb_changed = true;
7918
7919 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7920 DRM_DEBUG_KMS("modes are different, full mode set\n");
7921 drm_mode_debug_printmodeline(&set->crtc->mode);
7922 drm_mode_debug_printmodeline(set->mode);
7923 config->mode_changed = true;
7924 }
7925}
7926
2e431051 7927static int
9a935856
DV		 7928intel_modeset_stage_output_state(struct drm_device *dev,
7929 struct drm_mode_set *set,
7930 struct intel_set_config *config)
50f56119 7931{
85f9eb71 7932 struct drm_crtc *new_crtc;
9a935856
DV		 7933 struct intel_connector *connector;
7934 struct intel_encoder *encoder;
2e431051 7935 int count, ro;
50f56119 7936
9a935856
DV		 7937 /* The upper layers ensure that we either disabl a crtc or have a list
7938 * of connectors. For paranoia, double-check this. */
7939 WARN_ON(!set->fb && (set->num_connectors != 0));
7940 WARN_ON(set->fb && (set->num_connectors == 0));
7941
50f56119 7942 count = 0;
9a935856
DV		 7943 list_for_each_entry(connector, &dev->mode_config.connector_list,
7944 base.head) {
7945 /* Otherwise traverse passed in connector list and get encoders
7946 * for them. */
50f56119 7947 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 7948 if (set->connectors[ro] == &connector->base) {
7949 connector->new_encoder = connector->encoder;
50f56119
DV		 7950 break;
7951 }
7952 }
7953
9a935856
DV		 7954 /* If we disable the crtc, disable all its connectors. Also, if
7955 * the connector is on the changing crtc but not on the new
7956 * connector list, disable it. */
7957 if ((!set->fb || ro == set->num_connectors) &&
7958 connector->base.encoder &&
7959 connector->base.encoder->crtc == set->crtc) {
7960 connector->new_encoder = NULL;
7961
7962 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7963 connector->base.base.id,
7964 drm_get_connector_name(&connector->base));
7965 }
7966
7967
7968 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 7969 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 7970 config->mode_changed = true;
50f56119 7971 }
9a935856
DV		 7972
7973 /* Disable all disconnected encoders. */
7974 if (connector->base.status == connector_status_disconnected)
7975 connector->new_encoder = NULL;
50f56119 7976 }
9a935856 7977 /* connector->new_encoder is now updated for all connectors. */
50f56119 7978
9a935856 7979 /* Update crtc of enabled connectors. */
50f56119 7980 count = 0;
9a935856
DV		 7981 list_for_each_entry(connector, &dev->mode_config.connector_list,
7982 base.head) {
7983 if (!connector->new_encoder)
50f56119
DV		 7984 continue;
7985
9a935856 7986 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 7987
7988 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 7989 if (set->connectors[ro] == &connector->base)
50f56119
DV		 7990 new_crtc = set->crtc;
7991 }
7992
7993 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 7994 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7995 new_crtc)) {
5e2b584e 7996 return -EINVAL;
50f56119 7997 }
9a935856
DV		 7998 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7999
8000 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8001 connector->base.base.id,
8002 drm_get_connector_name(&connector->base),
8003 new_crtc->base.id);
8004 }
8005
8006 /* Check for any encoders that needs to be disabled. */
8007 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8008 base.head) {
8009 list_for_each_entry(connector,
8010 &dev->mode_config.connector_list,
8011 base.head) {
8012 if (connector->new_encoder == encoder) {
8013 WARN_ON(!connector->new_encoder->new_crtc);
8014
8015 goto next_encoder;
8016 }
8017 }
8018 encoder->new_crtc = NULL;
8019next_encoder:
8020 /* Only now check for crtc changes so we don't miss encoders
8021 * that will be disabled. */
8022 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8023 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8024 config->mode_changed = true;
50f56119
DV		 8025 }
8026 }
9a935856 8027 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8028
2e431051
DV		 8029 return 0;
8030}
8031
8032static int intel_crtc_set_config(struct drm_mode_set *set)
8033{
8034 struct drm_device *dev;
2e431051
DV		 8035 struct drm_mode_set save_set;
8036 struct intel_set_config *config;
8037 int ret;
2e431051 8038
8d3e375e
DV		 8039 BUG_ON(!set);
8040 BUG_ON(!set->crtc);
8041 BUG_ON(!set->crtc->helper_private);
2e431051
DV		 8042
8043 if (!set->mode)
8044 set->fb = NULL;
8045
431e50f7
DV		 8046 /* The fb helper likes to play gross jokes with ->mode_set_config.
8047 * Unfortunately the crtc helper doesn't do much at all for this case,
8048 * so we have to cope with this madness until the fb helper is fixed up. */
8049 if (set->fb && set->num_connectors == 0)
8050 return 0;
8051
2e431051
DV		 8052 if (set->fb) {
8053 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8054 set->crtc->base.id, set->fb->base.id,
8055 (int)set->num_connectors, set->x, set->y);
8056 } else {
8057 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8058 }
8059
8060 dev = set->crtc->dev;
8061
8062 ret = -ENOMEM;
8063 config = kzalloc(sizeof(*config), GFP_KERNEL);
8064 if (!config)
8065 goto out_config;
8066
8067 ret = intel_set_config_save_state(dev, config);
8068 if (ret)
8069 goto out_config;
8070
8071 save_set.crtc = set->crtc;
8072 save_set.mode = &set->crtc->mode;
8073 save_set.x = set->crtc->x;
8074 save_set.y = set->crtc->y;
8075 save_set.fb = set->crtc->fb;
8076
8077 /* Compute whether we need a full modeset, only an fb base update or no
8078 * change at all. In the future we might also check whether only the
8079 * mode changed, e.g. for LVDS where we only change the panel fitter in
8080 * such cases. */
8081 intel_set_config_compute_mode_changes(set, config);
8082
9a935856 8083 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8084 if (ret)
8085 goto fail;
8086
5e2b584e 8087 if (config->mode_changed) {
87f1faa6 8088 if (set->mode) {
50f56119
DV		 8089 DRM_DEBUG_KMS("attempting to set mode from"
8090 " userspace\n");
8091 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 8092 }
8093
8094 if (!intel_set_mode(set->crtc, set->mode,
8095 set->x, set->y, set->fb)) {
8096 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
8097 set->crtc->base.id);
8098 ret = -EINVAL;
8099 goto fail;
8100 }
5e2b584e 8101 } else if (config->fb_changed) {
4f660f49 8102 ret = intel_pipe_set_base(set->crtc,
94352cf9 8103 set->x, set->y, set->fb);
50f56119
DV		 8104 }
8105
d9e55608
DV		 8106 intel_set_config_free(config);
8107
50f56119
DV		 8108 return 0;
8109
8110fail:
85f9eb71 8111 intel_set_config_restore_state(dev, config);
50f56119
DV		 8112
8113 /* Try to restore the config */
5e2b584e 8114 if (config->mode_changed &&
a6778b3c
DV		 8115 !intel_set_mode(save_set.crtc, save_set.mode,
8116 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8117 DRM_ERROR("failed to restore config after modeset failure\n");
8118
d9e55608
DV		 8119out_config:
8120 intel_set_config_free(config);
50f56119
DV		 8121 return ret;
8122}
8123
f6e5b160 8124static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8125 .cursor_set = intel_crtc_cursor_set,
8126 .cursor_move = intel_crtc_cursor_move,
8127 .gamma_set = intel_crtc_gamma_set,
50f56119 8128 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8129 .destroy = intel_crtc_destroy,
8130 .page_flip = intel_crtc_page_flip,
8131};
8132
79f689aa
PZ		 8133static void intel_cpu_pll_init(struct drm_device *dev)
8134{
8135 if (IS_HASWELL(dev))
8136 intel_ddi_pll_init(dev);
8137}
8138
ee7b9f93
JB		 8139static void intel_pch_pll_init(struct drm_device *dev)
8140{
8141 drm_i915_private_t *dev_priv = dev->dev_private;
8142 int i;
8143
8144 if (dev_priv->num_pch_pll == 0) {
8145 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8146 return;
8147 }
8148
8149 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8150 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8151 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8152 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8153 }
8154}
8155
b358d0a6 8156static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8157{
22fd0fab 8158 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8159 struct intel_crtc *intel_crtc;
8160 int i;
8161
8162 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8163 if (intel_crtc == NULL)
8164 return;
8165
8166 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8167
8168 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8169 for (i = 0; i < 256; i++) {
8170 intel_crtc->lut_r[i] = i;
8171 intel_crtc->lut_g[i] = i;
8172 intel_crtc->lut_b[i] = i;
8173 }
8174
80824003
JB		 8175 /* Swap pipes & planes for FBC on pre-965 */
8176 intel_crtc->pipe = pipe;
8177 intel_crtc->plane = pipe;
a5c961d1 8178 intel_crtc->cpu_transcoder = pipe;
e2e767ab 8179 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8180 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8181 intel_crtc->plane = !pipe;
80824003
JB		 8182 }
8183
22fd0fab
JB		 8184 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8185 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8186 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8187 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8188
5a354204 8189 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3 8190
79e53945 8191 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8192}
8193
08d7b3d1 8194int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8195 struct drm_file *file)
08d7b3d1 8196{
08d7b3d1 8197 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8198 struct drm_mode_object *drmmode_obj;
8199 struct intel_crtc *crtc;
08d7b3d1 8200
1cff8f6b
DV		 8201 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8202 return -ENODEV;
08d7b3d1 8203
c05422d5
DV		 8204 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8205 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8206
c05422d5 8207 if (!drmmode_obj) {
08d7b3d1
CW		 8208 DRM_ERROR("no such CRTC id\n");
8209 return -EINVAL;
8210 }
8211
c05422d5
DV		 8212 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8213 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8214
c05422d5 8215 return 0;
08d7b3d1
CW		 8216}
8217
66a9278e 8218static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8219{
66a9278e
DV		 8220 struct drm_device *dev = encoder->base.dev;
8221 struct intel_encoder *source_encoder;
79e53945 8222 int index_mask = 0;
79e53945
JB		 8223 int entry = 0;
8224
66a9278e
DV		 8225 list_for_each_entry(source_encoder,
8226 &dev->mode_config.encoder_list, base.head) {
8227
8228 if (encoder == source_encoder)
79e53945 8229 index_mask |= (1 << entry);
66a9278e
DV		 8230
8231 /* Intel hw has only one MUX where enocoders could be cloned. */
8232 if (encoder->cloneable && source_encoder->cloneable)
8233 index_mask |= (1 << entry);
8234
79e53945
JB		 8235 entry++;
8236 }
4ef69c7a 8237
79e53945
JB		 8238 return index_mask;
8239}
8240
4d302442
CW		 8241static bool has_edp_a(struct drm_device *dev)
8242{
8243 struct drm_i915_private *dev_priv = dev->dev_private;
8244
8245 if (!IS_MOBILE(dev))
8246 return false;
8247
8248 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8249 return false;
8250
8251 if (IS_GEN5(dev) &&
8252 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8253 return false;
8254
8255 return true;
8256}
8257
79e53945
JB		 8258static void intel_setup_outputs(struct drm_device *dev)
8259{
725e30ad 8260 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8261 struct intel_encoder *encoder;
cb0953d7 8262 bool dpd_is_edp = false;
f3cfcba6 8263 bool has_lvds;
79e53945 8264
f3cfcba6 8265 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8266 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8267 /* disable the panel fitter on everything but LVDS */
8268 I915_WRITE(PFIT_CONTROL, 0);
8269 }
79e53945 8270
cb0953d7
AJ		 8271 intel_crt_init(dev);
8272
0e72a5b5
ED		 8273 if (IS_HASWELL(dev)) {
8274 int found;
8275
8276 /* Haswell uses DDI functions to detect digital outputs */
8277 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8278 /* DDI A only supports eDP */
8279 if (found)
8280 intel_ddi_init(dev, PORT_A);
8281
8282 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8283 * register */
8284 found = I915_READ(SFUSE_STRAP);
8285
8286 if (found & SFUSE_STRAP_DDIB_DETECTED)
8287 intel_ddi_init(dev, PORT_B);
8288 if (found & SFUSE_STRAP_DDIC_DETECTED)
8289 intel_ddi_init(dev, PORT_C);
8290 if (found & SFUSE_STRAP_DDID_DETECTED)
8291 intel_ddi_init(dev, PORT_D);
8292 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8293 int found;
270b3042
DV		 8294 dpd_is_edp = intel_dpd_is_edp(dev);
8295
8296 if (has_edp_a(dev))
8297 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8298
30ad48b7 8299 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca 8300 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8301 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8302 if (!found)
08d644ad 8303 intel_hdmi_init(dev, HDMIB, PORT_B);
5eb08b69 8304 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8305 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8306 }
8307
8308 if (I915_READ(HDMIC) & PORT_DETECTED)
08d644ad 8309 intel_hdmi_init(dev, HDMIC, PORT_C);
30ad48b7 8310
b708a1d5 8311 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
08d644ad 8312 intel_hdmi_init(dev, HDMID, PORT_D);
30ad48b7 8313
5eb08b69 8314 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8315 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8316
270b3042 8317 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8318 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d
JB		 8319 } else if (IS_VALLEYVIEW(dev)) {
8320 int found;
8321
19c03924
GB		 8322 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8323 if (I915_READ(DP_C) & DP_DETECTED)
8324 intel_dp_init(dev, DP_C, PORT_C);
8325
4a87d65d
JB		 8326 if (I915_READ(SDVOB) & PORT_DETECTED) {
8327 /* SDVOB multiplex with HDMIB */
8328 found = intel_sdvo_init(dev, SDVOB, true);
8329 if (!found)
08d644ad 8330 intel_hdmi_init(dev, SDVOB, PORT_B);
4a87d65d 8331 if (!found && (I915_READ(DP_B) & DP_DETECTED))
ab9d7c30 8332 intel_dp_init(dev, DP_B, PORT_B);
4a87d65d
JB		 8333 }
8334
8335 if (I915_READ(SDVOC) & PORT_DETECTED)
08d644ad 8336 intel_hdmi_init(dev, SDVOC, PORT_C);
5eb08b69 8337
103a196f 8338 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8339 bool found = false;
7d57382e 8340
725e30ad 8341 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 8342 DRM_DEBUG_KMS("probing SDVOB\n");
eef4eacb 8343 found = intel_sdvo_init(dev, SDVOB, true);
b01f2c3a
JB		 8344 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8345 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
08d644ad 8346 intel_hdmi_init(dev, SDVOB, PORT_B);
b01f2c3a 8347 }
27185ae1 8348
b01f2c3a
JB		 8349 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8350 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 8351 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 8352 }
725e30ad 8353 }
13520b05
KH		 8354
8355 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8356
b01f2c3a
JB		 8357 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8358 DRM_DEBUG_KMS("probing SDVOC\n");
eef4eacb 8359 found = intel_sdvo_init(dev, SDVOC, false);
b01f2c3a 8360 }
27185ae1
ML		 8361
8362 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8363
b01f2c3a
JB		 8364 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8365 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
08d644ad 8366 intel_hdmi_init(dev, SDVOC, PORT_C);
b01f2c3a
JB		 8367 }
8368 if (SUPPORTS_INTEGRATED_DP(dev)) {
8369 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 8370 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 8371 }
725e30ad 8372 }
27185ae1 8373
b01f2c3a
JB		 8374 if (SUPPORTS_INTEGRATED_DP(dev) &&
8375 (I915_READ(DP_D) & DP_DETECTED)) {
8376 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 8377 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 8378 }
bad720ff 8379 } else if (IS_GEN2(dev))
79e53945
JB		 8380 intel_dvo_init(dev);
8381
103a196f 8382 if (SUPPORTS_TV(dev))
79e53945
JB		 8383 intel_tv_init(dev);
8384
4ef69c7a
CW		 8385 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8386 encoder->base.possible_crtcs = encoder->crtc_mask;
8387 encoder->base.possible_clones =
66a9278e 8388 intel_encoder_clones(encoder);
79e53945 8389 }
47356eb6 8390
40579abe 8391 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9fb526db 8392 ironlake_init_pch_refclk(dev);
270b3042
DV		 8393
8394 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8395}
8396
8397static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8398{
8399 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8400
8401 drm_framebuffer_cleanup(fb);
05394f39 8402 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8403
8404 kfree(intel_fb);
8405}
8406
8407static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8408 struct drm_file *file,
79e53945
JB		 8409 unsigned int *handle)
8410{
8411 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8412 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8413
05394f39 8414 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8415}
8416
8417static const struct drm_framebuffer_funcs intel_fb_funcs = {
8418 .destroy = intel_user_framebuffer_destroy,
8419 .create_handle = intel_user_framebuffer_create_handle,
8420};
8421
38651674
DA		 8422int intel_framebuffer_init(struct drm_device *dev,
8423 struct intel_framebuffer *intel_fb,
308e5bcb 8424 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8425 struct drm_i915_gem_object *obj)
79e53945 8426{
79e53945
JB		 8427 int ret;
8428
05394f39 8429 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 8430 return -EINVAL;
8431
308e5bcb 8432 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 8433 return -EINVAL;
8434
5d7bd705
VS		 8435 /* FIXME <= Gen4 stride limits are bit unclear */
8436 if (mode_cmd->pitches[0] > 32768)
8437 return -EINVAL;
8438
8439 if (obj->tiling_mode != I915_TILING_NONE &&
8440 mode_cmd->pitches[0] != obj->stride)
8441 return -EINVAL;
8442
57779d06 8443 /* Reject formats not supported by any plane early. */
308e5bcb 8444 switch (mode_cmd->pixel_format) {
57779d06 8445 case DRM_FORMAT_C8:
04b3924d
VS		 8446 case DRM_FORMAT_RGB565:
8447 case DRM_FORMAT_XRGB8888:
8448 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8449 break;
8450 case DRM_FORMAT_XRGB1555:
8451 case DRM_FORMAT_ARGB1555:
8452 if (INTEL_INFO(dev)->gen > 3)
8453 return -EINVAL;
8454 break;
8455 case DRM_FORMAT_XBGR8888:
8456 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8457 case DRM_FORMAT_XRGB2101010:
8458 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8459 case DRM_FORMAT_XBGR2101010:
8460 case DRM_FORMAT_ABGR2101010:
8461 if (INTEL_INFO(dev)->gen < 4)
8462 return -EINVAL;
b5626747 8463 break;
04b3924d
VS		 8464 case DRM_FORMAT_YUYV:
8465 case DRM_FORMAT_UYVY:
8466 case DRM_FORMAT_YVYU:
8467 case DRM_FORMAT_VYUY:
57779d06
VS		 8468 if (INTEL_INFO(dev)->gen < 6)
8469 return -EINVAL;
57cd6508
CW		 8470 break;
8471 default:
57779d06 8472 DRM_DEBUG_KMS("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8473 return -EINVAL;
8474 }
8475
90f9a336
VS		 8476 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8477 if (mode_cmd->offsets[0] != 0)
8478 return -EINVAL;
8479
79e53945
JB		 8480 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8481 if (ret) {
8482 DRM_ERROR("framebuffer init failed %d\n", ret);
8483 return ret;
8484 }
8485
8486 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 8487 intel_fb->obj = obj;
79e53945
JB		 8488 return 0;
8489}
8490
79e53945
JB		 8491static struct drm_framebuffer *
8492intel_user_framebuffer_create(struct drm_device *dev,
8493 struct drm_file *filp,
308e5bcb 8494 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8495{
05394f39 8496 struct drm_i915_gem_object *obj;
79e53945 8497
308e5bcb
JB		 8498 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8499 mode_cmd->handles[0]));
c8725226 8500 if (&obj->base == NULL)
cce13ff7 8501 return ERR_PTR(-ENOENT);
79e53945 8502
d2dff872 8503 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8504}
8505
79e53945 8506static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8507 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8508 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8509};
8510
e70236a8
JB		 8511/* Set up chip specific display functions */
8512static void intel_init_display(struct drm_device *dev)
8513{
8514 struct drm_i915_private *dev_priv = dev->dev_private;
8515
8516 /* We always want a DPMS function */
09b4ddf9
PZ		 8517 if (IS_HASWELL(dev)) {
8518 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8519 dev_priv->display.crtc_enable = haswell_crtc_enable;
8520 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 8521 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 8522 dev_priv->display.update_plane = ironlake_update_plane;
8523 } else if (HAS_PCH_SPLIT(dev)) {
f564048e 8524 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 8525 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8526 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8527 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8528 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8529 } else {
f564048e 8530 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 8531 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8532 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8533 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8534 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8535 }
e70236a8 8536
e70236a8 8537 /* Returns the core display clock speed */
25eb05fc
JB		 8538 if (IS_VALLEYVIEW(dev))
8539 dev_priv->display.get_display_clock_speed =
8540 valleyview_get_display_clock_speed;
8541 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8542 dev_priv->display.get_display_clock_speed =
8543 i945_get_display_clock_speed;
8544 else if (IS_I915G(dev))
8545 dev_priv->display.get_display_clock_speed =
8546 i915_get_display_clock_speed;
f2b115e6 8547 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8548 dev_priv->display.get_display_clock_speed =
8549 i9xx_misc_get_display_clock_speed;
8550 else if (IS_I915GM(dev))
8551 dev_priv->display.get_display_clock_speed =
8552 i915gm_get_display_clock_speed;
8553 else if (IS_I865G(dev))
8554 dev_priv->display.get_display_clock_speed =
8555 i865_get_display_clock_speed;
f0f8a9ce 8556 else if (IS_I85X(dev))
e70236a8
JB		 8557 dev_priv->display.get_display_clock_speed =
8558 i855_get_display_clock_speed;
8559 else /* 852, 830 */
8560 dev_priv->display.get_display_clock_speed =
8561 i830_get_display_clock_speed;
8562
7f8a8569 8563 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8564 if (IS_GEN5(dev)) {
674cf967 8565 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8566 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8567 } else if (IS_GEN6(dev)) {
674cf967 8568 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8569 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8570 } else if (IS_IVYBRIDGE(dev)) {
8571 /* FIXME: detect B0+ stepping and use auto training */
8572 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 8573 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 8574 dev_priv->display.modeset_global_resources =
8575 ivb_modeset_global_resources;
c82e4d26
ED		 8576 } else if (IS_HASWELL(dev)) {
8577 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 8578 dev_priv->display.write_eld = haswell_write_eld;
7f8a8569
ZW		 8579 } else
8580 dev_priv->display.update_wm = NULL;
6067aaea 8581 } else if (IS_G4X(dev)) {
e0dac65e 8582 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8583 }
8c9f3aaf
JB		 8584
8585 /* Default just returns -ENODEV to indicate unsupported */
8586 dev_priv->display.queue_flip = intel_default_queue_flip;
8587
8588 switch (INTEL_INFO(dev)->gen) {
8589 case 2:
8590 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8591 break;
8592
8593 case 3:
8594 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8595 break;
8596
8597 case 4:
8598 case 5:
8599 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8600 break;
8601
8602 case 6:
8603 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8604 break;
7c9017e5
JB		 8605 case 7:
8606 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8607 break;
8c9f3aaf 8608 }
e70236a8
JB		 8609}
8610
b690e96c
JB		 8611/*
8612 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8613 * resume, or other times. This quirk makes sure that's the case for
8614 * affected systems.
8615 */
0206e353 8616static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8617{
8618 struct drm_i915_private *dev_priv = dev->dev_private;
8619
8620 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 8621 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 8622}
8623
435793df
KP		 8624/*
8625 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8626 */
8627static void quirk_ssc_force_disable(struct drm_device *dev)
8628{
8629 struct drm_i915_private *dev_priv = dev->dev_private;
8630 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 8631 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 8632}
8633
4dca20ef 8634/*
5a15ab5b
CE		 8635 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8636 * brightness value
4dca20ef
CE		 8637 */
8638static void quirk_invert_brightness(struct drm_device *dev)
8639{
8640 struct drm_i915_private *dev_priv = dev->dev_private;
8641 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 8642 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 8643}
8644
b690e96c
JB		 8645struct intel_quirk {
8646 int device;
8647 int subsystem_vendor;
8648 int subsystem_device;
8649 void (*hook)(struct drm_device *dev);
8650};
8651
c43b5634 8652static struct intel_quirk intel_quirks[] = {
b690e96c 8653 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8654 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 8655
b690e96c
JB		 8656 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8657 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8658
b690e96c
JB		 8659 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8660 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8661
ccd0d36e 8662 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 8663 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 8664 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 8665
8666 /* Lenovo U160 cannot use SSC on LVDS */
8667 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 8668
8669 /* Sony Vaio Y cannot use SSC on LVDS */
8670 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 8671
8672 /* Acer Aspire 5734Z must invert backlight brightness */
8673 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
b690e96c
JB		 8674};
8675
8676static void intel_init_quirks(struct drm_device *dev)
8677{
8678 struct pci_dev *d = dev->pdev;
8679 int i;
8680
8681 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8682 struct intel_quirk *q = &intel_quirks[i];
8683
8684 if (d->device == q->device &&
8685 (d->subsystem_vendor == q->subsystem_vendor ||
8686 q->subsystem_vendor == PCI_ANY_ID) &&
8687 (d->subsystem_device == q->subsystem_device ||
8688 q->subsystem_device == PCI_ANY_ID))
8689 q->hook(dev);
8690 }
8691}
8692
9cce37f4
JB		 8693/* Disable the VGA plane that we never use */
8694static void i915_disable_vga(struct drm_device *dev)
8695{
8696 struct drm_i915_private *dev_priv = dev->dev_private;
8697 u8 sr1;
8698 u32 vga_reg;
8699
8700 if (HAS_PCH_SPLIT(dev))
8701 vga_reg = CPU_VGACNTRL;
8702 else
8703 vga_reg = VGACNTRL;
8704
8705 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 8706 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 8707 sr1 = inb(VGA_SR_DATA);
8708 outb(sr1 | 1<<5, VGA_SR_DATA);
8709 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8710 udelay(300);
8711
8712 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8713 POSTING_READ(vga_reg);
8714}
8715
f817586c
DV		 8716void intel_modeset_init_hw(struct drm_device *dev)
8717{
0232e927
ED		 8718 /* We attempt to init the necessary power wells early in the initialization
8719 * time, so the subsystems that expect power to be enabled can work.
8720 */
8721 intel_init_power_wells(dev);
8722
a8f78b58
ED		 8723 intel_prepare_ddi(dev);
8724
f817586c
DV		 8725 intel_init_clock_gating(dev);
8726
79f5b2c7 8727 mutex_lock(&dev->struct_mutex);
8090c6b9 8728 intel_enable_gt_powersave(dev);
79f5b2c7 8729 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 8730}
8731
79e53945
JB		 8732void intel_modeset_init(struct drm_device *dev)
8733{
652c393a 8734 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 8735 int i, ret;
79e53945
JB		 8736
8737 drm_mode_config_init(dev);
8738
8739 dev->mode_config.min_width = 0;
8740 dev->mode_config.min_height = 0;
8741
019d96cb
DA		 8742 dev->mode_config.preferred_depth = 24;
8743 dev->mode_config.prefer_shadow = 1;
8744
e6ecefaa 8745 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 8746
b690e96c
JB		 8747 intel_init_quirks(dev);
8748
1fa61106
ED		 8749 intel_init_pm(dev);
8750
e70236a8
JB		 8751 intel_init_display(dev);
8752
a6c45cf0
CW		 8753 if (IS_GEN2(dev)) {
8754 dev->mode_config.max_width = 2048;
8755 dev->mode_config.max_height = 2048;
8756 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 8757 dev->mode_config.max_width = 4096;
8758 dev->mode_config.max_height = 4096;
79e53945 8759 } else {
a6c45cf0
CW		 8760 dev->mode_config.max_width = 8192;
8761 dev->mode_config.max_height = 8192;
79e53945 8762 }
dd2757f8 8763 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
79e53945 8764
28c97730 8765 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 8766 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 8767
a3524f1b 8768 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 8769 intel_crtc_init(dev, i);
00c2064b
JB		 8770 ret = intel_plane_init(dev, i);
8771 if (ret)
8772 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 8773 }
8774
79f689aa 8775 intel_cpu_pll_init(dev);
ee7b9f93
JB		 8776 intel_pch_pll_init(dev);
8777
9cce37f4
JB		 8778 /* Just disable it once at startup */
8779 i915_disable_vga(dev);
79e53945 8780 intel_setup_outputs(dev);
2c7111db
CW		 8781}
8782
24929352
DV		 8783static void
8784intel_connector_break_all_links(struct intel_connector *connector)
8785{
8786 connector->base.dpms = DRM_MODE_DPMS_OFF;
8787 connector->base.encoder = NULL;
8788 connector->encoder->connectors_active = false;
8789 connector->encoder->base.crtc = NULL;
8790}
8791
7fad798e
DV		 8792static void intel_enable_pipe_a(struct drm_device *dev)
8793{
8794 struct intel_connector *connector;
8795 struct drm_connector *crt = NULL;
8796 struct intel_load_detect_pipe load_detect_temp;
8797
8798 /* We can't just switch on the pipe A, we need to set things up with a
8799 * proper mode and output configuration. As a gross hack, enable pipe A
8800 * by enabling the load detect pipe once. */
8801 list_for_each_entry(connector,
8802 &dev->mode_config.connector_list,
8803 base.head) {
8804 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8805 crt = &connector->base;
8806 break;
8807 }
8808 }
8809
8810 if (!crt)
8811 return;
8812
8813 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8814 intel_release_load_detect_pipe(crt, &load_detect_temp);
8815
8816
8817}
8818
fa555837
DV		 8819static bool
8820intel_check_plane_mapping(struct intel_crtc *crtc)
8821{
8822 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8823 u32 reg, val;
8824
8825 if (dev_priv->num_pipe == 1)
8826 return true;
8827
8828 reg = DSPCNTR(!crtc->plane);
8829 val = I915_READ(reg);
8830
8831 if ((val & DISPLAY_PLANE_ENABLE) &&
8832 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8833 return false;
8834
8835 return true;
8836}
8837
24929352
DV		 8838static void intel_sanitize_crtc(struct intel_crtc *crtc)
8839{
8840 struct drm_device *dev = crtc->base.dev;
8841 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 8842 u32 reg;
24929352 8843
24929352 8844 /* Clear any frame start delays used for debugging left by the BIOS */
702e7a56 8845 reg = PIPECONF(crtc->cpu_transcoder);
24929352
DV		 8846 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8847
8848 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 8849 * disable the crtc (and hence change the state) if it is wrong. Note
8850 * that gen4+ has a fixed plane -> pipe mapping. */
8851 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 8852 struct intel_connector *connector;
8853 bool plane;
8854
24929352
DV		 8855 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8856 crtc->base.base.id);
8857
8858 /* Pipe has the wrong plane attached and the plane is active.
8859 * Temporarily change the plane mapping and disable everything
8860 * ... */
8861 plane = crtc->plane;
8862 crtc->plane = !plane;
8863 dev_priv->display.crtc_disable(&crtc->base);
8864 crtc->plane = plane;
8865
8866 /* ... and break all links. */
8867 list_for_each_entry(connector, &dev->mode_config.connector_list,
8868 base.head) {
8869 if (connector->encoder->base.crtc != &crtc->base)
8870 continue;
8871
8872 intel_connector_break_all_links(connector);
8873 }
8874
8875 WARN_ON(crtc->active);
8876 crtc->base.enabled = false;
8877 }
24929352 8878
7fad798e
DV		 8879 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8880 crtc->pipe == PIPE_A && !crtc->active) {
8881 /* BIOS forgot to enable pipe A, this mostly happens after
8882 * resume. Force-enable the pipe to fix this, the update_dpms
8883 * call below we restore the pipe to the right state, but leave
8884 * the required bits on. */
8885 intel_enable_pipe_a(dev);
8886 }
8887
24929352
DV		 8888 /* Adjust the state of the output pipe according to whether we
8889 * have active connectors/encoders. */
8890 intel_crtc_update_dpms(&crtc->base);
8891
8892 if (crtc->active != crtc->base.enabled) {
8893 struct intel_encoder *encoder;
8894
8895 /* This can happen either due to bugs in the get_hw_state
8896 * functions or because the pipe is force-enabled due to the
8897 * pipe A quirk. */
8898 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8899 crtc->base.base.id,
8900 crtc->base.enabled ? "enabled" : "disabled",
8901 crtc->active ? "enabled" : "disabled");
8902
8903 crtc->base.enabled = crtc->active;
8904
8905 /* Because we only establish the connector -> encoder ->
8906 * crtc links if something is active, this means the
8907 * crtc is now deactivated. Break the links. connector
8908 * -> encoder links are only establish when things are
8909 * actually up, hence no need to break them. */
8910 WARN_ON(crtc->active);
8911
8912 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8913 WARN_ON(encoder->connectors_active);
8914 encoder->base.crtc = NULL;
8915 }
8916 }
8917}
8918
8919static void intel_sanitize_encoder(struct intel_encoder *encoder)
8920{
8921 struct intel_connector *connector;
8922 struct drm_device *dev = encoder->base.dev;
8923
8924 /* We need to check both for a crtc link (meaning that the
8925 * encoder is active and trying to read from a pipe) and the
8926 * pipe itself being active. */
8927 bool has_active_crtc = encoder->base.crtc &&
8928 to_intel_crtc(encoder->base.crtc)->active;
8929
8930 if (encoder->connectors_active && !has_active_crtc) {
8931 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8932 encoder->base.base.id,
8933 drm_get_encoder_name(&encoder->base));
8934
8935 /* Connector is active, but has no active pipe. This is
8936 * fallout from our resume register restoring. Disable
8937 * the encoder manually again. */
8938 if (encoder->base.crtc) {
8939 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8940 encoder->base.base.id,
8941 drm_get_encoder_name(&encoder->base));
8942 encoder->disable(encoder);
8943 }
8944
8945 /* Inconsistent output/port/pipe state happens presumably due to
8946 * a bug in one of the get_hw_state functions. Or someplace else
8947 * in our code, like the register restore mess on resume. Clamp
8948 * things to off as a safer default. */
8949 list_for_each_entry(connector,
8950 &dev->mode_config.connector_list,
8951 base.head) {
8952 if (connector->encoder != encoder)
8953 continue;
8954
8955 intel_connector_break_all_links(connector);
8956 }
8957 }
8958 /* Enabled encoders without active connectors will be fixed in
8959 * the crtc fixup. */
8960}
8961
8962/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8963 * and i915 state tracking structures. */
8964void intel_modeset_setup_hw_state(struct drm_device *dev)
8965{
8966 struct drm_i915_private *dev_priv = dev->dev_private;
8967 enum pipe pipe;
8968 u32 tmp;
8969 struct intel_crtc *crtc;
8970 struct intel_encoder *encoder;
8971 struct intel_connector *connector;
8972
e28d54cb
PZ		 8973 if (IS_HASWELL(dev)) {
8974 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8975
8976 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8977 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8978 case TRANS_DDI_EDP_INPUT_A_ON:
8979 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8980 pipe = PIPE_A;
8981 break;
8982 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8983 pipe = PIPE_B;
8984 break;
8985 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8986 pipe = PIPE_C;
8987 break;
8988 }
8989
8990 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8991 crtc->cpu_transcoder = TRANSCODER_EDP;
8992
8993 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
8994 pipe_name(pipe));
8995 }
8996 }
8997
24929352
DV		 8998 for_each_pipe(pipe) {
8999 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9000
702e7a56 9001 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
24929352
DV		 9002 if (tmp & PIPECONF_ENABLE)
9003 crtc->active = true;
9004 else
9005 crtc->active = false;
9006
9007 crtc->base.enabled = crtc->active;
9008
9009 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9010 crtc->base.base.id,
9011 crtc->active ? "enabled" : "disabled");
9012 }
9013
6441ab5f
PZ		 9014 if (IS_HASWELL(dev))
9015 intel_ddi_setup_hw_pll_state(dev);
9016
24929352
DV		 9017 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9018 base.head) {
9019 pipe = 0;
9020
9021 if (encoder->get_hw_state(encoder, &pipe)) {
9022 encoder->base.crtc =
9023 dev_priv->pipe_to_crtc_mapping[pipe];
9024 } else {
9025 encoder->base.crtc = NULL;
9026 }
9027
9028 encoder->connectors_active = false;
9029 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9030 encoder->base.base.id,
9031 drm_get_encoder_name(&encoder->base),
9032 encoder->base.crtc ? "enabled" : "disabled",
9033 pipe);
9034 }
9035
9036 list_for_each_entry(connector, &dev->mode_config.connector_list,
9037 base.head) {
9038 if (connector->get_hw_state(connector)) {
9039 connector->base.dpms = DRM_MODE_DPMS_ON;
9040 connector->encoder->connectors_active = true;
9041 connector->base.encoder = &connector->encoder->base;
9042 } else {
9043 connector->base.dpms = DRM_MODE_DPMS_OFF;
9044 connector->base.encoder = NULL;
9045 }
9046 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9047 connector->base.base.id,
9048 drm_get_connector_name(&connector->base),
9049 connector->base.encoder ? "enabled" : "disabled");
9050 }
9051
9052 /* HW state is read out, now we need to sanitize this mess. */
9053 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9054 base.head) {
9055 intel_sanitize_encoder(encoder);
9056 }
9057
9058 for_each_pipe(pipe) {
9059 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9060 intel_sanitize_crtc(crtc);
9061 }
9a935856
DV		 9062
9063 intel_modeset_update_staged_output_state(dev);
8af6cf88
DV		 9064
9065 intel_modeset_check_state(dev);
2e938892
DV		 9066
9067 drm_mode_config_reset(dev);
24929352
DV		 9068}
9069
2c7111db
CW		 9070void intel_modeset_gem_init(struct drm_device *dev)
9071{
1833b134 9072 intel_modeset_init_hw(dev);
02e792fb
DV		 9073
9074 intel_setup_overlay(dev);
24929352
DV		 9075
9076 intel_modeset_setup_hw_state(dev);
79e53945
JB		 9077}
9078
9079void intel_modeset_cleanup(struct drm_device *dev)
9080{
652c393a
JB		 9081 struct drm_i915_private *dev_priv = dev->dev_private;
9082 struct drm_crtc *crtc;
9083 struct intel_crtc *intel_crtc;
9084
f87ea761 9085 drm_kms_helper_poll_fini(dev);
652c393a
JB		 9086 mutex_lock(&dev->struct_mutex);
9087
723bfd70
JB		 9088 intel_unregister_dsm_handler();
9089
9090
652c393a
JB		 9091 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9092 /* Skip inactive CRTCs */
9093 if (!crtc->fb)
9094 continue;
9095
9096 intel_crtc = to_intel_crtc(crtc);
3dec0095 9097 intel_increase_pllclock(crtc);
652c393a
JB		 9098 }
9099
973d04f9 9100 intel_disable_fbc(dev);
e70236a8 9101
8090c6b9 9102 intel_disable_gt_powersave(dev);
0cdab21f 9103
930ebb46
DV		 9104 ironlake_teardown_rc6(dev);
9105
57f350b6
JB		 9106 if (IS_VALLEYVIEW(dev))
9107 vlv_init_dpio(dev);
9108
69341a5e
KH		 9109 mutex_unlock(&dev->struct_mutex);
9110
6c0d9350
DV		 9111 /* Disable the irq before mode object teardown, for the irq might
9112 * enqueue unpin/hotplug work. */
9113 drm_irq_uninstall(dev);
9114 cancel_work_sync(&dev_priv->hotplug_work);
c6a828d3 9115 cancel_work_sync(&dev_priv->rps.work);
6c0d9350 9116
1630fe75
CW		 9117 /* flush any delayed tasks or pending work */
9118 flush_scheduled_work();
9119
79e53945
JB		 9120 drm_mode_config_cleanup(dev);
9121}
9122
f1c79df3
ZW		 9123/*
9124 * Return which encoder is currently attached for connector.
9125 */
df0e9248 9126struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9127{
df0e9248
CW		 9128 return &intel_attached_encoder(connector)->base;
9129}
f1c79df3 9130
df0e9248
CW		 9131void intel_connector_attach_encoder(struct intel_connector *connector,
9132 struct intel_encoder *encoder)
9133{
9134 connector->encoder = encoder;
9135 drm_mode_connector_attach_encoder(&connector->base,
9136 &encoder->base);
79e53945 9137}
28d52043
DA		 9138
9139/*
9140 * set vga decode state - true == enable VGA decode
9141 */
9142int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9143{
9144 struct drm_i915_private *dev_priv = dev->dev_private;
9145 u16 gmch_ctrl;
9146
9147 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9148 if (state)
9149 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9150 else
9151 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9152 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9153 return 0;
9154}
c4a1d9e4
CW		 9155
9156#ifdef CONFIG_DEBUG_FS
9157#include <linux/seq_file.h>
9158
9159struct intel_display_error_state {
9160 struct intel_cursor_error_state {
9161 u32 control;
9162 u32 position;
9163 u32 base;
9164 u32 size;
52331309 9165 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9166
9167 struct intel_pipe_error_state {
9168 u32 conf;
9169 u32 source;
9170
9171 u32 htotal;
9172 u32 hblank;
9173 u32 hsync;
9174 u32 vtotal;
9175 u32 vblank;
9176 u32 vsync;
52331309 9177 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9178
9179 struct intel_plane_error_state {
9180 u32 control;
9181 u32 stride;
9182 u32 size;
9183 u32 pos;
9184 u32 addr;
9185 u32 surface;
9186 u32 tile_offset;
52331309 9187 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9188};
9189
9190struct intel_display_error_state *
9191intel_display_capture_error_state(struct drm_device *dev)
9192{
0206e353 9193 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9194 struct intel_display_error_state *error;
702e7a56 9195 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9196 int i;
9197
9198 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9199 if (error == NULL)
9200 return NULL;
9201
52331309 9202 for_each_pipe(i) {
702e7a56
PZ		 9203 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9204
c4a1d9e4
CW		 9205 error->cursor[i].control = I915_READ(CURCNTR(i));
9206 error->cursor[i].position = I915_READ(CURPOS(i));
9207 error->cursor[i].base = I915_READ(CURBASE(i));
9208
9209 error->plane[i].control = I915_READ(DSPCNTR(i));
9210 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9211 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 9212 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 9213 error->plane[i].addr = I915_READ(DSPADDR(i));
9214 if (INTEL_INFO(dev)->gen >= 4) {
9215 error->plane[i].surface = I915_READ(DSPSURF(i));
9216 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9217 }
9218
702e7a56 9219 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9220 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9221 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9222 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9223 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9224 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9225 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9226 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9227 }
9228
9229 return error;
9230}
9231
9232void
9233intel_display_print_error_state(struct seq_file *m,
9234 struct drm_device *dev,
9235 struct intel_display_error_state *error)
9236{
52331309 9237 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 9238 int i;
9239
52331309
DL		 9240 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9241 for_each_pipe(i) {
c4a1d9e4
CW		 9242 seq_printf(m, "Pipe [%d]:\n", i);
9243 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9244 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9245 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9246 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9247 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9248 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9249 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9250 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9251
9252 seq_printf(m, "Plane [%d]:\n", i);
9253 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9254 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9255 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9256 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9257 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9258 if (INTEL_INFO(dev)->gen >= 4) {
9259 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9260 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9261 }
9262
9263 seq_printf(m, "Cursor [%d]:\n", i);
9264 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9265 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9266 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9267 }
9268}
9269#endif
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