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drm/i915: clean up plane bpp confusion
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 47
48typedef struct {
0206e353
AJ		 49 /* given values */
50 int n;
51 int m1, m2;
52 int p1, p2;
53 /* derived values */
54 int dot;
55 int vco;
56 int m;
57 int p;
79e53945
JB		 58} intel_clock_t;
59
60typedef struct {
0206e353 61 int min, max;
79e53945
JB		 62} intel_range_t;
63
64typedef struct {
0206e353
AJ		 65 int dot_limit;
66 int p2_slow, p2_fast;
79e53945
JB		 67} intel_p2_t;
68
69#define INTEL_P2_NUM 2
d4906093
ML		 70typedef struct intel_limit intel_limit_t;
71struct intel_limit {
0206e353
AJ		 72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
73 intel_p2_t p2;
f4808ab8
VS		 74 /**
75 * find_pll() - Find the best values for the PLL
76 * @limit: limits for the PLL
77 * @crtc: current CRTC
78 * @target: target frequency in kHz
79 * @refclk: reference clock frequency in kHz
80 * @match_clock: if provided, @best_clock P divider must
81 * match the P divider from @match_clock
82 * used for LVDS downclocking
83 * @best_clock: best PLL values found
84 *
85 * Returns true on success, false on failure.
86 */
87 bool (*find_pll)(const intel_limit_t *limit,
88 struct drm_crtc *crtc,
89 int target, int refclk,
90 intel_clock_t *match_clock,
91 intel_clock_t *best_clock);
d4906093 92};
79e53945 93
2377b741
JB		 94/* FDI */
95#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
96
d2acd215
DV		 97int
98intel_pch_rawclk(struct drm_device *dev)
99{
100 struct drm_i915_private *dev_priv = dev->dev_private;
101
102 WARN_ON(!HAS_PCH_SPLIT(dev));
103
104 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
105}
106
d4906093
ML		 107static bool
108intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 109 int target, int refclk, intel_clock_t *match_clock,
110 intel_clock_t *best_clock);
d4906093
ML		 111static bool
112intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 113 int target, int refclk, intel_clock_t *match_clock,
114 intel_clock_t *best_clock);
79e53945 115
a4fc5ed6
KP		 116static bool
117intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 118 int target, int refclk, intel_clock_t *match_clock,
119 intel_clock_t *best_clock);
5eb08b69 120static bool
f2b115e6 121intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 122 int target, int refclk, intel_clock_t *match_clock,
123 intel_clock_t *best_clock);
a4fc5ed6 124
a0c4da24
JB		 125static bool
126intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
127 int target, int refclk, intel_clock_t *match_clock,
128 intel_clock_t *best_clock);
129
021357ac
CW		 130static inline u32 /* units of 100MHz */
131intel_fdi_link_freq(struct drm_device *dev)
132{
8b99e68c
CW		 133 if (IS_GEN5(dev)) {
134 struct drm_i915_private *dev_priv = dev->dev_private;
135 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
136 } else
137 return 27;
021357ac
CW		 138}
139
e4b36699 140static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 141 .dot = { .min = 25000, .max = 350000 },
142 .vco = { .min = 930000, .max = 1400000 },
143 .n = { .min = 3, .max = 16 },
144 .m = { .min = 96, .max = 140 },
145 .m1 = { .min = 18, .max = 26 },
146 .m2 = { .min = 6, .max = 16 },
147 .p = { .min = 4, .max = 128 },
148 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 149 .p2 = { .dot_limit = 165000,
150 .p2_slow = 4, .p2_fast = 2 },
d4906093 151 .find_pll = intel_find_best_PLL,
e4b36699
KP		 152};
153
154static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 155 .dot = { .min = 25000, .max = 350000 },
156 .vco = { .min = 930000, .max = 1400000 },
157 .n = { .min = 3, .max = 16 },
158 .m = { .min = 96, .max = 140 },
159 .m1 = { .min = 18, .max = 26 },
160 .m2 = { .min = 6, .max = 16 },
161 .p = { .min = 4, .max = 128 },
162 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 163 .p2 = { .dot_limit = 165000,
164 .p2_slow = 14, .p2_fast = 7 },
d4906093 165 .find_pll = intel_find_best_PLL,
e4b36699 166};
273e27ca 167
e4b36699 168static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 169 .dot = { .min = 20000, .max = 400000 },
170 .vco = { .min = 1400000, .max = 2800000 },
171 .n = { .min = 1, .max = 6 },
172 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 173 .m1 = { .min = 8, .max = 18 },
174 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 175 .p = { .min = 5, .max = 80 },
176 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 177 .p2 = { .dot_limit = 200000,
178 .p2_slow = 10, .p2_fast = 5 },
d4906093 179 .find_pll = intel_find_best_PLL,
e4b36699
KP		 180};
181
182static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 183 .dot = { .min = 20000, .max = 400000 },
184 .vco = { .min = 1400000, .max = 2800000 },
185 .n = { .min = 1, .max = 6 },
186 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 187 .m1 = { .min = 8, .max = 18 },
188 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 189 .p = { .min = 7, .max = 98 },
190 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 191 .p2 = { .dot_limit = 112000,
192 .p2_slow = 14, .p2_fast = 7 },
d4906093 193 .find_pll = intel_find_best_PLL,
e4b36699
KP		 194};
195
273e27ca 196
e4b36699 197static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 198 .dot = { .min = 25000, .max = 270000 },
199 .vco = { .min = 1750000, .max = 3500000},
200 .n = { .min = 1, .max = 4 },
201 .m = { .min = 104, .max = 138 },
202 .m1 = { .min = 17, .max = 23 },
203 .m2 = { .min = 5, .max = 11 },
204 .p = { .min = 10, .max = 30 },
205 .p1 = { .min = 1, .max = 3},
206 .p2 = { .dot_limit = 270000,
207 .p2_slow = 10,
208 .p2_fast = 10
044c7c41 209 },
d4906093 210 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 211};
212
213static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 214 .dot = { .min = 22000, .max = 400000 },
215 .vco = { .min = 1750000, .max = 3500000},
216 .n = { .min = 1, .max = 4 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 16, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 5, .max = 80 },
221 .p1 = { .min = 1, .max = 8},
222 .p2 = { .dot_limit = 165000,
223 .p2_slow = 10, .p2_fast = 5 },
d4906093 224 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 225};
226
227static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 228 .dot = { .min = 20000, .max = 115000 },
229 .vco = { .min = 1750000, .max = 3500000 },
230 .n = { .min = 1, .max = 3 },
231 .m = { .min = 104, .max = 138 },
232 .m1 = { .min = 17, .max = 23 },
233 .m2 = { .min = 5, .max = 11 },
234 .p = { .min = 28, .max = 112 },
235 .p1 = { .min = 2, .max = 8 },
236 .p2 = { .dot_limit = 0,
237 .p2_slow = 14, .p2_fast = 14
044c7c41 238 },
d4906093 239 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 240};
241
242static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 243 .dot = { .min = 80000, .max = 224000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 14, .max = 42 },
250 .p1 = { .min = 2, .max = 6 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 7, .p2_fast = 7
044c7c41 253 },
d4906093 254 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 255};
256
257static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 258 .dot = { .min = 161670, .max = 227000 },
259 .vco = { .min = 1750000, .max = 3500000},
260 .n = { .min = 1, .max = 2 },
261 .m = { .min = 97, .max = 108 },
262 .m1 = { .min = 0x10, .max = 0x12 },
263 .m2 = { .min = 0x05, .max = 0x06 },
264 .p = { .min = 10, .max = 20 },
265 .p1 = { .min = 1, .max = 2},
266 .p2 = { .dot_limit = 0,
273e27ca 267 .p2_slow = 10, .p2_fast = 10 },
0206e353 268 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 269};
270
f2b115e6 271static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 272 .dot = { .min = 20000, .max = 400000},
273 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 274 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 275 .n = { .min = 3, .max = 6 },
276 .m = { .min = 2, .max = 256 },
273e27ca 277 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 278 .m1 = { .min = 0, .max = 0 },
279 .m2 = { .min = 0, .max = 254 },
280 .p = { .min = 5, .max = 80 },
281 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 282 .p2 = { .dot_limit = 200000,
283 .p2_slow = 10, .p2_fast = 5 },
6115707b 284 .find_pll = intel_find_best_PLL,
e4b36699
KP		 285};
286
f2b115e6 287static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 288 .dot = { .min = 20000, .max = 400000 },
289 .vco = { .min = 1700000, .max = 3500000 },
290 .n = { .min = 3, .max = 6 },
291 .m = { .min = 2, .max = 256 },
292 .m1 = { .min = 0, .max = 0 },
293 .m2 = { .min = 0, .max = 254 },
294 .p = { .min = 7, .max = 112 },
295 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 296 .p2 = { .dot_limit = 112000,
297 .p2_slow = 14, .p2_fast = 14 },
6115707b 298 .find_pll = intel_find_best_PLL,
e4b36699
KP		 299};
300
273e27ca
EA		 301/* Ironlake / Sandybridge
302 *
303 * We calculate clock using (register_value + 2) for N/M1/M2, so here
304 * the range value for them is (actual_value - 2).
305 */
b91ad0ec 306static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 5 },
310 .m = { .min = 79, .max = 127 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 5, .max = 80 },
314 .p1 = { .min = 1, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 10, .p2_fast = 5 },
4547668a 317 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 318};
319
b91ad0ec 320static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 79, .max = 118 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 28, .max = 112 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 331 .find_pll = intel_g4x_find_best_PLL,
332};
333
334static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 335 .dot = { .min = 25000, .max = 350000 },
336 .vco = { .min = 1760000, .max = 3510000 },
337 .n = { .min = 1, .max = 3 },
338 .m = { .min = 79, .max = 127 },
339 .m1 = { .min = 12, .max = 22 },
340 .m2 = { .min = 5, .max = 9 },
341 .p = { .min = 14, .max = 56 },
342 .p1 = { .min = 2, .max = 8 },
343 .p2 = { .dot_limit = 225000,
344 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 345 .find_pll = intel_g4x_find_best_PLL,
346};
347
273e27ca 348/* LVDS 100mhz refclk limits. */
b91ad0ec 349static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000 },
352 .n = { .min = 1, .max = 2 },
353 .m = { .min = 79, .max = 126 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 28, .max = 112 },
0206e353 357 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 358 .p2 = { .dot_limit = 225000,
359 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 360 .find_pll = intel_g4x_find_best_PLL,
361};
362
363static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 364 .dot = { .min = 25000, .max = 350000 },
365 .vco = { .min = 1760000, .max = 3510000 },
366 .n = { .min = 1, .max = 3 },
367 .m = { .min = 79, .max = 126 },
368 .m1 = { .min = 12, .max = 22 },
369 .m2 = { .min = 5, .max = 9 },
370 .p = { .min = 14, .max = 42 },
0206e353 371 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 372 .p2 = { .dot_limit = 225000,
373 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 374 .find_pll = intel_g4x_find_best_PLL,
375};
376
377static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 378 .dot = { .min = 25000, .max = 350000 },
379 .vco = { .min = 1760000, .max = 3510000},
380 .n = { .min = 1, .max = 2 },
381 .m = { .min = 81, .max = 90 },
382 .m1 = { .min = 12, .max = 22 },
383 .m2 = { .min = 5, .max = 9 },
384 .p = { .min = 10, .max = 20 },
385 .p1 = { .min = 1, .max = 2},
386 .p2 = { .dot_limit = 0,
273e27ca 387 .p2_slow = 10, .p2_fast = 10 },
0206e353 388 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 389};
390
a0c4da24
JB		 391static const intel_limit_t intel_limits_vlv_dac = {
392 .dot = { .min = 25000, .max = 270000 },
393 .vco = { .min = 4000000, .max = 6000000 },
394 .n = { .min = 1, .max = 7 },
395 .m = { .min = 22, .max = 450 }, /* guess */
396 .m1 = { .min = 2, .max = 3 },
397 .m2 = { .min = 11, .max = 156 },
398 .p = { .min = 10, .max = 30 },
399 .p1 = { .min = 2, .max = 3 },
400 .p2 = { .dot_limit = 270000,
401 .p2_slow = 2, .p2_fast = 20 },
402 .find_pll = intel_vlv_find_best_pll,
403};
404
405static const intel_limit_t intel_limits_vlv_hdmi = {
406 .dot = { .min = 20000, .max = 165000 },
17dc9257 407 .vco = { .min = 4000000, .max = 5994000},
a0c4da24
JB		 408 .n = { .min = 1, .max = 7 },
409 .m = { .min = 60, .max = 300 }, /* guess */
410 .m1 = { .min = 2, .max = 3 },
411 .m2 = { .min = 11, .max = 156 },
412 .p = { .min = 10, .max = 30 },
413 .p1 = { .min = 2, .max = 3 },
414 .p2 = { .dot_limit = 270000,
415 .p2_slow = 2, .p2_fast = 20 },
416 .find_pll = intel_vlv_find_best_pll,
417};
418
419static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 420 .dot = { .min = 25000, .max = 270000 },
421 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 422 .n = { .min = 1, .max = 7 },
74a4dd2e 423 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 424 .m1 = { .min = 2, .max = 3 },
425 .m2 = { .min = 11, .max = 156 },
426 .p = { .min = 10, .max = 30 },
427 .p1 = { .min = 2, .max = 3 },
428 .p2 = { .dot_limit = 270000,
429 .p2_slow = 2, .p2_fast = 20 },
430 .find_pll = intel_vlv_find_best_pll,
431};
432
57f350b6
JB		 433u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
434{
09153000 435 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
57f350b6 436
57f350b6
JB		 437 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
438 DRM_ERROR("DPIO idle wait timed out\n");
09153000 439 return 0;
57f350b6
JB		 440 }
441
442 I915_WRITE(DPIO_REG, reg);
443 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
444 DPIO_BYTE);
445 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
446 DRM_ERROR("DPIO read wait timed out\n");
09153000 447 return 0;
57f350b6 448 }
57f350b6 449
09153000 450 return I915_READ(DPIO_DATA);
57f350b6
JB		 451}
452
a0c4da24
JB		 453static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
454 u32 val)
455{
09153000 456 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a0c4da24 457
a0c4da24
JB		 458 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
459 DRM_ERROR("DPIO idle wait timed out\n");
09153000 460 return;
a0c4da24
JB		 461 }
462
463 I915_WRITE(DPIO_DATA, val);
464 I915_WRITE(DPIO_REG, reg);
465 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
466 DPIO_BYTE);
467 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
468 DRM_ERROR("DPIO write wait timed out\n");
a0c4da24
JB		 469}
470
57f350b6
JB		 471static void vlv_init_dpio(struct drm_device *dev)
472{
473 struct drm_i915_private *dev_priv = dev->dev_private;
474
475 /* Reset the DPIO config */
476 I915_WRITE(DPIO_CTL, 0);
477 POSTING_READ(DPIO_CTL);
478 I915_WRITE(DPIO_CTL, 1);
479 POSTING_READ(DPIO_CTL);
480}
481
1b894b59
CW		 482static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
483 int refclk)
2c07245f 484{
b91ad0ec 485 struct drm_device *dev = crtc->dev;
2c07245f 486 const intel_limit_t *limit;
b91ad0ec
ZW		 487
488 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 489 if (intel_is_dual_link_lvds(dev)) {
1b894b59 490 if (refclk == 100000)
b91ad0ec
ZW		 491 limit = &intel_limits_ironlake_dual_lvds_100m;
492 else
493 limit = &intel_limits_ironlake_dual_lvds;
494 } else {
1b894b59 495 if (refclk == 100000)
b91ad0ec
ZW		 496 limit = &intel_limits_ironlake_single_lvds_100m;
497 else
498 limit = &intel_limits_ironlake_single_lvds;
499 }
500 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
547dc041 501 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
4547668a 502 limit = &intel_limits_ironlake_display_port;
2c07245f 503 else
b91ad0ec 504 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 505
506 return limit;
507}
508
044c7c41
ML		 509static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
510{
511 struct drm_device *dev = crtc->dev;
044c7c41
ML		 512 const intel_limit_t *limit;
513
514 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 515 if (intel_is_dual_link_lvds(dev))
e4b36699 516 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 517 else
e4b36699 518 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 519 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
520 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 521 limit = &intel_limits_g4x_hdmi;
044c7c41 522 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 523 limit = &intel_limits_g4x_sdvo;
0206e353 524 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 525 limit = &intel_limits_g4x_display_port;
044c7c41 526 } else /* The option is for other outputs */
e4b36699 527 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 528
529 return limit;
530}
531
1b894b59 532static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 533{
534 struct drm_device *dev = crtc->dev;
535 const intel_limit_t *limit;
536
bad720ff 537 if (HAS_PCH_SPLIT(dev))
1b894b59 538 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 539 else if (IS_G4X(dev)) {
044c7c41 540 limit = intel_g4x_limit(crtc);
f2b115e6 541 } else if (IS_PINEVIEW(dev)) {
2177832f 542 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 543 limit = &intel_limits_pineview_lvds;
2177832f 544 else
f2b115e6 545 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 546 } else if (IS_VALLEYVIEW(dev)) {
547 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
548 limit = &intel_limits_vlv_dac;
549 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
550 limit = &intel_limits_vlv_hdmi;
551 else
552 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 553 } else if (!IS_GEN2(dev)) {
554 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
555 limit = &intel_limits_i9xx_lvds;
556 else
557 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 558 } else {
559 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 560 limit = &intel_limits_i8xx_lvds;
79e53945 561 else
e4b36699 562 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 563 }
564 return limit;
565}
566
f2b115e6
AJ		 567/* m1 is reserved as 0 in Pineview, n is a ring counter */
568static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 569{
2177832f
SL		 570 clock->m = clock->m2 + 2;
571 clock->p = clock->p1 * clock->p2;
572 clock->vco = refclk * clock->m / clock->n;
573 clock->dot = clock->vco / clock->p;
574}
575
576static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
577{
f2b115e6
AJ		 578 if (IS_PINEVIEW(dev)) {
579 pineview_clock(refclk, clock);
2177832f
SL		 580 return;
581 }
79e53945
JB		 582 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
583 clock->p = clock->p1 * clock->p2;
584 clock->vco = refclk * clock->m / (clock->n + 2);
585 clock->dot = clock->vco / clock->p;
586}
587
79e53945
JB		 588/**
589 * Returns whether any output on the specified pipe is of the specified type
590 */
4ef69c7a 591bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 592{
4ef69c7a 593 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 594 struct intel_encoder *encoder;
595
6c2b7c12
DV		 596 for_each_encoder_on_crtc(dev, crtc, encoder)
597 if (encoder->type == type)
4ef69c7a
CW		 598 return true;
599
600 return false;
79e53945
JB		 601}
602
7c04d1d9 603#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 604/**
605 * Returns whether the given set of divisors are valid for a given refclk with
606 * the given connectors.
607 */
608
1b894b59
CW		 609static bool intel_PLL_is_valid(struct drm_device *dev,
610 const intel_limit_t *limit,
611 const intel_clock_t *clock)
79e53945 612{
79e53945 613 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 614 INTELPllInvalid("p1 out of range\n");
79e53945 615 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 616 INTELPllInvalid("p out of range\n");
79e53945 617 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 618 INTELPllInvalid("m2 out of range\n");
79e53945 619 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 620 INTELPllInvalid("m1 out of range\n");
f2b115e6 621 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 622 INTELPllInvalid("m1 <= m2\n");
79e53945 623 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 624 INTELPllInvalid("m out of range\n");
79e53945 625 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 626 INTELPllInvalid("n out of range\n");
79e53945 627 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 628 INTELPllInvalid("vco out of range\n");
79e53945
JB		 629 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
630 * connector, etc., rather than just a single range.
631 */
632 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 633 INTELPllInvalid("dot out of range\n");
79e53945
JB		 634
635 return true;
636}
637
d4906093
ML		 638static bool
639intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 640 int target, int refclk, intel_clock_t *match_clock,
641 intel_clock_t *best_clock)
d4906093 642
79e53945
JB		 643{
644 struct drm_device *dev = crtc->dev;
79e53945 645 intel_clock_t clock;
79e53945
JB		 646 int err = target;
647
a210b028 648 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 649 /*
a210b028
DV		 650 * For LVDS just rely on its current settings for dual-channel.
651 * We haven't figured out how to reliably set up different
652 * single/dual channel state, if we even can.
79e53945 653 */
1974cad0 654 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 655 clock.p2 = limit->p2.p2_fast;
656 else
657 clock.p2 = limit->p2.p2_slow;
658 } else {
659 if (target < limit->p2.dot_limit)
660 clock.p2 = limit->p2.p2_slow;
661 else
662 clock.p2 = limit->p2.p2_fast;
663 }
664
0206e353 665 memset(best_clock, 0, sizeof(*best_clock));
79e53945 666
42158660
ZY		 667 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
668 clock.m1++) {
669 for (clock.m2 = limit->m2.min;
670 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 671 /* m1 is always 0 in Pineview */
672 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 673 break;
674 for (clock.n = limit->n.min;
675 clock.n <= limit->n.max; clock.n++) {
676 for (clock.p1 = limit->p1.min;
677 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 678 int this_err;
679
2177832f 680 intel_clock(dev, refclk, &clock);
1b894b59
CW		 681 if (!intel_PLL_is_valid(dev, limit,
682 &clock))
79e53945 683 continue;
cec2f356
SP		 684 if (match_clock &&
685 clock.p != match_clock->p)
686 continue;
79e53945
JB		 687
688 this_err = abs(clock.dot - target);
689 if (this_err < err) {
690 *best_clock = clock;
691 err = this_err;
692 }
693 }
694 }
695 }
696 }
697
698 return (err != target);
699}
700
d4906093
ML		 701static bool
702intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 703 int target, int refclk, intel_clock_t *match_clock,
704 intel_clock_t *best_clock)
d4906093
ML		 705{
706 struct drm_device *dev = crtc->dev;
d4906093
ML		 707 intel_clock_t clock;
708 int max_n;
709 bool found;
6ba770dc
AJ		 710 /* approximately equals target * 0.00585 */
711 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 712 found = false;
713
714 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 715 int lvds_reg;
716
c619eed4 717 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 718 lvds_reg = PCH_LVDS;
719 else
720 lvds_reg = LVDS;
1974cad0 721 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 722 clock.p2 = limit->p2.p2_fast;
723 else
724 clock.p2 = limit->p2.p2_slow;
725 } else {
726 if (target < limit->p2.dot_limit)
727 clock.p2 = limit->p2.p2_slow;
728 else
729 clock.p2 = limit->p2.p2_fast;
730 }
731
732 memset(best_clock, 0, sizeof(*best_clock));
733 max_n = limit->n.max;
f77f13e2 734 /* based on hardware requirement, prefer smaller n to precision */
d4906093 735 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 736 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 737 for (clock.m1 = limit->m1.max;
738 clock.m1 >= limit->m1.min; clock.m1--) {
739 for (clock.m2 = limit->m2.max;
740 clock.m2 >= limit->m2.min; clock.m2--) {
741 for (clock.p1 = limit->p1.max;
742 clock.p1 >= limit->p1.min; clock.p1--) {
743 int this_err;
744
2177832f 745 intel_clock(dev, refclk, &clock);
1b894b59
CW		 746 if (!intel_PLL_is_valid(dev, limit,
747 &clock))
d4906093 748 continue;
cec2f356
SP		 749 if (match_clock &&
750 clock.p != match_clock->p)
751 continue;
1b894b59
CW		 752
753 this_err = abs(clock.dot - target);
d4906093
ML		 754 if (this_err < err_most) {
755 *best_clock = clock;
756 err_most = this_err;
757 max_n = clock.n;
758 found = true;
759 }
760 }
761 }
762 }
763 }
2c07245f
ZW		 764 return found;
765}
766
5eb08b69 767static bool
f2b115e6 768intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 769 int target, int refclk, intel_clock_t *match_clock,
770 intel_clock_t *best_clock)
5eb08b69
ZW		 771{
772 struct drm_device *dev = crtc->dev;
773 intel_clock_t clock;
4547668a 774
5eb08b69
ZW		 775 if (target < 200000) {
776 clock.n = 1;
777 clock.p1 = 2;
778 clock.p2 = 10;
779 clock.m1 = 12;
780 clock.m2 = 9;
781 } else {
782 clock.n = 2;
783 clock.p1 = 1;
784 clock.p2 = 10;
785 clock.m1 = 14;
786 clock.m2 = 8;
787 }
788 intel_clock(dev, refclk, &clock);
789 memcpy(best_clock, &clock, sizeof(intel_clock_t));
790 return true;
791}
792
a4fc5ed6
KP		 793/* DisplayPort has only two frequencies, 162MHz and 270MHz */
794static bool
795intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 796 int target, int refclk, intel_clock_t *match_clock,
797 intel_clock_t *best_clock)
a4fc5ed6 798{
5eddb70b
CW		 799 intel_clock_t clock;
800 if (target < 200000) {
801 clock.p1 = 2;
802 clock.p2 = 10;
803 clock.n = 2;
804 clock.m1 = 23;
805 clock.m2 = 8;
806 } else {
807 clock.p1 = 1;
808 clock.p2 = 10;
809 clock.n = 1;
810 clock.m1 = 14;
811 clock.m2 = 2;
812 }
813 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
814 clock.p = (clock.p1 * clock.p2);
815 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
816 clock.vco = 0;
817 memcpy(best_clock, &clock, sizeof(intel_clock_t));
818 return true;
a4fc5ed6 819}
a0c4da24
JB		 820static bool
821intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
822 int target, int refclk, intel_clock_t *match_clock,
823 intel_clock_t *best_clock)
824{
825 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
826 u32 m, n, fastclk;
827 u32 updrate, minupdate, fracbits, p;
828 unsigned long bestppm, ppm, absppm;
829 int dotclk, flag;
830
af447bd3 831 flag = 0;
a0c4da24
JB		 832 dotclk = target * 1000;
833 bestppm = 1000000;
834 ppm = absppm = 0;
835 fastclk = dotclk / (2*100);
836 updrate = 0;
837 minupdate = 19200;
838 fracbits = 1;
839 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
840 bestm1 = bestm2 = bestp1 = bestp2 = 0;
841
842 /* based on hardware requirement, prefer smaller n to precision */
843 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
844 updrate = refclk / n;
845 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
846 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
847 if (p2 > 10)
848 p2 = p2 - 1;
849 p = p1 * p2;
850 /* based on hardware requirement, prefer bigger m1,m2 values */
851 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
852 m2 = (((2*(fastclk * p * n / m1 )) +
853 refclk) / (2*refclk));
854 m = m1 * m2;
855 vco = updrate * m;
856 if (vco >= limit->vco.min && vco < limit->vco.max) {
857 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
858 absppm = (ppm > 0) ? ppm : (-ppm);
859 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
860 bestppm = 0;
861 flag = 1;
862 }
863 if (absppm < bestppm - 10) {
864 bestppm = absppm;
865 flag = 1;
866 }
867 if (flag) {
868 bestn = n;
869 bestm1 = m1;
870 bestm2 = m2;
871 bestp1 = p1;
872 bestp2 = p2;
873 flag = 0;
874 }
875 }
876 }
877 }
878 }
879 }
880 best_clock->n = bestn;
881 best_clock->m1 = bestm1;
882 best_clock->m2 = bestm2;
883 best_clock->p1 = bestp1;
884 best_clock->p2 = bestp2;
885
886 return true;
887}
a4fc5ed6 888
a5c961d1
PZ		 889enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
890 enum pipe pipe)
891{
892 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
893 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
894
895 return intel_crtc->cpu_transcoder;
896}
897
a928d536
PZ		 898static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
899{
900 struct drm_i915_private *dev_priv = dev->dev_private;
901 u32 frame, frame_reg = PIPEFRAME(pipe);
902
903 frame = I915_READ(frame_reg);
904
905 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
906 DRM_DEBUG_KMS("vblank wait timed out\n");
907}
908
9d0498a2
JB		 909/**
910 * intel_wait_for_vblank - wait for vblank on a given pipe
911 * @dev: drm device
912 * @pipe: pipe to wait for
913 *
914 * Wait for vblank to occur on a given pipe. Needed for various bits of
915 * mode setting code.
916 */
917void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 918{
9d0498a2 919 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 920 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 921
a928d536
PZ		 922 if (INTEL_INFO(dev)->gen >= 5) {
923 ironlake_wait_for_vblank(dev, pipe);
924 return;
925 }
926
300387c0
CW		 927 /* Clear existing vblank status. Note this will clear any other
928 * sticky status fields as well.
929 *
930 * This races with i915_driver_irq_handler() with the result
931 * that either function could miss a vblank event. Here it is not
932 * fatal, as we will either wait upon the next vblank interrupt or
933 * timeout. Generally speaking intel_wait_for_vblank() is only
934 * called during modeset at which time the GPU should be idle and
935 * should *not* be performing page flips and thus not waiting on
936 * vblanks...
937 * Currently, the result of us stealing a vblank from the irq
938 * handler is that a single frame will be skipped during swapbuffers.
939 */
940 I915_WRITE(pipestat_reg,
941 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
942
9d0498a2 943 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 944 if (wait_for(I915_READ(pipestat_reg) &
945 PIPE_VBLANK_INTERRUPT_STATUS,
946 50))
9d0498a2
JB		 947 DRM_DEBUG_KMS("vblank wait timed out\n");
948}
949
ab7ad7f6
KP		 950/*
951 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 952 * @dev: drm device
953 * @pipe: pipe to wait for
954 *
955 * After disabling a pipe, we can't wait for vblank in the usual way,
956 * spinning on the vblank interrupt status bit, since we won't actually
957 * see an interrupt when the pipe is disabled.
958 *
ab7ad7f6
KP		 959 * On Gen4 and above:
960 * wait for the pipe register state bit to turn off
961 *
962 * Otherwise:
963 * wait for the display line value to settle (it usually
964 * ends up stopping at the start of the next frame).
58e10eb9 965 *
9d0498a2 966 */
58e10eb9 967void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 968{
969 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 970 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
971 pipe);
ab7ad7f6
KP		 972
973 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 974 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 975
976 /* Wait for the Pipe State to go off */
58e10eb9
CW		 977 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
978 100))
284637d9 979 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 980 } else {
837ba00f 981 u32 last_line, line_mask;
58e10eb9 982 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 983 unsigned long timeout = jiffies + msecs_to_jiffies(100);
984
837ba00f
PZ		 985 if (IS_GEN2(dev))
986 line_mask = DSL_LINEMASK_GEN2;
987 else
988 line_mask = DSL_LINEMASK_GEN3;
989
ab7ad7f6
KP		 990 /* Wait for the display line to settle */
991 do {
837ba00f 992 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 993 mdelay(5);
837ba00f 994 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 995 time_after(timeout, jiffies));
996 if (time_after(jiffies, timeout))
284637d9 997 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 998 }
79e53945
JB		 999}
1000
b0ea7d37
DL		 1001/*
1002 * ibx_digital_port_connected - is the specified port connected?
1003 * @dev_priv: i915 private structure
1004 * @port: the port to test
1005 *
1006 * Returns true if @port is connected, false otherwise.
1007 */
1008bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1009 struct intel_digital_port *port)
1010{
1011 u32 bit;
1012
c36346e3
DL		 1013 if (HAS_PCH_IBX(dev_priv->dev)) {
1014 switch(port->port) {
1015 case PORT_B:
1016 bit = SDE_PORTB_HOTPLUG;
1017 break;
1018 case PORT_C:
1019 bit = SDE_PORTC_HOTPLUG;
1020 break;
1021 case PORT_D:
1022 bit = SDE_PORTD_HOTPLUG;
1023 break;
1024 default:
1025 return true;
1026 }
1027 } else {
1028 switch(port->port) {
1029 case PORT_B:
1030 bit = SDE_PORTB_HOTPLUG_CPT;
1031 break;
1032 case PORT_C:
1033 bit = SDE_PORTC_HOTPLUG_CPT;
1034 break;
1035 case PORT_D:
1036 bit = SDE_PORTD_HOTPLUG_CPT;
1037 break;
1038 default:
1039 return true;
1040 }
b0ea7d37
DL		 1041 }
1042
1043 return I915_READ(SDEISR) & bit;
1044}
1045
b24e7179
JB		 1046static const char *state_string(bool enabled)
1047{
1048 return enabled ? "on" : "off";
1049}
1050
1051/* Only for pre-ILK configs */
1052static void assert_pll(struct drm_i915_private *dev_priv,
1053 enum pipe pipe, bool state)
1054{
1055 int reg;
1056 u32 val;
1057 bool cur_state;
1058
1059 reg = DPLL(pipe);
1060 val = I915_READ(reg);
1061 cur_state = !!(val & DPLL_VCO_ENABLE);
1062 WARN(cur_state != state,
1063 "PLL state assertion failure (expected %s, current %s)\n",
1064 state_string(state), state_string(cur_state));
1065}
1066#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1067#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1068
040484af
JB		 1069/* For ILK+ */
1070static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1071 struct intel_pch_pll *pll,
1072 struct intel_crtc *crtc,
1073 bool state)
040484af 1074{
040484af
JB		 1075 u32 val;
1076 bool cur_state;
1077
9d82aa17
ED		 1078 if (HAS_PCH_LPT(dev_priv->dev)) {
1079 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1080 return;
1081 }
1082
92b27b08
CW		 1083 if (WARN (!pll,
1084 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1085 return;
ee7b9f93 1086
92b27b08
CW		 1087 val = I915_READ(pll->pll_reg);
1088 cur_state = !!(val & DPLL_VCO_ENABLE);
1089 WARN(cur_state != state,
1090 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1091 pll->pll_reg, state_string(state), state_string(cur_state), val);
1092
1093 /* Make sure the selected PLL is correctly attached to the transcoder */
1094 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1095 u32 pch_dpll;
1096
1097 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1098 cur_state = pll->pll_reg == _PCH_DPLL_B;
1099 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1100 "PLL[%d] not attached to this transcoder %d: %08x\n",
1101 cur_state, crtc->pipe, pch_dpll)) {
1102 cur_state = !!(val >> (4*crtc->pipe + 3));
1103 WARN(cur_state != state,
1104 "PLL[%d] not %s on this transcoder %d: %08x\n",
1105 pll->pll_reg == _PCH_DPLL_B,
1106 state_string(state),
1107 crtc->pipe,
1108 val);
1109 }
d3ccbe86 1110 }
040484af 1111}
92b27b08
CW		 1112#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1113#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1114
1115static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1116 enum pipe pipe, bool state)
1117{
1118 int reg;
1119 u32 val;
1120 bool cur_state;
ad80a810
PZ		 1121 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1122 pipe);
040484af 1123
affa9354
PZ		 1124 if (HAS_DDI(dev_priv->dev)) {
1125 /* DDI does not have a specific FDI_TX register */
ad80a810 1126 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1127 val = I915_READ(reg);
ad80a810 1128 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1129 } else {
1130 reg = FDI_TX_CTL(pipe);
1131 val = I915_READ(reg);
1132 cur_state = !!(val & FDI_TX_ENABLE);
1133 }
040484af
JB		 1134 WARN(cur_state != state,
1135 "FDI TX state assertion failure (expected %s, current %s)\n",
1136 state_string(state), state_string(cur_state));
1137}
1138#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1139#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1140
1141static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1142 enum pipe pipe, bool state)
1143{
1144 int reg;
1145 u32 val;
1146 bool cur_state;
1147
d63fa0dc
PZ		 1148 reg = FDI_RX_CTL(pipe);
1149 val = I915_READ(reg);
1150 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1151 WARN(cur_state != state,
1152 "FDI RX state assertion failure (expected %s, current %s)\n",
1153 state_string(state), state_string(cur_state));
1154}
1155#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1156#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1157
1158static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1159 enum pipe pipe)
1160{
1161 int reg;
1162 u32 val;
1163
1164 /* ILK FDI PLL is always enabled */
1165 if (dev_priv->info->gen == 5)
1166 return;
1167
bf507ef7 1168 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1169 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1170 return;
1171
040484af
JB		 1172 reg = FDI_TX_CTL(pipe);
1173 val = I915_READ(reg);
1174 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1175}
1176
1177static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1178 enum pipe pipe)
1179{
1180 int reg;
1181 u32 val;
1182
1183 reg = FDI_RX_CTL(pipe);
1184 val = I915_READ(reg);
1185 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1186}
1187
ea0760cf
JB		 1188static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1189 enum pipe pipe)
1190{
1191 int pp_reg, lvds_reg;
1192 u32 val;
1193 enum pipe panel_pipe = PIPE_A;
0de3b485 1194 bool locked = true;
ea0760cf
JB		 1195
1196 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1197 pp_reg = PCH_PP_CONTROL;
1198 lvds_reg = PCH_LVDS;
1199 } else {
1200 pp_reg = PP_CONTROL;
1201 lvds_reg = LVDS;
1202 }
1203
1204 val = I915_READ(pp_reg);
1205 if (!(val & PANEL_POWER_ON) ||
1206 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1207 locked = false;
1208
1209 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1210 panel_pipe = PIPE_B;
1211
1212 WARN(panel_pipe == pipe && locked,
1213 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1214 pipe_name(pipe));
ea0760cf
JB		 1215}
1216
b840d907
JB		 1217void assert_pipe(struct drm_i915_private *dev_priv,
1218 enum pipe pipe, bool state)
b24e7179
JB		 1219{
1220 int reg;
1221 u32 val;
63d7bbe9 1222 bool cur_state;
702e7a56
PZ		 1223 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1224 pipe);
b24e7179 1225
8e636784
DV		 1226 /* if we need the pipe A quirk it must be always on */
1227 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1228 state = true;
1229
69310161
PZ		 1230 if (IS_HASWELL(dev_priv->dev) && cpu_transcoder != TRANSCODER_EDP &&
1231 !(I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_ENABLE)) {
1232 cur_state = false;
1233 } else {
1234 reg = PIPECONF(cpu_transcoder);
1235 val = I915_READ(reg);
1236 cur_state = !!(val & PIPECONF_ENABLE);
1237 }
1238
63d7bbe9
JB		 1239 WARN(cur_state != state,
1240 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1241 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1242}
1243
931872fc
CW		 1244static void assert_plane(struct drm_i915_private *dev_priv,
1245 enum plane plane, bool state)
b24e7179
JB		 1246{
1247 int reg;
1248 u32 val;
931872fc 1249 bool cur_state;
b24e7179
JB		 1250
1251 reg = DSPCNTR(plane);
1252 val = I915_READ(reg);
931872fc
CW		 1253 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1254 WARN(cur_state != state,
1255 "plane %c assertion failure (expected %s, current %s)\n",
1256 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1257}
1258
931872fc
CW		 1259#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1260#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1261
b24e7179
JB		 1262static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1263 enum pipe pipe)
1264{
1265 int reg, i;
1266 u32 val;
1267 int cur_pipe;
1268
19ec1358 1269 /* Planes are fixed to pipes on ILK+ */
da6ecc5d 1270 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
28c05794
AJ		 1271 reg = DSPCNTR(pipe);
1272 val = I915_READ(reg);
1273 WARN((val & DISPLAY_PLANE_ENABLE),
1274 "plane %c assertion failure, should be disabled but not\n",
1275 plane_name(pipe));
19ec1358 1276 return;
28c05794 1277 }
19ec1358 1278
b24e7179
JB		 1279 /* Need to check both planes against the pipe */
1280 for (i = 0; i < 2; i++) {
1281 reg = DSPCNTR(i);
1282 val = I915_READ(reg);
1283 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1284 DISPPLANE_SEL_PIPE_SHIFT;
1285 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1286 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1287 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1288 }
1289}
1290
92f2584a
JB		 1291static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1292{
1293 u32 val;
1294 bool enabled;
1295
9d82aa17
ED		 1296 if (HAS_PCH_LPT(dev_priv->dev)) {
1297 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1298 return;
1299 }
1300
92f2584a
JB		 1301 val = I915_READ(PCH_DREF_CONTROL);
1302 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1303 DREF_SUPERSPREAD_SOURCE_MASK));
1304 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1305}
1306
1307static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1308 enum pipe pipe)
1309{
1310 int reg;
1311 u32 val;
1312 bool enabled;
1313
1314 reg = TRANSCONF(pipe);
1315 val = I915_READ(reg);
1316 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1317 WARN(enabled,
1318 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1319 pipe_name(pipe));
92f2584a
JB		 1320}
1321
4e634389
KP		 1322static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1323 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1324{
1325 if ((val & DP_PORT_EN) == 0)
1326 return false;
1327
1328 if (HAS_PCH_CPT(dev_priv->dev)) {
1329 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1330 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1331 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1332 return false;
1333 } else {
1334 if ((val & DP_PIPE_MASK) != (pipe << 30))
1335 return false;
1336 }
1337 return true;
1338}
1339
1519b995
KP		 1340static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1341 enum pipe pipe, u32 val)
1342{
dc0fa718 1343 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1344 return false;
1345
1346 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1347 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1348 return false;
1349 } else {
dc0fa718 1350 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1351 return false;
1352 }
1353 return true;
1354}
1355
1356static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1357 enum pipe pipe, u32 val)
1358{
1359 if ((val & LVDS_PORT_EN) == 0)
1360 return false;
1361
1362 if (HAS_PCH_CPT(dev_priv->dev)) {
1363 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1364 return false;
1365 } else {
1366 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1367 return false;
1368 }
1369 return true;
1370}
1371
1372static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1373 enum pipe pipe, u32 val)
1374{
1375 if ((val & ADPA_DAC_ENABLE) == 0)
1376 return false;
1377 if (HAS_PCH_CPT(dev_priv->dev)) {
1378 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1379 return false;
1380 } else {
1381 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1382 return false;
1383 }
1384 return true;
1385}
1386
291906f1 1387static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1388 enum pipe pipe, int reg, u32 port_sel)
291906f1 1389{
47a05eca 1390 u32 val = I915_READ(reg);
4e634389 1391 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1392 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1393 reg, pipe_name(pipe));
de9a35ab 1394
75c5da27
DV		 1395 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1396 && (val & DP_PIPEB_SELECT),
de9a35ab 1397 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1398}
1399
1400static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1401 enum pipe pipe, int reg)
1402{
47a05eca 1403 u32 val = I915_READ(reg);
b70ad586 1404 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1405 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1406 reg, pipe_name(pipe));
de9a35ab 1407
dc0fa718 1408 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1409 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1410 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1411}
1412
1413static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1414 enum pipe pipe)
1415{
1416 int reg;
1417 u32 val;
291906f1 1418
f0575e92
KP		 1419 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1420 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1421 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1422
1423 reg = PCH_ADPA;
1424 val = I915_READ(reg);
b70ad586 1425 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1426 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1427 pipe_name(pipe));
291906f1
JB		 1428
1429 reg = PCH_LVDS;
1430 val = I915_READ(reg);
b70ad586 1431 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1432 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1433 pipe_name(pipe));
291906f1 1434
e2debe91
PZ		 1435 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1436 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1437 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1438}
1439
63d7bbe9
JB		 1440/**
1441 * intel_enable_pll - enable a PLL
1442 * @dev_priv: i915 private structure
1443 * @pipe: pipe PLL to enable
1444 *
1445 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1446 * make sure the PLL reg is writable first though, since the panel write
1447 * protect mechanism may be enabled.
1448 *
1449 * Note! This is for pre-ILK only.
7434a255
TR		 1450 *
1451 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1452 */
1453static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1454{
1455 int reg;
1456 u32 val;
1457
1458 /* No really, not for ILK+ */
a0c4da24 1459 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1460
1461 /* PLL is protected by panel, make sure we can write it */
1462 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1463 assert_panel_unlocked(dev_priv, pipe);
1464
1465 reg = DPLL(pipe);
1466 val = I915_READ(reg);
1467 val |= DPLL_VCO_ENABLE;
1468
1469 /* We do this three times for luck */
1470 I915_WRITE(reg, val);
1471 POSTING_READ(reg);
1472 udelay(150); /* wait for warmup */
1473 I915_WRITE(reg, val);
1474 POSTING_READ(reg);
1475 udelay(150); /* wait for warmup */
1476 I915_WRITE(reg, val);
1477 POSTING_READ(reg);
1478 udelay(150); /* wait for warmup */
1479}
1480
1481/**
1482 * intel_disable_pll - disable a PLL
1483 * @dev_priv: i915 private structure
1484 * @pipe: pipe PLL to disable
1485 *
1486 * Disable the PLL for @pipe, making sure the pipe is off first.
1487 *
1488 * Note! This is for pre-ILK only.
1489 */
1490static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1491{
1492 int reg;
1493 u32 val;
1494
1495 /* Don't disable pipe A or pipe A PLLs if needed */
1496 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1497 return;
1498
1499 /* Make sure the pipe isn't still relying on us */
1500 assert_pipe_disabled(dev_priv, pipe);
1501
1502 reg = DPLL(pipe);
1503 val = I915_READ(reg);
1504 val &= ~DPLL_VCO_ENABLE;
1505 I915_WRITE(reg, val);
1506 POSTING_READ(reg);
1507}
1508
a416edef
ED		 1509/* SBI access */
1510static void
988d6ee8
PZ		 1511intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1512 enum intel_sbi_destination destination)
a416edef 1513{
988d6ee8 1514 u32 tmp;
a416edef 1515
09153000 1516 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1517
39fb50f6 1518 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1519 100)) {
1520 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1521 return;
a416edef
ED		 1522 }
1523
988d6ee8
PZ		 1524 I915_WRITE(SBI_ADDR, (reg << 16));
1525 I915_WRITE(SBI_DATA, value);
1526
1527 if (destination == SBI_ICLK)
1528 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1529 else
1530 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1531 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
a416edef 1532
39fb50f6 1533 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1534 100)) {
1535 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
09153000 1536 return;
a416edef 1537 }
a416edef
ED		 1538}
1539
1540static u32
988d6ee8
PZ		 1541intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1542 enum intel_sbi_destination destination)
a416edef 1543{
39fb50f6 1544 u32 value = 0;
09153000 1545 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1546
39fb50f6 1547 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1548 100)) {
1549 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1550 return 0;
a416edef
ED		 1551 }
1552
988d6ee8
PZ		 1553 I915_WRITE(SBI_ADDR, (reg << 16));
1554
1555 if (destination == SBI_ICLK)
1556 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1557 else
1558 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1559 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
a416edef 1560
39fb50f6 1561 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1562 100)) {
1563 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
09153000 1564 return 0;
a416edef
ED		 1565 }
1566
09153000 1567 return I915_READ(SBI_DATA);
a416edef
ED		 1568}
1569
92f2584a 1570/**
b6b4e185 1571 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1572 * @dev_priv: i915 private structure
1573 * @pipe: pipe PLL to enable
1574 *
1575 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1576 * drives the transcoder clock.
1577 */
b6b4e185 1578static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1579{
ee7b9f93 1580 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1581 struct intel_pch_pll *pll;
92f2584a
JB		 1582 int reg;
1583 u32 val;
1584
48da64a8 1585 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1586 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1587 pll = intel_crtc->pch_pll;
1588 if (pll == NULL)
1589 return;
1590
1591 if (WARN_ON(pll->refcount == 0))
1592 return;
ee7b9f93
JB		 1593
1594 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1595 pll->pll_reg, pll->active, pll->on,
1596 intel_crtc->base.base.id);
92f2584a
JB		 1597
1598 /* PCH refclock must be enabled first */
1599 assert_pch_refclk_enabled(dev_priv);
1600
ee7b9f93 1601 if (pll->active++ && pll->on) {
92b27b08 1602 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1603 return;
1604 }
1605
1606 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1607
1608 reg = pll->pll_reg;
92f2584a
JB		 1609 val = I915_READ(reg);
1610 val |= DPLL_VCO_ENABLE;
1611 I915_WRITE(reg, val);
1612 POSTING_READ(reg);
1613 udelay(200);
ee7b9f93
JB		 1614
1615 pll->on = true;
92f2584a
JB		 1616}
1617
ee7b9f93 1618static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1619{
ee7b9f93
JB		 1620 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1621 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1622 int reg;
ee7b9f93 1623 u32 val;
4c609cb8 1624
92f2584a
JB		 1625 /* PCH only available on ILK+ */
1626 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1627 if (pll == NULL)
1628 return;
92f2584a 1629
48da64a8
CW		 1630 if (WARN_ON(pll->refcount == 0))
1631 return;
7a419866 1632
ee7b9f93
JB		 1633 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1634 pll->pll_reg, pll->active, pll->on,
1635 intel_crtc->base.base.id);
7a419866 1636
48da64a8 1637 if (WARN_ON(pll->active == 0)) {
92b27b08 1638 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1639 return;
1640 }
1641
ee7b9f93 1642 if (--pll->active) {
92b27b08 1643 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1644 return;
ee7b9f93
JB		 1645 }
1646
1647 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1648
1649 /* Make sure transcoder isn't still depending on us */
1650 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1651
ee7b9f93 1652 reg = pll->pll_reg;
92f2584a
JB		 1653 val = I915_READ(reg);
1654 val &= ~DPLL_VCO_ENABLE;
1655 I915_WRITE(reg, val);
1656 POSTING_READ(reg);
1657 udelay(200);
ee7b9f93
JB		 1658
1659 pll->on = false;
92f2584a
JB		 1660}
1661
b8a4f404
PZ		 1662static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1663 enum pipe pipe)
040484af 1664{
23670b32 1665 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1666 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1667 uint32_t reg, val, pipeconf_val;
040484af
JB		 1668
1669 /* PCH only available on ILK+ */
1670 BUG_ON(dev_priv->info->gen < 5);
1671
1672 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1673 assert_pch_pll_enabled(dev_priv,
1674 to_intel_crtc(crtc)->pch_pll,
1675 to_intel_crtc(crtc));
040484af
JB		 1676
1677 /* FDI must be feeding us bits for PCH ports */
1678 assert_fdi_tx_enabled(dev_priv, pipe);
1679 assert_fdi_rx_enabled(dev_priv, pipe);
1680
23670b32
DV		 1681 if (HAS_PCH_CPT(dev)) {
1682 /* Workaround: Set the timing override bit before enabling the
1683 * pch transcoder. */
1684 reg = TRANS_CHICKEN2(pipe);
1685 val = I915_READ(reg);
1686 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1687 I915_WRITE(reg, val);
59c859d6 1688 }
23670b32 1689
040484af
JB		 1690 reg = TRANSCONF(pipe);
1691 val = I915_READ(reg);
5f7f726d 1692 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1693
1694 if (HAS_PCH_IBX(dev_priv->dev)) {
1695 /*
1696 * make the BPC in transcoder be consistent with
1697 * that in pipeconf reg.
1698 */
dfd07d72
DV		 1699 val &= ~PIPECONF_BPC_MASK;
1700 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1701 }
5f7f726d
PZ		 1702
1703 val &= ~TRANS_INTERLACE_MASK;
1704 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1705 if (HAS_PCH_IBX(dev_priv->dev) &&
1706 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1707 val |= TRANS_LEGACY_INTERLACED_ILK;
1708 else
1709 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1710 else
1711 val |= TRANS_PROGRESSIVE;
1712
040484af
JB		 1713 I915_WRITE(reg, val | TRANS_ENABLE);
1714 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1715 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1716}
1717
8fb033d7 1718static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1719 enum transcoder cpu_transcoder)
040484af 1720{
8fb033d7 1721 u32 val, pipeconf_val;
8fb033d7
PZ		 1722
1723 /* PCH only available on ILK+ */
1724 BUG_ON(dev_priv->info->gen < 5);
1725
8fb033d7 1726 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1727 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1728 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1729
223a6fdf
PZ		 1730 /* Workaround: set timing override bit. */
1731 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1732 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1733 I915_WRITE(_TRANSA_CHICKEN2, val);
1734
25f3ef11 1735 val = TRANS_ENABLE;
937bb610 1736 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1737
9a76b1c6
PZ		 1738 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1739 PIPECONF_INTERLACED_ILK)
a35f2679 1740 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1741 else
1742 val |= TRANS_PROGRESSIVE;
1743
25f3ef11 1744 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
937bb610
PZ		 1745 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1746 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1747}
1748
b8a4f404
PZ		 1749static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1750 enum pipe pipe)
040484af 1751{
23670b32
DV		 1752 struct drm_device *dev = dev_priv->dev;
1753 uint32_t reg, val;
040484af
JB		 1754
1755 /* FDI relies on the transcoder */
1756 assert_fdi_tx_disabled(dev_priv, pipe);
1757 assert_fdi_rx_disabled(dev_priv, pipe);
1758
291906f1
JB		 1759 /* Ports must be off as well */
1760 assert_pch_ports_disabled(dev_priv, pipe);
1761
040484af
JB		 1762 reg = TRANSCONF(pipe);
1763 val = I915_READ(reg);
1764 val &= ~TRANS_ENABLE;
1765 I915_WRITE(reg, val);
1766 /* wait for PCH transcoder off, transcoder state */
1767 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1768 DRM_ERROR("failed to disable transcoder %d\n", pipe);
23670b32
DV		 1769
1770 if (!HAS_PCH_IBX(dev)) {
1771 /* Workaround: Clear the timing override chicken bit again. */
1772 reg = TRANS_CHICKEN2(pipe);
1773 val = I915_READ(reg);
1774 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1775 I915_WRITE(reg, val);
1776 }
040484af
JB		 1777}
1778
ab4d966c 1779static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1780{
8fb033d7
PZ		 1781 u32 val;
1782
8a52fd9f 1783 val = I915_READ(_TRANSACONF);
8fb033d7 1784 val &= ~TRANS_ENABLE;
8a52fd9f 1785 I915_WRITE(_TRANSACONF, val);
8fb033d7 1786 /* wait for PCH transcoder off, transcoder state */
8a52fd9f
PZ		 1787 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1788 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1789
1790 /* Workaround: clear timing override bit. */
1791 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1792 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1793 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1794}
1795
b24e7179 1796/**
309cfea8 1797 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1798 * @dev_priv: i915 private structure
1799 * @pipe: pipe to enable
040484af 1800 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1801 *
1802 * Enable @pipe, making sure that various hardware specific requirements
1803 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1804 *
1805 * @pipe should be %PIPE_A or %PIPE_B.
1806 *
1807 * Will wait until the pipe is actually running (i.e. first vblank) before
1808 * returning.
1809 */
040484af
JB		 1810static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1811 bool pch_port)
b24e7179 1812{
702e7a56
PZ		 1813 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1814 pipe);
1a240d4d 1815 enum pipe pch_transcoder;
b24e7179
JB		 1816 int reg;
1817 u32 val;
1818
681e5811 1819 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1820 pch_transcoder = TRANSCODER_A;
1821 else
1822 pch_transcoder = pipe;
1823
b24e7179
JB		 1824 /*
1825 * A pipe without a PLL won't actually be able to drive bits from
1826 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1827 * need the check.
1828 */
1829 if (!HAS_PCH_SPLIT(dev_priv->dev))
1830 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1831 else {
1832 if (pch_port) {
1833 /* if driving the PCH, we need FDI enabled */
cc391bbb 1834 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1835 assert_fdi_tx_pll_enabled(dev_priv,
1836 (enum pipe) cpu_transcoder);
040484af
JB		 1837 }
1838 /* FIXME: assert CPU port conditions for SNB+ */
1839 }
b24e7179 1840
702e7a56 1841 reg = PIPECONF(cpu_transcoder);
b24e7179 1842 val = I915_READ(reg);
00d70b15
CW		 1843 if (val & PIPECONF_ENABLE)
1844 return;
1845
1846 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1847 intel_wait_for_vblank(dev_priv->dev, pipe);
1848}
1849
1850/**
309cfea8 1851 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1852 * @dev_priv: i915 private structure
1853 * @pipe: pipe to disable
1854 *
1855 * Disable @pipe, making sure that various hardware specific requirements
1856 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1857 *
1858 * @pipe should be %PIPE_A or %PIPE_B.
1859 *
1860 * Will wait until the pipe has shut down before returning.
1861 */
1862static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1863 enum pipe pipe)
1864{
702e7a56
PZ		 1865 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1866 pipe);
b24e7179
JB		 1867 int reg;
1868 u32 val;
1869
1870 /*
1871 * Make sure planes won't keep trying to pump pixels to us,
1872 * or we might hang the display.
1873 */
1874 assert_planes_disabled(dev_priv, pipe);
1875
1876 /* Don't disable pipe A or pipe A PLLs if needed */
1877 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1878 return;
1879
702e7a56 1880 reg = PIPECONF(cpu_transcoder);
b24e7179 1881 val = I915_READ(reg);
00d70b15
CW		 1882 if ((val & PIPECONF_ENABLE) == 0)
1883 return;
1884
1885 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1886 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1887}
1888
d74362c9
KP		 1889/*
1890 * Plane regs are double buffered, going from enabled->disabled needs a
1891 * trigger in order to latch. The display address reg provides this.
1892 */
6f1d69b0 1893void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1894 enum plane plane)
1895{
14f86147
DL		 1896 if (dev_priv->info->gen >= 4)
1897 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1898 else
1899 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1900}
1901
b24e7179
JB		 1902/**
1903 * intel_enable_plane - enable a display plane on a given pipe
1904 * @dev_priv: i915 private structure
1905 * @plane: plane to enable
1906 * @pipe: pipe being fed
1907 *
1908 * Enable @plane on @pipe, making sure that @pipe is running first.
1909 */
1910static void intel_enable_plane(struct drm_i915_private *dev_priv,
1911 enum plane plane, enum pipe pipe)
1912{
1913 int reg;
1914 u32 val;
1915
1916 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1917 assert_pipe_enabled(dev_priv, pipe);
1918
1919 reg = DSPCNTR(plane);
1920 val = I915_READ(reg);
00d70b15
CW		 1921 if (val & DISPLAY_PLANE_ENABLE)
1922 return;
1923
1924 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1925 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1926 intel_wait_for_vblank(dev_priv->dev, pipe);
1927}
1928
b24e7179
JB		 1929/**
1930 * intel_disable_plane - disable a display plane
1931 * @dev_priv: i915 private structure
1932 * @plane: plane to disable
1933 * @pipe: pipe consuming the data
1934 *
1935 * Disable @plane; should be an independent operation.
1936 */
1937static void intel_disable_plane(struct drm_i915_private *dev_priv,
1938 enum plane plane, enum pipe pipe)
1939{
1940 int reg;
1941 u32 val;
1942
1943 reg = DSPCNTR(plane);
1944 val = I915_READ(reg);
00d70b15
CW		 1945 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1946 return;
1947
1948 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1949 intel_flush_display_plane(dev_priv, plane);
1950 intel_wait_for_vblank(dev_priv->dev, pipe);
1951}
1952
693db184
CW		 1953static bool need_vtd_wa(struct drm_device *dev)
1954{
1955#ifdef CONFIG_INTEL_IOMMU
1956 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1957 return true;
1958#endif
1959 return false;
1960}
1961
127bd2ac 1962int
48b956c5 1963intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1964 struct drm_i915_gem_object *obj,
919926ae 1965 struct intel_ring_buffer *pipelined)
6b95a207 1966{
ce453d81 1967 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1968 u32 alignment;
1969 int ret;
1970
05394f39 1971 switch (obj->tiling_mode) {
6b95a207 1972 case I915_TILING_NONE:
534843da
CW		 1973 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1974 alignment = 128 * 1024;
a6c45cf0 1975 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1976 alignment = 4 * 1024;
1977 else
1978 alignment = 64 * 1024;
6b95a207
KH		 1979 break;
1980 case I915_TILING_X:
1981 /* pin() will align the object as required by fence */
1982 alignment = 0;
1983 break;
1984 case I915_TILING_Y:
1985 /* FIXME: Is this true? */
1986 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1987 return -EINVAL;
1988 default:
1989 BUG();
1990 }
1991
693db184
CW		 1992 /* Note that the w/a also requires 64 PTE of padding following the
1993 * bo. We currently fill all unused PTE with the shadow page and so
1994 * we should always have valid PTE following the scanout preventing
1995 * the VT-d warning.
1996 */
1997 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1998 alignment = 256 * 1024;
1999
ce453d81 2000 dev_priv->mm.interruptible = false;
2da3b9b9 2001 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 2002 if (ret)
ce453d81 2003 goto err_interruptible;
6b95a207
KH		 2004
2005 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2006 * fence, whereas 965+ only requires a fence if using
2007 * framebuffer compression. For simplicity, we always install
2008 * a fence as the cost is not that onerous.
2009 */
06d98131 2010 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2011 if (ret)
2012 goto err_unpin;
1690e1eb 2013
9a5a53b3 2014 i915_gem_object_pin_fence(obj);
6b95a207 2015
ce453d81 2016 dev_priv->mm.interruptible = true;
6b95a207 2017 return 0;
48b956c5
CW		 2018
2019err_unpin:
2020 i915_gem_object_unpin(obj);
ce453d81
CW		 2021err_interruptible:
2022 dev_priv->mm.interruptible = true;
48b956c5 2023 return ret;
6b95a207
KH		 2024}
2025
1690e1eb
CW		 2026void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2027{
2028 i915_gem_object_unpin_fence(obj);
2029 i915_gem_object_unpin(obj);
2030}
2031
c2c75131
DV		 2032/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2033 * is assumed to be a power-of-two. */
bc752862
CW		 2034unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2035 unsigned int tiling_mode,
2036 unsigned int cpp,
2037 unsigned int pitch)
c2c75131 2038{
bc752862
CW		 2039 if (tiling_mode != I915_TILING_NONE) {
2040 unsigned int tile_rows, tiles;
c2c75131 2041
bc752862
CW		 2042 tile_rows = *y / 8;
2043 *y %= 8;
c2c75131 2044
bc752862
CW		 2045 tiles = *x / (512/cpp);
2046 *x %= 512/cpp;
2047
2048 return tile_rows * pitch * 8 + tiles * 4096;
2049 } else {
2050 unsigned int offset;
2051
2052 offset = *y * pitch + *x * cpp;
2053 *y = 0;
2054 *x = (offset & 4095) / cpp;
2055 return offset & -4096;
2056 }
c2c75131
DV		 2057}
2058
17638cd6
JB		 2059static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2060 int x, int y)
81255565
JB		 2061{
2062 struct drm_device *dev = crtc->dev;
2063 struct drm_i915_private *dev_priv = dev->dev_private;
2064 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2065 struct intel_framebuffer *intel_fb;
05394f39 2066 struct drm_i915_gem_object *obj;
81255565 2067 int plane = intel_crtc->plane;
e506a0c6 2068 unsigned long linear_offset;
81255565 2069 u32 dspcntr;
5eddb70b 2070 u32 reg;
81255565
JB		 2071
2072 switch (plane) {
2073 case 0:
2074 case 1:
2075 break;
2076 default:
2077 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2078 return -EINVAL;
2079 }
2080
2081 intel_fb = to_intel_framebuffer(fb);
2082 obj = intel_fb->obj;
81255565 2083
5eddb70b
CW		 2084 reg = DSPCNTR(plane);
2085 dspcntr = I915_READ(reg);
81255565
JB		 2086 /* Mask out pixel format bits in case we change it */
2087 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2088 switch (fb->pixel_format) {
2089 case DRM_FORMAT_C8:
81255565
JB		 2090 dspcntr |= DISPPLANE_8BPP;
2091 break;
57779d06
VS		 2092 case DRM_FORMAT_XRGB1555:
2093 case DRM_FORMAT_ARGB1555:
2094 dspcntr |= DISPPLANE_BGRX555;
81255565 2095 break;
57779d06
VS		 2096 case DRM_FORMAT_RGB565:
2097 dspcntr |= DISPPLANE_BGRX565;
2098 break;
2099 case DRM_FORMAT_XRGB8888:
2100 case DRM_FORMAT_ARGB8888:
2101 dspcntr |= DISPPLANE_BGRX888;
2102 break;
2103 case DRM_FORMAT_XBGR8888:
2104 case DRM_FORMAT_ABGR8888:
2105 dspcntr |= DISPPLANE_RGBX888;
2106 break;
2107 case DRM_FORMAT_XRGB2101010:
2108 case DRM_FORMAT_ARGB2101010:
2109 dspcntr |= DISPPLANE_BGRX101010;
2110 break;
2111 case DRM_FORMAT_XBGR2101010:
2112 case DRM_FORMAT_ABGR2101010:
2113 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2114 break;
2115 default:
baba133a 2116 BUG();
81255565 2117 }
57779d06 2118
a6c45cf0 2119 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2120 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2121 dspcntr |= DISPPLANE_TILED;
2122 else
2123 dspcntr &= ~DISPPLANE_TILED;
2124 }
2125
5eddb70b 2126 I915_WRITE(reg, dspcntr);
81255565 2127
e506a0c6 2128 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2129
c2c75131
DV		 2130 if (INTEL_INFO(dev)->gen >= 4) {
2131 intel_crtc->dspaddr_offset =
bc752862
CW		 2132 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2133 fb->bits_per_pixel / 8,
2134 fb->pitches[0]);
c2c75131
DV		 2135 linear_offset -= intel_crtc->dspaddr_offset;
2136 } else {
e506a0c6 2137 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2138 }
e506a0c6
DV		 2139
2140 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2141 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2142 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2143 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2144 I915_MODIFY_DISPBASE(DSPSURF(plane),
2145 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2146 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2147 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2148 } else
e506a0c6 2149 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2150 POSTING_READ(reg);
81255565 2151
17638cd6
JB		 2152 return 0;
2153}
2154
2155static int ironlake_update_plane(struct drm_crtc *crtc,
2156 struct drm_framebuffer *fb, int x, int y)
2157{
2158 struct drm_device *dev = crtc->dev;
2159 struct drm_i915_private *dev_priv = dev->dev_private;
2160 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2161 struct intel_framebuffer *intel_fb;
2162 struct drm_i915_gem_object *obj;
2163 int plane = intel_crtc->plane;
e506a0c6 2164 unsigned long linear_offset;
17638cd6
JB		 2165 u32 dspcntr;
2166 u32 reg;
2167
2168 switch (plane) {
2169 case 0:
2170 case 1:
27f8227b 2171 case 2:
17638cd6
JB		 2172 break;
2173 default:
2174 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2175 return -EINVAL;
2176 }
2177
2178 intel_fb = to_intel_framebuffer(fb);
2179 obj = intel_fb->obj;
2180
2181 reg = DSPCNTR(plane);
2182 dspcntr = I915_READ(reg);
2183 /* Mask out pixel format bits in case we change it */
2184 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2185 switch (fb->pixel_format) {
2186 case DRM_FORMAT_C8:
17638cd6
JB		 2187 dspcntr |= DISPPLANE_8BPP;
2188 break;
57779d06
VS		 2189 case DRM_FORMAT_RGB565:
2190 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2191 break;
57779d06
VS		 2192 case DRM_FORMAT_XRGB8888:
2193 case DRM_FORMAT_ARGB8888:
2194 dspcntr |= DISPPLANE_BGRX888;
2195 break;
2196 case DRM_FORMAT_XBGR8888:
2197 case DRM_FORMAT_ABGR8888:
2198 dspcntr |= DISPPLANE_RGBX888;
2199 break;
2200 case DRM_FORMAT_XRGB2101010:
2201 case DRM_FORMAT_ARGB2101010:
2202 dspcntr |= DISPPLANE_BGRX101010;
2203 break;
2204 case DRM_FORMAT_XBGR2101010:
2205 case DRM_FORMAT_ABGR2101010:
2206 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2207 break;
2208 default:
baba133a 2209 BUG();
17638cd6
JB		 2210 }
2211
2212 if (obj->tiling_mode != I915_TILING_NONE)
2213 dspcntr |= DISPPLANE_TILED;
2214 else
2215 dspcntr &= ~DISPPLANE_TILED;
2216
2217 /* must disable */
2218 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2219
2220 I915_WRITE(reg, dspcntr);
2221
e506a0c6 2222 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2223 intel_crtc->dspaddr_offset =
bc752862
CW		 2224 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2225 fb->bits_per_pixel / 8,
2226 fb->pitches[0]);
c2c75131 2227 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2228
e506a0c6
DV		 2229 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2230 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2231 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2232 I915_MODIFY_DISPBASE(DSPSURF(plane),
2233 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2234 if (IS_HASWELL(dev)) {
2235 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2236 } else {
2237 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2238 I915_WRITE(DSPLINOFF(plane), linear_offset);
2239 }
17638cd6
JB		 2240 POSTING_READ(reg);
2241
2242 return 0;
2243}
2244
2245/* Assume fb object is pinned & idle & fenced and just update base pointers */
2246static int
2247intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2248 int x, int y, enum mode_set_atomic state)
2249{
2250 struct drm_device *dev = crtc->dev;
2251 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2252
6b8e6ed0
CW		 2253 if (dev_priv->display.disable_fbc)
2254 dev_priv->display.disable_fbc(dev);
3dec0095 2255 intel_increase_pllclock(crtc);
81255565 2256
6b8e6ed0 2257 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2258}
2259
96a02917
VS		 2260void intel_display_handle_reset(struct drm_device *dev)
2261{
2262 struct drm_i915_private *dev_priv = dev->dev_private;
2263 struct drm_crtc *crtc;
2264
2265 /*
2266 * Flips in the rings have been nuked by the reset,
2267 * so complete all pending flips so that user space
2268 * will get its events and not get stuck.
2269 *
2270 * Also update the base address of all primary
2271 * planes to the the last fb to make sure we're
2272 * showing the correct fb after a reset.
2273 *
2274 * Need to make two loops over the crtcs so that we
2275 * don't try to grab a crtc mutex before the
2276 * pending_flip_queue really got woken up.
2277 */
2278
2279 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2280 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2281 enum plane plane = intel_crtc->plane;
2282
2283 intel_prepare_page_flip(dev, plane);
2284 intel_finish_page_flip_plane(dev, plane);
2285 }
2286
2287 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2288 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2289
2290 mutex_lock(&crtc->mutex);
2291 if (intel_crtc->active)
2292 dev_priv->display.update_plane(crtc, crtc->fb,
2293 crtc->x, crtc->y);
2294 mutex_unlock(&crtc->mutex);
2295 }
2296}
2297
14667a4b
CW		 2298static int
2299intel_finish_fb(struct drm_framebuffer *old_fb)
2300{
2301 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2302 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2303 bool was_interruptible = dev_priv->mm.interruptible;
2304 int ret;
2305
14667a4b
CW		 2306 /* Big Hammer, we also need to ensure that any pending
2307 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2308 * current scanout is retired before unpinning the old
2309 * framebuffer.
2310 *
2311 * This should only fail upon a hung GPU, in which case we
2312 * can safely continue.
2313 */
2314 dev_priv->mm.interruptible = false;
2315 ret = i915_gem_object_finish_gpu(obj);
2316 dev_priv->mm.interruptible = was_interruptible;
2317
2318 return ret;
2319}
2320
198598d0
VS		 2321static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2322{
2323 struct drm_device *dev = crtc->dev;
2324 struct drm_i915_master_private *master_priv;
2325 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2326
2327 if (!dev->primary->master)
2328 return;
2329
2330 master_priv = dev->primary->master->driver_priv;
2331 if (!master_priv->sarea_priv)
2332 return;
2333
2334 switch (intel_crtc->pipe) {
2335 case 0:
2336 master_priv->sarea_priv->pipeA_x = x;
2337 master_priv->sarea_priv->pipeA_y = y;
2338 break;
2339 case 1:
2340 master_priv->sarea_priv->pipeB_x = x;
2341 master_priv->sarea_priv->pipeB_y = y;
2342 break;
2343 default:
2344 break;
2345 }
2346}
2347
5c3b82e2 2348static int
3c4fdcfb 2349intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2350 struct drm_framebuffer *fb)
79e53945
JB		 2351{
2352 struct drm_device *dev = crtc->dev;
6b8e6ed0 2353 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2354 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2355 struct drm_framebuffer *old_fb;
5c3b82e2 2356 int ret;
79e53945
JB		 2357
2358 /* no fb bound */
94352cf9 2359 if (!fb) {
a5071c2f 2360 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2361 return 0;
2362 }
2363
7eb552ae 2364 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
5826eca5
ED		 2365 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2366 intel_crtc->plane,
7eb552ae 2367 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2368 return -EINVAL;
79e53945
JB		 2369 }
2370
5c3b82e2 2371 mutex_lock(&dev->struct_mutex);
265db958 2372 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2373 to_intel_framebuffer(fb)->obj,
919926ae 2374 NULL);
5c3b82e2
CW		 2375 if (ret != 0) {
2376 mutex_unlock(&dev->struct_mutex);
a5071c2f 2377 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2378 return ret;
2379 }
79e53945 2380
94352cf9 2381 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2382 if (ret) {
94352cf9 2383 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2384 mutex_unlock(&dev->struct_mutex);
a5071c2f 2385 DRM_ERROR("failed to update base address\n");
4e6cfefc 2386 return ret;
79e53945 2387 }
3c4fdcfb 2388
94352cf9
DV		 2389 old_fb = crtc->fb;
2390 crtc->fb = fb;
6c4c86f5
DV		 2391 crtc->x = x;
2392 crtc->y = y;
94352cf9 2393
b7f1de28
CW		 2394 if (old_fb) {
2395 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2396 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2397 }
652c393a 2398
6b8e6ed0 2399 intel_update_fbc(dev);
5c3b82e2 2400 mutex_unlock(&dev->struct_mutex);
79e53945 2401
198598d0 2402 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2403
2404 return 0;
79e53945
JB		 2405}
2406
5e84e1a4
ZW		 2407static void intel_fdi_normal_train(struct drm_crtc *crtc)
2408{
2409 struct drm_device *dev = crtc->dev;
2410 struct drm_i915_private *dev_priv = dev->dev_private;
2411 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2412 int pipe = intel_crtc->pipe;
2413 u32 reg, temp;
2414
2415 /* enable normal train */
2416 reg = FDI_TX_CTL(pipe);
2417 temp = I915_READ(reg);
61e499bf 2418 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2419 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2420 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2421 } else {
2422 temp &= ~FDI_LINK_TRAIN_NONE;
2423 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2424 }
5e84e1a4
ZW		 2425 I915_WRITE(reg, temp);
2426
2427 reg = FDI_RX_CTL(pipe);
2428 temp = I915_READ(reg);
2429 if (HAS_PCH_CPT(dev)) {
2430 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2431 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2432 } else {
2433 temp &= ~FDI_LINK_TRAIN_NONE;
2434 temp |= FDI_LINK_TRAIN_NONE;
2435 }
2436 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2437
2438 /* wait one idle pattern time */
2439 POSTING_READ(reg);
2440 udelay(1000);
357555c0
JB		 2441
2442 /* IVB wants error correction enabled */
2443 if (IS_IVYBRIDGE(dev))
2444 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2445 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2446}
2447
01a415fd
DV		 2448static void ivb_modeset_global_resources(struct drm_device *dev)
2449{
2450 struct drm_i915_private *dev_priv = dev->dev_private;
2451 struct intel_crtc *pipe_B_crtc =
2452 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2453 struct intel_crtc *pipe_C_crtc =
2454 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2455 uint32_t temp;
2456
2457 /* When everything is off disable fdi C so that we could enable fdi B
2458 * with all lanes. XXX: This misses the case where a pipe is not using
2459 * any pch resources and so doesn't need any fdi lanes. */
2460 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2461 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2462 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2463
2464 temp = I915_READ(SOUTH_CHICKEN1);
2465 temp &= ~FDI_BC_BIFURCATION_SELECT;
2466 DRM_DEBUG_KMS("disabling fdi C rx\n");
2467 I915_WRITE(SOUTH_CHICKEN1, temp);
2468 }
2469}
2470
8db9d77b
ZW		 2471/* The FDI link training functions for ILK/Ibexpeak. */
2472static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2473{
2474 struct drm_device *dev = crtc->dev;
2475 struct drm_i915_private *dev_priv = dev->dev_private;
2476 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2477 int pipe = intel_crtc->pipe;
0fc932b8 2478 int plane = intel_crtc->plane;
5eddb70b 2479 u32 reg, temp, tries;
8db9d77b 2480
0fc932b8
JB		 2481 /* FDI needs bits from pipe & plane first */
2482 assert_pipe_enabled(dev_priv, pipe);
2483 assert_plane_enabled(dev_priv, plane);
2484
e1a44743
AJ		 2485 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2486 for train result */
5eddb70b
CW		 2487 reg = FDI_RX_IMR(pipe);
2488 temp = I915_READ(reg);
e1a44743
AJ		 2489 temp &= ~FDI_RX_SYMBOL_LOCK;
2490 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2491 I915_WRITE(reg, temp);
2492 I915_READ(reg);
e1a44743
AJ		 2493 udelay(150);
2494
8db9d77b 2495 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2496 reg = FDI_TX_CTL(pipe);
2497 temp = I915_READ(reg);
77ffb597
AJ		 2498 temp &= ~(7 << 19);
2499 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2500 temp &= ~FDI_LINK_TRAIN_NONE;
2501 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2502 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2503
5eddb70b
CW		 2504 reg = FDI_RX_CTL(pipe);
2505 temp = I915_READ(reg);
8db9d77b
ZW		 2506 temp &= ~FDI_LINK_TRAIN_NONE;
2507 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2508 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2509
2510 POSTING_READ(reg);
8db9d77b
ZW		 2511 udelay(150);
2512
5b2adf89 2513 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2514 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2515 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2516 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2517
5eddb70b 2518 reg = FDI_RX_IIR(pipe);
e1a44743 2519 for (tries = 0; tries < 5; tries++) {
5eddb70b 2520 temp = I915_READ(reg);
8db9d77b
ZW		 2521 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2522
2523 if ((temp & FDI_RX_BIT_LOCK)) {
2524 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2525 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2526 break;
2527 }
8db9d77b 2528 }
e1a44743 2529 if (tries == 5)
5eddb70b 2530 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2531
2532 /* Train 2 */
5eddb70b
CW		 2533 reg = FDI_TX_CTL(pipe);
2534 temp = I915_READ(reg);
8db9d77b
ZW		 2535 temp &= ~FDI_LINK_TRAIN_NONE;
2536 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2537 I915_WRITE(reg, temp);
8db9d77b 2538
5eddb70b
CW		 2539 reg = FDI_RX_CTL(pipe);
2540 temp = I915_READ(reg);
8db9d77b
ZW		 2541 temp &= ~FDI_LINK_TRAIN_NONE;
2542 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2543 I915_WRITE(reg, temp);
8db9d77b 2544
5eddb70b
CW		 2545 POSTING_READ(reg);
2546 udelay(150);
8db9d77b 2547
5eddb70b 2548 reg = FDI_RX_IIR(pipe);
e1a44743 2549 for (tries = 0; tries < 5; tries++) {
5eddb70b 2550 temp = I915_READ(reg);
8db9d77b
ZW		 2551 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2552
2553 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2554 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2555 DRM_DEBUG_KMS("FDI train 2 done.\n");
2556 break;
2557 }
8db9d77b 2558 }
e1a44743 2559 if (tries == 5)
5eddb70b 2560 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2561
2562 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2563
8db9d77b
ZW		 2564}
2565
0206e353 2566static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2567 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2568 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2569 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2570 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2571};
2572
2573/* The FDI link training functions for SNB/Cougarpoint. */
2574static void gen6_fdi_link_train(struct drm_crtc *crtc)
2575{
2576 struct drm_device *dev = crtc->dev;
2577 struct drm_i915_private *dev_priv = dev->dev_private;
2578 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2579 int pipe = intel_crtc->pipe;
fa37d39e 2580 u32 reg, temp, i, retry;
8db9d77b 2581
e1a44743
AJ		 2582 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2583 for train result */
5eddb70b
CW		 2584 reg = FDI_RX_IMR(pipe);
2585 temp = I915_READ(reg);
e1a44743
AJ		 2586 temp &= ~FDI_RX_SYMBOL_LOCK;
2587 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2588 I915_WRITE(reg, temp);
2589
2590 POSTING_READ(reg);
e1a44743
AJ		 2591 udelay(150);
2592
8db9d77b 2593 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2594 reg = FDI_TX_CTL(pipe);
2595 temp = I915_READ(reg);
77ffb597
AJ		 2596 temp &= ~(7 << 19);
2597 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2598 temp &= ~FDI_LINK_TRAIN_NONE;
2599 temp |= FDI_LINK_TRAIN_PATTERN_1;
2600 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2601 /* SNB-B */
2602 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2603 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2604
d74cf324
DV		 2605 I915_WRITE(FDI_RX_MISC(pipe),
2606 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2607
5eddb70b
CW		 2608 reg = FDI_RX_CTL(pipe);
2609 temp = I915_READ(reg);
8db9d77b
ZW		 2610 if (HAS_PCH_CPT(dev)) {
2611 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2612 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2613 } else {
2614 temp &= ~FDI_LINK_TRAIN_NONE;
2615 temp |= FDI_LINK_TRAIN_PATTERN_1;
2616 }
5eddb70b
CW		 2617 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2618
2619 POSTING_READ(reg);
8db9d77b
ZW		 2620 udelay(150);
2621
0206e353 2622 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2623 reg = FDI_TX_CTL(pipe);
2624 temp = I915_READ(reg);
8db9d77b
ZW		 2625 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2626 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2627 I915_WRITE(reg, temp);
2628
2629 POSTING_READ(reg);
8db9d77b
ZW		 2630 udelay(500);
2631
fa37d39e
SP		 2632 for (retry = 0; retry < 5; retry++) {
2633 reg = FDI_RX_IIR(pipe);
2634 temp = I915_READ(reg);
2635 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2636 if (temp & FDI_RX_BIT_LOCK) {
2637 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2638 DRM_DEBUG_KMS("FDI train 1 done.\n");
2639 break;
2640 }
2641 udelay(50);
8db9d77b 2642 }
fa37d39e
SP		 2643 if (retry < 5)
2644 break;
8db9d77b
ZW		 2645 }
2646 if (i == 4)
5eddb70b 2647 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2648
2649 /* Train 2 */
5eddb70b
CW		 2650 reg = FDI_TX_CTL(pipe);
2651 temp = I915_READ(reg);
8db9d77b
ZW		 2652 temp &= ~FDI_LINK_TRAIN_NONE;
2653 temp |= FDI_LINK_TRAIN_PATTERN_2;
2654 if (IS_GEN6(dev)) {
2655 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2656 /* SNB-B */
2657 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2658 }
5eddb70b 2659 I915_WRITE(reg, temp);
8db9d77b 2660
5eddb70b
CW		 2661 reg = FDI_RX_CTL(pipe);
2662 temp = I915_READ(reg);
8db9d77b
ZW		 2663 if (HAS_PCH_CPT(dev)) {
2664 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2665 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2666 } else {
2667 temp &= ~FDI_LINK_TRAIN_NONE;
2668 temp |= FDI_LINK_TRAIN_PATTERN_2;
2669 }
5eddb70b
CW		 2670 I915_WRITE(reg, temp);
2671
2672 POSTING_READ(reg);
8db9d77b
ZW		 2673 udelay(150);
2674
0206e353 2675 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2676 reg = FDI_TX_CTL(pipe);
2677 temp = I915_READ(reg);
8db9d77b
ZW		 2678 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2679 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2680 I915_WRITE(reg, temp);
2681
2682 POSTING_READ(reg);
8db9d77b
ZW		 2683 udelay(500);
2684
fa37d39e
SP		 2685 for (retry = 0; retry < 5; retry++) {
2686 reg = FDI_RX_IIR(pipe);
2687 temp = I915_READ(reg);
2688 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2689 if (temp & FDI_RX_SYMBOL_LOCK) {
2690 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2691 DRM_DEBUG_KMS("FDI train 2 done.\n");
2692 break;
2693 }
2694 udelay(50);
8db9d77b 2695 }
fa37d39e
SP		 2696 if (retry < 5)
2697 break;
8db9d77b
ZW		 2698 }
2699 if (i == 4)
5eddb70b 2700 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2701
2702 DRM_DEBUG_KMS("FDI train done.\n");
2703}
2704
357555c0
JB		 2705/* Manual link training for Ivy Bridge A0 parts */
2706static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2707{
2708 struct drm_device *dev = crtc->dev;
2709 struct drm_i915_private *dev_priv = dev->dev_private;
2710 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2711 int pipe = intel_crtc->pipe;
2712 u32 reg, temp, i;
2713
2714 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2715 for train result */
2716 reg = FDI_RX_IMR(pipe);
2717 temp = I915_READ(reg);
2718 temp &= ~FDI_RX_SYMBOL_LOCK;
2719 temp &= ~FDI_RX_BIT_LOCK;
2720 I915_WRITE(reg, temp);
2721
2722 POSTING_READ(reg);
2723 udelay(150);
2724
01a415fd
DV		 2725 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2726 I915_READ(FDI_RX_IIR(pipe)));
2727
357555c0
JB		 2728 /* enable CPU FDI TX and PCH FDI RX */
2729 reg = FDI_TX_CTL(pipe);
2730 temp = I915_READ(reg);
2731 temp &= ~(7 << 19);
2732 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2733 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2734 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2735 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2736 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2737 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2738 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2739
d74cf324
DV		 2740 I915_WRITE(FDI_RX_MISC(pipe),
2741 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2742
357555c0
JB		 2743 reg = FDI_RX_CTL(pipe);
2744 temp = I915_READ(reg);
2745 temp &= ~FDI_LINK_TRAIN_AUTO;
2746 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2747 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2748 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2749 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2750
2751 POSTING_READ(reg);
2752 udelay(150);
2753
0206e353 2754 for (i = 0; i < 4; i++) {
357555c0
JB		 2755 reg = FDI_TX_CTL(pipe);
2756 temp = I915_READ(reg);
2757 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2758 temp |= snb_b_fdi_train_param[i];
2759 I915_WRITE(reg, temp);
2760
2761 POSTING_READ(reg);
2762 udelay(500);
2763
2764 reg = FDI_RX_IIR(pipe);
2765 temp = I915_READ(reg);
2766 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2767
2768 if (temp & FDI_RX_BIT_LOCK ||
2769 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2770 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2771 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2772 break;
2773 }
2774 }
2775 if (i == 4)
2776 DRM_ERROR("FDI train 1 fail!\n");
2777
2778 /* Train 2 */
2779 reg = FDI_TX_CTL(pipe);
2780 temp = I915_READ(reg);
2781 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2782 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2783 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2784 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2785 I915_WRITE(reg, temp);
2786
2787 reg = FDI_RX_CTL(pipe);
2788 temp = I915_READ(reg);
2789 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2790 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2791 I915_WRITE(reg, temp);
2792
2793 POSTING_READ(reg);
2794 udelay(150);
2795
0206e353 2796 for (i = 0; i < 4; i++) {
357555c0
JB		 2797 reg = FDI_TX_CTL(pipe);
2798 temp = I915_READ(reg);
2799 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2800 temp |= snb_b_fdi_train_param[i];
2801 I915_WRITE(reg, temp);
2802
2803 POSTING_READ(reg);
2804 udelay(500);
2805
2806 reg = FDI_RX_IIR(pipe);
2807 temp = I915_READ(reg);
2808 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2809
2810 if (temp & FDI_RX_SYMBOL_LOCK) {
2811 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2812 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2813 break;
2814 }
2815 }
2816 if (i == 4)
2817 DRM_ERROR("FDI train 2 fail!\n");
2818
2819 DRM_DEBUG_KMS("FDI train done.\n");
2820}
2821
88cefb6c 2822static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2823{
88cefb6c 2824 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2825 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2826 int pipe = intel_crtc->pipe;
5eddb70b 2827 u32 reg, temp;
79e53945 2828
c64e311e 2829
c98e9dcf 2830 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2831 reg = FDI_RX_CTL(pipe);
2832 temp = I915_READ(reg);
2833 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2834 temp |= (intel_crtc->fdi_lanes - 1) << 19;
dfd07d72 2835 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2836 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2837
2838 POSTING_READ(reg);
c98e9dcf
JB		 2839 udelay(200);
2840
2841 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2842 temp = I915_READ(reg);
2843 I915_WRITE(reg, temp | FDI_PCDCLK);
2844
2845 POSTING_READ(reg);
c98e9dcf
JB		 2846 udelay(200);
2847
20749730
PZ		 2848 /* Enable CPU FDI TX PLL, always on for Ironlake */
2849 reg = FDI_TX_CTL(pipe);
2850 temp = I915_READ(reg);
2851 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2852 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2853
20749730
PZ		 2854 POSTING_READ(reg);
2855 udelay(100);
6be4a607 2856 }
0e23b99d
JB		 2857}
2858
88cefb6c
DV		 2859static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2860{
2861 struct drm_device *dev = intel_crtc->base.dev;
2862 struct drm_i915_private *dev_priv = dev->dev_private;
2863 int pipe = intel_crtc->pipe;
2864 u32 reg, temp;
2865
2866 /* Switch from PCDclk to Rawclk */
2867 reg = FDI_RX_CTL(pipe);
2868 temp = I915_READ(reg);
2869 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2870
2871 /* Disable CPU FDI TX PLL */
2872 reg = FDI_TX_CTL(pipe);
2873 temp = I915_READ(reg);
2874 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2875
2876 POSTING_READ(reg);
2877 udelay(100);
2878
2879 reg = FDI_RX_CTL(pipe);
2880 temp = I915_READ(reg);
2881 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2882
2883 /* Wait for the clocks to turn off. */
2884 POSTING_READ(reg);
2885 udelay(100);
2886}
2887
0fc932b8
JB		 2888static void ironlake_fdi_disable(struct drm_crtc *crtc)
2889{
2890 struct drm_device *dev = crtc->dev;
2891 struct drm_i915_private *dev_priv = dev->dev_private;
2892 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2893 int pipe = intel_crtc->pipe;
2894 u32 reg, temp;
2895
2896 /* disable CPU FDI tx and PCH FDI rx */
2897 reg = FDI_TX_CTL(pipe);
2898 temp = I915_READ(reg);
2899 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2900 POSTING_READ(reg);
2901
2902 reg = FDI_RX_CTL(pipe);
2903 temp = I915_READ(reg);
2904 temp &= ~(0x7 << 16);
dfd07d72 2905 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2906 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2907
2908 POSTING_READ(reg);
2909 udelay(100);
2910
2911 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2912 if (HAS_PCH_IBX(dev)) {
2913 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2914 }
0fc932b8
JB		 2915
2916 /* still set train pattern 1 */
2917 reg = FDI_TX_CTL(pipe);
2918 temp = I915_READ(reg);
2919 temp &= ~FDI_LINK_TRAIN_NONE;
2920 temp |= FDI_LINK_TRAIN_PATTERN_1;
2921 I915_WRITE(reg, temp);
2922
2923 reg = FDI_RX_CTL(pipe);
2924 temp = I915_READ(reg);
2925 if (HAS_PCH_CPT(dev)) {
2926 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2927 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2928 } else {
2929 temp &= ~FDI_LINK_TRAIN_NONE;
2930 temp |= FDI_LINK_TRAIN_PATTERN_1;
2931 }
2932 /* BPC in FDI rx is consistent with that in PIPECONF */
2933 temp &= ~(0x07 << 16);
dfd07d72 2934 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2935 I915_WRITE(reg, temp);
2936
2937 POSTING_READ(reg);
2938 udelay(100);
2939}
2940
5bb61643
CW		 2941static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2942{
2943 struct drm_device *dev = crtc->dev;
2944 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2945 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2946 unsigned long flags;
2947 bool pending;
2948
10d83730
VS		 2949 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2950 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2951 return false;
2952
2953 spin_lock_irqsave(&dev->event_lock, flags);
2954 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2955 spin_unlock_irqrestore(&dev->event_lock, flags);
2956
2957 return pending;
2958}
2959
e6c3a2a6
CW		 2960static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2961{
0f91128d 2962 struct drm_device *dev = crtc->dev;
5bb61643 2963 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2964
2965 if (crtc->fb == NULL)
2966 return;
2967
2c10d571
DV		 2968 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2969
5bb61643
CW		 2970 wait_event(dev_priv->pending_flip_queue,
2971 !intel_crtc_has_pending_flip(crtc));
2972
0f91128d
CW		 2973 mutex_lock(&dev->struct_mutex);
2974 intel_finish_fb(crtc->fb);
2975 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2976}
2977
fc316cbe
PZ		 2978static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2979{
2980 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2981}
2982
e615efe4
ED		 2983/* Program iCLKIP clock to the desired frequency */
2984static void lpt_program_iclkip(struct drm_crtc *crtc)
2985{
2986 struct drm_device *dev = crtc->dev;
2987 struct drm_i915_private *dev_priv = dev->dev_private;
2988 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2989 u32 temp;
2990
09153000
DV		 2991 mutex_lock(&dev_priv->dpio_lock);
2992
e615efe4
ED		 2993 /* It is necessary to ungate the pixclk gate prior to programming
2994 * the divisors, and gate it back when it is done.
2995 */
2996 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2997
2998 /* Disable SSCCTL */
2999 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3000 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3001 SBI_SSCCTL_DISABLE,
3002 SBI_ICLK);
e615efe4
ED		 3003
3004 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3005 if (crtc->mode.clock == 20000) {
3006 auxdiv = 1;
3007 divsel = 0x41;
3008 phaseinc = 0x20;
3009 } else {
3010 /* The iCLK virtual clock root frequency is in MHz,
3011 * but the crtc->mode.clock in in KHz. To get the divisors,
3012 * it is necessary to divide one by another, so we
3013 * convert the virtual clock precision to KHz here for higher
3014 * precision.
3015 */
3016 u32 iclk_virtual_root_freq = 172800 * 1000;
3017 u32 iclk_pi_range = 64;
3018 u32 desired_divisor, msb_divisor_value, pi_value;
3019
3020 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3021 msb_divisor_value = desired_divisor / iclk_pi_range;
3022 pi_value = desired_divisor % iclk_pi_range;
3023
3024 auxdiv = 0;
3025 divsel = msb_divisor_value - 2;
3026 phaseinc = pi_value;
3027 }
3028
3029 /* This should not happen with any sane values */
3030 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3031 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3032 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3033 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3034
3035 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3036 crtc->mode.clock,
3037 auxdiv,
3038 divsel,
3039 phasedir,
3040 phaseinc);
3041
3042 /* Program SSCDIVINTPHASE6 */
988d6ee8 3043 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3044 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3045 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3046 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3047 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3048 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3049 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3050 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3051
3052 /* Program SSCAUXDIV */
988d6ee8 3053 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3054 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3055 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3056 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3057
3058 /* Enable modulator and associated divider */
988d6ee8 3059 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3060 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3061 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3062
3063 /* Wait for initialization time */
3064 udelay(24);
3065
3066 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 3067
3068 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 3069}
3070
f67a559d
JB		 3071/*
3072 * Enable PCH resources required for PCH ports:
3073 * - PCH PLLs
3074 * - FDI training & RX/TX
3075 * - update transcoder timings
3076 * - DP transcoding bits
3077 * - transcoder
3078 */
3079static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3080{
3081 struct drm_device *dev = crtc->dev;
3082 struct drm_i915_private *dev_priv = dev->dev_private;
3083 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3084 int pipe = intel_crtc->pipe;
ee7b9f93 3085 u32 reg, temp;
2c07245f 3086
e7e164db
CW		 3087 assert_transcoder_disabled(dev_priv, pipe);
3088
cd986abb
DV		 3089 /* Write the TU size bits before fdi link training, so that error
3090 * detection works. */
3091 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3092 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3093
c98e9dcf 3094 /* For PCH output, training FDI link */
674cf967 3095 dev_priv->display.fdi_link_train(crtc);
2c07245f 3096
572deb37
DV		 3097 /* XXX: pch pll's can be enabled any time before we enable the PCH
3098 * transcoder, and we actually should do this to not upset any PCH
3099 * transcoder that already use the clock when we share it.
3100 *
3101 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3102 * unconditionally resets the pll - we need that to have the right LVDS
3103 * enable sequence. */
b6b4e185 3104 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 3105
303b81e0 3106 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3107 u32 sel;
4b645f14 3108
c98e9dcf 3109 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3110 switch (pipe) {
3111 default:
3112 case 0:
3113 temp |= TRANSA_DPLL_ENABLE;
3114 sel = TRANSA_DPLLB_SEL;
3115 break;
3116 case 1:
3117 temp |= TRANSB_DPLL_ENABLE;
3118 sel = TRANSB_DPLLB_SEL;
3119 break;
3120 case 2:
3121 temp |= TRANSC_DPLL_ENABLE;
3122 sel = TRANSC_DPLLB_SEL;
3123 break;
d64311ab 3124 }
ee7b9f93
JB		 3125 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3126 temp |= sel;
3127 else
3128 temp &= ~sel;
c98e9dcf 3129 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3130 }
5eddb70b 3131
d9b6cb56
JB		 3132 /* set transcoder timing, panel must allow it */
3133 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3134 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3135 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3136 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3137
5eddb70b
CW		 3138 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3139 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3140 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3141 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3142
303b81e0 3143 intel_fdi_normal_train(crtc);
5e84e1a4 3144
c98e9dcf
JB		 3145 /* For PCH DP, enable TRANS_DP_CTL */
3146 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3147 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3148 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3149 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3150 reg = TRANS_DP_CTL(pipe);
3151 temp = I915_READ(reg);
3152 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3153 TRANS_DP_SYNC_MASK |
3154 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3155 temp |= (TRANS_DP_OUTPUT_ENABLE |
3156 TRANS_DP_ENH_FRAMING);
9325c9f0 3157 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3158
3159 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3160 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3161 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3162 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3163
3164 switch (intel_trans_dp_port_sel(crtc)) {
3165 case PCH_DP_B:
5eddb70b 3166 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3167 break;
3168 case PCH_DP_C:
5eddb70b 3169 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3170 break;
3171 case PCH_DP_D:
5eddb70b 3172 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3173 break;
3174 default:
e95d41e1 3175 BUG();
32f9d658 3176 }
2c07245f 3177
5eddb70b 3178 I915_WRITE(reg, temp);
6be4a607 3179 }
b52eb4dc 3180
b8a4f404 3181 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3182}
3183
1507e5bd
PZ		 3184static void lpt_pch_enable(struct drm_crtc *crtc)
3185{
3186 struct drm_device *dev = crtc->dev;
3187 struct drm_i915_private *dev_priv = dev->dev_private;
3188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
daed2dbb 3189 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
1507e5bd 3190
daed2dbb 3191 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3192
8c52b5e8 3193 lpt_program_iclkip(crtc);
1507e5bd 3194
0540e488 3195 /* Set transcoder timing. */
daed2dbb
PZ		 3196 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3197 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3198 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
1507e5bd 3199
daed2dbb
PZ		 3200 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3201 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3202 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3203 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
1507e5bd 3204
937bb610 3205 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3206}
3207
ee7b9f93
JB		 3208static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3209{
3210 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3211
3212 if (pll == NULL)
3213 return;
3214
3215 if (pll->refcount == 0) {
3216 WARN(1, "bad PCH PLL refcount\n");
3217 return;
3218 }
3219
3220 --pll->refcount;
3221 intel_crtc->pch_pll = NULL;
3222}
3223
3224static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3225{
3226 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3227 struct intel_pch_pll *pll;
3228 int i;
3229
3230 pll = intel_crtc->pch_pll;
3231 if (pll) {
3232 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3233 intel_crtc->base.base.id, pll->pll_reg);
3234 goto prepare;
3235 }
3236
98b6bd99
DV		 3237 if (HAS_PCH_IBX(dev_priv->dev)) {
3238 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3239 i = intel_crtc->pipe;
3240 pll = &dev_priv->pch_plls[i];
3241
3242 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3243 intel_crtc->base.base.id, pll->pll_reg);
3244
3245 goto found;
3246 }
3247
ee7b9f93
JB		 3248 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3249 pll = &dev_priv->pch_plls[i];
3250
3251 /* Only want to check enabled timings first */
3252 if (pll->refcount == 0)
3253 continue;
3254
3255 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3256 fp == I915_READ(pll->fp0_reg)) {
3257 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3258 intel_crtc->base.base.id,
3259 pll->pll_reg, pll->refcount, pll->active);
3260
3261 goto found;
3262 }
3263 }
3264
3265 /* Ok no matching timings, maybe there's a free one? */
3266 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3267 pll = &dev_priv->pch_plls[i];
3268 if (pll->refcount == 0) {
3269 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3270 intel_crtc->base.base.id, pll->pll_reg);
3271 goto found;
3272 }
3273 }
3274
3275 return NULL;
3276
3277found:
3278 intel_crtc->pch_pll = pll;
3279 pll->refcount++;
3280 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3281prepare: /* separate function? */
3282 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3283
e04c7350
CW		 3284 /* Wait for the clocks to stabilize before rewriting the regs */
3285 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3286 POSTING_READ(pll->pll_reg);
3287 udelay(150);
e04c7350
CW		 3288
3289 I915_WRITE(pll->fp0_reg, fp);
3290 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3291 pll->on = false;
3292 return pll;
3293}
3294
d4270e57
JB		 3295void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3296{
3297 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3298 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3299 u32 temp;
3300
3301 temp = I915_READ(dslreg);
3302 udelay(500);
3303 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57
JB		 3304 if (wait_for(I915_READ(dslreg) != temp, 5))
3305 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3306 }
3307}
3308
f67a559d
JB		 3309static void ironlake_crtc_enable(struct drm_crtc *crtc)
3310{
3311 struct drm_device *dev = crtc->dev;
3312 struct drm_i915_private *dev_priv = dev->dev_private;
3313 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3314 struct intel_encoder *encoder;
f67a559d
JB		 3315 int pipe = intel_crtc->pipe;
3316 int plane = intel_crtc->plane;
3317 u32 temp;
f67a559d 3318
08a48469
DV		 3319 WARN_ON(!crtc->enabled);
3320
f67a559d
JB		 3321 if (intel_crtc->active)
3322 return;
3323
3324 intel_crtc->active = true;
3325 intel_update_watermarks(dev);
3326
3327 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3328 temp = I915_READ(PCH_LVDS);
3329 if ((temp & LVDS_PORT_EN) == 0)
3330 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3331 }
3332
f67a559d 3333
5bfe2ac0 3334 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3335 /* Note: FDI PLL enabling _must_ be done before we enable the
3336 * cpu pipes, hence this is separate from all the other fdi/pch
3337 * enabling. */
88cefb6c 3338 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3339 } else {
3340 assert_fdi_tx_disabled(dev_priv, pipe);
3341 assert_fdi_rx_disabled(dev_priv, pipe);
3342 }
f67a559d 3343
bf49ec8c
DV		 3344 for_each_encoder_on_crtc(dev, crtc, encoder)
3345 if (encoder->pre_enable)
3346 encoder->pre_enable(encoder);
f67a559d
JB		 3347
3348 /* Enable panel fitting for LVDS */
3349 if (dev_priv->pch_pf_size &&
547dc041
JN		 3350 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3351 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
f67a559d
JB		 3352 /* Force use of hard-coded filter coefficients
3353 * as some pre-programmed values are broken,
3354 * e.g. x201.
3355 */
13888d78
PZ		 3356 if (IS_IVYBRIDGE(dev))
3357 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3358 PF_PIPE_SEL_IVB(pipe));
3359 else
3360 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
9db4a9c7
JB		 3361 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3362 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3363 }
3364
9c54c0dd
JB		 3365 /*
3366 * On ILK+ LUT must be loaded before the pipe is running but with
3367 * clocks enabled
3368 */
3369 intel_crtc_load_lut(crtc);
3370
5bfe2ac0
DV		 3371 intel_enable_pipe(dev_priv, pipe,
3372 intel_crtc->config.has_pch_encoder);
f67a559d
JB		 3373 intel_enable_plane(dev_priv, plane, pipe);
3374
5bfe2ac0 3375 if (intel_crtc->config.has_pch_encoder)
f67a559d 3376 ironlake_pch_enable(crtc);
c98e9dcf 3377
d1ebd816 3378 mutex_lock(&dev->struct_mutex);
bed4a673 3379 intel_update_fbc(dev);
d1ebd816
BW		 3380 mutex_unlock(&dev->struct_mutex);
3381
6b383a7f 3382 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3383
fa5c73b1
DV		 3384 for_each_encoder_on_crtc(dev, crtc, encoder)
3385 encoder->enable(encoder);
61b77ddd
DV		 3386
3387 if (HAS_PCH_CPT(dev))
3388 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3389
3390 /*
3391 * There seems to be a race in PCH platform hw (at least on some
3392 * outputs) where an enabled pipe still completes any pageflip right
3393 * away (as if the pipe is off) instead of waiting for vblank. As soon
3394 * as the first vblank happend, everything works as expected. Hence just
3395 * wait for one vblank before returning to avoid strange things
3396 * happening.
3397 */
3398 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3399}
3400
4f771f10
PZ		 3401static void haswell_crtc_enable(struct drm_crtc *crtc)
3402{
3403 struct drm_device *dev = crtc->dev;
3404 struct drm_i915_private *dev_priv = dev->dev_private;
3405 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3406 struct intel_encoder *encoder;
3407 int pipe = intel_crtc->pipe;
3408 int plane = intel_crtc->plane;
4f771f10
PZ		 3409
3410 WARN_ON(!crtc->enabled);
3411
3412 if (intel_crtc->active)
3413 return;
3414
3415 intel_crtc->active = true;
3416 intel_update_watermarks(dev);
3417
5bfe2ac0 3418 if (intel_crtc->config.has_pch_encoder)
04945641 3419 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3420
3421 for_each_encoder_on_crtc(dev, crtc, encoder)
3422 if (encoder->pre_enable)
3423 encoder->pre_enable(encoder);
3424
1f544388 3425 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3426
1f544388 3427 /* Enable panel fitting for eDP */
547dc041
JN		 3428 if (dev_priv->pch_pf_size &&
3429 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4f771f10
PZ		 3430 /* Force use of hard-coded filter coefficients
3431 * as some pre-programmed values are broken,
3432 * e.g. x201.
3433 */
54075a7d
PZ		 3434 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3435 PF_PIPE_SEL_IVB(pipe));
4f771f10
PZ		 3436 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3437 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3438 }
3439
3440 /*
3441 * On ILK+ LUT must be loaded before the pipe is running but with
3442 * clocks enabled
3443 */
3444 intel_crtc_load_lut(crtc);
3445
1f544388 3446 intel_ddi_set_pipe_settings(crtc);
8228c251 3447 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3448
5bfe2ac0
DV		 3449 intel_enable_pipe(dev_priv, pipe,
3450 intel_crtc->config.has_pch_encoder);
4f771f10
PZ		 3451 intel_enable_plane(dev_priv, plane, pipe);
3452
5bfe2ac0 3453 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3454 lpt_pch_enable(crtc);
4f771f10
PZ		 3455
3456 mutex_lock(&dev->struct_mutex);
3457 intel_update_fbc(dev);
3458 mutex_unlock(&dev->struct_mutex);
3459
3460 intel_crtc_update_cursor(crtc, true);
3461
3462 for_each_encoder_on_crtc(dev, crtc, encoder)
3463 encoder->enable(encoder);
3464
4f771f10
PZ		 3465 /*
3466 * There seems to be a race in PCH platform hw (at least on some
3467 * outputs) where an enabled pipe still completes any pageflip right
3468 * away (as if the pipe is off) instead of waiting for vblank. As soon
3469 * as the first vblank happend, everything works as expected. Hence just
3470 * wait for one vblank before returning to avoid strange things
3471 * happening.
3472 */
3473 intel_wait_for_vblank(dev, intel_crtc->pipe);
3474}
3475
6be4a607
JB		 3476static void ironlake_crtc_disable(struct drm_crtc *crtc)
3477{
3478 struct drm_device *dev = crtc->dev;
3479 struct drm_i915_private *dev_priv = dev->dev_private;
3480 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3481 struct intel_encoder *encoder;
6be4a607
JB		 3482 int pipe = intel_crtc->pipe;
3483 int plane = intel_crtc->plane;
5eddb70b 3484 u32 reg, temp;
b52eb4dc 3485
ef9c3aee 3486
f7abfe8b
CW		 3487 if (!intel_crtc->active)
3488 return;
3489
ea9d758d
DV		 3490 for_each_encoder_on_crtc(dev, crtc, encoder)
3491 encoder->disable(encoder);
3492
e6c3a2a6 3493 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3494 drm_vblank_off(dev, pipe);
6b383a7f 3495 intel_crtc_update_cursor(crtc, false);
5eddb70b 3496
b24e7179 3497 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3498
973d04f9
CW		 3499 if (dev_priv->cfb_plane == plane)
3500 intel_disable_fbc(dev);
2c07245f 3501
b24e7179 3502 intel_disable_pipe(dev_priv, pipe);
32f9d658 3503
6be4a607 3504 /* Disable PF */
9db4a9c7
JB		 3505 I915_WRITE(PF_CTL(pipe), 0);
3506 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3507
bf49ec8c
DV		 3508 for_each_encoder_on_crtc(dev, crtc, encoder)
3509 if (encoder->post_disable)
3510 encoder->post_disable(encoder);
2c07245f 3511
0fc932b8 3512 ironlake_fdi_disable(crtc);
249c0e64 3513
b8a4f404 3514 ironlake_disable_pch_transcoder(dev_priv, pipe);
913d8d11 3515
6be4a607
JB		 3516 if (HAS_PCH_CPT(dev)) {
3517 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3518 reg = TRANS_DP_CTL(pipe);
3519 temp = I915_READ(reg);
3520 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3521 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3522 I915_WRITE(reg, temp);
6be4a607
JB		 3523
3524 /* disable DPLL_SEL */
3525 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3526 switch (pipe) {
3527 case 0:
d64311ab 3528 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3529 break;
3530 case 1:
6be4a607 3531 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3532 break;
3533 case 2:
4b645f14 3534 /* C shares PLL A or B */
d64311ab 3535 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3536 break;
3537 default:
3538 BUG(); /* wtf */
3539 }
6be4a607 3540 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3541 }
e3421a18 3542
6be4a607 3543 /* disable PCH DPLL */
ee7b9f93 3544 intel_disable_pch_pll(intel_crtc);
8db9d77b 3545
88cefb6c 3546 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3547
f7abfe8b 3548 intel_crtc->active = false;
6b383a7f 3549 intel_update_watermarks(dev);
d1ebd816
BW		 3550
3551 mutex_lock(&dev->struct_mutex);
6b383a7f 3552 intel_update_fbc(dev);
d1ebd816 3553 mutex_unlock(&dev->struct_mutex);
6be4a607 3554}
1b3c7a47 3555
4f771f10 3556static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3557{
4f771f10
PZ		 3558 struct drm_device *dev = crtc->dev;
3559 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3560 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3561 struct intel_encoder *encoder;
3562 int pipe = intel_crtc->pipe;
3563 int plane = intel_crtc->plane;
ad80a810 3564 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
83616634 3565 bool is_pch_port;
ee7b9f93 3566
4f771f10
PZ		 3567 if (!intel_crtc->active)
3568 return;
3569
83616634
PZ		 3570 is_pch_port = haswell_crtc_driving_pch(crtc);
3571
4f771f10
PZ		 3572 for_each_encoder_on_crtc(dev, crtc, encoder)
3573 encoder->disable(encoder);
3574
3575 intel_crtc_wait_for_pending_flips(crtc);
3576 drm_vblank_off(dev, pipe);
3577 intel_crtc_update_cursor(crtc, false);
3578
3579 intel_disable_plane(dev_priv, plane, pipe);
3580
3581 if (dev_priv->cfb_plane == plane)
3582 intel_disable_fbc(dev);
3583
3584 intel_disable_pipe(dev_priv, pipe);
3585
ad80a810 3586 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10
PZ		 3587
3588 /* Disable PF */
3589 I915_WRITE(PF_CTL(pipe), 0);
3590 I915_WRITE(PF_WIN_SZ(pipe), 0);
3591
1f544388 3592 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3593
3594 for_each_encoder_on_crtc(dev, crtc, encoder)
3595 if (encoder->post_disable)
3596 encoder->post_disable(encoder);
3597
83616634 3598 if (is_pch_port) {
ab4d966c 3599 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 3600 intel_ddi_fdi_disable(crtc);
83616634 3601 }
4f771f10
PZ		 3602
3603 intel_crtc->active = false;
3604 intel_update_watermarks(dev);
3605
3606 mutex_lock(&dev->struct_mutex);
3607 intel_update_fbc(dev);
3608 mutex_unlock(&dev->struct_mutex);
3609}
3610
ee7b9f93
JB		 3611static void ironlake_crtc_off(struct drm_crtc *crtc)
3612{
3613 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3614 intel_put_pch_pll(intel_crtc);
3615}
3616
6441ab5f
PZ		 3617static void haswell_crtc_off(struct drm_crtc *crtc)
3618{
a5c961d1
PZ		 3619 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3620
3621 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3622 * start using it. */
1a240d4d 3623 intel_crtc->cpu_transcoder = (enum transcoder) intel_crtc->pipe;
a5c961d1 3624
6441ab5f
PZ		 3625 intel_ddi_put_crtc_pll(crtc);
3626}
3627
02e792fb
DV		 3628static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3629{
02e792fb 3630 if (!enable && intel_crtc->overlay) {
23f09ce3 3631 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3632 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3633
23f09ce3 3634 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3635 dev_priv->mm.interruptible = false;
3636 (void) intel_overlay_switch_off(intel_crtc->overlay);
3637 dev_priv->mm.interruptible = true;
23f09ce3 3638 mutex_unlock(&dev->struct_mutex);
02e792fb 3639 }
02e792fb 3640
5dcdbcb0
CW		 3641 /* Let userspace switch the overlay on again. In most cases userspace
3642 * has to recompute where to put it anyway.
3643 */
02e792fb
DV		 3644}
3645
61bc95c1
EE		 3646/**
3647 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3648 * cursor plane briefly if not already running after enabling the display
3649 * plane.
3650 * This workaround avoids occasional blank screens when self refresh is
3651 * enabled.
3652 */
3653static void
3654g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3655{
3656 u32 cntl = I915_READ(CURCNTR(pipe));
3657
3658 if ((cntl & CURSOR_MODE) == 0) {
3659 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3660
3661 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3662 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3663 intel_wait_for_vblank(dev_priv->dev, pipe);
3664 I915_WRITE(CURCNTR(pipe), cntl);
3665 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3666 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3667 }
3668}
3669
0b8765c6 3670static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3671{
3672 struct drm_device *dev = crtc->dev;
79e53945
JB		 3673 struct drm_i915_private *dev_priv = dev->dev_private;
3674 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3675 struct intel_encoder *encoder;
79e53945 3676 int pipe = intel_crtc->pipe;
80824003 3677 int plane = intel_crtc->plane;
79e53945 3678
08a48469
DV		 3679 WARN_ON(!crtc->enabled);
3680
f7abfe8b
CW		 3681 if (intel_crtc->active)
3682 return;
3683
3684 intel_crtc->active = true;
6b383a7f
CW		 3685 intel_update_watermarks(dev);
3686
63d7bbe9 3687 intel_enable_pll(dev_priv, pipe);
9d6d9f19
MK		 3688
3689 for_each_encoder_on_crtc(dev, crtc, encoder)
3690 if (encoder->pre_enable)
3691 encoder->pre_enable(encoder);
3692
040484af 3693 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3694 intel_enable_plane(dev_priv, plane, pipe);
61bc95c1
EE		 3695 if (IS_G4X(dev))
3696 g4x_fixup_plane(dev_priv, pipe);
79e53945 3697
0b8765c6 3698 intel_crtc_load_lut(crtc);
bed4a673 3699 intel_update_fbc(dev);
79e53945 3700
0b8765c6
JB		 3701 /* Give the overlay scaler a chance to enable if it's on this pipe */
3702 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3703 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3704
fa5c73b1
DV		 3705 for_each_encoder_on_crtc(dev, crtc, encoder)
3706 encoder->enable(encoder);
0b8765c6 3707}
79e53945 3708
0b8765c6
JB		 3709static void i9xx_crtc_disable(struct drm_crtc *crtc)
3710{
3711 struct drm_device *dev = crtc->dev;
3712 struct drm_i915_private *dev_priv = dev->dev_private;
3713 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3714 struct intel_encoder *encoder;
0b8765c6
JB		 3715 int pipe = intel_crtc->pipe;
3716 int plane = intel_crtc->plane;
24a1f16d 3717 u32 pctl;
b690e96c 3718
ef9c3aee 3719
f7abfe8b
CW		 3720 if (!intel_crtc->active)
3721 return;
3722
ea9d758d
DV		 3723 for_each_encoder_on_crtc(dev, crtc, encoder)
3724 encoder->disable(encoder);
3725
0b8765c6 3726 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3727 intel_crtc_wait_for_pending_flips(crtc);
3728 drm_vblank_off(dev, pipe);
0b8765c6 3729 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3730 intel_crtc_update_cursor(crtc, false);
0b8765c6 3731
973d04f9
CW		 3732 if (dev_priv->cfb_plane == plane)
3733 intel_disable_fbc(dev);
79e53945 3734
b24e7179 3735 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3736 intel_disable_pipe(dev_priv, pipe);
24a1f16d
MK		 3737
3738 /* Disable pannel fitter if it is on this pipe. */
3739 pctl = I915_READ(PFIT_CONTROL);
3740 if ((pctl & PFIT_ENABLE) &&
3741 ((pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT) == pipe)
3742 I915_WRITE(PFIT_CONTROL, 0);
3743
63d7bbe9 3744 intel_disable_pll(dev_priv, pipe);
0b8765c6 3745
f7abfe8b 3746 intel_crtc->active = false;
6b383a7f
CW		 3747 intel_update_fbc(dev);
3748 intel_update_watermarks(dev);
0b8765c6
JB		 3749}
3750
ee7b9f93
JB		 3751static void i9xx_crtc_off(struct drm_crtc *crtc)
3752{
3753}
3754
976f8a20
DV		 3755static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3756 bool enabled)
2c07245f
ZW		 3757{
3758 struct drm_device *dev = crtc->dev;
3759 struct drm_i915_master_private *master_priv;
3760 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3761 int pipe = intel_crtc->pipe;
79e53945
JB		 3762
3763 if (!dev->primary->master)
3764 return;
3765
3766 master_priv = dev->primary->master->driver_priv;
3767 if (!master_priv->sarea_priv)
3768 return;
3769
79e53945
JB		 3770 switch (pipe) {
3771 case 0:
3772 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3773 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3774 break;
3775 case 1:
3776 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3777 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3778 break;
3779 default:
9db4a9c7 3780 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3781 break;
3782 }
79e53945
JB		 3783}
3784
976f8a20
DV		 3785/**
3786 * Sets the power management mode of the pipe and plane.
3787 */
3788void intel_crtc_update_dpms(struct drm_crtc *crtc)
3789{
3790 struct drm_device *dev = crtc->dev;
3791 struct drm_i915_private *dev_priv = dev->dev_private;
3792 struct intel_encoder *intel_encoder;
3793 bool enable = false;
3794
3795 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3796 enable |= intel_encoder->connectors_active;
3797
3798 if (enable)
3799 dev_priv->display.crtc_enable(crtc);
3800 else
3801 dev_priv->display.crtc_disable(crtc);
3802
3803 intel_crtc_update_sarea(crtc, enable);
3804}
3805
cdd59983
CW		 3806static void intel_crtc_disable(struct drm_crtc *crtc)
3807{
cdd59983 3808 struct drm_device *dev = crtc->dev;
976f8a20 3809 struct drm_connector *connector;
ee7b9f93 3810 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3811 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3812
976f8a20
DV		 3813 /* crtc should still be enabled when we disable it. */
3814 WARN_ON(!crtc->enabled);
3815
7b9f35a6 3816 intel_crtc->eld_vld = false;
976f8a20
DV		 3817 dev_priv->display.crtc_disable(crtc);
3818 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3819 dev_priv->display.off(crtc);
3820
931872fc
CW		 3821 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3822 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3823
3824 if (crtc->fb) {
3825 mutex_lock(&dev->struct_mutex);
1690e1eb 3826 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3827 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3828 crtc->fb = NULL;
3829 }
3830
3831 /* Update computed state. */
3832 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3833 if (!connector->encoder || !connector->encoder->crtc)
3834 continue;
3835
3836 if (connector->encoder->crtc != crtc)
3837 continue;
3838
3839 connector->dpms = DRM_MODE_DPMS_OFF;
3840 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3841 }
3842}
3843
a261b246 3844void intel_modeset_disable(struct drm_device *dev)
79e53945 3845{
a261b246
DV		 3846 struct drm_crtc *crtc;
3847
3848 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3849 if (crtc->enabled)
3850 intel_crtc_disable(crtc);
3851 }
79e53945
JB		 3852}
3853
ea5b213a 3854void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3855{
4ef69c7a 3856 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3857
ea5b213a
CW		 3858 drm_encoder_cleanup(encoder);
3859 kfree(intel_encoder);
7e7d76c3
JB		 3860}
3861
5ab432ef
DV		 3862/* Simple dpms helper for encodres with just one connector, no cloning and only
3863 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3864 * state of the entire output pipe. */
3865void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3866{
5ab432ef
DV		 3867 if (mode == DRM_MODE_DPMS_ON) {
3868 encoder->connectors_active = true;
3869
b2cabb0e 3870 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3871 } else {
3872 encoder->connectors_active = false;
3873
b2cabb0e 3874 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3875 }
79e53945
JB		 3876}
3877
0a91ca29
DV		 3878/* Cross check the actual hw state with our own modeset state tracking (and it's
3879 * internal consistency). */
b980514c 3880static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3881{
0a91ca29
DV		 3882 if (connector->get_hw_state(connector)) {
3883 struct intel_encoder *encoder = connector->encoder;
3884 struct drm_crtc *crtc;
3885 bool encoder_enabled;
3886 enum pipe pipe;
3887
3888 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3889 connector->base.base.id,
3890 drm_get_connector_name(&connector->base));
3891
3892 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3893 "wrong connector dpms state\n");
3894 WARN(connector->base.encoder != &encoder->base,
3895 "active connector not linked to encoder\n");
3896 WARN(!encoder->connectors_active,
3897 "encoder->connectors_active not set\n");
3898
3899 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3900 WARN(!encoder_enabled, "encoder not enabled\n");
3901 if (WARN_ON(!encoder->base.crtc))
3902 return;
3903
3904 crtc = encoder->base.crtc;
3905
3906 WARN(!crtc->enabled, "crtc not enabled\n");
3907 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3908 WARN(pipe != to_intel_crtc(crtc)->pipe,
3909 "encoder active on the wrong pipe\n");
3910 }
79e53945
JB		 3911}
3912
5ab432ef
DV		 3913/* Even simpler default implementation, if there's really no special case to
3914 * consider. */
3915void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3916{
5ab432ef 3917 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3918
5ab432ef
DV		 3919 /* All the simple cases only support two dpms states. */
3920 if (mode != DRM_MODE_DPMS_ON)
3921 mode = DRM_MODE_DPMS_OFF;
d4270e57 3922
5ab432ef
DV		 3923 if (mode == connector->dpms)
3924 return;
3925
3926 connector->dpms = mode;
3927
3928 /* Only need to change hw state when actually enabled */
3929 if (encoder->base.crtc)
3930 intel_encoder_dpms(encoder, mode);
3931 else
8af6cf88 3932 WARN_ON(encoder->connectors_active != false);
0a91ca29 3933
b980514c 3934 intel_modeset_check_state(connector->dev);
79e53945
JB		 3935}
3936
f0947c37
DV		 3937/* Simple connector->get_hw_state implementation for encoders that support only
3938 * one connector and no cloning and hence the encoder state determines the state
3939 * of the connector. */
3940bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3941{
24929352 3942 enum pipe pipe = 0;
f0947c37 3943 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3944
f0947c37 3945 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3946}
3947
b8cecdf5
DV		 3948static bool intel_crtc_compute_config(struct drm_crtc *crtc,
3949 struct intel_crtc_config *pipe_config)
79e53945 3950{
2c07245f 3951 struct drm_device *dev = crtc->dev;
b8cecdf5 3952 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 3953
bad720ff 3954 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3955 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 3956 if (pipe_config->requested_mode.clock * 3
3957 > IRONLAKE_FDI_FREQ * 4)
2377b741 3958 return false;
2c07245f 3959 }
89749350 3960
f9bef081
DV		 3961 /* All interlaced capable intel hw wants timings in frames. Note though
3962 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3963 * timings, so we need to be careful not to clobber these.*/
7ae89233 3964 if (!pipe_config->timings_set)
f9bef081 3965 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3966
44f46b42
CW		 3967 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3968 * with a hsync front porch of 0.
3969 */
3970 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3971 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3972 return false;
3973
79e53945
JB		 3974 return true;
3975}
3976
25eb05fc
JB		 3977static int valleyview_get_display_clock_speed(struct drm_device *dev)
3978{
3979 return 400000; /* FIXME */
3980}
3981
e70236a8
JB		 3982static int i945_get_display_clock_speed(struct drm_device *dev)
3983{
3984 return 400000;
3985}
79e53945 3986
e70236a8 3987static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3988{
e70236a8
JB		 3989 return 333000;
3990}
79e53945 3991
e70236a8
JB		 3992static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3993{
3994 return 200000;
3995}
79e53945 3996
e70236a8
JB		 3997static int i915gm_get_display_clock_speed(struct drm_device *dev)
3998{
3999 u16 gcfgc = 0;
79e53945 4000
e70236a8
JB		 4001 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4002
4003 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4004 return 133000;
4005 else {
4006 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4007 case GC_DISPLAY_CLOCK_333_MHZ:
4008 return 333000;
4009 default:
4010 case GC_DISPLAY_CLOCK_190_200_MHZ:
4011 return 190000;
79e53945 4012 }
e70236a8
JB		 4013 }
4014}
4015
4016static int i865_get_display_clock_speed(struct drm_device *dev)
4017{
4018 return 266000;
4019}
4020
4021static int i855_get_display_clock_speed(struct drm_device *dev)
4022{
4023 u16 hpllcc = 0;
4024 /* Assume that the hardware is in the high speed state. This
4025 * should be the default.
4026 */
4027 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4028 case GC_CLOCK_133_200:
4029 case GC_CLOCK_100_200:
4030 return 200000;
4031 case GC_CLOCK_166_250:
4032 return 250000;
4033 case GC_CLOCK_100_133:
79e53945 4034 return 133000;
e70236a8 4035 }
79e53945 4036
e70236a8
JB		 4037 /* Shouldn't happen */
4038 return 0;
4039}
79e53945 4040
e70236a8
JB		 4041static int i830_get_display_clock_speed(struct drm_device *dev)
4042{
4043 return 133000;
79e53945
JB		 4044}
4045
2c07245f 4046static void
e69d0bc1 4047intel_reduce_ratio(uint32_t *num, uint32_t *den)
2c07245f
ZW		 4048{
4049 while (*num > 0xffffff || *den > 0xffffff) {
4050 *num >>= 1;
4051 *den >>= 1;
4052 }
4053}
4054
e69d0bc1
DV		 4055void
4056intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4057 int pixel_clock, int link_clock,
4058 struct intel_link_m_n *m_n)
2c07245f 4059{
e69d0bc1 4060 m_n->tu = 64;
22ed1113
CW		 4061 m_n->gmch_m = bits_per_pixel * pixel_clock;
4062 m_n->gmch_n = link_clock * nlanes * 8;
e69d0bc1 4063 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
22ed1113
CW		 4064 m_n->link_m = pixel_clock;
4065 m_n->link_n = link_clock;
e69d0bc1 4066 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4067}
4068
a7615030
CW		 4069static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4070{
72bbe58c
KP		 4071 if (i915_panel_use_ssc >= 0)
4072 return i915_panel_use_ssc != 0;
4073 return dev_priv->lvds_use_ssc
435793df 4074 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4075}
4076
a0c4da24
JB		 4077static int vlv_get_refclk(struct drm_crtc *crtc)
4078{
4079 struct drm_device *dev = crtc->dev;
4080 struct drm_i915_private *dev_priv = dev->dev_private;
4081 int refclk = 27000; /* for DP & HDMI */
4082
4083 return 100000; /* only one validated so far */
4084
4085 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4086 refclk = 96000;
4087 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4088 if (intel_panel_use_ssc(dev_priv))
4089 refclk = 100000;
4090 else
4091 refclk = 96000;
4092 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4093 refclk = 100000;
4094 }
4095
4096 return refclk;
4097}
4098
c65d77d8
JB		 4099static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4100{
4101 struct drm_device *dev = crtc->dev;
4102 struct drm_i915_private *dev_priv = dev->dev_private;
4103 int refclk;
4104
a0c4da24
JB		 4105 if (IS_VALLEYVIEW(dev)) {
4106 refclk = vlv_get_refclk(crtc);
4107 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 4108 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4109 refclk = dev_priv->lvds_ssc_freq * 1000;
4110 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4111 refclk / 1000);
4112 } else if (!IS_GEN2(dev)) {
4113 refclk = 96000;
4114 } else {
4115 refclk = 48000;
4116 }
4117
4118 return refclk;
4119}
4120
4121static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4122 intel_clock_t *clock)
4123{
4124 /* SDVO TV has fixed PLL values depend on its clock range,
4125 this mirrors vbios setting. */
4126 if (adjusted_mode->clock >= 100000
4127 && adjusted_mode->clock < 140500) {
4128 clock->p1 = 2;
4129 clock->p2 = 10;
4130 clock->n = 3;
4131 clock->m1 = 16;
4132 clock->m2 = 8;
4133 } else if (adjusted_mode->clock >= 140500
4134 && adjusted_mode->clock <= 200000) {
4135 clock->p1 = 1;
4136 clock->p2 = 10;
4137 clock->n = 6;
4138 clock->m1 = 12;
4139 clock->m2 = 8;
4140 }
4141}
4142
a7516a05
JB		 4143static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4144 intel_clock_t *clock,
4145 intel_clock_t *reduced_clock)
4146{
4147 struct drm_device *dev = crtc->dev;
4148 struct drm_i915_private *dev_priv = dev->dev_private;
4149 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4150 int pipe = intel_crtc->pipe;
4151 u32 fp, fp2 = 0;
4152
4153 if (IS_PINEVIEW(dev)) {
4154 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4155 if (reduced_clock)
4156 fp2 = (1 << reduced_clock->n) << 16 |
4157 reduced_clock->m1 << 8 | reduced_clock->m2;
4158 } else {
4159 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4160 if (reduced_clock)
4161 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4162 reduced_clock->m2;
4163 }
4164
4165 I915_WRITE(FP0(pipe), fp);
4166
4167 intel_crtc->lowfreq_avail = false;
4168 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4169 reduced_clock && i915_powersave) {
4170 I915_WRITE(FP1(pipe), fp2);
4171 intel_crtc->lowfreq_avail = true;
4172 } else {
4173 I915_WRITE(FP1(pipe), fp);
4174 }
4175}
4176
a0c4da24 4177static void vlv_update_pll(struct drm_crtc *crtc,
a0c4da24 4178 intel_clock_t *clock, intel_clock_t *reduced_clock,
2a8f64ca 4179 int num_connectors)
a0c4da24
JB		 4180{
4181 struct drm_device *dev = crtc->dev;
4182 struct drm_i915_private *dev_priv = dev->dev_private;
4183 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6cc5f341
DV		 4184 struct drm_display_mode *adjusted_mode =
4185 &intel_crtc->config.adjusted_mode;
4186 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
a0c4da24
JB		 4187 int pipe = intel_crtc->pipe;
4188 u32 dpll, mdiv, pdiv;
4189 u32 bestn, bestm1, bestm2, bestp1, bestp2;
2a8f64ca
VP		 4190 bool is_sdvo;
4191 u32 temp;
a0c4da24 4192
09153000
DV		 4193 mutex_lock(&dev_priv->dpio_lock);
4194
2a8f64ca
VP		 4195 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4196 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
a0c4da24 4197
2a8f64ca
VP		 4198 dpll = DPLL_VGA_MODE_DIS;
4199 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4200 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4201 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4202
4203 I915_WRITE(DPLL(pipe), dpll);
4204 POSTING_READ(DPLL(pipe));
a0c4da24
JB		 4205
4206 bestn = clock->n;
4207 bestm1 = clock->m1;
4208 bestm2 = clock->m2;
4209 bestp1 = clock->p1;
4210 bestp2 = clock->p2;
4211
2a8f64ca
VP		 4212 /*
4213 * In Valleyview PLL and program lane counter registers are exposed
4214 * through DPIO interface
4215 */
a0c4da24
JB		 4216 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4217 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4218 mdiv |= ((bestn << DPIO_N_SHIFT));
4219 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4220 mdiv |= (1 << DPIO_K_SHIFT);
4221 mdiv |= DPIO_ENABLE_CALIBRATION;
4222 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4223
4224 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4225
2a8f64ca 4226 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
a0c4da24 4227 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
2a8f64ca
VP		 4228 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4229 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
a0c4da24
JB		 4230 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4231
2a8f64ca 4232 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
a0c4da24
JB		 4233
4234 dpll |= DPLL_VCO_ENABLE;
4235 I915_WRITE(DPLL(pipe), dpll);
4236 POSTING_READ(DPLL(pipe));
4237 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4238 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4239
2a8f64ca
VP		 4240 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4241
4242 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4243 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4244
4245 I915_WRITE(DPLL(pipe), dpll);
4246
4247 /* Wait for the clocks to stabilize. */
4248 POSTING_READ(DPLL(pipe));
4249 udelay(150);
a0c4da24 4250
2a8f64ca
VP		 4251 temp = 0;
4252 if (is_sdvo) {
6cc5f341
DV		 4253 temp = 0;
4254 if (intel_crtc->config.pixel_multiplier > 1) {
4255 temp = (intel_crtc->config.pixel_multiplier - 1)
4256 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4257 }
a0c4da24 4258 }
2a8f64ca
VP		 4259 I915_WRITE(DPLL_MD(pipe), temp);
4260 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4261
2a8f64ca
VP		 4262 /* Now program lane control registers */
4263 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4264 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4265 {
4266 temp = 0x1000C4;
4267 if(pipe == 1)
4268 temp |= (1 << 21);
4269 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4270 }
4271 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4272 {
4273 temp = 0x1000C4;
4274 if(pipe == 1)
4275 temp |= (1 << 21);
4276 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4277 }
09153000
DV		 4278
4279 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4280}
4281
eb1cbe48 4282static void i9xx_update_pll(struct drm_crtc *crtc,
eb1cbe48
DV		 4283 intel_clock_t *clock, intel_clock_t *reduced_clock,
4284 int num_connectors)
4285{
4286 struct drm_device *dev = crtc->dev;
4287 struct drm_i915_private *dev_priv = dev->dev_private;
4288 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6cc5f341
DV		 4289 struct drm_display_mode *adjusted_mode =
4290 &intel_crtc->config.adjusted_mode;
4291 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
dafd226c 4292 struct intel_encoder *encoder;
eb1cbe48
DV		 4293 int pipe = intel_crtc->pipe;
4294 u32 dpll;
4295 bool is_sdvo;
4296
2a8f64ca
VP		 4297 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4298
eb1cbe48
DV		 4299 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4300 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4301
4302 dpll = DPLL_VGA_MODE_DIS;
4303
4304 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4305 dpll |= DPLLB_MODE_LVDS;
4306 else
4307 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4308
eb1cbe48 4309 if (is_sdvo) {
6cc5f341
DV		 4310 if ((intel_crtc->config.pixel_multiplier > 1) &&
4311 (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
4312 dpll |= (intel_crtc->config.pixel_multiplier - 1)
4313 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48
DV		 4314 }
4315 dpll |= DPLL_DVO_HIGH_SPEED;
4316 }
4317 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4318 dpll |= DPLL_DVO_HIGH_SPEED;
4319
4320 /* compute bitmask from p1 value */
4321 if (IS_PINEVIEW(dev))
4322 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4323 else {
4324 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4325 if (IS_G4X(dev) && reduced_clock)
4326 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4327 }
4328 switch (clock->p2) {
4329 case 5:
4330 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4331 break;
4332 case 7:
4333 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4334 break;
4335 case 10:
4336 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4337 break;
4338 case 14:
4339 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4340 break;
4341 }
4342 if (INTEL_INFO(dev)->gen >= 4)
4343 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4344
4345 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4346 dpll |= PLL_REF_INPUT_TVCLKINBC;
4347 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4348 /* XXX: just matching BIOS for now */
4349 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4350 dpll |= 3;
4351 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4352 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4353 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4354 else
4355 dpll |= PLL_REF_INPUT_DREFCLK;
4356
4357 dpll |= DPLL_VCO_ENABLE;
4358 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4359 POSTING_READ(DPLL(pipe));
4360 udelay(150);
4361
dafd226c
DV		 4362 for_each_encoder_on_crtc(dev, crtc, encoder)
4363 if (encoder->pre_pll_enable)
4364 encoder->pre_pll_enable(encoder);
eb1cbe48
DV		 4365
4366 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4367 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4368
4369 I915_WRITE(DPLL(pipe), dpll);
4370
4371 /* Wait for the clocks to stabilize. */
4372 POSTING_READ(DPLL(pipe));
4373 udelay(150);
4374
4375 if (INTEL_INFO(dev)->gen >= 4) {
4376 u32 temp = 0;
4377 if (is_sdvo) {
6cc5f341
DV		 4378 temp = 0;
4379 if (intel_crtc->config.pixel_multiplier > 1) {
4380 temp = (intel_crtc->config.pixel_multiplier - 1)
4381 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4382 }
eb1cbe48
DV		 4383 }
4384 I915_WRITE(DPLL_MD(pipe), temp);
4385 } else {
4386 /* The pixel multiplier can only be updated once the
4387 * DPLL is enabled and the clocks are stable.
4388 *
4389 * So write it again.
4390 */
4391 I915_WRITE(DPLL(pipe), dpll);
4392 }
4393}
4394
4395static void i8xx_update_pll(struct drm_crtc *crtc,
4396 struct drm_display_mode *adjusted_mode,
2a8f64ca 4397 intel_clock_t *clock, intel_clock_t *reduced_clock,
eb1cbe48
DV		 4398 int num_connectors)
4399{
4400 struct drm_device *dev = crtc->dev;
4401 struct drm_i915_private *dev_priv = dev->dev_private;
4402 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dafd226c 4403 struct intel_encoder *encoder;
eb1cbe48
DV		 4404 int pipe = intel_crtc->pipe;
4405 u32 dpll;
4406
2a8f64ca
VP		 4407 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4408
eb1cbe48
DV		 4409 dpll = DPLL_VGA_MODE_DIS;
4410
4411 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4412 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4413 } else {
4414 if (clock->p1 == 2)
4415 dpll |= PLL_P1_DIVIDE_BY_TWO;
4416 else
4417 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4418 if (clock->p2 == 4)
4419 dpll |= PLL_P2_DIVIDE_BY_4;
4420 }
4421
83f377ab 4422 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4423 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4424 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4425 else
4426 dpll |= PLL_REF_INPUT_DREFCLK;
4427
4428 dpll |= DPLL_VCO_ENABLE;
4429 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4430 POSTING_READ(DPLL(pipe));
4431 udelay(150);
4432
dafd226c
DV		 4433 for_each_encoder_on_crtc(dev, crtc, encoder)
4434 if (encoder->pre_pll_enable)
4435 encoder->pre_pll_enable(encoder);
eb1cbe48 4436
5b5896e4
DV		 4437 I915_WRITE(DPLL(pipe), dpll);
4438
4439 /* Wait for the clocks to stabilize. */
4440 POSTING_READ(DPLL(pipe));
4441 udelay(150);
4442
eb1cbe48
DV		 4443 /* The pixel multiplier can only be updated once the
4444 * DPLL is enabled and the clocks are stable.
4445 *
4446 * So write it again.
4447 */
4448 I915_WRITE(DPLL(pipe), dpll);
4449}
4450
b0e77b9c
PZ		 4451static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4452 struct drm_display_mode *mode,
4453 struct drm_display_mode *adjusted_mode)
4454{
4455 struct drm_device *dev = intel_crtc->base.dev;
4456 struct drm_i915_private *dev_priv = dev->dev_private;
4457 enum pipe pipe = intel_crtc->pipe;
fe2b8f9d 4458 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
b0e77b9c
PZ		 4459 uint32_t vsyncshift;
4460
4461 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4462 /* the chip adds 2 halflines automatically */
4463 adjusted_mode->crtc_vtotal -= 1;
4464 adjusted_mode->crtc_vblank_end -= 1;
4465 vsyncshift = adjusted_mode->crtc_hsync_start
4466 - adjusted_mode->crtc_htotal / 2;
4467 } else {
4468 vsyncshift = 0;
4469 }
4470
4471 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4472 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4473
fe2b8f9d 4474 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4475 (adjusted_mode->crtc_hdisplay - 1) |
4476 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4477 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4478 (adjusted_mode->crtc_hblank_start - 1) |
4479 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4480 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4481 (adjusted_mode->crtc_hsync_start - 1) |
4482 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4483
fe2b8f9d 4484 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4485 (adjusted_mode->crtc_vdisplay - 1) |
4486 ((adjusted_mode->crtc_vtotal - 1) << 16));
fe2b8f9d 4487 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c
PZ		 4488 (adjusted_mode->crtc_vblank_start - 1) |
4489 ((adjusted_mode->crtc_vblank_end - 1) << 16));
fe2b8f9d 4490 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4491 (adjusted_mode->crtc_vsync_start - 1) |
4492 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4493
b5e508d4
PZ		 4494 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4495 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4496 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4497 * bits. */
4498 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4499 (pipe == PIPE_B || pipe == PIPE_C))
4500 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4501
b0e77b9c
PZ		 4502 /* pipesrc controls the size that is scaled from, which should
4503 * always be the user's requested size.
4504 */
4505 I915_WRITE(PIPESRC(pipe),
4506 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4507}
4508
f564048e 4509static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4510 int x, int y,
94352cf9 4511 struct drm_framebuffer *fb)
79e53945
JB		 4512{
4513 struct drm_device *dev = crtc->dev;
4514 struct drm_i915_private *dev_priv = dev->dev_private;
4515 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 4516 struct drm_display_mode *adjusted_mode =
4517 &intel_crtc->config.adjusted_mode;
4518 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4519 int pipe = intel_crtc->pipe;
80824003 4520 int plane = intel_crtc->plane;
c751ce4f 4521 int refclk, num_connectors = 0;
652c393a 4522 intel_clock_t clock, reduced_clock;
b0e77b9c 4523 u32 dspcntr, pipeconf;
eb1cbe48
DV		 4524 bool ok, has_reduced_clock = false, is_sdvo = false;
4525 bool is_lvds = false, is_tv = false, is_dp = false;
5eddb70b 4526 struct intel_encoder *encoder;
d4906093 4527 const intel_limit_t *limit;
5c3b82e2 4528 int ret;
79e53945 4529
6c2b7c12 4530 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4531 switch (encoder->type) {
79e53945
JB		 4532 case INTEL_OUTPUT_LVDS:
4533 is_lvds = true;
4534 break;
4535 case INTEL_OUTPUT_SDVO:
7d57382e 4536 case INTEL_OUTPUT_HDMI:
79e53945 4537 is_sdvo = true;
5eddb70b 4538 if (encoder->needs_tv_clock)
e2f0ba97 4539 is_tv = true;
79e53945 4540 break;
79e53945
JB		 4541 case INTEL_OUTPUT_TVOUT:
4542 is_tv = true;
4543 break;
a4fc5ed6
KP		 4544 case INTEL_OUTPUT_DISPLAYPORT:
4545 is_dp = true;
4546 break;
79e53945 4547 }
43565a06 4548
c751ce4f 4549 num_connectors++;
79e53945
JB		 4550 }
4551
c65d77d8 4552 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4553
d4906093
ML		 4554 /*
4555 * Returns a set of divisors for the desired target clock with the given
4556 * refclk, or FALSE. The returned values represent the clock equation:
4557 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4558 */
1b894b59 4559 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4560 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4561 &clock);
79e53945
JB		 4562 if (!ok) {
4563 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4564 return -EINVAL;
79e53945
JB		 4565 }
4566
cda4b7d3 4567 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4568 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4569
ddc9003c 4570 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4571 /*
4572 * Ensure we match the reduced clock's P to the target clock.
4573 * If the clocks don't match, we can't switch the display clock
4574 * by using the FP0/FP1. In such case we will disable the LVDS
4575 * downclock feature.
4576 */
ddc9003c 4577 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4578 dev_priv->lvds_downclock,
4579 refclk,
cec2f356 4580 &clock,
5eddb70b 4581 &reduced_clock);
7026d4ac
ZW		 4582 }
4583
c65d77d8
JB		 4584 if (is_sdvo && is_tv)
4585 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 4586
eb1cbe48 4587 if (IS_GEN2(dev))
2a8f64ca
VP		 4588 i8xx_update_pll(crtc, adjusted_mode, &clock,
4589 has_reduced_clock ? &reduced_clock : NULL,
4590 num_connectors);
a0c4da24 4591 else if (IS_VALLEYVIEW(dev))
6cc5f341 4592 vlv_update_pll(crtc, &clock,
2a8f64ca
VP		 4593 has_reduced_clock ? &reduced_clock : NULL,
4594 num_connectors);
79e53945 4595 else
6cc5f341 4596 i9xx_update_pll(crtc, &clock,
eb1cbe48
DV		 4597 has_reduced_clock ? &reduced_clock : NULL,
4598 num_connectors);
79e53945
JB		 4599
4600 /* setup pipeconf */
5eddb70b 4601 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4602
4603 /* Set up the display plane register */
4604 dspcntr = DISPPLANE_GAMMA_ENABLE;
4605
da6ecc5d
JB		 4606 if (!IS_VALLEYVIEW(dev)) {
4607 if (pipe == 0)
4608 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4609 else
4610 dspcntr |= DISPPLANE_SEL_PIPE_B;
4611 }
79e53945 4612
a6c45cf0 4613 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4614 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4615 * core speed.
4616 *
4617 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4618 * pipe == 0 check?
4619 */
e70236a8
JB		 4620 if (mode->clock >
4621 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4622 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4623 else
5eddb70b 4624 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4625 }
4626
3b5c78a3 4627 /* default to 8bpc */
dfd07d72 4628 pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
3b5c78a3 4629 if (is_dp) {
965e0c48 4630 if (intel_crtc->config.dither) {
dfd07d72 4631 pipeconf |= PIPECONF_6BPC |
3b5c78a3
AJ		 4632 PIPECONF_DITHER_EN |
4633 PIPECONF_DITHER_TYPE_SP;
4634 }
4635 }
4636
19c03924 4637 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
965e0c48 4638 if (intel_crtc->config.dither) {
dfd07d72 4639 pipeconf |= PIPECONF_6BPC |
19c03924
GB		 4640 PIPECONF_ENABLE |
4641 I965_PIPECONF_ACTIVE;
4642 }
4643 }
4644
28c97730 4645 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4646 drm_mode_debug_printmodeline(mode);
4647
a7516a05
JB		 4648 if (HAS_PIPE_CXSR(dev)) {
4649 if (intel_crtc->lowfreq_avail) {
28c97730 4650 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 4651 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 4652 } else {
28c97730 4653 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4654 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4655 }
4656 }
4657
617cf884 4658 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575 4659 if (!IS_GEN2(dev) &&
b0e77b9c 4660 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
734b4157 4661 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
b0e77b9c 4662 else
617cf884 4663 pipeconf |= PIPECONF_PROGRESSIVE;
734b4157 4664
b0e77b9c 4665 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4666
4667 /* pipesrc and dspsize control the size that is scaled from,
4668 * which should always be the user's requested size.
79e53945 4669 */
929c77fb
EA		 4670 I915_WRITE(DSPSIZE(plane),
4671 ((mode->vdisplay - 1) << 16) |
4672 (mode->hdisplay - 1));
4673 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4674
f564048e
EA		 4675 I915_WRITE(PIPECONF(pipe), pipeconf);
4676 POSTING_READ(PIPECONF(pipe));
929c77fb 4677 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4678
4679 intel_wait_for_vblank(dev, pipe);
4680
f564048e
EA		 4681 I915_WRITE(DSPCNTR(plane), dspcntr);
4682 POSTING_READ(DSPCNTR(plane));
4683
94352cf9 4684 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4685
4686 intel_update_watermarks(dev);
4687
f564048e
EA		 4688 return ret;
4689}
4690
dde86e2d 4691static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4692{
4693 struct drm_i915_private *dev_priv = dev->dev_private;
4694 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4695 struct intel_encoder *encoder;
13d83a67
JB		 4696 u32 temp;
4697 bool has_lvds = false;
199e5d79
KP		 4698 bool has_cpu_edp = false;
4699 bool has_pch_edp = false;
4700 bool has_panel = false;
99eb6a01
KP		 4701 bool has_ck505 = false;
4702 bool can_ssc = false;
13d83a67
JB		 4703
4704 /* We need to take the global config into account */
199e5d79
KP		 4705 list_for_each_entry(encoder, &mode_config->encoder_list,
4706 base.head) {
4707 switch (encoder->type) {
4708 case INTEL_OUTPUT_LVDS:
4709 has_panel = true;
4710 has_lvds = true;
4711 break;
4712 case INTEL_OUTPUT_EDP:
4713 has_panel = true;
4714 if (intel_encoder_is_pch_edp(&encoder->base))
4715 has_pch_edp = true;
4716 else
4717 has_cpu_edp = true;
4718 break;
13d83a67
JB		 4719 }
4720 }
4721
99eb6a01
KP		 4722 if (HAS_PCH_IBX(dev)) {
4723 has_ck505 = dev_priv->display_clock_mode;
4724 can_ssc = has_ck505;
4725 } else {
4726 has_ck505 = false;
4727 can_ssc = true;
4728 }
4729
4730 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4731 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4732 has_ck505);
13d83a67
JB		 4733
4734 /* Ironlake: try to setup display ref clock before DPLL
4735 * enabling. This is only under driver's control after
4736 * PCH B stepping, previous chipset stepping should be
4737 * ignoring this setting.
4738 */
4739 temp = I915_READ(PCH_DREF_CONTROL);
4740 /* Always enable nonspread source */
4741 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4742
99eb6a01
KP		 4743 if (has_ck505)
4744 temp |= DREF_NONSPREAD_CK505_ENABLE;
4745 else
4746 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4747
199e5d79
KP		 4748 if (has_panel) {
4749 temp &= ~DREF_SSC_SOURCE_MASK;
4750 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4751
199e5d79 4752 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4753 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4754 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4755 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4756 } else
4757 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4758
4759 /* Get SSC going before enabling the outputs */
4760 I915_WRITE(PCH_DREF_CONTROL, temp);
4761 POSTING_READ(PCH_DREF_CONTROL);
4762 udelay(200);
4763
13d83a67
JB		 4764 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4765
4766 /* Enable CPU source on CPU attached eDP */
199e5d79 4767 if (has_cpu_edp) {
99eb6a01 4768 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4769 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4770 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4771 }
13d83a67
JB		 4772 else
4773 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4774 } else
4775 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4776
4777 I915_WRITE(PCH_DREF_CONTROL, temp);
4778 POSTING_READ(PCH_DREF_CONTROL);
4779 udelay(200);
4780 } else {
4781 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4782
4783 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4784
4785 /* Turn off CPU output */
4786 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4787
4788 I915_WRITE(PCH_DREF_CONTROL, temp);
4789 POSTING_READ(PCH_DREF_CONTROL);
4790 udelay(200);
4791
4792 /* Turn off the SSC source */
4793 temp &= ~DREF_SSC_SOURCE_MASK;
4794 temp |= DREF_SSC_SOURCE_DISABLE;
4795
4796 /* Turn off SSC1 */
4797 temp &= ~ DREF_SSC1_ENABLE;
4798
13d83a67
JB		 4799 I915_WRITE(PCH_DREF_CONTROL, temp);
4800 POSTING_READ(PCH_DREF_CONTROL);
4801 udelay(200);
4802 }
4803}
4804
dde86e2d
PZ		 4805/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4806static void lpt_init_pch_refclk(struct drm_device *dev)
4807{
4808 struct drm_i915_private *dev_priv = dev->dev_private;
4809 struct drm_mode_config *mode_config = &dev->mode_config;
4810 struct intel_encoder *encoder;
4811 bool has_vga = false;
4812 bool is_sdv = false;
4813 u32 tmp;
4814
4815 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4816 switch (encoder->type) {
4817 case INTEL_OUTPUT_ANALOG:
4818 has_vga = true;
4819 break;
4820 }
4821 }
4822
4823 if (!has_vga)
4824 return;
4825
c00db246
DV		 4826 mutex_lock(&dev_priv->dpio_lock);
4827
dde86e2d
PZ		 4828 /* XXX: Rip out SDV support once Haswell ships for real. */
4829 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
4830 is_sdv = true;
4831
4832 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4833 tmp &= ~SBI_SSCCTL_DISABLE;
4834 tmp |= SBI_SSCCTL_PATHALT;
4835 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4836
4837 udelay(24);
4838
4839 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4840 tmp &= ~SBI_SSCCTL_PATHALT;
4841 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4842
4843 if (!is_sdv) {
4844 tmp = I915_READ(SOUTH_CHICKEN2);
4845 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
4846 I915_WRITE(SOUTH_CHICKEN2, tmp);
4847
4848 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
4849 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
4850 DRM_ERROR("FDI mPHY reset assert timeout\n");
4851
4852 tmp = I915_READ(SOUTH_CHICKEN2);
4853 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
4854 I915_WRITE(SOUTH_CHICKEN2, tmp);
4855
4856 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
4857 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
4858 100))
4859 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
4860 }
4861
4862 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
4863 tmp &= ~(0xFF << 24);
4864 tmp |= (0x12 << 24);
4865 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
4866
4867 if (!is_sdv) {
4868 tmp = intel_sbi_read(dev_priv, 0x808C, SBI_MPHY);
4869 tmp &= ~(0x3 << 6);
4870 tmp |= (1 << 6) | (1 << 0);
4871 intel_sbi_write(dev_priv, 0x808C, tmp, SBI_MPHY);
4872 }
4873
4874 if (is_sdv) {
4875 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
4876 tmp |= 0x7FFF;
4877 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
4878 }
4879
4880 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
4881 tmp |= (1 << 11);
4882 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
4883
4884 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
4885 tmp |= (1 << 11);
4886 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
4887
4888 if (is_sdv) {
4889 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
4890 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4891 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
4892
4893 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
4894 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4895 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
4896
4897 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
4898 tmp |= (0x3F << 8);
4899 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
4900
4901 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
4902 tmp |= (0x3F << 8);
4903 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
4904 }
4905
4906 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
4907 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
4908 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
4909
4910 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
4911 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
4912 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
4913
4914 if (!is_sdv) {
4915 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
4916 tmp &= ~(7 << 13);
4917 tmp |= (5 << 13);
4918 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
4919
4920 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
4921 tmp &= ~(7 << 13);
4922 tmp |= (5 << 13);
4923 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
4924 }
4925
4926 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
4927 tmp &= ~0xFF;
4928 tmp |= 0x1C;
4929 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
4930
4931 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
4932 tmp &= ~0xFF;
4933 tmp |= 0x1C;
4934 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
4935
4936 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
4937 tmp &= ~(0xFF << 16);
4938 tmp |= (0x1C << 16);
4939 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
4940
4941 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
4942 tmp &= ~(0xFF << 16);
4943 tmp |= (0x1C << 16);
4944 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
4945
4946 if (!is_sdv) {
4947 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
4948 tmp |= (1 << 27);
4949 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
4950
4951 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
4952 tmp |= (1 << 27);
4953 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
4954
4955 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
4956 tmp &= ~(0xF << 28);
4957 tmp |= (4 << 28);
4958 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
4959
4960 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
4961 tmp &= ~(0xF << 28);
4962 tmp |= (4 << 28);
4963 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
4964 }
4965
4966 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
4967 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
4968 tmp |= SBI_DBUFF0_ENABLE;
4969 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 4970
4971 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 4972}
4973
4974/*
4975 * Initialize reference clocks when the driver loads
4976 */
4977void intel_init_pch_refclk(struct drm_device *dev)
4978{
4979 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4980 ironlake_init_pch_refclk(dev);
4981 else if (HAS_PCH_LPT(dev))
4982 lpt_init_pch_refclk(dev);
4983}
4984
d9d444cb
JB		 4985static int ironlake_get_refclk(struct drm_crtc *crtc)
4986{
4987 struct drm_device *dev = crtc->dev;
4988 struct drm_i915_private *dev_priv = dev->dev_private;
4989 struct intel_encoder *encoder;
d9d444cb
JB		 4990 struct intel_encoder *edp_encoder = NULL;
4991 int num_connectors = 0;
4992 bool is_lvds = false;
4993
6c2b7c12 4994 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 4995 switch (encoder->type) {
4996 case INTEL_OUTPUT_LVDS:
4997 is_lvds = true;
4998 break;
4999 case INTEL_OUTPUT_EDP:
5000 edp_encoder = encoder;
5001 break;
5002 }
5003 num_connectors++;
5004 }
5005
5006 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5007 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5008 dev_priv->lvds_ssc_freq);
5009 return dev_priv->lvds_ssc_freq * 1000;
5010 }
5011
5012 return 120000;
5013}
5014
c8203565 5015static void ironlake_set_pipeconf(struct drm_crtc *crtc,
f564048e 5016 struct drm_display_mode *adjusted_mode,
c8203565 5017 bool dither)
79e53945 5018{
c8203565 5019 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5020 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5021 int pipe = intel_crtc->pipe;
c8203565
PZ		 5022 uint32_t val;
5023
5024 val = I915_READ(PIPECONF(pipe));
5025
dfd07d72 5026 val &= ~PIPECONF_BPC_MASK;
965e0c48 5027 switch (intel_crtc->config.pipe_bpp) {
c8203565 5028 case 18:
dfd07d72 5029 val |= PIPECONF_6BPC;
c8203565
PZ		 5030 break;
5031 case 24:
dfd07d72 5032 val |= PIPECONF_8BPC;
c8203565
PZ		 5033 break;
5034 case 30:
dfd07d72 5035 val |= PIPECONF_10BPC;
c8203565
PZ		 5036 break;
5037 case 36:
dfd07d72 5038 val |= PIPECONF_12BPC;
c8203565
PZ		 5039 break;
5040 default:
cc769b62
PZ		 5041 /* Case prevented by intel_choose_pipe_bpp_dither. */
5042 BUG();
c8203565
PZ		 5043 }
5044
5045 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5046 if (dither)
5047 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5048
5049 val &= ~PIPECONF_INTERLACE_MASK;
5050 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5051 val |= PIPECONF_INTERLACED_ILK;
5052 else
5053 val |= PIPECONF_PROGRESSIVE;
5054
50f3b016 5055 if (intel_crtc->config.limited_color_range)
3685a8f3
VS		 5056 val |= PIPECONF_COLOR_RANGE_SELECT;
5057 else
5058 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5059
c8203565
PZ		 5060 I915_WRITE(PIPECONF(pipe), val);
5061 POSTING_READ(PIPECONF(pipe));
5062}
5063
86d3efce
VS		 5064/*
5065 * Set up the pipe CSC unit.
5066 *
5067 * Currently only full range RGB to limited range RGB conversion
5068 * is supported, but eventually this should handle various
5069 * RGB<->YCbCr scenarios as well.
5070 */
50f3b016 5071static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5072{
5073 struct drm_device *dev = crtc->dev;
5074 struct drm_i915_private *dev_priv = dev->dev_private;
5075 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5076 int pipe = intel_crtc->pipe;
5077 uint16_t coeff = 0x7800; /* 1.0 */
5078
5079 /*
5080 * TODO: Check what kind of values actually come out of the pipe
5081 * with these coeff/postoff values and adjust to get the best
5082 * accuracy. Perhaps we even need to take the bpc value into
5083 * consideration.
5084 */
5085
50f3b016 5086 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5087 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5088
5089 /*
5090 * GY/GU and RY/RU should be the other way around according
5091 * to BSpec, but reality doesn't agree. Just set them up in
5092 * a way that results in the correct picture.
5093 */
5094 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5095 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5096
5097 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5098 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5099
5100 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5101 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5102
5103 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5104 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5105 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5106
5107 if (INTEL_INFO(dev)->gen > 6) {
5108 uint16_t postoff = 0;
5109
50f3b016 5110 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5111 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5112
5113 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5114 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5115 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5116
5117 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5118 } else {
5119 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5120
50f3b016 5121 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5122 mode |= CSC_BLACK_SCREEN_OFFSET;
5123
5124 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5125 }
5126}
5127
ee2b0b38
PZ		 5128static void haswell_set_pipeconf(struct drm_crtc *crtc,
5129 struct drm_display_mode *adjusted_mode,
5130 bool dither)
5131{
5132 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5133 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
702e7a56 5134 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
ee2b0b38
PZ		 5135 uint32_t val;
5136
702e7a56 5137 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5138
5139 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5140 if (dither)
5141 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5142
5143 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5144 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5145 val |= PIPECONF_INTERLACED_ILK;
5146 else
5147 val |= PIPECONF_PROGRESSIVE;
5148
702e7a56
PZ		 5149 I915_WRITE(PIPECONF(cpu_transcoder), val);
5150 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5151}
5152
6591c6e4
PZ		 5153static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5154 struct drm_display_mode *adjusted_mode,
5155 intel_clock_t *clock,
5156 bool *has_reduced_clock,
5157 intel_clock_t *reduced_clock)
5158{
5159 struct drm_device *dev = crtc->dev;
5160 struct drm_i915_private *dev_priv = dev->dev_private;
5161 struct intel_encoder *intel_encoder;
5162 int refclk;
d4906093 5163 const intel_limit_t *limit;
6591c6e4 5164 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
79e53945 5165
6591c6e4
PZ		 5166 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5167 switch (intel_encoder->type) {
79e53945
JB		 5168 case INTEL_OUTPUT_LVDS:
5169 is_lvds = true;
5170 break;
5171 case INTEL_OUTPUT_SDVO:
7d57382e 5172 case INTEL_OUTPUT_HDMI:
79e53945 5173 is_sdvo = true;
6591c6e4 5174 if (intel_encoder->needs_tv_clock)
e2f0ba97 5175 is_tv = true;
79e53945 5176 break;
79e53945
JB		 5177 case INTEL_OUTPUT_TVOUT:
5178 is_tv = true;
5179 break;
79e53945
JB		 5180 }
5181 }
5182
d9d444cb 5183 refclk = ironlake_get_refclk(crtc);
79e53945 5184
d4906093
ML		 5185 /*
5186 * Returns a set of divisors for the desired target clock with the given
5187 * refclk, or FALSE. The returned values represent the clock equation:
5188 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5189 */
1b894b59 5190 limit = intel_limit(crtc, refclk);
6591c6e4
PZ		 5191 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5192 clock);
5193 if (!ret)
5194 return false;
cda4b7d3 5195
ddc9003c 5196 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5197 /*
5198 * Ensure we match the reduced clock's P to the target clock.
5199 * If the clocks don't match, we can't switch the display clock
5200 * by using the FP0/FP1. In such case we will disable the LVDS
5201 * downclock feature.
5202 */
6591c6e4
PZ		 5203 *has_reduced_clock = limit->find_pll(limit, crtc,
5204 dev_priv->lvds_downclock,
5205 refclk,
5206 clock,
5207 reduced_clock);
652c393a 5208 }
61e9653f
DV		 5209
5210 if (is_sdvo && is_tv)
6591c6e4
PZ		 5211 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5212
5213 return true;
5214}
5215
01a415fd
DV		 5216static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5217{
5218 struct drm_i915_private *dev_priv = dev->dev_private;
5219 uint32_t temp;
5220
5221 temp = I915_READ(SOUTH_CHICKEN1);
5222 if (temp & FDI_BC_BIFURCATION_SELECT)
5223 return;
5224
5225 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5226 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5227
5228 temp |= FDI_BC_BIFURCATION_SELECT;
5229 DRM_DEBUG_KMS("enabling fdi C rx\n");
5230 I915_WRITE(SOUTH_CHICKEN1, temp);
5231 POSTING_READ(SOUTH_CHICKEN1);
5232}
5233
5234static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5235{
5236 struct drm_device *dev = intel_crtc->base.dev;
5237 struct drm_i915_private *dev_priv = dev->dev_private;
5238 struct intel_crtc *pipe_B_crtc =
5239 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5240
5241 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5242 intel_crtc->pipe, intel_crtc->fdi_lanes);
5243 if (intel_crtc->fdi_lanes > 4) {
5244 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5245 intel_crtc->pipe, intel_crtc->fdi_lanes);
5246 /* Clamp lanes to avoid programming the hw with bogus values. */
5247 intel_crtc->fdi_lanes = 4;
5248
5249 return false;
5250 }
5251
7eb552ae 5252 if (INTEL_INFO(dev)->num_pipes == 2)
01a415fd
DV		 5253 return true;
5254
5255 switch (intel_crtc->pipe) {
5256 case PIPE_A:
5257 return true;
5258 case PIPE_B:
5259 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5260 intel_crtc->fdi_lanes > 2) {
5261 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5262 intel_crtc->pipe, intel_crtc->fdi_lanes);
5263 /* Clamp lanes to avoid programming the hw with bogus values. */
5264 intel_crtc->fdi_lanes = 2;
5265
5266 return false;
5267 }
5268
5269 if (intel_crtc->fdi_lanes > 2)
5270 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5271 else
5272 cpt_enable_fdi_bc_bifurcation(dev);
5273
5274 return true;
5275 case PIPE_C:
5276 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5277 if (intel_crtc->fdi_lanes > 2) {
5278 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5279 intel_crtc->pipe, intel_crtc->fdi_lanes);
5280 /* Clamp lanes to avoid programming the hw with bogus values. */
5281 intel_crtc->fdi_lanes = 2;
5282
5283 return false;
5284 }
5285 } else {
5286 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5287 return false;
5288 }
5289
5290 cpt_enable_fdi_bc_bifurcation(dev);
5291
5292 return true;
5293 default:
5294 BUG();
5295 }
5296}
5297
d4b1931c
PZ		 5298int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5299{
5300 /*
5301 * Account for spread spectrum to avoid
5302 * oversubscribing the link. Max center spread
5303 * is 2.5%; use 5% for safety's sake.
5304 */
5305 u32 bps = target_clock * bpp * 21 / 20;
5306 return bps / (link_bw * 8) + 1;
5307}
5308
6cc5f341 5309static void ironlake_set_m_n(struct drm_crtc *crtc)
79e53945
JB		 5310{
5311 struct drm_device *dev = crtc->dev;
5312 struct drm_i915_private *dev_priv = dev->dev_private;
5313 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6cc5f341
DV		 5314 struct drm_display_mode *adjusted_mode =
5315 &intel_crtc->config.adjusted_mode;
5316 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
afe2fcf5 5317 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
f48d8f23 5318 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
e69d0bc1 5319 struct intel_link_m_n m_n = {0};
6cc5f341 5320 int target_clock, lane, link_bw;
f48d8f23 5321 bool is_dp = false, is_cpu_edp = false;
79e53945 5322
f48d8f23
PZ		 5323 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5324 switch (intel_encoder->type) {
a4fc5ed6
KP		 5325 case INTEL_OUTPUT_DISPLAYPORT:
5326 is_dp = true;
5327 break;
32f9d658 5328 case INTEL_OUTPUT_EDP:
e3aef172 5329 is_dp = true;
f48d8f23 5330 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5331 is_cpu_edp = true;
f48d8f23 5332 edp_encoder = intel_encoder;
32f9d658 5333 break;
79e53945 5334 }
79e53945 5335 }
61e9653f 5336
2c07245f 5337 /* FDI link */
8febb297
EA		 5338 lane = 0;
5339 /* CPU eDP doesn't require FDI link, so just set DP M/N
5340 according to current link config */
e3aef172 5341 if (is_cpu_edp) {
e3aef172 5342 intel_edp_link_config(edp_encoder, &lane, &link_bw);
8febb297 5343 } else {
8febb297
EA		 5344 /* FDI is a binary signal running at ~2.7GHz, encoding
5345 * each output octet as 10 bits. The actual frequency
5346 * is stored as a divider into a 100MHz clock, and the
5347 * mode pixel clock is stored in units of 1KHz.
5348 * Hence the bw of each lane in terms of the mode signal
5349 * is:
5350 */
5351 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5352 }
58a27471 5353
94bf2ced
DV		 5354 /* [e]DP over FDI requires target mode clock instead of link clock. */
5355 if (edp_encoder)
5356 target_clock = intel_edp_target_clock(edp_encoder, mode);
5357 else if (is_dp)
5358 target_clock = mode->clock;
5359 else
5360 target_clock = adjusted_mode->clock;
5361
d4b1931c
PZ		 5362 if (!lane)
5363 lane = ironlake_get_lanes_required(target_clock, link_bw,
965e0c48 5364 intel_crtc->config.pipe_bpp);
2c07245f 5365
8febb297
EA		 5366 intel_crtc->fdi_lanes = lane;
5367
6cc5f341
DV		 5368 if (intel_crtc->config.pixel_multiplier > 1)
5369 link_bw *= intel_crtc->config.pixel_multiplier;
965e0c48
DV		 5370 intel_link_compute_m_n(intel_crtc->config.pipe_bpp, lane, target_clock,
5371 link_bw, &m_n);
8febb297 5372
afe2fcf5
PZ		 5373 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5374 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5375 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5376 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
f48d8f23
PZ		 5377}
5378
de13a2e3 5379static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
de13a2e3 5380 intel_clock_t *clock, u32 fp)
79e53945 5381{
de13a2e3 5382 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5383 struct drm_device *dev = crtc->dev;
5384 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5385 struct intel_encoder *intel_encoder;
5386 uint32_t dpll;
6cc5f341 5387 int factor, num_connectors = 0;
de13a2e3
PZ		 5388 bool is_lvds = false, is_sdvo = false, is_tv = false;
5389 bool is_dp = false, is_cpu_edp = false;
79e53945 5390
de13a2e3
PZ		 5391 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5392 switch (intel_encoder->type) {
79e53945
JB		 5393 case INTEL_OUTPUT_LVDS:
5394 is_lvds = true;
5395 break;
5396 case INTEL_OUTPUT_SDVO:
7d57382e 5397 case INTEL_OUTPUT_HDMI:
79e53945 5398 is_sdvo = true;
de13a2e3 5399 if (intel_encoder->needs_tv_clock)
e2f0ba97 5400 is_tv = true;
79e53945 5401 break;
79e53945
JB		 5402 case INTEL_OUTPUT_TVOUT:
5403 is_tv = true;
5404 break;
a4fc5ed6
KP		 5405 case INTEL_OUTPUT_DISPLAYPORT:
5406 is_dp = true;
5407 break;
32f9d658 5408 case INTEL_OUTPUT_EDP:
e3aef172 5409 is_dp = true;
de13a2e3 5410 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5411 is_cpu_edp = true;
32f9d658 5412 break;
79e53945 5413 }
43565a06 5414
c751ce4f 5415 num_connectors++;
79e53945 5416 }
79e53945 5417
c1858123 5418 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5419 factor = 21;
5420 if (is_lvds) {
5421 if ((intel_panel_use_ssc(dev_priv) &&
5422 dev_priv->lvds_ssc_freq == 100) ||
1974cad0 5423 intel_is_dual_link_lvds(dev))
8febb297
EA		 5424 factor = 25;
5425 } else if (is_sdvo && is_tv)
5426 factor = 20;
c1858123 5427
de13a2e3 5428 if (clock->m < factor * clock->n)
8febb297 5429 fp |= FP_CB_TUNE;
2c07245f 5430
5eddb70b 5431 dpll = 0;
2c07245f 5432
a07d6787
EA		 5433 if (is_lvds)
5434 dpll |= DPLLB_MODE_LVDS;
5435 else
5436 dpll |= DPLLB_MODE_DAC_SERIAL;
5437 if (is_sdvo) {
6cc5f341
DV		 5438 if (intel_crtc->config.pixel_multiplier > 1) {
5439 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5440 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5441 }
a07d6787
EA		 5442 dpll |= DPLL_DVO_HIGH_SPEED;
5443 }
e3aef172 5444 if (is_dp && !is_cpu_edp)
a07d6787 5445 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5446
a07d6787 5447 /* compute bitmask from p1 value */
de13a2e3 5448 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5449 /* also FPA1 */
de13a2e3 5450 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5451
de13a2e3 5452 switch (clock->p2) {
a07d6787
EA		 5453 case 5:
5454 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5455 break;
5456 case 7:
5457 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5458 break;
5459 case 10:
5460 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5461 break;
5462 case 14:
5463 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5464 break;
79e53945
JB		 5465 }
5466
43565a06
KH		 5467 if (is_sdvo && is_tv)
5468 dpll |= PLL_REF_INPUT_TVCLKINBC;
5469 else if (is_tv)
79e53945 5470 /* XXX: just matching BIOS for now */
43565a06 5471 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5472 dpll |= 3;
a7615030 5473 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5474 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5475 else
5476 dpll |= PLL_REF_INPUT_DREFCLK;
5477
de13a2e3
PZ		 5478 return dpll;
5479}
5480
5481static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5482 int x, int y,
5483 struct drm_framebuffer *fb)
5484{
5485 struct drm_device *dev = crtc->dev;
5486 struct drm_i915_private *dev_priv = dev->dev_private;
5487 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5488 struct drm_display_mode *adjusted_mode =
5489 &intel_crtc->config.adjusted_mode;
5490 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
de13a2e3
PZ		 5491 int pipe = intel_crtc->pipe;
5492 int plane = intel_crtc->plane;
5493 int num_connectors = 0;
5494 intel_clock_t clock, reduced_clock;
5495 u32 dpll, fp = 0, fp2 = 0;
e2f12b07
PZ		 5496 bool ok, has_reduced_clock = false;
5497 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
de13a2e3 5498 struct intel_encoder *encoder;
de13a2e3 5499 int ret;
01a415fd 5500 bool dither, fdi_config_ok;
de13a2e3
PZ		 5501
5502 for_each_encoder_on_crtc(dev, crtc, encoder) {
5503 switch (encoder->type) {
5504 case INTEL_OUTPUT_LVDS:
5505 is_lvds = true;
5506 break;
de13a2e3
PZ		 5507 case INTEL_OUTPUT_DISPLAYPORT:
5508 is_dp = true;
5509 break;
5510 case INTEL_OUTPUT_EDP:
5511 is_dp = true;
e2f12b07 5512 if (!intel_encoder_is_pch_edp(&encoder->base))
de13a2e3
PZ		 5513 is_cpu_edp = true;
5514 break;
5515 }
5516
5517 num_connectors++;
a07d6787 5518 }
79e53945 5519
5dc5298b
PZ		 5520 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5521 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5522
de13a2e3
PZ		 5523 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5524 &has_reduced_clock, &reduced_clock);
5525 if (!ok) {
5526 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5527 return -EINVAL;
79e53945
JB		 5528 }
5529
de13a2e3
PZ		 5530 /* Ensure that the cursor is valid for the new mode before changing... */
5531 intel_crtc_update_cursor(crtc, true);
5532
5533 /* determine panel color depth */
4e53c2e0 5534 dither = intel_crtc->config.dither;
de13a2e3
PZ		 5535 if (is_lvds && dev_priv->lvds_dither)
5536 dither = true;
5537
5538 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5539 if (has_reduced_clock)
5540 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5541 reduced_clock.m2;
5542
6cc5f341 5543 dpll = ironlake_compute_dpll(intel_crtc, &clock, fp);
79e53945 5544
f7cb34d4 5545 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5546 drm_mode_debug_printmodeline(mode);
5547
5dc5298b
PZ		 5548 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5549 if (!is_cpu_edp) {
ee7b9f93 5550 struct intel_pch_pll *pll;
4b645f14 5551
ee7b9f93
JB		 5552 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5553 if (pll == NULL) {
5554 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5555 pipe);
4b645f14
JB		 5556 return -EINVAL;
5557 }
ee7b9f93
JB		 5558 } else
5559 intel_put_pch_pll(intel_crtc);
79e53945 5560
2f0c2ad1 5561 if (is_dp && !is_cpu_edp)
a4fc5ed6 5562 intel_dp_set_m_n(crtc, mode, adjusted_mode);
79e53945 5563
dafd226c
DV		 5564 for_each_encoder_on_crtc(dev, crtc, encoder)
5565 if (encoder->pre_pll_enable)
5566 encoder->pre_pll_enable(encoder);
79e53945 5567
ee7b9f93
JB		 5568 if (intel_crtc->pch_pll) {
5569 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5570
32f9d658 5571 /* Wait for the clocks to stabilize. */
ee7b9f93 5572 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5573 udelay(150);
5574
8febb297
EA		 5575 /* The pixel multiplier can only be updated once the
5576 * DPLL is enabled and the clocks are stable.
5577 *
5578 * So write it again.
5579 */
ee7b9f93 5580 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5581 }
79e53945 5582
5eddb70b 5583 intel_crtc->lowfreq_avail = false;
ee7b9f93 5584 if (intel_crtc->pch_pll) {
4b645f14 5585 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5586 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5587 intel_crtc->lowfreq_avail = true;
4b645f14 5588 } else {
ee7b9f93 5589 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5590 }
5591 }
5592
b0e77b9c 5593 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b 5594
01a415fd
DV		 5595 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5596 * ironlake_check_fdi_lanes. */
6cc5f341 5597 ironlake_set_m_n(crtc);
2c07245f 5598
01a415fd 5599 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
2c07245f 5600
c8203565 5601 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
79e53945 5602
9d0498a2 5603 intel_wait_for_vblank(dev, pipe);
79e53945 5604
a1f9e77e
PZ		 5605 /* Set up the display plane register */
5606 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5607 POSTING_READ(DSPCNTR(plane));
79e53945 5608
94352cf9 5609 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5610
5611 intel_update_watermarks(dev);
5612
1f8eeabf
ED		 5613 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5614
01a415fd 5615 return fdi_config_ok ? ret : -EINVAL;
79e53945
JB		 5616}
5617
d6dd9eb1
DV		 5618static void haswell_modeset_global_resources(struct drm_device *dev)
5619{
5620 struct drm_i915_private *dev_priv = dev->dev_private;
5621 bool enable = false;
5622 struct intel_crtc *crtc;
5623 struct intel_encoder *encoder;
5624
5625 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5626 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5627 enable = true;
5628 /* XXX: Should check for edp transcoder here, but thanks to init
5629 * sequence that's not yet available. Just in case desktop eDP
5630 * on PORT D is possible on haswell, too. */
5631 }
5632
5633 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5634 base.head) {
5635 if (encoder->type != INTEL_OUTPUT_EDP &&
5636 encoder->connectors_active)
5637 enable = true;
5638 }
5639
5640 /* Even the eDP panel fitter is outside the always-on well. */
5641 if (dev_priv->pch_pf_size)
5642 enable = true;
5643
5644 intel_set_power_well(dev, enable);
5645}
5646
09b4ddf9 5647static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 5648 int x, int y,
5649 struct drm_framebuffer *fb)
5650{
5651 struct drm_device *dev = crtc->dev;
5652 struct drm_i915_private *dev_priv = dev->dev_private;
5653 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5654 struct drm_display_mode *adjusted_mode =
5655 &intel_crtc->config.adjusted_mode;
5656 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
09b4ddf9
PZ		 5657 int pipe = intel_crtc->pipe;
5658 int plane = intel_crtc->plane;
5659 int num_connectors = 0;
ed7ef439 5660 bool is_dp = false, is_cpu_edp = false;
09b4ddf9 5661 struct intel_encoder *encoder;
09b4ddf9
PZ		 5662 int ret;
5663 bool dither;
5664
5665 for_each_encoder_on_crtc(dev, crtc, encoder) {
5666 switch (encoder->type) {
09b4ddf9
PZ		 5667 case INTEL_OUTPUT_DISPLAYPORT:
5668 is_dp = true;
5669 break;
5670 case INTEL_OUTPUT_EDP:
5671 is_dp = true;
5672 if (!intel_encoder_is_pch_edp(&encoder->base))
5673 is_cpu_edp = true;
5674 break;
5675 }
5676
5677 num_connectors++;
5678 }
5679
5dc5298b
PZ		 5680 /* We are not sure yet this won't happen. */
5681 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5682 INTEL_PCH_TYPE(dev));
5683
5684 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5685 num_connectors, pipe_name(pipe));
5686
702e7a56 5687 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
1ce42920
PZ		 5688 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5689
5690 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5691
6441ab5f
PZ		 5692 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5693 return -EINVAL;
5694
09b4ddf9
PZ		 5695 /* Ensure that the cursor is valid for the new mode before changing... */
5696 intel_crtc_update_cursor(crtc, true);
5697
5698 /* determine panel color depth */
4e53c2e0 5699 dither = intel_crtc->config.dither;
09b4ddf9 5700
09b4ddf9
PZ		 5701 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5702 drm_mode_debug_printmodeline(mode);
5703
ed7ef439 5704 if (is_dp && !is_cpu_edp)
09b4ddf9 5705 intel_dp_set_m_n(crtc, mode, adjusted_mode);
09b4ddf9
PZ		 5706
5707 intel_crtc->lowfreq_avail = false;
09b4ddf9
PZ		 5708
5709 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5710
1eb8dfec 5711 if (!is_dp || is_cpu_edp)
6cc5f341 5712 ironlake_set_m_n(crtc);
09b4ddf9 5713
ee2b0b38 5714 haswell_set_pipeconf(crtc, adjusted_mode, dither);
09b4ddf9 5715
50f3b016 5716 intel_set_pipe_csc(crtc);
86d3efce 5717
09b4ddf9 5718 /* Set up the display plane register */
86d3efce 5719 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5720 POSTING_READ(DSPCNTR(plane));
5721
5722 ret = intel_pipe_set_base(crtc, x, y, fb);
5723
5724 intel_update_watermarks(dev);
5725
5726 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5727
1f803ee5 5728 return ret;
79e53945
JB		 5729}
5730
f564048e 5731static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 5732 int x, int y,
94352cf9 5733 struct drm_framebuffer *fb)
f564048e
EA		 5734{
5735 struct drm_device *dev = crtc->dev;
5736 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 5737 struct drm_encoder_helper_funcs *encoder_funcs;
5738 struct intel_encoder *encoder;
0b701d27 5739 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5740 struct drm_display_mode *adjusted_mode =
5741 &intel_crtc->config.adjusted_mode;
5742 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 5743 int pipe = intel_crtc->pipe;
f564048e
EA		 5744 int ret;
5745
cc464b2a
PZ		 5746 if (IS_HASWELL(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
5747 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5748 else
5749 intel_crtc->cpu_transcoder = pipe;
5750
0b701d27 5751 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5752
b8cecdf5
DV		 5753 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
5754
79e53945 5755 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5756
9256aa19
DV		 5757 if (ret != 0)
5758 return ret;
5759
5760 for_each_encoder_on_crtc(dev, crtc, encoder) {
5761 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5762 encoder->base.base.id,
5763 drm_get_encoder_name(&encoder->base),
5764 mode->base.id, mode->name);
6cc5f341
DV		 5765 if (encoder->mode_set) {
5766 encoder->mode_set(encoder);
5767 } else {
5768 encoder_funcs = encoder->base.helper_private;
5769 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5770 }
9256aa19
DV		 5771 }
5772
5773 return 0;
79e53945
JB		 5774}
5775
3a9627f4
WF		 5776static bool intel_eld_uptodate(struct drm_connector *connector,
5777 int reg_eldv, uint32_t bits_eldv,
5778 int reg_elda, uint32_t bits_elda,
5779 int reg_edid)
5780{
5781 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5782 uint8_t *eld = connector->eld;
5783 uint32_t i;
5784
5785 i = I915_READ(reg_eldv);
5786 i &= bits_eldv;
5787
5788 if (!eld[0])
5789 return !i;
5790
5791 if (!i)
5792 return false;
5793
5794 i = I915_READ(reg_elda);
5795 i &= ~bits_elda;
5796 I915_WRITE(reg_elda, i);
5797
5798 for (i = 0; i < eld[2]; i++)
5799 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5800 return false;
5801
5802 return true;
5803}
5804
e0dac65e
WF		 5805static void g4x_write_eld(struct drm_connector *connector,
5806 struct drm_crtc *crtc)
5807{
5808 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5809 uint8_t *eld = connector->eld;
5810 uint32_t eldv;
5811 uint32_t len;
5812 uint32_t i;
5813
5814 i = I915_READ(G4X_AUD_VID_DID);
5815
5816 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5817 eldv = G4X_ELDV_DEVCL_DEVBLC;
5818 else
5819 eldv = G4X_ELDV_DEVCTG;
5820
3a9627f4
WF		 5821 if (intel_eld_uptodate(connector,
5822 G4X_AUD_CNTL_ST, eldv,
5823 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5824 G4X_HDMIW_HDMIEDID))
5825 return;
5826
e0dac65e
WF		 5827 i = I915_READ(G4X_AUD_CNTL_ST);
5828 i &= ~(eldv | G4X_ELD_ADDR);
5829 len = (i >> 9) & 0x1f; /* ELD buffer size */
5830 I915_WRITE(G4X_AUD_CNTL_ST, i);
5831
5832 if (!eld[0])
5833 return;
5834
5835 len = min_t(uint8_t, eld[2], len);
5836 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5837 for (i = 0; i < len; i++)
5838 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5839
5840 i = I915_READ(G4X_AUD_CNTL_ST);
5841 i |= eldv;
5842 I915_WRITE(G4X_AUD_CNTL_ST, i);
5843}
5844
83358c85
WX		 5845static void haswell_write_eld(struct drm_connector *connector,
5846 struct drm_crtc *crtc)
5847{
5848 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5849 uint8_t *eld = connector->eld;
5850 struct drm_device *dev = crtc->dev;
7b9f35a6 5851 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 5852 uint32_t eldv;
5853 uint32_t i;
5854 int len;
5855 int pipe = to_intel_crtc(crtc)->pipe;
5856 int tmp;
5857
5858 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5859 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5860 int aud_config = HSW_AUD_CFG(pipe);
5861 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5862
5863
5864 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5865
5866 /* Audio output enable */
5867 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5868 tmp = I915_READ(aud_cntrl_st2);
5869 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5870 I915_WRITE(aud_cntrl_st2, tmp);
5871
5872 /* Wait for 1 vertical blank */
5873 intel_wait_for_vblank(dev, pipe);
5874
5875 /* Set ELD valid state */
5876 tmp = I915_READ(aud_cntrl_st2);
5877 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5878 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5879 I915_WRITE(aud_cntrl_st2, tmp);
5880 tmp = I915_READ(aud_cntrl_st2);
5881 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5882
5883 /* Enable HDMI mode */
5884 tmp = I915_READ(aud_config);
5885 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5886 /* clear N_programing_enable and N_value_index */
5887 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5888 I915_WRITE(aud_config, tmp);
5889
5890 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5891
5892 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 5893 intel_crtc->eld_vld = true;
83358c85
WX		 5894
5895 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5896 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5897 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5898 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5899 } else
5900 I915_WRITE(aud_config, 0);
5901
5902 if (intel_eld_uptodate(connector,
5903 aud_cntrl_st2, eldv,
5904 aud_cntl_st, IBX_ELD_ADDRESS,
5905 hdmiw_hdmiedid))
5906 return;
5907
5908 i = I915_READ(aud_cntrl_st2);
5909 i &= ~eldv;
5910 I915_WRITE(aud_cntrl_st2, i);
5911
5912 if (!eld[0])
5913 return;
5914
5915 i = I915_READ(aud_cntl_st);
5916 i &= ~IBX_ELD_ADDRESS;
5917 I915_WRITE(aud_cntl_st, i);
5918 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5919 DRM_DEBUG_DRIVER("port num:%d\n", i);
5920
5921 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5922 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5923 for (i = 0; i < len; i++)
5924 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5925
5926 i = I915_READ(aud_cntrl_st2);
5927 i |= eldv;
5928 I915_WRITE(aud_cntrl_st2, i);
5929
5930}
5931
e0dac65e
WF		 5932static void ironlake_write_eld(struct drm_connector *connector,
5933 struct drm_crtc *crtc)
5934{
5935 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5936 uint8_t *eld = connector->eld;
5937 uint32_t eldv;
5938 uint32_t i;
5939 int len;
5940 int hdmiw_hdmiedid;
b6daa025 5941 int aud_config;
e0dac65e
WF		 5942 int aud_cntl_st;
5943 int aud_cntrl_st2;
9b138a83 5944 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 5945
b3f33cbf 5946 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 5947 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5948 aud_config = IBX_AUD_CFG(pipe);
5949 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 5950 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 5951 } else {
9b138a83
WX		 5952 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5953 aud_config = CPT_AUD_CFG(pipe);
5954 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 5955 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 5956 }
5957
9b138a83 5958 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 5959
5960 i = I915_READ(aud_cntl_st);
9b138a83 5961 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 5962 if (!i) {
5963 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5964 /* operate blindly on all ports */
1202b4c6
WF		 5965 eldv = IBX_ELD_VALIDB;
5966 eldv |= IBX_ELD_VALIDB << 4;
5967 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 5968 } else {
5969 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 5970 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 5971 }
5972
3a9627f4
WF		 5973 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5974 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5975 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 5976 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5977 } else
5978 I915_WRITE(aud_config, 0);
e0dac65e 5979
3a9627f4
WF		 5980 if (intel_eld_uptodate(connector,
5981 aud_cntrl_st2, eldv,
5982 aud_cntl_st, IBX_ELD_ADDRESS,
5983 hdmiw_hdmiedid))
5984 return;
5985
e0dac65e
WF		 5986 i = I915_READ(aud_cntrl_st2);
5987 i &= ~eldv;
5988 I915_WRITE(aud_cntrl_st2, i);
5989
5990 if (!eld[0])
5991 return;
5992
e0dac65e 5993 i = I915_READ(aud_cntl_st);
1202b4c6 5994 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 5995 I915_WRITE(aud_cntl_st, i);
5996
5997 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5998 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5999 for (i = 0; i < len; i++)
6000 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6001
6002 i = I915_READ(aud_cntrl_st2);
6003 i |= eldv;
6004 I915_WRITE(aud_cntrl_st2, i);
6005}
6006
6007void intel_write_eld(struct drm_encoder *encoder,
6008 struct drm_display_mode *mode)
6009{
6010 struct drm_crtc *crtc = encoder->crtc;
6011 struct drm_connector *connector;
6012 struct drm_device *dev = encoder->dev;
6013 struct drm_i915_private *dev_priv = dev->dev_private;
6014
6015 connector = drm_select_eld(encoder, mode);
6016 if (!connector)
6017 return;
6018
6019 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6020 connector->base.id,
6021 drm_get_connector_name(connector),
6022 connector->encoder->base.id,
6023 drm_get_encoder_name(connector->encoder));
6024
6025 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6026
6027 if (dev_priv->display.write_eld)
6028 dev_priv->display.write_eld(connector, crtc);
6029}
6030
79e53945
JB		 6031/** Loads the palette/gamma unit for the CRTC with the prepared values */
6032void intel_crtc_load_lut(struct drm_crtc *crtc)
6033{
6034 struct drm_device *dev = crtc->dev;
6035 struct drm_i915_private *dev_priv = dev->dev_private;
6036 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6037 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6038 int i;
6039
6040 /* The clocks have to be on to load the palette. */
aed3f09d 6041 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6042 return;
6043
f2b115e6 6044 /* use legacy palette for Ironlake */
bad720ff 6045 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6046 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6047
79e53945
JB		 6048 for (i = 0; i < 256; i++) {
6049 I915_WRITE(palreg + 4 * i,
6050 (intel_crtc->lut_r[i] << 16) |
6051 (intel_crtc->lut_g[i] << 8) |
6052 intel_crtc->lut_b[i]);
6053 }
6054}
6055
560b85bb
CW		 6056static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6057{
6058 struct drm_device *dev = crtc->dev;
6059 struct drm_i915_private *dev_priv = dev->dev_private;
6060 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6061 bool visible = base != 0;
6062 u32 cntl;
6063
6064 if (intel_crtc->cursor_visible == visible)
6065 return;
6066
9db4a9c7 6067 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6068 if (visible) {
6069 /* On these chipsets we can only modify the base whilst
6070 * the cursor is disabled.
6071 */
9db4a9c7 6072 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6073
6074 cntl &= ~(CURSOR_FORMAT_MASK);
6075 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6076 cntl |= CURSOR_ENABLE |
6077 CURSOR_GAMMA_ENABLE |
6078 CURSOR_FORMAT_ARGB;
6079 } else
6080 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6081 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6082
6083 intel_crtc->cursor_visible = visible;
6084}
6085
6086static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6087{
6088 struct drm_device *dev = crtc->dev;
6089 struct drm_i915_private *dev_priv = dev->dev_private;
6090 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6091 int pipe = intel_crtc->pipe;
6092 bool visible = base != 0;
6093
6094 if (intel_crtc->cursor_visible != visible) {
548f245b 6095 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6096 if (base) {
6097 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6098 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6099 cntl |= pipe << 28; /* Connect to correct pipe */
6100 } else {
6101 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6102 cntl |= CURSOR_MODE_DISABLE;
6103 }
9db4a9c7 6104 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6105
6106 intel_crtc->cursor_visible = visible;
6107 }
6108 /* and commit changes on next vblank */
9db4a9c7 6109 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6110}
6111
65a21cd6
JB		 6112static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6113{
6114 struct drm_device *dev = crtc->dev;
6115 struct drm_i915_private *dev_priv = dev->dev_private;
6116 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6117 int pipe = intel_crtc->pipe;
6118 bool visible = base != 0;
6119
6120 if (intel_crtc->cursor_visible != visible) {
6121 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6122 if (base) {
6123 cntl &= ~CURSOR_MODE;
6124 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6125 } else {
6126 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6127 cntl |= CURSOR_MODE_DISABLE;
6128 }
86d3efce
VS		 6129 if (IS_HASWELL(dev))
6130 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6131 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6132
6133 intel_crtc->cursor_visible = visible;
6134 }
6135 /* and commit changes on next vblank */
6136 I915_WRITE(CURBASE_IVB(pipe), base);
6137}
6138
cda4b7d3 6139/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6140static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6141 bool on)
cda4b7d3
CW		 6142{
6143 struct drm_device *dev = crtc->dev;
6144 struct drm_i915_private *dev_priv = dev->dev_private;
6145 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6146 int pipe = intel_crtc->pipe;
6147 int x = intel_crtc->cursor_x;
6148 int y = intel_crtc->cursor_y;
560b85bb 6149 u32 base, pos;
cda4b7d3
CW		 6150 bool visible;
6151
6152 pos = 0;
6153
6b383a7f 6154 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6155 base = intel_crtc->cursor_addr;
6156 if (x > (int) crtc->fb->width)
6157 base = 0;
6158
6159 if (y > (int) crtc->fb->height)
6160 base = 0;
6161 } else
6162 base = 0;
6163
6164 if (x < 0) {
6165 if (x + intel_crtc->cursor_width < 0)
6166 base = 0;
6167
6168 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6169 x = -x;
6170 }
6171 pos |= x << CURSOR_X_SHIFT;
6172
6173 if (y < 0) {
6174 if (y + intel_crtc->cursor_height < 0)
6175 base = 0;
6176
6177 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6178 y = -y;
6179 }
6180 pos |= y << CURSOR_Y_SHIFT;
6181
6182 visible = base != 0;
560b85bb 6183 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6184 return;
6185
0cd83aa9 6186 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6187 I915_WRITE(CURPOS_IVB(pipe), pos);
6188 ivb_update_cursor(crtc, base);
6189 } else {
6190 I915_WRITE(CURPOS(pipe), pos);
6191 if (IS_845G(dev) || IS_I865G(dev))
6192 i845_update_cursor(crtc, base);
6193 else
6194 i9xx_update_cursor(crtc, base);
6195 }
cda4b7d3
CW		 6196}
6197
79e53945 6198static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6199 struct drm_file *file,
79e53945
JB		 6200 uint32_t handle,
6201 uint32_t width, uint32_t height)
6202{
6203 struct drm_device *dev = crtc->dev;
6204 struct drm_i915_private *dev_priv = dev->dev_private;
6205 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6206 struct drm_i915_gem_object *obj;
cda4b7d3 6207 uint32_t addr;
3f8bc370 6208 int ret;
79e53945 6209
79e53945
JB		 6210 /* if we want to turn off the cursor ignore width and height */
6211 if (!handle) {
28c97730 6212 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6213 addr = 0;
05394f39 6214 obj = NULL;
5004417d 6215 mutex_lock(&dev->struct_mutex);
3f8bc370 6216 goto finish;
79e53945
JB		 6217 }
6218
6219 /* Currently we only support 64x64 cursors */
6220 if (width != 64 || height != 64) {
6221 DRM_ERROR("we currently only support 64x64 cursors\n");
6222 return -EINVAL;
6223 }
6224
05394f39 6225 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6226 if (&obj->base == NULL)
79e53945
JB		 6227 return -ENOENT;
6228
05394f39 6229 if (obj->base.size < width * height * 4) {
79e53945 6230 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6231 ret = -ENOMEM;
6232 goto fail;
79e53945
JB		 6233 }
6234
71acb5eb 6235 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6236 mutex_lock(&dev->struct_mutex);
b295d1b6 6237 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6238 unsigned alignment;
6239
d9e86c0e
CW		 6240 if (obj->tiling_mode) {
6241 DRM_ERROR("cursor cannot be tiled\n");
6242 ret = -EINVAL;
6243 goto fail_locked;
6244 }
6245
693db184
CW		 6246 /* Note that the w/a also requires 2 PTE of padding following
6247 * the bo. We currently fill all unused PTE with the shadow
6248 * page and so we should always have valid PTE following the
6249 * cursor preventing the VT-d warning.
6250 */
6251 alignment = 0;
6252 if (need_vtd_wa(dev))
6253 alignment = 64*1024;
6254
6255 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6256 if (ret) {
6257 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6258 goto fail_locked;
e7b526bb
CW		 6259 }
6260
d9e86c0e
CW		 6261 ret = i915_gem_object_put_fence(obj);
6262 if (ret) {
2da3b9b9 6263 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6264 goto fail_unpin;
6265 }
6266
05394f39 6267 addr = obj->gtt_offset;
71acb5eb 6268 } else {
6eeefaf3 6269 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6270 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6271 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6272 align);
71acb5eb
DA		 6273 if (ret) {
6274 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6275 goto fail_locked;
71acb5eb 6276 }
05394f39 6277 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6278 }
6279
a6c45cf0 6280 if (IS_GEN2(dev))
14b60391
JB		 6281 I915_WRITE(CURSIZE, (height << 12) | width);
6282
3f8bc370 6283 finish:
3f8bc370 6284 if (intel_crtc->cursor_bo) {
b295d1b6 6285 if (dev_priv->info->cursor_needs_physical) {
05394f39 6286 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6287 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6288 } else
6289 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6290 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6291 }
80824003 6292
7f9872e0 6293 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6294
6295 intel_crtc->cursor_addr = addr;
05394f39 6296 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6297 intel_crtc->cursor_width = width;
6298 intel_crtc->cursor_height = height;
6299
6b383a7f 6300 intel_crtc_update_cursor(crtc, true);
3f8bc370 6301
79e53945 6302 return 0;
e7b526bb 6303fail_unpin:
05394f39 6304 i915_gem_object_unpin(obj);
7f9872e0 6305fail_locked:
34b8686e 6306 mutex_unlock(&dev->struct_mutex);
bc9025bd 6307fail:
05394f39 6308 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6309 return ret;
79e53945
JB		 6310}
6311
6312static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6313{
79e53945 6314 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6315
cda4b7d3
CW		 6316 intel_crtc->cursor_x = x;
6317 intel_crtc->cursor_y = y;
652c393a 6318
6b383a7f 6319 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6320
6321 return 0;
6322}
6323
6324/** Sets the color ramps on behalf of RandR */
6325void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6326 u16 blue, int regno)
6327{
6328 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6329
6330 intel_crtc->lut_r[regno] = red >> 8;
6331 intel_crtc->lut_g[regno] = green >> 8;
6332 intel_crtc->lut_b[regno] = blue >> 8;
6333}
6334
b8c00ac5
DA		 6335void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6336 u16 *blue, int regno)
6337{
6338 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6339
6340 *red = intel_crtc->lut_r[regno] << 8;
6341 *green = intel_crtc->lut_g[regno] << 8;
6342 *blue = intel_crtc->lut_b[regno] << 8;
6343}
6344
79e53945 6345static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6346 u16 *blue, uint32_t start, uint32_t size)
79e53945 6347{
7203425a 6348 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6349 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6350
7203425a 6351 for (i = start; i < end; i++) {
79e53945
JB		 6352 intel_crtc->lut_r[i] = red[i] >> 8;
6353 intel_crtc->lut_g[i] = green[i] >> 8;
6354 intel_crtc->lut_b[i] = blue[i] >> 8;
6355 }
6356
6357 intel_crtc_load_lut(crtc);
6358}
6359
79e53945
JB		 6360/* VESA 640x480x72Hz mode to set on the pipe */
6361static struct drm_display_mode load_detect_mode = {
6362 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6363 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6364};
6365
d2dff872
CW		 6366static struct drm_framebuffer *
6367intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6368 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6369 struct drm_i915_gem_object *obj)
6370{
6371 struct intel_framebuffer *intel_fb;
6372 int ret;
6373
6374 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6375 if (!intel_fb) {
6376 drm_gem_object_unreference_unlocked(&obj->base);
6377 return ERR_PTR(-ENOMEM);
6378 }
6379
6380 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6381 if (ret) {
6382 drm_gem_object_unreference_unlocked(&obj->base);
6383 kfree(intel_fb);
6384 return ERR_PTR(ret);
6385 }
6386
6387 return &intel_fb->base;
6388}
6389
6390static u32
6391intel_framebuffer_pitch_for_width(int width, int bpp)
6392{
6393 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6394 return ALIGN(pitch, 64);
6395}
6396
6397static u32
6398intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6399{
6400 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6401 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6402}
6403
6404static struct drm_framebuffer *
6405intel_framebuffer_create_for_mode(struct drm_device *dev,
6406 struct drm_display_mode *mode,
6407 int depth, int bpp)
6408{
6409 struct drm_i915_gem_object *obj;
0fed39bd 6410 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6411
6412 obj = i915_gem_alloc_object(dev,
6413 intel_framebuffer_size_for_mode(mode, bpp));
6414 if (obj == NULL)
6415 return ERR_PTR(-ENOMEM);
6416
6417 mode_cmd.width = mode->hdisplay;
6418 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6419 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6420 bpp);
5ca0c34a 6421 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6422
6423 return intel_framebuffer_create(dev, &mode_cmd, obj);
6424}
6425
6426static struct drm_framebuffer *
6427mode_fits_in_fbdev(struct drm_device *dev,
6428 struct drm_display_mode *mode)
6429{
6430 struct drm_i915_private *dev_priv = dev->dev_private;
6431 struct drm_i915_gem_object *obj;
6432 struct drm_framebuffer *fb;
6433
6434 if (dev_priv->fbdev == NULL)
6435 return NULL;
6436
6437 obj = dev_priv->fbdev->ifb.obj;
6438 if (obj == NULL)
6439 return NULL;
6440
6441 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6442 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6443 fb->bits_per_pixel))
d2dff872
CW		 6444 return NULL;
6445
01f2c773 6446 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6447 return NULL;
6448
6449 return fb;
6450}
6451
d2434ab7 6452bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6453 struct drm_display_mode *mode,
8261b191 6454 struct intel_load_detect_pipe *old)
79e53945
JB		 6455{
6456 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6457 struct intel_encoder *intel_encoder =
6458 intel_attached_encoder(connector);
79e53945 6459 struct drm_crtc *possible_crtc;
4ef69c7a 6460 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6461 struct drm_crtc *crtc = NULL;
6462 struct drm_device *dev = encoder->dev;
94352cf9 6463 struct drm_framebuffer *fb;
79e53945
JB		 6464 int i = -1;
6465
d2dff872
CW		 6466 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6467 connector->base.id, drm_get_connector_name(connector),
6468 encoder->base.id, drm_get_encoder_name(encoder));
6469
79e53945
JB		 6470 /*
6471 * Algorithm gets a little messy:
7a5e4805 6472 *
79e53945
JB		 6473 * - if the connector already has an assigned crtc, use it (but make
6474 * sure it's on first)
7a5e4805 6475 *
79e53945
JB		 6476 * - try to find the first unused crtc that can drive this connector,
6477 * and use that if we find one
79e53945
JB		 6478 */
6479
6480 /* See if we already have a CRTC for this connector */
6481 if (encoder->crtc) {
6482 crtc = encoder->crtc;
8261b191 6483
7b24056b
DV		 6484 mutex_lock(&crtc->mutex);
6485
24218aac 6486 old->dpms_mode = connector->dpms;
8261b191
CW		 6487 old->load_detect_temp = false;
6488
6489 /* Make sure the crtc and connector are running */
24218aac
DV		 6490 if (connector->dpms != DRM_MODE_DPMS_ON)
6491 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6492
7173188d 6493 return true;
79e53945
JB		 6494 }
6495
6496 /* Find an unused one (if possible) */
6497 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6498 i++;
6499 if (!(encoder->possible_crtcs & (1 << i)))
6500 continue;
6501 if (!possible_crtc->enabled) {
6502 crtc = possible_crtc;
6503 break;
6504 }
79e53945
JB		 6505 }
6506
6507 /*
6508 * If we didn't find an unused CRTC, don't use any.
6509 */
6510 if (!crtc) {
7173188d
CW		 6511 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6512 return false;
79e53945
JB		 6513 }
6514
7b24056b 6515 mutex_lock(&crtc->mutex);
fc303101
DV		 6516 intel_encoder->new_crtc = to_intel_crtc(crtc);
6517 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6518
6519 intel_crtc = to_intel_crtc(crtc);
24218aac 6520 old->dpms_mode = connector->dpms;
8261b191 6521 old->load_detect_temp = true;
d2dff872 6522 old->release_fb = NULL;
79e53945 6523
6492711d
CW		 6524 if (!mode)
6525 mode = &load_detect_mode;
79e53945 6526
d2dff872
CW		 6527 /* We need a framebuffer large enough to accommodate all accesses
6528 * that the plane may generate whilst we perform load detection.
6529 * We can not rely on the fbcon either being present (we get called
6530 * during its initialisation to detect all boot displays, or it may
6531 * not even exist) or that it is large enough to satisfy the
6532 * requested mode.
6533 */
94352cf9
DV		 6534 fb = mode_fits_in_fbdev(dev, mode);
6535 if (fb == NULL) {
d2dff872 6536 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6537 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6538 old->release_fb = fb;
d2dff872
CW		 6539 } else
6540 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6541 if (IS_ERR(fb)) {
d2dff872 6542 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6543 mutex_unlock(&crtc->mutex);
0e8b3d3e 6544 return false;
79e53945 6545 }
79e53945 6546
c0c36b94 6547 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6548 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6549 if (old->release_fb)
6550 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6551 mutex_unlock(&crtc->mutex);
0e8b3d3e 6552 return false;
79e53945 6553 }
7173188d 6554
79e53945 6555 /* let the connector get through one full cycle before testing */
9d0498a2 6556 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6557 return true;
79e53945
JB		 6558}
6559
d2434ab7 6560void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6561 struct intel_load_detect_pipe *old)
79e53945 6562{
d2434ab7
DV		 6563 struct intel_encoder *intel_encoder =
6564 intel_attached_encoder(connector);
4ef69c7a 6565 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6566 struct drm_crtc *crtc = encoder->crtc;
79e53945 6567
d2dff872
CW		 6568 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6569 connector->base.id, drm_get_connector_name(connector),
6570 encoder->base.id, drm_get_encoder_name(encoder));
6571
8261b191 6572 if (old->load_detect_temp) {
fc303101
DV		 6573 to_intel_connector(connector)->new_encoder = NULL;
6574 intel_encoder->new_crtc = NULL;
6575 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6576
36206361
DV		 6577 if (old->release_fb) {
6578 drm_framebuffer_unregister_private(old->release_fb);
6579 drm_framebuffer_unreference(old->release_fb);
6580 }
d2dff872 6581
67c96400 6582 mutex_unlock(&crtc->mutex);
0622a53c 6583 return;
79e53945
JB		 6584 }
6585
c751ce4f 6586 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6587 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6588 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6589
6590 mutex_unlock(&crtc->mutex);
79e53945
JB		 6591}
6592
6593/* Returns the clock of the currently programmed mode of the given pipe. */
6594static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6595{
6596 struct drm_i915_private *dev_priv = dev->dev_private;
6597 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6598 int pipe = intel_crtc->pipe;
548f245b 6599 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6600 u32 fp;
6601 intel_clock_t clock;
6602
6603 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6604 fp = I915_READ(FP0(pipe));
79e53945 6605 else
39adb7a5 6606 fp = I915_READ(FP1(pipe));
79e53945
JB		 6607
6608 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6609 if (IS_PINEVIEW(dev)) {
6610 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6611 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6612 } else {
6613 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6614 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6615 }
6616
a6c45cf0 6617 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6618 if (IS_PINEVIEW(dev))
6619 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6620 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6621 else
6622 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6623 DPLL_FPA01_P1_POST_DIV_SHIFT);
6624
6625 switch (dpll & DPLL_MODE_MASK) {
6626 case DPLLB_MODE_DAC_SERIAL:
6627 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6628 5 : 10;
6629 break;
6630 case DPLLB_MODE_LVDS:
6631 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6632 7 : 14;
6633 break;
6634 default:
28c97730 6635 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6636 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6637 return 0;
6638 }
6639
6640 /* XXX: Handle the 100Mhz refclk */
2177832f 6641 intel_clock(dev, 96000, &clock);
79e53945
JB		 6642 } else {
6643 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6644
6645 if (is_lvds) {
6646 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6647 DPLL_FPA01_P1_POST_DIV_SHIFT);
6648 clock.p2 = 14;
6649
6650 if ((dpll & PLL_REF_INPUT_MASK) ==
6651 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6652 /* XXX: might not be 66MHz */
2177832f 6653 intel_clock(dev, 66000, &clock);
79e53945 6654 } else
2177832f 6655 intel_clock(dev, 48000, &clock);
79e53945
JB		 6656 } else {
6657 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6658 clock.p1 = 2;
6659 else {
6660 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6661 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6662 }
6663 if (dpll & PLL_P2_DIVIDE_BY_4)
6664 clock.p2 = 4;
6665 else
6666 clock.p2 = 2;
6667
2177832f 6668 intel_clock(dev, 48000, &clock);
79e53945
JB		 6669 }
6670 }
6671
6672 /* XXX: It would be nice to validate the clocks, but we can't reuse
6673 * i830PllIsValid() because it relies on the xf86_config connector
6674 * configuration being accurate, which it isn't necessarily.
6675 */
6676
6677 return clock.dot;
6678}
6679
6680/** Returns the currently programmed mode of the given pipe. */
6681struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6682 struct drm_crtc *crtc)
6683{
548f245b 6684 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6685 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fe2b8f9d 6686 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
79e53945 6687 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6688 int htot = I915_READ(HTOTAL(cpu_transcoder));
6689 int hsync = I915_READ(HSYNC(cpu_transcoder));
6690 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6691 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6692
6693 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6694 if (!mode)
6695 return NULL;
6696
6697 mode->clock = intel_crtc_clock_get(dev, crtc);
6698 mode->hdisplay = (htot & 0xffff) + 1;
6699 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6700 mode->hsync_start = (hsync & 0xffff) + 1;
6701 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6702 mode->vdisplay = (vtot & 0xffff) + 1;
6703 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6704 mode->vsync_start = (vsync & 0xffff) + 1;
6705 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6706
6707 drm_mode_set_name(mode);
79e53945
JB		 6708
6709 return mode;
6710}
6711
3dec0095 6712static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6713{
6714 struct drm_device *dev = crtc->dev;
6715 drm_i915_private_t *dev_priv = dev->dev_private;
6716 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6717 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6718 int dpll_reg = DPLL(pipe);
6719 int dpll;
652c393a 6720
bad720ff 6721 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6722 return;
6723
6724 if (!dev_priv->lvds_downclock_avail)
6725 return;
6726
dbdc6479 6727 dpll = I915_READ(dpll_reg);
652c393a 6728 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6729 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6730
8ac5a6d5 6731 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6732
6733 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6734 I915_WRITE(dpll_reg, dpll);
9d0498a2 6735 intel_wait_for_vblank(dev, pipe);
dbdc6479 6736
652c393a
JB		 6737 dpll = I915_READ(dpll_reg);
6738 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6739 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6740 }
652c393a
JB		 6741}
6742
6743static void intel_decrease_pllclock(struct drm_crtc *crtc)
6744{
6745 struct drm_device *dev = crtc->dev;
6746 drm_i915_private_t *dev_priv = dev->dev_private;
6747 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6748
bad720ff 6749 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6750 return;
6751
6752 if (!dev_priv->lvds_downclock_avail)
6753 return;
6754
6755 /*
6756 * Since this is called by a timer, we should never get here in
6757 * the manual case.
6758 */
6759 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6760 int pipe = intel_crtc->pipe;
6761 int dpll_reg = DPLL(pipe);
6762 int dpll;
f6e5b160 6763
44d98a61 6764 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6765
8ac5a6d5 6766 assert_panel_unlocked(dev_priv, pipe);
652c393a 6767
dc257cf1 6768 dpll = I915_READ(dpll_reg);
652c393a
JB		 6769 dpll |= DISPLAY_RATE_SELECT_FPA1;
6770 I915_WRITE(dpll_reg, dpll);
9d0498a2 6771 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6772 dpll = I915_READ(dpll_reg);
6773 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6774 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6775 }
6776
6777}
6778
f047e395
CW		 6779void intel_mark_busy(struct drm_device *dev)
6780{
f047e395
CW		 6781 i915_update_gfx_val(dev->dev_private);
6782}
6783
6784void intel_mark_idle(struct drm_device *dev)
652c393a 6785{
652c393a 6786 struct drm_crtc *crtc;
652c393a
JB		 6787
6788 if (!i915_powersave)
6789 return;
6790
652c393a 6791 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6792 if (!crtc->fb)
6793 continue;
6794
725a5b54 6795 intel_decrease_pllclock(crtc);
652c393a 6796 }
652c393a
JB		 6797}
6798
725a5b54 6799void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
652c393a 6800{
f047e395
CW		 6801 struct drm_device *dev = obj->base.dev;
6802 struct drm_crtc *crtc;
652c393a 6803
f047e395 6804 if (!i915_powersave)
acb87dfb
CW		 6805 return;
6806
652c393a
JB		 6807 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6808 if (!crtc->fb)
6809 continue;
6810
f047e395 6811 if (to_intel_framebuffer(crtc->fb)->obj == obj)
725a5b54 6812 intel_increase_pllclock(crtc);
652c393a
JB		 6813 }
6814}
6815
79e53945
JB		 6816static void intel_crtc_destroy(struct drm_crtc *crtc)
6817{
6818 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6819 struct drm_device *dev = crtc->dev;
6820 struct intel_unpin_work *work;
6821 unsigned long flags;
6822
6823 spin_lock_irqsave(&dev->event_lock, flags);
6824 work = intel_crtc->unpin_work;
6825 intel_crtc->unpin_work = NULL;
6826 spin_unlock_irqrestore(&dev->event_lock, flags);
6827
6828 if (work) {
6829 cancel_work_sync(&work->work);
6830 kfree(work);
6831 }
79e53945
JB		 6832
6833 drm_crtc_cleanup(crtc);
67e77c5a 6834
79e53945
JB		 6835 kfree(intel_crtc);
6836}
6837
6b95a207
KH		 6838static void intel_unpin_work_fn(struct work_struct *__work)
6839{
6840 struct intel_unpin_work *work =
6841 container_of(__work, struct intel_unpin_work, work);
b4a98e57 6842 struct drm_device *dev = work->crtc->dev;
6b95a207 6843
b4a98e57 6844 mutex_lock(&dev->struct_mutex);
1690e1eb 6845 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 6846 drm_gem_object_unreference(&work->pending_flip_obj->base);
6847 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6848
b4a98e57
CW		 6849 intel_update_fbc(dev);
6850 mutex_unlock(&dev->struct_mutex);
6851
6852 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
6853 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
6854
6b95a207
KH		 6855 kfree(work);
6856}
6857
1afe3e9d 6858static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6859 struct drm_crtc *crtc)
6b95a207
KH		 6860{
6861 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6862 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6863 struct intel_unpin_work *work;
6b95a207
KH		 6864 unsigned long flags;
6865
6866 /* Ignore early vblank irqs */
6867 if (intel_crtc == NULL)
6868 return;
6869
6870 spin_lock_irqsave(&dev->event_lock, flags);
6871 work = intel_crtc->unpin_work;
e7d841ca
CW		 6872
6873 /* Ensure we don't miss a work->pending update ... */
6874 smp_rmb();
6875
6876 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 6877 spin_unlock_irqrestore(&dev->event_lock, flags);
6878 return;
6879 }
6880
e7d841ca
CW		 6881 /* and that the unpin work is consistent wrt ->pending. */
6882 smp_rmb();
6883
6b95a207 6884 intel_crtc->unpin_work = NULL;
6b95a207 6885
45a066eb
RC		 6886 if (work->event)
6887 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 6888
0af7e4df
MK		 6889 drm_vblank_put(dev, intel_crtc->pipe);
6890
6b95a207
KH		 6891 spin_unlock_irqrestore(&dev->event_lock, flags);
6892
2c10d571 6893 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 6894
6895 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 6896
6897 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6898}
6899
1afe3e9d
JB		 6900void intel_finish_page_flip(struct drm_device *dev, int pipe)
6901{
6902 drm_i915_private_t *dev_priv = dev->dev_private;
6903 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6904
49b14a5c 6905 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6906}
6907
6908void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6909{
6910 drm_i915_private_t *dev_priv = dev->dev_private;
6911 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6912
49b14a5c 6913 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6914}
6915
6b95a207
KH		 6916void intel_prepare_page_flip(struct drm_device *dev, int plane)
6917{
6918 drm_i915_private_t *dev_priv = dev->dev_private;
6919 struct intel_crtc *intel_crtc =
6920 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6921 unsigned long flags;
6922
e7d841ca
CW		 6923 /* NB: An MMIO update of the plane base pointer will also
6924 * generate a page-flip completion irq, i.e. every modeset
6925 * is also accompanied by a spurious intel_prepare_page_flip().
6926 */
6b95a207 6927 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 6928 if (intel_crtc->unpin_work)
6929 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 6930 spin_unlock_irqrestore(&dev->event_lock, flags);
6931}
6932
e7d841ca
CW		 6933inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
6934{
6935 /* Ensure that the work item is consistent when activating it ... */
6936 smp_wmb();
6937 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
6938 /* and that it is marked active as soon as the irq could fire. */
6939 smp_wmb();
6940}
6941
8c9f3aaf
JB		 6942static int intel_gen2_queue_flip(struct drm_device *dev,
6943 struct drm_crtc *crtc,
6944 struct drm_framebuffer *fb,
6945 struct drm_i915_gem_object *obj)
6946{
6947 struct drm_i915_private *dev_priv = dev->dev_private;
6948 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6949 u32 flip_mask;
6d90c952 6950 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6951 int ret;
6952
6d90c952 6953 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6954 if (ret)
83d4092b 6955 goto err;
8c9f3aaf 6956
6d90c952 6957 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6958 if (ret)
83d4092b 6959 goto err_unpin;
8c9f3aaf
JB		 6960
6961 /* Can't queue multiple flips, so wait for the previous
6962 * one to finish before executing the next.
6963 */
6964 if (intel_crtc->plane)
6965 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6966 else
6967 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6968 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6969 intel_ring_emit(ring, MI_NOOP);
6970 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6971 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6972 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6973 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 6974 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 6975
6976 intel_mark_page_flip_active(intel_crtc);
6d90c952 6977 intel_ring_advance(ring);
83d4092b
CW		 6978 return 0;
6979
6980err_unpin:
6981 intel_unpin_fb_obj(obj);
6982err:
8c9f3aaf
JB		 6983 return ret;
6984}
6985
6986static int intel_gen3_queue_flip(struct drm_device *dev,
6987 struct drm_crtc *crtc,
6988 struct drm_framebuffer *fb,
6989 struct drm_i915_gem_object *obj)
6990{
6991 struct drm_i915_private *dev_priv = dev->dev_private;
6992 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6993 u32 flip_mask;
6d90c952 6994 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6995 int ret;
6996
6d90c952 6997 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6998 if (ret)
83d4092b 6999 goto err;
8c9f3aaf 7000
6d90c952 7001 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7002 if (ret)
83d4092b 7003 goto err_unpin;
8c9f3aaf
JB		 7004
7005 if (intel_crtc->plane)
7006 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7007 else
7008 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7009 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7010 intel_ring_emit(ring, MI_NOOP);
7011 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7012 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7013 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7014 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7015 intel_ring_emit(ring, MI_NOOP);
7016
e7d841ca 7017 intel_mark_page_flip_active(intel_crtc);
6d90c952 7018 intel_ring_advance(ring);
83d4092b
CW		 7019 return 0;
7020
7021err_unpin:
7022 intel_unpin_fb_obj(obj);
7023err:
8c9f3aaf
JB		 7024 return ret;
7025}
7026
7027static int intel_gen4_queue_flip(struct drm_device *dev,
7028 struct drm_crtc *crtc,
7029 struct drm_framebuffer *fb,
7030 struct drm_i915_gem_object *obj)
7031{
7032 struct drm_i915_private *dev_priv = dev->dev_private;
7033 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7034 uint32_t pf, pipesrc;
6d90c952 7035 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7036 int ret;
7037
6d90c952 7038 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7039 if (ret)
83d4092b 7040 goto err;
8c9f3aaf 7041
6d90c952 7042 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7043 if (ret)
83d4092b 7044 goto err_unpin;
8c9f3aaf
JB		 7045
7046 /* i965+ uses the linear or tiled offsets from the
7047 * Display Registers (which do not change across a page-flip)
7048 * so we need only reprogram the base address.
7049 */
6d90c952
DV		 7050 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7051 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7052 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7053 intel_ring_emit(ring,
7054 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7055 obj->tiling_mode);
8c9f3aaf
JB		 7056
7057 /* XXX Enabling the panel-fitter across page-flip is so far
7058 * untested on non-native modes, so ignore it for now.
7059 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7060 */
7061 pf = 0;
7062 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7063 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7064
7065 intel_mark_page_flip_active(intel_crtc);
6d90c952 7066 intel_ring_advance(ring);
83d4092b
CW		 7067 return 0;
7068
7069err_unpin:
7070 intel_unpin_fb_obj(obj);
7071err:
8c9f3aaf
JB		 7072 return ret;
7073}
7074
7075static int intel_gen6_queue_flip(struct drm_device *dev,
7076 struct drm_crtc *crtc,
7077 struct drm_framebuffer *fb,
7078 struct drm_i915_gem_object *obj)
7079{
7080 struct drm_i915_private *dev_priv = dev->dev_private;
7081 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7082 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7083 uint32_t pf, pipesrc;
7084 int ret;
7085
6d90c952 7086 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7087 if (ret)
83d4092b 7088 goto err;
8c9f3aaf 7089
6d90c952 7090 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7091 if (ret)
83d4092b 7092 goto err_unpin;
8c9f3aaf 7093
6d90c952
DV		 7094 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7095 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7096 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7097 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7098
dc257cf1
DV		 7099 /* Contrary to the suggestions in the documentation,
7100 * "Enable Panel Fitter" does not seem to be required when page
7101 * flipping with a non-native mode, and worse causes a normal
7102 * modeset to fail.
7103 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7104 */
7105 pf = 0;
8c9f3aaf 7106 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7107 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7108
7109 intel_mark_page_flip_active(intel_crtc);
6d90c952 7110 intel_ring_advance(ring);
83d4092b
CW		 7111 return 0;
7112
7113err_unpin:
7114 intel_unpin_fb_obj(obj);
7115err:
8c9f3aaf
JB		 7116 return ret;
7117}
7118
7c9017e5
JB		 7119/*
7120 * On gen7 we currently use the blit ring because (in early silicon at least)
7121 * the render ring doesn't give us interrpts for page flip completion, which
7122 * means clients will hang after the first flip is queued. Fortunately the
7123 * blit ring generates interrupts properly, so use it instead.
7124 */
7125static int intel_gen7_queue_flip(struct drm_device *dev,
7126 struct drm_crtc *crtc,
7127 struct drm_framebuffer *fb,
7128 struct drm_i915_gem_object *obj)
7129{
7130 struct drm_i915_private *dev_priv = dev->dev_private;
7131 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7132 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7133 uint32_t plane_bit = 0;
7c9017e5
JB		 7134 int ret;
7135
7136 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7137 if (ret)
83d4092b 7138 goto err;
7c9017e5 7139
cb05d8de
DV		 7140 switch(intel_crtc->plane) {
7141 case PLANE_A:
7142 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7143 break;
7144 case PLANE_B:
7145 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7146 break;
7147 case PLANE_C:
7148 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7149 break;
7150 default:
7151 WARN_ONCE(1, "unknown plane in flip command\n");
7152 ret = -ENODEV;
ab3951eb 7153 goto err_unpin;
cb05d8de
DV		 7154 }
7155
7c9017e5
JB		 7156 ret = intel_ring_begin(ring, 4);
7157 if (ret)
83d4092b 7158 goto err_unpin;
7c9017e5 7159
cb05d8de 7160 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7161 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7162 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7163 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7164
7165 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7166 intel_ring_advance(ring);
83d4092b
CW		 7167 return 0;
7168
7169err_unpin:
7170 intel_unpin_fb_obj(obj);
7171err:
7c9017e5
JB		 7172 return ret;
7173}
7174
8c9f3aaf
JB		 7175static int intel_default_queue_flip(struct drm_device *dev,
7176 struct drm_crtc *crtc,
7177 struct drm_framebuffer *fb,
7178 struct drm_i915_gem_object *obj)
7179{
7180 return -ENODEV;
7181}
7182
6b95a207
KH		 7183static int intel_crtc_page_flip(struct drm_crtc *crtc,
7184 struct drm_framebuffer *fb,
7185 struct drm_pending_vblank_event *event)
7186{
7187 struct drm_device *dev = crtc->dev;
7188 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7189 struct drm_framebuffer *old_fb = crtc->fb;
7190 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7191 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7192 struct intel_unpin_work *work;
8c9f3aaf 7193 unsigned long flags;
52e68630 7194 int ret;
6b95a207 7195
e6a595d2
VS		 7196 /* Can't change pixel format via MI display flips. */
7197 if (fb->pixel_format != crtc->fb->pixel_format)
7198 return -EINVAL;
7199
7200 /*
7201 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7202 * Note that pitch changes could also affect these register.
7203 */
7204 if (INTEL_INFO(dev)->gen > 3 &&
7205 (fb->offsets[0] != crtc->fb->offsets[0] ||
7206 fb->pitches[0] != crtc->fb->pitches[0]))
7207 return -EINVAL;
7208
6b95a207
KH		 7209 work = kzalloc(sizeof *work, GFP_KERNEL);
7210 if (work == NULL)
7211 return -ENOMEM;
7212
6b95a207 7213 work->event = event;
b4a98e57 7214 work->crtc = crtc;
4a35f83b 7215 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7216 INIT_WORK(&work->work, intel_unpin_work_fn);
7217
7317c75e
JB		 7218 ret = drm_vblank_get(dev, intel_crtc->pipe);
7219 if (ret)
7220 goto free_work;
7221
6b95a207
KH		 7222 /* We borrow the event spin lock for protecting unpin_work */
7223 spin_lock_irqsave(&dev->event_lock, flags);
7224 if (intel_crtc->unpin_work) {
7225 spin_unlock_irqrestore(&dev->event_lock, flags);
7226 kfree(work);
7317c75e 7227 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7228
7229 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7230 return -EBUSY;
7231 }
7232 intel_crtc->unpin_work = work;
7233 spin_unlock_irqrestore(&dev->event_lock, flags);
7234
b4a98e57
CW		 7235 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7236 flush_workqueue(dev_priv->wq);
7237
79158103
CW		 7238 ret = i915_mutex_lock_interruptible(dev);
7239 if (ret)
7240 goto cleanup;
6b95a207 7241
75dfca80 7242 /* Reference the objects for the scheduled work. */
05394f39
CW		 7243 drm_gem_object_reference(&work->old_fb_obj->base);
7244 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7245
7246 crtc->fb = fb;
96b099fd 7247
e1f99ce6 7248 work->pending_flip_obj = obj;
e1f99ce6 7249
4e5359cd
SF		 7250 work->enable_stall_check = true;
7251
b4a98e57 7252 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7253 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7254
8c9f3aaf
JB		 7255 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7256 if (ret)
7257 goto cleanup_pending;
6b95a207 7258
7782de3b 7259 intel_disable_fbc(dev);
f047e395 7260 intel_mark_fb_busy(obj);
6b95a207
KH		 7261 mutex_unlock(&dev->struct_mutex);
7262
e5510fac
JB		 7263 trace_i915_flip_request(intel_crtc->plane, obj);
7264
6b95a207 7265 return 0;
96b099fd 7266
8c9f3aaf 7267cleanup_pending:
b4a98e57 7268 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7269 crtc->fb = old_fb;
05394f39
CW		 7270 drm_gem_object_unreference(&work->old_fb_obj->base);
7271 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7272 mutex_unlock(&dev->struct_mutex);
7273
79158103 7274cleanup:
96b099fd
CW		 7275 spin_lock_irqsave(&dev->event_lock, flags);
7276 intel_crtc->unpin_work = NULL;
7277 spin_unlock_irqrestore(&dev->event_lock, flags);
7278
7317c75e
JB		 7279 drm_vblank_put(dev, intel_crtc->pipe);
7280free_work:
96b099fd
CW		 7281 kfree(work);
7282
7283 return ret;
6b95a207
KH		 7284}
7285
f6e5b160 7286static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7287 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7288 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7289};
7290
6ed0f796 7291bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7292{
6ed0f796
DV		 7293 struct intel_encoder *other_encoder;
7294 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7295
6ed0f796
DV		 7296 if (WARN_ON(!crtc))
7297 return false;
7298
7299 list_for_each_entry(other_encoder,
7300 &crtc->dev->mode_config.encoder_list,
7301 base.head) {
7302
7303 if (&other_encoder->new_crtc->base != crtc ||
7304 encoder == other_encoder)
7305 continue;
7306 else
7307 return true;
f47166d2
CW		 7308 }
7309
6ed0f796
DV		 7310 return false;
7311}
47f1c6c9 7312
50f56119
DV		 7313static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7314 struct drm_crtc *crtc)
7315{
7316 struct drm_device *dev;
7317 struct drm_crtc *tmp;
7318 int crtc_mask = 1;
47f1c6c9 7319
50f56119 7320 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7321
50f56119 7322 dev = crtc->dev;
47f1c6c9 7323
50f56119
DV		 7324 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7325 if (tmp == crtc)
7326 break;
7327 crtc_mask <<= 1;
7328 }
47f1c6c9 7329
50f56119
DV		 7330 if (encoder->possible_crtcs & crtc_mask)
7331 return true;
7332 return false;
47f1c6c9 7333}
79e53945 7334
9a935856
DV		 7335/**
7336 * intel_modeset_update_staged_output_state
7337 *
7338 * Updates the staged output configuration state, e.g. after we've read out the
7339 * current hw state.
7340 */
7341static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7342{
9a935856
DV		 7343 struct intel_encoder *encoder;
7344 struct intel_connector *connector;
f6e5b160 7345
9a935856
DV		 7346 list_for_each_entry(connector, &dev->mode_config.connector_list,
7347 base.head) {
7348 connector->new_encoder =
7349 to_intel_encoder(connector->base.encoder);
7350 }
f6e5b160 7351
9a935856
DV		 7352 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7353 base.head) {
7354 encoder->new_crtc =
7355 to_intel_crtc(encoder->base.crtc);
7356 }
f6e5b160
CW		 7357}
7358
9a935856
DV		 7359/**
7360 * intel_modeset_commit_output_state
7361 *
7362 * This function copies the stage display pipe configuration to the real one.
7363 */
7364static void intel_modeset_commit_output_state(struct drm_device *dev)
7365{
7366 struct intel_encoder *encoder;
7367 struct intel_connector *connector;
f6e5b160 7368
9a935856
DV		 7369 list_for_each_entry(connector, &dev->mode_config.connector_list,
7370 base.head) {
7371 connector->base.encoder = &connector->new_encoder->base;
7372 }
f6e5b160 7373
9a935856
DV		 7374 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7375 base.head) {
7376 encoder->base.crtc = &encoder->new_crtc->base;
7377 }
7378}
7379
4e53c2e0
DV		 7380static int
7381pipe_config_set_bpp(struct drm_crtc *crtc,
7382 struct drm_framebuffer *fb,
7383 struct intel_crtc_config *pipe_config)
7384{
7385 struct drm_device *dev = crtc->dev;
7386 struct drm_connector *connector;
7387 int bpp;
7388
7389 switch (fb->depth) {
7390 case 8:
7391 bpp = 8*3; /* since we go through a colormap */
7392 break;
7393 case 15:
7394 case 16:
7395 bpp = 6*3; /* min is 18bpp */
7396 break;
7397 case 24:
7398 bpp = 8*3;
7399 break;
7400 case 30:
baba133a
DV		 7401 if (INTEL_INFO(dev)->gen < 4) {
7402 DRM_DEBUG_KMS("10 bpc not supported on gen2/3\n");
7403 return -EINVAL;
7404 }
7405
4e53c2e0
DV		 7406 bpp = 10*3;
7407 break;
baba133a 7408 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 7409 default:
7410 DRM_DEBUG_KMS("unsupported depth\n");
7411 return -EINVAL;
7412 }
7413
4e53c2e0
DV		 7414 pipe_config->pipe_bpp = bpp;
7415
7416 /* Clamp display bpp to EDID value */
7417 list_for_each_entry(connector, &dev->mode_config.connector_list,
7418 head) {
7419 if (connector->encoder && connector->encoder->crtc != crtc)
7420 continue;
7421
7422 /* Don't use an invalid EDID bpc value */
7423 if (connector->display_info.bpc &&
7424 connector->display_info.bpc * 3 < bpp) {
7425 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7426 bpp, connector->display_info.bpc*3);
7427 pipe_config->pipe_bpp = connector->display_info.bpc*3;
7428 }
7429 }
7430
7431 return bpp;
7432}
7433
b8cecdf5
DV		 7434static struct intel_crtc_config *
7435intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 7436 struct drm_framebuffer *fb,
b8cecdf5 7437 struct drm_display_mode *mode)
ee7b9f93 7438{
7758a113 7439 struct drm_device *dev = crtc->dev;
7758a113
DV		 7440 struct drm_encoder_helper_funcs *encoder_funcs;
7441 struct intel_encoder *encoder;
b8cecdf5 7442 struct intel_crtc_config *pipe_config;
4e53c2e0 7443 int plane_bpp;
ee7b9f93 7444
b8cecdf5
DV		 7445 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7446 if (!pipe_config)
7758a113
DV		 7447 return ERR_PTR(-ENOMEM);
7448
b8cecdf5
DV		 7449 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7450 drm_mode_copy(&pipe_config->requested_mode, mode);
7451
4e53c2e0
DV		 7452 plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
7453 if (plane_bpp < 0)
7454 goto fail;
7455
7758a113
DV		 7456 /* Pass our mode to the connectors and the CRTC to give them a chance to
7457 * adjust it according to limitations or connector properties, and also
7458 * a chance to reject the mode entirely.
47f1c6c9 7459 */
7758a113
DV		 7460 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7461 base.head) {
47f1c6c9 7462
7758a113
DV		 7463 if (&encoder->new_crtc->base != crtc)
7464 continue;
7ae89233
DV		 7465
7466 if (encoder->compute_config) {
7467 if (!(encoder->compute_config(encoder, pipe_config))) {
7468 DRM_DEBUG_KMS("Encoder config failure\n");
7469 goto fail;
7470 }
7471
7472 continue;
7473 }
7474
7758a113 7475 encoder_funcs = encoder->base.helper_private;
b8cecdf5
DV		 7476 if (!(encoder_funcs->mode_fixup(&encoder->base,
7477 &pipe_config->requested_mode,
7478 &pipe_config->adjusted_mode))) {
7758a113
DV		 7479 DRM_DEBUG_KMS("Encoder fixup failed\n");
7480 goto fail;
7481 }
ee7b9f93 7482 }
47f1c6c9 7483
b8cecdf5 7484 if (!(intel_crtc_compute_config(crtc, pipe_config))) {
7758a113
DV		 7485 DRM_DEBUG_KMS("CRTC fixup failed\n");
7486 goto fail;
ee7b9f93 7487 }
7758a113 7488 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
47f1c6c9 7489
4e53c2e0
DV		 7490 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7491 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7492 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7493
b8cecdf5 7494 return pipe_config;
7758a113 7495fail:
b8cecdf5 7496 kfree(pipe_config);
7758a113 7497 return ERR_PTR(-EINVAL);
ee7b9f93 7498}
47f1c6c9 7499
e2e1ed41
DV		 7500/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7501 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7502static void
7503intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7504 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7505{
7506 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7507 struct drm_device *dev = crtc->dev;
7508 struct intel_encoder *encoder;
7509 struct intel_connector *connector;
7510 struct drm_crtc *tmp_crtc;
79e53945 7511
e2e1ed41 7512 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7513
e2e1ed41
DV		 7514 /* Check which crtcs have changed outputs connected to them, these need
7515 * to be part of the prepare_pipes mask. We don't (yet) support global
7516 * modeset across multiple crtcs, so modeset_pipes will only have one
7517 * bit set at most. */
7518 list_for_each_entry(connector, &dev->mode_config.connector_list,
7519 base.head) {
7520 if (connector->base.encoder == &connector->new_encoder->base)
7521 continue;
79e53945 7522
e2e1ed41
DV		 7523 if (connector->base.encoder) {
7524 tmp_crtc = connector->base.encoder->crtc;
7525
7526 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7527 }
7528
7529 if (connector->new_encoder)
7530 *prepare_pipes |=
7531 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7532 }
7533
e2e1ed41
DV		 7534 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7535 base.head) {
7536 if (encoder->base.crtc == &encoder->new_crtc->base)
7537 continue;
7538
7539 if (encoder->base.crtc) {
7540 tmp_crtc = encoder->base.crtc;
7541
7542 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7543 }
7544
7545 if (encoder->new_crtc)
7546 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7547 }
7548
e2e1ed41
DV		 7549 /* Check for any pipes that will be fully disabled ... */
7550 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7551 base.head) {
7552 bool used = false;
22fd0fab 7553
e2e1ed41
DV		 7554 /* Don't try to disable disabled crtcs. */
7555 if (!intel_crtc->base.enabled)
7556 continue;
7e7d76c3 7557
e2e1ed41
DV		 7558 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7559 base.head) {
7560 if (encoder->new_crtc == intel_crtc)
7561 used = true;
7562 }
7563
7564 if (!used)
7565 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7566 }
7567
e2e1ed41
DV		 7568
7569 /* set_mode is also used to update properties on life display pipes. */
7570 intel_crtc = to_intel_crtc(crtc);
7571 if (crtc->enabled)
7572 *prepare_pipes |= 1 << intel_crtc->pipe;
7573
7574 /* We only support modeset on one single crtc, hence we need to do that
7575 * only for the passed in crtc iff we change anything else than just
7576 * disable crtcs.
7577 *
7578 * This is actually not true, to be fully compatible with the old crtc
7579 * helper we automatically disable _any_ output (i.e. doesn't need to be
7580 * connected to the crtc we're modesetting on) if it's disconnected.
7581 * Which is a rather nutty api (since changed the output configuration
7582 * without userspace's explicit request can lead to confusion), but
7583 * alas. Hence we currently need to modeset on all pipes we prepare. */
7584 if (*prepare_pipes)
7585 *modeset_pipes = *prepare_pipes;
7586
7587 /* ... and mask these out. */
7588 *modeset_pipes &= ~(*disable_pipes);
7589 *prepare_pipes &= ~(*disable_pipes);
47f1c6c9 7590}
79e53945 7591
ea9d758d 7592static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7593{
ea9d758d 7594 struct drm_encoder *encoder;
f6e5b160 7595 struct drm_device *dev = crtc->dev;
f6e5b160 7596
ea9d758d
DV		 7597 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7598 if (encoder->crtc == crtc)
7599 return true;
7600
7601 return false;
7602}
7603
7604static void
7605intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7606{
7607 struct intel_encoder *intel_encoder;
7608 struct intel_crtc *intel_crtc;
7609 struct drm_connector *connector;
7610
7611 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7612 base.head) {
7613 if (!intel_encoder->base.crtc)
7614 continue;
7615
7616 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7617
7618 if (prepare_pipes & (1 << intel_crtc->pipe))
7619 intel_encoder->connectors_active = false;
7620 }
7621
7622 intel_modeset_commit_output_state(dev);
7623
7624 /* Update computed state. */
7625 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7626 base.head) {
7627 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7628 }
7629
7630 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7631 if (!connector->encoder || !connector->encoder->crtc)
7632 continue;
7633
7634 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7635
7636 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7637 struct drm_property *dpms_property =
7638 dev->mode_config.dpms_property;
7639
ea9d758d 7640 connector->dpms = DRM_MODE_DPMS_ON;
662595df 7641 drm_object_property_set_value(&connector->base,
68d34720
DV		 7642 dpms_property,
7643 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7644
7645 intel_encoder = to_intel_encoder(connector->encoder);
7646 intel_encoder->connectors_active = true;
7647 }
7648 }
7649
7650}
7651
25c5b266
DV		 7652#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7653 list_for_each_entry((intel_crtc), \
7654 &(dev)->mode_config.crtc_list, \
7655 base.head) \
7656 if (mask & (1 <<(intel_crtc)->pipe)) \
7657
b980514c 7658void
8af6cf88
DV		 7659intel_modeset_check_state(struct drm_device *dev)
7660{
7661 struct intel_crtc *crtc;
7662 struct intel_encoder *encoder;
7663 struct intel_connector *connector;
7664
7665 list_for_each_entry(connector, &dev->mode_config.connector_list,
7666 base.head) {
7667 /* This also checks the encoder/connector hw state with the
7668 * ->get_hw_state callbacks. */
7669 intel_connector_check_state(connector);
7670
7671 WARN(&connector->new_encoder->base != connector->base.encoder,
7672 "connector's staged encoder doesn't match current encoder\n");
7673 }
7674
7675 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7676 base.head) {
7677 bool enabled = false;
7678 bool active = false;
7679 enum pipe pipe, tracked_pipe;
7680
7681 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7682 encoder->base.base.id,
7683 drm_get_encoder_name(&encoder->base));
7684
7685 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7686 "encoder's stage crtc doesn't match current crtc\n");
7687 WARN(encoder->connectors_active && !encoder->base.crtc,
7688 "encoder's active_connectors set, but no crtc\n");
7689
7690 list_for_each_entry(connector, &dev->mode_config.connector_list,
7691 base.head) {
7692 if (connector->base.encoder != &encoder->base)
7693 continue;
7694 enabled = true;
7695 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7696 active = true;
7697 }
7698 WARN(!!encoder->base.crtc != enabled,
7699 "encoder's enabled state mismatch "
7700 "(expected %i, found %i)\n",
7701 !!encoder->base.crtc, enabled);
7702 WARN(active && !encoder->base.crtc,
7703 "active encoder with no crtc\n");
7704
7705 WARN(encoder->connectors_active != active,
7706 "encoder's computed active state doesn't match tracked active state "
7707 "(expected %i, found %i)\n", active, encoder->connectors_active);
7708
7709 active = encoder->get_hw_state(encoder, &pipe);
7710 WARN(active != encoder->connectors_active,
7711 "encoder's hw state doesn't match sw tracking "
7712 "(expected %i, found %i)\n",
7713 encoder->connectors_active, active);
7714
7715 if (!encoder->base.crtc)
7716 continue;
7717
7718 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7719 WARN(active && pipe != tracked_pipe,
7720 "active encoder's pipe doesn't match"
7721 "(expected %i, found %i)\n",
7722 tracked_pipe, pipe);
7723
7724 }
7725
7726 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7727 base.head) {
7728 bool enabled = false;
7729 bool active = false;
7730
7731 DRM_DEBUG_KMS("[CRTC:%d]\n",
7732 crtc->base.base.id);
7733
7734 WARN(crtc->active && !crtc->base.enabled,
7735 "active crtc, but not enabled in sw tracking\n");
7736
7737 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7738 base.head) {
7739 if (encoder->base.crtc != &crtc->base)
7740 continue;
7741 enabled = true;
7742 if (encoder->connectors_active)
7743 active = true;
7744 }
7745 WARN(active != crtc->active,
7746 "crtc's computed active state doesn't match tracked active state "
7747 "(expected %i, found %i)\n", active, crtc->active);
7748 WARN(enabled != crtc->base.enabled,
7749 "crtc's computed enabled state doesn't match tracked enabled state "
7750 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7751
7752 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7753 }
7754}
7755
c0c36b94
CW		 7756int intel_set_mode(struct drm_crtc *crtc,
7757 struct drm_display_mode *mode,
7758 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 7759{
7760 struct drm_device *dev = crtc->dev;
dbf2b54e 7761 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 7762 struct drm_display_mode *saved_mode, *saved_hwmode;
7763 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 7764 struct intel_crtc *intel_crtc;
7765 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 7766 int ret = 0;
a6778b3c 7767
3ac18232 7768 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 7769 if (!saved_mode)
7770 return -ENOMEM;
3ac18232 7771 saved_hwmode = saved_mode + 1;
a6778b3c 7772
e2e1ed41 7773 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 7774 &prepare_pipes, &disable_pipes);
7775
3ac18232
TG		 7776 *saved_hwmode = crtc->hwmode;
7777 *saved_mode = crtc->mode;
a6778b3c 7778
25c5b266
DV		 7779 /* Hack: Because we don't (yet) support global modeset on multiple
7780 * crtcs, we don't keep track of the new mode for more than one crtc.
7781 * Hence simply check whether any bit is set in modeset_pipes in all the
7782 * pieces of code that are not yet converted to deal with mutliple crtcs
7783 * changing their mode at the same time. */
25c5b266 7784 if (modeset_pipes) {
4e53c2e0 7785 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 7786 if (IS_ERR(pipe_config)) {
7787 ret = PTR_ERR(pipe_config);
7788 pipe_config = NULL;
7789
3ac18232 7790 goto out;
25c5b266 7791 }
25c5b266 7792 }
a6778b3c 7793
460da916
DV		 7794 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7795 modeset_pipes, prepare_pipes, disable_pipes);
7796
7797 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7798 intel_crtc_disable(&intel_crtc->base);
7799
ea9d758d
DV		 7800 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7801 if (intel_crtc->base.enabled)
7802 dev_priv->display.crtc_disable(&intel_crtc->base);
7803 }
a6778b3c 7804
6c4c86f5
DV		 7805 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7806 * to set it here already despite that we pass it down the callchain.
f6e5b160 7807 */
b8cecdf5 7808 if (modeset_pipes) {
25c5b266 7809 crtc->mode = *mode;
b8cecdf5
DV		 7810 /* mode_set/enable/disable functions rely on a correct pipe
7811 * config. */
7812 to_intel_crtc(crtc)->config = *pipe_config;
7813 }
7758a113 7814
ea9d758d
DV		 7815 /* Only after disabling all output pipelines that will be changed can we
7816 * update the the output configuration. */
7817 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 7818
47fab737
DV		 7819 if (dev_priv->display.modeset_global_resources)
7820 dev_priv->display.modeset_global_resources(dev);
7821
a6778b3c
DV		 7822 /* Set up the DPLL and any encoders state that needs to adjust or depend
7823 * on the DPLL.
f6e5b160 7824 */
25c5b266 7825 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 7826 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 7827 x, y, fb);
7828 if (ret)
7829 goto done;
a6778b3c
DV		 7830 }
7831
7832 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 7833 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7834 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 7835
25c5b266
DV		 7836 if (modeset_pipes) {
7837 /* Store real post-adjustment hardware mode. */
b8cecdf5 7838 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 7839
25c5b266
DV		 7840 /* Calculate and store various constants which
7841 * are later needed by vblank and swap-completion
7842 * timestamping. They are derived from true hwmode.
7843 */
7844 drm_calc_timestamping_constants(crtc);
7845 }
a6778b3c
DV		 7846
7847 /* FIXME: add subpixel order */
7848done:
c0c36b94 7849 if (ret && crtc->enabled) {
3ac18232
TG		 7850 crtc->hwmode = *saved_hwmode;
7851 crtc->mode = *saved_mode;
8af6cf88
DV		 7852 } else {
7853 intel_modeset_check_state(dev);
a6778b3c
DV		 7854 }
7855
3ac18232 7856out:
b8cecdf5 7857 kfree(pipe_config);
3ac18232 7858 kfree(saved_mode);
a6778b3c 7859 return ret;
f6e5b160
CW		 7860}
7861
c0c36b94
CW		 7862void intel_crtc_restore_mode(struct drm_crtc *crtc)
7863{
7864 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
7865}
7866
25c5b266
DV		 7867#undef for_each_intel_crtc_masked
7868
d9e55608
DV		 7869static void intel_set_config_free(struct intel_set_config *config)
7870{
7871 if (!config)
7872 return;
7873
1aa4b628
DV		 7874 kfree(config->save_connector_encoders);
7875 kfree(config->save_encoder_crtcs);
d9e55608
DV		 7876 kfree(config);
7877}
7878
85f9eb71
DV		 7879static int intel_set_config_save_state(struct drm_device *dev,
7880 struct intel_set_config *config)
7881{
85f9eb71
DV		 7882 struct drm_encoder *encoder;
7883 struct drm_connector *connector;
7884 int count;
7885
1aa4b628
DV		 7886 config->save_encoder_crtcs =
7887 kcalloc(dev->mode_config.num_encoder,
7888 sizeof(struct drm_crtc *), GFP_KERNEL);
7889 if (!config->save_encoder_crtcs)
85f9eb71
DV		 7890 return -ENOMEM;
7891
1aa4b628
DV		 7892 config->save_connector_encoders =
7893 kcalloc(dev->mode_config.num_connector,
7894 sizeof(struct drm_encoder *), GFP_KERNEL);
7895 if (!config->save_connector_encoders)
85f9eb71
DV		 7896 return -ENOMEM;
7897
7898 /* Copy data. Note that driver private data is not affected.
7899 * Should anything bad happen only the expected state is
7900 * restored, not the drivers personal bookkeeping.
7901 */
85f9eb71
DV		 7902 count = 0;
7903 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 7904 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 7905 }
7906
7907 count = 0;
7908 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 7909 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 7910 }
7911
7912 return 0;
7913}
7914
7915static void intel_set_config_restore_state(struct drm_device *dev,
7916 struct intel_set_config *config)
7917{
9a935856
DV		 7918 struct intel_encoder *encoder;
7919 struct intel_connector *connector;
85f9eb71
DV		 7920 int count;
7921
85f9eb71 7922 count = 0;
9a935856
DV		 7923 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7924 encoder->new_crtc =
7925 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 7926 }
7927
7928 count = 0;
9a935856
DV		 7929 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7930 connector->new_encoder =
7931 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 7932 }
7933}
7934
5e2b584e
DV		 7935static void
7936intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7937 struct intel_set_config *config)
7938{
7939
7940 /* We should be able to check here if the fb has the same properties
7941 * and then just flip_or_move it */
7942 if (set->crtc->fb != set->fb) {
7943 /* If we have no fb then treat it as a full mode set */
7944 if (set->crtc->fb == NULL) {
7945 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7946 config->mode_changed = true;
7947 } else if (set->fb == NULL) {
7948 config->mode_changed = true;
7949 } else if (set->fb->depth != set->crtc->fb->depth) {
7950 config->mode_changed = true;
7951 } else if (set->fb->bits_per_pixel !=
7952 set->crtc->fb->bits_per_pixel) {
7953 config->mode_changed = true;
7954 } else
7955 config->fb_changed = true;
7956 }
7957
835c5873 7958 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 7959 config->fb_changed = true;
7960
7961 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7962 DRM_DEBUG_KMS("modes are different, full mode set\n");
7963 drm_mode_debug_printmodeline(&set->crtc->mode);
7964 drm_mode_debug_printmodeline(set->mode);
7965 config->mode_changed = true;
7966 }
7967}
7968
2e431051 7969static int
9a935856
DV		 7970intel_modeset_stage_output_state(struct drm_device *dev,
7971 struct drm_mode_set *set,
7972 struct intel_set_config *config)
50f56119 7973{
85f9eb71 7974 struct drm_crtc *new_crtc;
9a935856
DV		 7975 struct intel_connector *connector;
7976 struct intel_encoder *encoder;
2e431051 7977 int count, ro;
50f56119 7978
9abdda74 7979 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 7980 * of connectors. For paranoia, double-check this. */
7981 WARN_ON(!set->fb && (set->num_connectors != 0));
7982 WARN_ON(set->fb && (set->num_connectors == 0));
7983
50f56119 7984 count = 0;
9a935856
DV		 7985 list_for_each_entry(connector, &dev->mode_config.connector_list,
7986 base.head) {
7987 /* Otherwise traverse passed in connector list and get encoders
7988 * for them. */
50f56119 7989 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 7990 if (set->connectors[ro] == &connector->base) {
7991 connector->new_encoder = connector->encoder;
50f56119
DV		 7992 break;
7993 }
7994 }
7995
9a935856
DV		 7996 /* If we disable the crtc, disable all its connectors. Also, if
7997 * the connector is on the changing crtc but not on the new
7998 * connector list, disable it. */
7999 if ((!set->fb || ro == set->num_connectors) &&
8000 connector->base.encoder &&
8001 connector->base.encoder->crtc == set->crtc) {
8002 connector->new_encoder = NULL;
8003
8004 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8005 connector->base.base.id,
8006 drm_get_connector_name(&connector->base));
8007 }
8008
8009
8010 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8011 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8012 config->mode_changed = true;
50f56119
DV		 8013 }
8014 }
9a935856 8015 /* connector->new_encoder is now updated for all connectors. */
50f56119 8016
9a935856 8017 /* Update crtc of enabled connectors. */
50f56119 8018 count = 0;
9a935856
DV		 8019 list_for_each_entry(connector, &dev->mode_config.connector_list,
8020 base.head) {
8021 if (!connector->new_encoder)
50f56119
DV		 8022 continue;
8023
9a935856 8024 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8025
8026 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8027 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8028 new_crtc = set->crtc;
8029 }
8030
8031 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8032 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8033 new_crtc)) {
5e2b584e 8034 return -EINVAL;
50f56119 8035 }
9a935856
DV		 8036 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8037
8038 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8039 connector->base.base.id,
8040 drm_get_connector_name(&connector->base),
8041 new_crtc->base.id);
8042 }
8043
8044 /* Check for any encoders that needs to be disabled. */
8045 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8046 base.head) {
8047 list_for_each_entry(connector,
8048 &dev->mode_config.connector_list,
8049 base.head) {
8050 if (connector->new_encoder == encoder) {
8051 WARN_ON(!connector->new_encoder->new_crtc);
8052
8053 goto next_encoder;
8054 }
8055 }
8056 encoder->new_crtc = NULL;
8057next_encoder:
8058 /* Only now check for crtc changes so we don't miss encoders
8059 * that will be disabled. */
8060 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8061 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8062 config->mode_changed = true;
50f56119
DV		 8063 }
8064 }
9a935856 8065 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8066
2e431051
DV		 8067 return 0;
8068}
8069
8070static int intel_crtc_set_config(struct drm_mode_set *set)
8071{
8072 struct drm_device *dev;
2e431051
DV		 8073 struct drm_mode_set save_set;
8074 struct intel_set_config *config;
8075 int ret;
2e431051 8076
8d3e375e
DV		 8077 BUG_ON(!set);
8078 BUG_ON(!set->crtc);
8079 BUG_ON(!set->crtc->helper_private);
2e431051 8080
7e53f3a4
DV		 8081 /* Enforce sane interface api - has been abused by the fb helper. */
8082 BUG_ON(!set->mode && set->fb);
8083 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 8084
2e431051
DV		 8085 if (set->fb) {
8086 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8087 set->crtc->base.id, set->fb->base.id,
8088 (int)set->num_connectors, set->x, set->y);
8089 } else {
8090 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8091 }
8092
8093 dev = set->crtc->dev;
8094
8095 ret = -ENOMEM;
8096 config = kzalloc(sizeof(*config), GFP_KERNEL);
8097 if (!config)
8098 goto out_config;
8099
8100 ret = intel_set_config_save_state(dev, config);
8101 if (ret)
8102 goto out_config;
8103
8104 save_set.crtc = set->crtc;
8105 save_set.mode = &set->crtc->mode;
8106 save_set.x = set->crtc->x;
8107 save_set.y = set->crtc->y;
8108 save_set.fb = set->crtc->fb;
8109
8110 /* Compute whether we need a full modeset, only an fb base update or no
8111 * change at all. In the future we might also check whether only the
8112 * mode changed, e.g. for LVDS where we only change the panel fitter in
8113 * such cases. */
8114 intel_set_config_compute_mode_changes(set, config);
8115
9a935856 8116 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8117 if (ret)
8118 goto fail;
8119
5e2b584e 8120 if (config->mode_changed) {
87f1faa6 8121 if (set->mode) {
50f56119
DV		 8122 DRM_DEBUG_KMS("attempting to set mode from"
8123 " userspace\n");
8124 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 8125 }
8126
c0c36b94
CW		 8127 ret = intel_set_mode(set->crtc, set->mode,
8128 set->x, set->y, set->fb);
8129 if (ret) {
8130 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8131 set->crtc->base.id, ret);
87f1faa6
DV		 8132 goto fail;
8133 }
5e2b584e 8134 } else if (config->fb_changed) {
4878cae2
VS		 8135 intel_crtc_wait_for_pending_flips(set->crtc);
8136
4f660f49 8137 ret = intel_pipe_set_base(set->crtc,
94352cf9 8138 set->x, set->y, set->fb);
50f56119
DV		 8139 }
8140
d9e55608
DV		 8141 intel_set_config_free(config);
8142
50f56119
DV		 8143 return 0;
8144
8145fail:
85f9eb71 8146 intel_set_config_restore_state(dev, config);
50f56119
DV		 8147
8148 /* Try to restore the config */
5e2b584e 8149 if (config->mode_changed &&
c0c36b94
CW		 8150 intel_set_mode(save_set.crtc, save_set.mode,
8151 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8152 DRM_ERROR("failed to restore config after modeset failure\n");
8153
d9e55608
DV		 8154out_config:
8155 intel_set_config_free(config);
50f56119
DV		 8156 return ret;
8157}
f6e5b160
CW		 8158
8159static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8160 .cursor_set = intel_crtc_cursor_set,
8161 .cursor_move = intel_crtc_cursor_move,
8162 .gamma_set = intel_crtc_gamma_set,
50f56119 8163 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8164 .destroy = intel_crtc_destroy,
8165 .page_flip = intel_crtc_page_flip,
8166};
8167
79f689aa
PZ		 8168static void intel_cpu_pll_init(struct drm_device *dev)
8169{
affa9354 8170 if (HAS_DDI(dev))
79f689aa
PZ		 8171 intel_ddi_pll_init(dev);
8172}
8173
ee7b9f93
JB		 8174static void intel_pch_pll_init(struct drm_device *dev)
8175{
8176 drm_i915_private_t *dev_priv = dev->dev_private;
8177 int i;
8178
8179 if (dev_priv->num_pch_pll == 0) {
8180 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8181 return;
8182 }
8183
8184 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8185 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8186 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8187 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8188 }
8189}
8190
b358d0a6 8191static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8192{
22fd0fab 8193 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8194 struct intel_crtc *intel_crtc;
8195 int i;
8196
8197 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8198 if (intel_crtc == NULL)
8199 return;
8200
8201 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8202
8203 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8204 for (i = 0; i < 256; i++) {
8205 intel_crtc->lut_r[i] = i;
8206 intel_crtc->lut_g[i] = i;
8207 intel_crtc->lut_b[i] = i;
8208 }
8209
80824003
JB		 8210 /* Swap pipes & planes for FBC on pre-965 */
8211 intel_crtc->pipe = pipe;
8212 intel_crtc->plane = pipe;
a5c961d1 8213 intel_crtc->cpu_transcoder = pipe;
e2e767ab 8214 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8215 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8216 intel_crtc->plane = !pipe;
80824003
JB		 8217 }
8218
22fd0fab
JB		 8219 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8220 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8221 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8222 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8223
79e53945 8224 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8225}
8226
08d7b3d1 8227int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8228 struct drm_file *file)
08d7b3d1 8229{
08d7b3d1 8230 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8231 struct drm_mode_object *drmmode_obj;
8232 struct intel_crtc *crtc;
08d7b3d1 8233
1cff8f6b
DV		 8234 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8235 return -ENODEV;
08d7b3d1 8236
c05422d5
DV		 8237 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8238 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8239
c05422d5 8240 if (!drmmode_obj) {
08d7b3d1
CW		 8241 DRM_ERROR("no such CRTC id\n");
8242 return -EINVAL;
8243 }
8244
c05422d5
DV		 8245 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8246 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8247
c05422d5 8248 return 0;
08d7b3d1
CW		 8249}
8250
66a9278e 8251static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8252{
66a9278e
DV		 8253 struct drm_device *dev = encoder->base.dev;
8254 struct intel_encoder *source_encoder;
79e53945 8255 int index_mask = 0;
79e53945
JB		 8256 int entry = 0;
8257
66a9278e
DV		 8258 list_for_each_entry(source_encoder,
8259 &dev->mode_config.encoder_list, base.head) {
8260
8261 if (encoder == source_encoder)
79e53945 8262 index_mask |= (1 << entry);
66a9278e
DV		 8263
8264 /* Intel hw has only one MUX where enocoders could be cloned. */
8265 if (encoder->cloneable && source_encoder->cloneable)
8266 index_mask |= (1 << entry);
8267
79e53945
JB		 8268 entry++;
8269 }
4ef69c7a 8270
79e53945
JB		 8271 return index_mask;
8272}
8273
4d302442
CW		 8274static bool has_edp_a(struct drm_device *dev)
8275{
8276 struct drm_i915_private *dev_priv = dev->dev_private;
8277
8278 if (!IS_MOBILE(dev))
8279 return false;
8280
8281 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8282 return false;
8283
8284 if (IS_GEN5(dev) &&
8285 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8286 return false;
8287
8288 return true;
8289}
8290
79e53945
JB		 8291static void intel_setup_outputs(struct drm_device *dev)
8292{
725e30ad 8293 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8294 struct intel_encoder *encoder;
cb0953d7 8295 bool dpd_is_edp = false;
f3cfcba6 8296 bool has_lvds;
79e53945 8297
f3cfcba6 8298 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8299 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8300 /* disable the panel fitter on everything but LVDS */
8301 I915_WRITE(PFIT_CONTROL, 0);
8302 }
79e53945 8303
affa9354 8304 if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
79935fca 8305 intel_crt_init(dev);
cb0953d7 8306
affa9354 8307 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8308 int found;
8309
8310 /* Haswell uses DDI functions to detect digital outputs */
8311 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8312 /* DDI A only supports eDP */
8313 if (found)
8314 intel_ddi_init(dev, PORT_A);
8315
8316 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8317 * register */
8318 found = I915_READ(SFUSE_STRAP);
8319
8320 if (found & SFUSE_STRAP_DDIB_DETECTED)
8321 intel_ddi_init(dev, PORT_B);
8322 if (found & SFUSE_STRAP_DDIC_DETECTED)
8323 intel_ddi_init(dev, PORT_C);
8324 if (found & SFUSE_STRAP_DDID_DETECTED)
8325 intel_ddi_init(dev, PORT_D);
8326 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8327 int found;
270b3042
DV		 8328 dpd_is_edp = intel_dpd_is_edp(dev);
8329
8330 if (has_edp_a(dev))
8331 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8332
dc0fa718 8333 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 8334 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8335 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8336 if (!found)
e2debe91 8337 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 8338 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8339 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8340 }
8341
dc0fa718 8342 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 8343 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 8344
dc0fa718 8345 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 8346 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 8347
5eb08b69 8348 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8349 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8350
270b3042 8351 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8352 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 8353 } else if (IS_VALLEYVIEW(dev)) {
19c03924 8354 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 8355 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8356 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 8357
dc0fa718 8358 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 8359 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8360 PORT_B);
67cfc203
VS		 8361 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8362 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 8363 }
103a196f 8364 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8365 bool found = false;
7d57382e 8366
e2debe91 8367 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8368 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 8369 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 8370 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8371 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 8372 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 8373 }
27185ae1 8374
b01f2c3a
JB		 8375 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8376 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 8377 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 8378 }
725e30ad 8379 }
13520b05
KH		 8380
8381 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8382
e2debe91 8383 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8384 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 8385 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 8386 }
27185ae1 8387
e2debe91 8388 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 8389
b01f2c3a
JB		 8390 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8391 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 8392 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a
JB		 8393 }
8394 if (SUPPORTS_INTEGRATED_DP(dev)) {
8395 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 8396 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 8397 }
725e30ad 8398 }
27185ae1 8399
b01f2c3a
JB		 8400 if (SUPPORTS_INTEGRATED_DP(dev) &&
8401 (I915_READ(DP_D) & DP_DETECTED)) {
8402 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 8403 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 8404 }
bad720ff 8405 } else if (IS_GEN2(dev))
79e53945
JB		 8406 intel_dvo_init(dev);
8407
103a196f 8408 if (SUPPORTS_TV(dev))
79e53945
JB		 8409 intel_tv_init(dev);
8410
4ef69c7a
CW		 8411 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8412 encoder->base.possible_crtcs = encoder->crtc_mask;
8413 encoder->base.possible_clones =
66a9278e 8414 intel_encoder_clones(encoder);
79e53945 8415 }
47356eb6 8416
dde86e2d 8417 intel_init_pch_refclk(dev);
270b3042
DV		 8418
8419 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8420}
8421
8422static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8423{
8424 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8425
8426 drm_framebuffer_cleanup(fb);
05394f39 8427 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8428
8429 kfree(intel_fb);
8430}
8431
8432static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8433 struct drm_file *file,
79e53945
JB		 8434 unsigned int *handle)
8435{
8436 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8437 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8438
05394f39 8439 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8440}
8441
8442static const struct drm_framebuffer_funcs intel_fb_funcs = {
8443 .destroy = intel_user_framebuffer_destroy,
8444 .create_handle = intel_user_framebuffer_create_handle,
8445};
8446
38651674
DA		 8447int intel_framebuffer_init(struct drm_device *dev,
8448 struct intel_framebuffer *intel_fb,
308e5bcb 8449 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8450 struct drm_i915_gem_object *obj)
79e53945 8451{
79e53945
JB		 8452 int ret;
8453
c16ed4be
CW		 8454 if (obj->tiling_mode == I915_TILING_Y) {
8455 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 8456 return -EINVAL;
c16ed4be 8457 }
57cd6508 8458
c16ed4be
CW		 8459 if (mode_cmd->pitches[0] & 63) {
8460 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8461 mode_cmd->pitches[0]);
57cd6508 8462 return -EINVAL;
c16ed4be 8463 }
57cd6508 8464
5d7bd705 8465 /* FIXME <= Gen4 stride limits are bit unclear */
c16ed4be
CW		 8466 if (mode_cmd->pitches[0] > 32768) {
8467 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8468 mode_cmd->pitches[0]);
5d7bd705 8469 return -EINVAL;
c16ed4be 8470 }
5d7bd705
VS		 8471
8472 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 8473 mode_cmd->pitches[0] != obj->stride) {
8474 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8475 mode_cmd->pitches[0], obj->stride);
5d7bd705 8476 return -EINVAL;
c16ed4be 8477 }
5d7bd705 8478
57779d06 8479 /* Reject formats not supported by any plane early. */
308e5bcb 8480 switch (mode_cmd->pixel_format) {
57779d06 8481 case DRM_FORMAT_C8:
04b3924d
VS		 8482 case DRM_FORMAT_RGB565:
8483 case DRM_FORMAT_XRGB8888:
8484 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8485 break;
8486 case DRM_FORMAT_XRGB1555:
8487 case DRM_FORMAT_ARGB1555:
c16ed4be
CW		 8488 if (INTEL_INFO(dev)->gen > 3) {
8489 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8490 return -EINVAL;
c16ed4be 8491 }
57779d06
VS		 8492 break;
8493 case DRM_FORMAT_XBGR8888:
8494 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8495 case DRM_FORMAT_XRGB2101010:
8496 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8497 case DRM_FORMAT_XBGR2101010:
8498 case DRM_FORMAT_ABGR2101010:
c16ed4be
CW		 8499 if (INTEL_INFO(dev)->gen < 4) {
8500 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8501 return -EINVAL;
c16ed4be 8502 }
b5626747 8503 break;
04b3924d
VS		 8504 case DRM_FORMAT_YUYV:
8505 case DRM_FORMAT_UYVY:
8506 case DRM_FORMAT_YVYU:
8507 case DRM_FORMAT_VYUY:
c16ed4be
CW		 8508 if (INTEL_INFO(dev)->gen < 5) {
8509 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8510 return -EINVAL;
c16ed4be 8511 }
57cd6508
CW		 8512 break;
8513 default:
c16ed4be 8514 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8515 return -EINVAL;
8516 }
8517
90f9a336
VS		 8518 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8519 if (mode_cmd->offsets[0] != 0)
8520 return -EINVAL;
8521
c7d73f6a
DV		 8522 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8523 intel_fb->obj = obj;
8524
79e53945
JB		 8525 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8526 if (ret) {
8527 DRM_ERROR("framebuffer init failed %d\n", ret);
8528 return ret;
8529 }
8530
79e53945
JB		 8531 return 0;
8532}
8533
79e53945
JB		 8534static struct drm_framebuffer *
8535intel_user_framebuffer_create(struct drm_device *dev,
8536 struct drm_file *filp,
308e5bcb 8537 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8538{
05394f39 8539 struct drm_i915_gem_object *obj;
79e53945 8540
308e5bcb
JB		 8541 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8542 mode_cmd->handles[0]));
c8725226 8543 if (&obj->base == NULL)
cce13ff7 8544 return ERR_PTR(-ENOENT);
79e53945 8545
d2dff872 8546 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8547}
8548
79e53945 8549static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8550 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8551 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8552};
8553
e70236a8
JB		 8554/* Set up chip specific display functions */
8555static void intel_init_display(struct drm_device *dev)
8556{
8557 struct drm_i915_private *dev_priv = dev->dev_private;
8558
affa9354 8559 if (HAS_DDI(dev)) {
09b4ddf9 8560 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8561 dev_priv->display.crtc_enable = haswell_crtc_enable;
8562 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 8563 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 8564 dev_priv->display.update_plane = ironlake_update_plane;
8565 } else if (HAS_PCH_SPLIT(dev)) {
f564048e 8566 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 8567 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8568 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8569 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8570 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8571 } else {
f564048e 8572 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 8573 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8574 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8575 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8576 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8577 }
e70236a8 8578
e70236a8 8579 /* Returns the core display clock speed */
25eb05fc
JB		 8580 if (IS_VALLEYVIEW(dev))
8581 dev_priv->display.get_display_clock_speed =
8582 valleyview_get_display_clock_speed;
8583 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8584 dev_priv->display.get_display_clock_speed =
8585 i945_get_display_clock_speed;
8586 else if (IS_I915G(dev))
8587 dev_priv->display.get_display_clock_speed =
8588 i915_get_display_clock_speed;
f2b115e6 8589 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8590 dev_priv->display.get_display_clock_speed =
8591 i9xx_misc_get_display_clock_speed;
8592 else if (IS_I915GM(dev))
8593 dev_priv->display.get_display_clock_speed =
8594 i915gm_get_display_clock_speed;
8595 else if (IS_I865G(dev))
8596 dev_priv->display.get_display_clock_speed =
8597 i865_get_display_clock_speed;
f0f8a9ce 8598 else if (IS_I85X(dev))
e70236a8
JB		 8599 dev_priv->display.get_display_clock_speed =
8600 i855_get_display_clock_speed;
8601 else /* 852, 830 */
8602 dev_priv->display.get_display_clock_speed =
8603 i830_get_display_clock_speed;
8604
7f8a8569 8605 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8606 if (IS_GEN5(dev)) {
674cf967 8607 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8608 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8609 } else if (IS_GEN6(dev)) {
674cf967 8610 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8611 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8612 } else if (IS_IVYBRIDGE(dev)) {
8613 /* FIXME: detect B0+ stepping and use auto training */
8614 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 8615 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 8616 dev_priv->display.modeset_global_resources =
8617 ivb_modeset_global_resources;
c82e4d26
ED		 8618 } else if (IS_HASWELL(dev)) {
8619 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 8620 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 8621 dev_priv->display.modeset_global_resources =
8622 haswell_modeset_global_resources;
a0e63c22 8623 }
6067aaea 8624 } else if (IS_G4X(dev)) {
e0dac65e 8625 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8626 }
8c9f3aaf
JB		 8627
8628 /* Default just returns -ENODEV to indicate unsupported */
8629 dev_priv->display.queue_flip = intel_default_queue_flip;
8630
8631 switch (INTEL_INFO(dev)->gen) {
8632 case 2:
8633 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8634 break;
8635
8636 case 3:
8637 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8638 break;
8639
8640 case 4:
8641 case 5:
8642 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8643 break;
8644
8645 case 6:
8646 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8647 break;
7c9017e5
JB		 8648 case 7:
8649 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8650 break;
8c9f3aaf 8651 }
e70236a8
JB		 8652}
8653
b690e96c
JB		 8654/*
8655 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8656 * resume, or other times. This quirk makes sure that's the case for
8657 * affected systems.
8658 */
0206e353 8659static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8660{
8661 struct drm_i915_private *dev_priv = dev->dev_private;
8662
8663 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 8664 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 8665}
8666
435793df
KP		 8667/*
8668 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8669 */
8670static void quirk_ssc_force_disable(struct drm_device *dev)
8671{
8672 struct drm_i915_private *dev_priv = dev->dev_private;
8673 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 8674 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 8675}
8676
4dca20ef 8677/*
5a15ab5b
CE		 8678 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8679 * brightness value
4dca20ef
CE		 8680 */
8681static void quirk_invert_brightness(struct drm_device *dev)
8682{
8683 struct drm_i915_private *dev_priv = dev->dev_private;
8684 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 8685 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 8686}
8687
b690e96c
JB		 8688struct intel_quirk {
8689 int device;
8690 int subsystem_vendor;
8691 int subsystem_device;
8692 void (*hook)(struct drm_device *dev);
8693};
8694
5f85f176
EE		 8695/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8696struct intel_dmi_quirk {
8697 void (*hook)(struct drm_device *dev);
8698 const struct dmi_system_id (*dmi_id_list)[];
8699};
8700
8701static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8702{
8703 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8704 return 1;
8705}
8706
8707static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8708 {
8709 .dmi_id_list = &(const struct dmi_system_id[]) {
8710 {
8711 .callback = intel_dmi_reverse_brightness,
8712 .ident = "NCR Corporation",
8713 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8714 DMI_MATCH(DMI_PRODUCT_NAME, ""),
8715 },
8716 },
8717 { } /* terminating entry */
8718 },
8719 .hook = quirk_invert_brightness,
8720 },
8721};
8722
c43b5634 8723static struct intel_quirk intel_quirks[] = {
b690e96c 8724 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8725 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 8726
b690e96c
JB		 8727 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8728 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8729
b690e96c
JB		 8730 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8731 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8732
ccd0d36e 8733 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 8734 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 8735 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 8736
8737 /* Lenovo U160 cannot use SSC on LVDS */
8738 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 8739
8740 /* Sony Vaio Y cannot use SSC on LVDS */
8741 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 8742
8743 /* Acer Aspire 5734Z must invert backlight brightness */
8744 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 8745
8746 /* Acer/eMachines G725 */
8747 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 8748
8749 /* Acer/eMachines e725 */
8750 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 8751
8752 /* Acer/Packard Bell NCL20 */
8753 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 8754
8755 /* Acer Aspire 4736Z */
8756 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 8757};
8758
8759static void intel_init_quirks(struct drm_device *dev)
8760{
8761 struct pci_dev *d = dev->pdev;
8762 int i;
8763
8764 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8765 struct intel_quirk *q = &intel_quirks[i];
8766
8767 if (d->device == q->device &&
8768 (d->subsystem_vendor == q->subsystem_vendor ||
8769 q->subsystem_vendor == PCI_ANY_ID) &&
8770 (d->subsystem_device == q->subsystem_device ||
8771 q->subsystem_device == PCI_ANY_ID))
8772 q->hook(dev);
8773 }
5f85f176
EE		 8774 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8775 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8776 intel_dmi_quirks[i].hook(dev);
8777 }
b690e96c
JB		 8778}
8779
9cce37f4
JB		 8780/* Disable the VGA plane that we never use */
8781static void i915_disable_vga(struct drm_device *dev)
8782{
8783 struct drm_i915_private *dev_priv = dev->dev_private;
8784 u8 sr1;
766aa1c4 8785 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 8786
8787 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 8788 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 8789 sr1 = inb(VGA_SR_DATA);
8790 outb(sr1 | 1<<5, VGA_SR_DATA);
8791 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8792 udelay(300);
8793
8794 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8795 POSTING_READ(vga_reg);
8796}
8797
f817586c
DV		 8798void intel_modeset_init_hw(struct drm_device *dev)
8799{
fa42e23c 8800 intel_init_power_well(dev);
0232e927 8801
a8f78b58
ED		 8802 intel_prepare_ddi(dev);
8803
f817586c
DV		 8804 intel_init_clock_gating(dev);
8805
79f5b2c7 8806 mutex_lock(&dev->struct_mutex);
8090c6b9 8807 intel_enable_gt_powersave(dev);
79f5b2c7 8808 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 8809}
8810
79e53945
JB		 8811void intel_modeset_init(struct drm_device *dev)
8812{
652c393a 8813 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 8814 int i, ret;
79e53945
JB		 8815
8816 drm_mode_config_init(dev);
8817
8818 dev->mode_config.min_width = 0;
8819 dev->mode_config.min_height = 0;
8820
019d96cb
DA		 8821 dev->mode_config.preferred_depth = 24;
8822 dev->mode_config.prefer_shadow = 1;
8823
e6ecefaa 8824 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 8825
b690e96c
JB		 8826 intel_init_quirks(dev);
8827
1fa61106
ED		 8828 intel_init_pm(dev);
8829
e70236a8
JB		 8830 intel_init_display(dev);
8831
a6c45cf0
CW		 8832 if (IS_GEN2(dev)) {
8833 dev->mode_config.max_width = 2048;
8834 dev->mode_config.max_height = 2048;
8835 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 8836 dev->mode_config.max_width = 4096;
8837 dev->mode_config.max_height = 4096;
79e53945 8838 } else {
a6c45cf0
CW		 8839 dev->mode_config.max_width = 8192;
8840 dev->mode_config.max_height = 8192;
79e53945 8841 }
5d4545ae 8842 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 8843
28c97730 8844 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 8845 INTEL_INFO(dev)->num_pipes,
8846 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 8847
7eb552ae 8848 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
79e53945 8849 intel_crtc_init(dev, i);
00c2064b
JB		 8850 ret = intel_plane_init(dev, i);
8851 if (ret)
8852 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 8853 }
8854
79f689aa 8855 intel_cpu_pll_init(dev);
ee7b9f93
JB		 8856 intel_pch_pll_init(dev);
8857
9cce37f4
JB		 8858 /* Just disable it once at startup */
8859 i915_disable_vga(dev);
79e53945 8860 intel_setup_outputs(dev);
11be49eb
CW		 8861
8862 /* Just in case the BIOS is doing something questionable. */
8863 intel_disable_fbc(dev);
2c7111db
CW		 8864}
8865
24929352
DV		 8866static void
8867intel_connector_break_all_links(struct intel_connector *connector)
8868{
8869 connector->base.dpms = DRM_MODE_DPMS_OFF;
8870 connector->base.encoder = NULL;
8871 connector->encoder->connectors_active = false;
8872 connector->encoder->base.crtc = NULL;
8873}
8874
7fad798e
DV		 8875static void intel_enable_pipe_a(struct drm_device *dev)
8876{
8877 struct intel_connector *connector;
8878 struct drm_connector *crt = NULL;
8879 struct intel_load_detect_pipe load_detect_temp;
8880
8881 /* We can't just switch on the pipe A, we need to set things up with a
8882 * proper mode and output configuration. As a gross hack, enable pipe A
8883 * by enabling the load detect pipe once. */
8884 list_for_each_entry(connector,
8885 &dev->mode_config.connector_list,
8886 base.head) {
8887 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8888 crt = &connector->base;
8889 break;
8890 }
8891 }
8892
8893 if (!crt)
8894 return;
8895
8896 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8897 intel_release_load_detect_pipe(crt, &load_detect_temp);
8898
652c393a 8899
7fad798e
DV		 8900}
8901
fa555837
DV		 8902static bool
8903intel_check_plane_mapping(struct intel_crtc *crtc)
8904{
7eb552ae
BW		 8905 struct drm_device *dev = crtc->base.dev;
8906 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 8907 u32 reg, val;
8908
7eb552ae 8909 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 8910 return true;
8911
8912 reg = DSPCNTR(!crtc->plane);
8913 val = I915_READ(reg);
8914
8915 if ((val & DISPLAY_PLANE_ENABLE) &&
8916 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8917 return false;
8918
8919 return true;
8920}
8921
24929352
DV		 8922static void intel_sanitize_crtc(struct intel_crtc *crtc)
8923{
8924 struct drm_device *dev = crtc->base.dev;
8925 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 8926 u32 reg;
24929352 8927
24929352 8928 /* Clear any frame start delays used for debugging left by the BIOS */
702e7a56 8929 reg = PIPECONF(crtc->cpu_transcoder);
24929352
DV		 8930 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8931
8932 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 8933 * disable the crtc (and hence change the state) if it is wrong. Note
8934 * that gen4+ has a fixed plane -> pipe mapping. */
8935 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 8936 struct intel_connector *connector;
8937 bool plane;
8938
24929352
DV		 8939 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8940 crtc->base.base.id);
8941
8942 /* Pipe has the wrong plane attached and the plane is active.
8943 * Temporarily change the plane mapping and disable everything
8944 * ... */
8945 plane = crtc->plane;
8946 crtc->plane = !plane;
8947 dev_priv->display.crtc_disable(&crtc->base);
8948 crtc->plane = plane;
8949
8950 /* ... and break all links. */
8951 list_for_each_entry(connector, &dev->mode_config.connector_list,
8952 base.head) {
8953 if (connector->encoder->base.crtc != &crtc->base)
8954 continue;
8955
8956 intel_connector_break_all_links(connector);
8957 }
8958
8959 WARN_ON(crtc->active);
8960 crtc->base.enabled = false;
8961 }
24929352 8962
7fad798e
DV		 8963 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8964 crtc->pipe == PIPE_A && !crtc->active) {
8965 /* BIOS forgot to enable pipe A, this mostly happens after
8966 * resume. Force-enable the pipe to fix this, the update_dpms
8967 * call below we restore the pipe to the right state, but leave
8968 * the required bits on. */
8969 intel_enable_pipe_a(dev);
8970 }
8971
24929352
DV		 8972 /* Adjust the state of the output pipe according to whether we
8973 * have active connectors/encoders. */
8974 intel_crtc_update_dpms(&crtc->base);
8975
8976 if (crtc->active != crtc->base.enabled) {
8977 struct intel_encoder *encoder;
8978
8979 /* This can happen either due to bugs in the get_hw_state
8980 * functions or because the pipe is force-enabled due to the
8981 * pipe A quirk. */
8982 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8983 crtc->base.base.id,
8984 crtc->base.enabled ? "enabled" : "disabled",
8985 crtc->active ? "enabled" : "disabled");
8986
8987 crtc->base.enabled = crtc->active;
8988
8989 /* Because we only establish the connector -> encoder ->
8990 * crtc links if something is active, this means the
8991 * crtc is now deactivated. Break the links. connector
8992 * -> encoder links are only establish when things are
8993 * actually up, hence no need to break them. */
8994 WARN_ON(crtc->active);
8995
8996 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8997 WARN_ON(encoder->connectors_active);
8998 encoder->base.crtc = NULL;
8999 }
9000 }
9001}
9002
9003static void intel_sanitize_encoder(struct intel_encoder *encoder)
9004{
9005 struct intel_connector *connector;
9006 struct drm_device *dev = encoder->base.dev;
9007
9008 /* We need to check both for a crtc link (meaning that the
9009 * encoder is active and trying to read from a pipe) and the
9010 * pipe itself being active. */
9011 bool has_active_crtc = encoder->base.crtc &&
9012 to_intel_crtc(encoder->base.crtc)->active;
9013
9014 if (encoder->connectors_active && !has_active_crtc) {
9015 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9016 encoder->base.base.id,
9017 drm_get_encoder_name(&encoder->base));
9018
9019 /* Connector is active, but has no active pipe. This is
9020 * fallout from our resume register restoring. Disable
9021 * the encoder manually again. */
9022 if (encoder->base.crtc) {
9023 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9024 encoder->base.base.id,
9025 drm_get_encoder_name(&encoder->base));
9026 encoder->disable(encoder);
9027 }
9028
9029 /* Inconsistent output/port/pipe state happens presumably due to
9030 * a bug in one of the get_hw_state functions. Or someplace else
9031 * in our code, like the register restore mess on resume. Clamp
9032 * things to off as a safer default. */
9033 list_for_each_entry(connector,
9034 &dev->mode_config.connector_list,
9035 base.head) {
9036 if (connector->encoder != encoder)
9037 continue;
9038
9039 intel_connector_break_all_links(connector);
9040 }
9041 }
9042 /* Enabled encoders without active connectors will be fixed in
9043 * the crtc fixup. */
9044}
9045
44cec740 9046void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9047{
9048 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9049 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9050
9051 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9052 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9053 i915_disable_vga(dev);
0fde901f
KM		 9054 }
9055}
9056
24929352
DV		 9057/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9058 * and i915 state tracking structures. */
45e2b5f6
DV		 9059void intel_modeset_setup_hw_state(struct drm_device *dev,
9060 bool force_restore)
24929352
DV		 9061{
9062 struct drm_i915_private *dev_priv = dev->dev_private;
9063 enum pipe pipe;
9064 u32 tmp;
b5644d05 9065 struct drm_plane *plane;
24929352
DV		 9066 struct intel_crtc *crtc;
9067 struct intel_encoder *encoder;
9068 struct intel_connector *connector;
9069
affa9354 9070 if (HAS_DDI(dev)) {
e28d54cb
PZ		 9071 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9072
9073 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9074 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9075 case TRANS_DDI_EDP_INPUT_A_ON:
9076 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9077 pipe = PIPE_A;
9078 break;
9079 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9080 pipe = PIPE_B;
9081 break;
9082 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9083 pipe = PIPE_C;
9084 break;
aaa148ec
DL		 9085 default:
9086 /* A bogus value has been programmed, disable
9087 * the transcoder */
9088 WARN(1, "Bogus eDP source %08x\n", tmp);
9089 intel_ddi_disable_transcoder_func(dev_priv,
9090 TRANSCODER_EDP);
9091 goto setup_pipes;
e28d54cb
PZ		 9092 }
9093
9094 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9095 crtc->cpu_transcoder = TRANSCODER_EDP;
9096
9097 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9098 pipe_name(pipe));
9099 }
9100 }
9101
aaa148ec 9102setup_pipes:
24929352
DV		 9103 for_each_pipe(pipe) {
9104 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9105
702e7a56 9106 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
24929352
DV		 9107 if (tmp & PIPECONF_ENABLE)
9108 crtc->active = true;
9109 else
9110 crtc->active = false;
9111
9112 crtc->base.enabled = crtc->active;
9113
9114 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9115 crtc->base.base.id,
9116 crtc->active ? "enabled" : "disabled");
9117 }
9118
affa9354 9119 if (HAS_DDI(dev))
6441ab5f
PZ		 9120 intel_ddi_setup_hw_pll_state(dev);
9121
24929352
DV		 9122 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9123 base.head) {
9124 pipe = 0;
9125
9126 if (encoder->get_hw_state(encoder, &pipe)) {
9127 encoder->base.crtc =
9128 dev_priv->pipe_to_crtc_mapping[pipe];
9129 } else {
9130 encoder->base.crtc = NULL;
9131 }
9132
9133 encoder->connectors_active = false;
9134 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9135 encoder->base.base.id,
9136 drm_get_encoder_name(&encoder->base),
9137 encoder->base.crtc ? "enabled" : "disabled",
9138 pipe);
9139 }
9140
9141 list_for_each_entry(connector, &dev->mode_config.connector_list,
9142 base.head) {
9143 if (connector->get_hw_state(connector)) {
9144 connector->base.dpms = DRM_MODE_DPMS_ON;
9145 connector->encoder->connectors_active = true;
9146 connector->base.encoder = &connector->encoder->base;
9147 } else {
9148 connector->base.dpms = DRM_MODE_DPMS_OFF;
9149 connector->base.encoder = NULL;
9150 }
9151 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9152 connector->base.base.id,
9153 drm_get_connector_name(&connector->base),
9154 connector->base.encoder ? "enabled" : "disabled");
9155 }
9156
9157 /* HW state is read out, now we need to sanitize this mess. */
9158 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9159 base.head) {
9160 intel_sanitize_encoder(encoder);
9161 }
9162
9163 for_each_pipe(pipe) {
9164 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9165 intel_sanitize_crtc(crtc);
9166 }
9a935856 9167
45e2b5f6
DV		 9168 if (force_restore) {
9169 for_each_pipe(pipe) {
b5644d05
JB		 9170 struct drm_crtc *crtc =
9171 dev_priv->pipe_to_crtc_mapping[pipe];
9172 intel_crtc_restore_mode(crtc);
45e2b5f6 9173 }
b5644d05
JB		 9174 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9175 intel_plane_restore(plane);
0fde901f
KM		 9176
9177 i915_redisable_vga(dev);
45e2b5f6
DV		 9178 } else {
9179 intel_modeset_update_staged_output_state(dev);
9180 }
8af6cf88
DV		 9181
9182 intel_modeset_check_state(dev);
2e938892
DV		 9183
9184 drm_mode_config_reset(dev);
2c7111db
CW		 9185}
9186
9187void intel_modeset_gem_init(struct drm_device *dev)
9188{
1833b134 9189 intel_modeset_init_hw(dev);
02e792fb
DV		 9190
9191 intel_setup_overlay(dev);
24929352 9192
45e2b5f6 9193 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9194}
9195
9196void intel_modeset_cleanup(struct drm_device *dev)
9197{
652c393a
JB		 9198 struct drm_i915_private *dev_priv = dev->dev_private;
9199 struct drm_crtc *crtc;
9200 struct intel_crtc *intel_crtc;
9201
f87ea761 9202 drm_kms_helper_poll_fini(dev);
652c393a
JB		 9203 mutex_lock(&dev->struct_mutex);
9204
723bfd70
JB		 9205 intel_unregister_dsm_handler();
9206
9207
652c393a
JB		 9208 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9209 /* Skip inactive CRTCs */
9210 if (!crtc->fb)
9211 continue;
9212
9213 intel_crtc = to_intel_crtc(crtc);
3dec0095 9214 intel_increase_pllclock(crtc);
652c393a
JB		 9215 }
9216
973d04f9 9217 intel_disable_fbc(dev);
e70236a8 9218
8090c6b9 9219 intel_disable_gt_powersave(dev);
0cdab21f 9220
930ebb46
DV		 9221 ironlake_teardown_rc6(dev);
9222
57f350b6
JB		 9223 if (IS_VALLEYVIEW(dev))
9224 vlv_init_dpio(dev);
9225
69341a5e
KH		 9226 mutex_unlock(&dev->struct_mutex);
9227
6c0d9350
DV		 9228 /* Disable the irq before mode object teardown, for the irq might
9229 * enqueue unpin/hotplug work. */
9230 drm_irq_uninstall(dev);
9231 cancel_work_sync(&dev_priv->hotplug_work);
c6a828d3 9232 cancel_work_sync(&dev_priv->rps.work);
6c0d9350 9233
1630fe75
CW		 9234 /* flush any delayed tasks or pending work */
9235 flush_scheduled_work();
9236
79e53945 9237 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9238
9239 intel_cleanup_overlay(dev);
79e53945
JB		 9240}
9241
f1c79df3
ZW		 9242/*
9243 * Return which encoder is currently attached for connector.
9244 */
df0e9248 9245struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9246{
df0e9248
CW		 9247 return &intel_attached_encoder(connector)->base;
9248}
f1c79df3 9249
df0e9248
CW		 9250void intel_connector_attach_encoder(struct intel_connector *connector,
9251 struct intel_encoder *encoder)
9252{
9253 connector->encoder = encoder;
9254 drm_mode_connector_attach_encoder(&connector->base,
9255 &encoder->base);
79e53945 9256}
28d52043
DA		 9257
9258/*
9259 * set vga decode state - true == enable VGA decode
9260 */
9261int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9262{
9263 struct drm_i915_private *dev_priv = dev->dev_private;
9264 u16 gmch_ctrl;
9265
9266 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9267 if (state)
9268 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9269 else
9270 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9271 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9272 return 0;
9273}
c4a1d9e4
CW		 9274
9275#ifdef CONFIG_DEBUG_FS
9276#include <linux/seq_file.h>
9277
9278struct intel_display_error_state {
9279 struct intel_cursor_error_state {
9280 u32 control;
9281 u32 position;
9282 u32 base;
9283 u32 size;
52331309 9284 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9285
9286 struct intel_pipe_error_state {
9287 u32 conf;
9288 u32 source;
9289
9290 u32 htotal;
9291 u32 hblank;
9292 u32 hsync;
9293 u32 vtotal;
9294 u32 vblank;
9295 u32 vsync;
52331309 9296 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9297
9298 struct intel_plane_error_state {
9299 u32 control;
9300 u32 stride;
9301 u32 size;
9302 u32 pos;
9303 u32 addr;
9304 u32 surface;
9305 u32 tile_offset;
52331309 9306 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9307};
9308
9309struct intel_display_error_state *
9310intel_display_capture_error_state(struct drm_device *dev)
9311{
0206e353 9312 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9313 struct intel_display_error_state *error;
702e7a56 9314 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9315 int i;
9316
9317 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9318 if (error == NULL)
9319 return NULL;
9320
52331309 9321 for_each_pipe(i) {
702e7a56
PZ		 9322 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9323
a18c4c3d
PZ		 9324 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9325 error->cursor[i].control = I915_READ(CURCNTR(i));
9326 error->cursor[i].position = I915_READ(CURPOS(i));
9327 error->cursor[i].base = I915_READ(CURBASE(i));
9328 } else {
9329 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9330 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9331 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9332 }
c4a1d9e4
CW		 9333
9334 error->plane[i].control = I915_READ(DSPCNTR(i));
9335 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 9336 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9337 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 9338 error->plane[i].pos = I915_READ(DSPPOS(i));
9339 }
ca291363
PZ		 9340 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9341 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 9342 if (INTEL_INFO(dev)->gen >= 4) {
9343 error->plane[i].surface = I915_READ(DSPSURF(i));
9344 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9345 }
9346
702e7a56 9347 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9348 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9349 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9350 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9351 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9352 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9353 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9354 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9355 }
9356
9357 return error;
9358}
9359
9360void
9361intel_display_print_error_state(struct seq_file *m,
9362 struct drm_device *dev,
9363 struct intel_display_error_state *error)
9364{
9365 int i;
9366
7eb552ae 9367 seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
52331309 9368 for_each_pipe(i) {
c4a1d9e4
CW		 9369 seq_printf(m, "Pipe [%d]:\n", i);
9370 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9371 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9372 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9373 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9374 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9375 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9376 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9377 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9378
9379 seq_printf(m, "Plane [%d]:\n", i);
9380 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9381 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 9382 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9383 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
80ca378b
PZ		 9384 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9385 }
4b71a570 9386 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
ca291363 9387 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4
CW		 9388 if (INTEL_INFO(dev)->gen >= 4) {
9389 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9390 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9391 }
9392
9393 seq_printf(m, "Cursor [%d]:\n", i);
9394 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9395 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9396 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9397 }
9398}
9399#endif
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