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drm/i915: handle DDI-related assertions
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
79e53945
JB		 35#include "drmP.h"
36#include "intel_drv.h"
37#include "i915_drm.h"
38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
ab2c0672 40#include "drm_dp_helper.h"
79e53945 41#include "drm_crtc_helper.h"
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
32f9d658
ZW		 44#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
0206e353 46bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 47static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 48static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 49
50typedef struct {
0206e353
AJ		 51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
79e53945
JB		 60} intel_clock_t;
61
62typedef struct {
0206e353 63 int min, max;
79e53945
JB		 64} intel_range_t;
65
66typedef struct {
0206e353
AJ		 67 int dot_limit;
68 int p2_slow, p2_fast;
79e53945
JB		 69} intel_p2_t;
70
71#define INTEL_P2_NUM 2
d4906093
ML		 72typedef struct intel_limit intel_limit_t;
73struct intel_limit {
0206e353
AJ		 74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 77 int, int, intel_clock_t *, intel_clock_t *);
d4906093 78};
79e53945 79
2377b741
JB		 80/* FDI */
81#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
d4906093
ML		 83static bool
84intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 85 int target, int refclk, intel_clock_t *match_clock,
86 intel_clock_t *best_clock);
d4906093
ML		 87static bool
88intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 89 int target, int refclk, intel_clock_t *match_clock,
90 intel_clock_t *best_clock);
79e53945 91
a4fc5ed6
KP		 92static bool
93intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 94 int target, int refclk, intel_clock_t *match_clock,
95 intel_clock_t *best_clock);
5eb08b69 96static bool
f2b115e6 97intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 98 int target, int refclk, intel_clock_t *match_clock,
99 intel_clock_t *best_clock);
a4fc5ed6 100
021357ac
CW		 101static inline u32 /* units of 100MHz */
102intel_fdi_link_freq(struct drm_device *dev)
103{
8b99e68c
CW		 104 if (IS_GEN5(dev)) {
105 struct drm_i915_private *dev_priv = dev->dev_private;
106 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
107 } else
108 return 27;
021357ac
CW		 109}
110
e4b36699 111static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 112 .dot = { .min = 25000, .max = 350000 },
113 .vco = { .min = 930000, .max = 1400000 },
114 .n = { .min = 3, .max = 16 },
115 .m = { .min = 96, .max = 140 },
116 .m1 = { .min = 18, .max = 26 },
117 .m2 = { .min = 6, .max = 16 },
118 .p = { .min = 4, .max = 128 },
119 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 120 .p2 = { .dot_limit = 165000,
121 .p2_slow = 4, .p2_fast = 2 },
d4906093 122 .find_pll = intel_find_best_PLL,
e4b36699
KP		 123};
124
125static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 126 .dot = { .min = 25000, .max = 350000 },
127 .vco = { .min = 930000, .max = 1400000 },
128 .n = { .min = 3, .max = 16 },
129 .m = { .min = 96, .max = 140 },
130 .m1 = { .min = 18, .max = 26 },
131 .m2 = { .min = 6, .max = 16 },
132 .p = { .min = 4, .max = 128 },
133 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 134 .p2 = { .dot_limit = 165000,
135 .p2_slow = 14, .p2_fast = 7 },
d4906093 136 .find_pll = intel_find_best_PLL,
e4b36699 137};
273e27ca 138
e4b36699 139static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 140 .dot = { .min = 20000, .max = 400000 },
141 .vco = { .min = 1400000, .max = 2800000 },
142 .n = { .min = 1, .max = 6 },
143 .m = { .min = 70, .max = 120 },
144 .m1 = { .min = 10, .max = 22 },
145 .m2 = { .min = 5, .max = 9 },
146 .p = { .min = 5, .max = 80 },
147 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 148 .p2 = { .dot_limit = 200000,
149 .p2_slow = 10, .p2_fast = 5 },
d4906093 150 .find_pll = intel_find_best_PLL,
e4b36699
KP		 151};
152
153static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 154 .dot = { .min = 20000, .max = 400000 },
155 .vco = { .min = 1400000, .max = 2800000 },
156 .n = { .min = 1, .max = 6 },
157 .m = { .min = 70, .max = 120 },
158 .m1 = { .min = 10, .max = 22 },
159 .m2 = { .min = 5, .max = 9 },
160 .p = { .min = 7, .max = 98 },
161 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 162 .p2 = { .dot_limit = 112000,
163 .p2_slow = 14, .p2_fast = 7 },
d4906093 164 .find_pll = intel_find_best_PLL,
e4b36699
KP		 165};
166
273e27ca 167
e4b36699 168static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 169 .dot = { .min = 25000, .max = 270000 },
170 .vco = { .min = 1750000, .max = 3500000},
171 .n = { .min = 1, .max = 4 },
172 .m = { .min = 104, .max = 138 },
173 .m1 = { .min = 17, .max = 23 },
174 .m2 = { .min = 5, .max = 11 },
175 .p = { .min = 10, .max = 30 },
176 .p1 = { .min = 1, .max = 3},
177 .p2 = { .dot_limit = 270000,
178 .p2_slow = 10,
179 .p2_fast = 10
044c7c41 180 },
d4906093 181 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 182};
183
184static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 185 .dot = { .min = 22000, .max = 400000 },
186 .vco = { .min = 1750000, .max = 3500000},
187 .n = { .min = 1, .max = 4 },
188 .m = { .min = 104, .max = 138 },
189 .m1 = { .min = 16, .max = 23 },
190 .m2 = { .min = 5, .max = 11 },
191 .p = { .min = 5, .max = 80 },
192 .p1 = { .min = 1, .max = 8},
193 .p2 = { .dot_limit = 165000,
194 .p2_slow = 10, .p2_fast = 5 },
d4906093 195 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 196};
197
198static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 199 .dot = { .min = 20000, .max = 115000 },
200 .vco = { .min = 1750000, .max = 3500000 },
201 .n = { .min = 1, .max = 3 },
202 .m = { .min = 104, .max = 138 },
203 .m1 = { .min = 17, .max = 23 },
204 .m2 = { .min = 5, .max = 11 },
205 .p = { .min = 28, .max = 112 },
206 .p1 = { .min = 2, .max = 8 },
207 .p2 = { .dot_limit = 0,
208 .p2_slow = 14, .p2_fast = 14
044c7c41 209 },
d4906093 210 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 211};
212
213static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 214 .dot = { .min = 80000, .max = 224000 },
215 .vco = { .min = 1750000, .max = 3500000 },
216 .n = { .min = 1, .max = 3 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 17, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 14, .max = 42 },
221 .p1 = { .min = 2, .max = 6 },
222 .p2 = { .dot_limit = 0,
223 .p2_slow = 7, .p2_fast = 7
044c7c41 224 },
d4906093 225 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 226};
227
228static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 229 .dot = { .min = 161670, .max = 227000 },
230 .vco = { .min = 1750000, .max = 3500000},
231 .n = { .min = 1, .max = 2 },
232 .m = { .min = 97, .max = 108 },
233 .m1 = { .min = 0x10, .max = 0x12 },
234 .m2 = { .min = 0x05, .max = 0x06 },
235 .p = { .min = 10, .max = 20 },
236 .p1 = { .min = 1, .max = 2},
237 .p2 = { .dot_limit = 0,
273e27ca 238 .p2_slow = 10, .p2_fast = 10 },
0206e353 239 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 240};
241
f2b115e6 242static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 243 .dot = { .min = 20000, .max = 400000},
244 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 245 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 246 .n = { .min = 3, .max = 6 },
247 .m = { .min = 2, .max = 256 },
273e27ca 248 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 249 .m1 = { .min = 0, .max = 0 },
250 .m2 = { .min = 0, .max = 254 },
251 .p = { .min = 5, .max = 80 },
252 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 253 .p2 = { .dot_limit = 200000,
254 .p2_slow = 10, .p2_fast = 5 },
6115707b 255 .find_pll = intel_find_best_PLL,
e4b36699
KP		 256};
257
f2b115e6 258static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 259 .dot = { .min = 20000, .max = 400000 },
260 .vco = { .min = 1700000, .max = 3500000 },
261 .n = { .min = 3, .max = 6 },
262 .m = { .min = 2, .max = 256 },
263 .m1 = { .min = 0, .max = 0 },
264 .m2 = { .min = 0, .max = 254 },
265 .p = { .min = 7, .max = 112 },
266 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 267 .p2 = { .dot_limit = 112000,
268 .p2_slow = 14, .p2_fast = 14 },
6115707b 269 .find_pll = intel_find_best_PLL,
e4b36699
KP		 270};
271
273e27ca
EA		 272/* Ironlake / Sandybridge
273 *
274 * We calculate clock using (register_value + 2) for N/M1/M2, so here
275 * the range value for them is (actual_value - 2).
276 */
b91ad0ec 277static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 278 .dot = { .min = 25000, .max = 350000 },
279 .vco = { .min = 1760000, .max = 3510000 },
280 .n = { .min = 1, .max = 5 },
281 .m = { .min = 79, .max = 127 },
282 .m1 = { .min = 12, .max = 22 },
283 .m2 = { .min = 5, .max = 9 },
284 .p = { .min = 5, .max = 80 },
285 .p1 = { .min = 1, .max = 8 },
286 .p2 = { .dot_limit = 225000,
287 .p2_slow = 10, .p2_fast = 5 },
4547668a 288 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 289};
290
b91ad0ec 291static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 292 .dot = { .min = 25000, .max = 350000 },
293 .vco = { .min = 1760000, .max = 3510000 },
294 .n = { .min = 1, .max = 3 },
295 .m = { .min = 79, .max = 118 },
296 .m1 = { .min = 12, .max = 22 },
297 .m2 = { .min = 5, .max = 9 },
298 .p = { .min = 28, .max = 112 },
299 .p1 = { .min = 2, .max = 8 },
300 .p2 = { .dot_limit = 225000,
301 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 302 .find_pll = intel_g4x_find_best_PLL,
303};
304
305static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 306 .dot = { .min = 25000, .max = 350000 },
307 .vco = { .min = 1760000, .max = 3510000 },
308 .n = { .min = 1, .max = 3 },
309 .m = { .min = 79, .max = 127 },
310 .m1 = { .min = 12, .max = 22 },
311 .m2 = { .min = 5, .max = 9 },
312 .p = { .min = 14, .max = 56 },
313 .p1 = { .min = 2, .max = 8 },
314 .p2 = { .dot_limit = 225000,
315 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 316 .find_pll = intel_g4x_find_best_PLL,
317};
318
273e27ca 319/* LVDS 100mhz refclk limits. */
b91ad0ec 320static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 2 },
324 .m = { .min = 79, .max = 126 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 28, .max = 112 },
0206e353 328 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 331 .find_pll = intel_g4x_find_best_PLL,
332};
333
334static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 335 .dot = { .min = 25000, .max = 350000 },
336 .vco = { .min = 1760000, .max = 3510000 },
337 .n = { .min = 1, .max = 3 },
338 .m = { .min = 79, .max = 126 },
339 .m1 = { .min = 12, .max = 22 },
340 .m2 = { .min = 5, .max = 9 },
341 .p = { .min = 14, .max = 42 },
0206e353 342 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 343 .p2 = { .dot_limit = 225000,
344 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 345 .find_pll = intel_g4x_find_best_PLL,
346};
347
348static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 349 .dot = { .min = 25000, .max = 350000 },
350 .vco = { .min = 1760000, .max = 3510000},
351 .n = { .min = 1, .max = 2 },
352 .m = { .min = 81, .max = 90 },
353 .m1 = { .min = 12, .max = 22 },
354 .m2 = { .min = 5, .max = 9 },
355 .p = { .min = 10, .max = 20 },
356 .p1 = { .min = 1, .max = 2},
357 .p2 = { .dot_limit = 0,
273e27ca 358 .p2_slow = 10, .p2_fast = 10 },
0206e353 359 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 360};
361
57f350b6
JB		 362u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
363{
364 unsigned long flags;
365 u32 val = 0;
366
367 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
368 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
369 DRM_ERROR("DPIO idle wait timed out\n");
370 goto out_unlock;
371 }
372
373 I915_WRITE(DPIO_REG, reg);
374 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
375 DPIO_BYTE);
376 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
377 DRM_ERROR("DPIO read wait timed out\n");
378 goto out_unlock;
379 }
380 val = I915_READ(DPIO_DATA);
381
382out_unlock:
383 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
384 return val;
385}
386
57f350b6
JB		 387static void vlv_init_dpio(struct drm_device *dev)
388{
389 struct drm_i915_private *dev_priv = dev->dev_private;
390
391 /* Reset the DPIO config */
392 I915_WRITE(DPIO_CTL, 0);
393 POSTING_READ(DPIO_CTL);
394 I915_WRITE(DPIO_CTL, 1);
395 POSTING_READ(DPIO_CTL);
396}
397
618563e3
DV		 398static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
399{
400 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
401 return 1;
402}
403
404static const struct dmi_system_id intel_dual_link_lvds[] = {
405 {
406 .callback = intel_dual_link_lvds_callback,
407 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
408 .matches = {
409 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
410 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
411 },
412 },
413 { } /* terminating entry */
414};
415
b0354385
TI		 416static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
417 unsigned int reg)
418{
419 unsigned int val;
420
121d527a
TI		 421 /* use the module option value if specified */
422 if (i915_lvds_channel_mode > 0)
423 return i915_lvds_channel_mode == 2;
424
618563e3
DV		 425 if (dmi_check_system(intel_dual_link_lvds))
426 return true;
427
b0354385
TI		 428 if (dev_priv->lvds_val)
429 val = dev_priv->lvds_val;
430 else {
431 /* BIOS should set the proper LVDS register value at boot, but
432 * in reality, it doesn't set the value when the lid is closed;
433 * we need to check "the value to be set" in VBT when LVDS
434 * register is uninitialized.
435 */
436 val = I915_READ(reg);
437 if (!(val & ~LVDS_DETECTED))
438 val = dev_priv->bios_lvds_val;
439 dev_priv->lvds_val = val;
440 }
441 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
442}
443
1b894b59
CW		 444static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
445 int refclk)
2c07245f 446{
b91ad0ec
ZW		 447 struct drm_device *dev = crtc->dev;
448 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 449 const intel_limit_t *limit;
b91ad0ec
ZW		 450
451 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 452 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
b91ad0ec 453 /* LVDS dual channel */
1b894b59 454 if (refclk == 100000)
b91ad0ec
ZW		 455 limit = &intel_limits_ironlake_dual_lvds_100m;
456 else
457 limit = &intel_limits_ironlake_dual_lvds;
458 } else {
1b894b59 459 if (refclk == 100000)
b91ad0ec
ZW		 460 limit = &intel_limits_ironlake_single_lvds_100m;
461 else
462 limit = &intel_limits_ironlake_single_lvds;
463 }
464 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 465 HAS_eDP)
466 limit = &intel_limits_ironlake_display_port;
2c07245f 467 else
b91ad0ec 468 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 469
470 return limit;
471}
472
044c7c41
ML		 473static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
474{
475 struct drm_device *dev = crtc->dev;
476 struct drm_i915_private *dev_priv = dev->dev_private;
477 const intel_limit_t *limit;
478
479 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 480 if (is_dual_link_lvds(dev_priv, LVDS))
044c7c41 481 /* LVDS with dual channel */
e4b36699 482 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 483 else
484 /* LVDS with dual channel */
e4b36699 485 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 486 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
487 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 488 limit = &intel_limits_g4x_hdmi;
044c7c41 489 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 490 limit = &intel_limits_g4x_sdvo;
0206e353 491 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 492 limit = &intel_limits_g4x_display_port;
044c7c41 493 } else /* The option is for other outputs */
e4b36699 494 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 495
496 return limit;
497}
498
1b894b59 499static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 500{
501 struct drm_device *dev = crtc->dev;
502 const intel_limit_t *limit;
503
bad720ff 504 if (HAS_PCH_SPLIT(dev))
1b894b59 505 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 506 else if (IS_G4X(dev)) {
044c7c41 507 limit = intel_g4x_limit(crtc);
f2b115e6 508 } else if (IS_PINEVIEW(dev)) {
2177832f 509 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 510 limit = &intel_limits_pineview_lvds;
2177832f 511 else
f2b115e6 512 limit = &intel_limits_pineview_sdvo;
a6c45cf0
CW		 513 } else if (!IS_GEN2(dev)) {
514 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
515 limit = &intel_limits_i9xx_lvds;
516 else
517 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 518 } else {
519 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 520 limit = &intel_limits_i8xx_lvds;
79e53945 521 else
e4b36699 522 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 523 }
524 return limit;
525}
526
f2b115e6
AJ		 527/* m1 is reserved as 0 in Pineview, n is a ring counter */
528static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 529{
2177832f
SL		 530 clock->m = clock->m2 + 2;
531 clock->p = clock->p1 * clock->p2;
532 clock->vco = refclk * clock->m / clock->n;
533 clock->dot = clock->vco / clock->p;
534}
535
536static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
537{
f2b115e6
AJ		 538 if (IS_PINEVIEW(dev)) {
539 pineview_clock(refclk, clock);
2177832f
SL		 540 return;
541 }
79e53945
JB		 542 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
543 clock->p = clock->p1 * clock->p2;
544 clock->vco = refclk * clock->m / (clock->n + 2);
545 clock->dot = clock->vco / clock->p;
546}
547
79e53945
JB		 548/**
549 * Returns whether any output on the specified pipe is of the specified type
550 */
4ef69c7a 551bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 552{
4ef69c7a
CW		 553 struct drm_device *dev = crtc->dev;
554 struct drm_mode_config *mode_config = &dev->mode_config;
555 struct intel_encoder *encoder;
556
557 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
558 if (encoder->base.crtc == crtc && encoder->type == type)
559 return true;
560
561 return false;
79e53945
JB		 562}
563
7c04d1d9 564#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 565/**
566 * Returns whether the given set of divisors are valid for a given refclk with
567 * the given connectors.
568 */
569
1b894b59
CW		 570static bool intel_PLL_is_valid(struct drm_device *dev,
571 const intel_limit_t *limit,
572 const intel_clock_t *clock)
79e53945 573{
79e53945 574 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 575 INTELPllInvalid("p1 out of range\n");
79e53945 576 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 577 INTELPllInvalid("p out of range\n");
79e53945 578 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 579 INTELPllInvalid("m2 out of range\n");
79e53945 580 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 581 INTELPllInvalid("m1 out of range\n");
f2b115e6 582 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 583 INTELPllInvalid("m1 <= m2\n");
79e53945 584 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 585 INTELPllInvalid("m out of range\n");
79e53945 586 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 587 INTELPllInvalid("n out of range\n");
79e53945 588 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 589 INTELPllInvalid("vco out of range\n");
79e53945
JB		 590 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
591 * connector, etc., rather than just a single range.
592 */
593 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 594 INTELPllInvalid("dot out of range\n");
79e53945
JB		 595
596 return true;
597}
598
d4906093
ML		 599static bool
600intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 601 int target, int refclk, intel_clock_t *match_clock,
602 intel_clock_t *best_clock)
d4906093 603
79e53945
JB		 604{
605 struct drm_device *dev = crtc->dev;
606 struct drm_i915_private *dev_priv = dev->dev_private;
607 intel_clock_t clock;
79e53945
JB		 608 int err = target;
609
bc5e5718 610 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 611 (I915_READ(LVDS)) != 0) {
79e53945
JB		 612 /*
613 * For LVDS, if the panel is on, just rely on its current
614 * settings for dual-channel. We haven't figured out how to
615 * reliably set up different single/dual channel state, if we
616 * even can.
617 */
b0354385 618 if (is_dual_link_lvds(dev_priv, LVDS))
79e53945
JB		 619 clock.p2 = limit->p2.p2_fast;
620 else
621 clock.p2 = limit->p2.p2_slow;
622 } else {
623 if (target < limit->p2.dot_limit)
624 clock.p2 = limit->p2.p2_slow;
625 else
626 clock.p2 = limit->p2.p2_fast;
627 }
628
0206e353 629 memset(best_clock, 0, sizeof(*best_clock));
79e53945 630
42158660
ZY		 631 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
632 clock.m1++) {
633 for (clock.m2 = limit->m2.min;
634 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 635 /* m1 is always 0 in Pineview */
636 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 637 break;
638 for (clock.n = limit->n.min;
639 clock.n <= limit->n.max; clock.n++) {
640 for (clock.p1 = limit->p1.min;
641 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 642 int this_err;
643
2177832f 644 intel_clock(dev, refclk, &clock);
1b894b59
CW		 645 if (!intel_PLL_is_valid(dev, limit,
646 &clock))
79e53945 647 continue;
cec2f356
SP		 648 if (match_clock &&
649 clock.p != match_clock->p)
650 continue;
79e53945
JB		 651
652 this_err = abs(clock.dot - target);
653 if (this_err < err) {
654 *best_clock = clock;
655 err = this_err;
656 }
657 }
658 }
659 }
660 }
661
662 return (err != target);
663}
664
d4906093
ML		 665static bool
666intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 667 int target, int refclk, intel_clock_t *match_clock,
668 intel_clock_t *best_clock)
d4906093
ML		 669{
670 struct drm_device *dev = crtc->dev;
671 struct drm_i915_private *dev_priv = dev->dev_private;
672 intel_clock_t clock;
673 int max_n;
674 bool found;
6ba770dc
AJ		 675 /* approximately equals target * 0.00585 */
676 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 677 found = false;
678
679 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 680 int lvds_reg;
681
c619eed4 682 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 683 lvds_reg = PCH_LVDS;
684 else
685 lvds_reg = LVDS;
686 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 687 LVDS_CLKB_POWER_UP)
688 clock.p2 = limit->p2.p2_fast;
689 else
690 clock.p2 = limit->p2.p2_slow;
691 } else {
692 if (target < limit->p2.dot_limit)
693 clock.p2 = limit->p2.p2_slow;
694 else
695 clock.p2 = limit->p2.p2_fast;
696 }
697
698 memset(best_clock, 0, sizeof(*best_clock));
699 max_n = limit->n.max;
f77f13e2 700 /* based on hardware requirement, prefer smaller n to precision */
d4906093 701 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 702 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 703 for (clock.m1 = limit->m1.max;
704 clock.m1 >= limit->m1.min; clock.m1--) {
705 for (clock.m2 = limit->m2.max;
706 clock.m2 >= limit->m2.min; clock.m2--) {
707 for (clock.p1 = limit->p1.max;
708 clock.p1 >= limit->p1.min; clock.p1--) {
709 int this_err;
710
2177832f 711 intel_clock(dev, refclk, &clock);
1b894b59
CW		 712 if (!intel_PLL_is_valid(dev, limit,
713 &clock))
d4906093 714 continue;
cec2f356
SP		 715 if (match_clock &&
716 clock.p != match_clock->p)
717 continue;
1b894b59
CW		 718
719 this_err = abs(clock.dot - target);
d4906093
ML		 720 if (this_err < err_most) {
721 *best_clock = clock;
722 err_most = this_err;
723 max_n = clock.n;
724 found = true;
725 }
726 }
727 }
728 }
729 }
2c07245f
ZW		 730 return found;
731}
732
5eb08b69 733static bool
f2b115e6 734intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 735 int target, int refclk, intel_clock_t *match_clock,
736 intel_clock_t *best_clock)
5eb08b69
ZW		 737{
738 struct drm_device *dev = crtc->dev;
739 intel_clock_t clock;
4547668a 740
5eb08b69
ZW		 741 if (target < 200000) {
742 clock.n = 1;
743 clock.p1 = 2;
744 clock.p2 = 10;
745 clock.m1 = 12;
746 clock.m2 = 9;
747 } else {
748 clock.n = 2;
749 clock.p1 = 1;
750 clock.p2 = 10;
751 clock.m1 = 14;
752 clock.m2 = 8;
753 }
754 intel_clock(dev, refclk, &clock);
755 memcpy(best_clock, &clock, sizeof(intel_clock_t));
756 return true;
757}
758
a4fc5ed6
KP		 759/* DisplayPort has only two frequencies, 162MHz and 270MHz */
760static bool
761intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 762 int target, int refclk, intel_clock_t *match_clock,
763 intel_clock_t *best_clock)
a4fc5ed6 764{
5eddb70b
CW		 765 intel_clock_t clock;
766 if (target < 200000) {
767 clock.p1 = 2;
768 clock.p2 = 10;
769 clock.n = 2;
770 clock.m1 = 23;
771 clock.m2 = 8;
772 } else {
773 clock.p1 = 1;
774 clock.p2 = 10;
775 clock.n = 1;
776 clock.m1 = 14;
777 clock.m2 = 2;
778 }
779 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
780 clock.p = (clock.p1 * clock.p2);
781 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
782 clock.vco = 0;
783 memcpy(best_clock, &clock, sizeof(intel_clock_t));
784 return true;
a4fc5ed6
KP		 785}
786
a928d536
PZ		 787static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
788{
789 struct drm_i915_private *dev_priv = dev->dev_private;
790 u32 frame, frame_reg = PIPEFRAME(pipe);
791
792 frame = I915_READ(frame_reg);
793
794 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
795 DRM_DEBUG_KMS("vblank wait timed out\n");
796}
797
9d0498a2
JB		 798/**
799 * intel_wait_for_vblank - wait for vblank on a given pipe
800 * @dev: drm device
801 * @pipe: pipe to wait for
802 *
803 * Wait for vblank to occur on a given pipe. Needed for various bits of
804 * mode setting code.
805 */
806void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 807{
9d0498a2 808 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 809 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 810
a928d536
PZ		 811 if (INTEL_INFO(dev)->gen >= 5) {
812 ironlake_wait_for_vblank(dev, pipe);
813 return;
814 }
815
300387c0
CW		 816 /* Clear existing vblank status. Note this will clear any other
817 * sticky status fields as well.
818 *
819 * This races with i915_driver_irq_handler() with the result
820 * that either function could miss a vblank event. Here it is not
821 * fatal, as we will either wait upon the next vblank interrupt or
822 * timeout. Generally speaking intel_wait_for_vblank() is only
823 * called during modeset at which time the GPU should be idle and
824 * should *not* be performing page flips and thus not waiting on
825 * vblanks...
826 * Currently, the result of us stealing a vblank from the irq
827 * handler is that a single frame will be skipped during swapbuffers.
828 */
829 I915_WRITE(pipestat_reg,
830 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
831
9d0498a2 832 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 833 if (wait_for(I915_READ(pipestat_reg) &
834 PIPE_VBLANK_INTERRUPT_STATUS,
835 50))
9d0498a2
JB		 836 DRM_DEBUG_KMS("vblank wait timed out\n");
837}
838
ab7ad7f6
KP		 839/*
840 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 841 * @dev: drm device
842 * @pipe: pipe to wait for
843 *
844 * After disabling a pipe, we can't wait for vblank in the usual way,
845 * spinning on the vblank interrupt status bit, since we won't actually
846 * see an interrupt when the pipe is disabled.
847 *
ab7ad7f6
KP		 848 * On Gen4 and above:
849 * wait for the pipe register state bit to turn off
850 *
851 * Otherwise:
852 * wait for the display line value to settle (it usually
853 * ends up stopping at the start of the next frame).
58e10eb9 854 *
9d0498a2 855 */
58e10eb9 856void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 857{
858 struct drm_i915_private *dev_priv = dev->dev_private;
ab7ad7f6
KP		 859
860 if (INTEL_INFO(dev)->gen >= 4) {
58e10eb9 861 int reg = PIPECONF(pipe);
ab7ad7f6
KP		 862
863 /* Wait for the Pipe State to go off */
58e10eb9
CW		 864 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
865 100))
ab7ad7f6
KP		 866 DRM_DEBUG_KMS("pipe_off wait timed out\n");
867 } else {
837ba00f 868 u32 last_line, line_mask;
58e10eb9 869 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 870 unsigned long timeout = jiffies + msecs_to_jiffies(100);
871
837ba00f
PZ		 872 if (IS_GEN2(dev))
873 line_mask = DSL_LINEMASK_GEN2;
874 else
875 line_mask = DSL_LINEMASK_GEN3;
876
ab7ad7f6
KP		 877 /* Wait for the display line to settle */
878 do {
837ba00f 879 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 880 mdelay(5);
837ba00f 881 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 882 time_after(timeout, jiffies));
883 if (time_after(jiffies, timeout))
884 DRM_DEBUG_KMS("pipe_off wait timed out\n");
885 }
79e53945
JB		 886}
887
b24e7179
JB		 888static const char *state_string(bool enabled)
889{
890 return enabled ? "on" : "off";
891}
892
893/* Only for pre-ILK configs */
894static void assert_pll(struct drm_i915_private *dev_priv,
895 enum pipe pipe, bool state)
896{
897 int reg;
898 u32 val;
899 bool cur_state;
900
901 reg = DPLL(pipe);
902 val = I915_READ(reg);
903 cur_state = !!(val & DPLL_VCO_ENABLE);
904 WARN(cur_state != state,
905 "PLL state assertion failure (expected %s, current %s)\n",
906 state_string(state), state_string(cur_state));
907}
908#define assert_pll_enabled(d, p) assert_pll(d, p, true)
909#define assert_pll_disabled(d, p) assert_pll(d, p, false)
910
040484af
JB		 911/* For ILK+ */
912static void assert_pch_pll(struct drm_i915_private *dev_priv,
ee7b9f93 913 struct intel_crtc *intel_crtc, bool state)
040484af
JB		 914{
915 int reg;
916 u32 val;
917 bool cur_state;
918
9d82aa17
ED		 919 if (HAS_PCH_LPT(dev_priv->dev)) {
920 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
921 return;
922 }
923
ee7b9f93
JB		 924 if (!intel_crtc->pch_pll) {
925 WARN(1, "asserting PCH PLL enabled with no PLL\n");
926 return;
927 }
928
d3ccbe86
JB		 929 if (HAS_PCH_CPT(dev_priv->dev)) {
930 u32 pch_dpll;
931
932 pch_dpll = I915_READ(PCH_DPLL_SEL);
933
934 /* Make sure the selected PLL is enabled to the transcoder */
ee7b9f93
JB		 935 WARN(!((pch_dpll >> (4 * intel_crtc->pipe)) & 8),
936 "transcoder %d PLL not enabled\n", intel_crtc->pipe);
d3ccbe86
JB		 937 }
938
ee7b9f93 939 reg = intel_crtc->pch_pll->pll_reg;
040484af
JB		 940 val = I915_READ(reg);
941 cur_state = !!(val & DPLL_VCO_ENABLE);
942 WARN(cur_state != state,
943 "PCH PLL state assertion failure (expected %s, current %s)\n",
944 state_string(state), state_string(cur_state));
945}
946#define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
947#define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
948
949static void assert_fdi_tx(struct drm_i915_private *dev_priv,
950 enum pipe pipe, bool state)
951{
952 int reg;
953 u32 val;
954 bool cur_state;
955
bf507ef7
ED		 956 if (IS_HASWELL(dev_priv->dev)) {
957 /* On Haswell, DDI is used instead of FDI_TX_CTL */
958 reg = DDI_FUNC_CTL(pipe);
959 val = I915_READ(reg);
960 cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
961 } else {
962 reg = FDI_TX_CTL(pipe);
963 val = I915_READ(reg);
964 cur_state = !!(val & FDI_TX_ENABLE);
965 }
040484af
JB		 966 WARN(cur_state != state,
967 "FDI TX state assertion failure (expected %s, current %s)\n",
968 state_string(state), state_string(cur_state));
969}
970#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
971#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
972
973static void assert_fdi_rx(struct drm_i915_private *dev_priv,
974 enum pipe pipe, bool state)
975{
976 int reg;
977 u32 val;
978 bool cur_state;
979
980 reg = FDI_RX_CTL(pipe);
981 val = I915_READ(reg);
982 cur_state = !!(val & FDI_RX_ENABLE);
983 WARN(cur_state != state,
984 "FDI RX state assertion failure (expected %s, current %s)\n",
985 state_string(state), state_string(cur_state));
986}
987#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
988#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
989
990static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
991 enum pipe pipe)
992{
993 int reg;
994 u32 val;
995
996 /* ILK FDI PLL is always enabled */
997 if (dev_priv->info->gen == 5)
998 return;
999
bf507ef7
ED		 1000 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1001 if (IS_HASWELL(dev_priv->dev))
1002 return;
1003
040484af
JB		 1004 reg = FDI_TX_CTL(pipe);
1005 val = I915_READ(reg);
1006 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1007}
1008
1009static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1010 enum pipe pipe)
1011{
1012 int reg;
1013 u32 val;
1014
1015 reg = FDI_RX_CTL(pipe);
1016 val = I915_READ(reg);
1017 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1018}
1019
ea0760cf
JB		 1020static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1021 enum pipe pipe)
1022{
1023 int pp_reg, lvds_reg;
1024 u32 val;
1025 enum pipe panel_pipe = PIPE_A;
0de3b485 1026 bool locked = true;
ea0760cf
JB		 1027
1028 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1029 pp_reg = PCH_PP_CONTROL;
1030 lvds_reg = PCH_LVDS;
1031 } else {
1032 pp_reg = PP_CONTROL;
1033 lvds_reg = LVDS;
1034 }
1035
1036 val = I915_READ(pp_reg);
1037 if (!(val & PANEL_POWER_ON) ||
1038 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1039 locked = false;
1040
1041 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1042 panel_pipe = PIPE_B;
1043
1044 WARN(panel_pipe == pipe && locked,
1045 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1046 pipe_name(pipe));
ea0760cf
JB		 1047}
1048
b840d907
JB		 1049void assert_pipe(struct drm_i915_private *dev_priv,
1050 enum pipe pipe, bool state)
b24e7179
JB		 1051{
1052 int reg;
1053 u32 val;
63d7bbe9 1054 bool cur_state;
b24e7179 1055
8e636784
DV		 1056 /* if we need the pipe A quirk it must be always on */
1057 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1058 state = true;
1059
b24e7179
JB		 1060 reg = PIPECONF(pipe);
1061 val = I915_READ(reg);
63d7bbe9
JB		 1062 cur_state = !!(val & PIPECONF_ENABLE);
1063 WARN(cur_state != state,
1064 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1065 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1066}
1067
931872fc
CW		 1068static void assert_plane(struct drm_i915_private *dev_priv,
1069 enum plane plane, bool state)
b24e7179
JB		 1070{
1071 int reg;
1072 u32 val;
931872fc 1073 bool cur_state;
b24e7179
JB		 1074
1075 reg = DSPCNTR(plane);
1076 val = I915_READ(reg);
931872fc
CW		 1077 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1078 WARN(cur_state != state,
1079 "plane %c assertion failure (expected %s, current %s)\n",
1080 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1081}
1082
931872fc
CW		 1083#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1084#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1085
b24e7179
JB		 1086static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1087 enum pipe pipe)
1088{
1089 int reg, i;
1090 u32 val;
1091 int cur_pipe;
1092
19ec1358 1093 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 1094 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1095 reg = DSPCNTR(pipe);
1096 val = I915_READ(reg);
1097 WARN((val & DISPLAY_PLANE_ENABLE),
1098 "plane %c assertion failure, should be disabled but not\n",
1099 plane_name(pipe));
19ec1358 1100 return;
28c05794 1101 }
19ec1358 1102
b24e7179
JB		 1103 /* Need to check both planes against the pipe */
1104 for (i = 0; i < 2; i++) {
1105 reg = DSPCNTR(i);
1106 val = I915_READ(reg);
1107 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1108 DISPPLANE_SEL_PIPE_SHIFT;
1109 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1110 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1111 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1112 }
1113}
1114
92f2584a
JB		 1115static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1116{
1117 u32 val;
1118 bool enabled;
1119
9d82aa17
ED		 1120 if (HAS_PCH_LPT(dev_priv->dev)) {
1121 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1122 return;
1123 }
1124
92f2584a
JB		 1125 val = I915_READ(PCH_DREF_CONTROL);
1126 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1127 DREF_SUPERSPREAD_SOURCE_MASK));
1128 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1129}
1130
1131static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1132 enum pipe pipe)
1133{
1134 int reg;
1135 u32 val;
1136 bool enabled;
1137
1138 reg = TRANSCONF(pipe);
1139 val = I915_READ(reg);
1140 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1141 WARN(enabled,
1142 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1143 pipe_name(pipe));
92f2584a
JB		 1144}
1145
4e634389
KP		 1146static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1147 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1148{
1149 if ((val & DP_PORT_EN) == 0)
1150 return false;
1151
1152 if (HAS_PCH_CPT(dev_priv->dev)) {
1153 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1154 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1155 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1156 return false;
1157 } else {
1158 if ((val & DP_PIPE_MASK) != (pipe << 30))
1159 return false;
1160 }
1161 return true;
1162}
1163
1519b995
KP		 1164static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1165 enum pipe pipe, u32 val)
1166{
1167 if ((val & PORT_ENABLE) == 0)
1168 return false;
1169
1170 if (HAS_PCH_CPT(dev_priv->dev)) {
1171 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1172 return false;
1173 } else {
1174 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1175 return false;
1176 }
1177 return true;
1178}
1179
1180static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1181 enum pipe pipe, u32 val)
1182{
1183 if ((val & LVDS_PORT_EN) == 0)
1184 return false;
1185
1186 if (HAS_PCH_CPT(dev_priv->dev)) {
1187 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1188 return false;
1189 } else {
1190 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1191 return false;
1192 }
1193 return true;
1194}
1195
1196static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1197 enum pipe pipe, u32 val)
1198{
1199 if ((val & ADPA_DAC_ENABLE) == 0)
1200 return false;
1201 if (HAS_PCH_CPT(dev_priv->dev)) {
1202 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1203 return false;
1204 } else {
1205 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1206 return false;
1207 }
1208 return true;
1209}
1210
291906f1 1211static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1212 enum pipe pipe, int reg, u32 port_sel)
291906f1 1213{
47a05eca 1214 u32 val = I915_READ(reg);
4e634389 1215 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1216 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1217 reg, pipe_name(pipe));
291906f1
JB		 1218}
1219
1220static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1221 enum pipe pipe, int reg)
1222{
47a05eca 1223 u32 val = I915_READ(reg);
1519b995 1224 WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
23c99e77 1225 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1226 reg, pipe_name(pipe));
291906f1
JB		 1227}
1228
1229static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1230 enum pipe pipe)
1231{
1232 int reg;
1233 u32 val;
291906f1 1234
f0575e92
KP		 1235 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1236 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1237 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1238
1239 reg = PCH_ADPA;
1240 val = I915_READ(reg);
1519b995 1241 WARN(adpa_pipe_enabled(dev_priv, val, pipe),
291906f1 1242 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1243 pipe_name(pipe));
291906f1
JB		 1244
1245 reg = PCH_LVDS;
1246 val = I915_READ(reg);
1519b995 1247 WARN(lvds_pipe_enabled(dev_priv, val, pipe),
291906f1 1248 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1249 pipe_name(pipe));
291906f1
JB		 1250
1251 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1252 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1253 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1254}
1255
63d7bbe9
JB		 1256/**
1257 * intel_enable_pll - enable a PLL
1258 * @dev_priv: i915 private structure
1259 * @pipe: pipe PLL to enable
1260 *
1261 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1262 * make sure the PLL reg is writable first though, since the panel write
1263 * protect mechanism may be enabled.
1264 *
1265 * Note! This is for pre-ILK only.
1266 */
1267static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1268{
1269 int reg;
1270 u32 val;
1271
1272 /* No really, not for ILK+ */
1273 BUG_ON(dev_priv->info->gen >= 5);
1274
1275 /* PLL is protected by panel, make sure we can write it */
1276 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1277 assert_panel_unlocked(dev_priv, pipe);
1278
1279 reg = DPLL(pipe);
1280 val = I915_READ(reg);
1281 val |= DPLL_VCO_ENABLE;
1282
1283 /* We do this three times for luck */
1284 I915_WRITE(reg, val);
1285 POSTING_READ(reg);
1286 udelay(150); /* wait for warmup */
1287 I915_WRITE(reg, val);
1288 POSTING_READ(reg);
1289 udelay(150); /* wait for warmup */
1290 I915_WRITE(reg, val);
1291 POSTING_READ(reg);
1292 udelay(150); /* wait for warmup */
1293}
1294
1295/**
1296 * intel_disable_pll - disable a PLL
1297 * @dev_priv: i915 private structure
1298 * @pipe: pipe PLL to disable
1299 *
1300 * Disable the PLL for @pipe, making sure the pipe is off first.
1301 *
1302 * Note! This is for pre-ILK only.
1303 */
1304static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1305{
1306 int reg;
1307 u32 val;
1308
1309 /* Don't disable pipe A or pipe A PLLs if needed */
1310 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1311 return;
1312
1313 /* Make sure the pipe isn't still relying on us */
1314 assert_pipe_disabled(dev_priv, pipe);
1315
1316 reg = DPLL(pipe);
1317 val = I915_READ(reg);
1318 val &= ~DPLL_VCO_ENABLE;
1319 I915_WRITE(reg, val);
1320 POSTING_READ(reg);
1321}
1322
a416edef
ED		 1323/* SBI access */
1324static void
1325intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1326{
1327 unsigned long flags;
1328
1329 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1330 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_READY) == 0,
1331 100)) {
1332 DRM_ERROR("timeout waiting for SBI to become ready\n");
1333 goto out_unlock;
1334 }
1335
1336 I915_WRITE(SBI_ADDR,
1337 (reg << 16));
1338 I915_WRITE(SBI_DATA,
1339 value);
1340 I915_WRITE(SBI_CTL_STAT,
1341 SBI_BUSY |
1342 SBI_CTL_OP_CRWR);
1343
1344 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_READY | SBI_RESPONSE_SUCCESS)) == 0,
1345 100)) {
1346 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1347 goto out_unlock;
1348 }
1349
1350out_unlock:
1351 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1352}
1353
1354static u32
1355intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1356{
1357 unsigned long flags;
1358 u32 value;
1359
1360 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1361 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_READY) == 0,
1362 100)) {
1363 DRM_ERROR("timeout waiting for SBI to become ready\n");
1364 goto out_unlock;
1365 }
1366
1367 I915_WRITE(SBI_ADDR,
1368 (reg << 16));
1369 I915_WRITE(SBI_CTL_STAT,
1370 SBI_BUSY |
1371 SBI_CTL_OP_CRRD);
1372
1373 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_READY | SBI_RESPONSE_SUCCESS)) == 0,
1374 100)) {
1375 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1376 goto out_unlock;
1377 }
1378
1379 value = I915_READ(SBI_DATA);
1380
1381out_unlock:
1382 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1383 return value;
1384}
1385
92f2584a
JB		 1386/**
1387 * intel_enable_pch_pll - enable PCH PLL
1388 * @dev_priv: i915 private structure
1389 * @pipe: pipe PLL to enable
1390 *
1391 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1392 * drives the transcoder clock.
1393 */
ee7b9f93 1394static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1395{
ee7b9f93
JB		 1396 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1397 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a
JB		 1398 int reg;
1399 u32 val;
1400
1401 /* PCH only available on ILK+ */
1402 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1403 BUG_ON(pll == NULL);
1404 BUG_ON(pll->refcount == 0);
1405
1406 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1407 pll->pll_reg, pll->active, pll->on,
1408 intel_crtc->base.base.id);
92f2584a
JB		 1409
1410 /* PCH refclock must be enabled first */
1411 assert_pch_refclk_enabled(dev_priv);
1412
ee7b9f93
JB		 1413 if (pll->active++ && pll->on) {
1414 assert_pch_pll_enabled(dev_priv, intel_crtc);
1415 return;
1416 }
1417
1418 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1419
1420 reg = pll->pll_reg;
92f2584a
JB		 1421 val = I915_READ(reg);
1422 val |= DPLL_VCO_ENABLE;
1423 I915_WRITE(reg, val);
1424 POSTING_READ(reg);
1425 udelay(200);
ee7b9f93
JB		 1426
1427 pll->on = true;
92f2584a
JB		 1428}
1429
ee7b9f93 1430static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1431{
ee7b9f93
JB		 1432 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1433 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1434 int reg;
ee7b9f93 1435 u32 val;
4c609cb8 1436
92f2584a
JB		 1437 /* PCH only available on ILK+ */
1438 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1439 if (pll == NULL)
1440 return;
92f2584a 1441
ee7b9f93 1442 BUG_ON(pll->refcount == 0);
7a419866 1443
ee7b9f93
JB		 1444 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1445 pll->pll_reg, pll->active, pll->on,
1446 intel_crtc->base.base.id);
7a419866 1447
ee7b9f93
JB		 1448 BUG_ON(pll->active == 0);
1449 if (--pll->active) {
1450 assert_pch_pll_enabled(dev_priv, intel_crtc);
7a419866 1451 return;
ee7b9f93
JB		 1452 }
1453
1454 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1455
1456 /* Make sure transcoder isn't still depending on us */
1457 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1458
ee7b9f93 1459 reg = pll->pll_reg;
92f2584a
JB		 1460 val = I915_READ(reg);
1461 val &= ~DPLL_VCO_ENABLE;
1462 I915_WRITE(reg, val);
1463 POSTING_READ(reg);
1464 udelay(200);
ee7b9f93
JB		 1465
1466 pll->on = false;
92f2584a
JB		 1467}
1468
040484af
JB		 1469static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1470 enum pipe pipe)
1471{
1472 int reg;
5f7f726d 1473 u32 val, pipeconf_val;
7c26e5c6 1474 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
040484af
JB		 1475
1476 /* PCH only available on ILK+ */
1477 BUG_ON(dev_priv->info->gen < 5);
1478
1479 /* Make sure PCH DPLL is enabled */
ee7b9f93 1480 assert_pch_pll_enabled(dev_priv, to_intel_crtc(crtc));
040484af
JB		 1481
1482 /* FDI must be feeding us bits for PCH ports */
1483 assert_fdi_tx_enabled(dev_priv, pipe);
1484 assert_fdi_rx_enabled(dev_priv, pipe);
1485
1486 reg = TRANSCONF(pipe);
1487 val = I915_READ(reg);
5f7f726d 1488 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1489
1490 if (HAS_PCH_IBX(dev_priv->dev)) {
1491 /*
1492 * make the BPC in transcoder be consistent with
1493 * that in pipeconf reg.
1494 */
1495 val &= ~PIPE_BPC_MASK;
5f7f726d 1496 val |= pipeconf_val & PIPE_BPC_MASK;
e9bcff5c 1497 }
5f7f726d
PZ		 1498
1499 val &= ~TRANS_INTERLACE_MASK;
1500 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1501 if (HAS_PCH_IBX(dev_priv->dev) &&
1502 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1503 val |= TRANS_LEGACY_INTERLACED_ILK;
1504 else
1505 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1506 else
1507 val |= TRANS_PROGRESSIVE;
1508
040484af
JB		 1509 I915_WRITE(reg, val | TRANS_ENABLE);
1510 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1511 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1512}
1513
1514static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1515 enum pipe pipe)
1516{
1517 int reg;
1518 u32 val;
1519
1520 /* FDI relies on the transcoder */
1521 assert_fdi_tx_disabled(dev_priv, pipe);
1522 assert_fdi_rx_disabled(dev_priv, pipe);
1523
291906f1
JB		 1524 /* Ports must be off as well */
1525 assert_pch_ports_disabled(dev_priv, pipe);
1526
040484af
JB		 1527 reg = TRANSCONF(pipe);
1528 val = I915_READ(reg);
1529 val &= ~TRANS_ENABLE;
1530 I915_WRITE(reg, val);
1531 /* wait for PCH transcoder off, transcoder state */
1532 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1533 DRM_ERROR("failed to disable transcoder %d\n", pipe);
040484af
JB		 1534}
1535
b24e7179 1536/**
309cfea8 1537 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1538 * @dev_priv: i915 private structure
1539 * @pipe: pipe to enable
040484af 1540 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1541 *
1542 * Enable @pipe, making sure that various hardware specific requirements
1543 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1544 *
1545 * @pipe should be %PIPE_A or %PIPE_B.
1546 *
1547 * Will wait until the pipe is actually running (i.e. first vblank) before
1548 * returning.
1549 */
040484af
JB		 1550static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1551 bool pch_port)
b24e7179
JB		 1552{
1553 int reg;
1554 u32 val;
1555
1556 /*
1557 * A pipe without a PLL won't actually be able to drive bits from
1558 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1559 * need the check.
1560 */
1561 if (!HAS_PCH_SPLIT(dev_priv->dev))
1562 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1563 else {
1564 if (pch_port) {
1565 /* if driving the PCH, we need FDI enabled */
1566 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1567 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1568 }
1569 /* FIXME: assert CPU port conditions for SNB+ */
1570 }
b24e7179
JB		 1571
1572 reg = PIPECONF(pipe);
1573 val = I915_READ(reg);
00d70b15
CW		 1574 if (val & PIPECONF_ENABLE)
1575 return;
1576
1577 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1578 intel_wait_for_vblank(dev_priv->dev, pipe);
1579}
1580
1581/**
309cfea8 1582 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1583 * @dev_priv: i915 private structure
1584 * @pipe: pipe to disable
1585 *
1586 * Disable @pipe, making sure that various hardware specific requirements
1587 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1588 *
1589 * @pipe should be %PIPE_A or %PIPE_B.
1590 *
1591 * Will wait until the pipe has shut down before returning.
1592 */
1593static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1594 enum pipe pipe)
1595{
1596 int reg;
1597 u32 val;
1598
1599 /*
1600 * Make sure planes won't keep trying to pump pixels to us,
1601 * or we might hang the display.
1602 */
1603 assert_planes_disabled(dev_priv, pipe);
1604
1605 /* Don't disable pipe A or pipe A PLLs if needed */
1606 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1607 return;
1608
1609 reg = PIPECONF(pipe);
1610 val = I915_READ(reg);
00d70b15
CW		 1611 if ((val & PIPECONF_ENABLE) == 0)
1612 return;
1613
1614 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1615 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1616}
1617
d74362c9
KP		 1618/*
1619 * Plane regs are double buffered, going from enabled->disabled needs a
1620 * trigger in order to latch. The display address reg provides this.
1621 */
6f1d69b0 1622void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1623 enum plane plane)
1624{
1625 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1626 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1627}
1628
b24e7179
JB		 1629/**
1630 * intel_enable_plane - enable a display plane on a given pipe
1631 * @dev_priv: i915 private structure
1632 * @plane: plane to enable
1633 * @pipe: pipe being fed
1634 *
1635 * Enable @plane on @pipe, making sure that @pipe is running first.
1636 */
1637static void intel_enable_plane(struct drm_i915_private *dev_priv,
1638 enum plane plane, enum pipe pipe)
1639{
1640 int reg;
1641 u32 val;
1642
1643 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1644 assert_pipe_enabled(dev_priv, pipe);
1645
1646 reg = DSPCNTR(plane);
1647 val = I915_READ(reg);
00d70b15
CW		 1648 if (val & DISPLAY_PLANE_ENABLE)
1649 return;
1650
1651 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1652 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1653 intel_wait_for_vblank(dev_priv->dev, pipe);
1654}
1655
b24e7179
JB		 1656/**
1657 * intel_disable_plane - disable a display plane
1658 * @dev_priv: i915 private structure
1659 * @plane: plane to disable
1660 * @pipe: pipe consuming the data
1661 *
1662 * Disable @plane; should be an independent operation.
1663 */
1664static void intel_disable_plane(struct drm_i915_private *dev_priv,
1665 enum plane plane, enum pipe pipe)
1666{
1667 int reg;
1668 u32 val;
1669
1670 reg = DSPCNTR(plane);
1671 val = I915_READ(reg);
00d70b15
CW		 1672 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1673 return;
1674
1675 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1676 intel_flush_display_plane(dev_priv, plane);
1677 intel_wait_for_vblank(dev_priv->dev, pipe);
1678}
1679
47a05eca 1680static void disable_pch_dp(struct drm_i915_private *dev_priv,
f0575e92 1681 enum pipe pipe, int reg, u32 port_sel)
47a05eca
JB		 1682{
1683 u32 val = I915_READ(reg);
4e634389 1684 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
f0575e92 1685 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
47a05eca 1686 I915_WRITE(reg, val & ~DP_PORT_EN);
f0575e92 1687 }
47a05eca
JB		 1688}
1689
1690static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1691 enum pipe pipe, int reg)
1692{
1693 u32 val = I915_READ(reg);
1519b995 1694 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
f0575e92
KP		 1695 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1696 reg, pipe);
47a05eca 1697 I915_WRITE(reg, val & ~PORT_ENABLE);
f0575e92 1698 }
47a05eca
JB		 1699}
1700
1701/* Disable any ports connected to this transcoder */
1702static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1703 enum pipe pipe)
1704{
1705 u32 reg, val;
1706
1707 val = I915_READ(PCH_PP_CONTROL);
1708 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1709
f0575e92
KP		 1710 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1711 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1712 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
47a05eca
JB		 1713
1714 reg = PCH_ADPA;
1715 val = I915_READ(reg);
1519b995 1716 if (adpa_pipe_enabled(dev_priv, val, pipe))
47a05eca
JB		 1717 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1718
1719 reg = PCH_LVDS;
1720 val = I915_READ(reg);
1519b995
KP		 1721 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1722 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
47a05eca
JB		 1723 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1724 POSTING_READ(reg);
1725 udelay(100);
1726 }
1727
1728 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1729 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1730 disable_pch_hdmi(dev_priv, pipe, HDMID);
1731}
1732
127bd2ac 1733int
48b956c5 1734intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1735 struct drm_i915_gem_object *obj,
919926ae 1736 struct intel_ring_buffer *pipelined)
6b95a207 1737{
ce453d81 1738 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1739 u32 alignment;
1740 int ret;
1741
05394f39 1742 switch (obj->tiling_mode) {
6b95a207 1743 case I915_TILING_NONE:
534843da
CW		 1744 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1745 alignment = 128 * 1024;
a6c45cf0 1746 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1747 alignment = 4 * 1024;
1748 else
1749 alignment = 64 * 1024;
6b95a207
KH		 1750 break;
1751 case I915_TILING_X:
1752 /* pin() will align the object as required by fence */
1753 alignment = 0;
1754 break;
1755 case I915_TILING_Y:
1756 /* FIXME: Is this true? */
1757 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1758 return -EINVAL;
1759 default:
1760 BUG();
1761 }
1762
ce453d81 1763 dev_priv->mm.interruptible = false;
2da3b9b9 1764 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1765 if (ret)
ce453d81 1766 goto err_interruptible;
6b95a207
KH		 1767
1768 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1769 * fence, whereas 965+ only requires a fence if using
1770 * framebuffer compression. For simplicity, we always install
1771 * a fence as the cost is not that onerous.
1772 */
06d98131 1773 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1774 if (ret)
1775 goto err_unpin;
1690e1eb 1776
9a5a53b3 1777 i915_gem_object_pin_fence(obj);
6b95a207 1778
ce453d81 1779 dev_priv->mm.interruptible = true;
6b95a207 1780 return 0;
48b956c5
CW		 1781
1782err_unpin:
1783 i915_gem_object_unpin(obj);
ce453d81
CW		 1784err_interruptible:
1785 dev_priv->mm.interruptible = true;
48b956c5 1786 return ret;
6b95a207
KH		 1787}
1788
1690e1eb
CW		 1789void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1790{
1791 i915_gem_object_unpin_fence(obj);
1792 i915_gem_object_unpin(obj);
1793}
1794
17638cd6
JB		 1795static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1796 int x, int y)
81255565
JB		 1797{
1798 struct drm_device *dev = crtc->dev;
1799 struct drm_i915_private *dev_priv = dev->dev_private;
1800 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1801 struct intel_framebuffer *intel_fb;
05394f39 1802 struct drm_i915_gem_object *obj;
81255565
JB		 1803 int plane = intel_crtc->plane;
1804 unsigned long Start, Offset;
81255565 1805 u32 dspcntr;
5eddb70b 1806 u32 reg;
81255565
JB		 1807
1808 switch (plane) {
1809 case 0:
1810 case 1:
1811 break;
1812 default:
1813 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1814 return -EINVAL;
1815 }
1816
1817 intel_fb = to_intel_framebuffer(fb);
1818 obj = intel_fb->obj;
81255565 1819
5eddb70b
CW		 1820 reg = DSPCNTR(plane);
1821 dspcntr = I915_READ(reg);
81255565
JB		 1822 /* Mask out pixel format bits in case we change it */
1823 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1824 switch (fb->bits_per_pixel) {
1825 case 8:
1826 dspcntr |= DISPPLANE_8BPP;
1827 break;
1828 case 16:
1829 if (fb->depth == 15)
1830 dspcntr |= DISPPLANE_15_16BPP;
1831 else
1832 dspcntr |= DISPPLANE_16BPP;
1833 break;
1834 case 24:
1835 case 32:
1836 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1837 break;
1838 default:
17638cd6 1839 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
81255565
JB		 1840 return -EINVAL;
1841 }
a6c45cf0 1842 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1843 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1844 dspcntr |= DISPPLANE_TILED;
1845 else
1846 dspcntr &= ~DISPPLANE_TILED;
1847 }
1848
5eddb70b 1849 I915_WRITE(reg, dspcntr);
81255565 1850
05394f39 1851 Start = obj->gtt_offset;
01f2c773 1852 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 1853
4e6cfefc 1854 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
01f2c773
VS		 1855 Start, Offset, x, y, fb->pitches[0]);
1856 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 1857 if (INTEL_INFO(dev)->gen >= 4) {
446f2545 1858 I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
5eddb70b
CW		 1859 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1860 I915_WRITE(DSPADDR(plane), Offset);
1861 } else
1862 I915_WRITE(DSPADDR(plane), Start + Offset);
1863 POSTING_READ(reg);
81255565 1864
17638cd6
JB		 1865 return 0;
1866}
1867
1868static int ironlake_update_plane(struct drm_crtc *crtc,
1869 struct drm_framebuffer *fb, int x, int y)
1870{
1871 struct drm_device *dev = crtc->dev;
1872 struct drm_i915_private *dev_priv = dev->dev_private;
1873 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1874 struct intel_framebuffer *intel_fb;
1875 struct drm_i915_gem_object *obj;
1876 int plane = intel_crtc->plane;
1877 unsigned long Start, Offset;
1878 u32 dspcntr;
1879 u32 reg;
1880
1881 switch (plane) {
1882 case 0:
1883 case 1:
27f8227b 1884 case 2:
17638cd6
JB		 1885 break;
1886 default:
1887 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1888 return -EINVAL;
1889 }
1890
1891 intel_fb = to_intel_framebuffer(fb);
1892 obj = intel_fb->obj;
1893
1894 reg = DSPCNTR(plane);
1895 dspcntr = I915_READ(reg);
1896 /* Mask out pixel format bits in case we change it */
1897 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1898 switch (fb->bits_per_pixel) {
1899 case 8:
1900 dspcntr |= DISPPLANE_8BPP;
1901 break;
1902 case 16:
1903 if (fb->depth != 16)
1904 return -EINVAL;
1905
1906 dspcntr |= DISPPLANE_16BPP;
1907 break;
1908 case 24:
1909 case 32:
1910 if (fb->depth == 24)
1911 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1912 else if (fb->depth == 30)
1913 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1914 else
1915 return -EINVAL;
1916 break;
1917 default:
1918 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1919 return -EINVAL;
1920 }
1921
1922 if (obj->tiling_mode != I915_TILING_NONE)
1923 dspcntr |= DISPPLANE_TILED;
1924 else
1925 dspcntr &= ~DISPPLANE_TILED;
1926
1927 /* must disable */
1928 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1929
1930 I915_WRITE(reg, dspcntr);
1931
1932 Start = obj->gtt_offset;
01f2c773 1933 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
17638cd6
JB		 1934
1935 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
01f2c773
VS		 1936 Start, Offset, x, y, fb->pitches[0]);
1937 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
446f2545 1938 I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
17638cd6
JB		 1939 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1940 I915_WRITE(DSPADDR(plane), Offset);
1941 POSTING_READ(reg);
1942
1943 return 0;
1944}
1945
1946/* Assume fb object is pinned & idle & fenced and just update base pointers */
1947static int
1948intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1949 int x, int y, enum mode_set_atomic state)
1950{
1951 struct drm_device *dev = crtc->dev;
1952 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 1953
6b8e6ed0
CW		 1954 if (dev_priv->display.disable_fbc)
1955 dev_priv->display.disable_fbc(dev);
3dec0095 1956 intel_increase_pllclock(crtc);
81255565 1957
6b8e6ed0 1958 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 1959}
1960
14667a4b
CW		 1961static int
1962intel_finish_fb(struct drm_framebuffer *old_fb)
1963{
1964 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
1965 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1966 bool was_interruptible = dev_priv->mm.interruptible;
1967 int ret;
1968
1969 wait_event(dev_priv->pending_flip_queue,
1970 atomic_read(&dev_priv->mm.wedged) ||
1971 atomic_read(&obj->pending_flip) == 0);
1972
1973 /* Big Hammer, we also need to ensure that any pending
1974 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1975 * current scanout is retired before unpinning the old
1976 * framebuffer.
1977 *
1978 * This should only fail upon a hung GPU, in which case we
1979 * can safely continue.
1980 */
1981 dev_priv->mm.interruptible = false;
1982 ret = i915_gem_object_finish_gpu(obj);
1983 dev_priv->mm.interruptible = was_interruptible;
1984
1985 return ret;
1986}
1987
5c3b82e2 1988static int
3c4fdcfb
KH		 1989intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1990 struct drm_framebuffer *old_fb)
79e53945
JB		 1991{
1992 struct drm_device *dev = crtc->dev;
6b8e6ed0 1993 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 1994 struct drm_i915_master_private *master_priv;
1995 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5c3b82e2 1996 int ret;
79e53945
JB		 1997
1998 /* no fb bound */
1999 if (!crtc->fb) {
a5071c2f 2000 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2001 return 0;
2002 }
2003
5826eca5
ED		 2004 if(intel_crtc->plane > dev_priv->num_pipe) {
2005 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2006 intel_crtc->plane,
2007 dev_priv->num_pipe);
5c3b82e2 2008 return -EINVAL;
79e53945
JB		 2009 }
2010
5c3b82e2 2011 mutex_lock(&dev->struct_mutex);
265db958
CW		 2012 ret = intel_pin_and_fence_fb_obj(dev,
2013 to_intel_framebuffer(crtc->fb)->obj,
919926ae 2014 NULL);
5c3b82e2
CW		 2015 if (ret != 0) {
2016 mutex_unlock(&dev->struct_mutex);
a5071c2f 2017 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2018 return ret;
2019 }
79e53945 2020
14667a4b
CW		 2021 if (old_fb)
2022 intel_finish_fb(old_fb);
265db958 2023
6b8e6ed0 2024 ret = dev_priv->display.update_plane(crtc, crtc->fb, x, y);
4e6cfefc 2025 if (ret) {
1690e1eb 2026 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
5c3b82e2 2027 mutex_unlock(&dev->struct_mutex);
a5071c2f 2028 DRM_ERROR("failed to update base address\n");
4e6cfefc 2029 return ret;
79e53945 2030 }
3c4fdcfb 2031
b7f1de28
CW		 2032 if (old_fb) {
2033 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2034 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2035 }
652c393a 2036
6b8e6ed0 2037 intel_update_fbc(dev);
5c3b82e2 2038 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 2039
2040 if (!dev->primary->master)
5c3b82e2 2041 return 0;
79e53945
JB		 2042
2043 master_priv = dev->primary->master->driver_priv;
2044 if (!master_priv->sarea_priv)
5c3b82e2 2045 return 0;
79e53945 2046
265db958 2047 if (intel_crtc->pipe) {
79e53945
JB		 2048 master_priv->sarea_priv->pipeB_x = x;
2049 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW		 2050 } else {
2051 master_priv->sarea_priv->pipeA_x = x;
2052 master_priv->sarea_priv->pipeA_y = y;
79e53945 2053 }
5c3b82e2
CW		 2054
2055 return 0;
79e53945
JB		 2056}
2057
5eddb70b 2058static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2059{
2060 struct drm_device *dev = crtc->dev;
2061 struct drm_i915_private *dev_priv = dev->dev_private;
2062 u32 dpa_ctl;
2063
28c97730 2064 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2065 dpa_ctl = I915_READ(DP_A);
2066 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2067
2068 if (clock < 200000) {
2069 u32 temp;
2070 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2071 /* workaround for 160Mhz:
2072 1) program 0x4600c bits 15:0 = 0x8124
2073 2) program 0x46010 bit 0 = 1
2074 3) program 0x46034 bit 24 = 1
2075 4) program 0x64000 bit 14 = 1
2076 */
2077 temp = I915_READ(0x4600c);
2078 temp &= 0xffff0000;
2079 I915_WRITE(0x4600c, temp | 0x8124);
2080
2081 temp = I915_READ(0x46010);
2082 I915_WRITE(0x46010, temp | 1);
2083
2084 temp = I915_READ(0x46034);
2085 I915_WRITE(0x46034, temp | (1 << 24));
2086 } else {
2087 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2088 }
2089 I915_WRITE(DP_A, dpa_ctl);
2090
5eddb70b 2091 POSTING_READ(DP_A);
32f9d658
ZW		 2092 udelay(500);
2093}
2094
5e84e1a4
ZW		 2095static void intel_fdi_normal_train(struct drm_crtc *crtc)
2096{
2097 struct drm_device *dev = crtc->dev;
2098 struct drm_i915_private *dev_priv = dev->dev_private;
2099 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2100 int pipe = intel_crtc->pipe;
2101 u32 reg, temp;
2102
2103 /* enable normal train */
2104 reg = FDI_TX_CTL(pipe);
2105 temp = I915_READ(reg);
61e499bf 2106 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2107 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2108 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2109 } else {
2110 temp &= ~FDI_LINK_TRAIN_NONE;
2111 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2112 }
5e84e1a4
ZW		 2113 I915_WRITE(reg, temp);
2114
2115 reg = FDI_RX_CTL(pipe);
2116 temp = I915_READ(reg);
2117 if (HAS_PCH_CPT(dev)) {
2118 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2119 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2120 } else {
2121 temp &= ~FDI_LINK_TRAIN_NONE;
2122 temp |= FDI_LINK_TRAIN_NONE;
2123 }
2124 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2125
2126 /* wait one idle pattern time */
2127 POSTING_READ(reg);
2128 udelay(1000);
357555c0
JB		 2129
2130 /* IVB wants error correction enabled */
2131 if (IS_IVYBRIDGE(dev))
2132 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2133 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2134}
2135
291427f5
JB		 2136static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2137{
2138 struct drm_i915_private *dev_priv = dev->dev_private;
2139 u32 flags = I915_READ(SOUTH_CHICKEN1);
2140
2141 flags |= FDI_PHASE_SYNC_OVR(pipe);
2142 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2143 flags |= FDI_PHASE_SYNC_EN(pipe);
2144 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2145 POSTING_READ(SOUTH_CHICKEN1);
2146}
2147
8db9d77b
ZW		 2148/* The FDI link training functions for ILK/Ibexpeak. */
2149static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2150{
2151 struct drm_device *dev = crtc->dev;
2152 struct drm_i915_private *dev_priv = dev->dev_private;
2153 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2154 int pipe = intel_crtc->pipe;
0fc932b8 2155 int plane = intel_crtc->plane;
5eddb70b 2156 u32 reg, temp, tries;
8db9d77b 2157
0fc932b8
JB		 2158 /* FDI needs bits from pipe & plane first */
2159 assert_pipe_enabled(dev_priv, pipe);
2160 assert_plane_enabled(dev_priv, plane);
2161
e1a44743
AJ		 2162 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2163 for train result */
5eddb70b
CW		 2164 reg = FDI_RX_IMR(pipe);
2165 temp = I915_READ(reg);
e1a44743
AJ		 2166 temp &= ~FDI_RX_SYMBOL_LOCK;
2167 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2168 I915_WRITE(reg, temp);
2169 I915_READ(reg);
e1a44743
AJ		 2170 udelay(150);
2171
8db9d77b 2172 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2173 reg = FDI_TX_CTL(pipe);
2174 temp = I915_READ(reg);
77ffb597
AJ		 2175 temp &= ~(7 << 19);
2176 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2177 temp &= ~FDI_LINK_TRAIN_NONE;
2178 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2179 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2180
5eddb70b
CW		 2181 reg = FDI_RX_CTL(pipe);
2182 temp = I915_READ(reg);
8db9d77b
ZW		 2183 temp &= ~FDI_LINK_TRAIN_NONE;
2184 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2185 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2186
2187 POSTING_READ(reg);
8db9d77b
ZW		 2188 udelay(150);
2189
5b2adf89 2190 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2191 if (HAS_PCH_IBX(dev)) {
2192 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2193 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2194 FDI_RX_PHASE_SYNC_POINTER_EN);
2195 }
5b2adf89 2196
5eddb70b 2197 reg = FDI_RX_IIR(pipe);
e1a44743 2198 for (tries = 0; tries < 5; tries++) {
5eddb70b 2199 temp = I915_READ(reg);
8db9d77b
ZW		 2200 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2201
2202 if ((temp & FDI_RX_BIT_LOCK)) {
2203 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2204 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2205 break;
2206 }
8db9d77b 2207 }
e1a44743 2208 if (tries == 5)
5eddb70b 2209 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2210
2211 /* Train 2 */
5eddb70b
CW		 2212 reg = FDI_TX_CTL(pipe);
2213 temp = I915_READ(reg);
8db9d77b
ZW		 2214 temp &= ~FDI_LINK_TRAIN_NONE;
2215 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2216 I915_WRITE(reg, temp);
8db9d77b 2217
5eddb70b
CW		 2218 reg = FDI_RX_CTL(pipe);
2219 temp = I915_READ(reg);
8db9d77b
ZW		 2220 temp &= ~FDI_LINK_TRAIN_NONE;
2221 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2222 I915_WRITE(reg, temp);
8db9d77b 2223
5eddb70b
CW		 2224 POSTING_READ(reg);
2225 udelay(150);
8db9d77b 2226
5eddb70b 2227 reg = FDI_RX_IIR(pipe);
e1a44743 2228 for (tries = 0; tries < 5; tries++) {
5eddb70b 2229 temp = I915_READ(reg);
8db9d77b
ZW		 2230 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2231
2232 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2233 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2234 DRM_DEBUG_KMS("FDI train 2 done.\n");
2235 break;
2236 }
8db9d77b 2237 }
e1a44743 2238 if (tries == 5)
5eddb70b 2239 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2240
2241 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2242
8db9d77b
ZW		 2243}
2244
0206e353 2245static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2246 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2247 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2248 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2249 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2250};
2251
2252/* The FDI link training functions for SNB/Cougarpoint. */
2253static void gen6_fdi_link_train(struct drm_crtc *crtc)
2254{
2255 struct drm_device *dev = crtc->dev;
2256 struct drm_i915_private *dev_priv = dev->dev_private;
2257 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2258 int pipe = intel_crtc->pipe;
fa37d39e 2259 u32 reg, temp, i, retry;
8db9d77b 2260
e1a44743
AJ		 2261 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2262 for train result */
5eddb70b
CW		 2263 reg = FDI_RX_IMR(pipe);
2264 temp = I915_READ(reg);
e1a44743
AJ		 2265 temp &= ~FDI_RX_SYMBOL_LOCK;
2266 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2267 I915_WRITE(reg, temp);
2268
2269 POSTING_READ(reg);
e1a44743
AJ		 2270 udelay(150);
2271
8db9d77b 2272 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2273 reg = FDI_TX_CTL(pipe);
2274 temp = I915_READ(reg);
77ffb597
AJ		 2275 temp &= ~(7 << 19);
2276 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2277 temp &= ~FDI_LINK_TRAIN_NONE;
2278 temp |= FDI_LINK_TRAIN_PATTERN_1;
2279 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2280 /* SNB-B */
2281 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2282 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2283
5eddb70b
CW		 2284 reg = FDI_RX_CTL(pipe);
2285 temp = I915_READ(reg);
8db9d77b
ZW		 2286 if (HAS_PCH_CPT(dev)) {
2287 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2288 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2289 } else {
2290 temp &= ~FDI_LINK_TRAIN_NONE;
2291 temp |= FDI_LINK_TRAIN_PATTERN_1;
2292 }
5eddb70b
CW		 2293 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2294
2295 POSTING_READ(reg);
8db9d77b
ZW		 2296 udelay(150);
2297
291427f5
JB		 2298 if (HAS_PCH_CPT(dev))
2299 cpt_phase_pointer_enable(dev, pipe);
2300
0206e353 2301 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2302 reg = FDI_TX_CTL(pipe);
2303 temp = I915_READ(reg);
8db9d77b
ZW		 2304 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2305 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2306 I915_WRITE(reg, temp);
2307
2308 POSTING_READ(reg);
8db9d77b
ZW		 2309 udelay(500);
2310
fa37d39e
SP		 2311 for (retry = 0; retry < 5; retry++) {
2312 reg = FDI_RX_IIR(pipe);
2313 temp = I915_READ(reg);
2314 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2315 if (temp & FDI_RX_BIT_LOCK) {
2316 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2317 DRM_DEBUG_KMS("FDI train 1 done.\n");
2318 break;
2319 }
2320 udelay(50);
8db9d77b 2321 }
fa37d39e
SP		 2322 if (retry < 5)
2323 break;
8db9d77b
ZW		 2324 }
2325 if (i == 4)
5eddb70b 2326 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2327
2328 /* Train 2 */
5eddb70b
CW		 2329 reg = FDI_TX_CTL(pipe);
2330 temp = I915_READ(reg);
8db9d77b
ZW		 2331 temp &= ~FDI_LINK_TRAIN_NONE;
2332 temp |= FDI_LINK_TRAIN_PATTERN_2;
2333 if (IS_GEN6(dev)) {
2334 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2335 /* SNB-B */
2336 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2337 }
5eddb70b 2338 I915_WRITE(reg, temp);
8db9d77b 2339
5eddb70b
CW		 2340 reg = FDI_RX_CTL(pipe);
2341 temp = I915_READ(reg);
8db9d77b
ZW		 2342 if (HAS_PCH_CPT(dev)) {
2343 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2344 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2345 } else {
2346 temp &= ~FDI_LINK_TRAIN_NONE;
2347 temp |= FDI_LINK_TRAIN_PATTERN_2;
2348 }
5eddb70b
CW		 2349 I915_WRITE(reg, temp);
2350
2351 POSTING_READ(reg);
8db9d77b
ZW		 2352 udelay(150);
2353
0206e353 2354 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2355 reg = FDI_TX_CTL(pipe);
2356 temp = I915_READ(reg);
8db9d77b
ZW		 2357 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2358 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2359 I915_WRITE(reg, temp);
2360
2361 POSTING_READ(reg);
8db9d77b
ZW		 2362 udelay(500);
2363
fa37d39e
SP		 2364 for (retry = 0; retry < 5; retry++) {
2365 reg = FDI_RX_IIR(pipe);
2366 temp = I915_READ(reg);
2367 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2368 if (temp & FDI_RX_SYMBOL_LOCK) {
2369 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2370 DRM_DEBUG_KMS("FDI train 2 done.\n");
2371 break;
2372 }
2373 udelay(50);
8db9d77b 2374 }
fa37d39e
SP		 2375 if (retry < 5)
2376 break;
8db9d77b
ZW		 2377 }
2378 if (i == 4)
5eddb70b 2379 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2380
2381 DRM_DEBUG_KMS("FDI train done.\n");
2382}
2383
357555c0
JB		 2384/* Manual link training for Ivy Bridge A0 parts */
2385static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2386{
2387 struct drm_device *dev = crtc->dev;
2388 struct drm_i915_private *dev_priv = dev->dev_private;
2389 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2390 int pipe = intel_crtc->pipe;
2391 u32 reg, temp, i;
2392
2393 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2394 for train result */
2395 reg = FDI_RX_IMR(pipe);
2396 temp = I915_READ(reg);
2397 temp &= ~FDI_RX_SYMBOL_LOCK;
2398 temp &= ~FDI_RX_BIT_LOCK;
2399 I915_WRITE(reg, temp);
2400
2401 POSTING_READ(reg);
2402 udelay(150);
2403
2404 /* enable CPU FDI TX and PCH FDI RX */
2405 reg = FDI_TX_CTL(pipe);
2406 temp = I915_READ(reg);
2407 temp &= ~(7 << 19);
2408 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2409 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2410 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2411 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2412 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2413 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2414 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2415
2416 reg = FDI_RX_CTL(pipe);
2417 temp = I915_READ(reg);
2418 temp &= ~FDI_LINK_TRAIN_AUTO;
2419 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2420 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2421 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2422 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2423
2424 POSTING_READ(reg);
2425 udelay(150);
2426
291427f5
JB		 2427 if (HAS_PCH_CPT(dev))
2428 cpt_phase_pointer_enable(dev, pipe);
2429
0206e353 2430 for (i = 0; i < 4; i++) {
357555c0
JB		 2431 reg = FDI_TX_CTL(pipe);
2432 temp = I915_READ(reg);
2433 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2434 temp |= snb_b_fdi_train_param[i];
2435 I915_WRITE(reg, temp);
2436
2437 POSTING_READ(reg);
2438 udelay(500);
2439
2440 reg = FDI_RX_IIR(pipe);
2441 temp = I915_READ(reg);
2442 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2443
2444 if (temp & FDI_RX_BIT_LOCK ||
2445 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2446 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2447 DRM_DEBUG_KMS("FDI train 1 done.\n");
2448 break;
2449 }
2450 }
2451 if (i == 4)
2452 DRM_ERROR("FDI train 1 fail!\n");
2453
2454 /* Train 2 */
2455 reg = FDI_TX_CTL(pipe);
2456 temp = I915_READ(reg);
2457 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2458 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2459 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2460 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2461 I915_WRITE(reg, temp);
2462
2463 reg = FDI_RX_CTL(pipe);
2464 temp = I915_READ(reg);
2465 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2466 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2467 I915_WRITE(reg, temp);
2468
2469 POSTING_READ(reg);
2470 udelay(150);
2471
0206e353 2472 for (i = 0; i < 4; i++) {
357555c0
JB		 2473 reg = FDI_TX_CTL(pipe);
2474 temp = I915_READ(reg);
2475 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2476 temp |= snb_b_fdi_train_param[i];
2477 I915_WRITE(reg, temp);
2478
2479 POSTING_READ(reg);
2480 udelay(500);
2481
2482 reg = FDI_RX_IIR(pipe);
2483 temp = I915_READ(reg);
2484 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2485
2486 if (temp & FDI_RX_SYMBOL_LOCK) {
2487 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2488 DRM_DEBUG_KMS("FDI train 2 done.\n");
2489 break;
2490 }
2491 }
2492 if (i == 4)
2493 DRM_ERROR("FDI train 2 fail!\n");
2494
2495 DRM_DEBUG_KMS("FDI train done.\n");
2496}
2497
2498static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2c07245f
ZW		 2499{
2500 struct drm_device *dev = crtc->dev;
2501 struct drm_i915_private *dev_priv = dev->dev_private;
2502 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2503 int pipe = intel_crtc->pipe;
5eddb70b 2504 u32 reg, temp;
79e53945 2505
c64e311e 2506 /* Write the TU size bits so error detection works */
5eddb70b
CW		 2507 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2508 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
c64e311e 2509
c98e9dcf 2510 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2511 reg = FDI_RX_CTL(pipe);
2512 temp = I915_READ(reg);
2513 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2514 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2515 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2516 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2517
2518 POSTING_READ(reg);
c98e9dcf
JB		 2519 udelay(200);
2520
2521 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2522 temp = I915_READ(reg);
2523 I915_WRITE(reg, temp | FDI_PCDCLK);
2524
2525 POSTING_READ(reg);
c98e9dcf
JB		 2526 udelay(200);
2527
bf507ef7
ED		 2528 /* On Haswell, the PLL configuration for ports and pipes is handled
2529 * separately, as part of DDI setup */
2530 if (!IS_HASWELL(dev)) {
2531 /* Enable CPU FDI TX PLL, always on for Ironlake */
2532 reg = FDI_TX_CTL(pipe);
2533 temp = I915_READ(reg);
2534 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2535 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2536
bf507ef7
ED		 2537 POSTING_READ(reg);
2538 udelay(100);
2539 }
6be4a607 2540 }
0e23b99d
JB		 2541}
2542
291427f5
JB		 2543static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2544{
2545 struct drm_i915_private *dev_priv = dev->dev_private;
2546 u32 flags = I915_READ(SOUTH_CHICKEN1);
2547
2548 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2549 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2550 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2551 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2552 POSTING_READ(SOUTH_CHICKEN1);
2553}
0fc932b8
JB		 2554static void ironlake_fdi_disable(struct drm_crtc *crtc)
2555{
2556 struct drm_device *dev = crtc->dev;
2557 struct drm_i915_private *dev_priv = dev->dev_private;
2558 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2559 int pipe = intel_crtc->pipe;
2560 u32 reg, temp;
2561
2562 /* disable CPU FDI tx and PCH FDI rx */
2563 reg = FDI_TX_CTL(pipe);
2564 temp = I915_READ(reg);
2565 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2566 POSTING_READ(reg);
2567
2568 reg = FDI_RX_CTL(pipe);
2569 temp = I915_READ(reg);
2570 temp &= ~(0x7 << 16);
2571 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2572 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2573
2574 POSTING_READ(reg);
2575 udelay(100);
2576
2577 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2578 if (HAS_PCH_IBX(dev)) {
2579 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2580 I915_WRITE(FDI_RX_CHICKEN(pipe),
2581 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18 2582 ~FDI_RX_PHASE_SYNC_POINTER_EN));
291427f5
JB		 2583 } else if (HAS_PCH_CPT(dev)) {
2584 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2585 }
0fc932b8
JB		 2586
2587 /* still set train pattern 1 */
2588 reg = FDI_TX_CTL(pipe);
2589 temp = I915_READ(reg);
2590 temp &= ~FDI_LINK_TRAIN_NONE;
2591 temp |= FDI_LINK_TRAIN_PATTERN_1;
2592 I915_WRITE(reg, temp);
2593
2594 reg = FDI_RX_CTL(pipe);
2595 temp = I915_READ(reg);
2596 if (HAS_PCH_CPT(dev)) {
2597 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2598 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2599 } else {
2600 temp &= ~FDI_LINK_TRAIN_NONE;
2601 temp |= FDI_LINK_TRAIN_PATTERN_1;
2602 }
2603 /* BPC in FDI rx is consistent with that in PIPECONF */
2604 temp &= ~(0x07 << 16);
2605 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2606 I915_WRITE(reg, temp);
2607
2608 POSTING_READ(reg);
2609 udelay(100);
2610}
2611
e6c3a2a6
CW		 2612static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2613{
0f91128d 2614 struct drm_device *dev = crtc->dev;
e6c3a2a6
CW		 2615
2616 if (crtc->fb == NULL)
2617 return;
2618
0f91128d
CW		 2619 mutex_lock(&dev->struct_mutex);
2620 intel_finish_fb(crtc->fb);
2621 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2622}
2623
040484af
JB		 2624static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2625{
2626 struct drm_device *dev = crtc->dev;
2627 struct drm_mode_config *mode_config = &dev->mode_config;
2628 struct intel_encoder *encoder;
2629
2630 /*
2631 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2632 * must be driven by its own crtc; no sharing is possible.
2633 */
2634 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2635 if (encoder->base.crtc != crtc)
2636 continue;
2637
6ee8bab0
ED		 2638 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2639 * CPU handles all others */
2640 if (IS_HASWELL(dev)) {
2641 /* It is still unclear how this will work on PPT, so throw up a warning */
2642 WARN_ON(!HAS_PCH_LPT(dev));
2643
2644 if (encoder->type == DRM_MODE_ENCODER_DAC) {
2645 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2646 return true;
2647 } else {
2648 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
2649 encoder->type);
2650 return false;
2651 }
2652 }
2653
040484af
JB		 2654 switch (encoder->type) {
2655 case INTEL_OUTPUT_EDP:
2656 if (!intel_encoder_is_pch_edp(&encoder->base))
2657 return false;
2658 continue;
2659 }
2660 }
2661
2662 return true;
2663}
2664
f67a559d
JB		 2665/*
2666 * Enable PCH resources required for PCH ports:
2667 * - PCH PLLs
2668 * - FDI training & RX/TX
2669 * - update transcoder timings
2670 * - DP transcoding bits
2671 * - transcoder
2672 */
2673static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2674{
2675 struct drm_device *dev = crtc->dev;
2676 struct drm_i915_private *dev_priv = dev->dev_private;
2677 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2678 int pipe = intel_crtc->pipe;
ee7b9f93 2679 u32 reg, temp;
2c07245f 2680
c98e9dcf 2681 /* For PCH output, training FDI link */
674cf967 2682 dev_priv->display.fdi_link_train(crtc);
2c07245f 2683
ee7b9f93 2684 intel_enable_pch_pll(intel_crtc);
8db9d77b 2685
c98e9dcf 2686 if (HAS_PCH_CPT(dev)) {
ee7b9f93 2687 u32 sel;
4b645f14 2688
c98e9dcf 2689 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 2690 switch (pipe) {
2691 default:
2692 case 0:
2693 temp |= TRANSA_DPLL_ENABLE;
2694 sel = TRANSA_DPLLB_SEL;
2695 break;
2696 case 1:
2697 temp |= TRANSB_DPLL_ENABLE;
2698 sel = TRANSB_DPLLB_SEL;
2699 break;
2700 case 2:
2701 temp |= TRANSC_DPLL_ENABLE;
2702 sel = TRANSC_DPLLB_SEL;
2703 break;
d64311ab 2704 }
ee7b9f93
JB		 2705 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2706 temp |= sel;
2707 else
2708 temp &= ~sel;
c98e9dcf 2709 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2710 }
5eddb70b 2711
d9b6cb56
JB		 2712 /* set transcoder timing, panel must allow it */
2713 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 2714 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2715 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2716 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 2717
5eddb70b
CW		 2718 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2719 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2720 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 2721 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 2722
f57e1e3a
ED		 2723 if (!IS_HASWELL(dev))
2724 intel_fdi_normal_train(crtc);
5e84e1a4 2725
c98e9dcf
JB		 2726 /* For PCH DP, enable TRANS_DP_CTL */
2727 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 2728 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2729 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 2730 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 2731 reg = TRANS_DP_CTL(pipe);
2732 temp = I915_READ(reg);
2733 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 2734 TRANS_DP_SYNC_MASK |
2735 TRANS_DP_BPC_MASK);
5eddb70b
CW		 2736 temp |= (TRANS_DP_OUTPUT_ENABLE |
2737 TRANS_DP_ENH_FRAMING);
9325c9f0 2738 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 2739
2740 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 2741 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 2742 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 2743 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 2744
2745 switch (intel_trans_dp_port_sel(crtc)) {
2746 case PCH_DP_B:
5eddb70b 2747 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 2748 break;
2749 case PCH_DP_C:
5eddb70b 2750 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 2751 break;
2752 case PCH_DP_D:
5eddb70b 2753 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 2754 break;
2755 default:
2756 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
5eddb70b 2757 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 2758 break;
32f9d658 2759 }
2c07245f 2760
5eddb70b 2761 I915_WRITE(reg, temp);
6be4a607 2762 }
b52eb4dc 2763
040484af 2764 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 2765}
2766
ee7b9f93
JB		 2767static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
2768{
2769 struct intel_pch_pll *pll = intel_crtc->pch_pll;
2770
2771 if (pll == NULL)
2772 return;
2773
2774 if (pll->refcount == 0) {
2775 WARN(1, "bad PCH PLL refcount\n");
2776 return;
2777 }
2778
2779 --pll->refcount;
2780 intel_crtc->pch_pll = NULL;
2781}
2782
2783static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
2784{
2785 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
2786 struct intel_pch_pll *pll;
2787 int i;
2788
2789 pll = intel_crtc->pch_pll;
2790 if (pll) {
2791 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
2792 intel_crtc->base.base.id, pll->pll_reg);
2793 goto prepare;
2794 }
2795
2796 for (i = 0; i < dev_priv->num_pch_pll; i++) {
2797 pll = &dev_priv->pch_plls[i];
2798
2799 /* Only want to check enabled timings first */
2800 if (pll->refcount == 0)
2801 continue;
2802
2803 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
2804 fp == I915_READ(pll->fp0_reg)) {
2805 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
2806 intel_crtc->base.base.id,
2807 pll->pll_reg, pll->refcount, pll->active);
2808
2809 goto found;
2810 }
2811 }
2812
2813 /* Ok no matching timings, maybe there's a free one? */
2814 for (i = 0; i < dev_priv->num_pch_pll; i++) {
2815 pll = &dev_priv->pch_plls[i];
2816 if (pll->refcount == 0) {
2817 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
2818 intel_crtc->base.base.id, pll->pll_reg);
2819 goto found;
2820 }
2821 }
2822
2823 return NULL;
2824
2825found:
2826 intel_crtc->pch_pll = pll;
2827 pll->refcount++;
2828 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
2829prepare: /* separate function? */
2830 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 2831
e04c7350
CW		 2832 /* Wait for the clocks to stabilize before rewriting the regs */
2833 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 2834 POSTING_READ(pll->pll_reg);
2835 udelay(150);
e04c7350
CW		 2836
2837 I915_WRITE(pll->fp0_reg, fp);
2838 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 2839 pll->on = false;
2840 return pll;
2841}
2842
d4270e57
JB		 2843void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
2844{
2845 struct drm_i915_private *dev_priv = dev->dev_private;
2846 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
2847 u32 temp;
2848
2849 temp = I915_READ(dslreg);
2850 udelay(500);
2851 if (wait_for(I915_READ(dslreg) != temp, 5)) {
2852 /* Without this, mode sets may fail silently on FDI */
2853 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
2854 udelay(250);
2855 I915_WRITE(tc2reg, 0);
2856 if (wait_for(I915_READ(dslreg) != temp, 5))
2857 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
2858 }
2859}
2860
f67a559d
JB		 2861static void ironlake_crtc_enable(struct drm_crtc *crtc)
2862{
2863 struct drm_device *dev = crtc->dev;
2864 struct drm_i915_private *dev_priv = dev->dev_private;
2865 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2866 int pipe = intel_crtc->pipe;
2867 int plane = intel_crtc->plane;
2868 u32 temp;
2869 bool is_pch_port;
2870
2871 if (intel_crtc->active)
2872 return;
2873
2874 intel_crtc->active = true;
2875 intel_update_watermarks(dev);
2876
2877 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2878 temp = I915_READ(PCH_LVDS);
2879 if ((temp & LVDS_PORT_EN) == 0)
2880 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2881 }
2882
2883 is_pch_port = intel_crtc_driving_pch(crtc);
2884
2885 if (is_pch_port)
357555c0 2886 ironlake_fdi_pll_enable(crtc);
f67a559d
JB		 2887 else
2888 ironlake_fdi_disable(crtc);
2889
2890 /* Enable panel fitting for LVDS */
2891 if (dev_priv->pch_pf_size &&
2892 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2893 /* Force use of hard-coded filter coefficients
2894 * as some pre-programmed values are broken,
2895 * e.g. x201.
2896 */
9db4a9c7
JB		 2897 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2898 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2899 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 2900 }
2901
9c54c0dd
JB		 2902 /*
2903 * On ILK+ LUT must be loaded before the pipe is running but with
2904 * clocks enabled
2905 */
2906 intel_crtc_load_lut(crtc);
2907
f67a559d
JB		 2908 intel_enable_pipe(dev_priv, pipe, is_pch_port);
2909 intel_enable_plane(dev_priv, plane, pipe);
2910
2911 if (is_pch_port)
2912 ironlake_pch_enable(crtc);
c98e9dcf 2913
d1ebd816 2914 mutex_lock(&dev->struct_mutex);
bed4a673 2915 intel_update_fbc(dev);
d1ebd816
BW		 2916 mutex_unlock(&dev->struct_mutex);
2917
6b383a7f 2918 intel_crtc_update_cursor(crtc, true);
6be4a607
JB		 2919}
2920
2921static void ironlake_crtc_disable(struct drm_crtc *crtc)
2922{
2923 struct drm_device *dev = crtc->dev;
2924 struct drm_i915_private *dev_priv = dev->dev_private;
2925 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2926 int pipe = intel_crtc->pipe;
2927 int plane = intel_crtc->plane;
5eddb70b 2928 u32 reg, temp;
b52eb4dc 2929
f7abfe8b
CW		 2930 if (!intel_crtc->active)
2931 return;
2932
e6c3a2a6 2933 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 2934 drm_vblank_off(dev, pipe);
6b383a7f 2935 intel_crtc_update_cursor(crtc, false);
5eddb70b 2936
b24e7179 2937 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 2938
973d04f9
CW		 2939 if (dev_priv->cfb_plane == plane)
2940 intel_disable_fbc(dev);
2c07245f 2941
b24e7179 2942 intel_disable_pipe(dev_priv, pipe);
32f9d658 2943
6be4a607 2944 /* Disable PF */
9db4a9c7
JB		 2945 I915_WRITE(PF_CTL(pipe), 0);
2946 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 2947
0fc932b8 2948 ironlake_fdi_disable(crtc);
2c07245f 2949
47a05eca
JB		 2950 /* This is a horrible layering violation; we should be doing this in
2951 * the connector/encoder ->prepare instead, but we don't always have
2952 * enough information there about the config to know whether it will
2953 * actually be necessary or just cause undesired flicker.
2954 */
2955 intel_disable_pch_ports(dev_priv, pipe);
249c0e64 2956
040484af 2957 intel_disable_transcoder(dev_priv, pipe);
913d8d11 2958
6be4a607
JB		 2959 if (HAS_PCH_CPT(dev)) {
2960 /* disable TRANS_DP_CTL */
5eddb70b
CW		 2961 reg = TRANS_DP_CTL(pipe);
2962 temp = I915_READ(reg);
2963 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 2964 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 2965 I915_WRITE(reg, temp);
6be4a607
JB		 2966
2967 /* disable DPLL_SEL */
2968 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 2969 switch (pipe) {
2970 case 0:
d64311ab 2971 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 2972 break;
2973 case 1:
6be4a607 2974 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 2975 break;
2976 case 2:
4b645f14 2977 /* C shares PLL A or B */
d64311ab 2978 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 2979 break;
2980 default:
2981 BUG(); /* wtf */
2982 }
6be4a607 2983 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 2984 }
e3421a18 2985
6be4a607 2986 /* disable PCH DPLL */
ee7b9f93 2987 intel_disable_pch_pll(intel_crtc);
8db9d77b 2988
6be4a607 2989 /* Switch from PCDclk to Rawclk */
5eddb70b
CW		 2990 reg = FDI_RX_CTL(pipe);
2991 temp = I915_READ(reg);
2992 I915_WRITE(reg, temp & ~FDI_PCDCLK);
8db9d77b 2993
6be4a607 2994 /* Disable CPU FDI TX PLL */
5eddb70b
CW		 2995 reg = FDI_TX_CTL(pipe);
2996 temp = I915_READ(reg);
2997 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2998
2999 POSTING_READ(reg);
6be4a607 3000 udelay(100);
8db9d77b 3001
5eddb70b
CW		 3002 reg = FDI_RX_CTL(pipe);
3003 temp = I915_READ(reg);
3004 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2c07245f 3005
6be4a607 3006 /* Wait for the clocks to turn off. */
5eddb70b 3007 POSTING_READ(reg);
6be4a607 3008 udelay(100);
6b383a7f 3009
f7abfe8b 3010 intel_crtc->active = false;
6b383a7f 3011 intel_update_watermarks(dev);
d1ebd816
BW		 3012
3013 mutex_lock(&dev->struct_mutex);
6b383a7f 3014 intel_update_fbc(dev);
d1ebd816 3015 mutex_unlock(&dev->struct_mutex);
6be4a607 3016}
1b3c7a47 3017
6be4a607
JB		 3018static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3019{
3020 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3021 int pipe = intel_crtc->pipe;
3022 int plane = intel_crtc->plane;
8db9d77b 3023
6be4a607
JB		 3024 /* XXX: When our outputs are all unaware of DPMS modes other than off
3025 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3026 */
3027 switch (mode) {
3028 case DRM_MODE_DPMS_ON:
3029 case DRM_MODE_DPMS_STANDBY:
3030 case DRM_MODE_DPMS_SUSPEND:
3031 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3032 ironlake_crtc_enable(crtc);
3033 break;
1b3c7a47 3034
6be4a607
JB		 3035 case DRM_MODE_DPMS_OFF:
3036 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3037 ironlake_crtc_disable(crtc);
2c07245f
ZW		 3038 break;
3039 }
3040}
3041
ee7b9f93
JB		 3042static void ironlake_crtc_off(struct drm_crtc *crtc)
3043{
3044 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3045 intel_put_pch_pll(intel_crtc);
3046}
3047
02e792fb
DV		 3048static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3049{
02e792fb 3050 if (!enable && intel_crtc->overlay) {
23f09ce3 3051 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3052 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3053
23f09ce3 3054 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3055 dev_priv->mm.interruptible = false;
3056 (void) intel_overlay_switch_off(intel_crtc->overlay);
3057 dev_priv->mm.interruptible = true;
23f09ce3 3058 mutex_unlock(&dev->struct_mutex);
02e792fb 3059 }
02e792fb 3060
5dcdbcb0
CW		 3061 /* Let userspace switch the overlay on again. In most cases userspace
3062 * has to recompute where to put it anyway.
3063 */
02e792fb
DV		 3064}
3065
0b8765c6 3066static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3067{
3068 struct drm_device *dev = crtc->dev;
79e53945
JB		 3069 struct drm_i915_private *dev_priv = dev->dev_private;
3070 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3071 int pipe = intel_crtc->pipe;
80824003 3072 int plane = intel_crtc->plane;
79e53945 3073
f7abfe8b
CW		 3074 if (intel_crtc->active)
3075 return;
3076
3077 intel_crtc->active = true;
6b383a7f
CW		 3078 intel_update_watermarks(dev);
3079
63d7bbe9 3080 intel_enable_pll(dev_priv, pipe);
040484af 3081 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3082 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3083
0b8765c6 3084 intel_crtc_load_lut(crtc);
bed4a673 3085 intel_update_fbc(dev);
79e53945 3086
0b8765c6
JB		 3087 /* Give the overlay scaler a chance to enable if it's on this pipe */
3088 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3089 intel_crtc_update_cursor(crtc, true);
0b8765c6 3090}
79e53945 3091
0b8765c6
JB		 3092static void i9xx_crtc_disable(struct drm_crtc *crtc)
3093{
3094 struct drm_device *dev = crtc->dev;
3095 struct drm_i915_private *dev_priv = dev->dev_private;
3096 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3097 int pipe = intel_crtc->pipe;
3098 int plane = intel_crtc->plane;
b690e96c 3099
f7abfe8b
CW		 3100 if (!intel_crtc->active)
3101 return;
3102
0b8765c6 3103 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3104 intel_crtc_wait_for_pending_flips(crtc);
3105 drm_vblank_off(dev, pipe);
0b8765c6 3106 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3107 intel_crtc_update_cursor(crtc, false);
0b8765c6 3108
973d04f9
CW		 3109 if (dev_priv->cfb_plane == plane)
3110 intel_disable_fbc(dev);
79e53945 3111
b24e7179 3112 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3113 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3114 intel_disable_pll(dev_priv, pipe);
0b8765c6 3115
f7abfe8b 3116 intel_crtc->active = false;
6b383a7f
CW		 3117 intel_update_fbc(dev);
3118 intel_update_watermarks(dev);
0b8765c6
JB		 3119}
3120
3121static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3122{
3123 /* XXX: When our outputs are all unaware of DPMS modes other than off
3124 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3125 */
3126 switch (mode) {
3127 case DRM_MODE_DPMS_ON:
3128 case DRM_MODE_DPMS_STANDBY:
3129 case DRM_MODE_DPMS_SUSPEND:
3130 i9xx_crtc_enable(crtc);
3131 break;
3132 case DRM_MODE_DPMS_OFF:
3133 i9xx_crtc_disable(crtc);
79e53945
JB		 3134 break;
3135 }
2c07245f
ZW		 3136}
3137
ee7b9f93
JB		 3138static void i9xx_crtc_off(struct drm_crtc *crtc)
3139{
3140}
3141
2c07245f
ZW		 3142/**
3143 * Sets the power management mode of the pipe and plane.
2c07245f
ZW		 3144 */
3145static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3146{
3147 struct drm_device *dev = crtc->dev;
e70236a8 3148 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f
ZW		 3149 struct drm_i915_master_private *master_priv;
3150 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3151 int pipe = intel_crtc->pipe;
3152 bool enabled;
3153
032d2a0d
CW		 3154 if (intel_crtc->dpms_mode == mode)
3155 return;
3156
65655d4a 3157 intel_crtc->dpms_mode = mode;
debcaddc 3158
e70236a8 3159 dev_priv->display.dpms(crtc, mode);
79e53945
JB		 3160
3161 if (!dev->primary->master)
3162 return;
3163
3164 master_priv = dev->primary->master->driver_priv;
3165 if (!master_priv->sarea_priv)
3166 return;
3167
3168 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3169
3170 switch (pipe) {
3171 case 0:
3172 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3173 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3174 break;
3175 case 1:
3176 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3177 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3178 break;
3179 default:
9db4a9c7 3180 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3181 break;
3182 }
79e53945
JB		 3183}
3184
cdd59983
CW		 3185static void intel_crtc_disable(struct drm_crtc *crtc)
3186{
3187 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3188 struct drm_device *dev = crtc->dev;
ee7b9f93 3189 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983
CW		 3190
3191 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
ee7b9f93
JB		 3192 dev_priv->display.off(crtc);
3193
931872fc
CW		 3194 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3195 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3196
3197 if (crtc->fb) {
3198 mutex_lock(&dev->struct_mutex);
1690e1eb 3199 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983
CW		 3200 mutex_unlock(&dev->struct_mutex);
3201 }
3202}
3203
7e7d76c3
JB		 3204/* Prepare for a mode set.
3205 *
3206 * Note we could be a lot smarter here. We need to figure out which outputs
3207 * will be enabled, which disabled (in short, how the config will changes)
3208 * and perform the minimum necessary steps to accomplish that, e.g. updating
3209 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3210 * panel fitting is in the proper state, etc.
3211 */
3212static void i9xx_crtc_prepare(struct drm_crtc *crtc)
79e53945 3213{
7e7d76c3 3214 i9xx_crtc_disable(crtc);
79e53945
JB		 3215}
3216
7e7d76c3 3217static void i9xx_crtc_commit(struct drm_crtc *crtc)
79e53945 3218{
7e7d76c3 3219 i9xx_crtc_enable(crtc);
7e7d76c3
JB		 3220}
3221
3222static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3223{
7e7d76c3 3224 ironlake_crtc_disable(crtc);
7e7d76c3
JB		 3225}
3226
3227static void ironlake_crtc_commit(struct drm_crtc *crtc)
3228{
7e7d76c3 3229 ironlake_crtc_enable(crtc);
79e53945
JB		 3230}
3231
0206e353 3232void intel_encoder_prepare(struct drm_encoder *encoder)
79e53945
JB		 3233{
3234 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3235 /* lvds has its own version of prepare see intel_lvds_prepare */
3236 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3237}
3238
0206e353 3239void intel_encoder_commit(struct drm_encoder *encoder)
79e53945
JB		 3240{
3241 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
d4270e57 3242 struct drm_device *dev = encoder->dev;
d47d7cb8 3243 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
d4270e57 3244
79e53945
JB		 3245 /* lvds has its own version of commit see intel_lvds_commit */
3246 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
d4270e57
JB		 3247
3248 if (HAS_PCH_CPT(dev))
3249 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
79e53945
JB		 3250}
3251
ea5b213a
CW		 3252void intel_encoder_destroy(struct drm_encoder *encoder)
3253{
4ef69c7a 3254 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3255
ea5b213a
CW		 3256 drm_encoder_cleanup(encoder);
3257 kfree(intel_encoder);
3258}
3259
79e53945
JB		 3260static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3261 struct drm_display_mode *mode,
3262 struct drm_display_mode *adjusted_mode)
3263{
2c07245f 3264 struct drm_device *dev = crtc->dev;
89749350 3265
bad720ff 3266 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3267 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3268 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3269 return false;
2c07245f 3270 }
89749350 3271
f9bef081
DV		 3272 /* All interlaced capable intel hw wants timings in frames. Note though
3273 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3274 * timings, so we need to be careful not to clobber these.*/
3275 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3276 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3277
79e53945
JB		 3278 return true;
3279}
3280
25eb05fc
JB		 3281static int valleyview_get_display_clock_speed(struct drm_device *dev)
3282{
3283 return 400000; /* FIXME */
3284}
3285
e70236a8
JB		 3286static int i945_get_display_clock_speed(struct drm_device *dev)
3287{
3288 return 400000;
3289}
79e53945 3290
e70236a8 3291static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3292{
e70236a8
JB		 3293 return 333000;
3294}
79e53945 3295
e70236a8
JB		 3296static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3297{
3298 return 200000;
3299}
79e53945 3300
e70236a8
JB		 3301static int i915gm_get_display_clock_speed(struct drm_device *dev)
3302{
3303 u16 gcfgc = 0;
79e53945 3304
e70236a8
JB		 3305 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3306
3307 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3308 return 133000;
3309 else {
3310 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3311 case GC_DISPLAY_CLOCK_333_MHZ:
3312 return 333000;
3313 default:
3314 case GC_DISPLAY_CLOCK_190_200_MHZ:
3315 return 190000;
79e53945 3316 }
e70236a8
JB		 3317 }
3318}
3319
3320static int i865_get_display_clock_speed(struct drm_device *dev)
3321{
3322 return 266000;
3323}
3324
3325static int i855_get_display_clock_speed(struct drm_device *dev)
3326{
3327 u16 hpllcc = 0;
3328 /* Assume that the hardware is in the high speed state. This
3329 * should be the default.
3330 */
3331 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3332 case GC_CLOCK_133_200:
3333 case GC_CLOCK_100_200:
3334 return 200000;
3335 case GC_CLOCK_166_250:
3336 return 250000;
3337 case GC_CLOCK_100_133:
79e53945 3338 return 133000;
e70236a8 3339 }
79e53945 3340
e70236a8
JB		 3341 /* Shouldn't happen */
3342 return 0;
3343}
79e53945 3344
e70236a8
JB		 3345static int i830_get_display_clock_speed(struct drm_device *dev)
3346{
3347 return 133000;
79e53945
JB		 3348}
3349
2c07245f
ZW		 3350struct fdi_m_n {
3351 u32 tu;
3352 u32 gmch_m;
3353 u32 gmch_n;
3354 u32 link_m;
3355 u32 link_n;
3356};
3357
3358static void
3359fdi_reduce_ratio(u32 *num, u32 *den)
3360{
3361 while (*num > 0xffffff || *den > 0xffffff) {
3362 *num >>= 1;
3363 *den >>= 1;
3364 }
3365}
3366
2c07245f 3367static void
f2b115e6
AJ		 3368ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3369 int link_clock, struct fdi_m_n *m_n)
2c07245f 3370{
2c07245f
ZW		 3371 m_n->tu = 64; /* default size */
3372
22ed1113
CW		 3373 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3374 m_n->gmch_m = bits_per_pixel * pixel_clock;
3375 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3376 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3377
22ed1113
CW		 3378 m_n->link_m = pixel_clock;
3379 m_n->link_n = link_clock;
2c07245f
ZW		 3380 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3381}
3382
a7615030
CW		 3383static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3384{
72bbe58c
KP		 3385 if (i915_panel_use_ssc >= 0)
3386 return i915_panel_use_ssc != 0;
3387 return dev_priv->lvds_use_ssc
435793df 3388 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 3389}
3390
5a354204
JB		 3391/**
3392 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3393 * @crtc: CRTC structure
3b5c78a3 3394 * @mode: requested mode
5a354204
JB		 3395 *
3396 * A pipe may be connected to one or more outputs. Based on the depth of the
3397 * attached framebuffer, choose a good color depth to use on the pipe.
3398 *
3399 * If possible, match the pipe depth to the fb depth. In some cases, this
3400 * isn't ideal, because the connected output supports a lesser or restricted
3401 * set of depths. Resolve that here:
3402 * LVDS typically supports only 6bpc, so clamp down in that case
3403 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3404 * Displays may support a restricted set as well, check EDID and clamp as
3405 * appropriate.
3b5c78a3 3406 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 3407 *
3408 * RETURNS:
3409 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3410 * true if they don't match).
3411 */
3412static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3b5c78a3
AJ		 3413 unsigned int *pipe_bpp,
3414 struct drm_display_mode *mode)
5a354204
JB		 3415{
3416 struct drm_device *dev = crtc->dev;
3417 struct drm_i915_private *dev_priv = dev->dev_private;
3418 struct drm_encoder *encoder;
3419 struct drm_connector *connector;
3420 unsigned int display_bpc = UINT_MAX, bpc;
3421
3422 /* Walk the encoders & connectors on this crtc, get min bpc */
3423 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3424 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3425
3426 if (encoder->crtc != crtc)
3427 continue;
3428
3429 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3430 unsigned int lvds_bpc;
3431
3432 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3433 LVDS_A3_POWER_UP)
3434 lvds_bpc = 8;
3435 else
3436 lvds_bpc = 6;
3437
3438 if (lvds_bpc < display_bpc) {
82820490 3439 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 3440 display_bpc = lvds_bpc;
3441 }
3442 continue;
3443 }
3444
3445 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
3446 /* Use VBT settings if we have an eDP panel */
3447 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
3448
3449 if (edp_bpc < display_bpc) {
82820490 3450 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
5a354204
JB		 3451 display_bpc = edp_bpc;
3452 }
3453 continue;
3454 }
3455
3456 /* Not one of the known troublemakers, check the EDID */
3457 list_for_each_entry(connector, &dev->mode_config.connector_list,
3458 head) {
3459 if (connector->encoder != encoder)
3460 continue;
3461
62ac41a6
JB		 3462 /* Don't use an invalid EDID bpc value */
3463 if (connector->display_info.bpc &&
3464 connector->display_info.bpc < display_bpc) {
82820490 3465 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 3466 display_bpc = connector->display_info.bpc;
3467 }
3468 }
3469
3470 /*
3471 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3472 * through, clamp it down. (Note: >12bpc will be caught below.)
3473 */
3474 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3475 if (display_bpc > 8 && display_bpc < 12) {
82820490 3476 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 3477 display_bpc = 12;
3478 } else {
82820490 3479 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 3480 display_bpc = 8;
3481 }
3482 }
3483 }
3484
3b5c78a3
AJ		 3485 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3486 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3487 display_bpc = 6;
3488 }
3489
5a354204
JB		 3490 /*
3491 * We could just drive the pipe at the highest bpc all the time and
3492 * enable dithering as needed, but that costs bandwidth. So choose
3493 * the minimum value that expresses the full color range of the fb but
3494 * also stays within the max display bpc discovered above.
3495 */
3496
3497 switch (crtc->fb->depth) {
3498 case 8:
3499 bpc = 8; /* since we go through a colormap */
3500 break;
3501 case 15:
3502 case 16:
3503 bpc = 6; /* min is 18bpp */
3504 break;
3505 case 24:
578393cd 3506 bpc = 8;
5a354204
JB		 3507 break;
3508 case 30:
578393cd 3509 bpc = 10;
5a354204
JB		 3510 break;
3511 case 48:
578393cd 3512 bpc = 12;
5a354204
JB		 3513 break;
3514 default:
3515 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3516 bpc = min((unsigned int)8, display_bpc);
3517 break;
3518 }
3519
578393cd
KP		 3520 display_bpc = min(display_bpc, bpc);
3521
82820490
AJ		 3522 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3523 bpc, display_bpc);
5a354204 3524
578393cd 3525 *pipe_bpp = display_bpc * 3;
5a354204
JB		 3526
3527 return display_bpc != bpc;
3528}
3529
c65d77d8
JB		 3530static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3531{
3532 struct drm_device *dev = crtc->dev;
3533 struct drm_i915_private *dev_priv = dev->dev_private;
3534 int refclk;
3535
3536 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3537 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3538 refclk = dev_priv->lvds_ssc_freq * 1000;
3539 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3540 refclk / 1000);
3541 } else if (!IS_GEN2(dev)) {
3542 refclk = 96000;
3543 } else {
3544 refclk = 48000;
3545 }
3546
3547 return refclk;
3548}
3549
3550static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3551 intel_clock_t *clock)
3552{
3553 /* SDVO TV has fixed PLL values depend on its clock range,
3554 this mirrors vbios setting. */
3555 if (adjusted_mode->clock >= 100000
3556 && adjusted_mode->clock < 140500) {
3557 clock->p1 = 2;
3558 clock->p2 = 10;
3559 clock->n = 3;
3560 clock->m1 = 16;
3561 clock->m2 = 8;
3562 } else if (adjusted_mode->clock >= 140500
3563 && adjusted_mode->clock <= 200000) {
3564 clock->p1 = 1;
3565 clock->p2 = 10;
3566 clock->n = 6;
3567 clock->m1 = 12;
3568 clock->m2 = 8;
3569 }
3570}
3571
a7516a05
JB		 3572static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3573 intel_clock_t *clock,
3574 intel_clock_t *reduced_clock)
3575{
3576 struct drm_device *dev = crtc->dev;
3577 struct drm_i915_private *dev_priv = dev->dev_private;
3578 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3579 int pipe = intel_crtc->pipe;
3580 u32 fp, fp2 = 0;
3581
3582 if (IS_PINEVIEW(dev)) {
3583 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3584 if (reduced_clock)
3585 fp2 = (1 << reduced_clock->n) << 16 |
3586 reduced_clock->m1 << 8 | reduced_clock->m2;
3587 } else {
3588 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3589 if (reduced_clock)
3590 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3591 reduced_clock->m2;
3592 }
3593
3594 I915_WRITE(FP0(pipe), fp);
3595
3596 intel_crtc->lowfreq_avail = false;
3597 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3598 reduced_clock && i915_powersave) {
3599 I915_WRITE(FP1(pipe), fp2);
3600 intel_crtc->lowfreq_avail = true;
3601 } else {
3602 I915_WRITE(FP1(pipe), fp);
3603 }
3604}
3605
93e537a1
DV		 3606static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3607 struct drm_display_mode *adjusted_mode)
3608{
3609 struct drm_device *dev = crtc->dev;
3610 struct drm_i915_private *dev_priv = dev->dev_private;
3611 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3612 int pipe = intel_crtc->pipe;
284d5df5 3613 u32 temp;
93e537a1
DV		 3614
3615 temp = I915_READ(LVDS);
3616 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3617 if (pipe == 1) {
3618 temp |= LVDS_PIPEB_SELECT;
3619 } else {
3620 temp &= ~LVDS_PIPEB_SELECT;
3621 }
3622 /* set the corresponsding LVDS_BORDER bit */
3623 temp |= dev_priv->lvds_border_bits;
3624 /* Set the B0-B3 data pairs corresponding to whether we're going to
3625 * set the DPLLs for dual-channel mode or not.
3626 */
3627 if (clock->p2 == 7)
3628 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3629 else
3630 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3631
3632 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3633 * appropriately here, but we need to look more thoroughly into how
3634 * panels behave in the two modes.
3635 */
3636 /* set the dithering flag on LVDS as needed */
3637 if (INTEL_INFO(dev)->gen >= 4) {
3638 if (dev_priv->lvds_dither)
3639 temp |= LVDS_ENABLE_DITHER;
3640 else
3641 temp &= ~LVDS_ENABLE_DITHER;
3642 }
284d5df5 3643 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
93e537a1 3644 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 3645 temp |= LVDS_HSYNC_POLARITY;
93e537a1 3646 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 3647 temp |= LVDS_VSYNC_POLARITY;
93e537a1
DV		 3648 I915_WRITE(LVDS, temp);
3649}
3650
eb1cbe48
DV		 3651static void i9xx_update_pll(struct drm_crtc *crtc,
3652 struct drm_display_mode *mode,
3653 struct drm_display_mode *adjusted_mode,
3654 intel_clock_t *clock, intel_clock_t *reduced_clock,
3655 int num_connectors)
3656{
3657 struct drm_device *dev = crtc->dev;
3658 struct drm_i915_private *dev_priv = dev->dev_private;
3659 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3660 int pipe = intel_crtc->pipe;
3661 u32 dpll;
3662 bool is_sdvo;
3663
3664 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
3665 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
3666
3667 dpll = DPLL_VGA_MODE_DIS;
3668
3669 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3670 dpll |= DPLLB_MODE_LVDS;
3671 else
3672 dpll |= DPLLB_MODE_DAC_SERIAL;
3673 if (is_sdvo) {
3674 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3675 if (pixel_multiplier > 1) {
3676 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3677 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3678 }
3679 dpll |= DPLL_DVO_HIGH_SPEED;
3680 }
3681 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
3682 dpll |= DPLL_DVO_HIGH_SPEED;
3683
3684 /* compute bitmask from p1 value */
3685 if (IS_PINEVIEW(dev))
3686 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3687 else {
3688 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3689 if (IS_G4X(dev) && reduced_clock)
3690 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3691 }
3692 switch (clock->p2) {
3693 case 5:
3694 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3695 break;
3696 case 7:
3697 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3698 break;
3699 case 10:
3700 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3701 break;
3702 case 14:
3703 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3704 break;
3705 }
3706 if (INTEL_INFO(dev)->gen >= 4)
3707 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3708
3709 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3710 dpll |= PLL_REF_INPUT_TVCLKINBC;
3711 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3712 /* XXX: just matching BIOS for now */
3713 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3714 dpll |= 3;
3715 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3716 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
3717 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3718 else
3719 dpll |= PLL_REF_INPUT_DREFCLK;
3720
3721 dpll |= DPLL_VCO_ENABLE;
3722 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
3723 POSTING_READ(DPLL(pipe));
3724 udelay(150);
3725
3726 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3727 * This is an exception to the general rule that mode_set doesn't turn
3728 * things on.
3729 */
3730 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3731 intel_update_lvds(crtc, clock, adjusted_mode);
3732
3733 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
3734 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3735
3736 I915_WRITE(DPLL(pipe), dpll);
3737
3738 /* Wait for the clocks to stabilize. */
3739 POSTING_READ(DPLL(pipe));
3740 udelay(150);
3741
3742 if (INTEL_INFO(dev)->gen >= 4) {
3743 u32 temp = 0;
3744 if (is_sdvo) {
3745 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
3746 if (temp > 1)
3747 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
3748 else
3749 temp = 0;
3750 }
3751 I915_WRITE(DPLL_MD(pipe), temp);
3752 } else {
3753 /* The pixel multiplier can only be updated once the
3754 * DPLL is enabled and the clocks are stable.
3755 *
3756 * So write it again.
3757 */
3758 I915_WRITE(DPLL(pipe), dpll);
3759 }
3760}
3761
3762static void i8xx_update_pll(struct drm_crtc *crtc,
3763 struct drm_display_mode *adjusted_mode,
3764 intel_clock_t *clock,
3765 int num_connectors)
3766{
3767 struct drm_device *dev = crtc->dev;
3768 struct drm_i915_private *dev_priv = dev->dev_private;
3769 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3770 int pipe = intel_crtc->pipe;
3771 u32 dpll;
3772
3773 dpll = DPLL_VGA_MODE_DIS;
3774
3775 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3776 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3777 } else {
3778 if (clock->p1 == 2)
3779 dpll |= PLL_P1_DIVIDE_BY_TWO;
3780 else
3781 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3782 if (clock->p2 == 4)
3783 dpll |= PLL_P2_DIVIDE_BY_4;
3784 }
3785
3786 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3787 /* XXX: just matching BIOS for now */
3788 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3789 dpll |= 3;
3790 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3791 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
3792 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3793 else
3794 dpll |= PLL_REF_INPUT_DREFCLK;
3795
3796 dpll |= DPLL_VCO_ENABLE;
3797 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
3798 POSTING_READ(DPLL(pipe));
3799 udelay(150);
3800
3801 I915_WRITE(DPLL(pipe), dpll);
3802
3803 /* Wait for the clocks to stabilize. */
3804 POSTING_READ(DPLL(pipe));
3805 udelay(150);
3806
3807 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3808 * This is an exception to the general rule that mode_set doesn't turn
3809 * things on.
3810 */
3811 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3812 intel_update_lvds(crtc, clock, adjusted_mode);
3813
3814 /* The pixel multiplier can only be updated once the
3815 * DPLL is enabled and the clocks are stable.
3816 *
3817 * So write it again.
3818 */
3819 I915_WRITE(DPLL(pipe), dpll);
3820}
3821
f564048e
EA		 3822static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
3823 struct drm_display_mode *mode,
3824 struct drm_display_mode *adjusted_mode,
3825 int x, int y,
3826 struct drm_framebuffer *old_fb)
79e53945
JB		 3827{
3828 struct drm_device *dev = crtc->dev;
3829 struct drm_i915_private *dev_priv = dev->dev_private;
3830 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3831 int pipe = intel_crtc->pipe;
80824003 3832 int plane = intel_crtc->plane;
c751ce4f 3833 int refclk, num_connectors = 0;
652c393a 3834 intel_clock_t clock, reduced_clock;
eb1cbe48
DV		 3835 u32 dspcntr, pipeconf, vsyncshift;
3836 bool ok, has_reduced_clock = false, is_sdvo = false;
3837 bool is_lvds = false, is_tv = false, is_dp = false;
79e53945 3838 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 3839 struct intel_encoder *encoder;
d4906093 3840 const intel_limit_t *limit;
5c3b82e2 3841 int ret;
79e53945 3842
5eddb70b
CW		 3843 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3844 if (encoder->base.crtc != crtc)
79e53945
JB		 3845 continue;
3846
5eddb70b 3847 switch (encoder->type) {
79e53945
JB		 3848 case INTEL_OUTPUT_LVDS:
3849 is_lvds = true;
3850 break;
3851 case INTEL_OUTPUT_SDVO:
7d57382e 3852 case INTEL_OUTPUT_HDMI:
79e53945 3853 is_sdvo = true;
5eddb70b 3854 if (encoder->needs_tv_clock)
e2f0ba97 3855 is_tv = true;
79e53945 3856 break;
79e53945
JB		 3857 case INTEL_OUTPUT_TVOUT:
3858 is_tv = true;
3859 break;
a4fc5ed6
KP		 3860 case INTEL_OUTPUT_DISPLAYPORT:
3861 is_dp = true;
3862 break;
79e53945 3863 }
43565a06 3864
c751ce4f 3865 num_connectors++;
79e53945
JB		 3866 }
3867
c65d77d8 3868 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 3869
d4906093
ML		 3870 /*
3871 * Returns a set of divisors for the desired target clock with the given
3872 * refclk, or FALSE. The returned values represent the clock equation:
3873 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3874 */
1b894b59 3875 limit = intel_limit(crtc, refclk);
cec2f356
SP		 3876 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
3877 &clock);
79e53945
JB		 3878 if (!ok) {
3879 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 3880 return -EINVAL;
79e53945
JB		 3881 }
3882
cda4b7d3 3883 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 3884 intel_crtc_update_cursor(crtc, true);
cda4b7d3 3885
ddc9003c 3886 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 3887 /*
3888 * Ensure we match the reduced clock's P to the target clock.
3889 * If the clocks don't match, we can't switch the display clock
3890 * by using the FP0/FP1. In such case we will disable the LVDS
3891 * downclock feature.
3892 */
ddc9003c 3893 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 3894 dev_priv->lvds_downclock,
3895 refclk,
cec2f356 3896 &clock,
5eddb70b 3897 &reduced_clock);
7026d4ac
ZW		 3898 }
3899
c65d77d8
JB		 3900 if (is_sdvo && is_tv)
3901 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 3902
a7516a05
JB		 3903 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
3904 &reduced_clock : NULL);
79e53945 3905
eb1cbe48
DV		 3906 if (IS_GEN2(dev))
3907 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
79e53945 3908 else
eb1cbe48
DV		 3909 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
3910 has_reduced_clock ? &reduced_clock : NULL,
3911 num_connectors);
79e53945
JB		 3912
3913 /* setup pipeconf */
5eddb70b 3914 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 3915
3916 /* Set up the display plane register */
3917 dspcntr = DISPPLANE_GAMMA_ENABLE;
3918
929c77fb
EA		 3919 if (pipe == 0)
3920 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3921 else
3922 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 3923
a6c45cf0 3924 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 3925 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3926 * core speed.
3927 *
3928 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3929 * pipe == 0 check?
3930 */
e70236a8
JB		 3931 if (mode->clock >
3932 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 3933 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 3934 else
5eddb70b 3935 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 3936 }
3937
3b5c78a3
AJ		 3938 /* default to 8bpc */
3939 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
3940 if (is_dp) {
3941 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3942 pipeconf |= PIPECONF_BPP_6 |
3943 PIPECONF_DITHER_EN |
3944 PIPECONF_DITHER_TYPE_SP;
3945 }
3946 }
3947
28c97730 3948 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 3949 drm_mode_debug_printmodeline(mode);
3950
a7516a05
JB		 3951 if (HAS_PIPE_CXSR(dev)) {
3952 if (intel_crtc->lowfreq_avail) {
28c97730 3953 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 3954 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 3955 } else {
28c97730 3956 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 3957 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3958 }
3959 }
3960
617cf884 3961 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575
DV		 3962 if (!IS_GEN2(dev) &&
3963 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
734b4157
KH		 3964 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
3965 /* the chip adds 2 halflines automatically */
734b4157 3966 adjusted_mode->crtc_vtotal -= 1;
734b4157 3967 adjusted_mode->crtc_vblank_end -= 1;
0529a0d9
DV		 3968 vsyncshift = adjusted_mode->crtc_hsync_start
3969 - adjusted_mode->crtc_htotal/2;
3970 } else {
617cf884 3971 pipeconf |= PIPECONF_PROGRESSIVE;
0529a0d9
DV		 3972 vsyncshift = 0;
3973 }
3974
3975 if (!IS_GEN3(dev))
3976 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
734b4157 3977
5eddb70b
CW		 3978 I915_WRITE(HTOTAL(pipe),
3979 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 3980 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 3981 I915_WRITE(HBLANK(pipe),
3982 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 3983 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 3984 I915_WRITE(HSYNC(pipe),
3985 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 3986 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 3987
3988 I915_WRITE(VTOTAL(pipe),
3989 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 3990 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 3991 I915_WRITE(VBLANK(pipe),
3992 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 3993 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 3994 I915_WRITE(VSYNC(pipe),
3995 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 3996 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b
CW		 3997
3998 /* pipesrc and dspsize control the size that is scaled from,
3999 * which should always be the user's requested size.
79e53945 4000 */
929c77fb
EA		 4001 I915_WRITE(DSPSIZE(plane),
4002 ((mode->vdisplay - 1) << 16) |
4003 (mode->hdisplay - 1));
4004 I915_WRITE(DSPPOS(plane), 0);
5eddb70b
CW		 4005 I915_WRITE(PIPESRC(pipe),
4006 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 4007
f564048e
EA		 4008 I915_WRITE(PIPECONF(pipe), pipeconf);
4009 POSTING_READ(PIPECONF(pipe));
929c77fb 4010 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4011
4012 intel_wait_for_vblank(dev, pipe);
4013
f564048e
EA		 4014 I915_WRITE(DSPCNTR(plane), dspcntr);
4015 POSTING_READ(DSPCNTR(plane));
4016
4017 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4018
4019 intel_update_watermarks(dev);
4020
f564048e
EA		 4021 return ret;
4022}
4023
9fb526db
KP		 4024/*
4025 * Initialize reference clocks when the driver loads
4026 */
4027void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4028{
4029 struct drm_i915_private *dev_priv = dev->dev_private;
4030 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4031 struct intel_encoder *encoder;
13d83a67
JB		 4032 u32 temp;
4033 bool has_lvds = false;
199e5d79
KP		 4034 bool has_cpu_edp = false;
4035 bool has_pch_edp = false;
4036 bool has_panel = false;
99eb6a01
KP		 4037 bool has_ck505 = false;
4038 bool can_ssc = false;
13d83a67
JB		 4039
4040 /* We need to take the global config into account */
199e5d79
KP		 4041 list_for_each_entry(encoder, &mode_config->encoder_list,
4042 base.head) {
4043 switch (encoder->type) {
4044 case INTEL_OUTPUT_LVDS:
4045 has_panel = true;
4046 has_lvds = true;
4047 break;
4048 case INTEL_OUTPUT_EDP:
4049 has_panel = true;
4050 if (intel_encoder_is_pch_edp(&encoder->base))
4051 has_pch_edp = true;
4052 else
4053 has_cpu_edp = true;
4054 break;
13d83a67
JB		 4055 }
4056 }
4057
99eb6a01
KP		 4058 if (HAS_PCH_IBX(dev)) {
4059 has_ck505 = dev_priv->display_clock_mode;
4060 can_ssc = has_ck505;
4061 } else {
4062 has_ck505 = false;
4063 can_ssc = true;
4064 }
4065
4066 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4067 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4068 has_ck505);
13d83a67
JB		 4069
4070 /* Ironlake: try to setup display ref clock before DPLL
4071 * enabling. This is only under driver's control after
4072 * PCH B stepping, previous chipset stepping should be
4073 * ignoring this setting.
4074 */
4075 temp = I915_READ(PCH_DREF_CONTROL);
4076 /* Always enable nonspread source */
4077 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4078
99eb6a01
KP		 4079 if (has_ck505)
4080 temp |= DREF_NONSPREAD_CK505_ENABLE;
4081 else
4082 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4083
199e5d79
KP		 4084 if (has_panel) {
4085 temp &= ~DREF_SSC_SOURCE_MASK;
4086 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4087
199e5d79 4088 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4089 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4090 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4091 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4092 } else
4093 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4094
4095 /* Get SSC going before enabling the outputs */
4096 I915_WRITE(PCH_DREF_CONTROL, temp);
4097 POSTING_READ(PCH_DREF_CONTROL);
4098 udelay(200);
4099
13d83a67
JB		 4100 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4101
4102 /* Enable CPU source on CPU attached eDP */
199e5d79 4103 if (has_cpu_edp) {
99eb6a01 4104 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4105 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4106 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4107 }
13d83a67
JB		 4108 else
4109 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4110 } else
4111 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4112
4113 I915_WRITE(PCH_DREF_CONTROL, temp);
4114 POSTING_READ(PCH_DREF_CONTROL);
4115 udelay(200);
4116 } else {
4117 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4118
4119 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4120
4121 /* Turn off CPU output */
4122 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4123
4124 I915_WRITE(PCH_DREF_CONTROL, temp);
4125 POSTING_READ(PCH_DREF_CONTROL);
4126 udelay(200);
4127
4128 /* Turn off the SSC source */
4129 temp &= ~DREF_SSC_SOURCE_MASK;
4130 temp |= DREF_SSC_SOURCE_DISABLE;
4131
4132 /* Turn off SSC1 */
4133 temp &= ~ DREF_SSC1_ENABLE;
4134
13d83a67
JB		 4135 I915_WRITE(PCH_DREF_CONTROL, temp);
4136 POSTING_READ(PCH_DREF_CONTROL);
4137 udelay(200);
4138 }
4139}
4140
d9d444cb
JB		 4141static int ironlake_get_refclk(struct drm_crtc *crtc)
4142{
4143 struct drm_device *dev = crtc->dev;
4144 struct drm_i915_private *dev_priv = dev->dev_private;
4145 struct intel_encoder *encoder;
4146 struct drm_mode_config *mode_config = &dev->mode_config;
4147 struct intel_encoder *edp_encoder = NULL;
4148 int num_connectors = 0;
4149 bool is_lvds = false;
4150
4151 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4152 if (encoder->base.crtc != crtc)
4153 continue;
4154
4155 switch (encoder->type) {
4156 case INTEL_OUTPUT_LVDS:
4157 is_lvds = true;
4158 break;
4159 case INTEL_OUTPUT_EDP:
4160 edp_encoder = encoder;
4161 break;
4162 }
4163 num_connectors++;
4164 }
4165
4166 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4167 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4168 dev_priv->lvds_ssc_freq);
4169 return dev_priv->lvds_ssc_freq * 1000;
4170 }
4171
4172 return 120000;
4173}
4174
f564048e
EA		 4175static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4176 struct drm_display_mode *mode,
4177 struct drm_display_mode *adjusted_mode,
4178 int x, int y,
4179 struct drm_framebuffer *old_fb)
79e53945
JB		 4180{
4181 struct drm_device *dev = crtc->dev;
4182 struct drm_i915_private *dev_priv = dev->dev_private;
4183 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4184 int pipe = intel_crtc->pipe;
80824003 4185 int plane = intel_crtc->plane;
c751ce4f 4186 int refclk, num_connectors = 0;
652c393a 4187 intel_clock_t clock, reduced_clock;
5eddb70b 4188 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
a07d6787 4189 bool ok, has_reduced_clock = false, is_sdvo = false;
a4fc5ed6 4190 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
79e53945 4191 struct drm_mode_config *mode_config = &dev->mode_config;
e3aef172 4192 struct intel_encoder *encoder, *edp_encoder = NULL;
d4906093 4193 const intel_limit_t *limit;
5c3b82e2 4194 int ret;
2c07245f 4195 struct fdi_m_n m_n = {0};
fae14981 4196 u32 temp;
5a354204
JB		 4197 int target_clock, pixel_multiplier, lane, link_bw, factor;
4198 unsigned int pipe_bpp;
4199 bool dither;
e3aef172 4200 bool is_cpu_edp = false, is_pch_edp = false;
79e53945 4201
5eddb70b
CW		 4202 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4203 if (encoder->base.crtc != crtc)
79e53945
JB		 4204 continue;
4205
5eddb70b 4206 switch (encoder->type) {
79e53945
JB		 4207 case INTEL_OUTPUT_LVDS:
4208 is_lvds = true;
4209 break;
4210 case INTEL_OUTPUT_SDVO:
7d57382e 4211 case INTEL_OUTPUT_HDMI:
79e53945 4212 is_sdvo = true;
5eddb70b 4213 if (encoder->needs_tv_clock)
e2f0ba97 4214 is_tv = true;
79e53945 4215 break;
79e53945
JB		 4216 case INTEL_OUTPUT_TVOUT:
4217 is_tv = true;
4218 break;
4219 case INTEL_OUTPUT_ANALOG:
4220 is_crt = true;
4221 break;
a4fc5ed6
KP		 4222 case INTEL_OUTPUT_DISPLAYPORT:
4223 is_dp = true;
4224 break;
32f9d658 4225 case INTEL_OUTPUT_EDP:
e3aef172
JB		 4226 is_dp = true;
4227 if (intel_encoder_is_pch_edp(&encoder->base))
4228 is_pch_edp = true;
4229 else
4230 is_cpu_edp = true;
4231 edp_encoder = encoder;
32f9d658 4232 break;
79e53945 4233 }
43565a06 4234
c751ce4f 4235 num_connectors++;
79e53945
JB		 4236 }
4237
d9d444cb 4238 refclk = ironlake_get_refclk(crtc);
79e53945 4239
d4906093
ML		 4240 /*
4241 * Returns a set of divisors for the desired target clock with the given
4242 * refclk, or FALSE. The returned values represent the clock equation:
4243 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4244 */
1b894b59 4245 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4246 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4247 &clock);
79e53945
JB		 4248 if (!ok) {
4249 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4250 return -EINVAL;
79e53945
JB		 4251 }
4252
cda4b7d3 4253 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4254 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4255
ddc9003c 4256 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4257 /*
4258 * Ensure we match the reduced clock's P to the target clock.
4259 * If the clocks don't match, we can't switch the display clock
4260 * by using the FP0/FP1. In such case we will disable the LVDS
4261 * downclock feature.
4262 */
ddc9003c 4263 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4264 dev_priv->lvds_downclock,
4265 refclk,
cec2f356 4266 &clock,
5eddb70b 4267 &reduced_clock);
652c393a 4268 }
7026d4ac
ZW		 4269 /* SDVO TV has fixed PLL values depend on its clock range,
4270 this mirrors vbios setting. */
4271 if (is_sdvo && is_tv) {
4272 if (adjusted_mode->clock >= 100000
5eddb70b 4273 && adjusted_mode->clock < 140500) {
7026d4ac
ZW		 4274 clock.p1 = 2;
4275 clock.p2 = 10;
4276 clock.n = 3;
4277 clock.m1 = 16;
4278 clock.m2 = 8;
4279 } else if (adjusted_mode->clock >= 140500
5eddb70b 4280 && adjusted_mode->clock <= 200000) {
7026d4ac
ZW		 4281 clock.p1 = 1;
4282 clock.p2 = 10;
4283 clock.n = 6;
4284 clock.m1 = 12;
4285 clock.m2 = 8;
4286 }
4287 }
4288
2c07245f 4289 /* FDI link */
8febb297
EA		 4290 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4291 lane = 0;
4292 /* CPU eDP doesn't require FDI link, so just set DP M/N
4293 according to current link config */
e3aef172 4294 if (is_cpu_edp) {
8febb297 4295 target_clock = mode->clock;
e3aef172 4296 intel_edp_link_config(edp_encoder, &lane, &link_bw);
8febb297
EA		 4297 } else {
4298 /* [e]DP over FDI requires target mode clock
4299 instead of link clock */
e3aef172 4300 if (is_dp)
5eb08b69 4301 target_clock = mode->clock;
8febb297
EA		 4302 else
4303 target_clock = adjusted_mode->clock;
4304
4305 /* FDI is a binary signal running at ~2.7GHz, encoding
4306 * each output octet as 10 bits. The actual frequency
4307 * is stored as a divider into a 100MHz clock, and the
4308 * mode pixel clock is stored in units of 1KHz.
4309 * Hence the bw of each lane in terms of the mode signal
4310 * is:
4311 */
4312 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4313 }
58a27471 4314
8febb297
EA		 4315 /* determine panel color depth */
4316 temp = I915_READ(PIPECONF(pipe));
4317 temp &= ~PIPE_BPC_MASK;
3b5c78a3 4318 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
5a354204
JB		 4319 switch (pipe_bpp) {
4320 case 18:
4321 temp |= PIPE_6BPC;
8febb297 4322 break;
5a354204
JB		 4323 case 24:
4324 temp |= PIPE_8BPC;
8febb297 4325 break;
5a354204
JB		 4326 case 30:
4327 temp |= PIPE_10BPC;
8febb297 4328 break;
5a354204
JB		 4329 case 36:
4330 temp |= PIPE_12BPC;
8febb297
EA		 4331 break;
4332 default:
62ac41a6
JB		 4333 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4334 pipe_bpp);
5a354204
JB		 4335 temp |= PIPE_8BPC;
4336 pipe_bpp = 24;
4337 break;
8febb297 4338 }
77ffb597 4339
5a354204
JB		 4340 intel_crtc->bpp = pipe_bpp;
4341 I915_WRITE(PIPECONF(pipe), temp);
4342
8febb297
EA		 4343 if (!lane) {
4344 /*
4345 * Account for spread spectrum to avoid
4346 * oversubscribing the link. Max center spread
4347 * is 2.5%; use 5% for safety's sake.
4348 */
5a354204 4349 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
8febb297 4350 lane = bps / (link_bw * 8) + 1;
5eb08b69 4351 }
2c07245f 4352
8febb297
EA		 4353 intel_crtc->fdi_lanes = lane;
4354
4355 if (pixel_multiplier > 1)
4356 link_bw *= pixel_multiplier;
5a354204
JB		 4357 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4358 &m_n);
8febb297 4359
a07d6787
EA		 4360 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4361 if (has_reduced_clock)
4362 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4363 reduced_clock.m2;
79e53945 4364
c1858123 4365 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 4366 factor = 21;
4367 if (is_lvds) {
4368 if ((intel_panel_use_ssc(dev_priv) &&
4369 dev_priv->lvds_ssc_freq == 100) ||
4370 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4371 factor = 25;
4372 } else if (is_sdvo && is_tv)
4373 factor = 20;
c1858123 4374
cb0e0931 4375 if (clock.m < factor * clock.n)
8febb297 4376 fp |= FP_CB_TUNE;
2c07245f 4377
5eddb70b 4378 dpll = 0;
2c07245f 4379
a07d6787
EA		 4380 if (is_lvds)
4381 dpll |= DPLLB_MODE_LVDS;
4382 else
4383 dpll |= DPLLB_MODE_DAC_SERIAL;
4384 if (is_sdvo) {
4385 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4386 if (pixel_multiplier > 1) {
4387 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 4388 }
a07d6787
EA		 4389 dpll |= DPLL_DVO_HIGH_SPEED;
4390 }
e3aef172 4391 if (is_dp && !is_cpu_edp)
a07d6787 4392 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 4393
a07d6787
EA		 4394 /* compute bitmask from p1 value */
4395 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4396 /* also FPA1 */
4397 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4398
4399 switch (clock.p2) {
4400 case 5:
4401 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4402 break;
4403 case 7:
4404 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4405 break;
4406 case 10:
4407 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4408 break;
4409 case 14:
4410 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4411 break;
79e53945
JB		 4412 }
4413
43565a06
KH		 4414 if (is_sdvo && is_tv)
4415 dpll |= PLL_REF_INPUT_TVCLKINBC;
4416 else if (is_tv)
79e53945 4417 /* XXX: just matching BIOS for now */
43565a06 4418 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 4419 dpll |= 3;
a7615030 4420 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 4421 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 4422 else
4423 dpll |= PLL_REF_INPUT_DREFCLK;
4424
4425 /* setup pipeconf */
5eddb70b 4426 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4427
4428 /* Set up the display plane register */
4429 dspcntr = DISPPLANE_GAMMA_ENABLE;
4430
f7cb34d4 4431 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 4432 drm_mode_debug_printmodeline(mode);
4433
9d82aa17
ED		 4434 /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
4435 * pre-Haswell/LPT generation */
4436 if (HAS_PCH_LPT(dev)) {
4437 DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
4438 pipe);
4439 } else if (!is_cpu_edp) {
ee7b9f93 4440 struct intel_pch_pll *pll;
4b645f14 4441
ee7b9f93
JB		 4442 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4443 if (pll == NULL) {
4444 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4445 pipe);
4b645f14
JB		 4446 return -EINVAL;
4447 }
ee7b9f93
JB		 4448 } else
4449 intel_put_pch_pll(intel_crtc);
79e53945
JB		 4450
4451 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4452 * This is an exception to the general rule that mode_set doesn't turn
4453 * things on.
4454 */
4455 if (is_lvds) {
fae14981 4456 temp = I915_READ(PCH_LVDS);
5eddb70b 4457 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
7885d205
JB		 4458 if (HAS_PCH_CPT(dev)) {
4459 temp &= ~PORT_TRANS_SEL_MASK;
4b645f14 4460 temp |= PORT_TRANS_SEL_CPT(pipe);
7885d205
JB		 4461 } else {
4462 if (pipe == 1)
4463 temp |= LVDS_PIPEB_SELECT;
4464 else
4465 temp &= ~LVDS_PIPEB_SELECT;
4466 }
4b645f14 4467
a3e17eb8 4468 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 4469 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 4470 /* Set the B0-B3 data pairs corresponding to whether we're going to
4471 * set the DPLLs for dual-channel mode or not.
4472 */
4473 if (clock.p2 == 7)
5eddb70b 4474 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 4475 else
5eddb70b 4476 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 4477
4478 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4479 * appropriately here, but we need to look more thoroughly into how
4480 * panels behave in the two modes.
4481 */
284d5df5 4482 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
aa9b500d 4483 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 4484 temp |= LVDS_HSYNC_POLARITY;
aa9b500d 4485 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 4486 temp |= LVDS_VSYNC_POLARITY;
fae14981 4487 I915_WRITE(PCH_LVDS, temp);
79e53945 4488 }
434ed097 4489
8febb297
EA		 4490 pipeconf &= ~PIPECONF_DITHER_EN;
4491 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5a354204 4492 if ((is_lvds && dev_priv->lvds_dither) || dither) {
8febb297 4493 pipeconf |= PIPECONF_DITHER_EN;
f74974c7 4494 pipeconf |= PIPECONF_DITHER_TYPE_SP;
434ed097 4495 }
e3aef172 4496 if (is_dp && !is_cpu_edp) {
a4fc5ed6 4497 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 4498 } else {
8db9d77b 4499 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 4500 I915_WRITE(TRANSDATA_M1(pipe), 0);
4501 I915_WRITE(TRANSDATA_N1(pipe), 0);
4502 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4503 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 4504 }
79e53945 4505
ee7b9f93
JB		 4506 if (intel_crtc->pch_pll) {
4507 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 4508
32f9d658 4509 /* Wait for the clocks to stabilize. */
ee7b9f93 4510 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 4511 udelay(150);
4512
8febb297
EA		 4513 /* The pixel multiplier can only be updated once the
4514 * DPLL is enabled and the clocks are stable.
4515 *
4516 * So write it again.
4517 */
ee7b9f93 4518 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 4519 }
79e53945 4520
5eddb70b 4521 intel_crtc->lowfreq_avail = false;
ee7b9f93 4522 if (intel_crtc->pch_pll) {
4b645f14 4523 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 4524 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14
JB		 4525 intel_crtc->lowfreq_avail = true;
4526 if (HAS_PIPE_CXSR(dev)) {
4527 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4528 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4529 }
4530 } else {
ee7b9f93 4531 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
4b645f14
JB		 4532 if (HAS_PIPE_CXSR(dev)) {
4533 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4534 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4535 }
652c393a
JB		 4536 }
4537 }
4538
617cf884 4539 pipeconf &= ~PIPECONF_INTERLACE_MASK;
734b4157 4540 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5def474e 4541 pipeconf |= PIPECONF_INTERLACED_ILK;
734b4157 4542 /* the chip adds 2 halflines automatically */
734b4157 4543 adjusted_mode->crtc_vtotal -= 1;
734b4157 4544 adjusted_mode->crtc_vblank_end -= 1;
0529a0d9
DV		 4545 I915_WRITE(VSYNCSHIFT(pipe),
4546 adjusted_mode->crtc_hsync_start
4547 - adjusted_mode->crtc_htotal/2);
4548 } else {
617cf884 4549 pipeconf |= PIPECONF_PROGRESSIVE;
0529a0d9
DV		 4550 I915_WRITE(VSYNCSHIFT(pipe), 0);
4551 }
734b4157 4552
5eddb70b
CW		 4553 I915_WRITE(HTOTAL(pipe),
4554 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 4555 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 4556 I915_WRITE(HBLANK(pipe),
4557 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 4558 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 4559 I915_WRITE(HSYNC(pipe),
4560 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 4561 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 4562
4563 I915_WRITE(VTOTAL(pipe),
4564 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 4565 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 4566 I915_WRITE(VBLANK(pipe),
4567 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 4568 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 4569 I915_WRITE(VSYNC(pipe),
4570 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 4571 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b 4572
8febb297
EA		 4573 /* pipesrc controls the size that is scaled from, which should
4574 * always be the user's requested size.
79e53945 4575 */
5eddb70b
CW		 4576 I915_WRITE(PIPESRC(pipe),
4577 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 4578
8febb297
EA		 4579 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4580 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4581 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4582 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
2c07245f 4583
e3aef172 4584 if (is_cpu_edp)
8febb297 4585 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f 4586
5eddb70b
CW		 4587 I915_WRITE(PIPECONF(pipe), pipeconf);
4588 POSTING_READ(PIPECONF(pipe));
79e53945 4589
9d0498a2 4590 intel_wait_for_vblank(dev, pipe);
79e53945 4591
5eddb70b 4592 I915_WRITE(DSPCNTR(plane), dspcntr);
b24e7179 4593 POSTING_READ(DSPCNTR(plane));
79e53945 4594
5c3b82e2 4595 ret = intel_pipe_set_base(crtc, x, y, old_fb);
7662c8bd
SL		 4596
4597 intel_update_watermarks(dev);
4598
1f803ee5 4599 return ret;
79e53945
JB		 4600}
4601
f564048e
EA		 4602static int intel_crtc_mode_set(struct drm_crtc *crtc,
4603 struct drm_display_mode *mode,
4604 struct drm_display_mode *adjusted_mode,
4605 int x, int y,
4606 struct drm_framebuffer *old_fb)
4607{
4608 struct drm_device *dev = crtc->dev;
4609 struct drm_i915_private *dev_priv = dev->dev_private;
0b701d27
EA		 4610 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4611 int pipe = intel_crtc->pipe;
f564048e
EA		 4612 int ret;
4613
0b701d27 4614 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 4615
f564048e
EA		 4616 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
4617 x, y, old_fb);
79e53945 4618 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 4619
d8e70a25
JB		 4620 if (ret)
4621 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4622 else
4623 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
120eced9 4624
1f803ee5 4625 return ret;
79e53945
JB		 4626}
4627
3a9627f4
WF		 4628static bool intel_eld_uptodate(struct drm_connector *connector,
4629 int reg_eldv, uint32_t bits_eldv,
4630 int reg_elda, uint32_t bits_elda,
4631 int reg_edid)
4632{
4633 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4634 uint8_t *eld = connector->eld;
4635 uint32_t i;
4636
4637 i = I915_READ(reg_eldv);
4638 i &= bits_eldv;
4639
4640 if (!eld[0])
4641 return !i;
4642
4643 if (!i)
4644 return false;
4645
4646 i = I915_READ(reg_elda);
4647 i &= ~bits_elda;
4648 I915_WRITE(reg_elda, i);
4649
4650 for (i = 0; i < eld[2]; i++)
4651 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
4652 return false;
4653
4654 return true;
4655}
4656
e0dac65e
WF		 4657static void g4x_write_eld(struct drm_connector *connector,
4658 struct drm_crtc *crtc)
4659{
4660 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4661 uint8_t *eld = connector->eld;
4662 uint32_t eldv;
4663 uint32_t len;
4664 uint32_t i;
4665
4666 i = I915_READ(G4X_AUD_VID_DID);
4667
4668 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
4669 eldv = G4X_ELDV_DEVCL_DEVBLC;
4670 else
4671 eldv = G4X_ELDV_DEVCTG;
4672
3a9627f4
WF		 4673 if (intel_eld_uptodate(connector,
4674 G4X_AUD_CNTL_ST, eldv,
4675 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
4676 G4X_HDMIW_HDMIEDID))
4677 return;
4678
e0dac65e
WF		 4679 i = I915_READ(G4X_AUD_CNTL_ST);
4680 i &= ~(eldv | G4X_ELD_ADDR);
4681 len = (i >> 9) & 0x1f; /* ELD buffer size */
4682 I915_WRITE(G4X_AUD_CNTL_ST, i);
4683
4684 if (!eld[0])
4685 return;
4686
4687 len = min_t(uint8_t, eld[2], len);
4688 DRM_DEBUG_DRIVER("ELD size %d\n", len);
4689 for (i = 0; i < len; i++)
4690 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
4691
4692 i = I915_READ(G4X_AUD_CNTL_ST);
4693 i |= eldv;
4694 I915_WRITE(G4X_AUD_CNTL_ST, i);
4695}
4696
4697static void ironlake_write_eld(struct drm_connector *connector,
4698 struct drm_crtc *crtc)
4699{
4700 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4701 uint8_t *eld = connector->eld;
4702 uint32_t eldv;
4703 uint32_t i;
4704 int len;
4705 int hdmiw_hdmiedid;
b6daa025 4706 int aud_config;
e0dac65e
WF		 4707 int aud_cntl_st;
4708 int aud_cntrl_st2;
4709
b3f33cbf 4710 if (HAS_PCH_IBX(connector->dev)) {
1202b4c6 4711 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
b6daa025 4712 aud_config = IBX_AUD_CONFIG_A;
1202b4c6
WF		 4713 aud_cntl_st = IBX_AUD_CNTL_ST_A;
4714 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 4715 } else {
1202b4c6 4716 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
b6daa025 4717 aud_config = CPT_AUD_CONFIG_A;
1202b4c6
WF		 4718 aud_cntl_st = CPT_AUD_CNTL_ST_A;
4719 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 4720 }
4721
4722 i = to_intel_crtc(crtc)->pipe;
4723 hdmiw_hdmiedid += i * 0x100;
4724 aud_cntl_st += i * 0x100;
b6daa025 4725 aud_config += i * 0x100;
e0dac65e
WF		 4726
4727 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
4728
4729 i = I915_READ(aud_cntl_st);
4730 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
4731 if (!i) {
4732 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
4733 /* operate blindly on all ports */
1202b4c6
WF		 4734 eldv = IBX_ELD_VALIDB;
4735 eldv |= IBX_ELD_VALIDB << 4;
4736 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 4737 } else {
4738 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 4739 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 4740 }
4741
3a9627f4
WF		 4742 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
4743 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
4744 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 4745 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
4746 } else
4747 I915_WRITE(aud_config, 0);
e0dac65e 4748
3a9627f4
WF		 4749 if (intel_eld_uptodate(connector,
4750 aud_cntrl_st2, eldv,
4751 aud_cntl_st, IBX_ELD_ADDRESS,
4752 hdmiw_hdmiedid))
4753 return;
4754
e0dac65e
WF		 4755 i = I915_READ(aud_cntrl_st2);
4756 i &= ~eldv;
4757 I915_WRITE(aud_cntrl_st2, i);
4758
4759 if (!eld[0])
4760 return;
4761
e0dac65e 4762 i = I915_READ(aud_cntl_st);
1202b4c6 4763 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 4764 I915_WRITE(aud_cntl_st, i);
4765
4766 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
4767 DRM_DEBUG_DRIVER("ELD size %d\n", len);
4768 for (i = 0; i < len; i++)
4769 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
4770
4771 i = I915_READ(aud_cntrl_st2);
4772 i |= eldv;
4773 I915_WRITE(aud_cntrl_st2, i);
4774}
4775
4776void intel_write_eld(struct drm_encoder *encoder,
4777 struct drm_display_mode *mode)
4778{
4779 struct drm_crtc *crtc = encoder->crtc;
4780 struct drm_connector *connector;
4781 struct drm_device *dev = encoder->dev;
4782 struct drm_i915_private *dev_priv = dev->dev_private;
4783
4784 connector = drm_select_eld(encoder, mode);
4785 if (!connector)
4786 return;
4787
4788 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
4789 connector->base.id,
4790 drm_get_connector_name(connector),
4791 connector->encoder->base.id,
4792 drm_get_encoder_name(connector->encoder));
4793
4794 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
4795
4796 if (dev_priv->display.write_eld)
4797 dev_priv->display.write_eld(connector, crtc);
4798}
4799
79e53945
JB		 4800/** Loads the palette/gamma unit for the CRTC with the prepared values */
4801void intel_crtc_load_lut(struct drm_crtc *crtc)
4802{
4803 struct drm_device *dev = crtc->dev;
4804 struct drm_i915_private *dev_priv = dev->dev_private;
4805 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 4806 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 4807 int i;
4808
4809 /* The clocks have to be on to load the palette. */
aed3f09d 4810 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 4811 return;
4812
f2b115e6 4813 /* use legacy palette for Ironlake */
bad720ff 4814 if (HAS_PCH_SPLIT(dev))
9db4a9c7 4815 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 4816
79e53945
JB		 4817 for (i = 0; i < 256; i++) {
4818 I915_WRITE(palreg + 4 * i,
4819 (intel_crtc->lut_r[i] << 16) |
4820 (intel_crtc->lut_g[i] << 8) |
4821 intel_crtc->lut_b[i]);
4822 }
4823}
4824
560b85bb
CW		 4825static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4826{
4827 struct drm_device *dev = crtc->dev;
4828 struct drm_i915_private *dev_priv = dev->dev_private;
4829 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4830 bool visible = base != 0;
4831 u32 cntl;
4832
4833 if (intel_crtc->cursor_visible == visible)
4834 return;
4835
9db4a9c7 4836 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 4837 if (visible) {
4838 /* On these chipsets we can only modify the base whilst
4839 * the cursor is disabled.
4840 */
9db4a9c7 4841 I915_WRITE(_CURABASE, base);
560b85bb
CW		 4842
4843 cntl &= ~(CURSOR_FORMAT_MASK);
4844 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4845 cntl |= CURSOR_ENABLE |
4846 CURSOR_GAMMA_ENABLE |
4847 CURSOR_FORMAT_ARGB;
4848 } else
4849 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 4850 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 4851
4852 intel_crtc->cursor_visible = visible;
4853}
4854
4855static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4856{
4857 struct drm_device *dev = crtc->dev;
4858 struct drm_i915_private *dev_priv = dev->dev_private;
4859 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4860 int pipe = intel_crtc->pipe;
4861 bool visible = base != 0;
4862
4863 if (intel_crtc->cursor_visible != visible) {
548f245b 4864 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 4865 if (base) {
4866 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4867 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4868 cntl |= pipe << 28; /* Connect to correct pipe */
4869 } else {
4870 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4871 cntl |= CURSOR_MODE_DISABLE;
4872 }
9db4a9c7 4873 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 4874
4875 intel_crtc->cursor_visible = visible;
4876 }
4877 /* and commit changes on next vblank */
9db4a9c7 4878 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 4879}
4880
65a21cd6
JB		 4881static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
4882{
4883 struct drm_device *dev = crtc->dev;
4884 struct drm_i915_private *dev_priv = dev->dev_private;
4885 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4886 int pipe = intel_crtc->pipe;
4887 bool visible = base != 0;
4888
4889 if (intel_crtc->cursor_visible != visible) {
4890 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
4891 if (base) {
4892 cntl &= ~CURSOR_MODE;
4893 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4894 } else {
4895 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4896 cntl |= CURSOR_MODE_DISABLE;
4897 }
4898 I915_WRITE(CURCNTR_IVB(pipe), cntl);
4899
4900 intel_crtc->cursor_visible = visible;
4901 }
4902 /* and commit changes on next vblank */
4903 I915_WRITE(CURBASE_IVB(pipe), base);
4904}
4905
cda4b7d3 4906/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 4907static void intel_crtc_update_cursor(struct drm_crtc *crtc,
4908 bool on)
cda4b7d3
CW		 4909{
4910 struct drm_device *dev = crtc->dev;
4911 struct drm_i915_private *dev_priv = dev->dev_private;
4912 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4913 int pipe = intel_crtc->pipe;
4914 int x = intel_crtc->cursor_x;
4915 int y = intel_crtc->cursor_y;
560b85bb 4916 u32 base, pos;
cda4b7d3
CW		 4917 bool visible;
4918
4919 pos = 0;
4920
6b383a7f 4921 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 4922 base = intel_crtc->cursor_addr;
4923 if (x > (int) crtc->fb->width)
4924 base = 0;
4925
4926 if (y > (int) crtc->fb->height)
4927 base = 0;
4928 } else
4929 base = 0;
4930
4931 if (x < 0) {
4932 if (x + intel_crtc->cursor_width < 0)
4933 base = 0;
4934
4935 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4936 x = -x;
4937 }
4938 pos |= x << CURSOR_X_SHIFT;
4939
4940 if (y < 0) {
4941 if (y + intel_crtc->cursor_height < 0)
4942 base = 0;
4943
4944 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4945 y = -y;
4946 }
4947 pos |= y << CURSOR_Y_SHIFT;
4948
4949 visible = base != 0;
560b85bb 4950 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 4951 return;
4952
0cd83aa9 4953 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 4954 I915_WRITE(CURPOS_IVB(pipe), pos);
4955 ivb_update_cursor(crtc, base);
4956 } else {
4957 I915_WRITE(CURPOS(pipe), pos);
4958 if (IS_845G(dev) || IS_I865G(dev))
4959 i845_update_cursor(crtc, base);
4960 else
4961 i9xx_update_cursor(crtc, base);
4962 }
cda4b7d3
CW		 4963}
4964
79e53945 4965static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 4966 struct drm_file *file,
79e53945
JB		 4967 uint32_t handle,
4968 uint32_t width, uint32_t height)
4969{
4970 struct drm_device *dev = crtc->dev;
4971 struct drm_i915_private *dev_priv = dev->dev_private;
4972 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 4973 struct drm_i915_gem_object *obj;
cda4b7d3 4974 uint32_t addr;
3f8bc370 4975 int ret;
79e53945 4976
28c97730 4977 DRM_DEBUG_KMS("\n");
79e53945
JB		 4978
4979 /* if we want to turn off the cursor ignore width and height */
4980 if (!handle) {
28c97730 4981 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 4982 addr = 0;
05394f39 4983 obj = NULL;
5004417d 4984 mutex_lock(&dev->struct_mutex);
3f8bc370 4985 goto finish;
79e53945
JB		 4986 }
4987
4988 /* Currently we only support 64x64 cursors */
4989 if (width != 64 || height != 64) {
4990 DRM_ERROR("we currently only support 64x64 cursors\n");
4991 return -EINVAL;
4992 }
4993
05394f39 4994 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 4995 if (&obj->base == NULL)
79e53945
JB		 4996 return -ENOENT;
4997
05394f39 4998 if (obj->base.size < width * height * 4) {
79e53945 4999 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 5000 ret = -ENOMEM;
5001 goto fail;
79e53945
JB		 5002 }
5003
71acb5eb 5004 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 5005 mutex_lock(&dev->struct_mutex);
b295d1b6 5006 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 5007 if (obj->tiling_mode) {
5008 DRM_ERROR("cursor cannot be tiled\n");
5009 ret = -EINVAL;
5010 goto fail_locked;
5011 }
5012
2da3b9b9 5013 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 5014 if (ret) {
5015 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 5016 goto fail_locked;
e7b526bb
CW		 5017 }
5018
d9e86c0e
CW		 5019 ret = i915_gem_object_put_fence(obj);
5020 if (ret) {
2da3b9b9 5021 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 5022 goto fail_unpin;
5023 }
5024
05394f39 5025 addr = obj->gtt_offset;
71acb5eb 5026 } else {
6eeefaf3 5027 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 5028 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 5029 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5030 align);
71acb5eb
DA		 5031 if (ret) {
5032 DRM_ERROR("failed to attach phys object\n");
7f9872e0 5033 goto fail_locked;
71acb5eb 5034 }
05394f39 5035 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 5036 }
5037
a6c45cf0 5038 if (IS_GEN2(dev))
14b60391
JB		 5039 I915_WRITE(CURSIZE, (height << 12) | width);
5040
3f8bc370 5041 finish:
3f8bc370 5042 if (intel_crtc->cursor_bo) {
b295d1b6 5043 if (dev_priv->info->cursor_needs_physical) {
05394f39 5044 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 5045 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5046 } else
5047 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 5048 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 5049 }
80824003 5050
7f9872e0 5051 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 5052
5053 intel_crtc->cursor_addr = addr;
05394f39 5054 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 5055 intel_crtc->cursor_width = width;
5056 intel_crtc->cursor_height = height;
5057
6b383a7f 5058 intel_crtc_update_cursor(crtc, true);
3f8bc370 5059
79e53945 5060 return 0;
e7b526bb 5061fail_unpin:
05394f39 5062 i915_gem_object_unpin(obj);
7f9872e0 5063fail_locked:
34b8686e 5064 mutex_unlock(&dev->struct_mutex);
bc9025bd 5065fail:
05394f39 5066 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 5067 return ret;
79e53945
JB		 5068}
5069
5070static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5071{
79e53945 5072 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5073
cda4b7d3
CW		 5074 intel_crtc->cursor_x = x;
5075 intel_crtc->cursor_y = y;
652c393a 5076
6b383a7f 5077 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 5078
5079 return 0;
5080}
5081
5082/** Sets the color ramps on behalf of RandR */
5083void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5084 u16 blue, int regno)
5085{
5086 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5087
5088 intel_crtc->lut_r[regno] = red >> 8;
5089 intel_crtc->lut_g[regno] = green >> 8;
5090 intel_crtc->lut_b[regno] = blue >> 8;
5091}
5092
b8c00ac5
DA		 5093void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5094 u16 *blue, int regno)
5095{
5096 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5097
5098 *red = intel_crtc->lut_r[regno] << 8;
5099 *green = intel_crtc->lut_g[regno] << 8;
5100 *blue = intel_crtc->lut_b[regno] << 8;
5101}
5102
79e53945 5103static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 5104 u16 *blue, uint32_t start, uint32_t size)
79e53945 5105{
7203425a 5106 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 5107 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5108
7203425a 5109 for (i = start; i < end; i++) {
79e53945
JB		 5110 intel_crtc->lut_r[i] = red[i] >> 8;
5111 intel_crtc->lut_g[i] = green[i] >> 8;
5112 intel_crtc->lut_b[i] = blue[i] >> 8;
5113 }
5114
5115 intel_crtc_load_lut(crtc);
5116}
5117
5118/**
5119 * Get a pipe with a simple mode set on it for doing load-based monitor
5120 * detection.
5121 *
5122 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 5123 * its requirements. The pipe will be connected to no other encoders.
79e53945 5124 *
c751ce4f 5125 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 5126 * configured for it. In the future, it could choose to temporarily disable
5127 * some outputs to free up a pipe for its use.
5128 *
5129 * \return crtc, or NULL if no pipes are available.
5130 */
5131
5132/* VESA 640x480x72Hz mode to set on the pipe */
5133static struct drm_display_mode load_detect_mode = {
5134 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5135 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5136};
5137
d2dff872
CW		 5138static struct drm_framebuffer *
5139intel_framebuffer_create(struct drm_device *dev,
308e5bcb 5140 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 5141 struct drm_i915_gem_object *obj)
5142{
5143 struct intel_framebuffer *intel_fb;
5144 int ret;
5145
5146 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5147 if (!intel_fb) {
5148 drm_gem_object_unreference_unlocked(&obj->base);
5149 return ERR_PTR(-ENOMEM);
5150 }
5151
5152 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5153 if (ret) {
5154 drm_gem_object_unreference_unlocked(&obj->base);
5155 kfree(intel_fb);
5156 return ERR_PTR(ret);
5157 }
5158
5159 return &intel_fb->base;
5160}
5161
5162static u32
5163intel_framebuffer_pitch_for_width(int width, int bpp)
5164{
5165 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5166 return ALIGN(pitch, 64);
5167}
5168
5169static u32
5170intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5171{
5172 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5173 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5174}
5175
5176static struct drm_framebuffer *
5177intel_framebuffer_create_for_mode(struct drm_device *dev,
5178 struct drm_display_mode *mode,
5179 int depth, int bpp)
5180{
5181 struct drm_i915_gem_object *obj;
308e5bcb 5182 struct drm_mode_fb_cmd2 mode_cmd;
d2dff872
CW		 5183
5184 obj = i915_gem_alloc_object(dev,
5185 intel_framebuffer_size_for_mode(mode, bpp));
5186 if (obj == NULL)
5187 return ERR_PTR(-ENOMEM);
5188
5189 mode_cmd.width = mode->hdisplay;
5190 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 5191 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5192 bpp);
5ca0c34a 5193 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 5194
5195 return intel_framebuffer_create(dev, &mode_cmd, obj);
5196}
5197
5198static struct drm_framebuffer *
5199mode_fits_in_fbdev(struct drm_device *dev,
5200 struct drm_display_mode *mode)
5201{
5202 struct drm_i915_private *dev_priv = dev->dev_private;
5203 struct drm_i915_gem_object *obj;
5204 struct drm_framebuffer *fb;
5205
5206 if (dev_priv->fbdev == NULL)
5207 return NULL;
5208
5209 obj = dev_priv->fbdev->ifb.obj;
5210 if (obj == NULL)
5211 return NULL;
5212
5213 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 5214 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5215 fb->bits_per_pixel))
d2dff872
CW		 5216 return NULL;
5217
01f2c773 5218 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 5219 return NULL;
5220
5221 return fb;
5222}
5223
7173188d
CW		 5224bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5225 struct drm_connector *connector,
5226 struct drm_display_mode *mode,
8261b191 5227 struct intel_load_detect_pipe *old)
79e53945
JB		 5228{
5229 struct intel_crtc *intel_crtc;
5230 struct drm_crtc *possible_crtc;
4ef69c7a 5231 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5232 struct drm_crtc *crtc = NULL;
5233 struct drm_device *dev = encoder->dev;
d2dff872 5234 struct drm_framebuffer *old_fb;
79e53945
JB		 5235 int i = -1;
5236
d2dff872
CW		 5237 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5238 connector->base.id, drm_get_connector_name(connector),
5239 encoder->base.id, drm_get_encoder_name(encoder));
5240
79e53945
JB		 5241 /*
5242 * Algorithm gets a little messy:
7a5e4805 5243 *
79e53945
JB		 5244 * - if the connector already has an assigned crtc, use it (but make
5245 * sure it's on first)
7a5e4805 5246 *
79e53945
JB		 5247 * - try to find the first unused crtc that can drive this connector,
5248 * and use that if we find one
79e53945
JB		 5249 */
5250
5251 /* See if we already have a CRTC for this connector */
5252 if (encoder->crtc) {
5253 crtc = encoder->crtc;
8261b191 5254
79e53945 5255 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 5256 old->dpms_mode = intel_crtc->dpms_mode;
5257 old->load_detect_temp = false;
5258
5259 /* Make sure the crtc and connector are running */
79e53945 5260 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6492711d
CW		 5261 struct drm_encoder_helper_funcs *encoder_funcs;
5262 struct drm_crtc_helper_funcs *crtc_funcs;
5263
79e53945
JB		 5264 crtc_funcs = crtc->helper_private;
5265 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6492711d
CW		 5266
5267 encoder_funcs = encoder->helper_private;
79e53945
JB		 5268 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5269 }
8261b191 5270
7173188d 5271 return true;
79e53945
JB		 5272 }
5273
5274 /* Find an unused one (if possible) */
5275 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5276 i++;
5277 if (!(encoder->possible_crtcs & (1 << i)))
5278 continue;
5279 if (!possible_crtc->enabled) {
5280 crtc = possible_crtc;
5281 break;
5282 }
79e53945
JB		 5283 }
5284
5285 /*
5286 * If we didn't find an unused CRTC, don't use any.
5287 */
5288 if (!crtc) {
7173188d
CW		 5289 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5290 return false;
79e53945
JB		 5291 }
5292
5293 encoder->crtc = crtc;
c1c43977 5294 connector->encoder = encoder;
79e53945
JB		 5295
5296 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 5297 old->dpms_mode = intel_crtc->dpms_mode;
5298 old->load_detect_temp = true;
d2dff872 5299 old->release_fb = NULL;
79e53945 5300
6492711d
CW		 5301 if (!mode)
5302 mode = &load_detect_mode;
79e53945 5303
d2dff872
CW		 5304 old_fb = crtc->fb;
5305
5306 /* We need a framebuffer large enough to accommodate all accesses
5307 * that the plane may generate whilst we perform load detection.
5308 * We can not rely on the fbcon either being present (we get called
5309 * during its initialisation to detect all boot displays, or it may
5310 * not even exist) or that it is large enough to satisfy the
5311 * requested mode.
5312 */
5313 crtc->fb = mode_fits_in_fbdev(dev, mode);
5314 if (crtc->fb == NULL) {
5315 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5316 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5317 old->release_fb = crtc->fb;
5318 } else
5319 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5320 if (IS_ERR(crtc->fb)) {
5321 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5322 crtc->fb = old_fb;
5323 return false;
79e53945 5324 }
79e53945 5325
d2dff872 5326 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6492711d 5327 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 5328 if (old->release_fb)
5329 old->release_fb->funcs->destroy(old->release_fb);
5330 crtc->fb = old_fb;
6492711d 5331 return false;
79e53945 5332 }
7173188d 5333
79e53945 5334 /* let the connector get through one full cycle before testing */
9d0498a2 5335 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 5336
7173188d 5337 return true;
79e53945
JB		 5338}
5339
c1c43977 5340void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
8261b191
CW		 5341 struct drm_connector *connector,
5342 struct intel_load_detect_pipe *old)
79e53945 5343{
4ef69c7a 5344 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5345 struct drm_device *dev = encoder->dev;
5346 struct drm_crtc *crtc = encoder->crtc;
5347 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5348 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5349
d2dff872
CW		 5350 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5351 connector->base.id, drm_get_connector_name(connector),
5352 encoder->base.id, drm_get_encoder_name(encoder));
5353
8261b191 5354 if (old->load_detect_temp) {
c1c43977 5355 connector->encoder = NULL;
79e53945 5356 drm_helper_disable_unused_functions(dev);
d2dff872
CW		 5357
5358 if (old->release_fb)
5359 old->release_fb->funcs->destroy(old->release_fb);
5360
0622a53c 5361 return;
79e53945
JB		 5362 }
5363
c751ce4f 5364 /* Switch crtc and encoder back off if necessary */
0622a53c
CW		 5365 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5366 encoder_funcs->dpms(encoder, old->dpms_mode);
8261b191 5367 crtc_funcs->dpms(crtc, old->dpms_mode);
79e53945
JB		 5368 }
5369}
5370
5371/* Returns the clock of the currently programmed mode of the given pipe. */
5372static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5373{
5374 struct drm_i915_private *dev_priv = dev->dev_private;
5375 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5376 int pipe = intel_crtc->pipe;
548f245b 5377 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 5378 u32 fp;
5379 intel_clock_t clock;
5380
5381 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 5382 fp = I915_READ(FP0(pipe));
79e53945 5383 else
39adb7a5 5384 fp = I915_READ(FP1(pipe));
79e53945
JB		 5385
5386 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 5387 if (IS_PINEVIEW(dev)) {
5388 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5389 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 5390 } else {
5391 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5392 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5393 }
5394
a6c45cf0 5395 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 5396 if (IS_PINEVIEW(dev))
5397 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5398 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 5399 else
5400 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 5401 DPLL_FPA01_P1_POST_DIV_SHIFT);
5402
5403 switch (dpll & DPLL_MODE_MASK) {
5404 case DPLLB_MODE_DAC_SERIAL:
5405 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5406 5 : 10;
5407 break;
5408 case DPLLB_MODE_LVDS:
5409 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5410 7 : 14;
5411 break;
5412 default:
28c97730 5413 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 5414 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5415 return 0;
5416 }
5417
5418 /* XXX: Handle the 100Mhz refclk */
2177832f 5419 intel_clock(dev, 96000, &clock);
79e53945
JB		 5420 } else {
5421 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5422
5423 if (is_lvds) {
5424 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5425 DPLL_FPA01_P1_POST_DIV_SHIFT);
5426 clock.p2 = 14;
5427
5428 if ((dpll & PLL_REF_INPUT_MASK) ==
5429 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5430 /* XXX: might not be 66MHz */
2177832f 5431 intel_clock(dev, 66000, &clock);
79e53945 5432 } else
2177832f 5433 intel_clock(dev, 48000, &clock);
79e53945
JB		 5434 } else {
5435 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5436 clock.p1 = 2;
5437 else {
5438 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5439 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5440 }
5441 if (dpll & PLL_P2_DIVIDE_BY_4)
5442 clock.p2 = 4;
5443 else
5444 clock.p2 = 2;
5445
2177832f 5446 intel_clock(dev, 48000, &clock);
79e53945
JB		 5447 }
5448 }
5449
5450 /* XXX: It would be nice to validate the clocks, but we can't reuse
5451 * i830PllIsValid() because it relies on the xf86_config connector
5452 * configuration being accurate, which it isn't necessarily.
5453 */
5454
5455 return clock.dot;
5456}
5457
5458/** Returns the currently programmed mode of the given pipe. */
5459struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5460 struct drm_crtc *crtc)
5461{
548f245b 5462 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 5463 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5464 int pipe = intel_crtc->pipe;
5465 struct drm_display_mode *mode;
548f245b
JB		 5466 int htot = I915_READ(HTOTAL(pipe));
5467 int hsync = I915_READ(HSYNC(pipe));
5468 int vtot = I915_READ(VTOTAL(pipe));
5469 int vsync = I915_READ(VSYNC(pipe));
79e53945
JB		 5470
5471 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5472 if (!mode)
5473 return NULL;
5474
5475 mode->clock = intel_crtc_clock_get(dev, crtc);
5476 mode->hdisplay = (htot & 0xffff) + 1;
5477 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5478 mode->hsync_start = (hsync & 0xffff) + 1;
5479 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5480 mode->vdisplay = (vtot & 0xffff) + 1;
5481 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5482 mode->vsync_start = (vsync & 0xffff) + 1;
5483 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5484
5485 drm_mode_set_name(mode);
79e53945
JB		 5486
5487 return mode;
5488}
5489
652c393a
JB		 5490#define GPU_IDLE_TIMEOUT 500 /* ms */
5491
5492/* When this timer fires, we've been idle for awhile */
5493static void intel_gpu_idle_timer(unsigned long arg)
5494{
5495 struct drm_device *dev = (struct drm_device *)arg;
5496 drm_i915_private_t *dev_priv = dev->dev_private;
5497
ff7ea4c0
CW		 5498 if (!list_empty(&dev_priv->mm.active_list)) {
5499 /* Still processing requests, so just re-arm the timer. */
5500 mod_timer(&dev_priv->idle_timer, jiffies +
5501 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5502 return;
5503 }
652c393a 5504
ff7ea4c0 5505 dev_priv->busy = false;
01dfba93 5506 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 5507}
5508
652c393a
JB		 5509#define CRTC_IDLE_TIMEOUT 1000 /* ms */
5510
5511static void intel_crtc_idle_timer(unsigned long arg)
5512{
5513 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5514 struct drm_crtc *crtc = &intel_crtc->base;
5515 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
ff7ea4c0 5516 struct intel_framebuffer *intel_fb;
652c393a 5517
ff7ea4c0
CW		 5518 intel_fb = to_intel_framebuffer(crtc->fb);
5519 if (intel_fb && intel_fb->obj->active) {
5520 /* The framebuffer is still being accessed by the GPU. */
5521 mod_timer(&intel_crtc->idle_timer, jiffies +
5522 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5523 return;
5524 }
652c393a 5525
ff7ea4c0 5526 intel_crtc->busy = false;
01dfba93 5527 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 5528}
5529
3dec0095 5530static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 5531{
5532 struct drm_device *dev = crtc->dev;
5533 drm_i915_private_t *dev_priv = dev->dev_private;
5534 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5535 int pipe = intel_crtc->pipe;
dbdc6479
JB		 5536 int dpll_reg = DPLL(pipe);
5537 int dpll;
652c393a 5538
bad720ff 5539 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 5540 return;
5541
5542 if (!dev_priv->lvds_downclock_avail)
5543 return;
5544
dbdc6479 5545 dpll = I915_READ(dpll_reg);
652c393a 5546 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 5547 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 5548
8ac5a6d5 5549 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 5550
5551 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5552 I915_WRITE(dpll_reg, dpll);
9d0498a2 5553 intel_wait_for_vblank(dev, pipe);
dbdc6479 5554
652c393a
JB		 5555 dpll = I915_READ(dpll_reg);
5556 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 5557 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a
JB		 5558 }
5559
5560 /* Schedule downclock */
3dec0095
DV		 5561 mod_timer(&intel_crtc->idle_timer, jiffies +
5562 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
652c393a
JB		 5563}
5564
5565static void intel_decrease_pllclock(struct drm_crtc *crtc)
5566{
5567 struct drm_device *dev = crtc->dev;
5568 drm_i915_private_t *dev_priv = dev->dev_private;
5569 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 5570
bad720ff 5571 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 5572 return;
5573
5574 if (!dev_priv->lvds_downclock_avail)
5575 return;
5576
5577 /*
5578 * Since this is called by a timer, we should never get here in
5579 * the manual case.
5580 */
5581 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 5582 int pipe = intel_crtc->pipe;
5583 int dpll_reg = DPLL(pipe);
5584 int dpll;
f6e5b160 5585
44d98a61 5586 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 5587
8ac5a6d5 5588 assert_panel_unlocked(dev_priv, pipe);
652c393a 5589
dc257cf1 5590 dpll = I915_READ(dpll_reg);
652c393a
JB		 5591 dpll |= DISPLAY_RATE_SELECT_FPA1;
5592 I915_WRITE(dpll_reg, dpll);
9d0498a2 5593 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 5594 dpll = I915_READ(dpll_reg);
5595 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 5596 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 5597 }
5598
5599}
5600
5601/**
5602 * intel_idle_update - adjust clocks for idleness
5603 * @work: work struct
5604 *
5605 * Either the GPU or display (or both) went idle. Check the busy status
5606 * here and adjust the CRTC and GPU clocks as necessary.
5607 */
5608static void intel_idle_update(struct work_struct *work)
5609{
5610 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
5611 idle_work);
5612 struct drm_device *dev = dev_priv->dev;
5613 struct drm_crtc *crtc;
5614 struct intel_crtc *intel_crtc;
5615
5616 if (!i915_powersave)
5617 return;
5618
5619 mutex_lock(&dev->struct_mutex);
5620
7648fa99
JB		 5621 i915_update_gfx_val(dev_priv);
5622
652c393a
JB		 5623 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5624 /* Skip inactive CRTCs */
5625 if (!crtc->fb)
5626 continue;
5627
5628 intel_crtc = to_intel_crtc(crtc);
5629 if (!intel_crtc->busy)
5630 intel_decrease_pllclock(crtc);
5631 }
5632
45ac22c8 5633
652c393a
JB		 5634 mutex_unlock(&dev->struct_mutex);
5635}
5636
5637/**
5638 * intel_mark_busy - mark the GPU and possibly the display busy
5639 * @dev: drm device
5640 * @obj: object we're operating on
5641 *
5642 * Callers can use this function to indicate that the GPU is busy processing
5643 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
5644 * buffer), we'll also mark the display as busy, so we know to increase its
5645 * clock frequency.
5646 */
05394f39 5647void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
652c393a
JB		 5648{
5649 drm_i915_private_t *dev_priv = dev->dev_private;
5650 struct drm_crtc *crtc = NULL;
5651 struct intel_framebuffer *intel_fb;
5652 struct intel_crtc *intel_crtc;
5653
5e17ee74
ZW		 5654 if (!drm_core_check_feature(dev, DRIVER_MODESET))
5655 return;
5656
9104183d
CW		 5657 if (!dev_priv->busy) {
5658 intel_sanitize_pm(dev);
28cf798f 5659 dev_priv->busy = true;
9104183d 5660 } else
28cf798f
CW		 5661 mod_timer(&dev_priv->idle_timer, jiffies +
5662 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
652c393a 5663
acb87dfb
CW		 5664 if (obj == NULL)
5665 return;
5666
652c393a
JB		 5667 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5668 if (!crtc->fb)
5669 continue;
5670
5671 intel_crtc = to_intel_crtc(crtc);
5672 intel_fb = to_intel_framebuffer(crtc->fb);
5673 if (intel_fb->obj == obj) {
5674 if (!intel_crtc->busy) {
5675 /* Non-busy -> busy, upclock */
3dec0095 5676 intel_increase_pllclock(crtc);
652c393a
JB		 5677 intel_crtc->busy = true;
5678 } else {
5679 /* Busy -> busy, put off timer */
5680 mod_timer(&intel_crtc->idle_timer, jiffies +
5681 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5682 }
5683 }
5684 }
5685}
5686
79e53945
JB		 5687static void intel_crtc_destroy(struct drm_crtc *crtc)
5688{
5689 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 5690 struct drm_device *dev = crtc->dev;
5691 struct intel_unpin_work *work;
5692 unsigned long flags;
5693
5694 spin_lock_irqsave(&dev->event_lock, flags);
5695 work = intel_crtc->unpin_work;
5696 intel_crtc->unpin_work = NULL;
5697 spin_unlock_irqrestore(&dev->event_lock, flags);
5698
5699 if (work) {
5700 cancel_work_sync(&work->work);
5701 kfree(work);
5702 }
79e53945
JB		 5703
5704 drm_crtc_cleanup(crtc);
67e77c5a 5705
79e53945
JB		 5706 kfree(intel_crtc);
5707}
5708
6b95a207
KH		 5709static void intel_unpin_work_fn(struct work_struct *__work)
5710{
5711 struct intel_unpin_work *work =
5712 container_of(__work, struct intel_unpin_work, work);
5713
5714 mutex_lock(&work->dev->struct_mutex);
1690e1eb 5715 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 5716 drm_gem_object_unreference(&work->pending_flip_obj->base);
5717 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 5718
7782de3b 5719 intel_update_fbc(work->dev);
6b95a207
KH		 5720 mutex_unlock(&work->dev->struct_mutex);
5721 kfree(work);
5722}
5723
1afe3e9d 5724static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 5725 struct drm_crtc *crtc)
6b95a207
KH		 5726{
5727 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 5728 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5729 struct intel_unpin_work *work;
05394f39 5730 struct drm_i915_gem_object *obj;
6b95a207 5731 struct drm_pending_vblank_event *e;
49b14a5c 5732 struct timeval tnow, tvbl;
6b95a207
KH		 5733 unsigned long flags;
5734
5735 /* Ignore early vblank irqs */
5736 if (intel_crtc == NULL)
5737 return;
5738
49b14a5c
MK		 5739 do_gettimeofday(&tnow);
5740
6b95a207
KH		 5741 spin_lock_irqsave(&dev->event_lock, flags);
5742 work = intel_crtc->unpin_work;
5743 if (work == NULL || !work->pending) {
5744 spin_unlock_irqrestore(&dev->event_lock, flags);
5745 return;
5746 }
5747
5748 intel_crtc->unpin_work = NULL;
6b95a207
KH		 5749
5750 if (work->event) {
5751 e = work->event;
49b14a5c 5752 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df
MK		 5753
5754 /* Called before vblank count and timestamps have
5755 * been updated for the vblank interval of flip
5756 * completion? Need to increment vblank count and
5757 * add one videorefresh duration to returned timestamp
49b14a5c
MK		 5758 * to account for this. We assume this happened if we
5759 * get called over 0.9 frame durations after the last
5760 * timestamped vblank.
5761 *
5762 * This calculation can not be used with vrefresh rates
5763 * below 5Hz (10Hz to be on the safe side) without
5764 * promoting to 64 integers.
0af7e4df 5765 */
49b14a5c
MK		 5766 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
5767 9 * crtc->framedur_ns) {
0af7e4df 5768 e->event.sequence++;
49b14a5c
MK		 5769 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
5770 crtc->framedur_ns);
0af7e4df
MK		 5771 }
5772
49b14a5c
MK		 5773 e->event.tv_sec = tvbl.tv_sec;
5774 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 5775
6b95a207
KH		 5776 list_add_tail(&e->base.link,
5777 &e->base.file_priv->event_list);
5778 wake_up_interruptible(&e->base.file_priv->event_wait);
5779 }
5780
0af7e4df
MK		 5781 drm_vblank_put(dev, intel_crtc->pipe);
5782
6b95a207
KH		 5783 spin_unlock_irqrestore(&dev->event_lock, flags);
5784
05394f39 5785 obj = work->old_fb_obj;
d9e86c0e 5786
e59f2bac 5787 atomic_clear_mask(1 << intel_crtc->plane,
05394f39
CW		 5788 &obj->pending_flip.counter);
5789 if (atomic_read(&obj->pending_flip) == 0)
f787a5f5 5790 wake_up(&dev_priv->pending_flip_queue);
d9e86c0e 5791
6b95a207 5792 schedule_work(&work->work);
e5510fac
JB		 5793
5794 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 5795}
5796
1afe3e9d
JB		 5797void intel_finish_page_flip(struct drm_device *dev, int pipe)
5798{
5799 drm_i915_private_t *dev_priv = dev->dev_private;
5800 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5801
49b14a5c 5802 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 5803}
5804
5805void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5806{
5807 drm_i915_private_t *dev_priv = dev->dev_private;
5808 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5809
49b14a5c 5810 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 5811}
5812
6b95a207
KH		 5813void intel_prepare_page_flip(struct drm_device *dev, int plane)
5814{
5815 drm_i915_private_t *dev_priv = dev->dev_private;
5816 struct intel_crtc *intel_crtc =
5817 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5818 unsigned long flags;
5819
5820 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 5821 if (intel_crtc->unpin_work) {
4e5359cd
SF		 5822 if ((++intel_crtc->unpin_work->pending) > 1)
5823 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 5824 } else {
5825 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5826 }
6b95a207
KH		 5827 spin_unlock_irqrestore(&dev->event_lock, flags);
5828}
5829
8c9f3aaf
JB		 5830static int intel_gen2_queue_flip(struct drm_device *dev,
5831 struct drm_crtc *crtc,
5832 struct drm_framebuffer *fb,
5833 struct drm_i915_gem_object *obj)
5834{
5835 struct drm_i915_private *dev_priv = dev->dev_private;
5836 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5837 unsigned long offset;
5838 u32 flip_mask;
6d90c952 5839 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 5840 int ret;
5841
6d90c952 5842 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 5843 if (ret)
83d4092b 5844 goto err;
8c9f3aaf
JB		 5845
5846 /* Offset into the new buffer for cases of shared fbs between CRTCs */
01f2c773 5847 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
8c9f3aaf 5848
6d90c952 5849 ret = intel_ring_begin(ring, 6);
8c9f3aaf 5850 if (ret)
83d4092b 5851 goto err_unpin;
8c9f3aaf
JB		 5852
5853 /* Can't queue multiple flips, so wait for the previous
5854 * one to finish before executing the next.
5855 */
5856 if (intel_crtc->plane)
5857 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5858 else
5859 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 5860 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
5861 intel_ring_emit(ring, MI_NOOP);
5862 intel_ring_emit(ring, MI_DISPLAY_FLIP |
5863 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5864 intel_ring_emit(ring, fb->pitches[0]);
5865 intel_ring_emit(ring, obj->gtt_offset + offset);
5866 intel_ring_emit(ring, 0); /* aux display base address, unused */
5867 intel_ring_advance(ring);
83d4092b
CW		 5868 return 0;
5869
5870err_unpin:
5871 intel_unpin_fb_obj(obj);
5872err:
8c9f3aaf
JB		 5873 return ret;
5874}
5875
5876static int intel_gen3_queue_flip(struct drm_device *dev,
5877 struct drm_crtc *crtc,
5878 struct drm_framebuffer *fb,
5879 struct drm_i915_gem_object *obj)
5880{
5881 struct drm_i915_private *dev_priv = dev->dev_private;
5882 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5883 unsigned long offset;
5884 u32 flip_mask;
6d90c952 5885 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 5886 int ret;
5887
6d90c952 5888 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 5889 if (ret)
83d4092b 5890 goto err;
8c9f3aaf
JB		 5891
5892 /* Offset into the new buffer for cases of shared fbs between CRTCs */
01f2c773 5893 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
8c9f3aaf 5894
6d90c952 5895 ret = intel_ring_begin(ring, 6);
8c9f3aaf 5896 if (ret)
83d4092b 5897 goto err_unpin;
8c9f3aaf
JB		 5898
5899 if (intel_crtc->plane)
5900 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5901 else
5902 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 5903 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
5904 intel_ring_emit(ring, MI_NOOP);
5905 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
5906 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5907 intel_ring_emit(ring, fb->pitches[0]);
5908 intel_ring_emit(ring, obj->gtt_offset + offset);
5909 intel_ring_emit(ring, MI_NOOP);
5910
5911 intel_ring_advance(ring);
83d4092b
CW		 5912 return 0;
5913
5914err_unpin:
5915 intel_unpin_fb_obj(obj);
5916err:
8c9f3aaf
JB		 5917 return ret;
5918}
5919
5920static int intel_gen4_queue_flip(struct drm_device *dev,
5921 struct drm_crtc *crtc,
5922 struct drm_framebuffer *fb,
5923 struct drm_i915_gem_object *obj)
5924{
5925 struct drm_i915_private *dev_priv = dev->dev_private;
5926 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5927 uint32_t pf, pipesrc;
6d90c952 5928 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 5929 int ret;
5930
6d90c952 5931 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 5932 if (ret)
83d4092b 5933 goto err;
8c9f3aaf 5934
6d90c952 5935 ret = intel_ring_begin(ring, 4);
8c9f3aaf 5936 if (ret)
83d4092b 5937 goto err_unpin;
8c9f3aaf
JB		 5938
5939 /* i965+ uses the linear or tiled offsets from the
5940 * Display Registers (which do not change across a page-flip)
5941 * so we need only reprogram the base address.
5942 */
6d90c952
DV		 5943 intel_ring_emit(ring, MI_DISPLAY_FLIP |
5944 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5945 intel_ring_emit(ring, fb->pitches[0]);
5946 intel_ring_emit(ring, obj->gtt_offset | obj->tiling_mode);
8c9f3aaf
JB		 5947
5948 /* XXX Enabling the panel-fitter across page-flip is so far
5949 * untested on non-native modes, so ignore it for now.
5950 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5951 */
5952 pf = 0;
5953 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 5954 intel_ring_emit(ring, pf | pipesrc);
5955 intel_ring_advance(ring);
83d4092b
CW		 5956 return 0;
5957
5958err_unpin:
5959 intel_unpin_fb_obj(obj);
5960err:
8c9f3aaf
JB		 5961 return ret;
5962}
5963
5964static int intel_gen6_queue_flip(struct drm_device *dev,
5965 struct drm_crtc *crtc,
5966 struct drm_framebuffer *fb,
5967 struct drm_i915_gem_object *obj)
5968{
5969 struct drm_i915_private *dev_priv = dev->dev_private;
5970 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 5971 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 5972 uint32_t pf, pipesrc;
5973 int ret;
5974
6d90c952 5975 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 5976 if (ret)
83d4092b 5977 goto err;
8c9f3aaf 5978
6d90c952 5979 ret = intel_ring_begin(ring, 4);
8c9f3aaf 5980 if (ret)
83d4092b 5981 goto err_unpin;
8c9f3aaf 5982
6d90c952
DV		 5983 intel_ring_emit(ring, MI_DISPLAY_FLIP |
5984 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5985 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
5986 intel_ring_emit(ring, obj->gtt_offset);
8c9f3aaf 5987
dc257cf1
DV		 5988 /* Contrary to the suggestions in the documentation,
5989 * "Enable Panel Fitter" does not seem to be required when page
5990 * flipping with a non-native mode, and worse causes a normal
5991 * modeset to fail.
5992 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
5993 */
5994 pf = 0;
8c9f3aaf 5995 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 5996 intel_ring_emit(ring, pf | pipesrc);
5997 intel_ring_advance(ring);
83d4092b
CW		 5998 return 0;
5999
6000err_unpin:
6001 intel_unpin_fb_obj(obj);
6002err:
8c9f3aaf
JB		 6003 return ret;
6004}
6005
7c9017e5
JB		 6006/*
6007 * On gen7 we currently use the blit ring because (in early silicon at least)
6008 * the render ring doesn't give us interrpts for page flip completion, which
6009 * means clients will hang after the first flip is queued. Fortunately the
6010 * blit ring generates interrupts properly, so use it instead.
6011 */
6012static int intel_gen7_queue_flip(struct drm_device *dev,
6013 struct drm_crtc *crtc,
6014 struct drm_framebuffer *fb,
6015 struct drm_i915_gem_object *obj)
6016{
6017 struct drm_i915_private *dev_priv = dev->dev_private;
6018 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6019 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6020 int ret;
6021
6022 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6023 if (ret)
83d4092b 6024 goto err;
7c9017e5
JB		 6025
6026 ret = intel_ring_begin(ring, 4);
6027 if (ret)
83d4092b 6028 goto err_unpin;
7c9017e5
JB		 6029
6030 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
01f2c773 6031 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7c9017e5
JB		 6032 intel_ring_emit(ring, (obj->gtt_offset));
6033 intel_ring_emit(ring, (MI_NOOP));
6034 intel_ring_advance(ring);
83d4092b
CW		 6035 return 0;
6036
6037err_unpin:
6038 intel_unpin_fb_obj(obj);
6039err:
7c9017e5
JB		 6040 return ret;
6041}
6042
8c9f3aaf
JB		 6043static int intel_default_queue_flip(struct drm_device *dev,
6044 struct drm_crtc *crtc,
6045 struct drm_framebuffer *fb,
6046 struct drm_i915_gem_object *obj)
6047{
6048 return -ENODEV;
6049}
6050
6b95a207
KH		 6051static int intel_crtc_page_flip(struct drm_crtc *crtc,
6052 struct drm_framebuffer *fb,
6053 struct drm_pending_vblank_event *event)
6054{
6055 struct drm_device *dev = crtc->dev;
6056 struct drm_i915_private *dev_priv = dev->dev_private;
6057 struct intel_framebuffer *intel_fb;
05394f39 6058 struct drm_i915_gem_object *obj;
6b95a207
KH		 6059 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6060 struct intel_unpin_work *work;
8c9f3aaf 6061 unsigned long flags;
52e68630 6062 int ret;
6b95a207
KH		 6063
6064 work = kzalloc(sizeof *work, GFP_KERNEL);
6065 if (work == NULL)
6066 return -ENOMEM;
6067
6b95a207
KH		 6068 work->event = event;
6069 work->dev = crtc->dev;
6070 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 6071 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 6072 INIT_WORK(&work->work, intel_unpin_work_fn);
6073
7317c75e
JB		 6074 ret = drm_vblank_get(dev, intel_crtc->pipe);
6075 if (ret)
6076 goto free_work;
6077
6b95a207
KH		 6078 /* We borrow the event spin lock for protecting unpin_work */
6079 spin_lock_irqsave(&dev->event_lock, flags);
6080 if (intel_crtc->unpin_work) {
6081 spin_unlock_irqrestore(&dev->event_lock, flags);
6082 kfree(work);
7317c75e 6083 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 6084
6085 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 6086 return -EBUSY;
6087 }
6088 intel_crtc->unpin_work = work;
6089 spin_unlock_irqrestore(&dev->event_lock, flags);
6090
6091 intel_fb = to_intel_framebuffer(fb);
6092 obj = intel_fb->obj;
6093
468f0b44 6094 mutex_lock(&dev->struct_mutex);
6b95a207 6095
75dfca80 6096 /* Reference the objects for the scheduled work. */
05394f39
CW		 6097 drm_gem_object_reference(&work->old_fb_obj->base);
6098 drm_gem_object_reference(&obj->base);
6b95a207
KH		 6099
6100 crtc->fb = fb;
96b099fd 6101
e1f99ce6 6102 work->pending_flip_obj = obj;
e1f99ce6 6103
4e5359cd
SF		 6104 work->enable_stall_check = true;
6105
e1f99ce6
CW		 6106 /* Block clients from rendering to the new back buffer until
6107 * the flip occurs and the object is no longer visible.
6108 */
05394f39 6109 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 6110
8c9f3aaf
JB		 6111 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6112 if (ret)
6113 goto cleanup_pending;
6b95a207 6114
7782de3b 6115 intel_disable_fbc(dev);
acb87dfb 6116 intel_mark_busy(dev, obj);
6b95a207
KH		 6117 mutex_unlock(&dev->struct_mutex);
6118
e5510fac
JB		 6119 trace_i915_flip_request(intel_crtc->plane, obj);
6120
6b95a207 6121 return 0;
96b099fd 6122
8c9f3aaf
JB		 6123cleanup_pending:
6124 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
05394f39
CW		 6125 drm_gem_object_unreference(&work->old_fb_obj->base);
6126 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 6127 mutex_unlock(&dev->struct_mutex);
6128
6129 spin_lock_irqsave(&dev->event_lock, flags);
6130 intel_crtc->unpin_work = NULL;
6131 spin_unlock_irqrestore(&dev->event_lock, flags);
6132
7317c75e
JB		 6133 drm_vblank_put(dev, intel_crtc->pipe);
6134free_work:
96b099fd
CW		 6135 kfree(work);
6136
6137 return ret;
6b95a207
KH		 6138}
6139
47f1c6c9
CW		 6140static void intel_sanitize_modesetting(struct drm_device *dev,
6141 int pipe, int plane)
6142{
6143 struct drm_i915_private *dev_priv = dev->dev_private;
6144 u32 reg, val;
6145
f47166d2
CW		 6146 /* Clear any frame start delays used for debugging left by the BIOS */
6147 for_each_pipe(pipe) {
6148 reg = PIPECONF(pipe);
6149 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
6150 }
6151
47f1c6c9
CW		 6152 if (HAS_PCH_SPLIT(dev))
6153 return;
6154
6155 /* Who knows what state these registers were left in by the BIOS or
6156 * grub?
6157 *
6158 * If we leave the registers in a conflicting state (e.g. with the
6159 * display plane reading from the other pipe than the one we intend
6160 * to use) then when we attempt to teardown the active mode, we will
6161 * not disable the pipes and planes in the correct order -- leaving
6162 * a plane reading from a disabled pipe and possibly leading to
6163 * undefined behaviour.
6164 */
6165
6166 reg = DSPCNTR(plane);
6167 val = I915_READ(reg);
6168
6169 if ((val & DISPLAY_PLANE_ENABLE) == 0)
6170 return;
6171 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6172 return;
6173
6174 /* This display plane is active and attached to the other CPU pipe. */
6175 pipe = !pipe;
6176
6177 /* Disable the plane and wait for it to stop reading from the pipe. */
b24e7179
JB		 6178 intel_disable_plane(dev_priv, plane, pipe);
6179 intel_disable_pipe(dev_priv, pipe);
47f1c6c9 6180}
79e53945 6181
f6e5b160
CW		 6182static void intel_crtc_reset(struct drm_crtc *crtc)
6183{
6184 struct drm_device *dev = crtc->dev;
6185 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6186
6187 /* Reset flags back to the 'unknown' status so that they
6188 * will be correctly set on the initial modeset.
6189 */
6190 intel_crtc->dpms_mode = -1;
6191
6192 /* We need to fix up any BIOS configuration that conflicts with
6193 * our expectations.
6194 */
6195 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6196}
6197
6198static struct drm_crtc_helper_funcs intel_helper_funcs = {
6199 .dpms = intel_crtc_dpms,
6200 .mode_fixup = intel_crtc_mode_fixup,
6201 .mode_set = intel_crtc_mode_set,
6202 .mode_set_base = intel_pipe_set_base,
6203 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6204 .load_lut = intel_crtc_load_lut,
6205 .disable = intel_crtc_disable,
6206};
6207
6208static const struct drm_crtc_funcs intel_crtc_funcs = {
6209 .reset = intel_crtc_reset,
6210 .cursor_set = intel_crtc_cursor_set,
6211 .cursor_move = intel_crtc_cursor_move,
6212 .gamma_set = intel_crtc_gamma_set,
6213 .set_config = drm_crtc_helper_set_config,
6214 .destroy = intel_crtc_destroy,
6215 .page_flip = intel_crtc_page_flip,
6216};
6217
ee7b9f93
JB		 6218static void intel_pch_pll_init(struct drm_device *dev)
6219{
6220 drm_i915_private_t *dev_priv = dev->dev_private;
6221 int i;
6222
6223 if (dev_priv->num_pch_pll == 0) {
6224 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
6225 return;
6226 }
6227
6228 for (i = 0; i < dev_priv->num_pch_pll; i++) {
6229 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
6230 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
6231 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
6232 }
6233}
6234
b358d0a6 6235static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 6236{
22fd0fab 6237 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 6238 struct intel_crtc *intel_crtc;
6239 int i;
6240
6241 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6242 if (intel_crtc == NULL)
6243 return;
6244
6245 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6246
6247 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 6248 for (i = 0; i < 256; i++) {
6249 intel_crtc->lut_r[i] = i;
6250 intel_crtc->lut_g[i] = i;
6251 intel_crtc->lut_b[i] = i;
6252 }
6253
80824003
JB		 6254 /* Swap pipes & planes for FBC on pre-965 */
6255 intel_crtc->pipe = pipe;
6256 intel_crtc->plane = pipe;
e2e767ab 6257 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 6258 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 6259 intel_crtc->plane = !pipe;
80824003
JB		 6260 }
6261
22fd0fab
JB		 6262 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6263 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6264 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6265 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6266
5d1d0cc8 6267 intel_crtc_reset(&intel_crtc->base);
04dbff52 6268 intel_crtc->active = true; /* force the pipe off on setup_init_config */
5a354204 6269 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3
JB		 6270
6271 if (HAS_PCH_SPLIT(dev)) {
6272 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6273 intel_helper_funcs.commit = ironlake_crtc_commit;
6274 } else {
6275 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6276 intel_helper_funcs.commit = i9xx_crtc_commit;
6277 }
6278
79e53945
JB		 6279 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6280
652c393a
JB		 6281 intel_crtc->busy = false;
6282
6283 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6284 (unsigned long)intel_crtc);
79e53945
JB		 6285}
6286
08d7b3d1 6287int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 6288 struct drm_file *file)
08d7b3d1 6289{
08d7b3d1 6290 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 6291 struct drm_mode_object *drmmode_obj;
6292 struct intel_crtc *crtc;
08d7b3d1 6293
1cff8f6b
DV		 6294 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6295 return -ENODEV;
08d7b3d1 6296
c05422d5
DV		 6297 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6298 DRM_MODE_OBJECT_CRTC);
08d7b3d1 6299
c05422d5 6300 if (!drmmode_obj) {
08d7b3d1
CW		 6301 DRM_ERROR("no such CRTC id\n");
6302 return -EINVAL;
6303 }
6304
c05422d5
DV		 6305 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6306 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 6307
c05422d5 6308 return 0;
08d7b3d1
CW		 6309}
6310
c5e4df33 6311static int intel_encoder_clones(struct drm_device *dev, int type_mask)
79e53945 6312{
4ef69c7a 6313 struct intel_encoder *encoder;
79e53945 6314 int index_mask = 0;
79e53945
JB		 6315 int entry = 0;
6316
4ef69c7a
CW		 6317 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6318 if (type_mask & encoder->clone_mask)
79e53945
JB		 6319 index_mask |= (1 << entry);
6320 entry++;
6321 }
4ef69c7a 6322
79e53945
JB		 6323 return index_mask;
6324}
6325
4d302442
CW		 6326static bool has_edp_a(struct drm_device *dev)
6327{
6328 struct drm_i915_private *dev_priv = dev->dev_private;
6329
6330 if (!IS_MOBILE(dev))
6331 return false;
6332
6333 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6334 return false;
6335
6336 if (IS_GEN5(dev) &&
6337 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6338 return false;
6339
6340 return true;
6341}
6342
79e53945
JB		 6343static void intel_setup_outputs(struct drm_device *dev)
6344{
725e30ad 6345 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 6346 struct intel_encoder *encoder;
cb0953d7 6347 bool dpd_is_edp = false;
f3cfcba6 6348 bool has_lvds;
79e53945 6349
f3cfcba6 6350 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 6351 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6352 /* disable the panel fitter on everything but LVDS */
6353 I915_WRITE(PFIT_CONTROL, 0);
6354 }
79e53945 6355
bad720ff 6356 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 6357 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 6358
4d302442 6359 if (has_edp_a(dev))
32f9d658
ZW		 6360 intel_dp_init(dev, DP_A);
6361
cb0953d7
AJ		 6362 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6363 intel_dp_init(dev, PCH_DP_D);
6364 }
6365
6366 intel_crt_init(dev);
6367
6368 if (HAS_PCH_SPLIT(dev)) {
6369 int found;
6370
30ad48b7 6371 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca 6372 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 6373 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7
ZW		 6374 if (!found)
6375 intel_hdmi_init(dev, HDMIB);
5eb08b69
ZW		 6376 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6377 intel_dp_init(dev, PCH_DP_B);
30ad48b7
ZW		 6378 }
6379
6380 if (I915_READ(HDMIC) & PORT_DETECTED)
6381 intel_hdmi_init(dev, HDMIC);
6382
6383 if (I915_READ(HDMID) & PORT_DETECTED)
6384 intel_hdmi_init(dev, HDMID);
6385
5eb08b69
ZW		 6386 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6387 intel_dp_init(dev, PCH_DP_C);
6388
cb0953d7 6389 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5eb08b69
ZW		 6390 intel_dp_init(dev, PCH_DP_D);
6391
103a196f 6392 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 6393 bool found = false;
7d57382e 6394
725e30ad 6395 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 6396 DRM_DEBUG_KMS("probing SDVOB\n");
eef4eacb 6397 found = intel_sdvo_init(dev, SDVOB, true);
b01f2c3a
JB		 6398 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6399 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
725e30ad 6400 intel_hdmi_init(dev, SDVOB);
b01f2c3a 6401 }
27185ae1 6402
b01f2c3a
JB		 6403 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6404 DRM_DEBUG_KMS("probing DP_B\n");
a4fc5ed6 6405 intel_dp_init(dev, DP_B);
b01f2c3a 6406 }
725e30ad 6407 }
13520b05
KH		 6408
6409 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 6410
b01f2c3a
JB		 6411 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6412 DRM_DEBUG_KMS("probing SDVOC\n");
eef4eacb 6413 found = intel_sdvo_init(dev, SDVOC, false);
b01f2c3a 6414 }
27185ae1
ML		 6415
6416 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6417
b01f2c3a
JB		 6418 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6419 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
725e30ad 6420 intel_hdmi_init(dev, SDVOC);
b01f2c3a
JB		 6421 }
6422 if (SUPPORTS_INTEGRATED_DP(dev)) {
6423 DRM_DEBUG_KMS("probing DP_C\n");
a4fc5ed6 6424 intel_dp_init(dev, DP_C);
b01f2c3a 6425 }
725e30ad 6426 }
27185ae1 6427
b01f2c3a
JB		 6428 if (SUPPORTS_INTEGRATED_DP(dev) &&
6429 (I915_READ(DP_D) & DP_DETECTED)) {
6430 DRM_DEBUG_KMS("probing DP_D\n");
a4fc5ed6 6431 intel_dp_init(dev, DP_D);
b01f2c3a 6432 }
bad720ff 6433 } else if (IS_GEN2(dev))
79e53945
JB		 6434 intel_dvo_init(dev);
6435
103a196f 6436 if (SUPPORTS_TV(dev))
79e53945
JB		 6437 intel_tv_init(dev);
6438
4ef69c7a
CW		 6439 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6440 encoder->base.possible_crtcs = encoder->crtc_mask;
6441 encoder->base.possible_clones =
6442 intel_encoder_clones(dev, encoder->clone_mask);
79e53945 6443 }
47356eb6 6444
2c7111db
CW		 6445 /* disable all the possible outputs/crtcs before entering KMS mode */
6446 drm_helper_disable_unused_functions(dev);
9fb526db
KP		 6447
6448 if (HAS_PCH_SPLIT(dev))
6449 ironlake_init_pch_refclk(dev);
79e53945
JB		 6450}
6451
6452static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6453{
6454 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 6455
6456 drm_framebuffer_cleanup(fb);
05394f39 6457 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 6458
6459 kfree(intel_fb);
6460}
6461
6462static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 6463 struct drm_file *file,
79e53945
JB		 6464 unsigned int *handle)
6465{
6466 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 6467 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 6468
05394f39 6469 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 6470}
6471
6472static const struct drm_framebuffer_funcs intel_fb_funcs = {
6473 .destroy = intel_user_framebuffer_destroy,
6474 .create_handle = intel_user_framebuffer_create_handle,
6475};
6476
38651674
DA		 6477int intel_framebuffer_init(struct drm_device *dev,
6478 struct intel_framebuffer *intel_fb,
308e5bcb 6479 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 6480 struct drm_i915_gem_object *obj)
79e53945 6481{
79e53945
JB		 6482 int ret;
6483
05394f39 6484 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 6485 return -EINVAL;
6486
308e5bcb 6487 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 6488 return -EINVAL;
6489
308e5bcb 6490 switch (mode_cmd->pixel_format) {
04b3924d
VS		 6491 case DRM_FORMAT_RGB332:
6492 case DRM_FORMAT_RGB565:
6493 case DRM_FORMAT_XRGB8888:
b250da79 6494 case DRM_FORMAT_XBGR8888:
04b3924d
VS		 6495 case DRM_FORMAT_ARGB8888:
6496 case DRM_FORMAT_XRGB2101010:
6497 case DRM_FORMAT_ARGB2101010:
308e5bcb 6498 /* RGB formats are common across chipsets */
b5626747 6499 break;
04b3924d
VS		 6500 case DRM_FORMAT_YUYV:
6501 case DRM_FORMAT_UYVY:
6502 case DRM_FORMAT_YVYU:
6503 case DRM_FORMAT_VYUY:
57cd6508
CW		 6504 break;
6505 default:
aca25848
ED		 6506 DRM_DEBUG_KMS("unsupported pixel format %u\n",
6507 mode_cmd->pixel_format);
57cd6508
CW		 6508 return -EINVAL;
6509 }
6510
79e53945
JB		 6511 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6512 if (ret) {
6513 DRM_ERROR("framebuffer init failed %d\n", ret);
6514 return ret;
6515 }
6516
6517 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 6518 intel_fb->obj = obj;
79e53945
JB		 6519 return 0;
6520}
6521
79e53945
JB		 6522static struct drm_framebuffer *
6523intel_user_framebuffer_create(struct drm_device *dev,
6524 struct drm_file *filp,
308e5bcb 6525 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 6526{
05394f39 6527 struct drm_i915_gem_object *obj;
79e53945 6528
308e5bcb
JB		 6529 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
6530 mode_cmd->handles[0]));
c8725226 6531 if (&obj->base == NULL)
cce13ff7 6532 return ERR_PTR(-ENOENT);
79e53945 6533
d2dff872 6534 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 6535}
6536
79e53945 6537static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 6538 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 6539 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 6540};
6541
e70236a8
JB		 6542/* Set up chip specific display functions */
6543static void intel_init_display(struct drm_device *dev)
6544{
6545 struct drm_i915_private *dev_priv = dev->dev_private;
6546
6547 /* We always want a DPMS function */
f564048e 6548 if (HAS_PCH_SPLIT(dev)) {
f2b115e6 6549 dev_priv->display.dpms = ironlake_crtc_dpms;
f564048e 6550 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
ee7b9f93 6551 dev_priv->display.off = ironlake_crtc_off;
17638cd6 6552 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 6553 } else {
e70236a8 6554 dev_priv->display.dpms = i9xx_crtc_dpms;
f564048e 6555 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
ee7b9f93 6556 dev_priv->display.off = i9xx_crtc_off;
17638cd6 6557 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 6558 }
e70236a8 6559
e70236a8 6560 /* Returns the core display clock speed */
25eb05fc
JB		 6561 if (IS_VALLEYVIEW(dev))
6562 dev_priv->display.get_display_clock_speed =
6563 valleyview_get_display_clock_speed;
6564 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 6565 dev_priv->display.get_display_clock_speed =
6566 i945_get_display_clock_speed;
6567 else if (IS_I915G(dev))
6568 dev_priv->display.get_display_clock_speed =
6569 i915_get_display_clock_speed;
f2b115e6 6570 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 6571 dev_priv->display.get_display_clock_speed =
6572 i9xx_misc_get_display_clock_speed;
6573 else if (IS_I915GM(dev))
6574 dev_priv->display.get_display_clock_speed =
6575 i915gm_get_display_clock_speed;
6576 else if (IS_I865G(dev))
6577 dev_priv->display.get_display_clock_speed =
6578 i865_get_display_clock_speed;
f0f8a9ce 6579 else if (IS_I85X(dev))
e70236a8
JB		 6580 dev_priv->display.get_display_clock_speed =
6581 i855_get_display_clock_speed;
6582 else /* 852, 830 */
6583 dev_priv->display.get_display_clock_speed =
6584 i830_get_display_clock_speed;
6585
7f8a8569 6586 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 6587 if (IS_GEN5(dev)) {
674cf967 6588 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 6589 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 6590 } else if (IS_GEN6(dev)) {
674cf967 6591 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 6592 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 6593 } else if (IS_IVYBRIDGE(dev)) {
6594 /* FIXME: detect B0+ stepping and use auto training */
6595 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 6596 dev_priv->display.write_eld = ironlake_write_eld;
7f8a8569
ZW		 6597 } else
6598 dev_priv->display.update_wm = NULL;
ceb04246 6599 } else if (IS_VALLEYVIEW(dev)) {
575155a9
JB		 6600 dev_priv->display.force_wake_get = vlv_force_wake_get;
6601 dev_priv->display.force_wake_put = vlv_force_wake_put;
6067aaea 6602 } else if (IS_G4X(dev)) {
e0dac65e 6603 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 6604 }
8c9f3aaf
JB		 6605
6606 /* Default just returns -ENODEV to indicate unsupported */
6607 dev_priv->display.queue_flip = intel_default_queue_flip;
6608
6609 switch (INTEL_INFO(dev)->gen) {
6610 case 2:
6611 dev_priv->display.queue_flip = intel_gen2_queue_flip;
6612 break;
6613
6614 case 3:
6615 dev_priv->display.queue_flip = intel_gen3_queue_flip;
6616 break;
6617
6618 case 4:
6619 case 5:
6620 dev_priv->display.queue_flip = intel_gen4_queue_flip;
6621 break;
6622
6623 case 6:
6624 dev_priv->display.queue_flip = intel_gen6_queue_flip;
6625 break;
7c9017e5
JB		 6626 case 7:
6627 dev_priv->display.queue_flip = intel_gen7_queue_flip;
6628 break;
8c9f3aaf 6629 }
e70236a8
JB		 6630}
6631
b690e96c
JB		 6632/*
6633 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
6634 * resume, or other times. This quirk makes sure that's the case for
6635 * affected systems.
6636 */
0206e353 6637static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 6638{
6639 struct drm_i915_private *dev_priv = dev->dev_private;
6640
6641 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 6642 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 6643}
6644
435793df
KP		 6645/*
6646 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
6647 */
6648static void quirk_ssc_force_disable(struct drm_device *dev)
6649{
6650 struct drm_i915_private *dev_priv = dev->dev_private;
6651 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 6652 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 6653}
6654
4dca20ef 6655/*
5a15ab5b
CE		 6656 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
6657 * brightness value
4dca20ef
CE		 6658 */
6659static void quirk_invert_brightness(struct drm_device *dev)
6660{
6661 struct drm_i915_private *dev_priv = dev->dev_private;
6662 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 6663 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 6664}
6665
b690e96c
JB		 6666struct intel_quirk {
6667 int device;
6668 int subsystem_vendor;
6669 int subsystem_device;
6670 void (*hook)(struct drm_device *dev);
6671};
6672
c43b5634 6673static struct intel_quirk intel_quirks[] = {
b690e96c 6674 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 6675 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c
JB		 6676
6677 /* Thinkpad R31 needs pipe A force quirk */
6678 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
6679 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
6680 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
6681
6682 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
6683 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
6684 /* ThinkPad X40 needs pipe A force quirk */
6685
6686 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
6687 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
6688
6689 /* 855 & before need to leave pipe A & dpll A up */
6690 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6691 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 6692
6693 /* Lenovo U160 cannot use SSC on LVDS */
6694 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 6695
6696 /* Sony Vaio Y cannot use SSC on LVDS */
6697 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 6698
6699 /* Acer Aspire 5734Z must invert backlight brightness */
6700 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
b690e96c
JB		 6701};
6702
6703static void intel_init_quirks(struct drm_device *dev)
6704{
6705 struct pci_dev *d = dev->pdev;
6706 int i;
6707
6708 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
6709 struct intel_quirk *q = &intel_quirks[i];
6710
6711 if (d->device == q->device &&
6712 (d->subsystem_vendor == q->subsystem_vendor ||
6713 q->subsystem_vendor == PCI_ANY_ID) &&
6714 (d->subsystem_device == q->subsystem_device ||
6715 q->subsystem_device == PCI_ANY_ID))
6716 q->hook(dev);
6717 }
6718}
6719
9cce37f4
JB		 6720/* Disable the VGA plane that we never use */
6721static void i915_disable_vga(struct drm_device *dev)
6722{
6723 struct drm_i915_private *dev_priv = dev->dev_private;
6724 u8 sr1;
6725 u32 vga_reg;
6726
6727 if (HAS_PCH_SPLIT(dev))
6728 vga_reg = CPU_VGACNTRL;
6729 else
6730 vga_reg = VGACNTRL;
6731
6732 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 6733 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 6734 sr1 = inb(VGA_SR_DATA);
6735 outb(sr1 | 1<<5, VGA_SR_DATA);
6736 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6737 udelay(300);
6738
6739 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6740 POSTING_READ(vga_reg);
6741}
6742
f82cfb6b
JB		 6743static void ivb_pch_pwm_override(struct drm_device *dev)
6744{
6745 struct drm_i915_private *dev_priv = dev->dev_private;
6746
6747 /*
6748 * IVB has CPU eDP backlight regs too, set things up to let the
6749 * PCH regs control the backlight
6750 */
6751 I915_WRITE(BLC_PWM_CPU_CTL2, PWM_ENABLE);
6752 I915_WRITE(BLC_PWM_CPU_CTL, 0);
6753 I915_WRITE(BLC_PWM_PCH_CTL1, PWM_ENABLE | (1<<30));
6754}
6755
f817586c
DV		 6756void intel_modeset_init_hw(struct drm_device *dev)
6757{
6758 struct drm_i915_private *dev_priv = dev->dev_private;
6759
6760 intel_init_clock_gating(dev);
6761
6762 if (IS_IRONLAKE_M(dev)) {
6763 ironlake_enable_drps(dev);
1833b134 6764 ironlake_enable_rc6(dev);
f817586c
DV		 6765 intel_init_emon(dev);
6766 }
6767
b6834bd6 6768 if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
f817586c
DV		 6769 gen6_enable_rps(dev_priv);
6770 gen6_update_ring_freq(dev_priv);
6771 }
f82cfb6b
JB		 6772
6773 if (IS_IVYBRIDGE(dev))
6774 ivb_pch_pwm_override(dev);
f817586c
DV		 6775}
6776
79e53945
JB		 6777void intel_modeset_init(struct drm_device *dev)
6778{
652c393a 6779 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 6780 int i, ret;
79e53945
JB		 6781
6782 drm_mode_config_init(dev);
6783
6784 dev->mode_config.min_width = 0;
6785 dev->mode_config.min_height = 0;
6786
019d96cb
DA		 6787 dev->mode_config.preferred_depth = 24;
6788 dev->mode_config.prefer_shadow = 1;
6789
79e53945
JB		 6790 dev->mode_config.funcs = (void *)&intel_mode_funcs;
6791
b690e96c
JB		 6792 intel_init_quirks(dev);
6793
1fa61106
ED		 6794 intel_init_pm(dev);
6795
e70236a8
JB		 6796 intel_init_display(dev);
6797
a6c45cf0
CW		 6798 if (IS_GEN2(dev)) {
6799 dev->mode_config.max_width = 2048;
6800 dev->mode_config.max_height = 2048;
6801 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 6802 dev->mode_config.max_width = 4096;
6803 dev->mode_config.max_height = 4096;
79e53945 6804 } else {
a6c45cf0
CW		 6805 dev->mode_config.max_width = 8192;
6806 dev->mode_config.max_height = 8192;
79e53945 6807 }
35c3047a 6808 dev->mode_config.fb_base = dev->agp->base;
79e53945 6809
28c97730 6810 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 6811 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 6812
a3524f1b 6813 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 6814 intel_crtc_init(dev, i);
00c2064b
JB		 6815 ret = intel_plane_init(dev, i);
6816 if (ret)
6817 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 6818 }
6819
ee7b9f93
JB		 6820 intel_pch_pll_init(dev);
6821
9cce37f4
JB		 6822 /* Just disable it once at startup */
6823 i915_disable_vga(dev);
79e53945 6824 intel_setup_outputs(dev);
652c393a 6825
652c393a
JB		 6826 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6827 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6828 (unsigned long)dev);
2c7111db
CW		 6829}
6830
6831void intel_modeset_gem_init(struct drm_device *dev)
6832{
1833b134 6833 intel_modeset_init_hw(dev);
02e792fb
DV		 6834
6835 intel_setup_overlay(dev);
79e53945
JB		 6836}
6837
6838void intel_modeset_cleanup(struct drm_device *dev)
6839{
652c393a
JB		 6840 struct drm_i915_private *dev_priv = dev->dev_private;
6841 struct drm_crtc *crtc;
6842 struct intel_crtc *intel_crtc;
6843
f87ea761 6844 drm_kms_helper_poll_fini(dev);
652c393a
JB		 6845 mutex_lock(&dev->struct_mutex);
6846
723bfd70
JB		 6847 intel_unregister_dsm_handler();
6848
6849
652c393a
JB		 6850 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6851 /* Skip inactive CRTCs */
6852 if (!crtc->fb)
6853 continue;
6854
6855 intel_crtc = to_intel_crtc(crtc);
3dec0095 6856 intel_increase_pllclock(crtc);
652c393a
JB		 6857 }
6858
973d04f9 6859 intel_disable_fbc(dev);
e70236a8 6860
f97108d1
JB		 6861 if (IS_IRONLAKE_M(dev))
6862 ironlake_disable_drps(dev);
b6834bd6 6863 if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev))
3b8d8d91 6864 gen6_disable_rps(dev);
f97108d1 6865
d5bb081b
JB		 6866 if (IS_IRONLAKE_M(dev))
6867 ironlake_disable_rc6(dev);
0cdab21f 6868
57f350b6
JB		 6869 if (IS_VALLEYVIEW(dev))
6870 vlv_init_dpio(dev);
6871
69341a5e
KH		 6872 mutex_unlock(&dev->struct_mutex);
6873
6c0d9350
DV		 6874 /* Disable the irq before mode object teardown, for the irq might
6875 * enqueue unpin/hotplug work. */
6876 drm_irq_uninstall(dev);
6877 cancel_work_sync(&dev_priv->hotplug_work);
6fdd4d98 6878 cancel_work_sync(&dev_priv->rps_work);
6c0d9350 6879
1630fe75
CW		 6880 /* flush any delayed tasks or pending work */
6881 flush_scheduled_work();
6882
3dec0095
DV		 6883 /* Shut off idle work before the crtcs get freed. */
6884 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6885 intel_crtc = to_intel_crtc(crtc);
6886 del_timer_sync(&intel_crtc->idle_timer);
6887 }
6888 del_timer_sync(&dev_priv->idle_timer);
6889 cancel_work_sync(&dev_priv->idle_work);
6890
79e53945
JB		 6891 drm_mode_config_cleanup(dev);
6892}
6893
f1c79df3
ZW		 6894/*
6895 * Return which encoder is currently attached for connector.
6896 */
df0e9248 6897struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 6898{
df0e9248
CW		 6899 return &intel_attached_encoder(connector)->base;
6900}
f1c79df3 6901
df0e9248
CW		 6902void intel_connector_attach_encoder(struct intel_connector *connector,
6903 struct intel_encoder *encoder)
6904{
6905 connector->encoder = encoder;
6906 drm_mode_connector_attach_encoder(&connector->base,
6907 &encoder->base);
79e53945 6908}
28d52043
DA		 6909
6910/*
6911 * set vga decode state - true == enable VGA decode
6912 */
6913int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6914{
6915 struct drm_i915_private *dev_priv = dev->dev_private;
6916 u16 gmch_ctrl;
6917
6918 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6919 if (state)
6920 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6921 else
6922 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6923 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6924 return 0;
6925}
c4a1d9e4
CW		 6926
6927#ifdef CONFIG_DEBUG_FS
6928#include <linux/seq_file.h>
6929
6930struct intel_display_error_state {
6931 struct intel_cursor_error_state {
6932 u32 control;
6933 u32 position;
6934 u32 base;
6935 u32 size;
6936 } cursor[2];
6937
6938 struct intel_pipe_error_state {
6939 u32 conf;
6940 u32 source;
6941
6942 u32 htotal;
6943 u32 hblank;
6944 u32 hsync;
6945 u32 vtotal;
6946 u32 vblank;
6947 u32 vsync;
6948 } pipe[2];
6949
6950 struct intel_plane_error_state {
6951 u32 control;
6952 u32 stride;
6953 u32 size;
6954 u32 pos;
6955 u32 addr;
6956 u32 surface;
6957 u32 tile_offset;
6958 } plane[2];
6959};
6960
6961struct intel_display_error_state *
6962intel_display_capture_error_state(struct drm_device *dev)
6963{
0206e353 6964 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 6965 struct intel_display_error_state *error;
6966 int i;
6967
6968 error = kmalloc(sizeof(*error), GFP_ATOMIC);
6969 if (error == NULL)
6970 return NULL;
6971
6972 for (i = 0; i < 2; i++) {
6973 error->cursor[i].control = I915_READ(CURCNTR(i));
6974 error->cursor[i].position = I915_READ(CURPOS(i));
6975 error->cursor[i].base = I915_READ(CURBASE(i));
6976
6977 error->plane[i].control = I915_READ(DSPCNTR(i));
6978 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
6979 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 6980 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 6981 error->plane[i].addr = I915_READ(DSPADDR(i));
6982 if (INTEL_INFO(dev)->gen >= 4) {
6983 error->plane[i].surface = I915_READ(DSPSURF(i));
6984 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
6985 }
6986
6987 error->pipe[i].conf = I915_READ(PIPECONF(i));
6988 error->pipe[i].source = I915_READ(PIPESRC(i));
6989 error->pipe[i].htotal = I915_READ(HTOTAL(i));
6990 error->pipe[i].hblank = I915_READ(HBLANK(i));
6991 error->pipe[i].hsync = I915_READ(HSYNC(i));
6992 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
6993 error->pipe[i].vblank = I915_READ(VBLANK(i));
6994 error->pipe[i].vsync = I915_READ(VSYNC(i));
6995 }
6996
6997 return error;
6998}
6999
7000void
7001intel_display_print_error_state(struct seq_file *m,
7002 struct drm_device *dev,
7003 struct intel_display_error_state *error)
7004{
7005 int i;
7006
7007 for (i = 0; i < 2; i++) {
7008 seq_printf(m, "Pipe [%d]:\n", i);
7009 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
7010 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
7011 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
7012 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
7013 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
7014 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
7015 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
7016 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
7017
7018 seq_printf(m, "Plane [%d]:\n", i);
7019 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
7020 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
7021 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
7022 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
7023 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
7024 if (INTEL_INFO(dev)->gen >= 4) {
7025 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
7026 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
7027 }
7028
7029 seq_printf(m, "Cursor [%d]:\n", i);
7030 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
7031 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
7032 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
7033 }
7034}
7035#endif
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