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drm/i915: De-magic the VLV p2 divider step size
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
3dec0095 44static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 45static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 46
f1f644dc
JB		 47static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
48 struct intel_crtc_config *pipe_config);
18442d08
VS		 49static void ironlake_pch_clock_get(struct intel_crtc *crtc,
50 struct intel_crtc_config *pipe_config);
f1f644dc 51
e7457a9a
DL		 52static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
53 int x, int y, struct drm_framebuffer *old_fb);
54
55
79e53945 56typedef struct {
0206e353 57 int min, max;
79e53945
JB		 58} intel_range_t;
59
60typedef struct {
0206e353
AJ		 61 int dot_limit;
62 int p2_slow, p2_fast;
79e53945
JB		 63} intel_p2_t;
64
d4906093
ML		 65typedef struct intel_limit intel_limit_t;
66struct intel_limit {
0206e353
AJ		 67 intel_range_t dot, vco, n, m, m1, m2, p, p1;
68 intel_p2_t p2;
d4906093 69};
79e53945 70
d2acd215
DV		 71int
72intel_pch_rawclk(struct drm_device *dev)
73{
74 struct drm_i915_private *dev_priv = dev->dev_private;
75
76 WARN_ON(!HAS_PCH_SPLIT(dev));
77
78 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
79}
80
021357ac
CW		 81static inline u32 /* units of 100MHz */
82intel_fdi_link_freq(struct drm_device *dev)
83{
8b99e68c
CW		 84 if (IS_GEN5(dev)) {
85 struct drm_i915_private *dev_priv = dev->dev_private;
86 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
87 } else
88 return 27;
021357ac
CW		 89}
90
5d536e28 91static const intel_limit_t intel_limits_i8xx_dac = {
0206e353
AJ		 92 .dot = { .min = 25000, .max = 350000 },
93 .vco = { .min = 930000, .max = 1400000 },
94 .n = { .min = 3, .max = 16 },
95 .m = { .min = 96, .max = 140 },
96 .m1 = { .min = 18, .max = 26 },
97 .m2 = { .min = 6, .max = 16 },
98 .p = { .min = 4, .max = 128 },
99 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 100 .p2 = { .dot_limit = 165000,
101 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 102};
103
5d536e28
DV		 104static const intel_limit_t intel_limits_i8xx_dvo = {
105 .dot = { .min = 25000, .max = 350000 },
106 .vco = { .min = 930000, .max = 1400000 },
107 .n = { .min = 3, .max = 16 },
108 .m = { .min = 96, .max = 140 },
109 .m1 = { .min = 18, .max = 26 },
110 .m2 = { .min = 6, .max = 16 },
111 .p = { .min = 4, .max = 128 },
112 .p1 = { .min = 2, .max = 33 },
113 .p2 = { .dot_limit = 165000,
114 .p2_slow = 4, .p2_fast = 4 },
115};
116
e4b36699 117static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 118 .dot = { .min = 25000, .max = 350000 },
119 .vco = { .min = 930000, .max = 1400000 },
120 .n = { .min = 3, .max = 16 },
121 .m = { .min = 96, .max = 140 },
122 .m1 = { .min = 18, .max = 26 },
123 .m2 = { .min = 6, .max = 16 },
124 .p = { .min = 4, .max = 128 },
125 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 126 .p2 = { .dot_limit = 165000,
127 .p2_slow = 14, .p2_fast = 7 },
e4b36699 128};
273e27ca 129
e4b36699 130static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 131 .dot = { .min = 20000, .max = 400000 },
132 .vco = { .min = 1400000, .max = 2800000 },
133 .n = { .min = 1, .max = 6 },
134 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 135 .m1 = { .min = 8, .max = 18 },
136 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 137 .p = { .min = 5, .max = 80 },
138 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 139 .p2 = { .dot_limit = 200000,
140 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 141};
142
143static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 144 .dot = { .min = 20000, .max = 400000 },
145 .vco = { .min = 1400000, .max = 2800000 },
146 .n = { .min = 1, .max = 6 },
147 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 148 .m1 = { .min = 8, .max = 18 },
149 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 150 .p = { .min = 7, .max = 98 },
151 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 152 .p2 = { .dot_limit = 112000,
153 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 154};
155
273e27ca 156
e4b36699 157static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 158 .dot = { .min = 25000, .max = 270000 },
159 .vco = { .min = 1750000, .max = 3500000},
160 .n = { .min = 1, .max = 4 },
161 .m = { .min = 104, .max = 138 },
162 .m1 = { .min = 17, .max = 23 },
163 .m2 = { .min = 5, .max = 11 },
164 .p = { .min = 10, .max = 30 },
165 .p1 = { .min = 1, .max = 3},
166 .p2 = { .dot_limit = 270000,
167 .p2_slow = 10,
168 .p2_fast = 10
044c7c41 169 },
e4b36699
KP		 170};
171
172static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 173 .dot = { .min = 22000, .max = 400000 },
174 .vco = { .min = 1750000, .max = 3500000},
175 .n = { .min = 1, .max = 4 },
176 .m = { .min = 104, .max = 138 },
177 .m1 = { .min = 16, .max = 23 },
178 .m2 = { .min = 5, .max = 11 },
179 .p = { .min = 5, .max = 80 },
180 .p1 = { .min = 1, .max = 8},
181 .p2 = { .dot_limit = 165000,
182 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 183};
184
185static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 186 .dot = { .min = 20000, .max = 115000 },
187 .vco = { .min = 1750000, .max = 3500000 },
188 .n = { .min = 1, .max = 3 },
189 .m = { .min = 104, .max = 138 },
190 .m1 = { .min = 17, .max = 23 },
191 .m2 = { .min = 5, .max = 11 },
192 .p = { .min = 28, .max = 112 },
193 .p1 = { .min = 2, .max = 8 },
194 .p2 = { .dot_limit = 0,
195 .p2_slow = 14, .p2_fast = 14
044c7c41 196 },
e4b36699
KP		 197};
198
199static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 200 .dot = { .min = 80000, .max = 224000 },
201 .vco = { .min = 1750000, .max = 3500000 },
202 .n = { .min = 1, .max = 3 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 17, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 14, .max = 42 },
207 .p1 = { .min = 2, .max = 6 },
208 .p2 = { .dot_limit = 0,
209 .p2_slow = 7, .p2_fast = 7
044c7c41 210 },
e4b36699
KP		 211};
212
f2b115e6 213static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 214 .dot = { .min = 20000, .max = 400000},
215 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 216 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 217 .n = { .min = 3, .max = 6 },
218 .m = { .min = 2, .max = 256 },
273e27ca 219 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 220 .m1 = { .min = 0, .max = 0 },
221 .m2 = { .min = 0, .max = 254 },
222 .p = { .min = 5, .max = 80 },
223 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 224 .p2 = { .dot_limit = 200000,
225 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 226};
227
f2b115e6 228static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 229 .dot = { .min = 20000, .max = 400000 },
230 .vco = { .min = 1700000, .max = 3500000 },
231 .n = { .min = 3, .max = 6 },
232 .m = { .min = 2, .max = 256 },
233 .m1 = { .min = 0, .max = 0 },
234 .m2 = { .min = 0, .max = 254 },
235 .p = { .min = 7, .max = 112 },
236 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 237 .p2 = { .dot_limit = 112000,
238 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 239};
240
273e27ca
EA		 241/* Ironlake / Sandybridge
242 *
243 * We calculate clock using (register_value + 2) for N/M1/M2, so here
244 * the range value for them is (actual_value - 2).
245 */
b91ad0ec 246static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 247 .dot = { .min = 25000, .max = 350000 },
248 .vco = { .min = 1760000, .max = 3510000 },
249 .n = { .min = 1, .max = 5 },
250 .m = { .min = 79, .max = 127 },
251 .m1 = { .min = 12, .max = 22 },
252 .m2 = { .min = 5, .max = 9 },
253 .p = { .min = 5, .max = 80 },
254 .p1 = { .min = 1, .max = 8 },
255 .p2 = { .dot_limit = 225000,
256 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 257};
258
b91ad0ec 259static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 260 .dot = { .min = 25000, .max = 350000 },
261 .vco = { .min = 1760000, .max = 3510000 },
262 .n = { .min = 1, .max = 3 },
263 .m = { .min = 79, .max = 118 },
264 .m1 = { .min = 12, .max = 22 },
265 .m2 = { .min = 5, .max = 9 },
266 .p = { .min = 28, .max = 112 },
267 .p1 = { .min = 2, .max = 8 },
268 .p2 = { .dot_limit = 225000,
269 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 270};
271
272static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 273 .dot = { .min = 25000, .max = 350000 },
274 .vco = { .min = 1760000, .max = 3510000 },
275 .n = { .min = 1, .max = 3 },
276 .m = { .min = 79, .max = 127 },
277 .m1 = { .min = 12, .max = 22 },
278 .m2 = { .min = 5, .max = 9 },
279 .p = { .min = 14, .max = 56 },
280 .p1 = { .min = 2, .max = 8 },
281 .p2 = { .dot_limit = 225000,
282 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 283};
284
273e27ca 285/* LVDS 100mhz refclk limits. */
b91ad0ec 286static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 287 .dot = { .min = 25000, .max = 350000 },
288 .vco = { .min = 1760000, .max = 3510000 },
289 .n = { .min = 1, .max = 2 },
290 .m = { .min = 79, .max = 126 },
291 .m1 = { .min = 12, .max = 22 },
292 .m2 = { .min = 5, .max = 9 },
293 .p = { .min = 28, .max = 112 },
0206e353 294 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 295 .p2 = { .dot_limit = 225000,
296 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 297};
298
299static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 300 .dot = { .min = 25000, .max = 350000 },
301 .vco = { .min = 1760000, .max = 3510000 },
302 .n = { .min = 1, .max = 3 },
303 .m = { .min = 79, .max = 126 },
304 .m1 = { .min = 12, .max = 22 },
305 .m2 = { .min = 5, .max = 9 },
306 .p = { .min = 14, .max = 42 },
0206e353 307 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 308 .p2 = { .dot_limit = 225000,
309 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 310};
311
a0c4da24
JB		 312static const intel_limit_t intel_limits_vlv_dac = {
313 .dot = { .min = 25000, .max = 270000 },
314 .vco = { .min = 4000000, .max = 6000000 },
315 .n = { .min = 1, .max = 7 },
316 .m = { .min = 22, .max = 450 }, /* guess */
317 .m1 = { .min = 2, .max = 3 },
318 .m2 = { .min = 11, .max = 156 },
319 .p = { .min = 10, .max = 30 },
75e53986 320 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 321 .p2 = { .dot_limit = 270000,
322 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 323};
324
325static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 326 .dot = { .min = 25000, .max = 270000 },
327 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 328 .n = { .min = 1, .max = 7 },
329 .m = { .min = 60, .max = 300 }, /* guess */
330 .m1 = { .min = 2, .max = 3 },
331 .m2 = { .min = 11, .max = 156 },
332 .p = { .min = 10, .max = 30 },
333 .p1 = { .min = 2, .max = 3 },
334 .p2 = { .dot_limit = 270000,
335 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 336};
337
6b4bf1c4
VS		 338static void vlv_clock(int refclk, intel_clock_t *clock)
339{
340 clock->m = clock->m1 * clock->m2;
341 clock->p = clock->p1 * clock->p2;
342 clock->vco = refclk * clock->m / clock->n;
343 clock->dot = clock->vco / clock->p;
344}
345
e0638cdf
PZ		 346/**
347 * Returns whether any output on the specified pipe is of the specified type
348 */
349static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
350{
351 struct drm_device *dev = crtc->dev;
352 struct intel_encoder *encoder;
353
354 for_each_encoder_on_crtc(dev, crtc, encoder)
355 if (encoder->type == type)
356 return true;
357
358 return false;
359}
360
1b894b59
CW		 361static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
362 int refclk)
2c07245f 363{
b91ad0ec 364 struct drm_device *dev = crtc->dev;
2c07245f 365 const intel_limit_t *limit;
b91ad0ec
ZW		 366
367 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 368 if (intel_is_dual_link_lvds(dev)) {
1b894b59 369 if (refclk == 100000)
b91ad0ec
ZW		 370 limit = &intel_limits_ironlake_dual_lvds_100m;
371 else
372 limit = &intel_limits_ironlake_dual_lvds;
373 } else {
1b894b59 374 if (refclk == 100000)
b91ad0ec
ZW		 375 limit = &intel_limits_ironlake_single_lvds_100m;
376 else
377 limit = &intel_limits_ironlake_single_lvds;
378 }
c6bb3538 379 } else
b91ad0ec 380 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 381
382 return limit;
383}
384
044c7c41
ML		 385static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
386{
387 struct drm_device *dev = crtc->dev;
044c7c41
ML		 388 const intel_limit_t *limit;
389
390 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 391 if (intel_is_dual_link_lvds(dev))
e4b36699 392 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 393 else
e4b36699 394 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 395 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
396 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 397 limit = &intel_limits_g4x_hdmi;
044c7c41 398 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 399 limit = &intel_limits_g4x_sdvo;
044c7c41 400 } else /* The option is for other outputs */
e4b36699 401 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 402
403 return limit;
404}
405
1b894b59 406static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 407{
408 struct drm_device *dev = crtc->dev;
409 const intel_limit_t *limit;
410
bad720ff 411 if (HAS_PCH_SPLIT(dev))
1b894b59 412 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 413 else if (IS_G4X(dev)) {
044c7c41 414 limit = intel_g4x_limit(crtc);
f2b115e6 415 } else if (IS_PINEVIEW(dev)) {
2177832f 416 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 417 limit = &intel_limits_pineview_lvds;
2177832f 418 else
f2b115e6 419 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 420 } else if (IS_VALLEYVIEW(dev)) {
421 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
422 limit = &intel_limits_vlv_dac;
a0c4da24 423 else
65ce4bf5 424 limit = &intel_limits_vlv_hdmi;
a6c45cf0
CW		 425 } else if (!IS_GEN2(dev)) {
426 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
427 limit = &intel_limits_i9xx_lvds;
428 else
429 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 430 } else {
431 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 432 limit = &intel_limits_i8xx_lvds;
5d536e28 433 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
e4b36699 434 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 435 else
436 limit = &intel_limits_i8xx_dac;
79e53945
JB		 437 }
438 return limit;
439}
440
f2b115e6
AJ		 441/* m1 is reserved as 0 in Pineview, n is a ring counter */
442static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 443{
2177832f
SL		 444 clock->m = clock->m2 + 2;
445 clock->p = clock->p1 * clock->p2;
446 clock->vco = refclk * clock->m / clock->n;
447 clock->dot = clock->vco / clock->p;
448}
449
7429e9d4
DV		 450static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
451{
452 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
453}
454
ac58c3f0 455static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 456{
7429e9d4 457 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 458 clock->p = clock->p1 * clock->p2;
459 clock->vco = refclk * clock->m / (clock->n + 2);
460 clock->dot = clock->vco / clock->p;
461}
462
7c04d1d9 463#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 464/**
465 * Returns whether the given set of divisors are valid for a given refclk with
466 * the given connectors.
467 */
468
1b894b59
CW		 469static bool intel_PLL_is_valid(struct drm_device *dev,
470 const intel_limit_t *limit,
471 const intel_clock_t *clock)
79e53945 472{
79e53945 473 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 474 INTELPllInvalid("p1 out of range\n");
79e53945 475 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 476 INTELPllInvalid("p out of range\n");
79e53945 477 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 478 INTELPllInvalid("m2 out of range\n");
79e53945 479 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 480 INTELPllInvalid("m1 out of range\n");
f2b115e6 481 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 482 INTELPllInvalid("m1 <= m2\n");
79e53945 483 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 484 INTELPllInvalid("m out of range\n");
79e53945 485 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 486 INTELPllInvalid("n out of range\n");
79e53945 487 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 488 INTELPllInvalid("vco out of range\n");
79e53945
JB		 489 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
490 * connector, etc., rather than just a single range.
491 */
492 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 493 INTELPllInvalid("dot out of range\n");
79e53945
JB		 494
495 return true;
496}
497
d4906093 498static bool
ee9300bb 499i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 500 int target, int refclk, intel_clock_t *match_clock,
501 intel_clock_t *best_clock)
79e53945
JB		 502{
503 struct drm_device *dev = crtc->dev;
79e53945 504 intel_clock_t clock;
79e53945
JB		 505 int err = target;
506
a210b028 507 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 508 /*
a210b028
DV		 509 * For LVDS just rely on its current settings for dual-channel.
510 * We haven't figured out how to reliably set up different
511 * single/dual channel state, if we even can.
79e53945 512 */
1974cad0 513 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 514 clock.p2 = limit->p2.p2_fast;
515 else
516 clock.p2 = limit->p2.p2_slow;
517 } else {
518 if (target < limit->p2.dot_limit)
519 clock.p2 = limit->p2.p2_slow;
520 else
521 clock.p2 = limit->p2.p2_fast;
522 }
523
0206e353 524 memset(best_clock, 0, sizeof(*best_clock));
79e53945 525
42158660
ZY		 526 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
527 clock.m1++) {
528 for (clock.m2 = limit->m2.min;
529 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 530 if (clock.m2 >= clock.m1)
42158660
ZY		 531 break;
532 for (clock.n = limit->n.min;
533 clock.n <= limit->n.max; clock.n++) {
534 for (clock.p1 = limit->p1.min;
535 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 536 int this_err;
537
ac58c3f0
DV		 538 i9xx_clock(refclk, &clock);
539 if (!intel_PLL_is_valid(dev, limit,
540 &clock))
541 continue;
542 if (match_clock &&
543 clock.p != match_clock->p)
544 continue;
545
546 this_err = abs(clock.dot - target);
547 if (this_err < err) {
548 *best_clock = clock;
549 err = this_err;
550 }
551 }
552 }
553 }
554 }
555
556 return (err != target);
557}
558
559static bool
ee9300bb
DV		 560pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
561 int target, int refclk, intel_clock_t *match_clock,
562 intel_clock_t *best_clock)
79e53945
JB		 563{
564 struct drm_device *dev = crtc->dev;
79e53945 565 intel_clock_t clock;
79e53945
JB		 566 int err = target;
567
a210b028 568 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 569 /*
a210b028
DV		 570 * For LVDS just rely on its current settings for dual-channel.
571 * We haven't figured out how to reliably set up different
572 * single/dual channel state, if we even can.
79e53945 573 */
1974cad0 574 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 575 clock.p2 = limit->p2.p2_fast;
576 else
577 clock.p2 = limit->p2.p2_slow;
578 } else {
579 if (target < limit->p2.dot_limit)
580 clock.p2 = limit->p2.p2_slow;
581 else
582 clock.p2 = limit->p2.p2_fast;
583 }
584
0206e353 585 memset(best_clock, 0, sizeof(*best_clock));
79e53945 586
42158660
ZY		 587 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
588 clock.m1++) {
589 for (clock.m2 = limit->m2.min;
590 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 591 for (clock.n = limit->n.min;
592 clock.n <= limit->n.max; clock.n++) {
593 for (clock.p1 = limit->p1.min;
594 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 595 int this_err;
596
ac58c3f0 597 pineview_clock(refclk, &clock);
1b894b59
CW		 598 if (!intel_PLL_is_valid(dev, limit,
599 &clock))
79e53945 600 continue;
cec2f356
SP		 601 if (match_clock &&
602 clock.p != match_clock->p)
603 continue;
79e53945
JB		 604
605 this_err = abs(clock.dot - target);
606 if (this_err < err) {
607 *best_clock = clock;
608 err = this_err;
609 }
610 }
611 }
612 }
613 }
614
615 return (err != target);
616}
617
d4906093 618static bool
ee9300bb
DV		 619g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
620 int target, int refclk, intel_clock_t *match_clock,
621 intel_clock_t *best_clock)
d4906093
ML		 622{
623 struct drm_device *dev = crtc->dev;
d4906093
ML		 624 intel_clock_t clock;
625 int max_n;
626 bool found;
6ba770dc
AJ		 627 /* approximately equals target * 0.00585 */
628 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 629 found = false;
630
631 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 632 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 633 clock.p2 = limit->p2.p2_fast;
634 else
635 clock.p2 = limit->p2.p2_slow;
636 } else {
637 if (target < limit->p2.dot_limit)
638 clock.p2 = limit->p2.p2_slow;
639 else
640 clock.p2 = limit->p2.p2_fast;
641 }
642
643 memset(best_clock, 0, sizeof(*best_clock));
644 max_n = limit->n.max;
f77f13e2 645 /* based on hardware requirement, prefer smaller n to precision */
d4906093 646 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 647 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 648 for (clock.m1 = limit->m1.max;
649 clock.m1 >= limit->m1.min; clock.m1--) {
650 for (clock.m2 = limit->m2.max;
651 clock.m2 >= limit->m2.min; clock.m2--) {
652 for (clock.p1 = limit->p1.max;
653 clock.p1 >= limit->p1.min; clock.p1--) {
654 int this_err;
655
ac58c3f0 656 i9xx_clock(refclk, &clock);
1b894b59
CW		 657 if (!intel_PLL_is_valid(dev, limit,
658 &clock))
d4906093 659 continue;
1b894b59
CW		 660
661 this_err = abs(clock.dot - target);
d4906093
ML		 662 if (this_err < err_most) {
663 *best_clock = clock;
664 err_most = this_err;
665 max_n = clock.n;
666 found = true;
667 }
668 }
669 }
670 }
671 }
2c07245f
ZW		 672 return found;
673}
674
a0c4da24 675static bool
ee9300bb
DV		 676vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
677 int target, int refclk, intel_clock_t *match_clock,
678 intel_clock_t *best_clock)
a0c4da24 679{
6b4bf1c4
VS		 680 intel_clock_t clock;
681 u32 minupdate = 19200;
69e4f900 682 unsigned int bestppm = 1000000;
a0c4da24 683
6b4bf1c4
VS		 684 target *= 5; /* fast clock */
685
686 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 687
688 /* based on hardware requirement, prefer smaller n to precision */
6b4bf1c4
VS		 689 for (clock.n = limit->n.min; clock.n <= ((refclk) / minupdate); clock.n++) {
690 for (clock.p1 = limit->p1.max; clock.p1 > limit->p1.min; clock.p1--) {
c1a9ae43
VS		 691 for (clock.p2 = limit->p2.p2_fast; clock.p2 > 0;
692 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 693 clock.p = clock.p1 * clock.p2;
a0c4da24 694 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 695 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
69e4f900
VS		 696 unsigned int ppm, diff;
697
6b4bf1c4
VS		 698 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
699 refclk * clock.m1);
700
701 vlv_clock(refclk, &clock);
43b0ac53 702
6b4bf1c4
VS		 703 if (clock.vco < limit->vco.min ||
704 clock.vco >= limit->vco.max)
43b0ac53
VS		 705 continue;
706
6b4bf1c4
VS		 707 diff = abs(clock.dot - target);
708 ppm = div_u64(1000000ULL * diff, target);
709
710 if (ppm < 100 && clock.p > best_clock->p) {
43b0ac53 711 bestppm = 0;
6b4bf1c4 712 *best_clock = clock;
43b0ac53 713 }
6b4bf1c4 714
c686122c 715 if (bestppm >= 10 && ppm < bestppm - 10) {
69e4f900 716 bestppm = ppm;
6b4bf1c4 717 *best_clock = clock;
a0c4da24
JB		 718 }
719 }
720 }
721 }
722 }
a0c4da24
JB		 723
724 return true;
725}
a4fc5ed6 726
20ddf665
VS		 727bool intel_crtc_active(struct drm_crtc *crtc)
728{
729 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
730
731 /* Be paranoid as we can arrive here with only partial
732 * state retrieved from the hardware during setup.
733 *
241bfc38 734 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 735 * as Haswell has gained clock readout/fastboot support.
736 *
737 * We can ditch the crtc->fb check as soon as we can
738 * properly reconstruct framebuffers.
739 */
740 return intel_crtc->active && crtc->fb &&
241bfc38 741 intel_crtc->config.adjusted_mode.crtc_clock;
20ddf665
VS		 742}
743
a5c961d1
PZ		 744enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
745 enum pipe pipe)
746{
747 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
748 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
749
3b117c8f 750 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 751}
752
a928d536
PZ		 753static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
754{
755 struct drm_i915_private *dev_priv = dev->dev_private;
756 u32 frame, frame_reg = PIPEFRAME(pipe);
757
758 frame = I915_READ(frame_reg);
759
760 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
761 DRM_DEBUG_KMS("vblank wait timed out\n");
762}
763
9d0498a2
JB		 764/**
765 * intel_wait_for_vblank - wait for vblank on a given pipe
766 * @dev: drm device
767 * @pipe: pipe to wait for
768 *
769 * Wait for vblank to occur on a given pipe. Needed for various bits of
770 * mode setting code.
771 */
772void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 773{
9d0498a2 774 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 775 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 776
a928d536
PZ		 777 if (INTEL_INFO(dev)->gen >= 5) {
778 ironlake_wait_for_vblank(dev, pipe);
779 return;
780 }
781
300387c0
CW		 782 /* Clear existing vblank status. Note this will clear any other
783 * sticky status fields as well.
784 *
785 * This races with i915_driver_irq_handler() with the result
786 * that either function could miss a vblank event. Here it is not
787 * fatal, as we will either wait upon the next vblank interrupt or
788 * timeout. Generally speaking intel_wait_for_vblank() is only
789 * called during modeset at which time the GPU should be idle and
790 * should *not* be performing page flips and thus not waiting on
791 * vblanks...
792 * Currently, the result of us stealing a vblank from the irq
793 * handler is that a single frame will be skipped during swapbuffers.
794 */
795 I915_WRITE(pipestat_reg,
796 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
797
9d0498a2 798 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 799 if (wait_for(I915_READ(pipestat_reg) &
800 PIPE_VBLANK_INTERRUPT_STATUS,
801 50))
9d0498a2
JB		 802 DRM_DEBUG_KMS("vblank wait timed out\n");
803}
804
ab7ad7f6
KP		 805/*
806 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 807 * @dev: drm device
808 * @pipe: pipe to wait for
809 *
810 * After disabling a pipe, we can't wait for vblank in the usual way,
811 * spinning on the vblank interrupt status bit, since we won't actually
812 * see an interrupt when the pipe is disabled.
813 *
ab7ad7f6
KP		 814 * On Gen4 and above:
815 * wait for the pipe register state bit to turn off
816 *
817 * Otherwise:
818 * wait for the display line value to settle (it usually
819 * ends up stopping at the start of the next frame).
58e10eb9 820 *
9d0498a2 821 */
58e10eb9 822void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 823{
824 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 825 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
826 pipe);
ab7ad7f6
KP		 827
828 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 829 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 830
831 /* Wait for the Pipe State to go off */
58e10eb9
CW		 832 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
833 100))
284637d9 834 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 835 } else {
837ba00f 836 u32 last_line, line_mask;
58e10eb9 837 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 838 unsigned long timeout = jiffies + msecs_to_jiffies(100);
839
837ba00f
PZ		 840 if (IS_GEN2(dev))
841 line_mask = DSL_LINEMASK_GEN2;
842 else
843 line_mask = DSL_LINEMASK_GEN3;
844
ab7ad7f6
KP		 845 /* Wait for the display line to settle */
846 do {
837ba00f 847 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 848 mdelay(5);
837ba00f 849 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 850 time_after(timeout, jiffies));
851 if (time_after(jiffies, timeout))
284637d9 852 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 853 }
79e53945
JB		 854}
855
b0ea7d37
DL		 856/*
857 * ibx_digital_port_connected - is the specified port connected?
858 * @dev_priv: i915 private structure
859 * @port: the port to test
860 *
861 * Returns true if @port is connected, false otherwise.
862 */
863bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
864 struct intel_digital_port *port)
865{
866 u32 bit;
867
c36346e3
DL		 868 if (HAS_PCH_IBX(dev_priv->dev)) {
869 switch(port->port) {
870 case PORT_B:
871 bit = SDE_PORTB_HOTPLUG;
872 break;
873 case PORT_C:
874 bit = SDE_PORTC_HOTPLUG;
875 break;
876 case PORT_D:
877 bit = SDE_PORTD_HOTPLUG;
878 break;
879 default:
880 return true;
881 }
882 } else {
883 switch(port->port) {
884 case PORT_B:
885 bit = SDE_PORTB_HOTPLUG_CPT;
886 break;
887 case PORT_C:
888 bit = SDE_PORTC_HOTPLUG_CPT;
889 break;
890 case PORT_D:
891 bit = SDE_PORTD_HOTPLUG_CPT;
892 break;
893 default:
894 return true;
895 }
b0ea7d37
DL		 896 }
897
898 return I915_READ(SDEISR) & bit;
899}
900
b24e7179
JB		 901static const char *state_string(bool enabled)
902{
903 return enabled ? "on" : "off";
904}
905
906/* Only for pre-ILK configs */
55607e8a
DV		 907void assert_pll(struct drm_i915_private *dev_priv,
908 enum pipe pipe, bool state)
b24e7179
JB		 909{
910 int reg;
911 u32 val;
912 bool cur_state;
913
914 reg = DPLL(pipe);
915 val = I915_READ(reg);
916 cur_state = !!(val & DPLL_VCO_ENABLE);
917 WARN(cur_state != state,
918 "PLL state assertion failure (expected %s, current %s)\n",
919 state_string(state), state_string(cur_state));
920}
b24e7179 921
23538ef1
JN		 922/* XXX: the dsi pll is shared between MIPI DSI ports */
923static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
924{
925 u32 val;
926 bool cur_state;
927
928 mutex_lock(&dev_priv->dpio_lock);
929 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
930 mutex_unlock(&dev_priv->dpio_lock);
931
932 cur_state = val & DSI_PLL_VCO_EN;
933 WARN(cur_state != state,
934 "DSI PLL state assertion failure (expected %s, current %s)\n",
935 state_string(state), state_string(cur_state));
936}
937#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
938#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
939
55607e8a 940struct intel_shared_dpll *
e2b78267
DV		 941intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
942{
943 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
944
a43f6e0f 945 if (crtc->config.shared_dpll < 0)
e2b78267
DV		 946 return NULL;
947
a43f6e0f 948 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
e2b78267
DV		 949}
950
040484af 951/* For ILK+ */
55607e8a
DV		 952void assert_shared_dpll(struct drm_i915_private *dev_priv,
953 struct intel_shared_dpll *pll,
954 bool state)
040484af 955{
040484af 956 bool cur_state;
5358901f 957 struct intel_dpll_hw_state hw_state;
040484af 958
9d82aa17
ED		 959 if (HAS_PCH_LPT(dev_priv->dev)) {
960 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
961 return;
962 }
963
92b27b08 964 if (WARN (!pll,
46edb027 965 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 966 return;
ee7b9f93 967
5358901f 968 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
92b27b08 969 WARN(cur_state != state,
5358901f
DV		 970 "%s assertion failure (expected %s, current %s)\n",
971 pll->name, state_string(state), state_string(cur_state));
040484af 972}
040484af
JB		 973
974static void assert_fdi_tx(struct drm_i915_private *dev_priv,
975 enum pipe pipe, bool state)
976{
977 int reg;
978 u32 val;
979 bool cur_state;
ad80a810
PZ		 980 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
981 pipe);
040484af 982
affa9354
PZ		 983 if (HAS_DDI(dev_priv->dev)) {
984 /* DDI does not have a specific FDI_TX register */
ad80a810 985 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 986 val = I915_READ(reg);
ad80a810 987 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 988 } else {
989 reg = FDI_TX_CTL(pipe);
990 val = I915_READ(reg);
991 cur_state = !!(val & FDI_TX_ENABLE);
992 }
040484af
JB		 993 WARN(cur_state != state,
994 "FDI TX state assertion failure (expected %s, current %s)\n",
995 state_string(state), state_string(cur_state));
996}
997#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
998#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
999
1000static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1001 enum pipe pipe, bool state)
1002{
1003 int reg;
1004 u32 val;
1005 bool cur_state;
1006
d63fa0dc
PZ		 1007 reg = FDI_RX_CTL(pipe);
1008 val = I915_READ(reg);
1009 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1010 WARN(cur_state != state,
1011 "FDI RX state assertion failure (expected %s, current %s)\n",
1012 state_string(state), state_string(cur_state));
1013}
1014#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1015#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1016
1017static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1018 enum pipe pipe)
1019{
1020 int reg;
1021 u32 val;
1022
1023 /* ILK FDI PLL is always enabled */
1024 if (dev_priv->info->gen == 5)
1025 return;
1026
bf507ef7 1027 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1028 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1029 return;
1030
040484af
JB		 1031 reg = FDI_TX_CTL(pipe);
1032 val = I915_READ(reg);
1033 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1034}
1035
55607e8a
DV		 1036void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1037 enum pipe pipe, bool state)
040484af
JB		 1038{
1039 int reg;
1040 u32 val;
55607e8a 1041 bool cur_state;
040484af
JB		 1042
1043 reg = FDI_RX_CTL(pipe);
1044 val = I915_READ(reg);
55607e8a
DV		 1045 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1046 WARN(cur_state != state,
1047 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1048 state_string(state), state_string(cur_state));
040484af
JB		 1049}
1050
ea0760cf
JB		 1051static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1052 enum pipe pipe)
1053{
1054 int pp_reg, lvds_reg;
1055 u32 val;
1056 enum pipe panel_pipe = PIPE_A;
0de3b485 1057 bool locked = true;
ea0760cf
JB		 1058
1059 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1060 pp_reg = PCH_PP_CONTROL;
1061 lvds_reg = PCH_LVDS;
1062 } else {
1063 pp_reg = PP_CONTROL;
1064 lvds_reg = LVDS;
1065 }
1066
1067 val = I915_READ(pp_reg);
1068 if (!(val & PANEL_POWER_ON) ||
1069 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1070 locked = false;
1071
1072 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1073 panel_pipe = PIPE_B;
1074
1075 WARN(panel_pipe == pipe && locked,
1076 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1077 pipe_name(pipe));
ea0760cf
JB		 1078}
1079
93ce0ba6
JN		 1080static void assert_cursor(struct drm_i915_private *dev_priv,
1081 enum pipe pipe, bool state)
1082{
1083 struct drm_device *dev = dev_priv->dev;
1084 bool cur_state;
1085
1086 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1087 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1088 else if (IS_845G(dev) || IS_I865G(dev))
1089 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1090 else
1091 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1092
1093 WARN(cur_state != state,
1094 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1095 pipe_name(pipe), state_string(state), state_string(cur_state));
1096}
1097#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1098#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1099
b840d907
JB		 1100void assert_pipe(struct drm_i915_private *dev_priv,
1101 enum pipe pipe, bool state)
b24e7179
JB		 1102{
1103 int reg;
1104 u32 val;
63d7bbe9 1105 bool cur_state;
702e7a56
PZ		 1106 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1107 pipe);
b24e7179 1108
8e636784
DV		 1109 /* if we need the pipe A quirk it must be always on */
1110 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1111 state = true;
1112
b97186f0
PZ		 1113 if (!intel_display_power_enabled(dev_priv->dev,
1114 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1115 cur_state = false;
1116 } else {
1117 reg = PIPECONF(cpu_transcoder);
1118 val = I915_READ(reg);
1119 cur_state = !!(val & PIPECONF_ENABLE);
1120 }
1121
63d7bbe9
JB		 1122 WARN(cur_state != state,
1123 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1124 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1125}
1126
931872fc
CW		 1127static void assert_plane(struct drm_i915_private *dev_priv,
1128 enum plane plane, bool state)
b24e7179
JB		 1129{
1130 int reg;
1131 u32 val;
931872fc 1132 bool cur_state;
b24e7179
JB		 1133
1134 reg = DSPCNTR(plane);
1135 val = I915_READ(reg);
931872fc
CW		 1136 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1137 WARN(cur_state != state,
1138 "plane %c assertion failure (expected %s, current %s)\n",
1139 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1140}
1141
931872fc
CW		 1142#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1143#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1144
b24e7179
JB		 1145static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1146 enum pipe pipe)
1147{
653e1026 1148 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1149 int reg, i;
1150 u32 val;
1151 int cur_pipe;
1152
653e1026
VS		 1153 /* Primary planes are fixed to pipes on gen4+ */
1154 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1155 reg = DSPCNTR(pipe);
1156 val = I915_READ(reg);
1157 WARN((val & DISPLAY_PLANE_ENABLE),
1158 "plane %c assertion failure, should be disabled but not\n",
1159 plane_name(pipe));
19ec1358 1160 return;
28c05794 1161 }
19ec1358 1162
b24e7179 1163 /* Need to check both planes against the pipe */
08e2a7de 1164 for_each_pipe(i) {
b24e7179
JB		 1165 reg = DSPCNTR(i);
1166 val = I915_READ(reg);
1167 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1168 DISPPLANE_SEL_PIPE_SHIFT;
1169 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1170 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1171 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1172 }
1173}
1174
19332d7a
JB		 1175static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1176 enum pipe pipe)
1177{
20674eef 1178 struct drm_device *dev = dev_priv->dev;
19332d7a
JB		 1179 int reg, i;
1180 u32 val;
1181
20674eef
VS		 1182 if (IS_VALLEYVIEW(dev)) {
1183 for (i = 0; i < dev_priv->num_plane; i++) {
1184 reg = SPCNTR(pipe, i);
1185 val = I915_READ(reg);
1186 WARN((val & SP_ENABLE),
1187 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1188 sprite_name(pipe, i), pipe_name(pipe));
1189 }
1190 } else if (INTEL_INFO(dev)->gen >= 7) {
1191 reg = SPRCTL(pipe);
19332d7a 1192 val = I915_READ(reg);
20674eef 1193 WARN((val & SPRITE_ENABLE),
06da8da2 1194 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1195 plane_name(pipe), pipe_name(pipe));
1196 } else if (INTEL_INFO(dev)->gen >= 5) {
1197 reg = DVSCNTR(pipe);
19332d7a 1198 val = I915_READ(reg);
20674eef 1199 WARN((val & DVS_ENABLE),
06da8da2 1200 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1201 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1202 }
1203}
1204
92f2584a
JB		 1205static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1206{
1207 u32 val;
1208 bool enabled;
1209
9d82aa17
ED		 1210 if (HAS_PCH_LPT(dev_priv->dev)) {
1211 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1212 return;
1213 }
1214
92f2584a
JB		 1215 val = I915_READ(PCH_DREF_CONTROL);
1216 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1217 DREF_SUPERSPREAD_SOURCE_MASK));
1218 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1219}
1220
ab9412ba
DV		 1221static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1222 enum pipe pipe)
92f2584a
JB		 1223{
1224 int reg;
1225 u32 val;
1226 bool enabled;
1227
ab9412ba 1228 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1229 val = I915_READ(reg);
1230 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1231 WARN(enabled,
1232 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1233 pipe_name(pipe));
92f2584a
JB		 1234}
1235
4e634389
KP		 1236static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1237 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1238{
1239 if ((val & DP_PORT_EN) == 0)
1240 return false;
1241
1242 if (HAS_PCH_CPT(dev_priv->dev)) {
1243 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1244 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1245 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1246 return false;
1247 } else {
1248 if ((val & DP_PIPE_MASK) != (pipe << 30))
1249 return false;
1250 }
1251 return true;
1252}
1253
1519b995
KP		 1254static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1255 enum pipe pipe, u32 val)
1256{
dc0fa718 1257 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1258 return false;
1259
1260 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1261 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1262 return false;
1263 } else {
dc0fa718 1264 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1265 return false;
1266 }
1267 return true;
1268}
1269
1270static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1271 enum pipe pipe, u32 val)
1272{
1273 if ((val & LVDS_PORT_EN) == 0)
1274 return false;
1275
1276 if (HAS_PCH_CPT(dev_priv->dev)) {
1277 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1278 return false;
1279 } else {
1280 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1281 return false;
1282 }
1283 return true;
1284}
1285
1286static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1287 enum pipe pipe, u32 val)
1288{
1289 if ((val & ADPA_DAC_ENABLE) == 0)
1290 return false;
1291 if (HAS_PCH_CPT(dev_priv->dev)) {
1292 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1293 return false;
1294 } else {
1295 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1296 return false;
1297 }
1298 return true;
1299}
1300
291906f1 1301static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1302 enum pipe pipe, int reg, u32 port_sel)
291906f1 1303{
47a05eca 1304 u32 val = I915_READ(reg);
4e634389 1305 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1306 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1307 reg, pipe_name(pipe));
de9a35ab 1308
75c5da27
DV		 1309 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1310 && (val & DP_PIPEB_SELECT),
de9a35ab 1311 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1312}
1313
1314static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1315 enum pipe pipe, int reg)
1316{
47a05eca 1317 u32 val = I915_READ(reg);
b70ad586 1318 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1319 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1320 reg, pipe_name(pipe));
de9a35ab 1321
dc0fa718 1322 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1323 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1324 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1325}
1326
1327static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1328 enum pipe pipe)
1329{
1330 int reg;
1331 u32 val;
291906f1 1332
f0575e92
KP		 1333 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1334 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1335 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1336
1337 reg = PCH_ADPA;
1338 val = I915_READ(reg);
b70ad586 1339 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1340 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1341 pipe_name(pipe));
291906f1
JB		 1342
1343 reg = PCH_LVDS;
1344 val = I915_READ(reg);
b70ad586 1345 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1346 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1347 pipe_name(pipe));
291906f1 1348
e2debe91
PZ		 1349 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1350 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1351 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1352}
1353
40e9cf64
JB		 1354static void intel_init_dpio(struct drm_device *dev)
1355{
1356 struct drm_i915_private *dev_priv = dev->dev_private;
1357
1358 if (!IS_VALLEYVIEW(dev))
1359 return;
1360
1361 /*
1362 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1363 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
1364 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
1365 * b. The other bits such as sfr settings / modesel may all be set
1366 * to 0.
1367 *
1368 * This should only be done on init and resume from S3 with both
1369 * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1370 */
1371 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1372}
1373
426115cf 1374static void vlv_enable_pll(struct intel_crtc *crtc)
87442f73 1375{
426115cf
DV		 1376 struct drm_device *dev = crtc->base.dev;
1377 struct drm_i915_private *dev_priv = dev->dev_private;
1378 int reg = DPLL(crtc->pipe);
1379 u32 dpll = crtc->config.dpll_hw_state.dpll;
87442f73 1380
426115cf 1381 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1382
1383 /* No really, not for ILK+ */
1384 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1385
1386 /* PLL is protected by panel, make sure we can write it */
1387 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
426115cf 1388 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1389
426115cf
DV		 1390 I915_WRITE(reg, dpll);
1391 POSTING_READ(reg);
1392 udelay(150);
1393
1394 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1395 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1396
1397 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1398 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1399
1400 /* We do this three times for luck */
426115cf 1401 I915_WRITE(reg, dpll);
87442f73
DV		 1402 POSTING_READ(reg);
1403 udelay(150); /* wait for warmup */
426115cf 1404 I915_WRITE(reg, dpll);
87442f73
DV		 1405 POSTING_READ(reg);
1406 udelay(150); /* wait for warmup */
426115cf 1407 I915_WRITE(reg, dpll);
87442f73
DV		 1408 POSTING_READ(reg);
1409 udelay(150); /* wait for warmup */
1410}
1411
66e3d5c0 1412static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1413{
66e3d5c0
DV		 1414 struct drm_device *dev = crtc->base.dev;
1415 struct drm_i915_private *dev_priv = dev->dev_private;
1416 int reg = DPLL(crtc->pipe);
1417 u32 dpll = crtc->config.dpll_hw_state.dpll;
63d7bbe9 1418
66e3d5c0 1419 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1420
63d7bbe9 1421 /* No really, not for ILK+ */
87442f73 1422 BUG_ON(dev_priv->info->gen >= 5);
63d7bbe9
JB		 1423
1424 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1425 if (IS_MOBILE(dev) && !IS_I830(dev))
1426 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1427
66e3d5c0
DV		 1428 I915_WRITE(reg, dpll);
1429
1430 /* Wait for the clocks to stabilize. */
1431 POSTING_READ(reg);
1432 udelay(150);
1433
1434 if (INTEL_INFO(dev)->gen >= 4) {
1435 I915_WRITE(DPLL_MD(crtc->pipe),
1436 crtc->config.dpll_hw_state.dpll_md);
1437 } else {
1438 /* The pixel multiplier can only be updated once the
1439 * DPLL is enabled and the clocks are stable.
1440 *
1441 * So write it again.
1442 */
1443 I915_WRITE(reg, dpll);
1444 }
63d7bbe9
JB		 1445
1446 /* We do this three times for luck */
66e3d5c0 1447 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1448 POSTING_READ(reg);
1449 udelay(150); /* wait for warmup */
66e3d5c0 1450 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1451 POSTING_READ(reg);
1452 udelay(150); /* wait for warmup */
66e3d5c0 1453 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1454 POSTING_READ(reg);
1455 udelay(150); /* wait for warmup */
1456}
1457
1458/**
50b44a44 1459 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1460 * @dev_priv: i915 private structure
1461 * @pipe: pipe PLL to disable
1462 *
1463 * Disable the PLL for @pipe, making sure the pipe is off first.
1464 *
1465 * Note! This is for pre-ILK only.
1466 */
50b44a44 1467static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9 1468{
63d7bbe9
JB		 1469 /* Don't disable pipe A or pipe A PLLs if needed */
1470 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1471 return;
1472
1473 /* Make sure the pipe isn't still relying on us */
1474 assert_pipe_disabled(dev_priv, pipe);
1475
50b44a44
DV		 1476 I915_WRITE(DPLL(pipe), 0);
1477 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1478}
1479
f6071166
JB		 1480static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1481{
1482 u32 val = 0;
1483
1484 /* Make sure the pipe isn't still relying on us */
1485 assert_pipe_disabled(dev_priv, pipe);
1486
1487 /* Leave integrated clock source enabled */
1488 if (pipe == PIPE_B)
1489 val = DPLL_INTEGRATED_CRI_CLK_VLV;
1490 I915_WRITE(DPLL(pipe), val);
1491 POSTING_READ(DPLL(pipe));
1492}
1493
89b667f8
JB		 1494void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1495{
1496 u32 port_mask;
1497
1498 if (!port)
1499 port_mask = DPLL_PORTB_READY_MASK;
1500 else
1501 port_mask = DPLL_PORTC_READY_MASK;
1502
1503 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1504 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1505 'B' + port, I915_READ(DPLL(0)));
1506}
1507
92f2584a 1508/**
e72f9fbf 1509 * ironlake_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1510 * @dev_priv: i915 private structure
1511 * @pipe: pipe PLL to enable
1512 *
1513 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1514 * drives the transcoder clock.
1515 */
e2b78267 1516static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1517{
e2b78267
DV		 1518 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1519 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1520
48da64a8 1521 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1522 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1523 if (WARN_ON(pll == NULL))
48da64a8
CW		 1524 return;
1525
1526 if (WARN_ON(pll->refcount == 0))
1527 return;
ee7b9f93 1528
46edb027
DV		 1529 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1530 pll->name, pll->active, pll->on,
e2b78267 1531 crtc->base.base.id);
92f2584a 1532
cdbd2316
DV		 1533 if (pll->active++) {
1534 WARN_ON(!pll->on);
e9d6944e 1535 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1536 return;
1537 }
f4a091c7 1538 WARN_ON(pll->on);
ee7b9f93 1539
46edb027 1540 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1541 pll->enable(dev_priv, pll);
ee7b9f93 1542 pll->on = true;
92f2584a
JB		 1543}
1544
e2b78267 1545static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1546{
e2b78267
DV		 1547 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1548 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1549
92f2584a
JB		 1550 /* PCH only available on ILK+ */
1551 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1552 if (WARN_ON(pll == NULL))
ee7b9f93 1553 return;
92f2584a 1554
48da64a8
CW		 1555 if (WARN_ON(pll->refcount == 0))
1556 return;
7a419866 1557
46edb027
DV		 1558 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1559 pll->name, pll->active, pll->on,
e2b78267 1560 crtc->base.base.id);
7a419866 1561
48da64a8 1562 if (WARN_ON(pll->active == 0)) {
e9d6944e 1563 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1564 return;
1565 }
1566
e9d6944e 1567 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1568 WARN_ON(!pll->on);
cdbd2316 1569 if (--pll->active)
7a419866 1570 return;
ee7b9f93 1571
46edb027 1572 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1573 pll->disable(dev_priv, pll);
ee7b9f93 1574 pll->on = false;
92f2584a
JB		 1575}
1576
b8a4f404
PZ		 1577static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1578 enum pipe pipe)
040484af 1579{
23670b32 1580 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1581 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1582 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1583 uint32_t reg, val, pipeconf_val;
040484af
JB		 1584
1585 /* PCH only available on ILK+ */
1586 BUG_ON(dev_priv->info->gen < 5);
1587
1588 /* Make sure PCH DPLL is enabled */
e72f9fbf 1589 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1590 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1591
1592 /* FDI must be feeding us bits for PCH ports */
1593 assert_fdi_tx_enabled(dev_priv, pipe);
1594 assert_fdi_rx_enabled(dev_priv, pipe);
1595
23670b32
DV		 1596 if (HAS_PCH_CPT(dev)) {
1597 /* Workaround: Set the timing override bit before enabling the
1598 * pch transcoder. */
1599 reg = TRANS_CHICKEN2(pipe);
1600 val = I915_READ(reg);
1601 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1602 I915_WRITE(reg, val);
59c859d6 1603 }
23670b32 1604
ab9412ba 1605 reg = PCH_TRANSCONF(pipe);
040484af 1606 val = I915_READ(reg);
5f7f726d 1607 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1608
1609 if (HAS_PCH_IBX(dev_priv->dev)) {
1610 /*
1611 * make the BPC in transcoder be consistent with
1612 * that in pipeconf reg.
1613 */
dfd07d72
DV		 1614 val &= ~PIPECONF_BPC_MASK;
1615 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1616 }
5f7f726d
PZ		 1617
1618 val &= ~TRANS_INTERLACE_MASK;
1619 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1620 if (HAS_PCH_IBX(dev_priv->dev) &&
1621 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1622 val |= TRANS_LEGACY_INTERLACED_ILK;
1623 else
1624 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1625 else
1626 val |= TRANS_PROGRESSIVE;
1627
040484af
JB		 1628 I915_WRITE(reg, val | TRANS_ENABLE);
1629 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1630 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1631}
1632
8fb033d7 1633static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1634 enum transcoder cpu_transcoder)
040484af 1635{
8fb033d7 1636 u32 val, pipeconf_val;
8fb033d7
PZ		 1637
1638 /* PCH only available on ILK+ */
1639 BUG_ON(dev_priv->info->gen < 5);
1640
8fb033d7 1641 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1642 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1643 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1644
223a6fdf
PZ		 1645 /* Workaround: set timing override bit. */
1646 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1647 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1648 I915_WRITE(_TRANSA_CHICKEN2, val);
1649
25f3ef11 1650 val = TRANS_ENABLE;
937bb610 1651 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1652
9a76b1c6
PZ		 1653 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1654 PIPECONF_INTERLACED_ILK)
a35f2679 1655 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1656 else
1657 val |= TRANS_PROGRESSIVE;
1658
ab9412ba
DV		 1659 I915_WRITE(LPT_TRANSCONF, val);
1660 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1661 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1662}
1663
b8a4f404
PZ		 1664static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1665 enum pipe pipe)
040484af 1666{
23670b32
DV		 1667 struct drm_device *dev = dev_priv->dev;
1668 uint32_t reg, val;
040484af
JB		 1669
1670 /* FDI relies on the transcoder */
1671 assert_fdi_tx_disabled(dev_priv, pipe);
1672 assert_fdi_rx_disabled(dev_priv, pipe);
1673
291906f1
JB		 1674 /* Ports must be off as well */
1675 assert_pch_ports_disabled(dev_priv, pipe);
1676
ab9412ba 1677 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1678 val = I915_READ(reg);
1679 val &= ~TRANS_ENABLE;
1680 I915_WRITE(reg, val);
1681 /* wait for PCH transcoder off, transcoder state */
1682 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1683 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1684
1685 if (!HAS_PCH_IBX(dev)) {
1686 /* Workaround: Clear the timing override chicken bit again. */
1687 reg = TRANS_CHICKEN2(pipe);
1688 val = I915_READ(reg);
1689 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1690 I915_WRITE(reg, val);
1691 }
040484af
JB		 1692}
1693
ab4d966c 1694static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1695{
8fb033d7
PZ		 1696 u32 val;
1697
ab9412ba 1698 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1699 val &= ~TRANS_ENABLE;
ab9412ba 1700 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1701 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1702 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1703 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1704
1705 /* Workaround: clear timing override bit. */
1706 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1707 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1708 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1709}
1710
b24e7179 1711/**
309cfea8 1712 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1713 * @dev_priv: i915 private structure
1714 * @pipe: pipe to enable
040484af 1715 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1716 *
1717 * Enable @pipe, making sure that various hardware specific requirements
1718 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1719 *
1720 * @pipe should be %PIPE_A or %PIPE_B.
1721 *
1722 * Will wait until the pipe is actually running (i.e. first vblank) before
1723 * returning.
1724 */
040484af 1725static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
23538ef1 1726 bool pch_port, bool dsi)
b24e7179 1727{
702e7a56
PZ		 1728 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1729 pipe);
1a240d4d 1730 enum pipe pch_transcoder;
b24e7179
JB		 1731 int reg;
1732 u32 val;
1733
58c6eaa2 1734 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 1735 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 1736 assert_sprites_disabled(dev_priv, pipe);
1737
681e5811 1738 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1739 pch_transcoder = TRANSCODER_A;
1740 else
1741 pch_transcoder = pipe;
1742
b24e7179
JB		 1743 /*
1744 * A pipe without a PLL won't actually be able to drive bits from
1745 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1746 * need the check.
1747 */
1748 if (!HAS_PCH_SPLIT(dev_priv->dev))
23538ef1
JN		 1749 if (dsi)
1750 assert_dsi_pll_enabled(dev_priv);
1751 else
1752 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1753 else {
1754 if (pch_port) {
1755 /* if driving the PCH, we need FDI enabled */
cc391bbb 1756 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1757 assert_fdi_tx_pll_enabled(dev_priv,
1758 (enum pipe) cpu_transcoder);
040484af
JB		 1759 }
1760 /* FIXME: assert CPU port conditions for SNB+ */
1761 }
b24e7179 1762
702e7a56 1763 reg = PIPECONF(cpu_transcoder);
b24e7179 1764 val = I915_READ(reg);
00d70b15
CW		 1765 if (val & PIPECONF_ENABLE)
1766 return;
1767
1768 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1769 intel_wait_for_vblank(dev_priv->dev, pipe);
1770}
1771
1772/**
309cfea8 1773 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1774 * @dev_priv: i915 private structure
1775 * @pipe: pipe to disable
1776 *
1777 * Disable @pipe, making sure that various hardware specific requirements
1778 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1779 *
1780 * @pipe should be %PIPE_A or %PIPE_B.
1781 *
1782 * Will wait until the pipe has shut down before returning.
1783 */
1784static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1785 enum pipe pipe)
1786{
702e7a56
PZ		 1787 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1788 pipe);
b24e7179
JB		 1789 int reg;
1790 u32 val;
1791
1792 /*
1793 * Make sure planes won't keep trying to pump pixels to us,
1794 * or we might hang the display.
1795 */
1796 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 1797 assert_cursor_disabled(dev_priv, pipe);
19332d7a 1798 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1799
1800 /* Don't disable pipe A or pipe A PLLs if needed */
1801 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1802 return;
1803
702e7a56 1804 reg = PIPECONF(cpu_transcoder);
b24e7179 1805 val = I915_READ(reg);
00d70b15
CW		 1806 if ((val & PIPECONF_ENABLE) == 0)
1807 return;
1808
1809 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1810 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1811}
1812
d74362c9
KP		 1813/*
1814 * Plane regs are double buffered, going from enabled->disabled needs a
1815 * trigger in order to latch. The display address reg provides this.
1816 */
6f1d69b0 1817void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1818 enum plane plane)
1819{
14f86147
DL		 1820 if (dev_priv->info->gen >= 4)
1821 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1822 else
1823 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1824}
1825
b24e7179
JB		 1826/**
1827 * intel_enable_plane - enable a display plane on a given pipe
1828 * @dev_priv: i915 private structure
1829 * @plane: plane to enable
1830 * @pipe: pipe being fed
1831 *
1832 * Enable @plane on @pipe, making sure that @pipe is running first.
1833 */
1834static void intel_enable_plane(struct drm_i915_private *dev_priv,
1835 enum plane plane, enum pipe pipe)
1836{
1837 int reg;
1838 u32 val;
1839
1840 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1841 assert_pipe_enabled(dev_priv, pipe);
1842
1843 reg = DSPCNTR(plane);
1844 val = I915_READ(reg);
00d70b15
CW		 1845 if (val & DISPLAY_PLANE_ENABLE)
1846 return;
1847
1848 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1849 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1850 intel_wait_for_vblank(dev_priv->dev, pipe);
1851}
1852
b24e7179
JB		 1853/**
1854 * intel_disable_plane - disable a display plane
1855 * @dev_priv: i915 private structure
1856 * @plane: plane to disable
1857 * @pipe: pipe consuming the data
1858 *
1859 * Disable @plane; should be an independent operation.
1860 */
1861static void intel_disable_plane(struct drm_i915_private *dev_priv,
1862 enum plane plane, enum pipe pipe)
1863{
1864 int reg;
1865 u32 val;
1866
1867 reg = DSPCNTR(plane);
1868 val = I915_READ(reg);
00d70b15
CW		 1869 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1870 return;
1871
1872 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1873 intel_flush_display_plane(dev_priv, plane);
1874 intel_wait_for_vblank(dev_priv->dev, pipe);
1875}
1876
693db184
CW		 1877static bool need_vtd_wa(struct drm_device *dev)
1878{
1879#ifdef CONFIG_INTEL_IOMMU
1880 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1881 return true;
1882#endif
1883 return false;
1884}
1885
127bd2ac 1886int
48b956c5 1887intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1888 struct drm_i915_gem_object *obj,
919926ae 1889 struct intel_ring_buffer *pipelined)
6b95a207 1890{
ce453d81 1891 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1892 u32 alignment;
1893 int ret;
1894
05394f39 1895 switch (obj->tiling_mode) {
6b95a207 1896 case I915_TILING_NONE:
534843da
CW		 1897 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1898 alignment = 128 * 1024;
a6c45cf0 1899 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1900 alignment = 4 * 1024;
1901 else
1902 alignment = 64 * 1024;
6b95a207
KH		 1903 break;
1904 case I915_TILING_X:
1905 /* pin() will align the object as required by fence */
1906 alignment = 0;
1907 break;
1908 case I915_TILING_Y:
8bb6e959
DV		 1909 /* Despite that we check this in framebuffer_init userspace can
1910 * screw us over and change the tiling after the fact. Only
1911 * pinned buffers can't change their tiling. */
1912 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1913 return -EINVAL;
1914 default:
1915 BUG();
1916 }
1917
693db184
CW		 1918 /* Note that the w/a also requires 64 PTE of padding following the
1919 * bo. We currently fill all unused PTE with the shadow page and so
1920 * we should always have valid PTE following the scanout preventing
1921 * the VT-d warning.
1922 */
1923 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1924 alignment = 256 * 1024;
1925
ce453d81 1926 dev_priv->mm.interruptible = false;
2da3b9b9 1927 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1928 if (ret)
ce453d81 1929 goto err_interruptible;
6b95a207
KH		 1930
1931 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1932 * fence, whereas 965+ only requires a fence if using
1933 * framebuffer compression. For simplicity, we always install
1934 * a fence as the cost is not that onerous.
1935 */
06d98131 1936 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1937 if (ret)
1938 goto err_unpin;
1690e1eb 1939
9a5a53b3 1940 i915_gem_object_pin_fence(obj);
6b95a207 1941
ce453d81 1942 dev_priv->mm.interruptible = true;
6b95a207 1943 return 0;
48b956c5
CW		 1944
1945err_unpin:
cc98b413 1946 i915_gem_object_unpin_from_display_plane(obj);
ce453d81
CW		 1947err_interruptible:
1948 dev_priv->mm.interruptible = true;
48b956c5 1949 return ret;
6b95a207
KH		 1950}
1951
1690e1eb
CW		 1952void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1953{
1954 i915_gem_object_unpin_fence(obj);
cc98b413 1955 i915_gem_object_unpin_from_display_plane(obj);
1690e1eb
CW		 1956}
1957
c2c75131
DV		 1958/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1959 * is assumed to be a power-of-two. */
bc752862
CW		 1960unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1961 unsigned int tiling_mode,
1962 unsigned int cpp,
1963 unsigned int pitch)
c2c75131 1964{
bc752862
CW		 1965 if (tiling_mode != I915_TILING_NONE) {
1966 unsigned int tile_rows, tiles;
c2c75131 1967
bc752862
CW		 1968 tile_rows = *y / 8;
1969 *y %= 8;
c2c75131 1970
bc752862
CW		 1971 tiles = *x / (512/cpp);
1972 *x %= 512/cpp;
1973
1974 return tile_rows * pitch * 8 + tiles * 4096;
1975 } else {
1976 unsigned int offset;
1977
1978 offset = *y * pitch + *x * cpp;
1979 *y = 0;
1980 *x = (offset & 4095) / cpp;
1981 return offset & -4096;
1982 }
c2c75131
DV		 1983}
1984
17638cd6
JB		 1985static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1986 int x, int y)
81255565
JB		 1987{
1988 struct drm_device *dev = crtc->dev;
1989 struct drm_i915_private *dev_priv = dev->dev_private;
1990 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1991 struct intel_framebuffer *intel_fb;
05394f39 1992 struct drm_i915_gem_object *obj;
81255565 1993 int plane = intel_crtc->plane;
e506a0c6 1994 unsigned long linear_offset;
81255565 1995 u32 dspcntr;
5eddb70b 1996 u32 reg;
81255565
JB		 1997
1998 switch (plane) {
1999 case 0:
2000 case 1:
2001 break;
2002 default:
84f44ce7 2003 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 2004 return -EINVAL;
2005 }
2006
2007 intel_fb = to_intel_framebuffer(fb);
2008 obj = intel_fb->obj;
81255565 2009
5eddb70b
CW		 2010 reg = DSPCNTR(plane);
2011 dspcntr = I915_READ(reg);
81255565
JB		 2012 /* Mask out pixel format bits in case we change it */
2013 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2014 switch (fb->pixel_format) {
2015 case DRM_FORMAT_C8:
81255565
JB		 2016 dspcntr |= DISPPLANE_8BPP;
2017 break;
57779d06
VS		 2018 case DRM_FORMAT_XRGB1555:
2019 case DRM_FORMAT_ARGB1555:
2020 dspcntr |= DISPPLANE_BGRX555;
81255565 2021 break;
57779d06
VS		 2022 case DRM_FORMAT_RGB565:
2023 dspcntr |= DISPPLANE_BGRX565;
2024 break;
2025 case DRM_FORMAT_XRGB8888:
2026 case DRM_FORMAT_ARGB8888:
2027 dspcntr |= DISPPLANE_BGRX888;
2028 break;
2029 case DRM_FORMAT_XBGR8888:
2030 case DRM_FORMAT_ABGR8888:
2031 dspcntr |= DISPPLANE_RGBX888;
2032 break;
2033 case DRM_FORMAT_XRGB2101010:
2034 case DRM_FORMAT_ARGB2101010:
2035 dspcntr |= DISPPLANE_BGRX101010;
2036 break;
2037 case DRM_FORMAT_XBGR2101010:
2038 case DRM_FORMAT_ABGR2101010:
2039 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2040 break;
2041 default:
baba133a 2042 BUG();
81255565 2043 }
57779d06 2044
a6c45cf0 2045 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2046 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2047 dspcntr |= DISPPLANE_TILED;
2048 else
2049 dspcntr &= ~DISPPLANE_TILED;
2050 }
2051
de1aa629
VS		 2052 if (IS_G4X(dev))
2053 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2054
5eddb70b 2055 I915_WRITE(reg, dspcntr);
81255565 2056
e506a0c6 2057 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2058
c2c75131
DV		 2059 if (INTEL_INFO(dev)->gen >= 4) {
2060 intel_crtc->dspaddr_offset =
bc752862
CW		 2061 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2062 fb->bits_per_pixel / 8,
2063 fb->pitches[0]);
c2c75131
DV		 2064 linear_offset -= intel_crtc->dspaddr_offset;
2065 } else {
e506a0c6 2066 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2067 }
e506a0c6 2068
f343c5f6
BW		 2069 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2070 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2071 fb->pitches[0]);
01f2c773 2072 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2073 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131 2074 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2075 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2076 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2077 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2078 } else
f343c5f6 2079 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2080 POSTING_READ(reg);
81255565 2081
17638cd6
JB		 2082 return 0;
2083}
2084
2085static int ironlake_update_plane(struct drm_crtc *crtc,
2086 struct drm_framebuffer *fb, int x, int y)
2087{
2088 struct drm_device *dev = crtc->dev;
2089 struct drm_i915_private *dev_priv = dev->dev_private;
2090 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2091 struct intel_framebuffer *intel_fb;
2092 struct drm_i915_gem_object *obj;
2093 int plane = intel_crtc->plane;
e506a0c6 2094 unsigned long linear_offset;
17638cd6
JB		 2095 u32 dspcntr;
2096 u32 reg;
2097
2098 switch (plane) {
2099 case 0:
2100 case 1:
27f8227b 2101 case 2:
17638cd6
JB		 2102 break;
2103 default:
84f44ce7 2104 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2105 return -EINVAL;
2106 }
2107
2108 intel_fb = to_intel_framebuffer(fb);
2109 obj = intel_fb->obj;
2110
2111 reg = DSPCNTR(plane);
2112 dspcntr = I915_READ(reg);
2113 /* Mask out pixel format bits in case we change it */
2114 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2115 switch (fb->pixel_format) {
2116 case DRM_FORMAT_C8:
17638cd6
JB		 2117 dspcntr |= DISPPLANE_8BPP;
2118 break;
57779d06
VS		 2119 case DRM_FORMAT_RGB565:
2120 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2121 break;
57779d06
VS		 2122 case DRM_FORMAT_XRGB8888:
2123 case DRM_FORMAT_ARGB8888:
2124 dspcntr |= DISPPLANE_BGRX888;
2125 break;
2126 case DRM_FORMAT_XBGR8888:
2127 case DRM_FORMAT_ABGR8888:
2128 dspcntr |= DISPPLANE_RGBX888;
2129 break;
2130 case DRM_FORMAT_XRGB2101010:
2131 case DRM_FORMAT_ARGB2101010:
2132 dspcntr |= DISPPLANE_BGRX101010;
2133 break;
2134 case DRM_FORMAT_XBGR2101010:
2135 case DRM_FORMAT_ABGR2101010:
2136 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2137 break;
2138 default:
baba133a 2139 BUG();
17638cd6
JB		 2140 }
2141
2142 if (obj->tiling_mode != I915_TILING_NONE)
2143 dspcntr |= DISPPLANE_TILED;
2144 else
2145 dspcntr &= ~DISPPLANE_TILED;
2146
1f5d76db
PZ		 2147 if (IS_HASWELL(dev))
2148 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2149 else
2150 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6
JB		 2151
2152 I915_WRITE(reg, dspcntr);
2153
e506a0c6 2154 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2155 intel_crtc->dspaddr_offset =
bc752862
CW		 2156 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2157 fb->bits_per_pixel / 8,
2158 fb->pitches[0]);
c2c75131 2159 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2160
f343c5f6
BW		 2161 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2162 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2163 fb->pitches[0]);
01f2c773 2164 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131 2165 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2166 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2167 if (IS_HASWELL(dev)) {
2168 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2169 } else {
2170 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2171 I915_WRITE(DSPLINOFF(plane), linear_offset);
2172 }
17638cd6
JB		 2173 POSTING_READ(reg);
2174
2175 return 0;
2176}
2177
2178/* Assume fb object is pinned & idle & fenced and just update base pointers */
2179static int
2180intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2181 int x, int y, enum mode_set_atomic state)
2182{
2183 struct drm_device *dev = crtc->dev;
2184 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2185
6b8e6ed0
CW		 2186 if (dev_priv->display.disable_fbc)
2187 dev_priv->display.disable_fbc(dev);
3dec0095 2188 intel_increase_pllclock(crtc);
81255565 2189
6b8e6ed0 2190 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2191}
2192
96a02917
VS		 2193void intel_display_handle_reset(struct drm_device *dev)
2194{
2195 struct drm_i915_private *dev_priv = dev->dev_private;
2196 struct drm_crtc *crtc;
2197
2198 /*
2199 * Flips in the rings have been nuked by the reset,
2200 * so complete all pending flips so that user space
2201 * will get its events and not get stuck.
2202 *
2203 * Also update the base address of all primary
2204 * planes to the the last fb to make sure we're
2205 * showing the correct fb after a reset.
2206 *
2207 * Need to make two loops over the crtcs so that we
2208 * don't try to grab a crtc mutex before the
2209 * pending_flip_queue really got woken up.
2210 */
2211
2212 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2213 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2214 enum plane plane = intel_crtc->plane;
2215
2216 intel_prepare_page_flip(dev, plane);
2217 intel_finish_page_flip_plane(dev, plane);
2218 }
2219
2220 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2221 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2222
2223 mutex_lock(&crtc->mutex);
2224 if (intel_crtc->active)
2225 dev_priv->display.update_plane(crtc, crtc->fb,
2226 crtc->x, crtc->y);
2227 mutex_unlock(&crtc->mutex);
2228 }
2229}
2230
14667a4b
CW		 2231static int
2232intel_finish_fb(struct drm_framebuffer *old_fb)
2233{
2234 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2235 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2236 bool was_interruptible = dev_priv->mm.interruptible;
2237 int ret;
2238
14667a4b
CW		 2239 /* Big Hammer, we also need to ensure that any pending
2240 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2241 * current scanout is retired before unpinning the old
2242 * framebuffer.
2243 *
2244 * This should only fail upon a hung GPU, in which case we
2245 * can safely continue.
2246 */
2247 dev_priv->mm.interruptible = false;
2248 ret = i915_gem_object_finish_gpu(obj);
2249 dev_priv->mm.interruptible = was_interruptible;
2250
2251 return ret;
2252}
2253
198598d0
VS		 2254static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2255{
2256 struct drm_device *dev = crtc->dev;
2257 struct drm_i915_master_private *master_priv;
2258 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2259
2260 if (!dev->primary->master)
2261 return;
2262
2263 master_priv = dev->primary->master->driver_priv;
2264 if (!master_priv->sarea_priv)
2265 return;
2266
2267 switch (intel_crtc->pipe) {
2268 case 0:
2269 master_priv->sarea_priv->pipeA_x = x;
2270 master_priv->sarea_priv->pipeA_y = y;
2271 break;
2272 case 1:
2273 master_priv->sarea_priv->pipeB_x = x;
2274 master_priv->sarea_priv->pipeB_y = y;
2275 break;
2276 default:
2277 break;
2278 }
2279}
2280
5c3b82e2 2281static int
3c4fdcfb 2282intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2283 struct drm_framebuffer *fb)
79e53945
JB		 2284{
2285 struct drm_device *dev = crtc->dev;
6b8e6ed0 2286 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2287 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2288 struct drm_framebuffer *old_fb;
5c3b82e2 2289 int ret;
79e53945
JB		 2290
2291 /* no fb bound */
94352cf9 2292 if (!fb) {
a5071c2f 2293 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2294 return 0;
2295 }
2296
7eb552ae 2297 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2298 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2299 plane_name(intel_crtc->plane),
2300 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2301 return -EINVAL;
79e53945
JB		 2302 }
2303
5c3b82e2 2304 mutex_lock(&dev->struct_mutex);
265db958 2305 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2306 to_intel_framebuffer(fb)->obj,
919926ae 2307 NULL);
5c3b82e2
CW		 2308 if (ret != 0) {
2309 mutex_unlock(&dev->struct_mutex);
a5071c2f 2310 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2311 return ret;
2312 }
79e53945 2313
bb2043de
DL		 2314 /*
2315 * Update pipe size and adjust fitter if needed: the reason for this is
2316 * that in compute_mode_changes we check the native mode (not the pfit
2317 * mode) to see if we can flip rather than do a full mode set. In the
2318 * fastboot case, we'll flip, but if we don't update the pipesrc and
2319 * pfit state, we'll end up with a big fb scanned out into the wrong
2320 * sized surface.
2321 *
2322 * To fix this properly, we need to hoist the checks up into
2323 * compute_mode_changes (or above), check the actual pfit state and
2324 * whether the platform allows pfit disable with pipe active, and only
2325 * then update the pipesrc and pfit state, even on the flip path.
2326 */
4d6a3e63 2327 if (i915_fastboot) {
d7bf63f2
DL		 2328 const struct drm_display_mode *adjusted_mode =
2329 &intel_crtc->config.adjusted_mode;
2330
4d6a3e63 2331 I915_WRITE(PIPESRC(intel_crtc->pipe),
d7bf63f2
DL		 2332 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2333 (adjusted_mode->crtc_vdisplay - 1));
fd4daa9c 2334 if (!intel_crtc->config.pch_pfit.enabled &&
4d6a3e63
JB		 2335 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2336 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2337 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2338 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2339 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2340 }
2341 }
2342
94352cf9 2343 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2344 if (ret) {
94352cf9 2345 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2346 mutex_unlock(&dev->struct_mutex);
a5071c2f 2347 DRM_ERROR("failed to update base address\n");
4e6cfefc 2348 return ret;
79e53945 2349 }
3c4fdcfb 2350
94352cf9
DV		 2351 old_fb = crtc->fb;
2352 crtc->fb = fb;
6c4c86f5
DV		 2353 crtc->x = x;
2354 crtc->y = y;
94352cf9 2355
b7f1de28 2356 if (old_fb) {
d7697eea
DV		 2357 if (intel_crtc->active && old_fb != fb)
2358 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2359 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2360 }
652c393a 2361
6b8e6ed0 2362 intel_update_fbc(dev);
4906557e 2363 intel_edp_psr_update(dev);
5c3b82e2 2364 mutex_unlock(&dev->struct_mutex);
79e53945 2365
198598d0 2366 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2367
2368 return 0;
79e53945
JB		 2369}
2370
5e84e1a4
ZW		 2371static void intel_fdi_normal_train(struct drm_crtc *crtc)
2372{
2373 struct drm_device *dev = crtc->dev;
2374 struct drm_i915_private *dev_priv = dev->dev_private;
2375 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2376 int pipe = intel_crtc->pipe;
2377 u32 reg, temp;
2378
2379 /* enable normal train */
2380 reg = FDI_TX_CTL(pipe);
2381 temp = I915_READ(reg);
61e499bf 2382 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2383 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2384 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2385 } else {
2386 temp &= ~FDI_LINK_TRAIN_NONE;
2387 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2388 }
5e84e1a4
ZW		 2389 I915_WRITE(reg, temp);
2390
2391 reg = FDI_RX_CTL(pipe);
2392 temp = I915_READ(reg);
2393 if (HAS_PCH_CPT(dev)) {
2394 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2395 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2396 } else {
2397 temp &= ~FDI_LINK_TRAIN_NONE;
2398 temp |= FDI_LINK_TRAIN_NONE;
2399 }
2400 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2401
2402 /* wait one idle pattern time */
2403 POSTING_READ(reg);
2404 udelay(1000);
357555c0
JB		 2405
2406 /* IVB wants error correction enabled */
2407 if (IS_IVYBRIDGE(dev))
2408 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2409 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2410}
2411
1e833f40
DV		 2412static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2413{
2414 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2415}
2416
01a415fd
DV		 2417static void ivb_modeset_global_resources(struct drm_device *dev)
2418{
2419 struct drm_i915_private *dev_priv = dev->dev_private;
2420 struct intel_crtc *pipe_B_crtc =
2421 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2422 struct intel_crtc *pipe_C_crtc =
2423 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2424 uint32_t temp;
2425
1e833f40
DV		 2426 /*
2427 * When everything is off disable fdi C so that we could enable fdi B
2428 * with all lanes. Note that we don't care about enabled pipes without
2429 * an enabled pch encoder.
2430 */
2431 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2432 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2433 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2434 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2435
2436 temp = I915_READ(SOUTH_CHICKEN1);
2437 temp &= ~FDI_BC_BIFURCATION_SELECT;
2438 DRM_DEBUG_KMS("disabling fdi C rx\n");
2439 I915_WRITE(SOUTH_CHICKEN1, temp);
2440 }
2441}
2442
8db9d77b
ZW		 2443/* The FDI link training functions for ILK/Ibexpeak. */
2444static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2445{
2446 struct drm_device *dev = crtc->dev;
2447 struct drm_i915_private *dev_priv = dev->dev_private;
2448 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2449 int pipe = intel_crtc->pipe;
0fc932b8 2450 int plane = intel_crtc->plane;
5eddb70b 2451 u32 reg, temp, tries;
8db9d77b 2452
0fc932b8
JB		 2453 /* FDI needs bits from pipe & plane first */
2454 assert_pipe_enabled(dev_priv, pipe);
2455 assert_plane_enabled(dev_priv, plane);
2456
e1a44743
AJ		 2457 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2458 for train result */
5eddb70b
CW		 2459 reg = FDI_RX_IMR(pipe);
2460 temp = I915_READ(reg);
e1a44743
AJ		 2461 temp &= ~FDI_RX_SYMBOL_LOCK;
2462 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2463 I915_WRITE(reg, temp);
2464 I915_READ(reg);
e1a44743
AJ		 2465 udelay(150);
2466
8db9d77b 2467 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2468 reg = FDI_TX_CTL(pipe);
2469 temp = I915_READ(reg);
627eb5a3
DV		 2470 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2471 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2472 temp &= ~FDI_LINK_TRAIN_NONE;
2473 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2474 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2475
5eddb70b
CW		 2476 reg = FDI_RX_CTL(pipe);
2477 temp = I915_READ(reg);
8db9d77b
ZW		 2478 temp &= ~FDI_LINK_TRAIN_NONE;
2479 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2480 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2481
2482 POSTING_READ(reg);
8db9d77b
ZW		 2483 udelay(150);
2484
5b2adf89 2485 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2486 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2487 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2488 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2489
5eddb70b 2490 reg = FDI_RX_IIR(pipe);
e1a44743 2491 for (tries = 0; tries < 5; tries++) {
5eddb70b 2492 temp = I915_READ(reg);
8db9d77b
ZW		 2493 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2494
2495 if ((temp & FDI_RX_BIT_LOCK)) {
2496 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2497 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2498 break;
2499 }
8db9d77b 2500 }
e1a44743 2501 if (tries == 5)
5eddb70b 2502 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2503
2504 /* Train 2 */
5eddb70b
CW		 2505 reg = FDI_TX_CTL(pipe);
2506 temp = I915_READ(reg);
8db9d77b
ZW		 2507 temp &= ~FDI_LINK_TRAIN_NONE;
2508 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2509 I915_WRITE(reg, temp);
8db9d77b 2510
5eddb70b
CW		 2511 reg = FDI_RX_CTL(pipe);
2512 temp = I915_READ(reg);
8db9d77b
ZW		 2513 temp &= ~FDI_LINK_TRAIN_NONE;
2514 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2515 I915_WRITE(reg, temp);
8db9d77b 2516
5eddb70b
CW		 2517 POSTING_READ(reg);
2518 udelay(150);
8db9d77b 2519
5eddb70b 2520 reg = FDI_RX_IIR(pipe);
e1a44743 2521 for (tries = 0; tries < 5; tries++) {
5eddb70b 2522 temp = I915_READ(reg);
8db9d77b
ZW		 2523 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2524
2525 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2526 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2527 DRM_DEBUG_KMS("FDI train 2 done.\n");
2528 break;
2529 }
8db9d77b 2530 }
e1a44743 2531 if (tries == 5)
5eddb70b 2532 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2533
2534 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2535
8db9d77b
ZW		 2536}
2537
0206e353 2538static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2539 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2540 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2541 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2542 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2543};
2544
2545/* The FDI link training functions for SNB/Cougarpoint. */
2546static void gen6_fdi_link_train(struct drm_crtc *crtc)
2547{
2548 struct drm_device *dev = crtc->dev;
2549 struct drm_i915_private *dev_priv = dev->dev_private;
2550 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2551 int pipe = intel_crtc->pipe;
fa37d39e 2552 u32 reg, temp, i, retry;
8db9d77b 2553
e1a44743
AJ		 2554 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2555 for train result */
5eddb70b
CW		 2556 reg = FDI_RX_IMR(pipe);
2557 temp = I915_READ(reg);
e1a44743
AJ		 2558 temp &= ~FDI_RX_SYMBOL_LOCK;
2559 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2560 I915_WRITE(reg, temp);
2561
2562 POSTING_READ(reg);
e1a44743
AJ		 2563 udelay(150);
2564
8db9d77b 2565 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2566 reg = FDI_TX_CTL(pipe);
2567 temp = I915_READ(reg);
627eb5a3
DV		 2568 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2569 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2570 temp &= ~FDI_LINK_TRAIN_NONE;
2571 temp |= FDI_LINK_TRAIN_PATTERN_1;
2572 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2573 /* SNB-B */
2574 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2575 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2576
d74cf324
DV		 2577 I915_WRITE(FDI_RX_MISC(pipe),
2578 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2579
5eddb70b
CW		 2580 reg = FDI_RX_CTL(pipe);
2581 temp = I915_READ(reg);
8db9d77b
ZW		 2582 if (HAS_PCH_CPT(dev)) {
2583 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2584 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2585 } else {
2586 temp &= ~FDI_LINK_TRAIN_NONE;
2587 temp |= FDI_LINK_TRAIN_PATTERN_1;
2588 }
5eddb70b
CW		 2589 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2590
2591 POSTING_READ(reg);
8db9d77b
ZW		 2592 udelay(150);
2593
0206e353 2594 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2595 reg = FDI_TX_CTL(pipe);
2596 temp = I915_READ(reg);
8db9d77b
ZW		 2597 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2598 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2599 I915_WRITE(reg, temp);
2600
2601 POSTING_READ(reg);
8db9d77b
ZW		 2602 udelay(500);
2603
fa37d39e
SP		 2604 for (retry = 0; retry < 5; retry++) {
2605 reg = FDI_RX_IIR(pipe);
2606 temp = I915_READ(reg);
2607 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2608 if (temp & FDI_RX_BIT_LOCK) {
2609 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2610 DRM_DEBUG_KMS("FDI train 1 done.\n");
2611 break;
2612 }
2613 udelay(50);
8db9d77b 2614 }
fa37d39e
SP		 2615 if (retry < 5)
2616 break;
8db9d77b
ZW		 2617 }
2618 if (i == 4)
5eddb70b 2619 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2620
2621 /* Train 2 */
5eddb70b
CW		 2622 reg = FDI_TX_CTL(pipe);
2623 temp = I915_READ(reg);
8db9d77b
ZW		 2624 temp &= ~FDI_LINK_TRAIN_NONE;
2625 temp |= FDI_LINK_TRAIN_PATTERN_2;
2626 if (IS_GEN6(dev)) {
2627 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2628 /* SNB-B */
2629 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2630 }
5eddb70b 2631 I915_WRITE(reg, temp);
8db9d77b 2632
5eddb70b
CW		 2633 reg = FDI_RX_CTL(pipe);
2634 temp = I915_READ(reg);
8db9d77b
ZW		 2635 if (HAS_PCH_CPT(dev)) {
2636 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2637 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2638 } else {
2639 temp &= ~FDI_LINK_TRAIN_NONE;
2640 temp |= FDI_LINK_TRAIN_PATTERN_2;
2641 }
5eddb70b
CW		 2642 I915_WRITE(reg, temp);
2643
2644 POSTING_READ(reg);
8db9d77b
ZW		 2645 udelay(150);
2646
0206e353 2647 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2648 reg = FDI_TX_CTL(pipe);
2649 temp = I915_READ(reg);
8db9d77b
ZW		 2650 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2651 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2652 I915_WRITE(reg, temp);
2653
2654 POSTING_READ(reg);
8db9d77b
ZW		 2655 udelay(500);
2656
fa37d39e
SP		 2657 for (retry = 0; retry < 5; retry++) {
2658 reg = FDI_RX_IIR(pipe);
2659 temp = I915_READ(reg);
2660 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2661 if (temp & FDI_RX_SYMBOL_LOCK) {
2662 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2663 DRM_DEBUG_KMS("FDI train 2 done.\n");
2664 break;
2665 }
2666 udelay(50);
8db9d77b 2667 }
fa37d39e
SP		 2668 if (retry < 5)
2669 break;
8db9d77b
ZW		 2670 }
2671 if (i == 4)
5eddb70b 2672 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2673
2674 DRM_DEBUG_KMS("FDI train done.\n");
2675}
2676
357555c0
JB		 2677/* Manual link training for Ivy Bridge A0 parts */
2678static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2679{
2680 struct drm_device *dev = crtc->dev;
2681 struct drm_i915_private *dev_priv = dev->dev_private;
2682 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2683 int pipe = intel_crtc->pipe;
139ccd3f 2684 u32 reg, temp, i, j;
357555c0
JB		 2685
2686 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2687 for train result */
2688 reg = FDI_RX_IMR(pipe);
2689 temp = I915_READ(reg);
2690 temp &= ~FDI_RX_SYMBOL_LOCK;
2691 temp &= ~FDI_RX_BIT_LOCK;
2692 I915_WRITE(reg, temp);
2693
2694 POSTING_READ(reg);
2695 udelay(150);
2696
01a415fd
DV		 2697 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2698 I915_READ(FDI_RX_IIR(pipe)));
2699
139ccd3f
JB		 2700 /* Try each vswing and preemphasis setting twice before moving on */
2701 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2702 /* disable first in case we need to retry */
2703 reg = FDI_TX_CTL(pipe);
2704 temp = I915_READ(reg);
2705 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2706 temp &= ~FDI_TX_ENABLE;
2707 I915_WRITE(reg, temp);
357555c0 2708
139ccd3f
JB		 2709 reg = FDI_RX_CTL(pipe);
2710 temp = I915_READ(reg);
2711 temp &= ~FDI_LINK_TRAIN_AUTO;
2712 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2713 temp &= ~FDI_RX_ENABLE;
2714 I915_WRITE(reg, temp);
357555c0 2715
139ccd3f 2716 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 2717 reg = FDI_TX_CTL(pipe);
2718 temp = I915_READ(reg);
139ccd3f
JB		 2719 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2720 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2721 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 2722 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 2723 temp |= snb_b_fdi_train_param[j/2];
2724 temp |= FDI_COMPOSITE_SYNC;
2725 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 2726
139ccd3f
JB		 2727 I915_WRITE(FDI_RX_MISC(pipe),
2728 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 2729
139ccd3f 2730 reg = FDI_RX_CTL(pipe);
357555c0 2731 temp = I915_READ(reg);
139ccd3f
JB		 2732 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2733 temp |= FDI_COMPOSITE_SYNC;
2734 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 2735
139ccd3f
JB		 2736 POSTING_READ(reg);
2737 udelay(1); /* should be 0.5us */
357555c0 2738
139ccd3f
JB		 2739 for (i = 0; i < 4; i++) {
2740 reg = FDI_RX_IIR(pipe);
2741 temp = I915_READ(reg);
2742 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2743
139ccd3f
JB		 2744 if (temp & FDI_RX_BIT_LOCK ||
2745 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2746 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2747 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2748 i);
2749 break;
2750 }
2751 udelay(1); /* should be 0.5us */
2752 }
2753 if (i == 4) {
2754 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2755 continue;
2756 }
357555c0 2757
139ccd3f 2758 /* Train 2 */
357555c0
JB		 2759 reg = FDI_TX_CTL(pipe);
2760 temp = I915_READ(reg);
139ccd3f
JB		 2761 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2762 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2763 I915_WRITE(reg, temp);
2764
2765 reg = FDI_RX_CTL(pipe);
2766 temp = I915_READ(reg);
2767 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2768 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 2769 I915_WRITE(reg, temp);
2770
2771 POSTING_READ(reg);
139ccd3f 2772 udelay(2); /* should be 1.5us */
357555c0 2773
139ccd3f
JB		 2774 for (i = 0; i < 4; i++) {
2775 reg = FDI_RX_IIR(pipe);
2776 temp = I915_READ(reg);
2777 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2778
139ccd3f
JB		 2779 if (temp & FDI_RX_SYMBOL_LOCK ||
2780 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2781 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2782 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2783 i);
2784 goto train_done;
2785 }
2786 udelay(2); /* should be 1.5us */
357555c0 2787 }
139ccd3f
JB		 2788 if (i == 4)
2789 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 2790 }
357555c0 2791
139ccd3f 2792train_done:
357555c0
JB		 2793 DRM_DEBUG_KMS("FDI train done.\n");
2794}
2795
88cefb6c 2796static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2797{
88cefb6c 2798 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2799 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2800 int pipe = intel_crtc->pipe;
5eddb70b 2801 u32 reg, temp;
79e53945 2802
c64e311e 2803
c98e9dcf 2804 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2805 reg = FDI_RX_CTL(pipe);
2806 temp = I915_READ(reg);
627eb5a3
DV		 2807 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2808 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2809 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2810 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2811
2812 POSTING_READ(reg);
c98e9dcf
JB		 2813 udelay(200);
2814
2815 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2816 temp = I915_READ(reg);
2817 I915_WRITE(reg, temp | FDI_PCDCLK);
2818
2819 POSTING_READ(reg);
c98e9dcf
JB		 2820 udelay(200);
2821
20749730
PZ		 2822 /* Enable CPU FDI TX PLL, always on for Ironlake */
2823 reg = FDI_TX_CTL(pipe);
2824 temp = I915_READ(reg);
2825 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2826 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2827
20749730
PZ		 2828 POSTING_READ(reg);
2829 udelay(100);
6be4a607 2830 }
0e23b99d
JB		 2831}
2832
88cefb6c
DV		 2833static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2834{
2835 struct drm_device *dev = intel_crtc->base.dev;
2836 struct drm_i915_private *dev_priv = dev->dev_private;
2837 int pipe = intel_crtc->pipe;
2838 u32 reg, temp;
2839
2840 /* Switch from PCDclk to Rawclk */
2841 reg = FDI_RX_CTL(pipe);
2842 temp = I915_READ(reg);
2843 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2844
2845 /* Disable CPU FDI TX PLL */
2846 reg = FDI_TX_CTL(pipe);
2847 temp = I915_READ(reg);
2848 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2849
2850 POSTING_READ(reg);
2851 udelay(100);
2852
2853 reg = FDI_RX_CTL(pipe);
2854 temp = I915_READ(reg);
2855 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2856
2857 /* Wait for the clocks to turn off. */
2858 POSTING_READ(reg);
2859 udelay(100);
2860}
2861
0fc932b8
JB		 2862static void ironlake_fdi_disable(struct drm_crtc *crtc)
2863{
2864 struct drm_device *dev = crtc->dev;
2865 struct drm_i915_private *dev_priv = dev->dev_private;
2866 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2867 int pipe = intel_crtc->pipe;
2868 u32 reg, temp;
2869
2870 /* disable CPU FDI tx and PCH FDI rx */
2871 reg = FDI_TX_CTL(pipe);
2872 temp = I915_READ(reg);
2873 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2874 POSTING_READ(reg);
2875
2876 reg = FDI_RX_CTL(pipe);
2877 temp = I915_READ(reg);
2878 temp &= ~(0x7 << 16);
dfd07d72 2879 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2880 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2881
2882 POSTING_READ(reg);
2883 udelay(100);
2884
2885 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2886 if (HAS_PCH_IBX(dev)) {
2887 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2888 }
0fc932b8
JB		 2889
2890 /* still set train pattern 1 */
2891 reg = FDI_TX_CTL(pipe);
2892 temp = I915_READ(reg);
2893 temp &= ~FDI_LINK_TRAIN_NONE;
2894 temp |= FDI_LINK_TRAIN_PATTERN_1;
2895 I915_WRITE(reg, temp);
2896
2897 reg = FDI_RX_CTL(pipe);
2898 temp = I915_READ(reg);
2899 if (HAS_PCH_CPT(dev)) {
2900 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2901 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2902 } else {
2903 temp &= ~FDI_LINK_TRAIN_NONE;
2904 temp |= FDI_LINK_TRAIN_PATTERN_1;
2905 }
2906 /* BPC in FDI rx is consistent with that in PIPECONF */
2907 temp &= ~(0x07 << 16);
dfd07d72 2908 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2909 I915_WRITE(reg, temp);
2910
2911 POSTING_READ(reg);
2912 udelay(100);
2913}
2914
5bb61643
CW		 2915static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2916{
2917 struct drm_device *dev = crtc->dev;
2918 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2919 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2920 unsigned long flags;
2921 bool pending;
2922
10d83730
VS		 2923 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2924 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2925 return false;
2926
2927 spin_lock_irqsave(&dev->event_lock, flags);
2928 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2929 spin_unlock_irqrestore(&dev->event_lock, flags);
2930
2931 return pending;
2932}
2933
e6c3a2a6
CW		 2934static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2935{
0f91128d 2936 struct drm_device *dev = crtc->dev;
5bb61643 2937 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2938
2939 if (crtc->fb == NULL)
2940 return;
2941
2c10d571
DV		 2942 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2943
5bb61643
CW		 2944 wait_event(dev_priv->pending_flip_queue,
2945 !intel_crtc_has_pending_flip(crtc));
2946
0f91128d
CW		 2947 mutex_lock(&dev->struct_mutex);
2948 intel_finish_fb(crtc->fb);
2949 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2950}
2951
e615efe4
ED		 2952/* Program iCLKIP clock to the desired frequency */
2953static void lpt_program_iclkip(struct drm_crtc *crtc)
2954{
2955 struct drm_device *dev = crtc->dev;
2956 struct drm_i915_private *dev_priv = dev->dev_private;
241bfc38 2957 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
e615efe4
ED		 2958 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2959 u32 temp;
2960
09153000
DV		 2961 mutex_lock(&dev_priv->dpio_lock);
2962
e615efe4
ED		 2963 /* It is necessary to ungate the pixclk gate prior to programming
2964 * the divisors, and gate it back when it is done.
2965 */
2966 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2967
2968 /* Disable SSCCTL */
2969 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2970 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2971 SBI_SSCCTL_DISABLE,
2972 SBI_ICLK);
e615efe4
ED		 2973
2974 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 2975 if (clock == 20000) {
e615efe4
ED		 2976 auxdiv = 1;
2977 divsel = 0x41;
2978 phaseinc = 0x20;
2979 } else {
2980 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 2981 * but the adjusted_mode->crtc_clock in in KHz. To get the
2982 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 2983 * convert the virtual clock precision to KHz here for higher
2984 * precision.
2985 */
2986 u32 iclk_virtual_root_freq = 172800 * 1000;
2987 u32 iclk_pi_range = 64;
2988 u32 desired_divisor, msb_divisor_value, pi_value;
2989
12d7ceed 2990 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 2991 msb_divisor_value = desired_divisor / iclk_pi_range;
2992 pi_value = desired_divisor % iclk_pi_range;
2993
2994 auxdiv = 0;
2995 divsel = msb_divisor_value - 2;
2996 phaseinc = pi_value;
2997 }
2998
2999 /* This should not happen with any sane values */
3000 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3001 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3002 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3003 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3004
3005 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3006 clock,
e615efe4
ED		 3007 auxdiv,
3008 divsel,
3009 phasedir,
3010 phaseinc);
3011
3012 /* Program SSCDIVINTPHASE6 */
988d6ee8 3013 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3014 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3015 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3016 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3017 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3018 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3019 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3020 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3021
3022 /* Program SSCAUXDIV */
988d6ee8 3023 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3024 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3025 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3026 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3027
3028 /* Enable modulator and associated divider */
988d6ee8 3029 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3030 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3031 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3032
3033 /* Wait for initialization time */
3034 udelay(24);
3035
3036 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 3037
3038 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 3039}
3040
275f01b2
DV		 3041static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3042 enum pipe pch_transcoder)
3043{
3044 struct drm_device *dev = crtc->base.dev;
3045 struct drm_i915_private *dev_priv = dev->dev_private;
3046 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3047
3048 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3049 I915_READ(HTOTAL(cpu_transcoder)));
3050 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3051 I915_READ(HBLANK(cpu_transcoder)));
3052 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3053 I915_READ(HSYNC(cpu_transcoder)));
3054
3055 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3056 I915_READ(VTOTAL(cpu_transcoder)));
3057 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3058 I915_READ(VBLANK(cpu_transcoder)));
3059 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3060 I915_READ(VSYNC(cpu_transcoder)));
3061 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3062 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3063}
3064
f67a559d
JB		 3065/*
3066 * Enable PCH resources required for PCH ports:
3067 * - PCH PLLs
3068 * - FDI training & RX/TX
3069 * - update transcoder timings
3070 * - DP transcoding bits
3071 * - transcoder
3072 */
3073static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3074{
3075 struct drm_device *dev = crtc->dev;
3076 struct drm_i915_private *dev_priv = dev->dev_private;
3077 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3078 int pipe = intel_crtc->pipe;
ee7b9f93 3079 u32 reg, temp;
2c07245f 3080
ab9412ba 3081 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 3082
cd986abb
DV		 3083 /* Write the TU size bits before fdi link training, so that error
3084 * detection works. */
3085 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3086 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3087
c98e9dcf 3088 /* For PCH output, training FDI link */
674cf967 3089 dev_priv->display.fdi_link_train(crtc);
2c07245f 3090
3ad8a208
DV		 3091 /* We need to program the right clock selection before writing the pixel
3092 * mutliplier into the DPLL. */
303b81e0 3093 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3094 u32 sel;
4b645f14 3095
c98e9dcf 3096 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 3097 temp |= TRANS_DPLL_ENABLE(pipe);
3098 sel = TRANS_DPLLB_SEL(pipe);
a43f6e0f 3099 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 3100 temp |= sel;
3101 else
3102 temp &= ~sel;
c98e9dcf 3103 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3104 }
5eddb70b 3105
3ad8a208
DV		 3106 /* XXX: pch pll's can be enabled any time before we enable the PCH
3107 * transcoder, and we actually should do this to not upset any PCH
3108 * transcoder that already use the clock when we share it.
3109 *
3110 * Note that enable_shared_dpll tries to do the right thing, but
3111 * get_shared_dpll unconditionally resets the pll - we need that to have
3112 * the right LVDS enable sequence. */
3113 ironlake_enable_shared_dpll(intel_crtc);
3114
d9b6cb56
JB		 3115 /* set transcoder timing, panel must allow it */
3116 assert_panel_unlocked(dev_priv, pipe);
275f01b2 3117 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 3118
303b81e0 3119 intel_fdi_normal_train(crtc);
5e84e1a4 3120
c98e9dcf
JB		 3121 /* For PCH DP, enable TRANS_DP_CTL */
3122 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3123 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3124 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3125 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3126 reg = TRANS_DP_CTL(pipe);
3127 temp = I915_READ(reg);
3128 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3129 TRANS_DP_SYNC_MASK |
3130 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3131 temp |= (TRANS_DP_OUTPUT_ENABLE |
3132 TRANS_DP_ENH_FRAMING);
9325c9f0 3133 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3134
3135 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3136 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3137 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3138 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3139
3140 switch (intel_trans_dp_port_sel(crtc)) {
3141 case PCH_DP_B:
5eddb70b 3142 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3143 break;
3144 case PCH_DP_C:
5eddb70b 3145 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3146 break;
3147 case PCH_DP_D:
5eddb70b 3148 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3149 break;
3150 default:
e95d41e1 3151 BUG();
32f9d658 3152 }
2c07245f 3153
5eddb70b 3154 I915_WRITE(reg, temp);
6be4a607 3155 }
b52eb4dc 3156
b8a4f404 3157 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3158}
3159
1507e5bd
PZ		 3160static void lpt_pch_enable(struct drm_crtc *crtc)
3161{
3162 struct drm_device *dev = crtc->dev;
3163 struct drm_i915_private *dev_priv = dev->dev_private;
3164 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3165 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3166
ab9412ba 3167 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3168
8c52b5e8 3169 lpt_program_iclkip(crtc);
1507e5bd 3170
0540e488 3171 /* Set transcoder timing. */
275f01b2 3172 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3173
937bb610 3174 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3175}
3176
e2b78267 3177static void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3178{
e2b78267 3179 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 3180
3181 if (pll == NULL)
3182 return;
3183
3184 if (pll->refcount == 0) {
46edb027 3185 WARN(1, "bad %s refcount\n", pll->name);
ee7b9f93
JB		 3186 return;
3187 }
3188
f4a091c7
DV		 3189 if (--pll->refcount == 0) {
3190 WARN_ON(pll->on);
3191 WARN_ON(pll->active);
3192 }
3193
a43f6e0f 3194 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 3195}
3196
b89a1d39 3197static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3198{
e2b78267
DV		 3199 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3200 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3201 enum intel_dpll_id i;
ee7b9f93 3202
ee7b9f93 3203 if (pll) {
46edb027
DV		 3204 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3205 crtc->base.base.id, pll->name);
e2b78267 3206 intel_put_shared_dpll(crtc);
ee7b9f93
JB		 3207 }
3208
98b6bd99
DV		 3209 if (HAS_PCH_IBX(dev_priv->dev)) {
3210 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 3211 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 3212 pll = &dev_priv->shared_dplls[i];
98b6bd99 3213
46edb027
DV		 3214 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3215 crtc->base.base.id, pll->name);
98b6bd99
DV		 3216
3217 goto found;
3218 }
3219
e72f9fbf
DV		 3220 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3221 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 3222
3223 /* Only want to check enabled timings first */
3224 if (pll->refcount == 0)
3225 continue;
3226
b89a1d39
DV		 3227 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3228 sizeof(pll->hw_state)) == 0) {
46edb027 3229 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
e2b78267 3230 crtc->base.base.id,
46edb027 3231 pll->name, pll->refcount, pll->active);
ee7b9f93
JB		 3232
3233 goto found;
3234 }
3235 }
3236
3237 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 3238 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3239 pll = &dev_priv->shared_dplls[i];
ee7b9f93 3240 if (pll->refcount == 0) {
46edb027
DV		 3241 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3242 crtc->base.base.id, pll->name);
ee7b9f93
JB		 3243 goto found;
3244 }
3245 }
3246
3247 return NULL;
3248
3249found:
a43f6e0f 3250 crtc->config.shared_dpll = i;
46edb027
DV		 3251 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3252 pipe_name(crtc->pipe));
ee7b9f93 3253
cdbd2316 3254 if (pll->active == 0) {
66e985c0
DV		 3255 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3256 sizeof(pll->hw_state));
3257
46edb027 3258 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
cdbd2316 3259 WARN_ON(pll->on);
e9d6944e 3260 assert_shared_dpll_disabled(dev_priv, pll);
ee7b9f93 3261
15bdd4cf 3262 pll->mode_set(dev_priv, pll);
cdbd2316
DV		 3263 }
3264 pll->refcount++;
e04c7350 3265
ee7b9f93
JB		 3266 return pll;
3267}
3268
a1520318 3269static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3270{
3271 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3272 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3273 u32 temp;
3274
3275 temp = I915_READ(dslreg);
3276 udelay(500);
3277 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3278 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3279 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3280 }
3281}
3282
b074cec8
JB		 3283static void ironlake_pfit_enable(struct intel_crtc *crtc)
3284{
3285 struct drm_device *dev = crtc->base.dev;
3286 struct drm_i915_private *dev_priv = dev->dev_private;
3287 int pipe = crtc->pipe;
3288
fd4daa9c 3289 if (crtc->config.pch_pfit.enabled) {
b074cec8
JB		 3290 /* Force use of hard-coded filter coefficients
3291 * as some pre-programmed values are broken,
3292 * e.g. x201.
3293 */
3294 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3295 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3296 PF_PIPE_SEL_IVB(pipe));
3297 else
3298 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3299 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3300 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
d4270e57
JB		 3301 }
3302}
3303
bb53d4ae
VS		 3304static void intel_enable_planes(struct drm_crtc *crtc)
3305{
3306 struct drm_device *dev = crtc->dev;
3307 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3308 struct intel_plane *intel_plane;
3309
3310 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3311 if (intel_plane->pipe == pipe)
3312 intel_plane_restore(&intel_plane->base);
3313}
3314
3315static void intel_disable_planes(struct drm_crtc *crtc)
3316{
3317 struct drm_device *dev = crtc->dev;
3318 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3319 struct intel_plane *intel_plane;
3320
3321 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3322 if (intel_plane->pipe == pipe)
3323 intel_plane_disable(&intel_plane->base);
3324}
3325
d77e4531
PZ		 3326static void hsw_enable_ips(struct intel_crtc *crtc)
3327{
3328 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3329
3330 if (!crtc->config.ips_enabled)
3331 return;
3332
3333 /* We can only enable IPS after we enable a plane and wait for a vblank.
3334 * We guarantee that the plane is enabled by calling intel_enable_ips
3335 * only after intel_enable_plane. And intel_enable_plane already waits
3336 * for a vblank, so all we need to do here is to enable the IPS bit. */
3337 assert_plane_enabled(dev_priv, crtc->plane);
3338 I915_WRITE(IPS_CTL, IPS_ENABLE);
3339}
3340
3341static void hsw_disable_ips(struct intel_crtc *crtc)
3342{
3343 struct drm_device *dev = crtc->base.dev;
3344 struct drm_i915_private *dev_priv = dev->dev_private;
3345
3346 if (!crtc->config.ips_enabled)
3347 return;
3348
3349 assert_plane_enabled(dev_priv, crtc->plane);
3350 I915_WRITE(IPS_CTL, 0);
3351 POSTING_READ(IPS_CTL);
3352
3353 /* We need to wait for a vblank before we can disable the plane. */
3354 intel_wait_for_vblank(dev, crtc->pipe);
3355}
3356
3357/** Loads the palette/gamma unit for the CRTC with the prepared values */
3358static void intel_crtc_load_lut(struct drm_crtc *crtc)
3359{
3360 struct drm_device *dev = crtc->dev;
3361 struct drm_i915_private *dev_priv = dev->dev_private;
3362 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3363 enum pipe pipe = intel_crtc->pipe;
3364 int palreg = PALETTE(pipe);
3365 int i;
3366 bool reenable_ips = false;
3367
3368 /* The clocks have to be on to load the palette. */
3369 if (!crtc->enabled || !intel_crtc->active)
3370 return;
3371
3372 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3373 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3374 assert_dsi_pll_enabled(dev_priv);
3375 else
3376 assert_pll_enabled(dev_priv, pipe);
3377 }
3378
3379 /* use legacy palette for Ironlake */
3380 if (HAS_PCH_SPLIT(dev))
3381 palreg = LGC_PALETTE(pipe);
3382
3383 /* Workaround : Do not read or write the pipe palette/gamma data while
3384 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3385 */
3386 if (intel_crtc->config.ips_enabled &&
3387 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3388 GAMMA_MODE_MODE_SPLIT)) {
3389 hsw_disable_ips(intel_crtc);
3390 reenable_ips = true;
3391 }
3392
3393 for (i = 0; i < 256; i++) {
3394 I915_WRITE(palreg + 4 * i,
3395 (intel_crtc->lut_r[i] << 16) |
3396 (intel_crtc->lut_g[i] << 8) |
3397 intel_crtc->lut_b[i]);
3398 }
3399
3400 if (reenable_ips)
3401 hsw_enable_ips(intel_crtc);
3402}
3403
f67a559d
JB		 3404static void ironlake_crtc_enable(struct drm_crtc *crtc)
3405{
3406 struct drm_device *dev = crtc->dev;
3407 struct drm_i915_private *dev_priv = dev->dev_private;
3408 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3409 struct intel_encoder *encoder;
f67a559d
JB		 3410 int pipe = intel_crtc->pipe;
3411 int plane = intel_crtc->plane;
f67a559d 3412
08a48469
DV		 3413 WARN_ON(!crtc->enabled);
3414
f67a559d
JB		 3415 if (intel_crtc->active)
3416 return;
3417
3418 intel_crtc->active = true;
8664281b
PZ		 3419
3420 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3421 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3422
f6736a1a 3423 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 3424 if (encoder->pre_enable)
3425 encoder->pre_enable(encoder);
f67a559d 3426
5bfe2ac0 3427 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3428 /* Note: FDI PLL enabling _must_ be done before we enable the
3429 * cpu pipes, hence this is separate from all the other fdi/pch
3430 * enabling. */
88cefb6c 3431 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3432 } else {
3433 assert_fdi_tx_disabled(dev_priv, pipe);
3434 assert_fdi_rx_disabled(dev_priv, pipe);
3435 }
f67a559d 3436
b074cec8 3437 ironlake_pfit_enable(intel_crtc);
f67a559d 3438
9c54c0dd
JB		 3439 /*
3440 * On ILK+ LUT must be loaded before the pipe is running but with
3441 * clocks enabled
3442 */
3443 intel_crtc_load_lut(crtc);
3444
f37fcc2a 3445 intel_update_watermarks(crtc);
5bfe2ac0 3446 intel_enable_pipe(dev_priv, pipe,
23538ef1 3447 intel_crtc->config.has_pch_encoder, false);
f67a559d 3448 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3449 intel_enable_planes(crtc);
5c38d48c 3450 intel_crtc_update_cursor(crtc, true);
f67a559d 3451
5bfe2ac0 3452 if (intel_crtc->config.has_pch_encoder)
f67a559d 3453 ironlake_pch_enable(crtc);
c98e9dcf 3454
d1ebd816 3455 mutex_lock(&dev->struct_mutex);
bed4a673 3456 intel_update_fbc(dev);
d1ebd816
BW		 3457 mutex_unlock(&dev->struct_mutex);
3458
fa5c73b1
DV		 3459 for_each_encoder_on_crtc(dev, crtc, encoder)
3460 encoder->enable(encoder);
61b77ddd
DV		 3461
3462 if (HAS_PCH_CPT(dev))
a1520318 3463 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3464
3465 /*
3466 * There seems to be a race in PCH platform hw (at least on some
3467 * outputs) where an enabled pipe still completes any pageflip right
3468 * away (as if the pipe is off) instead of waiting for vblank. As soon
3469 * as the first vblank happend, everything works as expected. Hence just
3470 * wait for one vblank before returning to avoid strange things
3471 * happening.
3472 */
3473 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3474}
3475
42db64ef
PZ		 3476/* IPS only exists on ULT machines and is tied to pipe A. */
3477static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3478{
f5adf94e 3479 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 3480}
3481
dda9a66a
VS		 3482static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
3483{
3484 struct drm_device *dev = crtc->dev;
3485 struct drm_i915_private *dev_priv = dev->dev_private;
3486 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3487 int pipe = intel_crtc->pipe;
3488 int plane = intel_crtc->plane;
3489
3490 intel_enable_plane(dev_priv, plane, pipe);
3491 intel_enable_planes(crtc);
3492 intel_crtc_update_cursor(crtc, true);
3493
3494 hsw_enable_ips(intel_crtc);
3495
3496 mutex_lock(&dev->struct_mutex);
3497 intel_update_fbc(dev);
3498 mutex_unlock(&dev->struct_mutex);
3499}
3500
3501static void haswell_crtc_disable_planes(struct drm_crtc *crtc)
3502{
3503 struct drm_device *dev = crtc->dev;
3504 struct drm_i915_private *dev_priv = dev->dev_private;
3505 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3506 int pipe = intel_crtc->pipe;
3507 int plane = intel_crtc->plane;
3508
3509 intel_crtc_wait_for_pending_flips(crtc);
3510 drm_vblank_off(dev, pipe);
3511
3512 /* FBC must be disabled before disabling the plane on HSW. */
3513 if (dev_priv->fbc.plane == plane)
3514 intel_disable_fbc(dev);
3515
3516 hsw_disable_ips(intel_crtc);
3517
3518 intel_crtc_update_cursor(crtc, false);
3519 intel_disable_planes(crtc);
3520 intel_disable_plane(dev_priv, plane, pipe);
3521}
3522
e4916946
PZ		 3523/*
3524 * This implements the workaround described in the "notes" section of the mode
3525 * set sequence documentation. When going from no pipes or single pipe to
3526 * multiple pipes, and planes are enabled after the pipe, we need to wait at
3527 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3528 */
3529static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3530{
3531 struct drm_device *dev = crtc->base.dev;
3532 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3533
3534 /* We want to get the other_active_crtc only if there's only 1 other
3535 * active crtc. */
3536 list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3537 if (!crtc_it->active || crtc_it == crtc)
3538 continue;
3539
3540 if (other_active_crtc)
3541 return;
3542
3543 other_active_crtc = crtc_it;
3544 }
3545 if (!other_active_crtc)
3546 return;
3547
3548 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3549 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3550}
3551
4f771f10
PZ		 3552static void haswell_crtc_enable(struct drm_crtc *crtc)
3553{
3554 struct drm_device *dev = crtc->dev;
3555 struct drm_i915_private *dev_priv = dev->dev_private;
3556 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3557 struct intel_encoder *encoder;
3558 int pipe = intel_crtc->pipe;
4f771f10
PZ		 3559
3560 WARN_ON(!crtc->enabled);
3561
3562 if (intel_crtc->active)
3563 return;
3564
3565 intel_crtc->active = true;
8664281b
PZ		 3566
3567 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3568 if (intel_crtc->config.has_pch_encoder)
3569 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3570
5bfe2ac0 3571 if (intel_crtc->config.has_pch_encoder)
04945641 3572 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3573
3574 for_each_encoder_on_crtc(dev, crtc, encoder)
3575 if (encoder->pre_enable)
3576 encoder->pre_enable(encoder);
3577
1f544388 3578 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3579
b074cec8 3580 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3581
3582 /*
3583 * On ILK+ LUT must be loaded before the pipe is running but with
3584 * clocks enabled
3585 */
3586 intel_crtc_load_lut(crtc);
3587
1f544388 3588 intel_ddi_set_pipe_settings(crtc);
8228c251 3589 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3590
f37fcc2a 3591 intel_update_watermarks(crtc);
5bfe2ac0 3592 intel_enable_pipe(dev_priv, pipe,
23538ef1 3593 intel_crtc->config.has_pch_encoder, false);
42db64ef 3594
5bfe2ac0 3595 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3596 lpt_pch_enable(crtc);
4f771f10 3597
8807e55b 3598 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 3599 encoder->enable(encoder);
8807e55b
JN		 3600 intel_opregion_notify_encoder(encoder, true);
3601 }
4f771f10 3602
e4916946
PZ		 3603 /* If we change the relative order between pipe/planes enabling, we need
3604 * to change the workaround. */
3605 haswell_mode_set_planes_workaround(intel_crtc);
dda9a66a
VS		 3606 haswell_crtc_enable_planes(crtc);
3607
4f771f10
PZ		 3608 /*
3609 * There seems to be a race in PCH platform hw (at least on some
3610 * outputs) where an enabled pipe still completes any pageflip right
3611 * away (as if the pipe is off) instead of waiting for vblank. As soon
3612 * as the first vblank happend, everything works as expected. Hence just
3613 * wait for one vblank before returning to avoid strange things
3614 * happening.
3615 */
3616 intel_wait_for_vblank(dev, intel_crtc->pipe);
3617}
3618
3f8dce3a
DV		 3619static void ironlake_pfit_disable(struct intel_crtc *crtc)
3620{
3621 struct drm_device *dev = crtc->base.dev;
3622 struct drm_i915_private *dev_priv = dev->dev_private;
3623 int pipe = crtc->pipe;
3624
3625 /* To avoid upsetting the power well on haswell only disable the pfit if
3626 * it's in use. The hw state code will make sure we get this right. */
fd4daa9c 3627 if (crtc->config.pch_pfit.enabled) {
3f8dce3a
DV		 3628 I915_WRITE(PF_CTL(pipe), 0);
3629 I915_WRITE(PF_WIN_POS(pipe), 0);
3630 I915_WRITE(PF_WIN_SZ(pipe), 0);
3631 }
3632}
3633
6be4a607
JB		 3634static void ironlake_crtc_disable(struct drm_crtc *crtc)
3635{
3636 struct drm_device *dev = crtc->dev;
3637 struct drm_i915_private *dev_priv = dev->dev_private;
3638 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3639 struct intel_encoder *encoder;
6be4a607
JB		 3640 int pipe = intel_crtc->pipe;
3641 int plane = intel_crtc->plane;
5eddb70b 3642 u32 reg, temp;
b52eb4dc 3643
ef9c3aee 3644
f7abfe8b
CW		 3645 if (!intel_crtc->active)
3646 return;
3647
ea9d758d
DV		 3648 for_each_encoder_on_crtc(dev, crtc, encoder)
3649 encoder->disable(encoder);
3650
e6c3a2a6 3651 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3652 drm_vblank_off(dev, pipe);
913d8d11 3653
5c3fe8b0 3654 if (dev_priv->fbc.plane == plane)
973d04f9 3655 intel_disable_fbc(dev);
2c07245f 3656
0d5b8c61 3657 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3658 intel_disable_planes(crtc);
0d5b8c61
VS		 3659 intel_disable_plane(dev_priv, plane, pipe);
3660
d925c59a
DV		 3661 if (intel_crtc->config.has_pch_encoder)
3662 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3663
b24e7179 3664 intel_disable_pipe(dev_priv, pipe);
32f9d658 3665
3f8dce3a 3666 ironlake_pfit_disable(intel_crtc);
2c07245f 3667
bf49ec8c
DV		 3668 for_each_encoder_on_crtc(dev, crtc, encoder)
3669 if (encoder->post_disable)
3670 encoder->post_disable(encoder);
2c07245f 3671
d925c59a
DV		 3672 if (intel_crtc->config.has_pch_encoder) {
3673 ironlake_fdi_disable(crtc);
913d8d11 3674
d925c59a
DV		 3675 ironlake_disable_pch_transcoder(dev_priv, pipe);
3676 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
6be4a607 3677
d925c59a
DV		 3678 if (HAS_PCH_CPT(dev)) {
3679 /* disable TRANS_DP_CTL */
3680 reg = TRANS_DP_CTL(pipe);
3681 temp = I915_READ(reg);
3682 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3683 TRANS_DP_PORT_SEL_MASK);
3684 temp |= TRANS_DP_PORT_SEL_NONE;
3685 I915_WRITE(reg, temp);
3686
3687 /* disable DPLL_SEL */
3688 temp = I915_READ(PCH_DPLL_SEL);
11887397 3689 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 3690 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 3691 }
e3421a18 3692
d925c59a 3693 /* disable PCH DPLL */
e72f9fbf 3694 intel_disable_shared_dpll(intel_crtc);
8db9d77b 3695
d925c59a
DV		 3696 ironlake_fdi_pll_disable(intel_crtc);
3697 }
6b383a7f 3698
f7abfe8b 3699 intel_crtc->active = false;
46ba614c 3700 intel_update_watermarks(crtc);
d1ebd816
BW		 3701
3702 mutex_lock(&dev->struct_mutex);
6b383a7f 3703 intel_update_fbc(dev);
d1ebd816 3704 mutex_unlock(&dev->struct_mutex);
6be4a607 3705}
1b3c7a47 3706
4f771f10 3707static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3708{
4f771f10
PZ		 3709 struct drm_device *dev = crtc->dev;
3710 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3711 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3712 struct intel_encoder *encoder;
3713 int pipe = intel_crtc->pipe;
3b117c8f 3714 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3715
4f771f10
PZ		 3716 if (!intel_crtc->active)
3717 return;
3718
dda9a66a
VS		 3719 haswell_crtc_disable_planes(crtc);
3720
8807e55b
JN		 3721 for_each_encoder_on_crtc(dev, crtc, encoder) {
3722 intel_opregion_notify_encoder(encoder, false);
4f771f10 3723 encoder->disable(encoder);
8807e55b 3724 }
4f771f10 3725
8664281b
PZ		 3726 if (intel_crtc->config.has_pch_encoder)
3727 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3728 intel_disable_pipe(dev_priv, pipe);
3729
ad80a810 3730 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3731
3f8dce3a 3732 ironlake_pfit_disable(intel_crtc);
4f771f10 3733
1f544388 3734 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3735
3736 for_each_encoder_on_crtc(dev, crtc, encoder)
3737 if (encoder->post_disable)
3738 encoder->post_disable(encoder);
3739
88adfff1 3740 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3741 lpt_disable_pch_transcoder(dev_priv);
8664281b 3742 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3743 intel_ddi_fdi_disable(crtc);
83616634 3744 }
4f771f10
PZ		 3745
3746 intel_crtc->active = false;
46ba614c 3747 intel_update_watermarks(crtc);
4f771f10
PZ		 3748
3749 mutex_lock(&dev->struct_mutex);
3750 intel_update_fbc(dev);
3751 mutex_unlock(&dev->struct_mutex);
3752}
3753
ee7b9f93
JB		 3754static void ironlake_crtc_off(struct drm_crtc *crtc)
3755{
3756 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 3757 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 3758}
3759
6441ab5f
PZ		 3760static void haswell_crtc_off(struct drm_crtc *crtc)
3761{
3762 intel_ddi_put_crtc_pll(crtc);
3763}
3764
02e792fb
DV		 3765static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3766{
02e792fb 3767 if (!enable && intel_crtc->overlay) {
23f09ce3 3768 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3769 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3770
23f09ce3 3771 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3772 dev_priv->mm.interruptible = false;
3773 (void) intel_overlay_switch_off(intel_crtc->overlay);
3774 dev_priv->mm.interruptible = true;
23f09ce3 3775 mutex_unlock(&dev->struct_mutex);
02e792fb 3776 }
02e792fb 3777
5dcdbcb0
CW		 3778 /* Let userspace switch the overlay on again. In most cases userspace
3779 * has to recompute where to put it anyway.
3780 */
02e792fb
DV		 3781}
3782
61bc95c1
EE		 3783/**
3784 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3785 * cursor plane briefly if not already running after enabling the display
3786 * plane.
3787 * This workaround avoids occasional blank screens when self refresh is
3788 * enabled.
3789 */
3790static void
3791g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3792{
3793 u32 cntl = I915_READ(CURCNTR(pipe));
3794
3795 if ((cntl & CURSOR_MODE) == 0) {
3796 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3797
3798 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3799 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3800 intel_wait_for_vblank(dev_priv->dev, pipe);
3801 I915_WRITE(CURCNTR(pipe), cntl);
3802 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3803 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3804 }
3805}
3806
2dd24552
JB		 3807static void i9xx_pfit_enable(struct intel_crtc *crtc)
3808{
3809 struct drm_device *dev = crtc->base.dev;
3810 struct drm_i915_private *dev_priv = dev->dev_private;
3811 struct intel_crtc_config *pipe_config = &crtc->config;
3812
328d8e82 3813 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3814 return;
3815
2dd24552 3816 /*
c0b03411
DV		 3817 * The panel fitter should only be adjusted whilst the pipe is disabled,
3818 * according to register description and PRM.
2dd24552 3819 */
c0b03411
DV		 3820 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3821 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3822
b074cec8
JB		 3823 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3824 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3825
3826 /* Border color in case we don't scale up to the full screen. Black by
3827 * default, change to something else for debugging. */
3828 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3829}
3830
89b667f8
JB		 3831static void valleyview_crtc_enable(struct drm_crtc *crtc)
3832{
3833 struct drm_device *dev = crtc->dev;
3834 struct drm_i915_private *dev_priv = dev->dev_private;
3835 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3836 struct intel_encoder *encoder;
3837 int pipe = intel_crtc->pipe;
3838 int plane = intel_crtc->plane;
23538ef1 3839 bool is_dsi;
89b667f8
JB		 3840
3841 WARN_ON(!crtc->enabled);
3842
3843 if (intel_crtc->active)
3844 return;
3845
3846 intel_crtc->active = true;
89b667f8 3847
89b667f8
JB		 3848 for_each_encoder_on_crtc(dev, crtc, encoder)
3849 if (encoder->pre_pll_enable)
3850 encoder->pre_pll_enable(encoder);
3851
23538ef1
JN		 3852 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
3853
e9fd1c02
JN		 3854 if (!is_dsi)
3855 vlv_enable_pll(intel_crtc);
89b667f8
JB		 3856
3857 for_each_encoder_on_crtc(dev, crtc, encoder)
3858 if (encoder->pre_enable)
3859 encoder->pre_enable(encoder);
3860
2dd24552
JB		 3861 i9xx_pfit_enable(intel_crtc);
3862
63cbb074
VS		 3863 intel_crtc_load_lut(crtc);
3864
f37fcc2a 3865 intel_update_watermarks(crtc);
23538ef1 3866 intel_enable_pipe(dev_priv, pipe, false, is_dsi);
89b667f8 3867 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3868 intel_enable_planes(crtc);
5c38d48c 3869 intel_crtc_update_cursor(crtc, true);
89b667f8 3870
89b667f8 3871 intel_update_fbc(dev);
5004945f
JN		 3872
3873 for_each_encoder_on_crtc(dev, crtc, encoder)
3874 encoder->enable(encoder);
89b667f8
JB		 3875}
3876
0b8765c6 3877static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3878{
3879 struct drm_device *dev = crtc->dev;
79e53945
JB		 3880 struct drm_i915_private *dev_priv = dev->dev_private;
3881 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3882 struct intel_encoder *encoder;
79e53945 3883 int pipe = intel_crtc->pipe;
80824003 3884 int plane = intel_crtc->plane;
79e53945 3885
08a48469
DV		 3886 WARN_ON(!crtc->enabled);
3887
f7abfe8b
CW		 3888 if (intel_crtc->active)
3889 return;
3890
3891 intel_crtc->active = true;
6b383a7f 3892
9d6d9f19
MK		 3893 for_each_encoder_on_crtc(dev, crtc, encoder)
3894 if (encoder->pre_enable)
3895 encoder->pre_enable(encoder);
3896
f6736a1a
DV		 3897 i9xx_enable_pll(intel_crtc);
3898
2dd24552
JB		 3899 i9xx_pfit_enable(intel_crtc);
3900
63cbb074
VS		 3901 intel_crtc_load_lut(crtc);
3902
f37fcc2a 3903 intel_update_watermarks(crtc);
23538ef1 3904 intel_enable_pipe(dev_priv, pipe, false, false);
b24e7179 3905 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3906 intel_enable_planes(crtc);
22e407d7 3907 /* The fixup needs to happen before cursor is enabled */
61bc95c1
EE		 3908 if (IS_G4X(dev))
3909 g4x_fixup_plane(dev_priv, pipe);
22e407d7 3910 intel_crtc_update_cursor(crtc, true);
79e53945 3911
0b8765c6
JB		 3912 /* Give the overlay scaler a chance to enable if it's on this pipe */
3913 intel_crtc_dpms_overlay(intel_crtc, true);
ef9c3aee 3914
f440eb13 3915 intel_update_fbc(dev);
ef9c3aee 3916
fa5c73b1
DV		 3917 for_each_encoder_on_crtc(dev, crtc, encoder)
3918 encoder->enable(encoder);
0b8765c6 3919}
79e53945 3920
87476d63
DV		 3921static void i9xx_pfit_disable(struct intel_crtc *crtc)
3922{
3923 struct drm_device *dev = crtc->base.dev;
3924 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3925
328d8e82
DV		 3926 if (!crtc->config.gmch_pfit.control)
3927 return;
87476d63 3928
328d8e82 3929 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3930
328d8e82
DV		 3931 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3932 I915_READ(PFIT_CONTROL));
3933 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3934}
3935
0b8765c6
JB		 3936static void i9xx_crtc_disable(struct drm_crtc *crtc)
3937{
3938 struct drm_device *dev = crtc->dev;
3939 struct drm_i915_private *dev_priv = dev->dev_private;
3940 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3941 struct intel_encoder *encoder;
0b8765c6
JB		 3942 int pipe = intel_crtc->pipe;
3943 int plane = intel_crtc->plane;
ef9c3aee 3944
f7abfe8b
CW		 3945 if (!intel_crtc->active)
3946 return;
3947
ea9d758d
DV		 3948 for_each_encoder_on_crtc(dev, crtc, encoder)
3949 encoder->disable(encoder);
3950
0b8765c6 3951 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3952 intel_crtc_wait_for_pending_flips(crtc);
3953 drm_vblank_off(dev, pipe);
0b8765c6 3954
5c3fe8b0 3955 if (dev_priv->fbc.plane == plane)
973d04f9 3956 intel_disable_fbc(dev);
79e53945 3957
0d5b8c61
VS		 3958 intel_crtc_dpms_overlay(intel_crtc, false);
3959 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3960 intel_disable_planes(crtc);
b24e7179 3961 intel_disable_plane(dev_priv, plane, pipe);
0d5b8c61 3962
b24e7179 3963 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3964
87476d63 3965 i9xx_pfit_disable(intel_crtc);
24a1f16d 3966
89b667f8
JB		 3967 for_each_encoder_on_crtc(dev, crtc, encoder)
3968 if (encoder->post_disable)
3969 encoder->post_disable(encoder);
3970
f6071166
JB		 3971 if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3972 vlv_disable_pll(dev_priv, pipe);
3973 else if (!IS_VALLEYVIEW(dev))
e9fd1c02 3974 i9xx_disable_pll(dev_priv, pipe);
0b8765c6 3975
f7abfe8b 3976 intel_crtc->active = false;
46ba614c 3977 intel_update_watermarks(crtc);
f37fcc2a 3978
6b383a7f 3979 intel_update_fbc(dev);
0b8765c6
JB		 3980}
3981
ee7b9f93
JB		 3982static void i9xx_crtc_off(struct drm_crtc *crtc)
3983{
3984}
3985
976f8a20
DV		 3986static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3987 bool enabled)
2c07245f
ZW		 3988{
3989 struct drm_device *dev = crtc->dev;
3990 struct drm_i915_master_private *master_priv;
3991 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3992 int pipe = intel_crtc->pipe;
79e53945
JB		 3993
3994 if (!dev->primary->master)
3995 return;
3996
3997 master_priv = dev->primary->master->driver_priv;
3998 if (!master_priv->sarea_priv)
3999 return;
4000
79e53945
JB		 4001 switch (pipe) {
4002 case 0:
4003 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4004 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4005 break;
4006 case 1:
4007 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4008 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4009 break;
4010 default:
9db4a9c7 4011 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 4012 break;
4013 }
79e53945
JB		 4014}
4015
976f8a20
DV		 4016/**
4017 * Sets the power management mode of the pipe and plane.
4018 */
4019void intel_crtc_update_dpms(struct drm_crtc *crtc)
4020{
4021 struct drm_device *dev = crtc->dev;
4022 struct drm_i915_private *dev_priv = dev->dev_private;
4023 struct intel_encoder *intel_encoder;
4024 bool enable = false;
4025
4026 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4027 enable |= intel_encoder->connectors_active;
4028
4029 if (enable)
4030 dev_priv->display.crtc_enable(crtc);
4031 else
4032 dev_priv->display.crtc_disable(crtc);
4033
4034 intel_crtc_update_sarea(crtc, enable);
4035}
4036
cdd59983
CW		 4037static void intel_crtc_disable(struct drm_crtc *crtc)
4038{
cdd59983 4039 struct drm_device *dev = crtc->dev;
976f8a20 4040 struct drm_connector *connector;
ee7b9f93 4041 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 4042 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 4043
976f8a20
DV		 4044 /* crtc should still be enabled when we disable it. */
4045 WARN_ON(!crtc->enabled);
4046
4047 dev_priv->display.crtc_disable(crtc);
c77bf565 4048 intel_crtc->eld_vld = false;
976f8a20 4049 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 4050 dev_priv->display.off(crtc);
4051
931872fc 4052 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
93ce0ba6 4053 assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
931872fc 4054 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 4055
4056 if (crtc->fb) {
4057 mutex_lock(&dev->struct_mutex);
1690e1eb 4058 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 4059 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 4060 crtc->fb = NULL;
4061 }
4062
4063 /* Update computed state. */
4064 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4065 if (!connector->encoder || !connector->encoder->crtc)
4066 continue;
4067
4068 if (connector->encoder->crtc != crtc)
4069 continue;
4070
4071 connector->dpms = DRM_MODE_DPMS_OFF;
4072 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 4073 }
4074}
4075
ea5b213a 4076void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 4077{
4ef69c7a 4078 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 4079
ea5b213a
CW		 4080 drm_encoder_cleanup(encoder);
4081 kfree(intel_encoder);
7e7d76c3
JB		 4082}
4083
9237329d 4084/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 4085 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4086 * state of the entire output pipe. */
9237329d 4087static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 4088{
5ab432ef
DV		 4089 if (mode == DRM_MODE_DPMS_ON) {
4090 encoder->connectors_active = true;
4091
b2cabb0e 4092 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 4093 } else {
4094 encoder->connectors_active = false;
4095
b2cabb0e 4096 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 4097 }
79e53945
JB		 4098}
4099
0a91ca29
DV		 4100/* Cross check the actual hw state with our own modeset state tracking (and it's
4101 * internal consistency). */
b980514c 4102static void intel_connector_check_state(struct intel_connector *connector)
79e53945 4103{
0a91ca29
DV		 4104 if (connector->get_hw_state(connector)) {
4105 struct intel_encoder *encoder = connector->encoder;
4106 struct drm_crtc *crtc;
4107 bool encoder_enabled;
4108 enum pipe pipe;
4109
4110 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4111 connector->base.base.id,
4112 drm_get_connector_name(&connector->base));
4113
4114 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4115 "wrong connector dpms state\n");
4116 WARN(connector->base.encoder != &encoder->base,
4117 "active connector not linked to encoder\n");
4118 WARN(!encoder->connectors_active,
4119 "encoder->connectors_active not set\n");
4120
4121 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4122 WARN(!encoder_enabled, "encoder not enabled\n");
4123 if (WARN_ON(!encoder->base.crtc))
4124 return;
4125
4126 crtc = encoder->base.crtc;
4127
4128 WARN(!crtc->enabled, "crtc not enabled\n");
4129 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4130 WARN(pipe != to_intel_crtc(crtc)->pipe,
4131 "encoder active on the wrong pipe\n");
4132 }
79e53945
JB		 4133}
4134
5ab432ef
DV		 4135/* Even simpler default implementation, if there's really no special case to
4136 * consider. */
4137void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 4138{
5ab432ef 4139 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 4140
5ab432ef
DV		 4141 /* All the simple cases only support two dpms states. */
4142 if (mode != DRM_MODE_DPMS_ON)
4143 mode = DRM_MODE_DPMS_OFF;
d4270e57 4144
5ab432ef
DV		 4145 if (mode == connector->dpms)
4146 return;
4147
4148 connector->dpms = mode;
4149
4150 /* Only need to change hw state when actually enabled */
4151 if (encoder->base.crtc)
4152 intel_encoder_dpms(encoder, mode);
4153 else
8af6cf88 4154 WARN_ON(encoder->connectors_active != false);
0a91ca29 4155
b980514c 4156 intel_modeset_check_state(connector->dev);
79e53945
JB		 4157}
4158
f0947c37
DV		 4159/* Simple connector->get_hw_state implementation for encoders that support only
4160 * one connector and no cloning and hence the encoder state determines the state
4161 * of the connector. */
4162bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 4163{
24929352 4164 enum pipe pipe = 0;
f0947c37 4165 struct intel_encoder *encoder = connector->encoder;
ea5b213a 4166
f0947c37 4167 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 4168}
4169
1857e1da
DV		 4170static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4171 struct intel_crtc_config *pipe_config)
4172{
4173 struct drm_i915_private *dev_priv = dev->dev_private;
4174 struct intel_crtc *pipe_B_crtc =
4175 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4176
4177 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4178 pipe_name(pipe), pipe_config->fdi_lanes);
4179 if (pipe_config->fdi_lanes > 4) {
4180 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4181 pipe_name(pipe), pipe_config->fdi_lanes);
4182 return false;
4183 }
4184
4185 if (IS_HASWELL(dev)) {
4186 if (pipe_config->fdi_lanes > 2) {
4187 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4188 pipe_config->fdi_lanes);
4189 return false;
4190 } else {
4191 return true;
4192 }
4193 }
4194
4195 if (INTEL_INFO(dev)->num_pipes == 2)
4196 return true;
4197
4198 /* Ivybridge 3 pipe is really complicated */
4199 switch (pipe) {
4200 case PIPE_A:
4201 return true;
4202 case PIPE_B:
4203 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4204 pipe_config->fdi_lanes > 2) {
4205 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4206 pipe_name(pipe), pipe_config->fdi_lanes);
4207 return false;
4208 }
4209 return true;
4210 case PIPE_C:
1e833f40 4211 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 4212 pipe_B_crtc->config.fdi_lanes <= 2) {
4213 if (pipe_config->fdi_lanes > 2) {
4214 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4215 pipe_name(pipe), pipe_config->fdi_lanes);
4216 return false;
4217 }
4218 } else {
4219 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4220 return false;
4221 }
4222 return true;
4223 default:
4224 BUG();
4225 }
4226}
4227
e29c22c0
DV		 4228#define RETRY 1
4229static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4230 struct intel_crtc_config *pipe_config)
877d48d5 4231{
1857e1da 4232 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 4233 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 4234 int lane, link_bw, fdi_dotclock;
e29c22c0 4235 bool setup_ok, needs_recompute = false;
877d48d5 4236
e29c22c0 4237retry:
877d48d5
DV		 4238 /* FDI is a binary signal running at ~2.7GHz, encoding
4239 * each output octet as 10 bits. The actual frequency
4240 * is stored as a divider into a 100MHz clock, and the
4241 * mode pixel clock is stored in units of 1KHz.
4242 * Hence the bw of each lane in terms of the mode signal
4243 * is:
4244 */
4245 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4246
241bfc38 4247 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 4248
2bd89a07 4249 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 4250 pipe_config->pipe_bpp);
4251
4252 pipe_config->fdi_lanes = lane;
4253
2bd89a07 4254 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4255 link_bw, &pipe_config->fdi_m_n);
1857e1da 4256
e29c22c0
DV		 4257 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4258 intel_crtc->pipe, pipe_config);
4259 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4260 pipe_config->pipe_bpp -= 2*3;
4261 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4262 pipe_config->pipe_bpp);
4263 needs_recompute = true;
4264 pipe_config->bw_constrained = true;
4265
4266 goto retry;
4267 }
4268
4269 if (needs_recompute)
4270 return RETRY;
4271
4272 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4273}
4274
42db64ef
PZ		 4275static void hsw_compute_ips_config(struct intel_crtc *crtc,
4276 struct intel_crtc_config *pipe_config)
4277{
3c4ca58c
PZ		 4278 pipe_config->ips_enabled = i915_enable_ips &&
4279 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 4280 pipe_config->pipe_bpp <= 24;
42db64ef
PZ		 4281}
4282
a43f6e0f 4283static int intel_crtc_compute_config(struct intel_crtc *crtc,
e29c22c0 4284 struct intel_crtc_config *pipe_config)
79e53945 4285{
a43f6e0f 4286 struct drm_device *dev = crtc->base.dev;
b8cecdf5 4287 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4288
ad3a4479 4289 /* FIXME should check pixel clock limits on all platforms */
cf532bb2
VS		 4290 if (INTEL_INFO(dev)->gen < 4) {
4291 struct drm_i915_private *dev_priv = dev->dev_private;
4292 int clock_limit =
4293 dev_priv->display.get_display_clock_speed(dev);
4294
4295 /*
4296 * Enable pixel doubling when the dot clock
4297 * is > 90% of the (display) core speed.
4298 *
b397c96b
VS		 4299 * GDG double wide on either pipe,
4300 * otherwise pipe A only.
cf532bb2 4301 */
b397c96b 4302 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 4303 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 4304 clock_limit *= 2;
cf532bb2 4305 pipe_config->double_wide = true;
ad3a4479
VS		 4306 }
4307
241bfc38 4308 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 4309 return -EINVAL;
2c07245f 4310 }
89749350 4311
1d1d0e27
VS		 4312 /*
4313 * Pipe horizontal size must be even in:
4314 * - DVO ganged mode
4315 * - LVDS dual channel mode
4316 * - Double wide pipe
4317 */
4318 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4319 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4320 pipe_config->pipe_src_w &= ~1;
4321
8693a824
DL		 4322 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4323 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4324 */
4325 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4326 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4327 return -EINVAL;
44f46b42 4328
bd080ee5 4329 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4330 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4331 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4332 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4333 * for lvds. */
4334 pipe_config->pipe_bpp = 8*3;
4335 }
4336
f5adf94e 4337 if (HAS_IPS(dev))
a43f6e0f
DV		 4338 hsw_compute_ips_config(crtc, pipe_config);
4339
4340 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4341 * clock survives for now. */
4342 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4343 pipe_config->shared_dpll = crtc->config.shared_dpll;
42db64ef 4344
877d48d5 4345 if (pipe_config->has_pch_encoder)
a43f6e0f 4346 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 4347
e29c22c0 4348 return 0;
79e53945
JB		 4349}
4350
25eb05fc
JB		 4351static int valleyview_get_display_clock_speed(struct drm_device *dev)
4352{
4353 return 400000; /* FIXME */
4354}
4355
e70236a8
JB		 4356static int i945_get_display_clock_speed(struct drm_device *dev)
4357{
4358 return 400000;
4359}
79e53945 4360
e70236a8 4361static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4362{
e70236a8
JB		 4363 return 333000;
4364}
79e53945 4365
e70236a8
JB		 4366static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4367{
4368 return 200000;
4369}
79e53945 4370
257a7ffc
DV		 4371static int pnv_get_display_clock_speed(struct drm_device *dev)
4372{
4373 u16 gcfgc = 0;
4374
4375 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4376
4377 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4378 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4379 return 267000;
4380 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4381 return 333000;
4382 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4383 return 444000;
4384 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4385 return 200000;
4386 default:
4387 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4388 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4389 return 133000;
4390 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4391 return 167000;
4392 }
4393}
4394
e70236a8
JB		 4395static int i915gm_get_display_clock_speed(struct drm_device *dev)
4396{
4397 u16 gcfgc = 0;
79e53945 4398
e70236a8
JB		 4399 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4400
4401 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4402 return 133000;
4403 else {
4404 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4405 case GC_DISPLAY_CLOCK_333_MHZ:
4406 return 333000;
4407 default:
4408 case GC_DISPLAY_CLOCK_190_200_MHZ:
4409 return 190000;
79e53945 4410 }
e70236a8
JB		 4411 }
4412}
4413
4414static int i865_get_display_clock_speed(struct drm_device *dev)
4415{
4416 return 266000;
4417}
4418
4419static int i855_get_display_clock_speed(struct drm_device *dev)
4420{
4421 u16 hpllcc = 0;
4422 /* Assume that the hardware is in the high speed state. This
4423 * should be the default.
4424 */
4425 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4426 case GC_CLOCK_133_200:
4427 case GC_CLOCK_100_200:
4428 return 200000;
4429 case GC_CLOCK_166_250:
4430 return 250000;
4431 case GC_CLOCK_100_133:
79e53945 4432 return 133000;
e70236a8 4433 }
79e53945 4434
e70236a8
JB		 4435 /* Shouldn't happen */
4436 return 0;
4437}
79e53945 4438
e70236a8
JB		 4439static int i830_get_display_clock_speed(struct drm_device *dev)
4440{
4441 return 133000;
79e53945
JB		 4442}
4443
2c07245f 4444static void
a65851af 4445intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4446{
a65851af
VS		 4447 while (*num > DATA_LINK_M_N_MASK ||
4448 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4449 *num >>= 1;
4450 *den >>= 1;
4451 }
4452}
4453
a65851af
VS		 4454static void compute_m_n(unsigned int m, unsigned int n,
4455 uint32_t *ret_m, uint32_t *ret_n)
4456{
4457 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4458 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4459 intel_reduce_m_n_ratio(ret_m, ret_n);
4460}
4461
e69d0bc1
DV		 4462void
4463intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4464 int pixel_clock, int link_clock,
4465 struct intel_link_m_n *m_n)
2c07245f 4466{
e69d0bc1 4467 m_n->tu = 64;
a65851af
VS		 4468
4469 compute_m_n(bits_per_pixel * pixel_clock,
4470 link_clock * nlanes * 8,
4471 &m_n->gmch_m, &m_n->gmch_n);
4472
4473 compute_m_n(pixel_clock, link_clock,
4474 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4475}
4476
a7615030
CW		 4477static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4478{
72bbe58c
KP		 4479 if (i915_panel_use_ssc >= 0)
4480 return i915_panel_use_ssc != 0;
41aa3448 4481 return dev_priv->vbt.lvds_use_ssc
435793df 4482 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4483}
4484
c65d77d8
JB		 4485static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4486{
4487 struct drm_device *dev = crtc->dev;
4488 struct drm_i915_private *dev_priv = dev->dev_private;
4489 int refclk;
4490
a0c4da24 4491 if (IS_VALLEYVIEW(dev)) {
9a0ea498 4492 refclk = 100000;
a0c4da24 4493 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4494 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4495 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4496 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4497 refclk / 1000);
4498 } else if (!IS_GEN2(dev)) {
4499 refclk = 96000;
4500 } else {
4501 refclk = 48000;
4502 }
4503
4504 return refclk;
4505}
4506
7429e9d4 4507static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 4508{
7df00d7a 4509 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 4510}
f47709a9 4511
7429e9d4
DV		 4512static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4513{
4514 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 4515}
4516
f47709a9 4517static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4518 intel_clock_t *reduced_clock)
4519{
f47709a9 4520 struct drm_device *dev = crtc->base.dev;
a7516a05 4521 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4522 int pipe = crtc->pipe;
a7516a05
JB		 4523 u32 fp, fp2 = 0;
4524
4525 if (IS_PINEVIEW(dev)) {
7429e9d4 4526 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4527 if (reduced_clock)
7429e9d4 4528 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4529 } else {
7429e9d4 4530 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4531 if (reduced_clock)
7429e9d4 4532 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4533 }
4534
4535 I915_WRITE(FP0(pipe), fp);
8bcc2795 4536 crtc->config.dpll_hw_state.fp0 = fp;
a7516a05 4537
f47709a9
DV		 4538 crtc->lowfreq_avail = false;
4539 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4540 reduced_clock && i915_powersave) {
4541 I915_WRITE(FP1(pipe), fp2);
8bcc2795 4542 crtc->config.dpll_hw_state.fp1 = fp2;
f47709a9 4543 crtc->lowfreq_avail = true;
a7516a05
JB		 4544 } else {
4545 I915_WRITE(FP1(pipe), fp);
8bcc2795 4546 crtc->config.dpll_hw_state.fp1 = fp;
a7516a05
JB		 4547 }
4548}
4549
5e69f97f
CML		 4550static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4551 pipe)
89b667f8
JB		 4552{
4553 u32 reg_val;
4554
4555 /*
4556 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4557 * and set it to a reasonable value instead.
4558 */
5e69f97f 4559 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
89b667f8
JB		 4560 reg_val &= 0xffffff00;
4561 reg_val |= 0x00000030;
5e69f97f 4562 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
89b667f8 4563
5e69f97f 4564 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
89b667f8
JB		 4565 reg_val &= 0x8cffffff;
4566 reg_val = 0x8c000000;
5e69f97f 4567 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
89b667f8 4568
5e69f97f 4569 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
89b667f8 4570 reg_val &= 0xffffff00;
5e69f97f 4571 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
89b667f8 4572
5e69f97f 4573 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
89b667f8
JB		 4574 reg_val &= 0x00ffffff;
4575 reg_val |= 0xb0000000;
5e69f97f 4576 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4577}
4578
b551842d
DV		 4579static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4580 struct intel_link_m_n *m_n)
4581{
4582 struct drm_device *dev = crtc->base.dev;
4583 struct drm_i915_private *dev_priv = dev->dev_private;
4584 int pipe = crtc->pipe;
4585
e3b95f1e
DV		 4586 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4587 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4588 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4589 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4590}
4591
4592static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4593 struct intel_link_m_n *m_n)
4594{
4595 struct drm_device *dev = crtc->base.dev;
4596 struct drm_i915_private *dev_priv = dev->dev_private;
4597 int pipe = crtc->pipe;
4598 enum transcoder transcoder = crtc->config.cpu_transcoder;
4599
4600 if (INTEL_INFO(dev)->gen >= 5) {
4601 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4602 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4603 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4604 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4605 } else {
e3b95f1e
DV		 4606 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4607 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4608 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4609 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4610 }
4611}
4612
03afc4a2
DV		 4613static void intel_dp_set_m_n(struct intel_crtc *crtc)
4614{
4615 if (crtc->config.has_pch_encoder)
4616 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4617 else
4618 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4619}
4620
f47709a9 4621static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4622{
f47709a9 4623 struct drm_device *dev = crtc->base.dev;
a0c4da24 4624 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4625 int pipe = crtc->pipe;
89b667f8 4626 u32 dpll, mdiv;
a0c4da24 4627 u32 bestn, bestm1, bestm2, bestp1, bestp2;
198a037f 4628 u32 coreclk, reg_val, dpll_md;
a0c4da24 4629
09153000
DV		 4630 mutex_lock(&dev_priv->dpio_lock);
4631
f47709a9
DV		 4632 bestn = crtc->config.dpll.n;
4633 bestm1 = crtc->config.dpll.m1;
4634 bestm2 = crtc->config.dpll.m2;
4635 bestp1 = crtc->config.dpll.p1;
4636 bestp2 = crtc->config.dpll.p2;
a0c4da24 4637
89b667f8
JB		 4638 /* See eDP HDMI DPIO driver vbios notes doc */
4639
4640 /* PLL B needs special handling */
4641 if (pipe)
5e69f97f 4642 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 4643
4644 /* Set up Tx target for periodic Rcomp update */
5e69f97f 4645 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4646
4647 /* Disable target IRef on PLL */
5e69f97f 4648 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe));
89b667f8 4649 reg_val &= 0x00ffffff;
5e69f97f 4650 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4651
4652 /* Disable fast lock */
5e69f97f 4653 vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4654
4655 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4656 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4657 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4658 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4659 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4660
4661 /*
4662 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4663 * but we don't support that).
4664 * Note: don't use the DAC post divider as it seems unstable.
4665 */
4666 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5e69f97f 4667 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
a0c4da24 4668
a0c4da24 4669 mdiv |= DPIO_ENABLE_CALIBRATION;
5e69f97f 4670 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
a0c4da24 4671
89b667f8 4672 /* Set HBR and RBR LPF coefficients */
ff9a6750 4673 if (crtc->config.port_clock == 162000 ||
99750bd4 4674 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
89b667f8 4675 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5e69f97f 4676 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
885b0120 4677 0x009f0003);
89b667f8 4678 else
5e69f97f 4679 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
89b667f8
JB		 4680 0x00d0000f);
4681
4682 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4683 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4684 /* Use SSC source */
4685 if (!pipe)
5e69f97f 4686 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4687 0x0df40000);
4688 else
5e69f97f 4689 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4690 0x0df70000);
4691 } else { /* HDMI or VGA */
4692 /* Use bend source */
4693 if (!pipe)
5e69f97f 4694 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4695 0x0df70000);
4696 else
5e69f97f 4697 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4698 0x0df40000);
4699 }
a0c4da24 4700
5e69f97f 4701 coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4702 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4703 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4704 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4705 coreclk |= 0x01000000;
5e69f97f 4706 vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4707
5e69f97f 4708 vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4709
89b667f8
JB		 4710 /* Enable DPIO clock input */
4711 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4712 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
f6071166
JB		 4713 /* We should never disable this, set it here for state tracking */
4714 if (pipe == PIPE_B)
89b667f8 4715 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
a0c4da24 4716 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4717 crtc->config.dpll_hw_state.dpll = dpll;
4718
ef1b460d
DV		 4719 dpll_md = (crtc->config.pixel_multiplier - 1)
4720 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795
DV		 4721 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4722
89b667f8
JB		 4723 if (crtc->config.has_dp_encoder)
4724 intel_dp_set_m_n(crtc);
09153000
DV		 4725
4726 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4727}
4728
f47709a9
DV		 4729static void i9xx_update_pll(struct intel_crtc *crtc,
4730 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4731 int num_connectors)
4732{
f47709a9 4733 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4734 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 4735 u32 dpll;
4736 bool is_sdvo;
f47709a9 4737 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4738
f47709a9 4739 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4740
f47709a9
DV		 4741 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4742 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4743
4744 dpll = DPLL_VGA_MODE_DIS;
4745
f47709a9 4746 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4747 dpll |= DPLLB_MODE_LVDS;
4748 else
4749 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4750
ef1b460d 4751 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
198a037f
DV		 4752 dpll |= (crtc->config.pixel_multiplier - 1)
4753 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4754 }
198a037f
DV		 4755
4756 if (is_sdvo)
4a33e48d 4757 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 4758
f47709a9 4759 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4a33e48d 4760 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 4761
4762 /* compute bitmask from p1 value */
4763 if (IS_PINEVIEW(dev))
4764 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4765 else {
4766 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4767 if (IS_G4X(dev) && reduced_clock)
4768 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4769 }
4770 switch (clock->p2) {
4771 case 5:
4772 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4773 break;
4774 case 7:
4775 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4776 break;
4777 case 10:
4778 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4779 break;
4780 case 14:
4781 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4782 break;
4783 }
4784 if (INTEL_INFO(dev)->gen >= 4)
4785 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4786
09ede541 4787 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4788 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4789 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4790 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4791 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4792 else
4793 dpll |= PLL_REF_INPUT_DREFCLK;
4794
4795 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4796 crtc->config.dpll_hw_state.dpll = dpll;
4797
eb1cbe48 4798 if (INTEL_INFO(dev)->gen >= 4) {
ef1b460d
DV		 4799 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4800 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795 4801 crtc->config.dpll_hw_state.dpll_md = dpll_md;
eb1cbe48 4802 }
66e3d5c0
DV		 4803
4804 if (crtc->config.has_dp_encoder)
4805 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4806}
4807
f47709a9 4808static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 4809 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4810 int num_connectors)
4811{
f47709a9 4812 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4813 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 4814 u32 dpll;
f47709a9 4815 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4816
f47709a9 4817 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4818
eb1cbe48
DV		 4819 dpll = DPLL_VGA_MODE_DIS;
4820
f47709a9 4821 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4822 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4823 } else {
4824 if (clock->p1 == 2)
4825 dpll |= PLL_P1_DIVIDE_BY_TWO;
4826 else
4827 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4828 if (clock->p2 == 4)
4829 dpll |= PLL_P2_DIVIDE_BY_4;
4830 }
4831
4a33e48d
DV		 4832 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4833 dpll |= DPLL_DVO_2X_MODE;
4834
f47709a9 4835 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4836 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4837 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4838 else
4839 dpll |= PLL_REF_INPUT_DREFCLK;
4840
4841 dpll |= DPLL_VCO_ENABLE;
8bcc2795 4842 crtc->config.dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 4843}
4844
8a654f3b 4845static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 4846{
4847 struct drm_device *dev = intel_crtc->base.dev;
4848 struct drm_i915_private *dev_priv = dev->dev_private;
4849 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4850 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV		 4851 struct drm_display_mode *adjusted_mode =
4852 &intel_crtc->config.adjusted_mode;
4d8a62ea
DV		 4853 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4854
4855 /* We need to be careful not to changed the adjusted mode, for otherwise
4856 * the hw state checker will get angry at the mismatch. */
4857 crtc_vtotal = adjusted_mode->crtc_vtotal;
4858 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4859
4860 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4861 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4862 crtc_vtotal -= 1;
4863 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4864 vsyncshift = adjusted_mode->crtc_hsync_start
4865 - adjusted_mode->crtc_htotal / 2;
4866 } else {
4867 vsyncshift = 0;
4868 }
4869
4870 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4871 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4872
fe2b8f9d 4873 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4874 (adjusted_mode->crtc_hdisplay - 1) |
4875 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4876 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4877 (adjusted_mode->crtc_hblank_start - 1) |
4878 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4879 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4880 (adjusted_mode->crtc_hsync_start - 1) |
4881 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4882
fe2b8f9d 4883 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4884 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4885 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4886 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4887 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4888 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4889 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4890 (adjusted_mode->crtc_vsync_start - 1) |
4891 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4892
b5e508d4
PZ		 4893 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4894 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4895 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4896 * bits. */
4897 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4898 (pipe == PIPE_B || pipe == PIPE_C))
4899 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4900
b0e77b9c
PZ		 4901 /* pipesrc controls the size that is scaled from, which should
4902 * always be the user's requested size.
4903 */
4904 I915_WRITE(PIPESRC(pipe),
37327abd
VS		 4905 ((intel_crtc->config.pipe_src_w - 1) << 16) |
4906 (intel_crtc->config.pipe_src_h - 1));
b0e77b9c
PZ		 4907}
4908
1bd1bd80
DV		 4909static void intel_get_pipe_timings(struct intel_crtc *crtc,
4910 struct intel_crtc_config *pipe_config)
4911{
4912 struct drm_device *dev = crtc->base.dev;
4913 struct drm_i915_private *dev_priv = dev->dev_private;
4914 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4915 uint32_t tmp;
4916
4917 tmp = I915_READ(HTOTAL(cpu_transcoder));
4918 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4919 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4920 tmp = I915_READ(HBLANK(cpu_transcoder));
4921 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4922 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4923 tmp = I915_READ(HSYNC(cpu_transcoder));
4924 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4925 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4926
4927 tmp = I915_READ(VTOTAL(cpu_transcoder));
4928 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4929 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4930 tmp = I915_READ(VBLANK(cpu_transcoder));
4931 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4932 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4933 tmp = I915_READ(VSYNC(cpu_transcoder));
4934 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4935 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4936
4937 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4938 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4939 pipe_config->adjusted_mode.crtc_vtotal += 1;
4940 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4941 }
4942
4943 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 4944 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
4945 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
4946
4947 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
4948 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 4949}
4950
babea61d
JB		 4951static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4952 struct intel_crtc_config *pipe_config)
4953{
4954 struct drm_crtc *crtc = &intel_crtc->base;
4955
4956 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4957 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4958 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4959 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4960
4961 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4962 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4963 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4964 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4965
4966 crtc->mode.flags = pipe_config->adjusted_mode.flags;
4967
241bfc38 4968 crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock;
babea61d
JB		 4969 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4970}
4971
84b046f3
DV		 4972static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4973{
4974 struct drm_device *dev = intel_crtc->base.dev;
4975 struct drm_i915_private *dev_priv = dev->dev_private;
4976 uint32_t pipeconf;
4977
9f11a9e4 4978 pipeconf = 0;
84b046f3 4979
67c72a12
DV		 4980 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
4981 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
4982 pipeconf |= PIPECONF_ENABLE;
4983
cf532bb2
VS		 4984 if (intel_crtc->config.double_wide)
4985 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 4986
ff9ce46e
DV		 4987 /* only g4x and later have fancy bpc/dither controls */
4988 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e
DV		 4989 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4990 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4991 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4992 PIPECONF_DITHER_TYPE_SP;
84b046f3 4993
ff9ce46e
DV		 4994 switch (intel_crtc->config.pipe_bpp) {
4995 case 18:
4996 pipeconf |= PIPECONF_6BPC;
4997 break;
4998 case 24:
4999 pipeconf |= PIPECONF_8BPC;
5000 break;
5001 case 30:
5002 pipeconf |= PIPECONF_10BPC;
5003 break;
5004 default:
5005 /* Case prevented by intel_choose_pipe_bpp_dither. */
5006 BUG();
84b046f3
DV		 5007 }
5008 }
5009
5010 if (HAS_PIPE_CXSR(dev)) {
5011 if (intel_crtc->lowfreq_avail) {
5012 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5013 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5014 } else {
5015 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 5016 }
5017 }
5018
84b046f3
DV		 5019 if (!IS_GEN2(dev) &&
5020 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5021 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5022 else
5023 pipeconf |= PIPECONF_PROGRESSIVE;
5024
9f11a9e4
DV		 5025 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5026 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 5027
84b046f3
DV		 5028 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5029 POSTING_READ(PIPECONF(intel_crtc->pipe));
5030}
5031
f564048e 5032static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 5033 int x, int y,
94352cf9 5034 struct drm_framebuffer *fb)
79e53945
JB		 5035{
5036 struct drm_device *dev = crtc->dev;
5037 struct drm_i915_private *dev_priv = dev->dev_private;
5038 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5039 int pipe = intel_crtc->pipe;
80824003 5040 int plane = intel_crtc->plane;
c751ce4f 5041 int refclk, num_connectors = 0;
652c393a 5042 intel_clock_t clock, reduced_clock;
84b046f3 5043 u32 dspcntr;
a16af721 5044 bool ok, has_reduced_clock = false;
e9fd1c02 5045 bool is_lvds = false, is_dsi = false;
5eddb70b 5046 struct intel_encoder *encoder;
d4906093 5047 const intel_limit_t *limit;
5c3b82e2 5048 int ret;
79e53945 5049
6c2b7c12 5050 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 5051 switch (encoder->type) {
79e53945
JB		 5052 case INTEL_OUTPUT_LVDS:
5053 is_lvds = true;
5054 break;
e9fd1c02
JN		 5055 case INTEL_OUTPUT_DSI:
5056 is_dsi = true;
5057 break;
79e53945 5058 }
43565a06 5059
c751ce4f 5060 num_connectors++;
79e53945
JB		 5061 }
5062
f2335330
JN		 5063 if (is_dsi)
5064 goto skip_dpll;
5065
5066 if (!intel_crtc->config.clock_set) {
5067 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 5068
e9fd1c02
JN		 5069 /*
5070 * Returns a set of divisors for the desired target clock with
5071 * the given refclk, or FALSE. The returned values represent
5072 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5073 * 2) / p1 / p2.
5074 */
5075 limit = intel_limit(crtc, refclk);
5076 ok = dev_priv->display.find_dpll(limit, crtc,
5077 intel_crtc->config.port_clock,
5078 refclk, NULL, &clock);
f2335330 5079 if (!ok) {
e9fd1c02
JN		 5080 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5081 return -EINVAL;
5082 }
79e53945 5083
f2335330
JN		 5084 if (is_lvds && dev_priv->lvds_downclock_avail) {
5085 /*
5086 * Ensure we match the reduced clock's P to the target
5087 * clock. If the clocks don't match, we can't switch
5088 * the display clock by using the FP0/FP1. In such case
5089 * we will disable the LVDS downclock feature.
5090 */
5091 has_reduced_clock =
5092 dev_priv->display.find_dpll(limit, crtc,
5093 dev_priv->lvds_downclock,
5094 refclk, &clock,
5095 &reduced_clock);
5096 }
5097 /* Compat-code for transition, will disappear. */
f47709a9
DV		 5098 intel_crtc->config.dpll.n = clock.n;
5099 intel_crtc->config.dpll.m1 = clock.m1;
5100 intel_crtc->config.dpll.m2 = clock.m2;
5101 intel_crtc->config.dpll.p1 = clock.p1;
5102 intel_crtc->config.dpll.p2 = clock.p2;
5103 }
7026d4ac 5104
e9fd1c02 5105 if (IS_GEN2(dev)) {
8a654f3b 5106 i8xx_update_pll(intel_crtc,
2a8f64ca
VP		 5107 has_reduced_clock ? &reduced_clock : NULL,
5108 num_connectors);
e9fd1c02 5109 } else if (IS_VALLEYVIEW(dev)) {
f2335330 5110 vlv_update_pll(intel_crtc);
e9fd1c02 5111 } else {
f47709a9 5112 i9xx_update_pll(intel_crtc,
eb1cbe48 5113 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 5114 num_connectors);
e9fd1c02 5115 }
79e53945 5116
f2335330 5117skip_dpll:
79e53945
JB		 5118 /* Set up the display plane register */
5119 dspcntr = DISPPLANE_GAMMA_ENABLE;
5120
da6ecc5d
JB		 5121 if (!IS_VALLEYVIEW(dev)) {
5122 if (pipe == 0)
5123 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5124 else
5125 dspcntr |= DISPPLANE_SEL_PIPE_B;
5126 }
79e53945 5127
8a654f3b 5128 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW		 5129
5130 /* pipesrc and dspsize control the size that is scaled from,
5131 * which should always be the user's requested size.
79e53945 5132 */
929c77fb 5133 I915_WRITE(DSPSIZE(plane),
37327abd
VS		 5134 ((intel_crtc->config.pipe_src_h - 1) << 16) |
5135 (intel_crtc->config.pipe_src_w - 1));
929c77fb 5136 I915_WRITE(DSPPOS(plane), 0);
2c07245f 5137
84b046f3
DV		 5138 i9xx_set_pipeconf(intel_crtc);
5139
f564048e
EA		 5140 I915_WRITE(DSPCNTR(plane), dspcntr);
5141 POSTING_READ(DSPCNTR(plane));
5142
94352cf9 5143 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e 5144
f564048e
EA		 5145 return ret;
5146}
5147
2fa2fe9a
DV		 5148static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5149 struct intel_crtc_config *pipe_config)
5150{
5151 struct drm_device *dev = crtc->base.dev;
5152 struct drm_i915_private *dev_priv = dev->dev_private;
5153 uint32_t tmp;
5154
5155 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 5156 if (!(tmp & PFIT_ENABLE))
5157 return;
2fa2fe9a 5158
06922821 5159 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 5160 if (INTEL_INFO(dev)->gen < 4) {
5161 if (crtc->pipe != PIPE_B)
5162 return;
2fa2fe9a
DV		 5163 } else {
5164 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5165 return;
5166 }
5167
06922821 5168 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 5169 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5170 if (INTEL_INFO(dev)->gen < 5)
5171 pipe_config->gmch_pfit.lvds_border_bits =
5172 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5173}
5174
acbec814
JB		 5175static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5176 struct intel_crtc_config *pipe_config)
5177{
5178 struct drm_device *dev = crtc->base.dev;
5179 struct drm_i915_private *dev_priv = dev->dev_private;
5180 int pipe = pipe_config->cpu_transcoder;
5181 intel_clock_t clock;
5182 u32 mdiv;
662c6ecb 5183 int refclk = 100000;
acbec814
JB		 5184
5185 mutex_lock(&dev_priv->dpio_lock);
5186 mdiv = vlv_dpio_read(dev_priv, pipe, DPIO_DIV(pipe));
5187 mutex_unlock(&dev_priv->dpio_lock);
5188
5189 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5190 clock.m2 = mdiv & DPIO_M2DIV_MASK;
5191 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5192 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5193 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5194
662c6ecb
CW		 5195 clock.vco = refclk * clock.m1 * clock.m2 / clock.n;
5196 clock.dot = 2 * clock.vco / (clock.p1 * clock.p2);
acbec814
JB		 5197
5198 pipe_config->port_clock = clock.dot / 10;
5199}
5200
0e8ffe1b
DV		 5201static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5202 struct intel_crtc_config *pipe_config)
5203{
5204 struct drm_device *dev = crtc->base.dev;
5205 struct drm_i915_private *dev_priv = dev->dev_private;
5206 uint32_t tmp;
5207
e143a21c 5208 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 5209 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5210
0e8ffe1b
DV		 5211 tmp = I915_READ(PIPECONF(crtc->pipe));
5212 if (!(tmp & PIPECONF_ENABLE))
5213 return false;
5214
42571aef
VS		 5215 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5216 switch (tmp & PIPECONF_BPC_MASK) {
5217 case PIPECONF_6BPC:
5218 pipe_config->pipe_bpp = 18;
5219 break;
5220 case PIPECONF_8BPC:
5221 pipe_config->pipe_bpp = 24;
5222 break;
5223 case PIPECONF_10BPC:
5224 pipe_config->pipe_bpp = 30;
5225 break;
5226 default:
5227 break;
5228 }
5229 }
5230
282740f7
VS		 5231 if (INTEL_INFO(dev)->gen < 4)
5232 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5233
1bd1bd80
DV		 5234 intel_get_pipe_timings(crtc, pipe_config);
5235
2fa2fe9a
DV		 5236 i9xx_get_pfit_config(crtc, pipe_config);
5237
6c49f241
DV		 5238 if (INTEL_INFO(dev)->gen >= 4) {
5239 tmp = I915_READ(DPLL_MD(crtc->pipe));
5240 pipe_config->pixel_multiplier =
5241 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5242 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 5243 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 5244 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5245 tmp = I915_READ(DPLL(crtc->pipe));
5246 pipe_config->pixel_multiplier =
5247 ((tmp & SDVO_MULTIPLIER_MASK)
5248 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5249 } else {
5250 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5251 * port and will be fixed up in the encoder->get_config
5252 * function. */
5253 pipe_config->pixel_multiplier = 1;
5254 }
8bcc2795
DV		 5255 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5256 if (!IS_VALLEYVIEW(dev)) {
5257 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5258 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 5259 } else {
5260 /* Mask out read-only status bits. */
5261 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5262 DPLL_PORTC_READY_MASK |
5263 DPLL_PORTB_READY_MASK);
8bcc2795 5264 }
6c49f241 5265
acbec814
JB		 5266 if (IS_VALLEYVIEW(dev))
5267 vlv_crtc_clock_get(crtc, pipe_config);
5268 else
5269 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 5270
0e8ffe1b
DV		 5271 return true;
5272}
5273
dde86e2d 5274static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5275{
5276 struct drm_i915_private *dev_priv = dev->dev_private;
5277 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5278 struct intel_encoder *encoder;
74cfd7ac 5279 u32 val, final;
13d83a67 5280 bool has_lvds = false;
199e5d79 5281 bool has_cpu_edp = false;
199e5d79 5282 bool has_panel = false;
99eb6a01
KP		 5283 bool has_ck505 = false;
5284 bool can_ssc = false;
13d83a67
JB		 5285
5286 /* We need to take the global config into account */
199e5d79
KP		 5287 list_for_each_entry(encoder, &mode_config->encoder_list,
5288 base.head) {
5289 switch (encoder->type) {
5290 case INTEL_OUTPUT_LVDS:
5291 has_panel = true;
5292 has_lvds = true;
5293 break;
5294 case INTEL_OUTPUT_EDP:
5295 has_panel = true;
2de6905f 5296 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5297 has_cpu_edp = true;
5298 break;
13d83a67
JB		 5299 }
5300 }
5301
99eb6a01 5302 if (HAS_PCH_IBX(dev)) {
41aa3448 5303 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5304 can_ssc = has_ck505;
5305 } else {
5306 has_ck505 = false;
5307 can_ssc = true;
5308 }
5309
2de6905f
ID		 5310 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5311 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5312
5313 /* Ironlake: try to setup display ref clock before DPLL
5314 * enabling. This is only under driver's control after
5315 * PCH B stepping, previous chipset stepping should be
5316 * ignoring this setting.
5317 */
74cfd7ac
CW		 5318 val = I915_READ(PCH_DREF_CONTROL);
5319
5320 /* As we must carefully and slowly disable/enable each source in turn,
5321 * compute the final state we want first and check if we need to
5322 * make any changes at all.
5323 */
5324 final = val;
5325 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5326 if (has_ck505)
5327 final |= DREF_NONSPREAD_CK505_ENABLE;
5328 else
5329 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5330
5331 final &= ~DREF_SSC_SOURCE_MASK;
5332 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5333 final &= ~DREF_SSC1_ENABLE;
5334
5335 if (has_panel) {
5336 final |= DREF_SSC_SOURCE_ENABLE;
5337
5338 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5339 final |= DREF_SSC1_ENABLE;
5340
5341 if (has_cpu_edp) {
5342 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5343 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5344 else
5345 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5346 } else
5347 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5348 } else {
5349 final |= DREF_SSC_SOURCE_DISABLE;
5350 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5351 }
5352
5353 if (final == val)
5354 return;
5355
13d83a67 5356 /* Always enable nonspread source */
74cfd7ac 5357 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5358
99eb6a01 5359 if (has_ck505)
74cfd7ac 5360 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5361 else
74cfd7ac 5362 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5363
199e5d79 5364 if (has_panel) {
74cfd7ac
CW		 5365 val &= ~DREF_SSC_SOURCE_MASK;
5366 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5367
199e5d79 5368 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5369 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5370 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5371 val |= DREF_SSC1_ENABLE;
e77166b5 5372 } else
74cfd7ac 5373 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5374
5375 /* Get SSC going before enabling the outputs */
74cfd7ac 5376 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5377 POSTING_READ(PCH_DREF_CONTROL);
5378 udelay(200);
5379
74cfd7ac 5380 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5381
5382 /* Enable CPU source on CPU attached eDP */
199e5d79 5383 if (has_cpu_edp) {
99eb6a01 5384 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5385 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5386 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5387 }
13d83a67 5388 else
74cfd7ac 5389 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5390 } else
74cfd7ac 5391 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5392
74cfd7ac 5393 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5394 POSTING_READ(PCH_DREF_CONTROL);
5395 udelay(200);
5396 } else {
5397 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5398
74cfd7ac 5399 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5400
5401 /* Turn off CPU output */
74cfd7ac 5402 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5403
74cfd7ac 5404 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5405 POSTING_READ(PCH_DREF_CONTROL);
5406 udelay(200);
5407
5408 /* Turn off the SSC source */
74cfd7ac
CW		 5409 val &= ~DREF_SSC_SOURCE_MASK;
5410 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5411
5412 /* Turn off SSC1 */
74cfd7ac 5413 val &= ~DREF_SSC1_ENABLE;
199e5d79 5414
74cfd7ac 5415 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5416 POSTING_READ(PCH_DREF_CONTROL);
5417 udelay(200);
5418 }
74cfd7ac
CW		 5419
5420 BUG_ON(val != final);
13d83a67
JB		 5421}
5422
f31f2d55 5423static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 5424{
f31f2d55 5425 uint32_t tmp;
dde86e2d 5426
0ff066a9
PZ		 5427 tmp = I915_READ(SOUTH_CHICKEN2);
5428 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5429 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5430
0ff066a9
PZ		 5431 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5432 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5433 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 5434
0ff066a9
PZ		 5435 tmp = I915_READ(SOUTH_CHICKEN2);
5436 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5437 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5438
0ff066a9
PZ		 5439 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5440 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5441 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 5442}
5443
5444/* WaMPhyProgramming:hsw */
5445static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5446{
5447 uint32_t tmp;
dde86e2d
PZ		 5448
5449 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5450 tmp &= ~(0xFF << 24);
5451 tmp |= (0x12 << 24);
5452 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5453
dde86e2d
PZ		 5454 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5455 tmp |= (1 << 11);
5456 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5457
5458 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5459 tmp |= (1 << 11);
5460 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5461
dde86e2d
PZ		 5462 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5463 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5464 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5465
5466 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5467 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5468 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5469
0ff066a9
PZ		 5470 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5471 tmp &= ~(7 << 13);
5472 tmp |= (5 << 13);
5473 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 5474
0ff066a9
PZ		 5475 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5476 tmp &= ~(7 << 13);
5477 tmp |= (5 << 13);
5478 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 5479
5480 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5481 tmp &= ~0xFF;
5482 tmp |= 0x1C;
5483 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5484
5485 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5486 tmp &= ~0xFF;
5487 tmp |= 0x1C;
5488 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5489
5490 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5491 tmp &= ~(0xFF << 16);
5492 tmp |= (0x1C << 16);
5493 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5494
5495 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5496 tmp &= ~(0xFF << 16);
5497 tmp |= (0x1C << 16);
5498 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5499
0ff066a9
PZ		 5500 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5501 tmp |= (1 << 27);
5502 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 5503
0ff066a9
PZ		 5504 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5505 tmp |= (1 << 27);
5506 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 5507
0ff066a9
PZ		 5508 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5509 tmp &= ~(0xF << 28);
5510 tmp |= (4 << 28);
5511 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 5512
0ff066a9
PZ		 5513 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5514 tmp &= ~(0xF << 28);
5515 tmp |= (4 << 28);
5516 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 5517}
5518
2fa86a1f
PZ		 5519/* Implements 3 different sequences from BSpec chapter "Display iCLK
5520 * Programming" based on the parameters passed:
5521 * - Sequence to enable CLKOUT_DP
5522 * - Sequence to enable CLKOUT_DP without spread
5523 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5524 */
5525static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5526 bool with_fdi)
f31f2d55
PZ		 5527{
5528 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 5529 uint32_t reg, tmp;
5530
5531 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5532 with_spread = true;
5533 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5534 with_fdi, "LP PCH doesn't have FDI\n"))
5535 with_fdi = false;
f31f2d55
PZ		 5536
5537 mutex_lock(&dev_priv->dpio_lock);
5538
5539 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5540 tmp &= ~SBI_SSCCTL_DISABLE;
5541 tmp |= SBI_SSCCTL_PATHALT;
5542 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5543
5544 udelay(24);
5545
2fa86a1f
PZ		 5546 if (with_spread) {
5547 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5548 tmp &= ~SBI_SSCCTL_PATHALT;
5549 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 5550
2fa86a1f
PZ		 5551 if (with_fdi) {
5552 lpt_reset_fdi_mphy(dev_priv);
5553 lpt_program_fdi_mphy(dev_priv);
5554 }
5555 }
dde86e2d 5556
2fa86a1f
PZ		 5557 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5558 SBI_GEN0 : SBI_DBUFF0;
5559 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5560 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5561 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
DV		 5562
5563 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5564}
5565
47701c3b
PZ		 5566/* Sequence to disable CLKOUT_DP */
5567static void lpt_disable_clkout_dp(struct drm_device *dev)
5568{
5569 struct drm_i915_private *dev_priv = dev->dev_private;
5570 uint32_t reg, tmp;
5571
5572 mutex_lock(&dev_priv->dpio_lock);
5573
5574 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5575 SBI_GEN0 : SBI_DBUFF0;
5576 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5577 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5578 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5579
5580 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5581 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5582 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5583 tmp |= SBI_SSCCTL_PATHALT;
5584 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5585 udelay(32);
5586 }
5587 tmp |= SBI_SSCCTL_DISABLE;
5588 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5589 }
5590
5591 mutex_unlock(&dev_priv->dpio_lock);
5592}
5593
bf8fa3d3
PZ		 5594static void lpt_init_pch_refclk(struct drm_device *dev)
5595{
5596 struct drm_mode_config *mode_config = &dev->mode_config;
5597 struct intel_encoder *encoder;
5598 bool has_vga = false;
5599
5600 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5601 switch (encoder->type) {
5602 case INTEL_OUTPUT_ANALOG:
5603 has_vga = true;
5604 break;
5605 }
5606 }
5607
47701c3b
PZ		 5608 if (has_vga)
5609 lpt_enable_clkout_dp(dev, true, true);
5610 else
5611 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 5612}
5613
dde86e2d
PZ		 5614/*
5615 * Initialize reference clocks when the driver loads
5616 */
5617void intel_init_pch_refclk(struct drm_device *dev)
5618{
5619 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5620 ironlake_init_pch_refclk(dev);
5621 else if (HAS_PCH_LPT(dev))
5622 lpt_init_pch_refclk(dev);
5623}
5624
d9d444cb
JB		 5625static int ironlake_get_refclk(struct drm_crtc *crtc)
5626{
5627 struct drm_device *dev = crtc->dev;
5628 struct drm_i915_private *dev_priv = dev->dev_private;
5629 struct intel_encoder *encoder;
d9d444cb
JB		 5630 int num_connectors = 0;
5631 bool is_lvds = false;
5632
6c2b7c12 5633 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5634 switch (encoder->type) {
5635 case INTEL_OUTPUT_LVDS:
5636 is_lvds = true;
5637 break;
d9d444cb
JB		 5638 }
5639 num_connectors++;
5640 }
5641
5642 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5643 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5644 dev_priv->vbt.lvds_ssc_freq);
5645 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5646 }
5647
5648 return 120000;
5649}
5650
6ff93609 5651static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5652{
c8203565 5653 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5655 int pipe = intel_crtc->pipe;
c8203565
PZ		 5656 uint32_t val;
5657
78114071 5658 val = 0;
c8203565 5659
965e0c48 5660 switch (intel_crtc->config.pipe_bpp) {
c8203565 5661 case 18:
dfd07d72 5662 val |= PIPECONF_6BPC;
c8203565
PZ		 5663 break;
5664 case 24:
dfd07d72 5665 val |= PIPECONF_8BPC;
c8203565
PZ		 5666 break;
5667 case 30:
dfd07d72 5668 val |= PIPECONF_10BPC;
c8203565
PZ		 5669 break;
5670 case 36:
dfd07d72 5671 val |= PIPECONF_12BPC;
c8203565
PZ		 5672 break;
5673 default:
cc769b62
PZ		 5674 /* Case prevented by intel_choose_pipe_bpp_dither. */
5675 BUG();
c8203565
PZ		 5676 }
5677
d8b32247 5678 if (intel_crtc->config.dither)
c8203565
PZ		 5679 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5680
6ff93609 5681 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5682 val |= PIPECONF_INTERLACED_ILK;
5683 else
5684 val |= PIPECONF_PROGRESSIVE;
5685
50f3b016 5686 if (intel_crtc->config.limited_color_range)
3685a8f3 5687 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 5688
c8203565
PZ		 5689 I915_WRITE(PIPECONF(pipe), val);
5690 POSTING_READ(PIPECONF(pipe));
5691}
5692
86d3efce
VS		 5693/*
5694 * Set up the pipe CSC unit.
5695 *
5696 * Currently only full range RGB to limited range RGB conversion
5697 * is supported, but eventually this should handle various
5698 * RGB<->YCbCr scenarios as well.
5699 */
50f3b016 5700static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5701{
5702 struct drm_device *dev = crtc->dev;
5703 struct drm_i915_private *dev_priv = dev->dev_private;
5704 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5705 int pipe = intel_crtc->pipe;
5706 uint16_t coeff = 0x7800; /* 1.0 */
5707
5708 /*
5709 * TODO: Check what kind of values actually come out of the pipe
5710 * with these coeff/postoff values and adjust to get the best
5711 * accuracy. Perhaps we even need to take the bpc value into
5712 * consideration.
5713 */
5714
50f3b016 5715 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5716 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5717
5718 /*
5719 * GY/GU and RY/RU should be the other way around according
5720 * to BSpec, but reality doesn't agree. Just set them up in
5721 * a way that results in the correct picture.
5722 */
5723 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5724 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5725
5726 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5727 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5728
5729 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5730 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5731
5732 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5733 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5734 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5735
5736 if (INTEL_INFO(dev)->gen > 6) {
5737 uint16_t postoff = 0;
5738
50f3b016 5739 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5740 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5741
5742 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5743 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5744 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5745
5746 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5747 } else {
5748 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5749
50f3b016 5750 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5751 mode |= CSC_BLACK_SCREEN_OFFSET;
5752
5753 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5754 }
5755}
5756
6ff93609 5757static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5758{
5759 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5760 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5761 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5762 uint32_t val;
5763
3eff4faa 5764 val = 0;
ee2b0b38 5765
d8b32247 5766 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5767 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5768
6ff93609 5769 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5770 val |= PIPECONF_INTERLACED_ILK;
5771 else
5772 val |= PIPECONF_PROGRESSIVE;
5773
702e7a56
PZ		 5774 I915_WRITE(PIPECONF(cpu_transcoder), val);
5775 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 5776
5777 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5778 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
ee2b0b38
PZ		 5779}
5780
6591c6e4 5781static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ		 5782 intel_clock_t *clock,
5783 bool *has_reduced_clock,
5784 intel_clock_t *reduced_clock)
5785{
5786 struct drm_device *dev = crtc->dev;
5787 struct drm_i915_private *dev_priv = dev->dev_private;
5788 struct intel_encoder *intel_encoder;
5789 int refclk;
d4906093 5790 const intel_limit_t *limit;
a16af721 5791 bool ret, is_lvds = false;
79e53945 5792
6591c6e4
PZ		 5793 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5794 switch (intel_encoder->type) {
79e53945
JB		 5795 case INTEL_OUTPUT_LVDS:
5796 is_lvds = true;
5797 break;
79e53945
JB		 5798 }
5799 }
5800
d9d444cb 5801 refclk = ironlake_get_refclk(crtc);
79e53945 5802
d4906093
ML		 5803 /*
5804 * Returns a set of divisors for the desired target clock with the given
5805 * refclk, or FALSE. The returned values represent the clock equation:
5806 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5807 */
1b894b59 5808 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 5809 ret = dev_priv->display.find_dpll(limit, crtc,
5810 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 5811 refclk, NULL, clock);
6591c6e4
PZ		 5812 if (!ret)
5813 return false;
cda4b7d3 5814
ddc9003c 5815 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5816 /*
5817 * Ensure we match the reduced clock's P to the target clock.
5818 * If the clocks don't match, we can't switch the display clock
5819 * by using the FP0/FP1. In such case we will disable the LVDS
5820 * downclock feature.
5821 */
ee9300bb
DV		 5822 *has_reduced_clock =
5823 dev_priv->display.find_dpll(limit, crtc,
5824 dev_priv->lvds_downclock,
5825 refclk, clock,
5826 reduced_clock);
652c393a 5827 }
61e9653f 5828
6591c6e4
PZ		 5829 return true;
5830}
5831
01a415fd
DV		 5832static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5833{
5834 struct drm_i915_private *dev_priv = dev->dev_private;
5835 uint32_t temp;
5836
5837 temp = I915_READ(SOUTH_CHICKEN1);
5838 if (temp & FDI_BC_BIFURCATION_SELECT)
5839 return;
5840
5841 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5842 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5843
5844 temp |= FDI_BC_BIFURCATION_SELECT;
5845 DRM_DEBUG_KMS("enabling fdi C rx\n");
5846 I915_WRITE(SOUTH_CHICKEN1, temp);
5847 POSTING_READ(SOUTH_CHICKEN1);
5848}
5849
ebfd86fd 5850static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
01a415fd
DV		 5851{
5852 struct drm_device *dev = intel_crtc->base.dev;
5853 struct drm_i915_private *dev_priv = dev->dev_private;
01a415fd
DV		 5854
5855 switch (intel_crtc->pipe) {
5856 case PIPE_A:
ebfd86fd 5857 break;
01a415fd 5858 case PIPE_B:
ebfd86fd 5859 if (intel_crtc->config.fdi_lanes > 2)
01a415fd
DV		 5860 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5861 else
5862 cpt_enable_fdi_bc_bifurcation(dev);
5863
ebfd86fd 5864 break;
01a415fd 5865 case PIPE_C:
01a415fd
DV		 5866 cpt_enable_fdi_bc_bifurcation(dev);
5867
ebfd86fd 5868 break;
01a415fd
DV		 5869 default:
5870 BUG();
5871 }
5872}
5873
d4b1931c
PZ		 5874int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5875{
5876 /*
5877 * Account for spread spectrum to avoid
5878 * oversubscribing the link. Max center spread
5879 * is 2.5%; use 5% for safety's sake.
5880 */
5881 u32 bps = target_clock * bpp * 21 / 20;
5882 return bps / (link_bw * 8) + 1;
5883}
5884
7429e9d4 5885static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 5886{
7429e9d4 5887 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 5888}
5889
de13a2e3 5890static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5891 u32 *fp,
9a7c7890 5892 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5893{
de13a2e3 5894 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5895 struct drm_device *dev = crtc->dev;
5896 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5897 struct intel_encoder *intel_encoder;
5898 uint32_t dpll;
6cc5f341 5899 int factor, num_connectors = 0;
09ede541 5900 bool is_lvds = false, is_sdvo = false;
79e53945 5901
de13a2e3
PZ		 5902 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5903 switch (intel_encoder->type) {
79e53945
JB		 5904 case INTEL_OUTPUT_LVDS:
5905 is_lvds = true;
5906 break;
5907 case INTEL_OUTPUT_SDVO:
7d57382e 5908 case INTEL_OUTPUT_HDMI:
79e53945 5909 is_sdvo = true;
79e53945 5910 break;
79e53945 5911 }
43565a06 5912
c751ce4f 5913 num_connectors++;
79e53945 5914 }
79e53945 5915
c1858123 5916 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5917 factor = 21;
5918 if (is_lvds) {
5919 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5920 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5921 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5922 factor = 25;
09ede541 5923 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5924 factor = 20;
c1858123 5925
7429e9d4 5926 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5927 *fp |= FP_CB_TUNE;
2c07245f 5928
9a7c7890
DV		 5929 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5930 *fp2 |= FP_CB_TUNE;
5931
5eddb70b 5932 dpll = 0;
2c07245f 5933
a07d6787
EA		 5934 if (is_lvds)
5935 dpll |= DPLLB_MODE_LVDS;
5936 else
5937 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 5938
ef1b460d
DV		 5939 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5940 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 5941
5942 if (is_sdvo)
4a33e48d 5943 dpll |= DPLL_SDVO_HIGH_SPEED;
9566e9af 5944 if (intel_crtc->config.has_dp_encoder)
4a33e48d 5945 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 5946
a07d6787 5947 /* compute bitmask from p1 value */
7429e9d4 5948 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5949 /* also FPA1 */
7429e9d4 5950 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5951
7429e9d4 5952 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5953 case 5:
5954 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5955 break;
5956 case 7:
5957 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5958 break;
5959 case 10:
5960 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5961 break;
5962 case 14:
5963 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5964 break;
79e53945
JB		 5965 }
5966
b4c09f3b 5967 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5968 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5969 else
5970 dpll |= PLL_REF_INPUT_DREFCLK;
5971
959e16d6 5972 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 5973}
5974
5975static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5976 int x, int y,
5977 struct drm_framebuffer *fb)
5978{
5979 struct drm_device *dev = crtc->dev;
5980 struct drm_i915_private *dev_priv = dev->dev_private;
5981 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5982 int pipe = intel_crtc->pipe;
5983 int plane = intel_crtc->plane;
5984 int num_connectors = 0;
5985 intel_clock_t clock, reduced_clock;
cbbab5bd 5986 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5987 bool ok, has_reduced_clock = false;
8b47047b 5988 bool is_lvds = false;
de13a2e3 5989 struct intel_encoder *encoder;
e2b78267 5990 struct intel_shared_dpll *pll;
de13a2e3 5991 int ret;
de13a2e3
PZ		 5992
5993 for_each_encoder_on_crtc(dev, crtc, encoder) {
5994 switch (encoder->type) {
5995 case INTEL_OUTPUT_LVDS:
5996 is_lvds = true;
5997 break;
de13a2e3
PZ		 5998 }
5999
6000 num_connectors++;
a07d6787 6001 }
79e53945 6002
5dc5298b
PZ		 6003 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6004 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 6005
ff9a6750 6006 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 6007 &has_reduced_clock, &reduced_clock);
ee9300bb 6008 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 6009 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6010 return -EINVAL;
79e53945 6011 }
f47709a9
DV		 6012 /* Compat-code for transition, will disappear. */
6013 if (!intel_crtc->config.clock_set) {
6014 intel_crtc->config.dpll.n = clock.n;
6015 intel_crtc->config.dpll.m1 = clock.m1;
6016 intel_crtc->config.dpll.m2 = clock.m2;
6017 intel_crtc->config.dpll.p1 = clock.p1;
6018 intel_crtc->config.dpll.p2 = clock.p2;
6019 }
79e53945 6020
5dc5298b 6021 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 6022 if (intel_crtc->config.has_pch_encoder) {
7429e9d4 6023 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 6024 if (has_reduced_clock)
7429e9d4 6025 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 6026
7429e9d4 6027 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 6028 &fp, &reduced_clock,
6029 has_reduced_clock ? &fp2 : NULL);
6030
959e16d6 6031 intel_crtc->config.dpll_hw_state.dpll = dpll;
66e985c0
DV		 6032 intel_crtc->config.dpll_hw_state.fp0 = fp;
6033 if (has_reduced_clock)
6034 intel_crtc->config.dpll_hw_state.fp1 = fp2;
6035 else
6036 intel_crtc->config.dpll_hw_state.fp1 = fp;
6037
b89a1d39 6038 pll = intel_get_shared_dpll(intel_crtc);
ee7b9f93 6039 if (pll == NULL) {
84f44ce7
VS		 6040 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6041 pipe_name(pipe));
4b645f14
JB		 6042 return -EINVAL;
6043 }
ee7b9f93 6044 } else
e72f9fbf 6045 intel_put_shared_dpll(intel_crtc);
79e53945 6046
03afc4a2
DV		 6047 if (intel_crtc->config.has_dp_encoder)
6048 intel_dp_set_m_n(intel_crtc);
79e53945 6049
bcd644e0
DV		 6050 if (is_lvds && has_reduced_clock && i915_powersave)
6051 intel_crtc->lowfreq_avail = true;
6052 else
6053 intel_crtc->lowfreq_avail = false;
e2b78267
DV		 6054
6055 if (intel_crtc->config.has_pch_encoder) {
6056 pll = intel_crtc_to_shared_dpll(intel_crtc);
6057
652c393a
JB		 6058 }
6059
8a654f3b 6060 intel_set_pipe_timings(intel_crtc);
5eddb70b 6061
ca3a0ff8 6062 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 6063 intel_cpu_transcoder_set_m_n(intel_crtc,
6064 &intel_crtc->config.fdi_m_n);
6065 }
2c07245f 6066
ebfd86fd
DV		 6067 if (IS_IVYBRIDGE(dev))
6068 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
79e53945 6069
6ff93609 6070 ironlake_set_pipeconf(crtc);
79e53945 6071
a1f9e77e
PZ		 6072 /* Set up the display plane register */
6073 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 6074 POSTING_READ(DSPCNTR(plane));
79e53945 6075
94352cf9 6076 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd 6077
1857e1da 6078 return ret;
79e53945
JB		 6079}
6080
eb14cb74
VS		 6081static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6082 struct intel_link_m_n *m_n)
6083{
6084 struct drm_device *dev = crtc->base.dev;
6085 struct drm_i915_private *dev_priv = dev->dev_private;
6086 enum pipe pipe = crtc->pipe;
6087
6088 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6089 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6090 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6091 & ~TU_SIZE_MASK;
6092 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6093 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6094 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6095}
6096
6097static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6098 enum transcoder transcoder,
6099 struct intel_link_m_n *m_n)
72419203
DV		 6100{
6101 struct drm_device *dev = crtc->base.dev;
6102 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 6103 enum pipe pipe = crtc->pipe;
72419203 6104
eb14cb74
VS		 6105 if (INTEL_INFO(dev)->gen >= 5) {
6106 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6107 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6108 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6109 & ~TU_SIZE_MASK;
6110 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6111 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6112 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6113 } else {
6114 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6115 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6116 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6117 & ~TU_SIZE_MASK;
6118 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6119 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6120 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6121 }
6122}
6123
6124void intel_dp_get_m_n(struct intel_crtc *crtc,
6125 struct intel_crtc_config *pipe_config)
6126{
6127 if (crtc->config.has_pch_encoder)
6128 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6129 else
6130 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6131 &pipe_config->dp_m_n);
6132}
72419203 6133
eb14cb74
VS		 6134static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6135 struct intel_crtc_config *pipe_config)
6136{
6137 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6138 &pipe_config->fdi_m_n);
72419203
DV		 6139}
6140
2fa2fe9a
DV		 6141static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6142 struct intel_crtc_config *pipe_config)
6143{
6144 struct drm_device *dev = crtc->base.dev;
6145 struct drm_i915_private *dev_priv = dev->dev_private;
6146 uint32_t tmp;
6147
6148 tmp = I915_READ(PF_CTL(crtc->pipe));
6149
6150 if (tmp & PF_ENABLE) {
fd4daa9c 6151 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 6152 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6153 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 6154
6155 /* We currently do not free assignements of panel fitters on
6156 * ivb/hsw (since we don't use the higher upscaling modes which
6157 * differentiates them) so just WARN about this case for now. */
6158 if (IS_GEN7(dev)) {
6159 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6160 PF_PIPE_SEL_IVB(crtc->pipe));
6161 }
2fa2fe9a 6162 }
79e53945
JB		 6163}
6164
0e8ffe1b
DV		 6165static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6166 struct intel_crtc_config *pipe_config)
6167{
6168 struct drm_device *dev = crtc->base.dev;
6169 struct drm_i915_private *dev_priv = dev->dev_private;
6170 uint32_t tmp;
6171
e143a21c 6172 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 6173 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 6174
0e8ffe1b
DV		 6175 tmp = I915_READ(PIPECONF(crtc->pipe));
6176 if (!(tmp & PIPECONF_ENABLE))
6177 return false;
6178
42571aef
VS		 6179 switch (tmp & PIPECONF_BPC_MASK) {
6180 case PIPECONF_6BPC:
6181 pipe_config->pipe_bpp = 18;
6182 break;
6183 case PIPECONF_8BPC:
6184 pipe_config->pipe_bpp = 24;
6185 break;
6186 case PIPECONF_10BPC:
6187 pipe_config->pipe_bpp = 30;
6188 break;
6189 case PIPECONF_12BPC:
6190 pipe_config->pipe_bpp = 36;
6191 break;
6192 default:
6193 break;
6194 }
6195
ab9412ba 6196 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 6197 struct intel_shared_dpll *pll;
6198
88adfff1
DV		 6199 pipe_config->has_pch_encoder = true;
6200
627eb5a3
DV		 6201 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6202 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6203 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6204
6205 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 6206
c0d43d62 6207 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 6208 pipe_config->shared_dpll =
6209 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 6210 } else {
6211 tmp = I915_READ(PCH_DPLL_SEL);
6212 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6213 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6214 else
6215 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6216 }
66e985c0
DV		 6217
6218 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6219
6220 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6221 &pipe_config->dpll_hw_state));
c93f54cf
DV		 6222
6223 tmp = pipe_config->dpll_hw_state.dpll;
6224 pipe_config->pixel_multiplier =
6225 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6226 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 6227
6228 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 6229 } else {
6230 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 6231 }
6232
1bd1bd80
DV		 6233 intel_get_pipe_timings(crtc, pipe_config);
6234
2fa2fe9a
DV		 6235 ironlake_get_pfit_config(crtc, pipe_config);
6236
0e8ffe1b
DV		 6237 return true;
6238}
6239
be256dc7
PZ		 6240static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6241{
6242 struct drm_device *dev = dev_priv->dev;
6243 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6244 struct intel_crtc *crtc;
6245 unsigned long irqflags;
bd633a7c 6246 uint32_t val;
be256dc7
PZ		 6247
6248 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6249 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
6250 pipe_name(crtc->pipe));
6251
6252 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6253 WARN(plls->spll_refcount, "SPLL enabled\n");
6254 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6255 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6256 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6257 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6258 "CPU PWM1 enabled\n");
6259 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6260 "CPU PWM2 enabled\n");
6261 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6262 "PCH PWM1 enabled\n");
6263 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6264 "Utility pin enabled\n");
6265 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6266
6267 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6268 val = I915_READ(DEIMR);
6269 WARN((val & ~DE_PCH_EVENT_IVB) != val,
6270 "Unexpected DEIMR bits enabled: 0x%x\n", val);
6271 val = I915_READ(SDEIMR);
bd633a7c 6272 WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
be256dc7
PZ		 6273 "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6274 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6275}
6276
6277/*
6278 * This function implements pieces of two sequences from BSpec:
6279 * - Sequence for display software to disable LCPLL
6280 * - Sequence for display software to allow package C8+
6281 * The steps implemented here are just the steps that actually touch the LCPLL
6282 * register. Callers should take care of disabling all the display engine
6283 * functions, doing the mode unset, fixing interrupts, etc.
6284 */
6ff58d53
PZ		 6285static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6286 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 6287{
6288 uint32_t val;
6289
6290 assert_can_disable_lcpll(dev_priv);
6291
6292 val = I915_READ(LCPLL_CTL);
6293
6294 if (switch_to_fclk) {
6295 val |= LCPLL_CD_SOURCE_FCLK;
6296 I915_WRITE(LCPLL_CTL, val);
6297
6298 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6299 LCPLL_CD_SOURCE_FCLK_DONE, 1))
6300 DRM_ERROR("Switching to FCLK failed\n");
6301
6302 val = I915_READ(LCPLL_CTL);
6303 }
6304
6305 val |= LCPLL_PLL_DISABLE;
6306 I915_WRITE(LCPLL_CTL, val);
6307 POSTING_READ(LCPLL_CTL);
6308
6309 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6310 DRM_ERROR("LCPLL still locked\n");
6311
6312 val = I915_READ(D_COMP);
6313 val |= D_COMP_COMP_DISABLE;
515b2392
PZ		 6314 mutex_lock(&dev_priv->rps.hw_lock);
6315 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6316 DRM_ERROR("Failed to disable D_COMP\n");
6317 mutex_unlock(&dev_priv->rps.hw_lock);
be256dc7
PZ		 6318 POSTING_READ(D_COMP);
6319 ndelay(100);
6320
6321 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6322 DRM_ERROR("D_COMP RCOMP still in progress\n");
6323
6324 if (allow_power_down) {
6325 val = I915_READ(LCPLL_CTL);
6326 val |= LCPLL_POWER_DOWN_ALLOW;
6327 I915_WRITE(LCPLL_CTL, val);
6328 POSTING_READ(LCPLL_CTL);
6329 }
6330}
6331
6332/*
6333 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6334 * source.
6335 */
6ff58d53 6336static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 6337{
6338 uint32_t val;
6339
6340 val = I915_READ(LCPLL_CTL);
6341
6342 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6343 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6344 return;
6345
215733fa
PZ		 6346 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6347 * we'll hang the machine! */
6348 dev_priv->uncore.funcs.force_wake_get(dev_priv);
6349
be256dc7
PZ		 6350 if (val & LCPLL_POWER_DOWN_ALLOW) {
6351 val &= ~LCPLL_POWER_DOWN_ALLOW;
6352 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 6353 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 6354 }
6355
6356 val = I915_READ(D_COMP);
6357 val |= D_COMP_COMP_FORCE;
6358 val &= ~D_COMP_COMP_DISABLE;
515b2392
PZ		 6359 mutex_lock(&dev_priv->rps.hw_lock);
6360 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6361 DRM_ERROR("Failed to enable D_COMP\n");
6362 mutex_unlock(&dev_priv->rps.hw_lock);
35d8f2eb 6363 POSTING_READ(D_COMP);
be256dc7
PZ		 6364
6365 val = I915_READ(LCPLL_CTL);
6366 val &= ~LCPLL_PLL_DISABLE;
6367 I915_WRITE(LCPLL_CTL, val);
6368
6369 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6370 DRM_ERROR("LCPLL not locked yet\n");
6371
6372 if (val & LCPLL_CD_SOURCE_FCLK) {
6373 val = I915_READ(LCPLL_CTL);
6374 val &= ~LCPLL_CD_SOURCE_FCLK;
6375 I915_WRITE(LCPLL_CTL, val);
6376
6377 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6378 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6379 DRM_ERROR("Switching back to LCPLL failed\n");
6380 }
215733fa
PZ		 6381
6382 dev_priv->uncore.funcs.force_wake_put(dev_priv);
be256dc7
PZ		 6383}
6384
c67a470b
PZ		 6385void hsw_enable_pc8_work(struct work_struct *__work)
6386{
6387 struct drm_i915_private *dev_priv =
6388 container_of(to_delayed_work(__work), struct drm_i915_private,
6389 pc8.enable_work);
6390 struct drm_device *dev = dev_priv->dev;
6391 uint32_t val;
6392
6393 if (dev_priv->pc8.enabled)
6394 return;
6395
6396 DRM_DEBUG_KMS("Enabling package C8+\n");
6397
6398 dev_priv->pc8.enabled = true;
6399
6400 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6401 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6402 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6403 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6404 }
6405
6406 lpt_disable_clkout_dp(dev);
6407 hsw_pc8_disable_interrupts(dev);
6408 hsw_disable_lcpll(dev_priv, true, true);
6409}
6410
6411static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6412{
6413 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6414 WARN(dev_priv->pc8.disable_count < 1,
6415 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6416
6417 dev_priv->pc8.disable_count--;
6418 if (dev_priv->pc8.disable_count != 0)
6419 return;
6420
6421 schedule_delayed_work(&dev_priv->pc8.enable_work,
90058745 6422 msecs_to_jiffies(i915_pc8_timeout));
c67a470b
PZ		 6423}
6424
6425static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6426{
6427 struct drm_device *dev = dev_priv->dev;
6428 uint32_t val;
6429
6430 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6431 WARN(dev_priv->pc8.disable_count < 0,
6432 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6433
6434 dev_priv->pc8.disable_count++;
6435 if (dev_priv->pc8.disable_count != 1)
6436 return;
6437
6438 cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6439 if (!dev_priv->pc8.enabled)
6440 return;
6441
6442 DRM_DEBUG_KMS("Disabling package C8+\n");
6443
6444 hsw_restore_lcpll(dev_priv);
6445 hsw_pc8_restore_interrupts(dev);
6446 lpt_init_pch_refclk(dev);
6447
6448 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6449 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6450 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6451 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6452 }
6453
6454 intel_prepare_ddi(dev);
6455 i915_gem_init_swizzling(dev);
6456 mutex_lock(&dev_priv->rps.hw_lock);
6457 gen6_update_ring_freq(dev);
6458 mutex_unlock(&dev_priv->rps.hw_lock);
6459 dev_priv->pc8.enabled = false;
6460}
6461
6462void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6463{
6464 mutex_lock(&dev_priv->pc8.lock);
6465 __hsw_enable_package_c8(dev_priv);
6466 mutex_unlock(&dev_priv->pc8.lock);
6467}
6468
6469void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6470{
6471 mutex_lock(&dev_priv->pc8.lock);
6472 __hsw_disable_package_c8(dev_priv);
6473 mutex_unlock(&dev_priv->pc8.lock);
6474}
6475
6476static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6477{
6478 struct drm_device *dev = dev_priv->dev;
6479 struct intel_crtc *crtc;
6480 uint32_t val;
6481
6482 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6483 if (crtc->base.enabled)
6484 return false;
6485
6486 /* This case is still possible since we have the i915.disable_power_well
6487 * parameter and also the KVMr or something else might be requesting the
6488 * power well. */
6489 val = I915_READ(HSW_PWR_WELL_DRIVER);
6490 if (val != 0) {
6491 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6492 return false;
6493 }
6494
6495 return true;
6496}
6497
6498/* Since we're called from modeset_global_resources there's no way to
6499 * symmetrically increase and decrease the refcount, so we use
6500 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6501 * or not.
6502 */
6503static void hsw_update_package_c8(struct drm_device *dev)
6504{
6505 struct drm_i915_private *dev_priv = dev->dev_private;
6506 bool allow;
6507
6508 if (!i915_enable_pc8)
6509 return;
6510
6511 mutex_lock(&dev_priv->pc8.lock);
6512
6513 allow = hsw_can_enable_package_c8(dev_priv);
6514
6515 if (allow == dev_priv->pc8.requirements_met)
6516 goto done;
6517
6518 dev_priv->pc8.requirements_met = allow;
6519
6520 if (allow)
6521 __hsw_enable_package_c8(dev_priv);
6522 else
6523 __hsw_disable_package_c8(dev_priv);
6524
6525done:
6526 mutex_unlock(&dev_priv->pc8.lock);
6527}
6528
6529static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6530{
6531 if (!dev_priv->pc8.gpu_idle) {
6532 dev_priv->pc8.gpu_idle = true;
6533 hsw_enable_package_c8(dev_priv);
6534 }
6535}
6536
6537static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6538{
6539 if (dev_priv->pc8.gpu_idle) {
6540 dev_priv->pc8.gpu_idle = false;
6541 hsw_disable_package_c8(dev_priv);
6542 }
be256dc7
PZ		 6543}
6544
d6dd9eb1
DV		 6545static void haswell_modeset_global_resources(struct drm_device *dev)
6546{
d6dd9eb1
DV		 6547 bool enable = false;
6548 struct intel_crtc *crtc;
d6dd9eb1
DV		 6549
6550 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 6551 if (!crtc->base.enabled)
6552 continue;
d6dd9eb1 6553
fd4daa9c 6554 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.enabled ||
e7a639c4 6555 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 6556 enable = true;
6557 }
6558
d6dd9eb1 6559 intel_set_power_well(dev, enable);
c67a470b
PZ		 6560
6561 hsw_update_package_c8(dev);
d6dd9eb1
DV		 6562}
6563
09b4ddf9 6564static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 6565 int x, int y,
6566 struct drm_framebuffer *fb)
6567{
6568 struct drm_device *dev = crtc->dev;
6569 struct drm_i915_private *dev_priv = dev->dev_private;
6570 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 6571 int plane = intel_crtc->plane;
09b4ddf9 6572 int ret;
09b4ddf9 6573
ff9a6750 6574 if (!intel_ddi_pll_mode_set(crtc))
6441ab5f
PZ		 6575 return -EINVAL;
6576
03afc4a2
DV		 6577 if (intel_crtc->config.has_dp_encoder)
6578 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 6579
6580 intel_crtc->lowfreq_avail = false;
09b4ddf9 6581
8a654f3b 6582 intel_set_pipe_timings(intel_crtc);
09b4ddf9 6583
ca3a0ff8 6584 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 6585 intel_cpu_transcoder_set_m_n(intel_crtc,
6586 &intel_crtc->config.fdi_m_n);
6587 }
09b4ddf9 6588
6ff93609 6589 haswell_set_pipeconf(crtc);
09b4ddf9 6590
50f3b016 6591 intel_set_pipe_csc(crtc);
86d3efce 6592
09b4ddf9 6593 /* Set up the display plane register */
86d3efce 6594 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 6595 POSTING_READ(DSPCNTR(plane));
6596
6597 ret = intel_pipe_set_base(crtc, x, y, fb);
6598
1f803ee5 6599 return ret;
79e53945
JB		 6600}
6601
0e8ffe1b
DV		 6602static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6603 struct intel_crtc_config *pipe_config)
6604{
6605 struct drm_device *dev = crtc->base.dev;
6606 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 6607 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 6608 uint32_t tmp;
6609
e143a21c 6610 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 6611 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6612
eccb140b
DV		 6613 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6614 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6615 enum pipe trans_edp_pipe;
6616 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6617 default:
6618 WARN(1, "unknown pipe linked to edp transcoder\n");
6619 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6620 case TRANS_DDI_EDP_INPUT_A_ON:
6621 trans_edp_pipe = PIPE_A;
6622 break;
6623 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6624 trans_edp_pipe = PIPE_B;
6625 break;
6626 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6627 trans_edp_pipe = PIPE_C;
6628 break;
6629 }
6630
6631 if (trans_edp_pipe == crtc->pipe)
6632 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6633 }
6634
b97186f0 6635 if (!intel_display_power_enabled(dev,
eccb140b 6636 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 6637 return false;
6638
eccb140b 6639 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 6640 if (!(tmp & PIPECONF_ENABLE))
6641 return false;
6642
88adfff1 6643 /*
f196e6be 6644 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 6645 * DDI E. So just check whether this pipe is wired to DDI E and whether
6646 * the PCH transcoder is on.
6647 */
eccb140b 6648 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 6649 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 6650 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 6651 pipe_config->has_pch_encoder = true;
6652
627eb5a3
DV		 6653 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6654 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6655 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6656
6657 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 6658 }
6659
1bd1bd80
DV		 6660 intel_get_pipe_timings(crtc, pipe_config);
6661
2fa2fe9a
DV		 6662 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6663 if (intel_display_power_enabled(dev, pfit_domain))
6664 ironlake_get_pfit_config(crtc, pipe_config);
88adfff1 6665
42db64ef
PZ		 6666 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6667 (I915_READ(IPS_CTL) & IPS_ENABLE);
6668
6c49f241
DV		 6669 pipe_config->pixel_multiplier = 1;
6670
0e8ffe1b
DV		 6671 return true;
6672}
6673
f564048e 6674static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6675 int x, int y,
94352cf9 6676 struct drm_framebuffer *fb)
f564048e
EA		 6677{
6678 struct drm_device *dev = crtc->dev;
6679 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19 6680 struct intel_encoder *encoder;
0b701d27 6681 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 6682 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6683 int pipe = intel_crtc->pipe;
f564048e
EA		 6684 int ret;
6685
0b701d27 6686 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6687
b8cecdf5
DV		 6688 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6689
79e53945 6690 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6691
9256aa19
DV		 6692 if (ret != 0)
6693 return ret;
6694
6695 for_each_encoder_on_crtc(dev, crtc, encoder) {
6696 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6697 encoder->base.base.id,
6698 drm_get_encoder_name(&encoder->base),
6699 mode->base.id, mode->name);
36f2d1f1 6700 encoder->mode_set(encoder);
9256aa19
DV		 6701 }
6702
6703 return 0;
79e53945
JB		 6704}
6705
3a9627f4
WF		 6706static bool intel_eld_uptodate(struct drm_connector *connector,
6707 int reg_eldv, uint32_t bits_eldv,
6708 int reg_elda, uint32_t bits_elda,
6709 int reg_edid)
6710{
6711 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6712 uint8_t *eld = connector->eld;
6713 uint32_t i;
6714
6715 i = I915_READ(reg_eldv);
6716 i &= bits_eldv;
6717
6718 if (!eld[0])
6719 return !i;
6720
6721 if (!i)
6722 return false;
6723
6724 i = I915_READ(reg_elda);
6725 i &= ~bits_elda;
6726 I915_WRITE(reg_elda, i);
6727
6728 for (i = 0; i < eld[2]; i++)
6729 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6730 return false;
6731
6732 return true;
6733}
6734
e0dac65e
WF		 6735static void g4x_write_eld(struct drm_connector *connector,
6736 struct drm_crtc *crtc)
6737{
6738 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6739 uint8_t *eld = connector->eld;
6740 uint32_t eldv;
6741 uint32_t len;
6742 uint32_t i;
6743
6744 i = I915_READ(G4X_AUD_VID_DID);
6745
6746 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6747 eldv = G4X_ELDV_DEVCL_DEVBLC;
6748 else
6749 eldv = G4X_ELDV_DEVCTG;
6750
3a9627f4
WF		 6751 if (intel_eld_uptodate(connector,
6752 G4X_AUD_CNTL_ST, eldv,
6753 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6754 G4X_HDMIW_HDMIEDID))
6755 return;
6756
e0dac65e
WF		 6757 i = I915_READ(G4X_AUD_CNTL_ST);
6758 i &= ~(eldv | G4X_ELD_ADDR);
6759 len = (i >> 9) & 0x1f; /* ELD buffer size */
6760 I915_WRITE(G4X_AUD_CNTL_ST, i);
6761
6762 if (!eld[0])
6763 return;
6764
6765 len = min_t(uint8_t, eld[2], len);
6766 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6767 for (i = 0; i < len; i++)
6768 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6769
6770 i = I915_READ(G4X_AUD_CNTL_ST);
6771 i |= eldv;
6772 I915_WRITE(G4X_AUD_CNTL_ST, i);
6773}
6774
83358c85
WX		 6775static void haswell_write_eld(struct drm_connector *connector,
6776 struct drm_crtc *crtc)
6777{
6778 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6779 uint8_t *eld = connector->eld;
6780 struct drm_device *dev = crtc->dev;
7b9f35a6 6781 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6782 uint32_t eldv;
6783 uint32_t i;
6784 int len;
6785 int pipe = to_intel_crtc(crtc)->pipe;
6786 int tmp;
6787
6788 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6789 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6790 int aud_config = HSW_AUD_CFG(pipe);
6791 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6792
6793
6794 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6795
6796 /* Audio output enable */
6797 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6798 tmp = I915_READ(aud_cntrl_st2);
6799 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6800 I915_WRITE(aud_cntrl_st2, tmp);
6801
6802 /* Wait for 1 vertical blank */
6803 intel_wait_for_vblank(dev, pipe);
6804
6805 /* Set ELD valid state */
6806 tmp = I915_READ(aud_cntrl_st2);
7e7cb34f 6807 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
83358c85
WX		 6808 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6809 I915_WRITE(aud_cntrl_st2, tmp);
6810 tmp = I915_READ(aud_cntrl_st2);
7e7cb34f 6811 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
83358c85
WX		 6812
6813 /* Enable HDMI mode */
6814 tmp = I915_READ(aud_config);
7e7cb34f 6815 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
83358c85
WX		 6816 /* clear N_programing_enable and N_value_index */
6817 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6818 I915_WRITE(aud_config, tmp);
6819
6820 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6821
6822 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6823 intel_crtc->eld_vld = true;
83358c85
WX		 6824
6825 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6826 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6827 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6828 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6829 } else
6830 I915_WRITE(aud_config, 0);
6831
6832 if (intel_eld_uptodate(connector,
6833 aud_cntrl_st2, eldv,
6834 aud_cntl_st, IBX_ELD_ADDRESS,
6835 hdmiw_hdmiedid))
6836 return;
6837
6838 i = I915_READ(aud_cntrl_st2);
6839 i &= ~eldv;
6840 I915_WRITE(aud_cntrl_st2, i);
6841
6842 if (!eld[0])
6843 return;
6844
6845 i = I915_READ(aud_cntl_st);
6846 i &= ~IBX_ELD_ADDRESS;
6847 I915_WRITE(aud_cntl_st, i);
6848 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6849 DRM_DEBUG_DRIVER("port num:%d\n", i);
6850
6851 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6852 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6853 for (i = 0; i < len; i++)
6854 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6855
6856 i = I915_READ(aud_cntrl_st2);
6857 i |= eldv;
6858 I915_WRITE(aud_cntrl_st2, i);
6859
6860}
6861
e0dac65e
WF		 6862static void ironlake_write_eld(struct drm_connector *connector,
6863 struct drm_crtc *crtc)
6864{
6865 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6866 uint8_t *eld = connector->eld;
6867 uint32_t eldv;
6868 uint32_t i;
6869 int len;
6870 int hdmiw_hdmiedid;
b6daa025 6871 int aud_config;
e0dac65e
WF		 6872 int aud_cntl_st;
6873 int aud_cntrl_st2;
9b138a83 6874 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6875
b3f33cbf 6876 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6877 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6878 aud_config = IBX_AUD_CFG(pipe);
6879 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6880 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6881 } else {
9b138a83
WX		 6882 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6883 aud_config = CPT_AUD_CFG(pipe);
6884 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6885 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6886 }
6887
9b138a83 6888 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6889
6890 i = I915_READ(aud_cntl_st);
9b138a83 6891 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6892 if (!i) {
6893 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6894 /* operate blindly on all ports */
1202b4c6
WF		 6895 eldv = IBX_ELD_VALIDB;
6896 eldv |= IBX_ELD_VALIDB << 4;
6897 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6898 } else {
2582a850 6899 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6900 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6901 }
6902
3a9627f4
WF		 6903 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6904 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6905 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6906 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6907 } else
6908 I915_WRITE(aud_config, 0);
e0dac65e 6909
3a9627f4
WF		 6910 if (intel_eld_uptodate(connector,
6911 aud_cntrl_st2, eldv,
6912 aud_cntl_st, IBX_ELD_ADDRESS,
6913 hdmiw_hdmiedid))
6914 return;
6915
e0dac65e
WF		 6916 i = I915_READ(aud_cntrl_st2);
6917 i &= ~eldv;
6918 I915_WRITE(aud_cntrl_st2, i);
6919
6920 if (!eld[0])
6921 return;
6922
e0dac65e 6923 i = I915_READ(aud_cntl_st);
1202b4c6 6924 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6925 I915_WRITE(aud_cntl_st, i);
6926
6927 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6928 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6929 for (i = 0; i < len; i++)
6930 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6931
6932 i = I915_READ(aud_cntrl_st2);
6933 i |= eldv;
6934 I915_WRITE(aud_cntrl_st2, i);
6935}
6936
6937void intel_write_eld(struct drm_encoder *encoder,
6938 struct drm_display_mode *mode)
6939{
6940 struct drm_crtc *crtc = encoder->crtc;
6941 struct drm_connector *connector;
6942 struct drm_device *dev = encoder->dev;
6943 struct drm_i915_private *dev_priv = dev->dev_private;
6944
6945 connector = drm_select_eld(encoder, mode);
6946 if (!connector)
6947 return;
6948
6949 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6950 connector->base.id,
6951 drm_get_connector_name(connector),
6952 connector->encoder->base.id,
6953 drm_get_encoder_name(connector->encoder));
6954
6955 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6956
6957 if (dev_priv->display.write_eld)
6958 dev_priv->display.write_eld(connector, crtc);
6959}
6960
560b85bb
CW		 6961static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6962{
6963 struct drm_device *dev = crtc->dev;
6964 struct drm_i915_private *dev_priv = dev->dev_private;
6965 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6966 bool visible = base != 0;
6967 u32 cntl;
6968
6969 if (intel_crtc->cursor_visible == visible)
6970 return;
6971
9db4a9c7 6972 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6973 if (visible) {
6974 /* On these chipsets we can only modify the base whilst
6975 * the cursor is disabled.
6976 */
9db4a9c7 6977 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6978
6979 cntl &= ~(CURSOR_FORMAT_MASK);
6980 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6981 cntl |= CURSOR_ENABLE |
6982 CURSOR_GAMMA_ENABLE |
6983 CURSOR_FORMAT_ARGB;
6984 } else
6985 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6986 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6987
6988 intel_crtc->cursor_visible = visible;
6989}
6990
6991static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6992{
6993 struct drm_device *dev = crtc->dev;
6994 struct drm_i915_private *dev_priv = dev->dev_private;
6995 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6996 int pipe = intel_crtc->pipe;
6997 bool visible = base != 0;
6998
6999 if (intel_crtc->cursor_visible != visible) {
548f245b 7000 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 7001 if (base) {
7002 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7003 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7004 cntl |= pipe << 28; /* Connect to correct pipe */
7005 } else {
7006 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7007 cntl |= CURSOR_MODE_DISABLE;
7008 }
9db4a9c7 7009 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 7010
7011 intel_crtc->cursor_visible = visible;
7012 }
7013 /* and commit changes on next vblank */
9db4a9c7 7014 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 7015}
7016
65a21cd6
JB		 7017static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7018{
7019 struct drm_device *dev = crtc->dev;
7020 struct drm_i915_private *dev_priv = dev->dev_private;
7021 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7022 int pipe = intel_crtc->pipe;
7023 bool visible = base != 0;
7024
7025 if (intel_crtc->cursor_visible != visible) {
7026 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7027 if (base) {
7028 cntl &= ~CURSOR_MODE;
7029 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7030 } else {
7031 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7032 cntl |= CURSOR_MODE_DISABLE;
7033 }
1f5d76db 7034 if (IS_HASWELL(dev)) {
86d3efce 7035 cntl |= CURSOR_PIPE_CSC_ENABLE;
1f5d76db
PZ		 7036 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7037 }
65a21cd6
JB		 7038 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7039
7040 intel_crtc->cursor_visible = visible;
7041 }
7042 /* and commit changes on next vblank */
7043 I915_WRITE(CURBASE_IVB(pipe), base);
7044}
7045
cda4b7d3 7046/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 7047static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7048 bool on)
cda4b7d3
CW		 7049{
7050 struct drm_device *dev = crtc->dev;
7051 struct drm_i915_private *dev_priv = dev->dev_private;
7052 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7053 int pipe = intel_crtc->pipe;
7054 int x = intel_crtc->cursor_x;
7055 int y = intel_crtc->cursor_y;
d6e4db15 7056 u32 base = 0, pos = 0;
cda4b7d3
CW		 7057 bool visible;
7058
d6e4db15 7059 if (on)
cda4b7d3 7060 base = intel_crtc->cursor_addr;
cda4b7d3 7061
d6e4db15
VS		 7062 if (x >= intel_crtc->config.pipe_src_w)
7063 base = 0;
7064
7065 if (y >= intel_crtc->config.pipe_src_h)
cda4b7d3
CW		 7066 base = 0;
7067
7068 if (x < 0) {
efc9064e 7069 if (x + intel_crtc->cursor_width <= 0)
cda4b7d3
CW		 7070 base = 0;
7071
7072 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7073 x = -x;
7074 }
7075 pos |= x << CURSOR_X_SHIFT;
7076
7077 if (y < 0) {
efc9064e 7078 if (y + intel_crtc->cursor_height <= 0)
cda4b7d3
CW		 7079 base = 0;
7080
7081 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7082 y = -y;
7083 }
7084 pos |= y << CURSOR_Y_SHIFT;
7085
7086 visible = base != 0;
560b85bb 7087 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 7088 return;
7089
0cd83aa9 7090 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 7091 I915_WRITE(CURPOS_IVB(pipe), pos);
7092 ivb_update_cursor(crtc, base);
7093 } else {
7094 I915_WRITE(CURPOS(pipe), pos);
7095 if (IS_845G(dev) || IS_I865G(dev))
7096 i845_update_cursor(crtc, base);
7097 else
7098 i9xx_update_cursor(crtc, base);
7099 }
cda4b7d3
CW		 7100}
7101
79e53945 7102static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 7103 struct drm_file *file,
79e53945
JB		 7104 uint32_t handle,
7105 uint32_t width, uint32_t height)
7106{
7107 struct drm_device *dev = crtc->dev;
7108 struct drm_i915_private *dev_priv = dev->dev_private;
7109 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 7110 struct drm_i915_gem_object *obj;
cda4b7d3 7111 uint32_t addr;
3f8bc370 7112 int ret;
79e53945 7113
79e53945
JB		 7114 /* if we want to turn off the cursor ignore width and height */
7115 if (!handle) {
28c97730 7116 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 7117 addr = 0;
05394f39 7118 obj = NULL;
5004417d 7119 mutex_lock(&dev->struct_mutex);
3f8bc370 7120 goto finish;
79e53945
JB		 7121 }
7122
7123 /* Currently we only support 64x64 cursors */
7124 if (width != 64 || height != 64) {
7125 DRM_ERROR("we currently only support 64x64 cursors\n");
7126 return -EINVAL;
7127 }
7128
05394f39 7129 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 7130 if (&obj->base == NULL)
79e53945
JB		 7131 return -ENOENT;
7132
05394f39 7133 if (obj->base.size < width * height * 4) {
79e53945 7134 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 7135 ret = -ENOMEM;
7136 goto fail;
79e53945
JB		 7137 }
7138
71acb5eb 7139 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 7140 mutex_lock(&dev->struct_mutex);
b295d1b6 7141 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 7142 unsigned alignment;
7143
d9e86c0e
CW		 7144 if (obj->tiling_mode) {
7145 DRM_ERROR("cursor cannot be tiled\n");
7146 ret = -EINVAL;
7147 goto fail_locked;
7148 }
7149
693db184
CW		 7150 /* Note that the w/a also requires 2 PTE of padding following
7151 * the bo. We currently fill all unused PTE with the shadow
7152 * page and so we should always have valid PTE following the
7153 * cursor preventing the VT-d warning.
7154 */
7155 alignment = 0;
7156 if (need_vtd_wa(dev))
7157 alignment = 64*1024;
7158
7159 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 7160 if (ret) {
7161 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 7162 goto fail_locked;
e7b526bb
CW		 7163 }
7164
d9e86c0e
CW		 7165 ret = i915_gem_object_put_fence(obj);
7166 if (ret) {
2da3b9b9 7167 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 7168 goto fail_unpin;
7169 }
7170
f343c5f6 7171 addr = i915_gem_obj_ggtt_offset(obj);
71acb5eb 7172 } else {
6eeefaf3 7173 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 7174 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 7175 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7176 align);
71acb5eb
DA		 7177 if (ret) {
7178 DRM_ERROR("failed to attach phys object\n");
7f9872e0 7179 goto fail_locked;
71acb5eb 7180 }
05394f39 7181 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 7182 }
7183
a6c45cf0 7184 if (IS_GEN2(dev))
14b60391
JB		 7185 I915_WRITE(CURSIZE, (height << 12) | width);
7186
3f8bc370 7187 finish:
3f8bc370 7188 if (intel_crtc->cursor_bo) {
b295d1b6 7189 if (dev_priv->info->cursor_needs_physical) {
05394f39 7190 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 7191 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7192 } else
cc98b413 7193 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
05394f39 7194 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 7195 }
80824003 7196
7f9872e0 7197 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 7198
7199 intel_crtc->cursor_addr = addr;
05394f39 7200 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 7201 intel_crtc->cursor_width = width;
7202 intel_crtc->cursor_height = height;
7203
f2f5f771
VS		 7204 if (intel_crtc->active)
7205 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 7206
79e53945 7207 return 0;
e7b526bb 7208fail_unpin:
cc98b413 7209 i915_gem_object_unpin_from_display_plane(obj);
7f9872e0 7210fail_locked:
34b8686e 7211 mutex_unlock(&dev->struct_mutex);
bc9025bd 7212fail:
05394f39 7213 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 7214 return ret;
79e53945
JB		 7215}
7216
7217static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7218{
79e53945 7219 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7220
cda4b7d3
CW		 7221 intel_crtc->cursor_x = x;
7222 intel_crtc->cursor_y = y;
652c393a 7223
f2f5f771
VS		 7224 if (intel_crtc->active)
7225 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 7226
7227 return 0;
b8c00ac5
DA		 7228}
7229
79e53945 7230static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 7231 u16 *blue, uint32_t start, uint32_t size)
79e53945 7232{
7203425a 7233 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 7234 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7235
7203425a 7236 for (i = start; i < end; i++) {
79e53945
JB		 7237 intel_crtc->lut_r[i] = red[i] >> 8;
7238 intel_crtc->lut_g[i] = green[i] >> 8;
7239 intel_crtc->lut_b[i] = blue[i] >> 8;
7240 }
7241
7242 intel_crtc_load_lut(crtc);
7243}
7244
79e53945
JB		 7245/* VESA 640x480x72Hz mode to set on the pipe */
7246static struct drm_display_mode load_detect_mode = {
7247 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7248 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7249};
7250
d2dff872
CW		 7251static struct drm_framebuffer *
7252intel_framebuffer_create(struct drm_device *dev,
308e5bcb 7253 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 7254 struct drm_i915_gem_object *obj)
7255{
7256 struct intel_framebuffer *intel_fb;
7257 int ret;
7258
7259 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7260 if (!intel_fb) {
7261 drm_gem_object_unreference_unlocked(&obj->base);
7262 return ERR_PTR(-ENOMEM);
7263 }
7264
7265 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7266 if (ret) {
7267 drm_gem_object_unreference_unlocked(&obj->base);
7268 kfree(intel_fb);
7269 return ERR_PTR(ret);
7270 }
7271
7272 return &intel_fb->base;
7273}
7274
7275static u32
7276intel_framebuffer_pitch_for_width(int width, int bpp)
7277{
7278 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7279 return ALIGN(pitch, 64);
7280}
7281
7282static u32
7283intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7284{
7285 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7286 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7287}
7288
7289static struct drm_framebuffer *
7290intel_framebuffer_create_for_mode(struct drm_device *dev,
7291 struct drm_display_mode *mode,
7292 int depth, int bpp)
7293{
7294 struct drm_i915_gem_object *obj;
0fed39bd 7295 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 7296
7297 obj = i915_gem_alloc_object(dev,
7298 intel_framebuffer_size_for_mode(mode, bpp));
7299 if (obj == NULL)
7300 return ERR_PTR(-ENOMEM);
7301
7302 mode_cmd.width = mode->hdisplay;
7303 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 7304 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7305 bpp);
5ca0c34a 7306 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 7307
7308 return intel_framebuffer_create(dev, &mode_cmd, obj);
7309}
7310
7311static struct drm_framebuffer *
7312mode_fits_in_fbdev(struct drm_device *dev,
7313 struct drm_display_mode *mode)
7314{
7315 struct drm_i915_private *dev_priv = dev->dev_private;
7316 struct drm_i915_gem_object *obj;
7317 struct drm_framebuffer *fb;
7318
7319 if (dev_priv->fbdev == NULL)
7320 return NULL;
7321
7322 obj = dev_priv->fbdev->ifb.obj;
7323 if (obj == NULL)
7324 return NULL;
7325
7326 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 7327 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7328 fb->bits_per_pixel))
d2dff872
CW		 7329 return NULL;
7330
01f2c773 7331 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 7332 return NULL;
7333
7334 return fb;
7335}
7336
d2434ab7 7337bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 7338 struct drm_display_mode *mode,
8261b191 7339 struct intel_load_detect_pipe *old)
79e53945
JB		 7340{
7341 struct intel_crtc *intel_crtc;
d2434ab7
DV		 7342 struct intel_encoder *intel_encoder =
7343 intel_attached_encoder(connector);
79e53945 7344 struct drm_crtc *possible_crtc;
4ef69c7a 7345 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 7346 struct drm_crtc *crtc = NULL;
7347 struct drm_device *dev = encoder->dev;
94352cf9 7348 struct drm_framebuffer *fb;
79e53945
JB		 7349 int i = -1;
7350
d2dff872
CW		 7351 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7352 connector->base.id, drm_get_connector_name(connector),
7353 encoder->base.id, drm_get_encoder_name(encoder));
7354
79e53945
JB		 7355 /*
7356 * Algorithm gets a little messy:
7a5e4805 7357 *
79e53945
JB		 7358 * - if the connector already has an assigned crtc, use it (but make
7359 * sure it's on first)
7a5e4805 7360 *
79e53945
JB		 7361 * - try to find the first unused crtc that can drive this connector,
7362 * and use that if we find one
79e53945
JB		 7363 */
7364
7365 /* See if we already have a CRTC for this connector */
7366 if (encoder->crtc) {
7367 crtc = encoder->crtc;
8261b191 7368
7b24056b
DV		 7369 mutex_lock(&crtc->mutex);
7370
24218aac 7371 old->dpms_mode = connector->dpms;
8261b191
CW		 7372 old->load_detect_temp = false;
7373
7374 /* Make sure the crtc and connector are running */
24218aac
DV		 7375 if (connector->dpms != DRM_MODE_DPMS_ON)
7376 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 7377
7173188d 7378 return true;
79e53945
JB		 7379 }
7380
7381 /* Find an unused one (if possible) */
7382 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7383 i++;
7384 if (!(encoder->possible_crtcs & (1 << i)))
7385 continue;
7386 if (!possible_crtc->enabled) {
7387 crtc = possible_crtc;
7388 break;
7389 }
79e53945
JB		 7390 }
7391
7392 /*
7393 * If we didn't find an unused CRTC, don't use any.
7394 */
7395 if (!crtc) {
7173188d
CW		 7396 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7397 return false;
79e53945
JB		 7398 }
7399
7b24056b 7400 mutex_lock(&crtc->mutex);
fc303101
DV		 7401 intel_encoder->new_crtc = to_intel_crtc(crtc);
7402 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 7403
7404 intel_crtc = to_intel_crtc(crtc);
24218aac 7405 old->dpms_mode = connector->dpms;
8261b191 7406 old->load_detect_temp = true;
d2dff872 7407 old->release_fb = NULL;
79e53945 7408
6492711d
CW		 7409 if (!mode)
7410 mode = &load_detect_mode;
79e53945 7411
d2dff872
CW		 7412 /* We need a framebuffer large enough to accommodate all accesses
7413 * that the plane may generate whilst we perform load detection.
7414 * We can not rely on the fbcon either being present (we get called
7415 * during its initialisation to detect all boot displays, or it may
7416 * not even exist) or that it is large enough to satisfy the
7417 * requested mode.
7418 */
94352cf9
DV		 7419 fb = mode_fits_in_fbdev(dev, mode);
7420 if (fb == NULL) {
d2dff872 7421 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 7422 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7423 old->release_fb = fb;
d2dff872
CW		 7424 } else
7425 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 7426 if (IS_ERR(fb)) {
d2dff872 7427 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 7428 mutex_unlock(&crtc->mutex);
0e8b3d3e 7429 return false;
79e53945 7430 }
79e53945 7431
c0c36b94 7432 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 7433 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 7434 if (old->release_fb)
7435 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 7436 mutex_unlock(&crtc->mutex);
0e8b3d3e 7437 return false;
79e53945 7438 }
7173188d 7439
79e53945 7440 /* let the connector get through one full cycle before testing */
9d0498a2 7441 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 7442 return true;
79e53945
JB		 7443}
7444
d2434ab7 7445void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 7446 struct intel_load_detect_pipe *old)
79e53945 7447{
d2434ab7
DV		 7448 struct intel_encoder *intel_encoder =
7449 intel_attached_encoder(connector);
4ef69c7a 7450 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 7451 struct drm_crtc *crtc = encoder->crtc;
79e53945 7452
d2dff872
CW		 7453 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7454 connector->base.id, drm_get_connector_name(connector),
7455 encoder->base.id, drm_get_encoder_name(encoder));
7456
8261b191 7457 if (old->load_detect_temp) {
fc303101
DV		 7458 to_intel_connector(connector)->new_encoder = NULL;
7459 intel_encoder->new_crtc = NULL;
7460 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 7461
36206361
DV		 7462 if (old->release_fb) {
7463 drm_framebuffer_unregister_private(old->release_fb);
7464 drm_framebuffer_unreference(old->release_fb);
7465 }
d2dff872 7466
67c96400 7467 mutex_unlock(&crtc->mutex);
0622a53c 7468 return;
79e53945
JB		 7469 }
7470
c751ce4f 7471 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 7472 if (old->dpms_mode != DRM_MODE_DPMS_ON)
7473 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 7474
7475 mutex_unlock(&crtc->mutex);
79e53945
JB		 7476}
7477
da4a1efa
VS		 7478static int i9xx_pll_refclk(struct drm_device *dev,
7479 const struct intel_crtc_config *pipe_config)
7480{
7481 struct drm_i915_private *dev_priv = dev->dev_private;
7482 u32 dpll = pipe_config->dpll_hw_state.dpll;
7483
7484 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7485 return dev_priv->vbt.lvds_ssc_freq * 1000;
7486 else if (HAS_PCH_SPLIT(dev))
7487 return 120000;
7488 else if (!IS_GEN2(dev))
7489 return 96000;
7490 else
7491 return 48000;
7492}
7493
79e53945 7494/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc
JB		 7495static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7496 struct intel_crtc_config *pipe_config)
79e53945 7497{
f1f644dc 7498 struct drm_device *dev = crtc->base.dev;
79e53945 7499 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 7500 int pipe = pipe_config->cpu_transcoder;
293623f7 7501 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 7502 u32 fp;
7503 intel_clock_t clock;
da4a1efa 7504 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 7505
7506 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 7507 fp = pipe_config->dpll_hw_state.fp0;
79e53945 7508 else
293623f7 7509 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 7510
7511 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 7512 if (IS_PINEVIEW(dev)) {
7513 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7514 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 7515 } else {
7516 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7517 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7518 }
7519
a6c45cf0 7520 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 7521 if (IS_PINEVIEW(dev))
7522 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7523 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 7524 else
7525 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 7526 DPLL_FPA01_P1_POST_DIV_SHIFT);
7527
7528 switch (dpll & DPLL_MODE_MASK) {
7529 case DPLLB_MODE_DAC_SERIAL:
7530 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7531 5 : 10;
7532 break;
7533 case DPLLB_MODE_LVDS:
7534 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7535 7 : 14;
7536 break;
7537 default:
28c97730 7538 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 7539 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 7540 return;
79e53945
JB		 7541 }
7542
ac58c3f0 7543 if (IS_PINEVIEW(dev))
da4a1efa 7544 pineview_clock(refclk, &clock);
ac58c3f0 7545 else
da4a1efa 7546 i9xx_clock(refclk, &clock);
79e53945
JB		 7547 } else {
7548 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7549
7550 if (is_lvds) {
7551 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7552 DPLL_FPA01_P1_POST_DIV_SHIFT);
7553 clock.p2 = 14;
79e53945
JB		 7554 } else {
7555 if (dpll & PLL_P1_DIVIDE_BY_TWO)
7556 clock.p1 = 2;
7557 else {
7558 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7559 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7560 }
7561 if (dpll & PLL_P2_DIVIDE_BY_4)
7562 clock.p2 = 4;
7563 else
7564 clock.p2 = 2;
79e53945 7565 }
da4a1efa
VS		 7566
7567 i9xx_clock(refclk, &clock);
79e53945
JB		 7568 }
7569
18442d08
VS		 7570 /*
7571 * This value includes pixel_multiplier. We will use
241bfc38 7572 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 7573 * encoder's get_config() function.
7574 */
7575 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 7576}
7577
6878da05
VS		 7578int intel_dotclock_calculate(int link_freq,
7579 const struct intel_link_m_n *m_n)
f1f644dc 7580{
f1f644dc
JB		 7581 /*
7582 * The calculation for the data clock is:
1041a02f 7583 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 7584 * But we want to avoid losing precison if possible, so:
1041a02f 7585 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 7586 *
7587 * and the link clock is simpler:
1041a02f 7588 * link_clock = (m * link_clock) / n
f1f644dc
JB		 7589 */
7590
6878da05
VS		 7591 if (!m_n->link_n)
7592 return 0;
f1f644dc 7593
6878da05
VS		 7594 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
7595}
f1f644dc 7596
18442d08
VS		 7597static void ironlake_pch_clock_get(struct intel_crtc *crtc,
7598 struct intel_crtc_config *pipe_config)
6878da05
VS		 7599{
7600 struct drm_device *dev = crtc->base.dev;
79e53945 7601
18442d08
VS		 7602 /* read out port_clock from the DPLL */
7603 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 7604
f1f644dc 7605 /*
18442d08 7606 * This value does not include pixel_multiplier.
241bfc38 7607 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 7608 * agree once we know their relationship in the encoder's
7609 * get_config() function.
79e53945 7610 */
241bfc38 7611 pipe_config->adjusted_mode.crtc_clock =
18442d08
VS		 7612 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
7613 &pipe_config->fdi_m_n);
79e53945
JB		 7614}
7615
7616/** Returns the currently programmed mode of the given pipe. */
7617struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7618 struct drm_crtc *crtc)
7619{
548f245b 7620 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 7621 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 7622 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 7623 struct drm_display_mode *mode;
f1f644dc 7624 struct intel_crtc_config pipe_config;
fe2b8f9d
PZ		 7625 int htot = I915_READ(HTOTAL(cpu_transcoder));
7626 int hsync = I915_READ(HSYNC(cpu_transcoder));
7627 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7628 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 7629 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 7630
7631 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7632 if (!mode)
7633 return NULL;
7634
f1f644dc
JB		 7635 /*
7636 * Construct a pipe_config sufficient for getting the clock info
7637 * back out of crtc_clock_get.
7638 *
7639 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7640 * to use a real value here instead.
7641 */
293623f7 7642 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 7643 pipe_config.pixel_multiplier = 1;
293623f7
VS		 7644 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
7645 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
7646 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 7647 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7648
773ae034 7649 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 7650 mode->hdisplay = (htot & 0xffff) + 1;
7651 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7652 mode->hsync_start = (hsync & 0xffff) + 1;
7653 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7654 mode->vdisplay = (vtot & 0xffff) + 1;
7655 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7656 mode->vsync_start = (vsync & 0xffff) + 1;
7657 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7658
7659 drm_mode_set_name(mode);
79e53945
JB		 7660
7661 return mode;
7662}
7663
3dec0095 7664static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7665{
7666 struct drm_device *dev = crtc->dev;
7667 drm_i915_private_t *dev_priv = dev->dev_private;
7668 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7669 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7670 int dpll_reg = DPLL(pipe);
7671 int dpll;
652c393a 7672
bad720ff 7673 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7674 return;
7675
7676 if (!dev_priv->lvds_downclock_avail)
7677 return;
7678
dbdc6479 7679 dpll = I915_READ(dpll_reg);
652c393a 7680 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7681 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7682
8ac5a6d5 7683 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7684
7685 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7686 I915_WRITE(dpll_reg, dpll);
9d0498a2 7687 intel_wait_for_vblank(dev, pipe);
dbdc6479 7688
652c393a
JB		 7689 dpll = I915_READ(dpll_reg);
7690 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7691 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7692 }
652c393a
JB		 7693}
7694
7695static void intel_decrease_pllclock(struct drm_crtc *crtc)
7696{
7697 struct drm_device *dev = crtc->dev;
7698 drm_i915_private_t *dev_priv = dev->dev_private;
7699 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7700
bad720ff 7701 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7702 return;
7703
7704 if (!dev_priv->lvds_downclock_avail)
7705 return;
7706
7707 /*
7708 * Since this is called by a timer, we should never get here in
7709 * the manual case.
7710 */
7711 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7712 int pipe = intel_crtc->pipe;
7713 int dpll_reg = DPLL(pipe);
7714 int dpll;
f6e5b160 7715
44d98a61 7716 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7717
8ac5a6d5 7718 assert_panel_unlocked(dev_priv, pipe);
652c393a 7719
dc257cf1 7720 dpll = I915_READ(dpll_reg);
652c393a
JB		 7721 dpll |= DISPLAY_RATE_SELECT_FPA1;
7722 I915_WRITE(dpll_reg, dpll);
9d0498a2 7723 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7724 dpll = I915_READ(dpll_reg);
7725 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7726 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7727 }
7728
7729}
7730
f047e395
CW		 7731void intel_mark_busy(struct drm_device *dev)
7732{
c67a470b
PZ		 7733 struct drm_i915_private *dev_priv = dev->dev_private;
7734
7735 hsw_package_c8_gpu_busy(dev_priv);
7736 i915_update_gfx_val(dev_priv);
f047e395
CW		 7737}
7738
7739void intel_mark_idle(struct drm_device *dev)
652c393a 7740{
c67a470b 7741 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 7742 struct drm_crtc *crtc;
652c393a 7743
c67a470b
PZ		 7744 hsw_package_c8_gpu_idle(dev_priv);
7745
652c393a
JB		 7746 if (!i915_powersave)
7747 return;
7748
652c393a 7749 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7750 if (!crtc->fb)
7751 continue;
7752
725a5b54 7753 intel_decrease_pllclock(crtc);
652c393a 7754 }
b29c19b6
CW		 7755
7756 if (dev_priv->info->gen >= 6)
7757 gen6_rps_idle(dev->dev_private);
652c393a
JB		 7758}
7759
c65355bb
CW		 7760void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7761 struct intel_ring_buffer *ring)
652c393a 7762{
f047e395
CW		 7763 struct drm_device *dev = obj->base.dev;
7764 struct drm_crtc *crtc;
652c393a 7765
f047e395 7766 if (!i915_powersave)
acb87dfb
CW		 7767 return;
7768
652c393a
JB		 7769 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7770 if (!crtc->fb)
7771 continue;
7772
c65355bb
CW		 7773 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7774 continue;
7775
7776 intel_increase_pllclock(crtc);
7777 if (ring && intel_fbc_enabled(dev))
7778 ring->fbc_dirty = true;
652c393a
JB		 7779 }
7780}
7781
79e53945
JB		 7782static void intel_crtc_destroy(struct drm_crtc *crtc)
7783{
7784 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7785 struct drm_device *dev = crtc->dev;
7786 struct intel_unpin_work *work;
7787 unsigned long flags;
7788
7789 spin_lock_irqsave(&dev->event_lock, flags);
7790 work = intel_crtc->unpin_work;
7791 intel_crtc->unpin_work = NULL;
7792 spin_unlock_irqrestore(&dev->event_lock, flags);
7793
7794 if (work) {
7795 cancel_work_sync(&work->work);
7796 kfree(work);
7797 }
79e53945 7798
40ccc72b
MK		 7799 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7800
79e53945 7801 drm_crtc_cleanup(crtc);
67e77c5a 7802
79e53945
JB		 7803 kfree(intel_crtc);
7804}
7805
6b95a207
KH		 7806static void intel_unpin_work_fn(struct work_struct *__work)
7807{
7808 struct intel_unpin_work *work =
7809 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7810 struct drm_device *dev = work->crtc->dev;
6b95a207 7811
b4a98e57 7812 mutex_lock(&dev->struct_mutex);
1690e1eb 7813 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7814 drm_gem_object_unreference(&work->pending_flip_obj->base);
7815 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7816
b4a98e57
CW		 7817 intel_update_fbc(dev);
7818 mutex_unlock(&dev->struct_mutex);
7819
7820 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7821 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7822
6b95a207
KH		 7823 kfree(work);
7824}
7825
1afe3e9d 7826static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7827 struct drm_crtc *crtc)
6b95a207
KH		 7828{
7829 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7830 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7831 struct intel_unpin_work *work;
6b95a207
KH		 7832 unsigned long flags;
7833
7834 /* Ignore early vblank irqs */
7835 if (intel_crtc == NULL)
7836 return;
7837
7838 spin_lock_irqsave(&dev->event_lock, flags);
7839 work = intel_crtc->unpin_work;
e7d841ca
CW		 7840
7841 /* Ensure we don't miss a work->pending update ... */
7842 smp_rmb();
7843
7844 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7845 spin_unlock_irqrestore(&dev->event_lock, flags);
7846 return;
7847 }
7848
e7d841ca
CW		 7849 /* and that the unpin work is consistent wrt ->pending. */
7850 smp_rmb();
7851
6b95a207 7852 intel_crtc->unpin_work = NULL;
6b95a207 7853
45a066eb
RC		 7854 if (work->event)
7855 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7856
0af7e4df
MK		 7857 drm_vblank_put(dev, intel_crtc->pipe);
7858
6b95a207
KH		 7859 spin_unlock_irqrestore(&dev->event_lock, flags);
7860
2c10d571 7861 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7862
7863 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7864
7865 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7866}
7867
1afe3e9d
JB		 7868void intel_finish_page_flip(struct drm_device *dev, int pipe)
7869{
7870 drm_i915_private_t *dev_priv = dev->dev_private;
7871 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7872
49b14a5c 7873 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7874}
7875
7876void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7877{
7878 drm_i915_private_t *dev_priv = dev->dev_private;
7879 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7880
49b14a5c 7881 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7882}
7883
6b95a207
KH		 7884void intel_prepare_page_flip(struct drm_device *dev, int plane)
7885{
7886 drm_i915_private_t *dev_priv = dev->dev_private;
7887 struct intel_crtc *intel_crtc =
7888 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7889 unsigned long flags;
7890
e7d841ca
CW		 7891 /* NB: An MMIO update of the plane base pointer will also
7892 * generate a page-flip completion irq, i.e. every modeset
7893 * is also accompanied by a spurious intel_prepare_page_flip().
7894 */
6b95a207 7895 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7896 if (intel_crtc->unpin_work)
7897 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7898 spin_unlock_irqrestore(&dev->event_lock, flags);
7899}
7900
e7d841ca
CW		 7901inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7902{
7903 /* Ensure that the work item is consistent when activating it ... */
7904 smp_wmb();
7905 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7906 /* and that it is marked active as soon as the irq could fire. */
7907 smp_wmb();
7908}
7909
8c9f3aaf
JB		 7910static int intel_gen2_queue_flip(struct drm_device *dev,
7911 struct drm_crtc *crtc,
7912 struct drm_framebuffer *fb,
ed8d1975
KP		 7913 struct drm_i915_gem_object *obj,
7914 uint32_t flags)
8c9f3aaf
JB		 7915{
7916 struct drm_i915_private *dev_priv = dev->dev_private;
7917 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7918 u32 flip_mask;
6d90c952 7919 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7920 int ret;
7921
6d90c952 7922 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7923 if (ret)
83d4092b 7924 goto err;
8c9f3aaf 7925
6d90c952 7926 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7927 if (ret)
83d4092b 7928 goto err_unpin;
8c9f3aaf
JB		 7929
7930 /* Can't queue multiple flips, so wait for the previous
7931 * one to finish before executing the next.
7932 */
7933 if (intel_crtc->plane)
7934 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7935 else
7936 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7937 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7938 intel_ring_emit(ring, MI_NOOP);
7939 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7940 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7941 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7942 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952 7943 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7944
7945 intel_mark_page_flip_active(intel_crtc);
09246732 7946 __intel_ring_advance(ring);
83d4092b
CW		 7947 return 0;
7948
7949err_unpin:
7950 intel_unpin_fb_obj(obj);
7951err:
8c9f3aaf
JB		 7952 return ret;
7953}
7954
7955static int intel_gen3_queue_flip(struct drm_device *dev,
7956 struct drm_crtc *crtc,
7957 struct drm_framebuffer *fb,
ed8d1975
KP		 7958 struct drm_i915_gem_object *obj,
7959 uint32_t flags)
8c9f3aaf
JB		 7960{
7961 struct drm_i915_private *dev_priv = dev->dev_private;
7962 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7963 u32 flip_mask;
6d90c952 7964 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7965 int ret;
7966
6d90c952 7967 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7968 if (ret)
83d4092b 7969 goto err;
8c9f3aaf 7970
6d90c952 7971 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7972 if (ret)
83d4092b 7973 goto err_unpin;
8c9f3aaf
JB		 7974
7975 if (intel_crtc->plane)
7976 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7977 else
7978 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7979 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7980 intel_ring_emit(ring, MI_NOOP);
7981 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7982 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7983 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7984 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952
DV		 7985 intel_ring_emit(ring, MI_NOOP);
7986
e7d841ca 7987 intel_mark_page_flip_active(intel_crtc);
09246732 7988 __intel_ring_advance(ring);
83d4092b
CW		 7989 return 0;
7990
7991err_unpin:
7992 intel_unpin_fb_obj(obj);
7993err:
8c9f3aaf
JB		 7994 return ret;
7995}
7996
7997static int intel_gen4_queue_flip(struct drm_device *dev,
7998 struct drm_crtc *crtc,
7999 struct drm_framebuffer *fb,
ed8d1975
KP		 8000 struct drm_i915_gem_object *obj,
8001 uint32_t flags)
8c9f3aaf
JB		 8002{
8003 struct drm_i915_private *dev_priv = dev->dev_private;
8004 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8005 uint32_t pf, pipesrc;
6d90c952 8006 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 8007 int ret;
8008
6d90c952 8009 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 8010 if (ret)
83d4092b 8011 goto err;
8c9f3aaf 8012
6d90c952 8013 ret = intel_ring_begin(ring, 4);
8c9f3aaf 8014 if (ret)
83d4092b 8015 goto err_unpin;
8c9f3aaf
JB		 8016
8017 /* i965+ uses the linear or tiled offsets from the
8018 * Display Registers (which do not change across a page-flip)
8019 * so we need only reprogram the base address.
8020 */
6d90c952
DV		 8021 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8022 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8023 intel_ring_emit(ring, fb->pitches[0]);
c2c75131 8024 intel_ring_emit(ring,
f343c5f6 8025 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
c2c75131 8026 obj->tiling_mode);
8c9f3aaf
JB		 8027
8028 /* XXX Enabling the panel-fitter across page-flip is so far
8029 * untested on non-native modes, so ignore it for now.
8030 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8031 */
8032 pf = 0;
8033 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 8034 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 8035
8036 intel_mark_page_flip_active(intel_crtc);
09246732 8037 __intel_ring_advance(ring);
83d4092b
CW		 8038 return 0;
8039
8040err_unpin:
8041 intel_unpin_fb_obj(obj);
8042err:
8c9f3aaf
JB		 8043 return ret;
8044}
8045
8046static int intel_gen6_queue_flip(struct drm_device *dev,
8047 struct drm_crtc *crtc,
8048 struct drm_framebuffer *fb,
ed8d1975
KP		 8049 struct drm_i915_gem_object *obj,
8050 uint32_t flags)
8c9f3aaf
JB		 8051{
8052 struct drm_i915_private *dev_priv = dev->dev_private;
8053 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 8054 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 8055 uint32_t pf, pipesrc;
8056 int ret;
8057
6d90c952 8058 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 8059 if (ret)
83d4092b 8060 goto err;
8c9f3aaf 8061
6d90c952 8062 ret = intel_ring_begin(ring, 4);
8c9f3aaf 8063 if (ret)
83d4092b 8064 goto err_unpin;
8c9f3aaf 8065
6d90c952
DV		 8066 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8067 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8068 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
f343c5f6 8069 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8c9f3aaf 8070
dc257cf1
DV		 8071 /* Contrary to the suggestions in the documentation,
8072 * "Enable Panel Fitter" does not seem to be required when page
8073 * flipping with a non-native mode, and worse causes a normal
8074 * modeset to fail.
8075 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8076 */
8077 pf = 0;
8c9f3aaf 8078 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 8079 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 8080
8081 intel_mark_page_flip_active(intel_crtc);
09246732 8082 __intel_ring_advance(ring);
83d4092b
CW		 8083 return 0;
8084
8085err_unpin:
8086 intel_unpin_fb_obj(obj);
8087err:
8c9f3aaf
JB		 8088 return ret;
8089}
8090
7c9017e5
JB		 8091static int intel_gen7_queue_flip(struct drm_device *dev,
8092 struct drm_crtc *crtc,
8093 struct drm_framebuffer *fb,
ed8d1975
KP		 8094 struct drm_i915_gem_object *obj,
8095 uint32_t flags)
7c9017e5
JB		 8096{
8097 struct drm_i915_private *dev_priv = dev->dev_private;
8098 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ffe74d75 8099 struct intel_ring_buffer *ring;
cb05d8de 8100 uint32_t plane_bit = 0;
ffe74d75
CW		 8101 int len, ret;
8102
8103 ring = obj->ring;
1c5fd085 8104 if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
ffe74d75 8105 ring = &dev_priv->ring[BCS];
7c9017e5
JB		 8106
8107 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8108 if (ret)
83d4092b 8109 goto err;
7c9017e5 8110
cb05d8de
DV		 8111 switch(intel_crtc->plane) {
8112 case PLANE_A:
8113 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8114 break;
8115 case PLANE_B:
8116 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8117 break;
8118 case PLANE_C:
8119 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8120 break;
8121 default:
8122 WARN_ONCE(1, "unknown plane in flip command\n");
8123 ret = -ENODEV;
ab3951eb 8124 goto err_unpin;
cb05d8de
DV		 8125 }
8126
ffe74d75
CW		 8127 len = 4;
8128 if (ring->id == RCS)
8129 len += 6;
8130
8131 ret = intel_ring_begin(ring, len);
7c9017e5 8132 if (ret)
83d4092b 8133 goto err_unpin;
7c9017e5 8134
ffe74d75
CW		 8135 /* Unmask the flip-done completion message. Note that the bspec says that
8136 * we should do this for both the BCS and RCS, and that we must not unmask
8137 * more than one flip event at any time (or ensure that one flip message
8138 * can be sent by waiting for flip-done prior to queueing new flips).
8139 * Experimentation says that BCS works despite DERRMR masking all
8140 * flip-done completion events and that unmasking all planes at once
8141 * for the RCS also doesn't appear to drop events. Setting the DERRMR
8142 * to zero does lead to lockups within MI_DISPLAY_FLIP.
8143 */
8144 if (ring->id == RCS) {
8145 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8146 intel_ring_emit(ring, DERRMR);
8147 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8148 DERRMR_PIPEB_PRI_FLIP_DONE |
8149 DERRMR_PIPEC_PRI_FLIP_DONE));
8150 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
8151 intel_ring_emit(ring, DERRMR);
8152 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8153 }
8154
cb05d8de 8155 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 8156 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
f343c5f6 8157 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7c9017e5 8158 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 8159
8160 intel_mark_page_flip_active(intel_crtc);
09246732 8161 __intel_ring_advance(ring);
83d4092b
CW		 8162 return 0;
8163
8164err_unpin:
8165 intel_unpin_fb_obj(obj);
8166err:
7c9017e5
JB		 8167 return ret;
8168}
8169
8c9f3aaf
JB		 8170static int intel_default_queue_flip(struct drm_device *dev,
8171 struct drm_crtc *crtc,
8172 struct drm_framebuffer *fb,
ed8d1975
KP		 8173 struct drm_i915_gem_object *obj,
8174 uint32_t flags)
8c9f3aaf
JB		 8175{
8176 return -ENODEV;
8177}
8178
6b95a207
KH		 8179static int intel_crtc_page_flip(struct drm_crtc *crtc,
8180 struct drm_framebuffer *fb,
ed8d1975
KP		 8181 struct drm_pending_vblank_event *event,
8182 uint32_t page_flip_flags)
6b95a207
KH		 8183{
8184 struct drm_device *dev = crtc->dev;
8185 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 8186 struct drm_framebuffer *old_fb = crtc->fb;
8187 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 8188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8189 struct intel_unpin_work *work;
8c9f3aaf 8190 unsigned long flags;
52e68630 8191 int ret;
6b95a207 8192
e6a595d2
VS		 8193 /* Can't change pixel format via MI display flips. */
8194 if (fb->pixel_format != crtc->fb->pixel_format)
8195 return -EINVAL;
8196
8197 /*
8198 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8199 * Note that pitch changes could also affect these register.
8200 */
8201 if (INTEL_INFO(dev)->gen > 3 &&
8202 (fb->offsets[0] != crtc->fb->offsets[0] ||
8203 fb->pitches[0] != crtc->fb->pitches[0]))
8204 return -EINVAL;
8205
b14c5679 8206 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 8207 if (work == NULL)
8208 return -ENOMEM;
8209
6b95a207 8210 work->event = event;
b4a98e57 8211 work->crtc = crtc;
4a35f83b 8212 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 8213 INIT_WORK(&work->work, intel_unpin_work_fn);
8214
7317c75e
JB		 8215 ret = drm_vblank_get(dev, intel_crtc->pipe);
8216 if (ret)
8217 goto free_work;
8218
6b95a207
KH		 8219 /* We borrow the event spin lock for protecting unpin_work */
8220 spin_lock_irqsave(&dev->event_lock, flags);
8221 if (intel_crtc->unpin_work) {
8222 spin_unlock_irqrestore(&dev->event_lock, flags);
8223 kfree(work);
7317c75e 8224 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 8225
8226 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 8227 return -EBUSY;
8228 }
8229 intel_crtc->unpin_work = work;
8230 spin_unlock_irqrestore(&dev->event_lock, flags);
8231
b4a98e57
CW		 8232 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8233 flush_workqueue(dev_priv->wq);
8234
79158103
CW		 8235 ret = i915_mutex_lock_interruptible(dev);
8236 if (ret)
8237 goto cleanup;
6b95a207 8238
75dfca80 8239 /* Reference the objects for the scheduled work. */
05394f39
CW		 8240 drm_gem_object_reference(&work->old_fb_obj->base);
8241 drm_gem_object_reference(&obj->base);
6b95a207
KH		 8242
8243 crtc->fb = fb;
96b099fd 8244
e1f99ce6 8245 work->pending_flip_obj = obj;
e1f99ce6 8246
4e5359cd
SF		 8247 work->enable_stall_check = true;
8248
b4a98e57 8249 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 8250 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 8251
ed8d1975 8252 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8c9f3aaf
JB		 8253 if (ret)
8254 goto cleanup_pending;
6b95a207 8255
7782de3b 8256 intel_disable_fbc(dev);
c65355bb 8257 intel_mark_fb_busy(obj, NULL);
6b95a207
KH		 8258 mutex_unlock(&dev->struct_mutex);
8259
e5510fac
JB		 8260 trace_i915_flip_request(intel_crtc->plane, obj);
8261
6b95a207 8262 return 0;
96b099fd 8263
8c9f3aaf 8264cleanup_pending:
b4a98e57 8265 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 8266 crtc->fb = old_fb;
05394f39
CW		 8267 drm_gem_object_unreference(&work->old_fb_obj->base);
8268 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 8269 mutex_unlock(&dev->struct_mutex);
8270
79158103 8271cleanup:
96b099fd
CW		 8272 spin_lock_irqsave(&dev->event_lock, flags);
8273 intel_crtc->unpin_work = NULL;
8274 spin_unlock_irqrestore(&dev->event_lock, flags);
8275
7317c75e
JB		 8276 drm_vblank_put(dev, intel_crtc->pipe);
8277free_work:
96b099fd
CW		 8278 kfree(work);
8279
8280 return ret;
6b95a207
KH		 8281}
8282
f6e5b160 8283static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 8284 .mode_set_base_atomic = intel_pipe_set_base_atomic,
8285 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 8286};
8287
50f56119
DV		 8288static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8289 struct drm_crtc *crtc)
8290{
8291 struct drm_device *dev;
8292 struct drm_crtc *tmp;
8293 int crtc_mask = 1;
47f1c6c9 8294
50f56119 8295 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 8296
50f56119 8297 dev = crtc->dev;
47f1c6c9 8298
50f56119
DV		 8299 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8300 if (tmp == crtc)
8301 break;
8302 crtc_mask <<= 1;
8303 }
47f1c6c9 8304
50f56119
DV		 8305 if (encoder->possible_crtcs & crtc_mask)
8306 return true;
8307 return false;
47f1c6c9 8308}
79e53945 8309
9a935856
DV		 8310/**
8311 * intel_modeset_update_staged_output_state
8312 *
8313 * Updates the staged output configuration state, e.g. after we've read out the
8314 * current hw state.
8315 */
8316static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 8317{
9a935856
DV		 8318 struct intel_encoder *encoder;
8319 struct intel_connector *connector;
f6e5b160 8320
9a935856
DV		 8321 list_for_each_entry(connector, &dev->mode_config.connector_list,
8322 base.head) {
8323 connector->new_encoder =
8324 to_intel_encoder(connector->base.encoder);
8325 }
f6e5b160 8326
9a935856
DV		 8327 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8328 base.head) {
8329 encoder->new_crtc =
8330 to_intel_crtc(encoder->base.crtc);
8331 }
f6e5b160
CW		 8332}
8333
9a935856
DV		 8334/**
8335 * intel_modeset_commit_output_state
8336 *
8337 * This function copies the stage display pipe configuration to the real one.
8338 */
8339static void intel_modeset_commit_output_state(struct drm_device *dev)
8340{
8341 struct intel_encoder *encoder;
8342 struct intel_connector *connector;
f6e5b160 8343
9a935856
DV		 8344 list_for_each_entry(connector, &dev->mode_config.connector_list,
8345 base.head) {
8346 connector->base.encoder = &connector->new_encoder->base;
8347 }
f6e5b160 8348
9a935856
DV		 8349 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8350 base.head) {
8351 encoder->base.crtc = &encoder->new_crtc->base;
8352 }
8353}
8354
050f7aeb
DV		 8355static void
8356connected_sink_compute_bpp(struct intel_connector * connector,
8357 struct intel_crtc_config *pipe_config)
8358{
8359 int bpp = pipe_config->pipe_bpp;
8360
8361 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8362 connector->base.base.id,
8363 drm_get_connector_name(&connector->base));
8364
8365 /* Don't use an invalid EDID bpc value */
8366 if (connector->base.display_info.bpc &&
8367 connector->base.display_info.bpc * 3 < bpp) {
8368 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8369 bpp, connector->base.display_info.bpc*3);
8370 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8371 }
8372
8373 /* Clamp bpp to 8 on screens without EDID 1.4 */
8374 if (connector->base.display_info.bpc == 0 && bpp > 24) {
8375 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8376 bpp);
8377 pipe_config->pipe_bpp = 24;
8378 }
8379}
8380
4e53c2e0 8381static int
050f7aeb
DV		 8382compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8383 struct drm_framebuffer *fb,
8384 struct intel_crtc_config *pipe_config)
4e53c2e0 8385{
050f7aeb
DV		 8386 struct drm_device *dev = crtc->base.dev;
8387 struct intel_connector *connector;
4e53c2e0
DV		 8388 int bpp;
8389
d42264b1
DV		 8390 switch (fb->pixel_format) {
8391 case DRM_FORMAT_C8:
4e53c2e0
DV		 8392 bpp = 8*3; /* since we go through a colormap */
8393 break;
d42264b1
DV		 8394 case DRM_FORMAT_XRGB1555:
8395 case DRM_FORMAT_ARGB1555:
8396 /* checked in intel_framebuffer_init already */
8397 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8398 return -EINVAL;
8399 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 8400 bpp = 6*3; /* min is 18bpp */
8401 break;
d42264b1
DV		 8402 case DRM_FORMAT_XBGR8888:
8403 case DRM_FORMAT_ABGR8888:
8404 /* checked in intel_framebuffer_init already */
8405 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8406 return -EINVAL;
8407 case DRM_FORMAT_XRGB8888:
8408 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 8409 bpp = 8*3;
8410 break;
d42264b1
DV		 8411 case DRM_FORMAT_XRGB2101010:
8412 case DRM_FORMAT_ARGB2101010:
8413 case DRM_FORMAT_XBGR2101010:
8414 case DRM_FORMAT_ABGR2101010:
8415 /* checked in intel_framebuffer_init already */
8416 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 8417 return -EINVAL;
4e53c2e0
DV		 8418 bpp = 10*3;
8419 break;
baba133a 8420 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 8421 default:
8422 DRM_DEBUG_KMS("unsupported depth\n");
8423 return -EINVAL;
8424 }
8425
4e53c2e0
DV		 8426 pipe_config->pipe_bpp = bpp;
8427
8428 /* Clamp display bpp to EDID value */
8429 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 8430 base.head) {
1b829e05
DV		 8431 if (!connector->new_encoder ||
8432 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 8433 continue;
8434
050f7aeb 8435 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 8436 }
8437
8438 return bpp;
8439}
8440
644db711
DV		 8441static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
8442{
8443 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8444 "type: 0x%x flags: 0x%x\n",
1342830c 8445 mode->crtc_clock,
644db711
DV		 8446 mode->crtc_hdisplay, mode->crtc_hsync_start,
8447 mode->crtc_hsync_end, mode->crtc_htotal,
8448 mode->crtc_vdisplay, mode->crtc_vsync_start,
8449 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
8450}
8451
c0b03411
DV		 8452static void intel_dump_pipe_config(struct intel_crtc *crtc,
8453 struct intel_crtc_config *pipe_config,
8454 const char *context)
8455{
8456 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8457 context, pipe_name(crtc->pipe));
8458
8459 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8460 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8461 pipe_config->pipe_bpp, pipe_config->dither);
8462 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8463 pipe_config->has_pch_encoder,
8464 pipe_config->fdi_lanes,
8465 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8466 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8467 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 8468 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8469 pipe_config->has_dp_encoder,
8470 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8471 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8472 pipe_config->dp_m_n.tu);
c0b03411
DV		 8473 DRM_DEBUG_KMS("requested mode:\n");
8474 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8475 DRM_DEBUG_KMS("adjusted mode:\n");
8476 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
644db711 8477 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
d71b8d4a 8478 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 8479 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8480 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
c0b03411
DV		 8481 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8482 pipe_config->gmch_pfit.control,
8483 pipe_config->gmch_pfit.pgm_ratios,
8484 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 8485 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 8486 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 8487 pipe_config->pch_pfit.size,
8488 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 8489 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 8490 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
c0b03411
DV		 8491}
8492
accfc0c5
DV		 8493static bool check_encoder_cloning(struct drm_crtc *crtc)
8494{
8495 int num_encoders = 0;
8496 bool uncloneable_encoders = false;
8497 struct intel_encoder *encoder;
8498
8499 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8500 base.head) {
8501 if (&encoder->new_crtc->base != crtc)
8502 continue;
8503
8504 num_encoders++;
8505 if (!encoder->cloneable)
8506 uncloneable_encoders = true;
8507 }
8508
8509 return !(num_encoders > 1 && uncloneable_encoders);
8510}
8511
b8cecdf5
DV		 8512static struct intel_crtc_config *
8513intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 8514 struct drm_framebuffer *fb,
b8cecdf5 8515 struct drm_display_mode *mode)
ee7b9f93 8516{
7758a113 8517 struct drm_device *dev = crtc->dev;
7758a113 8518 struct intel_encoder *encoder;
b8cecdf5 8519 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 8520 int plane_bpp, ret = -EINVAL;
8521 bool retry = true;
ee7b9f93 8522
accfc0c5
DV		 8523 if (!check_encoder_cloning(crtc)) {
8524 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8525 return ERR_PTR(-EINVAL);
8526 }
8527
b8cecdf5
DV		 8528 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8529 if (!pipe_config)
7758a113
DV		 8530 return ERR_PTR(-ENOMEM);
8531
b8cecdf5
DV		 8532 drm_mode_copy(&pipe_config->adjusted_mode, mode);
8533 drm_mode_copy(&pipe_config->requested_mode, mode);
37327abd 8534
e143a21c
DV		 8535 pipe_config->cpu_transcoder =
8536 (enum transcoder) to_intel_crtc(crtc)->pipe;
c0d43d62 8537 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 8538
2960bc9c
ID		 8539 /*
8540 * Sanitize sync polarity flags based on requested ones. If neither
8541 * positive or negative polarity is requested, treat this as meaning
8542 * negative polarity.
8543 */
8544 if (!(pipe_config->adjusted_mode.flags &
8545 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8546 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8547
8548 if (!(pipe_config->adjusted_mode.flags &
8549 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8550 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8551
050f7aeb
DV		 8552 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8553 * plane pixel format and any sink constraints into account. Returns the
8554 * source plane bpp so that dithering can be selected on mismatches
8555 * after encoders and crtc also have had their say. */
8556 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8557 fb, pipe_config);
4e53c2e0
DV		 8558 if (plane_bpp < 0)
8559 goto fail;
8560
e41a56be
VS		 8561 /*
8562 * Determine the real pipe dimensions. Note that stereo modes can
8563 * increase the actual pipe size due to the frame doubling and
8564 * insertion of additional space for blanks between the frame. This
8565 * is stored in the crtc timings. We use the requested mode to do this
8566 * computation to clearly distinguish it from the adjusted mode, which
8567 * can be changed by the connectors in the below retry loop.
8568 */
8569 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
8570 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
8571 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
8572
e29c22c0 8573encoder_retry:
ef1b460d 8574 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 8575 pipe_config->port_clock = 0;
ef1b460d 8576 pipe_config->pixel_multiplier = 1;
ff9a6750 8577
135c81b8 8578 /* Fill in default crtc timings, allow encoders to overwrite them. */
6ce70f5e 8579 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
135c81b8 8580
7758a113
DV		 8581 /* Pass our mode to the connectors and the CRTC to give them a chance to
8582 * adjust it according to limitations or connector properties, and also
8583 * a chance to reject the mode entirely.
47f1c6c9 8584 */
7758a113
DV		 8585 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8586 base.head) {
47f1c6c9 8587
7758a113
DV		 8588 if (&encoder->new_crtc->base != crtc)
8589 continue;
7ae89233 8590
efea6e8e
DV		 8591 if (!(encoder->compute_config(encoder, pipe_config))) {
8592 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 8593 goto fail;
8594 }
ee7b9f93 8595 }
47f1c6c9 8596
ff9a6750
DV		 8597 /* Set default port clock if not overwritten by the encoder. Needs to be
8598 * done afterwards in case the encoder adjusts the mode. */
8599 if (!pipe_config->port_clock)
241bfc38
DL		 8600 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
8601 * pipe_config->pixel_multiplier;
ff9a6750 8602
a43f6e0f 8603 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 8604 if (ret < 0) {
7758a113
DV		 8605 DRM_DEBUG_KMS("CRTC fixup failed\n");
8606 goto fail;
ee7b9f93 8607 }
e29c22c0
DV		 8608
8609 if (ret == RETRY) {
8610 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8611 ret = -EINVAL;
8612 goto fail;
8613 }
8614
8615 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8616 retry = false;
8617 goto encoder_retry;
8618 }
8619
4e53c2e0
DV		 8620 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8621 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8622 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8623
b8cecdf5 8624 return pipe_config;
7758a113 8625fail:
b8cecdf5 8626 kfree(pipe_config);
e29c22c0 8627 return ERR_PTR(ret);
ee7b9f93 8628}
47f1c6c9 8629
e2e1ed41
DV		 8630/* Computes which crtcs are affected and sets the relevant bits in the mask. For
8631 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8632static void
8633intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8634 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 8635{
8636 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 8637 struct drm_device *dev = crtc->dev;
8638 struct intel_encoder *encoder;
8639 struct intel_connector *connector;
8640 struct drm_crtc *tmp_crtc;
79e53945 8641
e2e1ed41 8642 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 8643
e2e1ed41
DV		 8644 /* Check which crtcs have changed outputs connected to them, these need
8645 * to be part of the prepare_pipes mask. We don't (yet) support global
8646 * modeset across multiple crtcs, so modeset_pipes will only have one
8647 * bit set at most. */
8648 list_for_each_entry(connector, &dev->mode_config.connector_list,
8649 base.head) {
8650 if (connector->base.encoder == &connector->new_encoder->base)
8651 continue;
79e53945 8652
e2e1ed41
DV		 8653 if (connector->base.encoder) {
8654 tmp_crtc = connector->base.encoder->crtc;
8655
8656 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8657 }
8658
8659 if (connector->new_encoder)
8660 *prepare_pipes |=
8661 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 8662 }
8663
e2e1ed41
DV		 8664 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8665 base.head) {
8666 if (encoder->base.crtc == &encoder->new_crtc->base)
8667 continue;
8668
8669 if (encoder->base.crtc) {
8670 tmp_crtc = encoder->base.crtc;
8671
8672 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8673 }
8674
8675 if (encoder->new_crtc)
8676 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 8677 }
8678
e2e1ed41
DV		 8679 /* Check for any pipes that will be fully disabled ... */
8680 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8681 base.head) {
8682 bool used = false;
22fd0fab 8683
e2e1ed41
DV		 8684 /* Don't try to disable disabled crtcs. */
8685 if (!intel_crtc->base.enabled)
8686 continue;
7e7d76c3 8687
e2e1ed41
DV		 8688 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8689 base.head) {
8690 if (encoder->new_crtc == intel_crtc)
8691 used = true;
8692 }
8693
8694 if (!used)
8695 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 8696 }
8697
e2e1ed41
DV		 8698
8699 /* set_mode is also used to update properties on life display pipes. */
8700 intel_crtc = to_intel_crtc(crtc);
8701 if (crtc->enabled)
8702 *prepare_pipes |= 1 << intel_crtc->pipe;
8703
b6c5164d
DV		 8704 /*
8705 * For simplicity do a full modeset on any pipe where the output routing
8706 * changed. We could be more clever, but that would require us to be
8707 * more careful with calling the relevant encoder->mode_set functions.
8708 */
e2e1ed41
DV		 8709 if (*prepare_pipes)
8710 *modeset_pipes = *prepare_pipes;
8711
8712 /* ... and mask these out. */
8713 *modeset_pipes &= ~(*disable_pipes);
8714 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 8715
8716 /*
8717 * HACK: We don't (yet) fully support global modesets. intel_set_config
8718 * obies this rule, but the modeset restore mode of
8719 * intel_modeset_setup_hw_state does not.
8720 */
8721 *modeset_pipes &= 1 << intel_crtc->pipe;
8722 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 8723
8724 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8725 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 8726}
79e53945 8727
ea9d758d 8728static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 8729{
ea9d758d 8730 struct drm_encoder *encoder;
f6e5b160 8731 struct drm_device *dev = crtc->dev;
f6e5b160 8732
ea9d758d
DV		 8733 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8734 if (encoder->crtc == crtc)
8735 return true;
8736
8737 return false;
8738}
8739
8740static void
8741intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8742{
8743 struct intel_encoder *intel_encoder;
8744 struct intel_crtc *intel_crtc;
8745 struct drm_connector *connector;
8746
8747 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8748 base.head) {
8749 if (!intel_encoder->base.crtc)
8750 continue;
8751
8752 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8753
8754 if (prepare_pipes & (1 << intel_crtc->pipe))
8755 intel_encoder->connectors_active = false;
8756 }
8757
8758 intel_modeset_commit_output_state(dev);
8759
8760 /* Update computed state. */
8761 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8762 base.head) {
8763 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8764 }
8765
8766 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8767 if (!connector->encoder || !connector->encoder->crtc)
8768 continue;
8769
8770 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8771
8772 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8773 struct drm_property *dpms_property =
8774 dev->mode_config.dpms_property;
8775
ea9d758d 8776 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8777 drm_object_property_set_value(&connector->base,
68d34720
DV		 8778 dpms_property,
8779 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8780
8781 intel_encoder = to_intel_encoder(connector->encoder);
8782 intel_encoder->connectors_active = true;
8783 }
8784 }
8785
8786}
8787
3bd26263 8788static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 8789{
3bd26263 8790 int diff;
f1f644dc
JB		 8791
8792 if (clock1 == clock2)
8793 return true;
8794
8795 if (!clock1 || !clock2)
8796 return false;
8797
8798 diff = abs(clock1 - clock2);
8799
8800 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8801 return true;
8802
8803 return false;
8804}
8805
25c5b266
DV		 8806#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8807 list_for_each_entry((intel_crtc), \
8808 &(dev)->mode_config.crtc_list, \
8809 base.head) \
0973f18f 8810 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8811
0e8ffe1b 8812static bool
2fa2fe9a
DV		 8813intel_pipe_config_compare(struct drm_device *dev,
8814 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8815 struct intel_crtc_config *pipe_config)
8816{
66e985c0
DV		 8817#define PIPE_CONF_CHECK_X(name) \
8818 if (current_config->name != pipe_config->name) { \
8819 DRM_ERROR("mismatch in " #name " " \
8820 "(expected 0x%08x, found 0x%08x)\n", \
8821 current_config->name, \
8822 pipe_config->name); \
8823 return false; \
8824 }
8825
08a24034
DV		 8826#define PIPE_CONF_CHECK_I(name) \
8827 if (current_config->name != pipe_config->name) { \
8828 DRM_ERROR("mismatch in " #name " " \
8829 "(expected %i, found %i)\n", \
8830 current_config->name, \
8831 pipe_config->name); \
8832 return false; \
88adfff1
DV		 8833 }
8834
1bd1bd80
DV		 8835#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8836 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 8837 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 8838 "(expected %i, found %i)\n", \
8839 current_config->name & (mask), \
8840 pipe_config->name & (mask)); \
8841 return false; \
8842 }
8843
5e550656
VS		 8844#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
8845 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
8846 DRM_ERROR("mismatch in " #name " " \
8847 "(expected %i, found %i)\n", \
8848 current_config->name, \
8849 pipe_config->name); \
8850 return false; \
8851 }
8852
bb760063
DV		 8853#define PIPE_CONF_QUIRK(quirk) \
8854 ((current_config->quirks | pipe_config->quirks) & (quirk))
8855
eccb140b
DV		 8856 PIPE_CONF_CHECK_I(cpu_transcoder);
8857
08a24034
DV		 8858 PIPE_CONF_CHECK_I(has_pch_encoder);
8859 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8860 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8861 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8862 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8863 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8864 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8865
eb14cb74
VS		 8866 PIPE_CONF_CHECK_I(has_dp_encoder);
8867 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
8868 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
8869 PIPE_CONF_CHECK_I(dp_m_n.link_m);
8870 PIPE_CONF_CHECK_I(dp_m_n.link_n);
8871 PIPE_CONF_CHECK_I(dp_m_n.tu);
8872
1bd1bd80
DV		 8873 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8874 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8875 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8876 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8877 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8878 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8879
8880 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8881 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8882 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8883 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8884 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8885 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8886
c93f54cf 8887 PIPE_CONF_CHECK_I(pixel_multiplier);
6c49f241 8888
1bd1bd80
DV		 8889 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8890 DRM_MODE_FLAG_INTERLACE);
8891
bb760063
DV		 8892 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8893 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8894 DRM_MODE_FLAG_PHSYNC);
8895 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8896 DRM_MODE_FLAG_NHSYNC);
8897 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8898 DRM_MODE_FLAG_PVSYNC);
8899 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8900 DRM_MODE_FLAG_NVSYNC);
8901 }
045ac3b5 8902
37327abd
VS		 8903 PIPE_CONF_CHECK_I(pipe_src_w);
8904 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 8905
2fa2fe9a
DV		 8906 PIPE_CONF_CHECK_I(gmch_pfit.control);
8907 /* pfit ratios are autocomputed by the hw on gen4+ */
8908 if (INTEL_INFO(dev)->gen < 4)
8909 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8910 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
fd4daa9c
CW		 8911 PIPE_CONF_CHECK_I(pch_pfit.enabled);
8912 if (current_config->pch_pfit.enabled) {
8913 PIPE_CONF_CHECK_I(pch_pfit.pos);
8914 PIPE_CONF_CHECK_I(pch_pfit.size);
8915 }
2fa2fe9a 8916
42db64ef
PZ		 8917 PIPE_CONF_CHECK_I(ips_enabled);
8918
282740f7
VS		 8919 PIPE_CONF_CHECK_I(double_wide);
8920
c0d43d62 8921 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 8922 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 8923 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 8924 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8925 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
c0d43d62 8926
42571aef
VS		 8927 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
8928 PIPE_CONF_CHECK_I(pipe_bpp);
8929
d71b8d4a 8930 if (!IS_HASWELL(dev)) {
241bfc38 8931 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
d71b8d4a
VS		 8932 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
8933 }
5e550656 8934
66e985c0 8935#undef PIPE_CONF_CHECK_X
08a24034 8936#undef PIPE_CONF_CHECK_I
1bd1bd80 8937#undef PIPE_CONF_CHECK_FLAGS
5e550656 8938#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 8939#undef PIPE_CONF_QUIRK
88adfff1 8940
0e8ffe1b
DV		 8941 return true;
8942}
8943
91d1b4bd
DV		 8944static void
8945check_connector_state(struct drm_device *dev)
8af6cf88 8946{
8af6cf88
DV		 8947 struct intel_connector *connector;
8948
8949 list_for_each_entry(connector, &dev->mode_config.connector_list,
8950 base.head) {
8951 /* This also checks the encoder/connector hw state with the
8952 * ->get_hw_state callbacks. */
8953 intel_connector_check_state(connector);
8954
8955 WARN(&connector->new_encoder->base != connector->base.encoder,
8956 "connector's staged encoder doesn't match current encoder\n");
8957 }
91d1b4bd
DV		 8958}
8959
8960static void
8961check_encoder_state(struct drm_device *dev)
8962{
8963 struct intel_encoder *encoder;
8964 struct intel_connector *connector;
8af6cf88
DV		 8965
8966 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8967 base.head) {
8968 bool enabled = false;
8969 bool active = false;
8970 enum pipe pipe, tracked_pipe;
8971
8972 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8973 encoder->base.base.id,
8974 drm_get_encoder_name(&encoder->base));
8975
8976 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8977 "encoder's stage crtc doesn't match current crtc\n");
8978 WARN(encoder->connectors_active && !encoder->base.crtc,
8979 "encoder's active_connectors set, but no crtc\n");
8980
8981 list_for_each_entry(connector, &dev->mode_config.connector_list,
8982 base.head) {
8983 if (connector->base.encoder != &encoder->base)
8984 continue;
8985 enabled = true;
8986 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8987 active = true;
8988 }
8989 WARN(!!encoder->base.crtc != enabled,
8990 "encoder's enabled state mismatch "
8991 "(expected %i, found %i)\n",
8992 !!encoder->base.crtc, enabled);
8993 WARN(active && !encoder->base.crtc,
8994 "active encoder with no crtc\n");
8995
8996 WARN(encoder->connectors_active != active,
8997 "encoder's computed active state doesn't match tracked active state "
8998 "(expected %i, found %i)\n", active, encoder->connectors_active);
8999
9000 active = encoder->get_hw_state(encoder, &pipe);
9001 WARN(active != encoder->connectors_active,
9002 "encoder's hw state doesn't match sw tracking "
9003 "(expected %i, found %i)\n",
9004 encoder->connectors_active, active);
9005
9006 if (!encoder->base.crtc)
9007 continue;
9008
9009 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9010 WARN(active && pipe != tracked_pipe,
9011 "active encoder's pipe doesn't match"
9012 "(expected %i, found %i)\n",
9013 tracked_pipe, pipe);
9014
9015 }
91d1b4bd
DV		 9016}
9017
9018static void
9019check_crtc_state(struct drm_device *dev)
9020{
9021 drm_i915_private_t *dev_priv = dev->dev_private;
9022 struct intel_crtc *crtc;
9023 struct intel_encoder *encoder;
9024 struct intel_crtc_config pipe_config;
8af6cf88
DV		 9025
9026 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9027 base.head) {
9028 bool enabled = false;
9029 bool active = false;
9030
045ac3b5
JB		 9031 memset(&pipe_config, 0, sizeof(pipe_config));
9032
8af6cf88
DV		 9033 DRM_DEBUG_KMS("[CRTC:%d]\n",
9034 crtc->base.base.id);
9035
9036 WARN(crtc->active && !crtc->base.enabled,
9037 "active crtc, but not enabled in sw tracking\n");
9038
9039 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9040 base.head) {
9041 if (encoder->base.crtc != &crtc->base)
9042 continue;
9043 enabled = true;
9044 if (encoder->connectors_active)
9045 active = true;
9046 }
6c49f241 9047
8af6cf88
DV		 9048 WARN(active != crtc->active,
9049 "crtc's computed active state doesn't match tracked active state "
9050 "(expected %i, found %i)\n", active, crtc->active);
9051 WARN(enabled != crtc->base.enabled,
9052 "crtc's computed enabled state doesn't match tracked enabled state "
9053 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
9054
0e8ffe1b
DV		 9055 active = dev_priv->display.get_pipe_config(crtc,
9056 &pipe_config);
d62cf62a
DV		 9057
9058 /* hw state is inconsistent with the pipe A quirk */
9059 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
9060 active = crtc->active;
9061
6c49f241
DV		 9062 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9063 base.head) {
3eaba51c 9064 enum pipe pipe;
6c49f241
DV		 9065 if (encoder->base.crtc != &crtc->base)
9066 continue;
3eaba51c
VS		 9067 if (encoder->get_config &&
9068 encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 9069 encoder->get_config(encoder, &pipe_config);
9070 }
9071
0e8ffe1b
DV		 9072 WARN(crtc->active != active,
9073 "crtc active state doesn't match with hw state "
9074 "(expected %i, found %i)\n", crtc->active, active);
9075
c0b03411
DV		 9076 if (active &&
9077 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9078 WARN(1, "pipe state doesn't match!\n");
9079 intel_dump_pipe_config(crtc, &pipe_config,
9080 "[hw state]");
9081 intel_dump_pipe_config(crtc, &crtc->config,
9082 "[sw state]");
9083 }
8af6cf88
DV		 9084 }
9085}
9086
91d1b4bd
DV		 9087static void
9088check_shared_dpll_state(struct drm_device *dev)
9089{
9090 drm_i915_private_t *dev_priv = dev->dev_private;
9091 struct intel_crtc *crtc;
9092 struct intel_dpll_hw_state dpll_hw_state;
9093 int i;
5358901f
DV		 9094
9095 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9096 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9097 int enabled_crtcs = 0, active_crtcs = 0;
9098 bool active;
9099
9100 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9101
9102 DRM_DEBUG_KMS("%s\n", pll->name);
9103
9104 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9105
9106 WARN(pll->active > pll->refcount,
9107 "more active pll users than references: %i vs %i\n",
9108 pll->active, pll->refcount);
9109 WARN(pll->active && !pll->on,
9110 "pll in active use but not on in sw tracking\n");
35c95375
DV		 9111 WARN(pll->on && !pll->active,
9112 "pll in on but not on in use in sw tracking\n");
5358901f
DV		 9113 WARN(pll->on != active,
9114 "pll on state mismatch (expected %i, found %i)\n",
9115 pll->on, active);
9116
9117 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9118 base.head) {
9119 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9120 enabled_crtcs++;
9121 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9122 active_crtcs++;
9123 }
9124 WARN(pll->active != active_crtcs,
9125 "pll active crtcs mismatch (expected %i, found %i)\n",
9126 pll->active, active_crtcs);
9127 WARN(pll->refcount != enabled_crtcs,
9128 "pll enabled crtcs mismatch (expected %i, found %i)\n",
9129 pll->refcount, enabled_crtcs);
66e985c0
DV		 9130
9131 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9132 sizeof(dpll_hw_state)),
9133 "pll hw state mismatch\n");
5358901f 9134 }
8af6cf88
DV		 9135}
9136
91d1b4bd
DV		 9137void
9138intel_modeset_check_state(struct drm_device *dev)
9139{
9140 check_connector_state(dev);
9141 check_encoder_state(dev);
9142 check_crtc_state(dev);
9143 check_shared_dpll_state(dev);
9144}
9145
18442d08
VS		 9146void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9147 int dotclock)
9148{
9149 /*
9150 * FDI already provided one idea for the dotclock.
9151 * Yell if the encoder disagrees.
9152 */
241bfc38 9153 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
18442d08 9154 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
241bfc38 9155 pipe_config->adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 9156}
9157
f30da187
DV		 9158static int __intel_set_mode(struct drm_crtc *crtc,
9159 struct drm_display_mode *mode,
9160 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 9161{
9162 struct drm_device *dev = crtc->dev;
dbf2b54e 9163 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 9164 struct drm_display_mode *saved_mode, *saved_hwmode;
9165 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 9166 struct intel_crtc *intel_crtc;
9167 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 9168 int ret = 0;
a6778b3c 9169
a1e22653 9170 saved_mode = kcalloc(2, sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 9171 if (!saved_mode)
9172 return -ENOMEM;
3ac18232 9173 saved_hwmode = saved_mode + 1;
a6778b3c 9174
e2e1ed41 9175 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 9176 &prepare_pipes, &disable_pipes);
9177
3ac18232
TG		 9178 *saved_hwmode = crtc->hwmode;
9179 *saved_mode = crtc->mode;
a6778b3c 9180
25c5b266
DV		 9181 /* Hack: Because we don't (yet) support global modeset on multiple
9182 * crtcs, we don't keep track of the new mode for more than one crtc.
9183 * Hence simply check whether any bit is set in modeset_pipes in all the
9184 * pieces of code that are not yet converted to deal with mutliple crtcs
9185 * changing their mode at the same time. */
25c5b266 9186 if (modeset_pipes) {
4e53c2e0 9187 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 9188 if (IS_ERR(pipe_config)) {
9189 ret = PTR_ERR(pipe_config);
9190 pipe_config = NULL;
9191
3ac18232 9192 goto out;
25c5b266 9193 }
c0b03411
DV		 9194 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9195 "[modeset]");
25c5b266 9196 }
a6778b3c 9197
460da916
DV		 9198 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9199 intel_crtc_disable(&intel_crtc->base);
9200
ea9d758d
DV		 9201 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9202 if (intel_crtc->base.enabled)
9203 dev_priv->display.crtc_disable(&intel_crtc->base);
9204 }
a6778b3c 9205
6c4c86f5
DV		 9206 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9207 * to set it here already despite that we pass it down the callchain.
f6e5b160 9208 */
b8cecdf5 9209 if (modeset_pipes) {
25c5b266 9210 crtc->mode = *mode;
b8cecdf5
DV		 9211 /* mode_set/enable/disable functions rely on a correct pipe
9212 * config. */
9213 to_intel_crtc(crtc)->config = *pipe_config;
9214 }
7758a113 9215
ea9d758d
DV		 9216 /* Only after disabling all output pipelines that will be changed can we
9217 * update the the output configuration. */
9218 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 9219
47fab737
DV		 9220 if (dev_priv->display.modeset_global_resources)
9221 dev_priv->display.modeset_global_resources(dev);
9222
a6778b3c
DV		 9223 /* Set up the DPLL and any encoders state that needs to adjust or depend
9224 * on the DPLL.
f6e5b160 9225 */
25c5b266 9226 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 9227 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 9228 x, y, fb);
9229 if (ret)
9230 goto done;
a6778b3c
DV		 9231 }
9232
9233 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 9234 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9235 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 9236
25c5b266
DV		 9237 if (modeset_pipes) {
9238 /* Store real post-adjustment hardware mode. */
b8cecdf5 9239 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 9240
25c5b266
DV		 9241 /* Calculate and store various constants which
9242 * are later needed by vblank and swap-completion
9243 * timestamping. They are derived from true hwmode.
9244 */
9245 drm_calc_timestamping_constants(crtc);
9246 }
a6778b3c
DV		 9247
9248 /* FIXME: add subpixel order */
9249done:
c0c36b94 9250 if (ret && crtc->enabled) {
3ac18232
TG		 9251 crtc->hwmode = *saved_hwmode;
9252 crtc->mode = *saved_mode;
a6778b3c
DV		 9253 }
9254
3ac18232 9255out:
b8cecdf5 9256 kfree(pipe_config);
3ac18232 9257 kfree(saved_mode);
a6778b3c 9258 return ret;
f6e5b160
CW		 9259}
9260
e7457a9a
DL		 9261static int intel_set_mode(struct drm_crtc *crtc,
9262 struct drm_display_mode *mode,
9263 int x, int y, struct drm_framebuffer *fb)
f30da187
DV		 9264{
9265 int ret;
9266
9267 ret = __intel_set_mode(crtc, mode, x, y, fb);
9268
9269 if (ret == 0)
9270 intel_modeset_check_state(crtc->dev);
9271
9272 return ret;
9273}
9274
c0c36b94
CW		 9275void intel_crtc_restore_mode(struct drm_crtc *crtc)
9276{
9277 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9278}
9279
25c5b266
DV		 9280#undef for_each_intel_crtc_masked
9281
d9e55608
DV		 9282static void intel_set_config_free(struct intel_set_config *config)
9283{
9284 if (!config)
9285 return;
9286
1aa4b628
DV		 9287 kfree(config->save_connector_encoders);
9288 kfree(config->save_encoder_crtcs);
d9e55608
DV		 9289 kfree(config);
9290}
9291
85f9eb71
DV		 9292static int intel_set_config_save_state(struct drm_device *dev,
9293 struct intel_set_config *config)
9294{
85f9eb71
DV		 9295 struct drm_encoder *encoder;
9296 struct drm_connector *connector;
9297 int count;
9298
1aa4b628
DV		 9299 config->save_encoder_crtcs =
9300 kcalloc(dev->mode_config.num_encoder,
9301 sizeof(struct drm_crtc *), GFP_KERNEL);
9302 if (!config->save_encoder_crtcs)
85f9eb71
DV		 9303 return -ENOMEM;
9304
1aa4b628
DV		 9305 config->save_connector_encoders =
9306 kcalloc(dev->mode_config.num_connector,
9307 sizeof(struct drm_encoder *), GFP_KERNEL);
9308 if (!config->save_connector_encoders)
85f9eb71
DV		 9309 return -ENOMEM;
9310
9311 /* Copy data. Note that driver private data is not affected.
9312 * Should anything bad happen only the expected state is
9313 * restored, not the drivers personal bookkeeping.
9314 */
85f9eb71
DV		 9315 count = 0;
9316 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 9317 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 9318 }
9319
9320 count = 0;
9321 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 9322 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 9323 }
9324
9325 return 0;
9326}
9327
9328static void intel_set_config_restore_state(struct drm_device *dev,
9329 struct intel_set_config *config)
9330{
9a935856
DV		 9331 struct intel_encoder *encoder;
9332 struct intel_connector *connector;
85f9eb71
DV		 9333 int count;
9334
85f9eb71 9335 count = 0;
9a935856
DV		 9336 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9337 encoder->new_crtc =
9338 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 9339 }
9340
9341 count = 0;
9a935856
DV		 9342 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9343 connector->new_encoder =
9344 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 9345 }
9346}
9347
e3de42b6 9348static bool
2e57f47d 9349is_crtc_connector_off(struct drm_mode_set *set)
e3de42b6
ID		 9350{
9351 int i;
9352
2e57f47d
CW		 9353 if (set->num_connectors == 0)
9354 return false;
9355
9356 if (WARN_ON(set->connectors == NULL))
9357 return false;
9358
9359 for (i = 0; i < set->num_connectors; i++)
9360 if (set->connectors[i]->encoder &&
9361 set->connectors[i]->encoder->crtc == set->crtc &&
9362 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
e3de42b6
ID		 9363 return true;
9364
9365 return false;
9366}
9367
5e2b584e
DV		 9368static void
9369intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9370 struct intel_set_config *config)
9371{
9372
9373 /* We should be able to check here if the fb has the same properties
9374 * and then just flip_or_move it */
2e57f47d
CW		 9375 if (is_crtc_connector_off(set)) {
9376 config->mode_changed = true;
e3de42b6 9377 } else if (set->crtc->fb != set->fb) {
5e2b584e
DV		 9378 /* If we have no fb then treat it as a full mode set */
9379 if (set->crtc->fb == NULL) {
319d9827
JB		 9380 struct intel_crtc *intel_crtc =
9381 to_intel_crtc(set->crtc);
9382
9383 if (intel_crtc->active && i915_fastboot) {
9384 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9385 config->fb_changed = true;
9386 } else {
9387 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9388 config->mode_changed = true;
9389 }
5e2b584e
DV		 9390 } else if (set->fb == NULL) {
9391 config->mode_changed = true;
72f4901e
DV		 9392 } else if (set->fb->pixel_format !=
9393 set->crtc->fb->pixel_format) {
5e2b584e 9394 config->mode_changed = true;
e3de42b6 9395 } else {
5e2b584e 9396 config->fb_changed = true;
e3de42b6 9397 }
5e2b584e
DV		 9398 }
9399
835c5873 9400 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 9401 config->fb_changed = true;
9402
9403 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9404 DRM_DEBUG_KMS("modes are different, full mode set\n");
9405 drm_mode_debug_printmodeline(&set->crtc->mode);
9406 drm_mode_debug_printmodeline(set->mode);
9407 config->mode_changed = true;
9408 }
a1d95703
CW		 9409
9410 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9411 set->crtc->base.id, config->mode_changed, config->fb_changed);
5e2b584e
DV		 9412}
9413
2e431051 9414static int
9a935856
DV		 9415intel_modeset_stage_output_state(struct drm_device *dev,
9416 struct drm_mode_set *set,
9417 struct intel_set_config *config)
50f56119 9418{
85f9eb71 9419 struct drm_crtc *new_crtc;
9a935856
DV		 9420 struct intel_connector *connector;
9421 struct intel_encoder *encoder;
f3f08572 9422 int ro;
50f56119 9423
9abdda74 9424 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 9425 * of connectors. For paranoia, double-check this. */
9426 WARN_ON(!set->fb && (set->num_connectors != 0));
9427 WARN_ON(set->fb && (set->num_connectors == 0));
9428
9a935856
DV		 9429 list_for_each_entry(connector, &dev->mode_config.connector_list,
9430 base.head) {
9431 /* Otherwise traverse passed in connector list and get encoders
9432 * for them. */
50f56119 9433 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 9434 if (set->connectors[ro] == &connector->base) {
9435 connector->new_encoder = connector->encoder;
50f56119
DV		 9436 break;
9437 }
9438 }
9439
9a935856
DV		 9440 /* If we disable the crtc, disable all its connectors. Also, if
9441 * the connector is on the changing crtc but not on the new
9442 * connector list, disable it. */
9443 if ((!set->fb || ro == set->num_connectors) &&
9444 connector->base.encoder &&
9445 connector->base.encoder->crtc == set->crtc) {
9446 connector->new_encoder = NULL;
9447
9448 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9449 connector->base.base.id,
9450 drm_get_connector_name(&connector->base));
9451 }
9452
9453
9454 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 9455 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 9456 config->mode_changed = true;
50f56119
DV		 9457 }
9458 }
9a935856 9459 /* connector->new_encoder is now updated for all connectors. */
50f56119 9460
9a935856 9461 /* Update crtc of enabled connectors. */
9a935856
DV		 9462 list_for_each_entry(connector, &dev->mode_config.connector_list,
9463 base.head) {
9464 if (!connector->new_encoder)
50f56119
DV		 9465 continue;
9466
9a935856 9467 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 9468
9469 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 9470 if (set->connectors[ro] == &connector->base)
50f56119
DV		 9471 new_crtc = set->crtc;
9472 }
9473
9474 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 9475 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9476 new_crtc)) {
5e2b584e 9477 return -EINVAL;
50f56119 9478 }
9a935856
DV		 9479 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9480
9481 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9482 connector->base.base.id,
9483 drm_get_connector_name(&connector->base),
9484 new_crtc->base.id);
9485 }
9486
9487 /* Check for any encoders that needs to be disabled. */
9488 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9489 base.head) {
9490 list_for_each_entry(connector,
9491 &dev->mode_config.connector_list,
9492 base.head) {
9493 if (connector->new_encoder == encoder) {
9494 WARN_ON(!connector->new_encoder->new_crtc);
9495
9496 goto next_encoder;
9497 }
9498 }
9499 encoder->new_crtc = NULL;
9500next_encoder:
9501 /* Only now check for crtc changes so we don't miss encoders
9502 * that will be disabled. */
9503 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 9504 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 9505 config->mode_changed = true;
50f56119
DV		 9506 }
9507 }
9a935856 9508 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 9509
2e431051
DV		 9510 return 0;
9511}
9512
9513static int intel_crtc_set_config(struct drm_mode_set *set)
9514{
9515 struct drm_device *dev;
2e431051
DV		 9516 struct drm_mode_set save_set;
9517 struct intel_set_config *config;
9518 int ret;
2e431051 9519
8d3e375e
DV		 9520 BUG_ON(!set);
9521 BUG_ON(!set->crtc);
9522 BUG_ON(!set->crtc->helper_private);
2e431051 9523
7e53f3a4
DV		 9524 /* Enforce sane interface api - has been abused by the fb helper. */
9525 BUG_ON(!set->mode && set->fb);
9526 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 9527
2e431051
DV		 9528 if (set->fb) {
9529 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9530 set->crtc->base.id, set->fb->base.id,
9531 (int)set->num_connectors, set->x, set->y);
9532 } else {
9533 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 9534 }
9535
9536 dev = set->crtc->dev;
9537
9538 ret = -ENOMEM;
9539 config = kzalloc(sizeof(*config), GFP_KERNEL);
9540 if (!config)
9541 goto out_config;
9542
9543 ret = intel_set_config_save_state(dev, config);
9544 if (ret)
9545 goto out_config;
9546
9547 save_set.crtc = set->crtc;
9548 save_set.mode = &set->crtc->mode;
9549 save_set.x = set->crtc->x;
9550 save_set.y = set->crtc->y;
9551 save_set.fb = set->crtc->fb;
9552
9553 /* Compute whether we need a full modeset, only an fb base update or no
9554 * change at all. In the future we might also check whether only the
9555 * mode changed, e.g. for LVDS where we only change the panel fitter in
9556 * such cases. */
9557 intel_set_config_compute_mode_changes(set, config);
9558
9a935856 9559 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 9560 if (ret)
9561 goto fail;
9562
5e2b584e 9563 if (config->mode_changed) {
c0c36b94
CW		 9564 ret = intel_set_mode(set->crtc, set->mode,
9565 set->x, set->y, set->fb);
5e2b584e 9566 } else if (config->fb_changed) {
4878cae2
VS		 9567 intel_crtc_wait_for_pending_flips(set->crtc);
9568
4f660f49 9569 ret = intel_pipe_set_base(set->crtc,
94352cf9 9570 set->x, set->y, set->fb);
50f56119
DV		 9571 }
9572
2d05eae1 9573 if (ret) {
bf67dfeb
DV		 9574 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9575 set->crtc->base.id, ret);
50f56119 9576fail:
2d05eae1 9577 intel_set_config_restore_state(dev, config);
50f56119 9578
2d05eae1
CW		 9579 /* Try to restore the config */
9580 if (config->mode_changed &&
9581 intel_set_mode(save_set.crtc, save_set.mode,
9582 save_set.x, save_set.y, save_set.fb))
9583 DRM_ERROR("failed to restore config after modeset failure\n");
9584 }
50f56119 9585
d9e55608
DV		 9586out_config:
9587 intel_set_config_free(config);
50f56119
DV		 9588 return ret;
9589}
f6e5b160
CW		 9590
9591static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 9592 .cursor_set = intel_crtc_cursor_set,
9593 .cursor_move = intel_crtc_cursor_move,
9594 .gamma_set = intel_crtc_gamma_set,
50f56119 9595 .set_config = intel_crtc_set_config,
f6e5b160
CW		 9596 .destroy = intel_crtc_destroy,
9597 .page_flip = intel_crtc_page_flip,
9598};
9599
79f689aa
PZ		 9600static void intel_cpu_pll_init(struct drm_device *dev)
9601{
affa9354 9602 if (HAS_DDI(dev))
79f689aa
PZ		 9603 intel_ddi_pll_init(dev);
9604}
9605
5358901f
DV		 9606static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9607 struct intel_shared_dpll *pll,
9608 struct intel_dpll_hw_state *hw_state)
ee7b9f93 9609{
5358901f 9610 uint32_t val;
ee7b9f93 9611
5358901f 9612 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 9613 hw_state->dpll = val;
9614 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9615 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 9616
9617 return val & DPLL_VCO_ENABLE;
9618}
9619
15bdd4cf
DV		 9620static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9621 struct intel_shared_dpll *pll)
9622{
9623 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9624 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9625}
9626
e7b903d2
DV		 9627static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9628 struct intel_shared_dpll *pll)
9629{
e7b903d2
DV		 9630 /* PCH refclock must be enabled first */
9631 assert_pch_refclk_enabled(dev_priv);
9632
15bdd4cf
DV		 9633 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9634
9635 /* Wait for the clocks to stabilize. */
9636 POSTING_READ(PCH_DPLL(pll->id));
9637 udelay(150);
9638
9639 /* The pixel multiplier can only be updated once the
9640 * DPLL is enabled and the clocks are stable.
9641 *
9642 * So write it again.
9643 */
9644 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9645 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9646 udelay(200);
9647}
9648
9649static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9650 struct intel_shared_dpll *pll)
9651{
9652 struct drm_device *dev = dev_priv->dev;
9653 struct intel_crtc *crtc;
e7b903d2
DV		 9654
9655 /* Make sure no transcoder isn't still depending on us. */
9656 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9657 if (intel_crtc_to_shared_dpll(crtc) == pll)
9658 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 9659 }
9660
15bdd4cf
DV		 9661 I915_WRITE(PCH_DPLL(pll->id), 0);
9662 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9663 udelay(200);
9664}
9665
46edb027
DV		 9666static char *ibx_pch_dpll_names[] = {
9667 "PCH DPLL A",
9668 "PCH DPLL B",
9669};
9670
7c74ade1 9671static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 9672{
e7b903d2 9673 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 9674 int i;
9675
7c74ade1 9676 dev_priv->num_shared_dpll = 2;
ee7b9f93 9677
e72f9fbf 9678 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 9679 dev_priv->shared_dplls[i].id = i;
9680 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 9681 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 9682 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9683 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 9684 dev_priv->shared_dplls[i].get_hw_state =
9685 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 9686 }
9687}
9688
7c74ade1
DV		 9689static void intel_shared_dpll_init(struct drm_device *dev)
9690{
e7b903d2 9691 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1
DV		 9692
9693 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9694 ibx_pch_dpll_init(dev);
9695 else
9696 dev_priv->num_shared_dpll = 0;
9697
9698 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9699 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9700 dev_priv->num_shared_dpll);
9701}
9702
b358d0a6 9703static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 9704{
22fd0fab 9705 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 9706 struct intel_crtc *intel_crtc;
9707 int i;
9708
955382f3 9709 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 9710 if (intel_crtc == NULL)
9711 return;
9712
9713 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9714
9715 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 9716 for (i = 0; i < 256; i++) {
9717 intel_crtc->lut_r[i] = i;
9718 intel_crtc->lut_g[i] = i;
9719 intel_crtc->lut_b[i] = i;
9720 }
9721
80824003
JB		 9722 /* Swap pipes & planes for FBC on pre-965 */
9723 intel_crtc->pipe = pipe;
9724 intel_crtc->plane = pipe;
e2e767ab 9725 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 9726 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 9727 intel_crtc->plane = !pipe;
80824003
JB		 9728 }
9729
22fd0fab
JB		 9730 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9731 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9732 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9733 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9734
79e53945 9735 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 9736}
9737
08d7b3d1 9738int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 9739 struct drm_file *file)
08d7b3d1 9740{
08d7b3d1 9741 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 9742 struct drm_mode_object *drmmode_obj;
9743 struct intel_crtc *crtc;
08d7b3d1 9744
1cff8f6b
DV		 9745 if (!drm_core_check_feature(dev, DRIVER_MODESET))
9746 return -ENODEV;
08d7b3d1 9747
c05422d5
DV		 9748 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9749 DRM_MODE_OBJECT_CRTC);
08d7b3d1 9750
c05422d5 9751 if (!drmmode_obj) {
08d7b3d1
CW		 9752 DRM_ERROR("no such CRTC id\n");
9753 return -EINVAL;
9754 }
9755
c05422d5
DV		 9756 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9757 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 9758
c05422d5 9759 return 0;
08d7b3d1
CW		 9760}
9761
66a9278e 9762static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 9763{
66a9278e
DV		 9764 struct drm_device *dev = encoder->base.dev;
9765 struct intel_encoder *source_encoder;
79e53945 9766 int index_mask = 0;
79e53945
JB		 9767 int entry = 0;
9768
66a9278e
DV		 9769 list_for_each_entry(source_encoder,
9770 &dev->mode_config.encoder_list, base.head) {
9771
9772 if (encoder == source_encoder)
79e53945 9773 index_mask |= (1 << entry);
66a9278e
DV		 9774
9775 /* Intel hw has only one MUX where enocoders could be cloned. */
9776 if (encoder->cloneable && source_encoder->cloneable)
9777 index_mask |= (1 << entry);
9778
79e53945
JB		 9779 entry++;
9780 }
4ef69c7a 9781
79e53945
JB		 9782 return index_mask;
9783}
9784
4d302442
CW		 9785static bool has_edp_a(struct drm_device *dev)
9786{
9787 struct drm_i915_private *dev_priv = dev->dev_private;
9788
9789 if (!IS_MOBILE(dev))
9790 return false;
9791
9792 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9793 return false;
9794
9795 if (IS_GEN5(dev) &&
9796 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9797 return false;
9798
9799 return true;
9800}
9801
79e53945
JB		 9802static void intel_setup_outputs(struct drm_device *dev)
9803{
725e30ad 9804 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 9805 struct intel_encoder *encoder;
cb0953d7 9806 bool dpd_is_edp = false;
79e53945 9807
c9093354 9808 intel_lvds_init(dev);
79e53945 9809
c40c0f5b 9810 if (!IS_ULT(dev))
79935fca 9811 intel_crt_init(dev);
cb0953d7 9812
affa9354 9813 if (HAS_DDI(dev)) {
0e72a5b5
ED		 9814 int found;
9815
9816 /* Haswell uses DDI functions to detect digital outputs */
9817 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9818 /* DDI A only supports eDP */
9819 if (found)
9820 intel_ddi_init(dev, PORT_A);
9821
9822 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9823 * register */
9824 found = I915_READ(SFUSE_STRAP);
9825
9826 if (found & SFUSE_STRAP_DDIB_DETECTED)
9827 intel_ddi_init(dev, PORT_B);
9828 if (found & SFUSE_STRAP_DDIC_DETECTED)
9829 intel_ddi_init(dev, PORT_C);
9830 if (found & SFUSE_STRAP_DDID_DETECTED)
9831 intel_ddi_init(dev, PORT_D);
9832 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 9833 int found;
270b3042
DV		 9834 dpd_is_edp = intel_dpd_is_edp(dev);
9835
9836 if (has_edp_a(dev))
9837 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 9838
dc0fa718 9839 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 9840 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 9841 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 9842 if (!found)
e2debe91 9843 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 9844 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 9845 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 9846 }
9847
dc0fa718 9848 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 9849 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 9850
dc0fa718 9851 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 9852 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 9853
5eb08b69 9854 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 9855 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 9856
270b3042 9857 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 9858 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 9859 } else if (IS_VALLEYVIEW(dev)) {
19c03924 9860 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
6f6005a5
JB		 9861 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
9862 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
9863 PORT_C);
9864 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9865 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
9866 PORT_C);
9867 }
19c03924 9868
dc0fa718 9869 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 9870 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9871 PORT_B);
67cfc203
VS		 9872 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9873 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 9874 }
3cfca973
JN		 9875
9876 intel_dsi_init(dev);
103a196f 9877 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 9878 bool found = false;
7d57382e 9879
e2debe91 9880 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9881 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 9882 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 9883 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9884 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 9885 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 9886 }
27185ae1 9887
e7281eab 9888 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9889 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 9890 }
13520b05
KH		 9891
9892 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 9893
e2debe91 9894 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9895 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 9896 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 9897 }
27185ae1 9898
e2debe91 9899 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 9900
b01f2c3a
JB		 9901 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9902 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 9903 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 9904 }
e7281eab 9905 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9906 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 9907 }
27185ae1 9908
b01f2c3a 9909 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 9910 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 9911 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 9912 } else if (IS_GEN2(dev))
79e53945
JB		 9913 intel_dvo_init(dev);
9914
103a196f 9915 if (SUPPORTS_TV(dev))
79e53945
JB		 9916 intel_tv_init(dev);
9917
4ef69c7a
CW		 9918 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9919 encoder->base.possible_crtcs = encoder->crtc_mask;
9920 encoder->base.possible_clones =
66a9278e 9921 intel_encoder_clones(encoder);
79e53945 9922 }
47356eb6 9923
dde86e2d 9924 intel_init_pch_refclk(dev);
270b3042
DV		 9925
9926 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 9927}
9928
ddfe1567
CW		 9929void intel_framebuffer_fini(struct intel_framebuffer *fb)
9930{
9931 drm_framebuffer_cleanup(&fb->base);
9932 drm_gem_object_unreference_unlocked(&fb->obj->base);
9933}
9934
79e53945
JB		 9935static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9936{
9937 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 9938
ddfe1567 9939 intel_framebuffer_fini(intel_fb);
79e53945
JB		 9940 kfree(intel_fb);
9941}
9942
9943static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 9944 struct drm_file *file,
79e53945
JB		 9945 unsigned int *handle)
9946{
9947 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 9948 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 9949
05394f39 9950 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 9951}
9952
9953static const struct drm_framebuffer_funcs intel_fb_funcs = {
9954 .destroy = intel_user_framebuffer_destroy,
9955 .create_handle = intel_user_framebuffer_create_handle,
9956};
9957
38651674
DA		 9958int intel_framebuffer_init(struct drm_device *dev,
9959 struct intel_framebuffer *intel_fb,
308e5bcb 9960 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 9961 struct drm_i915_gem_object *obj)
79e53945 9962{
a35cdaa0 9963 int pitch_limit;
79e53945
JB		 9964 int ret;
9965
c16ed4be
CW		 9966 if (obj->tiling_mode == I915_TILING_Y) {
9967 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 9968 return -EINVAL;
c16ed4be 9969 }
57cd6508 9970
c16ed4be
CW		 9971 if (mode_cmd->pitches[0] & 63) {
9972 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9973 mode_cmd->pitches[0]);
57cd6508 9974 return -EINVAL;
c16ed4be 9975 }
57cd6508 9976
a35cdaa0
CW		 9977 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9978 pitch_limit = 32*1024;
9979 } else if (INTEL_INFO(dev)->gen >= 4) {
9980 if (obj->tiling_mode)
9981 pitch_limit = 16*1024;
9982 else
9983 pitch_limit = 32*1024;
9984 } else if (INTEL_INFO(dev)->gen >= 3) {
9985 if (obj->tiling_mode)
9986 pitch_limit = 8*1024;
9987 else
9988 pitch_limit = 16*1024;
9989 } else
9990 /* XXX DSPC is limited to 4k tiled */
9991 pitch_limit = 8*1024;
9992
9993 if (mode_cmd->pitches[0] > pitch_limit) {
9994 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9995 obj->tiling_mode ? "tiled" : "linear",
9996 mode_cmd->pitches[0], pitch_limit);
5d7bd705 9997 return -EINVAL;
c16ed4be 9998 }
5d7bd705
VS		 9999
10000 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 10001 mode_cmd->pitches[0] != obj->stride) {
10002 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10003 mode_cmd->pitches[0], obj->stride);
5d7bd705 10004 return -EINVAL;
c16ed4be 10005 }
5d7bd705 10006
57779d06 10007 /* Reject formats not supported by any plane early. */
308e5bcb 10008 switch (mode_cmd->pixel_format) {
57779d06 10009 case DRM_FORMAT_C8:
04b3924d
VS		 10010 case DRM_FORMAT_RGB565:
10011 case DRM_FORMAT_XRGB8888:
10012 case DRM_FORMAT_ARGB8888:
57779d06
VS		 10013 break;
10014 case DRM_FORMAT_XRGB1555:
10015 case DRM_FORMAT_ARGB1555:
c16ed4be 10016 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 10017 DRM_DEBUG("unsupported pixel format: %s\n",
10018 drm_get_format_name(mode_cmd->pixel_format));
57779d06 10019 return -EINVAL;
c16ed4be 10020 }
57779d06
VS		 10021 break;
10022 case DRM_FORMAT_XBGR8888:
10023 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 10024 case DRM_FORMAT_XRGB2101010:
10025 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 10026 case DRM_FORMAT_XBGR2101010:
10027 case DRM_FORMAT_ABGR2101010:
c16ed4be 10028 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 10029 DRM_DEBUG("unsupported pixel format: %s\n",
10030 drm_get_format_name(mode_cmd->pixel_format));
57779d06 10031 return -EINVAL;
c16ed4be 10032 }
b5626747 10033 break;
04b3924d
VS		 10034 case DRM_FORMAT_YUYV:
10035 case DRM_FORMAT_UYVY:
10036 case DRM_FORMAT_YVYU:
10037 case DRM_FORMAT_VYUY:
c16ed4be 10038 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 10039 DRM_DEBUG("unsupported pixel format: %s\n",
10040 drm_get_format_name(mode_cmd->pixel_format));
57779d06 10041 return -EINVAL;
c16ed4be 10042 }
57cd6508
CW		 10043 break;
10044 default:
4ee62c76
VS		 10045 DRM_DEBUG("unsupported pixel format: %s\n",
10046 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 10047 return -EINVAL;
10048 }
10049
90f9a336
VS		 10050 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10051 if (mode_cmd->offsets[0] != 0)
10052 return -EINVAL;
10053
c7d73f6a
DV		 10054 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
10055 intel_fb->obj = obj;
10056
79e53945
JB		 10057 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
10058 if (ret) {
10059 DRM_ERROR("framebuffer init failed %d\n", ret);
10060 return ret;
10061 }
10062
79e53945
JB		 10063 return 0;
10064}
10065
79e53945
JB		 10066static struct drm_framebuffer *
10067intel_user_framebuffer_create(struct drm_device *dev,
10068 struct drm_file *filp,
308e5bcb 10069 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 10070{
05394f39 10071 struct drm_i915_gem_object *obj;
79e53945 10072
308e5bcb
JB		 10073 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
10074 mode_cmd->handles[0]));
c8725226 10075 if (&obj->base == NULL)
cce13ff7 10076 return ERR_PTR(-ENOENT);
79e53945 10077
d2dff872 10078 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 10079}
10080
79e53945 10081static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 10082 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 10083 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 10084};
10085
e70236a8
JB		 10086/* Set up chip specific display functions */
10087static void intel_init_display(struct drm_device *dev)
10088{
10089 struct drm_i915_private *dev_priv = dev->dev_private;
10090
ee9300bb
DV		 10091 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
10092 dev_priv->display.find_dpll = g4x_find_best_dpll;
10093 else if (IS_VALLEYVIEW(dev))
10094 dev_priv->display.find_dpll = vlv_find_best_dpll;
10095 else if (IS_PINEVIEW(dev))
10096 dev_priv->display.find_dpll = pnv_find_best_dpll;
10097 else
10098 dev_priv->display.find_dpll = i9xx_find_best_dpll;
10099
affa9354 10100 if (HAS_DDI(dev)) {
0e8ffe1b 10101 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 10102 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 10103 dev_priv->display.crtc_enable = haswell_crtc_enable;
10104 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 10105 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 10106 dev_priv->display.update_plane = ironlake_update_plane;
10107 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 10108 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 10109 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 10110 dev_priv->display.crtc_enable = ironlake_crtc_enable;
10111 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 10112 dev_priv->display.off = ironlake_crtc_off;
17638cd6 10113 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 10114 } else if (IS_VALLEYVIEW(dev)) {
10115 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10116 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10117 dev_priv->display.crtc_enable = valleyview_crtc_enable;
10118 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10119 dev_priv->display.off = i9xx_crtc_off;
10120 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 10121 } else {
0e8ffe1b 10122 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 10123 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 10124 dev_priv->display.crtc_enable = i9xx_crtc_enable;
10125 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 10126 dev_priv->display.off = i9xx_crtc_off;
17638cd6 10127 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 10128 }
e70236a8 10129
e70236a8 10130 /* Returns the core display clock speed */
25eb05fc
JB		 10131 if (IS_VALLEYVIEW(dev))
10132 dev_priv->display.get_display_clock_speed =
10133 valleyview_get_display_clock_speed;
10134 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 10135 dev_priv->display.get_display_clock_speed =
10136 i945_get_display_clock_speed;
10137 else if (IS_I915G(dev))
10138 dev_priv->display.get_display_clock_speed =
10139 i915_get_display_clock_speed;
257a7ffc 10140 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 10141 dev_priv->display.get_display_clock_speed =
10142 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 10143 else if (IS_PINEVIEW(dev))
10144 dev_priv->display.get_display_clock_speed =
10145 pnv_get_display_clock_speed;
e70236a8
JB		 10146 else if (IS_I915GM(dev))
10147 dev_priv->display.get_display_clock_speed =
10148 i915gm_get_display_clock_speed;
10149 else if (IS_I865G(dev))
10150 dev_priv->display.get_display_clock_speed =
10151 i865_get_display_clock_speed;
f0f8a9ce 10152 else if (IS_I85X(dev))
e70236a8
JB		 10153 dev_priv->display.get_display_clock_speed =
10154 i855_get_display_clock_speed;
10155 else /* 852, 830 */
10156 dev_priv->display.get_display_clock_speed =
10157 i830_get_display_clock_speed;
10158
7f8a8569 10159 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 10160 if (IS_GEN5(dev)) {
674cf967 10161 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 10162 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 10163 } else if (IS_GEN6(dev)) {
674cf967 10164 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 10165 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 10166 } else if (IS_IVYBRIDGE(dev)) {
10167 /* FIXME: detect B0+ stepping and use auto training */
10168 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 10169 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 10170 dev_priv->display.modeset_global_resources =
10171 ivb_modeset_global_resources;
c82e4d26
ED		 10172 } else if (IS_HASWELL(dev)) {
10173 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 10174 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 10175 dev_priv->display.modeset_global_resources =
10176 haswell_modeset_global_resources;
a0e63c22 10177 }
6067aaea 10178 } else if (IS_G4X(dev)) {
e0dac65e 10179 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 10180 }
8c9f3aaf
JB		 10181
10182 /* Default just returns -ENODEV to indicate unsupported */
10183 dev_priv->display.queue_flip = intel_default_queue_flip;
10184
10185 switch (INTEL_INFO(dev)->gen) {
10186 case 2:
10187 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10188 break;
10189
10190 case 3:
10191 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10192 break;
10193
10194 case 4:
10195 case 5:
10196 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10197 break;
10198
10199 case 6:
10200 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10201 break;
7c9017e5
JB		 10202 case 7:
10203 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10204 break;
8c9f3aaf 10205 }
e70236a8
JB		 10206}
10207
b690e96c
JB		 10208/*
10209 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10210 * resume, or other times. This quirk makes sure that's the case for
10211 * affected systems.
10212 */
0206e353 10213static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 10214{
10215 struct drm_i915_private *dev_priv = dev->dev_private;
10216
10217 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 10218 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 10219}
10220
435793df
KP		 10221/*
10222 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10223 */
10224static void quirk_ssc_force_disable(struct drm_device *dev)
10225{
10226 struct drm_i915_private *dev_priv = dev->dev_private;
10227 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 10228 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 10229}
10230
4dca20ef 10231/*
5a15ab5b
CE		 10232 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10233 * brightness value
4dca20ef
CE		 10234 */
10235static void quirk_invert_brightness(struct drm_device *dev)
10236{
10237 struct drm_i915_private *dev_priv = dev->dev_private;
10238 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 10239 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 10240}
10241
e85843be
KM		 10242/*
10243 * Some machines (Dell XPS13) suffer broken backlight controls if
10244 * BLM_PCH_PWM_ENABLE is set.
10245 */
10246static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
10247{
10248 struct drm_i915_private *dev_priv = dev->dev_private;
10249 dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
10250 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
10251}
10252
b690e96c
JB		 10253struct intel_quirk {
10254 int device;
10255 int subsystem_vendor;
10256 int subsystem_device;
10257 void (*hook)(struct drm_device *dev);
10258};
10259
5f85f176
EE		 10260/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10261struct intel_dmi_quirk {
10262 void (*hook)(struct drm_device *dev);
10263 const struct dmi_system_id (*dmi_id_list)[];
10264};
10265
10266static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10267{
10268 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10269 return 1;
10270}
10271
10272static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10273 {
10274 .dmi_id_list = &(const struct dmi_system_id[]) {
10275 {
10276 .callback = intel_dmi_reverse_brightness,
10277 .ident = "NCR Corporation",
10278 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10279 DMI_MATCH(DMI_PRODUCT_NAME, ""),
10280 },
10281 },
10282 { } /* terminating entry */
10283 },
10284 .hook = quirk_invert_brightness,
10285 },
10286};
10287
c43b5634 10288static struct intel_quirk intel_quirks[] = {
b690e96c 10289 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 10290 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 10291
b690e96c
JB		 10292 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10293 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10294
b690e96c
JB		 10295 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10296 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10297
ccd0d36e 10298 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 10299 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 10300 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 10301
10302 /* Lenovo U160 cannot use SSC on LVDS */
10303 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 10304
10305 /* Sony Vaio Y cannot use SSC on LVDS */
10306 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 10307
ee1452d7
JN		 10308 /*
10309 * All GM45 Acer (and its brands eMachines and Packard Bell) laptops
10310 * seem to use inverted backlight PWM.
10311 */
10312 { 0x2a42, 0x1025, PCI_ANY_ID, quirk_invert_brightness },
e85843be
KM		 10313
10314 /* Dell XPS13 HD Sandy Bridge */
10315 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10316 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10317 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
b690e96c
JB		 10318};
10319
10320static void intel_init_quirks(struct drm_device *dev)
10321{
10322 struct pci_dev *d = dev->pdev;
10323 int i;
10324
10325 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10326 struct intel_quirk *q = &intel_quirks[i];
10327
10328 if (d->device == q->device &&
10329 (d->subsystem_vendor == q->subsystem_vendor ||
10330 q->subsystem_vendor == PCI_ANY_ID) &&
10331 (d->subsystem_device == q->subsystem_device ||
10332 q->subsystem_device == PCI_ANY_ID))
10333 q->hook(dev);
10334 }
5f85f176
EE		 10335 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10336 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10337 intel_dmi_quirks[i].hook(dev);
10338 }
b690e96c
JB		 10339}
10340
9cce37f4
JB		 10341/* Disable the VGA plane that we never use */
10342static void i915_disable_vga(struct drm_device *dev)
10343{
10344 struct drm_i915_private *dev_priv = dev->dev_private;
10345 u8 sr1;
766aa1c4 10346 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 10347
10348 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 10349 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 10350 sr1 = inb(VGA_SR_DATA);
10351 outb(sr1 | 1<<5, VGA_SR_DATA);
10352 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10353 udelay(300);
10354
10355 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10356 POSTING_READ(vga_reg);
10357}
10358
6e1b4fda 10359static void i915_enable_vga_mem(struct drm_device *dev)
81b5c7bc
AW		 10360{
10361 /* Enable VGA memory on Intel HD */
10362 if (HAS_PCH_SPLIT(dev)) {
10363 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10364 outb(inb(VGA_MSR_READ) | VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10365 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10366 VGA_RSRC_LEGACY_MEM |
10367 VGA_RSRC_NORMAL_IO |
10368 VGA_RSRC_NORMAL_MEM);
10369 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10370 }
10371}
10372
6e1b4fda
VS		 10373void i915_disable_vga_mem(struct drm_device *dev)
10374{
10375 /* Disable VGA memory on Intel HD */
10376 if (HAS_PCH_SPLIT(dev)) {
10377 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10378 outb(inb(VGA_MSR_READ) & ~VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10379 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10380 VGA_RSRC_NORMAL_IO |
10381 VGA_RSRC_NORMAL_MEM);
10382 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10383 }
10384}
10385
f817586c
DV		 10386void intel_modeset_init_hw(struct drm_device *dev)
10387{
f6071166
JB		 10388 struct drm_i915_private *dev_priv = dev->dev_private;
10389
a8f78b58
ED		 10390 intel_prepare_ddi(dev);
10391
f817586c
DV		 10392 intel_init_clock_gating(dev);
10393
f6071166
JB		 10394 /* Enable the CRI clock source so we can get at the display */
10395 if (IS_VALLEYVIEW(dev))
10396 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
10397 DPLL_INTEGRATED_CRI_CLK_VLV);
10398
40e9cf64
JB		 10399 intel_init_dpio(dev);
10400
79f5b2c7 10401 mutex_lock(&dev->struct_mutex);
8090c6b9 10402 intel_enable_gt_powersave(dev);
79f5b2c7 10403 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 10404}
10405
7d708ee4
ID		 10406void intel_modeset_suspend_hw(struct drm_device *dev)
10407{
10408 intel_suspend_hw(dev);
10409}
10410
79e53945
JB		 10411void intel_modeset_init(struct drm_device *dev)
10412{
652c393a 10413 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 10414 int i, j, ret;
79e53945
JB		 10415
10416 drm_mode_config_init(dev);
10417
10418 dev->mode_config.min_width = 0;
10419 dev->mode_config.min_height = 0;
10420
019d96cb
DA		 10421 dev->mode_config.preferred_depth = 24;
10422 dev->mode_config.prefer_shadow = 1;
10423
e6ecefaa 10424 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 10425
b690e96c
JB		 10426 intel_init_quirks(dev);
10427
1fa61106
ED		 10428 intel_init_pm(dev);
10429
e3c74757
BW		 10430 if (INTEL_INFO(dev)->num_pipes == 0)
10431 return;
10432
e70236a8
JB		 10433 intel_init_display(dev);
10434
a6c45cf0
CW		 10435 if (IS_GEN2(dev)) {
10436 dev->mode_config.max_width = 2048;
10437 dev->mode_config.max_height = 2048;
10438 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 10439 dev->mode_config.max_width = 4096;
10440 dev->mode_config.max_height = 4096;
79e53945 10441 } else {
a6c45cf0
CW		 10442 dev->mode_config.max_width = 8192;
10443 dev->mode_config.max_height = 8192;
79e53945 10444 }
5d4545ae 10445 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 10446
28c97730 10447 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 10448 INTEL_INFO(dev)->num_pipes,
10449 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 10450
08e2a7de 10451 for_each_pipe(i) {
79e53945 10452 intel_crtc_init(dev, i);
7f1f3851
JB		 10453 for (j = 0; j < dev_priv->num_plane; j++) {
10454 ret = intel_plane_init(dev, i, j);
10455 if (ret)
06da8da2
VS		 10456 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10457 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 10458 }
79e53945
JB		 10459 }
10460
79f689aa 10461 intel_cpu_pll_init(dev);
e72f9fbf 10462 intel_shared_dpll_init(dev);
ee7b9f93 10463
9cce37f4
JB		 10464 /* Just disable it once at startup */
10465 i915_disable_vga(dev);
79e53945 10466 intel_setup_outputs(dev);
11be49eb
CW		 10467
10468 /* Just in case the BIOS is doing something questionable. */
10469 intel_disable_fbc(dev);
2c7111db
CW		 10470}
10471
24929352
DV		 10472static void
10473intel_connector_break_all_links(struct intel_connector *connector)
10474{
10475 connector->base.dpms = DRM_MODE_DPMS_OFF;
10476 connector->base.encoder = NULL;
10477 connector->encoder->connectors_active = false;
10478 connector->encoder->base.crtc = NULL;
10479}
10480
7fad798e
DV		 10481static void intel_enable_pipe_a(struct drm_device *dev)
10482{
10483 struct intel_connector *connector;
10484 struct drm_connector *crt = NULL;
10485 struct intel_load_detect_pipe load_detect_temp;
10486
10487 /* We can't just switch on the pipe A, we need to set things up with a
10488 * proper mode and output configuration. As a gross hack, enable pipe A
10489 * by enabling the load detect pipe once. */
10490 list_for_each_entry(connector,
10491 &dev->mode_config.connector_list,
10492 base.head) {
10493 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10494 crt = &connector->base;
10495 break;
10496 }
10497 }
10498
10499 if (!crt)
10500 return;
10501
10502 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10503 intel_release_load_detect_pipe(crt, &load_detect_temp);
10504
652c393a 10505
7fad798e
DV		 10506}
10507
fa555837
DV		 10508static bool
10509intel_check_plane_mapping(struct intel_crtc *crtc)
10510{
7eb552ae
BW		 10511 struct drm_device *dev = crtc->base.dev;
10512 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 10513 u32 reg, val;
10514
7eb552ae 10515 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 10516 return true;
10517
10518 reg = DSPCNTR(!crtc->plane);
10519 val = I915_READ(reg);
10520
10521 if ((val & DISPLAY_PLANE_ENABLE) &&
10522 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10523 return false;
10524
10525 return true;
10526}
10527
24929352
DV		 10528static void intel_sanitize_crtc(struct intel_crtc *crtc)
10529{
10530 struct drm_device *dev = crtc->base.dev;
10531 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 10532 u32 reg;
24929352 10533
24929352 10534 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 10535 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 10536 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10537
10538 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 10539 * disable the crtc (and hence change the state) if it is wrong. Note
10540 * that gen4+ has a fixed plane -> pipe mapping. */
10541 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 10542 struct intel_connector *connector;
10543 bool plane;
10544
24929352
DV		 10545 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10546 crtc->base.base.id);
10547
10548 /* Pipe has the wrong plane attached and the plane is active.
10549 * Temporarily change the plane mapping and disable everything
10550 * ... */
10551 plane = crtc->plane;
10552 crtc->plane = !plane;
10553 dev_priv->display.crtc_disable(&crtc->base);
10554 crtc->plane = plane;
10555
10556 /* ... and break all links. */
10557 list_for_each_entry(connector, &dev->mode_config.connector_list,
10558 base.head) {
10559 if (connector->encoder->base.crtc != &crtc->base)
10560 continue;
10561
10562 intel_connector_break_all_links(connector);
10563 }
10564
10565 WARN_ON(crtc->active);
10566 crtc->base.enabled = false;
10567 }
24929352 10568
7fad798e
DV		 10569 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10570 crtc->pipe == PIPE_A && !crtc->active) {
10571 /* BIOS forgot to enable pipe A, this mostly happens after
10572 * resume. Force-enable the pipe to fix this, the update_dpms
10573 * call below we restore the pipe to the right state, but leave
10574 * the required bits on. */
10575 intel_enable_pipe_a(dev);
10576 }
10577
24929352
DV		 10578 /* Adjust the state of the output pipe according to whether we
10579 * have active connectors/encoders. */
10580 intel_crtc_update_dpms(&crtc->base);
10581
10582 if (crtc->active != crtc->base.enabled) {
10583 struct intel_encoder *encoder;
10584
10585 /* This can happen either due to bugs in the get_hw_state
10586 * functions or because the pipe is force-enabled due to the
10587 * pipe A quirk. */
10588 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10589 crtc->base.base.id,
10590 crtc->base.enabled ? "enabled" : "disabled",
10591 crtc->active ? "enabled" : "disabled");
10592
10593 crtc->base.enabled = crtc->active;
10594
10595 /* Because we only establish the connector -> encoder ->
10596 * crtc links if something is active, this means the
10597 * crtc is now deactivated. Break the links. connector
10598 * -> encoder links are only establish when things are
10599 * actually up, hence no need to break them. */
10600 WARN_ON(crtc->active);
10601
10602 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10603 WARN_ON(encoder->connectors_active);
10604 encoder->base.crtc = NULL;
10605 }
10606 }
10607}
10608
10609static void intel_sanitize_encoder(struct intel_encoder *encoder)
10610{
10611 struct intel_connector *connector;
10612 struct drm_device *dev = encoder->base.dev;
10613
10614 /* We need to check both for a crtc link (meaning that the
10615 * encoder is active and trying to read from a pipe) and the
10616 * pipe itself being active. */
10617 bool has_active_crtc = encoder->base.crtc &&
10618 to_intel_crtc(encoder->base.crtc)->active;
10619
10620 if (encoder->connectors_active && !has_active_crtc) {
10621 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10622 encoder->base.base.id,
10623 drm_get_encoder_name(&encoder->base));
10624
10625 /* Connector is active, but has no active pipe. This is
10626 * fallout from our resume register restoring. Disable
10627 * the encoder manually again. */
10628 if (encoder->base.crtc) {
10629 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10630 encoder->base.base.id,
10631 drm_get_encoder_name(&encoder->base));
10632 encoder->disable(encoder);
10633 }
10634
10635 /* Inconsistent output/port/pipe state happens presumably due to
10636 * a bug in one of the get_hw_state functions. Or someplace else
10637 * in our code, like the register restore mess on resume. Clamp
10638 * things to off as a safer default. */
10639 list_for_each_entry(connector,
10640 &dev->mode_config.connector_list,
10641 base.head) {
10642 if (connector->encoder != encoder)
10643 continue;
10644
10645 intel_connector_break_all_links(connector);
10646 }
10647 }
10648 /* Enabled encoders without active connectors will be fixed in
10649 * the crtc fixup. */
10650}
10651
44cec740 10652void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 10653{
10654 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 10655 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 10656
8dc8a27c
PZ		 10657 /* This function can be called both from intel_modeset_setup_hw_state or
10658 * at a very early point in our resume sequence, where the power well
10659 * structures are not yet restored. Since this function is at a very
10660 * paranoid "someone might have enabled VGA while we were not looking"
10661 * level, just check if the power well is enabled instead of trying to
10662 * follow the "don't touch the power well if we don't need it" policy
10663 * the rest of the driver uses. */
10664 if (HAS_POWER_WELL(dev) &&
6aedd1f5 10665 (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
8dc8a27c
PZ		 10666 return;
10667
0fde901f
KM		 10668 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
10669 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 10670 i915_disable_vga(dev);
6e1b4fda 10671 i915_disable_vga_mem(dev);
0fde901f
KM		 10672 }
10673}
10674
30e984df 10675static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 10676{
10677 struct drm_i915_private *dev_priv = dev->dev_private;
10678 enum pipe pipe;
24929352
DV		 10679 struct intel_crtc *crtc;
10680 struct intel_encoder *encoder;
10681 struct intel_connector *connector;
5358901f 10682 int i;
24929352 10683
0e8ffe1b
DV		 10684 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10685 base.head) {
88adfff1 10686 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 10687
0e8ffe1b
DV		 10688 crtc->active = dev_priv->display.get_pipe_config(crtc,
10689 &crtc->config);
24929352
DV		 10690
10691 crtc->base.enabled = crtc->active;
10692
10693 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10694 crtc->base.base.id,
10695 crtc->active ? "enabled" : "disabled");
10696 }
10697
5358901f 10698 /* FIXME: Smash this into the new shared dpll infrastructure. */
affa9354 10699 if (HAS_DDI(dev))
6441ab5f
PZ		 10700 intel_ddi_setup_hw_pll_state(dev);
10701
5358901f
DV		 10702 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10703 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10704
10705 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10706 pll->active = 0;
10707 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10708 base.head) {
10709 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10710 pll->active++;
10711 }
10712 pll->refcount = pll->active;
10713
35c95375
DV		 10714 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10715 pll->name, pll->refcount, pll->on);
5358901f
DV		 10716 }
10717
24929352
DV		 10718 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10719 base.head) {
10720 pipe = 0;
10721
10722 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 10723 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10724 encoder->base.crtc = &crtc->base;
510d5f2f 10725 if (encoder->get_config)
045ac3b5 10726 encoder->get_config(encoder, &crtc->config);
24929352
DV		 10727 } else {
10728 encoder->base.crtc = NULL;
10729 }
10730
10731 encoder->connectors_active = false;
10732 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10733 encoder->base.base.id,
10734 drm_get_encoder_name(&encoder->base),
10735 encoder->base.crtc ? "enabled" : "disabled",
10736 pipe);
10737 }
10738
10739 list_for_each_entry(connector, &dev->mode_config.connector_list,
10740 base.head) {
10741 if (connector->get_hw_state(connector)) {
10742 connector->base.dpms = DRM_MODE_DPMS_ON;
10743 connector->encoder->connectors_active = true;
10744 connector->base.encoder = &connector->encoder->base;
10745 } else {
10746 connector->base.dpms = DRM_MODE_DPMS_OFF;
10747 connector->base.encoder = NULL;
10748 }
10749 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10750 connector->base.base.id,
10751 drm_get_connector_name(&connector->base),
10752 connector->base.encoder ? "enabled" : "disabled");
10753 }
30e984df
DV		 10754}
10755
10756/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10757 * and i915 state tracking structures. */
10758void intel_modeset_setup_hw_state(struct drm_device *dev,
10759 bool force_restore)
10760{
10761 struct drm_i915_private *dev_priv = dev->dev_private;
10762 enum pipe pipe;
30e984df
DV		 10763 struct intel_crtc *crtc;
10764 struct intel_encoder *encoder;
35c95375 10765 int i;
30e984df
DV		 10766
10767 intel_modeset_readout_hw_state(dev);
24929352 10768
babea61d
JB		 10769 /*
10770 * Now that we have the config, copy it to each CRTC struct
10771 * Note that this could go away if we move to using crtc_config
10772 * checking everywhere.
10773 */
10774 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10775 base.head) {
10776 if (crtc->active && i915_fastboot) {
10777 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10778
10779 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10780 crtc->base.base.id);
10781 drm_mode_debug_printmodeline(&crtc->base.mode);
10782 }
10783 }
10784
24929352
DV		 10785 /* HW state is read out, now we need to sanitize this mess. */
10786 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10787 base.head) {
10788 intel_sanitize_encoder(encoder);
10789 }
10790
10791 for_each_pipe(pipe) {
10792 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10793 intel_sanitize_crtc(crtc);
c0b03411 10794 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 10795 }
9a935856 10796
35c95375
DV		 10797 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10798 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10799
10800 if (!pll->on || pll->active)
10801 continue;
10802
10803 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10804
10805 pll->disable(dev_priv, pll);
10806 pll->on = false;
10807 }
10808
45e2b5f6 10809 if (force_restore) {
7d0bc1ea
VS		 10810 i915_redisable_vga(dev);
10811
f30da187
DV		 10812 /*
10813 * We need to use raw interfaces for restoring state to avoid
10814 * checking (bogus) intermediate states.
10815 */
45e2b5f6 10816 for_each_pipe(pipe) {
b5644d05
JB		 10817 struct drm_crtc *crtc =
10818 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 10819
10820 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10821 crtc->fb);
45e2b5f6
DV		 10822 }
10823 } else {
10824 intel_modeset_update_staged_output_state(dev);
10825 }
8af6cf88
DV		 10826
10827 intel_modeset_check_state(dev);
2e938892
DV		 10828
10829 drm_mode_config_reset(dev);
2c7111db
CW		 10830}
10831
10832void intel_modeset_gem_init(struct drm_device *dev)
10833{
1833b134 10834 intel_modeset_init_hw(dev);
02e792fb
DV		 10835
10836 intel_setup_overlay(dev);
24929352 10837
45e2b5f6 10838 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 10839}
10840
10841void intel_modeset_cleanup(struct drm_device *dev)
10842{
652c393a
JB		 10843 struct drm_i915_private *dev_priv = dev->dev_private;
10844 struct drm_crtc *crtc;
d9255d57 10845 struct drm_connector *connector;
652c393a 10846
fd0c0642
DV		 10847 /*
10848 * Interrupts and polling as the first thing to avoid creating havoc.
10849 * Too much stuff here (turning of rps, connectors, ...) would
10850 * experience fancy races otherwise.
10851 */
10852 drm_irq_uninstall(dev);
10853 cancel_work_sync(&dev_priv->hotplug_work);
10854 /*
10855 * Due to the hpd irq storm handling the hotplug work can re-arm the
10856 * poll handlers. Hence disable polling after hpd handling is shut down.
10857 */
f87ea761 10858 drm_kms_helper_poll_fini(dev);
fd0c0642 10859
652c393a
JB		 10860 mutex_lock(&dev->struct_mutex);
10861
723bfd70
JB		 10862 intel_unregister_dsm_handler();
10863
652c393a
JB		 10864 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10865 /* Skip inactive CRTCs */
10866 if (!crtc->fb)
10867 continue;
10868
3dec0095 10869 intel_increase_pllclock(crtc);
652c393a
JB		 10870 }
10871
973d04f9 10872 intel_disable_fbc(dev);
e70236a8 10873
6e1b4fda 10874 i915_enable_vga_mem(dev);
81b5c7bc 10875
8090c6b9 10876 intel_disable_gt_powersave(dev);
0cdab21f 10877
930ebb46
DV		 10878 ironlake_teardown_rc6(dev);
10879
69341a5e
KH		 10880 mutex_unlock(&dev->struct_mutex);
10881
1630fe75
CW		 10882 /* flush any delayed tasks or pending work */
10883 flush_scheduled_work();
10884
dc652f90
JN		 10885 /* destroy backlight, if any, before the connectors */
10886 intel_panel_destroy_backlight(dev);
10887
d9255d57
PZ		 10888 /* destroy the sysfs files before encoders/connectors */
10889 list_for_each_entry(connector, &dev->mode_config.connector_list, head)
10890 drm_sysfs_connector_remove(connector);
10891
79e53945 10892 drm_mode_config_cleanup(dev);
4d7bb011
DV		 10893
10894 intel_cleanup_overlay(dev);
79e53945
JB		 10895}
10896
f1c79df3
ZW		 10897/*
10898 * Return which encoder is currently attached for connector.
10899 */
df0e9248 10900struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 10901{
df0e9248
CW		 10902 return &intel_attached_encoder(connector)->base;
10903}
f1c79df3 10904
df0e9248
CW		 10905void intel_connector_attach_encoder(struct intel_connector *connector,
10906 struct intel_encoder *encoder)
10907{
10908 connector->encoder = encoder;
10909 drm_mode_connector_attach_encoder(&connector->base,
10910 &encoder->base);
79e53945 10911}
28d52043
DA		 10912
10913/*
10914 * set vga decode state - true == enable VGA decode
10915 */
10916int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10917{
10918 struct drm_i915_private *dev_priv = dev->dev_private;
10919 u16 gmch_ctrl;
10920
10921 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10922 if (state)
10923 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10924 else
10925 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10926 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10927 return 0;
10928}
c4a1d9e4 10929
c4a1d9e4 10930struct intel_display_error_state {
ff57f1b0
PZ		 10931
10932 u32 power_well_driver;
10933
63b66e5b
CW		 10934 int num_transcoders;
10935
c4a1d9e4
CW		 10936 struct intel_cursor_error_state {
10937 u32 control;
10938 u32 position;
10939 u32 base;
10940 u32 size;
52331309 10941 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 10942
10943 struct intel_pipe_error_state {
c4a1d9e4 10944 u32 source;
52331309 10945 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 10946
10947 struct intel_plane_error_state {
10948 u32 control;
10949 u32 stride;
10950 u32 size;
10951 u32 pos;
10952 u32 addr;
10953 u32 surface;
10954 u32 tile_offset;
52331309 10955 } plane[I915_MAX_PIPES];
63b66e5b
CW		 10956
10957 struct intel_transcoder_error_state {
10958 enum transcoder cpu_transcoder;
10959
10960 u32 conf;
10961
10962 u32 htotal;
10963 u32 hblank;
10964 u32 hsync;
10965 u32 vtotal;
10966 u32 vblank;
10967 u32 vsync;
10968 } transcoder[4];
c4a1d9e4
CW		 10969};
10970
10971struct intel_display_error_state *
10972intel_display_capture_error_state(struct drm_device *dev)
10973{
0206e353 10974 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 10975 struct intel_display_error_state *error;
63b66e5b
CW		 10976 int transcoders[] = {
10977 TRANSCODER_A,
10978 TRANSCODER_B,
10979 TRANSCODER_C,
10980 TRANSCODER_EDP,
10981 };
c4a1d9e4
CW		 10982 int i;
10983
63b66e5b
CW		 10984 if (INTEL_INFO(dev)->num_pipes == 0)
10985 return NULL;
10986
c4a1d9e4
CW		 10987 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10988 if (error == NULL)
10989 return NULL;
10990
ff57f1b0
PZ		 10991 if (HAS_POWER_WELL(dev))
10992 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10993
52331309 10994 for_each_pipe(i) {
a18c4c3d
PZ		 10995 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10996 error->cursor[i].control = I915_READ(CURCNTR(i));
10997 error->cursor[i].position = I915_READ(CURPOS(i));
10998 error->cursor[i].base = I915_READ(CURBASE(i));
10999 } else {
11000 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
11001 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
11002 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
11003 }
c4a1d9e4
CW		 11004
11005 error->plane[i].control = I915_READ(DSPCNTR(i));
11006 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 11007 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 11008 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 11009 error->plane[i].pos = I915_READ(DSPPOS(i));
11010 }
ca291363
PZ		 11011 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11012 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 11013 if (INTEL_INFO(dev)->gen >= 4) {
11014 error->plane[i].surface = I915_READ(DSPSURF(i));
11015 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
11016 }
11017
c4a1d9e4 11018 error->pipe[i].source = I915_READ(PIPESRC(i));
63b66e5b
CW		 11019 }
11020
11021 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
11022 if (HAS_DDI(dev_priv->dev))
11023 error->num_transcoders++; /* Account for eDP. */
11024
11025 for (i = 0; i < error->num_transcoders; i++) {
11026 enum transcoder cpu_transcoder = transcoders[i];
11027
11028 error->transcoder[i].cpu_transcoder = cpu_transcoder;
11029
11030 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
11031 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
11032 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
11033 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
11034 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
11035 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
11036 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 11037 }
11038
12d217c7
PZ		 11039 /* In the code above we read the registers without checking if the power
11040 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
11041 * prevent the next I915_WRITE from detecting it and printing an error
11042 * message. */
907b28c5 11043 intel_uncore_clear_errors(dev);
12d217c7 11044
c4a1d9e4
CW		 11045 return error;
11046}
11047
edc3d884
MK		 11048#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
11049
c4a1d9e4 11050void
edc3d884 11051intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 11052 struct drm_device *dev,
11053 struct intel_display_error_state *error)
11054{
11055 int i;
11056
63b66e5b
CW		 11057 if (!error)
11058 return;
11059
edc3d884 11060 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 11061 if (HAS_POWER_WELL(dev))
edc3d884 11062 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 11063 error->power_well_driver);
52331309 11064 for_each_pipe(i) {
edc3d884 11065 err_printf(m, "Pipe [%d]:\n", i);
edc3d884 11066 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
edc3d884
MK		 11067
11068 err_printf(m, "Plane [%d]:\n", i);
11069 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
11070 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 11071 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 11072 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
11073 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 11074 }
4b71a570 11075 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 11076 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 11077 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 11078 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
11079 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 11080 }
11081
edc3d884
MK		 11082 err_printf(m, "Cursor [%d]:\n", i);
11083 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
11084 err_printf(m, " POS: %08x\n", error->cursor[i].position);
11085 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 11086 }
63b66e5b
CW		 11087
11088 for (i = 0; i < error->num_transcoders; i++) {
11089 err_printf(m, " CPU transcoder: %c\n",
11090 transcoder_name(error->transcoder[i].cpu_transcoder));
11091 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
11092 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
11093 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
11094 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
11095 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
11096 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
11097 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
11098 }
c4a1d9e4 11099}
ubuntu-bionic-kernel mirror