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drm/i915: Remove check for conflicting relocation write-domains
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 47
48typedef struct {
0206e353
AJ		 49 /* given values */
50 int n;
51 int m1, m2;
52 int p1, p2;
53 /* derived values */
54 int dot;
55 int vco;
56 int m;
57 int p;
79e53945
JB		 58} intel_clock_t;
59
60typedef struct {
0206e353 61 int min, max;
79e53945
JB		 62} intel_range_t;
63
64typedef struct {
0206e353
AJ		 65 int dot_limit;
66 int p2_slow, p2_fast;
79e53945
JB		 67} intel_p2_t;
68
69#define INTEL_P2_NUM 2
d4906093
ML		 70typedef struct intel_limit intel_limit_t;
71struct intel_limit {
0206e353
AJ		 72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
73 intel_p2_t p2;
74 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 75 int, int, intel_clock_t *, intel_clock_t *);
d4906093 76};
79e53945 77
2377b741
JB		 78/* FDI */
79#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
80
d2acd215
DV		 81int
82intel_pch_rawclk(struct drm_device *dev)
83{
84 struct drm_i915_private *dev_priv = dev->dev_private;
85
86 WARN_ON(!HAS_PCH_SPLIT(dev));
87
88 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
89}
90
d4906093
ML		 91static bool
92intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 93 int target, int refclk, intel_clock_t *match_clock,
94 intel_clock_t *best_clock);
d4906093
ML		 95static bool
96intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 97 int target, int refclk, intel_clock_t *match_clock,
98 intel_clock_t *best_clock);
79e53945 99
a4fc5ed6
KP		 100static bool
101intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 102 int target, int refclk, intel_clock_t *match_clock,
103 intel_clock_t *best_clock);
5eb08b69 104static bool
f2b115e6 105intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 106 int target, int refclk, intel_clock_t *match_clock,
107 intel_clock_t *best_clock);
a4fc5ed6 108
a0c4da24
JB		 109static bool
110intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
111 int target, int refclk, intel_clock_t *match_clock,
112 intel_clock_t *best_clock);
113
021357ac
CW		 114static inline u32 /* units of 100MHz */
115intel_fdi_link_freq(struct drm_device *dev)
116{
8b99e68c
CW		 117 if (IS_GEN5(dev)) {
118 struct drm_i915_private *dev_priv = dev->dev_private;
119 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
120 } else
121 return 27;
021357ac
CW		 122}
123
e4b36699 124static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 125 .dot = { .min = 25000, .max = 350000 },
126 .vco = { .min = 930000, .max = 1400000 },
127 .n = { .min = 3, .max = 16 },
128 .m = { .min = 96, .max = 140 },
129 .m1 = { .min = 18, .max = 26 },
130 .m2 = { .min = 6, .max = 16 },
131 .p = { .min = 4, .max = 128 },
132 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 133 .p2 = { .dot_limit = 165000,
134 .p2_slow = 4, .p2_fast = 2 },
d4906093 135 .find_pll = intel_find_best_PLL,
e4b36699
KP		 136};
137
138static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 139 .dot = { .min = 25000, .max = 350000 },
140 .vco = { .min = 930000, .max = 1400000 },
141 .n = { .min = 3, .max = 16 },
142 .m = { .min = 96, .max = 140 },
143 .m1 = { .min = 18, .max = 26 },
144 .m2 = { .min = 6, .max = 16 },
145 .p = { .min = 4, .max = 128 },
146 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 147 .p2 = { .dot_limit = 165000,
148 .p2_slow = 14, .p2_fast = 7 },
d4906093 149 .find_pll = intel_find_best_PLL,
e4b36699 150};
273e27ca 151
e4b36699 152static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 153 .dot = { .min = 20000, .max = 400000 },
154 .vco = { .min = 1400000, .max = 2800000 },
155 .n = { .min = 1, .max = 6 },
156 .m = { .min = 70, .max = 120 },
157 .m1 = { .min = 10, .max = 22 },
158 .m2 = { .min = 5, .max = 9 },
159 .p = { .min = 5, .max = 80 },
160 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 161 .p2 = { .dot_limit = 200000,
162 .p2_slow = 10, .p2_fast = 5 },
d4906093 163 .find_pll = intel_find_best_PLL,
e4b36699
KP		 164};
165
166static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 167 .dot = { .min = 20000, .max = 400000 },
168 .vco = { .min = 1400000, .max = 2800000 },
169 .n = { .min = 1, .max = 6 },
170 .m = { .min = 70, .max = 120 },
171 .m1 = { .min = 10, .max = 22 },
172 .m2 = { .min = 5, .max = 9 },
173 .p = { .min = 7, .max = 98 },
174 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 175 .p2 = { .dot_limit = 112000,
176 .p2_slow = 14, .p2_fast = 7 },
d4906093 177 .find_pll = intel_find_best_PLL,
e4b36699
KP		 178};
179
273e27ca 180
e4b36699 181static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 182 .dot = { .min = 25000, .max = 270000 },
183 .vco = { .min = 1750000, .max = 3500000},
184 .n = { .min = 1, .max = 4 },
185 .m = { .min = 104, .max = 138 },
186 .m1 = { .min = 17, .max = 23 },
187 .m2 = { .min = 5, .max = 11 },
188 .p = { .min = 10, .max = 30 },
189 .p1 = { .min = 1, .max = 3},
190 .p2 = { .dot_limit = 270000,
191 .p2_slow = 10,
192 .p2_fast = 10
044c7c41 193 },
d4906093 194 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 195};
196
197static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 198 .dot = { .min = 22000, .max = 400000 },
199 .vco = { .min = 1750000, .max = 3500000},
200 .n = { .min = 1, .max = 4 },
201 .m = { .min = 104, .max = 138 },
202 .m1 = { .min = 16, .max = 23 },
203 .m2 = { .min = 5, .max = 11 },
204 .p = { .min = 5, .max = 80 },
205 .p1 = { .min = 1, .max = 8},
206 .p2 = { .dot_limit = 165000,
207 .p2_slow = 10, .p2_fast = 5 },
d4906093 208 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 209};
210
211static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 212 .dot = { .min = 20000, .max = 115000 },
213 .vco = { .min = 1750000, .max = 3500000 },
214 .n = { .min = 1, .max = 3 },
215 .m = { .min = 104, .max = 138 },
216 .m1 = { .min = 17, .max = 23 },
217 .m2 = { .min = 5, .max = 11 },
218 .p = { .min = 28, .max = 112 },
219 .p1 = { .min = 2, .max = 8 },
220 .p2 = { .dot_limit = 0,
221 .p2_slow = 14, .p2_fast = 14
044c7c41 222 },
d4906093 223 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 224};
225
226static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 227 .dot = { .min = 80000, .max = 224000 },
228 .vco = { .min = 1750000, .max = 3500000 },
229 .n = { .min = 1, .max = 3 },
230 .m = { .min = 104, .max = 138 },
231 .m1 = { .min = 17, .max = 23 },
232 .m2 = { .min = 5, .max = 11 },
233 .p = { .min = 14, .max = 42 },
234 .p1 = { .min = 2, .max = 6 },
235 .p2 = { .dot_limit = 0,
236 .p2_slow = 7, .p2_fast = 7
044c7c41 237 },
d4906093 238 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 239};
240
241static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 242 .dot = { .min = 161670, .max = 227000 },
243 .vco = { .min = 1750000, .max = 3500000},
244 .n = { .min = 1, .max = 2 },
245 .m = { .min = 97, .max = 108 },
246 .m1 = { .min = 0x10, .max = 0x12 },
247 .m2 = { .min = 0x05, .max = 0x06 },
248 .p = { .min = 10, .max = 20 },
249 .p1 = { .min = 1, .max = 2},
250 .p2 = { .dot_limit = 0,
273e27ca 251 .p2_slow = 10, .p2_fast = 10 },
0206e353 252 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 253};
254
f2b115e6 255static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 256 .dot = { .min = 20000, .max = 400000},
257 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 258 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 259 .n = { .min = 3, .max = 6 },
260 .m = { .min = 2, .max = 256 },
273e27ca 261 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 262 .m1 = { .min = 0, .max = 0 },
263 .m2 = { .min = 0, .max = 254 },
264 .p = { .min = 5, .max = 80 },
265 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 266 .p2 = { .dot_limit = 200000,
267 .p2_slow = 10, .p2_fast = 5 },
6115707b 268 .find_pll = intel_find_best_PLL,
e4b36699
KP		 269};
270
f2b115e6 271static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 272 .dot = { .min = 20000, .max = 400000 },
273 .vco = { .min = 1700000, .max = 3500000 },
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 .m1 = { .min = 0, .max = 0 },
277 .m2 = { .min = 0, .max = 254 },
278 .p = { .min = 7, .max = 112 },
279 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 280 .p2 = { .dot_limit = 112000,
281 .p2_slow = 14, .p2_fast = 14 },
6115707b 282 .find_pll = intel_find_best_PLL,
e4b36699
KP		 283};
284
273e27ca
EA		 285/* Ironlake / Sandybridge
286 *
287 * We calculate clock using (register_value + 2) for N/M1/M2, so here
288 * the range value for them is (actual_value - 2).
289 */
b91ad0ec 290static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 291 .dot = { .min = 25000, .max = 350000 },
292 .vco = { .min = 1760000, .max = 3510000 },
293 .n = { .min = 1, .max = 5 },
294 .m = { .min = 79, .max = 127 },
295 .m1 = { .min = 12, .max = 22 },
296 .m2 = { .min = 5, .max = 9 },
297 .p = { .min = 5, .max = 80 },
298 .p1 = { .min = 1, .max = 8 },
299 .p2 = { .dot_limit = 225000,
300 .p2_slow = 10, .p2_fast = 5 },
4547668a 301 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 302};
303
b91ad0ec 304static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 305 .dot = { .min = 25000, .max = 350000 },
306 .vco = { .min = 1760000, .max = 3510000 },
307 .n = { .min = 1, .max = 3 },
308 .m = { .min = 79, .max = 118 },
309 .m1 = { .min = 12, .max = 22 },
310 .m2 = { .min = 5, .max = 9 },
311 .p = { .min = 28, .max = 112 },
312 .p1 = { .min = 2, .max = 8 },
313 .p2 = { .dot_limit = 225000,
314 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 315 .find_pll = intel_g4x_find_best_PLL,
316};
317
318static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 319 .dot = { .min = 25000, .max = 350000 },
320 .vco = { .min = 1760000, .max = 3510000 },
321 .n = { .min = 1, .max = 3 },
322 .m = { .min = 79, .max = 127 },
323 .m1 = { .min = 12, .max = 22 },
324 .m2 = { .min = 5, .max = 9 },
325 .p = { .min = 14, .max = 56 },
326 .p1 = { .min = 2, .max = 8 },
327 .p2 = { .dot_limit = 225000,
328 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 329 .find_pll = intel_g4x_find_best_PLL,
330};
331
273e27ca 332/* LVDS 100mhz refclk limits. */
b91ad0ec 333static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 334 .dot = { .min = 25000, .max = 350000 },
335 .vco = { .min = 1760000, .max = 3510000 },
336 .n = { .min = 1, .max = 2 },
337 .m = { .min = 79, .max = 126 },
338 .m1 = { .min = 12, .max = 22 },
339 .m2 = { .min = 5, .max = 9 },
340 .p = { .min = 28, .max = 112 },
0206e353 341 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 342 .p2 = { .dot_limit = 225000,
343 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 344 .find_pll = intel_g4x_find_best_PLL,
345};
346
347static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 348 .dot = { .min = 25000, .max = 350000 },
349 .vco = { .min = 1760000, .max = 3510000 },
350 .n = { .min = 1, .max = 3 },
351 .m = { .min = 79, .max = 126 },
352 .m1 = { .min = 12, .max = 22 },
353 .m2 = { .min = 5, .max = 9 },
354 .p = { .min = 14, .max = 42 },
0206e353 355 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 356 .p2 = { .dot_limit = 225000,
357 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 358 .find_pll = intel_g4x_find_best_PLL,
359};
360
361static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 362 .dot = { .min = 25000, .max = 350000 },
363 .vco = { .min = 1760000, .max = 3510000},
364 .n = { .min = 1, .max = 2 },
365 .m = { .min = 81, .max = 90 },
366 .m1 = { .min = 12, .max = 22 },
367 .m2 = { .min = 5, .max = 9 },
368 .p = { .min = 10, .max = 20 },
369 .p1 = { .min = 1, .max = 2},
370 .p2 = { .dot_limit = 0,
273e27ca 371 .p2_slow = 10, .p2_fast = 10 },
0206e353 372 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 373};
374
a0c4da24
JB		 375static const intel_limit_t intel_limits_vlv_dac = {
376 .dot = { .min = 25000, .max = 270000 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m = { .min = 22, .max = 450 }, /* guess */
380 .m1 = { .min = 2, .max = 3 },
381 .m2 = { .min = 11, .max = 156 },
382 .p = { .min = 10, .max = 30 },
383 .p1 = { .min = 2, .max = 3 },
384 .p2 = { .dot_limit = 270000,
385 .p2_slow = 2, .p2_fast = 20 },
386 .find_pll = intel_vlv_find_best_pll,
387};
388
389static const intel_limit_t intel_limits_vlv_hdmi = {
390 .dot = { .min = 20000, .max = 165000 },
17dc9257 391 .vco = { .min = 4000000, .max = 5994000},
a0c4da24
JB		 392 .n = { .min = 1, .max = 7 },
393 .m = { .min = 60, .max = 300 }, /* guess */
394 .m1 = { .min = 2, .max = 3 },
395 .m2 = { .min = 11, .max = 156 },
396 .p = { .min = 10, .max = 30 },
397 .p1 = { .min = 2, .max = 3 },
398 .p2 = { .dot_limit = 270000,
399 .p2_slow = 2, .p2_fast = 20 },
400 .find_pll = intel_vlv_find_best_pll,
401};
402
403static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 404 .dot = { .min = 25000, .max = 270000 },
405 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 406 .n = { .min = 1, .max = 7 },
74a4dd2e 407 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 408 .m1 = { .min = 2, .max = 3 },
409 .m2 = { .min = 11, .max = 156 },
410 .p = { .min = 10, .max = 30 },
411 .p1 = { .min = 2, .max = 3 },
412 .p2 = { .dot_limit = 270000,
413 .p2_slow = 2, .p2_fast = 20 },
414 .find_pll = intel_vlv_find_best_pll,
415};
416
57f350b6
JB		 417u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
418{
419 unsigned long flags;
420 u32 val = 0;
421
422 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
423 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
424 DRM_ERROR("DPIO idle wait timed out\n");
425 goto out_unlock;
426 }
427
428 I915_WRITE(DPIO_REG, reg);
429 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
430 DPIO_BYTE);
431 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
432 DRM_ERROR("DPIO read wait timed out\n");
433 goto out_unlock;
434 }
435 val = I915_READ(DPIO_DATA);
436
437out_unlock:
438 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
439 return val;
440}
441
a0c4da24
JB		 442static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
443 u32 val)
444{
445 unsigned long flags;
446
447 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
448 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
449 DRM_ERROR("DPIO idle wait timed out\n");
450 goto out_unlock;
451 }
452
453 I915_WRITE(DPIO_DATA, val);
454 I915_WRITE(DPIO_REG, reg);
455 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
456 DPIO_BYTE);
457 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
458 DRM_ERROR("DPIO write wait timed out\n");
459
460out_unlock:
461 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
462}
463
57f350b6
JB		 464static void vlv_init_dpio(struct drm_device *dev)
465{
466 struct drm_i915_private *dev_priv = dev->dev_private;
467
468 /* Reset the DPIO config */
469 I915_WRITE(DPIO_CTL, 0);
470 POSTING_READ(DPIO_CTL);
471 I915_WRITE(DPIO_CTL, 1);
472 POSTING_READ(DPIO_CTL);
473}
474
1b894b59
CW		 475static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
476 int refclk)
2c07245f 477{
b91ad0ec 478 struct drm_device *dev = crtc->dev;
2c07245f 479 const intel_limit_t *limit;
b91ad0ec
ZW		 480
481 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 482 if (intel_is_dual_link_lvds(dev)) {
b91ad0ec 483 /* LVDS dual channel */
1b894b59 484 if (refclk == 100000)
b91ad0ec
ZW		 485 limit = &intel_limits_ironlake_dual_lvds_100m;
486 else
487 limit = &intel_limits_ironlake_dual_lvds;
488 } else {
1b894b59 489 if (refclk == 100000)
b91ad0ec
ZW		 490 limit = &intel_limits_ironlake_single_lvds_100m;
491 else
492 limit = &intel_limits_ironlake_single_lvds;
493 }
494 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
547dc041 495 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
4547668a 496 limit = &intel_limits_ironlake_display_port;
2c07245f 497 else
b91ad0ec 498 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 499
500 return limit;
501}
502
044c7c41
ML		 503static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
504{
505 struct drm_device *dev = crtc->dev;
044c7c41
ML		 506 const intel_limit_t *limit;
507
508 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 509 if (intel_is_dual_link_lvds(dev))
044c7c41 510 /* LVDS with dual channel */
e4b36699 511 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 512 else
513 /* LVDS with dual channel */
e4b36699 514 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 515 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
516 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 517 limit = &intel_limits_g4x_hdmi;
044c7c41 518 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 519 limit = &intel_limits_g4x_sdvo;
0206e353 520 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 521 limit = &intel_limits_g4x_display_port;
044c7c41 522 } else /* The option is for other outputs */
e4b36699 523 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 524
525 return limit;
526}
527
1b894b59 528static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 529{
530 struct drm_device *dev = crtc->dev;
531 const intel_limit_t *limit;
532
bad720ff 533 if (HAS_PCH_SPLIT(dev))
1b894b59 534 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 535 else if (IS_G4X(dev)) {
044c7c41 536 limit = intel_g4x_limit(crtc);
f2b115e6 537 } else if (IS_PINEVIEW(dev)) {
2177832f 538 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 539 limit = &intel_limits_pineview_lvds;
2177832f 540 else
f2b115e6 541 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 542 } else if (IS_VALLEYVIEW(dev)) {
543 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
544 limit = &intel_limits_vlv_dac;
545 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
546 limit = &intel_limits_vlv_hdmi;
547 else
548 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 549 } else if (!IS_GEN2(dev)) {
550 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
551 limit = &intel_limits_i9xx_lvds;
552 else
553 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 554 } else {
555 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 556 limit = &intel_limits_i8xx_lvds;
79e53945 557 else
e4b36699 558 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 559 }
560 return limit;
561}
562
f2b115e6
AJ		 563/* m1 is reserved as 0 in Pineview, n is a ring counter */
564static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 565{
2177832f
SL		 566 clock->m = clock->m2 + 2;
567 clock->p = clock->p1 * clock->p2;
568 clock->vco = refclk * clock->m / clock->n;
569 clock->dot = clock->vco / clock->p;
570}
571
572static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
573{
f2b115e6
AJ		 574 if (IS_PINEVIEW(dev)) {
575 pineview_clock(refclk, clock);
2177832f
SL		 576 return;
577 }
79e53945
JB		 578 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
579 clock->p = clock->p1 * clock->p2;
580 clock->vco = refclk * clock->m / (clock->n + 2);
581 clock->dot = clock->vco / clock->p;
582}
583
79e53945
JB		 584/**
585 * Returns whether any output on the specified pipe is of the specified type
586 */
4ef69c7a 587bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 588{
4ef69c7a 589 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 590 struct intel_encoder *encoder;
591
6c2b7c12
DV		 592 for_each_encoder_on_crtc(dev, crtc, encoder)
593 if (encoder->type == type)
4ef69c7a
CW		 594 return true;
595
596 return false;
79e53945
JB		 597}
598
7c04d1d9 599#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 600/**
601 * Returns whether the given set of divisors are valid for a given refclk with
602 * the given connectors.
603 */
604
1b894b59
CW		 605static bool intel_PLL_is_valid(struct drm_device *dev,
606 const intel_limit_t *limit,
607 const intel_clock_t *clock)
79e53945 608{
79e53945 609 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 610 INTELPllInvalid("p1 out of range\n");
79e53945 611 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 612 INTELPllInvalid("p out of range\n");
79e53945 613 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 614 INTELPllInvalid("m2 out of range\n");
79e53945 615 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 616 INTELPllInvalid("m1 out of range\n");
f2b115e6 617 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 618 INTELPllInvalid("m1 <= m2\n");
79e53945 619 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 620 INTELPllInvalid("m out of range\n");
79e53945 621 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 622 INTELPllInvalid("n out of range\n");
79e53945 623 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 624 INTELPllInvalid("vco out of range\n");
79e53945
JB		 625 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
626 * connector, etc., rather than just a single range.
627 */
628 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 629 INTELPllInvalid("dot out of range\n");
79e53945
JB		 630
631 return true;
632}
633
d4906093
ML		 634static bool
635intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 636 int target, int refclk, intel_clock_t *match_clock,
637 intel_clock_t *best_clock)
d4906093 638
79e53945
JB		 639{
640 struct drm_device *dev = crtc->dev;
79e53945 641 intel_clock_t clock;
79e53945
JB		 642 int err = target;
643
a210b028 644 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 645 /*
a210b028
DV		 646 * For LVDS just rely on its current settings for dual-channel.
647 * We haven't figured out how to reliably set up different
648 * single/dual channel state, if we even can.
79e53945 649 */
1974cad0 650 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 651 clock.p2 = limit->p2.p2_fast;
652 else
653 clock.p2 = limit->p2.p2_slow;
654 } else {
655 if (target < limit->p2.dot_limit)
656 clock.p2 = limit->p2.p2_slow;
657 else
658 clock.p2 = limit->p2.p2_fast;
659 }
660
0206e353 661 memset(best_clock, 0, sizeof(*best_clock));
79e53945 662
42158660
ZY		 663 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
664 clock.m1++) {
665 for (clock.m2 = limit->m2.min;
666 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 667 /* m1 is always 0 in Pineview */
668 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 669 break;
670 for (clock.n = limit->n.min;
671 clock.n <= limit->n.max; clock.n++) {
672 for (clock.p1 = limit->p1.min;
673 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 674 int this_err;
675
2177832f 676 intel_clock(dev, refclk, &clock);
1b894b59
CW		 677 if (!intel_PLL_is_valid(dev, limit,
678 &clock))
79e53945 679 continue;
cec2f356
SP		 680 if (match_clock &&
681 clock.p != match_clock->p)
682 continue;
79e53945
JB		 683
684 this_err = abs(clock.dot - target);
685 if (this_err < err) {
686 *best_clock = clock;
687 err = this_err;
688 }
689 }
690 }
691 }
692 }
693
694 return (err != target);
695}
696
d4906093
ML		 697static bool
698intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 699 int target, int refclk, intel_clock_t *match_clock,
700 intel_clock_t *best_clock)
d4906093
ML		 701{
702 struct drm_device *dev = crtc->dev;
d4906093
ML		 703 intel_clock_t clock;
704 int max_n;
705 bool found;
6ba770dc
AJ		 706 /* approximately equals target * 0.00585 */
707 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 708 found = false;
709
710 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 711 int lvds_reg;
712
c619eed4 713 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 714 lvds_reg = PCH_LVDS;
715 else
716 lvds_reg = LVDS;
1974cad0 717 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 718 clock.p2 = limit->p2.p2_fast;
719 else
720 clock.p2 = limit->p2.p2_slow;
721 } else {
722 if (target < limit->p2.dot_limit)
723 clock.p2 = limit->p2.p2_slow;
724 else
725 clock.p2 = limit->p2.p2_fast;
726 }
727
728 memset(best_clock, 0, sizeof(*best_clock));
729 max_n = limit->n.max;
f77f13e2 730 /* based on hardware requirement, prefer smaller n to precision */
d4906093 731 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 732 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 733 for (clock.m1 = limit->m1.max;
734 clock.m1 >= limit->m1.min; clock.m1--) {
735 for (clock.m2 = limit->m2.max;
736 clock.m2 >= limit->m2.min; clock.m2--) {
737 for (clock.p1 = limit->p1.max;
738 clock.p1 >= limit->p1.min; clock.p1--) {
739 int this_err;
740
2177832f 741 intel_clock(dev, refclk, &clock);
1b894b59
CW		 742 if (!intel_PLL_is_valid(dev, limit,
743 &clock))
d4906093 744 continue;
cec2f356
SP		 745 if (match_clock &&
746 clock.p != match_clock->p)
747 continue;
1b894b59
CW		 748
749 this_err = abs(clock.dot - target);
d4906093
ML		 750 if (this_err < err_most) {
751 *best_clock = clock;
752 err_most = this_err;
753 max_n = clock.n;
754 found = true;
755 }
756 }
757 }
758 }
759 }
2c07245f
ZW		 760 return found;
761}
762
5eb08b69 763static bool
f2b115e6 764intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 765 int target, int refclk, intel_clock_t *match_clock,
766 intel_clock_t *best_clock)
5eb08b69
ZW		 767{
768 struct drm_device *dev = crtc->dev;
769 intel_clock_t clock;
4547668a 770
5eb08b69
ZW		 771 if (target < 200000) {
772 clock.n = 1;
773 clock.p1 = 2;
774 clock.p2 = 10;
775 clock.m1 = 12;
776 clock.m2 = 9;
777 } else {
778 clock.n = 2;
779 clock.p1 = 1;
780 clock.p2 = 10;
781 clock.m1 = 14;
782 clock.m2 = 8;
783 }
784 intel_clock(dev, refclk, &clock);
785 memcpy(best_clock, &clock, sizeof(intel_clock_t));
786 return true;
787}
788
a4fc5ed6
KP		 789/* DisplayPort has only two frequencies, 162MHz and 270MHz */
790static bool
791intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 792 int target, int refclk, intel_clock_t *match_clock,
793 intel_clock_t *best_clock)
a4fc5ed6 794{
5eddb70b
CW		 795 intel_clock_t clock;
796 if (target < 200000) {
797 clock.p1 = 2;
798 clock.p2 = 10;
799 clock.n = 2;
800 clock.m1 = 23;
801 clock.m2 = 8;
802 } else {
803 clock.p1 = 1;
804 clock.p2 = 10;
805 clock.n = 1;
806 clock.m1 = 14;
807 clock.m2 = 2;
808 }
809 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
810 clock.p = (clock.p1 * clock.p2);
811 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
812 clock.vco = 0;
813 memcpy(best_clock, &clock, sizeof(intel_clock_t));
814 return true;
a4fc5ed6 815}
a0c4da24
JB		 816static bool
817intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
818 int target, int refclk, intel_clock_t *match_clock,
819 intel_clock_t *best_clock)
820{
821 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
822 u32 m, n, fastclk;
823 u32 updrate, minupdate, fracbits, p;
824 unsigned long bestppm, ppm, absppm;
825 int dotclk, flag;
826
af447bd3 827 flag = 0;
a0c4da24
JB		 828 dotclk = target * 1000;
829 bestppm = 1000000;
830 ppm = absppm = 0;
831 fastclk = dotclk / (2*100);
832 updrate = 0;
833 minupdate = 19200;
834 fracbits = 1;
835 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
836 bestm1 = bestm2 = bestp1 = bestp2 = 0;
837
838 /* based on hardware requirement, prefer smaller n to precision */
839 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
840 updrate = refclk / n;
841 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
842 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
843 if (p2 > 10)
844 p2 = p2 - 1;
845 p = p1 * p2;
846 /* based on hardware requirement, prefer bigger m1,m2 values */
847 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
848 m2 = (((2*(fastclk * p * n / m1 )) +
849 refclk) / (2*refclk));
850 m = m1 * m2;
851 vco = updrate * m;
852 if (vco >= limit->vco.min && vco < limit->vco.max) {
853 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
854 absppm = (ppm > 0) ? ppm : (-ppm);
855 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
856 bestppm = 0;
857 flag = 1;
858 }
859 if (absppm < bestppm - 10) {
860 bestppm = absppm;
861 flag = 1;
862 }
863 if (flag) {
864 bestn = n;
865 bestm1 = m1;
866 bestm2 = m2;
867 bestp1 = p1;
868 bestp2 = p2;
869 flag = 0;
870 }
871 }
872 }
873 }
874 }
875 }
876 best_clock->n = bestn;
877 best_clock->m1 = bestm1;
878 best_clock->m2 = bestm2;
879 best_clock->p1 = bestp1;
880 best_clock->p2 = bestp2;
881
882 return true;
883}
a4fc5ed6 884
a5c961d1
PZ		 885enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
886 enum pipe pipe)
887{
888 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
889 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
890
891 return intel_crtc->cpu_transcoder;
892}
893
a928d536
PZ		 894static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
895{
896 struct drm_i915_private *dev_priv = dev->dev_private;
897 u32 frame, frame_reg = PIPEFRAME(pipe);
898
899 frame = I915_READ(frame_reg);
900
901 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
902 DRM_DEBUG_KMS("vblank wait timed out\n");
903}
904
9d0498a2
JB		 905/**
906 * intel_wait_for_vblank - wait for vblank on a given pipe
907 * @dev: drm device
908 * @pipe: pipe to wait for
909 *
910 * Wait for vblank to occur on a given pipe. Needed for various bits of
911 * mode setting code.
912 */
913void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 914{
9d0498a2 915 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 916 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 917
a928d536
PZ		 918 if (INTEL_INFO(dev)->gen >= 5) {
919 ironlake_wait_for_vblank(dev, pipe);
920 return;
921 }
922
300387c0
CW		 923 /* Clear existing vblank status. Note this will clear any other
924 * sticky status fields as well.
925 *
926 * This races with i915_driver_irq_handler() with the result
927 * that either function could miss a vblank event. Here it is not
928 * fatal, as we will either wait upon the next vblank interrupt or
929 * timeout. Generally speaking intel_wait_for_vblank() is only
930 * called during modeset at which time the GPU should be idle and
931 * should *not* be performing page flips and thus not waiting on
932 * vblanks...
933 * Currently, the result of us stealing a vblank from the irq
934 * handler is that a single frame will be skipped during swapbuffers.
935 */
936 I915_WRITE(pipestat_reg,
937 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
938
9d0498a2 939 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 940 if (wait_for(I915_READ(pipestat_reg) &
941 PIPE_VBLANK_INTERRUPT_STATUS,
942 50))
9d0498a2
JB		 943 DRM_DEBUG_KMS("vblank wait timed out\n");
944}
945
ab7ad7f6
KP		 946/*
947 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 948 * @dev: drm device
949 * @pipe: pipe to wait for
950 *
951 * After disabling a pipe, we can't wait for vblank in the usual way,
952 * spinning on the vblank interrupt status bit, since we won't actually
953 * see an interrupt when the pipe is disabled.
954 *
ab7ad7f6
KP		 955 * On Gen4 and above:
956 * wait for the pipe register state bit to turn off
957 *
958 * Otherwise:
959 * wait for the display line value to settle (it usually
960 * ends up stopping at the start of the next frame).
58e10eb9 961 *
9d0498a2 962 */
58e10eb9 963void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 964{
965 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 966 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
967 pipe);
ab7ad7f6
KP		 968
969 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 970 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 971
972 /* Wait for the Pipe State to go off */
58e10eb9
CW		 973 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
974 100))
284637d9 975 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 976 } else {
837ba00f 977 u32 last_line, line_mask;
58e10eb9 978 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 979 unsigned long timeout = jiffies + msecs_to_jiffies(100);
980
837ba00f
PZ		 981 if (IS_GEN2(dev))
982 line_mask = DSL_LINEMASK_GEN2;
983 else
984 line_mask = DSL_LINEMASK_GEN3;
985
ab7ad7f6
KP		 986 /* Wait for the display line to settle */
987 do {
837ba00f 988 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 989 mdelay(5);
837ba00f 990 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 991 time_after(timeout, jiffies));
992 if (time_after(jiffies, timeout))
284637d9 993 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 994 }
79e53945
JB		 995}
996
b24e7179
JB		 997static const char *state_string(bool enabled)
998{
999 return enabled ? "on" : "off";
1000}
1001
1002/* Only for pre-ILK configs */
1003static void assert_pll(struct drm_i915_private *dev_priv,
1004 enum pipe pipe, bool state)
1005{
1006 int reg;
1007 u32 val;
1008 bool cur_state;
1009
1010 reg = DPLL(pipe);
1011 val = I915_READ(reg);
1012 cur_state = !!(val & DPLL_VCO_ENABLE);
1013 WARN(cur_state != state,
1014 "PLL state assertion failure (expected %s, current %s)\n",
1015 state_string(state), state_string(cur_state));
1016}
1017#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1018#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1019
040484af
JB		 1020/* For ILK+ */
1021static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1022 struct intel_pch_pll *pll,
1023 struct intel_crtc *crtc,
1024 bool state)
040484af 1025{
040484af
JB		 1026 u32 val;
1027 bool cur_state;
1028
9d82aa17
ED		 1029 if (HAS_PCH_LPT(dev_priv->dev)) {
1030 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1031 return;
1032 }
1033
92b27b08
CW		 1034 if (WARN (!pll,
1035 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1036 return;
ee7b9f93 1037
92b27b08
CW		 1038 val = I915_READ(pll->pll_reg);
1039 cur_state = !!(val & DPLL_VCO_ENABLE);
1040 WARN(cur_state != state,
1041 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1042 pll->pll_reg, state_string(state), state_string(cur_state), val);
1043
1044 /* Make sure the selected PLL is correctly attached to the transcoder */
1045 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1046 u32 pch_dpll;
1047
1048 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1049 cur_state = pll->pll_reg == _PCH_DPLL_B;
1050 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1051 "PLL[%d] not attached to this transcoder %d: %08x\n",
1052 cur_state, crtc->pipe, pch_dpll)) {
1053 cur_state = !!(val >> (4*crtc->pipe + 3));
1054 WARN(cur_state != state,
1055 "PLL[%d] not %s on this transcoder %d: %08x\n",
1056 pll->pll_reg == _PCH_DPLL_B,
1057 state_string(state),
1058 crtc->pipe,
1059 val);
1060 }
d3ccbe86 1061 }
040484af 1062}
92b27b08
CW		 1063#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1064#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1065
1066static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1067 enum pipe pipe, bool state)
1068{
1069 int reg;
1070 u32 val;
1071 bool cur_state;
ad80a810
PZ		 1072 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1073 pipe);
040484af 1074
affa9354
PZ		 1075 if (HAS_DDI(dev_priv->dev)) {
1076 /* DDI does not have a specific FDI_TX register */
ad80a810 1077 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1078 val = I915_READ(reg);
ad80a810 1079 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1080 } else {
1081 reg = FDI_TX_CTL(pipe);
1082 val = I915_READ(reg);
1083 cur_state = !!(val & FDI_TX_ENABLE);
1084 }
040484af
JB		 1085 WARN(cur_state != state,
1086 "FDI TX state assertion failure (expected %s, current %s)\n",
1087 state_string(state), state_string(cur_state));
1088}
1089#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1090#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1091
1092static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1093 enum pipe pipe, bool state)
1094{
1095 int reg;
1096 u32 val;
1097 bool cur_state;
1098
d63fa0dc
PZ		 1099 reg = FDI_RX_CTL(pipe);
1100 val = I915_READ(reg);
1101 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1102 WARN(cur_state != state,
1103 "FDI RX state assertion failure (expected %s, current %s)\n",
1104 state_string(state), state_string(cur_state));
1105}
1106#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1107#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1108
1109static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1110 enum pipe pipe)
1111{
1112 int reg;
1113 u32 val;
1114
1115 /* ILK FDI PLL is always enabled */
1116 if (dev_priv->info->gen == 5)
1117 return;
1118
bf507ef7 1119 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1120 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1121 return;
1122
040484af
JB		 1123 reg = FDI_TX_CTL(pipe);
1124 val = I915_READ(reg);
1125 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1126}
1127
1128static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1129 enum pipe pipe)
1130{
1131 int reg;
1132 u32 val;
1133
1134 reg = FDI_RX_CTL(pipe);
1135 val = I915_READ(reg);
1136 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1137}
1138
ea0760cf
JB		 1139static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1140 enum pipe pipe)
1141{
1142 int pp_reg, lvds_reg;
1143 u32 val;
1144 enum pipe panel_pipe = PIPE_A;
0de3b485 1145 bool locked = true;
ea0760cf
JB		 1146
1147 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1148 pp_reg = PCH_PP_CONTROL;
1149 lvds_reg = PCH_LVDS;
1150 } else {
1151 pp_reg = PP_CONTROL;
1152 lvds_reg = LVDS;
1153 }
1154
1155 val = I915_READ(pp_reg);
1156 if (!(val & PANEL_POWER_ON) ||
1157 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1158 locked = false;
1159
1160 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1161 panel_pipe = PIPE_B;
1162
1163 WARN(panel_pipe == pipe && locked,
1164 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1165 pipe_name(pipe));
ea0760cf
JB		 1166}
1167
b840d907
JB		 1168void assert_pipe(struct drm_i915_private *dev_priv,
1169 enum pipe pipe, bool state)
b24e7179
JB		 1170{
1171 int reg;
1172 u32 val;
63d7bbe9 1173 bool cur_state;
702e7a56
PZ		 1174 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1175 pipe);
b24e7179 1176
8e636784
DV		 1177 /* if we need the pipe A quirk it must be always on */
1178 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1179 state = true;
1180
702e7a56 1181 reg = PIPECONF(cpu_transcoder);
b24e7179 1182 val = I915_READ(reg);
63d7bbe9
JB		 1183 cur_state = !!(val & PIPECONF_ENABLE);
1184 WARN(cur_state != state,
1185 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1186 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1187}
1188
931872fc
CW		 1189static void assert_plane(struct drm_i915_private *dev_priv,
1190 enum plane plane, bool state)
b24e7179
JB		 1191{
1192 int reg;
1193 u32 val;
931872fc 1194 bool cur_state;
b24e7179
JB		 1195
1196 reg = DSPCNTR(plane);
1197 val = I915_READ(reg);
931872fc
CW		 1198 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1199 WARN(cur_state != state,
1200 "plane %c assertion failure (expected %s, current %s)\n",
1201 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1202}
1203
931872fc
CW		 1204#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1205#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1206
b24e7179
JB		 1207static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1208 enum pipe pipe)
1209{
1210 int reg, i;
1211 u32 val;
1212 int cur_pipe;
1213
19ec1358 1214 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 1215 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1216 reg = DSPCNTR(pipe);
1217 val = I915_READ(reg);
1218 WARN((val & DISPLAY_PLANE_ENABLE),
1219 "plane %c assertion failure, should be disabled but not\n",
1220 plane_name(pipe));
19ec1358 1221 return;
28c05794 1222 }
19ec1358 1223
b24e7179
JB		 1224 /* Need to check both planes against the pipe */
1225 for (i = 0; i < 2; i++) {
1226 reg = DSPCNTR(i);
1227 val = I915_READ(reg);
1228 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1229 DISPPLANE_SEL_PIPE_SHIFT;
1230 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1231 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1232 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1233 }
1234}
1235
92f2584a
JB		 1236static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1237{
1238 u32 val;
1239 bool enabled;
1240
9d82aa17
ED		 1241 if (HAS_PCH_LPT(dev_priv->dev)) {
1242 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1243 return;
1244 }
1245
92f2584a
JB		 1246 val = I915_READ(PCH_DREF_CONTROL);
1247 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1248 DREF_SUPERSPREAD_SOURCE_MASK));
1249 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1250}
1251
1252static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1253 enum pipe pipe)
1254{
1255 int reg;
1256 u32 val;
1257 bool enabled;
1258
1259 reg = TRANSCONF(pipe);
1260 val = I915_READ(reg);
1261 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1262 WARN(enabled,
1263 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1264 pipe_name(pipe));
92f2584a
JB		 1265}
1266
4e634389
KP		 1267static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1268 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1269{
1270 if ((val & DP_PORT_EN) == 0)
1271 return false;
1272
1273 if (HAS_PCH_CPT(dev_priv->dev)) {
1274 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1275 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1276 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1277 return false;
1278 } else {
1279 if ((val & DP_PIPE_MASK) != (pipe << 30))
1280 return false;
1281 }
1282 return true;
1283}
1284
1519b995
KP		 1285static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1286 enum pipe pipe, u32 val)
1287{
1288 if ((val & PORT_ENABLE) == 0)
1289 return false;
1290
1291 if (HAS_PCH_CPT(dev_priv->dev)) {
1292 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1293 return false;
1294 } else {
1295 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1296 return false;
1297 }
1298 return true;
1299}
1300
1301static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1302 enum pipe pipe, u32 val)
1303{
1304 if ((val & LVDS_PORT_EN) == 0)
1305 return false;
1306
1307 if (HAS_PCH_CPT(dev_priv->dev)) {
1308 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1309 return false;
1310 } else {
1311 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1312 return false;
1313 }
1314 return true;
1315}
1316
1317static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1318 enum pipe pipe, u32 val)
1319{
1320 if ((val & ADPA_DAC_ENABLE) == 0)
1321 return false;
1322 if (HAS_PCH_CPT(dev_priv->dev)) {
1323 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1324 return false;
1325 } else {
1326 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1327 return false;
1328 }
1329 return true;
1330}
1331
291906f1 1332static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1333 enum pipe pipe, int reg, u32 port_sel)
291906f1 1334{
47a05eca 1335 u32 val = I915_READ(reg);
4e634389 1336 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1337 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1338 reg, pipe_name(pipe));
de9a35ab 1339
75c5da27
DV		 1340 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1341 && (val & DP_PIPEB_SELECT),
de9a35ab 1342 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1343}
1344
1345static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1346 enum pipe pipe, int reg)
1347{
47a05eca 1348 u32 val = I915_READ(reg);
b70ad586 1349 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1350 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1351 reg, pipe_name(pipe));
de9a35ab 1352
75c5da27
DV		 1353 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1354 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1355 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1356}
1357
1358static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1359 enum pipe pipe)
1360{
1361 int reg;
1362 u32 val;
291906f1 1363
f0575e92
KP		 1364 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1365 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1366 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1367
1368 reg = PCH_ADPA;
1369 val = I915_READ(reg);
b70ad586 1370 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1371 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1372 pipe_name(pipe));
291906f1
JB		 1373
1374 reg = PCH_LVDS;
1375 val = I915_READ(reg);
b70ad586 1376 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1377 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1378 pipe_name(pipe));
291906f1
JB		 1379
1380 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1381 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1382 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1383}
1384
63d7bbe9
JB		 1385/**
1386 * intel_enable_pll - enable a PLL
1387 * @dev_priv: i915 private structure
1388 * @pipe: pipe PLL to enable
1389 *
1390 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1391 * make sure the PLL reg is writable first though, since the panel write
1392 * protect mechanism may be enabled.
1393 *
1394 * Note! This is for pre-ILK only.
7434a255
TR		 1395 *
1396 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1397 */
1398static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1399{
1400 int reg;
1401 u32 val;
1402
1403 /* No really, not for ILK+ */
a0c4da24 1404 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1405
1406 /* PLL is protected by panel, make sure we can write it */
1407 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1408 assert_panel_unlocked(dev_priv, pipe);
1409
1410 reg = DPLL(pipe);
1411 val = I915_READ(reg);
1412 val |= DPLL_VCO_ENABLE;
1413
1414 /* We do this three times for luck */
1415 I915_WRITE(reg, val);
1416 POSTING_READ(reg);
1417 udelay(150); /* wait for warmup */
1418 I915_WRITE(reg, val);
1419 POSTING_READ(reg);
1420 udelay(150); /* wait for warmup */
1421 I915_WRITE(reg, val);
1422 POSTING_READ(reg);
1423 udelay(150); /* wait for warmup */
1424}
1425
1426/**
1427 * intel_disable_pll - disable a PLL
1428 * @dev_priv: i915 private structure
1429 * @pipe: pipe PLL to disable
1430 *
1431 * Disable the PLL for @pipe, making sure the pipe is off first.
1432 *
1433 * Note! This is for pre-ILK only.
1434 */
1435static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1436{
1437 int reg;
1438 u32 val;
1439
1440 /* Don't disable pipe A or pipe A PLLs if needed */
1441 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1442 return;
1443
1444 /* Make sure the pipe isn't still relying on us */
1445 assert_pipe_disabled(dev_priv, pipe);
1446
1447 reg = DPLL(pipe);
1448 val = I915_READ(reg);
1449 val &= ~DPLL_VCO_ENABLE;
1450 I915_WRITE(reg, val);
1451 POSTING_READ(reg);
1452}
1453
a416edef
ED		 1454/* SBI access */
1455static void
1456intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1457{
1458 unsigned long flags;
1459
1460 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1461 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1462 100)) {
1463 DRM_ERROR("timeout waiting for SBI to become ready\n");
1464 goto out_unlock;
1465 }
1466
1467 I915_WRITE(SBI_ADDR,
1468 (reg << 16));
1469 I915_WRITE(SBI_DATA,
1470 value);
1471 I915_WRITE(SBI_CTL_STAT,
1472 SBI_BUSY |
1473 SBI_CTL_OP_CRWR);
1474
39fb50f6 1475 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1476 100)) {
1477 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1478 goto out_unlock;
1479 }
1480
1481out_unlock:
1482 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1483}
1484
1485static u32
1486intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1487{
1488 unsigned long flags;
39fb50f6 1489 u32 value = 0;
a416edef
ED		 1490
1491 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1492 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1493 100)) {
1494 DRM_ERROR("timeout waiting for SBI to become ready\n");
1495 goto out_unlock;
1496 }
1497
1498 I915_WRITE(SBI_ADDR,
1499 (reg << 16));
1500 I915_WRITE(SBI_CTL_STAT,
1501 SBI_BUSY |
1502 SBI_CTL_OP_CRRD);
1503
39fb50f6 1504 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1505 100)) {
1506 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1507 goto out_unlock;
1508 }
1509
1510 value = I915_READ(SBI_DATA);
1511
1512out_unlock:
1513 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1514 return value;
1515}
1516
92f2584a 1517/**
b6b4e185 1518 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1519 * @dev_priv: i915 private structure
1520 * @pipe: pipe PLL to enable
1521 *
1522 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1523 * drives the transcoder clock.
1524 */
b6b4e185 1525static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1526{
ee7b9f93 1527 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1528 struct intel_pch_pll *pll;
92f2584a
JB		 1529 int reg;
1530 u32 val;
1531
48da64a8 1532 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1533 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1534 pll = intel_crtc->pch_pll;
1535 if (pll == NULL)
1536 return;
1537
1538 if (WARN_ON(pll->refcount == 0))
1539 return;
ee7b9f93
JB		 1540
1541 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1542 pll->pll_reg, pll->active, pll->on,
1543 intel_crtc->base.base.id);
92f2584a
JB		 1544
1545 /* PCH refclock must be enabled first */
1546 assert_pch_refclk_enabled(dev_priv);
1547
ee7b9f93 1548 if (pll->active++ && pll->on) {
92b27b08 1549 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1550 return;
1551 }
1552
1553 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1554
1555 reg = pll->pll_reg;
92f2584a
JB		 1556 val = I915_READ(reg);
1557 val |= DPLL_VCO_ENABLE;
1558 I915_WRITE(reg, val);
1559 POSTING_READ(reg);
1560 udelay(200);
ee7b9f93
JB		 1561
1562 pll->on = true;
92f2584a
JB		 1563}
1564
ee7b9f93 1565static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1566{
ee7b9f93
JB		 1567 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1568 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1569 int reg;
ee7b9f93 1570 u32 val;
4c609cb8 1571
92f2584a
JB		 1572 /* PCH only available on ILK+ */
1573 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1574 if (pll == NULL)
1575 return;
92f2584a 1576
48da64a8
CW		 1577 if (WARN_ON(pll->refcount == 0))
1578 return;
7a419866 1579
ee7b9f93
JB		 1580 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1581 pll->pll_reg, pll->active, pll->on,
1582 intel_crtc->base.base.id);
7a419866 1583
48da64a8 1584 if (WARN_ON(pll->active == 0)) {
92b27b08 1585 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1586 return;
1587 }
1588
ee7b9f93 1589 if (--pll->active) {
92b27b08 1590 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1591 return;
ee7b9f93
JB		 1592 }
1593
1594 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1595
1596 /* Make sure transcoder isn't still depending on us */
1597 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1598
ee7b9f93 1599 reg = pll->pll_reg;
92f2584a
JB		 1600 val = I915_READ(reg);
1601 val &= ~DPLL_VCO_ENABLE;
1602 I915_WRITE(reg, val);
1603 POSTING_READ(reg);
1604 udelay(200);
ee7b9f93
JB		 1605
1606 pll->on = false;
92f2584a
JB		 1607}
1608
b8a4f404
PZ		 1609static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1610 enum pipe pipe)
040484af 1611{
23670b32 1612 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1613 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1614 uint32_t reg, val, pipeconf_val;
040484af
JB		 1615
1616 /* PCH only available on ILK+ */
1617 BUG_ON(dev_priv->info->gen < 5);
1618
1619 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1620 assert_pch_pll_enabled(dev_priv,
1621 to_intel_crtc(crtc)->pch_pll,
1622 to_intel_crtc(crtc));
040484af
JB		 1623
1624 /* FDI must be feeding us bits for PCH ports */
1625 assert_fdi_tx_enabled(dev_priv, pipe);
1626 assert_fdi_rx_enabled(dev_priv, pipe);
1627
23670b32
DV		 1628 if (HAS_PCH_CPT(dev)) {
1629 /* Workaround: Set the timing override bit before enabling the
1630 * pch transcoder. */
1631 reg = TRANS_CHICKEN2(pipe);
1632 val = I915_READ(reg);
1633 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1634 I915_WRITE(reg, val);
59c859d6 1635 }
23670b32 1636
040484af
JB		 1637 reg = TRANSCONF(pipe);
1638 val = I915_READ(reg);
5f7f726d 1639 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1640
1641 if (HAS_PCH_IBX(dev_priv->dev)) {
1642 /*
1643 * make the BPC in transcoder be consistent with
1644 * that in pipeconf reg.
1645 */
1646 val &= ~PIPE_BPC_MASK;
5f7f726d 1647 val |= pipeconf_val & PIPE_BPC_MASK;
e9bcff5c 1648 }
5f7f726d
PZ		 1649
1650 val &= ~TRANS_INTERLACE_MASK;
1651 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1652 if (HAS_PCH_IBX(dev_priv->dev) &&
1653 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1654 val |= TRANS_LEGACY_INTERLACED_ILK;
1655 else
1656 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1657 else
1658 val |= TRANS_PROGRESSIVE;
1659
040484af
JB		 1660 I915_WRITE(reg, val | TRANS_ENABLE);
1661 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1662 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1663}
1664
8fb033d7 1665static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1666 enum transcoder cpu_transcoder)
040484af 1667{
8fb033d7 1668 u32 val, pipeconf_val;
8fb033d7
PZ		 1669
1670 /* PCH only available on ILK+ */
1671 BUG_ON(dev_priv->info->gen < 5);
1672
8fb033d7 1673 /* FDI must be feeding us bits for PCH ports */
937bb610
PZ		 1674 assert_fdi_tx_enabled(dev_priv, cpu_transcoder);
1675 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1676
223a6fdf
PZ		 1677 /* Workaround: set timing override bit. */
1678 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1679 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1680 I915_WRITE(_TRANSA_CHICKEN2, val);
1681
25f3ef11 1682 val = TRANS_ENABLE;
937bb610 1683 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1684
9a76b1c6
PZ		 1685 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1686 PIPECONF_INTERLACED_ILK)
a35f2679 1687 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1688 else
1689 val |= TRANS_PROGRESSIVE;
1690
25f3ef11 1691 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
937bb610
PZ		 1692 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1693 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1694}
1695
b8a4f404
PZ		 1696static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1697 enum pipe pipe)
040484af 1698{
23670b32
DV		 1699 struct drm_device *dev = dev_priv->dev;
1700 uint32_t reg, val;
040484af
JB		 1701
1702 /* FDI relies on the transcoder */
1703 assert_fdi_tx_disabled(dev_priv, pipe);
1704 assert_fdi_rx_disabled(dev_priv, pipe);
1705
291906f1
JB		 1706 /* Ports must be off as well */
1707 assert_pch_ports_disabled(dev_priv, pipe);
1708
040484af
JB		 1709 reg = TRANSCONF(pipe);
1710 val = I915_READ(reg);
1711 val &= ~TRANS_ENABLE;
1712 I915_WRITE(reg, val);
1713 /* wait for PCH transcoder off, transcoder state */
1714 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1715 DRM_ERROR("failed to disable transcoder %d\n", pipe);
23670b32
DV		 1716
1717 if (!HAS_PCH_IBX(dev)) {
1718 /* Workaround: Clear the timing override chicken bit again. */
1719 reg = TRANS_CHICKEN2(pipe);
1720 val = I915_READ(reg);
1721 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1722 I915_WRITE(reg, val);
1723 }
040484af
JB		 1724}
1725
ab4d966c 1726static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1727{
8fb033d7
PZ		 1728 u32 val;
1729
8a52fd9f 1730 val = I915_READ(_TRANSACONF);
8fb033d7 1731 val &= ~TRANS_ENABLE;
8a52fd9f 1732 I915_WRITE(_TRANSACONF, val);
8fb033d7 1733 /* wait for PCH transcoder off, transcoder state */
8a52fd9f
PZ		 1734 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1735 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1736
1737 /* Workaround: clear timing override bit. */
1738 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1739 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1740 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1741}
1742
b24e7179 1743/**
309cfea8 1744 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1745 * @dev_priv: i915 private structure
1746 * @pipe: pipe to enable
040484af 1747 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1748 *
1749 * Enable @pipe, making sure that various hardware specific requirements
1750 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1751 *
1752 * @pipe should be %PIPE_A or %PIPE_B.
1753 *
1754 * Will wait until the pipe is actually running (i.e. first vblank) before
1755 * returning.
1756 */
040484af
JB		 1757static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1758 bool pch_port)
b24e7179 1759{
702e7a56
PZ		 1760 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1761 pipe);
cc391bbb 1762 enum transcoder pch_transcoder;
b24e7179
JB		 1763 int reg;
1764 u32 val;
1765
cc391bbb
PZ		 1766 if (IS_HASWELL(dev_priv->dev))
1767 pch_transcoder = TRANSCODER_A;
1768 else
1769 pch_transcoder = pipe;
1770
b24e7179
JB		 1771 /*
1772 * A pipe without a PLL won't actually be able to drive bits from
1773 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1774 * need the check.
1775 */
1776 if (!HAS_PCH_SPLIT(dev_priv->dev))
1777 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1778 else {
1779 if (pch_port) {
1780 /* if driving the PCH, we need FDI enabled */
cc391bbb
PZ		 1781 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1782 assert_fdi_tx_pll_enabled(dev_priv, cpu_transcoder);
040484af
JB		 1783 }
1784 /* FIXME: assert CPU port conditions for SNB+ */
1785 }
b24e7179 1786
702e7a56 1787 reg = PIPECONF(cpu_transcoder);
b24e7179 1788 val = I915_READ(reg);
00d70b15
CW		 1789 if (val & PIPECONF_ENABLE)
1790 return;
1791
1792 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1793 intel_wait_for_vblank(dev_priv->dev, pipe);
1794}
1795
1796/**
309cfea8 1797 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1798 * @dev_priv: i915 private structure
1799 * @pipe: pipe to disable
1800 *
1801 * Disable @pipe, making sure that various hardware specific requirements
1802 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1803 *
1804 * @pipe should be %PIPE_A or %PIPE_B.
1805 *
1806 * Will wait until the pipe has shut down before returning.
1807 */
1808static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1809 enum pipe pipe)
1810{
702e7a56
PZ		 1811 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1812 pipe);
b24e7179
JB		 1813 int reg;
1814 u32 val;
1815
1816 /*
1817 * Make sure planes won't keep trying to pump pixels to us,
1818 * or we might hang the display.
1819 */
1820 assert_planes_disabled(dev_priv, pipe);
1821
1822 /* Don't disable pipe A or pipe A PLLs if needed */
1823 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1824 return;
1825
702e7a56 1826 reg = PIPECONF(cpu_transcoder);
b24e7179 1827 val = I915_READ(reg);
00d70b15
CW		 1828 if ((val & PIPECONF_ENABLE) == 0)
1829 return;
1830
1831 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1832 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1833}
1834
d74362c9
KP		 1835/*
1836 * Plane regs are double buffered, going from enabled->disabled needs a
1837 * trigger in order to latch. The display address reg provides this.
1838 */
6f1d69b0 1839void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1840 enum plane plane)
1841{
14f86147
DL		 1842 if (dev_priv->info->gen >= 4)
1843 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1844 else
1845 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1846}
1847
b24e7179
JB		 1848/**
1849 * intel_enable_plane - enable a display plane on a given pipe
1850 * @dev_priv: i915 private structure
1851 * @plane: plane to enable
1852 * @pipe: pipe being fed
1853 *
1854 * Enable @plane on @pipe, making sure that @pipe is running first.
1855 */
1856static void intel_enable_plane(struct drm_i915_private *dev_priv,
1857 enum plane plane, enum pipe pipe)
1858{
1859 int reg;
1860 u32 val;
1861
1862 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1863 assert_pipe_enabled(dev_priv, pipe);
1864
1865 reg = DSPCNTR(plane);
1866 val = I915_READ(reg);
00d70b15
CW		 1867 if (val & DISPLAY_PLANE_ENABLE)
1868 return;
1869
1870 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1871 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1872 intel_wait_for_vblank(dev_priv->dev, pipe);
1873}
1874
b24e7179
JB		 1875/**
1876 * intel_disable_plane - disable a display plane
1877 * @dev_priv: i915 private structure
1878 * @plane: plane to disable
1879 * @pipe: pipe consuming the data
1880 *
1881 * Disable @plane; should be an independent operation.
1882 */
1883static void intel_disable_plane(struct drm_i915_private *dev_priv,
1884 enum plane plane, enum pipe pipe)
1885{
1886 int reg;
1887 u32 val;
1888
1889 reg = DSPCNTR(plane);
1890 val = I915_READ(reg);
00d70b15
CW		 1891 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1892 return;
1893
1894 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1895 intel_flush_display_plane(dev_priv, plane);
1896 intel_wait_for_vblank(dev_priv->dev, pipe);
1897}
1898
127bd2ac 1899int
48b956c5 1900intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1901 struct drm_i915_gem_object *obj,
919926ae 1902 struct intel_ring_buffer *pipelined)
6b95a207 1903{
ce453d81 1904 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1905 u32 alignment;
1906 int ret;
1907
05394f39 1908 switch (obj->tiling_mode) {
6b95a207 1909 case I915_TILING_NONE:
534843da
CW		 1910 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1911 alignment = 128 * 1024;
a6c45cf0 1912 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1913 alignment = 4 * 1024;
1914 else
1915 alignment = 64 * 1024;
6b95a207
KH		 1916 break;
1917 case I915_TILING_X:
1918 /* pin() will align the object as required by fence */
1919 alignment = 0;
1920 break;
1921 case I915_TILING_Y:
1922 /* FIXME: Is this true? */
1923 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1924 return -EINVAL;
1925 default:
1926 BUG();
1927 }
1928
ce453d81 1929 dev_priv->mm.interruptible = false;
2da3b9b9 1930 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1931 if (ret)
ce453d81 1932 goto err_interruptible;
6b95a207
KH		 1933
1934 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1935 * fence, whereas 965+ only requires a fence if using
1936 * framebuffer compression. For simplicity, we always install
1937 * a fence as the cost is not that onerous.
1938 */
06d98131 1939 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1940 if (ret)
1941 goto err_unpin;
1690e1eb 1942
9a5a53b3 1943 i915_gem_object_pin_fence(obj);
6b95a207 1944
ce453d81 1945 dev_priv->mm.interruptible = true;
6b95a207 1946 return 0;
48b956c5
CW		 1947
1948err_unpin:
1949 i915_gem_object_unpin(obj);
ce453d81
CW		 1950err_interruptible:
1951 dev_priv->mm.interruptible = true;
48b956c5 1952 return ret;
6b95a207
KH		 1953}
1954
1690e1eb
CW		 1955void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1956{
1957 i915_gem_object_unpin_fence(obj);
1958 i915_gem_object_unpin(obj);
1959}
1960
c2c75131
DV		 1961/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1962 * is assumed to be a power-of-two. */
5a35e99e
DL		 1963unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
1964 unsigned int bpp,
1965 unsigned int pitch)
c2c75131
DV		 1966{
1967 int tile_rows, tiles;
1968
1969 tile_rows = *y / 8;
1970 *y %= 8;
1971 tiles = *x / (512/bpp);
1972 *x %= 512/bpp;
1973
1974 return tile_rows * pitch * 8 + tiles * 4096;
1975}
1976
17638cd6
JB		 1977static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1978 int x, int y)
81255565
JB		 1979{
1980 struct drm_device *dev = crtc->dev;
1981 struct drm_i915_private *dev_priv = dev->dev_private;
1982 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1983 struct intel_framebuffer *intel_fb;
05394f39 1984 struct drm_i915_gem_object *obj;
81255565 1985 int plane = intel_crtc->plane;
e506a0c6 1986 unsigned long linear_offset;
81255565 1987 u32 dspcntr;
5eddb70b 1988 u32 reg;
81255565
JB		 1989
1990 switch (plane) {
1991 case 0:
1992 case 1:
1993 break;
1994 default:
1995 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1996 return -EINVAL;
1997 }
1998
1999 intel_fb = to_intel_framebuffer(fb);
2000 obj = intel_fb->obj;
81255565 2001
5eddb70b
CW		 2002 reg = DSPCNTR(plane);
2003 dspcntr = I915_READ(reg);
81255565
JB		 2004 /* Mask out pixel format bits in case we change it */
2005 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2006 switch (fb->pixel_format) {
2007 case DRM_FORMAT_C8:
81255565
JB		 2008 dspcntr |= DISPPLANE_8BPP;
2009 break;
57779d06
VS		 2010 case DRM_FORMAT_XRGB1555:
2011 case DRM_FORMAT_ARGB1555:
2012 dspcntr |= DISPPLANE_BGRX555;
81255565 2013 break;
57779d06
VS		 2014 case DRM_FORMAT_RGB565:
2015 dspcntr |= DISPPLANE_BGRX565;
2016 break;
2017 case DRM_FORMAT_XRGB8888:
2018 case DRM_FORMAT_ARGB8888:
2019 dspcntr |= DISPPLANE_BGRX888;
2020 break;
2021 case DRM_FORMAT_XBGR8888:
2022 case DRM_FORMAT_ABGR8888:
2023 dspcntr |= DISPPLANE_RGBX888;
2024 break;
2025 case DRM_FORMAT_XRGB2101010:
2026 case DRM_FORMAT_ARGB2101010:
2027 dspcntr |= DISPPLANE_BGRX101010;
2028 break;
2029 case DRM_FORMAT_XBGR2101010:
2030 case DRM_FORMAT_ABGR2101010:
2031 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2032 break;
2033 default:
57779d06 2034 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
81255565
JB		 2035 return -EINVAL;
2036 }
57779d06 2037
a6c45cf0 2038 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2039 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2040 dspcntr |= DISPPLANE_TILED;
2041 else
2042 dspcntr &= ~DISPPLANE_TILED;
2043 }
2044
5eddb70b 2045 I915_WRITE(reg, dspcntr);
81255565 2046
e506a0c6 2047 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2048
c2c75131
DV		 2049 if (INTEL_INFO(dev)->gen >= 4) {
2050 intel_crtc->dspaddr_offset =
5a35e99e
DL		 2051 intel_gen4_compute_offset_xtiled(&x, &y,
2052 fb->bits_per_pixel / 8,
2053 fb->pitches[0]);
c2c75131
DV		 2054 linear_offset -= intel_crtc->dspaddr_offset;
2055 } else {
e506a0c6 2056 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2057 }
e506a0c6
DV		 2058
2059 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2060 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2061 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2062 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2063 I915_MODIFY_DISPBASE(DSPSURF(plane),
2064 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2065 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2066 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2067 } else
e506a0c6 2068 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2069 POSTING_READ(reg);
81255565 2070
17638cd6
JB		 2071 return 0;
2072}
2073
2074static int ironlake_update_plane(struct drm_crtc *crtc,
2075 struct drm_framebuffer *fb, int x, int y)
2076{
2077 struct drm_device *dev = crtc->dev;
2078 struct drm_i915_private *dev_priv = dev->dev_private;
2079 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2080 struct intel_framebuffer *intel_fb;
2081 struct drm_i915_gem_object *obj;
2082 int plane = intel_crtc->plane;
e506a0c6 2083 unsigned long linear_offset;
17638cd6
JB		 2084 u32 dspcntr;
2085 u32 reg;
2086
2087 switch (plane) {
2088 case 0:
2089 case 1:
27f8227b 2090 case 2:
17638cd6
JB		 2091 break;
2092 default:
2093 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2094 return -EINVAL;
2095 }
2096
2097 intel_fb = to_intel_framebuffer(fb);
2098 obj = intel_fb->obj;
2099
2100 reg = DSPCNTR(plane);
2101 dspcntr = I915_READ(reg);
2102 /* Mask out pixel format bits in case we change it */
2103 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2104 switch (fb->pixel_format) {
2105 case DRM_FORMAT_C8:
17638cd6
JB		 2106 dspcntr |= DISPPLANE_8BPP;
2107 break;
57779d06
VS		 2108 case DRM_FORMAT_RGB565:
2109 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2110 break;
57779d06
VS		 2111 case DRM_FORMAT_XRGB8888:
2112 case DRM_FORMAT_ARGB8888:
2113 dspcntr |= DISPPLANE_BGRX888;
2114 break;
2115 case DRM_FORMAT_XBGR8888:
2116 case DRM_FORMAT_ABGR8888:
2117 dspcntr |= DISPPLANE_RGBX888;
2118 break;
2119 case DRM_FORMAT_XRGB2101010:
2120 case DRM_FORMAT_ARGB2101010:
2121 dspcntr |= DISPPLANE_BGRX101010;
2122 break;
2123 case DRM_FORMAT_XBGR2101010:
2124 case DRM_FORMAT_ABGR2101010:
2125 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2126 break;
2127 default:
57779d06 2128 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
17638cd6
JB		 2129 return -EINVAL;
2130 }
2131
2132 if (obj->tiling_mode != I915_TILING_NONE)
2133 dspcntr |= DISPPLANE_TILED;
2134 else
2135 dspcntr &= ~DISPPLANE_TILED;
2136
2137 /* must disable */
2138 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2139
2140 I915_WRITE(reg, dspcntr);
2141
e506a0c6 2142 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2143 intel_crtc->dspaddr_offset =
5a35e99e
DL		 2144 intel_gen4_compute_offset_xtiled(&x, &y,
2145 fb->bits_per_pixel / 8,
2146 fb->pitches[0]);
c2c75131 2147 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2148
e506a0c6
DV		 2149 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2150 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2151 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2152 I915_MODIFY_DISPBASE(DSPSURF(plane),
2153 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2154 if (IS_HASWELL(dev)) {
2155 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2156 } else {
2157 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2158 I915_WRITE(DSPLINOFF(plane), linear_offset);
2159 }
17638cd6
JB		 2160 POSTING_READ(reg);
2161
2162 return 0;
2163}
2164
2165/* Assume fb object is pinned & idle & fenced and just update base pointers */
2166static int
2167intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2168 int x, int y, enum mode_set_atomic state)
2169{
2170 struct drm_device *dev = crtc->dev;
2171 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2172
6b8e6ed0
CW		 2173 if (dev_priv->display.disable_fbc)
2174 dev_priv->display.disable_fbc(dev);
3dec0095 2175 intel_increase_pllclock(crtc);
81255565 2176
6b8e6ed0 2177 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2178}
2179
14667a4b
CW		 2180static int
2181intel_finish_fb(struct drm_framebuffer *old_fb)
2182{
2183 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2184 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2185 bool was_interruptible = dev_priv->mm.interruptible;
2186 int ret;
2187
2188 wait_event(dev_priv->pending_flip_queue,
2189 atomic_read(&dev_priv->mm.wedged) ||
2190 atomic_read(&obj->pending_flip) == 0);
2191
2192 /* Big Hammer, we also need to ensure that any pending
2193 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2194 * current scanout is retired before unpinning the old
2195 * framebuffer.
2196 *
2197 * This should only fail upon a hung GPU, in which case we
2198 * can safely continue.
2199 */
2200 dev_priv->mm.interruptible = false;
2201 ret = i915_gem_object_finish_gpu(obj);
2202 dev_priv->mm.interruptible = was_interruptible;
2203
2204 return ret;
2205}
2206
198598d0
VS		 2207static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2208{
2209 struct drm_device *dev = crtc->dev;
2210 struct drm_i915_master_private *master_priv;
2211 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2212
2213 if (!dev->primary->master)
2214 return;
2215
2216 master_priv = dev->primary->master->driver_priv;
2217 if (!master_priv->sarea_priv)
2218 return;
2219
2220 switch (intel_crtc->pipe) {
2221 case 0:
2222 master_priv->sarea_priv->pipeA_x = x;
2223 master_priv->sarea_priv->pipeA_y = y;
2224 break;
2225 case 1:
2226 master_priv->sarea_priv->pipeB_x = x;
2227 master_priv->sarea_priv->pipeB_y = y;
2228 break;
2229 default:
2230 break;
2231 }
2232}
2233
5c3b82e2 2234static int
3c4fdcfb 2235intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2236 struct drm_framebuffer *fb)
79e53945
JB		 2237{
2238 struct drm_device *dev = crtc->dev;
6b8e6ed0 2239 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2240 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2241 struct drm_framebuffer *old_fb;
5c3b82e2 2242 int ret;
79e53945
JB		 2243
2244 /* no fb bound */
94352cf9 2245 if (!fb) {
a5071c2f 2246 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2247 return 0;
2248 }
2249
5826eca5
ED		 2250 if(intel_crtc->plane > dev_priv->num_pipe) {
2251 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2252 intel_crtc->plane,
2253 dev_priv->num_pipe);
5c3b82e2 2254 return -EINVAL;
79e53945
JB		 2255 }
2256
5c3b82e2 2257 mutex_lock(&dev->struct_mutex);
265db958 2258 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2259 to_intel_framebuffer(fb)->obj,
919926ae 2260 NULL);
5c3b82e2
CW		 2261 if (ret != 0) {
2262 mutex_unlock(&dev->struct_mutex);
a5071c2f 2263 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2264 return ret;
2265 }
79e53945 2266
94352cf9
DV		 2267 if (crtc->fb)
2268 intel_finish_fb(crtc->fb);
265db958 2269
94352cf9 2270 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2271 if (ret) {
94352cf9 2272 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2273 mutex_unlock(&dev->struct_mutex);
a5071c2f 2274 DRM_ERROR("failed to update base address\n");
4e6cfefc 2275 return ret;
79e53945 2276 }
3c4fdcfb 2277
94352cf9
DV		 2278 old_fb = crtc->fb;
2279 crtc->fb = fb;
6c4c86f5
DV		 2280 crtc->x = x;
2281 crtc->y = y;
94352cf9 2282
b7f1de28
CW		 2283 if (old_fb) {
2284 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2285 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2286 }
652c393a 2287
6b8e6ed0 2288 intel_update_fbc(dev);
5c3b82e2 2289 mutex_unlock(&dev->struct_mutex);
79e53945 2290
198598d0 2291 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2292
2293 return 0;
79e53945
JB		 2294}
2295
5eddb70b 2296static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2297{
2298 struct drm_device *dev = crtc->dev;
2299 struct drm_i915_private *dev_priv = dev->dev_private;
2300 u32 dpa_ctl;
2301
28c97730 2302 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2303 dpa_ctl = I915_READ(DP_A);
2304 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2305
2306 if (clock < 200000) {
2307 u32 temp;
2308 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2309 /* workaround for 160Mhz:
2310 1) program 0x4600c bits 15:0 = 0x8124
2311 2) program 0x46010 bit 0 = 1
2312 3) program 0x46034 bit 24 = 1
2313 4) program 0x64000 bit 14 = 1
2314 */
2315 temp = I915_READ(0x4600c);
2316 temp &= 0xffff0000;
2317 I915_WRITE(0x4600c, temp | 0x8124);
2318
2319 temp = I915_READ(0x46010);
2320 I915_WRITE(0x46010, temp | 1);
2321
2322 temp = I915_READ(0x46034);
2323 I915_WRITE(0x46034, temp | (1 << 24));
2324 } else {
2325 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2326 }
2327 I915_WRITE(DP_A, dpa_ctl);
2328
5eddb70b 2329 POSTING_READ(DP_A);
32f9d658
ZW		 2330 udelay(500);
2331}
2332
5e84e1a4
ZW		 2333static void intel_fdi_normal_train(struct drm_crtc *crtc)
2334{
2335 struct drm_device *dev = crtc->dev;
2336 struct drm_i915_private *dev_priv = dev->dev_private;
2337 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2338 int pipe = intel_crtc->pipe;
2339 u32 reg, temp;
2340
2341 /* enable normal train */
2342 reg = FDI_TX_CTL(pipe);
2343 temp = I915_READ(reg);
61e499bf 2344 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2345 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2346 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2347 } else {
2348 temp &= ~FDI_LINK_TRAIN_NONE;
2349 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2350 }
5e84e1a4
ZW		 2351 I915_WRITE(reg, temp);
2352
2353 reg = FDI_RX_CTL(pipe);
2354 temp = I915_READ(reg);
2355 if (HAS_PCH_CPT(dev)) {
2356 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2357 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2358 } else {
2359 temp &= ~FDI_LINK_TRAIN_NONE;
2360 temp |= FDI_LINK_TRAIN_NONE;
2361 }
2362 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2363
2364 /* wait one idle pattern time */
2365 POSTING_READ(reg);
2366 udelay(1000);
357555c0
JB		 2367
2368 /* IVB wants error correction enabled */
2369 if (IS_IVYBRIDGE(dev))
2370 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2371 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2372}
2373
291427f5
JB		 2374static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2375{
2376 struct drm_i915_private *dev_priv = dev->dev_private;
2377 u32 flags = I915_READ(SOUTH_CHICKEN1);
2378
2379 flags |= FDI_PHASE_SYNC_OVR(pipe);
2380 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2381 flags |= FDI_PHASE_SYNC_EN(pipe);
2382 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2383 POSTING_READ(SOUTH_CHICKEN1);
2384}
2385
01a415fd
DV		 2386static void ivb_modeset_global_resources(struct drm_device *dev)
2387{
2388 struct drm_i915_private *dev_priv = dev->dev_private;
2389 struct intel_crtc *pipe_B_crtc =
2390 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2391 struct intel_crtc *pipe_C_crtc =
2392 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2393 uint32_t temp;
2394
2395 /* When everything is off disable fdi C so that we could enable fdi B
2396 * with all lanes. XXX: This misses the case where a pipe is not using
2397 * any pch resources and so doesn't need any fdi lanes. */
2398 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2399 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2400 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2401
2402 temp = I915_READ(SOUTH_CHICKEN1);
2403 temp &= ~FDI_BC_BIFURCATION_SELECT;
2404 DRM_DEBUG_KMS("disabling fdi C rx\n");
2405 I915_WRITE(SOUTH_CHICKEN1, temp);
2406 }
2407}
2408
8db9d77b
ZW		 2409/* The FDI link training functions for ILK/Ibexpeak. */
2410static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2411{
2412 struct drm_device *dev = crtc->dev;
2413 struct drm_i915_private *dev_priv = dev->dev_private;
2414 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2415 int pipe = intel_crtc->pipe;
0fc932b8 2416 int plane = intel_crtc->plane;
5eddb70b 2417 u32 reg, temp, tries;
8db9d77b 2418
0fc932b8
JB		 2419 /* FDI needs bits from pipe & plane first */
2420 assert_pipe_enabled(dev_priv, pipe);
2421 assert_plane_enabled(dev_priv, plane);
2422
e1a44743
AJ		 2423 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2424 for train result */
5eddb70b
CW		 2425 reg = FDI_RX_IMR(pipe);
2426 temp = I915_READ(reg);
e1a44743
AJ		 2427 temp &= ~FDI_RX_SYMBOL_LOCK;
2428 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2429 I915_WRITE(reg, temp);
2430 I915_READ(reg);
e1a44743
AJ		 2431 udelay(150);
2432
8db9d77b 2433 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2434 reg = FDI_TX_CTL(pipe);
2435 temp = I915_READ(reg);
77ffb597
AJ		 2436 temp &= ~(7 << 19);
2437 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2438 temp &= ~FDI_LINK_TRAIN_NONE;
2439 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2440 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2441
5eddb70b
CW		 2442 reg = FDI_RX_CTL(pipe);
2443 temp = I915_READ(reg);
8db9d77b
ZW		 2444 temp &= ~FDI_LINK_TRAIN_NONE;
2445 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2446 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2447
2448 POSTING_READ(reg);
8db9d77b
ZW		 2449 udelay(150);
2450
5b2adf89 2451 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2452 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2453 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2454 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2455
5eddb70b 2456 reg = FDI_RX_IIR(pipe);
e1a44743 2457 for (tries = 0; tries < 5; tries++) {
5eddb70b 2458 temp = I915_READ(reg);
8db9d77b
ZW		 2459 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2460
2461 if ((temp & FDI_RX_BIT_LOCK)) {
2462 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2463 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2464 break;
2465 }
8db9d77b 2466 }
e1a44743 2467 if (tries == 5)
5eddb70b 2468 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2469
2470 /* Train 2 */
5eddb70b
CW		 2471 reg = FDI_TX_CTL(pipe);
2472 temp = I915_READ(reg);
8db9d77b
ZW		 2473 temp &= ~FDI_LINK_TRAIN_NONE;
2474 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2475 I915_WRITE(reg, temp);
8db9d77b 2476
5eddb70b
CW		 2477 reg = FDI_RX_CTL(pipe);
2478 temp = I915_READ(reg);
8db9d77b
ZW		 2479 temp &= ~FDI_LINK_TRAIN_NONE;
2480 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2481 I915_WRITE(reg, temp);
8db9d77b 2482
5eddb70b
CW		 2483 POSTING_READ(reg);
2484 udelay(150);
8db9d77b 2485
5eddb70b 2486 reg = FDI_RX_IIR(pipe);
e1a44743 2487 for (tries = 0; tries < 5; tries++) {
5eddb70b 2488 temp = I915_READ(reg);
8db9d77b
ZW		 2489 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2490
2491 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2492 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2493 DRM_DEBUG_KMS("FDI train 2 done.\n");
2494 break;
2495 }
8db9d77b 2496 }
e1a44743 2497 if (tries == 5)
5eddb70b 2498 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2499
2500 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2501
8db9d77b
ZW		 2502}
2503
0206e353 2504static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2505 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2506 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2507 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2508 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2509};
2510
2511/* The FDI link training functions for SNB/Cougarpoint. */
2512static void gen6_fdi_link_train(struct drm_crtc *crtc)
2513{
2514 struct drm_device *dev = crtc->dev;
2515 struct drm_i915_private *dev_priv = dev->dev_private;
2516 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2517 int pipe = intel_crtc->pipe;
fa37d39e 2518 u32 reg, temp, i, retry;
8db9d77b 2519
e1a44743
AJ		 2520 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2521 for train result */
5eddb70b
CW		 2522 reg = FDI_RX_IMR(pipe);
2523 temp = I915_READ(reg);
e1a44743
AJ		 2524 temp &= ~FDI_RX_SYMBOL_LOCK;
2525 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2526 I915_WRITE(reg, temp);
2527
2528 POSTING_READ(reg);
e1a44743
AJ		 2529 udelay(150);
2530
8db9d77b 2531 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2532 reg = FDI_TX_CTL(pipe);
2533 temp = I915_READ(reg);
77ffb597
AJ		 2534 temp &= ~(7 << 19);
2535 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2536 temp &= ~FDI_LINK_TRAIN_NONE;
2537 temp |= FDI_LINK_TRAIN_PATTERN_1;
2538 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2539 /* SNB-B */
2540 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2541 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2542
d74cf324
DV		 2543 I915_WRITE(FDI_RX_MISC(pipe),
2544 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2545
5eddb70b
CW		 2546 reg = FDI_RX_CTL(pipe);
2547 temp = I915_READ(reg);
8db9d77b
ZW		 2548 if (HAS_PCH_CPT(dev)) {
2549 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2550 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2551 } else {
2552 temp &= ~FDI_LINK_TRAIN_NONE;
2553 temp |= FDI_LINK_TRAIN_PATTERN_1;
2554 }
5eddb70b
CW		 2555 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2556
2557 POSTING_READ(reg);
8db9d77b
ZW		 2558 udelay(150);
2559
8f5718a6 2560 cpt_phase_pointer_enable(dev, pipe);
291427f5 2561
0206e353 2562 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2563 reg = FDI_TX_CTL(pipe);
2564 temp = I915_READ(reg);
8db9d77b
ZW		 2565 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2566 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2567 I915_WRITE(reg, temp);
2568
2569 POSTING_READ(reg);
8db9d77b
ZW		 2570 udelay(500);
2571
fa37d39e
SP		 2572 for (retry = 0; retry < 5; retry++) {
2573 reg = FDI_RX_IIR(pipe);
2574 temp = I915_READ(reg);
2575 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2576 if (temp & FDI_RX_BIT_LOCK) {
2577 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2578 DRM_DEBUG_KMS("FDI train 1 done.\n");
2579 break;
2580 }
2581 udelay(50);
8db9d77b 2582 }
fa37d39e
SP		 2583 if (retry < 5)
2584 break;
8db9d77b
ZW		 2585 }
2586 if (i == 4)
5eddb70b 2587 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2588
2589 /* Train 2 */
5eddb70b
CW		 2590 reg = FDI_TX_CTL(pipe);
2591 temp = I915_READ(reg);
8db9d77b
ZW		 2592 temp &= ~FDI_LINK_TRAIN_NONE;
2593 temp |= FDI_LINK_TRAIN_PATTERN_2;
2594 if (IS_GEN6(dev)) {
2595 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2596 /* SNB-B */
2597 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2598 }
5eddb70b 2599 I915_WRITE(reg, temp);
8db9d77b 2600
5eddb70b
CW		 2601 reg = FDI_RX_CTL(pipe);
2602 temp = I915_READ(reg);
8db9d77b
ZW		 2603 if (HAS_PCH_CPT(dev)) {
2604 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2605 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2606 } else {
2607 temp &= ~FDI_LINK_TRAIN_NONE;
2608 temp |= FDI_LINK_TRAIN_PATTERN_2;
2609 }
5eddb70b
CW		 2610 I915_WRITE(reg, temp);
2611
2612 POSTING_READ(reg);
8db9d77b
ZW		 2613 udelay(150);
2614
0206e353 2615 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2616 reg = FDI_TX_CTL(pipe);
2617 temp = I915_READ(reg);
8db9d77b
ZW		 2618 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2619 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2620 I915_WRITE(reg, temp);
2621
2622 POSTING_READ(reg);
8db9d77b
ZW		 2623 udelay(500);
2624
fa37d39e
SP		 2625 for (retry = 0; retry < 5; retry++) {
2626 reg = FDI_RX_IIR(pipe);
2627 temp = I915_READ(reg);
2628 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2629 if (temp & FDI_RX_SYMBOL_LOCK) {
2630 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2631 DRM_DEBUG_KMS("FDI train 2 done.\n");
2632 break;
2633 }
2634 udelay(50);
8db9d77b 2635 }
fa37d39e
SP		 2636 if (retry < 5)
2637 break;
8db9d77b
ZW		 2638 }
2639 if (i == 4)
5eddb70b 2640 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2641
2642 DRM_DEBUG_KMS("FDI train done.\n");
2643}
2644
357555c0
JB		 2645/* Manual link training for Ivy Bridge A0 parts */
2646static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2647{
2648 struct drm_device *dev = crtc->dev;
2649 struct drm_i915_private *dev_priv = dev->dev_private;
2650 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2651 int pipe = intel_crtc->pipe;
2652 u32 reg, temp, i;
2653
2654 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2655 for train result */
2656 reg = FDI_RX_IMR(pipe);
2657 temp = I915_READ(reg);
2658 temp &= ~FDI_RX_SYMBOL_LOCK;
2659 temp &= ~FDI_RX_BIT_LOCK;
2660 I915_WRITE(reg, temp);
2661
2662 POSTING_READ(reg);
2663 udelay(150);
2664
01a415fd
DV		 2665 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2666 I915_READ(FDI_RX_IIR(pipe)));
2667
357555c0
JB		 2668 /* enable CPU FDI TX and PCH FDI RX */
2669 reg = FDI_TX_CTL(pipe);
2670 temp = I915_READ(reg);
2671 temp &= ~(7 << 19);
2672 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2673 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2674 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2675 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2676 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2677 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2678 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2679
d74cf324
DV		 2680 I915_WRITE(FDI_RX_MISC(pipe),
2681 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2682
357555c0
JB		 2683 reg = FDI_RX_CTL(pipe);
2684 temp = I915_READ(reg);
2685 temp &= ~FDI_LINK_TRAIN_AUTO;
2686 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2687 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2688 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2689 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2690
2691 POSTING_READ(reg);
2692 udelay(150);
2693
8f5718a6 2694 cpt_phase_pointer_enable(dev, pipe);
291427f5 2695
0206e353 2696 for (i = 0; i < 4; i++) {
357555c0
JB		 2697 reg = FDI_TX_CTL(pipe);
2698 temp = I915_READ(reg);
2699 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2700 temp |= snb_b_fdi_train_param[i];
2701 I915_WRITE(reg, temp);
2702
2703 POSTING_READ(reg);
2704 udelay(500);
2705
2706 reg = FDI_RX_IIR(pipe);
2707 temp = I915_READ(reg);
2708 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2709
2710 if (temp & FDI_RX_BIT_LOCK ||
2711 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2712 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2713 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2714 break;
2715 }
2716 }
2717 if (i == 4)
2718 DRM_ERROR("FDI train 1 fail!\n");
2719
2720 /* Train 2 */
2721 reg = FDI_TX_CTL(pipe);
2722 temp = I915_READ(reg);
2723 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2724 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2725 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2726 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2727 I915_WRITE(reg, temp);
2728
2729 reg = FDI_RX_CTL(pipe);
2730 temp = I915_READ(reg);
2731 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2732 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2733 I915_WRITE(reg, temp);
2734
2735 POSTING_READ(reg);
2736 udelay(150);
2737
0206e353 2738 for (i = 0; i < 4; i++) {
357555c0
JB		 2739 reg = FDI_TX_CTL(pipe);
2740 temp = I915_READ(reg);
2741 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2742 temp |= snb_b_fdi_train_param[i];
2743 I915_WRITE(reg, temp);
2744
2745 POSTING_READ(reg);
2746 udelay(500);
2747
2748 reg = FDI_RX_IIR(pipe);
2749 temp = I915_READ(reg);
2750 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2751
2752 if (temp & FDI_RX_SYMBOL_LOCK) {
2753 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2754 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2755 break;
2756 }
2757 }
2758 if (i == 4)
2759 DRM_ERROR("FDI train 2 fail!\n");
2760
2761 DRM_DEBUG_KMS("FDI train done.\n");
2762}
2763
88cefb6c 2764static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2765{
88cefb6c 2766 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2767 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2768 int pipe = intel_crtc->pipe;
5eddb70b 2769 u32 reg, temp;
79e53945 2770
c64e311e 2771
c98e9dcf 2772 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2773 reg = FDI_RX_CTL(pipe);
2774 temp = I915_READ(reg);
2775 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2776 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2777 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2778 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2779
2780 POSTING_READ(reg);
c98e9dcf
JB		 2781 udelay(200);
2782
2783 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2784 temp = I915_READ(reg);
2785 I915_WRITE(reg, temp | FDI_PCDCLK);
2786
2787 POSTING_READ(reg);
c98e9dcf
JB		 2788 udelay(200);
2789
20749730
PZ		 2790 /* Enable CPU FDI TX PLL, always on for Ironlake */
2791 reg = FDI_TX_CTL(pipe);
2792 temp = I915_READ(reg);
2793 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2794 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2795
20749730
PZ		 2796 POSTING_READ(reg);
2797 udelay(100);
6be4a607 2798 }
0e23b99d
JB		 2799}
2800
88cefb6c
DV		 2801static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2802{
2803 struct drm_device *dev = intel_crtc->base.dev;
2804 struct drm_i915_private *dev_priv = dev->dev_private;
2805 int pipe = intel_crtc->pipe;
2806 u32 reg, temp;
2807
2808 /* Switch from PCDclk to Rawclk */
2809 reg = FDI_RX_CTL(pipe);
2810 temp = I915_READ(reg);
2811 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2812
2813 /* Disable CPU FDI TX PLL */
2814 reg = FDI_TX_CTL(pipe);
2815 temp = I915_READ(reg);
2816 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2817
2818 POSTING_READ(reg);
2819 udelay(100);
2820
2821 reg = FDI_RX_CTL(pipe);
2822 temp = I915_READ(reg);
2823 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2824
2825 /* Wait for the clocks to turn off. */
2826 POSTING_READ(reg);
2827 udelay(100);
2828}
2829
291427f5
JB		 2830static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2831{
2832 struct drm_i915_private *dev_priv = dev->dev_private;
2833 u32 flags = I915_READ(SOUTH_CHICKEN1);
2834
2835 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2836 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2837 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2838 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2839 POSTING_READ(SOUTH_CHICKEN1);
2840}
0fc932b8
JB		 2841static void ironlake_fdi_disable(struct drm_crtc *crtc)
2842{
2843 struct drm_device *dev = crtc->dev;
2844 struct drm_i915_private *dev_priv = dev->dev_private;
2845 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2846 int pipe = intel_crtc->pipe;
2847 u32 reg, temp;
2848
2849 /* disable CPU FDI tx and PCH FDI rx */
2850 reg = FDI_TX_CTL(pipe);
2851 temp = I915_READ(reg);
2852 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2853 POSTING_READ(reg);
2854
2855 reg = FDI_RX_CTL(pipe);
2856 temp = I915_READ(reg);
2857 temp &= ~(0x7 << 16);
2858 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2859 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2860
2861 POSTING_READ(reg);
2862 udelay(100);
2863
2864 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2865 if (HAS_PCH_IBX(dev)) {
2866 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
291427f5
JB		 2867 } else if (HAS_PCH_CPT(dev)) {
2868 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2869 }
0fc932b8
JB		 2870
2871 /* still set train pattern 1 */
2872 reg = FDI_TX_CTL(pipe);
2873 temp = I915_READ(reg);
2874 temp &= ~FDI_LINK_TRAIN_NONE;
2875 temp |= FDI_LINK_TRAIN_PATTERN_1;
2876 I915_WRITE(reg, temp);
2877
2878 reg = FDI_RX_CTL(pipe);
2879 temp = I915_READ(reg);
2880 if (HAS_PCH_CPT(dev)) {
2881 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2882 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2883 } else {
2884 temp &= ~FDI_LINK_TRAIN_NONE;
2885 temp |= FDI_LINK_TRAIN_PATTERN_1;
2886 }
2887 /* BPC in FDI rx is consistent with that in PIPECONF */
2888 temp &= ~(0x07 << 16);
2889 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2890 I915_WRITE(reg, temp);
2891
2892 POSTING_READ(reg);
2893 udelay(100);
2894}
2895
5bb61643
CW		 2896static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2897{
2898 struct drm_device *dev = crtc->dev;
2899 struct drm_i915_private *dev_priv = dev->dev_private;
2900 unsigned long flags;
2901 bool pending;
2902
2903 if (atomic_read(&dev_priv->mm.wedged))
2904 return false;
2905
2906 spin_lock_irqsave(&dev->event_lock, flags);
2907 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2908 spin_unlock_irqrestore(&dev->event_lock, flags);
2909
2910 return pending;
2911}
2912
e6c3a2a6
CW		 2913static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2914{
0f91128d 2915 struct drm_device *dev = crtc->dev;
5bb61643 2916 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2917
2918 if (crtc->fb == NULL)
2919 return;
2920
5bb61643
CW		 2921 wait_event(dev_priv->pending_flip_queue,
2922 !intel_crtc_has_pending_flip(crtc));
2923
0f91128d
CW		 2924 mutex_lock(&dev->struct_mutex);
2925 intel_finish_fb(crtc->fb);
2926 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2927}
2928
fc316cbe 2929static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
040484af
JB		 2930{
2931 struct drm_device *dev = crtc->dev;
228d3e36 2932 struct intel_encoder *intel_encoder;
040484af
JB		 2933
2934 /*
2935 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2936 * must be driven by its own crtc; no sharing is possible.
2937 */
228d3e36 2938 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
228d3e36 2939 switch (intel_encoder->type) {
040484af 2940 case INTEL_OUTPUT_EDP:
228d3e36 2941 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
040484af
JB		 2942 return false;
2943 continue;
2944 }
2945 }
2946
2947 return true;
2948}
2949
fc316cbe
PZ		 2950static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2951{
2952 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2953}
2954
e615efe4
ED		 2955/* Program iCLKIP clock to the desired frequency */
2956static void lpt_program_iclkip(struct drm_crtc *crtc)
2957{
2958 struct drm_device *dev = crtc->dev;
2959 struct drm_i915_private *dev_priv = dev->dev_private;
2960 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2961 u32 temp;
2962
2963 /* It is necessary to ungate the pixclk gate prior to programming
2964 * the divisors, and gate it back when it is done.
2965 */
2966 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2967
2968 /* Disable SSCCTL */
2969 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2970 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2971 SBI_SSCCTL_DISABLE);
2972
2973 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2974 if (crtc->mode.clock == 20000) {
2975 auxdiv = 1;
2976 divsel = 0x41;
2977 phaseinc = 0x20;
2978 } else {
2979 /* The iCLK virtual clock root frequency is in MHz,
2980 * but the crtc->mode.clock in in KHz. To get the divisors,
2981 * it is necessary to divide one by another, so we
2982 * convert the virtual clock precision to KHz here for higher
2983 * precision.
2984 */
2985 u32 iclk_virtual_root_freq = 172800 * 1000;
2986 u32 iclk_pi_range = 64;
2987 u32 desired_divisor, msb_divisor_value, pi_value;
2988
2989 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2990 msb_divisor_value = desired_divisor / iclk_pi_range;
2991 pi_value = desired_divisor % iclk_pi_range;
2992
2993 auxdiv = 0;
2994 divsel = msb_divisor_value - 2;
2995 phaseinc = pi_value;
2996 }
2997
2998 /* This should not happen with any sane values */
2999 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3000 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3001 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3002 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3003
3004 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3005 crtc->mode.clock,
3006 auxdiv,
3007 divsel,
3008 phasedir,
3009 phaseinc);
3010
3011 /* Program SSCDIVINTPHASE6 */
3012 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
3013 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3014 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3015 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3016 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3017 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3018 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3019
3020 intel_sbi_write(dev_priv,
3021 SBI_SSCDIVINTPHASE6,
3022 temp);
3023
3024 /* Program SSCAUXDIV */
3025 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
3026 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3027 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3028 intel_sbi_write(dev_priv,
3029 SBI_SSCAUXDIV6,
3030 temp);
3031
3032
3033 /* Enable modulator and associated divider */
3034 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
3035 temp &= ~SBI_SSCCTL_DISABLE;
3036 intel_sbi_write(dev_priv,
3037 SBI_SSCCTL6,
3038 temp);
3039
3040 /* Wait for initialization time */
3041 udelay(24);
3042
3043 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3044}
3045
f67a559d
JB		 3046/*
3047 * Enable PCH resources required for PCH ports:
3048 * - PCH PLLs
3049 * - FDI training & RX/TX
3050 * - update transcoder timings
3051 * - DP transcoding bits
3052 * - transcoder
3053 */
3054static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3055{
3056 struct drm_device *dev = crtc->dev;
3057 struct drm_i915_private *dev_priv = dev->dev_private;
3058 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3059 int pipe = intel_crtc->pipe;
ee7b9f93 3060 u32 reg, temp;
2c07245f 3061
e7e164db
CW		 3062 assert_transcoder_disabled(dev_priv, pipe);
3063
cd986abb
DV		 3064 /* Write the TU size bits before fdi link training, so that error
3065 * detection works. */
3066 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3067 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3068
c98e9dcf 3069 /* For PCH output, training FDI link */
674cf967 3070 dev_priv->display.fdi_link_train(crtc);
2c07245f 3071
572deb37
DV		 3072 /* XXX: pch pll's can be enabled any time before we enable the PCH
3073 * transcoder, and we actually should do this to not upset any PCH
3074 * transcoder that already use the clock when we share it.
3075 *
3076 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3077 * unconditionally resets the pll - we need that to have the right LVDS
3078 * enable sequence. */
b6b4e185 3079 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 3080
303b81e0 3081 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3082 u32 sel;
4b645f14 3083
c98e9dcf 3084 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3085 switch (pipe) {
3086 default:
3087 case 0:
3088 temp |= TRANSA_DPLL_ENABLE;
3089 sel = TRANSA_DPLLB_SEL;
3090 break;
3091 case 1:
3092 temp |= TRANSB_DPLL_ENABLE;
3093 sel = TRANSB_DPLLB_SEL;
3094 break;
3095 case 2:
3096 temp |= TRANSC_DPLL_ENABLE;
3097 sel = TRANSC_DPLLB_SEL;
3098 break;
d64311ab 3099 }
ee7b9f93
JB		 3100 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3101 temp |= sel;
3102 else
3103 temp &= ~sel;
c98e9dcf 3104 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3105 }
5eddb70b 3106
d9b6cb56
JB		 3107 /* set transcoder timing, panel must allow it */
3108 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3109 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3110 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3111 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3112
5eddb70b
CW		 3113 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3114 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3115 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3116 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3117
303b81e0 3118 intel_fdi_normal_train(crtc);
5e84e1a4 3119
c98e9dcf
JB		 3120 /* For PCH DP, enable TRANS_DP_CTL */
3121 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3122 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3123 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 3124 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 3125 reg = TRANS_DP_CTL(pipe);
3126 temp = I915_READ(reg);
3127 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3128 TRANS_DP_SYNC_MASK |
3129 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3130 temp |= (TRANS_DP_OUTPUT_ENABLE |
3131 TRANS_DP_ENH_FRAMING);
9325c9f0 3132 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3133
3134 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3135 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3136 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3137 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3138
3139 switch (intel_trans_dp_port_sel(crtc)) {
3140 case PCH_DP_B:
5eddb70b 3141 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3142 break;
3143 case PCH_DP_C:
5eddb70b 3144 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3145 break;
3146 case PCH_DP_D:
5eddb70b 3147 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3148 break;
3149 default:
e95d41e1 3150 BUG();
32f9d658 3151 }
2c07245f 3152
5eddb70b 3153 I915_WRITE(reg, temp);
6be4a607 3154 }
b52eb4dc 3155
b8a4f404 3156 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3157}
3158
1507e5bd
PZ		 3159static void lpt_pch_enable(struct drm_crtc *crtc)
3160{
3161 struct drm_device *dev = crtc->dev;
3162 struct drm_i915_private *dev_priv = dev->dev_private;
3163 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
daed2dbb 3164 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
1507e5bd 3165
daed2dbb 3166 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3167
8c52b5e8 3168 lpt_program_iclkip(crtc);
1507e5bd 3169
0540e488 3170 /* Set transcoder timing. */
daed2dbb
PZ		 3171 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3172 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3173 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
1507e5bd 3174
daed2dbb
PZ		 3175 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3176 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3177 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3178 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
1507e5bd 3179
937bb610 3180 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3181}
3182
ee7b9f93
JB		 3183static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3184{
3185 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3186
3187 if (pll == NULL)
3188 return;
3189
3190 if (pll->refcount == 0) {
3191 WARN(1, "bad PCH PLL refcount\n");
3192 return;
3193 }
3194
3195 --pll->refcount;
3196 intel_crtc->pch_pll = NULL;
3197}
3198
3199static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3200{
3201 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3202 struct intel_pch_pll *pll;
3203 int i;
3204
3205 pll = intel_crtc->pch_pll;
3206 if (pll) {
3207 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3208 intel_crtc->base.base.id, pll->pll_reg);
3209 goto prepare;
3210 }
3211
98b6bd99
DV		 3212 if (HAS_PCH_IBX(dev_priv->dev)) {
3213 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3214 i = intel_crtc->pipe;
3215 pll = &dev_priv->pch_plls[i];
3216
3217 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3218 intel_crtc->base.base.id, pll->pll_reg);
3219
3220 goto found;
3221 }
3222
ee7b9f93
JB		 3223 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3224 pll = &dev_priv->pch_plls[i];
3225
3226 /* Only want to check enabled timings first */
3227 if (pll->refcount == 0)
3228 continue;
3229
3230 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3231 fp == I915_READ(pll->fp0_reg)) {
3232 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3233 intel_crtc->base.base.id,
3234 pll->pll_reg, pll->refcount, pll->active);
3235
3236 goto found;
3237 }
3238 }
3239
3240 /* Ok no matching timings, maybe there's a free one? */
3241 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3242 pll = &dev_priv->pch_plls[i];
3243 if (pll->refcount == 0) {
3244 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3245 intel_crtc->base.base.id, pll->pll_reg);
3246 goto found;
3247 }
3248 }
3249
3250 return NULL;
3251
3252found:
3253 intel_crtc->pch_pll = pll;
3254 pll->refcount++;
3255 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3256prepare: /* separate function? */
3257 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3258
e04c7350
CW		 3259 /* Wait for the clocks to stabilize before rewriting the regs */
3260 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3261 POSTING_READ(pll->pll_reg);
3262 udelay(150);
e04c7350
CW		 3263
3264 I915_WRITE(pll->fp0_reg, fp);
3265 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3266 pll->on = false;
3267 return pll;
3268}
3269
d4270e57
JB		 3270void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3271{
3272 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3273 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3274 u32 temp;
3275
3276 temp = I915_READ(dslreg);
3277 udelay(500);
3278 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57
JB		 3279 if (wait_for(I915_READ(dslreg) != temp, 5))
3280 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3281 }
3282}
3283
f67a559d
JB		 3284static void ironlake_crtc_enable(struct drm_crtc *crtc)
3285{
3286 struct drm_device *dev = crtc->dev;
3287 struct drm_i915_private *dev_priv = dev->dev_private;
3288 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3289 struct intel_encoder *encoder;
f67a559d
JB		 3290 int pipe = intel_crtc->pipe;
3291 int plane = intel_crtc->plane;
3292 u32 temp;
3293 bool is_pch_port;
3294
08a48469
DV		 3295 WARN_ON(!crtc->enabled);
3296
f67a559d
JB		 3297 if (intel_crtc->active)
3298 return;
3299
3300 intel_crtc->active = true;
3301 intel_update_watermarks(dev);
3302
3303 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3304 temp = I915_READ(PCH_LVDS);
3305 if ((temp & LVDS_PORT_EN) == 0)
3306 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3307 }
3308
fc316cbe 3309 is_pch_port = ironlake_crtc_driving_pch(crtc);
f67a559d 3310
46b6f814 3311 if (is_pch_port) {
fff367c7
DV		 3312 /* Note: FDI PLL enabling _must_ be done before we enable the
3313 * cpu pipes, hence this is separate from all the other fdi/pch
3314 * enabling. */
88cefb6c 3315 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3316 } else {
3317 assert_fdi_tx_disabled(dev_priv, pipe);
3318 assert_fdi_rx_disabled(dev_priv, pipe);
3319 }
f67a559d 3320
bf49ec8c
DV		 3321 for_each_encoder_on_crtc(dev, crtc, encoder)
3322 if (encoder->pre_enable)
3323 encoder->pre_enable(encoder);
f67a559d
JB		 3324
3325 /* Enable panel fitting for LVDS */
3326 if (dev_priv->pch_pf_size &&
547dc041
JN		 3327 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3328 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
f67a559d
JB		 3329 /* Force use of hard-coded filter coefficients
3330 * as some pre-programmed values are broken,
3331 * e.g. x201.
3332 */
13888d78
PZ		 3333 if (IS_IVYBRIDGE(dev))
3334 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3335 PF_PIPE_SEL_IVB(pipe));
3336 else
3337 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
9db4a9c7
JB		 3338 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3339 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3340 }
3341
9c54c0dd
JB		 3342 /*
3343 * On ILK+ LUT must be loaded before the pipe is running but with
3344 * clocks enabled
3345 */
3346 intel_crtc_load_lut(crtc);
3347
f67a559d
JB		 3348 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3349 intel_enable_plane(dev_priv, plane, pipe);
3350
3351 if (is_pch_port)
3352 ironlake_pch_enable(crtc);
c98e9dcf 3353
d1ebd816 3354 mutex_lock(&dev->struct_mutex);
bed4a673 3355 intel_update_fbc(dev);
d1ebd816
BW		 3356 mutex_unlock(&dev->struct_mutex);
3357
6b383a7f 3358 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3359
fa5c73b1
DV		 3360 for_each_encoder_on_crtc(dev, crtc, encoder)
3361 encoder->enable(encoder);
61b77ddd
DV		 3362
3363 if (HAS_PCH_CPT(dev))
3364 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3365
3366 /*
3367 * There seems to be a race in PCH platform hw (at least on some
3368 * outputs) where an enabled pipe still completes any pageflip right
3369 * away (as if the pipe is off) instead of waiting for vblank. As soon
3370 * as the first vblank happend, everything works as expected. Hence just
3371 * wait for one vblank before returning to avoid strange things
3372 * happening.
3373 */
3374 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3375}
3376
4f771f10
PZ		 3377static void haswell_crtc_enable(struct drm_crtc *crtc)
3378{
3379 struct drm_device *dev = crtc->dev;
3380 struct drm_i915_private *dev_priv = dev->dev_private;
3381 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3382 struct intel_encoder *encoder;
3383 int pipe = intel_crtc->pipe;
3384 int plane = intel_crtc->plane;
4f771f10
PZ		 3385 bool is_pch_port;
3386
3387 WARN_ON(!crtc->enabled);
3388
3389 if (intel_crtc->active)
3390 return;
3391
3392 intel_crtc->active = true;
3393 intel_update_watermarks(dev);
3394
fc316cbe 3395 is_pch_port = haswell_crtc_driving_pch(crtc);
4f771f10 3396
83616634 3397 if (is_pch_port)
04945641 3398 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3399
3400 for_each_encoder_on_crtc(dev, crtc, encoder)
3401 if (encoder->pre_enable)
3402 encoder->pre_enable(encoder);
3403
1f544388 3404 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3405
1f544388 3406 /* Enable panel fitting for eDP */
547dc041
JN		 3407 if (dev_priv->pch_pf_size &&
3408 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4f771f10
PZ		 3409 /* Force use of hard-coded filter coefficients
3410 * as some pre-programmed values are broken,
3411 * e.g. x201.
3412 */
54075a7d
PZ		 3413 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3414 PF_PIPE_SEL_IVB(pipe));
4f771f10
PZ		 3415 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3416 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3417 }
3418
3419 /*
3420 * On ILK+ LUT must be loaded before the pipe is running but with
3421 * clocks enabled
3422 */
3423 intel_crtc_load_lut(crtc);
3424
1f544388
PZ		 3425 intel_ddi_set_pipe_settings(crtc);
3426 intel_ddi_enable_pipe_func(crtc);
4f771f10
PZ		 3427
3428 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3429 intel_enable_plane(dev_priv, plane, pipe);
3430
3431 if (is_pch_port)
1507e5bd 3432 lpt_pch_enable(crtc);
4f771f10
PZ		 3433
3434 mutex_lock(&dev->struct_mutex);
3435 intel_update_fbc(dev);
3436 mutex_unlock(&dev->struct_mutex);
3437
3438 intel_crtc_update_cursor(crtc, true);
3439
3440 for_each_encoder_on_crtc(dev, crtc, encoder)
3441 encoder->enable(encoder);
3442
4f771f10
PZ		 3443 /*
3444 * There seems to be a race in PCH platform hw (at least on some
3445 * outputs) where an enabled pipe still completes any pageflip right
3446 * away (as if the pipe is off) instead of waiting for vblank. As soon
3447 * as the first vblank happend, everything works as expected. Hence just
3448 * wait for one vblank before returning to avoid strange things
3449 * happening.
3450 */
3451 intel_wait_for_vblank(dev, intel_crtc->pipe);
3452}
3453
6be4a607
JB		 3454static void ironlake_crtc_disable(struct drm_crtc *crtc)
3455{
3456 struct drm_device *dev = crtc->dev;
3457 struct drm_i915_private *dev_priv = dev->dev_private;
3458 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3459 struct intel_encoder *encoder;
6be4a607
JB		 3460 int pipe = intel_crtc->pipe;
3461 int plane = intel_crtc->plane;
5eddb70b 3462 u32 reg, temp;
b52eb4dc 3463
ef9c3aee 3464
f7abfe8b
CW		 3465 if (!intel_crtc->active)
3466 return;
3467
ea9d758d
DV		 3468 for_each_encoder_on_crtc(dev, crtc, encoder)
3469 encoder->disable(encoder);
3470
e6c3a2a6 3471 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3472 drm_vblank_off(dev, pipe);
6b383a7f 3473 intel_crtc_update_cursor(crtc, false);
5eddb70b 3474
b24e7179 3475 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3476
973d04f9
CW		 3477 if (dev_priv->cfb_plane == plane)
3478 intel_disable_fbc(dev);
2c07245f 3479
b24e7179 3480 intel_disable_pipe(dev_priv, pipe);
32f9d658 3481
6be4a607 3482 /* Disable PF */
9db4a9c7
JB		 3483 I915_WRITE(PF_CTL(pipe), 0);
3484 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3485
bf49ec8c
DV		 3486 for_each_encoder_on_crtc(dev, crtc, encoder)
3487 if (encoder->post_disable)
3488 encoder->post_disable(encoder);
2c07245f 3489
0fc932b8 3490 ironlake_fdi_disable(crtc);
249c0e64 3491
b8a4f404 3492 ironlake_disable_pch_transcoder(dev_priv, pipe);
913d8d11 3493
6be4a607
JB		 3494 if (HAS_PCH_CPT(dev)) {
3495 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3496 reg = TRANS_DP_CTL(pipe);
3497 temp = I915_READ(reg);
3498 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3499 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3500 I915_WRITE(reg, temp);
6be4a607
JB		 3501
3502 /* disable DPLL_SEL */
3503 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3504 switch (pipe) {
3505 case 0:
d64311ab 3506 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3507 break;
3508 case 1:
6be4a607 3509 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3510 break;
3511 case 2:
4b645f14 3512 /* C shares PLL A or B */
d64311ab 3513 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3514 break;
3515 default:
3516 BUG(); /* wtf */
3517 }
6be4a607 3518 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3519 }
e3421a18 3520
6be4a607 3521 /* disable PCH DPLL */
ee7b9f93 3522 intel_disable_pch_pll(intel_crtc);
8db9d77b 3523
88cefb6c 3524 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3525
f7abfe8b 3526 intel_crtc->active = false;
6b383a7f 3527 intel_update_watermarks(dev);
d1ebd816
BW		 3528
3529 mutex_lock(&dev->struct_mutex);
6b383a7f 3530 intel_update_fbc(dev);
d1ebd816 3531 mutex_unlock(&dev->struct_mutex);
6be4a607 3532}
1b3c7a47 3533
4f771f10 3534static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3535{
4f771f10
PZ		 3536 struct drm_device *dev = crtc->dev;
3537 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3538 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3539 struct intel_encoder *encoder;
3540 int pipe = intel_crtc->pipe;
3541 int plane = intel_crtc->plane;
ad80a810 3542 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
83616634 3543 bool is_pch_port;
ee7b9f93 3544
4f771f10
PZ		 3545 if (!intel_crtc->active)
3546 return;
3547
83616634
PZ		 3548 is_pch_port = haswell_crtc_driving_pch(crtc);
3549
4f771f10
PZ		 3550 for_each_encoder_on_crtc(dev, crtc, encoder)
3551 encoder->disable(encoder);
3552
3553 intel_crtc_wait_for_pending_flips(crtc);
3554 drm_vblank_off(dev, pipe);
3555 intel_crtc_update_cursor(crtc, false);
3556
3557 intel_disable_plane(dev_priv, plane, pipe);
3558
3559 if (dev_priv->cfb_plane == plane)
3560 intel_disable_fbc(dev);
3561
3562 intel_disable_pipe(dev_priv, pipe);
3563
ad80a810 3564 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10
PZ		 3565
3566 /* Disable PF */
3567 I915_WRITE(PF_CTL(pipe), 0);
3568 I915_WRITE(PF_WIN_SZ(pipe), 0);
3569
1f544388 3570 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3571
3572 for_each_encoder_on_crtc(dev, crtc, encoder)
3573 if (encoder->post_disable)
3574 encoder->post_disable(encoder);
3575
83616634 3576 if (is_pch_port) {
ab4d966c 3577 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 3578 intel_ddi_fdi_disable(crtc);
83616634 3579 }
4f771f10
PZ		 3580
3581 intel_crtc->active = false;
3582 intel_update_watermarks(dev);
3583
3584 mutex_lock(&dev->struct_mutex);
3585 intel_update_fbc(dev);
3586 mutex_unlock(&dev->struct_mutex);
3587}
3588
ee7b9f93
JB		 3589static void ironlake_crtc_off(struct drm_crtc *crtc)
3590{
3591 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3592 intel_put_pch_pll(intel_crtc);
3593}
3594
6441ab5f
PZ		 3595static void haswell_crtc_off(struct drm_crtc *crtc)
3596{
a5c961d1
PZ		 3597 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3598
3599 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3600 * start using it. */
3601 intel_crtc->cpu_transcoder = intel_crtc->pipe;
3602
6441ab5f
PZ		 3603 intel_ddi_put_crtc_pll(crtc);
3604}
3605
02e792fb
DV		 3606static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3607{
02e792fb 3608 if (!enable && intel_crtc->overlay) {
23f09ce3 3609 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3610 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3611
23f09ce3 3612 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3613 dev_priv->mm.interruptible = false;
3614 (void) intel_overlay_switch_off(intel_crtc->overlay);
3615 dev_priv->mm.interruptible = true;
23f09ce3 3616 mutex_unlock(&dev->struct_mutex);
02e792fb 3617 }
02e792fb 3618
5dcdbcb0
CW		 3619 /* Let userspace switch the overlay on again. In most cases userspace
3620 * has to recompute where to put it anyway.
3621 */
02e792fb
DV		 3622}
3623
0b8765c6 3624static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3625{
3626 struct drm_device *dev = crtc->dev;
79e53945
JB		 3627 struct drm_i915_private *dev_priv = dev->dev_private;
3628 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3629 struct intel_encoder *encoder;
79e53945 3630 int pipe = intel_crtc->pipe;
80824003 3631 int plane = intel_crtc->plane;
79e53945 3632
08a48469
DV		 3633 WARN_ON(!crtc->enabled);
3634
f7abfe8b
CW		 3635 if (intel_crtc->active)
3636 return;
3637
3638 intel_crtc->active = true;
6b383a7f
CW		 3639 intel_update_watermarks(dev);
3640
63d7bbe9 3641 intel_enable_pll(dev_priv, pipe);
040484af 3642 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3643 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3644
0b8765c6 3645 intel_crtc_load_lut(crtc);
bed4a673 3646 intel_update_fbc(dev);
79e53945 3647
0b8765c6
JB		 3648 /* Give the overlay scaler a chance to enable if it's on this pipe */
3649 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3650 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3651
fa5c73b1
DV		 3652 for_each_encoder_on_crtc(dev, crtc, encoder)
3653 encoder->enable(encoder);
0b8765c6 3654}
79e53945 3655
0b8765c6
JB		 3656static void i9xx_crtc_disable(struct drm_crtc *crtc)
3657{
3658 struct drm_device *dev = crtc->dev;
3659 struct drm_i915_private *dev_priv = dev->dev_private;
3660 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3661 struct intel_encoder *encoder;
0b8765c6
JB		 3662 int pipe = intel_crtc->pipe;
3663 int plane = intel_crtc->plane;
b690e96c 3664
ef9c3aee 3665
f7abfe8b
CW		 3666 if (!intel_crtc->active)
3667 return;
3668
ea9d758d
DV		 3669 for_each_encoder_on_crtc(dev, crtc, encoder)
3670 encoder->disable(encoder);
3671
0b8765c6 3672 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3673 intel_crtc_wait_for_pending_flips(crtc);
3674 drm_vblank_off(dev, pipe);
0b8765c6 3675 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3676 intel_crtc_update_cursor(crtc, false);
0b8765c6 3677
973d04f9
CW		 3678 if (dev_priv->cfb_plane == plane)
3679 intel_disable_fbc(dev);
79e53945 3680
b24e7179 3681 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3682 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3683 intel_disable_pll(dev_priv, pipe);
0b8765c6 3684
f7abfe8b 3685 intel_crtc->active = false;
6b383a7f
CW		 3686 intel_update_fbc(dev);
3687 intel_update_watermarks(dev);
0b8765c6
JB		 3688}
3689
ee7b9f93
JB		 3690static void i9xx_crtc_off(struct drm_crtc *crtc)
3691{
3692}
3693
976f8a20
DV		 3694static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3695 bool enabled)
2c07245f
ZW		 3696{
3697 struct drm_device *dev = crtc->dev;
3698 struct drm_i915_master_private *master_priv;
3699 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3700 int pipe = intel_crtc->pipe;
79e53945
JB		 3701
3702 if (!dev->primary->master)
3703 return;
3704
3705 master_priv = dev->primary->master->driver_priv;
3706 if (!master_priv->sarea_priv)
3707 return;
3708
79e53945
JB		 3709 switch (pipe) {
3710 case 0:
3711 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3712 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3713 break;
3714 case 1:
3715 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3716 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3717 break;
3718 default:
9db4a9c7 3719 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3720 break;
3721 }
79e53945
JB		 3722}
3723
976f8a20
DV		 3724/**
3725 * Sets the power management mode of the pipe and plane.
3726 */
3727void intel_crtc_update_dpms(struct drm_crtc *crtc)
3728{
3729 struct drm_device *dev = crtc->dev;
3730 struct drm_i915_private *dev_priv = dev->dev_private;
3731 struct intel_encoder *intel_encoder;
3732 bool enable = false;
3733
3734 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3735 enable |= intel_encoder->connectors_active;
3736
3737 if (enable)
3738 dev_priv->display.crtc_enable(crtc);
3739 else
3740 dev_priv->display.crtc_disable(crtc);
3741
3742 intel_crtc_update_sarea(crtc, enable);
3743}
3744
3745static void intel_crtc_noop(struct drm_crtc *crtc)
3746{
3747}
3748
cdd59983
CW		 3749static void intel_crtc_disable(struct drm_crtc *crtc)
3750{
cdd59983 3751 struct drm_device *dev = crtc->dev;
976f8a20 3752 struct drm_connector *connector;
ee7b9f93 3753 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 3754
976f8a20
DV		 3755 /* crtc should still be enabled when we disable it. */
3756 WARN_ON(!crtc->enabled);
3757
3758 dev_priv->display.crtc_disable(crtc);
3759 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3760 dev_priv->display.off(crtc);
3761
931872fc
CW		 3762 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3763 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3764
3765 if (crtc->fb) {
3766 mutex_lock(&dev->struct_mutex);
1690e1eb 3767 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3768 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3769 crtc->fb = NULL;
3770 }
3771
3772 /* Update computed state. */
3773 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3774 if (!connector->encoder || !connector->encoder->crtc)
3775 continue;
3776
3777 if (connector->encoder->crtc != crtc)
3778 continue;
3779
3780 connector->dpms = DRM_MODE_DPMS_OFF;
3781 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3782 }
3783}
3784
a261b246 3785void intel_modeset_disable(struct drm_device *dev)
79e53945 3786{
a261b246
DV		 3787 struct drm_crtc *crtc;
3788
3789 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3790 if (crtc->enabled)
3791 intel_crtc_disable(crtc);
3792 }
79e53945
JB		 3793}
3794
1f703855 3795void intel_encoder_noop(struct drm_encoder *encoder)
79e53945 3796{
7e7d76c3
JB		 3797}
3798
ea5b213a 3799void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3800{
4ef69c7a 3801 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3802
ea5b213a
CW		 3803 drm_encoder_cleanup(encoder);
3804 kfree(intel_encoder);
7e7d76c3
JB		 3805}
3806
5ab432ef
DV		 3807/* Simple dpms helper for encodres with just one connector, no cloning and only
3808 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3809 * state of the entire output pipe. */
3810void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3811{
5ab432ef
DV		 3812 if (mode == DRM_MODE_DPMS_ON) {
3813 encoder->connectors_active = true;
3814
b2cabb0e 3815 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3816 } else {
3817 encoder->connectors_active = false;
3818
b2cabb0e 3819 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3820 }
79e53945
JB		 3821}
3822
0a91ca29
DV		 3823/* Cross check the actual hw state with our own modeset state tracking (and it's
3824 * internal consistency). */
b980514c 3825static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3826{
0a91ca29
DV		 3827 if (connector->get_hw_state(connector)) {
3828 struct intel_encoder *encoder = connector->encoder;
3829 struct drm_crtc *crtc;
3830 bool encoder_enabled;
3831 enum pipe pipe;
3832
3833 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3834 connector->base.base.id,
3835 drm_get_connector_name(&connector->base));
3836
3837 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3838 "wrong connector dpms state\n");
3839 WARN(connector->base.encoder != &encoder->base,
3840 "active connector not linked to encoder\n");
3841 WARN(!encoder->connectors_active,
3842 "encoder->connectors_active not set\n");
3843
3844 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3845 WARN(!encoder_enabled, "encoder not enabled\n");
3846 if (WARN_ON(!encoder->base.crtc))
3847 return;
3848
3849 crtc = encoder->base.crtc;
3850
3851 WARN(!crtc->enabled, "crtc not enabled\n");
3852 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3853 WARN(pipe != to_intel_crtc(crtc)->pipe,
3854 "encoder active on the wrong pipe\n");
3855 }
79e53945
JB		 3856}
3857
5ab432ef
DV		 3858/* Even simpler default implementation, if there's really no special case to
3859 * consider. */
3860void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3861{
5ab432ef 3862 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3863
5ab432ef
DV		 3864 /* All the simple cases only support two dpms states. */
3865 if (mode != DRM_MODE_DPMS_ON)
3866 mode = DRM_MODE_DPMS_OFF;
d4270e57 3867
5ab432ef
DV		 3868 if (mode == connector->dpms)
3869 return;
3870
3871 connector->dpms = mode;
3872
3873 /* Only need to change hw state when actually enabled */
3874 if (encoder->base.crtc)
3875 intel_encoder_dpms(encoder, mode);
3876 else
8af6cf88 3877 WARN_ON(encoder->connectors_active != false);
0a91ca29 3878
b980514c 3879 intel_modeset_check_state(connector->dev);
79e53945
JB		 3880}
3881
f0947c37
DV		 3882/* Simple connector->get_hw_state implementation for encoders that support only
3883 * one connector and no cloning and hence the encoder state determines the state
3884 * of the connector. */
3885bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3886{
24929352 3887 enum pipe pipe = 0;
f0947c37 3888 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3889
f0947c37 3890 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3891}
3892
79e53945 3893static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
35313cde 3894 const struct drm_display_mode *mode,
79e53945
JB		 3895 struct drm_display_mode *adjusted_mode)
3896{
2c07245f 3897 struct drm_device *dev = crtc->dev;
89749350 3898
bad720ff 3899 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3900 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3901 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3902 return false;
2c07245f 3903 }
89749350 3904
f9bef081
DV		 3905 /* All interlaced capable intel hw wants timings in frames. Note though
3906 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3907 * timings, so we need to be careful not to clobber these.*/
3908 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3909 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3910
44f46b42
CW		 3911 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3912 * with a hsync front porch of 0.
3913 */
3914 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3915 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3916 return false;
3917
79e53945
JB		 3918 return true;
3919}
3920
25eb05fc
JB		 3921static int valleyview_get_display_clock_speed(struct drm_device *dev)
3922{
3923 return 400000; /* FIXME */
3924}
3925
e70236a8
JB		 3926static int i945_get_display_clock_speed(struct drm_device *dev)
3927{
3928 return 400000;
3929}
79e53945 3930
e70236a8 3931static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3932{
e70236a8
JB		 3933 return 333000;
3934}
79e53945 3935
e70236a8
JB		 3936static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3937{
3938 return 200000;
3939}
79e53945 3940
e70236a8
JB		 3941static int i915gm_get_display_clock_speed(struct drm_device *dev)
3942{
3943 u16 gcfgc = 0;
79e53945 3944
e70236a8
JB		 3945 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3946
3947 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3948 return 133000;
3949 else {
3950 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3951 case GC_DISPLAY_CLOCK_333_MHZ:
3952 return 333000;
3953 default:
3954 case GC_DISPLAY_CLOCK_190_200_MHZ:
3955 return 190000;
79e53945 3956 }
e70236a8
JB		 3957 }
3958}
3959
3960static int i865_get_display_clock_speed(struct drm_device *dev)
3961{
3962 return 266000;
3963}
3964
3965static int i855_get_display_clock_speed(struct drm_device *dev)
3966{
3967 u16 hpllcc = 0;
3968 /* Assume that the hardware is in the high speed state. This
3969 * should be the default.
3970 */
3971 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3972 case GC_CLOCK_133_200:
3973 case GC_CLOCK_100_200:
3974 return 200000;
3975 case GC_CLOCK_166_250:
3976 return 250000;
3977 case GC_CLOCK_100_133:
79e53945 3978 return 133000;
e70236a8 3979 }
79e53945 3980
e70236a8
JB		 3981 /* Shouldn't happen */
3982 return 0;
3983}
79e53945 3984
e70236a8
JB		 3985static int i830_get_display_clock_speed(struct drm_device *dev)
3986{
3987 return 133000;
79e53945
JB		 3988}
3989
2c07245f
ZW		 3990struct fdi_m_n {
3991 u32 tu;
3992 u32 gmch_m;
3993 u32 gmch_n;
3994 u32 link_m;
3995 u32 link_n;
3996};
3997
3998static void
3999fdi_reduce_ratio(u32 *num, u32 *den)
4000{
4001 while (*num > 0xffffff || *den > 0xffffff) {
4002 *num >>= 1;
4003 *den >>= 1;
4004 }
4005}
4006
2c07245f 4007static void
f2b115e6
AJ		 4008ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
4009 int link_clock, struct fdi_m_n *m_n)
2c07245f 4010{
2c07245f
ZW		 4011 m_n->tu = 64; /* default size */
4012
22ed1113
CW		 4013 /* BUG_ON(pixel_clock > INT_MAX / 36); */
4014 m_n->gmch_m = bits_per_pixel * pixel_clock;
4015 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 4016 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4017
22ed1113
CW		 4018 m_n->link_m = pixel_clock;
4019 m_n->link_n = link_clock;
2c07245f
ZW		 4020 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
4021}
4022
a7615030
CW		 4023static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4024{
72bbe58c
KP		 4025 if (i915_panel_use_ssc >= 0)
4026 return i915_panel_use_ssc != 0;
4027 return dev_priv->lvds_use_ssc
435793df 4028 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4029}
4030
5a354204
JB		 4031/**
4032 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4033 * @crtc: CRTC structure
3b5c78a3 4034 * @mode: requested mode
5a354204
JB		 4035 *
4036 * A pipe may be connected to one or more outputs. Based on the depth of the
4037 * attached framebuffer, choose a good color depth to use on the pipe.
4038 *
4039 * If possible, match the pipe depth to the fb depth. In some cases, this
4040 * isn't ideal, because the connected output supports a lesser or restricted
4041 * set of depths. Resolve that here:
4042 * LVDS typically supports only 6bpc, so clamp down in that case
4043 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4044 * Displays may support a restricted set as well, check EDID and clamp as
4045 * appropriate.
3b5c78a3 4046 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 4047 *
4048 * RETURNS:
4049 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4050 * true if they don't match).
4051 */
4052static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
94352cf9 4053 struct drm_framebuffer *fb,
3b5c78a3
AJ		 4054 unsigned int *pipe_bpp,
4055 struct drm_display_mode *mode)
5a354204
JB		 4056{
4057 struct drm_device *dev = crtc->dev;
4058 struct drm_i915_private *dev_priv = dev->dev_private;
5a354204 4059 struct drm_connector *connector;
6c2b7c12 4060 struct intel_encoder *intel_encoder;
5a354204
JB		 4061 unsigned int display_bpc = UINT_MAX, bpc;
4062
4063 /* Walk the encoders & connectors on this crtc, get min bpc */
6c2b7c12 4064 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5a354204
JB		 4065
4066 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4067 unsigned int lvds_bpc;
4068
4069 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4070 LVDS_A3_POWER_UP)
4071 lvds_bpc = 8;
4072 else
4073 lvds_bpc = 6;
4074
4075 if (lvds_bpc < display_bpc) {
82820490 4076 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 4077 display_bpc = lvds_bpc;
4078 }
4079 continue;
4080 }
4081
5a354204
JB		 4082 /* Not one of the known troublemakers, check the EDID */
4083 list_for_each_entry(connector, &dev->mode_config.connector_list,
4084 head) {
6c2b7c12 4085 if (connector->encoder != &intel_encoder->base)
5a354204
JB		 4086 continue;
4087
62ac41a6
JB		 4088 /* Don't use an invalid EDID bpc value */
4089 if (connector->display_info.bpc &&
4090 connector->display_info.bpc < display_bpc) {
82820490 4091 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 4092 display_bpc = connector->display_info.bpc;
4093 }
4094 }
4095
4096 /*
4097 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4098 * through, clamp it down. (Note: >12bpc will be caught below.)
4099 */
4100 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4101 if (display_bpc > 8 && display_bpc < 12) {
82820490 4102 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 4103 display_bpc = 12;
4104 } else {
82820490 4105 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 4106 display_bpc = 8;
4107 }
4108 }
4109 }
4110
3b5c78a3
AJ		 4111 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4112 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4113 display_bpc = 6;
4114 }
4115
5a354204
JB		 4116 /*
4117 * We could just drive the pipe at the highest bpc all the time and
4118 * enable dithering as needed, but that costs bandwidth. So choose
4119 * the minimum value that expresses the full color range of the fb but
4120 * also stays within the max display bpc discovered above.
4121 */
4122
94352cf9 4123 switch (fb->depth) {
5a354204
JB		 4124 case 8:
4125 bpc = 8; /* since we go through a colormap */
4126 break;
4127 case 15:
4128 case 16:
4129 bpc = 6; /* min is 18bpp */
4130 break;
4131 case 24:
578393cd 4132 bpc = 8;
5a354204
JB		 4133 break;
4134 case 30:
578393cd 4135 bpc = 10;
5a354204
JB		 4136 break;
4137 case 48:
578393cd 4138 bpc = 12;
5a354204
JB		 4139 break;
4140 default:
4141 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4142 bpc = min((unsigned int)8, display_bpc);
4143 break;
4144 }
4145
578393cd
KP		 4146 display_bpc = min(display_bpc, bpc);
4147
82820490
AJ		 4148 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4149 bpc, display_bpc);
5a354204 4150
578393cd 4151 *pipe_bpp = display_bpc * 3;
5a354204
JB		 4152
4153 return display_bpc != bpc;
4154}
4155
a0c4da24
JB		 4156static int vlv_get_refclk(struct drm_crtc *crtc)
4157{
4158 struct drm_device *dev = crtc->dev;
4159 struct drm_i915_private *dev_priv = dev->dev_private;
4160 int refclk = 27000; /* for DP & HDMI */
4161
4162 return 100000; /* only one validated so far */
4163
4164 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4165 refclk = 96000;
4166 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4167 if (intel_panel_use_ssc(dev_priv))
4168 refclk = 100000;
4169 else
4170 refclk = 96000;
4171 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4172 refclk = 100000;
4173 }
4174
4175 return refclk;
4176}
4177
c65d77d8
JB		 4178static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4179{
4180 struct drm_device *dev = crtc->dev;
4181 struct drm_i915_private *dev_priv = dev->dev_private;
4182 int refclk;
4183
a0c4da24
JB		 4184 if (IS_VALLEYVIEW(dev)) {
4185 refclk = vlv_get_refclk(crtc);
4186 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 4187 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4188 refclk = dev_priv->lvds_ssc_freq * 1000;
4189 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4190 refclk / 1000);
4191 } else if (!IS_GEN2(dev)) {
4192 refclk = 96000;
4193 } else {
4194 refclk = 48000;
4195 }
4196
4197 return refclk;
4198}
4199
4200static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4201 intel_clock_t *clock)
4202{
4203 /* SDVO TV has fixed PLL values depend on its clock range,
4204 this mirrors vbios setting. */
4205 if (adjusted_mode->clock >= 100000
4206 && adjusted_mode->clock < 140500) {
4207 clock->p1 = 2;
4208 clock->p2 = 10;
4209 clock->n = 3;
4210 clock->m1 = 16;
4211 clock->m2 = 8;
4212 } else if (adjusted_mode->clock >= 140500
4213 && adjusted_mode->clock <= 200000) {
4214 clock->p1 = 1;
4215 clock->p2 = 10;
4216 clock->n = 6;
4217 clock->m1 = 12;
4218 clock->m2 = 8;
4219 }
4220}
4221
a7516a05
JB		 4222static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4223 intel_clock_t *clock,
4224 intel_clock_t *reduced_clock)
4225{
4226 struct drm_device *dev = crtc->dev;
4227 struct drm_i915_private *dev_priv = dev->dev_private;
4228 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4229 int pipe = intel_crtc->pipe;
4230 u32 fp, fp2 = 0;
4231
4232 if (IS_PINEVIEW(dev)) {
4233 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4234 if (reduced_clock)
4235 fp2 = (1 << reduced_clock->n) << 16 |
4236 reduced_clock->m1 << 8 | reduced_clock->m2;
4237 } else {
4238 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4239 if (reduced_clock)
4240 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4241 reduced_clock->m2;
4242 }
4243
4244 I915_WRITE(FP0(pipe), fp);
4245
4246 intel_crtc->lowfreq_avail = false;
4247 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4248 reduced_clock && i915_powersave) {
4249 I915_WRITE(FP1(pipe), fp2);
4250 intel_crtc->lowfreq_avail = true;
4251 } else {
4252 I915_WRITE(FP1(pipe), fp);
4253 }
4254}
4255
a0c4da24
JB		 4256static void vlv_update_pll(struct drm_crtc *crtc,
4257 struct drm_display_mode *mode,
4258 struct drm_display_mode *adjusted_mode,
4259 intel_clock_t *clock, intel_clock_t *reduced_clock,
2a8f64ca 4260 int num_connectors)
a0c4da24
JB		 4261{
4262 struct drm_device *dev = crtc->dev;
4263 struct drm_i915_private *dev_priv = dev->dev_private;
4264 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4265 int pipe = intel_crtc->pipe;
4266 u32 dpll, mdiv, pdiv;
4267 u32 bestn, bestm1, bestm2, bestp1, bestp2;
2a8f64ca
VP		 4268 bool is_sdvo;
4269 u32 temp;
a0c4da24 4270
2a8f64ca
VP		 4271 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4272 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
a0c4da24 4273
2a8f64ca
VP		 4274 dpll = DPLL_VGA_MODE_DIS;
4275 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4276 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4277 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4278
4279 I915_WRITE(DPLL(pipe), dpll);
4280 POSTING_READ(DPLL(pipe));
a0c4da24
JB		 4281
4282 bestn = clock->n;
4283 bestm1 = clock->m1;
4284 bestm2 = clock->m2;
4285 bestp1 = clock->p1;
4286 bestp2 = clock->p2;
4287
2a8f64ca
VP		 4288 /*
4289 * In Valleyview PLL and program lane counter registers are exposed
4290 * through DPIO interface
4291 */
a0c4da24
JB		 4292 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4293 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4294 mdiv |= ((bestn << DPIO_N_SHIFT));
4295 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4296 mdiv |= (1 << DPIO_K_SHIFT);
4297 mdiv |= DPIO_ENABLE_CALIBRATION;
4298 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4299
4300 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4301
2a8f64ca 4302 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
a0c4da24 4303 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
2a8f64ca
VP		 4304 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4305 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
a0c4da24
JB		 4306 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4307
2a8f64ca 4308 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
a0c4da24
JB		 4309
4310 dpll |= DPLL_VCO_ENABLE;
4311 I915_WRITE(DPLL(pipe), dpll);
4312 POSTING_READ(DPLL(pipe));
4313 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4314 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4315
2a8f64ca
VP		 4316 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4317
4318 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4319 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4320
4321 I915_WRITE(DPLL(pipe), dpll);
4322
4323 /* Wait for the clocks to stabilize. */
4324 POSTING_READ(DPLL(pipe));
4325 udelay(150);
a0c4da24 4326
2a8f64ca
VP		 4327 temp = 0;
4328 if (is_sdvo) {
4329 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
a0c4da24
JB		 4330 if (temp > 1)
4331 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4332 else
4333 temp = 0;
a0c4da24 4334 }
2a8f64ca
VP		 4335 I915_WRITE(DPLL_MD(pipe), temp);
4336 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4337
2a8f64ca
VP		 4338 /* Now program lane control registers */
4339 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4340 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4341 {
4342 temp = 0x1000C4;
4343 if(pipe == 1)
4344 temp |= (1 << 21);
4345 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4346 }
4347 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4348 {
4349 temp = 0x1000C4;
4350 if(pipe == 1)
4351 temp |= (1 << 21);
4352 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4353 }
a0c4da24
JB		 4354}
4355
eb1cbe48
DV		 4356static void i9xx_update_pll(struct drm_crtc *crtc,
4357 struct drm_display_mode *mode,
4358 struct drm_display_mode *adjusted_mode,
4359 intel_clock_t *clock, intel_clock_t *reduced_clock,
4360 int num_connectors)
4361{
4362 struct drm_device *dev = crtc->dev;
4363 struct drm_i915_private *dev_priv = dev->dev_private;
4364 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dafd226c 4365 struct intel_encoder *encoder;
eb1cbe48
DV		 4366 int pipe = intel_crtc->pipe;
4367 u32 dpll;
4368 bool is_sdvo;
4369
2a8f64ca
VP		 4370 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4371
eb1cbe48
DV		 4372 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4373 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4374
4375 dpll = DPLL_VGA_MODE_DIS;
4376
4377 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4378 dpll |= DPLLB_MODE_LVDS;
4379 else
4380 dpll |= DPLLB_MODE_DAC_SERIAL;
4381 if (is_sdvo) {
4382 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4383 if (pixel_multiplier > 1) {
4384 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4385 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4386 }
4387 dpll |= DPLL_DVO_HIGH_SPEED;
4388 }
4389 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4390 dpll |= DPLL_DVO_HIGH_SPEED;
4391
4392 /* compute bitmask from p1 value */
4393 if (IS_PINEVIEW(dev))
4394 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4395 else {
4396 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4397 if (IS_G4X(dev) && reduced_clock)
4398 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4399 }
4400 switch (clock->p2) {
4401 case 5:
4402 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4403 break;
4404 case 7:
4405 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4406 break;
4407 case 10:
4408 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4409 break;
4410 case 14:
4411 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4412 break;
4413 }
4414 if (INTEL_INFO(dev)->gen >= 4)
4415 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4416
4417 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4418 dpll |= PLL_REF_INPUT_TVCLKINBC;
4419 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4420 /* XXX: just matching BIOS for now */
4421 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4422 dpll |= 3;
4423 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4424 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4425 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4426 else
4427 dpll |= PLL_REF_INPUT_DREFCLK;
4428
4429 dpll |= DPLL_VCO_ENABLE;
4430 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4431 POSTING_READ(DPLL(pipe));
4432 udelay(150);
4433
dafd226c
DV		 4434 for_each_encoder_on_crtc(dev, crtc, encoder)
4435 if (encoder->pre_pll_enable)
4436 encoder->pre_pll_enable(encoder);
4437
eb1cbe48
DV		 4438 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4439 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4440
4441 I915_WRITE(DPLL(pipe), dpll);
4442
4443 /* Wait for the clocks to stabilize. */
4444 POSTING_READ(DPLL(pipe));
4445 udelay(150);
4446
4447 if (INTEL_INFO(dev)->gen >= 4) {
4448 u32 temp = 0;
4449 if (is_sdvo) {
4450 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4451 if (temp > 1)
4452 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4453 else
4454 temp = 0;
4455 }
4456 I915_WRITE(DPLL_MD(pipe), temp);
4457 } else {
4458 /* The pixel multiplier can only be updated once the
4459 * DPLL is enabled and the clocks are stable.
4460 *
4461 * So write it again.
4462 */
4463 I915_WRITE(DPLL(pipe), dpll);
4464 }
4465}
4466
4467static void i8xx_update_pll(struct drm_crtc *crtc,
4468 struct drm_display_mode *adjusted_mode,
2a8f64ca 4469 intel_clock_t *clock, intel_clock_t *reduced_clock,
eb1cbe48
DV		 4470 int num_connectors)
4471{
4472 struct drm_device *dev = crtc->dev;
4473 struct drm_i915_private *dev_priv = dev->dev_private;
4474 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dafd226c 4475 struct intel_encoder *encoder;
eb1cbe48
DV		 4476 int pipe = intel_crtc->pipe;
4477 u32 dpll;
4478
2a8f64ca
VP		 4479 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4480
eb1cbe48
DV		 4481 dpll = DPLL_VGA_MODE_DIS;
4482
4483 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4484 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4485 } else {
4486 if (clock->p1 == 2)
4487 dpll |= PLL_P1_DIVIDE_BY_TWO;
4488 else
4489 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4490 if (clock->p2 == 4)
4491 dpll |= PLL_P2_DIVIDE_BY_4;
4492 }
4493
4494 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4495 /* XXX: just matching BIOS for now */
4496 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4497 dpll |= 3;
4498 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4499 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4500 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4501 else
4502 dpll |= PLL_REF_INPUT_DREFCLK;
4503
4504 dpll |= DPLL_VCO_ENABLE;
4505 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4506 POSTING_READ(DPLL(pipe));
4507 udelay(150);
4508
dafd226c
DV		 4509 for_each_encoder_on_crtc(dev, crtc, encoder)
4510 if (encoder->pre_pll_enable)
4511 encoder->pre_pll_enable(encoder);
4512
5b5896e4
DV		 4513 I915_WRITE(DPLL(pipe), dpll);
4514
4515 /* Wait for the clocks to stabilize. */
4516 POSTING_READ(DPLL(pipe));
4517 udelay(150);
4518
eb1cbe48
DV		 4519 /* The pixel multiplier can only be updated once the
4520 * DPLL is enabled and the clocks are stable.
4521 *
4522 * So write it again.
4523 */
4524 I915_WRITE(DPLL(pipe), dpll);
4525}
4526
b0e77b9c
PZ		 4527static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4528 struct drm_display_mode *mode,
4529 struct drm_display_mode *adjusted_mode)
4530{
4531 struct drm_device *dev = intel_crtc->base.dev;
4532 struct drm_i915_private *dev_priv = dev->dev_private;
4533 enum pipe pipe = intel_crtc->pipe;
fe2b8f9d 4534 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
b0e77b9c
PZ		 4535 uint32_t vsyncshift;
4536
4537 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4538 /* the chip adds 2 halflines automatically */
4539 adjusted_mode->crtc_vtotal -= 1;
4540 adjusted_mode->crtc_vblank_end -= 1;
4541 vsyncshift = adjusted_mode->crtc_hsync_start
4542 - adjusted_mode->crtc_htotal / 2;
4543 } else {
4544 vsyncshift = 0;
4545 }
4546
4547 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4548 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4549
fe2b8f9d 4550 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4551 (adjusted_mode->crtc_hdisplay - 1) |
4552 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4553 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4554 (adjusted_mode->crtc_hblank_start - 1) |
4555 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4556 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4557 (adjusted_mode->crtc_hsync_start - 1) |
4558 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4559
fe2b8f9d 4560 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4561 (adjusted_mode->crtc_vdisplay - 1) |
4562 ((adjusted_mode->crtc_vtotal - 1) << 16));
fe2b8f9d 4563 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c
PZ		 4564 (adjusted_mode->crtc_vblank_start - 1) |
4565 ((adjusted_mode->crtc_vblank_end - 1) << 16));
fe2b8f9d 4566 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4567 (adjusted_mode->crtc_vsync_start - 1) |
4568 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4569
b5e508d4
PZ		 4570 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4571 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4572 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4573 * bits. */
4574 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4575 (pipe == PIPE_B || pipe == PIPE_C))
4576 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4577
b0e77b9c
PZ		 4578 /* pipesrc controls the size that is scaled from, which should
4579 * always be the user's requested size.
4580 */
4581 I915_WRITE(PIPESRC(pipe),
4582 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4583}
4584
f564048e
EA		 4585static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4586 struct drm_display_mode *mode,
4587 struct drm_display_mode *adjusted_mode,
4588 int x, int y,
94352cf9 4589 struct drm_framebuffer *fb)
79e53945
JB		 4590{
4591 struct drm_device *dev = crtc->dev;
4592 struct drm_i915_private *dev_priv = dev->dev_private;
4593 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4594 int pipe = intel_crtc->pipe;
80824003 4595 int plane = intel_crtc->plane;
c751ce4f 4596 int refclk, num_connectors = 0;
652c393a 4597 intel_clock_t clock, reduced_clock;
b0e77b9c 4598 u32 dspcntr, pipeconf;
eb1cbe48
DV		 4599 bool ok, has_reduced_clock = false, is_sdvo = false;
4600 bool is_lvds = false, is_tv = false, is_dp = false;
5eddb70b 4601 struct intel_encoder *encoder;
d4906093 4602 const intel_limit_t *limit;
5c3b82e2 4603 int ret;
79e53945 4604
6c2b7c12 4605 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4606 switch (encoder->type) {
79e53945
JB		 4607 case INTEL_OUTPUT_LVDS:
4608 is_lvds = true;
4609 break;
4610 case INTEL_OUTPUT_SDVO:
7d57382e 4611 case INTEL_OUTPUT_HDMI:
79e53945 4612 is_sdvo = true;
5eddb70b 4613 if (encoder->needs_tv_clock)
e2f0ba97 4614 is_tv = true;
79e53945 4615 break;
79e53945
JB		 4616 case INTEL_OUTPUT_TVOUT:
4617 is_tv = true;
4618 break;
a4fc5ed6
KP		 4619 case INTEL_OUTPUT_DISPLAYPORT:
4620 is_dp = true;
4621 break;
79e53945 4622 }
43565a06 4623
c751ce4f 4624 num_connectors++;
79e53945
JB		 4625 }
4626
c65d77d8 4627 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4628
d4906093
ML		 4629 /*
4630 * Returns a set of divisors for the desired target clock with the given
4631 * refclk, or FALSE. The returned values represent the clock equation:
4632 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4633 */
1b894b59 4634 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4635 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4636 &clock);
79e53945
JB		 4637 if (!ok) {
4638 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4639 return -EINVAL;
79e53945
JB		 4640 }
4641
cda4b7d3 4642 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4643 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4644
ddc9003c 4645 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4646 /*
4647 * Ensure we match the reduced clock's P to the target clock.
4648 * If the clocks don't match, we can't switch the display clock
4649 * by using the FP0/FP1. In such case we will disable the LVDS
4650 * downclock feature.
4651 */
ddc9003c 4652 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4653 dev_priv->lvds_downclock,
4654 refclk,
cec2f356 4655 &clock,
5eddb70b 4656 &reduced_clock);
7026d4ac
ZW		 4657 }
4658
c65d77d8
JB		 4659 if (is_sdvo && is_tv)
4660 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 4661
eb1cbe48 4662 if (IS_GEN2(dev))
2a8f64ca
VP		 4663 i8xx_update_pll(crtc, adjusted_mode, &clock,
4664 has_reduced_clock ? &reduced_clock : NULL,
4665 num_connectors);
a0c4da24 4666 else if (IS_VALLEYVIEW(dev))
2a8f64ca
VP		 4667 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4668 has_reduced_clock ? &reduced_clock : NULL,
4669 num_connectors);
79e53945 4670 else
eb1cbe48
DV		 4671 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4672 has_reduced_clock ? &reduced_clock : NULL,
4673 num_connectors);
79e53945
JB		 4674
4675 /* setup pipeconf */
5eddb70b 4676 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4677
4678 /* Set up the display plane register */
4679 dspcntr = DISPPLANE_GAMMA_ENABLE;
4680
929c77fb
EA		 4681 if (pipe == 0)
4682 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4683 else
4684 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4685
a6c45cf0 4686 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4687 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4688 * core speed.
4689 *
4690 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4691 * pipe == 0 check?
4692 */
e70236a8
JB		 4693 if (mode->clock >
4694 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4695 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4696 else
5eddb70b 4697 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4698 }
4699
3b5c78a3
AJ		 4700 /* default to 8bpc */
4701 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4702 if (is_dp) {
0c96c65b 4703 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3b5c78a3
AJ		 4704 pipeconf |= PIPECONF_BPP_6 |
4705 PIPECONF_DITHER_EN |
4706 PIPECONF_DITHER_TYPE_SP;
4707 }
4708 }
4709
19c03924
GB		 4710 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4711 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4712 pipeconf |= PIPECONF_BPP_6 |
4713 PIPECONF_ENABLE |
4714 I965_PIPECONF_ACTIVE;
4715 }
4716 }
4717
28c97730 4718 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4719 drm_mode_debug_printmodeline(mode);
4720
a7516a05
JB		 4721 if (HAS_PIPE_CXSR(dev)) {
4722 if (intel_crtc->lowfreq_avail) {
28c97730 4723 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 4724 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 4725 } else {
28c97730 4726 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4727 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4728 }
4729 }
4730
617cf884 4731 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575 4732 if (!IS_GEN2(dev) &&
b0e77b9c 4733 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
734b4157 4734 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
b0e77b9c 4735 else
617cf884 4736 pipeconf |= PIPECONF_PROGRESSIVE;
734b4157 4737
b0e77b9c 4738 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4739
4740 /* pipesrc and dspsize control the size that is scaled from,
4741 * which should always be the user's requested size.
79e53945 4742 */
929c77fb
EA		 4743 I915_WRITE(DSPSIZE(plane),
4744 ((mode->vdisplay - 1) << 16) |
4745 (mode->hdisplay - 1));
4746 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4747
f564048e
EA		 4748 I915_WRITE(PIPECONF(pipe), pipeconf);
4749 POSTING_READ(PIPECONF(pipe));
929c77fb 4750 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4751
4752 intel_wait_for_vblank(dev, pipe);
4753
f564048e
EA		 4754 I915_WRITE(DSPCNTR(plane), dspcntr);
4755 POSTING_READ(DSPCNTR(plane));
4756
94352cf9 4757 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4758
4759 intel_update_watermarks(dev);
4760
f564048e
EA		 4761 return ret;
4762}
4763
9fb526db
KP		 4764/*
4765 * Initialize reference clocks when the driver loads
4766 */
4767void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4768{
4769 struct drm_i915_private *dev_priv = dev->dev_private;
4770 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4771 struct intel_encoder *encoder;
13d83a67
JB		 4772 u32 temp;
4773 bool has_lvds = false;
199e5d79
KP		 4774 bool has_cpu_edp = false;
4775 bool has_pch_edp = false;
4776 bool has_panel = false;
99eb6a01
KP		 4777 bool has_ck505 = false;
4778 bool can_ssc = false;
13d83a67
JB		 4779
4780 /* We need to take the global config into account */
199e5d79
KP		 4781 list_for_each_entry(encoder, &mode_config->encoder_list,
4782 base.head) {
4783 switch (encoder->type) {
4784 case INTEL_OUTPUT_LVDS:
4785 has_panel = true;
4786 has_lvds = true;
4787 break;
4788 case INTEL_OUTPUT_EDP:
4789 has_panel = true;
4790 if (intel_encoder_is_pch_edp(&encoder->base))
4791 has_pch_edp = true;
4792 else
4793 has_cpu_edp = true;
4794 break;
13d83a67
JB		 4795 }
4796 }
4797
99eb6a01
KP		 4798 if (HAS_PCH_IBX(dev)) {
4799 has_ck505 = dev_priv->display_clock_mode;
4800 can_ssc = has_ck505;
4801 } else {
4802 has_ck505 = false;
4803 can_ssc = true;
4804 }
4805
4806 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4807 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4808 has_ck505);
13d83a67
JB		 4809
4810 /* Ironlake: try to setup display ref clock before DPLL
4811 * enabling. This is only under driver's control after
4812 * PCH B stepping, previous chipset stepping should be
4813 * ignoring this setting.
4814 */
4815 temp = I915_READ(PCH_DREF_CONTROL);
4816 /* Always enable nonspread source */
4817 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4818
99eb6a01
KP		 4819 if (has_ck505)
4820 temp |= DREF_NONSPREAD_CK505_ENABLE;
4821 else
4822 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4823
199e5d79
KP		 4824 if (has_panel) {
4825 temp &= ~DREF_SSC_SOURCE_MASK;
4826 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4827
199e5d79 4828 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4829 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4830 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4831 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4832 } else
4833 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4834
4835 /* Get SSC going before enabling the outputs */
4836 I915_WRITE(PCH_DREF_CONTROL, temp);
4837 POSTING_READ(PCH_DREF_CONTROL);
4838 udelay(200);
4839
13d83a67
JB		 4840 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4841
4842 /* Enable CPU source on CPU attached eDP */
199e5d79 4843 if (has_cpu_edp) {
99eb6a01 4844 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4845 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4846 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4847 }
13d83a67
JB		 4848 else
4849 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4850 } else
4851 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4852
4853 I915_WRITE(PCH_DREF_CONTROL, temp);
4854 POSTING_READ(PCH_DREF_CONTROL);
4855 udelay(200);
4856 } else {
4857 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4858
4859 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4860
4861 /* Turn off CPU output */
4862 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4863
4864 I915_WRITE(PCH_DREF_CONTROL, temp);
4865 POSTING_READ(PCH_DREF_CONTROL);
4866 udelay(200);
4867
4868 /* Turn off the SSC source */
4869 temp &= ~DREF_SSC_SOURCE_MASK;
4870 temp |= DREF_SSC_SOURCE_DISABLE;
4871
4872 /* Turn off SSC1 */
4873 temp &= ~ DREF_SSC1_ENABLE;
4874
13d83a67
JB		 4875 I915_WRITE(PCH_DREF_CONTROL, temp);
4876 POSTING_READ(PCH_DREF_CONTROL);
4877 udelay(200);
4878 }
4879}
4880
d9d444cb
JB		 4881static int ironlake_get_refclk(struct drm_crtc *crtc)
4882{
4883 struct drm_device *dev = crtc->dev;
4884 struct drm_i915_private *dev_priv = dev->dev_private;
4885 struct intel_encoder *encoder;
d9d444cb
JB		 4886 struct intel_encoder *edp_encoder = NULL;
4887 int num_connectors = 0;
4888 bool is_lvds = false;
4889
6c2b7c12 4890 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 4891 switch (encoder->type) {
4892 case INTEL_OUTPUT_LVDS:
4893 is_lvds = true;
4894 break;
4895 case INTEL_OUTPUT_EDP:
4896 edp_encoder = encoder;
4897 break;
4898 }
4899 num_connectors++;
4900 }
4901
4902 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4903 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4904 dev_priv->lvds_ssc_freq);
4905 return dev_priv->lvds_ssc_freq * 1000;
4906 }
4907
4908 return 120000;
4909}
4910
c8203565 4911static void ironlake_set_pipeconf(struct drm_crtc *crtc,
f564048e 4912 struct drm_display_mode *adjusted_mode,
c8203565 4913 bool dither)
79e53945 4914{
c8203565 4915 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 4916 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4917 int pipe = intel_crtc->pipe;
c8203565
PZ		 4918 uint32_t val;
4919
4920 val = I915_READ(PIPECONF(pipe));
4921
4922 val &= ~PIPE_BPC_MASK;
4923 switch (intel_crtc->bpp) {
4924 case 18:
4925 val |= PIPE_6BPC;
4926 break;
4927 case 24:
4928 val |= PIPE_8BPC;
4929 break;
4930 case 30:
4931 val |= PIPE_10BPC;
4932 break;
4933 case 36:
4934 val |= PIPE_12BPC;
4935 break;
4936 default:
cc769b62
PZ		 4937 /* Case prevented by intel_choose_pipe_bpp_dither. */
4938 BUG();
c8203565
PZ		 4939 }
4940
4941 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4942 if (dither)
4943 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4944
4945 val &= ~PIPECONF_INTERLACE_MASK;
4946 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4947 val |= PIPECONF_INTERLACED_ILK;
4948 else
4949 val |= PIPECONF_PROGRESSIVE;
4950
4951 I915_WRITE(PIPECONF(pipe), val);
4952 POSTING_READ(PIPECONF(pipe));
4953}
4954
ee2b0b38
PZ		 4955static void haswell_set_pipeconf(struct drm_crtc *crtc,
4956 struct drm_display_mode *adjusted_mode,
4957 bool dither)
4958{
4959 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4960 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
702e7a56 4961 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
ee2b0b38
PZ		 4962 uint32_t val;
4963
702e7a56 4964 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 4965
4966 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4967 if (dither)
4968 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4969
4970 val &= ~PIPECONF_INTERLACE_MASK_HSW;
4971 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4972 val |= PIPECONF_INTERLACED_ILK;
4973 else
4974 val |= PIPECONF_PROGRESSIVE;
4975
702e7a56
PZ		 4976 I915_WRITE(PIPECONF(cpu_transcoder), val);
4977 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 4978}
4979
6591c6e4
PZ		 4980static bool ironlake_compute_clocks(struct drm_crtc *crtc,
4981 struct drm_display_mode *adjusted_mode,
4982 intel_clock_t *clock,
4983 bool *has_reduced_clock,
4984 intel_clock_t *reduced_clock)
4985{
4986 struct drm_device *dev = crtc->dev;
4987 struct drm_i915_private *dev_priv = dev->dev_private;
4988 struct intel_encoder *intel_encoder;
4989 int refclk;
d4906093 4990 const intel_limit_t *limit;
6591c6e4 4991 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
79e53945 4992
6591c6e4
PZ		 4993 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4994 switch (intel_encoder->type) {
79e53945
JB		 4995 case INTEL_OUTPUT_LVDS:
4996 is_lvds = true;
4997 break;
4998 case INTEL_OUTPUT_SDVO:
7d57382e 4999 case INTEL_OUTPUT_HDMI:
79e53945 5000 is_sdvo = true;
6591c6e4 5001 if (intel_encoder->needs_tv_clock)
e2f0ba97 5002 is_tv = true;
79e53945 5003 break;
79e53945
JB		 5004 case INTEL_OUTPUT_TVOUT:
5005 is_tv = true;
5006 break;
79e53945
JB		 5007 }
5008 }
5009
d9d444cb 5010 refclk = ironlake_get_refclk(crtc);
79e53945 5011
d4906093
ML		 5012 /*
5013 * Returns a set of divisors for the desired target clock with the given
5014 * refclk, or FALSE. The returned values represent the clock equation:
5015 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5016 */
1b894b59 5017 limit = intel_limit(crtc, refclk);
6591c6e4
PZ		 5018 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5019 clock);
5020 if (!ret)
5021 return false;
cda4b7d3 5022
ddc9003c 5023 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5024 /*
5025 * Ensure we match the reduced clock's P to the target clock.
5026 * If the clocks don't match, we can't switch the display clock
5027 * by using the FP0/FP1. In such case we will disable the LVDS
5028 * downclock feature.
5029 */
6591c6e4
PZ		 5030 *has_reduced_clock = limit->find_pll(limit, crtc,
5031 dev_priv->lvds_downclock,
5032 refclk,
5033 clock,
5034 reduced_clock);
652c393a 5035 }
61e9653f
DV		 5036
5037 if (is_sdvo && is_tv)
6591c6e4
PZ		 5038 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5039
5040 return true;
5041}
5042
01a415fd
DV		 5043static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5044{
5045 struct drm_i915_private *dev_priv = dev->dev_private;
5046 uint32_t temp;
5047
5048 temp = I915_READ(SOUTH_CHICKEN1);
5049 if (temp & FDI_BC_BIFURCATION_SELECT)
5050 return;
5051
5052 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5053 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5054
5055 temp |= FDI_BC_BIFURCATION_SELECT;
5056 DRM_DEBUG_KMS("enabling fdi C rx\n");
5057 I915_WRITE(SOUTH_CHICKEN1, temp);
5058 POSTING_READ(SOUTH_CHICKEN1);
5059}
5060
5061static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5062{
5063 struct drm_device *dev = intel_crtc->base.dev;
5064 struct drm_i915_private *dev_priv = dev->dev_private;
5065 struct intel_crtc *pipe_B_crtc =
5066 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5067
5068 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5069 intel_crtc->pipe, intel_crtc->fdi_lanes);
5070 if (intel_crtc->fdi_lanes > 4) {
5071 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5072 intel_crtc->pipe, intel_crtc->fdi_lanes);
5073 /* Clamp lanes to avoid programming the hw with bogus values. */
5074 intel_crtc->fdi_lanes = 4;
5075
5076 return false;
5077 }
5078
5079 if (dev_priv->num_pipe == 2)
5080 return true;
5081
5082 switch (intel_crtc->pipe) {
5083 case PIPE_A:
5084 return true;
5085 case PIPE_B:
5086 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5087 intel_crtc->fdi_lanes > 2) {
5088 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5089 intel_crtc->pipe, intel_crtc->fdi_lanes);
5090 /* Clamp lanes to avoid programming the hw with bogus values. */
5091 intel_crtc->fdi_lanes = 2;
5092
5093 return false;
5094 }
5095
5096 if (intel_crtc->fdi_lanes > 2)
5097 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5098 else
5099 cpt_enable_fdi_bc_bifurcation(dev);
5100
5101 return true;
5102 case PIPE_C:
5103 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5104 if (intel_crtc->fdi_lanes > 2) {
5105 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5106 intel_crtc->pipe, intel_crtc->fdi_lanes);
5107 /* Clamp lanes to avoid programming the hw with bogus values. */
5108 intel_crtc->fdi_lanes = 2;
5109
5110 return false;
5111 }
5112 } else {
5113 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5114 return false;
5115 }
5116
5117 cpt_enable_fdi_bc_bifurcation(dev);
5118
5119 return true;
5120 default:
5121 BUG();
5122 }
5123}
5124
f48d8f23
PZ		 5125static void ironlake_set_m_n(struct drm_crtc *crtc,
5126 struct drm_display_mode *mode,
5127 struct drm_display_mode *adjusted_mode)
79e53945
JB		 5128{
5129 struct drm_device *dev = crtc->dev;
5130 struct drm_i915_private *dev_priv = dev->dev_private;
5131 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
afe2fcf5 5132 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
f48d8f23 5133 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
2c07245f 5134 struct fdi_m_n m_n = {0};
f48d8f23
PZ		 5135 int target_clock, pixel_multiplier, lane, link_bw;
5136 bool is_dp = false, is_cpu_edp = false;
79e53945 5137
f48d8f23
PZ		 5138 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5139 switch (intel_encoder->type) {
a4fc5ed6
KP		 5140 case INTEL_OUTPUT_DISPLAYPORT:
5141 is_dp = true;
5142 break;
32f9d658 5143 case INTEL_OUTPUT_EDP:
e3aef172 5144 is_dp = true;
f48d8f23 5145 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5146 is_cpu_edp = true;
f48d8f23 5147 edp_encoder = intel_encoder;
32f9d658 5148 break;
79e53945 5149 }
79e53945 5150 }
61e9653f 5151
2c07245f 5152 /* FDI link */
8febb297
EA		 5153 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5154 lane = 0;
5155 /* CPU eDP doesn't require FDI link, so just set DP M/N
5156 according to current link config */
e3aef172 5157 if (is_cpu_edp) {
e3aef172 5158 intel_edp_link_config(edp_encoder, &lane, &link_bw);
8febb297 5159 } else {
8febb297
EA		 5160 /* FDI is a binary signal running at ~2.7GHz, encoding
5161 * each output octet as 10 bits. The actual frequency
5162 * is stored as a divider into a 100MHz clock, and the
5163 * mode pixel clock is stored in units of 1KHz.
5164 * Hence the bw of each lane in terms of the mode signal
5165 * is:
5166 */
5167 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5168 }
58a27471 5169
94bf2ced
DV		 5170 /* [e]DP over FDI requires target mode clock instead of link clock. */
5171 if (edp_encoder)
5172 target_clock = intel_edp_target_clock(edp_encoder, mode);
5173 else if (is_dp)
5174 target_clock = mode->clock;
5175 else
5176 target_clock = adjusted_mode->clock;
5177
8febb297
EA		 5178 if (!lane) {
5179 /*
5180 * Account for spread spectrum to avoid
5181 * oversubscribing the link. Max center spread
5182 * is 2.5%; use 5% for safety's sake.
5183 */
5a354204 5184 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
8febb297 5185 lane = bps / (link_bw * 8) + 1;
5eb08b69 5186 }
2c07245f 5187
8febb297
EA		 5188 intel_crtc->fdi_lanes = lane;
5189
5190 if (pixel_multiplier > 1)
5191 link_bw *= pixel_multiplier;
5a354204
JB		 5192 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5193 &m_n);
8febb297 5194
afe2fcf5
PZ		 5195 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5196 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5197 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5198 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
f48d8f23
PZ		 5199}
5200
de13a2e3
PZ		 5201static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5202 struct drm_display_mode *adjusted_mode,
5203 intel_clock_t *clock, u32 fp)
79e53945 5204{
de13a2e3 5205 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5206 struct drm_device *dev = crtc->dev;
5207 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5208 struct intel_encoder *intel_encoder;
5209 uint32_t dpll;
5210 int factor, pixel_multiplier, num_connectors = 0;
5211 bool is_lvds = false, is_sdvo = false, is_tv = false;
5212 bool is_dp = false, is_cpu_edp = false;
79e53945 5213
de13a2e3
PZ		 5214 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5215 switch (intel_encoder->type) {
79e53945
JB		 5216 case INTEL_OUTPUT_LVDS:
5217 is_lvds = true;
5218 break;
5219 case INTEL_OUTPUT_SDVO:
7d57382e 5220 case INTEL_OUTPUT_HDMI:
79e53945 5221 is_sdvo = true;
de13a2e3 5222 if (intel_encoder->needs_tv_clock)
e2f0ba97 5223 is_tv = true;
79e53945 5224 break;
79e53945
JB		 5225 case INTEL_OUTPUT_TVOUT:
5226 is_tv = true;
5227 break;
a4fc5ed6
KP		 5228 case INTEL_OUTPUT_DISPLAYPORT:
5229 is_dp = true;
5230 break;
32f9d658 5231 case INTEL_OUTPUT_EDP:
e3aef172 5232 is_dp = true;
de13a2e3 5233 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5234 is_cpu_edp = true;
32f9d658 5235 break;
79e53945 5236 }
43565a06 5237
c751ce4f 5238 num_connectors++;
79e53945 5239 }
79e53945 5240
c1858123 5241 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5242 factor = 21;
5243 if (is_lvds) {
5244 if ((intel_panel_use_ssc(dev_priv) &&
5245 dev_priv->lvds_ssc_freq == 100) ||
1974cad0 5246 intel_is_dual_link_lvds(dev))
8febb297
EA		 5247 factor = 25;
5248 } else if (is_sdvo && is_tv)
5249 factor = 20;
c1858123 5250
de13a2e3 5251 if (clock->m < factor * clock->n)
8febb297 5252 fp |= FP_CB_TUNE;
2c07245f 5253
5eddb70b 5254 dpll = 0;
2c07245f 5255
a07d6787
EA		 5256 if (is_lvds)
5257 dpll |= DPLLB_MODE_LVDS;
5258 else
5259 dpll |= DPLLB_MODE_DAC_SERIAL;
5260 if (is_sdvo) {
de13a2e3 5261 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
a07d6787
EA		 5262 if (pixel_multiplier > 1) {
5263 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5264 }
a07d6787
EA		 5265 dpll |= DPLL_DVO_HIGH_SPEED;
5266 }
e3aef172 5267 if (is_dp && !is_cpu_edp)
a07d6787 5268 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5269
a07d6787 5270 /* compute bitmask from p1 value */
de13a2e3 5271 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5272 /* also FPA1 */
de13a2e3 5273 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5274
de13a2e3 5275 switch (clock->p2) {
a07d6787
EA		 5276 case 5:
5277 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5278 break;
5279 case 7:
5280 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5281 break;
5282 case 10:
5283 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5284 break;
5285 case 14:
5286 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5287 break;
79e53945
JB		 5288 }
5289
43565a06
KH		 5290 if (is_sdvo && is_tv)
5291 dpll |= PLL_REF_INPUT_TVCLKINBC;
5292 else if (is_tv)
79e53945 5293 /* XXX: just matching BIOS for now */
43565a06 5294 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5295 dpll |= 3;
a7615030 5296 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5297 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5298 else
5299 dpll |= PLL_REF_INPUT_DREFCLK;
5300
de13a2e3
PZ		 5301 return dpll;
5302}
5303
5304static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5305 struct drm_display_mode *mode,
5306 struct drm_display_mode *adjusted_mode,
5307 int x, int y,
5308 struct drm_framebuffer *fb)
5309{
5310 struct drm_device *dev = crtc->dev;
5311 struct drm_i915_private *dev_priv = dev->dev_private;
5312 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5313 int pipe = intel_crtc->pipe;
5314 int plane = intel_crtc->plane;
5315 int num_connectors = 0;
5316 intel_clock_t clock, reduced_clock;
5317 u32 dpll, fp = 0, fp2 = 0;
e2f12b07
PZ		 5318 bool ok, has_reduced_clock = false;
5319 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
de13a2e3 5320 struct intel_encoder *encoder;
de13a2e3 5321 int ret;
01a415fd 5322 bool dither, fdi_config_ok;
de13a2e3
PZ		 5323
5324 for_each_encoder_on_crtc(dev, crtc, encoder) {
5325 switch (encoder->type) {
5326 case INTEL_OUTPUT_LVDS:
5327 is_lvds = true;
5328 break;
de13a2e3
PZ		 5329 case INTEL_OUTPUT_DISPLAYPORT:
5330 is_dp = true;
5331 break;
5332 case INTEL_OUTPUT_EDP:
5333 is_dp = true;
e2f12b07 5334 if (!intel_encoder_is_pch_edp(&encoder->base))
de13a2e3
PZ		 5335 is_cpu_edp = true;
5336 break;
5337 }
5338
5339 num_connectors++;
a07d6787 5340 }
79e53945 5341
5dc5298b
PZ		 5342 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5343 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5344
de13a2e3
PZ		 5345 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5346 &has_reduced_clock, &reduced_clock);
5347 if (!ok) {
5348 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5349 return -EINVAL;
79e53945
JB		 5350 }
5351
de13a2e3
PZ		 5352 /* Ensure that the cursor is valid for the new mode before changing... */
5353 intel_crtc_update_cursor(crtc, true);
5354
5355 /* determine panel color depth */
c8241969
JN		 5356 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5357 adjusted_mode);
de13a2e3
PZ		 5358 if (is_lvds && dev_priv->lvds_dither)
5359 dither = true;
5360
5361 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5362 if (has_reduced_clock)
5363 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5364 reduced_clock.m2;
5365
5366 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
79e53945 5367
f7cb34d4 5368 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5369 drm_mode_debug_printmodeline(mode);
5370
5dc5298b
PZ		 5371 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5372 if (!is_cpu_edp) {
ee7b9f93 5373 struct intel_pch_pll *pll;
4b645f14 5374
ee7b9f93
JB		 5375 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5376 if (pll == NULL) {
5377 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5378 pipe);
4b645f14
JB		 5379 return -EINVAL;
5380 }
ee7b9f93
JB		 5381 } else
5382 intel_put_pch_pll(intel_crtc);
79e53945 5383
e3aef172 5384 if (is_dp && !is_cpu_edp) {
a4fc5ed6 5385 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 5386 } else {
8db9d77b 5387 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 5388 I915_WRITE(TRANSDATA_M1(pipe), 0);
5389 I915_WRITE(TRANSDATA_N1(pipe), 0);
5390 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5391 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 5392 }
79e53945 5393
dafd226c
DV		 5394 for_each_encoder_on_crtc(dev, crtc, encoder)
5395 if (encoder->pre_pll_enable)
5396 encoder->pre_pll_enable(encoder);
5397
ee7b9f93
JB		 5398 if (intel_crtc->pch_pll) {
5399 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5400
32f9d658 5401 /* Wait for the clocks to stabilize. */
ee7b9f93 5402 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5403 udelay(150);
5404
8febb297
EA		 5405 /* The pixel multiplier can only be updated once the
5406 * DPLL is enabled and the clocks are stable.
5407 *
5408 * So write it again.
5409 */
ee7b9f93 5410 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5411 }
79e53945 5412
5eddb70b 5413 intel_crtc->lowfreq_avail = false;
ee7b9f93 5414 if (intel_crtc->pch_pll) {
4b645f14 5415 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5416 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5417 intel_crtc->lowfreq_avail = true;
4b645f14 5418 } else {
ee7b9f93 5419 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5420 }
5421 }
5422
b0e77b9c 5423 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b 5424
01a415fd
DV		 5425 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5426 * ironlake_check_fdi_lanes. */
f48d8f23 5427 ironlake_set_m_n(crtc, mode, adjusted_mode);
2c07245f 5428
01a415fd 5429 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
2c07245f 5430
e3aef172 5431 if (is_cpu_edp)
8febb297 5432 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f 5433
c8203565 5434 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
79e53945 5435
9d0498a2 5436 intel_wait_for_vblank(dev, pipe);
79e53945 5437
a1f9e77e
PZ		 5438 /* Set up the display plane register */
5439 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5440 POSTING_READ(DSPCNTR(plane));
79e53945 5441
94352cf9 5442 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5443
5444 intel_update_watermarks(dev);
5445
1f8eeabf
ED		 5446 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5447
01a415fd 5448 return fdi_config_ok ? ret : -EINVAL;
79e53945
JB		 5449}
5450
09b4ddf9
PZ		 5451static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5452 struct drm_display_mode *mode,
5453 struct drm_display_mode *adjusted_mode,
5454 int x, int y,
5455 struct drm_framebuffer *fb)
5456{
5457 struct drm_device *dev = crtc->dev;
5458 struct drm_i915_private *dev_priv = dev->dev_private;
5459 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5460 int pipe = intel_crtc->pipe;
5461 int plane = intel_crtc->plane;
5462 int num_connectors = 0;
5463 intel_clock_t clock, reduced_clock;
5dc5298b 5464 u32 dpll = 0, fp = 0, fp2 = 0;
09b4ddf9
PZ		 5465 bool ok, has_reduced_clock = false;
5466 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5467 struct intel_encoder *encoder;
5468 u32 temp;
5469 int ret;
5470 bool dither;
5471
5472 for_each_encoder_on_crtc(dev, crtc, encoder) {
5473 switch (encoder->type) {
5474 case INTEL_OUTPUT_LVDS:
5475 is_lvds = true;
5476 break;
5477 case INTEL_OUTPUT_DISPLAYPORT:
5478 is_dp = true;
5479 break;
5480 case INTEL_OUTPUT_EDP:
5481 is_dp = true;
5482 if (!intel_encoder_is_pch_edp(&encoder->base))
5483 is_cpu_edp = true;
5484 break;
5485 }
5486
5487 num_connectors++;
5488 }
5489
a5c961d1
PZ		 5490 if (is_cpu_edp)
5491 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5492 else
5493 intel_crtc->cpu_transcoder = pipe;
5494
5dc5298b
PZ		 5495 /* We are not sure yet this won't happen. */
5496 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5497 INTEL_PCH_TYPE(dev));
5498
5499 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5500 num_connectors, pipe_name(pipe));
5501
702e7a56 5502 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
1ce42920
PZ		 5503 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5504
5505 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5506
6441ab5f
PZ		 5507 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5508 return -EINVAL;
5509
5dc5298b
PZ		 5510 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5511 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5512 &has_reduced_clock,
5513 &reduced_clock);
5514 if (!ok) {
5515 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5516 return -EINVAL;
5517 }
09b4ddf9
PZ		 5518 }
5519
5520 /* Ensure that the cursor is valid for the new mode before changing... */
5521 intel_crtc_update_cursor(crtc, true);
5522
5523 /* determine panel color depth */
c8241969
JN		 5524 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5525 adjusted_mode);
09b4ddf9
PZ		 5526 if (is_lvds && dev_priv->lvds_dither)
5527 dither = true;
5528
09b4ddf9
PZ		 5529 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5530 drm_mode_debug_printmodeline(mode);
5531
5dc5298b
PZ		 5532 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5533 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5534 if (has_reduced_clock)
5535 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5536 reduced_clock.m2;
5537
5538 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5539 fp);
5540
5541 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5542 * own on pre-Haswell/LPT generation */
5543 if (!is_cpu_edp) {
5544 struct intel_pch_pll *pll;
5545
5546 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5547 if (pll == NULL) {
5548 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5549 pipe);
5550 return -EINVAL;
5551 }
5552 } else
5553 intel_put_pch_pll(intel_crtc);
09b4ddf9 5554
5dc5298b
PZ		 5555 /* The LVDS pin pair needs to be on before the DPLLs are
5556 * enabled. This is an exception to the general rule that
5557 * mode_set doesn't turn things on.
5558 */
5559 if (is_lvds) {
5560 temp = I915_READ(PCH_LVDS);
5561 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5562 if (HAS_PCH_CPT(dev)) {
5563 temp &= ~PORT_TRANS_SEL_MASK;
5564 temp |= PORT_TRANS_SEL_CPT(pipe);
5565 } else {
5566 if (pipe == 1)
5567 temp |= LVDS_PIPEB_SELECT;
5568 else
5569 temp &= ~LVDS_PIPEB_SELECT;
5570 }
09b4ddf9 5571
5dc5298b
PZ		 5572 /* set the corresponsding LVDS_BORDER bit */
5573 temp |= dev_priv->lvds_border_bits;
5574 /* Set the B0-B3 data pairs corresponding to whether
5575 * we're going to set the DPLLs for dual-channel mode or
5576 * not.
5577 */
5578 if (clock.p2 == 7)
5579 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
09b4ddf9 5580 else
5dc5298b
PZ		 5581 temp &= ~(LVDS_B0B3_POWER_UP |
5582 LVDS_CLKB_POWER_UP);
5583
5584 /* It would be nice to set 24 vs 18-bit mode
5585 * (LVDS_A3_POWER_UP) appropriately here, but we need to
5586 * look more thoroughly into how panels behave in the
5587 * two modes.
5588 */
5589 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5590 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5591 temp |= LVDS_HSYNC_POLARITY;
5592 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5593 temp |= LVDS_VSYNC_POLARITY;
5594 I915_WRITE(PCH_LVDS, temp);
09b4ddf9 5595 }
09b4ddf9
PZ		 5596 }
5597
5598 if (is_dp && !is_cpu_edp) {
5599 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5600 } else {
5dc5298b
PZ		 5601 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5602 /* For non-DP output, clear any trans DP clock recovery
5603 * setting.*/
5604 I915_WRITE(TRANSDATA_M1(pipe), 0);
5605 I915_WRITE(TRANSDATA_N1(pipe), 0);
5606 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5607 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5608 }
09b4ddf9
PZ		 5609 }
5610
5611 intel_crtc->lowfreq_avail = false;
5dc5298b
PZ		 5612 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5613 if (intel_crtc->pch_pll) {
5614 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5615
5616 /* Wait for the clocks to stabilize. */
5617 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5618 udelay(150);
5619
5620 /* The pixel multiplier can only be updated once the
5621 * DPLL is enabled and the clocks are stable.
5622 *
5623 * So write it again.
5624 */
5625 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5626 }
5627
5628 if (intel_crtc->pch_pll) {
5629 if (is_lvds && has_reduced_clock && i915_powersave) {
5630 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5631 intel_crtc->lowfreq_avail = true;
5632 } else {
5633 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5634 }
09b4ddf9
PZ		 5635 }
5636 }
5637
5638 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5639
1eb8dfec
PZ		 5640 if (!is_dp || is_cpu_edp)
5641 ironlake_set_m_n(crtc, mode, adjusted_mode);
09b4ddf9 5642
5dc5298b
PZ		 5643 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5644 if (is_cpu_edp)
5645 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
09b4ddf9 5646
ee2b0b38 5647 haswell_set_pipeconf(crtc, adjusted_mode, dither);
09b4ddf9 5648
09b4ddf9
PZ		 5649 /* Set up the display plane register */
5650 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5651 POSTING_READ(DSPCNTR(plane));
5652
5653 ret = intel_pipe_set_base(crtc, x, y, fb);
5654
5655 intel_update_watermarks(dev);
5656
5657 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5658
1f803ee5 5659 return ret;
79e53945
JB		 5660}
5661
f564048e
EA		 5662static int intel_crtc_mode_set(struct drm_crtc *crtc,
5663 struct drm_display_mode *mode,
5664 struct drm_display_mode *adjusted_mode,
5665 int x, int y,
94352cf9 5666 struct drm_framebuffer *fb)
f564048e
EA		 5667{
5668 struct drm_device *dev = crtc->dev;
5669 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 5670 struct drm_encoder_helper_funcs *encoder_funcs;
5671 struct intel_encoder *encoder;
0b701d27
EA		 5672 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5673 int pipe = intel_crtc->pipe;
f564048e
EA		 5674 int ret;
5675
0b701d27 5676 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5677
f564048e 5678 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
94352cf9 5679 x, y, fb);
79e53945 5680 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5681
9256aa19
DV		 5682 if (ret != 0)
5683 return ret;
5684
5685 for_each_encoder_on_crtc(dev, crtc, encoder) {
5686 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5687 encoder->base.base.id,
5688 drm_get_encoder_name(&encoder->base),
5689 mode->base.id, mode->name);
5690 encoder_funcs = encoder->base.helper_private;
5691 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5692 }
5693
5694 return 0;
79e53945
JB		 5695}
5696
3a9627f4
WF		 5697static bool intel_eld_uptodate(struct drm_connector *connector,
5698 int reg_eldv, uint32_t bits_eldv,
5699 int reg_elda, uint32_t bits_elda,
5700 int reg_edid)
5701{
5702 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5703 uint8_t *eld = connector->eld;
5704 uint32_t i;
5705
5706 i = I915_READ(reg_eldv);
5707 i &= bits_eldv;
5708
5709 if (!eld[0])
5710 return !i;
5711
5712 if (!i)
5713 return false;
5714
5715 i = I915_READ(reg_elda);
5716 i &= ~bits_elda;
5717 I915_WRITE(reg_elda, i);
5718
5719 for (i = 0; i < eld[2]; i++)
5720 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5721 return false;
5722
5723 return true;
5724}
5725
e0dac65e
WF		 5726static void g4x_write_eld(struct drm_connector *connector,
5727 struct drm_crtc *crtc)
5728{
5729 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5730 uint8_t *eld = connector->eld;
5731 uint32_t eldv;
5732 uint32_t len;
5733 uint32_t i;
5734
5735 i = I915_READ(G4X_AUD_VID_DID);
5736
5737 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5738 eldv = G4X_ELDV_DEVCL_DEVBLC;
5739 else
5740 eldv = G4X_ELDV_DEVCTG;
5741
3a9627f4
WF		 5742 if (intel_eld_uptodate(connector,
5743 G4X_AUD_CNTL_ST, eldv,
5744 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5745 G4X_HDMIW_HDMIEDID))
5746 return;
5747
e0dac65e
WF		 5748 i = I915_READ(G4X_AUD_CNTL_ST);
5749 i &= ~(eldv | G4X_ELD_ADDR);
5750 len = (i >> 9) & 0x1f; /* ELD buffer size */
5751 I915_WRITE(G4X_AUD_CNTL_ST, i);
5752
5753 if (!eld[0])
5754 return;
5755
5756 len = min_t(uint8_t, eld[2], len);
5757 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5758 for (i = 0; i < len; i++)
5759 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5760
5761 i = I915_READ(G4X_AUD_CNTL_ST);
5762 i |= eldv;
5763 I915_WRITE(G4X_AUD_CNTL_ST, i);
5764}
5765
83358c85
WX		 5766static void haswell_write_eld(struct drm_connector *connector,
5767 struct drm_crtc *crtc)
5768{
5769 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5770 uint8_t *eld = connector->eld;
5771 struct drm_device *dev = crtc->dev;
5772 uint32_t eldv;
5773 uint32_t i;
5774 int len;
5775 int pipe = to_intel_crtc(crtc)->pipe;
5776 int tmp;
5777
5778 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5779 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5780 int aud_config = HSW_AUD_CFG(pipe);
5781 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5782
5783
5784 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5785
5786 /* Audio output enable */
5787 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5788 tmp = I915_READ(aud_cntrl_st2);
5789 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5790 I915_WRITE(aud_cntrl_st2, tmp);
5791
5792 /* Wait for 1 vertical blank */
5793 intel_wait_for_vblank(dev, pipe);
5794
5795 /* Set ELD valid state */
5796 tmp = I915_READ(aud_cntrl_st2);
5797 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5798 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5799 I915_WRITE(aud_cntrl_st2, tmp);
5800 tmp = I915_READ(aud_cntrl_st2);
5801 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5802
5803 /* Enable HDMI mode */
5804 tmp = I915_READ(aud_config);
5805 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5806 /* clear N_programing_enable and N_value_index */
5807 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5808 I915_WRITE(aud_config, tmp);
5809
5810 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5811
5812 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5813
5814 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5815 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5816 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5817 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5818 } else
5819 I915_WRITE(aud_config, 0);
5820
5821 if (intel_eld_uptodate(connector,
5822 aud_cntrl_st2, eldv,
5823 aud_cntl_st, IBX_ELD_ADDRESS,
5824 hdmiw_hdmiedid))
5825 return;
5826
5827 i = I915_READ(aud_cntrl_st2);
5828 i &= ~eldv;
5829 I915_WRITE(aud_cntrl_st2, i);
5830
5831 if (!eld[0])
5832 return;
5833
5834 i = I915_READ(aud_cntl_st);
5835 i &= ~IBX_ELD_ADDRESS;
5836 I915_WRITE(aud_cntl_st, i);
5837 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5838 DRM_DEBUG_DRIVER("port num:%d\n", i);
5839
5840 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5841 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5842 for (i = 0; i < len; i++)
5843 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5844
5845 i = I915_READ(aud_cntrl_st2);
5846 i |= eldv;
5847 I915_WRITE(aud_cntrl_st2, i);
5848
5849}
5850
e0dac65e
WF		 5851static void ironlake_write_eld(struct drm_connector *connector,
5852 struct drm_crtc *crtc)
5853{
5854 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5855 uint8_t *eld = connector->eld;
5856 uint32_t eldv;
5857 uint32_t i;
5858 int len;
5859 int hdmiw_hdmiedid;
b6daa025 5860 int aud_config;
e0dac65e
WF		 5861 int aud_cntl_st;
5862 int aud_cntrl_st2;
9b138a83 5863 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 5864
b3f33cbf 5865 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 5866 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5867 aud_config = IBX_AUD_CFG(pipe);
5868 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 5869 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 5870 } else {
9b138a83
WX		 5871 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5872 aud_config = CPT_AUD_CFG(pipe);
5873 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 5874 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 5875 }
5876
9b138a83 5877 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 5878
5879 i = I915_READ(aud_cntl_st);
9b138a83 5880 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 5881 if (!i) {
5882 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5883 /* operate blindly on all ports */
1202b4c6
WF		 5884 eldv = IBX_ELD_VALIDB;
5885 eldv |= IBX_ELD_VALIDB << 4;
5886 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 5887 } else {
5888 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 5889 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 5890 }
5891
3a9627f4
WF		 5892 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5893 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5894 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 5895 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5896 } else
5897 I915_WRITE(aud_config, 0);
e0dac65e 5898
3a9627f4
WF		 5899 if (intel_eld_uptodate(connector,
5900 aud_cntrl_st2, eldv,
5901 aud_cntl_st, IBX_ELD_ADDRESS,
5902 hdmiw_hdmiedid))
5903 return;
5904
e0dac65e
WF		 5905 i = I915_READ(aud_cntrl_st2);
5906 i &= ~eldv;
5907 I915_WRITE(aud_cntrl_st2, i);
5908
5909 if (!eld[0])
5910 return;
5911
e0dac65e 5912 i = I915_READ(aud_cntl_st);
1202b4c6 5913 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 5914 I915_WRITE(aud_cntl_st, i);
5915
5916 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5917 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5918 for (i = 0; i < len; i++)
5919 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5920
5921 i = I915_READ(aud_cntrl_st2);
5922 i |= eldv;
5923 I915_WRITE(aud_cntrl_st2, i);
5924}
5925
5926void intel_write_eld(struct drm_encoder *encoder,
5927 struct drm_display_mode *mode)
5928{
5929 struct drm_crtc *crtc = encoder->crtc;
5930 struct drm_connector *connector;
5931 struct drm_device *dev = encoder->dev;
5932 struct drm_i915_private *dev_priv = dev->dev_private;
5933
5934 connector = drm_select_eld(encoder, mode);
5935 if (!connector)
5936 return;
5937
5938 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5939 connector->base.id,
5940 drm_get_connector_name(connector),
5941 connector->encoder->base.id,
5942 drm_get_encoder_name(connector->encoder));
5943
5944 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5945
5946 if (dev_priv->display.write_eld)
5947 dev_priv->display.write_eld(connector, crtc);
5948}
5949
79e53945
JB		 5950/** Loads the palette/gamma unit for the CRTC with the prepared values */
5951void intel_crtc_load_lut(struct drm_crtc *crtc)
5952{
5953 struct drm_device *dev = crtc->dev;
5954 struct drm_i915_private *dev_priv = dev->dev_private;
5955 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 5956 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 5957 int i;
5958
5959 /* The clocks have to be on to load the palette. */
aed3f09d 5960 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 5961 return;
5962
f2b115e6 5963 /* use legacy palette for Ironlake */
bad720ff 5964 if (HAS_PCH_SPLIT(dev))
9db4a9c7 5965 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 5966
79e53945
JB		 5967 for (i = 0; i < 256; i++) {
5968 I915_WRITE(palreg + 4 * i,
5969 (intel_crtc->lut_r[i] << 16) |
5970 (intel_crtc->lut_g[i] << 8) |
5971 intel_crtc->lut_b[i]);
5972 }
5973}
5974
560b85bb
CW		 5975static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5976{
5977 struct drm_device *dev = crtc->dev;
5978 struct drm_i915_private *dev_priv = dev->dev_private;
5979 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5980 bool visible = base != 0;
5981 u32 cntl;
5982
5983 if (intel_crtc->cursor_visible == visible)
5984 return;
5985
9db4a9c7 5986 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 5987 if (visible) {
5988 /* On these chipsets we can only modify the base whilst
5989 * the cursor is disabled.
5990 */
9db4a9c7 5991 I915_WRITE(_CURABASE, base);
560b85bb
CW		 5992
5993 cntl &= ~(CURSOR_FORMAT_MASK);
5994 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5995 cntl |= CURSOR_ENABLE |
5996 CURSOR_GAMMA_ENABLE |
5997 CURSOR_FORMAT_ARGB;
5998 } else
5999 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6000 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6001
6002 intel_crtc->cursor_visible = visible;
6003}
6004
6005static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6006{
6007 struct drm_device *dev = crtc->dev;
6008 struct drm_i915_private *dev_priv = dev->dev_private;
6009 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6010 int pipe = intel_crtc->pipe;
6011 bool visible = base != 0;
6012
6013 if (intel_crtc->cursor_visible != visible) {
548f245b 6014 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6015 if (base) {
6016 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6017 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6018 cntl |= pipe << 28; /* Connect to correct pipe */
6019 } else {
6020 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6021 cntl |= CURSOR_MODE_DISABLE;
6022 }
9db4a9c7 6023 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6024
6025 intel_crtc->cursor_visible = visible;
6026 }
6027 /* and commit changes on next vblank */
9db4a9c7 6028 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6029}
6030
65a21cd6
JB		 6031static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6032{
6033 struct drm_device *dev = crtc->dev;
6034 struct drm_i915_private *dev_priv = dev->dev_private;
6035 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6036 int pipe = intel_crtc->pipe;
6037 bool visible = base != 0;
6038
6039 if (intel_crtc->cursor_visible != visible) {
6040 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6041 if (base) {
6042 cntl &= ~CURSOR_MODE;
6043 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6044 } else {
6045 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6046 cntl |= CURSOR_MODE_DISABLE;
6047 }
6048 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6049
6050 intel_crtc->cursor_visible = visible;
6051 }
6052 /* and commit changes on next vblank */
6053 I915_WRITE(CURBASE_IVB(pipe), base);
6054}
6055
cda4b7d3 6056/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6057static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6058 bool on)
cda4b7d3
CW		 6059{
6060 struct drm_device *dev = crtc->dev;
6061 struct drm_i915_private *dev_priv = dev->dev_private;
6062 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6063 int pipe = intel_crtc->pipe;
6064 int x = intel_crtc->cursor_x;
6065 int y = intel_crtc->cursor_y;
560b85bb 6066 u32 base, pos;
cda4b7d3
CW		 6067 bool visible;
6068
6069 pos = 0;
6070
6b383a7f 6071 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6072 base = intel_crtc->cursor_addr;
6073 if (x > (int) crtc->fb->width)
6074 base = 0;
6075
6076 if (y > (int) crtc->fb->height)
6077 base = 0;
6078 } else
6079 base = 0;
6080
6081 if (x < 0) {
6082 if (x + intel_crtc->cursor_width < 0)
6083 base = 0;
6084
6085 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6086 x = -x;
6087 }
6088 pos |= x << CURSOR_X_SHIFT;
6089
6090 if (y < 0) {
6091 if (y + intel_crtc->cursor_height < 0)
6092 base = 0;
6093
6094 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6095 y = -y;
6096 }
6097 pos |= y << CURSOR_Y_SHIFT;
6098
6099 visible = base != 0;
560b85bb 6100 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6101 return;
6102
0cd83aa9 6103 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6104 I915_WRITE(CURPOS_IVB(pipe), pos);
6105 ivb_update_cursor(crtc, base);
6106 } else {
6107 I915_WRITE(CURPOS(pipe), pos);
6108 if (IS_845G(dev) || IS_I865G(dev))
6109 i845_update_cursor(crtc, base);
6110 else
6111 i9xx_update_cursor(crtc, base);
6112 }
cda4b7d3
CW		 6113}
6114
79e53945 6115static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6116 struct drm_file *file,
79e53945
JB		 6117 uint32_t handle,
6118 uint32_t width, uint32_t height)
6119{
6120 struct drm_device *dev = crtc->dev;
6121 struct drm_i915_private *dev_priv = dev->dev_private;
6122 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6123 struct drm_i915_gem_object *obj;
cda4b7d3 6124 uint32_t addr;
3f8bc370 6125 int ret;
79e53945 6126
79e53945
JB		 6127 /* if we want to turn off the cursor ignore width and height */
6128 if (!handle) {
28c97730 6129 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6130 addr = 0;
05394f39 6131 obj = NULL;
5004417d 6132 mutex_lock(&dev->struct_mutex);
3f8bc370 6133 goto finish;
79e53945
JB		 6134 }
6135
6136 /* Currently we only support 64x64 cursors */
6137 if (width != 64 || height != 64) {
6138 DRM_ERROR("we currently only support 64x64 cursors\n");
6139 return -EINVAL;
6140 }
6141
05394f39 6142 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6143 if (&obj->base == NULL)
79e53945
JB		 6144 return -ENOENT;
6145
05394f39 6146 if (obj->base.size < width * height * 4) {
79e53945 6147 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6148 ret = -ENOMEM;
6149 goto fail;
79e53945
JB		 6150 }
6151
71acb5eb 6152 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6153 mutex_lock(&dev->struct_mutex);
b295d1b6 6154 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 6155 if (obj->tiling_mode) {
6156 DRM_ERROR("cursor cannot be tiled\n");
6157 ret = -EINVAL;
6158 goto fail_locked;
6159 }
6160
2da3b9b9 6161 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 6162 if (ret) {
6163 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6164 goto fail_locked;
e7b526bb
CW		 6165 }
6166
d9e86c0e
CW		 6167 ret = i915_gem_object_put_fence(obj);
6168 if (ret) {
2da3b9b9 6169 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6170 goto fail_unpin;
6171 }
6172
05394f39 6173 addr = obj->gtt_offset;
71acb5eb 6174 } else {
6eeefaf3 6175 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6176 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6177 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6178 align);
71acb5eb
DA		 6179 if (ret) {
6180 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6181 goto fail_locked;
71acb5eb 6182 }
05394f39 6183 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6184 }
6185
a6c45cf0 6186 if (IS_GEN2(dev))
14b60391
JB		 6187 I915_WRITE(CURSIZE, (height << 12) | width);
6188
3f8bc370 6189 finish:
3f8bc370 6190 if (intel_crtc->cursor_bo) {
b295d1b6 6191 if (dev_priv->info->cursor_needs_physical) {
05394f39 6192 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6193 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6194 } else
6195 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6196 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6197 }
80824003 6198
7f9872e0 6199 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6200
6201 intel_crtc->cursor_addr = addr;
05394f39 6202 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6203 intel_crtc->cursor_width = width;
6204 intel_crtc->cursor_height = height;
6205
6b383a7f 6206 intel_crtc_update_cursor(crtc, true);
3f8bc370 6207
79e53945 6208 return 0;
e7b526bb 6209fail_unpin:
05394f39 6210 i915_gem_object_unpin(obj);
7f9872e0 6211fail_locked:
34b8686e 6212 mutex_unlock(&dev->struct_mutex);
bc9025bd 6213fail:
05394f39 6214 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6215 return ret;
79e53945
JB		 6216}
6217
6218static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6219{
79e53945 6220 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6221
cda4b7d3
CW		 6222 intel_crtc->cursor_x = x;
6223 intel_crtc->cursor_y = y;
652c393a 6224
6b383a7f 6225 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6226
6227 return 0;
6228}
6229
6230/** Sets the color ramps on behalf of RandR */
6231void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6232 u16 blue, int regno)
6233{
6234 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6235
6236 intel_crtc->lut_r[regno] = red >> 8;
6237 intel_crtc->lut_g[regno] = green >> 8;
6238 intel_crtc->lut_b[regno] = blue >> 8;
6239}
6240
b8c00ac5
DA		 6241void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6242 u16 *blue, int regno)
6243{
6244 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6245
6246 *red = intel_crtc->lut_r[regno] << 8;
6247 *green = intel_crtc->lut_g[regno] << 8;
6248 *blue = intel_crtc->lut_b[regno] << 8;
6249}
6250
79e53945 6251static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6252 u16 *blue, uint32_t start, uint32_t size)
79e53945 6253{
7203425a 6254 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6255 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6256
7203425a 6257 for (i = start; i < end; i++) {
79e53945
JB		 6258 intel_crtc->lut_r[i] = red[i] >> 8;
6259 intel_crtc->lut_g[i] = green[i] >> 8;
6260 intel_crtc->lut_b[i] = blue[i] >> 8;
6261 }
6262
6263 intel_crtc_load_lut(crtc);
6264}
6265
6266/**
6267 * Get a pipe with a simple mode set on it for doing load-based monitor
6268 * detection.
6269 *
6270 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 6271 * its requirements. The pipe will be connected to no other encoders.
79e53945 6272 *
c751ce4f 6273 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 6274 * configured for it. In the future, it could choose to temporarily disable
6275 * some outputs to free up a pipe for its use.
6276 *
6277 * \return crtc, or NULL if no pipes are available.
6278 */
6279
6280/* VESA 640x480x72Hz mode to set on the pipe */
6281static struct drm_display_mode load_detect_mode = {
6282 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6283 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6284};
6285
d2dff872
CW		 6286static struct drm_framebuffer *
6287intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6288 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6289 struct drm_i915_gem_object *obj)
6290{
6291 struct intel_framebuffer *intel_fb;
6292 int ret;
6293
6294 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6295 if (!intel_fb) {
6296 drm_gem_object_unreference_unlocked(&obj->base);
6297 return ERR_PTR(-ENOMEM);
6298 }
6299
6300 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6301 if (ret) {
6302 drm_gem_object_unreference_unlocked(&obj->base);
6303 kfree(intel_fb);
6304 return ERR_PTR(ret);
6305 }
6306
6307 return &intel_fb->base;
6308}
6309
6310static u32
6311intel_framebuffer_pitch_for_width(int width, int bpp)
6312{
6313 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6314 return ALIGN(pitch, 64);
6315}
6316
6317static u32
6318intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6319{
6320 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6321 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6322}
6323
6324static struct drm_framebuffer *
6325intel_framebuffer_create_for_mode(struct drm_device *dev,
6326 struct drm_display_mode *mode,
6327 int depth, int bpp)
6328{
6329 struct drm_i915_gem_object *obj;
0fed39bd 6330 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6331
6332 obj = i915_gem_alloc_object(dev,
6333 intel_framebuffer_size_for_mode(mode, bpp));
6334 if (obj == NULL)
6335 return ERR_PTR(-ENOMEM);
6336
6337 mode_cmd.width = mode->hdisplay;
6338 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6339 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6340 bpp);
5ca0c34a 6341 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6342
6343 return intel_framebuffer_create(dev, &mode_cmd, obj);
6344}
6345
6346static struct drm_framebuffer *
6347mode_fits_in_fbdev(struct drm_device *dev,
6348 struct drm_display_mode *mode)
6349{
6350 struct drm_i915_private *dev_priv = dev->dev_private;
6351 struct drm_i915_gem_object *obj;
6352 struct drm_framebuffer *fb;
6353
6354 if (dev_priv->fbdev == NULL)
6355 return NULL;
6356
6357 obj = dev_priv->fbdev->ifb.obj;
6358 if (obj == NULL)
6359 return NULL;
6360
6361 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6362 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6363 fb->bits_per_pixel))
d2dff872
CW		 6364 return NULL;
6365
01f2c773 6366 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6367 return NULL;
6368
6369 return fb;
6370}
6371
d2434ab7 6372bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6373 struct drm_display_mode *mode,
8261b191 6374 struct intel_load_detect_pipe *old)
79e53945
JB		 6375{
6376 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6377 struct intel_encoder *intel_encoder =
6378 intel_attached_encoder(connector);
79e53945 6379 struct drm_crtc *possible_crtc;
4ef69c7a 6380 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6381 struct drm_crtc *crtc = NULL;
6382 struct drm_device *dev = encoder->dev;
94352cf9 6383 struct drm_framebuffer *fb;
79e53945
JB		 6384 int i = -1;
6385
d2dff872
CW		 6386 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6387 connector->base.id, drm_get_connector_name(connector),
6388 encoder->base.id, drm_get_encoder_name(encoder));
6389
79e53945
JB		 6390 /*
6391 * Algorithm gets a little messy:
7a5e4805 6392 *
79e53945
JB		 6393 * - if the connector already has an assigned crtc, use it (but make
6394 * sure it's on first)
7a5e4805 6395 *
79e53945
JB		 6396 * - try to find the first unused crtc that can drive this connector,
6397 * and use that if we find one
79e53945
JB		 6398 */
6399
6400 /* See if we already have a CRTC for this connector */
6401 if (encoder->crtc) {
6402 crtc = encoder->crtc;
8261b191 6403
24218aac 6404 old->dpms_mode = connector->dpms;
8261b191
CW		 6405 old->load_detect_temp = false;
6406
6407 /* Make sure the crtc and connector are running */
24218aac
DV		 6408 if (connector->dpms != DRM_MODE_DPMS_ON)
6409 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6410
7173188d 6411 return true;
79e53945
JB		 6412 }
6413
6414 /* Find an unused one (if possible) */
6415 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6416 i++;
6417 if (!(encoder->possible_crtcs & (1 << i)))
6418 continue;
6419 if (!possible_crtc->enabled) {
6420 crtc = possible_crtc;
6421 break;
6422 }
79e53945
JB		 6423 }
6424
6425 /*
6426 * If we didn't find an unused CRTC, don't use any.
6427 */
6428 if (!crtc) {
7173188d
CW		 6429 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6430 return false;
79e53945
JB		 6431 }
6432
fc303101
DV		 6433 intel_encoder->new_crtc = to_intel_crtc(crtc);
6434 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6435
6436 intel_crtc = to_intel_crtc(crtc);
24218aac 6437 old->dpms_mode = connector->dpms;
8261b191 6438 old->load_detect_temp = true;
d2dff872 6439 old->release_fb = NULL;
79e53945 6440
6492711d
CW		 6441 if (!mode)
6442 mode = &load_detect_mode;
79e53945 6443
d2dff872
CW		 6444 /* We need a framebuffer large enough to accommodate all accesses
6445 * that the plane may generate whilst we perform load detection.
6446 * We can not rely on the fbcon either being present (we get called
6447 * during its initialisation to detect all boot displays, or it may
6448 * not even exist) or that it is large enough to satisfy the
6449 * requested mode.
6450 */
94352cf9
DV		 6451 fb = mode_fits_in_fbdev(dev, mode);
6452 if (fb == NULL) {
d2dff872 6453 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6454 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6455 old->release_fb = fb;
d2dff872
CW		 6456 } else
6457 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6458 if (IS_ERR(fb)) {
d2dff872 6459 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
0e8b3d3e 6460 return false;
79e53945 6461 }
79e53945 6462
94352cf9 6463 if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6464 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6465 if (old->release_fb)
6466 old->release_fb->funcs->destroy(old->release_fb);
0e8b3d3e 6467 return false;
79e53945 6468 }
7173188d 6469
79e53945 6470 /* let the connector get through one full cycle before testing */
9d0498a2 6471 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6472 return true;
79e53945
JB		 6473}
6474
d2434ab7 6475void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6476 struct intel_load_detect_pipe *old)
79e53945 6477{
d2434ab7
DV		 6478 struct intel_encoder *intel_encoder =
6479 intel_attached_encoder(connector);
4ef69c7a 6480 struct drm_encoder *encoder = &intel_encoder->base;
79e53945 6481
d2dff872
CW		 6482 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6483 connector->base.id, drm_get_connector_name(connector),
6484 encoder->base.id, drm_get_encoder_name(encoder));
6485
8261b191 6486 if (old->load_detect_temp) {
fc303101
DV		 6487 struct drm_crtc *crtc = encoder->crtc;
6488
6489 to_intel_connector(connector)->new_encoder = NULL;
6490 intel_encoder->new_crtc = NULL;
6491 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872
CW		 6492
6493 if (old->release_fb)
6494 old->release_fb->funcs->destroy(old->release_fb);
6495
0622a53c 6496 return;
79e53945
JB		 6497 }
6498
c751ce4f 6499 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6500 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6501 connector->funcs->dpms(connector, old->dpms_mode);
79e53945
JB		 6502}
6503
6504/* Returns the clock of the currently programmed mode of the given pipe. */
6505static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6506{
6507 struct drm_i915_private *dev_priv = dev->dev_private;
6508 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6509 int pipe = intel_crtc->pipe;
548f245b 6510 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6511 u32 fp;
6512 intel_clock_t clock;
6513
6514 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6515 fp = I915_READ(FP0(pipe));
79e53945 6516 else
39adb7a5 6517 fp = I915_READ(FP1(pipe));
79e53945
JB		 6518
6519 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6520 if (IS_PINEVIEW(dev)) {
6521 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6522 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6523 } else {
6524 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6525 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6526 }
6527
a6c45cf0 6528 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6529 if (IS_PINEVIEW(dev))
6530 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6531 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6532 else
6533 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6534 DPLL_FPA01_P1_POST_DIV_SHIFT);
6535
6536 switch (dpll & DPLL_MODE_MASK) {
6537 case DPLLB_MODE_DAC_SERIAL:
6538 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6539 5 : 10;
6540 break;
6541 case DPLLB_MODE_LVDS:
6542 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6543 7 : 14;
6544 break;
6545 default:
28c97730 6546 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6547 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6548 return 0;
6549 }
6550
6551 /* XXX: Handle the 100Mhz refclk */
2177832f 6552 intel_clock(dev, 96000, &clock);
79e53945
JB		 6553 } else {
6554 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6555
6556 if (is_lvds) {
6557 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6558 DPLL_FPA01_P1_POST_DIV_SHIFT);
6559 clock.p2 = 14;
6560
6561 if ((dpll & PLL_REF_INPUT_MASK) ==
6562 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6563 /* XXX: might not be 66MHz */
2177832f 6564 intel_clock(dev, 66000, &clock);
79e53945 6565 } else
2177832f 6566 intel_clock(dev, 48000, &clock);
79e53945
JB		 6567 } else {
6568 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6569 clock.p1 = 2;
6570 else {
6571 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6572 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6573 }
6574 if (dpll & PLL_P2_DIVIDE_BY_4)
6575 clock.p2 = 4;
6576 else
6577 clock.p2 = 2;
6578
2177832f 6579 intel_clock(dev, 48000, &clock);
79e53945
JB		 6580 }
6581 }
6582
6583 /* XXX: It would be nice to validate the clocks, but we can't reuse
6584 * i830PllIsValid() because it relies on the xf86_config connector
6585 * configuration being accurate, which it isn't necessarily.
6586 */
6587
6588 return clock.dot;
6589}
6590
6591/** Returns the currently programmed mode of the given pipe. */
6592struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6593 struct drm_crtc *crtc)
6594{
548f245b 6595 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6596 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fe2b8f9d 6597 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
79e53945 6598 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6599 int htot = I915_READ(HTOTAL(cpu_transcoder));
6600 int hsync = I915_READ(HSYNC(cpu_transcoder));
6601 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6602 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6603
6604 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6605 if (!mode)
6606 return NULL;
6607
6608 mode->clock = intel_crtc_clock_get(dev, crtc);
6609 mode->hdisplay = (htot & 0xffff) + 1;
6610 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6611 mode->hsync_start = (hsync & 0xffff) + 1;
6612 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6613 mode->vdisplay = (vtot & 0xffff) + 1;
6614 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6615 mode->vsync_start = (vsync & 0xffff) + 1;
6616 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6617
6618 drm_mode_set_name(mode);
79e53945
JB		 6619
6620 return mode;
6621}
6622
3dec0095 6623static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6624{
6625 struct drm_device *dev = crtc->dev;
6626 drm_i915_private_t *dev_priv = dev->dev_private;
6627 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6628 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6629 int dpll_reg = DPLL(pipe);
6630 int dpll;
652c393a 6631
bad720ff 6632 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6633 return;
6634
6635 if (!dev_priv->lvds_downclock_avail)
6636 return;
6637
dbdc6479 6638 dpll = I915_READ(dpll_reg);
652c393a 6639 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6640 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6641
8ac5a6d5 6642 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6643
6644 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6645 I915_WRITE(dpll_reg, dpll);
9d0498a2 6646 intel_wait_for_vblank(dev, pipe);
dbdc6479 6647
652c393a
JB		 6648 dpll = I915_READ(dpll_reg);
6649 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6650 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6651 }
652c393a
JB		 6652}
6653
6654static void intel_decrease_pllclock(struct drm_crtc *crtc)
6655{
6656 struct drm_device *dev = crtc->dev;
6657 drm_i915_private_t *dev_priv = dev->dev_private;
6658 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6659
bad720ff 6660 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6661 return;
6662
6663 if (!dev_priv->lvds_downclock_avail)
6664 return;
6665
6666 /*
6667 * Since this is called by a timer, we should never get here in
6668 * the manual case.
6669 */
6670 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6671 int pipe = intel_crtc->pipe;
6672 int dpll_reg = DPLL(pipe);
6673 int dpll;
f6e5b160 6674
44d98a61 6675 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6676
8ac5a6d5 6677 assert_panel_unlocked(dev_priv, pipe);
652c393a 6678
dc257cf1 6679 dpll = I915_READ(dpll_reg);
652c393a
JB		 6680 dpll |= DISPLAY_RATE_SELECT_FPA1;
6681 I915_WRITE(dpll_reg, dpll);
9d0498a2 6682 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6683 dpll = I915_READ(dpll_reg);
6684 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6685 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6686 }
6687
6688}
6689
f047e395
CW		 6690void intel_mark_busy(struct drm_device *dev)
6691{
f047e395
CW		 6692 i915_update_gfx_val(dev->dev_private);
6693}
6694
6695void intel_mark_idle(struct drm_device *dev)
652c393a 6696{
f047e395
CW		 6697}
6698
6699void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6700{
6701 struct drm_device *dev = obj->base.dev;
652c393a 6702 struct drm_crtc *crtc;
652c393a
JB		 6703
6704 if (!i915_powersave)
6705 return;
6706
652c393a 6707 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6708 if (!crtc->fb)
6709 continue;
6710
f047e395
CW		 6711 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6712 intel_increase_pllclock(crtc);
652c393a 6713 }
652c393a
JB		 6714}
6715
f047e395 6716void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
652c393a 6717{
f047e395
CW		 6718 struct drm_device *dev = obj->base.dev;
6719 struct drm_crtc *crtc;
652c393a 6720
f047e395 6721 if (!i915_powersave)
acb87dfb
CW		 6722 return;
6723
652c393a
JB		 6724 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6725 if (!crtc->fb)
6726 continue;
6727
f047e395
CW		 6728 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6729 intel_decrease_pllclock(crtc);
652c393a
JB		 6730 }
6731}
6732
79e53945
JB		 6733static void intel_crtc_destroy(struct drm_crtc *crtc)
6734{
6735 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6736 struct drm_device *dev = crtc->dev;
6737 struct intel_unpin_work *work;
6738 unsigned long flags;
6739
6740 spin_lock_irqsave(&dev->event_lock, flags);
6741 work = intel_crtc->unpin_work;
6742 intel_crtc->unpin_work = NULL;
6743 spin_unlock_irqrestore(&dev->event_lock, flags);
6744
6745 if (work) {
6746 cancel_work_sync(&work->work);
6747 kfree(work);
6748 }
79e53945
JB		 6749
6750 drm_crtc_cleanup(crtc);
67e77c5a 6751
79e53945
JB		 6752 kfree(intel_crtc);
6753}
6754
6b95a207
KH		 6755static void intel_unpin_work_fn(struct work_struct *__work)
6756{
6757 struct intel_unpin_work *work =
6758 container_of(__work, struct intel_unpin_work, work);
b4a98e57 6759 struct drm_device *dev = work->crtc->dev;
6b95a207 6760
b4a98e57 6761 mutex_lock(&dev->struct_mutex);
1690e1eb 6762 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 6763 drm_gem_object_unreference(&work->pending_flip_obj->base);
6764 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6765
b4a98e57
CW		 6766 intel_update_fbc(dev);
6767 mutex_unlock(&dev->struct_mutex);
6768
6769 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
6770 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
6771
6b95a207
KH		 6772 kfree(work);
6773}
6774
1afe3e9d 6775static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6776 struct drm_crtc *crtc)
6b95a207
KH		 6777{
6778 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6779 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6780 struct intel_unpin_work *work;
05394f39 6781 struct drm_i915_gem_object *obj;
6b95a207
KH		 6782 unsigned long flags;
6783
6784 /* Ignore early vblank irqs */
6785 if (intel_crtc == NULL)
6786 return;
6787
6788 spin_lock_irqsave(&dev->event_lock, flags);
6789 work = intel_crtc->unpin_work;
6790 if (work == NULL || !work->pending) {
6791 spin_unlock_irqrestore(&dev->event_lock, flags);
6792 return;
6793 }
6794
6795 intel_crtc->unpin_work = NULL;
6b95a207 6796
45a066eb
RC		 6797 if (work->event)
6798 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 6799
0af7e4df
MK		 6800 drm_vblank_put(dev, intel_crtc->pipe);
6801
6b95a207
KH		 6802 spin_unlock_irqrestore(&dev->event_lock, flags);
6803
05394f39 6804 obj = work->old_fb_obj;
d9e86c0e 6805
5bb61643 6806 wake_up(&dev_priv->pending_flip_queue);
b4a98e57
CW		 6807
6808 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 6809
6810 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6811}
6812
1afe3e9d
JB		 6813void intel_finish_page_flip(struct drm_device *dev, int pipe)
6814{
6815 drm_i915_private_t *dev_priv = dev->dev_private;
6816 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6817
49b14a5c 6818 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6819}
6820
6821void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6822{
6823 drm_i915_private_t *dev_priv = dev->dev_private;
6824 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6825
49b14a5c 6826 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6827}
6828
6b95a207
KH		 6829void intel_prepare_page_flip(struct drm_device *dev, int plane)
6830{
6831 drm_i915_private_t *dev_priv = dev->dev_private;
6832 struct intel_crtc *intel_crtc =
6833 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6834 unsigned long flags;
6835
6836 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 6837 if (intel_crtc->unpin_work) {
4e5359cd
SF		 6838 if ((++intel_crtc->unpin_work->pending) > 1)
6839 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 6840 } else {
6841 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6842 }
6b95a207
KH		 6843 spin_unlock_irqrestore(&dev->event_lock, flags);
6844}
6845
8c9f3aaf
JB		 6846static int intel_gen2_queue_flip(struct drm_device *dev,
6847 struct drm_crtc *crtc,
6848 struct drm_framebuffer *fb,
6849 struct drm_i915_gem_object *obj)
6850{
6851 struct drm_i915_private *dev_priv = dev->dev_private;
6852 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6853 u32 flip_mask;
6d90c952 6854 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6855 int ret;
6856
6d90c952 6857 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6858 if (ret)
83d4092b 6859 goto err;
8c9f3aaf 6860
6d90c952 6861 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6862 if (ret)
83d4092b 6863 goto err_unpin;
8c9f3aaf
JB		 6864
6865 /* Can't queue multiple flips, so wait for the previous
6866 * one to finish before executing the next.
6867 */
6868 if (intel_crtc->plane)
6869 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6870 else
6871 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6872 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6873 intel_ring_emit(ring, MI_NOOP);
6874 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6875 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6876 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6877 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 6878 intel_ring_emit(ring, 0); /* aux display base address, unused */
6879 intel_ring_advance(ring);
83d4092b
CW		 6880 return 0;
6881
6882err_unpin:
6883 intel_unpin_fb_obj(obj);
6884err:
8c9f3aaf
JB		 6885 return ret;
6886}
6887
6888static int intel_gen3_queue_flip(struct drm_device *dev,
6889 struct drm_crtc *crtc,
6890 struct drm_framebuffer *fb,
6891 struct drm_i915_gem_object *obj)
6892{
6893 struct drm_i915_private *dev_priv = dev->dev_private;
6894 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6895 u32 flip_mask;
6d90c952 6896 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6897 int ret;
6898
6d90c952 6899 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6900 if (ret)
83d4092b 6901 goto err;
8c9f3aaf 6902
6d90c952 6903 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6904 if (ret)
83d4092b 6905 goto err_unpin;
8c9f3aaf
JB		 6906
6907 if (intel_crtc->plane)
6908 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6909 else
6910 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6911 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6912 intel_ring_emit(ring, MI_NOOP);
6913 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6914 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6915 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6916 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 6917 intel_ring_emit(ring, MI_NOOP);
6918
6919 intel_ring_advance(ring);
83d4092b
CW		 6920 return 0;
6921
6922err_unpin:
6923 intel_unpin_fb_obj(obj);
6924err:
8c9f3aaf
JB		 6925 return ret;
6926}
6927
6928static int intel_gen4_queue_flip(struct drm_device *dev,
6929 struct drm_crtc *crtc,
6930 struct drm_framebuffer *fb,
6931 struct drm_i915_gem_object *obj)
6932{
6933 struct drm_i915_private *dev_priv = dev->dev_private;
6934 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6935 uint32_t pf, pipesrc;
6d90c952 6936 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6937 int ret;
6938
6d90c952 6939 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6940 if (ret)
83d4092b 6941 goto err;
8c9f3aaf 6942
6d90c952 6943 ret = intel_ring_begin(ring, 4);
8c9f3aaf 6944 if (ret)
83d4092b 6945 goto err_unpin;
8c9f3aaf
JB		 6946
6947 /* i965+ uses the linear or tiled offsets from the
6948 * Display Registers (which do not change across a page-flip)
6949 * so we need only reprogram the base address.
6950 */
6d90c952
DV		 6951 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6952 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6953 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 6954 intel_ring_emit(ring,
6955 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6956 obj->tiling_mode);
8c9f3aaf
JB		 6957
6958 /* XXX Enabling the panel-fitter across page-flip is so far
6959 * untested on non-native modes, so ignore it for now.
6960 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6961 */
6962 pf = 0;
6963 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 6964 intel_ring_emit(ring, pf | pipesrc);
6965 intel_ring_advance(ring);
83d4092b
CW		 6966 return 0;
6967
6968err_unpin:
6969 intel_unpin_fb_obj(obj);
6970err:
8c9f3aaf
JB		 6971 return ret;
6972}
6973
6974static int intel_gen6_queue_flip(struct drm_device *dev,
6975 struct drm_crtc *crtc,
6976 struct drm_framebuffer *fb,
6977 struct drm_i915_gem_object *obj)
6978{
6979 struct drm_i915_private *dev_priv = dev->dev_private;
6980 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 6981 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6982 uint32_t pf, pipesrc;
6983 int ret;
6984
6d90c952 6985 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6986 if (ret)
83d4092b 6987 goto err;
8c9f3aaf 6988
6d90c952 6989 ret = intel_ring_begin(ring, 4);
8c9f3aaf 6990 if (ret)
83d4092b 6991 goto err_unpin;
8c9f3aaf 6992
6d90c952
DV		 6993 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6994 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6995 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 6996 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 6997
dc257cf1
DV		 6998 /* Contrary to the suggestions in the documentation,
6999 * "Enable Panel Fitter" does not seem to be required when page
7000 * flipping with a non-native mode, and worse causes a normal
7001 * modeset to fail.
7002 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7003 */
7004 pf = 0;
8c9f3aaf 7005 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 7006 intel_ring_emit(ring, pf | pipesrc);
7007 intel_ring_advance(ring);
83d4092b
CW		 7008 return 0;
7009
7010err_unpin:
7011 intel_unpin_fb_obj(obj);
7012err:
8c9f3aaf
JB		 7013 return ret;
7014}
7015
7c9017e5
JB		 7016/*
7017 * On gen7 we currently use the blit ring because (in early silicon at least)
7018 * the render ring doesn't give us interrpts for page flip completion, which
7019 * means clients will hang after the first flip is queued. Fortunately the
7020 * blit ring generates interrupts properly, so use it instead.
7021 */
7022static int intel_gen7_queue_flip(struct drm_device *dev,
7023 struct drm_crtc *crtc,
7024 struct drm_framebuffer *fb,
7025 struct drm_i915_gem_object *obj)
7026{
7027 struct drm_i915_private *dev_priv = dev->dev_private;
7028 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7029 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7030 uint32_t plane_bit = 0;
7c9017e5
JB		 7031 int ret;
7032
7033 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7034 if (ret)
83d4092b 7035 goto err;
7c9017e5 7036
cb05d8de
DV		 7037 switch(intel_crtc->plane) {
7038 case PLANE_A:
7039 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7040 break;
7041 case PLANE_B:
7042 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7043 break;
7044 case PLANE_C:
7045 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7046 break;
7047 default:
7048 WARN_ONCE(1, "unknown plane in flip command\n");
7049 ret = -ENODEV;
ab3951eb 7050 goto err_unpin;
cb05d8de
DV		 7051 }
7052
7c9017e5
JB		 7053 ret = intel_ring_begin(ring, 4);
7054 if (ret)
83d4092b 7055 goto err_unpin;
7c9017e5 7056
cb05d8de 7057 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7058 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7059 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5
JB		 7060 intel_ring_emit(ring, (MI_NOOP));
7061 intel_ring_advance(ring);
83d4092b
CW		 7062 return 0;
7063
7064err_unpin:
7065 intel_unpin_fb_obj(obj);
7066err:
7c9017e5
JB		 7067 return ret;
7068}
7069
8c9f3aaf
JB		 7070static int intel_default_queue_flip(struct drm_device *dev,
7071 struct drm_crtc *crtc,
7072 struct drm_framebuffer *fb,
7073 struct drm_i915_gem_object *obj)
7074{
7075 return -ENODEV;
7076}
7077
6b95a207
KH		 7078static int intel_crtc_page_flip(struct drm_crtc *crtc,
7079 struct drm_framebuffer *fb,
7080 struct drm_pending_vblank_event *event)
7081{
7082 struct drm_device *dev = crtc->dev;
7083 struct drm_i915_private *dev_priv = dev->dev_private;
7084 struct intel_framebuffer *intel_fb;
05394f39 7085 struct drm_i915_gem_object *obj;
6b95a207
KH		 7086 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7087 struct intel_unpin_work *work;
8c9f3aaf 7088 unsigned long flags;
52e68630 7089 int ret;
6b95a207 7090
e6a595d2
VS		 7091 /* Can't change pixel format via MI display flips. */
7092 if (fb->pixel_format != crtc->fb->pixel_format)
7093 return -EINVAL;
7094
7095 /*
7096 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7097 * Note that pitch changes could also affect these register.
7098 */
7099 if (INTEL_INFO(dev)->gen > 3 &&
7100 (fb->offsets[0] != crtc->fb->offsets[0] ||
7101 fb->pitches[0] != crtc->fb->pitches[0]))
7102 return -EINVAL;
7103
6b95a207
KH		 7104 work = kzalloc(sizeof *work, GFP_KERNEL);
7105 if (work == NULL)
7106 return -ENOMEM;
7107
6b95a207 7108 work->event = event;
b4a98e57 7109 work->crtc = crtc;
6b95a207 7110 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 7111 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 7112 INIT_WORK(&work->work, intel_unpin_work_fn);
7113
7317c75e
JB		 7114 ret = drm_vblank_get(dev, intel_crtc->pipe);
7115 if (ret)
7116 goto free_work;
7117
6b95a207
KH		 7118 /* We borrow the event spin lock for protecting unpin_work */
7119 spin_lock_irqsave(&dev->event_lock, flags);
7120 if (intel_crtc->unpin_work) {
7121 spin_unlock_irqrestore(&dev->event_lock, flags);
7122 kfree(work);
7317c75e 7123 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7124
7125 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7126 return -EBUSY;
7127 }
7128 intel_crtc->unpin_work = work;
7129 spin_unlock_irqrestore(&dev->event_lock, flags);
7130
7131 intel_fb = to_intel_framebuffer(fb);
7132 obj = intel_fb->obj;
7133
b4a98e57
CW		 7134 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7135 flush_workqueue(dev_priv->wq);
7136
79158103
CW		 7137 ret = i915_mutex_lock_interruptible(dev);
7138 if (ret)
7139 goto cleanup;
6b95a207 7140
75dfca80 7141 /* Reference the objects for the scheduled work. */
05394f39
CW		 7142 drm_gem_object_reference(&work->old_fb_obj->base);
7143 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7144
7145 crtc->fb = fb;
96b099fd 7146
e1f99ce6 7147 work->pending_flip_obj = obj;
e1f99ce6 7148
4e5359cd
SF		 7149 work->enable_stall_check = true;
7150
b4a98e57 7151 atomic_inc(&intel_crtc->unpin_work_count);
e1f99ce6 7152
8c9f3aaf
JB		 7153 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7154 if (ret)
7155 goto cleanup_pending;
6b95a207 7156
7782de3b 7157 intel_disable_fbc(dev);
f047e395 7158 intel_mark_fb_busy(obj);
6b95a207
KH		 7159 mutex_unlock(&dev->struct_mutex);
7160
e5510fac
JB		 7161 trace_i915_flip_request(intel_crtc->plane, obj);
7162
6b95a207 7163 return 0;
96b099fd 7164
8c9f3aaf 7165cleanup_pending:
b4a98e57 7166 atomic_dec(&intel_crtc->unpin_work_count);
05394f39
CW		 7167 drm_gem_object_unreference(&work->old_fb_obj->base);
7168 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7169 mutex_unlock(&dev->struct_mutex);
7170
79158103 7171cleanup:
96b099fd
CW		 7172 spin_lock_irqsave(&dev->event_lock, flags);
7173 intel_crtc->unpin_work = NULL;
7174 spin_unlock_irqrestore(&dev->event_lock, flags);
7175
7317c75e
JB		 7176 drm_vblank_put(dev, intel_crtc->pipe);
7177free_work:
96b099fd
CW		 7178 kfree(work);
7179
7180 return ret;
6b95a207
KH		 7181}
7182
f6e5b160 7183static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7184 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7185 .load_lut = intel_crtc_load_lut,
976f8a20 7186 .disable = intel_crtc_noop,
f6e5b160
CW		 7187};
7188
6ed0f796 7189bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7190{
6ed0f796
DV		 7191 struct intel_encoder *other_encoder;
7192 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7193
6ed0f796
DV		 7194 if (WARN_ON(!crtc))
7195 return false;
7196
7197 list_for_each_entry(other_encoder,
7198 &crtc->dev->mode_config.encoder_list,
7199 base.head) {
7200
7201 if (&other_encoder->new_crtc->base != crtc ||
7202 encoder == other_encoder)
7203 continue;
7204 else
7205 return true;
f47166d2
CW		 7206 }
7207
6ed0f796
DV		 7208 return false;
7209}
47f1c6c9 7210
50f56119
DV		 7211static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7212 struct drm_crtc *crtc)
7213{
7214 struct drm_device *dev;
7215 struct drm_crtc *tmp;
7216 int crtc_mask = 1;
47f1c6c9 7217
50f56119 7218 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7219
50f56119 7220 dev = crtc->dev;
47f1c6c9 7221
50f56119
DV		 7222 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7223 if (tmp == crtc)
7224 break;
7225 crtc_mask <<= 1;
7226 }
47f1c6c9 7227
50f56119
DV		 7228 if (encoder->possible_crtcs & crtc_mask)
7229 return true;
7230 return false;
47f1c6c9 7231}
79e53945 7232
9a935856
DV		 7233/**
7234 * intel_modeset_update_staged_output_state
7235 *
7236 * Updates the staged output configuration state, e.g. after we've read out the
7237 * current hw state.
7238 */
7239static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7240{
9a935856
DV		 7241 struct intel_encoder *encoder;
7242 struct intel_connector *connector;
f6e5b160 7243
9a935856
DV		 7244 list_for_each_entry(connector, &dev->mode_config.connector_list,
7245 base.head) {
7246 connector->new_encoder =
7247 to_intel_encoder(connector->base.encoder);
7248 }
f6e5b160 7249
9a935856
DV		 7250 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7251 base.head) {
7252 encoder->new_crtc =
7253 to_intel_crtc(encoder->base.crtc);
7254 }
f6e5b160
CW		 7255}
7256
9a935856
DV		 7257/**
7258 * intel_modeset_commit_output_state
7259 *
7260 * This function copies the stage display pipe configuration to the real one.
7261 */
7262static void intel_modeset_commit_output_state(struct drm_device *dev)
7263{
7264 struct intel_encoder *encoder;
7265 struct intel_connector *connector;
f6e5b160 7266
9a935856
DV		 7267 list_for_each_entry(connector, &dev->mode_config.connector_list,
7268 base.head) {
7269 connector->base.encoder = &connector->new_encoder->base;
7270 }
f6e5b160 7271
9a935856
DV		 7272 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7273 base.head) {
7274 encoder->base.crtc = &encoder->new_crtc->base;
7275 }
7276}
7277
7758a113
DV		 7278static struct drm_display_mode *
7279intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7280 struct drm_display_mode *mode)
ee7b9f93 7281{
7758a113
DV		 7282 struct drm_device *dev = crtc->dev;
7283 struct drm_display_mode *adjusted_mode;
7284 struct drm_encoder_helper_funcs *encoder_funcs;
7285 struct intel_encoder *encoder;
ee7b9f93 7286
7758a113
DV		 7287 adjusted_mode = drm_mode_duplicate(dev, mode);
7288 if (!adjusted_mode)
7289 return ERR_PTR(-ENOMEM);
7290
7291 /* Pass our mode to the connectors and the CRTC to give them a chance to
7292 * adjust it according to limitations or connector properties, and also
7293 * a chance to reject the mode entirely.
47f1c6c9 7294 */
7758a113
DV		 7295 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7296 base.head) {
47f1c6c9 7297
7758a113
DV		 7298 if (&encoder->new_crtc->base != crtc)
7299 continue;
7300 encoder_funcs = encoder->base.helper_private;
7301 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7302 adjusted_mode))) {
7303 DRM_DEBUG_KMS("Encoder fixup failed\n");
7304 goto fail;
7305 }
ee7b9f93 7306 }
47f1c6c9 7307
7758a113
DV		 7308 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7309 DRM_DEBUG_KMS("CRTC fixup failed\n");
7310 goto fail;
ee7b9f93 7311 }
7758a113 7312 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
47f1c6c9 7313
7758a113
DV		 7314 return adjusted_mode;
7315fail:
7316 drm_mode_destroy(dev, adjusted_mode);
7317 return ERR_PTR(-EINVAL);
ee7b9f93 7318}
47f1c6c9 7319
e2e1ed41
DV		 7320/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7321 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7322static void
7323intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7324 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7325{
7326 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7327 struct drm_device *dev = crtc->dev;
7328 struct intel_encoder *encoder;
7329 struct intel_connector *connector;
7330 struct drm_crtc *tmp_crtc;
79e53945 7331
e2e1ed41 7332 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7333
e2e1ed41
DV		 7334 /* Check which crtcs have changed outputs connected to them, these need
7335 * to be part of the prepare_pipes mask. We don't (yet) support global
7336 * modeset across multiple crtcs, so modeset_pipes will only have one
7337 * bit set at most. */
7338 list_for_each_entry(connector, &dev->mode_config.connector_list,
7339 base.head) {
7340 if (connector->base.encoder == &connector->new_encoder->base)
7341 continue;
79e53945 7342
e2e1ed41
DV		 7343 if (connector->base.encoder) {
7344 tmp_crtc = connector->base.encoder->crtc;
7345
7346 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7347 }
7348
7349 if (connector->new_encoder)
7350 *prepare_pipes |=
7351 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7352 }
7353
e2e1ed41
DV		 7354 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7355 base.head) {
7356 if (encoder->base.crtc == &encoder->new_crtc->base)
7357 continue;
7358
7359 if (encoder->base.crtc) {
7360 tmp_crtc = encoder->base.crtc;
7361
7362 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7363 }
7364
7365 if (encoder->new_crtc)
7366 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7367 }
7368
e2e1ed41
DV		 7369 /* Check for any pipes that will be fully disabled ... */
7370 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7371 base.head) {
7372 bool used = false;
22fd0fab 7373
e2e1ed41
DV		 7374 /* Don't try to disable disabled crtcs. */
7375 if (!intel_crtc->base.enabled)
7376 continue;
7e7d76c3 7377
e2e1ed41
DV		 7378 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7379 base.head) {
7380 if (encoder->new_crtc == intel_crtc)
7381 used = true;
7382 }
7383
7384 if (!used)
7385 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7386 }
7387
e2e1ed41
DV		 7388
7389 /* set_mode is also used to update properties on life display pipes. */
7390 intel_crtc = to_intel_crtc(crtc);
7391 if (crtc->enabled)
7392 *prepare_pipes |= 1 << intel_crtc->pipe;
7393
7394 /* We only support modeset on one single crtc, hence we need to do that
7395 * only for the passed in crtc iff we change anything else than just
7396 * disable crtcs.
7397 *
7398 * This is actually not true, to be fully compatible with the old crtc
7399 * helper we automatically disable _any_ output (i.e. doesn't need to be
7400 * connected to the crtc we're modesetting on) if it's disconnected.
7401 * Which is a rather nutty api (since changed the output configuration
7402 * without userspace's explicit request can lead to confusion), but
7403 * alas. Hence we currently need to modeset on all pipes we prepare. */
7404 if (*prepare_pipes)
7405 *modeset_pipes = *prepare_pipes;
7406
7407 /* ... and mask these out. */
7408 *modeset_pipes &= ~(*disable_pipes);
7409 *prepare_pipes &= ~(*disable_pipes);
47f1c6c9 7410}
79e53945 7411
ea9d758d 7412static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7413{
ea9d758d 7414 struct drm_encoder *encoder;
f6e5b160 7415 struct drm_device *dev = crtc->dev;
f6e5b160 7416
ea9d758d
DV		 7417 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7418 if (encoder->crtc == crtc)
7419 return true;
7420
7421 return false;
7422}
7423
7424static void
7425intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7426{
7427 struct intel_encoder *intel_encoder;
7428 struct intel_crtc *intel_crtc;
7429 struct drm_connector *connector;
7430
7431 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7432 base.head) {
7433 if (!intel_encoder->base.crtc)
7434 continue;
7435
7436 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7437
7438 if (prepare_pipes & (1 << intel_crtc->pipe))
7439 intel_encoder->connectors_active = false;
7440 }
7441
7442 intel_modeset_commit_output_state(dev);
7443
7444 /* Update computed state. */
7445 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7446 base.head) {
7447 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7448 }
7449
7450 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7451 if (!connector->encoder || !connector->encoder->crtc)
7452 continue;
7453
7454 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7455
7456 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7457 struct drm_property *dpms_property =
7458 dev->mode_config.dpms_property;
7459
ea9d758d 7460 connector->dpms = DRM_MODE_DPMS_ON;
662595df 7461 drm_object_property_set_value(&connector->base,
68d34720
DV		 7462 dpms_property,
7463 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7464
7465 intel_encoder = to_intel_encoder(connector->encoder);
7466 intel_encoder->connectors_active = true;
7467 }
7468 }
7469
7470}
7471
25c5b266
DV		 7472#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7473 list_for_each_entry((intel_crtc), \
7474 &(dev)->mode_config.crtc_list, \
7475 base.head) \
7476 if (mask & (1 <<(intel_crtc)->pipe)) \
7477
b980514c 7478void
8af6cf88
DV		 7479intel_modeset_check_state(struct drm_device *dev)
7480{
7481 struct intel_crtc *crtc;
7482 struct intel_encoder *encoder;
7483 struct intel_connector *connector;
7484
7485 list_for_each_entry(connector, &dev->mode_config.connector_list,
7486 base.head) {
7487 /* This also checks the encoder/connector hw state with the
7488 * ->get_hw_state callbacks. */
7489 intel_connector_check_state(connector);
7490
7491 WARN(&connector->new_encoder->base != connector->base.encoder,
7492 "connector's staged encoder doesn't match current encoder\n");
7493 }
7494
7495 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7496 base.head) {
7497 bool enabled = false;
7498 bool active = false;
7499 enum pipe pipe, tracked_pipe;
7500
7501 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7502 encoder->base.base.id,
7503 drm_get_encoder_name(&encoder->base));
7504
7505 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7506 "encoder's stage crtc doesn't match current crtc\n");
7507 WARN(encoder->connectors_active && !encoder->base.crtc,
7508 "encoder's active_connectors set, but no crtc\n");
7509
7510 list_for_each_entry(connector, &dev->mode_config.connector_list,
7511 base.head) {
7512 if (connector->base.encoder != &encoder->base)
7513 continue;
7514 enabled = true;
7515 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7516 active = true;
7517 }
7518 WARN(!!encoder->base.crtc != enabled,
7519 "encoder's enabled state mismatch "
7520 "(expected %i, found %i)\n",
7521 !!encoder->base.crtc, enabled);
7522 WARN(active && !encoder->base.crtc,
7523 "active encoder with no crtc\n");
7524
7525 WARN(encoder->connectors_active != active,
7526 "encoder's computed active state doesn't match tracked active state "
7527 "(expected %i, found %i)\n", active, encoder->connectors_active);
7528
7529 active = encoder->get_hw_state(encoder, &pipe);
7530 WARN(active != encoder->connectors_active,
7531 "encoder's hw state doesn't match sw tracking "
7532 "(expected %i, found %i)\n",
7533 encoder->connectors_active, active);
7534
7535 if (!encoder->base.crtc)
7536 continue;
7537
7538 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7539 WARN(active && pipe != tracked_pipe,
7540 "active encoder's pipe doesn't match"
7541 "(expected %i, found %i)\n",
7542 tracked_pipe, pipe);
7543
7544 }
7545
7546 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7547 base.head) {
7548 bool enabled = false;
7549 bool active = false;
7550
7551 DRM_DEBUG_KMS("[CRTC:%d]\n",
7552 crtc->base.base.id);
7553
7554 WARN(crtc->active && !crtc->base.enabled,
7555 "active crtc, but not enabled in sw tracking\n");
7556
7557 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7558 base.head) {
7559 if (encoder->base.crtc != &crtc->base)
7560 continue;
7561 enabled = true;
7562 if (encoder->connectors_active)
7563 active = true;
7564 }
7565 WARN(active != crtc->active,
7566 "crtc's computed active state doesn't match tracked active state "
7567 "(expected %i, found %i)\n", active, crtc->active);
7568 WARN(enabled != crtc->base.enabled,
7569 "crtc's computed enabled state doesn't match tracked enabled state "
7570 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7571
7572 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7573 }
7574}
7575
a6778b3c
DV		 7576bool intel_set_mode(struct drm_crtc *crtc,
7577 struct drm_display_mode *mode,
94352cf9 7578 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 7579{
7580 struct drm_device *dev = crtc->dev;
dbf2b54e 7581 drm_i915_private_t *dev_priv = dev->dev_private;
a6778b3c 7582 struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
25c5b266
DV		 7583 struct intel_crtc *intel_crtc;
7584 unsigned disable_pipes, prepare_pipes, modeset_pipes;
a6778b3c
DV		 7585 bool ret = true;
7586
e2e1ed41 7587 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 7588 &prepare_pipes, &disable_pipes);
7589
7590 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7591 modeset_pipes, prepare_pipes, disable_pipes);
e2e1ed41 7592
976f8a20
DV		 7593 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7594 intel_crtc_disable(&intel_crtc->base);
87f1faa6 7595
a6778b3c
DV		 7596 saved_hwmode = crtc->hwmode;
7597 saved_mode = crtc->mode;
a6778b3c 7598
25c5b266
DV		 7599 /* Hack: Because we don't (yet) support global modeset on multiple
7600 * crtcs, we don't keep track of the new mode for more than one crtc.
7601 * Hence simply check whether any bit is set in modeset_pipes in all the
7602 * pieces of code that are not yet converted to deal with mutliple crtcs
7603 * changing their mode at the same time. */
7604 adjusted_mode = NULL;
7605 if (modeset_pipes) {
7606 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7607 if (IS_ERR(adjusted_mode)) {
7608 return false;
7609 }
25c5b266 7610 }
a6778b3c 7611
ea9d758d
DV		 7612 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7613 if (intel_crtc->base.enabled)
7614 dev_priv->display.crtc_disable(&intel_crtc->base);
7615 }
a6778b3c 7616
6c4c86f5
DV		 7617 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7618 * to set it here already despite that we pass it down the callchain.
f6e5b160 7619 */
6c4c86f5 7620 if (modeset_pipes)
25c5b266 7621 crtc->mode = *mode;
7758a113 7622
ea9d758d
DV		 7623 /* Only after disabling all output pipelines that will be changed can we
7624 * update the the output configuration. */
7625 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 7626
47fab737
DV		 7627 if (dev_priv->display.modeset_global_resources)
7628 dev_priv->display.modeset_global_resources(dev);
7629
a6778b3c
DV		 7630 /* Set up the DPLL and any encoders state that needs to adjust or depend
7631 * on the DPLL.
f6e5b160 7632 */
25c5b266
DV		 7633 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7634 ret = !intel_crtc_mode_set(&intel_crtc->base,
7635 mode, adjusted_mode,
7636 x, y, fb);
7637 if (!ret)
7638 goto done;
a6778b3c
DV		 7639 }
7640
7641 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 7642 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7643 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 7644
25c5b266
DV		 7645 if (modeset_pipes) {
7646 /* Store real post-adjustment hardware mode. */
7647 crtc->hwmode = *adjusted_mode;
a6778b3c 7648
25c5b266
DV		 7649 /* Calculate and store various constants which
7650 * are later needed by vblank and swap-completion
7651 * timestamping. They are derived from true hwmode.
7652 */
7653 drm_calc_timestamping_constants(crtc);
7654 }
a6778b3c
DV		 7655
7656 /* FIXME: add subpixel order */
7657done:
7658 drm_mode_destroy(dev, adjusted_mode);
25c5b266 7659 if (!ret && crtc->enabled) {
a6778b3c
DV		 7660 crtc->hwmode = saved_hwmode;
7661 crtc->mode = saved_mode;
8af6cf88
DV		 7662 } else {
7663 intel_modeset_check_state(dev);
a6778b3c
DV		 7664 }
7665
7666 return ret;
f6e5b160
CW		 7667}
7668
25c5b266
DV		 7669#undef for_each_intel_crtc_masked
7670
d9e55608
DV		 7671static void intel_set_config_free(struct intel_set_config *config)
7672{
7673 if (!config)
7674 return;
7675
1aa4b628
DV		 7676 kfree(config->save_connector_encoders);
7677 kfree(config->save_encoder_crtcs);
d9e55608
DV		 7678 kfree(config);
7679}
7680
85f9eb71
DV		 7681static int intel_set_config_save_state(struct drm_device *dev,
7682 struct intel_set_config *config)
7683{
85f9eb71
DV		 7684 struct drm_encoder *encoder;
7685 struct drm_connector *connector;
7686 int count;
7687
1aa4b628
DV		 7688 config->save_encoder_crtcs =
7689 kcalloc(dev->mode_config.num_encoder,
7690 sizeof(struct drm_crtc *), GFP_KERNEL);
7691 if (!config->save_encoder_crtcs)
85f9eb71
DV		 7692 return -ENOMEM;
7693
1aa4b628
DV		 7694 config->save_connector_encoders =
7695 kcalloc(dev->mode_config.num_connector,
7696 sizeof(struct drm_encoder *), GFP_KERNEL);
7697 if (!config->save_connector_encoders)
85f9eb71
DV		 7698 return -ENOMEM;
7699
7700 /* Copy data. Note that driver private data is not affected.
7701 * Should anything bad happen only the expected state is
7702 * restored, not the drivers personal bookkeeping.
7703 */
85f9eb71
DV		 7704 count = 0;
7705 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 7706 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 7707 }
7708
7709 count = 0;
7710 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 7711 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 7712 }
7713
7714 return 0;
7715}
7716
7717static void intel_set_config_restore_state(struct drm_device *dev,
7718 struct intel_set_config *config)
7719{
9a935856
DV		 7720 struct intel_encoder *encoder;
7721 struct intel_connector *connector;
85f9eb71
DV		 7722 int count;
7723
85f9eb71 7724 count = 0;
9a935856
DV		 7725 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7726 encoder->new_crtc =
7727 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 7728 }
7729
7730 count = 0;
9a935856
DV		 7731 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7732 connector->new_encoder =
7733 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 7734 }
7735}
7736
5e2b584e
DV		 7737static void
7738intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7739 struct intel_set_config *config)
7740{
7741
7742 /* We should be able to check here if the fb has the same properties
7743 * and then just flip_or_move it */
7744 if (set->crtc->fb != set->fb) {
7745 /* If we have no fb then treat it as a full mode set */
7746 if (set->crtc->fb == NULL) {
7747 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7748 config->mode_changed = true;
7749 } else if (set->fb == NULL) {
7750 config->mode_changed = true;
7751 } else if (set->fb->depth != set->crtc->fb->depth) {
7752 config->mode_changed = true;
7753 } else if (set->fb->bits_per_pixel !=
7754 set->crtc->fb->bits_per_pixel) {
7755 config->mode_changed = true;
7756 } else
7757 config->fb_changed = true;
7758 }
7759
835c5873 7760 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 7761 config->fb_changed = true;
7762
7763 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7764 DRM_DEBUG_KMS("modes are different, full mode set\n");
7765 drm_mode_debug_printmodeline(&set->crtc->mode);
7766 drm_mode_debug_printmodeline(set->mode);
7767 config->mode_changed = true;
7768 }
7769}
7770
2e431051 7771static int
9a935856
DV		 7772intel_modeset_stage_output_state(struct drm_device *dev,
7773 struct drm_mode_set *set,
7774 struct intel_set_config *config)
50f56119 7775{
85f9eb71 7776 struct drm_crtc *new_crtc;
9a935856
DV		 7777 struct intel_connector *connector;
7778 struct intel_encoder *encoder;
2e431051 7779 int count, ro;
50f56119 7780
9a935856
DV		 7781 /* The upper layers ensure that we either disabl a crtc or have a list
7782 * of connectors. For paranoia, double-check this. */
7783 WARN_ON(!set->fb && (set->num_connectors != 0));
7784 WARN_ON(set->fb && (set->num_connectors == 0));
7785
50f56119 7786 count = 0;
9a935856
DV		 7787 list_for_each_entry(connector, &dev->mode_config.connector_list,
7788 base.head) {
7789 /* Otherwise traverse passed in connector list and get encoders
7790 * for them. */
50f56119 7791 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 7792 if (set->connectors[ro] == &connector->base) {
7793 connector->new_encoder = connector->encoder;
50f56119
DV		 7794 break;
7795 }
7796 }
7797
9a935856
DV		 7798 /* If we disable the crtc, disable all its connectors. Also, if
7799 * the connector is on the changing crtc but not on the new
7800 * connector list, disable it. */
7801 if ((!set->fb || ro == set->num_connectors) &&
7802 connector->base.encoder &&
7803 connector->base.encoder->crtc == set->crtc) {
7804 connector->new_encoder = NULL;
7805
7806 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7807 connector->base.base.id,
7808 drm_get_connector_name(&connector->base));
7809 }
7810
7811
7812 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 7813 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 7814 config->mode_changed = true;
50f56119 7815 }
9a935856
DV		 7816
7817 /* Disable all disconnected encoders. */
7818 if (connector->base.status == connector_status_disconnected)
7819 connector->new_encoder = NULL;
50f56119 7820 }
9a935856 7821 /* connector->new_encoder is now updated for all connectors. */
50f56119 7822
9a935856 7823 /* Update crtc of enabled connectors. */
50f56119 7824 count = 0;
9a935856
DV		 7825 list_for_each_entry(connector, &dev->mode_config.connector_list,
7826 base.head) {
7827 if (!connector->new_encoder)
50f56119
DV		 7828 continue;
7829
9a935856 7830 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 7831
7832 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 7833 if (set->connectors[ro] == &connector->base)
50f56119
DV		 7834 new_crtc = set->crtc;
7835 }
7836
7837 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 7838 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7839 new_crtc)) {
5e2b584e 7840 return -EINVAL;
50f56119 7841 }
9a935856
DV		 7842 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7843
7844 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7845 connector->base.base.id,
7846 drm_get_connector_name(&connector->base),
7847 new_crtc->base.id);
7848 }
7849
7850 /* Check for any encoders that needs to be disabled. */
7851 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7852 base.head) {
7853 list_for_each_entry(connector,
7854 &dev->mode_config.connector_list,
7855 base.head) {
7856 if (connector->new_encoder == encoder) {
7857 WARN_ON(!connector->new_encoder->new_crtc);
7858
7859 goto next_encoder;
7860 }
7861 }
7862 encoder->new_crtc = NULL;
7863next_encoder:
7864 /* Only now check for crtc changes so we don't miss encoders
7865 * that will be disabled. */
7866 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 7867 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 7868 config->mode_changed = true;
50f56119
DV		 7869 }
7870 }
9a935856 7871 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 7872
2e431051
DV		 7873 return 0;
7874}
7875
7876static int intel_crtc_set_config(struct drm_mode_set *set)
7877{
7878 struct drm_device *dev;
2e431051
DV		 7879 struct drm_mode_set save_set;
7880 struct intel_set_config *config;
7881 int ret;
2e431051 7882
8d3e375e
DV		 7883 BUG_ON(!set);
7884 BUG_ON(!set->crtc);
7885 BUG_ON(!set->crtc->helper_private);
2e431051
DV		 7886
7887 if (!set->mode)
7888 set->fb = NULL;
7889
431e50f7
DV		 7890 /* The fb helper likes to play gross jokes with ->mode_set_config.
7891 * Unfortunately the crtc helper doesn't do much at all for this case,
7892 * so we have to cope with this madness until the fb helper is fixed up. */
7893 if (set->fb && set->num_connectors == 0)
7894 return 0;
7895
2e431051
DV		 7896 if (set->fb) {
7897 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
7898 set->crtc->base.id, set->fb->base.id,
7899 (int)set->num_connectors, set->x, set->y);
7900 } else {
7901 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 7902 }
7903
7904 dev = set->crtc->dev;
7905
7906 ret = -ENOMEM;
7907 config = kzalloc(sizeof(*config), GFP_KERNEL);
7908 if (!config)
7909 goto out_config;
7910
7911 ret = intel_set_config_save_state(dev, config);
7912 if (ret)
7913 goto out_config;
7914
7915 save_set.crtc = set->crtc;
7916 save_set.mode = &set->crtc->mode;
7917 save_set.x = set->crtc->x;
7918 save_set.y = set->crtc->y;
7919 save_set.fb = set->crtc->fb;
7920
7921 /* Compute whether we need a full modeset, only an fb base update or no
7922 * change at all. In the future we might also check whether only the
7923 * mode changed, e.g. for LVDS where we only change the panel fitter in
7924 * such cases. */
7925 intel_set_config_compute_mode_changes(set, config);
7926
9a935856 7927 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 7928 if (ret)
7929 goto fail;
7930
5e2b584e 7931 if (config->mode_changed) {
87f1faa6 7932 if (set->mode) {
50f56119
DV		 7933 DRM_DEBUG_KMS("attempting to set mode from"
7934 " userspace\n");
7935 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 7936 }
7937
7938 if (!intel_set_mode(set->crtc, set->mode,
7939 set->x, set->y, set->fb)) {
7940 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
7941 set->crtc->base.id);
7942 ret = -EINVAL;
7943 goto fail;
7944 }
5e2b584e 7945 } else if (config->fb_changed) {
4f660f49 7946 ret = intel_pipe_set_base(set->crtc,
94352cf9 7947 set->x, set->y, set->fb);
50f56119
DV		 7948 }
7949
d9e55608
DV		 7950 intel_set_config_free(config);
7951
50f56119
DV		 7952 return 0;
7953
7954fail:
85f9eb71 7955 intel_set_config_restore_state(dev, config);
50f56119
DV		 7956
7957 /* Try to restore the config */
5e2b584e 7958 if (config->mode_changed &&
a6778b3c
DV		 7959 !intel_set_mode(save_set.crtc, save_set.mode,
7960 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 7961 DRM_ERROR("failed to restore config after modeset failure\n");
7962
d9e55608
DV		 7963out_config:
7964 intel_set_config_free(config);
50f56119
DV		 7965 return ret;
7966}
f6e5b160
CW		 7967
7968static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 7969 .cursor_set = intel_crtc_cursor_set,
7970 .cursor_move = intel_crtc_cursor_move,
7971 .gamma_set = intel_crtc_gamma_set,
50f56119 7972 .set_config = intel_crtc_set_config,
f6e5b160
CW		 7973 .destroy = intel_crtc_destroy,
7974 .page_flip = intel_crtc_page_flip,
7975};
7976
79f689aa
PZ		 7977static void intel_cpu_pll_init(struct drm_device *dev)
7978{
affa9354 7979 if (HAS_DDI(dev))
79f689aa
PZ		 7980 intel_ddi_pll_init(dev);
7981}
7982
ee7b9f93
JB		 7983static void intel_pch_pll_init(struct drm_device *dev)
7984{
7985 drm_i915_private_t *dev_priv = dev->dev_private;
7986 int i;
7987
7988 if (dev_priv->num_pch_pll == 0) {
7989 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
7990 return;
7991 }
7992
7993 for (i = 0; i < dev_priv->num_pch_pll; i++) {
7994 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
7995 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
7996 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
7997 }
7998}
7999
b358d0a6 8000static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8001{
22fd0fab 8002 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8003 struct intel_crtc *intel_crtc;
8004 int i;
8005
8006 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8007 if (intel_crtc == NULL)
8008 return;
8009
8010 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8011
8012 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8013 for (i = 0; i < 256; i++) {
8014 intel_crtc->lut_r[i] = i;
8015 intel_crtc->lut_g[i] = i;
8016 intel_crtc->lut_b[i] = i;
8017 }
8018
80824003
JB		 8019 /* Swap pipes & planes for FBC on pre-965 */
8020 intel_crtc->pipe = pipe;
8021 intel_crtc->plane = pipe;
a5c961d1 8022 intel_crtc->cpu_transcoder = pipe;
e2e767ab 8023 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8024 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8025 intel_crtc->plane = !pipe;
80824003
JB		 8026 }
8027
22fd0fab
JB		 8028 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8029 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8030 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8031 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8032
5a354204 8033 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3 8034
79e53945 8035 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8036}
8037
08d7b3d1 8038int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8039 struct drm_file *file)
08d7b3d1 8040{
08d7b3d1 8041 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8042 struct drm_mode_object *drmmode_obj;
8043 struct intel_crtc *crtc;
08d7b3d1 8044
1cff8f6b
DV		 8045 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8046 return -ENODEV;
08d7b3d1 8047
c05422d5
DV		 8048 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8049 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8050
c05422d5 8051 if (!drmmode_obj) {
08d7b3d1
CW		 8052 DRM_ERROR("no such CRTC id\n");
8053 return -EINVAL;
8054 }
8055
c05422d5
DV		 8056 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8057 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8058
c05422d5 8059 return 0;
08d7b3d1
CW		 8060}
8061
66a9278e 8062static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8063{
66a9278e
DV		 8064 struct drm_device *dev = encoder->base.dev;
8065 struct intel_encoder *source_encoder;
79e53945 8066 int index_mask = 0;
79e53945
JB		 8067 int entry = 0;
8068
66a9278e
DV		 8069 list_for_each_entry(source_encoder,
8070 &dev->mode_config.encoder_list, base.head) {
8071
8072 if (encoder == source_encoder)
79e53945 8073 index_mask |= (1 << entry);
66a9278e
DV		 8074
8075 /* Intel hw has only one MUX where enocoders could be cloned. */
8076 if (encoder->cloneable && source_encoder->cloneable)
8077 index_mask |= (1 << entry);
8078
79e53945
JB		 8079 entry++;
8080 }
4ef69c7a 8081
79e53945
JB		 8082 return index_mask;
8083}
8084
4d302442
CW		 8085static bool has_edp_a(struct drm_device *dev)
8086{
8087 struct drm_i915_private *dev_priv = dev->dev_private;
8088
8089 if (!IS_MOBILE(dev))
8090 return false;
8091
8092 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8093 return false;
8094
8095 if (IS_GEN5(dev) &&
8096 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8097 return false;
8098
8099 return true;
8100}
8101
79e53945
JB		 8102static void intel_setup_outputs(struct drm_device *dev)
8103{
725e30ad 8104 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8105 struct intel_encoder *encoder;
cb0953d7 8106 bool dpd_is_edp = false;
f3cfcba6 8107 bool has_lvds;
79e53945 8108
f3cfcba6 8109 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8110 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8111 /* disable the panel fitter on everything but LVDS */
8112 I915_WRITE(PFIT_CONTROL, 0);
8113 }
79e53945 8114
affa9354 8115 if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
79935fca 8116 intel_crt_init(dev);
cb0953d7 8117
affa9354 8118 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8119 int found;
8120
8121 /* Haswell uses DDI functions to detect digital outputs */
8122 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8123 /* DDI A only supports eDP */
8124 if (found)
8125 intel_ddi_init(dev, PORT_A);
8126
8127 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8128 * register */
8129 found = I915_READ(SFUSE_STRAP);
8130
8131 if (found & SFUSE_STRAP_DDIB_DETECTED)
8132 intel_ddi_init(dev, PORT_B);
8133 if (found & SFUSE_STRAP_DDIC_DETECTED)
8134 intel_ddi_init(dev, PORT_C);
8135 if (found & SFUSE_STRAP_DDID_DETECTED)
8136 intel_ddi_init(dev, PORT_D);
8137 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8138 int found;
270b3042
DV		 8139 dpd_is_edp = intel_dpd_is_edp(dev);
8140
8141 if (has_edp_a(dev))
8142 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8143
30ad48b7 8144 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca 8145 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8146 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8147 if (!found)
08d644ad 8148 intel_hdmi_init(dev, HDMIB, PORT_B);
5eb08b69 8149 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8150 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8151 }
8152
8153 if (I915_READ(HDMIC) & PORT_DETECTED)
08d644ad 8154 intel_hdmi_init(dev, HDMIC, PORT_C);
30ad48b7 8155
b708a1d5 8156 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
08d644ad 8157 intel_hdmi_init(dev, HDMID, PORT_D);
30ad48b7 8158
5eb08b69 8159 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8160 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8161
270b3042 8162 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8163 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d
JB		 8164 } else if (IS_VALLEYVIEW(dev)) {
8165 int found;
8166
19c03924
GB		 8167 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8168 if (I915_READ(DP_C) & DP_DETECTED)
8169 intel_dp_init(dev, DP_C, PORT_C);
8170
4a87d65d
JB		 8171 if (I915_READ(SDVOB) & PORT_DETECTED) {
8172 /* SDVOB multiplex with HDMIB */
8173 found = intel_sdvo_init(dev, SDVOB, true);
8174 if (!found)
08d644ad 8175 intel_hdmi_init(dev, SDVOB, PORT_B);
4a87d65d 8176 if (!found && (I915_READ(DP_B) & DP_DETECTED))
ab9d7c30 8177 intel_dp_init(dev, DP_B, PORT_B);
4a87d65d
JB		 8178 }
8179
8180 if (I915_READ(SDVOC) & PORT_DETECTED)
08d644ad 8181 intel_hdmi_init(dev, SDVOC, PORT_C);
5eb08b69 8182
103a196f 8183 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8184 bool found = false;
7d57382e 8185
725e30ad 8186 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 8187 DRM_DEBUG_KMS("probing SDVOB\n");
eef4eacb 8188 found = intel_sdvo_init(dev, SDVOB, true);
b01f2c3a
JB		 8189 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8190 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
08d644ad 8191 intel_hdmi_init(dev, SDVOB, PORT_B);
b01f2c3a 8192 }
27185ae1 8193
b01f2c3a
JB		 8194 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8195 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 8196 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 8197 }
725e30ad 8198 }
13520b05
KH		 8199
8200 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8201
b01f2c3a
JB		 8202 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8203 DRM_DEBUG_KMS("probing SDVOC\n");
eef4eacb 8204 found = intel_sdvo_init(dev, SDVOC, false);
b01f2c3a 8205 }
27185ae1
ML		 8206
8207 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8208
b01f2c3a
JB		 8209 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8210 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
08d644ad 8211 intel_hdmi_init(dev, SDVOC, PORT_C);
b01f2c3a
JB		 8212 }
8213 if (SUPPORTS_INTEGRATED_DP(dev)) {
8214 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 8215 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 8216 }
725e30ad 8217 }
27185ae1 8218
b01f2c3a
JB		 8219 if (SUPPORTS_INTEGRATED_DP(dev) &&
8220 (I915_READ(DP_D) & DP_DETECTED)) {
8221 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 8222 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 8223 }
bad720ff 8224 } else if (IS_GEN2(dev))
79e53945
JB		 8225 intel_dvo_init(dev);
8226
103a196f 8227 if (SUPPORTS_TV(dev))
79e53945
JB		 8228 intel_tv_init(dev);
8229
4ef69c7a
CW		 8230 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8231 encoder->base.possible_crtcs = encoder->crtc_mask;
8232 encoder->base.possible_clones =
66a9278e 8233 intel_encoder_clones(encoder);
79e53945 8234 }
47356eb6 8235
40579abe 8236 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9fb526db 8237 ironlake_init_pch_refclk(dev);
270b3042
DV		 8238
8239 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8240}
8241
8242static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8243{
8244 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8245
8246 drm_framebuffer_cleanup(fb);
05394f39 8247 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8248
8249 kfree(intel_fb);
8250}
8251
8252static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8253 struct drm_file *file,
79e53945
JB		 8254 unsigned int *handle)
8255{
8256 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8257 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8258
05394f39 8259 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8260}
8261
8262static const struct drm_framebuffer_funcs intel_fb_funcs = {
8263 .destroy = intel_user_framebuffer_destroy,
8264 .create_handle = intel_user_framebuffer_create_handle,
8265};
8266
38651674
DA		 8267int intel_framebuffer_init(struct drm_device *dev,
8268 struct intel_framebuffer *intel_fb,
308e5bcb 8269 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8270 struct drm_i915_gem_object *obj)
79e53945 8271{
79e53945
JB		 8272 int ret;
8273
05394f39 8274 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 8275 return -EINVAL;
8276
308e5bcb 8277 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 8278 return -EINVAL;
8279
5d7bd705
VS		 8280 /* FIXME <= Gen4 stride limits are bit unclear */
8281 if (mode_cmd->pitches[0] > 32768)
8282 return -EINVAL;
8283
8284 if (obj->tiling_mode != I915_TILING_NONE &&
8285 mode_cmd->pitches[0] != obj->stride)
8286 return -EINVAL;
8287
57779d06 8288 /* Reject formats not supported by any plane early. */
308e5bcb 8289 switch (mode_cmd->pixel_format) {
57779d06 8290 case DRM_FORMAT_C8:
04b3924d
VS		 8291 case DRM_FORMAT_RGB565:
8292 case DRM_FORMAT_XRGB8888:
8293 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8294 break;
8295 case DRM_FORMAT_XRGB1555:
8296 case DRM_FORMAT_ARGB1555:
8297 if (INTEL_INFO(dev)->gen > 3)
8298 return -EINVAL;
8299 break;
8300 case DRM_FORMAT_XBGR8888:
8301 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8302 case DRM_FORMAT_XRGB2101010:
8303 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8304 case DRM_FORMAT_XBGR2101010:
8305 case DRM_FORMAT_ABGR2101010:
8306 if (INTEL_INFO(dev)->gen < 4)
8307 return -EINVAL;
b5626747 8308 break;
04b3924d
VS		 8309 case DRM_FORMAT_YUYV:
8310 case DRM_FORMAT_UYVY:
8311 case DRM_FORMAT_YVYU:
8312 case DRM_FORMAT_VYUY:
57779d06
VS		 8313 if (INTEL_INFO(dev)->gen < 6)
8314 return -EINVAL;
57cd6508
CW		 8315 break;
8316 default:
57779d06 8317 DRM_DEBUG_KMS("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8318 return -EINVAL;
8319 }
8320
90f9a336
VS		 8321 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8322 if (mode_cmd->offsets[0] != 0)
8323 return -EINVAL;
8324
79e53945
JB		 8325 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8326 if (ret) {
8327 DRM_ERROR("framebuffer init failed %d\n", ret);
8328 return ret;
8329 }
8330
8331 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 8332 intel_fb->obj = obj;
79e53945
JB		 8333 return 0;
8334}
8335
79e53945
JB		 8336static struct drm_framebuffer *
8337intel_user_framebuffer_create(struct drm_device *dev,
8338 struct drm_file *filp,
308e5bcb 8339 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8340{
05394f39 8341 struct drm_i915_gem_object *obj;
79e53945 8342
308e5bcb
JB		 8343 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8344 mode_cmd->handles[0]));
c8725226 8345 if (&obj->base == NULL)
cce13ff7 8346 return ERR_PTR(-ENOENT);
79e53945 8347
d2dff872 8348 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8349}
8350
79e53945 8351static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8352 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8353 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8354};
8355
e70236a8
JB		 8356/* Set up chip specific display functions */
8357static void intel_init_display(struct drm_device *dev)
8358{
8359 struct drm_i915_private *dev_priv = dev->dev_private;
8360
8361 /* We always want a DPMS function */
affa9354 8362 if (HAS_DDI(dev)) {
09b4ddf9 8363 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8364 dev_priv->display.crtc_enable = haswell_crtc_enable;
8365 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 8366 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 8367 dev_priv->display.update_plane = ironlake_update_plane;
8368 } else if (HAS_PCH_SPLIT(dev)) {
f564048e 8369 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 8370 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8371 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8372 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8373 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8374 } else {
f564048e 8375 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 8376 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8377 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8378 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8379 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8380 }
e70236a8 8381
e70236a8 8382 /* Returns the core display clock speed */
25eb05fc
JB		 8383 if (IS_VALLEYVIEW(dev))
8384 dev_priv->display.get_display_clock_speed =
8385 valleyview_get_display_clock_speed;
8386 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8387 dev_priv->display.get_display_clock_speed =
8388 i945_get_display_clock_speed;
8389 else if (IS_I915G(dev))
8390 dev_priv->display.get_display_clock_speed =
8391 i915_get_display_clock_speed;
f2b115e6 8392 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8393 dev_priv->display.get_display_clock_speed =
8394 i9xx_misc_get_display_clock_speed;
8395 else if (IS_I915GM(dev))
8396 dev_priv->display.get_display_clock_speed =
8397 i915gm_get_display_clock_speed;
8398 else if (IS_I865G(dev))
8399 dev_priv->display.get_display_clock_speed =
8400 i865_get_display_clock_speed;
f0f8a9ce 8401 else if (IS_I85X(dev))
e70236a8
JB		 8402 dev_priv->display.get_display_clock_speed =
8403 i855_get_display_clock_speed;
8404 else /* 852, 830 */
8405 dev_priv->display.get_display_clock_speed =
8406 i830_get_display_clock_speed;
8407
7f8a8569 8408 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8409 if (IS_GEN5(dev)) {
674cf967 8410 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8411 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8412 } else if (IS_GEN6(dev)) {
674cf967 8413 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8414 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8415 } else if (IS_IVYBRIDGE(dev)) {
8416 /* FIXME: detect B0+ stepping and use auto training */
8417 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 8418 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 8419 dev_priv->display.modeset_global_resources =
8420 ivb_modeset_global_resources;
c82e4d26
ED		 8421 } else if (IS_HASWELL(dev)) {
8422 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 8423 dev_priv->display.write_eld = haswell_write_eld;
7f8a8569
ZW		 8424 } else
8425 dev_priv->display.update_wm = NULL;
6067aaea 8426 } else if (IS_G4X(dev)) {
e0dac65e 8427 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8428 }
8c9f3aaf
JB		 8429
8430 /* Default just returns -ENODEV to indicate unsupported */
8431 dev_priv->display.queue_flip = intel_default_queue_flip;
8432
8433 switch (INTEL_INFO(dev)->gen) {
8434 case 2:
8435 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8436 break;
8437
8438 case 3:
8439 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8440 break;
8441
8442 case 4:
8443 case 5:
8444 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8445 break;
8446
8447 case 6:
8448 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8449 break;
7c9017e5
JB		 8450 case 7:
8451 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8452 break;
8c9f3aaf 8453 }
e70236a8
JB		 8454}
8455
b690e96c
JB		 8456/*
8457 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8458 * resume, or other times. This quirk makes sure that's the case for
8459 * affected systems.
8460 */
0206e353 8461static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8462{
8463 struct drm_i915_private *dev_priv = dev->dev_private;
8464
8465 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 8466 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 8467}
8468
435793df
KP		 8469/*
8470 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8471 */
8472static void quirk_ssc_force_disable(struct drm_device *dev)
8473{
8474 struct drm_i915_private *dev_priv = dev->dev_private;
8475 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 8476 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 8477}
8478
4dca20ef 8479/*
5a15ab5b
CE		 8480 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8481 * brightness value
4dca20ef
CE		 8482 */
8483static void quirk_invert_brightness(struct drm_device *dev)
8484{
8485 struct drm_i915_private *dev_priv = dev->dev_private;
8486 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 8487 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 8488}
8489
b690e96c
JB		 8490struct intel_quirk {
8491 int device;
8492 int subsystem_vendor;
8493 int subsystem_device;
8494 void (*hook)(struct drm_device *dev);
8495};
8496
5f85f176
EE		 8497/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8498struct intel_dmi_quirk {
8499 void (*hook)(struct drm_device *dev);
8500 const struct dmi_system_id (*dmi_id_list)[];
8501};
8502
8503static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8504{
8505 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8506 return 1;
8507}
8508
8509static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8510 {
8511 .dmi_id_list = &(const struct dmi_system_id[]) {
8512 {
8513 .callback = intel_dmi_reverse_brightness,
8514 .ident = "NCR Corporation",
8515 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8516 DMI_MATCH(DMI_PRODUCT_NAME, ""),
8517 },
8518 },
8519 { } /* terminating entry */
8520 },
8521 .hook = quirk_invert_brightness,
8522 },
8523};
8524
c43b5634 8525static struct intel_quirk intel_quirks[] = {
b690e96c 8526 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8527 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 8528
b690e96c
JB		 8529 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8530 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8531
b690e96c
JB		 8532 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8533 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8534
ccd0d36e 8535 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 8536 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 8537 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 8538
8539 /* Lenovo U160 cannot use SSC on LVDS */
8540 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 8541
8542 /* Sony Vaio Y cannot use SSC on LVDS */
8543 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 8544
8545 /* Acer Aspire 5734Z must invert backlight brightness */
8546 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
b690e96c
JB		 8547};
8548
8549static void intel_init_quirks(struct drm_device *dev)
8550{
8551 struct pci_dev *d = dev->pdev;
8552 int i;
8553
8554 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8555 struct intel_quirk *q = &intel_quirks[i];
8556
8557 if (d->device == q->device &&
8558 (d->subsystem_vendor == q->subsystem_vendor ||
8559 q->subsystem_vendor == PCI_ANY_ID) &&
8560 (d->subsystem_device == q->subsystem_device ||
8561 q->subsystem_device == PCI_ANY_ID))
8562 q->hook(dev);
8563 }
5f85f176
EE		 8564 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8565 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8566 intel_dmi_quirks[i].hook(dev);
8567 }
b690e96c
JB		 8568}
8569
9cce37f4
JB		 8570/* Disable the VGA plane that we never use */
8571static void i915_disable_vga(struct drm_device *dev)
8572{
8573 struct drm_i915_private *dev_priv = dev->dev_private;
8574 u8 sr1;
8575 u32 vga_reg;
8576
8577 if (HAS_PCH_SPLIT(dev))
8578 vga_reg = CPU_VGACNTRL;
8579 else
8580 vga_reg = VGACNTRL;
8581
8582 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 8583 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 8584 sr1 = inb(VGA_SR_DATA);
8585 outb(sr1 | 1<<5, VGA_SR_DATA);
8586 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8587 udelay(300);
8588
8589 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8590 POSTING_READ(vga_reg);
8591}
8592
f817586c
DV		 8593void intel_modeset_init_hw(struct drm_device *dev)
8594{
0232e927
ED		 8595 /* We attempt to init the necessary power wells early in the initialization
8596 * time, so the subsystems that expect power to be enabled can work.
8597 */
8598 intel_init_power_wells(dev);
8599
a8f78b58
ED		 8600 intel_prepare_ddi(dev);
8601
f817586c
DV		 8602 intel_init_clock_gating(dev);
8603
79f5b2c7 8604 mutex_lock(&dev->struct_mutex);
8090c6b9 8605 intel_enable_gt_powersave(dev);
79f5b2c7 8606 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 8607}
8608
79e53945
JB		 8609void intel_modeset_init(struct drm_device *dev)
8610{
652c393a 8611 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 8612 int i, ret;
79e53945
JB		 8613
8614 drm_mode_config_init(dev);
8615
8616 dev->mode_config.min_width = 0;
8617 dev->mode_config.min_height = 0;
8618
019d96cb
DA		 8619 dev->mode_config.preferred_depth = 24;
8620 dev->mode_config.prefer_shadow = 1;
8621
e6ecefaa 8622 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 8623
b690e96c
JB		 8624 intel_init_quirks(dev);
8625
1fa61106
ED		 8626 intel_init_pm(dev);
8627
e70236a8
JB		 8628 intel_init_display(dev);
8629
a6c45cf0
CW		 8630 if (IS_GEN2(dev)) {
8631 dev->mode_config.max_width = 2048;
8632 dev->mode_config.max_height = 2048;
8633 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 8634 dev->mode_config.max_width = 4096;
8635 dev->mode_config.max_height = 4096;
79e53945 8636 } else {
a6c45cf0
CW		 8637 dev->mode_config.max_width = 8192;
8638 dev->mode_config.max_height = 8192;
79e53945 8639 }
dd2757f8 8640 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
79e53945 8641
28c97730 8642 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 8643 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 8644
a3524f1b 8645 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 8646 intel_crtc_init(dev, i);
00c2064b
JB		 8647 ret = intel_plane_init(dev, i);
8648 if (ret)
8649 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 8650 }
8651
79f689aa 8652 intel_cpu_pll_init(dev);
ee7b9f93
JB		 8653 intel_pch_pll_init(dev);
8654
9cce37f4
JB		 8655 /* Just disable it once at startup */
8656 i915_disable_vga(dev);
79e53945 8657 intel_setup_outputs(dev);
11be49eb
CW		 8658
8659 /* Just in case the BIOS is doing something questionable. */
8660 intel_disable_fbc(dev);
2c7111db
CW		 8661}
8662
24929352
DV		 8663static void
8664intel_connector_break_all_links(struct intel_connector *connector)
8665{
8666 connector->base.dpms = DRM_MODE_DPMS_OFF;
8667 connector->base.encoder = NULL;
8668 connector->encoder->connectors_active = false;
8669 connector->encoder->base.crtc = NULL;
8670}
8671
7fad798e
DV		 8672static void intel_enable_pipe_a(struct drm_device *dev)
8673{
8674 struct intel_connector *connector;
8675 struct drm_connector *crt = NULL;
8676 struct intel_load_detect_pipe load_detect_temp;
8677
8678 /* We can't just switch on the pipe A, we need to set things up with a
8679 * proper mode and output configuration. As a gross hack, enable pipe A
8680 * by enabling the load detect pipe once. */
8681 list_for_each_entry(connector,
8682 &dev->mode_config.connector_list,
8683 base.head) {
8684 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8685 crt = &connector->base;
8686 break;
8687 }
8688 }
8689
8690 if (!crt)
8691 return;
8692
8693 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8694 intel_release_load_detect_pipe(crt, &load_detect_temp);
8695
652c393a 8696
7fad798e
DV		 8697}
8698
fa555837
DV		 8699static bool
8700intel_check_plane_mapping(struct intel_crtc *crtc)
8701{
8702 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8703 u32 reg, val;
8704
8705 if (dev_priv->num_pipe == 1)
8706 return true;
8707
8708 reg = DSPCNTR(!crtc->plane);
8709 val = I915_READ(reg);
8710
8711 if ((val & DISPLAY_PLANE_ENABLE) &&
8712 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8713 return false;
8714
8715 return true;
8716}
8717
24929352
DV		 8718static void intel_sanitize_crtc(struct intel_crtc *crtc)
8719{
8720 struct drm_device *dev = crtc->base.dev;
8721 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 8722 u32 reg;
24929352 8723
24929352 8724 /* Clear any frame start delays used for debugging left by the BIOS */
702e7a56 8725 reg = PIPECONF(crtc->cpu_transcoder);
24929352
DV		 8726 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8727
8728 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 8729 * disable the crtc (and hence change the state) if it is wrong. Note
8730 * that gen4+ has a fixed plane -> pipe mapping. */
8731 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 8732 struct intel_connector *connector;
8733 bool plane;
8734
24929352
DV		 8735 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8736 crtc->base.base.id);
8737
8738 /* Pipe has the wrong plane attached and the plane is active.
8739 * Temporarily change the plane mapping and disable everything
8740 * ... */
8741 plane = crtc->plane;
8742 crtc->plane = !plane;
8743 dev_priv->display.crtc_disable(&crtc->base);
8744 crtc->plane = plane;
8745
8746 /* ... and break all links. */
8747 list_for_each_entry(connector, &dev->mode_config.connector_list,
8748 base.head) {
8749 if (connector->encoder->base.crtc != &crtc->base)
8750 continue;
8751
8752 intel_connector_break_all_links(connector);
8753 }
8754
8755 WARN_ON(crtc->active);
8756 crtc->base.enabled = false;
8757 }
24929352 8758
7fad798e
DV		 8759 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8760 crtc->pipe == PIPE_A && !crtc->active) {
8761 /* BIOS forgot to enable pipe A, this mostly happens after
8762 * resume. Force-enable the pipe to fix this, the update_dpms
8763 * call below we restore the pipe to the right state, but leave
8764 * the required bits on. */
8765 intel_enable_pipe_a(dev);
8766 }
8767
24929352
DV		 8768 /* Adjust the state of the output pipe according to whether we
8769 * have active connectors/encoders. */
8770 intel_crtc_update_dpms(&crtc->base);
8771
8772 if (crtc->active != crtc->base.enabled) {
8773 struct intel_encoder *encoder;
8774
8775 /* This can happen either due to bugs in the get_hw_state
8776 * functions or because the pipe is force-enabled due to the
8777 * pipe A quirk. */
8778 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8779 crtc->base.base.id,
8780 crtc->base.enabled ? "enabled" : "disabled",
8781 crtc->active ? "enabled" : "disabled");
8782
8783 crtc->base.enabled = crtc->active;
8784
8785 /* Because we only establish the connector -> encoder ->
8786 * crtc links if something is active, this means the
8787 * crtc is now deactivated. Break the links. connector
8788 * -> encoder links are only establish when things are
8789 * actually up, hence no need to break them. */
8790 WARN_ON(crtc->active);
8791
8792 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8793 WARN_ON(encoder->connectors_active);
8794 encoder->base.crtc = NULL;
8795 }
8796 }
8797}
8798
8799static void intel_sanitize_encoder(struct intel_encoder *encoder)
8800{
8801 struct intel_connector *connector;
8802 struct drm_device *dev = encoder->base.dev;
8803
8804 /* We need to check both for a crtc link (meaning that the
8805 * encoder is active and trying to read from a pipe) and the
8806 * pipe itself being active. */
8807 bool has_active_crtc = encoder->base.crtc &&
8808 to_intel_crtc(encoder->base.crtc)->active;
8809
8810 if (encoder->connectors_active && !has_active_crtc) {
8811 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8812 encoder->base.base.id,
8813 drm_get_encoder_name(&encoder->base));
8814
8815 /* Connector is active, but has no active pipe. This is
8816 * fallout from our resume register restoring. Disable
8817 * the encoder manually again. */
8818 if (encoder->base.crtc) {
8819 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8820 encoder->base.base.id,
8821 drm_get_encoder_name(&encoder->base));
8822 encoder->disable(encoder);
8823 }
8824
8825 /* Inconsistent output/port/pipe state happens presumably due to
8826 * a bug in one of the get_hw_state functions. Or someplace else
8827 * in our code, like the register restore mess on resume. Clamp
8828 * things to off as a safer default. */
8829 list_for_each_entry(connector,
8830 &dev->mode_config.connector_list,
8831 base.head) {
8832 if (connector->encoder != encoder)
8833 continue;
8834
8835 intel_connector_break_all_links(connector);
8836 }
8837 }
8838 /* Enabled encoders without active connectors will be fixed in
8839 * the crtc fixup. */
8840}
8841
8842/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8843 * and i915 state tracking structures. */
45e2b5f6
DV		 8844void intel_modeset_setup_hw_state(struct drm_device *dev,
8845 bool force_restore)
24929352
DV		 8846{
8847 struct drm_i915_private *dev_priv = dev->dev_private;
8848 enum pipe pipe;
8849 u32 tmp;
8850 struct intel_crtc *crtc;
8851 struct intel_encoder *encoder;
8852 struct intel_connector *connector;
8853
affa9354 8854 if (HAS_DDI(dev)) {
e28d54cb
PZ		 8855 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8856
8857 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8858 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8859 case TRANS_DDI_EDP_INPUT_A_ON:
8860 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8861 pipe = PIPE_A;
8862 break;
8863 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8864 pipe = PIPE_B;
8865 break;
8866 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8867 pipe = PIPE_C;
8868 break;
8869 }
8870
8871 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8872 crtc->cpu_transcoder = TRANSCODER_EDP;
8873
8874 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
8875 pipe_name(pipe));
8876 }
8877 }
8878
24929352
DV		 8879 for_each_pipe(pipe) {
8880 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8881
702e7a56 8882 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
24929352
DV		 8883 if (tmp & PIPECONF_ENABLE)
8884 crtc->active = true;
8885 else
8886 crtc->active = false;
8887
8888 crtc->base.enabled = crtc->active;
8889
8890 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
8891 crtc->base.base.id,
8892 crtc->active ? "enabled" : "disabled");
8893 }
8894
affa9354 8895 if (HAS_DDI(dev))
6441ab5f
PZ		 8896 intel_ddi_setup_hw_pll_state(dev);
8897
24929352
DV		 8898 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8899 base.head) {
8900 pipe = 0;
8901
8902 if (encoder->get_hw_state(encoder, &pipe)) {
8903 encoder->base.crtc =
8904 dev_priv->pipe_to_crtc_mapping[pipe];
8905 } else {
8906 encoder->base.crtc = NULL;
8907 }
8908
8909 encoder->connectors_active = false;
8910 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
8911 encoder->base.base.id,
8912 drm_get_encoder_name(&encoder->base),
8913 encoder->base.crtc ? "enabled" : "disabled",
8914 pipe);
8915 }
8916
8917 list_for_each_entry(connector, &dev->mode_config.connector_list,
8918 base.head) {
8919 if (connector->get_hw_state(connector)) {
8920 connector->base.dpms = DRM_MODE_DPMS_ON;
8921 connector->encoder->connectors_active = true;
8922 connector->base.encoder = &connector->encoder->base;
8923 } else {
8924 connector->base.dpms = DRM_MODE_DPMS_OFF;
8925 connector->base.encoder = NULL;
8926 }
8927 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
8928 connector->base.base.id,
8929 drm_get_connector_name(&connector->base),
8930 connector->base.encoder ? "enabled" : "disabled");
8931 }
8932
8933 /* HW state is read out, now we need to sanitize this mess. */
8934 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8935 base.head) {
8936 intel_sanitize_encoder(encoder);
8937 }
8938
8939 for_each_pipe(pipe) {
8940 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8941 intel_sanitize_crtc(crtc);
8942 }
9a935856 8943
45e2b5f6
DV		 8944 if (force_restore) {
8945 for_each_pipe(pipe) {
8946 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8947 intel_set_mode(&crtc->base, &crtc->base.mode,
8948 crtc->base.x, crtc->base.y, crtc->base.fb);
8949 }
8950 } else {
8951 intel_modeset_update_staged_output_state(dev);
8952 }
8af6cf88
DV		 8953
8954 intel_modeset_check_state(dev);
2e938892
DV		 8955
8956 drm_mode_config_reset(dev);
2c7111db
CW		 8957}
8958
8959void intel_modeset_gem_init(struct drm_device *dev)
8960{
1833b134 8961 intel_modeset_init_hw(dev);
02e792fb
DV		 8962
8963 intel_setup_overlay(dev);
24929352 8964
45e2b5f6 8965 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 8966}
8967
8968void intel_modeset_cleanup(struct drm_device *dev)
8969{
652c393a
JB		 8970 struct drm_i915_private *dev_priv = dev->dev_private;
8971 struct drm_crtc *crtc;
8972 struct intel_crtc *intel_crtc;
8973
f87ea761 8974 drm_kms_helper_poll_fini(dev);
652c393a
JB		 8975 mutex_lock(&dev->struct_mutex);
8976
723bfd70
JB		 8977 intel_unregister_dsm_handler();
8978
8979
652c393a
JB		 8980 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8981 /* Skip inactive CRTCs */
8982 if (!crtc->fb)
8983 continue;
8984
8985 intel_crtc = to_intel_crtc(crtc);
3dec0095 8986 intel_increase_pllclock(crtc);
652c393a
JB		 8987 }
8988
973d04f9 8989 intel_disable_fbc(dev);
e70236a8 8990
8090c6b9 8991 intel_disable_gt_powersave(dev);
0cdab21f 8992
930ebb46
DV		 8993 ironlake_teardown_rc6(dev);
8994
57f350b6
JB		 8995 if (IS_VALLEYVIEW(dev))
8996 vlv_init_dpio(dev);
8997
69341a5e
KH		 8998 mutex_unlock(&dev->struct_mutex);
8999
6c0d9350
DV		 9000 /* Disable the irq before mode object teardown, for the irq might
9001 * enqueue unpin/hotplug work. */
9002 drm_irq_uninstall(dev);
9003 cancel_work_sync(&dev_priv->hotplug_work);
c6a828d3 9004 cancel_work_sync(&dev_priv->rps.work);
6c0d9350 9005
1630fe75
CW		 9006 /* flush any delayed tasks or pending work */
9007 flush_scheduled_work();
9008
79e53945
JB		 9009 drm_mode_config_cleanup(dev);
9010}
9011
f1c79df3
ZW		 9012/*
9013 * Return which encoder is currently attached for connector.
9014 */
df0e9248 9015struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9016{
df0e9248
CW		 9017 return &intel_attached_encoder(connector)->base;
9018}
f1c79df3 9019
df0e9248
CW		 9020void intel_connector_attach_encoder(struct intel_connector *connector,
9021 struct intel_encoder *encoder)
9022{
9023 connector->encoder = encoder;
9024 drm_mode_connector_attach_encoder(&connector->base,
9025 &encoder->base);
79e53945 9026}
28d52043
DA		 9027
9028/*
9029 * set vga decode state - true == enable VGA decode
9030 */
9031int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9032{
9033 struct drm_i915_private *dev_priv = dev->dev_private;
9034 u16 gmch_ctrl;
9035
9036 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9037 if (state)
9038 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9039 else
9040 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9041 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9042 return 0;
9043}
c4a1d9e4
CW		 9044
9045#ifdef CONFIG_DEBUG_FS
9046#include <linux/seq_file.h>
9047
9048struct intel_display_error_state {
9049 struct intel_cursor_error_state {
9050 u32 control;
9051 u32 position;
9052 u32 base;
9053 u32 size;
52331309 9054 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9055
9056 struct intel_pipe_error_state {
9057 u32 conf;
9058 u32 source;
9059
9060 u32 htotal;
9061 u32 hblank;
9062 u32 hsync;
9063 u32 vtotal;
9064 u32 vblank;
9065 u32 vsync;
52331309 9066 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9067
9068 struct intel_plane_error_state {
9069 u32 control;
9070 u32 stride;
9071 u32 size;
9072 u32 pos;
9073 u32 addr;
9074 u32 surface;
9075 u32 tile_offset;
52331309 9076 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9077};
9078
9079struct intel_display_error_state *
9080intel_display_capture_error_state(struct drm_device *dev)
9081{
0206e353 9082 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9083 struct intel_display_error_state *error;
702e7a56 9084 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9085 int i;
9086
9087 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9088 if (error == NULL)
9089 return NULL;
9090
52331309 9091 for_each_pipe(i) {
702e7a56
PZ		 9092 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9093
c4a1d9e4
CW		 9094 error->cursor[i].control = I915_READ(CURCNTR(i));
9095 error->cursor[i].position = I915_READ(CURPOS(i));
9096 error->cursor[i].base = I915_READ(CURBASE(i));
9097
9098 error->plane[i].control = I915_READ(DSPCNTR(i));
9099 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9100 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 9101 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 9102 error->plane[i].addr = I915_READ(DSPADDR(i));
9103 if (INTEL_INFO(dev)->gen >= 4) {
9104 error->plane[i].surface = I915_READ(DSPSURF(i));
9105 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9106 }
9107
702e7a56 9108 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9109 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9110 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9111 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9112 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9113 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9114 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9115 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9116 }
9117
9118 return error;
9119}
9120
9121void
9122intel_display_print_error_state(struct seq_file *m,
9123 struct drm_device *dev,
9124 struct intel_display_error_state *error)
9125{
52331309 9126 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 9127 int i;
9128
52331309
DL		 9129 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9130 for_each_pipe(i) {
c4a1d9e4
CW		 9131 seq_printf(m, "Pipe [%d]:\n", i);
9132 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9133 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9134 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9135 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9136 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9137 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9138 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9139 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9140
9141 seq_printf(m, "Plane [%d]:\n", i);
9142 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9143 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9144 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9145 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9146 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9147 if (INTEL_INFO(dev)->gen >= 4) {
9148 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9149 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9150 }
9151
9152 seq_printf(m, "Cursor [%d]:\n", i);
9153 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9154 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9155 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9156 }
9157}
9158#endif
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