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drm/i915: Use adjusted_mode when checking conditions for PSR
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
f1f644dc
JB		 48static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
49 struct intel_crtc_config *pipe_config);
18442d08
VS		 50static void ironlake_pch_clock_get(struct intel_crtc *crtc,
51 struct intel_crtc_config *pipe_config);
f1f644dc 52
e7457a9a
DL		 53static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
54 int x, int y, struct drm_framebuffer *old_fb);
55
56
79e53945 57typedef struct {
0206e353 58 int min, max;
79e53945
JB		 59} intel_range_t;
60
61typedef struct {
0206e353
AJ		 62 int dot_limit;
63 int p2_slow, p2_fast;
79e53945
JB		 64} intel_p2_t;
65
d4906093
ML		 66typedef struct intel_limit intel_limit_t;
67struct intel_limit {
0206e353
AJ		 68 intel_range_t dot, vco, n, m, m1, m2, p, p1;
69 intel_p2_t p2;
d4906093 70};
79e53945 71
d2acd215
DV		 72int
73intel_pch_rawclk(struct drm_device *dev)
74{
75 struct drm_i915_private *dev_priv = dev->dev_private;
76
77 WARN_ON(!HAS_PCH_SPLIT(dev));
78
79 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
80}
81
021357ac
CW		 82static inline u32 /* units of 100MHz */
83intel_fdi_link_freq(struct drm_device *dev)
84{
8b99e68c
CW		 85 if (IS_GEN5(dev)) {
86 struct drm_i915_private *dev_priv = dev->dev_private;
87 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
88 } else
89 return 27;
021357ac
CW		 90}
91
5d536e28 92static const intel_limit_t intel_limits_i8xx_dac = {
0206e353
AJ		 93 .dot = { .min = 25000, .max = 350000 },
94 .vco = { .min = 930000, .max = 1400000 },
95 .n = { .min = 3, .max = 16 },
96 .m = { .min = 96, .max = 140 },
97 .m1 = { .min = 18, .max = 26 },
98 .m2 = { .min = 6, .max = 16 },
99 .p = { .min = 4, .max = 128 },
100 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 101 .p2 = { .dot_limit = 165000,
102 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 103};
104
5d536e28
DV		 105static const intel_limit_t intel_limits_i8xx_dvo = {
106 .dot = { .min = 25000, .max = 350000 },
107 .vco = { .min = 930000, .max = 1400000 },
108 .n = { .min = 3, .max = 16 },
109 .m = { .min = 96, .max = 140 },
110 .m1 = { .min = 18, .max = 26 },
111 .m2 = { .min = 6, .max = 16 },
112 .p = { .min = 4, .max = 128 },
113 .p1 = { .min = 2, .max = 33 },
114 .p2 = { .dot_limit = 165000,
115 .p2_slow = 4, .p2_fast = 4 },
116};
117
e4b36699 118static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 119 .dot = { .min = 25000, .max = 350000 },
120 .vco = { .min = 930000, .max = 1400000 },
121 .n = { .min = 3, .max = 16 },
122 .m = { .min = 96, .max = 140 },
123 .m1 = { .min = 18, .max = 26 },
124 .m2 = { .min = 6, .max = 16 },
125 .p = { .min = 4, .max = 128 },
126 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 127 .p2 = { .dot_limit = 165000,
128 .p2_slow = 14, .p2_fast = 7 },
e4b36699 129};
273e27ca 130
e4b36699 131static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 132 .dot = { .min = 20000, .max = 400000 },
133 .vco = { .min = 1400000, .max = 2800000 },
134 .n = { .min = 1, .max = 6 },
135 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 136 .m1 = { .min = 8, .max = 18 },
137 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 138 .p = { .min = 5, .max = 80 },
139 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 140 .p2 = { .dot_limit = 200000,
141 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 142};
143
144static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 145 .dot = { .min = 20000, .max = 400000 },
146 .vco = { .min = 1400000, .max = 2800000 },
147 .n = { .min = 1, .max = 6 },
148 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 149 .m1 = { .min = 8, .max = 18 },
150 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 151 .p = { .min = 7, .max = 98 },
152 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 153 .p2 = { .dot_limit = 112000,
154 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 155};
156
273e27ca 157
e4b36699 158static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 159 .dot = { .min = 25000, .max = 270000 },
160 .vco = { .min = 1750000, .max = 3500000},
161 .n = { .min = 1, .max = 4 },
162 .m = { .min = 104, .max = 138 },
163 .m1 = { .min = 17, .max = 23 },
164 .m2 = { .min = 5, .max = 11 },
165 .p = { .min = 10, .max = 30 },
166 .p1 = { .min = 1, .max = 3},
167 .p2 = { .dot_limit = 270000,
168 .p2_slow = 10,
169 .p2_fast = 10
044c7c41 170 },
e4b36699
KP		 171};
172
173static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 174 .dot = { .min = 22000, .max = 400000 },
175 .vco = { .min = 1750000, .max = 3500000},
176 .n = { .min = 1, .max = 4 },
177 .m = { .min = 104, .max = 138 },
178 .m1 = { .min = 16, .max = 23 },
179 .m2 = { .min = 5, .max = 11 },
180 .p = { .min = 5, .max = 80 },
181 .p1 = { .min = 1, .max = 8},
182 .p2 = { .dot_limit = 165000,
183 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 184};
185
186static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 187 .dot = { .min = 20000, .max = 115000 },
188 .vco = { .min = 1750000, .max = 3500000 },
189 .n = { .min = 1, .max = 3 },
190 .m = { .min = 104, .max = 138 },
191 .m1 = { .min = 17, .max = 23 },
192 .m2 = { .min = 5, .max = 11 },
193 .p = { .min = 28, .max = 112 },
194 .p1 = { .min = 2, .max = 8 },
195 .p2 = { .dot_limit = 0,
196 .p2_slow = 14, .p2_fast = 14
044c7c41 197 },
e4b36699
KP		 198};
199
200static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 201 .dot = { .min = 80000, .max = 224000 },
202 .vco = { .min = 1750000, .max = 3500000 },
203 .n = { .min = 1, .max = 3 },
204 .m = { .min = 104, .max = 138 },
205 .m1 = { .min = 17, .max = 23 },
206 .m2 = { .min = 5, .max = 11 },
207 .p = { .min = 14, .max = 42 },
208 .p1 = { .min = 2, .max = 6 },
209 .p2 = { .dot_limit = 0,
210 .p2_slow = 7, .p2_fast = 7
044c7c41 211 },
e4b36699
KP		 212};
213
f2b115e6 214static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 215 .dot = { .min = 20000, .max = 400000},
216 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 217 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 218 .n = { .min = 3, .max = 6 },
219 .m = { .min = 2, .max = 256 },
273e27ca 220 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 221 .m1 = { .min = 0, .max = 0 },
222 .m2 = { .min = 0, .max = 254 },
223 .p = { .min = 5, .max = 80 },
224 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 225 .p2 = { .dot_limit = 200000,
226 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 227};
228
f2b115e6 229static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 230 .dot = { .min = 20000, .max = 400000 },
231 .vco = { .min = 1700000, .max = 3500000 },
232 .n = { .min = 3, .max = 6 },
233 .m = { .min = 2, .max = 256 },
234 .m1 = { .min = 0, .max = 0 },
235 .m2 = { .min = 0, .max = 254 },
236 .p = { .min = 7, .max = 112 },
237 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 238 .p2 = { .dot_limit = 112000,
239 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 240};
241
273e27ca
EA		 242/* Ironlake / Sandybridge
243 *
244 * We calculate clock using (register_value + 2) for N/M1/M2, so here
245 * the range value for them is (actual_value - 2).
246 */
b91ad0ec 247static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 248 .dot = { .min = 25000, .max = 350000 },
249 .vco = { .min = 1760000, .max = 3510000 },
250 .n = { .min = 1, .max = 5 },
251 .m = { .min = 79, .max = 127 },
252 .m1 = { .min = 12, .max = 22 },
253 .m2 = { .min = 5, .max = 9 },
254 .p = { .min = 5, .max = 80 },
255 .p1 = { .min = 1, .max = 8 },
256 .p2 = { .dot_limit = 225000,
257 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 258};
259
b91ad0ec 260static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 261 .dot = { .min = 25000, .max = 350000 },
262 .vco = { .min = 1760000, .max = 3510000 },
263 .n = { .min = 1, .max = 3 },
264 .m = { .min = 79, .max = 118 },
265 .m1 = { .min = 12, .max = 22 },
266 .m2 = { .min = 5, .max = 9 },
267 .p = { .min = 28, .max = 112 },
268 .p1 = { .min = 2, .max = 8 },
269 .p2 = { .dot_limit = 225000,
270 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 271};
272
273static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 274 .dot = { .min = 25000, .max = 350000 },
275 .vco = { .min = 1760000, .max = 3510000 },
276 .n = { .min = 1, .max = 3 },
277 .m = { .min = 79, .max = 127 },
278 .m1 = { .min = 12, .max = 22 },
279 .m2 = { .min = 5, .max = 9 },
280 .p = { .min = 14, .max = 56 },
281 .p1 = { .min = 2, .max = 8 },
282 .p2 = { .dot_limit = 225000,
283 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 284};
285
273e27ca 286/* LVDS 100mhz refclk limits. */
b91ad0ec 287static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 288 .dot = { .min = 25000, .max = 350000 },
289 .vco = { .min = 1760000, .max = 3510000 },
290 .n = { .min = 1, .max = 2 },
291 .m = { .min = 79, .max = 126 },
292 .m1 = { .min = 12, .max = 22 },
293 .m2 = { .min = 5, .max = 9 },
294 .p = { .min = 28, .max = 112 },
0206e353 295 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 296 .p2 = { .dot_limit = 225000,
297 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 298};
299
300static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 301 .dot = { .min = 25000, .max = 350000 },
302 .vco = { .min = 1760000, .max = 3510000 },
303 .n = { .min = 1, .max = 3 },
304 .m = { .min = 79, .max = 126 },
305 .m1 = { .min = 12, .max = 22 },
306 .m2 = { .min = 5, .max = 9 },
307 .p = { .min = 14, .max = 42 },
0206e353 308 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 309 .p2 = { .dot_limit = 225000,
310 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 311};
312
a0c4da24
JB		 313static const intel_limit_t intel_limits_vlv_dac = {
314 .dot = { .min = 25000, .max = 270000 },
315 .vco = { .min = 4000000, .max = 6000000 },
316 .n = { .min = 1, .max = 7 },
317 .m = { .min = 22, .max = 450 }, /* guess */
318 .m1 = { .min = 2, .max = 3 },
319 .m2 = { .min = 11, .max = 156 },
320 .p = { .min = 10, .max = 30 },
75e53986 321 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 322 .p2 = { .dot_limit = 270000,
323 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 324};
325
326static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 327 .dot = { .min = 25000, .max = 270000 },
328 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 329 .n = { .min = 1, .max = 7 },
330 .m = { .min = 60, .max = 300 }, /* guess */
331 .m1 = { .min = 2, .max = 3 },
332 .m2 = { .min = 11, .max = 156 },
333 .p = { .min = 10, .max = 30 },
334 .p1 = { .min = 2, .max = 3 },
335 .p2 = { .dot_limit = 270000,
336 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 337};
338
1b894b59
CW		 339static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
340 int refclk)
2c07245f 341{
b91ad0ec 342 struct drm_device *dev = crtc->dev;
2c07245f 343 const intel_limit_t *limit;
b91ad0ec
ZW		 344
345 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 346 if (intel_is_dual_link_lvds(dev)) {
1b894b59 347 if (refclk == 100000)
b91ad0ec
ZW		 348 limit = &intel_limits_ironlake_dual_lvds_100m;
349 else
350 limit = &intel_limits_ironlake_dual_lvds;
351 } else {
1b894b59 352 if (refclk == 100000)
b91ad0ec
ZW		 353 limit = &intel_limits_ironlake_single_lvds_100m;
354 else
355 limit = &intel_limits_ironlake_single_lvds;
356 }
c6bb3538 357 } else
b91ad0ec 358 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 359
360 return limit;
361}
362
044c7c41
ML		 363static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
364{
365 struct drm_device *dev = crtc->dev;
044c7c41
ML		 366 const intel_limit_t *limit;
367
368 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 369 if (intel_is_dual_link_lvds(dev))
e4b36699 370 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 371 else
e4b36699 372 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 373 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
374 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 375 limit = &intel_limits_g4x_hdmi;
044c7c41 376 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 377 limit = &intel_limits_g4x_sdvo;
044c7c41 378 } else /* The option is for other outputs */
e4b36699 379 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 380
381 return limit;
382}
383
1b894b59 384static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 385{
386 struct drm_device *dev = crtc->dev;
387 const intel_limit_t *limit;
388
bad720ff 389 if (HAS_PCH_SPLIT(dev))
1b894b59 390 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 391 else if (IS_G4X(dev)) {
044c7c41 392 limit = intel_g4x_limit(crtc);
f2b115e6 393 } else if (IS_PINEVIEW(dev)) {
2177832f 394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 395 limit = &intel_limits_pineview_lvds;
2177832f 396 else
f2b115e6 397 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 398 } else if (IS_VALLEYVIEW(dev)) {
399 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
400 limit = &intel_limits_vlv_dac;
a0c4da24 401 else
65ce4bf5 402 limit = &intel_limits_vlv_hdmi;
a6c45cf0
CW		 403 } else if (!IS_GEN2(dev)) {
404 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
405 limit = &intel_limits_i9xx_lvds;
406 else
407 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 408 } else {
409 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 410 limit = &intel_limits_i8xx_lvds;
5d536e28 411 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
e4b36699 412 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 413 else
414 limit = &intel_limits_i8xx_dac;
79e53945
JB		 415 }
416 return limit;
417}
418
f2b115e6
AJ		 419/* m1 is reserved as 0 in Pineview, n is a ring counter */
420static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 421{
2177832f
SL		 422 clock->m = clock->m2 + 2;
423 clock->p = clock->p1 * clock->p2;
424 clock->vco = refclk * clock->m / clock->n;
425 clock->dot = clock->vco / clock->p;
426}
427
7429e9d4
DV		 428static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
429{
430 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
431}
432
ac58c3f0 433static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 434{
7429e9d4 435 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 436 clock->p = clock->p1 * clock->p2;
437 clock->vco = refclk * clock->m / (clock->n + 2);
438 clock->dot = clock->vco / clock->p;
439}
440
79e53945
JB		 441/**
442 * Returns whether any output on the specified pipe is of the specified type
443 */
4ef69c7a 444bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 445{
4ef69c7a 446 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 447 struct intel_encoder *encoder;
448
6c2b7c12
DV		 449 for_each_encoder_on_crtc(dev, crtc, encoder)
450 if (encoder->type == type)
4ef69c7a
CW		 451 return true;
452
453 return false;
79e53945
JB		 454}
455
7c04d1d9 456#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 457/**
458 * Returns whether the given set of divisors are valid for a given refclk with
459 * the given connectors.
460 */
461
1b894b59
CW		 462static bool intel_PLL_is_valid(struct drm_device *dev,
463 const intel_limit_t *limit,
464 const intel_clock_t *clock)
79e53945 465{
79e53945 466 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 467 INTELPllInvalid("p1 out of range\n");
79e53945 468 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 469 INTELPllInvalid("p out of range\n");
79e53945 470 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 471 INTELPllInvalid("m2 out of range\n");
79e53945 472 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 473 INTELPllInvalid("m1 out of range\n");
f2b115e6 474 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 475 INTELPllInvalid("m1 <= m2\n");
79e53945 476 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 477 INTELPllInvalid("m out of range\n");
79e53945 478 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 479 INTELPllInvalid("n out of range\n");
79e53945 480 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 481 INTELPllInvalid("vco out of range\n");
79e53945
JB		 482 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
483 * connector, etc., rather than just a single range.
484 */
485 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 486 INTELPllInvalid("dot out of range\n");
79e53945
JB		 487
488 return true;
489}
490
d4906093 491static bool
ee9300bb 492i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 493 int target, int refclk, intel_clock_t *match_clock,
494 intel_clock_t *best_clock)
79e53945
JB		 495{
496 struct drm_device *dev = crtc->dev;
79e53945 497 intel_clock_t clock;
79e53945
JB		 498 int err = target;
499
a210b028 500 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 501 /*
a210b028
DV		 502 * For LVDS just rely on its current settings for dual-channel.
503 * We haven't figured out how to reliably set up different
504 * single/dual channel state, if we even can.
79e53945 505 */
1974cad0 506 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 507 clock.p2 = limit->p2.p2_fast;
508 else
509 clock.p2 = limit->p2.p2_slow;
510 } else {
511 if (target < limit->p2.dot_limit)
512 clock.p2 = limit->p2.p2_slow;
513 else
514 clock.p2 = limit->p2.p2_fast;
515 }
516
0206e353 517 memset(best_clock, 0, sizeof(*best_clock));
79e53945 518
42158660
ZY		 519 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
520 clock.m1++) {
521 for (clock.m2 = limit->m2.min;
522 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 523 if (clock.m2 >= clock.m1)
42158660
ZY		 524 break;
525 for (clock.n = limit->n.min;
526 clock.n <= limit->n.max; clock.n++) {
527 for (clock.p1 = limit->p1.min;
528 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 529 int this_err;
530
ac58c3f0
DV		 531 i9xx_clock(refclk, &clock);
532 if (!intel_PLL_is_valid(dev, limit,
533 &clock))
534 continue;
535 if (match_clock &&
536 clock.p != match_clock->p)
537 continue;
538
539 this_err = abs(clock.dot - target);
540 if (this_err < err) {
541 *best_clock = clock;
542 err = this_err;
543 }
544 }
545 }
546 }
547 }
548
549 return (err != target);
550}
551
552static bool
ee9300bb
DV		 553pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
554 int target, int refclk, intel_clock_t *match_clock,
555 intel_clock_t *best_clock)
79e53945
JB		 556{
557 struct drm_device *dev = crtc->dev;
79e53945 558 intel_clock_t clock;
79e53945
JB		 559 int err = target;
560
a210b028 561 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 562 /*
a210b028
DV		 563 * For LVDS just rely on its current settings for dual-channel.
564 * We haven't figured out how to reliably set up different
565 * single/dual channel state, if we even can.
79e53945 566 */
1974cad0 567 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 568 clock.p2 = limit->p2.p2_fast;
569 else
570 clock.p2 = limit->p2.p2_slow;
571 } else {
572 if (target < limit->p2.dot_limit)
573 clock.p2 = limit->p2.p2_slow;
574 else
575 clock.p2 = limit->p2.p2_fast;
576 }
577
0206e353 578 memset(best_clock, 0, sizeof(*best_clock));
79e53945 579
42158660
ZY		 580 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
581 clock.m1++) {
582 for (clock.m2 = limit->m2.min;
583 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 584 for (clock.n = limit->n.min;
585 clock.n <= limit->n.max; clock.n++) {
586 for (clock.p1 = limit->p1.min;
587 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 588 int this_err;
589
ac58c3f0 590 pineview_clock(refclk, &clock);
1b894b59
CW		 591 if (!intel_PLL_is_valid(dev, limit,
592 &clock))
79e53945 593 continue;
cec2f356
SP		 594 if (match_clock &&
595 clock.p != match_clock->p)
596 continue;
79e53945
JB		 597
598 this_err = abs(clock.dot - target);
599 if (this_err < err) {
600 *best_clock = clock;
601 err = this_err;
602 }
603 }
604 }
605 }
606 }
607
608 return (err != target);
609}
610
d4906093 611static bool
ee9300bb
DV		 612g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
613 int target, int refclk, intel_clock_t *match_clock,
614 intel_clock_t *best_clock)
d4906093
ML		 615{
616 struct drm_device *dev = crtc->dev;
d4906093
ML		 617 intel_clock_t clock;
618 int max_n;
619 bool found;
6ba770dc
AJ		 620 /* approximately equals target * 0.00585 */
621 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 622 found = false;
623
624 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 625 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 626 clock.p2 = limit->p2.p2_fast;
627 else
628 clock.p2 = limit->p2.p2_slow;
629 } else {
630 if (target < limit->p2.dot_limit)
631 clock.p2 = limit->p2.p2_slow;
632 else
633 clock.p2 = limit->p2.p2_fast;
634 }
635
636 memset(best_clock, 0, sizeof(*best_clock));
637 max_n = limit->n.max;
f77f13e2 638 /* based on hardware requirement, prefer smaller n to precision */
d4906093 639 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 640 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 641 for (clock.m1 = limit->m1.max;
642 clock.m1 >= limit->m1.min; clock.m1--) {
643 for (clock.m2 = limit->m2.max;
644 clock.m2 >= limit->m2.min; clock.m2--) {
645 for (clock.p1 = limit->p1.max;
646 clock.p1 >= limit->p1.min; clock.p1--) {
647 int this_err;
648
ac58c3f0 649 i9xx_clock(refclk, &clock);
1b894b59
CW		 650 if (!intel_PLL_is_valid(dev, limit,
651 &clock))
d4906093 652 continue;
1b894b59
CW		 653
654 this_err = abs(clock.dot - target);
d4906093
ML		 655 if (this_err < err_most) {
656 *best_clock = clock;
657 err_most = this_err;
658 max_n = clock.n;
659 found = true;
660 }
661 }
662 }
663 }
664 }
2c07245f
ZW		 665 return found;
666}
667
a0c4da24 668static bool
ee9300bb
DV		 669vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
670 int target, int refclk, intel_clock_t *match_clock,
671 intel_clock_t *best_clock)
a0c4da24
JB		 672{
673 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
674 u32 m, n, fastclk;
f3f08572 675 u32 updrate, minupdate, p;
a0c4da24
JB		 676 unsigned long bestppm, ppm, absppm;
677 int dotclk, flag;
678
af447bd3 679 flag = 0;
a0c4da24
JB		 680 dotclk = target * 1000;
681 bestppm = 1000000;
682 ppm = absppm = 0;
683 fastclk = dotclk / (2*100);
684 updrate = 0;
685 minupdate = 19200;
a0c4da24
JB		 686 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
687 bestm1 = bestm2 = bestp1 = bestp2 = 0;
688
689 /* based on hardware requirement, prefer smaller n to precision */
690 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
691 updrate = refclk / n;
692 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
693 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
694 if (p2 > 10)
695 p2 = p2 - 1;
696 p = p1 * p2;
697 /* based on hardware requirement, prefer bigger m1,m2 values */
698 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
699 m2 = (((2*(fastclk * p * n / m1 )) +
700 refclk) / (2*refclk));
701 m = m1 * m2;
702 vco = updrate * m;
703 if (vco >= limit->vco.min && vco < limit->vco.max) {
704 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
705 absppm = (ppm > 0) ? ppm : (-ppm);
706 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
707 bestppm = 0;
708 flag = 1;
709 }
710 if (absppm < bestppm - 10) {
711 bestppm = absppm;
712 flag = 1;
713 }
714 if (flag) {
715 bestn = n;
716 bestm1 = m1;
717 bestm2 = m2;
718 bestp1 = p1;
719 bestp2 = p2;
720 flag = 0;
721 }
722 }
723 }
724 }
725 }
726 }
727 best_clock->n = bestn;
728 best_clock->m1 = bestm1;
729 best_clock->m2 = bestm2;
730 best_clock->p1 = bestp1;
731 best_clock->p2 = bestp2;
732
733 return true;
734}
a4fc5ed6 735
a5c961d1
PZ		 736enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
737 enum pipe pipe)
738{
739 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
740 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
741
3b117c8f 742 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 743}
744
a928d536
PZ		 745static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
746{
747 struct drm_i915_private *dev_priv = dev->dev_private;
748 u32 frame, frame_reg = PIPEFRAME(pipe);
749
750 frame = I915_READ(frame_reg);
751
752 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
753 DRM_DEBUG_KMS("vblank wait timed out\n");
754}
755
9d0498a2
JB		 756/**
757 * intel_wait_for_vblank - wait for vblank on a given pipe
758 * @dev: drm device
759 * @pipe: pipe to wait for
760 *
761 * Wait for vblank to occur on a given pipe. Needed for various bits of
762 * mode setting code.
763 */
764void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 765{
9d0498a2 766 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 767 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 768
a928d536
PZ		 769 if (INTEL_INFO(dev)->gen >= 5) {
770 ironlake_wait_for_vblank(dev, pipe);
771 return;
772 }
773
300387c0
CW		 774 /* Clear existing vblank status. Note this will clear any other
775 * sticky status fields as well.
776 *
777 * This races with i915_driver_irq_handler() with the result
778 * that either function could miss a vblank event. Here it is not
779 * fatal, as we will either wait upon the next vblank interrupt or
780 * timeout. Generally speaking intel_wait_for_vblank() is only
781 * called during modeset at which time the GPU should be idle and
782 * should *not* be performing page flips and thus not waiting on
783 * vblanks...
784 * Currently, the result of us stealing a vblank from the irq
785 * handler is that a single frame will be skipped during swapbuffers.
786 */
787 I915_WRITE(pipestat_reg,
788 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
789
9d0498a2 790 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 791 if (wait_for(I915_READ(pipestat_reg) &
792 PIPE_VBLANK_INTERRUPT_STATUS,
793 50))
9d0498a2
JB		 794 DRM_DEBUG_KMS("vblank wait timed out\n");
795}
796
ab7ad7f6
KP		 797/*
798 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 799 * @dev: drm device
800 * @pipe: pipe to wait for
801 *
802 * After disabling a pipe, we can't wait for vblank in the usual way,
803 * spinning on the vblank interrupt status bit, since we won't actually
804 * see an interrupt when the pipe is disabled.
805 *
ab7ad7f6
KP		 806 * On Gen4 and above:
807 * wait for the pipe register state bit to turn off
808 *
809 * Otherwise:
810 * wait for the display line value to settle (it usually
811 * ends up stopping at the start of the next frame).
58e10eb9 812 *
9d0498a2 813 */
58e10eb9 814void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 815{
816 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 817 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
818 pipe);
ab7ad7f6
KP		 819
820 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 821 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 822
823 /* Wait for the Pipe State to go off */
58e10eb9
CW		 824 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
825 100))
284637d9 826 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 827 } else {
837ba00f 828 u32 last_line, line_mask;
58e10eb9 829 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 830 unsigned long timeout = jiffies + msecs_to_jiffies(100);
831
837ba00f
PZ		 832 if (IS_GEN2(dev))
833 line_mask = DSL_LINEMASK_GEN2;
834 else
835 line_mask = DSL_LINEMASK_GEN3;
836
ab7ad7f6
KP		 837 /* Wait for the display line to settle */
838 do {
837ba00f 839 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 840 mdelay(5);
837ba00f 841 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 842 time_after(timeout, jiffies));
843 if (time_after(jiffies, timeout))
284637d9 844 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 845 }
79e53945
JB		 846}
847
b0ea7d37
DL		 848/*
849 * ibx_digital_port_connected - is the specified port connected?
850 * @dev_priv: i915 private structure
851 * @port: the port to test
852 *
853 * Returns true if @port is connected, false otherwise.
854 */
855bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
856 struct intel_digital_port *port)
857{
858 u32 bit;
859
c36346e3
DL		 860 if (HAS_PCH_IBX(dev_priv->dev)) {
861 switch(port->port) {
862 case PORT_B:
863 bit = SDE_PORTB_HOTPLUG;
864 break;
865 case PORT_C:
866 bit = SDE_PORTC_HOTPLUG;
867 break;
868 case PORT_D:
869 bit = SDE_PORTD_HOTPLUG;
870 break;
871 default:
872 return true;
873 }
874 } else {
875 switch(port->port) {
876 case PORT_B:
877 bit = SDE_PORTB_HOTPLUG_CPT;
878 break;
879 case PORT_C:
880 bit = SDE_PORTC_HOTPLUG_CPT;
881 break;
882 case PORT_D:
883 bit = SDE_PORTD_HOTPLUG_CPT;
884 break;
885 default:
886 return true;
887 }
b0ea7d37
DL		 888 }
889
890 return I915_READ(SDEISR) & bit;
891}
892
b24e7179
JB		 893static const char *state_string(bool enabled)
894{
895 return enabled ? "on" : "off";
896}
897
898/* Only for pre-ILK configs */
55607e8a
DV		 899void assert_pll(struct drm_i915_private *dev_priv,
900 enum pipe pipe, bool state)
b24e7179
JB		 901{
902 int reg;
903 u32 val;
904 bool cur_state;
905
906 reg = DPLL(pipe);
907 val = I915_READ(reg);
908 cur_state = !!(val & DPLL_VCO_ENABLE);
909 WARN(cur_state != state,
910 "PLL state assertion failure (expected %s, current %s)\n",
911 state_string(state), state_string(cur_state));
912}
b24e7179 913
23538ef1
JN		 914/* XXX: the dsi pll is shared between MIPI DSI ports */
915static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
916{
917 u32 val;
918 bool cur_state;
919
920 mutex_lock(&dev_priv->dpio_lock);
921 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
922 mutex_unlock(&dev_priv->dpio_lock);
923
924 cur_state = val & DSI_PLL_VCO_EN;
925 WARN(cur_state != state,
926 "DSI PLL state assertion failure (expected %s, current %s)\n",
927 state_string(state), state_string(cur_state));
928}
929#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
930#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
931
55607e8a 932struct intel_shared_dpll *
e2b78267
DV		 933intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
934{
935 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
936
a43f6e0f 937 if (crtc->config.shared_dpll < 0)
e2b78267
DV		 938 return NULL;
939
a43f6e0f 940 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
e2b78267
DV		 941}
942
040484af 943/* For ILK+ */
55607e8a
DV		 944void assert_shared_dpll(struct drm_i915_private *dev_priv,
945 struct intel_shared_dpll *pll,
946 bool state)
040484af 947{
040484af 948 bool cur_state;
5358901f 949 struct intel_dpll_hw_state hw_state;
040484af 950
9d82aa17
ED		 951 if (HAS_PCH_LPT(dev_priv->dev)) {
952 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
953 return;
954 }
955
92b27b08 956 if (WARN (!pll,
46edb027 957 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 958 return;
ee7b9f93 959
5358901f 960 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
92b27b08 961 WARN(cur_state != state,
5358901f
DV		 962 "%s assertion failure (expected %s, current %s)\n",
963 pll->name, state_string(state), state_string(cur_state));
040484af 964}
040484af
JB		 965
966static void assert_fdi_tx(struct drm_i915_private *dev_priv,
967 enum pipe pipe, bool state)
968{
969 int reg;
970 u32 val;
971 bool cur_state;
ad80a810
PZ		 972 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
973 pipe);
040484af 974
affa9354
PZ		 975 if (HAS_DDI(dev_priv->dev)) {
976 /* DDI does not have a specific FDI_TX register */
ad80a810 977 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 978 val = I915_READ(reg);
ad80a810 979 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 980 } else {
981 reg = FDI_TX_CTL(pipe);
982 val = I915_READ(reg);
983 cur_state = !!(val & FDI_TX_ENABLE);
984 }
040484af
JB		 985 WARN(cur_state != state,
986 "FDI TX state assertion failure (expected %s, current %s)\n",
987 state_string(state), state_string(cur_state));
988}
989#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
990#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
991
992static void assert_fdi_rx(struct drm_i915_private *dev_priv,
993 enum pipe pipe, bool state)
994{
995 int reg;
996 u32 val;
997 bool cur_state;
998
d63fa0dc
PZ		 999 reg = FDI_RX_CTL(pipe);
1000 val = I915_READ(reg);
1001 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1002 WARN(cur_state != state,
1003 "FDI RX state assertion failure (expected %s, current %s)\n",
1004 state_string(state), state_string(cur_state));
1005}
1006#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1007#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1008
1009static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1010 enum pipe pipe)
1011{
1012 int reg;
1013 u32 val;
1014
1015 /* ILK FDI PLL is always enabled */
1016 if (dev_priv->info->gen == 5)
1017 return;
1018
bf507ef7 1019 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1020 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1021 return;
1022
040484af
JB		 1023 reg = FDI_TX_CTL(pipe);
1024 val = I915_READ(reg);
1025 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1026}
1027
55607e8a
DV		 1028void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1029 enum pipe pipe, bool state)
040484af
JB		 1030{
1031 int reg;
1032 u32 val;
55607e8a 1033 bool cur_state;
040484af
JB		 1034
1035 reg = FDI_RX_CTL(pipe);
1036 val = I915_READ(reg);
55607e8a
DV		 1037 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1038 WARN(cur_state != state,
1039 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1040 state_string(state), state_string(cur_state));
040484af
JB		 1041}
1042
ea0760cf
JB		 1043static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1044 enum pipe pipe)
1045{
1046 int pp_reg, lvds_reg;
1047 u32 val;
1048 enum pipe panel_pipe = PIPE_A;
0de3b485 1049 bool locked = true;
ea0760cf
JB		 1050
1051 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1052 pp_reg = PCH_PP_CONTROL;
1053 lvds_reg = PCH_LVDS;
1054 } else {
1055 pp_reg = PP_CONTROL;
1056 lvds_reg = LVDS;
1057 }
1058
1059 val = I915_READ(pp_reg);
1060 if (!(val & PANEL_POWER_ON) ||
1061 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1062 locked = false;
1063
1064 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1065 panel_pipe = PIPE_B;
1066
1067 WARN(panel_pipe == pipe && locked,
1068 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1069 pipe_name(pipe));
ea0760cf
JB		 1070}
1071
93ce0ba6
JN		 1072static void assert_cursor(struct drm_i915_private *dev_priv,
1073 enum pipe pipe, bool state)
1074{
1075 struct drm_device *dev = dev_priv->dev;
1076 bool cur_state;
1077
1078 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1079 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1080 else if (IS_845G(dev) || IS_I865G(dev))
1081 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1082 else
1083 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1084
1085 WARN(cur_state != state,
1086 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1087 pipe_name(pipe), state_string(state), state_string(cur_state));
1088}
1089#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1090#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1091
b840d907
JB		 1092void assert_pipe(struct drm_i915_private *dev_priv,
1093 enum pipe pipe, bool state)
b24e7179
JB		 1094{
1095 int reg;
1096 u32 val;
63d7bbe9 1097 bool cur_state;
702e7a56
PZ		 1098 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1099 pipe);
b24e7179 1100
8e636784
DV		 1101 /* if we need the pipe A quirk it must be always on */
1102 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1103 state = true;
1104
b97186f0
PZ		 1105 if (!intel_display_power_enabled(dev_priv->dev,
1106 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1107 cur_state = false;
1108 } else {
1109 reg = PIPECONF(cpu_transcoder);
1110 val = I915_READ(reg);
1111 cur_state = !!(val & PIPECONF_ENABLE);
1112 }
1113
63d7bbe9
JB		 1114 WARN(cur_state != state,
1115 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1116 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1117}
1118
931872fc
CW		 1119static void assert_plane(struct drm_i915_private *dev_priv,
1120 enum plane plane, bool state)
b24e7179
JB		 1121{
1122 int reg;
1123 u32 val;
931872fc 1124 bool cur_state;
b24e7179
JB		 1125
1126 reg = DSPCNTR(plane);
1127 val = I915_READ(reg);
931872fc
CW		 1128 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1129 WARN(cur_state != state,
1130 "plane %c assertion failure (expected %s, current %s)\n",
1131 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1132}
1133
931872fc
CW		 1134#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1135#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1136
b24e7179
JB		 1137static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1138 enum pipe pipe)
1139{
653e1026 1140 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1141 int reg, i;
1142 u32 val;
1143 int cur_pipe;
1144
653e1026
VS		 1145 /* Primary planes are fixed to pipes on gen4+ */
1146 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1147 reg = DSPCNTR(pipe);
1148 val = I915_READ(reg);
1149 WARN((val & DISPLAY_PLANE_ENABLE),
1150 "plane %c assertion failure, should be disabled but not\n",
1151 plane_name(pipe));
19ec1358 1152 return;
28c05794 1153 }
19ec1358 1154
b24e7179 1155 /* Need to check both planes against the pipe */
08e2a7de 1156 for_each_pipe(i) {
b24e7179
JB		 1157 reg = DSPCNTR(i);
1158 val = I915_READ(reg);
1159 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1160 DISPPLANE_SEL_PIPE_SHIFT;
1161 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1162 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1163 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1164 }
1165}
1166
19332d7a
JB		 1167static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1168 enum pipe pipe)
1169{
20674eef 1170 struct drm_device *dev = dev_priv->dev;
19332d7a
JB		 1171 int reg, i;
1172 u32 val;
1173
20674eef
VS		 1174 if (IS_VALLEYVIEW(dev)) {
1175 for (i = 0; i < dev_priv->num_plane; i++) {
1176 reg = SPCNTR(pipe, i);
1177 val = I915_READ(reg);
1178 WARN((val & SP_ENABLE),
1179 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1180 sprite_name(pipe, i), pipe_name(pipe));
1181 }
1182 } else if (INTEL_INFO(dev)->gen >= 7) {
1183 reg = SPRCTL(pipe);
19332d7a 1184 val = I915_READ(reg);
20674eef 1185 WARN((val & SPRITE_ENABLE),
06da8da2 1186 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1187 plane_name(pipe), pipe_name(pipe));
1188 } else if (INTEL_INFO(dev)->gen >= 5) {
1189 reg = DVSCNTR(pipe);
19332d7a 1190 val = I915_READ(reg);
20674eef 1191 WARN((val & DVS_ENABLE),
06da8da2 1192 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1193 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1194 }
1195}
1196
92f2584a
JB		 1197static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1198{
1199 u32 val;
1200 bool enabled;
1201
9d82aa17
ED		 1202 if (HAS_PCH_LPT(dev_priv->dev)) {
1203 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1204 return;
1205 }
1206
92f2584a
JB		 1207 val = I915_READ(PCH_DREF_CONTROL);
1208 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1209 DREF_SUPERSPREAD_SOURCE_MASK));
1210 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1211}
1212
ab9412ba
DV		 1213static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1214 enum pipe pipe)
92f2584a
JB		 1215{
1216 int reg;
1217 u32 val;
1218 bool enabled;
1219
ab9412ba 1220 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1221 val = I915_READ(reg);
1222 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1223 WARN(enabled,
1224 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1225 pipe_name(pipe));
92f2584a
JB		 1226}
1227
4e634389
KP		 1228static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1229 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1230{
1231 if ((val & DP_PORT_EN) == 0)
1232 return false;
1233
1234 if (HAS_PCH_CPT(dev_priv->dev)) {
1235 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1236 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1237 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1238 return false;
1239 } else {
1240 if ((val & DP_PIPE_MASK) != (pipe << 30))
1241 return false;
1242 }
1243 return true;
1244}
1245
1519b995
KP		 1246static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1247 enum pipe pipe, u32 val)
1248{
dc0fa718 1249 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1250 return false;
1251
1252 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1253 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1254 return false;
1255 } else {
dc0fa718 1256 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1257 return false;
1258 }
1259 return true;
1260}
1261
1262static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1263 enum pipe pipe, u32 val)
1264{
1265 if ((val & LVDS_PORT_EN) == 0)
1266 return false;
1267
1268 if (HAS_PCH_CPT(dev_priv->dev)) {
1269 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1270 return false;
1271 } else {
1272 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1273 return false;
1274 }
1275 return true;
1276}
1277
1278static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1279 enum pipe pipe, u32 val)
1280{
1281 if ((val & ADPA_DAC_ENABLE) == 0)
1282 return false;
1283 if (HAS_PCH_CPT(dev_priv->dev)) {
1284 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1285 return false;
1286 } else {
1287 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1288 return false;
1289 }
1290 return true;
1291}
1292
291906f1 1293static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1294 enum pipe pipe, int reg, u32 port_sel)
291906f1 1295{
47a05eca 1296 u32 val = I915_READ(reg);
4e634389 1297 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1298 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1299 reg, pipe_name(pipe));
de9a35ab 1300
75c5da27
DV		 1301 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1302 && (val & DP_PIPEB_SELECT),
de9a35ab 1303 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1304}
1305
1306static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1307 enum pipe pipe, int reg)
1308{
47a05eca 1309 u32 val = I915_READ(reg);
b70ad586 1310 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1311 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1312 reg, pipe_name(pipe));
de9a35ab 1313
dc0fa718 1314 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1315 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1316 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1317}
1318
1319static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1320 enum pipe pipe)
1321{
1322 int reg;
1323 u32 val;
291906f1 1324
f0575e92
KP		 1325 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1326 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1327 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1328
1329 reg = PCH_ADPA;
1330 val = I915_READ(reg);
b70ad586 1331 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1332 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1333 pipe_name(pipe));
291906f1
JB		 1334
1335 reg = PCH_LVDS;
1336 val = I915_READ(reg);
b70ad586 1337 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1338 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1339 pipe_name(pipe));
291906f1 1340
e2debe91
PZ		 1341 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1342 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1343 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1344}
1345
426115cf 1346static void vlv_enable_pll(struct intel_crtc *crtc)
87442f73 1347{
426115cf
DV		 1348 struct drm_device *dev = crtc->base.dev;
1349 struct drm_i915_private *dev_priv = dev->dev_private;
1350 int reg = DPLL(crtc->pipe);
1351 u32 dpll = crtc->config.dpll_hw_state.dpll;
87442f73 1352
426115cf 1353 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1354
1355 /* No really, not for ILK+ */
1356 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1357
1358 /* PLL is protected by panel, make sure we can write it */
1359 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
426115cf 1360 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1361
426115cf
DV		 1362 I915_WRITE(reg, dpll);
1363 POSTING_READ(reg);
1364 udelay(150);
1365
1366 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1367 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1368
1369 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1370 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1371
1372 /* We do this three times for luck */
426115cf 1373 I915_WRITE(reg, dpll);
87442f73
DV		 1374 POSTING_READ(reg);
1375 udelay(150); /* wait for warmup */
426115cf 1376 I915_WRITE(reg, dpll);
87442f73
DV		 1377 POSTING_READ(reg);
1378 udelay(150); /* wait for warmup */
426115cf 1379 I915_WRITE(reg, dpll);
87442f73
DV		 1380 POSTING_READ(reg);
1381 udelay(150); /* wait for warmup */
1382}
1383
66e3d5c0 1384static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1385{
66e3d5c0
DV		 1386 struct drm_device *dev = crtc->base.dev;
1387 struct drm_i915_private *dev_priv = dev->dev_private;
1388 int reg = DPLL(crtc->pipe);
1389 u32 dpll = crtc->config.dpll_hw_state.dpll;
63d7bbe9 1390
66e3d5c0 1391 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1392
63d7bbe9 1393 /* No really, not for ILK+ */
87442f73 1394 BUG_ON(dev_priv->info->gen >= 5);
63d7bbe9
JB		 1395
1396 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1397 if (IS_MOBILE(dev) && !IS_I830(dev))
1398 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1399
66e3d5c0
DV		 1400 I915_WRITE(reg, dpll);
1401
1402 /* Wait for the clocks to stabilize. */
1403 POSTING_READ(reg);
1404 udelay(150);
1405
1406 if (INTEL_INFO(dev)->gen >= 4) {
1407 I915_WRITE(DPLL_MD(crtc->pipe),
1408 crtc->config.dpll_hw_state.dpll_md);
1409 } else {
1410 /* The pixel multiplier can only be updated once the
1411 * DPLL is enabled and the clocks are stable.
1412 *
1413 * So write it again.
1414 */
1415 I915_WRITE(reg, dpll);
1416 }
63d7bbe9
JB		 1417
1418 /* We do this three times for luck */
66e3d5c0 1419 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1420 POSTING_READ(reg);
1421 udelay(150); /* wait for warmup */
66e3d5c0 1422 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1423 POSTING_READ(reg);
1424 udelay(150); /* wait for warmup */
66e3d5c0 1425 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1426 POSTING_READ(reg);
1427 udelay(150); /* wait for warmup */
1428}
1429
1430/**
50b44a44 1431 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1432 * @dev_priv: i915 private structure
1433 * @pipe: pipe PLL to disable
1434 *
1435 * Disable the PLL for @pipe, making sure the pipe is off first.
1436 *
1437 * Note! This is for pre-ILK only.
1438 */
50b44a44 1439static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9 1440{
63d7bbe9
JB		 1441 /* Don't disable pipe A or pipe A PLLs if needed */
1442 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1443 return;
1444
1445 /* Make sure the pipe isn't still relying on us */
1446 assert_pipe_disabled(dev_priv, pipe);
1447
50b44a44
DV		 1448 I915_WRITE(DPLL(pipe), 0);
1449 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1450}
1451
89b667f8
JB		 1452void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1453{
1454 u32 port_mask;
1455
1456 if (!port)
1457 port_mask = DPLL_PORTB_READY_MASK;
1458 else
1459 port_mask = DPLL_PORTC_READY_MASK;
1460
1461 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1462 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1463 'B' + port, I915_READ(DPLL(0)));
1464}
1465
92f2584a 1466/**
e72f9fbf 1467 * ironlake_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1468 * @dev_priv: i915 private structure
1469 * @pipe: pipe PLL to enable
1470 *
1471 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1472 * drives the transcoder clock.
1473 */
e2b78267 1474static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1475{
e2b78267
DV		 1476 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1477 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1478
48da64a8 1479 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1480 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1481 if (WARN_ON(pll == NULL))
48da64a8
CW		 1482 return;
1483
1484 if (WARN_ON(pll->refcount == 0))
1485 return;
ee7b9f93 1486
46edb027
DV		 1487 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1488 pll->name, pll->active, pll->on,
e2b78267 1489 crtc->base.base.id);
92f2584a 1490
cdbd2316
DV		 1491 if (pll->active++) {
1492 WARN_ON(!pll->on);
e9d6944e 1493 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1494 return;
1495 }
f4a091c7 1496 WARN_ON(pll->on);
ee7b9f93 1497
46edb027 1498 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1499 pll->enable(dev_priv, pll);
ee7b9f93 1500 pll->on = true;
92f2584a
JB		 1501}
1502
e2b78267 1503static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1504{
e2b78267
DV		 1505 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1506 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1507
92f2584a
JB		 1508 /* PCH only available on ILK+ */
1509 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1510 if (WARN_ON(pll == NULL))
ee7b9f93 1511 return;
92f2584a 1512
48da64a8
CW		 1513 if (WARN_ON(pll->refcount == 0))
1514 return;
7a419866 1515
46edb027
DV		 1516 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1517 pll->name, pll->active, pll->on,
e2b78267 1518 crtc->base.base.id);
7a419866 1519
48da64a8 1520 if (WARN_ON(pll->active == 0)) {
e9d6944e 1521 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1522 return;
1523 }
1524
e9d6944e 1525 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1526 WARN_ON(!pll->on);
cdbd2316 1527 if (--pll->active)
7a419866 1528 return;
ee7b9f93 1529
46edb027 1530 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1531 pll->disable(dev_priv, pll);
ee7b9f93 1532 pll->on = false;
92f2584a
JB		 1533}
1534
b8a4f404
PZ		 1535static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1536 enum pipe pipe)
040484af 1537{
23670b32 1538 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1539 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1540 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1541 uint32_t reg, val, pipeconf_val;
040484af
JB		 1542
1543 /* PCH only available on ILK+ */
1544 BUG_ON(dev_priv->info->gen < 5);
1545
1546 /* Make sure PCH DPLL is enabled */
e72f9fbf 1547 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1548 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1549
1550 /* FDI must be feeding us bits for PCH ports */
1551 assert_fdi_tx_enabled(dev_priv, pipe);
1552 assert_fdi_rx_enabled(dev_priv, pipe);
1553
23670b32
DV		 1554 if (HAS_PCH_CPT(dev)) {
1555 /* Workaround: Set the timing override bit before enabling the
1556 * pch transcoder. */
1557 reg = TRANS_CHICKEN2(pipe);
1558 val = I915_READ(reg);
1559 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1560 I915_WRITE(reg, val);
59c859d6 1561 }
23670b32 1562
ab9412ba 1563 reg = PCH_TRANSCONF(pipe);
040484af 1564 val = I915_READ(reg);
5f7f726d 1565 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1566
1567 if (HAS_PCH_IBX(dev_priv->dev)) {
1568 /*
1569 * make the BPC in transcoder be consistent with
1570 * that in pipeconf reg.
1571 */
dfd07d72
DV		 1572 val &= ~PIPECONF_BPC_MASK;
1573 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1574 }
5f7f726d
PZ		 1575
1576 val &= ~TRANS_INTERLACE_MASK;
1577 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1578 if (HAS_PCH_IBX(dev_priv->dev) &&
1579 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1580 val |= TRANS_LEGACY_INTERLACED_ILK;
1581 else
1582 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1583 else
1584 val |= TRANS_PROGRESSIVE;
1585
040484af
JB		 1586 I915_WRITE(reg, val | TRANS_ENABLE);
1587 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1588 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1589}
1590
8fb033d7 1591static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1592 enum transcoder cpu_transcoder)
040484af 1593{
8fb033d7 1594 u32 val, pipeconf_val;
8fb033d7
PZ		 1595
1596 /* PCH only available on ILK+ */
1597 BUG_ON(dev_priv->info->gen < 5);
1598
8fb033d7 1599 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1600 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1601 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1602
223a6fdf
PZ		 1603 /* Workaround: set timing override bit. */
1604 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1605 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1606 I915_WRITE(_TRANSA_CHICKEN2, val);
1607
25f3ef11 1608 val = TRANS_ENABLE;
937bb610 1609 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1610
9a76b1c6
PZ		 1611 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1612 PIPECONF_INTERLACED_ILK)
a35f2679 1613 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1614 else
1615 val |= TRANS_PROGRESSIVE;
1616
ab9412ba
DV		 1617 I915_WRITE(LPT_TRANSCONF, val);
1618 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1619 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1620}
1621
b8a4f404
PZ		 1622static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1623 enum pipe pipe)
040484af 1624{
23670b32
DV		 1625 struct drm_device *dev = dev_priv->dev;
1626 uint32_t reg, val;
040484af
JB		 1627
1628 /* FDI relies on the transcoder */
1629 assert_fdi_tx_disabled(dev_priv, pipe);
1630 assert_fdi_rx_disabled(dev_priv, pipe);
1631
291906f1
JB		 1632 /* Ports must be off as well */
1633 assert_pch_ports_disabled(dev_priv, pipe);
1634
ab9412ba 1635 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1636 val = I915_READ(reg);
1637 val &= ~TRANS_ENABLE;
1638 I915_WRITE(reg, val);
1639 /* wait for PCH transcoder off, transcoder state */
1640 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1641 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1642
1643 if (!HAS_PCH_IBX(dev)) {
1644 /* Workaround: Clear the timing override chicken bit again. */
1645 reg = TRANS_CHICKEN2(pipe);
1646 val = I915_READ(reg);
1647 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1648 I915_WRITE(reg, val);
1649 }
040484af
JB		 1650}
1651
ab4d966c 1652static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1653{
8fb033d7
PZ		 1654 u32 val;
1655
ab9412ba 1656 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1657 val &= ~TRANS_ENABLE;
ab9412ba 1658 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1659 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1660 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1661 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1662
1663 /* Workaround: clear timing override bit. */
1664 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1665 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1666 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1667}
1668
b24e7179 1669/**
309cfea8 1670 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1671 * @dev_priv: i915 private structure
1672 * @pipe: pipe to enable
040484af 1673 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1674 *
1675 * Enable @pipe, making sure that various hardware specific requirements
1676 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1677 *
1678 * @pipe should be %PIPE_A or %PIPE_B.
1679 *
1680 * Will wait until the pipe is actually running (i.e. first vblank) before
1681 * returning.
1682 */
040484af 1683static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
23538ef1 1684 bool pch_port, bool dsi)
b24e7179 1685{
702e7a56
PZ		 1686 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1687 pipe);
1a240d4d 1688 enum pipe pch_transcoder;
b24e7179
JB		 1689 int reg;
1690 u32 val;
1691
58c6eaa2 1692 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 1693 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 1694 assert_sprites_disabled(dev_priv, pipe);
1695
681e5811 1696 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1697 pch_transcoder = TRANSCODER_A;
1698 else
1699 pch_transcoder = pipe;
1700
b24e7179
JB		 1701 /*
1702 * A pipe without a PLL won't actually be able to drive bits from
1703 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1704 * need the check.
1705 */
1706 if (!HAS_PCH_SPLIT(dev_priv->dev))
23538ef1
JN		 1707 if (dsi)
1708 assert_dsi_pll_enabled(dev_priv);
1709 else
1710 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1711 else {
1712 if (pch_port) {
1713 /* if driving the PCH, we need FDI enabled */
cc391bbb 1714 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1715 assert_fdi_tx_pll_enabled(dev_priv,
1716 (enum pipe) cpu_transcoder);
040484af
JB		 1717 }
1718 /* FIXME: assert CPU port conditions for SNB+ */
1719 }
b24e7179 1720
702e7a56 1721 reg = PIPECONF(cpu_transcoder);
b24e7179 1722 val = I915_READ(reg);
00d70b15
CW		 1723 if (val & PIPECONF_ENABLE)
1724 return;
1725
1726 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1727 intel_wait_for_vblank(dev_priv->dev, pipe);
1728}
1729
1730/**
309cfea8 1731 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1732 * @dev_priv: i915 private structure
1733 * @pipe: pipe to disable
1734 *
1735 * Disable @pipe, making sure that various hardware specific requirements
1736 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1737 *
1738 * @pipe should be %PIPE_A or %PIPE_B.
1739 *
1740 * Will wait until the pipe has shut down before returning.
1741 */
1742static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1743 enum pipe pipe)
1744{
702e7a56
PZ		 1745 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1746 pipe);
b24e7179
JB		 1747 int reg;
1748 u32 val;
1749
1750 /*
1751 * Make sure planes won't keep trying to pump pixels to us,
1752 * or we might hang the display.
1753 */
1754 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 1755 assert_cursor_disabled(dev_priv, pipe);
19332d7a 1756 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1757
1758 /* Don't disable pipe A or pipe A PLLs if needed */
1759 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1760 return;
1761
702e7a56 1762 reg = PIPECONF(cpu_transcoder);
b24e7179 1763 val = I915_READ(reg);
00d70b15
CW		 1764 if ((val & PIPECONF_ENABLE) == 0)
1765 return;
1766
1767 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1768 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1769}
1770
d74362c9
KP		 1771/*
1772 * Plane regs are double buffered, going from enabled->disabled needs a
1773 * trigger in order to latch. The display address reg provides this.
1774 */
6f1d69b0 1775void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1776 enum plane plane)
1777{
14f86147
DL		 1778 if (dev_priv->info->gen >= 4)
1779 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1780 else
1781 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1782}
1783
b24e7179
JB		 1784/**
1785 * intel_enable_plane - enable a display plane on a given pipe
1786 * @dev_priv: i915 private structure
1787 * @plane: plane to enable
1788 * @pipe: pipe being fed
1789 *
1790 * Enable @plane on @pipe, making sure that @pipe is running first.
1791 */
1792static void intel_enable_plane(struct drm_i915_private *dev_priv,
1793 enum plane plane, enum pipe pipe)
1794{
1795 int reg;
1796 u32 val;
1797
1798 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1799 assert_pipe_enabled(dev_priv, pipe);
1800
1801 reg = DSPCNTR(plane);
1802 val = I915_READ(reg);
00d70b15
CW		 1803 if (val & DISPLAY_PLANE_ENABLE)
1804 return;
1805
1806 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1807 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1808 intel_wait_for_vblank(dev_priv->dev, pipe);
1809}
1810
b24e7179
JB		 1811/**
1812 * intel_disable_plane - disable a display plane
1813 * @dev_priv: i915 private structure
1814 * @plane: plane to disable
1815 * @pipe: pipe consuming the data
1816 *
1817 * Disable @plane; should be an independent operation.
1818 */
1819static void intel_disable_plane(struct drm_i915_private *dev_priv,
1820 enum plane plane, enum pipe pipe)
1821{
1822 int reg;
1823 u32 val;
1824
1825 reg = DSPCNTR(plane);
1826 val = I915_READ(reg);
00d70b15
CW		 1827 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1828 return;
1829
1830 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1831 intel_flush_display_plane(dev_priv, plane);
1832 intel_wait_for_vblank(dev_priv->dev, pipe);
1833}
1834
693db184
CW		 1835static bool need_vtd_wa(struct drm_device *dev)
1836{
1837#ifdef CONFIG_INTEL_IOMMU
1838 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1839 return true;
1840#endif
1841 return false;
1842}
1843
127bd2ac 1844int
48b956c5 1845intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1846 struct drm_i915_gem_object *obj,
919926ae 1847 struct intel_ring_buffer *pipelined)
6b95a207 1848{
ce453d81 1849 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1850 u32 alignment;
1851 int ret;
1852
05394f39 1853 switch (obj->tiling_mode) {
6b95a207 1854 case I915_TILING_NONE:
534843da
CW		 1855 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1856 alignment = 128 * 1024;
a6c45cf0 1857 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1858 alignment = 4 * 1024;
1859 else
1860 alignment = 64 * 1024;
6b95a207
KH		 1861 break;
1862 case I915_TILING_X:
1863 /* pin() will align the object as required by fence */
1864 alignment = 0;
1865 break;
1866 case I915_TILING_Y:
8bb6e959
DV		 1867 /* Despite that we check this in framebuffer_init userspace can
1868 * screw us over and change the tiling after the fact. Only
1869 * pinned buffers can't change their tiling. */
1870 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1871 return -EINVAL;
1872 default:
1873 BUG();
1874 }
1875
693db184
CW		 1876 /* Note that the w/a also requires 64 PTE of padding following the
1877 * bo. We currently fill all unused PTE with the shadow page and so
1878 * we should always have valid PTE following the scanout preventing
1879 * the VT-d warning.
1880 */
1881 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1882 alignment = 256 * 1024;
1883
ce453d81 1884 dev_priv->mm.interruptible = false;
2da3b9b9 1885 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1886 if (ret)
ce453d81 1887 goto err_interruptible;
6b95a207
KH		 1888
1889 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1890 * fence, whereas 965+ only requires a fence if using
1891 * framebuffer compression. For simplicity, we always install
1892 * a fence as the cost is not that onerous.
1893 */
06d98131 1894 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1895 if (ret)
1896 goto err_unpin;
1690e1eb 1897
9a5a53b3 1898 i915_gem_object_pin_fence(obj);
6b95a207 1899
ce453d81 1900 dev_priv->mm.interruptible = true;
6b95a207 1901 return 0;
48b956c5
CW		 1902
1903err_unpin:
cc98b413 1904 i915_gem_object_unpin_from_display_plane(obj);
ce453d81
CW		 1905err_interruptible:
1906 dev_priv->mm.interruptible = true;
48b956c5 1907 return ret;
6b95a207
KH		 1908}
1909
1690e1eb
CW		 1910void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1911{
1912 i915_gem_object_unpin_fence(obj);
cc98b413 1913 i915_gem_object_unpin_from_display_plane(obj);
1690e1eb
CW		 1914}
1915
c2c75131
DV		 1916/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1917 * is assumed to be a power-of-two. */
bc752862
CW		 1918unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1919 unsigned int tiling_mode,
1920 unsigned int cpp,
1921 unsigned int pitch)
c2c75131 1922{
bc752862
CW		 1923 if (tiling_mode != I915_TILING_NONE) {
1924 unsigned int tile_rows, tiles;
c2c75131 1925
bc752862
CW		 1926 tile_rows = *y / 8;
1927 *y %= 8;
c2c75131 1928
bc752862
CW		 1929 tiles = *x / (512/cpp);
1930 *x %= 512/cpp;
1931
1932 return tile_rows * pitch * 8 + tiles * 4096;
1933 } else {
1934 unsigned int offset;
1935
1936 offset = *y * pitch + *x * cpp;
1937 *y = 0;
1938 *x = (offset & 4095) / cpp;
1939 return offset & -4096;
1940 }
c2c75131
DV		 1941}
1942
17638cd6
JB		 1943static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1944 int x, int y)
81255565
JB		 1945{
1946 struct drm_device *dev = crtc->dev;
1947 struct drm_i915_private *dev_priv = dev->dev_private;
1948 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1949 struct intel_framebuffer *intel_fb;
05394f39 1950 struct drm_i915_gem_object *obj;
81255565 1951 int plane = intel_crtc->plane;
e506a0c6 1952 unsigned long linear_offset;
81255565 1953 u32 dspcntr;
5eddb70b 1954 u32 reg;
81255565
JB		 1955
1956 switch (plane) {
1957 case 0:
1958 case 1:
1959 break;
1960 default:
84f44ce7 1961 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 1962 return -EINVAL;
1963 }
1964
1965 intel_fb = to_intel_framebuffer(fb);
1966 obj = intel_fb->obj;
81255565 1967
5eddb70b
CW		 1968 reg = DSPCNTR(plane);
1969 dspcntr = I915_READ(reg);
81255565
JB		 1970 /* Mask out pixel format bits in case we change it */
1971 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 1972 switch (fb->pixel_format) {
1973 case DRM_FORMAT_C8:
81255565
JB		 1974 dspcntr |= DISPPLANE_8BPP;
1975 break;
57779d06
VS		 1976 case DRM_FORMAT_XRGB1555:
1977 case DRM_FORMAT_ARGB1555:
1978 dspcntr |= DISPPLANE_BGRX555;
81255565 1979 break;
57779d06
VS		 1980 case DRM_FORMAT_RGB565:
1981 dspcntr |= DISPPLANE_BGRX565;
1982 break;
1983 case DRM_FORMAT_XRGB8888:
1984 case DRM_FORMAT_ARGB8888:
1985 dspcntr |= DISPPLANE_BGRX888;
1986 break;
1987 case DRM_FORMAT_XBGR8888:
1988 case DRM_FORMAT_ABGR8888:
1989 dspcntr |= DISPPLANE_RGBX888;
1990 break;
1991 case DRM_FORMAT_XRGB2101010:
1992 case DRM_FORMAT_ARGB2101010:
1993 dspcntr |= DISPPLANE_BGRX101010;
1994 break;
1995 case DRM_FORMAT_XBGR2101010:
1996 case DRM_FORMAT_ABGR2101010:
1997 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 1998 break;
1999 default:
baba133a 2000 BUG();
81255565 2001 }
57779d06 2002
a6c45cf0 2003 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2004 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2005 dspcntr |= DISPPLANE_TILED;
2006 else
2007 dspcntr &= ~DISPPLANE_TILED;
2008 }
2009
de1aa629
VS		 2010 if (IS_G4X(dev))
2011 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2012
5eddb70b 2013 I915_WRITE(reg, dspcntr);
81255565 2014
e506a0c6 2015 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2016
c2c75131
DV		 2017 if (INTEL_INFO(dev)->gen >= 4) {
2018 intel_crtc->dspaddr_offset =
bc752862
CW		 2019 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2020 fb->bits_per_pixel / 8,
2021 fb->pitches[0]);
c2c75131
DV		 2022 linear_offset -= intel_crtc->dspaddr_offset;
2023 } else {
e506a0c6 2024 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2025 }
e506a0c6 2026
f343c5f6
BW		 2027 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2028 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2029 fb->pitches[0]);
01f2c773 2030 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2031 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131 2032 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2033 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2034 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2035 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2036 } else
f343c5f6 2037 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2038 POSTING_READ(reg);
81255565 2039
17638cd6
JB		 2040 return 0;
2041}
2042
2043static int ironlake_update_plane(struct drm_crtc *crtc,
2044 struct drm_framebuffer *fb, int x, int y)
2045{
2046 struct drm_device *dev = crtc->dev;
2047 struct drm_i915_private *dev_priv = dev->dev_private;
2048 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2049 struct intel_framebuffer *intel_fb;
2050 struct drm_i915_gem_object *obj;
2051 int plane = intel_crtc->plane;
e506a0c6 2052 unsigned long linear_offset;
17638cd6
JB		 2053 u32 dspcntr;
2054 u32 reg;
2055
2056 switch (plane) {
2057 case 0:
2058 case 1:
27f8227b 2059 case 2:
17638cd6
JB		 2060 break;
2061 default:
84f44ce7 2062 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2063 return -EINVAL;
2064 }
2065
2066 intel_fb = to_intel_framebuffer(fb);
2067 obj = intel_fb->obj;
2068
2069 reg = DSPCNTR(plane);
2070 dspcntr = I915_READ(reg);
2071 /* Mask out pixel format bits in case we change it */
2072 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2073 switch (fb->pixel_format) {
2074 case DRM_FORMAT_C8:
17638cd6
JB		 2075 dspcntr |= DISPPLANE_8BPP;
2076 break;
57779d06
VS		 2077 case DRM_FORMAT_RGB565:
2078 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2079 break;
57779d06
VS		 2080 case DRM_FORMAT_XRGB8888:
2081 case DRM_FORMAT_ARGB8888:
2082 dspcntr |= DISPPLANE_BGRX888;
2083 break;
2084 case DRM_FORMAT_XBGR8888:
2085 case DRM_FORMAT_ABGR8888:
2086 dspcntr |= DISPPLANE_RGBX888;
2087 break;
2088 case DRM_FORMAT_XRGB2101010:
2089 case DRM_FORMAT_ARGB2101010:
2090 dspcntr |= DISPPLANE_BGRX101010;
2091 break;
2092 case DRM_FORMAT_XBGR2101010:
2093 case DRM_FORMAT_ABGR2101010:
2094 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2095 break;
2096 default:
baba133a 2097 BUG();
17638cd6
JB		 2098 }
2099
2100 if (obj->tiling_mode != I915_TILING_NONE)
2101 dspcntr |= DISPPLANE_TILED;
2102 else
2103 dspcntr &= ~DISPPLANE_TILED;
2104
1f5d76db
PZ		 2105 if (IS_HASWELL(dev))
2106 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2107 else
2108 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6
JB		 2109
2110 I915_WRITE(reg, dspcntr);
2111
e506a0c6 2112 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2113 intel_crtc->dspaddr_offset =
bc752862
CW		 2114 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2115 fb->bits_per_pixel / 8,
2116 fb->pitches[0]);
c2c75131 2117 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2118
f343c5f6
BW		 2119 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2120 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2121 fb->pitches[0]);
01f2c773 2122 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131 2123 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2124 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2125 if (IS_HASWELL(dev)) {
2126 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2127 } else {
2128 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2129 I915_WRITE(DSPLINOFF(plane), linear_offset);
2130 }
17638cd6
JB		 2131 POSTING_READ(reg);
2132
2133 return 0;
2134}
2135
2136/* Assume fb object is pinned & idle & fenced and just update base pointers */
2137static int
2138intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2139 int x, int y, enum mode_set_atomic state)
2140{
2141 struct drm_device *dev = crtc->dev;
2142 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2143
6b8e6ed0
CW		 2144 if (dev_priv->display.disable_fbc)
2145 dev_priv->display.disable_fbc(dev);
3dec0095 2146 intel_increase_pllclock(crtc);
81255565 2147
6b8e6ed0 2148 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2149}
2150
96a02917
VS		 2151void intel_display_handle_reset(struct drm_device *dev)
2152{
2153 struct drm_i915_private *dev_priv = dev->dev_private;
2154 struct drm_crtc *crtc;
2155
2156 /*
2157 * Flips in the rings have been nuked by the reset,
2158 * so complete all pending flips so that user space
2159 * will get its events and not get stuck.
2160 *
2161 * Also update the base address of all primary
2162 * planes to the the last fb to make sure we're
2163 * showing the correct fb after a reset.
2164 *
2165 * Need to make two loops over the crtcs so that we
2166 * don't try to grab a crtc mutex before the
2167 * pending_flip_queue really got woken up.
2168 */
2169
2170 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2171 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2172 enum plane plane = intel_crtc->plane;
2173
2174 intel_prepare_page_flip(dev, plane);
2175 intel_finish_page_flip_plane(dev, plane);
2176 }
2177
2178 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2179 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2180
2181 mutex_lock(&crtc->mutex);
2182 if (intel_crtc->active)
2183 dev_priv->display.update_plane(crtc, crtc->fb,
2184 crtc->x, crtc->y);
2185 mutex_unlock(&crtc->mutex);
2186 }
2187}
2188
14667a4b
CW		 2189static int
2190intel_finish_fb(struct drm_framebuffer *old_fb)
2191{
2192 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2193 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2194 bool was_interruptible = dev_priv->mm.interruptible;
2195 int ret;
2196
14667a4b
CW		 2197 /* Big Hammer, we also need to ensure that any pending
2198 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2199 * current scanout is retired before unpinning the old
2200 * framebuffer.
2201 *
2202 * This should only fail upon a hung GPU, in which case we
2203 * can safely continue.
2204 */
2205 dev_priv->mm.interruptible = false;
2206 ret = i915_gem_object_finish_gpu(obj);
2207 dev_priv->mm.interruptible = was_interruptible;
2208
2209 return ret;
2210}
2211
198598d0
VS		 2212static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2213{
2214 struct drm_device *dev = crtc->dev;
2215 struct drm_i915_master_private *master_priv;
2216 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2217
2218 if (!dev->primary->master)
2219 return;
2220
2221 master_priv = dev->primary->master->driver_priv;
2222 if (!master_priv->sarea_priv)
2223 return;
2224
2225 switch (intel_crtc->pipe) {
2226 case 0:
2227 master_priv->sarea_priv->pipeA_x = x;
2228 master_priv->sarea_priv->pipeA_y = y;
2229 break;
2230 case 1:
2231 master_priv->sarea_priv->pipeB_x = x;
2232 master_priv->sarea_priv->pipeB_y = y;
2233 break;
2234 default:
2235 break;
2236 }
2237}
2238
5c3b82e2 2239static int
3c4fdcfb 2240intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2241 struct drm_framebuffer *fb)
79e53945
JB		 2242{
2243 struct drm_device *dev = crtc->dev;
6b8e6ed0 2244 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2245 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2246 struct drm_framebuffer *old_fb;
5c3b82e2 2247 int ret;
79e53945
JB		 2248
2249 /* no fb bound */
94352cf9 2250 if (!fb) {
a5071c2f 2251 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2252 return 0;
2253 }
2254
7eb552ae 2255 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2256 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2257 plane_name(intel_crtc->plane),
2258 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2259 return -EINVAL;
79e53945
JB		 2260 }
2261
5c3b82e2 2262 mutex_lock(&dev->struct_mutex);
265db958 2263 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2264 to_intel_framebuffer(fb)->obj,
919926ae 2265 NULL);
5c3b82e2
CW		 2266 if (ret != 0) {
2267 mutex_unlock(&dev->struct_mutex);
a5071c2f 2268 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2269 return ret;
2270 }
79e53945 2271
4d6a3e63
JB		 2272 /* Update pipe size and adjust fitter if needed */
2273 if (i915_fastboot) {
2274 I915_WRITE(PIPESRC(intel_crtc->pipe),
2275 ((crtc->mode.hdisplay - 1) << 16) |
2276 (crtc->mode.vdisplay - 1));
2277 if (!intel_crtc->config.pch_pfit.size &&
2278 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2279 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2280 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2281 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2282 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2283 }
2284 }
2285
94352cf9 2286 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2287 if (ret) {
94352cf9 2288 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2289 mutex_unlock(&dev->struct_mutex);
a5071c2f 2290 DRM_ERROR("failed to update base address\n");
4e6cfefc 2291 return ret;
79e53945 2292 }
3c4fdcfb 2293
94352cf9
DV		 2294 old_fb = crtc->fb;
2295 crtc->fb = fb;
6c4c86f5
DV		 2296 crtc->x = x;
2297 crtc->y = y;
94352cf9 2298
b7f1de28 2299 if (old_fb) {
d7697eea
DV		 2300 if (intel_crtc->active && old_fb != fb)
2301 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2302 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2303 }
652c393a 2304
6b8e6ed0 2305 intel_update_fbc(dev);
4906557e 2306 intel_edp_psr_update(dev);
5c3b82e2 2307 mutex_unlock(&dev->struct_mutex);
79e53945 2308
198598d0 2309 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2310
2311 return 0;
79e53945
JB		 2312}
2313
5e84e1a4
ZW		 2314static void intel_fdi_normal_train(struct drm_crtc *crtc)
2315{
2316 struct drm_device *dev = crtc->dev;
2317 struct drm_i915_private *dev_priv = dev->dev_private;
2318 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2319 int pipe = intel_crtc->pipe;
2320 u32 reg, temp;
2321
2322 /* enable normal train */
2323 reg = FDI_TX_CTL(pipe);
2324 temp = I915_READ(reg);
61e499bf 2325 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2326 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2327 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2328 } else {
2329 temp &= ~FDI_LINK_TRAIN_NONE;
2330 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2331 }
5e84e1a4
ZW		 2332 I915_WRITE(reg, temp);
2333
2334 reg = FDI_RX_CTL(pipe);
2335 temp = I915_READ(reg);
2336 if (HAS_PCH_CPT(dev)) {
2337 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2338 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2339 } else {
2340 temp &= ~FDI_LINK_TRAIN_NONE;
2341 temp |= FDI_LINK_TRAIN_NONE;
2342 }
2343 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2344
2345 /* wait one idle pattern time */
2346 POSTING_READ(reg);
2347 udelay(1000);
357555c0
JB		 2348
2349 /* IVB wants error correction enabled */
2350 if (IS_IVYBRIDGE(dev))
2351 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2352 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2353}
2354
1e833f40
DV		 2355static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2356{
2357 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2358}
2359
01a415fd
DV		 2360static void ivb_modeset_global_resources(struct drm_device *dev)
2361{
2362 struct drm_i915_private *dev_priv = dev->dev_private;
2363 struct intel_crtc *pipe_B_crtc =
2364 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2365 struct intel_crtc *pipe_C_crtc =
2366 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2367 uint32_t temp;
2368
1e833f40
DV		 2369 /*
2370 * When everything is off disable fdi C so that we could enable fdi B
2371 * with all lanes. Note that we don't care about enabled pipes without
2372 * an enabled pch encoder.
2373 */
2374 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2375 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2376 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2377 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2378
2379 temp = I915_READ(SOUTH_CHICKEN1);
2380 temp &= ~FDI_BC_BIFURCATION_SELECT;
2381 DRM_DEBUG_KMS("disabling fdi C rx\n");
2382 I915_WRITE(SOUTH_CHICKEN1, temp);
2383 }
2384}
2385
8db9d77b
ZW		 2386/* The FDI link training functions for ILK/Ibexpeak. */
2387static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2388{
2389 struct drm_device *dev = crtc->dev;
2390 struct drm_i915_private *dev_priv = dev->dev_private;
2391 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2392 int pipe = intel_crtc->pipe;
0fc932b8 2393 int plane = intel_crtc->plane;
5eddb70b 2394 u32 reg, temp, tries;
8db9d77b 2395
0fc932b8
JB		 2396 /* FDI needs bits from pipe & plane first */
2397 assert_pipe_enabled(dev_priv, pipe);
2398 assert_plane_enabled(dev_priv, plane);
2399
e1a44743
AJ		 2400 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2401 for train result */
5eddb70b
CW		 2402 reg = FDI_RX_IMR(pipe);
2403 temp = I915_READ(reg);
e1a44743
AJ		 2404 temp &= ~FDI_RX_SYMBOL_LOCK;
2405 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2406 I915_WRITE(reg, temp);
2407 I915_READ(reg);
e1a44743
AJ		 2408 udelay(150);
2409
8db9d77b 2410 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2411 reg = FDI_TX_CTL(pipe);
2412 temp = I915_READ(reg);
627eb5a3
DV		 2413 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2414 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2415 temp &= ~FDI_LINK_TRAIN_NONE;
2416 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2417 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2418
5eddb70b
CW		 2419 reg = FDI_RX_CTL(pipe);
2420 temp = I915_READ(reg);
8db9d77b
ZW		 2421 temp &= ~FDI_LINK_TRAIN_NONE;
2422 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2423 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2424
2425 POSTING_READ(reg);
8db9d77b
ZW		 2426 udelay(150);
2427
5b2adf89 2428 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2429 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2430 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2431 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2432
5eddb70b 2433 reg = FDI_RX_IIR(pipe);
e1a44743 2434 for (tries = 0; tries < 5; tries++) {
5eddb70b 2435 temp = I915_READ(reg);
8db9d77b
ZW		 2436 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2437
2438 if ((temp & FDI_RX_BIT_LOCK)) {
2439 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2440 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2441 break;
2442 }
8db9d77b 2443 }
e1a44743 2444 if (tries == 5)
5eddb70b 2445 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2446
2447 /* Train 2 */
5eddb70b
CW		 2448 reg = FDI_TX_CTL(pipe);
2449 temp = I915_READ(reg);
8db9d77b
ZW		 2450 temp &= ~FDI_LINK_TRAIN_NONE;
2451 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2452 I915_WRITE(reg, temp);
8db9d77b 2453
5eddb70b
CW		 2454 reg = FDI_RX_CTL(pipe);
2455 temp = I915_READ(reg);
8db9d77b
ZW		 2456 temp &= ~FDI_LINK_TRAIN_NONE;
2457 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2458 I915_WRITE(reg, temp);
8db9d77b 2459
5eddb70b
CW		 2460 POSTING_READ(reg);
2461 udelay(150);
8db9d77b 2462
5eddb70b 2463 reg = FDI_RX_IIR(pipe);
e1a44743 2464 for (tries = 0; tries < 5; tries++) {
5eddb70b 2465 temp = I915_READ(reg);
8db9d77b
ZW		 2466 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2467
2468 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2469 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2470 DRM_DEBUG_KMS("FDI train 2 done.\n");
2471 break;
2472 }
8db9d77b 2473 }
e1a44743 2474 if (tries == 5)
5eddb70b 2475 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2476
2477 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2478
8db9d77b
ZW		 2479}
2480
0206e353 2481static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2482 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2483 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2484 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2485 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2486};
2487
2488/* The FDI link training functions for SNB/Cougarpoint. */
2489static void gen6_fdi_link_train(struct drm_crtc *crtc)
2490{
2491 struct drm_device *dev = crtc->dev;
2492 struct drm_i915_private *dev_priv = dev->dev_private;
2493 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2494 int pipe = intel_crtc->pipe;
fa37d39e 2495 u32 reg, temp, i, retry;
8db9d77b 2496
e1a44743
AJ		 2497 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2498 for train result */
5eddb70b
CW		 2499 reg = FDI_RX_IMR(pipe);
2500 temp = I915_READ(reg);
e1a44743
AJ		 2501 temp &= ~FDI_RX_SYMBOL_LOCK;
2502 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2503 I915_WRITE(reg, temp);
2504
2505 POSTING_READ(reg);
e1a44743
AJ		 2506 udelay(150);
2507
8db9d77b 2508 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2509 reg = FDI_TX_CTL(pipe);
2510 temp = I915_READ(reg);
627eb5a3
DV		 2511 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2512 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2513 temp &= ~FDI_LINK_TRAIN_NONE;
2514 temp |= FDI_LINK_TRAIN_PATTERN_1;
2515 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2516 /* SNB-B */
2517 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2518 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2519
d74cf324
DV		 2520 I915_WRITE(FDI_RX_MISC(pipe),
2521 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2522
5eddb70b
CW		 2523 reg = FDI_RX_CTL(pipe);
2524 temp = I915_READ(reg);
8db9d77b
ZW		 2525 if (HAS_PCH_CPT(dev)) {
2526 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2527 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2528 } else {
2529 temp &= ~FDI_LINK_TRAIN_NONE;
2530 temp |= FDI_LINK_TRAIN_PATTERN_1;
2531 }
5eddb70b
CW		 2532 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2533
2534 POSTING_READ(reg);
8db9d77b
ZW		 2535 udelay(150);
2536
0206e353 2537 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2538 reg = FDI_TX_CTL(pipe);
2539 temp = I915_READ(reg);
8db9d77b
ZW		 2540 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2541 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2542 I915_WRITE(reg, temp);
2543
2544 POSTING_READ(reg);
8db9d77b
ZW		 2545 udelay(500);
2546
fa37d39e
SP		 2547 for (retry = 0; retry < 5; retry++) {
2548 reg = FDI_RX_IIR(pipe);
2549 temp = I915_READ(reg);
2550 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2551 if (temp & FDI_RX_BIT_LOCK) {
2552 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2553 DRM_DEBUG_KMS("FDI train 1 done.\n");
2554 break;
2555 }
2556 udelay(50);
8db9d77b 2557 }
fa37d39e
SP		 2558 if (retry < 5)
2559 break;
8db9d77b
ZW		 2560 }
2561 if (i == 4)
5eddb70b 2562 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2563
2564 /* Train 2 */
5eddb70b
CW		 2565 reg = FDI_TX_CTL(pipe);
2566 temp = I915_READ(reg);
8db9d77b
ZW		 2567 temp &= ~FDI_LINK_TRAIN_NONE;
2568 temp |= FDI_LINK_TRAIN_PATTERN_2;
2569 if (IS_GEN6(dev)) {
2570 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2571 /* SNB-B */
2572 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2573 }
5eddb70b 2574 I915_WRITE(reg, temp);
8db9d77b 2575
5eddb70b
CW		 2576 reg = FDI_RX_CTL(pipe);
2577 temp = I915_READ(reg);
8db9d77b
ZW		 2578 if (HAS_PCH_CPT(dev)) {
2579 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2580 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2581 } else {
2582 temp &= ~FDI_LINK_TRAIN_NONE;
2583 temp |= FDI_LINK_TRAIN_PATTERN_2;
2584 }
5eddb70b
CW		 2585 I915_WRITE(reg, temp);
2586
2587 POSTING_READ(reg);
8db9d77b
ZW		 2588 udelay(150);
2589
0206e353 2590 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2591 reg = FDI_TX_CTL(pipe);
2592 temp = I915_READ(reg);
8db9d77b
ZW		 2593 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2594 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2595 I915_WRITE(reg, temp);
2596
2597 POSTING_READ(reg);
8db9d77b
ZW		 2598 udelay(500);
2599
fa37d39e
SP		 2600 for (retry = 0; retry < 5; retry++) {
2601 reg = FDI_RX_IIR(pipe);
2602 temp = I915_READ(reg);
2603 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2604 if (temp & FDI_RX_SYMBOL_LOCK) {
2605 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2606 DRM_DEBUG_KMS("FDI train 2 done.\n");
2607 break;
2608 }
2609 udelay(50);
8db9d77b 2610 }
fa37d39e
SP		 2611 if (retry < 5)
2612 break;
8db9d77b
ZW		 2613 }
2614 if (i == 4)
5eddb70b 2615 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2616
2617 DRM_DEBUG_KMS("FDI train done.\n");
2618}
2619
357555c0
JB		 2620/* Manual link training for Ivy Bridge A0 parts */
2621static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2622{
2623 struct drm_device *dev = crtc->dev;
2624 struct drm_i915_private *dev_priv = dev->dev_private;
2625 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2626 int pipe = intel_crtc->pipe;
139ccd3f 2627 u32 reg, temp, i, j;
357555c0
JB		 2628
2629 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2630 for train result */
2631 reg = FDI_RX_IMR(pipe);
2632 temp = I915_READ(reg);
2633 temp &= ~FDI_RX_SYMBOL_LOCK;
2634 temp &= ~FDI_RX_BIT_LOCK;
2635 I915_WRITE(reg, temp);
2636
2637 POSTING_READ(reg);
2638 udelay(150);
2639
01a415fd
DV		 2640 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2641 I915_READ(FDI_RX_IIR(pipe)));
2642
139ccd3f
JB		 2643 /* Try each vswing and preemphasis setting twice before moving on */
2644 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2645 /* disable first in case we need to retry */
2646 reg = FDI_TX_CTL(pipe);
2647 temp = I915_READ(reg);
2648 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2649 temp &= ~FDI_TX_ENABLE;
2650 I915_WRITE(reg, temp);
357555c0 2651
139ccd3f
JB		 2652 reg = FDI_RX_CTL(pipe);
2653 temp = I915_READ(reg);
2654 temp &= ~FDI_LINK_TRAIN_AUTO;
2655 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2656 temp &= ~FDI_RX_ENABLE;
2657 I915_WRITE(reg, temp);
357555c0 2658
139ccd3f 2659 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 2660 reg = FDI_TX_CTL(pipe);
2661 temp = I915_READ(reg);
139ccd3f
JB		 2662 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2663 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2664 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 2665 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 2666 temp |= snb_b_fdi_train_param[j/2];
2667 temp |= FDI_COMPOSITE_SYNC;
2668 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 2669
139ccd3f
JB		 2670 I915_WRITE(FDI_RX_MISC(pipe),
2671 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 2672
139ccd3f 2673 reg = FDI_RX_CTL(pipe);
357555c0 2674 temp = I915_READ(reg);
139ccd3f
JB		 2675 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2676 temp |= FDI_COMPOSITE_SYNC;
2677 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 2678
139ccd3f
JB		 2679 POSTING_READ(reg);
2680 udelay(1); /* should be 0.5us */
357555c0 2681
139ccd3f
JB		 2682 for (i = 0; i < 4; i++) {
2683 reg = FDI_RX_IIR(pipe);
2684 temp = I915_READ(reg);
2685 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2686
139ccd3f
JB		 2687 if (temp & FDI_RX_BIT_LOCK ||
2688 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2689 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2690 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2691 i);
2692 break;
2693 }
2694 udelay(1); /* should be 0.5us */
2695 }
2696 if (i == 4) {
2697 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2698 continue;
2699 }
357555c0 2700
139ccd3f 2701 /* Train 2 */
357555c0
JB		 2702 reg = FDI_TX_CTL(pipe);
2703 temp = I915_READ(reg);
139ccd3f
JB		 2704 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2705 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2706 I915_WRITE(reg, temp);
2707
2708 reg = FDI_RX_CTL(pipe);
2709 temp = I915_READ(reg);
2710 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2711 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 2712 I915_WRITE(reg, temp);
2713
2714 POSTING_READ(reg);
139ccd3f 2715 udelay(2); /* should be 1.5us */
357555c0 2716
139ccd3f
JB		 2717 for (i = 0; i < 4; i++) {
2718 reg = FDI_RX_IIR(pipe);
2719 temp = I915_READ(reg);
2720 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2721
139ccd3f
JB		 2722 if (temp & FDI_RX_SYMBOL_LOCK ||
2723 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2724 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2725 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2726 i);
2727 goto train_done;
2728 }
2729 udelay(2); /* should be 1.5us */
357555c0 2730 }
139ccd3f
JB		 2731 if (i == 4)
2732 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 2733 }
357555c0 2734
139ccd3f 2735train_done:
357555c0
JB		 2736 DRM_DEBUG_KMS("FDI train done.\n");
2737}
2738
88cefb6c 2739static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2740{
88cefb6c 2741 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2742 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2743 int pipe = intel_crtc->pipe;
5eddb70b 2744 u32 reg, temp;
79e53945 2745
c64e311e 2746
c98e9dcf 2747 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2748 reg = FDI_RX_CTL(pipe);
2749 temp = I915_READ(reg);
627eb5a3
DV		 2750 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2751 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2752 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2753 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2754
2755 POSTING_READ(reg);
c98e9dcf
JB		 2756 udelay(200);
2757
2758 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2759 temp = I915_READ(reg);
2760 I915_WRITE(reg, temp | FDI_PCDCLK);
2761
2762 POSTING_READ(reg);
c98e9dcf
JB		 2763 udelay(200);
2764
20749730
PZ		 2765 /* Enable CPU FDI TX PLL, always on for Ironlake */
2766 reg = FDI_TX_CTL(pipe);
2767 temp = I915_READ(reg);
2768 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2769 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2770
20749730
PZ		 2771 POSTING_READ(reg);
2772 udelay(100);
6be4a607 2773 }
0e23b99d
JB		 2774}
2775
88cefb6c
DV		 2776static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2777{
2778 struct drm_device *dev = intel_crtc->base.dev;
2779 struct drm_i915_private *dev_priv = dev->dev_private;
2780 int pipe = intel_crtc->pipe;
2781 u32 reg, temp;
2782
2783 /* Switch from PCDclk to Rawclk */
2784 reg = FDI_RX_CTL(pipe);
2785 temp = I915_READ(reg);
2786 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2787
2788 /* Disable CPU FDI TX PLL */
2789 reg = FDI_TX_CTL(pipe);
2790 temp = I915_READ(reg);
2791 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2792
2793 POSTING_READ(reg);
2794 udelay(100);
2795
2796 reg = FDI_RX_CTL(pipe);
2797 temp = I915_READ(reg);
2798 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2799
2800 /* Wait for the clocks to turn off. */
2801 POSTING_READ(reg);
2802 udelay(100);
2803}
2804
0fc932b8
JB		 2805static void ironlake_fdi_disable(struct drm_crtc *crtc)
2806{
2807 struct drm_device *dev = crtc->dev;
2808 struct drm_i915_private *dev_priv = dev->dev_private;
2809 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2810 int pipe = intel_crtc->pipe;
2811 u32 reg, temp;
2812
2813 /* disable CPU FDI tx and PCH FDI rx */
2814 reg = FDI_TX_CTL(pipe);
2815 temp = I915_READ(reg);
2816 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2817 POSTING_READ(reg);
2818
2819 reg = FDI_RX_CTL(pipe);
2820 temp = I915_READ(reg);
2821 temp &= ~(0x7 << 16);
dfd07d72 2822 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2823 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2824
2825 POSTING_READ(reg);
2826 udelay(100);
2827
2828 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2829 if (HAS_PCH_IBX(dev)) {
2830 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2831 }
0fc932b8
JB		 2832
2833 /* still set train pattern 1 */
2834 reg = FDI_TX_CTL(pipe);
2835 temp = I915_READ(reg);
2836 temp &= ~FDI_LINK_TRAIN_NONE;
2837 temp |= FDI_LINK_TRAIN_PATTERN_1;
2838 I915_WRITE(reg, temp);
2839
2840 reg = FDI_RX_CTL(pipe);
2841 temp = I915_READ(reg);
2842 if (HAS_PCH_CPT(dev)) {
2843 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2844 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2845 } else {
2846 temp &= ~FDI_LINK_TRAIN_NONE;
2847 temp |= FDI_LINK_TRAIN_PATTERN_1;
2848 }
2849 /* BPC in FDI rx is consistent with that in PIPECONF */
2850 temp &= ~(0x07 << 16);
dfd07d72 2851 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2852 I915_WRITE(reg, temp);
2853
2854 POSTING_READ(reg);
2855 udelay(100);
2856}
2857
5bb61643
CW		 2858static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2859{
2860 struct drm_device *dev = crtc->dev;
2861 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2862 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2863 unsigned long flags;
2864 bool pending;
2865
10d83730
VS		 2866 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2867 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2868 return false;
2869
2870 spin_lock_irqsave(&dev->event_lock, flags);
2871 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2872 spin_unlock_irqrestore(&dev->event_lock, flags);
2873
2874 return pending;
2875}
2876
e6c3a2a6
CW		 2877static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2878{
0f91128d 2879 struct drm_device *dev = crtc->dev;
5bb61643 2880 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2881
2882 if (crtc->fb == NULL)
2883 return;
2884
2c10d571
DV		 2885 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2886
5bb61643
CW		 2887 wait_event(dev_priv->pending_flip_queue,
2888 !intel_crtc_has_pending_flip(crtc));
2889
0f91128d
CW		 2890 mutex_lock(&dev->struct_mutex);
2891 intel_finish_fb(crtc->fb);
2892 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2893}
2894
e615efe4
ED		 2895/* Program iCLKIP clock to the desired frequency */
2896static void lpt_program_iclkip(struct drm_crtc *crtc)
2897{
2898 struct drm_device *dev = crtc->dev;
2899 struct drm_i915_private *dev_priv = dev->dev_private;
12d7ceed 2900 int clock = to_intel_crtc(crtc)->config.adjusted_mode.clock;
e615efe4
ED		 2901 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2902 u32 temp;
2903
09153000
DV		 2904 mutex_lock(&dev_priv->dpio_lock);
2905
e615efe4
ED		 2906 /* It is necessary to ungate the pixclk gate prior to programming
2907 * the divisors, and gate it back when it is done.
2908 */
2909 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2910
2911 /* Disable SSCCTL */
2912 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2913 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2914 SBI_SSCCTL_DISABLE,
2915 SBI_ICLK);
e615efe4
ED		 2916
2917 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 2918 if (clock == 20000) {
e615efe4
ED		 2919 auxdiv = 1;
2920 divsel = 0x41;
2921 phaseinc = 0x20;
2922 } else {
2923 /* The iCLK virtual clock root frequency is in MHz,
12d7ceed 2924 * but the adjusted_mode->clock in in KHz. To get the divisors,
e615efe4
ED		 2925 * it is necessary to divide one by another, so we
2926 * convert the virtual clock precision to KHz here for higher
2927 * precision.
2928 */
2929 u32 iclk_virtual_root_freq = 172800 * 1000;
2930 u32 iclk_pi_range = 64;
2931 u32 desired_divisor, msb_divisor_value, pi_value;
2932
12d7ceed 2933 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 2934 msb_divisor_value = desired_divisor / iclk_pi_range;
2935 pi_value = desired_divisor % iclk_pi_range;
2936
2937 auxdiv = 0;
2938 divsel = msb_divisor_value - 2;
2939 phaseinc = pi_value;
2940 }
2941
2942 /* This should not happen with any sane values */
2943 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2944 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2945 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2946 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2947
2948 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 2949 clock,
e615efe4
ED		 2950 auxdiv,
2951 divsel,
2952 phasedir,
2953 phaseinc);
2954
2955 /* Program SSCDIVINTPHASE6 */
988d6ee8 2956 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2957 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2958 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2959 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2960 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2961 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2962 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2963 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2964
2965 /* Program SSCAUXDIV */
988d6ee8 2966 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2967 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2968 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2969 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2970
2971 /* Enable modulator and associated divider */
988d6ee8 2972 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2973 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2974 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2975
2976 /* Wait for initialization time */
2977 udelay(24);
2978
2979 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2980
2981 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2982}
2983
275f01b2
DV		 2984static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2985 enum pipe pch_transcoder)
2986{
2987 struct drm_device *dev = crtc->base.dev;
2988 struct drm_i915_private *dev_priv = dev->dev_private;
2989 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2990
2991 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2992 I915_READ(HTOTAL(cpu_transcoder)));
2993 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2994 I915_READ(HBLANK(cpu_transcoder)));
2995 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2996 I915_READ(HSYNC(cpu_transcoder)));
2997
2998 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2999 I915_READ(VTOTAL(cpu_transcoder)));
3000 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3001 I915_READ(VBLANK(cpu_transcoder)));
3002 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3003 I915_READ(VSYNC(cpu_transcoder)));
3004 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3005 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3006}
3007
f67a559d
JB		 3008/*
3009 * Enable PCH resources required for PCH ports:
3010 * - PCH PLLs
3011 * - FDI training & RX/TX
3012 * - update transcoder timings
3013 * - DP transcoding bits
3014 * - transcoder
3015 */
3016static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3017{
3018 struct drm_device *dev = crtc->dev;
3019 struct drm_i915_private *dev_priv = dev->dev_private;
3020 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3021 int pipe = intel_crtc->pipe;
ee7b9f93 3022 u32 reg, temp;
2c07245f 3023
ab9412ba 3024 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 3025
cd986abb
DV		 3026 /* Write the TU size bits before fdi link training, so that error
3027 * detection works. */
3028 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3029 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3030
c98e9dcf 3031 /* For PCH output, training FDI link */
674cf967 3032 dev_priv->display.fdi_link_train(crtc);
2c07245f 3033
3ad8a208
DV		 3034 /* We need to program the right clock selection before writing the pixel
3035 * mutliplier into the DPLL. */
303b81e0 3036 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3037 u32 sel;
4b645f14 3038
c98e9dcf 3039 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 3040 temp |= TRANS_DPLL_ENABLE(pipe);
3041 sel = TRANS_DPLLB_SEL(pipe);
a43f6e0f 3042 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 3043 temp |= sel;
3044 else
3045 temp &= ~sel;
c98e9dcf 3046 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3047 }
5eddb70b 3048
3ad8a208
DV		 3049 /* XXX: pch pll's can be enabled any time before we enable the PCH
3050 * transcoder, and we actually should do this to not upset any PCH
3051 * transcoder that already use the clock when we share it.
3052 *
3053 * Note that enable_shared_dpll tries to do the right thing, but
3054 * get_shared_dpll unconditionally resets the pll - we need that to have
3055 * the right LVDS enable sequence. */
3056 ironlake_enable_shared_dpll(intel_crtc);
3057
d9b6cb56
JB		 3058 /* set transcoder timing, panel must allow it */
3059 assert_panel_unlocked(dev_priv, pipe);
275f01b2 3060 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 3061
303b81e0 3062 intel_fdi_normal_train(crtc);
5e84e1a4 3063
c98e9dcf
JB		 3064 /* For PCH DP, enable TRANS_DP_CTL */
3065 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3066 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3067 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3068 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3069 reg = TRANS_DP_CTL(pipe);
3070 temp = I915_READ(reg);
3071 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3072 TRANS_DP_SYNC_MASK |
3073 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3074 temp |= (TRANS_DP_OUTPUT_ENABLE |
3075 TRANS_DP_ENH_FRAMING);
9325c9f0 3076 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3077
3078 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3079 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3080 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3081 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3082
3083 switch (intel_trans_dp_port_sel(crtc)) {
3084 case PCH_DP_B:
5eddb70b 3085 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3086 break;
3087 case PCH_DP_C:
5eddb70b 3088 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3089 break;
3090 case PCH_DP_D:
5eddb70b 3091 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3092 break;
3093 default:
e95d41e1 3094 BUG();
32f9d658 3095 }
2c07245f 3096
5eddb70b 3097 I915_WRITE(reg, temp);
6be4a607 3098 }
b52eb4dc 3099
b8a4f404 3100 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3101}
3102
1507e5bd
PZ		 3103static void lpt_pch_enable(struct drm_crtc *crtc)
3104{
3105 struct drm_device *dev = crtc->dev;
3106 struct drm_i915_private *dev_priv = dev->dev_private;
3107 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3108 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3109
ab9412ba 3110 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3111
8c52b5e8 3112 lpt_program_iclkip(crtc);
1507e5bd 3113
0540e488 3114 /* Set transcoder timing. */
275f01b2 3115 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3116
937bb610 3117 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3118}
3119
e2b78267 3120static void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3121{
e2b78267 3122 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 3123
3124 if (pll == NULL)
3125 return;
3126
3127 if (pll->refcount == 0) {
46edb027 3128 WARN(1, "bad %s refcount\n", pll->name);
ee7b9f93
JB		 3129 return;
3130 }
3131
f4a091c7
DV		 3132 if (--pll->refcount == 0) {
3133 WARN_ON(pll->on);
3134 WARN_ON(pll->active);
3135 }
3136
a43f6e0f 3137 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 3138}
3139
b89a1d39 3140static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3141{
e2b78267
DV		 3142 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3143 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3144 enum intel_dpll_id i;
ee7b9f93 3145
ee7b9f93 3146 if (pll) {
46edb027
DV		 3147 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3148 crtc->base.base.id, pll->name);
e2b78267 3149 intel_put_shared_dpll(crtc);
ee7b9f93
JB		 3150 }
3151
98b6bd99
DV		 3152 if (HAS_PCH_IBX(dev_priv->dev)) {
3153 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 3154 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 3155 pll = &dev_priv->shared_dplls[i];
98b6bd99 3156
46edb027
DV		 3157 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3158 crtc->base.base.id, pll->name);
98b6bd99
DV		 3159
3160 goto found;
3161 }
3162
e72f9fbf
DV		 3163 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3164 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 3165
3166 /* Only want to check enabled timings first */
3167 if (pll->refcount == 0)
3168 continue;
3169
b89a1d39
DV		 3170 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3171 sizeof(pll->hw_state)) == 0) {
46edb027 3172 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
e2b78267 3173 crtc->base.base.id,
46edb027 3174 pll->name, pll->refcount, pll->active);
ee7b9f93
JB		 3175
3176 goto found;
3177 }
3178 }
3179
3180 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 3181 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3182 pll = &dev_priv->shared_dplls[i];
ee7b9f93 3183 if (pll->refcount == 0) {
46edb027
DV		 3184 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3185 crtc->base.base.id, pll->name);
ee7b9f93
JB		 3186 goto found;
3187 }
3188 }
3189
3190 return NULL;
3191
3192found:
a43f6e0f 3193 crtc->config.shared_dpll = i;
46edb027
DV		 3194 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3195 pipe_name(crtc->pipe));
ee7b9f93 3196
cdbd2316 3197 if (pll->active == 0) {
66e985c0
DV		 3198 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3199 sizeof(pll->hw_state));
3200
46edb027 3201 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
cdbd2316 3202 WARN_ON(pll->on);
e9d6944e 3203 assert_shared_dpll_disabled(dev_priv, pll);
ee7b9f93 3204
15bdd4cf 3205 pll->mode_set(dev_priv, pll);
cdbd2316
DV		 3206 }
3207 pll->refcount++;
e04c7350 3208
ee7b9f93
JB		 3209 return pll;
3210}
3211
a1520318 3212static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3213{
3214 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3215 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3216 u32 temp;
3217
3218 temp = I915_READ(dslreg);
3219 udelay(500);
3220 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3221 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3222 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3223 }
3224}
3225
b074cec8
JB		 3226static void ironlake_pfit_enable(struct intel_crtc *crtc)
3227{
3228 struct drm_device *dev = crtc->base.dev;
3229 struct drm_i915_private *dev_priv = dev->dev_private;
3230 int pipe = crtc->pipe;
3231
0ef37f3f 3232 if (crtc->config.pch_pfit.size) {
b074cec8
JB		 3233 /* Force use of hard-coded filter coefficients
3234 * as some pre-programmed values are broken,
3235 * e.g. x201.
3236 */
3237 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3238 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3239 PF_PIPE_SEL_IVB(pipe));
3240 else
3241 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3242 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3243 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
d4270e57
JB		 3244 }
3245}
3246
bb53d4ae
VS		 3247static void intel_enable_planes(struct drm_crtc *crtc)
3248{
3249 struct drm_device *dev = crtc->dev;
3250 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3251 struct intel_plane *intel_plane;
3252
3253 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3254 if (intel_plane->pipe == pipe)
3255 intel_plane_restore(&intel_plane->base);
3256}
3257
3258static void intel_disable_planes(struct drm_crtc *crtc)
3259{
3260 struct drm_device *dev = crtc->dev;
3261 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3262 struct intel_plane *intel_plane;
3263
3264 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3265 if (intel_plane->pipe == pipe)
3266 intel_plane_disable(&intel_plane->base);
3267}
3268
f67a559d
JB		 3269static void ironlake_crtc_enable(struct drm_crtc *crtc)
3270{
3271 struct drm_device *dev = crtc->dev;
3272 struct drm_i915_private *dev_priv = dev->dev_private;
3273 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3274 struct intel_encoder *encoder;
f67a559d
JB		 3275 int pipe = intel_crtc->pipe;
3276 int plane = intel_crtc->plane;
f67a559d 3277
08a48469
DV		 3278 WARN_ON(!crtc->enabled);
3279
f67a559d
JB		 3280 if (intel_crtc->active)
3281 return;
3282
3283 intel_crtc->active = true;
8664281b
PZ		 3284
3285 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3286 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3287
f6736a1a 3288 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 3289 if (encoder->pre_enable)
3290 encoder->pre_enable(encoder);
f67a559d 3291
5bfe2ac0 3292 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3293 /* Note: FDI PLL enabling _must_ be done before we enable the
3294 * cpu pipes, hence this is separate from all the other fdi/pch
3295 * enabling. */
88cefb6c 3296 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3297 } else {
3298 assert_fdi_tx_disabled(dev_priv, pipe);
3299 assert_fdi_rx_disabled(dev_priv, pipe);
3300 }
f67a559d 3301
b074cec8 3302 ironlake_pfit_enable(intel_crtc);
f67a559d 3303
9c54c0dd
JB		 3304 /*
3305 * On ILK+ LUT must be loaded before the pipe is running but with
3306 * clocks enabled
3307 */
3308 intel_crtc_load_lut(crtc);
3309
f37fcc2a 3310 intel_update_watermarks(crtc);
5bfe2ac0 3311 intel_enable_pipe(dev_priv, pipe,
23538ef1 3312 intel_crtc->config.has_pch_encoder, false);
f67a559d 3313 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3314 intel_enable_planes(crtc);
5c38d48c 3315 intel_crtc_update_cursor(crtc, true);
f67a559d 3316
5bfe2ac0 3317 if (intel_crtc->config.has_pch_encoder)
f67a559d 3318 ironlake_pch_enable(crtc);
c98e9dcf 3319
d1ebd816 3320 mutex_lock(&dev->struct_mutex);
bed4a673 3321 intel_update_fbc(dev);
d1ebd816
BW		 3322 mutex_unlock(&dev->struct_mutex);
3323
fa5c73b1
DV		 3324 for_each_encoder_on_crtc(dev, crtc, encoder)
3325 encoder->enable(encoder);
61b77ddd
DV		 3326
3327 if (HAS_PCH_CPT(dev))
a1520318 3328 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3329
3330 /*
3331 * There seems to be a race in PCH platform hw (at least on some
3332 * outputs) where an enabled pipe still completes any pageflip right
3333 * away (as if the pipe is off) instead of waiting for vblank. As soon
3334 * as the first vblank happend, everything works as expected. Hence just
3335 * wait for one vblank before returning to avoid strange things
3336 * happening.
3337 */
3338 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3339}
3340
42db64ef
PZ		 3341/* IPS only exists on ULT machines and is tied to pipe A. */
3342static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3343{
f5adf94e 3344 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 3345}
3346
3347static void hsw_enable_ips(struct intel_crtc *crtc)
3348{
3349 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3350
3351 if (!crtc->config.ips_enabled)
3352 return;
3353
3354 /* We can only enable IPS after we enable a plane and wait for a vblank.
3355 * We guarantee that the plane is enabled by calling intel_enable_ips
3356 * only after intel_enable_plane. And intel_enable_plane already waits
3357 * for a vblank, so all we need to do here is to enable the IPS bit. */
3358 assert_plane_enabled(dev_priv, crtc->plane);
3359 I915_WRITE(IPS_CTL, IPS_ENABLE);
3360}
3361
3362static void hsw_disable_ips(struct intel_crtc *crtc)
3363{
3364 struct drm_device *dev = crtc->base.dev;
3365 struct drm_i915_private *dev_priv = dev->dev_private;
3366
3367 if (!crtc->config.ips_enabled)
3368 return;
3369
3370 assert_plane_enabled(dev_priv, crtc->plane);
3371 I915_WRITE(IPS_CTL, 0);
3372
3373 /* We need to wait for a vblank before we can disable the plane. */
3374 intel_wait_for_vblank(dev, crtc->pipe);
3375}
3376
4f771f10
PZ		 3377static void haswell_crtc_enable(struct drm_crtc *crtc)
3378{
3379 struct drm_device *dev = crtc->dev;
3380 struct drm_i915_private *dev_priv = dev->dev_private;
3381 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3382 struct intel_encoder *encoder;
3383 int pipe = intel_crtc->pipe;
3384 int plane = intel_crtc->plane;
4f771f10
PZ		 3385
3386 WARN_ON(!crtc->enabled);
3387
3388 if (intel_crtc->active)
3389 return;
3390
3391 intel_crtc->active = true;
8664281b
PZ		 3392
3393 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3394 if (intel_crtc->config.has_pch_encoder)
3395 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3396
5bfe2ac0 3397 if (intel_crtc->config.has_pch_encoder)
04945641 3398 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3399
3400 for_each_encoder_on_crtc(dev, crtc, encoder)
3401 if (encoder->pre_enable)
3402 encoder->pre_enable(encoder);
3403
1f544388 3404 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3405
b074cec8 3406 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3407
3408 /*
3409 * On ILK+ LUT must be loaded before the pipe is running but with
3410 * clocks enabled
3411 */
3412 intel_crtc_load_lut(crtc);
3413
1f544388 3414 intel_ddi_set_pipe_settings(crtc);
8228c251 3415 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3416
f37fcc2a 3417 intel_update_watermarks(crtc);
5bfe2ac0 3418 intel_enable_pipe(dev_priv, pipe,
23538ef1 3419 intel_crtc->config.has_pch_encoder, false);
4f771f10 3420 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3421 intel_enable_planes(crtc);
5c38d48c 3422 intel_crtc_update_cursor(crtc, true);
4f771f10 3423
42db64ef
PZ		 3424 hsw_enable_ips(intel_crtc);
3425
5bfe2ac0 3426 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3427 lpt_pch_enable(crtc);
4f771f10
PZ		 3428
3429 mutex_lock(&dev->struct_mutex);
3430 intel_update_fbc(dev);
3431 mutex_unlock(&dev->struct_mutex);
3432
8807e55b 3433 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 3434 encoder->enable(encoder);
8807e55b
JN		 3435 intel_opregion_notify_encoder(encoder, true);
3436 }
4f771f10 3437
4f771f10
PZ		 3438 /*
3439 * There seems to be a race in PCH platform hw (at least on some
3440 * outputs) where an enabled pipe still completes any pageflip right
3441 * away (as if the pipe is off) instead of waiting for vblank. As soon
3442 * as the first vblank happend, everything works as expected. Hence just
3443 * wait for one vblank before returning to avoid strange things
3444 * happening.
3445 */
3446 intel_wait_for_vblank(dev, intel_crtc->pipe);
3447}
3448
3f8dce3a
DV		 3449static void ironlake_pfit_disable(struct intel_crtc *crtc)
3450{
3451 struct drm_device *dev = crtc->base.dev;
3452 struct drm_i915_private *dev_priv = dev->dev_private;
3453 int pipe = crtc->pipe;
3454
3455 /* To avoid upsetting the power well on haswell only disable the pfit if
3456 * it's in use. The hw state code will make sure we get this right. */
3457 if (crtc->config.pch_pfit.size) {
3458 I915_WRITE(PF_CTL(pipe), 0);
3459 I915_WRITE(PF_WIN_POS(pipe), 0);
3460 I915_WRITE(PF_WIN_SZ(pipe), 0);
3461 }
3462}
3463
6be4a607
JB		 3464static void ironlake_crtc_disable(struct drm_crtc *crtc)
3465{
3466 struct drm_device *dev = crtc->dev;
3467 struct drm_i915_private *dev_priv = dev->dev_private;
3468 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3469 struct intel_encoder *encoder;
6be4a607
JB		 3470 int pipe = intel_crtc->pipe;
3471 int plane = intel_crtc->plane;
5eddb70b 3472 u32 reg, temp;
b52eb4dc 3473
ef9c3aee 3474
f7abfe8b
CW		 3475 if (!intel_crtc->active)
3476 return;
3477
ea9d758d
DV		 3478 for_each_encoder_on_crtc(dev, crtc, encoder)
3479 encoder->disable(encoder);
3480
e6c3a2a6 3481 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3482 drm_vblank_off(dev, pipe);
913d8d11 3483
5c3fe8b0 3484 if (dev_priv->fbc.plane == plane)
973d04f9 3485 intel_disable_fbc(dev);
2c07245f 3486
0d5b8c61 3487 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3488 intel_disable_planes(crtc);
0d5b8c61
VS		 3489 intel_disable_plane(dev_priv, plane, pipe);
3490
d925c59a
DV		 3491 if (intel_crtc->config.has_pch_encoder)
3492 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3493
b24e7179 3494 intel_disable_pipe(dev_priv, pipe);
32f9d658 3495
3f8dce3a 3496 ironlake_pfit_disable(intel_crtc);
2c07245f 3497
bf49ec8c
DV		 3498 for_each_encoder_on_crtc(dev, crtc, encoder)
3499 if (encoder->post_disable)
3500 encoder->post_disable(encoder);
2c07245f 3501
d925c59a
DV		 3502 if (intel_crtc->config.has_pch_encoder) {
3503 ironlake_fdi_disable(crtc);
913d8d11 3504
d925c59a
DV		 3505 ironlake_disable_pch_transcoder(dev_priv, pipe);
3506 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
6be4a607 3507
d925c59a
DV		 3508 if (HAS_PCH_CPT(dev)) {
3509 /* disable TRANS_DP_CTL */
3510 reg = TRANS_DP_CTL(pipe);
3511 temp = I915_READ(reg);
3512 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3513 TRANS_DP_PORT_SEL_MASK);
3514 temp |= TRANS_DP_PORT_SEL_NONE;
3515 I915_WRITE(reg, temp);
3516
3517 /* disable DPLL_SEL */
3518 temp = I915_READ(PCH_DPLL_SEL);
11887397 3519 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 3520 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 3521 }
e3421a18 3522
d925c59a 3523 /* disable PCH DPLL */
e72f9fbf 3524 intel_disable_shared_dpll(intel_crtc);
8db9d77b 3525
d925c59a
DV		 3526 ironlake_fdi_pll_disable(intel_crtc);
3527 }
6b383a7f 3528
f7abfe8b 3529 intel_crtc->active = false;
46ba614c 3530 intel_update_watermarks(crtc);
d1ebd816
BW		 3531
3532 mutex_lock(&dev->struct_mutex);
6b383a7f 3533 intel_update_fbc(dev);
d1ebd816 3534 mutex_unlock(&dev->struct_mutex);
6be4a607 3535}
1b3c7a47 3536
4f771f10 3537static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3538{
4f771f10
PZ		 3539 struct drm_device *dev = crtc->dev;
3540 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3541 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3542 struct intel_encoder *encoder;
3543 int pipe = intel_crtc->pipe;
3544 int plane = intel_crtc->plane;
3b117c8f 3545 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3546
4f771f10
PZ		 3547 if (!intel_crtc->active)
3548 return;
3549
8807e55b
JN		 3550 for_each_encoder_on_crtc(dev, crtc, encoder) {
3551 intel_opregion_notify_encoder(encoder, false);
4f771f10 3552 encoder->disable(encoder);
8807e55b 3553 }
4f771f10
PZ		 3554
3555 intel_crtc_wait_for_pending_flips(crtc);
3556 drm_vblank_off(dev, pipe);
4f771f10 3557
891348b2 3558 /* FBC must be disabled before disabling the plane on HSW. */
5c3fe8b0 3559 if (dev_priv->fbc.plane == plane)
4f771f10
PZ		 3560 intel_disable_fbc(dev);
3561
42db64ef
PZ		 3562 hsw_disable_ips(intel_crtc);
3563
0d5b8c61 3564 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3565 intel_disable_planes(crtc);
891348b2
RV		 3566 intel_disable_plane(dev_priv, plane, pipe);
3567
8664281b
PZ		 3568 if (intel_crtc->config.has_pch_encoder)
3569 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3570 intel_disable_pipe(dev_priv, pipe);
3571
ad80a810 3572 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3573
3f8dce3a 3574 ironlake_pfit_disable(intel_crtc);
4f771f10 3575
1f544388 3576 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3577
3578 for_each_encoder_on_crtc(dev, crtc, encoder)
3579 if (encoder->post_disable)
3580 encoder->post_disable(encoder);
3581
88adfff1 3582 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3583 lpt_disable_pch_transcoder(dev_priv);
8664281b 3584 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3585 intel_ddi_fdi_disable(crtc);
83616634 3586 }
4f771f10
PZ		 3587
3588 intel_crtc->active = false;
46ba614c 3589 intel_update_watermarks(crtc);
4f771f10
PZ		 3590
3591 mutex_lock(&dev->struct_mutex);
3592 intel_update_fbc(dev);
3593 mutex_unlock(&dev->struct_mutex);
3594}
3595
ee7b9f93
JB		 3596static void ironlake_crtc_off(struct drm_crtc *crtc)
3597{
3598 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 3599 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 3600}
3601
6441ab5f
PZ		 3602static void haswell_crtc_off(struct drm_crtc *crtc)
3603{
3604 intel_ddi_put_crtc_pll(crtc);
3605}
3606
02e792fb
DV		 3607static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3608{
02e792fb 3609 if (!enable && intel_crtc->overlay) {
23f09ce3 3610 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3611 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3612
23f09ce3 3613 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3614 dev_priv->mm.interruptible = false;
3615 (void) intel_overlay_switch_off(intel_crtc->overlay);
3616 dev_priv->mm.interruptible = true;
23f09ce3 3617 mutex_unlock(&dev->struct_mutex);
02e792fb 3618 }
02e792fb 3619
5dcdbcb0
CW		 3620 /* Let userspace switch the overlay on again. In most cases userspace
3621 * has to recompute where to put it anyway.
3622 */
02e792fb
DV		 3623}
3624
61bc95c1
EE		 3625/**
3626 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3627 * cursor plane briefly if not already running after enabling the display
3628 * plane.
3629 * This workaround avoids occasional blank screens when self refresh is
3630 * enabled.
3631 */
3632static void
3633g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3634{
3635 u32 cntl = I915_READ(CURCNTR(pipe));
3636
3637 if ((cntl & CURSOR_MODE) == 0) {
3638 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3639
3640 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3641 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3642 intel_wait_for_vblank(dev_priv->dev, pipe);
3643 I915_WRITE(CURCNTR(pipe), cntl);
3644 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3645 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3646 }
3647}
3648
2dd24552
JB		 3649static void i9xx_pfit_enable(struct intel_crtc *crtc)
3650{
3651 struct drm_device *dev = crtc->base.dev;
3652 struct drm_i915_private *dev_priv = dev->dev_private;
3653 struct intel_crtc_config *pipe_config = &crtc->config;
3654
328d8e82 3655 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3656 return;
3657
2dd24552 3658 /*
c0b03411
DV		 3659 * The panel fitter should only be adjusted whilst the pipe is disabled,
3660 * according to register description and PRM.
2dd24552 3661 */
c0b03411
DV		 3662 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3663 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3664
b074cec8
JB		 3665 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3666 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3667
3668 /* Border color in case we don't scale up to the full screen. Black by
3669 * default, change to something else for debugging. */
3670 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3671}
3672
89b667f8
JB		 3673static void valleyview_crtc_enable(struct drm_crtc *crtc)
3674{
3675 struct drm_device *dev = crtc->dev;
3676 struct drm_i915_private *dev_priv = dev->dev_private;
3677 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3678 struct intel_encoder *encoder;
3679 int pipe = intel_crtc->pipe;
3680 int plane = intel_crtc->plane;
23538ef1 3681 bool is_dsi;
89b667f8
JB		 3682
3683 WARN_ON(!crtc->enabled);
3684
3685 if (intel_crtc->active)
3686 return;
3687
3688 intel_crtc->active = true;
89b667f8 3689
89b667f8
JB		 3690 for_each_encoder_on_crtc(dev, crtc, encoder)
3691 if (encoder->pre_pll_enable)
3692 encoder->pre_pll_enable(encoder);
3693
23538ef1
JN		 3694 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
3695
e9fd1c02
JN		 3696 if (!is_dsi)
3697 vlv_enable_pll(intel_crtc);
89b667f8
JB		 3698
3699 for_each_encoder_on_crtc(dev, crtc, encoder)
3700 if (encoder->pre_enable)
3701 encoder->pre_enable(encoder);
3702
2dd24552
JB		 3703 i9xx_pfit_enable(intel_crtc);
3704
63cbb074
VS		 3705 intel_crtc_load_lut(crtc);
3706
f37fcc2a 3707 intel_update_watermarks(crtc);
23538ef1 3708 intel_enable_pipe(dev_priv, pipe, false, is_dsi);
89b667f8 3709 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3710 intel_enable_planes(crtc);
5c38d48c 3711 intel_crtc_update_cursor(crtc, true);
89b667f8 3712
89b667f8 3713 intel_update_fbc(dev);
5004945f
JN		 3714
3715 for_each_encoder_on_crtc(dev, crtc, encoder)
3716 encoder->enable(encoder);
89b667f8
JB		 3717}
3718
0b8765c6 3719static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3720{
3721 struct drm_device *dev = crtc->dev;
79e53945
JB		 3722 struct drm_i915_private *dev_priv = dev->dev_private;
3723 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3724 struct intel_encoder *encoder;
79e53945 3725 int pipe = intel_crtc->pipe;
80824003 3726 int plane = intel_crtc->plane;
79e53945 3727
08a48469
DV		 3728 WARN_ON(!crtc->enabled);
3729
f7abfe8b
CW		 3730 if (intel_crtc->active)
3731 return;
3732
3733 intel_crtc->active = true;
6b383a7f 3734
9d6d9f19
MK		 3735 for_each_encoder_on_crtc(dev, crtc, encoder)
3736 if (encoder->pre_enable)
3737 encoder->pre_enable(encoder);
3738
f6736a1a
DV		 3739 i9xx_enable_pll(intel_crtc);
3740
2dd24552
JB		 3741 i9xx_pfit_enable(intel_crtc);
3742
63cbb074
VS		 3743 intel_crtc_load_lut(crtc);
3744
f37fcc2a 3745 intel_update_watermarks(crtc);
23538ef1 3746 intel_enable_pipe(dev_priv, pipe, false, false);
b24e7179 3747 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3748 intel_enable_planes(crtc);
22e407d7 3749 /* The fixup needs to happen before cursor is enabled */
61bc95c1
EE		 3750 if (IS_G4X(dev))
3751 g4x_fixup_plane(dev_priv, pipe);
22e407d7 3752 intel_crtc_update_cursor(crtc, true);
79e53945 3753
0b8765c6
JB		 3754 /* Give the overlay scaler a chance to enable if it's on this pipe */
3755 intel_crtc_dpms_overlay(intel_crtc, true);
ef9c3aee 3756
f440eb13 3757 intel_update_fbc(dev);
ef9c3aee 3758
fa5c73b1
DV		 3759 for_each_encoder_on_crtc(dev, crtc, encoder)
3760 encoder->enable(encoder);
0b8765c6 3761}
79e53945 3762
87476d63
DV		 3763static void i9xx_pfit_disable(struct intel_crtc *crtc)
3764{
3765 struct drm_device *dev = crtc->base.dev;
3766 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3767
328d8e82
DV		 3768 if (!crtc->config.gmch_pfit.control)
3769 return;
87476d63 3770
328d8e82 3771 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3772
328d8e82
DV		 3773 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3774 I915_READ(PFIT_CONTROL));
3775 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3776}
3777
0b8765c6
JB		 3778static void i9xx_crtc_disable(struct drm_crtc *crtc)
3779{
3780 struct drm_device *dev = crtc->dev;
3781 struct drm_i915_private *dev_priv = dev->dev_private;
3782 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3783 struct intel_encoder *encoder;
0b8765c6
JB		 3784 int pipe = intel_crtc->pipe;
3785 int plane = intel_crtc->plane;
ef9c3aee 3786
f7abfe8b
CW		 3787 if (!intel_crtc->active)
3788 return;
3789
ea9d758d
DV		 3790 for_each_encoder_on_crtc(dev, crtc, encoder)
3791 encoder->disable(encoder);
3792
0b8765c6 3793 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3794 intel_crtc_wait_for_pending_flips(crtc);
3795 drm_vblank_off(dev, pipe);
0b8765c6 3796
5c3fe8b0 3797 if (dev_priv->fbc.plane == plane)
973d04f9 3798 intel_disable_fbc(dev);
79e53945 3799
0d5b8c61
VS		 3800 intel_crtc_dpms_overlay(intel_crtc, false);
3801 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3802 intel_disable_planes(crtc);
b24e7179 3803 intel_disable_plane(dev_priv, plane, pipe);
0d5b8c61 3804
b24e7179 3805 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3806
87476d63 3807 i9xx_pfit_disable(intel_crtc);
24a1f16d 3808
89b667f8
JB		 3809 for_each_encoder_on_crtc(dev, crtc, encoder)
3810 if (encoder->post_disable)
3811 encoder->post_disable(encoder);
3812
e9fd1c02
JN		 3813 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3814 i9xx_disable_pll(dev_priv, pipe);
0b8765c6 3815
f7abfe8b 3816 intel_crtc->active = false;
46ba614c 3817 intel_update_watermarks(crtc);
f37fcc2a
VS		 3818
3819 intel_update_fbc(dev);
0b8765c6
JB		 3820}
3821
ee7b9f93
JB		 3822static void i9xx_crtc_off(struct drm_crtc *crtc)
3823{
3824}
3825
976f8a20
DV		 3826static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3827 bool enabled)
2c07245f
ZW		 3828{
3829 struct drm_device *dev = crtc->dev;
3830 struct drm_i915_master_private *master_priv;
3831 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3832 int pipe = intel_crtc->pipe;
79e53945
JB		 3833
3834 if (!dev->primary->master)
3835 return;
3836
3837 master_priv = dev->primary->master->driver_priv;
3838 if (!master_priv->sarea_priv)
3839 return;
3840
79e53945
JB		 3841 switch (pipe) {
3842 case 0:
3843 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3844 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3845 break;
3846 case 1:
3847 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3848 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3849 break;
3850 default:
9db4a9c7 3851 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3852 break;
3853 }
79e53945
JB		 3854}
3855
976f8a20
DV		 3856/**
3857 * Sets the power management mode of the pipe and plane.
3858 */
3859void intel_crtc_update_dpms(struct drm_crtc *crtc)
3860{
3861 struct drm_device *dev = crtc->dev;
3862 struct drm_i915_private *dev_priv = dev->dev_private;
3863 struct intel_encoder *intel_encoder;
3864 bool enable = false;
3865
3866 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3867 enable |= intel_encoder->connectors_active;
3868
3869 if (enable)
3870 dev_priv->display.crtc_enable(crtc);
3871 else
3872 dev_priv->display.crtc_disable(crtc);
3873
3874 intel_crtc_update_sarea(crtc, enable);
3875}
3876
cdd59983
CW		 3877static void intel_crtc_disable(struct drm_crtc *crtc)
3878{
cdd59983 3879 struct drm_device *dev = crtc->dev;
976f8a20 3880 struct drm_connector *connector;
ee7b9f93 3881 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3882 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3883
976f8a20
DV		 3884 /* crtc should still be enabled when we disable it. */
3885 WARN_ON(!crtc->enabled);
3886
3887 dev_priv->display.crtc_disable(crtc);
c77bf565 3888 intel_crtc->eld_vld = false;
976f8a20 3889 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3890 dev_priv->display.off(crtc);
3891
931872fc 3892 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
93ce0ba6 3893 assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
931872fc 3894 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3895
3896 if (crtc->fb) {
3897 mutex_lock(&dev->struct_mutex);
1690e1eb 3898 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3899 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3900 crtc->fb = NULL;
3901 }
3902
3903 /* Update computed state. */
3904 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3905 if (!connector->encoder || !connector->encoder->crtc)
3906 continue;
3907
3908 if (connector->encoder->crtc != crtc)
3909 continue;
3910
3911 connector->dpms = DRM_MODE_DPMS_OFF;
3912 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3913 }
3914}
3915
ea5b213a 3916void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3917{
4ef69c7a 3918 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3919
ea5b213a
CW		 3920 drm_encoder_cleanup(encoder);
3921 kfree(intel_encoder);
7e7d76c3
JB		 3922}
3923
9237329d 3924/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 3925 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3926 * state of the entire output pipe. */
9237329d 3927static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3928{
5ab432ef
DV		 3929 if (mode == DRM_MODE_DPMS_ON) {
3930 encoder->connectors_active = true;
3931
b2cabb0e 3932 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3933 } else {
3934 encoder->connectors_active = false;
3935
b2cabb0e 3936 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3937 }
79e53945
JB		 3938}
3939
0a91ca29
DV		 3940/* Cross check the actual hw state with our own modeset state tracking (and it's
3941 * internal consistency). */
b980514c 3942static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3943{
0a91ca29
DV		 3944 if (connector->get_hw_state(connector)) {
3945 struct intel_encoder *encoder = connector->encoder;
3946 struct drm_crtc *crtc;
3947 bool encoder_enabled;
3948 enum pipe pipe;
3949
3950 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3951 connector->base.base.id,
3952 drm_get_connector_name(&connector->base));
3953
3954 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3955 "wrong connector dpms state\n");
3956 WARN(connector->base.encoder != &encoder->base,
3957 "active connector not linked to encoder\n");
3958 WARN(!encoder->connectors_active,
3959 "encoder->connectors_active not set\n");
3960
3961 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3962 WARN(!encoder_enabled, "encoder not enabled\n");
3963 if (WARN_ON(!encoder->base.crtc))
3964 return;
3965
3966 crtc = encoder->base.crtc;
3967
3968 WARN(!crtc->enabled, "crtc not enabled\n");
3969 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3970 WARN(pipe != to_intel_crtc(crtc)->pipe,
3971 "encoder active on the wrong pipe\n");
3972 }
79e53945
JB		 3973}
3974
5ab432ef
DV		 3975/* Even simpler default implementation, if there's really no special case to
3976 * consider. */
3977void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3978{
5ab432ef 3979 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3980
5ab432ef
DV		 3981 /* All the simple cases only support two dpms states. */
3982 if (mode != DRM_MODE_DPMS_ON)
3983 mode = DRM_MODE_DPMS_OFF;
d4270e57 3984
5ab432ef
DV		 3985 if (mode == connector->dpms)
3986 return;
3987
3988 connector->dpms = mode;
3989
3990 /* Only need to change hw state when actually enabled */
3991 if (encoder->base.crtc)
3992 intel_encoder_dpms(encoder, mode);
3993 else
8af6cf88 3994 WARN_ON(encoder->connectors_active != false);
0a91ca29 3995
b980514c 3996 intel_modeset_check_state(connector->dev);
79e53945
JB		 3997}
3998
f0947c37
DV		 3999/* Simple connector->get_hw_state implementation for encoders that support only
4000 * one connector and no cloning and hence the encoder state determines the state
4001 * of the connector. */
4002bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 4003{
24929352 4004 enum pipe pipe = 0;
f0947c37 4005 struct intel_encoder *encoder = connector->encoder;
ea5b213a 4006
f0947c37 4007 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 4008}
4009
1857e1da
DV		 4010static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4011 struct intel_crtc_config *pipe_config)
4012{
4013 struct drm_i915_private *dev_priv = dev->dev_private;
4014 struct intel_crtc *pipe_B_crtc =
4015 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4016
4017 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4018 pipe_name(pipe), pipe_config->fdi_lanes);
4019 if (pipe_config->fdi_lanes > 4) {
4020 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4021 pipe_name(pipe), pipe_config->fdi_lanes);
4022 return false;
4023 }
4024
4025 if (IS_HASWELL(dev)) {
4026 if (pipe_config->fdi_lanes > 2) {
4027 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4028 pipe_config->fdi_lanes);
4029 return false;
4030 } else {
4031 return true;
4032 }
4033 }
4034
4035 if (INTEL_INFO(dev)->num_pipes == 2)
4036 return true;
4037
4038 /* Ivybridge 3 pipe is really complicated */
4039 switch (pipe) {
4040 case PIPE_A:
4041 return true;
4042 case PIPE_B:
4043 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4044 pipe_config->fdi_lanes > 2) {
4045 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4046 pipe_name(pipe), pipe_config->fdi_lanes);
4047 return false;
4048 }
4049 return true;
4050 case PIPE_C:
1e833f40 4051 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 4052 pipe_B_crtc->config.fdi_lanes <= 2) {
4053 if (pipe_config->fdi_lanes > 2) {
4054 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4055 pipe_name(pipe), pipe_config->fdi_lanes);
4056 return false;
4057 }
4058 } else {
4059 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4060 return false;
4061 }
4062 return true;
4063 default:
4064 BUG();
4065 }
4066}
4067
e29c22c0
DV		 4068#define RETRY 1
4069static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4070 struct intel_crtc_config *pipe_config)
877d48d5 4071{
1857e1da 4072 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 4073 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 4074 int lane, link_bw, fdi_dotclock;
e29c22c0 4075 bool setup_ok, needs_recompute = false;
877d48d5 4076
e29c22c0 4077retry:
877d48d5
DV		 4078 /* FDI is a binary signal running at ~2.7GHz, encoding
4079 * each output octet as 10 bits. The actual frequency
4080 * is stored as a divider into a 100MHz clock, and the
4081 * mode pixel clock is stored in units of 1KHz.
4082 * Hence the bw of each lane in terms of the mode signal
4083 * is:
4084 */
4085 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4086
ff9a6750 4087 fdi_dotclock = adjusted_mode->clock;
877d48d5 4088
2bd89a07 4089 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 4090 pipe_config->pipe_bpp);
4091
4092 pipe_config->fdi_lanes = lane;
4093
2bd89a07 4094 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4095 link_bw, &pipe_config->fdi_m_n);
1857e1da 4096
e29c22c0
DV		 4097 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4098 intel_crtc->pipe, pipe_config);
4099 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4100 pipe_config->pipe_bpp -= 2*3;
4101 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4102 pipe_config->pipe_bpp);
4103 needs_recompute = true;
4104 pipe_config->bw_constrained = true;
4105
4106 goto retry;
4107 }
4108
4109 if (needs_recompute)
4110 return RETRY;
4111
4112 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4113}
4114
42db64ef
PZ		 4115static void hsw_compute_ips_config(struct intel_crtc *crtc,
4116 struct intel_crtc_config *pipe_config)
4117{
3c4ca58c
PZ		 4118 pipe_config->ips_enabled = i915_enable_ips &&
4119 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 4120 pipe_config->pipe_bpp <= 24;
42db64ef
PZ		 4121}
4122
a43f6e0f 4123static int intel_crtc_compute_config(struct intel_crtc *crtc,
e29c22c0 4124 struct intel_crtc_config *pipe_config)
79e53945 4125{
a43f6e0f 4126 struct drm_device *dev = crtc->base.dev;
b8cecdf5 4127 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4128
8693a824
DL		 4129 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4130 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4131 */
4132 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4133 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4134 return -EINVAL;
44f46b42 4135
bd080ee5 4136 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4137 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4138 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4139 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4140 * for lvds. */
4141 pipe_config->pipe_bpp = 8*3;
4142 }
4143
f5adf94e 4144 if (HAS_IPS(dev))
a43f6e0f
DV		 4145 hsw_compute_ips_config(crtc, pipe_config);
4146
4147 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4148 * clock survives for now. */
4149 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4150 pipe_config->shared_dpll = crtc->config.shared_dpll;
42db64ef 4151
877d48d5 4152 if (pipe_config->has_pch_encoder)
a43f6e0f 4153 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 4154
e29c22c0 4155 return 0;
79e53945
JB		 4156}
4157
25eb05fc
JB		 4158static int valleyview_get_display_clock_speed(struct drm_device *dev)
4159{
4160 return 400000; /* FIXME */
4161}
4162
e70236a8
JB		 4163static int i945_get_display_clock_speed(struct drm_device *dev)
4164{
4165 return 400000;
4166}
79e53945 4167
e70236a8 4168static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4169{
e70236a8
JB		 4170 return 333000;
4171}
79e53945 4172
e70236a8
JB		 4173static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4174{
4175 return 200000;
4176}
79e53945 4177
257a7ffc
DV		 4178static int pnv_get_display_clock_speed(struct drm_device *dev)
4179{
4180 u16 gcfgc = 0;
4181
4182 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4183
4184 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4185 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4186 return 267000;
4187 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4188 return 333000;
4189 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4190 return 444000;
4191 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4192 return 200000;
4193 default:
4194 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4195 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4196 return 133000;
4197 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4198 return 167000;
4199 }
4200}
4201
e70236a8
JB		 4202static int i915gm_get_display_clock_speed(struct drm_device *dev)
4203{
4204 u16 gcfgc = 0;
79e53945 4205
e70236a8
JB		 4206 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4207
4208 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4209 return 133000;
4210 else {
4211 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4212 case GC_DISPLAY_CLOCK_333_MHZ:
4213 return 333000;
4214 default:
4215 case GC_DISPLAY_CLOCK_190_200_MHZ:
4216 return 190000;
79e53945 4217 }
e70236a8
JB		 4218 }
4219}
4220
4221static int i865_get_display_clock_speed(struct drm_device *dev)
4222{
4223 return 266000;
4224}
4225
4226static int i855_get_display_clock_speed(struct drm_device *dev)
4227{
4228 u16 hpllcc = 0;
4229 /* Assume that the hardware is in the high speed state. This
4230 * should be the default.
4231 */
4232 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4233 case GC_CLOCK_133_200:
4234 case GC_CLOCK_100_200:
4235 return 200000;
4236 case GC_CLOCK_166_250:
4237 return 250000;
4238 case GC_CLOCK_100_133:
79e53945 4239 return 133000;
e70236a8 4240 }
79e53945 4241
e70236a8
JB		 4242 /* Shouldn't happen */
4243 return 0;
4244}
79e53945 4245
e70236a8
JB		 4246static int i830_get_display_clock_speed(struct drm_device *dev)
4247{
4248 return 133000;
79e53945
JB		 4249}
4250
2c07245f 4251static void
a65851af 4252intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4253{
a65851af
VS		 4254 while (*num > DATA_LINK_M_N_MASK ||
4255 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4256 *num >>= 1;
4257 *den >>= 1;
4258 }
4259}
4260
a65851af
VS		 4261static void compute_m_n(unsigned int m, unsigned int n,
4262 uint32_t *ret_m, uint32_t *ret_n)
4263{
4264 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4265 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4266 intel_reduce_m_n_ratio(ret_m, ret_n);
4267}
4268
e69d0bc1
DV		 4269void
4270intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4271 int pixel_clock, int link_clock,
4272 struct intel_link_m_n *m_n)
2c07245f 4273{
e69d0bc1 4274 m_n->tu = 64;
a65851af
VS		 4275
4276 compute_m_n(bits_per_pixel * pixel_clock,
4277 link_clock * nlanes * 8,
4278 &m_n->gmch_m, &m_n->gmch_n);
4279
4280 compute_m_n(pixel_clock, link_clock,
4281 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4282}
4283
a7615030
CW		 4284static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4285{
72bbe58c
KP		 4286 if (i915_panel_use_ssc >= 0)
4287 return i915_panel_use_ssc != 0;
41aa3448 4288 return dev_priv->vbt.lvds_use_ssc
435793df 4289 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4290}
4291
a0c4da24
JB		 4292static int vlv_get_refclk(struct drm_crtc *crtc)
4293{
4294 struct drm_device *dev = crtc->dev;
4295 struct drm_i915_private *dev_priv = dev->dev_private;
4296 int refclk = 27000; /* for DP & HDMI */
4297
4298 return 100000; /* only one validated so far */
4299
4300 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4301 refclk = 96000;
4302 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4303 if (intel_panel_use_ssc(dev_priv))
4304 refclk = 100000;
4305 else
4306 refclk = 96000;
4307 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4308 refclk = 100000;
4309 }
4310
4311 return refclk;
4312}
4313
c65d77d8
JB		 4314static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4315{
4316 struct drm_device *dev = crtc->dev;
4317 struct drm_i915_private *dev_priv = dev->dev_private;
4318 int refclk;
4319
a0c4da24
JB		 4320 if (IS_VALLEYVIEW(dev)) {
4321 refclk = vlv_get_refclk(crtc);
4322 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4323 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4324 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4325 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4326 refclk / 1000);
4327 } else if (!IS_GEN2(dev)) {
4328 refclk = 96000;
4329 } else {
4330 refclk = 48000;
4331 }
4332
4333 return refclk;
4334}
4335
7429e9d4 4336static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 4337{
7df00d7a 4338 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 4339}
f47709a9 4340
7429e9d4
DV		 4341static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4342{
4343 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 4344}
4345
f47709a9 4346static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4347 intel_clock_t *reduced_clock)
4348{
f47709a9 4349 struct drm_device *dev = crtc->base.dev;
a7516a05 4350 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4351 int pipe = crtc->pipe;
a7516a05
JB		 4352 u32 fp, fp2 = 0;
4353
4354 if (IS_PINEVIEW(dev)) {
7429e9d4 4355 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4356 if (reduced_clock)
7429e9d4 4357 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4358 } else {
7429e9d4 4359 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4360 if (reduced_clock)
7429e9d4 4361 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4362 }
4363
4364 I915_WRITE(FP0(pipe), fp);
8bcc2795 4365 crtc->config.dpll_hw_state.fp0 = fp;
a7516a05 4366
f47709a9
DV		 4367 crtc->lowfreq_avail = false;
4368 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4369 reduced_clock && i915_powersave) {
4370 I915_WRITE(FP1(pipe), fp2);
8bcc2795 4371 crtc->config.dpll_hw_state.fp1 = fp2;
f47709a9 4372 crtc->lowfreq_avail = true;
a7516a05
JB		 4373 } else {
4374 I915_WRITE(FP1(pipe), fp);
8bcc2795 4375 crtc->config.dpll_hw_state.fp1 = fp;
a7516a05
JB		 4376 }
4377}
4378
5e69f97f
CML		 4379static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4380 pipe)
89b667f8
JB		 4381{
4382 u32 reg_val;
4383
4384 /*
4385 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4386 * and set it to a reasonable value instead.
4387 */
5e69f97f 4388 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
89b667f8
JB		 4389 reg_val &= 0xffffff00;
4390 reg_val |= 0x00000030;
5e69f97f 4391 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
89b667f8 4392
5e69f97f 4393 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
89b667f8
JB		 4394 reg_val &= 0x8cffffff;
4395 reg_val = 0x8c000000;
5e69f97f 4396 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
89b667f8 4397
5e69f97f 4398 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
89b667f8 4399 reg_val &= 0xffffff00;
5e69f97f 4400 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
89b667f8 4401
5e69f97f 4402 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
89b667f8
JB		 4403 reg_val &= 0x00ffffff;
4404 reg_val |= 0xb0000000;
5e69f97f 4405 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4406}
4407
b551842d
DV		 4408static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4409 struct intel_link_m_n *m_n)
4410{
4411 struct drm_device *dev = crtc->base.dev;
4412 struct drm_i915_private *dev_priv = dev->dev_private;
4413 int pipe = crtc->pipe;
4414
e3b95f1e
DV		 4415 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4416 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4417 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4418 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4419}
4420
4421static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4422 struct intel_link_m_n *m_n)
4423{
4424 struct drm_device *dev = crtc->base.dev;
4425 struct drm_i915_private *dev_priv = dev->dev_private;
4426 int pipe = crtc->pipe;
4427 enum transcoder transcoder = crtc->config.cpu_transcoder;
4428
4429 if (INTEL_INFO(dev)->gen >= 5) {
4430 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4431 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4432 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4433 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4434 } else {
e3b95f1e
DV		 4435 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4436 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4437 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4438 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4439 }
4440}
4441
03afc4a2
DV		 4442static void intel_dp_set_m_n(struct intel_crtc *crtc)
4443{
4444 if (crtc->config.has_pch_encoder)
4445 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4446 else
4447 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4448}
4449
f47709a9 4450static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4451{
f47709a9 4452 struct drm_device *dev = crtc->base.dev;
a0c4da24 4453 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4454 int pipe = crtc->pipe;
89b667f8 4455 u32 dpll, mdiv;
a0c4da24 4456 u32 bestn, bestm1, bestm2, bestp1, bestp2;
198a037f 4457 u32 coreclk, reg_val, dpll_md;
a0c4da24 4458
09153000
DV		 4459 mutex_lock(&dev_priv->dpio_lock);
4460
f47709a9
DV		 4461 bestn = crtc->config.dpll.n;
4462 bestm1 = crtc->config.dpll.m1;
4463 bestm2 = crtc->config.dpll.m2;
4464 bestp1 = crtc->config.dpll.p1;
4465 bestp2 = crtc->config.dpll.p2;
a0c4da24 4466
89b667f8
JB		 4467 /* See eDP HDMI DPIO driver vbios notes doc */
4468
4469 /* PLL B needs special handling */
4470 if (pipe)
5e69f97f 4471 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 4472
4473 /* Set up Tx target for periodic Rcomp update */
5e69f97f 4474 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4475
4476 /* Disable target IRef on PLL */
5e69f97f 4477 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe));
89b667f8 4478 reg_val &= 0x00ffffff;
5e69f97f 4479 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4480
4481 /* Disable fast lock */
5e69f97f 4482 vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4483
4484 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4485 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4486 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4487 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4488 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4489
4490 /*
4491 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4492 * but we don't support that).
4493 * Note: don't use the DAC post divider as it seems unstable.
4494 */
4495 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5e69f97f 4496 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
a0c4da24 4497
a0c4da24 4498 mdiv |= DPIO_ENABLE_CALIBRATION;
5e69f97f 4499 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
a0c4da24 4500
89b667f8 4501 /* Set HBR and RBR LPF coefficients */
ff9a6750 4502 if (crtc->config.port_clock == 162000 ||
99750bd4 4503 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
89b667f8 4504 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5e69f97f 4505 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
885b0120 4506 0x009f0003);
89b667f8 4507 else
5e69f97f 4508 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
89b667f8
JB		 4509 0x00d0000f);
4510
4511 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4512 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4513 /* Use SSC source */
4514 if (!pipe)
5e69f97f 4515 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4516 0x0df40000);
4517 else
5e69f97f 4518 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4519 0x0df70000);
4520 } else { /* HDMI or VGA */
4521 /* Use bend source */
4522 if (!pipe)
5e69f97f 4523 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4524 0x0df70000);
4525 else
5e69f97f 4526 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4527 0x0df40000);
4528 }
a0c4da24 4529
5e69f97f 4530 coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4531 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4532 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4533 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4534 coreclk |= 0x01000000;
5e69f97f 4535 vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4536
5e69f97f 4537 vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4538
89b667f8
JB		 4539 /* Enable DPIO clock input */
4540 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4541 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4542 if (pipe)
4543 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
a0c4da24
JB		 4544
4545 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4546 crtc->config.dpll_hw_state.dpll = dpll;
4547
ef1b460d
DV		 4548 dpll_md = (crtc->config.pixel_multiplier - 1)
4549 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795
DV		 4550 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4551
89b667f8
JB		 4552 if (crtc->config.has_dp_encoder)
4553 intel_dp_set_m_n(crtc);
09153000
DV		 4554
4555 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4556}
4557
f47709a9
DV		 4558static void i9xx_update_pll(struct intel_crtc *crtc,
4559 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4560 int num_connectors)
4561{
f47709a9 4562 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4563 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 4564 u32 dpll;
4565 bool is_sdvo;
f47709a9 4566 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4567
f47709a9 4568 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4569
f47709a9
DV		 4570 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4571 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4572
4573 dpll = DPLL_VGA_MODE_DIS;
4574
f47709a9 4575 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4576 dpll |= DPLLB_MODE_LVDS;
4577 else
4578 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4579
ef1b460d 4580 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
198a037f
DV		 4581 dpll |= (crtc->config.pixel_multiplier - 1)
4582 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4583 }
198a037f
DV		 4584
4585 if (is_sdvo)
4a33e48d 4586 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 4587
f47709a9 4588 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4a33e48d 4589 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 4590
4591 /* compute bitmask from p1 value */
4592 if (IS_PINEVIEW(dev))
4593 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4594 else {
4595 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4596 if (IS_G4X(dev) && reduced_clock)
4597 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4598 }
4599 switch (clock->p2) {
4600 case 5:
4601 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4602 break;
4603 case 7:
4604 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4605 break;
4606 case 10:
4607 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4608 break;
4609 case 14:
4610 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4611 break;
4612 }
4613 if (INTEL_INFO(dev)->gen >= 4)
4614 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4615
09ede541 4616 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4617 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4618 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4619 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4620 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4621 else
4622 dpll |= PLL_REF_INPUT_DREFCLK;
4623
4624 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4625 crtc->config.dpll_hw_state.dpll = dpll;
4626
eb1cbe48 4627 if (INTEL_INFO(dev)->gen >= 4) {
ef1b460d
DV		 4628 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4629 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795 4630 crtc->config.dpll_hw_state.dpll_md = dpll_md;
eb1cbe48 4631 }
66e3d5c0
DV		 4632
4633 if (crtc->config.has_dp_encoder)
4634 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4635}
4636
f47709a9 4637static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 4638 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4639 int num_connectors)
4640{
f47709a9 4641 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4642 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 4643 u32 dpll;
f47709a9 4644 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4645
f47709a9 4646 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4647
eb1cbe48
DV		 4648 dpll = DPLL_VGA_MODE_DIS;
4649
f47709a9 4650 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4651 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4652 } else {
4653 if (clock->p1 == 2)
4654 dpll |= PLL_P1_DIVIDE_BY_TWO;
4655 else
4656 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4657 if (clock->p2 == 4)
4658 dpll |= PLL_P2_DIVIDE_BY_4;
4659 }
4660
4a33e48d
DV		 4661 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4662 dpll |= DPLL_DVO_2X_MODE;
4663
f47709a9 4664 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4665 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4666 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4667 else
4668 dpll |= PLL_REF_INPUT_DREFCLK;
4669
4670 dpll |= DPLL_VCO_ENABLE;
8bcc2795 4671 crtc->config.dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 4672}
4673
8a654f3b 4674static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 4675{
4676 struct drm_device *dev = intel_crtc->base.dev;
4677 struct drm_i915_private *dev_priv = dev->dev_private;
4678 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4679 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV		 4680 struct drm_display_mode *adjusted_mode =
4681 &intel_crtc->config.adjusted_mode;
4682 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4d8a62ea
DV		 4683 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4684
4685 /* We need to be careful not to changed the adjusted mode, for otherwise
4686 * the hw state checker will get angry at the mismatch. */
4687 crtc_vtotal = adjusted_mode->crtc_vtotal;
4688 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4689
4690 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4691 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4692 crtc_vtotal -= 1;
4693 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4694 vsyncshift = adjusted_mode->crtc_hsync_start
4695 - adjusted_mode->crtc_htotal / 2;
4696 } else {
4697 vsyncshift = 0;
4698 }
4699
4700 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4701 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4702
fe2b8f9d 4703 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4704 (adjusted_mode->crtc_hdisplay - 1) |
4705 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4706 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4707 (adjusted_mode->crtc_hblank_start - 1) |
4708 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4709 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4710 (adjusted_mode->crtc_hsync_start - 1) |
4711 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4712
fe2b8f9d 4713 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4714 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4715 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4716 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4717 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4718 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4719 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4720 (adjusted_mode->crtc_vsync_start - 1) |
4721 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4722
b5e508d4
PZ		 4723 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4724 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4725 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4726 * bits. */
4727 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4728 (pipe == PIPE_B || pipe == PIPE_C))
4729 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4730
b0e77b9c
PZ		 4731 /* pipesrc controls the size that is scaled from, which should
4732 * always be the user's requested size.
4733 */
4734 I915_WRITE(PIPESRC(pipe),
4735 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4736}
4737
1bd1bd80
DV		 4738static void intel_get_pipe_timings(struct intel_crtc *crtc,
4739 struct intel_crtc_config *pipe_config)
4740{
4741 struct drm_device *dev = crtc->base.dev;
4742 struct drm_i915_private *dev_priv = dev->dev_private;
4743 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4744 uint32_t tmp;
4745
4746 tmp = I915_READ(HTOTAL(cpu_transcoder));
4747 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4748 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4749 tmp = I915_READ(HBLANK(cpu_transcoder));
4750 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4751 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4752 tmp = I915_READ(HSYNC(cpu_transcoder));
4753 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4754 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4755
4756 tmp = I915_READ(VTOTAL(cpu_transcoder));
4757 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4758 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4759 tmp = I915_READ(VBLANK(cpu_transcoder));
4760 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4761 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4762 tmp = I915_READ(VSYNC(cpu_transcoder));
4763 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4764 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4765
4766 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4767 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4768 pipe_config->adjusted_mode.crtc_vtotal += 1;
4769 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4770 }
4771
4772 tmp = I915_READ(PIPESRC(crtc->pipe));
4773 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4774 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4775}
4776
babea61d
JB		 4777static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4778 struct intel_crtc_config *pipe_config)
4779{
4780 struct drm_crtc *crtc = &intel_crtc->base;
4781
4782 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4783 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4784 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4785 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4786
4787 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4788 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4789 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4790 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4791
4792 crtc->mode.flags = pipe_config->adjusted_mode.flags;
4793
4794 crtc->mode.clock = pipe_config->adjusted_mode.clock;
4795 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4796}
4797
84b046f3
DV		 4798static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4799{
4800 struct drm_device *dev = intel_crtc->base.dev;
4801 struct drm_i915_private *dev_priv = dev->dev_private;
4802 uint32_t pipeconf;
4803
9f11a9e4 4804 pipeconf = 0;
84b046f3
DV		 4805
4806 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4807 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4808 * core speed.
4809 *
4810 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4811 * pipe == 0 check?
4812 */
a2b076b6 4813 if (intel_crtc->config.adjusted_mode.clock >
84b046f3
DV		 4814 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4815 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3
DV		 4816 }
4817
ff9ce46e
DV		 4818 /* only g4x and later have fancy bpc/dither controls */
4819 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e
DV		 4820 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4821 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4822 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4823 PIPECONF_DITHER_TYPE_SP;
84b046f3 4824
ff9ce46e
DV		 4825 switch (intel_crtc->config.pipe_bpp) {
4826 case 18:
4827 pipeconf |= PIPECONF_6BPC;
4828 break;
4829 case 24:
4830 pipeconf |= PIPECONF_8BPC;
4831 break;
4832 case 30:
4833 pipeconf |= PIPECONF_10BPC;
4834 break;
4835 default:
4836 /* Case prevented by intel_choose_pipe_bpp_dither. */
4837 BUG();
84b046f3
DV		 4838 }
4839 }
4840
4841 if (HAS_PIPE_CXSR(dev)) {
4842 if (intel_crtc->lowfreq_avail) {
4843 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4844 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4845 } else {
4846 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 4847 }
4848 }
4849
84b046f3
DV		 4850 if (!IS_GEN2(dev) &&
4851 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4852 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4853 else
4854 pipeconf |= PIPECONF_PROGRESSIVE;
4855
9f11a9e4
DV		 4856 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4857 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 4858
84b046f3
DV		 4859 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4860 POSTING_READ(PIPECONF(intel_crtc->pipe));
4861}
4862
f564048e 4863static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4864 int x, int y,
94352cf9 4865 struct drm_framebuffer *fb)
79e53945
JB		 4866{
4867 struct drm_device *dev = crtc->dev;
4868 struct drm_i915_private *dev_priv = dev->dev_private;
4869 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 4870 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4871 int pipe = intel_crtc->pipe;
80824003 4872 int plane = intel_crtc->plane;
c751ce4f 4873 int refclk, num_connectors = 0;
652c393a 4874 intel_clock_t clock, reduced_clock;
84b046f3 4875 u32 dspcntr;
a16af721 4876 bool ok, has_reduced_clock = false;
e9fd1c02 4877 bool is_lvds = false, is_dsi = false;
5eddb70b 4878 struct intel_encoder *encoder;
d4906093 4879 const intel_limit_t *limit;
5c3b82e2 4880 int ret;
79e53945 4881
6c2b7c12 4882 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4883 switch (encoder->type) {
79e53945
JB		 4884 case INTEL_OUTPUT_LVDS:
4885 is_lvds = true;
4886 break;
e9fd1c02
JN		 4887 case INTEL_OUTPUT_DSI:
4888 is_dsi = true;
4889 break;
79e53945 4890 }
43565a06 4891
c751ce4f 4892 num_connectors++;
79e53945
JB		 4893 }
4894
c65d77d8 4895 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4896
65ce4bf5 4897 if (!is_dsi && !intel_crtc->config.clock_set) {
e9fd1c02
JN		 4898 /*
4899 * Returns a set of divisors for the desired target clock with
4900 * the given refclk, or FALSE. The returned values represent
4901 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
4902 * 2) / p1 / p2.
4903 */
4904 limit = intel_limit(crtc, refclk);
4905 ok = dev_priv->display.find_dpll(limit, crtc,
4906 intel_crtc->config.port_clock,
4907 refclk, NULL, &clock);
4908 if (!ok && !intel_crtc->config.clock_set) {
4909 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4910 return -EINVAL;
4911 }
79e53945
JB		 4912 }
4913
cda4b7d3 4914 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4915 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4916
e9fd1c02 4917 if (!is_dsi && is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4918 /*
4919 * Ensure we match the reduced clock's P to the target clock.
4920 * If the clocks don't match, we can't switch the display clock
4921 * by using the FP0/FP1. In such case we will disable the LVDS
4922 * downclock feature.
4923 */
65ce4bf5 4924 limit = intel_limit(crtc, refclk);
ee9300bb
DV		 4925 has_reduced_clock =
4926 dev_priv->display.find_dpll(limit, crtc,
5eddb70b 4927 dev_priv->lvds_downclock,
ee9300bb 4928 refclk, &clock,
5eddb70b 4929 &reduced_clock);
7026d4ac 4930 }
f47709a9
DV		 4931 /* Compat-code for transition, will disappear. */
4932 if (!intel_crtc->config.clock_set) {
4933 intel_crtc->config.dpll.n = clock.n;
4934 intel_crtc->config.dpll.m1 = clock.m1;
4935 intel_crtc->config.dpll.m2 = clock.m2;
4936 intel_crtc->config.dpll.p1 = clock.p1;
4937 intel_crtc->config.dpll.p2 = clock.p2;
4938 }
7026d4ac 4939
e9fd1c02 4940 if (IS_GEN2(dev)) {
8a654f3b 4941 i8xx_update_pll(intel_crtc,
2a8f64ca
VP		 4942 has_reduced_clock ? &reduced_clock : NULL,
4943 num_connectors);
e9fd1c02
JN		 4944 } else if (IS_VALLEYVIEW(dev)) {
4945 if (!is_dsi)
4946 vlv_update_pll(intel_crtc);
4947 } else {
f47709a9 4948 i9xx_update_pll(intel_crtc,
eb1cbe48 4949 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4950 num_connectors);
e9fd1c02 4951 }
79e53945 4952
79e53945
JB		 4953 /* Set up the display plane register */
4954 dspcntr = DISPPLANE_GAMMA_ENABLE;
4955
da6ecc5d
JB		 4956 if (!IS_VALLEYVIEW(dev)) {
4957 if (pipe == 0)
4958 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4959 else
4960 dspcntr |= DISPPLANE_SEL_PIPE_B;
4961 }
79e53945 4962
8a654f3b 4963 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW		 4964
4965 /* pipesrc and dspsize control the size that is scaled from,
4966 * which should always be the user's requested size.
79e53945 4967 */
929c77fb
EA		 4968 I915_WRITE(DSPSIZE(plane),
4969 ((mode->vdisplay - 1) << 16) |
4970 (mode->hdisplay - 1));
4971 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4972
84b046f3
DV		 4973 i9xx_set_pipeconf(intel_crtc);
4974
f564048e
EA		 4975 I915_WRITE(DSPCNTR(plane), dspcntr);
4976 POSTING_READ(DSPCNTR(plane));
4977
94352cf9 4978 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e 4979
f564048e
EA		 4980 return ret;
4981}
4982
2fa2fe9a
DV		 4983static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4984 struct intel_crtc_config *pipe_config)
4985{
4986 struct drm_device *dev = crtc->base.dev;
4987 struct drm_i915_private *dev_priv = dev->dev_private;
4988 uint32_t tmp;
4989
4990 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 4991 if (!(tmp & PFIT_ENABLE))
4992 return;
2fa2fe9a 4993
06922821 4994 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 4995 if (INTEL_INFO(dev)->gen < 4) {
4996 if (crtc->pipe != PIPE_B)
4997 return;
2fa2fe9a
DV		 4998 } else {
4999 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5000 return;
5001 }
5002
06922821 5003 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 5004 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5005 if (INTEL_INFO(dev)->gen < 5)
5006 pipe_config->gmch_pfit.lvds_border_bits =
5007 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5008}
5009
0e8ffe1b
DV		 5010static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5011 struct intel_crtc_config *pipe_config)
5012{
5013 struct drm_device *dev = crtc->base.dev;
5014 struct drm_i915_private *dev_priv = dev->dev_private;
5015 uint32_t tmp;
5016
e143a21c 5017 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 5018 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5019
0e8ffe1b
DV		 5020 tmp = I915_READ(PIPECONF(crtc->pipe));
5021 if (!(tmp & PIPECONF_ENABLE))
5022 return false;
5023
42571aef
VS		 5024 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5025 switch (tmp & PIPECONF_BPC_MASK) {
5026 case PIPECONF_6BPC:
5027 pipe_config->pipe_bpp = 18;
5028 break;
5029 case PIPECONF_8BPC:
5030 pipe_config->pipe_bpp = 24;
5031 break;
5032 case PIPECONF_10BPC:
5033 pipe_config->pipe_bpp = 30;
5034 break;
5035 default:
5036 break;
5037 }
5038 }
5039
1bd1bd80
DV		 5040 intel_get_pipe_timings(crtc, pipe_config);
5041
2fa2fe9a
DV		 5042 i9xx_get_pfit_config(crtc, pipe_config);
5043
6c49f241
DV		 5044 if (INTEL_INFO(dev)->gen >= 4) {
5045 tmp = I915_READ(DPLL_MD(crtc->pipe));
5046 pipe_config->pixel_multiplier =
5047 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5048 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 5049 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 5050 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5051 tmp = I915_READ(DPLL(crtc->pipe));
5052 pipe_config->pixel_multiplier =
5053 ((tmp & SDVO_MULTIPLIER_MASK)
5054 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5055 } else {
5056 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5057 * port and will be fixed up in the encoder->get_config
5058 * function. */
5059 pipe_config->pixel_multiplier = 1;
5060 }
8bcc2795
DV		 5061 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5062 if (!IS_VALLEYVIEW(dev)) {
5063 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5064 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 5065 } else {
5066 /* Mask out read-only status bits. */
5067 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5068 DPLL_PORTC_READY_MASK |
5069 DPLL_PORTB_READY_MASK);
8bcc2795 5070 }
6c49f241 5071
18442d08
VS		 5072 i9xx_crtc_clock_get(crtc, pipe_config);
5073
0e8ffe1b
DV		 5074 return true;
5075}
5076
dde86e2d 5077static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5078{
5079 struct drm_i915_private *dev_priv = dev->dev_private;
5080 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5081 struct intel_encoder *encoder;
74cfd7ac 5082 u32 val, final;
13d83a67 5083 bool has_lvds = false;
199e5d79 5084 bool has_cpu_edp = false;
199e5d79 5085 bool has_panel = false;
99eb6a01
KP		 5086 bool has_ck505 = false;
5087 bool can_ssc = false;
13d83a67
JB		 5088
5089 /* We need to take the global config into account */
199e5d79
KP		 5090 list_for_each_entry(encoder, &mode_config->encoder_list,
5091 base.head) {
5092 switch (encoder->type) {
5093 case INTEL_OUTPUT_LVDS:
5094 has_panel = true;
5095 has_lvds = true;
5096 break;
5097 case INTEL_OUTPUT_EDP:
5098 has_panel = true;
2de6905f 5099 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5100 has_cpu_edp = true;
5101 break;
13d83a67
JB		 5102 }
5103 }
5104
99eb6a01 5105 if (HAS_PCH_IBX(dev)) {
41aa3448 5106 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5107 can_ssc = has_ck505;
5108 } else {
5109 has_ck505 = false;
5110 can_ssc = true;
5111 }
5112
2de6905f
ID		 5113 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5114 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5115
5116 /* Ironlake: try to setup display ref clock before DPLL
5117 * enabling. This is only under driver's control after
5118 * PCH B stepping, previous chipset stepping should be
5119 * ignoring this setting.
5120 */
74cfd7ac
CW		 5121 val = I915_READ(PCH_DREF_CONTROL);
5122
5123 /* As we must carefully and slowly disable/enable each source in turn,
5124 * compute the final state we want first and check if we need to
5125 * make any changes at all.
5126 */
5127 final = val;
5128 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5129 if (has_ck505)
5130 final |= DREF_NONSPREAD_CK505_ENABLE;
5131 else
5132 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5133
5134 final &= ~DREF_SSC_SOURCE_MASK;
5135 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5136 final &= ~DREF_SSC1_ENABLE;
5137
5138 if (has_panel) {
5139 final |= DREF_SSC_SOURCE_ENABLE;
5140
5141 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5142 final |= DREF_SSC1_ENABLE;
5143
5144 if (has_cpu_edp) {
5145 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5146 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5147 else
5148 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5149 } else
5150 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5151 } else {
5152 final |= DREF_SSC_SOURCE_DISABLE;
5153 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5154 }
5155
5156 if (final == val)
5157 return;
5158
13d83a67 5159 /* Always enable nonspread source */
74cfd7ac 5160 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5161
99eb6a01 5162 if (has_ck505)
74cfd7ac 5163 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5164 else
74cfd7ac 5165 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5166
199e5d79 5167 if (has_panel) {
74cfd7ac
CW		 5168 val &= ~DREF_SSC_SOURCE_MASK;
5169 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5170
199e5d79 5171 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5172 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5173 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5174 val |= DREF_SSC1_ENABLE;
e77166b5 5175 } else
74cfd7ac 5176 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5177
5178 /* Get SSC going before enabling the outputs */
74cfd7ac 5179 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5180 POSTING_READ(PCH_DREF_CONTROL);
5181 udelay(200);
5182
74cfd7ac 5183 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5184
5185 /* Enable CPU source on CPU attached eDP */
199e5d79 5186 if (has_cpu_edp) {
99eb6a01 5187 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5188 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5189 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5190 }
13d83a67 5191 else
74cfd7ac 5192 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5193 } else
74cfd7ac 5194 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5195
74cfd7ac 5196 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5197 POSTING_READ(PCH_DREF_CONTROL);
5198 udelay(200);
5199 } else {
5200 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5201
74cfd7ac 5202 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5203
5204 /* Turn off CPU output */
74cfd7ac 5205 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5206
74cfd7ac 5207 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5208 POSTING_READ(PCH_DREF_CONTROL);
5209 udelay(200);
5210
5211 /* Turn off the SSC source */
74cfd7ac
CW		 5212 val &= ~DREF_SSC_SOURCE_MASK;
5213 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5214
5215 /* Turn off SSC1 */
74cfd7ac 5216 val &= ~DREF_SSC1_ENABLE;
199e5d79 5217
74cfd7ac 5218 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5219 POSTING_READ(PCH_DREF_CONTROL);
5220 udelay(200);
5221 }
74cfd7ac
CW		 5222
5223 BUG_ON(val != final);
13d83a67
JB		 5224}
5225
f31f2d55 5226static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 5227{
f31f2d55 5228 uint32_t tmp;
dde86e2d 5229
0ff066a9
PZ		 5230 tmp = I915_READ(SOUTH_CHICKEN2);
5231 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5232 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5233
0ff066a9
PZ		 5234 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5235 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5236 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 5237
0ff066a9
PZ		 5238 tmp = I915_READ(SOUTH_CHICKEN2);
5239 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5240 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5241
0ff066a9
PZ		 5242 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5243 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5244 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 5245}
5246
5247/* WaMPhyProgramming:hsw */
5248static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5249{
5250 uint32_t tmp;
dde86e2d
PZ		 5251
5252 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5253 tmp &= ~(0xFF << 24);
5254 tmp |= (0x12 << 24);
5255 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5256
dde86e2d
PZ		 5257 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5258 tmp |= (1 << 11);
5259 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5260
5261 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5262 tmp |= (1 << 11);
5263 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5264
dde86e2d
PZ		 5265 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5266 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5267 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5268
5269 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5270 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5271 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5272
0ff066a9
PZ		 5273 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5274 tmp &= ~(7 << 13);
5275 tmp |= (5 << 13);
5276 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 5277
0ff066a9
PZ		 5278 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5279 tmp &= ~(7 << 13);
5280 tmp |= (5 << 13);
5281 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 5282
5283 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5284 tmp &= ~0xFF;
5285 tmp |= 0x1C;
5286 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5287
5288 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5289 tmp &= ~0xFF;
5290 tmp |= 0x1C;
5291 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5292
5293 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5294 tmp &= ~(0xFF << 16);
5295 tmp |= (0x1C << 16);
5296 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5297
5298 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5299 tmp &= ~(0xFF << 16);
5300 tmp |= (0x1C << 16);
5301 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5302
0ff066a9
PZ		 5303 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5304 tmp |= (1 << 27);
5305 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 5306
0ff066a9
PZ		 5307 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5308 tmp |= (1 << 27);
5309 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 5310
0ff066a9
PZ		 5311 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5312 tmp &= ~(0xF << 28);
5313 tmp |= (4 << 28);
5314 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 5315
0ff066a9
PZ		 5316 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5317 tmp &= ~(0xF << 28);
5318 tmp |= (4 << 28);
5319 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 5320}
5321
2fa86a1f
PZ		 5322/* Implements 3 different sequences from BSpec chapter "Display iCLK
5323 * Programming" based on the parameters passed:
5324 * - Sequence to enable CLKOUT_DP
5325 * - Sequence to enable CLKOUT_DP without spread
5326 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5327 */
5328static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5329 bool with_fdi)
f31f2d55
PZ		 5330{
5331 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 5332 uint32_t reg, tmp;
5333
5334 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5335 with_spread = true;
5336 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5337 with_fdi, "LP PCH doesn't have FDI\n"))
5338 with_fdi = false;
f31f2d55
PZ		 5339
5340 mutex_lock(&dev_priv->dpio_lock);
5341
5342 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5343 tmp &= ~SBI_SSCCTL_DISABLE;
5344 tmp |= SBI_SSCCTL_PATHALT;
5345 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5346
5347 udelay(24);
5348
2fa86a1f
PZ		 5349 if (with_spread) {
5350 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5351 tmp &= ~SBI_SSCCTL_PATHALT;
5352 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 5353
2fa86a1f
PZ		 5354 if (with_fdi) {
5355 lpt_reset_fdi_mphy(dev_priv);
5356 lpt_program_fdi_mphy(dev_priv);
5357 }
5358 }
dde86e2d 5359
2fa86a1f
PZ		 5360 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5361 SBI_GEN0 : SBI_DBUFF0;
5362 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5363 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5364 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
DV		 5365
5366 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5367}
5368
47701c3b
PZ		 5369/* Sequence to disable CLKOUT_DP */
5370static void lpt_disable_clkout_dp(struct drm_device *dev)
5371{
5372 struct drm_i915_private *dev_priv = dev->dev_private;
5373 uint32_t reg, tmp;
5374
5375 mutex_lock(&dev_priv->dpio_lock);
5376
5377 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5378 SBI_GEN0 : SBI_DBUFF0;
5379 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5380 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5381 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5382
5383 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5384 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5385 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5386 tmp |= SBI_SSCCTL_PATHALT;
5387 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5388 udelay(32);
5389 }
5390 tmp |= SBI_SSCCTL_DISABLE;
5391 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5392 }
5393
5394 mutex_unlock(&dev_priv->dpio_lock);
5395}
5396
bf8fa3d3
PZ		 5397static void lpt_init_pch_refclk(struct drm_device *dev)
5398{
5399 struct drm_mode_config *mode_config = &dev->mode_config;
5400 struct intel_encoder *encoder;
5401 bool has_vga = false;
5402
5403 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5404 switch (encoder->type) {
5405 case INTEL_OUTPUT_ANALOG:
5406 has_vga = true;
5407 break;
5408 }
5409 }
5410
47701c3b
PZ		 5411 if (has_vga)
5412 lpt_enable_clkout_dp(dev, true, true);
5413 else
5414 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 5415}
5416
dde86e2d
PZ		 5417/*
5418 * Initialize reference clocks when the driver loads
5419 */
5420void intel_init_pch_refclk(struct drm_device *dev)
5421{
5422 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5423 ironlake_init_pch_refclk(dev);
5424 else if (HAS_PCH_LPT(dev))
5425 lpt_init_pch_refclk(dev);
5426}
5427
d9d444cb
JB		 5428static int ironlake_get_refclk(struct drm_crtc *crtc)
5429{
5430 struct drm_device *dev = crtc->dev;
5431 struct drm_i915_private *dev_priv = dev->dev_private;
5432 struct intel_encoder *encoder;
d9d444cb
JB		 5433 int num_connectors = 0;
5434 bool is_lvds = false;
5435
6c2b7c12 5436 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5437 switch (encoder->type) {
5438 case INTEL_OUTPUT_LVDS:
5439 is_lvds = true;
5440 break;
d9d444cb
JB		 5441 }
5442 num_connectors++;
5443 }
5444
5445 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5446 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5447 dev_priv->vbt.lvds_ssc_freq);
5448 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5449 }
5450
5451 return 120000;
5452}
5453
6ff93609 5454static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5455{
c8203565 5456 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5457 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5458 int pipe = intel_crtc->pipe;
c8203565
PZ		 5459 uint32_t val;
5460
78114071 5461 val = 0;
c8203565 5462
965e0c48 5463 switch (intel_crtc->config.pipe_bpp) {
c8203565 5464 case 18:
dfd07d72 5465 val |= PIPECONF_6BPC;
c8203565
PZ		 5466 break;
5467 case 24:
dfd07d72 5468 val |= PIPECONF_8BPC;
c8203565
PZ		 5469 break;
5470 case 30:
dfd07d72 5471 val |= PIPECONF_10BPC;
c8203565
PZ		 5472 break;
5473 case 36:
dfd07d72 5474 val |= PIPECONF_12BPC;
c8203565
PZ		 5475 break;
5476 default:
cc769b62
PZ		 5477 /* Case prevented by intel_choose_pipe_bpp_dither. */
5478 BUG();
c8203565
PZ		 5479 }
5480
d8b32247 5481 if (intel_crtc->config.dither)
c8203565
PZ		 5482 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5483
6ff93609 5484 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5485 val |= PIPECONF_INTERLACED_ILK;
5486 else
5487 val |= PIPECONF_PROGRESSIVE;
5488
50f3b016 5489 if (intel_crtc->config.limited_color_range)
3685a8f3 5490 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 5491
c8203565
PZ		 5492 I915_WRITE(PIPECONF(pipe), val);
5493 POSTING_READ(PIPECONF(pipe));
5494}
5495
86d3efce
VS		 5496/*
5497 * Set up the pipe CSC unit.
5498 *
5499 * Currently only full range RGB to limited range RGB conversion
5500 * is supported, but eventually this should handle various
5501 * RGB<->YCbCr scenarios as well.
5502 */
50f3b016 5503static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5504{
5505 struct drm_device *dev = crtc->dev;
5506 struct drm_i915_private *dev_priv = dev->dev_private;
5507 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5508 int pipe = intel_crtc->pipe;
5509 uint16_t coeff = 0x7800; /* 1.0 */
5510
5511 /*
5512 * TODO: Check what kind of values actually come out of the pipe
5513 * with these coeff/postoff values and adjust to get the best
5514 * accuracy. Perhaps we even need to take the bpc value into
5515 * consideration.
5516 */
5517
50f3b016 5518 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5519 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5520
5521 /*
5522 * GY/GU and RY/RU should be the other way around according
5523 * to BSpec, but reality doesn't agree. Just set them up in
5524 * a way that results in the correct picture.
5525 */
5526 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5527 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5528
5529 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5530 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5531
5532 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5533 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5534
5535 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5536 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5537 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5538
5539 if (INTEL_INFO(dev)->gen > 6) {
5540 uint16_t postoff = 0;
5541
50f3b016 5542 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5543 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5544
5545 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5546 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5547 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5548
5549 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5550 } else {
5551 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5552
50f3b016 5553 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5554 mode |= CSC_BLACK_SCREEN_OFFSET;
5555
5556 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5557 }
5558}
5559
6ff93609 5560static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5561{
5562 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5563 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5564 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5565 uint32_t val;
5566
3eff4faa 5567 val = 0;
ee2b0b38 5568
d8b32247 5569 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5570 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5571
6ff93609 5572 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5573 val |= PIPECONF_INTERLACED_ILK;
5574 else
5575 val |= PIPECONF_PROGRESSIVE;
5576
702e7a56
PZ		 5577 I915_WRITE(PIPECONF(cpu_transcoder), val);
5578 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 5579
5580 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5581 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
ee2b0b38
PZ		 5582}
5583
6591c6e4 5584static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ		 5585 intel_clock_t *clock,
5586 bool *has_reduced_clock,
5587 intel_clock_t *reduced_clock)
5588{
5589 struct drm_device *dev = crtc->dev;
5590 struct drm_i915_private *dev_priv = dev->dev_private;
5591 struct intel_encoder *intel_encoder;
5592 int refclk;
d4906093 5593 const intel_limit_t *limit;
a16af721 5594 bool ret, is_lvds = false;
79e53945 5595
6591c6e4
PZ		 5596 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5597 switch (intel_encoder->type) {
79e53945
JB		 5598 case INTEL_OUTPUT_LVDS:
5599 is_lvds = true;
5600 break;
79e53945
JB		 5601 }
5602 }
5603
d9d444cb 5604 refclk = ironlake_get_refclk(crtc);
79e53945 5605
d4906093
ML		 5606 /*
5607 * Returns a set of divisors for the desired target clock with the given
5608 * refclk, or FALSE. The returned values represent the clock equation:
5609 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5610 */
1b894b59 5611 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 5612 ret = dev_priv->display.find_dpll(limit, crtc,
5613 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 5614 refclk, NULL, clock);
6591c6e4
PZ		 5615 if (!ret)
5616 return false;
cda4b7d3 5617
ddc9003c 5618 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5619 /*
5620 * Ensure we match the reduced clock's P to the target clock.
5621 * If the clocks don't match, we can't switch the display clock
5622 * by using the FP0/FP1. In such case we will disable the LVDS
5623 * downclock feature.
5624 */
ee9300bb
DV		 5625 *has_reduced_clock =
5626 dev_priv->display.find_dpll(limit, crtc,
5627 dev_priv->lvds_downclock,
5628 refclk, clock,
5629 reduced_clock);
652c393a 5630 }
61e9653f 5631
6591c6e4
PZ		 5632 return true;
5633}
5634
01a415fd
DV		 5635static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5636{
5637 struct drm_i915_private *dev_priv = dev->dev_private;
5638 uint32_t temp;
5639
5640 temp = I915_READ(SOUTH_CHICKEN1);
5641 if (temp & FDI_BC_BIFURCATION_SELECT)
5642 return;
5643
5644 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5645 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5646
5647 temp |= FDI_BC_BIFURCATION_SELECT;
5648 DRM_DEBUG_KMS("enabling fdi C rx\n");
5649 I915_WRITE(SOUTH_CHICKEN1, temp);
5650 POSTING_READ(SOUTH_CHICKEN1);
5651}
5652
ebfd86fd 5653static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
01a415fd
DV		 5654{
5655 struct drm_device *dev = intel_crtc->base.dev;
5656 struct drm_i915_private *dev_priv = dev->dev_private;
01a415fd
DV		 5657
5658 switch (intel_crtc->pipe) {
5659 case PIPE_A:
ebfd86fd 5660 break;
01a415fd 5661 case PIPE_B:
ebfd86fd 5662 if (intel_crtc->config.fdi_lanes > 2)
01a415fd
DV		 5663 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5664 else
5665 cpt_enable_fdi_bc_bifurcation(dev);
5666
ebfd86fd 5667 break;
01a415fd 5668 case PIPE_C:
01a415fd
DV		 5669 cpt_enable_fdi_bc_bifurcation(dev);
5670
ebfd86fd 5671 break;
01a415fd
DV		 5672 default:
5673 BUG();
5674 }
5675}
5676
d4b1931c
PZ		 5677int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5678{
5679 /*
5680 * Account for spread spectrum to avoid
5681 * oversubscribing the link. Max center spread
5682 * is 2.5%; use 5% for safety's sake.
5683 */
5684 u32 bps = target_clock * bpp * 21 / 20;
5685 return bps / (link_bw * 8) + 1;
5686}
5687
7429e9d4 5688static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 5689{
7429e9d4 5690 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 5691}
5692
de13a2e3 5693static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5694 u32 *fp,
9a7c7890 5695 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5696{
de13a2e3 5697 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5698 struct drm_device *dev = crtc->dev;
5699 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5700 struct intel_encoder *intel_encoder;
5701 uint32_t dpll;
6cc5f341 5702 int factor, num_connectors = 0;
09ede541 5703 bool is_lvds = false, is_sdvo = false;
79e53945 5704
de13a2e3
PZ		 5705 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5706 switch (intel_encoder->type) {
79e53945
JB		 5707 case INTEL_OUTPUT_LVDS:
5708 is_lvds = true;
5709 break;
5710 case INTEL_OUTPUT_SDVO:
7d57382e 5711 case INTEL_OUTPUT_HDMI:
79e53945 5712 is_sdvo = true;
79e53945 5713 break;
79e53945 5714 }
43565a06 5715
c751ce4f 5716 num_connectors++;
79e53945 5717 }
79e53945 5718
c1858123 5719 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5720 factor = 21;
5721 if (is_lvds) {
5722 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5723 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5724 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5725 factor = 25;
09ede541 5726 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5727 factor = 20;
c1858123 5728
7429e9d4 5729 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5730 *fp |= FP_CB_TUNE;
2c07245f 5731
9a7c7890
DV		 5732 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5733 *fp2 |= FP_CB_TUNE;
5734
5eddb70b 5735 dpll = 0;
2c07245f 5736
a07d6787
EA		 5737 if (is_lvds)
5738 dpll |= DPLLB_MODE_LVDS;
5739 else
5740 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 5741
ef1b460d
DV		 5742 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5743 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 5744
5745 if (is_sdvo)
4a33e48d 5746 dpll |= DPLL_SDVO_HIGH_SPEED;
9566e9af 5747 if (intel_crtc->config.has_dp_encoder)
4a33e48d 5748 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 5749
a07d6787 5750 /* compute bitmask from p1 value */
7429e9d4 5751 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5752 /* also FPA1 */
7429e9d4 5753 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5754
7429e9d4 5755 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5756 case 5:
5757 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5758 break;
5759 case 7:
5760 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5761 break;
5762 case 10:
5763 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5764 break;
5765 case 14:
5766 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5767 break;
79e53945
JB		 5768 }
5769
b4c09f3b 5770 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5771 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5772 else
5773 dpll |= PLL_REF_INPUT_DREFCLK;
5774
959e16d6 5775 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 5776}
5777
5778static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5779 int x, int y,
5780 struct drm_framebuffer *fb)
5781{
5782 struct drm_device *dev = crtc->dev;
5783 struct drm_i915_private *dev_priv = dev->dev_private;
5784 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5785 int pipe = intel_crtc->pipe;
5786 int plane = intel_crtc->plane;
5787 int num_connectors = 0;
5788 intel_clock_t clock, reduced_clock;
cbbab5bd 5789 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5790 bool ok, has_reduced_clock = false;
8b47047b 5791 bool is_lvds = false;
de13a2e3 5792 struct intel_encoder *encoder;
e2b78267 5793 struct intel_shared_dpll *pll;
de13a2e3 5794 int ret;
de13a2e3
PZ		 5795
5796 for_each_encoder_on_crtc(dev, crtc, encoder) {
5797 switch (encoder->type) {
5798 case INTEL_OUTPUT_LVDS:
5799 is_lvds = true;
5800 break;
de13a2e3
PZ		 5801 }
5802
5803 num_connectors++;
a07d6787 5804 }
79e53945 5805
5dc5298b
PZ		 5806 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5807 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5808
ff9a6750 5809 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 5810 &has_reduced_clock, &reduced_clock);
ee9300bb 5811 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 5812 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5813 return -EINVAL;
79e53945 5814 }
f47709a9
DV		 5815 /* Compat-code for transition, will disappear. */
5816 if (!intel_crtc->config.clock_set) {
5817 intel_crtc->config.dpll.n = clock.n;
5818 intel_crtc->config.dpll.m1 = clock.m1;
5819 intel_crtc->config.dpll.m2 = clock.m2;
5820 intel_crtc->config.dpll.p1 = clock.p1;
5821 intel_crtc->config.dpll.p2 = clock.p2;
5822 }
79e53945 5823
de13a2e3
PZ		 5824 /* Ensure that the cursor is valid for the new mode before changing... */
5825 intel_crtc_update_cursor(crtc, true);
5826
5dc5298b 5827 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5828 if (intel_crtc->config.has_pch_encoder) {
7429e9d4 5829 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5830 if (has_reduced_clock)
7429e9d4 5831 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5832
7429e9d4 5833 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5834 &fp, &reduced_clock,
5835 has_reduced_clock ? &fp2 : NULL);
5836
959e16d6 5837 intel_crtc->config.dpll_hw_state.dpll = dpll;
66e985c0
DV		 5838 intel_crtc->config.dpll_hw_state.fp0 = fp;
5839 if (has_reduced_clock)
5840 intel_crtc->config.dpll_hw_state.fp1 = fp2;
5841 else
5842 intel_crtc->config.dpll_hw_state.fp1 = fp;
5843
b89a1d39 5844 pll = intel_get_shared_dpll(intel_crtc);
ee7b9f93 5845 if (pll == NULL) {
84f44ce7
VS		 5846 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5847 pipe_name(pipe));
4b645f14
JB		 5848 return -EINVAL;
5849 }
ee7b9f93 5850 } else
e72f9fbf 5851 intel_put_shared_dpll(intel_crtc);
79e53945 5852
03afc4a2
DV		 5853 if (intel_crtc->config.has_dp_encoder)
5854 intel_dp_set_m_n(intel_crtc);
79e53945 5855
bcd644e0
DV		 5856 if (is_lvds && has_reduced_clock && i915_powersave)
5857 intel_crtc->lowfreq_avail = true;
5858 else
5859 intel_crtc->lowfreq_avail = false;
e2b78267
DV		 5860
5861 if (intel_crtc->config.has_pch_encoder) {
5862 pll = intel_crtc_to_shared_dpll(intel_crtc);
5863
652c393a
JB		 5864 }
5865
8a654f3b 5866 intel_set_pipe_timings(intel_crtc);
5eddb70b 5867
ca3a0ff8 5868 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5869 intel_cpu_transcoder_set_m_n(intel_crtc,
5870 &intel_crtc->config.fdi_m_n);
5871 }
2c07245f 5872
ebfd86fd
DV		 5873 if (IS_IVYBRIDGE(dev))
5874 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
79e53945 5875
6ff93609 5876 ironlake_set_pipeconf(crtc);
79e53945 5877
a1f9e77e
PZ		 5878 /* Set up the display plane register */
5879 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5880 POSTING_READ(DSPCNTR(plane));
79e53945 5881
94352cf9 5882 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd 5883
1857e1da 5884 return ret;
79e53945
JB		 5885}
5886
eb14cb74
VS		 5887static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
5888 struct intel_link_m_n *m_n)
5889{
5890 struct drm_device *dev = crtc->base.dev;
5891 struct drm_i915_private *dev_priv = dev->dev_private;
5892 enum pipe pipe = crtc->pipe;
5893
5894 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
5895 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
5896 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
5897 & ~TU_SIZE_MASK;
5898 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
5899 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
5900 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5901}
5902
5903static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
5904 enum transcoder transcoder,
5905 struct intel_link_m_n *m_n)
72419203
DV		 5906{
5907 struct drm_device *dev = crtc->base.dev;
5908 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74
VS		 5909 enum pipe pipe = crtc->pipe;
5910
5911 if (INTEL_INFO(dev)->gen >= 5) {
5912 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
5913 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
5914 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5915 & ~TU_SIZE_MASK;
5916 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5917 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5918 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5919 } else {
5920 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
5921 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
5922 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
5923 & ~TU_SIZE_MASK;
5924 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
5925 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
5926 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5927 }
5928}
5929
5930void intel_dp_get_m_n(struct intel_crtc *crtc,
5931 struct intel_crtc_config *pipe_config)
5932{
5933 if (crtc->config.has_pch_encoder)
5934 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
5935 else
5936 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
5937 &pipe_config->dp_m_n);
5938}
72419203 5939
eb14cb74
VS		 5940static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5941 struct intel_crtc_config *pipe_config)
5942{
5943 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
5944 &pipe_config->fdi_m_n);
72419203
DV		 5945}
5946
2fa2fe9a
DV		 5947static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5948 struct intel_crtc_config *pipe_config)
5949{
5950 struct drm_device *dev = crtc->base.dev;
5951 struct drm_i915_private *dev_priv = dev->dev_private;
5952 uint32_t tmp;
5953
5954 tmp = I915_READ(PF_CTL(crtc->pipe));
5955
5956 if (tmp & PF_ENABLE) {
5957 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5958 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 5959
5960 /* We currently do not free assignements of panel fitters on
5961 * ivb/hsw (since we don't use the higher upscaling modes which
5962 * differentiates them) so just WARN about this case for now. */
5963 if (IS_GEN7(dev)) {
5964 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5965 PF_PIPE_SEL_IVB(crtc->pipe));
5966 }
2fa2fe9a 5967 }
79e53945
JB		 5968}
5969
0e8ffe1b
DV		 5970static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5971 struct intel_crtc_config *pipe_config)
5972{
5973 struct drm_device *dev = crtc->base.dev;
5974 struct drm_i915_private *dev_priv = dev->dev_private;
5975 uint32_t tmp;
5976
e143a21c 5977 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 5978 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5979
0e8ffe1b
DV		 5980 tmp = I915_READ(PIPECONF(crtc->pipe));
5981 if (!(tmp & PIPECONF_ENABLE))
5982 return false;
5983
42571aef
VS		 5984 switch (tmp & PIPECONF_BPC_MASK) {
5985 case PIPECONF_6BPC:
5986 pipe_config->pipe_bpp = 18;
5987 break;
5988 case PIPECONF_8BPC:
5989 pipe_config->pipe_bpp = 24;
5990 break;
5991 case PIPECONF_10BPC:
5992 pipe_config->pipe_bpp = 30;
5993 break;
5994 case PIPECONF_12BPC:
5995 pipe_config->pipe_bpp = 36;
5996 break;
5997 default:
5998 break;
5999 }
6000
ab9412ba 6001 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 6002 struct intel_shared_dpll *pll;
6003
88adfff1
DV		 6004 pipe_config->has_pch_encoder = true;
6005
627eb5a3
DV		 6006 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6007 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6008 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6009
6010 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 6011
c0d43d62 6012 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 6013 pipe_config->shared_dpll =
6014 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 6015 } else {
6016 tmp = I915_READ(PCH_DPLL_SEL);
6017 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6018 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6019 else
6020 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6021 }
66e985c0
DV		 6022
6023 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6024
6025 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6026 &pipe_config->dpll_hw_state));
c93f54cf
DV		 6027
6028 tmp = pipe_config->dpll_hw_state.dpll;
6029 pipe_config->pixel_multiplier =
6030 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6031 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 6032
6033 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 6034 } else {
6035 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 6036 }
6037
1bd1bd80
DV		 6038 intel_get_pipe_timings(crtc, pipe_config);
6039
2fa2fe9a
DV		 6040 ironlake_get_pfit_config(crtc, pipe_config);
6041
0e8ffe1b
DV		 6042 return true;
6043}
6044
be256dc7
PZ		 6045static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6046{
6047 struct drm_device *dev = dev_priv->dev;
6048 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6049 struct intel_crtc *crtc;
6050 unsigned long irqflags;
bd633a7c 6051 uint32_t val;
be256dc7
PZ		 6052
6053 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6054 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
6055 pipe_name(crtc->pipe));
6056
6057 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6058 WARN(plls->spll_refcount, "SPLL enabled\n");
6059 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6060 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6061 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6062 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6063 "CPU PWM1 enabled\n");
6064 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6065 "CPU PWM2 enabled\n");
6066 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6067 "PCH PWM1 enabled\n");
6068 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6069 "Utility pin enabled\n");
6070 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6071
6072 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6073 val = I915_READ(DEIMR);
6074 WARN((val & ~DE_PCH_EVENT_IVB) != val,
6075 "Unexpected DEIMR bits enabled: 0x%x\n", val);
6076 val = I915_READ(SDEIMR);
bd633a7c 6077 WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
be256dc7
PZ		 6078 "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6079 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6080}
6081
6082/*
6083 * This function implements pieces of two sequences from BSpec:
6084 * - Sequence for display software to disable LCPLL
6085 * - Sequence for display software to allow package C8+
6086 * The steps implemented here are just the steps that actually touch the LCPLL
6087 * register. Callers should take care of disabling all the display engine
6088 * functions, doing the mode unset, fixing interrupts, etc.
6089 */
6090void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6091 bool switch_to_fclk, bool allow_power_down)
6092{
6093 uint32_t val;
6094
6095 assert_can_disable_lcpll(dev_priv);
6096
6097 val = I915_READ(LCPLL_CTL);
6098
6099 if (switch_to_fclk) {
6100 val |= LCPLL_CD_SOURCE_FCLK;
6101 I915_WRITE(LCPLL_CTL, val);
6102
6103 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6104 LCPLL_CD_SOURCE_FCLK_DONE, 1))
6105 DRM_ERROR("Switching to FCLK failed\n");
6106
6107 val = I915_READ(LCPLL_CTL);
6108 }
6109
6110 val |= LCPLL_PLL_DISABLE;
6111 I915_WRITE(LCPLL_CTL, val);
6112 POSTING_READ(LCPLL_CTL);
6113
6114 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6115 DRM_ERROR("LCPLL still locked\n");
6116
6117 val = I915_READ(D_COMP);
6118 val |= D_COMP_COMP_DISABLE;
6119 I915_WRITE(D_COMP, val);
6120 POSTING_READ(D_COMP);
6121 ndelay(100);
6122
6123 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6124 DRM_ERROR("D_COMP RCOMP still in progress\n");
6125
6126 if (allow_power_down) {
6127 val = I915_READ(LCPLL_CTL);
6128 val |= LCPLL_POWER_DOWN_ALLOW;
6129 I915_WRITE(LCPLL_CTL, val);
6130 POSTING_READ(LCPLL_CTL);
6131 }
6132}
6133
6134/*
6135 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6136 * source.
6137 */
6138void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6139{
6140 uint32_t val;
6141
6142 val = I915_READ(LCPLL_CTL);
6143
6144 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6145 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6146 return;
6147
215733fa
PZ		 6148 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6149 * we'll hang the machine! */
6150 dev_priv->uncore.funcs.force_wake_get(dev_priv);
6151
be256dc7
PZ		 6152 if (val & LCPLL_POWER_DOWN_ALLOW) {
6153 val &= ~LCPLL_POWER_DOWN_ALLOW;
6154 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 6155 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 6156 }
6157
6158 val = I915_READ(D_COMP);
6159 val |= D_COMP_COMP_FORCE;
6160 val &= ~D_COMP_COMP_DISABLE;
6161 I915_WRITE(D_COMP, val);
35d8f2eb 6162 POSTING_READ(D_COMP);
be256dc7
PZ		 6163
6164 val = I915_READ(LCPLL_CTL);
6165 val &= ~LCPLL_PLL_DISABLE;
6166 I915_WRITE(LCPLL_CTL, val);
6167
6168 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6169 DRM_ERROR("LCPLL not locked yet\n");
6170
6171 if (val & LCPLL_CD_SOURCE_FCLK) {
6172 val = I915_READ(LCPLL_CTL);
6173 val &= ~LCPLL_CD_SOURCE_FCLK;
6174 I915_WRITE(LCPLL_CTL, val);
6175
6176 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6177 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6178 DRM_ERROR("Switching back to LCPLL failed\n");
6179 }
215733fa
PZ		 6180
6181 dev_priv->uncore.funcs.force_wake_put(dev_priv);
be256dc7
PZ		 6182}
6183
c67a470b
PZ		 6184void hsw_enable_pc8_work(struct work_struct *__work)
6185{
6186 struct drm_i915_private *dev_priv =
6187 container_of(to_delayed_work(__work), struct drm_i915_private,
6188 pc8.enable_work);
6189 struct drm_device *dev = dev_priv->dev;
6190 uint32_t val;
6191
6192 if (dev_priv->pc8.enabled)
6193 return;
6194
6195 DRM_DEBUG_KMS("Enabling package C8+\n");
6196
6197 dev_priv->pc8.enabled = true;
6198
6199 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6200 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6201 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6202 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6203 }
6204
6205 lpt_disable_clkout_dp(dev);
6206 hsw_pc8_disable_interrupts(dev);
6207 hsw_disable_lcpll(dev_priv, true, true);
6208}
6209
6210static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6211{
6212 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6213 WARN(dev_priv->pc8.disable_count < 1,
6214 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6215
6216 dev_priv->pc8.disable_count--;
6217 if (dev_priv->pc8.disable_count != 0)
6218 return;
6219
6220 schedule_delayed_work(&dev_priv->pc8.enable_work,
90058745 6221 msecs_to_jiffies(i915_pc8_timeout));
c67a470b
PZ		 6222}
6223
6224static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6225{
6226 struct drm_device *dev = dev_priv->dev;
6227 uint32_t val;
6228
6229 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6230 WARN(dev_priv->pc8.disable_count < 0,
6231 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6232
6233 dev_priv->pc8.disable_count++;
6234 if (dev_priv->pc8.disable_count != 1)
6235 return;
6236
6237 cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6238 if (!dev_priv->pc8.enabled)
6239 return;
6240
6241 DRM_DEBUG_KMS("Disabling package C8+\n");
6242
6243 hsw_restore_lcpll(dev_priv);
6244 hsw_pc8_restore_interrupts(dev);
6245 lpt_init_pch_refclk(dev);
6246
6247 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6248 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6249 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6250 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6251 }
6252
6253 intel_prepare_ddi(dev);
6254 i915_gem_init_swizzling(dev);
6255 mutex_lock(&dev_priv->rps.hw_lock);
6256 gen6_update_ring_freq(dev);
6257 mutex_unlock(&dev_priv->rps.hw_lock);
6258 dev_priv->pc8.enabled = false;
6259}
6260
6261void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6262{
6263 mutex_lock(&dev_priv->pc8.lock);
6264 __hsw_enable_package_c8(dev_priv);
6265 mutex_unlock(&dev_priv->pc8.lock);
6266}
6267
6268void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6269{
6270 mutex_lock(&dev_priv->pc8.lock);
6271 __hsw_disable_package_c8(dev_priv);
6272 mutex_unlock(&dev_priv->pc8.lock);
6273}
6274
6275static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6276{
6277 struct drm_device *dev = dev_priv->dev;
6278 struct intel_crtc *crtc;
6279 uint32_t val;
6280
6281 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6282 if (crtc->base.enabled)
6283 return false;
6284
6285 /* This case is still possible since we have the i915.disable_power_well
6286 * parameter and also the KVMr or something else might be requesting the
6287 * power well. */
6288 val = I915_READ(HSW_PWR_WELL_DRIVER);
6289 if (val != 0) {
6290 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6291 return false;
6292 }
6293
6294 return true;
6295}
6296
6297/* Since we're called from modeset_global_resources there's no way to
6298 * symmetrically increase and decrease the refcount, so we use
6299 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6300 * or not.
6301 */
6302static void hsw_update_package_c8(struct drm_device *dev)
6303{
6304 struct drm_i915_private *dev_priv = dev->dev_private;
6305 bool allow;
6306
6307 if (!i915_enable_pc8)
6308 return;
6309
6310 mutex_lock(&dev_priv->pc8.lock);
6311
6312 allow = hsw_can_enable_package_c8(dev_priv);
6313
6314 if (allow == dev_priv->pc8.requirements_met)
6315 goto done;
6316
6317 dev_priv->pc8.requirements_met = allow;
6318
6319 if (allow)
6320 __hsw_enable_package_c8(dev_priv);
6321 else
6322 __hsw_disable_package_c8(dev_priv);
6323
6324done:
6325 mutex_unlock(&dev_priv->pc8.lock);
6326}
6327
6328static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6329{
6330 if (!dev_priv->pc8.gpu_idle) {
6331 dev_priv->pc8.gpu_idle = true;
6332 hsw_enable_package_c8(dev_priv);
6333 }
6334}
6335
6336static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6337{
6338 if (dev_priv->pc8.gpu_idle) {
6339 dev_priv->pc8.gpu_idle = false;
6340 hsw_disable_package_c8(dev_priv);
6341 }
be256dc7
PZ		 6342}
6343
d6dd9eb1
DV		 6344static void haswell_modeset_global_resources(struct drm_device *dev)
6345{
d6dd9eb1
DV		 6346 bool enable = false;
6347 struct intel_crtc *crtc;
d6dd9eb1
DV		 6348
6349 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 6350 if (!crtc->base.enabled)
6351 continue;
d6dd9eb1 6352
e7a639c4
DV		 6353 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
6354 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 6355 enable = true;
6356 }
6357
d6dd9eb1 6358 intel_set_power_well(dev, enable);
c67a470b
PZ		 6359
6360 hsw_update_package_c8(dev);
d6dd9eb1
DV		 6361}
6362
09b4ddf9 6363static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 6364 int x, int y,
6365 struct drm_framebuffer *fb)
6366{
6367 struct drm_device *dev = crtc->dev;
6368 struct drm_i915_private *dev_priv = dev->dev_private;
6369 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 6370 int plane = intel_crtc->plane;
09b4ddf9 6371 int ret;
09b4ddf9 6372
ff9a6750 6373 if (!intel_ddi_pll_mode_set(crtc))
6441ab5f
PZ		 6374 return -EINVAL;
6375
09b4ddf9
PZ		 6376 /* Ensure that the cursor is valid for the new mode before changing... */
6377 intel_crtc_update_cursor(crtc, true);
6378
03afc4a2
DV		 6379 if (intel_crtc->config.has_dp_encoder)
6380 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 6381
6382 intel_crtc->lowfreq_avail = false;
09b4ddf9 6383
8a654f3b 6384 intel_set_pipe_timings(intel_crtc);
09b4ddf9 6385
ca3a0ff8 6386 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 6387 intel_cpu_transcoder_set_m_n(intel_crtc,
6388 &intel_crtc->config.fdi_m_n);
6389 }
09b4ddf9 6390
6ff93609 6391 haswell_set_pipeconf(crtc);
09b4ddf9 6392
50f3b016 6393 intel_set_pipe_csc(crtc);
86d3efce 6394
09b4ddf9 6395 /* Set up the display plane register */
86d3efce 6396 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 6397 POSTING_READ(DSPCNTR(plane));
6398
6399 ret = intel_pipe_set_base(crtc, x, y, fb);
6400
1f803ee5 6401 return ret;
79e53945
JB		 6402}
6403
0e8ffe1b
DV		 6404static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6405 struct intel_crtc_config *pipe_config)
6406{
6407 struct drm_device *dev = crtc->base.dev;
6408 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 6409 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 6410 uint32_t tmp;
6411
e143a21c 6412 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 6413 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6414
eccb140b
DV		 6415 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6416 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6417 enum pipe trans_edp_pipe;
6418 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6419 default:
6420 WARN(1, "unknown pipe linked to edp transcoder\n");
6421 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6422 case TRANS_DDI_EDP_INPUT_A_ON:
6423 trans_edp_pipe = PIPE_A;
6424 break;
6425 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6426 trans_edp_pipe = PIPE_B;
6427 break;
6428 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6429 trans_edp_pipe = PIPE_C;
6430 break;
6431 }
6432
6433 if (trans_edp_pipe == crtc->pipe)
6434 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6435 }
6436
b97186f0 6437 if (!intel_display_power_enabled(dev,
eccb140b 6438 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 6439 return false;
6440
eccb140b 6441 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 6442 if (!(tmp & PIPECONF_ENABLE))
6443 return false;
6444
88adfff1 6445 /*
f196e6be 6446 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 6447 * DDI E. So just check whether this pipe is wired to DDI E and whether
6448 * the PCH transcoder is on.
6449 */
eccb140b 6450 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 6451 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 6452 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 6453 pipe_config->has_pch_encoder = true;
6454
627eb5a3
DV		 6455 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6456 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6457 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6458
6459 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 6460 }
6461
1bd1bd80
DV		 6462 intel_get_pipe_timings(crtc, pipe_config);
6463
2fa2fe9a
DV		 6464 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6465 if (intel_display_power_enabled(dev, pfit_domain))
6466 ironlake_get_pfit_config(crtc, pipe_config);
88adfff1 6467
42db64ef
PZ		 6468 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6469 (I915_READ(IPS_CTL) & IPS_ENABLE);
6470
6c49f241
DV		 6471 pipe_config->pixel_multiplier = 1;
6472
0e8ffe1b
DV		 6473 return true;
6474}
6475
f564048e 6476static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6477 int x, int y,
94352cf9 6478 struct drm_framebuffer *fb)
f564048e
EA		 6479{
6480 struct drm_device *dev = crtc->dev;
6481 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19 6482 struct intel_encoder *encoder;
0b701d27 6483 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 6484 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6485 int pipe = intel_crtc->pipe;
f564048e
EA		 6486 int ret;
6487
0b701d27 6488 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6489
b8cecdf5
DV		 6490 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6491
79e53945 6492 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6493
9256aa19
DV		 6494 if (ret != 0)
6495 return ret;
6496
6497 for_each_encoder_on_crtc(dev, crtc, encoder) {
6498 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6499 encoder->base.base.id,
6500 drm_get_encoder_name(&encoder->base),
6501 mode->base.id, mode->name);
36f2d1f1 6502 encoder->mode_set(encoder);
9256aa19
DV		 6503 }
6504
6505 return 0;
79e53945
JB		 6506}
6507
3a9627f4
WF		 6508static bool intel_eld_uptodate(struct drm_connector *connector,
6509 int reg_eldv, uint32_t bits_eldv,
6510 int reg_elda, uint32_t bits_elda,
6511 int reg_edid)
6512{
6513 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6514 uint8_t *eld = connector->eld;
6515 uint32_t i;
6516
6517 i = I915_READ(reg_eldv);
6518 i &= bits_eldv;
6519
6520 if (!eld[0])
6521 return !i;
6522
6523 if (!i)
6524 return false;
6525
6526 i = I915_READ(reg_elda);
6527 i &= ~bits_elda;
6528 I915_WRITE(reg_elda, i);
6529
6530 for (i = 0; i < eld[2]; i++)
6531 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6532 return false;
6533
6534 return true;
6535}
6536
e0dac65e
WF		 6537static void g4x_write_eld(struct drm_connector *connector,
6538 struct drm_crtc *crtc)
6539{
6540 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6541 uint8_t *eld = connector->eld;
6542 uint32_t eldv;
6543 uint32_t len;
6544 uint32_t i;
6545
6546 i = I915_READ(G4X_AUD_VID_DID);
6547
6548 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6549 eldv = G4X_ELDV_DEVCL_DEVBLC;
6550 else
6551 eldv = G4X_ELDV_DEVCTG;
6552
3a9627f4
WF		 6553 if (intel_eld_uptodate(connector,
6554 G4X_AUD_CNTL_ST, eldv,
6555 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6556 G4X_HDMIW_HDMIEDID))
6557 return;
6558
e0dac65e
WF		 6559 i = I915_READ(G4X_AUD_CNTL_ST);
6560 i &= ~(eldv | G4X_ELD_ADDR);
6561 len = (i >> 9) & 0x1f; /* ELD buffer size */
6562 I915_WRITE(G4X_AUD_CNTL_ST, i);
6563
6564 if (!eld[0])
6565 return;
6566
6567 len = min_t(uint8_t, eld[2], len);
6568 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6569 for (i = 0; i < len; i++)
6570 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6571
6572 i = I915_READ(G4X_AUD_CNTL_ST);
6573 i |= eldv;
6574 I915_WRITE(G4X_AUD_CNTL_ST, i);
6575}
6576
83358c85
WX		 6577static void haswell_write_eld(struct drm_connector *connector,
6578 struct drm_crtc *crtc)
6579{
6580 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6581 uint8_t *eld = connector->eld;
6582 struct drm_device *dev = crtc->dev;
7b9f35a6 6583 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6584 uint32_t eldv;
6585 uint32_t i;
6586 int len;
6587 int pipe = to_intel_crtc(crtc)->pipe;
6588 int tmp;
6589
6590 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6591 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6592 int aud_config = HSW_AUD_CFG(pipe);
6593 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6594
6595
6596 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6597
6598 /* Audio output enable */
6599 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6600 tmp = I915_READ(aud_cntrl_st2);
6601 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6602 I915_WRITE(aud_cntrl_st2, tmp);
6603
6604 /* Wait for 1 vertical blank */
6605 intel_wait_for_vblank(dev, pipe);
6606
6607 /* Set ELD valid state */
6608 tmp = I915_READ(aud_cntrl_st2);
6609 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6610 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6611 I915_WRITE(aud_cntrl_st2, tmp);
6612 tmp = I915_READ(aud_cntrl_st2);
6613 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6614
6615 /* Enable HDMI mode */
6616 tmp = I915_READ(aud_config);
6617 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6618 /* clear N_programing_enable and N_value_index */
6619 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6620 I915_WRITE(aud_config, tmp);
6621
6622 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6623
6624 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6625 intel_crtc->eld_vld = true;
83358c85
WX		 6626
6627 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6628 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6629 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6630 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6631 } else
6632 I915_WRITE(aud_config, 0);
6633
6634 if (intel_eld_uptodate(connector,
6635 aud_cntrl_st2, eldv,
6636 aud_cntl_st, IBX_ELD_ADDRESS,
6637 hdmiw_hdmiedid))
6638 return;
6639
6640 i = I915_READ(aud_cntrl_st2);
6641 i &= ~eldv;
6642 I915_WRITE(aud_cntrl_st2, i);
6643
6644 if (!eld[0])
6645 return;
6646
6647 i = I915_READ(aud_cntl_st);
6648 i &= ~IBX_ELD_ADDRESS;
6649 I915_WRITE(aud_cntl_st, i);
6650 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6651 DRM_DEBUG_DRIVER("port num:%d\n", i);
6652
6653 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6654 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6655 for (i = 0; i < len; i++)
6656 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6657
6658 i = I915_READ(aud_cntrl_st2);
6659 i |= eldv;
6660 I915_WRITE(aud_cntrl_st2, i);
6661
6662}
6663
e0dac65e
WF		 6664static void ironlake_write_eld(struct drm_connector *connector,
6665 struct drm_crtc *crtc)
6666{
6667 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6668 uint8_t *eld = connector->eld;
6669 uint32_t eldv;
6670 uint32_t i;
6671 int len;
6672 int hdmiw_hdmiedid;
b6daa025 6673 int aud_config;
e0dac65e
WF		 6674 int aud_cntl_st;
6675 int aud_cntrl_st2;
9b138a83 6676 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6677
b3f33cbf 6678 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6679 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6680 aud_config = IBX_AUD_CFG(pipe);
6681 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6682 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6683 } else {
9b138a83
WX		 6684 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6685 aud_config = CPT_AUD_CFG(pipe);
6686 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6687 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6688 }
6689
9b138a83 6690 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6691
6692 i = I915_READ(aud_cntl_st);
9b138a83 6693 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6694 if (!i) {
6695 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6696 /* operate blindly on all ports */
1202b4c6
WF		 6697 eldv = IBX_ELD_VALIDB;
6698 eldv |= IBX_ELD_VALIDB << 4;
6699 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6700 } else {
2582a850 6701 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6702 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6703 }
6704
3a9627f4
WF		 6705 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6706 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6707 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6708 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6709 } else
6710 I915_WRITE(aud_config, 0);
e0dac65e 6711
3a9627f4
WF		 6712 if (intel_eld_uptodate(connector,
6713 aud_cntrl_st2, eldv,
6714 aud_cntl_st, IBX_ELD_ADDRESS,
6715 hdmiw_hdmiedid))
6716 return;
6717
e0dac65e
WF		 6718 i = I915_READ(aud_cntrl_st2);
6719 i &= ~eldv;
6720 I915_WRITE(aud_cntrl_st2, i);
6721
6722 if (!eld[0])
6723 return;
6724
e0dac65e 6725 i = I915_READ(aud_cntl_st);
1202b4c6 6726 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6727 I915_WRITE(aud_cntl_st, i);
6728
6729 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6730 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6731 for (i = 0; i < len; i++)
6732 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6733
6734 i = I915_READ(aud_cntrl_st2);
6735 i |= eldv;
6736 I915_WRITE(aud_cntrl_st2, i);
6737}
6738
6739void intel_write_eld(struct drm_encoder *encoder,
6740 struct drm_display_mode *mode)
6741{
6742 struct drm_crtc *crtc = encoder->crtc;
6743 struct drm_connector *connector;
6744 struct drm_device *dev = encoder->dev;
6745 struct drm_i915_private *dev_priv = dev->dev_private;
6746
6747 connector = drm_select_eld(encoder, mode);
6748 if (!connector)
6749 return;
6750
6751 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6752 connector->base.id,
6753 drm_get_connector_name(connector),
6754 connector->encoder->base.id,
6755 drm_get_encoder_name(connector->encoder));
6756
6757 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6758
6759 if (dev_priv->display.write_eld)
6760 dev_priv->display.write_eld(connector, crtc);
6761}
6762
79e53945
JB		 6763/** Loads the palette/gamma unit for the CRTC with the prepared values */
6764void intel_crtc_load_lut(struct drm_crtc *crtc)
6765{
6766 struct drm_device *dev = crtc->dev;
6767 struct drm_i915_private *dev_priv = dev->dev_private;
6768 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
42db64ef
PZ		 6769 enum pipe pipe = intel_crtc->pipe;
6770 int palreg = PALETTE(pipe);
79e53945 6771 int i;
42db64ef 6772 bool reenable_ips = false;
79e53945
JB		 6773
6774 /* The clocks have to be on to load the palette. */
aed3f09d 6775 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6776 return;
6777
23538ef1
JN		 6778 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
6779 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
6780 assert_dsi_pll_enabled(dev_priv);
6781 else
6782 assert_pll_enabled(dev_priv, pipe);
6783 }
14420bd0 6784
f2b115e6 6785 /* use legacy palette for Ironlake */
bad720ff 6786 if (HAS_PCH_SPLIT(dev))
42db64ef
PZ		 6787 palreg = LGC_PALETTE(pipe);
6788
6789 /* Workaround : Do not read or write the pipe palette/gamma data while
6790 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6791 */
6792 if (intel_crtc->config.ips_enabled &&
6793 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6794 GAMMA_MODE_MODE_SPLIT)) {
6795 hsw_disable_ips(intel_crtc);
6796 reenable_ips = true;
6797 }
2c07245f 6798
79e53945
JB		 6799 for (i = 0; i < 256; i++) {
6800 I915_WRITE(palreg + 4 * i,
6801 (intel_crtc->lut_r[i] << 16) |
6802 (intel_crtc->lut_g[i] << 8) |
6803 intel_crtc->lut_b[i]);
6804 }
42db64ef
PZ		 6805
6806 if (reenable_ips)
6807 hsw_enable_ips(intel_crtc);
79e53945
JB		 6808}
6809
560b85bb
CW		 6810static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6811{
6812 struct drm_device *dev = crtc->dev;
6813 struct drm_i915_private *dev_priv = dev->dev_private;
6814 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6815 bool visible = base != 0;
6816 u32 cntl;
6817
6818 if (intel_crtc->cursor_visible == visible)
6819 return;
6820
9db4a9c7 6821 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6822 if (visible) {
6823 /* On these chipsets we can only modify the base whilst
6824 * the cursor is disabled.
6825 */
9db4a9c7 6826 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6827
6828 cntl &= ~(CURSOR_FORMAT_MASK);
6829 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6830 cntl |= CURSOR_ENABLE |
6831 CURSOR_GAMMA_ENABLE |
6832 CURSOR_FORMAT_ARGB;
6833 } else
6834 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6835 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6836
6837 intel_crtc->cursor_visible = visible;
6838}
6839
6840static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6841{
6842 struct drm_device *dev = crtc->dev;
6843 struct drm_i915_private *dev_priv = dev->dev_private;
6844 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6845 int pipe = intel_crtc->pipe;
6846 bool visible = base != 0;
6847
6848 if (intel_crtc->cursor_visible != visible) {
548f245b 6849 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6850 if (base) {
6851 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6852 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6853 cntl |= pipe << 28; /* Connect to correct pipe */
6854 } else {
6855 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6856 cntl |= CURSOR_MODE_DISABLE;
6857 }
9db4a9c7 6858 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6859
6860 intel_crtc->cursor_visible = visible;
6861 }
6862 /* and commit changes on next vblank */
9db4a9c7 6863 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6864}
6865
65a21cd6
JB		 6866static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6867{
6868 struct drm_device *dev = crtc->dev;
6869 struct drm_i915_private *dev_priv = dev->dev_private;
6870 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6871 int pipe = intel_crtc->pipe;
6872 bool visible = base != 0;
6873
6874 if (intel_crtc->cursor_visible != visible) {
6875 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6876 if (base) {
6877 cntl &= ~CURSOR_MODE;
6878 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6879 } else {
6880 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6881 cntl |= CURSOR_MODE_DISABLE;
6882 }
1f5d76db 6883 if (IS_HASWELL(dev)) {
86d3efce 6884 cntl |= CURSOR_PIPE_CSC_ENABLE;
1f5d76db
PZ		 6885 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
6886 }
65a21cd6
JB		 6887 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6888
6889 intel_crtc->cursor_visible = visible;
6890 }
6891 /* and commit changes on next vblank */
6892 I915_WRITE(CURBASE_IVB(pipe), base);
6893}
6894
cda4b7d3 6895/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6896static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6897 bool on)
cda4b7d3
CW		 6898{
6899 struct drm_device *dev = crtc->dev;
6900 struct drm_i915_private *dev_priv = dev->dev_private;
6901 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6902 int pipe = intel_crtc->pipe;
6903 int x = intel_crtc->cursor_x;
6904 int y = intel_crtc->cursor_y;
560b85bb 6905 u32 base, pos;
cda4b7d3
CW		 6906 bool visible;
6907
6908 pos = 0;
6909
6b383a7f 6910 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6911 base = intel_crtc->cursor_addr;
6912 if (x > (int) crtc->fb->width)
6913 base = 0;
6914
6915 if (y > (int) crtc->fb->height)
6916 base = 0;
6917 } else
6918 base = 0;
6919
6920 if (x < 0) {
6921 if (x + intel_crtc->cursor_width < 0)
6922 base = 0;
6923
6924 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6925 x = -x;
6926 }
6927 pos |= x << CURSOR_X_SHIFT;
6928
6929 if (y < 0) {
6930 if (y + intel_crtc->cursor_height < 0)
6931 base = 0;
6932
6933 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6934 y = -y;
6935 }
6936 pos |= y << CURSOR_Y_SHIFT;
6937
6938 visible = base != 0;
560b85bb 6939 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6940 return;
6941
0cd83aa9 6942 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6943 I915_WRITE(CURPOS_IVB(pipe), pos);
6944 ivb_update_cursor(crtc, base);
6945 } else {
6946 I915_WRITE(CURPOS(pipe), pos);
6947 if (IS_845G(dev) || IS_I865G(dev))
6948 i845_update_cursor(crtc, base);
6949 else
6950 i9xx_update_cursor(crtc, base);
6951 }
cda4b7d3
CW		 6952}
6953
79e53945 6954static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6955 struct drm_file *file,
79e53945
JB		 6956 uint32_t handle,
6957 uint32_t width, uint32_t height)
6958{
6959 struct drm_device *dev = crtc->dev;
6960 struct drm_i915_private *dev_priv = dev->dev_private;
6961 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6962 struct drm_i915_gem_object *obj;
cda4b7d3 6963 uint32_t addr;
3f8bc370 6964 int ret;
79e53945 6965
79e53945
JB		 6966 /* if we want to turn off the cursor ignore width and height */
6967 if (!handle) {
28c97730 6968 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6969 addr = 0;
05394f39 6970 obj = NULL;
5004417d 6971 mutex_lock(&dev->struct_mutex);
3f8bc370 6972 goto finish;
79e53945
JB		 6973 }
6974
6975 /* Currently we only support 64x64 cursors */
6976 if (width != 64 || height != 64) {
6977 DRM_ERROR("we currently only support 64x64 cursors\n");
6978 return -EINVAL;
6979 }
6980
05394f39 6981 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6982 if (&obj->base == NULL)
79e53945
JB		 6983 return -ENOENT;
6984
05394f39 6985 if (obj->base.size < width * height * 4) {
79e53945 6986 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6987 ret = -ENOMEM;
6988 goto fail;
79e53945
JB		 6989 }
6990
71acb5eb 6991 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6992 mutex_lock(&dev->struct_mutex);
b295d1b6 6993 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6994 unsigned alignment;
6995
d9e86c0e
CW		 6996 if (obj->tiling_mode) {
6997 DRM_ERROR("cursor cannot be tiled\n");
6998 ret = -EINVAL;
6999 goto fail_locked;
7000 }
7001
693db184
CW		 7002 /* Note that the w/a also requires 2 PTE of padding following
7003 * the bo. We currently fill all unused PTE with the shadow
7004 * page and so we should always have valid PTE following the
7005 * cursor preventing the VT-d warning.
7006 */
7007 alignment = 0;
7008 if (need_vtd_wa(dev))
7009 alignment = 64*1024;
7010
7011 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 7012 if (ret) {
7013 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 7014 goto fail_locked;
e7b526bb
CW		 7015 }
7016
d9e86c0e
CW		 7017 ret = i915_gem_object_put_fence(obj);
7018 if (ret) {
2da3b9b9 7019 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 7020 goto fail_unpin;
7021 }
7022
f343c5f6 7023 addr = i915_gem_obj_ggtt_offset(obj);
71acb5eb 7024 } else {
6eeefaf3 7025 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 7026 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 7027 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7028 align);
71acb5eb
DA		 7029 if (ret) {
7030 DRM_ERROR("failed to attach phys object\n");
7f9872e0 7031 goto fail_locked;
71acb5eb 7032 }
05394f39 7033 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 7034 }
7035
a6c45cf0 7036 if (IS_GEN2(dev))
14b60391
JB		 7037 I915_WRITE(CURSIZE, (height << 12) | width);
7038
3f8bc370 7039 finish:
3f8bc370 7040 if (intel_crtc->cursor_bo) {
b295d1b6 7041 if (dev_priv->info->cursor_needs_physical) {
05394f39 7042 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 7043 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7044 } else
cc98b413 7045 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
05394f39 7046 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 7047 }
80824003 7048
7f9872e0 7049 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 7050
7051 intel_crtc->cursor_addr = addr;
05394f39 7052 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 7053 intel_crtc->cursor_width = width;
7054 intel_crtc->cursor_height = height;
7055
40ccc72b 7056 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 7057
79e53945 7058 return 0;
e7b526bb 7059fail_unpin:
cc98b413 7060 i915_gem_object_unpin_from_display_plane(obj);
7f9872e0 7061fail_locked:
34b8686e 7062 mutex_unlock(&dev->struct_mutex);
bc9025bd 7063fail:
05394f39 7064 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 7065 return ret;
79e53945
JB		 7066}
7067
7068static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7069{
79e53945 7070 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7071
cda4b7d3
CW		 7072 intel_crtc->cursor_x = x;
7073 intel_crtc->cursor_y = y;
652c393a 7074
40ccc72b 7075 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 7076
7077 return 0;
7078}
7079
7080/** Sets the color ramps on behalf of RandR */
7081void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
7082 u16 blue, int regno)
7083{
7084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7085
7086 intel_crtc->lut_r[regno] = red >> 8;
7087 intel_crtc->lut_g[regno] = green >> 8;
7088 intel_crtc->lut_b[regno] = blue >> 8;
7089}
7090
b8c00ac5
DA		 7091void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
7092 u16 *blue, int regno)
7093{
7094 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7095
7096 *red = intel_crtc->lut_r[regno] << 8;
7097 *green = intel_crtc->lut_g[regno] << 8;
7098 *blue = intel_crtc->lut_b[regno] << 8;
7099}
7100
79e53945 7101static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 7102 u16 *blue, uint32_t start, uint32_t size)
79e53945 7103{
7203425a 7104 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 7105 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7106
7203425a 7107 for (i = start; i < end; i++) {
79e53945
JB		 7108 intel_crtc->lut_r[i] = red[i] >> 8;
7109 intel_crtc->lut_g[i] = green[i] >> 8;
7110 intel_crtc->lut_b[i] = blue[i] >> 8;
7111 }
7112
7113 intel_crtc_load_lut(crtc);
7114}
7115
79e53945
JB		 7116/* VESA 640x480x72Hz mode to set on the pipe */
7117static struct drm_display_mode load_detect_mode = {
7118 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7119 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7120};
7121
d2dff872
CW		 7122static struct drm_framebuffer *
7123intel_framebuffer_create(struct drm_device *dev,
308e5bcb 7124 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 7125 struct drm_i915_gem_object *obj)
7126{
7127 struct intel_framebuffer *intel_fb;
7128 int ret;
7129
7130 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7131 if (!intel_fb) {
7132 drm_gem_object_unreference_unlocked(&obj->base);
7133 return ERR_PTR(-ENOMEM);
7134 }
7135
7136 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7137 if (ret) {
7138 drm_gem_object_unreference_unlocked(&obj->base);
7139 kfree(intel_fb);
7140 return ERR_PTR(ret);
7141 }
7142
7143 return &intel_fb->base;
7144}
7145
7146static u32
7147intel_framebuffer_pitch_for_width(int width, int bpp)
7148{
7149 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7150 return ALIGN(pitch, 64);
7151}
7152
7153static u32
7154intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7155{
7156 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7157 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7158}
7159
7160static struct drm_framebuffer *
7161intel_framebuffer_create_for_mode(struct drm_device *dev,
7162 struct drm_display_mode *mode,
7163 int depth, int bpp)
7164{
7165 struct drm_i915_gem_object *obj;
0fed39bd 7166 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 7167
7168 obj = i915_gem_alloc_object(dev,
7169 intel_framebuffer_size_for_mode(mode, bpp));
7170 if (obj == NULL)
7171 return ERR_PTR(-ENOMEM);
7172
7173 mode_cmd.width = mode->hdisplay;
7174 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 7175 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7176 bpp);
5ca0c34a 7177 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 7178
7179 return intel_framebuffer_create(dev, &mode_cmd, obj);
7180}
7181
7182static struct drm_framebuffer *
7183mode_fits_in_fbdev(struct drm_device *dev,
7184 struct drm_display_mode *mode)
7185{
7186 struct drm_i915_private *dev_priv = dev->dev_private;
7187 struct drm_i915_gem_object *obj;
7188 struct drm_framebuffer *fb;
7189
7190 if (dev_priv->fbdev == NULL)
7191 return NULL;
7192
7193 obj = dev_priv->fbdev->ifb.obj;
7194 if (obj == NULL)
7195 return NULL;
7196
7197 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 7198 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7199 fb->bits_per_pixel))
d2dff872
CW		 7200 return NULL;
7201
01f2c773 7202 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 7203 return NULL;
7204
7205 return fb;
7206}
7207
d2434ab7 7208bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 7209 struct drm_display_mode *mode,
8261b191 7210 struct intel_load_detect_pipe *old)
79e53945
JB		 7211{
7212 struct intel_crtc *intel_crtc;
d2434ab7
DV		 7213 struct intel_encoder *intel_encoder =
7214 intel_attached_encoder(connector);
79e53945 7215 struct drm_crtc *possible_crtc;
4ef69c7a 7216 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 7217 struct drm_crtc *crtc = NULL;
7218 struct drm_device *dev = encoder->dev;
94352cf9 7219 struct drm_framebuffer *fb;
79e53945
JB		 7220 int i = -1;
7221
d2dff872
CW		 7222 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7223 connector->base.id, drm_get_connector_name(connector),
7224 encoder->base.id, drm_get_encoder_name(encoder));
7225
79e53945
JB		 7226 /*
7227 * Algorithm gets a little messy:
7a5e4805 7228 *
79e53945
JB		 7229 * - if the connector already has an assigned crtc, use it (but make
7230 * sure it's on first)
7a5e4805 7231 *
79e53945
JB		 7232 * - try to find the first unused crtc that can drive this connector,
7233 * and use that if we find one
79e53945
JB		 7234 */
7235
7236 /* See if we already have a CRTC for this connector */
7237 if (encoder->crtc) {
7238 crtc = encoder->crtc;
8261b191 7239
7b24056b
DV		 7240 mutex_lock(&crtc->mutex);
7241
24218aac 7242 old->dpms_mode = connector->dpms;
8261b191
CW		 7243 old->load_detect_temp = false;
7244
7245 /* Make sure the crtc and connector are running */
24218aac
DV		 7246 if (connector->dpms != DRM_MODE_DPMS_ON)
7247 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 7248
7173188d 7249 return true;
79e53945
JB		 7250 }
7251
7252 /* Find an unused one (if possible) */
7253 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7254 i++;
7255 if (!(encoder->possible_crtcs & (1 << i)))
7256 continue;
7257 if (!possible_crtc->enabled) {
7258 crtc = possible_crtc;
7259 break;
7260 }
79e53945
JB		 7261 }
7262
7263 /*
7264 * If we didn't find an unused CRTC, don't use any.
7265 */
7266 if (!crtc) {
7173188d
CW		 7267 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7268 return false;
79e53945
JB		 7269 }
7270
7b24056b 7271 mutex_lock(&crtc->mutex);
fc303101
DV		 7272 intel_encoder->new_crtc = to_intel_crtc(crtc);
7273 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 7274
7275 intel_crtc = to_intel_crtc(crtc);
24218aac 7276 old->dpms_mode = connector->dpms;
8261b191 7277 old->load_detect_temp = true;
d2dff872 7278 old->release_fb = NULL;
79e53945 7279
6492711d
CW		 7280 if (!mode)
7281 mode = &load_detect_mode;
79e53945 7282
d2dff872
CW		 7283 /* We need a framebuffer large enough to accommodate all accesses
7284 * that the plane may generate whilst we perform load detection.
7285 * We can not rely on the fbcon either being present (we get called
7286 * during its initialisation to detect all boot displays, or it may
7287 * not even exist) or that it is large enough to satisfy the
7288 * requested mode.
7289 */
94352cf9
DV		 7290 fb = mode_fits_in_fbdev(dev, mode);
7291 if (fb == NULL) {
d2dff872 7292 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 7293 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7294 old->release_fb = fb;
d2dff872
CW		 7295 } else
7296 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 7297 if (IS_ERR(fb)) {
d2dff872 7298 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 7299 mutex_unlock(&crtc->mutex);
0e8b3d3e 7300 return false;
79e53945 7301 }
79e53945 7302
c0c36b94 7303 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 7304 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 7305 if (old->release_fb)
7306 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 7307 mutex_unlock(&crtc->mutex);
0e8b3d3e 7308 return false;
79e53945 7309 }
7173188d 7310
79e53945 7311 /* let the connector get through one full cycle before testing */
9d0498a2 7312 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 7313 return true;
79e53945
JB		 7314}
7315
d2434ab7 7316void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 7317 struct intel_load_detect_pipe *old)
79e53945 7318{
d2434ab7
DV		 7319 struct intel_encoder *intel_encoder =
7320 intel_attached_encoder(connector);
4ef69c7a 7321 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 7322 struct drm_crtc *crtc = encoder->crtc;
79e53945 7323
d2dff872
CW		 7324 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7325 connector->base.id, drm_get_connector_name(connector),
7326 encoder->base.id, drm_get_encoder_name(encoder));
7327
8261b191 7328 if (old->load_detect_temp) {
fc303101
DV		 7329 to_intel_connector(connector)->new_encoder = NULL;
7330 intel_encoder->new_crtc = NULL;
7331 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 7332
36206361
DV		 7333 if (old->release_fb) {
7334 drm_framebuffer_unregister_private(old->release_fb);
7335 drm_framebuffer_unreference(old->release_fb);
7336 }
d2dff872 7337
67c96400 7338 mutex_unlock(&crtc->mutex);
0622a53c 7339 return;
79e53945
JB		 7340 }
7341
c751ce4f 7342 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 7343 if (old->dpms_mode != DRM_MODE_DPMS_ON)
7344 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 7345
7346 mutex_unlock(&crtc->mutex);
79e53945
JB		 7347}
7348
da4a1efa
VS		 7349static int i9xx_pll_refclk(struct drm_device *dev,
7350 const struct intel_crtc_config *pipe_config)
7351{
7352 struct drm_i915_private *dev_priv = dev->dev_private;
7353 u32 dpll = pipe_config->dpll_hw_state.dpll;
7354
7355 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7356 return dev_priv->vbt.lvds_ssc_freq * 1000;
7357 else if (HAS_PCH_SPLIT(dev))
7358 return 120000;
7359 else if (!IS_GEN2(dev))
7360 return 96000;
7361 else
7362 return 48000;
7363}
7364
79e53945 7365/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc
JB		 7366static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7367 struct intel_crtc_config *pipe_config)
79e53945 7368{
f1f644dc 7369 struct drm_device *dev = crtc->base.dev;
79e53945 7370 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 7371 int pipe = pipe_config->cpu_transcoder;
293623f7 7372 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 7373 u32 fp;
7374 intel_clock_t clock;
da4a1efa 7375 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 7376
7377 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 7378 fp = pipe_config->dpll_hw_state.fp0;
79e53945 7379 else
293623f7 7380 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 7381
7382 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 7383 if (IS_PINEVIEW(dev)) {
7384 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7385 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 7386 } else {
7387 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7388 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7389 }
7390
a6c45cf0 7391 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 7392 if (IS_PINEVIEW(dev))
7393 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7394 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 7395 else
7396 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 7397 DPLL_FPA01_P1_POST_DIV_SHIFT);
7398
7399 switch (dpll & DPLL_MODE_MASK) {
7400 case DPLLB_MODE_DAC_SERIAL:
7401 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7402 5 : 10;
7403 break;
7404 case DPLLB_MODE_LVDS:
7405 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7406 7 : 14;
7407 break;
7408 default:
28c97730 7409 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 7410 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 7411 return;
79e53945
JB		 7412 }
7413
ac58c3f0 7414 if (IS_PINEVIEW(dev))
da4a1efa 7415 pineview_clock(refclk, &clock);
ac58c3f0 7416 else
da4a1efa 7417 i9xx_clock(refclk, &clock);
79e53945
JB		 7418 } else {
7419 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7420
7421 if (is_lvds) {
7422 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7423 DPLL_FPA01_P1_POST_DIV_SHIFT);
7424 clock.p2 = 14;
79e53945
JB		 7425 } else {
7426 if (dpll & PLL_P1_DIVIDE_BY_TWO)
7427 clock.p1 = 2;
7428 else {
7429 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7430 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7431 }
7432 if (dpll & PLL_P2_DIVIDE_BY_4)
7433 clock.p2 = 4;
7434 else
7435 clock.p2 = 2;
79e53945 7436 }
da4a1efa
VS		 7437
7438 i9xx_clock(refclk, &clock);
79e53945
JB		 7439 }
7440
18442d08
VS		 7441 /*
7442 * This value includes pixel_multiplier. We will use
7443 * port_clock to compute adjusted_mode.clock in the
7444 * encoder's get_config() function.
7445 */
7446 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 7447}
7448
6878da05
VS		 7449int intel_dotclock_calculate(int link_freq,
7450 const struct intel_link_m_n *m_n)
f1f644dc 7451{
f1f644dc
JB		 7452 /*
7453 * The calculation for the data clock is:
1041a02f 7454 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 7455 * But we want to avoid losing precison if possible, so:
1041a02f 7456 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 7457 *
7458 * and the link clock is simpler:
1041a02f 7459 * link_clock = (m * link_clock) / n
f1f644dc
JB		 7460 */
7461
6878da05
VS		 7462 if (!m_n->link_n)
7463 return 0;
7464
7465 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
7466}
7467
18442d08
VS		 7468static void ironlake_pch_clock_get(struct intel_crtc *crtc,
7469 struct intel_crtc_config *pipe_config)
6878da05
VS		 7470{
7471 struct drm_device *dev = crtc->base.dev;
18442d08
VS		 7472
7473 /* read out port_clock from the DPLL */
7474 i9xx_crtc_clock_get(crtc, pipe_config);
6878da05 7475
f1f644dc 7476 /*
18442d08
VS		 7477 * This value does not include pixel_multiplier.
7478 * We will check that port_clock and adjusted_mode.clock
7479 * agree once we know their relationship in the encoder's
7480 * get_config() function.
79e53945 7481 */
18442d08
VS		 7482 pipe_config->adjusted_mode.clock =
7483 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
7484 &pipe_config->fdi_m_n);
79e53945
JB		 7485}
7486
7487/** Returns the currently programmed mode of the given pipe. */
7488struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7489 struct drm_crtc *crtc)
7490{
548f245b 7491 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 7492 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 7493 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 7494 struct drm_display_mode *mode;
f1f644dc 7495 struct intel_crtc_config pipe_config;
fe2b8f9d
PZ		 7496 int htot = I915_READ(HTOTAL(cpu_transcoder));
7497 int hsync = I915_READ(HSYNC(cpu_transcoder));
7498 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7499 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 7500 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 7501
7502 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7503 if (!mode)
7504 return NULL;
7505
f1f644dc
JB		 7506 /*
7507 * Construct a pipe_config sufficient for getting the clock info
7508 * back out of crtc_clock_get.
7509 *
7510 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7511 * to use a real value here instead.
7512 */
293623f7 7513 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 7514 pipe_config.pixel_multiplier = 1;
293623f7
VS		 7515 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
7516 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
7517 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 7518 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7519
7520 mode->clock = pipe_config.adjusted_mode.clock;
79e53945
JB		 7521 mode->hdisplay = (htot & 0xffff) + 1;
7522 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7523 mode->hsync_start = (hsync & 0xffff) + 1;
7524 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7525 mode->vdisplay = (vtot & 0xffff) + 1;
7526 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7527 mode->vsync_start = (vsync & 0xffff) + 1;
7528 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7529
7530 drm_mode_set_name(mode);
79e53945
JB		 7531
7532 return mode;
7533}
7534
3dec0095 7535static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7536{
7537 struct drm_device *dev = crtc->dev;
7538 drm_i915_private_t *dev_priv = dev->dev_private;
7539 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7540 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7541 int dpll_reg = DPLL(pipe);
7542 int dpll;
652c393a 7543
bad720ff 7544 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7545 return;
7546
7547 if (!dev_priv->lvds_downclock_avail)
7548 return;
7549
dbdc6479 7550 dpll = I915_READ(dpll_reg);
652c393a 7551 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7552 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7553
8ac5a6d5 7554 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7555
7556 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7557 I915_WRITE(dpll_reg, dpll);
9d0498a2 7558 intel_wait_for_vblank(dev, pipe);
dbdc6479 7559
652c393a
JB		 7560 dpll = I915_READ(dpll_reg);
7561 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7562 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7563 }
652c393a
JB		 7564}
7565
7566static void intel_decrease_pllclock(struct drm_crtc *crtc)
7567{
7568 struct drm_device *dev = crtc->dev;
7569 drm_i915_private_t *dev_priv = dev->dev_private;
7570 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7571
bad720ff 7572 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7573 return;
7574
7575 if (!dev_priv->lvds_downclock_avail)
7576 return;
7577
7578 /*
7579 * Since this is called by a timer, we should never get here in
7580 * the manual case.
7581 */
7582 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7583 int pipe = intel_crtc->pipe;
7584 int dpll_reg = DPLL(pipe);
7585 int dpll;
f6e5b160 7586
44d98a61 7587 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7588
8ac5a6d5 7589 assert_panel_unlocked(dev_priv, pipe);
652c393a 7590
dc257cf1 7591 dpll = I915_READ(dpll_reg);
652c393a
JB		 7592 dpll |= DISPLAY_RATE_SELECT_FPA1;
7593 I915_WRITE(dpll_reg, dpll);
9d0498a2 7594 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7595 dpll = I915_READ(dpll_reg);
7596 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7597 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7598 }
7599
7600}
7601
f047e395
CW		 7602void intel_mark_busy(struct drm_device *dev)
7603{
c67a470b
PZ		 7604 struct drm_i915_private *dev_priv = dev->dev_private;
7605
7606 hsw_package_c8_gpu_busy(dev_priv);
7607 i915_update_gfx_val(dev_priv);
f047e395
CW		 7608}
7609
7610void intel_mark_idle(struct drm_device *dev)
652c393a 7611{
c67a470b 7612 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 7613 struct drm_crtc *crtc;
652c393a 7614
c67a470b
PZ		 7615 hsw_package_c8_gpu_idle(dev_priv);
7616
652c393a
JB		 7617 if (!i915_powersave)
7618 return;
7619
652c393a 7620 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7621 if (!crtc->fb)
7622 continue;
7623
725a5b54 7624 intel_decrease_pllclock(crtc);
652c393a 7625 }
652c393a
JB		 7626}
7627
c65355bb
CW		 7628void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7629 struct intel_ring_buffer *ring)
652c393a 7630{
f047e395
CW		 7631 struct drm_device *dev = obj->base.dev;
7632 struct drm_crtc *crtc;
652c393a 7633
f047e395 7634 if (!i915_powersave)
acb87dfb
CW		 7635 return;
7636
652c393a
JB		 7637 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7638 if (!crtc->fb)
7639 continue;
7640
c65355bb
CW		 7641 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7642 continue;
7643
7644 intel_increase_pllclock(crtc);
7645 if (ring && intel_fbc_enabled(dev))
7646 ring->fbc_dirty = true;
652c393a
JB		 7647 }
7648}
7649
79e53945
JB		 7650static void intel_crtc_destroy(struct drm_crtc *crtc)
7651{
7652 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7653 struct drm_device *dev = crtc->dev;
7654 struct intel_unpin_work *work;
7655 unsigned long flags;
7656
7657 spin_lock_irqsave(&dev->event_lock, flags);
7658 work = intel_crtc->unpin_work;
7659 intel_crtc->unpin_work = NULL;
7660 spin_unlock_irqrestore(&dev->event_lock, flags);
7661
7662 if (work) {
7663 cancel_work_sync(&work->work);
7664 kfree(work);
7665 }
79e53945 7666
40ccc72b
MK		 7667 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7668
79e53945 7669 drm_crtc_cleanup(crtc);
67e77c5a 7670
79e53945
JB		 7671 kfree(intel_crtc);
7672}
7673
6b95a207
KH		 7674static void intel_unpin_work_fn(struct work_struct *__work)
7675{
7676 struct intel_unpin_work *work =
7677 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7678 struct drm_device *dev = work->crtc->dev;
6b95a207 7679
b4a98e57 7680 mutex_lock(&dev->struct_mutex);
1690e1eb 7681 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7682 drm_gem_object_unreference(&work->pending_flip_obj->base);
7683 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7684
b4a98e57
CW		 7685 intel_update_fbc(dev);
7686 mutex_unlock(&dev->struct_mutex);
7687
7688 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7689 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7690
6b95a207
KH		 7691 kfree(work);
7692}
7693
1afe3e9d 7694static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7695 struct drm_crtc *crtc)
6b95a207
KH		 7696{
7697 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7698 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7699 struct intel_unpin_work *work;
6b95a207
KH		 7700 unsigned long flags;
7701
7702 /* Ignore early vblank irqs */
7703 if (intel_crtc == NULL)
7704 return;
7705
7706 spin_lock_irqsave(&dev->event_lock, flags);
7707 work = intel_crtc->unpin_work;
e7d841ca
CW		 7708
7709 /* Ensure we don't miss a work->pending update ... */
7710 smp_rmb();
7711
7712 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7713 spin_unlock_irqrestore(&dev->event_lock, flags);
7714 return;
7715 }
7716
e7d841ca
CW		 7717 /* and that the unpin work is consistent wrt ->pending. */
7718 smp_rmb();
7719
6b95a207 7720 intel_crtc->unpin_work = NULL;
6b95a207 7721
45a066eb
RC		 7722 if (work->event)
7723 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7724
0af7e4df
MK		 7725 drm_vblank_put(dev, intel_crtc->pipe);
7726
6b95a207
KH		 7727 spin_unlock_irqrestore(&dev->event_lock, flags);
7728
2c10d571 7729 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7730
7731 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7732
7733 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7734}
7735
1afe3e9d
JB		 7736void intel_finish_page_flip(struct drm_device *dev, int pipe)
7737{
7738 drm_i915_private_t *dev_priv = dev->dev_private;
7739 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7740
49b14a5c 7741 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7742}
7743
7744void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7745{
7746 drm_i915_private_t *dev_priv = dev->dev_private;
7747 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7748
49b14a5c 7749 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7750}
7751
6b95a207
KH		 7752void intel_prepare_page_flip(struct drm_device *dev, int plane)
7753{
7754 drm_i915_private_t *dev_priv = dev->dev_private;
7755 struct intel_crtc *intel_crtc =
7756 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7757 unsigned long flags;
7758
e7d841ca
CW		 7759 /* NB: An MMIO update of the plane base pointer will also
7760 * generate a page-flip completion irq, i.e. every modeset
7761 * is also accompanied by a spurious intel_prepare_page_flip().
7762 */
6b95a207 7763 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7764 if (intel_crtc->unpin_work)
7765 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7766 spin_unlock_irqrestore(&dev->event_lock, flags);
7767}
7768
e7d841ca
CW		 7769inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7770{
7771 /* Ensure that the work item is consistent when activating it ... */
7772 smp_wmb();
7773 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7774 /* and that it is marked active as soon as the irq could fire. */
7775 smp_wmb();
7776}
7777
8c9f3aaf
JB		 7778static int intel_gen2_queue_flip(struct drm_device *dev,
7779 struct drm_crtc *crtc,
7780 struct drm_framebuffer *fb,
ed8d1975
KP		 7781 struct drm_i915_gem_object *obj,
7782 uint32_t flags)
8c9f3aaf
JB		 7783{
7784 struct drm_i915_private *dev_priv = dev->dev_private;
7785 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7786 u32 flip_mask;
6d90c952 7787 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7788 int ret;
7789
6d90c952 7790 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7791 if (ret)
83d4092b 7792 goto err;
8c9f3aaf 7793
6d90c952 7794 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7795 if (ret)
83d4092b 7796 goto err_unpin;
8c9f3aaf
JB		 7797
7798 /* Can't queue multiple flips, so wait for the previous
7799 * one to finish before executing the next.
7800 */
7801 if (intel_crtc->plane)
7802 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7803 else
7804 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7805 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7806 intel_ring_emit(ring, MI_NOOP);
7807 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7808 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7809 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7810 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952 7811 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7812
7813 intel_mark_page_flip_active(intel_crtc);
09246732 7814 __intel_ring_advance(ring);
83d4092b
CW		 7815 return 0;
7816
7817err_unpin:
7818 intel_unpin_fb_obj(obj);
7819err:
8c9f3aaf
JB		 7820 return ret;
7821}
7822
7823static int intel_gen3_queue_flip(struct drm_device *dev,
7824 struct drm_crtc *crtc,
7825 struct drm_framebuffer *fb,
ed8d1975
KP		 7826 struct drm_i915_gem_object *obj,
7827 uint32_t flags)
8c9f3aaf
JB		 7828{
7829 struct drm_i915_private *dev_priv = dev->dev_private;
7830 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7831 u32 flip_mask;
6d90c952 7832 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7833 int ret;
7834
6d90c952 7835 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7836 if (ret)
83d4092b 7837 goto err;
8c9f3aaf 7838
6d90c952 7839 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7840 if (ret)
83d4092b 7841 goto err_unpin;
8c9f3aaf
JB		 7842
7843 if (intel_crtc->plane)
7844 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7845 else
7846 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7847 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7848 intel_ring_emit(ring, MI_NOOP);
7849 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7850 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7851 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7852 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952
DV		 7853 intel_ring_emit(ring, MI_NOOP);
7854
e7d841ca 7855 intel_mark_page_flip_active(intel_crtc);
09246732 7856 __intel_ring_advance(ring);
83d4092b
CW		 7857 return 0;
7858
7859err_unpin:
7860 intel_unpin_fb_obj(obj);
7861err:
8c9f3aaf
JB		 7862 return ret;
7863}
7864
7865static int intel_gen4_queue_flip(struct drm_device *dev,
7866 struct drm_crtc *crtc,
7867 struct drm_framebuffer *fb,
ed8d1975
KP		 7868 struct drm_i915_gem_object *obj,
7869 uint32_t flags)
8c9f3aaf
JB		 7870{
7871 struct drm_i915_private *dev_priv = dev->dev_private;
7872 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7873 uint32_t pf, pipesrc;
6d90c952 7874 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7875 int ret;
7876
6d90c952 7877 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7878 if (ret)
83d4092b 7879 goto err;
8c9f3aaf 7880
6d90c952 7881 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7882 if (ret)
83d4092b 7883 goto err_unpin;
8c9f3aaf
JB		 7884
7885 /* i965+ uses the linear or tiled offsets from the
7886 * Display Registers (which do not change across a page-flip)
7887 * so we need only reprogram the base address.
7888 */
6d90c952
DV		 7889 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7890 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7891 intel_ring_emit(ring, fb->pitches[0]);
c2c75131 7892 intel_ring_emit(ring,
f343c5f6 7893 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
c2c75131 7894 obj->tiling_mode);
8c9f3aaf
JB		 7895
7896 /* XXX Enabling the panel-fitter across page-flip is so far
7897 * untested on non-native modes, so ignore it for now.
7898 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7899 */
7900 pf = 0;
7901 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7902 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7903
7904 intel_mark_page_flip_active(intel_crtc);
09246732 7905 __intel_ring_advance(ring);
83d4092b
CW		 7906 return 0;
7907
7908err_unpin:
7909 intel_unpin_fb_obj(obj);
7910err:
8c9f3aaf
JB		 7911 return ret;
7912}
7913
7914static int intel_gen6_queue_flip(struct drm_device *dev,
7915 struct drm_crtc *crtc,
7916 struct drm_framebuffer *fb,
ed8d1975
KP		 7917 struct drm_i915_gem_object *obj,
7918 uint32_t flags)
8c9f3aaf
JB		 7919{
7920 struct drm_i915_private *dev_priv = dev->dev_private;
7921 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7922 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7923 uint32_t pf, pipesrc;
7924 int ret;
7925
6d90c952 7926 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7927 if (ret)
83d4092b 7928 goto err;
8c9f3aaf 7929
6d90c952 7930 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7931 if (ret)
83d4092b 7932 goto err_unpin;
8c9f3aaf 7933
6d90c952
DV		 7934 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7935 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7936 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
f343c5f6 7937 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8c9f3aaf 7938
dc257cf1
DV		 7939 /* Contrary to the suggestions in the documentation,
7940 * "Enable Panel Fitter" does not seem to be required when page
7941 * flipping with a non-native mode, and worse causes a normal
7942 * modeset to fail.
7943 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7944 */
7945 pf = 0;
8c9f3aaf 7946 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7947 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7948
7949 intel_mark_page_flip_active(intel_crtc);
09246732 7950 __intel_ring_advance(ring);
83d4092b
CW		 7951 return 0;
7952
7953err_unpin:
7954 intel_unpin_fb_obj(obj);
7955err:
8c9f3aaf
JB		 7956 return ret;
7957}
7958
7c9017e5
JB		 7959static int intel_gen7_queue_flip(struct drm_device *dev,
7960 struct drm_crtc *crtc,
7961 struct drm_framebuffer *fb,
ed8d1975
KP		 7962 struct drm_i915_gem_object *obj,
7963 uint32_t flags)
7c9017e5
JB		 7964{
7965 struct drm_i915_private *dev_priv = dev->dev_private;
7966 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ffe74d75 7967 struct intel_ring_buffer *ring;
cb05d8de 7968 uint32_t plane_bit = 0;
ffe74d75
CW		 7969 int len, ret;
7970
7971 ring = obj->ring;
7972 if (ring == NULL || ring->id != RCS)
7973 ring = &dev_priv->ring[BCS];
7c9017e5
JB		 7974
7975 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7976 if (ret)
83d4092b 7977 goto err;
7c9017e5 7978
cb05d8de
DV		 7979 switch(intel_crtc->plane) {
7980 case PLANE_A:
7981 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7982 break;
7983 case PLANE_B:
7984 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7985 break;
7986 case PLANE_C:
7987 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7988 break;
7989 default:
7990 WARN_ONCE(1, "unknown plane in flip command\n");
7991 ret = -ENODEV;
ab3951eb 7992 goto err_unpin;
cb05d8de
DV		 7993 }
7994
ffe74d75
CW		 7995 len = 4;
7996 if (ring->id == RCS)
7997 len += 6;
7998
7999 ret = intel_ring_begin(ring, len);
7c9017e5 8000 if (ret)
83d4092b 8001 goto err_unpin;
7c9017e5 8002
ffe74d75
CW		 8003 /* Unmask the flip-done completion message. Note that the bspec says that
8004 * we should do this for both the BCS and RCS, and that we must not unmask
8005 * more than one flip event at any time (or ensure that one flip message
8006 * can be sent by waiting for flip-done prior to queueing new flips).
8007 * Experimentation says that BCS works despite DERRMR masking all
8008 * flip-done completion events and that unmasking all planes at once
8009 * for the RCS also doesn't appear to drop events. Setting the DERRMR
8010 * to zero does lead to lockups within MI_DISPLAY_FLIP.
8011 */
8012 if (ring->id == RCS) {
8013 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8014 intel_ring_emit(ring, DERRMR);
8015 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8016 DERRMR_PIPEB_PRI_FLIP_DONE |
8017 DERRMR_PIPEC_PRI_FLIP_DONE));
8018 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
8019 intel_ring_emit(ring, DERRMR);
8020 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8021 }
8022
cb05d8de 8023 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 8024 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
f343c5f6 8025 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7c9017e5 8026 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 8027
8028 intel_mark_page_flip_active(intel_crtc);
09246732 8029 __intel_ring_advance(ring);
83d4092b
CW		 8030 return 0;
8031
8032err_unpin:
8033 intel_unpin_fb_obj(obj);
8034err:
7c9017e5
JB		 8035 return ret;
8036}
8037
8c9f3aaf
JB		 8038static int intel_default_queue_flip(struct drm_device *dev,
8039 struct drm_crtc *crtc,
8040 struct drm_framebuffer *fb,
ed8d1975
KP		 8041 struct drm_i915_gem_object *obj,
8042 uint32_t flags)
8c9f3aaf
JB		 8043{
8044 return -ENODEV;
8045}
8046
6b95a207
KH		 8047static int intel_crtc_page_flip(struct drm_crtc *crtc,
8048 struct drm_framebuffer *fb,
ed8d1975
KP		 8049 struct drm_pending_vblank_event *event,
8050 uint32_t page_flip_flags)
6b95a207
KH		 8051{
8052 struct drm_device *dev = crtc->dev;
8053 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 8054 struct drm_framebuffer *old_fb = crtc->fb;
8055 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 8056 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8057 struct intel_unpin_work *work;
8c9f3aaf 8058 unsigned long flags;
52e68630 8059 int ret;
6b95a207 8060
e6a595d2
VS		 8061 /* Can't change pixel format via MI display flips. */
8062 if (fb->pixel_format != crtc->fb->pixel_format)
8063 return -EINVAL;
8064
8065 /*
8066 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8067 * Note that pitch changes could also affect these register.
8068 */
8069 if (INTEL_INFO(dev)->gen > 3 &&
8070 (fb->offsets[0] != crtc->fb->offsets[0] ||
8071 fb->pitches[0] != crtc->fb->pitches[0]))
8072 return -EINVAL;
8073
6b95a207
KH		 8074 work = kzalloc(sizeof *work, GFP_KERNEL);
8075 if (work == NULL)
8076 return -ENOMEM;
8077
6b95a207 8078 work->event = event;
b4a98e57 8079 work->crtc = crtc;
4a35f83b 8080 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 8081 INIT_WORK(&work->work, intel_unpin_work_fn);
8082
7317c75e
JB		 8083 ret = drm_vblank_get(dev, intel_crtc->pipe);
8084 if (ret)
8085 goto free_work;
8086
6b95a207
KH		 8087 /* We borrow the event spin lock for protecting unpin_work */
8088 spin_lock_irqsave(&dev->event_lock, flags);
8089 if (intel_crtc->unpin_work) {
8090 spin_unlock_irqrestore(&dev->event_lock, flags);
8091 kfree(work);
7317c75e 8092 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 8093
8094 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 8095 return -EBUSY;
8096 }
8097 intel_crtc->unpin_work = work;
8098 spin_unlock_irqrestore(&dev->event_lock, flags);
8099
b4a98e57
CW		 8100 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8101 flush_workqueue(dev_priv->wq);
8102
79158103
CW		 8103 ret = i915_mutex_lock_interruptible(dev);
8104 if (ret)
8105 goto cleanup;
6b95a207 8106
75dfca80 8107 /* Reference the objects for the scheduled work. */
05394f39
CW		 8108 drm_gem_object_reference(&work->old_fb_obj->base);
8109 drm_gem_object_reference(&obj->base);
6b95a207
KH		 8110
8111 crtc->fb = fb;
96b099fd 8112
e1f99ce6 8113 work->pending_flip_obj = obj;
e1f99ce6 8114
4e5359cd
SF		 8115 work->enable_stall_check = true;
8116
b4a98e57 8117 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 8118 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 8119
ed8d1975 8120 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8c9f3aaf
JB		 8121 if (ret)
8122 goto cleanup_pending;
6b95a207 8123
7782de3b 8124 intel_disable_fbc(dev);
c65355bb 8125 intel_mark_fb_busy(obj, NULL);
6b95a207
KH		 8126 mutex_unlock(&dev->struct_mutex);
8127
e5510fac
JB		 8128 trace_i915_flip_request(intel_crtc->plane, obj);
8129
6b95a207 8130 return 0;
96b099fd 8131
8c9f3aaf 8132cleanup_pending:
b4a98e57 8133 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 8134 crtc->fb = old_fb;
05394f39
CW		 8135 drm_gem_object_unreference(&work->old_fb_obj->base);
8136 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 8137 mutex_unlock(&dev->struct_mutex);
8138
79158103 8139cleanup:
96b099fd
CW		 8140 spin_lock_irqsave(&dev->event_lock, flags);
8141 intel_crtc->unpin_work = NULL;
8142 spin_unlock_irqrestore(&dev->event_lock, flags);
8143
7317c75e
JB		 8144 drm_vblank_put(dev, intel_crtc->pipe);
8145free_work:
96b099fd
CW		 8146 kfree(work);
8147
8148 return ret;
6b95a207
KH		 8149}
8150
f6e5b160 8151static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 8152 .mode_set_base_atomic = intel_pipe_set_base_atomic,
8153 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 8154};
8155
50f56119
DV		 8156static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8157 struct drm_crtc *crtc)
8158{
8159 struct drm_device *dev;
8160 struct drm_crtc *tmp;
8161 int crtc_mask = 1;
47f1c6c9 8162
50f56119 8163 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 8164
50f56119 8165 dev = crtc->dev;
47f1c6c9 8166
50f56119
DV		 8167 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8168 if (tmp == crtc)
8169 break;
8170 crtc_mask <<= 1;
8171 }
47f1c6c9 8172
50f56119
DV		 8173 if (encoder->possible_crtcs & crtc_mask)
8174 return true;
8175 return false;
47f1c6c9 8176}
79e53945 8177
9a935856
DV		 8178/**
8179 * intel_modeset_update_staged_output_state
8180 *
8181 * Updates the staged output configuration state, e.g. after we've read out the
8182 * current hw state.
8183 */
8184static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 8185{
9a935856
DV		 8186 struct intel_encoder *encoder;
8187 struct intel_connector *connector;
f6e5b160 8188
9a935856
DV		 8189 list_for_each_entry(connector, &dev->mode_config.connector_list,
8190 base.head) {
8191 connector->new_encoder =
8192 to_intel_encoder(connector->base.encoder);
8193 }
f6e5b160 8194
9a935856
DV		 8195 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8196 base.head) {
8197 encoder->new_crtc =
8198 to_intel_crtc(encoder->base.crtc);
8199 }
f6e5b160
CW		 8200}
8201
9a935856
DV		 8202/**
8203 * intel_modeset_commit_output_state
8204 *
8205 * This function copies the stage display pipe configuration to the real one.
8206 */
8207static void intel_modeset_commit_output_state(struct drm_device *dev)
8208{
8209 struct intel_encoder *encoder;
8210 struct intel_connector *connector;
f6e5b160 8211
9a935856
DV		 8212 list_for_each_entry(connector, &dev->mode_config.connector_list,
8213 base.head) {
8214 connector->base.encoder = &connector->new_encoder->base;
8215 }
f6e5b160 8216
9a935856
DV		 8217 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8218 base.head) {
8219 encoder->base.crtc = &encoder->new_crtc->base;
8220 }
8221}
8222
050f7aeb
DV		 8223static void
8224connected_sink_compute_bpp(struct intel_connector * connector,
8225 struct intel_crtc_config *pipe_config)
8226{
8227 int bpp = pipe_config->pipe_bpp;
8228
8229 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8230 connector->base.base.id,
8231 drm_get_connector_name(&connector->base));
8232
8233 /* Don't use an invalid EDID bpc value */
8234 if (connector->base.display_info.bpc &&
8235 connector->base.display_info.bpc * 3 < bpp) {
8236 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8237 bpp, connector->base.display_info.bpc*3);
8238 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8239 }
8240
8241 /* Clamp bpp to 8 on screens without EDID 1.4 */
8242 if (connector->base.display_info.bpc == 0 && bpp > 24) {
8243 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8244 bpp);
8245 pipe_config->pipe_bpp = 24;
8246 }
8247}
8248
4e53c2e0 8249static int
050f7aeb
DV		 8250compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8251 struct drm_framebuffer *fb,
8252 struct intel_crtc_config *pipe_config)
4e53c2e0 8253{
050f7aeb
DV		 8254 struct drm_device *dev = crtc->base.dev;
8255 struct intel_connector *connector;
4e53c2e0
DV		 8256 int bpp;
8257
d42264b1
DV		 8258 switch (fb->pixel_format) {
8259 case DRM_FORMAT_C8:
4e53c2e0
DV		 8260 bpp = 8*3; /* since we go through a colormap */
8261 break;
d42264b1
DV		 8262 case DRM_FORMAT_XRGB1555:
8263 case DRM_FORMAT_ARGB1555:
8264 /* checked in intel_framebuffer_init already */
8265 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8266 return -EINVAL;
8267 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 8268 bpp = 6*3; /* min is 18bpp */
8269 break;
d42264b1
DV		 8270 case DRM_FORMAT_XBGR8888:
8271 case DRM_FORMAT_ABGR8888:
8272 /* checked in intel_framebuffer_init already */
8273 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8274 return -EINVAL;
8275 case DRM_FORMAT_XRGB8888:
8276 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 8277 bpp = 8*3;
8278 break;
d42264b1
DV		 8279 case DRM_FORMAT_XRGB2101010:
8280 case DRM_FORMAT_ARGB2101010:
8281 case DRM_FORMAT_XBGR2101010:
8282 case DRM_FORMAT_ABGR2101010:
8283 /* checked in intel_framebuffer_init already */
8284 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 8285 return -EINVAL;
4e53c2e0
DV		 8286 bpp = 10*3;
8287 break;
baba133a 8288 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 8289 default:
8290 DRM_DEBUG_KMS("unsupported depth\n");
8291 return -EINVAL;
8292 }
8293
4e53c2e0
DV		 8294 pipe_config->pipe_bpp = bpp;
8295
8296 /* Clamp display bpp to EDID value */
8297 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 8298 base.head) {
1b829e05
DV		 8299 if (!connector->new_encoder ||
8300 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 8301 continue;
8302
050f7aeb 8303 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 8304 }
8305
8306 return bpp;
8307}
8308
c0b03411
DV		 8309static void intel_dump_pipe_config(struct intel_crtc *crtc,
8310 struct intel_crtc_config *pipe_config,
8311 const char *context)
8312{
8313 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8314 context, pipe_name(crtc->pipe));
8315
8316 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8317 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8318 pipe_config->pipe_bpp, pipe_config->dither);
8319 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8320 pipe_config->has_pch_encoder,
8321 pipe_config->fdi_lanes,
8322 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8323 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8324 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 8325 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8326 pipe_config->has_dp_encoder,
8327 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8328 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8329 pipe_config->dp_m_n.tu);
c0b03411
DV		 8330 DRM_DEBUG_KMS("requested mode:\n");
8331 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8332 DRM_DEBUG_KMS("adjusted mode:\n");
8333 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
d71b8d4a 8334 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
c0b03411
DV		 8335 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8336 pipe_config->gmch_pfit.control,
8337 pipe_config->gmch_pfit.pgm_ratios,
8338 pipe_config->gmch_pfit.lvds_border_bits);
8339 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
8340 pipe_config->pch_pfit.pos,
8341 pipe_config->pch_pfit.size);
42db64ef 8342 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
c0b03411
DV		 8343}
8344
accfc0c5
DV		 8345static bool check_encoder_cloning(struct drm_crtc *crtc)
8346{
8347 int num_encoders = 0;
8348 bool uncloneable_encoders = false;
8349 struct intel_encoder *encoder;
8350
8351 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8352 base.head) {
8353 if (&encoder->new_crtc->base != crtc)
8354 continue;
8355
8356 num_encoders++;
8357 if (!encoder->cloneable)
8358 uncloneable_encoders = true;
8359 }
8360
8361 return !(num_encoders > 1 && uncloneable_encoders);
8362}
8363
b8cecdf5
DV		 8364static struct intel_crtc_config *
8365intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 8366 struct drm_framebuffer *fb,
b8cecdf5 8367 struct drm_display_mode *mode)
ee7b9f93 8368{
7758a113 8369 struct drm_device *dev = crtc->dev;
7758a113 8370 struct intel_encoder *encoder;
b8cecdf5 8371 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 8372 int plane_bpp, ret = -EINVAL;
8373 bool retry = true;
ee7b9f93 8374
accfc0c5
DV		 8375 if (!check_encoder_cloning(crtc)) {
8376 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8377 return ERR_PTR(-EINVAL);
8378 }
8379
b8cecdf5
DV		 8380 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8381 if (!pipe_config)
7758a113
DV		 8382 return ERR_PTR(-ENOMEM);
8383
b8cecdf5
DV		 8384 drm_mode_copy(&pipe_config->adjusted_mode, mode);
8385 drm_mode_copy(&pipe_config->requested_mode, mode);
e143a21c
DV		 8386 pipe_config->cpu_transcoder =
8387 (enum transcoder) to_intel_crtc(crtc)->pipe;
c0d43d62 8388 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 8389
2960bc9c
ID		 8390 /*
8391 * Sanitize sync polarity flags based on requested ones. If neither
8392 * positive or negative polarity is requested, treat this as meaning
8393 * negative polarity.
8394 */
8395 if (!(pipe_config->adjusted_mode.flags &
8396 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8397 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8398
8399 if (!(pipe_config->adjusted_mode.flags &
8400 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8401 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8402
050f7aeb
DV		 8403 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8404 * plane pixel format and any sink constraints into account. Returns the
8405 * source plane bpp so that dithering can be selected on mismatches
8406 * after encoders and crtc also have had their say. */
8407 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8408 fb, pipe_config);
4e53c2e0
DV		 8409 if (plane_bpp < 0)
8410 goto fail;
8411
e29c22c0 8412encoder_retry:
ef1b460d 8413 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 8414 pipe_config->port_clock = 0;
ef1b460d 8415 pipe_config->pixel_multiplier = 1;
ff9a6750 8416
135c81b8
DV		 8417 /* Fill in default crtc timings, allow encoders to overwrite them. */
8418 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, 0);
8419
7758a113
DV		 8420 /* Pass our mode to the connectors and the CRTC to give them a chance to
8421 * adjust it according to limitations or connector properties, and also
8422 * a chance to reject the mode entirely.
47f1c6c9 8423 */
7758a113
DV		 8424 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8425 base.head) {
47f1c6c9 8426
7758a113
DV		 8427 if (&encoder->new_crtc->base != crtc)
8428 continue;
7ae89233 8429
efea6e8e
DV		 8430 if (!(encoder->compute_config(encoder, pipe_config))) {
8431 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 8432 goto fail;
8433 }
ee7b9f93 8434 }
47f1c6c9 8435
ff9a6750
DV		 8436 /* Set default port clock if not overwritten by the encoder. Needs to be
8437 * done afterwards in case the encoder adjusts the mode. */
8438 if (!pipe_config->port_clock)
3c52f4eb
VS		 8439 pipe_config->port_clock = pipe_config->adjusted_mode.clock *
8440 pipe_config->pixel_multiplier;
ff9a6750 8441
a43f6e0f 8442 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 8443 if (ret < 0) {
7758a113
DV		 8444 DRM_DEBUG_KMS("CRTC fixup failed\n");
8445 goto fail;
ee7b9f93 8446 }
e29c22c0
DV		 8447
8448 if (ret == RETRY) {
8449 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8450 ret = -EINVAL;
8451 goto fail;
8452 }
8453
8454 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8455 retry = false;
8456 goto encoder_retry;
8457 }
8458
4e53c2e0
DV		 8459 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8460 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8461 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8462
b8cecdf5 8463 return pipe_config;
7758a113 8464fail:
b8cecdf5 8465 kfree(pipe_config);
e29c22c0 8466 return ERR_PTR(ret);
ee7b9f93 8467}
47f1c6c9 8468
e2e1ed41
DV		 8469/* Computes which crtcs are affected and sets the relevant bits in the mask. For
8470 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8471static void
8472intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8473 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 8474{
8475 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 8476 struct drm_device *dev = crtc->dev;
8477 struct intel_encoder *encoder;
8478 struct intel_connector *connector;
8479 struct drm_crtc *tmp_crtc;
79e53945 8480
e2e1ed41 8481 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 8482
e2e1ed41
DV		 8483 /* Check which crtcs have changed outputs connected to them, these need
8484 * to be part of the prepare_pipes mask. We don't (yet) support global
8485 * modeset across multiple crtcs, so modeset_pipes will only have one
8486 * bit set at most. */
8487 list_for_each_entry(connector, &dev->mode_config.connector_list,
8488 base.head) {
8489 if (connector->base.encoder == &connector->new_encoder->base)
8490 continue;
79e53945 8491
e2e1ed41
DV		 8492 if (connector->base.encoder) {
8493 tmp_crtc = connector->base.encoder->crtc;
8494
8495 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8496 }
8497
8498 if (connector->new_encoder)
8499 *prepare_pipes |=
8500 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 8501 }
8502
e2e1ed41
DV		 8503 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8504 base.head) {
8505 if (encoder->base.crtc == &encoder->new_crtc->base)
8506 continue;
8507
8508 if (encoder->base.crtc) {
8509 tmp_crtc = encoder->base.crtc;
8510
8511 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8512 }
8513
8514 if (encoder->new_crtc)
8515 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 8516 }
8517
e2e1ed41
DV		 8518 /* Check for any pipes that will be fully disabled ... */
8519 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8520 base.head) {
8521 bool used = false;
22fd0fab 8522
e2e1ed41
DV		 8523 /* Don't try to disable disabled crtcs. */
8524 if (!intel_crtc->base.enabled)
8525 continue;
7e7d76c3 8526
e2e1ed41
DV		 8527 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8528 base.head) {
8529 if (encoder->new_crtc == intel_crtc)
8530 used = true;
8531 }
8532
8533 if (!used)
8534 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 8535 }
8536
e2e1ed41
DV		 8537
8538 /* set_mode is also used to update properties on life display pipes. */
8539 intel_crtc = to_intel_crtc(crtc);
8540 if (crtc->enabled)
8541 *prepare_pipes |= 1 << intel_crtc->pipe;
8542
b6c5164d
DV		 8543 /*
8544 * For simplicity do a full modeset on any pipe where the output routing
8545 * changed. We could be more clever, but that would require us to be
8546 * more careful with calling the relevant encoder->mode_set functions.
8547 */
e2e1ed41
DV		 8548 if (*prepare_pipes)
8549 *modeset_pipes = *prepare_pipes;
8550
8551 /* ... and mask these out. */
8552 *modeset_pipes &= ~(*disable_pipes);
8553 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 8554
8555 /*
8556 * HACK: We don't (yet) fully support global modesets. intel_set_config
8557 * obies this rule, but the modeset restore mode of
8558 * intel_modeset_setup_hw_state does not.
8559 */
8560 *modeset_pipes &= 1 << intel_crtc->pipe;
8561 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 8562
8563 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8564 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 8565}
79e53945 8566
ea9d758d 8567static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 8568{
ea9d758d 8569 struct drm_encoder *encoder;
f6e5b160 8570 struct drm_device *dev = crtc->dev;
f6e5b160 8571
ea9d758d
DV		 8572 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8573 if (encoder->crtc == crtc)
8574 return true;
8575
8576 return false;
8577}
8578
8579static void
8580intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8581{
8582 struct intel_encoder *intel_encoder;
8583 struct intel_crtc *intel_crtc;
8584 struct drm_connector *connector;
8585
8586 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8587 base.head) {
8588 if (!intel_encoder->base.crtc)
8589 continue;
8590
8591 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8592
8593 if (prepare_pipes & (1 << intel_crtc->pipe))
8594 intel_encoder->connectors_active = false;
8595 }
8596
8597 intel_modeset_commit_output_state(dev);
8598
8599 /* Update computed state. */
8600 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8601 base.head) {
8602 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8603 }
8604
8605 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8606 if (!connector->encoder || !connector->encoder->crtc)
8607 continue;
8608
8609 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8610
8611 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8612 struct drm_property *dpms_property =
8613 dev->mode_config.dpms_property;
8614
ea9d758d 8615 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8616 drm_object_property_set_value(&connector->base,
68d34720
DV		 8617 dpms_property,
8618 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8619
8620 intel_encoder = to_intel_encoder(connector->encoder);
8621 intel_encoder->connectors_active = true;
8622 }
8623 }
8624
8625}
8626
3bd26263 8627static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 8628{
3bd26263 8629 int diff;
f1f644dc
JB		 8630
8631 if (clock1 == clock2)
8632 return true;
8633
8634 if (!clock1 || !clock2)
8635 return false;
8636
8637 diff = abs(clock1 - clock2);
8638
8639 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8640 return true;
8641
8642 return false;
8643}
8644
25c5b266
DV		 8645#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8646 list_for_each_entry((intel_crtc), \
8647 &(dev)->mode_config.crtc_list, \
8648 base.head) \
0973f18f 8649 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8650
0e8ffe1b 8651static bool
2fa2fe9a
DV		 8652intel_pipe_config_compare(struct drm_device *dev,
8653 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8654 struct intel_crtc_config *pipe_config)
8655{
66e985c0
DV		 8656#define PIPE_CONF_CHECK_X(name) \
8657 if (current_config->name != pipe_config->name) { \
8658 DRM_ERROR("mismatch in " #name " " \
8659 "(expected 0x%08x, found 0x%08x)\n", \
8660 current_config->name, \
8661 pipe_config->name); \
8662 return false; \
8663 }
8664
08a24034
DV		 8665#define PIPE_CONF_CHECK_I(name) \
8666 if (current_config->name != pipe_config->name) { \
8667 DRM_ERROR("mismatch in " #name " " \
8668 "(expected %i, found %i)\n", \
8669 current_config->name, \
8670 pipe_config->name); \
8671 return false; \
88adfff1
DV		 8672 }
8673
1bd1bd80
DV		 8674#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8675 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 8676 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 8677 "(expected %i, found %i)\n", \
8678 current_config->name & (mask), \
8679 pipe_config->name & (mask)); \
8680 return false; \
8681 }
8682
5e550656
VS		 8683#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
8684 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
8685 DRM_ERROR("mismatch in " #name " " \
8686 "(expected %i, found %i)\n", \
8687 current_config->name, \
8688 pipe_config->name); \
8689 return false; \
8690 }
8691
bb760063
DV		 8692#define PIPE_CONF_QUIRK(quirk) \
8693 ((current_config->quirks | pipe_config->quirks) & (quirk))
8694
eccb140b
DV		 8695 PIPE_CONF_CHECK_I(cpu_transcoder);
8696
08a24034
DV		 8697 PIPE_CONF_CHECK_I(has_pch_encoder);
8698 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8699 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8700 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8701 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8702 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8703 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8704
eb14cb74
VS		 8705 PIPE_CONF_CHECK_I(has_dp_encoder);
8706 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
8707 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
8708 PIPE_CONF_CHECK_I(dp_m_n.link_m);
8709 PIPE_CONF_CHECK_I(dp_m_n.link_n);
8710 PIPE_CONF_CHECK_I(dp_m_n.tu);
8711
1bd1bd80
DV		 8712 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8713 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8714 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8715 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8716 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8717 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8718
8719 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8720 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8721 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8722 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8723 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8724 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8725
c93f54cf 8726 PIPE_CONF_CHECK_I(pixel_multiplier);
6c49f241 8727
1bd1bd80
DV		 8728 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8729 DRM_MODE_FLAG_INTERLACE);
8730
bb760063
DV		 8731 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8732 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8733 DRM_MODE_FLAG_PHSYNC);
8734 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8735 DRM_MODE_FLAG_NHSYNC);
8736 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8737 DRM_MODE_FLAG_PVSYNC);
8738 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8739 DRM_MODE_FLAG_NVSYNC);
8740 }
045ac3b5 8741
1bd1bd80
DV		 8742 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8743 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8744
2fa2fe9a
DV		 8745 PIPE_CONF_CHECK_I(gmch_pfit.control);
8746 /* pfit ratios are autocomputed by the hw on gen4+ */
8747 if (INTEL_INFO(dev)->gen < 4)
8748 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8749 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8750 PIPE_CONF_CHECK_I(pch_pfit.pos);
8751 PIPE_CONF_CHECK_I(pch_pfit.size);
8752
42db64ef
PZ		 8753 PIPE_CONF_CHECK_I(ips_enabled);
8754
c0d43d62 8755 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 8756 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 8757 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 8758 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8759 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
c0d43d62 8760
42571aef
VS		 8761 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
8762 PIPE_CONF_CHECK_I(pipe_bpp);
8763
d71b8d4a 8764 if (!IS_HASWELL(dev)) {
5e550656 8765 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.clock);
d71b8d4a
VS		 8766 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
8767 }
5e550656 8768
66e985c0 8769#undef PIPE_CONF_CHECK_X
08a24034 8770#undef PIPE_CONF_CHECK_I
1bd1bd80 8771#undef PIPE_CONF_CHECK_FLAGS
5e550656 8772#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 8773#undef PIPE_CONF_QUIRK
88adfff1 8774
0e8ffe1b
DV		 8775 return true;
8776}
8777
91d1b4bd
DV		 8778static void
8779check_connector_state(struct drm_device *dev)
8af6cf88 8780{
8af6cf88
DV		 8781 struct intel_connector *connector;
8782
8783 list_for_each_entry(connector, &dev->mode_config.connector_list,
8784 base.head) {
8785 /* This also checks the encoder/connector hw state with the
8786 * ->get_hw_state callbacks. */
8787 intel_connector_check_state(connector);
8788
8789 WARN(&connector->new_encoder->base != connector->base.encoder,
8790 "connector's staged encoder doesn't match current encoder\n");
8791 }
91d1b4bd
DV		 8792}
8793
8794static void
8795check_encoder_state(struct drm_device *dev)
8796{
8797 struct intel_encoder *encoder;
8798 struct intel_connector *connector;
8af6cf88
DV		 8799
8800 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8801 base.head) {
8802 bool enabled = false;
8803 bool active = false;
8804 enum pipe pipe, tracked_pipe;
8805
8806 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8807 encoder->base.base.id,
8808 drm_get_encoder_name(&encoder->base));
8809
8810 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8811 "encoder's stage crtc doesn't match current crtc\n");
8812 WARN(encoder->connectors_active && !encoder->base.crtc,
8813 "encoder's active_connectors set, but no crtc\n");
8814
8815 list_for_each_entry(connector, &dev->mode_config.connector_list,
8816 base.head) {
8817 if (connector->base.encoder != &encoder->base)
8818 continue;
8819 enabled = true;
8820 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8821 active = true;
8822 }
8823 WARN(!!encoder->base.crtc != enabled,
8824 "encoder's enabled state mismatch "
8825 "(expected %i, found %i)\n",
8826 !!encoder->base.crtc, enabled);
8827 WARN(active && !encoder->base.crtc,
8828 "active encoder with no crtc\n");
8829
8830 WARN(encoder->connectors_active != active,
8831 "encoder's computed active state doesn't match tracked active state "
8832 "(expected %i, found %i)\n", active, encoder->connectors_active);
8833
8834 active = encoder->get_hw_state(encoder, &pipe);
8835 WARN(active != encoder->connectors_active,
8836 "encoder's hw state doesn't match sw tracking "
8837 "(expected %i, found %i)\n",
8838 encoder->connectors_active, active);
8839
8840 if (!encoder->base.crtc)
8841 continue;
8842
8843 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8844 WARN(active && pipe != tracked_pipe,
8845 "active encoder's pipe doesn't match"
8846 "(expected %i, found %i)\n",
8847 tracked_pipe, pipe);
8848
8849 }
91d1b4bd
DV		 8850}
8851
8852static void
8853check_crtc_state(struct drm_device *dev)
8854{
8855 drm_i915_private_t *dev_priv = dev->dev_private;
8856 struct intel_crtc *crtc;
8857 struct intel_encoder *encoder;
8858 struct intel_crtc_config pipe_config;
8af6cf88
DV		 8859
8860 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8861 base.head) {
8862 bool enabled = false;
8863 bool active = false;
8864
045ac3b5
JB		 8865 memset(&pipe_config, 0, sizeof(pipe_config));
8866
8af6cf88
DV		 8867 DRM_DEBUG_KMS("[CRTC:%d]\n",
8868 crtc->base.base.id);
8869
8870 WARN(crtc->active && !crtc->base.enabled,
8871 "active crtc, but not enabled in sw tracking\n");
8872
8873 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8874 base.head) {
8875 if (encoder->base.crtc != &crtc->base)
8876 continue;
8877 enabled = true;
8878 if (encoder->connectors_active)
8879 active = true;
8880 }
6c49f241 8881
8af6cf88
DV		 8882 WARN(active != crtc->active,
8883 "crtc's computed active state doesn't match tracked active state "
8884 "(expected %i, found %i)\n", active, crtc->active);
8885 WARN(enabled != crtc->base.enabled,
8886 "crtc's computed enabled state doesn't match tracked enabled state "
8887 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8888
0e8ffe1b
DV		 8889 active = dev_priv->display.get_pipe_config(crtc,
8890 &pipe_config);
d62cf62a
DV		 8891
8892 /* hw state is inconsistent with the pipe A quirk */
8893 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8894 active = crtc->active;
8895
6c49f241
DV		 8896 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8897 base.head) {
3eaba51c 8898 enum pipe pipe;
6c49f241
DV		 8899 if (encoder->base.crtc != &crtc->base)
8900 continue;
3eaba51c
VS		 8901 if (encoder->get_config &&
8902 encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 8903 encoder->get_config(encoder, &pipe_config);
8904 }
8905
0e8ffe1b
DV		 8906 WARN(crtc->active != active,
8907 "crtc active state doesn't match with hw state "
8908 "(expected %i, found %i)\n", crtc->active, active);
8909
c0b03411
DV		 8910 if (active &&
8911 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8912 WARN(1, "pipe state doesn't match!\n");
8913 intel_dump_pipe_config(crtc, &pipe_config,
8914 "[hw state]");
8915 intel_dump_pipe_config(crtc, &crtc->config,
8916 "[sw state]");
8917 }
8af6cf88
DV		 8918 }
8919}
8920
91d1b4bd
DV		 8921static void
8922check_shared_dpll_state(struct drm_device *dev)
8923{
8924 drm_i915_private_t *dev_priv = dev->dev_private;
8925 struct intel_crtc *crtc;
8926 struct intel_dpll_hw_state dpll_hw_state;
8927 int i;
5358901f
DV		 8928
8929 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8930 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8931 int enabled_crtcs = 0, active_crtcs = 0;
8932 bool active;
8933
8934 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8935
8936 DRM_DEBUG_KMS("%s\n", pll->name);
8937
8938 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8939
8940 WARN(pll->active > pll->refcount,
8941 "more active pll users than references: %i vs %i\n",
8942 pll->active, pll->refcount);
8943 WARN(pll->active && !pll->on,
8944 "pll in active use but not on in sw tracking\n");
35c95375
DV		 8945 WARN(pll->on && !pll->active,
8946 "pll in on but not on in use in sw tracking\n");
5358901f
DV		 8947 WARN(pll->on != active,
8948 "pll on state mismatch (expected %i, found %i)\n",
8949 pll->on, active);
8950
8951 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8952 base.head) {
8953 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8954 enabled_crtcs++;
8955 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8956 active_crtcs++;
8957 }
8958 WARN(pll->active != active_crtcs,
8959 "pll active crtcs mismatch (expected %i, found %i)\n",
8960 pll->active, active_crtcs);
8961 WARN(pll->refcount != enabled_crtcs,
8962 "pll enabled crtcs mismatch (expected %i, found %i)\n",
8963 pll->refcount, enabled_crtcs);
66e985c0
DV		 8964
8965 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8966 sizeof(dpll_hw_state)),
8967 "pll hw state mismatch\n");
5358901f 8968 }
8af6cf88
DV		 8969}
8970
91d1b4bd
DV		 8971void
8972intel_modeset_check_state(struct drm_device *dev)
8973{
8974 check_connector_state(dev);
8975 check_encoder_state(dev);
8976 check_crtc_state(dev);
8977 check_shared_dpll_state(dev);
8978}
8979
18442d08
VS		 8980void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
8981 int dotclock)
8982{
8983 /*
8984 * FDI already provided one idea for the dotclock.
8985 * Yell if the encoder disagrees.
8986 */
8987 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.clock, dotclock),
8988 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
8989 pipe_config->adjusted_mode.clock, dotclock);
8990}
8991
f30da187
DV		 8992static int __intel_set_mode(struct drm_crtc *crtc,
8993 struct drm_display_mode *mode,
8994 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 8995{
8996 struct drm_device *dev = crtc->dev;
dbf2b54e 8997 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 8998 struct drm_display_mode *saved_mode, *saved_hwmode;
8999 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 9000 struct intel_crtc *intel_crtc;
9001 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 9002 int ret = 0;
a6778b3c 9003
3ac18232 9004 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 9005 if (!saved_mode)
9006 return -ENOMEM;
3ac18232 9007 saved_hwmode = saved_mode + 1;
a6778b3c 9008
e2e1ed41 9009 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 9010 &prepare_pipes, &disable_pipes);
9011
3ac18232
TG		 9012 *saved_hwmode = crtc->hwmode;
9013 *saved_mode = crtc->mode;
a6778b3c 9014
25c5b266
DV		 9015 /* Hack: Because we don't (yet) support global modeset on multiple
9016 * crtcs, we don't keep track of the new mode for more than one crtc.
9017 * Hence simply check whether any bit is set in modeset_pipes in all the
9018 * pieces of code that are not yet converted to deal with mutliple crtcs
9019 * changing their mode at the same time. */
25c5b266 9020 if (modeset_pipes) {
4e53c2e0 9021 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 9022 if (IS_ERR(pipe_config)) {
9023 ret = PTR_ERR(pipe_config);
9024 pipe_config = NULL;
9025
3ac18232 9026 goto out;
25c5b266 9027 }
c0b03411
DV		 9028 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9029 "[modeset]");
25c5b266 9030 }
a6778b3c 9031
460da916
DV		 9032 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9033 intel_crtc_disable(&intel_crtc->base);
9034
ea9d758d
DV		 9035 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9036 if (intel_crtc->base.enabled)
9037 dev_priv->display.crtc_disable(&intel_crtc->base);
9038 }
a6778b3c 9039
6c4c86f5
DV		 9040 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9041 * to set it here already despite that we pass it down the callchain.
f6e5b160 9042 */
b8cecdf5 9043 if (modeset_pipes) {
25c5b266 9044 crtc->mode = *mode;
b8cecdf5
DV		 9045 /* mode_set/enable/disable functions rely on a correct pipe
9046 * config. */
9047 to_intel_crtc(crtc)->config = *pipe_config;
9048 }
7758a113 9049
ea9d758d
DV		 9050 /* Only after disabling all output pipelines that will be changed can we
9051 * update the the output configuration. */
9052 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 9053
47fab737
DV		 9054 if (dev_priv->display.modeset_global_resources)
9055 dev_priv->display.modeset_global_resources(dev);
9056
a6778b3c
DV		 9057 /* Set up the DPLL and any encoders state that needs to adjust or depend
9058 * on the DPLL.
f6e5b160 9059 */
25c5b266 9060 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 9061 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 9062 x, y, fb);
9063 if (ret)
9064 goto done;
a6778b3c
DV		 9065 }
9066
9067 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 9068 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9069 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 9070
25c5b266
DV		 9071 if (modeset_pipes) {
9072 /* Store real post-adjustment hardware mode. */
b8cecdf5 9073 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 9074
25c5b266
DV		 9075 /* Calculate and store various constants which
9076 * are later needed by vblank and swap-completion
9077 * timestamping. They are derived from true hwmode.
9078 */
9079 drm_calc_timestamping_constants(crtc);
9080 }
a6778b3c
DV		 9081
9082 /* FIXME: add subpixel order */
9083done:
c0c36b94 9084 if (ret && crtc->enabled) {
3ac18232
TG		 9085 crtc->hwmode = *saved_hwmode;
9086 crtc->mode = *saved_mode;
a6778b3c
DV		 9087 }
9088
3ac18232 9089out:
b8cecdf5 9090 kfree(pipe_config);
3ac18232 9091 kfree(saved_mode);
a6778b3c 9092 return ret;
f6e5b160
CW		 9093}
9094
e7457a9a
DL		 9095static int intel_set_mode(struct drm_crtc *crtc,
9096 struct drm_display_mode *mode,
9097 int x, int y, struct drm_framebuffer *fb)
f30da187
DV		 9098{
9099 int ret;
9100
9101 ret = __intel_set_mode(crtc, mode, x, y, fb);
9102
9103 if (ret == 0)
9104 intel_modeset_check_state(crtc->dev);
9105
9106 return ret;
9107}
9108
c0c36b94
CW		 9109void intel_crtc_restore_mode(struct drm_crtc *crtc)
9110{
9111 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9112}
9113
25c5b266
DV		 9114#undef for_each_intel_crtc_masked
9115
d9e55608
DV		 9116static void intel_set_config_free(struct intel_set_config *config)
9117{
9118 if (!config)
9119 return;
9120
1aa4b628
DV		 9121 kfree(config->save_connector_encoders);
9122 kfree(config->save_encoder_crtcs);
d9e55608
DV		 9123 kfree(config);
9124}
9125
85f9eb71
DV		 9126static int intel_set_config_save_state(struct drm_device *dev,
9127 struct intel_set_config *config)
9128{
85f9eb71
DV		 9129 struct drm_encoder *encoder;
9130 struct drm_connector *connector;
9131 int count;
9132
1aa4b628
DV		 9133 config->save_encoder_crtcs =
9134 kcalloc(dev->mode_config.num_encoder,
9135 sizeof(struct drm_crtc *), GFP_KERNEL);
9136 if (!config->save_encoder_crtcs)
85f9eb71
DV		 9137 return -ENOMEM;
9138
1aa4b628
DV		 9139 config->save_connector_encoders =
9140 kcalloc(dev->mode_config.num_connector,
9141 sizeof(struct drm_encoder *), GFP_KERNEL);
9142 if (!config->save_connector_encoders)
85f9eb71
DV		 9143 return -ENOMEM;
9144
9145 /* Copy data. Note that driver private data is not affected.
9146 * Should anything bad happen only the expected state is
9147 * restored, not the drivers personal bookkeeping.
9148 */
85f9eb71
DV		 9149 count = 0;
9150 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 9151 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 9152 }
9153
9154 count = 0;
9155 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 9156 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 9157 }
9158
9159 return 0;
9160}
9161
9162static void intel_set_config_restore_state(struct drm_device *dev,
9163 struct intel_set_config *config)
9164{
9a935856
DV		 9165 struct intel_encoder *encoder;
9166 struct intel_connector *connector;
85f9eb71
DV		 9167 int count;
9168
85f9eb71 9169 count = 0;
9a935856
DV		 9170 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9171 encoder->new_crtc =
9172 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 9173 }
9174
9175 count = 0;
9a935856
DV		 9176 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9177 connector->new_encoder =
9178 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 9179 }
9180}
9181
e3de42b6 9182static bool
2e57f47d 9183is_crtc_connector_off(struct drm_mode_set *set)
e3de42b6
ID		 9184{
9185 int i;
9186
2e57f47d
CW		 9187 if (set->num_connectors == 0)
9188 return false;
9189
9190 if (WARN_ON(set->connectors == NULL))
9191 return false;
9192
9193 for (i = 0; i < set->num_connectors; i++)
9194 if (set->connectors[i]->encoder &&
9195 set->connectors[i]->encoder->crtc == set->crtc &&
9196 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
e3de42b6
ID		 9197 return true;
9198
9199 return false;
9200}
9201
5e2b584e
DV		 9202static void
9203intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9204 struct intel_set_config *config)
9205{
9206
9207 /* We should be able to check here if the fb has the same properties
9208 * and then just flip_or_move it */
2e57f47d
CW		 9209 if (is_crtc_connector_off(set)) {
9210 config->mode_changed = true;
e3de42b6 9211 } else if (set->crtc->fb != set->fb) {
5e2b584e
DV		 9212 /* If we have no fb then treat it as a full mode set */
9213 if (set->crtc->fb == NULL) {
319d9827
JB		 9214 struct intel_crtc *intel_crtc =
9215 to_intel_crtc(set->crtc);
9216
9217 if (intel_crtc->active && i915_fastboot) {
9218 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9219 config->fb_changed = true;
9220 } else {
9221 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9222 config->mode_changed = true;
9223 }
5e2b584e
DV		 9224 } else if (set->fb == NULL) {
9225 config->mode_changed = true;
72f4901e
DV		 9226 } else if (set->fb->pixel_format !=
9227 set->crtc->fb->pixel_format) {
5e2b584e 9228 config->mode_changed = true;
e3de42b6 9229 } else {
5e2b584e 9230 config->fb_changed = true;
e3de42b6 9231 }
5e2b584e
DV		 9232 }
9233
835c5873 9234 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 9235 config->fb_changed = true;
9236
9237 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9238 DRM_DEBUG_KMS("modes are different, full mode set\n");
9239 drm_mode_debug_printmodeline(&set->crtc->mode);
9240 drm_mode_debug_printmodeline(set->mode);
9241 config->mode_changed = true;
9242 }
a1d95703
CW		 9243
9244 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9245 set->crtc->base.id, config->mode_changed, config->fb_changed);
5e2b584e
DV		 9246}
9247
2e431051 9248static int
9a935856
DV		 9249intel_modeset_stage_output_state(struct drm_device *dev,
9250 struct drm_mode_set *set,
9251 struct intel_set_config *config)
50f56119 9252{
85f9eb71 9253 struct drm_crtc *new_crtc;
9a935856
DV		 9254 struct intel_connector *connector;
9255 struct intel_encoder *encoder;
f3f08572 9256 int ro;
50f56119 9257
9abdda74 9258 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 9259 * of connectors. For paranoia, double-check this. */
9260 WARN_ON(!set->fb && (set->num_connectors != 0));
9261 WARN_ON(set->fb && (set->num_connectors == 0));
9262
9a935856
DV		 9263 list_for_each_entry(connector, &dev->mode_config.connector_list,
9264 base.head) {
9265 /* Otherwise traverse passed in connector list and get encoders
9266 * for them. */
50f56119 9267 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 9268 if (set->connectors[ro] == &connector->base) {
9269 connector->new_encoder = connector->encoder;
50f56119
DV		 9270 break;
9271 }
9272 }
9273
9a935856
DV		 9274 /* If we disable the crtc, disable all its connectors. Also, if
9275 * the connector is on the changing crtc but not on the new
9276 * connector list, disable it. */
9277 if ((!set->fb || ro == set->num_connectors) &&
9278 connector->base.encoder &&
9279 connector->base.encoder->crtc == set->crtc) {
9280 connector->new_encoder = NULL;
9281
9282 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9283 connector->base.base.id,
9284 drm_get_connector_name(&connector->base));
9285 }
9286
9287
9288 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 9289 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 9290 config->mode_changed = true;
50f56119
DV		 9291 }
9292 }
9a935856 9293 /* connector->new_encoder is now updated for all connectors. */
50f56119 9294
9a935856 9295 /* Update crtc of enabled connectors. */
9a935856
DV		 9296 list_for_each_entry(connector, &dev->mode_config.connector_list,
9297 base.head) {
9298 if (!connector->new_encoder)
50f56119
DV		 9299 continue;
9300
9a935856 9301 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 9302
9303 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 9304 if (set->connectors[ro] == &connector->base)
50f56119
DV		 9305 new_crtc = set->crtc;
9306 }
9307
9308 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 9309 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9310 new_crtc)) {
5e2b584e 9311 return -EINVAL;
50f56119 9312 }
9a935856
DV		 9313 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9314
9315 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9316 connector->base.base.id,
9317 drm_get_connector_name(&connector->base),
9318 new_crtc->base.id);
9319 }
9320
9321 /* Check for any encoders that needs to be disabled. */
9322 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9323 base.head) {
9324 list_for_each_entry(connector,
9325 &dev->mode_config.connector_list,
9326 base.head) {
9327 if (connector->new_encoder == encoder) {
9328 WARN_ON(!connector->new_encoder->new_crtc);
9329
9330 goto next_encoder;
9331 }
9332 }
9333 encoder->new_crtc = NULL;
9334next_encoder:
9335 /* Only now check for crtc changes so we don't miss encoders
9336 * that will be disabled. */
9337 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 9338 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 9339 config->mode_changed = true;
50f56119
DV		 9340 }
9341 }
9a935856 9342 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 9343
2e431051
DV		 9344 return 0;
9345}
9346
9347static int intel_crtc_set_config(struct drm_mode_set *set)
9348{
9349 struct drm_device *dev;
2e431051
DV		 9350 struct drm_mode_set save_set;
9351 struct intel_set_config *config;
9352 int ret;
2e431051 9353
8d3e375e
DV		 9354 BUG_ON(!set);
9355 BUG_ON(!set->crtc);
9356 BUG_ON(!set->crtc->helper_private);
2e431051 9357
7e53f3a4
DV		 9358 /* Enforce sane interface api - has been abused by the fb helper. */
9359 BUG_ON(!set->mode && set->fb);
9360 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 9361
2e431051
DV		 9362 if (set->fb) {
9363 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9364 set->crtc->base.id, set->fb->base.id,
9365 (int)set->num_connectors, set->x, set->y);
9366 } else {
9367 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 9368 }
9369
9370 dev = set->crtc->dev;
9371
9372 ret = -ENOMEM;
9373 config = kzalloc(sizeof(*config), GFP_KERNEL);
9374 if (!config)
9375 goto out_config;
9376
9377 ret = intel_set_config_save_state(dev, config);
9378 if (ret)
9379 goto out_config;
9380
9381 save_set.crtc = set->crtc;
9382 save_set.mode = &set->crtc->mode;
9383 save_set.x = set->crtc->x;
9384 save_set.y = set->crtc->y;
9385 save_set.fb = set->crtc->fb;
9386
9387 /* Compute whether we need a full modeset, only an fb base update or no
9388 * change at all. In the future we might also check whether only the
9389 * mode changed, e.g. for LVDS where we only change the panel fitter in
9390 * such cases. */
9391 intel_set_config_compute_mode_changes(set, config);
9392
9a935856 9393 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 9394 if (ret)
9395 goto fail;
9396
5e2b584e 9397 if (config->mode_changed) {
c0c36b94
CW		 9398 ret = intel_set_mode(set->crtc, set->mode,
9399 set->x, set->y, set->fb);
5e2b584e 9400 } else if (config->fb_changed) {
4878cae2
VS		 9401 intel_crtc_wait_for_pending_flips(set->crtc);
9402
4f660f49 9403 ret = intel_pipe_set_base(set->crtc,
94352cf9 9404 set->x, set->y, set->fb);
50f56119
DV		 9405 }
9406
2d05eae1 9407 if (ret) {
bf67dfeb
DV		 9408 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9409 set->crtc->base.id, ret);
50f56119 9410fail:
2d05eae1 9411 intel_set_config_restore_state(dev, config);
50f56119 9412
2d05eae1
CW		 9413 /* Try to restore the config */
9414 if (config->mode_changed &&
9415 intel_set_mode(save_set.crtc, save_set.mode,
9416 save_set.x, save_set.y, save_set.fb))
9417 DRM_ERROR("failed to restore config after modeset failure\n");
9418 }
50f56119 9419
d9e55608
DV		 9420out_config:
9421 intel_set_config_free(config);
50f56119
DV		 9422 return ret;
9423}
f6e5b160
CW		 9424
9425static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 9426 .cursor_set = intel_crtc_cursor_set,
9427 .cursor_move = intel_crtc_cursor_move,
9428 .gamma_set = intel_crtc_gamma_set,
50f56119 9429 .set_config = intel_crtc_set_config,
f6e5b160
CW		 9430 .destroy = intel_crtc_destroy,
9431 .page_flip = intel_crtc_page_flip,
9432};
9433
79f689aa
PZ		 9434static void intel_cpu_pll_init(struct drm_device *dev)
9435{
affa9354 9436 if (HAS_DDI(dev))
79f689aa
PZ		 9437 intel_ddi_pll_init(dev);
9438}
9439
5358901f
DV		 9440static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9441 struct intel_shared_dpll *pll,
9442 struct intel_dpll_hw_state *hw_state)
ee7b9f93 9443{
5358901f 9444 uint32_t val;
ee7b9f93 9445
5358901f 9446 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 9447 hw_state->dpll = val;
9448 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9449 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 9450
9451 return val & DPLL_VCO_ENABLE;
9452}
9453
15bdd4cf
DV		 9454static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9455 struct intel_shared_dpll *pll)
9456{
9457 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9458 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9459}
9460
e7b903d2
DV		 9461static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9462 struct intel_shared_dpll *pll)
9463{
e7b903d2
DV		 9464 /* PCH refclock must be enabled first */
9465 assert_pch_refclk_enabled(dev_priv);
9466
15bdd4cf
DV		 9467 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9468
9469 /* Wait for the clocks to stabilize. */
9470 POSTING_READ(PCH_DPLL(pll->id));
9471 udelay(150);
9472
9473 /* The pixel multiplier can only be updated once the
9474 * DPLL is enabled and the clocks are stable.
9475 *
9476 * So write it again.
9477 */
9478 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9479 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9480 udelay(200);
9481}
9482
9483static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9484 struct intel_shared_dpll *pll)
9485{
9486 struct drm_device *dev = dev_priv->dev;
9487 struct intel_crtc *crtc;
e7b903d2
DV		 9488
9489 /* Make sure no transcoder isn't still depending on us. */
9490 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9491 if (intel_crtc_to_shared_dpll(crtc) == pll)
9492 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 9493 }
9494
15bdd4cf
DV		 9495 I915_WRITE(PCH_DPLL(pll->id), 0);
9496 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9497 udelay(200);
9498}
9499
46edb027
DV		 9500static char *ibx_pch_dpll_names[] = {
9501 "PCH DPLL A",
9502 "PCH DPLL B",
9503};
9504
7c74ade1 9505static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 9506{
e7b903d2 9507 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 9508 int i;
9509
7c74ade1 9510 dev_priv->num_shared_dpll = 2;
ee7b9f93 9511
e72f9fbf 9512 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 9513 dev_priv->shared_dplls[i].id = i;
9514 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 9515 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 9516 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9517 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 9518 dev_priv->shared_dplls[i].get_hw_state =
9519 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 9520 }
9521}
9522
7c74ade1
DV		 9523static void intel_shared_dpll_init(struct drm_device *dev)
9524{
e7b903d2 9525 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1
DV		 9526
9527 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9528 ibx_pch_dpll_init(dev);
9529 else
9530 dev_priv->num_shared_dpll = 0;
9531
9532 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9533 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9534 dev_priv->num_shared_dpll);
9535}
9536
b358d0a6 9537static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 9538{
22fd0fab 9539 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 9540 struct intel_crtc *intel_crtc;
9541 int i;
9542
9543 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
9544 if (intel_crtc == NULL)
9545 return;
9546
9547 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9548
9549 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 9550 for (i = 0; i < 256; i++) {
9551 intel_crtc->lut_r[i] = i;
9552 intel_crtc->lut_g[i] = i;
9553 intel_crtc->lut_b[i] = i;
9554 }
9555
80824003
JB		 9556 /* Swap pipes & planes for FBC on pre-965 */
9557 intel_crtc->pipe = pipe;
9558 intel_crtc->plane = pipe;
e2e767ab 9559 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 9560 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 9561 intel_crtc->plane = !pipe;
80824003
JB		 9562 }
9563
22fd0fab
JB		 9564 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9565 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9566 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9567 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9568
79e53945 9569 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 9570}
9571
08d7b3d1 9572int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 9573 struct drm_file *file)
08d7b3d1 9574{
08d7b3d1 9575 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 9576 struct drm_mode_object *drmmode_obj;
9577 struct intel_crtc *crtc;
08d7b3d1 9578
1cff8f6b
DV		 9579 if (!drm_core_check_feature(dev, DRIVER_MODESET))
9580 return -ENODEV;
08d7b3d1 9581
c05422d5
DV		 9582 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9583 DRM_MODE_OBJECT_CRTC);
08d7b3d1 9584
c05422d5 9585 if (!drmmode_obj) {
08d7b3d1
CW		 9586 DRM_ERROR("no such CRTC id\n");
9587 return -EINVAL;
9588 }
9589
c05422d5
DV		 9590 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9591 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 9592
c05422d5 9593 return 0;
08d7b3d1
CW		 9594}
9595
66a9278e 9596static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 9597{
66a9278e
DV		 9598 struct drm_device *dev = encoder->base.dev;
9599 struct intel_encoder *source_encoder;
79e53945 9600 int index_mask = 0;
79e53945
JB		 9601 int entry = 0;
9602
66a9278e
DV		 9603 list_for_each_entry(source_encoder,
9604 &dev->mode_config.encoder_list, base.head) {
9605
9606 if (encoder == source_encoder)
79e53945 9607 index_mask |= (1 << entry);
66a9278e
DV		 9608
9609 /* Intel hw has only one MUX where enocoders could be cloned. */
9610 if (encoder->cloneable && source_encoder->cloneable)
9611 index_mask |= (1 << entry);
9612
79e53945
JB		 9613 entry++;
9614 }
4ef69c7a 9615
79e53945
JB		 9616 return index_mask;
9617}
9618
4d302442
CW		 9619static bool has_edp_a(struct drm_device *dev)
9620{
9621 struct drm_i915_private *dev_priv = dev->dev_private;
9622
9623 if (!IS_MOBILE(dev))
9624 return false;
9625
9626 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9627 return false;
9628
9629 if (IS_GEN5(dev) &&
9630 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9631 return false;
9632
9633 return true;
9634}
9635
79e53945
JB		 9636static void intel_setup_outputs(struct drm_device *dev)
9637{
725e30ad 9638 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 9639 struct intel_encoder *encoder;
cb0953d7 9640 bool dpd_is_edp = false;
79e53945 9641
c9093354 9642 intel_lvds_init(dev);
79e53945 9643
c40c0f5b 9644 if (!IS_ULT(dev))
79935fca 9645 intel_crt_init(dev);
cb0953d7 9646
affa9354 9647 if (HAS_DDI(dev)) {
0e72a5b5
ED		 9648 int found;
9649
9650 /* Haswell uses DDI functions to detect digital outputs */
9651 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9652 /* DDI A only supports eDP */
9653 if (found)
9654 intel_ddi_init(dev, PORT_A);
9655
9656 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9657 * register */
9658 found = I915_READ(SFUSE_STRAP);
9659
9660 if (found & SFUSE_STRAP_DDIB_DETECTED)
9661 intel_ddi_init(dev, PORT_B);
9662 if (found & SFUSE_STRAP_DDIC_DETECTED)
9663 intel_ddi_init(dev, PORT_C);
9664 if (found & SFUSE_STRAP_DDID_DETECTED)
9665 intel_ddi_init(dev, PORT_D);
9666 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 9667 int found;
270b3042
DV		 9668 dpd_is_edp = intel_dpd_is_edp(dev);
9669
9670 if (has_edp_a(dev))
9671 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 9672
dc0fa718 9673 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 9674 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 9675 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 9676 if (!found)
e2debe91 9677 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 9678 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 9679 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 9680 }
9681
dc0fa718 9682 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 9683 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 9684
dc0fa718 9685 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 9686 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 9687
5eb08b69 9688 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 9689 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 9690
270b3042 9691 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 9692 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 9693 } else if (IS_VALLEYVIEW(dev)) {
19c03924 9694 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
6f6005a5
JB		 9695 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
9696 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
9697 PORT_C);
9698 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9699 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
9700 PORT_C);
9701 }
19c03924 9702
dc0fa718 9703 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 9704 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9705 PORT_B);
67cfc203
VS		 9706 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9707 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 9708 }
3cfca973
JN		 9709
9710 intel_dsi_init(dev);
103a196f 9711 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 9712 bool found = false;
7d57382e 9713
e2debe91 9714 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9715 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 9716 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 9717 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9718 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 9719 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 9720 }
27185ae1 9721
e7281eab 9722 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9723 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 9724 }
13520b05
KH		 9725
9726 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 9727
e2debe91 9728 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9729 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 9730 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 9731 }
27185ae1 9732
e2debe91 9733 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 9734
b01f2c3a
JB		 9735 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9736 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 9737 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 9738 }
e7281eab 9739 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9740 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 9741 }
27185ae1 9742
b01f2c3a 9743 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 9744 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 9745 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 9746 } else if (IS_GEN2(dev))
79e53945
JB		 9747 intel_dvo_init(dev);
9748
103a196f 9749 if (SUPPORTS_TV(dev))
79e53945
JB		 9750 intel_tv_init(dev);
9751
4ef69c7a
CW		 9752 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9753 encoder->base.possible_crtcs = encoder->crtc_mask;
9754 encoder->base.possible_clones =
66a9278e 9755 intel_encoder_clones(encoder);
79e53945 9756 }
47356eb6 9757
dde86e2d 9758 intel_init_pch_refclk(dev);
270b3042
DV		 9759
9760 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 9761}
9762
ddfe1567
CW		 9763void intel_framebuffer_fini(struct intel_framebuffer *fb)
9764{
9765 drm_framebuffer_cleanup(&fb->base);
9766 drm_gem_object_unreference_unlocked(&fb->obj->base);
9767}
9768
79e53945
JB		 9769static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9770{
9771 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 9772
ddfe1567 9773 intel_framebuffer_fini(intel_fb);
79e53945
JB		 9774 kfree(intel_fb);
9775}
9776
9777static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 9778 struct drm_file *file,
79e53945
JB		 9779 unsigned int *handle)
9780{
9781 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 9782 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 9783
05394f39 9784 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 9785}
9786
9787static const struct drm_framebuffer_funcs intel_fb_funcs = {
9788 .destroy = intel_user_framebuffer_destroy,
9789 .create_handle = intel_user_framebuffer_create_handle,
9790};
9791
38651674
DA		 9792int intel_framebuffer_init(struct drm_device *dev,
9793 struct intel_framebuffer *intel_fb,
308e5bcb 9794 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 9795 struct drm_i915_gem_object *obj)
79e53945 9796{
a35cdaa0 9797 int pitch_limit;
79e53945
JB		 9798 int ret;
9799
c16ed4be
CW		 9800 if (obj->tiling_mode == I915_TILING_Y) {
9801 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 9802 return -EINVAL;
c16ed4be 9803 }
57cd6508 9804
c16ed4be
CW		 9805 if (mode_cmd->pitches[0] & 63) {
9806 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9807 mode_cmd->pitches[0]);
57cd6508 9808 return -EINVAL;
c16ed4be 9809 }
57cd6508 9810
a35cdaa0
CW		 9811 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9812 pitch_limit = 32*1024;
9813 } else if (INTEL_INFO(dev)->gen >= 4) {
9814 if (obj->tiling_mode)
9815 pitch_limit = 16*1024;
9816 else
9817 pitch_limit = 32*1024;
9818 } else if (INTEL_INFO(dev)->gen >= 3) {
9819 if (obj->tiling_mode)
9820 pitch_limit = 8*1024;
9821 else
9822 pitch_limit = 16*1024;
9823 } else
9824 /* XXX DSPC is limited to 4k tiled */
9825 pitch_limit = 8*1024;
9826
9827 if (mode_cmd->pitches[0] > pitch_limit) {
9828 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9829 obj->tiling_mode ? "tiled" : "linear",
9830 mode_cmd->pitches[0], pitch_limit);
5d7bd705 9831 return -EINVAL;
c16ed4be 9832 }
5d7bd705
VS		 9833
9834 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 9835 mode_cmd->pitches[0] != obj->stride) {
9836 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9837 mode_cmd->pitches[0], obj->stride);
5d7bd705 9838 return -EINVAL;
c16ed4be 9839 }
5d7bd705 9840
57779d06 9841 /* Reject formats not supported by any plane early. */
308e5bcb 9842 switch (mode_cmd->pixel_format) {
57779d06 9843 case DRM_FORMAT_C8:
04b3924d
VS		 9844 case DRM_FORMAT_RGB565:
9845 case DRM_FORMAT_XRGB8888:
9846 case DRM_FORMAT_ARGB8888:
57779d06
VS		 9847 break;
9848 case DRM_FORMAT_XRGB1555:
9849 case DRM_FORMAT_ARGB1555:
c16ed4be 9850 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 9851 DRM_DEBUG("unsupported pixel format: %s\n",
9852 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9853 return -EINVAL;
c16ed4be 9854 }
57779d06
VS		 9855 break;
9856 case DRM_FORMAT_XBGR8888:
9857 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 9858 case DRM_FORMAT_XRGB2101010:
9859 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 9860 case DRM_FORMAT_XBGR2101010:
9861 case DRM_FORMAT_ABGR2101010:
c16ed4be 9862 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 9863 DRM_DEBUG("unsupported pixel format: %s\n",
9864 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9865 return -EINVAL;
c16ed4be 9866 }
b5626747 9867 break;
04b3924d
VS		 9868 case DRM_FORMAT_YUYV:
9869 case DRM_FORMAT_UYVY:
9870 case DRM_FORMAT_YVYU:
9871 case DRM_FORMAT_VYUY:
c16ed4be 9872 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 9873 DRM_DEBUG("unsupported pixel format: %s\n",
9874 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9875 return -EINVAL;
c16ed4be 9876 }
57cd6508
CW		 9877 break;
9878 default:
4ee62c76
VS		 9879 DRM_DEBUG("unsupported pixel format: %s\n",
9880 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 9881 return -EINVAL;
9882 }
9883
90f9a336
VS		 9884 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9885 if (mode_cmd->offsets[0] != 0)
9886 return -EINVAL;
9887
c7d73f6a
DV		 9888 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9889 intel_fb->obj = obj;
9890
79e53945
JB		 9891 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9892 if (ret) {
9893 DRM_ERROR("framebuffer init failed %d\n", ret);
9894 return ret;
9895 }
9896
79e53945
JB		 9897 return 0;
9898}
9899
79e53945
JB		 9900static struct drm_framebuffer *
9901intel_user_framebuffer_create(struct drm_device *dev,
9902 struct drm_file *filp,
308e5bcb 9903 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 9904{
05394f39 9905 struct drm_i915_gem_object *obj;
79e53945 9906
308e5bcb
JB		 9907 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9908 mode_cmd->handles[0]));
c8725226 9909 if (&obj->base == NULL)
cce13ff7 9910 return ERR_PTR(-ENOENT);
79e53945 9911
d2dff872 9912 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 9913}
9914
79e53945 9915static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 9916 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 9917 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 9918};
9919
e70236a8
JB		 9920/* Set up chip specific display functions */
9921static void intel_init_display(struct drm_device *dev)
9922{
9923 struct drm_i915_private *dev_priv = dev->dev_private;
9924
ee9300bb
DV		 9925 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9926 dev_priv->display.find_dpll = g4x_find_best_dpll;
9927 else if (IS_VALLEYVIEW(dev))
9928 dev_priv->display.find_dpll = vlv_find_best_dpll;
9929 else if (IS_PINEVIEW(dev))
9930 dev_priv->display.find_dpll = pnv_find_best_dpll;
9931 else
9932 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9933
affa9354 9934 if (HAS_DDI(dev)) {
0e8ffe1b 9935 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 9936 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 9937 dev_priv->display.crtc_enable = haswell_crtc_enable;
9938 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 9939 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 9940 dev_priv->display.update_plane = ironlake_update_plane;
9941 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 9942 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 9943 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 9944 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9945 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 9946 dev_priv->display.off = ironlake_crtc_off;
17638cd6 9947 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 9948 } else if (IS_VALLEYVIEW(dev)) {
9949 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9950 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9951 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9952 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9953 dev_priv->display.off = i9xx_crtc_off;
9954 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9955 } else {
0e8ffe1b 9956 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 9957 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 9958 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9959 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 9960 dev_priv->display.off = i9xx_crtc_off;
17638cd6 9961 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9962 }
e70236a8 9963
e70236a8 9964 /* Returns the core display clock speed */
25eb05fc
JB		 9965 if (IS_VALLEYVIEW(dev))
9966 dev_priv->display.get_display_clock_speed =
9967 valleyview_get_display_clock_speed;
9968 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 9969 dev_priv->display.get_display_clock_speed =
9970 i945_get_display_clock_speed;
9971 else if (IS_I915G(dev))
9972 dev_priv->display.get_display_clock_speed =
9973 i915_get_display_clock_speed;
257a7ffc 9974 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 9975 dev_priv->display.get_display_clock_speed =
9976 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 9977 else if (IS_PINEVIEW(dev))
9978 dev_priv->display.get_display_clock_speed =
9979 pnv_get_display_clock_speed;
e70236a8
JB		 9980 else if (IS_I915GM(dev))
9981 dev_priv->display.get_display_clock_speed =
9982 i915gm_get_display_clock_speed;
9983 else if (IS_I865G(dev))
9984 dev_priv->display.get_display_clock_speed =
9985 i865_get_display_clock_speed;
f0f8a9ce 9986 else if (IS_I85X(dev))
e70236a8
JB		 9987 dev_priv->display.get_display_clock_speed =
9988 i855_get_display_clock_speed;
9989 else /* 852, 830 */
9990 dev_priv->display.get_display_clock_speed =
9991 i830_get_display_clock_speed;
9992
7f8a8569 9993 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 9994 if (IS_GEN5(dev)) {
674cf967 9995 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 9996 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 9997 } else if (IS_GEN6(dev)) {
674cf967 9998 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 9999 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 10000 } else if (IS_IVYBRIDGE(dev)) {
10001 /* FIXME: detect B0+ stepping and use auto training */
10002 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 10003 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 10004 dev_priv->display.modeset_global_resources =
10005 ivb_modeset_global_resources;
c82e4d26
ED		 10006 } else if (IS_HASWELL(dev)) {
10007 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 10008 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 10009 dev_priv->display.modeset_global_resources =
10010 haswell_modeset_global_resources;
a0e63c22 10011 }
6067aaea 10012 } else if (IS_G4X(dev)) {
e0dac65e 10013 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 10014 }
8c9f3aaf
JB		 10015
10016 /* Default just returns -ENODEV to indicate unsupported */
10017 dev_priv->display.queue_flip = intel_default_queue_flip;
10018
10019 switch (INTEL_INFO(dev)->gen) {
10020 case 2:
10021 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10022 break;
10023
10024 case 3:
10025 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10026 break;
10027
10028 case 4:
10029 case 5:
10030 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10031 break;
10032
10033 case 6:
10034 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10035 break;
7c9017e5
JB		 10036 case 7:
10037 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10038 break;
8c9f3aaf 10039 }
e70236a8
JB		 10040}
10041
b690e96c
JB		 10042/*
10043 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10044 * resume, or other times. This quirk makes sure that's the case for
10045 * affected systems.
10046 */
0206e353 10047static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 10048{
10049 struct drm_i915_private *dev_priv = dev->dev_private;
10050
10051 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 10052 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 10053}
10054
435793df
KP		 10055/*
10056 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10057 */
10058static void quirk_ssc_force_disable(struct drm_device *dev)
10059{
10060 struct drm_i915_private *dev_priv = dev->dev_private;
10061 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 10062 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 10063}
10064
4dca20ef 10065/*
5a15ab5b
CE		 10066 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10067 * brightness value
4dca20ef
CE		 10068 */
10069static void quirk_invert_brightness(struct drm_device *dev)
10070{
10071 struct drm_i915_private *dev_priv = dev->dev_private;
10072 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 10073 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 10074}
10075
e85843be
KM		 10076/*
10077 * Some machines (Dell XPS13) suffer broken backlight controls if
10078 * BLM_PCH_PWM_ENABLE is set.
10079 */
10080static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
10081{
10082 struct drm_i915_private *dev_priv = dev->dev_private;
10083 dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
10084 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
10085}
10086
b690e96c
JB		 10087struct intel_quirk {
10088 int device;
10089 int subsystem_vendor;
10090 int subsystem_device;
10091 void (*hook)(struct drm_device *dev);
10092};
10093
5f85f176
EE		 10094/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10095struct intel_dmi_quirk {
10096 void (*hook)(struct drm_device *dev);
10097 const struct dmi_system_id (*dmi_id_list)[];
10098};
10099
10100static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10101{
10102 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10103 return 1;
10104}
10105
10106static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10107 {
10108 .dmi_id_list = &(const struct dmi_system_id[]) {
10109 {
10110 .callback = intel_dmi_reverse_brightness,
10111 .ident = "NCR Corporation",
10112 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10113 DMI_MATCH(DMI_PRODUCT_NAME, ""),
10114 },
10115 },
10116 { } /* terminating entry */
10117 },
10118 .hook = quirk_invert_brightness,
10119 },
10120};
10121
c43b5634 10122static struct intel_quirk intel_quirks[] = {
b690e96c 10123 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 10124 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 10125
b690e96c
JB		 10126 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10127 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10128
b690e96c
JB		 10129 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10130 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10131
ccd0d36e 10132 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 10133 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 10134 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 10135
10136 /* Lenovo U160 cannot use SSC on LVDS */
10137 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 10138
10139 /* Sony Vaio Y cannot use SSC on LVDS */
10140 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 10141
10142 /* Acer Aspire 5734Z must invert backlight brightness */
10143 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 10144
10145 /* Acer/eMachines G725 */
10146 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 10147
10148 /* Acer/eMachines e725 */
10149 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 10150
10151 /* Acer/Packard Bell NCL20 */
10152 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 10153
10154 /* Acer Aspire 4736Z */
10155 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
e85843be
KM		 10156
10157 /* Dell XPS13 HD Sandy Bridge */
10158 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10159 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10160 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
b690e96c
JB		 10161};
10162
10163static void intel_init_quirks(struct drm_device *dev)
10164{
10165 struct pci_dev *d = dev->pdev;
10166 int i;
10167
10168 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10169 struct intel_quirk *q = &intel_quirks[i];
10170
10171 if (d->device == q->device &&
10172 (d->subsystem_vendor == q->subsystem_vendor ||
10173 q->subsystem_vendor == PCI_ANY_ID) &&
10174 (d->subsystem_device == q->subsystem_device ||
10175 q->subsystem_device == PCI_ANY_ID))
10176 q->hook(dev);
10177 }
5f85f176
EE		 10178 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10179 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10180 intel_dmi_quirks[i].hook(dev);
10181 }
b690e96c
JB		 10182}
10183
9cce37f4
JB		 10184/* Disable the VGA plane that we never use */
10185static void i915_disable_vga(struct drm_device *dev)
10186{
10187 struct drm_i915_private *dev_priv = dev->dev_private;
10188 u8 sr1;
766aa1c4 10189 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 10190
10191 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 10192 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 10193 sr1 = inb(VGA_SR_DATA);
10194 outb(sr1 | 1<<5, VGA_SR_DATA);
81b5c7bc
AW		 10195
10196 /* Disable VGA memory on Intel HD */
10197 if (HAS_PCH_SPLIT(dev)) {
10198 outb(inb(VGA_MSR_READ) & ~VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10199 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10200 VGA_RSRC_NORMAL_IO |
10201 VGA_RSRC_NORMAL_MEM);
10202 }
10203
9cce37f4
JB		 10204 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10205 udelay(300);
10206
10207 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10208 POSTING_READ(vga_reg);
10209}
10210
81b5c7bc
AW		 10211static void i915_enable_vga(struct drm_device *dev)
10212{
10213 /* Enable VGA memory on Intel HD */
10214 if (HAS_PCH_SPLIT(dev)) {
10215 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10216 outb(inb(VGA_MSR_READ) | VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10217 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10218 VGA_RSRC_LEGACY_MEM |
10219 VGA_RSRC_NORMAL_IO |
10220 VGA_RSRC_NORMAL_MEM);
10221 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10222 }
10223}
10224
f817586c
DV		 10225void intel_modeset_init_hw(struct drm_device *dev)
10226{
fa42e23c 10227 intel_init_power_well(dev);
0232e927 10228
a8f78b58
ED		 10229 intel_prepare_ddi(dev);
10230
f817586c
DV		 10231 intel_init_clock_gating(dev);
10232
79f5b2c7 10233 mutex_lock(&dev->struct_mutex);
8090c6b9 10234 intel_enable_gt_powersave(dev);
79f5b2c7 10235 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 10236}
10237
7d708ee4
ID		 10238void intel_modeset_suspend_hw(struct drm_device *dev)
10239{
10240 intel_suspend_hw(dev);
10241}
10242
79e53945
JB		 10243void intel_modeset_init(struct drm_device *dev)
10244{
652c393a 10245 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 10246 int i, j, ret;
79e53945
JB		 10247
10248 drm_mode_config_init(dev);
10249
10250 dev->mode_config.min_width = 0;
10251 dev->mode_config.min_height = 0;
10252
019d96cb
DA		 10253 dev->mode_config.preferred_depth = 24;
10254 dev->mode_config.prefer_shadow = 1;
10255
e6ecefaa 10256 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 10257
b690e96c
JB		 10258 intel_init_quirks(dev);
10259
1fa61106
ED		 10260 intel_init_pm(dev);
10261
e3c74757
BW		 10262 if (INTEL_INFO(dev)->num_pipes == 0)
10263 return;
10264
e70236a8
JB		 10265 intel_init_display(dev);
10266
a6c45cf0
CW		 10267 if (IS_GEN2(dev)) {
10268 dev->mode_config.max_width = 2048;
10269 dev->mode_config.max_height = 2048;
10270 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 10271 dev->mode_config.max_width = 4096;
10272 dev->mode_config.max_height = 4096;
79e53945 10273 } else {
a6c45cf0
CW		 10274 dev->mode_config.max_width = 8192;
10275 dev->mode_config.max_height = 8192;
79e53945 10276 }
5d4545ae 10277 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 10278
28c97730 10279 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 10280 INTEL_INFO(dev)->num_pipes,
10281 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 10282
08e2a7de 10283 for_each_pipe(i) {
79e53945 10284 intel_crtc_init(dev, i);
7f1f3851
JB		 10285 for (j = 0; j < dev_priv->num_plane; j++) {
10286 ret = intel_plane_init(dev, i, j);
10287 if (ret)
06da8da2
VS		 10288 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10289 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 10290 }
79e53945
JB		 10291 }
10292
79f689aa 10293 intel_cpu_pll_init(dev);
e72f9fbf 10294 intel_shared_dpll_init(dev);
ee7b9f93 10295
9cce37f4
JB		 10296 /* Just disable it once at startup */
10297 i915_disable_vga(dev);
79e53945 10298 intel_setup_outputs(dev);
11be49eb
CW		 10299
10300 /* Just in case the BIOS is doing something questionable. */
10301 intel_disable_fbc(dev);
2c7111db
CW		 10302}
10303
24929352
DV		 10304static void
10305intel_connector_break_all_links(struct intel_connector *connector)
10306{
10307 connector->base.dpms = DRM_MODE_DPMS_OFF;
10308 connector->base.encoder = NULL;
10309 connector->encoder->connectors_active = false;
10310 connector->encoder->base.crtc = NULL;
10311}
10312
7fad798e
DV		 10313static void intel_enable_pipe_a(struct drm_device *dev)
10314{
10315 struct intel_connector *connector;
10316 struct drm_connector *crt = NULL;
10317 struct intel_load_detect_pipe load_detect_temp;
10318
10319 /* We can't just switch on the pipe A, we need to set things up with a
10320 * proper mode and output configuration. As a gross hack, enable pipe A
10321 * by enabling the load detect pipe once. */
10322 list_for_each_entry(connector,
10323 &dev->mode_config.connector_list,
10324 base.head) {
10325 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10326 crt = &connector->base;
10327 break;
10328 }
10329 }
10330
10331 if (!crt)
10332 return;
10333
10334 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10335 intel_release_load_detect_pipe(crt, &load_detect_temp);
10336
652c393a 10337
7fad798e
DV		 10338}
10339
fa555837
DV		 10340static bool
10341intel_check_plane_mapping(struct intel_crtc *crtc)
10342{
7eb552ae
BW		 10343 struct drm_device *dev = crtc->base.dev;
10344 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 10345 u32 reg, val;
10346
7eb552ae 10347 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 10348 return true;
10349
10350 reg = DSPCNTR(!crtc->plane);
10351 val = I915_READ(reg);
10352
10353 if ((val & DISPLAY_PLANE_ENABLE) &&
10354 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10355 return false;
10356
10357 return true;
10358}
10359
24929352
DV		 10360static void intel_sanitize_crtc(struct intel_crtc *crtc)
10361{
10362 struct drm_device *dev = crtc->base.dev;
10363 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 10364 u32 reg;
24929352 10365
24929352 10366 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 10367 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 10368 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10369
10370 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 10371 * disable the crtc (and hence change the state) if it is wrong. Note
10372 * that gen4+ has a fixed plane -> pipe mapping. */
10373 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 10374 struct intel_connector *connector;
10375 bool plane;
10376
24929352
DV		 10377 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10378 crtc->base.base.id);
10379
10380 /* Pipe has the wrong plane attached and the plane is active.
10381 * Temporarily change the plane mapping and disable everything
10382 * ... */
10383 plane = crtc->plane;
10384 crtc->plane = !plane;
10385 dev_priv->display.crtc_disable(&crtc->base);
10386 crtc->plane = plane;
10387
10388 /* ... and break all links. */
10389 list_for_each_entry(connector, &dev->mode_config.connector_list,
10390 base.head) {
10391 if (connector->encoder->base.crtc != &crtc->base)
10392 continue;
10393
10394 intel_connector_break_all_links(connector);
10395 }
10396
10397 WARN_ON(crtc->active);
10398 crtc->base.enabled = false;
10399 }
24929352 10400
7fad798e
DV		 10401 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10402 crtc->pipe == PIPE_A && !crtc->active) {
10403 /* BIOS forgot to enable pipe A, this mostly happens after
10404 * resume. Force-enable the pipe to fix this, the update_dpms
10405 * call below we restore the pipe to the right state, but leave
10406 * the required bits on. */
10407 intel_enable_pipe_a(dev);
10408 }
10409
24929352
DV		 10410 /* Adjust the state of the output pipe according to whether we
10411 * have active connectors/encoders. */
10412 intel_crtc_update_dpms(&crtc->base);
10413
10414 if (crtc->active != crtc->base.enabled) {
10415 struct intel_encoder *encoder;
10416
10417 /* This can happen either due to bugs in the get_hw_state
10418 * functions or because the pipe is force-enabled due to the
10419 * pipe A quirk. */
10420 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10421 crtc->base.base.id,
10422 crtc->base.enabled ? "enabled" : "disabled",
10423 crtc->active ? "enabled" : "disabled");
10424
10425 crtc->base.enabled = crtc->active;
10426
10427 /* Because we only establish the connector -> encoder ->
10428 * crtc links if something is active, this means the
10429 * crtc is now deactivated. Break the links. connector
10430 * -> encoder links are only establish when things are
10431 * actually up, hence no need to break them. */
10432 WARN_ON(crtc->active);
10433
10434 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10435 WARN_ON(encoder->connectors_active);
10436 encoder->base.crtc = NULL;
10437 }
10438 }
10439}
10440
10441static void intel_sanitize_encoder(struct intel_encoder *encoder)
10442{
10443 struct intel_connector *connector;
10444 struct drm_device *dev = encoder->base.dev;
10445
10446 /* We need to check both for a crtc link (meaning that the
10447 * encoder is active and trying to read from a pipe) and the
10448 * pipe itself being active. */
10449 bool has_active_crtc = encoder->base.crtc &&
10450 to_intel_crtc(encoder->base.crtc)->active;
10451
10452 if (encoder->connectors_active && !has_active_crtc) {
10453 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10454 encoder->base.base.id,
10455 drm_get_encoder_name(&encoder->base));
10456
10457 /* Connector is active, but has no active pipe. This is
10458 * fallout from our resume register restoring. Disable
10459 * the encoder manually again. */
10460 if (encoder->base.crtc) {
10461 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10462 encoder->base.base.id,
10463 drm_get_encoder_name(&encoder->base));
10464 encoder->disable(encoder);
10465 }
10466
10467 /* Inconsistent output/port/pipe state happens presumably due to
10468 * a bug in one of the get_hw_state functions. Or someplace else
10469 * in our code, like the register restore mess on resume. Clamp
10470 * things to off as a safer default. */
10471 list_for_each_entry(connector,
10472 &dev->mode_config.connector_list,
10473 base.head) {
10474 if (connector->encoder != encoder)
10475 continue;
10476
10477 intel_connector_break_all_links(connector);
10478 }
10479 }
10480 /* Enabled encoders without active connectors will be fixed in
10481 * the crtc fixup. */
10482}
10483
44cec740 10484void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 10485{
10486 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 10487 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 10488
8dc8a27c
PZ		 10489 /* This function can be called both from intel_modeset_setup_hw_state or
10490 * at a very early point in our resume sequence, where the power well
10491 * structures are not yet restored. Since this function is at a very
10492 * paranoid "someone might have enabled VGA while we were not looking"
10493 * level, just check if the power well is enabled instead of trying to
10494 * follow the "don't touch the power well if we don't need it" policy
10495 * the rest of the driver uses. */
10496 if (HAS_POWER_WELL(dev) &&
6aedd1f5 10497 (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
8dc8a27c
PZ		 10498 return;
10499
0fde901f
KM		 10500 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
10501 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 10502 i915_disable_vga(dev);
0fde901f
KM		 10503 }
10504}
10505
30e984df 10506static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 10507{
10508 struct drm_i915_private *dev_priv = dev->dev_private;
10509 enum pipe pipe;
24929352
DV		 10510 struct intel_crtc *crtc;
10511 struct intel_encoder *encoder;
10512 struct intel_connector *connector;
5358901f 10513 int i;
24929352 10514
0e8ffe1b
DV		 10515 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10516 base.head) {
88adfff1 10517 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 10518
0e8ffe1b
DV		 10519 crtc->active = dev_priv->display.get_pipe_config(crtc,
10520 &crtc->config);
24929352
DV		 10521
10522 crtc->base.enabled = crtc->active;
10523
10524 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10525 crtc->base.base.id,
10526 crtc->active ? "enabled" : "disabled");
10527 }
10528
5358901f 10529 /* FIXME: Smash this into the new shared dpll infrastructure. */
affa9354 10530 if (HAS_DDI(dev))
6441ab5f
PZ		 10531 intel_ddi_setup_hw_pll_state(dev);
10532
5358901f
DV		 10533 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10534 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10535
10536 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10537 pll->active = 0;
10538 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10539 base.head) {
10540 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10541 pll->active++;
10542 }
10543 pll->refcount = pll->active;
10544
35c95375
DV		 10545 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10546 pll->name, pll->refcount, pll->on);
5358901f
DV		 10547 }
10548
24929352
DV		 10549 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10550 base.head) {
10551 pipe = 0;
10552
10553 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 10554 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10555 encoder->base.crtc = &crtc->base;
510d5f2f 10556 if (encoder->get_config)
045ac3b5 10557 encoder->get_config(encoder, &crtc->config);
24929352
DV		 10558 } else {
10559 encoder->base.crtc = NULL;
10560 }
10561
10562 encoder->connectors_active = false;
10563 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10564 encoder->base.base.id,
10565 drm_get_encoder_name(&encoder->base),
10566 encoder->base.crtc ? "enabled" : "disabled",
10567 pipe);
10568 }
10569
10570 list_for_each_entry(connector, &dev->mode_config.connector_list,
10571 base.head) {
10572 if (connector->get_hw_state(connector)) {
10573 connector->base.dpms = DRM_MODE_DPMS_ON;
10574 connector->encoder->connectors_active = true;
10575 connector->base.encoder = &connector->encoder->base;
10576 } else {
10577 connector->base.dpms = DRM_MODE_DPMS_OFF;
10578 connector->base.encoder = NULL;
10579 }
10580 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10581 connector->base.base.id,
10582 drm_get_connector_name(&connector->base),
10583 connector->base.encoder ? "enabled" : "disabled");
10584 }
30e984df
DV		 10585}
10586
10587/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10588 * and i915 state tracking structures. */
10589void intel_modeset_setup_hw_state(struct drm_device *dev,
10590 bool force_restore)
10591{
10592 struct drm_i915_private *dev_priv = dev->dev_private;
10593 enum pipe pipe;
10594 struct drm_plane *plane;
10595 struct intel_crtc *crtc;
10596 struct intel_encoder *encoder;
35c95375 10597 int i;
30e984df
DV		 10598
10599 intel_modeset_readout_hw_state(dev);
24929352 10600
babea61d
JB		 10601 /*
10602 * Now that we have the config, copy it to each CRTC struct
10603 * Note that this could go away if we move to using crtc_config
10604 * checking everywhere.
10605 */
10606 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10607 base.head) {
10608 if (crtc->active && i915_fastboot) {
10609 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10610
10611 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10612 crtc->base.base.id);
10613 drm_mode_debug_printmodeline(&crtc->base.mode);
10614 }
10615 }
10616
24929352
DV		 10617 /* HW state is read out, now we need to sanitize this mess. */
10618 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10619 base.head) {
10620 intel_sanitize_encoder(encoder);
10621 }
10622
10623 for_each_pipe(pipe) {
10624 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10625 intel_sanitize_crtc(crtc);
c0b03411 10626 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 10627 }
9a935856 10628
35c95375
DV		 10629 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10630 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10631
10632 if (!pll->on || pll->active)
10633 continue;
10634
10635 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10636
10637 pll->disable(dev_priv, pll);
10638 pll->on = false;
10639 }
10640
45e2b5f6 10641 if (force_restore) {
f30da187
DV		 10642 /*
10643 * We need to use raw interfaces for restoring state to avoid
10644 * checking (bogus) intermediate states.
10645 */
45e2b5f6 10646 for_each_pipe(pipe) {
b5644d05
JB		 10647 struct drm_crtc *crtc =
10648 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 10649
10650 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10651 crtc->fb);
45e2b5f6 10652 }
b5644d05
JB		 10653 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
10654 intel_plane_restore(plane);
0fde901f
KM		 10655
10656 i915_redisable_vga(dev);
45e2b5f6
DV		 10657 } else {
10658 intel_modeset_update_staged_output_state(dev);
10659 }
8af6cf88
DV		 10660
10661 intel_modeset_check_state(dev);
2e938892
DV		 10662
10663 drm_mode_config_reset(dev);
2c7111db
CW		 10664}
10665
10666void intel_modeset_gem_init(struct drm_device *dev)
10667{
1833b134 10668 intel_modeset_init_hw(dev);
02e792fb
DV		 10669
10670 intel_setup_overlay(dev);
24929352 10671
45e2b5f6 10672 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 10673}
10674
10675void intel_modeset_cleanup(struct drm_device *dev)
10676{
652c393a
JB		 10677 struct drm_i915_private *dev_priv = dev->dev_private;
10678 struct drm_crtc *crtc;
652c393a 10679
fd0c0642
DV		 10680 /*
10681 * Interrupts and polling as the first thing to avoid creating havoc.
10682 * Too much stuff here (turning of rps, connectors, ...) would
10683 * experience fancy races otherwise.
10684 */
10685 drm_irq_uninstall(dev);
10686 cancel_work_sync(&dev_priv->hotplug_work);
10687 /*
10688 * Due to the hpd irq storm handling the hotplug work can re-arm the
10689 * poll handlers. Hence disable polling after hpd handling is shut down.
10690 */
f87ea761 10691 drm_kms_helper_poll_fini(dev);
fd0c0642 10692
652c393a
JB		 10693 mutex_lock(&dev->struct_mutex);
10694
723bfd70
JB		 10695 intel_unregister_dsm_handler();
10696
652c393a
JB		 10697 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10698 /* Skip inactive CRTCs */
10699 if (!crtc->fb)
10700 continue;
10701
3dec0095 10702 intel_increase_pllclock(crtc);
652c393a
JB		 10703 }
10704
973d04f9 10705 intel_disable_fbc(dev);
e70236a8 10706
81b5c7bc
AW		 10707 i915_enable_vga(dev);
10708
8090c6b9 10709 intel_disable_gt_powersave(dev);
0cdab21f 10710
930ebb46
DV		 10711 ironlake_teardown_rc6(dev);
10712
69341a5e
KH		 10713 mutex_unlock(&dev->struct_mutex);
10714
1630fe75
CW		 10715 /* flush any delayed tasks or pending work */
10716 flush_scheduled_work();
10717
dc652f90
JN		 10718 /* destroy backlight, if any, before the connectors */
10719 intel_panel_destroy_backlight(dev);
10720
79e53945 10721 drm_mode_config_cleanup(dev);
4d7bb011
DV		 10722
10723 intel_cleanup_overlay(dev);
79e53945
JB		 10724}
10725
f1c79df3
ZW		 10726/*
10727 * Return which encoder is currently attached for connector.
10728 */
df0e9248 10729struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 10730{
df0e9248
CW		 10731 return &intel_attached_encoder(connector)->base;
10732}
f1c79df3 10733
df0e9248
CW		 10734void intel_connector_attach_encoder(struct intel_connector *connector,
10735 struct intel_encoder *encoder)
10736{
10737 connector->encoder = encoder;
10738 drm_mode_connector_attach_encoder(&connector->base,
10739 &encoder->base);
79e53945 10740}
28d52043
DA		 10741
10742/*
10743 * set vga decode state - true == enable VGA decode
10744 */
10745int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10746{
10747 struct drm_i915_private *dev_priv = dev->dev_private;
10748 u16 gmch_ctrl;
10749
10750 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10751 if (state)
10752 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10753 else
10754 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10755 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10756 return 0;
10757}
c4a1d9e4 10758
c4a1d9e4 10759struct intel_display_error_state {
ff57f1b0
PZ		 10760
10761 u32 power_well_driver;
10762
63b66e5b
CW		 10763 int num_transcoders;
10764
c4a1d9e4
CW		 10765 struct intel_cursor_error_state {
10766 u32 control;
10767 u32 position;
10768 u32 base;
10769 u32 size;
52331309 10770 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 10771
10772 struct intel_pipe_error_state {
c4a1d9e4 10773 u32 source;
52331309 10774 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 10775
10776 struct intel_plane_error_state {
10777 u32 control;
10778 u32 stride;
10779 u32 size;
10780 u32 pos;
10781 u32 addr;
10782 u32 surface;
10783 u32 tile_offset;
52331309 10784 } plane[I915_MAX_PIPES];
63b66e5b
CW		 10785
10786 struct intel_transcoder_error_state {
10787 enum transcoder cpu_transcoder;
10788
10789 u32 conf;
10790
10791 u32 htotal;
10792 u32 hblank;
10793 u32 hsync;
10794 u32 vtotal;
10795 u32 vblank;
10796 u32 vsync;
10797 } transcoder[4];
c4a1d9e4
CW		 10798};
10799
10800struct intel_display_error_state *
10801intel_display_capture_error_state(struct drm_device *dev)
10802{
0206e353 10803 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 10804 struct intel_display_error_state *error;
63b66e5b
CW		 10805 int transcoders[] = {
10806 TRANSCODER_A,
10807 TRANSCODER_B,
10808 TRANSCODER_C,
10809 TRANSCODER_EDP,
10810 };
c4a1d9e4
CW		 10811 int i;
10812
63b66e5b
CW		 10813 if (INTEL_INFO(dev)->num_pipes == 0)
10814 return NULL;
10815
c4a1d9e4
CW		 10816 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10817 if (error == NULL)
10818 return NULL;
10819
ff57f1b0
PZ		 10820 if (HAS_POWER_WELL(dev))
10821 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10822
52331309 10823 for_each_pipe(i) {
a18c4c3d
PZ		 10824 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10825 error->cursor[i].control = I915_READ(CURCNTR(i));
10826 error->cursor[i].position = I915_READ(CURPOS(i));
10827 error->cursor[i].base = I915_READ(CURBASE(i));
10828 } else {
10829 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10830 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10831 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10832 }
c4a1d9e4
CW		 10833
10834 error->plane[i].control = I915_READ(DSPCNTR(i));
10835 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 10836 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 10837 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 10838 error->plane[i].pos = I915_READ(DSPPOS(i));
10839 }
ca291363
PZ		 10840 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10841 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 10842 if (INTEL_INFO(dev)->gen >= 4) {
10843 error->plane[i].surface = I915_READ(DSPSURF(i));
10844 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10845 }
10846
c4a1d9e4 10847 error->pipe[i].source = I915_READ(PIPESRC(i));
63b66e5b
CW		 10848 }
10849
10850 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
10851 if (HAS_DDI(dev_priv->dev))
10852 error->num_transcoders++; /* Account for eDP. */
10853
10854 for (i = 0; i < error->num_transcoders; i++) {
10855 enum transcoder cpu_transcoder = transcoders[i];
10856
10857 error->transcoder[i].cpu_transcoder = cpu_transcoder;
10858
10859 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10860 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10861 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10862 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10863 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10864 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10865 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 10866 }
10867
12d217c7
PZ		 10868 /* In the code above we read the registers without checking if the power
10869 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10870 * prevent the next I915_WRITE from detecting it and printing an error
10871 * message. */
907b28c5 10872 intel_uncore_clear_errors(dev);
12d217c7 10873
c4a1d9e4
CW		 10874 return error;
10875}
10876
edc3d884
MK		 10877#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10878
c4a1d9e4 10879void
edc3d884 10880intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 10881 struct drm_device *dev,
10882 struct intel_display_error_state *error)
10883{
10884 int i;
10885
63b66e5b
CW		 10886 if (!error)
10887 return;
10888
edc3d884 10889 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 10890 if (HAS_POWER_WELL(dev))
edc3d884 10891 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 10892 error->power_well_driver);
52331309 10893 for_each_pipe(i) {
edc3d884 10894 err_printf(m, "Pipe [%d]:\n", i);
edc3d884 10895 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
edc3d884
MK		 10896
10897 err_printf(m, "Plane [%d]:\n", i);
10898 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
10899 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 10900 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 10901 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
10902 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 10903 }
4b71a570 10904 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 10905 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 10906 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 10907 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
10908 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 10909 }
10910
edc3d884
MK		 10911 err_printf(m, "Cursor [%d]:\n", i);
10912 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
10913 err_printf(m, " POS: %08x\n", error->cursor[i].position);
10914 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 10915 }
63b66e5b
CW		 10916
10917 for (i = 0; i < error->num_transcoders; i++) {
10918 err_printf(m, " CPU transcoder: %c\n",
10919 transcoder_name(error->transcoder[i].cpu_transcoder));
10920 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
10921 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
10922 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
10923 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
10924 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
10925 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
10926 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
10927 }
c4a1d9e4 10928}
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