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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
760285e7 DH |
40 | #include <drm/drm_dp_helper.h> |
41 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
42 | #include <drm/drm_plane_helper.h> |
43 | #include <drm/drm_rect.h> | |
c0f372b3 | 44 | #include <linux/dma_remapping.h> |
79e53945 | 45 | |
465c120c MR |
46 | /* Primary plane formats supported by all gen */ |
47 | #define COMMON_PRIMARY_FORMATS \ | |
48 | DRM_FORMAT_C8, \ | |
49 | DRM_FORMAT_RGB565, \ | |
50 | DRM_FORMAT_XRGB8888, \ | |
51 | DRM_FORMAT_ARGB8888 | |
52 | ||
53 | /* Primary plane formats for gen <= 3 */ | |
54 | static const uint32_t intel_primary_formats_gen2[] = { | |
55 | COMMON_PRIMARY_FORMATS, | |
56 | DRM_FORMAT_XRGB1555, | |
57 | DRM_FORMAT_ARGB1555, | |
58 | }; | |
59 | ||
60 | /* Primary plane formats for gen >= 4 */ | |
61 | static const uint32_t intel_primary_formats_gen4[] = { | |
62 | COMMON_PRIMARY_FORMATS, \ | |
63 | DRM_FORMAT_XBGR8888, | |
64 | DRM_FORMAT_ABGR8888, | |
65 | DRM_FORMAT_XRGB2101010, | |
66 | DRM_FORMAT_ARGB2101010, | |
67 | DRM_FORMAT_XBGR2101010, | |
68 | DRM_FORMAT_ABGR2101010, | |
69 | }; | |
70 | ||
3d7d6510 MR |
71 | /* Cursor formats */ |
72 | static const uint32_t intel_cursor_formats[] = { | |
73 | DRM_FORMAT_ARGB8888, | |
74 | }; | |
75 | ||
ef9348c8 | 76 | #define DIV_ROUND_CLOSEST_ULL(ll, d) \ |
465c120c | 77 | ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; }) |
ef9348c8 | 78 | |
cc36513c DV |
79 | static void intel_increase_pllclock(struct drm_device *dev, |
80 | enum pipe pipe); | |
6b383a7f | 81 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 | 82 | |
f1f644dc JB |
83 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
84 | struct intel_crtc_config *pipe_config); | |
18442d08 VS |
85 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
86 | struct intel_crtc_config *pipe_config); | |
f1f644dc | 87 | |
e7457a9a DL |
88 | static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
89 | int x, int y, struct drm_framebuffer *old_fb); | |
eb1bfe80 JB |
90 | static int intel_framebuffer_init(struct drm_device *dev, |
91 | struct intel_framebuffer *ifb, | |
92 | struct drm_mode_fb_cmd2 *mode_cmd, | |
93 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
94 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
95 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
29407aab | 96 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
97 | struct intel_link_m_n *m_n, |
98 | struct intel_link_m_n *m2_n2); | |
29407aab | 99 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 DV |
100 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
101 | static void intel_set_pipe_csc(struct drm_crtc *crtc); | |
bdd4b6a6 | 102 | static void vlv_prepare_pll(struct intel_crtc *crtc); |
e7457a9a | 103 | |
0e32b39c DA |
104 | static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe) |
105 | { | |
106 | if (!connector->mst_port) | |
107 | return connector->encoder; | |
108 | else | |
109 | return &connector->mst_port->mst_encoders[pipe]->base; | |
110 | } | |
111 | ||
79e53945 | 112 | typedef struct { |
0206e353 | 113 | int min, max; |
79e53945 JB |
114 | } intel_range_t; |
115 | ||
116 | typedef struct { | |
0206e353 AJ |
117 | int dot_limit; |
118 | int p2_slow, p2_fast; | |
79e53945 JB |
119 | } intel_p2_t; |
120 | ||
d4906093 ML |
121 | typedef struct intel_limit intel_limit_t; |
122 | struct intel_limit { | |
0206e353 AJ |
123 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
124 | intel_p2_t p2; | |
d4906093 | 125 | }; |
79e53945 | 126 | |
d2acd215 DV |
127 | int |
128 | intel_pch_rawclk(struct drm_device *dev) | |
129 | { | |
130 | struct drm_i915_private *dev_priv = dev->dev_private; | |
131 | ||
132 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
133 | ||
134 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
135 | } | |
136 | ||
021357ac CW |
137 | static inline u32 /* units of 100MHz */ |
138 | intel_fdi_link_freq(struct drm_device *dev) | |
139 | { | |
8b99e68c CW |
140 | if (IS_GEN5(dev)) { |
141 | struct drm_i915_private *dev_priv = dev->dev_private; | |
142 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
143 | } else | |
144 | return 27; | |
021357ac CW |
145 | } |
146 | ||
5d536e28 | 147 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 148 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 149 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 150 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
151 | .m = { .min = 96, .max = 140 }, |
152 | .m1 = { .min = 18, .max = 26 }, | |
153 | .m2 = { .min = 6, .max = 16 }, | |
154 | .p = { .min = 4, .max = 128 }, | |
155 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
156 | .p2 = { .dot_limit = 165000, |
157 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
158 | }; |
159 | ||
5d536e28 DV |
160 | static const intel_limit_t intel_limits_i8xx_dvo = { |
161 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 162 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 163 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
164 | .m = { .min = 96, .max = 140 }, |
165 | .m1 = { .min = 18, .max = 26 }, | |
166 | .m2 = { .min = 6, .max = 16 }, | |
167 | .p = { .min = 4, .max = 128 }, | |
168 | .p1 = { .min = 2, .max = 33 }, | |
169 | .p2 = { .dot_limit = 165000, | |
170 | .p2_slow = 4, .p2_fast = 4 }, | |
171 | }; | |
172 | ||
e4b36699 | 173 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 174 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 175 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 176 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
177 | .m = { .min = 96, .max = 140 }, |
178 | .m1 = { .min = 18, .max = 26 }, | |
179 | .m2 = { .min = 6, .max = 16 }, | |
180 | .p = { .min = 4, .max = 128 }, | |
181 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
182 | .p2 = { .dot_limit = 165000, |
183 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 184 | }; |
273e27ca | 185 | |
e4b36699 | 186 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
187 | .dot = { .min = 20000, .max = 400000 }, |
188 | .vco = { .min = 1400000, .max = 2800000 }, | |
189 | .n = { .min = 1, .max = 6 }, | |
190 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
191 | .m1 = { .min = 8, .max = 18 }, |
192 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
193 | .p = { .min = 5, .max = 80 }, |
194 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
195 | .p2 = { .dot_limit = 200000, |
196 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
197 | }; |
198 | ||
199 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
200 | .dot = { .min = 20000, .max = 400000 }, |
201 | .vco = { .min = 1400000, .max = 2800000 }, | |
202 | .n = { .min = 1, .max = 6 }, | |
203 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
204 | .m1 = { .min = 8, .max = 18 }, |
205 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
206 | .p = { .min = 7, .max = 98 }, |
207 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
208 | .p2 = { .dot_limit = 112000, |
209 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
210 | }; |
211 | ||
273e27ca | 212 | |
e4b36699 | 213 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
214 | .dot = { .min = 25000, .max = 270000 }, |
215 | .vco = { .min = 1750000, .max = 3500000}, | |
216 | .n = { .min = 1, .max = 4 }, | |
217 | .m = { .min = 104, .max = 138 }, | |
218 | .m1 = { .min = 17, .max = 23 }, | |
219 | .m2 = { .min = 5, .max = 11 }, | |
220 | .p = { .min = 10, .max = 30 }, | |
221 | .p1 = { .min = 1, .max = 3}, | |
222 | .p2 = { .dot_limit = 270000, | |
223 | .p2_slow = 10, | |
224 | .p2_fast = 10 | |
044c7c41 | 225 | }, |
e4b36699 KP |
226 | }; |
227 | ||
228 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
229 | .dot = { .min = 22000, .max = 400000 }, |
230 | .vco = { .min = 1750000, .max = 3500000}, | |
231 | .n = { .min = 1, .max = 4 }, | |
232 | .m = { .min = 104, .max = 138 }, | |
233 | .m1 = { .min = 16, .max = 23 }, | |
234 | .m2 = { .min = 5, .max = 11 }, | |
235 | .p = { .min = 5, .max = 80 }, | |
236 | .p1 = { .min = 1, .max = 8}, | |
237 | .p2 = { .dot_limit = 165000, | |
238 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
239 | }; |
240 | ||
241 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
242 | .dot = { .min = 20000, .max = 115000 }, |
243 | .vco = { .min = 1750000, .max = 3500000 }, | |
244 | .n = { .min = 1, .max = 3 }, | |
245 | .m = { .min = 104, .max = 138 }, | |
246 | .m1 = { .min = 17, .max = 23 }, | |
247 | .m2 = { .min = 5, .max = 11 }, | |
248 | .p = { .min = 28, .max = 112 }, | |
249 | .p1 = { .min = 2, .max = 8 }, | |
250 | .p2 = { .dot_limit = 0, | |
251 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 252 | }, |
e4b36699 KP |
253 | }; |
254 | ||
255 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
256 | .dot = { .min = 80000, .max = 224000 }, |
257 | .vco = { .min = 1750000, .max = 3500000 }, | |
258 | .n = { .min = 1, .max = 3 }, | |
259 | .m = { .min = 104, .max = 138 }, | |
260 | .m1 = { .min = 17, .max = 23 }, | |
261 | .m2 = { .min = 5, .max = 11 }, | |
262 | .p = { .min = 14, .max = 42 }, | |
263 | .p1 = { .min = 2, .max = 6 }, | |
264 | .p2 = { .dot_limit = 0, | |
265 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 266 | }, |
e4b36699 KP |
267 | }; |
268 | ||
f2b115e6 | 269 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
270 | .dot = { .min = 20000, .max = 400000}, |
271 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 272 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
273 | .n = { .min = 3, .max = 6 }, |
274 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 275 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
276 | .m1 = { .min = 0, .max = 0 }, |
277 | .m2 = { .min = 0, .max = 254 }, | |
278 | .p = { .min = 5, .max = 80 }, | |
279 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
280 | .p2 = { .dot_limit = 200000, |
281 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
282 | }; |
283 | ||
f2b115e6 | 284 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
285 | .dot = { .min = 20000, .max = 400000 }, |
286 | .vco = { .min = 1700000, .max = 3500000 }, | |
287 | .n = { .min = 3, .max = 6 }, | |
288 | .m = { .min = 2, .max = 256 }, | |
289 | .m1 = { .min = 0, .max = 0 }, | |
290 | .m2 = { .min = 0, .max = 254 }, | |
291 | .p = { .min = 7, .max = 112 }, | |
292 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
293 | .p2 = { .dot_limit = 112000, |
294 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
295 | }; |
296 | ||
273e27ca EA |
297 | /* Ironlake / Sandybridge |
298 | * | |
299 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
300 | * the range value for them is (actual_value - 2). | |
301 | */ | |
b91ad0ec | 302 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
303 | .dot = { .min = 25000, .max = 350000 }, |
304 | .vco = { .min = 1760000, .max = 3510000 }, | |
305 | .n = { .min = 1, .max = 5 }, | |
306 | .m = { .min = 79, .max = 127 }, | |
307 | .m1 = { .min = 12, .max = 22 }, | |
308 | .m2 = { .min = 5, .max = 9 }, | |
309 | .p = { .min = 5, .max = 80 }, | |
310 | .p1 = { .min = 1, .max = 8 }, | |
311 | .p2 = { .dot_limit = 225000, | |
312 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
313 | }; |
314 | ||
b91ad0ec | 315 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
316 | .dot = { .min = 25000, .max = 350000 }, |
317 | .vco = { .min = 1760000, .max = 3510000 }, | |
318 | .n = { .min = 1, .max = 3 }, | |
319 | .m = { .min = 79, .max = 118 }, | |
320 | .m1 = { .min = 12, .max = 22 }, | |
321 | .m2 = { .min = 5, .max = 9 }, | |
322 | .p = { .min = 28, .max = 112 }, | |
323 | .p1 = { .min = 2, .max = 8 }, | |
324 | .p2 = { .dot_limit = 225000, | |
325 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
326 | }; |
327 | ||
328 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
329 | .dot = { .min = 25000, .max = 350000 }, |
330 | .vco = { .min = 1760000, .max = 3510000 }, | |
331 | .n = { .min = 1, .max = 3 }, | |
332 | .m = { .min = 79, .max = 127 }, | |
333 | .m1 = { .min = 12, .max = 22 }, | |
334 | .m2 = { .min = 5, .max = 9 }, | |
335 | .p = { .min = 14, .max = 56 }, | |
336 | .p1 = { .min = 2, .max = 8 }, | |
337 | .p2 = { .dot_limit = 225000, | |
338 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
339 | }; |
340 | ||
273e27ca | 341 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 342 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
343 | .dot = { .min = 25000, .max = 350000 }, |
344 | .vco = { .min = 1760000, .max = 3510000 }, | |
345 | .n = { .min = 1, .max = 2 }, | |
346 | .m = { .min = 79, .max = 126 }, | |
347 | .m1 = { .min = 12, .max = 22 }, | |
348 | .m2 = { .min = 5, .max = 9 }, | |
349 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 350 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
351 | .p2 = { .dot_limit = 225000, |
352 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
353 | }; |
354 | ||
355 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
356 | .dot = { .min = 25000, .max = 350000 }, |
357 | .vco = { .min = 1760000, .max = 3510000 }, | |
358 | .n = { .min = 1, .max = 3 }, | |
359 | .m = { .min = 79, .max = 126 }, | |
360 | .m1 = { .min = 12, .max = 22 }, | |
361 | .m2 = { .min = 5, .max = 9 }, | |
362 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 363 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
364 | .p2 = { .dot_limit = 225000, |
365 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
366 | }; |
367 | ||
dc730512 | 368 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
369 | /* |
370 | * These are the data rate limits (measured in fast clocks) | |
371 | * since those are the strictest limits we have. The fast | |
372 | * clock and actual rate limits are more relaxed, so checking | |
373 | * them would make no difference. | |
374 | */ | |
375 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 376 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 377 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
378 | .m1 = { .min = 2, .max = 3 }, |
379 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 380 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 381 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
382 | }; |
383 | ||
ef9348c8 CML |
384 | static const intel_limit_t intel_limits_chv = { |
385 | /* | |
386 | * These are the data rate limits (measured in fast clocks) | |
387 | * since those are the strictest limits we have. The fast | |
388 | * clock and actual rate limits are more relaxed, so checking | |
389 | * them would make no difference. | |
390 | */ | |
391 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
392 | .vco = { .min = 4860000, .max = 6700000 }, | |
393 | .n = { .min = 1, .max = 1 }, | |
394 | .m1 = { .min = 2, .max = 2 }, | |
395 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
396 | .p1 = { .min = 2, .max = 4 }, | |
397 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
398 | }; | |
399 | ||
6b4bf1c4 VS |
400 | static void vlv_clock(int refclk, intel_clock_t *clock) |
401 | { | |
402 | clock->m = clock->m1 * clock->m2; | |
403 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
404 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
405 | return; | |
fb03ac01 VS |
406 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
407 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
6b4bf1c4 VS |
408 | } |
409 | ||
e0638cdf PZ |
410 | /** |
411 | * Returns whether any output on the specified pipe is of the specified type | |
412 | */ | |
413 | static bool intel_pipe_has_type(struct drm_crtc *crtc, int type) | |
414 | { | |
415 | struct drm_device *dev = crtc->dev; | |
416 | struct intel_encoder *encoder; | |
417 | ||
418 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
419 | if (encoder->type == type) | |
420 | return true; | |
421 | ||
422 | return false; | |
423 | } | |
424 | ||
1b894b59 CW |
425 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
426 | int refclk) | |
2c07245f | 427 | { |
b91ad0ec | 428 | struct drm_device *dev = crtc->dev; |
2c07245f | 429 | const intel_limit_t *limit; |
b91ad0ec ZW |
430 | |
431 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 432 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 433 | if (refclk == 100000) |
b91ad0ec ZW |
434 | limit = &intel_limits_ironlake_dual_lvds_100m; |
435 | else | |
436 | limit = &intel_limits_ironlake_dual_lvds; | |
437 | } else { | |
1b894b59 | 438 | if (refclk == 100000) |
b91ad0ec ZW |
439 | limit = &intel_limits_ironlake_single_lvds_100m; |
440 | else | |
441 | limit = &intel_limits_ironlake_single_lvds; | |
442 | } | |
c6bb3538 | 443 | } else |
b91ad0ec | 444 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
445 | |
446 | return limit; | |
447 | } | |
448 | ||
044c7c41 ML |
449 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
450 | { | |
451 | struct drm_device *dev = crtc->dev; | |
044c7c41 ML |
452 | const intel_limit_t *limit; |
453 | ||
454 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 455 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 456 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 457 | else |
e4b36699 | 458 | limit = &intel_limits_g4x_single_channel_lvds; |
044c7c41 ML |
459 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
460 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 461 | limit = &intel_limits_g4x_hdmi; |
044c7c41 | 462 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 463 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 464 | } else /* The option is for other outputs */ |
e4b36699 | 465 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
466 | |
467 | return limit; | |
468 | } | |
469 | ||
1b894b59 | 470 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
79e53945 JB |
471 | { |
472 | struct drm_device *dev = crtc->dev; | |
473 | const intel_limit_t *limit; | |
474 | ||
bad720ff | 475 | if (HAS_PCH_SPLIT(dev)) |
1b894b59 | 476 | limit = intel_ironlake_limit(crtc, refclk); |
2c07245f | 477 | else if (IS_G4X(dev)) { |
044c7c41 | 478 | limit = intel_g4x_limit(crtc); |
f2b115e6 | 479 | } else if (IS_PINEVIEW(dev)) { |
2177832f | 480 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 481 | limit = &intel_limits_pineview_lvds; |
2177832f | 482 | else |
f2b115e6 | 483 | limit = &intel_limits_pineview_sdvo; |
ef9348c8 CML |
484 | } else if (IS_CHERRYVIEW(dev)) { |
485 | limit = &intel_limits_chv; | |
a0c4da24 | 486 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 487 | limit = &intel_limits_vlv; |
a6c45cf0 CW |
488 | } else if (!IS_GEN2(dev)) { |
489 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
490 | limit = &intel_limits_i9xx_lvds; | |
491 | else | |
492 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 JB |
493 | } else { |
494 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
e4b36699 | 495 | limit = &intel_limits_i8xx_lvds; |
5d536e28 | 496 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO)) |
e4b36699 | 497 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
498 | else |
499 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
500 | } |
501 | return limit; | |
502 | } | |
503 | ||
f2b115e6 AJ |
504 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
505 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 506 | { |
2177832f SL |
507 | clock->m = clock->m2 + 2; |
508 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
509 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
510 | return; | |
fb03ac01 VS |
511 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
512 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
2177832f SL |
513 | } |
514 | ||
7429e9d4 DV |
515 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
516 | { | |
517 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
518 | } | |
519 | ||
ac58c3f0 | 520 | static void i9xx_clock(int refclk, intel_clock_t *clock) |
2177832f | 521 | { |
7429e9d4 | 522 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 523 | clock->p = clock->p1 * clock->p2; |
ed5ca77e VS |
524 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
525 | return; | |
fb03ac01 VS |
526 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
527 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
79e53945 JB |
528 | } |
529 | ||
ef9348c8 CML |
530 | static void chv_clock(int refclk, intel_clock_t *clock) |
531 | { | |
532 | clock->m = clock->m1 * clock->m2; | |
533 | clock->p = clock->p1 * clock->p2; | |
534 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
535 | return; | |
536 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, | |
537 | clock->n << 22); | |
538 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
539 | } | |
540 | ||
7c04d1d9 | 541 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
542 | /** |
543 | * Returns whether the given set of divisors are valid for a given refclk with | |
544 | * the given connectors. | |
545 | */ | |
546 | ||
1b894b59 CW |
547 | static bool intel_PLL_is_valid(struct drm_device *dev, |
548 | const intel_limit_t *limit, | |
549 | const intel_clock_t *clock) | |
79e53945 | 550 | { |
f01b7962 VS |
551 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
552 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 553 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 554 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 555 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 556 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 557 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 558 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 VS |
559 | |
560 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev)) | |
561 | if (clock->m1 <= clock->m2) | |
562 | INTELPllInvalid("m1 <= m2\n"); | |
563 | ||
564 | if (!IS_VALLEYVIEW(dev)) { | |
565 | if (clock->p < limit->p.min || limit->p.max < clock->p) | |
566 | INTELPllInvalid("p out of range\n"); | |
567 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
568 | INTELPllInvalid("m out of range\n"); | |
569 | } | |
570 | ||
79e53945 | 571 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 572 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
573 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
574 | * connector, etc., rather than just a single range. | |
575 | */ | |
576 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 577 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
578 | |
579 | return true; | |
580 | } | |
581 | ||
d4906093 | 582 | static bool |
ee9300bb | 583 | i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
cec2f356 SP |
584 | int target, int refclk, intel_clock_t *match_clock, |
585 | intel_clock_t *best_clock) | |
79e53945 JB |
586 | { |
587 | struct drm_device *dev = crtc->dev; | |
79e53945 | 588 | intel_clock_t clock; |
79e53945 JB |
589 | int err = target; |
590 | ||
a210b028 | 591 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 592 | /* |
a210b028 DV |
593 | * For LVDS just rely on its current settings for dual-channel. |
594 | * We haven't figured out how to reliably set up different | |
595 | * single/dual channel state, if we even can. | |
79e53945 | 596 | */ |
1974cad0 | 597 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
598 | clock.p2 = limit->p2.p2_fast; |
599 | else | |
600 | clock.p2 = limit->p2.p2_slow; | |
601 | } else { | |
602 | if (target < limit->p2.dot_limit) | |
603 | clock.p2 = limit->p2.p2_slow; | |
604 | else | |
605 | clock.p2 = limit->p2.p2_fast; | |
606 | } | |
607 | ||
0206e353 | 608 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 609 | |
42158660 ZY |
610 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
611 | clock.m1++) { | |
612 | for (clock.m2 = limit->m2.min; | |
613 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 614 | if (clock.m2 >= clock.m1) |
42158660 ZY |
615 | break; |
616 | for (clock.n = limit->n.min; | |
617 | clock.n <= limit->n.max; clock.n++) { | |
618 | for (clock.p1 = limit->p1.min; | |
619 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
620 | int this_err; |
621 | ||
ac58c3f0 DV |
622 | i9xx_clock(refclk, &clock); |
623 | if (!intel_PLL_is_valid(dev, limit, | |
624 | &clock)) | |
625 | continue; | |
626 | if (match_clock && | |
627 | clock.p != match_clock->p) | |
628 | continue; | |
629 | ||
630 | this_err = abs(clock.dot - target); | |
631 | if (this_err < err) { | |
632 | *best_clock = clock; | |
633 | err = this_err; | |
634 | } | |
635 | } | |
636 | } | |
637 | } | |
638 | } | |
639 | ||
640 | return (err != target); | |
641 | } | |
642 | ||
643 | static bool | |
ee9300bb DV |
644 | pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
645 | int target, int refclk, intel_clock_t *match_clock, | |
646 | intel_clock_t *best_clock) | |
79e53945 JB |
647 | { |
648 | struct drm_device *dev = crtc->dev; | |
79e53945 | 649 | intel_clock_t clock; |
79e53945 JB |
650 | int err = target; |
651 | ||
a210b028 | 652 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 653 | /* |
a210b028 DV |
654 | * For LVDS just rely on its current settings for dual-channel. |
655 | * We haven't figured out how to reliably set up different | |
656 | * single/dual channel state, if we even can. | |
79e53945 | 657 | */ |
1974cad0 | 658 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
659 | clock.p2 = limit->p2.p2_fast; |
660 | else | |
661 | clock.p2 = limit->p2.p2_slow; | |
662 | } else { | |
663 | if (target < limit->p2.dot_limit) | |
664 | clock.p2 = limit->p2.p2_slow; | |
665 | else | |
666 | clock.p2 = limit->p2.p2_fast; | |
667 | } | |
668 | ||
0206e353 | 669 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 670 | |
42158660 ZY |
671 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
672 | clock.m1++) { | |
673 | for (clock.m2 = limit->m2.min; | |
674 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
675 | for (clock.n = limit->n.min; |
676 | clock.n <= limit->n.max; clock.n++) { | |
677 | for (clock.p1 = limit->p1.min; | |
678 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
679 | int this_err; |
680 | ||
ac58c3f0 | 681 | pineview_clock(refclk, &clock); |
1b894b59 CW |
682 | if (!intel_PLL_is_valid(dev, limit, |
683 | &clock)) | |
79e53945 | 684 | continue; |
cec2f356 SP |
685 | if (match_clock && |
686 | clock.p != match_clock->p) | |
687 | continue; | |
79e53945 JB |
688 | |
689 | this_err = abs(clock.dot - target); | |
690 | if (this_err < err) { | |
691 | *best_clock = clock; | |
692 | err = this_err; | |
693 | } | |
694 | } | |
695 | } | |
696 | } | |
697 | } | |
698 | ||
699 | return (err != target); | |
700 | } | |
701 | ||
d4906093 | 702 | static bool |
ee9300bb DV |
703 | g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
704 | int target, int refclk, intel_clock_t *match_clock, | |
705 | intel_clock_t *best_clock) | |
d4906093 ML |
706 | { |
707 | struct drm_device *dev = crtc->dev; | |
d4906093 ML |
708 | intel_clock_t clock; |
709 | int max_n; | |
710 | bool found; | |
6ba770dc AJ |
711 | /* approximately equals target * 0.00585 */ |
712 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
713 | found = false; |
714 | ||
715 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 716 | if (intel_is_dual_link_lvds(dev)) |
d4906093 ML |
717 | clock.p2 = limit->p2.p2_fast; |
718 | else | |
719 | clock.p2 = limit->p2.p2_slow; | |
720 | } else { | |
721 | if (target < limit->p2.dot_limit) | |
722 | clock.p2 = limit->p2.p2_slow; | |
723 | else | |
724 | clock.p2 = limit->p2.p2_fast; | |
725 | } | |
726 | ||
727 | memset(best_clock, 0, sizeof(*best_clock)); | |
728 | max_n = limit->n.max; | |
f77f13e2 | 729 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 730 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 731 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
732 | for (clock.m1 = limit->m1.max; |
733 | clock.m1 >= limit->m1.min; clock.m1--) { | |
734 | for (clock.m2 = limit->m2.max; | |
735 | clock.m2 >= limit->m2.min; clock.m2--) { | |
736 | for (clock.p1 = limit->p1.max; | |
737 | clock.p1 >= limit->p1.min; clock.p1--) { | |
738 | int this_err; | |
739 | ||
ac58c3f0 | 740 | i9xx_clock(refclk, &clock); |
1b894b59 CW |
741 | if (!intel_PLL_is_valid(dev, limit, |
742 | &clock)) | |
d4906093 | 743 | continue; |
1b894b59 CW |
744 | |
745 | this_err = abs(clock.dot - target); | |
d4906093 ML |
746 | if (this_err < err_most) { |
747 | *best_clock = clock; | |
748 | err_most = this_err; | |
749 | max_n = clock.n; | |
750 | found = true; | |
751 | } | |
752 | } | |
753 | } | |
754 | } | |
755 | } | |
2c07245f ZW |
756 | return found; |
757 | } | |
758 | ||
a0c4da24 | 759 | static bool |
ee9300bb DV |
760 | vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
761 | int target, int refclk, intel_clock_t *match_clock, | |
762 | intel_clock_t *best_clock) | |
a0c4da24 | 763 | { |
f01b7962 | 764 | struct drm_device *dev = crtc->dev; |
6b4bf1c4 | 765 | intel_clock_t clock; |
69e4f900 | 766 | unsigned int bestppm = 1000000; |
27e639bf VS |
767 | /* min update 19.2 MHz */ |
768 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 769 | bool found = false; |
a0c4da24 | 770 | |
6b4bf1c4 VS |
771 | target *= 5; /* fast clock */ |
772 | ||
773 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
774 | |
775 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 776 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 777 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 778 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 779 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 780 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 781 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 782 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
69e4f900 VS |
783 | unsigned int ppm, diff; |
784 | ||
6b4bf1c4 VS |
785 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
786 | refclk * clock.m1); | |
787 | ||
788 | vlv_clock(refclk, &clock); | |
43b0ac53 | 789 | |
f01b7962 VS |
790 | if (!intel_PLL_is_valid(dev, limit, |
791 | &clock)) | |
43b0ac53 VS |
792 | continue; |
793 | ||
6b4bf1c4 VS |
794 | diff = abs(clock.dot - target); |
795 | ppm = div_u64(1000000ULL * diff, target); | |
796 | ||
797 | if (ppm < 100 && clock.p > best_clock->p) { | |
43b0ac53 | 798 | bestppm = 0; |
6b4bf1c4 | 799 | *best_clock = clock; |
49e497ef | 800 | found = true; |
43b0ac53 | 801 | } |
6b4bf1c4 | 802 | |
c686122c | 803 | if (bestppm >= 10 && ppm < bestppm - 10) { |
69e4f900 | 804 | bestppm = ppm; |
6b4bf1c4 | 805 | *best_clock = clock; |
49e497ef | 806 | found = true; |
a0c4da24 JB |
807 | } |
808 | } | |
809 | } | |
810 | } | |
811 | } | |
a0c4da24 | 812 | |
49e497ef | 813 | return found; |
a0c4da24 | 814 | } |
a4fc5ed6 | 815 | |
ef9348c8 CML |
816 | static bool |
817 | chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, | |
818 | int target, int refclk, intel_clock_t *match_clock, | |
819 | intel_clock_t *best_clock) | |
820 | { | |
821 | struct drm_device *dev = crtc->dev; | |
822 | intel_clock_t clock; | |
823 | uint64_t m2; | |
824 | int found = false; | |
825 | ||
826 | memset(best_clock, 0, sizeof(*best_clock)); | |
827 | ||
828 | /* | |
829 | * Based on hardware doc, the n always set to 1, and m1 always | |
830 | * set to 2. If requires to support 200Mhz refclk, we need to | |
831 | * revisit this because n may not 1 anymore. | |
832 | */ | |
833 | clock.n = 1, clock.m1 = 2; | |
834 | target *= 5; /* fast clock */ | |
835 | ||
836 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
837 | for (clock.p2 = limit->p2.p2_fast; | |
838 | clock.p2 >= limit->p2.p2_slow; | |
839 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
840 | ||
841 | clock.p = clock.p1 * clock.p2; | |
842 | ||
843 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
844 | clock.n) << 22, refclk * clock.m1); | |
845 | ||
846 | if (m2 > INT_MAX/clock.m1) | |
847 | continue; | |
848 | ||
849 | clock.m2 = m2; | |
850 | ||
851 | chv_clock(refclk, &clock); | |
852 | ||
853 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
854 | continue; | |
855 | ||
856 | /* based on hardware requirement, prefer bigger p | |
857 | */ | |
858 | if (clock.p > best_clock->p) { | |
859 | *best_clock = clock; | |
860 | found = true; | |
861 | } | |
862 | } | |
863 | } | |
864 | ||
865 | return found; | |
866 | } | |
867 | ||
20ddf665 VS |
868 | bool intel_crtc_active(struct drm_crtc *crtc) |
869 | { | |
870 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
871 | ||
872 | /* Be paranoid as we can arrive here with only partial | |
873 | * state retrieved from the hardware during setup. | |
874 | * | |
241bfc38 | 875 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
876 | * as Haswell has gained clock readout/fastboot support. |
877 | * | |
66e514c1 | 878 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 VS |
879 | * properly reconstruct framebuffers. |
880 | */ | |
f4510a27 | 881 | return intel_crtc->active && crtc->primary->fb && |
241bfc38 | 882 | intel_crtc->config.adjusted_mode.crtc_clock; |
20ddf665 VS |
883 | } |
884 | ||
a5c961d1 PZ |
885 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
886 | enum pipe pipe) | |
887 | { | |
888 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
889 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
890 | ||
3b117c8f | 891 | return intel_crtc->config.cpu_transcoder; |
a5c961d1 PZ |
892 | } |
893 | ||
57e22f4a | 894 | static void g4x_wait_for_vblank(struct drm_device *dev, int pipe) |
a928d536 PZ |
895 | { |
896 | struct drm_i915_private *dev_priv = dev->dev_private; | |
57e22f4a | 897 | u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe); |
a928d536 PZ |
898 | |
899 | frame = I915_READ(frame_reg); | |
900 | ||
901 | if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50)) | |
93937071 | 902 | WARN(1, "vblank wait timed out\n"); |
a928d536 PZ |
903 | } |
904 | ||
9d0498a2 JB |
905 | /** |
906 | * intel_wait_for_vblank - wait for vblank on a given pipe | |
907 | * @dev: drm device | |
908 | * @pipe: pipe to wait for | |
909 | * | |
910 | * Wait for vblank to occur on a given pipe. Needed for various bits of | |
911 | * mode setting code. | |
912 | */ | |
913 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) | |
79e53945 | 914 | { |
9d0498a2 | 915 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 916 | int pipestat_reg = PIPESTAT(pipe); |
9d0498a2 | 917 | |
57e22f4a VS |
918 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
919 | g4x_wait_for_vblank(dev, pipe); | |
a928d536 PZ |
920 | return; |
921 | } | |
922 | ||
300387c0 CW |
923 | /* Clear existing vblank status. Note this will clear any other |
924 | * sticky status fields as well. | |
925 | * | |
926 | * This races with i915_driver_irq_handler() with the result | |
927 | * that either function could miss a vblank event. Here it is not | |
928 | * fatal, as we will either wait upon the next vblank interrupt or | |
929 | * timeout. Generally speaking intel_wait_for_vblank() is only | |
930 | * called during modeset at which time the GPU should be idle and | |
931 | * should *not* be performing page flips and thus not waiting on | |
932 | * vblanks... | |
933 | * Currently, the result of us stealing a vblank from the irq | |
934 | * handler is that a single frame will be skipped during swapbuffers. | |
935 | */ | |
936 | I915_WRITE(pipestat_reg, | |
937 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); | |
938 | ||
9d0498a2 | 939 | /* Wait for vblank interrupt bit to set */ |
481b6af3 CW |
940 | if (wait_for(I915_READ(pipestat_reg) & |
941 | PIPE_VBLANK_INTERRUPT_STATUS, | |
942 | 50)) | |
9d0498a2 JB |
943 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
944 | } | |
945 | ||
fbf49ea2 VS |
946 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
947 | { | |
948 | struct drm_i915_private *dev_priv = dev->dev_private; | |
949 | u32 reg = PIPEDSL(pipe); | |
950 | u32 line1, line2; | |
951 | u32 line_mask; | |
952 | ||
953 | if (IS_GEN2(dev)) | |
954 | line_mask = DSL_LINEMASK_GEN2; | |
955 | else | |
956 | line_mask = DSL_LINEMASK_GEN3; | |
957 | ||
958 | line1 = I915_READ(reg) & line_mask; | |
959 | mdelay(5); | |
960 | line2 = I915_READ(reg) & line_mask; | |
961 | ||
962 | return line1 == line2; | |
963 | } | |
964 | ||
ab7ad7f6 KP |
965 | /* |
966 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
9d0498a2 JB |
967 | * @dev: drm device |
968 | * @pipe: pipe to wait for | |
969 | * | |
970 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
971 | * spinning on the vblank interrupt status bit, since we won't actually | |
972 | * see an interrupt when the pipe is disabled. | |
973 | * | |
ab7ad7f6 KP |
974 | * On Gen4 and above: |
975 | * wait for the pipe register state bit to turn off | |
976 | * | |
977 | * Otherwise: | |
978 | * wait for the display line value to settle (it usually | |
979 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 980 | * |
9d0498a2 | 981 | */ |
58e10eb9 | 982 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
9d0498a2 JB |
983 | { |
984 | struct drm_i915_private *dev_priv = dev->dev_private; | |
702e7a56 PZ |
985 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
986 | pipe); | |
ab7ad7f6 KP |
987 | |
988 | if (INTEL_INFO(dev)->gen >= 4) { | |
702e7a56 | 989 | int reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
990 | |
991 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
992 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
993 | 100)) | |
284637d9 | 994 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 995 | } else { |
ab7ad7f6 | 996 | /* Wait for the display line to settle */ |
fbf49ea2 | 997 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 998 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 999 | } |
79e53945 JB |
1000 | } |
1001 | ||
b0ea7d37 DL |
1002 | /* |
1003 | * ibx_digital_port_connected - is the specified port connected? | |
1004 | * @dev_priv: i915 private structure | |
1005 | * @port: the port to test | |
1006 | * | |
1007 | * Returns true if @port is connected, false otherwise. | |
1008 | */ | |
1009 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, | |
1010 | struct intel_digital_port *port) | |
1011 | { | |
1012 | u32 bit; | |
1013 | ||
c36346e3 | 1014 | if (HAS_PCH_IBX(dev_priv->dev)) { |
eba905b2 | 1015 | switch (port->port) { |
c36346e3 DL |
1016 | case PORT_B: |
1017 | bit = SDE_PORTB_HOTPLUG; | |
1018 | break; | |
1019 | case PORT_C: | |
1020 | bit = SDE_PORTC_HOTPLUG; | |
1021 | break; | |
1022 | case PORT_D: | |
1023 | bit = SDE_PORTD_HOTPLUG; | |
1024 | break; | |
1025 | default: | |
1026 | return true; | |
1027 | } | |
1028 | } else { | |
eba905b2 | 1029 | switch (port->port) { |
c36346e3 DL |
1030 | case PORT_B: |
1031 | bit = SDE_PORTB_HOTPLUG_CPT; | |
1032 | break; | |
1033 | case PORT_C: | |
1034 | bit = SDE_PORTC_HOTPLUG_CPT; | |
1035 | break; | |
1036 | case PORT_D: | |
1037 | bit = SDE_PORTD_HOTPLUG_CPT; | |
1038 | break; | |
1039 | default: | |
1040 | return true; | |
1041 | } | |
b0ea7d37 DL |
1042 | } |
1043 | ||
1044 | return I915_READ(SDEISR) & bit; | |
1045 | } | |
1046 | ||
b24e7179 JB |
1047 | static const char *state_string(bool enabled) |
1048 | { | |
1049 | return enabled ? "on" : "off"; | |
1050 | } | |
1051 | ||
1052 | /* Only for pre-ILK configs */ | |
55607e8a DV |
1053 | void assert_pll(struct drm_i915_private *dev_priv, |
1054 | enum pipe pipe, bool state) | |
b24e7179 JB |
1055 | { |
1056 | int reg; | |
1057 | u32 val; | |
1058 | bool cur_state; | |
1059 | ||
1060 | reg = DPLL(pipe); | |
1061 | val = I915_READ(reg); | |
1062 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
1063 | WARN(cur_state != state, | |
1064 | "PLL state assertion failure (expected %s, current %s)\n", | |
1065 | state_string(state), state_string(cur_state)); | |
1066 | } | |
b24e7179 | 1067 | |
23538ef1 JN |
1068 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
1069 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
1070 | { | |
1071 | u32 val; | |
1072 | bool cur_state; | |
1073 | ||
1074 | mutex_lock(&dev_priv->dpio_lock); | |
1075 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); | |
1076 | mutex_unlock(&dev_priv->dpio_lock); | |
1077 | ||
1078 | cur_state = val & DSI_PLL_VCO_EN; | |
1079 | WARN(cur_state != state, | |
1080 | "DSI PLL state assertion failure (expected %s, current %s)\n", | |
1081 | state_string(state), state_string(cur_state)); | |
1082 | } | |
1083 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1084 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
1085 | ||
55607e8a | 1086 | struct intel_shared_dpll * |
e2b78267 DV |
1087 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
1088 | { | |
1089 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
1090 | ||
a43f6e0f | 1091 | if (crtc->config.shared_dpll < 0) |
e2b78267 DV |
1092 | return NULL; |
1093 | ||
a43f6e0f | 1094 | return &dev_priv->shared_dplls[crtc->config.shared_dpll]; |
e2b78267 DV |
1095 | } |
1096 | ||
040484af | 1097 | /* For ILK+ */ |
55607e8a DV |
1098 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
1099 | struct intel_shared_dpll *pll, | |
1100 | bool state) | |
040484af | 1101 | { |
040484af | 1102 | bool cur_state; |
5358901f | 1103 | struct intel_dpll_hw_state hw_state; |
040484af | 1104 | |
92b27b08 | 1105 | if (WARN (!pll, |
46edb027 | 1106 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
ee7b9f93 | 1107 | return; |
ee7b9f93 | 1108 | |
5358901f | 1109 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
92b27b08 | 1110 | WARN(cur_state != state, |
5358901f DV |
1111 | "%s assertion failure (expected %s, current %s)\n", |
1112 | pll->name, state_string(state), state_string(cur_state)); | |
040484af | 1113 | } |
040484af JB |
1114 | |
1115 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1116 | enum pipe pipe, bool state) | |
1117 | { | |
1118 | int reg; | |
1119 | u32 val; | |
1120 | bool cur_state; | |
ad80a810 PZ |
1121 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1122 | pipe); | |
040484af | 1123 | |
affa9354 PZ |
1124 | if (HAS_DDI(dev_priv->dev)) { |
1125 | /* DDI does not have a specific FDI_TX register */ | |
ad80a810 | 1126 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
bf507ef7 | 1127 | val = I915_READ(reg); |
ad80a810 | 1128 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 ED |
1129 | } else { |
1130 | reg = FDI_TX_CTL(pipe); | |
1131 | val = I915_READ(reg); | |
1132 | cur_state = !!(val & FDI_TX_ENABLE); | |
1133 | } | |
040484af JB |
1134 | WARN(cur_state != state, |
1135 | "FDI TX state assertion failure (expected %s, current %s)\n", | |
1136 | state_string(state), state_string(cur_state)); | |
1137 | } | |
1138 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1139 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1140 | ||
1141 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1142 | enum pipe pipe, bool state) | |
1143 | { | |
1144 | int reg; | |
1145 | u32 val; | |
1146 | bool cur_state; | |
1147 | ||
d63fa0dc PZ |
1148 | reg = FDI_RX_CTL(pipe); |
1149 | val = I915_READ(reg); | |
1150 | cur_state = !!(val & FDI_RX_ENABLE); | |
040484af JB |
1151 | WARN(cur_state != state, |
1152 | "FDI RX state assertion failure (expected %s, current %s)\n", | |
1153 | state_string(state), state_string(cur_state)); | |
1154 | } | |
1155 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1156 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1157 | ||
1158 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1159 | enum pipe pipe) | |
1160 | { | |
1161 | int reg; | |
1162 | u32 val; | |
1163 | ||
1164 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1165 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1166 | return; |
1167 | ||
bf507ef7 | 1168 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1169 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1170 | return; |
1171 | ||
040484af JB |
1172 | reg = FDI_TX_CTL(pipe); |
1173 | val = I915_READ(reg); | |
1174 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); | |
1175 | } | |
1176 | ||
55607e8a DV |
1177 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1178 | enum pipe pipe, bool state) | |
040484af JB |
1179 | { |
1180 | int reg; | |
1181 | u32 val; | |
55607e8a | 1182 | bool cur_state; |
040484af JB |
1183 | |
1184 | reg = FDI_RX_CTL(pipe); | |
1185 | val = I915_READ(reg); | |
55607e8a DV |
1186 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
1187 | WARN(cur_state != state, | |
1188 | "FDI RX PLL assertion failure (expected %s, current %s)\n", | |
1189 | state_string(state), state_string(cur_state)); | |
040484af JB |
1190 | } |
1191 | ||
ea0760cf JB |
1192 | static void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1193 | enum pipe pipe) | |
1194 | { | |
1195 | int pp_reg, lvds_reg; | |
1196 | u32 val; | |
1197 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1198 | bool locked = true; |
ea0760cf JB |
1199 | |
1200 | if (HAS_PCH_SPLIT(dev_priv->dev)) { | |
1201 | pp_reg = PCH_PP_CONTROL; | |
1202 | lvds_reg = PCH_LVDS; | |
1203 | } else { | |
1204 | pp_reg = PP_CONTROL; | |
1205 | lvds_reg = LVDS; | |
1206 | } | |
1207 | ||
1208 | val = I915_READ(pp_reg); | |
1209 | if (!(val & PANEL_POWER_ON) || | |
1210 | ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) | |
1211 | locked = false; | |
1212 | ||
1213 | if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) | |
1214 | panel_pipe = PIPE_B; | |
1215 | ||
1216 | WARN(panel_pipe == pipe && locked, | |
1217 | "panel assertion failure, pipe %c regs locked\n", | |
9db4a9c7 | 1218 | pipe_name(pipe)); |
ea0760cf JB |
1219 | } |
1220 | ||
93ce0ba6 JN |
1221 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1222 | enum pipe pipe, bool state) | |
1223 | { | |
1224 | struct drm_device *dev = dev_priv->dev; | |
1225 | bool cur_state; | |
1226 | ||
d9d82081 | 1227 | if (IS_845G(dev) || IS_I865G(dev)) |
93ce0ba6 | 1228 | cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE; |
d9d82081 | 1229 | else |
5efb3e28 | 1230 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 JN |
1231 | |
1232 | WARN(cur_state != state, | |
1233 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", | |
1234 | pipe_name(pipe), state_string(state), state_string(cur_state)); | |
1235 | } | |
1236 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1237 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1238 | ||
b840d907 JB |
1239 | void assert_pipe(struct drm_i915_private *dev_priv, |
1240 | enum pipe pipe, bool state) | |
b24e7179 JB |
1241 | { |
1242 | int reg; | |
1243 | u32 val; | |
63d7bbe9 | 1244 | bool cur_state; |
702e7a56 PZ |
1245 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1246 | pipe); | |
b24e7179 | 1247 | |
8e636784 DV |
1248 | /* if we need the pipe A quirk it must be always on */ |
1249 | if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
1250 | state = true; | |
1251 | ||
da7e29bd | 1252 | if (!intel_display_power_enabled(dev_priv, |
b97186f0 | 1253 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
69310161 PZ |
1254 | cur_state = false; |
1255 | } else { | |
1256 | reg = PIPECONF(cpu_transcoder); | |
1257 | val = I915_READ(reg); | |
1258 | cur_state = !!(val & PIPECONF_ENABLE); | |
1259 | } | |
1260 | ||
63d7bbe9 JB |
1261 | WARN(cur_state != state, |
1262 | "pipe %c assertion failure (expected %s, current %s)\n", | |
9db4a9c7 | 1263 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1264 | } |
1265 | ||
931872fc CW |
1266 | static void assert_plane(struct drm_i915_private *dev_priv, |
1267 | enum plane plane, bool state) | |
b24e7179 JB |
1268 | { |
1269 | int reg; | |
1270 | u32 val; | |
931872fc | 1271 | bool cur_state; |
b24e7179 JB |
1272 | |
1273 | reg = DSPCNTR(plane); | |
1274 | val = I915_READ(reg); | |
931872fc CW |
1275 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
1276 | WARN(cur_state != state, | |
1277 | "plane %c assertion failure (expected %s, current %s)\n", | |
1278 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1279 | } |
1280 | ||
931872fc CW |
1281 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1282 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1283 | ||
b24e7179 JB |
1284 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1285 | enum pipe pipe) | |
1286 | { | |
653e1026 | 1287 | struct drm_device *dev = dev_priv->dev; |
b24e7179 JB |
1288 | int reg, i; |
1289 | u32 val; | |
1290 | int cur_pipe; | |
1291 | ||
653e1026 VS |
1292 | /* Primary planes are fixed to pipes on gen4+ */ |
1293 | if (INTEL_INFO(dev)->gen >= 4) { | |
28c05794 AJ |
1294 | reg = DSPCNTR(pipe); |
1295 | val = I915_READ(reg); | |
83f26f16 | 1296 | WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1297 | "plane %c assertion failure, should be disabled but not\n", |
1298 | plane_name(pipe)); | |
19ec1358 | 1299 | return; |
28c05794 | 1300 | } |
19ec1358 | 1301 | |
b24e7179 | 1302 | /* Need to check both planes against the pipe */ |
08e2a7de | 1303 | for_each_pipe(i) { |
b24e7179 JB |
1304 | reg = DSPCNTR(i); |
1305 | val = I915_READ(reg); | |
1306 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1307 | DISPPLANE_SEL_PIPE_SHIFT; | |
1308 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, | |
9db4a9c7 JB |
1309 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1310 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1311 | } |
1312 | } | |
1313 | ||
19332d7a JB |
1314 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1315 | enum pipe pipe) | |
1316 | { | |
20674eef | 1317 | struct drm_device *dev = dev_priv->dev; |
1fe47785 | 1318 | int reg, sprite; |
19332d7a JB |
1319 | u32 val; |
1320 | ||
20674eef | 1321 | if (IS_VALLEYVIEW(dev)) { |
1fe47785 DL |
1322 | for_each_sprite(pipe, sprite) { |
1323 | reg = SPCNTR(pipe, sprite); | |
20674eef | 1324 | val = I915_READ(reg); |
83f26f16 | 1325 | WARN(val & SP_ENABLE, |
20674eef | 1326 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1327 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1328 | } |
1329 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
1330 | reg = SPRCTL(pipe); | |
19332d7a | 1331 | val = I915_READ(reg); |
83f26f16 | 1332 | WARN(val & SPRITE_ENABLE, |
06da8da2 | 1333 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1334 | plane_name(pipe), pipe_name(pipe)); |
1335 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
1336 | reg = DVSCNTR(pipe); | |
19332d7a | 1337 | val = I915_READ(reg); |
83f26f16 | 1338 | WARN(val & DVS_ENABLE, |
06da8da2 | 1339 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1340 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1341 | } |
1342 | } | |
1343 | ||
89eff4be | 1344 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
92f2584a JB |
1345 | { |
1346 | u32 val; | |
1347 | bool enabled; | |
1348 | ||
89eff4be | 1349 | WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
9d82aa17 | 1350 | |
92f2584a JB |
1351 | val = I915_READ(PCH_DREF_CONTROL); |
1352 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1353 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
1354 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); | |
1355 | } | |
1356 | ||
ab9412ba DV |
1357 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1358 | enum pipe pipe) | |
92f2584a JB |
1359 | { |
1360 | int reg; | |
1361 | u32 val; | |
1362 | bool enabled; | |
1363 | ||
ab9412ba | 1364 | reg = PCH_TRANSCONF(pipe); |
92f2584a JB |
1365 | val = I915_READ(reg); |
1366 | enabled = !!(val & TRANS_ENABLE); | |
9db4a9c7 JB |
1367 | WARN(enabled, |
1368 | "transcoder assertion failed, should be off on pipe %c but is still active\n", | |
1369 | pipe_name(pipe)); | |
92f2584a JB |
1370 | } |
1371 | ||
4e634389 KP |
1372 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1373 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1374 | { |
1375 | if ((val & DP_PORT_EN) == 0) | |
1376 | return false; | |
1377 | ||
1378 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1379 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1380 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1381 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1382 | return false; | |
44f37d1f CML |
1383 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1384 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) | |
1385 | return false; | |
f0575e92 KP |
1386 | } else { |
1387 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1388 | return false; | |
1389 | } | |
1390 | return true; | |
1391 | } | |
1392 | ||
1519b995 KP |
1393 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1394 | enum pipe pipe, u32 val) | |
1395 | { | |
dc0fa718 | 1396 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1397 | return false; |
1398 | ||
1399 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1400 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1401 | return false; |
44f37d1f CML |
1402 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1403 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) | |
1404 | return false; | |
1519b995 | 1405 | } else { |
dc0fa718 | 1406 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1407 | return false; |
1408 | } | |
1409 | return true; | |
1410 | } | |
1411 | ||
1412 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1413 | enum pipe pipe, u32 val) | |
1414 | { | |
1415 | if ((val & LVDS_PORT_EN) == 0) | |
1416 | return false; | |
1417 | ||
1418 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1419 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1420 | return false; | |
1421 | } else { | |
1422 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1423 | return false; | |
1424 | } | |
1425 | return true; | |
1426 | } | |
1427 | ||
1428 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1429 | enum pipe pipe, u32 val) | |
1430 | { | |
1431 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1432 | return false; | |
1433 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1434 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1435 | return false; | |
1436 | } else { | |
1437 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1438 | return false; | |
1439 | } | |
1440 | return true; | |
1441 | } | |
1442 | ||
291906f1 | 1443 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1444 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1445 | { |
47a05eca | 1446 | u32 val = I915_READ(reg); |
4e634389 | 1447 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1448 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1449 | reg, pipe_name(pipe)); |
de9a35ab | 1450 | |
75c5da27 DV |
1451 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
1452 | && (val & DP_PIPEB_SELECT), | |
de9a35ab | 1453 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1454 | } |
1455 | ||
1456 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1457 | enum pipe pipe, int reg) | |
1458 | { | |
47a05eca | 1459 | u32 val = I915_READ(reg); |
b70ad586 | 1460 | WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1461 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1462 | reg, pipe_name(pipe)); |
de9a35ab | 1463 | |
dc0fa718 | 1464 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1465 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1466 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1467 | } |
1468 | ||
1469 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1470 | enum pipe pipe) | |
1471 | { | |
1472 | int reg; | |
1473 | u32 val; | |
291906f1 | 1474 | |
f0575e92 KP |
1475 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1476 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1477 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1478 | |
1479 | reg = PCH_ADPA; | |
1480 | val = I915_READ(reg); | |
b70ad586 | 1481 | WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1482 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1483 | pipe_name(pipe)); |
291906f1 JB |
1484 | |
1485 | reg = PCH_LVDS; | |
1486 | val = I915_READ(reg); | |
b70ad586 | 1487 | WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1488 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1489 | pipe_name(pipe)); |
291906f1 | 1490 | |
e2debe91 PZ |
1491 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1492 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1493 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1494 | } |
1495 | ||
40e9cf64 JB |
1496 | static void intel_init_dpio(struct drm_device *dev) |
1497 | { | |
1498 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1499 | ||
1500 | if (!IS_VALLEYVIEW(dev)) | |
1501 | return; | |
1502 | ||
a09caddd CML |
1503 | /* |
1504 | * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C), | |
1505 | * CHV x1 PHY (DP/HDMI D) | |
1506 | * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C) | |
1507 | */ | |
1508 | if (IS_CHERRYVIEW(dev)) { | |
1509 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2; | |
1510 | DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO; | |
1511 | } else { | |
1512 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; | |
1513 | } | |
5382f5f3 JB |
1514 | } |
1515 | ||
426115cf | 1516 | static void vlv_enable_pll(struct intel_crtc *crtc) |
87442f73 | 1517 | { |
426115cf DV |
1518 | struct drm_device *dev = crtc->base.dev; |
1519 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1520 | int reg = DPLL(crtc->pipe); | |
1521 | u32 dpll = crtc->config.dpll_hw_state.dpll; | |
87442f73 | 1522 | |
426115cf | 1523 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 DV |
1524 | |
1525 | /* No really, not for ILK+ */ | |
1526 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); | |
1527 | ||
1528 | /* PLL is protected by panel, make sure we can write it */ | |
1529 | if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) | |
426115cf | 1530 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1531 | |
426115cf DV |
1532 | I915_WRITE(reg, dpll); |
1533 | POSTING_READ(reg); | |
1534 | udelay(150); | |
1535 | ||
1536 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1537 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1538 | ||
1539 | I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md); | |
1540 | POSTING_READ(DPLL_MD(crtc->pipe)); | |
87442f73 DV |
1541 | |
1542 | /* We do this three times for luck */ | |
426115cf | 1543 | I915_WRITE(reg, dpll); |
87442f73 DV |
1544 | POSTING_READ(reg); |
1545 | udelay(150); /* wait for warmup */ | |
426115cf | 1546 | I915_WRITE(reg, dpll); |
87442f73 DV |
1547 | POSTING_READ(reg); |
1548 | udelay(150); /* wait for warmup */ | |
426115cf | 1549 | I915_WRITE(reg, dpll); |
87442f73 DV |
1550 | POSTING_READ(reg); |
1551 | udelay(150); /* wait for warmup */ | |
1552 | } | |
1553 | ||
9d556c99 CML |
1554 | static void chv_enable_pll(struct intel_crtc *crtc) |
1555 | { | |
1556 | struct drm_device *dev = crtc->base.dev; | |
1557 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1558 | int pipe = crtc->pipe; | |
1559 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9d556c99 CML |
1560 | u32 tmp; |
1561 | ||
1562 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1563 | ||
1564 | BUG_ON(!IS_CHERRYVIEW(dev_priv->dev)); | |
1565 | ||
1566 | mutex_lock(&dev_priv->dpio_lock); | |
1567 | ||
1568 | /* Enable back the 10bit clock to display controller */ | |
1569 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1570 | tmp |= DPIO_DCLKP_EN; | |
1571 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1572 | ||
1573 | /* | |
1574 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1575 | */ | |
1576 | udelay(1); | |
1577 | ||
1578 | /* Enable PLL */ | |
a11b0703 | 1579 | I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll); |
9d556c99 CML |
1580 | |
1581 | /* Check PLL is locked */ | |
a11b0703 | 1582 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
9d556c99 CML |
1583 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
1584 | ||
a11b0703 VS |
1585 | /* not sure when this should be written */ |
1586 | I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md); | |
1587 | POSTING_READ(DPLL_MD(pipe)); | |
1588 | ||
9d556c99 CML |
1589 | mutex_unlock(&dev_priv->dpio_lock); |
1590 | } | |
1591 | ||
66e3d5c0 | 1592 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1593 | { |
66e3d5c0 DV |
1594 | struct drm_device *dev = crtc->base.dev; |
1595 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1596 | int reg = DPLL(crtc->pipe); | |
1597 | u32 dpll = crtc->config.dpll_hw_state.dpll; | |
63d7bbe9 | 1598 | |
66e3d5c0 | 1599 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1600 | |
63d7bbe9 | 1601 | /* No really, not for ILK+ */ |
3d13ef2e | 1602 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1603 | |
1604 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1605 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1606 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1607 | |
66e3d5c0 DV |
1608 | I915_WRITE(reg, dpll); |
1609 | ||
1610 | /* Wait for the clocks to stabilize. */ | |
1611 | POSTING_READ(reg); | |
1612 | udelay(150); | |
1613 | ||
1614 | if (INTEL_INFO(dev)->gen >= 4) { | |
1615 | I915_WRITE(DPLL_MD(crtc->pipe), | |
1616 | crtc->config.dpll_hw_state.dpll_md); | |
1617 | } else { | |
1618 | /* The pixel multiplier can only be updated once the | |
1619 | * DPLL is enabled and the clocks are stable. | |
1620 | * | |
1621 | * So write it again. | |
1622 | */ | |
1623 | I915_WRITE(reg, dpll); | |
1624 | } | |
63d7bbe9 JB |
1625 | |
1626 | /* We do this three times for luck */ | |
66e3d5c0 | 1627 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1628 | POSTING_READ(reg); |
1629 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1630 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1631 | POSTING_READ(reg); |
1632 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1633 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1634 | POSTING_READ(reg); |
1635 | udelay(150); /* wait for warmup */ | |
1636 | } | |
1637 | ||
1638 | /** | |
50b44a44 | 1639 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1640 | * @dev_priv: i915 private structure |
1641 | * @pipe: pipe PLL to disable | |
1642 | * | |
1643 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1644 | * | |
1645 | * Note! This is for pre-ILK only. | |
1646 | */ | |
50b44a44 | 1647 | static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
63d7bbe9 | 1648 | { |
63d7bbe9 JB |
1649 | /* Don't disable pipe A or pipe A PLLs if needed */ |
1650 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1651 | return; | |
1652 | ||
1653 | /* Make sure the pipe isn't still relying on us */ | |
1654 | assert_pipe_disabled(dev_priv, pipe); | |
1655 | ||
50b44a44 DV |
1656 | I915_WRITE(DPLL(pipe), 0); |
1657 | POSTING_READ(DPLL(pipe)); | |
63d7bbe9 JB |
1658 | } |
1659 | ||
f6071166 JB |
1660 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1661 | { | |
1662 | u32 val = 0; | |
1663 | ||
1664 | /* Make sure the pipe isn't still relying on us */ | |
1665 | assert_pipe_disabled(dev_priv, pipe); | |
1666 | ||
e5cbfbfb ID |
1667 | /* |
1668 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1669 | * The latter is needed for VGA hotplug / manual detection. | |
1670 | */ | |
f6071166 | 1671 | if (pipe == PIPE_B) |
e5cbfbfb | 1672 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV; |
f6071166 JB |
1673 | I915_WRITE(DPLL(pipe), val); |
1674 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1675 | |
1676 | } | |
1677 | ||
1678 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1679 | { | |
d752048d | 1680 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1681 | u32 val; |
1682 | ||
a11b0703 VS |
1683 | /* Make sure the pipe isn't still relying on us */ |
1684 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1685 | |
a11b0703 | 1686 | /* Set PLL en = 0 */ |
d17ec4ce | 1687 | val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV; |
a11b0703 VS |
1688 | if (pipe != PIPE_A) |
1689 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1690 | I915_WRITE(DPLL(pipe), val); | |
1691 | POSTING_READ(DPLL(pipe)); | |
d752048d VS |
1692 | |
1693 | mutex_lock(&dev_priv->dpio_lock); | |
1694 | ||
1695 | /* Disable 10bit clock to display controller */ | |
1696 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1697 | val &= ~DPIO_DCLKP_EN; | |
1698 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1699 | ||
61407f6d VS |
1700 | /* disable left/right clock distribution */ |
1701 | if (pipe != PIPE_B) { | |
1702 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); | |
1703 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); | |
1704 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); | |
1705 | } else { | |
1706 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); | |
1707 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); | |
1708 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); | |
1709 | } | |
1710 | ||
d752048d | 1711 | mutex_unlock(&dev_priv->dpio_lock); |
f6071166 JB |
1712 | } |
1713 | ||
e4607fcf CML |
1714 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
1715 | struct intel_digital_port *dport) | |
89b667f8 JB |
1716 | { |
1717 | u32 port_mask; | |
00fc31b7 | 1718 | int dpll_reg; |
89b667f8 | 1719 | |
e4607fcf CML |
1720 | switch (dport->port) { |
1721 | case PORT_B: | |
89b667f8 | 1722 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1723 | dpll_reg = DPLL(0); |
e4607fcf CML |
1724 | break; |
1725 | case PORT_C: | |
89b667f8 | 1726 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 CML |
1727 | dpll_reg = DPLL(0); |
1728 | break; | |
1729 | case PORT_D: | |
1730 | port_mask = DPLL_PORTD_READY_MASK; | |
1731 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1732 | break; |
1733 | default: | |
1734 | BUG(); | |
1735 | } | |
89b667f8 | 1736 | |
00fc31b7 | 1737 | if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000)) |
89b667f8 | 1738 | WARN(1, "timed out waiting for port %c ready: 0x%08x\n", |
00fc31b7 | 1739 | port_name(dport->port), I915_READ(dpll_reg)); |
89b667f8 JB |
1740 | } |
1741 | ||
b14b1055 DV |
1742 | static void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
1743 | { | |
1744 | struct drm_device *dev = crtc->base.dev; | |
1745 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1746 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
1747 | ||
be19f0ff CW |
1748 | if (WARN_ON(pll == NULL)) |
1749 | return; | |
1750 | ||
b14b1055 DV |
1751 | WARN_ON(!pll->refcount); |
1752 | if (pll->active == 0) { | |
1753 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); | |
1754 | WARN_ON(pll->on); | |
1755 | assert_shared_dpll_disabled(dev_priv, pll); | |
1756 | ||
1757 | pll->mode_set(dev_priv, pll); | |
1758 | } | |
1759 | } | |
1760 | ||
92f2584a | 1761 | /** |
85b3894f | 1762 | * intel_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1763 | * @dev_priv: i915 private structure |
1764 | * @pipe: pipe PLL to enable | |
1765 | * | |
1766 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1767 | * drives the transcoder clock. | |
1768 | */ | |
85b3894f | 1769 | static void intel_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1770 | { |
3d13ef2e DL |
1771 | struct drm_device *dev = crtc->base.dev; |
1772 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1773 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
92f2584a | 1774 | |
87a875bb | 1775 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1776 | return; |
1777 | ||
1778 | if (WARN_ON(pll->refcount == 0)) | |
1779 | return; | |
ee7b9f93 | 1780 | |
74dd6928 | 1781 | DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n", |
46edb027 | 1782 | pll->name, pll->active, pll->on, |
e2b78267 | 1783 | crtc->base.base.id); |
92f2584a | 1784 | |
cdbd2316 DV |
1785 | if (pll->active++) { |
1786 | WARN_ON(!pll->on); | |
e9d6944e | 1787 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1788 | return; |
1789 | } | |
f4a091c7 | 1790 | WARN_ON(pll->on); |
ee7b9f93 | 1791 | |
bd2bb1b9 PZ |
1792 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
1793 | ||
46edb027 | 1794 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1795 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1796 | pll->on = true; |
92f2584a JB |
1797 | } |
1798 | ||
716c2e55 | 1799 | void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1800 | { |
3d13ef2e DL |
1801 | struct drm_device *dev = crtc->base.dev; |
1802 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1803 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
4c609cb8 | 1804 | |
92f2584a | 1805 | /* PCH only available on ILK+ */ |
3d13ef2e | 1806 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
87a875bb | 1807 | if (WARN_ON(pll == NULL)) |
ee7b9f93 | 1808 | return; |
92f2584a | 1809 | |
48da64a8 CW |
1810 | if (WARN_ON(pll->refcount == 0)) |
1811 | return; | |
7a419866 | 1812 | |
46edb027 DV |
1813 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1814 | pll->name, pll->active, pll->on, | |
e2b78267 | 1815 | crtc->base.base.id); |
7a419866 | 1816 | |
48da64a8 | 1817 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1818 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1819 | return; |
1820 | } | |
1821 | ||
e9d6944e | 1822 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1823 | WARN_ON(!pll->on); |
cdbd2316 | 1824 | if (--pll->active) |
7a419866 | 1825 | return; |
ee7b9f93 | 1826 | |
46edb027 | 1827 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1828 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1829 | pll->on = false; |
bd2bb1b9 PZ |
1830 | |
1831 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
92f2584a JB |
1832 | } |
1833 | ||
b8a4f404 PZ |
1834 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1835 | enum pipe pipe) | |
040484af | 1836 | { |
23670b32 | 1837 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1838 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1839 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
23670b32 | 1840 | uint32_t reg, val, pipeconf_val; |
040484af JB |
1841 | |
1842 | /* PCH only available on ILK+ */ | |
3d13ef2e | 1843 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
040484af JB |
1844 | |
1845 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1846 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1847 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1848 | |
1849 | /* FDI must be feeding us bits for PCH ports */ | |
1850 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1851 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1852 | ||
23670b32 DV |
1853 | if (HAS_PCH_CPT(dev)) { |
1854 | /* Workaround: Set the timing override bit before enabling the | |
1855 | * pch transcoder. */ | |
1856 | reg = TRANS_CHICKEN2(pipe); | |
1857 | val = I915_READ(reg); | |
1858 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1859 | I915_WRITE(reg, val); | |
59c859d6 | 1860 | } |
23670b32 | 1861 | |
ab9412ba | 1862 | reg = PCH_TRANSCONF(pipe); |
040484af | 1863 | val = I915_READ(reg); |
5f7f726d | 1864 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1865 | |
1866 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1867 | /* | |
1868 | * make the BPC in transcoder be consistent with | |
1869 | * that in pipeconf reg. | |
1870 | */ | |
dfd07d72 DV |
1871 | val &= ~PIPECONF_BPC_MASK; |
1872 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1873 | } |
5f7f726d PZ |
1874 | |
1875 | val &= ~TRANS_INTERLACE_MASK; | |
1876 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 PZ |
1877 | if (HAS_PCH_IBX(dev_priv->dev) && |
1878 | intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) | |
1879 | val |= TRANS_LEGACY_INTERLACED_ILK; | |
1880 | else | |
1881 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1882 | else |
1883 | val |= TRANS_PROGRESSIVE; | |
1884 | ||
040484af JB |
1885 | I915_WRITE(reg, val | TRANS_ENABLE); |
1886 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 1887 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1888 | } |
1889 | ||
8fb033d7 | 1890 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1891 | enum transcoder cpu_transcoder) |
040484af | 1892 | { |
8fb033d7 | 1893 | u32 val, pipeconf_val; |
8fb033d7 PZ |
1894 | |
1895 | /* PCH only available on ILK+ */ | |
3d13ef2e | 1896 | BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5); |
8fb033d7 | 1897 | |
8fb033d7 | 1898 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1899 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1900 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1901 | |
223a6fdf PZ |
1902 | /* Workaround: set timing override bit. */ |
1903 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1904 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf PZ |
1905 | I915_WRITE(_TRANSA_CHICKEN2, val); |
1906 | ||
25f3ef11 | 1907 | val = TRANS_ENABLE; |
937bb610 | 1908 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1909 | |
9a76b1c6 PZ |
1910 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1911 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1912 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1913 | else |
1914 | val |= TRANS_PROGRESSIVE; | |
1915 | ||
ab9412ba DV |
1916 | I915_WRITE(LPT_TRANSCONF, val); |
1917 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 1918 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1919 | } |
1920 | ||
b8a4f404 PZ |
1921 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1922 | enum pipe pipe) | |
040484af | 1923 | { |
23670b32 DV |
1924 | struct drm_device *dev = dev_priv->dev; |
1925 | uint32_t reg, val; | |
040484af JB |
1926 | |
1927 | /* FDI relies on the transcoder */ | |
1928 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1929 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1930 | ||
291906f1 JB |
1931 | /* Ports must be off as well */ |
1932 | assert_pch_ports_disabled(dev_priv, pipe); | |
1933 | ||
ab9412ba | 1934 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1935 | val = I915_READ(reg); |
1936 | val &= ~TRANS_ENABLE; | |
1937 | I915_WRITE(reg, val); | |
1938 | /* wait for PCH transcoder off, transcoder state */ | |
1939 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 1940 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 DV |
1941 | |
1942 | if (!HAS_PCH_IBX(dev)) { | |
1943 | /* Workaround: Clear the timing override chicken bit again. */ | |
1944 | reg = TRANS_CHICKEN2(pipe); | |
1945 | val = I915_READ(reg); | |
1946 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1947 | I915_WRITE(reg, val); | |
1948 | } | |
040484af JB |
1949 | } |
1950 | ||
ab4d966c | 1951 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1952 | { |
8fb033d7 PZ |
1953 | u32 val; |
1954 | ||
ab9412ba | 1955 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1956 | val &= ~TRANS_ENABLE; |
ab9412ba | 1957 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1958 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 1959 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 1960 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1961 | |
1962 | /* Workaround: clear timing override bit. */ | |
1963 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1964 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf | 1965 | I915_WRITE(_TRANSA_CHICKEN2, val); |
040484af JB |
1966 | } |
1967 | ||
b24e7179 | 1968 | /** |
309cfea8 | 1969 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 1970 | * @crtc: crtc responsible for the pipe |
b24e7179 | 1971 | * |
0372264a | 1972 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 1973 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 1974 | */ |
e1fdc473 | 1975 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 1976 | { |
0372264a PZ |
1977 | struct drm_device *dev = crtc->base.dev; |
1978 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1979 | enum pipe pipe = crtc->pipe; | |
702e7a56 PZ |
1980 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1981 | pipe); | |
1a240d4d | 1982 | enum pipe pch_transcoder; |
b24e7179 JB |
1983 | int reg; |
1984 | u32 val; | |
1985 | ||
58c6eaa2 | 1986 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 1987 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
1988 | assert_sprites_disabled(dev_priv, pipe); |
1989 | ||
681e5811 | 1990 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
1991 | pch_transcoder = TRANSCODER_A; |
1992 | else | |
1993 | pch_transcoder = pipe; | |
1994 | ||
b24e7179 JB |
1995 | /* |
1996 | * A pipe without a PLL won't actually be able to drive bits from | |
1997 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1998 | * need the check. | |
1999 | */ | |
2000 | if (!HAS_PCH_SPLIT(dev_priv->dev)) | |
fbf3218a | 2001 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
2002 | assert_dsi_pll_enabled(dev_priv); |
2003 | else | |
2004 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 2005 | else { |
30421c4f | 2006 | if (crtc->config.has_pch_encoder) { |
040484af | 2007 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 2008 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
2009 | assert_fdi_tx_pll_enabled(dev_priv, |
2010 | (enum pipe) cpu_transcoder); | |
040484af JB |
2011 | } |
2012 | /* FIXME: assert CPU port conditions for SNB+ */ | |
2013 | } | |
b24e7179 | 2014 | |
702e7a56 | 2015 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2016 | val = I915_READ(reg); |
7ad25d48 PZ |
2017 | if (val & PIPECONF_ENABLE) { |
2018 | WARN_ON(!(pipe == PIPE_A && | |
2019 | dev_priv->quirks & QUIRK_PIPEA_FORCE)); | |
00d70b15 | 2020 | return; |
7ad25d48 | 2021 | } |
00d70b15 CW |
2022 | |
2023 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 2024 | POSTING_READ(reg); |
b24e7179 JB |
2025 | } |
2026 | ||
2027 | /** | |
309cfea8 | 2028 | * intel_disable_pipe - disable a pipe, asserting requirements |
b24e7179 JB |
2029 | * @dev_priv: i915 private structure |
2030 | * @pipe: pipe to disable | |
2031 | * | |
2032 | * Disable @pipe, making sure that various hardware specific requirements | |
2033 | * are met, if applicable, e.g. plane disabled, panel fitter off, etc. | |
2034 | * | |
2035 | * @pipe should be %PIPE_A or %PIPE_B. | |
2036 | * | |
2037 | * Will wait until the pipe has shut down before returning. | |
2038 | */ | |
2039 | static void intel_disable_pipe(struct drm_i915_private *dev_priv, | |
2040 | enum pipe pipe) | |
2041 | { | |
702e7a56 PZ |
2042 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
2043 | pipe); | |
b24e7179 JB |
2044 | int reg; |
2045 | u32 val; | |
2046 | ||
2047 | /* | |
2048 | * Make sure planes won't keep trying to pump pixels to us, | |
2049 | * or we might hang the display. | |
2050 | */ | |
2051 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2052 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2053 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 JB |
2054 | |
2055 | /* Don't disable pipe A or pipe A PLLs if needed */ | |
2056 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
2057 | return; | |
2058 | ||
702e7a56 | 2059 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2060 | val = I915_READ(reg); |
00d70b15 CW |
2061 | if ((val & PIPECONF_ENABLE) == 0) |
2062 | return; | |
2063 | ||
2064 | I915_WRITE(reg, val & ~PIPECONF_ENABLE); | |
b24e7179 JB |
2065 | intel_wait_for_pipe_off(dev_priv->dev, pipe); |
2066 | } | |
2067 | ||
d74362c9 KP |
2068 | /* |
2069 | * Plane regs are double buffered, going from enabled->disabled needs a | |
2070 | * trigger in order to latch. The display address reg provides this. | |
2071 | */ | |
1dba99f4 VS |
2072 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
2073 | enum plane plane) | |
d74362c9 | 2074 | { |
3d13ef2e DL |
2075 | struct drm_device *dev = dev_priv->dev; |
2076 | u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane); | |
1dba99f4 VS |
2077 | |
2078 | I915_WRITE(reg, I915_READ(reg)); | |
2079 | POSTING_READ(reg); | |
d74362c9 KP |
2080 | } |
2081 | ||
b24e7179 | 2082 | /** |
262ca2b0 | 2083 | * intel_enable_primary_hw_plane - enable the primary plane on a given pipe |
b24e7179 JB |
2084 | * @dev_priv: i915 private structure |
2085 | * @plane: plane to enable | |
2086 | * @pipe: pipe being fed | |
2087 | * | |
2088 | * Enable @plane on @pipe, making sure that @pipe is running first. | |
2089 | */ | |
262ca2b0 MR |
2090 | static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv, |
2091 | enum plane plane, enum pipe pipe) | |
b24e7179 | 2092 | { |
33c3b0d1 | 2093 | struct drm_device *dev = dev_priv->dev; |
939c2fe8 VS |
2094 | struct intel_crtc *intel_crtc = |
2095 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
b24e7179 JB |
2096 | int reg; |
2097 | u32 val; | |
2098 | ||
2099 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
2100 | assert_pipe_enabled(dev_priv, pipe); | |
2101 | ||
98ec7739 VS |
2102 | if (intel_crtc->primary_enabled) |
2103 | return; | |
0037f71c | 2104 | |
4c445e0e | 2105 | intel_crtc->primary_enabled = true; |
939c2fe8 | 2106 | |
b24e7179 JB |
2107 | reg = DSPCNTR(plane); |
2108 | val = I915_READ(reg); | |
10efa932 | 2109 | WARN_ON(val & DISPLAY_PLANE_ENABLE); |
00d70b15 CW |
2110 | |
2111 | I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); | |
1dba99f4 | 2112 | intel_flush_primary_plane(dev_priv, plane); |
33c3b0d1 VS |
2113 | |
2114 | /* | |
2115 | * BDW signals flip done immediately if the plane | |
2116 | * is disabled, even if the plane enable is already | |
2117 | * armed to occur at the next vblank :( | |
2118 | */ | |
2119 | if (IS_BROADWELL(dev)) | |
2120 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
b24e7179 JB |
2121 | } |
2122 | ||
b24e7179 | 2123 | /** |
262ca2b0 | 2124 | * intel_disable_primary_hw_plane - disable the primary hardware plane |
b24e7179 JB |
2125 | * @dev_priv: i915 private structure |
2126 | * @plane: plane to disable | |
2127 | * @pipe: pipe consuming the data | |
2128 | * | |
2129 | * Disable @plane; should be an independent operation. | |
2130 | */ | |
262ca2b0 MR |
2131 | static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv, |
2132 | enum plane plane, enum pipe pipe) | |
b24e7179 | 2133 | { |
939c2fe8 VS |
2134 | struct intel_crtc *intel_crtc = |
2135 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
b24e7179 JB |
2136 | int reg; |
2137 | u32 val; | |
2138 | ||
98ec7739 VS |
2139 | if (!intel_crtc->primary_enabled) |
2140 | return; | |
0037f71c | 2141 | |
4c445e0e | 2142 | intel_crtc->primary_enabled = false; |
939c2fe8 | 2143 | |
b24e7179 JB |
2144 | reg = DSPCNTR(plane); |
2145 | val = I915_READ(reg); | |
10efa932 | 2146 | WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0); |
00d70b15 CW |
2147 | |
2148 | I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); | |
1dba99f4 | 2149 | intel_flush_primary_plane(dev_priv, plane); |
b24e7179 JB |
2150 | } |
2151 | ||
693db184 CW |
2152 | static bool need_vtd_wa(struct drm_device *dev) |
2153 | { | |
2154 | #ifdef CONFIG_INTEL_IOMMU | |
2155 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2156 | return true; | |
2157 | #endif | |
2158 | return false; | |
2159 | } | |
2160 | ||
a57ce0b2 JB |
2161 | static int intel_align_height(struct drm_device *dev, int height, bool tiled) |
2162 | { | |
2163 | int tile_height; | |
2164 | ||
2165 | tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1; | |
2166 | return ALIGN(height, tile_height); | |
2167 | } | |
2168 | ||
127bd2ac | 2169 | int |
48b956c5 | 2170 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
05394f39 | 2171 | struct drm_i915_gem_object *obj, |
a4872ba6 | 2172 | struct intel_engine_cs *pipelined) |
6b95a207 | 2173 | { |
ce453d81 | 2174 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
2175 | u32 alignment; |
2176 | int ret; | |
2177 | ||
ebcdd39e MR |
2178 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2179 | ||
05394f39 | 2180 | switch (obj->tiling_mode) { |
6b95a207 | 2181 | case I915_TILING_NONE: |
534843da CW |
2182 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
2183 | alignment = 128 * 1024; | |
a6c45cf0 | 2184 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
2185 | alignment = 4 * 1024; |
2186 | else | |
2187 | alignment = 64 * 1024; | |
6b95a207 KH |
2188 | break; |
2189 | case I915_TILING_X: | |
2190 | /* pin() will align the object as required by fence */ | |
2191 | alignment = 0; | |
2192 | break; | |
2193 | case I915_TILING_Y: | |
80075d49 | 2194 | WARN(1, "Y tiled bo slipped through, driver bug!\n"); |
6b95a207 KH |
2195 | return -EINVAL; |
2196 | default: | |
2197 | BUG(); | |
2198 | } | |
2199 | ||
693db184 CW |
2200 | /* Note that the w/a also requires 64 PTE of padding following the |
2201 | * bo. We currently fill all unused PTE with the shadow page and so | |
2202 | * we should always have valid PTE following the scanout preventing | |
2203 | * the VT-d warning. | |
2204 | */ | |
2205 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2206 | alignment = 256 * 1024; | |
2207 | ||
ce453d81 | 2208 | dev_priv->mm.interruptible = false; |
2da3b9b9 | 2209 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
48b956c5 | 2210 | if (ret) |
ce453d81 | 2211 | goto err_interruptible; |
6b95a207 KH |
2212 | |
2213 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2214 | * fence, whereas 965+ only requires a fence if using | |
2215 | * framebuffer compression. For simplicity, we always install | |
2216 | * a fence as the cost is not that onerous. | |
2217 | */ | |
06d98131 | 2218 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
2219 | if (ret) |
2220 | goto err_unpin; | |
1690e1eb | 2221 | |
9a5a53b3 | 2222 | i915_gem_object_pin_fence(obj); |
6b95a207 | 2223 | |
ce453d81 | 2224 | dev_priv->mm.interruptible = true; |
6b95a207 | 2225 | return 0; |
48b956c5 CW |
2226 | |
2227 | err_unpin: | |
cc98b413 | 2228 | i915_gem_object_unpin_from_display_plane(obj); |
ce453d81 CW |
2229 | err_interruptible: |
2230 | dev_priv->mm.interruptible = true; | |
48b956c5 | 2231 | return ret; |
6b95a207 KH |
2232 | } |
2233 | ||
1690e1eb CW |
2234 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
2235 | { | |
ebcdd39e MR |
2236 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2237 | ||
1690e1eb | 2238 | i915_gem_object_unpin_fence(obj); |
cc98b413 | 2239 | i915_gem_object_unpin_from_display_plane(obj); |
1690e1eb CW |
2240 | } |
2241 | ||
c2c75131 DV |
2242 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2243 | * is assumed to be a power-of-two. */ | |
bc752862 CW |
2244 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
2245 | unsigned int tiling_mode, | |
2246 | unsigned int cpp, | |
2247 | unsigned int pitch) | |
c2c75131 | 2248 | { |
bc752862 CW |
2249 | if (tiling_mode != I915_TILING_NONE) { |
2250 | unsigned int tile_rows, tiles; | |
c2c75131 | 2251 | |
bc752862 CW |
2252 | tile_rows = *y / 8; |
2253 | *y %= 8; | |
c2c75131 | 2254 | |
bc752862 CW |
2255 | tiles = *x / (512/cpp); |
2256 | *x %= 512/cpp; | |
2257 | ||
2258 | return tile_rows * pitch * 8 + tiles * 4096; | |
2259 | } else { | |
2260 | unsigned int offset; | |
2261 | ||
2262 | offset = *y * pitch + *x * cpp; | |
2263 | *y = 0; | |
2264 | *x = (offset & 4095) / cpp; | |
2265 | return offset & -4096; | |
2266 | } | |
c2c75131 DV |
2267 | } |
2268 | ||
46f297fb JB |
2269 | int intel_format_to_fourcc(int format) |
2270 | { | |
2271 | switch (format) { | |
2272 | case DISPPLANE_8BPP: | |
2273 | return DRM_FORMAT_C8; | |
2274 | case DISPPLANE_BGRX555: | |
2275 | return DRM_FORMAT_XRGB1555; | |
2276 | case DISPPLANE_BGRX565: | |
2277 | return DRM_FORMAT_RGB565; | |
2278 | default: | |
2279 | case DISPPLANE_BGRX888: | |
2280 | return DRM_FORMAT_XRGB8888; | |
2281 | case DISPPLANE_RGBX888: | |
2282 | return DRM_FORMAT_XBGR8888; | |
2283 | case DISPPLANE_BGRX101010: | |
2284 | return DRM_FORMAT_XRGB2101010; | |
2285 | case DISPPLANE_RGBX101010: | |
2286 | return DRM_FORMAT_XBGR2101010; | |
2287 | } | |
2288 | } | |
2289 | ||
484b41dd | 2290 | static bool intel_alloc_plane_obj(struct intel_crtc *crtc, |
46f297fb JB |
2291 | struct intel_plane_config *plane_config) |
2292 | { | |
2293 | struct drm_device *dev = crtc->base.dev; | |
2294 | struct drm_i915_gem_object *obj = NULL; | |
2295 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2296 | u32 base = plane_config->base; | |
2297 | ||
ff2652ea CW |
2298 | if (plane_config->size == 0) |
2299 | return false; | |
2300 | ||
46f297fb JB |
2301 | obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base, |
2302 | plane_config->size); | |
2303 | if (!obj) | |
484b41dd | 2304 | return false; |
46f297fb JB |
2305 | |
2306 | if (plane_config->tiled) { | |
2307 | obj->tiling_mode = I915_TILING_X; | |
66e514c1 | 2308 | obj->stride = crtc->base.primary->fb->pitches[0]; |
46f297fb JB |
2309 | } |
2310 | ||
66e514c1 DA |
2311 | mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format; |
2312 | mode_cmd.width = crtc->base.primary->fb->width; | |
2313 | mode_cmd.height = crtc->base.primary->fb->height; | |
2314 | mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0]; | |
46f297fb JB |
2315 | |
2316 | mutex_lock(&dev->struct_mutex); | |
2317 | ||
66e514c1 | 2318 | if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb), |
484b41dd | 2319 | &mode_cmd, obj)) { |
46f297fb JB |
2320 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2321 | goto out_unref_obj; | |
2322 | } | |
2323 | ||
a071fa00 | 2324 | obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe); |
46f297fb | 2325 | mutex_unlock(&dev->struct_mutex); |
484b41dd JB |
2326 | |
2327 | DRM_DEBUG_KMS("plane fb obj %p\n", obj); | |
2328 | return true; | |
46f297fb JB |
2329 | |
2330 | out_unref_obj: | |
2331 | drm_gem_object_unreference(&obj->base); | |
2332 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2333 | return false; |
2334 | } | |
2335 | ||
2336 | static void intel_find_plane_obj(struct intel_crtc *intel_crtc, | |
2337 | struct intel_plane_config *plane_config) | |
2338 | { | |
2339 | struct drm_device *dev = intel_crtc->base.dev; | |
2340 | struct drm_crtc *c; | |
2341 | struct intel_crtc *i; | |
2ff8fde1 | 2342 | struct drm_i915_gem_object *obj; |
484b41dd | 2343 | |
66e514c1 | 2344 | if (!intel_crtc->base.primary->fb) |
484b41dd JB |
2345 | return; |
2346 | ||
2347 | if (intel_alloc_plane_obj(intel_crtc, plane_config)) | |
2348 | return; | |
2349 | ||
66e514c1 DA |
2350 | kfree(intel_crtc->base.primary->fb); |
2351 | intel_crtc->base.primary->fb = NULL; | |
484b41dd JB |
2352 | |
2353 | /* | |
2354 | * Failed to alloc the obj, check to see if we should share | |
2355 | * an fb with another CRTC instead | |
2356 | */ | |
70e1e0ec | 2357 | for_each_crtc(dev, c) { |
484b41dd JB |
2358 | i = to_intel_crtc(c); |
2359 | ||
2360 | if (c == &intel_crtc->base) | |
2361 | continue; | |
2362 | ||
2ff8fde1 MR |
2363 | if (!i->active) |
2364 | continue; | |
2365 | ||
2366 | obj = intel_fb_obj(c->primary->fb); | |
2367 | if (obj == NULL) | |
484b41dd JB |
2368 | continue; |
2369 | ||
2ff8fde1 | 2370 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
66e514c1 DA |
2371 | drm_framebuffer_reference(c->primary->fb); |
2372 | intel_crtc->base.primary->fb = c->primary->fb; | |
2ff8fde1 | 2373 | obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe); |
484b41dd JB |
2374 | break; |
2375 | } | |
2376 | } | |
46f297fb JB |
2377 | } |
2378 | ||
29b9bde6 DV |
2379 | static void i9xx_update_primary_plane(struct drm_crtc *crtc, |
2380 | struct drm_framebuffer *fb, | |
2381 | int x, int y) | |
81255565 JB |
2382 | { |
2383 | struct drm_device *dev = crtc->dev; | |
2384 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2385 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2ff8fde1 | 2386 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
81255565 | 2387 | int plane = intel_crtc->plane; |
e506a0c6 | 2388 | unsigned long linear_offset; |
81255565 | 2389 | u32 dspcntr; |
5eddb70b | 2390 | u32 reg; |
81255565 | 2391 | |
5eddb70b CW |
2392 | reg = DSPCNTR(plane); |
2393 | dspcntr = I915_READ(reg); | |
81255565 JB |
2394 | /* Mask out pixel format bits in case we change it */ |
2395 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
57779d06 VS |
2396 | switch (fb->pixel_format) { |
2397 | case DRM_FORMAT_C8: | |
81255565 JB |
2398 | dspcntr |= DISPPLANE_8BPP; |
2399 | break; | |
57779d06 VS |
2400 | case DRM_FORMAT_XRGB1555: |
2401 | case DRM_FORMAT_ARGB1555: | |
2402 | dspcntr |= DISPPLANE_BGRX555; | |
81255565 | 2403 | break; |
57779d06 VS |
2404 | case DRM_FORMAT_RGB565: |
2405 | dspcntr |= DISPPLANE_BGRX565; | |
2406 | break; | |
2407 | case DRM_FORMAT_XRGB8888: | |
2408 | case DRM_FORMAT_ARGB8888: | |
2409 | dspcntr |= DISPPLANE_BGRX888; | |
2410 | break; | |
2411 | case DRM_FORMAT_XBGR8888: | |
2412 | case DRM_FORMAT_ABGR8888: | |
2413 | dspcntr |= DISPPLANE_RGBX888; | |
2414 | break; | |
2415 | case DRM_FORMAT_XRGB2101010: | |
2416 | case DRM_FORMAT_ARGB2101010: | |
2417 | dspcntr |= DISPPLANE_BGRX101010; | |
2418 | break; | |
2419 | case DRM_FORMAT_XBGR2101010: | |
2420 | case DRM_FORMAT_ABGR2101010: | |
2421 | dspcntr |= DISPPLANE_RGBX101010; | |
81255565 JB |
2422 | break; |
2423 | default: | |
baba133a | 2424 | BUG(); |
81255565 | 2425 | } |
57779d06 | 2426 | |
a6c45cf0 | 2427 | if (INTEL_INFO(dev)->gen >= 4) { |
05394f39 | 2428 | if (obj->tiling_mode != I915_TILING_NONE) |
81255565 JB |
2429 | dspcntr |= DISPPLANE_TILED; |
2430 | else | |
2431 | dspcntr &= ~DISPPLANE_TILED; | |
2432 | } | |
2433 | ||
de1aa629 VS |
2434 | if (IS_G4X(dev)) |
2435 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2436 | ||
5eddb70b | 2437 | I915_WRITE(reg, dspcntr); |
81255565 | 2438 | |
e506a0c6 | 2439 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
81255565 | 2440 | |
c2c75131 DV |
2441 | if (INTEL_INFO(dev)->gen >= 4) { |
2442 | intel_crtc->dspaddr_offset = | |
bc752862 CW |
2443 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2444 | fb->bits_per_pixel / 8, | |
2445 | fb->pitches[0]); | |
c2c75131 DV |
2446 | linear_offset -= intel_crtc->dspaddr_offset; |
2447 | } else { | |
e506a0c6 | 2448 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2449 | } |
e506a0c6 | 2450 | |
f343c5f6 BW |
2451 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2452 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, | |
2453 | fb->pitches[0]); | |
01f2c773 | 2454 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2455 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2456 | I915_WRITE(DSPSURF(plane), |
2457 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2458 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2459 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2460 | } else |
f343c5f6 | 2461 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2462 | POSTING_READ(reg); |
17638cd6 JB |
2463 | } |
2464 | ||
29b9bde6 DV |
2465 | static void ironlake_update_primary_plane(struct drm_crtc *crtc, |
2466 | struct drm_framebuffer *fb, | |
2467 | int x, int y) | |
17638cd6 JB |
2468 | { |
2469 | struct drm_device *dev = crtc->dev; | |
2470 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2471 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2ff8fde1 | 2472 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
17638cd6 | 2473 | int plane = intel_crtc->plane; |
e506a0c6 | 2474 | unsigned long linear_offset; |
17638cd6 JB |
2475 | u32 dspcntr; |
2476 | u32 reg; | |
2477 | ||
17638cd6 JB |
2478 | reg = DSPCNTR(plane); |
2479 | dspcntr = I915_READ(reg); | |
2480 | /* Mask out pixel format bits in case we change it */ | |
2481 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
57779d06 VS |
2482 | switch (fb->pixel_format) { |
2483 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2484 | dspcntr |= DISPPLANE_8BPP; |
2485 | break; | |
57779d06 VS |
2486 | case DRM_FORMAT_RGB565: |
2487 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2488 | break; |
57779d06 VS |
2489 | case DRM_FORMAT_XRGB8888: |
2490 | case DRM_FORMAT_ARGB8888: | |
2491 | dspcntr |= DISPPLANE_BGRX888; | |
2492 | break; | |
2493 | case DRM_FORMAT_XBGR8888: | |
2494 | case DRM_FORMAT_ABGR8888: | |
2495 | dspcntr |= DISPPLANE_RGBX888; | |
2496 | break; | |
2497 | case DRM_FORMAT_XRGB2101010: | |
2498 | case DRM_FORMAT_ARGB2101010: | |
2499 | dspcntr |= DISPPLANE_BGRX101010; | |
2500 | break; | |
2501 | case DRM_FORMAT_XBGR2101010: | |
2502 | case DRM_FORMAT_ABGR2101010: | |
2503 | dspcntr |= DISPPLANE_RGBX101010; | |
17638cd6 JB |
2504 | break; |
2505 | default: | |
baba133a | 2506 | BUG(); |
17638cd6 JB |
2507 | } |
2508 | ||
2509 | if (obj->tiling_mode != I915_TILING_NONE) | |
2510 | dspcntr |= DISPPLANE_TILED; | |
2511 | else | |
2512 | dspcntr &= ~DISPPLANE_TILED; | |
2513 | ||
b42c6009 | 2514 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
1f5d76db PZ |
2515 | dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE; |
2516 | else | |
2517 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
17638cd6 JB |
2518 | |
2519 | I915_WRITE(reg, dspcntr); | |
2520 | ||
e506a0c6 | 2521 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
c2c75131 | 2522 | intel_crtc->dspaddr_offset = |
bc752862 CW |
2523 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2524 | fb->bits_per_pixel / 8, | |
2525 | fb->pitches[0]); | |
c2c75131 | 2526 | linear_offset -= intel_crtc->dspaddr_offset; |
17638cd6 | 2527 | |
f343c5f6 BW |
2528 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2529 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, | |
2530 | fb->pitches[0]); | |
01f2c773 | 2531 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2532 | I915_WRITE(DSPSURF(plane), |
2533 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2534 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2535 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2536 | } else { | |
2537 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2538 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2539 | } | |
17638cd6 | 2540 | POSTING_READ(reg); |
17638cd6 JB |
2541 | } |
2542 | ||
2543 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ | |
2544 | static int | |
2545 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
2546 | int x, int y, enum mode_set_atomic state) | |
2547 | { | |
2548 | struct drm_device *dev = crtc->dev; | |
2549 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 2550 | |
6b8e6ed0 CW |
2551 | if (dev_priv->display.disable_fbc) |
2552 | dev_priv->display.disable_fbc(dev); | |
cc36513c | 2553 | intel_increase_pllclock(dev, to_intel_crtc(crtc)->pipe); |
81255565 | 2554 | |
29b9bde6 DV |
2555 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
2556 | ||
2557 | return 0; | |
81255565 JB |
2558 | } |
2559 | ||
96a02917 VS |
2560 | void intel_display_handle_reset(struct drm_device *dev) |
2561 | { | |
2562 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2563 | struct drm_crtc *crtc; | |
2564 | ||
2565 | /* | |
2566 | * Flips in the rings have been nuked by the reset, | |
2567 | * so complete all pending flips so that user space | |
2568 | * will get its events and not get stuck. | |
2569 | * | |
2570 | * Also update the base address of all primary | |
2571 | * planes to the the last fb to make sure we're | |
2572 | * showing the correct fb after a reset. | |
2573 | * | |
2574 | * Need to make two loops over the crtcs so that we | |
2575 | * don't try to grab a crtc mutex before the | |
2576 | * pending_flip_queue really got woken up. | |
2577 | */ | |
2578 | ||
70e1e0ec | 2579 | for_each_crtc(dev, crtc) { |
96a02917 VS |
2580 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2581 | enum plane plane = intel_crtc->plane; | |
2582 | ||
2583 | intel_prepare_page_flip(dev, plane); | |
2584 | intel_finish_page_flip_plane(dev, plane); | |
2585 | } | |
2586 | ||
70e1e0ec | 2587 | for_each_crtc(dev, crtc) { |
96a02917 VS |
2588 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2589 | ||
51fd371b | 2590 | drm_modeset_lock(&crtc->mutex, NULL); |
947fdaad CW |
2591 | /* |
2592 | * FIXME: Once we have proper support for primary planes (and | |
2593 | * disabling them without disabling the entire crtc) allow again | |
66e514c1 | 2594 | * a NULL crtc->primary->fb. |
947fdaad | 2595 | */ |
f4510a27 | 2596 | if (intel_crtc->active && crtc->primary->fb) |
262ca2b0 | 2597 | dev_priv->display.update_primary_plane(crtc, |
66e514c1 | 2598 | crtc->primary->fb, |
262ca2b0 MR |
2599 | crtc->x, |
2600 | crtc->y); | |
51fd371b | 2601 | drm_modeset_unlock(&crtc->mutex); |
96a02917 VS |
2602 | } |
2603 | } | |
2604 | ||
14667a4b CW |
2605 | static int |
2606 | intel_finish_fb(struct drm_framebuffer *old_fb) | |
2607 | { | |
2ff8fde1 | 2608 | struct drm_i915_gem_object *obj = intel_fb_obj(old_fb); |
14667a4b CW |
2609 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
2610 | bool was_interruptible = dev_priv->mm.interruptible; | |
2611 | int ret; | |
2612 | ||
14667a4b CW |
2613 | /* Big Hammer, we also need to ensure that any pending |
2614 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
2615 | * current scanout is retired before unpinning the old | |
2616 | * framebuffer. | |
2617 | * | |
2618 | * This should only fail upon a hung GPU, in which case we | |
2619 | * can safely continue. | |
2620 | */ | |
2621 | dev_priv->mm.interruptible = false; | |
2622 | ret = i915_gem_object_finish_gpu(obj); | |
2623 | dev_priv->mm.interruptible = was_interruptible; | |
2624 | ||
2625 | return ret; | |
2626 | } | |
2627 | ||
7d5e3799 CW |
2628 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
2629 | { | |
2630 | struct drm_device *dev = crtc->dev; | |
2631 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2632 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2633 | unsigned long flags; | |
2634 | bool pending; | |
2635 | ||
2636 | if (i915_reset_in_progress(&dev_priv->gpu_error) || | |
2637 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
2638 | return false; | |
2639 | ||
2640 | spin_lock_irqsave(&dev->event_lock, flags); | |
2641 | pending = to_intel_crtc(crtc)->unpin_work != NULL; | |
2642 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
2643 | ||
2644 | return pending; | |
2645 | } | |
2646 | ||
5c3b82e2 | 2647 | static int |
3c4fdcfb | 2648 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
94352cf9 | 2649 | struct drm_framebuffer *fb) |
79e53945 JB |
2650 | { |
2651 | struct drm_device *dev = crtc->dev; | |
6b8e6ed0 | 2652 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 2653 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
a071fa00 | 2654 | enum pipe pipe = intel_crtc->pipe; |
2ff8fde1 MR |
2655 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
2656 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
2657 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb); | |
5c3b82e2 | 2658 | int ret; |
79e53945 | 2659 | |
7d5e3799 CW |
2660 | if (intel_crtc_has_pending_flip(crtc)) { |
2661 | DRM_ERROR("pipe is still busy with an old pageflip\n"); | |
2662 | return -EBUSY; | |
2663 | } | |
2664 | ||
79e53945 | 2665 | /* no fb bound */ |
94352cf9 | 2666 | if (!fb) { |
a5071c2f | 2667 | DRM_ERROR("No FB bound\n"); |
5c3b82e2 CW |
2668 | return 0; |
2669 | } | |
2670 | ||
7eb552ae | 2671 | if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) { |
84f44ce7 VS |
2672 | DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n", |
2673 | plane_name(intel_crtc->plane), | |
2674 | INTEL_INFO(dev)->num_pipes); | |
5c3b82e2 | 2675 | return -EINVAL; |
79e53945 JB |
2676 | } |
2677 | ||
5c3b82e2 | 2678 | mutex_lock(&dev->struct_mutex); |
a071fa00 DV |
2679 | ret = intel_pin_and_fence_fb_obj(dev, obj, NULL); |
2680 | if (ret == 0) | |
91565c85 | 2681 | i915_gem_track_fb(old_obj, obj, |
a071fa00 | 2682 | INTEL_FRONTBUFFER_PRIMARY(pipe)); |
8ac36ec1 | 2683 | mutex_unlock(&dev->struct_mutex); |
5c3b82e2 | 2684 | if (ret != 0) { |
a5071c2f | 2685 | DRM_ERROR("pin & fence failed\n"); |
5c3b82e2 CW |
2686 | return ret; |
2687 | } | |
79e53945 | 2688 | |
bb2043de DL |
2689 | /* |
2690 | * Update pipe size and adjust fitter if needed: the reason for this is | |
2691 | * that in compute_mode_changes we check the native mode (not the pfit | |
2692 | * mode) to see if we can flip rather than do a full mode set. In the | |
2693 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
2694 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
2695 | * sized surface. | |
2696 | * | |
2697 | * To fix this properly, we need to hoist the checks up into | |
2698 | * compute_mode_changes (or above), check the actual pfit state and | |
2699 | * whether the platform allows pfit disable with pipe active, and only | |
2700 | * then update the pipesrc and pfit state, even on the flip path. | |
2701 | */ | |
d330a953 | 2702 | if (i915.fastboot) { |
d7bf63f2 DL |
2703 | const struct drm_display_mode *adjusted_mode = |
2704 | &intel_crtc->config.adjusted_mode; | |
2705 | ||
4d6a3e63 | 2706 | I915_WRITE(PIPESRC(intel_crtc->pipe), |
d7bf63f2 DL |
2707 | ((adjusted_mode->crtc_hdisplay - 1) << 16) | |
2708 | (adjusted_mode->crtc_vdisplay - 1)); | |
fd4daa9c | 2709 | if (!intel_crtc->config.pch_pfit.enabled && |
4d6a3e63 JB |
2710 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
2711 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
2712 | I915_WRITE(PF_CTL(intel_crtc->pipe), 0); | |
2713 | I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0); | |
2714 | I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0); | |
2715 | } | |
0637d60d JB |
2716 | intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay; |
2717 | intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay; | |
4d6a3e63 JB |
2718 | } |
2719 | ||
29b9bde6 | 2720 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
3c4fdcfb | 2721 | |
f99d7069 DV |
2722 | if (intel_crtc->active) |
2723 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); | |
2724 | ||
f4510a27 | 2725 | crtc->primary->fb = fb; |
6c4c86f5 DV |
2726 | crtc->x = x; |
2727 | crtc->y = y; | |
94352cf9 | 2728 | |
b7f1de28 | 2729 | if (old_fb) { |
d7697eea DV |
2730 | if (intel_crtc->active && old_fb != fb) |
2731 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
8ac36ec1 | 2732 | mutex_lock(&dev->struct_mutex); |
2ff8fde1 | 2733 | intel_unpin_fb_obj(old_obj); |
8ac36ec1 | 2734 | mutex_unlock(&dev->struct_mutex); |
b7f1de28 | 2735 | } |
652c393a | 2736 | |
8ac36ec1 | 2737 | mutex_lock(&dev->struct_mutex); |
6b8e6ed0 | 2738 | intel_update_fbc(dev); |
5c3b82e2 | 2739 | mutex_unlock(&dev->struct_mutex); |
79e53945 | 2740 | |
5c3b82e2 | 2741 | return 0; |
79e53945 JB |
2742 | } |
2743 | ||
5e84e1a4 ZW |
2744 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
2745 | { | |
2746 | struct drm_device *dev = crtc->dev; | |
2747 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2748 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2749 | int pipe = intel_crtc->pipe; | |
2750 | u32 reg, temp; | |
2751 | ||
2752 | /* enable normal train */ | |
2753 | reg = FDI_TX_CTL(pipe); | |
2754 | temp = I915_READ(reg); | |
61e499bf | 2755 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
2756 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2757 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
2758 | } else { |
2759 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2760 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 2761 | } |
5e84e1a4 ZW |
2762 | I915_WRITE(reg, temp); |
2763 | ||
2764 | reg = FDI_RX_CTL(pipe); | |
2765 | temp = I915_READ(reg); | |
2766 | if (HAS_PCH_CPT(dev)) { | |
2767 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2768 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
2769 | } else { | |
2770 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2771 | temp |= FDI_LINK_TRAIN_NONE; | |
2772 | } | |
2773 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
2774 | ||
2775 | /* wait one idle pattern time */ | |
2776 | POSTING_READ(reg); | |
2777 | udelay(1000); | |
357555c0 JB |
2778 | |
2779 | /* IVB wants error correction enabled */ | |
2780 | if (IS_IVYBRIDGE(dev)) | |
2781 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
2782 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
2783 | } |
2784 | ||
1fbc0d78 | 2785 | static bool pipe_has_enabled_pch(struct intel_crtc *crtc) |
1e833f40 | 2786 | { |
1fbc0d78 DV |
2787 | return crtc->base.enabled && crtc->active && |
2788 | crtc->config.has_pch_encoder; | |
1e833f40 DV |
2789 | } |
2790 | ||
01a415fd DV |
2791 | static void ivb_modeset_global_resources(struct drm_device *dev) |
2792 | { | |
2793 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2794 | struct intel_crtc *pipe_B_crtc = | |
2795 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
2796 | struct intel_crtc *pipe_C_crtc = | |
2797 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]); | |
2798 | uint32_t temp; | |
2799 | ||
1e833f40 DV |
2800 | /* |
2801 | * When everything is off disable fdi C so that we could enable fdi B | |
2802 | * with all lanes. Note that we don't care about enabled pipes without | |
2803 | * an enabled pch encoder. | |
2804 | */ | |
2805 | if (!pipe_has_enabled_pch(pipe_B_crtc) && | |
2806 | !pipe_has_enabled_pch(pipe_C_crtc)) { | |
01a415fd DV |
2807 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
2808 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
2809 | ||
2810 | temp = I915_READ(SOUTH_CHICKEN1); | |
2811 | temp &= ~FDI_BC_BIFURCATION_SELECT; | |
2812 | DRM_DEBUG_KMS("disabling fdi C rx\n"); | |
2813 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
2814 | } | |
2815 | } | |
2816 | ||
8db9d77b ZW |
2817 | /* The FDI link training functions for ILK/Ibexpeak. */ |
2818 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
2819 | { | |
2820 | struct drm_device *dev = crtc->dev; | |
2821 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2822 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2823 | int pipe = intel_crtc->pipe; | |
5eddb70b | 2824 | u32 reg, temp, tries; |
8db9d77b | 2825 | |
1c8562f6 | 2826 | /* FDI needs bits from pipe first */ |
0fc932b8 | 2827 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 2828 | |
e1a44743 AJ |
2829 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2830 | for train result */ | |
5eddb70b CW |
2831 | reg = FDI_RX_IMR(pipe); |
2832 | temp = I915_READ(reg); | |
e1a44743 AJ |
2833 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2834 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2835 | I915_WRITE(reg, temp); |
2836 | I915_READ(reg); | |
e1a44743 AJ |
2837 | udelay(150); |
2838 | ||
8db9d77b | 2839 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2840 | reg = FDI_TX_CTL(pipe); |
2841 | temp = I915_READ(reg); | |
627eb5a3 DV |
2842 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2843 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
8db9d77b ZW |
2844 | temp &= ~FDI_LINK_TRAIN_NONE; |
2845 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 2846 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2847 | |
5eddb70b CW |
2848 | reg = FDI_RX_CTL(pipe); |
2849 | temp = I915_READ(reg); | |
8db9d77b ZW |
2850 | temp &= ~FDI_LINK_TRAIN_NONE; |
2851 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
2852 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2853 | ||
2854 | POSTING_READ(reg); | |
8db9d77b ZW |
2855 | udelay(150); |
2856 | ||
5b2adf89 | 2857 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
2858 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
2859 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
2860 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 2861 | |
5eddb70b | 2862 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2863 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2864 | temp = I915_READ(reg); |
8db9d77b ZW |
2865 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2866 | ||
2867 | if ((temp & FDI_RX_BIT_LOCK)) { | |
2868 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 2869 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
2870 | break; |
2871 | } | |
8db9d77b | 2872 | } |
e1a44743 | 2873 | if (tries == 5) |
5eddb70b | 2874 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2875 | |
2876 | /* Train 2 */ | |
5eddb70b CW |
2877 | reg = FDI_TX_CTL(pipe); |
2878 | temp = I915_READ(reg); | |
8db9d77b ZW |
2879 | temp &= ~FDI_LINK_TRAIN_NONE; |
2880 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2881 | I915_WRITE(reg, temp); |
8db9d77b | 2882 | |
5eddb70b CW |
2883 | reg = FDI_RX_CTL(pipe); |
2884 | temp = I915_READ(reg); | |
8db9d77b ZW |
2885 | temp &= ~FDI_LINK_TRAIN_NONE; |
2886 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2887 | I915_WRITE(reg, temp); |
8db9d77b | 2888 | |
5eddb70b CW |
2889 | POSTING_READ(reg); |
2890 | udelay(150); | |
8db9d77b | 2891 | |
5eddb70b | 2892 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2893 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2894 | temp = I915_READ(reg); |
8db9d77b ZW |
2895 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2896 | ||
2897 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 2898 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
2899 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2900 | break; | |
2901 | } | |
8db9d77b | 2902 | } |
e1a44743 | 2903 | if (tries == 5) |
5eddb70b | 2904 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2905 | |
2906 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 2907 | |
8db9d77b ZW |
2908 | } |
2909 | ||
0206e353 | 2910 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
2911 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
2912 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
2913 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
2914 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
2915 | }; | |
2916 | ||
2917 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
2918 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
2919 | { | |
2920 | struct drm_device *dev = crtc->dev; | |
2921 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2922 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2923 | int pipe = intel_crtc->pipe; | |
fa37d39e | 2924 | u32 reg, temp, i, retry; |
8db9d77b | 2925 | |
e1a44743 AJ |
2926 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2927 | for train result */ | |
5eddb70b CW |
2928 | reg = FDI_RX_IMR(pipe); |
2929 | temp = I915_READ(reg); | |
e1a44743 AJ |
2930 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2931 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2932 | I915_WRITE(reg, temp); |
2933 | ||
2934 | POSTING_READ(reg); | |
e1a44743 AJ |
2935 | udelay(150); |
2936 | ||
8db9d77b | 2937 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2938 | reg = FDI_TX_CTL(pipe); |
2939 | temp = I915_READ(reg); | |
627eb5a3 DV |
2940 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2941 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
8db9d77b ZW |
2942 | temp &= ~FDI_LINK_TRAIN_NONE; |
2943 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2944 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2945 | /* SNB-B */ | |
2946 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 2947 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2948 | |
d74cf324 DV |
2949 | I915_WRITE(FDI_RX_MISC(pipe), |
2950 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
2951 | ||
5eddb70b CW |
2952 | reg = FDI_RX_CTL(pipe); |
2953 | temp = I915_READ(reg); | |
8db9d77b ZW |
2954 | if (HAS_PCH_CPT(dev)) { |
2955 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2956 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2957 | } else { | |
2958 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2959 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2960 | } | |
5eddb70b CW |
2961 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2962 | ||
2963 | POSTING_READ(reg); | |
8db9d77b ZW |
2964 | udelay(150); |
2965 | ||
0206e353 | 2966 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2967 | reg = FDI_TX_CTL(pipe); |
2968 | temp = I915_READ(reg); | |
8db9d77b ZW |
2969 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2970 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2971 | I915_WRITE(reg, temp); |
2972 | ||
2973 | POSTING_READ(reg); | |
8db9d77b ZW |
2974 | udelay(500); |
2975 | ||
fa37d39e SP |
2976 | for (retry = 0; retry < 5; retry++) { |
2977 | reg = FDI_RX_IIR(pipe); | |
2978 | temp = I915_READ(reg); | |
2979 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2980 | if (temp & FDI_RX_BIT_LOCK) { | |
2981 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
2982 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
2983 | break; | |
2984 | } | |
2985 | udelay(50); | |
8db9d77b | 2986 | } |
fa37d39e SP |
2987 | if (retry < 5) |
2988 | break; | |
8db9d77b ZW |
2989 | } |
2990 | if (i == 4) | |
5eddb70b | 2991 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2992 | |
2993 | /* Train 2 */ | |
5eddb70b CW |
2994 | reg = FDI_TX_CTL(pipe); |
2995 | temp = I915_READ(reg); | |
8db9d77b ZW |
2996 | temp &= ~FDI_LINK_TRAIN_NONE; |
2997 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2998 | if (IS_GEN6(dev)) { | |
2999 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3000 | /* SNB-B */ | |
3001 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3002 | } | |
5eddb70b | 3003 | I915_WRITE(reg, temp); |
8db9d77b | 3004 | |
5eddb70b CW |
3005 | reg = FDI_RX_CTL(pipe); |
3006 | temp = I915_READ(reg); | |
8db9d77b ZW |
3007 | if (HAS_PCH_CPT(dev)) { |
3008 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3009 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3010 | } else { | |
3011 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3012 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3013 | } | |
5eddb70b CW |
3014 | I915_WRITE(reg, temp); |
3015 | ||
3016 | POSTING_READ(reg); | |
8db9d77b ZW |
3017 | udelay(150); |
3018 | ||
0206e353 | 3019 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3020 | reg = FDI_TX_CTL(pipe); |
3021 | temp = I915_READ(reg); | |
8db9d77b ZW |
3022 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3023 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3024 | I915_WRITE(reg, temp); |
3025 | ||
3026 | POSTING_READ(reg); | |
8db9d77b ZW |
3027 | udelay(500); |
3028 | ||
fa37d39e SP |
3029 | for (retry = 0; retry < 5; retry++) { |
3030 | reg = FDI_RX_IIR(pipe); | |
3031 | temp = I915_READ(reg); | |
3032 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3033 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3034 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3035 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3036 | break; | |
3037 | } | |
3038 | udelay(50); | |
8db9d77b | 3039 | } |
fa37d39e SP |
3040 | if (retry < 5) |
3041 | break; | |
8db9d77b ZW |
3042 | } |
3043 | if (i == 4) | |
5eddb70b | 3044 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3045 | |
3046 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3047 | } | |
3048 | ||
357555c0 JB |
3049 | /* Manual link training for Ivy Bridge A0 parts */ |
3050 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3051 | { | |
3052 | struct drm_device *dev = crtc->dev; | |
3053 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3054 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3055 | int pipe = intel_crtc->pipe; | |
139ccd3f | 3056 | u32 reg, temp, i, j; |
357555c0 JB |
3057 | |
3058 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3059 | for train result */ | |
3060 | reg = FDI_RX_IMR(pipe); | |
3061 | temp = I915_READ(reg); | |
3062 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3063 | temp &= ~FDI_RX_BIT_LOCK; | |
3064 | I915_WRITE(reg, temp); | |
3065 | ||
3066 | POSTING_READ(reg); | |
3067 | udelay(150); | |
3068 | ||
01a415fd DV |
3069 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3070 | I915_READ(FDI_RX_IIR(pipe))); | |
3071 | ||
139ccd3f JB |
3072 | /* Try each vswing and preemphasis setting twice before moving on */ |
3073 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3074 | /* disable first in case we need to retry */ | |
3075 | reg = FDI_TX_CTL(pipe); | |
3076 | temp = I915_READ(reg); | |
3077 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3078 | temp &= ~FDI_TX_ENABLE; | |
3079 | I915_WRITE(reg, temp); | |
357555c0 | 3080 | |
139ccd3f JB |
3081 | reg = FDI_RX_CTL(pipe); |
3082 | temp = I915_READ(reg); | |
3083 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3084 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3085 | temp &= ~FDI_RX_ENABLE; | |
3086 | I915_WRITE(reg, temp); | |
357555c0 | 3087 | |
139ccd3f | 3088 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3089 | reg = FDI_TX_CTL(pipe); |
3090 | temp = I915_READ(reg); | |
139ccd3f JB |
3091 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
3092 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
3093 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; | |
357555c0 | 3094 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3095 | temp |= snb_b_fdi_train_param[j/2]; |
3096 | temp |= FDI_COMPOSITE_SYNC; | |
3097 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3098 | |
139ccd3f JB |
3099 | I915_WRITE(FDI_RX_MISC(pipe), |
3100 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3101 | |
139ccd3f | 3102 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3103 | temp = I915_READ(reg); |
139ccd3f JB |
3104 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3105 | temp |= FDI_COMPOSITE_SYNC; | |
3106 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3107 | |
139ccd3f JB |
3108 | POSTING_READ(reg); |
3109 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3110 | |
139ccd3f JB |
3111 | for (i = 0; i < 4; i++) { |
3112 | reg = FDI_RX_IIR(pipe); | |
3113 | temp = I915_READ(reg); | |
3114 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3115 | |
139ccd3f JB |
3116 | if (temp & FDI_RX_BIT_LOCK || |
3117 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3118 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3119 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3120 | i); | |
3121 | break; | |
3122 | } | |
3123 | udelay(1); /* should be 0.5us */ | |
3124 | } | |
3125 | if (i == 4) { | |
3126 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3127 | continue; | |
3128 | } | |
357555c0 | 3129 | |
139ccd3f | 3130 | /* Train 2 */ |
357555c0 JB |
3131 | reg = FDI_TX_CTL(pipe); |
3132 | temp = I915_READ(reg); | |
139ccd3f JB |
3133 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3134 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3135 | I915_WRITE(reg, temp); | |
3136 | ||
3137 | reg = FDI_RX_CTL(pipe); | |
3138 | temp = I915_READ(reg); | |
3139 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3140 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3141 | I915_WRITE(reg, temp); |
3142 | ||
3143 | POSTING_READ(reg); | |
139ccd3f | 3144 | udelay(2); /* should be 1.5us */ |
357555c0 | 3145 | |
139ccd3f JB |
3146 | for (i = 0; i < 4; i++) { |
3147 | reg = FDI_RX_IIR(pipe); | |
3148 | temp = I915_READ(reg); | |
3149 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3150 | |
139ccd3f JB |
3151 | if (temp & FDI_RX_SYMBOL_LOCK || |
3152 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3153 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3154 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3155 | i); | |
3156 | goto train_done; | |
3157 | } | |
3158 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3159 | } |
139ccd3f JB |
3160 | if (i == 4) |
3161 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3162 | } |
357555c0 | 3163 | |
139ccd3f | 3164 | train_done: |
357555c0 JB |
3165 | DRM_DEBUG_KMS("FDI train done.\n"); |
3166 | } | |
3167 | ||
88cefb6c | 3168 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3169 | { |
88cefb6c | 3170 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3171 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3172 | int pipe = intel_crtc->pipe; |
5eddb70b | 3173 | u32 reg, temp; |
79e53945 | 3174 | |
c64e311e | 3175 | |
c98e9dcf | 3176 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3177 | reg = FDI_RX_CTL(pipe); |
3178 | temp = I915_READ(reg); | |
627eb5a3 DV |
3179 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
3180 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
dfd07d72 | 3181 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3182 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3183 | ||
3184 | POSTING_READ(reg); | |
c98e9dcf JB |
3185 | udelay(200); |
3186 | ||
3187 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3188 | temp = I915_READ(reg); |
3189 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3190 | ||
3191 | POSTING_READ(reg); | |
c98e9dcf JB |
3192 | udelay(200); |
3193 | ||
20749730 PZ |
3194 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3195 | reg = FDI_TX_CTL(pipe); | |
3196 | temp = I915_READ(reg); | |
3197 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3198 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3199 | |
20749730 PZ |
3200 | POSTING_READ(reg); |
3201 | udelay(100); | |
6be4a607 | 3202 | } |
0e23b99d JB |
3203 | } |
3204 | ||
88cefb6c DV |
3205 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3206 | { | |
3207 | struct drm_device *dev = intel_crtc->base.dev; | |
3208 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3209 | int pipe = intel_crtc->pipe; | |
3210 | u32 reg, temp; | |
3211 | ||
3212 | /* Switch from PCDclk to Rawclk */ | |
3213 | reg = FDI_RX_CTL(pipe); | |
3214 | temp = I915_READ(reg); | |
3215 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3216 | ||
3217 | /* Disable CPU FDI TX PLL */ | |
3218 | reg = FDI_TX_CTL(pipe); | |
3219 | temp = I915_READ(reg); | |
3220 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3221 | ||
3222 | POSTING_READ(reg); | |
3223 | udelay(100); | |
3224 | ||
3225 | reg = FDI_RX_CTL(pipe); | |
3226 | temp = I915_READ(reg); | |
3227 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3228 | ||
3229 | /* Wait for the clocks to turn off. */ | |
3230 | POSTING_READ(reg); | |
3231 | udelay(100); | |
3232 | } | |
3233 | ||
0fc932b8 JB |
3234 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3235 | { | |
3236 | struct drm_device *dev = crtc->dev; | |
3237 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3238 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3239 | int pipe = intel_crtc->pipe; | |
3240 | u32 reg, temp; | |
3241 | ||
3242 | /* disable CPU FDI tx and PCH FDI rx */ | |
3243 | reg = FDI_TX_CTL(pipe); | |
3244 | temp = I915_READ(reg); | |
3245 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3246 | POSTING_READ(reg); | |
3247 | ||
3248 | reg = FDI_RX_CTL(pipe); | |
3249 | temp = I915_READ(reg); | |
3250 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3251 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3252 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3253 | ||
3254 | POSTING_READ(reg); | |
3255 | udelay(100); | |
3256 | ||
3257 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3258 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3259 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3260 | |
3261 | /* still set train pattern 1 */ | |
3262 | reg = FDI_TX_CTL(pipe); | |
3263 | temp = I915_READ(reg); | |
3264 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3265 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3266 | I915_WRITE(reg, temp); | |
3267 | ||
3268 | reg = FDI_RX_CTL(pipe); | |
3269 | temp = I915_READ(reg); | |
3270 | if (HAS_PCH_CPT(dev)) { | |
3271 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3272 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3273 | } else { | |
3274 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3275 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3276 | } | |
3277 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3278 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3279 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3280 | I915_WRITE(reg, temp); |
3281 | ||
3282 | POSTING_READ(reg); | |
3283 | udelay(100); | |
3284 | } | |
3285 | ||
5dce5b93 CW |
3286 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3287 | { | |
3288 | struct intel_crtc *crtc; | |
3289 | ||
3290 | /* Note that we don't need to be called with mode_config.lock here | |
3291 | * as our list of CRTC objects is static for the lifetime of the | |
3292 | * device and so cannot disappear as we iterate. Similarly, we can | |
3293 | * happily treat the predicates as racy, atomic checks as userspace | |
3294 | * cannot claim and pin a new fb without at least acquring the | |
3295 | * struct_mutex and so serialising with us. | |
3296 | */ | |
d3fcc808 | 3297 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3298 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3299 | continue; | |
3300 | ||
3301 | if (crtc->unpin_work) | |
3302 | intel_wait_for_vblank(dev, crtc->pipe); | |
3303 | ||
3304 | return true; | |
3305 | } | |
3306 | ||
3307 | return false; | |
3308 | } | |
3309 | ||
46a55d30 | 3310 | void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3311 | { |
0f91128d | 3312 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3313 | struct drm_i915_private *dev_priv = dev->dev_private; |
e6c3a2a6 | 3314 | |
f4510a27 | 3315 | if (crtc->primary->fb == NULL) |
e6c3a2a6 CW |
3316 | return; |
3317 | ||
2c10d571 DV |
3318 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
3319 | ||
eed6d67d DV |
3320 | WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue, |
3321 | !intel_crtc_has_pending_flip(crtc), | |
3322 | 60*HZ) == 0); | |
5bb61643 | 3323 | |
0f91128d | 3324 | mutex_lock(&dev->struct_mutex); |
f4510a27 | 3325 | intel_finish_fb(crtc->primary->fb); |
0f91128d | 3326 | mutex_unlock(&dev->struct_mutex); |
e6c3a2a6 CW |
3327 | } |
3328 | ||
e615efe4 ED |
3329 | /* Program iCLKIP clock to the desired frequency */ |
3330 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3331 | { | |
3332 | struct drm_device *dev = crtc->dev; | |
3333 | struct drm_i915_private *dev_priv = dev->dev_private; | |
241bfc38 | 3334 | int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock; |
e615efe4 ED |
3335 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3336 | u32 temp; | |
3337 | ||
09153000 DV |
3338 | mutex_lock(&dev_priv->dpio_lock); |
3339 | ||
e615efe4 ED |
3340 | /* It is necessary to ungate the pixclk gate prior to programming |
3341 | * the divisors, and gate it back when it is done. | |
3342 | */ | |
3343 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3344 | ||
3345 | /* Disable SSCCTL */ | |
3346 | intel_sbi_write(dev_priv, SBI_SSCCTL6, | |
988d6ee8 PZ |
3347 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
3348 | SBI_SSCCTL_DISABLE, | |
3349 | SBI_ICLK); | |
e615efe4 ED |
3350 | |
3351 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 3352 | if (clock == 20000) { |
e615efe4 ED |
3353 | auxdiv = 1; |
3354 | divsel = 0x41; | |
3355 | phaseinc = 0x20; | |
3356 | } else { | |
3357 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
3358 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3359 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
3360 | * convert the virtual clock precision to KHz here for higher |
3361 | * precision. | |
3362 | */ | |
3363 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3364 | u32 iclk_pi_range = 64; | |
3365 | u32 desired_divisor, msb_divisor_value, pi_value; | |
3366 | ||
12d7ceed | 3367 | desired_divisor = (iclk_virtual_root_freq / clock); |
e615efe4 ED |
3368 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3369 | pi_value = desired_divisor % iclk_pi_range; | |
3370 | ||
3371 | auxdiv = 0; | |
3372 | divsel = msb_divisor_value - 2; | |
3373 | phaseinc = pi_value; | |
3374 | } | |
3375 | ||
3376 | /* This should not happen with any sane values */ | |
3377 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3378 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3379 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3380 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3381 | ||
3382 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3383 | clock, |
e615efe4 ED |
3384 | auxdiv, |
3385 | divsel, | |
3386 | phasedir, | |
3387 | phaseinc); | |
3388 | ||
3389 | /* Program SSCDIVINTPHASE6 */ | |
988d6ee8 | 3390 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
3391 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
3392 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
3393 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
3394 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
3395 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
3396 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 3397 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
3398 | |
3399 | /* Program SSCAUXDIV */ | |
988d6ee8 | 3400 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
3401 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
3402 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 3403 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
3404 | |
3405 | /* Enable modulator and associated divider */ | |
988d6ee8 | 3406 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 3407 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 3408 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 ED |
3409 | |
3410 | /* Wait for initialization time */ | |
3411 | udelay(24); | |
3412 | ||
3413 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
09153000 DV |
3414 | |
3415 | mutex_unlock(&dev_priv->dpio_lock); | |
e615efe4 ED |
3416 | } |
3417 | ||
275f01b2 DV |
3418 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
3419 | enum pipe pch_transcoder) | |
3420 | { | |
3421 | struct drm_device *dev = crtc->base.dev; | |
3422 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3423 | enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; | |
3424 | ||
3425 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
3426 | I915_READ(HTOTAL(cpu_transcoder))); | |
3427 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
3428 | I915_READ(HBLANK(cpu_transcoder))); | |
3429 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
3430 | I915_READ(HSYNC(cpu_transcoder))); | |
3431 | ||
3432 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
3433 | I915_READ(VTOTAL(cpu_transcoder))); | |
3434 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
3435 | I915_READ(VBLANK(cpu_transcoder))); | |
3436 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
3437 | I915_READ(VSYNC(cpu_transcoder))); | |
3438 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
3439 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
3440 | } | |
3441 | ||
1fbc0d78 DV |
3442 | static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev) |
3443 | { | |
3444 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3445 | uint32_t temp; | |
3446 | ||
3447 | temp = I915_READ(SOUTH_CHICKEN1); | |
3448 | if (temp & FDI_BC_BIFURCATION_SELECT) | |
3449 | return; | |
3450 | ||
3451 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
3452 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
3453 | ||
3454 | temp |= FDI_BC_BIFURCATION_SELECT; | |
3455 | DRM_DEBUG_KMS("enabling fdi C rx\n"); | |
3456 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
3457 | POSTING_READ(SOUTH_CHICKEN1); | |
3458 | } | |
3459 | ||
3460 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
3461 | { | |
3462 | struct drm_device *dev = intel_crtc->base.dev; | |
3463 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3464 | ||
3465 | switch (intel_crtc->pipe) { | |
3466 | case PIPE_A: | |
3467 | break; | |
3468 | case PIPE_B: | |
3469 | if (intel_crtc->config.fdi_lanes > 2) | |
3470 | WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT); | |
3471 | else | |
3472 | cpt_enable_fdi_bc_bifurcation(dev); | |
3473 | ||
3474 | break; | |
3475 | case PIPE_C: | |
3476 | cpt_enable_fdi_bc_bifurcation(dev); | |
3477 | ||
3478 | break; | |
3479 | default: | |
3480 | BUG(); | |
3481 | } | |
3482 | } | |
3483 | ||
f67a559d JB |
3484 | /* |
3485 | * Enable PCH resources required for PCH ports: | |
3486 | * - PCH PLLs | |
3487 | * - FDI training & RX/TX | |
3488 | * - update transcoder timings | |
3489 | * - DP transcoding bits | |
3490 | * - transcoder | |
3491 | */ | |
3492 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
3493 | { |
3494 | struct drm_device *dev = crtc->dev; | |
3495 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3496 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3497 | int pipe = intel_crtc->pipe; | |
ee7b9f93 | 3498 | u32 reg, temp; |
2c07245f | 3499 | |
ab9412ba | 3500 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 3501 | |
1fbc0d78 DV |
3502 | if (IS_IVYBRIDGE(dev)) |
3503 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
3504 | ||
cd986abb DV |
3505 | /* Write the TU size bits before fdi link training, so that error |
3506 | * detection works. */ | |
3507 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
3508 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
3509 | ||
c98e9dcf | 3510 | /* For PCH output, training FDI link */ |
674cf967 | 3511 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 3512 | |
3ad8a208 DV |
3513 | /* We need to program the right clock selection before writing the pixel |
3514 | * mutliplier into the DPLL. */ | |
303b81e0 | 3515 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 3516 | u32 sel; |
4b645f14 | 3517 | |
c98e9dcf | 3518 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
3519 | temp |= TRANS_DPLL_ENABLE(pipe); |
3520 | sel = TRANS_DPLLB_SEL(pipe); | |
a43f6e0f | 3521 | if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
3522 | temp |= sel; |
3523 | else | |
3524 | temp &= ~sel; | |
c98e9dcf | 3525 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 3526 | } |
5eddb70b | 3527 | |
3ad8a208 DV |
3528 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
3529 | * transcoder, and we actually should do this to not upset any PCH | |
3530 | * transcoder that already use the clock when we share it. | |
3531 | * | |
3532 | * Note that enable_shared_dpll tries to do the right thing, but | |
3533 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
3534 | * the right LVDS enable sequence. */ | |
85b3894f | 3535 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 3536 | |
d9b6cb56 JB |
3537 | /* set transcoder timing, panel must allow it */ |
3538 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 3539 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 3540 | |
303b81e0 | 3541 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 3542 | |
c98e9dcf JB |
3543 | /* For PCH DP, enable TRANS_DP_CTL */ |
3544 | if (HAS_PCH_CPT(dev) && | |
417e822d KP |
3545 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
3546 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
dfd07d72 | 3547 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
5eddb70b CW |
3548 | reg = TRANS_DP_CTL(pipe); |
3549 | temp = I915_READ(reg); | |
3550 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
3551 | TRANS_DP_SYNC_MASK | |
3552 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
3553 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
3554 | TRANS_DP_ENH_FRAMING); | |
9325c9f0 | 3555 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
3556 | |
3557 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 3558 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 3559 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 3560 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
3561 | |
3562 | switch (intel_trans_dp_port_sel(crtc)) { | |
3563 | case PCH_DP_B: | |
5eddb70b | 3564 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
3565 | break; |
3566 | case PCH_DP_C: | |
5eddb70b | 3567 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
3568 | break; |
3569 | case PCH_DP_D: | |
5eddb70b | 3570 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
3571 | break; |
3572 | default: | |
e95d41e1 | 3573 | BUG(); |
32f9d658 | 3574 | } |
2c07245f | 3575 | |
5eddb70b | 3576 | I915_WRITE(reg, temp); |
6be4a607 | 3577 | } |
b52eb4dc | 3578 | |
b8a4f404 | 3579 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
3580 | } |
3581 | ||
1507e5bd PZ |
3582 | static void lpt_pch_enable(struct drm_crtc *crtc) |
3583 | { | |
3584 | struct drm_device *dev = crtc->dev; | |
3585 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3586 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3b117c8f | 3587 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
1507e5bd | 3588 | |
ab9412ba | 3589 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 3590 | |
8c52b5e8 | 3591 | lpt_program_iclkip(crtc); |
1507e5bd | 3592 | |
0540e488 | 3593 | /* Set transcoder timing. */ |
275f01b2 | 3594 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 3595 | |
937bb610 | 3596 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
3597 | } |
3598 | ||
716c2e55 | 3599 | void intel_put_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 3600 | { |
e2b78267 | 3601 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
ee7b9f93 JB |
3602 | |
3603 | if (pll == NULL) | |
3604 | return; | |
3605 | ||
3606 | if (pll->refcount == 0) { | |
46edb027 | 3607 | WARN(1, "bad %s refcount\n", pll->name); |
ee7b9f93 JB |
3608 | return; |
3609 | } | |
3610 | ||
f4a091c7 DV |
3611 | if (--pll->refcount == 0) { |
3612 | WARN_ON(pll->on); | |
3613 | WARN_ON(pll->active); | |
3614 | } | |
3615 | ||
a43f6e0f | 3616 | crtc->config.shared_dpll = DPLL_ID_PRIVATE; |
ee7b9f93 JB |
3617 | } |
3618 | ||
716c2e55 | 3619 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 3620 | { |
e2b78267 DV |
3621 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
3622 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
3623 | enum intel_dpll_id i; | |
ee7b9f93 | 3624 | |
ee7b9f93 | 3625 | if (pll) { |
46edb027 DV |
3626 | DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n", |
3627 | crtc->base.base.id, pll->name); | |
e2b78267 | 3628 | intel_put_shared_dpll(crtc); |
ee7b9f93 JB |
3629 | } |
3630 | ||
98b6bd99 DV |
3631 | if (HAS_PCH_IBX(dev_priv->dev)) { |
3632 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 3633 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 3634 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 3635 | |
46edb027 DV |
3636 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
3637 | crtc->base.base.id, pll->name); | |
98b6bd99 | 3638 | |
f2a69f44 DV |
3639 | WARN_ON(pll->refcount); |
3640 | ||
98b6bd99 DV |
3641 | goto found; |
3642 | } | |
3643 | ||
e72f9fbf DV |
3644 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3645 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 JB |
3646 | |
3647 | /* Only want to check enabled timings first */ | |
3648 | if (pll->refcount == 0) | |
3649 | continue; | |
3650 | ||
b89a1d39 DV |
3651 | if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state, |
3652 | sizeof(pll->hw_state)) == 0) { | |
46edb027 | 3653 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n", |
e2b78267 | 3654 | crtc->base.base.id, |
46edb027 | 3655 | pll->name, pll->refcount, pll->active); |
ee7b9f93 JB |
3656 | |
3657 | goto found; | |
3658 | } | |
3659 | } | |
3660 | ||
3661 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
3662 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3663 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 | 3664 | if (pll->refcount == 0) { |
46edb027 DV |
3665 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
3666 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
3667 | goto found; |
3668 | } | |
3669 | } | |
3670 | ||
3671 | return NULL; | |
3672 | ||
3673 | found: | |
f2a69f44 DV |
3674 | if (pll->refcount == 0) |
3675 | pll->hw_state = crtc->config.dpll_hw_state; | |
3676 | ||
a43f6e0f | 3677 | crtc->config.shared_dpll = i; |
46edb027 DV |
3678 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
3679 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 3680 | |
cdbd2316 | 3681 | pll->refcount++; |
e04c7350 | 3682 | |
ee7b9f93 JB |
3683 | return pll; |
3684 | } | |
3685 | ||
a1520318 | 3686 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
3687 | { |
3688 | struct drm_i915_private *dev_priv = dev->dev_private; | |
23670b32 | 3689 | int dslreg = PIPEDSL(pipe); |
d4270e57 JB |
3690 | u32 temp; |
3691 | ||
3692 | temp = I915_READ(dslreg); | |
3693 | udelay(500); | |
3694 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 3695 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 3696 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
3697 | } |
3698 | } | |
3699 | ||
b074cec8 JB |
3700 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
3701 | { | |
3702 | struct drm_device *dev = crtc->base.dev; | |
3703 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3704 | int pipe = crtc->pipe; | |
3705 | ||
fd4daa9c | 3706 | if (crtc->config.pch_pfit.enabled) { |
b074cec8 JB |
3707 | /* Force use of hard-coded filter coefficients |
3708 | * as some pre-programmed values are broken, | |
3709 | * e.g. x201. | |
3710 | */ | |
3711 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
3712 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
3713 | PF_PIPE_SEL_IVB(pipe)); | |
3714 | else | |
3715 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
3716 | I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos); | |
3717 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size); | |
d4270e57 JB |
3718 | } |
3719 | } | |
3720 | ||
bb53d4ae VS |
3721 | static void intel_enable_planes(struct drm_crtc *crtc) |
3722 | { | |
3723 | struct drm_device *dev = crtc->dev; | |
3724 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
af2b653b | 3725 | struct drm_plane *plane; |
bb53d4ae VS |
3726 | struct intel_plane *intel_plane; |
3727 | ||
af2b653b MR |
3728 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
3729 | intel_plane = to_intel_plane(plane); | |
bb53d4ae VS |
3730 | if (intel_plane->pipe == pipe) |
3731 | intel_plane_restore(&intel_plane->base); | |
af2b653b | 3732 | } |
bb53d4ae VS |
3733 | } |
3734 | ||
3735 | static void intel_disable_planes(struct drm_crtc *crtc) | |
3736 | { | |
3737 | struct drm_device *dev = crtc->dev; | |
3738 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
af2b653b | 3739 | struct drm_plane *plane; |
bb53d4ae VS |
3740 | struct intel_plane *intel_plane; |
3741 | ||
af2b653b MR |
3742 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
3743 | intel_plane = to_intel_plane(plane); | |
bb53d4ae VS |
3744 | if (intel_plane->pipe == pipe) |
3745 | intel_plane_disable(&intel_plane->base); | |
af2b653b | 3746 | } |
bb53d4ae VS |
3747 | } |
3748 | ||
20bc8673 | 3749 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 3750 | { |
cea165c3 VS |
3751 | struct drm_device *dev = crtc->base.dev; |
3752 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d77e4531 PZ |
3753 | |
3754 | if (!crtc->config.ips_enabled) | |
3755 | return; | |
3756 | ||
cea165c3 VS |
3757 | /* We can only enable IPS after we enable a plane and wait for a vblank */ |
3758 | intel_wait_for_vblank(dev, crtc->pipe); | |
3759 | ||
d77e4531 | 3760 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 3761 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
3762 | mutex_lock(&dev_priv->rps.hw_lock); |
3763 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
3764 | mutex_unlock(&dev_priv->rps.hw_lock); | |
3765 | /* Quoting Art Runyan: "its not safe to expect any particular | |
3766 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
3767 | * mailbox." Moreover, the mailbox may return a bogus state, |
3768 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
3769 | */ |
3770 | } else { | |
3771 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
3772 | /* The bit only becomes 1 in the next vblank, so this wait here | |
3773 | * is essentially intel_wait_for_vblank. If we don't have this | |
3774 | * and don't wait for vblanks until the end of crtc_enable, then | |
3775 | * the HW state readout code will complain that the expected | |
3776 | * IPS_CTL value is not the one we read. */ | |
3777 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
3778 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
3779 | } | |
d77e4531 PZ |
3780 | } |
3781 | ||
20bc8673 | 3782 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
3783 | { |
3784 | struct drm_device *dev = crtc->base.dev; | |
3785 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3786 | ||
3787 | if (!crtc->config.ips_enabled) | |
3788 | return; | |
3789 | ||
3790 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 3791 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
3792 | mutex_lock(&dev_priv->rps.hw_lock); |
3793 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
3794 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
3795 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
3796 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
3797 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 3798 | } else { |
2a114cc1 | 3799 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
3800 | POSTING_READ(IPS_CTL); |
3801 | } | |
d77e4531 PZ |
3802 | |
3803 | /* We need to wait for a vblank before we can disable the plane. */ | |
3804 | intel_wait_for_vblank(dev, crtc->pipe); | |
3805 | } | |
3806 | ||
3807 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
3808 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
3809 | { | |
3810 | struct drm_device *dev = crtc->dev; | |
3811 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3812 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3813 | enum pipe pipe = intel_crtc->pipe; | |
3814 | int palreg = PALETTE(pipe); | |
3815 | int i; | |
3816 | bool reenable_ips = false; | |
3817 | ||
3818 | /* The clocks have to be on to load the palette. */ | |
3819 | if (!crtc->enabled || !intel_crtc->active) | |
3820 | return; | |
3821 | ||
3822 | if (!HAS_PCH_SPLIT(dev_priv->dev)) { | |
3823 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) | |
3824 | assert_dsi_pll_enabled(dev_priv); | |
3825 | else | |
3826 | assert_pll_enabled(dev_priv, pipe); | |
3827 | } | |
3828 | ||
3829 | /* use legacy palette for Ironlake */ | |
7a1db49a | 3830 | if (!HAS_GMCH_DISPLAY(dev)) |
d77e4531 PZ |
3831 | palreg = LGC_PALETTE(pipe); |
3832 | ||
3833 | /* Workaround : Do not read or write the pipe palette/gamma data while | |
3834 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
3835 | */ | |
41e6fc4c | 3836 | if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled && |
d77e4531 PZ |
3837 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
3838 | GAMMA_MODE_MODE_SPLIT)) { | |
3839 | hsw_disable_ips(intel_crtc); | |
3840 | reenable_ips = true; | |
3841 | } | |
3842 | ||
3843 | for (i = 0; i < 256; i++) { | |
3844 | I915_WRITE(palreg + 4 * i, | |
3845 | (intel_crtc->lut_r[i] << 16) | | |
3846 | (intel_crtc->lut_g[i] << 8) | | |
3847 | intel_crtc->lut_b[i]); | |
3848 | } | |
3849 | ||
3850 | if (reenable_ips) | |
3851 | hsw_enable_ips(intel_crtc); | |
3852 | } | |
3853 | ||
d3eedb1a VS |
3854 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
3855 | { | |
3856 | if (!enable && intel_crtc->overlay) { | |
3857 | struct drm_device *dev = intel_crtc->base.dev; | |
3858 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3859 | ||
3860 | mutex_lock(&dev->struct_mutex); | |
3861 | dev_priv->mm.interruptible = false; | |
3862 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
3863 | dev_priv->mm.interruptible = true; | |
3864 | mutex_unlock(&dev->struct_mutex); | |
3865 | } | |
3866 | ||
3867 | /* Let userspace switch the overlay on again. In most cases userspace | |
3868 | * has to recompute where to put it anyway. | |
3869 | */ | |
3870 | } | |
3871 | ||
d3eedb1a | 3872 | static void intel_crtc_enable_planes(struct drm_crtc *crtc) |
a5c4d7bc VS |
3873 | { |
3874 | struct drm_device *dev = crtc->dev; | |
3875 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3876 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3877 | int pipe = intel_crtc->pipe; | |
3878 | int plane = intel_crtc->plane; | |
3879 | ||
f98551ae VS |
3880 | drm_vblank_on(dev, pipe); |
3881 | ||
a5c4d7bc VS |
3882 | intel_enable_primary_hw_plane(dev_priv, plane, pipe); |
3883 | intel_enable_planes(crtc); | |
3884 | intel_crtc_update_cursor(crtc, true); | |
d3eedb1a | 3885 | intel_crtc_dpms_overlay(intel_crtc, true); |
a5c4d7bc VS |
3886 | |
3887 | hsw_enable_ips(intel_crtc); | |
3888 | ||
3889 | mutex_lock(&dev->struct_mutex); | |
3890 | intel_update_fbc(dev); | |
3891 | mutex_unlock(&dev->struct_mutex); | |
f99d7069 DV |
3892 | |
3893 | /* | |
3894 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
3895 | * to compute the mask of flip planes precisely. For the time being | |
3896 | * consider this a flip from a NULL plane. | |
3897 | */ | |
3898 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
3899 | } |
3900 | ||
d3eedb1a | 3901 | static void intel_crtc_disable_planes(struct drm_crtc *crtc) |
a5c4d7bc VS |
3902 | { |
3903 | struct drm_device *dev = crtc->dev; | |
3904 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3905 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3906 | int pipe = intel_crtc->pipe; | |
3907 | int plane = intel_crtc->plane; | |
3908 | ||
3909 | intel_crtc_wait_for_pending_flips(crtc); | |
a5c4d7bc VS |
3910 | |
3911 | if (dev_priv->fbc.plane == plane) | |
3912 | intel_disable_fbc(dev); | |
3913 | ||
3914 | hsw_disable_ips(intel_crtc); | |
3915 | ||
d3eedb1a | 3916 | intel_crtc_dpms_overlay(intel_crtc, false); |
a5c4d7bc VS |
3917 | intel_crtc_update_cursor(crtc, false); |
3918 | intel_disable_planes(crtc); | |
3919 | intel_disable_primary_hw_plane(dev_priv, plane, pipe); | |
f98551ae | 3920 | |
f99d7069 DV |
3921 | /* |
3922 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
3923 | * to compute the mask of flip planes precisely. For the time being | |
3924 | * consider this a flip to a NULL plane. | |
3925 | */ | |
3926 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
3927 | ||
f98551ae | 3928 | drm_vblank_off(dev, pipe); |
a5c4d7bc VS |
3929 | } |
3930 | ||
f67a559d JB |
3931 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
3932 | { | |
3933 | struct drm_device *dev = crtc->dev; | |
3934 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3935 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3936 | struct intel_encoder *encoder; |
f67a559d | 3937 | int pipe = intel_crtc->pipe; |
29407aab | 3938 | enum plane plane = intel_crtc->plane; |
f67a559d | 3939 | |
08a48469 DV |
3940 | WARN_ON(!crtc->enabled); |
3941 | ||
f67a559d JB |
3942 | if (intel_crtc->active) |
3943 | return; | |
3944 | ||
b14b1055 DV |
3945 | if (intel_crtc->config.has_pch_encoder) |
3946 | intel_prepare_shared_dpll(intel_crtc); | |
3947 | ||
29407aab DV |
3948 | if (intel_crtc->config.has_dp_encoder) |
3949 | intel_dp_set_m_n(intel_crtc); | |
3950 | ||
3951 | intel_set_pipe_timings(intel_crtc); | |
3952 | ||
3953 | if (intel_crtc->config.has_pch_encoder) { | |
3954 | intel_cpu_transcoder_set_m_n(intel_crtc, | |
f769cd24 | 3955 | &intel_crtc->config.fdi_m_n, NULL); |
29407aab DV |
3956 | } |
3957 | ||
3958 | ironlake_set_pipeconf(crtc); | |
3959 | ||
3960 | /* Set up the display plane register */ | |
3961 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); | |
3962 | POSTING_READ(DSPCNTR(plane)); | |
3963 | ||
3964 | dev_priv->display.update_primary_plane(crtc, crtc->primary->fb, | |
3965 | crtc->x, crtc->y); | |
3966 | ||
f67a559d | 3967 | intel_crtc->active = true; |
8664281b PZ |
3968 | |
3969 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
3970 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); | |
3971 | ||
f6736a1a | 3972 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
3973 | if (encoder->pre_enable) |
3974 | encoder->pre_enable(encoder); | |
f67a559d | 3975 | |
5bfe2ac0 | 3976 | if (intel_crtc->config.has_pch_encoder) { |
fff367c7 DV |
3977 | /* Note: FDI PLL enabling _must_ be done before we enable the |
3978 | * cpu pipes, hence this is separate from all the other fdi/pch | |
3979 | * enabling. */ | |
88cefb6c | 3980 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
3981 | } else { |
3982 | assert_fdi_tx_disabled(dev_priv, pipe); | |
3983 | assert_fdi_rx_disabled(dev_priv, pipe); | |
3984 | } | |
f67a559d | 3985 | |
b074cec8 | 3986 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 3987 | |
9c54c0dd JB |
3988 | /* |
3989 | * On ILK+ LUT must be loaded before the pipe is running but with | |
3990 | * clocks enabled | |
3991 | */ | |
3992 | intel_crtc_load_lut(crtc); | |
3993 | ||
f37fcc2a | 3994 | intel_update_watermarks(crtc); |
e1fdc473 | 3995 | intel_enable_pipe(intel_crtc); |
f67a559d | 3996 | |
5bfe2ac0 | 3997 | if (intel_crtc->config.has_pch_encoder) |
f67a559d | 3998 | ironlake_pch_enable(crtc); |
c98e9dcf | 3999 | |
fa5c73b1 DV |
4000 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4001 | encoder->enable(encoder); | |
61b77ddd DV |
4002 | |
4003 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4004 | cpt_verify_modeset(dev, intel_crtc->pipe); |
6ce94100 | 4005 | |
d3eedb1a | 4006 | intel_crtc_enable_planes(crtc); |
6be4a607 JB |
4007 | } |
4008 | ||
42db64ef PZ |
4009 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4010 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4011 | { | |
f5adf94e | 4012 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4013 | } |
4014 | ||
e4916946 PZ |
4015 | /* |
4016 | * This implements the workaround described in the "notes" section of the mode | |
4017 | * set sequence documentation. When going from no pipes or single pipe to | |
4018 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
4019 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
4020 | */ | |
4021 | static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc) | |
4022 | { | |
4023 | struct drm_device *dev = crtc->base.dev; | |
4024 | struct intel_crtc *crtc_it, *other_active_crtc = NULL; | |
4025 | ||
4026 | /* We want to get the other_active_crtc only if there's only 1 other | |
4027 | * active crtc. */ | |
d3fcc808 | 4028 | for_each_intel_crtc(dev, crtc_it) { |
e4916946 PZ |
4029 | if (!crtc_it->active || crtc_it == crtc) |
4030 | continue; | |
4031 | ||
4032 | if (other_active_crtc) | |
4033 | return; | |
4034 | ||
4035 | other_active_crtc = crtc_it; | |
4036 | } | |
4037 | if (!other_active_crtc) | |
4038 | return; | |
4039 | ||
4040 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4041 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4042 | } | |
4043 | ||
4f771f10 PZ |
4044 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4045 | { | |
4046 | struct drm_device *dev = crtc->dev; | |
4047 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4048 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4049 | struct intel_encoder *encoder; | |
4050 | int pipe = intel_crtc->pipe; | |
229fca97 | 4051 | enum plane plane = intel_crtc->plane; |
4f771f10 PZ |
4052 | |
4053 | WARN_ON(!crtc->enabled); | |
4054 | ||
4055 | if (intel_crtc->active) | |
4056 | return; | |
4057 | ||
df8ad70c DV |
4058 | if (intel_crtc_to_shared_dpll(intel_crtc)) |
4059 | intel_enable_shared_dpll(intel_crtc); | |
4060 | ||
229fca97 DV |
4061 | if (intel_crtc->config.has_dp_encoder) |
4062 | intel_dp_set_m_n(intel_crtc); | |
4063 | ||
4064 | intel_set_pipe_timings(intel_crtc); | |
4065 | ||
4066 | if (intel_crtc->config.has_pch_encoder) { | |
4067 | intel_cpu_transcoder_set_m_n(intel_crtc, | |
f769cd24 | 4068 | &intel_crtc->config.fdi_m_n, NULL); |
229fca97 DV |
4069 | } |
4070 | ||
4071 | haswell_set_pipeconf(crtc); | |
4072 | ||
4073 | intel_set_pipe_csc(crtc); | |
4074 | ||
4075 | /* Set up the display plane register */ | |
4076 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE); | |
4077 | POSTING_READ(DSPCNTR(plane)); | |
4078 | ||
4079 | dev_priv->display.update_primary_plane(crtc, crtc->primary->fb, | |
4080 | crtc->x, crtc->y); | |
4081 | ||
4f771f10 | 4082 | intel_crtc->active = true; |
8664281b PZ |
4083 | |
4084 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
4f771f10 PZ |
4085 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4086 | if (encoder->pre_enable) | |
4087 | encoder->pre_enable(encoder); | |
4088 | ||
4fe9467d ID |
4089 | if (intel_crtc->config.has_pch_encoder) { |
4090 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); | |
4091 | dev_priv->display.fdi_link_train(crtc); | |
4092 | } | |
4093 | ||
1f544388 | 4094 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 4095 | |
b074cec8 | 4096 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
4097 | |
4098 | /* | |
4099 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4100 | * clocks enabled | |
4101 | */ | |
4102 | intel_crtc_load_lut(crtc); | |
4103 | ||
1f544388 | 4104 | intel_ddi_set_pipe_settings(crtc); |
8228c251 | 4105 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 4106 | |
f37fcc2a | 4107 | intel_update_watermarks(crtc); |
e1fdc473 | 4108 | intel_enable_pipe(intel_crtc); |
42db64ef | 4109 | |
5bfe2ac0 | 4110 | if (intel_crtc->config.has_pch_encoder) |
1507e5bd | 4111 | lpt_pch_enable(crtc); |
4f771f10 | 4112 | |
0e32b39c DA |
4113 | if (intel_crtc->config.dp_encoder_is_mst) |
4114 | intel_ddi_set_vc_payload_alloc(crtc, true); | |
4115 | ||
8807e55b | 4116 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 4117 | encoder->enable(encoder); |
8807e55b JN |
4118 | intel_opregion_notify_encoder(encoder, true); |
4119 | } | |
4f771f10 | 4120 | |
e4916946 PZ |
4121 | /* If we change the relative order between pipe/planes enabling, we need |
4122 | * to change the workaround. */ | |
4123 | haswell_mode_set_planes_workaround(intel_crtc); | |
d3eedb1a | 4124 | intel_crtc_enable_planes(crtc); |
4f771f10 PZ |
4125 | } |
4126 | ||
3f8dce3a DV |
4127 | static void ironlake_pfit_disable(struct intel_crtc *crtc) |
4128 | { | |
4129 | struct drm_device *dev = crtc->base.dev; | |
4130 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4131 | int pipe = crtc->pipe; | |
4132 | ||
4133 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
4134 | * it's in use. The hw state code will make sure we get this right. */ | |
fd4daa9c | 4135 | if (crtc->config.pch_pfit.enabled) { |
3f8dce3a DV |
4136 | I915_WRITE(PF_CTL(pipe), 0); |
4137 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
4138 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
4139 | } | |
4140 | } | |
4141 | ||
6be4a607 JB |
4142 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
4143 | { | |
4144 | struct drm_device *dev = crtc->dev; | |
4145 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4146 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4147 | struct intel_encoder *encoder; |
6be4a607 | 4148 | int pipe = intel_crtc->pipe; |
5eddb70b | 4149 | u32 reg, temp; |
b52eb4dc | 4150 | |
f7abfe8b CW |
4151 | if (!intel_crtc->active) |
4152 | return; | |
4153 | ||
d3eedb1a | 4154 | intel_crtc_disable_planes(crtc); |
a5c4d7bc | 4155 | |
ea9d758d DV |
4156 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4157 | encoder->disable(encoder); | |
4158 | ||
d925c59a DV |
4159 | if (intel_crtc->config.has_pch_encoder) |
4160 | intel_set_pch_fifo_underrun_reporting(dev, pipe, false); | |
4161 | ||
b24e7179 | 4162 | intel_disable_pipe(dev_priv, pipe); |
32f9d658 | 4163 | |
0e32b39c DA |
4164 | if (intel_crtc->config.dp_encoder_is_mst) |
4165 | intel_ddi_set_vc_payload_alloc(crtc, false); | |
4166 | ||
3f8dce3a | 4167 | ironlake_pfit_disable(intel_crtc); |
2c07245f | 4168 | |
bf49ec8c DV |
4169 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4170 | if (encoder->post_disable) | |
4171 | encoder->post_disable(encoder); | |
2c07245f | 4172 | |
d925c59a DV |
4173 | if (intel_crtc->config.has_pch_encoder) { |
4174 | ironlake_fdi_disable(crtc); | |
913d8d11 | 4175 | |
d925c59a DV |
4176 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
4177 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); | |
6be4a607 | 4178 | |
d925c59a DV |
4179 | if (HAS_PCH_CPT(dev)) { |
4180 | /* disable TRANS_DP_CTL */ | |
4181 | reg = TRANS_DP_CTL(pipe); | |
4182 | temp = I915_READ(reg); | |
4183 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
4184 | TRANS_DP_PORT_SEL_MASK); | |
4185 | temp |= TRANS_DP_PORT_SEL_NONE; | |
4186 | I915_WRITE(reg, temp); | |
4187 | ||
4188 | /* disable DPLL_SEL */ | |
4189 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 4190 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 4191 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 4192 | } |
e3421a18 | 4193 | |
d925c59a | 4194 | /* disable PCH DPLL */ |
e72f9fbf | 4195 | intel_disable_shared_dpll(intel_crtc); |
8db9d77b | 4196 | |
d925c59a DV |
4197 | ironlake_fdi_pll_disable(intel_crtc); |
4198 | } | |
6b383a7f | 4199 | |
f7abfe8b | 4200 | intel_crtc->active = false; |
46ba614c | 4201 | intel_update_watermarks(crtc); |
d1ebd816 BW |
4202 | |
4203 | mutex_lock(&dev->struct_mutex); | |
6b383a7f | 4204 | intel_update_fbc(dev); |
d1ebd816 | 4205 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 4206 | } |
1b3c7a47 | 4207 | |
4f771f10 | 4208 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 4209 | { |
4f771f10 PZ |
4210 | struct drm_device *dev = crtc->dev; |
4211 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 4212 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 PZ |
4213 | struct intel_encoder *encoder; |
4214 | int pipe = intel_crtc->pipe; | |
3b117c8f | 4215 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
ee7b9f93 | 4216 | |
4f771f10 PZ |
4217 | if (!intel_crtc->active) |
4218 | return; | |
4219 | ||
d3eedb1a | 4220 | intel_crtc_disable_planes(crtc); |
dda9a66a | 4221 | |
8807e55b JN |
4222 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4223 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 4224 | encoder->disable(encoder); |
8807e55b | 4225 | } |
4f771f10 | 4226 | |
8664281b PZ |
4227 | if (intel_crtc->config.has_pch_encoder) |
4228 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false); | |
4f771f10 PZ |
4229 | intel_disable_pipe(dev_priv, pipe); |
4230 | ||
ad80a810 | 4231 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 4232 | |
3f8dce3a | 4233 | ironlake_pfit_disable(intel_crtc); |
4f771f10 | 4234 | |
1f544388 | 4235 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 4236 | |
88adfff1 | 4237 | if (intel_crtc->config.has_pch_encoder) { |
ab4d966c | 4238 | lpt_disable_pch_transcoder(dev_priv); |
8664281b | 4239 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); |
1ad960f2 | 4240 | intel_ddi_fdi_disable(crtc); |
83616634 | 4241 | } |
4f771f10 | 4242 | |
97b040aa ID |
4243 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4244 | if (encoder->post_disable) | |
4245 | encoder->post_disable(encoder); | |
4246 | ||
4f771f10 | 4247 | intel_crtc->active = false; |
46ba614c | 4248 | intel_update_watermarks(crtc); |
4f771f10 PZ |
4249 | |
4250 | mutex_lock(&dev->struct_mutex); | |
4251 | intel_update_fbc(dev); | |
4252 | mutex_unlock(&dev->struct_mutex); | |
df8ad70c DV |
4253 | |
4254 | if (intel_crtc_to_shared_dpll(intel_crtc)) | |
4255 | intel_disable_shared_dpll(intel_crtc); | |
4f771f10 PZ |
4256 | } |
4257 | ||
ee7b9f93 JB |
4258 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
4259 | { | |
4260 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
e72f9fbf | 4261 | intel_put_shared_dpll(intel_crtc); |
ee7b9f93 JB |
4262 | } |
4263 | ||
6441ab5f | 4264 | |
2dd24552 JB |
4265 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
4266 | { | |
4267 | struct drm_device *dev = crtc->base.dev; | |
4268 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4269 | struct intel_crtc_config *pipe_config = &crtc->config; | |
4270 | ||
328d8e82 | 4271 | if (!crtc->config.gmch_pfit.control) |
2dd24552 JB |
4272 | return; |
4273 | ||
2dd24552 | 4274 | /* |
c0b03411 DV |
4275 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
4276 | * according to register description and PRM. | |
2dd24552 | 4277 | */ |
c0b03411 DV |
4278 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
4279 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 4280 | |
b074cec8 JB |
4281 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
4282 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
4283 | |
4284 | /* Border color in case we don't scale up to the full screen. Black by | |
4285 | * default, change to something else for debugging. */ | |
4286 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
4287 | } |
4288 | ||
d05410f9 DA |
4289 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
4290 | { | |
4291 | switch (port) { | |
4292 | case PORT_A: | |
4293 | return POWER_DOMAIN_PORT_DDI_A_4_LANES; | |
4294 | case PORT_B: | |
4295 | return POWER_DOMAIN_PORT_DDI_B_4_LANES; | |
4296 | case PORT_C: | |
4297 | return POWER_DOMAIN_PORT_DDI_C_4_LANES; | |
4298 | case PORT_D: | |
4299 | return POWER_DOMAIN_PORT_DDI_D_4_LANES; | |
4300 | default: | |
4301 | WARN_ON_ONCE(1); | |
4302 | return POWER_DOMAIN_PORT_OTHER; | |
4303 | } | |
4304 | } | |
4305 | ||
77d22dca ID |
4306 | #define for_each_power_domain(domain, mask) \ |
4307 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
4308 | if ((1 << (domain)) & (mask)) | |
4309 | ||
319be8ae ID |
4310 | enum intel_display_power_domain |
4311 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
4312 | { | |
4313 | struct drm_device *dev = intel_encoder->base.dev; | |
4314 | struct intel_digital_port *intel_dig_port; | |
4315 | ||
4316 | switch (intel_encoder->type) { | |
4317 | case INTEL_OUTPUT_UNKNOWN: | |
4318 | /* Only DDI platforms should ever use this output type */ | |
4319 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
4320 | case INTEL_OUTPUT_DISPLAYPORT: | |
4321 | case INTEL_OUTPUT_HDMI: | |
4322 | case INTEL_OUTPUT_EDP: | |
4323 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 4324 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
4325 | case INTEL_OUTPUT_DP_MST: |
4326 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
4327 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
4328 | case INTEL_OUTPUT_ANALOG: |
4329 | return POWER_DOMAIN_PORT_CRT; | |
4330 | case INTEL_OUTPUT_DSI: | |
4331 | return POWER_DOMAIN_PORT_DSI; | |
4332 | default: | |
4333 | return POWER_DOMAIN_PORT_OTHER; | |
4334 | } | |
4335 | } | |
4336 | ||
4337 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) | |
77d22dca | 4338 | { |
319be8ae ID |
4339 | struct drm_device *dev = crtc->dev; |
4340 | struct intel_encoder *intel_encoder; | |
4341 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4342 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca ID |
4343 | unsigned long mask; |
4344 | enum transcoder transcoder; | |
4345 | ||
4346 | transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); | |
4347 | ||
4348 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); | |
4349 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
fabf6e51 DV |
4350 | if (intel_crtc->config.pch_pfit.enabled || |
4351 | intel_crtc->config.pch_pfit.force_thru) | |
77d22dca ID |
4352 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
4353 | ||
319be8ae ID |
4354 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
4355 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); | |
4356 | ||
77d22dca ID |
4357 | return mask; |
4358 | } | |
4359 | ||
4360 | void intel_display_set_init_power(struct drm_i915_private *dev_priv, | |
4361 | bool enable) | |
4362 | { | |
4363 | if (dev_priv->power_domains.init_power_on == enable) | |
4364 | return; | |
4365 | ||
4366 | if (enable) | |
4367 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); | |
4368 | else | |
4369 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); | |
4370 | ||
4371 | dev_priv->power_domains.init_power_on = enable; | |
4372 | } | |
4373 | ||
4374 | static void modeset_update_crtc_power_domains(struct drm_device *dev) | |
4375 | { | |
4376 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4377 | unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }; | |
4378 | struct intel_crtc *crtc; | |
4379 | ||
4380 | /* | |
4381 | * First get all needed power domains, then put all unneeded, to avoid | |
4382 | * any unnecessary toggling of the power wells. | |
4383 | */ | |
d3fcc808 | 4384 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
4385 | enum intel_display_power_domain domain; |
4386 | ||
4387 | if (!crtc->base.enabled) | |
4388 | continue; | |
4389 | ||
319be8ae | 4390 | pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base); |
77d22dca ID |
4391 | |
4392 | for_each_power_domain(domain, pipe_domains[crtc->pipe]) | |
4393 | intel_display_power_get(dev_priv, domain); | |
4394 | } | |
4395 | ||
d3fcc808 | 4396 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
4397 | enum intel_display_power_domain domain; |
4398 | ||
4399 | for_each_power_domain(domain, crtc->enabled_power_domains) | |
4400 | intel_display_power_put(dev_priv, domain); | |
4401 | ||
4402 | crtc->enabled_power_domains = pipe_domains[crtc->pipe]; | |
4403 | } | |
4404 | ||
4405 | intel_display_set_init_power(dev_priv, false); | |
4406 | } | |
4407 | ||
dfcab17e | 4408 | /* returns HPLL frequency in kHz */ |
f8bf63fd | 4409 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) |
30a970c6 | 4410 | { |
586f49dc | 4411 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
30a970c6 | 4412 | |
586f49dc JB |
4413 | /* Obtain SKU information */ |
4414 | mutex_lock(&dev_priv->dpio_lock); | |
4415 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
4416 | CCK_FUSE_HPLL_FREQ_MASK; | |
4417 | mutex_unlock(&dev_priv->dpio_lock); | |
30a970c6 | 4418 | |
dfcab17e | 4419 | return vco_freq[hpll_freq] * 1000; |
30a970c6 JB |
4420 | } |
4421 | ||
f8bf63fd VS |
4422 | static void vlv_update_cdclk(struct drm_device *dev) |
4423 | { | |
4424 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4425 | ||
4426 | dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev); | |
4427 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz", | |
4428 | dev_priv->vlv_cdclk_freq); | |
4429 | ||
4430 | /* | |
4431 | * Program the gmbus_freq based on the cdclk frequency. | |
4432 | * BSpec erroneously claims we should aim for 4MHz, but | |
4433 | * in fact 1MHz is the correct frequency. | |
4434 | */ | |
4435 | I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq); | |
4436 | } | |
4437 | ||
30a970c6 JB |
4438 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
4439 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
4440 | { | |
4441 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4442 | u32 val, cmd; | |
4443 | ||
d197b7d3 | 4444 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq); |
d60c4473 | 4445 | |
dfcab17e | 4446 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 4447 | cmd = 2; |
dfcab17e | 4448 | else if (cdclk == 266667) |
30a970c6 JB |
4449 | cmd = 1; |
4450 | else | |
4451 | cmd = 0; | |
4452 | ||
4453 | mutex_lock(&dev_priv->rps.hw_lock); | |
4454 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
4455 | val &= ~DSPFREQGUAR_MASK; | |
4456 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
4457 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
4458 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
4459 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
4460 | 50)) { | |
4461 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
4462 | } | |
4463 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4464 | ||
dfcab17e | 4465 | if (cdclk == 400000) { |
30a970c6 JB |
4466 | u32 divider, vco; |
4467 | ||
4468 | vco = valleyview_get_vco(dev_priv); | |
dfcab17e | 4469 | divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1; |
30a970c6 JB |
4470 | |
4471 | mutex_lock(&dev_priv->dpio_lock); | |
4472 | /* adjust cdclk divider */ | |
4473 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
9cf33db5 | 4474 | val &= ~DISPLAY_FREQUENCY_VALUES; |
30a970c6 JB |
4475 | val |= divider; |
4476 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
4477 | |
4478 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
4479 | DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), | |
4480 | 50)) | |
4481 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
4482 | mutex_unlock(&dev_priv->dpio_lock); |
4483 | } | |
4484 | ||
4485 | mutex_lock(&dev_priv->dpio_lock); | |
4486 | /* adjust self-refresh exit latency value */ | |
4487 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
4488 | val &= ~0x7f; | |
4489 | ||
4490 | /* | |
4491 | * For high bandwidth configs, we set a higher latency in the bunit | |
4492 | * so that the core display fetch happens in time to avoid underruns. | |
4493 | */ | |
dfcab17e | 4494 | if (cdclk == 400000) |
30a970c6 JB |
4495 | val |= 4500 / 250; /* 4.5 usec */ |
4496 | else | |
4497 | val |= 3000 / 250; /* 3.0 usec */ | |
4498 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
4499 | mutex_unlock(&dev_priv->dpio_lock); | |
4500 | ||
f8bf63fd | 4501 | vlv_update_cdclk(dev); |
30a970c6 JB |
4502 | } |
4503 | ||
383c5a6a VS |
4504 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
4505 | { | |
4506 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4507 | u32 val, cmd; | |
4508 | ||
4509 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq); | |
4510 | ||
4511 | switch (cdclk) { | |
4512 | case 400000: | |
4513 | cmd = 3; | |
4514 | break; | |
4515 | case 333333: | |
4516 | case 320000: | |
4517 | cmd = 2; | |
4518 | break; | |
4519 | case 266667: | |
4520 | cmd = 1; | |
4521 | break; | |
4522 | case 200000: | |
4523 | cmd = 0; | |
4524 | break; | |
4525 | default: | |
4526 | WARN_ON(1); | |
4527 | return; | |
4528 | } | |
4529 | ||
4530 | mutex_lock(&dev_priv->rps.hw_lock); | |
4531 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
4532 | val &= ~DSPFREQGUAR_MASK_CHV; | |
4533 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
4534 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
4535 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
4536 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
4537 | 50)) { | |
4538 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
4539 | } | |
4540 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4541 | ||
4542 | vlv_update_cdclk(dev); | |
4543 | } | |
4544 | ||
30a970c6 JB |
4545 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
4546 | int max_pixclk) | |
4547 | { | |
29dc7ef3 VS |
4548 | int vco = valleyview_get_vco(dev_priv); |
4549 | int freq_320 = (vco << 1) % 320000 != 0 ? 333333 : 320000; | |
4550 | ||
d49a340d VS |
4551 | /* FIXME: Punit isn't quite ready yet */ |
4552 | if (IS_CHERRYVIEW(dev_priv->dev)) | |
4553 | return 400000; | |
4554 | ||
30a970c6 JB |
4555 | /* |
4556 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
4557 | * 200MHz | |
4558 | * 267MHz | |
29dc7ef3 | 4559 | * 320/333MHz (depends on HPLL freq) |
30a970c6 JB |
4560 | * 400MHz |
4561 | * So we check to see whether we're above 90% of the lower bin and | |
4562 | * adjust if needed. | |
e37c67a1 VS |
4563 | * |
4564 | * We seem to get an unstable or solid color picture at 200MHz. | |
4565 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
4566 | * are off. | |
30a970c6 | 4567 | */ |
29dc7ef3 | 4568 | if (max_pixclk > freq_320*9/10) |
dfcab17e VS |
4569 | return 400000; |
4570 | else if (max_pixclk > 266667*9/10) | |
29dc7ef3 | 4571 | return freq_320; |
e37c67a1 | 4572 | else if (max_pixclk > 0) |
dfcab17e | 4573 | return 266667; |
e37c67a1 VS |
4574 | else |
4575 | return 200000; | |
30a970c6 JB |
4576 | } |
4577 | ||
2f2d7aa1 VS |
4578 | /* compute the max pixel clock for new configuration */ |
4579 | static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv) | |
30a970c6 JB |
4580 | { |
4581 | struct drm_device *dev = dev_priv->dev; | |
4582 | struct intel_crtc *intel_crtc; | |
4583 | int max_pixclk = 0; | |
4584 | ||
d3fcc808 | 4585 | for_each_intel_crtc(dev, intel_crtc) { |
2f2d7aa1 | 4586 | if (intel_crtc->new_enabled) |
30a970c6 | 4587 | max_pixclk = max(max_pixclk, |
2f2d7aa1 | 4588 | intel_crtc->new_config->adjusted_mode.crtc_clock); |
30a970c6 JB |
4589 | } |
4590 | ||
4591 | return max_pixclk; | |
4592 | } | |
4593 | ||
4594 | static void valleyview_modeset_global_pipes(struct drm_device *dev, | |
2f2d7aa1 | 4595 | unsigned *prepare_pipes) |
30a970c6 JB |
4596 | { |
4597 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4598 | struct intel_crtc *intel_crtc; | |
2f2d7aa1 | 4599 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
30a970c6 | 4600 | |
d60c4473 ID |
4601 | if (valleyview_calc_cdclk(dev_priv, max_pixclk) == |
4602 | dev_priv->vlv_cdclk_freq) | |
30a970c6 JB |
4603 | return; |
4604 | ||
2f2d7aa1 | 4605 | /* disable/enable all currently active pipes while we change cdclk */ |
d3fcc808 | 4606 | for_each_intel_crtc(dev, intel_crtc) |
30a970c6 JB |
4607 | if (intel_crtc->base.enabled) |
4608 | *prepare_pipes |= (1 << intel_crtc->pipe); | |
4609 | } | |
4610 | ||
4611 | static void valleyview_modeset_global_resources(struct drm_device *dev) | |
4612 | { | |
4613 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2f2d7aa1 | 4614 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
30a970c6 JB |
4615 | int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); |
4616 | ||
383c5a6a VS |
4617 | if (req_cdclk != dev_priv->vlv_cdclk_freq) { |
4618 | if (IS_CHERRYVIEW(dev)) | |
4619 | cherryview_set_cdclk(dev, req_cdclk); | |
4620 | else | |
4621 | valleyview_set_cdclk(dev, req_cdclk); | |
4622 | } | |
4623 | ||
77961eb9 | 4624 | modeset_update_crtc_power_domains(dev); |
30a970c6 JB |
4625 | } |
4626 | ||
89b667f8 JB |
4627 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
4628 | { | |
4629 | struct drm_device *dev = crtc->dev; | |
5b18e57c | 4630 | struct drm_i915_private *dev_priv = dev->dev_private; |
89b667f8 JB |
4631 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4632 | struct intel_encoder *encoder; | |
4633 | int pipe = intel_crtc->pipe; | |
5b18e57c | 4634 | int plane = intel_crtc->plane; |
23538ef1 | 4635 | bool is_dsi; |
5b18e57c | 4636 | u32 dspcntr; |
89b667f8 JB |
4637 | |
4638 | WARN_ON(!crtc->enabled); | |
4639 | ||
4640 | if (intel_crtc->active) | |
4641 | return; | |
4642 | ||
8525a235 SK |
4643 | is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI); |
4644 | ||
4645 | if (!is_dsi && !IS_CHERRYVIEW(dev)) | |
4646 | vlv_prepare_pll(intel_crtc); | |
bdd4b6a6 | 4647 | |
5b18e57c DV |
4648 | /* Set up the display plane register */ |
4649 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
4650 | ||
4651 | if (intel_crtc->config.has_dp_encoder) | |
4652 | intel_dp_set_m_n(intel_crtc); | |
4653 | ||
4654 | intel_set_pipe_timings(intel_crtc); | |
4655 | ||
4656 | /* pipesrc and dspsize control the size that is scaled from, | |
4657 | * which should always be the user's requested size. | |
4658 | */ | |
4659 | I915_WRITE(DSPSIZE(plane), | |
4660 | ((intel_crtc->config.pipe_src_h - 1) << 16) | | |
4661 | (intel_crtc->config.pipe_src_w - 1)); | |
4662 | I915_WRITE(DSPPOS(plane), 0); | |
4663 | ||
4664 | i9xx_set_pipeconf(intel_crtc); | |
4665 | ||
4666 | I915_WRITE(DSPCNTR(plane), dspcntr); | |
4667 | POSTING_READ(DSPCNTR(plane)); | |
4668 | ||
4669 | dev_priv->display.update_primary_plane(crtc, crtc->primary->fb, | |
4670 | crtc->x, crtc->y); | |
4671 | ||
89b667f8 | 4672 | intel_crtc->active = true; |
89b667f8 | 4673 | |
4a3436e8 VS |
4674 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
4675 | ||
89b667f8 JB |
4676 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4677 | if (encoder->pre_pll_enable) | |
4678 | encoder->pre_pll_enable(encoder); | |
4679 | ||
9d556c99 CML |
4680 | if (!is_dsi) { |
4681 | if (IS_CHERRYVIEW(dev)) | |
4682 | chv_enable_pll(intel_crtc); | |
4683 | else | |
4684 | vlv_enable_pll(intel_crtc); | |
4685 | } | |
89b667f8 JB |
4686 | |
4687 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
4688 | if (encoder->pre_enable) | |
4689 | encoder->pre_enable(encoder); | |
4690 | ||
2dd24552 JB |
4691 | i9xx_pfit_enable(intel_crtc); |
4692 | ||
63cbb074 VS |
4693 | intel_crtc_load_lut(crtc); |
4694 | ||
f37fcc2a | 4695 | intel_update_watermarks(crtc); |
e1fdc473 | 4696 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 4697 | |
5004945f JN |
4698 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4699 | encoder->enable(encoder); | |
9ab0460b VS |
4700 | |
4701 | intel_crtc_enable_planes(crtc); | |
d40d9187 | 4702 | |
56b80e1f VS |
4703 | /* Underruns don't raise interrupts, so check manually. */ |
4704 | i9xx_check_fifo_underruns(dev); | |
89b667f8 JB |
4705 | } |
4706 | ||
f13c2ef3 DV |
4707 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
4708 | { | |
4709 | struct drm_device *dev = crtc->base.dev; | |
4710 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4711 | ||
4712 | I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0); | |
4713 | I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1); | |
4714 | } | |
4715 | ||
0b8765c6 | 4716 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
4717 | { |
4718 | struct drm_device *dev = crtc->dev; | |
5b18e57c | 4719 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 4720 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 4721 | struct intel_encoder *encoder; |
79e53945 | 4722 | int pipe = intel_crtc->pipe; |
5b18e57c DV |
4723 | int plane = intel_crtc->plane; |
4724 | u32 dspcntr; | |
79e53945 | 4725 | |
08a48469 DV |
4726 | WARN_ON(!crtc->enabled); |
4727 | ||
f7abfe8b CW |
4728 | if (intel_crtc->active) |
4729 | return; | |
4730 | ||
f13c2ef3 DV |
4731 | i9xx_set_pll_dividers(intel_crtc); |
4732 | ||
5b18e57c DV |
4733 | /* Set up the display plane register */ |
4734 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
4735 | ||
4736 | if (pipe == 0) | |
4737 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; | |
4738 | else | |
4739 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
4740 | ||
4741 | if (intel_crtc->config.has_dp_encoder) | |
4742 | intel_dp_set_m_n(intel_crtc); | |
4743 | ||
4744 | intel_set_pipe_timings(intel_crtc); | |
4745 | ||
4746 | /* pipesrc and dspsize control the size that is scaled from, | |
4747 | * which should always be the user's requested size. | |
4748 | */ | |
4749 | I915_WRITE(DSPSIZE(plane), | |
4750 | ((intel_crtc->config.pipe_src_h - 1) << 16) | | |
4751 | (intel_crtc->config.pipe_src_w - 1)); | |
4752 | I915_WRITE(DSPPOS(plane), 0); | |
4753 | ||
4754 | i9xx_set_pipeconf(intel_crtc); | |
4755 | ||
4756 | I915_WRITE(DSPCNTR(plane), dspcntr); | |
4757 | POSTING_READ(DSPCNTR(plane)); | |
4758 | ||
4759 | dev_priv->display.update_primary_plane(crtc, crtc->primary->fb, | |
4760 | crtc->x, crtc->y); | |
4761 | ||
f7abfe8b | 4762 | intel_crtc->active = true; |
6b383a7f | 4763 | |
4a3436e8 VS |
4764 | if (!IS_GEN2(dev)) |
4765 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
4766 | ||
9d6d9f19 MK |
4767 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4768 | if (encoder->pre_enable) | |
4769 | encoder->pre_enable(encoder); | |
4770 | ||
f6736a1a DV |
4771 | i9xx_enable_pll(intel_crtc); |
4772 | ||
2dd24552 JB |
4773 | i9xx_pfit_enable(intel_crtc); |
4774 | ||
63cbb074 VS |
4775 | intel_crtc_load_lut(crtc); |
4776 | ||
f37fcc2a | 4777 | intel_update_watermarks(crtc); |
e1fdc473 | 4778 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 4779 | |
fa5c73b1 DV |
4780 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4781 | encoder->enable(encoder); | |
9ab0460b VS |
4782 | |
4783 | intel_crtc_enable_planes(crtc); | |
d40d9187 | 4784 | |
4a3436e8 VS |
4785 | /* |
4786 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4787 | * So don't enable underrun reporting before at least some planes | |
4788 | * are enabled. | |
4789 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4790 | * but leave the pipe running. | |
4791 | */ | |
4792 | if (IS_GEN2(dev)) | |
4793 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
4794 | ||
56b80e1f VS |
4795 | /* Underruns don't raise interrupts, so check manually. */ |
4796 | i9xx_check_fifo_underruns(dev); | |
0b8765c6 | 4797 | } |
79e53945 | 4798 | |
87476d63 DV |
4799 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
4800 | { | |
4801 | struct drm_device *dev = crtc->base.dev; | |
4802 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 4803 | |
328d8e82 DV |
4804 | if (!crtc->config.gmch_pfit.control) |
4805 | return; | |
87476d63 | 4806 | |
328d8e82 | 4807 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 4808 | |
328d8e82 DV |
4809 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
4810 | I915_READ(PFIT_CONTROL)); | |
4811 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
4812 | } |
4813 | ||
0b8765c6 JB |
4814 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
4815 | { | |
4816 | struct drm_device *dev = crtc->dev; | |
4817 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4818 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4819 | struct intel_encoder *encoder; |
0b8765c6 | 4820 | int pipe = intel_crtc->pipe; |
ef9c3aee | 4821 | |
f7abfe8b CW |
4822 | if (!intel_crtc->active) |
4823 | return; | |
4824 | ||
4a3436e8 VS |
4825 | /* |
4826 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4827 | * So diasble underrun reporting before all the planes get disabled. | |
4828 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4829 | * but leave the pipe running. | |
4830 | */ | |
4831 | if (IS_GEN2(dev)) | |
4832 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false); | |
4833 | ||
564ed191 ID |
4834 | /* |
4835 | * Vblank time updates from the shadow to live plane control register | |
4836 | * are blocked if the memory self-refresh mode is active at that | |
4837 | * moment. So to make sure the plane gets truly disabled, disable | |
4838 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4839 | * will be checked/applied by the HW only at the next frame start | |
4840 | * event which is after the vblank start event, so we need to have a | |
4841 | * wait-for-vblank between disabling the plane and the pipe. | |
4842 | */ | |
4843 | intel_set_memory_cxsr(dev_priv, false); | |
9ab0460b VS |
4844 | intel_crtc_disable_planes(crtc); |
4845 | ||
ea9d758d DV |
4846 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4847 | encoder->disable(encoder); | |
4848 | ||
6304cd91 VS |
4849 | /* |
4850 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
4851 | * wait for planes to fully turn off before disabling the pipe. | |
564ed191 ID |
4852 | * We also need to wait on all gmch platforms because of the |
4853 | * self-refresh mode constraint explained above. | |
6304cd91 | 4854 | */ |
564ed191 | 4855 | intel_wait_for_vblank(dev, pipe); |
6304cd91 | 4856 | |
b24e7179 | 4857 | intel_disable_pipe(dev_priv, pipe); |
24a1f16d | 4858 | |
87476d63 | 4859 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 4860 | |
89b667f8 JB |
4861 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4862 | if (encoder->post_disable) | |
4863 | encoder->post_disable(encoder); | |
4864 | ||
076ed3b2 CML |
4865 | if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) { |
4866 | if (IS_CHERRYVIEW(dev)) | |
4867 | chv_disable_pll(dev_priv, pipe); | |
4868 | else if (IS_VALLEYVIEW(dev)) | |
4869 | vlv_disable_pll(dev_priv, pipe); | |
4870 | else | |
4871 | i9xx_disable_pll(dev_priv, pipe); | |
4872 | } | |
0b8765c6 | 4873 | |
4a3436e8 VS |
4874 | if (!IS_GEN2(dev)) |
4875 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false); | |
4876 | ||
f7abfe8b | 4877 | intel_crtc->active = false; |
46ba614c | 4878 | intel_update_watermarks(crtc); |
f37fcc2a | 4879 | |
efa9624e | 4880 | mutex_lock(&dev->struct_mutex); |
6b383a7f | 4881 | intel_update_fbc(dev); |
efa9624e | 4882 | mutex_unlock(&dev->struct_mutex); |
0b8765c6 JB |
4883 | } |
4884 | ||
ee7b9f93 JB |
4885 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
4886 | { | |
4887 | } | |
4888 | ||
976f8a20 DV |
4889 | static void intel_crtc_update_sarea(struct drm_crtc *crtc, |
4890 | bool enabled) | |
2c07245f ZW |
4891 | { |
4892 | struct drm_device *dev = crtc->dev; | |
4893 | struct drm_i915_master_private *master_priv; | |
4894 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4895 | int pipe = intel_crtc->pipe; | |
79e53945 JB |
4896 | |
4897 | if (!dev->primary->master) | |
4898 | return; | |
4899 | ||
4900 | master_priv = dev->primary->master->driver_priv; | |
4901 | if (!master_priv->sarea_priv) | |
4902 | return; | |
4903 | ||
79e53945 JB |
4904 | switch (pipe) { |
4905 | case 0: | |
4906 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; | |
4907 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; | |
4908 | break; | |
4909 | case 1: | |
4910 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; | |
4911 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; | |
4912 | break; | |
4913 | default: | |
9db4a9c7 | 4914 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
79e53945 JB |
4915 | break; |
4916 | } | |
79e53945 JB |
4917 | } |
4918 | ||
b04c5bd6 BF |
4919 | /* Master function to enable/disable CRTC and corresponding power wells */ |
4920 | void intel_crtc_control(struct drm_crtc *crtc, bool enable) | |
976f8a20 DV |
4921 | { |
4922 | struct drm_device *dev = crtc->dev; | |
4923 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0e572fe7 | 4924 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
0e572fe7 DV |
4925 | enum intel_display_power_domain domain; |
4926 | unsigned long domains; | |
976f8a20 | 4927 | |
0e572fe7 DV |
4928 | if (enable) { |
4929 | if (!intel_crtc->active) { | |
e1e9fb84 DV |
4930 | domains = get_crtc_power_domains(crtc); |
4931 | for_each_power_domain(domain, domains) | |
4932 | intel_display_power_get(dev_priv, domain); | |
4933 | intel_crtc->enabled_power_domains = domains; | |
0e572fe7 DV |
4934 | |
4935 | dev_priv->display.crtc_enable(crtc); | |
4936 | } | |
4937 | } else { | |
4938 | if (intel_crtc->active) { | |
4939 | dev_priv->display.crtc_disable(crtc); | |
4940 | ||
e1e9fb84 DV |
4941 | domains = intel_crtc->enabled_power_domains; |
4942 | for_each_power_domain(domain, domains) | |
4943 | intel_display_power_put(dev_priv, domain); | |
4944 | intel_crtc->enabled_power_domains = 0; | |
0e572fe7 DV |
4945 | } |
4946 | } | |
b04c5bd6 BF |
4947 | } |
4948 | ||
4949 | /** | |
4950 | * Sets the power management mode of the pipe and plane. | |
4951 | */ | |
4952 | void intel_crtc_update_dpms(struct drm_crtc *crtc) | |
4953 | { | |
4954 | struct drm_device *dev = crtc->dev; | |
4955 | struct intel_encoder *intel_encoder; | |
4956 | bool enable = false; | |
4957 | ||
4958 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) | |
4959 | enable |= intel_encoder->connectors_active; | |
4960 | ||
4961 | intel_crtc_control(crtc, enable); | |
976f8a20 DV |
4962 | |
4963 | intel_crtc_update_sarea(crtc, enable); | |
4964 | } | |
4965 | ||
cdd59983 CW |
4966 | static void intel_crtc_disable(struct drm_crtc *crtc) |
4967 | { | |
cdd59983 | 4968 | struct drm_device *dev = crtc->dev; |
976f8a20 | 4969 | struct drm_connector *connector; |
ee7b9f93 | 4970 | struct drm_i915_private *dev_priv = dev->dev_private; |
2ff8fde1 | 4971 | struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb); |
a071fa00 | 4972 | enum pipe pipe = to_intel_crtc(crtc)->pipe; |
cdd59983 | 4973 | |
976f8a20 DV |
4974 | /* crtc should still be enabled when we disable it. */ |
4975 | WARN_ON(!crtc->enabled); | |
4976 | ||
4977 | dev_priv->display.crtc_disable(crtc); | |
4978 | intel_crtc_update_sarea(crtc, false); | |
ee7b9f93 JB |
4979 | dev_priv->display.off(crtc); |
4980 | ||
f4510a27 | 4981 | if (crtc->primary->fb) { |
cdd59983 | 4982 | mutex_lock(&dev->struct_mutex); |
a071fa00 DV |
4983 | intel_unpin_fb_obj(old_obj); |
4984 | i915_gem_track_fb(old_obj, NULL, | |
4985 | INTEL_FRONTBUFFER_PRIMARY(pipe)); | |
cdd59983 | 4986 | mutex_unlock(&dev->struct_mutex); |
f4510a27 | 4987 | crtc->primary->fb = NULL; |
976f8a20 DV |
4988 | } |
4989 | ||
4990 | /* Update computed state. */ | |
4991 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4992 | if (!connector->encoder || !connector->encoder->crtc) | |
4993 | continue; | |
4994 | ||
4995 | if (connector->encoder->crtc != crtc) | |
4996 | continue; | |
4997 | ||
4998 | connector->dpms = DRM_MODE_DPMS_OFF; | |
4999 | to_intel_encoder(connector->encoder)->connectors_active = false; | |
cdd59983 CW |
5000 | } |
5001 | } | |
5002 | ||
ea5b213a | 5003 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 5004 | { |
4ef69c7a | 5005 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 5006 | |
ea5b213a CW |
5007 | drm_encoder_cleanup(encoder); |
5008 | kfree(intel_encoder); | |
7e7d76c3 JB |
5009 | } |
5010 | ||
9237329d | 5011 | /* Simple dpms helper for encoders with just one connector, no cloning and only |
5ab432ef DV |
5012 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
5013 | * state of the entire output pipe. */ | |
9237329d | 5014 | static void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
7e7d76c3 | 5015 | { |
5ab432ef DV |
5016 | if (mode == DRM_MODE_DPMS_ON) { |
5017 | encoder->connectors_active = true; | |
5018 | ||
b2cabb0e | 5019 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef DV |
5020 | } else { |
5021 | encoder->connectors_active = false; | |
5022 | ||
b2cabb0e | 5023 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef | 5024 | } |
79e53945 JB |
5025 | } |
5026 | ||
0a91ca29 DV |
5027 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
5028 | * internal consistency). */ | |
b980514c | 5029 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 5030 | { |
0a91ca29 DV |
5031 | if (connector->get_hw_state(connector)) { |
5032 | struct intel_encoder *encoder = connector->encoder; | |
5033 | struct drm_crtc *crtc; | |
5034 | bool encoder_enabled; | |
5035 | enum pipe pipe; | |
5036 | ||
5037 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
5038 | connector->base.base.id, | |
c23cc417 | 5039 | connector->base.name); |
0a91ca29 | 5040 | |
0e32b39c DA |
5041 | /* there is no real hw state for MST connectors */ |
5042 | if (connector->mst_port) | |
5043 | return; | |
5044 | ||
0a91ca29 DV |
5045 | WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, |
5046 | "wrong connector dpms state\n"); | |
5047 | WARN(connector->base.encoder != &encoder->base, | |
5048 | "active connector not linked to encoder\n"); | |
0a91ca29 | 5049 | |
36cd7444 DA |
5050 | if (encoder) { |
5051 | WARN(!encoder->connectors_active, | |
5052 | "encoder->connectors_active not set\n"); | |
5053 | ||
5054 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); | |
5055 | WARN(!encoder_enabled, "encoder not enabled\n"); | |
5056 | if (WARN_ON(!encoder->base.crtc)) | |
5057 | return; | |
0a91ca29 | 5058 | |
36cd7444 | 5059 | crtc = encoder->base.crtc; |
0a91ca29 | 5060 | |
36cd7444 DA |
5061 | WARN(!crtc->enabled, "crtc not enabled\n"); |
5062 | WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); | |
5063 | WARN(pipe != to_intel_crtc(crtc)->pipe, | |
5064 | "encoder active on the wrong pipe\n"); | |
5065 | } | |
0a91ca29 | 5066 | } |
79e53945 JB |
5067 | } |
5068 | ||
5ab432ef DV |
5069 | /* Even simpler default implementation, if there's really no special case to |
5070 | * consider. */ | |
5071 | void intel_connector_dpms(struct drm_connector *connector, int mode) | |
79e53945 | 5072 | { |
5ab432ef DV |
5073 | /* All the simple cases only support two dpms states. */ |
5074 | if (mode != DRM_MODE_DPMS_ON) | |
5075 | mode = DRM_MODE_DPMS_OFF; | |
d4270e57 | 5076 | |
5ab432ef DV |
5077 | if (mode == connector->dpms) |
5078 | return; | |
5079 | ||
5080 | connector->dpms = mode; | |
5081 | ||
5082 | /* Only need to change hw state when actually enabled */ | |
c9976dcf CW |
5083 | if (connector->encoder) |
5084 | intel_encoder_dpms(to_intel_encoder(connector->encoder), mode); | |
0a91ca29 | 5085 | |
b980514c | 5086 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
5087 | } |
5088 | ||
f0947c37 DV |
5089 | /* Simple connector->get_hw_state implementation for encoders that support only |
5090 | * one connector and no cloning and hence the encoder state determines the state | |
5091 | * of the connector. */ | |
5092 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 5093 | { |
24929352 | 5094 | enum pipe pipe = 0; |
f0947c37 | 5095 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 5096 | |
f0947c37 | 5097 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
5098 | } |
5099 | ||
1857e1da DV |
5100 | static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5101 | struct intel_crtc_config *pipe_config) | |
5102 | { | |
5103 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5104 | struct intel_crtc *pipe_B_crtc = | |
5105 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
5106 | ||
5107 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", | |
5108 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5109 | if (pipe_config->fdi_lanes > 4) { | |
5110 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
5111 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5112 | return false; | |
5113 | } | |
5114 | ||
bafb6553 | 5115 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
5116 | if (pipe_config->fdi_lanes > 2) { |
5117 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
5118 | pipe_config->fdi_lanes); | |
5119 | return false; | |
5120 | } else { | |
5121 | return true; | |
5122 | } | |
5123 | } | |
5124 | ||
5125 | if (INTEL_INFO(dev)->num_pipes == 2) | |
5126 | return true; | |
5127 | ||
5128 | /* Ivybridge 3 pipe is really complicated */ | |
5129 | switch (pipe) { | |
5130 | case PIPE_A: | |
5131 | return true; | |
5132 | case PIPE_B: | |
5133 | if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled && | |
5134 | pipe_config->fdi_lanes > 2) { | |
5135 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
5136 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5137 | return false; | |
5138 | } | |
5139 | return true; | |
5140 | case PIPE_C: | |
1e833f40 | 5141 | if (!pipe_has_enabled_pch(pipe_B_crtc) || |
1857e1da DV |
5142 | pipe_B_crtc->config.fdi_lanes <= 2) { |
5143 | if (pipe_config->fdi_lanes > 2) { | |
5144 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
5145 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5146 | return false; | |
5147 | } | |
5148 | } else { | |
5149 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); | |
5150 | return false; | |
5151 | } | |
5152 | return true; | |
5153 | default: | |
5154 | BUG(); | |
5155 | } | |
5156 | } | |
5157 | ||
e29c22c0 DV |
5158 | #define RETRY 1 |
5159 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5160 | struct intel_crtc_config *pipe_config) | |
877d48d5 | 5161 | { |
1857e1da | 5162 | struct drm_device *dev = intel_crtc->base.dev; |
877d48d5 | 5163 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
ff9a6750 | 5164 | int lane, link_bw, fdi_dotclock; |
e29c22c0 | 5165 | bool setup_ok, needs_recompute = false; |
877d48d5 | 5166 | |
e29c22c0 | 5167 | retry: |
877d48d5 DV |
5168 | /* FDI is a binary signal running at ~2.7GHz, encoding |
5169 | * each output octet as 10 bits. The actual frequency | |
5170 | * is stored as a divider into a 100MHz clock, and the | |
5171 | * mode pixel clock is stored in units of 1KHz. | |
5172 | * Hence the bw of each lane in terms of the mode signal | |
5173 | * is: | |
5174 | */ | |
5175 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
5176 | ||
241bfc38 | 5177 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 5178 | |
2bd89a07 | 5179 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
5180 | pipe_config->pipe_bpp); |
5181 | ||
5182 | pipe_config->fdi_lanes = lane; | |
5183 | ||
2bd89a07 | 5184 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 5185 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 5186 | |
e29c22c0 DV |
5187 | setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
5188 | intel_crtc->pipe, pipe_config); | |
5189 | if (!setup_ok && pipe_config->pipe_bpp > 6*3) { | |
5190 | pipe_config->pipe_bpp -= 2*3; | |
5191 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
5192 | pipe_config->pipe_bpp); | |
5193 | needs_recompute = true; | |
5194 | pipe_config->bw_constrained = true; | |
5195 | ||
5196 | goto retry; | |
5197 | } | |
5198 | ||
5199 | if (needs_recompute) | |
5200 | return RETRY; | |
5201 | ||
5202 | return setup_ok ? 0 : -EINVAL; | |
877d48d5 DV |
5203 | } |
5204 | ||
42db64ef PZ |
5205 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5206 | struct intel_crtc_config *pipe_config) | |
5207 | { | |
d330a953 | 5208 | pipe_config->ips_enabled = i915.enable_ips && |
3c4ca58c | 5209 | hsw_crtc_supports_ips(crtc) && |
b6dfdc9b | 5210 | pipe_config->pipe_bpp <= 24; |
42db64ef PZ |
5211 | } |
5212 | ||
a43f6e0f | 5213 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
e29c22c0 | 5214 | struct intel_crtc_config *pipe_config) |
79e53945 | 5215 | { |
a43f6e0f | 5216 | struct drm_device *dev = crtc->base.dev; |
b8cecdf5 | 5217 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
89749350 | 5218 | |
ad3a4479 | 5219 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 VS |
5220 | if (INTEL_INFO(dev)->gen < 4) { |
5221 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5222 | int clock_limit = | |
5223 | dev_priv->display.get_display_clock_speed(dev); | |
5224 | ||
5225 | /* | |
5226 | * Enable pixel doubling when the dot clock | |
5227 | * is > 90% of the (display) core speed. | |
5228 | * | |
b397c96b VS |
5229 | * GDG double wide on either pipe, |
5230 | * otherwise pipe A only. | |
cf532bb2 | 5231 | */ |
b397c96b | 5232 | if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && |
241bfc38 | 5233 | adjusted_mode->crtc_clock > clock_limit * 9 / 10) { |
ad3a4479 | 5234 | clock_limit *= 2; |
cf532bb2 | 5235 | pipe_config->double_wide = true; |
ad3a4479 VS |
5236 | } |
5237 | ||
241bfc38 | 5238 | if (adjusted_mode->crtc_clock > clock_limit * 9 / 10) |
e29c22c0 | 5239 | return -EINVAL; |
2c07245f | 5240 | } |
89749350 | 5241 | |
1d1d0e27 VS |
5242 | /* |
5243 | * Pipe horizontal size must be even in: | |
5244 | * - DVO ganged mode | |
5245 | * - LVDS dual channel mode | |
5246 | * - Double wide pipe | |
5247 | */ | |
5248 | if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && | |
5249 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) | |
5250 | pipe_config->pipe_src_w &= ~1; | |
5251 | ||
8693a824 DL |
5252 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
5253 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
5254 | */ |
5255 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
5256 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) | |
e29c22c0 | 5257 | return -EINVAL; |
44f46b42 | 5258 | |
bd080ee5 | 5259 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) { |
5d2d38dd | 5260 | pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */ |
bd080ee5 | 5261 | } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) { |
5d2d38dd DV |
5262 | /* only a 8bpc pipe, with 6bpc dither through the panel fitter |
5263 | * for lvds. */ | |
5264 | pipe_config->pipe_bpp = 8*3; | |
5265 | } | |
5266 | ||
f5adf94e | 5267 | if (HAS_IPS(dev)) |
a43f6e0f DV |
5268 | hsw_compute_ips_config(crtc, pipe_config); |
5269 | ||
12030431 DV |
5270 | /* |
5271 | * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the | |
5272 | * old clock survives for now. | |
5273 | */ | |
5274 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev) || HAS_DDI(dev)) | |
a43f6e0f | 5275 | pipe_config->shared_dpll = crtc->config.shared_dpll; |
42db64ef | 5276 | |
877d48d5 | 5277 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 5278 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 5279 | |
e29c22c0 | 5280 | return 0; |
79e53945 JB |
5281 | } |
5282 | ||
25eb05fc JB |
5283 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
5284 | { | |
d197b7d3 VS |
5285 | struct drm_i915_private *dev_priv = dev->dev_private; |
5286 | int vco = valleyview_get_vco(dev_priv); | |
5287 | u32 val; | |
5288 | int divider; | |
5289 | ||
d49a340d VS |
5290 | /* FIXME: Punit isn't quite ready yet */ |
5291 | if (IS_CHERRYVIEW(dev)) | |
5292 | return 400000; | |
5293 | ||
d197b7d3 VS |
5294 | mutex_lock(&dev_priv->dpio_lock); |
5295 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
5296 | mutex_unlock(&dev_priv->dpio_lock); | |
5297 | ||
5298 | divider = val & DISPLAY_FREQUENCY_VALUES; | |
5299 | ||
7d007f40 VS |
5300 | WARN((val & DISPLAY_FREQUENCY_STATUS) != |
5301 | (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), | |
5302 | "cdclk change in progress\n"); | |
5303 | ||
d197b7d3 | 5304 | return DIV_ROUND_CLOSEST(vco << 1, divider + 1); |
25eb05fc JB |
5305 | } |
5306 | ||
e70236a8 JB |
5307 | static int i945_get_display_clock_speed(struct drm_device *dev) |
5308 | { | |
5309 | return 400000; | |
5310 | } | |
79e53945 | 5311 | |
e70236a8 | 5312 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 5313 | { |
e70236a8 JB |
5314 | return 333000; |
5315 | } | |
79e53945 | 5316 | |
e70236a8 JB |
5317 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
5318 | { | |
5319 | return 200000; | |
5320 | } | |
79e53945 | 5321 | |
257a7ffc DV |
5322 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
5323 | { | |
5324 | u16 gcfgc = 0; | |
5325 | ||
5326 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
5327 | ||
5328 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
5329 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
5330 | return 267000; | |
5331 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: | |
5332 | return 333000; | |
5333 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: | |
5334 | return 444000; | |
5335 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: | |
5336 | return 200000; | |
5337 | default: | |
5338 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
5339 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
5340 | return 133000; | |
5341 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: | |
5342 | return 167000; | |
5343 | } | |
5344 | } | |
5345 | ||
e70236a8 JB |
5346 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
5347 | { | |
5348 | u16 gcfgc = 0; | |
79e53945 | 5349 | |
e70236a8 JB |
5350 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
5351 | ||
5352 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
5353 | return 133000; | |
5354 | else { | |
5355 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
5356 | case GC_DISPLAY_CLOCK_333_MHZ: | |
5357 | return 333000; | |
5358 | default: | |
5359 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
5360 | return 190000; | |
79e53945 | 5361 | } |
e70236a8 JB |
5362 | } |
5363 | } | |
5364 | ||
5365 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
5366 | { | |
5367 | return 266000; | |
5368 | } | |
5369 | ||
5370 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
5371 | { | |
5372 | u16 hpllcc = 0; | |
5373 | /* Assume that the hardware is in the high speed state. This | |
5374 | * should be the default. | |
5375 | */ | |
5376 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
5377 | case GC_CLOCK_133_200: | |
5378 | case GC_CLOCK_100_200: | |
5379 | return 200000; | |
5380 | case GC_CLOCK_166_250: | |
5381 | return 250000; | |
5382 | case GC_CLOCK_100_133: | |
79e53945 | 5383 | return 133000; |
e70236a8 | 5384 | } |
79e53945 | 5385 | |
e70236a8 JB |
5386 | /* Shouldn't happen */ |
5387 | return 0; | |
5388 | } | |
79e53945 | 5389 | |
e70236a8 JB |
5390 | static int i830_get_display_clock_speed(struct drm_device *dev) |
5391 | { | |
5392 | return 133000; | |
79e53945 JB |
5393 | } |
5394 | ||
2c07245f | 5395 | static void |
a65851af | 5396 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 5397 | { |
a65851af VS |
5398 | while (*num > DATA_LINK_M_N_MASK || |
5399 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
5400 | *num >>= 1; |
5401 | *den >>= 1; | |
5402 | } | |
5403 | } | |
5404 | ||
a65851af VS |
5405 | static void compute_m_n(unsigned int m, unsigned int n, |
5406 | uint32_t *ret_m, uint32_t *ret_n) | |
5407 | { | |
5408 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
5409 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
5410 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
5411 | } | |
5412 | ||
e69d0bc1 DV |
5413 | void |
5414 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
5415 | int pixel_clock, int link_clock, | |
5416 | struct intel_link_m_n *m_n) | |
2c07245f | 5417 | { |
e69d0bc1 | 5418 | m_n->tu = 64; |
a65851af VS |
5419 | |
5420 | compute_m_n(bits_per_pixel * pixel_clock, | |
5421 | link_clock * nlanes * 8, | |
5422 | &m_n->gmch_m, &m_n->gmch_n); | |
5423 | ||
5424 | compute_m_n(pixel_clock, link_clock, | |
5425 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
5426 | } |
5427 | ||
a7615030 CW |
5428 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
5429 | { | |
d330a953 JN |
5430 | if (i915.panel_use_ssc >= 0) |
5431 | return i915.panel_use_ssc != 0; | |
41aa3448 | 5432 | return dev_priv->vbt.lvds_use_ssc |
435793df | 5433 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
5434 | } |
5435 | ||
c65d77d8 JB |
5436 | static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) |
5437 | { | |
5438 | struct drm_device *dev = crtc->dev; | |
5439 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5440 | int refclk; | |
5441 | ||
a0c4da24 | 5442 | if (IS_VALLEYVIEW(dev)) { |
9a0ea498 | 5443 | refclk = 100000; |
a0c4da24 | 5444 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 5445 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
e91e941b VS |
5446 | refclk = dev_priv->vbt.lvds_ssc_freq; |
5447 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
5448 | } else if (!IS_GEN2(dev)) { |
5449 | refclk = 96000; | |
5450 | } else { | |
5451 | refclk = 48000; | |
5452 | } | |
5453 | ||
5454 | return refclk; | |
5455 | } | |
5456 | ||
7429e9d4 | 5457 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 5458 | { |
7df00d7a | 5459 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 5460 | } |
f47709a9 | 5461 | |
7429e9d4 DV |
5462 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
5463 | { | |
5464 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
5465 | } |
5466 | ||
f47709a9 | 5467 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
a7516a05 JB |
5468 | intel_clock_t *reduced_clock) |
5469 | { | |
f47709a9 | 5470 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
5471 | u32 fp, fp2 = 0; |
5472 | ||
5473 | if (IS_PINEVIEW(dev)) { | |
7429e9d4 | 5474 | fp = pnv_dpll_compute_fp(&crtc->config.dpll); |
a7516a05 | 5475 | if (reduced_clock) |
7429e9d4 | 5476 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 5477 | } else { |
7429e9d4 | 5478 | fp = i9xx_dpll_compute_fp(&crtc->config.dpll); |
a7516a05 | 5479 | if (reduced_clock) |
7429e9d4 | 5480 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
5481 | } |
5482 | ||
8bcc2795 | 5483 | crtc->config.dpll_hw_state.fp0 = fp; |
a7516a05 | 5484 | |
f47709a9 DV |
5485 | crtc->lowfreq_avail = false; |
5486 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && | |
d330a953 | 5487 | reduced_clock && i915.powersave) { |
8bcc2795 | 5488 | crtc->config.dpll_hw_state.fp1 = fp2; |
f47709a9 | 5489 | crtc->lowfreq_avail = true; |
a7516a05 | 5490 | } else { |
8bcc2795 | 5491 | crtc->config.dpll_hw_state.fp1 = fp; |
a7516a05 JB |
5492 | } |
5493 | } | |
5494 | ||
5e69f97f CML |
5495 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
5496 | pipe) | |
89b667f8 JB |
5497 | { |
5498 | u32 reg_val; | |
5499 | ||
5500 | /* | |
5501 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
5502 | * and set it to a reasonable value instead. | |
5503 | */ | |
ab3c759a | 5504 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
5505 | reg_val &= 0xffffff00; |
5506 | reg_val |= 0x00000030; | |
ab3c759a | 5507 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 5508 | |
ab3c759a | 5509 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
5510 | reg_val &= 0x8cffffff; |
5511 | reg_val = 0x8c000000; | |
ab3c759a | 5512 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 5513 | |
ab3c759a | 5514 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 5515 | reg_val &= 0xffffff00; |
ab3c759a | 5516 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 5517 | |
ab3c759a | 5518 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
5519 | reg_val &= 0x00ffffff; |
5520 | reg_val |= 0xb0000000; | |
ab3c759a | 5521 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
5522 | } |
5523 | ||
b551842d DV |
5524 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
5525 | struct intel_link_m_n *m_n) | |
5526 | { | |
5527 | struct drm_device *dev = crtc->base.dev; | |
5528 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5529 | int pipe = crtc->pipe; | |
5530 | ||
e3b95f1e DV |
5531 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
5532 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
5533 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
5534 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
5535 | } |
5536 | ||
5537 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
5538 | struct intel_link_m_n *m_n, |
5539 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
5540 | { |
5541 | struct drm_device *dev = crtc->base.dev; | |
5542 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5543 | int pipe = crtc->pipe; | |
5544 | enum transcoder transcoder = crtc->config.cpu_transcoder; | |
5545 | ||
5546 | if (INTEL_INFO(dev)->gen >= 5) { | |
5547 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
5548 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
5549 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
5550 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
5551 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
5552 | * for gen < 8) and if DRRS is supported (to make sure the | |
5553 | * registers are not unnecessarily accessed). | |
5554 | */ | |
5555 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
5556 | crtc->config.has_drrs) { | |
5557 | I915_WRITE(PIPE_DATA_M2(transcoder), | |
5558 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
5559 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
5560 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
5561 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
5562 | } | |
b551842d | 5563 | } else { |
e3b95f1e DV |
5564 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
5565 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
5566 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
5567 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
5568 | } |
5569 | } | |
5570 | ||
f769cd24 | 5571 | void intel_dp_set_m_n(struct intel_crtc *crtc) |
03afc4a2 DV |
5572 | { |
5573 | if (crtc->config.has_pch_encoder) | |
5574 | intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); | |
5575 | else | |
f769cd24 VK |
5576 | intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n, |
5577 | &crtc->config.dp_m2_n2); | |
03afc4a2 DV |
5578 | } |
5579 | ||
f47709a9 | 5580 | static void vlv_update_pll(struct intel_crtc *crtc) |
bdd4b6a6 DV |
5581 | { |
5582 | u32 dpll, dpll_md; | |
5583 | ||
5584 | /* | |
5585 | * Enable DPIO clock input. We should never disable the reference | |
5586 | * clock for pipe B, since VGA hotplug / manual detection depends | |
5587 | * on it. | |
5588 | */ | |
5589 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | | |
5590 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; | |
5591 | /* We should never disable this, set it here for state tracking */ | |
5592 | if (crtc->pipe == PIPE_B) | |
5593 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
5594 | dpll |= DPLL_VCO_ENABLE; | |
5595 | crtc->config.dpll_hw_state.dpll = dpll; | |
5596 | ||
5597 | dpll_md = (crtc->config.pixel_multiplier - 1) | |
5598 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
5599 | crtc->config.dpll_hw_state.dpll_md = dpll_md; | |
5600 | } | |
5601 | ||
5602 | static void vlv_prepare_pll(struct intel_crtc *crtc) | |
a0c4da24 | 5603 | { |
f47709a9 | 5604 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 5605 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 5606 | int pipe = crtc->pipe; |
bdd4b6a6 | 5607 | u32 mdiv; |
a0c4da24 | 5608 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 5609 | u32 coreclk, reg_val; |
a0c4da24 | 5610 | |
09153000 DV |
5611 | mutex_lock(&dev_priv->dpio_lock); |
5612 | ||
f47709a9 DV |
5613 | bestn = crtc->config.dpll.n; |
5614 | bestm1 = crtc->config.dpll.m1; | |
5615 | bestm2 = crtc->config.dpll.m2; | |
5616 | bestp1 = crtc->config.dpll.p1; | |
5617 | bestp2 = crtc->config.dpll.p2; | |
a0c4da24 | 5618 | |
89b667f8 JB |
5619 | /* See eDP HDMI DPIO driver vbios notes doc */ |
5620 | ||
5621 | /* PLL B needs special handling */ | |
bdd4b6a6 | 5622 | if (pipe == PIPE_B) |
5e69f97f | 5623 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
5624 | |
5625 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 5626 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
5627 | |
5628 | /* Disable target IRef on PLL */ | |
ab3c759a | 5629 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 5630 | reg_val &= 0x00ffffff; |
ab3c759a | 5631 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
5632 | |
5633 | /* Disable fast lock */ | |
ab3c759a | 5634 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
5635 | |
5636 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
5637 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
5638 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
5639 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 5640 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
5641 | |
5642 | /* | |
5643 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
5644 | * but we don't support that). | |
5645 | * Note: don't use the DAC post divider as it seems unstable. | |
5646 | */ | |
5647 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 5648 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 5649 | |
a0c4da24 | 5650 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 5651 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 5652 | |
89b667f8 | 5653 | /* Set HBR and RBR LPF coefficients */ |
ff9a6750 | 5654 | if (crtc->config.port_clock == 162000 || |
99750bd4 | 5655 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) || |
89b667f8 | 5656 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) |
ab3c759a | 5657 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 5658 | 0x009f0003); |
89b667f8 | 5659 | else |
ab3c759a | 5660 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
5661 | 0x00d0000f); |
5662 | ||
5663 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) || | |
5664 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) { | |
5665 | /* Use SSC source */ | |
bdd4b6a6 | 5666 | if (pipe == PIPE_A) |
ab3c759a | 5667 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5668 | 0x0df40000); |
5669 | else | |
ab3c759a | 5670 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5671 | 0x0df70000); |
5672 | } else { /* HDMI or VGA */ | |
5673 | /* Use bend source */ | |
bdd4b6a6 | 5674 | if (pipe == PIPE_A) |
ab3c759a | 5675 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5676 | 0x0df70000); |
5677 | else | |
ab3c759a | 5678 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5679 | 0x0df40000); |
5680 | } | |
a0c4da24 | 5681 | |
ab3c759a | 5682 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 JB |
5683 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
5684 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) || | |
5685 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) | |
5686 | coreclk |= 0x01000000; | |
ab3c759a | 5687 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 5688 | |
ab3c759a | 5689 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
09153000 | 5690 | mutex_unlock(&dev_priv->dpio_lock); |
a0c4da24 JB |
5691 | } |
5692 | ||
9d556c99 CML |
5693 | static void chv_update_pll(struct intel_crtc *crtc) |
5694 | { | |
5695 | struct drm_device *dev = crtc->base.dev; | |
5696 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5697 | int pipe = crtc->pipe; | |
5698 | int dpll_reg = DPLL(crtc->pipe); | |
5699 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
580d3811 | 5700 | u32 loopfilter, intcoeff; |
9d556c99 CML |
5701 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
5702 | int refclk; | |
5703 | ||
a11b0703 VS |
5704 | crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV | |
5705 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | | |
5706 | DPLL_VCO_ENABLE; | |
5707 | if (pipe != PIPE_A) | |
5708 | crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
5709 | ||
5710 | crtc->config.dpll_hw_state.dpll_md = | |
5711 | (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
9d556c99 CML |
5712 | |
5713 | bestn = crtc->config.dpll.n; | |
5714 | bestm2_frac = crtc->config.dpll.m2 & 0x3fffff; | |
5715 | bestm1 = crtc->config.dpll.m1; | |
5716 | bestm2 = crtc->config.dpll.m2 >> 22; | |
5717 | bestp1 = crtc->config.dpll.p1; | |
5718 | bestp2 = crtc->config.dpll.p2; | |
5719 | ||
5720 | /* | |
5721 | * Enable Refclk and SSC | |
5722 | */ | |
a11b0703 VS |
5723 | I915_WRITE(dpll_reg, |
5724 | crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); | |
5725 | ||
5726 | mutex_lock(&dev_priv->dpio_lock); | |
9d556c99 | 5727 | |
9d556c99 CML |
5728 | /* p1 and p2 divider */ |
5729 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
5730 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
5731 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
5732 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
5733 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
5734 | ||
5735 | /* Feedback post-divider - m2 */ | |
5736 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
5737 | ||
5738 | /* Feedback refclk divider - n and m1 */ | |
5739 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
5740 | DPIO_CHV_M1_DIV_BY_2 | | |
5741 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
5742 | ||
5743 | /* M2 fraction division */ | |
5744 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); | |
5745 | ||
5746 | /* M2 fraction division enable */ | |
5747 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), | |
5748 | DPIO_CHV_FRAC_DIV_EN | | |
5749 | (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT)); | |
5750 | ||
5751 | /* Loop filter */ | |
5752 | refclk = i9xx_get_refclk(&crtc->base, 0); | |
5753 | loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT | | |
5754 | 2 << DPIO_CHV_GAIN_CTRL_SHIFT; | |
5755 | if (refclk == 100000) | |
5756 | intcoeff = 11; | |
5757 | else if (refclk == 38400) | |
5758 | intcoeff = 10; | |
5759 | else | |
5760 | intcoeff = 9; | |
5761 | loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT; | |
5762 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); | |
5763 | ||
5764 | /* AFC Recal */ | |
5765 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
5766 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
5767 | DPIO_AFC_RECAL); | |
5768 | ||
5769 | mutex_unlock(&dev_priv->dpio_lock); | |
5770 | } | |
5771 | ||
f47709a9 DV |
5772 | static void i9xx_update_pll(struct intel_crtc *crtc, |
5773 | intel_clock_t *reduced_clock, | |
eb1cbe48 DV |
5774 | int num_connectors) |
5775 | { | |
f47709a9 | 5776 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 5777 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
5778 | u32 dpll; |
5779 | bool is_sdvo; | |
f47709a9 | 5780 | struct dpll *clock = &crtc->config.dpll; |
eb1cbe48 | 5781 | |
f47709a9 | 5782 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 5783 | |
f47709a9 DV |
5784 | is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) || |
5785 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
5786 | |
5787 | dpll = DPLL_VGA_MODE_DIS; | |
5788 | ||
f47709a9 | 5789 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
5790 | dpll |= DPLLB_MODE_LVDS; |
5791 | else | |
5792 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 5793 | |
ef1b460d | 5794 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
198a037f DV |
5795 | dpll |= (crtc->config.pixel_multiplier - 1) |
5796 | << SDVO_MULTIPLIER_SHIFT_HIRES; | |
eb1cbe48 | 5797 | } |
198a037f DV |
5798 | |
5799 | if (is_sdvo) | |
4a33e48d | 5800 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 5801 | |
f47709a9 | 5802 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) |
4a33e48d | 5803 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
5804 | |
5805 | /* compute bitmask from p1 value */ | |
5806 | if (IS_PINEVIEW(dev)) | |
5807 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
5808 | else { | |
5809 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5810 | if (IS_G4X(dev) && reduced_clock) | |
5811 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
5812 | } | |
5813 | switch (clock->p2) { | |
5814 | case 5: | |
5815 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
5816 | break; | |
5817 | case 7: | |
5818 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
5819 | break; | |
5820 | case 10: | |
5821 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
5822 | break; | |
5823 | case 14: | |
5824 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
5825 | break; | |
5826 | } | |
5827 | if (INTEL_INFO(dev)->gen >= 4) | |
5828 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
5829 | ||
09ede541 | 5830 | if (crtc->config.sdvo_tv_clock) |
eb1cbe48 | 5831 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
f47709a9 | 5832 | else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
5833 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
5834 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
5835 | else | |
5836 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5837 | ||
5838 | dpll |= DPLL_VCO_ENABLE; | |
8bcc2795 DV |
5839 | crtc->config.dpll_hw_state.dpll = dpll; |
5840 | ||
eb1cbe48 | 5841 | if (INTEL_INFO(dev)->gen >= 4) { |
ef1b460d DV |
5842 | u32 dpll_md = (crtc->config.pixel_multiplier - 1) |
5843 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
8bcc2795 | 5844 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
5845 | } |
5846 | } | |
5847 | ||
f47709a9 | 5848 | static void i8xx_update_pll(struct intel_crtc *crtc, |
f47709a9 | 5849 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
5850 | int num_connectors) |
5851 | { | |
f47709a9 | 5852 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 5853 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 5854 | u32 dpll; |
f47709a9 | 5855 | struct dpll *clock = &crtc->config.dpll; |
eb1cbe48 | 5856 | |
f47709a9 | 5857 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 5858 | |
eb1cbe48 DV |
5859 | dpll = DPLL_VGA_MODE_DIS; |
5860 | ||
f47709a9 | 5861 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
5862 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
5863 | } else { | |
5864 | if (clock->p1 == 2) | |
5865 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
5866 | else | |
5867 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5868 | if (clock->p2 == 4) | |
5869 | dpll |= PLL_P2_DIVIDE_BY_4; | |
5870 | } | |
5871 | ||
4a33e48d DV |
5872 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO)) |
5873 | dpll |= DPLL_DVO_2X_MODE; | |
5874 | ||
f47709a9 | 5875 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
5876 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
5877 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
5878 | else | |
5879 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5880 | ||
5881 | dpll |= DPLL_VCO_ENABLE; | |
8bcc2795 | 5882 | crtc->config.dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
5883 | } |
5884 | ||
8a654f3b | 5885 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
5886 | { |
5887 | struct drm_device *dev = intel_crtc->base.dev; | |
5888 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5889 | enum pipe pipe = intel_crtc->pipe; | |
3b117c8f | 5890 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
8a654f3b DV |
5891 | struct drm_display_mode *adjusted_mode = |
5892 | &intel_crtc->config.adjusted_mode; | |
1caea6e9 VS |
5893 | uint32_t crtc_vtotal, crtc_vblank_end; |
5894 | int vsyncshift = 0; | |
4d8a62ea DV |
5895 | |
5896 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
5897 | * the hw state checker will get angry at the mismatch. */ | |
5898 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
5899 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 5900 | |
609aeaca | 5901 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 5902 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
5903 | crtc_vtotal -= 1; |
5904 | crtc_vblank_end -= 1; | |
609aeaca VS |
5905 | |
5906 | if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO)) | |
5907 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; | |
5908 | else | |
5909 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
5910 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
5911 | if (vsyncshift < 0) |
5912 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
5913 | } |
5914 | ||
5915 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 5916 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 5917 | |
fe2b8f9d | 5918 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
5919 | (adjusted_mode->crtc_hdisplay - 1) | |
5920 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 5921 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
5922 | (adjusted_mode->crtc_hblank_start - 1) | |
5923 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 5924 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
5925 | (adjusted_mode->crtc_hsync_start - 1) | |
5926 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
5927 | ||
fe2b8f9d | 5928 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 5929 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 5930 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 5931 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 5932 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 5933 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 5934 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
5935 | (adjusted_mode->crtc_vsync_start - 1) | |
5936 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
5937 | ||
b5e508d4 PZ |
5938 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
5939 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
5940 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
5941 | * bits. */ | |
5942 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
5943 | (pipe == PIPE_B || pipe == PIPE_C)) | |
5944 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
5945 | ||
b0e77b9c PZ |
5946 | /* pipesrc controls the size that is scaled from, which should |
5947 | * always be the user's requested size. | |
5948 | */ | |
5949 | I915_WRITE(PIPESRC(pipe), | |
37327abd VS |
5950 | ((intel_crtc->config.pipe_src_w - 1) << 16) | |
5951 | (intel_crtc->config.pipe_src_h - 1)); | |
b0e77b9c PZ |
5952 | } |
5953 | ||
1bd1bd80 DV |
5954 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5955 | struct intel_crtc_config *pipe_config) | |
5956 | { | |
5957 | struct drm_device *dev = crtc->base.dev; | |
5958 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5959 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
5960 | uint32_t tmp; | |
5961 | ||
5962 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
5963 | pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; | |
5964 | pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
5965 | tmp = I915_READ(HBLANK(cpu_transcoder)); | |
5966 | pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; | |
5967 | pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
5968 | tmp = I915_READ(HSYNC(cpu_transcoder)); | |
5969 | pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; | |
5970 | pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
5971 | ||
5972 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
5973 | pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; | |
5974 | pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
5975 | tmp = I915_READ(VBLANK(cpu_transcoder)); | |
5976 | pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; | |
5977 | pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
5978 | tmp = I915_READ(VSYNC(cpu_transcoder)); | |
5979 | pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; | |
5980 | pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
5981 | ||
5982 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
5983 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; | |
5984 | pipe_config->adjusted_mode.crtc_vtotal += 1; | |
5985 | pipe_config->adjusted_mode.crtc_vblank_end += 1; | |
5986 | } | |
5987 | ||
5988 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
5989 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
5990 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
5991 | ||
5992 | pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h; | |
5993 | pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
5994 | } |
5995 | ||
f6a83288 DV |
5996 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5997 | struct intel_crtc_config *pipe_config) | |
babea61d | 5998 | { |
f6a83288 DV |
5999 | mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay; |
6000 | mode->htotal = pipe_config->adjusted_mode.crtc_htotal; | |
6001 | mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start; | |
6002 | mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end; | |
babea61d | 6003 | |
f6a83288 DV |
6004 | mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay; |
6005 | mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal; | |
6006 | mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start; | |
6007 | mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end; | |
babea61d | 6008 | |
f6a83288 | 6009 | mode->flags = pipe_config->adjusted_mode.flags; |
babea61d | 6010 | |
f6a83288 DV |
6011 | mode->clock = pipe_config->adjusted_mode.crtc_clock; |
6012 | mode->flags |= pipe_config->adjusted_mode.flags; | |
babea61d JB |
6013 | } |
6014 | ||
84b046f3 DV |
6015 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
6016 | { | |
6017 | struct drm_device *dev = intel_crtc->base.dev; | |
6018 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6019 | uint32_t pipeconf; | |
6020 | ||
9f11a9e4 | 6021 | pipeconf = 0; |
84b046f3 | 6022 | |
67c72a12 DV |
6023 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
6024 | I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE) | |
6025 | pipeconf |= PIPECONF_ENABLE; | |
6026 | ||
cf532bb2 VS |
6027 | if (intel_crtc->config.double_wide) |
6028 | pipeconf |= PIPECONF_DOUBLE_WIDE; | |
84b046f3 | 6029 | |
ff9ce46e DV |
6030 | /* only g4x and later have fancy bpc/dither controls */ |
6031 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { | |
ff9ce46e DV |
6032 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6033 | if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30) | |
6034 | pipeconf |= PIPECONF_DITHER_EN | | |
84b046f3 | 6035 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 6036 | |
ff9ce46e DV |
6037 | switch (intel_crtc->config.pipe_bpp) { |
6038 | case 18: | |
6039 | pipeconf |= PIPECONF_6BPC; | |
6040 | break; | |
6041 | case 24: | |
6042 | pipeconf |= PIPECONF_8BPC; | |
6043 | break; | |
6044 | case 30: | |
6045 | pipeconf |= PIPECONF_10BPC; | |
6046 | break; | |
6047 | default: | |
6048 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
6049 | BUG(); | |
84b046f3 DV |
6050 | } |
6051 | } | |
6052 | ||
6053 | if (HAS_PIPE_CXSR(dev)) { | |
6054 | if (intel_crtc->lowfreq_avail) { | |
6055 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
6056 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
6057 | } else { | |
6058 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
6059 | } |
6060 | } | |
6061 | ||
efc2cfff VS |
6062 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
6063 | if (INTEL_INFO(dev)->gen < 4 || | |
6064 | intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO)) | |
6065 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; | |
6066 | else | |
6067 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
6068 | } else | |
84b046f3 DV |
6069 | pipeconf |= PIPECONF_PROGRESSIVE; |
6070 | ||
9f11a9e4 DV |
6071 | if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range) |
6072 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; | |
9c8e09b7 | 6073 | |
84b046f3 DV |
6074 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
6075 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
6076 | } | |
6077 | ||
f564048e | 6078 | static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
f564048e | 6079 | int x, int y, |
94352cf9 | 6080 | struct drm_framebuffer *fb) |
79e53945 JB |
6081 | { |
6082 | struct drm_device *dev = crtc->dev; | |
6083 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6084 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
c751ce4f | 6085 | int refclk, num_connectors = 0; |
652c393a | 6086 | intel_clock_t clock, reduced_clock; |
a16af721 | 6087 | bool ok, has_reduced_clock = false; |
e9fd1c02 | 6088 | bool is_lvds = false, is_dsi = false; |
5eddb70b | 6089 | struct intel_encoder *encoder; |
d4906093 | 6090 | const intel_limit_t *limit; |
79e53945 | 6091 | |
6c2b7c12 | 6092 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5eddb70b | 6093 | switch (encoder->type) { |
79e53945 JB |
6094 | case INTEL_OUTPUT_LVDS: |
6095 | is_lvds = true; | |
6096 | break; | |
e9fd1c02 JN |
6097 | case INTEL_OUTPUT_DSI: |
6098 | is_dsi = true; | |
6099 | break; | |
79e53945 | 6100 | } |
43565a06 | 6101 | |
c751ce4f | 6102 | num_connectors++; |
79e53945 JB |
6103 | } |
6104 | ||
f2335330 | 6105 | if (is_dsi) |
5b18e57c | 6106 | return 0; |
f2335330 JN |
6107 | |
6108 | if (!intel_crtc->config.clock_set) { | |
6109 | refclk = i9xx_get_refclk(crtc, num_connectors); | |
79e53945 | 6110 | |
e9fd1c02 JN |
6111 | /* |
6112 | * Returns a set of divisors for the desired target clock with | |
6113 | * the given refclk, or FALSE. The returned values represent | |
6114 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
6115 | * 2) / p1 / p2. | |
6116 | */ | |
6117 | limit = intel_limit(crtc, refclk); | |
6118 | ok = dev_priv->display.find_dpll(limit, crtc, | |
6119 | intel_crtc->config.port_clock, | |
6120 | refclk, NULL, &clock); | |
f2335330 | 6121 | if (!ok) { |
e9fd1c02 JN |
6122 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
6123 | return -EINVAL; | |
6124 | } | |
79e53945 | 6125 | |
f2335330 JN |
6126 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
6127 | /* | |
6128 | * Ensure we match the reduced clock's P to the target | |
6129 | * clock. If the clocks don't match, we can't switch | |
6130 | * the display clock by using the FP0/FP1. In such case | |
6131 | * we will disable the LVDS downclock feature. | |
6132 | */ | |
6133 | has_reduced_clock = | |
6134 | dev_priv->display.find_dpll(limit, crtc, | |
6135 | dev_priv->lvds_downclock, | |
6136 | refclk, &clock, | |
6137 | &reduced_clock); | |
6138 | } | |
6139 | /* Compat-code for transition, will disappear. */ | |
f47709a9 DV |
6140 | intel_crtc->config.dpll.n = clock.n; |
6141 | intel_crtc->config.dpll.m1 = clock.m1; | |
6142 | intel_crtc->config.dpll.m2 = clock.m2; | |
6143 | intel_crtc->config.dpll.p1 = clock.p1; | |
6144 | intel_crtc->config.dpll.p2 = clock.p2; | |
6145 | } | |
7026d4ac | 6146 | |
e9fd1c02 | 6147 | if (IS_GEN2(dev)) { |
8a654f3b | 6148 | i8xx_update_pll(intel_crtc, |
2a8f64ca VP |
6149 | has_reduced_clock ? &reduced_clock : NULL, |
6150 | num_connectors); | |
9d556c99 CML |
6151 | } else if (IS_CHERRYVIEW(dev)) { |
6152 | chv_update_pll(intel_crtc); | |
e9fd1c02 | 6153 | } else if (IS_VALLEYVIEW(dev)) { |
f2335330 | 6154 | vlv_update_pll(intel_crtc); |
e9fd1c02 | 6155 | } else { |
f47709a9 | 6156 | i9xx_update_pll(intel_crtc, |
eb1cbe48 | 6157 | has_reduced_clock ? &reduced_clock : NULL, |
eba905b2 | 6158 | num_connectors); |
e9fd1c02 | 6159 | } |
79e53945 | 6160 | |
c8f7a0db | 6161 | return 0; |
f564048e EA |
6162 | } |
6163 | ||
2fa2fe9a DV |
6164 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
6165 | struct intel_crtc_config *pipe_config) | |
6166 | { | |
6167 | struct drm_device *dev = crtc->base.dev; | |
6168 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6169 | uint32_t tmp; | |
6170 | ||
dc9e7dec VS |
6171 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
6172 | return; | |
6173 | ||
2fa2fe9a | 6174 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
6175 | if (!(tmp & PFIT_ENABLE)) |
6176 | return; | |
2fa2fe9a | 6177 | |
06922821 | 6178 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
6179 | if (INTEL_INFO(dev)->gen < 4) { |
6180 | if (crtc->pipe != PIPE_B) | |
6181 | return; | |
2fa2fe9a DV |
6182 | } else { |
6183 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
6184 | return; | |
6185 | } | |
6186 | ||
06922821 | 6187 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
6188 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
6189 | if (INTEL_INFO(dev)->gen < 5) | |
6190 | pipe_config->gmch_pfit.lvds_border_bits = | |
6191 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
6192 | } | |
6193 | ||
acbec814 JB |
6194 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
6195 | struct intel_crtc_config *pipe_config) | |
6196 | { | |
6197 | struct drm_device *dev = crtc->base.dev; | |
6198 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6199 | int pipe = pipe_config->cpu_transcoder; | |
6200 | intel_clock_t clock; | |
6201 | u32 mdiv; | |
662c6ecb | 6202 | int refclk = 100000; |
acbec814 | 6203 | |
f573de5a SK |
6204 | /* In case of MIPI DPLL will not even be used */ |
6205 | if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) | |
6206 | return; | |
6207 | ||
acbec814 | 6208 | mutex_lock(&dev_priv->dpio_lock); |
ab3c759a | 6209 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
acbec814 JB |
6210 | mutex_unlock(&dev_priv->dpio_lock); |
6211 | ||
6212 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
6213 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
6214 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
6215 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
6216 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
6217 | ||
f646628b | 6218 | vlv_clock(refclk, &clock); |
acbec814 | 6219 | |
f646628b VS |
6220 | /* clock.dot is the fast clock */ |
6221 | pipe_config->port_clock = clock.dot / 5; | |
acbec814 JB |
6222 | } |
6223 | ||
1ad292b5 JB |
6224 | static void i9xx_get_plane_config(struct intel_crtc *crtc, |
6225 | struct intel_plane_config *plane_config) | |
6226 | { | |
6227 | struct drm_device *dev = crtc->base.dev; | |
6228 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6229 | u32 val, base, offset; | |
6230 | int pipe = crtc->pipe, plane = crtc->plane; | |
6231 | int fourcc, pixel_format; | |
6232 | int aligned_height; | |
6233 | ||
66e514c1 DA |
6234 | crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL); |
6235 | if (!crtc->base.primary->fb) { | |
1ad292b5 JB |
6236 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
6237 | return; | |
6238 | } | |
6239 | ||
6240 | val = I915_READ(DSPCNTR(plane)); | |
6241 | ||
6242 | if (INTEL_INFO(dev)->gen >= 4) | |
6243 | if (val & DISPPLANE_TILED) | |
6244 | plane_config->tiled = true; | |
6245 | ||
6246 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
6247 | fourcc = intel_format_to_fourcc(pixel_format); | |
66e514c1 DA |
6248 | crtc->base.primary->fb->pixel_format = fourcc; |
6249 | crtc->base.primary->fb->bits_per_pixel = | |
1ad292b5 JB |
6250 | drm_format_plane_cpp(fourcc, 0) * 8; |
6251 | ||
6252 | if (INTEL_INFO(dev)->gen >= 4) { | |
6253 | if (plane_config->tiled) | |
6254 | offset = I915_READ(DSPTILEOFF(plane)); | |
6255 | else | |
6256 | offset = I915_READ(DSPLINOFF(plane)); | |
6257 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
6258 | } else { | |
6259 | base = I915_READ(DSPADDR(plane)); | |
6260 | } | |
6261 | plane_config->base = base; | |
6262 | ||
6263 | val = I915_READ(PIPESRC(pipe)); | |
66e514c1 DA |
6264 | crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1; |
6265 | crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
6266 | |
6267 | val = I915_READ(DSPSTRIDE(pipe)); | |
026b96e2 | 6268 | crtc->base.primary->fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 6269 | |
66e514c1 | 6270 | aligned_height = intel_align_height(dev, crtc->base.primary->fb->height, |
1ad292b5 JB |
6271 | plane_config->tiled); |
6272 | ||
1267a26b FF |
6273 | plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] * |
6274 | aligned_height); | |
1ad292b5 JB |
6275 | |
6276 | DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
66e514c1 DA |
6277 | pipe, plane, crtc->base.primary->fb->width, |
6278 | crtc->base.primary->fb->height, | |
6279 | crtc->base.primary->fb->bits_per_pixel, base, | |
6280 | crtc->base.primary->fb->pitches[0], | |
1ad292b5 JB |
6281 | plane_config->size); |
6282 | ||
6283 | } | |
6284 | ||
70b23a98 VS |
6285 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
6286 | struct intel_crtc_config *pipe_config) | |
6287 | { | |
6288 | struct drm_device *dev = crtc->base.dev; | |
6289 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6290 | int pipe = pipe_config->cpu_transcoder; | |
6291 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
6292 | intel_clock_t clock; | |
6293 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2; | |
6294 | int refclk = 100000; | |
6295 | ||
6296 | mutex_lock(&dev_priv->dpio_lock); | |
6297 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); | |
6298 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
6299 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
6300 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
6301 | mutex_unlock(&dev_priv->dpio_lock); | |
6302 | ||
6303 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
6304 | clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff); | |
6305 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; | |
6306 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
6307 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
6308 | ||
6309 | chv_clock(refclk, &clock); | |
6310 | ||
6311 | /* clock.dot is the fast clock */ | |
6312 | pipe_config->port_clock = clock.dot / 5; | |
6313 | } | |
6314 | ||
0e8ffe1b DV |
6315 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
6316 | struct intel_crtc_config *pipe_config) | |
6317 | { | |
6318 | struct drm_device *dev = crtc->base.dev; | |
6319 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6320 | uint32_t tmp; | |
6321 | ||
b5482bd0 ID |
6322 | if (!intel_display_power_enabled(dev_priv, |
6323 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
6324 | return false; | |
6325 | ||
e143a21c | 6326 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 6327 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 6328 | |
0e8ffe1b DV |
6329 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
6330 | if (!(tmp & PIPECONF_ENABLE)) | |
6331 | return false; | |
6332 | ||
42571aef VS |
6333 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
6334 | switch (tmp & PIPECONF_BPC_MASK) { | |
6335 | case PIPECONF_6BPC: | |
6336 | pipe_config->pipe_bpp = 18; | |
6337 | break; | |
6338 | case PIPECONF_8BPC: | |
6339 | pipe_config->pipe_bpp = 24; | |
6340 | break; | |
6341 | case PIPECONF_10BPC: | |
6342 | pipe_config->pipe_bpp = 30; | |
6343 | break; | |
6344 | default: | |
6345 | break; | |
6346 | } | |
6347 | } | |
6348 | ||
b5a9fa09 DV |
6349 | if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
6350 | pipe_config->limited_color_range = true; | |
6351 | ||
282740f7 VS |
6352 | if (INTEL_INFO(dev)->gen < 4) |
6353 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
6354 | ||
1bd1bd80 DV |
6355 | intel_get_pipe_timings(crtc, pipe_config); |
6356 | ||
2fa2fe9a DV |
6357 | i9xx_get_pfit_config(crtc, pipe_config); |
6358 | ||
6c49f241 DV |
6359 | if (INTEL_INFO(dev)->gen >= 4) { |
6360 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
6361 | pipe_config->pixel_multiplier = | |
6362 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
6363 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 6364 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
6365 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
6366 | tmp = I915_READ(DPLL(crtc->pipe)); | |
6367 | pipe_config->pixel_multiplier = | |
6368 | ((tmp & SDVO_MULTIPLIER_MASK) | |
6369 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
6370 | } else { | |
6371 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
6372 | * port and will be fixed up in the encoder->get_config | |
6373 | * function. */ | |
6374 | pipe_config->pixel_multiplier = 1; | |
6375 | } | |
8bcc2795 DV |
6376 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
6377 | if (!IS_VALLEYVIEW(dev)) { | |
6378 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); | |
6379 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
6380 | } else { |
6381 | /* Mask out read-only status bits. */ | |
6382 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
6383 | DPLL_PORTC_READY_MASK | | |
6384 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 6385 | } |
6c49f241 | 6386 | |
70b23a98 VS |
6387 | if (IS_CHERRYVIEW(dev)) |
6388 | chv_crtc_clock_get(crtc, pipe_config); | |
6389 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
6390 | vlv_crtc_clock_get(crtc, pipe_config); |
6391 | else | |
6392 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 6393 | |
0e8ffe1b DV |
6394 | return true; |
6395 | } | |
6396 | ||
dde86e2d | 6397 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
6398 | { |
6399 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6400 | struct drm_mode_config *mode_config = &dev->mode_config; | |
13d83a67 | 6401 | struct intel_encoder *encoder; |
74cfd7ac | 6402 | u32 val, final; |
13d83a67 | 6403 | bool has_lvds = false; |
199e5d79 | 6404 | bool has_cpu_edp = false; |
199e5d79 | 6405 | bool has_panel = false; |
99eb6a01 KP |
6406 | bool has_ck505 = false; |
6407 | bool can_ssc = false; | |
13d83a67 JB |
6408 | |
6409 | /* We need to take the global config into account */ | |
199e5d79 KP |
6410 | list_for_each_entry(encoder, &mode_config->encoder_list, |
6411 | base.head) { | |
6412 | switch (encoder->type) { | |
6413 | case INTEL_OUTPUT_LVDS: | |
6414 | has_panel = true; | |
6415 | has_lvds = true; | |
6416 | break; | |
6417 | case INTEL_OUTPUT_EDP: | |
6418 | has_panel = true; | |
2de6905f | 6419 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
6420 | has_cpu_edp = true; |
6421 | break; | |
13d83a67 JB |
6422 | } |
6423 | } | |
6424 | ||
99eb6a01 | 6425 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 6426 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
6427 | can_ssc = has_ck505; |
6428 | } else { | |
6429 | has_ck505 = false; | |
6430 | can_ssc = true; | |
6431 | } | |
6432 | ||
2de6905f ID |
6433 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
6434 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
6435 | |
6436 | /* Ironlake: try to setup display ref clock before DPLL | |
6437 | * enabling. This is only under driver's control after | |
6438 | * PCH B stepping, previous chipset stepping should be | |
6439 | * ignoring this setting. | |
6440 | */ | |
74cfd7ac CW |
6441 | val = I915_READ(PCH_DREF_CONTROL); |
6442 | ||
6443 | /* As we must carefully and slowly disable/enable each source in turn, | |
6444 | * compute the final state we want first and check if we need to | |
6445 | * make any changes at all. | |
6446 | */ | |
6447 | final = val; | |
6448 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
6449 | if (has_ck505) | |
6450 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
6451 | else | |
6452 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
6453 | ||
6454 | final &= ~DREF_SSC_SOURCE_MASK; | |
6455 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
6456 | final &= ~DREF_SSC1_ENABLE; | |
6457 | ||
6458 | if (has_panel) { | |
6459 | final |= DREF_SSC_SOURCE_ENABLE; | |
6460 | ||
6461 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
6462 | final |= DREF_SSC1_ENABLE; | |
6463 | ||
6464 | if (has_cpu_edp) { | |
6465 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
6466 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
6467 | else | |
6468 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
6469 | } else | |
6470 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
6471 | } else { | |
6472 | final |= DREF_SSC_SOURCE_DISABLE; | |
6473 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
6474 | } | |
6475 | ||
6476 | if (final == val) | |
6477 | return; | |
6478 | ||
13d83a67 | 6479 | /* Always enable nonspread source */ |
74cfd7ac | 6480 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 6481 | |
99eb6a01 | 6482 | if (has_ck505) |
74cfd7ac | 6483 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 6484 | else |
74cfd7ac | 6485 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 6486 | |
199e5d79 | 6487 | if (has_panel) { |
74cfd7ac CW |
6488 | val &= ~DREF_SSC_SOURCE_MASK; |
6489 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 6490 | |
199e5d79 | 6491 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 6492 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 6493 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 6494 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 6495 | } else |
74cfd7ac | 6496 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
6497 | |
6498 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 6499 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
6500 | POSTING_READ(PCH_DREF_CONTROL); |
6501 | udelay(200); | |
6502 | ||
74cfd7ac | 6503 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
6504 | |
6505 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 6506 | if (has_cpu_edp) { |
99eb6a01 | 6507 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 6508 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 6509 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 6510 | } else |
74cfd7ac | 6511 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 6512 | } else |
74cfd7ac | 6513 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 6514 | |
74cfd7ac | 6515 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
6516 | POSTING_READ(PCH_DREF_CONTROL); |
6517 | udelay(200); | |
6518 | } else { | |
6519 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
6520 | ||
74cfd7ac | 6521 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
6522 | |
6523 | /* Turn off CPU output */ | |
74cfd7ac | 6524 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 6525 | |
74cfd7ac | 6526 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
6527 | POSTING_READ(PCH_DREF_CONTROL); |
6528 | udelay(200); | |
6529 | ||
6530 | /* Turn off the SSC source */ | |
74cfd7ac CW |
6531 | val &= ~DREF_SSC_SOURCE_MASK; |
6532 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
6533 | |
6534 | /* Turn off SSC1 */ | |
74cfd7ac | 6535 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 6536 | |
74cfd7ac | 6537 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
6538 | POSTING_READ(PCH_DREF_CONTROL); |
6539 | udelay(200); | |
6540 | } | |
74cfd7ac CW |
6541 | |
6542 | BUG_ON(val != final); | |
13d83a67 JB |
6543 | } |
6544 | ||
f31f2d55 | 6545 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 6546 | { |
f31f2d55 | 6547 | uint32_t tmp; |
dde86e2d | 6548 | |
0ff066a9 PZ |
6549 | tmp = I915_READ(SOUTH_CHICKEN2); |
6550 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
6551 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 6552 | |
0ff066a9 PZ |
6553 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
6554 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
6555 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 6556 | |
0ff066a9 PZ |
6557 | tmp = I915_READ(SOUTH_CHICKEN2); |
6558 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
6559 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 6560 | |
0ff066a9 PZ |
6561 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
6562 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
6563 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
6564 | } |
6565 | ||
6566 | /* WaMPhyProgramming:hsw */ | |
6567 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
6568 | { | |
6569 | uint32_t tmp; | |
dde86e2d PZ |
6570 | |
6571 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
6572 | tmp &= ~(0xFF << 24); | |
6573 | tmp |= (0x12 << 24); | |
6574 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
6575 | ||
dde86e2d PZ |
6576 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
6577 | tmp |= (1 << 11); | |
6578 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
6579 | ||
6580 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
6581 | tmp |= (1 << 11); | |
6582 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
6583 | ||
dde86e2d PZ |
6584 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
6585 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
6586 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
6587 | ||
6588 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
6589 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
6590 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
6591 | ||
0ff066a9 PZ |
6592 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
6593 | tmp &= ~(7 << 13); | |
6594 | tmp |= (5 << 13); | |
6595 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 6596 | |
0ff066a9 PZ |
6597 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
6598 | tmp &= ~(7 << 13); | |
6599 | tmp |= (5 << 13); | |
6600 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
6601 | |
6602 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
6603 | tmp &= ~0xFF; | |
6604 | tmp |= 0x1C; | |
6605 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
6606 | ||
6607 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
6608 | tmp &= ~0xFF; | |
6609 | tmp |= 0x1C; | |
6610 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
6611 | ||
6612 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
6613 | tmp &= ~(0xFF << 16); | |
6614 | tmp |= (0x1C << 16); | |
6615 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
6616 | ||
6617 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
6618 | tmp &= ~(0xFF << 16); | |
6619 | tmp |= (0x1C << 16); | |
6620 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
6621 | ||
0ff066a9 PZ |
6622 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
6623 | tmp |= (1 << 27); | |
6624 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 6625 | |
0ff066a9 PZ |
6626 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
6627 | tmp |= (1 << 27); | |
6628 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 6629 | |
0ff066a9 PZ |
6630 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
6631 | tmp &= ~(0xF << 28); | |
6632 | tmp |= (4 << 28); | |
6633 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 6634 | |
0ff066a9 PZ |
6635 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
6636 | tmp &= ~(0xF << 28); | |
6637 | tmp |= (4 << 28); | |
6638 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
6639 | } |
6640 | ||
2fa86a1f PZ |
6641 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
6642 | * Programming" based on the parameters passed: | |
6643 | * - Sequence to enable CLKOUT_DP | |
6644 | * - Sequence to enable CLKOUT_DP without spread | |
6645 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
6646 | */ | |
6647 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
6648 | bool with_fdi) | |
f31f2d55 PZ |
6649 | { |
6650 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
6651 | uint32_t reg, tmp; |
6652 | ||
6653 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
6654 | with_spread = true; | |
6655 | if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && | |
6656 | with_fdi, "LP PCH doesn't have FDI\n")) | |
6657 | with_fdi = false; | |
f31f2d55 PZ |
6658 | |
6659 | mutex_lock(&dev_priv->dpio_lock); | |
6660 | ||
6661 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
6662 | tmp &= ~SBI_SSCCTL_DISABLE; | |
6663 | tmp |= SBI_SSCCTL_PATHALT; | |
6664 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
6665 | ||
6666 | udelay(24); | |
6667 | ||
2fa86a1f PZ |
6668 | if (with_spread) { |
6669 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
6670 | tmp &= ~SBI_SSCCTL_PATHALT; | |
6671 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 6672 | |
2fa86a1f PZ |
6673 | if (with_fdi) { |
6674 | lpt_reset_fdi_mphy(dev_priv); | |
6675 | lpt_program_fdi_mphy(dev_priv); | |
6676 | } | |
6677 | } | |
dde86e2d | 6678 | |
2fa86a1f PZ |
6679 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
6680 | SBI_GEN0 : SBI_DBUFF0; | |
6681 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
6682 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
6683 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 DV |
6684 | |
6685 | mutex_unlock(&dev_priv->dpio_lock); | |
dde86e2d PZ |
6686 | } |
6687 | ||
47701c3b PZ |
6688 | /* Sequence to disable CLKOUT_DP */ |
6689 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
6690 | { | |
6691 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6692 | uint32_t reg, tmp; | |
6693 | ||
6694 | mutex_lock(&dev_priv->dpio_lock); | |
6695 | ||
6696 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? | |
6697 | SBI_GEN0 : SBI_DBUFF0; | |
6698 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
6699 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
6700 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
6701 | ||
6702 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
6703 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
6704 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
6705 | tmp |= SBI_SSCCTL_PATHALT; | |
6706 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
6707 | udelay(32); | |
6708 | } | |
6709 | tmp |= SBI_SSCCTL_DISABLE; | |
6710 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
6711 | } | |
6712 | ||
6713 | mutex_unlock(&dev_priv->dpio_lock); | |
6714 | } | |
6715 | ||
bf8fa3d3 PZ |
6716 | static void lpt_init_pch_refclk(struct drm_device *dev) |
6717 | { | |
6718 | struct drm_mode_config *mode_config = &dev->mode_config; | |
6719 | struct intel_encoder *encoder; | |
6720 | bool has_vga = false; | |
6721 | ||
6722 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { | |
6723 | switch (encoder->type) { | |
6724 | case INTEL_OUTPUT_ANALOG: | |
6725 | has_vga = true; | |
6726 | break; | |
6727 | } | |
6728 | } | |
6729 | ||
47701c3b PZ |
6730 | if (has_vga) |
6731 | lpt_enable_clkout_dp(dev, true, true); | |
6732 | else | |
6733 | lpt_disable_clkout_dp(dev); | |
bf8fa3d3 PZ |
6734 | } |
6735 | ||
dde86e2d PZ |
6736 | /* |
6737 | * Initialize reference clocks when the driver loads | |
6738 | */ | |
6739 | void intel_init_pch_refclk(struct drm_device *dev) | |
6740 | { | |
6741 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
6742 | ironlake_init_pch_refclk(dev); | |
6743 | else if (HAS_PCH_LPT(dev)) | |
6744 | lpt_init_pch_refclk(dev); | |
6745 | } | |
6746 | ||
d9d444cb JB |
6747 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
6748 | { | |
6749 | struct drm_device *dev = crtc->dev; | |
6750 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6751 | struct intel_encoder *encoder; | |
d9d444cb JB |
6752 | int num_connectors = 0; |
6753 | bool is_lvds = false; | |
6754 | ||
6c2b7c12 | 6755 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
d9d444cb JB |
6756 | switch (encoder->type) { |
6757 | case INTEL_OUTPUT_LVDS: | |
6758 | is_lvds = true; | |
6759 | break; | |
d9d444cb JB |
6760 | } |
6761 | num_connectors++; | |
6762 | } | |
6763 | ||
6764 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
e91e941b | 6765 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
41aa3448 | 6766 | dev_priv->vbt.lvds_ssc_freq); |
e91e941b | 6767 | return dev_priv->vbt.lvds_ssc_freq; |
d9d444cb JB |
6768 | } |
6769 | ||
6770 | return 120000; | |
6771 | } | |
6772 | ||
6ff93609 | 6773 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 6774 | { |
c8203565 | 6775 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
6776 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6777 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
6778 | uint32_t val; |
6779 | ||
78114071 | 6780 | val = 0; |
c8203565 | 6781 | |
965e0c48 | 6782 | switch (intel_crtc->config.pipe_bpp) { |
c8203565 | 6783 | case 18: |
dfd07d72 | 6784 | val |= PIPECONF_6BPC; |
c8203565 PZ |
6785 | break; |
6786 | case 24: | |
dfd07d72 | 6787 | val |= PIPECONF_8BPC; |
c8203565 PZ |
6788 | break; |
6789 | case 30: | |
dfd07d72 | 6790 | val |= PIPECONF_10BPC; |
c8203565 PZ |
6791 | break; |
6792 | case 36: | |
dfd07d72 | 6793 | val |= PIPECONF_12BPC; |
c8203565 PZ |
6794 | break; |
6795 | default: | |
cc769b62 PZ |
6796 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
6797 | BUG(); | |
c8203565 PZ |
6798 | } |
6799 | ||
d8b32247 | 6800 | if (intel_crtc->config.dither) |
c8203565 PZ |
6801 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
6802 | ||
6ff93609 | 6803 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
6804 | val |= PIPECONF_INTERLACED_ILK; |
6805 | else | |
6806 | val |= PIPECONF_PROGRESSIVE; | |
6807 | ||
50f3b016 | 6808 | if (intel_crtc->config.limited_color_range) |
3685a8f3 | 6809 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 6810 | |
c8203565 PZ |
6811 | I915_WRITE(PIPECONF(pipe), val); |
6812 | POSTING_READ(PIPECONF(pipe)); | |
6813 | } | |
6814 | ||
86d3efce VS |
6815 | /* |
6816 | * Set up the pipe CSC unit. | |
6817 | * | |
6818 | * Currently only full range RGB to limited range RGB conversion | |
6819 | * is supported, but eventually this should handle various | |
6820 | * RGB<->YCbCr scenarios as well. | |
6821 | */ | |
50f3b016 | 6822 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
6823 | { |
6824 | struct drm_device *dev = crtc->dev; | |
6825 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6826 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6827 | int pipe = intel_crtc->pipe; | |
6828 | uint16_t coeff = 0x7800; /* 1.0 */ | |
6829 | ||
6830 | /* | |
6831 | * TODO: Check what kind of values actually come out of the pipe | |
6832 | * with these coeff/postoff values and adjust to get the best | |
6833 | * accuracy. Perhaps we even need to take the bpc value into | |
6834 | * consideration. | |
6835 | */ | |
6836 | ||
50f3b016 | 6837 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
6838 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
6839 | ||
6840 | /* | |
6841 | * GY/GU and RY/RU should be the other way around according | |
6842 | * to BSpec, but reality doesn't agree. Just set them up in | |
6843 | * a way that results in the correct picture. | |
6844 | */ | |
6845 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
6846 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
6847 | ||
6848 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
6849 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
6850 | ||
6851 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
6852 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
6853 | ||
6854 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
6855 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
6856 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
6857 | ||
6858 | if (INTEL_INFO(dev)->gen > 6) { | |
6859 | uint16_t postoff = 0; | |
6860 | ||
50f3b016 | 6861 | if (intel_crtc->config.limited_color_range) |
32cf0cb0 | 6862 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
86d3efce VS |
6863 | |
6864 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
6865 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
6866 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
6867 | ||
6868 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
6869 | } else { | |
6870 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
6871 | ||
50f3b016 | 6872 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
6873 | mode |= CSC_BLACK_SCREEN_OFFSET; |
6874 | ||
6875 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
6876 | } | |
6877 | } | |
6878 | ||
6ff93609 | 6879 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 6880 | { |
756f85cf PZ |
6881 | struct drm_device *dev = crtc->dev; |
6882 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 6883 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 6884 | enum pipe pipe = intel_crtc->pipe; |
3b117c8f | 6885 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
ee2b0b38 PZ |
6886 | uint32_t val; |
6887 | ||
3eff4faa | 6888 | val = 0; |
ee2b0b38 | 6889 | |
756f85cf | 6890 | if (IS_HASWELL(dev) && intel_crtc->config.dither) |
ee2b0b38 PZ |
6891 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
6892 | ||
6ff93609 | 6893 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
6894 | val |= PIPECONF_INTERLACED_ILK; |
6895 | else | |
6896 | val |= PIPECONF_PROGRESSIVE; | |
6897 | ||
702e7a56 PZ |
6898 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
6899 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
6900 | |
6901 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
6902 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf PZ |
6903 | |
6904 | if (IS_BROADWELL(dev)) { | |
6905 | val = 0; | |
6906 | ||
6907 | switch (intel_crtc->config.pipe_bpp) { | |
6908 | case 18: | |
6909 | val |= PIPEMISC_DITHER_6_BPC; | |
6910 | break; | |
6911 | case 24: | |
6912 | val |= PIPEMISC_DITHER_8_BPC; | |
6913 | break; | |
6914 | case 30: | |
6915 | val |= PIPEMISC_DITHER_10_BPC; | |
6916 | break; | |
6917 | case 36: | |
6918 | val |= PIPEMISC_DITHER_12_BPC; | |
6919 | break; | |
6920 | default: | |
6921 | /* Case prevented by pipe_config_set_bpp. */ | |
6922 | BUG(); | |
6923 | } | |
6924 | ||
6925 | if (intel_crtc->config.dither) | |
6926 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; | |
6927 | ||
6928 | I915_WRITE(PIPEMISC(pipe), val); | |
6929 | } | |
ee2b0b38 PZ |
6930 | } |
6931 | ||
6591c6e4 | 6932 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
6591c6e4 PZ |
6933 | intel_clock_t *clock, |
6934 | bool *has_reduced_clock, | |
6935 | intel_clock_t *reduced_clock) | |
6936 | { | |
6937 | struct drm_device *dev = crtc->dev; | |
6938 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6939 | struct intel_encoder *intel_encoder; | |
6940 | int refclk; | |
d4906093 | 6941 | const intel_limit_t *limit; |
a16af721 | 6942 | bool ret, is_lvds = false; |
79e53945 | 6943 | |
6591c6e4 PZ |
6944 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
6945 | switch (intel_encoder->type) { | |
79e53945 JB |
6946 | case INTEL_OUTPUT_LVDS: |
6947 | is_lvds = true; | |
6948 | break; | |
79e53945 JB |
6949 | } |
6950 | } | |
6951 | ||
d9d444cb | 6952 | refclk = ironlake_get_refclk(crtc); |
79e53945 | 6953 | |
d4906093 ML |
6954 | /* |
6955 | * Returns a set of divisors for the desired target clock with the given | |
6956 | * refclk, or FALSE. The returned values represent the clock equation: | |
6957 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
6958 | */ | |
1b894b59 | 6959 | limit = intel_limit(crtc, refclk); |
ff9a6750 DV |
6960 | ret = dev_priv->display.find_dpll(limit, crtc, |
6961 | to_intel_crtc(crtc)->config.port_clock, | |
ee9300bb | 6962 | refclk, NULL, clock); |
6591c6e4 PZ |
6963 | if (!ret) |
6964 | return false; | |
cda4b7d3 | 6965 | |
ddc9003c | 6966 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
6967 | /* |
6968 | * Ensure we match the reduced clock's P to the target clock. | |
6969 | * If the clocks don't match, we can't switch the display clock | |
6970 | * by using the FP0/FP1. In such case we will disable the LVDS | |
6971 | * downclock feature. | |
6972 | */ | |
ee9300bb DV |
6973 | *has_reduced_clock = |
6974 | dev_priv->display.find_dpll(limit, crtc, | |
6975 | dev_priv->lvds_downclock, | |
6976 | refclk, clock, | |
6977 | reduced_clock); | |
652c393a | 6978 | } |
61e9653f | 6979 | |
6591c6e4 PZ |
6980 | return true; |
6981 | } | |
6982 | ||
d4b1931c PZ |
6983 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
6984 | { | |
6985 | /* | |
6986 | * Account for spread spectrum to avoid | |
6987 | * oversubscribing the link. Max center spread | |
6988 | * is 2.5%; use 5% for safety's sake. | |
6989 | */ | |
6990 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 6991 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
6992 | } |
6993 | ||
7429e9d4 | 6994 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 6995 | { |
7429e9d4 | 6996 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
6997 | } |
6998 | ||
de13a2e3 | 6999 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
7429e9d4 | 7000 | u32 *fp, |
9a7c7890 | 7001 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 7002 | { |
de13a2e3 | 7003 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
7004 | struct drm_device *dev = crtc->dev; |
7005 | struct drm_i915_private *dev_priv = dev->dev_private; | |
de13a2e3 PZ |
7006 | struct intel_encoder *intel_encoder; |
7007 | uint32_t dpll; | |
6cc5f341 | 7008 | int factor, num_connectors = 0; |
09ede541 | 7009 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 7010 | |
de13a2e3 PZ |
7011 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
7012 | switch (intel_encoder->type) { | |
79e53945 JB |
7013 | case INTEL_OUTPUT_LVDS: |
7014 | is_lvds = true; | |
7015 | break; | |
7016 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 7017 | case INTEL_OUTPUT_HDMI: |
79e53945 | 7018 | is_sdvo = true; |
79e53945 | 7019 | break; |
79e53945 | 7020 | } |
43565a06 | 7021 | |
c751ce4f | 7022 | num_connectors++; |
79e53945 | 7023 | } |
79e53945 | 7024 | |
c1858123 | 7025 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
7026 | factor = 21; |
7027 | if (is_lvds) { | |
7028 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 7029 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 7030 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 7031 | factor = 25; |
09ede541 | 7032 | } else if (intel_crtc->config.sdvo_tv_clock) |
8febb297 | 7033 | factor = 20; |
c1858123 | 7034 | |
7429e9d4 | 7035 | if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor)) |
7d0ac5b7 | 7036 | *fp |= FP_CB_TUNE; |
2c07245f | 7037 | |
9a7c7890 DV |
7038 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
7039 | *fp2 |= FP_CB_TUNE; | |
7040 | ||
5eddb70b | 7041 | dpll = 0; |
2c07245f | 7042 | |
a07d6787 EA |
7043 | if (is_lvds) |
7044 | dpll |= DPLLB_MODE_LVDS; | |
7045 | else | |
7046 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 7047 | |
ef1b460d DV |
7048 | dpll |= (intel_crtc->config.pixel_multiplier - 1) |
7049 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; | |
198a037f DV |
7050 | |
7051 | if (is_sdvo) | |
4a33e48d | 7052 | dpll |= DPLL_SDVO_HIGH_SPEED; |
9566e9af | 7053 | if (intel_crtc->config.has_dp_encoder) |
4a33e48d | 7054 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 7055 | |
a07d6787 | 7056 | /* compute bitmask from p1 value */ |
7429e9d4 | 7057 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 7058 | /* also FPA1 */ |
7429e9d4 | 7059 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 7060 | |
7429e9d4 | 7061 | switch (intel_crtc->config.dpll.p2) { |
a07d6787 EA |
7062 | case 5: |
7063 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7064 | break; | |
7065 | case 7: | |
7066 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7067 | break; | |
7068 | case 10: | |
7069 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7070 | break; | |
7071 | case 14: | |
7072 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7073 | break; | |
79e53945 JB |
7074 | } |
7075 | ||
b4c09f3b | 7076 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 7077 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
7078 | else |
7079 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7080 | ||
959e16d6 | 7081 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
7082 | } |
7083 | ||
7084 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, | |
de13a2e3 PZ |
7085 | int x, int y, |
7086 | struct drm_framebuffer *fb) | |
7087 | { | |
7088 | struct drm_device *dev = crtc->dev; | |
de13a2e3 | 7089 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
de13a2e3 PZ |
7090 | int num_connectors = 0; |
7091 | intel_clock_t clock, reduced_clock; | |
cbbab5bd | 7092 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 7093 | bool ok, has_reduced_clock = false; |
8b47047b | 7094 | bool is_lvds = false; |
de13a2e3 | 7095 | struct intel_encoder *encoder; |
e2b78267 | 7096 | struct intel_shared_dpll *pll; |
de13a2e3 PZ |
7097 | |
7098 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
7099 | switch (encoder->type) { | |
7100 | case INTEL_OUTPUT_LVDS: | |
7101 | is_lvds = true; | |
7102 | break; | |
de13a2e3 PZ |
7103 | } |
7104 | ||
7105 | num_connectors++; | |
a07d6787 | 7106 | } |
79e53945 | 7107 | |
5dc5298b PZ |
7108 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
7109 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 7110 | |
ff9a6750 | 7111 | ok = ironlake_compute_clocks(crtc, &clock, |
de13a2e3 | 7112 | &has_reduced_clock, &reduced_clock); |
ee9300bb | 7113 | if (!ok && !intel_crtc->config.clock_set) { |
de13a2e3 PZ |
7114 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
7115 | return -EINVAL; | |
79e53945 | 7116 | } |
f47709a9 DV |
7117 | /* Compat-code for transition, will disappear. */ |
7118 | if (!intel_crtc->config.clock_set) { | |
7119 | intel_crtc->config.dpll.n = clock.n; | |
7120 | intel_crtc->config.dpll.m1 = clock.m1; | |
7121 | intel_crtc->config.dpll.m2 = clock.m2; | |
7122 | intel_crtc->config.dpll.p1 = clock.p1; | |
7123 | intel_crtc->config.dpll.p2 = clock.p2; | |
7124 | } | |
79e53945 | 7125 | |
5dc5298b | 7126 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
8b47047b | 7127 | if (intel_crtc->config.has_pch_encoder) { |
7429e9d4 | 7128 | fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll); |
cbbab5bd | 7129 | if (has_reduced_clock) |
7429e9d4 | 7130 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 7131 | |
7429e9d4 | 7132 | dpll = ironlake_compute_dpll(intel_crtc, |
cbbab5bd DV |
7133 | &fp, &reduced_clock, |
7134 | has_reduced_clock ? &fp2 : NULL); | |
7135 | ||
959e16d6 | 7136 | intel_crtc->config.dpll_hw_state.dpll = dpll; |
66e985c0 DV |
7137 | intel_crtc->config.dpll_hw_state.fp0 = fp; |
7138 | if (has_reduced_clock) | |
7139 | intel_crtc->config.dpll_hw_state.fp1 = fp2; | |
7140 | else | |
7141 | intel_crtc->config.dpll_hw_state.fp1 = fp; | |
7142 | ||
b89a1d39 | 7143 | pll = intel_get_shared_dpll(intel_crtc); |
ee7b9f93 | 7144 | if (pll == NULL) { |
84f44ce7 | 7145 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
29407aab | 7146 | pipe_name(intel_crtc->pipe)); |
4b645f14 JB |
7147 | return -EINVAL; |
7148 | } | |
ee7b9f93 | 7149 | } else |
e72f9fbf | 7150 | intel_put_shared_dpll(intel_crtc); |
79e53945 | 7151 | |
d330a953 | 7152 | if (is_lvds && has_reduced_clock && i915.powersave) |
bcd644e0 DV |
7153 | intel_crtc->lowfreq_avail = true; |
7154 | else | |
7155 | intel_crtc->lowfreq_avail = false; | |
e2b78267 | 7156 | |
c8f7a0db | 7157 | return 0; |
79e53945 JB |
7158 | } |
7159 | ||
eb14cb74 VS |
7160 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
7161 | struct intel_link_m_n *m_n) | |
7162 | { | |
7163 | struct drm_device *dev = crtc->base.dev; | |
7164 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7165 | enum pipe pipe = crtc->pipe; | |
7166 | ||
7167 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
7168 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
7169 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
7170 | & ~TU_SIZE_MASK; | |
7171 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
7172 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
7173 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
7174 | } | |
7175 | ||
7176 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
7177 | enum transcoder transcoder, | |
b95af8be VK |
7178 | struct intel_link_m_n *m_n, |
7179 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
7180 | { |
7181 | struct drm_device *dev = crtc->base.dev; | |
7182 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 7183 | enum pipe pipe = crtc->pipe; |
72419203 | 7184 | |
eb14cb74 VS |
7185 | if (INTEL_INFO(dev)->gen >= 5) { |
7186 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
7187 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
7188 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
7189 | & ~TU_SIZE_MASK; | |
7190 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
7191 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
7192 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
7193 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
7194 | * gen < 8) and if DRRS is supported (to make sure the | |
7195 | * registers are not unnecessarily read). | |
7196 | */ | |
7197 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
7198 | crtc->config.has_drrs) { | |
7199 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); | |
7200 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
7201 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
7202 | & ~TU_SIZE_MASK; | |
7203 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
7204 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
7205 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
7206 | } | |
eb14cb74 VS |
7207 | } else { |
7208 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
7209 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
7210 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
7211 | & ~TU_SIZE_MASK; | |
7212 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
7213 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
7214 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
7215 | } | |
7216 | } | |
7217 | ||
7218 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
7219 | struct intel_crtc_config *pipe_config) | |
7220 | { | |
7221 | if (crtc->config.has_pch_encoder) | |
7222 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); | |
7223 | else | |
7224 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
7225 | &pipe_config->dp_m_n, |
7226 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 7227 | } |
72419203 | 7228 | |
eb14cb74 VS |
7229 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
7230 | struct intel_crtc_config *pipe_config) | |
7231 | { | |
7232 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 7233 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
7234 | } |
7235 | ||
2fa2fe9a DV |
7236 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
7237 | struct intel_crtc_config *pipe_config) | |
7238 | { | |
7239 | struct drm_device *dev = crtc->base.dev; | |
7240 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7241 | uint32_t tmp; | |
7242 | ||
7243 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
7244 | ||
7245 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 7246 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
7247 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
7248 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
7249 | |
7250 | /* We currently do not free assignements of panel fitters on | |
7251 | * ivb/hsw (since we don't use the higher upscaling modes which | |
7252 | * differentiates them) so just WARN about this case for now. */ | |
7253 | if (IS_GEN7(dev)) { | |
7254 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
7255 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
7256 | } | |
2fa2fe9a | 7257 | } |
79e53945 JB |
7258 | } |
7259 | ||
4c6baa59 JB |
7260 | static void ironlake_get_plane_config(struct intel_crtc *crtc, |
7261 | struct intel_plane_config *plane_config) | |
7262 | { | |
7263 | struct drm_device *dev = crtc->base.dev; | |
7264 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7265 | u32 val, base, offset; | |
7266 | int pipe = crtc->pipe, plane = crtc->plane; | |
7267 | int fourcc, pixel_format; | |
7268 | int aligned_height; | |
7269 | ||
66e514c1 DA |
7270 | crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL); |
7271 | if (!crtc->base.primary->fb) { | |
4c6baa59 JB |
7272 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
7273 | return; | |
7274 | } | |
7275 | ||
7276 | val = I915_READ(DSPCNTR(plane)); | |
7277 | ||
7278 | if (INTEL_INFO(dev)->gen >= 4) | |
7279 | if (val & DISPPLANE_TILED) | |
7280 | plane_config->tiled = true; | |
7281 | ||
7282 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
7283 | fourcc = intel_format_to_fourcc(pixel_format); | |
66e514c1 DA |
7284 | crtc->base.primary->fb->pixel_format = fourcc; |
7285 | crtc->base.primary->fb->bits_per_pixel = | |
4c6baa59 JB |
7286 | drm_format_plane_cpp(fourcc, 0) * 8; |
7287 | ||
7288 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
7289 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { | |
7290 | offset = I915_READ(DSPOFFSET(plane)); | |
7291 | } else { | |
7292 | if (plane_config->tiled) | |
7293 | offset = I915_READ(DSPTILEOFF(plane)); | |
7294 | else | |
7295 | offset = I915_READ(DSPLINOFF(plane)); | |
7296 | } | |
7297 | plane_config->base = base; | |
7298 | ||
7299 | val = I915_READ(PIPESRC(pipe)); | |
66e514c1 DA |
7300 | crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1; |
7301 | crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
7302 | |
7303 | val = I915_READ(DSPSTRIDE(pipe)); | |
026b96e2 | 7304 | crtc->base.primary->fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 7305 | |
66e514c1 | 7306 | aligned_height = intel_align_height(dev, crtc->base.primary->fb->height, |
4c6baa59 JB |
7307 | plane_config->tiled); |
7308 | ||
1267a26b FF |
7309 | plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] * |
7310 | aligned_height); | |
4c6baa59 JB |
7311 | |
7312 | DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
66e514c1 DA |
7313 | pipe, plane, crtc->base.primary->fb->width, |
7314 | crtc->base.primary->fb->height, | |
7315 | crtc->base.primary->fb->bits_per_pixel, base, | |
7316 | crtc->base.primary->fb->pitches[0], | |
4c6baa59 JB |
7317 | plane_config->size); |
7318 | } | |
7319 | ||
0e8ffe1b DV |
7320 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
7321 | struct intel_crtc_config *pipe_config) | |
7322 | { | |
7323 | struct drm_device *dev = crtc->base.dev; | |
7324 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7325 | uint32_t tmp; | |
7326 | ||
930e8c9e PZ |
7327 | if (!intel_display_power_enabled(dev_priv, |
7328 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
7329 | return false; | |
7330 | ||
e143a21c | 7331 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 7332 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 7333 | |
0e8ffe1b DV |
7334 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
7335 | if (!(tmp & PIPECONF_ENABLE)) | |
7336 | return false; | |
7337 | ||
42571aef VS |
7338 | switch (tmp & PIPECONF_BPC_MASK) { |
7339 | case PIPECONF_6BPC: | |
7340 | pipe_config->pipe_bpp = 18; | |
7341 | break; | |
7342 | case PIPECONF_8BPC: | |
7343 | pipe_config->pipe_bpp = 24; | |
7344 | break; | |
7345 | case PIPECONF_10BPC: | |
7346 | pipe_config->pipe_bpp = 30; | |
7347 | break; | |
7348 | case PIPECONF_12BPC: | |
7349 | pipe_config->pipe_bpp = 36; | |
7350 | break; | |
7351 | default: | |
7352 | break; | |
7353 | } | |
7354 | ||
b5a9fa09 DV |
7355 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
7356 | pipe_config->limited_color_range = true; | |
7357 | ||
ab9412ba | 7358 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
7359 | struct intel_shared_dpll *pll; |
7360 | ||
88adfff1 DV |
7361 | pipe_config->has_pch_encoder = true; |
7362 | ||
627eb5a3 DV |
7363 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
7364 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
7365 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
7366 | |
7367 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 7368 | |
c0d43d62 | 7369 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
7370 | pipe_config->shared_dpll = |
7371 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
7372 | } else { |
7373 | tmp = I915_READ(PCH_DPLL_SEL); | |
7374 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
7375 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
7376 | else | |
7377 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
7378 | } | |
66e985c0 DV |
7379 | |
7380 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
7381 | ||
7382 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
7383 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
7384 | |
7385 | tmp = pipe_config->dpll_hw_state.dpll; | |
7386 | pipe_config->pixel_multiplier = | |
7387 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
7388 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
7389 | |
7390 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
7391 | } else { |
7392 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
7393 | } |
7394 | ||
1bd1bd80 DV |
7395 | intel_get_pipe_timings(crtc, pipe_config); |
7396 | ||
2fa2fe9a DV |
7397 | ironlake_get_pfit_config(crtc, pipe_config); |
7398 | ||
0e8ffe1b DV |
7399 | return true; |
7400 | } | |
7401 | ||
be256dc7 PZ |
7402 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
7403 | { | |
7404 | struct drm_device *dev = dev_priv->dev; | |
be256dc7 | 7405 | struct intel_crtc *crtc; |
be256dc7 | 7406 | |
d3fcc808 | 7407 | for_each_intel_crtc(dev, crtc) |
798183c5 | 7408 | WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
7409 | pipe_name(crtc->pipe)); |
7410 | ||
7411 | WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); | |
8cc3e169 DV |
7412 | WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); |
7413 | WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); | |
7414 | WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
be256dc7 PZ |
7415 | WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); |
7416 | WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
7417 | "CPU PWM1 enabled\n"); | |
c5107b87 PZ |
7418 | if (IS_HASWELL(dev)) |
7419 | WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, | |
7420 | "CPU PWM2 enabled\n"); | |
be256dc7 PZ |
7421 | WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
7422 | "PCH PWM1 enabled\n"); | |
7423 | WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, | |
7424 | "Utility pin enabled\n"); | |
7425 | WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); | |
7426 | ||
9926ada1 PZ |
7427 | /* |
7428 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
7429 | * interrupts remain enabled. We used to check for that, but since it's | |
7430 | * gen-specific and since we only disable LCPLL after we fully disable | |
7431 | * the interrupts, the check below should be enough. | |
7432 | */ | |
9df7575f | 7433 | WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
7434 | } |
7435 | ||
9ccd5aeb PZ |
7436 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
7437 | { | |
7438 | struct drm_device *dev = dev_priv->dev; | |
7439 | ||
7440 | if (IS_HASWELL(dev)) | |
7441 | return I915_READ(D_COMP_HSW); | |
7442 | else | |
7443 | return I915_READ(D_COMP_BDW); | |
7444 | } | |
7445 | ||
3c4c9b81 PZ |
7446 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
7447 | { | |
7448 | struct drm_device *dev = dev_priv->dev; | |
7449 | ||
7450 | if (IS_HASWELL(dev)) { | |
7451 | mutex_lock(&dev_priv->rps.hw_lock); | |
7452 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
7453 | val)) | |
f475dadf | 7454 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
7455 | mutex_unlock(&dev_priv->rps.hw_lock); |
7456 | } else { | |
9ccd5aeb PZ |
7457 | I915_WRITE(D_COMP_BDW, val); |
7458 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 7459 | } |
be256dc7 PZ |
7460 | } |
7461 | ||
7462 | /* | |
7463 | * This function implements pieces of two sequences from BSpec: | |
7464 | * - Sequence for display software to disable LCPLL | |
7465 | * - Sequence for display software to allow package C8+ | |
7466 | * The steps implemented here are just the steps that actually touch the LCPLL | |
7467 | * register. Callers should take care of disabling all the display engine | |
7468 | * functions, doing the mode unset, fixing interrupts, etc. | |
7469 | */ | |
6ff58d53 PZ |
7470 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
7471 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
7472 | { |
7473 | uint32_t val; | |
7474 | ||
7475 | assert_can_disable_lcpll(dev_priv); | |
7476 | ||
7477 | val = I915_READ(LCPLL_CTL); | |
7478 | ||
7479 | if (switch_to_fclk) { | |
7480 | val |= LCPLL_CD_SOURCE_FCLK; | |
7481 | I915_WRITE(LCPLL_CTL, val); | |
7482 | ||
7483 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
7484 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
7485 | DRM_ERROR("Switching to FCLK failed\n"); | |
7486 | ||
7487 | val = I915_READ(LCPLL_CTL); | |
7488 | } | |
7489 | ||
7490 | val |= LCPLL_PLL_DISABLE; | |
7491 | I915_WRITE(LCPLL_CTL, val); | |
7492 | POSTING_READ(LCPLL_CTL); | |
7493 | ||
7494 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
7495 | DRM_ERROR("LCPLL still locked\n"); | |
7496 | ||
9ccd5aeb | 7497 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 7498 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 7499 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
7500 | ndelay(100); |
7501 | ||
9ccd5aeb PZ |
7502 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
7503 | 1)) | |
be256dc7 PZ |
7504 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
7505 | ||
7506 | if (allow_power_down) { | |
7507 | val = I915_READ(LCPLL_CTL); | |
7508 | val |= LCPLL_POWER_DOWN_ALLOW; | |
7509 | I915_WRITE(LCPLL_CTL, val); | |
7510 | POSTING_READ(LCPLL_CTL); | |
7511 | } | |
7512 | } | |
7513 | ||
7514 | /* | |
7515 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
7516 | * source. | |
7517 | */ | |
6ff58d53 | 7518 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
7519 | { |
7520 | uint32_t val; | |
a8a8bd54 | 7521 | unsigned long irqflags; |
be256dc7 PZ |
7522 | |
7523 | val = I915_READ(LCPLL_CTL); | |
7524 | ||
7525 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
7526 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
7527 | return; | |
7528 | ||
a8a8bd54 PZ |
7529 | /* |
7530 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
7531 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
7532 | * | |
7533 | * The other problem is that hsw_restore_lcpll() is called as part of | |
7534 | * the runtime PM resume sequence, so we can't just call | |
7535 | * gen6_gt_force_wake_get() because that function calls | |
7536 | * intel_runtime_pm_get(), and we can't change the runtime PM refcount | |
7537 | * while we are on the resume sequence. So to solve this problem we have | |
7538 | * to call special forcewake code that doesn't touch runtime PM and | |
7539 | * doesn't enable the forcewake delayed work. | |
7540 | */ | |
7541 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
7542 | if (dev_priv->uncore.forcewake_count++ == 0) | |
7543 | dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL); | |
7544 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
215733fa | 7545 | |
be256dc7 PZ |
7546 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
7547 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
7548 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 7549 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
7550 | } |
7551 | ||
9ccd5aeb | 7552 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
7553 | val |= D_COMP_COMP_FORCE; |
7554 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 7555 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
7556 | |
7557 | val = I915_READ(LCPLL_CTL); | |
7558 | val &= ~LCPLL_PLL_DISABLE; | |
7559 | I915_WRITE(LCPLL_CTL, val); | |
7560 | ||
7561 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
7562 | DRM_ERROR("LCPLL not locked yet\n"); | |
7563 | ||
7564 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
7565 | val = I915_READ(LCPLL_CTL); | |
7566 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
7567 | I915_WRITE(LCPLL_CTL, val); | |
7568 | ||
7569 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
7570 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
7571 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
7572 | } | |
215733fa | 7573 | |
a8a8bd54 PZ |
7574 | /* See the big comment above. */ |
7575 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
7576 | if (--dev_priv->uncore.forcewake_count == 0) | |
7577 | dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL); | |
7578 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
be256dc7 PZ |
7579 | } |
7580 | ||
765dab67 PZ |
7581 | /* |
7582 | * Package states C8 and deeper are really deep PC states that can only be | |
7583 | * reached when all the devices on the system allow it, so even if the graphics | |
7584 | * device allows PC8+, it doesn't mean the system will actually get to these | |
7585 | * states. Our driver only allows PC8+ when going into runtime PM. | |
7586 | * | |
7587 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
7588 | * well is disabled and most interrupts are disabled, and these are also | |
7589 | * requirements for runtime PM. When these conditions are met, we manually do | |
7590 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
7591 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
7592 | * hang the machine. | |
7593 | * | |
7594 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
7595 | * the state of some registers, so when we come back from PC8+ we need to | |
7596 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
7597 | * need to take care of the registers kept by RC6. Notice that this happens even | |
7598 | * if we don't put the device in PCI D3 state (which is what currently happens | |
7599 | * because of the runtime PM support). | |
7600 | * | |
7601 | * For more, read "Display Sequences for Package C8" on the hardware | |
7602 | * documentation. | |
7603 | */ | |
a14cb6fc | 7604 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 7605 | { |
c67a470b PZ |
7606 | struct drm_device *dev = dev_priv->dev; |
7607 | uint32_t val; | |
7608 | ||
c67a470b PZ |
7609 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
7610 | ||
c67a470b PZ |
7611 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
7612 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
7613 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
7614 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
7615 | } | |
7616 | ||
7617 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
7618 | hsw_disable_lcpll(dev_priv, true, true); |
7619 | } | |
7620 | ||
a14cb6fc | 7621 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
7622 | { |
7623 | struct drm_device *dev = dev_priv->dev; | |
7624 | uint32_t val; | |
7625 | ||
c67a470b PZ |
7626 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
7627 | ||
7628 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
7629 | lpt_init_pch_refclk(dev); |
7630 | ||
7631 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
7632 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
7633 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
7634 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
7635 | } | |
7636 | ||
7637 | intel_prepare_ddi(dev); | |
c67a470b PZ |
7638 | } |
7639 | ||
9a952a0d PZ |
7640 | static void snb_modeset_global_resources(struct drm_device *dev) |
7641 | { | |
7642 | modeset_update_crtc_power_domains(dev); | |
7643 | } | |
7644 | ||
4f074129 ID |
7645 | static void haswell_modeset_global_resources(struct drm_device *dev) |
7646 | { | |
da723569 | 7647 | modeset_update_crtc_power_domains(dev); |
d6dd9eb1 DV |
7648 | } |
7649 | ||
09b4ddf9 | 7650 | static int haswell_crtc_mode_set(struct drm_crtc *crtc, |
09b4ddf9 PZ |
7651 | int x, int y, |
7652 | struct drm_framebuffer *fb) | |
7653 | { | |
09b4ddf9 | 7654 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
09b4ddf9 | 7655 | |
566b734a | 7656 | if (!intel_ddi_pll_select(intel_crtc)) |
6441ab5f | 7657 | return -EINVAL; |
716c2e55 | 7658 | |
644cef34 DV |
7659 | intel_crtc->lowfreq_avail = false; |
7660 | ||
c8f7a0db | 7661 | return 0; |
79e53945 JB |
7662 | } |
7663 | ||
7d2c8175 DL |
7664 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
7665 | enum port port, | |
7666 | struct intel_crtc_config *pipe_config) | |
7667 | { | |
7668 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); | |
7669 | ||
7670 | switch (pipe_config->ddi_pll_sel) { | |
7671 | case PORT_CLK_SEL_WRPLL1: | |
7672 | pipe_config->shared_dpll = DPLL_ID_WRPLL1; | |
7673 | break; | |
7674 | case PORT_CLK_SEL_WRPLL2: | |
7675 | pipe_config->shared_dpll = DPLL_ID_WRPLL2; | |
7676 | break; | |
7677 | } | |
7678 | } | |
7679 | ||
26804afd DV |
7680 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
7681 | struct intel_crtc_config *pipe_config) | |
7682 | { | |
7683 | struct drm_device *dev = crtc->base.dev; | |
7684 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d452c5b6 | 7685 | struct intel_shared_dpll *pll; |
26804afd DV |
7686 | enum port port; |
7687 | uint32_t tmp; | |
7688 | ||
7689 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
7690 | ||
7691 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
7692 | ||
7d2c8175 | 7693 | haswell_get_ddi_pll(dev_priv, port, pipe_config); |
9cd86933 | 7694 | |
d452c5b6 DV |
7695 | if (pipe_config->shared_dpll >= 0) { |
7696 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
7697 | ||
7698 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
7699 | &pipe_config->dpll_hw_state)); | |
7700 | } | |
7701 | ||
26804afd DV |
7702 | /* |
7703 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
7704 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
7705 | * the PCH transcoder is on. | |
7706 | */ | |
7707 | if ((port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
7708 | pipe_config->has_pch_encoder = true; | |
7709 | ||
7710 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
7711 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
7712 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
7713 | ||
7714 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
7715 | } | |
7716 | } | |
7717 | ||
0e8ffe1b DV |
7718 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
7719 | struct intel_crtc_config *pipe_config) | |
7720 | { | |
7721 | struct drm_device *dev = crtc->base.dev; | |
7722 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 7723 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
7724 | uint32_t tmp; |
7725 | ||
b5482bd0 ID |
7726 | if (!intel_display_power_enabled(dev_priv, |
7727 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
7728 | return false; | |
7729 | ||
e143a21c | 7730 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
7731 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
7732 | ||
eccb140b DV |
7733 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
7734 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
7735 | enum pipe trans_edp_pipe; | |
7736 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
7737 | default: | |
7738 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
7739 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
7740 | case TRANS_DDI_EDP_INPUT_A_ON: | |
7741 | trans_edp_pipe = PIPE_A; | |
7742 | break; | |
7743 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
7744 | trans_edp_pipe = PIPE_B; | |
7745 | break; | |
7746 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
7747 | trans_edp_pipe = PIPE_C; | |
7748 | break; | |
7749 | } | |
7750 | ||
7751 | if (trans_edp_pipe == crtc->pipe) | |
7752 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
7753 | } | |
7754 | ||
da7e29bd | 7755 | if (!intel_display_power_enabled(dev_priv, |
eccb140b | 7756 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
7757 | return false; |
7758 | ||
eccb140b | 7759 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
7760 | if (!(tmp & PIPECONF_ENABLE)) |
7761 | return false; | |
7762 | ||
26804afd | 7763 | haswell_get_ddi_port_state(crtc, pipe_config); |
627eb5a3 | 7764 | |
1bd1bd80 DV |
7765 | intel_get_pipe_timings(crtc, pipe_config); |
7766 | ||
2fa2fe9a | 7767 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
da7e29bd | 7768 | if (intel_display_power_enabled(dev_priv, pfit_domain)) |
2fa2fe9a | 7769 | ironlake_get_pfit_config(crtc, pipe_config); |
88adfff1 | 7770 | |
e59150dc JB |
7771 | if (IS_HASWELL(dev)) |
7772 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
7773 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 7774 | |
6c49f241 DV |
7775 | pipe_config->pixel_multiplier = 1; |
7776 | ||
0e8ffe1b DV |
7777 | return true; |
7778 | } | |
7779 | ||
1a91510d JN |
7780 | static struct { |
7781 | int clock; | |
7782 | u32 config; | |
7783 | } hdmi_audio_clock[] = { | |
7784 | { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, | |
7785 | { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ | |
7786 | { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, | |
7787 | { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, | |
7788 | { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, | |
7789 | { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, | |
7790 | { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, | |
7791 | { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, | |
7792 | { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, | |
7793 | { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, | |
7794 | }; | |
7795 | ||
7796 | /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ | |
7797 | static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode) | |
7798 | { | |
7799 | int i; | |
7800 | ||
7801 | for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { | |
7802 | if (mode->clock == hdmi_audio_clock[i].clock) | |
7803 | break; | |
7804 | } | |
7805 | ||
7806 | if (i == ARRAY_SIZE(hdmi_audio_clock)) { | |
7807 | DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock); | |
7808 | i = 1; | |
7809 | } | |
7810 | ||
7811 | DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n", | |
7812 | hdmi_audio_clock[i].clock, | |
7813 | hdmi_audio_clock[i].config); | |
7814 | ||
7815 | return hdmi_audio_clock[i].config; | |
7816 | } | |
7817 | ||
3a9627f4 WF |
7818 | static bool intel_eld_uptodate(struct drm_connector *connector, |
7819 | int reg_eldv, uint32_t bits_eldv, | |
7820 | int reg_elda, uint32_t bits_elda, | |
7821 | int reg_edid) | |
7822 | { | |
7823 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7824 | uint8_t *eld = connector->eld; | |
7825 | uint32_t i; | |
7826 | ||
7827 | i = I915_READ(reg_eldv); | |
7828 | i &= bits_eldv; | |
7829 | ||
7830 | if (!eld[0]) | |
7831 | return !i; | |
7832 | ||
7833 | if (!i) | |
7834 | return false; | |
7835 | ||
7836 | i = I915_READ(reg_elda); | |
7837 | i &= ~bits_elda; | |
7838 | I915_WRITE(reg_elda, i); | |
7839 | ||
7840 | for (i = 0; i < eld[2]; i++) | |
7841 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) | |
7842 | return false; | |
7843 | ||
7844 | return true; | |
7845 | } | |
7846 | ||
e0dac65e | 7847 | static void g4x_write_eld(struct drm_connector *connector, |
34427052 JN |
7848 | struct drm_crtc *crtc, |
7849 | struct drm_display_mode *mode) | |
e0dac65e WF |
7850 | { |
7851 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7852 | uint8_t *eld = connector->eld; | |
7853 | uint32_t eldv; | |
7854 | uint32_t len; | |
7855 | uint32_t i; | |
7856 | ||
7857 | i = I915_READ(G4X_AUD_VID_DID); | |
7858 | ||
7859 | if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) | |
7860 | eldv = G4X_ELDV_DEVCL_DEVBLC; | |
7861 | else | |
7862 | eldv = G4X_ELDV_DEVCTG; | |
7863 | ||
3a9627f4 WF |
7864 | if (intel_eld_uptodate(connector, |
7865 | G4X_AUD_CNTL_ST, eldv, | |
7866 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR, | |
7867 | G4X_HDMIW_HDMIEDID)) | |
7868 | return; | |
7869 | ||
e0dac65e WF |
7870 | i = I915_READ(G4X_AUD_CNTL_ST); |
7871 | i &= ~(eldv | G4X_ELD_ADDR); | |
7872 | len = (i >> 9) & 0x1f; /* ELD buffer size */ | |
7873 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
7874 | ||
7875 | if (!eld[0]) | |
7876 | return; | |
7877 | ||
7878 | len = min_t(uint8_t, eld[2], len); | |
7879 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
7880 | for (i = 0; i < len; i++) | |
7881 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); | |
7882 | ||
7883 | i = I915_READ(G4X_AUD_CNTL_ST); | |
7884 | i |= eldv; | |
7885 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
7886 | } | |
7887 | ||
83358c85 | 7888 | static void haswell_write_eld(struct drm_connector *connector, |
34427052 JN |
7889 | struct drm_crtc *crtc, |
7890 | struct drm_display_mode *mode) | |
83358c85 WX |
7891 | { |
7892 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7893 | uint8_t *eld = connector->eld; | |
83358c85 WX |
7894 | uint32_t eldv; |
7895 | uint32_t i; | |
7896 | int len; | |
7897 | int pipe = to_intel_crtc(crtc)->pipe; | |
7898 | int tmp; | |
7899 | ||
7900 | int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe); | |
7901 | int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe); | |
7902 | int aud_config = HSW_AUD_CFG(pipe); | |
7903 | int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD; | |
7904 | ||
83358c85 WX |
7905 | /* Audio output enable */ |
7906 | DRM_DEBUG_DRIVER("HDMI audio: enable codec\n"); | |
7907 | tmp = I915_READ(aud_cntrl_st2); | |
7908 | tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4)); | |
7909 | I915_WRITE(aud_cntrl_st2, tmp); | |
c7905792 | 7910 | POSTING_READ(aud_cntrl_st2); |
83358c85 | 7911 | |
c7905792 | 7912 | assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe); |
83358c85 WX |
7913 | |
7914 | /* Set ELD valid state */ | |
7915 | tmp = I915_READ(aud_cntrl_st2); | |
7e7cb34f | 7916 | DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp); |
83358c85 WX |
7917 | tmp |= (AUDIO_ELD_VALID_A << (pipe * 4)); |
7918 | I915_WRITE(aud_cntrl_st2, tmp); | |
7919 | tmp = I915_READ(aud_cntrl_st2); | |
7e7cb34f | 7920 | DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp); |
83358c85 WX |
7921 | |
7922 | /* Enable HDMI mode */ | |
7923 | tmp = I915_READ(aud_config); | |
7e7cb34f | 7924 | DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp); |
83358c85 WX |
7925 | /* clear N_programing_enable and N_value_index */ |
7926 | tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE); | |
7927 | I915_WRITE(aud_config, tmp); | |
7928 | ||
7929 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); | |
7930 | ||
7931 | eldv = AUDIO_ELD_VALID_A << (pipe * 4); | |
7932 | ||
7933 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { | |
7934 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
7935 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
7936 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ | |
1a91510d JN |
7937 | } else { |
7938 | I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode)); | |
7939 | } | |
83358c85 WX |
7940 | |
7941 | if (intel_eld_uptodate(connector, | |
7942 | aud_cntrl_st2, eldv, | |
7943 | aud_cntl_st, IBX_ELD_ADDRESS, | |
7944 | hdmiw_hdmiedid)) | |
7945 | return; | |
7946 | ||
7947 | i = I915_READ(aud_cntrl_st2); | |
7948 | i &= ~eldv; | |
7949 | I915_WRITE(aud_cntrl_st2, i); | |
7950 | ||
7951 | if (!eld[0]) | |
7952 | return; | |
7953 | ||
7954 | i = I915_READ(aud_cntl_st); | |
7955 | i &= ~IBX_ELD_ADDRESS; | |
7956 | I915_WRITE(aud_cntl_st, i); | |
7957 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ | |
7958 | DRM_DEBUG_DRIVER("port num:%d\n", i); | |
7959 | ||
7960 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
7961 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
7962 | for (i = 0; i < len; i++) | |
7963 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
7964 | ||
7965 | i = I915_READ(aud_cntrl_st2); | |
7966 | i |= eldv; | |
7967 | I915_WRITE(aud_cntrl_st2, i); | |
7968 | ||
7969 | } | |
7970 | ||
e0dac65e | 7971 | static void ironlake_write_eld(struct drm_connector *connector, |
34427052 JN |
7972 | struct drm_crtc *crtc, |
7973 | struct drm_display_mode *mode) | |
e0dac65e WF |
7974 | { |
7975 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7976 | uint8_t *eld = connector->eld; | |
7977 | uint32_t eldv; | |
7978 | uint32_t i; | |
7979 | int len; | |
7980 | int hdmiw_hdmiedid; | |
b6daa025 | 7981 | int aud_config; |
e0dac65e WF |
7982 | int aud_cntl_st; |
7983 | int aud_cntrl_st2; | |
9b138a83 | 7984 | int pipe = to_intel_crtc(crtc)->pipe; |
e0dac65e | 7985 | |
b3f33cbf | 7986 | if (HAS_PCH_IBX(connector->dev)) { |
9b138a83 WX |
7987 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); |
7988 | aud_config = IBX_AUD_CFG(pipe); | |
7989 | aud_cntl_st = IBX_AUD_CNTL_ST(pipe); | |
1202b4c6 | 7990 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; |
9ca2fe73 ML |
7991 | } else if (IS_VALLEYVIEW(connector->dev)) { |
7992 | hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); | |
7993 | aud_config = VLV_AUD_CFG(pipe); | |
7994 | aud_cntl_st = VLV_AUD_CNTL_ST(pipe); | |
7995 | aud_cntrl_st2 = VLV_AUD_CNTL_ST2; | |
e0dac65e | 7996 | } else { |
9b138a83 WX |
7997 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); |
7998 | aud_config = CPT_AUD_CFG(pipe); | |
7999 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); | |
1202b4c6 | 8000 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; |
e0dac65e WF |
8001 | } |
8002 | ||
9b138a83 | 8003 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
e0dac65e | 8004 | |
9ca2fe73 ML |
8005 | if (IS_VALLEYVIEW(connector->dev)) { |
8006 | struct intel_encoder *intel_encoder; | |
8007 | struct intel_digital_port *intel_dig_port; | |
8008 | ||
8009 | intel_encoder = intel_attached_encoder(connector); | |
8010 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
8011 | i = intel_dig_port->port; | |
8012 | } else { | |
8013 | i = I915_READ(aud_cntl_st); | |
8014 | i = (i >> 29) & DIP_PORT_SEL_MASK; | |
8015 | /* DIP_Port_Select, 0x1 = PortB */ | |
8016 | } | |
8017 | ||
e0dac65e WF |
8018 | if (!i) { |
8019 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); | |
8020 | /* operate blindly on all ports */ | |
1202b4c6 WF |
8021 | eldv = IBX_ELD_VALIDB; |
8022 | eldv |= IBX_ELD_VALIDB << 4; | |
8023 | eldv |= IBX_ELD_VALIDB << 8; | |
e0dac65e | 8024 | } else { |
2582a850 | 8025 | DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i)); |
1202b4c6 | 8026 | eldv = IBX_ELD_VALIDB << ((i - 1) * 4); |
e0dac65e WF |
8027 | } |
8028 | ||
3a9627f4 WF |
8029 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
8030 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
8031 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
b6daa025 | 8032 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
1a91510d JN |
8033 | } else { |
8034 | I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode)); | |
8035 | } | |
e0dac65e | 8036 | |
3a9627f4 WF |
8037 | if (intel_eld_uptodate(connector, |
8038 | aud_cntrl_st2, eldv, | |
8039 | aud_cntl_st, IBX_ELD_ADDRESS, | |
8040 | hdmiw_hdmiedid)) | |
8041 | return; | |
8042 | ||
e0dac65e WF |
8043 | i = I915_READ(aud_cntrl_st2); |
8044 | i &= ~eldv; | |
8045 | I915_WRITE(aud_cntrl_st2, i); | |
8046 | ||
8047 | if (!eld[0]) | |
8048 | return; | |
8049 | ||
e0dac65e | 8050 | i = I915_READ(aud_cntl_st); |
1202b4c6 | 8051 | i &= ~IBX_ELD_ADDRESS; |
e0dac65e WF |
8052 | I915_WRITE(aud_cntl_st, i); |
8053 | ||
8054 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
8055 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
8056 | for (i = 0; i < len; i++) | |
8057 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
8058 | ||
8059 | i = I915_READ(aud_cntrl_st2); | |
8060 | i |= eldv; | |
8061 | I915_WRITE(aud_cntrl_st2, i); | |
8062 | } | |
8063 | ||
8064 | void intel_write_eld(struct drm_encoder *encoder, | |
8065 | struct drm_display_mode *mode) | |
8066 | { | |
8067 | struct drm_crtc *crtc = encoder->crtc; | |
8068 | struct drm_connector *connector; | |
8069 | struct drm_device *dev = encoder->dev; | |
8070 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8071 | ||
8072 | connector = drm_select_eld(encoder, mode); | |
8073 | if (!connector) | |
8074 | return; | |
8075 | ||
8076 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", | |
8077 | connector->base.id, | |
c23cc417 | 8078 | connector->name, |
e0dac65e | 8079 | connector->encoder->base.id, |
8e329a03 | 8080 | connector->encoder->name); |
e0dac65e WF |
8081 | |
8082 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; | |
8083 | ||
8084 | if (dev_priv->display.write_eld) | |
34427052 | 8085 | dev_priv->display.write_eld(connector, crtc, mode); |
e0dac65e WF |
8086 | } |
8087 | ||
560b85bb CW |
8088 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
8089 | { | |
8090 | struct drm_device *dev = crtc->dev; | |
8091 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8092 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4b0e333e | 8093 | uint32_t cntl; |
560b85bb | 8094 | |
4b0e333e | 8095 | if (base != intel_crtc->cursor_base) { |
560b85bb CW |
8096 | /* On these chipsets we can only modify the base whilst |
8097 | * the cursor is disabled. | |
8098 | */ | |
4b0e333e CW |
8099 | if (intel_crtc->cursor_cntl) { |
8100 | I915_WRITE(_CURACNTR, 0); | |
8101 | POSTING_READ(_CURACNTR); | |
8102 | intel_crtc->cursor_cntl = 0; | |
8103 | } | |
8104 | ||
9db4a9c7 | 8105 | I915_WRITE(_CURABASE, base); |
4b0e333e CW |
8106 | POSTING_READ(_CURABASE); |
8107 | } | |
560b85bb | 8108 | |
4b0e333e CW |
8109 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ |
8110 | cntl = 0; | |
8111 | if (base) | |
8112 | cntl = (CURSOR_ENABLE | | |
560b85bb | 8113 | CURSOR_GAMMA_ENABLE | |
4b0e333e CW |
8114 | CURSOR_FORMAT_ARGB); |
8115 | if (intel_crtc->cursor_cntl != cntl) { | |
8116 | I915_WRITE(_CURACNTR, cntl); | |
8117 | POSTING_READ(_CURACNTR); | |
8118 | intel_crtc->cursor_cntl = cntl; | |
8119 | } | |
560b85bb CW |
8120 | } |
8121 | ||
8122 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) | |
8123 | { | |
8124 | struct drm_device *dev = crtc->dev; | |
8125 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8126 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8127 | int pipe = intel_crtc->pipe; | |
4b0e333e | 8128 | uint32_t cntl; |
4726e0b0 | 8129 | |
4b0e333e CW |
8130 | cntl = 0; |
8131 | if (base) { | |
8132 | cntl = MCURSOR_GAMMA_ENABLE; | |
8133 | switch (intel_crtc->cursor_width) { | |
4726e0b0 SK |
8134 | case 64: |
8135 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
8136 | break; | |
8137 | case 128: | |
8138 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
8139 | break; | |
8140 | case 256: | |
8141 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
8142 | break; | |
8143 | default: | |
8144 | WARN_ON(1); | |
8145 | return; | |
560b85bb | 8146 | } |
4b0e333e CW |
8147 | cntl |= pipe << 28; /* Connect to correct pipe */ |
8148 | } | |
8149 | if (intel_crtc->cursor_cntl != cntl) { | |
9db4a9c7 | 8150 | I915_WRITE(CURCNTR(pipe), cntl); |
4b0e333e CW |
8151 | POSTING_READ(CURCNTR(pipe)); |
8152 | intel_crtc->cursor_cntl = cntl; | |
560b85bb | 8153 | } |
4b0e333e | 8154 | |
560b85bb | 8155 | /* and commit changes on next vblank */ |
9db4a9c7 | 8156 | I915_WRITE(CURBASE(pipe), base); |
b2ea8ef5 | 8157 | POSTING_READ(CURBASE(pipe)); |
560b85bb CW |
8158 | } |
8159 | ||
65a21cd6 JB |
8160 | static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) |
8161 | { | |
8162 | struct drm_device *dev = crtc->dev; | |
8163 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8164 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8165 | int pipe = intel_crtc->pipe; | |
4b0e333e CW |
8166 | uint32_t cntl; |
8167 | ||
8168 | cntl = 0; | |
8169 | if (base) { | |
8170 | cntl = MCURSOR_GAMMA_ENABLE; | |
8171 | switch (intel_crtc->cursor_width) { | |
4726e0b0 SK |
8172 | case 64: |
8173 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
8174 | break; | |
8175 | case 128: | |
8176 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
8177 | break; | |
8178 | case 256: | |
8179 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
8180 | break; | |
8181 | default: | |
8182 | WARN_ON(1); | |
8183 | return; | |
65a21cd6 | 8184 | } |
4b0e333e CW |
8185 | } |
8186 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
8187 | cntl |= CURSOR_PIPE_CSC_ENABLE; | |
65a21cd6 | 8188 | |
4b0e333e CW |
8189 | if (intel_crtc->cursor_cntl != cntl) { |
8190 | I915_WRITE(CURCNTR(pipe), cntl); | |
8191 | POSTING_READ(CURCNTR(pipe)); | |
8192 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 8193 | } |
4b0e333e | 8194 | |
65a21cd6 | 8195 | /* and commit changes on next vblank */ |
5efb3e28 VS |
8196 | I915_WRITE(CURBASE(pipe), base); |
8197 | POSTING_READ(CURBASE(pipe)); | |
65a21cd6 JB |
8198 | } |
8199 | ||
cda4b7d3 | 8200 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
8201 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
8202 | bool on) | |
cda4b7d3 CW |
8203 | { |
8204 | struct drm_device *dev = crtc->dev; | |
8205 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8206 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8207 | int pipe = intel_crtc->pipe; | |
3d7d6510 MR |
8208 | int x = crtc->cursor_x; |
8209 | int y = crtc->cursor_y; | |
d6e4db15 | 8210 | u32 base = 0, pos = 0; |
cda4b7d3 | 8211 | |
d6e4db15 | 8212 | if (on) |
cda4b7d3 | 8213 | base = intel_crtc->cursor_addr; |
cda4b7d3 | 8214 | |
d6e4db15 VS |
8215 | if (x >= intel_crtc->config.pipe_src_w) |
8216 | base = 0; | |
8217 | ||
8218 | if (y >= intel_crtc->config.pipe_src_h) | |
cda4b7d3 CW |
8219 | base = 0; |
8220 | ||
8221 | if (x < 0) { | |
efc9064e | 8222 | if (x + intel_crtc->cursor_width <= 0) |
cda4b7d3 CW |
8223 | base = 0; |
8224 | ||
8225 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
8226 | x = -x; | |
8227 | } | |
8228 | pos |= x << CURSOR_X_SHIFT; | |
8229 | ||
8230 | if (y < 0) { | |
efc9064e | 8231 | if (y + intel_crtc->cursor_height <= 0) |
cda4b7d3 CW |
8232 | base = 0; |
8233 | ||
8234 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
8235 | y = -y; | |
8236 | } | |
8237 | pos |= y << CURSOR_Y_SHIFT; | |
8238 | ||
4b0e333e | 8239 | if (base == 0 && intel_crtc->cursor_base == 0) |
cda4b7d3 CW |
8240 | return; |
8241 | ||
5efb3e28 VS |
8242 | I915_WRITE(CURPOS(pipe), pos); |
8243 | ||
8244 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
65a21cd6 | 8245 | ivb_update_cursor(crtc, base); |
5efb3e28 VS |
8246 | else if (IS_845G(dev) || IS_I865G(dev)) |
8247 | i845_update_cursor(crtc, base); | |
8248 | else | |
8249 | i9xx_update_cursor(crtc, base); | |
4b0e333e | 8250 | intel_crtc->cursor_base = base; |
cda4b7d3 CW |
8251 | } |
8252 | ||
e3287951 MR |
8253 | /* |
8254 | * intel_crtc_cursor_set_obj - Set cursor to specified GEM object | |
8255 | * | |
8256 | * Note that the object's reference will be consumed if the update fails. If | |
8257 | * the update succeeds, the reference of the old object (if any) will be | |
8258 | * consumed. | |
8259 | */ | |
8260 | static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc, | |
8261 | struct drm_i915_gem_object *obj, | |
8262 | uint32_t width, uint32_t height) | |
79e53945 JB |
8263 | { |
8264 | struct drm_device *dev = crtc->dev; | |
8265 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8266 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
a071fa00 | 8267 | enum pipe pipe = intel_crtc->pipe; |
64f962e3 | 8268 | unsigned old_width; |
cda4b7d3 | 8269 | uint32_t addr; |
3f8bc370 | 8270 | int ret; |
79e53945 | 8271 | |
79e53945 | 8272 | /* if we want to turn off the cursor ignore width and height */ |
e3287951 | 8273 | if (!obj) { |
28c97730 | 8274 | DRM_DEBUG_KMS("cursor off\n"); |
3f8bc370 | 8275 | addr = 0; |
05394f39 | 8276 | obj = NULL; |
5004417d | 8277 | mutex_lock(&dev->struct_mutex); |
3f8bc370 | 8278 | goto finish; |
79e53945 JB |
8279 | } |
8280 | ||
4726e0b0 SK |
8281 | /* Check for which cursor types we support */ |
8282 | if (!((width == 64 && height == 64) || | |
8283 | (width == 128 && height == 128 && !IS_GEN2(dev)) || | |
8284 | (width == 256 && height == 256 && !IS_GEN2(dev)))) { | |
8285 | DRM_DEBUG("Cursor dimension not supported\n"); | |
79e53945 JB |
8286 | return -EINVAL; |
8287 | } | |
8288 | ||
05394f39 | 8289 | if (obj->base.size < width * height * 4) { |
e3287951 | 8290 | DRM_DEBUG_KMS("buffer is too small\n"); |
34b8686e DA |
8291 | ret = -ENOMEM; |
8292 | goto fail; | |
79e53945 JB |
8293 | } |
8294 | ||
71acb5eb | 8295 | /* we only need to pin inside GTT if cursor is non-phy */ |
7f9872e0 | 8296 | mutex_lock(&dev->struct_mutex); |
3d13ef2e | 8297 | if (!INTEL_INFO(dev)->cursor_needs_physical) { |
693db184 CW |
8298 | unsigned alignment; |
8299 | ||
d9e86c0e | 8300 | if (obj->tiling_mode) { |
3b25b31f | 8301 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
d9e86c0e CW |
8302 | ret = -EINVAL; |
8303 | goto fail_locked; | |
8304 | } | |
8305 | ||
693db184 CW |
8306 | /* Note that the w/a also requires 2 PTE of padding following |
8307 | * the bo. We currently fill all unused PTE with the shadow | |
8308 | * page and so we should always have valid PTE following the | |
8309 | * cursor preventing the VT-d warning. | |
8310 | */ | |
8311 | alignment = 0; | |
8312 | if (need_vtd_wa(dev)) | |
8313 | alignment = 64*1024; | |
8314 | ||
8315 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL); | |
e7b526bb | 8316 | if (ret) { |
3b25b31f | 8317 | DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n"); |
2da3b9b9 | 8318 | goto fail_locked; |
e7b526bb CW |
8319 | } |
8320 | ||
d9e86c0e CW |
8321 | ret = i915_gem_object_put_fence(obj); |
8322 | if (ret) { | |
3b25b31f | 8323 | DRM_DEBUG_KMS("failed to release fence for cursor"); |
d9e86c0e CW |
8324 | goto fail_unpin; |
8325 | } | |
8326 | ||
f343c5f6 | 8327 | addr = i915_gem_obj_ggtt_offset(obj); |
71acb5eb | 8328 | } else { |
6eeefaf3 | 8329 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
00731155 | 8330 | ret = i915_gem_object_attach_phys(obj, align); |
71acb5eb | 8331 | if (ret) { |
3b25b31f | 8332 | DRM_DEBUG_KMS("failed to attach phys object\n"); |
7f9872e0 | 8333 | goto fail_locked; |
71acb5eb | 8334 | } |
00731155 | 8335 | addr = obj->phys_handle->busaddr; |
3f8bc370 KH |
8336 | } |
8337 | ||
a6c45cf0 | 8338 | if (IS_GEN2(dev)) |
14b60391 JB |
8339 | I915_WRITE(CURSIZE, (height << 12) | width); |
8340 | ||
3f8bc370 | 8341 | finish: |
3f8bc370 | 8342 | if (intel_crtc->cursor_bo) { |
00731155 | 8343 | if (!INTEL_INFO(dev)->cursor_needs_physical) |
cc98b413 | 8344 | i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo); |
3f8bc370 | 8345 | } |
80824003 | 8346 | |
a071fa00 DV |
8347 | i915_gem_track_fb(intel_crtc->cursor_bo, obj, |
8348 | INTEL_FRONTBUFFER_CURSOR(pipe)); | |
7f9872e0 | 8349 | mutex_unlock(&dev->struct_mutex); |
3f8bc370 | 8350 | |
64f962e3 CW |
8351 | old_width = intel_crtc->cursor_width; |
8352 | ||
3f8bc370 | 8353 | intel_crtc->cursor_addr = addr; |
05394f39 | 8354 | intel_crtc->cursor_bo = obj; |
cda4b7d3 CW |
8355 | intel_crtc->cursor_width = width; |
8356 | intel_crtc->cursor_height = height; | |
8357 | ||
64f962e3 CW |
8358 | if (intel_crtc->active) { |
8359 | if (old_width != width) | |
8360 | intel_update_watermarks(crtc); | |
f2f5f771 | 8361 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); |
64f962e3 | 8362 | } |
3f8bc370 | 8363 | |
f99d7069 DV |
8364 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe)); |
8365 | ||
79e53945 | 8366 | return 0; |
e7b526bb | 8367 | fail_unpin: |
cc98b413 | 8368 | i915_gem_object_unpin_from_display_plane(obj); |
7f9872e0 | 8369 | fail_locked: |
34b8686e | 8370 | mutex_unlock(&dev->struct_mutex); |
bc9025bd | 8371 | fail: |
05394f39 | 8372 | drm_gem_object_unreference_unlocked(&obj->base); |
34b8686e | 8373 | return ret; |
79e53945 JB |
8374 | } |
8375 | ||
79e53945 | 8376 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 8377 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 8378 | { |
7203425a | 8379 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 8380 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 8381 | |
7203425a | 8382 | for (i = start; i < end; i++) { |
79e53945 JB |
8383 | intel_crtc->lut_r[i] = red[i] >> 8; |
8384 | intel_crtc->lut_g[i] = green[i] >> 8; | |
8385 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
8386 | } | |
8387 | ||
8388 | intel_crtc_load_lut(crtc); | |
8389 | } | |
8390 | ||
79e53945 JB |
8391 | /* VESA 640x480x72Hz mode to set on the pipe */ |
8392 | static struct drm_display_mode load_detect_mode = { | |
8393 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
8394 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
8395 | }; | |
8396 | ||
a8bb6818 DV |
8397 | struct drm_framebuffer * |
8398 | __intel_framebuffer_create(struct drm_device *dev, | |
8399 | struct drm_mode_fb_cmd2 *mode_cmd, | |
8400 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
8401 | { |
8402 | struct intel_framebuffer *intel_fb; | |
8403 | int ret; | |
8404 | ||
8405 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
8406 | if (!intel_fb) { | |
8407 | drm_gem_object_unreference_unlocked(&obj->base); | |
8408 | return ERR_PTR(-ENOMEM); | |
8409 | } | |
8410 | ||
8411 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
8412 | if (ret) |
8413 | goto err; | |
d2dff872 CW |
8414 | |
8415 | return &intel_fb->base; | |
dd4916c5 DV |
8416 | err: |
8417 | drm_gem_object_unreference_unlocked(&obj->base); | |
8418 | kfree(intel_fb); | |
8419 | ||
8420 | return ERR_PTR(ret); | |
d2dff872 CW |
8421 | } |
8422 | ||
b5ea642a | 8423 | static struct drm_framebuffer * |
a8bb6818 DV |
8424 | intel_framebuffer_create(struct drm_device *dev, |
8425 | struct drm_mode_fb_cmd2 *mode_cmd, | |
8426 | struct drm_i915_gem_object *obj) | |
8427 | { | |
8428 | struct drm_framebuffer *fb; | |
8429 | int ret; | |
8430 | ||
8431 | ret = i915_mutex_lock_interruptible(dev); | |
8432 | if (ret) | |
8433 | return ERR_PTR(ret); | |
8434 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
8435 | mutex_unlock(&dev->struct_mutex); | |
8436 | ||
8437 | return fb; | |
8438 | } | |
8439 | ||
d2dff872 CW |
8440 | static u32 |
8441 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
8442 | { | |
8443 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
8444 | return ALIGN(pitch, 64); | |
8445 | } | |
8446 | ||
8447 | static u32 | |
8448 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
8449 | { | |
8450 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 8451 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
8452 | } |
8453 | ||
8454 | static struct drm_framebuffer * | |
8455 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
8456 | struct drm_display_mode *mode, | |
8457 | int depth, int bpp) | |
8458 | { | |
8459 | struct drm_i915_gem_object *obj; | |
0fed39bd | 8460 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
8461 | |
8462 | obj = i915_gem_alloc_object(dev, | |
8463 | intel_framebuffer_size_for_mode(mode, bpp)); | |
8464 | if (obj == NULL) | |
8465 | return ERR_PTR(-ENOMEM); | |
8466 | ||
8467 | mode_cmd.width = mode->hdisplay; | |
8468 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
8469 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
8470 | bpp); | |
5ca0c34a | 8471 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
8472 | |
8473 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
8474 | } | |
8475 | ||
8476 | static struct drm_framebuffer * | |
8477 | mode_fits_in_fbdev(struct drm_device *dev, | |
8478 | struct drm_display_mode *mode) | |
8479 | { | |
4520f53a | 8480 | #ifdef CONFIG_DRM_I915_FBDEV |
d2dff872 CW |
8481 | struct drm_i915_private *dev_priv = dev->dev_private; |
8482 | struct drm_i915_gem_object *obj; | |
8483 | struct drm_framebuffer *fb; | |
8484 | ||
4c0e5528 | 8485 | if (!dev_priv->fbdev) |
d2dff872 CW |
8486 | return NULL; |
8487 | ||
4c0e5528 | 8488 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
8489 | return NULL; |
8490 | ||
4c0e5528 DV |
8491 | obj = dev_priv->fbdev->fb->obj; |
8492 | BUG_ON(!obj); | |
8493 | ||
8bcd4553 | 8494 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
8495 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
8496 | fb->bits_per_pixel)) | |
d2dff872 CW |
8497 | return NULL; |
8498 | ||
01f2c773 | 8499 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
8500 | return NULL; |
8501 | ||
8502 | return fb; | |
4520f53a DV |
8503 | #else |
8504 | return NULL; | |
8505 | #endif | |
d2dff872 CW |
8506 | } |
8507 | ||
d2434ab7 | 8508 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 8509 | struct drm_display_mode *mode, |
51fd371b RC |
8510 | struct intel_load_detect_pipe *old, |
8511 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
8512 | { |
8513 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
8514 | struct intel_encoder *intel_encoder = |
8515 | intel_attached_encoder(connector); | |
79e53945 | 8516 | struct drm_crtc *possible_crtc; |
4ef69c7a | 8517 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
8518 | struct drm_crtc *crtc = NULL; |
8519 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 8520 | struct drm_framebuffer *fb; |
51fd371b RC |
8521 | struct drm_mode_config *config = &dev->mode_config; |
8522 | int ret, i = -1; | |
79e53945 | 8523 | |
d2dff872 | 8524 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 8525 | connector->base.id, connector->name, |
8e329a03 | 8526 | encoder->base.id, encoder->name); |
d2dff872 | 8527 | |
51fd371b RC |
8528 | drm_modeset_acquire_init(ctx, 0); |
8529 | ||
8530 | retry: | |
8531 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
8532 | if (ret) | |
8533 | goto fail_unlock; | |
6e9f798d | 8534 | |
79e53945 JB |
8535 | /* |
8536 | * Algorithm gets a little messy: | |
7a5e4805 | 8537 | * |
79e53945 JB |
8538 | * - if the connector already has an assigned crtc, use it (but make |
8539 | * sure it's on first) | |
7a5e4805 | 8540 | * |
79e53945 JB |
8541 | * - try to find the first unused crtc that can drive this connector, |
8542 | * and use that if we find one | |
79e53945 JB |
8543 | */ |
8544 | ||
8545 | /* See if we already have a CRTC for this connector */ | |
8546 | if (encoder->crtc) { | |
8547 | crtc = encoder->crtc; | |
8261b191 | 8548 | |
51fd371b RC |
8549 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
8550 | if (ret) | |
8551 | goto fail_unlock; | |
7b24056b | 8552 | |
24218aac | 8553 | old->dpms_mode = connector->dpms; |
8261b191 CW |
8554 | old->load_detect_temp = false; |
8555 | ||
8556 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
8557 | if (connector->dpms != DRM_MODE_DPMS_ON) |
8558 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 8559 | |
7173188d | 8560 | return true; |
79e53945 JB |
8561 | } |
8562 | ||
8563 | /* Find an unused one (if possible) */ | |
70e1e0ec | 8564 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
8565 | i++; |
8566 | if (!(encoder->possible_crtcs & (1 << i))) | |
8567 | continue; | |
8568 | if (!possible_crtc->enabled) { | |
8569 | crtc = possible_crtc; | |
8570 | break; | |
8571 | } | |
79e53945 JB |
8572 | } |
8573 | ||
8574 | /* | |
8575 | * If we didn't find an unused CRTC, don't use any. | |
8576 | */ | |
8577 | if (!crtc) { | |
7173188d | 8578 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
51fd371b | 8579 | goto fail_unlock; |
79e53945 JB |
8580 | } |
8581 | ||
51fd371b RC |
8582 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
8583 | if (ret) | |
8584 | goto fail_unlock; | |
fc303101 DV |
8585 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
8586 | to_intel_connector(connector)->new_encoder = intel_encoder; | |
79e53945 JB |
8587 | |
8588 | intel_crtc = to_intel_crtc(crtc); | |
412b61d8 VS |
8589 | intel_crtc->new_enabled = true; |
8590 | intel_crtc->new_config = &intel_crtc->config; | |
24218aac | 8591 | old->dpms_mode = connector->dpms; |
8261b191 | 8592 | old->load_detect_temp = true; |
d2dff872 | 8593 | old->release_fb = NULL; |
79e53945 | 8594 | |
6492711d CW |
8595 | if (!mode) |
8596 | mode = &load_detect_mode; | |
79e53945 | 8597 | |
d2dff872 CW |
8598 | /* We need a framebuffer large enough to accommodate all accesses |
8599 | * that the plane may generate whilst we perform load detection. | |
8600 | * We can not rely on the fbcon either being present (we get called | |
8601 | * during its initialisation to detect all boot displays, or it may | |
8602 | * not even exist) or that it is large enough to satisfy the | |
8603 | * requested mode. | |
8604 | */ | |
94352cf9 DV |
8605 | fb = mode_fits_in_fbdev(dev, mode); |
8606 | if (fb == NULL) { | |
d2dff872 | 8607 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
8608 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
8609 | old->release_fb = fb; | |
d2dff872 CW |
8610 | } else |
8611 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 8612 | if (IS_ERR(fb)) { |
d2dff872 | 8613 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 8614 | goto fail; |
79e53945 | 8615 | } |
79e53945 | 8616 | |
c0c36b94 | 8617 | if (intel_set_mode(crtc, mode, 0, 0, fb)) { |
6492711d | 8618 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
8619 | if (old->release_fb) |
8620 | old->release_fb->funcs->destroy(old->release_fb); | |
412b61d8 | 8621 | goto fail; |
79e53945 | 8622 | } |
7173188d | 8623 | |
79e53945 | 8624 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 8625 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 8626 | return true; |
412b61d8 VS |
8627 | |
8628 | fail: | |
8629 | intel_crtc->new_enabled = crtc->enabled; | |
8630 | if (intel_crtc->new_enabled) | |
8631 | intel_crtc->new_config = &intel_crtc->config; | |
8632 | else | |
8633 | intel_crtc->new_config = NULL; | |
51fd371b RC |
8634 | fail_unlock: |
8635 | if (ret == -EDEADLK) { | |
8636 | drm_modeset_backoff(ctx); | |
8637 | goto retry; | |
8638 | } | |
8639 | ||
8640 | drm_modeset_drop_locks(ctx); | |
8641 | drm_modeset_acquire_fini(ctx); | |
6e9f798d | 8642 | |
412b61d8 | 8643 | return false; |
79e53945 JB |
8644 | } |
8645 | ||
d2434ab7 | 8646 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
51fd371b RC |
8647 | struct intel_load_detect_pipe *old, |
8648 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 8649 | { |
d2434ab7 DV |
8650 | struct intel_encoder *intel_encoder = |
8651 | intel_attached_encoder(connector); | |
4ef69c7a | 8652 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 8653 | struct drm_crtc *crtc = encoder->crtc; |
412b61d8 | 8654 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 8655 | |
d2dff872 | 8656 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 8657 | connector->base.id, connector->name, |
8e329a03 | 8658 | encoder->base.id, encoder->name); |
d2dff872 | 8659 | |
8261b191 | 8660 | if (old->load_detect_temp) { |
fc303101 DV |
8661 | to_intel_connector(connector)->new_encoder = NULL; |
8662 | intel_encoder->new_crtc = NULL; | |
412b61d8 VS |
8663 | intel_crtc->new_enabled = false; |
8664 | intel_crtc->new_config = NULL; | |
fc303101 | 8665 | intel_set_mode(crtc, NULL, 0, 0, NULL); |
d2dff872 | 8666 | |
36206361 DV |
8667 | if (old->release_fb) { |
8668 | drm_framebuffer_unregister_private(old->release_fb); | |
8669 | drm_framebuffer_unreference(old->release_fb); | |
8670 | } | |
d2dff872 | 8671 | |
51fd371b | 8672 | goto unlock; |
0622a53c | 8673 | return; |
79e53945 JB |
8674 | } |
8675 | ||
c751ce4f | 8676 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
8677 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
8678 | connector->funcs->dpms(connector, old->dpms_mode); | |
7b24056b | 8679 | |
51fd371b RC |
8680 | unlock: |
8681 | drm_modeset_drop_locks(ctx); | |
8682 | drm_modeset_acquire_fini(ctx); | |
79e53945 JB |
8683 | } |
8684 | ||
da4a1efa VS |
8685 | static int i9xx_pll_refclk(struct drm_device *dev, |
8686 | const struct intel_crtc_config *pipe_config) | |
8687 | { | |
8688 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8689 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
8690 | ||
8691 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 8692 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
8693 | else if (HAS_PCH_SPLIT(dev)) |
8694 | return 120000; | |
8695 | else if (!IS_GEN2(dev)) | |
8696 | return 96000; | |
8697 | else | |
8698 | return 48000; | |
8699 | } | |
8700 | ||
79e53945 | 8701 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc JB |
8702 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
8703 | struct intel_crtc_config *pipe_config) | |
79e53945 | 8704 | { |
f1f644dc | 8705 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 8706 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 8707 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 8708 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
8709 | u32 fp; |
8710 | intel_clock_t clock; | |
da4a1efa | 8711 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
8712 | |
8713 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 8714 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 8715 | else |
293623f7 | 8716 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
8717 | |
8718 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
8719 | if (IS_PINEVIEW(dev)) { |
8720 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
8721 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
8722 | } else { |
8723 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
8724 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
8725 | } | |
8726 | ||
a6c45cf0 | 8727 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
8728 | if (IS_PINEVIEW(dev)) |
8729 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
8730 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
8731 | else |
8732 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
8733 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
8734 | ||
8735 | switch (dpll & DPLL_MODE_MASK) { | |
8736 | case DPLLB_MODE_DAC_SERIAL: | |
8737 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
8738 | 5 : 10; | |
8739 | break; | |
8740 | case DPLLB_MODE_LVDS: | |
8741 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
8742 | 7 : 14; | |
8743 | break; | |
8744 | default: | |
28c97730 | 8745 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 8746 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 8747 | return; |
79e53945 JB |
8748 | } |
8749 | ||
ac58c3f0 | 8750 | if (IS_PINEVIEW(dev)) |
da4a1efa | 8751 | pineview_clock(refclk, &clock); |
ac58c3f0 | 8752 | else |
da4a1efa | 8753 | i9xx_clock(refclk, &clock); |
79e53945 | 8754 | } else { |
0fb58223 | 8755 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 8756 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
8757 | |
8758 | if (is_lvds) { | |
8759 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
8760 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
8761 | |
8762 | if (lvds & LVDS_CLKB_POWER_UP) | |
8763 | clock.p2 = 7; | |
8764 | else | |
8765 | clock.p2 = 14; | |
79e53945 JB |
8766 | } else { |
8767 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
8768 | clock.p1 = 2; | |
8769 | else { | |
8770 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
8771 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
8772 | } | |
8773 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
8774 | clock.p2 = 4; | |
8775 | else | |
8776 | clock.p2 = 2; | |
79e53945 | 8777 | } |
da4a1efa VS |
8778 | |
8779 | i9xx_clock(refclk, &clock); | |
79e53945 JB |
8780 | } |
8781 | ||
18442d08 VS |
8782 | /* |
8783 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 8784 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
8785 | * encoder's get_config() function. |
8786 | */ | |
8787 | pipe_config->port_clock = clock.dot; | |
f1f644dc JB |
8788 | } |
8789 | ||
6878da05 VS |
8790 | int intel_dotclock_calculate(int link_freq, |
8791 | const struct intel_link_m_n *m_n) | |
f1f644dc | 8792 | { |
f1f644dc JB |
8793 | /* |
8794 | * The calculation for the data clock is: | |
1041a02f | 8795 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 8796 | * But we want to avoid losing precison if possible, so: |
1041a02f | 8797 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
8798 | * |
8799 | * and the link clock is simpler: | |
1041a02f | 8800 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
8801 | */ |
8802 | ||
6878da05 VS |
8803 | if (!m_n->link_n) |
8804 | return 0; | |
f1f644dc | 8805 | |
6878da05 VS |
8806 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
8807 | } | |
f1f644dc | 8808 | |
18442d08 VS |
8809 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
8810 | struct intel_crtc_config *pipe_config) | |
6878da05 VS |
8811 | { |
8812 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 8813 | |
18442d08 VS |
8814 | /* read out port_clock from the DPLL */ |
8815 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 8816 | |
f1f644dc | 8817 | /* |
18442d08 | 8818 | * This value does not include pixel_multiplier. |
241bfc38 | 8819 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
8820 | * agree once we know their relationship in the encoder's |
8821 | * get_config() function. | |
79e53945 | 8822 | */ |
241bfc38 | 8823 | pipe_config->adjusted_mode.crtc_clock = |
18442d08 VS |
8824 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
8825 | &pipe_config->fdi_m_n); | |
79e53945 JB |
8826 | } |
8827 | ||
8828 | /** Returns the currently programmed mode of the given pipe. */ | |
8829 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
8830 | struct drm_crtc *crtc) | |
8831 | { | |
548f245b | 8832 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 8833 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3b117c8f | 8834 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
79e53945 | 8835 | struct drm_display_mode *mode; |
f1f644dc | 8836 | struct intel_crtc_config pipe_config; |
fe2b8f9d PZ |
8837 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
8838 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
8839 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
8840 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 8841 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
8842 | |
8843 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
8844 | if (!mode) | |
8845 | return NULL; | |
8846 | ||
f1f644dc JB |
8847 | /* |
8848 | * Construct a pipe_config sufficient for getting the clock info | |
8849 | * back out of crtc_clock_get. | |
8850 | * | |
8851 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
8852 | * to use a real value here instead. | |
8853 | */ | |
293623f7 | 8854 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
f1f644dc | 8855 | pipe_config.pixel_multiplier = 1; |
293623f7 VS |
8856 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
8857 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
8858 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
f1f644dc JB |
8859 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
8860 | ||
773ae034 | 8861 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
79e53945 JB |
8862 | mode->hdisplay = (htot & 0xffff) + 1; |
8863 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
8864 | mode->hsync_start = (hsync & 0xffff) + 1; | |
8865 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
8866 | mode->vdisplay = (vtot & 0xffff) + 1; | |
8867 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
8868 | mode->vsync_start = (vsync & 0xffff) + 1; | |
8869 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
8870 | ||
8871 | drm_mode_set_name(mode); | |
79e53945 JB |
8872 | |
8873 | return mode; | |
8874 | } | |
8875 | ||
cc36513c DV |
8876 | static void intel_increase_pllclock(struct drm_device *dev, |
8877 | enum pipe pipe) | |
652c393a | 8878 | { |
fbee40df | 8879 | struct drm_i915_private *dev_priv = dev->dev_private; |
dbdc6479 JB |
8880 | int dpll_reg = DPLL(pipe); |
8881 | int dpll; | |
652c393a | 8882 | |
baff296c | 8883 | if (!HAS_GMCH_DISPLAY(dev)) |
652c393a JB |
8884 | return; |
8885 | ||
8886 | if (!dev_priv->lvds_downclock_avail) | |
8887 | return; | |
8888 | ||
dbdc6479 | 8889 | dpll = I915_READ(dpll_reg); |
652c393a | 8890 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
44d98a61 | 8891 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
652c393a | 8892 | |
8ac5a6d5 | 8893 | assert_panel_unlocked(dev_priv, pipe); |
652c393a JB |
8894 | |
8895 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; | |
8896 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 8897 | intel_wait_for_vblank(dev, pipe); |
dbdc6479 | 8898 | |
652c393a JB |
8899 | dpll = I915_READ(dpll_reg); |
8900 | if (dpll & DISPLAY_RATE_SELECT_FPA1) | |
44d98a61 | 8901 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
652c393a | 8902 | } |
652c393a JB |
8903 | } |
8904 | ||
8905 | static void intel_decrease_pllclock(struct drm_crtc *crtc) | |
8906 | { | |
8907 | struct drm_device *dev = crtc->dev; | |
fbee40df | 8908 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 8909 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
652c393a | 8910 | |
baff296c | 8911 | if (!HAS_GMCH_DISPLAY(dev)) |
652c393a JB |
8912 | return; |
8913 | ||
8914 | if (!dev_priv->lvds_downclock_avail) | |
8915 | return; | |
8916 | ||
8917 | /* | |
8918 | * Since this is called by a timer, we should never get here in | |
8919 | * the manual case. | |
8920 | */ | |
8921 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
dc257cf1 DV |
8922 | int pipe = intel_crtc->pipe; |
8923 | int dpll_reg = DPLL(pipe); | |
8924 | int dpll; | |
f6e5b160 | 8925 | |
44d98a61 | 8926 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a | 8927 | |
8ac5a6d5 | 8928 | assert_panel_unlocked(dev_priv, pipe); |
652c393a | 8929 | |
dc257cf1 | 8930 | dpll = I915_READ(dpll_reg); |
652c393a JB |
8931 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
8932 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 8933 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
8934 | dpll = I915_READ(dpll_reg); |
8935 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 8936 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
8937 | } |
8938 | ||
8939 | } | |
8940 | ||
f047e395 CW |
8941 | void intel_mark_busy(struct drm_device *dev) |
8942 | { | |
c67a470b PZ |
8943 | struct drm_i915_private *dev_priv = dev->dev_private; |
8944 | ||
f62a0076 CW |
8945 | if (dev_priv->mm.busy) |
8946 | return; | |
8947 | ||
43694d69 | 8948 | intel_runtime_pm_get(dev_priv); |
c67a470b | 8949 | i915_update_gfx_val(dev_priv); |
f62a0076 | 8950 | dev_priv->mm.busy = true; |
f047e395 CW |
8951 | } |
8952 | ||
8953 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 8954 | { |
c67a470b | 8955 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 8956 | struct drm_crtc *crtc; |
652c393a | 8957 | |
f62a0076 CW |
8958 | if (!dev_priv->mm.busy) |
8959 | return; | |
8960 | ||
8961 | dev_priv->mm.busy = false; | |
8962 | ||
d330a953 | 8963 | if (!i915.powersave) |
bb4cdd53 | 8964 | goto out; |
652c393a | 8965 | |
70e1e0ec | 8966 | for_each_crtc(dev, crtc) { |
f4510a27 | 8967 | if (!crtc->primary->fb) |
652c393a JB |
8968 | continue; |
8969 | ||
725a5b54 | 8970 | intel_decrease_pllclock(crtc); |
652c393a | 8971 | } |
b29c19b6 | 8972 | |
3d13ef2e | 8973 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 8974 | gen6_rps_idle(dev->dev_private); |
bb4cdd53 PZ |
8975 | |
8976 | out: | |
43694d69 | 8977 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
8978 | } |
8979 | ||
7c8f8a70 | 8980 | |
f99d7069 DV |
8981 | /** |
8982 | * intel_mark_fb_busy - mark given planes as busy | |
8983 | * @dev: DRM device | |
8984 | * @frontbuffer_bits: bits for the affected planes | |
8985 | * @ring: optional ring for asynchronous commands | |
8986 | * | |
8987 | * This function gets called every time the screen contents change. It can be | |
8988 | * used to keep e.g. the update rate at the nominal refresh rate with DRRS. | |
8989 | */ | |
8990 | static void intel_mark_fb_busy(struct drm_device *dev, | |
8991 | unsigned frontbuffer_bits, | |
8992 | struct intel_engine_cs *ring) | |
652c393a | 8993 | { |
cc36513c | 8994 | enum pipe pipe; |
652c393a | 8995 | |
d330a953 | 8996 | if (!i915.powersave) |
acb87dfb CW |
8997 | return; |
8998 | ||
cc36513c | 8999 | for_each_pipe(pipe) { |
f99d7069 | 9000 | if (!(frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe))) |
c65355bb CW |
9001 | continue; |
9002 | ||
cc36513c | 9003 | intel_increase_pllclock(dev, pipe); |
c65355bb CW |
9004 | if (ring && intel_fbc_enabled(dev)) |
9005 | ring->fbc_dirty = true; | |
652c393a JB |
9006 | } |
9007 | } | |
9008 | ||
f99d7069 DV |
9009 | /** |
9010 | * intel_fb_obj_invalidate - invalidate frontbuffer object | |
9011 | * @obj: GEM object to invalidate | |
9012 | * @ring: set for asynchronous rendering | |
9013 | * | |
9014 | * This function gets called every time rendering on the given object starts and | |
9015 | * frontbuffer caching (fbc, low refresh rate for DRRS, panel self refresh) must | |
9016 | * be invalidated. If @ring is non-NULL any subsequent invalidation will be delayed | |
9017 | * until the rendering completes or a flip on this frontbuffer plane is | |
9018 | * scheduled. | |
9019 | */ | |
9020 | void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj, | |
9021 | struct intel_engine_cs *ring) | |
9022 | { | |
9023 | struct drm_device *dev = obj->base.dev; | |
9024 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9025 | ||
9026 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); | |
9027 | ||
9028 | if (!obj->frontbuffer_bits) | |
9029 | return; | |
9030 | ||
9031 | if (ring) { | |
9032 | mutex_lock(&dev_priv->fb_tracking.lock); | |
9033 | dev_priv->fb_tracking.busy_bits | |
9034 | |= obj->frontbuffer_bits; | |
9035 | dev_priv->fb_tracking.flip_bits | |
9036 | &= ~obj->frontbuffer_bits; | |
9037 | mutex_unlock(&dev_priv->fb_tracking.lock); | |
9038 | } | |
9039 | ||
9040 | intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring); | |
9041 | ||
9ca15301 | 9042 | intel_edp_psr_invalidate(dev, obj->frontbuffer_bits); |
f99d7069 DV |
9043 | } |
9044 | ||
9045 | /** | |
9046 | * intel_frontbuffer_flush - flush frontbuffer | |
9047 | * @dev: DRM device | |
9048 | * @frontbuffer_bits: frontbuffer plane tracking bits | |
9049 | * | |
9050 | * This function gets called every time rendering on the given planes has | |
9051 | * completed and frontbuffer caching can be started again. Flushes will get | |
9052 | * delayed if they're blocked by some oustanding asynchronous rendering. | |
9053 | * | |
9054 | * Can be called without any locks held. | |
9055 | */ | |
9056 | void intel_frontbuffer_flush(struct drm_device *dev, | |
9057 | unsigned frontbuffer_bits) | |
9058 | { | |
9059 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9060 | ||
9061 | /* Delay flushing when rings are still busy.*/ | |
9062 | mutex_lock(&dev_priv->fb_tracking.lock); | |
9063 | frontbuffer_bits &= ~dev_priv->fb_tracking.busy_bits; | |
9064 | mutex_unlock(&dev_priv->fb_tracking.lock); | |
9065 | ||
9066 | intel_mark_fb_busy(dev, frontbuffer_bits, NULL); | |
9067 | ||
9ca15301 | 9068 | intel_edp_psr_flush(dev, frontbuffer_bits); |
f99d7069 DV |
9069 | } |
9070 | ||
9071 | /** | |
9072 | * intel_fb_obj_flush - flush frontbuffer object | |
9073 | * @obj: GEM object to flush | |
9074 | * @retire: set when retiring asynchronous rendering | |
9075 | * | |
9076 | * This function gets called every time rendering on the given object has | |
9077 | * completed and frontbuffer caching can be started again. If @retire is true | |
9078 | * then any delayed flushes will be unblocked. | |
9079 | */ | |
9080 | void intel_fb_obj_flush(struct drm_i915_gem_object *obj, | |
9081 | bool retire) | |
9082 | { | |
9083 | struct drm_device *dev = obj->base.dev; | |
9084 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9085 | unsigned frontbuffer_bits; | |
9086 | ||
9087 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); | |
9088 | ||
9089 | if (!obj->frontbuffer_bits) | |
9090 | return; | |
9091 | ||
9092 | frontbuffer_bits = obj->frontbuffer_bits; | |
9093 | ||
9094 | if (retire) { | |
9095 | mutex_lock(&dev_priv->fb_tracking.lock); | |
9096 | /* Filter out new bits since rendering started. */ | |
9097 | frontbuffer_bits &= dev_priv->fb_tracking.busy_bits; | |
9098 | ||
9099 | dev_priv->fb_tracking.busy_bits &= ~frontbuffer_bits; | |
9100 | mutex_unlock(&dev_priv->fb_tracking.lock); | |
9101 | } | |
9102 | ||
9103 | intel_frontbuffer_flush(dev, frontbuffer_bits); | |
9104 | } | |
9105 | ||
9106 | /** | |
9107 | * intel_frontbuffer_flip_prepare - prepare asnychronous frontbuffer flip | |
9108 | * @dev: DRM device | |
9109 | * @frontbuffer_bits: frontbuffer plane tracking bits | |
9110 | * | |
9111 | * This function gets called after scheduling a flip on @obj. The actual | |
9112 | * frontbuffer flushing will be delayed until completion is signalled with | |
9113 | * intel_frontbuffer_flip_complete. If an invalidate happens in between this | |
9114 | * flush will be cancelled. | |
9115 | * | |
9116 | * Can be called without any locks held. | |
9117 | */ | |
9118 | void intel_frontbuffer_flip_prepare(struct drm_device *dev, | |
9119 | unsigned frontbuffer_bits) | |
9120 | { | |
9121 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9122 | ||
9123 | mutex_lock(&dev_priv->fb_tracking.lock); | |
9124 | dev_priv->fb_tracking.flip_bits | |
9125 | |= frontbuffer_bits; | |
9126 | mutex_unlock(&dev_priv->fb_tracking.lock); | |
9127 | } | |
9128 | ||
9129 | /** | |
9130 | * intel_frontbuffer_flip_complete - complete asynchronous frontbuffer flush | |
9131 | * @dev: DRM device | |
9132 | * @frontbuffer_bits: frontbuffer plane tracking bits | |
9133 | * | |
9134 | * This function gets called after the flip has been latched and will complete | |
9135 | * on the next vblank. It will execute the fush if it hasn't been cancalled yet. | |
9136 | * | |
9137 | * Can be called without any locks held. | |
9138 | */ | |
9139 | void intel_frontbuffer_flip_complete(struct drm_device *dev, | |
9140 | unsigned frontbuffer_bits) | |
9141 | { | |
9142 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9143 | ||
9144 | mutex_lock(&dev_priv->fb_tracking.lock); | |
9145 | /* Mask any cancelled flips. */ | |
9146 | frontbuffer_bits &= dev_priv->fb_tracking.flip_bits; | |
9147 | dev_priv->fb_tracking.flip_bits &= ~frontbuffer_bits; | |
9148 | mutex_unlock(&dev_priv->fb_tracking.lock); | |
9149 | ||
9150 | intel_frontbuffer_flush(dev, frontbuffer_bits); | |
9151 | } | |
9152 | ||
79e53945 JB |
9153 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
9154 | { | |
9155 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
9156 | struct drm_device *dev = crtc->dev; |
9157 | struct intel_unpin_work *work; | |
9158 | unsigned long flags; | |
9159 | ||
9160 | spin_lock_irqsave(&dev->event_lock, flags); | |
9161 | work = intel_crtc->unpin_work; | |
9162 | intel_crtc->unpin_work = NULL; | |
9163 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
9164 | ||
9165 | if (work) { | |
9166 | cancel_work_sync(&work->work); | |
9167 | kfree(work); | |
9168 | } | |
79e53945 JB |
9169 | |
9170 | drm_crtc_cleanup(crtc); | |
67e77c5a | 9171 | |
79e53945 JB |
9172 | kfree(intel_crtc); |
9173 | } | |
9174 | ||
6b95a207 KH |
9175 | static void intel_unpin_work_fn(struct work_struct *__work) |
9176 | { | |
9177 | struct intel_unpin_work *work = | |
9178 | container_of(__work, struct intel_unpin_work, work); | |
b4a98e57 | 9179 | struct drm_device *dev = work->crtc->dev; |
f99d7069 | 9180 | enum pipe pipe = to_intel_crtc(work->crtc)->pipe; |
6b95a207 | 9181 | |
b4a98e57 | 9182 | mutex_lock(&dev->struct_mutex); |
1690e1eb | 9183 | intel_unpin_fb_obj(work->old_fb_obj); |
05394f39 CW |
9184 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
9185 | drm_gem_object_unreference(&work->old_fb_obj->base); | |
d9e86c0e | 9186 | |
b4a98e57 CW |
9187 | intel_update_fbc(dev); |
9188 | mutex_unlock(&dev->struct_mutex); | |
9189 | ||
f99d7069 DV |
9190 | intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
9191 | ||
b4a98e57 CW |
9192 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); |
9193 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); | |
9194 | ||
6b95a207 KH |
9195 | kfree(work); |
9196 | } | |
9197 | ||
1afe3e9d | 9198 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 9199 | struct drm_crtc *crtc) |
6b95a207 | 9200 | { |
fbee40df | 9201 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
9202 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
9203 | struct intel_unpin_work *work; | |
6b95a207 KH |
9204 | unsigned long flags; |
9205 | ||
9206 | /* Ignore early vblank irqs */ | |
9207 | if (intel_crtc == NULL) | |
9208 | return; | |
9209 | ||
9210 | spin_lock_irqsave(&dev->event_lock, flags); | |
9211 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
9212 | |
9213 | /* Ensure we don't miss a work->pending update ... */ | |
9214 | smp_rmb(); | |
9215 | ||
9216 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
9217 | spin_unlock_irqrestore(&dev->event_lock, flags); |
9218 | return; | |
9219 | } | |
9220 | ||
e7d841ca CW |
9221 | /* and that the unpin work is consistent wrt ->pending. */ |
9222 | smp_rmb(); | |
9223 | ||
6b95a207 | 9224 | intel_crtc->unpin_work = NULL; |
6b95a207 | 9225 | |
45a066eb RC |
9226 | if (work->event) |
9227 | drm_send_vblank_event(dev, intel_crtc->pipe, work->event); | |
6b95a207 | 9228 | |
87b6b101 | 9229 | drm_crtc_vblank_put(crtc); |
0af7e4df | 9230 | |
6b95a207 KH |
9231 | spin_unlock_irqrestore(&dev->event_lock, flags); |
9232 | ||
2c10d571 | 9233 | wake_up_all(&dev_priv->pending_flip_queue); |
b4a98e57 CW |
9234 | |
9235 | queue_work(dev_priv->wq, &work->work); | |
e5510fac JB |
9236 | |
9237 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); | |
6b95a207 KH |
9238 | } |
9239 | ||
1afe3e9d JB |
9240 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
9241 | { | |
fbee40df | 9242 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
9243 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
9244 | ||
49b14a5c | 9245 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
9246 | } |
9247 | ||
9248 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
9249 | { | |
fbee40df | 9250 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
9251 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
9252 | ||
49b14a5c | 9253 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
9254 | } |
9255 | ||
75f7f3ec VS |
9256 | /* Is 'a' after or equal to 'b'? */ |
9257 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
9258 | { | |
9259 | return !((a - b) & 0x80000000); | |
9260 | } | |
9261 | ||
9262 | static bool page_flip_finished(struct intel_crtc *crtc) | |
9263 | { | |
9264 | struct drm_device *dev = crtc->base.dev; | |
9265 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9266 | ||
9267 | /* | |
9268 | * The relevant registers doen't exist on pre-ctg. | |
9269 | * As the flip done interrupt doesn't trigger for mmio | |
9270 | * flips on gmch platforms, a flip count check isn't | |
9271 | * really needed there. But since ctg has the registers, | |
9272 | * include it in the check anyway. | |
9273 | */ | |
9274 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
9275 | return true; | |
9276 | ||
9277 | /* | |
9278 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
9279 | * used the same base address. In that case the mmio flip might | |
9280 | * have completed, but the CS hasn't even executed the flip yet. | |
9281 | * | |
9282 | * A flip count check isn't enough as the CS might have updated | |
9283 | * the base address just after start of vblank, but before we | |
9284 | * managed to process the interrupt. This means we'd complete the | |
9285 | * CS flip too soon. | |
9286 | * | |
9287 | * Combining both checks should get us a good enough result. It may | |
9288 | * still happen that the CS flip has been executed, but has not | |
9289 | * yet actually completed. But in case the base address is the same | |
9290 | * anyway, we don't really care. | |
9291 | */ | |
9292 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
9293 | crtc->unpin_work->gtt_offset && | |
9294 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)), | |
9295 | crtc->unpin_work->flip_count); | |
9296 | } | |
9297 | ||
6b95a207 KH |
9298 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
9299 | { | |
fbee40df | 9300 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
9301 | struct intel_crtc *intel_crtc = |
9302 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
9303 | unsigned long flags; | |
9304 | ||
e7d841ca CW |
9305 | /* NB: An MMIO update of the plane base pointer will also |
9306 | * generate a page-flip completion irq, i.e. every modeset | |
9307 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
9308 | */ | |
6b95a207 | 9309 | spin_lock_irqsave(&dev->event_lock, flags); |
75f7f3ec | 9310 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
e7d841ca | 9311 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
6b95a207 KH |
9312 | spin_unlock_irqrestore(&dev->event_lock, flags); |
9313 | } | |
9314 | ||
eba905b2 | 9315 | static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
e7d841ca CW |
9316 | { |
9317 | /* Ensure that the work item is consistent when activating it ... */ | |
9318 | smp_wmb(); | |
9319 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); | |
9320 | /* and that it is marked active as soon as the irq could fire. */ | |
9321 | smp_wmb(); | |
9322 | } | |
9323 | ||
8c9f3aaf JB |
9324 | static int intel_gen2_queue_flip(struct drm_device *dev, |
9325 | struct drm_crtc *crtc, | |
9326 | struct drm_framebuffer *fb, | |
ed8d1975 | 9327 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9328 | struct intel_engine_cs *ring, |
ed8d1975 | 9329 | uint32_t flags) |
8c9f3aaf | 9330 | { |
8c9f3aaf | 9331 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
9332 | u32 flip_mask; |
9333 | int ret; | |
9334 | ||
6d90c952 | 9335 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 9336 | if (ret) |
4fa62c89 | 9337 | return ret; |
8c9f3aaf JB |
9338 | |
9339 | /* Can't queue multiple flips, so wait for the previous | |
9340 | * one to finish before executing the next. | |
9341 | */ | |
9342 | if (intel_crtc->plane) | |
9343 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
9344 | else | |
9345 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
9346 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
9347 | intel_ring_emit(ring, MI_NOOP); | |
9348 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
9349 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9350 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9351 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 | 9352 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca CW |
9353 | |
9354 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9355 | __intel_ring_advance(ring); |
83d4092b | 9356 | return 0; |
8c9f3aaf JB |
9357 | } |
9358 | ||
9359 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
9360 | struct drm_crtc *crtc, | |
9361 | struct drm_framebuffer *fb, | |
ed8d1975 | 9362 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9363 | struct intel_engine_cs *ring, |
ed8d1975 | 9364 | uint32_t flags) |
8c9f3aaf | 9365 | { |
8c9f3aaf | 9366 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
9367 | u32 flip_mask; |
9368 | int ret; | |
9369 | ||
6d90c952 | 9370 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 9371 | if (ret) |
4fa62c89 | 9372 | return ret; |
8c9f3aaf JB |
9373 | |
9374 | if (intel_crtc->plane) | |
9375 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
9376 | else | |
9377 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
9378 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
9379 | intel_ring_emit(ring, MI_NOOP); | |
9380 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
9381 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9382 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9383 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 DV |
9384 | intel_ring_emit(ring, MI_NOOP); |
9385 | ||
e7d841ca | 9386 | intel_mark_page_flip_active(intel_crtc); |
09246732 | 9387 | __intel_ring_advance(ring); |
83d4092b | 9388 | return 0; |
8c9f3aaf JB |
9389 | } |
9390 | ||
9391 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
9392 | struct drm_crtc *crtc, | |
9393 | struct drm_framebuffer *fb, | |
ed8d1975 | 9394 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9395 | struct intel_engine_cs *ring, |
ed8d1975 | 9396 | uint32_t flags) |
8c9f3aaf JB |
9397 | { |
9398 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9399 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9400 | uint32_t pf, pipesrc; | |
9401 | int ret; | |
9402 | ||
6d90c952 | 9403 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 9404 | if (ret) |
4fa62c89 | 9405 | return ret; |
8c9f3aaf JB |
9406 | |
9407 | /* i965+ uses the linear or tiled offsets from the | |
9408 | * Display Registers (which do not change across a page-flip) | |
9409 | * so we need only reprogram the base address. | |
9410 | */ | |
6d90c952 DV |
9411 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
9412 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9413 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9414 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | |
c2c75131 | 9415 | obj->tiling_mode); |
8c9f3aaf JB |
9416 | |
9417 | /* XXX Enabling the panel-fitter across page-flip is so far | |
9418 | * untested on non-native modes, so ignore it for now. | |
9419 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
9420 | */ | |
9421 | pf = 0; | |
9422 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 9423 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
9424 | |
9425 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9426 | __intel_ring_advance(ring); |
83d4092b | 9427 | return 0; |
8c9f3aaf JB |
9428 | } |
9429 | ||
9430 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
9431 | struct drm_crtc *crtc, | |
9432 | struct drm_framebuffer *fb, | |
ed8d1975 | 9433 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9434 | struct intel_engine_cs *ring, |
ed8d1975 | 9435 | uint32_t flags) |
8c9f3aaf JB |
9436 | { |
9437 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9438 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9439 | uint32_t pf, pipesrc; | |
9440 | int ret; | |
9441 | ||
6d90c952 | 9442 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 9443 | if (ret) |
4fa62c89 | 9444 | return ret; |
8c9f3aaf | 9445 | |
6d90c952 DV |
9446 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
9447 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9448 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
75f7f3ec | 9449 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
8c9f3aaf | 9450 | |
dc257cf1 DV |
9451 | /* Contrary to the suggestions in the documentation, |
9452 | * "Enable Panel Fitter" does not seem to be required when page | |
9453 | * flipping with a non-native mode, and worse causes a normal | |
9454 | * modeset to fail. | |
9455 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
9456 | */ | |
9457 | pf = 0; | |
8c9f3aaf | 9458 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 9459 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
9460 | |
9461 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9462 | __intel_ring_advance(ring); |
83d4092b | 9463 | return 0; |
8c9f3aaf JB |
9464 | } |
9465 | ||
7c9017e5 JB |
9466 | static int intel_gen7_queue_flip(struct drm_device *dev, |
9467 | struct drm_crtc *crtc, | |
9468 | struct drm_framebuffer *fb, | |
ed8d1975 | 9469 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9470 | struct intel_engine_cs *ring, |
ed8d1975 | 9471 | uint32_t flags) |
7c9017e5 | 9472 | { |
7c9017e5 | 9473 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cb05d8de | 9474 | uint32_t plane_bit = 0; |
ffe74d75 CW |
9475 | int len, ret; |
9476 | ||
eba905b2 | 9477 | switch (intel_crtc->plane) { |
cb05d8de DV |
9478 | case PLANE_A: |
9479 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
9480 | break; | |
9481 | case PLANE_B: | |
9482 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
9483 | break; | |
9484 | case PLANE_C: | |
9485 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
9486 | break; | |
9487 | default: | |
9488 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
4fa62c89 | 9489 | return -ENODEV; |
cb05d8de DV |
9490 | } |
9491 | ||
ffe74d75 | 9492 | len = 4; |
f476828a | 9493 | if (ring->id == RCS) { |
ffe74d75 | 9494 | len += 6; |
f476828a DL |
9495 | /* |
9496 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
9497 | * 48bits addresses, and we need a NOOP for the batch size to | |
9498 | * stay even. | |
9499 | */ | |
9500 | if (IS_GEN8(dev)) | |
9501 | len += 2; | |
9502 | } | |
ffe74d75 | 9503 | |
f66fab8e VS |
9504 | /* |
9505 | * BSpec MI_DISPLAY_FLIP for IVB: | |
9506 | * "The full packet must be contained within the same cache line." | |
9507 | * | |
9508 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
9509 | * cacheline, if we ever start emitting more commands before | |
9510 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
9511 | * then do the cacheline alignment, and finally emit the | |
9512 | * MI_DISPLAY_FLIP. | |
9513 | */ | |
9514 | ret = intel_ring_cacheline_align(ring); | |
9515 | if (ret) | |
4fa62c89 | 9516 | return ret; |
f66fab8e | 9517 | |
ffe74d75 | 9518 | ret = intel_ring_begin(ring, len); |
7c9017e5 | 9519 | if (ret) |
4fa62c89 | 9520 | return ret; |
7c9017e5 | 9521 | |
ffe74d75 CW |
9522 | /* Unmask the flip-done completion message. Note that the bspec says that |
9523 | * we should do this for both the BCS and RCS, and that we must not unmask | |
9524 | * more than one flip event at any time (or ensure that one flip message | |
9525 | * can be sent by waiting for flip-done prior to queueing new flips). | |
9526 | * Experimentation says that BCS works despite DERRMR masking all | |
9527 | * flip-done completion events and that unmasking all planes at once | |
9528 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
9529 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
9530 | */ | |
9531 | if (ring->id == RCS) { | |
9532 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
9533 | intel_ring_emit(ring, DERRMR); | |
9534 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
9535 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
9536 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
f476828a DL |
9537 | if (IS_GEN8(dev)) |
9538 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) | | |
9539 | MI_SRM_LRM_GLOBAL_GTT); | |
9540 | else | |
9541 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | | |
9542 | MI_SRM_LRM_GLOBAL_GTT); | |
ffe74d75 CW |
9543 | intel_ring_emit(ring, DERRMR); |
9544 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
f476828a DL |
9545 | if (IS_GEN8(dev)) { |
9546 | intel_ring_emit(ring, 0); | |
9547 | intel_ring_emit(ring, MI_NOOP); | |
9548 | } | |
ffe74d75 CW |
9549 | } |
9550 | ||
cb05d8de | 9551 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 9552 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
75f7f3ec | 9553 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
7c9017e5 | 9554 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca CW |
9555 | |
9556 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9557 | __intel_ring_advance(ring); |
83d4092b | 9558 | return 0; |
7c9017e5 JB |
9559 | } |
9560 | ||
84c33a64 SG |
9561 | static bool use_mmio_flip(struct intel_engine_cs *ring, |
9562 | struct drm_i915_gem_object *obj) | |
9563 | { | |
9564 | /* | |
9565 | * This is not being used for older platforms, because | |
9566 | * non-availability of flip done interrupt forces us to use | |
9567 | * CS flips. Older platforms derive flip done using some clever | |
9568 | * tricks involving the flip_pending status bits and vblank irqs. | |
9569 | * So using MMIO flips there would disrupt this mechanism. | |
9570 | */ | |
9571 | ||
8e09bf83 CW |
9572 | if (ring == NULL) |
9573 | return true; | |
9574 | ||
84c33a64 SG |
9575 | if (INTEL_INFO(ring->dev)->gen < 5) |
9576 | return false; | |
9577 | ||
9578 | if (i915.use_mmio_flip < 0) | |
9579 | return false; | |
9580 | else if (i915.use_mmio_flip > 0) | |
9581 | return true; | |
9582 | else | |
9583 | return ring != obj->ring; | |
9584 | } | |
9585 | ||
9586 | static void intel_do_mmio_flip(struct intel_crtc *intel_crtc) | |
9587 | { | |
9588 | struct drm_device *dev = intel_crtc->base.dev; | |
9589 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9590 | struct intel_framebuffer *intel_fb = | |
9591 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
9592 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
9593 | u32 dspcntr; | |
9594 | u32 reg; | |
9595 | ||
9596 | intel_mark_page_flip_active(intel_crtc); | |
9597 | ||
9598 | reg = DSPCNTR(intel_crtc->plane); | |
9599 | dspcntr = I915_READ(reg); | |
9600 | ||
9601 | if (INTEL_INFO(dev)->gen >= 4) { | |
9602 | if (obj->tiling_mode != I915_TILING_NONE) | |
9603 | dspcntr |= DISPPLANE_TILED; | |
9604 | else | |
9605 | dspcntr &= ~DISPPLANE_TILED; | |
9606 | } | |
9607 | I915_WRITE(reg, dspcntr); | |
9608 | ||
9609 | I915_WRITE(DSPSURF(intel_crtc->plane), | |
9610 | intel_crtc->unpin_work->gtt_offset); | |
9611 | POSTING_READ(DSPSURF(intel_crtc->plane)); | |
9612 | } | |
9613 | ||
9614 | static int intel_postpone_flip(struct drm_i915_gem_object *obj) | |
9615 | { | |
9616 | struct intel_engine_cs *ring; | |
9617 | int ret; | |
9618 | ||
9619 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
9620 | ||
9621 | if (!obj->last_write_seqno) | |
9622 | return 0; | |
9623 | ||
9624 | ring = obj->ring; | |
9625 | ||
9626 | if (i915_seqno_passed(ring->get_seqno(ring, true), | |
9627 | obj->last_write_seqno)) | |
9628 | return 0; | |
9629 | ||
9630 | ret = i915_gem_check_olr(ring, obj->last_write_seqno); | |
9631 | if (ret) | |
9632 | return ret; | |
9633 | ||
9634 | if (WARN_ON(!ring->irq_get(ring))) | |
9635 | return 0; | |
9636 | ||
9637 | return 1; | |
9638 | } | |
9639 | ||
9640 | void intel_notify_mmio_flip(struct intel_engine_cs *ring) | |
9641 | { | |
9642 | struct drm_i915_private *dev_priv = to_i915(ring->dev); | |
9643 | struct intel_crtc *intel_crtc; | |
9644 | unsigned long irq_flags; | |
9645 | u32 seqno; | |
9646 | ||
9647 | seqno = ring->get_seqno(ring, false); | |
9648 | ||
9649 | spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags); | |
9650 | for_each_intel_crtc(ring->dev, intel_crtc) { | |
9651 | struct intel_mmio_flip *mmio_flip; | |
9652 | ||
9653 | mmio_flip = &intel_crtc->mmio_flip; | |
9654 | if (mmio_flip->seqno == 0) | |
9655 | continue; | |
9656 | ||
9657 | if (ring->id != mmio_flip->ring_id) | |
9658 | continue; | |
9659 | ||
9660 | if (i915_seqno_passed(seqno, mmio_flip->seqno)) { | |
9661 | intel_do_mmio_flip(intel_crtc); | |
9662 | mmio_flip->seqno = 0; | |
9663 | ring->irq_put(ring); | |
9664 | } | |
9665 | } | |
9666 | spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags); | |
9667 | } | |
9668 | ||
9669 | static int intel_queue_mmio_flip(struct drm_device *dev, | |
9670 | struct drm_crtc *crtc, | |
9671 | struct drm_framebuffer *fb, | |
9672 | struct drm_i915_gem_object *obj, | |
9673 | struct intel_engine_cs *ring, | |
9674 | uint32_t flags) | |
9675 | { | |
9676 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9677 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9678 | unsigned long irq_flags; | |
9679 | int ret; | |
9680 | ||
9681 | if (WARN_ON(intel_crtc->mmio_flip.seqno)) | |
9682 | return -EBUSY; | |
9683 | ||
9684 | ret = intel_postpone_flip(obj); | |
9685 | if (ret < 0) | |
9686 | return ret; | |
9687 | if (ret == 0) { | |
9688 | intel_do_mmio_flip(intel_crtc); | |
9689 | return 0; | |
9690 | } | |
9691 | ||
9692 | spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags); | |
9693 | intel_crtc->mmio_flip.seqno = obj->last_write_seqno; | |
9694 | intel_crtc->mmio_flip.ring_id = obj->ring->id; | |
9695 | spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags); | |
9696 | ||
9697 | /* | |
9698 | * Double check to catch cases where irq fired before | |
9699 | * mmio flip data was ready | |
9700 | */ | |
9701 | intel_notify_mmio_flip(obj->ring); | |
9702 | return 0; | |
9703 | } | |
9704 | ||
8c9f3aaf JB |
9705 | static int intel_default_queue_flip(struct drm_device *dev, |
9706 | struct drm_crtc *crtc, | |
9707 | struct drm_framebuffer *fb, | |
ed8d1975 | 9708 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9709 | struct intel_engine_cs *ring, |
ed8d1975 | 9710 | uint32_t flags) |
8c9f3aaf JB |
9711 | { |
9712 | return -ENODEV; | |
9713 | } | |
9714 | ||
6b95a207 KH |
9715 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
9716 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
9717 | struct drm_pending_vblank_event *event, |
9718 | uint32_t page_flip_flags) | |
6b95a207 KH |
9719 | { |
9720 | struct drm_device *dev = crtc->dev; | |
9721 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 9722 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
2ff8fde1 | 9723 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
6b95a207 | 9724 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
a071fa00 | 9725 | enum pipe pipe = intel_crtc->pipe; |
6b95a207 | 9726 | struct intel_unpin_work *work; |
a4872ba6 | 9727 | struct intel_engine_cs *ring; |
8c9f3aaf | 9728 | unsigned long flags; |
52e68630 | 9729 | int ret; |
6b95a207 | 9730 | |
2ff8fde1 MR |
9731 | /* |
9732 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
9733 | * check to be safe. In the future we may enable pageflipping from | |
9734 | * a disabled primary plane. | |
9735 | */ | |
9736 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
9737 | return -EBUSY; | |
9738 | ||
e6a595d2 | 9739 | /* Can't change pixel format via MI display flips. */ |
f4510a27 | 9740 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
e6a595d2 VS |
9741 | return -EINVAL; |
9742 | ||
9743 | /* | |
9744 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
9745 | * Note that pitch changes could also affect these register. | |
9746 | */ | |
9747 | if (INTEL_INFO(dev)->gen > 3 && | |
f4510a27 MR |
9748 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
9749 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
e6a595d2 VS |
9750 | return -EINVAL; |
9751 | ||
f900db47 CW |
9752 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
9753 | goto out_hang; | |
9754 | ||
b14c5679 | 9755 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
9756 | if (work == NULL) |
9757 | return -ENOMEM; | |
9758 | ||
6b95a207 | 9759 | work->event = event; |
b4a98e57 | 9760 | work->crtc = crtc; |
2ff8fde1 | 9761 | work->old_fb_obj = intel_fb_obj(old_fb); |
6b95a207 KH |
9762 | INIT_WORK(&work->work, intel_unpin_work_fn); |
9763 | ||
87b6b101 | 9764 | ret = drm_crtc_vblank_get(crtc); |
7317c75e JB |
9765 | if (ret) |
9766 | goto free_work; | |
9767 | ||
6b95a207 KH |
9768 | /* We borrow the event spin lock for protecting unpin_work */ |
9769 | spin_lock_irqsave(&dev->event_lock, flags); | |
9770 | if (intel_crtc->unpin_work) { | |
9771 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
9772 | kfree(work); | |
87b6b101 | 9773 | drm_crtc_vblank_put(crtc); |
468f0b44 CW |
9774 | |
9775 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
6b95a207 KH |
9776 | return -EBUSY; |
9777 | } | |
9778 | intel_crtc->unpin_work = work; | |
9779 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
9780 | ||
b4a98e57 CW |
9781 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
9782 | flush_workqueue(dev_priv->wq); | |
9783 | ||
79158103 CW |
9784 | ret = i915_mutex_lock_interruptible(dev); |
9785 | if (ret) | |
9786 | goto cleanup; | |
6b95a207 | 9787 | |
75dfca80 | 9788 | /* Reference the objects for the scheduled work. */ |
05394f39 CW |
9789 | drm_gem_object_reference(&work->old_fb_obj->base); |
9790 | drm_gem_object_reference(&obj->base); | |
6b95a207 | 9791 | |
f4510a27 | 9792 | crtc->primary->fb = fb; |
96b099fd | 9793 | |
e1f99ce6 | 9794 | work->pending_flip_obj = obj; |
e1f99ce6 | 9795 | |
4e5359cd SF |
9796 | work->enable_stall_check = true; |
9797 | ||
b4a98e57 | 9798 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 9799 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 9800 | |
75f7f3ec | 9801 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
a071fa00 | 9802 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1; |
75f7f3ec | 9803 | |
4fa62c89 VS |
9804 | if (IS_VALLEYVIEW(dev)) { |
9805 | ring = &dev_priv->ring[BCS]; | |
8e09bf83 CW |
9806 | if (obj->tiling_mode != work->old_fb_obj->tiling_mode) |
9807 | /* vlv: DISPLAY_FLIP fails to change tiling */ | |
9808 | ring = NULL; | |
2a92d5bc CW |
9809 | } else if (IS_IVYBRIDGE(dev)) { |
9810 | ring = &dev_priv->ring[BCS]; | |
4fa62c89 VS |
9811 | } else if (INTEL_INFO(dev)->gen >= 7) { |
9812 | ring = obj->ring; | |
9813 | if (ring == NULL || ring->id != RCS) | |
9814 | ring = &dev_priv->ring[BCS]; | |
9815 | } else { | |
9816 | ring = &dev_priv->ring[RCS]; | |
9817 | } | |
9818 | ||
9819 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); | |
8c9f3aaf JB |
9820 | if (ret) |
9821 | goto cleanup_pending; | |
6b95a207 | 9822 | |
4fa62c89 VS |
9823 | work->gtt_offset = |
9824 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset; | |
9825 | ||
84c33a64 SG |
9826 | if (use_mmio_flip(ring, obj)) |
9827 | ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring, | |
9828 | page_flip_flags); | |
9829 | else | |
9830 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring, | |
9831 | page_flip_flags); | |
4fa62c89 VS |
9832 | if (ret) |
9833 | goto cleanup_unpin; | |
9834 | ||
a071fa00 DV |
9835 | i915_gem_track_fb(work->old_fb_obj, obj, |
9836 | INTEL_FRONTBUFFER_PRIMARY(pipe)); | |
9837 | ||
7782de3b | 9838 | intel_disable_fbc(dev); |
f99d7069 | 9839 | intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
6b95a207 KH |
9840 | mutex_unlock(&dev->struct_mutex); |
9841 | ||
e5510fac JB |
9842 | trace_i915_flip_request(intel_crtc->plane, obj); |
9843 | ||
6b95a207 | 9844 | return 0; |
96b099fd | 9845 | |
4fa62c89 VS |
9846 | cleanup_unpin: |
9847 | intel_unpin_fb_obj(obj); | |
8c9f3aaf | 9848 | cleanup_pending: |
b4a98e57 | 9849 | atomic_dec(&intel_crtc->unpin_work_count); |
f4510a27 | 9850 | crtc->primary->fb = old_fb; |
05394f39 CW |
9851 | drm_gem_object_unreference(&work->old_fb_obj->base); |
9852 | drm_gem_object_unreference(&obj->base); | |
96b099fd CW |
9853 | mutex_unlock(&dev->struct_mutex); |
9854 | ||
79158103 | 9855 | cleanup: |
96b099fd CW |
9856 | spin_lock_irqsave(&dev->event_lock, flags); |
9857 | intel_crtc->unpin_work = NULL; | |
9858 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
9859 | ||
87b6b101 | 9860 | drm_crtc_vblank_put(crtc); |
7317c75e | 9861 | free_work: |
96b099fd CW |
9862 | kfree(work); |
9863 | ||
f900db47 CW |
9864 | if (ret == -EIO) { |
9865 | out_hang: | |
9866 | intel_crtc_wait_for_pending_flips(crtc); | |
9867 | ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb); | |
9868 | if (ret == 0 && event) | |
a071fa00 | 9869 | drm_send_vblank_event(dev, pipe, event); |
f900db47 | 9870 | } |
96b099fd | 9871 | return ret; |
6b95a207 KH |
9872 | } |
9873 | ||
f6e5b160 | 9874 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
9875 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
9876 | .load_lut = intel_crtc_load_lut, | |
f6e5b160 CW |
9877 | }; |
9878 | ||
9a935856 DV |
9879 | /** |
9880 | * intel_modeset_update_staged_output_state | |
9881 | * | |
9882 | * Updates the staged output configuration state, e.g. after we've read out the | |
9883 | * current hw state. | |
9884 | */ | |
9885 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) | |
f6e5b160 | 9886 | { |
7668851f | 9887 | struct intel_crtc *crtc; |
9a935856 DV |
9888 | struct intel_encoder *encoder; |
9889 | struct intel_connector *connector; | |
f6e5b160 | 9890 | |
9a935856 DV |
9891 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9892 | base.head) { | |
9893 | connector->new_encoder = | |
9894 | to_intel_encoder(connector->base.encoder); | |
9895 | } | |
f6e5b160 | 9896 | |
9a935856 DV |
9897 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9898 | base.head) { | |
9899 | encoder->new_crtc = | |
9900 | to_intel_crtc(encoder->base.crtc); | |
9901 | } | |
7668851f | 9902 | |
d3fcc808 | 9903 | for_each_intel_crtc(dev, crtc) { |
7668851f | 9904 | crtc->new_enabled = crtc->base.enabled; |
7bd0a8e7 VS |
9905 | |
9906 | if (crtc->new_enabled) | |
9907 | crtc->new_config = &crtc->config; | |
9908 | else | |
9909 | crtc->new_config = NULL; | |
7668851f | 9910 | } |
f6e5b160 CW |
9911 | } |
9912 | ||
9a935856 DV |
9913 | /** |
9914 | * intel_modeset_commit_output_state | |
9915 | * | |
9916 | * This function copies the stage display pipe configuration to the real one. | |
9917 | */ | |
9918 | static void intel_modeset_commit_output_state(struct drm_device *dev) | |
9919 | { | |
7668851f | 9920 | struct intel_crtc *crtc; |
9a935856 DV |
9921 | struct intel_encoder *encoder; |
9922 | struct intel_connector *connector; | |
f6e5b160 | 9923 | |
9a935856 DV |
9924 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9925 | base.head) { | |
9926 | connector->base.encoder = &connector->new_encoder->base; | |
9927 | } | |
f6e5b160 | 9928 | |
9a935856 DV |
9929 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9930 | base.head) { | |
9931 | encoder->base.crtc = &encoder->new_crtc->base; | |
9932 | } | |
7668851f | 9933 | |
d3fcc808 | 9934 | for_each_intel_crtc(dev, crtc) { |
7668851f VS |
9935 | crtc->base.enabled = crtc->new_enabled; |
9936 | } | |
9a935856 DV |
9937 | } |
9938 | ||
050f7aeb | 9939 | static void |
eba905b2 | 9940 | connected_sink_compute_bpp(struct intel_connector *connector, |
050f7aeb DV |
9941 | struct intel_crtc_config *pipe_config) |
9942 | { | |
9943 | int bpp = pipe_config->pipe_bpp; | |
9944 | ||
9945 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
9946 | connector->base.base.id, | |
c23cc417 | 9947 | connector->base.name); |
050f7aeb DV |
9948 | |
9949 | /* Don't use an invalid EDID bpc value */ | |
9950 | if (connector->base.display_info.bpc && | |
9951 | connector->base.display_info.bpc * 3 < bpp) { | |
9952 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
9953 | bpp, connector->base.display_info.bpc*3); | |
9954 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
9955 | } | |
9956 | ||
9957 | /* Clamp bpp to 8 on screens without EDID 1.4 */ | |
9958 | if (connector->base.display_info.bpc == 0 && bpp > 24) { | |
9959 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", | |
9960 | bpp); | |
9961 | pipe_config->pipe_bpp = 24; | |
9962 | } | |
9963 | } | |
9964 | ||
4e53c2e0 | 9965 | static int |
050f7aeb DV |
9966 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
9967 | struct drm_framebuffer *fb, | |
9968 | struct intel_crtc_config *pipe_config) | |
4e53c2e0 | 9969 | { |
050f7aeb DV |
9970 | struct drm_device *dev = crtc->base.dev; |
9971 | struct intel_connector *connector; | |
4e53c2e0 DV |
9972 | int bpp; |
9973 | ||
d42264b1 DV |
9974 | switch (fb->pixel_format) { |
9975 | case DRM_FORMAT_C8: | |
4e53c2e0 DV |
9976 | bpp = 8*3; /* since we go through a colormap */ |
9977 | break; | |
d42264b1 DV |
9978 | case DRM_FORMAT_XRGB1555: |
9979 | case DRM_FORMAT_ARGB1555: | |
9980 | /* checked in intel_framebuffer_init already */ | |
9981 | if (WARN_ON(INTEL_INFO(dev)->gen > 3)) | |
9982 | return -EINVAL; | |
9983 | case DRM_FORMAT_RGB565: | |
4e53c2e0 DV |
9984 | bpp = 6*3; /* min is 18bpp */ |
9985 | break; | |
d42264b1 DV |
9986 | case DRM_FORMAT_XBGR8888: |
9987 | case DRM_FORMAT_ABGR8888: | |
9988 | /* checked in intel_framebuffer_init already */ | |
9989 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
9990 | return -EINVAL; | |
9991 | case DRM_FORMAT_XRGB8888: | |
9992 | case DRM_FORMAT_ARGB8888: | |
4e53c2e0 DV |
9993 | bpp = 8*3; |
9994 | break; | |
d42264b1 DV |
9995 | case DRM_FORMAT_XRGB2101010: |
9996 | case DRM_FORMAT_ARGB2101010: | |
9997 | case DRM_FORMAT_XBGR2101010: | |
9998 | case DRM_FORMAT_ABGR2101010: | |
9999 | /* checked in intel_framebuffer_init already */ | |
10000 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
baba133a | 10001 | return -EINVAL; |
4e53c2e0 DV |
10002 | bpp = 10*3; |
10003 | break; | |
baba133a | 10004 | /* TODO: gen4+ supports 16 bpc floating point, too. */ |
4e53c2e0 DV |
10005 | default: |
10006 | DRM_DEBUG_KMS("unsupported depth\n"); | |
10007 | return -EINVAL; | |
10008 | } | |
10009 | ||
4e53c2e0 DV |
10010 | pipe_config->pipe_bpp = bpp; |
10011 | ||
10012 | /* Clamp display bpp to EDID value */ | |
10013 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
050f7aeb | 10014 | base.head) { |
1b829e05 DV |
10015 | if (!connector->new_encoder || |
10016 | connector->new_encoder->new_crtc != crtc) | |
4e53c2e0 DV |
10017 | continue; |
10018 | ||
050f7aeb | 10019 | connected_sink_compute_bpp(connector, pipe_config); |
4e53c2e0 DV |
10020 | } |
10021 | ||
10022 | return bpp; | |
10023 | } | |
10024 | ||
644db711 DV |
10025 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
10026 | { | |
10027 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
10028 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 10029 | mode->crtc_clock, |
644db711 DV |
10030 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
10031 | mode->crtc_hsync_end, mode->crtc_htotal, | |
10032 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
10033 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
10034 | } | |
10035 | ||
c0b03411 DV |
10036 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
10037 | struct intel_crtc_config *pipe_config, | |
10038 | const char *context) | |
10039 | { | |
10040 | DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id, | |
10041 | context, pipe_name(crtc->pipe)); | |
10042 | ||
10043 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
10044 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
10045 | pipe_config->pipe_bpp, pipe_config->dither); | |
10046 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
10047 | pipe_config->has_pch_encoder, | |
10048 | pipe_config->fdi_lanes, | |
10049 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
10050 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
10051 | pipe_config->fdi_m_n.tu); | |
eb14cb74 VS |
10052 | DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
10053 | pipe_config->has_dp_encoder, | |
10054 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, | |
10055 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
10056 | pipe_config->dp_m_n.tu); | |
b95af8be VK |
10057 | |
10058 | DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", | |
10059 | pipe_config->has_dp_encoder, | |
10060 | pipe_config->dp_m2_n2.gmch_m, | |
10061 | pipe_config->dp_m2_n2.gmch_n, | |
10062 | pipe_config->dp_m2_n2.link_m, | |
10063 | pipe_config->dp_m2_n2.link_n, | |
10064 | pipe_config->dp_m2_n2.tu); | |
10065 | ||
c0b03411 DV |
10066 | DRM_DEBUG_KMS("requested mode:\n"); |
10067 | drm_mode_debug_printmodeline(&pipe_config->requested_mode); | |
10068 | DRM_DEBUG_KMS("adjusted mode:\n"); | |
10069 | drm_mode_debug_printmodeline(&pipe_config->adjusted_mode); | |
644db711 | 10070 | intel_dump_crtc_timings(&pipe_config->adjusted_mode); |
d71b8d4a | 10071 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
10072 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
10073 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
c0b03411 DV |
10074 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
10075 | pipe_config->gmch_pfit.control, | |
10076 | pipe_config->gmch_pfit.pgm_ratios, | |
10077 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 10078 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 10079 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
10080 | pipe_config->pch_pfit.size, |
10081 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 10082 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 10083 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
c0b03411 DV |
10084 | } |
10085 | ||
bc079e8b VS |
10086 | static bool encoders_cloneable(const struct intel_encoder *a, |
10087 | const struct intel_encoder *b) | |
accfc0c5 | 10088 | { |
bc079e8b VS |
10089 | /* masks could be asymmetric, so check both ways */ |
10090 | return a == b || (a->cloneable & (1 << b->type) && | |
10091 | b->cloneable & (1 << a->type)); | |
10092 | } | |
10093 | ||
10094 | static bool check_single_encoder_cloning(struct intel_crtc *crtc, | |
10095 | struct intel_encoder *encoder) | |
10096 | { | |
10097 | struct drm_device *dev = crtc->base.dev; | |
10098 | struct intel_encoder *source_encoder; | |
10099 | ||
10100 | list_for_each_entry(source_encoder, | |
10101 | &dev->mode_config.encoder_list, base.head) { | |
10102 | if (source_encoder->new_crtc != crtc) | |
10103 | continue; | |
10104 | ||
10105 | if (!encoders_cloneable(encoder, source_encoder)) | |
10106 | return false; | |
10107 | } | |
10108 | ||
10109 | return true; | |
10110 | } | |
10111 | ||
10112 | static bool check_encoder_cloning(struct intel_crtc *crtc) | |
10113 | { | |
10114 | struct drm_device *dev = crtc->base.dev; | |
accfc0c5 DV |
10115 | struct intel_encoder *encoder; |
10116 | ||
bc079e8b VS |
10117 | list_for_each_entry(encoder, |
10118 | &dev->mode_config.encoder_list, base.head) { | |
10119 | if (encoder->new_crtc != crtc) | |
accfc0c5 DV |
10120 | continue; |
10121 | ||
bc079e8b VS |
10122 | if (!check_single_encoder_cloning(crtc, encoder)) |
10123 | return false; | |
accfc0c5 DV |
10124 | } |
10125 | ||
bc079e8b | 10126 | return true; |
accfc0c5 DV |
10127 | } |
10128 | ||
b8cecdf5 DV |
10129 | static struct intel_crtc_config * |
10130 | intel_modeset_pipe_config(struct drm_crtc *crtc, | |
4e53c2e0 | 10131 | struct drm_framebuffer *fb, |
b8cecdf5 | 10132 | struct drm_display_mode *mode) |
ee7b9f93 | 10133 | { |
7758a113 | 10134 | struct drm_device *dev = crtc->dev; |
7758a113 | 10135 | struct intel_encoder *encoder; |
b8cecdf5 | 10136 | struct intel_crtc_config *pipe_config; |
e29c22c0 DV |
10137 | int plane_bpp, ret = -EINVAL; |
10138 | bool retry = true; | |
ee7b9f93 | 10139 | |
bc079e8b | 10140 | if (!check_encoder_cloning(to_intel_crtc(crtc))) { |
accfc0c5 DV |
10141 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); |
10142 | return ERR_PTR(-EINVAL); | |
10143 | } | |
10144 | ||
b8cecdf5 DV |
10145 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
10146 | if (!pipe_config) | |
7758a113 DV |
10147 | return ERR_PTR(-ENOMEM); |
10148 | ||
b8cecdf5 DV |
10149 | drm_mode_copy(&pipe_config->adjusted_mode, mode); |
10150 | drm_mode_copy(&pipe_config->requested_mode, mode); | |
37327abd | 10151 | |
e143a21c DV |
10152 | pipe_config->cpu_transcoder = |
10153 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
c0d43d62 | 10154 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
b8cecdf5 | 10155 | |
2960bc9c ID |
10156 | /* |
10157 | * Sanitize sync polarity flags based on requested ones. If neither | |
10158 | * positive or negative polarity is requested, treat this as meaning | |
10159 | * negative polarity. | |
10160 | */ | |
10161 | if (!(pipe_config->adjusted_mode.flags & | |
10162 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) | |
10163 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; | |
10164 | ||
10165 | if (!(pipe_config->adjusted_mode.flags & | |
10166 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) | |
10167 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; | |
10168 | ||
050f7aeb DV |
10169 | /* Compute a starting value for pipe_config->pipe_bpp taking the source |
10170 | * plane pixel format and any sink constraints into account. Returns the | |
10171 | * source plane bpp so that dithering can be selected on mismatches | |
10172 | * after encoders and crtc also have had their say. */ | |
10173 | plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), | |
10174 | fb, pipe_config); | |
4e53c2e0 DV |
10175 | if (plane_bpp < 0) |
10176 | goto fail; | |
10177 | ||
e41a56be VS |
10178 | /* |
10179 | * Determine the real pipe dimensions. Note that stereo modes can | |
10180 | * increase the actual pipe size due to the frame doubling and | |
10181 | * insertion of additional space for blanks between the frame. This | |
10182 | * is stored in the crtc timings. We use the requested mode to do this | |
10183 | * computation to clearly distinguish it from the adjusted mode, which | |
10184 | * can be changed by the connectors in the below retry loop. | |
10185 | */ | |
10186 | drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE); | |
10187 | pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay; | |
10188 | pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay; | |
10189 | ||
e29c22c0 | 10190 | encoder_retry: |
ef1b460d | 10191 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 10192 | pipe_config->port_clock = 0; |
ef1b460d | 10193 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 10194 | |
135c81b8 | 10195 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
6ce70f5e | 10196 | drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE); |
135c81b8 | 10197 | |
7758a113 DV |
10198 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
10199 | * adjust it according to limitations or connector properties, and also | |
10200 | * a chance to reject the mode entirely. | |
47f1c6c9 | 10201 | */ |
7758a113 DV |
10202 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
10203 | base.head) { | |
47f1c6c9 | 10204 | |
7758a113 DV |
10205 | if (&encoder->new_crtc->base != crtc) |
10206 | continue; | |
7ae89233 | 10207 | |
efea6e8e DV |
10208 | if (!(encoder->compute_config(encoder, pipe_config))) { |
10209 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
10210 | goto fail; |
10211 | } | |
ee7b9f93 | 10212 | } |
47f1c6c9 | 10213 | |
ff9a6750 DV |
10214 | /* Set default port clock if not overwritten by the encoder. Needs to be |
10215 | * done afterwards in case the encoder adjusts the mode. */ | |
10216 | if (!pipe_config->port_clock) | |
241bfc38 DL |
10217 | pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock |
10218 | * pipe_config->pixel_multiplier; | |
ff9a6750 | 10219 | |
a43f6e0f | 10220 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 10221 | if (ret < 0) { |
7758a113 DV |
10222 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
10223 | goto fail; | |
ee7b9f93 | 10224 | } |
e29c22c0 DV |
10225 | |
10226 | if (ret == RETRY) { | |
10227 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
10228 | ret = -EINVAL; | |
10229 | goto fail; | |
10230 | } | |
10231 | ||
10232 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
10233 | retry = false; | |
10234 | goto encoder_retry; | |
10235 | } | |
10236 | ||
4e53c2e0 DV |
10237 | pipe_config->dither = pipe_config->pipe_bpp != plane_bpp; |
10238 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", | |
10239 | plane_bpp, pipe_config->pipe_bpp, pipe_config->dither); | |
10240 | ||
b8cecdf5 | 10241 | return pipe_config; |
7758a113 | 10242 | fail: |
b8cecdf5 | 10243 | kfree(pipe_config); |
e29c22c0 | 10244 | return ERR_PTR(ret); |
ee7b9f93 | 10245 | } |
47f1c6c9 | 10246 | |
e2e1ed41 DV |
10247 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
10248 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ | |
10249 | static void | |
10250 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, | |
10251 | unsigned *prepare_pipes, unsigned *disable_pipes) | |
79e53945 JB |
10252 | { |
10253 | struct intel_crtc *intel_crtc; | |
e2e1ed41 DV |
10254 | struct drm_device *dev = crtc->dev; |
10255 | struct intel_encoder *encoder; | |
10256 | struct intel_connector *connector; | |
10257 | struct drm_crtc *tmp_crtc; | |
79e53945 | 10258 | |
e2e1ed41 | 10259 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
79e53945 | 10260 | |
e2e1ed41 DV |
10261 | /* Check which crtcs have changed outputs connected to them, these need |
10262 | * to be part of the prepare_pipes mask. We don't (yet) support global | |
10263 | * modeset across multiple crtcs, so modeset_pipes will only have one | |
10264 | * bit set at most. */ | |
10265 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
10266 | base.head) { | |
10267 | if (connector->base.encoder == &connector->new_encoder->base) | |
10268 | continue; | |
79e53945 | 10269 | |
e2e1ed41 DV |
10270 | if (connector->base.encoder) { |
10271 | tmp_crtc = connector->base.encoder->crtc; | |
10272 | ||
10273 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
10274 | } | |
10275 | ||
10276 | if (connector->new_encoder) | |
10277 | *prepare_pipes |= | |
10278 | 1 << connector->new_encoder->new_crtc->pipe; | |
79e53945 JB |
10279 | } |
10280 | ||
e2e1ed41 DV |
10281 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
10282 | base.head) { | |
10283 | if (encoder->base.crtc == &encoder->new_crtc->base) | |
10284 | continue; | |
10285 | ||
10286 | if (encoder->base.crtc) { | |
10287 | tmp_crtc = encoder->base.crtc; | |
10288 | ||
10289 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
10290 | } | |
10291 | ||
10292 | if (encoder->new_crtc) | |
10293 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; | |
80824003 JB |
10294 | } |
10295 | ||
7668851f | 10296 | /* Check for pipes that will be enabled/disabled ... */ |
d3fcc808 | 10297 | for_each_intel_crtc(dev, intel_crtc) { |
7668851f | 10298 | if (intel_crtc->base.enabled == intel_crtc->new_enabled) |
e2e1ed41 | 10299 | continue; |
7e7d76c3 | 10300 | |
7668851f | 10301 | if (!intel_crtc->new_enabled) |
e2e1ed41 | 10302 | *disable_pipes |= 1 << intel_crtc->pipe; |
7668851f VS |
10303 | else |
10304 | *prepare_pipes |= 1 << intel_crtc->pipe; | |
7e7d76c3 JB |
10305 | } |
10306 | ||
e2e1ed41 DV |
10307 | |
10308 | /* set_mode is also used to update properties on life display pipes. */ | |
10309 | intel_crtc = to_intel_crtc(crtc); | |
7668851f | 10310 | if (intel_crtc->new_enabled) |
e2e1ed41 DV |
10311 | *prepare_pipes |= 1 << intel_crtc->pipe; |
10312 | ||
b6c5164d DV |
10313 | /* |
10314 | * For simplicity do a full modeset on any pipe where the output routing | |
10315 | * changed. We could be more clever, but that would require us to be | |
10316 | * more careful with calling the relevant encoder->mode_set functions. | |
10317 | */ | |
e2e1ed41 DV |
10318 | if (*prepare_pipes) |
10319 | *modeset_pipes = *prepare_pipes; | |
10320 | ||
10321 | /* ... and mask these out. */ | |
10322 | *modeset_pipes &= ~(*disable_pipes); | |
10323 | *prepare_pipes &= ~(*disable_pipes); | |
b6c5164d DV |
10324 | |
10325 | /* | |
10326 | * HACK: We don't (yet) fully support global modesets. intel_set_config | |
10327 | * obies this rule, but the modeset restore mode of | |
10328 | * intel_modeset_setup_hw_state does not. | |
10329 | */ | |
10330 | *modeset_pipes &= 1 << intel_crtc->pipe; | |
10331 | *prepare_pipes &= 1 << intel_crtc->pipe; | |
e3641d3f DV |
10332 | |
10333 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", | |
10334 | *modeset_pipes, *prepare_pipes, *disable_pipes); | |
47f1c6c9 | 10335 | } |
79e53945 | 10336 | |
ea9d758d | 10337 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
f6e5b160 | 10338 | { |
ea9d758d | 10339 | struct drm_encoder *encoder; |
f6e5b160 | 10340 | struct drm_device *dev = crtc->dev; |
f6e5b160 | 10341 | |
ea9d758d DV |
10342 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
10343 | if (encoder->crtc == crtc) | |
10344 | return true; | |
10345 | ||
10346 | return false; | |
10347 | } | |
10348 | ||
10349 | static void | |
10350 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) | |
10351 | { | |
10352 | struct intel_encoder *intel_encoder; | |
10353 | struct intel_crtc *intel_crtc; | |
10354 | struct drm_connector *connector; | |
10355 | ||
10356 | list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list, | |
10357 | base.head) { | |
10358 | if (!intel_encoder->base.crtc) | |
10359 | continue; | |
10360 | ||
10361 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); | |
10362 | ||
10363 | if (prepare_pipes & (1 << intel_crtc->pipe)) | |
10364 | intel_encoder->connectors_active = false; | |
10365 | } | |
10366 | ||
10367 | intel_modeset_commit_output_state(dev); | |
10368 | ||
7668851f | 10369 | /* Double check state. */ |
d3fcc808 | 10370 | for_each_intel_crtc(dev, intel_crtc) { |
7668851f | 10371 | WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base)); |
7bd0a8e7 VS |
10372 | WARN_ON(intel_crtc->new_config && |
10373 | intel_crtc->new_config != &intel_crtc->config); | |
10374 | WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config); | |
ea9d758d DV |
10375 | } |
10376 | ||
10377 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
10378 | if (!connector->encoder || !connector->encoder->crtc) | |
10379 | continue; | |
10380 | ||
10381 | intel_crtc = to_intel_crtc(connector->encoder->crtc); | |
10382 | ||
10383 | if (prepare_pipes & (1 << intel_crtc->pipe)) { | |
68d34720 DV |
10384 | struct drm_property *dpms_property = |
10385 | dev->mode_config.dpms_property; | |
10386 | ||
ea9d758d | 10387 | connector->dpms = DRM_MODE_DPMS_ON; |
662595df | 10388 | drm_object_property_set_value(&connector->base, |
68d34720 DV |
10389 | dpms_property, |
10390 | DRM_MODE_DPMS_ON); | |
ea9d758d DV |
10391 | |
10392 | intel_encoder = to_intel_encoder(connector->encoder); | |
10393 | intel_encoder->connectors_active = true; | |
10394 | } | |
10395 | } | |
10396 | ||
10397 | } | |
10398 | ||
3bd26263 | 10399 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 10400 | { |
3bd26263 | 10401 | int diff; |
f1f644dc JB |
10402 | |
10403 | if (clock1 == clock2) | |
10404 | return true; | |
10405 | ||
10406 | if (!clock1 || !clock2) | |
10407 | return false; | |
10408 | ||
10409 | diff = abs(clock1 - clock2); | |
10410 | ||
10411 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
10412 | return true; | |
10413 | ||
10414 | return false; | |
10415 | } | |
10416 | ||
25c5b266 DV |
10417 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
10418 | list_for_each_entry((intel_crtc), \ | |
10419 | &(dev)->mode_config.crtc_list, \ | |
10420 | base.head) \ | |
0973f18f | 10421 | if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 10422 | |
0e8ffe1b | 10423 | static bool |
2fa2fe9a DV |
10424 | intel_pipe_config_compare(struct drm_device *dev, |
10425 | struct intel_crtc_config *current_config, | |
0e8ffe1b DV |
10426 | struct intel_crtc_config *pipe_config) |
10427 | { | |
66e985c0 DV |
10428 | #define PIPE_CONF_CHECK_X(name) \ |
10429 | if (current_config->name != pipe_config->name) { \ | |
10430 | DRM_ERROR("mismatch in " #name " " \ | |
10431 | "(expected 0x%08x, found 0x%08x)\n", \ | |
10432 | current_config->name, \ | |
10433 | pipe_config->name); \ | |
10434 | return false; \ | |
10435 | } | |
10436 | ||
08a24034 DV |
10437 | #define PIPE_CONF_CHECK_I(name) \ |
10438 | if (current_config->name != pipe_config->name) { \ | |
10439 | DRM_ERROR("mismatch in " #name " " \ | |
10440 | "(expected %i, found %i)\n", \ | |
10441 | current_config->name, \ | |
10442 | pipe_config->name); \ | |
10443 | return false; \ | |
88adfff1 DV |
10444 | } |
10445 | ||
b95af8be VK |
10446 | /* This is required for BDW+ where there is only one set of registers for |
10447 | * switching between high and low RR. | |
10448 | * This macro can be used whenever a comparison has to be made between one | |
10449 | * hw state and multiple sw state variables. | |
10450 | */ | |
10451 | #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \ | |
10452 | if ((current_config->name != pipe_config->name) && \ | |
10453 | (current_config->alt_name != pipe_config->name)) { \ | |
10454 | DRM_ERROR("mismatch in " #name " " \ | |
10455 | "(expected %i or %i, found %i)\n", \ | |
10456 | current_config->name, \ | |
10457 | current_config->alt_name, \ | |
10458 | pipe_config->name); \ | |
10459 | return false; \ | |
10460 | } | |
10461 | ||
1bd1bd80 DV |
10462 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
10463 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
6f02488e | 10464 | DRM_ERROR("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
10465 | "(expected %i, found %i)\n", \ |
10466 | current_config->name & (mask), \ | |
10467 | pipe_config->name & (mask)); \ | |
10468 | return false; \ | |
10469 | } | |
10470 | ||
5e550656 VS |
10471 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
10472 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
10473 | DRM_ERROR("mismatch in " #name " " \ | |
10474 | "(expected %i, found %i)\n", \ | |
10475 | current_config->name, \ | |
10476 | pipe_config->name); \ | |
10477 | return false; \ | |
10478 | } | |
10479 | ||
bb760063 DV |
10480 | #define PIPE_CONF_QUIRK(quirk) \ |
10481 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
10482 | ||
eccb140b DV |
10483 | PIPE_CONF_CHECK_I(cpu_transcoder); |
10484 | ||
08a24034 DV |
10485 | PIPE_CONF_CHECK_I(has_pch_encoder); |
10486 | PIPE_CONF_CHECK_I(fdi_lanes); | |
72419203 DV |
10487 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); |
10488 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); | |
10489 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); | |
10490 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); | |
10491 | PIPE_CONF_CHECK_I(fdi_m_n.tu); | |
08a24034 | 10492 | |
eb14cb74 | 10493 | PIPE_CONF_CHECK_I(has_dp_encoder); |
b95af8be VK |
10494 | |
10495 | if (INTEL_INFO(dev)->gen < 8) { | |
10496 | PIPE_CONF_CHECK_I(dp_m_n.gmch_m); | |
10497 | PIPE_CONF_CHECK_I(dp_m_n.gmch_n); | |
10498 | PIPE_CONF_CHECK_I(dp_m_n.link_m); | |
10499 | PIPE_CONF_CHECK_I(dp_m_n.link_n); | |
10500 | PIPE_CONF_CHECK_I(dp_m_n.tu); | |
10501 | ||
10502 | if (current_config->has_drrs) { | |
10503 | PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m); | |
10504 | PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n); | |
10505 | PIPE_CONF_CHECK_I(dp_m2_n2.link_m); | |
10506 | PIPE_CONF_CHECK_I(dp_m2_n2.link_n); | |
10507 | PIPE_CONF_CHECK_I(dp_m2_n2.tu); | |
10508 | } | |
10509 | } else { | |
10510 | PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m); | |
10511 | PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n); | |
10512 | PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m); | |
10513 | PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n); | |
10514 | PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu); | |
10515 | } | |
eb14cb74 | 10516 | |
1bd1bd80 DV |
10517 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay); |
10518 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal); | |
10519 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start); | |
10520 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end); | |
10521 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start); | |
10522 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end); | |
10523 | ||
10524 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay); | |
10525 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal); | |
10526 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start); | |
10527 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end); | |
10528 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start); | |
10529 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end); | |
10530 | ||
c93f54cf | 10531 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 10532 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 DV |
10533 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
10534 | IS_VALLEYVIEW(dev)) | |
10535 | PIPE_CONF_CHECK_I(limited_color_range); | |
6c49f241 | 10536 | |
9ed109a7 DV |
10537 | PIPE_CONF_CHECK_I(has_audio); |
10538 | ||
1bd1bd80 DV |
10539 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
10540 | DRM_MODE_FLAG_INTERLACE); | |
10541 | ||
bb760063 DV |
10542 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
10543 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
10544 | DRM_MODE_FLAG_PHSYNC); | |
10545 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
10546 | DRM_MODE_FLAG_NHSYNC); | |
10547 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
10548 | DRM_MODE_FLAG_PVSYNC); | |
10549 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
10550 | DRM_MODE_FLAG_NVSYNC); | |
10551 | } | |
045ac3b5 | 10552 | |
37327abd VS |
10553 | PIPE_CONF_CHECK_I(pipe_src_w); |
10554 | PIPE_CONF_CHECK_I(pipe_src_h); | |
1bd1bd80 | 10555 | |
9953599b DV |
10556 | /* |
10557 | * FIXME: BIOS likes to set up a cloned config with lvds+external | |
10558 | * screen. Since we don't yet re-compute the pipe config when moving | |
10559 | * just the lvds port away to another pipe the sw tracking won't match. | |
10560 | * | |
10561 | * Proper atomic modesets with recomputed global state will fix this. | |
10562 | * Until then just don't check gmch state for inherited modes. | |
10563 | */ | |
10564 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) { | |
10565 | PIPE_CONF_CHECK_I(gmch_pfit.control); | |
10566 | /* pfit ratios are autocomputed by the hw on gen4+ */ | |
10567 | if (INTEL_INFO(dev)->gen < 4) | |
10568 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
10569 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); | |
10570 | } | |
10571 | ||
fd4daa9c CW |
10572 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
10573 | if (current_config->pch_pfit.enabled) { | |
10574 | PIPE_CONF_CHECK_I(pch_pfit.pos); | |
10575 | PIPE_CONF_CHECK_I(pch_pfit.size); | |
10576 | } | |
2fa2fe9a | 10577 | |
e59150dc JB |
10578 | /* BDW+ don't expose a synchronous way to read the state */ |
10579 | if (IS_HASWELL(dev)) | |
10580 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 10581 | |
282740f7 VS |
10582 | PIPE_CONF_CHECK_I(double_wide); |
10583 | ||
26804afd DV |
10584 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
10585 | ||
c0d43d62 | 10586 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 10587 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 10588 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
10589 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
10590 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 10591 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
c0d43d62 | 10592 | |
42571aef VS |
10593 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
10594 | PIPE_CONF_CHECK_I(pipe_bpp); | |
10595 | ||
a9a7e98a JB |
10596 | PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock); |
10597 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); | |
5e550656 | 10598 | |
66e985c0 | 10599 | #undef PIPE_CONF_CHECK_X |
08a24034 | 10600 | #undef PIPE_CONF_CHECK_I |
b95af8be | 10601 | #undef PIPE_CONF_CHECK_I_ALT |
1bd1bd80 | 10602 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 10603 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 10604 | #undef PIPE_CONF_QUIRK |
88adfff1 | 10605 | |
0e8ffe1b DV |
10606 | return true; |
10607 | } | |
10608 | ||
91d1b4bd DV |
10609 | static void |
10610 | check_connector_state(struct drm_device *dev) | |
8af6cf88 | 10611 | { |
8af6cf88 DV |
10612 | struct intel_connector *connector; |
10613 | ||
10614 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
10615 | base.head) { | |
10616 | /* This also checks the encoder/connector hw state with the | |
10617 | * ->get_hw_state callbacks. */ | |
10618 | intel_connector_check_state(connector); | |
10619 | ||
10620 | WARN(&connector->new_encoder->base != connector->base.encoder, | |
10621 | "connector's staged encoder doesn't match current encoder\n"); | |
10622 | } | |
91d1b4bd DV |
10623 | } |
10624 | ||
10625 | static void | |
10626 | check_encoder_state(struct drm_device *dev) | |
10627 | { | |
10628 | struct intel_encoder *encoder; | |
10629 | struct intel_connector *connector; | |
8af6cf88 DV |
10630 | |
10631 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
10632 | base.head) { | |
10633 | bool enabled = false; | |
10634 | bool active = false; | |
10635 | enum pipe pipe, tracked_pipe; | |
10636 | ||
10637 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
10638 | encoder->base.base.id, | |
8e329a03 | 10639 | encoder->base.name); |
8af6cf88 DV |
10640 | |
10641 | WARN(&encoder->new_crtc->base != encoder->base.crtc, | |
10642 | "encoder's stage crtc doesn't match current crtc\n"); | |
10643 | WARN(encoder->connectors_active && !encoder->base.crtc, | |
10644 | "encoder's active_connectors set, but no crtc\n"); | |
10645 | ||
10646 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
10647 | base.head) { | |
10648 | if (connector->base.encoder != &encoder->base) | |
10649 | continue; | |
10650 | enabled = true; | |
10651 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) | |
10652 | active = true; | |
10653 | } | |
0e32b39c DA |
10654 | /* |
10655 | * for MST connectors if we unplug the connector is gone | |
10656 | * away but the encoder is still connected to a crtc | |
10657 | * until a modeset happens in response to the hotplug. | |
10658 | */ | |
10659 | if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST) | |
10660 | continue; | |
10661 | ||
8af6cf88 DV |
10662 | WARN(!!encoder->base.crtc != enabled, |
10663 | "encoder's enabled state mismatch " | |
10664 | "(expected %i, found %i)\n", | |
10665 | !!encoder->base.crtc, enabled); | |
10666 | WARN(active && !encoder->base.crtc, | |
10667 | "active encoder with no crtc\n"); | |
10668 | ||
10669 | WARN(encoder->connectors_active != active, | |
10670 | "encoder's computed active state doesn't match tracked active state " | |
10671 | "(expected %i, found %i)\n", active, encoder->connectors_active); | |
10672 | ||
10673 | active = encoder->get_hw_state(encoder, &pipe); | |
10674 | WARN(active != encoder->connectors_active, | |
10675 | "encoder's hw state doesn't match sw tracking " | |
10676 | "(expected %i, found %i)\n", | |
10677 | encoder->connectors_active, active); | |
10678 | ||
10679 | if (!encoder->base.crtc) | |
10680 | continue; | |
10681 | ||
10682 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; | |
10683 | WARN(active && pipe != tracked_pipe, | |
10684 | "active encoder's pipe doesn't match" | |
10685 | "(expected %i, found %i)\n", | |
10686 | tracked_pipe, pipe); | |
10687 | ||
10688 | } | |
91d1b4bd DV |
10689 | } |
10690 | ||
10691 | static void | |
10692 | check_crtc_state(struct drm_device *dev) | |
10693 | { | |
fbee40df | 10694 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
10695 | struct intel_crtc *crtc; |
10696 | struct intel_encoder *encoder; | |
10697 | struct intel_crtc_config pipe_config; | |
8af6cf88 | 10698 | |
d3fcc808 | 10699 | for_each_intel_crtc(dev, crtc) { |
8af6cf88 DV |
10700 | bool enabled = false; |
10701 | bool active = false; | |
10702 | ||
045ac3b5 JB |
10703 | memset(&pipe_config, 0, sizeof(pipe_config)); |
10704 | ||
8af6cf88 DV |
10705 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
10706 | crtc->base.base.id); | |
10707 | ||
10708 | WARN(crtc->active && !crtc->base.enabled, | |
10709 | "active crtc, but not enabled in sw tracking\n"); | |
10710 | ||
10711 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
10712 | base.head) { | |
10713 | if (encoder->base.crtc != &crtc->base) | |
10714 | continue; | |
10715 | enabled = true; | |
10716 | if (encoder->connectors_active) | |
10717 | active = true; | |
10718 | } | |
6c49f241 | 10719 | |
8af6cf88 DV |
10720 | WARN(active != crtc->active, |
10721 | "crtc's computed active state doesn't match tracked active state " | |
10722 | "(expected %i, found %i)\n", active, crtc->active); | |
10723 | WARN(enabled != crtc->base.enabled, | |
10724 | "crtc's computed enabled state doesn't match tracked enabled state " | |
10725 | "(expected %i, found %i)\n", enabled, crtc->base.enabled); | |
10726 | ||
0e8ffe1b DV |
10727 | active = dev_priv->display.get_pipe_config(crtc, |
10728 | &pipe_config); | |
d62cf62a DV |
10729 | |
10730 | /* hw state is inconsistent with the pipe A quirk */ | |
10731 | if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
10732 | active = crtc->active; | |
10733 | ||
6c49f241 DV |
10734 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
10735 | base.head) { | |
3eaba51c | 10736 | enum pipe pipe; |
6c49f241 DV |
10737 | if (encoder->base.crtc != &crtc->base) |
10738 | continue; | |
1d37b689 | 10739 | if (encoder->get_hw_state(encoder, &pipe)) |
6c49f241 DV |
10740 | encoder->get_config(encoder, &pipe_config); |
10741 | } | |
10742 | ||
0e8ffe1b DV |
10743 | WARN(crtc->active != active, |
10744 | "crtc active state doesn't match with hw state " | |
10745 | "(expected %i, found %i)\n", crtc->active, active); | |
10746 | ||
c0b03411 DV |
10747 | if (active && |
10748 | !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) { | |
10749 | WARN(1, "pipe state doesn't match!\n"); | |
10750 | intel_dump_pipe_config(crtc, &pipe_config, | |
10751 | "[hw state]"); | |
10752 | intel_dump_pipe_config(crtc, &crtc->config, | |
10753 | "[sw state]"); | |
10754 | } | |
8af6cf88 DV |
10755 | } |
10756 | } | |
10757 | ||
91d1b4bd DV |
10758 | static void |
10759 | check_shared_dpll_state(struct drm_device *dev) | |
10760 | { | |
fbee40df | 10761 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
10762 | struct intel_crtc *crtc; |
10763 | struct intel_dpll_hw_state dpll_hw_state; | |
10764 | int i; | |
5358901f DV |
10765 | |
10766 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
10767 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
10768 | int enabled_crtcs = 0, active_crtcs = 0; | |
10769 | bool active; | |
10770 | ||
10771 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
10772 | ||
10773 | DRM_DEBUG_KMS("%s\n", pll->name); | |
10774 | ||
10775 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
10776 | ||
10777 | WARN(pll->active > pll->refcount, | |
10778 | "more active pll users than references: %i vs %i\n", | |
10779 | pll->active, pll->refcount); | |
10780 | WARN(pll->active && !pll->on, | |
10781 | "pll in active use but not on in sw tracking\n"); | |
35c95375 DV |
10782 | WARN(pll->on && !pll->active, |
10783 | "pll in on but not on in use in sw tracking\n"); | |
5358901f DV |
10784 | WARN(pll->on != active, |
10785 | "pll on state mismatch (expected %i, found %i)\n", | |
10786 | pll->on, active); | |
10787 | ||
d3fcc808 | 10788 | for_each_intel_crtc(dev, crtc) { |
5358901f DV |
10789 | if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll) |
10790 | enabled_crtcs++; | |
10791 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
10792 | active_crtcs++; | |
10793 | } | |
10794 | WARN(pll->active != active_crtcs, | |
10795 | "pll active crtcs mismatch (expected %i, found %i)\n", | |
10796 | pll->active, active_crtcs); | |
10797 | WARN(pll->refcount != enabled_crtcs, | |
10798 | "pll enabled crtcs mismatch (expected %i, found %i)\n", | |
10799 | pll->refcount, enabled_crtcs); | |
66e985c0 DV |
10800 | |
10801 | WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state, | |
10802 | sizeof(dpll_hw_state)), | |
10803 | "pll hw state mismatch\n"); | |
5358901f | 10804 | } |
8af6cf88 DV |
10805 | } |
10806 | ||
91d1b4bd DV |
10807 | void |
10808 | intel_modeset_check_state(struct drm_device *dev) | |
10809 | { | |
10810 | check_connector_state(dev); | |
10811 | check_encoder_state(dev); | |
10812 | check_crtc_state(dev); | |
10813 | check_shared_dpll_state(dev); | |
10814 | } | |
10815 | ||
18442d08 VS |
10816 | void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, |
10817 | int dotclock) | |
10818 | { | |
10819 | /* | |
10820 | * FDI already provided one idea for the dotclock. | |
10821 | * Yell if the encoder disagrees. | |
10822 | */ | |
241bfc38 | 10823 | WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock), |
18442d08 | 10824 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
241bfc38 | 10825 | pipe_config->adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
10826 | } |
10827 | ||
80715b2f VS |
10828 | static void update_scanline_offset(struct intel_crtc *crtc) |
10829 | { | |
10830 | struct drm_device *dev = crtc->base.dev; | |
10831 | ||
10832 | /* | |
10833 | * The scanline counter increments at the leading edge of hsync. | |
10834 | * | |
10835 | * On most platforms it starts counting from vtotal-1 on the | |
10836 | * first active line. That means the scanline counter value is | |
10837 | * always one less than what we would expect. Ie. just after | |
10838 | * start of vblank, which also occurs at start of hsync (on the | |
10839 | * last active line), the scanline counter will read vblank_start-1. | |
10840 | * | |
10841 | * On gen2 the scanline counter starts counting from 1 instead | |
10842 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
10843 | * to keep the value positive), instead of adding one. | |
10844 | * | |
10845 | * On HSW+ the behaviour of the scanline counter depends on the output | |
10846 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
10847 | * there's an extra 1 line difference. So we need to add two instead of | |
10848 | * one to the value. | |
10849 | */ | |
10850 | if (IS_GEN2(dev)) { | |
10851 | const struct drm_display_mode *mode = &crtc->config.adjusted_mode; | |
10852 | int vtotal; | |
10853 | ||
10854 | vtotal = mode->crtc_vtotal; | |
10855 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
10856 | vtotal /= 2; | |
10857 | ||
10858 | crtc->scanline_offset = vtotal - 1; | |
10859 | } else if (HAS_DDI(dev) && | |
10860 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) { | |
10861 | crtc->scanline_offset = 2; | |
10862 | } else | |
10863 | crtc->scanline_offset = 1; | |
10864 | } | |
10865 | ||
f30da187 DV |
10866 | static int __intel_set_mode(struct drm_crtc *crtc, |
10867 | struct drm_display_mode *mode, | |
10868 | int x, int y, struct drm_framebuffer *fb) | |
a6778b3c DV |
10869 | { |
10870 | struct drm_device *dev = crtc->dev; | |
fbee40df | 10871 | struct drm_i915_private *dev_priv = dev->dev_private; |
4b4b9238 | 10872 | struct drm_display_mode *saved_mode; |
b8cecdf5 | 10873 | struct intel_crtc_config *pipe_config = NULL; |
25c5b266 DV |
10874 | struct intel_crtc *intel_crtc; |
10875 | unsigned disable_pipes, prepare_pipes, modeset_pipes; | |
c0c36b94 | 10876 | int ret = 0; |
a6778b3c | 10877 | |
4b4b9238 | 10878 | saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL); |
c0c36b94 CW |
10879 | if (!saved_mode) |
10880 | return -ENOMEM; | |
a6778b3c | 10881 | |
e2e1ed41 | 10882 | intel_modeset_affected_pipes(crtc, &modeset_pipes, |
25c5b266 DV |
10883 | &prepare_pipes, &disable_pipes); |
10884 | ||
3ac18232 | 10885 | *saved_mode = crtc->mode; |
a6778b3c | 10886 | |
25c5b266 DV |
10887 | /* Hack: Because we don't (yet) support global modeset on multiple |
10888 | * crtcs, we don't keep track of the new mode for more than one crtc. | |
10889 | * Hence simply check whether any bit is set in modeset_pipes in all the | |
10890 | * pieces of code that are not yet converted to deal with mutliple crtcs | |
10891 | * changing their mode at the same time. */ | |
25c5b266 | 10892 | if (modeset_pipes) { |
4e53c2e0 | 10893 | pipe_config = intel_modeset_pipe_config(crtc, fb, mode); |
b8cecdf5 DV |
10894 | if (IS_ERR(pipe_config)) { |
10895 | ret = PTR_ERR(pipe_config); | |
10896 | pipe_config = NULL; | |
10897 | ||
3ac18232 | 10898 | goto out; |
25c5b266 | 10899 | } |
c0b03411 DV |
10900 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
10901 | "[modeset]"); | |
50741abc | 10902 | to_intel_crtc(crtc)->new_config = pipe_config; |
25c5b266 | 10903 | } |
a6778b3c | 10904 | |
30a970c6 JB |
10905 | /* |
10906 | * See if the config requires any additional preparation, e.g. | |
10907 | * to adjust global state with pipes off. We need to do this | |
10908 | * here so we can get the modeset_pipe updated config for the new | |
10909 | * mode set on this crtc. For other crtcs we need to use the | |
10910 | * adjusted_mode bits in the crtc directly. | |
10911 | */ | |
c164f833 | 10912 | if (IS_VALLEYVIEW(dev)) { |
2f2d7aa1 | 10913 | valleyview_modeset_global_pipes(dev, &prepare_pipes); |
30a970c6 | 10914 | |
c164f833 VS |
10915 | /* may have added more to prepare_pipes than we should */ |
10916 | prepare_pipes &= ~disable_pipes; | |
10917 | } | |
10918 | ||
460da916 DV |
10919 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
10920 | intel_crtc_disable(&intel_crtc->base); | |
10921 | ||
ea9d758d DV |
10922 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
10923 | if (intel_crtc->base.enabled) | |
10924 | dev_priv->display.crtc_disable(&intel_crtc->base); | |
10925 | } | |
a6778b3c | 10926 | |
6c4c86f5 DV |
10927 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
10928 | * to set it here already despite that we pass it down the callchain. | |
f6e5b160 | 10929 | */ |
b8cecdf5 | 10930 | if (modeset_pipes) { |
25c5b266 | 10931 | crtc->mode = *mode; |
b8cecdf5 DV |
10932 | /* mode_set/enable/disable functions rely on a correct pipe |
10933 | * config. */ | |
10934 | to_intel_crtc(crtc)->config = *pipe_config; | |
50741abc | 10935 | to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config; |
c326c0a9 VS |
10936 | |
10937 | /* | |
10938 | * Calculate and store various constants which | |
10939 | * are later needed by vblank and swap-completion | |
10940 | * timestamping. They are derived from true hwmode. | |
10941 | */ | |
10942 | drm_calc_timestamping_constants(crtc, | |
10943 | &pipe_config->adjusted_mode); | |
b8cecdf5 | 10944 | } |
7758a113 | 10945 | |
ea9d758d DV |
10946 | /* Only after disabling all output pipelines that will be changed can we |
10947 | * update the the output configuration. */ | |
10948 | intel_modeset_update_state(dev, prepare_pipes); | |
f6e5b160 | 10949 | |
47fab737 DV |
10950 | if (dev_priv->display.modeset_global_resources) |
10951 | dev_priv->display.modeset_global_resources(dev); | |
10952 | ||
a6778b3c DV |
10953 | /* Set up the DPLL and any encoders state that needs to adjust or depend |
10954 | * on the DPLL. | |
f6e5b160 | 10955 | */ |
25c5b266 | 10956 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
2ff8fde1 MR |
10957 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
10958 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb); | |
10959 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
4c10794f DV |
10960 | |
10961 | mutex_lock(&dev->struct_mutex); | |
10962 | ret = intel_pin_and_fence_fb_obj(dev, | |
a071fa00 | 10963 | obj, |
4c10794f DV |
10964 | NULL); |
10965 | if (ret != 0) { | |
10966 | DRM_ERROR("pin & fence failed\n"); | |
10967 | mutex_unlock(&dev->struct_mutex); | |
10968 | goto done; | |
10969 | } | |
2ff8fde1 | 10970 | if (old_fb) |
a071fa00 | 10971 | intel_unpin_fb_obj(old_obj); |
a071fa00 DV |
10972 | i915_gem_track_fb(old_obj, obj, |
10973 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe)); | |
4c10794f DV |
10974 | mutex_unlock(&dev->struct_mutex); |
10975 | ||
10976 | crtc->primary->fb = fb; | |
10977 | crtc->x = x; | |
10978 | crtc->y = y; | |
10979 | ||
4271b753 DV |
10980 | ret = dev_priv->display.crtc_mode_set(&intel_crtc->base, |
10981 | x, y, fb); | |
c0c36b94 CW |
10982 | if (ret) |
10983 | goto done; | |
a6778b3c DV |
10984 | } |
10985 | ||
10986 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ | |
80715b2f VS |
10987 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
10988 | update_scanline_offset(intel_crtc); | |
10989 | ||
25c5b266 | 10990 | dev_priv->display.crtc_enable(&intel_crtc->base); |
80715b2f | 10991 | } |
a6778b3c | 10992 | |
a6778b3c DV |
10993 | /* FIXME: add subpixel order */ |
10994 | done: | |
4b4b9238 | 10995 | if (ret && crtc->enabled) |
3ac18232 | 10996 | crtc->mode = *saved_mode; |
a6778b3c | 10997 | |
3ac18232 | 10998 | out: |
b8cecdf5 | 10999 | kfree(pipe_config); |
3ac18232 | 11000 | kfree(saved_mode); |
a6778b3c | 11001 | return ret; |
f6e5b160 CW |
11002 | } |
11003 | ||
e7457a9a DL |
11004 | static int intel_set_mode(struct drm_crtc *crtc, |
11005 | struct drm_display_mode *mode, | |
11006 | int x, int y, struct drm_framebuffer *fb) | |
f30da187 DV |
11007 | { |
11008 | int ret; | |
11009 | ||
11010 | ret = __intel_set_mode(crtc, mode, x, y, fb); | |
11011 | ||
11012 | if (ret == 0) | |
11013 | intel_modeset_check_state(crtc->dev); | |
11014 | ||
11015 | return ret; | |
11016 | } | |
11017 | ||
c0c36b94 CW |
11018 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
11019 | { | |
f4510a27 | 11020 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb); |
c0c36b94 CW |
11021 | } |
11022 | ||
25c5b266 DV |
11023 | #undef for_each_intel_crtc_masked |
11024 | ||
d9e55608 DV |
11025 | static void intel_set_config_free(struct intel_set_config *config) |
11026 | { | |
11027 | if (!config) | |
11028 | return; | |
11029 | ||
1aa4b628 DV |
11030 | kfree(config->save_connector_encoders); |
11031 | kfree(config->save_encoder_crtcs); | |
7668851f | 11032 | kfree(config->save_crtc_enabled); |
d9e55608 DV |
11033 | kfree(config); |
11034 | } | |
11035 | ||
85f9eb71 DV |
11036 | static int intel_set_config_save_state(struct drm_device *dev, |
11037 | struct intel_set_config *config) | |
11038 | { | |
7668851f | 11039 | struct drm_crtc *crtc; |
85f9eb71 DV |
11040 | struct drm_encoder *encoder; |
11041 | struct drm_connector *connector; | |
11042 | int count; | |
11043 | ||
7668851f VS |
11044 | config->save_crtc_enabled = |
11045 | kcalloc(dev->mode_config.num_crtc, | |
11046 | sizeof(bool), GFP_KERNEL); | |
11047 | if (!config->save_crtc_enabled) | |
11048 | return -ENOMEM; | |
11049 | ||
1aa4b628 DV |
11050 | config->save_encoder_crtcs = |
11051 | kcalloc(dev->mode_config.num_encoder, | |
11052 | sizeof(struct drm_crtc *), GFP_KERNEL); | |
11053 | if (!config->save_encoder_crtcs) | |
85f9eb71 DV |
11054 | return -ENOMEM; |
11055 | ||
1aa4b628 DV |
11056 | config->save_connector_encoders = |
11057 | kcalloc(dev->mode_config.num_connector, | |
11058 | sizeof(struct drm_encoder *), GFP_KERNEL); | |
11059 | if (!config->save_connector_encoders) | |
85f9eb71 DV |
11060 | return -ENOMEM; |
11061 | ||
11062 | /* Copy data. Note that driver private data is not affected. | |
11063 | * Should anything bad happen only the expected state is | |
11064 | * restored, not the drivers personal bookkeeping. | |
11065 | */ | |
7668851f | 11066 | count = 0; |
70e1e0ec | 11067 | for_each_crtc(dev, crtc) { |
7668851f VS |
11068 | config->save_crtc_enabled[count++] = crtc->enabled; |
11069 | } | |
11070 | ||
85f9eb71 DV |
11071 | count = 0; |
11072 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
1aa4b628 | 11073 | config->save_encoder_crtcs[count++] = encoder->crtc; |
85f9eb71 DV |
11074 | } |
11075 | ||
11076 | count = 0; | |
11077 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1aa4b628 | 11078 | config->save_connector_encoders[count++] = connector->encoder; |
85f9eb71 DV |
11079 | } |
11080 | ||
11081 | return 0; | |
11082 | } | |
11083 | ||
11084 | static void intel_set_config_restore_state(struct drm_device *dev, | |
11085 | struct intel_set_config *config) | |
11086 | { | |
7668851f | 11087 | struct intel_crtc *crtc; |
9a935856 DV |
11088 | struct intel_encoder *encoder; |
11089 | struct intel_connector *connector; | |
85f9eb71 DV |
11090 | int count; |
11091 | ||
7668851f | 11092 | count = 0; |
d3fcc808 | 11093 | for_each_intel_crtc(dev, crtc) { |
7668851f | 11094 | crtc->new_enabled = config->save_crtc_enabled[count++]; |
7bd0a8e7 VS |
11095 | |
11096 | if (crtc->new_enabled) | |
11097 | crtc->new_config = &crtc->config; | |
11098 | else | |
11099 | crtc->new_config = NULL; | |
7668851f VS |
11100 | } |
11101 | ||
85f9eb71 | 11102 | count = 0; |
9a935856 DV |
11103 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
11104 | encoder->new_crtc = | |
11105 | to_intel_crtc(config->save_encoder_crtcs[count++]); | |
85f9eb71 DV |
11106 | } |
11107 | ||
11108 | count = 0; | |
9a935856 DV |
11109 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { |
11110 | connector->new_encoder = | |
11111 | to_intel_encoder(config->save_connector_encoders[count++]); | |
85f9eb71 DV |
11112 | } |
11113 | } | |
11114 | ||
e3de42b6 | 11115 | static bool |
2e57f47d | 11116 | is_crtc_connector_off(struct drm_mode_set *set) |
e3de42b6 ID |
11117 | { |
11118 | int i; | |
11119 | ||
2e57f47d CW |
11120 | if (set->num_connectors == 0) |
11121 | return false; | |
11122 | ||
11123 | if (WARN_ON(set->connectors == NULL)) | |
11124 | return false; | |
11125 | ||
11126 | for (i = 0; i < set->num_connectors; i++) | |
11127 | if (set->connectors[i]->encoder && | |
11128 | set->connectors[i]->encoder->crtc == set->crtc && | |
11129 | set->connectors[i]->dpms != DRM_MODE_DPMS_ON) | |
e3de42b6 ID |
11130 | return true; |
11131 | ||
11132 | return false; | |
11133 | } | |
11134 | ||
5e2b584e DV |
11135 | static void |
11136 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, | |
11137 | struct intel_set_config *config) | |
11138 | { | |
11139 | ||
11140 | /* We should be able to check here if the fb has the same properties | |
11141 | * and then just flip_or_move it */ | |
2e57f47d CW |
11142 | if (is_crtc_connector_off(set)) { |
11143 | config->mode_changed = true; | |
f4510a27 | 11144 | } else if (set->crtc->primary->fb != set->fb) { |
3b150f08 MR |
11145 | /* |
11146 | * If we have no fb, we can only flip as long as the crtc is | |
11147 | * active, otherwise we need a full mode set. The crtc may | |
11148 | * be active if we've only disabled the primary plane, or | |
11149 | * in fastboot situations. | |
11150 | */ | |
f4510a27 | 11151 | if (set->crtc->primary->fb == NULL) { |
319d9827 JB |
11152 | struct intel_crtc *intel_crtc = |
11153 | to_intel_crtc(set->crtc); | |
11154 | ||
3b150f08 | 11155 | if (intel_crtc->active) { |
319d9827 JB |
11156 | DRM_DEBUG_KMS("crtc has no fb, will flip\n"); |
11157 | config->fb_changed = true; | |
11158 | } else { | |
11159 | DRM_DEBUG_KMS("inactive crtc, full mode set\n"); | |
11160 | config->mode_changed = true; | |
11161 | } | |
5e2b584e DV |
11162 | } else if (set->fb == NULL) { |
11163 | config->mode_changed = true; | |
72f4901e | 11164 | } else if (set->fb->pixel_format != |
f4510a27 | 11165 | set->crtc->primary->fb->pixel_format) { |
5e2b584e | 11166 | config->mode_changed = true; |
e3de42b6 | 11167 | } else { |
5e2b584e | 11168 | config->fb_changed = true; |
e3de42b6 | 11169 | } |
5e2b584e DV |
11170 | } |
11171 | ||
835c5873 | 11172 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
5e2b584e DV |
11173 | config->fb_changed = true; |
11174 | ||
11175 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { | |
11176 | DRM_DEBUG_KMS("modes are different, full mode set\n"); | |
11177 | drm_mode_debug_printmodeline(&set->crtc->mode); | |
11178 | drm_mode_debug_printmodeline(set->mode); | |
11179 | config->mode_changed = true; | |
11180 | } | |
a1d95703 CW |
11181 | |
11182 | DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n", | |
11183 | set->crtc->base.id, config->mode_changed, config->fb_changed); | |
5e2b584e DV |
11184 | } |
11185 | ||
2e431051 | 11186 | static int |
9a935856 DV |
11187 | intel_modeset_stage_output_state(struct drm_device *dev, |
11188 | struct drm_mode_set *set, | |
11189 | struct intel_set_config *config) | |
50f56119 | 11190 | { |
9a935856 DV |
11191 | struct intel_connector *connector; |
11192 | struct intel_encoder *encoder; | |
7668851f | 11193 | struct intel_crtc *crtc; |
f3f08572 | 11194 | int ro; |
50f56119 | 11195 | |
9abdda74 | 11196 | /* The upper layers ensure that we either disable a crtc or have a list |
9a935856 DV |
11197 | * of connectors. For paranoia, double-check this. */ |
11198 | WARN_ON(!set->fb && (set->num_connectors != 0)); | |
11199 | WARN_ON(set->fb && (set->num_connectors == 0)); | |
11200 | ||
9a935856 DV |
11201 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
11202 | base.head) { | |
11203 | /* Otherwise traverse passed in connector list and get encoders | |
11204 | * for them. */ | |
50f56119 | 11205 | for (ro = 0; ro < set->num_connectors; ro++) { |
9a935856 | 11206 | if (set->connectors[ro] == &connector->base) { |
0e32b39c | 11207 | connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe); |
50f56119 DV |
11208 | break; |
11209 | } | |
11210 | } | |
11211 | ||
9a935856 DV |
11212 | /* If we disable the crtc, disable all its connectors. Also, if |
11213 | * the connector is on the changing crtc but not on the new | |
11214 | * connector list, disable it. */ | |
11215 | if ((!set->fb || ro == set->num_connectors) && | |
11216 | connector->base.encoder && | |
11217 | connector->base.encoder->crtc == set->crtc) { | |
11218 | connector->new_encoder = NULL; | |
11219 | ||
11220 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", | |
11221 | connector->base.base.id, | |
c23cc417 | 11222 | connector->base.name); |
9a935856 DV |
11223 | } |
11224 | ||
11225 | ||
11226 | if (&connector->new_encoder->base != connector->base.encoder) { | |
50f56119 | 11227 | DRM_DEBUG_KMS("encoder changed, full mode switch\n"); |
5e2b584e | 11228 | config->mode_changed = true; |
50f56119 DV |
11229 | } |
11230 | } | |
9a935856 | 11231 | /* connector->new_encoder is now updated for all connectors. */ |
50f56119 | 11232 | |
9a935856 | 11233 | /* Update crtc of enabled connectors. */ |
9a935856 DV |
11234 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
11235 | base.head) { | |
7668851f VS |
11236 | struct drm_crtc *new_crtc; |
11237 | ||
9a935856 | 11238 | if (!connector->new_encoder) |
50f56119 DV |
11239 | continue; |
11240 | ||
9a935856 | 11241 | new_crtc = connector->new_encoder->base.crtc; |
50f56119 DV |
11242 | |
11243 | for (ro = 0; ro < set->num_connectors; ro++) { | |
9a935856 | 11244 | if (set->connectors[ro] == &connector->base) |
50f56119 DV |
11245 | new_crtc = set->crtc; |
11246 | } | |
11247 | ||
11248 | /* Make sure the new CRTC will work with the encoder */ | |
14509916 TR |
11249 | if (!drm_encoder_crtc_ok(&connector->new_encoder->base, |
11250 | new_crtc)) { | |
5e2b584e | 11251 | return -EINVAL; |
50f56119 | 11252 | } |
0e32b39c | 11253 | connector->new_encoder->new_crtc = to_intel_crtc(new_crtc); |
9a935856 DV |
11254 | |
11255 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", | |
11256 | connector->base.base.id, | |
c23cc417 | 11257 | connector->base.name, |
9a935856 DV |
11258 | new_crtc->base.id); |
11259 | } | |
11260 | ||
11261 | /* Check for any encoders that needs to be disabled. */ | |
11262 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
11263 | base.head) { | |
5a65f358 | 11264 | int num_connectors = 0; |
9a935856 DV |
11265 | list_for_each_entry(connector, |
11266 | &dev->mode_config.connector_list, | |
11267 | base.head) { | |
11268 | if (connector->new_encoder == encoder) { | |
11269 | WARN_ON(!connector->new_encoder->new_crtc); | |
5a65f358 | 11270 | num_connectors++; |
9a935856 DV |
11271 | } |
11272 | } | |
5a65f358 PZ |
11273 | |
11274 | if (num_connectors == 0) | |
11275 | encoder->new_crtc = NULL; | |
11276 | else if (num_connectors > 1) | |
11277 | return -EINVAL; | |
11278 | ||
9a935856 DV |
11279 | /* Only now check for crtc changes so we don't miss encoders |
11280 | * that will be disabled. */ | |
11281 | if (&encoder->new_crtc->base != encoder->base.crtc) { | |
50f56119 | 11282 | DRM_DEBUG_KMS("crtc changed, full mode switch\n"); |
5e2b584e | 11283 | config->mode_changed = true; |
50f56119 DV |
11284 | } |
11285 | } | |
9a935856 | 11286 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
0e32b39c DA |
11287 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
11288 | base.head) { | |
11289 | if (connector->new_encoder) | |
11290 | if (connector->new_encoder != connector->encoder) | |
11291 | connector->encoder = connector->new_encoder; | |
11292 | } | |
d3fcc808 | 11293 | for_each_intel_crtc(dev, crtc) { |
7668851f VS |
11294 | crtc->new_enabled = false; |
11295 | ||
11296 | list_for_each_entry(encoder, | |
11297 | &dev->mode_config.encoder_list, | |
11298 | base.head) { | |
11299 | if (encoder->new_crtc == crtc) { | |
11300 | crtc->new_enabled = true; | |
11301 | break; | |
11302 | } | |
11303 | } | |
11304 | ||
11305 | if (crtc->new_enabled != crtc->base.enabled) { | |
11306 | DRM_DEBUG_KMS("crtc %sabled, full mode switch\n", | |
11307 | crtc->new_enabled ? "en" : "dis"); | |
11308 | config->mode_changed = true; | |
11309 | } | |
7bd0a8e7 VS |
11310 | |
11311 | if (crtc->new_enabled) | |
11312 | crtc->new_config = &crtc->config; | |
11313 | else | |
11314 | crtc->new_config = NULL; | |
7668851f VS |
11315 | } |
11316 | ||
2e431051 DV |
11317 | return 0; |
11318 | } | |
11319 | ||
7d00a1f5 VS |
11320 | static void disable_crtc_nofb(struct intel_crtc *crtc) |
11321 | { | |
11322 | struct drm_device *dev = crtc->base.dev; | |
11323 | struct intel_encoder *encoder; | |
11324 | struct intel_connector *connector; | |
11325 | ||
11326 | DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n", | |
11327 | pipe_name(crtc->pipe)); | |
11328 | ||
11329 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { | |
11330 | if (connector->new_encoder && | |
11331 | connector->new_encoder->new_crtc == crtc) | |
11332 | connector->new_encoder = NULL; | |
11333 | } | |
11334 | ||
11335 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { | |
11336 | if (encoder->new_crtc == crtc) | |
11337 | encoder->new_crtc = NULL; | |
11338 | } | |
11339 | ||
11340 | crtc->new_enabled = false; | |
7bd0a8e7 | 11341 | crtc->new_config = NULL; |
7d00a1f5 VS |
11342 | } |
11343 | ||
2e431051 DV |
11344 | static int intel_crtc_set_config(struct drm_mode_set *set) |
11345 | { | |
11346 | struct drm_device *dev; | |
2e431051 DV |
11347 | struct drm_mode_set save_set; |
11348 | struct intel_set_config *config; | |
11349 | int ret; | |
2e431051 | 11350 | |
8d3e375e DV |
11351 | BUG_ON(!set); |
11352 | BUG_ON(!set->crtc); | |
11353 | BUG_ON(!set->crtc->helper_private); | |
2e431051 | 11354 | |
7e53f3a4 DV |
11355 | /* Enforce sane interface api - has been abused by the fb helper. */ |
11356 | BUG_ON(!set->mode && set->fb); | |
11357 | BUG_ON(set->fb && set->num_connectors == 0); | |
431e50f7 | 11358 | |
2e431051 DV |
11359 | if (set->fb) { |
11360 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", | |
11361 | set->crtc->base.id, set->fb->base.id, | |
11362 | (int)set->num_connectors, set->x, set->y); | |
11363 | } else { | |
11364 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); | |
2e431051 DV |
11365 | } |
11366 | ||
11367 | dev = set->crtc->dev; | |
11368 | ||
11369 | ret = -ENOMEM; | |
11370 | config = kzalloc(sizeof(*config), GFP_KERNEL); | |
11371 | if (!config) | |
11372 | goto out_config; | |
11373 | ||
11374 | ret = intel_set_config_save_state(dev, config); | |
11375 | if (ret) | |
11376 | goto out_config; | |
11377 | ||
11378 | save_set.crtc = set->crtc; | |
11379 | save_set.mode = &set->crtc->mode; | |
11380 | save_set.x = set->crtc->x; | |
11381 | save_set.y = set->crtc->y; | |
f4510a27 | 11382 | save_set.fb = set->crtc->primary->fb; |
2e431051 DV |
11383 | |
11384 | /* Compute whether we need a full modeset, only an fb base update or no | |
11385 | * change at all. In the future we might also check whether only the | |
11386 | * mode changed, e.g. for LVDS where we only change the panel fitter in | |
11387 | * such cases. */ | |
11388 | intel_set_config_compute_mode_changes(set, config); | |
11389 | ||
9a935856 | 11390 | ret = intel_modeset_stage_output_state(dev, set, config); |
2e431051 DV |
11391 | if (ret) |
11392 | goto fail; | |
11393 | ||
5e2b584e | 11394 | if (config->mode_changed) { |
c0c36b94 CW |
11395 | ret = intel_set_mode(set->crtc, set->mode, |
11396 | set->x, set->y, set->fb); | |
5e2b584e | 11397 | } else if (config->fb_changed) { |
3b150f08 MR |
11398 | struct drm_i915_private *dev_priv = dev->dev_private; |
11399 | struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc); | |
11400 | ||
4878cae2 VS |
11401 | intel_crtc_wait_for_pending_flips(set->crtc); |
11402 | ||
4f660f49 | 11403 | ret = intel_pipe_set_base(set->crtc, |
94352cf9 | 11404 | set->x, set->y, set->fb); |
3b150f08 MR |
11405 | |
11406 | /* | |
11407 | * We need to make sure the primary plane is re-enabled if it | |
11408 | * has previously been turned off. | |
11409 | */ | |
11410 | if (!intel_crtc->primary_enabled && ret == 0) { | |
11411 | WARN_ON(!intel_crtc->active); | |
11412 | intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane, | |
11413 | intel_crtc->pipe); | |
11414 | } | |
11415 | ||
7ca51a3a JB |
11416 | /* |
11417 | * In the fastboot case this may be our only check of the | |
11418 | * state after boot. It would be better to only do it on | |
11419 | * the first update, but we don't have a nice way of doing that | |
11420 | * (and really, set_config isn't used much for high freq page | |
11421 | * flipping, so increasing its cost here shouldn't be a big | |
11422 | * deal). | |
11423 | */ | |
d330a953 | 11424 | if (i915.fastboot && ret == 0) |
7ca51a3a | 11425 | intel_modeset_check_state(set->crtc->dev); |
50f56119 DV |
11426 | } |
11427 | ||
2d05eae1 | 11428 | if (ret) { |
bf67dfeb DV |
11429 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
11430 | set->crtc->base.id, ret); | |
50f56119 | 11431 | fail: |
2d05eae1 | 11432 | intel_set_config_restore_state(dev, config); |
50f56119 | 11433 | |
7d00a1f5 VS |
11434 | /* |
11435 | * HACK: if the pipe was on, but we didn't have a framebuffer, | |
11436 | * force the pipe off to avoid oopsing in the modeset code | |
11437 | * due to fb==NULL. This should only happen during boot since | |
11438 | * we don't yet reconstruct the FB from the hardware state. | |
11439 | */ | |
11440 | if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb) | |
11441 | disable_crtc_nofb(to_intel_crtc(save_set.crtc)); | |
11442 | ||
2d05eae1 CW |
11443 | /* Try to restore the config */ |
11444 | if (config->mode_changed && | |
11445 | intel_set_mode(save_set.crtc, save_set.mode, | |
11446 | save_set.x, save_set.y, save_set.fb)) | |
11447 | DRM_ERROR("failed to restore config after modeset failure\n"); | |
11448 | } | |
50f56119 | 11449 | |
d9e55608 DV |
11450 | out_config: |
11451 | intel_set_config_free(config); | |
50f56119 DV |
11452 | return ret; |
11453 | } | |
f6e5b160 CW |
11454 | |
11455 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
f6e5b160 | 11456 | .gamma_set = intel_crtc_gamma_set, |
50f56119 | 11457 | .set_config = intel_crtc_set_config, |
f6e5b160 CW |
11458 | .destroy = intel_crtc_destroy, |
11459 | .page_flip = intel_crtc_page_flip, | |
11460 | }; | |
11461 | ||
5358901f DV |
11462 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
11463 | struct intel_shared_dpll *pll, | |
11464 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 11465 | { |
5358901f | 11466 | uint32_t val; |
ee7b9f93 | 11467 | |
bd2bb1b9 PZ |
11468 | if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
11469 | return false; | |
11470 | ||
5358901f | 11471 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
11472 | hw_state->dpll = val; |
11473 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
11474 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
11475 | |
11476 | return val & DPLL_VCO_ENABLE; | |
11477 | } | |
11478 | ||
15bdd4cf DV |
11479 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
11480 | struct intel_shared_dpll *pll) | |
11481 | { | |
11482 | I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0); | |
11483 | I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1); | |
11484 | } | |
11485 | ||
e7b903d2 DV |
11486 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
11487 | struct intel_shared_dpll *pll) | |
11488 | { | |
e7b903d2 | 11489 | /* PCH refclock must be enabled first */ |
89eff4be | 11490 | ibx_assert_pch_refclk_enabled(dev_priv); |
e7b903d2 | 11491 | |
15bdd4cf DV |
11492 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); |
11493 | ||
11494 | /* Wait for the clocks to stabilize. */ | |
11495 | POSTING_READ(PCH_DPLL(pll->id)); | |
11496 | udelay(150); | |
11497 | ||
11498 | /* The pixel multiplier can only be updated once the | |
11499 | * DPLL is enabled and the clocks are stable. | |
11500 | * | |
11501 | * So write it again. | |
11502 | */ | |
11503 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); | |
11504 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
11505 | udelay(200); |
11506 | } | |
11507 | ||
11508 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
11509 | struct intel_shared_dpll *pll) | |
11510 | { | |
11511 | struct drm_device *dev = dev_priv->dev; | |
11512 | struct intel_crtc *crtc; | |
e7b903d2 DV |
11513 | |
11514 | /* Make sure no transcoder isn't still depending on us. */ | |
d3fcc808 | 11515 | for_each_intel_crtc(dev, crtc) { |
e7b903d2 DV |
11516 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
11517 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
11518 | } |
11519 | ||
15bdd4cf DV |
11520 | I915_WRITE(PCH_DPLL(pll->id), 0); |
11521 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
11522 | udelay(200); |
11523 | } | |
11524 | ||
46edb027 DV |
11525 | static char *ibx_pch_dpll_names[] = { |
11526 | "PCH DPLL A", | |
11527 | "PCH DPLL B", | |
11528 | }; | |
11529 | ||
7c74ade1 | 11530 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 11531 | { |
e7b903d2 | 11532 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
11533 | int i; |
11534 | ||
7c74ade1 | 11535 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 11536 | |
e72f9fbf | 11537 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
11538 | dev_priv->shared_dplls[i].id = i; |
11539 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 11540 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
11541 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
11542 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
11543 | dev_priv->shared_dplls[i].get_hw_state = |
11544 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
11545 | } |
11546 | } | |
11547 | ||
7c74ade1 DV |
11548 | static void intel_shared_dpll_init(struct drm_device *dev) |
11549 | { | |
e7b903d2 | 11550 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 | 11551 | |
9cd86933 DV |
11552 | if (HAS_DDI(dev)) |
11553 | intel_ddi_pll_init(dev); | |
11554 | else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
7c74ade1 DV |
11555 | ibx_pch_dpll_init(dev); |
11556 | else | |
11557 | dev_priv->num_shared_dpll = 0; | |
11558 | ||
11559 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
7c74ade1 DV |
11560 | } |
11561 | ||
465c120c MR |
11562 | static int |
11563 | intel_primary_plane_disable(struct drm_plane *plane) | |
11564 | { | |
11565 | struct drm_device *dev = plane->dev; | |
11566 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11567 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
11568 | struct intel_crtc *intel_crtc; | |
11569 | ||
11570 | if (!plane->fb) | |
11571 | return 0; | |
11572 | ||
11573 | BUG_ON(!plane->crtc); | |
11574 | ||
11575 | intel_crtc = to_intel_crtc(plane->crtc); | |
11576 | ||
11577 | /* | |
11578 | * Even though we checked plane->fb above, it's still possible that | |
11579 | * the primary plane has been implicitly disabled because the crtc | |
11580 | * coordinates given weren't visible, or because we detected | |
11581 | * that it was 100% covered by a sprite plane. Or, the CRTC may be | |
11582 | * off and we've set a fb, but haven't actually turned on the CRTC yet. | |
11583 | * In either case, we need to unpin the FB and let the fb pointer get | |
11584 | * updated, but otherwise we don't need to touch the hardware. | |
11585 | */ | |
11586 | if (!intel_crtc->primary_enabled) | |
11587 | goto disable_unpin; | |
11588 | ||
11589 | intel_crtc_wait_for_pending_flips(plane->crtc); | |
11590 | intel_disable_primary_hw_plane(dev_priv, intel_plane->plane, | |
11591 | intel_plane->pipe); | |
465c120c | 11592 | disable_unpin: |
4c34574f | 11593 | mutex_lock(&dev->struct_mutex); |
2ff8fde1 | 11594 | i915_gem_track_fb(intel_fb_obj(plane->fb), NULL, |
a071fa00 | 11595 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe)); |
2ff8fde1 | 11596 | intel_unpin_fb_obj(intel_fb_obj(plane->fb)); |
4c34574f | 11597 | mutex_unlock(&dev->struct_mutex); |
465c120c MR |
11598 | plane->fb = NULL; |
11599 | ||
11600 | return 0; | |
11601 | } | |
11602 | ||
11603 | static int | |
11604 | intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc, | |
11605 | struct drm_framebuffer *fb, int crtc_x, int crtc_y, | |
11606 | unsigned int crtc_w, unsigned int crtc_h, | |
11607 | uint32_t src_x, uint32_t src_y, | |
11608 | uint32_t src_w, uint32_t src_h) | |
11609 | { | |
11610 | struct drm_device *dev = crtc->dev; | |
11611 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11612 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11613 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
2ff8fde1 MR |
11614 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
11615 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb); | |
465c120c MR |
11616 | struct drm_rect dest = { |
11617 | /* integer pixels */ | |
11618 | .x1 = crtc_x, | |
11619 | .y1 = crtc_y, | |
11620 | .x2 = crtc_x + crtc_w, | |
11621 | .y2 = crtc_y + crtc_h, | |
11622 | }; | |
11623 | struct drm_rect src = { | |
11624 | /* 16.16 fixed point */ | |
11625 | .x1 = src_x, | |
11626 | .y1 = src_y, | |
11627 | .x2 = src_x + src_w, | |
11628 | .y2 = src_y + src_h, | |
11629 | }; | |
11630 | const struct drm_rect clip = { | |
11631 | /* integer pixels */ | |
11632 | .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0, | |
11633 | .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0, | |
11634 | }; | |
11635 | bool visible; | |
11636 | int ret; | |
11637 | ||
11638 | ret = drm_plane_helper_check_update(plane, crtc, fb, | |
11639 | &src, &dest, &clip, | |
11640 | DRM_PLANE_HELPER_NO_SCALING, | |
11641 | DRM_PLANE_HELPER_NO_SCALING, | |
11642 | false, true, &visible); | |
11643 | ||
11644 | if (ret) | |
11645 | return ret; | |
11646 | ||
11647 | /* | |
11648 | * If the CRTC isn't enabled, we're just pinning the framebuffer, | |
11649 | * updating the fb pointer, and returning without touching the | |
11650 | * hardware. This allows us to later do a drmModeSetCrtc with fb=-1 to | |
11651 | * turn on the display with all planes setup as desired. | |
11652 | */ | |
11653 | if (!crtc->enabled) { | |
4c34574f MR |
11654 | mutex_lock(&dev->struct_mutex); |
11655 | ||
465c120c MR |
11656 | /* |
11657 | * If we already called setplane while the crtc was disabled, | |
11658 | * we may have an fb pinned; unpin it. | |
11659 | */ | |
11660 | if (plane->fb) | |
a071fa00 DV |
11661 | intel_unpin_fb_obj(old_obj); |
11662 | ||
11663 | i915_gem_track_fb(old_obj, obj, | |
11664 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe)); | |
465c120c MR |
11665 | |
11666 | /* Pin and return without programming hardware */ | |
4c34574f MR |
11667 | ret = intel_pin_and_fence_fb_obj(dev, obj, NULL); |
11668 | mutex_unlock(&dev->struct_mutex); | |
11669 | ||
11670 | return ret; | |
465c120c MR |
11671 | } |
11672 | ||
11673 | intel_crtc_wait_for_pending_flips(crtc); | |
11674 | ||
11675 | /* | |
11676 | * If clipping results in a non-visible primary plane, we'll disable | |
11677 | * the primary plane. Note that this is a bit different than what | |
11678 | * happens if userspace explicitly disables the plane by passing fb=0 | |
11679 | * because plane->fb still gets set and pinned. | |
11680 | */ | |
11681 | if (!visible) { | |
4c34574f MR |
11682 | mutex_lock(&dev->struct_mutex); |
11683 | ||
465c120c MR |
11684 | /* |
11685 | * Try to pin the new fb first so that we can bail out if we | |
11686 | * fail. | |
11687 | */ | |
11688 | if (plane->fb != fb) { | |
a071fa00 | 11689 | ret = intel_pin_and_fence_fb_obj(dev, obj, NULL); |
4c34574f MR |
11690 | if (ret) { |
11691 | mutex_unlock(&dev->struct_mutex); | |
465c120c | 11692 | return ret; |
4c34574f | 11693 | } |
465c120c MR |
11694 | } |
11695 | ||
a071fa00 DV |
11696 | i915_gem_track_fb(old_obj, obj, |
11697 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe)); | |
11698 | ||
465c120c MR |
11699 | if (intel_crtc->primary_enabled) |
11700 | intel_disable_primary_hw_plane(dev_priv, | |
11701 | intel_plane->plane, | |
11702 | intel_plane->pipe); | |
11703 | ||
11704 | ||
11705 | if (plane->fb != fb) | |
11706 | if (plane->fb) | |
a071fa00 | 11707 | intel_unpin_fb_obj(old_obj); |
465c120c | 11708 | |
4c34574f MR |
11709 | mutex_unlock(&dev->struct_mutex); |
11710 | ||
465c120c MR |
11711 | return 0; |
11712 | } | |
11713 | ||
11714 | ret = intel_pipe_set_base(crtc, src.x1, src.y1, fb); | |
11715 | if (ret) | |
11716 | return ret; | |
11717 | ||
11718 | if (!intel_crtc->primary_enabled) | |
11719 | intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane, | |
11720 | intel_crtc->pipe); | |
11721 | ||
11722 | return 0; | |
11723 | } | |
11724 | ||
3d7d6510 MR |
11725 | /* Common destruction function for both primary and cursor planes */ |
11726 | static void intel_plane_destroy(struct drm_plane *plane) | |
465c120c MR |
11727 | { |
11728 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
11729 | drm_plane_cleanup(plane); | |
11730 | kfree(intel_plane); | |
11731 | } | |
11732 | ||
11733 | static const struct drm_plane_funcs intel_primary_plane_funcs = { | |
11734 | .update_plane = intel_primary_plane_setplane, | |
11735 | .disable_plane = intel_primary_plane_disable, | |
3d7d6510 | 11736 | .destroy = intel_plane_destroy, |
465c120c MR |
11737 | }; |
11738 | ||
11739 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
11740 | int pipe) | |
11741 | { | |
11742 | struct intel_plane *primary; | |
11743 | const uint32_t *intel_primary_formats; | |
11744 | int num_formats; | |
11745 | ||
11746 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
11747 | if (primary == NULL) | |
11748 | return NULL; | |
11749 | ||
11750 | primary->can_scale = false; | |
11751 | primary->max_downscale = 1; | |
11752 | primary->pipe = pipe; | |
11753 | primary->plane = pipe; | |
11754 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) | |
11755 | primary->plane = !pipe; | |
11756 | ||
11757 | if (INTEL_INFO(dev)->gen <= 3) { | |
11758 | intel_primary_formats = intel_primary_formats_gen2; | |
11759 | num_formats = ARRAY_SIZE(intel_primary_formats_gen2); | |
11760 | } else { | |
11761 | intel_primary_formats = intel_primary_formats_gen4; | |
11762 | num_formats = ARRAY_SIZE(intel_primary_formats_gen4); | |
11763 | } | |
11764 | ||
11765 | drm_universal_plane_init(dev, &primary->base, 0, | |
11766 | &intel_primary_plane_funcs, | |
11767 | intel_primary_formats, num_formats, | |
11768 | DRM_PLANE_TYPE_PRIMARY); | |
11769 | return &primary->base; | |
11770 | } | |
11771 | ||
3d7d6510 MR |
11772 | static int |
11773 | intel_cursor_plane_disable(struct drm_plane *plane) | |
11774 | { | |
11775 | if (!plane->fb) | |
11776 | return 0; | |
11777 | ||
11778 | BUG_ON(!plane->crtc); | |
11779 | ||
11780 | return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0); | |
11781 | } | |
11782 | ||
11783 | static int | |
11784 | intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, | |
11785 | struct drm_framebuffer *fb, int crtc_x, int crtc_y, | |
11786 | unsigned int crtc_w, unsigned int crtc_h, | |
11787 | uint32_t src_x, uint32_t src_y, | |
11788 | uint32_t src_w, uint32_t src_h) | |
11789 | { | |
11790 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11791 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
11792 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
11793 | struct drm_rect dest = { | |
11794 | /* integer pixels */ | |
11795 | .x1 = crtc_x, | |
11796 | .y1 = crtc_y, | |
11797 | .x2 = crtc_x + crtc_w, | |
11798 | .y2 = crtc_y + crtc_h, | |
11799 | }; | |
11800 | struct drm_rect src = { | |
11801 | /* 16.16 fixed point */ | |
11802 | .x1 = src_x, | |
11803 | .y1 = src_y, | |
11804 | .x2 = src_x + src_w, | |
11805 | .y2 = src_y + src_h, | |
11806 | }; | |
11807 | const struct drm_rect clip = { | |
11808 | /* integer pixels */ | |
11809 | .x2 = intel_crtc->config.pipe_src_w, | |
11810 | .y2 = intel_crtc->config.pipe_src_h, | |
11811 | }; | |
11812 | bool visible; | |
11813 | int ret; | |
11814 | ||
11815 | ret = drm_plane_helper_check_update(plane, crtc, fb, | |
11816 | &src, &dest, &clip, | |
11817 | DRM_PLANE_HELPER_NO_SCALING, | |
11818 | DRM_PLANE_HELPER_NO_SCALING, | |
11819 | true, true, &visible); | |
11820 | if (ret) | |
11821 | return ret; | |
11822 | ||
11823 | crtc->cursor_x = crtc_x; | |
11824 | crtc->cursor_y = crtc_y; | |
11825 | if (fb != crtc->cursor->fb) { | |
11826 | return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h); | |
11827 | } else { | |
11828 | intel_crtc_update_cursor(crtc, visible); | |
11829 | return 0; | |
11830 | } | |
11831 | } | |
11832 | static const struct drm_plane_funcs intel_cursor_plane_funcs = { | |
11833 | .update_plane = intel_cursor_plane_update, | |
11834 | .disable_plane = intel_cursor_plane_disable, | |
11835 | .destroy = intel_plane_destroy, | |
11836 | }; | |
11837 | ||
11838 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, | |
11839 | int pipe) | |
11840 | { | |
11841 | struct intel_plane *cursor; | |
11842 | ||
11843 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
11844 | if (cursor == NULL) | |
11845 | return NULL; | |
11846 | ||
11847 | cursor->can_scale = false; | |
11848 | cursor->max_downscale = 1; | |
11849 | cursor->pipe = pipe; | |
11850 | cursor->plane = pipe; | |
11851 | ||
11852 | drm_universal_plane_init(dev, &cursor->base, 0, | |
11853 | &intel_cursor_plane_funcs, | |
11854 | intel_cursor_formats, | |
11855 | ARRAY_SIZE(intel_cursor_formats), | |
11856 | DRM_PLANE_TYPE_CURSOR); | |
11857 | return &cursor->base; | |
11858 | } | |
11859 | ||
b358d0a6 | 11860 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 11861 | { |
fbee40df | 11862 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 11863 | struct intel_crtc *intel_crtc; |
3d7d6510 MR |
11864 | struct drm_plane *primary = NULL; |
11865 | struct drm_plane *cursor = NULL; | |
465c120c | 11866 | int i, ret; |
79e53945 | 11867 | |
955382f3 | 11868 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
11869 | if (intel_crtc == NULL) |
11870 | return; | |
11871 | ||
465c120c | 11872 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
11873 | if (!primary) |
11874 | goto fail; | |
11875 | ||
11876 | cursor = intel_cursor_plane_create(dev, pipe); | |
11877 | if (!cursor) | |
11878 | goto fail; | |
11879 | ||
465c120c | 11880 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
3d7d6510 MR |
11881 | cursor, &intel_crtc_funcs); |
11882 | if (ret) | |
11883 | goto fail; | |
79e53945 JB |
11884 | |
11885 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
11886 | for (i = 0; i < 256; i++) { |
11887 | intel_crtc->lut_r[i] = i; | |
11888 | intel_crtc->lut_g[i] = i; | |
11889 | intel_crtc->lut_b[i] = i; | |
11890 | } | |
11891 | ||
1f1c2e24 VS |
11892 | /* |
11893 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 11894 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 11895 | */ |
80824003 JB |
11896 | intel_crtc->pipe = pipe; |
11897 | intel_crtc->plane = pipe; | |
3a77c4c4 | 11898 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 11899 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 11900 | intel_crtc->plane = !pipe; |
80824003 JB |
11901 | } |
11902 | ||
4b0e333e CW |
11903 | intel_crtc->cursor_base = ~0; |
11904 | intel_crtc->cursor_cntl = ~0; | |
11905 | ||
22fd0fab JB |
11906 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
11907 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
11908 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
11909 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
11910 | ||
79e53945 | 11911 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 DV |
11912 | |
11913 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); | |
3d7d6510 MR |
11914 | return; |
11915 | ||
11916 | fail: | |
11917 | if (primary) | |
11918 | drm_plane_cleanup(primary); | |
11919 | if (cursor) | |
11920 | drm_plane_cleanup(cursor); | |
11921 | kfree(intel_crtc); | |
79e53945 JB |
11922 | } |
11923 | ||
752aa88a JB |
11924 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
11925 | { | |
11926 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 11927 | struct drm_device *dev = connector->base.dev; |
752aa88a | 11928 | |
51fd371b | 11929 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a JB |
11930 | |
11931 | if (!encoder) | |
11932 | return INVALID_PIPE; | |
11933 | ||
11934 | return to_intel_crtc(encoder->crtc)->pipe; | |
11935 | } | |
11936 | ||
08d7b3d1 | 11937 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 11938 | struct drm_file *file) |
08d7b3d1 | 11939 | { |
08d7b3d1 | 11940 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 11941 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 11942 | struct intel_crtc *crtc; |
08d7b3d1 | 11943 | |
1cff8f6b DV |
11944 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
11945 | return -ENODEV; | |
08d7b3d1 | 11946 | |
7707e653 | 11947 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
08d7b3d1 | 11948 | |
7707e653 | 11949 | if (!drmmode_crtc) { |
08d7b3d1 | 11950 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 11951 | return -ENOENT; |
08d7b3d1 CW |
11952 | } |
11953 | ||
7707e653 | 11954 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 11955 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 11956 | |
c05422d5 | 11957 | return 0; |
08d7b3d1 CW |
11958 | } |
11959 | ||
66a9278e | 11960 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 11961 | { |
66a9278e DV |
11962 | struct drm_device *dev = encoder->base.dev; |
11963 | struct intel_encoder *source_encoder; | |
79e53945 | 11964 | int index_mask = 0; |
79e53945 JB |
11965 | int entry = 0; |
11966 | ||
66a9278e DV |
11967 | list_for_each_entry(source_encoder, |
11968 | &dev->mode_config.encoder_list, base.head) { | |
bc079e8b | 11969 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
11970 | index_mask |= (1 << entry); |
11971 | ||
79e53945 JB |
11972 | entry++; |
11973 | } | |
4ef69c7a | 11974 | |
79e53945 JB |
11975 | return index_mask; |
11976 | } | |
11977 | ||
4d302442 CW |
11978 | static bool has_edp_a(struct drm_device *dev) |
11979 | { | |
11980 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11981 | ||
11982 | if (!IS_MOBILE(dev)) | |
11983 | return false; | |
11984 | ||
11985 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
11986 | return false; | |
11987 | ||
e3589908 | 11988 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
11989 | return false; |
11990 | ||
11991 | return true; | |
11992 | } | |
11993 | ||
ba0fbca4 DL |
11994 | const char *intel_output_name(int output) |
11995 | { | |
11996 | static const char *names[] = { | |
11997 | [INTEL_OUTPUT_UNUSED] = "Unused", | |
11998 | [INTEL_OUTPUT_ANALOG] = "Analog", | |
11999 | [INTEL_OUTPUT_DVO] = "DVO", | |
12000 | [INTEL_OUTPUT_SDVO] = "SDVO", | |
12001 | [INTEL_OUTPUT_LVDS] = "LVDS", | |
12002 | [INTEL_OUTPUT_TVOUT] = "TV", | |
12003 | [INTEL_OUTPUT_HDMI] = "HDMI", | |
12004 | [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort", | |
12005 | [INTEL_OUTPUT_EDP] = "eDP", | |
12006 | [INTEL_OUTPUT_DSI] = "DSI", | |
12007 | [INTEL_OUTPUT_UNKNOWN] = "Unknown", | |
12008 | }; | |
12009 | ||
12010 | if (output < 0 || output >= ARRAY_SIZE(names) || !names[output]) | |
12011 | return "Invalid"; | |
12012 | ||
12013 | return names[output]; | |
12014 | } | |
12015 | ||
84b4e042 JB |
12016 | static bool intel_crt_present(struct drm_device *dev) |
12017 | { | |
12018 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12019 | ||
12020 | if (IS_ULT(dev)) | |
12021 | return false; | |
12022 | ||
12023 | if (IS_CHERRYVIEW(dev)) | |
12024 | return false; | |
12025 | ||
12026 | if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support) | |
12027 | return false; | |
12028 | ||
12029 | return true; | |
12030 | } | |
12031 | ||
79e53945 JB |
12032 | static void intel_setup_outputs(struct drm_device *dev) |
12033 | { | |
725e30ad | 12034 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 12035 | struct intel_encoder *encoder; |
cb0953d7 | 12036 | bool dpd_is_edp = false; |
79e53945 | 12037 | |
c9093354 | 12038 | intel_lvds_init(dev); |
79e53945 | 12039 | |
84b4e042 | 12040 | if (intel_crt_present(dev)) |
79935fca | 12041 | intel_crt_init(dev); |
cb0953d7 | 12042 | |
affa9354 | 12043 | if (HAS_DDI(dev)) { |
0e72a5b5 ED |
12044 | int found; |
12045 | ||
12046 | /* Haswell uses DDI functions to detect digital outputs */ | |
12047 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; | |
12048 | /* DDI A only supports eDP */ | |
12049 | if (found) | |
12050 | intel_ddi_init(dev, PORT_A); | |
12051 | ||
12052 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
12053 | * register */ | |
12054 | found = I915_READ(SFUSE_STRAP); | |
12055 | ||
12056 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
12057 | intel_ddi_init(dev, PORT_B); | |
12058 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
12059 | intel_ddi_init(dev, PORT_C); | |
12060 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
12061 | intel_ddi_init(dev, PORT_D); | |
12062 | } else if (HAS_PCH_SPLIT(dev)) { | |
cb0953d7 | 12063 | int found; |
5d8a7752 | 12064 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
12065 | |
12066 | if (has_edp_a(dev)) | |
12067 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 12068 | |
dc0fa718 | 12069 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 12070 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 12071 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 | 12072 | if (!found) |
e2debe91 | 12073 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 12074 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 12075 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
12076 | } |
12077 | ||
dc0fa718 | 12078 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 12079 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 12080 | |
dc0fa718 | 12081 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 12082 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 12083 | |
5eb08b69 | 12084 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 12085 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 12086 | |
270b3042 | 12087 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 12088 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
4a87d65d | 12089 | } else if (IS_VALLEYVIEW(dev)) { |
585a94b8 AB |
12090 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) { |
12091 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, | |
12092 | PORT_B); | |
12093 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED) | |
12094 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); | |
12095 | } | |
12096 | ||
6f6005a5 JB |
12097 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) { |
12098 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, | |
12099 | PORT_C); | |
12100 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED) | |
5d8a7752 | 12101 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); |
6f6005a5 | 12102 | } |
19c03924 | 12103 | |
9418c1f1 VS |
12104 | if (IS_CHERRYVIEW(dev)) { |
12105 | if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) { | |
12106 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID, | |
12107 | PORT_D); | |
12108 | if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED) | |
12109 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D); | |
12110 | } | |
12111 | } | |
12112 | ||
3cfca973 | 12113 | intel_dsi_init(dev); |
103a196f | 12114 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 12115 | bool found = false; |
7d57382e | 12116 | |
e2debe91 | 12117 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 12118 | DRM_DEBUG_KMS("probing SDVOB\n"); |
e2debe91 | 12119 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
b01f2c3a JB |
12120 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
12121 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
e2debe91 | 12122 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 12123 | } |
27185ae1 | 12124 | |
e7281eab | 12125 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 12126 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 12127 | } |
13520b05 KH |
12128 | |
12129 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 12130 | |
e2debe91 | 12131 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 12132 | DRM_DEBUG_KMS("probing SDVOC\n"); |
e2debe91 | 12133 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
b01f2c3a | 12134 | } |
27185ae1 | 12135 | |
e2debe91 | 12136 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 12137 | |
b01f2c3a JB |
12138 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
12139 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
e2debe91 | 12140 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 12141 | } |
e7281eab | 12142 | if (SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 12143 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 12144 | } |
27185ae1 | 12145 | |
b01f2c3a | 12146 | if (SUPPORTS_INTEGRATED_DP(dev) && |
e7281eab | 12147 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 12148 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 12149 | } else if (IS_GEN2(dev)) |
79e53945 JB |
12150 | intel_dvo_init(dev); |
12151 | ||
103a196f | 12152 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
12153 | intel_tv_init(dev); |
12154 | ||
7c8f8a70 RV |
12155 | intel_edp_psr_init(dev); |
12156 | ||
4ef69c7a CW |
12157 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
12158 | encoder->base.possible_crtcs = encoder->crtc_mask; | |
12159 | encoder->base.possible_clones = | |
66a9278e | 12160 | intel_encoder_clones(encoder); |
79e53945 | 12161 | } |
47356eb6 | 12162 | |
dde86e2d | 12163 | intel_init_pch_refclk(dev); |
270b3042 DV |
12164 | |
12165 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
12166 | } |
12167 | ||
12168 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
12169 | { | |
60a5ca01 | 12170 | struct drm_device *dev = fb->dev; |
79e53945 | 12171 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 12172 | |
ef2d633e | 12173 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 12174 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 12175 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
60a5ca01 VS |
12176 | drm_gem_object_unreference(&intel_fb->obj->base); |
12177 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
12178 | kfree(intel_fb); |
12179 | } | |
12180 | ||
12181 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 12182 | struct drm_file *file, |
79e53945 JB |
12183 | unsigned int *handle) |
12184 | { | |
12185 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 12186 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 12187 | |
05394f39 | 12188 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
12189 | } |
12190 | ||
12191 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
12192 | .destroy = intel_user_framebuffer_destroy, | |
12193 | .create_handle = intel_user_framebuffer_create_handle, | |
12194 | }; | |
12195 | ||
b5ea642a DV |
12196 | static int intel_framebuffer_init(struct drm_device *dev, |
12197 | struct intel_framebuffer *intel_fb, | |
12198 | struct drm_mode_fb_cmd2 *mode_cmd, | |
12199 | struct drm_i915_gem_object *obj) | |
79e53945 | 12200 | { |
a57ce0b2 | 12201 | int aligned_height; |
a35cdaa0 | 12202 | int pitch_limit; |
79e53945 JB |
12203 | int ret; |
12204 | ||
dd4916c5 DV |
12205 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
12206 | ||
c16ed4be CW |
12207 | if (obj->tiling_mode == I915_TILING_Y) { |
12208 | DRM_DEBUG("hardware does not support tiling Y\n"); | |
57cd6508 | 12209 | return -EINVAL; |
c16ed4be | 12210 | } |
57cd6508 | 12211 | |
c16ed4be CW |
12212 | if (mode_cmd->pitches[0] & 63) { |
12213 | DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n", | |
12214 | mode_cmd->pitches[0]); | |
57cd6508 | 12215 | return -EINVAL; |
c16ed4be | 12216 | } |
57cd6508 | 12217 | |
a35cdaa0 CW |
12218 | if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) { |
12219 | pitch_limit = 32*1024; | |
12220 | } else if (INTEL_INFO(dev)->gen >= 4) { | |
12221 | if (obj->tiling_mode) | |
12222 | pitch_limit = 16*1024; | |
12223 | else | |
12224 | pitch_limit = 32*1024; | |
12225 | } else if (INTEL_INFO(dev)->gen >= 3) { | |
12226 | if (obj->tiling_mode) | |
12227 | pitch_limit = 8*1024; | |
12228 | else | |
12229 | pitch_limit = 16*1024; | |
12230 | } else | |
12231 | /* XXX DSPC is limited to 4k tiled */ | |
12232 | pitch_limit = 8*1024; | |
12233 | ||
12234 | if (mode_cmd->pitches[0] > pitch_limit) { | |
12235 | DRM_DEBUG("%s pitch (%d) must be at less than %d\n", | |
12236 | obj->tiling_mode ? "tiled" : "linear", | |
12237 | mode_cmd->pitches[0], pitch_limit); | |
5d7bd705 | 12238 | return -EINVAL; |
c16ed4be | 12239 | } |
5d7bd705 VS |
12240 | |
12241 | if (obj->tiling_mode != I915_TILING_NONE && | |
c16ed4be CW |
12242 | mode_cmd->pitches[0] != obj->stride) { |
12243 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
12244 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 12245 | return -EINVAL; |
c16ed4be | 12246 | } |
5d7bd705 | 12247 | |
57779d06 | 12248 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 12249 | switch (mode_cmd->pixel_format) { |
57779d06 | 12250 | case DRM_FORMAT_C8: |
04b3924d VS |
12251 | case DRM_FORMAT_RGB565: |
12252 | case DRM_FORMAT_XRGB8888: | |
12253 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
12254 | break; |
12255 | case DRM_FORMAT_XRGB1555: | |
12256 | case DRM_FORMAT_ARGB1555: | |
c16ed4be | 12257 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
12258 | DRM_DEBUG("unsupported pixel format: %s\n", |
12259 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 12260 | return -EINVAL; |
c16ed4be | 12261 | } |
57779d06 VS |
12262 | break; |
12263 | case DRM_FORMAT_XBGR8888: | |
12264 | case DRM_FORMAT_ABGR8888: | |
04b3924d VS |
12265 | case DRM_FORMAT_XRGB2101010: |
12266 | case DRM_FORMAT_ARGB2101010: | |
57779d06 VS |
12267 | case DRM_FORMAT_XBGR2101010: |
12268 | case DRM_FORMAT_ABGR2101010: | |
c16ed4be | 12269 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
12270 | DRM_DEBUG("unsupported pixel format: %s\n", |
12271 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 12272 | return -EINVAL; |
c16ed4be | 12273 | } |
b5626747 | 12274 | break; |
04b3924d VS |
12275 | case DRM_FORMAT_YUYV: |
12276 | case DRM_FORMAT_UYVY: | |
12277 | case DRM_FORMAT_YVYU: | |
12278 | case DRM_FORMAT_VYUY: | |
c16ed4be | 12279 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
12280 | DRM_DEBUG("unsupported pixel format: %s\n", |
12281 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 12282 | return -EINVAL; |
c16ed4be | 12283 | } |
57cd6508 CW |
12284 | break; |
12285 | default: | |
4ee62c76 VS |
12286 | DRM_DEBUG("unsupported pixel format: %s\n", |
12287 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
12288 | return -EINVAL; |
12289 | } | |
12290 | ||
90f9a336 VS |
12291 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
12292 | if (mode_cmd->offsets[0] != 0) | |
12293 | return -EINVAL; | |
12294 | ||
a57ce0b2 JB |
12295 | aligned_height = intel_align_height(dev, mode_cmd->height, |
12296 | obj->tiling_mode); | |
53155c0a DV |
12297 | /* FIXME drm helper for size checks (especially planar formats)? */ |
12298 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
12299 | return -EINVAL; | |
12300 | ||
c7d73f6a DV |
12301 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
12302 | intel_fb->obj = obj; | |
80075d49 | 12303 | intel_fb->obj->framebuffer_references++; |
c7d73f6a | 12304 | |
79e53945 JB |
12305 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
12306 | if (ret) { | |
12307 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
12308 | return ret; | |
12309 | } | |
12310 | ||
79e53945 JB |
12311 | return 0; |
12312 | } | |
12313 | ||
79e53945 JB |
12314 | static struct drm_framebuffer * |
12315 | intel_user_framebuffer_create(struct drm_device *dev, | |
12316 | struct drm_file *filp, | |
308e5bcb | 12317 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 12318 | { |
05394f39 | 12319 | struct drm_i915_gem_object *obj; |
79e53945 | 12320 | |
308e5bcb JB |
12321 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
12322 | mode_cmd->handles[0])); | |
c8725226 | 12323 | if (&obj->base == NULL) |
cce13ff7 | 12324 | return ERR_PTR(-ENOENT); |
79e53945 | 12325 | |
d2dff872 | 12326 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
12327 | } |
12328 | ||
4520f53a | 12329 | #ifndef CONFIG_DRM_I915_FBDEV |
0632fef6 | 12330 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
12331 | { |
12332 | } | |
12333 | #endif | |
12334 | ||
79e53945 | 12335 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 12336 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 12337 | .output_poll_changed = intel_fbdev_output_poll_changed, |
79e53945 JB |
12338 | }; |
12339 | ||
e70236a8 JB |
12340 | /* Set up chip specific display functions */ |
12341 | static void intel_init_display(struct drm_device *dev) | |
12342 | { | |
12343 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12344 | ||
ee9300bb DV |
12345 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
12346 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
ef9348c8 CML |
12347 | else if (IS_CHERRYVIEW(dev)) |
12348 | dev_priv->display.find_dpll = chv_find_best_dpll; | |
ee9300bb DV |
12349 | else if (IS_VALLEYVIEW(dev)) |
12350 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
12351 | else if (IS_PINEVIEW(dev)) | |
12352 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
12353 | else | |
12354 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
12355 | ||
affa9354 | 12356 | if (HAS_DDI(dev)) { |
0e8ffe1b | 12357 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
4c6baa59 | 12358 | dev_priv->display.get_plane_config = ironlake_get_plane_config; |
09b4ddf9 | 12359 | dev_priv->display.crtc_mode_set = haswell_crtc_mode_set; |
4f771f10 PZ |
12360 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
12361 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
df8ad70c | 12362 | dev_priv->display.off = ironlake_crtc_off; |
262ca2b0 MR |
12363 | dev_priv->display.update_primary_plane = |
12364 | ironlake_update_primary_plane; | |
09b4ddf9 | 12365 | } else if (HAS_PCH_SPLIT(dev)) { |
0e8ffe1b | 12366 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
4c6baa59 | 12367 | dev_priv->display.get_plane_config = ironlake_get_plane_config; |
f564048e | 12368 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
76e5a89c DV |
12369 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
12370 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
ee7b9f93 | 12371 | dev_priv->display.off = ironlake_crtc_off; |
262ca2b0 MR |
12372 | dev_priv->display.update_primary_plane = |
12373 | ironlake_update_primary_plane; | |
89b667f8 JB |
12374 | } else if (IS_VALLEYVIEW(dev)) { |
12375 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
1ad292b5 | 12376 | dev_priv->display.get_plane_config = i9xx_get_plane_config; |
89b667f8 JB |
12377 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
12378 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
12379 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
12380 | dev_priv->display.off = i9xx_crtc_off; | |
262ca2b0 MR |
12381 | dev_priv->display.update_primary_plane = |
12382 | i9xx_update_primary_plane; | |
f564048e | 12383 | } else { |
0e8ffe1b | 12384 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
1ad292b5 | 12385 | dev_priv->display.get_plane_config = i9xx_get_plane_config; |
f564048e | 12386 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
76e5a89c DV |
12387 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
12388 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
ee7b9f93 | 12389 | dev_priv->display.off = i9xx_crtc_off; |
262ca2b0 MR |
12390 | dev_priv->display.update_primary_plane = |
12391 | i9xx_update_primary_plane; | |
f564048e | 12392 | } |
e70236a8 | 12393 | |
e70236a8 | 12394 | /* Returns the core display clock speed */ |
25eb05fc JB |
12395 | if (IS_VALLEYVIEW(dev)) |
12396 | dev_priv->display.get_display_clock_speed = | |
12397 | valleyview_get_display_clock_speed; | |
12398 | else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) | |
e70236a8 JB |
12399 | dev_priv->display.get_display_clock_speed = |
12400 | i945_get_display_clock_speed; | |
12401 | else if (IS_I915G(dev)) | |
12402 | dev_priv->display.get_display_clock_speed = | |
12403 | i915_get_display_clock_speed; | |
257a7ffc | 12404 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
12405 | dev_priv->display.get_display_clock_speed = |
12406 | i9xx_misc_get_display_clock_speed; | |
257a7ffc DV |
12407 | else if (IS_PINEVIEW(dev)) |
12408 | dev_priv->display.get_display_clock_speed = | |
12409 | pnv_get_display_clock_speed; | |
e70236a8 JB |
12410 | else if (IS_I915GM(dev)) |
12411 | dev_priv->display.get_display_clock_speed = | |
12412 | i915gm_get_display_clock_speed; | |
12413 | else if (IS_I865G(dev)) | |
12414 | dev_priv->display.get_display_clock_speed = | |
12415 | i865_get_display_clock_speed; | |
f0f8a9ce | 12416 | else if (IS_I85X(dev)) |
e70236a8 JB |
12417 | dev_priv->display.get_display_clock_speed = |
12418 | i855_get_display_clock_speed; | |
12419 | else /* 852, 830 */ | |
12420 | dev_priv->display.get_display_clock_speed = | |
12421 | i830_get_display_clock_speed; | |
12422 | ||
7f8a8569 | 12423 | if (HAS_PCH_SPLIT(dev)) { |
f00a3ddf | 12424 | if (IS_GEN5(dev)) { |
674cf967 | 12425 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
e0dac65e | 12426 | dev_priv->display.write_eld = ironlake_write_eld; |
1398261a | 12427 | } else if (IS_GEN6(dev)) { |
674cf967 | 12428 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
e0dac65e | 12429 | dev_priv->display.write_eld = ironlake_write_eld; |
9a952a0d PZ |
12430 | dev_priv->display.modeset_global_resources = |
12431 | snb_modeset_global_resources; | |
357555c0 JB |
12432 | } else if (IS_IVYBRIDGE(dev)) { |
12433 | /* FIXME: detect B0+ stepping and use auto training */ | |
12434 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
e0dac65e | 12435 | dev_priv->display.write_eld = ironlake_write_eld; |
01a415fd DV |
12436 | dev_priv->display.modeset_global_resources = |
12437 | ivb_modeset_global_resources; | |
4e0bbc31 | 12438 | } else if (IS_HASWELL(dev) || IS_GEN8(dev)) { |
c82e4d26 | 12439 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
83358c85 | 12440 | dev_priv->display.write_eld = haswell_write_eld; |
d6dd9eb1 DV |
12441 | dev_priv->display.modeset_global_resources = |
12442 | haswell_modeset_global_resources; | |
a0e63c22 | 12443 | } |
6067aaea | 12444 | } else if (IS_G4X(dev)) { |
e0dac65e | 12445 | dev_priv->display.write_eld = g4x_write_eld; |
30a970c6 JB |
12446 | } else if (IS_VALLEYVIEW(dev)) { |
12447 | dev_priv->display.modeset_global_resources = | |
12448 | valleyview_modeset_global_resources; | |
9ca2fe73 | 12449 | dev_priv->display.write_eld = ironlake_write_eld; |
e70236a8 | 12450 | } |
8c9f3aaf JB |
12451 | |
12452 | /* Default just returns -ENODEV to indicate unsupported */ | |
12453 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
12454 | ||
12455 | switch (INTEL_INFO(dev)->gen) { | |
12456 | case 2: | |
12457 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
12458 | break; | |
12459 | ||
12460 | case 3: | |
12461 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
12462 | break; | |
12463 | ||
12464 | case 4: | |
12465 | case 5: | |
12466 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
12467 | break; | |
12468 | ||
12469 | case 6: | |
12470 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
12471 | break; | |
7c9017e5 | 12472 | case 7: |
4e0bbc31 | 12473 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
12474 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
12475 | break; | |
8c9f3aaf | 12476 | } |
7bd688cd JN |
12477 | |
12478 | intel_panel_init_backlight_funcs(dev); | |
e70236a8 JB |
12479 | } |
12480 | ||
b690e96c JB |
12481 | /* |
12482 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
12483 | * resume, or other times. This quirk makes sure that's the case for | |
12484 | * affected systems. | |
12485 | */ | |
0206e353 | 12486 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
12487 | { |
12488 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12489 | ||
12490 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 12491 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
12492 | } |
12493 | ||
435793df KP |
12494 | /* |
12495 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
12496 | */ | |
12497 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
12498 | { | |
12499 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12500 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 12501 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
12502 | } |
12503 | ||
4dca20ef | 12504 | /* |
5a15ab5b CE |
12505 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
12506 | * brightness value | |
4dca20ef CE |
12507 | */ |
12508 | static void quirk_invert_brightness(struct drm_device *dev) | |
12509 | { | |
12510 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12511 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 12512 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
12513 | } |
12514 | ||
9c72cc6f SD |
12515 | /* Some VBT's incorrectly indicate no backlight is present */ |
12516 | static void quirk_backlight_present(struct drm_device *dev) | |
12517 | { | |
12518 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12519 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; | |
12520 | DRM_INFO("applying backlight present quirk\n"); | |
12521 | } | |
12522 | ||
b690e96c JB |
12523 | struct intel_quirk { |
12524 | int device; | |
12525 | int subsystem_vendor; | |
12526 | int subsystem_device; | |
12527 | void (*hook)(struct drm_device *dev); | |
12528 | }; | |
12529 | ||
5f85f176 EE |
12530 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
12531 | struct intel_dmi_quirk { | |
12532 | void (*hook)(struct drm_device *dev); | |
12533 | const struct dmi_system_id (*dmi_id_list)[]; | |
12534 | }; | |
12535 | ||
12536 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
12537 | { | |
12538 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
12539 | return 1; | |
12540 | } | |
12541 | ||
12542 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
12543 | { | |
12544 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
12545 | { | |
12546 | .callback = intel_dmi_reverse_brightness, | |
12547 | .ident = "NCR Corporation", | |
12548 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
12549 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
12550 | }, | |
12551 | }, | |
12552 | { } /* terminating entry */ | |
12553 | }, | |
12554 | .hook = quirk_invert_brightness, | |
12555 | }, | |
12556 | }; | |
12557 | ||
c43b5634 | 12558 | static struct intel_quirk intel_quirks[] = { |
b690e96c | 12559 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
0206e353 | 12560 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
b690e96c | 12561 | |
b690e96c JB |
12562 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
12563 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
12564 | ||
b690e96c JB |
12565 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
12566 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
12567 | ||
435793df KP |
12568 | /* Lenovo U160 cannot use SSC on LVDS */ |
12569 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
12570 | |
12571 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
12572 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 12573 | |
be505f64 AH |
12574 | /* Acer Aspire 5734Z must invert backlight brightness */ |
12575 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
12576 | ||
12577 | /* Acer/eMachines G725 */ | |
12578 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
12579 | ||
12580 | /* Acer/eMachines e725 */ | |
12581 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
12582 | ||
12583 | /* Acer/Packard Bell NCL20 */ | |
12584 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
12585 | ||
12586 | /* Acer Aspire 4736Z */ | |
12587 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
12588 | |
12589 | /* Acer Aspire 5336 */ | |
12590 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
12591 | |
12592 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
12593 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c SD |
12594 | |
12595 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ | |
12596 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
12597 | |
12598 | /* HP Chromebook 14 (Celeron 2955U) */ | |
12599 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
b690e96c JB |
12600 | }; |
12601 | ||
12602 | static void intel_init_quirks(struct drm_device *dev) | |
12603 | { | |
12604 | struct pci_dev *d = dev->pdev; | |
12605 | int i; | |
12606 | ||
12607 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
12608 | struct intel_quirk *q = &intel_quirks[i]; | |
12609 | ||
12610 | if (d->device == q->device && | |
12611 | (d->subsystem_vendor == q->subsystem_vendor || | |
12612 | q->subsystem_vendor == PCI_ANY_ID) && | |
12613 | (d->subsystem_device == q->subsystem_device || | |
12614 | q->subsystem_device == PCI_ANY_ID)) | |
12615 | q->hook(dev); | |
12616 | } | |
5f85f176 EE |
12617 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
12618 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
12619 | intel_dmi_quirks[i].hook(dev); | |
12620 | } | |
b690e96c JB |
12621 | } |
12622 | ||
9cce37f4 JB |
12623 | /* Disable the VGA plane that we never use */ |
12624 | static void i915_disable_vga(struct drm_device *dev) | |
12625 | { | |
12626 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12627 | u8 sr1; | |
766aa1c4 | 12628 | u32 vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 12629 | |
2b37c616 | 12630 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 12631 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 12632 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
12633 | sr1 = inb(VGA_SR_DATA); |
12634 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
12635 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
12636 | udelay(300); | |
12637 | ||
12638 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); | |
12639 | POSTING_READ(vga_reg); | |
12640 | } | |
12641 | ||
f817586c DV |
12642 | void intel_modeset_init_hw(struct drm_device *dev) |
12643 | { | |
a8f78b58 ED |
12644 | intel_prepare_ddi(dev); |
12645 | ||
f8bf63fd VS |
12646 | if (IS_VALLEYVIEW(dev)) |
12647 | vlv_update_cdclk(dev); | |
12648 | ||
f817586c DV |
12649 | intel_init_clock_gating(dev); |
12650 | ||
8090c6b9 | 12651 | intel_enable_gt_powersave(dev); |
f817586c DV |
12652 | } |
12653 | ||
7d708ee4 ID |
12654 | void intel_modeset_suspend_hw(struct drm_device *dev) |
12655 | { | |
12656 | intel_suspend_hw(dev); | |
12657 | } | |
12658 | ||
79e53945 JB |
12659 | void intel_modeset_init(struct drm_device *dev) |
12660 | { | |
652c393a | 12661 | struct drm_i915_private *dev_priv = dev->dev_private; |
1fe47785 | 12662 | int sprite, ret; |
8cc87b75 | 12663 | enum pipe pipe; |
46f297fb | 12664 | struct intel_crtc *crtc; |
79e53945 JB |
12665 | |
12666 | drm_mode_config_init(dev); | |
12667 | ||
12668 | dev->mode_config.min_width = 0; | |
12669 | dev->mode_config.min_height = 0; | |
12670 | ||
019d96cb DA |
12671 | dev->mode_config.preferred_depth = 24; |
12672 | dev->mode_config.prefer_shadow = 1; | |
12673 | ||
e6ecefaa | 12674 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 12675 | |
b690e96c JB |
12676 | intel_init_quirks(dev); |
12677 | ||
1fa61106 ED |
12678 | intel_init_pm(dev); |
12679 | ||
e3c74757 BW |
12680 | if (INTEL_INFO(dev)->num_pipes == 0) |
12681 | return; | |
12682 | ||
e70236a8 JB |
12683 | intel_init_display(dev); |
12684 | ||
a6c45cf0 CW |
12685 | if (IS_GEN2(dev)) { |
12686 | dev->mode_config.max_width = 2048; | |
12687 | dev->mode_config.max_height = 2048; | |
12688 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
12689 | dev->mode_config.max_width = 4096; |
12690 | dev->mode_config.max_height = 4096; | |
79e53945 | 12691 | } else { |
a6c45cf0 CW |
12692 | dev->mode_config.max_width = 8192; |
12693 | dev->mode_config.max_height = 8192; | |
79e53945 | 12694 | } |
068be561 DL |
12695 | |
12696 | if (IS_GEN2(dev)) { | |
12697 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; | |
12698 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
12699 | } else { | |
12700 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
12701 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
12702 | } | |
12703 | ||
5d4545ae | 12704 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 12705 | |
28c97730 | 12706 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
12707 | INTEL_INFO(dev)->num_pipes, |
12708 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 12709 | |
8cc87b75 DL |
12710 | for_each_pipe(pipe) { |
12711 | intel_crtc_init(dev, pipe); | |
1fe47785 DL |
12712 | for_each_sprite(pipe, sprite) { |
12713 | ret = intel_plane_init(dev, pipe, sprite); | |
7f1f3851 | 12714 | if (ret) |
06da8da2 | 12715 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 12716 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 12717 | } |
79e53945 JB |
12718 | } |
12719 | ||
f42bb70d JB |
12720 | intel_init_dpio(dev); |
12721 | ||
e72f9fbf | 12722 | intel_shared_dpll_init(dev); |
ee7b9f93 | 12723 | |
9cce37f4 JB |
12724 | /* Just disable it once at startup */ |
12725 | i915_disable_vga(dev); | |
79e53945 | 12726 | intel_setup_outputs(dev); |
11be49eb CW |
12727 | |
12728 | /* Just in case the BIOS is doing something questionable. */ | |
12729 | intel_disable_fbc(dev); | |
fa9fa083 | 12730 | |
6e9f798d | 12731 | drm_modeset_lock_all(dev); |
fa9fa083 | 12732 | intel_modeset_setup_hw_state(dev, false); |
6e9f798d | 12733 | drm_modeset_unlock_all(dev); |
46f297fb | 12734 | |
d3fcc808 | 12735 | for_each_intel_crtc(dev, crtc) { |
46f297fb JB |
12736 | if (!crtc->active) |
12737 | continue; | |
12738 | ||
46f297fb | 12739 | /* |
46f297fb JB |
12740 | * Note that reserving the BIOS fb up front prevents us |
12741 | * from stuffing other stolen allocations like the ring | |
12742 | * on top. This prevents some ugliness at boot time, and | |
12743 | * can even allow for smooth boot transitions if the BIOS | |
12744 | * fb is large enough for the active pipe configuration. | |
12745 | */ | |
12746 | if (dev_priv->display.get_plane_config) { | |
12747 | dev_priv->display.get_plane_config(crtc, | |
12748 | &crtc->plane_config); | |
12749 | /* | |
12750 | * If the fb is shared between multiple heads, we'll | |
12751 | * just get the first one. | |
12752 | */ | |
484b41dd | 12753 | intel_find_plane_obj(crtc, &crtc->plane_config); |
46f297fb | 12754 | } |
46f297fb | 12755 | } |
2c7111db CW |
12756 | } |
12757 | ||
7fad798e DV |
12758 | static void intel_enable_pipe_a(struct drm_device *dev) |
12759 | { | |
12760 | struct intel_connector *connector; | |
12761 | struct drm_connector *crt = NULL; | |
12762 | struct intel_load_detect_pipe load_detect_temp; | |
51fd371b | 12763 | struct drm_modeset_acquire_ctx ctx; |
7fad798e DV |
12764 | |
12765 | /* We can't just switch on the pipe A, we need to set things up with a | |
12766 | * proper mode and output configuration. As a gross hack, enable pipe A | |
12767 | * by enabling the load detect pipe once. */ | |
12768 | list_for_each_entry(connector, | |
12769 | &dev->mode_config.connector_list, | |
12770 | base.head) { | |
12771 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { | |
12772 | crt = &connector->base; | |
12773 | break; | |
12774 | } | |
12775 | } | |
12776 | ||
12777 | if (!crt) | |
12778 | return; | |
12779 | ||
51fd371b RC |
12780 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, &ctx)) |
12781 | intel_release_load_detect_pipe(crt, &load_detect_temp, &ctx); | |
7fad798e | 12782 | |
652c393a | 12783 | |
7fad798e DV |
12784 | } |
12785 | ||
fa555837 DV |
12786 | static bool |
12787 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
12788 | { | |
7eb552ae BW |
12789 | struct drm_device *dev = crtc->base.dev; |
12790 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 DV |
12791 | u32 reg, val; |
12792 | ||
7eb552ae | 12793 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
12794 | return true; |
12795 | ||
12796 | reg = DSPCNTR(!crtc->plane); | |
12797 | val = I915_READ(reg); | |
12798 | ||
12799 | if ((val & DISPLAY_PLANE_ENABLE) && | |
12800 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
12801 | return false; | |
12802 | ||
12803 | return true; | |
12804 | } | |
12805 | ||
24929352 DV |
12806 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
12807 | { | |
12808 | struct drm_device *dev = crtc->base.dev; | |
12809 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 | 12810 | u32 reg; |
24929352 | 12811 | |
24929352 | 12812 | /* Clear any frame start delays used for debugging left by the BIOS */ |
3b117c8f | 12813 | reg = PIPECONF(crtc->config.cpu_transcoder); |
24929352 DV |
12814 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
12815 | ||
d3eaf884 VS |
12816 | /* restore vblank interrupts to correct state */ |
12817 | if (crtc->active) | |
12818 | drm_vblank_on(dev, crtc->pipe); | |
12819 | else | |
12820 | drm_vblank_off(dev, crtc->pipe); | |
12821 | ||
24929352 | 12822 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
12823 | * disable the crtc (and hence change the state) if it is wrong. Note |
12824 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
12825 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
12826 | struct intel_connector *connector; |
12827 | bool plane; | |
12828 | ||
24929352 DV |
12829 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
12830 | crtc->base.base.id); | |
12831 | ||
12832 | /* Pipe has the wrong plane attached and the plane is active. | |
12833 | * Temporarily change the plane mapping and disable everything | |
12834 | * ... */ | |
12835 | plane = crtc->plane; | |
12836 | crtc->plane = !plane; | |
9c8958bc | 12837 | crtc->primary_enabled = true; |
24929352 DV |
12838 | dev_priv->display.crtc_disable(&crtc->base); |
12839 | crtc->plane = plane; | |
12840 | ||
12841 | /* ... and break all links. */ | |
12842 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
12843 | base.head) { | |
12844 | if (connector->encoder->base.crtc != &crtc->base) | |
12845 | continue; | |
12846 | ||
7f1950fb EE |
12847 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
12848 | connector->base.encoder = NULL; | |
24929352 | 12849 | } |
7f1950fb EE |
12850 | /* multiple connectors may have the same encoder: |
12851 | * handle them and break crtc link separately */ | |
12852 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
12853 | base.head) | |
12854 | if (connector->encoder->base.crtc == &crtc->base) { | |
12855 | connector->encoder->base.crtc = NULL; | |
12856 | connector->encoder->connectors_active = false; | |
12857 | } | |
24929352 DV |
12858 | |
12859 | WARN_ON(crtc->active); | |
12860 | crtc->base.enabled = false; | |
12861 | } | |
24929352 | 12862 | |
7fad798e DV |
12863 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
12864 | crtc->pipe == PIPE_A && !crtc->active) { | |
12865 | /* BIOS forgot to enable pipe A, this mostly happens after | |
12866 | * resume. Force-enable the pipe to fix this, the update_dpms | |
12867 | * call below we restore the pipe to the right state, but leave | |
12868 | * the required bits on. */ | |
12869 | intel_enable_pipe_a(dev); | |
12870 | } | |
12871 | ||
24929352 DV |
12872 | /* Adjust the state of the output pipe according to whether we |
12873 | * have active connectors/encoders. */ | |
12874 | intel_crtc_update_dpms(&crtc->base); | |
12875 | ||
12876 | if (crtc->active != crtc->base.enabled) { | |
12877 | struct intel_encoder *encoder; | |
12878 | ||
12879 | /* This can happen either due to bugs in the get_hw_state | |
12880 | * functions or because the pipe is force-enabled due to the | |
12881 | * pipe A quirk. */ | |
12882 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
12883 | crtc->base.base.id, | |
12884 | crtc->base.enabled ? "enabled" : "disabled", | |
12885 | crtc->active ? "enabled" : "disabled"); | |
12886 | ||
12887 | crtc->base.enabled = crtc->active; | |
12888 | ||
12889 | /* Because we only establish the connector -> encoder -> | |
12890 | * crtc links if something is active, this means the | |
12891 | * crtc is now deactivated. Break the links. connector | |
12892 | * -> encoder links are only establish when things are | |
12893 | * actually up, hence no need to break them. */ | |
12894 | WARN_ON(crtc->active); | |
12895 | ||
12896 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { | |
12897 | WARN_ON(encoder->connectors_active); | |
12898 | encoder->base.crtc = NULL; | |
12899 | } | |
12900 | } | |
c5ab3bc0 DV |
12901 | |
12902 | if (crtc->active || IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen < 5) { | |
4cc31489 DV |
12903 | /* |
12904 | * We start out with underrun reporting disabled to avoid races. | |
12905 | * For correct bookkeeping mark this on active crtcs. | |
12906 | * | |
c5ab3bc0 DV |
12907 | * Also on gmch platforms we dont have any hardware bits to |
12908 | * disable the underrun reporting. Which means we need to start | |
12909 | * out with underrun reporting disabled also on inactive pipes, | |
12910 | * since otherwise we'll complain about the garbage we read when | |
12911 | * e.g. coming up after runtime pm. | |
12912 | * | |
4cc31489 DV |
12913 | * No protection against concurrent access is required - at |
12914 | * worst a fifo underrun happens which also sets this to false. | |
12915 | */ | |
12916 | crtc->cpu_fifo_underrun_disabled = true; | |
12917 | crtc->pch_fifo_underrun_disabled = true; | |
80715b2f VS |
12918 | |
12919 | update_scanline_offset(crtc); | |
4cc31489 | 12920 | } |
24929352 DV |
12921 | } |
12922 | ||
12923 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
12924 | { | |
12925 | struct intel_connector *connector; | |
12926 | struct drm_device *dev = encoder->base.dev; | |
12927 | ||
12928 | /* We need to check both for a crtc link (meaning that the | |
12929 | * encoder is active and trying to read from a pipe) and the | |
12930 | * pipe itself being active. */ | |
12931 | bool has_active_crtc = encoder->base.crtc && | |
12932 | to_intel_crtc(encoder->base.crtc)->active; | |
12933 | ||
12934 | if (encoder->connectors_active && !has_active_crtc) { | |
12935 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", | |
12936 | encoder->base.base.id, | |
8e329a03 | 12937 | encoder->base.name); |
24929352 DV |
12938 | |
12939 | /* Connector is active, but has no active pipe. This is | |
12940 | * fallout from our resume register restoring. Disable | |
12941 | * the encoder manually again. */ | |
12942 | if (encoder->base.crtc) { | |
12943 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
12944 | encoder->base.base.id, | |
8e329a03 | 12945 | encoder->base.name); |
24929352 | 12946 | encoder->disable(encoder); |
a62d1497 VS |
12947 | if (encoder->post_disable) |
12948 | encoder->post_disable(encoder); | |
24929352 | 12949 | } |
7f1950fb EE |
12950 | encoder->base.crtc = NULL; |
12951 | encoder->connectors_active = false; | |
24929352 DV |
12952 | |
12953 | /* Inconsistent output/port/pipe state happens presumably due to | |
12954 | * a bug in one of the get_hw_state functions. Or someplace else | |
12955 | * in our code, like the register restore mess on resume. Clamp | |
12956 | * things to off as a safer default. */ | |
12957 | list_for_each_entry(connector, | |
12958 | &dev->mode_config.connector_list, | |
12959 | base.head) { | |
12960 | if (connector->encoder != encoder) | |
12961 | continue; | |
7f1950fb EE |
12962 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
12963 | connector->base.encoder = NULL; | |
24929352 DV |
12964 | } |
12965 | } | |
12966 | /* Enabled encoders without active connectors will be fixed in | |
12967 | * the crtc fixup. */ | |
12968 | } | |
12969 | ||
04098753 | 12970 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
12971 | { |
12972 | struct drm_i915_private *dev_priv = dev->dev_private; | |
766aa1c4 | 12973 | u32 vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 12974 | |
04098753 ID |
12975 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
12976 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
12977 | i915_disable_vga(dev); | |
12978 | } | |
12979 | } | |
12980 | ||
12981 | void i915_redisable_vga(struct drm_device *dev) | |
12982 | { | |
12983 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12984 | ||
8dc8a27c PZ |
12985 | /* This function can be called both from intel_modeset_setup_hw_state or |
12986 | * at a very early point in our resume sequence, where the power well | |
12987 | * structures are not yet restored. Since this function is at a very | |
12988 | * paranoid "someone might have enabled VGA while we were not looking" | |
12989 | * level, just check if the power well is enabled instead of trying to | |
12990 | * follow the "don't touch the power well if we don't need it" policy | |
12991 | * the rest of the driver uses. */ | |
04098753 | 12992 | if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
12993 | return; |
12994 | ||
04098753 | 12995 | i915_redisable_vga_power_on(dev); |
0fde901f KM |
12996 | } |
12997 | ||
98ec7739 VS |
12998 | static bool primary_get_hw_state(struct intel_crtc *crtc) |
12999 | { | |
13000 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
13001 | ||
13002 | if (!crtc->active) | |
13003 | return false; | |
13004 | ||
13005 | return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE; | |
13006 | } | |
13007 | ||
30e984df | 13008 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
13009 | { |
13010 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13011 | enum pipe pipe; | |
24929352 DV |
13012 | struct intel_crtc *crtc; |
13013 | struct intel_encoder *encoder; | |
13014 | struct intel_connector *connector; | |
5358901f | 13015 | int i; |
24929352 | 13016 | |
d3fcc808 | 13017 | for_each_intel_crtc(dev, crtc) { |
88adfff1 | 13018 | memset(&crtc->config, 0, sizeof(crtc->config)); |
3b117c8f | 13019 | |
9953599b DV |
13020 | crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE; |
13021 | ||
0e8ffe1b DV |
13022 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
13023 | &crtc->config); | |
24929352 DV |
13024 | |
13025 | crtc->base.enabled = crtc->active; | |
98ec7739 | 13026 | crtc->primary_enabled = primary_get_hw_state(crtc); |
24929352 DV |
13027 | |
13028 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
13029 | crtc->base.base.id, | |
13030 | crtc->active ? "enabled" : "disabled"); | |
13031 | } | |
13032 | ||
5358901f DV |
13033 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
13034 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
13035 | ||
13036 | pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state); | |
13037 | pll->active = 0; | |
d3fcc808 | 13038 | for_each_intel_crtc(dev, crtc) { |
5358901f DV |
13039 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) |
13040 | pll->active++; | |
13041 | } | |
13042 | pll->refcount = pll->active; | |
13043 | ||
35c95375 DV |
13044 | DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n", |
13045 | pll->name, pll->refcount, pll->on); | |
bd2bb1b9 PZ |
13046 | |
13047 | if (pll->refcount) | |
13048 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); | |
5358901f DV |
13049 | } |
13050 | ||
24929352 DV |
13051 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
13052 | base.head) { | |
13053 | pipe = 0; | |
13054 | ||
13055 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
13056 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
13057 | encoder->base.crtc = &crtc->base; | |
1d37b689 | 13058 | encoder->get_config(encoder, &crtc->config); |
24929352 DV |
13059 | } else { |
13060 | encoder->base.crtc = NULL; | |
13061 | } | |
13062 | ||
13063 | encoder->connectors_active = false; | |
6f2bcceb | 13064 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 13065 | encoder->base.base.id, |
8e329a03 | 13066 | encoder->base.name, |
24929352 | 13067 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 13068 | pipe_name(pipe)); |
24929352 DV |
13069 | } |
13070 | ||
13071 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
13072 | base.head) { | |
13073 | if (connector->get_hw_state(connector)) { | |
13074 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
13075 | connector->encoder->connectors_active = true; | |
13076 | connector->base.encoder = &connector->encoder->base; | |
13077 | } else { | |
13078 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
13079 | connector->base.encoder = NULL; | |
13080 | } | |
13081 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
13082 | connector->base.base.id, | |
c23cc417 | 13083 | connector->base.name, |
24929352 DV |
13084 | connector->base.encoder ? "enabled" : "disabled"); |
13085 | } | |
30e984df DV |
13086 | } |
13087 | ||
13088 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm | |
13089 | * and i915 state tracking structures. */ | |
13090 | void intel_modeset_setup_hw_state(struct drm_device *dev, | |
13091 | bool force_restore) | |
13092 | { | |
13093 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13094 | enum pipe pipe; | |
30e984df DV |
13095 | struct intel_crtc *crtc; |
13096 | struct intel_encoder *encoder; | |
35c95375 | 13097 | int i; |
30e984df DV |
13098 | |
13099 | intel_modeset_readout_hw_state(dev); | |
24929352 | 13100 | |
babea61d JB |
13101 | /* |
13102 | * Now that we have the config, copy it to each CRTC struct | |
13103 | * Note that this could go away if we move to using crtc_config | |
13104 | * checking everywhere. | |
13105 | */ | |
d3fcc808 | 13106 | for_each_intel_crtc(dev, crtc) { |
d330a953 | 13107 | if (crtc->active && i915.fastboot) { |
f6a83288 | 13108 | intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config); |
babea61d JB |
13109 | DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", |
13110 | crtc->base.base.id); | |
13111 | drm_mode_debug_printmodeline(&crtc->base.mode); | |
13112 | } | |
13113 | } | |
13114 | ||
24929352 DV |
13115 | /* HW state is read out, now we need to sanitize this mess. */ |
13116 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
13117 | base.head) { | |
13118 | intel_sanitize_encoder(encoder); | |
13119 | } | |
13120 | ||
13121 | for_each_pipe(pipe) { | |
13122 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
13123 | intel_sanitize_crtc(crtc); | |
c0b03411 | 13124 | intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]"); |
24929352 | 13125 | } |
9a935856 | 13126 | |
35c95375 DV |
13127 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
13128 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
13129 | ||
13130 | if (!pll->on || pll->active) | |
13131 | continue; | |
13132 | ||
13133 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
13134 | ||
13135 | pll->disable(dev_priv, pll); | |
13136 | pll->on = false; | |
13137 | } | |
13138 | ||
96f90c54 | 13139 | if (HAS_PCH_SPLIT(dev)) |
243e6a44 VS |
13140 | ilk_wm_get_hw_state(dev); |
13141 | ||
45e2b5f6 | 13142 | if (force_restore) { |
7d0bc1ea VS |
13143 | i915_redisable_vga(dev); |
13144 | ||
f30da187 DV |
13145 | /* |
13146 | * We need to use raw interfaces for restoring state to avoid | |
13147 | * checking (bogus) intermediate states. | |
13148 | */ | |
45e2b5f6 | 13149 | for_each_pipe(pipe) { |
b5644d05 JB |
13150 | struct drm_crtc *crtc = |
13151 | dev_priv->pipe_to_crtc_mapping[pipe]; | |
f30da187 DV |
13152 | |
13153 | __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, | |
f4510a27 | 13154 | crtc->primary->fb); |
45e2b5f6 DV |
13155 | } |
13156 | } else { | |
13157 | intel_modeset_update_staged_output_state(dev); | |
13158 | } | |
8af6cf88 DV |
13159 | |
13160 | intel_modeset_check_state(dev); | |
2c7111db CW |
13161 | } |
13162 | ||
13163 | void intel_modeset_gem_init(struct drm_device *dev) | |
13164 | { | |
484b41dd | 13165 | struct drm_crtc *c; |
2ff8fde1 | 13166 | struct drm_i915_gem_object *obj; |
484b41dd | 13167 | |
ae48434c ID |
13168 | mutex_lock(&dev->struct_mutex); |
13169 | intel_init_gt_powersave(dev); | |
13170 | mutex_unlock(&dev->struct_mutex); | |
13171 | ||
1833b134 | 13172 | intel_modeset_init_hw(dev); |
02e792fb DV |
13173 | |
13174 | intel_setup_overlay(dev); | |
484b41dd JB |
13175 | |
13176 | /* | |
13177 | * Make sure any fbs we allocated at startup are properly | |
13178 | * pinned & fenced. When we do the allocation it's too early | |
13179 | * for this. | |
13180 | */ | |
13181 | mutex_lock(&dev->struct_mutex); | |
70e1e0ec | 13182 | for_each_crtc(dev, c) { |
2ff8fde1 MR |
13183 | obj = intel_fb_obj(c->primary->fb); |
13184 | if (obj == NULL) | |
484b41dd JB |
13185 | continue; |
13186 | ||
2ff8fde1 | 13187 | if (intel_pin_and_fence_fb_obj(dev, obj, NULL)) { |
484b41dd JB |
13188 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
13189 | to_intel_crtc(c)->pipe); | |
66e514c1 DA |
13190 | drm_framebuffer_unreference(c->primary->fb); |
13191 | c->primary->fb = NULL; | |
484b41dd JB |
13192 | } |
13193 | } | |
13194 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
13195 | } |
13196 | ||
4932e2c3 ID |
13197 | void intel_connector_unregister(struct intel_connector *intel_connector) |
13198 | { | |
13199 | struct drm_connector *connector = &intel_connector->base; | |
13200 | ||
13201 | intel_panel_destroy_backlight(connector); | |
34ea3d38 | 13202 | drm_connector_unregister(connector); |
4932e2c3 ID |
13203 | } |
13204 | ||
79e53945 JB |
13205 | void intel_modeset_cleanup(struct drm_device *dev) |
13206 | { | |
652c393a | 13207 | struct drm_i915_private *dev_priv = dev->dev_private; |
d9255d57 | 13208 | struct drm_connector *connector; |
652c393a | 13209 | |
fd0c0642 DV |
13210 | /* |
13211 | * Interrupts and polling as the first thing to avoid creating havoc. | |
13212 | * Too much stuff here (turning of rps, connectors, ...) would | |
13213 | * experience fancy races otherwise. | |
13214 | */ | |
13215 | drm_irq_uninstall(dev); | |
13216 | cancel_work_sync(&dev_priv->hotplug_work); | |
eb21b92b JB |
13217 | dev_priv->pm._irqs_disabled = true; |
13218 | ||
fd0c0642 DV |
13219 | /* |
13220 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
13221 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
13222 | */ | |
f87ea761 | 13223 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 13224 | |
652c393a JB |
13225 | mutex_lock(&dev->struct_mutex); |
13226 | ||
723bfd70 JB |
13227 | intel_unregister_dsm_handler(); |
13228 | ||
973d04f9 | 13229 | intel_disable_fbc(dev); |
e70236a8 | 13230 | |
8090c6b9 | 13231 | intel_disable_gt_powersave(dev); |
0cdab21f | 13232 | |
930ebb46 DV |
13233 | ironlake_teardown_rc6(dev); |
13234 | ||
69341a5e KH |
13235 | mutex_unlock(&dev->struct_mutex); |
13236 | ||
1630fe75 CW |
13237 | /* flush any delayed tasks or pending work */ |
13238 | flush_scheduled_work(); | |
13239 | ||
db31af1d JN |
13240 | /* destroy the backlight and sysfs files before encoders/connectors */ |
13241 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4932e2c3 ID |
13242 | struct intel_connector *intel_connector; |
13243 | ||
13244 | intel_connector = to_intel_connector(connector); | |
13245 | intel_connector->unregister(intel_connector); | |
db31af1d | 13246 | } |
d9255d57 | 13247 | |
79e53945 | 13248 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
13249 | |
13250 | intel_cleanup_overlay(dev); | |
ae48434c ID |
13251 | |
13252 | mutex_lock(&dev->struct_mutex); | |
13253 | intel_cleanup_gt_powersave(dev); | |
13254 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
13255 | } |
13256 | ||
f1c79df3 ZW |
13257 | /* |
13258 | * Return which encoder is currently attached for connector. | |
13259 | */ | |
df0e9248 | 13260 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 13261 | { |
df0e9248 CW |
13262 | return &intel_attached_encoder(connector)->base; |
13263 | } | |
f1c79df3 | 13264 | |
df0e9248 CW |
13265 | void intel_connector_attach_encoder(struct intel_connector *connector, |
13266 | struct intel_encoder *encoder) | |
13267 | { | |
13268 | connector->encoder = encoder; | |
13269 | drm_mode_connector_attach_encoder(&connector->base, | |
13270 | &encoder->base); | |
79e53945 | 13271 | } |
28d52043 DA |
13272 | |
13273 | /* | |
13274 | * set vga decode state - true == enable VGA decode | |
13275 | */ | |
13276 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
13277 | { | |
13278 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 13279 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
13280 | u16 gmch_ctrl; |
13281 | ||
75fa041d CW |
13282 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
13283 | DRM_ERROR("failed to read control word\n"); | |
13284 | return -EIO; | |
13285 | } | |
13286 | ||
c0cc8a55 CW |
13287 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
13288 | return 0; | |
13289 | ||
28d52043 DA |
13290 | if (state) |
13291 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
13292 | else | |
13293 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
13294 | |
13295 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
13296 | DRM_ERROR("failed to write control word\n"); | |
13297 | return -EIO; | |
13298 | } | |
13299 | ||
28d52043 DA |
13300 | return 0; |
13301 | } | |
c4a1d9e4 | 13302 | |
c4a1d9e4 | 13303 | struct intel_display_error_state { |
ff57f1b0 PZ |
13304 | |
13305 | u32 power_well_driver; | |
13306 | ||
63b66e5b CW |
13307 | int num_transcoders; |
13308 | ||
c4a1d9e4 CW |
13309 | struct intel_cursor_error_state { |
13310 | u32 control; | |
13311 | u32 position; | |
13312 | u32 base; | |
13313 | u32 size; | |
52331309 | 13314 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
13315 | |
13316 | struct intel_pipe_error_state { | |
ddf9c536 | 13317 | bool power_domain_on; |
c4a1d9e4 | 13318 | u32 source; |
f301b1e1 | 13319 | u32 stat; |
52331309 | 13320 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
13321 | |
13322 | struct intel_plane_error_state { | |
13323 | u32 control; | |
13324 | u32 stride; | |
13325 | u32 size; | |
13326 | u32 pos; | |
13327 | u32 addr; | |
13328 | u32 surface; | |
13329 | u32 tile_offset; | |
52331309 | 13330 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
13331 | |
13332 | struct intel_transcoder_error_state { | |
ddf9c536 | 13333 | bool power_domain_on; |
63b66e5b CW |
13334 | enum transcoder cpu_transcoder; |
13335 | ||
13336 | u32 conf; | |
13337 | ||
13338 | u32 htotal; | |
13339 | u32 hblank; | |
13340 | u32 hsync; | |
13341 | u32 vtotal; | |
13342 | u32 vblank; | |
13343 | u32 vsync; | |
13344 | } transcoder[4]; | |
c4a1d9e4 CW |
13345 | }; |
13346 | ||
13347 | struct intel_display_error_state * | |
13348 | intel_display_capture_error_state(struct drm_device *dev) | |
13349 | { | |
fbee40df | 13350 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 | 13351 | struct intel_display_error_state *error; |
63b66e5b CW |
13352 | int transcoders[] = { |
13353 | TRANSCODER_A, | |
13354 | TRANSCODER_B, | |
13355 | TRANSCODER_C, | |
13356 | TRANSCODER_EDP, | |
13357 | }; | |
c4a1d9e4 CW |
13358 | int i; |
13359 | ||
63b66e5b CW |
13360 | if (INTEL_INFO(dev)->num_pipes == 0) |
13361 | return NULL; | |
13362 | ||
9d1cb914 | 13363 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
13364 | if (error == NULL) |
13365 | return NULL; | |
13366 | ||
190be112 | 13367 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
13368 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
13369 | ||
52331309 | 13370 | for_each_pipe(i) { |
ddf9c536 | 13371 | error->pipe[i].power_domain_on = |
bfafe93a ID |
13372 | intel_display_power_enabled_unlocked(dev_priv, |
13373 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 13374 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
13375 | continue; |
13376 | ||
5efb3e28 VS |
13377 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
13378 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
13379 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
13380 | |
13381 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
13382 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 13383 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 13384 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
13385 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
13386 | } | |
ca291363 PZ |
13387 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
13388 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
13389 | if (INTEL_INFO(dev)->gen >= 4) { |
13390 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
13391 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
13392 | } | |
13393 | ||
c4a1d9e4 | 13394 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 13395 | |
3abfce77 | 13396 | if (HAS_GMCH_DISPLAY(dev)) |
f301b1e1 | 13397 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
13398 | } |
13399 | ||
13400 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
13401 | if (HAS_DDI(dev_priv->dev)) | |
13402 | error->num_transcoders++; /* Account for eDP. */ | |
13403 | ||
13404 | for (i = 0; i < error->num_transcoders; i++) { | |
13405 | enum transcoder cpu_transcoder = transcoders[i]; | |
13406 | ||
ddf9c536 | 13407 | error->transcoder[i].power_domain_on = |
bfafe93a | 13408 | intel_display_power_enabled_unlocked(dev_priv, |
38cc1daf | 13409 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 13410 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
13411 | continue; |
13412 | ||
63b66e5b CW |
13413 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
13414 | ||
13415 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
13416 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
13417 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
13418 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
13419 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
13420 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
13421 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
13422 | } |
13423 | ||
13424 | return error; | |
13425 | } | |
13426 | ||
edc3d884 MK |
13427 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
13428 | ||
c4a1d9e4 | 13429 | void |
edc3d884 | 13430 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
13431 | struct drm_device *dev, |
13432 | struct intel_display_error_state *error) | |
13433 | { | |
13434 | int i; | |
13435 | ||
63b66e5b CW |
13436 | if (!error) |
13437 | return; | |
13438 | ||
edc3d884 | 13439 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 13440 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 13441 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 13442 | error->power_well_driver); |
52331309 | 13443 | for_each_pipe(i) { |
edc3d884 | 13444 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 ID |
13445 | err_printf(m, " Power: %s\n", |
13446 | error->pipe[i].power_domain_on ? "on" : "off"); | |
edc3d884 | 13447 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 13448 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
13449 | |
13450 | err_printf(m, "Plane [%d]:\n", i); | |
13451 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
13452 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 13453 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
13454 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
13455 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 13456 | } |
4b71a570 | 13457 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 13458 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 13459 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
13460 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
13461 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
13462 | } |
13463 | ||
edc3d884 MK |
13464 | err_printf(m, "Cursor [%d]:\n", i); |
13465 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
13466 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
13467 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 13468 | } |
63b66e5b CW |
13469 | |
13470 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 13471 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b | 13472 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 ID |
13473 | err_printf(m, " Power: %s\n", |
13474 | error->transcoder[i].power_domain_on ? "on" : "off"); | |
63b66e5b CW |
13475 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
13476 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
13477 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
13478 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
13479 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
13480 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
13481 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
13482 | } | |
c4a1d9e4 | 13483 | } |