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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
319c1d42 | 40 | #include <drm/drm_atomic.h> |
c196e1d6 | 41 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
42 | #include <drm/drm_dp_helper.h> |
43 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
44 | #include <drm/drm_plane_helper.h> |
45 | #include <drm/drm_rect.h> | |
c0f372b3 | 46 | #include <linux/dma_remapping.h> |
79e53945 | 47 | |
465c120c MR |
48 | /* Primary plane formats supported by all gen */ |
49 | #define COMMON_PRIMARY_FORMATS \ | |
50 | DRM_FORMAT_C8, \ | |
51 | DRM_FORMAT_RGB565, \ | |
52 | DRM_FORMAT_XRGB8888, \ | |
53 | DRM_FORMAT_ARGB8888 | |
54 | ||
55 | /* Primary plane formats for gen <= 3 */ | |
56 | static const uint32_t intel_primary_formats_gen2[] = { | |
57 | COMMON_PRIMARY_FORMATS, | |
58 | DRM_FORMAT_XRGB1555, | |
59 | DRM_FORMAT_ARGB1555, | |
60 | }; | |
61 | ||
62 | /* Primary plane formats for gen >= 4 */ | |
63 | static const uint32_t intel_primary_formats_gen4[] = { | |
64 | COMMON_PRIMARY_FORMATS, \ | |
65 | DRM_FORMAT_XBGR8888, | |
66 | DRM_FORMAT_ABGR8888, | |
67 | DRM_FORMAT_XRGB2101010, | |
68 | DRM_FORMAT_ARGB2101010, | |
69 | DRM_FORMAT_XBGR2101010, | |
70 | DRM_FORMAT_ABGR2101010, | |
71 | }; | |
72 | ||
3d7d6510 MR |
73 | /* Cursor formats */ |
74 | static const uint32_t intel_cursor_formats[] = { | |
75 | DRM_FORMAT_ARGB8888, | |
76 | }; | |
77 | ||
6b383a7f | 78 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 | 79 | |
f1f644dc | 80 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 81 | struct intel_crtc_state *pipe_config); |
18442d08 | 82 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 83 | struct intel_crtc_state *pipe_config); |
f1f644dc | 84 | |
e7457a9a | 85 | static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
83a57153 ACO |
86 | int x, int y, struct drm_framebuffer *old_fb, |
87 | struct drm_atomic_state *state); | |
eb1bfe80 JB |
88 | static int intel_framebuffer_init(struct drm_device *dev, |
89 | struct intel_framebuffer *ifb, | |
90 | struct drm_mode_fb_cmd2 *mode_cmd, | |
91 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
92 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
93 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
29407aab | 94 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
95 | struct intel_link_m_n *m_n, |
96 | struct intel_link_m_n *m2_n2); | |
29407aab | 97 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 DV |
98 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
99 | static void intel_set_pipe_csc(struct drm_crtc *crtc); | |
d288f65f | 100 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 101 | const struct intel_crtc_state *pipe_config); |
d288f65f | 102 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 103 | const struct intel_crtc_state *pipe_config); |
ea2c67bb MR |
104 | static void intel_begin_crtc_commit(struct drm_crtc *crtc); |
105 | static void intel_finish_crtc_commit(struct drm_crtc *crtc); | |
549e2bfb CK |
106 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
107 | struct intel_crtc_state *crtc_state); | |
e7457a9a | 108 | |
0e32b39c DA |
109 | static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe) |
110 | { | |
111 | if (!connector->mst_port) | |
112 | return connector->encoder; | |
113 | else | |
114 | return &connector->mst_port->mst_encoders[pipe]->base; | |
115 | } | |
116 | ||
79e53945 | 117 | typedef struct { |
0206e353 | 118 | int min, max; |
79e53945 JB |
119 | } intel_range_t; |
120 | ||
121 | typedef struct { | |
0206e353 AJ |
122 | int dot_limit; |
123 | int p2_slow, p2_fast; | |
79e53945 JB |
124 | } intel_p2_t; |
125 | ||
d4906093 ML |
126 | typedef struct intel_limit intel_limit_t; |
127 | struct intel_limit { | |
0206e353 AJ |
128 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
129 | intel_p2_t p2; | |
d4906093 | 130 | }; |
79e53945 | 131 | |
d2acd215 DV |
132 | int |
133 | intel_pch_rawclk(struct drm_device *dev) | |
134 | { | |
135 | struct drm_i915_private *dev_priv = dev->dev_private; | |
136 | ||
137 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
138 | ||
139 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
140 | } | |
141 | ||
021357ac CW |
142 | static inline u32 /* units of 100MHz */ |
143 | intel_fdi_link_freq(struct drm_device *dev) | |
144 | { | |
8b99e68c CW |
145 | if (IS_GEN5(dev)) { |
146 | struct drm_i915_private *dev_priv = dev->dev_private; | |
147 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
148 | } else | |
149 | return 27; | |
021357ac CW |
150 | } |
151 | ||
5d536e28 | 152 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 153 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 154 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 155 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
156 | .m = { .min = 96, .max = 140 }, |
157 | .m1 = { .min = 18, .max = 26 }, | |
158 | .m2 = { .min = 6, .max = 16 }, | |
159 | .p = { .min = 4, .max = 128 }, | |
160 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
161 | .p2 = { .dot_limit = 165000, |
162 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
163 | }; |
164 | ||
5d536e28 DV |
165 | static const intel_limit_t intel_limits_i8xx_dvo = { |
166 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 167 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 168 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
169 | .m = { .min = 96, .max = 140 }, |
170 | .m1 = { .min = 18, .max = 26 }, | |
171 | .m2 = { .min = 6, .max = 16 }, | |
172 | .p = { .min = 4, .max = 128 }, | |
173 | .p1 = { .min = 2, .max = 33 }, | |
174 | .p2 = { .dot_limit = 165000, | |
175 | .p2_slow = 4, .p2_fast = 4 }, | |
176 | }; | |
177 | ||
e4b36699 | 178 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 179 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 180 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 181 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
182 | .m = { .min = 96, .max = 140 }, |
183 | .m1 = { .min = 18, .max = 26 }, | |
184 | .m2 = { .min = 6, .max = 16 }, | |
185 | .p = { .min = 4, .max = 128 }, | |
186 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
187 | .p2 = { .dot_limit = 165000, |
188 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 189 | }; |
273e27ca | 190 | |
e4b36699 | 191 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
192 | .dot = { .min = 20000, .max = 400000 }, |
193 | .vco = { .min = 1400000, .max = 2800000 }, | |
194 | .n = { .min = 1, .max = 6 }, | |
195 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
196 | .m1 = { .min = 8, .max = 18 }, |
197 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
198 | .p = { .min = 5, .max = 80 }, |
199 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
200 | .p2 = { .dot_limit = 200000, |
201 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
202 | }; |
203 | ||
204 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
205 | .dot = { .min = 20000, .max = 400000 }, |
206 | .vco = { .min = 1400000, .max = 2800000 }, | |
207 | .n = { .min = 1, .max = 6 }, | |
208 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
209 | .m1 = { .min = 8, .max = 18 }, |
210 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
211 | .p = { .min = 7, .max = 98 }, |
212 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
213 | .p2 = { .dot_limit = 112000, |
214 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
215 | }; |
216 | ||
273e27ca | 217 | |
e4b36699 | 218 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
219 | .dot = { .min = 25000, .max = 270000 }, |
220 | .vco = { .min = 1750000, .max = 3500000}, | |
221 | .n = { .min = 1, .max = 4 }, | |
222 | .m = { .min = 104, .max = 138 }, | |
223 | .m1 = { .min = 17, .max = 23 }, | |
224 | .m2 = { .min = 5, .max = 11 }, | |
225 | .p = { .min = 10, .max = 30 }, | |
226 | .p1 = { .min = 1, .max = 3}, | |
227 | .p2 = { .dot_limit = 270000, | |
228 | .p2_slow = 10, | |
229 | .p2_fast = 10 | |
044c7c41 | 230 | }, |
e4b36699 KP |
231 | }; |
232 | ||
233 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
234 | .dot = { .min = 22000, .max = 400000 }, |
235 | .vco = { .min = 1750000, .max = 3500000}, | |
236 | .n = { .min = 1, .max = 4 }, | |
237 | .m = { .min = 104, .max = 138 }, | |
238 | .m1 = { .min = 16, .max = 23 }, | |
239 | .m2 = { .min = 5, .max = 11 }, | |
240 | .p = { .min = 5, .max = 80 }, | |
241 | .p1 = { .min = 1, .max = 8}, | |
242 | .p2 = { .dot_limit = 165000, | |
243 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
244 | }; |
245 | ||
246 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
247 | .dot = { .min = 20000, .max = 115000 }, |
248 | .vco = { .min = 1750000, .max = 3500000 }, | |
249 | .n = { .min = 1, .max = 3 }, | |
250 | .m = { .min = 104, .max = 138 }, | |
251 | .m1 = { .min = 17, .max = 23 }, | |
252 | .m2 = { .min = 5, .max = 11 }, | |
253 | .p = { .min = 28, .max = 112 }, | |
254 | .p1 = { .min = 2, .max = 8 }, | |
255 | .p2 = { .dot_limit = 0, | |
256 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 257 | }, |
e4b36699 KP |
258 | }; |
259 | ||
260 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
261 | .dot = { .min = 80000, .max = 224000 }, |
262 | .vco = { .min = 1750000, .max = 3500000 }, | |
263 | .n = { .min = 1, .max = 3 }, | |
264 | .m = { .min = 104, .max = 138 }, | |
265 | .m1 = { .min = 17, .max = 23 }, | |
266 | .m2 = { .min = 5, .max = 11 }, | |
267 | .p = { .min = 14, .max = 42 }, | |
268 | .p1 = { .min = 2, .max = 6 }, | |
269 | .p2 = { .dot_limit = 0, | |
270 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 271 | }, |
e4b36699 KP |
272 | }; |
273 | ||
f2b115e6 | 274 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
275 | .dot = { .min = 20000, .max = 400000}, |
276 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 277 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
278 | .n = { .min = 3, .max = 6 }, |
279 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 280 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
281 | .m1 = { .min = 0, .max = 0 }, |
282 | .m2 = { .min = 0, .max = 254 }, | |
283 | .p = { .min = 5, .max = 80 }, | |
284 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
285 | .p2 = { .dot_limit = 200000, |
286 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
287 | }; |
288 | ||
f2b115e6 | 289 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
290 | .dot = { .min = 20000, .max = 400000 }, |
291 | .vco = { .min = 1700000, .max = 3500000 }, | |
292 | .n = { .min = 3, .max = 6 }, | |
293 | .m = { .min = 2, .max = 256 }, | |
294 | .m1 = { .min = 0, .max = 0 }, | |
295 | .m2 = { .min = 0, .max = 254 }, | |
296 | .p = { .min = 7, .max = 112 }, | |
297 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
298 | .p2 = { .dot_limit = 112000, |
299 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
300 | }; |
301 | ||
273e27ca EA |
302 | /* Ironlake / Sandybridge |
303 | * | |
304 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
305 | * the range value for them is (actual_value - 2). | |
306 | */ | |
b91ad0ec | 307 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
308 | .dot = { .min = 25000, .max = 350000 }, |
309 | .vco = { .min = 1760000, .max = 3510000 }, | |
310 | .n = { .min = 1, .max = 5 }, | |
311 | .m = { .min = 79, .max = 127 }, | |
312 | .m1 = { .min = 12, .max = 22 }, | |
313 | .m2 = { .min = 5, .max = 9 }, | |
314 | .p = { .min = 5, .max = 80 }, | |
315 | .p1 = { .min = 1, .max = 8 }, | |
316 | .p2 = { .dot_limit = 225000, | |
317 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
318 | }; |
319 | ||
b91ad0ec | 320 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
321 | .dot = { .min = 25000, .max = 350000 }, |
322 | .vco = { .min = 1760000, .max = 3510000 }, | |
323 | .n = { .min = 1, .max = 3 }, | |
324 | .m = { .min = 79, .max = 118 }, | |
325 | .m1 = { .min = 12, .max = 22 }, | |
326 | .m2 = { .min = 5, .max = 9 }, | |
327 | .p = { .min = 28, .max = 112 }, | |
328 | .p1 = { .min = 2, .max = 8 }, | |
329 | .p2 = { .dot_limit = 225000, | |
330 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
331 | }; |
332 | ||
333 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
334 | .dot = { .min = 25000, .max = 350000 }, |
335 | .vco = { .min = 1760000, .max = 3510000 }, | |
336 | .n = { .min = 1, .max = 3 }, | |
337 | .m = { .min = 79, .max = 127 }, | |
338 | .m1 = { .min = 12, .max = 22 }, | |
339 | .m2 = { .min = 5, .max = 9 }, | |
340 | .p = { .min = 14, .max = 56 }, | |
341 | .p1 = { .min = 2, .max = 8 }, | |
342 | .p2 = { .dot_limit = 225000, | |
343 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
344 | }; |
345 | ||
273e27ca | 346 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 347 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
348 | .dot = { .min = 25000, .max = 350000 }, |
349 | .vco = { .min = 1760000, .max = 3510000 }, | |
350 | .n = { .min = 1, .max = 2 }, | |
351 | .m = { .min = 79, .max = 126 }, | |
352 | .m1 = { .min = 12, .max = 22 }, | |
353 | .m2 = { .min = 5, .max = 9 }, | |
354 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 355 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
356 | .p2 = { .dot_limit = 225000, |
357 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
358 | }; |
359 | ||
360 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
361 | .dot = { .min = 25000, .max = 350000 }, |
362 | .vco = { .min = 1760000, .max = 3510000 }, | |
363 | .n = { .min = 1, .max = 3 }, | |
364 | .m = { .min = 79, .max = 126 }, | |
365 | .m1 = { .min = 12, .max = 22 }, | |
366 | .m2 = { .min = 5, .max = 9 }, | |
367 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 368 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
369 | .p2 = { .dot_limit = 225000, |
370 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
371 | }; |
372 | ||
dc730512 | 373 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
374 | /* |
375 | * These are the data rate limits (measured in fast clocks) | |
376 | * since those are the strictest limits we have. The fast | |
377 | * clock and actual rate limits are more relaxed, so checking | |
378 | * them would make no difference. | |
379 | */ | |
380 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 381 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 382 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
383 | .m1 = { .min = 2, .max = 3 }, |
384 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 385 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 386 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
387 | }; |
388 | ||
ef9348c8 CML |
389 | static const intel_limit_t intel_limits_chv = { |
390 | /* | |
391 | * These are the data rate limits (measured in fast clocks) | |
392 | * since those are the strictest limits we have. The fast | |
393 | * clock and actual rate limits are more relaxed, so checking | |
394 | * them would make no difference. | |
395 | */ | |
396 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 397 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
398 | .n = { .min = 1, .max = 1 }, |
399 | .m1 = { .min = 2, .max = 2 }, | |
400 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
401 | .p1 = { .min = 2, .max = 4 }, | |
402 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
403 | }; | |
404 | ||
6b4bf1c4 VS |
405 | static void vlv_clock(int refclk, intel_clock_t *clock) |
406 | { | |
407 | clock->m = clock->m1 * clock->m2; | |
408 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
409 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
410 | return; | |
fb03ac01 VS |
411 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
412 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
6b4bf1c4 VS |
413 | } |
414 | ||
e0638cdf PZ |
415 | /** |
416 | * Returns whether any output on the specified pipe is of the specified type | |
417 | */ | |
4093561b | 418 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) |
e0638cdf | 419 | { |
409ee761 | 420 | struct drm_device *dev = crtc->base.dev; |
e0638cdf PZ |
421 | struct intel_encoder *encoder; |
422 | ||
409ee761 | 423 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
e0638cdf PZ |
424 | if (encoder->type == type) |
425 | return true; | |
426 | ||
427 | return false; | |
428 | } | |
429 | ||
d0737e1d ACO |
430 | /** |
431 | * Returns whether any output on the specified pipe will have the specified | |
432 | * type after a staged modeset is complete, i.e., the same as | |
433 | * intel_pipe_has_type() but looking at encoder->new_crtc instead of | |
434 | * encoder->crtc. | |
435 | */ | |
a93e255f ACO |
436 | static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state, |
437 | int type) | |
d0737e1d | 438 | { |
a93e255f ACO |
439 | struct drm_atomic_state *state = crtc_state->base.state; |
440 | struct drm_connector_state *connector_state; | |
d0737e1d | 441 | struct intel_encoder *encoder; |
a93e255f ACO |
442 | int i, num_connectors = 0; |
443 | ||
444 | for (i = 0; i < state->num_connector; i++) { | |
445 | if (!state->connectors[i]) | |
446 | continue; | |
447 | ||
448 | connector_state = state->connector_states[i]; | |
449 | if (connector_state->crtc != crtc_state->base.crtc) | |
450 | continue; | |
451 | ||
452 | num_connectors++; | |
d0737e1d | 453 | |
a93e255f ACO |
454 | encoder = to_intel_encoder(connector_state->best_encoder); |
455 | if (encoder->type == type) | |
d0737e1d | 456 | return true; |
a93e255f ACO |
457 | } |
458 | ||
459 | WARN_ON(num_connectors == 0); | |
d0737e1d ACO |
460 | |
461 | return false; | |
462 | } | |
463 | ||
a93e255f ACO |
464 | static const intel_limit_t * |
465 | intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk) | |
2c07245f | 466 | { |
a93e255f | 467 | struct drm_device *dev = crtc_state->base.crtc->dev; |
2c07245f | 468 | const intel_limit_t *limit; |
b91ad0ec | 469 | |
a93e255f | 470 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 471 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 472 | if (refclk == 100000) |
b91ad0ec ZW |
473 | limit = &intel_limits_ironlake_dual_lvds_100m; |
474 | else | |
475 | limit = &intel_limits_ironlake_dual_lvds; | |
476 | } else { | |
1b894b59 | 477 | if (refclk == 100000) |
b91ad0ec ZW |
478 | limit = &intel_limits_ironlake_single_lvds_100m; |
479 | else | |
480 | limit = &intel_limits_ironlake_single_lvds; | |
481 | } | |
c6bb3538 | 482 | } else |
b91ad0ec | 483 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
484 | |
485 | return limit; | |
486 | } | |
487 | ||
a93e255f ACO |
488 | static const intel_limit_t * |
489 | intel_g4x_limit(struct intel_crtc_state *crtc_state) | |
044c7c41 | 490 | { |
a93e255f | 491 | struct drm_device *dev = crtc_state->base.crtc->dev; |
044c7c41 ML |
492 | const intel_limit_t *limit; |
493 | ||
a93e255f | 494 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 495 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 496 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 497 | else |
e4b36699 | 498 | limit = &intel_limits_g4x_single_channel_lvds; |
a93e255f ACO |
499 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) || |
500 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 501 | limit = &intel_limits_g4x_hdmi; |
a93e255f | 502 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 503 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 504 | } else /* The option is for other outputs */ |
e4b36699 | 505 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
506 | |
507 | return limit; | |
508 | } | |
509 | ||
a93e255f ACO |
510 | static const intel_limit_t * |
511 | intel_limit(struct intel_crtc_state *crtc_state, int refclk) | |
79e53945 | 512 | { |
a93e255f | 513 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 JB |
514 | const intel_limit_t *limit; |
515 | ||
bad720ff | 516 | if (HAS_PCH_SPLIT(dev)) |
a93e255f | 517 | limit = intel_ironlake_limit(crtc_state, refclk); |
2c07245f | 518 | else if (IS_G4X(dev)) { |
a93e255f | 519 | limit = intel_g4x_limit(crtc_state); |
f2b115e6 | 520 | } else if (IS_PINEVIEW(dev)) { |
a93e255f | 521 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 522 | limit = &intel_limits_pineview_lvds; |
2177832f | 523 | else |
f2b115e6 | 524 | limit = &intel_limits_pineview_sdvo; |
ef9348c8 CML |
525 | } else if (IS_CHERRYVIEW(dev)) { |
526 | limit = &intel_limits_chv; | |
a0c4da24 | 527 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 528 | limit = &intel_limits_vlv; |
a6c45cf0 | 529 | } else if (!IS_GEN2(dev)) { |
a93e255f | 530 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a6c45cf0 CW |
531 | limit = &intel_limits_i9xx_lvds; |
532 | else | |
533 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 | 534 | } else { |
a93e255f | 535 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
e4b36699 | 536 | limit = &intel_limits_i8xx_lvds; |
a93e255f | 537 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
e4b36699 | 538 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
539 | else |
540 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
541 | } |
542 | return limit; | |
543 | } | |
544 | ||
f2b115e6 AJ |
545 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
546 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 547 | { |
2177832f SL |
548 | clock->m = clock->m2 + 2; |
549 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
550 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
551 | return; | |
fb03ac01 VS |
552 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
553 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
2177832f SL |
554 | } |
555 | ||
7429e9d4 DV |
556 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
557 | { | |
558 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
559 | } | |
560 | ||
ac58c3f0 | 561 | static void i9xx_clock(int refclk, intel_clock_t *clock) |
2177832f | 562 | { |
7429e9d4 | 563 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 564 | clock->p = clock->p1 * clock->p2; |
ed5ca77e VS |
565 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
566 | return; | |
fb03ac01 VS |
567 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
568 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
79e53945 JB |
569 | } |
570 | ||
ef9348c8 CML |
571 | static void chv_clock(int refclk, intel_clock_t *clock) |
572 | { | |
573 | clock->m = clock->m1 * clock->m2; | |
574 | clock->p = clock->p1 * clock->p2; | |
575 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
576 | return; | |
577 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, | |
578 | clock->n << 22); | |
579 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
580 | } | |
581 | ||
7c04d1d9 | 582 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
583 | /** |
584 | * Returns whether the given set of divisors are valid for a given refclk with | |
585 | * the given connectors. | |
586 | */ | |
587 | ||
1b894b59 CW |
588 | static bool intel_PLL_is_valid(struct drm_device *dev, |
589 | const intel_limit_t *limit, | |
590 | const intel_clock_t *clock) | |
79e53945 | 591 | { |
f01b7962 VS |
592 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
593 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 594 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 595 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 596 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 597 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 598 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 599 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 VS |
600 | |
601 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev)) | |
602 | if (clock->m1 <= clock->m2) | |
603 | INTELPllInvalid("m1 <= m2\n"); | |
604 | ||
605 | if (!IS_VALLEYVIEW(dev)) { | |
606 | if (clock->p < limit->p.min || limit->p.max < clock->p) | |
607 | INTELPllInvalid("p out of range\n"); | |
608 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
609 | INTELPllInvalid("m out of range\n"); | |
610 | } | |
611 | ||
79e53945 | 612 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 613 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
614 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
615 | * connector, etc., rather than just a single range. | |
616 | */ | |
617 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 618 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
619 | |
620 | return true; | |
621 | } | |
622 | ||
d4906093 | 623 | static bool |
a93e255f ACO |
624 | i9xx_find_best_dpll(const intel_limit_t *limit, |
625 | struct intel_crtc_state *crtc_state, | |
cec2f356 SP |
626 | int target, int refclk, intel_clock_t *match_clock, |
627 | intel_clock_t *best_clock) | |
79e53945 | 628 | { |
a93e255f | 629 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 630 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 631 | intel_clock_t clock; |
79e53945 JB |
632 | int err = target; |
633 | ||
a93e255f | 634 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 635 | /* |
a210b028 DV |
636 | * For LVDS just rely on its current settings for dual-channel. |
637 | * We haven't figured out how to reliably set up different | |
638 | * single/dual channel state, if we even can. | |
79e53945 | 639 | */ |
1974cad0 | 640 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
641 | clock.p2 = limit->p2.p2_fast; |
642 | else | |
643 | clock.p2 = limit->p2.p2_slow; | |
644 | } else { | |
645 | if (target < limit->p2.dot_limit) | |
646 | clock.p2 = limit->p2.p2_slow; | |
647 | else | |
648 | clock.p2 = limit->p2.p2_fast; | |
649 | } | |
650 | ||
0206e353 | 651 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 652 | |
42158660 ZY |
653 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
654 | clock.m1++) { | |
655 | for (clock.m2 = limit->m2.min; | |
656 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 657 | if (clock.m2 >= clock.m1) |
42158660 ZY |
658 | break; |
659 | for (clock.n = limit->n.min; | |
660 | clock.n <= limit->n.max; clock.n++) { | |
661 | for (clock.p1 = limit->p1.min; | |
662 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
663 | int this_err; |
664 | ||
ac58c3f0 DV |
665 | i9xx_clock(refclk, &clock); |
666 | if (!intel_PLL_is_valid(dev, limit, | |
667 | &clock)) | |
668 | continue; | |
669 | if (match_clock && | |
670 | clock.p != match_clock->p) | |
671 | continue; | |
672 | ||
673 | this_err = abs(clock.dot - target); | |
674 | if (this_err < err) { | |
675 | *best_clock = clock; | |
676 | err = this_err; | |
677 | } | |
678 | } | |
679 | } | |
680 | } | |
681 | } | |
682 | ||
683 | return (err != target); | |
684 | } | |
685 | ||
686 | static bool | |
a93e255f ACO |
687 | pnv_find_best_dpll(const intel_limit_t *limit, |
688 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
689 | int target, int refclk, intel_clock_t *match_clock, |
690 | intel_clock_t *best_clock) | |
79e53945 | 691 | { |
a93e255f | 692 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 693 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 694 | intel_clock_t clock; |
79e53945 JB |
695 | int err = target; |
696 | ||
a93e255f | 697 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 698 | /* |
a210b028 DV |
699 | * For LVDS just rely on its current settings for dual-channel. |
700 | * We haven't figured out how to reliably set up different | |
701 | * single/dual channel state, if we even can. | |
79e53945 | 702 | */ |
1974cad0 | 703 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
704 | clock.p2 = limit->p2.p2_fast; |
705 | else | |
706 | clock.p2 = limit->p2.p2_slow; | |
707 | } else { | |
708 | if (target < limit->p2.dot_limit) | |
709 | clock.p2 = limit->p2.p2_slow; | |
710 | else | |
711 | clock.p2 = limit->p2.p2_fast; | |
712 | } | |
713 | ||
0206e353 | 714 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 715 | |
42158660 ZY |
716 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
717 | clock.m1++) { | |
718 | for (clock.m2 = limit->m2.min; | |
719 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
720 | for (clock.n = limit->n.min; |
721 | clock.n <= limit->n.max; clock.n++) { | |
722 | for (clock.p1 = limit->p1.min; | |
723 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
724 | int this_err; |
725 | ||
ac58c3f0 | 726 | pineview_clock(refclk, &clock); |
1b894b59 CW |
727 | if (!intel_PLL_is_valid(dev, limit, |
728 | &clock)) | |
79e53945 | 729 | continue; |
cec2f356 SP |
730 | if (match_clock && |
731 | clock.p != match_clock->p) | |
732 | continue; | |
79e53945 JB |
733 | |
734 | this_err = abs(clock.dot - target); | |
735 | if (this_err < err) { | |
736 | *best_clock = clock; | |
737 | err = this_err; | |
738 | } | |
739 | } | |
740 | } | |
741 | } | |
742 | } | |
743 | ||
744 | return (err != target); | |
745 | } | |
746 | ||
d4906093 | 747 | static bool |
a93e255f ACO |
748 | g4x_find_best_dpll(const intel_limit_t *limit, |
749 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
750 | int target, int refclk, intel_clock_t *match_clock, |
751 | intel_clock_t *best_clock) | |
d4906093 | 752 | { |
a93e255f | 753 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 754 | struct drm_device *dev = crtc->base.dev; |
d4906093 ML |
755 | intel_clock_t clock; |
756 | int max_n; | |
757 | bool found; | |
6ba770dc AJ |
758 | /* approximately equals target * 0.00585 */ |
759 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
760 | found = false; |
761 | ||
a93e255f | 762 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 763 | if (intel_is_dual_link_lvds(dev)) |
d4906093 ML |
764 | clock.p2 = limit->p2.p2_fast; |
765 | else | |
766 | clock.p2 = limit->p2.p2_slow; | |
767 | } else { | |
768 | if (target < limit->p2.dot_limit) | |
769 | clock.p2 = limit->p2.p2_slow; | |
770 | else | |
771 | clock.p2 = limit->p2.p2_fast; | |
772 | } | |
773 | ||
774 | memset(best_clock, 0, sizeof(*best_clock)); | |
775 | max_n = limit->n.max; | |
f77f13e2 | 776 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 777 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 778 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
779 | for (clock.m1 = limit->m1.max; |
780 | clock.m1 >= limit->m1.min; clock.m1--) { | |
781 | for (clock.m2 = limit->m2.max; | |
782 | clock.m2 >= limit->m2.min; clock.m2--) { | |
783 | for (clock.p1 = limit->p1.max; | |
784 | clock.p1 >= limit->p1.min; clock.p1--) { | |
785 | int this_err; | |
786 | ||
ac58c3f0 | 787 | i9xx_clock(refclk, &clock); |
1b894b59 CW |
788 | if (!intel_PLL_is_valid(dev, limit, |
789 | &clock)) | |
d4906093 | 790 | continue; |
1b894b59 CW |
791 | |
792 | this_err = abs(clock.dot - target); | |
d4906093 ML |
793 | if (this_err < err_most) { |
794 | *best_clock = clock; | |
795 | err_most = this_err; | |
796 | max_n = clock.n; | |
797 | found = true; | |
798 | } | |
799 | } | |
800 | } | |
801 | } | |
802 | } | |
2c07245f ZW |
803 | return found; |
804 | } | |
805 | ||
d5dd62bd ID |
806 | /* |
807 | * Check if the calculated PLL configuration is more optimal compared to the | |
808 | * best configuration and error found so far. Return the calculated error. | |
809 | */ | |
810 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
811 | const intel_clock_t *calculated_clock, | |
812 | const intel_clock_t *best_clock, | |
813 | unsigned int best_error_ppm, | |
814 | unsigned int *error_ppm) | |
815 | { | |
9ca3ba01 ID |
816 | /* |
817 | * For CHV ignore the error and consider only the P value. | |
818 | * Prefer a bigger P value based on HW requirements. | |
819 | */ | |
820 | if (IS_CHERRYVIEW(dev)) { | |
821 | *error_ppm = 0; | |
822 | ||
823 | return calculated_clock->p > best_clock->p; | |
824 | } | |
825 | ||
24be4e46 ID |
826 | if (WARN_ON_ONCE(!target_freq)) |
827 | return false; | |
828 | ||
d5dd62bd ID |
829 | *error_ppm = div_u64(1000000ULL * |
830 | abs(target_freq - calculated_clock->dot), | |
831 | target_freq); | |
832 | /* | |
833 | * Prefer a better P value over a better (smaller) error if the error | |
834 | * is small. Ensure this preference for future configurations too by | |
835 | * setting the error to 0. | |
836 | */ | |
837 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
838 | *error_ppm = 0; | |
839 | ||
840 | return true; | |
841 | } | |
842 | ||
843 | return *error_ppm + 10 < best_error_ppm; | |
844 | } | |
845 | ||
a0c4da24 | 846 | static bool |
a93e255f ACO |
847 | vlv_find_best_dpll(const intel_limit_t *limit, |
848 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
849 | int target, int refclk, intel_clock_t *match_clock, |
850 | intel_clock_t *best_clock) | |
a0c4da24 | 851 | { |
a93e255f | 852 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 853 | struct drm_device *dev = crtc->base.dev; |
6b4bf1c4 | 854 | intel_clock_t clock; |
69e4f900 | 855 | unsigned int bestppm = 1000000; |
27e639bf VS |
856 | /* min update 19.2 MHz */ |
857 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 858 | bool found = false; |
a0c4da24 | 859 | |
6b4bf1c4 VS |
860 | target *= 5; /* fast clock */ |
861 | ||
862 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
863 | |
864 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 865 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 866 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 867 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 868 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 869 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 870 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 871 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 872 | unsigned int ppm; |
69e4f900 | 873 | |
6b4bf1c4 VS |
874 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
875 | refclk * clock.m1); | |
876 | ||
877 | vlv_clock(refclk, &clock); | |
43b0ac53 | 878 | |
f01b7962 VS |
879 | if (!intel_PLL_is_valid(dev, limit, |
880 | &clock)) | |
43b0ac53 VS |
881 | continue; |
882 | ||
d5dd62bd ID |
883 | if (!vlv_PLL_is_optimal(dev, target, |
884 | &clock, | |
885 | best_clock, | |
886 | bestppm, &ppm)) | |
887 | continue; | |
6b4bf1c4 | 888 | |
d5dd62bd ID |
889 | *best_clock = clock; |
890 | bestppm = ppm; | |
891 | found = true; | |
a0c4da24 JB |
892 | } |
893 | } | |
894 | } | |
895 | } | |
a0c4da24 | 896 | |
49e497ef | 897 | return found; |
a0c4da24 | 898 | } |
a4fc5ed6 | 899 | |
ef9348c8 | 900 | static bool |
a93e255f ACO |
901 | chv_find_best_dpll(const intel_limit_t *limit, |
902 | struct intel_crtc_state *crtc_state, | |
ef9348c8 CML |
903 | int target, int refclk, intel_clock_t *match_clock, |
904 | intel_clock_t *best_clock) | |
905 | { | |
a93e255f | 906 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 907 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 908 | unsigned int best_error_ppm; |
ef9348c8 CML |
909 | intel_clock_t clock; |
910 | uint64_t m2; | |
911 | int found = false; | |
912 | ||
913 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 914 | best_error_ppm = 1000000; |
ef9348c8 CML |
915 | |
916 | /* | |
917 | * Based on hardware doc, the n always set to 1, and m1 always | |
918 | * set to 2. If requires to support 200Mhz refclk, we need to | |
919 | * revisit this because n may not 1 anymore. | |
920 | */ | |
921 | clock.n = 1, clock.m1 = 2; | |
922 | target *= 5; /* fast clock */ | |
923 | ||
924 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
925 | for (clock.p2 = limit->p2.p2_fast; | |
926 | clock.p2 >= limit->p2.p2_slow; | |
927 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 928 | unsigned int error_ppm; |
ef9348c8 CML |
929 | |
930 | clock.p = clock.p1 * clock.p2; | |
931 | ||
932 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
933 | clock.n) << 22, refclk * clock.m1); | |
934 | ||
935 | if (m2 > INT_MAX/clock.m1) | |
936 | continue; | |
937 | ||
938 | clock.m2 = m2; | |
939 | ||
940 | chv_clock(refclk, &clock); | |
941 | ||
942 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
943 | continue; | |
944 | ||
9ca3ba01 ID |
945 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
946 | best_error_ppm, &error_ppm)) | |
947 | continue; | |
948 | ||
949 | *best_clock = clock; | |
950 | best_error_ppm = error_ppm; | |
951 | found = true; | |
ef9348c8 CML |
952 | } |
953 | } | |
954 | ||
955 | return found; | |
956 | } | |
957 | ||
20ddf665 VS |
958 | bool intel_crtc_active(struct drm_crtc *crtc) |
959 | { | |
960 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
961 | ||
962 | /* Be paranoid as we can arrive here with only partial | |
963 | * state retrieved from the hardware during setup. | |
964 | * | |
241bfc38 | 965 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
966 | * as Haswell has gained clock readout/fastboot support. |
967 | * | |
66e514c1 | 968 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 969 | * properly reconstruct framebuffers. |
c3d1f436 MR |
970 | * |
971 | * FIXME: The intel_crtc->active here should be switched to | |
972 | * crtc->state->active once we have proper CRTC states wired up | |
973 | * for atomic. | |
20ddf665 | 974 | */ |
c3d1f436 | 975 | return intel_crtc->active && crtc->primary->state->fb && |
6e3c9717 | 976 | intel_crtc->config->base.adjusted_mode.crtc_clock; |
20ddf665 VS |
977 | } |
978 | ||
a5c961d1 PZ |
979 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
980 | enum pipe pipe) | |
981 | { | |
982 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
983 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
984 | ||
6e3c9717 | 985 | return intel_crtc->config->cpu_transcoder; |
a5c961d1 PZ |
986 | } |
987 | ||
fbf49ea2 VS |
988 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
989 | { | |
990 | struct drm_i915_private *dev_priv = dev->dev_private; | |
991 | u32 reg = PIPEDSL(pipe); | |
992 | u32 line1, line2; | |
993 | u32 line_mask; | |
994 | ||
995 | if (IS_GEN2(dev)) | |
996 | line_mask = DSL_LINEMASK_GEN2; | |
997 | else | |
998 | line_mask = DSL_LINEMASK_GEN3; | |
999 | ||
1000 | line1 = I915_READ(reg) & line_mask; | |
1001 | mdelay(5); | |
1002 | line2 = I915_READ(reg) & line_mask; | |
1003 | ||
1004 | return line1 == line2; | |
1005 | } | |
1006 | ||
ab7ad7f6 KP |
1007 | /* |
1008 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 1009 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
1010 | * |
1011 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1012 | * spinning on the vblank interrupt status bit, since we won't actually | |
1013 | * see an interrupt when the pipe is disabled. | |
1014 | * | |
ab7ad7f6 KP |
1015 | * On Gen4 and above: |
1016 | * wait for the pipe register state bit to turn off | |
1017 | * | |
1018 | * Otherwise: | |
1019 | * wait for the display line value to settle (it usually | |
1020 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1021 | * |
9d0498a2 | 1022 | */ |
575f7ab7 | 1023 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1024 | { |
575f7ab7 | 1025 | struct drm_device *dev = crtc->base.dev; |
9d0498a2 | 1026 | struct drm_i915_private *dev_priv = dev->dev_private; |
6e3c9717 | 1027 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1028 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 KP |
1029 | |
1030 | if (INTEL_INFO(dev)->gen >= 4) { | |
702e7a56 | 1031 | int reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1032 | |
1033 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
1034 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
1035 | 100)) | |
284637d9 | 1036 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1037 | } else { |
ab7ad7f6 | 1038 | /* Wait for the display line to settle */ |
fbf49ea2 | 1039 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 1040 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1041 | } |
79e53945 JB |
1042 | } |
1043 | ||
b0ea7d37 DL |
1044 | /* |
1045 | * ibx_digital_port_connected - is the specified port connected? | |
1046 | * @dev_priv: i915 private structure | |
1047 | * @port: the port to test | |
1048 | * | |
1049 | * Returns true if @port is connected, false otherwise. | |
1050 | */ | |
1051 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, | |
1052 | struct intel_digital_port *port) | |
1053 | { | |
1054 | u32 bit; | |
1055 | ||
c36346e3 | 1056 | if (HAS_PCH_IBX(dev_priv->dev)) { |
eba905b2 | 1057 | switch (port->port) { |
c36346e3 DL |
1058 | case PORT_B: |
1059 | bit = SDE_PORTB_HOTPLUG; | |
1060 | break; | |
1061 | case PORT_C: | |
1062 | bit = SDE_PORTC_HOTPLUG; | |
1063 | break; | |
1064 | case PORT_D: | |
1065 | bit = SDE_PORTD_HOTPLUG; | |
1066 | break; | |
1067 | default: | |
1068 | return true; | |
1069 | } | |
1070 | } else { | |
eba905b2 | 1071 | switch (port->port) { |
c36346e3 DL |
1072 | case PORT_B: |
1073 | bit = SDE_PORTB_HOTPLUG_CPT; | |
1074 | break; | |
1075 | case PORT_C: | |
1076 | bit = SDE_PORTC_HOTPLUG_CPT; | |
1077 | break; | |
1078 | case PORT_D: | |
1079 | bit = SDE_PORTD_HOTPLUG_CPT; | |
1080 | break; | |
1081 | default: | |
1082 | return true; | |
1083 | } | |
b0ea7d37 DL |
1084 | } |
1085 | ||
1086 | return I915_READ(SDEISR) & bit; | |
1087 | } | |
1088 | ||
b24e7179 JB |
1089 | static const char *state_string(bool enabled) |
1090 | { | |
1091 | return enabled ? "on" : "off"; | |
1092 | } | |
1093 | ||
1094 | /* Only for pre-ILK configs */ | |
55607e8a DV |
1095 | void assert_pll(struct drm_i915_private *dev_priv, |
1096 | enum pipe pipe, bool state) | |
b24e7179 JB |
1097 | { |
1098 | int reg; | |
1099 | u32 val; | |
1100 | bool cur_state; | |
1101 | ||
1102 | reg = DPLL(pipe); | |
1103 | val = I915_READ(reg); | |
1104 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
e2c719b7 | 1105 | I915_STATE_WARN(cur_state != state, |
b24e7179 JB |
1106 | "PLL state assertion failure (expected %s, current %s)\n", |
1107 | state_string(state), state_string(cur_state)); | |
1108 | } | |
b24e7179 | 1109 | |
23538ef1 JN |
1110 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
1111 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
1112 | { | |
1113 | u32 val; | |
1114 | bool cur_state; | |
1115 | ||
1116 | mutex_lock(&dev_priv->dpio_lock); | |
1117 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); | |
1118 | mutex_unlock(&dev_priv->dpio_lock); | |
1119 | ||
1120 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1121 | I915_STATE_WARN(cur_state != state, |
23538ef1 JN |
1122 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
1123 | state_string(state), state_string(cur_state)); | |
1124 | } | |
1125 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1126 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
1127 | ||
55607e8a | 1128 | struct intel_shared_dpll * |
e2b78267 DV |
1129 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
1130 | { | |
1131 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
1132 | ||
6e3c9717 | 1133 | if (crtc->config->shared_dpll < 0) |
e2b78267 DV |
1134 | return NULL; |
1135 | ||
6e3c9717 | 1136 | return &dev_priv->shared_dplls[crtc->config->shared_dpll]; |
e2b78267 DV |
1137 | } |
1138 | ||
040484af | 1139 | /* For ILK+ */ |
55607e8a DV |
1140 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
1141 | struct intel_shared_dpll *pll, | |
1142 | bool state) | |
040484af | 1143 | { |
040484af | 1144 | bool cur_state; |
5358901f | 1145 | struct intel_dpll_hw_state hw_state; |
040484af | 1146 | |
92b27b08 | 1147 | if (WARN (!pll, |
46edb027 | 1148 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
ee7b9f93 | 1149 | return; |
ee7b9f93 | 1150 | |
5358901f | 1151 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
e2c719b7 | 1152 | I915_STATE_WARN(cur_state != state, |
5358901f DV |
1153 | "%s assertion failure (expected %s, current %s)\n", |
1154 | pll->name, state_string(state), state_string(cur_state)); | |
040484af | 1155 | } |
040484af JB |
1156 | |
1157 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1158 | enum pipe pipe, bool state) | |
1159 | { | |
1160 | int reg; | |
1161 | u32 val; | |
1162 | bool cur_state; | |
ad80a810 PZ |
1163 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1164 | pipe); | |
040484af | 1165 | |
affa9354 PZ |
1166 | if (HAS_DDI(dev_priv->dev)) { |
1167 | /* DDI does not have a specific FDI_TX register */ | |
ad80a810 | 1168 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
bf507ef7 | 1169 | val = I915_READ(reg); |
ad80a810 | 1170 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 ED |
1171 | } else { |
1172 | reg = FDI_TX_CTL(pipe); | |
1173 | val = I915_READ(reg); | |
1174 | cur_state = !!(val & FDI_TX_ENABLE); | |
1175 | } | |
e2c719b7 | 1176 | I915_STATE_WARN(cur_state != state, |
040484af JB |
1177 | "FDI TX state assertion failure (expected %s, current %s)\n", |
1178 | state_string(state), state_string(cur_state)); | |
1179 | } | |
1180 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1181 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1182 | ||
1183 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1184 | enum pipe pipe, bool state) | |
1185 | { | |
1186 | int reg; | |
1187 | u32 val; | |
1188 | bool cur_state; | |
1189 | ||
d63fa0dc PZ |
1190 | reg = FDI_RX_CTL(pipe); |
1191 | val = I915_READ(reg); | |
1192 | cur_state = !!(val & FDI_RX_ENABLE); | |
e2c719b7 | 1193 | I915_STATE_WARN(cur_state != state, |
040484af JB |
1194 | "FDI RX state assertion failure (expected %s, current %s)\n", |
1195 | state_string(state), state_string(cur_state)); | |
1196 | } | |
1197 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1198 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1199 | ||
1200 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1201 | enum pipe pipe) | |
1202 | { | |
1203 | int reg; | |
1204 | u32 val; | |
1205 | ||
1206 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1207 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1208 | return; |
1209 | ||
bf507ef7 | 1210 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1211 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1212 | return; |
1213 | ||
040484af JB |
1214 | reg = FDI_TX_CTL(pipe); |
1215 | val = I915_READ(reg); | |
e2c719b7 | 1216 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1217 | } |
1218 | ||
55607e8a DV |
1219 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1220 | enum pipe pipe, bool state) | |
040484af JB |
1221 | { |
1222 | int reg; | |
1223 | u32 val; | |
55607e8a | 1224 | bool cur_state; |
040484af JB |
1225 | |
1226 | reg = FDI_RX_CTL(pipe); | |
1227 | val = I915_READ(reg); | |
55607e8a | 1228 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1229 | I915_STATE_WARN(cur_state != state, |
55607e8a DV |
1230 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
1231 | state_string(state), state_string(cur_state)); | |
040484af JB |
1232 | } |
1233 | ||
b680c37a DV |
1234 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1235 | enum pipe pipe) | |
ea0760cf | 1236 | { |
bedd4dba JN |
1237 | struct drm_device *dev = dev_priv->dev; |
1238 | int pp_reg; | |
ea0760cf JB |
1239 | u32 val; |
1240 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1241 | bool locked = true; |
ea0760cf | 1242 | |
bedd4dba JN |
1243 | if (WARN_ON(HAS_DDI(dev))) |
1244 | return; | |
1245 | ||
1246 | if (HAS_PCH_SPLIT(dev)) { | |
1247 | u32 port_sel; | |
1248 | ||
ea0760cf | 1249 | pp_reg = PCH_PP_CONTROL; |
bedd4dba JN |
1250 | port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; |
1251 | ||
1252 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1253 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1254 | panel_pipe = PIPE_B; | |
1255 | /* XXX: else fix for eDP */ | |
1256 | } else if (IS_VALLEYVIEW(dev)) { | |
1257 | /* presumably write lock depends on pipe, not port select */ | |
1258 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); | |
1259 | panel_pipe = pipe; | |
ea0760cf JB |
1260 | } else { |
1261 | pp_reg = PP_CONTROL; | |
bedd4dba JN |
1262 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1263 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1264 | } |
1265 | ||
1266 | val = I915_READ(pp_reg); | |
1267 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1268 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1269 | locked = false; |
1270 | ||
e2c719b7 | 1271 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1272 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1273 | pipe_name(pipe)); |
ea0760cf JB |
1274 | } |
1275 | ||
93ce0ba6 JN |
1276 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1277 | enum pipe pipe, bool state) | |
1278 | { | |
1279 | struct drm_device *dev = dev_priv->dev; | |
1280 | bool cur_state; | |
1281 | ||
d9d82081 | 1282 | if (IS_845G(dev) || IS_I865G(dev)) |
93ce0ba6 | 1283 | cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE; |
d9d82081 | 1284 | else |
5efb3e28 | 1285 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1286 | |
e2c719b7 | 1287 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 JN |
1288 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
1289 | pipe_name(pipe), state_string(state), state_string(cur_state)); | |
1290 | } | |
1291 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1292 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1293 | ||
b840d907 JB |
1294 | void assert_pipe(struct drm_i915_private *dev_priv, |
1295 | enum pipe pipe, bool state) | |
b24e7179 JB |
1296 | { |
1297 | int reg; | |
1298 | u32 val; | |
63d7bbe9 | 1299 | bool cur_state; |
702e7a56 PZ |
1300 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1301 | pipe); | |
b24e7179 | 1302 | |
b6b5d049 VS |
1303 | /* if we need the pipe quirk it must be always on */ |
1304 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1305 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1306 | state = true; |
1307 | ||
f458ebbc | 1308 | if (!intel_display_power_is_enabled(dev_priv, |
b97186f0 | 1309 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
69310161 PZ |
1310 | cur_state = false; |
1311 | } else { | |
1312 | reg = PIPECONF(cpu_transcoder); | |
1313 | val = I915_READ(reg); | |
1314 | cur_state = !!(val & PIPECONF_ENABLE); | |
1315 | } | |
1316 | ||
e2c719b7 | 1317 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1318 | "pipe %c assertion failure (expected %s, current %s)\n", |
9db4a9c7 | 1319 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1320 | } |
1321 | ||
931872fc CW |
1322 | static void assert_plane(struct drm_i915_private *dev_priv, |
1323 | enum plane plane, bool state) | |
b24e7179 JB |
1324 | { |
1325 | int reg; | |
1326 | u32 val; | |
931872fc | 1327 | bool cur_state; |
b24e7179 JB |
1328 | |
1329 | reg = DSPCNTR(plane); | |
1330 | val = I915_READ(reg); | |
931872fc | 1331 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1332 | I915_STATE_WARN(cur_state != state, |
931872fc CW |
1333 | "plane %c assertion failure (expected %s, current %s)\n", |
1334 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1335 | } |
1336 | ||
931872fc CW |
1337 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1338 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1339 | ||
b24e7179 JB |
1340 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1341 | enum pipe pipe) | |
1342 | { | |
653e1026 | 1343 | struct drm_device *dev = dev_priv->dev; |
b24e7179 JB |
1344 | int reg, i; |
1345 | u32 val; | |
1346 | int cur_pipe; | |
1347 | ||
653e1026 VS |
1348 | /* Primary planes are fixed to pipes on gen4+ */ |
1349 | if (INTEL_INFO(dev)->gen >= 4) { | |
28c05794 AJ |
1350 | reg = DSPCNTR(pipe); |
1351 | val = I915_READ(reg); | |
e2c719b7 | 1352 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1353 | "plane %c assertion failure, should be disabled but not\n", |
1354 | plane_name(pipe)); | |
19ec1358 | 1355 | return; |
28c05794 | 1356 | } |
19ec1358 | 1357 | |
b24e7179 | 1358 | /* Need to check both planes against the pipe */ |
055e393f | 1359 | for_each_pipe(dev_priv, i) { |
b24e7179 JB |
1360 | reg = DSPCNTR(i); |
1361 | val = I915_READ(reg); | |
1362 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1363 | DISPPLANE_SEL_PIPE_SHIFT; | |
e2c719b7 | 1364 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1365 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1366 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1367 | } |
1368 | } | |
1369 | ||
19332d7a JB |
1370 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1371 | enum pipe pipe) | |
1372 | { | |
20674eef | 1373 | struct drm_device *dev = dev_priv->dev; |
1fe47785 | 1374 | int reg, sprite; |
19332d7a JB |
1375 | u32 val; |
1376 | ||
7feb8b88 | 1377 | if (INTEL_INFO(dev)->gen >= 9) { |
3bdcfc0c | 1378 | for_each_sprite(dev_priv, pipe, sprite) { |
7feb8b88 | 1379 | val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1380 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1381 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1382 | sprite, pipe_name(pipe)); | |
1383 | } | |
1384 | } else if (IS_VALLEYVIEW(dev)) { | |
3bdcfc0c | 1385 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 1386 | reg = SPCNTR(pipe, sprite); |
20674eef | 1387 | val = I915_READ(reg); |
e2c719b7 | 1388 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1389 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1390 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1391 | } |
1392 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
1393 | reg = SPRCTL(pipe); | |
19332d7a | 1394 | val = I915_READ(reg); |
e2c719b7 | 1395 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1396 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1397 | plane_name(pipe), pipe_name(pipe)); |
1398 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
1399 | reg = DVSCNTR(pipe); | |
19332d7a | 1400 | val = I915_READ(reg); |
e2c719b7 | 1401 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1402 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1403 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1404 | } |
1405 | } | |
1406 | ||
08c71e5e VS |
1407 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1408 | { | |
e2c719b7 | 1409 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1410 | drm_crtc_vblank_put(crtc); |
1411 | } | |
1412 | ||
89eff4be | 1413 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
92f2584a JB |
1414 | { |
1415 | u32 val; | |
1416 | bool enabled; | |
1417 | ||
e2c719b7 | 1418 | I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
9d82aa17 | 1419 | |
92f2584a JB |
1420 | val = I915_READ(PCH_DREF_CONTROL); |
1421 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1422 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
e2c719b7 | 1423 | I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
92f2584a JB |
1424 | } |
1425 | ||
ab9412ba DV |
1426 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1427 | enum pipe pipe) | |
92f2584a JB |
1428 | { |
1429 | int reg; | |
1430 | u32 val; | |
1431 | bool enabled; | |
1432 | ||
ab9412ba | 1433 | reg = PCH_TRANSCONF(pipe); |
92f2584a JB |
1434 | val = I915_READ(reg); |
1435 | enabled = !!(val & TRANS_ENABLE); | |
e2c719b7 | 1436 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1437 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1438 | pipe_name(pipe)); | |
92f2584a JB |
1439 | } |
1440 | ||
4e634389 KP |
1441 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1442 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1443 | { |
1444 | if ((val & DP_PORT_EN) == 0) | |
1445 | return false; | |
1446 | ||
1447 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1448 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1449 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1450 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1451 | return false; | |
44f37d1f CML |
1452 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1453 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) | |
1454 | return false; | |
f0575e92 KP |
1455 | } else { |
1456 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1457 | return false; | |
1458 | } | |
1459 | return true; | |
1460 | } | |
1461 | ||
1519b995 KP |
1462 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1463 | enum pipe pipe, u32 val) | |
1464 | { | |
dc0fa718 | 1465 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1466 | return false; |
1467 | ||
1468 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1469 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1470 | return false; |
44f37d1f CML |
1471 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1472 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) | |
1473 | return false; | |
1519b995 | 1474 | } else { |
dc0fa718 | 1475 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1476 | return false; |
1477 | } | |
1478 | return true; | |
1479 | } | |
1480 | ||
1481 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1482 | enum pipe pipe, u32 val) | |
1483 | { | |
1484 | if ((val & LVDS_PORT_EN) == 0) | |
1485 | return false; | |
1486 | ||
1487 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1488 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1489 | return false; | |
1490 | } else { | |
1491 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1492 | return false; | |
1493 | } | |
1494 | return true; | |
1495 | } | |
1496 | ||
1497 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1498 | enum pipe pipe, u32 val) | |
1499 | { | |
1500 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1501 | return false; | |
1502 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1503 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1504 | return false; | |
1505 | } else { | |
1506 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1507 | return false; | |
1508 | } | |
1509 | return true; | |
1510 | } | |
1511 | ||
291906f1 | 1512 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1513 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1514 | { |
47a05eca | 1515 | u32 val = I915_READ(reg); |
e2c719b7 | 1516 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1517 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1518 | reg, pipe_name(pipe)); |
de9a35ab | 1519 | |
e2c719b7 | 1520 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1521 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1522 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1523 | } |
1524 | ||
1525 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1526 | enum pipe pipe, int reg) | |
1527 | { | |
47a05eca | 1528 | u32 val = I915_READ(reg); |
e2c719b7 | 1529 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1530 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1531 | reg, pipe_name(pipe)); |
de9a35ab | 1532 | |
e2c719b7 | 1533 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1534 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1535 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1536 | } |
1537 | ||
1538 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1539 | enum pipe pipe) | |
1540 | { | |
1541 | int reg; | |
1542 | u32 val; | |
291906f1 | 1543 | |
f0575e92 KP |
1544 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1545 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1546 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1547 | |
1548 | reg = PCH_ADPA; | |
1549 | val = I915_READ(reg); | |
e2c719b7 | 1550 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1551 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1552 | pipe_name(pipe)); |
291906f1 JB |
1553 | |
1554 | reg = PCH_LVDS; | |
1555 | val = I915_READ(reg); | |
e2c719b7 | 1556 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1557 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1558 | pipe_name(pipe)); |
291906f1 | 1559 | |
e2debe91 PZ |
1560 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1561 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1562 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1563 | } |
1564 | ||
40e9cf64 JB |
1565 | static void intel_init_dpio(struct drm_device *dev) |
1566 | { | |
1567 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1568 | ||
1569 | if (!IS_VALLEYVIEW(dev)) | |
1570 | return; | |
1571 | ||
a09caddd CML |
1572 | /* |
1573 | * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C), | |
1574 | * CHV x1 PHY (DP/HDMI D) | |
1575 | * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C) | |
1576 | */ | |
1577 | if (IS_CHERRYVIEW(dev)) { | |
1578 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2; | |
1579 | DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO; | |
1580 | } else { | |
1581 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; | |
1582 | } | |
5382f5f3 JB |
1583 | } |
1584 | ||
d288f65f | 1585 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1586 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1587 | { |
426115cf DV |
1588 | struct drm_device *dev = crtc->base.dev; |
1589 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1590 | int reg = DPLL(crtc->pipe); | |
d288f65f | 1591 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
87442f73 | 1592 | |
426115cf | 1593 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 DV |
1594 | |
1595 | /* No really, not for ILK+ */ | |
1596 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); | |
1597 | ||
1598 | /* PLL is protected by panel, make sure we can write it */ | |
6a9e7363 | 1599 | if (IS_MOBILE(dev_priv->dev)) |
426115cf | 1600 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1601 | |
426115cf DV |
1602 | I915_WRITE(reg, dpll); |
1603 | POSTING_READ(reg); | |
1604 | udelay(150); | |
1605 | ||
1606 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1607 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1608 | ||
d288f65f | 1609 | I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); |
426115cf | 1610 | POSTING_READ(DPLL_MD(crtc->pipe)); |
87442f73 DV |
1611 | |
1612 | /* We do this three times for luck */ | |
426115cf | 1613 | I915_WRITE(reg, dpll); |
87442f73 DV |
1614 | POSTING_READ(reg); |
1615 | udelay(150); /* wait for warmup */ | |
426115cf | 1616 | I915_WRITE(reg, dpll); |
87442f73 DV |
1617 | POSTING_READ(reg); |
1618 | udelay(150); /* wait for warmup */ | |
426115cf | 1619 | I915_WRITE(reg, dpll); |
87442f73 DV |
1620 | POSTING_READ(reg); |
1621 | udelay(150); /* wait for warmup */ | |
1622 | } | |
1623 | ||
d288f65f | 1624 | static void chv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1625 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
1626 | { |
1627 | struct drm_device *dev = crtc->base.dev; | |
1628 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1629 | int pipe = crtc->pipe; | |
1630 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9d556c99 CML |
1631 | u32 tmp; |
1632 | ||
1633 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1634 | ||
1635 | BUG_ON(!IS_CHERRYVIEW(dev_priv->dev)); | |
1636 | ||
1637 | mutex_lock(&dev_priv->dpio_lock); | |
1638 | ||
1639 | /* Enable back the 10bit clock to display controller */ | |
1640 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1641 | tmp |= DPIO_DCLKP_EN; | |
1642 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1643 | ||
1644 | /* | |
1645 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1646 | */ | |
1647 | udelay(1); | |
1648 | ||
1649 | /* Enable PLL */ | |
d288f65f | 1650 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1651 | |
1652 | /* Check PLL is locked */ | |
a11b0703 | 1653 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
9d556c99 CML |
1654 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
1655 | ||
a11b0703 | 1656 | /* not sure when this should be written */ |
d288f65f | 1657 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
a11b0703 VS |
1658 | POSTING_READ(DPLL_MD(pipe)); |
1659 | ||
9d556c99 CML |
1660 | mutex_unlock(&dev_priv->dpio_lock); |
1661 | } | |
1662 | ||
1c4e0274 VS |
1663 | static int intel_num_dvo_pipes(struct drm_device *dev) |
1664 | { | |
1665 | struct intel_crtc *crtc; | |
1666 | int count = 0; | |
1667 | ||
1668 | for_each_intel_crtc(dev, crtc) | |
1669 | count += crtc->active && | |
409ee761 | 1670 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO); |
1c4e0274 VS |
1671 | |
1672 | return count; | |
1673 | } | |
1674 | ||
66e3d5c0 | 1675 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1676 | { |
66e3d5c0 DV |
1677 | struct drm_device *dev = crtc->base.dev; |
1678 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1679 | int reg = DPLL(crtc->pipe); | |
6e3c9717 | 1680 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1681 | |
66e3d5c0 | 1682 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1683 | |
63d7bbe9 | 1684 | /* No really, not for ILK+ */ |
3d13ef2e | 1685 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1686 | |
1687 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1688 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1689 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1690 | |
1c4e0274 VS |
1691 | /* Enable DVO 2x clock on both PLLs if necessary */ |
1692 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { | |
1693 | /* | |
1694 | * It appears to be important that we don't enable this | |
1695 | * for the current pipe before otherwise configuring the | |
1696 | * PLL. No idea how this should be handled if multiple | |
1697 | * DVO outputs are enabled simultaneosly. | |
1698 | */ | |
1699 | dpll |= DPLL_DVO_2X_MODE; | |
1700 | I915_WRITE(DPLL(!crtc->pipe), | |
1701 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1702 | } | |
66e3d5c0 DV |
1703 | |
1704 | /* Wait for the clocks to stabilize. */ | |
1705 | POSTING_READ(reg); | |
1706 | udelay(150); | |
1707 | ||
1708 | if (INTEL_INFO(dev)->gen >= 4) { | |
1709 | I915_WRITE(DPLL_MD(crtc->pipe), | |
6e3c9717 | 1710 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1711 | } else { |
1712 | /* The pixel multiplier can only be updated once the | |
1713 | * DPLL is enabled and the clocks are stable. | |
1714 | * | |
1715 | * So write it again. | |
1716 | */ | |
1717 | I915_WRITE(reg, dpll); | |
1718 | } | |
63d7bbe9 JB |
1719 | |
1720 | /* We do this three times for luck */ | |
66e3d5c0 | 1721 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1722 | POSTING_READ(reg); |
1723 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1724 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1725 | POSTING_READ(reg); |
1726 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1727 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1728 | POSTING_READ(reg); |
1729 | udelay(150); /* wait for warmup */ | |
1730 | } | |
1731 | ||
1732 | /** | |
50b44a44 | 1733 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1734 | * @dev_priv: i915 private structure |
1735 | * @pipe: pipe PLL to disable | |
1736 | * | |
1737 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1738 | * | |
1739 | * Note! This is for pre-ILK only. | |
1740 | */ | |
1c4e0274 | 1741 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1742 | { |
1c4e0274 VS |
1743 | struct drm_device *dev = crtc->base.dev; |
1744 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1745 | enum pipe pipe = crtc->pipe; | |
1746 | ||
1747 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
1748 | if (IS_I830(dev) && | |
409ee761 | 1749 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) && |
1c4e0274 VS |
1750 | intel_num_dvo_pipes(dev) == 1) { |
1751 | I915_WRITE(DPLL(PIPE_B), | |
1752 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1753 | I915_WRITE(DPLL(PIPE_A), | |
1754 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1755 | } | |
1756 | ||
b6b5d049 VS |
1757 | /* Don't disable pipe or pipe PLLs if needed */ |
1758 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1759 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1760 | return; |
1761 | ||
1762 | /* Make sure the pipe isn't still relying on us */ | |
1763 | assert_pipe_disabled(dev_priv, pipe); | |
1764 | ||
50b44a44 DV |
1765 | I915_WRITE(DPLL(pipe), 0); |
1766 | POSTING_READ(DPLL(pipe)); | |
63d7bbe9 JB |
1767 | } |
1768 | ||
f6071166 JB |
1769 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1770 | { | |
1771 | u32 val = 0; | |
1772 | ||
1773 | /* Make sure the pipe isn't still relying on us */ | |
1774 | assert_pipe_disabled(dev_priv, pipe); | |
1775 | ||
e5cbfbfb ID |
1776 | /* |
1777 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1778 | * The latter is needed for VGA hotplug / manual detection. | |
1779 | */ | |
f6071166 | 1780 | if (pipe == PIPE_B) |
e5cbfbfb | 1781 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV; |
f6071166 JB |
1782 | I915_WRITE(DPLL(pipe), val); |
1783 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1784 | |
1785 | } | |
1786 | ||
1787 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1788 | { | |
d752048d | 1789 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1790 | u32 val; |
1791 | ||
a11b0703 VS |
1792 | /* Make sure the pipe isn't still relying on us */ |
1793 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1794 | |
a11b0703 | 1795 | /* Set PLL en = 0 */ |
d17ec4ce | 1796 | val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV; |
a11b0703 VS |
1797 | if (pipe != PIPE_A) |
1798 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1799 | I915_WRITE(DPLL(pipe), val); | |
1800 | POSTING_READ(DPLL(pipe)); | |
d752048d VS |
1801 | |
1802 | mutex_lock(&dev_priv->dpio_lock); | |
1803 | ||
1804 | /* Disable 10bit clock to display controller */ | |
1805 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1806 | val &= ~DPIO_DCLKP_EN; | |
1807 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1808 | ||
61407f6d VS |
1809 | /* disable left/right clock distribution */ |
1810 | if (pipe != PIPE_B) { | |
1811 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); | |
1812 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); | |
1813 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); | |
1814 | } else { | |
1815 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); | |
1816 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); | |
1817 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); | |
1818 | } | |
1819 | ||
d752048d | 1820 | mutex_unlock(&dev_priv->dpio_lock); |
f6071166 JB |
1821 | } |
1822 | ||
e4607fcf CML |
1823 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
1824 | struct intel_digital_port *dport) | |
89b667f8 JB |
1825 | { |
1826 | u32 port_mask; | |
00fc31b7 | 1827 | int dpll_reg; |
89b667f8 | 1828 | |
e4607fcf CML |
1829 | switch (dport->port) { |
1830 | case PORT_B: | |
89b667f8 | 1831 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1832 | dpll_reg = DPLL(0); |
e4607fcf CML |
1833 | break; |
1834 | case PORT_C: | |
89b667f8 | 1835 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 CML |
1836 | dpll_reg = DPLL(0); |
1837 | break; | |
1838 | case PORT_D: | |
1839 | port_mask = DPLL_PORTD_READY_MASK; | |
1840 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1841 | break; |
1842 | default: | |
1843 | BUG(); | |
1844 | } | |
89b667f8 | 1845 | |
00fc31b7 | 1846 | if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000)) |
89b667f8 | 1847 | WARN(1, "timed out waiting for port %c ready: 0x%08x\n", |
00fc31b7 | 1848 | port_name(dport->port), I915_READ(dpll_reg)); |
89b667f8 JB |
1849 | } |
1850 | ||
b14b1055 DV |
1851 | static void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
1852 | { | |
1853 | struct drm_device *dev = crtc->base.dev; | |
1854 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1855 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
1856 | ||
be19f0ff CW |
1857 | if (WARN_ON(pll == NULL)) |
1858 | return; | |
1859 | ||
3e369b76 | 1860 | WARN_ON(!pll->config.crtc_mask); |
b14b1055 DV |
1861 | if (pll->active == 0) { |
1862 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); | |
1863 | WARN_ON(pll->on); | |
1864 | assert_shared_dpll_disabled(dev_priv, pll); | |
1865 | ||
1866 | pll->mode_set(dev_priv, pll); | |
1867 | } | |
1868 | } | |
1869 | ||
92f2584a | 1870 | /** |
85b3894f | 1871 | * intel_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1872 | * @dev_priv: i915 private structure |
1873 | * @pipe: pipe PLL to enable | |
1874 | * | |
1875 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1876 | * drives the transcoder clock. | |
1877 | */ | |
85b3894f | 1878 | static void intel_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1879 | { |
3d13ef2e DL |
1880 | struct drm_device *dev = crtc->base.dev; |
1881 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1882 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
92f2584a | 1883 | |
87a875bb | 1884 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1885 | return; |
1886 | ||
3e369b76 | 1887 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1888 | return; |
ee7b9f93 | 1889 | |
74dd6928 | 1890 | DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n", |
46edb027 | 1891 | pll->name, pll->active, pll->on, |
e2b78267 | 1892 | crtc->base.base.id); |
92f2584a | 1893 | |
cdbd2316 DV |
1894 | if (pll->active++) { |
1895 | WARN_ON(!pll->on); | |
e9d6944e | 1896 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1897 | return; |
1898 | } | |
f4a091c7 | 1899 | WARN_ON(pll->on); |
ee7b9f93 | 1900 | |
bd2bb1b9 PZ |
1901 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
1902 | ||
46edb027 | 1903 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1904 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1905 | pll->on = true; |
92f2584a JB |
1906 | } |
1907 | ||
f6daaec2 | 1908 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1909 | { |
3d13ef2e DL |
1910 | struct drm_device *dev = crtc->base.dev; |
1911 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1912 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
4c609cb8 | 1913 | |
92f2584a | 1914 | /* PCH only available on ILK+ */ |
3d13ef2e | 1915 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
87a875bb | 1916 | if (WARN_ON(pll == NULL)) |
ee7b9f93 | 1917 | return; |
92f2584a | 1918 | |
3e369b76 | 1919 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1920 | return; |
7a419866 | 1921 | |
46edb027 DV |
1922 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1923 | pll->name, pll->active, pll->on, | |
e2b78267 | 1924 | crtc->base.base.id); |
7a419866 | 1925 | |
48da64a8 | 1926 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1927 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1928 | return; |
1929 | } | |
1930 | ||
e9d6944e | 1931 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1932 | WARN_ON(!pll->on); |
cdbd2316 | 1933 | if (--pll->active) |
7a419866 | 1934 | return; |
ee7b9f93 | 1935 | |
46edb027 | 1936 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1937 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1938 | pll->on = false; |
bd2bb1b9 PZ |
1939 | |
1940 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
92f2584a JB |
1941 | } |
1942 | ||
b8a4f404 PZ |
1943 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1944 | enum pipe pipe) | |
040484af | 1945 | { |
23670b32 | 1946 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1947 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1948 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
23670b32 | 1949 | uint32_t reg, val, pipeconf_val; |
040484af JB |
1950 | |
1951 | /* PCH only available on ILK+ */ | |
55522f37 | 1952 | BUG_ON(!HAS_PCH_SPLIT(dev)); |
040484af JB |
1953 | |
1954 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1955 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1956 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1957 | |
1958 | /* FDI must be feeding us bits for PCH ports */ | |
1959 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1960 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1961 | ||
23670b32 DV |
1962 | if (HAS_PCH_CPT(dev)) { |
1963 | /* Workaround: Set the timing override bit before enabling the | |
1964 | * pch transcoder. */ | |
1965 | reg = TRANS_CHICKEN2(pipe); | |
1966 | val = I915_READ(reg); | |
1967 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1968 | I915_WRITE(reg, val); | |
59c859d6 | 1969 | } |
23670b32 | 1970 | |
ab9412ba | 1971 | reg = PCH_TRANSCONF(pipe); |
040484af | 1972 | val = I915_READ(reg); |
5f7f726d | 1973 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1974 | |
1975 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1976 | /* | |
1977 | * make the BPC in transcoder be consistent with | |
1978 | * that in pipeconf reg. | |
1979 | */ | |
dfd07d72 DV |
1980 | val &= ~PIPECONF_BPC_MASK; |
1981 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1982 | } |
5f7f726d PZ |
1983 | |
1984 | val &= ~TRANS_INTERLACE_MASK; | |
1985 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 | 1986 | if (HAS_PCH_IBX(dev_priv->dev) && |
409ee761 | 1987 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
1988 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1989 | else | |
1990 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1991 | else |
1992 | val |= TRANS_PROGRESSIVE; | |
1993 | ||
040484af JB |
1994 | I915_WRITE(reg, val | TRANS_ENABLE); |
1995 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 1996 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1997 | } |
1998 | ||
8fb033d7 | 1999 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 2000 | enum transcoder cpu_transcoder) |
040484af | 2001 | { |
8fb033d7 | 2002 | u32 val, pipeconf_val; |
8fb033d7 PZ |
2003 | |
2004 | /* PCH only available on ILK+ */ | |
55522f37 | 2005 | BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev)); |
8fb033d7 | 2006 | |
8fb033d7 | 2007 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 2008 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 2009 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 2010 | |
223a6fdf PZ |
2011 | /* Workaround: set timing override bit. */ |
2012 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 2013 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf PZ |
2014 | I915_WRITE(_TRANSA_CHICKEN2, val); |
2015 | ||
25f3ef11 | 2016 | val = TRANS_ENABLE; |
937bb610 | 2017 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 2018 | |
9a76b1c6 PZ |
2019 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
2020 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 2021 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
2022 | else |
2023 | val |= TRANS_PROGRESSIVE; | |
2024 | ||
ab9412ba DV |
2025 | I915_WRITE(LPT_TRANSCONF, val); |
2026 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 2027 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
2028 | } |
2029 | ||
b8a4f404 PZ |
2030 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
2031 | enum pipe pipe) | |
040484af | 2032 | { |
23670b32 DV |
2033 | struct drm_device *dev = dev_priv->dev; |
2034 | uint32_t reg, val; | |
040484af JB |
2035 | |
2036 | /* FDI relies on the transcoder */ | |
2037 | assert_fdi_tx_disabled(dev_priv, pipe); | |
2038 | assert_fdi_rx_disabled(dev_priv, pipe); | |
2039 | ||
291906f1 JB |
2040 | /* Ports must be off as well */ |
2041 | assert_pch_ports_disabled(dev_priv, pipe); | |
2042 | ||
ab9412ba | 2043 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
2044 | val = I915_READ(reg); |
2045 | val &= ~TRANS_ENABLE; | |
2046 | I915_WRITE(reg, val); | |
2047 | /* wait for PCH transcoder off, transcoder state */ | |
2048 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 2049 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 DV |
2050 | |
2051 | if (!HAS_PCH_IBX(dev)) { | |
2052 | /* Workaround: Clear the timing override chicken bit again. */ | |
2053 | reg = TRANS_CHICKEN2(pipe); | |
2054 | val = I915_READ(reg); | |
2055 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
2056 | I915_WRITE(reg, val); | |
2057 | } | |
040484af JB |
2058 | } |
2059 | ||
ab4d966c | 2060 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 2061 | { |
8fb033d7 PZ |
2062 | u32 val; |
2063 | ||
ab9412ba | 2064 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 2065 | val &= ~TRANS_ENABLE; |
ab9412ba | 2066 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 2067 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 2068 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 2069 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
2070 | |
2071 | /* Workaround: clear timing override bit. */ | |
2072 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 2073 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf | 2074 | I915_WRITE(_TRANSA_CHICKEN2, val); |
040484af JB |
2075 | } |
2076 | ||
b24e7179 | 2077 | /** |
309cfea8 | 2078 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 2079 | * @crtc: crtc responsible for the pipe |
b24e7179 | 2080 | * |
0372264a | 2081 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 2082 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 2083 | */ |
e1fdc473 | 2084 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2085 | { |
0372264a PZ |
2086 | struct drm_device *dev = crtc->base.dev; |
2087 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2088 | enum pipe pipe = crtc->pipe; | |
702e7a56 PZ |
2089 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
2090 | pipe); | |
1a240d4d | 2091 | enum pipe pch_transcoder; |
b24e7179 JB |
2092 | int reg; |
2093 | u32 val; | |
2094 | ||
58c6eaa2 | 2095 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 2096 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
2097 | assert_sprites_disabled(dev_priv, pipe); |
2098 | ||
681e5811 | 2099 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
2100 | pch_transcoder = TRANSCODER_A; |
2101 | else | |
2102 | pch_transcoder = pipe; | |
2103 | ||
b24e7179 JB |
2104 | /* |
2105 | * A pipe without a PLL won't actually be able to drive bits from | |
2106 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
2107 | * need the check. | |
2108 | */ | |
2109 | if (!HAS_PCH_SPLIT(dev_priv->dev)) | |
409ee761 | 2110 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
2111 | assert_dsi_pll_enabled(dev_priv); |
2112 | else | |
2113 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 2114 | else { |
6e3c9717 | 2115 | if (crtc->config->has_pch_encoder) { |
040484af | 2116 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 2117 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
2118 | assert_fdi_tx_pll_enabled(dev_priv, |
2119 | (enum pipe) cpu_transcoder); | |
040484af JB |
2120 | } |
2121 | /* FIXME: assert CPU port conditions for SNB+ */ | |
2122 | } | |
b24e7179 | 2123 | |
702e7a56 | 2124 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2125 | val = I915_READ(reg); |
7ad25d48 | 2126 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
2127 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
2128 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 2129 | return; |
7ad25d48 | 2130 | } |
00d70b15 CW |
2131 | |
2132 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 2133 | POSTING_READ(reg); |
b24e7179 JB |
2134 | } |
2135 | ||
2136 | /** | |
309cfea8 | 2137 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2138 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2139 | * |
575f7ab7 VS |
2140 | * Disable the pipe of @crtc, making sure that various hardware |
2141 | * specific requirements are met, if applicable, e.g. plane | |
2142 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2143 | * |
2144 | * Will wait until the pipe has shut down before returning. | |
2145 | */ | |
575f7ab7 | 2146 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2147 | { |
575f7ab7 | 2148 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
6e3c9717 | 2149 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 2150 | enum pipe pipe = crtc->pipe; |
b24e7179 JB |
2151 | int reg; |
2152 | u32 val; | |
2153 | ||
2154 | /* | |
2155 | * Make sure planes won't keep trying to pump pixels to us, | |
2156 | * or we might hang the display. | |
2157 | */ | |
2158 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2159 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2160 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2161 | |
702e7a56 | 2162 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2163 | val = I915_READ(reg); |
00d70b15 CW |
2164 | if ((val & PIPECONF_ENABLE) == 0) |
2165 | return; | |
2166 | ||
67adc644 VS |
2167 | /* |
2168 | * Double wide has implications for planes | |
2169 | * so best keep it disabled when not needed. | |
2170 | */ | |
6e3c9717 | 2171 | if (crtc->config->double_wide) |
67adc644 VS |
2172 | val &= ~PIPECONF_DOUBLE_WIDE; |
2173 | ||
2174 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2175 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2176 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2177 | val &= ~PIPECONF_ENABLE; |
2178 | ||
2179 | I915_WRITE(reg, val); | |
2180 | if ((val & PIPECONF_ENABLE) == 0) | |
2181 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2182 | } |
2183 | ||
d74362c9 KP |
2184 | /* |
2185 | * Plane regs are double buffered, going from enabled->disabled needs a | |
2186 | * trigger in order to latch. The display address reg provides this. | |
2187 | */ | |
1dba99f4 VS |
2188 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
2189 | enum plane plane) | |
d74362c9 | 2190 | { |
3d13ef2e DL |
2191 | struct drm_device *dev = dev_priv->dev; |
2192 | u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane); | |
1dba99f4 VS |
2193 | |
2194 | I915_WRITE(reg, I915_READ(reg)); | |
2195 | POSTING_READ(reg); | |
d74362c9 KP |
2196 | } |
2197 | ||
b24e7179 | 2198 | /** |
262ca2b0 | 2199 | * intel_enable_primary_hw_plane - enable the primary plane on a given pipe |
fdd508a6 VS |
2200 | * @plane: plane to be enabled |
2201 | * @crtc: crtc for the plane | |
b24e7179 | 2202 | * |
fdd508a6 | 2203 | * Enable @plane on @crtc, making sure that the pipe is running first. |
b24e7179 | 2204 | */ |
fdd508a6 VS |
2205 | static void intel_enable_primary_hw_plane(struct drm_plane *plane, |
2206 | struct drm_crtc *crtc) | |
b24e7179 | 2207 | { |
fdd508a6 VS |
2208 | struct drm_device *dev = plane->dev; |
2209 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2210 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b24e7179 JB |
2211 | |
2212 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
fdd508a6 | 2213 | assert_pipe_enabled(dev_priv, intel_crtc->pipe); |
b24e7179 | 2214 | |
98ec7739 VS |
2215 | if (intel_crtc->primary_enabled) |
2216 | return; | |
0037f71c | 2217 | |
4c445e0e | 2218 | intel_crtc->primary_enabled = true; |
939c2fe8 | 2219 | |
fdd508a6 VS |
2220 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
2221 | crtc->x, crtc->y); | |
33c3b0d1 VS |
2222 | |
2223 | /* | |
2224 | * BDW signals flip done immediately if the plane | |
2225 | * is disabled, even if the plane enable is already | |
2226 | * armed to occur at the next vblank :( | |
2227 | */ | |
2228 | if (IS_BROADWELL(dev)) | |
2229 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
b24e7179 JB |
2230 | } |
2231 | ||
b24e7179 | 2232 | /** |
262ca2b0 | 2233 | * intel_disable_primary_hw_plane - disable the primary hardware plane |
fdd508a6 VS |
2234 | * @plane: plane to be disabled |
2235 | * @crtc: crtc for the plane | |
b24e7179 | 2236 | * |
fdd508a6 | 2237 | * Disable @plane on @crtc, making sure that the pipe is running first. |
b24e7179 | 2238 | */ |
fdd508a6 VS |
2239 | static void intel_disable_primary_hw_plane(struct drm_plane *plane, |
2240 | struct drm_crtc *crtc) | |
b24e7179 | 2241 | { |
fdd508a6 VS |
2242 | struct drm_device *dev = plane->dev; |
2243 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2244 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2245 | ||
32b7eeec MR |
2246 | if (WARN_ON(!intel_crtc->active)) |
2247 | return; | |
b24e7179 | 2248 | |
98ec7739 VS |
2249 | if (!intel_crtc->primary_enabled) |
2250 | return; | |
0037f71c | 2251 | |
4c445e0e | 2252 | intel_crtc->primary_enabled = false; |
939c2fe8 | 2253 | |
fdd508a6 VS |
2254 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
2255 | crtc->x, crtc->y); | |
b24e7179 JB |
2256 | } |
2257 | ||
693db184 CW |
2258 | static bool need_vtd_wa(struct drm_device *dev) |
2259 | { | |
2260 | #ifdef CONFIG_INTEL_IOMMU | |
2261 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2262 | return true; | |
2263 | #endif | |
2264 | return false; | |
2265 | } | |
2266 | ||
50470bb0 | 2267 | unsigned int |
6761dd31 TU |
2268 | intel_tile_height(struct drm_device *dev, uint32_t pixel_format, |
2269 | uint64_t fb_format_modifier) | |
a57ce0b2 | 2270 | { |
6761dd31 TU |
2271 | unsigned int tile_height; |
2272 | uint32_t pixel_bytes; | |
a57ce0b2 | 2273 | |
b5d0e9bf DL |
2274 | switch (fb_format_modifier) { |
2275 | case DRM_FORMAT_MOD_NONE: | |
2276 | tile_height = 1; | |
2277 | break; | |
2278 | case I915_FORMAT_MOD_X_TILED: | |
2279 | tile_height = IS_GEN2(dev) ? 16 : 8; | |
2280 | break; | |
2281 | case I915_FORMAT_MOD_Y_TILED: | |
2282 | tile_height = 32; | |
2283 | break; | |
2284 | case I915_FORMAT_MOD_Yf_TILED: | |
6761dd31 TU |
2285 | pixel_bytes = drm_format_plane_cpp(pixel_format, 0); |
2286 | switch (pixel_bytes) { | |
b5d0e9bf | 2287 | default: |
6761dd31 | 2288 | case 1: |
b5d0e9bf DL |
2289 | tile_height = 64; |
2290 | break; | |
6761dd31 TU |
2291 | case 2: |
2292 | case 4: | |
b5d0e9bf DL |
2293 | tile_height = 32; |
2294 | break; | |
6761dd31 | 2295 | case 8: |
b5d0e9bf DL |
2296 | tile_height = 16; |
2297 | break; | |
6761dd31 | 2298 | case 16: |
b5d0e9bf DL |
2299 | WARN_ONCE(1, |
2300 | "128-bit pixels are not supported for display!"); | |
2301 | tile_height = 16; | |
2302 | break; | |
2303 | } | |
2304 | break; | |
2305 | default: | |
2306 | MISSING_CASE(fb_format_modifier); | |
2307 | tile_height = 1; | |
2308 | break; | |
2309 | } | |
091df6cb | 2310 | |
6761dd31 TU |
2311 | return tile_height; |
2312 | } | |
2313 | ||
2314 | unsigned int | |
2315 | intel_fb_align_height(struct drm_device *dev, unsigned int height, | |
2316 | uint32_t pixel_format, uint64_t fb_format_modifier) | |
2317 | { | |
2318 | return ALIGN(height, intel_tile_height(dev, pixel_format, | |
2319 | fb_format_modifier)); | |
a57ce0b2 JB |
2320 | } |
2321 | ||
f64b98cd TU |
2322 | static int |
2323 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb, | |
2324 | const struct drm_plane_state *plane_state) | |
2325 | { | |
50470bb0 | 2326 | struct intel_rotation_info *info = &view->rotation_info; |
50470bb0 | 2327 | |
f64b98cd TU |
2328 | *view = i915_ggtt_view_normal; |
2329 | ||
50470bb0 TU |
2330 | if (!plane_state) |
2331 | return 0; | |
2332 | ||
121920fa | 2333 | if (!intel_rotation_90_or_270(plane_state->rotation)) |
50470bb0 TU |
2334 | return 0; |
2335 | ||
9abc4648 | 2336 | *view = i915_ggtt_view_rotated; |
50470bb0 TU |
2337 | |
2338 | info->height = fb->height; | |
2339 | info->pixel_format = fb->pixel_format; | |
2340 | info->pitch = fb->pitches[0]; | |
2341 | info->fb_modifier = fb->modifier[0]; | |
2342 | ||
f64b98cd TU |
2343 | return 0; |
2344 | } | |
2345 | ||
127bd2ac | 2346 | int |
850c4cdc TU |
2347 | intel_pin_and_fence_fb_obj(struct drm_plane *plane, |
2348 | struct drm_framebuffer *fb, | |
82bc3b2d | 2349 | const struct drm_plane_state *plane_state, |
a4872ba6 | 2350 | struct intel_engine_cs *pipelined) |
6b95a207 | 2351 | { |
850c4cdc | 2352 | struct drm_device *dev = fb->dev; |
ce453d81 | 2353 | struct drm_i915_private *dev_priv = dev->dev_private; |
850c4cdc | 2354 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2355 | struct i915_ggtt_view view; |
6b95a207 KH |
2356 | u32 alignment; |
2357 | int ret; | |
2358 | ||
ebcdd39e MR |
2359 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2360 | ||
7b911adc TU |
2361 | switch (fb->modifier[0]) { |
2362 | case DRM_FORMAT_MOD_NONE: | |
1fada4cc DL |
2363 | if (INTEL_INFO(dev)->gen >= 9) |
2364 | alignment = 256 * 1024; | |
2365 | else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) | |
534843da | 2366 | alignment = 128 * 1024; |
a6c45cf0 | 2367 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
2368 | alignment = 4 * 1024; |
2369 | else | |
2370 | alignment = 64 * 1024; | |
6b95a207 | 2371 | break; |
7b911adc | 2372 | case I915_FORMAT_MOD_X_TILED: |
1fada4cc DL |
2373 | if (INTEL_INFO(dev)->gen >= 9) |
2374 | alignment = 256 * 1024; | |
2375 | else { | |
2376 | /* pin() will align the object as required by fence */ | |
2377 | alignment = 0; | |
2378 | } | |
6b95a207 | 2379 | break; |
7b911adc | 2380 | case I915_FORMAT_MOD_Y_TILED: |
1327b9a1 DL |
2381 | case I915_FORMAT_MOD_Yf_TILED: |
2382 | if (WARN_ONCE(INTEL_INFO(dev)->gen < 9, | |
2383 | "Y tiling bo slipped through, driver bug!\n")) | |
2384 | return -EINVAL; | |
2385 | alignment = 1 * 1024 * 1024; | |
2386 | break; | |
6b95a207 | 2387 | default: |
7b911adc TU |
2388 | MISSING_CASE(fb->modifier[0]); |
2389 | return -EINVAL; | |
6b95a207 KH |
2390 | } |
2391 | ||
f64b98cd TU |
2392 | ret = intel_fill_fb_ggtt_view(&view, fb, plane_state); |
2393 | if (ret) | |
2394 | return ret; | |
2395 | ||
693db184 CW |
2396 | /* Note that the w/a also requires 64 PTE of padding following the |
2397 | * bo. We currently fill all unused PTE with the shadow page and so | |
2398 | * we should always have valid PTE following the scanout preventing | |
2399 | * the VT-d warning. | |
2400 | */ | |
2401 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2402 | alignment = 256 * 1024; | |
2403 | ||
d6dd6843 PZ |
2404 | /* |
2405 | * Global gtt pte registers are special registers which actually forward | |
2406 | * writes to a chunk of system memory. Which means that there is no risk | |
2407 | * that the register values disappear as soon as we call | |
2408 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2409 | * pin/unpin/fence and not more. | |
2410 | */ | |
2411 | intel_runtime_pm_get(dev_priv); | |
2412 | ||
ce453d81 | 2413 | dev_priv->mm.interruptible = false; |
e6617330 | 2414 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined, |
f64b98cd | 2415 | &view); |
48b956c5 | 2416 | if (ret) |
ce453d81 | 2417 | goto err_interruptible; |
6b95a207 KH |
2418 | |
2419 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2420 | * fence, whereas 965+ only requires a fence if using | |
2421 | * framebuffer compression. For simplicity, we always install | |
2422 | * a fence as the cost is not that onerous. | |
2423 | */ | |
06d98131 | 2424 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
2425 | if (ret) |
2426 | goto err_unpin; | |
1690e1eb | 2427 | |
9a5a53b3 | 2428 | i915_gem_object_pin_fence(obj); |
6b95a207 | 2429 | |
ce453d81 | 2430 | dev_priv->mm.interruptible = true; |
d6dd6843 | 2431 | intel_runtime_pm_put(dev_priv); |
6b95a207 | 2432 | return 0; |
48b956c5 CW |
2433 | |
2434 | err_unpin: | |
f64b98cd | 2435 | i915_gem_object_unpin_from_display_plane(obj, &view); |
ce453d81 CW |
2436 | err_interruptible: |
2437 | dev_priv->mm.interruptible = true; | |
d6dd6843 | 2438 | intel_runtime_pm_put(dev_priv); |
48b956c5 | 2439 | return ret; |
6b95a207 KH |
2440 | } |
2441 | ||
82bc3b2d TU |
2442 | static void intel_unpin_fb_obj(struct drm_framebuffer *fb, |
2443 | const struct drm_plane_state *plane_state) | |
1690e1eb | 2444 | { |
82bc3b2d | 2445 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd TU |
2446 | struct i915_ggtt_view view; |
2447 | int ret; | |
82bc3b2d | 2448 | |
ebcdd39e MR |
2449 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2450 | ||
f64b98cd TU |
2451 | ret = intel_fill_fb_ggtt_view(&view, fb, plane_state); |
2452 | WARN_ONCE(ret, "Couldn't get view from plane state!"); | |
2453 | ||
1690e1eb | 2454 | i915_gem_object_unpin_fence(obj); |
f64b98cd | 2455 | i915_gem_object_unpin_from_display_plane(obj, &view); |
1690e1eb CW |
2456 | } |
2457 | ||
c2c75131 DV |
2458 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2459 | * is assumed to be a power-of-two. */ | |
bc752862 CW |
2460 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
2461 | unsigned int tiling_mode, | |
2462 | unsigned int cpp, | |
2463 | unsigned int pitch) | |
c2c75131 | 2464 | { |
bc752862 CW |
2465 | if (tiling_mode != I915_TILING_NONE) { |
2466 | unsigned int tile_rows, tiles; | |
c2c75131 | 2467 | |
bc752862 CW |
2468 | tile_rows = *y / 8; |
2469 | *y %= 8; | |
c2c75131 | 2470 | |
bc752862 CW |
2471 | tiles = *x / (512/cpp); |
2472 | *x %= 512/cpp; | |
2473 | ||
2474 | return tile_rows * pitch * 8 + tiles * 4096; | |
2475 | } else { | |
2476 | unsigned int offset; | |
2477 | ||
2478 | offset = *y * pitch + *x * cpp; | |
2479 | *y = 0; | |
2480 | *x = (offset & 4095) / cpp; | |
2481 | return offset & -4096; | |
2482 | } | |
c2c75131 DV |
2483 | } |
2484 | ||
b35d63fa | 2485 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2486 | { |
2487 | switch (format) { | |
2488 | case DISPPLANE_8BPP: | |
2489 | return DRM_FORMAT_C8; | |
2490 | case DISPPLANE_BGRX555: | |
2491 | return DRM_FORMAT_XRGB1555; | |
2492 | case DISPPLANE_BGRX565: | |
2493 | return DRM_FORMAT_RGB565; | |
2494 | default: | |
2495 | case DISPPLANE_BGRX888: | |
2496 | return DRM_FORMAT_XRGB8888; | |
2497 | case DISPPLANE_RGBX888: | |
2498 | return DRM_FORMAT_XBGR8888; | |
2499 | case DISPPLANE_BGRX101010: | |
2500 | return DRM_FORMAT_XRGB2101010; | |
2501 | case DISPPLANE_RGBX101010: | |
2502 | return DRM_FORMAT_XBGR2101010; | |
2503 | } | |
2504 | } | |
2505 | ||
bc8d7dff DL |
2506 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2507 | { | |
2508 | switch (format) { | |
2509 | case PLANE_CTL_FORMAT_RGB_565: | |
2510 | return DRM_FORMAT_RGB565; | |
2511 | default: | |
2512 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2513 | if (rgb_order) { | |
2514 | if (alpha) | |
2515 | return DRM_FORMAT_ABGR8888; | |
2516 | else | |
2517 | return DRM_FORMAT_XBGR8888; | |
2518 | } else { | |
2519 | if (alpha) | |
2520 | return DRM_FORMAT_ARGB8888; | |
2521 | else | |
2522 | return DRM_FORMAT_XRGB8888; | |
2523 | } | |
2524 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2525 | if (rgb_order) | |
2526 | return DRM_FORMAT_XBGR2101010; | |
2527 | else | |
2528 | return DRM_FORMAT_XRGB2101010; | |
2529 | } | |
2530 | } | |
2531 | ||
5724dbd1 | 2532 | static bool |
f6936e29 DV |
2533 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2534 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2535 | { |
2536 | struct drm_device *dev = crtc->base.dev; | |
2537 | struct drm_i915_gem_object *obj = NULL; | |
2538 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2539 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2540 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2541 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2542 | PAGE_SIZE); | |
2543 | ||
2544 | size_aligned -= base_aligned; | |
46f297fb | 2545 | |
ff2652ea CW |
2546 | if (plane_config->size == 0) |
2547 | return false; | |
2548 | ||
f37b5c2b DV |
2549 | obj = i915_gem_object_create_stolen_for_preallocated(dev, |
2550 | base_aligned, | |
2551 | base_aligned, | |
2552 | size_aligned); | |
46f297fb | 2553 | if (!obj) |
484b41dd | 2554 | return false; |
46f297fb | 2555 | |
49af449b DL |
2556 | obj->tiling_mode = plane_config->tiling; |
2557 | if (obj->tiling_mode == I915_TILING_X) | |
6bf129df | 2558 | obj->stride = fb->pitches[0]; |
46f297fb | 2559 | |
6bf129df DL |
2560 | mode_cmd.pixel_format = fb->pixel_format; |
2561 | mode_cmd.width = fb->width; | |
2562 | mode_cmd.height = fb->height; | |
2563 | mode_cmd.pitches[0] = fb->pitches[0]; | |
18c5247e DV |
2564 | mode_cmd.modifier[0] = fb->modifier[0]; |
2565 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; | |
46f297fb JB |
2566 | |
2567 | mutex_lock(&dev->struct_mutex); | |
6bf129df | 2568 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
484b41dd | 2569 | &mode_cmd, obj)) { |
46f297fb JB |
2570 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2571 | goto out_unref_obj; | |
2572 | } | |
46f297fb | 2573 | mutex_unlock(&dev->struct_mutex); |
484b41dd | 2574 | |
f6936e29 | 2575 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2576 | return true; |
46f297fb JB |
2577 | |
2578 | out_unref_obj: | |
2579 | drm_gem_object_unreference(&obj->base); | |
2580 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2581 | return false; |
2582 | } | |
2583 | ||
afd65eb4 MR |
2584 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2585 | static void | |
2586 | update_state_fb(struct drm_plane *plane) | |
2587 | { | |
2588 | if (plane->fb == plane->state->fb) | |
2589 | return; | |
2590 | ||
2591 | if (plane->state->fb) | |
2592 | drm_framebuffer_unreference(plane->state->fb); | |
2593 | plane->state->fb = plane->fb; | |
2594 | if (plane->state->fb) | |
2595 | drm_framebuffer_reference(plane->state->fb); | |
2596 | } | |
2597 | ||
5724dbd1 | 2598 | static void |
f6936e29 DV |
2599 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2600 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2601 | { |
2602 | struct drm_device *dev = intel_crtc->base.dev; | |
d9ceb816 | 2603 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd JB |
2604 | struct drm_crtc *c; |
2605 | struct intel_crtc *i; | |
2ff8fde1 | 2606 | struct drm_i915_gem_object *obj; |
88595ac9 DV |
2607 | struct drm_plane *primary = intel_crtc->base.primary; |
2608 | struct drm_framebuffer *fb; | |
484b41dd | 2609 | |
2d14030b | 2610 | if (!plane_config->fb) |
484b41dd JB |
2611 | return; |
2612 | ||
f6936e29 | 2613 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2614 | fb = &plane_config->fb->base; |
2615 | goto valid_fb; | |
f55548b5 | 2616 | } |
484b41dd | 2617 | |
2d14030b | 2618 | kfree(plane_config->fb); |
484b41dd JB |
2619 | |
2620 | /* | |
2621 | * Failed to alloc the obj, check to see if we should share | |
2622 | * an fb with another CRTC instead | |
2623 | */ | |
70e1e0ec | 2624 | for_each_crtc(dev, c) { |
484b41dd JB |
2625 | i = to_intel_crtc(c); |
2626 | ||
2627 | if (c == &intel_crtc->base) | |
2628 | continue; | |
2629 | ||
2ff8fde1 MR |
2630 | if (!i->active) |
2631 | continue; | |
2632 | ||
88595ac9 DV |
2633 | fb = c->primary->fb; |
2634 | if (!fb) | |
484b41dd JB |
2635 | continue; |
2636 | ||
88595ac9 | 2637 | obj = intel_fb_obj(fb); |
2ff8fde1 | 2638 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
88595ac9 DV |
2639 | drm_framebuffer_reference(fb); |
2640 | goto valid_fb; | |
484b41dd JB |
2641 | } |
2642 | } | |
88595ac9 DV |
2643 | |
2644 | return; | |
2645 | ||
2646 | valid_fb: | |
2647 | obj = intel_fb_obj(fb); | |
2648 | if (obj->tiling_mode != I915_TILING_NONE) | |
2649 | dev_priv->preserve_bios_swizzle = true; | |
2650 | ||
2651 | primary->fb = fb; | |
2652 | primary->state->crtc = &intel_crtc->base; | |
2653 | primary->crtc = &intel_crtc->base; | |
2654 | update_state_fb(primary); | |
2655 | obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe); | |
46f297fb JB |
2656 | } |
2657 | ||
29b9bde6 DV |
2658 | static void i9xx_update_primary_plane(struct drm_crtc *crtc, |
2659 | struct drm_framebuffer *fb, | |
2660 | int x, int y) | |
81255565 JB |
2661 | { |
2662 | struct drm_device *dev = crtc->dev; | |
2663 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2664 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
c9ba6fad | 2665 | struct drm_i915_gem_object *obj; |
81255565 | 2666 | int plane = intel_crtc->plane; |
e506a0c6 | 2667 | unsigned long linear_offset; |
81255565 | 2668 | u32 dspcntr; |
f45651ba | 2669 | u32 reg = DSPCNTR(plane); |
48404c1e | 2670 | int pixel_size; |
f45651ba | 2671 | |
fdd508a6 VS |
2672 | if (!intel_crtc->primary_enabled) { |
2673 | I915_WRITE(reg, 0); | |
2674 | if (INTEL_INFO(dev)->gen >= 4) | |
2675 | I915_WRITE(DSPSURF(plane), 0); | |
2676 | else | |
2677 | I915_WRITE(DSPADDR(plane), 0); | |
2678 | POSTING_READ(reg); | |
2679 | return; | |
2680 | } | |
2681 | ||
c9ba6fad VS |
2682 | obj = intel_fb_obj(fb); |
2683 | if (WARN_ON(obj == NULL)) | |
2684 | return; | |
2685 | ||
2686 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2687 | ||
f45651ba VS |
2688 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2689 | ||
fdd508a6 | 2690 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2691 | |
2692 | if (INTEL_INFO(dev)->gen < 4) { | |
2693 | if (intel_crtc->pipe == PIPE_B) | |
2694 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2695 | ||
2696 | /* pipesrc and dspsize control the size that is scaled from, | |
2697 | * which should always be the user's requested size. | |
2698 | */ | |
2699 | I915_WRITE(DSPSIZE(plane), | |
6e3c9717 ACO |
2700 | ((intel_crtc->config->pipe_src_h - 1) << 16) | |
2701 | (intel_crtc->config->pipe_src_w - 1)); | |
f45651ba | 2702 | I915_WRITE(DSPPOS(plane), 0); |
c14b0485 VS |
2703 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
2704 | I915_WRITE(PRIMSIZE(plane), | |
6e3c9717 ACO |
2705 | ((intel_crtc->config->pipe_src_h - 1) << 16) | |
2706 | (intel_crtc->config->pipe_src_w - 1)); | |
c14b0485 VS |
2707 | I915_WRITE(PRIMPOS(plane), 0); |
2708 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 2709 | } |
81255565 | 2710 | |
57779d06 VS |
2711 | switch (fb->pixel_format) { |
2712 | case DRM_FORMAT_C8: | |
81255565 JB |
2713 | dspcntr |= DISPPLANE_8BPP; |
2714 | break; | |
57779d06 VS |
2715 | case DRM_FORMAT_XRGB1555: |
2716 | case DRM_FORMAT_ARGB1555: | |
2717 | dspcntr |= DISPPLANE_BGRX555; | |
81255565 | 2718 | break; |
57779d06 VS |
2719 | case DRM_FORMAT_RGB565: |
2720 | dspcntr |= DISPPLANE_BGRX565; | |
2721 | break; | |
2722 | case DRM_FORMAT_XRGB8888: | |
2723 | case DRM_FORMAT_ARGB8888: | |
2724 | dspcntr |= DISPPLANE_BGRX888; | |
2725 | break; | |
2726 | case DRM_FORMAT_XBGR8888: | |
2727 | case DRM_FORMAT_ABGR8888: | |
2728 | dspcntr |= DISPPLANE_RGBX888; | |
2729 | break; | |
2730 | case DRM_FORMAT_XRGB2101010: | |
2731 | case DRM_FORMAT_ARGB2101010: | |
2732 | dspcntr |= DISPPLANE_BGRX101010; | |
2733 | break; | |
2734 | case DRM_FORMAT_XBGR2101010: | |
2735 | case DRM_FORMAT_ABGR2101010: | |
2736 | dspcntr |= DISPPLANE_RGBX101010; | |
81255565 JB |
2737 | break; |
2738 | default: | |
baba133a | 2739 | BUG(); |
81255565 | 2740 | } |
57779d06 | 2741 | |
f45651ba VS |
2742 | if (INTEL_INFO(dev)->gen >= 4 && |
2743 | obj->tiling_mode != I915_TILING_NONE) | |
2744 | dspcntr |= DISPPLANE_TILED; | |
81255565 | 2745 | |
de1aa629 VS |
2746 | if (IS_G4X(dev)) |
2747 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2748 | ||
b9897127 | 2749 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
81255565 | 2750 | |
c2c75131 DV |
2751 | if (INTEL_INFO(dev)->gen >= 4) { |
2752 | intel_crtc->dspaddr_offset = | |
bc752862 | 2753 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
b9897127 | 2754 | pixel_size, |
bc752862 | 2755 | fb->pitches[0]); |
c2c75131 DV |
2756 | linear_offset -= intel_crtc->dspaddr_offset; |
2757 | } else { | |
e506a0c6 | 2758 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2759 | } |
e506a0c6 | 2760 | |
8e7d688b | 2761 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2762 | dspcntr |= DISPPLANE_ROTATE_180; |
2763 | ||
6e3c9717 ACO |
2764 | x += (intel_crtc->config->pipe_src_w - 1); |
2765 | y += (intel_crtc->config->pipe_src_h - 1); | |
48404c1e SJ |
2766 | |
2767 | /* Finding the last pixel of the last line of the display | |
2768 | data and adding to linear_offset*/ | |
2769 | linear_offset += | |
6e3c9717 ACO |
2770 | (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
2771 | (intel_crtc->config->pipe_src_w - 1) * pixel_size; | |
48404c1e SJ |
2772 | } |
2773 | ||
2774 | I915_WRITE(reg, dspcntr); | |
2775 | ||
01f2c773 | 2776 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2777 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2778 | I915_WRITE(DSPSURF(plane), |
2779 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2780 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2781 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2782 | } else |
f343c5f6 | 2783 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2784 | POSTING_READ(reg); |
17638cd6 JB |
2785 | } |
2786 | ||
29b9bde6 DV |
2787 | static void ironlake_update_primary_plane(struct drm_crtc *crtc, |
2788 | struct drm_framebuffer *fb, | |
2789 | int x, int y) | |
17638cd6 JB |
2790 | { |
2791 | struct drm_device *dev = crtc->dev; | |
2792 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2793 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
c9ba6fad | 2794 | struct drm_i915_gem_object *obj; |
17638cd6 | 2795 | int plane = intel_crtc->plane; |
e506a0c6 | 2796 | unsigned long linear_offset; |
17638cd6 | 2797 | u32 dspcntr; |
f45651ba | 2798 | u32 reg = DSPCNTR(plane); |
48404c1e | 2799 | int pixel_size; |
f45651ba | 2800 | |
fdd508a6 VS |
2801 | if (!intel_crtc->primary_enabled) { |
2802 | I915_WRITE(reg, 0); | |
2803 | I915_WRITE(DSPSURF(plane), 0); | |
2804 | POSTING_READ(reg); | |
2805 | return; | |
2806 | } | |
2807 | ||
c9ba6fad VS |
2808 | obj = intel_fb_obj(fb); |
2809 | if (WARN_ON(obj == NULL)) | |
2810 | return; | |
2811 | ||
2812 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2813 | ||
f45651ba VS |
2814 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2815 | ||
fdd508a6 | 2816 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2817 | |
2818 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2819 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
17638cd6 | 2820 | |
57779d06 VS |
2821 | switch (fb->pixel_format) { |
2822 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2823 | dspcntr |= DISPPLANE_8BPP; |
2824 | break; | |
57779d06 VS |
2825 | case DRM_FORMAT_RGB565: |
2826 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2827 | break; |
57779d06 VS |
2828 | case DRM_FORMAT_XRGB8888: |
2829 | case DRM_FORMAT_ARGB8888: | |
2830 | dspcntr |= DISPPLANE_BGRX888; | |
2831 | break; | |
2832 | case DRM_FORMAT_XBGR8888: | |
2833 | case DRM_FORMAT_ABGR8888: | |
2834 | dspcntr |= DISPPLANE_RGBX888; | |
2835 | break; | |
2836 | case DRM_FORMAT_XRGB2101010: | |
2837 | case DRM_FORMAT_ARGB2101010: | |
2838 | dspcntr |= DISPPLANE_BGRX101010; | |
2839 | break; | |
2840 | case DRM_FORMAT_XBGR2101010: | |
2841 | case DRM_FORMAT_ABGR2101010: | |
2842 | dspcntr |= DISPPLANE_RGBX101010; | |
17638cd6 JB |
2843 | break; |
2844 | default: | |
baba133a | 2845 | BUG(); |
17638cd6 JB |
2846 | } |
2847 | ||
2848 | if (obj->tiling_mode != I915_TILING_NONE) | |
2849 | dspcntr |= DISPPLANE_TILED; | |
17638cd6 | 2850 | |
f45651ba | 2851 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
1f5d76db | 2852 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 2853 | |
b9897127 | 2854 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
c2c75131 | 2855 | intel_crtc->dspaddr_offset = |
bc752862 | 2856 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
b9897127 | 2857 | pixel_size, |
bc752862 | 2858 | fb->pitches[0]); |
c2c75131 | 2859 | linear_offset -= intel_crtc->dspaddr_offset; |
8e7d688b | 2860 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2861 | dspcntr |= DISPPLANE_ROTATE_180; |
2862 | ||
2863 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
6e3c9717 ACO |
2864 | x += (intel_crtc->config->pipe_src_w - 1); |
2865 | y += (intel_crtc->config->pipe_src_h - 1); | |
48404c1e SJ |
2866 | |
2867 | /* Finding the last pixel of the last line of the display | |
2868 | data and adding to linear_offset*/ | |
2869 | linear_offset += | |
6e3c9717 ACO |
2870 | (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
2871 | (intel_crtc->config->pipe_src_w - 1) * pixel_size; | |
48404c1e SJ |
2872 | } |
2873 | } | |
2874 | ||
2875 | I915_WRITE(reg, dspcntr); | |
17638cd6 | 2876 | |
01f2c773 | 2877 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2878 | I915_WRITE(DSPSURF(plane), |
2879 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2880 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2881 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2882 | } else { | |
2883 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2884 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2885 | } | |
17638cd6 | 2886 | POSTING_READ(reg); |
17638cd6 JB |
2887 | } |
2888 | ||
b321803d DL |
2889 | u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier, |
2890 | uint32_t pixel_format) | |
2891 | { | |
2892 | u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8; | |
2893 | ||
2894 | /* | |
2895 | * The stride is either expressed as a multiple of 64 bytes | |
2896 | * chunks for linear buffers or in number of tiles for tiled | |
2897 | * buffers. | |
2898 | */ | |
2899 | switch (fb_modifier) { | |
2900 | case DRM_FORMAT_MOD_NONE: | |
2901 | return 64; | |
2902 | case I915_FORMAT_MOD_X_TILED: | |
2903 | if (INTEL_INFO(dev)->gen == 2) | |
2904 | return 128; | |
2905 | return 512; | |
2906 | case I915_FORMAT_MOD_Y_TILED: | |
2907 | /* No need to check for old gens and Y tiling since this is | |
2908 | * about the display engine and those will be blocked before | |
2909 | * we get here. | |
2910 | */ | |
2911 | return 128; | |
2912 | case I915_FORMAT_MOD_Yf_TILED: | |
2913 | if (bits_per_pixel == 8) | |
2914 | return 64; | |
2915 | else | |
2916 | return 128; | |
2917 | default: | |
2918 | MISSING_CASE(fb_modifier); | |
2919 | return 64; | |
2920 | } | |
2921 | } | |
2922 | ||
121920fa TU |
2923 | unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane, |
2924 | struct drm_i915_gem_object *obj) | |
2925 | { | |
9abc4648 | 2926 | const struct i915_ggtt_view *view = &i915_ggtt_view_normal; |
121920fa TU |
2927 | |
2928 | if (intel_rotation_90_or_270(intel_plane->base.state->rotation)) | |
9abc4648 | 2929 | view = &i915_ggtt_view_rotated; |
121920fa TU |
2930 | |
2931 | return i915_gem_obj_ggtt_offset_view(obj, view); | |
2932 | } | |
2933 | ||
a1b2278e CK |
2934 | /* |
2935 | * This function detaches (aka. unbinds) unused scalers in hardware | |
2936 | */ | |
2937 | void skl_detach_scalers(struct intel_crtc *intel_crtc) | |
2938 | { | |
2939 | struct drm_device *dev; | |
2940 | struct drm_i915_private *dev_priv; | |
2941 | struct intel_crtc_scaler_state *scaler_state; | |
2942 | int i; | |
2943 | ||
2944 | if (!intel_crtc || !intel_crtc->config) | |
2945 | return; | |
2946 | ||
2947 | dev = intel_crtc->base.dev; | |
2948 | dev_priv = dev->dev_private; | |
2949 | scaler_state = &intel_crtc->config->scaler_state; | |
2950 | ||
2951 | /* loop through and disable scalers that aren't in use */ | |
2952 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
2953 | if (!scaler_state->scalers[i].in_use) { | |
2954 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0); | |
2955 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0); | |
2956 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0); | |
2957 | DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n", | |
2958 | intel_crtc->base.base.id, intel_crtc->pipe, i); | |
2959 | } | |
2960 | } | |
2961 | } | |
2962 | ||
70d21f0e DL |
2963 | static void skylake_update_primary_plane(struct drm_crtc *crtc, |
2964 | struct drm_framebuffer *fb, | |
2965 | int x, int y) | |
2966 | { | |
2967 | struct drm_device *dev = crtc->dev; | |
2968 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2969 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
70d21f0e DL |
2970 | struct drm_i915_gem_object *obj; |
2971 | int pipe = intel_crtc->pipe; | |
3b7a5119 SJ |
2972 | u32 plane_ctl, stride_div, stride; |
2973 | u32 tile_height, plane_offset, plane_size; | |
2974 | unsigned int rotation; | |
2975 | int x_offset, y_offset; | |
121920fa | 2976 | unsigned long surf_addr; |
3b7a5119 | 2977 | struct drm_plane *plane; |
70d21f0e DL |
2978 | |
2979 | if (!intel_crtc->primary_enabled) { | |
2980 | I915_WRITE(PLANE_CTL(pipe, 0), 0); | |
2981 | I915_WRITE(PLANE_SURF(pipe, 0), 0); | |
2982 | POSTING_READ(PLANE_CTL(pipe, 0)); | |
2983 | return; | |
2984 | } | |
2985 | ||
2986 | plane_ctl = PLANE_CTL_ENABLE | | |
2987 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
2988 | PLANE_CTL_PIPE_CSC_ENABLE; | |
2989 | ||
2990 | switch (fb->pixel_format) { | |
2991 | case DRM_FORMAT_RGB565: | |
2992 | plane_ctl |= PLANE_CTL_FORMAT_RGB_565; | |
2993 | break; | |
2994 | case DRM_FORMAT_XRGB8888: | |
2995 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888; | |
2996 | break; | |
f75fb42a JN |
2997 | case DRM_FORMAT_ARGB8888: |
2998 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888; | |
2999 | plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY; | |
3000 | break; | |
70d21f0e DL |
3001 | case DRM_FORMAT_XBGR8888: |
3002 | plane_ctl |= PLANE_CTL_ORDER_RGBX; | |
3003 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888; | |
3004 | break; | |
f75fb42a JN |
3005 | case DRM_FORMAT_ABGR8888: |
3006 | plane_ctl |= PLANE_CTL_ORDER_RGBX; | |
3007 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888; | |
3008 | plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY; | |
3009 | break; | |
70d21f0e DL |
3010 | case DRM_FORMAT_XRGB2101010: |
3011 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010; | |
3012 | break; | |
3013 | case DRM_FORMAT_XBGR2101010: | |
3014 | plane_ctl |= PLANE_CTL_ORDER_RGBX; | |
3015 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010; | |
3016 | break; | |
3017 | default: | |
3018 | BUG(); | |
3019 | } | |
3020 | ||
30af77c4 DV |
3021 | switch (fb->modifier[0]) { |
3022 | case DRM_FORMAT_MOD_NONE: | |
70d21f0e | 3023 | break; |
30af77c4 | 3024 | case I915_FORMAT_MOD_X_TILED: |
70d21f0e | 3025 | plane_ctl |= PLANE_CTL_TILED_X; |
b321803d DL |
3026 | break; |
3027 | case I915_FORMAT_MOD_Y_TILED: | |
3028 | plane_ctl |= PLANE_CTL_TILED_Y; | |
3029 | break; | |
3030 | case I915_FORMAT_MOD_Yf_TILED: | |
3031 | plane_ctl |= PLANE_CTL_TILED_YF; | |
70d21f0e DL |
3032 | break; |
3033 | default: | |
b321803d | 3034 | MISSING_CASE(fb->modifier[0]); |
70d21f0e DL |
3035 | } |
3036 | ||
3037 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
3b7a5119 SJ |
3038 | |
3039 | plane = crtc->primary; | |
3040 | rotation = plane->state->rotation; | |
3041 | switch (rotation) { | |
3042 | case BIT(DRM_ROTATE_90): | |
3043 | plane_ctl |= PLANE_CTL_ROTATE_90; | |
3044 | break; | |
3045 | ||
3046 | case BIT(DRM_ROTATE_180): | |
1447dde0 | 3047 | plane_ctl |= PLANE_CTL_ROTATE_180; |
3b7a5119 SJ |
3048 | break; |
3049 | ||
3050 | case BIT(DRM_ROTATE_270): | |
3051 | plane_ctl |= PLANE_CTL_ROTATE_270; | |
3052 | break; | |
3053 | } | |
70d21f0e | 3054 | |
b321803d DL |
3055 | obj = intel_fb_obj(fb); |
3056 | stride_div = intel_fb_stride_alignment(dev, fb->modifier[0], | |
3057 | fb->pixel_format); | |
3b7a5119 SJ |
3058 | surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj); |
3059 | ||
3060 | if (intel_rotation_90_or_270(rotation)) { | |
3061 | /* stride = Surface height in tiles */ | |
3062 | tile_height = intel_tile_height(dev, fb->bits_per_pixel, | |
3063 | fb->modifier[0]); | |
3064 | stride = DIV_ROUND_UP(fb->height, tile_height); | |
3065 | x_offset = stride * tile_height - y - (plane->state->src_h >> 16); | |
3066 | y_offset = x; | |
3067 | plane_size = ((plane->state->src_w >> 16) - 1) << 16 | | |
3068 | ((plane->state->src_h >> 16) - 1); | |
3069 | } else { | |
3070 | stride = fb->pitches[0] / stride_div; | |
3071 | x_offset = x; | |
3072 | y_offset = y; | |
3073 | plane_size = ((plane->state->src_h >> 16) - 1) << 16 | | |
3074 | ((plane->state->src_w >> 16) - 1); | |
3075 | } | |
3076 | plane_offset = y_offset << 16 | x_offset; | |
b321803d | 3077 | |
70d21f0e | 3078 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); |
70d21f0e | 3079 | I915_WRITE(PLANE_POS(pipe, 0), 0); |
3b7a5119 SJ |
3080 | I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset); |
3081 | I915_WRITE(PLANE_SIZE(pipe, 0), plane_size); | |
3082 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
121920fa | 3083 | I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); |
70d21f0e DL |
3084 | |
3085 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3086 | } | |
3087 | ||
17638cd6 JB |
3088 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3089 | static int | |
3090 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3091 | int x, int y, enum mode_set_atomic state) | |
3092 | { | |
3093 | struct drm_device *dev = crtc->dev; | |
3094 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 3095 | |
6b8e6ed0 CW |
3096 | if (dev_priv->display.disable_fbc) |
3097 | dev_priv->display.disable_fbc(dev); | |
81255565 | 3098 | |
29b9bde6 DV |
3099 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
3100 | ||
3101 | return 0; | |
81255565 JB |
3102 | } |
3103 | ||
7514747d | 3104 | static void intel_complete_page_flips(struct drm_device *dev) |
96a02917 | 3105 | { |
96a02917 VS |
3106 | struct drm_crtc *crtc; |
3107 | ||
70e1e0ec | 3108 | for_each_crtc(dev, crtc) { |
96a02917 VS |
3109 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3110 | enum plane plane = intel_crtc->plane; | |
3111 | ||
3112 | intel_prepare_page_flip(dev, plane); | |
3113 | intel_finish_page_flip_plane(dev, plane); | |
3114 | } | |
7514747d VS |
3115 | } |
3116 | ||
3117 | static void intel_update_primary_planes(struct drm_device *dev) | |
3118 | { | |
3119 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3120 | struct drm_crtc *crtc; | |
96a02917 | 3121 | |
70e1e0ec | 3122 | for_each_crtc(dev, crtc) { |
96a02917 VS |
3123 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3124 | ||
51fd371b | 3125 | drm_modeset_lock(&crtc->mutex, NULL); |
947fdaad CW |
3126 | /* |
3127 | * FIXME: Once we have proper support for primary planes (and | |
3128 | * disabling them without disabling the entire crtc) allow again | |
66e514c1 | 3129 | * a NULL crtc->primary->fb. |
947fdaad | 3130 | */ |
f4510a27 | 3131 | if (intel_crtc->active && crtc->primary->fb) |
262ca2b0 | 3132 | dev_priv->display.update_primary_plane(crtc, |
66e514c1 | 3133 | crtc->primary->fb, |
262ca2b0 MR |
3134 | crtc->x, |
3135 | crtc->y); | |
51fd371b | 3136 | drm_modeset_unlock(&crtc->mutex); |
96a02917 VS |
3137 | } |
3138 | } | |
3139 | ||
7514747d VS |
3140 | void intel_prepare_reset(struct drm_device *dev) |
3141 | { | |
f98ce92f VS |
3142 | struct drm_i915_private *dev_priv = to_i915(dev); |
3143 | struct intel_crtc *crtc; | |
3144 | ||
7514747d VS |
3145 | /* no reset support for gen2 */ |
3146 | if (IS_GEN2(dev)) | |
3147 | return; | |
3148 | ||
3149 | /* reset doesn't touch the display */ | |
3150 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
3151 | return; | |
3152 | ||
3153 | drm_modeset_lock_all(dev); | |
f98ce92f VS |
3154 | |
3155 | /* | |
3156 | * Disabling the crtcs gracefully seems nicer. Also the | |
3157 | * g33 docs say we should at least disable all the planes. | |
3158 | */ | |
3159 | for_each_intel_crtc(dev, crtc) { | |
3160 | if (crtc->active) | |
3161 | dev_priv->display.crtc_disable(&crtc->base); | |
3162 | } | |
7514747d VS |
3163 | } |
3164 | ||
3165 | void intel_finish_reset(struct drm_device *dev) | |
3166 | { | |
3167 | struct drm_i915_private *dev_priv = to_i915(dev); | |
3168 | ||
3169 | /* | |
3170 | * Flips in the rings will be nuked by the reset, | |
3171 | * so complete all pending flips so that user space | |
3172 | * will get its events and not get stuck. | |
3173 | */ | |
3174 | intel_complete_page_flips(dev); | |
3175 | ||
3176 | /* no reset support for gen2 */ | |
3177 | if (IS_GEN2(dev)) | |
3178 | return; | |
3179 | ||
3180 | /* reset doesn't touch the display */ | |
3181 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) { | |
3182 | /* | |
3183 | * Flips in the rings have been nuked by the reset, | |
3184 | * so update the base address of all primary | |
3185 | * planes to the the last fb to make sure we're | |
3186 | * showing the correct fb after a reset. | |
3187 | */ | |
3188 | intel_update_primary_planes(dev); | |
3189 | return; | |
3190 | } | |
3191 | ||
3192 | /* | |
3193 | * The display has been reset as well, | |
3194 | * so need a full re-initialization. | |
3195 | */ | |
3196 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3197 | intel_runtime_pm_enable_interrupts(dev_priv); | |
3198 | ||
3199 | intel_modeset_init_hw(dev); | |
3200 | ||
3201 | spin_lock_irq(&dev_priv->irq_lock); | |
3202 | if (dev_priv->display.hpd_irq_setup) | |
3203 | dev_priv->display.hpd_irq_setup(dev); | |
3204 | spin_unlock_irq(&dev_priv->irq_lock); | |
3205 | ||
3206 | intel_modeset_setup_hw_state(dev, true); | |
3207 | ||
3208 | intel_hpd_init(dev_priv); | |
3209 | ||
3210 | drm_modeset_unlock_all(dev); | |
3211 | } | |
3212 | ||
14667a4b CW |
3213 | static int |
3214 | intel_finish_fb(struct drm_framebuffer *old_fb) | |
3215 | { | |
2ff8fde1 | 3216 | struct drm_i915_gem_object *obj = intel_fb_obj(old_fb); |
14667a4b CW |
3217 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
3218 | bool was_interruptible = dev_priv->mm.interruptible; | |
3219 | int ret; | |
3220 | ||
14667a4b CW |
3221 | /* Big Hammer, we also need to ensure that any pending |
3222 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
3223 | * current scanout is retired before unpinning the old | |
3224 | * framebuffer. | |
3225 | * | |
3226 | * This should only fail upon a hung GPU, in which case we | |
3227 | * can safely continue. | |
3228 | */ | |
3229 | dev_priv->mm.interruptible = false; | |
3230 | ret = i915_gem_object_finish_gpu(obj); | |
3231 | dev_priv->mm.interruptible = was_interruptible; | |
3232 | ||
3233 | return ret; | |
3234 | } | |
3235 | ||
7d5e3799 CW |
3236 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3237 | { | |
3238 | struct drm_device *dev = crtc->dev; | |
3239 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3240 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7d5e3799 CW |
3241 | bool pending; |
3242 | ||
3243 | if (i915_reset_in_progress(&dev_priv->gpu_error) || | |
3244 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
3245 | return false; | |
3246 | ||
5e2d7afc | 3247 | spin_lock_irq(&dev->event_lock); |
7d5e3799 | 3248 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
5e2d7afc | 3249 | spin_unlock_irq(&dev->event_lock); |
7d5e3799 CW |
3250 | |
3251 | return pending; | |
3252 | } | |
3253 | ||
e30e8f75 GP |
3254 | static void intel_update_pipe_size(struct intel_crtc *crtc) |
3255 | { | |
3256 | struct drm_device *dev = crtc->base.dev; | |
3257 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3258 | const struct drm_display_mode *adjusted_mode; | |
3259 | ||
3260 | if (!i915.fastboot) | |
3261 | return; | |
3262 | ||
3263 | /* | |
3264 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3265 | * that in compute_mode_changes we check the native mode (not the pfit | |
3266 | * mode) to see if we can flip rather than do a full mode set. In the | |
3267 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3268 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3269 | * sized surface. | |
3270 | * | |
3271 | * To fix this properly, we need to hoist the checks up into | |
3272 | * compute_mode_changes (or above), check the actual pfit state and | |
3273 | * whether the platform allows pfit disable with pipe active, and only | |
3274 | * then update the pipesrc and pfit state, even on the flip path. | |
3275 | */ | |
3276 | ||
6e3c9717 | 3277 | adjusted_mode = &crtc->config->base.adjusted_mode; |
e30e8f75 GP |
3278 | |
3279 | I915_WRITE(PIPESRC(crtc->pipe), | |
3280 | ((adjusted_mode->crtc_hdisplay - 1) << 16) | | |
3281 | (adjusted_mode->crtc_vdisplay - 1)); | |
6e3c9717 | 3282 | if (!crtc->config->pch_pfit.enabled && |
409ee761 ACO |
3283 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
3284 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
e30e8f75 GP |
3285 | I915_WRITE(PF_CTL(crtc->pipe), 0); |
3286 | I915_WRITE(PF_WIN_POS(crtc->pipe), 0); | |
3287 | I915_WRITE(PF_WIN_SZ(crtc->pipe), 0); | |
3288 | } | |
6e3c9717 ACO |
3289 | crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay; |
3290 | crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay; | |
e30e8f75 GP |
3291 | } |
3292 | ||
5e84e1a4 ZW |
3293 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
3294 | { | |
3295 | struct drm_device *dev = crtc->dev; | |
3296 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3297 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3298 | int pipe = intel_crtc->pipe; | |
3299 | u32 reg, temp; | |
3300 | ||
3301 | /* enable normal train */ | |
3302 | reg = FDI_TX_CTL(pipe); | |
3303 | temp = I915_READ(reg); | |
61e499bf | 3304 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
3305 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3306 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3307 | } else { |
3308 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3309 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3310 | } |
5e84e1a4 ZW |
3311 | I915_WRITE(reg, temp); |
3312 | ||
3313 | reg = FDI_RX_CTL(pipe); | |
3314 | temp = I915_READ(reg); | |
3315 | if (HAS_PCH_CPT(dev)) { | |
3316 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3317 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3318 | } else { | |
3319 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3320 | temp |= FDI_LINK_TRAIN_NONE; | |
3321 | } | |
3322 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3323 | ||
3324 | /* wait one idle pattern time */ | |
3325 | POSTING_READ(reg); | |
3326 | udelay(1000); | |
357555c0 JB |
3327 | |
3328 | /* IVB wants error correction enabled */ | |
3329 | if (IS_IVYBRIDGE(dev)) | |
3330 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
3331 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3332 | } |
3333 | ||
8db9d77b ZW |
3334 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3335 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3336 | { | |
3337 | struct drm_device *dev = crtc->dev; | |
3338 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3339 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3340 | int pipe = intel_crtc->pipe; | |
5eddb70b | 3341 | u32 reg, temp, tries; |
8db9d77b | 3342 | |
1c8562f6 | 3343 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3344 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3345 | |
e1a44743 AJ |
3346 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3347 | for train result */ | |
5eddb70b CW |
3348 | reg = FDI_RX_IMR(pipe); |
3349 | temp = I915_READ(reg); | |
e1a44743 AJ |
3350 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3351 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3352 | I915_WRITE(reg, temp); |
3353 | I915_READ(reg); | |
e1a44743 AJ |
3354 | udelay(150); |
3355 | ||
8db9d77b | 3356 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3357 | reg = FDI_TX_CTL(pipe); |
3358 | temp = I915_READ(reg); | |
627eb5a3 | 3359 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3360 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3361 | temp &= ~FDI_LINK_TRAIN_NONE; |
3362 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3363 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3364 | |
5eddb70b CW |
3365 | reg = FDI_RX_CTL(pipe); |
3366 | temp = I915_READ(reg); | |
8db9d77b ZW |
3367 | temp &= ~FDI_LINK_TRAIN_NONE; |
3368 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3369 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3370 | ||
3371 | POSTING_READ(reg); | |
8db9d77b ZW |
3372 | udelay(150); |
3373 | ||
5b2adf89 | 3374 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3375 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3376 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3377 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3378 | |
5eddb70b | 3379 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3380 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3381 | temp = I915_READ(reg); |
8db9d77b ZW |
3382 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3383 | ||
3384 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3385 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3386 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3387 | break; |
3388 | } | |
8db9d77b | 3389 | } |
e1a44743 | 3390 | if (tries == 5) |
5eddb70b | 3391 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3392 | |
3393 | /* Train 2 */ | |
5eddb70b CW |
3394 | reg = FDI_TX_CTL(pipe); |
3395 | temp = I915_READ(reg); | |
8db9d77b ZW |
3396 | temp &= ~FDI_LINK_TRAIN_NONE; |
3397 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3398 | I915_WRITE(reg, temp); |
8db9d77b | 3399 | |
5eddb70b CW |
3400 | reg = FDI_RX_CTL(pipe); |
3401 | temp = I915_READ(reg); | |
8db9d77b ZW |
3402 | temp &= ~FDI_LINK_TRAIN_NONE; |
3403 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3404 | I915_WRITE(reg, temp); |
8db9d77b | 3405 | |
5eddb70b CW |
3406 | POSTING_READ(reg); |
3407 | udelay(150); | |
8db9d77b | 3408 | |
5eddb70b | 3409 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3410 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3411 | temp = I915_READ(reg); |
8db9d77b ZW |
3412 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3413 | ||
3414 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3415 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3416 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3417 | break; | |
3418 | } | |
8db9d77b | 3419 | } |
e1a44743 | 3420 | if (tries == 5) |
5eddb70b | 3421 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3422 | |
3423 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3424 | |
8db9d77b ZW |
3425 | } |
3426 | ||
0206e353 | 3427 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3428 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3429 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3430 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3431 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3432 | }; | |
3433 | ||
3434 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3435 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3436 | { | |
3437 | struct drm_device *dev = crtc->dev; | |
3438 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3439 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3440 | int pipe = intel_crtc->pipe; | |
fa37d39e | 3441 | u32 reg, temp, i, retry; |
8db9d77b | 3442 | |
e1a44743 AJ |
3443 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3444 | for train result */ | |
5eddb70b CW |
3445 | reg = FDI_RX_IMR(pipe); |
3446 | temp = I915_READ(reg); | |
e1a44743 AJ |
3447 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3448 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3449 | I915_WRITE(reg, temp); |
3450 | ||
3451 | POSTING_READ(reg); | |
e1a44743 AJ |
3452 | udelay(150); |
3453 | ||
8db9d77b | 3454 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3455 | reg = FDI_TX_CTL(pipe); |
3456 | temp = I915_READ(reg); | |
627eb5a3 | 3457 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3458 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3459 | temp &= ~FDI_LINK_TRAIN_NONE; |
3460 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3461 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3462 | /* SNB-B */ | |
3463 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3464 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3465 | |
d74cf324 DV |
3466 | I915_WRITE(FDI_RX_MISC(pipe), |
3467 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3468 | ||
5eddb70b CW |
3469 | reg = FDI_RX_CTL(pipe); |
3470 | temp = I915_READ(reg); | |
8db9d77b ZW |
3471 | if (HAS_PCH_CPT(dev)) { |
3472 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3473 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3474 | } else { | |
3475 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3476 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3477 | } | |
5eddb70b CW |
3478 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3479 | ||
3480 | POSTING_READ(reg); | |
8db9d77b ZW |
3481 | udelay(150); |
3482 | ||
0206e353 | 3483 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3484 | reg = FDI_TX_CTL(pipe); |
3485 | temp = I915_READ(reg); | |
8db9d77b ZW |
3486 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3487 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3488 | I915_WRITE(reg, temp); |
3489 | ||
3490 | POSTING_READ(reg); | |
8db9d77b ZW |
3491 | udelay(500); |
3492 | ||
fa37d39e SP |
3493 | for (retry = 0; retry < 5; retry++) { |
3494 | reg = FDI_RX_IIR(pipe); | |
3495 | temp = I915_READ(reg); | |
3496 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3497 | if (temp & FDI_RX_BIT_LOCK) { | |
3498 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3499 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3500 | break; | |
3501 | } | |
3502 | udelay(50); | |
8db9d77b | 3503 | } |
fa37d39e SP |
3504 | if (retry < 5) |
3505 | break; | |
8db9d77b ZW |
3506 | } |
3507 | if (i == 4) | |
5eddb70b | 3508 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3509 | |
3510 | /* Train 2 */ | |
5eddb70b CW |
3511 | reg = FDI_TX_CTL(pipe); |
3512 | temp = I915_READ(reg); | |
8db9d77b ZW |
3513 | temp &= ~FDI_LINK_TRAIN_NONE; |
3514 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3515 | if (IS_GEN6(dev)) { | |
3516 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3517 | /* SNB-B */ | |
3518 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3519 | } | |
5eddb70b | 3520 | I915_WRITE(reg, temp); |
8db9d77b | 3521 | |
5eddb70b CW |
3522 | reg = FDI_RX_CTL(pipe); |
3523 | temp = I915_READ(reg); | |
8db9d77b ZW |
3524 | if (HAS_PCH_CPT(dev)) { |
3525 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3526 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3527 | } else { | |
3528 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3529 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3530 | } | |
5eddb70b CW |
3531 | I915_WRITE(reg, temp); |
3532 | ||
3533 | POSTING_READ(reg); | |
8db9d77b ZW |
3534 | udelay(150); |
3535 | ||
0206e353 | 3536 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3537 | reg = FDI_TX_CTL(pipe); |
3538 | temp = I915_READ(reg); | |
8db9d77b ZW |
3539 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3540 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3541 | I915_WRITE(reg, temp); |
3542 | ||
3543 | POSTING_READ(reg); | |
8db9d77b ZW |
3544 | udelay(500); |
3545 | ||
fa37d39e SP |
3546 | for (retry = 0; retry < 5; retry++) { |
3547 | reg = FDI_RX_IIR(pipe); | |
3548 | temp = I915_READ(reg); | |
3549 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3550 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3551 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3552 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3553 | break; | |
3554 | } | |
3555 | udelay(50); | |
8db9d77b | 3556 | } |
fa37d39e SP |
3557 | if (retry < 5) |
3558 | break; | |
8db9d77b ZW |
3559 | } |
3560 | if (i == 4) | |
5eddb70b | 3561 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3562 | |
3563 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3564 | } | |
3565 | ||
357555c0 JB |
3566 | /* Manual link training for Ivy Bridge A0 parts */ |
3567 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3568 | { | |
3569 | struct drm_device *dev = crtc->dev; | |
3570 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3571 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3572 | int pipe = intel_crtc->pipe; | |
139ccd3f | 3573 | u32 reg, temp, i, j; |
357555c0 JB |
3574 | |
3575 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3576 | for train result */ | |
3577 | reg = FDI_RX_IMR(pipe); | |
3578 | temp = I915_READ(reg); | |
3579 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3580 | temp &= ~FDI_RX_BIT_LOCK; | |
3581 | I915_WRITE(reg, temp); | |
3582 | ||
3583 | POSTING_READ(reg); | |
3584 | udelay(150); | |
3585 | ||
01a415fd DV |
3586 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3587 | I915_READ(FDI_RX_IIR(pipe))); | |
3588 | ||
139ccd3f JB |
3589 | /* Try each vswing and preemphasis setting twice before moving on */ |
3590 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3591 | /* disable first in case we need to retry */ | |
3592 | reg = FDI_TX_CTL(pipe); | |
3593 | temp = I915_READ(reg); | |
3594 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3595 | temp &= ~FDI_TX_ENABLE; | |
3596 | I915_WRITE(reg, temp); | |
357555c0 | 3597 | |
139ccd3f JB |
3598 | reg = FDI_RX_CTL(pipe); |
3599 | temp = I915_READ(reg); | |
3600 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3601 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3602 | temp &= ~FDI_RX_ENABLE; | |
3603 | I915_WRITE(reg, temp); | |
357555c0 | 3604 | |
139ccd3f | 3605 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3606 | reg = FDI_TX_CTL(pipe); |
3607 | temp = I915_READ(reg); | |
139ccd3f | 3608 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3609 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
139ccd3f | 3610 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 3611 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3612 | temp |= snb_b_fdi_train_param[j/2]; |
3613 | temp |= FDI_COMPOSITE_SYNC; | |
3614 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3615 | |
139ccd3f JB |
3616 | I915_WRITE(FDI_RX_MISC(pipe), |
3617 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3618 | |
139ccd3f | 3619 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3620 | temp = I915_READ(reg); |
139ccd3f JB |
3621 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3622 | temp |= FDI_COMPOSITE_SYNC; | |
3623 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3624 | |
139ccd3f JB |
3625 | POSTING_READ(reg); |
3626 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3627 | |
139ccd3f JB |
3628 | for (i = 0; i < 4; i++) { |
3629 | reg = FDI_RX_IIR(pipe); | |
3630 | temp = I915_READ(reg); | |
3631 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3632 | |
139ccd3f JB |
3633 | if (temp & FDI_RX_BIT_LOCK || |
3634 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3635 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3636 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3637 | i); | |
3638 | break; | |
3639 | } | |
3640 | udelay(1); /* should be 0.5us */ | |
3641 | } | |
3642 | if (i == 4) { | |
3643 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3644 | continue; | |
3645 | } | |
357555c0 | 3646 | |
139ccd3f | 3647 | /* Train 2 */ |
357555c0 JB |
3648 | reg = FDI_TX_CTL(pipe); |
3649 | temp = I915_READ(reg); | |
139ccd3f JB |
3650 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3651 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3652 | I915_WRITE(reg, temp); | |
3653 | ||
3654 | reg = FDI_RX_CTL(pipe); | |
3655 | temp = I915_READ(reg); | |
3656 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3657 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3658 | I915_WRITE(reg, temp); |
3659 | ||
3660 | POSTING_READ(reg); | |
139ccd3f | 3661 | udelay(2); /* should be 1.5us */ |
357555c0 | 3662 | |
139ccd3f JB |
3663 | for (i = 0; i < 4; i++) { |
3664 | reg = FDI_RX_IIR(pipe); | |
3665 | temp = I915_READ(reg); | |
3666 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3667 | |
139ccd3f JB |
3668 | if (temp & FDI_RX_SYMBOL_LOCK || |
3669 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3670 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3671 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3672 | i); | |
3673 | goto train_done; | |
3674 | } | |
3675 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3676 | } |
139ccd3f JB |
3677 | if (i == 4) |
3678 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3679 | } |
357555c0 | 3680 | |
139ccd3f | 3681 | train_done: |
357555c0 JB |
3682 | DRM_DEBUG_KMS("FDI train done.\n"); |
3683 | } | |
3684 | ||
88cefb6c | 3685 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3686 | { |
88cefb6c | 3687 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3688 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3689 | int pipe = intel_crtc->pipe; |
5eddb70b | 3690 | u32 reg, temp; |
79e53945 | 3691 | |
c64e311e | 3692 | |
c98e9dcf | 3693 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3694 | reg = FDI_RX_CTL(pipe); |
3695 | temp = I915_READ(reg); | |
627eb5a3 | 3696 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 3697 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 3698 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3699 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3700 | ||
3701 | POSTING_READ(reg); | |
c98e9dcf JB |
3702 | udelay(200); |
3703 | ||
3704 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3705 | temp = I915_READ(reg); |
3706 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3707 | ||
3708 | POSTING_READ(reg); | |
c98e9dcf JB |
3709 | udelay(200); |
3710 | ||
20749730 PZ |
3711 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3712 | reg = FDI_TX_CTL(pipe); | |
3713 | temp = I915_READ(reg); | |
3714 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3715 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3716 | |
20749730 PZ |
3717 | POSTING_READ(reg); |
3718 | udelay(100); | |
6be4a607 | 3719 | } |
0e23b99d JB |
3720 | } |
3721 | ||
88cefb6c DV |
3722 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3723 | { | |
3724 | struct drm_device *dev = intel_crtc->base.dev; | |
3725 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3726 | int pipe = intel_crtc->pipe; | |
3727 | u32 reg, temp; | |
3728 | ||
3729 | /* Switch from PCDclk to Rawclk */ | |
3730 | reg = FDI_RX_CTL(pipe); | |
3731 | temp = I915_READ(reg); | |
3732 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3733 | ||
3734 | /* Disable CPU FDI TX PLL */ | |
3735 | reg = FDI_TX_CTL(pipe); | |
3736 | temp = I915_READ(reg); | |
3737 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3738 | ||
3739 | POSTING_READ(reg); | |
3740 | udelay(100); | |
3741 | ||
3742 | reg = FDI_RX_CTL(pipe); | |
3743 | temp = I915_READ(reg); | |
3744 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3745 | ||
3746 | /* Wait for the clocks to turn off. */ | |
3747 | POSTING_READ(reg); | |
3748 | udelay(100); | |
3749 | } | |
3750 | ||
0fc932b8 JB |
3751 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3752 | { | |
3753 | struct drm_device *dev = crtc->dev; | |
3754 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3755 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3756 | int pipe = intel_crtc->pipe; | |
3757 | u32 reg, temp; | |
3758 | ||
3759 | /* disable CPU FDI tx and PCH FDI rx */ | |
3760 | reg = FDI_TX_CTL(pipe); | |
3761 | temp = I915_READ(reg); | |
3762 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3763 | POSTING_READ(reg); | |
3764 | ||
3765 | reg = FDI_RX_CTL(pipe); | |
3766 | temp = I915_READ(reg); | |
3767 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3768 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3769 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3770 | ||
3771 | POSTING_READ(reg); | |
3772 | udelay(100); | |
3773 | ||
3774 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3775 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3776 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3777 | |
3778 | /* still set train pattern 1 */ | |
3779 | reg = FDI_TX_CTL(pipe); | |
3780 | temp = I915_READ(reg); | |
3781 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3782 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3783 | I915_WRITE(reg, temp); | |
3784 | ||
3785 | reg = FDI_RX_CTL(pipe); | |
3786 | temp = I915_READ(reg); | |
3787 | if (HAS_PCH_CPT(dev)) { | |
3788 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3789 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3790 | } else { | |
3791 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3792 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3793 | } | |
3794 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3795 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3796 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3797 | I915_WRITE(reg, temp); |
3798 | ||
3799 | POSTING_READ(reg); | |
3800 | udelay(100); | |
3801 | } | |
3802 | ||
5dce5b93 CW |
3803 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3804 | { | |
3805 | struct intel_crtc *crtc; | |
3806 | ||
3807 | /* Note that we don't need to be called with mode_config.lock here | |
3808 | * as our list of CRTC objects is static for the lifetime of the | |
3809 | * device and so cannot disappear as we iterate. Similarly, we can | |
3810 | * happily treat the predicates as racy, atomic checks as userspace | |
3811 | * cannot claim and pin a new fb without at least acquring the | |
3812 | * struct_mutex and so serialising with us. | |
3813 | */ | |
d3fcc808 | 3814 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3815 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3816 | continue; | |
3817 | ||
3818 | if (crtc->unpin_work) | |
3819 | intel_wait_for_vblank(dev, crtc->pipe); | |
3820 | ||
3821 | return true; | |
3822 | } | |
3823 | ||
3824 | return false; | |
3825 | } | |
3826 | ||
d6bbafa1 CW |
3827 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
3828 | { | |
3829 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
3830 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
3831 | ||
3832 | /* ensure that the unpin work is consistent wrt ->pending. */ | |
3833 | smp_rmb(); | |
3834 | intel_crtc->unpin_work = NULL; | |
3835 | ||
3836 | if (work->event) | |
3837 | drm_send_vblank_event(intel_crtc->base.dev, | |
3838 | intel_crtc->pipe, | |
3839 | work->event); | |
3840 | ||
3841 | drm_crtc_vblank_put(&intel_crtc->base); | |
3842 | ||
3843 | wake_up_all(&dev_priv->pending_flip_queue); | |
3844 | queue_work(dev_priv->wq, &work->work); | |
3845 | ||
3846 | trace_i915_flip_complete(intel_crtc->plane, | |
3847 | work->pending_flip_obj); | |
3848 | } | |
3849 | ||
46a55d30 | 3850 | void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3851 | { |
0f91128d | 3852 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3853 | struct drm_i915_private *dev_priv = dev->dev_private; |
e6c3a2a6 | 3854 | |
2c10d571 | 3855 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
9c787942 CW |
3856 | if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue, |
3857 | !intel_crtc_has_pending_flip(crtc), | |
3858 | 60*HZ) == 0)) { | |
3859 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2c10d571 | 3860 | |
5e2d7afc | 3861 | spin_lock_irq(&dev->event_lock); |
9c787942 CW |
3862 | if (intel_crtc->unpin_work) { |
3863 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
3864 | page_flip_completed(intel_crtc); | |
3865 | } | |
5e2d7afc | 3866 | spin_unlock_irq(&dev->event_lock); |
9c787942 | 3867 | } |
5bb61643 | 3868 | |
975d568a CW |
3869 | if (crtc->primary->fb) { |
3870 | mutex_lock(&dev->struct_mutex); | |
3871 | intel_finish_fb(crtc->primary->fb); | |
3872 | mutex_unlock(&dev->struct_mutex); | |
3873 | } | |
e6c3a2a6 CW |
3874 | } |
3875 | ||
e615efe4 ED |
3876 | /* Program iCLKIP clock to the desired frequency */ |
3877 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3878 | { | |
3879 | struct drm_device *dev = crtc->dev; | |
3880 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 3881 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
e615efe4 ED |
3882 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3883 | u32 temp; | |
3884 | ||
09153000 DV |
3885 | mutex_lock(&dev_priv->dpio_lock); |
3886 | ||
e615efe4 ED |
3887 | /* It is necessary to ungate the pixclk gate prior to programming |
3888 | * the divisors, and gate it back when it is done. | |
3889 | */ | |
3890 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3891 | ||
3892 | /* Disable SSCCTL */ | |
3893 | intel_sbi_write(dev_priv, SBI_SSCCTL6, | |
988d6ee8 PZ |
3894 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
3895 | SBI_SSCCTL_DISABLE, | |
3896 | SBI_ICLK); | |
e615efe4 ED |
3897 | |
3898 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 3899 | if (clock == 20000) { |
e615efe4 ED |
3900 | auxdiv = 1; |
3901 | divsel = 0x41; | |
3902 | phaseinc = 0x20; | |
3903 | } else { | |
3904 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
3905 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3906 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
3907 | * convert the virtual clock precision to KHz here for higher |
3908 | * precision. | |
3909 | */ | |
3910 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3911 | u32 iclk_pi_range = 64; | |
3912 | u32 desired_divisor, msb_divisor_value, pi_value; | |
3913 | ||
12d7ceed | 3914 | desired_divisor = (iclk_virtual_root_freq / clock); |
e615efe4 ED |
3915 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3916 | pi_value = desired_divisor % iclk_pi_range; | |
3917 | ||
3918 | auxdiv = 0; | |
3919 | divsel = msb_divisor_value - 2; | |
3920 | phaseinc = pi_value; | |
3921 | } | |
3922 | ||
3923 | /* This should not happen with any sane values */ | |
3924 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3925 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3926 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3927 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3928 | ||
3929 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3930 | clock, |
e615efe4 ED |
3931 | auxdiv, |
3932 | divsel, | |
3933 | phasedir, | |
3934 | phaseinc); | |
3935 | ||
3936 | /* Program SSCDIVINTPHASE6 */ | |
988d6ee8 | 3937 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
3938 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
3939 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
3940 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
3941 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
3942 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
3943 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 3944 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
3945 | |
3946 | /* Program SSCAUXDIV */ | |
988d6ee8 | 3947 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
3948 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
3949 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 3950 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
3951 | |
3952 | /* Enable modulator and associated divider */ | |
988d6ee8 | 3953 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 3954 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 3955 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 ED |
3956 | |
3957 | /* Wait for initialization time */ | |
3958 | udelay(24); | |
3959 | ||
3960 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
09153000 DV |
3961 | |
3962 | mutex_unlock(&dev_priv->dpio_lock); | |
e615efe4 ED |
3963 | } |
3964 | ||
275f01b2 DV |
3965 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
3966 | enum pipe pch_transcoder) | |
3967 | { | |
3968 | struct drm_device *dev = crtc->base.dev; | |
3969 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 3970 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
3971 | |
3972 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
3973 | I915_READ(HTOTAL(cpu_transcoder))); | |
3974 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
3975 | I915_READ(HBLANK(cpu_transcoder))); | |
3976 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
3977 | I915_READ(HSYNC(cpu_transcoder))); | |
3978 | ||
3979 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
3980 | I915_READ(VTOTAL(cpu_transcoder))); | |
3981 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
3982 | I915_READ(VBLANK(cpu_transcoder))); | |
3983 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
3984 | I915_READ(VSYNC(cpu_transcoder))); | |
3985 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
3986 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
3987 | } | |
3988 | ||
003632d9 | 3989 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 DV |
3990 | { |
3991 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3992 | uint32_t temp; | |
3993 | ||
3994 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 3995 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
3996 | return; |
3997 | ||
3998 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
3999 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4000 | ||
003632d9 ACO |
4001 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4002 | if (enable) | |
4003 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4004 | ||
4005 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4006 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4007 | POSTING_READ(SOUTH_CHICKEN1); | |
4008 | } | |
4009 | ||
4010 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4011 | { | |
4012 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4013 | |
4014 | switch (intel_crtc->pipe) { | |
4015 | case PIPE_A: | |
4016 | break; | |
4017 | case PIPE_B: | |
6e3c9717 | 4018 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4019 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4020 | else |
003632d9 | 4021 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4022 | |
4023 | break; | |
4024 | case PIPE_C: | |
003632d9 | 4025 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4026 | |
4027 | break; | |
4028 | default: | |
4029 | BUG(); | |
4030 | } | |
4031 | } | |
4032 | ||
f67a559d JB |
4033 | /* |
4034 | * Enable PCH resources required for PCH ports: | |
4035 | * - PCH PLLs | |
4036 | * - FDI training & RX/TX | |
4037 | * - update transcoder timings | |
4038 | * - DP transcoding bits | |
4039 | * - transcoder | |
4040 | */ | |
4041 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
4042 | { |
4043 | struct drm_device *dev = crtc->dev; | |
4044 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4045 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4046 | int pipe = intel_crtc->pipe; | |
ee7b9f93 | 4047 | u32 reg, temp; |
2c07245f | 4048 | |
ab9412ba | 4049 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4050 | |
1fbc0d78 DV |
4051 | if (IS_IVYBRIDGE(dev)) |
4052 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
4053 | ||
cd986abb DV |
4054 | /* Write the TU size bits before fdi link training, so that error |
4055 | * detection works. */ | |
4056 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4057 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4058 | ||
c98e9dcf | 4059 | /* For PCH output, training FDI link */ |
674cf967 | 4060 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 4061 | |
3ad8a208 DV |
4062 | /* We need to program the right clock selection before writing the pixel |
4063 | * mutliplier into the DPLL. */ | |
303b81e0 | 4064 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 4065 | u32 sel; |
4b645f14 | 4066 | |
c98e9dcf | 4067 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4068 | temp |= TRANS_DPLL_ENABLE(pipe); |
4069 | sel = TRANS_DPLLB_SEL(pipe); | |
6e3c9717 | 4070 | if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
4071 | temp |= sel; |
4072 | else | |
4073 | temp &= ~sel; | |
c98e9dcf | 4074 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4075 | } |
5eddb70b | 4076 | |
3ad8a208 DV |
4077 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4078 | * transcoder, and we actually should do this to not upset any PCH | |
4079 | * transcoder that already use the clock when we share it. | |
4080 | * | |
4081 | * Note that enable_shared_dpll tries to do the right thing, but | |
4082 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4083 | * the right LVDS enable sequence. */ | |
85b3894f | 4084 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 4085 | |
d9b6cb56 JB |
4086 | /* set transcoder timing, panel must allow it */ |
4087 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 4088 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 4089 | |
303b81e0 | 4090 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4091 | |
c98e9dcf | 4092 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e3c9717 | 4093 | if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { |
dfd07d72 | 4094 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
5eddb70b CW |
4095 | reg = TRANS_DP_CTL(pipe); |
4096 | temp = I915_READ(reg); | |
4097 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4098 | TRANS_DP_SYNC_MASK | |
4099 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
4100 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
4101 | TRANS_DP_ENH_FRAMING); | |
9325c9f0 | 4102 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
4103 | |
4104 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 4105 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 4106 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4107 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4108 | |
4109 | switch (intel_trans_dp_port_sel(crtc)) { | |
4110 | case PCH_DP_B: | |
5eddb70b | 4111 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
4112 | break; |
4113 | case PCH_DP_C: | |
5eddb70b | 4114 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
4115 | break; |
4116 | case PCH_DP_D: | |
5eddb70b | 4117 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4118 | break; |
4119 | default: | |
e95d41e1 | 4120 | BUG(); |
32f9d658 | 4121 | } |
2c07245f | 4122 | |
5eddb70b | 4123 | I915_WRITE(reg, temp); |
6be4a607 | 4124 | } |
b52eb4dc | 4125 | |
b8a4f404 | 4126 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4127 | } |
4128 | ||
1507e5bd PZ |
4129 | static void lpt_pch_enable(struct drm_crtc *crtc) |
4130 | { | |
4131 | struct drm_device *dev = crtc->dev; | |
4132 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4133 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6e3c9717 | 4134 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1507e5bd | 4135 | |
ab9412ba | 4136 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4137 | |
8c52b5e8 | 4138 | lpt_program_iclkip(crtc); |
1507e5bd | 4139 | |
0540e488 | 4140 | /* Set transcoder timing. */ |
275f01b2 | 4141 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 4142 | |
937bb610 | 4143 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4144 | } |
4145 | ||
716c2e55 | 4146 | void intel_put_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 4147 | { |
e2b78267 | 4148 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
ee7b9f93 JB |
4149 | |
4150 | if (pll == NULL) | |
4151 | return; | |
4152 | ||
3e369b76 | 4153 | if (!(pll->config.crtc_mask & (1 << crtc->pipe))) { |
1e6f2ddc | 4154 | WARN(1, "bad %s crtc mask\n", pll->name); |
ee7b9f93 JB |
4155 | return; |
4156 | } | |
4157 | ||
3e369b76 ACO |
4158 | pll->config.crtc_mask &= ~(1 << crtc->pipe); |
4159 | if (pll->config.crtc_mask == 0) { | |
f4a091c7 DV |
4160 | WARN_ON(pll->on); |
4161 | WARN_ON(pll->active); | |
4162 | } | |
4163 | ||
6e3c9717 | 4164 | crtc->config->shared_dpll = DPLL_ID_PRIVATE; |
ee7b9f93 JB |
4165 | } |
4166 | ||
190f68c5 ACO |
4167 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, |
4168 | struct intel_crtc_state *crtc_state) | |
ee7b9f93 | 4169 | { |
e2b78267 | 4170 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
8bd31e67 | 4171 | struct intel_shared_dpll *pll; |
e2b78267 | 4172 | enum intel_dpll_id i; |
ee7b9f93 | 4173 | |
98b6bd99 DV |
4174 | if (HAS_PCH_IBX(dev_priv->dev)) { |
4175 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 4176 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 4177 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 4178 | |
46edb027 DV |
4179 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
4180 | crtc->base.base.id, pll->name); | |
98b6bd99 | 4181 | |
8bd31e67 | 4182 | WARN_ON(pll->new_config->crtc_mask); |
f2a69f44 | 4183 | |
98b6bd99 DV |
4184 | goto found; |
4185 | } | |
4186 | ||
e72f9fbf DV |
4187 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4188 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 JB |
4189 | |
4190 | /* Only want to check enabled timings first */ | |
8bd31e67 | 4191 | if (pll->new_config->crtc_mask == 0) |
ee7b9f93 JB |
4192 | continue; |
4193 | ||
190f68c5 | 4194 | if (memcmp(&crtc_state->dpll_hw_state, |
8bd31e67 ACO |
4195 | &pll->new_config->hw_state, |
4196 | sizeof(pll->new_config->hw_state)) == 0) { | |
4197 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n", | |
1e6f2ddc | 4198 | crtc->base.base.id, pll->name, |
8bd31e67 ACO |
4199 | pll->new_config->crtc_mask, |
4200 | pll->active); | |
ee7b9f93 JB |
4201 | goto found; |
4202 | } | |
4203 | } | |
4204 | ||
4205 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
4206 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4207 | pll = &dev_priv->shared_dplls[i]; | |
8bd31e67 | 4208 | if (pll->new_config->crtc_mask == 0) { |
46edb027 DV |
4209 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
4210 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
4211 | goto found; |
4212 | } | |
4213 | } | |
4214 | ||
4215 | return NULL; | |
4216 | ||
4217 | found: | |
8bd31e67 | 4218 | if (pll->new_config->crtc_mask == 0) |
190f68c5 | 4219 | pll->new_config->hw_state = crtc_state->dpll_hw_state; |
f2a69f44 | 4220 | |
190f68c5 | 4221 | crtc_state->shared_dpll = i; |
46edb027 DV |
4222 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
4223 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 4224 | |
8bd31e67 | 4225 | pll->new_config->crtc_mask |= 1 << crtc->pipe; |
e04c7350 | 4226 | |
ee7b9f93 JB |
4227 | return pll; |
4228 | } | |
4229 | ||
8bd31e67 ACO |
4230 | /** |
4231 | * intel_shared_dpll_start_config - start a new PLL staged config | |
4232 | * @dev_priv: DRM device | |
4233 | * @clear_pipes: mask of pipes that will have their PLLs freed | |
4234 | * | |
4235 | * Starts a new PLL staged config, copying the current config but | |
4236 | * releasing the references of pipes specified in clear_pipes. | |
4237 | */ | |
4238 | static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv, | |
4239 | unsigned clear_pipes) | |
4240 | { | |
4241 | struct intel_shared_dpll *pll; | |
4242 | enum intel_dpll_id i; | |
4243 | ||
4244 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
4245 | pll = &dev_priv->shared_dplls[i]; | |
4246 | ||
4247 | pll->new_config = kmemdup(&pll->config, sizeof pll->config, | |
4248 | GFP_KERNEL); | |
4249 | if (!pll->new_config) | |
4250 | goto cleanup; | |
4251 | ||
4252 | pll->new_config->crtc_mask &= ~clear_pipes; | |
4253 | } | |
4254 | ||
4255 | return 0; | |
4256 | ||
4257 | cleanup: | |
4258 | while (--i >= 0) { | |
4259 | pll = &dev_priv->shared_dplls[i]; | |
f354d733 | 4260 | kfree(pll->new_config); |
8bd31e67 ACO |
4261 | pll->new_config = NULL; |
4262 | } | |
4263 | ||
4264 | return -ENOMEM; | |
4265 | } | |
4266 | ||
4267 | static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv) | |
4268 | { | |
4269 | struct intel_shared_dpll *pll; | |
4270 | enum intel_dpll_id i; | |
4271 | ||
4272 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
4273 | pll = &dev_priv->shared_dplls[i]; | |
4274 | ||
4275 | WARN_ON(pll->new_config == &pll->config); | |
4276 | ||
4277 | pll->config = *pll->new_config; | |
4278 | kfree(pll->new_config); | |
4279 | pll->new_config = NULL; | |
4280 | } | |
4281 | } | |
4282 | ||
4283 | static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv) | |
4284 | { | |
4285 | struct intel_shared_dpll *pll; | |
4286 | enum intel_dpll_id i; | |
4287 | ||
4288 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
4289 | pll = &dev_priv->shared_dplls[i]; | |
4290 | ||
4291 | WARN_ON(pll->new_config == &pll->config); | |
4292 | ||
4293 | kfree(pll->new_config); | |
4294 | pll->new_config = NULL; | |
4295 | } | |
4296 | } | |
4297 | ||
a1520318 | 4298 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
4299 | { |
4300 | struct drm_i915_private *dev_priv = dev->dev_private; | |
23670b32 | 4301 | int dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4302 | u32 temp; |
4303 | ||
4304 | temp = I915_READ(dslreg); | |
4305 | udelay(500); | |
4306 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4307 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4308 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4309 | } |
4310 | } | |
4311 | ||
a1b2278e CK |
4312 | /** |
4313 | * skl_update_scaler_users - Stages update to crtc's scaler state | |
4314 | * @intel_crtc: crtc | |
4315 | * @crtc_state: crtc_state | |
4316 | * @plane: plane (NULL indicates crtc is requesting update) | |
4317 | * @plane_state: plane's state | |
4318 | * @force_detach: request unconditional detachment of scaler | |
4319 | * | |
4320 | * This function updates scaler state for requested plane or crtc. | |
4321 | * To request scaler usage update for a plane, caller shall pass plane pointer. | |
4322 | * To request scaler usage update for crtc, caller shall pass plane pointer | |
4323 | * as NULL. | |
4324 | * | |
4325 | * Return | |
4326 | * 0 - scaler_usage updated successfully | |
4327 | * error - requested scaling cannot be supported or other error condition | |
4328 | */ | |
4329 | int | |
4330 | skl_update_scaler_users( | |
4331 | struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state, | |
4332 | struct intel_plane *intel_plane, struct intel_plane_state *plane_state, | |
4333 | int force_detach) | |
4334 | { | |
4335 | int need_scaling; | |
4336 | int idx; | |
4337 | int src_w, src_h, dst_w, dst_h; | |
4338 | int *scaler_id; | |
4339 | struct drm_framebuffer *fb; | |
4340 | struct intel_crtc_scaler_state *scaler_state; | |
4341 | ||
4342 | if (!intel_crtc || !crtc_state) | |
4343 | return 0; | |
4344 | ||
4345 | scaler_state = &crtc_state->scaler_state; | |
4346 | ||
4347 | idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX; | |
4348 | fb = intel_plane ? plane_state->base.fb : NULL; | |
4349 | ||
4350 | if (intel_plane) { | |
4351 | src_w = drm_rect_width(&plane_state->src) >> 16; | |
4352 | src_h = drm_rect_height(&plane_state->src) >> 16; | |
4353 | dst_w = drm_rect_width(&plane_state->dst); | |
4354 | dst_h = drm_rect_height(&plane_state->dst); | |
4355 | scaler_id = &plane_state->scaler_id; | |
4356 | } else { | |
4357 | struct drm_display_mode *adjusted_mode = | |
4358 | &crtc_state->base.adjusted_mode; | |
4359 | src_w = crtc_state->pipe_src_w; | |
4360 | src_h = crtc_state->pipe_src_h; | |
4361 | dst_w = adjusted_mode->hdisplay; | |
4362 | dst_h = adjusted_mode->vdisplay; | |
4363 | scaler_id = &scaler_state->scaler_id; | |
4364 | } | |
4365 | need_scaling = (src_w != dst_w || src_h != dst_h); | |
4366 | ||
4367 | /* | |
4368 | * if plane is being disabled or scaler is no more required or force detach | |
4369 | * - free scaler binded to this plane/crtc | |
4370 | * - in order to do this, update crtc->scaler_usage | |
4371 | * | |
4372 | * Here scaler state in crtc_state is set free so that | |
4373 | * scaler can be assigned to other user. Actual register | |
4374 | * update to free the scaler is done in plane/panel-fit programming. | |
4375 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4376 | */ | |
4377 | if (force_detach || !need_scaling || (intel_plane && | |
4378 | (!fb || !plane_state->visible))) { | |
4379 | if (*scaler_id >= 0) { | |
4380 | scaler_state->scaler_users &= ~(1 << idx); | |
4381 | scaler_state->scalers[*scaler_id].in_use = 0; | |
4382 | ||
4383 | DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d " | |
4384 | "crtc_state = %p scaler_users = 0x%x\n", | |
4385 | intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC", | |
4386 | intel_plane ? intel_plane->base.base.id : | |
4387 | intel_crtc->base.base.id, crtc_state, | |
4388 | scaler_state->scaler_users); | |
4389 | *scaler_id = -1; | |
4390 | } | |
4391 | return 0; | |
4392 | } | |
4393 | ||
4394 | /* range checks */ | |
4395 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4396 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4397 | ||
4398 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4399 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
4400 | DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u " | |
4401 | "size is out of scaler range\n", | |
4402 | intel_plane ? "PLANE" : "CRTC", | |
4403 | intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id, | |
4404 | intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h); | |
4405 | return -EINVAL; | |
4406 | } | |
4407 | ||
4408 | /* check colorkey */ | |
4409 | if (intel_plane && intel_plane->ckey.flags != I915_SET_COLORKEY_NONE) { | |
4410 | DRM_DEBUG_KMS("PLANE:%d scaling with color key not allowed", | |
4411 | intel_plane->base.base.id); | |
4412 | return -EINVAL; | |
4413 | } | |
4414 | ||
4415 | /* Check src format */ | |
4416 | if (intel_plane) { | |
4417 | switch (fb->pixel_format) { | |
4418 | case DRM_FORMAT_RGB565: | |
4419 | case DRM_FORMAT_XBGR8888: | |
4420 | case DRM_FORMAT_XRGB8888: | |
4421 | case DRM_FORMAT_ABGR8888: | |
4422 | case DRM_FORMAT_ARGB8888: | |
4423 | case DRM_FORMAT_XRGB2101010: | |
4424 | case DRM_FORMAT_ARGB2101010: | |
4425 | case DRM_FORMAT_XBGR2101010: | |
4426 | case DRM_FORMAT_ABGR2101010: | |
4427 | case DRM_FORMAT_YUYV: | |
4428 | case DRM_FORMAT_YVYU: | |
4429 | case DRM_FORMAT_UYVY: | |
4430 | case DRM_FORMAT_VYUY: | |
4431 | break; | |
4432 | default: | |
4433 | DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n", | |
4434 | intel_plane->base.base.id, fb->base.id, fb->pixel_format); | |
4435 | return -EINVAL; | |
4436 | } | |
4437 | } | |
4438 | ||
4439 | /* mark this plane as a scaler user in crtc_state */ | |
4440 | scaler_state->scaler_users |= (1 << idx); | |
4441 | DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u " | |
4442 | "crtc_state = %p scaler_users = 0x%x\n", | |
4443 | intel_plane ? "PLANE" : "CRTC", | |
4444 | intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id, | |
4445 | src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users); | |
4446 | return 0; | |
4447 | } | |
4448 | ||
4449 | static void skylake_pfit_update(struct intel_crtc *crtc, int enable) | |
bd2e244f JB |
4450 | { |
4451 | struct drm_device *dev = crtc->base.dev; | |
4452 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4453 | int pipe = crtc->pipe; | |
a1b2278e CK |
4454 | struct intel_crtc_scaler_state *scaler_state = |
4455 | &crtc->config->scaler_state; | |
4456 | ||
4457 | DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); | |
4458 | ||
4459 | /* To update pfit, first update scaler state */ | |
4460 | skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable); | |
4461 | intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config); | |
4462 | skl_detach_scalers(crtc); | |
4463 | if (!enable) | |
4464 | return; | |
bd2e244f | 4465 | |
6e3c9717 | 4466 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4467 | int id; |
4468 | ||
4469 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { | |
4470 | DRM_ERROR("Requesting pfit without getting a scaler first\n"); | |
4471 | return; | |
4472 | } | |
4473 | ||
4474 | id = scaler_state->scaler_id; | |
4475 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4476 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4477 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4478 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
4479 | ||
4480 | DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); | |
bd2e244f JB |
4481 | } |
4482 | } | |
4483 | ||
b074cec8 JB |
4484 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4485 | { | |
4486 | struct drm_device *dev = crtc->base.dev; | |
4487 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4488 | int pipe = crtc->pipe; | |
4489 | ||
6e3c9717 | 4490 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4491 | /* Force use of hard-coded filter coefficients |
4492 | * as some pre-programmed values are broken, | |
4493 | * e.g. x201. | |
4494 | */ | |
4495 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
4496 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
4497 | PF_PIPE_SEL_IVB(pipe)); | |
4498 | else | |
4499 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4500 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4501 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4502 | } |
4503 | } | |
4504 | ||
4a3b8769 | 4505 | static void intel_enable_sprite_planes(struct drm_crtc *crtc) |
bb53d4ae VS |
4506 | { |
4507 | struct drm_device *dev = crtc->dev; | |
4508 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
af2b653b | 4509 | struct drm_plane *plane; |
bb53d4ae VS |
4510 | struct intel_plane *intel_plane; |
4511 | ||
af2b653b MR |
4512 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
4513 | intel_plane = to_intel_plane(plane); | |
bb53d4ae VS |
4514 | if (intel_plane->pipe == pipe) |
4515 | intel_plane_restore(&intel_plane->base); | |
af2b653b | 4516 | } |
bb53d4ae VS |
4517 | } |
4518 | ||
0d703d4e MR |
4519 | /* |
4520 | * Disable a plane internally without actually modifying the plane's state. | |
4521 | * This will allow us to easily restore the plane later by just reprogramming | |
4522 | * its state. | |
4523 | */ | |
4524 | static void disable_plane_internal(struct drm_plane *plane) | |
4525 | { | |
4526 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
4527 | struct drm_plane_state *state = | |
4528 | plane->funcs->atomic_duplicate_state(plane); | |
4529 | struct intel_plane_state *intel_state = to_intel_plane_state(state); | |
4530 | ||
4531 | intel_state->visible = false; | |
4532 | intel_plane->commit_plane(plane, intel_state); | |
4533 | ||
4534 | intel_plane_destroy_state(plane, state); | |
4535 | } | |
4536 | ||
4a3b8769 | 4537 | static void intel_disable_sprite_planes(struct drm_crtc *crtc) |
bb53d4ae VS |
4538 | { |
4539 | struct drm_device *dev = crtc->dev; | |
4540 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
af2b653b | 4541 | struct drm_plane *plane; |
bb53d4ae VS |
4542 | struct intel_plane *intel_plane; |
4543 | ||
af2b653b MR |
4544 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
4545 | intel_plane = to_intel_plane(plane); | |
0d703d4e MR |
4546 | if (plane->fb && intel_plane->pipe == pipe) |
4547 | disable_plane_internal(plane); | |
af2b653b | 4548 | } |
bb53d4ae VS |
4549 | } |
4550 | ||
20bc8673 | 4551 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4552 | { |
cea165c3 VS |
4553 | struct drm_device *dev = crtc->base.dev; |
4554 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d77e4531 | 4555 | |
6e3c9717 | 4556 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4557 | return; |
4558 | ||
cea165c3 VS |
4559 | /* We can only enable IPS after we enable a plane and wait for a vblank */ |
4560 | intel_wait_for_vblank(dev, crtc->pipe); | |
4561 | ||
d77e4531 | 4562 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 4563 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4564 | mutex_lock(&dev_priv->rps.hw_lock); |
4565 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4566 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4567 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4568 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4569 | * mailbox." Moreover, the mailbox may return a bogus state, |
4570 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4571 | */ |
4572 | } else { | |
4573 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4574 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4575 | * is essentially intel_wait_for_vblank. If we don't have this | |
4576 | * and don't wait for vblanks until the end of crtc_enable, then | |
4577 | * the HW state readout code will complain that the expected | |
4578 | * IPS_CTL value is not the one we read. */ | |
4579 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
4580 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
4581 | } | |
d77e4531 PZ |
4582 | } |
4583 | ||
20bc8673 | 4584 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4585 | { |
4586 | struct drm_device *dev = crtc->base.dev; | |
4587 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4588 | ||
6e3c9717 | 4589 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4590 | return; |
4591 | ||
4592 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 4593 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4594 | mutex_lock(&dev_priv->rps.hw_lock); |
4595 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4596 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
4597 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
4598 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
4599 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 4600 | } else { |
2a114cc1 | 4601 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4602 | POSTING_READ(IPS_CTL); |
4603 | } | |
d77e4531 PZ |
4604 | |
4605 | /* We need to wait for a vblank before we can disable the plane. */ | |
4606 | intel_wait_for_vblank(dev, crtc->pipe); | |
4607 | } | |
4608 | ||
4609 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
4610 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
4611 | { | |
4612 | struct drm_device *dev = crtc->dev; | |
4613 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4614 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4615 | enum pipe pipe = intel_crtc->pipe; | |
4616 | int palreg = PALETTE(pipe); | |
4617 | int i; | |
4618 | bool reenable_ips = false; | |
4619 | ||
4620 | /* The clocks have to be on to load the palette. */ | |
83d65738 | 4621 | if (!crtc->state->enable || !intel_crtc->active) |
d77e4531 PZ |
4622 | return; |
4623 | ||
4624 | if (!HAS_PCH_SPLIT(dev_priv->dev)) { | |
409ee761 | 4625 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) |
d77e4531 PZ |
4626 | assert_dsi_pll_enabled(dev_priv); |
4627 | else | |
4628 | assert_pll_enabled(dev_priv, pipe); | |
4629 | } | |
4630 | ||
4631 | /* use legacy palette for Ironlake */ | |
7a1db49a | 4632 | if (!HAS_GMCH_DISPLAY(dev)) |
d77e4531 PZ |
4633 | palreg = LGC_PALETTE(pipe); |
4634 | ||
4635 | /* Workaround : Do not read or write the pipe palette/gamma data while | |
4636 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
4637 | */ | |
6e3c9717 | 4638 | if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled && |
d77e4531 PZ |
4639 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
4640 | GAMMA_MODE_MODE_SPLIT)) { | |
4641 | hsw_disable_ips(intel_crtc); | |
4642 | reenable_ips = true; | |
4643 | } | |
4644 | ||
4645 | for (i = 0; i < 256; i++) { | |
4646 | I915_WRITE(palreg + 4 * i, | |
4647 | (intel_crtc->lut_r[i] << 16) | | |
4648 | (intel_crtc->lut_g[i] << 8) | | |
4649 | intel_crtc->lut_b[i]); | |
4650 | } | |
4651 | ||
4652 | if (reenable_ips) | |
4653 | hsw_enable_ips(intel_crtc); | |
4654 | } | |
4655 | ||
d3eedb1a VS |
4656 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
4657 | { | |
4658 | if (!enable && intel_crtc->overlay) { | |
4659 | struct drm_device *dev = intel_crtc->base.dev; | |
4660 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4661 | ||
4662 | mutex_lock(&dev->struct_mutex); | |
4663 | dev_priv->mm.interruptible = false; | |
4664 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4665 | dev_priv->mm.interruptible = true; | |
4666 | mutex_unlock(&dev->struct_mutex); | |
4667 | } | |
4668 | ||
4669 | /* Let userspace switch the overlay on again. In most cases userspace | |
4670 | * has to recompute where to put it anyway. | |
4671 | */ | |
4672 | } | |
4673 | ||
d3eedb1a | 4674 | static void intel_crtc_enable_planes(struct drm_crtc *crtc) |
a5c4d7bc VS |
4675 | { |
4676 | struct drm_device *dev = crtc->dev; | |
a5c4d7bc VS |
4677 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4678 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4679 | |
fdd508a6 | 4680 | intel_enable_primary_hw_plane(crtc->primary, crtc); |
4a3b8769 | 4681 | intel_enable_sprite_planes(crtc); |
a5c4d7bc | 4682 | intel_crtc_update_cursor(crtc, true); |
d3eedb1a | 4683 | intel_crtc_dpms_overlay(intel_crtc, true); |
a5c4d7bc VS |
4684 | |
4685 | hsw_enable_ips(intel_crtc); | |
4686 | ||
4687 | mutex_lock(&dev->struct_mutex); | |
7ff0ebcc | 4688 | intel_fbc_update(dev); |
a5c4d7bc | 4689 | mutex_unlock(&dev->struct_mutex); |
f99d7069 DV |
4690 | |
4691 | /* | |
4692 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4693 | * to compute the mask of flip planes precisely. For the time being | |
4694 | * consider this a flip from a NULL plane. | |
4695 | */ | |
4696 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4697 | } |
4698 | ||
d3eedb1a | 4699 | static void intel_crtc_disable_planes(struct drm_crtc *crtc) |
a5c4d7bc VS |
4700 | { |
4701 | struct drm_device *dev = crtc->dev; | |
4702 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4703 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4704 | int pipe = intel_crtc->pipe; | |
a5c4d7bc VS |
4705 | |
4706 | intel_crtc_wait_for_pending_flips(crtc); | |
a5c4d7bc | 4707 | |
e35fef21 | 4708 | if (dev_priv->fbc.crtc == intel_crtc) |
7ff0ebcc | 4709 | intel_fbc_disable(dev); |
a5c4d7bc VS |
4710 | |
4711 | hsw_disable_ips(intel_crtc); | |
4712 | ||
d3eedb1a | 4713 | intel_crtc_dpms_overlay(intel_crtc, false); |
a5c4d7bc | 4714 | intel_crtc_update_cursor(crtc, false); |
4a3b8769 | 4715 | intel_disable_sprite_planes(crtc); |
fdd508a6 | 4716 | intel_disable_primary_hw_plane(crtc->primary, crtc); |
f98551ae | 4717 | |
f99d7069 DV |
4718 | /* |
4719 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4720 | * to compute the mask of flip planes precisely. For the time being | |
4721 | * consider this a flip to a NULL plane. | |
4722 | */ | |
4723 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4724 | } |
4725 | ||
f67a559d JB |
4726 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
4727 | { | |
4728 | struct drm_device *dev = crtc->dev; | |
4729 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4730 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4731 | struct intel_encoder *encoder; |
f67a559d | 4732 | int pipe = intel_crtc->pipe; |
f67a559d | 4733 | |
83d65738 | 4734 | WARN_ON(!crtc->state->enable); |
08a48469 | 4735 | |
f67a559d JB |
4736 | if (intel_crtc->active) |
4737 | return; | |
4738 | ||
6e3c9717 | 4739 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
4740 | intel_prepare_shared_dpll(intel_crtc); |
4741 | ||
6e3c9717 | 4742 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4743 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
4744 | |
4745 | intel_set_pipe_timings(intel_crtc); | |
4746 | ||
6e3c9717 | 4747 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 4748 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4749 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
4750 | } |
4751 | ||
4752 | ironlake_set_pipeconf(crtc); | |
4753 | ||
f67a559d | 4754 | intel_crtc->active = true; |
8664281b | 4755 | |
a72e4c9f DV |
4756 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4757 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
8664281b | 4758 | |
f6736a1a | 4759 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
4760 | if (encoder->pre_enable) |
4761 | encoder->pre_enable(encoder); | |
f67a559d | 4762 | |
6e3c9717 | 4763 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
4764 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4765 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4766 | * enabling. */ | |
88cefb6c | 4767 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4768 | } else { |
4769 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4770 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4771 | } | |
f67a559d | 4772 | |
b074cec8 | 4773 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4774 | |
9c54c0dd JB |
4775 | /* |
4776 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4777 | * clocks enabled | |
4778 | */ | |
4779 | intel_crtc_load_lut(crtc); | |
4780 | ||
f37fcc2a | 4781 | intel_update_watermarks(crtc); |
e1fdc473 | 4782 | intel_enable_pipe(intel_crtc); |
f67a559d | 4783 | |
6e3c9717 | 4784 | if (intel_crtc->config->has_pch_encoder) |
f67a559d | 4785 | ironlake_pch_enable(crtc); |
c98e9dcf | 4786 | |
f9b61ff6 DV |
4787 | assert_vblank_disabled(crtc); |
4788 | drm_crtc_vblank_on(crtc); | |
4789 | ||
fa5c73b1 DV |
4790 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4791 | encoder->enable(encoder); | |
61b77ddd DV |
4792 | |
4793 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4794 | cpt_verify_modeset(dev, intel_crtc->pipe); |
6ce94100 | 4795 | |
d3eedb1a | 4796 | intel_crtc_enable_planes(crtc); |
6be4a607 JB |
4797 | } |
4798 | ||
42db64ef PZ |
4799 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4800 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4801 | { | |
f5adf94e | 4802 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4803 | } |
4804 | ||
e4916946 PZ |
4805 | /* |
4806 | * This implements the workaround described in the "notes" section of the mode | |
4807 | * set sequence documentation. When going from no pipes or single pipe to | |
4808 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
4809 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
4810 | */ | |
4811 | static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc) | |
4812 | { | |
4813 | struct drm_device *dev = crtc->base.dev; | |
4814 | struct intel_crtc *crtc_it, *other_active_crtc = NULL; | |
4815 | ||
4816 | /* We want to get the other_active_crtc only if there's only 1 other | |
4817 | * active crtc. */ | |
d3fcc808 | 4818 | for_each_intel_crtc(dev, crtc_it) { |
e4916946 PZ |
4819 | if (!crtc_it->active || crtc_it == crtc) |
4820 | continue; | |
4821 | ||
4822 | if (other_active_crtc) | |
4823 | return; | |
4824 | ||
4825 | other_active_crtc = crtc_it; | |
4826 | } | |
4827 | if (!other_active_crtc) | |
4828 | return; | |
4829 | ||
4830 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4831 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4832 | } | |
4833 | ||
4f771f10 PZ |
4834 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4835 | { | |
4836 | struct drm_device *dev = crtc->dev; | |
4837 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4838 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4839 | struct intel_encoder *encoder; | |
4840 | int pipe = intel_crtc->pipe; | |
4f771f10 | 4841 | |
83d65738 | 4842 | WARN_ON(!crtc->state->enable); |
4f771f10 PZ |
4843 | |
4844 | if (intel_crtc->active) | |
4845 | return; | |
4846 | ||
df8ad70c DV |
4847 | if (intel_crtc_to_shared_dpll(intel_crtc)) |
4848 | intel_enable_shared_dpll(intel_crtc); | |
4849 | ||
6e3c9717 | 4850 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4851 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 DV |
4852 | |
4853 | intel_set_pipe_timings(intel_crtc); | |
4854 | ||
6e3c9717 ACO |
4855 | if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) { |
4856 | I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder), | |
4857 | intel_crtc->config->pixel_multiplier - 1); | |
ebb69c95 CT |
4858 | } |
4859 | ||
6e3c9717 | 4860 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 4861 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4862 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
4863 | } |
4864 | ||
4865 | haswell_set_pipeconf(crtc); | |
4866 | ||
4867 | intel_set_pipe_csc(crtc); | |
4868 | ||
4f771f10 | 4869 | intel_crtc->active = true; |
8664281b | 4870 | |
a72e4c9f | 4871 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4f771f10 PZ |
4872 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4873 | if (encoder->pre_enable) | |
4874 | encoder->pre_enable(encoder); | |
4875 | ||
6e3c9717 | 4876 | if (intel_crtc->config->has_pch_encoder) { |
a72e4c9f DV |
4877 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
4878 | true); | |
4fe9467d ID |
4879 | dev_priv->display.fdi_link_train(crtc); |
4880 | } | |
4881 | ||
1f544388 | 4882 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 4883 | |
bd2e244f | 4884 | if (IS_SKYLAKE(dev)) |
a1b2278e | 4885 | skylake_pfit_update(intel_crtc, 1); |
bd2e244f JB |
4886 | else |
4887 | ironlake_pfit_enable(intel_crtc); | |
4f771f10 PZ |
4888 | |
4889 | /* | |
4890 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4891 | * clocks enabled | |
4892 | */ | |
4893 | intel_crtc_load_lut(crtc); | |
4894 | ||
1f544388 | 4895 | intel_ddi_set_pipe_settings(crtc); |
8228c251 | 4896 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 4897 | |
f37fcc2a | 4898 | intel_update_watermarks(crtc); |
e1fdc473 | 4899 | intel_enable_pipe(intel_crtc); |
42db64ef | 4900 | |
6e3c9717 | 4901 | if (intel_crtc->config->has_pch_encoder) |
1507e5bd | 4902 | lpt_pch_enable(crtc); |
4f771f10 | 4903 | |
6e3c9717 | 4904 | if (intel_crtc->config->dp_encoder_is_mst) |
0e32b39c DA |
4905 | intel_ddi_set_vc_payload_alloc(crtc, true); |
4906 | ||
f9b61ff6 DV |
4907 | assert_vblank_disabled(crtc); |
4908 | drm_crtc_vblank_on(crtc); | |
4909 | ||
8807e55b | 4910 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 4911 | encoder->enable(encoder); |
8807e55b JN |
4912 | intel_opregion_notify_encoder(encoder, true); |
4913 | } | |
4f771f10 | 4914 | |
e4916946 PZ |
4915 | /* If we change the relative order between pipe/planes enabling, we need |
4916 | * to change the workaround. */ | |
4917 | haswell_mode_set_planes_workaround(intel_crtc); | |
d3eedb1a | 4918 | intel_crtc_enable_planes(crtc); |
4f771f10 PZ |
4919 | } |
4920 | ||
3f8dce3a DV |
4921 | static void ironlake_pfit_disable(struct intel_crtc *crtc) |
4922 | { | |
4923 | struct drm_device *dev = crtc->base.dev; | |
4924 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4925 | int pipe = crtc->pipe; | |
4926 | ||
4927 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
4928 | * it's in use. The hw state code will make sure we get this right. */ | |
6e3c9717 | 4929 | if (crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
4930 | I915_WRITE(PF_CTL(pipe), 0); |
4931 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
4932 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
4933 | } | |
4934 | } | |
4935 | ||
6be4a607 JB |
4936 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
4937 | { | |
4938 | struct drm_device *dev = crtc->dev; | |
4939 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4940 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4941 | struct intel_encoder *encoder; |
6be4a607 | 4942 | int pipe = intel_crtc->pipe; |
5eddb70b | 4943 | u32 reg, temp; |
b52eb4dc | 4944 | |
f7abfe8b CW |
4945 | if (!intel_crtc->active) |
4946 | return; | |
4947 | ||
d3eedb1a | 4948 | intel_crtc_disable_planes(crtc); |
a5c4d7bc | 4949 | |
ea9d758d DV |
4950 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4951 | encoder->disable(encoder); | |
4952 | ||
f9b61ff6 DV |
4953 | drm_crtc_vblank_off(crtc); |
4954 | assert_vblank_disabled(crtc); | |
4955 | ||
6e3c9717 | 4956 | if (intel_crtc->config->has_pch_encoder) |
a72e4c9f | 4957 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
d925c59a | 4958 | |
575f7ab7 | 4959 | intel_disable_pipe(intel_crtc); |
32f9d658 | 4960 | |
3f8dce3a | 4961 | ironlake_pfit_disable(intel_crtc); |
2c07245f | 4962 | |
bf49ec8c DV |
4963 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4964 | if (encoder->post_disable) | |
4965 | encoder->post_disable(encoder); | |
2c07245f | 4966 | |
6e3c9717 | 4967 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 4968 | ironlake_fdi_disable(crtc); |
913d8d11 | 4969 | |
d925c59a | 4970 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 4971 | |
d925c59a DV |
4972 | if (HAS_PCH_CPT(dev)) { |
4973 | /* disable TRANS_DP_CTL */ | |
4974 | reg = TRANS_DP_CTL(pipe); | |
4975 | temp = I915_READ(reg); | |
4976 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
4977 | TRANS_DP_PORT_SEL_MASK); | |
4978 | temp |= TRANS_DP_PORT_SEL_NONE; | |
4979 | I915_WRITE(reg, temp); | |
4980 | ||
4981 | /* disable DPLL_SEL */ | |
4982 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 4983 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 4984 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 4985 | } |
e3421a18 | 4986 | |
d925c59a | 4987 | /* disable PCH DPLL */ |
e72f9fbf | 4988 | intel_disable_shared_dpll(intel_crtc); |
8db9d77b | 4989 | |
d925c59a DV |
4990 | ironlake_fdi_pll_disable(intel_crtc); |
4991 | } | |
6b383a7f | 4992 | |
f7abfe8b | 4993 | intel_crtc->active = false; |
46ba614c | 4994 | intel_update_watermarks(crtc); |
d1ebd816 BW |
4995 | |
4996 | mutex_lock(&dev->struct_mutex); | |
7ff0ebcc | 4997 | intel_fbc_update(dev); |
d1ebd816 | 4998 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 4999 | } |
1b3c7a47 | 5000 | |
4f771f10 | 5001 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 5002 | { |
4f771f10 PZ |
5003 | struct drm_device *dev = crtc->dev; |
5004 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 5005 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 | 5006 | struct intel_encoder *encoder; |
6e3c9717 | 5007 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5008 | |
4f771f10 PZ |
5009 | if (!intel_crtc->active) |
5010 | return; | |
5011 | ||
d3eedb1a | 5012 | intel_crtc_disable_planes(crtc); |
dda9a66a | 5013 | |
8807e55b JN |
5014 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5015 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 5016 | encoder->disable(encoder); |
8807e55b | 5017 | } |
4f771f10 | 5018 | |
f9b61ff6 DV |
5019 | drm_crtc_vblank_off(crtc); |
5020 | assert_vblank_disabled(crtc); | |
5021 | ||
6e3c9717 | 5022 | if (intel_crtc->config->has_pch_encoder) |
a72e4c9f DV |
5023 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5024 | false); | |
575f7ab7 | 5025 | intel_disable_pipe(intel_crtc); |
4f771f10 | 5026 | |
6e3c9717 | 5027 | if (intel_crtc->config->dp_encoder_is_mst) |
a4bf214f VS |
5028 | intel_ddi_set_vc_payload_alloc(crtc, false); |
5029 | ||
ad80a810 | 5030 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5031 | |
bd2e244f | 5032 | if (IS_SKYLAKE(dev)) |
a1b2278e | 5033 | skylake_pfit_update(intel_crtc, 0); |
bd2e244f JB |
5034 | else |
5035 | ironlake_pfit_disable(intel_crtc); | |
4f771f10 | 5036 | |
1f544388 | 5037 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 5038 | |
6e3c9717 | 5039 | if (intel_crtc->config->has_pch_encoder) { |
ab4d966c | 5040 | lpt_disable_pch_transcoder(dev_priv); |
1ad960f2 | 5041 | intel_ddi_fdi_disable(crtc); |
83616634 | 5042 | } |
4f771f10 | 5043 | |
97b040aa ID |
5044 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5045 | if (encoder->post_disable) | |
5046 | encoder->post_disable(encoder); | |
5047 | ||
4f771f10 | 5048 | intel_crtc->active = false; |
46ba614c | 5049 | intel_update_watermarks(crtc); |
4f771f10 PZ |
5050 | |
5051 | mutex_lock(&dev->struct_mutex); | |
7ff0ebcc | 5052 | intel_fbc_update(dev); |
4f771f10 | 5053 | mutex_unlock(&dev->struct_mutex); |
df8ad70c DV |
5054 | |
5055 | if (intel_crtc_to_shared_dpll(intel_crtc)) | |
5056 | intel_disable_shared_dpll(intel_crtc); | |
4f771f10 PZ |
5057 | } |
5058 | ||
ee7b9f93 JB |
5059 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
5060 | { | |
5061 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
e72f9fbf | 5062 | intel_put_shared_dpll(intel_crtc); |
ee7b9f93 JB |
5063 | } |
5064 | ||
6441ab5f | 5065 | |
2dd24552 JB |
5066 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5067 | { | |
5068 | struct drm_device *dev = crtc->base.dev; | |
5069 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 5070 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5071 | |
681a8504 | 5072 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5073 | return; |
5074 | ||
2dd24552 | 5075 | /* |
c0b03411 DV |
5076 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5077 | * according to register description and PRM. | |
2dd24552 | 5078 | */ |
c0b03411 DV |
5079 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5080 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5081 | |
b074cec8 JB |
5082 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5083 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5084 | |
5085 | /* Border color in case we don't scale up to the full screen. Black by | |
5086 | * default, change to something else for debugging. */ | |
5087 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5088 | } |
5089 | ||
d05410f9 DA |
5090 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
5091 | { | |
5092 | switch (port) { | |
5093 | case PORT_A: | |
5094 | return POWER_DOMAIN_PORT_DDI_A_4_LANES; | |
5095 | case PORT_B: | |
5096 | return POWER_DOMAIN_PORT_DDI_B_4_LANES; | |
5097 | case PORT_C: | |
5098 | return POWER_DOMAIN_PORT_DDI_C_4_LANES; | |
5099 | case PORT_D: | |
5100 | return POWER_DOMAIN_PORT_DDI_D_4_LANES; | |
5101 | default: | |
5102 | WARN_ON_ONCE(1); | |
5103 | return POWER_DOMAIN_PORT_OTHER; | |
5104 | } | |
5105 | } | |
5106 | ||
77d22dca ID |
5107 | #define for_each_power_domain(domain, mask) \ |
5108 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
5109 | if ((1 << (domain)) & (mask)) | |
5110 | ||
319be8ae ID |
5111 | enum intel_display_power_domain |
5112 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
5113 | { | |
5114 | struct drm_device *dev = intel_encoder->base.dev; | |
5115 | struct intel_digital_port *intel_dig_port; | |
5116 | ||
5117 | switch (intel_encoder->type) { | |
5118 | case INTEL_OUTPUT_UNKNOWN: | |
5119 | /* Only DDI platforms should ever use this output type */ | |
5120 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
5121 | case INTEL_OUTPUT_DISPLAYPORT: | |
5122 | case INTEL_OUTPUT_HDMI: | |
5123 | case INTEL_OUTPUT_EDP: | |
5124 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 5125 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
5126 | case INTEL_OUTPUT_DP_MST: |
5127 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5128 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
5129 | case INTEL_OUTPUT_ANALOG: |
5130 | return POWER_DOMAIN_PORT_CRT; | |
5131 | case INTEL_OUTPUT_DSI: | |
5132 | return POWER_DOMAIN_PORT_DSI; | |
5133 | default: | |
5134 | return POWER_DOMAIN_PORT_OTHER; | |
5135 | } | |
5136 | } | |
5137 | ||
5138 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) | |
77d22dca | 5139 | { |
319be8ae ID |
5140 | struct drm_device *dev = crtc->dev; |
5141 | struct intel_encoder *intel_encoder; | |
5142 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5143 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca ID |
5144 | unsigned long mask; |
5145 | enum transcoder transcoder; | |
5146 | ||
5147 | transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); | |
5148 | ||
5149 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); | |
5150 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
6e3c9717 ACO |
5151 | if (intel_crtc->config->pch_pfit.enabled || |
5152 | intel_crtc->config->pch_pfit.force_thru) | |
77d22dca ID |
5153 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
5154 | ||
319be8ae ID |
5155 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
5156 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); | |
5157 | ||
77d22dca ID |
5158 | return mask; |
5159 | } | |
5160 | ||
679dacd4 | 5161 | static void modeset_update_crtc_power_domains(struct drm_atomic_state *state) |
77d22dca | 5162 | { |
679dacd4 | 5163 | struct drm_device *dev = state->dev; |
77d22dca ID |
5164 | struct drm_i915_private *dev_priv = dev->dev_private; |
5165 | unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }; | |
5166 | struct intel_crtc *crtc; | |
5167 | ||
5168 | /* | |
5169 | * First get all needed power domains, then put all unneeded, to avoid | |
5170 | * any unnecessary toggling of the power wells. | |
5171 | */ | |
d3fcc808 | 5172 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
5173 | enum intel_display_power_domain domain; |
5174 | ||
83d65738 | 5175 | if (!crtc->base.state->enable) |
77d22dca ID |
5176 | continue; |
5177 | ||
319be8ae | 5178 | pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base); |
77d22dca ID |
5179 | |
5180 | for_each_power_domain(domain, pipe_domains[crtc->pipe]) | |
5181 | intel_display_power_get(dev_priv, domain); | |
5182 | } | |
5183 | ||
50f6e502 | 5184 | if (dev_priv->display.modeset_global_resources) |
679dacd4 | 5185 | dev_priv->display.modeset_global_resources(state); |
50f6e502 | 5186 | |
d3fcc808 | 5187 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
5188 | enum intel_display_power_domain domain; |
5189 | ||
5190 | for_each_power_domain(domain, crtc->enabled_power_domains) | |
5191 | intel_display_power_put(dev_priv, domain); | |
5192 | ||
5193 | crtc->enabled_power_domains = pipe_domains[crtc->pipe]; | |
5194 | } | |
5195 | ||
5196 | intel_display_set_init_power(dev_priv, false); | |
5197 | } | |
5198 | ||
f8437dd1 VK |
5199 | void broxton_set_cdclk(struct drm_device *dev, int frequency) |
5200 | { | |
5201 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5202 | uint32_t divider; | |
5203 | uint32_t ratio; | |
5204 | uint32_t current_freq; | |
5205 | int ret; | |
5206 | ||
5207 | /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */ | |
5208 | switch (frequency) { | |
5209 | case 144000: | |
5210 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; | |
5211 | ratio = BXT_DE_PLL_RATIO(60); | |
5212 | break; | |
5213 | case 288000: | |
5214 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; | |
5215 | ratio = BXT_DE_PLL_RATIO(60); | |
5216 | break; | |
5217 | case 384000: | |
5218 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; | |
5219 | ratio = BXT_DE_PLL_RATIO(60); | |
5220 | break; | |
5221 | case 576000: | |
5222 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5223 | ratio = BXT_DE_PLL_RATIO(60); | |
5224 | break; | |
5225 | case 624000: | |
5226 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5227 | ratio = BXT_DE_PLL_RATIO(65); | |
5228 | break; | |
5229 | case 19200: | |
5230 | /* | |
5231 | * Bypass frequency with DE PLL disabled. Init ratio, divider | |
5232 | * to suppress GCC warning. | |
5233 | */ | |
5234 | ratio = 0; | |
5235 | divider = 0; | |
5236 | break; | |
5237 | default: | |
5238 | DRM_ERROR("unsupported CDCLK freq %d", frequency); | |
5239 | ||
5240 | return; | |
5241 | } | |
5242 | ||
5243 | mutex_lock(&dev_priv->rps.hw_lock); | |
5244 | /* Inform power controller of upcoming frequency change */ | |
5245 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5246 | 0x80000000); | |
5247 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5248 | ||
5249 | if (ret) { | |
5250 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", | |
5251 | ret, frequency); | |
5252 | return; | |
5253 | } | |
5254 | ||
5255 | current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK; | |
5256 | /* convert from .1 fixpoint MHz with -1MHz offset to kHz */ | |
5257 | current_freq = current_freq * 500 + 1000; | |
5258 | ||
5259 | /* | |
5260 | * DE PLL has to be disabled when | |
5261 | * - setting to 19.2MHz (bypass, PLL isn't used) | |
5262 | * - before setting to 624MHz (PLL needs toggling) | |
5263 | * - before setting to any frequency from 624MHz (PLL needs toggling) | |
5264 | */ | |
5265 | if (frequency == 19200 || frequency == 624000 || | |
5266 | current_freq == 624000) { | |
5267 | I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE); | |
5268 | /* Timeout 200us */ | |
5269 | if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK), | |
5270 | 1)) | |
5271 | DRM_ERROR("timout waiting for DE PLL unlock\n"); | |
5272 | } | |
5273 | ||
5274 | if (frequency != 19200) { | |
5275 | uint32_t val; | |
5276 | ||
5277 | val = I915_READ(BXT_DE_PLL_CTL); | |
5278 | val &= ~BXT_DE_PLL_RATIO_MASK; | |
5279 | val |= ratio; | |
5280 | I915_WRITE(BXT_DE_PLL_CTL, val); | |
5281 | ||
5282 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); | |
5283 | /* Timeout 200us */ | |
5284 | if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1)) | |
5285 | DRM_ERROR("timeout waiting for DE PLL lock\n"); | |
5286 | ||
5287 | val = I915_READ(CDCLK_CTL); | |
5288 | val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK; | |
5289 | val |= divider; | |
5290 | /* | |
5291 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
5292 | * enable otherwise. | |
5293 | */ | |
5294 | val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5295 | if (frequency >= 500000) | |
5296 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5297 | ||
5298 | val &= ~CDCLK_FREQ_DECIMAL_MASK; | |
5299 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ | |
5300 | val |= (frequency - 1000) / 500; | |
5301 | I915_WRITE(CDCLK_CTL, val); | |
5302 | } | |
5303 | ||
5304 | mutex_lock(&dev_priv->rps.hw_lock); | |
5305 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5306 | DIV_ROUND_UP(frequency, 25000)); | |
5307 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5308 | ||
5309 | if (ret) { | |
5310 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", | |
5311 | ret, frequency); | |
5312 | return; | |
5313 | } | |
5314 | ||
5315 | dev_priv->cdclk_freq = frequency; | |
5316 | } | |
5317 | ||
5318 | void broxton_init_cdclk(struct drm_device *dev) | |
5319 | { | |
5320 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5321 | uint32_t val; | |
5322 | ||
5323 | /* | |
5324 | * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT | |
5325 | * or else the reset will hang because there is no PCH to respond. | |
5326 | * Move the handshake programming to initialization sequence. | |
5327 | * Previously was left up to BIOS. | |
5328 | */ | |
5329 | val = I915_READ(HSW_NDE_RSTWRN_OPT); | |
5330 | val &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
5331 | I915_WRITE(HSW_NDE_RSTWRN_OPT, val); | |
5332 | ||
5333 | /* Enable PG1 for cdclk */ | |
5334 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); | |
5335 | ||
5336 | /* check if cd clock is enabled */ | |
5337 | if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) { | |
5338 | DRM_DEBUG_KMS("Display already initialized\n"); | |
5339 | return; | |
5340 | } | |
5341 | ||
5342 | /* | |
5343 | * FIXME: | |
5344 | * - The initial CDCLK needs to be read from VBT. | |
5345 | * Need to make this change after VBT has changes for BXT. | |
5346 | * - check if setting the max (or any) cdclk freq is really necessary | |
5347 | * here, it belongs to modeset time | |
5348 | */ | |
5349 | broxton_set_cdclk(dev, 624000); | |
5350 | ||
5351 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
5352 | udelay(10); | |
5353 | ||
5354 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5355 | DRM_ERROR("DBuf power enable timeout!\n"); | |
5356 | } | |
5357 | ||
5358 | void broxton_uninit_cdclk(struct drm_device *dev) | |
5359 | { | |
5360 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5361 | ||
5362 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
5363 | udelay(10); | |
5364 | ||
5365 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5366 | DRM_ERROR("DBuf power disable timeout!\n"); | |
5367 | ||
5368 | /* Set minimum (bypass) frequency, in effect turning off the DE PLL */ | |
5369 | broxton_set_cdclk(dev, 19200); | |
5370 | ||
5371 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
5372 | } | |
5373 | ||
dfcab17e | 5374 | /* returns HPLL frequency in kHz */ |
f8bf63fd | 5375 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) |
30a970c6 | 5376 | { |
586f49dc | 5377 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
30a970c6 | 5378 | |
586f49dc JB |
5379 | /* Obtain SKU information */ |
5380 | mutex_lock(&dev_priv->dpio_lock); | |
5381 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
5382 | CCK_FUSE_HPLL_FREQ_MASK; | |
5383 | mutex_unlock(&dev_priv->dpio_lock); | |
30a970c6 | 5384 | |
dfcab17e | 5385 | return vco_freq[hpll_freq] * 1000; |
30a970c6 JB |
5386 | } |
5387 | ||
f8bf63fd VS |
5388 | static void vlv_update_cdclk(struct drm_device *dev) |
5389 | { | |
5390 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5391 | ||
164dfd28 | 5392 | dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev); |
43dc52c3 | 5393 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", |
164dfd28 | 5394 | dev_priv->cdclk_freq); |
f8bf63fd VS |
5395 | |
5396 | /* | |
5397 | * Program the gmbus_freq based on the cdclk frequency. | |
5398 | * BSpec erroneously claims we should aim for 4MHz, but | |
5399 | * in fact 1MHz is the correct frequency. | |
5400 | */ | |
164dfd28 | 5401 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); |
f8bf63fd VS |
5402 | } |
5403 | ||
30a970c6 JB |
5404 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
5405 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
5406 | { | |
5407 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5408 | u32 val, cmd; | |
5409 | ||
164dfd28 VK |
5410 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5411 | != dev_priv->cdclk_freq); | |
d60c4473 | 5412 | |
dfcab17e | 5413 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 5414 | cmd = 2; |
dfcab17e | 5415 | else if (cdclk == 266667) |
30a970c6 JB |
5416 | cmd = 1; |
5417 | else | |
5418 | cmd = 0; | |
5419 | ||
5420 | mutex_lock(&dev_priv->rps.hw_lock); | |
5421 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5422 | val &= ~DSPFREQGUAR_MASK; | |
5423 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
5424 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5425 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5426 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
5427 | 50)) { | |
5428 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5429 | } | |
5430 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5431 | ||
dfcab17e | 5432 | if (cdclk == 400000) { |
6bcda4f0 | 5433 | u32 divider; |
30a970c6 | 5434 | |
6bcda4f0 | 5435 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 JB |
5436 | |
5437 | mutex_lock(&dev_priv->dpio_lock); | |
5438 | /* adjust cdclk divider */ | |
5439 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
9cf33db5 | 5440 | val &= ~DISPLAY_FREQUENCY_VALUES; |
30a970c6 JB |
5441 | val |= divider; |
5442 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
5443 | |
5444 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
5445 | DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), | |
5446 | 50)) | |
5447 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
5448 | mutex_unlock(&dev_priv->dpio_lock); |
5449 | } | |
5450 | ||
5451 | mutex_lock(&dev_priv->dpio_lock); | |
5452 | /* adjust self-refresh exit latency value */ | |
5453 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
5454 | val &= ~0x7f; | |
5455 | ||
5456 | /* | |
5457 | * For high bandwidth configs, we set a higher latency in the bunit | |
5458 | * so that the core display fetch happens in time to avoid underruns. | |
5459 | */ | |
dfcab17e | 5460 | if (cdclk == 400000) |
30a970c6 JB |
5461 | val |= 4500 / 250; /* 4.5 usec */ |
5462 | else | |
5463 | val |= 3000 / 250; /* 3.0 usec */ | |
5464 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
5465 | mutex_unlock(&dev_priv->dpio_lock); | |
5466 | ||
f8bf63fd | 5467 | vlv_update_cdclk(dev); |
30a970c6 JB |
5468 | } |
5469 | ||
383c5a6a VS |
5470 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
5471 | { | |
5472 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5473 | u32 val, cmd; | |
5474 | ||
164dfd28 VK |
5475 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5476 | != dev_priv->cdclk_freq); | |
383c5a6a VS |
5477 | |
5478 | switch (cdclk) { | |
383c5a6a VS |
5479 | case 333333: |
5480 | case 320000: | |
383c5a6a | 5481 | case 266667: |
383c5a6a | 5482 | case 200000: |
383c5a6a VS |
5483 | break; |
5484 | default: | |
5f77eeb0 | 5485 | MISSING_CASE(cdclk); |
383c5a6a VS |
5486 | return; |
5487 | } | |
5488 | ||
9d0d3fda VS |
5489 | /* |
5490 | * Specs are full of misinformation, but testing on actual | |
5491 | * hardware has shown that we just need to write the desired | |
5492 | * CCK divider into the Punit register. | |
5493 | */ | |
5494 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
5495 | ||
383c5a6a VS |
5496 | mutex_lock(&dev_priv->rps.hw_lock); |
5497 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5498 | val &= ~DSPFREQGUAR_MASK_CHV; | |
5499 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
5500 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5501 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5502 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
5503 | 50)) { | |
5504 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5505 | } | |
5506 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5507 | ||
5508 | vlv_update_cdclk(dev); | |
5509 | } | |
5510 | ||
30a970c6 JB |
5511 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
5512 | int max_pixclk) | |
5513 | { | |
6bcda4f0 | 5514 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
6cca3195 | 5515 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
29dc7ef3 | 5516 | |
30a970c6 JB |
5517 | /* |
5518 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
5519 | * 200MHz | |
5520 | * 267MHz | |
29dc7ef3 | 5521 | * 320/333MHz (depends on HPLL freq) |
6cca3195 VS |
5522 | * 400MHz (VLV only) |
5523 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) | |
5524 | * of the lower bin and adjust if needed. | |
e37c67a1 VS |
5525 | * |
5526 | * We seem to get an unstable or solid color picture at 200MHz. | |
5527 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
5528 | * are off. | |
30a970c6 | 5529 | */ |
6cca3195 VS |
5530 | if (!IS_CHERRYVIEW(dev_priv) && |
5531 | max_pixclk > freq_320*limit/100) | |
dfcab17e | 5532 | return 400000; |
6cca3195 | 5533 | else if (max_pixclk > 266667*limit/100) |
29dc7ef3 | 5534 | return freq_320; |
e37c67a1 | 5535 | else if (max_pixclk > 0) |
dfcab17e | 5536 | return 266667; |
e37c67a1 VS |
5537 | else |
5538 | return 200000; | |
30a970c6 JB |
5539 | } |
5540 | ||
f8437dd1 VK |
5541 | static int broxton_calc_cdclk(struct drm_i915_private *dev_priv, |
5542 | int max_pixclk) | |
5543 | { | |
5544 | /* | |
5545 | * FIXME: | |
5546 | * - remove the guardband, it's not needed on BXT | |
5547 | * - set 19.2MHz bypass frequency if there are no active pipes | |
5548 | */ | |
5549 | if (max_pixclk > 576000*9/10) | |
5550 | return 624000; | |
5551 | else if (max_pixclk > 384000*9/10) | |
5552 | return 576000; | |
5553 | else if (max_pixclk > 288000*9/10) | |
5554 | return 384000; | |
5555 | else if (max_pixclk > 144000*9/10) | |
5556 | return 288000; | |
5557 | else | |
5558 | return 144000; | |
5559 | } | |
5560 | ||
2f2d7aa1 | 5561 | /* compute the max pixel clock for new configuration */ |
304603f4 | 5562 | static int intel_mode_max_pixclk(struct drm_atomic_state *state) |
30a970c6 | 5563 | { |
304603f4 | 5564 | struct drm_device *dev = state->dev; |
30a970c6 | 5565 | struct intel_crtc *intel_crtc; |
304603f4 | 5566 | struct intel_crtc_state *crtc_state; |
30a970c6 JB |
5567 | int max_pixclk = 0; |
5568 | ||
d3fcc808 | 5569 | for_each_intel_crtc(dev, intel_crtc) { |
304603f4 ACO |
5570 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
5571 | if (IS_ERR(crtc_state)) | |
5572 | return PTR_ERR(crtc_state); | |
5573 | ||
5574 | if (!crtc_state->base.enable) | |
5575 | continue; | |
5576 | ||
5577 | max_pixclk = max(max_pixclk, | |
5578 | crtc_state->base.adjusted_mode.crtc_clock); | |
30a970c6 JB |
5579 | } |
5580 | ||
5581 | return max_pixclk; | |
5582 | } | |
5583 | ||
304603f4 | 5584 | static int valleyview_modeset_global_pipes(struct drm_atomic_state *state, |
2f2d7aa1 | 5585 | unsigned *prepare_pipes) |
30a970c6 | 5586 | { |
304603f4 | 5587 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
30a970c6 | 5588 | struct intel_crtc *intel_crtc; |
304603f4 | 5589 | int max_pixclk = intel_mode_max_pixclk(state); |
f8437dd1 | 5590 | int cdclk; |
304603f4 ACO |
5591 | |
5592 | if (max_pixclk < 0) | |
5593 | return max_pixclk; | |
30a970c6 | 5594 | |
f8437dd1 VK |
5595 | if (IS_VALLEYVIEW(dev_priv)) |
5596 | cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); | |
5597 | else | |
5598 | cdclk = broxton_calc_cdclk(dev_priv, max_pixclk); | |
5599 | ||
5600 | if (cdclk == dev_priv->cdclk_freq) | |
304603f4 | 5601 | return 0; |
30a970c6 | 5602 | |
2f2d7aa1 | 5603 | /* disable/enable all currently active pipes while we change cdclk */ |
304603f4 | 5604 | for_each_intel_crtc(state->dev, intel_crtc) |
83d65738 | 5605 | if (intel_crtc->base.state->enable) |
30a970c6 | 5606 | *prepare_pipes |= (1 << intel_crtc->pipe); |
304603f4 ACO |
5607 | |
5608 | return 0; | |
30a970c6 JB |
5609 | } |
5610 | ||
1e69cd74 VS |
5611 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
5612 | { | |
5613 | unsigned int credits, default_credits; | |
5614 | ||
5615 | if (IS_CHERRYVIEW(dev_priv)) | |
5616 | default_credits = PFI_CREDIT(12); | |
5617 | else | |
5618 | default_credits = PFI_CREDIT(8); | |
5619 | ||
164dfd28 | 5620 | if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) { |
1e69cd74 VS |
5621 | /* CHV suggested value is 31 or 63 */ |
5622 | if (IS_CHERRYVIEW(dev_priv)) | |
5623 | credits = PFI_CREDIT_31; | |
5624 | else | |
5625 | credits = PFI_CREDIT(15); | |
5626 | } else { | |
5627 | credits = default_credits; | |
5628 | } | |
5629 | ||
5630 | /* | |
5631 | * WA - write default credits before re-programming | |
5632 | * FIXME: should we also set the resend bit here? | |
5633 | */ | |
5634 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
5635 | default_credits); | |
5636 | ||
5637 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
5638 | credits | PFI_CREDIT_RESEND); | |
5639 | ||
5640 | /* | |
5641 | * FIXME is this guaranteed to clear | |
5642 | * immediately or should we poll for it? | |
5643 | */ | |
5644 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
5645 | } | |
5646 | ||
679dacd4 | 5647 | static void valleyview_modeset_global_resources(struct drm_atomic_state *state) |
30a970c6 | 5648 | { |
679dacd4 | 5649 | struct drm_device *dev = state->dev; |
30a970c6 | 5650 | struct drm_i915_private *dev_priv = dev->dev_private; |
304603f4 ACO |
5651 | int max_pixclk = intel_mode_max_pixclk(state); |
5652 | int req_cdclk; | |
5653 | ||
5654 | /* The only reason this can fail is if we fail to add the crtc_state | |
5655 | * to the atomic state. But that can't happen since the call to | |
5656 | * intel_mode_max_pixclk() in valleyview_modeset_global_pipes() (which | |
5657 | * can't have failed otherwise the mode set would be aborted) added all | |
5658 | * the states already. */ | |
5659 | if (WARN_ON(max_pixclk < 0)) | |
5660 | return; | |
5661 | ||
5662 | req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); | |
30a970c6 | 5663 | |
164dfd28 | 5664 | if (req_cdclk != dev_priv->cdclk_freq) { |
738c05c0 ID |
5665 | /* |
5666 | * FIXME: We can end up here with all power domains off, yet | |
5667 | * with a CDCLK frequency other than the minimum. To account | |
5668 | * for this take the PIPE-A power domain, which covers the HW | |
5669 | * blocks needed for the following programming. This can be | |
5670 | * removed once it's guaranteed that we get here either with | |
5671 | * the minimum CDCLK set, or the required power domains | |
5672 | * enabled. | |
5673 | */ | |
5674 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
5675 | ||
383c5a6a VS |
5676 | if (IS_CHERRYVIEW(dev)) |
5677 | cherryview_set_cdclk(dev, req_cdclk); | |
5678 | else | |
5679 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 | 5680 | |
1e69cd74 VS |
5681 | vlv_program_pfi_credits(dev_priv); |
5682 | ||
738c05c0 | 5683 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
383c5a6a | 5684 | } |
30a970c6 JB |
5685 | } |
5686 | ||
89b667f8 JB |
5687 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
5688 | { | |
5689 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 5690 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 JB |
5691 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5692 | struct intel_encoder *encoder; | |
5693 | int pipe = intel_crtc->pipe; | |
23538ef1 | 5694 | bool is_dsi; |
89b667f8 | 5695 | |
83d65738 | 5696 | WARN_ON(!crtc->state->enable); |
89b667f8 JB |
5697 | |
5698 | if (intel_crtc->active) | |
5699 | return; | |
5700 | ||
409ee761 | 5701 | is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI); |
8525a235 | 5702 | |
1ae0d137 VS |
5703 | if (!is_dsi) { |
5704 | if (IS_CHERRYVIEW(dev)) | |
6e3c9717 | 5705 | chv_prepare_pll(intel_crtc, intel_crtc->config); |
1ae0d137 | 5706 | else |
6e3c9717 | 5707 | vlv_prepare_pll(intel_crtc, intel_crtc->config); |
1ae0d137 | 5708 | } |
5b18e57c | 5709 | |
6e3c9717 | 5710 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 5711 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
5712 | |
5713 | intel_set_pipe_timings(intel_crtc); | |
5714 | ||
c14b0485 VS |
5715 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
5716 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5717 | ||
5718 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
5719 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
5720 | } | |
5721 | ||
5b18e57c DV |
5722 | i9xx_set_pipeconf(intel_crtc); |
5723 | ||
89b667f8 | 5724 | intel_crtc->active = true; |
89b667f8 | 5725 | |
a72e4c9f | 5726 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 5727 | |
89b667f8 JB |
5728 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5729 | if (encoder->pre_pll_enable) | |
5730 | encoder->pre_pll_enable(encoder); | |
5731 | ||
9d556c99 CML |
5732 | if (!is_dsi) { |
5733 | if (IS_CHERRYVIEW(dev)) | |
6e3c9717 | 5734 | chv_enable_pll(intel_crtc, intel_crtc->config); |
9d556c99 | 5735 | else |
6e3c9717 | 5736 | vlv_enable_pll(intel_crtc, intel_crtc->config); |
9d556c99 | 5737 | } |
89b667f8 JB |
5738 | |
5739 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
5740 | if (encoder->pre_enable) | |
5741 | encoder->pre_enable(encoder); | |
5742 | ||
2dd24552 JB |
5743 | i9xx_pfit_enable(intel_crtc); |
5744 | ||
63cbb074 VS |
5745 | intel_crtc_load_lut(crtc); |
5746 | ||
f37fcc2a | 5747 | intel_update_watermarks(crtc); |
e1fdc473 | 5748 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 5749 | |
4b3a9526 VS |
5750 | assert_vblank_disabled(crtc); |
5751 | drm_crtc_vblank_on(crtc); | |
5752 | ||
f9b61ff6 DV |
5753 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5754 | encoder->enable(encoder); | |
5755 | ||
9ab0460b | 5756 | intel_crtc_enable_planes(crtc); |
d40d9187 | 5757 | |
56b80e1f | 5758 | /* Underruns don't raise interrupts, so check manually. */ |
a72e4c9f | 5759 | i9xx_check_fifo_underruns(dev_priv); |
89b667f8 JB |
5760 | } |
5761 | ||
f13c2ef3 DV |
5762 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
5763 | { | |
5764 | struct drm_device *dev = crtc->base.dev; | |
5765 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5766 | ||
6e3c9717 ACO |
5767 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
5768 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
f13c2ef3 DV |
5769 | } |
5770 | ||
0b8765c6 | 5771 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
5772 | { |
5773 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 5774 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 5775 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 5776 | struct intel_encoder *encoder; |
79e53945 | 5777 | int pipe = intel_crtc->pipe; |
79e53945 | 5778 | |
83d65738 | 5779 | WARN_ON(!crtc->state->enable); |
08a48469 | 5780 | |
f7abfe8b CW |
5781 | if (intel_crtc->active) |
5782 | return; | |
5783 | ||
f13c2ef3 DV |
5784 | i9xx_set_pll_dividers(intel_crtc); |
5785 | ||
6e3c9717 | 5786 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 5787 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
5788 | |
5789 | intel_set_pipe_timings(intel_crtc); | |
5790 | ||
5b18e57c DV |
5791 | i9xx_set_pipeconf(intel_crtc); |
5792 | ||
f7abfe8b | 5793 | intel_crtc->active = true; |
6b383a7f | 5794 | |
4a3436e8 | 5795 | if (!IS_GEN2(dev)) |
a72e4c9f | 5796 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 5797 | |
9d6d9f19 MK |
5798 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5799 | if (encoder->pre_enable) | |
5800 | encoder->pre_enable(encoder); | |
5801 | ||
f6736a1a DV |
5802 | i9xx_enable_pll(intel_crtc); |
5803 | ||
2dd24552 JB |
5804 | i9xx_pfit_enable(intel_crtc); |
5805 | ||
63cbb074 VS |
5806 | intel_crtc_load_lut(crtc); |
5807 | ||
f37fcc2a | 5808 | intel_update_watermarks(crtc); |
e1fdc473 | 5809 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 5810 | |
4b3a9526 VS |
5811 | assert_vblank_disabled(crtc); |
5812 | drm_crtc_vblank_on(crtc); | |
5813 | ||
f9b61ff6 DV |
5814 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5815 | encoder->enable(encoder); | |
5816 | ||
9ab0460b | 5817 | intel_crtc_enable_planes(crtc); |
d40d9187 | 5818 | |
4a3436e8 VS |
5819 | /* |
5820 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
5821 | * So don't enable underrun reporting before at least some planes | |
5822 | * are enabled. | |
5823 | * FIXME: Need to fix the logic to work when we turn off all planes | |
5824 | * but leave the pipe running. | |
5825 | */ | |
5826 | if (IS_GEN2(dev)) | |
a72e4c9f | 5827 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 5828 | |
56b80e1f | 5829 | /* Underruns don't raise interrupts, so check manually. */ |
a72e4c9f | 5830 | i9xx_check_fifo_underruns(dev_priv); |
0b8765c6 | 5831 | } |
79e53945 | 5832 | |
87476d63 DV |
5833 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
5834 | { | |
5835 | struct drm_device *dev = crtc->base.dev; | |
5836 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 5837 | |
6e3c9717 | 5838 | if (!crtc->config->gmch_pfit.control) |
328d8e82 | 5839 | return; |
87476d63 | 5840 | |
328d8e82 | 5841 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 5842 | |
328d8e82 DV |
5843 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
5844 | I915_READ(PFIT_CONTROL)); | |
5845 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
5846 | } |
5847 | ||
0b8765c6 JB |
5848 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
5849 | { | |
5850 | struct drm_device *dev = crtc->dev; | |
5851 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5852 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 5853 | struct intel_encoder *encoder; |
0b8765c6 | 5854 | int pipe = intel_crtc->pipe; |
ef9c3aee | 5855 | |
f7abfe8b CW |
5856 | if (!intel_crtc->active) |
5857 | return; | |
5858 | ||
4a3436e8 VS |
5859 | /* |
5860 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
5861 | * So diasble underrun reporting before all the planes get disabled. | |
5862 | * FIXME: Need to fix the logic to work when we turn off all planes | |
5863 | * but leave the pipe running. | |
5864 | */ | |
5865 | if (IS_GEN2(dev)) | |
a72e4c9f | 5866 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
4a3436e8 | 5867 | |
564ed191 ID |
5868 | /* |
5869 | * Vblank time updates from the shadow to live plane control register | |
5870 | * are blocked if the memory self-refresh mode is active at that | |
5871 | * moment. So to make sure the plane gets truly disabled, disable | |
5872 | * first the self-refresh mode. The self-refresh enable bit in turn | |
5873 | * will be checked/applied by the HW only at the next frame start | |
5874 | * event which is after the vblank start event, so we need to have a | |
5875 | * wait-for-vblank between disabling the plane and the pipe. | |
5876 | */ | |
5877 | intel_set_memory_cxsr(dev_priv, false); | |
9ab0460b VS |
5878 | intel_crtc_disable_planes(crtc); |
5879 | ||
6304cd91 VS |
5880 | /* |
5881 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
5882 | * wait for planes to fully turn off before disabling the pipe. | |
564ed191 ID |
5883 | * We also need to wait on all gmch platforms because of the |
5884 | * self-refresh mode constraint explained above. | |
6304cd91 | 5885 | */ |
564ed191 | 5886 | intel_wait_for_vblank(dev, pipe); |
6304cd91 | 5887 | |
4b3a9526 VS |
5888 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5889 | encoder->disable(encoder); | |
5890 | ||
f9b61ff6 DV |
5891 | drm_crtc_vblank_off(crtc); |
5892 | assert_vblank_disabled(crtc); | |
5893 | ||
575f7ab7 | 5894 | intel_disable_pipe(intel_crtc); |
24a1f16d | 5895 | |
87476d63 | 5896 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 5897 | |
89b667f8 JB |
5898 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5899 | if (encoder->post_disable) | |
5900 | encoder->post_disable(encoder); | |
5901 | ||
409ee761 | 5902 | if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) { |
076ed3b2 CML |
5903 | if (IS_CHERRYVIEW(dev)) |
5904 | chv_disable_pll(dev_priv, pipe); | |
5905 | else if (IS_VALLEYVIEW(dev)) | |
5906 | vlv_disable_pll(dev_priv, pipe); | |
5907 | else | |
1c4e0274 | 5908 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 5909 | } |
0b8765c6 | 5910 | |
4a3436e8 | 5911 | if (!IS_GEN2(dev)) |
a72e4c9f | 5912 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
4a3436e8 | 5913 | |
f7abfe8b | 5914 | intel_crtc->active = false; |
46ba614c | 5915 | intel_update_watermarks(crtc); |
f37fcc2a | 5916 | |
efa9624e | 5917 | mutex_lock(&dev->struct_mutex); |
7ff0ebcc | 5918 | intel_fbc_update(dev); |
efa9624e | 5919 | mutex_unlock(&dev->struct_mutex); |
0b8765c6 JB |
5920 | } |
5921 | ||
ee7b9f93 JB |
5922 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
5923 | { | |
5924 | } | |
5925 | ||
b04c5bd6 BF |
5926 | /* Master function to enable/disable CRTC and corresponding power wells */ |
5927 | void intel_crtc_control(struct drm_crtc *crtc, bool enable) | |
976f8a20 DV |
5928 | { |
5929 | struct drm_device *dev = crtc->dev; | |
5930 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0e572fe7 | 5931 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
0e572fe7 DV |
5932 | enum intel_display_power_domain domain; |
5933 | unsigned long domains; | |
976f8a20 | 5934 | |
0e572fe7 DV |
5935 | if (enable) { |
5936 | if (!intel_crtc->active) { | |
e1e9fb84 DV |
5937 | domains = get_crtc_power_domains(crtc); |
5938 | for_each_power_domain(domain, domains) | |
5939 | intel_display_power_get(dev_priv, domain); | |
5940 | intel_crtc->enabled_power_domains = domains; | |
0e572fe7 DV |
5941 | |
5942 | dev_priv->display.crtc_enable(crtc); | |
5943 | } | |
5944 | } else { | |
5945 | if (intel_crtc->active) { | |
5946 | dev_priv->display.crtc_disable(crtc); | |
5947 | ||
e1e9fb84 DV |
5948 | domains = intel_crtc->enabled_power_domains; |
5949 | for_each_power_domain(domain, domains) | |
5950 | intel_display_power_put(dev_priv, domain); | |
5951 | intel_crtc->enabled_power_domains = 0; | |
0e572fe7 DV |
5952 | } |
5953 | } | |
b04c5bd6 BF |
5954 | } |
5955 | ||
5956 | /** | |
5957 | * Sets the power management mode of the pipe and plane. | |
5958 | */ | |
5959 | void intel_crtc_update_dpms(struct drm_crtc *crtc) | |
5960 | { | |
5961 | struct drm_device *dev = crtc->dev; | |
5962 | struct intel_encoder *intel_encoder; | |
5963 | bool enable = false; | |
5964 | ||
5965 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) | |
5966 | enable |= intel_encoder->connectors_active; | |
5967 | ||
5968 | intel_crtc_control(crtc, enable); | |
976f8a20 DV |
5969 | } |
5970 | ||
cdd59983 CW |
5971 | static void intel_crtc_disable(struct drm_crtc *crtc) |
5972 | { | |
cdd59983 | 5973 | struct drm_device *dev = crtc->dev; |
976f8a20 | 5974 | struct drm_connector *connector; |
ee7b9f93 | 5975 | struct drm_i915_private *dev_priv = dev->dev_private; |
cdd59983 | 5976 | |
976f8a20 | 5977 | /* crtc should still be enabled when we disable it. */ |
83d65738 | 5978 | WARN_ON(!crtc->state->enable); |
976f8a20 DV |
5979 | |
5980 | dev_priv->display.crtc_disable(crtc); | |
ee7b9f93 JB |
5981 | dev_priv->display.off(crtc); |
5982 | ||
70a101f8 | 5983 | drm_plane_helper_disable(crtc->primary); |
976f8a20 DV |
5984 | |
5985 | /* Update computed state. */ | |
5986 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
5987 | if (!connector->encoder || !connector->encoder->crtc) | |
5988 | continue; | |
5989 | ||
5990 | if (connector->encoder->crtc != crtc) | |
5991 | continue; | |
5992 | ||
5993 | connector->dpms = DRM_MODE_DPMS_OFF; | |
5994 | to_intel_encoder(connector->encoder)->connectors_active = false; | |
cdd59983 CW |
5995 | } |
5996 | } | |
5997 | ||
ea5b213a | 5998 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 5999 | { |
4ef69c7a | 6000 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 6001 | |
ea5b213a CW |
6002 | drm_encoder_cleanup(encoder); |
6003 | kfree(intel_encoder); | |
7e7d76c3 JB |
6004 | } |
6005 | ||
9237329d | 6006 | /* Simple dpms helper for encoders with just one connector, no cloning and only |
5ab432ef DV |
6007 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
6008 | * state of the entire output pipe. */ | |
9237329d | 6009 | static void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
7e7d76c3 | 6010 | { |
5ab432ef DV |
6011 | if (mode == DRM_MODE_DPMS_ON) { |
6012 | encoder->connectors_active = true; | |
6013 | ||
b2cabb0e | 6014 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef DV |
6015 | } else { |
6016 | encoder->connectors_active = false; | |
6017 | ||
b2cabb0e | 6018 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef | 6019 | } |
79e53945 JB |
6020 | } |
6021 | ||
0a91ca29 DV |
6022 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
6023 | * internal consistency). */ | |
b980514c | 6024 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 6025 | { |
0a91ca29 DV |
6026 | if (connector->get_hw_state(connector)) { |
6027 | struct intel_encoder *encoder = connector->encoder; | |
6028 | struct drm_crtc *crtc; | |
6029 | bool encoder_enabled; | |
6030 | enum pipe pipe; | |
6031 | ||
6032 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
6033 | connector->base.base.id, | |
c23cc417 | 6034 | connector->base.name); |
0a91ca29 | 6035 | |
0e32b39c DA |
6036 | /* there is no real hw state for MST connectors */ |
6037 | if (connector->mst_port) | |
6038 | return; | |
6039 | ||
e2c719b7 | 6040 | I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, |
0a91ca29 | 6041 | "wrong connector dpms state\n"); |
e2c719b7 | 6042 | I915_STATE_WARN(connector->base.encoder != &encoder->base, |
0a91ca29 | 6043 | "active connector not linked to encoder\n"); |
0a91ca29 | 6044 | |
36cd7444 | 6045 | if (encoder) { |
e2c719b7 | 6046 | I915_STATE_WARN(!encoder->connectors_active, |
36cd7444 DA |
6047 | "encoder->connectors_active not set\n"); |
6048 | ||
6049 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); | |
e2c719b7 RC |
6050 | I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n"); |
6051 | if (I915_STATE_WARN_ON(!encoder->base.crtc)) | |
36cd7444 | 6052 | return; |
0a91ca29 | 6053 | |
36cd7444 | 6054 | crtc = encoder->base.crtc; |
0a91ca29 | 6055 | |
83d65738 MR |
6056 | I915_STATE_WARN(!crtc->state->enable, |
6057 | "crtc not enabled\n"); | |
e2c719b7 RC |
6058 | I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); |
6059 | I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe, | |
36cd7444 DA |
6060 | "encoder active on the wrong pipe\n"); |
6061 | } | |
0a91ca29 | 6062 | } |
79e53945 JB |
6063 | } |
6064 | ||
9bdbd0b9 ACO |
6065 | int intel_connector_init(struct intel_connector *connector) |
6066 | { | |
6067 | struct drm_connector_state *connector_state; | |
6068 | ||
6069 | connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL); | |
6070 | if (!connector_state) | |
6071 | return -ENOMEM; | |
6072 | ||
6073 | connector->base.state = connector_state; | |
6074 | return 0; | |
6075 | } | |
6076 | ||
6077 | struct intel_connector *intel_connector_alloc(void) | |
6078 | { | |
6079 | struct intel_connector *connector; | |
6080 | ||
6081 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
6082 | if (!connector) | |
6083 | return NULL; | |
6084 | ||
6085 | if (intel_connector_init(connector) < 0) { | |
6086 | kfree(connector); | |
6087 | return NULL; | |
6088 | } | |
6089 | ||
6090 | return connector; | |
6091 | } | |
6092 | ||
5ab432ef DV |
6093 | /* Even simpler default implementation, if there's really no special case to |
6094 | * consider. */ | |
6095 | void intel_connector_dpms(struct drm_connector *connector, int mode) | |
79e53945 | 6096 | { |
5ab432ef DV |
6097 | /* All the simple cases only support two dpms states. */ |
6098 | if (mode != DRM_MODE_DPMS_ON) | |
6099 | mode = DRM_MODE_DPMS_OFF; | |
d4270e57 | 6100 | |
5ab432ef DV |
6101 | if (mode == connector->dpms) |
6102 | return; | |
6103 | ||
6104 | connector->dpms = mode; | |
6105 | ||
6106 | /* Only need to change hw state when actually enabled */ | |
c9976dcf CW |
6107 | if (connector->encoder) |
6108 | intel_encoder_dpms(to_intel_encoder(connector->encoder), mode); | |
0a91ca29 | 6109 | |
b980514c | 6110 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
6111 | } |
6112 | ||
f0947c37 DV |
6113 | /* Simple connector->get_hw_state implementation for encoders that support only |
6114 | * one connector and no cloning and hence the encoder state determines the state | |
6115 | * of the connector. */ | |
6116 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 6117 | { |
24929352 | 6118 | enum pipe pipe = 0; |
f0947c37 | 6119 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 6120 | |
f0947c37 | 6121 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
6122 | } |
6123 | ||
6d293983 | 6124 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 6125 | { |
6d293983 ACO |
6126 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
6127 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
6128 | |
6129 | return 0; | |
6130 | } | |
6131 | ||
6d293983 | 6132 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 6133 | struct intel_crtc_state *pipe_config) |
1857e1da | 6134 | { |
6d293983 ACO |
6135 | struct drm_atomic_state *state = pipe_config->base.state; |
6136 | struct intel_crtc *other_crtc; | |
6137 | struct intel_crtc_state *other_crtc_state; | |
6138 | ||
1857e1da DV |
6139 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
6140 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6141 | if (pipe_config->fdi_lanes > 4) { | |
6142 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
6143 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6144 | return -EINVAL; |
1857e1da DV |
6145 | } |
6146 | ||
bafb6553 | 6147 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
6148 | if (pipe_config->fdi_lanes > 2) { |
6149 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
6150 | pipe_config->fdi_lanes); | |
6d293983 | 6151 | return -EINVAL; |
1857e1da | 6152 | } else { |
6d293983 | 6153 | return 0; |
1857e1da DV |
6154 | } |
6155 | } | |
6156 | ||
6157 | if (INTEL_INFO(dev)->num_pipes == 2) | |
6d293983 | 6158 | return 0; |
1857e1da DV |
6159 | |
6160 | /* Ivybridge 3 pipe is really complicated */ | |
6161 | switch (pipe) { | |
6162 | case PIPE_A: | |
6d293983 | 6163 | return 0; |
1857e1da | 6164 | case PIPE_B: |
6d293983 ACO |
6165 | if (pipe_config->fdi_lanes <= 2) |
6166 | return 0; | |
6167 | ||
6168 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C)); | |
6169 | other_crtc_state = | |
6170 | intel_atomic_get_crtc_state(state, other_crtc); | |
6171 | if (IS_ERR(other_crtc_state)) | |
6172 | return PTR_ERR(other_crtc_state); | |
6173 | ||
6174 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
6175 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
6176 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6177 | return -EINVAL; |
1857e1da | 6178 | } |
6d293983 | 6179 | return 0; |
1857e1da | 6180 | case PIPE_C: |
251cc67c VS |
6181 | if (pipe_config->fdi_lanes > 2) { |
6182 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
6183 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6184 | return -EINVAL; |
251cc67c | 6185 | } |
6d293983 ACO |
6186 | |
6187 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B)); | |
6188 | other_crtc_state = | |
6189 | intel_atomic_get_crtc_state(state, other_crtc); | |
6190 | if (IS_ERR(other_crtc_state)) | |
6191 | return PTR_ERR(other_crtc_state); | |
6192 | ||
6193 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 6194 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 6195 | return -EINVAL; |
1857e1da | 6196 | } |
6d293983 | 6197 | return 0; |
1857e1da DV |
6198 | default: |
6199 | BUG(); | |
6200 | } | |
6201 | } | |
6202 | ||
e29c22c0 DV |
6203 | #define RETRY 1 |
6204 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 6205 | struct intel_crtc_state *pipe_config) |
877d48d5 | 6206 | { |
1857e1da | 6207 | struct drm_device *dev = intel_crtc->base.dev; |
2d112de7 | 6208 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
6209 | int lane, link_bw, fdi_dotclock, ret; |
6210 | bool needs_recompute = false; | |
877d48d5 | 6211 | |
e29c22c0 | 6212 | retry: |
877d48d5 DV |
6213 | /* FDI is a binary signal running at ~2.7GHz, encoding |
6214 | * each output octet as 10 bits. The actual frequency | |
6215 | * is stored as a divider into a 100MHz clock, and the | |
6216 | * mode pixel clock is stored in units of 1KHz. | |
6217 | * Hence the bw of each lane in terms of the mode signal | |
6218 | * is: | |
6219 | */ | |
6220 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
6221 | ||
241bfc38 | 6222 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 6223 | |
2bd89a07 | 6224 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
6225 | pipe_config->pipe_bpp); |
6226 | ||
6227 | pipe_config->fdi_lanes = lane; | |
6228 | ||
2bd89a07 | 6229 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 6230 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 6231 | |
6d293983 ACO |
6232 | ret = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
6233 | intel_crtc->pipe, pipe_config); | |
6234 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { | |
e29c22c0 DV |
6235 | pipe_config->pipe_bpp -= 2*3; |
6236 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
6237 | pipe_config->pipe_bpp); | |
6238 | needs_recompute = true; | |
6239 | pipe_config->bw_constrained = true; | |
6240 | ||
6241 | goto retry; | |
6242 | } | |
6243 | ||
6244 | if (needs_recompute) | |
6245 | return RETRY; | |
6246 | ||
6d293983 | 6247 | return ret; |
877d48d5 DV |
6248 | } |
6249 | ||
42db64ef | 6250 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5cec258b | 6251 | struct intel_crtc_state *pipe_config) |
42db64ef | 6252 | { |
d330a953 | 6253 | pipe_config->ips_enabled = i915.enable_ips && |
3c4ca58c | 6254 | hsw_crtc_supports_ips(crtc) && |
b6dfdc9b | 6255 | pipe_config->pipe_bpp <= 24; |
42db64ef PZ |
6256 | } |
6257 | ||
a43f6e0f | 6258 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
5cec258b | 6259 | struct intel_crtc_state *pipe_config) |
79e53945 | 6260 | { |
a43f6e0f | 6261 | struct drm_device *dev = crtc->base.dev; |
8bd31e67 | 6262 | struct drm_i915_private *dev_priv = dev->dev_private; |
2d112de7 | 6263 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
d03c93d4 | 6264 | int ret; |
89749350 | 6265 | |
ad3a4479 | 6266 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 | 6267 | if (INTEL_INFO(dev)->gen < 4) { |
cf532bb2 VS |
6268 | int clock_limit = |
6269 | dev_priv->display.get_display_clock_speed(dev); | |
6270 | ||
6271 | /* | |
6272 | * Enable pixel doubling when the dot clock | |
6273 | * is > 90% of the (display) core speed. | |
6274 | * | |
b397c96b VS |
6275 | * GDG double wide on either pipe, |
6276 | * otherwise pipe A only. | |
cf532bb2 | 6277 | */ |
b397c96b | 6278 | if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && |
241bfc38 | 6279 | adjusted_mode->crtc_clock > clock_limit * 9 / 10) { |
ad3a4479 | 6280 | clock_limit *= 2; |
cf532bb2 | 6281 | pipe_config->double_wide = true; |
ad3a4479 VS |
6282 | } |
6283 | ||
241bfc38 | 6284 | if (adjusted_mode->crtc_clock > clock_limit * 9 / 10) |
e29c22c0 | 6285 | return -EINVAL; |
2c07245f | 6286 | } |
89749350 | 6287 | |
1d1d0e27 VS |
6288 | /* |
6289 | * Pipe horizontal size must be even in: | |
6290 | * - DVO ganged mode | |
6291 | * - LVDS dual channel mode | |
6292 | * - Double wide pipe | |
6293 | */ | |
a93e255f | 6294 | if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
6295 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
6296 | pipe_config->pipe_src_w &= ~1; | |
6297 | ||
8693a824 DL |
6298 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
6299 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
6300 | */ |
6301 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
6302 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) | |
e29c22c0 | 6303 | return -EINVAL; |
44f46b42 | 6304 | |
f5adf94e | 6305 | if (HAS_IPS(dev)) |
a43f6e0f DV |
6306 | hsw_compute_ips_config(crtc, pipe_config); |
6307 | ||
877d48d5 | 6308 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 6309 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 6310 | |
d03c93d4 CK |
6311 | /* FIXME: remove below call once atomic mode set is place and all crtc |
6312 | * related checks called from atomic_crtc_check function */ | |
6313 | ret = 0; | |
6314 | DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n", | |
6315 | crtc, pipe_config->base.state); | |
6316 | ret = intel_atomic_setup_scalers(dev, crtc, pipe_config); | |
6317 | ||
6318 | return ret; | |
79e53945 JB |
6319 | } |
6320 | ||
1652d19e VS |
6321 | static int skylake_get_display_clock_speed(struct drm_device *dev) |
6322 | { | |
6323 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6324 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
6325 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6326 | uint32_t linkrate; | |
6327 | ||
6328 | if (!(lcpll1 & LCPLL_PLL_ENABLE)) { | |
6329 | WARN(1, "LCPLL1 not enabled\n"); | |
6330 | return 24000; /* 24MHz is the cd freq with NSSC ref */ | |
6331 | } | |
6332 | ||
6333 | if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540) | |
6334 | return 540000; | |
6335 | ||
6336 | linkrate = (I915_READ(DPLL_CTRL1) & | |
6337 | DPLL_CRTL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1; | |
6338 | ||
6339 | if (linkrate == DPLL_CRTL1_LINK_RATE_2160 || | |
6340 | linkrate == DPLL_CRTL1_LINK_RATE_1080) { | |
6341 | /* vco 8640 */ | |
6342 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6343 | case CDCLK_FREQ_450_432: | |
6344 | return 432000; | |
6345 | case CDCLK_FREQ_337_308: | |
6346 | return 308570; | |
6347 | case CDCLK_FREQ_675_617: | |
6348 | return 617140; | |
6349 | default: | |
6350 | WARN(1, "Unknown cd freq selection\n"); | |
6351 | } | |
6352 | } else { | |
6353 | /* vco 8100 */ | |
6354 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6355 | case CDCLK_FREQ_450_432: | |
6356 | return 450000; | |
6357 | case CDCLK_FREQ_337_308: | |
6358 | return 337500; | |
6359 | case CDCLK_FREQ_675_617: | |
6360 | return 675000; | |
6361 | default: | |
6362 | WARN(1, "Unknown cd freq selection\n"); | |
6363 | } | |
6364 | } | |
6365 | ||
6366 | /* error case, do as if DPLL0 isn't enabled */ | |
6367 | return 24000; | |
6368 | } | |
6369 | ||
6370 | static int broadwell_get_display_clock_speed(struct drm_device *dev) | |
6371 | { | |
6372 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6373 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6374 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6375 | ||
6376 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6377 | return 800000; | |
6378 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6379 | return 450000; | |
6380 | else if (freq == LCPLL_CLK_FREQ_450) | |
6381 | return 450000; | |
6382 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
6383 | return 540000; | |
6384 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
6385 | return 337500; | |
6386 | else | |
6387 | return 675000; | |
6388 | } | |
6389 | ||
6390 | static int haswell_get_display_clock_speed(struct drm_device *dev) | |
6391 | { | |
6392 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6393 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6394 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6395 | ||
6396 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6397 | return 800000; | |
6398 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6399 | return 450000; | |
6400 | else if (freq == LCPLL_CLK_FREQ_450) | |
6401 | return 450000; | |
6402 | else if (IS_HSW_ULT(dev)) | |
6403 | return 337500; | |
6404 | else | |
6405 | return 540000; | |
6406 | } | |
6407 | ||
25eb05fc JB |
6408 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
6409 | { | |
d197b7d3 | 6410 | struct drm_i915_private *dev_priv = dev->dev_private; |
d197b7d3 VS |
6411 | u32 val; |
6412 | int divider; | |
6413 | ||
6bcda4f0 VS |
6414 | if (dev_priv->hpll_freq == 0) |
6415 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
6416 | ||
d197b7d3 VS |
6417 | mutex_lock(&dev_priv->dpio_lock); |
6418 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
6419 | mutex_unlock(&dev_priv->dpio_lock); | |
6420 | ||
6421 | divider = val & DISPLAY_FREQUENCY_VALUES; | |
6422 | ||
7d007f40 VS |
6423 | WARN((val & DISPLAY_FREQUENCY_STATUS) != |
6424 | (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), | |
6425 | "cdclk change in progress\n"); | |
6426 | ||
6bcda4f0 | 6427 | return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1); |
25eb05fc JB |
6428 | } |
6429 | ||
b37a6434 VS |
6430 | static int ilk_get_display_clock_speed(struct drm_device *dev) |
6431 | { | |
6432 | return 450000; | |
6433 | } | |
6434 | ||
e70236a8 JB |
6435 | static int i945_get_display_clock_speed(struct drm_device *dev) |
6436 | { | |
6437 | return 400000; | |
6438 | } | |
79e53945 | 6439 | |
e70236a8 | 6440 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 6441 | { |
e907f170 | 6442 | return 333333; |
e70236a8 | 6443 | } |
79e53945 | 6444 | |
e70236a8 JB |
6445 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
6446 | { | |
6447 | return 200000; | |
6448 | } | |
79e53945 | 6449 | |
257a7ffc DV |
6450 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
6451 | { | |
6452 | u16 gcfgc = 0; | |
6453 | ||
6454 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
6455 | ||
6456 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6457 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
e907f170 | 6458 | return 266667; |
257a7ffc | 6459 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
e907f170 | 6460 | return 333333; |
257a7ffc | 6461 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
e907f170 | 6462 | return 444444; |
257a7ffc DV |
6463 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
6464 | return 200000; | |
6465 | default: | |
6466 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
6467 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
e907f170 | 6468 | return 133333; |
257a7ffc | 6469 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
e907f170 | 6470 | return 166667; |
257a7ffc DV |
6471 | } |
6472 | } | |
6473 | ||
e70236a8 JB |
6474 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
6475 | { | |
6476 | u16 gcfgc = 0; | |
79e53945 | 6477 | |
e70236a8 JB |
6478 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
6479 | ||
6480 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
e907f170 | 6481 | return 133333; |
e70236a8 JB |
6482 | else { |
6483 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6484 | case GC_DISPLAY_CLOCK_333_MHZ: | |
e907f170 | 6485 | return 333333; |
e70236a8 JB |
6486 | default: |
6487 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
6488 | return 190000; | |
79e53945 | 6489 | } |
e70236a8 JB |
6490 | } |
6491 | } | |
6492 | ||
6493 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
6494 | { | |
e907f170 | 6495 | return 266667; |
e70236a8 JB |
6496 | } |
6497 | ||
6498 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
6499 | { | |
6500 | u16 hpllcc = 0; | |
6501 | /* Assume that the hardware is in the high speed state. This | |
6502 | * should be the default. | |
6503 | */ | |
6504 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
6505 | case GC_CLOCK_133_200: | |
6506 | case GC_CLOCK_100_200: | |
6507 | return 200000; | |
6508 | case GC_CLOCK_166_250: | |
6509 | return 250000; | |
6510 | case GC_CLOCK_100_133: | |
e907f170 | 6511 | return 133333; |
e70236a8 | 6512 | } |
79e53945 | 6513 | |
e70236a8 JB |
6514 | /* Shouldn't happen */ |
6515 | return 0; | |
6516 | } | |
79e53945 | 6517 | |
e70236a8 JB |
6518 | static int i830_get_display_clock_speed(struct drm_device *dev) |
6519 | { | |
e907f170 | 6520 | return 133333; |
79e53945 JB |
6521 | } |
6522 | ||
2c07245f | 6523 | static void |
a65851af | 6524 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 6525 | { |
a65851af VS |
6526 | while (*num > DATA_LINK_M_N_MASK || |
6527 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
6528 | *num >>= 1; |
6529 | *den >>= 1; | |
6530 | } | |
6531 | } | |
6532 | ||
a65851af VS |
6533 | static void compute_m_n(unsigned int m, unsigned int n, |
6534 | uint32_t *ret_m, uint32_t *ret_n) | |
6535 | { | |
6536 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
6537 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
6538 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
6539 | } | |
6540 | ||
e69d0bc1 DV |
6541 | void |
6542 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
6543 | int pixel_clock, int link_clock, | |
6544 | struct intel_link_m_n *m_n) | |
2c07245f | 6545 | { |
e69d0bc1 | 6546 | m_n->tu = 64; |
a65851af VS |
6547 | |
6548 | compute_m_n(bits_per_pixel * pixel_clock, | |
6549 | link_clock * nlanes * 8, | |
6550 | &m_n->gmch_m, &m_n->gmch_n); | |
6551 | ||
6552 | compute_m_n(pixel_clock, link_clock, | |
6553 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
6554 | } |
6555 | ||
a7615030 CW |
6556 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
6557 | { | |
d330a953 JN |
6558 | if (i915.panel_use_ssc >= 0) |
6559 | return i915.panel_use_ssc != 0; | |
41aa3448 | 6560 | return dev_priv->vbt.lvds_use_ssc |
435793df | 6561 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
6562 | } |
6563 | ||
a93e255f ACO |
6564 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
6565 | int num_connectors) | |
c65d77d8 | 6566 | { |
a93e255f | 6567 | struct drm_device *dev = crtc_state->base.crtc->dev; |
c65d77d8 JB |
6568 | struct drm_i915_private *dev_priv = dev->dev_private; |
6569 | int refclk; | |
6570 | ||
a93e255f ACO |
6571 | WARN_ON(!crtc_state->base.state); |
6572 | ||
a0c4da24 | 6573 | if (IS_VALLEYVIEW(dev)) { |
9a0ea498 | 6574 | refclk = 100000; |
a93e255f | 6575 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 6576 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
e91e941b VS |
6577 | refclk = dev_priv->vbt.lvds_ssc_freq; |
6578 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
6579 | } else if (!IS_GEN2(dev)) { |
6580 | refclk = 96000; | |
6581 | } else { | |
6582 | refclk = 48000; | |
6583 | } | |
6584 | ||
6585 | return refclk; | |
6586 | } | |
6587 | ||
7429e9d4 | 6588 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 6589 | { |
7df00d7a | 6590 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 6591 | } |
f47709a9 | 6592 | |
7429e9d4 DV |
6593 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
6594 | { | |
6595 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
6596 | } |
6597 | ||
f47709a9 | 6598 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 6599 | struct intel_crtc_state *crtc_state, |
a7516a05 JB |
6600 | intel_clock_t *reduced_clock) |
6601 | { | |
f47709a9 | 6602 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
6603 | u32 fp, fp2 = 0; |
6604 | ||
6605 | if (IS_PINEVIEW(dev)) { | |
190f68c5 | 6606 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 6607 | if (reduced_clock) |
7429e9d4 | 6608 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 6609 | } else { |
190f68c5 | 6610 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 6611 | if (reduced_clock) |
7429e9d4 | 6612 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
6613 | } |
6614 | ||
190f68c5 | 6615 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 6616 | |
f47709a9 | 6617 | crtc->lowfreq_avail = false; |
a93e255f | 6618 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 6619 | reduced_clock) { |
190f68c5 | 6620 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 6621 | crtc->lowfreq_avail = true; |
a7516a05 | 6622 | } else { |
190f68c5 | 6623 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
6624 | } |
6625 | } | |
6626 | ||
5e69f97f CML |
6627 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
6628 | pipe) | |
89b667f8 JB |
6629 | { |
6630 | u32 reg_val; | |
6631 | ||
6632 | /* | |
6633 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
6634 | * and set it to a reasonable value instead. | |
6635 | */ | |
ab3c759a | 6636 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
6637 | reg_val &= 0xffffff00; |
6638 | reg_val |= 0x00000030; | |
ab3c759a | 6639 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 6640 | |
ab3c759a | 6641 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
6642 | reg_val &= 0x8cffffff; |
6643 | reg_val = 0x8c000000; | |
ab3c759a | 6644 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 6645 | |
ab3c759a | 6646 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 6647 | reg_val &= 0xffffff00; |
ab3c759a | 6648 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 6649 | |
ab3c759a | 6650 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
6651 | reg_val &= 0x00ffffff; |
6652 | reg_val |= 0xb0000000; | |
ab3c759a | 6653 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
6654 | } |
6655 | ||
b551842d DV |
6656 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
6657 | struct intel_link_m_n *m_n) | |
6658 | { | |
6659 | struct drm_device *dev = crtc->base.dev; | |
6660 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6661 | int pipe = crtc->pipe; | |
6662 | ||
e3b95f1e DV |
6663 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6664 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
6665 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
6666 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
6667 | } |
6668 | ||
6669 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
6670 | struct intel_link_m_n *m_n, |
6671 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
6672 | { |
6673 | struct drm_device *dev = crtc->base.dev; | |
6674 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6675 | int pipe = crtc->pipe; | |
6e3c9717 | 6676 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d DV |
6677 | |
6678 | if (INTEL_INFO(dev)->gen >= 5) { | |
6679 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
6680 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
6681 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
6682 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
6683 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
6684 | * for gen < 8) and if DRRS is supported (to make sure the | |
6685 | * registers are not unnecessarily accessed). | |
6686 | */ | |
44395bfe | 6687 | if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && |
6e3c9717 | 6688 | crtc->config->has_drrs) { |
f769cd24 VK |
6689 | I915_WRITE(PIPE_DATA_M2(transcoder), |
6690 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
6691 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
6692 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
6693 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
6694 | } | |
b551842d | 6695 | } else { |
e3b95f1e DV |
6696 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6697 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
6698 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
6699 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
6700 | } |
6701 | } | |
6702 | ||
fe3cd48d | 6703 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 6704 | { |
fe3cd48d R |
6705 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
6706 | ||
6707 | if (m_n == M1_N1) { | |
6708 | dp_m_n = &crtc->config->dp_m_n; | |
6709 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
6710 | } else if (m_n == M2_N2) { | |
6711 | ||
6712 | /* | |
6713 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
6714 | * needs to be programmed into M1_N1. | |
6715 | */ | |
6716 | dp_m_n = &crtc->config->dp_m2_n2; | |
6717 | } else { | |
6718 | DRM_ERROR("Unsupported divider value\n"); | |
6719 | return; | |
6720 | } | |
6721 | ||
6e3c9717 ACO |
6722 | if (crtc->config->has_pch_encoder) |
6723 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 6724 | else |
fe3cd48d | 6725 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
6726 | } |
6727 | ||
d288f65f | 6728 | static void vlv_update_pll(struct intel_crtc *crtc, |
5cec258b | 6729 | struct intel_crtc_state *pipe_config) |
bdd4b6a6 DV |
6730 | { |
6731 | u32 dpll, dpll_md; | |
6732 | ||
6733 | /* | |
6734 | * Enable DPIO clock input. We should never disable the reference | |
6735 | * clock for pipe B, since VGA hotplug / manual detection depends | |
6736 | * on it. | |
6737 | */ | |
6738 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | | |
6739 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; | |
6740 | /* We should never disable this, set it here for state tracking */ | |
6741 | if (crtc->pipe == PIPE_B) | |
6742 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
6743 | dpll |= DPLL_VCO_ENABLE; | |
d288f65f | 6744 | pipe_config->dpll_hw_state.dpll = dpll; |
bdd4b6a6 | 6745 | |
d288f65f | 6746 | dpll_md = (pipe_config->pixel_multiplier - 1) |
bdd4b6a6 | 6747 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
d288f65f | 6748 | pipe_config->dpll_hw_state.dpll_md = dpll_md; |
bdd4b6a6 DV |
6749 | } |
6750 | ||
d288f65f | 6751 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 6752 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 6753 | { |
f47709a9 | 6754 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 6755 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 6756 | int pipe = crtc->pipe; |
bdd4b6a6 | 6757 | u32 mdiv; |
a0c4da24 | 6758 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 6759 | u32 coreclk, reg_val; |
a0c4da24 | 6760 | |
09153000 DV |
6761 | mutex_lock(&dev_priv->dpio_lock); |
6762 | ||
d288f65f VS |
6763 | bestn = pipe_config->dpll.n; |
6764 | bestm1 = pipe_config->dpll.m1; | |
6765 | bestm2 = pipe_config->dpll.m2; | |
6766 | bestp1 = pipe_config->dpll.p1; | |
6767 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 6768 | |
89b667f8 JB |
6769 | /* See eDP HDMI DPIO driver vbios notes doc */ |
6770 | ||
6771 | /* PLL B needs special handling */ | |
bdd4b6a6 | 6772 | if (pipe == PIPE_B) |
5e69f97f | 6773 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
6774 | |
6775 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 6776 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
6777 | |
6778 | /* Disable target IRef on PLL */ | |
ab3c759a | 6779 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 6780 | reg_val &= 0x00ffffff; |
ab3c759a | 6781 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
6782 | |
6783 | /* Disable fast lock */ | |
ab3c759a | 6784 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
6785 | |
6786 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
6787 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
6788 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
6789 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 6790 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
6791 | |
6792 | /* | |
6793 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
6794 | * but we don't support that). | |
6795 | * Note: don't use the DAC post divider as it seems unstable. | |
6796 | */ | |
6797 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 6798 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 6799 | |
a0c4da24 | 6800 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 6801 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 6802 | |
89b667f8 | 6803 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 6804 | if (pipe_config->port_clock == 162000 || |
409ee761 ACO |
6805 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) || |
6806 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 6807 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 6808 | 0x009f0003); |
89b667f8 | 6809 | else |
ab3c759a | 6810 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
6811 | 0x00d0000f); |
6812 | ||
681a8504 | 6813 | if (pipe_config->has_dp_encoder) { |
89b667f8 | 6814 | /* Use SSC source */ |
bdd4b6a6 | 6815 | if (pipe == PIPE_A) |
ab3c759a | 6816 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6817 | 0x0df40000); |
6818 | else | |
ab3c759a | 6819 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6820 | 0x0df70000); |
6821 | } else { /* HDMI or VGA */ | |
6822 | /* Use bend source */ | |
bdd4b6a6 | 6823 | if (pipe == PIPE_A) |
ab3c759a | 6824 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6825 | 0x0df70000); |
6826 | else | |
ab3c759a | 6827 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6828 | 0x0df40000); |
6829 | } | |
a0c4da24 | 6830 | |
ab3c759a | 6831 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 6832 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
409ee761 ACO |
6833 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
6834 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) | |
89b667f8 | 6835 | coreclk |= 0x01000000; |
ab3c759a | 6836 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 6837 | |
ab3c759a | 6838 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
09153000 | 6839 | mutex_unlock(&dev_priv->dpio_lock); |
a0c4da24 JB |
6840 | } |
6841 | ||
d288f65f | 6842 | static void chv_update_pll(struct intel_crtc *crtc, |
5cec258b | 6843 | struct intel_crtc_state *pipe_config) |
1ae0d137 | 6844 | { |
d288f65f | 6845 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV | |
1ae0d137 VS |
6846 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | |
6847 | DPLL_VCO_ENABLE; | |
6848 | if (crtc->pipe != PIPE_A) | |
d288f65f | 6849 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
1ae0d137 | 6850 | |
d288f65f VS |
6851 | pipe_config->dpll_hw_state.dpll_md = |
6852 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
1ae0d137 VS |
6853 | } |
6854 | ||
d288f65f | 6855 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 6856 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
6857 | { |
6858 | struct drm_device *dev = crtc->base.dev; | |
6859 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6860 | int pipe = crtc->pipe; | |
6861 | int dpll_reg = DPLL(crtc->pipe); | |
6862 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9cbe40c1 | 6863 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 6864 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 6865 | u32 dpio_val; |
9cbe40c1 | 6866 | int vco; |
9d556c99 | 6867 | |
d288f65f VS |
6868 | bestn = pipe_config->dpll.n; |
6869 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
6870 | bestm1 = pipe_config->dpll.m1; | |
6871 | bestm2 = pipe_config->dpll.m2 >> 22; | |
6872 | bestp1 = pipe_config->dpll.p1; | |
6873 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 6874 | vco = pipe_config->dpll.vco; |
a945ce7e | 6875 | dpio_val = 0; |
9cbe40c1 | 6876 | loopfilter = 0; |
9d556c99 CML |
6877 | |
6878 | /* | |
6879 | * Enable Refclk and SSC | |
6880 | */ | |
a11b0703 | 6881 | I915_WRITE(dpll_reg, |
d288f65f | 6882 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); |
a11b0703 VS |
6883 | |
6884 | mutex_lock(&dev_priv->dpio_lock); | |
9d556c99 | 6885 | |
9d556c99 CML |
6886 | /* p1 and p2 divider */ |
6887 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
6888 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
6889 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
6890 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
6891 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
6892 | ||
6893 | /* Feedback post-divider - m2 */ | |
6894 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
6895 | ||
6896 | /* Feedback refclk divider - n and m1 */ | |
6897 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
6898 | DPIO_CHV_M1_DIV_BY_2 | | |
6899 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
6900 | ||
6901 | /* M2 fraction division */ | |
a945ce7e VP |
6902 | if (bestm2_frac) |
6903 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); | |
9d556c99 CML |
6904 | |
6905 | /* M2 fraction division enable */ | |
a945ce7e VP |
6906 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
6907 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
6908 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
6909 | if (bestm2_frac) | |
6910 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
6911 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 6912 | |
de3a0fde VP |
6913 | /* Program digital lock detect threshold */ |
6914 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
6915 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
6916 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
6917 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
6918 | if (!bestm2_frac) | |
6919 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
6920 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
6921 | ||
9d556c99 | 6922 | /* Loop filter */ |
9cbe40c1 VP |
6923 | if (vco == 5400000) { |
6924 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6925 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
6926 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6927 | tribuf_calcntr = 0x9; | |
6928 | } else if (vco <= 6200000) { | |
6929 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6930 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
6931 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6932 | tribuf_calcntr = 0x9; | |
6933 | } else if (vco <= 6480000) { | |
6934 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6935 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
6936 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6937 | tribuf_calcntr = 0x8; | |
6938 | } else { | |
6939 | /* Not supported. Apply the same limits as in the max case */ | |
6940 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6941 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
6942 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6943 | tribuf_calcntr = 0; | |
6944 | } | |
9d556c99 CML |
6945 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
6946 | ||
968040b2 | 6947 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
6948 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
6949 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
6950 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
6951 | ||
9d556c99 CML |
6952 | /* AFC Recal */ |
6953 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
6954 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
6955 | DPIO_AFC_RECAL); | |
6956 | ||
6957 | mutex_unlock(&dev_priv->dpio_lock); | |
6958 | } | |
6959 | ||
d288f65f VS |
6960 | /** |
6961 | * vlv_force_pll_on - forcibly enable just the PLL | |
6962 | * @dev_priv: i915 private structure | |
6963 | * @pipe: pipe PLL to enable | |
6964 | * @dpll: PLL configuration | |
6965 | * | |
6966 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
6967 | * in cases where we need the PLL enabled even when @pipe is not going to | |
6968 | * be enabled. | |
6969 | */ | |
6970 | void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, | |
6971 | const struct dpll *dpll) | |
6972 | { | |
6973 | struct intel_crtc *crtc = | |
6974 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
5cec258b | 6975 | struct intel_crtc_state pipe_config = { |
a93e255f | 6976 | .base.crtc = &crtc->base, |
d288f65f VS |
6977 | .pixel_multiplier = 1, |
6978 | .dpll = *dpll, | |
6979 | }; | |
6980 | ||
6981 | if (IS_CHERRYVIEW(dev)) { | |
6982 | chv_update_pll(crtc, &pipe_config); | |
6983 | chv_prepare_pll(crtc, &pipe_config); | |
6984 | chv_enable_pll(crtc, &pipe_config); | |
6985 | } else { | |
6986 | vlv_update_pll(crtc, &pipe_config); | |
6987 | vlv_prepare_pll(crtc, &pipe_config); | |
6988 | vlv_enable_pll(crtc, &pipe_config); | |
6989 | } | |
6990 | } | |
6991 | ||
6992 | /** | |
6993 | * vlv_force_pll_off - forcibly disable just the PLL | |
6994 | * @dev_priv: i915 private structure | |
6995 | * @pipe: pipe PLL to disable | |
6996 | * | |
6997 | * Disable the PLL for @pipe. To be used in cases where we need | |
6998 | * the PLL enabled even when @pipe is not going to be enabled. | |
6999 | */ | |
7000 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) | |
7001 | { | |
7002 | if (IS_CHERRYVIEW(dev)) | |
7003 | chv_disable_pll(to_i915(dev), pipe); | |
7004 | else | |
7005 | vlv_disable_pll(to_i915(dev), pipe); | |
7006 | } | |
7007 | ||
f47709a9 | 7008 | static void i9xx_update_pll(struct intel_crtc *crtc, |
190f68c5 | 7009 | struct intel_crtc_state *crtc_state, |
f47709a9 | 7010 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
7011 | int num_connectors) |
7012 | { | |
f47709a9 | 7013 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7014 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
7015 | u32 dpll; |
7016 | bool is_sdvo; | |
190f68c5 | 7017 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7018 | |
190f68c5 | 7019 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7020 | |
a93e255f ACO |
7021 | is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) || |
7022 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
7023 | |
7024 | dpll = DPLL_VGA_MODE_DIS; | |
7025 | ||
a93e255f | 7026 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
7027 | dpll |= DPLLB_MODE_LVDS; |
7028 | else | |
7029 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 7030 | |
ef1b460d | 7031 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
190f68c5 | 7032 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 7033 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 7034 | } |
198a037f DV |
7035 | |
7036 | if (is_sdvo) | |
4a33e48d | 7037 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 7038 | |
190f68c5 | 7039 | if (crtc_state->has_dp_encoder) |
4a33e48d | 7040 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
7041 | |
7042 | /* compute bitmask from p1 value */ | |
7043 | if (IS_PINEVIEW(dev)) | |
7044 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
7045 | else { | |
7046 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7047 | if (IS_G4X(dev) && reduced_clock) | |
7048 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
7049 | } | |
7050 | switch (clock->p2) { | |
7051 | case 5: | |
7052 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7053 | break; | |
7054 | case 7: | |
7055 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7056 | break; | |
7057 | case 10: | |
7058 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7059 | break; | |
7060 | case 14: | |
7061 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7062 | break; | |
7063 | } | |
7064 | if (INTEL_INFO(dev)->gen >= 4) | |
7065 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
7066 | ||
190f68c5 | 7067 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 7068 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
a93e255f | 7069 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7070 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7071 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7072 | else | |
7073 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7074 | ||
7075 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7076 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 7077 | |
eb1cbe48 | 7078 | if (INTEL_INFO(dev)->gen >= 4) { |
190f68c5 | 7079 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 7080 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 7081 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
7082 | } |
7083 | } | |
7084 | ||
f47709a9 | 7085 | static void i8xx_update_pll(struct intel_crtc *crtc, |
190f68c5 | 7086 | struct intel_crtc_state *crtc_state, |
f47709a9 | 7087 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
7088 | int num_connectors) |
7089 | { | |
f47709a9 | 7090 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7091 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 7092 | u32 dpll; |
190f68c5 | 7093 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7094 | |
190f68c5 | 7095 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7096 | |
eb1cbe48 DV |
7097 | dpll = DPLL_VGA_MODE_DIS; |
7098 | ||
a93e255f | 7099 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
7100 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
7101 | } else { | |
7102 | if (clock->p1 == 2) | |
7103 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
7104 | else | |
7105 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7106 | if (clock->p2 == 4) | |
7107 | dpll |= PLL_P2_DIVIDE_BY_4; | |
7108 | } | |
7109 | ||
a93e255f | 7110 | if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
4a33e48d DV |
7111 | dpll |= DPLL_DVO_2X_MODE; |
7112 | ||
a93e255f | 7113 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7114 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7115 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7116 | else | |
7117 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7118 | ||
7119 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7120 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
7121 | } |
7122 | ||
8a654f3b | 7123 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
7124 | { |
7125 | struct drm_device *dev = intel_crtc->base.dev; | |
7126 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7127 | enum pipe pipe = intel_crtc->pipe; | |
6e3c9717 | 7128 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
8a654f3b | 7129 | struct drm_display_mode *adjusted_mode = |
6e3c9717 | 7130 | &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
7131 | uint32_t crtc_vtotal, crtc_vblank_end; |
7132 | int vsyncshift = 0; | |
4d8a62ea DV |
7133 | |
7134 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
7135 | * the hw state checker will get angry at the mismatch. */ | |
7136 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
7137 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 7138 | |
609aeaca | 7139 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 7140 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
7141 | crtc_vtotal -= 1; |
7142 | crtc_vblank_end -= 1; | |
609aeaca | 7143 | |
409ee761 | 7144 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
7145 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
7146 | else | |
7147 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
7148 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
7149 | if (vsyncshift < 0) |
7150 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
7151 | } |
7152 | ||
7153 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 7154 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 7155 | |
fe2b8f9d | 7156 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
7157 | (adjusted_mode->crtc_hdisplay - 1) | |
7158 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 7159 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
7160 | (adjusted_mode->crtc_hblank_start - 1) | |
7161 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 7162 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
7163 | (adjusted_mode->crtc_hsync_start - 1) | |
7164 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
7165 | ||
fe2b8f9d | 7166 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 7167 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 7168 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 7169 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 7170 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 7171 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 7172 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
7173 | (adjusted_mode->crtc_vsync_start - 1) | |
7174 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
7175 | ||
b5e508d4 PZ |
7176 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
7177 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
7178 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
7179 | * bits. */ | |
7180 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
7181 | (pipe == PIPE_B || pipe == PIPE_C)) | |
7182 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
7183 | ||
b0e77b9c PZ |
7184 | /* pipesrc controls the size that is scaled from, which should |
7185 | * always be the user's requested size. | |
7186 | */ | |
7187 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
7188 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
7189 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
7190 | } |
7191 | ||
1bd1bd80 | 7192 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 7193 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
7194 | { |
7195 | struct drm_device *dev = crtc->base.dev; | |
7196 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7197 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
7198 | uint32_t tmp; | |
7199 | ||
7200 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7201 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
7202 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7203 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
7204 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
7205 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7206 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
7207 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
7208 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7209 | |
7210 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7211 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
7212 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7213 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
7214 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
7215 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7216 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
7217 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
7218 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7219 | |
7220 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
7221 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
7222 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
7223 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 DV |
7224 | } |
7225 | ||
7226 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
7227 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
7228 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
7229 | ||
2d112de7 ACO |
7230 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
7231 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
7232 | } |
7233 | ||
f6a83288 | 7234 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 7235 | struct intel_crtc_state *pipe_config) |
babea61d | 7236 | { |
2d112de7 ACO |
7237 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
7238 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
7239 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
7240 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 7241 | |
2d112de7 ACO |
7242 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
7243 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
7244 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
7245 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 7246 | |
2d112de7 | 7247 | mode->flags = pipe_config->base.adjusted_mode.flags; |
babea61d | 7248 | |
2d112de7 ACO |
7249 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
7250 | mode->flags |= pipe_config->base.adjusted_mode.flags; | |
babea61d JB |
7251 | } |
7252 | ||
84b046f3 DV |
7253 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
7254 | { | |
7255 | struct drm_device *dev = intel_crtc->base.dev; | |
7256 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7257 | uint32_t pipeconf; | |
7258 | ||
9f11a9e4 | 7259 | pipeconf = 0; |
84b046f3 | 7260 | |
b6b5d049 VS |
7261 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
7262 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
7263 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 7264 | |
6e3c9717 | 7265 | if (intel_crtc->config->double_wide) |
cf532bb2 | 7266 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 7267 | |
ff9ce46e DV |
7268 | /* only g4x and later have fancy bpc/dither controls */ |
7269 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { | |
ff9ce46e | 7270 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 7271 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 7272 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 7273 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 7274 | |
6e3c9717 | 7275 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
7276 | case 18: |
7277 | pipeconf |= PIPECONF_6BPC; | |
7278 | break; | |
7279 | case 24: | |
7280 | pipeconf |= PIPECONF_8BPC; | |
7281 | break; | |
7282 | case 30: | |
7283 | pipeconf |= PIPECONF_10BPC; | |
7284 | break; | |
7285 | default: | |
7286 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
7287 | BUG(); | |
84b046f3 DV |
7288 | } |
7289 | } | |
7290 | ||
7291 | if (HAS_PIPE_CXSR(dev)) { | |
7292 | if (intel_crtc->lowfreq_avail) { | |
7293 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
7294 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
7295 | } else { | |
7296 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
7297 | } |
7298 | } | |
7299 | ||
6e3c9717 | 7300 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
efc2cfff | 7301 | if (INTEL_INFO(dev)->gen < 4 || |
409ee761 | 7302 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
7303 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
7304 | else | |
7305 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
7306 | } else | |
84b046f3 DV |
7307 | pipeconf |= PIPECONF_PROGRESSIVE; |
7308 | ||
6e3c9717 | 7309 | if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range) |
9f11a9e4 | 7310 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 7311 | |
84b046f3 DV |
7312 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
7313 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
7314 | } | |
7315 | ||
190f68c5 ACO |
7316 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
7317 | struct intel_crtc_state *crtc_state) | |
79e53945 | 7318 | { |
c7653199 | 7319 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 7320 | struct drm_i915_private *dev_priv = dev->dev_private; |
c751ce4f | 7321 | int refclk, num_connectors = 0; |
652c393a | 7322 | intel_clock_t clock, reduced_clock; |
a16af721 | 7323 | bool ok, has_reduced_clock = false; |
e9fd1c02 | 7324 | bool is_lvds = false, is_dsi = false; |
5eddb70b | 7325 | struct intel_encoder *encoder; |
d4906093 | 7326 | const intel_limit_t *limit; |
55bb9992 ACO |
7327 | struct drm_atomic_state *state = crtc_state->base.state; |
7328 | struct drm_connector_state *connector_state; | |
7329 | int i; | |
79e53945 | 7330 | |
55bb9992 ACO |
7331 | for (i = 0; i < state->num_connector; i++) { |
7332 | if (!state->connectors[i]) | |
d0737e1d ACO |
7333 | continue; |
7334 | ||
55bb9992 ACO |
7335 | connector_state = state->connector_states[i]; |
7336 | if (connector_state->crtc != &crtc->base) | |
7337 | continue; | |
7338 | ||
7339 | encoder = to_intel_encoder(connector_state->best_encoder); | |
7340 | ||
5eddb70b | 7341 | switch (encoder->type) { |
79e53945 JB |
7342 | case INTEL_OUTPUT_LVDS: |
7343 | is_lvds = true; | |
7344 | break; | |
e9fd1c02 JN |
7345 | case INTEL_OUTPUT_DSI: |
7346 | is_dsi = true; | |
7347 | break; | |
6847d71b PZ |
7348 | default: |
7349 | break; | |
79e53945 | 7350 | } |
43565a06 | 7351 | |
c751ce4f | 7352 | num_connectors++; |
79e53945 JB |
7353 | } |
7354 | ||
f2335330 | 7355 | if (is_dsi) |
5b18e57c | 7356 | return 0; |
f2335330 | 7357 | |
190f68c5 | 7358 | if (!crtc_state->clock_set) { |
a93e255f | 7359 | refclk = i9xx_get_refclk(crtc_state, num_connectors); |
79e53945 | 7360 | |
e9fd1c02 JN |
7361 | /* |
7362 | * Returns a set of divisors for the desired target clock with | |
7363 | * the given refclk, or FALSE. The returned values represent | |
7364 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
7365 | * 2) / p1 / p2. | |
7366 | */ | |
a93e255f ACO |
7367 | limit = intel_limit(crtc_state, refclk); |
7368 | ok = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 7369 | crtc_state->port_clock, |
e9fd1c02 | 7370 | refclk, NULL, &clock); |
f2335330 | 7371 | if (!ok) { |
e9fd1c02 JN |
7372 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
7373 | return -EINVAL; | |
7374 | } | |
79e53945 | 7375 | |
f2335330 JN |
7376 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
7377 | /* | |
7378 | * Ensure we match the reduced clock's P to the target | |
7379 | * clock. If the clocks don't match, we can't switch | |
7380 | * the display clock by using the FP0/FP1. In such case | |
7381 | * we will disable the LVDS downclock feature. | |
7382 | */ | |
7383 | has_reduced_clock = | |
a93e255f | 7384 | dev_priv->display.find_dpll(limit, crtc_state, |
f2335330 JN |
7385 | dev_priv->lvds_downclock, |
7386 | refclk, &clock, | |
7387 | &reduced_clock); | |
7388 | } | |
7389 | /* Compat-code for transition, will disappear. */ | |
190f68c5 ACO |
7390 | crtc_state->dpll.n = clock.n; |
7391 | crtc_state->dpll.m1 = clock.m1; | |
7392 | crtc_state->dpll.m2 = clock.m2; | |
7393 | crtc_state->dpll.p1 = clock.p1; | |
7394 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 7395 | } |
7026d4ac | 7396 | |
e9fd1c02 | 7397 | if (IS_GEN2(dev)) { |
190f68c5 | 7398 | i8xx_update_pll(crtc, crtc_state, |
2a8f64ca VP |
7399 | has_reduced_clock ? &reduced_clock : NULL, |
7400 | num_connectors); | |
9d556c99 | 7401 | } else if (IS_CHERRYVIEW(dev)) { |
190f68c5 | 7402 | chv_update_pll(crtc, crtc_state); |
e9fd1c02 | 7403 | } else if (IS_VALLEYVIEW(dev)) { |
190f68c5 | 7404 | vlv_update_pll(crtc, crtc_state); |
e9fd1c02 | 7405 | } else { |
190f68c5 | 7406 | i9xx_update_pll(crtc, crtc_state, |
eb1cbe48 | 7407 | has_reduced_clock ? &reduced_clock : NULL, |
eba905b2 | 7408 | num_connectors); |
e9fd1c02 | 7409 | } |
79e53945 | 7410 | |
c8f7a0db | 7411 | return 0; |
f564048e EA |
7412 | } |
7413 | ||
2fa2fe9a | 7414 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 7415 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
7416 | { |
7417 | struct drm_device *dev = crtc->base.dev; | |
7418 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7419 | uint32_t tmp; | |
7420 | ||
dc9e7dec VS |
7421 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
7422 | return; | |
7423 | ||
2fa2fe9a | 7424 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
7425 | if (!(tmp & PFIT_ENABLE)) |
7426 | return; | |
2fa2fe9a | 7427 | |
06922821 | 7428 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
7429 | if (INTEL_INFO(dev)->gen < 4) { |
7430 | if (crtc->pipe != PIPE_B) | |
7431 | return; | |
2fa2fe9a DV |
7432 | } else { |
7433 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
7434 | return; | |
7435 | } | |
7436 | ||
06922821 | 7437 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
7438 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
7439 | if (INTEL_INFO(dev)->gen < 5) | |
7440 | pipe_config->gmch_pfit.lvds_border_bits = | |
7441 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
7442 | } | |
7443 | ||
acbec814 | 7444 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 7445 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
7446 | { |
7447 | struct drm_device *dev = crtc->base.dev; | |
7448 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7449 | int pipe = pipe_config->cpu_transcoder; | |
7450 | intel_clock_t clock; | |
7451 | u32 mdiv; | |
662c6ecb | 7452 | int refclk = 100000; |
acbec814 | 7453 | |
f573de5a SK |
7454 | /* In case of MIPI DPLL will not even be used */ |
7455 | if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) | |
7456 | return; | |
7457 | ||
acbec814 | 7458 | mutex_lock(&dev_priv->dpio_lock); |
ab3c759a | 7459 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
acbec814 JB |
7460 | mutex_unlock(&dev_priv->dpio_lock); |
7461 | ||
7462 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
7463 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
7464 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
7465 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
7466 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
7467 | ||
f646628b | 7468 | vlv_clock(refclk, &clock); |
acbec814 | 7469 | |
f646628b VS |
7470 | /* clock.dot is the fast clock */ |
7471 | pipe_config->port_clock = clock.dot / 5; | |
acbec814 JB |
7472 | } |
7473 | ||
5724dbd1 DL |
7474 | static void |
7475 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
7476 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
7477 | { |
7478 | struct drm_device *dev = crtc->base.dev; | |
7479 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7480 | u32 val, base, offset; | |
7481 | int pipe = crtc->pipe, plane = crtc->plane; | |
7482 | int fourcc, pixel_format; | |
6761dd31 | 7483 | unsigned int aligned_height; |
b113d5ee | 7484 | struct drm_framebuffer *fb; |
1b842c89 | 7485 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 7486 | |
42a7b088 DL |
7487 | val = I915_READ(DSPCNTR(plane)); |
7488 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
7489 | return; | |
7490 | ||
d9806c9f | 7491 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 7492 | if (!intel_fb) { |
1ad292b5 JB |
7493 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
7494 | return; | |
7495 | } | |
7496 | ||
1b842c89 DL |
7497 | fb = &intel_fb->base; |
7498 | ||
18c5247e DV |
7499 | if (INTEL_INFO(dev)->gen >= 4) { |
7500 | if (val & DISPPLANE_TILED) { | |
49af449b | 7501 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
7502 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
7503 | } | |
7504 | } | |
1ad292b5 JB |
7505 | |
7506 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 7507 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
7508 | fb->pixel_format = fourcc; |
7509 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
1ad292b5 JB |
7510 | |
7511 | if (INTEL_INFO(dev)->gen >= 4) { | |
49af449b | 7512 | if (plane_config->tiling) |
1ad292b5 JB |
7513 | offset = I915_READ(DSPTILEOFF(plane)); |
7514 | else | |
7515 | offset = I915_READ(DSPLINOFF(plane)); | |
7516 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
7517 | } else { | |
7518 | base = I915_READ(DSPADDR(plane)); | |
7519 | } | |
7520 | plane_config->base = base; | |
7521 | ||
7522 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
7523 | fb->width = ((val >> 16) & 0xfff) + 1; |
7524 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
7525 | |
7526 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 7527 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 7528 | |
b113d5ee | 7529 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
7530 | fb->pixel_format, |
7531 | fb->modifier[0]); | |
1ad292b5 | 7532 | |
f37b5c2b | 7533 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 7534 | |
2844a921 DL |
7535 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
7536 | pipe_name(pipe), plane, fb->width, fb->height, | |
7537 | fb->bits_per_pixel, base, fb->pitches[0], | |
7538 | plane_config->size); | |
1ad292b5 | 7539 | |
2d14030b | 7540 | plane_config->fb = intel_fb; |
1ad292b5 JB |
7541 | } |
7542 | ||
70b23a98 | 7543 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 7544 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
7545 | { |
7546 | struct drm_device *dev = crtc->base.dev; | |
7547 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7548 | int pipe = pipe_config->cpu_transcoder; | |
7549 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
7550 | intel_clock_t clock; | |
7551 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2; | |
7552 | int refclk = 100000; | |
7553 | ||
7554 | mutex_lock(&dev_priv->dpio_lock); | |
7555 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); | |
7556 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
7557 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
7558 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
7559 | mutex_unlock(&dev_priv->dpio_lock); | |
7560 | ||
7561 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
7562 | clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff); | |
7563 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; | |
7564 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
7565 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
7566 | ||
7567 | chv_clock(refclk, &clock); | |
7568 | ||
7569 | /* clock.dot is the fast clock */ | |
7570 | pipe_config->port_clock = clock.dot / 5; | |
7571 | } | |
7572 | ||
0e8ffe1b | 7573 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 7574 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
7575 | { |
7576 | struct drm_device *dev = crtc->base.dev; | |
7577 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7578 | uint32_t tmp; | |
7579 | ||
f458ebbc DV |
7580 | if (!intel_display_power_is_enabled(dev_priv, |
7581 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
b5482bd0 ID |
7582 | return false; |
7583 | ||
e143a21c | 7584 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 7585 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 7586 | |
0e8ffe1b DV |
7587 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
7588 | if (!(tmp & PIPECONF_ENABLE)) | |
7589 | return false; | |
7590 | ||
42571aef VS |
7591 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
7592 | switch (tmp & PIPECONF_BPC_MASK) { | |
7593 | case PIPECONF_6BPC: | |
7594 | pipe_config->pipe_bpp = 18; | |
7595 | break; | |
7596 | case PIPECONF_8BPC: | |
7597 | pipe_config->pipe_bpp = 24; | |
7598 | break; | |
7599 | case PIPECONF_10BPC: | |
7600 | pipe_config->pipe_bpp = 30; | |
7601 | break; | |
7602 | default: | |
7603 | break; | |
7604 | } | |
7605 | } | |
7606 | ||
b5a9fa09 DV |
7607 | if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
7608 | pipe_config->limited_color_range = true; | |
7609 | ||
282740f7 VS |
7610 | if (INTEL_INFO(dev)->gen < 4) |
7611 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
7612 | ||
1bd1bd80 DV |
7613 | intel_get_pipe_timings(crtc, pipe_config); |
7614 | ||
2fa2fe9a DV |
7615 | i9xx_get_pfit_config(crtc, pipe_config); |
7616 | ||
6c49f241 DV |
7617 | if (INTEL_INFO(dev)->gen >= 4) { |
7618 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
7619 | pipe_config->pixel_multiplier = | |
7620 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
7621 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 7622 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
7623 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
7624 | tmp = I915_READ(DPLL(crtc->pipe)); | |
7625 | pipe_config->pixel_multiplier = | |
7626 | ((tmp & SDVO_MULTIPLIER_MASK) | |
7627 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
7628 | } else { | |
7629 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
7630 | * port and will be fixed up in the encoder->get_config | |
7631 | * function. */ | |
7632 | pipe_config->pixel_multiplier = 1; | |
7633 | } | |
8bcc2795 DV |
7634 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
7635 | if (!IS_VALLEYVIEW(dev)) { | |
1c4e0274 VS |
7636 | /* |
7637 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
7638 | * on 830. Filter it out here so that we don't | |
7639 | * report errors due to that. | |
7640 | */ | |
7641 | if (IS_I830(dev)) | |
7642 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; | |
7643 | ||
8bcc2795 DV |
7644 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
7645 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
7646 | } else { |
7647 | /* Mask out read-only status bits. */ | |
7648 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
7649 | DPLL_PORTC_READY_MASK | | |
7650 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 7651 | } |
6c49f241 | 7652 | |
70b23a98 VS |
7653 | if (IS_CHERRYVIEW(dev)) |
7654 | chv_crtc_clock_get(crtc, pipe_config); | |
7655 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
7656 | vlv_crtc_clock_get(crtc, pipe_config); |
7657 | else | |
7658 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 7659 | |
0e8ffe1b DV |
7660 | return true; |
7661 | } | |
7662 | ||
dde86e2d | 7663 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
7664 | { |
7665 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13d83a67 | 7666 | struct intel_encoder *encoder; |
74cfd7ac | 7667 | u32 val, final; |
13d83a67 | 7668 | bool has_lvds = false; |
199e5d79 | 7669 | bool has_cpu_edp = false; |
199e5d79 | 7670 | bool has_panel = false; |
99eb6a01 KP |
7671 | bool has_ck505 = false; |
7672 | bool can_ssc = false; | |
13d83a67 JB |
7673 | |
7674 | /* We need to take the global config into account */ | |
b2784e15 | 7675 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
7676 | switch (encoder->type) { |
7677 | case INTEL_OUTPUT_LVDS: | |
7678 | has_panel = true; | |
7679 | has_lvds = true; | |
7680 | break; | |
7681 | case INTEL_OUTPUT_EDP: | |
7682 | has_panel = true; | |
2de6905f | 7683 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
7684 | has_cpu_edp = true; |
7685 | break; | |
6847d71b PZ |
7686 | default: |
7687 | break; | |
13d83a67 JB |
7688 | } |
7689 | } | |
7690 | ||
99eb6a01 | 7691 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 7692 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
7693 | can_ssc = has_ck505; |
7694 | } else { | |
7695 | has_ck505 = false; | |
7696 | can_ssc = true; | |
7697 | } | |
7698 | ||
2de6905f ID |
7699 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
7700 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
7701 | |
7702 | /* Ironlake: try to setup display ref clock before DPLL | |
7703 | * enabling. This is only under driver's control after | |
7704 | * PCH B stepping, previous chipset stepping should be | |
7705 | * ignoring this setting. | |
7706 | */ | |
74cfd7ac CW |
7707 | val = I915_READ(PCH_DREF_CONTROL); |
7708 | ||
7709 | /* As we must carefully and slowly disable/enable each source in turn, | |
7710 | * compute the final state we want first and check if we need to | |
7711 | * make any changes at all. | |
7712 | */ | |
7713 | final = val; | |
7714 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
7715 | if (has_ck505) | |
7716 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
7717 | else | |
7718 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
7719 | ||
7720 | final &= ~DREF_SSC_SOURCE_MASK; | |
7721 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
7722 | final &= ~DREF_SSC1_ENABLE; | |
7723 | ||
7724 | if (has_panel) { | |
7725 | final |= DREF_SSC_SOURCE_ENABLE; | |
7726 | ||
7727 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
7728 | final |= DREF_SSC1_ENABLE; | |
7729 | ||
7730 | if (has_cpu_edp) { | |
7731 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
7732 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
7733 | else | |
7734 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
7735 | } else | |
7736 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
7737 | } else { | |
7738 | final |= DREF_SSC_SOURCE_DISABLE; | |
7739 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
7740 | } | |
7741 | ||
7742 | if (final == val) | |
7743 | return; | |
7744 | ||
13d83a67 | 7745 | /* Always enable nonspread source */ |
74cfd7ac | 7746 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 7747 | |
99eb6a01 | 7748 | if (has_ck505) |
74cfd7ac | 7749 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 7750 | else |
74cfd7ac | 7751 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 7752 | |
199e5d79 | 7753 | if (has_panel) { |
74cfd7ac CW |
7754 | val &= ~DREF_SSC_SOURCE_MASK; |
7755 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 7756 | |
199e5d79 | 7757 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 7758 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 7759 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 7760 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 7761 | } else |
74cfd7ac | 7762 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
7763 | |
7764 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 7765 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7766 | POSTING_READ(PCH_DREF_CONTROL); |
7767 | udelay(200); | |
7768 | ||
74cfd7ac | 7769 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
7770 | |
7771 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 7772 | if (has_cpu_edp) { |
99eb6a01 | 7773 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 7774 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 7775 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 7776 | } else |
74cfd7ac | 7777 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 7778 | } else |
74cfd7ac | 7779 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 7780 | |
74cfd7ac | 7781 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7782 | POSTING_READ(PCH_DREF_CONTROL); |
7783 | udelay(200); | |
7784 | } else { | |
7785 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
7786 | ||
74cfd7ac | 7787 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
7788 | |
7789 | /* Turn off CPU output */ | |
74cfd7ac | 7790 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 7791 | |
74cfd7ac | 7792 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7793 | POSTING_READ(PCH_DREF_CONTROL); |
7794 | udelay(200); | |
7795 | ||
7796 | /* Turn off the SSC source */ | |
74cfd7ac CW |
7797 | val &= ~DREF_SSC_SOURCE_MASK; |
7798 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
7799 | |
7800 | /* Turn off SSC1 */ | |
74cfd7ac | 7801 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 7802 | |
74cfd7ac | 7803 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
7804 | POSTING_READ(PCH_DREF_CONTROL); |
7805 | udelay(200); | |
7806 | } | |
74cfd7ac CW |
7807 | |
7808 | BUG_ON(val != final); | |
13d83a67 JB |
7809 | } |
7810 | ||
f31f2d55 | 7811 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 7812 | { |
f31f2d55 | 7813 | uint32_t tmp; |
dde86e2d | 7814 | |
0ff066a9 PZ |
7815 | tmp = I915_READ(SOUTH_CHICKEN2); |
7816 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
7817 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 7818 | |
0ff066a9 PZ |
7819 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
7820 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
7821 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 7822 | |
0ff066a9 PZ |
7823 | tmp = I915_READ(SOUTH_CHICKEN2); |
7824 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
7825 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 7826 | |
0ff066a9 PZ |
7827 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
7828 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
7829 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
7830 | } |
7831 | ||
7832 | /* WaMPhyProgramming:hsw */ | |
7833 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
7834 | { | |
7835 | uint32_t tmp; | |
dde86e2d PZ |
7836 | |
7837 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
7838 | tmp &= ~(0xFF << 24); | |
7839 | tmp |= (0x12 << 24); | |
7840 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
7841 | ||
dde86e2d PZ |
7842 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
7843 | tmp |= (1 << 11); | |
7844 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
7845 | ||
7846 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
7847 | tmp |= (1 << 11); | |
7848 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
7849 | ||
dde86e2d PZ |
7850 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
7851 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
7852 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
7853 | ||
7854 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
7855 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
7856 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
7857 | ||
0ff066a9 PZ |
7858 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
7859 | tmp &= ~(7 << 13); | |
7860 | tmp |= (5 << 13); | |
7861 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 7862 | |
0ff066a9 PZ |
7863 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
7864 | tmp &= ~(7 << 13); | |
7865 | tmp |= (5 << 13); | |
7866 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
7867 | |
7868 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
7869 | tmp &= ~0xFF; | |
7870 | tmp |= 0x1C; | |
7871 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
7872 | ||
7873 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
7874 | tmp &= ~0xFF; | |
7875 | tmp |= 0x1C; | |
7876 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
7877 | ||
7878 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
7879 | tmp &= ~(0xFF << 16); | |
7880 | tmp |= (0x1C << 16); | |
7881 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
7882 | ||
7883 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
7884 | tmp &= ~(0xFF << 16); | |
7885 | tmp |= (0x1C << 16); | |
7886 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
7887 | ||
0ff066a9 PZ |
7888 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
7889 | tmp |= (1 << 27); | |
7890 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 7891 | |
0ff066a9 PZ |
7892 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
7893 | tmp |= (1 << 27); | |
7894 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 7895 | |
0ff066a9 PZ |
7896 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
7897 | tmp &= ~(0xF << 28); | |
7898 | tmp |= (4 << 28); | |
7899 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 7900 | |
0ff066a9 PZ |
7901 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
7902 | tmp &= ~(0xF << 28); | |
7903 | tmp |= (4 << 28); | |
7904 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
7905 | } |
7906 | ||
2fa86a1f PZ |
7907 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
7908 | * Programming" based on the parameters passed: | |
7909 | * - Sequence to enable CLKOUT_DP | |
7910 | * - Sequence to enable CLKOUT_DP without spread | |
7911 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
7912 | */ | |
7913 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
7914 | bool with_fdi) | |
f31f2d55 PZ |
7915 | { |
7916 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
7917 | uint32_t reg, tmp; |
7918 | ||
7919 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
7920 | with_spread = true; | |
7921 | if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && | |
7922 | with_fdi, "LP PCH doesn't have FDI\n")) | |
7923 | with_fdi = false; | |
f31f2d55 PZ |
7924 | |
7925 | mutex_lock(&dev_priv->dpio_lock); | |
7926 | ||
7927 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7928 | tmp &= ~SBI_SSCCTL_DISABLE; | |
7929 | tmp |= SBI_SSCCTL_PATHALT; | |
7930 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7931 | ||
7932 | udelay(24); | |
7933 | ||
2fa86a1f PZ |
7934 | if (with_spread) { |
7935 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7936 | tmp &= ~SBI_SSCCTL_PATHALT; | |
7937 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 7938 | |
2fa86a1f PZ |
7939 | if (with_fdi) { |
7940 | lpt_reset_fdi_mphy(dev_priv); | |
7941 | lpt_program_fdi_mphy(dev_priv); | |
7942 | } | |
7943 | } | |
dde86e2d | 7944 | |
2fa86a1f PZ |
7945 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
7946 | SBI_GEN0 : SBI_DBUFF0; | |
7947 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
7948 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
7949 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 DV |
7950 | |
7951 | mutex_unlock(&dev_priv->dpio_lock); | |
dde86e2d PZ |
7952 | } |
7953 | ||
47701c3b PZ |
7954 | /* Sequence to disable CLKOUT_DP */ |
7955 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
7956 | { | |
7957 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7958 | uint32_t reg, tmp; | |
7959 | ||
7960 | mutex_lock(&dev_priv->dpio_lock); | |
7961 | ||
7962 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? | |
7963 | SBI_GEN0 : SBI_DBUFF0; | |
7964 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
7965 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
7966 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
7967 | ||
7968 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7969 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
7970 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
7971 | tmp |= SBI_SSCCTL_PATHALT; | |
7972 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7973 | udelay(32); | |
7974 | } | |
7975 | tmp |= SBI_SSCCTL_DISABLE; | |
7976 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7977 | } | |
7978 | ||
7979 | mutex_unlock(&dev_priv->dpio_lock); | |
7980 | } | |
7981 | ||
bf8fa3d3 PZ |
7982 | static void lpt_init_pch_refclk(struct drm_device *dev) |
7983 | { | |
bf8fa3d3 PZ |
7984 | struct intel_encoder *encoder; |
7985 | bool has_vga = false; | |
7986 | ||
b2784e15 | 7987 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
7988 | switch (encoder->type) { |
7989 | case INTEL_OUTPUT_ANALOG: | |
7990 | has_vga = true; | |
7991 | break; | |
6847d71b PZ |
7992 | default: |
7993 | break; | |
bf8fa3d3 PZ |
7994 | } |
7995 | } | |
7996 | ||
47701c3b PZ |
7997 | if (has_vga) |
7998 | lpt_enable_clkout_dp(dev, true, true); | |
7999 | else | |
8000 | lpt_disable_clkout_dp(dev); | |
bf8fa3d3 PZ |
8001 | } |
8002 | ||
dde86e2d PZ |
8003 | /* |
8004 | * Initialize reference clocks when the driver loads | |
8005 | */ | |
8006 | void intel_init_pch_refclk(struct drm_device *dev) | |
8007 | { | |
8008 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
8009 | ironlake_init_pch_refclk(dev); | |
8010 | else if (HAS_PCH_LPT(dev)) | |
8011 | lpt_init_pch_refclk(dev); | |
8012 | } | |
8013 | ||
55bb9992 | 8014 | static int ironlake_get_refclk(struct intel_crtc_state *crtc_state) |
d9d444cb | 8015 | { |
55bb9992 | 8016 | struct drm_device *dev = crtc_state->base.crtc->dev; |
d9d444cb | 8017 | struct drm_i915_private *dev_priv = dev->dev_private; |
55bb9992 ACO |
8018 | struct drm_atomic_state *state = crtc_state->base.state; |
8019 | struct drm_connector_state *connector_state; | |
d9d444cb | 8020 | struct intel_encoder *encoder; |
55bb9992 | 8021 | int num_connectors = 0, i; |
d9d444cb JB |
8022 | bool is_lvds = false; |
8023 | ||
55bb9992 ACO |
8024 | for (i = 0; i < state->num_connector; i++) { |
8025 | if (!state->connectors[i]) | |
d0737e1d ACO |
8026 | continue; |
8027 | ||
55bb9992 ACO |
8028 | connector_state = state->connector_states[i]; |
8029 | if (connector_state->crtc != crtc_state->base.crtc) | |
8030 | continue; | |
8031 | ||
8032 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8033 | ||
d9d444cb JB |
8034 | switch (encoder->type) { |
8035 | case INTEL_OUTPUT_LVDS: | |
8036 | is_lvds = true; | |
8037 | break; | |
6847d71b PZ |
8038 | default: |
8039 | break; | |
d9d444cb JB |
8040 | } |
8041 | num_connectors++; | |
8042 | } | |
8043 | ||
8044 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
e91e941b | 8045 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
41aa3448 | 8046 | dev_priv->vbt.lvds_ssc_freq); |
e91e941b | 8047 | return dev_priv->vbt.lvds_ssc_freq; |
d9d444cb JB |
8048 | } |
8049 | ||
8050 | return 120000; | |
8051 | } | |
8052 | ||
6ff93609 | 8053 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 8054 | { |
c8203565 | 8055 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
8056 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8057 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
8058 | uint32_t val; |
8059 | ||
78114071 | 8060 | val = 0; |
c8203565 | 8061 | |
6e3c9717 | 8062 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 8063 | case 18: |
dfd07d72 | 8064 | val |= PIPECONF_6BPC; |
c8203565 PZ |
8065 | break; |
8066 | case 24: | |
dfd07d72 | 8067 | val |= PIPECONF_8BPC; |
c8203565 PZ |
8068 | break; |
8069 | case 30: | |
dfd07d72 | 8070 | val |= PIPECONF_10BPC; |
c8203565 PZ |
8071 | break; |
8072 | case 36: | |
dfd07d72 | 8073 | val |= PIPECONF_12BPC; |
c8203565 PZ |
8074 | break; |
8075 | default: | |
cc769b62 PZ |
8076 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
8077 | BUG(); | |
c8203565 PZ |
8078 | } |
8079 | ||
6e3c9717 | 8080 | if (intel_crtc->config->dither) |
c8203565 PZ |
8081 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8082 | ||
6e3c9717 | 8083 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
8084 | val |= PIPECONF_INTERLACED_ILK; |
8085 | else | |
8086 | val |= PIPECONF_PROGRESSIVE; | |
8087 | ||
6e3c9717 | 8088 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 8089 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 8090 | |
c8203565 PZ |
8091 | I915_WRITE(PIPECONF(pipe), val); |
8092 | POSTING_READ(PIPECONF(pipe)); | |
8093 | } | |
8094 | ||
86d3efce VS |
8095 | /* |
8096 | * Set up the pipe CSC unit. | |
8097 | * | |
8098 | * Currently only full range RGB to limited range RGB conversion | |
8099 | * is supported, but eventually this should handle various | |
8100 | * RGB<->YCbCr scenarios as well. | |
8101 | */ | |
50f3b016 | 8102 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
8103 | { |
8104 | struct drm_device *dev = crtc->dev; | |
8105 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8106 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8107 | int pipe = intel_crtc->pipe; | |
8108 | uint16_t coeff = 0x7800; /* 1.0 */ | |
8109 | ||
8110 | /* | |
8111 | * TODO: Check what kind of values actually come out of the pipe | |
8112 | * with these coeff/postoff values and adjust to get the best | |
8113 | * accuracy. Perhaps we even need to take the bpc value into | |
8114 | * consideration. | |
8115 | */ | |
8116 | ||
6e3c9717 | 8117 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
8118 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
8119 | ||
8120 | /* | |
8121 | * GY/GU and RY/RU should be the other way around according | |
8122 | * to BSpec, but reality doesn't agree. Just set them up in | |
8123 | * a way that results in the correct picture. | |
8124 | */ | |
8125 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
8126 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
8127 | ||
8128 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
8129 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
8130 | ||
8131 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
8132 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
8133 | ||
8134 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
8135 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
8136 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
8137 | ||
8138 | if (INTEL_INFO(dev)->gen > 6) { | |
8139 | uint16_t postoff = 0; | |
8140 | ||
6e3c9717 | 8141 | if (intel_crtc->config->limited_color_range) |
32cf0cb0 | 8142 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
86d3efce VS |
8143 | |
8144 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
8145 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
8146 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
8147 | ||
8148 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
8149 | } else { | |
8150 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
8151 | ||
6e3c9717 | 8152 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
8153 | mode |= CSC_BLACK_SCREEN_OFFSET; |
8154 | ||
8155 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
8156 | } | |
8157 | } | |
8158 | ||
6ff93609 | 8159 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 8160 | { |
756f85cf PZ |
8161 | struct drm_device *dev = crtc->dev; |
8162 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 8163 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 8164 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 8165 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee2b0b38 PZ |
8166 | uint32_t val; |
8167 | ||
3eff4faa | 8168 | val = 0; |
ee2b0b38 | 8169 | |
6e3c9717 | 8170 | if (IS_HASWELL(dev) && intel_crtc->config->dither) |
ee2b0b38 PZ |
8171 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8172 | ||
6e3c9717 | 8173 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
8174 | val |= PIPECONF_INTERLACED_ILK; |
8175 | else | |
8176 | val |= PIPECONF_PROGRESSIVE; | |
8177 | ||
702e7a56 PZ |
8178 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
8179 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
8180 | |
8181 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
8182 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf | 8183 | |
3cdf122c | 8184 | if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { |
756f85cf PZ |
8185 | val = 0; |
8186 | ||
6e3c9717 | 8187 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
8188 | case 18: |
8189 | val |= PIPEMISC_DITHER_6_BPC; | |
8190 | break; | |
8191 | case 24: | |
8192 | val |= PIPEMISC_DITHER_8_BPC; | |
8193 | break; | |
8194 | case 30: | |
8195 | val |= PIPEMISC_DITHER_10_BPC; | |
8196 | break; | |
8197 | case 36: | |
8198 | val |= PIPEMISC_DITHER_12_BPC; | |
8199 | break; | |
8200 | default: | |
8201 | /* Case prevented by pipe_config_set_bpp. */ | |
8202 | BUG(); | |
8203 | } | |
8204 | ||
6e3c9717 | 8205 | if (intel_crtc->config->dither) |
756f85cf PZ |
8206 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
8207 | ||
8208 | I915_WRITE(PIPEMISC(pipe), val); | |
8209 | } | |
ee2b0b38 PZ |
8210 | } |
8211 | ||
6591c6e4 | 8212 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
190f68c5 | 8213 | struct intel_crtc_state *crtc_state, |
6591c6e4 PZ |
8214 | intel_clock_t *clock, |
8215 | bool *has_reduced_clock, | |
8216 | intel_clock_t *reduced_clock) | |
8217 | { | |
8218 | struct drm_device *dev = crtc->dev; | |
8219 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6591c6e4 | 8220 | int refclk; |
d4906093 | 8221 | const intel_limit_t *limit; |
a16af721 | 8222 | bool ret, is_lvds = false; |
79e53945 | 8223 | |
a93e255f | 8224 | is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS); |
79e53945 | 8225 | |
55bb9992 | 8226 | refclk = ironlake_get_refclk(crtc_state); |
79e53945 | 8227 | |
d4906093 ML |
8228 | /* |
8229 | * Returns a set of divisors for the desired target clock with the given | |
8230 | * refclk, or FALSE. The returned values represent the clock equation: | |
8231 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
8232 | */ | |
a93e255f ACO |
8233 | limit = intel_limit(crtc_state, refclk); |
8234 | ret = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 8235 | crtc_state->port_clock, |
ee9300bb | 8236 | refclk, NULL, clock); |
6591c6e4 PZ |
8237 | if (!ret) |
8238 | return false; | |
cda4b7d3 | 8239 | |
ddc9003c | 8240 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
8241 | /* |
8242 | * Ensure we match the reduced clock's P to the target clock. | |
8243 | * If the clocks don't match, we can't switch the display clock | |
8244 | * by using the FP0/FP1. In such case we will disable the LVDS | |
8245 | * downclock feature. | |
8246 | */ | |
ee9300bb | 8247 | *has_reduced_clock = |
a93e255f | 8248 | dev_priv->display.find_dpll(limit, crtc_state, |
ee9300bb DV |
8249 | dev_priv->lvds_downclock, |
8250 | refclk, clock, | |
8251 | reduced_clock); | |
652c393a | 8252 | } |
61e9653f | 8253 | |
6591c6e4 PZ |
8254 | return true; |
8255 | } | |
8256 | ||
d4b1931c PZ |
8257 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
8258 | { | |
8259 | /* | |
8260 | * Account for spread spectrum to avoid | |
8261 | * oversubscribing the link. Max center spread | |
8262 | * is 2.5%; use 5% for safety's sake. | |
8263 | */ | |
8264 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 8265 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
8266 | } |
8267 | ||
7429e9d4 | 8268 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 8269 | { |
7429e9d4 | 8270 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
8271 | } |
8272 | ||
de13a2e3 | 8273 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
190f68c5 | 8274 | struct intel_crtc_state *crtc_state, |
7429e9d4 | 8275 | u32 *fp, |
9a7c7890 | 8276 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 8277 | { |
de13a2e3 | 8278 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
8279 | struct drm_device *dev = crtc->dev; |
8280 | struct drm_i915_private *dev_priv = dev->dev_private; | |
55bb9992 ACO |
8281 | struct drm_atomic_state *state = crtc_state->base.state; |
8282 | struct drm_connector_state *connector_state; | |
8283 | struct intel_encoder *encoder; | |
de13a2e3 | 8284 | uint32_t dpll; |
55bb9992 | 8285 | int factor, num_connectors = 0, i; |
09ede541 | 8286 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 8287 | |
55bb9992 ACO |
8288 | for (i = 0; i < state->num_connector; i++) { |
8289 | if (!state->connectors[i]) | |
d0737e1d ACO |
8290 | continue; |
8291 | ||
55bb9992 ACO |
8292 | connector_state = state->connector_states[i]; |
8293 | if (connector_state->crtc != crtc_state->base.crtc) | |
8294 | continue; | |
8295 | ||
8296 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8297 | ||
8298 | switch (encoder->type) { | |
79e53945 JB |
8299 | case INTEL_OUTPUT_LVDS: |
8300 | is_lvds = true; | |
8301 | break; | |
8302 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 8303 | case INTEL_OUTPUT_HDMI: |
79e53945 | 8304 | is_sdvo = true; |
79e53945 | 8305 | break; |
6847d71b PZ |
8306 | default: |
8307 | break; | |
79e53945 | 8308 | } |
43565a06 | 8309 | |
c751ce4f | 8310 | num_connectors++; |
79e53945 | 8311 | } |
79e53945 | 8312 | |
c1858123 | 8313 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
8314 | factor = 21; |
8315 | if (is_lvds) { | |
8316 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 8317 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 8318 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 8319 | factor = 25; |
190f68c5 | 8320 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 8321 | factor = 20; |
c1858123 | 8322 | |
190f68c5 | 8323 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
7d0ac5b7 | 8324 | *fp |= FP_CB_TUNE; |
2c07245f | 8325 | |
9a7c7890 DV |
8326 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
8327 | *fp2 |= FP_CB_TUNE; | |
8328 | ||
5eddb70b | 8329 | dpll = 0; |
2c07245f | 8330 | |
a07d6787 EA |
8331 | if (is_lvds) |
8332 | dpll |= DPLLB_MODE_LVDS; | |
8333 | else | |
8334 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 8335 | |
190f68c5 | 8336 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 8337 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f DV |
8338 | |
8339 | if (is_sdvo) | |
4a33e48d | 8340 | dpll |= DPLL_SDVO_HIGH_SPEED; |
190f68c5 | 8341 | if (crtc_state->has_dp_encoder) |
4a33e48d | 8342 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 8343 | |
a07d6787 | 8344 | /* compute bitmask from p1 value */ |
190f68c5 | 8345 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 8346 | /* also FPA1 */ |
190f68c5 | 8347 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 8348 | |
190f68c5 | 8349 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
8350 | case 5: |
8351 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
8352 | break; | |
8353 | case 7: | |
8354 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
8355 | break; | |
8356 | case 10: | |
8357 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
8358 | break; | |
8359 | case 14: | |
8360 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
8361 | break; | |
79e53945 JB |
8362 | } |
8363 | ||
b4c09f3b | 8364 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 8365 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
8366 | else |
8367 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8368 | ||
959e16d6 | 8369 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
8370 | } |
8371 | ||
190f68c5 ACO |
8372 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
8373 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 8374 | { |
c7653199 | 8375 | struct drm_device *dev = crtc->base.dev; |
de13a2e3 | 8376 | intel_clock_t clock, reduced_clock; |
cbbab5bd | 8377 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 8378 | bool ok, has_reduced_clock = false; |
8b47047b | 8379 | bool is_lvds = false; |
e2b78267 | 8380 | struct intel_shared_dpll *pll; |
de13a2e3 | 8381 | |
409ee761 | 8382 | is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS); |
79e53945 | 8383 | |
5dc5298b PZ |
8384 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
8385 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 8386 | |
190f68c5 | 8387 | ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock, |
de13a2e3 | 8388 | &has_reduced_clock, &reduced_clock); |
190f68c5 | 8389 | if (!ok && !crtc_state->clock_set) { |
de13a2e3 PZ |
8390 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
8391 | return -EINVAL; | |
79e53945 | 8392 | } |
f47709a9 | 8393 | /* Compat-code for transition, will disappear. */ |
190f68c5 ACO |
8394 | if (!crtc_state->clock_set) { |
8395 | crtc_state->dpll.n = clock.n; | |
8396 | crtc_state->dpll.m1 = clock.m1; | |
8397 | crtc_state->dpll.m2 = clock.m2; | |
8398 | crtc_state->dpll.p1 = clock.p1; | |
8399 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 8400 | } |
79e53945 | 8401 | |
5dc5298b | 8402 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
190f68c5 ACO |
8403 | if (crtc_state->has_pch_encoder) { |
8404 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); | |
cbbab5bd | 8405 | if (has_reduced_clock) |
7429e9d4 | 8406 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 8407 | |
190f68c5 | 8408 | dpll = ironlake_compute_dpll(crtc, crtc_state, |
cbbab5bd DV |
8409 | &fp, &reduced_clock, |
8410 | has_reduced_clock ? &fp2 : NULL); | |
8411 | ||
190f68c5 ACO |
8412 | crtc_state->dpll_hw_state.dpll = dpll; |
8413 | crtc_state->dpll_hw_state.fp0 = fp; | |
66e985c0 | 8414 | if (has_reduced_clock) |
190f68c5 | 8415 | crtc_state->dpll_hw_state.fp1 = fp2; |
66e985c0 | 8416 | else |
190f68c5 | 8417 | crtc_state->dpll_hw_state.fp1 = fp; |
66e985c0 | 8418 | |
190f68c5 | 8419 | pll = intel_get_shared_dpll(crtc, crtc_state); |
ee7b9f93 | 8420 | if (pll == NULL) { |
84f44ce7 | 8421 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
c7653199 | 8422 | pipe_name(crtc->pipe)); |
4b645f14 JB |
8423 | return -EINVAL; |
8424 | } | |
3fb37703 | 8425 | } |
79e53945 | 8426 | |
ab585dea | 8427 | if (is_lvds && has_reduced_clock) |
c7653199 | 8428 | crtc->lowfreq_avail = true; |
bcd644e0 | 8429 | else |
c7653199 | 8430 | crtc->lowfreq_avail = false; |
e2b78267 | 8431 | |
c8f7a0db | 8432 | return 0; |
79e53945 JB |
8433 | } |
8434 | ||
eb14cb74 VS |
8435 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
8436 | struct intel_link_m_n *m_n) | |
8437 | { | |
8438 | struct drm_device *dev = crtc->base.dev; | |
8439 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8440 | enum pipe pipe = crtc->pipe; | |
8441 | ||
8442 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
8443 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
8444 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8445 | & ~TU_SIZE_MASK; | |
8446 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
8447 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8448 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8449 | } | |
8450 | ||
8451 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
8452 | enum transcoder transcoder, | |
b95af8be VK |
8453 | struct intel_link_m_n *m_n, |
8454 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
8455 | { |
8456 | struct drm_device *dev = crtc->base.dev; | |
8457 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 8458 | enum pipe pipe = crtc->pipe; |
72419203 | 8459 | |
eb14cb74 VS |
8460 | if (INTEL_INFO(dev)->gen >= 5) { |
8461 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
8462 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
8463 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
8464 | & ~TU_SIZE_MASK; | |
8465 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
8466 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
8467 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
8468 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
8469 | * gen < 8) and if DRRS is supported (to make sure the | |
8470 | * registers are not unnecessarily read). | |
8471 | */ | |
8472 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
6e3c9717 | 8473 | crtc->config->has_drrs) { |
b95af8be VK |
8474 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
8475 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
8476 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
8477 | & ~TU_SIZE_MASK; | |
8478 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
8479 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
8480 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8481 | } | |
eb14cb74 VS |
8482 | } else { |
8483 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
8484 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
8485 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8486 | & ~TU_SIZE_MASK; | |
8487 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
8488 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8489 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8490 | } | |
8491 | } | |
8492 | ||
8493 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 8494 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 8495 | { |
681a8504 | 8496 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
8497 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
8498 | else | |
8499 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
8500 | &pipe_config->dp_m_n, |
8501 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 8502 | } |
72419203 | 8503 | |
eb14cb74 | 8504 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 8505 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
8506 | { |
8507 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 8508 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
8509 | } |
8510 | ||
bd2e244f | 8511 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8512 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
8513 | { |
8514 | struct drm_device *dev = crtc->base.dev; | |
8515 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a1b2278e CK |
8516 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
8517 | uint32_t ps_ctrl = 0; | |
8518 | int id = -1; | |
8519 | int i; | |
bd2e244f | 8520 | |
a1b2278e CK |
8521 | /* find scaler attached to this pipe */ |
8522 | for (i = 0; i < crtc->num_scalers; i++) { | |
8523 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
8524 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
8525 | id = i; | |
8526 | pipe_config->pch_pfit.enabled = true; | |
8527 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
8528 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
8529 | break; | |
8530 | } | |
8531 | } | |
bd2e244f | 8532 | |
a1b2278e CK |
8533 | scaler_state->scaler_id = id; |
8534 | if (id >= 0) { | |
8535 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
8536 | } else { | |
8537 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
8538 | } |
8539 | } | |
8540 | ||
5724dbd1 DL |
8541 | static void |
8542 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
8543 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
8544 | { |
8545 | struct drm_device *dev = crtc->base.dev; | |
8546 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40f46283 | 8547 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
8548 | int pipe = crtc->pipe; |
8549 | int fourcc, pixel_format; | |
6761dd31 | 8550 | unsigned int aligned_height; |
bc8d7dff | 8551 | struct drm_framebuffer *fb; |
1b842c89 | 8552 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 8553 | |
d9806c9f | 8554 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8555 | if (!intel_fb) { |
bc8d7dff DL |
8556 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8557 | return; | |
8558 | } | |
8559 | ||
1b842c89 DL |
8560 | fb = &intel_fb->base; |
8561 | ||
bc8d7dff | 8562 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
8563 | if (!(val & PLANE_CTL_ENABLE)) |
8564 | goto error; | |
8565 | ||
bc8d7dff DL |
8566 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
8567 | fourcc = skl_format_to_fourcc(pixel_format, | |
8568 | val & PLANE_CTL_ORDER_RGBX, | |
8569 | val & PLANE_CTL_ALPHA_MASK); | |
8570 | fb->pixel_format = fourcc; | |
8571 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
8572 | ||
40f46283 DL |
8573 | tiling = val & PLANE_CTL_TILED_MASK; |
8574 | switch (tiling) { | |
8575 | case PLANE_CTL_TILED_LINEAR: | |
8576 | fb->modifier[0] = DRM_FORMAT_MOD_NONE; | |
8577 | break; | |
8578 | case PLANE_CTL_TILED_X: | |
8579 | plane_config->tiling = I915_TILING_X; | |
8580 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
8581 | break; | |
8582 | case PLANE_CTL_TILED_Y: | |
8583 | fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; | |
8584 | break; | |
8585 | case PLANE_CTL_TILED_YF: | |
8586 | fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; | |
8587 | break; | |
8588 | default: | |
8589 | MISSING_CASE(tiling); | |
8590 | goto error; | |
8591 | } | |
8592 | ||
bc8d7dff DL |
8593 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
8594 | plane_config->base = base; | |
8595 | ||
8596 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
8597 | ||
8598 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
8599 | fb->height = ((val >> 16) & 0xfff) + 1; | |
8600 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
8601 | ||
8602 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
40f46283 DL |
8603 | stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0], |
8604 | fb->pixel_format); | |
bc8d7dff DL |
8605 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
8606 | ||
8607 | aligned_height = intel_fb_align_height(dev, fb->height, | |
091df6cb DV |
8608 | fb->pixel_format, |
8609 | fb->modifier[0]); | |
bc8d7dff | 8610 | |
f37b5c2b | 8611 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
8612 | |
8613 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
8614 | pipe_name(pipe), fb->width, fb->height, | |
8615 | fb->bits_per_pixel, base, fb->pitches[0], | |
8616 | plane_config->size); | |
8617 | ||
2d14030b | 8618 | plane_config->fb = intel_fb; |
bc8d7dff DL |
8619 | return; |
8620 | ||
8621 | error: | |
8622 | kfree(fb); | |
8623 | } | |
8624 | ||
2fa2fe9a | 8625 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8626 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
8627 | { |
8628 | struct drm_device *dev = crtc->base.dev; | |
8629 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8630 | uint32_t tmp; | |
8631 | ||
8632 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
8633 | ||
8634 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 8635 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
8636 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
8637 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
8638 | |
8639 | /* We currently do not free assignements of panel fitters on | |
8640 | * ivb/hsw (since we don't use the higher upscaling modes which | |
8641 | * differentiates them) so just WARN about this case for now. */ | |
8642 | if (IS_GEN7(dev)) { | |
8643 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
8644 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
8645 | } | |
2fa2fe9a | 8646 | } |
79e53945 JB |
8647 | } |
8648 | ||
5724dbd1 DL |
8649 | static void |
8650 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
8651 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
8652 | { |
8653 | struct drm_device *dev = crtc->base.dev; | |
8654 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8655 | u32 val, base, offset; | |
aeee5a49 | 8656 | int pipe = crtc->pipe; |
4c6baa59 | 8657 | int fourcc, pixel_format; |
6761dd31 | 8658 | unsigned int aligned_height; |
b113d5ee | 8659 | struct drm_framebuffer *fb; |
1b842c89 | 8660 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 8661 | |
42a7b088 DL |
8662 | val = I915_READ(DSPCNTR(pipe)); |
8663 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8664 | return; | |
8665 | ||
d9806c9f | 8666 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8667 | if (!intel_fb) { |
4c6baa59 JB |
8668 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8669 | return; | |
8670 | } | |
8671 | ||
1b842c89 DL |
8672 | fb = &intel_fb->base; |
8673 | ||
18c5247e DV |
8674 | if (INTEL_INFO(dev)->gen >= 4) { |
8675 | if (val & DISPPLANE_TILED) { | |
49af449b | 8676 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
8677 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
8678 | } | |
8679 | } | |
4c6baa59 JB |
8680 | |
8681 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8682 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
8683 | fb->pixel_format = fourcc; |
8684 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
4c6baa59 | 8685 | |
aeee5a49 | 8686 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
4c6baa59 | 8687 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
aeee5a49 | 8688 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 8689 | } else { |
49af449b | 8690 | if (plane_config->tiling) |
aeee5a49 | 8691 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 8692 | else |
aeee5a49 | 8693 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
8694 | } |
8695 | plane_config->base = base; | |
8696 | ||
8697 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8698 | fb->width = ((val >> 16) & 0xfff) + 1; |
8699 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
8700 | |
8701 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8702 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 8703 | |
b113d5ee | 8704 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
8705 | fb->pixel_format, |
8706 | fb->modifier[0]); | |
4c6baa59 | 8707 | |
f37b5c2b | 8708 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 8709 | |
2844a921 DL |
8710 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8711 | pipe_name(pipe), fb->width, fb->height, | |
8712 | fb->bits_per_pixel, base, fb->pitches[0], | |
8713 | plane_config->size); | |
b113d5ee | 8714 | |
2d14030b | 8715 | plane_config->fb = intel_fb; |
4c6baa59 JB |
8716 | } |
8717 | ||
0e8ffe1b | 8718 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8719 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8720 | { |
8721 | struct drm_device *dev = crtc->base.dev; | |
8722 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8723 | uint32_t tmp; | |
8724 | ||
f458ebbc DV |
8725 | if (!intel_display_power_is_enabled(dev_priv, |
8726 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
930e8c9e PZ |
8727 | return false; |
8728 | ||
e143a21c | 8729 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 8730 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 8731 | |
0e8ffe1b DV |
8732 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8733 | if (!(tmp & PIPECONF_ENABLE)) | |
8734 | return false; | |
8735 | ||
42571aef VS |
8736 | switch (tmp & PIPECONF_BPC_MASK) { |
8737 | case PIPECONF_6BPC: | |
8738 | pipe_config->pipe_bpp = 18; | |
8739 | break; | |
8740 | case PIPECONF_8BPC: | |
8741 | pipe_config->pipe_bpp = 24; | |
8742 | break; | |
8743 | case PIPECONF_10BPC: | |
8744 | pipe_config->pipe_bpp = 30; | |
8745 | break; | |
8746 | case PIPECONF_12BPC: | |
8747 | pipe_config->pipe_bpp = 36; | |
8748 | break; | |
8749 | default: | |
8750 | break; | |
8751 | } | |
8752 | ||
b5a9fa09 DV |
8753 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
8754 | pipe_config->limited_color_range = true; | |
8755 | ||
ab9412ba | 8756 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
8757 | struct intel_shared_dpll *pll; |
8758 | ||
88adfff1 DV |
8759 | pipe_config->has_pch_encoder = true; |
8760 | ||
627eb5a3 DV |
8761 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
8762 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
8763 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
8764 | |
8765 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 8766 | |
c0d43d62 | 8767 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
8768 | pipe_config->shared_dpll = |
8769 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
8770 | } else { |
8771 | tmp = I915_READ(PCH_DPLL_SEL); | |
8772 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
8773 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
8774 | else | |
8775 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
8776 | } | |
66e985c0 DV |
8777 | |
8778 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
8779 | ||
8780 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
8781 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
8782 | |
8783 | tmp = pipe_config->dpll_hw_state.dpll; | |
8784 | pipe_config->pixel_multiplier = | |
8785 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
8786 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
8787 | |
8788 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
8789 | } else { |
8790 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
8791 | } |
8792 | ||
1bd1bd80 DV |
8793 | intel_get_pipe_timings(crtc, pipe_config); |
8794 | ||
2fa2fe9a DV |
8795 | ironlake_get_pfit_config(crtc, pipe_config); |
8796 | ||
0e8ffe1b DV |
8797 | return true; |
8798 | } | |
8799 | ||
be256dc7 PZ |
8800 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
8801 | { | |
8802 | struct drm_device *dev = dev_priv->dev; | |
be256dc7 | 8803 | struct intel_crtc *crtc; |
be256dc7 | 8804 | |
d3fcc808 | 8805 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 8806 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
8807 | pipe_name(crtc->pipe)); |
8808 | ||
e2c719b7 RC |
8809 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
8810 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
8811 | I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); | |
8812 | I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
8813 | I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); | |
8814 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
be256dc7 | 8815 | "CPU PWM1 enabled\n"); |
c5107b87 | 8816 | if (IS_HASWELL(dev)) |
e2c719b7 | 8817 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 8818 | "CPU PWM2 enabled\n"); |
e2c719b7 | 8819 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 8820 | "PCH PWM1 enabled\n"); |
e2c719b7 | 8821 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 8822 | "Utility pin enabled\n"); |
e2c719b7 | 8823 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 8824 | |
9926ada1 PZ |
8825 | /* |
8826 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
8827 | * interrupts remain enabled. We used to check for that, but since it's | |
8828 | * gen-specific and since we only disable LCPLL after we fully disable | |
8829 | * the interrupts, the check below should be enough. | |
8830 | */ | |
e2c719b7 | 8831 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
8832 | } |
8833 | ||
9ccd5aeb PZ |
8834 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
8835 | { | |
8836 | struct drm_device *dev = dev_priv->dev; | |
8837 | ||
8838 | if (IS_HASWELL(dev)) | |
8839 | return I915_READ(D_COMP_HSW); | |
8840 | else | |
8841 | return I915_READ(D_COMP_BDW); | |
8842 | } | |
8843 | ||
3c4c9b81 PZ |
8844 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
8845 | { | |
8846 | struct drm_device *dev = dev_priv->dev; | |
8847 | ||
8848 | if (IS_HASWELL(dev)) { | |
8849 | mutex_lock(&dev_priv->rps.hw_lock); | |
8850 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
8851 | val)) | |
f475dadf | 8852 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
8853 | mutex_unlock(&dev_priv->rps.hw_lock); |
8854 | } else { | |
9ccd5aeb PZ |
8855 | I915_WRITE(D_COMP_BDW, val); |
8856 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 8857 | } |
be256dc7 PZ |
8858 | } |
8859 | ||
8860 | /* | |
8861 | * This function implements pieces of two sequences from BSpec: | |
8862 | * - Sequence for display software to disable LCPLL | |
8863 | * - Sequence for display software to allow package C8+ | |
8864 | * The steps implemented here are just the steps that actually touch the LCPLL | |
8865 | * register. Callers should take care of disabling all the display engine | |
8866 | * functions, doing the mode unset, fixing interrupts, etc. | |
8867 | */ | |
6ff58d53 PZ |
8868 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
8869 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
8870 | { |
8871 | uint32_t val; | |
8872 | ||
8873 | assert_can_disable_lcpll(dev_priv); | |
8874 | ||
8875 | val = I915_READ(LCPLL_CTL); | |
8876 | ||
8877 | if (switch_to_fclk) { | |
8878 | val |= LCPLL_CD_SOURCE_FCLK; | |
8879 | I915_WRITE(LCPLL_CTL, val); | |
8880 | ||
8881 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
8882 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
8883 | DRM_ERROR("Switching to FCLK failed\n"); | |
8884 | ||
8885 | val = I915_READ(LCPLL_CTL); | |
8886 | } | |
8887 | ||
8888 | val |= LCPLL_PLL_DISABLE; | |
8889 | I915_WRITE(LCPLL_CTL, val); | |
8890 | POSTING_READ(LCPLL_CTL); | |
8891 | ||
8892 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
8893 | DRM_ERROR("LCPLL still locked\n"); | |
8894 | ||
9ccd5aeb | 8895 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 8896 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 8897 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
8898 | ndelay(100); |
8899 | ||
9ccd5aeb PZ |
8900 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
8901 | 1)) | |
be256dc7 PZ |
8902 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
8903 | ||
8904 | if (allow_power_down) { | |
8905 | val = I915_READ(LCPLL_CTL); | |
8906 | val |= LCPLL_POWER_DOWN_ALLOW; | |
8907 | I915_WRITE(LCPLL_CTL, val); | |
8908 | POSTING_READ(LCPLL_CTL); | |
8909 | } | |
8910 | } | |
8911 | ||
8912 | /* | |
8913 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
8914 | * source. | |
8915 | */ | |
6ff58d53 | 8916 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
8917 | { |
8918 | uint32_t val; | |
8919 | ||
8920 | val = I915_READ(LCPLL_CTL); | |
8921 | ||
8922 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
8923 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
8924 | return; | |
8925 | ||
a8a8bd54 PZ |
8926 | /* |
8927 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
8928 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 8929 | */ |
59bad947 | 8930 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 8931 | |
be256dc7 PZ |
8932 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
8933 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
8934 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 8935 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
8936 | } |
8937 | ||
9ccd5aeb | 8938 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
8939 | val |= D_COMP_COMP_FORCE; |
8940 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 8941 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
8942 | |
8943 | val = I915_READ(LCPLL_CTL); | |
8944 | val &= ~LCPLL_PLL_DISABLE; | |
8945 | I915_WRITE(LCPLL_CTL, val); | |
8946 | ||
8947 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
8948 | DRM_ERROR("LCPLL not locked yet\n"); | |
8949 | ||
8950 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
8951 | val = I915_READ(LCPLL_CTL); | |
8952 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
8953 | I915_WRITE(LCPLL_CTL, val); | |
8954 | ||
8955 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
8956 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
8957 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
8958 | } | |
215733fa | 8959 | |
59bad947 | 8960 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
be256dc7 PZ |
8961 | } |
8962 | ||
765dab67 PZ |
8963 | /* |
8964 | * Package states C8 and deeper are really deep PC states that can only be | |
8965 | * reached when all the devices on the system allow it, so even if the graphics | |
8966 | * device allows PC8+, it doesn't mean the system will actually get to these | |
8967 | * states. Our driver only allows PC8+ when going into runtime PM. | |
8968 | * | |
8969 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
8970 | * well is disabled and most interrupts are disabled, and these are also | |
8971 | * requirements for runtime PM. When these conditions are met, we manually do | |
8972 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
8973 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
8974 | * hang the machine. | |
8975 | * | |
8976 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
8977 | * the state of some registers, so when we come back from PC8+ we need to | |
8978 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
8979 | * need to take care of the registers kept by RC6. Notice that this happens even | |
8980 | * if we don't put the device in PCI D3 state (which is what currently happens | |
8981 | * because of the runtime PM support). | |
8982 | * | |
8983 | * For more, read "Display Sequences for Package C8" on the hardware | |
8984 | * documentation. | |
8985 | */ | |
a14cb6fc | 8986 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 8987 | { |
c67a470b PZ |
8988 | struct drm_device *dev = dev_priv->dev; |
8989 | uint32_t val; | |
8990 | ||
c67a470b PZ |
8991 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
8992 | ||
c67a470b PZ |
8993 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
8994 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
8995 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
8996 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
8997 | } | |
8998 | ||
8999 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
9000 | hsw_disable_lcpll(dev_priv, true, true); |
9001 | } | |
9002 | ||
a14cb6fc | 9003 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
9004 | { |
9005 | struct drm_device *dev = dev_priv->dev; | |
9006 | uint32_t val; | |
9007 | ||
c67a470b PZ |
9008 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
9009 | ||
9010 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
9011 | lpt_init_pch_refclk(dev); |
9012 | ||
9013 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
9014 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
9015 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
9016 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9017 | } | |
9018 | ||
9019 | intel_prepare_ddi(dev); | |
c67a470b PZ |
9020 | } |
9021 | ||
f8437dd1 VK |
9022 | static void broxton_modeset_global_resources(struct drm_atomic_state *state) |
9023 | { | |
9024 | struct drm_device *dev = state->dev; | |
9025 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9026 | int max_pixclk = intel_mode_max_pixclk(state); | |
9027 | int req_cdclk; | |
9028 | ||
9029 | /* see the comment in valleyview_modeset_global_resources */ | |
9030 | if (WARN_ON(max_pixclk < 0)) | |
9031 | return; | |
9032 | ||
9033 | req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk); | |
9034 | ||
9035 | if (req_cdclk != dev_priv->cdclk_freq) | |
9036 | broxton_set_cdclk(dev, req_cdclk); | |
9037 | } | |
9038 | ||
190f68c5 ACO |
9039 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
9040 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 9041 | { |
190f68c5 | 9042 | if (!intel_ddi_pll_select(crtc, crtc_state)) |
6441ab5f | 9043 | return -EINVAL; |
716c2e55 | 9044 | |
c7653199 | 9045 | crtc->lowfreq_avail = false; |
644cef34 | 9046 | |
c8f7a0db | 9047 | return 0; |
79e53945 JB |
9048 | } |
9049 | ||
96b7dfb7 S |
9050 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
9051 | enum port port, | |
5cec258b | 9052 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 9053 | { |
3148ade7 | 9054 | u32 temp, dpll_ctl1; |
96b7dfb7 S |
9055 | |
9056 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
9057 | pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); | |
9058 | ||
9059 | switch (pipe_config->ddi_pll_sel) { | |
3148ade7 DL |
9060 | case SKL_DPLL0: |
9061 | /* | |
9062 | * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part | |
9063 | * of the shared DPLL framework and thus needs to be read out | |
9064 | * separately | |
9065 | */ | |
9066 | dpll_ctl1 = I915_READ(DPLL_CTRL1); | |
9067 | pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f; | |
9068 | break; | |
96b7dfb7 S |
9069 | case SKL_DPLL1: |
9070 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
9071 | break; | |
9072 | case SKL_DPLL2: | |
9073 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
9074 | break; | |
9075 | case SKL_DPLL3: | |
9076 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
9077 | break; | |
96b7dfb7 S |
9078 | } |
9079 | } | |
9080 | ||
7d2c8175 DL |
9081 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
9082 | enum port port, | |
5cec258b | 9083 | struct intel_crtc_state *pipe_config) |
7d2c8175 DL |
9084 | { |
9085 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); | |
9086 | ||
9087 | switch (pipe_config->ddi_pll_sel) { | |
9088 | case PORT_CLK_SEL_WRPLL1: | |
9089 | pipe_config->shared_dpll = DPLL_ID_WRPLL1; | |
9090 | break; | |
9091 | case PORT_CLK_SEL_WRPLL2: | |
9092 | pipe_config->shared_dpll = DPLL_ID_WRPLL2; | |
9093 | break; | |
9094 | } | |
9095 | } | |
9096 | ||
26804afd | 9097 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 9098 | struct intel_crtc_state *pipe_config) |
26804afd DV |
9099 | { |
9100 | struct drm_device *dev = crtc->base.dev; | |
9101 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d452c5b6 | 9102 | struct intel_shared_dpll *pll; |
26804afd DV |
9103 | enum port port; |
9104 | uint32_t tmp; | |
9105 | ||
9106 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
9107 | ||
9108 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
9109 | ||
96b7dfb7 S |
9110 | if (IS_SKYLAKE(dev)) |
9111 | skylake_get_ddi_pll(dev_priv, port, pipe_config); | |
9112 | else | |
9113 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 9114 | |
d452c5b6 DV |
9115 | if (pipe_config->shared_dpll >= 0) { |
9116 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
9117 | ||
9118 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
9119 | &pipe_config->dpll_hw_state)); | |
9120 | } | |
9121 | ||
26804afd DV |
9122 | /* |
9123 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
9124 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
9125 | * the PCH transcoder is on. | |
9126 | */ | |
ca370455 DL |
9127 | if (INTEL_INFO(dev)->gen < 9 && |
9128 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
26804afd DV |
9129 | pipe_config->has_pch_encoder = true; |
9130 | ||
9131 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
9132 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9133 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
9134 | ||
9135 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
9136 | } | |
9137 | } | |
9138 | ||
0e8ffe1b | 9139 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9140 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9141 | { |
9142 | struct drm_device *dev = crtc->base.dev; | |
9143 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 9144 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
9145 | uint32_t tmp; |
9146 | ||
f458ebbc | 9147 | if (!intel_display_power_is_enabled(dev_priv, |
b5482bd0 ID |
9148 | POWER_DOMAIN_PIPE(crtc->pipe))) |
9149 | return false; | |
9150 | ||
e143a21c | 9151 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
9152 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
9153 | ||
eccb140b DV |
9154 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
9155 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
9156 | enum pipe trans_edp_pipe; | |
9157 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
9158 | default: | |
9159 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
9160 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
9161 | case TRANS_DDI_EDP_INPUT_A_ON: | |
9162 | trans_edp_pipe = PIPE_A; | |
9163 | break; | |
9164 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
9165 | trans_edp_pipe = PIPE_B; | |
9166 | break; | |
9167 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
9168 | trans_edp_pipe = PIPE_C; | |
9169 | break; | |
9170 | } | |
9171 | ||
9172 | if (trans_edp_pipe == crtc->pipe) | |
9173 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
9174 | } | |
9175 | ||
f458ebbc | 9176 | if (!intel_display_power_is_enabled(dev_priv, |
eccb140b | 9177 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
9178 | return false; |
9179 | ||
eccb140b | 9180 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
9181 | if (!(tmp & PIPECONF_ENABLE)) |
9182 | return false; | |
9183 | ||
26804afd | 9184 | haswell_get_ddi_port_state(crtc, pipe_config); |
627eb5a3 | 9185 | |
1bd1bd80 DV |
9186 | intel_get_pipe_timings(crtc, pipe_config); |
9187 | ||
a1b2278e CK |
9188 | if (INTEL_INFO(dev)->gen >= 9) { |
9189 | skl_init_scalers(dev, crtc, pipe_config); | |
9190 | } | |
9191 | ||
2fa2fe9a | 9192 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
bd2e244f JB |
9193 | if (intel_display_power_is_enabled(dev_priv, pfit_domain)) { |
9194 | if (IS_SKYLAKE(dev)) | |
9195 | skylake_get_pfit_config(crtc, pipe_config); | |
9196 | else | |
9197 | ironlake_get_pfit_config(crtc, pipe_config); | |
a1b2278e CK |
9198 | } else { |
9199 | pipe_config->scaler_state.scaler_id = -1; | |
9200 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f | 9201 | } |
88adfff1 | 9202 | |
e59150dc JB |
9203 | if (IS_HASWELL(dev)) |
9204 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
9205 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 9206 | |
ebb69c95 CT |
9207 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP) { |
9208 | pipe_config->pixel_multiplier = | |
9209 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
9210 | } else { | |
9211 | pipe_config->pixel_multiplier = 1; | |
9212 | } | |
6c49f241 | 9213 | |
0e8ffe1b DV |
9214 | return true; |
9215 | } | |
9216 | ||
560b85bb CW |
9217 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
9218 | { | |
9219 | struct drm_device *dev = crtc->dev; | |
9220 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9221 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dc41c154 | 9222 | uint32_t cntl = 0, size = 0; |
560b85bb | 9223 | |
dc41c154 | 9224 | if (base) { |
3dd512fb MR |
9225 | unsigned int width = intel_crtc->base.cursor->state->crtc_w; |
9226 | unsigned int height = intel_crtc->base.cursor->state->crtc_h; | |
dc41c154 VS |
9227 | unsigned int stride = roundup_pow_of_two(width) * 4; |
9228 | ||
9229 | switch (stride) { | |
9230 | default: | |
9231 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
9232 | width, stride); | |
9233 | stride = 256; | |
9234 | /* fallthrough */ | |
9235 | case 256: | |
9236 | case 512: | |
9237 | case 1024: | |
9238 | case 2048: | |
9239 | break; | |
4b0e333e CW |
9240 | } |
9241 | ||
dc41c154 VS |
9242 | cntl |= CURSOR_ENABLE | |
9243 | CURSOR_GAMMA_ENABLE | | |
9244 | CURSOR_FORMAT_ARGB | | |
9245 | CURSOR_STRIDE(stride); | |
9246 | ||
9247 | size = (height << 12) | width; | |
4b0e333e | 9248 | } |
560b85bb | 9249 | |
dc41c154 VS |
9250 | if (intel_crtc->cursor_cntl != 0 && |
9251 | (intel_crtc->cursor_base != base || | |
9252 | intel_crtc->cursor_size != size || | |
9253 | intel_crtc->cursor_cntl != cntl)) { | |
9254 | /* On these chipsets we can only modify the base/size/stride | |
9255 | * whilst the cursor is disabled. | |
9256 | */ | |
9257 | I915_WRITE(_CURACNTR, 0); | |
4b0e333e | 9258 | POSTING_READ(_CURACNTR); |
dc41c154 | 9259 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 9260 | } |
560b85bb | 9261 | |
99d1f387 | 9262 | if (intel_crtc->cursor_base != base) { |
9db4a9c7 | 9263 | I915_WRITE(_CURABASE, base); |
99d1f387 VS |
9264 | intel_crtc->cursor_base = base; |
9265 | } | |
4726e0b0 | 9266 | |
dc41c154 VS |
9267 | if (intel_crtc->cursor_size != size) { |
9268 | I915_WRITE(CURSIZE, size); | |
9269 | intel_crtc->cursor_size = size; | |
4b0e333e | 9270 | } |
560b85bb | 9271 | |
4b0e333e | 9272 | if (intel_crtc->cursor_cntl != cntl) { |
4b0e333e CW |
9273 | I915_WRITE(_CURACNTR, cntl); |
9274 | POSTING_READ(_CURACNTR); | |
4b0e333e | 9275 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 9276 | } |
560b85bb CW |
9277 | } |
9278 | ||
560b85bb | 9279 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) |
65a21cd6 JB |
9280 | { |
9281 | struct drm_device *dev = crtc->dev; | |
9282 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9283 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9284 | int pipe = intel_crtc->pipe; | |
4b0e333e CW |
9285 | uint32_t cntl; |
9286 | ||
9287 | cntl = 0; | |
9288 | if (base) { | |
9289 | cntl = MCURSOR_GAMMA_ENABLE; | |
3dd512fb | 9290 | switch (intel_crtc->base.cursor->state->crtc_w) { |
4726e0b0 SK |
9291 | case 64: |
9292 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
9293 | break; | |
9294 | case 128: | |
9295 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
9296 | break; | |
9297 | case 256: | |
9298 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
9299 | break; | |
9300 | default: | |
3dd512fb | 9301 | MISSING_CASE(intel_crtc->base.cursor->state->crtc_w); |
4726e0b0 | 9302 | return; |
65a21cd6 | 9303 | } |
4b0e333e | 9304 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 VS |
9305 | |
9306 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
9307 | cntl |= CURSOR_PIPE_CSC_ENABLE; | |
4b0e333e | 9308 | } |
65a21cd6 | 9309 | |
8e7d688b | 9310 | if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) |
4398ad45 VS |
9311 | cntl |= CURSOR_ROTATE_180; |
9312 | ||
4b0e333e CW |
9313 | if (intel_crtc->cursor_cntl != cntl) { |
9314 | I915_WRITE(CURCNTR(pipe), cntl); | |
9315 | POSTING_READ(CURCNTR(pipe)); | |
9316 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 9317 | } |
4b0e333e | 9318 | |
65a21cd6 | 9319 | /* and commit changes on next vblank */ |
5efb3e28 VS |
9320 | I915_WRITE(CURBASE(pipe), base); |
9321 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
9322 | |
9323 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
9324 | } |
9325 | ||
cda4b7d3 | 9326 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
9327 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
9328 | bool on) | |
cda4b7d3 CW |
9329 | { |
9330 | struct drm_device *dev = crtc->dev; | |
9331 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9332 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9333 | int pipe = intel_crtc->pipe; | |
3d7d6510 MR |
9334 | int x = crtc->cursor_x; |
9335 | int y = crtc->cursor_y; | |
d6e4db15 | 9336 | u32 base = 0, pos = 0; |
cda4b7d3 | 9337 | |
d6e4db15 | 9338 | if (on) |
cda4b7d3 | 9339 | base = intel_crtc->cursor_addr; |
cda4b7d3 | 9340 | |
6e3c9717 | 9341 | if (x >= intel_crtc->config->pipe_src_w) |
d6e4db15 VS |
9342 | base = 0; |
9343 | ||
6e3c9717 | 9344 | if (y >= intel_crtc->config->pipe_src_h) |
cda4b7d3 CW |
9345 | base = 0; |
9346 | ||
9347 | if (x < 0) { | |
3dd512fb | 9348 | if (x + intel_crtc->base.cursor->state->crtc_w <= 0) |
cda4b7d3 CW |
9349 | base = 0; |
9350 | ||
9351 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
9352 | x = -x; | |
9353 | } | |
9354 | pos |= x << CURSOR_X_SHIFT; | |
9355 | ||
9356 | if (y < 0) { | |
3dd512fb | 9357 | if (y + intel_crtc->base.cursor->state->crtc_h <= 0) |
cda4b7d3 CW |
9358 | base = 0; |
9359 | ||
9360 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
9361 | y = -y; | |
9362 | } | |
9363 | pos |= y << CURSOR_Y_SHIFT; | |
9364 | ||
4b0e333e | 9365 | if (base == 0 && intel_crtc->cursor_base == 0) |
cda4b7d3 CW |
9366 | return; |
9367 | ||
5efb3e28 VS |
9368 | I915_WRITE(CURPOS(pipe), pos); |
9369 | ||
4398ad45 VS |
9370 | /* ILK+ do this automagically */ |
9371 | if (HAS_GMCH_DISPLAY(dev) && | |
8e7d688b | 9372 | crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) { |
3dd512fb MR |
9373 | base += (intel_crtc->base.cursor->state->crtc_h * |
9374 | intel_crtc->base.cursor->state->crtc_w - 1) * 4; | |
4398ad45 VS |
9375 | } |
9376 | ||
8ac54669 | 9377 | if (IS_845G(dev) || IS_I865G(dev)) |
5efb3e28 VS |
9378 | i845_update_cursor(crtc, base); |
9379 | else | |
9380 | i9xx_update_cursor(crtc, base); | |
cda4b7d3 CW |
9381 | } |
9382 | ||
dc41c154 VS |
9383 | static bool cursor_size_ok(struct drm_device *dev, |
9384 | uint32_t width, uint32_t height) | |
9385 | { | |
9386 | if (width == 0 || height == 0) | |
9387 | return false; | |
9388 | ||
9389 | /* | |
9390 | * 845g/865g are special in that they are only limited by | |
9391 | * the width of their cursors, the height is arbitrary up to | |
9392 | * the precision of the register. Everything else requires | |
9393 | * square cursors, limited to a few power-of-two sizes. | |
9394 | */ | |
9395 | if (IS_845G(dev) || IS_I865G(dev)) { | |
9396 | if ((width & 63) != 0) | |
9397 | return false; | |
9398 | ||
9399 | if (width > (IS_845G(dev) ? 64 : 512)) | |
9400 | return false; | |
9401 | ||
9402 | if (height > 1023) | |
9403 | return false; | |
9404 | } else { | |
9405 | switch (width | height) { | |
9406 | case 256: | |
9407 | case 128: | |
9408 | if (IS_GEN2(dev)) | |
9409 | return false; | |
9410 | case 64: | |
9411 | break; | |
9412 | default: | |
9413 | return false; | |
9414 | } | |
9415 | } | |
9416 | ||
9417 | return true; | |
9418 | } | |
9419 | ||
79e53945 | 9420 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 9421 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 9422 | { |
7203425a | 9423 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 9424 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 9425 | |
7203425a | 9426 | for (i = start; i < end; i++) { |
79e53945 JB |
9427 | intel_crtc->lut_r[i] = red[i] >> 8; |
9428 | intel_crtc->lut_g[i] = green[i] >> 8; | |
9429 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
9430 | } | |
9431 | ||
9432 | intel_crtc_load_lut(crtc); | |
9433 | } | |
9434 | ||
79e53945 JB |
9435 | /* VESA 640x480x72Hz mode to set on the pipe */ |
9436 | static struct drm_display_mode load_detect_mode = { | |
9437 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
9438 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
9439 | }; | |
9440 | ||
a8bb6818 DV |
9441 | struct drm_framebuffer * |
9442 | __intel_framebuffer_create(struct drm_device *dev, | |
9443 | struct drm_mode_fb_cmd2 *mode_cmd, | |
9444 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
9445 | { |
9446 | struct intel_framebuffer *intel_fb; | |
9447 | int ret; | |
9448 | ||
9449 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
9450 | if (!intel_fb) { | |
6ccb81f2 | 9451 | drm_gem_object_unreference(&obj->base); |
d2dff872 CW |
9452 | return ERR_PTR(-ENOMEM); |
9453 | } | |
9454 | ||
9455 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
9456 | if (ret) |
9457 | goto err; | |
d2dff872 CW |
9458 | |
9459 | return &intel_fb->base; | |
dd4916c5 | 9460 | err: |
6ccb81f2 | 9461 | drm_gem_object_unreference(&obj->base); |
dd4916c5 DV |
9462 | kfree(intel_fb); |
9463 | ||
9464 | return ERR_PTR(ret); | |
d2dff872 CW |
9465 | } |
9466 | ||
b5ea642a | 9467 | static struct drm_framebuffer * |
a8bb6818 DV |
9468 | intel_framebuffer_create(struct drm_device *dev, |
9469 | struct drm_mode_fb_cmd2 *mode_cmd, | |
9470 | struct drm_i915_gem_object *obj) | |
9471 | { | |
9472 | struct drm_framebuffer *fb; | |
9473 | int ret; | |
9474 | ||
9475 | ret = i915_mutex_lock_interruptible(dev); | |
9476 | if (ret) | |
9477 | return ERR_PTR(ret); | |
9478 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
9479 | mutex_unlock(&dev->struct_mutex); | |
9480 | ||
9481 | return fb; | |
9482 | } | |
9483 | ||
d2dff872 CW |
9484 | static u32 |
9485 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
9486 | { | |
9487 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
9488 | return ALIGN(pitch, 64); | |
9489 | } | |
9490 | ||
9491 | static u32 | |
9492 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
9493 | { | |
9494 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 9495 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
9496 | } |
9497 | ||
9498 | static struct drm_framebuffer * | |
9499 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
9500 | struct drm_display_mode *mode, | |
9501 | int depth, int bpp) | |
9502 | { | |
9503 | struct drm_i915_gem_object *obj; | |
0fed39bd | 9504 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
9505 | |
9506 | obj = i915_gem_alloc_object(dev, | |
9507 | intel_framebuffer_size_for_mode(mode, bpp)); | |
9508 | if (obj == NULL) | |
9509 | return ERR_PTR(-ENOMEM); | |
9510 | ||
9511 | mode_cmd.width = mode->hdisplay; | |
9512 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
9513 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
9514 | bpp); | |
5ca0c34a | 9515 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
9516 | |
9517 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
9518 | } | |
9519 | ||
9520 | static struct drm_framebuffer * | |
9521 | mode_fits_in_fbdev(struct drm_device *dev, | |
9522 | struct drm_display_mode *mode) | |
9523 | { | |
4520f53a | 9524 | #ifdef CONFIG_DRM_I915_FBDEV |
d2dff872 CW |
9525 | struct drm_i915_private *dev_priv = dev->dev_private; |
9526 | struct drm_i915_gem_object *obj; | |
9527 | struct drm_framebuffer *fb; | |
9528 | ||
4c0e5528 | 9529 | if (!dev_priv->fbdev) |
d2dff872 CW |
9530 | return NULL; |
9531 | ||
4c0e5528 | 9532 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
9533 | return NULL; |
9534 | ||
4c0e5528 DV |
9535 | obj = dev_priv->fbdev->fb->obj; |
9536 | BUG_ON(!obj); | |
9537 | ||
8bcd4553 | 9538 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
9539 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
9540 | fb->bits_per_pixel)) | |
d2dff872 CW |
9541 | return NULL; |
9542 | ||
01f2c773 | 9543 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
9544 | return NULL; |
9545 | ||
9546 | return fb; | |
4520f53a DV |
9547 | #else |
9548 | return NULL; | |
9549 | #endif | |
d2dff872 CW |
9550 | } |
9551 | ||
d2434ab7 | 9552 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 9553 | struct drm_display_mode *mode, |
51fd371b RC |
9554 | struct intel_load_detect_pipe *old, |
9555 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
9556 | { |
9557 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
9558 | struct intel_encoder *intel_encoder = |
9559 | intel_attached_encoder(connector); | |
79e53945 | 9560 | struct drm_crtc *possible_crtc; |
4ef69c7a | 9561 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
9562 | struct drm_crtc *crtc = NULL; |
9563 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 9564 | struct drm_framebuffer *fb; |
51fd371b | 9565 | struct drm_mode_config *config = &dev->mode_config; |
83a57153 | 9566 | struct drm_atomic_state *state = NULL; |
944b0c76 | 9567 | struct drm_connector_state *connector_state; |
51fd371b | 9568 | int ret, i = -1; |
79e53945 | 9569 | |
d2dff872 | 9570 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 9571 | connector->base.id, connector->name, |
8e329a03 | 9572 | encoder->base.id, encoder->name); |
d2dff872 | 9573 | |
51fd371b RC |
9574 | retry: |
9575 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
9576 | if (ret) | |
9577 | goto fail_unlock; | |
6e9f798d | 9578 | |
79e53945 JB |
9579 | /* |
9580 | * Algorithm gets a little messy: | |
7a5e4805 | 9581 | * |
79e53945 JB |
9582 | * - if the connector already has an assigned crtc, use it (but make |
9583 | * sure it's on first) | |
7a5e4805 | 9584 | * |
79e53945 JB |
9585 | * - try to find the first unused crtc that can drive this connector, |
9586 | * and use that if we find one | |
79e53945 JB |
9587 | */ |
9588 | ||
9589 | /* See if we already have a CRTC for this connector */ | |
9590 | if (encoder->crtc) { | |
9591 | crtc = encoder->crtc; | |
8261b191 | 9592 | |
51fd371b | 9593 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de DV |
9594 | if (ret) |
9595 | goto fail_unlock; | |
9596 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); | |
51fd371b RC |
9597 | if (ret) |
9598 | goto fail_unlock; | |
7b24056b | 9599 | |
24218aac | 9600 | old->dpms_mode = connector->dpms; |
8261b191 CW |
9601 | old->load_detect_temp = false; |
9602 | ||
9603 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
9604 | if (connector->dpms != DRM_MODE_DPMS_ON) |
9605 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 9606 | |
7173188d | 9607 | return true; |
79e53945 JB |
9608 | } |
9609 | ||
9610 | /* Find an unused one (if possible) */ | |
70e1e0ec | 9611 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
9612 | i++; |
9613 | if (!(encoder->possible_crtcs & (1 << i))) | |
9614 | continue; | |
83d65738 | 9615 | if (possible_crtc->state->enable) |
a459249c VS |
9616 | continue; |
9617 | /* This can occur when applying the pipe A quirk on resume. */ | |
9618 | if (to_intel_crtc(possible_crtc)->new_enabled) | |
9619 | continue; | |
9620 | ||
9621 | crtc = possible_crtc; | |
9622 | break; | |
79e53945 JB |
9623 | } |
9624 | ||
9625 | /* | |
9626 | * If we didn't find an unused CRTC, don't use any. | |
9627 | */ | |
9628 | if (!crtc) { | |
7173188d | 9629 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
51fd371b | 9630 | goto fail_unlock; |
79e53945 JB |
9631 | } |
9632 | ||
51fd371b RC |
9633 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
9634 | if (ret) | |
4d02e2de DV |
9635 | goto fail_unlock; |
9636 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); | |
9637 | if (ret) | |
51fd371b | 9638 | goto fail_unlock; |
fc303101 DV |
9639 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
9640 | to_intel_connector(connector)->new_encoder = intel_encoder; | |
79e53945 JB |
9641 | |
9642 | intel_crtc = to_intel_crtc(crtc); | |
412b61d8 | 9643 | intel_crtc->new_enabled = true; |
24218aac | 9644 | old->dpms_mode = connector->dpms; |
8261b191 | 9645 | old->load_detect_temp = true; |
d2dff872 | 9646 | old->release_fb = NULL; |
79e53945 | 9647 | |
83a57153 ACO |
9648 | state = drm_atomic_state_alloc(dev); |
9649 | if (!state) | |
9650 | return false; | |
9651 | ||
9652 | state->acquire_ctx = ctx; | |
9653 | ||
944b0c76 ACO |
9654 | connector_state = drm_atomic_get_connector_state(state, connector); |
9655 | if (IS_ERR(connector_state)) { | |
9656 | ret = PTR_ERR(connector_state); | |
9657 | goto fail; | |
9658 | } | |
9659 | ||
9660 | connector_state->crtc = crtc; | |
9661 | connector_state->best_encoder = &intel_encoder->base; | |
9662 | ||
6492711d CW |
9663 | if (!mode) |
9664 | mode = &load_detect_mode; | |
79e53945 | 9665 | |
d2dff872 CW |
9666 | /* We need a framebuffer large enough to accommodate all accesses |
9667 | * that the plane may generate whilst we perform load detection. | |
9668 | * We can not rely on the fbcon either being present (we get called | |
9669 | * during its initialisation to detect all boot displays, or it may | |
9670 | * not even exist) or that it is large enough to satisfy the | |
9671 | * requested mode. | |
9672 | */ | |
94352cf9 DV |
9673 | fb = mode_fits_in_fbdev(dev, mode); |
9674 | if (fb == NULL) { | |
d2dff872 | 9675 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
9676 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
9677 | old->release_fb = fb; | |
d2dff872 CW |
9678 | } else |
9679 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 9680 | if (IS_ERR(fb)) { |
d2dff872 | 9681 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 9682 | goto fail; |
79e53945 | 9683 | } |
79e53945 | 9684 | |
83a57153 | 9685 | if (intel_set_mode(crtc, mode, 0, 0, fb, state)) { |
6492711d | 9686 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
9687 | if (old->release_fb) |
9688 | old->release_fb->funcs->destroy(old->release_fb); | |
412b61d8 | 9689 | goto fail; |
79e53945 | 9690 | } |
9128b040 | 9691 | crtc->primary->crtc = crtc; |
7173188d | 9692 | |
79e53945 | 9693 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 9694 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 9695 | return true; |
412b61d8 VS |
9696 | |
9697 | fail: | |
83d65738 | 9698 | intel_crtc->new_enabled = crtc->state->enable; |
51fd371b | 9699 | fail_unlock: |
83a57153 ACO |
9700 | if (state) { |
9701 | drm_atomic_state_free(state); | |
9702 | state = NULL; | |
9703 | } | |
9704 | ||
51fd371b RC |
9705 | if (ret == -EDEADLK) { |
9706 | drm_modeset_backoff(ctx); | |
9707 | goto retry; | |
9708 | } | |
9709 | ||
412b61d8 | 9710 | return false; |
79e53945 JB |
9711 | } |
9712 | ||
d2434ab7 | 9713 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
9714 | struct intel_load_detect_pipe *old, |
9715 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 9716 | { |
83a57153 | 9717 | struct drm_device *dev = connector->dev; |
d2434ab7 DV |
9718 | struct intel_encoder *intel_encoder = |
9719 | intel_attached_encoder(connector); | |
4ef69c7a | 9720 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 9721 | struct drm_crtc *crtc = encoder->crtc; |
412b61d8 | 9722 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
83a57153 | 9723 | struct drm_atomic_state *state; |
944b0c76 | 9724 | struct drm_connector_state *connector_state; |
79e53945 | 9725 | |
d2dff872 | 9726 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 9727 | connector->base.id, connector->name, |
8e329a03 | 9728 | encoder->base.id, encoder->name); |
d2dff872 | 9729 | |
8261b191 | 9730 | if (old->load_detect_temp) { |
83a57153 | 9731 | state = drm_atomic_state_alloc(dev); |
944b0c76 ACO |
9732 | if (!state) |
9733 | goto fail; | |
83a57153 ACO |
9734 | |
9735 | state->acquire_ctx = ctx; | |
9736 | ||
944b0c76 ACO |
9737 | connector_state = drm_atomic_get_connector_state(state, connector); |
9738 | if (IS_ERR(connector_state)) | |
9739 | goto fail; | |
9740 | ||
fc303101 DV |
9741 | to_intel_connector(connector)->new_encoder = NULL; |
9742 | intel_encoder->new_crtc = NULL; | |
412b61d8 | 9743 | intel_crtc->new_enabled = false; |
944b0c76 ACO |
9744 | |
9745 | connector_state->best_encoder = NULL; | |
9746 | connector_state->crtc = NULL; | |
9747 | ||
83a57153 ACO |
9748 | intel_set_mode(crtc, NULL, 0, 0, NULL, state); |
9749 | ||
9750 | drm_atomic_state_free(state); | |
d2dff872 | 9751 | |
36206361 DV |
9752 | if (old->release_fb) { |
9753 | drm_framebuffer_unregister_private(old->release_fb); | |
9754 | drm_framebuffer_unreference(old->release_fb); | |
9755 | } | |
d2dff872 | 9756 | |
0622a53c | 9757 | return; |
79e53945 JB |
9758 | } |
9759 | ||
c751ce4f | 9760 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
9761 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
9762 | connector->funcs->dpms(connector, old->dpms_mode); | |
944b0c76 ACO |
9763 | |
9764 | return; | |
9765 | fail: | |
9766 | DRM_DEBUG_KMS("Couldn't release load detect pipe.\n"); | |
9767 | drm_atomic_state_free(state); | |
79e53945 JB |
9768 | } |
9769 | ||
da4a1efa | 9770 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 9771 | const struct intel_crtc_state *pipe_config) |
da4a1efa VS |
9772 | { |
9773 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9774 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
9775 | ||
9776 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 9777 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
9778 | else if (HAS_PCH_SPLIT(dev)) |
9779 | return 120000; | |
9780 | else if (!IS_GEN2(dev)) | |
9781 | return 96000; | |
9782 | else | |
9783 | return 48000; | |
9784 | } | |
9785 | ||
79e53945 | 9786 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 9787 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 9788 | struct intel_crtc_state *pipe_config) |
79e53945 | 9789 | { |
f1f644dc | 9790 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 9791 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 9792 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 9793 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
9794 | u32 fp; |
9795 | intel_clock_t clock; | |
da4a1efa | 9796 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
9797 | |
9798 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 9799 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 9800 | else |
293623f7 | 9801 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
9802 | |
9803 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
9804 | if (IS_PINEVIEW(dev)) { |
9805 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
9806 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
9807 | } else { |
9808 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
9809 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
9810 | } | |
9811 | ||
a6c45cf0 | 9812 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
9813 | if (IS_PINEVIEW(dev)) |
9814 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
9815 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
9816 | else |
9817 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
9818 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
9819 | ||
9820 | switch (dpll & DPLL_MODE_MASK) { | |
9821 | case DPLLB_MODE_DAC_SERIAL: | |
9822 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
9823 | 5 : 10; | |
9824 | break; | |
9825 | case DPLLB_MODE_LVDS: | |
9826 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
9827 | 7 : 14; | |
9828 | break; | |
9829 | default: | |
28c97730 | 9830 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 9831 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 9832 | return; |
79e53945 JB |
9833 | } |
9834 | ||
ac58c3f0 | 9835 | if (IS_PINEVIEW(dev)) |
da4a1efa | 9836 | pineview_clock(refclk, &clock); |
ac58c3f0 | 9837 | else |
da4a1efa | 9838 | i9xx_clock(refclk, &clock); |
79e53945 | 9839 | } else { |
0fb58223 | 9840 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 9841 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
9842 | |
9843 | if (is_lvds) { | |
9844 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
9845 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
9846 | |
9847 | if (lvds & LVDS_CLKB_POWER_UP) | |
9848 | clock.p2 = 7; | |
9849 | else | |
9850 | clock.p2 = 14; | |
79e53945 JB |
9851 | } else { |
9852 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
9853 | clock.p1 = 2; | |
9854 | else { | |
9855 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
9856 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
9857 | } | |
9858 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
9859 | clock.p2 = 4; | |
9860 | else | |
9861 | clock.p2 = 2; | |
79e53945 | 9862 | } |
da4a1efa VS |
9863 | |
9864 | i9xx_clock(refclk, &clock); | |
79e53945 JB |
9865 | } |
9866 | ||
18442d08 VS |
9867 | /* |
9868 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 9869 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
9870 | * encoder's get_config() function. |
9871 | */ | |
9872 | pipe_config->port_clock = clock.dot; | |
f1f644dc JB |
9873 | } |
9874 | ||
6878da05 VS |
9875 | int intel_dotclock_calculate(int link_freq, |
9876 | const struct intel_link_m_n *m_n) | |
f1f644dc | 9877 | { |
f1f644dc JB |
9878 | /* |
9879 | * The calculation for the data clock is: | |
1041a02f | 9880 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 9881 | * But we want to avoid losing precison if possible, so: |
1041a02f | 9882 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
9883 | * |
9884 | * and the link clock is simpler: | |
1041a02f | 9885 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
9886 | */ |
9887 | ||
6878da05 VS |
9888 | if (!m_n->link_n) |
9889 | return 0; | |
f1f644dc | 9890 | |
6878da05 VS |
9891 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
9892 | } | |
f1f644dc | 9893 | |
18442d08 | 9894 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 9895 | struct intel_crtc_state *pipe_config) |
6878da05 VS |
9896 | { |
9897 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 9898 | |
18442d08 VS |
9899 | /* read out port_clock from the DPLL */ |
9900 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 9901 | |
f1f644dc | 9902 | /* |
18442d08 | 9903 | * This value does not include pixel_multiplier. |
241bfc38 | 9904 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
9905 | * agree once we know their relationship in the encoder's |
9906 | * get_config() function. | |
79e53945 | 9907 | */ |
2d112de7 | 9908 | pipe_config->base.adjusted_mode.crtc_clock = |
18442d08 VS |
9909 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
9910 | &pipe_config->fdi_m_n); | |
79e53945 JB |
9911 | } |
9912 | ||
9913 | /** Returns the currently programmed mode of the given pipe. */ | |
9914 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
9915 | struct drm_crtc *crtc) | |
9916 | { | |
548f245b | 9917 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 9918 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 9919 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 9920 | struct drm_display_mode *mode; |
5cec258b | 9921 | struct intel_crtc_state pipe_config; |
fe2b8f9d PZ |
9922 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
9923 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
9924 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
9925 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 9926 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
9927 | |
9928 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
9929 | if (!mode) | |
9930 | return NULL; | |
9931 | ||
f1f644dc JB |
9932 | /* |
9933 | * Construct a pipe_config sufficient for getting the clock info | |
9934 | * back out of crtc_clock_get. | |
9935 | * | |
9936 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
9937 | * to use a real value here instead. | |
9938 | */ | |
293623f7 | 9939 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
f1f644dc | 9940 | pipe_config.pixel_multiplier = 1; |
293623f7 VS |
9941 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
9942 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
9943 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
f1f644dc JB |
9944 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
9945 | ||
773ae034 | 9946 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
79e53945 JB |
9947 | mode->hdisplay = (htot & 0xffff) + 1; |
9948 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
9949 | mode->hsync_start = (hsync & 0xffff) + 1; | |
9950 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
9951 | mode->vdisplay = (vtot & 0xffff) + 1; | |
9952 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
9953 | mode->vsync_start = (vsync & 0xffff) + 1; | |
9954 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
9955 | ||
9956 | drm_mode_set_name(mode); | |
79e53945 JB |
9957 | |
9958 | return mode; | |
9959 | } | |
9960 | ||
652c393a JB |
9961 | static void intel_decrease_pllclock(struct drm_crtc *crtc) |
9962 | { | |
9963 | struct drm_device *dev = crtc->dev; | |
fbee40df | 9964 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 9965 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
652c393a | 9966 | |
baff296c | 9967 | if (!HAS_GMCH_DISPLAY(dev)) |
652c393a JB |
9968 | return; |
9969 | ||
9970 | if (!dev_priv->lvds_downclock_avail) | |
9971 | return; | |
9972 | ||
9973 | /* | |
9974 | * Since this is called by a timer, we should never get here in | |
9975 | * the manual case. | |
9976 | */ | |
9977 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
dc257cf1 DV |
9978 | int pipe = intel_crtc->pipe; |
9979 | int dpll_reg = DPLL(pipe); | |
9980 | int dpll; | |
f6e5b160 | 9981 | |
44d98a61 | 9982 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a | 9983 | |
8ac5a6d5 | 9984 | assert_panel_unlocked(dev_priv, pipe); |
652c393a | 9985 | |
dc257cf1 | 9986 | dpll = I915_READ(dpll_reg); |
652c393a JB |
9987 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
9988 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 9989 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
9990 | dpll = I915_READ(dpll_reg); |
9991 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 9992 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
9993 | } |
9994 | ||
9995 | } | |
9996 | ||
f047e395 CW |
9997 | void intel_mark_busy(struct drm_device *dev) |
9998 | { | |
c67a470b PZ |
9999 | struct drm_i915_private *dev_priv = dev->dev_private; |
10000 | ||
f62a0076 CW |
10001 | if (dev_priv->mm.busy) |
10002 | return; | |
10003 | ||
43694d69 | 10004 | intel_runtime_pm_get(dev_priv); |
c67a470b | 10005 | i915_update_gfx_val(dev_priv); |
43cf3bf0 CW |
10006 | if (INTEL_INFO(dev)->gen >= 6) |
10007 | gen6_rps_busy(dev_priv); | |
f62a0076 | 10008 | dev_priv->mm.busy = true; |
f047e395 CW |
10009 | } |
10010 | ||
10011 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 10012 | { |
c67a470b | 10013 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 10014 | struct drm_crtc *crtc; |
652c393a | 10015 | |
f62a0076 CW |
10016 | if (!dev_priv->mm.busy) |
10017 | return; | |
10018 | ||
10019 | dev_priv->mm.busy = false; | |
10020 | ||
70e1e0ec | 10021 | for_each_crtc(dev, crtc) { |
f4510a27 | 10022 | if (!crtc->primary->fb) |
652c393a JB |
10023 | continue; |
10024 | ||
725a5b54 | 10025 | intel_decrease_pllclock(crtc); |
652c393a | 10026 | } |
b29c19b6 | 10027 | |
3d13ef2e | 10028 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 10029 | gen6_rps_idle(dev->dev_private); |
bb4cdd53 | 10030 | |
43694d69 | 10031 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
10032 | } |
10033 | ||
f5de6e07 ACO |
10034 | static void intel_crtc_set_state(struct intel_crtc *crtc, |
10035 | struct intel_crtc_state *crtc_state) | |
10036 | { | |
10037 | kfree(crtc->config); | |
10038 | crtc->config = crtc_state; | |
16f3f658 | 10039 | crtc->base.state = &crtc_state->base; |
f5de6e07 ACO |
10040 | } |
10041 | ||
79e53945 JB |
10042 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
10043 | { | |
10044 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
10045 | struct drm_device *dev = crtc->dev; |
10046 | struct intel_unpin_work *work; | |
67e77c5a | 10047 | |
5e2d7afc | 10048 | spin_lock_irq(&dev->event_lock); |
67e77c5a DV |
10049 | work = intel_crtc->unpin_work; |
10050 | intel_crtc->unpin_work = NULL; | |
5e2d7afc | 10051 | spin_unlock_irq(&dev->event_lock); |
67e77c5a DV |
10052 | |
10053 | if (work) { | |
10054 | cancel_work_sync(&work->work); | |
10055 | kfree(work); | |
10056 | } | |
79e53945 | 10057 | |
f5de6e07 | 10058 | intel_crtc_set_state(intel_crtc, NULL); |
79e53945 | 10059 | drm_crtc_cleanup(crtc); |
67e77c5a | 10060 | |
79e53945 JB |
10061 | kfree(intel_crtc); |
10062 | } | |
10063 | ||
6b95a207 KH |
10064 | static void intel_unpin_work_fn(struct work_struct *__work) |
10065 | { | |
10066 | struct intel_unpin_work *work = | |
10067 | container_of(__work, struct intel_unpin_work, work); | |
b4a98e57 | 10068 | struct drm_device *dev = work->crtc->dev; |
f99d7069 | 10069 | enum pipe pipe = to_intel_crtc(work->crtc)->pipe; |
6b95a207 | 10070 | |
b4a98e57 | 10071 | mutex_lock(&dev->struct_mutex); |
82bc3b2d | 10072 | intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state); |
05394f39 | 10073 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
d9e86c0e | 10074 | |
7ff0ebcc | 10075 | intel_fbc_update(dev); |
f06cc1b9 JH |
10076 | |
10077 | if (work->flip_queued_req) | |
146d84f0 | 10078 | i915_gem_request_assign(&work->flip_queued_req, NULL); |
b4a98e57 CW |
10079 | mutex_unlock(&dev->struct_mutex); |
10080 | ||
f99d7069 | 10081 | intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
89ed88ba | 10082 | drm_framebuffer_unreference(work->old_fb); |
f99d7069 | 10083 | |
b4a98e57 CW |
10084 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); |
10085 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); | |
10086 | ||
6b95a207 KH |
10087 | kfree(work); |
10088 | } | |
10089 | ||
1afe3e9d | 10090 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 10091 | struct drm_crtc *crtc) |
6b95a207 | 10092 | { |
6b95a207 KH |
10093 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10094 | struct intel_unpin_work *work; | |
6b95a207 KH |
10095 | unsigned long flags; |
10096 | ||
10097 | /* Ignore early vblank irqs */ | |
10098 | if (intel_crtc == NULL) | |
10099 | return; | |
10100 | ||
f326038a DV |
10101 | /* |
10102 | * This is called both by irq handlers and the reset code (to complete | |
10103 | * lost pageflips) so needs the full irqsave spinlocks. | |
10104 | */ | |
6b95a207 KH |
10105 | spin_lock_irqsave(&dev->event_lock, flags); |
10106 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
10107 | |
10108 | /* Ensure we don't miss a work->pending update ... */ | |
10109 | smp_rmb(); | |
10110 | ||
10111 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
10112 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10113 | return; | |
10114 | } | |
10115 | ||
d6bbafa1 | 10116 | page_flip_completed(intel_crtc); |
0af7e4df | 10117 | |
6b95a207 | 10118 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6b95a207 KH |
10119 | } |
10120 | ||
1afe3e9d JB |
10121 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
10122 | { | |
fbee40df | 10123 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10124 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
10125 | ||
49b14a5c | 10126 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10127 | } |
10128 | ||
10129 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
10130 | { | |
fbee40df | 10131 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10132 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
10133 | ||
49b14a5c | 10134 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10135 | } |
10136 | ||
75f7f3ec VS |
10137 | /* Is 'a' after or equal to 'b'? */ |
10138 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
10139 | { | |
10140 | return !((a - b) & 0x80000000); | |
10141 | } | |
10142 | ||
10143 | static bool page_flip_finished(struct intel_crtc *crtc) | |
10144 | { | |
10145 | struct drm_device *dev = crtc->base.dev; | |
10146 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10147 | ||
bdfa7542 VS |
10148 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
10149 | crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
10150 | return true; | |
10151 | ||
75f7f3ec VS |
10152 | /* |
10153 | * The relevant registers doen't exist on pre-ctg. | |
10154 | * As the flip done interrupt doesn't trigger for mmio | |
10155 | * flips on gmch platforms, a flip count check isn't | |
10156 | * really needed there. But since ctg has the registers, | |
10157 | * include it in the check anyway. | |
10158 | */ | |
10159 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
10160 | return true; | |
10161 | ||
10162 | /* | |
10163 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
10164 | * used the same base address. In that case the mmio flip might | |
10165 | * have completed, but the CS hasn't even executed the flip yet. | |
10166 | * | |
10167 | * A flip count check isn't enough as the CS might have updated | |
10168 | * the base address just after start of vblank, but before we | |
10169 | * managed to process the interrupt. This means we'd complete the | |
10170 | * CS flip too soon. | |
10171 | * | |
10172 | * Combining both checks should get us a good enough result. It may | |
10173 | * still happen that the CS flip has been executed, but has not | |
10174 | * yet actually completed. But in case the base address is the same | |
10175 | * anyway, we don't really care. | |
10176 | */ | |
10177 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
10178 | crtc->unpin_work->gtt_offset && | |
10179 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)), | |
10180 | crtc->unpin_work->flip_count); | |
10181 | } | |
10182 | ||
6b95a207 KH |
10183 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
10184 | { | |
fbee40df | 10185 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
10186 | struct intel_crtc *intel_crtc = |
10187 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
10188 | unsigned long flags; | |
10189 | ||
f326038a DV |
10190 | |
10191 | /* | |
10192 | * This is called both by irq handlers and the reset code (to complete | |
10193 | * lost pageflips) so needs the full irqsave spinlocks. | |
10194 | * | |
10195 | * NB: An MMIO update of the plane base pointer will also | |
e7d841ca CW |
10196 | * generate a page-flip completion irq, i.e. every modeset |
10197 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
10198 | */ | |
6b95a207 | 10199 | spin_lock_irqsave(&dev->event_lock, flags); |
75f7f3ec | 10200 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
e7d841ca | 10201 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
6b95a207 KH |
10202 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10203 | } | |
10204 | ||
eba905b2 | 10205 | static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
e7d841ca CW |
10206 | { |
10207 | /* Ensure that the work item is consistent when activating it ... */ | |
10208 | smp_wmb(); | |
10209 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); | |
10210 | /* and that it is marked active as soon as the irq could fire. */ | |
10211 | smp_wmb(); | |
10212 | } | |
10213 | ||
8c9f3aaf JB |
10214 | static int intel_gen2_queue_flip(struct drm_device *dev, |
10215 | struct drm_crtc *crtc, | |
10216 | struct drm_framebuffer *fb, | |
ed8d1975 | 10217 | struct drm_i915_gem_object *obj, |
a4872ba6 | 10218 | struct intel_engine_cs *ring, |
ed8d1975 | 10219 | uint32_t flags) |
8c9f3aaf | 10220 | { |
8c9f3aaf | 10221 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
10222 | u32 flip_mask; |
10223 | int ret; | |
10224 | ||
6d90c952 | 10225 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 10226 | if (ret) |
4fa62c89 | 10227 | return ret; |
8c9f3aaf JB |
10228 | |
10229 | /* Can't queue multiple flips, so wait for the previous | |
10230 | * one to finish before executing the next. | |
10231 | */ | |
10232 | if (intel_crtc->plane) | |
10233 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
10234 | else | |
10235 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
10236 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
10237 | intel_ring_emit(ring, MI_NOOP); | |
10238 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
10239 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
10240 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 10241 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 | 10242 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca CW |
10243 | |
10244 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 10245 | __intel_ring_advance(ring); |
83d4092b | 10246 | return 0; |
8c9f3aaf JB |
10247 | } |
10248 | ||
10249 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
10250 | struct drm_crtc *crtc, | |
10251 | struct drm_framebuffer *fb, | |
ed8d1975 | 10252 | struct drm_i915_gem_object *obj, |
a4872ba6 | 10253 | struct intel_engine_cs *ring, |
ed8d1975 | 10254 | uint32_t flags) |
8c9f3aaf | 10255 | { |
8c9f3aaf | 10256 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
10257 | u32 flip_mask; |
10258 | int ret; | |
10259 | ||
6d90c952 | 10260 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 10261 | if (ret) |
4fa62c89 | 10262 | return ret; |
8c9f3aaf JB |
10263 | |
10264 | if (intel_crtc->plane) | |
10265 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
10266 | else | |
10267 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
10268 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
10269 | intel_ring_emit(ring, MI_NOOP); | |
10270 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
10271 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
10272 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 10273 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 DV |
10274 | intel_ring_emit(ring, MI_NOOP); |
10275 | ||
e7d841ca | 10276 | intel_mark_page_flip_active(intel_crtc); |
09246732 | 10277 | __intel_ring_advance(ring); |
83d4092b | 10278 | return 0; |
8c9f3aaf JB |
10279 | } |
10280 | ||
10281 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
10282 | struct drm_crtc *crtc, | |
10283 | struct drm_framebuffer *fb, | |
ed8d1975 | 10284 | struct drm_i915_gem_object *obj, |
a4872ba6 | 10285 | struct intel_engine_cs *ring, |
ed8d1975 | 10286 | uint32_t flags) |
8c9f3aaf JB |
10287 | { |
10288 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10289 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10290 | uint32_t pf, pipesrc; | |
10291 | int ret; | |
10292 | ||
6d90c952 | 10293 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 10294 | if (ret) |
4fa62c89 | 10295 | return ret; |
8c9f3aaf JB |
10296 | |
10297 | /* i965+ uses the linear or tiled offsets from the | |
10298 | * Display Registers (which do not change across a page-flip) | |
10299 | * so we need only reprogram the base address. | |
10300 | */ | |
6d90c952 DV |
10301 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
10302 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
10303 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 10304 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | |
c2c75131 | 10305 | obj->tiling_mode); |
8c9f3aaf JB |
10306 | |
10307 | /* XXX Enabling the panel-fitter across page-flip is so far | |
10308 | * untested on non-native modes, so ignore it for now. | |
10309 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
10310 | */ | |
10311 | pf = 0; | |
10312 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 10313 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
10314 | |
10315 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 10316 | __intel_ring_advance(ring); |
83d4092b | 10317 | return 0; |
8c9f3aaf JB |
10318 | } |
10319 | ||
10320 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
10321 | struct drm_crtc *crtc, | |
10322 | struct drm_framebuffer *fb, | |
ed8d1975 | 10323 | struct drm_i915_gem_object *obj, |
a4872ba6 | 10324 | struct intel_engine_cs *ring, |
ed8d1975 | 10325 | uint32_t flags) |
8c9f3aaf JB |
10326 | { |
10327 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10328 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10329 | uint32_t pf, pipesrc; | |
10330 | int ret; | |
10331 | ||
6d90c952 | 10332 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 10333 | if (ret) |
4fa62c89 | 10334 | return ret; |
8c9f3aaf | 10335 | |
6d90c952 DV |
10336 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
10337 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
10338 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
75f7f3ec | 10339 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
8c9f3aaf | 10340 | |
dc257cf1 DV |
10341 | /* Contrary to the suggestions in the documentation, |
10342 | * "Enable Panel Fitter" does not seem to be required when page | |
10343 | * flipping with a non-native mode, and worse causes a normal | |
10344 | * modeset to fail. | |
10345 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
10346 | */ | |
10347 | pf = 0; | |
8c9f3aaf | 10348 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 10349 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
10350 | |
10351 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 10352 | __intel_ring_advance(ring); |
83d4092b | 10353 | return 0; |
8c9f3aaf JB |
10354 | } |
10355 | ||
7c9017e5 JB |
10356 | static int intel_gen7_queue_flip(struct drm_device *dev, |
10357 | struct drm_crtc *crtc, | |
10358 | struct drm_framebuffer *fb, | |
ed8d1975 | 10359 | struct drm_i915_gem_object *obj, |
a4872ba6 | 10360 | struct intel_engine_cs *ring, |
ed8d1975 | 10361 | uint32_t flags) |
7c9017e5 | 10362 | { |
7c9017e5 | 10363 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cb05d8de | 10364 | uint32_t plane_bit = 0; |
ffe74d75 CW |
10365 | int len, ret; |
10366 | ||
eba905b2 | 10367 | switch (intel_crtc->plane) { |
cb05d8de DV |
10368 | case PLANE_A: |
10369 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
10370 | break; | |
10371 | case PLANE_B: | |
10372 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
10373 | break; | |
10374 | case PLANE_C: | |
10375 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
10376 | break; | |
10377 | default: | |
10378 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
4fa62c89 | 10379 | return -ENODEV; |
cb05d8de DV |
10380 | } |
10381 | ||
ffe74d75 | 10382 | len = 4; |
f476828a | 10383 | if (ring->id == RCS) { |
ffe74d75 | 10384 | len += 6; |
f476828a DL |
10385 | /* |
10386 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
10387 | * 48bits addresses, and we need a NOOP for the batch size to | |
10388 | * stay even. | |
10389 | */ | |
10390 | if (IS_GEN8(dev)) | |
10391 | len += 2; | |
10392 | } | |
ffe74d75 | 10393 | |
f66fab8e VS |
10394 | /* |
10395 | * BSpec MI_DISPLAY_FLIP for IVB: | |
10396 | * "The full packet must be contained within the same cache line." | |
10397 | * | |
10398 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
10399 | * cacheline, if we ever start emitting more commands before | |
10400 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
10401 | * then do the cacheline alignment, and finally emit the | |
10402 | * MI_DISPLAY_FLIP. | |
10403 | */ | |
10404 | ret = intel_ring_cacheline_align(ring); | |
10405 | if (ret) | |
4fa62c89 | 10406 | return ret; |
f66fab8e | 10407 | |
ffe74d75 | 10408 | ret = intel_ring_begin(ring, len); |
7c9017e5 | 10409 | if (ret) |
4fa62c89 | 10410 | return ret; |
7c9017e5 | 10411 | |
ffe74d75 CW |
10412 | /* Unmask the flip-done completion message. Note that the bspec says that |
10413 | * we should do this for both the BCS and RCS, and that we must not unmask | |
10414 | * more than one flip event at any time (or ensure that one flip message | |
10415 | * can be sent by waiting for flip-done prior to queueing new flips). | |
10416 | * Experimentation says that BCS works despite DERRMR masking all | |
10417 | * flip-done completion events and that unmasking all planes at once | |
10418 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
10419 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
10420 | */ | |
10421 | if (ring->id == RCS) { | |
10422 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
10423 | intel_ring_emit(ring, DERRMR); | |
10424 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
10425 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
10426 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
f476828a DL |
10427 | if (IS_GEN8(dev)) |
10428 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) | | |
10429 | MI_SRM_LRM_GLOBAL_GTT); | |
10430 | else | |
10431 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | | |
10432 | MI_SRM_LRM_GLOBAL_GTT); | |
ffe74d75 CW |
10433 | intel_ring_emit(ring, DERRMR); |
10434 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
f476828a DL |
10435 | if (IS_GEN8(dev)) { |
10436 | intel_ring_emit(ring, 0); | |
10437 | intel_ring_emit(ring, MI_NOOP); | |
10438 | } | |
ffe74d75 CW |
10439 | } |
10440 | ||
cb05d8de | 10441 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 10442 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
75f7f3ec | 10443 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
7c9017e5 | 10444 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca CW |
10445 | |
10446 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 10447 | __intel_ring_advance(ring); |
83d4092b | 10448 | return 0; |
7c9017e5 JB |
10449 | } |
10450 | ||
84c33a64 SG |
10451 | static bool use_mmio_flip(struct intel_engine_cs *ring, |
10452 | struct drm_i915_gem_object *obj) | |
10453 | { | |
10454 | /* | |
10455 | * This is not being used for older platforms, because | |
10456 | * non-availability of flip done interrupt forces us to use | |
10457 | * CS flips. Older platforms derive flip done using some clever | |
10458 | * tricks involving the flip_pending status bits and vblank irqs. | |
10459 | * So using MMIO flips there would disrupt this mechanism. | |
10460 | */ | |
10461 | ||
8e09bf83 CW |
10462 | if (ring == NULL) |
10463 | return true; | |
10464 | ||
84c33a64 SG |
10465 | if (INTEL_INFO(ring->dev)->gen < 5) |
10466 | return false; | |
10467 | ||
10468 | if (i915.use_mmio_flip < 0) | |
10469 | return false; | |
10470 | else if (i915.use_mmio_flip > 0) | |
10471 | return true; | |
14bf993e OM |
10472 | else if (i915.enable_execlists) |
10473 | return true; | |
84c33a64 | 10474 | else |
41c52415 | 10475 | return ring != i915_gem_request_get_ring(obj->last_read_req); |
84c33a64 SG |
10476 | } |
10477 | ||
ff944564 DL |
10478 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc) |
10479 | { | |
10480 | struct drm_device *dev = intel_crtc->base.dev; | |
10481 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10482 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; | |
10483 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
10484 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
10485 | const enum pipe pipe = intel_crtc->pipe; | |
10486 | u32 ctl, stride; | |
10487 | ||
10488 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
10489 | ctl &= ~PLANE_CTL_TILED_MASK; | |
10490 | if (obj->tiling_mode == I915_TILING_X) | |
10491 | ctl |= PLANE_CTL_TILED_X; | |
10492 | ||
10493 | /* | |
10494 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
10495 | * linear buffers or in number of tiles for tiled buffers. | |
10496 | */ | |
10497 | stride = fb->pitches[0] >> 6; | |
10498 | if (obj->tiling_mode == I915_TILING_X) | |
10499 | stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */ | |
10500 | ||
10501 | /* | |
10502 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
10503 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
10504 | */ | |
10505 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
10506 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
10507 | ||
10508 | I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset); | |
10509 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
10510 | } | |
10511 | ||
10512 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc) | |
84c33a64 SG |
10513 | { |
10514 | struct drm_device *dev = intel_crtc->base.dev; | |
10515 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10516 | struct intel_framebuffer *intel_fb = | |
10517 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
10518 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
10519 | u32 dspcntr; | |
10520 | u32 reg; | |
10521 | ||
84c33a64 SG |
10522 | reg = DSPCNTR(intel_crtc->plane); |
10523 | dspcntr = I915_READ(reg); | |
10524 | ||
c5d97472 DL |
10525 | if (obj->tiling_mode != I915_TILING_NONE) |
10526 | dspcntr |= DISPPLANE_TILED; | |
10527 | else | |
10528 | dspcntr &= ~DISPPLANE_TILED; | |
10529 | ||
84c33a64 SG |
10530 | I915_WRITE(reg, dspcntr); |
10531 | ||
10532 | I915_WRITE(DSPSURF(intel_crtc->plane), | |
10533 | intel_crtc->unpin_work->gtt_offset); | |
10534 | POSTING_READ(DSPSURF(intel_crtc->plane)); | |
84c33a64 | 10535 | |
ff944564 DL |
10536 | } |
10537 | ||
10538 | /* | |
10539 | * XXX: This is the temporary way to update the plane registers until we get | |
10540 | * around to using the usual plane update functions for MMIO flips | |
10541 | */ | |
10542 | static void intel_do_mmio_flip(struct intel_crtc *intel_crtc) | |
10543 | { | |
10544 | struct drm_device *dev = intel_crtc->base.dev; | |
10545 | bool atomic_update; | |
10546 | u32 start_vbl_count; | |
10547 | ||
10548 | intel_mark_page_flip_active(intel_crtc); | |
10549 | ||
10550 | atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count); | |
10551 | ||
10552 | if (INTEL_INFO(dev)->gen >= 9) | |
10553 | skl_do_mmio_flip(intel_crtc); | |
10554 | else | |
10555 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
10556 | ilk_do_mmio_flip(intel_crtc); | |
10557 | ||
9362c7c5 ACO |
10558 | if (atomic_update) |
10559 | intel_pipe_update_end(intel_crtc, start_vbl_count); | |
84c33a64 SG |
10560 | } |
10561 | ||
9362c7c5 | 10562 | static void intel_mmio_flip_work_func(struct work_struct *work) |
84c33a64 | 10563 | { |
cc8c4cc2 | 10564 | struct intel_crtc *crtc = |
9362c7c5 | 10565 | container_of(work, struct intel_crtc, mmio_flip.work); |
cc8c4cc2 | 10566 | struct intel_mmio_flip *mmio_flip; |
84c33a64 | 10567 | |
cc8c4cc2 JH |
10568 | mmio_flip = &crtc->mmio_flip; |
10569 | if (mmio_flip->req) | |
9c654818 JH |
10570 | WARN_ON(__i915_wait_request(mmio_flip->req, |
10571 | crtc->reset_counter, | |
10572 | false, NULL, NULL) != 0); | |
84c33a64 | 10573 | |
cc8c4cc2 JH |
10574 | intel_do_mmio_flip(crtc); |
10575 | if (mmio_flip->req) { | |
10576 | mutex_lock(&crtc->base.dev->struct_mutex); | |
146d84f0 | 10577 | i915_gem_request_assign(&mmio_flip->req, NULL); |
cc8c4cc2 JH |
10578 | mutex_unlock(&crtc->base.dev->struct_mutex); |
10579 | } | |
84c33a64 SG |
10580 | } |
10581 | ||
10582 | static int intel_queue_mmio_flip(struct drm_device *dev, | |
10583 | struct drm_crtc *crtc, | |
10584 | struct drm_framebuffer *fb, | |
10585 | struct drm_i915_gem_object *obj, | |
10586 | struct intel_engine_cs *ring, | |
10587 | uint32_t flags) | |
10588 | { | |
84c33a64 | 10589 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
84c33a64 | 10590 | |
cc8c4cc2 JH |
10591 | i915_gem_request_assign(&intel_crtc->mmio_flip.req, |
10592 | obj->last_write_req); | |
536f5b5e ACO |
10593 | |
10594 | schedule_work(&intel_crtc->mmio_flip.work); | |
84c33a64 | 10595 | |
84c33a64 SG |
10596 | return 0; |
10597 | } | |
10598 | ||
8c9f3aaf JB |
10599 | static int intel_default_queue_flip(struct drm_device *dev, |
10600 | struct drm_crtc *crtc, | |
10601 | struct drm_framebuffer *fb, | |
ed8d1975 | 10602 | struct drm_i915_gem_object *obj, |
a4872ba6 | 10603 | struct intel_engine_cs *ring, |
ed8d1975 | 10604 | uint32_t flags) |
8c9f3aaf JB |
10605 | { |
10606 | return -ENODEV; | |
10607 | } | |
10608 | ||
d6bbafa1 CW |
10609 | static bool __intel_pageflip_stall_check(struct drm_device *dev, |
10610 | struct drm_crtc *crtc) | |
10611 | { | |
10612 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10613 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10614 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
10615 | u32 addr; | |
10616 | ||
10617 | if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE) | |
10618 | return true; | |
10619 | ||
10620 | if (!work->enable_stall_check) | |
10621 | return false; | |
10622 | ||
10623 | if (work->flip_ready_vblank == 0) { | |
3a8a946e DV |
10624 | if (work->flip_queued_req && |
10625 | !i915_gem_request_completed(work->flip_queued_req, true)) | |
d6bbafa1 CW |
10626 | return false; |
10627 | ||
1e3feefd | 10628 | work->flip_ready_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 CW |
10629 | } |
10630 | ||
1e3feefd | 10631 | if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3) |
d6bbafa1 CW |
10632 | return false; |
10633 | ||
10634 | /* Potential stall - if we see that the flip has happened, | |
10635 | * assume a missed interrupt. */ | |
10636 | if (INTEL_INFO(dev)->gen >= 4) | |
10637 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
10638 | else | |
10639 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
10640 | ||
10641 | /* There is a potential issue here with a false positive after a flip | |
10642 | * to the same address. We could address this by checking for a | |
10643 | * non-incrementing frame counter. | |
10644 | */ | |
10645 | return addr == work->gtt_offset; | |
10646 | } | |
10647 | ||
10648 | void intel_check_page_flip(struct drm_device *dev, int pipe) | |
10649 | { | |
10650 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10651 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
10652 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6ad790c0 | 10653 | struct intel_unpin_work *work; |
f326038a | 10654 | |
6c51d46f | 10655 | WARN_ON(!in_interrupt()); |
d6bbafa1 CW |
10656 | |
10657 | if (crtc == NULL) | |
10658 | return; | |
10659 | ||
f326038a | 10660 | spin_lock(&dev->event_lock); |
6ad790c0 CW |
10661 | work = intel_crtc->unpin_work; |
10662 | if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) { | |
d6bbafa1 | 10663 | WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n", |
6ad790c0 | 10664 | work->flip_queued_vblank, drm_vblank_count(dev, pipe)); |
d6bbafa1 | 10665 | page_flip_completed(intel_crtc); |
6ad790c0 | 10666 | work = NULL; |
d6bbafa1 | 10667 | } |
6ad790c0 CW |
10668 | if (work != NULL && |
10669 | drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1) | |
10670 | intel_queue_rps_boost_for_request(dev, work->flip_queued_req); | |
f326038a | 10671 | spin_unlock(&dev->event_lock); |
d6bbafa1 CW |
10672 | } |
10673 | ||
6b95a207 KH |
10674 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
10675 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
10676 | struct drm_pending_vblank_event *event, |
10677 | uint32_t page_flip_flags) | |
6b95a207 KH |
10678 | { |
10679 | struct drm_device *dev = crtc->dev; | |
10680 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 10681 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
2ff8fde1 | 10682 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
6b95a207 | 10683 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
455a6808 | 10684 | struct drm_plane *primary = crtc->primary; |
a071fa00 | 10685 | enum pipe pipe = intel_crtc->pipe; |
6b95a207 | 10686 | struct intel_unpin_work *work; |
a4872ba6 | 10687 | struct intel_engine_cs *ring; |
cf5d8a46 | 10688 | bool mmio_flip; |
52e68630 | 10689 | int ret; |
6b95a207 | 10690 | |
2ff8fde1 MR |
10691 | /* |
10692 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
10693 | * check to be safe. In the future we may enable pageflipping from | |
10694 | * a disabled primary plane. | |
10695 | */ | |
10696 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
10697 | return -EBUSY; | |
10698 | ||
e6a595d2 | 10699 | /* Can't change pixel format via MI display flips. */ |
f4510a27 | 10700 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
e6a595d2 VS |
10701 | return -EINVAL; |
10702 | ||
10703 | /* | |
10704 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
10705 | * Note that pitch changes could also affect these register. | |
10706 | */ | |
10707 | if (INTEL_INFO(dev)->gen > 3 && | |
f4510a27 MR |
10708 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
10709 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
e6a595d2 VS |
10710 | return -EINVAL; |
10711 | ||
f900db47 CW |
10712 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
10713 | goto out_hang; | |
10714 | ||
b14c5679 | 10715 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
10716 | if (work == NULL) |
10717 | return -ENOMEM; | |
10718 | ||
6b95a207 | 10719 | work->event = event; |
b4a98e57 | 10720 | work->crtc = crtc; |
ab8d6675 | 10721 | work->old_fb = old_fb; |
6b95a207 KH |
10722 | INIT_WORK(&work->work, intel_unpin_work_fn); |
10723 | ||
87b6b101 | 10724 | ret = drm_crtc_vblank_get(crtc); |
7317c75e JB |
10725 | if (ret) |
10726 | goto free_work; | |
10727 | ||
6b95a207 | 10728 | /* We borrow the event spin lock for protecting unpin_work */ |
5e2d7afc | 10729 | spin_lock_irq(&dev->event_lock); |
6b95a207 | 10730 | if (intel_crtc->unpin_work) { |
d6bbafa1 CW |
10731 | /* Before declaring the flip queue wedged, check if |
10732 | * the hardware completed the operation behind our backs. | |
10733 | */ | |
10734 | if (__intel_pageflip_stall_check(dev, crtc)) { | |
10735 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
10736 | page_flip_completed(intel_crtc); | |
10737 | } else { | |
10738 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
5e2d7afc | 10739 | spin_unlock_irq(&dev->event_lock); |
468f0b44 | 10740 | |
d6bbafa1 CW |
10741 | drm_crtc_vblank_put(crtc); |
10742 | kfree(work); | |
10743 | return -EBUSY; | |
10744 | } | |
6b95a207 KH |
10745 | } |
10746 | intel_crtc->unpin_work = work; | |
5e2d7afc | 10747 | spin_unlock_irq(&dev->event_lock); |
6b95a207 | 10748 | |
b4a98e57 CW |
10749 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
10750 | flush_workqueue(dev_priv->wq); | |
10751 | ||
75dfca80 | 10752 | /* Reference the objects for the scheduled work. */ |
ab8d6675 | 10753 | drm_framebuffer_reference(work->old_fb); |
05394f39 | 10754 | drm_gem_object_reference(&obj->base); |
6b95a207 | 10755 | |
f4510a27 | 10756 | crtc->primary->fb = fb; |
afd65eb4 | 10757 | update_state_fb(crtc->primary); |
1ed1f968 | 10758 | |
e1f99ce6 | 10759 | work->pending_flip_obj = obj; |
e1f99ce6 | 10760 | |
89ed88ba CW |
10761 | ret = i915_mutex_lock_interruptible(dev); |
10762 | if (ret) | |
10763 | goto cleanup; | |
10764 | ||
b4a98e57 | 10765 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 10766 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 10767 | |
75f7f3ec | 10768 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
a071fa00 | 10769 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1; |
75f7f3ec | 10770 | |
4fa62c89 VS |
10771 | if (IS_VALLEYVIEW(dev)) { |
10772 | ring = &dev_priv->ring[BCS]; | |
ab8d6675 | 10773 | if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode) |
8e09bf83 CW |
10774 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
10775 | ring = NULL; | |
48bf5b2d | 10776 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
2a92d5bc | 10777 | ring = &dev_priv->ring[BCS]; |
4fa62c89 | 10778 | } else if (INTEL_INFO(dev)->gen >= 7) { |
41c52415 | 10779 | ring = i915_gem_request_get_ring(obj->last_read_req); |
4fa62c89 VS |
10780 | if (ring == NULL || ring->id != RCS) |
10781 | ring = &dev_priv->ring[BCS]; | |
10782 | } else { | |
10783 | ring = &dev_priv->ring[RCS]; | |
10784 | } | |
10785 | ||
cf5d8a46 CW |
10786 | mmio_flip = use_mmio_flip(ring, obj); |
10787 | ||
10788 | /* When using CS flips, we want to emit semaphores between rings. | |
10789 | * However, when using mmio flips we will create a task to do the | |
10790 | * synchronisation, so all we want here is to pin the framebuffer | |
10791 | * into the display plane and skip any waits. | |
10792 | */ | |
82bc3b2d | 10793 | ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, |
cf5d8a46 CW |
10794 | crtc->primary->state, |
10795 | mmio_flip ? i915_gem_request_get_ring(obj->last_read_req) : ring); | |
8c9f3aaf JB |
10796 | if (ret) |
10797 | goto cleanup_pending; | |
6b95a207 | 10798 | |
121920fa TU |
10799 | work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj) |
10800 | + intel_crtc->dspaddr_offset; | |
4fa62c89 | 10801 | |
cf5d8a46 | 10802 | if (mmio_flip) { |
84c33a64 SG |
10803 | ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring, |
10804 | page_flip_flags); | |
d6bbafa1 CW |
10805 | if (ret) |
10806 | goto cleanup_unpin; | |
10807 | ||
f06cc1b9 JH |
10808 | i915_gem_request_assign(&work->flip_queued_req, |
10809 | obj->last_write_req); | |
d6bbafa1 | 10810 | } else { |
84c33a64 | 10811 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring, |
d6bbafa1 CW |
10812 | page_flip_flags); |
10813 | if (ret) | |
10814 | goto cleanup_unpin; | |
10815 | ||
f06cc1b9 JH |
10816 | i915_gem_request_assign(&work->flip_queued_req, |
10817 | intel_ring_get_request(ring)); | |
d6bbafa1 CW |
10818 | } |
10819 | ||
1e3feefd | 10820 | work->flip_queued_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 | 10821 | work->enable_stall_check = true; |
4fa62c89 | 10822 | |
ab8d6675 | 10823 | i915_gem_track_fb(intel_fb_obj(work->old_fb), obj, |
a071fa00 DV |
10824 | INTEL_FRONTBUFFER_PRIMARY(pipe)); |
10825 | ||
7ff0ebcc | 10826 | intel_fbc_disable(dev); |
f99d7069 | 10827 | intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
6b95a207 KH |
10828 | mutex_unlock(&dev->struct_mutex); |
10829 | ||
e5510fac JB |
10830 | trace_i915_flip_request(intel_crtc->plane, obj); |
10831 | ||
6b95a207 | 10832 | return 0; |
96b099fd | 10833 | |
4fa62c89 | 10834 | cleanup_unpin: |
82bc3b2d | 10835 | intel_unpin_fb_obj(fb, crtc->primary->state); |
8c9f3aaf | 10836 | cleanup_pending: |
b4a98e57 | 10837 | atomic_dec(&intel_crtc->unpin_work_count); |
89ed88ba CW |
10838 | mutex_unlock(&dev->struct_mutex); |
10839 | cleanup: | |
f4510a27 | 10840 | crtc->primary->fb = old_fb; |
afd65eb4 | 10841 | update_state_fb(crtc->primary); |
89ed88ba CW |
10842 | |
10843 | drm_gem_object_unreference_unlocked(&obj->base); | |
ab8d6675 | 10844 | drm_framebuffer_unreference(work->old_fb); |
96b099fd | 10845 | |
5e2d7afc | 10846 | spin_lock_irq(&dev->event_lock); |
96b099fd | 10847 | intel_crtc->unpin_work = NULL; |
5e2d7afc | 10848 | spin_unlock_irq(&dev->event_lock); |
96b099fd | 10849 | |
87b6b101 | 10850 | drm_crtc_vblank_put(crtc); |
7317c75e | 10851 | free_work: |
96b099fd CW |
10852 | kfree(work); |
10853 | ||
f900db47 CW |
10854 | if (ret == -EIO) { |
10855 | out_hang: | |
53a366b9 | 10856 | ret = intel_plane_restore(primary); |
f0d3dad3 | 10857 | if (ret == 0 && event) { |
5e2d7afc | 10858 | spin_lock_irq(&dev->event_lock); |
a071fa00 | 10859 | drm_send_vblank_event(dev, pipe, event); |
5e2d7afc | 10860 | spin_unlock_irq(&dev->event_lock); |
f0d3dad3 | 10861 | } |
f900db47 | 10862 | } |
96b099fd | 10863 | return ret; |
6b95a207 KH |
10864 | } |
10865 | ||
f6e5b160 | 10866 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
10867 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
10868 | .load_lut = intel_crtc_load_lut, | |
ea2c67bb MR |
10869 | .atomic_begin = intel_begin_crtc_commit, |
10870 | .atomic_flush = intel_finish_crtc_commit, | |
f6e5b160 CW |
10871 | }; |
10872 | ||
9a935856 DV |
10873 | /** |
10874 | * intel_modeset_update_staged_output_state | |
10875 | * | |
10876 | * Updates the staged output configuration state, e.g. after we've read out the | |
10877 | * current hw state. | |
10878 | */ | |
10879 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) | |
f6e5b160 | 10880 | { |
7668851f | 10881 | struct intel_crtc *crtc; |
9a935856 DV |
10882 | struct intel_encoder *encoder; |
10883 | struct intel_connector *connector; | |
f6e5b160 | 10884 | |
3a3371ff | 10885 | for_each_intel_connector(dev, connector) { |
9a935856 DV |
10886 | connector->new_encoder = |
10887 | to_intel_encoder(connector->base.encoder); | |
10888 | } | |
f6e5b160 | 10889 | |
b2784e15 | 10890 | for_each_intel_encoder(dev, encoder) { |
9a935856 DV |
10891 | encoder->new_crtc = |
10892 | to_intel_crtc(encoder->base.crtc); | |
10893 | } | |
7668851f | 10894 | |
d3fcc808 | 10895 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 10896 | crtc->new_enabled = crtc->base.state->enable; |
7668851f | 10897 | } |
f6e5b160 CW |
10898 | } |
10899 | ||
d29b2f9d ACO |
10900 | /* Transitional helper to copy current connector/encoder state to |
10901 | * connector->state. This is needed so that code that is partially | |
10902 | * converted to atomic does the right thing. | |
10903 | */ | |
10904 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) | |
10905 | { | |
10906 | struct intel_connector *connector; | |
10907 | ||
10908 | for_each_intel_connector(dev, connector) { | |
10909 | if (connector->base.encoder) { | |
10910 | connector->base.state->best_encoder = | |
10911 | connector->base.encoder; | |
10912 | connector->base.state->crtc = | |
10913 | connector->base.encoder->crtc; | |
10914 | } else { | |
10915 | connector->base.state->best_encoder = NULL; | |
10916 | connector->base.state->crtc = NULL; | |
10917 | } | |
10918 | } | |
10919 | } | |
10920 | ||
9a935856 DV |
10921 | /** |
10922 | * intel_modeset_commit_output_state | |
10923 | * | |
10924 | * This function copies the stage display pipe configuration to the real one. | |
10925 | */ | |
10926 | static void intel_modeset_commit_output_state(struct drm_device *dev) | |
10927 | { | |
7668851f | 10928 | struct intel_crtc *crtc; |
9a935856 DV |
10929 | struct intel_encoder *encoder; |
10930 | struct intel_connector *connector; | |
f6e5b160 | 10931 | |
3a3371ff | 10932 | for_each_intel_connector(dev, connector) { |
9a935856 DV |
10933 | connector->base.encoder = &connector->new_encoder->base; |
10934 | } | |
f6e5b160 | 10935 | |
b2784e15 | 10936 | for_each_intel_encoder(dev, encoder) { |
9a935856 DV |
10937 | encoder->base.crtc = &encoder->new_crtc->base; |
10938 | } | |
7668851f | 10939 | |
d3fcc808 | 10940 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 10941 | crtc->base.state->enable = crtc->new_enabled; |
7668851f VS |
10942 | crtc->base.enabled = crtc->new_enabled; |
10943 | } | |
d29b2f9d ACO |
10944 | |
10945 | intel_modeset_update_connector_atomic_state(dev); | |
9a935856 DV |
10946 | } |
10947 | ||
050f7aeb | 10948 | static void |
eba905b2 | 10949 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 10950 | struct intel_crtc_state *pipe_config) |
050f7aeb DV |
10951 | { |
10952 | int bpp = pipe_config->pipe_bpp; | |
10953 | ||
10954 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
10955 | connector->base.base.id, | |
c23cc417 | 10956 | connector->base.name); |
050f7aeb DV |
10957 | |
10958 | /* Don't use an invalid EDID bpc value */ | |
10959 | if (connector->base.display_info.bpc && | |
10960 | connector->base.display_info.bpc * 3 < bpp) { | |
10961 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
10962 | bpp, connector->base.display_info.bpc*3); | |
10963 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
10964 | } | |
10965 | ||
10966 | /* Clamp bpp to 8 on screens without EDID 1.4 */ | |
10967 | if (connector->base.display_info.bpc == 0 && bpp > 24) { | |
10968 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", | |
10969 | bpp); | |
10970 | pipe_config->pipe_bpp = 24; | |
10971 | } | |
10972 | } | |
10973 | ||
4e53c2e0 | 10974 | static int |
050f7aeb | 10975 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 10976 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 10977 | { |
050f7aeb | 10978 | struct drm_device *dev = crtc->base.dev; |
1486017f | 10979 | struct drm_atomic_state *state; |
050f7aeb | 10980 | struct intel_connector *connector; |
1486017f | 10981 | int bpp, i; |
4e53c2e0 | 10982 | |
d328c9d7 | 10983 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev))) |
4e53c2e0 | 10984 | bpp = 10*3; |
d328c9d7 DV |
10985 | else if (INTEL_INFO(dev)->gen >= 5) |
10986 | bpp = 12*3; | |
10987 | else | |
10988 | bpp = 8*3; | |
10989 | ||
4e53c2e0 | 10990 | |
4e53c2e0 DV |
10991 | pipe_config->pipe_bpp = bpp; |
10992 | ||
1486017f ACO |
10993 | state = pipe_config->base.state; |
10994 | ||
4e53c2e0 | 10995 | /* Clamp display bpp to EDID value */ |
1486017f ACO |
10996 | for (i = 0; i < state->num_connector; i++) { |
10997 | if (!state->connectors[i]) | |
10998 | continue; | |
10999 | ||
11000 | connector = to_intel_connector(state->connectors[i]); | |
11001 | if (state->connector_states[i]->crtc != &crtc->base) | |
4e53c2e0 DV |
11002 | continue; |
11003 | ||
050f7aeb | 11004 | connected_sink_compute_bpp(connector, pipe_config); |
4e53c2e0 DV |
11005 | } |
11006 | ||
11007 | return bpp; | |
11008 | } | |
11009 | ||
644db711 DV |
11010 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
11011 | { | |
11012 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
11013 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 11014 | mode->crtc_clock, |
644db711 DV |
11015 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
11016 | mode->crtc_hsync_end, mode->crtc_htotal, | |
11017 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
11018 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
11019 | } | |
11020 | ||
c0b03411 | 11021 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 11022 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
11023 | const char *context) |
11024 | { | |
6a60cd87 CK |
11025 | struct drm_device *dev = crtc->base.dev; |
11026 | struct drm_plane *plane; | |
11027 | struct intel_plane *intel_plane; | |
11028 | struct intel_plane_state *state; | |
11029 | struct drm_framebuffer *fb; | |
11030 | ||
11031 | DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id, | |
11032 | context, pipe_config, pipe_name(crtc->pipe)); | |
c0b03411 DV |
11033 | |
11034 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
11035 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
11036 | pipe_config->pipe_bpp, pipe_config->dither); | |
11037 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
11038 | pipe_config->has_pch_encoder, | |
11039 | pipe_config->fdi_lanes, | |
11040 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
11041 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
11042 | pipe_config->fdi_m_n.tu); | |
eb14cb74 VS |
11043 | DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
11044 | pipe_config->has_dp_encoder, | |
11045 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, | |
11046 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
11047 | pipe_config->dp_m_n.tu); | |
b95af8be VK |
11048 | |
11049 | DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", | |
11050 | pipe_config->has_dp_encoder, | |
11051 | pipe_config->dp_m2_n2.gmch_m, | |
11052 | pipe_config->dp_m2_n2.gmch_n, | |
11053 | pipe_config->dp_m2_n2.link_m, | |
11054 | pipe_config->dp_m2_n2.link_n, | |
11055 | pipe_config->dp_m2_n2.tu); | |
11056 | ||
55072d19 DV |
11057 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
11058 | pipe_config->has_audio, | |
11059 | pipe_config->has_infoframe); | |
11060 | ||
c0b03411 | 11061 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 11062 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 11063 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
11064 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
11065 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
d71b8d4a | 11066 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
11067 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
11068 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
6a60cd87 CK |
11069 | DRM_DEBUG_KMS("num_scalers: %d\n", crtc->num_scalers); |
11070 | DRM_DEBUG_KMS("scaler_users: 0x%x\n", pipe_config->scaler_state.scaler_users); | |
11071 | DRM_DEBUG_KMS("scaler id: %d\n", pipe_config->scaler_state.scaler_id); | |
c0b03411 DV |
11072 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
11073 | pipe_config->gmch_pfit.control, | |
11074 | pipe_config->gmch_pfit.pgm_ratios, | |
11075 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 11076 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 11077 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
11078 | pipe_config->pch_pfit.size, |
11079 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 11080 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 11081 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
6a60cd87 CK |
11082 | |
11083 | DRM_DEBUG_KMS("planes on this crtc\n"); | |
11084 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
11085 | intel_plane = to_intel_plane(plane); | |
11086 | if (intel_plane->pipe != crtc->pipe) | |
11087 | continue; | |
11088 | ||
11089 | state = to_intel_plane_state(plane->state); | |
11090 | fb = state->base.fb; | |
11091 | if (!fb) { | |
11092 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d " | |
11093 | "disabled, scaler_id = %d\n", | |
11094 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
11095 | plane->base.id, intel_plane->pipe, | |
11096 | (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1, | |
11097 | drm_plane_index(plane), state->scaler_id); | |
11098 | continue; | |
11099 | } | |
11100 | ||
11101 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled", | |
11102 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
11103 | plane->base.id, intel_plane->pipe, | |
11104 | crtc->base.primary == plane ? 0 : intel_plane->plane + 1, | |
11105 | drm_plane_index(plane)); | |
11106 | DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x", | |
11107 | fb->base.id, fb->width, fb->height, fb->pixel_format); | |
11108 | DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n", | |
11109 | state->scaler_id, | |
11110 | state->src.x1 >> 16, state->src.y1 >> 16, | |
11111 | drm_rect_width(&state->src) >> 16, | |
11112 | drm_rect_height(&state->src) >> 16, | |
11113 | state->dst.x1, state->dst.y1, | |
11114 | drm_rect_width(&state->dst), drm_rect_height(&state->dst)); | |
11115 | } | |
c0b03411 DV |
11116 | } |
11117 | ||
bc079e8b VS |
11118 | static bool encoders_cloneable(const struct intel_encoder *a, |
11119 | const struct intel_encoder *b) | |
accfc0c5 | 11120 | { |
bc079e8b VS |
11121 | /* masks could be asymmetric, so check both ways */ |
11122 | return a == b || (a->cloneable & (1 << b->type) && | |
11123 | b->cloneable & (1 << a->type)); | |
11124 | } | |
11125 | ||
98a221da ACO |
11126 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, |
11127 | struct intel_crtc *crtc, | |
bc079e8b VS |
11128 | struct intel_encoder *encoder) |
11129 | { | |
bc079e8b | 11130 | struct intel_encoder *source_encoder; |
98a221da ACO |
11131 | struct drm_connector_state *connector_state; |
11132 | int i; | |
11133 | ||
11134 | for (i = 0; i < state->num_connector; i++) { | |
11135 | if (!state->connectors[i]) | |
11136 | continue; | |
bc079e8b | 11137 | |
98a221da ACO |
11138 | connector_state = state->connector_states[i]; |
11139 | if (connector_state->crtc != &crtc->base) | |
bc079e8b VS |
11140 | continue; |
11141 | ||
98a221da ACO |
11142 | source_encoder = |
11143 | to_intel_encoder(connector_state->best_encoder); | |
bc079e8b VS |
11144 | if (!encoders_cloneable(encoder, source_encoder)) |
11145 | return false; | |
11146 | } | |
11147 | ||
11148 | return true; | |
11149 | } | |
11150 | ||
98a221da ACO |
11151 | static bool check_encoder_cloning(struct drm_atomic_state *state, |
11152 | struct intel_crtc *crtc) | |
bc079e8b | 11153 | { |
accfc0c5 | 11154 | struct intel_encoder *encoder; |
98a221da ACO |
11155 | struct drm_connector_state *connector_state; |
11156 | int i; | |
accfc0c5 | 11157 | |
98a221da ACO |
11158 | for (i = 0; i < state->num_connector; i++) { |
11159 | if (!state->connectors[i]) | |
accfc0c5 DV |
11160 | continue; |
11161 | ||
98a221da ACO |
11162 | connector_state = state->connector_states[i]; |
11163 | if (connector_state->crtc != &crtc->base) | |
11164 | continue; | |
11165 | ||
11166 | encoder = to_intel_encoder(connector_state->best_encoder); | |
11167 | if (!check_single_encoder_cloning(state, crtc, encoder)) | |
bc079e8b | 11168 | return false; |
accfc0c5 DV |
11169 | } |
11170 | ||
bc079e8b | 11171 | return true; |
accfc0c5 DV |
11172 | } |
11173 | ||
5448a00d | 11174 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 11175 | { |
5448a00d ACO |
11176 | struct drm_device *dev = state->dev; |
11177 | struct intel_encoder *encoder; | |
11178 | struct drm_connector_state *connector_state; | |
00f0b378 | 11179 | unsigned int used_ports = 0; |
5448a00d | 11180 | int i; |
00f0b378 VS |
11181 | |
11182 | /* | |
11183 | * Walk the connector list instead of the encoder | |
11184 | * list to detect the problem on ddi platforms | |
11185 | * where there's just one encoder per digital port. | |
11186 | */ | |
5448a00d ACO |
11187 | for (i = 0; i < state->num_connector; i++) { |
11188 | if (!state->connectors[i]) | |
11189 | continue; | |
00f0b378 | 11190 | |
5448a00d ACO |
11191 | connector_state = state->connector_states[i]; |
11192 | if (!connector_state->best_encoder) | |
00f0b378 VS |
11193 | continue; |
11194 | ||
5448a00d ACO |
11195 | encoder = to_intel_encoder(connector_state->best_encoder); |
11196 | ||
11197 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
11198 | |
11199 | switch (encoder->type) { | |
11200 | unsigned int port_mask; | |
11201 | case INTEL_OUTPUT_UNKNOWN: | |
11202 | if (WARN_ON(!HAS_DDI(dev))) | |
11203 | break; | |
11204 | case INTEL_OUTPUT_DISPLAYPORT: | |
11205 | case INTEL_OUTPUT_HDMI: | |
11206 | case INTEL_OUTPUT_EDP: | |
11207 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
11208 | ||
11209 | /* the same port mustn't appear more than once */ | |
11210 | if (used_ports & port_mask) | |
11211 | return false; | |
11212 | ||
11213 | used_ports |= port_mask; | |
11214 | default: | |
11215 | break; | |
11216 | } | |
11217 | } | |
11218 | ||
11219 | return true; | |
11220 | } | |
11221 | ||
83a57153 ACO |
11222 | static void |
11223 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
11224 | { | |
11225 | struct drm_crtc_state tmp_state; | |
663a3640 | 11226 | struct intel_crtc_scaler_state scaler_state; |
83a57153 | 11227 | |
663a3640 | 11228 | /* Clear only the intel specific part of the crtc state excluding scalers */ |
83a57153 | 11229 | tmp_state = crtc_state->base; |
663a3640 | 11230 | scaler_state = crtc_state->scaler_state; |
83a57153 ACO |
11231 | memset(crtc_state, 0, sizeof *crtc_state); |
11232 | crtc_state->base = tmp_state; | |
663a3640 | 11233 | crtc_state->scaler_state = scaler_state; |
83a57153 ACO |
11234 | } |
11235 | ||
5cec258b | 11236 | static struct intel_crtc_state * |
b8cecdf5 | 11237 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
4e53c2e0 | 11238 | struct drm_framebuffer *fb, |
83a57153 ACO |
11239 | struct drm_display_mode *mode, |
11240 | struct drm_atomic_state *state) | |
ee7b9f93 | 11241 | { |
7758a113 | 11242 | struct intel_encoder *encoder; |
0b901879 ACO |
11243 | struct intel_connector *connector; |
11244 | struct drm_connector_state *connector_state; | |
5cec258b | 11245 | struct intel_crtc_state *pipe_config; |
d328c9d7 | 11246 | int base_bpp, ret = -EINVAL; |
0b901879 | 11247 | int i; |
e29c22c0 | 11248 | bool retry = true; |
ee7b9f93 | 11249 | |
98a221da | 11250 | if (!check_encoder_cloning(state, to_intel_crtc(crtc))) { |
accfc0c5 DV |
11251 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); |
11252 | return ERR_PTR(-EINVAL); | |
11253 | } | |
11254 | ||
5448a00d | 11255 | if (!check_digital_port_conflicts(state)) { |
00f0b378 VS |
11256 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); |
11257 | return ERR_PTR(-EINVAL); | |
11258 | } | |
11259 | ||
83a57153 ACO |
11260 | pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc)); |
11261 | if (IS_ERR(pipe_config)) | |
11262 | return pipe_config; | |
11263 | ||
11264 | clear_intel_crtc_state(pipe_config); | |
7758a113 | 11265 | |
07878248 | 11266 | pipe_config->base.crtc = crtc; |
2d112de7 ACO |
11267 | drm_mode_copy(&pipe_config->base.adjusted_mode, mode); |
11268 | drm_mode_copy(&pipe_config->base.mode, mode); | |
37327abd | 11269 | |
e143a21c DV |
11270 | pipe_config->cpu_transcoder = |
11271 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
c0d43d62 | 11272 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
b8cecdf5 | 11273 | |
2960bc9c ID |
11274 | /* |
11275 | * Sanitize sync polarity flags based on requested ones. If neither | |
11276 | * positive or negative polarity is requested, treat this as meaning | |
11277 | * negative polarity. | |
11278 | */ | |
2d112de7 | 11279 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 11280 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 11281 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 11282 | |
2d112de7 | 11283 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 11284 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 11285 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 11286 | |
050f7aeb DV |
11287 | /* Compute a starting value for pipe_config->pipe_bpp taking the source |
11288 | * plane pixel format and any sink constraints into account. Returns the | |
11289 | * source plane bpp so that dithering can be selected on mismatches | |
11290 | * after encoders and crtc also have had their say. */ | |
d328c9d7 DV |
11291 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
11292 | pipe_config); | |
11293 | if (base_bpp < 0) | |
4e53c2e0 DV |
11294 | goto fail; |
11295 | ||
e41a56be VS |
11296 | /* |
11297 | * Determine the real pipe dimensions. Note that stereo modes can | |
11298 | * increase the actual pipe size due to the frame doubling and | |
11299 | * insertion of additional space for blanks between the frame. This | |
11300 | * is stored in the crtc timings. We use the requested mode to do this | |
11301 | * computation to clearly distinguish it from the adjusted mode, which | |
11302 | * can be changed by the connectors in the below retry loop. | |
11303 | */ | |
2d112de7 | 11304 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
11305 | &pipe_config->pipe_src_w, |
11306 | &pipe_config->pipe_src_h); | |
e41a56be | 11307 | |
e29c22c0 | 11308 | encoder_retry: |
ef1b460d | 11309 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 11310 | pipe_config->port_clock = 0; |
ef1b460d | 11311 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 11312 | |
135c81b8 | 11313 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
11314 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
11315 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 11316 | |
7758a113 DV |
11317 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
11318 | * adjust it according to limitations or connector properties, and also | |
11319 | * a chance to reject the mode entirely. | |
47f1c6c9 | 11320 | */ |
0b901879 ACO |
11321 | for (i = 0; i < state->num_connector; i++) { |
11322 | connector = to_intel_connector(state->connectors[i]); | |
11323 | if (!connector) | |
11324 | continue; | |
47f1c6c9 | 11325 | |
0b901879 ACO |
11326 | connector_state = state->connector_states[i]; |
11327 | if (connector_state->crtc != crtc) | |
7758a113 | 11328 | continue; |
7ae89233 | 11329 | |
0b901879 ACO |
11330 | encoder = to_intel_encoder(connector_state->best_encoder); |
11331 | ||
efea6e8e DV |
11332 | if (!(encoder->compute_config(encoder, pipe_config))) { |
11333 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
11334 | goto fail; |
11335 | } | |
ee7b9f93 | 11336 | } |
47f1c6c9 | 11337 | |
ff9a6750 DV |
11338 | /* Set default port clock if not overwritten by the encoder. Needs to be |
11339 | * done afterwards in case the encoder adjusts the mode. */ | |
11340 | if (!pipe_config->port_clock) | |
2d112de7 | 11341 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 11342 | * pipe_config->pixel_multiplier; |
ff9a6750 | 11343 | |
a43f6e0f | 11344 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 11345 | if (ret < 0) { |
7758a113 DV |
11346 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
11347 | goto fail; | |
ee7b9f93 | 11348 | } |
e29c22c0 DV |
11349 | |
11350 | if (ret == RETRY) { | |
11351 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
11352 | ret = -EINVAL; | |
11353 | goto fail; | |
11354 | } | |
11355 | ||
11356 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
11357 | retry = false; | |
11358 | goto encoder_retry; | |
11359 | } | |
11360 | ||
d328c9d7 | 11361 | pipe_config->dither = pipe_config->pipe_bpp != base_bpp; |
4e53c2e0 | 11362 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 11363 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 11364 | |
b8cecdf5 | 11365 | return pipe_config; |
7758a113 | 11366 | fail: |
e29c22c0 | 11367 | return ERR_PTR(ret); |
ee7b9f93 | 11368 | } |
47f1c6c9 | 11369 | |
e2e1ed41 DV |
11370 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
11371 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ | |
11372 | static void | |
11373 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, | |
11374 | unsigned *prepare_pipes, unsigned *disable_pipes) | |
79e53945 JB |
11375 | { |
11376 | struct intel_crtc *intel_crtc; | |
e2e1ed41 DV |
11377 | struct drm_device *dev = crtc->dev; |
11378 | struct intel_encoder *encoder; | |
11379 | struct intel_connector *connector; | |
11380 | struct drm_crtc *tmp_crtc; | |
79e53945 | 11381 | |
e2e1ed41 | 11382 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
79e53945 | 11383 | |
e2e1ed41 DV |
11384 | /* Check which crtcs have changed outputs connected to them, these need |
11385 | * to be part of the prepare_pipes mask. We don't (yet) support global | |
11386 | * modeset across multiple crtcs, so modeset_pipes will only have one | |
11387 | * bit set at most. */ | |
3a3371ff | 11388 | for_each_intel_connector(dev, connector) { |
e2e1ed41 DV |
11389 | if (connector->base.encoder == &connector->new_encoder->base) |
11390 | continue; | |
79e53945 | 11391 | |
e2e1ed41 DV |
11392 | if (connector->base.encoder) { |
11393 | tmp_crtc = connector->base.encoder->crtc; | |
11394 | ||
11395 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
11396 | } | |
11397 | ||
11398 | if (connector->new_encoder) | |
11399 | *prepare_pipes |= | |
11400 | 1 << connector->new_encoder->new_crtc->pipe; | |
79e53945 JB |
11401 | } |
11402 | ||
b2784e15 | 11403 | for_each_intel_encoder(dev, encoder) { |
e2e1ed41 DV |
11404 | if (encoder->base.crtc == &encoder->new_crtc->base) |
11405 | continue; | |
11406 | ||
11407 | if (encoder->base.crtc) { | |
11408 | tmp_crtc = encoder->base.crtc; | |
11409 | ||
11410 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
11411 | } | |
11412 | ||
11413 | if (encoder->new_crtc) | |
11414 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; | |
80824003 JB |
11415 | } |
11416 | ||
7668851f | 11417 | /* Check for pipes that will be enabled/disabled ... */ |
d3fcc808 | 11418 | for_each_intel_crtc(dev, intel_crtc) { |
83d65738 | 11419 | if (intel_crtc->base.state->enable == intel_crtc->new_enabled) |
e2e1ed41 | 11420 | continue; |
7e7d76c3 | 11421 | |
7668851f | 11422 | if (!intel_crtc->new_enabled) |
e2e1ed41 | 11423 | *disable_pipes |= 1 << intel_crtc->pipe; |
7668851f VS |
11424 | else |
11425 | *prepare_pipes |= 1 << intel_crtc->pipe; | |
7e7d76c3 JB |
11426 | } |
11427 | ||
e2e1ed41 DV |
11428 | |
11429 | /* set_mode is also used to update properties on life display pipes. */ | |
11430 | intel_crtc = to_intel_crtc(crtc); | |
7668851f | 11431 | if (intel_crtc->new_enabled) |
e2e1ed41 DV |
11432 | *prepare_pipes |= 1 << intel_crtc->pipe; |
11433 | ||
b6c5164d DV |
11434 | /* |
11435 | * For simplicity do a full modeset on any pipe where the output routing | |
11436 | * changed. We could be more clever, but that would require us to be | |
11437 | * more careful with calling the relevant encoder->mode_set functions. | |
11438 | */ | |
e2e1ed41 DV |
11439 | if (*prepare_pipes) |
11440 | *modeset_pipes = *prepare_pipes; | |
11441 | ||
11442 | /* ... and mask these out. */ | |
11443 | *modeset_pipes &= ~(*disable_pipes); | |
11444 | *prepare_pipes &= ~(*disable_pipes); | |
b6c5164d DV |
11445 | |
11446 | /* | |
11447 | * HACK: We don't (yet) fully support global modesets. intel_set_config | |
11448 | * obies this rule, but the modeset restore mode of | |
11449 | * intel_modeset_setup_hw_state does not. | |
11450 | */ | |
11451 | *modeset_pipes &= 1 << intel_crtc->pipe; | |
11452 | *prepare_pipes &= 1 << intel_crtc->pipe; | |
e3641d3f DV |
11453 | |
11454 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", | |
11455 | *modeset_pipes, *prepare_pipes, *disable_pipes); | |
47f1c6c9 | 11456 | } |
79e53945 | 11457 | |
ea9d758d | 11458 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
f6e5b160 | 11459 | { |
ea9d758d | 11460 | struct drm_encoder *encoder; |
f6e5b160 | 11461 | struct drm_device *dev = crtc->dev; |
f6e5b160 | 11462 | |
ea9d758d DV |
11463 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
11464 | if (encoder->crtc == crtc) | |
11465 | return true; | |
11466 | ||
11467 | return false; | |
11468 | } | |
11469 | ||
11470 | static void | |
11471 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) | |
11472 | { | |
ba41c0de | 11473 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea9d758d DV |
11474 | struct intel_encoder *intel_encoder; |
11475 | struct intel_crtc *intel_crtc; | |
11476 | struct drm_connector *connector; | |
11477 | ||
ba41c0de DV |
11478 | intel_shared_dpll_commit(dev_priv); |
11479 | ||
b2784e15 | 11480 | for_each_intel_encoder(dev, intel_encoder) { |
ea9d758d DV |
11481 | if (!intel_encoder->base.crtc) |
11482 | continue; | |
11483 | ||
11484 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); | |
11485 | ||
11486 | if (prepare_pipes & (1 << intel_crtc->pipe)) | |
11487 | intel_encoder->connectors_active = false; | |
11488 | } | |
11489 | ||
11490 | intel_modeset_commit_output_state(dev); | |
11491 | ||
7668851f | 11492 | /* Double check state. */ |
d3fcc808 | 11493 | for_each_intel_crtc(dev, intel_crtc) { |
83d65738 | 11494 | WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base)); |
ea9d758d DV |
11495 | } |
11496 | ||
11497 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
11498 | if (!connector->encoder || !connector->encoder->crtc) | |
11499 | continue; | |
11500 | ||
11501 | intel_crtc = to_intel_crtc(connector->encoder->crtc); | |
11502 | ||
11503 | if (prepare_pipes & (1 << intel_crtc->pipe)) { | |
68d34720 DV |
11504 | struct drm_property *dpms_property = |
11505 | dev->mode_config.dpms_property; | |
11506 | ||
ea9d758d | 11507 | connector->dpms = DRM_MODE_DPMS_ON; |
662595df | 11508 | drm_object_property_set_value(&connector->base, |
68d34720 DV |
11509 | dpms_property, |
11510 | DRM_MODE_DPMS_ON); | |
ea9d758d DV |
11511 | |
11512 | intel_encoder = to_intel_encoder(connector->encoder); | |
11513 | intel_encoder->connectors_active = true; | |
11514 | } | |
11515 | } | |
11516 | ||
11517 | } | |
11518 | ||
3bd26263 | 11519 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 11520 | { |
3bd26263 | 11521 | int diff; |
f1f644dc JB |
11522 | |
11523 | if (clock1 == clock2) | |
11524 | return true; | |
11525 | ||
11526 | if (!clock1 || !clock2) | |
11527 | return false; | |
11528 | ||
11529 | diff = abs(clock1 - clock2); | |
11530 | ||
11531 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
11532 | return true; | |
11533 | ||
11534 | return false; | |
11535 | } | |
11536 | ||
25c5b266 DV |
11537 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
11538 | list_for_each_entry((intel_crtc), \ | |
11539 | &(dev)->mode_config.crtc_list, \ | |
11540 | base.head) \ | |
0973f18f | 11541 | if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 11542 | |
0e8ffe1b | 11543 | static bool |
2fa2fe9a | 11544 | intel_pipe_config_compare(struct drm_device *dev, |
5cec258b ACO |
11545 | struct intel_crtc_state *current_config, |
11546 | struct intel_crtc_state *pipe_config) | |
0e8ffe1b | 11547 | { |
66e985c0 DV |
11548 | #define PIPE_CONF_CHECK_X(name) \ |
11549 | if (current_config->name != pipe_config->name) { \ | |
11550 | DRM_ERROR("mismatch in " #name " " \ | |
11551 | "(expected 0x%08x, found 0x%08x)\n", \ | |
11552 | current_config->name, \ | |
11553 | pipe_config->name); \ | |
11554 | return false; \ | |
11555 | } | |
11556 | ||
08a24034 DV |
11557 | #define PIPE_CONF_CHECK_I(name) \ |
11558 | if (current_config->name != pipe_config->name) { \ | |
11559 | DRM_ERROR("mismatch in " #name " " \ | |
11560 | "(expected %i, found %i)\n", \ | |
11561 | current_config->name, \ | |
11562 | pipe_config->name); \ | |
11563 | return false; \ | |
88adfff1 DV |
11564 | } |
11565 | ||
b95af8be VK |
11566 | /* This is required for BDW+ where there is only one set of registers for |
11567 | * switching between high and low RR. | |
11568 | * This macro can be used whenever a comparison has to be made between one | |
11569 | * hw state and multiple sw state variables. | |
11570 | */ | |
11571 | #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \ | |
11572 | if ((current_config->name != pipe_config->name) && \ | |
11573 | (current_config->alt_name != pipe_config->name)) { \ | |
11574 | DRM_ERROR("mismatch in " #name " " \ | |
11575 | "(expected %i or %i, found %i)\n", \ | |
11576 | current_config->name, \ | |
11577 | current_config->alt_name, \ | |
11578 | pipe_config->name); \ | |
11579 | return false; \ | |
11580 | } | |
11581 | ||
1bd1bd80 DV |
11582 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
11583 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
6f02488e | 11584 | DRM_ERROR("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
11585 | "(expected %i, found %i)\n", \ |
11586 | current_config->name & (mask), \ | |
11587 | pipe_config->name & (mask)); \ | |
11588 | return false; \ | |
11589 | } | |
11590 | ||
5e550656 VS |
11591 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
11592 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
11593 | DRM_ERROR("mismatch in " #name " " \ | |
11594 | "(expected %i, found %i)\n", \ | |
11595 | current_config->name, \ | |
11596 | pipe_config->name); \ | |
11597 | return false; \ | |
11598 | } | |
11599 | ||
bb760063 DV |
11600 | #define PIPE_CONF_QUIRK(quirk) \ |
11601 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
11602 | ||
eccb140b DV |
11603 | PIPE_CONF_CHECK_I(cpu_transcoder); |
11604 | ||
08a24034 DV |
11605 | PIPE_CONF_CHECK_I(has_pch_encoder); |
11606 | PIPE_CONF_CHECK_I(fdi_lanes); | |
72419203 DV |
11607 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); |
11608 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); | |
11609 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); | |
11610 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); | |
11611 | PIPE_CONF_CHECK_I(fdi_m_n.tu); | |
08a24034 | 11612 | |
eb14cb74 | 11613 | PIPE_CONF_CHECK_I(has_dp_encoder); |
b95af8be VK |
11614 | |
11615 | if (INTEL_INFO(dev)->gen < 8) { | |
11616 | PIPE_CONF_CHECK_I(dp_m_n.gmch_m); | |
11617 | PIPE_CONF_CHECK_I(dp_m_n.gmch_n); | |
11618 | PIPE_CONF_CHECK_I(dp_m_n.link_m); | |
11619 | PIPE_CONF_CHECK_I(dp_m_n.link_n); | |
11620 | PIPE_CONF_CHECK_I(dp_m_n.tu); | |
11621 | ||
11622 | if (current_config->has_drrs) { | |
11623 | PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m); | |
11624 | PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n); | |
11625 | PIPE_CONF_CHECK_I(dp_m2_n2.link_m); | |
11626 | PIPE_CONF_CHECK_I(dp_m2_n2.link_n); | |
11627 | PIPE_CONF_CHECK_I(dp_m2_n2.tu); | |
11628 | } | |
11629 | } else { | |
11630 | PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m); | |
11631 | PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n); | |
11632 | PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m); | |
11633 | PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n); | |
11634 | PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu); | |
11635 | } | |
eb14cb74 | 11636 | |
2d112de7 ACO |
11637 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
11638 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
11639 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
11640 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
11641 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
11642 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 11643 | |
2d112de7 ACO |
11644 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
11645 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
11646 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
11647 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
11648 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
11649 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 11650 | |
c93f54cf | 11651 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 11652 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 DV |
11653 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
11654 | IS_VALLEYVIEW(dev)) | |
11655 | PIPE_CONF_CHECK_I(limited_color_range); | |
e43823ec | 11656 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 11657 | |
9ed109a7 DV |
11658 | PIPE_CONF_CHECK_I(has_audio); |
11659 | ||
2d112de7 | 11660 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
11661 | DRM_MODE_FLAG_INTERLACE); |
11662 | ||
bb760063 | 11663 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 11664 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11665 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 11666 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11667 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 11668 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11669 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 11670 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
11671 | DRM_MODE_FLAG_NVSYNC); |
11672 | } | |
045ac3b5 | 11673 | |
37327abd VS |
11674 | PIPE_CONF_CHECK_I(pipe_src_w); |
11675 | PIPE_CONF_CHECK_I(pipe_src_h); | |
1bd1bd80 | 11676 | |
9953599b DV |
11677 | /* |
11678 | * FIXME: BIOS likes to set up a cloned config with lvds+external | |
11679 | * screen. Since we don't yet re-compute the pipe config when moving | |
11680 | * just the lvds port away to another pipe the sw tracking won't match. | |
11681 | * | |
11682 | * Proper atomic modesets with recomputed global state will fix this. | |
11683 | * Until then just don't check gmch state for inherited modes. | |
11684 | */ | |
11685 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) { | |
11686 | PIPE_CONF_CHECK_I(gmch_pfit.control); | |
11687 | /* pfit ratios are autocomputed by the hw on gen4+ */ | |
11688 | if (INTEL_INFO(dev)->gen < 4) | |
11689 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
11690 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); | |
11691 | } | |
11692 | ||
fd4daa9c CW |
11693 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
11694 | if (current_config->pch_pfit.enabled) { | |
11695 | PIPE_CONF_CHECK_I(pch_pfit.pos); | |
11696 | PIPE_CONF_CHECK_I(pch_pfit.size); | |
11697 | } | |
2fa2fe9a | 11698 | |
a1b2278e CK |
11699 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
11700 | ||
e59150dc JB |
11701 | /* BDW+ don't expose a synchronous way to read the state */ |
11702 | if (IS_HASWELL(dev)) | |
11703 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 11704 | |
282740f7 VS |
11705 | PIPE_CONF_CHECK_I(double_wide); |
11706 | ||
26804afd DV |
11707 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
11708 | ||
c0d43d62 | 11709 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 11710 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 11711 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
11712 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
11713 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 11714 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
3f4cd19f DL |
11715 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
11716 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
11717 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 11718 | |
42571aef VS |
11719 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
11720 | PIPE_CONF_CHECK_I(pipe_bpp); | |
11721 | ||
2d112de7 | 11722 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 11723 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 11724 | |
66e985c0 | 11725 | #undef PIPE_CONF_CHECK_X |
08a24034 | 11726 | #undef PIPE_CONF_CHECK_I |
b95af8be | 11727 | #undef PIPE_CONF_CHECK_I_ALT |
1bd1bd80 | 11728 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 11729 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 11730 | #undef PIPE_CONF_QUIRK |
88adfff1 | 11731 | |
0e8ffe1b DV |
11732 | return true; |
11733 | } | |
11734 | ||
08db6652 DL |
11735 | static void check_wm_state(struct drm_device *dev) |
11736 | { | |
11737 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11738 | struct skl_ddb_allocation hw_ddb, *sw_ddb; | |
11739 | struct intel_crtc *intel_crtc; | |
11740 | int plane; | |
11741 | ||
11742 | if (INTEL_INFO(dev)->gen < 9) | |
11743 | return; | |
11744 | ||
11745 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); | |
11746 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
11747 | ||
11748 | for_each_intel_crtc(dev, intel_crtc) { | |
11749 | struct skl_ddb_entry *hw_entry, *sw_entry; | |
11750 | const enum pipe pipe = intel_crtc->pipe; | |
11751 | ||
11752 | if (!intel_crtc->active) | |
11753 | continue; | |
11754 | ||
11755 | /* planes */ | |
dd740780 | 11756 | for_each_plane(dev_priv, pipe, plane) { |
08db6652 DL |
11757 | hw_entry = &hw_ddb.plane[pipe][plane]; |
11758 | sw_entry = &sw_ddb->plane[pipe][plane]; | |
11759 | ||
11760 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
11761 | continue; | |
11762 | ||
11763 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " | |
11764 | "(expected (%u,%u), found (%u,%u))\n", | |
11765 | pipe_name(pipe), plane + 1, | |
11766 | sw_entry->start, sw_entry->end, | |
11767 | hw_entry->start, hw_entry->end); | |
11768 | } | |
11769 | ||
11770 | /* cursor */ | |
11771 | hw_entry = &hw_ddb.cursor[pipe]; | |
11772 | sw_entry = &sw_ddb->cursor[pipe]; | |
11773 | ||
11774 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
11775 | continue; | |
11776 | ||
11777 | DRM_ERROR("mismatch in DDB state pipe %c cursor " | |
11778 | "(expected (%u,%u), found (%u,%u))\n", | |
11779 | pipe_name(pipe), | |
11780 | sw_entry->start, sw_entry->end, | |
11781 | hw_entry->start, hw_entry->end); | |
11782 | } | |
11783 | } | |
11784 | ||
91d1b4bd DV |
11785 | static void |
11786 | check_connector_state(struct drm_device *dev) | |
8af6cf88 | 11787 | { |
8af6cf88 DV |
11788 | struct intel_connector *connector; |
11789 | ||
3a3371ff | 11790 | for_each_intel_connector(dev, connector) { |
8af6cf88 DV |
11791 | /* This also checks the encoder/connector hw state with the |
11792 | * ->get_hw_state callbacks. */ | |
11793 | intel_connector_check_state(connector); | |
11794 | ||
e2c719b7 | 11795 | I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder, |
8af6cf88 DV |
11796 | "connector's staged encoder doesn't match current encoder\n"); |
11797 | } | |
91d1b4bd DV |
11798 | } |
11799 | ||
11800 | static void | |
11801 | check_encoder_state(struct drm_device *dev) | |
11802 | { | |
11803 | struct intel_encoder *encoder; | |
11804 | struct intel_connector *connector; | |
8af6cf88 | 11805 | |
b2784e15 | 11806 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 DV |
11807 | bool enabled = false; |
11808 | bool active = false; | |
11809 | enum pipe pipe, tracked_pipe; | |
11810 | ||
11811 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
11812 | encoder->base.base.id, | |
8e329a03 | 11813 | encoder->base.name); |
8af6cf88 | 11814 | |
e2c719b7 | 11815 | I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc, |
8af6cf88 | 11816 | "encoder's stage crtc doesn't match current crtc\n"); |
e2c719b7 | 11817 | I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc, |
8af6cf88 DV |
11818 | "encoder's active_connectors set, but no crtc\n"); |
11819 | ||
3a3371ff | 11820 | for_each_intel_connector(dev, connector) { |
8af6cf88 DV |
11821 | if (connector->base.encoder != &encoder->base) |
11822 | continue; | |
11823 | enabled = true; | |
11824 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) | |
11825 | active = true; | |
11826 | } | |
0e32b39c DA |
11827 | /* |
11828 | * for MST connectors if we unplug the connector is gone | |
11829 | * away but the encoder is still connected to a crtc | |
11830 | * until a modeset happens in response to the hotplug. | |
11831 | */ | |
11832 | if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST) | |
11833 | continue; | |
11834 | ||
e2c719b7 | 11835 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
11836 | "encoder's enabled state mismatch " |
11837 | "(expected %i, found %i)\n", | |
11838 | !!encoder->base.crtc, enabled); | |
e2c719b7 | 11839 | I915_STATE_WARN(active && !encoder->base.crtc, |
8af6cf88 DV |
11840 | "active encoder with no crtc\n"); |
11841 | ||
e2c719b7 | 11842 | I915_STATE_WARN(encoder->connectors_active != active, |
8af6cf88 DV |
11843 | "encoder's computed active state doesn't match tracked active state " |
11844 | "(expected %i, found %i)\n", active, encoder->connectors_active); | |
11845 | ||
11846 | active = encoder->get_hw_state(encoder, &pipe); | |
e2c719b7 | 11847 | I915_STATE_WARN(active != encoder->connectors_active, |
8af6cf88 DV |
11848 | "encoder's hw state doesn't match sw tracking " |
11849 | "(expected %i, found %i)\n", | |
11850 | encoder->connectors_active, active); | |
11851 | ||
11852 | if (!encoder->base.crtc) | |
11853 | continue; | |
11854 | ||
11855 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; | |
e2c719b7 | 11856 | I915_STATE_WARN(active && pipe != tracked_pipe, |
8af6cf88 DV |
11857 | "active encoder's pipe doesn't match" |
11858 | "(expected %i, found %i)\n", | |
11859 | tracked_pipe, pipe); | |
11860 | ||
11861 | } | |
91d1b4bd DV |
11862 | } |
11863 | ||
11864 | static void | |
11865 | check_crtc_state(struct drm_device *dev) | |
11866 | { | |
fbee40df | 11867 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
11868 | struct intel_crtc *crtc; |
11869 | struct intel_encoder *encoder; | |
5cec258b | 11870 | struct intel_crtc_state pipe_config; |
8af6cf88 | 11871 | |
d3fcc808 | 11872 | for_each_intel_crtc(dev, crtc) { |
8af6cf88 DV |
11873 | bool enabled = false; |
11874 | bool active = false; | |
11875 | ||
045ac3b5 JB |
11876 | memset(&pipe_config, 0, sizeof(pipe_config)); |
11877 | ||
8af6cf88 DV |
11878 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
11879 | crtc->base.base.id); | |
11880 | ||
83d65738 | 11881 | I915_STATE_WARN(crtc->active && !crtc->base.state->enable, |
8af6cf88 DV |
11882 | "active crtc, but not enabled in sw tracking\n"); |
11883 | ||
b2784e15 | 11884 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 DV |
11885 | if (encoder->base.crtc != &crtc->base) |
11886 | continue; | |
11887 | enabled = true; | |
11888 | if (encoder->connectors_active) | |
11889 | active = true; | |
11890 | } | |
6c49f241 | 11891 | |
e2c719b7 | 11892 | I915_STATE_WARN(active != crtc->active, |
8af6cf88 DV |
11893 | "crtc's computed active state doesn't match tracked active state " |
11894 | "(expected %i, found %i)\n", active, crtc->active); | |
83d65738 | 11895 | I915_STATE_WARN(enabled != crtc->base.state->enable, |
8af6cf88 | 11896 | "crtc's computed enabled state doesn't match tracked enabled state " |
83d65738 MR |
11897 | "(expected %i, found %i)\n", enabled, |
11898 | crtc->base.state->enable); | |
8af6cf88 | 11899 | |
0e8ffe1b DV |
11900 | active = dev_priv->display.get_pipe_config(crtc, |
11901 | &pipe_config); | |
d62cf62a | 11902 | |
b6b5d049 VS |
11903 | /* hw state is inconsistent with the pipe quirk */ |
11904 | if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
11905 | (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
d62cf62a DV |
11906 | active = crtc->active; |
11907 | ||
b2784e15 | 11908 | for_each_intel_encoder(dev, encoder) { |
3eaba51c | 11909 | enum pipe pipe; |
6c49f241 DV |
11910 | if (encoder->base.crtc != &crtc->base) |
11911 | continue; | |
1d37b689 | 11912 | if (encoder->get_hw_state(encoder, &pipe)) |
6c49f241 DV |
11913 | encoder->get_config(encoder, &pipe_config); |
11914 | } | |
11915 | ||
e2c719b7 | 11916 | I915_STATE_WARN(crtc->active != active, |
0e8ffe1b DV |
11917 | "crtc active state doesn't match with hw state " |
11918 | "(expected %i, found %i)\n", crtc->active, active); | |
11919 | ||
c0b03411 | 11920 | if (active && |
6e3c9717 | 11921 | !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) { |
e2c719b7 | 11922 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); |
c0b03411 DV |
11923 | intel_dump_pipe_config(crtc, &pipe_config, |
11924 | "[hw state]"); | |
6e3c9717 | 11925 | intel_dump_pipe_config(crtc, crtc->config, |
c0b03411 DV |
11926 | "[sw state]"); |
11927 | } | |
8af6cf88 DV |
11928 | } |
11929 | } | |
11930 | ||
91d1b4bd DV |
11931 | static void |
11932 | check_shared_dpll_state(struct drm_device *dev) | |
11933 | { | |
fbee40df | 11934 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
11935 | struct intel_crtc *crtc; |
11936 | struct intel_dpll_hw_state dpll_hw_state; | |
11937 | int i; | |
5358901f DV |
11938 | |
11939 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
11940 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
11941 | int enabled_crtcs = 0, active_crtcs = 0; | |
11942 | bool active; | |
11943 | ||
11944 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
11945 | ||
11946 | DRM_DEBUG_KMS("%s\n", pll->name); | |
11947 | ||
11948 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
11949 | ||
e2c719b7 | 11950 | I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask), |
5358901f | 11951 | "more active pll users than references: %i vs %i\n", |
3e369b76 | 11952 | pll->active, hweight32(pll->config.crtc_mask)); |
e2c719b7 | 11953 | I915_STATE_WARN(pll->active && !pll->on, |
5358901f | 11954 | "pll in active use but not on in sw tracking\n"); |
e2c719b7 | 11955 | I915_STATE_WARN(pll->on && !pll->active, |
35c95375 | 11956 | "pll in on but not on in use in sw tracking\n"); |
e2c719b7 | 11957 | I915_STATE_WARN(pll->on != active, |
5358901f DV |
11958 | "pll on state mismatch (expected %i, found %i)\n", |
11959 | pll->on, active); | |
11960 | ||
d3fcc808 | 11961 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 11962 | if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll) |
5358901f DV |
11963 | enabled_crtcs++; |
11964 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
11965 | active_crtcs++; | |
11966 | } | |
e2c719b7 | 11967 | I915_STATE_WARN(pll->active != active_crtcs, |
5358901f DV |
11968 | "pll active crtcs mismatch (expected %i, found %i)\n", |
11969 | pll->active, active_crtcs); | |
e2c719b7 | 11970 | I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs, |
5358901f | 11971 | "pll enabled crtcs mismatch (expected %i, found %i)\n", |
3e369b76 | 11972 | hweight32(pll->config.crtc_mask), enabled_crtcs); |
66e985c0 | 11973 | |
e2c719b7 | 11974 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state, |
66e985c0 DV |
11975 | sizeof(dpll_hw_state)), |
11976 | "pll hw state mismatch\n"); | |
5358901f | 11977 | } |
8af6cf88 DV |
11978 | } |
11979 | ||
91d1b4bd DV |
11980 | void |
11981 | intel_modeset_check_state(struct drm_device *dev) | |
11982 | { | |
08db6652 | 11983 | check_wm_state(dev); |
91d1b4bd DV |
11984 | check_connector_state(dev); |
11985 | check_encoder_state(dev); | |
11986 | check_crtc_state(dev); | |
11987 | check_shared_dpll_state(dev); | |
11988 | } | |
11989 | ||
5cec258b | 11990 | void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config, |
18442d08 VS |
11991 | int dotclock) |
11992 | { | |
11993 | /* | |
11994 | * FDI already provided one idea for the dotclock. | |
11995 | * Yell if the encoder disagrees. | |
11996 | */ | |
2d112de7 | 11997 | WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock), |
18442d08 | 11998 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
2d112de7 | 11999 | pipe_config->base.adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
12000 | } |
12001 | ||
80715b2f VS |
12002 | static void update_scanline_offset(struct intel_crtc *crtc) |
12003 | { | |
12004 | struct drm_device *dev = crtc->base.dev; | |
12005 | ||
12006 | /* | |
12007 | * The scanline counter increments at the leading edge of hsync. | |
12008 | * | |
12009 | * On most platforms it starts counting from vtotal-1 on the | |
12010 | * first active line. That means the scanline counter value is | |
12011 | * always one less than what we would expect. Ie. just after | |
12012 | * start of vblank, which also occurs at start of hsync (on the | |
12013 | * last active line), the scanline counter will read vblank_start-1. | |
12014 | * | |
12015 | * On gen2 the scanline counter starts counting from 1 instead | |
12016 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
12017 | * to keep the value positive), instead of adding one. | |
12018 | * | |
12019 | * On HSW+ the behaviour of the scanline counter depends on the output | |
12020 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
12021 | * there's an extra 1 line difference. So we need to add two instead of | |
12022 | * one to the value. | |
12023 | */ | |
12024 | if (IS_GEN2(dev)) { | |
6e3c9717 | 12025 | const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
12026 | int vtotal; |
12027 | ||
12028 | vtotal = mode->crtc_vtotal; | |
12029 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
12030 | vtotal /= 2; | |
12031 | ||
12032 | crtc->scanline_offset = vtotal - 1; | |
12033 | } else if (HAS_DDI(dev) && | |
409ee761 | 12034 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
12035 | crtc->scanline_offset = 2; |
12036 | } else | |
12037 | crtc->scanline_offset = 1; | |
12038 | } | |
12039 | ||
5cec258b | 12040 | static struct intel_crtc_state * |
7f27126e JB |
12041 | intel_modeset_compute_config(struct drm_crtc *crtc, |
12042 | struct drm_display_mode *mode, | |
12043 | struct drm_framebuffer *fb, | |
83a57153 | 12044 | struct drm_atomic_state *state, |
7f27126e JB |
12045 | unsigned *modeset_pipes, |
12046 | unsigned *prepare_pipes, | |
12047 | unsigned *disable_pipes) | |
12048 | { | |
db7542dd | 12049 | struct drm_device *dev = crtc->dev; |
5cec258b | 12050 | struct intel_crtc_state *pipe_config = NULL; |
db7542dd | 12051 | struct intel_crtc *intel_crtc; |
0b901879 ACO |
12052 | int ret = 0; |
12053 | ||
12054 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
12055 | if (ret) | |
12056 | return ERR_PTR(ret); | |
7f27126e JB |
12057 | |
12058 | intel_modeset_affected_pipes(crtc, modeset_pipes, | |
12059 | prepare_pipes, disable_pipes); | |
12060 | ||
db7542dd ACO |
12061 | for_each_intel_crtc_masked(dev, *disable_pipes, intel_crtc) { |
12062 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
12063 | if (IS_ERR(pipe_config)) | |
12064 | return pipe_config; | |
12065 | ||
12066 | pipe_config->base.enable = false; | |
12067 | } | |
7f27126e JB |
12068 | |
12069 | /* | |
12070 | * Note this needs changes when we start tracking multiple modes | |
12071 | * and crtcs. At that point we'll need to compute the whole config | |
12072 | * (i.e. one pipe_config for each crtc) rather than just the one | |
12073 | * for this crtc. | |
12074 | */ | |
db7542dd ACO |
12075 | for_each_intel_crtc_masked(dev, *modeset_pipes, intel_crtc) { |
12076 | /* FIXME: For now we still expect modeset_pipes has at most | |
12077 | * one bit set. */ | |
12078 | if (WARN_ON(&intel_crtc->base != crtc)) | |
12079 | continue; | |
83a57153 | 12080 | |
db7542dd ACO |
12081 | pipe_config = intel_modeset_pipe_config(crtc, fb, mode, state); |
12082 | if (IS_ERR(pipe_config)) | |
12083 | return pipe_config; | |
7f27126e | 12084 | |
304603f4 ACO |
12085 | pipe_config->base.enable = true; |
12086 | ||
db7542dd ACO |
12087 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
12088 | "[modeset]"); | |
12089 | } | |
12090 | ||
12091 | return intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));; | |
7f27126e JB |
12092 | } |
12093 | ||
225da59b | 12094 | static int __intel_set_mode_setup_plls(struct drm_atomic_state *state, |
ed6739ef ACO |
12095 | unsigned modeset_pipes, |
12096 | unsigned disable_pipes) | |
12097 | { | |
225da59b | 12098 | struct drm_device *dev = state->dev; |
ed6739ef ACO |
12099 | struct drm_i915_private *dev_priv = to_i915(dev); |
12100 | unsigned clear_pipes = modeset_pipes | disable_pipes; | |
12101 | struct intel_crtc *intel_crtc; | |
12102 | int ret = 0; | |
12103 | ||
12104 | if (!dev_priv->display.crtc_compute_clock) | |
12105 | return 0; | |
12106 | ||
12107 | ret = intel_shared_dpll_start_config(dev_priv, clear_pipes); | |
12108 | if (ret) | |
12109 | goto done; | |
12110 | ||
12111 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { | |
225da59b ACO |
12112 | struct intel_crtc_state *crtc_state = |
12113 | intel_atomic_get_crtc_state(state, intel_crtc); | |
12114 | ||
12115 | /* Modeset pipes should have a new state by now */ | |
12116 | if (WARN_ON(IS_ERR(crtc_state))) | |
12117 | continue; | |
12118 | ||
ed6739ef | 12119 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, |
225da59b | 12120 | crtc_state); |
ed6739ef ACO |
12121 | if (ret) { |
12122 | intel_shared_dpll_abort_config(dev_priv); | |
12123 | goto done; | |
12124 | } | |
12125 | } | |
12126 | ||
12127 | done: | |
12128 | return ret; | |
12129 | } | |
12130 | ||
f30da187 DV |
12131 | static int __intel_set_mode(struct drm_crtc *crtc, |
12132 | struct drm_display_mode *mode, | |
7f27126e | 12133 | int x, int y, struct drm_framebuffer *fb, |
5cec258b | 12134 | struct intel_crtc_state *pipe_config, |
7f27126e JB |
12135 | unsigned modeset_pipes, |
12136 | unsigned prepare_pipes, | |
12137 | unsigned disable_pipes) | |
a6778b3c DV |
12138 | { |
12139 | struct drm_device *dev = crtc->dev; | |
fbee40df | 12140 | struct drm_i915_private *dev_priv = dev->dev_private; |
4b4b9238 | 12141 | struct drm_display_mode *saved_mode; |
304603f4 | 12142 | struct drm_atomic_state *state = pipe_config->base.state; |
83a57153 | 12143 | struct intel_crtc_state *crtc_state_copy = NULL; |
25c5b266 | 12144 | struct intel_crtc *intel_crtc; |
c0c36b94 | 12145 | int ret = 0; |
a6778b3c | 12146 | |
4b4b9238 | 12147 | saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL); |
c0c36b94 CW |
12148 | if (!saved_mode) |
12149 | return -ENOMEM; | |
a6778b3c | 12150 | |
83a57153 ACO |
12151 | crtc_state_copy = kmalloc(sizeof(*crtc_state_copy), GFP_KERNEL); |
12152 | if (!crtc_state_copy) { | |
12153 | ret = -ENOMEM; | |
12154 | goto done; | |
12155 | } | |
12156 | ||
3ac18232 | 12157 | *saved_mode = crtc->mode; |
a6778b3c | 12158 | |
30a970c6 JB |
12159 | /* |
12160 | * See if the config requires any additional preparation, e.g. | |
12161 | * to adjust global state with pipes off. We need to do this | |
12162 | * here so we can get the modeset_pipe updated config for the new | |
12163 | * mode set on this crtc. For other crtcs we need to use the | |
12164 | * adjusted_mode bits in the crtc directly. | |
12165 | */ | |
f8437dd1 | 12166 | if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) { |
304603f4 ACO |
12167 | ret = valleyview_modeset_global_pipes(state, &prepare_pipes); |
12168 | if (ret) | |
12169 | goto done; | |
30a970c6 | 12170 | |
c164f833 VS |
12171 | /* may have added more to prepare_pipes than we should */ |
12172 | prepare_pipes &= ~disable_pipes; | |
12173 | } | |
12174 | ||
225da59b | 12175 | ret = __intel_set_mode_setup_plls(state, modeset_pipes, disable_pipes); |
ed6739ef ACO |
12176 | if (ret) |
12177 | goto done; | |
8bd31e67 | 12178 | |
460da916 DV |
12179 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
12180 | intel_crtc_disable(&intel_crtc->base); | |
12181 | ||
ea9d758d | 12182 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
83d65738 | 12183 | if (intel_crtc->base.state->enable) |
ea9d758d DV |
12184 | dev_priv->display.crtc_disable(&intel_crtc->base); |
12185 | } | |
a6778b3c | 12186 | |
6c4c86f5 DV |
12187 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
12188 | * to set it here already despite that we pass it down the callchain. | |
7f27126e JB |
12189 | * |
12190 | * Note we'll need to fix this up when we start tracking multiple | |
12191 | * pipes; here we assume a single modeset_pipe and only track the | |
12192 | * single crtc and mode. | |
f6e5b160 | 12193 | */ |
b8cecdf5 | 12194 | if (modeset_pipes) { |
25c5b266 | 12195 | crtc->mode = *mode; |
b8cecdf5 DV |
12196 | /* mode_set/enable/disable functions rely on a correct pipe |
12197 | * config. */ | |
f5de6e07 | 12198 | intel_crtc_set_state(to_intel_crtc(crtc), pipe_config); |
c326c0a9 VS |
12199 | |
12200 | /* | |
12201 | * Calculate and store various constants which | |
12202 | * are later needed by vblank and swap-completion | |
12203 | * timestamping. They are derived from true hwmode. | |
12204 | */ | |
12205 | drm_calc_timestamping_constants(crtc, | |
2d112de7 | 12206 | &pipe_config->base.adjusted_mode); |
b8cecdf5 | 12207 | } |
7758a113 | 12208 | |
ea9d758d DV |
12209 | /* Only after disabling all output pipelines that will be changed can we |
12210 | * update the the output configuration. */ | |
12211 | intel_modeset_update_state(dev, prepare_pipes); | |
f6e5b160 | 12212 | |
304603f4 | 12213 | modeset_update_crtc_power_domains(state); |
47fab737 | 12214 | |
25c5b266 | 12215 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
455a6808 GP |
12216 | struct drm_plane *primary = intel_crtc->base.primary; |
12217 | int vdisplay, hdisplay; | |
4c10794f | 12218 | |
455a6808 | 12219 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); |
70a101f8 MR |
12220 | ret = drm_plane_helper_update(primary, &intel_crtc->base, |
12221 | fb, 0, 0, | |
12222 | hdisplay, vdisplay, | |
12223 | x << 16, y << 16, | |
12224 | hdisplay << 16, vdisplay << 16); | |
a6778b3c DV |
12225 | } |
12226 | ||
12227 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ | |
80715b2f VS |
12228 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
12229 | update_scanline_offset(intel_crtc); | |
12230 | ||
25c5b266 | 12231 | dev_priv->display.crtc_enable(&intel_crtc->base); |
80715b2f | 12232 | } |
a6778b3c | 12233 | |
a6778b3c DV |
12234 | /* FIXME: add subpixel order */ |
12235 | done: | |
83d65738 | 12236 | if (ret && crtc->state->enable) |
3ac18232 | 12237 | crtc->mode = *saved_mode; |
a6778b3c | 12238 | |
83a57153 ACO |
12239 | if (ret == 0 && pipe_config) { |
12240 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12241 | ||
12242 | /* The pipe_config will be freed with the atomic state, so | |
12243 | * make a copy. */ | |
12244 | memcpy(crtc_state_copy, intel_crtc->config, | |
12245 | sizeof *crtc_state_copy); | |
12246 | intel_crtc->config = crtc_state_copy; | |
12247 | intel_crtc->base.state = &crtc_state_copy->base; | |
83a57153 ACO |
12248 | } else { |
12249 | kfree(crtc_state_copy); | |
12250 | } | |
12251 | ||
3ac18232 | 12252 | kfree(saved_mode); |
a6778b3c | 12253 | return ret; |
f6e5b160 CW |
12254 | } |
12255 | ||
7f27126e JB |
12256 | static int intel_set_mode_pipes(struct drm_crtc *crtc, |
12257 | struct drm_display_mode *mode, | |
12258 | int x, int y, struct drm_framebuffer *fb, | |
5cec258b | 12259 | struct intel_crtc_state *pipe_config, |
7f27126e JB |
12260 | unsigned modeset_pipes, |
12261 | unsigned prepare_pipes, | |
12262 | unsigned disable_pipes) | |
f30da187 DV |
12263 | { |
12264 | int ret; | |
12265 | ||
7f27126e JB |
12266 | ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes, |
12267 | prepare_pipes, disable_pipes); | |
f30da187 DV |
12268 | |
12269 | if (ret == 0) | |
12270 | intel_modeset_check_state(crtc->dev); | |
12271 | ||
12272 | return ret; | |
12273 | } | |
12274 | ||
7f27126e JB |
12275 | static int intel_set_mode(struct drm_crtc *crtc, |
12276 | struct drm_display_mode *mode, | |
83a57153 ACO |
12277 | int x, int y, struct drm_framebuffer *fb, |
12278 | struct drm_atomic_state *state) | |
7f27126e | 12279 | { |
5cec258b | 12280 | struct intel_crtc_state *pipe_config; |
7f27126e | 12281 | unsigned modeset_pipes, prepare_pipes, disable_pipes; |
83a57153 | 12282 | int ret = 0; |
7f27126e | 12283 | |
83a57153 | 12284 | pipe_config = intel_modeset_compute_config(crtc, mode, fb, state, |
7f27126e JB |
12285 | &modeset_pipes, |
12286 | &prepare_pipes, | |
12287 | &disable_pipes); | |
12288 | ||
83a57153 ACO |
12289 | if (IS_ERR(pipe_config)) { |
12290 | ret = PTR_ERR(pipe_config); | |
12291 | goto out; | |
12292 | } | |
12293 | ||
12294 | ret = intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config, | |
12295 | modeset_pipes, prepare_pipes, | |
12296 | disable_pipes); | |
12297 | if (ret) | |
12298 | goto out; | |
7f27126e | 12299 | |
83a57153 ACO |
12300 | out: |
12301 | return ret; | |
7f27126e JB |
12302 | } |
12303 | ||
c0c36b94 CW |
12304 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
12305 | { | |
83a57153 ACO |
12306 | struct drm_device *dev = crtc->dev; |
12307 | struct drm_atomic_state *state; | |
12308 | struct intel_encoder *encoder; | |
12309 | struct intel_connector *connector; | |
12310 | struct drm_connector_state *connector_state; | |
12311 | ||
12312 | state = drm_atomic_state_alloc(dev); | |
12313 | if (!state) { | |
12314 | DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory", | |
12315 | crtc->base.id); | |
12316 | return; | |
12317 | } | |
12318 | ||
12319 | state->acquire_ctx = dev->mode_config.acquire_ctx; | |
12320 | ||
12321 | /* The force restore path in the HW readout code relies on the staged | |
12322 | * config still keeping the user requested config while the actual | |
12323 | * state has been overwritten by the configuration read from HW. We | |
12324 | * need to copy the staged config to the atomic state, otherwise the | |
12325 | * mode set will just reapply the state the HW is already in. */ | |
12326 | for_each_intel_encoder(dev, encoder) { | |
12327 | if (&encoder->new_crtc->base != crtc) | |
12328 | continue; | |
12329 | ||
12330 | for_each_intel_connector(dev, connector) { | |
12331 | if (connector->new_encoder != encoder) | |
12332 | continue; | |
12333 | ||
12334 | connector_state = drm_atomic_get_connector_state(state, &connector->base); | |
12335 | if (IS_ERR(connector_state)) { | |
12336 | DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n", | |
12337 | connector->base.base.id, | |
12338 | connector->base.name, | |
12339 | PTR_ERR(connector_state)); | |
12340 | continue; | |
12341 | } | |
12342 | ||
12343 | connector_state->crtc = crtc; | |
12344 | connector_state->best_encoder = &encoder->base; | |
12345 | } | |
12346 | } | |
12347 | ||
12348 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb, | |
12349 | state); | |
12350 | ||
12351 | drm_atomic_state_free(state); | |
c0c36b94 CW |
12352 | } |
12353 | ||
25c5b266 DV |
12354 | #undef for_each_intel_crtc_masked |
12355 | ||
d9e55608 DV |
12356 | static void intel_set_config_free(struct intel_set_config *config) |
12357 | { | |
12358 | if (!config) | |
12359 | return; | |
12360 | ||
1aa4b628 DV |
12361 | kfree(config->save_connector_encoders); |
12362 | kfree(config->save_encoder_crtcs); | |
7668851f | 12363 | kfree(config->save_crtc_enabled); |
d9e55608 DV |
12364 | kfree(config); |
12365 | } | |
12366 | ||
85f9eb71 DV |
12367 | static int intel_set_config_save_state(struct drm_device *dev, |
12368 | struct intel_set_config *config) | |
12369 | { | |
7668851f | 12370 | struct drm_crtc *crtc; |
85f9eb71 DV |
12371 | struct drm_encoder *encoder; |
12372 | struct drm_connector *connector; | |
12373 | int count; | |
12374 | ||
7668851f VS |
12375 | config->save_crtc_enabled = |
12376 | kcalloc(dev->mode_config.num_crtc, | |
12377 | sizeof(bool), GFP_KERNEL); | |
12378 | if (!config->save_crtc_enabled) | |
12379 | return -ENOMEM; | |
12380 | ||
1aa4b628 DV |
12381 | config->save_encoder_crtcs = |
12382 | kcalloc(dev->mode_config.num_encoder, | |
12383 | sizeof(struct drm_crtc *), GFP_KERNEL); | |
12384 | if (!config->save_encoder_crtcs) | |
85f9eb71 DV |
12385 | return -ENOMEM; |
12386 | ||
1aa4b628 DV |
12387 | config->save_connector_encoders = |
12388 | kcalloc(dev->mode_config.num_connector, | |
12389 | sizeof(struct drm_encoder *), GFP_KERNEL); | |
12390 | if (!config->save_connector_encoders) | |
85f9eb71 DV |
12391 | return -ENOMEM; |
12392 | ||
12393 | /* Copy data. Note that driver private data is not affected. | |
12394 | * Should anything bad happen only the expected state is | |
12395 | * restored, not the drivers personal bookkeeping. | |
12396 | */ | |
7668851f | 12397 | count = 0; |
70e1e0ec | 12398 | for_each_crtc(dev, crtc) { |
83d65738 | 12399 | config->save_crtc_enabled[count++] = crtc->state->enable; |
7668851f VS |
12400 | } |
12401 | ||
85f9eb71 DV |
12402 | count = 0; |
12403 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
1aa4b628 | 12404 | config->save_encoder_crtcs[count++] = encoder->crtc; |
85f9eb71 DV |
12405 | } |
12406 | ||
12407 | count = 0; | |
12408 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1aa4b628 | 12409 | config->save_connector_encoders[count++] = connector->encoder; |
85f9eb71 DV |
12410 | } |
12411 | ||
12412 | return 0; | |
12413 | } | |
12414 | ||
12415 | static void intel_set_config_restore_state(struct drm_device *dev, | |
12416 | struct intel_set_config *config) | |
12417 | { | |
7668851f | 12418 | struct intel_crtc *crtc; |
9a935856 DV |
12419 | struct intel_encoder *encoder; |
12420 | struct intel_connector *connector; | |
85f9eb71 DV |
12421 | int count; |
12422 | ||
7668851f | 12423 | count = 0; |
d3fcc808 | 12424 | for_each_intel_crtc(dev, crtc) { |
7668851f VS |
12425 | crtc->new_enabled = config->save_crtc_enabled[count++]; |
12426 | } | |
12427 | ||
85f9eb71 | 12428 | count = 0; |
b2784e15 | 12429 | for_each_intel_encoder(dev, encoder) { |
9a935856 DV |
12430 | encoder->new_crtc = |
12431 | to_intel_crtc(config->save_encoder_crtcs[count++]); | |
85f9eb71 DV |
12432 | } |
12433 | ||
12434 | count = 0; | |
3a3371ff | 12435 | for_each_intel_connector(dev, connector) { |
9a935856 DV |
12436 | connector->new_encoder = |
12437 | to_intel_encoder(config->save_connector_encoders[count++]); | |
85f9eb71 DV |
12438 | } |
12439 | } | |
12440 | ||
e3de42b6 | 12441 | static bool |
2e57f47d | 12442 | is_crtc_connector_off(struct drm_mode_set *set) |
e3de42b6 ID |
12443 | { |
12444 | int i; | |
12445 | ||
2e57f47d CW |
12446 | if (set->num_connectors == 0) |
12447 | return false; | |
12448 | ||
12449 | if (WARN_ON(set->connectors == NULL)) | |
12450 | return false; | |
12451 | ||
12452 | for (i = 0; i < set->num_connectors; i++) | |
12453 | if (set->connectors[i]->encoder && | |
12454 | set->connectors[i]->encoder->crtc == set->crtc && | |
12455 | set->connectors[i]->dpms != DRM_MODE_DPMS_ON) | |
e3de42b6 ID |
12456 | return true; |
12457 | ||
12458 | return false; | |
12459 | } | |
12460 | ||
5e2b584e DV |
12461 | static void |
12462 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, | |
12463 | struct intel_set_config *config) | |
12464 | { | |
12465 | ||
12466 | /* We should be able to check here if the fb has the same properties | |
12467 | * and then just flip_or_move it */ | |
2e57f47d CW |
12468 | if (is_crtc_connector_off(set)) { |
12469 | config->mode_changed = true; | |
f4510a27 | 12470 | } else if (set->crtc->primary->fb != set->fb) { |
3b150f08 MR |
12471 | /* |
12472 | * If we have no fb, we can only flip as long as the crtc is | |
12473 | * active, otherwise we need a full mode set. The crtc may | |
12474 | * be active if we've only disabled the primary plane, or | |
12475 | * in fastboot situations. | |
12476 | */ | |
f4510a27 | 12477 | if (set->crtc->primary->fb == NULL) { |
319d9827 JB |
12478 | struct intel_crtc *intel_crtc = |
12479 | to_intel_crtc(set->crtc); | |
12480 | ||
3b150f08 | 12481 | if (intel_crtc->active) { |
319d9827 JB |
12482 | DRM_DEBUG_KMS("crtc has no fb, will flip\n"); |
12483 | config->fb_changed = true; | |
12484 | } else { | |
12485 | DRM_DEBUG_KMS("inactive crtc, full mode set\n"); | |
12486 | config->mode_changed = true; | |
12487 | } | |
5e2b584e DV |
12488 | } else if (set->fb == NULL) { |
12489 | config->mode_changed = true; | |
72f4901e | 12490 | } else if (set->fb->pixel_format != |
f4510a27 | 12491 | set->crtc->primary->fb->pixel_format) { |
5e2b584e | 12492 | config->mode_changed = true; |
e3de42b6 | 12493 | } else { |
5e2b584e | 12494 | config->fb_changed = true; |
e3de42b6 | 12495 | } |
5e2b584e DV |
12496 | } |
12497 | ||
835c5873 | 12498 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
5e2b584e DV |
12499 | config->fb_changed = true; |
12500 | ||
12501 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { | |
12502 | DRM_DEBUG_KMS("modes are different, full mode set\n"); | |
12503 | drm_mode_debug_printmodeline(&set->crtc->mode); | |
12504 | drm_mode_debug_printmodeline(set->mode); | |
12505 | config->mode_changed = true; | |
12506 | } | |
a1d95703 CW |
12507 | |
12508 | DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n", | |
12509 | set->crtc->base.id, config->mode_changed, config->fb_changed); | |
5e2b584e DV |
12510 | } |
12511 | ||
2e431051 | 12512 | static int |
9a935856 DV |
12513 | intel_modeset_stage_output_state(struct drm_device *dev, |
12514 | struct drm_mode_set *set, | |
944b0c76 ACO |
12515 | struct intel_set_config *config, |
12516 | struct drm_atomic_state *state) | |
50f56119 | 12517 | { |
9a935856 | 12518 | struct intel_connector *connector; |
944b0c76 | 12519 | struct drm_connector_state *connector_state; |
9a935856 | 12520 | struct intel_encoder *encoder; |
7668851f | 12521 | struct intel_crtc *crtc; |
f3f08572 | 12522 | int ro; |
50f56119 | 12523 | |
9abdda74 | 12524 | /* The upper layers ensure that we either disable a crtc or have a list |
9a935856 DV |
12525 | * of connectors. For paranoia, double-check this. */ |
12526 | WARN_ON(!set->fb && (set->num_connectors != 0)); | |
12527 | WARN_ON(set->fb && (set->num_connectors == 0)); | |
12528 | ||
3a3371ff | 12529 | for_each_intel_connector(dev, connector) { |
9a935856 DV |
12530 | /* Otherwise traverse passed in connector list and get encoders |
12531 | * for them. */ | |
50f56119 | 12532 | for (ro = 0; ro < set->num_connectors; ro++) { |
9a935856 | 12533 | if (set->connectors[ro] == &connector->base) { |
0e32b39c | 12534 | connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe); |
50f56119 DV |
12535 | break; |
12536 | } | |
12537 | } | |
12538 | ||
9a935856 DV |
12539 | /* If we disable the crtc, disable all its connectors. Also, if |
12540 | * the connector is on the changing crtc but not on the new | |
12541 | * connector list, disable it. */ | |
12542 | if ((!set->fb || ro == set->num_connectors) && | |
12543 | connector->base.encoder && | |
12544 | connector->base.encoder->crtc == set->crtc) { | |
12545 | connector->new_encoder = NULL; | |
12546 | ||
12547 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", | |
12548 | connector->base.base.id, | |
c23cc417 | 12549 | connector->base.name); |
9a935856 DV |
12550 | } |
12551 | ||
12552 | ||
12553 | if (&connector->new_encoder->base != connector->base.encoder) { | |
10634189 ACO |
12554 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n", |
12555 | connector->base.base.id, | |
12556 | connector->base.name); | |
5e2b584e | 12557 | config->mode_changed = true; |
50f56119 DV |
12558 | } |
12559 | } | |
9a935856 | 12560 | /* connector->new_encoder is now updated for all connectors. */ |
50f56119 | 12561 | |
9a935856 | 12562 | /* Update crtc of enabled connectors. */ |
3a3371ff | 12563 | for_each_intel_connector(dev, connector) { |
7668851f VS |
12564 | struct drm_crtc *new_crtc; |
12565 | ||
9a935856 | 12566 | if (!connector->new_encoder) |
50f56119 DV |
12567 | continue; |
12568 | ||
9a935856 | 12569 | new_crtc = connector->new_encoder->base.crtc; |
50f56119 DV |
12570 | |
12571 | for (ro = 0; ro < set->num_connectors; ro++) { | |
9a935856 | 12572 | if (set->connectors[ro] == &connector->base) |
50f56119 DV |
12573 | new_crtc = set->crtc; |
12574 | } | |
12575 | ||
12576 | /* Make sure the new CRTC will work with the encoder */ | |
14509916 TR |
12577 | if (!drm_encoder_crtc_ok(&connector->new_encoder->base, |
12578 | new_crtc)) { | |
5e2b584e | 12579 | return -EINVAL; |
50f56119 | 12580 | } |
0e32b39c | 12581 | connector->new_encoder->new_crtc = to_intel_crtc(new_crtc); |
9a935856 | 12582 | |
944b0c76 ACO |
12583 | connector_state = |
12584 | drm_atomic_get_connector_state(state, &connector->base); | |
12585 | if (IS_ERR(connector_state)) | |
12586 | return PTR_ERR(connector_state); | |
12587 | ||
12588 | connector_state->crtc = new_crtc; | |
12589 | connector_state->best_encoder = &connector->new_encoder->base; | |
12590 | ||
9a935856 DV |
12591 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", |
12592 | connector->base.base.id, | |
c23cc417 | 12593 | connector->base.name, |
9a935856 DV |
12594 | new_crtc->base.id); |
12595 | } | |
12596 | ||
12597 | /* Check for any encoders that needs to be disabled. */ | |
b2784e15 | 12598 | for_each_intel_encoder(dev, encoder) { |
5a65f358 | 12599 | int num_connectors = 0; |
3a3371ff | 12600 | for_each_intel_connector(dev, connector) { |
9a935856 DV |
12601 | if (connector->new_encoder == encoder) { |
12602 | WARN_ON(!connector->new_encoder->new_crtc); | |
5a65f358 | 12603 | num_connectors++; |
9a935856 DV |
12604 | } |
12605 | } | |
5a65f358 PZ |
12606 | |
12607 | if (num_connectors == 0) | |
12608 | encoder->new_crtc = NULL; | |
12609 | else if (num_connectors > 1) | |
12610 | return -EINVAL; | |
12611 | ||
9a935856 DV |
12612 | /* Only now check for crtc changes so we don't miss encoders |
12613 | * that will be disabled. */ | |
12614 | if (&encoder->new_crtc->base != encoder->base.crtc) { | |
10634189 ACO |
12615 | DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n", |
12616 | encoder->base.base.id, | |
12617 | encoder->base.name); | |
5e2b584e | 12618 | config->mode_changed = true; |
50f56119 DV |
12619 | } |
12620 | } | |
9a935856 | 12621 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
3a3371ff | 12622 | for_each_intel_connector(dev, connector) { |
944b0c76 ACO |
12623 | connector_state = |
12624 | drm_atomic_get_connector_state(state, &connector->base); | |
9d918c15 ACO |
12625 | if (IS_ERR(connector_state)) |
12626 | return PTR_ERR(connector_state); | |
944b0c76 ACO |
12627 | |
12628 | if (connector->new_encoder) { | |
0e32b39c DA |
12629 | if (connector->new_encoder != connector->encoder) |
12630 | connector->encoder = connector->new_encoder; | |
944b0c76 ACO |
12631 | } else { |
12632 | connector_state->crtc = NULL; | |
f61cccf3 | 12633 | connector_state->best_encoder = NULL; |
944b0c76 | 12634 | } |
0e32b39c | 12635 | } |
d3fcc808 | 12636 | for_each_intel_crtc(dev, crtc) { |
7668851f VS |
12637 | crtc->new_enabled = false; |
12638 | ||
b2784e15 | 12639 | for_each_intel_encoder(dev, encoder) { |
7668851f VS |
12640 | if (encoder->new_crtc == crtc) { |
12641 | crtc->new_enabled = true; | |
12642 | break; | |
12643 | } | |
12644 | } | |
12645 | ||
83d65738 | 12646 | if (crtc->new_enabled != crtc->base.state->enable) { |
10634189 ACO |
12647 | DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n", |
12648 | crtc->base.base.id, | |
7668851f VS |
12649 | crtc->new_enabled ? "en" : "dis"); |
12650 | config->mode_changed = true; | |
12651 | } | |
12652 | } | |
12653 | ||
2e431051 DV |
12654 | return 0; |
12655 | } | |
12656 | ||
7d00a1f5 VS |
12657 | static void disable_crtc_nofb(struct intel_crtc *crtc) |
12658 | { | |
12659 | struct drm_device *dev = crtc->base.dev; | |
12660 | struct intel_encoder *encoder; | |
12661 | struct intel_connector *connector; | |
12662 | ||
12663 | DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n", | |
12664 | pipe_name(crtc->pipe)); | |
12665 | ||
3a3371ff | 12666 | for_each_intel_connector(dev, connector) { |
7d00a1f5 VS |
12667 | if (connector->new_encoder && |
12668 | connector->new_encoder->new_crtc == crtc) | |
12669 | connector->new_encoder = NULL; | |
12670 | } | |
12671 | ||
b2784e15 | 12672 | for_each_intel_encoder(dev, encoder) { |
7d00a1f5 VS |
12673 | if (encoder->new_crtc == crtc) |
12674 | encoder->new_crtc = NULL; | |
12675 | } | |
12676 | ||
12677 | crtc->new_enabled = false; | |
12678 | } | |
12679 | ||
2e431051 DV |
12680 | static int intel_crtc_set_config(struct drm_mode_set *set) |
12681 | { | |
12682 | struct drm_device *dev; | |
2e431051 | 12683 | struct drm_mode_set save_set; |
83a57153 | 12684 | struct drm_atomic_state *state = NULL; |
2e431051 | 12685 | struct intel_set_config *config; |
5cec258b | 12686 | struct intel_crtc_state *pipe_config; |
50f52756 | 12687 | unsigned modeset_pipes, prepare_pipes, disable_pipes; |
2e431051 | 12688 | int ret; |
2e431051 | 12689 | |
8d3e375e DV |
12690 | BUG_ON(!set); |
12691 | BUG_ON(!set->crtc); | |
12692 | BUG_ON(!set->crtc->helper_private); | |
2e431051 | 12693 | |
7e53f3a4 DV |
12694 | /* Enforce sane interface api - has been abused by the fb helper. */ |
12695 | BUG_ON(!set->mode && set->fb); | |
12696 | BUG_ON(set->fb && set->num_connectors == 0); | |
431e50f7 | 12697 | |
2e431051 DV |
12698 | if (set->fb) { |
12699 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", | |
12700 | set->crtc->base.id, set->fb->base.id, | |
12701 | (int)set->num_connectors, set->x, set->y); | |
12702 | } else { | |
12703 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); | |
2e431051 DV |
12704 | } |
12705 | ||
12706 | dev = set->crtc->dev; | |
12707 | ||
12708 | ret = -ENOMEM; | |
12709 | config = kzalloc(sizeof(*config), GFP_KERNEL); | |
12710 | if (!config) | |
12711 | goto out_config; | |
12712 | ||
12713 | ret = intel_set_config_save_state(dev, config); | |
12714 | if (ret) | |
12715 | goto out_config; | |
12716 | ||
12717 | save_set.crtc = set->crtc; | |
12718 | save_set.mode = &set->crtc->mode; | |
12719 | save_set.x = set->crtc->x; | |
12720 | save_set.y = set->crtc->y; | |
f4510a27 | 12721 | save_set.fb = set->crtc->primary->fb; |
2e431051 DV |
12722 | |
12723 | /* Compute whether we need a full modeset, only an fb base update or no | |
12724 | * change at all. In the future we might also check whether only the | |
12725 | * mode changed, e.g. for LVDS where we only change the panel fitter in | |
12726 | * such cases. */ | |
12727 | intel_set_config_compute_mode_changes(set, config); | |
12728 | ||
83a57153 ACO |
12729 | state = drm_atomic_state_alloc(dev); |
12730 | if (!state) { | |
12731 | ret = -ENOMEM; | |
12732 | goto out_config; | |
12733 | } | |
12734 | ||
12735 | state->acquire_ctx = dev->mode_config.acquire_ctx; | |
12736 | ||
944b0c76 | 12737 | ret = intel_modeset_stage_output_state(dev, set, config, state); |
2e431051 DV |
12738 | if (ret) |
12739 | goto fail; | |
12740 | ||
50f52756 | 12741 | pipe_config = intel_modeset_compute_config(set->crtc, set->mode, |
83a57153 | 12742 | set->fb, state, |
50f52756 JB |
12743 | &modeset_pipes, |
12744 | &prepare_pipes, | |
12745 | &disable_pipes); | |
20664591 | 12746 | if (IS_ERR(pipe_config)) { |
6ac0483b | 12747 | ret = PTR_ERR(pipe_config); |
50f52756 | 12748 | goto fail; |
20664591 | 12749 | } else if (pipe_config) { |
b9950a13 | 12750 | if (pipe_config->has_audio != |
6e3c9717 | 12751 | to_intel_crtc(set->crtc)->config->has_audio) |
20664591 JB |
12752 | config->mode_changed = true; |
12753 | ||
af15d2ce JB |
12754 | /* |
12755 | * Note we have an issue here with infoframes: current code | |
12756 | * only updates them on the full mode set path per hw | |
12757 | * requirements. So here we should be checking for any | |
12758 | * required changes and forcing a mode set. | |
12759 | */ | |
20664591 | 12760 | } |
50f52756 | 12761 | |
1f9954d0 JB |
12762 | intel_update_pipe_size(to_intel_crtc(set->crtc)); |
12763 | ||
5e2b584e | 12764 | if (config->mode_changed) { |
50f52756 JB |
12765 | ret = intel_set_mode_pipes(set->crtc, set->mode, |
12766 | set->x, set->y, set->fb, pipe_config, | |
12767 | modeset_pipes, prepare_pipes, | |
12768 | disable_pipes); | |
5e2b584e | 12769 | } else if (config->fb_changed) { |
3b150f08 | 12770 | struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc); |
455a6808 GP |
12771 | struct drm_plane *primary = set->crtc->primary; |
12772 | int vdisplay, hdisplay; | |
3b150f08 | 12773 | |
455a6808 | 12774 | drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay); |
70a101f8 MR |
12775 | ret = drm_plane_helper_update(primary, set->crtc, set->fb, |
12776 | 0, 0, hdisplay, vdisplay, | |
12777 | set->x << 16, set->y << 16, | |
12778 | hdisplay << 16, vdisplay << 16); | |
3b150f08 MR |
12779 | |
12780 | /* | |
12781 | * We need to make sure the primary plane is re-enabled if it | |
12782 | * has previously been turned off. | |
12783 | */ | |
12784 | if (!intel_crtc->primary_enabled && ret == 0) { | |
12785 | WARN_ON(!intel_crtc->active); | |
fdd508a6 | 12786 | intel_enable_primary_hw_plane(set->crtc->primary, set->crtc); |
3b150f08 MR |
12787 | } |
12788 | ||
7ca51a3a JB |
12789 | /* |
12790 | * In the fastboot case this may be our only check of the | |
12791 | * state after boot. It would be better to only do it on | |
12792 | * the first update, but we don't have a nice way of doing that | |
12793 | * (and really, set_config isn't used much for high freq page | |
12794 | * flipping, so increasing its cost here shouldn't be a big | |
12795 | * deal). | |
12796 | */ | |
d330a953 | 12797 | if (i915.fastboot && ret == 0) |
7ca51a3a | 12798 | intel_modeset_check_state(set->crtc->dev); |
50f56119 DV |
12799 | } |
12800 | ||
2d05eae1 | 12801 | if (ret) { |
bf67dfeb DV |
12802 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
12803 | set->crtc->base.id, ret); | |
50f56119 | 12804 | fail: |
2d05eae1 | 12805 | intel_set_config_restore_state(dev, config); |
50f56119 | 12806 | |
83a57153 ACO |
12807 | drm_atomic_state_clear(state); |
12808 | ||
7d00a1f5 VS |
12809 | /* |
12810 | * HACK: if the pipe was on, but we didn't have a framebuffer, | |
12811 | * force the pipe off to avoid oopsing in the modeset code | |
12812 | * due to fb==NULL. This should only happen during boot since | |
12813 | * we don't yet reconstruct the FB from the hardware state. | |
12814 | */ | |
12815 | if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb) | |
12816 | disable_crtc_nofb(to_intel_crtc(save_set.crtc)); | |
12817 | ||
2d05eae1 CW |
12818 | /* Try to restore the config */ |
12819 | if (config->mode_changed && | |
12820 | intel_set_mode(save_set.crtc, save_set.mode, | |
83a57153 ACO |
12821 | save_set.x, save_set.y, save_set.fb, |
12822 | state)) | |
2d05eae1 CW |
12823 | DRM_ERROR("failed to restore config after modeset failure\n"); |
12824 | } | |
50f56119 | 12825 | |
d9e55608 | 12826 | out_config: |
83a57153 ACO |
12827 | if (state) |
12828 | drm_atomic_state_free(state); | |
12829 | ||
d9e55608 | 12830 | intel_set_config_free(config); |
50f56119 DV |
12831 | return ret; |
12832 | } | |
f6e5b160 CW |
12833 | |
12834 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
f6e5b160 | 12835 | .gamma_set = intel_crtc_gamma_set, |
50f56119 | 12836 | .set_config = intel_crtc_set_config, |
f6e5b160 CW |
12837 | .destroy = intel_crtc_destroy, |
12838 | .page_flip = intel_crtc_page_flip, | |
1356837e MR |
12839 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
12840 | .atomic_destroy_state = intel_crtc_destroy_state, | |
f6e5b160 CW |
12841 | }; |
12842 | ||
5358901f DV |
12843 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
12844 | struct intel_shared_dpll *pll, | |
12845 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 12846 | { |
5358901f | 12847 | uint32_t val; |
ee7b9f93 | 12848 | |
f458ebbc | 12849 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
bd2bb1b9 PZ |
12850 | return false; |
12851 | ||
5358901f | 12852 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
12853 | hw_state->dpll = val; |
12854 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
12855 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
12856 | |
12857 | return val & DPLL_VCO_ENABLE; | |
12858 | } | |
12859 | ||
15bdd4cf DV |
12860 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
12861 | struct intel_shared_dpll *pll) | |
12862 | { | |
3e369b76 ACO |
12863 | I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0); |
12864 | I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1); | |
15bdd4cf DV |
12865 | } |
12866 | ||
e7b903d2 DV |
12867 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
12868 | struct intel_shared_dpll *pll) | |
12869 | { | |
e7b903d2 | 12870 | /* PCH refclock must be enabled first */ |
89eff4be | 12871 | ibx_assert_pch_refclk_enabled(dev_priv); |
e7b903d2 | 12872 | |
3e369b76 | 12873 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf DV |
12874 | |
12875 | /* Wait for the clocks to stabilize. */ | |
12876 | POSTING_READ(PCH_DPLL(pll->id)); | |
12877 | udelay(150); | |
12878 | ||
12879 | /* The pixel multiplier can only be updated once the | |
12880 | * DPLL is enabled and the clocks are stable. | |
12881 | * | |
12882 | * So write it again. | |
12883 | */ | |
3e369b76 | 12884 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf | 12885 | POSTING_READ(PCH_DPLL(pll->id)); |
e7b903d2 DV |
12886 | udelay(200); |
12887 | } | |
12888 | ||
12889 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
12890 | struct intel_shared_dpll *pll) | |
12891 | { | |
12892 | struct drm_device *dev = dev_priv->dev; | |
12893 | struct intel_crtc *crtc; | |
e7b903d2 DV |
12894 | |
12895 | /* Make sure no transcoder isn't still depending on us. */ | |
d3fcc808 | 12896 | for_each_intel_crtc(dev, crtc) { |
e7b903d2 DV |
12897 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
12898 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
12899 | } |
12900 | ||
15bdd4cf DV |
12901 | I915_WRITE(PCH_DPLL(pll->id), 0); |
12902 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
12903 | udelay(200); |
12904 | } | |
12905 | ||
46edb027 DV |
12906 | static char *ibx_pch_dpll_names[] = { |
12907 | "PCH DPLL A", | |
12908 | "PCH DPLL B", | |
12909 | }; | |
12910 | ||
7c74ade1 | 12911 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 12912 | { |
e7b903d2 | 12913 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
12914 | int i; |
12915 | ||
7c74ade1 | 12916 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 12917 | |
e72f9fbf | 12918 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
12919 | dev_priv->shared_dplls[i].id = i; |
12920 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 12921 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
12922 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
12923 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
12924 | dev_priv->shared_dplls[i].get_hw_state = |
12925 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
12926 | } |
12927 | } | |
12928 | ||
7c74ade1 DV |
12929 | static void intel_shared_dpll_init(struct drm_device *dev) |
12930 | { | |
e7b903d2 | 12931 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 | 12932 | |
9cd86933 DV |
12933 | if (HAS_DDI(dev)) |
12934 | intel_ddi_pll_init(dev); | |
12935 | else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
7c74ade1 DV |
12936 | ibx_pch_dpll_init(dev); |
12937 | else | |
12938 | dev_priv->num_shared_dpll = 0; | |
12939 | ||
12940 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
7c74ade1 DV |
12941 | } |
12942 | ||
1fc0a8f7 TU |
12943 | /** |
12944 | * intel_wm_need_update - Check whether watermarks need updating | |
12945 | * @plane: drm plane | |
12946 | * @state: new plane state | |
12947 | * | |
12948 | * Check current plane state versus the new one to determine whether | |
12949 | * watermarks need to be recalculated. | |
12950 | * | |
12951 | * Returns true or false. | |
12952 | */ | |
12953 | bool intel_wm_need_update(struct drm_plane *plane, | |
12954 | struct drm_plane_state *state) | |
12955 | { | |
12956 | /* Update watermarks on tiling changes. */ | |
12957 | if (!plane->state->fb || !state->fb || | |
12958 | plane->state->fb->modifier[0] != state->fb->modifier[0] || | |
12959 | plane->state->rotation != state->rotation) | |
12960 | return true; | |
12961 | ||
12962 | return false; | |
12963 | } | |
12964 | ||
6beb8c23 MR |
12965 | /** |
12966 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
12967 | * @plane: drm plane to prepare for | |
12968 | * @fb: framebuffer to prepare for presentation | |
12969 | * | |
12970 | * Prepares a framebuffer for usage on a display plane. Generally this | |
12971 | * involves pinning the underlying object and updating the frontbuffer tracking | |
12972 | * bits. Some older platforms need special physical address handling for | |
12973 | * cursor planes. | |
12974 | * | |
12975 | * Returns 0 on success, negative error code on failure. | |
12976 | */ | |
12977 | int | |
12978 | intel_prepare_plane_fb(struct drm_plane *plane, | |
d136dfee TU |
12979 | struct drm_framebuffer *fb, |
12980 | const struct drm_plane_state *new_state) | |
465c120c MR |
12981 | { |
12982 | struct drm_device *dev = plane->dev; | |
6beb8c23 MR |
12983 | struct intel_plane *intel_plane = to_intel_plane(plane); |
12984 | enum pipe pipe = intel_plane->pipe; | |
12985 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
12986 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb); | |
12987 | unsigned frontbuffer_bits = 0; | |
12988 | int ret = 0; | |
465c120c | 12989 | |
ea2c67bb | 12990 | if (!obj) |
465c120c MR |
12991 | return 0; |
12992 | ||
6beb8c23 MR |
12993 | switch (plane->type) { |
12994 | case DRM_PLANE_TYPE_PRIMARY: | |
12995 | frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe); | |
12996 | break; | |
12997 | case DRM_PLANE_TYPE_CURSOR: | |
12998 | frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe); | |
12999 | break; | |
13000 | case DRM_PLANE_TYPE_OVERLAY: | |
13001 | frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe); | |
13002 | break; | |
13003 | } | |
465c120c | 13004 | |
6beb8c23 | 13005 | mutex_lock(&dev->struct_mutex); |
465c120c | 13006 | |
6beb8c23 MR |
13007 | if (plane->type == DRM_PLANE_TYPE_CURSOR && |
13008 | INTEL_INFO(dev)->cursor_needs_physical) { | |
13009 | int align = IS_I830(dev) ? 16 * 1024 : 256; | |
13010 | ret = i915_gem_object_attach_phys(obj, align); | |
13011 | if (ret) | |
13012 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
13013 | } else { | |
82bc3b2d | 13014 | ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL); |
6beb8c23 | 13015 | } |
465c120c | 13016 | |
6beb8c23 MR |
13017 | if (ret == 0) |
13018 | i915_gem_track_fb(old_obj, obj, frontbuffer_bits); | |
fdd508a6 | 13019 | |
4c34574f | 13020 | mutex_unlock(&dev->struct_mutex); |
465c120c | 13021 | |
6beb8c23 MR |
13022 | return ret; |
13023 | } | |
13024 | ||
38f3ce3a MR |
13025 | /** |
13026 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
13027 | * @plane: drm plane to clean up for | |
13028 | * @fb: old framebuffer that was on plane | |
13029 | * | |
13030 | * Cleans up a framebuffer that has just been removed from a plane. | |
13031 | */ | |
13032 | void | |
13033 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
d136dfee TU |
13034 | struct drm_framebuffer *fb, |
13035 | const struct drm_plane_state *old_state) | |
38f3ce3a MR |
13036 | { |
13037 | struct drm_device *dev = plane->dev; | |
13038 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
13039 | ||
13040 | if (WARN_ON(!obj)) | |
13041 | return; | |
13042 | ||
13043 | if (plane->type != DRM_PLANE_TYPE_CURSOR || | |
13044 | !INTEL_INFO(dev)->cursor_needs_physical) { | |
13045 | mutex_lock(&dev->struct_mutex); | |
82bc3b2d | 13046 | intel_unpin_fb_obj(fb, old_state); |
38f3ce3a MR |
13047 | mutex_unlock(&dev->struct_mutex); |
13048 | } | |
465c120c MR |
13049 | } |
13050 | ||
13051 | static int | |
3c692a41 GP |
13052 | intel_check_primary_plane(struct drm_plane *plane, |
13053 | struct intel_plane_state *state) | |
13054 | { | |
32b7eeec MR |
13055 | struct drm_device *dev = plane->dev; |
13056 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2b875c22 | 13057 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb | 13058 | struct intel_crtc *intel_crtc; |
2b875c22 | 13059 | struct drm_framebuffer *fb = state->base.fb; |
3c692a41 GP |
13060 | struct drm_rect *dest = &state->dst; |
13061 | struct drm_rect *src = &state->src; | |
13062 | const struct drm_rect *clip = &state->clip; | |
d8106366 | 13063 | bool can_position = false; |
465c120c MR |
13064 | int ret; |
13065 | ||
ea2c67bb MR |
13066 | crtc = crtc ? crtc : plane->crtc; |
13067 | intel_crtc = to_intel_crtc(crtc); | |
13068 | ||
d8106366 SJ |
13069 | if (INTEL_INFO(dev)->gen >= 9) |
13070 | can_position = true; | |
13071 | ||
c59cb179 MR |
13072 | ret = drm_plane_helper_check_update(plane, crtc, fb, |
13073 | src, dest, clip, | |
13074 | DRM_PLANE_HELPER_NO_SCALING, | |
13075 | DRM_PLANE_HELPER_NO_SCALING, | |
d8106366 SJ |
13076 | can_position, true, |
13077 | &state->visible); | |
c59cb179 MR |
13078 | if (ret) |
13079 | return ret; | |
465c120c | 13080 | |
32b7eeec MR |
13081 | if (intel_crtc->active) { |
13082 | intel_crtc->atomic.wait_for_flips = true; | |
13083 | ||
13084 | /* | |
13085 | * FBC does not work on some platforms for rotated | |
13086 | * planes, so disable it when rotation is not 0 and | |
13087 | * update it when rotation is set back to 0. | |
13088 | * | |
13089 | * FIXME: This is redundant with the fbc update done in | |
13090 | * the primary plane enable function except that that | |
13091 | * one is done too late. We eventually need to unify | |
13092 | * this. | |
13093 | */ | |
13094 | if (intel_crtc->primary_enabled && | |
13095 | INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && | |
e35fef21 | 13096 | dev_priv->fbc.crtc == intel_crtc && |
8e7d688b | 13097 | state->base.rotation != BIT(DRM_ROTATE_0)) { |
32b7eeec MR |
13098 | intel_crtc->atomic.disable_fbc = true; |
13099 | } | |
13100 | ||
13101 | if (state->visible) { | |
13102 | /* | |
13103 | * BDW signals flip done immediately if the plane | |
13104 | * is disabled, even if the plane enable is already | |
13105 | * armed to occur at the next vblank :( | |
13106 | */ | |
13107 | if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled) | |
13108 | intel_crtc->atomic.wait_vblank = true; | |
13109 | } | |
13110 | ||
13111 | intel_crtc->atomic.fb_bits |= | |
13112 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe); | |
13113 | ||
13114 | intel_crtc->atomic.update_fbc = true; | |
0fda6568 | 13115 | |
1fc0a8f7 | 13116 | if (intel_wm_need_update(plane, &state->base)) |
0fda6568 | 13117 | intel_crtc->atomic.update_wm = true; |
ccc759dc GP |
13118 | } |
13119 | ||
14af293f GP |
13120 | return 0; |
13121 | } | |
13122 | ||
13123 | static void | |
13124 | intel_commit_primary_plane(struct drm_plane *plane, | |
13125 | struct intel_plane_state *state) | |
13126 | { | |
2b875c22 MR |
13127 | struct drm_crtc *crtc = state->base.crtc; |
13128 | struct drm_framebuffer *fb = state->base.fb; | |
13129 | struct drm_device *dev = plane->dev; | |
14af293f | 13130 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea2c67bb | 13131 | struct intel_crtc *intel_crtc; |
14af293f GP |
13132 | struct drm_rect *src = &state->src; |
13133 | ||
ea2c67bb MR |
13134 | crtc = crtc ? crtc : plane->crtc; |
13135 | intel_crtc = to_intel_crtc(crtc); | |
cf4c7c12 MR |
13136 | |
13137 | plane->fb = fb; | |
9dc806fc MR |
13138 | crtc->x = src->x1 >> 16; |
13139 | crtc->y = src->y1 >> 16; | |
ccc759dc | 13140 | |
ccc759dc | 13141 | if (intel_crtc->active) { |
ccc759dc | 13142 | if (state->visible) { |
ccc759dc GP |
13143 | /* FIXME: kill this fastboot hack */ |
13144 | intel_update_pipe_size(intel_crtc); | |
465c120c | 13145 | |
ccc759dc | 13146 | intel_crtc->primary_enabled = true; |
465c120c | 13147 | |
ccc759dc GP |
13148 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
13149 | crtc->x, crtc->y); | |
ccc759dc GP |
13150 | } else { |
13151 | /* | |
13152 | * If clipping results in a non-visible primary plane, | |
13153 | * we'll disable the primary plane. Note that this is | |
13154 | * a bit different than what happens if userspace | |
13155 | * explicitly disables the plane by passing fb=0 | |
13156 | * because plane->fb still gets set and pinned. | |
13157 | */ | |
13158 | intel_disable_primary_hw_plane(plane, crtc); | |
48404c1e | 13159 | } |
ccc759dc | 13160 | } |
465c120c MR |
13161 | } |
13162 | ||
32b7eeec | 13163 | static void intel_begin_crtc_commit(struct drm_crtc *crtc) |
3c692a41 | 13164 | { |
32b7eeec | 13165 | struct drm_device *dev = crtc->dev; |
140fd38d | 13166 | struct drm_i915_private *dev_priv = dev->dev_private; |
3c692a41 | 13167 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ea2c67bb MR |
13168 | struct intel_plane *intel_plane; |
13169 | struct drm_plane *p; | |
13170 | unsigned fb_bits = 0; | |
13171 | ||
13172 | /* Track fb's for any planes being disabled */ | |
13173 | list_for_each_entry(p, &dev->mode_config.plane_list, head) { | |
13174 | intel_plane = to_intel_plane(p); | |
13175 | ||
13176 | if (intel_crtc->atomic.disabled_planes & | |
13177 | (1 << drm_plane_index(p))) { | |
13178 | switch (p->type) { | |
13179 | case DRM_PLANE_TYPE_PRIMARY: | |
13180 | fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe); | |
13181 | break; | |
13182 | case DRM_PLANE_TYPE_CURSOR: | |
13183 | fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe); | |
13184 | break; | |
13185 | case DRM_PLANE_TYPE_OVERLAY: | |
13186 | fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe); | |
13187 | break; | |
13188 | } | |
3c692a41 | 13189 | |
ea2c67bb MR |
13190 | mutex_lock(&dev->struct_mutex); |
13191 | i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits); | |
13192 | mutex_unlock(&dev->struct_mutex); | |
13193 | } | |
13194 | } | |
3c692a41 | 13195 | |
32b7eeec MR |
13196 | if (intel_crtc->atomic.wait_for_flips) |
13197 | intel_crtc_wait_for_pending_flips(crtc); | |
3c692a41 | 13198 | |
32b7eeec MR |
13199 | if (intel_crtc->atomic.disable_fbc) |
13200 | intel_fbc_disable(dev); | |
3c692a41 | 13201 | |
32b7eeec MR |
13202 | if (intel_crtc->atomic.pre_disable_primary) |
13203 | intel_pre_disable_primary(crtc); | |
3c692a41 | 13204 | |
32b7eeec MR |
13205 | if (intel_crtc->atomic.update_wm) |
13206 | intel_update_watermarks(crtc); | |
3c692a41 | 13207 | |
32b7eeec | 13208 | intel_runtime_pm_get(dev_priv); |
3c692a41 | 13209 | |
c34c9ee4 MR |
13210 | /* Perform vblank evasion around commit operation */ |
13211 | if (intel_crtc->active) | |
13212 | intel_crtc->atomic.evade = | |
13213 | intel_pipe_update_start(intel_crtc, | |
13214 | &intel_crtc->atomic.start_vbl_count); | |
32b7eeec MR |
13215 | } |
13216 | ||
13217 | static void intel_finish_crtc_commit(struct drm_crtc *crtc) | |
13218 | { | |
13219 | struct drm_device *dev = crtc->dev; | |
13220 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13221 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
13222 | struct drm_plane *p; | |
13223 | ||
c34c9ee4 MR |
13224 | if (intel_crtc->atomic.evade) |
13225 | intel_pipe_update_end(intel_crtc, | |
13226 | intel_crtc->atomic.start_vbl_count); | |
3c692a41 | 13227 | |
140fd38d | 13228 | intel_runtime_pm_put(dev_priv); |
3c692a41 | 13229 | |
32b7eeec MR |
13230 | if (intel_crtc->atomic.wait_vblank) |
13231 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
13232 | ||
13233 | intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits); | |
13234 | ||
13235 | if (intel_crtc->atomic.update_fbc) { | |
ccc759dc | 13236 | mutex_lock(&dev->struct_mutex); |
7ff0ebcc | 13237 | intel_fbc_update(dev); |
ccc759dc | 13238 | mutex_unlock(&dev->struct_mutex); |
38f3ce3a | 13239 | } |
3c692a41 | 13240 | |
32b7eeec MR |
13241 | if (intel_crtc->atomic.post_enable_primary) |
13242 | intel_post_enable_primary(crtc); | |
3c692a41 | 13243 | |
32b7eeec MR |
13244 | drm_for_each_legacy_plane(p, &dev->mode_config.plane_list) |
13245 | if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p)) | |
13246 | intel_update_sprite_watermarks(p, crtc, 0, 0, 0, | |
13247 | false, false); | |
13248 | ||
13249 | memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic)); | |
3c692a41 GP |
13250 | } |
13251 | ||
cf4c7c12 | 13252 | /** |
4a3b8769 MR |
13253 | * intel_plane_destroy - destroy a plane |
13254 | * @plane: plane to destroy | |
cf4c7c12 | 13255 | * |
4a3b8769 MR |
13256 | * Common destruction function for all types of planes (primary, cursor, |
13257 | * sprite). | |
cf4c7c12 | 13258 | */ |
4a3b8769 | 13259 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c MR |
13260 | { |
13261 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
13262 | drm_plane_cleanup(plane); | |
13263 | kfree(intel_plane); | |
13264 | } | |
13265 | ||
65a3fea0 | 13266 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
13267 | .update_plane = drm_atomic_helper_update_plane, |
13268 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 13269 | .destroy = intel_plane_destroy, |
c196e1d6 | 13270 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
13271 | .atomic_get_property = intel_plane_atomic_get_property, |
13272 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
13273 | .atomic_duplicate_state = intel_plane_duplicate_state, |
13274 | .atomic_destroy_state = intel_plane_destroy_state, | |
13275 | ||
465c120c MR |
13276 | }; |
13277 | ||
13278 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
13279 | int pipe) | |
13280 | { | |
13281 | struct intel_plane *primary; | |
8e7d688b | 13282 | struct intel_plane_state *state; |
465c120c MR |
13283 | const uint32_t *intel_primary_formats; |
13284 | int num_formats; | |
13285 | ||
13286 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
13287 | if (primary == NULL) | |
13288 | return NULL; | |
13289 | ||
8e7d688b MR |
13290 | state = intel_create_plane_state(&primary->base); |
13291 | if (!state) { | |
ea2c67bb MR |
13292 | kfree(primary); |
13293 | return NULL; | |
13294 | } | |
8e7d688b | 13295 | primary->base.state = &state->base; |
ea2c67bb | 13296 | |
465c120c MR |
13297 | primary->can_scale = false; |
13298 | primary->max_downscale = 1; | |
549e2bfb | 13299 | state->scaler_id = -1; |
465c120c MR |
13300 | primary->pipe = pipe; |
13301 | primary->plane = pipe; | |
c59cb179 MR |
13302 | primary->check_plane = intel_check_primary_plane; |
13303 | primary->commit_plane = intel_commit_primary_plane; | |
08e221fb | 13304 | primary->ckey.flags = I915_SET_COLORKEY_NONE; |
465c120c MR |
13305 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
13306 | primary->plane = !pipe; | |
13307 | ||
13308 | if (INTEL_INFO(dev)->gen <= 3) { | |
13309 | intel_primary_formats = intel_primary_formats_gen2; | |
13310 | num_formats = ARRAY_SIZE(intel_primary_formats_gen2); | |
13311 | } else { | |
13312 | intel_primary_formats = intel_primary_formats_gen4; | |
13313 | num_formats = ARRAY_SIZE(intel_primary_formats_gen4); | |
13314 | } | |
13315 | ||
13316 | drm_universal_plane_init(dev, &primary->base, 0, | |
65a3fea0 | 13317 | &intel_plane_funcs, |
465c120c MR |
13318 | intel_primary_formats, num_formats, |
13319 | DRM_PLANE_TYPE_PRIMARY); | |
48404c1e | 13320 | |
3b7a5119 SJ |
13321 | if (INTEL_INFO(dev)->gen >= 4) |
13322 | intel_create_rotation_property(dev, primary); | |
48404c1e | 13323 | |
ea2c67bb MR |
13324 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
13325 | ||
465c120c MR |
13326 | return &primary->base; |
13327 | } | |
13328 | ||
3b7a5119 SJ |
13329 | void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane) |
13330 | { | |
13331 | if (!dev->mode_config.rotation_property) { | |
13332 | unsigned long flags = BIT(DRM_ROTATE_0) | | |
13333 | BIT(DRM_ROTATE_180); | |
13334 | ||
13335 | if (INTEL_INFO(dev)->gen >= 9) | |
13336 | flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270); | |
13337 | ||
13338 | dev->mode_config.rotation_property = | |
13339 | drm_mode_create_rotation_property(dev, flags); | |
13340 | } | |
13341 | if (dev->mode_config.rotation_property) | |
13342 | drm_object_attach_property(&plane->base.base, | |
13343 | dev->mode_config.rotation_property, | |
13344 | plane->base.state->rotation); | |
13345 | } | |
13346 | ||
3d7d6510 | 13347 | static int |
852e787c GP |
13348 | intel_check_cursor_plane(struct drm_plane *plane, |
13349 | struct intel_plane_state *state) | |
3d7d6510 | 13350 | { |
2b875c22 | 13351 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb | 13352 | struct drm_device *dev = plane->dev; |
2b875c22 | 13353 | struct drm_framebuffer *fb = state->base.fb; |
852e787c GP |
13354 | struct drm_rect *dest = &state->dst; |
13355 | struct drm_rect *src = &state->src; | |
13356 | const struct drm_rect *clip = &state->clip; | |
757f9a3e | 13357 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
ea2c67bb | 13358 | struct intel_crtc *intel_crtc; |
757f9a3e GP |
13359 | unsigned stride; |
13360 | int ret; | |
3d7d6510 | 13361 | |
ea2c67bb MR |
13362 | crtc = crtc ? crtc : plane->crtc; |
13363 | intel_crtc = to_intel_crtc(crtc); | |
13364 | ||
757f9a3e | 13365 | ret = drm_plane_helper_check_update(plane, crtc, fb, |
852e787c | 13366 | src, dest, clip, |
3d7d6510 MR |
13367 | DRM_PLANE_HELPER_NO_SCALING, |
13368 | DRM_PLANE_HELPER_NO_SCALING, | |
852e787c | 13369 | true, true, &state->visible); |
757f9a3e GP |
13370 | if (ret) |
13371 | return ret; | |
13372 | ||
13373 | ||
13374 | /* if we want to turn off the cursor ignore width and height */ | |
13375 | if (!obj) | |
32b7eeec | 13376 | goto finish; |
757f9a3e | 13377 | |
757f9a3e | 13378 | /* Check for which cursor types we support */ |
ea2c67bb MR |
13379 | if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) { |
13380 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", | |
13381 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
13382 | return -EINVAL; |
13383 | } | |
13384 | ||
ea2c67bb MR |
13385 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
13386 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
13387 | DRM_DEBUG_KMS("buffer is too small\n"); |
13388 | return -ENOMEM; | |
13389 | } | |
13390 | ||
3a656b54 | 13391 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
757f9a3e GP |
13392 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
13393 | ret = -EINVAL; | |
13394 | } | |
757f9a3e | 13395 | |
32b7eeec MR |
13396 | finish: |
13397 | if (intel_crtc->active) { | |
3749f463 | 13398 | if (plane->state->crtc_w != state->base.crtc_w) |
32b7eeec MR |
13399 | intel_crtc->atomic.update_wm = true; |
13400 | ||
13401 | intel_crtc->atomic.fb_bits |= | |
13402 | INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe); | |
13403 | } | |
13404 | ||
757f9a3e | 13405 | return ret; |
852e787c | 13406 | } |
3d7d6510 | 13407 | |
f4a2cf29 | 13408 | static void |
852e787c GP |
13409 | intel_commit_cursor_plane(struct drm_plane *plane, |
13410 | struct intel_plane_state *state) | |
13411 | { | |
2b875c22 | 13412 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb MR |
13413 | struct drm_device *dev = plane->dev; |
13414 | struct intel_crtc *intel_crtc; | |
2b875c22 | 13415 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 13416 | uint32_t addr; |
852e787c | 13417 | |
ea2c67bb MR |
13418 | crtc = crtc ? crtc : plane->crtc; |
13419 | intel_crtc = to_intel_crtc(crtc); | |
13420 | ||
2b875c22 | 13421 | plane->fb = state->base.fb; |
ea2c67bb MR |
13422 | crtc->cursor_x = state->base.crtc_x; |
13423 | crtc->cursor_y = state->base.crtc_y; | |
13424 | ||
a912f12f GP |
13425 | if (intel_crtc->cursor_bo == obj) |
13426 | goto update; | |
4ed91096 | 13427 | |
f4a2cf29 | 13428 | if (!obj) |
a912f12f | 13429 | addr = 0; |
f4a2cf29 | 13430 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
a912f12f | 13431 | addr = i915_gem_obj_ggtt_offset(obj); |
f4a2cf29 | 13432 | else |
a912f12f | 13433 | addr = obj->phys_handle->busaddr; |
852e787c | 13434 | |
a912f12f GP |
13435 | intel_crtc->cursor_addr = addr; |
13436 | intel_crtc->cursor_bo = obj; | |
13437 | update: | |
852e787c | 13438 | |
32b7eeec | 13439 | if (intel_crtc->active) |
a912f12f | 13440 | intel_crtc_update_cursor(crtc, state->visible); |
852e787c GP |
13441 | } |
13442 | ||
3d7d6510 MR |
13443 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
13444 | int pipe) | |
13445 | { | |
13446 | struct intel_plane *cursor; | |
8e7d688b | 13447 | struct intel_plane_state *state; |
3d7d6510 MR |
13448 | |
13449 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
13450 | if (cursor == NULL) | |
13451 | return NULL; | |
13452 | ||
8e7d688b MR |
13453 | state = intel_create_plane_state(&cursor->base); |
13454 | if (!state) { | |
ea2c67bb MR |
13455 | kfree(cursor); |
13456 | return NULL; | |
13457 | } | |
8e7d688b | 13458 | cursor->base.state = &state->base; |
ea2c67bb | 13459 | |
3d7d6510 MR |
13460 | cursor->can_scale = false; |
13461 | cursor->max_downscale = 1; | |
13462 | cursor->pipe = pipe; | |
13463 | cursor->plane = pipe; | |
549e2bfb | 13464 | state->scaler_id = -1; |
c59cb179 MR |
13465 | cursor->check_plane = intel_check_cursor_plane; |
13466 | cursor->commit_plane = intel_commit_cursor_plane; | |
3d7d6510 MR |
13467 | |
13468 | drm_universal_plane_init(dev, &cursor->base, 0, | |
65a3fea0 | 13469 | &intel_plane_funcs, |
3d7d6510 MR |
13470 | intel_cursor_formats, |
13471 | ARRAY_SIZE(intel_cursor_formats), | |
13472 | DRM_PLANE_TYPE_CURSOR); | |
4398ad45 VS |
13473 | |
13474 | if (INTEL_INFO(dev)->gen >= 4) { | |
13475 | if (!dev->mode_config.rotation_property) | |
13476 | dev->mode_config.rotation_property = | |
13477 | drm_mode_create_rotation_property(dev, | |
13478 | BIT(DRM_ROTATE_0) | | |
13479 | BIT(DRM_ROTATE_180)); | |
13480 | if (dev->mode_config.rotation_property) | |
13481 | drm_object_attach_property(&cursor->base.base, | |
13482 | dev->mode_config.rotation_property, | |
8e7d688b | 13483 | state->base.rotation); |
4398ad45 VS |
13484 | } |
13485 | ||
ea2c67bb MR |
13486 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
13487 | ||
3d7d6510 MR |
13488 | return &cursor->base; |
13489 | } | |
13490 | ||
549e2bfb CK |
13491 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
13492 | struct intel_crtc_state *crtc_state) | |
13493 | { | |
13494 | int i; | |
13495 | struct intel_scaler *intel_scaler; | |
13496 | struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; | |
13497 | ||
13498 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
13499 | intel_scaler = &scaler_state->scalers[i]; | |
13500 | intel_scaler->in_use = 0; | |
13501 | intel_scaler->id = i; | |
13502 | ||
13503 | intel_scaler->mode = PS_SCALER_MODE_DYN; | |
13504 | } | |
13505 | ||
13506 | scaler_state->scaler_id = -1; | |
13507 | } | |
13508 | ||
b358d0a6 | 13509 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 13510 | { |
fbee40df | 13511 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 13512 | struct intel_crtc *intel_crtc; |
f5de6e07 | 13513 | struct intel_crtc_state *crtc_state = NULL; |
3d7d6510 MR |
13514 | struct drm_plane *primary = NULL; |
13515 | struct drm_plane *cursor = NULL; | |
465c120c | 13516 | int i, ret; |
79e53945 | 13517 | |
955382f3 | 13518 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
13519 | if (intel_crtc == NULL) |
13520 | return; | |
13521 | ||
f5de6e07 ACO |
13522 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
13523 | if (!crtc_state) | |
13524 | goto fail; | |
13525 | intel_crtc_set_state(intel_crtc, crtc_state); | |
07878248 | 13526 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 13527 | |
549e2bfb CK |
13528 | /* initialize shared scalers */ |
13529 | if (INTEL_INFO(dev)->gen >= 9) { | |
13530 | if (pipe == PIPE_C) | |
13531 | intel_crtc->num_scalers = 1; | |
13532 | else | |
13533 | intel_crtc->num_scalers = SKL_NUM_SCALERS; | |
13534 | ||
13535 | skl_init_scalers(dev, intel_crtc, crtc_state); | |
13536 | } | |
13537 | ||
465c120c | 13538 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
13539 | if (!primary) |
13540 | goto fail; | |
13541 | ||
13542 | cursor = intel_cursor_plane_create(dev, pipe); | |
13543 | if (!cursor) | |
13544 | goto fail; | |
13545 | ||
465c120c | 13546 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
3d7d6510 MR |
13547 | cursor, &intel_crtc_funcs); |
13548 | if (ret) | |
13549 | goto fail; | |
79e53945 JB |
13550 | |
13551 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
13552 | for (i = 0; i < 256; i++) { |
13553 | intel_crtc->lut_r[i] = i; | |
13554 | intel_crtc->lut_g[i] = i; | |
13555 | intel_crtc->lut_b[i] = i; | |
13556 | } | |
13557 | ||
1f1c2e24 VS |
13558 | /* |
13559 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 13560 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 13561 | */ |
80824003 JB |
13562 | intel_crtc->pipe = pipe; |
13563 | intel_crtc->plane = pipe; | |
3a77c4c4 | 13564 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 13565 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 13566 | intel_crtc->plane = !pipe; |
80824003 JB |
13567 | } |
13568 | ||
4b0e333e CW |
13569 | intel_crtc->cursor_base = ~0; |
13570 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 13571 | intel_crtc->cursor_size = ~0; |
8d7849db | 13572 | |
22fd0fab JB |
13573 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
13574 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
13575 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
13576 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
13577 | ||
9362c7c5 ACO |
13578 | INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func); |
13579 | ||
79e53945 | 13580 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 DV |
13581 | |
13582 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); | |
3d7d6510 MR |
13583 | return; |
13584 | ||
13585 | fail: | |
13586 | if (primary) | |
13587 | drm_plane_cleanup(primary); | |
13588 | if (cursor) | |
13589 | drm_plane_cleanup(cursor); | |
f5de6e07 | 13590 | kfree(crtc_state); |
3d7d6510 | 13591 | kfree(intel_crtc); |
79e53945 JB |
13592 | } |
13593 | ||
752aa88a JB |
13594 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
13595 | { | |
13596 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 13597 | struct drm_device *dev = connector->base.dev; |
752aa88a | 13598 | |
51fd371b | 13599 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 13600 | |
d3babd3f | 13601 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
13602 | return INVALID_PIPE; |
13603 | ||
13604 | return to_intel_crtc(encoder->crtc)->pipe; | |
13605 | } | |
13606 | ||
08d7b3d1 | 13607 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 13608 | struct drm_file *file) |
08d7b3d1 | 13609 | { |
08d7b3d1 | 13610 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 13611 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 13612 | struct intel_crtc *crtc; |
08d7b3d1 | 13613 | |
7707e653 | 13614 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
08d7b3d1 | 13615 | |
7707e653 | 13616 | if (!drmmode_crtc) { |
08d7b3d1 | 13617 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 13618 | return -ENOENT; |
08d7b3d1 CW |
13619 | } |
13620 | ||
7707e653 | 13621 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 13622 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 13623 | |
c05422d5 | 13624 | return 0; |
08d7b3d1 CW |
13625 | } |
13626 | ||
66a9278e | 13627 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 13628 | { |
66a9278e DV |
13629 | struct drm_device *dev = encoder->base.dev; |
13630 | struct intel_encoder *source_encoder; | |
79e53945 | 13631 | int index_mask = 0; |
79e53945 JB |
13632 | int entry = 0; |
13633 | ||
b2784e15 | 13634 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 13635 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
13636 | index_mask |= (1 << entry); |
13637 | ||
79e53945 JB |
13638 | entry++; |
13639 | } | |
4ef69c7a | 13640 | |
79e53945 JB |
13641 | return index_mask; |
13642 | } | |
13643 | ||
4d302442 CW |
13644 | static bool has_edp_a(struct drm_device *dev) |
13645 | { | |
13646 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13647 | ||
13648 | if (!IS_MOBILE(dev)) | |
13649 | return false; | |
13650 | ||
13651 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
13652 | return false; | |
13653 | ||
e3589908 | 13654 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
13655 | return false; |
13656 | ||
13657 | return true; | |
13658 | } | |
13659 | ||
84b4e042 JB |
13660 | static bool intel_crt_present(struct drm_device *dev) |
13661 | { | |
13662 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13663 | ||
884497ed DL |
13664 | if (INTEL_INFO(dev)->gen >= 9) |
13665 | return false; | |
13666 | ||
cf404ce4 | 13667 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
84b4e042 JB |
13668 | return false; |
13669 | ||
13670 | if (IS_CHERRYVIEW(dev)) | |
13671 | return false; | |
13672 | ||
13673 | if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support) | |
13674 | return false; | |
13675 | ||
13676 | return true; | |
13677 | } | |
13678 | ||
79e53945 JB |
13679 | static void intel_setup_outputs(struct drm_device *dev) |
13680 | { | |
725e30ad | 13681 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 13682 | struct intel_encoder *encoder; |
cb0953d7 | 13683 | bool dpd_is_edp = false; |
79e53945 | 13684 | |
c9093354 | 13685 | intel_lvds_init(dev); |
79e53945 | 13686 | |
84b4e042 | 13687 | if (intel_crt_present(dev)) |
79935fca | 13688 | intel_crt_init(dev); |
cb0953d7 | 13689 | |
c776eb2e VK |
13690 | if (IS_BROXTON(dev)) { |
13691 | /* | |
13692 | * FIXME: Broxton doesn't support port detection via the | |
13693 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
13694 | * detect the ports. | |
13695 | */ | |
13696 | intel_ddi_init(dev, PORT_A); | |
13697 | intel_ddi_init(dev, PORT_B); | |
13698 | intel_ddi_init(dev, PORT_C); | |
13699 | } else if (HAS_DDI(dev)) { | |
0e72a5b5 ED |
13700 | int found; |
13701 | ||
de31facd JB |
13702 | /* |
13703 | * Haswell uses DDI functions to detect digital outputs. | |
13704 | * On SKL pre-D0 the strap isn't connected, so we assume | |
13705 | * it's there. | |
13706 | */ | |
0e72a5b5 | 13707 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; |
de31facd JB |
13708 | /* WaIgnoreDDIAStrap: skl */ |
13709 | if (found || | |
13710 | (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0)) | |
0e72a5b5 ED |
13711 | intel_ddi_init(dev, PORT_A); |
13712 | ||
13713 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
13714 | * register */ | |
13715 | found = I915_READ(SFUSE_STRAP); | |
13716 | ||
13717 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
13718 | intel_ddi_init(dev, PORT_B); | |
13719 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
13720 | intel_ddi_init(dev, PORT_C); | |
13721 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
13722 | intel_ddi_init(dev, PORT_D); | |
13723 | } else if (HAS_PCH_SPLIT(dev)) { | |
cb0953d7 | 13724 | int found; |
5d8a7752 | 13725 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
13726 | |
13727 | if (has_edp_a(dev)) | |
13728 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 13729 | |
dc0fa718 | 13730 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 13731 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 13732 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 | 13733 | if (!found) |
e2debe91 | 13734 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 13735 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 13736 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
13737 | } |
13738 | ||
dc0fa718 | 13739 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 13740 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 13741 | |
dc0fa718 | 13742 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 13743 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 13744 | |
5eb08b69 | 13745 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 13746 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 13747 | |
270b3042 | 13748 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 13749 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
4a87d65d | 13750 | } else if (IS_VALLEYVIEW(dev)) { |
e17ac6db VS |
13751 | /* |
13752 | * The DP_DETECTED bit is the latched state of the DDC | |
13753 | * SDA pin at boot. However since eDP doesn't require DDC | |
13754 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
13755 | * eDP ports may have been muxed to an alternate function. | |
13756 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
13757 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
13758 | * detect eDP ports. | |
13759 | */ | |
d2182a66 VS |
13760 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED && |
13761 | !intel_dp_is_edp(dev, PORT_B)) | |
585a94b8 AB |
13762 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, |
13763 | PORT_B); | |
e17ac6db VS |
13764 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED || |
13765 | intel_dp_is_edp(dev, PORT_B)) | |
13766 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); | |
585a94b8 | 13767 | |
d2182a66 VS |
13768 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED && |
13769 | !intel_dp_is_edp(dev, PORT_C)) | |
6f6005a5 JB |
13770 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, |
13771 | PORT_C); | |
e17ac6db VS |
13772 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED || |
13773 | intel_dp_is_edp(dev, PORT_C)) | |
13774 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); | |
19c03924 | 13775 | |
9418c1f1 | 13776 | if (IS_CHERRYVIEW(dev)) { |
e17ac6db | 13777 | if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) |
9418c1f1 VS |
13778 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID, |
13779 | PORT_D); | |
e17ac6db VS |
13780 | /* eDP not supported on port D, so don't check VBT */ |
13781 | if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED) | |
13782 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D); | |
9418c1f1 VS |
13783 | } |
13784 | ||
3cfca973 | 13785 | intel_dsi_init(dev); |
103a196f | 13786 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 13787 | bool found = false; |
7d57382e | 13788 | |
e2debe91 | 13789 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 13790 | DRM_DEBUG_KMS("probing SDVOB\n"); |
e2debe91 | 13791 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
b01f2c3a JB |
13792 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
13793 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
e2debe91 | 13794 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 13795 | } |
27185ae1 | 13796 | |
e7281eab | 13797 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 13798 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 13799 | } |
13520b05 KH |
13800 | |
13801 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 13802 | |
e2debe91 | 13803 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 13804 | DRM_DEBUG_KMS("probing SDVOC\n"); |
e2debe91 | 13805 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
b01f2c3a | 13806 | } |
27185ae1 | 13807 | |
e2debe91 | 13808 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 13809 | |
b01f2c3a JB |
13810 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
13811 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
e2debe91 | 13812 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 13813 | } |
e7281eab | 13814 | if (SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 13815 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 13816 | } |
27185ae1 | 13817 | |
b01f2c3a | 13818 | if (SUPPORTS_INTEGRATED_DP(dev) && |
e7281eab | 13819 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 13820 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 13821 | } else if (IS_GEN2(dev)) |
79e53945 JB |
13822 | intel_dvo_init(dev); |
13823 | ||
103a196f | 13824 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
13825 | intel_tv_init(dev); |
13826 | ||
0bc12bcb | 13827 | intel_psr_init(dev); |
7c8f8a70 | 13828 | |
b2784e15 | 13829 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
13830 | encoder->base.possible_crtcs = encoder->crtc_mask; |
13831 | encoder->base.possible_clones = | |
66a9278e | 13832 | intel_encoder_clones(encoder); |
79e53945 | 13833 | } |
47356eb6 | 13834 | |
dde86e2d | 13835 | intel_init_pch_refclk(dev); |
270b3042 DV |
13836 | |
13837 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
13838 | } |
13839 | ||
13840 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
13841 | { | |
60a5ca01 | 13842 | struct drm_device *dev = fb->dev; |
79e53945 | 13843 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 13844 | |
ef2d633e | 13845 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 13846 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 13847 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
60a5ca01 VS |
13848 | drm_gem_object_unreference(&intel_fb->obj->base); |
13849 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
13850 | kfree(intel_fb); |
13851 | } | |
13852 | ||
13853 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 13854 | struct drm_file *file, |
79e53945 JB |
13855 | unsigned int *handle) |
13856 | { | |
13857 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 13858 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 13859 | |
05394f39 | 13860 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
13861 | } |
13862 | ||
13863 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
13864 | .destroy = intel_user_framebuffer_destroy, | |
13865 | .create_handle = intel_user_framebuffer_create_handle, | |
13866 | }; | |
13867 | ||
b321803d DL |
13868 | static |
13869 | u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, | |
13870 | uint32_t pixel_format) | |
13871 | { | |
13872 | u32 gen = INTEL_INFO(dev)->gen; | |
13873 | ||
13874 | if (gen >= 9) { | |
13875 | /* "The stride in bytes must not exceed the of the size of 8K | |
13876 | * pixels and 32K bytes." | |
13877 | */ | |
13878 | return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768); | |
13879 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) { | |
13880 | return 32*1024; | |
13881 | } else if (gen >= 4) { | |
13882 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
13883 | return 16*1024; | |
13884 | else | |
13885 | return 32*1024; | |
13886 | } else if (gen >= 3) { | |
13887 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
13888 | return 8*1024; | |
13889 | else | |
13890 | return 16*1024; | |
13891 | } else { | |
13892 | /* XXX DSPC is limited to 4k tiled */ | |
13893 | return 8*1024; | |
13894 | } | |
13895 | } | |
13896 | ||
b5ea642a DV |
13897 | static int intel_framebuffer_init(struct drm_device *dev, |
13898 | struct intel_framebuffer *intel_fb, | |
13899 | struct drm_mode_fb_cmd2 *mode_cmd, | |
13900 | struct drm_i915_gem_object *obj) | |
79e53945 | 13901 | { |
6761dd31 | 13902 | unsigned int aligned_height; |
79e53945 | 13903 | int ret; |
b321803d | 13904 | u32 pitch_limit, stride_alignment; |
79e53945 | 13905 | |
dd4916c5 DV |
13906 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
13907 | ||
2a80eada DV |
13908 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
13909 | /* Enforce that fb modifier and tiling mode match, but only for | |
13910 | * X-tiled. This is needed for FBC. */ | |
13911 | if (!!(obj->tiling_mode == I915_TILING_X) != | |
13912 | !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) { | |
13913 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); | |
13914 | return -EINVAL; | |
13915 | } | |
13916 | } else { | |
13917 | if (obj->tiling_mode == I915_TILING_X) | |
13918 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
13919 | else if (obj->tiling_mode == I915_TILING_Y) { | |
13920 | DRM_DEBUG("No Y tiling for legacy addfb\n"); | |
13921 | return -EINVAL; | |
13922 | } | |
13923 | } | |
13924 | ||
9a8f0a12 TU |
13925 | /* Passed in modifier sanity checking. */ |
13926 | switch (mode_cmd->modifier[0]) { | |
13927 | case I915_FORMAT_MOD_Y_TILED: | |
13928 | case I915_FORMAT_MOD_Yf_TILED: | |
13929 | if (INTEL_INFO(dev)->gen < 9) { | |
13930 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", | |
13931 | mode_cmd->modifier[0]); | |
13932 | return -EINVAL; | |
13933 | } | |
13934 | case DRM_FORMAT_MOD_NONE: | |
13935 | case I915_FORMAT_MOD_X_TILED: | |
13936 | break; | |
13937 | default: | |
c0f40428 JB |
13938 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
13939 | mode_cmd->modifier[0]); | |
57cd6508 | 13940 | return -EINVAL; |
c16ed4be | 13941 | } |
57cd6508 | 13942 | |
b321803d DL |
13943 | stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0], |
13944 | mode_cmd->pixel_format); | |
13945 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
13946 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
13947 | mode_cmd->pitches[0], stride_alignment); | |
57cd6508 | 13948 | return -EINVAL; |
c16ed4be | 13949 | } |
57cd6508 | 13950 | |
b321803d DL |
13951 | pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], |
13952 | mode_cmd->pixel_format); | |
a35cdaa0 | 13953 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
13954 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
13955 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 13956 | "tiled" : "linear", |
a35cdaa0 | 13957 | mode_cmd->pitches[0], pitch_limit); |
5d7bd705 | 13958 | return -EINVAL; |
c16ed4be | 13959 | } |
5d7bd705 | 13960 | |
2a80eada | 13961 | if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED && |
c16ed4be CW |
13962 | mode_cmd->pitches[0] != obj->stride) { |
13963 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
13964 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 13965 | return -EINVAL; |
c16ed4be | 13966 | } |
5d7bd705 | 13967 | |
57779d06 | 13968 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 13969 | switch (mode_cmd->pixel_format) { |
57779d06 | 13970 | case DRM_FORMAT_C8: |
04b3924d VS |
13971 | case DRM_FORMAT_RGB565: |
13972 | case DRM_FORMAT_XRGB8888: | |
13973 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
13974 | break; |
13975 | case DRM_FORMAT_XRGB1555: | |
13976 | case DRM_FORMAT_ARGB1555: | |
c16ed4be | 13977 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
13978 | DRM_DEBUG("unsupported pixel format: %s\n", |
13979 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 13980 | return -EINVAL; |
c16ed4be | 13981 | } |
57779d06 VS |
13982 | break; |
13983 | case DRM_FORMAT_XBGR8888: | |
13984 | case DRM_FORMAT_ABGR8888: | |
04b3924d VS |
13985 | case DRM_FORMAT_XRGB2101010: |
13986 | case DRM_FORMAT_ARGB2101010: | |
57779d06 VS |
13987 | case DRM_FORMAT_XBGR2101010: |
13988 | case DRM_FORMAT_ABGR2101010: | |
c16ed4be | 13989 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
13990 | DRM_DEBUG("unsupported pixel format: %s\n", |
13991 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 13992 | return -EINVAL; |
c16ed4be | 13993 | } |
b5626747 | 13994 | break; |
04b3924d VS |
13995 | case DRM_FORMAT_YUYV: |
13996 | case DRM_FORMAT_UYVY: | |
13997 | case DRM_FORMAT_YVYU: | |
13998 | case DRM_FORMAT_VYUY: | |
c16ed4be | 13999 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
14000 | DRM_DEBUG("unsupported pixel format: %s\n", |
14001 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14002 | return -EINVAL; |
c16ed4be | 14003 | } |
57cd6508 CW |
14004 | break; |
14005 | default: | |
4ee62c76 VS |
14006 | DRM_DEBUG("unsupported pixel format: %s\n", |
14007 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
14008 | return -EINVAL; |
14009 | } | |
14010 | ||
90f9a336 VS |
14011 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
14012 | if (mode_cmd->offsets[0] != 0) | |
14013 | return -EINVAL; | |
14014 | ||
ec2c981e | 14015 | aligned_height = intel_fb_align_height(dev, mode_cmd->height, |
091df6cb DV |
14016 | mode_cmd->pixel_format, |
14017 | mode_cmd->modifier[0]); | |
53155c0a DV |
14018 | /* FIXME drm helper for size checks (especially planar formats)? */ |
14019 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
14020 | return -EINVAL; | |
14021 | ||
c7d73f6a DV |
14022 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
14023 | intel_fb->obj = obj; | |
80075d49 | 14024 | intel_fb->obj->framebuffer_references++; |
c7d73f6a | 14025 | |
79e53945 JB |
14026 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
14027 | if (ret) { | |
14028 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
14029 | return ret; | |
14030 | } | |
14031 | ||
79e53945 JB |
14032 | return 0; |
14033 | } | |
14034 | ||
79e53945 JB |
14035 | static struct drm_framebuffer * |
14036 | intel_user_framebuffer_create(struct drm_device *dev, | |
14037 | struct drm_file *filp, | |
308e5bcb | 14038 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 14039 | { |
05394f39 | 14040 | struct drm_i915_gem_object *obj; |
79e53945 | 14041 | |
308e5bcb JB |
14042 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
14043 | mode_cmd->handles[0])); | |
c8725226 | 14044 | if (&obj->base == NULL) |
cce13ff7 | 14045 | return ERR_PTR(-ENOENT); |
79e53945 | 14046 | |
d2dff872 | 14047 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
14048 | } |
14049 | ||
4520f53a | 14050 | #ifndef CONFIG_DRM_I915_FBDEV |
0632fef6 | 14051 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
14052 | { |
14053 | } | |
14054 | #endif | |
14055 | ||
79e53945 | 14056 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 14057 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 14058 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
14059 | .atomic_check = intel_atomic_check, |
14060 | .atomic_commit = intel_atomic_commit, | |
79e53945 JB |
14061 | }; |
14062 | ||
e70236a8 JB |
14063 | /* Set up chip specific display functions */ |
14064 | static void intel_init_display(struct drm_device *dev) | |
14065 | { | |
14066 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14067 | ||
ee9300bb DV |
14068 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
14069 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
ef9348c8 CML |
14070 | else if (IS_CHERRYVIEW(dev)) |
14071 | dev_priv->display.find_dpll = chv_find_best_dpll; | |
ee9300bb DV |
14072 | else if (IS_VALLEYVIEW(dev)) |
14073 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
14074 | else if (IS_PINEVIEW(dev)) | |
14075 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
14076 | else | |
14077 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
14078 | ||
bc8d7dff DL |
14079 | if (INTEL_INFO(dev)->gen >= 9) { |
14080 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; | |
5724dbd1 DL |
14081 | dev_priv->display.get_initial_plane_config = |
14082 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
14083 | dev_priv->display.crtc_compute_clock = |
14084 | haswell_crtc_compute_clock; | |
14085 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
14086 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
14087 | dev_priv->display.off = ironlake_crtc_off; | |
14088 | dev_priv->display.update_primary_plane = | |
14089 | skylake_update_primary_plane; | |
14090 | } else if (HAS_DDI(dev)) { | |
0e8ffe1b | 14091 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14092 | dev_priv->display.get_initial_plane_config = |
14093 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
14094 | dev_priv->display.crtc_compute_clock = |
14095 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
14096 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
14097 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
df8ad70c | 14098 | dev_priv->display.off = ironlake_crtc_off; |
bc8d7dff DL |
14099 | dev_priv->display.update_primary_plane = |
14100 | ironlake_update_primary_plane; | |
09b4ddf9 | 14101 | } else if (HAS_PCH_SPLIT(dev)) { |
0e8ffe1b | 14102 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
14103 | dev_priv->display.get_initial_plane_config = |
14104 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
14105 | dev_priv->display.crtc_compute_clock = |
14106 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
14107 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
14108 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
ee7b9f93 | 14109 | dev_priv->display.off = ironlake_crtc_off; |
262ca2b0 MR |
14110 | dev_priv->display.update_primary_plane = |
14111 | ironlake_update_primary_plane; | |
89b667f8 JB |
14112 | } else if (IS_VALLEYVIEW(dev)) { |
14113 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
5724dbd1 DL |
14114 | dev_priv->display.get_initial_plane_config = |
14115 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14116 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
89b667f8 JB |
14117 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
14118 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
14119 | dev_priv->display.off = i9xx_crtc_off; | |
262ca2b0 MR |
14120 | dev_priv->display.update_primary_plane = |
14121 | i9xx_update_primary_plane; | |
f564048e | 14122 | } else { |
0e8ffe1b | 14123 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14124 | dev_priv->display.get_initial_plane_config = |
14125 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14126 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
14127 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
14128 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
ee7b9f93 | 14129 | dev_priv->display.off = i9xx_crtc_off; |
262ca2b0 MR |
14130 | dev_priv->display.update_primary_plane = |
14131 | i9xx_update_primary_plane; | |
f564048e | 14132 | } |
e70236a8 | 14133 | |
e70236a8 | 14134 | /* Returns the core display clock speed */ |
1652d19e VS |
14135 | if (IS_SKYLAKE(dev)) |
14136 | dev_priv->display.get_display_clock_speed = | |
14137 | skylake_get_display_clock_speed; | |
14138 | else if (IS_BROADWELL(dev)) | |
14139 | dev_priv->display.get_display_clock_speed = | |
14140 | broadwell_get_display_clock_speed; | |
14141 | else if (IS_HASWELL(dev)) | |
14142 | dev_priv->display.get_display_clock_speed = | |
14143 | haswell_get_display_clock_speed; | |
14144 | else if (IS_VALLEYVIEW(dev)) | |
25eb05fc JB |
14145 | dev_priv->display.get_display_clock_speed = |
14146 | valleyview_get_display_clock_speed; | |
b37a6434 VS |
14147 | else if (IS_GEN5(dev)) |
14148 | dev_priv->display.get_display_clock_speed = | |
14149 | ilk_get_display_clock_speed; | |
a7c66cd8 VS |
14150 | else if (IS_I945G(dev) || IS_BROADWATER(dev) || |
14151 | IS_GEN6(dev) || IS_IVYBRIDGE(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) | |
e70236a8 JB |
14152 | dev_priv->display.get_display_clock_speed = |
14153 | i945_get_display_clock_speed; | |
14154 | else if (IS_I915G(dev)) | |
14155 | dev_priv->display.get_display_clock_speed = | |
14156 | i915_get_display_clock_speed; | |
257a7ffc | 14157 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
14158 | dev_priv->display.get_display_clock_speed = |
14159 | i9xx_misc_get_display_clock_speed; | |
257a7ffc DV |
14160 | else if (IS_PINEVIEW(dev)) |
14161 | dev_priv->display.get_display_clock_speed = | |
14162 | pnv_get_display_clock_speed; | |
e70236a8 JB |
14163 | else if (IS_I915GM(dev)) |
14164 | dev_priv->display.get_display_clock_speed = | |
14165 | i915gm_get_display_clock_speed; | |
14166 | else if (IS_I865G(dev)) | |
14167 | dev_priv->display.get_display_clock_speed = | |
14168 | i865_get_display_clock_speed; | |
f0f8a9ce | 14169 | else if (IS_I85X(dev)) |
e70236a8 JB |
14170 | dev_priv->display.get_display_clock_speed = |
14171 | i855_get_display_clock_speed; | |
14172 | else /* 852, 830 */ | |
14173 | dev_priv->display.get_display_clock_speed = | |
14174 | i830_get_display_clock_speed; | |
14175 | ||
7c10a2b5 | 14176 | if (IS_GEN5(dev)) { |
3bb11b53 | 14177 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
3bb11b53 SJ |
14178 | } else if (IS_GEN6(dev)) { |
14179 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; | |
3bb11b53 SJ |
14180 | } else if (IS_IVYBRIDGE(dev)) { |
14181 | /* FIXME: detect B0+ stepping and use auto training */ | |
14182 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
059b2fe9 | 14183 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
3bb11b53 | 14184 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
30a970c6 JB |
14185 | } else if (IS_VALLEYVIEW(dev)) { |
14186 | dev_priv->display.modeset_global_resources = | |
14187 | valleyview_modeset_global_resources; | |
f8437dd1 VK |
14188 | } else if (IS_BROXTON(dev)) { |
14189 | dev_priv->display.modeset_global_resources = | |
14190 | broxton_modeset_global_resources; | |
e70236a8 | 14191 | } |
8c9f3aaf | 14192 | |
8c9f3aaf JB |
14193 | switch (INTEL_INFO(dev)->gen) { |
14194 | case 2: | |
14195 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
14196 | break; | |
14197 | ||
14198 | case 3: | |
14199 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
14200 | break; | |
14201 | ||
14202 | case 4: | |
14203 | case 5: | |
14204 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
14205 | break; | |
14206 | ||
14207 | case 6: | |
14208 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
14209 | break; | |
7c9017e5 | 14210 | case 7: |
4e0bbc31 | 14211 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
14212 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
14213 | break; | |
830c81db | 14214 | case 9: |
ba343e02 TU |
14215 | /* Drop through - unsupported since execlist only. */ |
14216 | default: | |
14217 | /* Default just returns -ENODEV to indicate unsupported */ | |
14218 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
8c9f3aaf | 14219 | } |
7bd688cd JN |
14220 | |
14221 | intel_panel_init_backlight_funcs(dev); | |
e39b999a VS |
14222 | |
14223 | mutex_init(&dev_priv->pps_mutex); | |
e70236a8 JB |
14224 | } |
14225 | ||
b690e96c JB |
14226 | /* |
14227 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
14228 | * resume, or other times. This quirk makes sure that's the case for | |
14229 | * affected systems. | |
14230 | */ | |
0206e353 | 14231 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
14232 | { |
14233 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14234 | ||
14235 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 14236 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
14237 | } |
14238 | ||
b6b5d049 VS |
14239 | static void quirk_pipeb_force(struct drm_device *dev) |
14240 | { | |
14241 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14242 | ||
14243 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
14244 | DRM_INFO("applying pipe b force quirk\n"); | |
14245 | } | |
14246 | ||
435793df KP |
14247 | /* |
14248 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
14249 | */ | |
14250 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
14251 | { | |
14252 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14253 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 14254 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
14255 | } |
14256 | ||
4dca20ef | 14257 | /* |
5a15ab5b CE |
14258 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
14259 | * brightness value | |
4dca20ef CE |
14260 | */ |
14261 | static void quirk_invert_brightness(struct drm_device *dev) | |
14262 | { | |
14263 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14264 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 14265 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
14266 | } |
14267 | ||
9c72cc6f SD |
14268 | /* Some VBT's incorrectly indicate no backlight is present */ |
14269 | static void quirk_backlight_present(struct drm_device *dev) | |
14270 | { | |
14271 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14272 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; | |
14273 | DRM_INFO("applying backlight present quirk\n"); | |
14274 | } | |
14275 | ||
b690e96c JB |
14276 | struct intel_quirk { |
14277 | int device; | |
14278 | int subsystem_vendor; | |
14279 | int subsystem_device; | |
14280 | void (*hook)(struct drm_device *dev); | |
14281 | }; | |
14282 | ||
5f85f176 EE |
14283 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
14284 | struct intel_dmi_quirk { | |
14285 | void (*hook)(struct drm_device *dev); | |
14286 | const struct dmi_system_id (*dmi_id_list)[]; | |
14287 | }; | |
14288 | ||
14289 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
14290 | { | |
14291 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
14292 | return 1; | |
14293 | } | |
14294 | ||
14295 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
14296 | { | |
14297 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
14298 | { | |
14299 | .callback = intel_dmi_reverse_brightness, | |
14300 | .ident = "NCR Corporation", | |
14301 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
14302 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
14303 | }, | |
14304 | }, | |
14305 | { } /* terminating entry */ | |
14306 | }, | |
14307 | .hook = quirk_invert_brightness, | |
14308 | }, | |
14309 | }; | |
14310 | ||
c43b5634 | 14311 | static struct intel_quirk intel_quirks[] = { |
b690e96c | 14312 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
0206e353 | 14313 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
b690e96c | 14314 | |
b690e96c JB |
14315 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
14316 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
14317 | ||
b690e96c JB |
14318 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
14319 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
14320 | ||
5f080c0f VS |
14321 | /* 830 needs to leave pipe A & dpll A up */ |
14322 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
14323 | ||
b6b5d049 VS |
14324 | /* 830 needs to leave pipe B & dpll B up */ |
14325 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
14326 | ||
435793df KP |
14327 | /* Lenovo U160 cannot use SSC on LVDS */ |
14328 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
14329 | |
14330 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
14331 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 14332 | |
be505f64 AH |
14333 | /* Acer Aspire 5734Z must invert backlight brightness */ |
14334 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
14335 | ||
14336 | /* Acer/eMachines G725 */ | |
14337 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
14338 | ||
14339 | /* Acer/eMachines e725 */ | |
14340 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
14341 | ||
14342 | /* Acer/Packard Bell NCL20 */ | |
14343 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
14344 | ||
14345 | /* Acer Aspire 4736Z */ | |
14346 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
14347 | |
14348 | /* Acer Aspire 5336 */ | |
14349 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
14350 | |
14351 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
14352 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 14353 | |
dfb3d47b SD |
14354 | /* Acer C720 Chromebook (Core i3 4005U) */ |
14355 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
14356 | ||
b2a9601c | 14357 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
14358 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
14359 | ||
d4967d8c SD |
14360 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
14361 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
14362 | |
14363 | /* HP Chromebook 14 (Celeron 2955U) */ | |
14364 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
14365 | |
14366 | /* Dell Chromebook 11 */ | |
14367 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
14368 | }; |
14369 | ||
14370 | static void intel_init_quirks(struct drm_device *dev) | |
14371 | { | |
14372 | struct pci_dev *d = dev->pdev; | |
14373 | int i; | |
14374 | ||
14375 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
14376 | struct intel_quirk *q = &intel_quirks[i]; | |
14377 | ||
14378 | if (d->device == q->device && | |
14379 | (d->subsystem_vendor == q->subsystem_vendor || | |
14380 | q->subsystem_vendor == PCI_ANY_ID) && | |
14381 | (d->subsystem_device == q->subsystem_device || | |
14382 | q->subsystem_device == PCI_ANY_ID)) | |
14383 | q->hook(dev); | |
14384 | } | |
5f85f176 EE |
14385 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
14386 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
14387 | intel_dmi_quirks[i].hook(dev); | |
14388 | } | |
b690e96c JB |
14389 | } |
14390 | ||
9cce37f4 JB |
14391 | /* Disable the VGA plane that we never use */ |
14392 | static void i915_disable_vga(struct drm_device *dev) | |
14393 | { | |
14394 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14395 | u8 sr1; | |
766aa1c4 | 14396 | u32 vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 14397 | |
2b37c616 | 14398 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 14399 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 14400 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
14401 | sr1 = inb(VGA_SR_DATA); |
14402 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
14403 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
14404 | udelay(300); | |
14405 | ||
01f5a626 | 14406 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
14407 | POSTING_READ(vga_reg); |
14408 | } | |
14409 | ||
f817586c DV |
14410 | void intel_modeset_init_hw(struct drm_device *dev) |
14411 | { | |
a8f78b58 ED |
14412 | intel_prepare_ddi(dev); |
14413 | ||
f8bf63fd VS |
14414 | if (IS_VALLEYVIEW(dev)) |
14415 | vlv_update_cdclk(dev); | |
14416 | ||
f817586c DV |
14417 | intel_init_clock_gating(dev); |
14418 | ||
8090c6b9 | 14419 | intel_enable_gt_powersave(dev); |
f817586c DV |
14420 | } |
14421 | ||
79e53945 JB |
14422 | void intel_modeset_init(struct drm_device *dev) |
14423 | { | |
652c393a | 14424 | struct drm_i915_private *dev_priv = dev->dev_private; |
1fe47785 | 14425 | int sprite, ret; |
8cc87b75 | 14426 | enum pipe pipe; |
46f297fb | 14427 | struct intel_crtc *crtc; |
79e53945 JB |
14428 | |
14429 | drm_mode_config_init(dev); | |
14430 | ||
14431 | dev->mode_config.min_width = 0; | |
14432 | dev->mode_config.min_height = 0; | |
14433 | ||
019d96cb DA |
14434 | dev->mode_config.preferred_depth = 24; |
14435 | dev->mode_config.prefer_shadow = 1; | |
14436 | ||
25bab385 TU |
14437 | dev->mode_config.allow_fb_modifiers = true; |
14438 | ||
e6ecefaa | 14439 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 14440 | |
b690e96c JB |
14441 | intel_init_quirks(dev); |
14442 | ||
1fa61106 ED |
14443 | intel_init_pm(dev); |
14444 | ||
e3c74757 BW |
14445 | if (INTEL_INFO(dev)->num_pipes == 0) |
14446 | return; | |
14447 | ||
e70236a8 | 14448 | intel_init_display(dev); |
7c10a2b5 | 14449 | intel_init_audio(dev); |
e70236a8 | 14450 | |
a6c45cf0 CW |
14451 | if (IS_GEN2(dev)) { |
14452 | dev->mode_config.max_width = 2048; | |
14453 | dev->mode_config.max_height = 2048; | |
14454 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
14455 | dev->mode_config.max_width = 4096; |
14456 | dev->mode_config.max_height = 4096; | |
79e53945 | 14457 | } else { |
a6c45cf0 CW |
14458 | dev->mode_config.max_width = 8192; |
14459 | dev->mode_config.max_height = 8192; | |
79e53945 | 14460 | } |
068be561 | 14461 | |
dc41c154 VS |
14462 | if (IS_845G(dev) || IS_I865G(dev)) { |
14463 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
14464 | dev->mode_config.cursor_height = 1023; | |
14465 | } else if (IS_GEN2(dev)) { | |
068be561 DL |
14466 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
14467 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
14468 | } else { | |
14469 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
14470 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
14471 | } | |
14472 | ||
5d4545ae | 14473 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 14474 | |
28c97730 | 14475 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
14476 | INTEL_INFO(dev)->num_pipes, |
14477 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 14478 | |
055e393f | 14479 | for_each_pipe(dev_priv, pipe) { |
8cc87b75 | 14480 | intel_crtc_init(dev, pipe); |
3bdcfc0c | 14481 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 14482 | ret = intel_plane_init(dev, pipe, sprite); |
7f1f3851 | 14483 | if (ret) |
06da8da2 | 14484 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 14485 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 14486 | } |
79e53945 JB |
14487 | } |
14488 | ||
f42bb70d JB |
14489 | intel_init_dpio(dev); |
14490 | ||
e72f9fbf | 14491 | intel_shared_dpll_init(dev); |
ee7b9f93 | 14492 | |
9cce37f4 JB |
14493 | /* Just disable it once at startup */ |
14494 | i915_disable_vga(dev); | |
79e53945 | 14495 | intel_setup_outputs(dev); |
11be49eb CW |
14496 | |
14497 | /* Just in case the BIOS is doing something questionable. */ | |
7ff0ebcc | 14498 | intel_fbc_disable(dev); |
fa9fa083 | 14499 | |
6e9f798d | 14500 | drm_modeset_lock_all(dev); |
fa9fa083 | 14501 | intel_modeset_setup_hw_state(dev, false); |
6e9f798d | 14502 | drm_modeset_unlock_all(dev); |
46f297fb | 14503 | |
d3fcc808 | 14504 | for_each_intel_crtc(dev, crtc) { |
46f297fb JB |
14505 | if (!crtc->active) |
14506 | continue; | |
14507 | ||
46f297fb | 14508 | /* |
46f297fb JB |
14509 | * Note that reserving the BIOS fb up front prevents us |
14510 | * from stuffing other stolen allocations like the ring | |
14511 | * on top. This prevents some ugliness at boot time, and | |
14512 | * can even allow for smooth boot transitions if the BIOS | |
14513 | * fb is large enough for the active pipe configuration. | |
14514 | */ | |
5724dbd1 DL |
14515 | if (dev_priv->display.get_initial_plane_config) { |
14516 | dev_priv->display.get_initial_plane_config(crtc, | |
46f297fb JB |
14517 | &crtc->plane_config); |
14518 | /* | |
14519 | * If the fb is shared between multiple heads, we'll | |
14520 | * just get the first one. | |
14521 | */ | |
f6936e29 | 14522 | intel_find_initial_plane_obj(crtc, &crtc->plane_config); |
46f297fb | 14523 | } |
46f297fb | 14524 | } |
2c7111db CW |
14525 | } |
14526 | ||
7fad798e DV |
14527 | static void intel_enable_pipe_a(struct drm_device *dev) |
14528 | { | |
14529 | struct intel_connector *connector; | |
14530 | struct drm_connector *crt = NULL; | |
14531 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 14532 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
14533 | |
14534 | /* We can't just switch on the pipe A, we need to set things up with a | |
14535 | * proper mode and output configuration. As a gross hack, enable pipe A | |
14536 | * by enabling the load detect pipe once. */ | |
3a3371ff | 14537 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
14538 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
14539 | crt = &connector->base; | |
14540 | break; | |
14541 | } | |
14542 | } | |
14543 | ||
14544 | if (!crt) | |
14545 | return; | |
14546 | ||
208bf9fd | 14547 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
49172fee | 14548 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
14549 | } |
14550 | ||
fa555837 DV |
14551 | static bool |
14552 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
14553 | { | |
7eb552ae BW |
14554 | struct drm_device *dev = crtc->base.dev; |
14555 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 DV |
14556 | u32 reg, val; |
14557 | ||
7eb552ae | 14558 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
14559 | return true; |
14560 | ||
14561 | reg = DSPCNTR(!crtc->plane); | |
14562 | val = I915_READ(reg); | |
14563 | ||
14564 | if ((val & DISPLAY_PLANE_ENABLE) && | |
14565 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
14566 | return false; | |
14567 | ||
14568 | return true; | |
14569 | } | |
14570 | ||
24929352 DV |
14571 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
14572 | { | |
14573 | struct drm_device *dev = crtc->base.dev; | |
14574 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 | 14575 | u32 reg; |
24929352 | 14576 | |
24929352 | 14577 | /* Clear any frame start delays used for debugging left by the BIOS */ |
6e3c9717 | 14578 | reg = PIPECONF(crtc->config->cpu_transcoder); |
24929352 DV |
14579 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
14580 | ||
d3eaf884 | 14581 | /* restore vblank interrupts to correct state */ |
9625604c | 14582 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 VS |
14583 | if (crtc->active) { |
14584 | update_scanline_offset(crtc); | |
9625604c DV |
14585 | drm_crtc_vblank_on(&crtc->base); |
14586 | } | |
d3eaf884 | 14587 | |
24929352 | 14588 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
14589 | * disable the crtc (and hence change the state) if it is wrong. Note |
14590 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
14591 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
14592 | struct intel_connector *connector; |
14593 | bool plane; | |
14594 | ||
24929352 DV |
14595 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
14596 | crtc->base.base.id); | |
14597 | ||
14598 | /* Pipe has the wrong plane attached and the plane is active. | |
14599 | * Temporarily change the plane mapping and disable everything | |
14600 | * ... */ | |
14601 | plane = crtc->plane; | |
14602 | crtc->plane = !plane; | |
9c8958bc | 14603 | crtc->primary_enabled = true; |
24929352 DV |
14604 | dev_priv->display.crtc_disable(&crtc->base); |
14605 | crtc->plane = plane; | |
14606 | ||
14607 | /* ... and break all links. */ | |
3a3371ff | 14608 | for_each_intel_connector(dev, connector) { |
24929352 DV |
14609 | if (connector->encoder->base.crtc != &crtc->base) |
14610 | continue; | |
14611 | ||
7f1950fb EE |
14612 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
14613 | connector->base.encoder = NULL; | |
24929352 | 14614 | } |
7f1950fb EE |
14615 | /* multiple connectors may have the same encoder: |
14616 | * handle them and break crtc link separately */ | |
3a3371ff | 14617 | for_each_intel_connector(dev, connector) |
7f1950fb EE |
14618 | if (connector->encoder->base.crtc == &crtc->base) { |
14619 | connector->encoder->base.crtc = NULL; | |
14620 | connector->encoder->connectors_active = false; | |
14621 | } | |
24929352 DV |
14622 | |
14623 | WARN_ON(crtc->active); | |
83d65738 | 14624 | crtc->base.state->enable = false; |
24929352 DV |
14625 | crtc->base.enabled = false; |
14626 | } | |
24929352 | 14627 | |
7fad798e DV |
14628 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
14629 | crtc->pipe == PIPE_A && !crtc->active) { | |
14630 | /* BIOS forgot to enable pipe A, this mostly happens after | |
14631 | * resume. Force-enable the pipe to fix this, the update_dpms | |
14632 | * call below we restore the pipe to the right state, but leave | |
14633 | * the required bits on. */ | |
14634 | intel_enable_pipe_a(dev); | |
14635 | } | |
14636 | ||
24929352 DV |
14637 | /* Adjust the state of the output pipe according to whether we |
14638 | * have active connectors/encoders. */ | |
14639 | intel_crtc_update_dpms(&crtc->base); | |
14640 | ||
83d65738 | 14641 | if (crtc->active != crtc->base.state->enable) { |
24929352 DV |
14642 | struct intel_encoder *encoder; |
14643 | ||
14644 | /* This can happen either due to bugs in the get_hw_state | |
14645 | * functions or because the pipe is force-enabled due to the | |
14646 | * pipe A quirk. */ | |
14647 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
14648 | crtc->base.base.id, | |
83d65738 | 14649 | crtc->base.state->enable ? "enabled" : "disabled", |
24929352 DV |
14650 | crtc->active ? "enabled" : "disabled"); |
14651 | ||
83d65738 | 14652 | crtc->base.state->enable = crtc->active; |
24929352 DV |
14653 | crtc->base.enabled = crtc->active; |
14654 | ||
14655 | /* Because we only establish the connector -> encoder -> | |
14656 | * crtc links if something is active, this means the | |
14657 | * crtc is now deactivated. Break the links. connector | |
14658 | * -> encoder links are only establish when things are | |
14659 | * actually up, hence no need to break them. */ | |
14660 | WARN_ON(crtc->active); | |
14661 | ||
14662 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { | |
14663 | WARN_ON(encoder->connectors_active); | |
14664 | encoder->base.crtc = NULL; | |
14665 | } | |
14666 | } | |
c5ab3bc0 | 14667 | |
a3ed6aad | 14668 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
4cc31489 DV |
14669 | /* |
14670 | * We start out with underrun reporting disabled to avoid races. | |
14671 | * For correct bookkeeping mark this on active crtcs. | |
14672 | * | |
c5ab3bc0 DV |
14673 | * Also on gmch platforms we dont have any hardware bits to |
14674 | * disable the underrun reporting. Which means we need to start | |
14675 | * out with underrun reporting disabled also on inactive pipes, | |
14676 | * since otherwise we'll complain about the garbage we read when | |
14677 | * e.g. coming up after runtime pm. | |
14678 | * | |
4cc31489 DV |
14679 | * No protection against concurrent access is required - at |
14680 | * worst a fifo underrun happens which also sets this to false. | |
14681 | */ | |
14682 | crtc->cpu_fifo_underrun_disabled = true; | |
14683 | crtc->pch_fifo_underrun_disabled = true; | |
14684 | } | |
24929352 DV |
14685 | } |
14686 | ||
14687 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
14688 | { | |
14689 | struct intel_connector *connector; | |
14690 | struct drm_device *dev = encoder->base.dev; | |
14691 | ||
14692 | /* We need to check both for a crtc link (meaning that the | |
14693 | * encoder is active and trying to read from a pipe) and the | |
14694 | * pipe itself being active. */ | |
14695 | bool has_active_crtc = encoder->base.crtc && | |
14696 | to_intel_crtc(encoder->base.crtc)->active; | |
14697 | ||
14698 | if (encoder->connectors_active && !has_active_crtc) { | |
14699 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", | |
14700 | encoder->base.base.id, | |
8e329a03 | 14701 | encoder->base.name); |
24929352 DV |
14702 | |
14703 | /* Connector is active, but has no active pipe. This is | |
14704 | * fallout from our resume register restoring. Disable | |
14705 | * the encoder manually again. */ | |
14706 | if (encoder->base.crtc) { | |
14707 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
14708 | encoder->base.base.id, | |
8e329a03 | 14709 | encoder->base.name); |
24929352 | 14710 | encoder->disable(encoder); |
a62d1497 VS |
14711 | if (encoder->post_disable) |
14712 | encoder->post_disable(encoder); | |
24929352 | 14713 | } |
7f1950fb EE |
14714 | encoder->base.crtc = NULL; |
14715 | encoder->connectors_active = false; | |
24929352 DV |
14716 | |
14717 | /* Inconsistent output/port/pipe state happens presumably due to | |
14718 | * a bug in one of the get_hw_state functions. Or someplace else | |
14719 | * in our code, like the register restore mess on resume. Clamp | |
14720 | * things to off as a safer default. */ | |
3a3371ff | 14721 | for_each_intel_connector(dev, connector) { |
24929352 DV |
14722 | if (connector->encoder != encoder) |
14723 | continue; | |
7f1950fb EE |
14724 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
14725 | connector->base.encoder = NULL; | |
24929352 DV |
14726 | } |
14727 | } | |
14728 | /* Enabled encoders without active connectors will be fixed in | |
14729 | * the crtc fixup. */ | |
14730 | } | |
14731 | ||
04098753 | 14732 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
14733 | { |
14734 | struct drm_i915_private *dev_priv = dev->dev_private; | |
766aa1c4 | 14735 | u32 vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 14736 | |
04098753 ID |
14737 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
14738 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
14739 | i915_disable_vga(dev); | |
14740 | } | |
14741 | } | |
14742 | ||
14743 | void i915_redisable_vga(struct drm_device *dev) | |
14744 | { | |
14745 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14746 | ||
8dc8a27c PZ |
14747 | /* This function can be called both from intel_modeset_setup_hw_state or |
14748 | * at a very early point in our resume sequence, where the power well | |
14749 | * structures are not yet restored. Since this function is at a very | |
14750 | * paranoid "someone might have enabled VGA while we were not looking" | |
14751 | * level, just check if the power well is enabled instead of trying to | |
14752 | * follow the "don't touch the power well if we don't need it" policy | |
14753 | * the rest of the driver uses. */ | |
f458ebbc | 14754 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
14755 | return; |
14756 | ||
04098753 | 14757 | i915_redisable_vga_power_on(dev); |
0fde901f KM |
14758 | } |
14759 | ||
98ec7739 VS |
14760 | static bool primary_get_hw_state(struct intel_crtc *crtc) |
14761 | { | |
14762 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
14763 | ||
14764 | if (!crtc->active) | |
14765 | return false; | |
14766 | ||
14767 | return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE; | |
14768 | } | |
14769 | ||
30e984df | 14770 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
14771 | { |
14772 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14773 | enum pipe pipe; | |
24929352 DV |
14774 | struct intel_crtc *crtc; |
14775 | struct intel_encoder *encoder; | |
14776 | struct intel_connector *connector; | |
5358901f | 14777 | int i; |
24929352 | 14778 | |
d3fcc808 | 14779 | for_each_intel_crtc(dev, crtc) { |
6e3c9717 | 14780 | memset(crtc->config, 0, sizeof(*crtc->config)); |
3b117c8f | 14781 | |
6e3c9717 | 14782 | crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE; |
9953599b | 14783 | |
0e8ffe1b | 14784 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
6e3c9717 | 14785 | crtc->config); |
24929352 | 14786 | |
83d65738 | 14787 | crtc->base.state->enable = crtc->active; |
24929352 | 14788 | crtc->base.enabled = crtc->active; |
98ec7739 | 14789 | crtc->primary_enabled = primary_get_hw_state(crtc); |
24929352 DV |
14790 | |
14791 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
14792 | crtc->base.base.id, | |
14793 | crtc->active ? "enabled" : "disabled"); | |
14794 | } | |
14795 | ||
5358901f DV |
14796 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
14797 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
14798 | ||
3e369b76 ACO |
14799 | pll->on = pll->get_hw_state(dev_priv, pll, |
14800 | &pll->config.hw_state); | |
5358901f | 14801 | pll->active = 0; |
3e369b76 | 14802 | pll->config.crtc_mask = 0; |
d3fcc808 | 14803 | for_each_intel_crtc(dev, crtc) { |
1e6f2ddc | 14804 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) { |
5358901f | 14805 | pll->active++; |
3e369b76 | 14806 | pll->config.crtc_mask |= 1 << crtc->pipe; |
1e6f2ddc | 14807 | } |
5358901f | 14808 | } |
5358901f | 14809 | |
1e6f2ddc | 14810 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 14811 | pll->name, pll->config.crtc_mask, pll->on); |
bd2bb1b9 | 14812 | |
3e369b76 | 14813 | if (pll->config.crtc_mask) |
bd2bb1b9 | 14814 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
5358901f DV |
14815 | } |
14816 | ||
b2784e15 | 14817 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
14818 | pipe = 0; |
14819 | ||
14820 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
14821 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
14822 | encoder->base.crtc = &crtc->base; | |
6e3c9717 | 14823 | encoder->get_config(encoder, crtc->config); |
24929352 DV |
14824 | } else { |
14825 | encoder->base.crtc = NULL; | |
14826 | } | |
14827 | ||
14828 | encoder->connectors_active = false; | |
6f2bcceb | 14829 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 14830 | encoder->base.base.id, |
8e329a03 | 14831 | encoder->base.name, |
24929352 | 14832 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 14833 | pipe_name(pipe)); |
24929352 DV |
14834 | } |
14835 | ||
3a3371ff | 14836 | for_each_intel_connector(dev, connector) { |
24929352 DV |
14837 | if (connector->get_hw_state(connector)) { |
14838 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
14839 | connector->encoder->connectors_active = true; | |
14840 | connector->base.encoder = &connector->encoder->base; | |
14841 | } else { | |
14842 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
14843 | connector->base.encoder = NULL; | |
14844 | } | |
14845 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
14846 | connector->base.base.id, | |
c23cc417 | 14847 | connector->base.name, |
24929352 DV |
14848 | connector->base.encoder ? "enabled" : "disabled"); |
14849 | } | |
30e984df DV |
14850 | } |
14851 | ||
14852 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm | |
14853 | * and i915 state tracking structures. */ | |
14854 | void intel_modeset_setup_hw_state(struct drm_device *dev, | |
14855 | bool force_restore) | |
14856 | { | |
14857 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14858 | enum pipe pipe; | |
30e984df DV |
14859 | struct intel_crtc *crtc; |
14860 | struct intel_encoder *encoder; | |
35c95375 | 14861 | int i; |
30e984df DV |
14862 | |
14863 | intel_modeset_readout_hw_state(dev); | |
24929352 | 14864 | |
babea61d JB |
14865 | /* |
14866 | * Now that we have the config, copy it to each CRTC struct | |
14867 | * Note that this could go away if we move to using crtc_config | |
14868 | * checking everywhere. | |
14869 | */ | |
d3fcc808 | 14870 | for_each_intel_crtc(dev, crtc) { |
d330a953 | 14871 | if (crtc->active && i915.fastboot) { |
6e3c9717 ACO |
14872 | intel_mode_from_pipe_config(&crtc->base.mode, |
14873 | crtc->config); | |
babea61d JB |
14874 | DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", |
14875 | crtc->base.base.id); | |
14876 | drm_mode_debug_printmodeline(&crtc->base.mode); | |
14877 | } | |
14878 | } | |
14879 | ||
24929352 | 14880 | /* HW state is read out, now we need to sanitize this mess. */ |
b2784e15 | 14881 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
14882 | intel_sanitize_encoder(encoder); |
14883 | } | |
14884 | ||
055e393f | 14885 | for_each_pipe(dev_priv, pipe) { |
24929352 DV |
14886 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
14887 | intel_sanitize_crtc(crtc); | |
6e3c9717 ACO |
14888 | intel_dump_pipe_config(crtc, crtc->config, |
14889 | "[setup_hw_state]"); | |
24929352 | 14890 | } |
9a935856 | 14891 | |
d29b2f9d ACO |
14892 | intel_modeset_update_connector_atomic_state(dev); |
14893 | ||
35c95375 DV |
14894 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
14895 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
14896 | ||
14897 | if (!pll->on || pll->active) | |
14898 | continue; | |
14899 | ||
14900 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
14901 | ||
14902 | pll->disable(dev_priv, pll); | |
14903 | pll->on = false; | |
14904 | } | |
14905 | ||
3078999f PB |
14906 | if (IS_GEN9(dev)) |
14907 | skl_wm_get_hw_state(dev); | |
14908 | else if (HAS_PCH_SPLIT(dev)) | |
243e6a44 VS |
14909 | ilk_wm_get_hw_state(dev); |
14910 | ||
45e2b5f6 | 14911 | if (force_restore) { |
7d0bc1ea VS |
14912 | i915_redisable_vga(dev); |
14913 | ||
f30da187 DV |
14914 | /* |
14915 | * We need to use raw interfaces for restoring state to avoid | |
14916 | * checking (bogus) intermediate states. | |
14917 | */ | |
055e393f | 14918 | for_each_pipe(dev_priv, pipe) { |
b5644d05 JB |
14919 | struct drm_crtc *crtc = |
14920 | dev_priv->pipe_to_crtc_mapping[pipe]; | |
f30da187 | 14921 | |
83a57153 | 14922 | intel_crtc_restore_mode(crtc); |
45e2b5f6 DV |
14923 | } |
14924 | } else { | |
14925 | intel_modeset_update_staged_output_state(dev); | |
14926 | } | |
8af6cf88 DV |
14927 | |
14928 | intel_modeset_check_state(dev); | |
2c7111db CW |
14929 | } |
14930 | ||
14931 | void intel_modeset_gem_init(struct drm_device *dev) | |
14932 | { | |
92122789 | 14933 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd | 14934 | struct drm_crtc *c; |
2ff8fde1 | 14935 | struct drm_i915_gem_object *obj; |
484b41dd | 14936 | |
ae48434c ID |
14937 | mutex_lock(&dev->struct_mutex); |
14938 | intel_init_gt_powersave(dev); | |
14939 | mutex_unlock(&dev->struct_mutex); | |
14940 | ||
92122789 JB |
14941 | /* |
14942 | * There may be no VBT; and if the BIOS enabled SSC we can | |
14943 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
14944 | * BIOS isn't using it, don't assume it will work even if the VBT | |
14945 | * indicates as much. | |
14946 | */ | |
14947 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
14948 | dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & | |
14949 | DREF_SSC1_ENABLE); | |
14950 | ||
1833b134 | 14951 | intel_modeset_init_hw(dev); |
02e792fb DV |
14952 | |
14953 | intel_setup_overlay(dev); | |
484b41dd JB |
14954 | |
14955 | /* | |
14956 | * Make sure any fbs we allocated at startup are properly | |
14957 | * pinned & fenced. When we do the allocation it's too early | |
14958 | * for this. | |
14959 | */ | |
14960 | mutex_lock(&dev->struct_mutex); | |
70e1e0ec | 14961 | for_each_crtc(dev, c) { |
2ff8fde1 MR |
14962 | obj = intel_fb_obj(c->primary->fb); |
14963 | if (obj == NULL) | |
484b41dd JB |
14964 | continue; |
14965 | ||
850c4cdc TU |
14966 | if (intel_pin_and_fence_fb_obj(c->primary, |
14967 | c->primary->fb, | |
82bc3b2d | 14968 | c->primary->state, |
850c4cdc | 14969 | NULL)) { |
484b41dd JB |
14970 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
14971 | to_intel_crtc(c)->pipe); | |
66e514c1 DA |
14972 | drm_framebuffer_unreference(c->primary->fb); |
14973 | c->primary->fb = NULL; | |
afd65eb4 | 14974 | update_state_fb(c->primary); |
484b41dd JB |
14975 | } |
14976 | } | |
14977 | mutex_unlock(&dev->struct_mutex); | |
0962c3c9 VS |
14978 | |
14979 | intel_backlight_register(dev); | |
79e53945 JB |
14980 | } |
14981 | ||
4932e2c3 ID |
14982 | void intel_connector_unregister(struct intel_connector *intel_connector) |
14983 | { | |
14984 | struct drm_connector *connector = &intel_connector->base; | |
14985 | ||
14986 | intel_panel_destroy_backlight(connector); | |
34ea3d38 | 14987 | drm_connector_unregister(connector); |
4932e2c3 ID |
14988 | } |
14989 | ||
79e53945 JB |
14990 | void intel_modeset_cleanup(struct drm_device *dev) |
14991 | { | |
652c393a | 14992 | struct drm_i915_private *dev_priv = dev->dev_private; |
d9255d57 | 14993 | struct drm_connector *connector; |
652c393a | 14994 | |
2eb5252e ID |
14995 | intel_disable_gt_powersave(dev); |
14996 | ||
0962c3c9 VS |
14997 | intel_backlight_unregister(dev); |
14998 | ||
fd0c0642 DV |
14999 | /* |
15000 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 15001 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
15002 | * experience fancy races otherwise. |
15003 | */ | |
2aeb7d3a | 15004 | intel_irq_uninstall(dev_priv); |
eb21b92b | 15005 | |
fd0c0642 DV |
15006 | /* |
15007 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
15008 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
15009 | */ | |
f87ea761 | 15010 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 15011 | |
652c393a JB |
15012 | mutex_lock(&dev->struct_mutex); |
15013 | ||
723bfd70 JB |
15014 | intel_unregister_dsm_handler(); |
15015 | ||
7ff0ebcc | 15016 | intel_fbc_disable(dev); |
e70236a8 | 15017 | |
69341a5e KH |
15018 | mutex_unlock(&dev->struct_mutex); |
15019 | ||
1630fe75 CW |
15020 | /* flush any delayed tasks or pending work */ |
15021 | flush_scheduled_work(); | |
15022 | ||
db31af1d JN |
15023 | /* destroy the backlight and sysfs files before encoders/connectors */ |
15024 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4932e2c3 ID |
15025 | struct intel_connector *intel_connector; |
15026 | ||
15027 | intel_connector = to_intel_connector(connector); | |
15028 | intel_connector->unregister(intel_connector); | |
db31af1d | 15029 | } |
d9255d57 | 15030 | |
79e53945 | 15031 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
15032 | |
15033 | intel_cleanup_overlay(dev); | |
ae48434c ID |
15034 | |
15035 | mutex_lock(&dev->struct_mutex); | |
15036 | intel_cleanup_gt_powersave(dev); | |
15037 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
15038 | } |
15039 | ||
f1c79df3 ZW |
15040 | /* |
15041 | * Return which encoder is currently attached for connector. | |
15042 | */ | |
df0e9248 | 15043 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 15044 | { |
df0e9248 CW |
15045 | return &intel_attached_encoder(connector)->base; |
15046 | } | |
f1c79df3 | 15047 | |
df0e9248 CW |
15048 | void intel_connector_attach_encoder(struct intel_connector *connector, |
15049 | struct intel_encoder *encoder) | |
15050 | { | |
15051 | connector->encoder = encoder; | |
15052 | drm_mode_connector_attach_encoder(&connector->base, | |
15053 | &encoder->base); | |
79e53945 | 15054 | } |
28d52043 DA |
15055 | |
15056 | /* | |
15057 | * set vga decode state - true == enable VGA decode | |
15058 | */ | |
15059 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
15060 | { | |
15061 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 15062 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
15063 | u16 gmch_ctrl; |
15064 | ||
75fa041d CW |
15065 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
15066 | DRM_ERROR("failed to read control word\n"); | |
15067 | return -EIO; | |
15068 | } | |
15069 | ||
c0cc8a55 CW |
15070 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
15071 | return 0; | |
15072 | ||
28d52043 DA |
15073 | if (state) |
15074 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
15075 | else | |
15076 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
15077 | |
15078 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
15079 | DRM_ERROR("failed to write control word\n"); | |
15080 | return -EIO; | |
15081 | } | |
15082 | ||
28d52043 DA |
15083 | return 0; |
15084 | } | |
c4a1d9e4 | 15085 | |
c4a1d9e4 | 15086 | struct intel_display_error_state { |
ff57f1b0 PZ |
15087 | |
15088 | u32 power_well_driver; | |
15089 | ||
63b66e5b CW |
15090 | int num_transcoders; |
15091 | ||
c4a1d9e4 CW |
15092 | struct intel_cursor_error_state { |
15093 | u32 control; | |
15094 | u32 position; | |
15095 | u32 base; | |
15096 | u32 size; | |
52331309 | 15097 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15098 | |
15099 | struct intel_pipe_error_state { | |
ddf9c536 | 15100 | bool power_domain_on; |
c4a1d9e4 | 15101 | u32 source; |
f301b1e1 | 15102 | u32 stat; |
52331309 | 15103 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15104 | |
15105 | struct intel_plane_error_state { | |
15106 | u32 control; | |
15107 | u32 stride; | |
15108 | u32 size; | |
15109 | u32 pos; | |
15110 | u32 addr; | |
15111 | u32 surface; | |
15112 | u32 tile_offset; | |
52331309 | 15113 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
15114 | |
15115 | struct intel_transcoder_error_state { | |
ddf9c536 | 15116 | bool power_domain_on; |
63b66e5b CW |
15117 | enum transcoder cpu_transcoder; |
15118 | ||
15119 | u32 conf; | |
15120 | ||
15121 | u32 htotal; | |
15122 | u32 hblank; | |
15123 | u32 hsync; | |
15124 | u32 vtotal; | |
15125 | u32 vblank; | |
15126 | u32 vsync; | |
15127 | } transcoder[4]; | |
c4a1d9e4 CW |
15128 | }; |
15129 | ||
15130 | struct intel_display_error_state * | |
15131 | intel_display_capture_error_state(struct drm_device *dev) | |
15132 | { | |
fbee40df | 15133 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 | 15134 | struct intel_display_error_state *error; |
63b66e5b CW |
15135 | int transcoders[] = { |
15136 | TRANSCODER_A, | |
15137 | TRANSCODER_B, | |
15138 | TRANSCODER_C, | |
15139 | TRANSCODER_EDP, | |
15140 | }; | |
c4a1d9e4 CW |
15141 | int i; |
15142 | ||
63b66e5b CW |
15143 | if (INTEL_INFO(dev)->num_pipes == 0) |
15144 | return NULL; | |
15145 | ||
9d1cb914 | 15146 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
15147 | if (error == NULL) |
15148 | return NULL; | |
15149 | ||
190be112 | 15150 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
15151 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
15152 | ||
055e393f | 15153 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 15154 | error->pipe[i].power_domain_on = |
f458ebbc DV |
15155 | __intel_display_power_is_enabled(dev_priv, |
15156 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 15157 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
15158 | continue; |
15159 | ||
5efb3e28 VS |
15160 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
15161 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
15162 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
15163 | |
15164 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
15165 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 15166 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 15167 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
15168 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
15169 | } | |
ca291363 PZ |
15170 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
15171 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
15172 | if (INTEL_INFO(dev)->gen >= 4) { |
15173 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
15174 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
15175 | } | |
15176 | ||
c4a1d9e4 | 15177 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 15178 | |
3abfce77 | 15179 | if (HAS_GMCH_DISPLAY(dev)) |
f301b1e1 | 15180 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
15181 | } |
15182 | ||
15183 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
15184 | if (HAS_DDI(dev_priv->dev)) | |
15185 | error->num_transcoders++; /* Account for eDP. */ | |
15186 | ||
15187 | for (i = 0; i < error->num_transcoders; i++) { | |
15188 | enum transcoder cpu_transcoder = transcoders[i]; | |
15189 | ||
ddf9c536 | 15190 | error->transcoder[i].power_domain_on = |
f458ebbc | 15191 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 15192 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 15193 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
15194 | continue; |
15195 | ||
63b66e5b CW |
15196 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
15197 | ||
15198 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
15199 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
15200 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
15201 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
15202 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
15203 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
15204 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
15205 | } |
15206 | ||
15207 | return error; | |
15208 | } | |
15209 | ||
edc3d884 MK |
15210 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
15211 | ||
c4a1d9e4 | 15212 | void |
edc3d884 | 15213 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
15214 | struct drm_device *dev, |
15215 | struct intel_display_error_state *error) | |
15216 | { | |
055e393f | 15217 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
15218 | int i; |
15219 | ||
63b66e5b CW |
15220 | if (!error) |
15221 | return; | |
15222 | ||
edc3d884 | 15223 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 15224 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 15225 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 15226 | error->power_well_driver); |
055e393f | 15227 | for_each_pipe(dev_priv, i) { |
edc3d884 | 15228 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 ID |
15229 | err_printf(m, " Power: %s\n", |
15230 | error->pipe[i].power_domain_on ? "on" : "off"); | |
edc3d884 | 15231 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 15232 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
15233 | |
15234 | err_printf(m, "Plane [%d]:\n", i); | |
15235 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
15236 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 15237 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
15238 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
15239 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 15240 | } |
4b71a570 | 15241 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 15242 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 15243 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
15244 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
15245 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
15246 | } |
15247 | ||
edc3d884 MK |
15248 | err_printf(m, "Cursor [%d]:\n", i); |
15249 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
15250 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
15251 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 15252 | } |
63b66e5b CW |
15253 | |
15254 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 15255 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b | 15256 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 ID |
15257 | err_printf(m, " Power: %s\n", |
15258 | error->transcoder[i].power_domain_on ? "on" : "off"); | |
63b66e5b CW |
15259 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
15260 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
15261 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
15262 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
15263 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
15264 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
15265 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
15266 | } | |
c4a1d9e4 | 15267 | } |
e2fcdaa9 VS |
15268 | |
15269 | void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file) | |
15270 | { | |
15271 | struct intel_crtc *crtc; | |
15272 | ||
15273 | for_each_intel_crtc(dev, crtc) { | |
15274 | struct intel_unpin_work *work; | |
e2fcdaa9 | 15275 | |
5e2d7afc | 15276 | spin_lock_irq(&dev->event_lock); |
e2fcdaa9 VS |
15277 | |
15278 | work = crtc->unpin_work; | |
15279 | ||
15280 | if (work && work->event && | |
15281 | work->event->base.file_priv == file) { | |
15282 | kfree(work->event); | |
15283 | work->event = NULL; | |
15284 | } | |
15285 | ||
5e2d7afc | 15286 | spin_unlock_irq(&dev->event_lock); |
e2fcdaa9 VS |
15287 | } |
15288 | } |