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drm/i915: add encoder->pre_pll_enable callback
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 47
48typedef struct {
0206e353
AJ		 49 /* given values */
50 int n;
51 int m1, m2;
52 int p1, p2;
53 /* derived values */
54 int dot;
55 int vco;
56 int m;
57 int p;
79e53945
JB		 58} intel_clock_t;
59
60typedef struct {
0206e353 61 int min, max;
79e53945
JB		 62} intel_range_t;
63
64typedef struct {
0206e353
AJ		 65 int dot_limit;
66 int p2_slow, p2_fast;
79e53945
JB		 67} intel_p2_t;
68
69#define INTEL_P2_NUM 2
d4906093
ML		 70typedef struct intel_limit intel_limit_t;
71struct intel_limit {
0206e353
AJ		 72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
73 intel_p2_t p2;
74 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 75 int, int, intel_clock_t *, intel_clock_t *);
d4906093 76};
79e53945 77
2377b741
JB		 78/* FDI */
79#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
80
d2acd215
DV		 81int
82intel_pch_rawclk(struct drm_device *dev)
83{
84 struct drm_i915_private *dev_priv = dev->dev_private;
85
86 WARN_ON(!HAS_PCH_SPLIT(dev));
87
88 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
89}
90
d4906093
ML		 91static bool
92intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 93 int target, int refclk, intel_clock_t *match_clock,
94 intel_clock_t *best_clock);
d4906093
ML		 95static bool
96intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 97 int target, int refclk, intel_clock_t *match_clock,
98 intel_clock_t *best_clock);
79e53945 99
a4fc5ed6
KP		 100static bool
101intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 102 int target, int refclk, intel_clock_t *match_clock,
103 intel_clock_t *best_clock);
5eb08b69 104static bool
f2b115e6 105intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 106 int target, int refclk, intel_clock_t *match_clock,
107 intel_clock_t *best_clock);
a4fc5ed6 108
a0c4da24
JB		 109static bool
110intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
111 int target, int refclk, intel_clock_t *match_clock,
112 intel_clock_t *best_clock);
113
021357ac
CW		 114static inline u32 /* units of 100MHz */
115intel_fdi_link_freq(struct drm_device *dev)
116{
8b99e68c
CW		 117 if (IS_GEN5(dev)) {
118 struct drm_i915_private *dev_priv = dev->dev_private;
119 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
120 } else
121 return 27;
021357ac
CW		 122}
123
e4b36699 124static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 125 .dot = { .min = 25000, .max = 350000 },
126 .vco = { .min = 930000, .max = 1400000 },
127 .n = { .min = 3, .max = 16 },
128 .m = { .min = 96, .max = 140 },
129 .m1 = { .min = 18, .max = 26 },
130 .m2 = { .min = 6, .max = 16 },
131 .p = { .min = 4, .max = 128 },
132 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 133 .p2 = { .dot_limit = 165000,
134 .p2_slow = 4, .p2_fast = 2 },
d4906093 135 .find_pll = intel_find_best_PLL,
e4b36699
KP		 136};
137
138static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 139 .dot = { .min = 25000, .max = 350000 },
140 .vco = { .min = 930000, .max = 1400000 },
141 .n = { .min = 3, .max = 16 },
142 .m = { .min = 96, .max = 140 },
143 .m1 = { .min = 18, .max = 26 },
144 .m2 = { .min = 6, .max = 16 },
145 .p = { .min = 4, .max = 128 },
146 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 147 .p2 = { .dot_limit = 165000,
148 .p2_slow = 14, .p2_fast = 7 },
d4906093 149 .find_pll = intel_find_best_PLL,
e4b36699 150};
273e27ca 151
e4b36699 152static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 153 .dot = { .min = 20000, .max = 400000 },
154 .vco = { .min = 1400000, .max = 2800000 },
155 .n = { .min = 1, .max = 6 },
156 .m = { .min = 70, .max = 120 },
157 .m1 = { .min = 10, .max = 22 },
158 .m2 = { .min = 5, .max = 9 },
159 .p = { .min = 5, .max = 80 },
160 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 161 .p2 = { .dot_limit = 200000,
162 .p2_slow = 10, .p2_fast = 5 },
d4906093 163 .find_pll = intel_find_best_PLL,
e4b36699
KP		 164};
165
166static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 167 .dot = { .min = 20000, .max = 400000 },
168 .vco = { .min = 1400000, .max = 2800000 },
169 .n = { .min = 1, .max = 6 },
170 .m = { .min = 70, .max = 120 },
171 .m1 = { .min = 10, .max = 22 },
172 .m2 = { .min = 5, .max = 9 },
173 .p = { .min = 7, .max = 98 },
174 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 175 .p2 = { .dot_limit = 112000,
176 .p2_slow = 14, .p2_fast = 7 },
d4906093 177 .find_pll = intel_find_best_PLL,
e4b36699
KP		 178};
179
273e27ca 180
e4b36699 181static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 182 .dot = { .min = 25000, .max = 270000 },
183 .vco = { .min = 1750000, .max = 3500000},
184 .n = { .min = 1, .max = 4 },
185 .m = { .min = 104, .max = 138 },
186 .m1 = { .min = 17, .max = 23 },
187 .m2 = { .min = 5, .max = 11 },
188 .p = { .min = 10, .max = 30 },
189 .p1 = { .min = 1, .max = 3},
190 .p2 = { .dot_limit = 270000,
191 .p2_slow = 10,
192 .p2_fast = 10
044c7c41 193 },
d4906093 194 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 195};
196
197static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 198 .dot = { .min = 22000, .max = 400000 },
199 .vco = { .min = 1750000, .max = 3500000},
200 .n = { .min = 1, .max = 4 },
201 .m = { .min = 104, .max = 138 },
202 .m1 = { .min = 16, .max = 23 },
203 .m2 = { .min = 5, .max = 11 },
204 .p = { .min = 5, .max = 80 },
205 .p1 = { .min = 1, .max = 8},
206 .p2 = { .dot_limit = 165000,
207 .p2_slow = 10, .p2_fast = 5 },
d4906093 208 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 209};
210
211static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 212 .dot = { .min = 20000, .max = 115000 },
213 .vco = { .min = 1750000, .max = 3500000 },
214 .n = { .min = 1, .max = 3 },
215 .m = { .min = 104, .max = 138 },
216 .m1 = { .min = 17, .max = 23 },
217 .m2 = { .min = 5, .max = 11 },
218 .p = { .min = 28, .max = 112 },
219 .p1 = { .min = 2, .max = 8 },
220 .p2 = { .dot_limit = 0,
221 .p2_slow = 14, .p2_fast = 14
044c7c41 222 },
d4906093 223 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 224};
225
226static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 227 .dot = { .min = 80000, .max = 224000 },
228 .vco = { .min = 1750000, .max = 3500000 },
229 .n = { .min = 1, .max = 3 },
230 .m = { .min = 104, .max = 138 },
231 .m1 = { .min = 17, .max = 23 },
232 .m2 = { .min = 5, .max = 11 },
233 .p = { .min = 14, .max = 42 },
234 .p1 = { .min = 2, .max = 6 },
235 .p2 = { .dot_limit = 0,
236 .p2_slow = 7, .p2_fast = 7
044c7c41 237 },
d4906093 238 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 239};
240
241static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 242 .dot = { .min = 161670, .max = 227000 },
243 .vco = { .min = 1750000, .max = 3500000},
244 .n = { .min = 1, .max = 2 },
245 .m = { .min = 97, .max = 108 },
246 .m1 = { .min = 0x10, .max = 0x12 },
247 .m2 = { .min = 0x05, .max = 0x06 },
248 .p = { .min = 10, .max = 20 },
249 .p1 = { .min = 1, .max = 2},
250 .p2 = { .dot_limit = 0,
273e27ca 251 .p2_slow = 10, .p2_fast = 10 },
0206e353 252 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 253};
254
f2b115e6 255static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 256 .dot = { .min = 20000, .max = 400000},
257 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 258 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 259 .n = { .min = 3, .max = 6 },
260 .m = { .min = 2, .max = 256 },
273e27ca 261 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 262 .m1 = { .min = 0, .max = 0 },
263 .m2 = { .min = 0, .max = 254 },
264 .p = { .min = 5, .max = 80 },
265 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 266 .p2 = { .dot_limit = 200000,
267 .p2_slow = 10, .p2_fast = 5 },
6115707b 268 .find_pll = intel_find_best_PLL,
e4b36699
KP		 269};
270
f2b115e6 271static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 272 .dot = { .min = 20000, .max = 400000 },
273 .vco = { .min = 1700000, .max = 3500000 },
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 .m1 = { .min = 0, .max = 0 },
277 .m2 = { .min = 0, .max = 254 },
278 .p = { .min = 7, .max = 112 },
279 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 280 .p2 = { .dot_limit = 112000,
281 .p2_slow = 14, .p2_fast = 14 },
6115707b 282 .find_pll = intel_find_best_PLL,
e4b36699
KP		 283};
284
273e27ca
EA		 285/* Ironlake / Sandybridge
286 *
287 * We calculate clock using (register_value + 2) for N/M1/M2, so here
288 * the range value for them is (actual_value - 2).
289 */
b91ad0ec 290static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 291 .dot = { .min = 25000, .max = 350000 },
292 .vco = { .min = 1760000, .max = 3510000 },
293 .n = { .min = 1, .max = 5 },
294 .m = { .min = 79, .max = 127 },
295 .m1 = { .min = 12, .max = 22 },
296 .m2 = { .min = 5, .max = 9 },
297 .p = { .min = 5, .max = 80 },
298 .p1 = { .min = 1, .max = 8 },
299 .p2 = { .dot_limit = 225000,
300 .p2_slow = 10, .p2_fast = 5 },
4547668a 301 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 302};
303
b91ad0ec 304static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 305 .dot = { .min = 25000, .max = 350000 },
306 .vco = { .min = 1760000, .max = 3510000 },
307 .n = { .min = 1, .max = 3 },
308 .m = { .min = 79, .max = 118 },
309 .m1 = { .min = 12, .max = 22 },
310 .m2 = { .min = 5, .max = 9 },
311 .p = { .min = 28, .max = 112 },
312 .p1 = { .min = 2, .max = 8 },
313 .p2 = { .dot_limit = 225000,
314 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 315 .find_pll = intel_g4x_find_best_PLL,
316};
317
318static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 319 .dot = { .min = 25000, .max = 350000 },
320 .vco = { .min = 1760000, .max = 3510000 },
321 .n = { .min = 1, .max = 3 },
322 .m = { .min = 79, .max = 127 },
323 .m1 = { .min = 12, .max = 22 },
324 .m2 = { .min = 5, .max = 9 },
325 .p = { .min = 14, .max = 56 },
326 .p1 = { .min = 2, .max = 8 },
327 .p2 = { .dot_limit = 225000,
328 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 329 .find_pll = intel_g4x_find_best_PLL,
330};
331
273e27ca 332/* LVDS 100mhz refclk limits. */
b91ad0ec 333static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 334 .dot = { .min = 25000, .max = 350000 },
335 .vco = { .min = 1760000, .max = 3510000 },
336 .n = { .min = 1, .max = 2 },
337 .m = { .min = 79, .max = 126 },
338 .m1 = { .min = 12, .max = 22 },
339 .m2 = { .min = 5, .max = 9 },
340 .p = { .min = 28, .max = 112 },
0206e353 341 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 342 .p2 = { .dot_limit = 225000,
343 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 344 .find_pll = intel_g4x_find_best_PLL,
345};
346
347static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 348 .dot = { .min = 25000, .max = 350000 },
349 .vco = { .min = 1760000, .max = 3510000 },
350 .n = { .min = 1, .max = 3 },
351 .m = { .min = 79, .max = 126 },
352 .m1 = { .min = 12, .max = 22 },
353 .m2 = { .min = 5, .max = 9 },
354 .p = { .min = 14, .max = 42 },
0206e353 355 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 356 .p2 = { .dot_limit = 225000,
357 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 358 .find_pll = intel_g4x_find_best_PLL,
359};
360
361static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 362 .dot = { .min = 25000, .max = 350000 },
363 .vco = { .min = 1760000, .max = 3510000},
364 .n = { .min = 1, .max = 2 },
365 .m = { .min = 81, .max = 90 },
366 .m1 = { .min = 12, .max = 22 },
367 .m2 = { .min = 5, .max = 9 },
368 .p = { .min = 10, .max = 20 },
369 .p1 = { .min = 1, .max = 2},
370 .p2 = { .dot_limit = 0,
273e27ca 371 .p2_slow = 10, .p2_fast = 10 },
0206e353 372 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 373};
374
a0c4da24
JB		 375static const intel_limit_t intel_limits_vlv_dac = {
376 .dot = { .min = 25000, .max = 270000 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m = { .min = 22, .max = 450 }, /* guess */
380 .m1 = { .min = 2, .max = 3 },
381 .m2 = { .min = 11, .max = 156 },
382 .p = { .min = 10, .max = 30 },
383 .p1 = { .min = 2, .max = 3 },
384 .p2 = { .dot_limit = 270000,
385 .p2_slow = 2, .p2_fast = 20 },
386 .find_pll = intel_vlv_find_best_pll,
387};
388
389static const intel_limit_t intel_limits_vlv_hdmi = {
390 .dot = { .min = 20000, .max = 165000 },
17dc9257 391 .vco = { .min = 4000000, .max = 5994000},
a0c4da24
JB		 392 .n = { .min = 1, .max = 7 },
393 .m = { .min = 60, .max = 300 }, /* guess */
394 .m1 = { .min = 2, .max = 3 },
395 .m2 = { .min = 11, .max = 156 },
396 .p = { .min = 10, .max = 30 },
397 .p1 = { .min = 2, .max = 3 },
398 .p2 = { .dot_limit = 270000,
399 .p2_slow = 2, .p2_fast = 20 },
400 .find_pll = intel_vlv_find_best_pll,
401};
402
403static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 404 .dot = { .min = 25000, .max = 270000 },
405 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 406 .n = { .min = 1, .max = 7 },
74a4dd2e 407 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 408 .m1 = { .min = 2, .max = 3 },
409 .m2 = { .min = 11, .max = 156 },
410 .p = { .min = 10, .max = 30 },
411 .p1 = { .min = 2, .max = 3 },
412 .p2 = { .dot_limit = 270000,
413 .p2_slow = 2, .p2_fast = 20 },
414 .find_pll = intel_vlv_find_best_pll,
415};
416
57f350b6
JB		 417u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
418{
419 unsigned long flags;
420 u32 val = 0;
421
422 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
423 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
424 DRM_ERROR("DPIO idle wait timed out\n");
425 goto out_unlock;
426 }
427
428 I915_WRITE(DPIO_REG, reg);
429 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
430 DPIO_BYTE);
431 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
432 DRM_ERROR("DPIO read wait timed out\n");
433 goto out_unlock;
434 }
435 val = I915_READ(DPIO_DATA);
436
437out_unlock:
438 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
439 return val;
440}
441
a0c4da24
JB		 442static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
443 u32 val)
444{
445 unsigned long flags;
446
447 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
448 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
449 DRM_ERROR("DPIO idle wait timed out\n");
450 goto out_unlock;
451 }
452
453 I915_WRITE(DPIO_DATA, val);
454 I915_WRITE(DPIO_REG, reg);
455 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
456 DPIO_BYTE);
457 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
458 DRM_ERROR("DPIO write wait timed out\n");
459
460out_unlock:
461 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
462}
463
57f350b6
JB		 464static void vlv_init_dpio(struct drm_device *dev)
465{
466 struct drm_i915_private *dev_priv = dev->dev_private;
467
468 /* Reset the DPIO config */
469 I915_WRITE(DPIO_CTL, 0);
470 POSTING_READ(DPIO_CTL);
471 I915_WRITE(DPIO_CTL, 1);
472 POSTING_READ(DPIO_CTL);
473}
474
618563e3
DV		 475static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
476{
477 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
478 return 1;
479}
480
481static const struct dmi_system_id intel_dual_link_lvds[] = {
482 {
483 .callback = intel_dual_link_lvds_callback,
484 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
485 .matches = {
486 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
487 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
488 },
489 },
490 { } /* terminating entry */
491};
492
b0354385
TI		 493static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
494 unsigned int reg)
495{
496 unsigned int val;
497
121d527a
TI		 498 /* use the module option value if specified */
499 if (i915_lvds_channel_mode > 0)
500 return i915_lvds_channel_mode == 2;
501
618563e3
DV		 502 if (dmi_check_system(intel_dual_link_lvds))
503 return true;
504
b0354385
TI		 505 if (dev_priv->lvds_val)
506 val = dev_priv->lvds_val;
507 else {
508 /* BIOS should set the proper LVDS register value at boot, but
509 * in reality, it doesn't set the value when the lid is closed;
510 * we need to check "the value to be set" in VBT when LVDS
511 * register is uninitialized.
512 */
513 val = I915_READ(reg);
14d94a3d 514 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
b0354385
TI		 515 val = dev_priv->bios_lvds_val;
516 dev_priv->lvds_val = val;
517 }
518 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
519}
520
1b894b59
CW		 521static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
522 int refclk)
2c07245f 523{
b91ad0ec
ZW		 524 struct drm_device *dev = crtc->dev;
525 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 526 const intel_limit_t *limit;
b91ad0ec
ZW		 527
528 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 529 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
b91ad0ec 530 /* LVDS dual channel */
1b894b59 531 if (refclk == 100000)
b91ad0ec
ZW		 532 limit = &intel_limits_ironlake_dual_lvds_100m;
533 else
534 limit = &intel_limits_ironlake_dual_lvds;
535 } else {
1b894b59 536 if (refclk == 100000)
b91ad0ec
ZW		 537 limit = &intel_limits_ironlake_single_lvds_100m;
538 else
539 limit = &intel_limits_ironlake_single_lvds;
540 }
541 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
547dc041 542 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
4547668a 543 limit = &intel_limits_ironlake_display_port;
2c07245f 544 else
b91ad0ec 545 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 546
547 return limit;
548}
549
044c7c41
ML		 550static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
551{
552 struct drm_device *dev = crtc->dev;
553 struct drm_i915_private *dev_priv = dev->dev_private;
554 const intel_limit_t *limit;
555
556 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 557 if (is_dual_link_lvds(dev_priv, LVDS))
044c7c41 558 /* LVDS with dual channel */
e4b36699 559 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 560 else
561 /* LVDS with dual channel */
e4b36699 562 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 563 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
564 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 565 limit = &intel_limits_g4x_hdmi;
044c7c41 566 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 567 limit = &intel_limits_g4x_sdvo;
0206e353 568 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 569 limit = &intel_limits_g4x_display_port;
044c7c41 570 } else /* The option is for other outputs */
e4b36699 571 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 572
573 return limit;
574}
575
1b894b59 576static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 577{
578 struct drm_device *dev = crtc->dev;
579 const intel_limit_t *limit;
580
bad720ff 581 if (HAS_PCH_SPLIT(dev))
1b894b59 582 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 583 else if (IS_G4X(dev)) {
044c7c41 584 limit = intel_g4x_limit(crtc);
f2b115e6 585 } else if (IS_PINEVIEW(dev)) {
2177832f 586 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 587 limit = &intel_limits_pineview_lvds;
2177832f 588 else
f2b115e6 589 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 590 } else if (IS_VALLEYVIEW(dev)) {
591 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
592 limit = &intel_limits_vlv_dac;
593 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
594 limit = &intel_limits_vlv_hdmi;
595 else
596 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 597 } else if (!IS_GEN2(dev)) {
598 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
599 limit = &intel_limits_i9xx_lvds;
600 else
601 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 602 } else {
603 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 604 limit = &intel_limits_i8xx_lvds;
79e53945 605 else
e4b36699 606 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 607 }
608 return limit;
609}
610
f2b115e6
AJ		 611/* m1 is reserved as 0 in Pineview, n is a ring counter */
612static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 613{
2177832f
SL		 614 clock->m = clock->m2 + 2;
615 clock->p = clock->p1 * clock->p2;
616 clock->vco = refclk * clock->m / clock->n;
617 clock->dot = clock->vco / clock->p;
618}
619
620static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
621{
f2b115e6
AJ		 622 if (IS_PINEVIEW(dev)) {
623 pineview_clock(refclk, clock);
2177832f
SL		 624 return;
625 }
79e53945
JB		 626 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
627 clock->p = clock->p1 * clock->p2;
628 clock->vco = refclk * clock->m / (clock->n + 2);
629 clock->dot = clock->vco / clock->p;
630}
631
79e53945
JB		 632/**
633 * Returns whether any output on the specified pipe is of the specified type
634 */
4ef69c7a 635bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 636{
4ef69c7a 637 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 638 struct intel_encoder *encoder;
639
6c2b7c12
DV		 640 for_each_encoder_on_crtc(dev, crtc, encoder)
641 if (encoder->type == type)
4ef69c7a
CW		 642 return true;
643
644 return false;
79e53945
JB		 645}
646
7c04d1d9 647#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 648/**
649 * Returns whether the given set of divisors are valid for a given refclk with
650 * the given connectors.
651 */
652
1b894b59
CW		 653static bool intel_PLL_is_valid(struct drm_device *dev,
654 const intel_limit_t *limit,
655 const intel_clock_t *clock)
79e53945 656{
79e53945 657 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 658 INTELPllInvalid("p1 out of range\n");
79e53945 659 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 660 INTELPllInvalid("p out of range\n");
79e53945 661 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 662 INTELPllInvalid("m2 out of range\n");
79e53945 663 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 664 INTELPllInvalid("m1 out of range\n");
f2b115e6 665 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 666 INTELPllInvalid("m1 <= m2\n");
79e53945 667 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 668 INTELPllInvalid("m out of range\n");
79e53945 669 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 670 INTELPllInvalid("n out of range\n");
79e53945 671 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 672 INTELPllInvalid("vco out of range\n");
79e53945
JB		 673 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
674 * connector, etc., rather than just a single range.
675 */
676 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 677 INTELPllInvalid("dot out of range\n");
79e53945
JB		 678
679 return true;
680}
681
d4906093
ML		 682static bool
683intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 684 int target, int refclk, intel_clock_t *match_clock,
685 intel_clock_t *best_clock)
d4906093 686
79e53945
JB		 687{
688 struct drm_device *dev = crtc->dev;
689 struct drm_i915_private *dev_priv = dev->dev_private;
690 intel_clock_t clock;
79e53945
JB		 691 int err = target;
692
bc5e5718 693 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 694 (I915_READ(LVDS)) != 0) {
79e53945
JB		 695 /*
696 * For LVDS, if the panel is on, just rely on its current
697 * settings for dual-channel. We haven't figured out how to
698 * reliably set up different single/dual channel state, if we
699 * even can.
700 */
b0354385 701 if (is_dual_link_lvds(dev_priv, LVDS))
79e53945
JB		 702 clock.p2 = limit->p2.p2_fast;
703 else
704 clock.p2 = limit->p2.p2_slow;
705 } else {
706 if (target < limit->p2.dot_limit)
707 clock.p2 = limit->p2.p2_slow;
708 else
709 clock.p2 = limit->p2.p2_fast;
710 }
711
0206e353 712 memset(best_clock, 0, sizeof(*best_clock));
79e53945 713
42158660
ZY		 714 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
715 clock.m1++) {
716 for (clock.m2 = limit->m2.min;
717 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 718 /* m1 is always 0 in Pineview */
719 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 720 break;
721 for (clock.n = limit->n.min;
722 clock.n <= limit->n.max; clock.n++) {
723 for (clock.p1 = limit->p1.min;
724 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 725 int this_err;
726
2177832f 727 intel_clock(dev, refclk, &clock);
1b894b59
CW		 728 if (!intel_PLL_is_valid(dev, limit,
729 &clock))
79e53945 730 continue;
cec2f356
SP		 731 if (match_clock &&
732 clock.p != match_clock->p)
733 continue;
79e53945
JB		 734
735 this_err = abs(clock.dot - target);
736 if (this_err < err) {
737 *best_clock = clock;
738 err = this_err;
739 }
740 }
741 }
742 }
743 }
744
745 return (err != target);
746}
747
d4906093
ML		 748static bool
749intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 750 int target, int refclk, intel_clock_t *match_clock,
751 intel_clock_t *best_clock)
d4906093
ML		 752{
753 struct drm_device *dev = crtc->dev;
754 struct drm_i915_private *dev_priv = dev->dev_private;
755 intel_clock_t clock;
756 int max_n;
757 bool found;
6ba770dc
AJ		 758 /* approximately equals target * 0.00585 */
759 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 760 found = false;
761
762 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 763 int lvds_reg;
764
c619eed4 765 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 766 lvds_reg = PCH_LVDS;
767 else
768 lvds_reg = LVDS;
769 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 770 LVDS_CLKB_POWER_UP)
771 clock.p2 = limit->p2.p2_fast;
772 else
773 clock.p2 = limit->p2.p2_slow;
774 } else {
775 if (target < limit->p2.dot_limit)
776 clock.p2 = limit->p2.p2_slow;
777 else
778 clock.p2 = limit->p2.p2_fast;
779 }
780
781 memset(best_clock, 0, sizeof(*best_clock));
782 max_n = limit->n.max;
f77f13e2 783 /* based on hardware requirement, prefer smaller n to precision */
d4906093 784 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 785 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 786 for (clock.m1 = limit->m1.max;
787 clock.m1 >= limit->m1.min; clock.m1--) {
788 for (clock.m2 = limit->m2.max;
789 clock.m2 >= limit->m2.min; clock.m2--) {
790 for (clock.p1 = limit->p1.max;
791 clock.p1 >= limit->p1.min; clock.p1--) {
792 int this_err;
793
2177832f 794 intel_clock(dev, refclk, &clock);
1b894b59
CW		 795 if (!intel_PLL_is_valid(dev, limit,
796 &clock))
d4906093 797 continue;
cec2f356
SP		 798 if (match_clock &&
799 clock.p != match_clock->p)
800 continue;
1b894b59
CW		 801
802 this_err = abs(clock.dot - target);
d4906093
ML		 803 if (this_err < err_most) {
804 *best_clock = clock;
805 err_most = this_err;
806 max_n = clock.n;
807 found = true;
808 }
809 }
810 }
811 }
812 }
2c07245f
ZW		 813 return found;
814}
815
5eb08b69 816static bool
f2b115e6 817intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 818 int target, int refclk, intel_clock_t *match_clock,
819 intel_clock_t *best_clock)
5eb08b69
ZW		 820{
821 struct drm_device *dev = crtc->dev;
822 intel_clock_t clock;
4547668a 823
5eb08b69
ZW		 824 if (target < 200000) {
825 clock.n = 1;
826 clock.p1 = 2;
827 clock.p2 = 10;
828 clock.m1 = 12;
829 clock.m2 = 9;
830 } else {
831 clock.n = 2;
832 clock.p1 = 1;
833 clock.p2 = 10;
834 clock.m1 = 14;
835 clock.m2 = 8;
836 }
837 intel_clock(dev, refclk, &clock);
838 memcpy(best_clock, &clock, sizeof(intel_clock_t));
839 return true;
840}
841
a4fc5ed6
KP		 842/* DisplayPort has only two frequencies, 162MHz and 270MHz */
843static bool
844intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 845 int target, int refclk, intel_clock_t *match_clock,
846 intel_clock_t *best_clock)
a4fc5ed6 847{
5eddb70b
CW		 848 intel_clock_t clock;
849 if (target < 200000) {
850 clock.p1 = 2;
851 clock.p2 = 10;
852 clock.n = 2;
853 clock.m1 = 23;
854 clock.m2 = 8;
855 } else {
856 clock.p1 = 1;
857 clock.p2 = 10;
858 clock.n = 1;
859 clock.m1 = 14;
860 clock.m2 = 2;
861 }
862 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
863 clock.p = (clock.p1 * clock.p2);
864 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
865 clock.vco = 0;
866 memcpy(best_clock, &clock, sizeof(intel_clock_t));
867 return true;
a4fc5ed6 868}
a0c4da24
JB		 869static bool
870intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
871 int target, int refclk, intel_clock_t *match_clock,
872 intel_clock_t *best_clock)
873{
874 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
875 u32 m, n, fastclk;
876 u32 updrate, minupdate, fracbits, p;
877 unsigned long bestppm, ppm, absppm;
878 int dotclk, flag;
879
af447bd3 880 flag = 0;
a0c4da24
JB		 881 dotclk = target * 1000;
882 bestppm = 1000000;
883 ppm = absppm = 0;
884 fastclk = dotclk / (2*100);
885 updrate = 0;
886 minupdate = 19200;
887 fracbits = 1;
888 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
889 bestm1 = bestm2 = bestp1 = bestp2 = 0;
890
891 /* based on hardware requirement, prefer smaller n to precision */
892 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
893 updrate = refclk / n;
894 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
895 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
896 if (p2 > 10)
897 p2 = p2 - 1;
898 p = p1 * p2;
899 /* based on hardware requirement, prefer bigger m1,m2 values */
900 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
901 m2 = (((2*(fastclk * p * n / m1 )) +
902 refclk) / (2*refclk));
903 m = m1 * m2;
904 vco = updrate * m;
905 if (vco >= limit->vco.min && vco < limit->vco.max) {
906 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
907 absppm = (ppm > 0) ? ppm : (-ppm);
908 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
909 bestppm = 0;
910 flag = 1;
911 }
912 if (absppm < bestppm - 10) {
913 bestppm = absppm;
914 flag = 1;
915 }
916 if (flag) {
917 bestn = n;
918 bestm1 = m1;
919 bestm2 = m2;
920 bestp1 = p1;
921 bestp2 = p2;
922 flag = 0;
923 }
924 }
925 }
926 }
927 }
928 }
929 best_clock->n = bestn;
930 best_clock->m1 = bestm1;
931 best_clock->m2 = bestm2;
932 best_clock->p1 = bestp1;
933 best_clock->p2 = bestp2;
934
935 return true;
936}
a4fc5ed6 937
a5c961d1
PZ		 938enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
939 enum pipe pipe)
940{
941 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
942 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
943
944 return intel_crtc->cpu_transcoder;
945}
946
a928d536
PZ		 947static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
948{
949 struct drm_i915_private *dev_priv = dev->dev_private;
950 u32 frame, frame_reg = PIPEFRAME(pipe);
951
952 frame = I915_READ(frame_reg);
953
954 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
955 DRM_DEBUG_KMS("vblank wait timed out\n");
956}
957
9d0498a2
JB		 958/**
959 * intel_wait_for_vblank - wait for vblank on a given pipe
960 * @dev: drm device
961 * @pipe: pipe to wait for
962 *
963 * Wait for vblank to occur on a given pipe. Needed for various bits of
964 * mode setting code.
965 */
966void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 967{
9d0498a2 968 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 969 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 970
a928d536
PZ		 971 if (INTEL_INFO(dev)->gen >= 5) {
972 ironlake_wait_for_vblank(dev, pipe);
973 return;
974 }
975
300387c0
CW		 976 /* Clear existing vblank status. Note this will clear any other
977 * sticky status fields as well.
978 *
979 * This races with i915_driver_irq_handler() with the result
980 * that either function could miss a vblank event. Here it is not
981 * fatal, as we will either wait upon the next vblank interrupt or
982 * timeout. Generally speaking intel_wait_for_vblank() is only
983 * called during modeset at which time the GPU should be idle and
984 * should *not* be performing page flips and thus not waiting on
985 * vblanks...
986 * Currently, the result of us stealing a vblank from the irq
987 * handler is that a single frame will be skipped during swapbuffers.
988 */
989 I915_WRITE(pipestat_reg,
990 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
991
9d0498a2 992 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 993 if (wait_for(I915_READ(pipestat_reg) &
994 PIPE_VBLANK_INTERRUPT_STATUS,
995 50))
9d0498a2
JB		 996 DRM_DEBUG_KMS("vblank wait timed out\n");
997}
998
ab7ad7f6
KP		 999/*
1000 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 1001 * @dev: drm device
1002 * @pipe: pipe to wait for
1003 *
1004 * After disabling a pipe, we can't wait for vblank in the usual way,
1005 * spinning on the vblank interrupt status bit, since we won't actually
1006 * see an interrupt when the pipe is disabled.
1007 *
ab7ad7f6
KP		 1008 * On Gen4 and above:
1009 * wait for the pipe register state bit to turn off
1010 *
1011 * Otherwise:
1012 * wait for the display line value to settle (it usually
1013 * ends up stopping at the start of the next frame).
58e10eb9 1014 *
9d0498a2 1015 */
58e10eb9 1016void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 1017{
1018 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 1019 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1020 pipe);
ab7ad7f6
KP		 1021
1022 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1023 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1024
1025 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1026 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1027 100))
284637d9 1028 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1029 } else {
837ba00f 1030 u32 last_line, line_mask;
58e10eb9 1031 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 1032 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1033
837ba00f
PZ		 1034 if (IS_GEN2(dev))
1035 line_mask = DSL_LINEMASK_GEN2;
1036 else
1037 line_mask = DSL_LINEMASK_GEN3;
1038
ab7ad7f6
KP		 1039 /* Wait for the display line to settle */
1040 do {
837ba00f 1041 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 1042 mdelay(5);
837ba00f 1043 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 1044 time_after(timeout, jiffies));
1045 if (time_after(jiffies, timeout))
284637d9 1046 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1047 }
79e53945
JB		 1048}
1049
b24e7179
JB		 1050static const char *state_string(bool enabled)
1051{
1052 return enabled ? "on" : "off";
1053}
1054
1055/* Only for pre-ILK configs */
1056static void assert_pll(struct drm_i915_private *dev_priv,
1057 enum pipe pipe, bool state)
1058{
1059 int reg;
1060 u32 val;
1061 bool cur_state;
1062
1063 reg = DPLL(pipe);
1064 val = I915_READ(reg);
1065 cur_state = !!(val & DPLL_VCO_ENABLE);
1066 WARN(cur_state != state,
1067 "PLL state assertion failure (expected %s, current %s)\n",
1068 state_string(state), state_string(cur_state));
1069}
1070#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1071#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1072
040484af
JB		 1073/* For ILK+ */
1074static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1075 struct intel_pch_pll *pll,
1076 struct intel_crtc *crtc,
1077 bool state)
040484af 1078{
040484af
JB		 1079 u32 val;
1080 bool cur_state;
1081
9d82aa17
ED		 1082 if (HAS_PCH_LPT(dev_priv->dev)) {
1083 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1084 return;
1085 }
1086
92b27b08
CW		 1087 if (WARN (!pll,
1088 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1089 return;
ee7b9f93 1090
92b27b08
CW		 1091 val = I915_READ(pll->pll_reg);
1092 cur_state = !!(val & DPLL_VCO_ENABLE);
1093 WARN(cur_state != state,
1094 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1095 pll->pll_reg, state_string(state), state_string(cur_state), val);
1096
1097 /* Make sure the selected PLL is correctly attached to the transcoder */
1098 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1099 u32 pch_dpll;
1100
1101 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1102 cur_state = pll->pll_reg == _PCH_DPLL_B;
1103 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1104 "PLL[%d] not attached to this transcoder %d: %08x\n",
1105 cur_state, crtc->pipe, pch_dpll)) {
1106 cur_state = !!(val >> (4*crtc->pipe + 3));
1107 WARN(cur_state != state,
1108 "PLL[%d] not %s on this transcoder %d: %08x\n",
1109 pll->pll_reg == _PCH_DPLL_B,
1110 state_string(state),
1111 crtc->pipe,
1112 val);
1113 }
d3ccbe86 1114 }
040484af 1115}
92b27b08
CW		 1116#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1117#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1118
1119static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1120 enum pipe pipe, bool state)
1121{
1122 int reg;
1123 u32 val;
1124 bool cur_state;
ad80a810
PZ		 1125 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1126 pipe);
040484af 1127
bf507ef7
ED		 1128 if (IS_HASWELL(dev_priv->dev)) {
1129 /* On Haswell, DDI is used instead of FDI_TX_CTL */
ad80a810 1130 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1131 val = I915_READ(reg);
ad80a810 1132 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1133 } else {
1134 reg = FDI_TX_CTL(pipe);
1135 val = I915_READ(reg);
1136 cur_state = !!(val & FDI_TX_ENABLE);
1137 }
040484af
JB		 1138 WARN(cur_state != state,
1139 "FDI TX state assertion failure (expected %s, current %s)\n",
1140 state_string(state), state_string(cur_state));
1141}
1142#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1143#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1144
1145static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1146 enum pipe pipe, bool state)
1147{
1148 int reg;
1149 u32 val;
1150 bool cur_state;
1151
d63fa0dc
PZ		 1152 reg = FDI_RX_CTL(pipe);
1153 val = I915_READ(reg);
1154 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1155 WARN(cur_state != state,
1156 "FDI RX state assertion failure (expected %s, current %s)\n",
1157 state_string(state), state_string(cur_state));
1158}
1159#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1160#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1161
1162static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1163 enum pipe pipe)
1164{
1165 int reg;
1166 u32 val;
1167
1168 /* ILK FDI PLL is always enabled */
1169 if (dev_priv->info->gen == 5)
1170 return;
1171
bf507ef7
ED		 1172 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1173 if (IS_HASWELL(dev_priv->dev))
1174 return;
1175
040484af
JB		 1176 reg = FDI_TX_CTL(pipe);
1177 val = I915_READ(reg);
1178 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1179}
1180
1181static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1182 enum pipe pipe)
1183{
1184 int reg;
1185 u32 val;
1186
1187 reg = FDI_RX_CTL(pipe);
1188 val = I915_READ(reg);
1189 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1190}
1191
ea0760cf
JB		 1192static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1193 enum pipe pipe)
1194{
1195 int pp_reg, lvds_reg;
1196 u32 val;
1197 enum pipe panel_pipe = PIPE_A;
0de3b485 1198 bool locked = true;
ea0760cf
JB		 1199
1200 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1201 pp_reg = PCH_PP_CONTROL;
1202 lvds_reg = PCH_LVDS;
1203 } else {
1204 pp_reg = PP_CONTROL;
1205 lvds_reg = LVDS;
1206 }
1207
1208 val = I915_READ(pp_reg);
1209 if (!(val & PANEL_POWER_ON) ||
1210 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1211 locked = false;
1212
1213 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1214 panel_pipe = PIPE_B;
1215
1216 WARN(panel_pipe == pipe && locked,
1217 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1218 pipe_name(pipe));
ea0760cf
JB		 1219}
1220
b840d907
JB		 1221void assert_pipe(struct drm_i915_private *dev_priv,
1222 enum pipe pipe, bool state)
b24e7179
JB		 1223{
1224 int reg;
1225 u32 val;
63d7bbe9 1226 bool cur_state;
702e7a56
PZ		 1227 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1228 pipe);
b24e7179 1229
8e636784
DV		 1230 /* if we need the pipe A quirk it must be always on */
1231 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1232 state = true;
1233
702e7a56 1234 reg = PIPECONF(cpu_transcoder);
b24e7179 1235 val = I915_READ(reg);
63d7bbe9
JB		 1236 cur_state = !!(val & PIPECONF_ENABLE);
1237 WARN(cur_state != state,
1238 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1239 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1240}
1241
931872fc
CW		 1242static void assert_plane(struct drm_i915_private *dev_priv,
1243 enum plane plane, bool state)
b24e7179
JB		 1244{
1245 int reg;
1246 u32 val;
931872fc 1247 bool cur_state;
b24e7179
JB		 1248
1249 reg = DSPCNTR(plane);
1250 val = I915_READ(reg);
931872fc
CW		 1251 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1252 WARN(cur_state != state,
1253 "plane %c assertion failure (expected %s, current %s)\n",
1254 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1255}
1256
931872fc
CW		 1257#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1258#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1259
b24e7179
JB		 1260static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1261 enum pipe pipe)
1262{
1263 int reg, i;
1264 u32 val;
1265 int cur_pipe;
1266
19ec1358 1267 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 1268 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1269 reg = DSPCNTR(pipe);
1270 val = I915_READ(reg);
1271 WARN((val & DISPLAY_PLANE_ENABLE),
1272 "plane %c assertion failure, should be disabled but not\n",
1273 plane_name(pipe));
19ec1358 1274 return;
28c05794 1275 }
19ec1358 1276
b24e7179
JB		 1277 /* Need to check both planes against the pipe */
1278 for (i = 0; i < 2; i++) {
1279 reg = DSPCNTR(i);
1280 val = I915_READ(reg);
1281 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1282 DISPPLANE_SEL_PIPE_SHIFT;
1283 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1284 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1285 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1286 }
1287}
1288
92f2584a
JB		 1289static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1290{
1291 u32 val;
1292 bool enabled;
1293
9d82aa17
ED		 1294 if (HAS_PCH_LPT(dev_priv->dev)) {
1295 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1296 return;
1297 }
1298
92f2584a
JB		 1299 val = I915_READ(PCH_DREF_CONTROL);
1300 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1301 DREF_SUPERSPREAD_SOURCE_MASK));
1302 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1303}
1304
1305static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1306 enum pipe pipe)
1307{
1308 int reg;
1309 u32 val;
1310 bool enabled;
1311
1312 reg = TRANSCONF(pipe);
1313 val = I915_READ(reg);
1314 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1315 WARN(enabled,
1316 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1317 pipe_name(pipe));
92f2584a
JB		 1318}
1319
4e634389
KP		 1320static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1321 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1322{
1323 if ((val & DP_PORT_EN) == 0)
1324 return false;
1325
1326 if (HAS_PCH_CPT(dev_priv->dev)) {
1327 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1328 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1329 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1330 return false;
1331 } else {
1332 if ((val & DP_PIPE_MASK) != (pipe << 30))
1333 return false;
1334 }
1335 return true;
1336}
1337
1519b995
KP		 1338static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1339 enum pipe pipe, u32 val)
1340{
1341 if ((val & PORT_ENABLE) == 0)
1342 return false;
1343
1344 if (HAS_PCH_CPT(dev_priv->dev)) {
1345 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1346 return false;
1347 } else {
1348 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1349 return false;
1350 }
1351 return true;
1352}
1353
1354static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1355 enum pipe pipe, u32 val)
1356{
1357 if ((val & LVDS_PORT_EN) == 0)
1358 return false;
1359
1360 if (HAS_PCH_CPT(dev_priv->dev)) {
1361 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1362 return false;
1363 } else {
1364 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1365 return false;
1366 }
1367 return true;
1368}
1369
1370static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1371 enum pipe pipe, u32 val)
1372{
1373 if ((val & ADPA_DAC_ENABLE) == 0)
1374 return false;
1375 if (HAS_PCH_CPT(dev_priv->dev)) {
1376 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1377 return false;
1378 } else {
1379 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1380 return false;
1381 }
1382 return true;
1383}
1384
291906f1 1385static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1386 enum pipe pipe, int reg, u32 port_sel)
291906f1 1387{
47a05eca 1388 u32 val = I915_READ(reg);
4e634389 1389 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1390 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1391 reg, pipe_name(pipe));
de9a35ab 1392
75c5da27
DV		 1393 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1394 && (val & DP_PIPEB_SELECT),
de9a35ab 1395 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1396}
1397
1398static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1399 enum pipe pipe, int reg)
1400{
47a05eca 1401 u32 val = I915_READ(reg);
b70ad586 1402 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1403 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1404 reg, pipe_name(pipe));
de9a35ab 1405
75c5da27
DV		 1406 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1407 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1408 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1409}
1410
1411static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1412 enum pipe pipe)
1413{
1414 int reg;
1415 u32 val;
291906f1 1416
f0575e92
KP		 1417 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1418 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1419 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1420
1421 reg = PCH_ADPA;
1422 val = I915_READ(reg);
b70ad586 1423 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1424 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1425 pipe_name(pipe));
291906f1
JB		 1426
1427 reg = PCH_LVDS;
1428 val = I915_READ(reg);
b70ad586 1429 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1430 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1431 pipe_name(pipe));
291906f1
JB		 1432
1433 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1434 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1435 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1436}
1437
63d7bbe9
JB		 1438/**
1439 * intel_enable_pll - enable a PLL
1440 * @dev_priv: i915 private structure
1441 * @pipe: pipe PLL to enable
1442 *
1443 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1444 * make sure the PLL reg is writable first though, since the panel write
1445 * protect mechanism may be enabled.
1446 *
1447 * Note! This is for pre-ILK only.
7434a255
TR		 1448 *
1449 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1450 */
1451static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1452{
1453 int reg;
1454 u32 val;
1455
1456 /* No really, not for ILK+ */
a0c4da24 1457 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1458
1459 /* PLL is protected by panel, make sure we can write it */
1460 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1461 assert_panel_unlocked(dev_priv, pipe);
1462
1463 reg = DPLL(pipe);
1464 val = I915_READ(reg);
1465 val |= DPLL_VCO_ENABLE;
1466
1467 /* We do this three times for luck */
1468 I915_WRITE(reg, val);
1469 POSTING_READ(reg);
1470 udelay(150); /* wait for warmup */
1471 I915_WRITE(reg, val);
1472 POSTING_READ(reg);
1473 udelay(150); /* wait for warmup */
1474 I915_WRITE(reg, val);
1475 POSTING_READ(reg);
1476 udelay(150); /* wait for warmup */
1477}
1478
1479/**
1480 * intel_disable_pll - disable a PLL
1481 * @dev_priv: i915 private structure
1482 * @pipe: pipe PLL to disable
1483 *
1484 * Disable the PLL for @pipe, making sure the pipe is off first.
1485 *
1486 * Note! This is for pre-ILK only.
1487 */
1488static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1489{
1490 int reg;
1491 u32 val;
1492
1493 /* Don't disable pipe A or pipe A PLLs if needed */
1494 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1495 return;
1496
1497 /* Make sure the pipe isn't still relying on us */
1498 assert_pipe_disabled(dev_priv, pipe);
1499
1500 reg = DPLL(pipe);
1501 val = I915_READ(reg);
1502 val &= ~DPLL_VCO_ENABLE;
1503 I915_WRITE(reg, val);
1504 POSTING_READ(reg);
1505}
1506
a416edef
ED		 1507/* SBI access */
1508static void
1509intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1510{
1511 unsigned long flags;
1512
1513 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1514 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1515 100)) {
1516 DRM_ERROR("timeout waiting for SBI to become ready\n");
1517 goto out_unlock;
1518 }
1519
1520 I915_WRITE(SBI_ADDR,
1521 (reg << 16));
1522 I915_WRITE(SBI_DATA,
1523 value);
1524 I915_WRITE(SBI_CTL_STAT,
1525 SBI_BUSY |
1526 SBI_CTL_OP_CRWR);
1527
39fb50f6 1528 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1529 100)) {
1530 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1531 goto out_unlock;
1532 }
1533
1534out_unlock:
1535 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1536}
1537
1538static u32
1539intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1540{
1541 unsigned long flags;
39fb50f6 1542 u32 value = 0;
a416edef
ED		 1543
1544 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1545 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1546 100)) {
1547 DRM_ERROR("timeout waiting for SBI to become ready\n");
1548 goto out_unlock;
1549 }
1550
1551 I915_WRITE(SBI_ADDR,
1552 (reg << 16));
1553 I915_WRITE(SBI_CTL_STAT,
1554 SBI_BUSY |
1555 SBI_CTL_OP_CRRD);
1556
39fb50f6 1557 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1558 100)) {
1559 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1560 goto out_unlock;
1561 }
1562
1563 value = I915_READ(SBI_DATA);
1564
1565out_unlock:
1566 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1567 return value;
1568}
1569
92f2584a 1570/**
b6b4e185 1571 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1572 * @dev_priv: i915 private structure
1573 * @pipe: pipe PLL to enable
1574 *
1575 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1576 * drives the transcoder clock.
1577 */
b6b4e185 1578static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1579{
ee7b9f93 1580 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1581 struct intel_pch_pll *pll;
92f2584a
JB		 1582 int reg;
1583 u32 val;
1584
48da64a8 1585 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1586 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1587 pll = intel_crtc->pch_pll;
1588 if (pll == NULL)
1589 return;
1590
1591 if (WARN_ON(pll->refcount == 0))
1592 return;
ee7b9f93
JB		 1593
1594 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1595 pll->pll_reg, pll->active, pll->on,
1596 intel_crtc->base.base.id);
92f2584a
JB		 1597
1598 /* PCH refclock must be enabled first */
1599 assert_pch_refclk_enabled(dev_priv);
1600
ee7b9f93 1601 if (pll->active++ && pll->on) {
92b27b08 1602 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1603 return;
1604 }
1605
1606 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1607
1608 reg = pll->pll_reg;
92f2584a
JB		 1609 val = I915_READ(reg);
1610 val |= DPLL_VCO_ENABLE;
1611 I915_WRITE(reg, val);
1612 POSTING_READ(reg);
1613 udelay(200);
ee7b9f93
JB		 1614
1615 pll->on = true;
92f2584a
JB		 1616}
1617
ee7b9f93 1618static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1619{
ee7b9f93
JB		 1620 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1621 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1622 int reg;
ee7b9f93 1623 u32 val;
4c609cb8 1624
92f2584a
JB		 1625 /* PCH only available on ILK+ */
1626 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1627 if (pll == NULL)
1628 return;
92f2584a 1629
48da64a8
CW		 1630 if (WARN_ON(pll->refcount == 0))
1631 return;
7a419866 1632
ee7b9f93
JB		 1633 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1634 pll->pll_reg, pll->active, pll->on,
1635 intel_crtc->base.base.id);
7a419866 1636
48da64a8 1637 if (WARN_ON(pll->active == 0)) {
92b27b08 1638 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1639 return;
1640 }
1641
ee7b9f93 1642 if (--pll->active) {
92b27b08 1643 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1644 return;
ee7b9f93
JB		 1645 }
1646
1647 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1648
1649 /* Make sure transcoder isn't still depending on us */
1650 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1651
ee7b9f93 1652 reg = pll->pll_reg;
92f2584a
JB		 1653 val = I915_READ(reg);
1654 val &= ~DPLL_VCO_ENABLE;
1655 I915_WRITE(reg, val);
1656 POSTING_READ(reg);
1657 udelay(200);
ee7b9f93
JB		 1658
1659 pll->on = false;
92f2584a
JB		 1660}
1661
b8a4f404
PZ		 1662static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1663 enum pipe pipe)
040484af 1664{
23670b32 1665 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1666 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1667 uint32_t reg, val, pipeconf_val;
040484af
JB		 1668
1669 /* PCH only available on ILK+ */
1670 BUG_ON(dev_priv->info->gen < 5);
1671
1672 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1673 assert_pch_pll_enabled(dev_priv,
1674 to_intel_crtc(crtc)->pch_pll,
1675 to_intel_crtc(crtc));
040484af
JB		 1676
1677 /* FDI must be feeding us bits for PCH ports */
1678 assert_fdi_tx_enabled(dev_priv, pipe);
1679 assert_fdi_rx_enabled(dev_priv, pipe);
1680
23670b32
DV		 1681 if (HAS_PCH_CPT(dev)) {
1682 /* Workaround: Set the timing override bit before enabling the
1683 * pch transcoder. */
1684 reg = TRANS_CHICKEN2(pipe);
1685 val = I915_READ(reg);
1686 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1687 I915_WRITE(reg, val);
59c859d6 1688 }
23670b32 1689
040484af
JB		 1690 reg = TRANSCONF(pipe);
1691 val = I915_READ(reg);
5f7f726d 1692 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1693
1694 if (HAS_PCH_IBX(dev_priv->dev)) {
1695 /*
1696 * make the BPC in transcoder be consistent with
1697 * that in pipeconf reg.
1698 */
1699 val &= ~PIPE_BPC_MASK;
5f7f726d 1700 val |= pipeconf_val & PIPE_BPC_MASK;
e9bcff5c 1701 }
5f7f726d
PZ		 1702
1703 val &= ~TRANS_INTERLACE_MASK;
1704 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1705 if (HAS_PCH_IBX(dev_priv->dev) &&
1706 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1707 val |= TRANS_LEGACY_INTERLACED_ILK;
1708 else
1709 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1710 else
1711 val |= TRANS_PROGRESSIVE;
1712
040484af
JB		 1713 I915_WRITE(reg, val | TRANS_ENABLE);
1714 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1715 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1716}
1717
8fb033d7 1718static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1719 enum transcoder cpu_transcoder)
040484af 1720{
8fb033d7 1721 u32 val, pipeconf_val;
8fb033d7
PZ		 1722
1723 /* PCH only available on ILK+ */
1724 BUG_ON(dev_priv->info->gen < 5);
1725
8fb033d7 1726 /* FDI must be feeding us bits for PCH ports */
937bb610
PZ		 1727 assert_fdi_tx_enabled(dev_priv, cpu_transcoder);
1728 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1729
223a6fdf
PZ		 1730 /* Workaround: set timing override bit. */
1731 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1732 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1733 I915_WRITE(_TRANSA_CHICKEN2, val);
1734
25f3ef11 1735 val = TRANS_ENABLE;
937bb610 1736 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1737
9a76b1c6
PZ		 1738 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1739 PIPECONF_INTERLACED_ILK)
a35f2679 1740 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1741 else
1742 val |= TRANS_PROGRESSIVE;
1743
25f3ef11 1744 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
937bb610
PZ		 1745 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1746 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1747}
1748
b8a4f404
PZ		 1749static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1750 enum pipe pipe)
040484af 1751{
23670b32
DV		 1752 struct drm_device *dev = dev_priv->dev;
1753 uint32_t reg, val;
040484af
JB		 1754
1755 /* FDI relies on the transcoder */
1756 assert_fdi_tx_disabled(dev_priv, pipe);
1757 assert_fdi_rx_disabled(dev_priv, pipe);
1758
291906f1
JB		 1759 /* Ports must be off as well */
1760 assert_pch_ports_disabled(dev_priv, pipe);
1761
040484af
JB		 1762 reg = TRANSCONF(pipe);
1763 val = I915_READ(reg);
1764 val &= ~TRANS_ENABLE;
1765 I915_WRITE(reg, val);
1766 /* wait for PCH transcoder off, transcoder state */
1767 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1768 DRM_ERROR("failed to disable transcoder %d\n", pipe);
23670b32
DV		 1769
1770 if (!HAS_PCH_IBX(dev)) {
1771 /* Workaround: Clear the timing override chicken bit again. */
1772 reg = TRANS_CHICKEN2(pipe);
1773 val = I915_READ(reg);
1774 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1775 I915_WRITE(reg, val);
1776 }
040484af
JB		 1777}
1778
ab4d966c 1779static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1780{
8fb033d7
PZ		 1781 u32 val;
1782
8a52fd9f 1783 val = I915_READ(_TRANSACONF);
8fb033d7 1784 val &= ~TRANS_ENABLE;
8a52fd9f 1785 I915_WRITE(_TRANSACONF, val);
8fb033d7 1786 /* wait for PCH transcoder off, transcoder state */
8a52fd9f
PZ		 1787 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1788 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1789
1790 /* Workaround: clear timing override bit. */
1791 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1792 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1793 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1794}
1795
b24e7179 1796/**
309cfea8 1797 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1798 * @dev_priv: i915 private structure
1799 * @pipe: pipe to enable
040484af 1800 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1801 *
1802 * Enable @pipe, making sure that various hardware specific requirements
1803 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1804 *
1805 * @pipe should be %PIPE_A or %PIPE_B.
1806 *
1807 * Will wait until the pipe is actually running (i.e. first vblank) before
1808 * returning.
1809 */
040484af
JB		 1810static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1811 bool pch_port)
b24e7179 1812{
702e7a56
PZ		 1813 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1814 pipe);
cc391bbb 1815 enum transcoder pch_transcoder;
b24e7179
JB		 1816 int reg;
1817 u32 val;
1818
cc391bbb
PZ		 1819 if (IS_HASWELL(dev_priv->dev))
1820 pch_transcoder = TRANSCODER_A;
1821 else
1822 pch_transcoder = pipe;
1823
b24e7179
JB		 1824 /*
1825 * A pipe without a PLL won't actually be able to drive bits from
1826 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1827 * need the check.
1828 */
1829 if (!HAS_PCH_SPLIT(dev_priv->dev))
1830 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1831 else {
1832 if (pch_port) {
1833 /* if driving the PCH, we need FDI enabled */
cc391bbb
PZ		 1834 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1835 assert_fdi_tx_pll_enabled(dev_priv, cpu_transcoder);
040484af
JB		 1836 }
1837 /* FIXME: assert CPU port conditions for SNB+ */
1838 }
b24e7179 1839
702e7a56 1840 reg = PIPECONF(cpu_transcoder);
b24e7179 1841 val = I915_READ(reg);
00d70b15
CW		 1842 if (val & PIPECONF_ENABLE)
1843 return;
1844
1845 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1846 intel_wait_for_vblank(dev_priv->dev, pipe);
1847}
1848
1849/**
309cfea8 1850 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1851 * @dev_priv: i915 private structure
1852 * @pipe: pipe to disable
1853 *
1854 * Disable @pipe, making sure that various hardware specific requirements
1855 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1856 *
1857 * @pipe should be %PIPE_A or %PIPE_B.
1858 *
1859 * Will wait until the pipe has shut down before returning.
1860 */
1861static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1862 enum pipe pipe)
1863{
702e7a56
PZ		 1864 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1865 pipe);
b24e7179
JB		 1866 int reg;
1867 u32 val;
1868
1869 /*
1870 * Make sure planes won't keep trying to pump pixels to us,
1871 * or we might hang the display.
1872 */
1873 assert_planes_disabled(dev_priv, pipe);
1874
1875 /* Don't disable pipe A or pipe A PLLs if needed */
1876 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1877 return;
1878
702e7a56 1879 reg = PIPECONF(cpu_transcoder);
b24e7179 1880 val = I915_READ(reg);
00d70b15
CW		 1881 if ((val & PIPECONF_ENABLE) == 0)
1882 return;
1883
1884 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1885 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1886}
1887
d74362c9
KP		 1888/*
1889 * Plane regs are double buffered, going from enabled->disabled needs a
1890 * trigger in order to latch. The display address reg provides this.
1891 */
6f1d69b0 1892void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1893 enum plane plane)
1894{
14f86147
DL		 1895 if (dev_priv->info->gen >= 4)
1896 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1897 else
1898 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1899}
1900
b24e7179
JB		 1901/**
1902 * intel_enable_plane - enable a display plane on a given pipe
1903 * @dev_priv: i915 private structure
1904 * @plane: plane to enable
1905 * @pipe: pipe being fed
1906 *
1907 * Enable @plane on @pipe, making sure that @pipe is running first.
1908 */
1909static void intel_enable_plane(struct drm_i915_private *dev_priv,
1910 enum plane plane, enum pipe pipe)
1911{
1912 int reg;
1913 u32 val;
1914
1915 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1916 assert_pipe_enabled(dev_priv, pipe);
1917
1918 reg = DSPCNTR(plane);
1919 val = I915_READ(reg);
00d70b15
CW		 1920 if (val & DISPLAY_PLANE_ENABLE)
1921 return;
1922
1923 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1924 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1925 intel_wait_for_vblank(dev_priv->dev, pipe);
1926}
1927
b24e7179
JB		 1928/**
1929 * intel_disable_plane - disable a display plane
1930 * @dev_priv: i915 private structure
1931 * @plane: plane to disable
1932 * @pipe: pipe consuming the data
1933 *
1934 * Disable @plane; should be an independent operation.
1935 */
1936static void intel_disable_plane(struct drm_i915_private *dev_priv,
1937 enum plane plane, enum pipe pipe)
1938{
1939 int reg;
1940 u32 val;
1941
1942 reg = DSPCNTR(plane);
1943 val = I915_READ(reg);
00d70b15
CW		 1944 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1945 return;
1946
1947 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1948 intel_flush_display_plane(dev_priv, plane);
1949 intel_wait_for_vblank(dev_priv->dev, pipe);
1950}
1951
127bd2ac 1952int
48b956c5 1953intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1954 struct drm_i915_gem_object *obj,
919926ae 1955 struct intel_ring_buffer *pipelined)
6b95a207 1956{
ce453d81 1957 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1958 u32 alignment;
1959 int ret;
1960
05394f39 1961 switch (obj->tiling_mode) {
6b95a207 1962 case I915_TILING_NONE:
534843da
CW		 1963 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1964 alignment = 128 * 1024;
a6c45cf0 1965 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1966 alignment = 4 * 1024;
1967 else
1968 alignment = 64 * 1024;
6b95a207
KH		 1969 break;
1970 case I915_TILING_X:
1971 /* pin() will align the object as required by fence */
1972 alignment = 0;
1973 break;
1974 case I915_TILING_Y:
1975 /* FIXME: Is this true? */
1976 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1977 return -EINVAL;
1978 default:
1979 BUG();
1980 }
1981
ce453d81 1982 dev_priv->mm.interruptible = false;
2da3b9b9 1983 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1984 if (ret)
ce453d81 1985 goto err_interruptible;
6b95a207
KH		 1986
1987 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1988 * fence, whereas 965+ only requires a fence if using
1989 * framebuffer compression. For simplicity, we always install
1990 * a fence as the cost is not that onerous.
1991 */
06d98131 1992 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1993 if (ret)
1994 goto err_unpin;
1690e1eb 1995
9a5a53b3 1996 i915_gem_object_pin_fence(obj);
6b95a207 1997
ce453d81 1998 dev_priv->mm.interruptible = true;
6b95a207 1999 return 0;
48b956c5
CW		 2000
2001err_unpin:
2002 i915_gem_object_unpin(obj);
ce453d81
CW		 2003err_interruptible:
2004 dev_priv->mm.interruptible = true;
48b956c5 2005 return ret;
6b95a207
KH		 2006}
2007
1690e1eb
CW		 2008void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2009{
2010 i915_gem_object_unpin_fence(obj);
2011 i915_gem_object_unpin(obj);
2012}
2013
c2c75131
DV		 2014/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2015 * is assumed to be a power-of-two. */
5a35e99e
DL		 2016unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
2017 unsigned int bpp,
2018 unsigned int pitch)
c2c75131
DV		 2019{
2020 int tile_rows, tiles;
2021
2022 tile_rows = *y / 8;
2023 *y %= 8;
2024 tiles = *x / (512/bpp);
2025 *x %= 512/bpp;
2026
2027 return tile_rows * pitch * 8 + tiles * 4096;
2028}
2029
17638cd6
JB		 2030static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2031 int x, int y)
81255565
JB		 2032{
2033 struct drm_device *dev = crtc->dev;
2034 struct drm_i915_private *dev_priv = dev->dev_private;
2035 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2036 struct intel_framebuffer *intel_fb;
05394f39 2037 struct drm_i915_gem_object *obj;
81255565 2038 int plane = intel_crtc->plane;
e506a0c6 2039 unsigned long linear_offset;
81255565 2040 u32 dspcntr;
5eddb70b 2041 u32 reg;
81255565
JB		 2042
2043 switch (plane) {
2044 case 0:
2045 case 1:
2046 break;
2047 default:
2048 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2049 return -EINVAL;
2050 }
2051
2052 intel_fb = to_intel_framebuffer(fb);
2053 obj = intel_fb->obj;
81255565 2054
5eddb70b
CW		 2055 reg = DSPCNTR(plane);
2056 dspcntr = I915_READ(reg);
81255565
JB		 2057 /* Mask out pixel format bits in case we change it */
2058 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2059 switch (fb->pixel_format) {
2060 case DRM_FORMAT_C8:
81255565
JB		 2061 dspcntr |= DISPPLANE_8BPP;
2062 break;
57779d06
VS		 2063 case DRM_FORMAT_XRGB1555:
2064 case DRM_FORMAT_ARGB1555:
2065 dspcntr |= DISPPLANE_BGRX555;
81255565 2066 break;
57779d06
VS		 2067 case DRM_FORMAT_RGB565:
2068 dspcntr |= DISPPLANE_BGRX565;
2069 break;
2070 case DRM_FORMAT_XRGB8888:
2071 case DRM_FORMAT_ARGB8888:
2072 dspcntr |= DISPPLANE_BGRX888;
2073 break;
2074 case DRM_FORMAT_XBGR8888:
2075 case DRM_FORMAT_ABGR8888:
2076 dspcntr |= DISPPLANE_RGBX888;
2077 break;
2078 case DRM_FORMAT_XRGB2101010:
2079 case DRM_FORMAT_ARGB2101010:
2080 dspcntr |= DISPPLANE_BGRX101010;
2081 break;
2082 case DRM_FORMAT_XBGR2101010:
2083 case DRM_FORMAT_ABGR2101010:
2084 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2085 break;
2086 default:
57779d06 2087 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
81255565
JB		 2088 return -EINVAL;
2089 }
57779d06 2090
a6c45cf0 2091 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2092 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2093 dspcntr |= DISPPLANE_TILED;
2094 else
2095 dspcntr &= ~DISPPLANE_TILED;
2096 }
2097
5eddb70b 2098 I915_WRITE(reg, dspcntr);
81255565 2099
e506a0c6 2100 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2101
c2c75131
DV		 2102 if (INTEL_INFO(dev)->gen >= 4) {
2103 intel_crtc->dspaddr_offset =
5a35e99e
DL		 2104 intel_gen4_compute_offset_xtiled(&x, &y,
2105 fb->bits_per_pixel / 8,
2106 fb->pitches[0]);
c2c75131
DV		 2107 linear_offset -= intel_crtc->dspaddr_offset;
2108 } else {
e506a0c6 2109 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2110 }
e506a0c6
DV		 2111
2112 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2113 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2114 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2115 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2116 I915_MODIFY_DISPBASE(DSPSURF(plane),
2117 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2118 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2119 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2120 } else
e506a0c6 2121 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2122 POSTING_READ(reg);
81255565 2123
17638cd6
JB		 2124 return 0;
2125}
2126
2127static int ironlake_update_plane(struct drm_crtc *crtc,
2128 struct drm_framebuffer *fb, int x, int y)
2129{
2130 struct drm_device *dev = crtc->dev;
2131 struct drm_i915_private *dev_priv = dev->dev_private;
2132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2133 struct intel_framebuffer *intel_fb;
2134 struct drm_i915_gem_object *obj;
2135 int plane = intel_crtc->plane;
e506a0c6 2136 unsigned long linear_offset;
17638cd6
JB		 2137 u32 dspcntr;
2138 u32 reg;
2139
2140 switch (plane) {
2141 case 0:
2142 case 1:
27f8227b 2143 case 2:
17638cd6
JB		 2144 break;
2145 default:
2146 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2147 return -EINVAL;
2148 }
2149
2150 intel_fb = to_intel_framebuffer(fb);
2151 obj = intel_fb->obj;
2152
2153 reg = DSPCNTR(plane);
2154 dspcntr = I915_READ(reg);
2155 /* Mask out pixel format bits in case we change it */
2156 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2157 switch (fb->pixel_format) {
2158 case DRM_FORMAT_C8:
17638cd6
JB		 2159 dspcntr |= DISPPLANE_8BPP;
2160 break;
57779d06
VS		 2161 case DRM_FORMAT_RGB565:
2162 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2163 break;
57779d06
VS		 2164 case DRM_FORMAT_XRGB8888:
2165 case DRM_FORMAT_ARGB8888:
2166 dspcntr |= DISPPLANE_BGRX888;
2167 break;
2168 case DRM_FORMAT_XBGR8888:
2169 case DRM_FORMAT_ABGR8888:
2170 dspcntr |= DISPPLANE_RGBX888;
2171 break;
2172 case DRM_FORMAT_XRGB2101010:
2173 case DRM_FORMAT_ARGB2101010:
2174 dspcntr |= DISPPLANE_BGRX101010;
2175 break;
2176 case DRM_FORMAT_XBGR2101010:
2177 case DRM_FORMAT_ABGR2101010:
2178 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2179 break;
2180 default:
57779d06 2181 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
17638cd6
JB		 2182 return -EINVAL;
2183 }
2184
2185 if (obj->tiling_mode != I915_TILING_NONE)
2186 dspcntr |= DISPPLANE_TILED;
2187 else
2188 dspcntr &= ~DISPPLANE_TILED;
2189
2190 /* must disable */
2191 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2192
2193 I915_WRITE(reg, dspcntr);
2194
e506a0c6 2195 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2196 intel_crtc->dspaddr_offset =
5a35e99e
DL		 2197 intel_gen4_compute_offset_xtiled(&x, &y,
2198 fb->bits_per_pixel / 8,
2199 fb->pitches[0]);
c2c75131 2200 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2201
e506a0c6
DV		 2202 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2203 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2204 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2205 I915_MODIFY_DISPBASE(DSPSURF(plane),
2206 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2207 if (IS_HASWELL(dev)) {
2208 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2209 } else {
2210 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2211 I915_WRITE(DSPLINOFF(plane), linear_offset);
2212 }
17638cd6
JB		 2213 POSTING_READ(reg);
2214
2215 return 0;
2216}
2217
2218/* Assume fb object is pinned & idle & fenced and just update base pointers */
2219static int
2220intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2221 int x, int y, enum mode_set_atomic state)
2222{
2223 struct drm_device *dev = crtc->dev;
2224 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2225
6b8e6ed0
CW		 2226 if (dev_priv->display.disable_fbc)
2227 dev_priv->display.disable_fbc(dev);
3dec0095 2228 intel_increase_pllclock(crtc);
81255565 2229
6b8e6ed0 2230 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2231}
2232
14667a4b
CW		 2233static int
2234intel_finish_fb(struct drm_framebuffer *old_fb)
2235{
2236 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2237 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2238 bool was_interruptible = dev_priv->mm.interruptible;
2239 int ret;
2240
2241 wait_event(dev_priv->pending_flip_queue,
2242 atomic_read(&dev_priv->mm.wedged) ||
2243 atomic_read(&obj->pending_flip) == 0);
2244
2245 /* Big Hammer, we also need to ensure that any pending
2246 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2247 * current scanout is retired before unpinning the old
2248 * framebuffer.
2249 *
2250 * This should only fail upon a hung GPU, in which case we
2251 * can safely continue.
2252 */
2253 dev_priv->mm.interruptible = false;
2254 ret = i915_gem_object_finish_gpu(obj);
2255 dev_priv->mm.interruptible = was_interruptible;
2256
2257 return ret;
2258}
2259
198598d0
VS		 2260static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2261{
2262 struct drm_device *dev = crtc->dev;
2263 struct drm_i915_master_private *master_priv;
2264 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2265
2266 if (!dev->primary->master)
2267 return;
2268
2269 master_priv = dev->primary->master->driver_priv;
2270 if (!master_priv->sarea_priv)
2271 return;
2272
2273 switch (intel_crtc->pipe) {
2274 case 0:
2275 master_priv->sarea_priv->pipeA_x = x;
2276 master_priv->sarea_priv->pipeA_y = y;
2277 break;
2278 case 1:
2279 master_priv->sarea_priv->pipeB_x = x;
2280 master_priv->sarea_priv->pipeB_y = y;
2281 break;
2282 default:
2283 break;
2284 }
2285}
2286
5c3b82e2 2287static int
3c4fdcfb 2288intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2289 struct drm_framebuffer *fb)
79e53945
JB		 2290{
2291 struct drm_device *dev = crtc->dev;
6b8e6ed0 2292 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2293 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2294 struct drm_framebuffer *old_fb;
5c3b82e2 2295 int ret;
79e53945
JB		 2296
2297 /* no fb bound */
94352cf9 2298 if (!fb) {
a5071c2f 2299 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2300 return 0;
2301 }
2302
5826eca5
ED		 2303 if(intel_crtc->plane > dev_priv->num_pipe) {
2304 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2305 intel_crtc->plane,
2306 dev_priv->num_pipe);
5c3b82e2 2307 return -EINVAL;
79e53945
JB		 2308 }
2309
5c3b82e2 2310 mutex_lock(&dev->struct_mutex);
265db958 2311 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2312 to_intel_framebuffer(fb)->obj,
919926ae 2313 NULL);
5c3b82e2
CW		 2314 if (ret != 0) {
2315 mutex_unlock(&dev->struct_mutex);
a5071c2f 2316 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2317 return ret;
2318 }
79e53945 2319
94352cf9
DV		 2320 if (crtc->fb)
2321 intel_finish_fb(crtc->fb);
265db958 2322
94352cf9 2323 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2324 if (ret) {
94352cf9 2325 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2326 mutex_unlock(&dev->struct_mutex);
a5071c2f 2327 DRM_ERROR("failed to update base address\n");
4e6cfefc 2328 return ret;
79e53945 2329 }
3c4fdcfb 2330
94352cf9
DV		 2331 old_fb = crtc->fb;
2332 crtc->fb = fb;
6c4c86f5
DV		 2333 crtc->x = x;
2334 crtc->y = y;
94352cf9 2335
b7f1de28
CW		 2336 if (old_fb) {
2337 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2338 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2339 }
652c393a 2340
6b8e6ed0 2341 intel_update_fbc(dev);
5c3b82e2 2342 mutex_unlock(&dev->struct_mutex);
79e53945 2343
198598d0 2344 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2345
2346 return 0;
79e53945
JB		 2347}
2348
5eddb70b 2349static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2350{
2351 struct drm_device *dev = crtc->dev;
2352 struct drm_i915_private *dev_priv = dev->dev_private;
2353 u32 dpa_ctl;
2354
28c97730 2355 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2356 dpa_ctl = I915_READ(DP_A);
2357 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2358
2359 if (clock < 200000) {
2360 u32 temp;
2361 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2362 /* workaround for 160Mhz:
2363 1) program 0x4600c bits 15:0 = 0x8124
2364 2) program 0x46010 bit 0 = 1
2365 3) program 0x46034 bit 24 = 1
2366 4) program 0x64000 bit 14 = 1
2367 */
2368 temp = I915_READ(0x4600c);
2369 temp &= 0xffff0000;
2370 I915_WRITE(0x4600c, temp | 0x8124);
2371
2372 temp = I915_READ(0x46010);
2373 I915_WRITE(0x46010, temp | 1);
2374
2375 temp = I915_READ(0x46034);
2376 I915_WRITE(0x46034, temp | (1 << 24));
2377 } else {
2378 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2379 }
2380 I915_WRITE(DP_A, dpa_ctl);
2381
5eddb70b 2382 POSTING_READ(DP_A);
32f9d658
ZW		 2383 udelay(500);
2384}
2385
5e84e1a4
ZW		 2386static void intel_fdi_normal_train(struct drm_crtc *crtc)
2387{
2388 struct drm_device *dev = crtc->dev;
2389 struct drm_i915_private *dev_priv = dev->dev_private;
2390 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2391 int pipe = intel_crtc->pipe;
2392 u32 reg, temp;
2393
2394 /* enable normal train */
2395 reg = FDI_TX_CTL(pipe);
2396 temp = I915_READ(reg);
61e499bf 2397 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2398 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2399 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2400 } else {
2401 temp &= ~FDI_LINK_TRAIN_NONE;
2402 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2403 }
5e84e1a4
ZW		 2404 I915_WRITE(reg, temp);
2405
2406 reg = FDI_RX_CTL(pipe);
2407 temp = I915_READ(reg);
2408 if (HAS_PCH_CPT(dev)) {
2409 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2410 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2411 } else {
2412 temp &= ~FDI_LINK_TRAIN_NONE;
2413 temp |= FDI_LINK_TRAIN_NONE;
2414 }
2415 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2416
2417 /* wait one idle pattern time */
2418 POSTING_READ(reg);
2419 udelay(1000);
357555c0
JB		 2420
2421 /* IVB wants error correction enabled */
2422 if (IS_IVYBRIDGE(dev))
2423 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2424 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2425}
2426
291427f5
JB		 2427static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2428{
2429 struct drm_i915_private *dev_priv = dev->dev_private;
2430 u32 flags = I915_READ(SOUTH_CHICKEN1);
2431
2432 flags |= FDI_PHASE_SYNC_OVR(pipe);
2433 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2434 flags |= FDI_PHASE_SYNC_EN(pipe);
2435 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2436 POSTING_READ(SOUTH_CHICKEN1);
2437}
2438
01a415fd
DV		 2439static void ivb_modeset_global_resources(struct drm_device *dev)
2440{
2441 struct drm_i915_private *dev_priv = dev->dev_private;
2442 struct intel_crtc *pipe_B_crtc =
2443 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2444 struct intel_crtc *pipe_C_crtc =
2445 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2446 uint32_t temp;
2447
2448 /* When everything is off disable fdi C so that we could enable fdi B
2449 * with all lanes. XXX: This misses the case where a pipe is not using
2450 * any pch resources and so doesn't need any fdi lanes. */
2451 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2452 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2453 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2454
2455 temp = I915_READ(SOUTH_CHICKEN1);
2456 temp &= ~FDI_BC_BIFURCATION_SELECT;
2457 DRM_DEBUG_KMS("disabling fdi C rx\n");
2458 I915_WRITE(SOUTH_CHICKEN1, temp);
2459 }
2460}
2461
8db9d77b
ZW		 2462/* The FDI link training functions for ILK/Ibexpeak. */
2463static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2464{
2465 struct drm_device *dev = crtc->dev;
2466 struct drm_i915_private *dev_priv = dev->dev_private;
2467 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2468 int pipe = intel_crtc->pipe;
0fc932b8 2469 int plane = intel_crtc->plane;
5eddb70b 2470 u32 reg, temp, tries;
8db9d77b 2471
0fc932b8
JB		 2472 /* FDI needs bits from pipe & plane first */
2473 assert_pipe_enabled(dev_priv, pipe);
2474 assert_plane_enabled(dev_priv, plane);
2475
e1a44743
AJ		 2476 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2477 for train result */
5eddb70b
CW		 2478 reg = FDI_RX_IMR(pipe);
2479 temp = I915_READ(reg);
e1a44743
AJ		 2480 temp &= ~FDI_RX_SYMBOL_LOCK;
2481 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2482 I915_WRITE(reg, temp);
2483 I915_READ(reg);
e1a44743
AJ		 2484 udelay(150);
2485
8db9d77b 2486 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2487 reg = FDI_TX_CTL(pipe);
2488 temp = I915_READ(reg);
77ffb597
AJ		 2489 temp &= ~(7 << 19);
2490 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2491 temp &= ~FDI_LINK_TRAIN_NONE;
2492 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2493 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2494
5eddb70b
CW		 2495 reg = FDI_RX_CTL(pipe);
2496 temp = I915_READ(reg);
8db9d77b
ZW		 2497 temp &= ~FDI_LINK_TRAIN_NONE;
2498 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2499 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2500
2501 POSTING_READ(reg);
8db9d77b
ZW		 2502 udelay(150);
2503
5b2adf89 2504 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2505 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2506 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2507 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2508
5eddb70b 2509 reg = FDI_RX_IIR(pipe);
e1a44743 2510 for (tries = 0; tries < 5; tries++) {
5eddb70b 2511 temp = I915_READ(reg);
8db9d77b
ZW		 2512 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2513
2514 if ((temp & FDI_RX_BIT_LOCK)) {
2515 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2516 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2517 break;
2518 }
8db9d77b 2519 }
e1a44743 2520 if (tries == 5)
5eddb70b 2521 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2522
2523 /* Train 2 */
5eddb70b
CW		 2524 reg = FDI_TX_CTL(pipe);
2525 temp = I915_READ(reg);
8db9d77b
ZW		 2526 temp &= ~FDI_LINK_TRAIN_NONE;
2527 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2528 I915_WRITE(reg, temp);
8db9d77b 2529
5eddb70b
CW		 2530 reg = FDI_RX_CTL(pipe);
2531 temp = I915_READ(reg);
8db9d77b
ZW		 2532 temp &= ~FDI_LINK_TRAIN_NONE;
2533 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2534 I915_WRITE(reg, temp);
8db9d77b 2535
5eddb70b
CW		 2536 POSTING_READ(reg);
2537 udelay(150);
8db9d77b 2538
5eddb70b 2539 reg = FDI_RX_IIR(pipe);
e1a44743 2540 for (tries = 0; tries < 5; tries++) {
5eddb70b 2541 temp = I915_READ(reg);
8db9d77b
ZW		 2542 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2543
2544 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2545 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2546 DRM_DEBUG_KMS("FDI train 2 done.\n");
2547 break;
2548 }
8db9d77b 2549 }
e1a44743 2550 if (tries == 5)
5eddb70b 2551 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2552
2553 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2554
8db9d77b
ZW		 2555}
2556
0206e353 2557static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2558 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2559 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2560 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2561 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2562};
2563
2564/* The FDI link training functions for SNB/Cougarpoint. */
2565static void gen6_fdi_link_train(struct drm_crtc *crtc)
2566{
2567 struct drm_device *dev = crtc->dev;
2568 struct drm_i915_private *dev_priv = dev->dev_private;
2569 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2570 int pipe = intel_crtc->pipe;
fa37d39e 2571 u32 reg, temp, i, retry;
8db9d77b 2572
e1a44743
AJ		 2573 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2574 for train result */
5eddb70b
CW		 2575 reg = FDI_RX_IMR(pipe);
2576 temp = I915_READ(reg);
e1a44743
AJ		 2577 temp &= ~FDI_RX_SYMBOL_LOCK;
2578 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2579 I915_WRITE(reg, temp);
2580
2581 POSTING_READ(reg);
e1a44743
AJ		 2582 udelay(150);
2583
8db9d77b 2584 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2585 reg = FDI_TX_CTL(pipe);
2586 temp = I915_READ(reg);
77ffb597
AJ		 2587 temp &= ~(7 << 19);
2588 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2589 temp &= ~FDI_LINK_TRAIN_NONE;
2590 temp |= FDI_LINK_TRAIN_PATTERN_1;
2591 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2592 /* SNB-B */
2593 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2594 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2595
d74cf324
DV		 2596 I915_WRITE(FDI_RX_MISC(pipe),
2597 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2598
5eddb70b
CW		 2599 reg = FDI_RX_CTL(pipe);
2600 temp = I915_READ(reg);
8db9d77b
ZW		 2601 if (HAS_PCH_CPT(dev)) {
2602 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2603 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2604 } else {
2605 temp &= ~FDI_LINK_TRAIN_NONE;
2606 temp |= FDI_LINK_TRAIN_PATTERN_1;
2607 }
5eddb70b
CW		 2608 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2609
2610 POSTING_READ(reg);
8db9d77b
ZW		 2611 udelay(150);
2612
8f5718a6 2613 cpt_phase_pointer_enable(dev, pipe);
291427f5 2614
0206e353 2615 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2616 reg = FDI_TX_CTL(pipe);
2617 temp = I915_READ(reg);
8db9d77b
ZW		 2618 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2619 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2620 I915_WRITE(reg, temp);
2621
2622 POSTING_READ(reg);
8db9d77b
ZW		 2623 udelay(500);
2624
fa37d39e
SP		 2625 for (retry = 0; retry < 5; retry++) {
2626 reg = FDI_RX_IIR(pipe);
2627 temp = I915_READ(reg);
2628 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2629 if (temp & FDI_RX_BIT_LOCK) {
2630 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2631 DRM_DEBUG_KMS("FDI train 1 done.\n");
2632 break;
2633 }
2634 udelay(50);
8db9d77b 2635 }
fa37d39e
SP		 2636 if (retry < 5)
2637 break;
8db9d77b
ZW		 2638 }
2639 if (i == 4)
5eddb70b 2640 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2641
2642 /* Train 2 */
5eddb70b
CW		 2643 reg = FDI_TX_CTL(pipe);
2644 temp = I915_READ(reg);
8db9d77b
ZW		 2645 temp &= ~FDI_LINK_TRAIN_NONE;
2646 temp |= FDI_LINK_TRAIN_PATTERN_2;
2647 if (IS_GEN6(dev)) {
2648 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2649 /* SNB-B */
2650 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2651 }
5eddb70b 2652 I915_WRITE(reg, temp);
8db9d77b 2653
5eddb70b
CW		 2654 reg = FDI_RX_CTL(pipe);
2655 temp = I915_READ(reg);
8db9d77b
ZW		 2656 if (HAS_PCH_CPT(dev)) {
2657 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2658 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2659 } else {
2660 temp &= ~FDI_LINK_TRAIN_NONE;
2661 temp |= FDI_LINK_TRAIN_PATTERN_2;
2662 }
5eddb70b
CW		 2663 I915_WRITE(reg, temp);
2664
2665 POSTING_READ(reg);
8db9d77b
ZW		 2666 udelay(150);
2667
0206e353 2668 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2669 reg = FDI_TX_CTL(pipe);
2670 temp = I915_READ(reg);
8db9d77b
ZW		 2671 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2672 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2673 I915_WRITE(reg, temp);
2674
2675 POSTING_READ(reg);
8db9d77b
ZW		 2676 udelay(500);
2677
fa37d39e
SP		 2678 for (retry = 0; retry < 5; retry++) {
2679 reg = FDI_RX_IIR(pipe);
2680 temp = I915_READ(reg);
2681 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2682 if (temp & FDI_RX_SYMBOL_LOCK) {
2683 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2684 DRM_DEBUG_KMS("FDI train 2 done.\n");
2685 break;
2686 }
2687 udelay(50);
8db9d77b 2688 }
fa37d39e
SP		 2689 if (retry < 5)
2690 break;
8db9d77b
ZW		 2691 }
2692 if (i == 4)
5eddb70b 2693 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2694
2695 DRM_DEBUG_KMS("FDI train done.\n");
2696}
2697
357555c0
JB		 2698/* Manual link training for Ivy Bridge A0 parts */
2699static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2700{
2701 struct drm_device *dev = crtc->dev;
2702 struct drm_i915_private *dev_priv = dev->dev_private;
2703 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2704 int pipe = intel_crtc->pipe;
2705 u32 reg, temp, i;
2706
2707 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2708 for train result */
2709 reg = FDI_RX_IMR(pipe);
2710 temp = I915_READ(reg);
2711 temp &= ~FDI_RX_SYMBOL_LOCK;
2712 temp &= ~FDI_RX_BIT_LOCK;
2713 I915_WRITE(reg, temp);
2714
2715 POSTING_READ(reg);
2716 udelay(150);
2717
01a415fd
DV		 2718 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2719 I915_READ(FDI_RX_IIR(pipe)));
2720
357555c0
JB		 2721 /* enable CPU FDI TX and PCH FDI RX */
2722 reg = FDI_TX_CTL(pipe);
2723 temp = I915_READ(reg);
2724 temp &= ~(7 << 19);
2725 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2726 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2727 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2728 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2729 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2730 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2731 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2732
d74cf324
DV		 2733 I915_WRITE(FDI_RX_MISC(pipe),
2734 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2735
357555c0
JB		 2736 reg = FDI_RX_CTL(pipe);
2737 temp = I915_READ(reg);
2738 temp &= ~FDI_LINK_TRAIN_AUTO;
2739 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2740 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2741 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2742 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2743
2744 POSTING_READ(reg);
2745 udelay(150);
2746
8f5718a6 2747 cpt_phase_pointer_enable(dev, pipe);
291427f5 2748
0206e353 2749 for (i = 0; i < 4; i++) {
357555c0
JB		 2750 reg = FDI_TX_CTL(pipe);
2751 temp = I915_READ(reg);
2752 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2753 temp |= snb_b_fdi_train_param[i];
2754 I915_WRITE(reg, temp);
2755
2756 POSTING_READ(reg);
2757 udelay(500);
2758
2759 reg = FDI_RX_IIR(pipe);
2760 temp = I915_READ(reg);
2761 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2762
2763 if (temp & FDI_RX_BIT_LOCK ||
2764 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2765 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2766 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2767 break;
2768 }
2769 }
2770 if (i == 4)
2771 DRM_ERROR("FDI train 1 fail!\n");
2772
2773 /* Train 2 */
2774 reg = FDI_TX_CTL(pipe);
2775 temp = I915_READ(reg);
2776 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2777 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2778 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2779 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2780 I915_WRITE(reg, temp);
2781
2782 reg = FDI_RX_CTL(pipe);
2783 temp = I915_READ(reg);
2784 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2785 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2786 I915_WRITE(reg, temp);
2787
2788 POSTING_READ(reg);
2789 udelay(150);
2790
0206e353 2791 for (i = 0; i < 4; i++) {
357555c0
JB		 2792 reg = FDI_TX_CTL(pipe);
2793 temp = I915_READ(reg);
2794 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2795 temp |= snb_b_fdi_train_param[i];
2796 I915_WRITE(reg, temp);
2797
2798 POSTING_READ(reg);
2799 udelay(500);
2800
2801 reg = FDI_RX_IIR(pipe);
2802 temp = I915_READ(reg);
2803 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2804
2805 if (temp & FDI_RX_SYMBOL_LOCK) {
2806 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2807 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2808 break;
2809 }
2810 }
2811 if (i == 4)
2812 DRM_ERROR("FDI train 2 fail!\n");
2813
2814 DRM_DEBUG_KMS("FDI train done.\n");
2815}
2816
88cefb6c 2817static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2818{
88cefb6c 2819 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2820 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2821 int pipe = intel_crtc->pipe;
5eddb70b 2822 u32 reg, temp;
79e53945 2823
c64e311e 2824
c98e9dcf 2825 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2826 reg = FDI_RX_CTL(pipe);
2827 temp = I915_READ(reg);
2828 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2829 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2830 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2831 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2832
2833 POSTING_READ(reg);
c98e9dcf
JB		 2834 udelay(200);
2835
2836 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2837 temp = I915_READ(reg);
2838 I915_WRITE(reg, temp | FDI_PCDCLK);
2839
2840 POSTING_READ(reg);
c98e9dcf
JB		 2841 udelay(200);
2842
bf507ef7
ED		 2843 /* On Haswell, the PLL configuration for ports and pipes is handled
2844 * separately, as part of DDI setup */
2845 if (!IS_HASWELL(dev)) {
2846 /* Enable CPU FDI TX PLL, always on for Ironlake */
2847 reg = FDI_TX_CTL(pipe);
2848 temp = I915_READ(reg);
2849 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2850 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2851
bf507ef7
ED		 2852 POSTING_READ(reg);
2853 udelay(100);
2854 }
6be4a607 2855 }
0e23b99d
JB		 2856}
2857
88cefb6c
DV		 2858static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2859{
2860 struct drm_device *dev = intel_crtc->base.dev;
2861 struct drm_i915_private *dev_priv = dev->dev_private;
2862 int pipe = intel_crtc->pipe;
2863 u32 reg, temp;
2864
2865 /* Switch from PCDclk to Rawclk */
2866 reg = FDI_RX_CTL(pipe);
2867 temp = I915_READ(reg);
2868 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2869
2870 /* Disable CPU FDI TX PLL */
2871 reg = FDI_TX_CTL(pipe);
2872 temp = I915_READ(reg);
2873 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2874
2875 POSTING_READ(reg);
2876 udelay(100);
2877
2878 reg = FDI_RX_CTL(pipe);
2879 temp = I915_READ(reg);
2880 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2881
2882 /* Wait for the clocks to turn off. */
2883 POSTING_READ(reg);
2884 udelay(100);
2885}
2886
291427f5
JB		 2887static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2888{
2889 struct drm_i915_private *dev_priv = dev->dev_private;
2890 u32 flags = I915_READ(SOUTH_CHICKEN1);
2891
2892 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2893 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2894 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2895 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2896 POSTING_READ(SOUTH_CHICKEN1);
2897}
0fc932b8
JB		 2898static void ironlake_fdi_disable(struct drm_crtc *crtc)
2899{
2900 struct drm_device *dev = crtc->dev;
2901 struct drm_i915_private *dev_priv = dev->dev_private;
2902 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2903 int pipe = intel_crtc->pipe;
2904 u32 reg, temp;
2905
2906 /* disable CPU FDI tx and PCH FDI rx */
2907 reg = FDI_TX_CTL(pipe);
2908 temp = I915_READ(reg);
2909 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2910 POSTING_READ(reg);
2911
2912 reg = FDI_RX_CTL(pipe);
2913 temp = I915_READ(reg);
2914 temp &= ~(0x7 << 16);
2915 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2916 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2917
2918 POSTING_READ(reg);
2919 udelay(100);
2920
2921 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2922 if (HAS_PCH_IBX(dev)) {
2923 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
291427f5
JB		 2924 } else if (HAS_PCH_CPT(dev)) {
2925 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2926 }
0fc932b8
JB		 2927
2928 /* still set train pattern 1 */
2929 reg = FDI_TX_CTL(pipe);
2930 temp = I915_READ(reg);
2931 temp &= ~FDI_LINK_TRAIN_NONE;
2932 temp |= FDI_LINK_TRAIN_PATTERN_1;
2933 I915_WRITE(reg, temp);
2934
2935 reg = FDI_RX_CTL(pipe);
2936 temp = I915_READ(reg);
2937 if (HAS_PCH_CPT(dev)) {
2938 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2939 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2940 } else {
2941 temp &= ~FDI_LINK_TRAIN_NONE;
2942 temp |= FDI_LINK_TRAIN_PATTERN_1;
2943 }
2944 /* BPC in FDI rx is consistent with that in PIPECONF */
2945 temp &= ~(0x07 << 16);
2946 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2947 I915_WRITE(reg, temp);
2948
2949 POSTING_READ(reg);
2950 udelay(100);
2951}
2952
5bb61643
CW		 2953static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2954{
2955 struct drm_device *dev = crtc->dev;
2956 struct drm_i915_private *dev_priv = dev->dev_private;
2957 unsigned long flags;
2958 bool pending;
2959
2960 if (atomic_read(&dev_priv->mm.wedged))
2961 return false;
2962
2963 spin_lock_irqsave(&dev->event_lock, flags);
2964 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2965 spin_unlock_irqrestore(&dev->event_lock, flags);
2966
2967 return pending;
2968}
2969
e6c3a2a6
CW		 2970static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2971{
0f91128d 2972 struct drm_device *dev = crtc->dev;
5bb61643 2973 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2974
2975 if (crtc->fb == NULL)
2976 return;
2977
5bb61643
CW		 2978 wait_event(dev_priv->pending_flip_queue,
2979 !intel_crtc_has_pending_flip(crtc));
2980
0f91128d
CW		 2981 mutex_lock(&dev->struct_mutex);
2982 intel_finish_fb(crtc->fb);
2983 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2984}
2985
fc316cbe 2986static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
040484af
JB		 2987{
2988 struct drm_device *dev = crtc->dev;
228d3e36 2989 struct intel_encoder *intel_encoder;
040484af
JB		 2990
2991 /*
2992 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2993 * must be driven by its own crtc; no sharing is possible.
2994 */
228d3e36 2995 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
228d3e36 2996 switch (intel_encoder->type) {
040484af 2997 case INTEL_OUTPUT_EDP:
228d3e36 2998 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
040484af
JB		 2999 return false;
3000 continue;
3001 }
3002 }
3003
3004 return true;
3005}
3006
fc316cbe
PZ		 3007static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
3008{
3009 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
3010}
3011
e615efe4
ED		 3012/* Program iCLKIP clock to the desired frequency */
3013static void lpt_program_iclkip(struct drm_crtc *crtc)
3014{
3015 struct drm_device *dev = crtc->dev;
3016 struct drm_i915_private *dev_priv = dev->dev_private;
3017 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3018 u32 temp;
3019
3020 /* It is necessary to ungate the pixclk gate prior to programming
3021 * the divisors, and gate it back when it is done.
3022 */
3023 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3024
3025 /* Disable SSCCTL */
3026 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3027 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
3028 SBI_SSCCTL_DISABLE);
3029
3030 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3031 if (crtc->mode.clock == 20000) {
3032 auxdiv = 1;
3033 divsel = 0x41;
3034 phaseinc = 0x20;
3035 } else {
3036 /* The iCLK virtual clock root frequency is in MHz,
3037 * but the crtc->mode.clock in in KHz. To get the divisors,
3038 * it is necessary to divide one by another, so we
3039 * convert the virtual clock precision to KHz here for higher
3040 * precision.
3041 */
3042 u32 iclk_virtual_root_freq = 172800 * 1000;
3043 u32 iclk_pi_range = 64;
3044 u32 desired_divisor, msb_divisor_value, pi_value;
3045
3046 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3047 msb_divisor_value = desired_divisor / iclk_pi_range;
3048 pi_value = desired_divisor % iclk_pi_range;
3049
3050 auxdiv = 0;
3051 divsel = msb_divisor_value - 2;
3052 phaseinc = pi_value;
3053 }
3054
3055 /* This should not happen with any sane values */
3056 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3057 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3058 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3059 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3060
3061 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3062 crtc->mode.clock,
3063 auxdiv,
3064 divsel,
3065 phasedir,
3066 phaseinc);
3067
3068 /* Program SSCDIVINTPHASE6 */
3069 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
3070 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3071 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3072 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3073 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3074 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3075 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3076
3077 intel_sbi_write(dev_priv,
3078 SBI_SSCDIVINTPHASE6,
3079 temp);
3080
3081 /* Program SSCAUXDIV */
3082 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
3083 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3084 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3085 intel_sbi_write(dev_priv,
3086 SBI_SSCAUXDIV6,
3087 temp);
3088
3089
3090 /* Enable modulator and associated divider */
3091 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
3092 temp &= ~SBI_SSCCTL_DISABLE;
3093 intel_sbi_write(dev_priv,
3094 SBI_SSCCTL6,
3095 temp);
3096
3097 /* Wait for initialization time */
3098 udelay(24);
3099
3100 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3101}
3102
f67a559d
JB		 3103/*
3104 * Enable PCH resources required for PCH ports:
3105 * - PCH PLLs
3106 * - FDI training & RX/TX
3107 * - update transcoder timings
3108 * - DP transcoding bits
3109 * - transcoder
3110 */
3111static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3112{
3113 struct drm_device *dev = crtc->dev;
3114 struct drm_i915_private *dev_priv = dev->dev_private;
3115 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3116 int pipe = intel_crtc->pipe;
ee7b9f93 3117 u32 reg, temp;
2c07245f 3118
e7e164db
CW		 3119 assert_transcoder_disabled(dev_priv, pipe);
3120
cd986abb
DV		 3121 /* Write the TU size bits before fdi link training, so that error
3122 * detection works. */
3123 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3124 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3125
c98e9dcf 3126 /* For PCH output, training FDI link */
674cf967 3127 dev_priv->display.fdi_link_train(crtc);
2c07245f 3128
572deb37
DV		 3129 /* XXX: pch pll's can be enabled any time before we enable the PCH
3130 * transcoder, and we actually should do this to not upset any PCH
3131 * transcoder that already use the clock when we share it.
3132 *
3133 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3134 * unconditionally resets the pll - we need that to have the right LVDS
3135 * enable sequence. */
b6b4e185 3136 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 3137
303b81e0 3138 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3139 u32 sel;
4b645f14 3140
c98e9dcf 3141 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3142 switch (pipe) {
3143 default:
3144 case 0:
3145 temp |= TRANSA_DPLL_ENABLE;
3146 sel = TRANSA_DPLLB_SEL;
3147 break;
3148 case 1:
3149 temp |= TRANSB_DPLL_ENABLE;
3150 sel = TRANSB_DPLLB_SEL;
3151 break;
3152 case 2:
3153 temp |= TRANSC_DPLL_ENABLE;
3154 sel = TRANSC_DPLLB_SEL;
3155 break;
d64311ab 3156 }
ee7b9f93
JB		 3157 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3158 temp |= sel;
3159 else
3160 temp &= ~sel;
c98e9dcf 3161 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3162 }
5eddb70b 3163
d9b6cb56
JB		 3164 /* set transcoder timing, panel must allow it */
3165 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3166 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3167 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3168 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3169
5eddb70b
CW		 3170 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3171 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3172 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3173 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3174
303b81e0 3175 intel_fdi_normal_train(crtc);
5e84e1a4 3176
c98e9dcf
JB		 3177 /* For PCH DP, enable TRANS_DP_CTL */
3178 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3179 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3180 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 3181 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 3182 reg = TRANS_DP_CTL(pipe);
3183 temp = I915_READ(reg);
3184 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3185 TRANS_DP_SYNC_MASK |
3186 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3187 temp |= (TRANS_DP_OUTPUT_ENABLE |
3188 TRANS_DP_ENH_FRAMING);
9325c9f0 3189 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3190
3191 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3192 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3193 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3194 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3195
3196 switch (intel_trans_dp_port_sel(crtc)) {
3197 case PCH_DP_B:
5eddb70b 3198 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3199 break;
3200 case PCH_DP_C:
5eddb70b 3201 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3202 break;
3203 case PCH_DP_D:
5eddb70b 3204 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3205 break;
3206 default:
e95d41e1 3207 BUG();
32f9d658 3208 }
2c07245f 3209
5eddb70b 3210 I915_WRITE(reg, temp);
6be4a607 3211 }
b52eb4dc 3212
b8a4f404 3213 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3214}
3215
1507e5bd
PZ		 3216static void lpt_pch_enable(struct drm_crtc *crtc)
3217{
3218 struct drm_device *dev = crtc->dev;
3219 struct drm_i915_private *dev_priv = dev->dev_private;
3220 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
daed2dbb 3221 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
1507e5bd 3222
daed2dbb 3223 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3224
8c52b5e8 3225 lpt_program_iclkip(crtc);
1507e5bd 3226
0540e488 3227 /* Set transcoder timing. */
daed2dbb
PZ		 3228 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3229 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3230 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
1507e5bd 3231
daed2dbb
PZ		 3232 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3233 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3234 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3235 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
1507e5bd 3236
937bb610 3237 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3238}
3239
ee7b9f93
JB		 3240static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3241{
3242 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3243
3244 if (pll == NULL)
3245 return;
3246
3247 if (pll->refcount == 0) {
3248 WARN(1, "bad PCH PLL refcount\n");
3249 return;
3250 }
3251
3252 --pll->refcount;
3253 intel_crtc->pch_pll = NULL;
3254}
3255
3256static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3257{
3258 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3259 struct intel_pch_pll *pll;
3260 int i;
3261
3262 pll = intel_crtc->pch_pll;
3263 if (pll) {
3264 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3265 intel_crtc->base.base.id, pll->pll_reg);
3266 goto prepare;
3267 }
3268
98b6bd99
DV		 3269 if (HAS_PCH_IBX(dev_priv->dev)) {
3270 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3271 i = intel_crtc->pipe;
3272 pll = &dev_priv->pch_plls[i];
3273
3274 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3275 intel_crtc->base.base.id, pll->pll_reg);
3276
3277 goto found;
3278 }
3279
ee7b9f93
JB		 3280 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3281 pll = &dev_priv->pch_plls[i];
3282
3283 /* Only want to check enabled timings first */
3284 if (pll->refcount == 0)
3285 continue;
3286
3287 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3288 fp == I915_READ(pll->fp0_reg)) {
3289 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3290 intel_crtc->base.base.id,
3291 pll->pll_reg, pll->refcount, pll->active);
3292
3293 goto found;
3294 }
3295 }
3296
3297 /* Ok no matching timings, maybe there's a free one? */
3298 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3299 pll = &dev_priv->pch_plls[i];
3300 if (pll->refcount == 0) {
3301 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3302 intel_crtc->base.base.id, pll->pll_reg);
3303 goto found;
3304 }
3305 }
3306
3307 return NULL;
3308
3309found:
3310 intel_crtc->pch_pll = pll;
3311 pll->refcount++;
3312 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3313prepare: /* separate function? */
3314 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3315
e04c7350
CW		 3316 /* Wait for the clocks to stabilize before rewriting the regs */
3317 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3318 POSTING_READ(pll->pll_reg);
3319 udelay(150);
e04c7350
CW		 3320
3321 I915_WRITE(pll->fp0_reg, fp);
3322 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3323 pll->on = false;
3324 return pll;
3325}
3326
d4270e57
JB		 3327void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3328{
3329 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3330 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3331 u32 temp;
3332
3333 temp = I915_READ(dslreg);
3334 udelay(500);
3335 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57
JB		 3336 if (wait_for(I915_READ(dslreg) != temp, 5))
3337 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3338 }
3339}
3340
f67a559d
JB		 3341static void ironlake_crtc_enable(struct drm_crtc *crtc)
3342{
3343 struct drm_device *dev = crtc->dev;
3344 struct drm_i915_private *dev_priv = dev->dev_private;
3345 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3346 struct intel_encoder *encoder;
f67a559d
JB		 3347 int pipe = intel_crtc->pipe;
3348 int plane = intel_crtc->plane;
3349 u32 temp;
3350 bool is_pch_port;
3351
08a48469
DV		 3352 WARN_ON(!crtc->enabled);
3353
f67a559d
JB		 3354 if (intel_crtc->active)
3355 return;
3356
3357 intel_crtc->active = true;
3358 intel_update_watermarks(dev);
3359
3360 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3361 temp = I915_READ(PCH_LVDS);
3362 if ((temp & LVDS_PORT_EN) == 0)
3363 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3364 }
3365
fc316cbe 3366 is_pch_port = ironlake_crtc_driving_pch(crtc);
f67a559d 3367
46b6f814 3368 if (is_pch_port) {
fff367c7
DV		 3369 /* Note: FDI PLL enabling _must_ be done before we enable the
3370 * cpu pipes, hence this is separate from all the other fdi/pch
3371 * enabling. */
88cefb6c 3372 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3373 } else {
3374 assert_fdi_tx_disabled(dev_priv, pipe);
3375 assert_fdi_rx_disabled(dev_priv, pipe);
3376 }
f67a559d 3377
bf49ec8c
DV		 3378 for_each_encoder_on_crtc(dev, crtc, encoder)
3379 if (encoder->pre_enable)
3380 encoder->pre_enable(encoder);
f67a559d
JB		 3381
3382 /* Enable panel fitting for LVDS */
3383 if (dev_priv->pch_pf_size &&
547dc041
JN		 3384 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3385 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
f67a559d
JB		 3386 /* Force use of hard-coded filter coefficients
3387 * as some pre-programmed values are broken,
3388 * e.g. x201.
3389 */
13888d78
PZ		 3390 if (IS_IVYBRIDGE(dev))
3391 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3392 PF_PIPE_SEL_IVB(pipe));
3393 else
3394 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
9db4a9c7
JB		 3395 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3396 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3397 }
3398
9c54c0dd
JB		 3399 /*
3400 * On ILK+ LUT must be loaded before the pipe is running but with
3401 * clocks enabled
3402 */
3403 intel_crtc_load_lut(crtc);
3404
f67a559d
JB		 3405 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3406 intel_enable_plane(dev_priv, plane, pipe);
3407
3408 if (is_pch_port)
3409 ironlake_pch_enable(crtc);
c98e9dcf 3410
d1ebd816 3411 mutex_lock(&dev->struct_mutex);
bed4a673 3412 intel_update_fbc(dev);
d1ebd816
BW		 3413 mutex_unlock(&dev->struct_mutex);
3414
6b383a7f 3415 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3416
fa5c73b1
DV		 3417 for_each_encoder_on_crtc(dev, crtc, encoder)
3418 encoder->enable(encoder);
61b77ddd
DV		 3419
3420 if (HAS_PCH_CPT(dev))
3421 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3422
3423 /*
3424 * There seems to be a race in PCH platform hw (at least on some
3425 * outputs) where an enabled pipe still completes any pageflip right
3426 * away (as if the pipe is off) instead of waiting for vblank. As soon
3427 * as the first vblank happend, everything works as expected. Hence just
3428 * wait for one vblank before returning to avoid strange things
3429 * happening.
3430 */
3431 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3432}
3433
4f771f10
PZ		 3434static void haswell_crtc_enable(struct drm_crtc *crtc)
3435{
3436 struct drm_device *dev = crtc->dev;
3437 struct drm_i915_private *dev_priv = dev->dev_private;
3438 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3439 struct intel_encoder *encoder;
3440 int pipe = intel_crtc->pipe;
3441 int plane = intel_crtc->plane;
4f771f10
PZ		 3442 bool is_pch_port;
3443
3444 WARN_ON(!crtc->enabled);
3445
3446 if (intel_crtc->active)
3447 return;
3448
3449 intel_crtc->active = true;
3450 intel_update_watermarks(dev);
3451
fc316cbe 3452 is_pch_port = haswell_crtc_driving_pch(crtc);
4f771f10 3453
83616634 3454 if (is_pch_port)
04945641 3455 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3456
3457 for_each_encoder_on_crtc(dev, crtc, encoder)
3458 if (encoder->pre_enable)
3459 encoder->pre_enable(encoder);
3460
1f544388 3461 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3462
1f544388 3463 /* Enable panel fitting for eDP */
547dc041
JN		 3464 if (dev_priv->pch_pf_size &&
3465 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4f771f10
PZ		 3466 /* Force use of hard-coded filter coefficients
3467 * as some pre-programmed values are broken,
3468 * e.g. x201.
3469 */
54075a7d
PZ		 3470 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3471 PF_PIPE_SEL_IVB(pipe));
4f771f10
PZ		 3472 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3473 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3474 }
3475
3476 /*
3477 * On ILK+ LUT must be loaded before the pipe is running but with
3478 * clocks enabled
3479 */
3480 intel_crtc_load_lut(crtc);
3481
1f544388
PZ		 3482 intel_ddi_set_pipe_settings(crtc);
3483 intel_ddi_enable_pipe_func(crtc);
4f771f10
PZ		 3484
3485 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3486 intel_enable_plane(dev_priv, plane, pipe);
3487
3488 if (is_pch_port)
1507e5bd 3489 lpt_pch_enable(crtc);
4f771f10
PZ		 3490
3491 mutex_lock(&dev->struct_mutex);
3492 intel_update_fbc(dev);
3493 mutex_unlock(&dev->struct_mutex);
3494
3495 intel_crtc_update_cursor(crtc, true);
3496
3497 for_each_encoder_on_crtc(dev, crtc, encoder)
3498 encoder->enable(encoder);
3499
4f771f10
PZ		 3500 /*
3501 * There seems to be a race in PCH platform hw (at least on some
3502 * outputs) where an enabled pipe still completes any pageflip right
3503 * away (as if the pipe is off) instead of waiting for vblank. As soon
3504 * as the first vblank happend, everything works as expected. Hence just
3505 * wait for one vblank before returning to avoid strange things
3506 * happening.
3507 */
3508 intel_wait_for_vblank(dev, intel_crtc->pipe);
3509}
3510
6be4a607
JB		 3511static void ironlake_crtc_disable(struct drm_crtc *crtc)
3512{
3513 struct drm_device *dev = crtc->dev;
3514 struct drm_i915_private *dev_priv = dev->dev_private;
3515 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3516 struct intel_encoder *encoder;
6be4a607
JB		 3517 int pipe = intel_crtc->pipe;
3518 int plane = intel_crtc->plane;
5eddb70b 3519 u32 reg, temp;
b52eb4dc 3520
ef9c3aee 3521
f7abfe8b
CW		 3522 if (!intel_crtc->active)
3523 return;
3524
ea9d758d
DV		 3525 for_each_encoder_on_crtc(dev, crtc, encoder)
3526 encoder->disable(encoder);
3527
e6c3a2a6 3528 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3529 drm_vblank_off(dev, pipe);
6b383a7f 3530 intel_crtc_update_cursor(crtc, false);
5eddb70b 3531
b24e7179 3532 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3533
973d04f9
CW		 3534 if (dev_priv->cfb_plane == plane)
3535 intel_disable_fbc(dev);
2c07245f 3536
b24e7179 3537 intel_disable_pipe(dev_priv, pipe);
32f9d658 3538
6be4a607 3539 /* Disable PF */
9db4a9c7
JB		 3540 I915_WRITE(PF_CTL(pipe), 0);
3541 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3542
bf49ec8c
DV		 3543 for_each_encoder_on_crtc(dev, crtc, encoder)
3544 if (encoder->post_disable)
3545 encoder->post_disable(encoder);
2c07245f 3546
0fc932b8 3547 ironlake_fdi_disable(crtc);
249c0e64 3548
b8a4f404 3549 ironlake_disable_pch_transcoder(dev_priv, pipe);
913d8d11 3550
6be4a607
JB		 3551 if (HAS_PCH_CPT(dev)) {
3552 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3553 reg = TRANS_DP_CTL(pipe);
3554 temp = I915_READ(reg);
3555 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3556 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3557 I915_WRITE(reg, temp);
6be4a607
JB		 3558
3559 /* disable DPLL_SEL */
3560 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3561 switch (pipe) {
3562 case 0:
d64311ab 3563 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3564 break;
3565 case 1:
6be4a607 3566 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3567 break;
3568 case 2:
4b645f14 3569 /* C shares PLL A or B */
d64311ab 3570 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3571 break;
3572 default:
3573 BUG(); /* wtf */
3574 }
6be4a607 3575 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3576 }
e3421a18 3577
6be4a607 3578 /* disable PCH DPLL */
ee7b9f93 3579 intel_disable_pch_pll(intel_crtc);
8db9d77b 3580
88cefb6c 3581 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3582
f7abfe8b 3583 intel_crtc->active = false;
6b383a7f 3584 intel_update_watermarks(dev);
d1ebd816
BW		 3585
3586 mutex_lock(&dev->struct_mutex);
6b383a7f 3587 intel_update_fbc(dev);
d1ebd816 3588 mutex_unlock(&dev->struct_mutex);
6be4a607 3589}
1b3c7a47 3590
4f771f10 3591static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3592{
4f771f10
PZ		 3593 struct drm_device *dev = crtc->dev;
3594 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3595 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3596 struct intel_encoder *encoder;
3597 int pipe = intel_crtc->pipe;
3598 int plane = intel_crtc->plane;
ad80a810 3599 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
83616634 3600 bool is_pch_port;
ee7b9f93 3601
4f771f10
PZ		 3602 if (!intel_crtc->active)
3603 return;
3604
83616634
PZ		 3605 is_pch_port = haswell_crtc_driving_pch(crtc);
3606
4f771f10
PZ		 3607 for_each_encoder_on_crtc(dev, crtc, encoder)
3608 encoder->disable(encoder);
3609
3610 intel_crtc_wait_for_pending_flips(crtc);
3611 drm_vblank_off(dev, pipe);
3612 intel_crtc_update_cursor(crtc, false);
3613
3614 intel_disable_plane(dev_priv, plane, pipe);
3615
3616 if (dev_priv->cfb_plane == plane)
3617 intel_disable_fbc(dev);
3618
3619 intel_disable_pipe(dev_priv, pipe);
3620
ad80a810 3621 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10
PZ		 3622
3623 /* Disable PF */
3624 I915_WRITE(PF_CTL(pipe), 0);
3625 I915_WRITE(PF_WIN_SZ(pipe), 0);
3626
1f544388 3627 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3628
3629 for_each_encoder_on_crtc(dev, crtc, encoder)
3630 if (encoder->post_disable)
3631 encoder->post_disable(encoder);
3632
83616634 3633 if (is_pch_port) {
ab4d966c 3634 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 3635 intel_ddi_fdi_disable(crtc);
83616634 3636 }
4f771f10
PZ		 3637
3638 intel_crtc->active = false;
3639 intel_update_watermarks(dev);
3640
3641 mutex_lock(&dev->struct_mutex);
3642 intel_update_fbc(dev);
3643 mutex_unlock(&dev->struct_mutex);
3644}
3645
ee7b9f93
JB		 3646static void ironlake_crtc_off(struct drm_crtc *crtc)
3647{
3648 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3649 intel_put_pch_pll(intel_crtc);
3650}
3651
6441ab5f
PZ		 3652static void haswell_crtc_off(struct drm_crtc *crtc)
3653{
a5c961d1
PZ		 3654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3655
3656 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3657 * start using it. */
3658 intel_crtc->cpu_transcoder = intel_crtc->pipe;
3659
6441ab5f
PZ		 3660 intel_ddi_put_crtc_pll(crtc);
3661}
3662
02e792fb
DV		 3663static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3664{
02e792fb 3665 if (!enable && intel_crtc->overlay) {
23f09ce3 3666 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3667 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3668
23f09ce3 3669 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3670 dev_priv->mm.interruptible = false;
3671 (void) intel_overlay_switch_off(intel_crtc->overlay);
3672 dev_priv->mm.interruptible = true;
23f09ce3 3673 mutex_unlock(&dev->struct_mutex);
02e792fb 3674 }
02e792fb 3675
5dcdbcb0
CW		 3676 /* Let userspace switch the overlay on again. In most cases userspace
3677 * has to recompute where to put it anyway.
3678 */
02e792fb
DV		 3679}
3680
0b8765c6 3681static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3682{
3683 struct drm_device *dev = crtc->dev;
79e53945
JB		 3684 struct drm_i915_private *dev_priv = dev->dev_private;
3685 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3686 struct intel_encoder *encoder;
79e53945 3687 int pipe = intel_crtc->pipe;
80824003 3688 int plane = intel_crtc->plane;
79e53945 3689
08a48469
DV		 3690 WARN_ON(!crtc->enabled);
3691
f7abfe8b
CW		 3692 if (intel_crtc->active)
3693 return;
3694
3695 intel_crtc->active = true;
6b383a7f
CW		 3696 intel_update_watermarks(dev);
3697
63d7bbe9 3698 intel_enable_pll(dev_priv, pipe);
040484af 3699 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3700 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3701
0b8765c6 3702 intel_crtc_load_lut(crtc);
bed4a673 3703 intel_update_fbc(dev);
79e53945 3704
0b8765c6
JB		 3705 /* Give the overlay scaler a chance to enable if it's on this pipe */
3706 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3707 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3708
fa5c73b1
DV		 3709 for_each_encoder_on_crtc(dev, crtc, encoder)
3710 encoder->enable(encoder);
0b8765c6 3711}
79e53945 3712
0b8765c6
JB		 3713static void i9xx_crtc_disable(struct drm_crtc *crtc)
3714{
3715 struct drm_device *dev = crtc->dev;
3716 struct drm_i915_private *dev_priv = dev->dev_private;
3717 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3718 struct intel_encoder *encoder;
0b8765c6
JB		 3719 int pipe = intel_crtc->pipe;
3720 int plane = intel_crtc->plane;
b690e96c 3721
ef9c3aee 3722
f7abfe8b
CW		 3723 if (!intel_crtc->active)
3724 return;
3725
ea9d758d
DV		 3726 for_each_encoder_on_crtc(dev, crtc, encoder)
3727 encoder->disable(encoder);
3728
0b8765c6 3729 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3730 intel_crtc_wait_for_pending_flips(crtc);
3731 drm_vblank_off(dev, pipe);
0b8765c6 3732 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3733 intel_crtc_update_cursor(crtc, false);
0b8765c6 3734
973d04f9
CW		 3735 if (dev_priv->cfb_plane == plane)
3736 intel_disable_fbc(dev);
79e53945 3737
b24e7179 3738 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3739 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3740 intel_disable_pll(dev_priv, pipe);
0b8765c6 3741
f7abfe8b 3742 intel_crtc->active = false;
6b383a7f
CW		 3743 intel_update_fbc(dev);
3744 intel_update_watermarks(dev);
0b8765c6
JB		 3745}
3746
ee7b9f93
JB		 3747static void i9xx_crtc_off(struct drm_crtc *crtc)
3748{
3749}
3750
976f8a20
DV		 3751static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3752 bool enabled)
2c07245f
ZW		 3753{
3754 struct drm_device *dev = crtc->dev;
3755 struct drm_i915_master_private *master_priv;
3756 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3757 int pipe = intel_crtc->pipe;
79e53945
JB		 3758
3759 if (!dev->primary->master)
3760 return;
3761
3762 master_priv = dev->primary->master->driver_priv;
3763 if (!master_priv->sarea_priv)
3764 return;
3765
79e53945
JB		 3766 switch (pipe) {
3767 case 0:
3768 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3769 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3770 break;
3771 case 1:
3772 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3773 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3774 break;
3775 default:
9db4a9c7 3776 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3777 break;
3778 }
79e53945
JB		 3779}
3780
976f8a20
DV		 3781/**
3782 * Sets the power management mode of the pipe and plane.
3783 */
3784void intel_crtc_update_dpms(struct drm_crtc *crtc)
3785{
3786 struct drm_device *dev = crtc->dev;
3787 struct drm_i915_private *dev_priv = dev->dev_private;
3788 struct intel_encoder *intel_encoder;
3789 bool enable = false;
3790
3791 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3792 enable |= intel_encoder->connectors_active;
3793
3794 if (enable)
3795 dev_priv->display.crtc_enable(crtc);
3796 else
3797 dev_priv->display.crtc_disable(crtc);
3798
3799 intel_crtc_update_sarea(crtc, enable);
3800}
3801
3802static void intel_crtc_noop(struct drm_crtc *crtc)
3803{
3804}
3805
cdd59983
CW		 3806static void intel_crtc_disable(struct drm_crtc *crtc)
3807{
cdd59983 3808 struct drm_device *dev = crtc->dev;
976f8a20 3809 struct drm_connector *connector;
ee7b9f93 3810 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 3811
976f8a20
DV		 3812 /* crtc should still be enabled when we disable it. */
3813 WARN_ON(!crtc->enabled);
3814
3815 dev_priv->display.crtc_disable(crtc);
3816 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3817 dev_priv->display.off(crtc);
3818
931872fc
CW		 3819 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3820 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3821
3822 if (crtc->fb) {
3823 mutex_lock(&dev->struct_mutex);
1690e1eb 3824 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3825 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3826 crtc->fb = NULL;
3827 }
3828
3829 /* Update computed state. */
3830 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3831 if (!connector->encoder || !connector->encoder->crtc)
3832 continue;
3833
3834 if (connector->encoder->crtc != crtc)
3835 continue;
3836
3837 connector->dpms = DRM_MODE_DPMS_OFF;
3838 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3839 }
3840}
3841
a261b246 3842void intel_modeset_disable(struct drm_device *dev)
79e53945 3843{
a261b246
DV		 3844 struct drm_crtc *crtc;
3845
3846 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3847 if (crtc->enabled)
3848 intel_crtc_disable(crtc);
3849 }
79e53945
JB		 3850}
3851
1f703855 3852void intel_encoder_noop(struct drm_encoder *encoder)
79e53945 3853{
7e7d76c3
JB		 3854}
3855
ea5b213a 3856void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3857{
4ef69c7a 3858 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3859
ea5b213a
CW		 3860 drm_encoder_cleanup(encoder);
3861 kfree(intel_encoder);
7e7d76c3
JB		 3862}
3863
5ab432ef
DV		 3864/* Simple dpms helper for encodres with just one connector, no cloning and only
3865 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3866 * state of the entire output pipe. */
3867void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3868{
5ab432ef
DV		 3869 if (mode == DRM_MODE_DPMS_ON) {
3870 encoder->connectors_active = true;
3871
b2cabb0e 3872 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3873 } else {
3874 encoder->connectors_active = false;
3875
b2cabb0e 3876 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3877 }
79e53945
JB		 3878}
3879
0a91ca29
DV		 3880/* Cross check the actual hw state with our own modeset state tracking (and it's
3881 * internal consistency). */
b980514c 3882static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3883{
0a91ca29
DV		 3884 if (connector->get_hw_state(connector)) {
3885 struct intel_encoder *encoder = connector->encoder;
3886 struct drm_crtc *crtc;
3887 bool encoder_enabled;
3888 enum pipe pipe;
3889
3890 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3891 connector->base.base.id,
3892 drm_get_connector_name(&connector->base));
3893
3894 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3895 "wrong connector dpms state\n");
3896 WARN(connector->base.encoder != &encoder->base,
3897 "active connector not linked to encoder\n");
3898 WARN(!encoder->connectors_active,
3899 "encoder->connectors_active not set\n");
3900
3901 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3902 WARN(!encoder_enabled, "encoder not enabled\n");
3903 if (WARN_ON(!encoder->base.crtc))
3904 return;
3905
3906 crtc = encoder->base.crtc;
3907
3908 WARN(!crtc->enabled, "crtc not enabled\n");
3909 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3910 WARN(pipe != to_intel_crtc(crtc)->pipe,
3911 "encoder active on the wrong pipe\n");
3912 }
79e53945
JB		 3913}
3914
5ab432ef
DV		 3915/* Even simpler default implementation, if there's really no special case to
3916 * consider. */
3917void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3918{
5ab432ef 3919 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3920
5ab432ef
DV		 3921 /* All the simple cases only support two dpms states. */
3922 if (mode != DRM_MODE_DPMS_ON)
3923 mode = DRM_MODE_DPMS_OFF;
d4270e57 3924
5ab432ef
DV		 3925 if (mode == connector->dpms)
3926 return;
3927
3928 connector->dpms = mode;
3929
3930 /* Only need to change hw state when actually enabled */
3931 if (encoder->base.crtc)
3932 intel_encoder_dpms(encoder, mode);
3933 else
8af6cf88 3934 WARN_ON(encoder->connectors_active != false);
0a91ca29 3935
b980514c 3936 intel_modeset_check_state(connector->dev);
79e53945
JB		 3937}
3938
f0947c37
DV		 3939/* Simple connector->get_hw_state implementation for encoders that support only
3940 * one connector and no cloning and hence the encoder state determines the state
3941 * of the connector. */
3942bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3943{
24929352 3944 enum pipe pipe = 0;
f0947c37 3945 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3946
f0947c37 3947 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3948}
3949
79e53945 3950static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
35313cde 3951 const struct drm_display_mode *mode,
79e53945
JB		 3952 struct drm_display_mode *adjusted_mode)
3953{
2c07245f 3954 struct drm_device *dev = crtc->dev;
89749350 3955
bad720ff 3956 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3957 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3958 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3959 return false;
2c07245f 3960 }
89749350 3961
f9bef081
DV		 3962 /* All interlaced capable intel hw wants timings in frames. Note though
3963 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3964 * timings, so we need to be careful not to clobber these.*/
3965 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3966 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3967
44f46b42
CW		 3968 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3969 * with a hsync front porch of 0.
3970 */
3971 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3972 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3973 return false;
3974
79e53945
JB		 3975 return true;
3976}
3977
25eb05fc
JB		 3978static int valleyview_get_display_clock_speed(struct drm_device *dev)
3979{
3980 return 400000; /* FIXME */
3981}
3982
e70236a8
JB		 3983static int i945_get_display_clock_speed(struct drm_device *dev)
3984{
3985 return 400000;
3986}
79e53945 3987
e70236a8 3988static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3989{
e70236a8
JB		 3990 return 333000;
3991}
79e53945 3992
e70236a8
JB		 3993static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3994{
3995 return 200000;
3996}
79e53945 3997
e70236a8
JB		 3998static int i915gm_get_display_clock_speed(struct drm_device *dev)
3999{
4000 u16 gcfgc = 0;
79e53945 4001
e70236a8
JB		 4002 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4003
4004 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4005 return 133000;
4006 else {
4007 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4008 case GC_DISPLAY_CLOCK_333_MHZ:
4009 return 333000;
4010 default:
4011 case GC_DISPLAY_CLOCK_190_200_MHZ:
4012 return 190000;
79e53945 4013 }
e70236a8
JB		 4014 }
4015}
4016
4017static int i865_get_display_clock_speed(struct drm_device *dev)
4018{
4019 return 266000;
4020}
4021
4022static int i855_get_display_clock_speed(struct drm_device *dev)
4023{
4024 u16 hpllcc = 0;
4025 /* Assume that the hardware is in the high speed state. This
4026 * should be the default.
4027 */
4028 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4029 case GC_CLOCK_133_200:
4030 case GC_CLOCK_100_200:
4031 return 200000;
4032 case GC_CLOCK_166_250:
4033 return 250000;
4034 case GC_CLOCK_100_133:
79e53945 4035 return 133000;
e70236a8 4036 }
79e53945 4037
e70236a8
JB		 4038 /* Shouldn't happen */
4039 return 0;
4040}
79e53945 4041
e70236a8
JB		 4042static int i830_get_display_clock_speed(struct drm_device *dev)
4043{
4044 return 133000;
79e53945
JB		 4045}
4046
2c07245f
ZW		 4047struct fdi_m_n {
4048 u32 tu;
4049 u32 gmch_m;
4050 u32 gmch_n;
4051 u32 link_m;
4052 u32 link_n;
4053};
4054
4055static void
4056fdi_reduce_ratio(u32 *num, u32 *den)
4057{
4058 while (*num > 0xffffff || *den > 0xffffff) {
4059 *num >>= 1;
4060 *den >>= 1;
4061 }
4062}
4063
2c07245f 4064static void
f2b115e6
AJ		 4065ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
4066 int link_clock, struct fdi_m_n *m_n)
2c07245f 4067{
2c07245f
ZW		 4068 m_n->tu = 64; /* default size */
4069
22ed1113
CW		 4070 /* BUG_ON(pixel_clock > INT_MAX / 36); */
4071 m_n->gmch_m = bits_per_pixel * pixel_clock;
4072 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 4073 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4074
22ed1113
CW		 4075 m_n->link_m = pixel_clock;
4076 m_n->link_n = link_clock;
2c07245f
ZW		 4077 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
4078}
4079
a7615030
CW		 4080static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4081{
72bbe58c
KP		 4082 if (i915_panel_use_ssc >= 0)
4083 return i915_panel_use_ssc != 0;
4084 return dev_priv->lvds_use_ssc
435793df 4085 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4086}
4087
5a354204
JB		 4088/**
4089 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4090 * @crtc: CRTC structure
3b5c78a3 4091 * @mode: requested mode
5a354204
JB		 4092 *
4093 * A pipe may be connected to one or more outputs. Based on the depth of the
4094 * attached framebuffer, choose a good color depth to use on the pipe.
4095 *
4096 * If possible, match the pipe depth to the fb depth. In some cases, this
4097 * isn't ideal, because the connected output supports a lesser or restricted
4098 * set of depths. Resolve that here:
4099 * LVDS typically supports only 6bpc, so clamp down in that case
4100 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4101 * Displays may support a restricted set as well, check EDID and clamp as
4102 * appropriate.
3b5c78a3 4103 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 4104 *
4105 * RETURNS:
4106 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4107 * true if they don't match).
4108 */
4109static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
94352cf9 4110 struct drm_framebuffer *fb,
3b5c78a3
AJ		 4111 unsigned int *pipe_bpp,
4112 struct drm_display_mode *mode)
5a354204
JB		 4113{
4114 struct drm_device *dev = crtc->dev;
4115 struct drm_i915_private *dev_priv = dev->dev_private;
5a354204 4116 struct drm_connector *connector;
6c2b7c12 4117 struct intel_encoder *intel_encoder;
5a354204
JB		 4118 unsigned int display_bpc = UINT_MAX, bpc;
4119
4120 /* Walk the encoders & connectors on this crtc, get min bpc */
6c2b7c12 4121 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5a354204
JB		 4122
4123 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4124 unsigned int lvds_bpc;
4125
4126 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4127 LVDS_A3_POWER_UP)
4128 lvds_bpc = 8;
4129 else
4130 lvds_bpc = 6;
4131
4132 if (lvds_bpc < display_bpc) {
82820490 4133 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 4134 display_bpc = lvds_bpc;
4135 }
4136 continue;
4137 }
4138
5a354204
JB		 4139 /* Not one of the known troublemakers, check the EDID */
4140 list_for_each_entry(connector, &dev->mode_config.connector_list,
4141 head) {
6c2b7c12 4142 if (connector->encoder != &intel_encoder->base)
5a354204
JB		 4143 continue;
4144
62ac41a6
JB		 4145 /* Don't use an invalid EDID bpc value */
4146 if (connector->display_info.bpc &&
4147 connector->display_info.bpc < display_bpc) {
82820490 4148 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 4149 display_bpc = connector->display_info.bpc;
4150 }
4151 }
4152
4153 /*
4154 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4155 * through, clamp it down. (Note: >12bpc will be caught below.)
4156 */
4157 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4158 if (display_bpc > 8 && display_bpc < 12) {
82820490 4159 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 4160 display_bpc = 12;
4161 } else {
82820490 4162 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 4163 display_bpc = 8;
4164 }
4165 }
4166 }
4167
3b5c78a3
AJ		 4168 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4169 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4170 display_bpc = 6;
4171 }
4172
5a354204
JB		 4173 /*
4174 * We could just drive the pipe at the highest bpc all the time and
4175 * enable dithering as needed, but that costs bandwidth. So choose
4176 * the minimum value that expresses the full color range of the fb but
4177 * also stays within the max display bpc discovered above.
4178 */
4179
94352cf9 4180 switch (fb->depth) {
5a354204
JB		 4181 case 8:
4182 bpc = 8; /* since we go through a colormap */
4183 break;
4184 case 15:
4185 case 16:
4186 bpc = 6; /* min is 18bpp */
4187 break;
4188 case 24:
578393cd 4189 bpc = 8;
5a354204
JB		 4190 break;
4191 case 30:
578393cd 4192 bpc = 10;
5a354204
JB		 4193 break;
4194 case 48:
578393cd 4195 bpc = 12;
5a354204
JB		 4196 break;
4197 default:
4198 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4199 bpc = min((unsigned int)8, display_bpc);
4200 break;
4201 }
4202
578393cd
KP		 4203 display_bpc = min(display_bpc, bpc);
4204
82820490
AJ		 4205 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4206 bpc, display_bpc);
5a354204 4207
578393cd 4208 *pipe_bpp = display_bpc * 3;
5a354204
JB		 4209
4210 return display_bpc != bpc;
4211}
4212
a0c4da24
JB		 4213static int vlv_get_refclk(struct drm_crtc *crtc)
4214{
4215 struct drm_device *dev = crtc->dev;
4216 struct drm_i915_private *dev_priv = dev->dev_private;
4217 int refclk = 27000; /* for DP & HDMI */
4218
4219 return 100000; /* only one validated so far */
4220
4221 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4222 refclk = 96000;
4223 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4224 if (intel_panel_use_ssc(dev_priv))
4225 refclk = 100000;
4226 else
4227 refclk = 96000;
4228 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4229 refclk = 100000;
4230 }
4231
4232 return refclk;
4233}
4234
c65d77d8
JB		 4235static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4236{
4237 struct drm_device *dev = crtc->dev;
4238 struct drm_i915_private *dev_priv = dev->dev_private;
4239 int refclk;
4240
a0c4da24
JB		 4241 if (IS_VALLEYVIEW(dev)) {
4242 refclk = vlv_get_refclk(crtc);
4243 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 4244 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4245 refclk = dev_priv->lvds_ssc_freq * 1000;
4246 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4247 refclk / 1000);
4248 } else if (!IS_GEN2(dev)) {
4249 refclk = 96000;
4250 } else {
4251 refclk = 48000;
4252 }
4253
4254 return refclk;
4255}
4256
4257static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4258 intel_clock_t *clock)
4259{
4260 /* SDVO TV has fixed PLL values depend on its clock range,
4261 this mirrors vbios setting. */
4262 if (adjusted_mode->clock >= 100000
4263 && adjusted_mode->clock < 140500) {
4264 clock->p1 = 2;
4265 clock->p2 = 10;
4266 clock->n = 3;
4267 clock->m1 = 16;
4268 clock->m2 = 8;
4269 } else if (adjusted_mode->clock >= 140500
4270 && adjusted_mode->clock <= 200000) {
4271 clock->p1 = 1;
4272 clock->p2 = 10;
4273 clock->n = 6;
4274 clock->m1 = 12;
4275 clock->m2 = 8;
4276 }
4277}
4278
a7516a05
JB		 4279static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4280 intel_clock_t *clock,
4281 intel_clock_t *reduced_clock)
4282{
4283 struct drm_device *dev = crtc->dev;
4284 struct drm_i915_private *dev_priv = dev->dev_private;
4285 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4286 int pipe = intel_crtc->pipe;
4287 u32 fp, fp2 = 0;
4288
4289 if (IS_PINEVIEW(dev)) {
4290 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4291 if (reduced_clock)
4292 fp2 = (1 << reduced_clock->n) << 16 |
4293 reduced_clock->m1 << 8 | reduced_clock->m2;
4294 } else {
4295 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4296 if (reduced_clock)
4297 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4298 reduced_clock->m2;
4299 }
4300
4301 I915_WRITE(FP0(pipe), fp);
4302
4303 intel_crtc->lowfreq_avail = false;
4304 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4305 reduced_clock && i915_powersave) {
4306 I915_WRITE(FP1(pipe), fp2);
4307 intel_crtc->lowfreq_avail = true;
4308 } else {
4309 I915_WRITE(FP1(pipe), fp);
4310 }
4311}
4312
93e537a1
DV		 4313static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4314 struct drm_display_mode *adjusted_mode)
4315{
4316 struct drm_device *dev = crtc->dev;
4317 struct drm_i915_private *dev_priv = dev->dev_private;
4318 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4319 int pipe = intel_crtc->pipe;
284d5df5 4320 u32 temp;
93e537a1
DV		 4321
4322 temp = I915_READ(LVDS);
4323 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4324 if (pipe == 1) {
4325 temp |= LVDS_PIPEB_SELECT;
4326 } else {
4327 temp &= ~LVDS_PIPEB_SELECT;
4328 }
4329 /* set the corresponsding LVDS_BORDER bit */
4330 temp |= dev_priv->lvds_border_bits;
4331 /* Set the B0-B3 data pairs corresponding to whether we're going to
4332 * set the DPLLs for dual-channel mode or not.
4333 */
4334 if (clock->p2 == 7)
4335 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4336 else
4337 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4338
4339 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4340 * appropriately here, but we need to look more thoroughly into how
4341 * panels behave in the two modes.
4342 */
4343 /* set the dithering flag on LVDS as needed */
4344 if (INTEL_INFO(dev)->gen >= 4) {
4345 if (dev_priv->lvds_dither)
4346 temp |= LVDS_ENABLE_DITHER;
4347 else
4348 temp &= ~LVDS_ENABLE_DITHER;
4349 }
284d5df5 4350 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
93e537a1 4351 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 4352 temp |= LVDS_HSYNC_POLARITY;
93e537a1 4353 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 4354 temp |= LVDS_VSYNC_POLARITY;
93e537a1
DV		 4355 I915_WRITE(LVDS, temp);
4356}
4357
a0c4da24
JB		 4358static void vlv_update_pll(struct drm_crtc *crtc,
4359 struct drm_display_mode *mode,
4360 struct drm_display_mode *adjusted_mode,
4361 intel_clock_t *clock, intel_clock_t *reduced_clock,
2a8f64ca 4362 int num_connectors)
a0c4da24
JB		 4363{
4364 struct drm_device *dev = crtc->dev;
4365 struct drm_i915_private *dev_priv = dev->dev_private;
4366 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4367 int pipe = intel_crtc->pipe;
4368 u32 dpll, mdiv, pdiv;
4369 u32 bestn, bestm1, bestm2, bestp1, bestp2;
2a8f64ca
VP		 4370 bool is_sdvo;
4371 u32 temp;
a0c4da24 4372
2a8f64ca
VP		 4373 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4374 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
a0c4da24 4375
2a8f64ca
VP		 4376 dpll = DPLL_VGA_MODE_DIS;
4377 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4378 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4379 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4380
4381 I915_WRITE(DPLL(pipe), dpll);
4382 POSTING_READ(DPLL(pipe));
a0c4da24
JB		 4383
4384 bestn = clock->n;
4385 bestm1 = clock->m1;
4386 bestm2 = clock->m2;
4387 bestp1 = clock->p1;
4388 bestp2 = clock->p2;
4389
2a8f64ca
VP		 4390 /*
4391 * In Valleyview PLL and program lane counter registers are exposed
4392 * through DPIO interface
4393 */
a0c4da24
JB		 4394 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4395 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4396 mdiv |= ((bestn << DPIO_N_SHIFT));
4397 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4398 mdiv |= (1 << DPIO_K_SHIFT);
4399 mdiv |= DPIO_ENABLE_CALIBRATION;
4400 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4401
4402 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4403
2a8f64ca 4404 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
a0c4da24 4405 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
2a8f64ca
VP		 4406 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4407 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
a0c4da24
JB		 4408 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4409
2a8f64ca 4410 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
a0c4da24
JB		 4411
4412 dpll |= DPLL_VCO_ENABLE;
4413 I915_WRITE(DPLL(pipe), dpll);
4414 POSTING_READ(DPLL(pipe));
4415 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4416 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4417
2a8f64ca
VP		 4418 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4419
4420 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4421 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4422
4423 I915_WRITE(DPLL(pipe), dpll);
4424
4425 /* Wait for the clocks to stabilize. */
4426 POSTING_READ(DPLL(pipe));
4427 udelay(150);
a0c4da24 4428
2a8f64ca
VP		 4429 temp = 0;
4430 if (is_sdvo) {
4431 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
a0c4da24
JB		 4432 if (temp > 1)
4433 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4434 else
4435 temp = 0;
a0c4da24 4436 }
2a8f64ca
VP		 4437 I915_WRITE(DPLL_MD(pipe), temp);
4438 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4439
2a8f64ca
VP		 4440 /* Now program lane control registers */
4441 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4442 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4443 {
4444 temp = 0x1000C4;
4445 if(pipe == 1)
4446 temp |= (1 << 21);
4447 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4448 }
4449 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4450 {
4451 temp = 0x1000C4;
4452 if(pipe == 1)
4453 temp |= (1 << 21);
4454 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4455 }
a0c4da24
JB		 4456}
4457
eb1cbe48
DV		 4458static void i9xx_update_pll(struct drm_crtc *crtc,
4459 struct drm_display_mode *mode,
4460 struct drm_display_mode *adjusted_mode,
4461 intel_clock_t *clock, intel_clock_t *reduced_clock,
4462 int num_connectors)
4463{
4464 struct drm_device *dev = crtc->dev;
4465 struct drm_i915_private *dev_priv = dev->dev_private;
4466 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dafd226c 4467 struct intel_encoder *encoder;
eb1cbe48
DV		 4468 int pipe = intel_crtc->pipe;
4469 u32 dpll;
4470 bool is_sdvo;
4471
2a8f64ca
VP		 4472 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4473
eb1cbe48
DV		 4474 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4475 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4476
4477 dpll = DPLL_VGA_MODE_DIS;
4478
4479 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4480 dpll |= DPLLB_MODE_LVDS;
4481 else
4482 dpll |= DPLLB_MODE_DAC_SERIAL;
4483 if (is_sdvo) {
4484 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4485 if (pixel_multiplier > 1) {
4486 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4487 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4488 }
4489 dpll |= DPLL_DVO_HIGH_SPEED;
4490 }
4491 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4492 dpll |= DPLL_DVO_HIGH_SPEED;
4493
4494 /* compute bitmask from p1 value */
4495 if (IS_PINEVIEW(dev))
4496 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4497 else {
4498 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4499 if (IS_G4X(dev) && reduced_clock)
4500 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4501 }
4502 switch (clock->p2) {
4503 case 5:
4504 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4505 break;
4506 case 7:
4507 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4508 break;
4509 case 10:
4510 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4511 break;
4512 case 14:
4513 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4514 break;
4515 }
4516 if (INTEL_INFO(dev)->gen >= 4)
4517 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4518
4519 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4520 dpll |= PLL_REF_INPUT_TVCLKINBC;
4521 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4522 /* XXX: just matching BIOS for now */
4523 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4524 dpll |= 3;
4525 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4526 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4527 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4528 else
4529 dpll |= PLL_REF_INPUT_DREFCLK;
4530
4531 dpll |= DPLL_VCO_ENABLE;
4532 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4533 POSTING_READ(DPLL(pipe));
4534 udelay(150);
4535
dafd226c
DV		 4536 for_each_encoder_on_crtc(dev, crtc, encoder)
4537 if (encoder->pre_pll_enable)
4538 encoder->pre_pll_enable(encoder);
4539
eb1cbe48
DV		 4540 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4541 * This is an exception to the general rule that mode_set doesn't turn
4542 * things on.
4543 */
4544 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4545 intel_update_lvds(crtc, clock, adjusted_mode);
4546
4547 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4548 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4549
4550 I915_WRITE(DPLL(pipe), dpll);
4551
4552 /* Wait for the clocks to stabilize. */
4553 POSTING_READ(DPLL(pipe));
4554 udelay(150);
4555
4556 if (INTEL_INFO(dev)->gen >= 4) {
4557 u32 temp = 0;
4558 if (is_sdvo) {
4559 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4560 if (temp > 1)
4561 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4562 else
4563 temp = 0;
4564 }
4565 I915_WRITE(DPLL_MD(pipe), temp);
4566 } else {
4567 /* The pixel multiplier can only be updated once the
4568 * DPLL is enabled and the clocks are stable.
4569 *
4570 * So write it again.
4571 */
4572 I915_WRITE(DPLL(pipe), dpll);
4573 }
4574}
4575
4576static void i8xx_update_pll(struct drm_crtc *crtc,
4577 struct drm_display_mode *adjusted_mode,
2a8f64ca 4578 intel_clock_t *clock, intel_clock_t *reduced_clock,
eb1cbe48
DV		 4579 int num_connectors)
4580{
4581 struct drm_device *dev = crtc->dev;
4582 struct drm_i915_private *dev_priv = dev->dev_private;
4583 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dafd226c 4584 struct intel_encoder *encoder;
eb1cbe48
DV		 4585 int pipe = intel_crtc->pipe;
4586 u32 dpll;
4587
2a8f64ca
VP		 4588 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4589
eb1cbe48
DV		 4590 dpll = DPLL_VGA_MODE_DIS;
4591
4592 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4593 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4594 } else {
4595 if (clock->p1 == 2)
4596 dpll |= PLL_P1_DIVIDE_BY_TWO;
4597 else
4598 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4599 if (clock->p2 == 4)
4600 dpll |= PLL_P2_DIVIDE_BY_4;
4601 }
4602
4603 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4604 /* XXX: just matching BIOS for now */
4605 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4606 dpll |= 3;
4607 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4608 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4609 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4610 else
4611 dpll |= PLL_REF_INPUT_DREFCLK;
4612
4613 dpll |= DPLL_VCO_ENABLE;
4614 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4615 POSTING_READ(DPLL(pipe));
4616 udelay(150);
4617
dafd226c
DV		 4618 for_each_encoder_on_crtc(dev, crtc, encoder)
4619 if (encoder->pre_pll_enable)
4620 encoder->pre_pll_enable(encoder);
4621
eb1cbe48
DV		 4622 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4623 * This is an exception to the general rule that mode_set doesn't turn
4624 * things on.
4625 */
4626 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4627 intel_update_lvds(crtc, clock, adjusted_mode);
4628
5b5896e4
DV		 4629 I915_WRITE(DPLL(pipe), dpll);
4630
4631 /* Wait for the clocks to stabilize. */
4632 POSTING_READ(DPLL(pipe));
4633 udelay(150);
4634
eb1cbe48
DV		 4635 /* The pixel multiplier can only be updated once the
4636 * DPLL is enabled and the clocks are stable.
4637 *
4638 * So write it again.
4639 */
4640 I915_WRITE(DPLL(pipe), dpll);
4641}
4642
b0e77b9c
PZ		 4643static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4644 struct drm_display_mode *mode,
4645 struct drm_display_mode *adjusted_mode)
4646{
4647 struct drm_device *dev = intel_crtc->base.dev;
4648 struct drm_i915_private *dev_priv = dev->dev_private;
4649 enum pipe pipe = intel_crtc->pipe;
fe2b8f9d 4650 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
b0e77b9c
PZ		 4651 uint32_t vsyncshift;
4652
4653 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4654 /* the chip adds 2 halflines automatically */
4655 adjusted_mode->crtc_vtotal -= 1;
4656 adjusted_mode->crtc_vblank_end -= 1;
4657 vsyncshift = adjusted_mode->crtc_hsync_start
4658 - adjusted_mode->crtc_htotal / 2;
4659 } else {
4660 vsyncshift = 0;
4661 }
4662
4663 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4664 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4665
fe2b8f9d 4666 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4667 (adjusted_mode->crtc_hdisplay - 1) |
4668 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4669 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4670 (adjusted_mode->crtc_hblank_start - 1) |
4671 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4672 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4673 (adjusted_mode->crtc_hsync_start - 1) |
4674 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4675
fe2b8f9d 4676 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4677 (adjusted_mode->crtc_vdisplay - 1) |
4678 ((adjusted_mode->crtc_vtotal - 1) << 16));
fe2b8f9d 4679 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c
PZ		 4680 (adjusted_mode->crtc_vblank_start - 1) |
4681 ((adjusted_mode->crtc_vblank_end - 1) << 16));
fe2b8f9d 4682 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4683 (adjusted_mode->crtc_vsync_start - 1) |
4684 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4685
b5e508d4
PZ		 4686 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4687 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4688 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4689 * bits. */
4690 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4691 (pipe == PIPE_B || pipe == PIPE_C))
4692 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4693
b0e77b9c
PZ		 4694 /* pipesrc controls the size that is scaled from, which should
4695 * always be the user's requested size.
4696 */
4697 I915_WRITE(PIPESRC(pipe),
4698 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4699}
4700
f564048e
EA		 4701static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4702 struct drm_display_mode *mode,
4703 struct drm_display_mode *adjusted_mode,
4704 int x, int y,
94352cf9 4705 struct drm_framebuffer *fb)
79e53945
JB		 4706{
4707 struct drm_device *dev = crtc->dev;
4708 struct drm_i915_private *dev_priv = dev->dev_private;
4709 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4710 int pipe = intel_crtc->pipe;
80824003 4711 int plane = intel_crtc->plane;
c751ce4f 4712 int refclk, num_connectors = 0;
652c393a 4713 intel_clock_t clock, reduced_clock;
b0e77b9c 4714 u32 dspcntr, pipeconf;
eb1cbe48
DV		 4715 bool ok, has_reduced_clock = false, is_sdvo = false;
4716 bool is_lvds = false, is_tv = false, is_dp = false;
5eddb70b 4717 struct intel_encoder *encoder;
d4906093 4718 const intel_limit_t *limit;
5c3b82e2 4719 int ret;
79e53945 4720
6c2b7c12 4721 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4722 switch (encoder->type) {
79e53945
JB		 4723 case INTEL_OUTPUT_LVDS:
4724 is_lvds = true;
4725 break;
4726 case INTEL_OUTPUT_SDVO:
7d57382e 4727 case INTEL_OUTPUT_HDMI:
79e53945 4728 is_sdvo = true;
5eddb70b 4729 if (encoder->needs_tv_clock)
e2f0ba97 4730 is_tv = true;
79e53945 4731 break;
79e53945
JB		 4732 case INTEL_OUTPUT_TVOUT:
4733 is_tv = true;
4734 break;
a4fc5ed6
KP		 4735 case INTEL_OUTPUT_DISPLAYPORT:
4736 is_dp = true;
4737 break;
79e53945 4738 }
43565a06 4739
c751ce4f 4740 num_connectors++;
79e53945
JB		 4741 }
4742
c65d77d8 4743 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4744
d4906093
ML		 4745 /*
4746 * Returns a set of divisors for the desired target clock with the given
4747 * refclk, or FALSE. The returned values represent the clock equation:
4748 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4749 */
1b894b59 4750 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4751 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4752 &clock);
79e53945
JB		 4753 if (!ok) {
4754 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4755 return -EINVAL;
79e53945
JB		 4756 }
4757
cda4b7d3 4758 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4759 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4760
ddc9003c 4761 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4762 /*
4763 * Ensure we match the reduced clock's P to the target clock.
4764 * If the clocks don't match, we can't switch the display clock
4765 * by using the FP0/FP1. In such case we will disable the LVDS
4766 * downclock feature.
4767 */
ddc9003c 4768 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4769 dev_priv->lvds_downclock,
4770 refclk,
cec2f356 4771 &clock,
5eddb70b 4772 &reduced_clock);
7026d4ac
ZW		 4773 }
4774
c65d77d8
JB		 4775 if (is_sdvo && is_tv)
4776 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 4777
eb1cbe48 4778 if (IS_GEN2(dev))
2a8f64ca
VP		 4779 i8xx_update_pll(crtc, adjusted_mode, &clock,
4780 has_reduced_clock ? &reduced_clock : NULL,
4781 num_connectors);
a0c4da24 4782 else if (IS_VALLEYVIEW(dev))
2a8f64ca
VP		 4783 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4784 has_reduced_clock ? &reduced_clock : NULL,
4785 num_connectors);
79e53945 4786 else
eb1cbe48
DV		 4787 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4788 has_reduced_clock ? &reduced_clock : NULL,
4789 num_connectors);
79e53945
JB		 4790
4791 /* setup pipeconf */
5eddb70b 4792 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4793
4794 /* Set up the display plane register */
4795 dspcntr = DISPPLANE_GAMMA_ENABLE;
4796
929c77fb
EA		 4797 if (pipe == 0)
4798 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4799 else
4800 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4801
a6c45cf0 4802 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4803 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4804 * core speed.
4805 *
4806 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4807 * pipe == 0 check?
4808 */
e70236a8
JB		 4809 if (mode->clock >
4810 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4811 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4812 else
5eddb70b 4813 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4814 }
4815
3b5c78a3
AJ		 4816 /* default to 8bpc */
4817 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4818 if (is_dp) {
0c96c65b 4819 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3b5c78a3
AJ		 4820 pipeconf |= PIPECONF_BPP_6 |
4821 PIPECONF_DITHER_EN |
4822 PIPECONF_DITHER_TYPE_SP;
4823 }
4824 }
4825
19c03924
GB		 4826 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4827 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4828 pipeconf |= PIPECONF_BPP_6 |
4829 PIPECONF_ENABLE |
4830 I965_PIPECONF_ACTIVE;
4831 }
4832 }
4833
28c97730 4834 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4835 drm_mode_debug_printmodeline(mode);
4836
a7516a05
JB		 4837 if (HAS_PIPE_CXSR(dev)) {
4838 if (intel_crtc->lowfreq_avail) {
28c97730 4839 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 4840 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 4841 } else {
28c97730 4842 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4843 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4844 }
4845 }
4846
617cf884 4847 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575 4848 if (!IS_GEN2(dev) &&
b0e77b9c 4849 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
734b4157 4850 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
b0e77b9c 4851 else
617cf884 4852 pipeconf |= PIPECONF_PROGRESSIVE;
734b4157 4853
b0e77b9c 4854 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4855
4856 /* pipesrc and dspsize control the size that is scaled from,
4857 * which should always be the user's requested size.
79e53945 4858 */
929c77fb
EA		 4859 I915_WRITE(DSPSIZE(plane),
4860 ((mode->vdisplay - 1) << 16) |
4861 (mode->hdisplay - 1));
4862 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4863
f564048e
EA		 4864 I915_WRITE(PIPECONF(pipe), pipeconf);
4865 POSTING_READ(PIPECONF(pipe));
929c77fb 4866 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4867
4868 intel_wait_for_vblank(dev, pipe);
4869
f564048e
EA		 4870 I915_WRITE(DSPCNTR(plane), dspcntr);
4871 POSTING_READ(DSPCNTR(plane));
4872
94352cf9 4873 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4874
4875 intel_update_watermarks(dev);
4876
f564048e
EA		 4877 return ret;
4878}
4879
9fb526db
KP		 4880/*
4881 * Initialize reference clocks when the driver loads
4882 */
4883void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4884{
4885 struct drm_i915_private *dev_priv = dev->dev_private;
4886 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4887 struct intel_encoder *encoder;
13d83a67
JB		 4888 u32 temp;
4889 bool has_lvds = false;
199e5d79
KP		 4890 bool has_cpu_edp = false;
4891 bool has_pch_edp = false;
4892 bool has_panel = false;
99eb6a01
KP		 4893 bool has_ck505 = false;
4894 bool can_ssc = false;
13d83a67
JB		 4895
4896 /* We need to take the global config into account */
199e5d79
KP		 4897 list_for_each_entry(encoder, &mode_config->encoder_list,
4898 base.head) {
4899 switch (encoder->type) {
4900 case INTEL_OUTPUT_LVDS:
4901 has_panel = true;
4902 has_lvds = true;
4903 break;
4904 case INTEL_OUTPUT_EDP:
4905 has_panel = true;
4906 if (intel_encoder_is_pch_edp(&encoder->base))
4907 has_pch_edp = true;
4908 else
4909 has_cpu_edp = true;
4910 break;
13d83a67
JB		 4911 }
4912 }
4913
99eb6a01
KP		 4914 if (HAS_PCH_IBX(dev)) {
4915 has_ck505 = dev_priv->display_clock_mode;
4916 can_ssc = has_ck505;
4917 } else {
4918 has_ck505 = false;
4919 can_ssc = true;
4920 }
4921
4922 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4923 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4924 has_ck505);
13d83a67
JB		 4925
4926 /* Ironlake: try to setup display ref clock before DPLL
4927 * enabling. This is only under driver's control after
4928 * PCH B stepping, previous chipset stepping should be
4929 * ignoring this setting.
4930 */
4931 temp = I915_READ(PCH_DREF_CONTROL);
4932 /* Always enable nonspread source */
4933 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4934
99eb6a01
KP		 4935 if (has_ck505)
4936 temp |= DREF_NONSPREAD_CK505_ENABLE;
4937 else
4938 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4939
199e5d79
KP		 4940 if (has_panel) {
4941 temp &= ~DREF_SSC_SOURCE_MASK;
4942 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4943
199e5d79 4944 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4945 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4946 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4947 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4948 } else
4949 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4950
4951 /* Get SSC going before enabling the outputs */
4952 I915_WRITE(PCH_DREF_CONTROL, temp);
4953 POSTING_READ(PCH_DREF_CONTROL);
4954 udelay(200);
4955
13d83a67
JB		 4956 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4957
4958 /* Enable CPU source on CPU attached eDP */
199e5d79 4959 if (has_cpu_edp) {
99eb6a01 4960 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4961 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4962 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4963 }
13d83a67
JB		 4964 else
4965 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4966 } else
4967 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4968
4969 I915_WRITE(PCH_DREF_CONTROL, temp);
4970 POSTING_READ(PCH_DREF_CONTROL);
4971 udelay(200);
4972 } else {
4973 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4974
4975 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4976
4977 /* Turn off CPU output */
4978 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4979
4980 I915_WRITE(PCH_DREF_CONTROL, temp);
4981 POSTING_READ(PCH_DREF_CONTROL);
4982 udelay(200);
4983
4984 /* Turn off the SSC source */
4985 temp &= ~DREF_SSC_SOURCE_MASK;
4986 temp |= DREF_SSC_SOURCE_DISABLE;
4987
4988 /* Turn off SSC1 */
4989 temp &= ~ DREF_SSC1_ENABLE;
4990
13d83a67
JB		 4991 I915_WRITE(PCH_DREF_CONTROL, temp);
4992 POSTING_READ(PCH_DREF_CONTROL);
4993 udelay(200);
4994 }
4995}
4996
d9d444cb
JB		 4997static int ironlake_get_refclk(struct drm_crtc *crtc)
4998{
4999 struct drm_device *dev = crtc->dev;
5000 struct drm_i915_private *dev_priv = dev->dev_private;
5001 struct intel_encoder *encoder;
d9d444cb
JB		 5002 struct intel_encoder *edp_encoder = NULL;
5003 int num_connectors = 0;
5004 bool is_lvds = false;
5005
6c2b7c12 5006 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5007 switch (encoder->type) {
5008 case INTEL_OUTPUT_LVDS:
5009 is_lvds = true;
5010 break;
5011 case INTEL_OUTPUT_EDP:
5012 edp_encoder = encoder;
5013 break;
5014 }
5015 num_connectors++;
5016 }
5017
5018 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5019 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5020 dev_priv->lvds_ssc_freq);
5021 return dev_priv->lvds_ssc_freq * 1000;
5022 }
5023
5024 return 120000;
5025}
5026
c8203565 5027static void ironlake_set_pipeconf(struct drm_crtc *crtc,
f564048e 5028 struct drm_display_mode *adjusted_mode,
c8203565 5029 bool dither)
79e53945 5030{
c8203565 5031 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5032 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5033 int pipe = intel_crtc->pipe;
c8203565
PZ		 5034 uint32_t val;
5035
5036 val = I915_READ(PIPECONF(pipe));
5037
5038 val &= ~PIPE_BPC_MASK;
5039 switch (intel_crtc->bpp) {
5040 case 18:
5041 val |= PIPE_6BPC;
5042 break;
5043 case 24:
5044 val |= PIPE_8BPC;
5045 break;
5046 case 30:
5047 val |= PIPE_10BPC;
5048 break;
5049 case 36:
5050 val |= PIPE_12BPC;
5051 break;
5052 default:
cc769b62
PZ		 5053 /* Case prevented by intel_choose_pipe_bpp_dither. */
5054 BUG();
c8203565
PZ		 5055 }
5056
5057 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5058 if (dither)
5059 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5060
5061 val &= ~PIPECONF_INTERLACE_MASK;
5062 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5063 val |= PIPECONF_INTERLACED_ILK;
5064 else
5065 val |= PIPECONF_PROGRESSIVE;
5066
5067 I915_WRITE(PIPECONF(pipe), val);
5068 POSTING_READ(PIPECONF(pipe));
5069}
5070
ee2b0b38
PZ		 5071static void haswell_set_pipeconf(struct drm_crtc *crtc,
5072 struct drm_display_mode *adjusted_mode,
5073 bool dither)
5074{
5075 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5076 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
702e7a56 5077 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
ee2b0b38
PZ		 5078 uint32_t val;
5079
702e7a56 5080 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5081
5082 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5083 if (dither)
5084 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5085
5086 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5087 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5088 val |= PIPECONF_INTERLACED_ILK;
5089 else
5090 val |= PIPECONF_PROGRESSIVE;
5091
702e7a56
PZ		 5092 I915_WRITE(PIPECONF(cpu_transcoder), val);
5093 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5094}
5095
6591c6e4
PZ		 5096static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5097 struct drm_display_mode *adjusted_mode,
5098 intel_clock_t *clock,
5099 bool *has_reduced_clock,
5100 intel_clock_t *reduced_clock)
5101{
5102 struct drm_device *dev = crtc->dev;
5103 struct drm_i915_private *dev_priv = dev->dev_private;
5104 struct intel_encoder *intel_encoder;
5105 int refclk;
d4906093 5106 const intel_limit_t *limit;
6591c6e4 5107 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
79e53945 5108
6591c6e4
PZ		 5109 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5110 switch (intel_encoder->type) {
79e53945
JB		 5111 case INTEL_OUTPUT_LVDS:
5112 is_lvds = true;
5113 break;
5114 case INTEL_OUTPUT_SDVO:
7d57382e 5115 case INTEL_OUTPUT_HDMI:
79e53945 5116 is_sdvo = true;
6591c6e4 5117 if (intel_encoder->needs_tv_clock)
e2f0ba97 5118 is_tv = true;
79e53945 5119 break;
79e53945
JB		 5120 case INTEL_OUTPUT_TVOUT:
5121 is_tv = true;
5122 break;
79e53945
JB		 5123 }
5124 }
5125
d9d444cb 5126 refclk = ironlake_get_refclk(crtc);
79e53945 5127
d4906093
ML		 5128 /*
5129 * Returns a set of divisors for the desired target clock with the given
5130 * refclk, or FALSE. The returned values represent the clock equation:
5131 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5132 */
1b894b59 5133 limit = intel_limit(crtc, refclk);
6591c6e4
PZ		 5134 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5135 clock);
5136 if (!ret)
5137 return false;
cda4b7d3 5138
ddc9003c 5139 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5140 /*
5141 * Ensure we match the reduced clock's P to the target clock.
5142 * If the clocks don't match, we can't switch the display clock
5143 * by using the FP0/FP1. In such case we will disable the LVDS
5144 * downclock feature.
5145 */
6591c6e4
PZ		 5146 *has_reduced_clock = limit->find_pll(limit, crtc,
5147 dev_priv->lvds_downclock,
5148 refclk,
5149 clock,
5150 reduced_clock);
652c393a 5151 }
61e9653f
DV		 5152
5153 if (is_sdvo && is_tv)
6591c6e4
PZ		 5154 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5155
5156 return true;
5157}
5158
01a415fd
DV		 5159static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5160{
5161 struct drm_i915_private *dev_priv = dev->dev_private;
5162 uint32_t temp;
5163
5164 temp = I915_READ(SOUTH_CHICKEN1);
5165 if (temp & FDI_BC_BIFURCATION_SELECT)
5166 return;
5167
5168 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5169 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5170
5171 temp |= FDI_BC_BIFURCATION_SELECT;
5172 DRM_DEBUG_KMS("enabling fdi C rx\n");
5173 I915_WRITE(SOUTH_CHICKEN1, temp);
5174 POSTING_READ(SOUTH_CHICKEN1);
5175}
5176
5177static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5178{
5179 struct drm_device *dev = intel_crtc->base.dev;
5180 struct drm_i915_private *dev_priv = dev->dev_private;
5181 struct intel_crtc *pipe_B_crtc =
5182 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5183
5184 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5185 intel_crtc->pipe, intel_crtc->fdi_lanes);
5186 if (intel_crtc->fdi_lanes > 4) {
5187 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5188 intel_crtc->pipe, intel_crtc->fdi_lanes);
5189 /* Clamp lanes to avoid programming the hw with bogus values. */
5190 intel_crtc->fdi_lanes = 4;
5191
5192 return false;
5193 }
5194
5195 if (dev_priv->num_pipe == 2)
5196 return true;
5197
5198 switch (intel_crtc->pipe) {
5199 case PIPE_A:
5200 return true;
5201 case PIPE_B:
5202 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5203 intel_crtc->fdi_lanes > 2) {
5204 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5205 intel_crtc->pipe, intel_crtc->fdi_lanes);
5206 /* Clamp lanes to avoid programming the hw with bogus values. */
5207 intel_crtc->fdi_lanes = 2;
5208
5209 return false;
5210 }
5211
5212 if (intel_crtc->fdi_lanes > 2)
5213 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5214 else
5215 cpt_enable_fdi_bc_bifurcation(dev);
5216
5217 return true;
5218 case PIPE_C:
5219 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5220 if (intel_crtc->fdi_lanes > 2) {
5221 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5222 intel_crtc->pipe, intel_crtc->fdi_lanes);
5223 /* Clamp lanes to avoid programming the hw with bogus values. */
5224 intel_crtc->fdi_lanes = 2;
5225
5226 return false;
5227 }
5228 } else {
5229 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5230 return false;
5231 }
5232
5233 cpt_enable_fdi_bc_bifurcation(dev);
5234
5235 return true;
5236 default:
5237 BUG();
5238 }
5239}
5240
f48d8f23
PZ		 5241static void ironlake_set_m_n(struct drm_crtc *crtc,
5242 struct drm_display_mode *mode,
5243 struct drm_display_mode *adjusted_mode)
79e53945
JB		 5244{
5245 struct drm_device *dev = crtc->dev;
5246 struct drm_i915_private *dev_priv = dev->dev_private;
5247 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
afe2fcf5 5248 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
f48d8f23 5249 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
2c07245f 5250 struct fdi_m_n m_n = {0};
f48d8f23
PZ		 5251 int target_clock, pixel_multiplier, lane, link_bw;
5252 bool is_dp = false, is_cpu_edp = false;
79e53945 5253
f48d8f23
PZ		 5254 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5255 switch (intel_encoder->type) {
a4fc5ed6
KP		 5256 case INTEL_OUTPUT_DISPLAYPORT:
5257 is_dp = true;
5258 break;
32f9d658 5259 case INTEL_OUTPUT_EDP:
e3aef172 5260 is_dp = true;
f48d8f23 5261 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5262 is_cpu_edp = true;
f48d8f23 5263 edp_encoder = intel_encoder;
32f9d658 5264 break;
79e53945 5265 }
79e53945 5266 }
61e9653f 5267
2c07245f 5268 /* FDI link */
8febb297
EA		 5269 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5270 lane = 0;
5271 /* CPU eDP doesn't require FDI link, so just set DP M/N
5272 according to current link config */
e3aef172 5273 if (is_cpu_edp) {
e3aef172 5274 intel_edp_link_config(edp_encoder, &lane, &link_bw);
8febb297 5275 } else {
8febb297
EA		 5276 /* FDI is a binary signal running at ~2.7GHz, encoding
5277 * each output octet as 10 bits. The actual frequency
5278 * is stored as a divider into a 100MHz clock, and the
5279 * mode pixel clock is stored in units of 1KHz.
5280 * Hence the bw of each lane in terms of the mode signal
5281 * is:
5282 */
5283 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5284 }
58a27471 5285
94bf2ced
DV		 5286 /* [e]DP over FDI requires target mode clock instead of link clock. */
5287 if (edp_encoder)
5288 target_clock = intel_edp_target_clock(edp_encoder, mode);
5289 else if (is_dp)
5290 target_clock = mode->clock;
5291 else
5292 target_clock = adjusted_mode->clock;
5293
8febb297
EA		 5294 if (!lane) {
5295 /*
5296 * Account for spread spectrum to avoid
5297 * oversubscribing the link. Max center spread
5298 * is 2.5%; use 5% for safety's sake.
5299 */
5a354204 5300 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
8febb297 5301 lane = bps / (link_bw * 8) + 1;
5eb08b69 5302 }
2c07245f 5303
8febb297
EA		 5304 intel_crtc->fdi_lanes = lane;
5305
5306 if (pixel_multiplier > 1)
5307 link_bw *= pixel_multiplier;
5a354204
JB		 5308 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5309 &m_n);
8febb297 5310
afe2fcf5
PZ		 5311 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5312 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5313 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5314 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
f48d8f23
PZ		 5315}
5316
de13a2e3
PZ		 5317static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5318 struct drm_display_mode *adjusted_mode,
5319 intel_clock_t *clock, u32 fp)
79e53945 5320{
de13a2e3 5321 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5322 struct drm_device *dev = crtc->dev;
5323 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5324 struct intel_encoder *intel_encoder;
5325 uint32_t dpll;
5326 int factor, pixel_multiplier, num_connectors = 0;
5327 bool is_lvds = false, is_sdvo = false, is_tv = false;
5328 bool is_dp = false, is_cpu_edp = false;
79e53945 5329
de13a2e3
PZ		 5330 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5331 switch (intel_encoder->type) {
79e53945
JB		 5332 case INTEL_OUTPUT_LVDS:
5333 is_lvds = true;
5334 break;
5335 case INTEL_OUTPUT_SDVO:
7d57382e 5336 case INTEL_OUTPUT_HDMI:
79e53945 5337 is_sdvo = true;
de13a2e3 5338 if (intel_encoder->needs_tv_clock)
e2f0ba97 5339 is_tv = true;
79e53945 5340 break;
79e53945
JB		 5341 case INTEL_OUTPUT_TVOUT:
5342 is_tv = true;
5343 break;
a4fc5ed6
KP		 5344 case INTEL_OUTPUT_DISPLAYPORT:
5345 is_dp = true;
5346 break;
32f9d658 5347 case INTEL_OUTPUT_EDP:
e3aef172 5348 is_dp = true;
de13a2e3 5349 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5350 is_cpu_edp = true;
32f9d658 5351 break;
79e53945 5352 }
43565a06 5353
c751ce4f 5354 num_connectors++;
79e53945 5355 }
79e53945 5356
c1858123 5357 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5358 factor = 21;
5359 if (is_lvds) {
5360 if ((intel_panel_use_ssc(dev_priv) &&
5361 dev_priv->lvds_ssc_freq == 100) ||
5362 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5363 factor = 25;
5364 } else if (is_sdvo && is_tv)
5365 factor = 20;
c1858123 5366
de13a2e3 5367 if (clock->m < factor * clock->n)
8febb297 5368 fp |= FP_CB_TUNE;
2c07245f 5369
5eddb70b 5370 dpll = 0;
2c07245f 5371
a07d6787
EA		 5372 if (is_lvds)
5373 dpll |= DPLLB_MODE_LVDS;
5374 else
5375 dpll |= DPLLB_MODE_DAC_SERIAL;
5376 if (is_sdvo) {
de13a2e3 5377 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
a07d6787
EA		 5378 if (pixel_multiplier > 1) {
5379 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5380 }
a07d6787
EA		 5381 dpll |= DPLL_DVO_HIGH_SPEED;
5382 }
e3aef172 5383 if (is_dp && !is_cpu_edp)
a07d6787 5384 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5385
a07d6787 5386 /* compute bitmask from p1 value */
de13a2e3 5387 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5388 /* also FPA1 */
de13a2e3 5389 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5390
de13a2e3 5391 switch (clock->p2) {
a07d6787
EA		 5392 case 5:
5393 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5394 break;
5395 case 7:
5396 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5397 break;
5398 case 10:
5399 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5400 break;
5401 case 14:
5402 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5403 break;
79e53945
JB		 5404 }
5405
43565a06
KH		 5406 if (is_sdvo && is_tv)
5407 dpll |= PLL_REF_INPUT_TVCLKINBC;
5408 else if (is_tv)
79e53945 5409 /* XXX: just matching BIOS for now */
43565a06 5410 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5411 dpll |= 3;
a7615030 5412 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5413 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5414 else
5415 dpll |= PLL_REF_INPUT_DREFCLK;
5416
de13a2e3
PZ		 5417 return dpll;
5418}
5419
5420static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5421 struct drm_display_mode *mode,
5422 struct drm_display_mode *adjusted_mode,
5423 int x, int y,
5424 struct drm_framebuffer *fb)
5425{
5426 struct drm_device *dev = crtc->dev;
5427 struct drm_i915_private *dev_priv = dev->dev_private;
5428 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5429 int pipe = intel_crtc->pipe;
5430 int plane = intel_crtc->plane;
5431 int num_connectors = 0;
5432 intel_clock_t clock, reduced_clock;
5433 u32 dpll, fp = 0, fp2 = 0;
e2f12b07
PZ		 5434 bool ok, has_reduced_clock = false;
5435 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
de13a2e3
PZ		 5436 struct intel_encoder *encoder;
5437 u32 temp;
5438 int ret;
01a415fd 5439 bool dither, fdi_config_ok;
de13a2e3
PZ		 5440
5441 for_each_encoder_on_crtc(dev, crtc, encoder) {
5442 switch (encoder->type) {
5443 case INTEL_OUTPUT_LVDS:
5444 is_lvds = true;
5445 break;
de13a2e3
PZ		 5446 case INTEL_OUTPUT_DISPLAYPORT:
5447 is_dp = true;
5448 break;
5449 case INTEL_OUTPUT_EDP:
5450 is_dp = true;
e2f12b07 5451 if (!intel_encoder_is_pch_edp(&encoder->base))
de13a2e3
PZ		 5452 is_cpu_edp = true;
5453 break;
5454 }
5455
5456 num_connectors++;
a07d6787 5457 }
79e53945 5458
5dc5298b
PZ		 5459 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5460 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5461
de13a2e3
PZ		 5462 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5463 &has_reduced_clock, &reduced_clock);
5464 if (!ok) {
5465 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5466 return -EINVAL;
79e53945
JB		 5467 }
5468
de13a2e3
PZ		 5469 /* Ensure that the cursor is valid for the new mode before changing... */
5470 intel_crtc_update_cursor(crtc, true);
5471
5472 /* determine panel color depth */
c8241969
JN		 5473 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5474 adjusted_mode);
de13a2e3
PZ		 5475 if (is_lvds && dev_priv->lvds_dither)
5476 dither = true;
5477
5478 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5479 if (has_reduced_clock)
5480 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5481 reduced_clock.m2;
5482
5483 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
79e53945 5484
f7cb34d4 5485 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5486 drm_mode_debug_printmodeline(mode);
5487
5dc5298b
PZ		 5488 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5489 if (!is_cpu_edp) {
ee7b9f93 5490 struct intel_pch_pll *pll;
4b645f14 5491
ee7b9f93
JB		 5492 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5493 if (pll == NULL) {
5494 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5495 pipe);
4b645f14
JB		 5496 return -EINVAL;
5497 }
ee7b9f93
JB		 5498 } else
5499 intel_put_pch_pll(intel_crtc);
79e53945
JB		 5500
5501 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5502 * This is an exception to the general rule that mode_set doesn't turn
5503 * things on.
5504 */
5505 if (is_lvds) {
fae14981 5506 temp = I915_READ(PCH_LVDS);
5eddb70b 5507 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
7885d205
JB		 5508 if (HAS_PCH_CPT(dev)) {
5509 temp &= ~PORT_TRANS_SEL_MASK;
4b645f14 5510 temp |= PORT_TRANS_SEL_CPT(pipe);
7885d205
JB		 5511 } else {
5512 if (pipe == 1)
5513 temp |= LVDS_PIPEB_SELECT;
5514 else
5515 temp &= ~LVDS_PIPEB_SELECT;
5516 }
4b645f14 5517
a3e17eb8 5518 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5519 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5520 /* Set the B0-B3 data pairs corresponding to whether we're going to
5521 * set the DPLLs for dual-channel mode or not.
5522 */
5523 if (clock.p2 == 7)
5eddb70b 5524 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5525 else
5eddb70b 5526 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5527
5528 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5529 * appropriately here, but we need to look more thoroughly into how
5530 * panels behave in the two modes.
5531 */
284d5df5 5532 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
aa9b500d 5533 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 5534 temp |= LVDS_HSYNC_POLARITY;
aa9b500d 5535 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 5536 temp |= LVDS_VSYNC_POLARITY;
fae14981 5537 I915_WRITE(PCH_LVDS, temp);
79e53945 5538 }
434ed097 5539
e3aef172 5540 if (is_dp && !is_cpu_edp) {
a4fc5ed6 5541 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 5542 } else {
8db9d77b 5543 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 5544 I915_WRITE(TRANSDATA_M1(pipe), 0);
5545 I915_WRITE(TRANSDATA_N1(pipe), 0);
5546 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5547 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 5548 }
79e53945 5549
dafd226c
DV		 5550 for_each_encoder_on_crtc(dev, crtc, encoder)
5551 if (encoder->pre_pll_enable)
5552 encoder->pre_pll_enable(encoder);
5553
ee7b9f93
JB		 5554 if (intel_crtc->pch_pll) {
5555 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5556
32f9d658 5557 /* Wait for the clocks to stabilize. */
ee7b9f93 5558 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5559 udelay(150);
5560
8febb297
EA		 5561 /* The pixel multiplier can only be updated once the
5562 * DPLL is enabled and the clocks are stable.
5563 *
5564 * So write it again.
5565 */
ee7b9f93 5566 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5567 }
79e53945 5568
5eddb70b 5569 intel_crtc->lowfreq_avail = false;
ee7b9f93 5570 if (intel_crtc->pch_pll) {
4b645f14 5571 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5572 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5573 intel_crtc->lowfreq_avail = true;
4b645f14 5574 } else {
ee7b9f93 5575 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5576 }
5577 }
5578
b0e77b9c 5579 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b 5580
01a415fd
DV		 5581 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5582 * ironlake_check_fdi_lanes. */
f48d8f23 5583 ironlake_set_m_n(crtc, mode, adjusted_mode);
2c07245f 5584
01a415fd 5585 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
2c07245f 5586
e3aef172 5587 if (is_cpu_edp)
8febb297 5588 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f 5589
c8203565 5590 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
79e53945 5591
9d0498a2 5592 intel_wait_for_vblank(dev, pipe);
79e53945 5593
a1f9e77e
PZ		 5594 /* Set up the display plane register */
5595 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5596 POSTING_READ(DSPCNTR(plane));
79e53945 5597
94352cf9 5598 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5599
5600 intel_update_watermarks(dev);
5601
1f8eeabf
ED		 5602 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5603
01a415fd 5604 return fdi_config_ok ? ret : -EINVAL;
79e53945
JB		 5605}
5606
09b4ddf9
PZ		 5607static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5608 struct drm_display_mode *mode,
5609 struct drm_display_mode *adjusted_mode,
5610 int x, int y,
5611 struct drm_framebuffer *fb)
5612{
5613 struct drm_device *dev = crtc->dev;
5614 struct drm_i915_private *dev_priv = dev->dev_private;
5615 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5616 int pipe = intel_crtc->pipe;
5617 int plane = intel_crtc->plane;
5618 int num_connectors = 0;
5619 intel_clock_t clock, reduced_clock;
5dc5298b 5620 u32 dpll = 0, fp = 0, fp2 = 0;
09b4ddf9
PZ		 5621 bool ok, has_reduced_clock = false;
5622 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5623 struct intel_encoder *encoder;
5624 u32 temp;
5625 int ret;
5626 bool dither;
5627
5628 for_each_encoder_on_crtc(dev, crtc, encoder) {
5629 switch (encoder->type) {
5630 case INTEL_OUTPUT_LVDS:
5631 is_lvds = true;
5632 break;
5633 case INTEL_OUTPUT_DISPLAYPORT:
5634 is_dp = true;
5635 break;
5636 case INTEL_OUTPUT_EDP:
5637 is_dp = true;
5638 if (!intel_encoder_is_pch_edp(&encoder->base))
5639 is_cpu_edp = true;
5640 break;
5641 }
5642
5643 num_connectors++;
5644 }
5645
a5c961d1
PZ		 5646 if (is_cpu_edp)
5647 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5648 else
5649 intel_crtc->cpu_transcoder = pipe;
5650
5dc5298b
PZ		 5651 /* We are not sure yet this won't happen. */
5652 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5653 INTEL_PCH_TYPE(dev));
5654
5655 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5656 num_connectors, pipe_name(pipe));
5657
702e7a56 5658 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
1ce42920
PZ		 5659 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5660
5661 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5662
6441ab5f
PZ		 5663 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5664 return -EINVAL;
5665
5dc5298b
PZ		 5666 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5667 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5668 &has_reduced_clock,
5669 &reduced_clock);
5670 if (!ok) {
5671 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5672 return -EINVAL;
5673 }
09b4ddf9
PZ		 5674 }
5675
5676 /* Ensure that the cursor is valid for the new mode before changing... */
5677 intel_crtc_update_cursor(crtc, true);
5678
5679 /* determine panel color depth */
c8241969
JN		 5680 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5681 adjusted_mode);
09b4ddf9
PZ		 5682 if (is_lvds && dev_priv->lvds_dither)
5683 dither = true;
5684
09b4ddf9
PZ		 5685 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5686 drm_mode_debug_printmodeline(mode);
5687
5dc5298b
PZ		 5688 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5689 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5690 if (has_reduced_clock)
5691 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5692 reduced_clock.m2;
5693
5694 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5695 fp);
5696
5697 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5698 * own on pre-Haswell/LPT generation */
5699 if (!is_cpu_edp) {
5700 struct intel_pch_pll *pll;
5701
5702 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5703 if (pll == NULL) {
5704 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5705 pipe);
5706 return -EINVAL;
5707 }
5708 } else
5709 intel_put_pch_pll(intel_crtc);
09b4ddf9 5710
5dc5298b
PZ		 5711 /* The LVDS pin pair needs to be on before the DPLLs are
5712 * enabled. This is an exception to the general rule that
5713 * mode_set doesn't turn things on.
5714 */
5715 if (is_lvds) {
5716 temp = I915_READ(PCH_LVDS);
5717 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5718 if (HAS_PCH_CPT(dev)) {
5719 temp &= ~PORT_TRANS_SEL_MASK;
5720 temp |= PORT_TRANS_SEL_CPT(pipe);
5721 } else {
5722 if (pipe == 1)
5723 temp |= LVDS_PIPEB_SELECT;
5724 else
5725 temp &= ~LVDS_PIPEB_SELECT;
5726 }
09b4ddf9 5727
5dc5298b
PZ		 5728 /* set the corresponsding LVDS_BORDER bit */
5729 temp |= dev_priv->lvds_border_bits;
5730 /* Set the B0-B3 data pairs corresponding to whether
5731 * we're going to set the DPLLs for dual-channel mode or
5732 * not.
5733 */
5734 if (clock.p2 == 7)
5735 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
09b4ddf9 5736 else
5dc5298b
PZ		 5737 temp &= ~(LVDS_B0B3_POWER_UP |
5738 LVDS_CLKB_POWER_UP);
5739
5740 /* It would be nice to set 24 vs 18-bit mode
5741 * (LVDS_A3_POWER_UP) appropriately here, but we need to
5742 * look more thoroughly into how panels behave in the
5743 * two modes.
5744 */
5745 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5746 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5747 temp |= LVDS_HSYNC_POLARITY;
5748 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5749 temp |= LVDS_VSYNC_POLARITY;
5750 I915_WRITE(PCH_LVDS, temp);
09b4ddf9 5751 }
09b4ddf9
PZ		 5752 }
5753
5754 if (is_dp && !is_cpu_edp) {
5755 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5756 } else {
5dc5298b
PZ		 5757 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5758 /* For non-DP output, clear any trans DP clock recovery
5759 * setting.*/
5760 I915_WRITE(TRANSDATA_M1(pipe), 0);
5761 I915_WRITE(TRANSDATA_N1(pipe), 0);
5762 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5763 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5764 }
09b4ddf9
PZ		 5765 }
5766
5767 intel_crtc->lowfreq_avail = false;
5dc5298b
PZ		 5768 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5769 if (intel_crtc->pch_pll) {
5770 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5771
5772 /* Wait for the clocks to stabilize. */
5773 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5774 udelay(150);
5775
5776 /* The pixel multiplier can only be updated once the
5777 * DPLL is enabled and the clocks are stable.
5778 *
5779 * So write it again.
5780 */
5781 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5782 }
5783
5784 if (intel_crtc->pch_pll) {
5785 if (is_lvds && has_reduced_clock && i915_powersave) {
5786 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5787 intel_crtc->lowfreq_avail = true;
5788 } else {
5789 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5790 }
09b4ddf9
PZ		 5791 }
5792 }
5793
5794 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5795
1eb8dfec
PZ		 5796 if (!is_dp || is_cpu_edp)
5797 ironlake_set_m_n(crtc, mode, adjusted_mode);
09b4ddf9 5798
5dc5298b
PZ		 5799 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5800 if (is_cpu_edp)
5801 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
09b4ddf9 5802
ee2b0b38 5803 haswell_set_pipeconf(crtc, adjusted_mode, dither);
09b4ddf9 5804
09b4ddf9
PZ		 5805 /* Set up the display plane register */
5806 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5807 POSTING_READ(DSPCNTR(plane));
5808
5809 ret = intel_pipe_set_base(crtc, x, y, fb);
5810
5811 intel_update_watermarks(dev);
5812
5813 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5814
1f803ee5 5815 return ret;
79e53945
JB		 5816}
5817
f564048e
EA		 5818static int intel_crtc_mode_set(struct drm_crtc *crtc,
5819 struct drm_display_mode *mode,
5820 struct drm_display_mode *adjusted_mode,
5821 int x, int y,
94352cf9 5822 struct drm_framebuffer *fb)
f564048e
EA		 5823{
5824 struct drm_device *dev = crtc->dev;
5825 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 5826 struct drm_encoder_helper_funcs *encoder_funcs;
5827 struct intel_encoder *encoder;
0b701d27
EA		 5828 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5829 int pipe = intel_crtc->pipe;
f564048e
EA		 5830 int ret;
5831
0b701d27 5832 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5833
f564048e 5834 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
94352cf9 5835 x, y, fb);
79e53945 5836 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5837
9256aa19
DV		 5838 if (ret != 0)
5839 return ret;
5840
5841 for_each_encoder_on_crtc(dev, crtc, encoder) {
5842 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5843 encoder->base.base.id,
5844 drm_get_encoder_name(&encoder->base),
5845 mode->base.id, mode->name);
5846 encoder_funcs = encoder->base.helper_private;
5847 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5848 }
5849
5850 return 0;
79e53945
JB		 5851}
5852
3a9627f4
WF		 5853static bool intel_eld_uptodate(struct drm_connector *connector,
5854 int reg_eldv, uint32_t bits_eldv,
5855 int reg_elda, uint32_t bits_elda,
5856 int reg_edid)
5857{
5858 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5859 uint8_t *eld = connector->eld;
5860 uint32_t i;
5861
5862 i = I915_READ(reg_eldv);
5863 i &= bits_eldv;
5864
5865 if (!eld[0])
5866 return !i;
5867
5868 if (!i)
5869 return false;
5870
5871 i = I915_READ(reg_elda);
5872 i &= ~bits_elda;
5873 I915_WRITE(reg_elda, i);
5874
5875 for (i = 0; i < eld[2]; i++)
5876 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5877 return false;
5878
5879 return true;
5880}
5881
e0dac65e
WF		 5882static void g4x_write_eld(struct drm_connector *connector,
5883 struct drm_crtc *crtc)
5884{
5885 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5886 uint8_t *eld = connector->eld;
5887 uint32_t eldv;
5888 uint32_t len;
5889 uint32_t i;
5890
5891 i = I915_READ(G4X_AUD_VID_DID);
5892
5893 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5894 eldv = G4X_ELDV_DEVCL_DEVBLC;
5895 else
5896 eldv = G4X_ELDV_DEVCTG;
5897
3a9627f4
WF		 5898 if (intel_eld_uptodate(connector,
5899 G4X_AUD_CNTL_ST, eldv,
5900 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5901 G4X_HDMIW_HDMIEDID))
5902 return;
5903
e0dac65e
WF		 5904 i = I915_READ(G4X_AUD_CNTL_ST);
5905 i &= ~(eldv | G4X_ELD_ADDR);
5906 len = (i >> 9) & 0x1f; /* ELD buffer size */
5907 I915_WRITE(G4X_AUD_CNTL_ST, i);
5908
5909 if (!eld[0])
5910 return;
5911
5912 len = min_t(uint8_t, eld[2], len);
5913 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5914 for (i = 0; i < len; i++)
5915 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5916
5917 i = I915_READ(G4X_AUD_CNTL_ST);
5918 i |= eldv;
5919 I915_WRITE(G4X_AUD_CNTL_ST, i);
5920}
5921
83358c85
WX		 5922static void haswell_write_eld(struct drm_connector *connector,
5923 struct drm_crtc *crtc)
5924{
5925 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5926 uint8_t *eld = connector->eld;
5927 struct drm_device *dev = crtc->dev;
5928 uint32_t eldv;
5929 uint32_t i;
5930 int len;
5931 int pipe = to_intel_crtc(crtc)->pipe;
5932 int tmp;
5933
5934 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5935 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5936 int aud_config = HSW_AUD_CFG(pipe);
5937 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5938
5939
5940 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5941
5942 /* Audio output enable */
5943 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5944 tmp = I915_READ(aud_cntrl_st2);
5945 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5946 I915_WRITE(aud_cntrl_st2, tmp);
5947
5948 /* Wait for 1 vertical blank */
5949 intel_wait_for_vblank(dev, pipe);
5950
5951 /* Set ELD valid state */
5952 tmp = I915_READ(aud_cntrl_st2);
5953 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5954 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5955 I915_WRITE(aud_cntrl_st2, tmp);
5956 tmp = I915_READ(aud_cntrl_st2);
5957 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5958
5959 /* Enable HDMI mode */
5960 tmp = I915_READ(aud_config);
5961 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5962 /* clear N_programing_enable and N_value_index */
5963 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5964 I915_WRITE(aud_config, tmp);
5965
5966 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5967
5968 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5969
5970 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5971 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5972 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5973 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5974 } else
5975 I915_WRITE(aud_config, 0);
5976
5977 if (intel_eld_uptodate(connector,
5978 aud_cntrl_st2, eldv,
5979 aud_cntl_st, IBX_ELD_ADDRESS,
5980 hdmiw_hdmiedid))
5981 return;
5982
5983 i = I915_READ(aud_cntrl_st2);
5984 i &= ~eldv;
5985 I915_WRITE(aud_cntrl_st2, i);
5986
5987 if (!eld[0])
5988 return;
5989
5990 i = I915_READ(aud_cntl_st);
5991 i &= ~IBX_ELD_ADDRESS;
5992 I915_WRITE(aud_cntl_st, i);
5993 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5994 DRM_DEBUG_DRIVER("port num:%d\n", i);
5995
5996 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5997 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5998 for (i = 0; i < len; i++)
5999 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6000
6001 i = I915_READ(aud_cntrl_st2);
6002 i |= eldv;
6003 I915_WRITE(aud_cntrl_st2, i);
6004
6005}
6006
e0dac65e
WF		 6007static void ironlake_write_eld(struct drm_connector *connector,
6008 struct drm_crtc *crtc)
6009{
6010 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6011 uint8_t *eld = connector->eld;
6012 uint32_t eldv;
6013 uint32_t i;
6014 int len;
6015 int hdmiw_hdmiedid;
b6daa025 6016 int aud_config;
e0dac65e
WF		 6017 int aud_cntl_st;
6018 int aud_cntrl_st2;
9b138a83 6019 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6020
b3f33cbf 6021 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6022 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6023 aud_config = IBX_AUD_CFG(pipe);
6024 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6025 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6026 } else {
9b138a83
WX		 6027 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6028 aud_config = CPT_AUD_CFG(pipe);
6029 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6030 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6031 }
6032
9b138a83 6033 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6034
6035 i = I915_READ(aud_cntl_st);
9b138a83 6036 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6037 if (!i) {
6038 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6039 /* operate blindly on all ports */
1202b4c6
WF		 6040 eldv = IBX_ELD_VALIDB;
6041 eldv |= IBX_ELD_VALIDB << 4;
6042 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 6043 } else {
6044 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 6045 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6046 }
6047
3a9627f4
WF		 6048 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6049 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6050 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6051 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6052 } else
6053 I915_WRITE(aud_config, 0);
e0dac65e 6054
3a9627f4
WF		 6055 if (intel_eld_uptodate(connector,
6056 aud_cntrl_st2, eldv,
6057 aud_cntl_st, IBX_ELD_ADDRESS,
6058 hdmiw_hdmiedid))
6059 return;
6060
e0dac65e
WF		 6061 i = I915_READ(aud_cntrl_st2);
6062 i &= ~eldv;
6063 I915_WRITE(aud_cntrl_st2, i);
6064
6065 if (!eld[0])
6066 return;
6067
e0dac65e 6068 i = I915_READ(aud_cntl_st);
1202b4c6 6069 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6070 I915_WRITE(aud_cntl_st, i);
6071
6072 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6073 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6074 for (i = 0; i < len; i++)
6075 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6076
6077 i = I915_READ(aud_cntrl_st2);
6078 i |= eldv;
6079 I915_WRITE(aud_cntrl_st2, i);
6080}
6081
6082void intel_write_eld(struct drm_encoder *encoder,
6083 struct drm_display_mode *mode)
6084{
6085 struct drm_crtc *crtc = encoder->crtc;
6086 struct drm_connector *connector;
6087 struct drm_device *dev = encoder->dev;
6088 struct drm_i915_private *dev_priv = dev->dev_private;
6089
6090 connector = drm_select_eld(encoder, mode);
6091 if (!connector)
6092 return;
6093
6094 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6095 connector->base.id,
6096 drm_get_connector_name(connector),
6097 connector->encoder->base.id,
6098 drm_get_encoder_name(connector->encoder));
6099
6100 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6101
6102 if (dev_priv->display.write_eld)
6103 dev_priv->display.write_eld(connector, crtc);
6104}
6105
79e53945
JB		 6106/** Loads the palette/gamma unit for the CRTC with the prepared values */
6107void intel_crtc_load_lut(struct drm_crtc *crtc)
6108{
6109 struct drm_device *dev = crtc->dev;
6110 struct drm_i915_private *dev_priv = dev->dev_private;
6111 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6112 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6113 int i;
6114
6115 /* The clocks have to be on to load the palette. */
aed3f09d 6116 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6117 return;
6118
f2b115e6 6119 /* use legacy palette for Ironlake */
bad720ff 6120 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6121 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6122
79e53945
JB		 6123 for (i = 0; i < 256; i++) {
6124 I915_WRITE(palreg + 4 * i,
6125 (intel_crtc->lut_r[i] << 16) |
6126 (intel_crtc->lut_g[i] << 8) |
6127 intel_crtc->lut_b[i]);
6128 }
6129}
6130
560b85bb
CW		 6131static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6132{
6133 struct drm_device *dev = crtc->dev;
6134 struct drm_i915_private *dev_priv = dev->dev_private;
6135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6136 bool visible = base != 0;
6137 u32 cntl;
6138
6139 if (intel_crtc->cursor_visible == visible)
6140 return;
6141
9db4a9c7 6142 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6143 if (visible) {
6144 /* On these chipsets we can only modify the base whilst
6145 * the cursor is disabled.
6146 */
9db4a9c7 6147 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6148
6149 cntl &= ~(CURSOR_FORMAT_MASK);
6150 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6151 cntl |= CURSOR_ENABLE |
6152 CURSOR_GAMMA_ENABLE |
6153 CURSOR_FORMAT_ARGB;
6154 } else
6155 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6156 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6157
6158 intel_crtc->cursor_visible = visible;
6159}
6160
6161static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6162{
6163 struct drm_device *dev = crtc->dev;
6164 struct drm_i915_private *dev_priv = dev->dev_private;
6165 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6166 int pipe = intel_crtc->pipe;
6167 bool visible = base != 0;
6168
6169 if (intel_crtc->cursor_visible != visible) {
548f245b 6170 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6171 if (base) {
6172 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6173 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6174 cntl |= pipe << 28; /* Connect to correct pipe */
6175 } else {
6176 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6177 cntl |= CURSOR_MODE_DISABLE;
6178 }
9db4a9c7 6179 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6180
6181 intel_crtc->cursor_visible = visible;
6182 }
6183 /* and commit changes on next vblank */
9db4a9c7 6184 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6185}
6186
65a21cd6
JB		 6187static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6188{
6189 struct drm_device *dev = crtc->dev;
6190 struct drm_i915_private *dev_priv = dev->dev_private;
6191 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6192 int pipe = intel_crtc->pipe;
6193 bool visible = base != 0;
6194
6195 if (intel_crtc->cursor_visible != visible) {
6196 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6197 if (base) {
6198 cntl &= ~CURSOR_MODE;
6199 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6200 } else {
6201 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6202 cntl |= CURSOR_MODE_DISABLE;
6203 }
6204 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6205
6206 intel_crtc->cursor_visible = visible;
6207 }
6208 /* and commit changes on next vblank */
6209 I915_WRITE(CURBASE_IVB(pipe), base);
6210}
6211
cda4b7d3 6212/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6213static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6214 bool on)
cda4b7d3
CW		 6215{
6216 struct drm_device *dev = crtc->dev;
6217 struct drm_i915_private *dev_priv = dev->dev_private;
6218 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6219 int pipe = intel_crtc->pipe;
6220 int x = intel_crtc->cursor_x;
6221 int y = intel_crtc->cursor_y;
560b85bb 6222 u32 base, pos;
cda4b7d3
CW		 6223 bool visible;
6224
6225 pos = 0;
6226
6b383a7f 6227 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6228 base = intel_crtc->cursor_addr;
6229 if (x > (int) crtc->fb->width)
6230 base = 0;
6231
6232 if (y > (int) crtc->fb->height)
6233 base = 0;
6234 } else
6235 base = 0;
6236
6237 if (x < 0) {
6238 if (x + intel_crtc->cursor_width < 0)
6239 base = 0;
6240
6241 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6242 x = -x;
6243 }
6244 pos |= x << CURSOR_X_SHIFT;
6245
6246 if (y < 0) {
6247 if (y + intel_crtc->cursor_height < 0)
6248 base = 0;
6249
6250 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6251 y = -y;
6252 }
6253 pos |= y << CURSOR_Y_SHIFT;
6254
6255 visible = base != 0;
560b85bb 6256 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6257 return;
6258
0cd83aa9 6259 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6260 I915_WRITE(CURPOS_IVB(pipe), pos);
6261 ivb_update_cursor(crtc, base);
6262 } else {
6263 I915_WRITE(CURPOS(pipe), pos);
6264 if (IS_845G(dev) || IS_I865G(dev))
6265 i845_update_cursor(crtc, base);
6266 else
6267 i9xx_update_cursor(crtc, base);
6268 }
cda4b7d3
CW		 6269}
6270
79e53945 6271static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6272 struct drm_file *file,
79e53945
JB		 6273 uint32_t handle,
6274 uint32_t width, uint32_t height)
6275{
6276 struct drm_device *dev = crtc->dev;
6277 struct drm_i915_private *dev_priv = dev->dev_private;
6278 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6279 struct drm_i915_gem_object *obj;
cda4b7d3 6280 uint32_t addr;
3f8bc370 6281 int ret;
79e53945 6282
79e53945
JB		 6283 /* if we want to turn off the cursor ignore width and height */
6284 if (!handle) {
28c97730 6285 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6286 addr = 0;
05394f39 6287 obj = NULL;
5004417d 6288 mutex_lock(&dev->struct_mutex);
3f8bc370 6289 goto finish;
79e53945
JB		 6290 }
6291
6292 /* Currently we only support 64x64 cursors */
6293 if (width != 64 || height != 64) {
6294 DRM_ERROR("we currently only support 64x64 cursors\n");
6295 return -EINVAL;
6296 }
6297
05394f39 6298 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6299 if (&obj->base == NULL)
79e53945
JB		 6300 return -ENOENT;
6301
05394f39 6302 if (obj->base.size < width * height * 4) {
79e53945 6303 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6304 ret = -ENOMEM;
6305 goto fail;
79e53945
JB		 6306 }
6307
71acb5eb 6308 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6309 mutex_lock(&dev->struct_mutex);
b295d1b6 6310 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 6311 if (obj->tiling_mode) {
6312 DRM_ERROR("cursor cannot be tiled\n");
6313 ret = -EINVAL;
6314 goto fail_locked;
6315 }
6316
2da3b9b9 6317 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 6318 if (ret) {
6319 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6320 goto fail_locked;
e7b526bb
CW		 6321 }
6322
d9e86c0e
CW		 6323 ret = i915_gem_object_put_fence(obj);
6324 if (ret) {
2da3b9b9 6325 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6326 goto fail_unpin;
6327 }
6328
05394f39 6329 addr = obj->gtt_offset;
71acb5eb 6330 } else {
6eeefaf3 6331 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6332 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6333 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6334 align);
71acb5eb
DA		 6335 if (ret) {
6336 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6337 goto fail_locked;
71acb5eb 6338 }
05394f39 6339 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6340 }
6341
a6c45cf0 6342 if (IS_GEN2(dev))
14b60391
JB		 6343 I915_WRITE(CURSIZE, (height << 12) | width);
6344
3f8bc370 6345 finish:
3f8bc370 6346 if (intel_crtc->cursor_bo) {
b295d1b6 6347 if (dev_priv->info->cursor_needs_physical) {
05394f39 6348 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6349 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6350 } else
6351 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6352 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6353 }
80824003 6354
7f9872e0 6355 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6356
6357 intel_crtc->cursor_addr = addr;
05394f39 6358 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6359 intel_crtc->cursor_width = width;
6360 intel_crtc->cursor_height = height;
6361
6b383a7f 6362 intel_crtc_update_cursor(crtc, true);
3f8bc370 6363
79e53945 6364 return 0;
e7b526bb 6365fail_unpin:
05394f39 6366 i915_gem_object_unpin(obj);
7f9872e0 6367fail_locked:
34b8686e 6368 mutex_unlock(&dev->struct_mutex);
bc9025bd 6369fail:
05394f39 6370 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6371 return ret;
79e53945
JB		 6372}
6373
6374static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6375{
79e53945 6376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6377
cda4b7d3
CW		 6378 intel_crtc->cursor_x = x;
6379 intel_crtc->cursor_y = y;
652c393a 6380
6b383a7f 6381 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6382
6383 return 0;
6384}
6385
6386/** Sets the color ramps on behalf of RandR */
6387void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6388 u16 blue, int regno)
6389{
6390 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6391
6392 intel_crtc->lut_r[regno] = red >> 8;
6393 intel_crtc->lut_g[regno] = green >> 8;
6394 intel_crtc->lut_b[regno] = blue >> 8;
6395}
6396
b8c00ac5
DA		 6397void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6398 u16 *blue, int regno)
6399{
6400 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6401
6402 *red = intel_crtc->lut_r[regno] << 8;
6403 *green = intel_crtc->lut_g[regno] << 8;
6404 *blue = intel_crtc->lut_b[regno] << 8;
6405}
6406
79e53945 6407static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6408 u16 *blue, uint32_t start, uint32_t size)
79e53945 6409{
7203425a 6410 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6411 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6412
7203425a 6413 for (i = start; i < end; i++) {
79e53945
JB		 6414 intel_crtc->lut_r[i] = red[i] >> 8;
6415 intel_crtc->lut_g[i] = green[i] >> 8;
6416 intel_crtc->lut_b[i] = blue[i] >> 8;
6417 }
6418
6419 intel_crtc_load_lut(crtc);
6420}
6421
6422/**
6423 * Get a pipe with a simple mode set on it for doing load-based monitor
6424 * detection.
6425 *
6426 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 6427 * its requirements. The pipe will be connected to no other encoders.
79e53945 6428 *
c751ce4f 6429 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 6430 * configured for it. In the future, it could choose to temporarily disable
6431 * some outputs to free up a pipe for its use.
6432 *
6433 * \return crtc, or NULL if no pipes are available.
6434 */
6435
6436/* VESA 640x480x72Hz mode to set on the pipe */
6437static struct drm_display_mode load_detect_mode = {
6438 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6439 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6440};
6441
d2dff872
CW		 6442static struct drm_framebuffer *
6443intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6444 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6445 struct drm_i915_gem_object *obj)
6446{
6447 struct intel_framebuffer *intel_fb;
6448 int ret;
6449
6450 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6451 if (!intel_fb) {
6452 drm_gem_object_unreference_unlocked(&obj->base);
6453 return ERR_PTR(-ENOMEM);
6454 }
6455
6456 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6457 if (ret) {
6458 drm_gem_object_unreference_unlocked(&obj->base);
6459 kfree(intel_fb);
6460 return ERR_PTR(ret);
6461 }
6462
6463 return &intel_fb->base;
6464}
6465
6466static u32
6467intel_framebuffer_pitch_for_width(int width, int bpp)
6468{
6469 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6470 return ALIGN(pitch, 64);
6471}
6472
6473static u32
6474intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6475{
6476 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6477 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6478}
6479
6480static struct drm_framebuffer *
6481intel_framebuffer_create_for_mode(struct drm_device *dev,
6482 struct drm_display_mode *mode,
6483 int depth, int bpp)
6484{
6485 struct drm_i915_gem_object *obj;
0fed39bd 6486 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6487
6488 obj = i915_gem_alloc_object(dev,
6489 intel_framebuffer_size_for_mode(mode, bpp));
6490 if (obj == NULL)
6491 return ERR_PTR(-ENOMEM);
6492
6493 mode_cmd.width = mode->hdisplay;
6494 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6495 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6496 bpp);
5ca0c34a 6497 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6498
6499 return intel_framebuffer_create(dev, &mode_cmd, obj);
6500}
6501
6502static struct drm_framebuffer *
6503mode_fits_in_fbdev(struct drm_device *dev,
6504 struct drm_display_mode *mode)
6505{
6506 struct drm_i915_private *dev_priv = dev->dev_private;
6507 struct drm_i915_gem_object *obj;
6508 struct drm_framebuffer *fb;
6509
6510 if (dev_priv->fbdev == NULL)
6511 return NULL;
6512
6513 obj = dev_priv->fbdev->ifb.obj;
6514 if (obj == NULL)
6515 return NULL;
6516
6517 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6518 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6519 fb->bits_per_pixel))
d2dff872
CW		 6520 return NULL;
6521
01f2c773 6522 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6523 return NULL;
6524
6525 return fb;
6526}
6527
d2434ab7 6528bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6529 struct drm_display_mode *mode,
8261b191 6530 struct intel_load_detect_pipe *old)
79e53945
JB		 6531{
6532 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6533 struct intel_encoder *intel_encoder =
6534 intel_attached_encoder(connector);
79e53945 6535 struct drm_crtc *possible_crtc;
4ef69c7a 6536 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6537 struct drm_crtc *crtc = NULL;
6538 struct drm_device *dev = encoder->dev;
94352cf9 6539 struct drm_framebuffer *fb;
79e53945
JB		 6540 int i = -1;
6541
d2dff872
CW		 6542 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6543 connector->base.id, drm_get_connector_name(connector),
6544 encoder->base.id, drm_get_encoder_name(encoder));
6545
79e53945
JB		 6546 /*
6547 * Algorithm gets a little messy:
7a5e4805 6548 *
79e53945
JB		 6549 * - if the connector already has an assigned crtc, use it (but make
6550 * sure it's on first)
7a5e4805 6551 *
79e53945
JB		 6552 * - try to find the first unused crtc that can drive this connector,
6553 * and use that if we find one
79e53945
JB		 6554 */
6555
6556 /* See if we already have a CRTC for this connector */
6557 if (encoder->crtc) {
6558 crtc = encoder->crtc;
8261b191 6559
24218aac 6560 old->dpms_mode = connector->dpms;
8261b191
CW		 6561 old->load_detect_temp = false;
6562
6563 /* Make sure the crtc and connector are running */
24218aac
DV		 6564 if (connector->dpms != DRM_MODE_DPMS_ON)
6565 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6566
7173188d 6567 return true;
79e53945
JB		 6568 }
6569
6570 /* Find an unused one (if possible) */
6571 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6572 i++;
6573 if (!(encoder->possible_crtcs & (1 << i)))
6574 continue;
6575 if (!possible_crtc->enabled) {
6576 crtc = possible_crtc;
6577 break;
6578 }
79e53945
JB		 6579 }
6580
6581 /*
6582 * If we didn't find an unused CRTC, don't use any.
6583 */
6584 if (!crtc) {
7173188d
CW		 6585 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6586 return false;
79e53945
JB		 6587 }
6588
fc303101
DV		 6589 intel_encoder->new_crtc = to_intel_crtc(crtc);
6590 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6591
6592 intel_crtc = to_intel_crtc(crtc);
24218aac 6593 old->dpms_mode = connector->dpms;
8261b191 6594 old->load_detect_temp = true;
d2dff872 6595 old->release_fb = NULL;
79e53945 6596
6492711d
CW		 6597 if (!mode)
6598 mode = &load_detect_mode;
79e53945 6599
d2dff872
CW		 6600 /* We need a framebuffer large enough to accommodate all accesses
6601 * that the plane may generate whilst we perform load detection.
6602 * We can not rely on the fbcon either being present (we get called
6603 * during its initialisation to detect all boot displays, or it may
6604 * not even exist) or that it is large enough to satisfy the
6605 * requested mode.
6606 */
94352cf9
DV		 6607 fb = mode_fits_in_fbdev(dev, mode);
6608 if (fb == NULL) {
d2dff872 6609 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6610 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6611 old->release_fb = fb;
d2dff872
CW		 6612 } else
6613 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6614 if (IS_ERR(fb)) {
d2dff872 6615 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
0e8b3d3e 6616 return false;
79e53945 6617 }
79e53945 6618
94352cf9 6619 if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6620 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6621 if (old->release_fb)
6622 old->release_fb->funcs->destroy(old->release_fb);
0e8b3d3e 6623 return false;
79e53945 6624 }
7173188d 6625
79e53945 6626 /* let the connector get through one full cycle before testing */
9d0498a2 6627 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6628 return true;
79e53945
JB		 6629}
6630
d2434ab7 6631void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6632 struct intel_load_detect_pipe *old)
79e53945 6633{
d2434ab7
DV		 6634 struct intel_encoder *intel_encoder =
6635 intel_attached_encoder(connector);
4ef69c7a 6636 struct drm_encoder *encoder = &intel_encoder->base;
79e53945 6637
d2dff872
CW		 6638 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6639 connector->base.id, drm_get_connector_name(connector),
6640 encoder->base.id, drm_get_encoder_name(encoder));
6641
8261b191 6642 if (old->load_detect_temp) {
fc303101
DV		 6643 struct drm_crtc *crtc = encoder->crtc;
6644
6645 to_intel_connector(connector)->new_encoder = NULL;
6646 intel_encoder->new_crtc = NULL;
6647 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872
CW		 6648
6649 if (old->release_fb)
6650 old->release_fb->funcs->destroy(old->release_fb);
6651
0622a53c 6652 return;
79e53945
JB		 6653 }
6654
c751ce4f 6655 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6656 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6657 connector->funcs->dpms(connector, old->dpms_mode);
79e53945
JB		 6658}
6659
6660/* Returns the clock of the currently programmed mode of the given pipe. */
6661static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6662{
6663 struct drm_i915_private *dev_priv = dev->dev_private;
6664 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6665 int pipe = intel_crtc->pipe;
548f245b 6666 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6667 u32 fp;
6668 intel_clock_t clock;
6669
6670 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6671 fp = I915_READ(FP0(pipe));
79e53945 6672 else
39adb7a5 6673 fp = I915_READ(FP1(pipe));
79e53945
JB		 6674
6675 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6676 if (IS_PINEVIEW(dev)) {
6677 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6678 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6679 } else {
6680 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6681 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6682 }
6683
a6c45cf0 6684 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6685 if (IS_PINEVIEW(dev))
6686 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6687 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6688 else
6689 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6690 DPLL_FPA01_P1_POST_DIV_SHIFT);
6691
6692 switch (dpll & DPLL_MODE_MASK) {
6693 case DPLLB_MODE_DAC_SERIAL:
6694 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6695 5 : 10;
6696 break;
6697 case DPLLB_MODE_LVDS:
6698 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6699 7 : 14;
6700 break;
6701 default:
28c97730 6702 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6703 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6704 return 0;
6705 }
6706
6707 /* XXX: Handle the 100Mhz refclk */
2177832f 6708 intel_clock(dev, 96000, &clock);
79e53945
JB		 6709 } else {
6710 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6711
6712 if (is_lvds) {
6713 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6714 DPLL_FPA01_P1_POST_DIV_SHIFT);
6715 clock.p2 = 14;
6716
6717 if ((dpll & PLL_REF_INPUT_MASK) ==
6718 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6719 /* XXX: might not be 66MHz */
2177832f 6720 intel_clock(dev, 66000, &clock);
79e53945 6721 } else
2177832f 6722 intel_clock(dev, 48000, &clock);
79e53945
JB		 6723 } else {
6724 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6725 clock.p1 = 2;
6726 else {
6727 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6728 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6729 }
6730 if (dpll & PLL_P2_DIVIDE_BY_4)
6731 clock.p2 = 4;
6732 else
6733 clock.p2 = 2;
6734
2177832f 6735 intel_clock(dev, 48000, &clock);
79e53945
JB		 6736 }
6737 }
6738
6739 /* XXX: It would be nice to validate the clocks, but we can't reuse
6740 * i830PllIsValid() because it relies on the xf86_config connector
6741 * configuration being accurate, which it isn't necessarily.
6742 */
6743
6744 return clock.dot;
6745}
6746
6747/** Returns the currently programmed mode of the given pipe. */
6748struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6749 struct drm_crtc *crtc)
6750{
548f245b 6751 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6752 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fe2b8f9d 6753 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
79e53945 6754 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6755 int htot = I915_READ(HTOTAL(cpu_transcoder));
6756 int hsync = I915_READ(HSYNC(cpu_transcoder));
6757 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6758 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6759
6760 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6761 if (!mode)
6762 return NULL;
6763
6764 mode->clock = intel_crtc_clock_get(dev, crtc);
6765 mode->hdisplay = (htot & 0xffff) + 1;
6766 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6767 mode->hsync_start = (hsync & 0xffff) + 1;
6768 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6769 mode->vdisplay = (vtot & 0xffff) + 1;
6770 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6771 mode->vsync_start = (vsync & 0xffff) + 1;
6772 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6773
6774 drm_mode_set_name(mode);
79e53945
JB		 6775
6776 return mode;
6777}
6778
3dec0095 6779static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6780{
6781 struct drm_device *dev = crtc->dev;
6782 drm_i915_private_t *dev_priv = dev->dev_private;
6783 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6784 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6785 int dpll_reg = DPLL(pipe);
6786 int dpll;
652c393a 6787
bad720ff 6788 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6789 return;
6790
6791 if (!dev_priv->lvds_downclock_avail)
6792 return;
6793
dbdc6479 6794 dpll = I915_READ(dpll_reg);
652c393a 6795 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6796 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6797
8ac5a6d5 6798 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6799
6800 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6801 I915_WRITE(dpll_reg, dpll);
9d0498a2 6802 intel_wait_for_vblank(dev, pipe);
dbdc6479 6803
652c393a
JB		 6804 dpll = I915_READ(dpll_reg);
6805 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6806 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6807 }
652c393a
JB		 6808}
6809
6810static void intel_decrease_pllclock(struct drm_crtc *crtc)
6811{
6812 struct drm_device *dev = crtc->dev;
6813 drm_i915_private_t *dev_priv = dev->dev_private;
6814 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6815
bad720ff 6816 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6817 return;
6818
6819 if (!dev_priv->lvds_downclock_avail)
6820 return;
6821
6822 /*
6823 * Since this is called by a timer, we should never get here in
6824 * the manual case.
6825 */
6826 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6827 int pipe = intel_crtc->pipe;
6828 int dpll_reg = DPLL(pipe);
6829 int dpll;
f6e5b160 6830
44d98a61 6831 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6832
8ac5a6d5 6833 assert_panel_unlocked(dev_priv, pipe);
652c393a 6834
dc257cf1 6835 dpll = I915_READ(dpll_reg);
652c393a
JB		 6836 dpll |= DISPLAY_RATE_SELECT_FPA1;
6837 I915_WRITE(dpll_reg, dpll);
9d0498a2 6838 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6839 dpll = I915_READ(dpll_reg);
6840 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6841 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6842 }
6843
6844}
6845
f047e395
CW		 6846void intel_mark_busy(struct drm_device *dev)
6847{
f047e395
CW		 6848 i915_update_gfx_val(dev->dev_private);
6849}
6850
6851void intel_mark_idle(struct drm_device *dev)
652c393a 6852{
f047e395
CW		 6853}
6854
6855void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6856{
6857 struct drm_device *dev = obj->base.dev;
652c393a 6858 struct drm_crtc *crtc;
652c393a
JB		 6859
6860 if (!i915_powersave)
6861 return;
6862
652c393a 6863 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6864 if (!crtc->fb)
6865 continue;
6866
f047e395
CW		 6867 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6868 intel_increase_pllclock(crtc);
652c393a 6869 }
652c393a
JB		 6870}
6871
f047e395 6872void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
652c393a 6873{
f047e395
CW		 6874 struct drm_device *dev = obj->base.dev;
6875 struct drm_crtc *crtc;
652c393a 6876
f047e395 6877 if (!i915_powersave)
acb87dfb
CW		 6878 return;
6879
652c393a
JB		 6880 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6881 if (!crtc->fb)
6882 continue;
6883
f047e395
CW		 6884 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6885 intel_decrease_pllclock(crtc);
652c393a
JB		 6886 }
6887}
6888
79e53945
JB		 6889static void intel_crtc_destroy(struct drm_crtc *crtc)
6890{
6891 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6892 struct drm_device *dev = crtc->dev;
6893 struct intel_unpin_work *work;
6894 unsigned long flags;
6895
6896 spin_lock_irqsave(&dev->event_lock, flags);
6897 work = intel_crtc->unpin_work;
6898 intel_crtc->unpin_work = NULL;
6899 spin_unlock_irqrestore(&dev->event_lock, flags);
6900
6901 if (work) {
6902 cancel_work_sync(&work->work);
6903 kfree(work);
6904 }
79e53945
JB		 6905
6906 drm_crtc_cleanup(crtc);
67e77c5a 6907
79e53945
JB		 6908 kfree(intel_crtc);
6909}
6910
6b95a207
KH		 6911static void intel_unpin_work_fn(struct work_struct *__work)
6912{
6913 struct intel_unpin_work *work =
6914 container_of(__work, struct intel_unpin_work, work);
b4a98e57 6915 struct drm_device *dev = work->crtc->dev;
6b95a207 6916
b4a98e57 6917 mutex_lock(&dev->struct_mutex);
1690e1eb 6918 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 6919 drm_gem_object_unreference(&work->pending_flip_obj->base);
6920 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6921
b4a98e57
CW		 6922 intel_update_fbc(dev);
6923 mutex_unlock(&dev->struct_mutex);
6924
6925 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
6926 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
6927
6b95a207
KH		 6928 kfree(work);
6929}
6930
1afe3e9d 6931static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6932 struct drm_crtc *crtc)
6b95a207
KH		 6933{
6934 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6935 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6936 struct intel_unpin_work *work;
05394f39 6937 struct drm_i915_gem_object *obj;
6b95a207
KH		 6938 unsigned long flags;
6939
6940 /* Ignore early vblank irqs */
6941 if (intel_crtc == NULL)
6942 return;
6943
6944 spin_lock_irqsave(&dev->event_lock, flags);
6945 work = intel_crtc->unpin_work;
6946 if (work == NULL || !work->pending) {
6947 spin_unlock_irqrestore(&dev->event_lock, flags);
6948 return;
6949 }
6950
6951 intel_crtc->unpin_work = NULL;
6b95a207 6952
45a066eb
RC		 6953 if (work->event)
6954 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 6955
0af7e4df
MK		 6956 drm_vblank_put(dev, intel_crtc->pipe);
6957
6b95a207
KH		 6958 spin_unlock_irqrestore(&dev->event_lock, flags);
6959
05394f39 6960 obj = work->old_fb_obj;
d9e86c0e 6961
5bb61643 6962 wake_up(&dev_priv->pending_flip_queue);
b4a98e57
CW		 6963
6964 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 6965
6966 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6967}
6968
1afe3e9d
JB		 6969void intel_finish_page_flip(struct drm_device *dev, int pipe)
6970{
6971 drm_i915_private_t *dev_priv = dev->dev_private;
6972 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6973
49b14a5c 6974 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6975}
6976
6977void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6978{
6979 drm_i915_private_t *dev_priv = dev->dev_private;
6980 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6981
49b14a5c 6982 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6983}
6984
6b95a207
KH		 6985void intel_prepare_page_flip(struct drm_device *dev, int plane)
6986{
6987 drm_i915_private_t *dev_priv = dev->dev_private;
6988 struct intel_crtc *intel_crtc =
6989 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6990 unsigned long flags;
6991
6992 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 6993 if (intel_crtc->unpin_work) {
4e5359cd
SF		 6994 if ((++intel_crtc->unpin_work->pending) > 1)
6995 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 6996 } else {
6997 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6998 }
6b95a207
KH		 6999 spin_unlock_irqrestore(&dev->event_lock, flags);
7000}
7001
8c9f3aaf
JB		 7002static int intel_gen2_queue_flip(struct drm_device *dev,
7003 struct drm_crtc *crtc,
7004 struct drm_framebuffer *fb,
7005 struct drm_i915_gem_object *obj)
7006{
7007 struct drm_i915_private *dev_priv = dev->dev_private;
7008 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7009 u32 flip_mask;
6d90c952 7010 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7011 int ret;
7012
6d90c952 7013 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7014 if (ret)
83d4092b 7015 goto err;
8c9f3aaf 7016
6d90c952 7017 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7018 if (ret)
83d4092b 7019 goto err_unpin;
8c9f3aaf
JB		 7020
7021 /* Can't queue multiple flips, so wait for the previous
7022 * one to finish before executing the next.
7023 */
7024 if (intel_crtc->plane)
7025 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7026 else
7027 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7028 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7029 intel_ring_emit(ring, MI_NOOP);
7030 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7031 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7032 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7033 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7034 intel_ring_emit(ring, 0); /* aux display base address, unused */
7035 intel_ring_advance(ring);
83d4092b
CW		 7036 return 0;
7037
7038err_unpin:
7039 intel_unpin_fb_obj(obj);
7040err:
8c9f3aaf
JB		 7041 return ret;
7042}
7043
7044static int intel_gen3_queue_flip(struct drm_device *dev,
7045 struct drm_crtc *crtc,
7046 struct drm_framebuffer *fb,
7047 struct drm_i915_gem_object *obj)
7048{
7049 struct drm_i915_private *dev_priv = dev->dev_private;
7050 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7051 u32 flip_mask;
6d90c952 7052 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7053 int ret;
7054
6d90c952 7055 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7056 if (ret)
83d4092b 7057 goto err;
8c9f3aaf 7058
6d90c952 7059 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7060 if (ret)
83d4092b 7061 goto err_unpin;
8c9f3aaf
JB		 7062
7063 if (intel_crtc->plane)
7064 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7065 else
7066 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7067 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7068 intel_ring_emit(ring, MI_NOOP);
7069 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7070 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7071 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7072 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7073 intel_ring_emit(ring, MI_NOOP);
7074
7075 intel_ring_advance(ring);
83d4092b
CW		 7076 return 0;
7077
7078err_unpin:
7079 intel_unpin_fb_obj(obj);
7080err:
8c9f3aaf
JB		 7081 return ret;
7082}
7083
7084static int intel_gen4_queue_flip(struct drm_device *dev,
7085 struct drm_crtc *crtc,
7086 struct drm_framebuffer *fb,
7087 struct drm_i915_gem_object *obj)
7088{
7089 struct drm_i915_private *dev_priv = dev->dev_private;
7090 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7091 uint32_t pf, pipesrc;
6d90c952 7092 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7093 int ret;
7094
6d90c952 7095 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7096 if (ret)
83d4092b 7097 goto err;
8c9f3aaf 7098
6d90c952 7099 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7100 if (ret)
83d4092b 7101 goto err_unpin;
8c9f3aaf
JB		 7102
7103 /* i965+ uses the linear or tiled offsets from the
7104 * Display Registers (which do not change across a page-flip)
7105 * so we need only reprogram the base address.
7106 */
6d90c952
DV		 7107 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7108 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7109 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7110 intel_ring_emit(ring,
7111 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7112 obj->tiling_mode);
8c9f3aaf
JB		 7113
7114 /* XXX Enabling the panel-fitter across page-flip is so far
7115 * untested on non-native modes, so ignore it for now.
7116 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7117 */
7118 pf = 0;
7119 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 7120 intel_ring_emit(ring, pf | pipesrc);
7121 intel_ring_advance(ring);
83d4092b
CW		 7122 return 0;
7123
7124err_unpin:
7125 intel_unpin_fb_obj(obj);
7126err:
8c9f3aaf
JB		 7127 return ret;
7128}
7129
7130static int intel_gen6_queue_flip(struct drm_device *dev,
7131 struct drm_crtc *crtc,
7132 struct drm_framebuffer *fb,
7133 struct drm_i915_gem_object *obj)
7134{
7135 struct drm_i915_private *dev_priv = dev->dev_private;
7136 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7137 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7138 uint32_t pf, pipesrc;
7139 int ret;
7140
6d90c952 7141 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7142 if (ret)
83d4092b 7143 goto err;
8c9f3aaf 7144
6d90c952 7145 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7146 if (ret)
83d4092b 7147 goto err_unpin;
8c9f3aaf 7148
6d90c952
DV		 7149 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7150 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7151 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7152 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7153
dc257cf1
DV		 7154 /* Contrary to the suggestions in the documentation,
7155 * "Enable Panel Fitter" does not seem to be required when page
7156 * flipping with a non-native mode, and worse causes a normal
7157 * modeset to fail.
7158 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7159 */
7160 pf = 0;
8c9f3aaf 7161 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 7162 intel_ring_emit(ring, pf | pipesrc);
7163 intel_ring_advance(ring);
83d4092b
CW		 7164 return 0;
7165
7166err_unpin:
7167 intel_unpin_fb_obj(obj);
7168err:
8c9f3aaf
JB		 7169 return ret;
7170}
7171
7c9017e5
JB		 7172/*
7173 * On gen7 we currently use the blit ring because (in early silicon at least)
7174 * the render ring doesn't give us interrpts for page flip completion, which
7175 * means clients will hang after the first flip is queued. Fortunately the
7176 * blit ring generates interrupts properly, so use it instead.
7177 */
7178static int intel_gen7_queue_flip(struct drm_device *dev,
7179 struct drm_crtc *crtc,
7180 struct drm_framebuffer *fb,
7181 struct drm_i915_gem_object *obj)
7182{
7183 struct drm_i915_private *dev_priv = dev->dev_private;
7184 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7185 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7186 uint32_t plane_bit = 0;
7c9017e5
JB		 7187 int ret;
7188
7189 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7190 if (ret)
83d4092b 7191 goto err;
7c9017e5 7192
cb05d8de
DV		 7193 switch(intel_crtc->plane) {
7194 case PLANE_A:
7195 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7196 break;
7197 case PLANE_B:
7198 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7199 break;
7200 case PLANE_C:
7201 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7202 break;
7203 default:
7204 WARN_ONCE(1, "unknown plane in flip command\n");
7205 ret = -ENODEV;
ab3951eb 7206 goto err_unpin;
cb05d8de
DV		 7207 }
7208
7c9017e5
JB		 7209 ret = intel_ring_begin(ring, 4);
7210 if (ret)
83d4092b 7211 goto err_unpin;
7c9017e5 7212
cb05d8de 7213 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7214 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7215 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5
JB		 7216 intel_ring_emit(ring, (MI_NOOP));
7217 intel_ring_advance(ring);
83d4092b
CW		 7218 return 0;
7219
7220err_unpin:
7221 intel_unpin_fb_obj(obj);
7222err:
7c9017e5
JB		 7223 return ret;
7224}
7225
8c9f3aaf
JB		 7226static int intel_default_queue_flip(struct drm_device *dev,
7227 struct drm_crtc *crtc,
7228 struct drm_framebuffer *fb,
7229 struct drm_i915_gem_object *obj)
7230{
7231 return -ENODEV;
7232}
7233
6b95a207
KH		 7234static int intel_crtc_page_flip(struct drm_crtc *crtc,
7235 struct drm_framebuffer *fb,
7236 struct drm_pending_vblank_event *event)
7237{
7238 struct drm_device *dev = crtc->dev;
7239 struct drm_i915_private *dev_priv = dev->dev_private;
7240 struct intel_framebuffer *intel_fb;
05394f39 7241 struct drm_i915_gem_object *obj;
6b95a207
KH		 7242 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7243 struct intel_unpin_work *work;
8c9f3aaf 7244 unsigned long flags;
52e68630 7245 int ret;
6b95a207 7246
e6a595d2
VS		 7247 /* Can't change pixel format via MI display flips. */
7248 if (fb->pixel_format != crtc->fb->pixel_format)
7249 return -EINVAL;
7250
7251 /*
7252 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7253 * Note that pitch changes could also affect these register.
7254 */
7255 if (INTEL_INFO(dev)->gen > 3 &&
7256 (fb->offsets[0] != crtc->fb->offsets[0] ||
7257 fb->pitches[0] != crtc->fb->pitches[0]))
7258 return -EINVAL;
7259
6b95a207
KH		 7260 work = kzalloc(sizeof *work, GFP_KERNEL);
7261 if (work == NULL)
7262 return -ENOMEM;
7263
6b95a207 7264 work->event = event;
b4a98e57 7265 work->crtc = crtc;
6b95a207 7266 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 7267 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 7268 INIT_WORK(&work->work, intel_unpin_work_fn);
7269
7317c75e
JB		 7270 ret = drm_vblank_get(dev, intel_crtc->pipe);
7271 if (ret)
7272 goto free_work;
7273
6b95a207
KH		 7274 /* We borrow the event spin lock for protecting unpin_work */
7275 spin_lock_irqsave(&dev->event_lock, flags);
7276 if (intel_crtc->unpin_work) {
7277 spin_unlock_irqrestore(&dev->event_lock, flags);
7278 kfree(work);
7317c75e 7279 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7280
7281 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7282 return -EBUSY;
7283 }
7284 intel_crtc->unpin_work = work;
7285 spin_unlock_irqrestore(&dev->event_lock, flags);
7286
7287 intel_fb = to_intel_framebuffer(fb);
7288 obj = intel_fb->obj;
7289
b4a98e57
CW		 7290 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7291 flush_workqueue(dev_priv->wq);
7292
79158103
CW		 7293 ret = i915_mutex_lock_interruptible(dev);
7294 if (ret)
7295 goto cleanup;
6b95a207 7296
75dfca80 7297 /* Reference the objects for the scheduled work. */
05394f39
CW		 7298 drm_gem_object_reference(&work->old_fb_obj->base);
7299 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7300
7301 crtc->fb = fb;
96b099fd 7302
e1f99ce6 7303 work->pending_flip_obj = obj;
e1f99ce6 7304
4e5359cd
SF		 7305 work->enable_stall_check = true;
7306
b4a98e57 7307 atomic_inc(&intel_crtc->unpin_work_count);
e1f99ce6 7308
8c9f3aaf
JB		 7309 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7310 if (ret)
7311 goto cleanup_pending;
6b95a207 7312
7782de3b 7313 intel_disable_fbc(dev);
f047e395 7314 intel_mark_fb_busy(obj);
6b95a207
KH		 7315 mutex_unlock(&dev->struct_mutex);
7316
e5510fac
JB		 7317 trace_i915_flip_request(intel_crtc->plane, obj);
7318
6b95a207 7319 return 0;
96b099fd 7320
8c9f3aaf 7321cleanup_pending:
b4a98e57 7322 atomic_dec(&intel_crtc->unpin_work_count);
05394f39
CW		 7323 drm_gem_object_unreference(&work->old_fb_obj->base);
7324 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7325 mutex_unlock(&dev->struct_mutex);
7326
79158103 7327cleanup:
96b099fd
CW		 7328 spin_lock_irqsave(&dev->event_lock, flags);
7329 intel_crtc->unpin_work = NULL;
7330 spin_unlock_irqrestore(&dev->event_lock, flags);
7331
7317c75e
JB		 7332 drm_vblank_put(dev, intel_crtc->pipe);
7333free_work:
96b099fd
CW		 7334 kfree(work);
7335
7336 return ret;
6b95a207
KH		 7337}
7338
f6e5b160 7339static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7340 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7341 .load_lut = intel_crtc_load_lut,
976f8a20 7342 .disable = intel_crtc_noop,
f6e5b160
CW		 7343};
7344
6ed0f796 7345bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7346{
6ed0f796
DV		 7347 struct intel_encoder *other_encoder;
7348 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7349
6ed0f796
DV		 7350 if (WARN_ON(!crtc))
7351 return false;
7352
7353 list_for_each_entry(other_encoder,
7354 &crtc->dev->mode_config.encoder_list,
7355 base.head) {
7356
7357 if (&other_encoder->new_crtc->base != crtc ||
7358 encoder == other_encoder)
7359 continue;
7360 else
7361 return true;
f47166d2
CW		 7362 }
7363
6ed0f796
DV		 7364 return false;
7365}
47f1c6c9 7366
50f56119
DV		 7367static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7368 struct drm_crtc *crtc)
7369{
7370 struct drm_device *dev;
7371 struct drm_crtc *tmp;
7372 int crtc_mask = 1;
47f1c6c9 7373
50f56119 7374 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7375
50f56119 7376 dev = crtc->dev;
47f1c6c9 7377
50f56119
DV		 7378 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7379 if (tmp == crtc)
7380 break;
7381 crtc_mask <<= 1;
7382 }
47f1c6c9 7383
50f56119
DV		 7384 if (encoder->possible_crtcs & crtc_mask)
7385 return true;
7386 return false;
47f1c6c9 7387}
79e53945 7388
9a935856
DV		 7389/**
7390 * intel_modeset_update_staged_output_state
7391 *
7392 * Updates the staged output configuration state, e.g. after we've read out the
7393 * current hw state.
7394 */
7395static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7396{
9a935856
DV		 7397 struct intel_encoder *encoder;
7398 struct intel_connector *connector;
f6e5b160 7399
9a935856
DV		 7400 list_for_each_entry(connector, &dev->mode_config.connector_list,
7401 base.head) {
7402 connector->new_encoder =
7403 to_intel_encoder(connector->base.encoder);
7404 }
f6e5b160 7405
9a935856
DV		 7406 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7407 base.head) {
7408 encoder->new_crtc =
7409 to_intel_crtc(encoder->base.crtc);
7410 }
f6e5b160
CW		 7411}
7412
9a935856
DV		 7413/**
7414 * intel_modeset_commit_output_state
7415 *
7416 * This function copies the stage display pipe configuration to the real one.
7417 */
7418static void intel_modeset_commit_output_state(struct drm_device *dev)
7419{
7420 struct intel_encoder *encoder;
7421 struct intel_connector *connector;
f6e5b160 7422
9a935856
DV		 7423 list_for_each_entry(connector, &dev->mode_config.connector_list,
7424 base.head) {
7425 connector->base.encoder = &connector->new_encoder->base;
7426 }
f6e5b160 7427
9a935856
DV		 7428 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7429 base.head) {
7430 encoder->base.crtc = &encoder->new_crtc->base;
7431 }
7432}
7433
7758a113
DV		 7434static struct drm_display_mode *
7435intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7436 struct drm_display_mode *mode)
ee7b9f93 7437{
7758a113
DV		 7438 struct drm_device *dev = crtc->dev;
7439 struct drm_display_mode *adjusted_mode;
7440 struct drm_encoder_helper_funcs *encoder_funcs;
7441 struct intel_encoder *encoder;
ee7b9f93 7442
7758a113
DV		 7443 adjusted_mode = drm_mode_duplicate(dev, mode);
7444 if (!adjusted_mode)
7445 return ERR_PTR(-ENOMEM);
7446
7447 /* Pass our mode to the connectors and the CRTC to give them a chance to
7448 * adjust it according to limitations or connector properties, and also
7449 * a chance to reject the mode entirely.
47f1c6c9 7450 */
7758a113
DV		 7451 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7452 base.head) {
47f1c6c9 7453
7758a113
DV		 7454 if (&encoder->new_crtc->base != crtc)
7455 continue;
7456 encoder_funcs = encoder->base.helper_private;
7457 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7458 adjusted_mode))) {
7459 DRM_DEBUG_KMS("Encoder fixup failed\n");
7460 goto fail;
7461 }
ee7b9f93 7462 }
47f1c6c9 7463
7758a113
DV		 7464 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7465 DRM_DEBUG_KMS("CRTC fixup failed\n");
7466 goto fail;
ee7b9f93 7467 }
7758a113 7468 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
47f1c6c9 7469
7758a113
DV		 7470 return adjusted_mode;
7471fail:
7472 drm_mode_destroy(dev, adjusted_mode);
7473 return ERR_PTR(-EINVAL);
ee7b9f93 7474}
47f1c6c9 7475
e2e1ed41
DV		 7476/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7477 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7478static void
7479intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7480 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7481{
7482 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7483 struct drm_device *dev = crtc->dev;
7484 struct intel_encoder *encoder;
7485 struct intel_connector *connector;
7486 struct drm_crtc *tmp_crtc;
79e53945 7487
e2e1ed41 7488 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7489
e2e1ed41
DV		 7490 /* Check which crtcs have changed outputs connected to them, these need
7491 * to be part of the prepare_pipes mask. We don't (yet) support global
7492 * modeset across multiple crtcs, so modeset_pipes will only have one
7493 * bit set at most. */
7494 list_for_each_entry(connector, &dev->mode_config.connector_list,
7495 base.head) {
7496 if (connector->base.encoder == &connector->new_encoder->base)
7497 continue;
79e53945 7498
e2e1ed41
DV		 7499 if (connector->base.encoder) {
7500 tmp_crtc = connector->base.encoder->crtc;
7501
7502 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7503 }
7504
7505 if (connector->new_encoder)
7506 *prepare_pipes |=
7507 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7508 }
7509
e2e1ed41
DV		 7510 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7511 base.head) {
7512 if (encoder->base.crtc == &encoder->new_crtc->base)
7513 continue;
7514
7515 if (encoder->base.crtc) {
7516 tmp_crtc = encoder->base.crtc;
7517
7518 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7519 }
7520
7521 if (encoder->new_crtc)
7522 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7523 }
7524
e2e1ed41
DV		 7525 /* Check for any pipes that will be fully disabled ... */
7526 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7527 base.head) {
7528 bool used = false;
22fd0fab 7529
e2e1ed41
DV		 7530 /* Don't try to disable disabled crtcs. */
7531 if (!intel_crtc->base.enabled)
7532 continue;
7e7d76c3 7533
e2e1ed41
DV		 7534 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7535 base.head) {
7536 if (encoder->new_crtc == intel_crtc)
7537 used = true;
7538 }
7539
7540 if (!used)
7541 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7542 }
7543
e2e1ed41
DV		 7544
7545 /* set_mode is also used to update properties on life display pipes. */
7546 intel_crtc = to_intel_crtc(crtc);
7547 if (crtc->enabled)
7548 *prepare_pipes |= 1 << intel_crtc->pipe;
7549
7550 /* We only support modeset on one single crtc, hence we need to do that
7551 * only for the passed in crtc iff we change anything else than just
7552 * disable crtcs.
7553 *
7554 * This is actually not true, to be fully compatible with the old crtc
7555 * helper we automatically disable _any_ output (i.e. doesn't need to be
7556 * connected to the crtc we're modesetting on) if it's disconnected.
7557 * Which is a rather nutty api (since changed the output configuration
7558 * without userspace's explicit request can lead to confusion), but
7559 * alas. Hence we currently need to modeset on all pipes we prepare. */
7560 if (*prepare_pipes)
7561 *modeset_pipes = *prepare_pipes;
7562
7563 /* ... and mask these out. */
7564 *modeset_pipes &= ~(*disable_pipes);
7565 *prepare_pipes &= ~(*disable_pipes);
47f1c6c9 7566}
79e53945 7567
ea9d758d 7568static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7569{
ea9d758d 7570 struct drm_encoder *encoder;
f6e5b160 7571 struct drm_device *dev = crtc->dev;
f6e5b160 7572
ea9d758d
DV		 7573 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7574 if (encoder->crtc == crtc)
7575 return true;
7576
7577 return false;
7578}
7579
7580static void
7581intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7582{
7583 struct intel_encoder *intel_encoder;
7584 struct intel_crtc *intel_crtc;
7585 struct drm_connector *connector;
7586
7587 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7588 base.head) {
7589 if (!intel_encoder->base.crtc)
7590 continue;
7591
7592 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7593
7594 if (prepare_pipes & (1 << intel_crtc->pipe))
7595 intel_encoder->connectors_active = false;
7596 }
7597
7598 intel_modeset_commit_output_state(dev);
7599
7600 /* Update computed state. */
7601 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7602 base.head) {
7603 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7604 }
7605
7606 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7607 if (!connector->encoder || !connector->encoder->crtc)
7608 continue;
7609
7610 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7611
7612 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7613 struct drm_property *dpms_property =
7614 dev->mode_config.dpms_property;
7615
ea9d758d 7616 connector->dpms = DRM_MODE_DPMS_ON;
662595df 7617 drm_object_property_set_value(&connector->base,
68d34720
DV		 7618 dpms_property,
7619 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7620
7621 intel_encoder = to_intel_encoder(connector->encoder);
7622 intel_encoder->connectors_active = true;
7623 }
7624 }
7625
7626}
7627
25c5b266
DV		 7628#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7629 list_for_each_entry((intel_crtc), \
7630 &(dev)->mode_config.crtc_list, \
7631 base.head) \
7632 if (mask & (1 <<(intel_crtc)->pipe)) \
7633
b980514c 7634void
8af6cf88
DV		 7635intel_modeset_check_state(struct drm_device *dev)
7636{
7637 struct intel_crtc *crtc;
7638 struct intel_encoder *encoder;
7639 struct intel_connector *connector;
7640
7641 list_for_each_entry(connector, &dev->mode_config.connector_list,
7642 base.head) {
7643 /* This also checks the encoder/connector hw state with the
7644 * ->get_hw_state callbacks. */
7645 intel_connector_check_state(connector);
7646
7647 WARN(&connector->new_encoder->base != connector->base.encoder,
7648 "connector's staged encoder doesn't match current encoder\n");
7649 }
7650
7651 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7652 base.head) {
7653 bool enabled = false;
7654 bool active = false;
7655 enum pipe pipe, tracked_pipe;
7656
7657 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7658 encoder->base.base.id,
7659 drm_get_encoder_name(&encoder->base));
7660
7661 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7662 "encoder's stage crtc doesn't match current crtc\n");
7663 WARN(encoder->connectors_active && !encoder->base.crtc,
7664 "encoder's active_connectors set, but no crtc\n");
7665
7666 list_for_each_entry(connector, &dev->mode_config.connector_list,
7667 base.head) {
7668 if (connector->base.encoder != &encoder->base)
7669 continue;
7670 enabled = true;
7671 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7672 active = true;
7673 }
7674 WARN(!!encoder->base.crtc != enabled,
7675 "encoder's enabled state mismatch "
7676 "(expected %i, found %i)\n",
7677 !!encoder->base.crtc, enabled);
7678 WARN(active && !encoder->base.crtc,
7679 "active encoder with no crtc\n");
7680
7681 WARN(encoder->connectors_active != active,
7682 "encoder's computed active state doesn't match tracked active state "
7683 "(expected %i, found %i)\n", active, encoder->connectors_active);
7684
7685 active = encoder->get_hw_state(encoder, &pipe);
7686 WARN(active != encoder->connectors_active,
7687 "encoder's hw state doesn't match sw tracking "
7688 "(expected %i, found %i)\n",
7689 encoder->connectors_active, active);
7690
7691 if (!encoder->base.crtc)
7692 continue;
7693
7694 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7695 WARN(active && pipe != tracked_pipe,
7696 "active encoder's pipe doesn't match"
7697 "(expected %i, found %i)\n",
7698 tracked_pipe, pipe);
7699
7700 }
7701
7702 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7703 base.head) {
7704 bool enabled = false;
7705 bool active = false;
7706
7707 DRM_DEBUG_KMS("[CRTC:%d]\n",
7708 crtc->base.base.id);
7709
7710 WARN(crtc->active && !crtc->base.enabled,
7711 "active crtc, but not enabled in sw tracking\n");
7712
7713 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7714 base.head) {
7715 if (encoder->base.crtc != &crtc->base)
7716 continue;
7717 enabled = true;
7718 if (encoder->connectors_active)
7719 active = true;
7720 }
7721 WARN(active != crtc->active,
7722 "crtc's computed active state doesn't match tracked active state "
7723 "(expected %i, found %i)\n", active, crtc->active);
7724 WARN(enabled != crtc->base.enabled,
7725 "crtc's computed enabled state doesn't match tracked enabled state "
7726 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7727
7728 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7729 }
7730}
7731
a6778b3c
DV		 7732bool intel_set_mode(struct drm_crtc *crtc,
7733 struct drm_display_mode *mode,
94352cf9 7734 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 7735{
7736 struct drm_device *dev = crtc->dev;
dbf2b54e 7737 drm_i915_private_t *dev_priv = dev->dev_private;
a6778b3c 7738 struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
25c5b266
DV		 7739 struct intel_crtc *intel_crtc;
7740 unsigned disable_pipes, prepare_pipes, modeset_pipes;
a6778b3c
DV		 7741 bool ret = true;
7742
e2e1ed41 7743 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 7744 &prepare_pipes, &disable_pipes);
7745
7746 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7747 modeset_pipes, prepare_pipes, disable_pipes);
e2e1ed41 7748
976f8a20
DV		 7749 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7750 intel_crtc_disable(&intel_crtc->base);
87f1faa6 7751
a6778b3c
DV		 7752 saved_hwmode = crtc->hwmode;
7753 saved_mode = crtc->mode;
a6778b3c 7754
25c5b266
DV		 7755 /* Hack: Because we don't (yet) support global modeset on multiple
7756 * crtcs, we don't keep track of the new mode for more than one crtc.
7757 * Hence simply check whether any bit is set in modeset_pipes in all the
7758 * pieces of code that are not yet converted to deal with mutliple crtcs
7759 * changing their mode at the same time. */
7760 adjusted_mode = NULL;
7761 if (modeset_pipes) {
7762 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7763 if (IS_ERR(adjusted_mode)) {
7764 return false;
7765 }
25c5b266 7766 }
a6778b3c 7767
ea9d758d
DV		 7768 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7769 if (intel_crtc->base.enabled)
7770 dev_priv->display.crtc_disable(&intel_crtc->base);
7771 }
a6778b3c 7772
6c4c86f5
DV		 7773 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7774 * to set it here already despite that we pass it down the callchain.
f6e5b160 7775 */
6c4c86f5 7776 if (modeset_pipes)
25c5b266 7777 crtc->mode = *mode;
7758a113 7778
ea9d758d
DV		 7779 /* Only after disabling all output pipelines that will be changed can we
7780 * update the the output configuration. */
7781 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 7782
47fab737
DV		 7783 if (dev_priv->display.modeset_global_resources)
7784 dev_priv->display.modeset_global_resources(dev);
7785
a6778b3c
DV		 7786 /* Set up the DPLL and any encoders state that needs to adjust or depend
7787 * on the DPLL.
f6e5b160 7788 */
25c5b266
DV		 7789 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7790 ret = !intel_crtc_mode_set(&intel_crtc->base,
7791 mode, adjusted_mode,
7792 x, y, fb);
7793 if (!ret)
7794 goto done;
a6778b3c
DV		 7795 }
7796
7797 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 7798 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7799 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 7800
25c5b266
DV		 7801 if (modeset_pipes) {
7802 /* Store real post-adjustment hardware mode. */
7803 crtc->hwmode = *adjusted_mode;
a6778b3c 7804
25c5b266
DV		 7805 /* Calculate and store various constants which
7806 * are later needed by vblank and swap-completion
7807 * timestamping. They are derived from true hwmode.
7808 */
7809 drm_calc_timestamping_constants(crtc);
7810 }
a6778b3c
DV		 7811
7812 /* FIXME: add subpixel order */
7813done:
7814 drm_mode_destroy(dev, adjusted_mode);
25c5b266 7815 if (!ret && crtc->enabled) {
a6778b3c
DV		 7816 crtc->hwmode = saved_hwmode;
7817 crtc->mode = saved_mode;
8af6cf88
DV		 7818 } else {
7819 intel_modeset_check_state(dev);
a6778b3c
DV		 7820 }
7821
7822 return ret;
f6e5b160
CW		 7823}
7824
25c5b266
DV		 7825#undef for_each_intel_crtc_masked
7826
d9e55608
DV		 7827static void intel_set_config_free(struct intel_set_config *config)
7828{
7829 if (!config)
7830 return;
7831
1aa4b628
DV		 7832 kfree(config->save_connector_encoders);
7833 kfree(config->save_encoder_crtcs);
d9e55608
DV		 7834 kfree(config);
7835}
7836
85f9eb71
DV		 7837static int intel_set_config_save_state(struct drm_device *dev,
7838 struct intel_set_config *config)
7839{
85f9eb71
DV		 7840 struct drm_encoder *encoder;
7841 struct drm_connector *connector;
7842 int count;
7843
1aa4b628
DV		 7844 config->save_encoder_crtcs =
7845 kcalloc(dev->mode_config.num_encoder,
7846 sizeof(struct drm_crtc *), GFP_KERNEL);
7847 if (!config->save_encoder_crtcs)
85f9eb71
DV		 7848 return -ENOMEM;
7849
1aa4b628
DV		 7850 config->save_connector_encoders =
7851 kcalloc(dev->mode_config.num_connector,
7852 sizeof(struct drm_encoder *), GFP_KERNEL);
7853 if (!config->save_connector_encoders)
85f9eb71
DV		 7854 return -ENOMEM;
7855
7856 /* Copy data. Note that driver private data is not affected.
7857 * Should anything bad happen only the expected state is
7858 * restored, not the drivers personal bookkeeping.
7859 */
85f9eb71
DV		 7860 count = 0;
7861 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 7862 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 7863 }
7864
7865 count = 0;
7866 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 7867 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 7868 }
7869
7870 return 0;
7871}
7872
7873static void intel_set_config_restore_state(struct drm_device *dev,
7874 struct intel_set_config *config)
7875{
9a935856
DV		 7876 struct intel_encoder *encoder;
7877 struct intel_connector *connector;
85f9eb71
DV		 7878 int count;
7879
85f9eb71 7880 count = 0;
9a935856
DV		 7881 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7882 encoder->new_crtc =
7883 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 7884 }
7885
7886 count = 0;
9a935856
DV		 7887 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7888 connector->new_encoder =
7889 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 7890 }
7891}
7892
5e2b584e
DV		 7893static void
7894intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7895 struct intel_set_config *config)
7896{
7897
7898 /* We should be able to check here if the fb has the same properties
7899 * and then just flip_or_move it */
7900 if (set->crtc->fb != set->fb) {
7901 /* If we have no fb then treat it as a full mode set */
7902 if (set->crtc->fb == NULL) {
7903 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7904 config->mode_changed = true;
7905 } else if (set->fb == NULL) {
7906 config->mode_changed = true;
7907 } else if (set->fb->depth != set->crtc->fb->depth) {
7908 config->mode_changed = true;
7909 } else if (set->fb->bits_per_pixel !=
7910 set->crtc->fb->bits_per_pixel) {
7911 config->mode_changed = true;
7912 } else
7913 config->fb_changed = true;
7914 }
7915
835c5873 7916 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 7917 config->fb_changed = true;
7918
7919 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7920 DRM_DEBUG_KMS("modes are different, full mode set\n");
7921 drm_mode_debug_printmodeline(&set->crtc->mode);
7922 drm_mode_debug_printmodeline(set->mode);
7923 config->mode_changed = true;
7924 }
7925}
7926
2e431051 7927static int
9a935856
DV		 7928intel_modeset_stage_output_state(struct drm_device *dev,
7929 struct drm_mode_set *set,
7930 struct intel_set_config *config)
50f56119 7931{
85f9eb71 7932 struct drm_crtc *new_crtc;
9a935856
DV		 7933 struct intel_connector *connector;
7934 struct intel_encoder *encoder;
2e431051 7935 int count, ro;
50f56119 7936
9a935856
DV		 7937 /* The upper layers ensure that we either disabl a crtc or have a list
7938 * of connectors. For paranoia, double-check this. */
7939 WARN_ON(!set->fb && (set->num_connectors != 0));
7940 WARN_ON(set->fb && (set->num_connectors == 0));
7941
50f56119 7942 count = 0;
9a935856
DV		 7943 list_for_each_entry(connector, &dev->mode_config.connector_list,
7944 base.head) {
7945 /* Otherwise traverse passed in connector list and get encoders
7946 * for them. */
50f56119 7947 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 7948 if (set->connectors[ro] == &connector->base) {
7949 connector->new_encoder = connector->encoder;
50f56119
DV		 7950 break;
7951 }
7952 }
7953
9a935856
DV		 7954 /* If we disable the crtc, disable all its connectors. Also, if
7955 * the connector is on the changing crtc but not on the new
7956 * connector list, disable it. */
7957 if ((!set->fb || ro == set->num_connectors) &&
7958 connector->base.encoder &&
7959 connector->base.encoder->crtc == set->crtc) {
7960 connector->new_encoder = NULL;
7961
7962 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7963 connector->base.base.id,
7964 drm_get_connector_name(&connector->base));
7965 }
7966
7967
7968 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 7969 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 7970 config->mode_changed = true;
50f56119 7971 }
9a935856
DV		 7972
7973 /* Disable all disconnected encoders. */
7974 if (connector->base.status == connector_status_disconnected)
7975 connector->new_encoder = NULL;
50f56119 7976 }
9a935856 7977 /* connector->new_encoder is now updated for all connectors. */
50f56119 7978
9a935856 7979 /* Update crtc of enabled connectors. */
50f56119 7980 count = 0;
9a935856
DV		 7981 list_for_each_entry(connector, &dev->mode_config.connector_list,
7982 base.head) {
7983 if (!connector->new_encoder)
50f56119
DV		 7984 continue;
7985
9a935856 7986 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 7987
7988 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 7989 if (set->connectors[ro] == &connector->base)
50f56119
DV		 7990 new_crtc = set->crtc;
7991 }
7992
7993 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 7994 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7995 new_crtc)) {
5e2b584e 7996 return -EINVAL;
50f56119 7997 }
9a935856
DV		 7998 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7999
8000 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8001 connector->base.base.id,
8002 drm_get_connector_name(&connector->base),
8003 new_crtc->base.id);
8004 }
8005
8006 /* Check for any encoders that needs to be disabled. */
8007 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8008 base.head) {
8009 list_for_each_entry(connector,
8010 &dev->mode_config.connector_list,
8011 base.head) {
8012 if (connector->new_encoder == encoder) {
8013 WARN_ON(!connector->new_encoder->new_crtc);
8014
8015 goto next_encoder;
8016 }
8017 }
8018 encoder->new_crtc = NULL;
8019next_encoder:
8020 /* Only now check for crtc changes so we don't miss encoders
8021 * that will be disabled. */
8022 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8023 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8024 config->mode_changed = true;
50f56119
DV		 8025 }
8026 }
9a935856 8027 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8028
2e431051
DV		 8029 return 0;
8030}
8031
8032static int intel_crtc_set_config(struct drm_mode_set *set)
8033{
8034 struct drm_device *dev;
2e431051
DV		 8035 struct drm_mode_set save_set;
8036 struct intel_set_config *config;
8037 int ret;
2e431051 8038
8d3e375e
DV		 8039 BUG_ON(!set);
8040 BUG_ON(!set->crtc);
8041 BUG_ON(!set->crtc->helper_private);
2e431051
DV		 8042
8043 if (!set->mode)
8044 set->fb = NULL;
8045
431e50f7
DV		 8046 /* The fb helper likes to play gross jokes with ->mode_set_config.
8047 * Unfortunately the crtc helper doesn't do much at all for this case,
8048 * so we have to cope with this madness until the fb helper is fixed up. */
8049 if (set->fb && set->num_connectors == 0)
8050 return 0;
8051
2e431051
DV		 8052 if (set->fb) {
8053 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8054 set->crtc->base.id, set->fb->base.id,
8055 (int)set->num_connectors, set->x, set->y);
8056 } else {
8057 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8058 }
8059
8060 dev = set->crtc->dev;
8061
8062 ret = -ENOMEM;
8063 config = kzalloc(sizeof(*config), GFP_KERNEL);
8064 if (!config)
8065 goto out_config;
8066
8067 ret = intel_set_config_save_state(dev, config);
8068 if (ret)
8069 goto out_config;
8070
8071 save_set.crtc = set->crtc;
8072 save_set.mode = &set->crtc->mode;
8073 save_set.x = set->crtc->x;
8074 save_set.y = set->crtc->y;
8075 save_set.fb = set->crtc->fb;
8076
8077 /* Compute whether we need a full modeset, only an fb base update or no
8078 * change at all. In the future we might also check whether only the
8079 * mode changed, e.g. for LVDS where we only change the panel fitter in
8080 * such cases. */
8081 intel_set_config_compute_mode_changes(set, config);
8082
9a935856 8083 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8084 if (ret)
8085 goto fail;
8086
5e2b584e 8087 if (config->mode_changed) {
87f1faa6 8088 if (set->mode) {
50f56119
DV		 8089 DRM_DEBUG_KMS("attempting to set mode from"
8090 " userspace\n");
8091 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 8092 }
8093
8094 if (!intel_set_mode(set->crtc, set->mode,
8095 set->x, set->y, set->fb)) {
8096 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
8097 set->crtc->base.id);
8098 ret = -EINVAL;
8099 goto fail;
8100 }
5e2b584e 8101 } else if (config->fb_changed) {
4f660f49 8102 ret = intel_pipe_set_base(set->crtc,
94352cf9 8103 set->x, set->y, set->fb);
50f56119
DV		 8104 }
8105
d9e55608
DV		 8106 intel_set_config_free(config);
8107
50f56119
DV		 8108 return 0;
8109
8110fail:
85f9eb71 8111 intel_set_config_restore_state(dev, config);
50f56119
DV		 8112
8113 /* Try to restore the config */
5e2b584e 8114 if (config->mode_changed &&
a6778b3c
DV		 8115 !intel_set_mode(save_set.crtc, save_set.mode,
8116 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8117 DRM_ERROR("failed to restore config after modeset failure\n");
8118
d9e55608
DV		 8119out_config:
8120 intel_set_config_free(config);
50f56119
DV		 8121 return ret;
8122}
f6e5b160
CW		 8123
8124static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8125 .cursor_set = intel_crtc_cursor_set,
8126 .cursor_move = intel_crtc_cursor_move,
8127 .gamma_set = intel_crtc_gamma_set,
50f56119 8128 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8129 .destroy = intel_crtc_destroy,
8130 .page_flip = intel_crtc_page_flip,
8131};
8132
79f689aa
PZ		 8133static void intel_cpu_pll_init(struct drm_device *dev)
8134{
8135 if (IS_HASWELL(dev))
8136 intel_ddi_pll_init(dev);
8137}
8138
ee7b9f93
JB		 8139static void intel_pch_pll_init(struct drm_device *dev)
8140{
8141 drm_i915_private_t *dev_priv = dev->dev_private;
8142 int i;
8143
8144 if (dev_priv->num_pch_pll == 0) {
8145 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8146 return;
8147 }
8148
8149 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8150 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8151 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8152 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8153 }
8154}
8155
b358d0a6 8156static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8157{
22fd0fab 8158 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8159 struct intel_crtc *intel_crtc;
8160 int i;
8161
8162 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8163 if (intel_crtc == NULL)
8164 return;
8165
8166 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8167
8168 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8169 for (i = 0; i < 256; i++) {
8170 intel_crtc->lut_r[i] = i;
8171 intel_crtc->lut_g[i] = i;
8172 intel_crtc->lut_b[i] = i;
8173 }
8174
80824003
JB		 8175 /* Swap pipes & planes for FBC on pre-965 */
8176 intel_crtc->pipe = pipe;
8177 intel_crtc->plane = pipe;
a5c961d1 8178 intel_crtc->cpu_transcoder = pipe;
e2e767ab 8179 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8180 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8181 intel_crtc->plane = !pipe;
80824003
JB		 8182 }
8183
22fd0fab
JB		 8184 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8185 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8186 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8187 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8188
5a354204 8189 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3 8190
79e53945 8191 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8192}
8193
08d7b3d1 8194int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8195 struct drm_file *file)
08d7b3d1 8196{
08d7b3d1 8197 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8198 struct drm_mode_object *drmmode_obj;
8199 struct intel_crtc *crtc;
08d7b3d1 8200
1cff8f6b
DV		 8201 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8202 return -ENODEV;
08d7b3d1 8203
c05422d5
DV		 8204 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8205 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8206
c05422d5 8207 if (!drmmode_obj) {
08d7b3d1
CW		 8208 DRM_ERROR("no such CRTC id\n");
8209 return -EINVAL;
8210 }
8211
c05422d5
DV		 8212 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8213 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8214
c05422d5 8215 return 0;
08d7b3d1
CW		 8216}
8217
66a9278e 8218static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8219{
66a9278e
DV		 8220 struct drm_device *dev = encoder->base.dev;
8221 struct intel_encoder *source_encoder;
79e53945 8222 int index_mask = 0;
79e53945
JB		 8223 int entry = 0;
8224
66a9278e
DV		 8225 list_for_each_entry(source_encoder,
8226 &dev->mode_config.encoder_list, base.head) {
8227
8228 if (encoder == source_encoder)
79e53945 8229 index_mask |= (1 << entry);
66a9278e
DV		 8230
8231 /* Intel hw has only one MUX where enocoders could be cloned. */
8232 if (encoder->cloneable && source_encoder->cloneable)
8233 index_mask |= (1 << entry);
8234
79e53945
JB		 8235 entry++;
8236 }
4ef69c7a 8237
79e53945
JB		 8238 return index_mask;
8239}
8240
4d302442
CW		 8241static bool has_edp_a(struct drm_device *dev)
8242{
8243 struct drm_i915_private *dev_priv = dev->dev_private;
8244
8245 if (!IS_MOBILE(dev))
8246 return false;
8247
8248 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8249 return false;
8250
8251 if (IS_GEN5(dev) &&
8252 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8253 return false;
8254
8255 return true;
8256}
8257
79e53945
JB		 8258static void intel_setup_outputs(struct drm_device *dev)
8259{
725e30ad 8260 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8261 struct intel_encoder *encoder;
cb0953d7 8262 bool dpd_is_edp = false;
f3cfcba6 8263 bool has_lvds;
79e53945 8264
f3cfcba6 8265 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8266 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8267 /* disable the panel fitter on everything but LVDS */
8268 I915_WRITE(PFIT_CONTROL, 0);
8269 }
79e53945 8270
79935fca
PZ		 8271 if (!(IS_HASWELL(dev) &&
8272 (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
8273 intel_crt_init(dev);
cb0953d7 8274
0e72a5b5
ED		 8275 if (IS_HASWELL(dev)) {
8276 int found;
8277
8278 /* Haswell uses DDI functions to detect digital outputs */
8279 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8280 /* DDI A only supports eDP */
8281 if (found)
8282 intel_ddi_init(dev, PORT_A);
8283
8284 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8285 * register */
8286 found = I915_READ(SFUSE_STRAP);
8287
8288 if (found & SFUSE_STRAP_DDIB_DETECTED)
8289 intel_ddi_init(dev, PORT_B);
8290 if (found & SFUSE_STRAP_DDIC_DETECTED)
8291 intel_ddi_init(dev, PORT_C);
8292 if (found & SFUSE_STRAP_DDID_DETECTED)
8293 intel_ddi_init(dev, PORT_D);
8294 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8295 int found;
270b3042
DV		 8296 dpd_is_edp = intel_dpd_is_edp(dev);
8297
8298 if (has_edp_a(dev))
8299 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8300
30ad48b7 8301 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca 8302 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8303 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8304 if (!found)
08d644ad 8305 intel_hdmi_init(dev, HDMIB, PORT_B);
5eb08b69 8306 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8307 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8308 }
8309
8310 if (I915_READ(HDMIC) & PORT_DETECTED)
08d644ad 8311 intel_hdmi_init(dev, HDMIC, PORT_C);
30ad48b7 8312
b708a1d5 8313 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
08d644ad 8314 intel_hdmi_init(dev, HDMID, PORT_D);
30ad48b7 8315
5eb08b69 8316 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8317 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8318
270b3042 8319 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8320 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d
JB		 8321 } else if (IS_VALLEYVIEW(dev)) {
8322 int found;
8323
19c03924
GB		 8324 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8325 if (I915_READ(DP_C) & DP_DETECTED)
8326 intel_dp_init(dev, DP_C, PORT_C);
8327
4a87d65d
JB		 8328 if (I915_READ(SDVOB) & PORT_DETECTED) {
8329 /* SDVOB multiplex with HDMIB */
8330 found = intel_sdvo_init(dev, SDVOB, true);
8331 if (!found)
08d644ad 8332 intel_hdmi_init(dev, SDVOB, PORT_B);
4a87d65d 8333 if (!found && (I915_READ(DP_B) & DP_DETECTED))
ab9d7c30 8334 intel_dp_init(dev, DP_B, PORT_B);
4a87d65d
JB		 8335 }
8336
8337 if (I915_READ(SDVOC) & PORT_DETECTED)
08d644ad 8338 intel_hdmi_init(dev, SDVOC, PORT_C);
5eb08b69 8339
103a196f 8340 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8341 bool found = false;
7d57382e 8342
725e30ad 8343 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 8344 DRM_DEBUG_KMS("probing SDVOB\n");
eef4eacb 8345 found = intel_sdvo_init(dev, SDVOB, true);
b01f2c3a
JB		 8346 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8347 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
08d644ad 8348 intel_hdmi_init(dev, SDVOB, PORT_B);
b01f2c3a 8349 }
27185ae1 8350
b01f2c3a
JB		 8351 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8352 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 8353 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 8354 }
725e30ad 8355 }
13520b05
KH		 8356
8357 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8358
b01f2c3a
JB		 8359 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8360 DRM_DEBUG_KMS("probing SDVOC\n");
eef4eacb 8361 found = intel_sdvo_init(dev, SDVOC, false);
b01f2c3a 8362 }
27185ae1
ML		 8363
8364 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8365
b01f2c3a
JB		 8366 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8367 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
08d644ad 8368 intel_hdmi_init(dev, SDVOC, PORT_C);
b01f2c3a
JB		 8369 }
8370 if (SUPPORTS_INTEGRATED_DP(dev)) {
8371 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 8372 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 8373 }
725e30ad 8374 }
27185ae1 8375
b01f2c3a
JB		 8376 if (SUPPORTS_INTEGRATED_DP(dev) &&
8377 (I915_READ(DP_D) & DP_DETECTED)) {
8378 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 8379 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 8380 }
bad720ff 8381 } else if (IS_GEN2(dev))
79e53945
JB		 8382 intel_dvo_init(dev);
8383
103a196f 8384 if (SUPPORTS_TV(dev))
79e53945
JB		 8385 intel_tv_init(dev);
8386
4ef69c7a
CW		 8387 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8388 encoder->base.possible_crtcs = encoder->crtc_mask;
8389 encoder->base.possible_clones =
66a9278e 8390 intel_encoder_clones(encoder);
79e53945 8391 }
47356eb6 8392
40579abe 8393 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9fb526db 8394 ironlake_init_pch_refclk(dev);
270b3042
DV		 8395
8396 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8397}
8398
8399static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8400{
8401 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8402
8403 drm_framebuffer_cleanup(fb);
05394f39 8404 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8405
8406 kfree(intel_fb);
8407}
8408
8409static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8410 struct drm_file *file,
79e53945
JB		 8411 unsigned int *handle)
8412{
8413 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8414 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8415
05394f39 8416 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8417}
8418
8419static const struct drm_framebuffer_funcs intel_fb_funcs = {
8420 .destroy = intel_user_framebuffer_destroy,
8421 .create_handle = intel_user_framebuffer_create_handle,
8422};
8423
38651674
DA		 8424int intel_framebuffer_init(struct drm_device *dev,
8425 struct intel_framebuffer *intel_fb,
308e5bcb 8426 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8427 struct drm_i915_gem_object *obj)
79e53945 8428{
79e53945
JB		 8429 int ret;
8430
05394f39 8431 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 8432 return -EINVAL;
8433
308e5bcb 8434 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 8435 return -EINVAL;
8436
5d7bd705
VS		 8437 /* FIXME <= Gen4 stride limits are bit unclear */
8438 if (mode_cmd->pitches[0] > 32768)
8439 return -EINVAL;
8440
8441 if (obj->tiling_mode != I915_TILING_NONE &&
8442 mode_cmd->pitches[0] != obj->stride)
8443 return -EINVAL;
8444
57779d06 8445 /* Reject formats not supported by any plane early. */
308e5bcb 8446 switch (mode_cmd->pixel_format) {
57779d06 8447 case DRM_FORMAT_C8:
04b3924d
VS		 8448 case DRM_FORMAT_RGB565:
8449 case DRM_FORMAT_XRGB8888:
8450 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8451 break;
8452 case DRM_FORMAT_XRGB1555:
8453 case DRM_FORMAT_ARGB1555:
8454 if (INTEL_INFO(dev)->gen > 3)
8455 return -EINVAL;
8456 break;
8457 case DRM_FORMAT_XBGR8888:
8458 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8459 case DRM_FORMAT_XRGB2101010:
8460 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8461 case DRM_FORMAT_XBGR2101010:
8462 case DRM_FORMAT_ABGR2101010:
8463 if (INTEL_INFO(dev)->gen < 4)
8464 return -EINVAL;
b5626747 8465 break;
04b3924d
VS		 8466 case DRM_FORMAT_YUYV:
8467 case DRM_FORMAT_UYVY:
8468 case DRM_FORMAT_YVYU:
8469 case DRM_FORMAT_VYUY:
57779d06
VS		 8470 if (INTEL_INFO(dev)->gen < 6)
8471 return -EINVAL;
57cd6508
CW		 8472 break;
8473 default:
57779d06 8474 DRM_DEBUG_KMS("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8475 return -EINVAL;
8476 }
8477
90f9a336
VS		 8478 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8479 if (mode_cmd->offsets[0] != 0)
8480 return -EINVAL;
8481
79e53945
JB		 8482 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8483 if (ret) {
8484 DRM_ERROR("framebuffer init failed %d\n", ret);
8485 return ret;
8486 }
8487
8488 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 8489 intel_fb->obj = obj;
79e53945
JB		 8490 return 0;
8491}
8492
79e53945
JB		 8493static struct drm_framebuffer *
8494intel_user_framebuffer_create(struct drm_device *dev,
8495 struct drm_file *filp,
308e5bcb 8496 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8497{
05394f39 8498 struct drm_i915_gem_object *obj;
79e53945 8499
308e5bcb
JB		 8500 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8501 mode_cmd->handles[0]));
c8725226 8502 if (&obj->base == NULL)
cce13ff7 8503 return ERR_PTR(-ENOENT);
79e53945 8504
d2dff872 8505 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8506}
8507
79e53945 8508static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8509 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8510 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8511};
8512
e70236a8
JB		 8513/* Set up chip specific display functions */
8514static void intel_init_display(struct drm_device *dev)
8515{
8516 struct drm_i915_private *dev_priv = dev->dev_private;
8517
8518 /* We always want a DPMS function */
09b4ddf9
PZ		 8519 if (IS_HASWELL(dev)) {
8520 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8521 dev_priv->display.crtc_enable = haswell_crtc_enable;
8522 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 8523 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 8524 dev_priv->display.update_plane = ironlake_update_plane;
8525 } else if (HAS_PCH_SPLIT(dev)) {
f564048e 8526 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 8527 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8528 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8529 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8530 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8531 } else {
f564048e 8532 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 8533 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8534 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8535 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8536 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8537 }
e70236a8 8538
e70236a8 8539 /* Returns the core display clock speed */
25eb05fc
JB		 8540 if (IS_VALLEYVIEW(dev))
8541 dev_priv->display.get_display_clock_speed =
8542 valleyview_get_display_clock_speed;
8543 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8544 dev_priv->display.get_display_clock_speed =
8545 i945_get_display_clock_speed;
8546 else if (IS_I915G(dev))
8547 dev_priv->display.get_display_clock_speed =
8548 i915_get_display_clock_speed;
f2b115e6 8549 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8550 dev_priv->display.get_display_clock_speed =
8551 i9xx_misc_get_display_clock_speed;
8552 else if (IS_I915GM(dev))
8553 dev_priv->display.get_display_clock_speed =
8554 i915gm_get_display_clock_speed;
8555 else if (IS_I865G(dev))
8556 dev_priv->display.get_display_clock_speed =
8557 i865_get_display_clock_speed;
f0f8a9ce 8558 else if (IS_I85X(dev))
e70236a8
JB		 8559 dev_priv->display.get_display_clock_speed =
8560 i855_get_display_clock_speed;
8561 else /* 852, 830 */
8562 dev_priv->display.get_display_clock_speed =
8563 i830_get_display_clock_speed;
8564
7f8a8569 8565 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8566 if (IS_GEN5(dev)) {
674cf967 8567 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8568 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8569 } else if (IS_GEN6(dev)) {
674cf967 8570 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8571 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8572 } else if (IS_IVYBRIDGE(dev)) {
8573 /* FIXME: detect B0+ stepping and use auto training */
8574 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 8575 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 8576 dev_priv->display.modeset_global_resources =
8577 ivb_modeset_global_resources;
c82e4d26
ED		 8578 } else if (IS_HASWELL(dev)) {
8579 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 8580 dev_priv->display.write_eld = haswell_write_eld;
7f8a8569
ZW		 8581 } else
8582 dev_priv->display.update_wm = NULL;
6067aaea 8583 } else if (IS_G4X(dev)) {
e0dac65e 8584 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8585 }
8c9f3aaf
JB		 8586
8587 /* Default just returns -ENODEV to indicate unsupported */
8588 dev_priv->display.queue_flip = intel_default_queue_flip;
8589
8590 switch (INTEL_INFO(dev)->gen) {
8591 case 2:
8592 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8593 break;
8594
8595 case 3:
8596 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8597 break;
8598
8599 case 4:
8600 case 5:
8601 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8602 break;
8603
8604 case 6:
8605 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8606 break;
7c9017e5
JB		 8607 case 7:
8608 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8609 break;
8c9f3aaf 8610 }
e70236a8
JB		 8611}
8612
b690e96c
JB		 8613/*
8614 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8615 * resume, or other times. This quirk makes sure that's the case for
8616 * affected systems.
8617 */
0206e353 8618static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8619{
8620 struct drm_i915_private *dev_priv = dev->dev_private;
8621
8622 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 8623 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 8624}
8625
435793df
KP		 8626/*
8627 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8628 */
8629static void quirk_ssc_force_disable(struct drm_device *dev)
8630{
8631 struct drm_i915_private *dev_priv = dev->dev_private;
8632 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 8633 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 8634}
8635
4dca20ef 8636/*
5a15ab5b
CE		 8637 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8638 * brightness value
4dca20ef
CE		 8639 */
8640static void quirk_invert_brightness(struct drm_device *dev)
8641{
8642 struct drm_i915_private *dev_priv = dev->dev_private;
8643 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 8644 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 8645}
8646
b690e96c
JB		 8647struct intel_quirk {
8648 int device;
8649 int subsystem_vendor;
8650 int subsystem_device;
8651 void (*hook)(struct drm_device *dev);
8652};
8653
5f85f176
EE		 8654/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8655struct intel_dmi_quirk {
8656 void (*hook)(struct drm_device *dev);
8657 const struct dmi_system_id (*dmi_id_list)[];
8658};
8659
8660static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8661{
8662 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8663 return 1;
8664}
8665
8666static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8667 {
8668 .dmi_id_list = &(const struct dmi_system_id[]) {
8669 {
8670 .callback = intel_dmi_reverse_brightness,
8671 .ident = "NCR Corporation",
8672 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8673 DMI_MATCH(DMI_PRODUCT_NAME, ""),
8674 },
8675 },
8676 { } /* terminating entry */
8677 },
8678 .hook = quirk_invert_brightness,
8679 },
8680};
8681
c43b5634 8682static struct intel_quirk intel_quirks[] = {
b690e96c 8683 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8684 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 8685
b690e96c
JB		 8686 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8687 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8688
b690e96c
JB		 8689 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8690 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8691
ccd0d36e 8692 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 8693 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 8694 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 8695
8696 /* Lenovo U160 cannot use SSC on LVDS */
8697 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 8698
8699 /* Sony Vaio Y cannot use SSC on LVDS */
8700 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 8701
8702 /* Acer Aspire 5734Z must invert backlight brightness */
8703 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
b690e96c
JB		 8704};
8705
8706static void intel_init_quirks(struct drm_device *dev)
8707{
8708 struct pci_dev *d = dev->pdev;
8709 int i;
8710
8711 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8712 struct intel_quirk *q = &intel_quirks[i];
8713
8714 if (d->device == q->device &&
8715 (d->subsystem_vendor == q->subsystem_vendor ||
8716 q->subsystem_vendor == PCI_ANY_ID) &&
8717 (d->subsystem_device == q->subsystem_device ||
8718 q->subsystem_device == PCI_ANY_ID))
8719 q->hook(dev);
8720 }
5f85f176
EE		 8721 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8722 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8723 intel_dmi_quirks[i].hook(dev);
8724 }
b690e96c
JB		 8725}
8726
9cce37f4
JB		 8727/* Disable the VGA plane that we never use */
8728static void i915_disable_vga(struct drm_device *dev)
8729{
8730 struct drm_i915_private *dev_priv = dev->dev_private;
8731 u8 sr1;
8732 u32 vga_reg;
8733
8734 if (HAS_PCH_SPLIT(dev))
8735 vga_reg = CPU_VGACNTRL;
8736 else
8737 vga_reg = VGACNTRL;
8738
8739 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 8740 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 8741 sr1 = inb(VGA_SR_DATA);
8742 outb(sr1 | 1<<5, VGA_SR_DATA);
8743 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8744 udelay(300);
8745
8746 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8747 POSTING_READ(vga_reg);
8748}
8749
f817586c
DV		 8750void intel_modeset_init_hw(struct drm_device *dev)
8751{
0232e927
ED		 8752 /* We attempt to init the necessary power wells early in the initialization
8753 * time, so the subsystems that expect power to be enabled can work.
8754 */
8755 intel_init_power_wells(dev);
8756
a8f78b58
ED		 8757 intel_prepare_ddi(dev);
8758
f817586c
DV		 8759 intel_init_clock_gating(dev);
8760
79f5b2c7 8761 mutex_lock(&dev->struct_mutex);
8090c6b9 8762 intel_enable_gt_powersave(dev);
79f5b2c7 8763 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 8764}
8765
79e53945
JB		 8766void intel_modeset_init(struct drm_device *dev)
8767{
652c393a 8768 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 8769 int i, ret;
79e53945
JB		 8770
8771 drm_mode_config_init(dev);
8772
8773 dev->mode_config.min_width = 0;
8774 dev->mode_config.min_height = 0;
8775
019d96cb
DA		 8776 dev->mode_config.preferred_depth = 24;
8777 dev->mode_config.prefer_shadow = 1;
8778
e6ecefaa 8779 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 8780
b690e96c
JB		 8781 intel_init_quirks(dev);
8782
1fa61106
ED		 8783 intel_init_pm(dev);
8784
e70236a8
JB		 8785 intel_init_display(dev);
8786
a6c45cf0
CW		 8787 if (IS_GEN2(dev)) {
8788 dev->mode_config.max_width = 2048;
8789 dev->mode_config.max_height = 2048;
8790 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 8791 dev->mode_config.max_width = 4096;
8792 dev->mode_config.max_height = 4096;
79e53945 8793 } else {
a6c45cf0
CW		 8794 dev->mode_config.max_width = 8192;
8795 dev->mode_config.max_height = 8192;
79e53945 8796 }
dd2757f8 8797 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
79e53945 8798
28c97730 8799 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 8800 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 8801
a3524f1b 8802 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 8803 intel_crtc_init(dev, i);
00c2064b
JB		 8804 ret = intel_plane_init(dev, i);
8805 if (ret)
8806 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 8807 }
8808
79f689aa 8809 intel_cpu_pll_init(dev);
ee7b9f93
JB		 8810 intel_pch_pll_init(dev);
8811
9cce37f4
JB		 8812 /* Just disable it once at startup */
8813 i915_disable_vga(dev);
79e53945 8814 intel_setup_outputs(dev);
2c7111db
CW		 8815}
8816
24929352
DV		 8817static void
8818intel_connector_break_all_links(struct intel_connector *connector)
8819{
8820 connector->base.dpms = DRM_MODE_DPMS_OFF;
8821 connector->base.encoder = NULL;
8822 connector->encoder->connectors_active = false;
8823 connector->encoder->base.crtc = NULL;
8824}
8825
7fad798e
DV		 8826static void intel_enable_pipe_a(struct drm_device *dev)
8827{
8828 struct intel_connector *connector;
8829 struct drm_connector *crt = NULL;
8830 struct intel_load_detect_pipe load_detect_temp;
8831
8832 /* We can't just switch on the pipe A, we need to set things up with a
8833 * proper mode and output configuration. As a gross hack, enable pipe A
8834 * by enabling the load detect pipe once. */
8835 list_for_each_entry(connector,
8836 &dev->mode_config.connector_list,
8837 base.head) {
8838 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8839 crt = &connector->base;
8840 break;
8841 }
8842 }
8843
8844 if (!crt)
8845 return;
8846
8847 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8848 intel_release_load_detect_pipe(crt, &load_detect_temp);
8849
652c393a 8850
7fad798e
DV		 8851}
8852
fa555837
DV		 8853static bool
8854intel_check_plane_mapping(struct intel_crtc *crtc)
8855{
8856 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8857 u32 reg, val;
8858
8859 if (dev_priv->num_pipe == 1)
8860 return true;
8861
8862 reg = DSPCNTR(!crtc->plane);
8863 val = I915_READ(reg);
8864
8865 if ((val & DISPLAY_PLANE_ENABLE) &&
8866 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8867 return false;
8868
8869 return true;
8870}
8871
24929352
DV		 8872static void intel_sanitize_crtc(struct intel_crtc *crtc)
8873{
8874 struct drm_device *dev = crtc->base.dev;
8875 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 8876 u32 reg;
24929352 8877
24929352 8878 /* Clear any frame start delays used for debugging left by the BIOS */
702e7a56 8879 reg = PIPECONF(crtc->cpu_transcoder);
24929352
DV		 8880 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8881
8882 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 8883 * disable the crtc (and hence change the state) if it is wrong. Note
8884 * that gen4+ has a fixed plane -> pipe mapping. */
8885 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 8886 struct intel_connector *connector;
8887 bool plane;
8888
24929352
DV		 8889 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8890 crtc->base.base.id);
8891
8892 /* Pipe has the wrong plane attached and the plane is active.
8893 * Temporarily change the plane mapping and disable everything
8894 * ... */
8895 plane = crtc->plane;
8896 crtc->plane = !plane;
8897 dev_priv->display.crtc_disable(&crtc->base);
8898 crtc->plane = plane;
8899
8900 /* ... and break all links. */
8901 list_for_each_entry(connector, &dev->mode_config.connector_list,
8902 base.head) {
8903 if (connector->encoder->base.crtc != &crtc->base)
8904 continue;
8905
8906 intel_connector_break_all_links(connector);
8907 }
8908
8909 WARN_ON(crtc->active);
8910 crtc->base.enabled = false;
8911 }
24929352 8912
7fad798e
DV		 8913 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8914 crtc->pipe == PIPE_A && !crtc->active) {
8915 /* BIOS forgot to enable pipe A, this mostly happens after
8916 * resume. Force-enable the pipe to fix this, the update_dpms
8917 * call below we restore the pipe to the right state, but leave
8918 * the required bits on. */
8919 intel_enable_pipe_a(dev);
8920 }
8921
24929352
DV		 8922 /* Adjust the state of the output pipe according to whether we
8923 * have active connectors/encoders. */
8924 intel_crtc_update_dpms(&crtc->base);
8925
8926 if (crtc->active != crtc->base.enabled) {
8927 struct intel_encoder *encoder;
8928
8929 /* This can happen either due to bugs in the get_hw_state
8930 * functions or because the pipe is force-enabled due to the
8931 * pipe A quirk. */
8932 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8933 crtc->base.base.id,
8934 crtc->base.enabled ? "enabled" : "disabled",
8935 crtc->active ? "enabled" : "disabled");
8936
8937 crtc->base.enabled = crtc->active;
8938
8939 /* Because we only establish the connector -> encoder ->
8940 * crtc links if something is active, this means the
8941 * crtc is now deactivated. Break the links. connector
8942 * -> encoder links are only establish when things are
8943 * actually up, hence no need to break them. */
8944 WARN_ON(crtc->active);
8945
8946 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8947 WARN_ON(encoder->connectors_active);
8948 encoder->base.crtc = NULL;
8949 }
8950 }
8951}
8952
8953static void intel_sanitize_encoder(struct intel_encoder *encoder)
8954{
8955 struct intel_connector *connector;
8956 struct drm_device *dev = encoder->base.dev;
8957
8958 /* We need to check both for a crtc link (meaning that the
8959 * encoder is active and trying to read from a pipe) and the
8960 * pipe itself being active. */
8961 bool has_active_crtc = encoder->base.crtc &&
8962 to_intel_crtc(encoder->base.crtc)->active;
8963
8964 if (encoder->connectors_active && !has_active_crtc) {
8965 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8966 encoder->base.base.id,
8967 drm_get_encoder_name(&encoder->base));
8968
8969 /* Connector is active, but has no active pipe. This is
8970 * fallout from our resume register restoring. Disable
8971 * the encoder manually again. */
8972 if (encoder->base.crtc) {
8973 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8974 encoder->base.base.id,
8975 drm_get_encoder_name(&encoder->base));
8976 encoder->disable(encoder);
8977 }
8978
8979 /* Inconsistent output/port/pipe state happens presumably due to
8980 * a bug in one of the get_hw_state functions. Or someplace else
8981 * in our code, like the register restore mess on resume. Clamp
8982 * things to off as a safer default. */
8983 list_for_each_entry(connector,
8984 &dev->mode_config.connector_list,
8985 base.head) {
8986 if (connector->encoder != encoder)
8987 continue;
8988
8989 intel_connector_break_all_links(connector);
8990 }
8991 }
8992 /* Enabled encoders without active connectors will be fixed in
8993 * the crtc fixup. */
8994}
8995
8996/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8997 * and i915 state tracking structures. */
45e2b5f6
DV		 8998void intel_modeset_setup_hw_state(struct drm_device *dev,
8999 bool force_restore)
24929352
DV		 9000{
9001 struct drm_i915_private *dev_priv = dev->dev_private;
9002 enum pipe pipe;
9003 u32 tmp;
9004 struct intel_crtc *crtc;
9005 struct intel_encoder *encoder;
9006 struct intel_connector *connector;
9007
e28d54cb
PZ		 9008 if (IS_HASWELL(dev)) {
9009 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9010
9011 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9012 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9013 case TRANS_DDI_EDP_INPUT_A_ON:
9014 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9015 pipe = PIPE_A;
9016 break;
9017 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9018 pipe = PIPE_B;
9019 break;
9020 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9021 pipe = PIPE_C;
9022 break;
9023 }
9024
9025 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9026 crtc->cpu_transcoder = TRANSCODER_EDP;
9027
9028 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9029 pipe_name(pipe));
9030 }
9031 }
9032
24929352
DV		 9033 for_each_pipe(pipe) {
9034 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9035
702e7a56 9036 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
24929352
DV		 9037 if (tmp & PIPECONF_ENABLE)
9038 crtc->active = true;
9039 else
9040 crtc->active = false;
9041
9042 crtc->base.enabled = crtc->active;
9043
9044 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9045 crtc->base.base.id,
9046 crtc->active ? "enabled" : "disabled");
9047 }
9048
6441ab5f
PZ		 9049 if (IS_HASWELL(dev))
9050 intel_ddi_setup_hw_pll_state(dev);
9051
24929352
DV		 9052 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9053 base.head) {
9054 pipe = 0;
9055
9056 if (encoder->get_hw_state(encoder, &pipe)) {
9057 encoder->base.crtc =
9058 dev_priv->pipe_to_crtc_mapping[pipe];
9059 } else {
9060 encoder->base.crtc = NULL;
9061 }
9062
9063 encoder->connectors_active = false;
9064 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9065 encoder->base.base.id,
9066 drm_get_encoder_name(&encoder->base),
9067 encoder->base.crtc ? "enabled" : "disabled",
9068 pipe);
9069 }
9070
9071 list_for_each_entry(connector, &dev->mode_config.connector_list,
9072 base.head) {
9073 if (connector->get_hw_state(connector)) {
9074 connector->base.dpms = DRM_MODE_DPMS_ON;
9075 connector->encoder->connectors_active = true;
9076 connector->base.encoder = &connector->encoder->base;
9077 } else {
9078 connector->base.dpms = DRM_MODE_DPMS_OFF;
9079 connector->base.encoder = NULL;
9080 }
9081 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9082 connector->base.base.id,
9083 drm_get_connector_name(&connector->base),
9084 connector->base.encoder ? "enabled" : "disabled");
9085 }
9086
9087 /* HW state is read out, now we need to sanitize this mess. */
9088 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9089 base.head) {
9090 intel_sanitize_encoder(encoder);
9091 }
9092
9093 for_each_pipe(pipe) {
9094 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9095 intel_sanitize_crtc(crtc);
9096 }
9a935856 9097
45e2b5f6
DV		 9098 if (force_restore) {
9099 for_each_pipe(pipe) {
9100 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9101 intel_set_mode(&crtc->base, &crtc->base.mode,
9102 crtc->base.x, crtc->base.y, crtc->base.fb);
9103 }
9104 } else {
9105 intel_modeset_update_staged_output_state(dev);
9106 }
8af6cf88
DV		 9107
9108 intel_modeset_check_state(dev);
2e938892
DV		 9109
9110 drm_mode_config_reset(dev);
2c7111db
CW		 9111}
9112
9113void intel_modeset_gem_init(struct drm_device *dev)
9114{
1833b134 9115 intel_modeset_init_hw(dev);
02e792fb
DV		 9116
9117 intel_setup_overlay(dev);
24929352 9118
45e2b5f6 9119 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9120}
9121
9122void intel_modeset_cleanup(struct drm_device *dev)
9123{
652c393a
JB		 9124 struct drm_i915_private *dev_priv = dev->dev_private;
9125 struct drm_crtc *crtc;
9126 struct intel_crtc *intel_crtc;
9127
f87ea761 9128 drm_kms_helper_poll_fini(dev);
652c393a
JB		 9129 mutex_lock(&dev->struct_mutex);
9130
723bfd70
JB		 9131 intel_unregister_dsm_handler();
9132
9133
652c393a
JB		 9134 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9135 /* Skip inactive CRTCs */
9136 if (!crtc->fb)
9137 continue;
9138
9139 intel_crtc = to_intel_crtc(crtc);
3dec0095 9140 intel_increase_pllclock(crtc);
652c393a
JB		 9141 }
9142
973d04f9 9143 intel_disable_fbc(dev);
e70236a8 9144
8090c6b9 9145 intel_disable_gt_powersave(dev);
0cdab21f 9146
930ebb46
DV		 9147 ironlake_teardown_rc6(dev);
9148
57f350b6
JB		 9149 if (IS_VALLEYVIEW(dev))
9150 vlv_init_dpio(dev);
9151
69341a5e
KH		 9152 mutex_unlock(&dev->struct_mutex);
9153
6c0d9350
DV		 9154 /* Disable the irq before mode object teardown, for the irq might
9155 * enqueue unpin/hotplug work. */
9156 drm_irq_uninstall(dev);
9157 cancel_work_sync(&dev_priv->hotplug_work);
c6a828d3 9158 cancel_work_sync(&dev_priv->rps.work);
6c0d9350 9159
1630fe75
CW		 9160 /* flush any delayed tasks or pending work */
9161 flush_scheduled_work();
9162
79e53945
JB		 9163 drm_mode_config_cleanup(dev);
9164}
9165
f1c79df3
ZW		 9166/*
9167 * Return which encoder is currently attached for connector.
9168 */
df0e9248 9169struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9170{
df0e9248
CW		 9171 return &intel_attached_encoder(connector)->base;
9172}
f1c79df3 9173
df0e9248
CW		 9174void intel_connector_attach_encoder(struct intel_connector *connector,
9175 struct intel_encoder *encoder)
9176{
9177 connector->encoder = encoder;
9178 drm_mode_connector_attach_encoder(&connector->base,
9179 &encoder->base);
79e53945 9180}
28d52043
DA		 9181
9182/*
9183 * set vga decode state - true == enable VGA decode
9184 */
9185int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9186{
9187 struct drm_i915_private *dev_priv = dev->dev_private;
9188 u16 gmch_ctrl;
9189
9190 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9191 if (state)
9192 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9193 else
9194 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9195 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9196 return 0;
9197}
c4a1d9e4
CW		 9198
9199#ifdef CONFIG_DEBUG_FS
9200#include <linux/seq_file.h>
9201
9202struct intel_display_error_state {
9203 struct intel_cursor_error_state {
9204 u32 control;
9205 u32 position;
9206 u32 base;
9207 u32 size;
52331309 9208 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9209
9210 struct intel_pipe_error_state {
9211 u32 conf;
9212 u32 source;
9213
9214 u32 htotal;
9215 u32 hblank;
9216 u32 hsync;
9217 u32 vtotal;
9218 u32 vblank;
9219 u32 vsync;
52331309 9220 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9221
9222 struct intel_plane_error_state {
9223 u32 control;
9224 u32 stride;
9225 u32 size;
9226 u32 pos;
9227 u32 addr;
9228 u32 surface;
9229 u32 tile_offset;
52331309 9230 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9231};
9232
9233struct intel_display_error_state *
9234intel_display_capture_error_state(struct drm_device *dev)
9235{
0206e353 9236 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9237 struct intel_display_error_state *error;
702e7a56 9238 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9239 int i;
9240
9241 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9242 if (error == NULL)
9243 return NULL;
9244
52331309 9245 for_each_pipe(i) {
702e7a56
PZ		 9246 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9247
c4a1d9e4
CW		 9248 error->cursor[i].control = I915_READ(CURCNTR(i));
9249 error->cursor[i].position = I915_READ(CURPOS(i));
9250 error->cursor[i].base = I915_READ(CURBASE(i));
9251
9252 error->plane[i].control = I915_READ(DSPCNTR(i));
9253 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9254 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 9255 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 9256 error->plane[i].addr = I915_READ(DSPADDR(i));
9257 if (INTEL_INFO(dev)->gen >= 4) {
9258 error->plane[i].surface = I915_READ(DSPSURF(i));
9259 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9260 }
9261
702e7a56 9262 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9263 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9264 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9265 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9266 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9267 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9268 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9269 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9270 }
9271
9272 return error;
9273}
9274
9275void
9276intel_display_print_error_state(struct seq_file *m,
9277 struct drm_device *dev,
9278 struct intel_display_error_state *error)
9279{
52331309 9280 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 9281 int i;
9282
52331309
DL		 9283 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9284 for_each_pipe(i) {
c4a1d9e4
CW		 9285 seq_printf(m, "Pipe [%d]:\n", i);
9286 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9287 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9288 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9289 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9290 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9291 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9292 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9293 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9294
9295 seq_printf(m, "Plane [%d]:\n", i);
9296 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9297 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9298 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9299 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9300 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9301 if (INTEL_INFO(dev)->gen >= 4) {
9302 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9303 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9304 }
9305
9306 seq_printf(m, "Cursor [%d]:\n", i);
9307 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9308 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9309 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9310 }
9311}
9312#endif
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