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drm/i915: add i9xx pfit pipe asserts
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 47
48typedef struct {
0206e353
AJ		 49 /* given values */
50 int n;
51 int m1, m2;
52 int p1, p2;
53 /* derived values */
54 int dot;
55 int vco;
56 int m;
57 int p;
79e53945
JB		 58} intel_clock_t;
59
60typedef struct {
0206e353 61 int min, max;
79e53945
JB		 62} intel_range_t;
63
64typedef struct {
0206e353
AJ		 65 int dot_limit;
66 int p2_slow, p2_fast;
79e53945
JB		 67} intel_p2_t;
68
69#define INTEL_P2_NUM 2
d4906093
ML		 70typedef struct intel_limit intel_limit_t;
71struct intel_limit {
0206e353
AJ		 72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
73 intel_p2_t p2;
f4808ab8
VS		 74 /**
75 * find_pll() - Find the best values for the PLL
76 * @limit: limits for the PLL
77 * @crtc: current CRTC
78 * @target: target frequency in kHz
79 * @refclk: reference clock frequency in kHz
80 * @match_clock: if provided, @best_clock P divider must
81 * match the P divider from @match_clock
82 * used for LVDS downclocking
83 * @best_clock: best PLL values found
84 *
85 * Returns true on success, false on failure.
86 */
87 bool (*find_pll)(const intel_limit_t *limit,
88 struct drm_crtc *crtc,
89 int target, int refclk,
90 intel_clock_t *match_clock,
91 intel_clock_t *best_clock);
d4906093 92};
79e53945 93
2377b741
JB		 94/* FDI */
95#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
96
d2acd215
DV		 97int
98intel_pch_rawclk(struct drm_device *dev)
99{
100 struct drm_i915_private *dev_priv = dev->dev_private;
101
102 WARN_ON(!HAS_PCH_SPLIT(dev));
103
104 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
105}
106
d4906093
ML		 107static bool
108intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 109 int target, int refclk, intel_clock_t *match_clock,
110 intel_clock_t *best_clock);
d4906093
ML		 111static bool
112intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 113 int target, int refclk, intel_clock_t *match_clock,
114 intel_clock_t *best_clock);
79e53945 115
a4fc5ed6
KP		 116static bool
117intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 118 int target, int refclk, intel_clock_t *match_clock,
119 intel_clock_t *best_clock);
5eb08b69 120static bool
f2b115e6 121intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 122 int target, int refclk, intel_clock_t *match_clock,
123 intel_clock_t *best_clock);
a4fc5ed6 124
a0c4da24
JB		 125static bool
126intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
127 int target, int refclk, intel_clock_t *match_clock,
128 intel_clock_t *best_clock);
129
021357ac
CW		 130static inline u32 /* units of 100MHz */
131intel_fdi_link_freq(struct drm_device *dev)
132{
8b99e68c
CW		 133 if (IS_GEN5(dev)) {
134 struct drm_i915_private *dev_priv = dev->dev_private;
135 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
136 } else
137 return 27;
021357ac
CW		 138}
139
e4b36699 140static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 141 .dot = { .min = 25000, .max = 350000 },
142 .vco = { .min = 930000, .max = 1400000 },
143 .n = { .min = 3, .max = 16 },
144 .m = { .min = 96, .max = 140 },
145 .m1 = { .min = 18, .max = 26 },
146 .m2 = { .min = 6, .max = 16 },
147 .p = { .min = 4, .max = 128 },
148 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 149 .p2 = { .dot_limit = 165000,
150 .p2_slow = 4, .p2_fast = 2 },
d4906093 151 .find_pll = intel_find_best_PLL,
e4b36699
KP		 152};
153
154static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 155 .dot = { .min = 25000, .max = 350000 },
156 .vco = { .min = 930000, .max = 1400000 },
157 .n = { .min = 3, .max = 16 },
158 .m = { .min = 96, .max = 140 },
159 .m1 = { .min = 18, .max = 26 },
160 .m2 = { .min = 6, .max = 16 },
161 .p = { .min = 4, .max = 128 },
162 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 163 .p2 = { .dot_limit = 165000,
164 .p2_slow = 14, .p2_fast = 7 },
d4906093 165 .find_pll = intel_find_best_PLL,
e4b36699 166};
273e27ca 167
e4b36699 168static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 169 .dot = { .min = 20000, .max = 400000 },
170 .vco = { .min = 1400000, .max = 2800000 },
171 .n = { .min = 1, .max = 6 },
172 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 173 .m1 = { .min = 8, .max = 18 },
174 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 175 .p = { .min = 5, .max = 80 },
176 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 177 .p2 = { .dot_limit = 200000,
178 .p2_slow = 10, .p2_fast = 5 },
d4906093 179 .find_pll = intel_find_best_PLL,
e4b36699
KP		 180};
181
182static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 183 .dot = { .min = 20000, .max = 400000 },
184 .vco = { .min = 1400000, .max = 2800000 },
185 .n = { .min = 1, .max = 6 },
186 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 187 .m1 = { .min = 8, .max = 18 },
188 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 189 .p = { .min = 7, .max = 98 },
190 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 191 .p2 = { .dot_limit = 112000,
192 .p2_slow = 14, .p2_fast = 7 },
d4906093 193 .find_pll = intel_find_best_PLL,
e4b36699
KP		 194};
195
273e27ca 196
e4b36699 197static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 198 .dot = { .min = 25000, .max = 270000 },
199 .vco = { .min = 1750000, .max = 3500000},
200 .n = { .min = 1, .max = 4 },
201 .m = { .min = 104, .max = 138 },
202 .m1 = { .min = 17, .max = 23 },
203 .m2 = { .min = 5, .max = 11 },
204 .p = { .min = 10, .max = 30 },
205 .p1 = { .min = 1, .max = 3},
206 .p2 = { .dot_limit = 270000,
207 .p2_slow = 10,
208 .p2_fast = 10
044c7c41 209 },
d4906093 210 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 211};
212
213static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 214 .dot = { .min = 22000, .max = 400000 },
215 .vco = { .min = 1750000, .max = 3500000},
216 .n = { .min = 1, .max = 4 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 16, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 5, .max = 80 },
221 .p1 = { .min = 1, .max = 8},
222 .p2 = { .dot_limit = 165000,
223 .p2_slow = 10, .p2_fast = 5 },
d4906093 224 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 225};
226
227static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 228 .dot = { .min = 20000, .max = 115000 },
229 .vco = { .min = 1750000, .max = 3500000 },
230 .n = { .min = 1, .max = 3 },
231 .m = { .min = 104, .max = 138 },
232 .m1 = { .min = 17, .max = 23 },
233 .m2 = { .min = 5, .max = 11 },
234 .p = { .min = 28, .max = 112 },
235 .p1 = { .min = 2, .max = 8 },
236 .p2 = { .dot_limit = 0,
237 .p2_slow = 14, .p2_fast = 14
044c7c41 238 },
d4906093 239 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 240};
241
242static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 243 .dot = { .min = 80000, .max = 224000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 14, .max = 42 },
250 .p1 = { .min = 2, .max = 6 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 7, .p2_fast = 7
044c7c41 253 },
d4906093 254 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 255};
256
257static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 258 .dot = { .min = 161670, .max = 227000 },
259 .vco = { .min = 1750000, .max = 3500000},
260 .n = { .min = 1, .max = 2 },
261 .m = { .min = 97, .max = 108 },
262 .m1 = { .min = 0x10, .max = 0x12 },
263 .m2 = { .min = 0x05, .max = 0x06 },
264 .p = { .min = 10, .max = 20 },
265 .p1 = { .min = 1, .max = 2},
266 .p2 = { .dot_limit = 0,
273e27ca 267 .p2_slow = 10, .p2_fast = 10 },
0206e353 268 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 269};
270
f2b115e6 271static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 272 .dot = { .min = 20000, .max = 400000},
273 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 274 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 275 .n = { .min = 3, .max = 6 },
276 .m = { .min = 2, .max = 256 },
273e27ca 277 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 278 .m1 = { .min = 0, .max = 0 },
279 .m2 = { .min = 0, .max = 254 },
280 .p = { .min = 5, .max = 80 },
281 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 282 .p2 = { .dot_limit = 200000,
283 .p2_slow = 10, .p2_fast = 5 },
6115707b 284 .find_pll = intel_find_best_PLL,
e4b36699
KP		 285};
286
f2b115e6 287static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 288 .dot = { .min = 20000, .max = 400000 },
289 .vco = { .min = 1700000, .max = 3500000 },
290 .n = { .min = 3, .max = 6 },
291 .m = { .min = 2, .max = 256 },
292 .m1 = { .min = 0, .max = 0 },
293 .m2 = { .min = 0, .max = 254 },
294 .p = { .min = 7, .max = 112 },
295 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 296 .p2 = { .dot_limit = 112000,
297 .p2_slow = 14, .p2_fast = 14 },
6115707b 298 .find_pll = intel_find_best_PLL,
e4b36699
KP		 299};
300
273e27ca
EA		 301/* Ironlake / Sandybridge
302 *
303 * We calculate clock using (register_value + 2) for N/M1/M2, so here
304 * the range value for them is (actual_value - 2).
305 */
b91ad0ec 306static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 5 },
310 .m = { .min = 79, .max = 127 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 5, .max = 80 },
314 .p1 = { .min = 1, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 10, .p2_fast = 5 },
4547668a 317 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 318};
319
b91ad0ec 320static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 79, .max = 118 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 28, .max = 112 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 331 .find_pll = intel_g4x_find_best_PLL,
332};
333
334static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 335 .dot = { .min = 25000, .max = 350000 },
336 .vco = { .min = 1760000, .max = 3510000 },
337 .n = { .min = 1, .max = 3 },
338 .m = { .min = 79, .max = 127 },
339 .m1 = { .min = 12, .max = 22 },
340 .m2 = { .min = 5, .max = 9 },
341 .p = { .min = 14, .max = 56 },
342 .p1 = { .min = 2, .max = 8 },
343 .p2 = { .dot_limit = 225000,
344 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 345 .find_pll = intel_g4x_find_best_PLL,
346};
347
273e27ca 348/* LVDS 100mhz refclk limits. */
b91ad0ec 349static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000 },
352 .n = { .min = 1, .max = 2 },
353 .m = { .min = 79, .max = 126 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 28, .max = 112 },
0206e353 357 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 358 .p2 = { .dot_limit = 225000,
359 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 360 .find_pll = intel_g4x_find_best_PLL,
361};
362
363static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 364 .dot = { .min = 25000, .max = 350000 },
365 .vco = { .min = 1760000, .max = 3510000 },
366 .n = { .min = 1, .max = 3 },
367 .m = { .min = 79, .max = 126 },
368 .m1 = { .min = 12, .max = 22 },
369 .m2 = { .min = 5, .max = 9 },
370 .p = { .min = 14, .max = 42 },
0206e353 371 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 372 .p2 = { .dot_limit = 225000,
373 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 374 .find_pll = intel_g4x_find_best_PLL,
375};
376
377static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 378 .dot = { .min = 25000, .max = 350000 },
379 .vco = { .min = 1760000, .max = 3510000},
380 .n = { .min = 1, .max = 2 },
381 .m = { .min = 81, .max = 90 },
382 .m1 = { .min = 12, .max = 22 },
383 .m2 = { .min = 5, .max = 9 },
384 .p = { .min = 10, .max = 20 },
385 .p1 = { .min = 1, .max = 2},
386 .p2 = { .dot_limit = 0,
273e27ca 387 .p2_slow = 10, .p2_fast = 10 },
0206e353 388 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 389};
390
a0c4da24
JB		 391static const intel_limit_t intel_limits_vlv_dac = {
392 .dot = { .min = 25000, .max = 270000 },
393 .vco = { .min = 4000000, .max = 6000000 },
394 .n = { .min = 1, .max = 7 },
395 .m = { .min = 22, .max = 450 }, /* guess */
396 .m1 = { .min = 2, .max = 3 },
397 .m2 = { .min = 11, .max = 156 },
398 .p = { .min = 10, .max = 30 },
399 .p1 = { .min = 2, .max = 3 },
400 .p2 = { .dot_limit = 270000,
401 .p2_slow = 2, .p2_fast = 20 },
402 .find_pll = intel_vlv_find_best_pll,
403};
404
405static const intel_limit_t intel_limits_vlv_hdmi = {
406 .dot = { .min = 20000, .max = 165000 },
17dc9257 407 .vco = { .min = 4000000, .max = 5994000},
a0c4da24
JB		 408 .n = { .min = 1, .max = 7 },
409 .m = { .min = 60, .max = 300 }, /* guess */
410 .m1 = { .min = 2, .max = 3 },
411 .m2 = { .min = 11, .max = 156 },
412 .p = { .min = 10, .max = 30 },
413 .p1 = { .min = 2, .max = 3 },
414 .p2 = { .dot_limit = 270000,
415 .p2_slow = 2, .p2_fast = 20 },
416 .find_pll = intel_vlv_find_best_pll,
417};
418
419static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 420 .dot = { .min = 25000, .max = 270000 },
421 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 422 .n = { .min = 1, .max = 7 },
74a4dd2e 423 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 424 .m1 = { .min = 2, .max = 3 },
425 .m2 = { .min = 11, .max = 156 },
426 .p = { .min = 10, .max = 30 },
427 .p1 = { .min = 2, .max = 3 },
428 .p2 = { .dot_limit = 270000,
429 .p2_slow = 2, .p2_fast = 20 },
430 .find_pll = intel_vlv_find_best_pll,
431};
432
57f350b6
JB		 433u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
434{
09153000 435 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
57f350b6 436
57f350b6
JB		 437 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
438 DRM_ERROR("DPIO idle wait timed out\n");
09153000 439 return 0;
57f350b6
JB		 440 }
441
442 I915_WRITE(DPIO_REG, reg);
443 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
444 DPIO_BYTE);
445 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
446 DRM_ERROR("DPIO read wait timed out\n");
09153000 447 return 0;
57f350b6 448 }
57f350b6 449
09153000 450 return I915_READ(DPIO_DATA);
57f350b6
JB		 451}
452
a0c4da24
JB		 453static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
454 u32 val)
455{
09153000 456 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a0c4da24 457
a0c4da24
JB		 458 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
459 DRM_ERROR("DPIO idle wait timed out\n");
09153000 460 return;
a0c4da24
JB		 461 }
462
463 I915_WRITE(DPIO_DATA, val);
464 I915_WRITE(DPIO_REG, reg);
465 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
466 DPIO_BYTE);
467 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
468 DRM_ERROR("DPIO write wait timed out\n");
a0c4da24
JB		 469}
470
57f350b6
JB		 471static void vlv_init_dpio(struct drm_device *dev)
472{
473 struct drm_i915_private *dev_priv = dev->dev_private;
474
475 /* Reset the DPIO config */
476 I915_WRITE(DPIO_CTL, 0);
477 POSTING_READ(DPIO_CTL);
478 I915_WRITE(DPIO_CTL, 1);
479 POSTING_READ(DPIO_CTL);
480}
481
1b894b59
CW		 482static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
483 int refclk)
2c07245f 484{
b91ad0ec 485 struct drm_device *dev = crtc->dev;
2c07245f 486 const intel_limit_t *limit;
b91ad0ec
ZW		 487
488 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 489 if (intel_is_dual_link_lvds(dev)) {
1b894b59 490 if (refclk == 100000)
b91ad0ec
ZW		 491 limit = &intel_limits_ironlake_dual_lvds_100m;
492 else
493 limit = &intel_limits_ironlake_dual_lvds;
494 } else {
1b894b59 495 if (refclk == 100000)
b91ad0ec
ZW		 496 limit = &intel_limits_ironlake_single_lvds_100m;
497 else
498 limit = &intel_limits_ironlake_single_lvds;
499 }
500 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
547dc041 501 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
4547668a 502 limit = &intel_limits_ironlake_display_port;
2c07245f 503 else
b91ad0ec 504 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 505
506 return limit;
507}
508
044c7c41
ML		 509static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
510{
511 struct drm_device *dev = crtc->dev;
044c7c41
ML		 512 const intel_limit_t *limit;
513
514 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 515 if (intel_is_dual_link_lvds(dev))
e4b36699 516 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 517 else
e4b36699 518 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 519 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
520 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 521 limit = &intel_limits_g4x_hdmi;
044c7c41 522 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 523 limit = &intel_limits_g4x_sdvo;
0206e353 524 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 525 limit = &intel_limits_g4x_display_port;
044c7c41 526 } else /* The option is for other outputs */
e4b36699 527 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 528
529 return limit;
530}
531
1b894b59 532static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 533{
534 struct drm_device *dev = crtc->dev;
535 const intel_limit_t *limit;
536
bad720ff 537 if (HAS_PCH_SPLIT(dev))
1b894b59 538 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 539 else if (IS_G4X(dev)) {
044c7c41 540 limit = intel_g4x_limit(crtc);
f2b115e6 541 } else if (IS_PINEVIEW(dev)) {
2177832f 542 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 543 limit = &intel_limits_pineview_lvds;
2177832f 544 else
f2b115e6 545 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 546 } else if (IS_VALLEYVIEW(dev)) {
547 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
548 limit = &intel_limits_vlv_dac;
549 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
550 limit = &intel_limits_vlv_hdmi;
551 else
552 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 553 } else if (!IS_GEN2(dev)) {
554 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
555 limit = &intel_limits_i9xx_lvds;
556 else
557 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 558 } else {
559 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 560 limit = &intel_limits_i8xx_lvds;
79e53945 561 else
e4b36699 562 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 563 }
564 return limit;
565}
566
f2b115e6
AJ		 567/* m1 is reserved as 0 in Pineview, n is a ring counter */
568static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 569{
2177832f
SL		 570 clock->m = clock->m2 + 2;
571 clock->p = clock->p1 * clock->p2;
572 clock->vco = refclk * clock->m / clock->n;
573 clock->dot = clock->vco / clock->p;
574}
575
576static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
577{
f2b115e6
AJ		 578 if (IS_PINEVIEW(dev)) {
579 pineview_clock(refclk, clock);
2177832f
SL		 580 return;
581 }
79e53945
JB		 582 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
583 clock->p = clock->p1 * clock->p2;
584 clock->vco = refclk * clock->m / (clock->n + 2);
585 clock->dot = clock->vco / clock->p;
586}
587
79e53945
JB		 588/**
589 * Returns whether any output on the specified pipe is of the specified type
590 */
4ef69c7a 591bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 592{
4ef69c7a 593 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 594 struct intel_encoder *encoder;
595
6c2b7c12
DV		 596 for_each_encoder_on_crtc(dev, crtc, encoder)
597 if (encoder->type == type)
4ef69c7a
CW		 598 return true;
599
600 return false;
79e53945
JB		 601}
602
7c04d1d9 603#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 604/**
605 * Returns whether the given set of divisors are valid for a given refclk with
606 * the given connectors.
607 */
608
1b894b59
CW		 609static bool intel_PLL_is_valid(struct drm_device *dev,
610 const intel_limit_t *limit,
611 const intel_clock_t *clock)
79e53945 612{
79e53945 613 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 614 INTELPllInvalid("p1 out of range\n");
79e53945 615 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 616 INTELPllInvalid("p out of range\n");
79e53945 617 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 618 INTELPllInvalid("m2 out of range\n");
79e53945 619 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 620 INTELPllInvalid("m1 out of range\n");
f2b115e6 621 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 622 INTELPllInvalid("m1 <= m2\n");
79e53945 623 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 624 INTELPllInvalid("m out of range\n");
79e53945 625 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 626 INTELPllInvalid("n out of range\n");
79e53945 627 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 628 INTELPllInvalid("vco out of range\n");
79e53945
JB		 629 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
630 * connector, etc., rather than just a single range.
631 */
632 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 633 INTELPllInvalid("dot out of range\n");
79e53945
JB		 634
635 return true;
636}
637
d4906093
ML		 638static bool
639intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 640 int target, int refclk, intel_clock_t *match_clock,
641 intel_clock_t *best_clock)
d4906093 642
79e53945
JB		 643{
644 struct drm_device *dev = crtc->dev;
79e53945 645 intel_clock_t clock;
79e53945
JB		 646 int err = target;
647
a210b028 648 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 649 /*
a210b028
DV		 650 * For LVDS just rely on its current settings for dual-channel.
651 * We haven't figured out how to reliably set up different
652 * single/dual channel state, if we even can.
79e53945 653 */
1974cad0 654 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 655 clock.p2 = limit->p2.p2_fast;
656 else
657 clock.p2 = limit->p2.p2_slow;
658 } else {
659 if (target < limit->p2.dot_limit)
660 clock.p2 = limit->p2.p2_slow;
661 else
662 clock.p2 = limit->p2.p2_fast;
663 }
664
0206e353 665 memset(best_clock, 0, sizeof(*best_clock));
79e53945 666
42158660
ZY		 667 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
668 clock.m1++) {
669 for (clock.m2 = limit->m2.min;
670 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 671 /* m1 is always 0 in Pineview */
672 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 673 break;
674 for (clock.n = limit->n.min;
675 clock.n <= limit->n.max; clock.n++) {
676 for (clock.p1 = limit->p1.min;
677 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 678 int this_err;
679
2177832f 680 intel_clock(dev, refclk, &clock);
1b894b59
CW		 681 if (!intel_PLL_is_valid(dev, limit,
682 &clock))
79e53945 683 continue;
cec2f356
SP		 684 if (match_clock &&
685 clock.p != match_clock->p)
686 continue;
79e53945
JB		 687
688 this_err = abs(clock.dot - target);
689 if (this_err < err) {
690 *best_clock = clock;
691 err = this_err;
692 }
693 }
694 }
695 }
696 }
697
698 return (err != target);
699}
700
d4906093
ML		 701static bool
702intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 703 int target, int refclk, intel_clock_t *match_clock,
704 intel_clock_t *best_clock)
d4906093
ML		 705{
706 struct drm_device *dev = crtc->dev;
d4906093
ML		 707 intel_clock_t clock;
708 int max_n;
709 bool found;
6ba770dc
AJ		 710 /* approximately equals target * 0.00585 */
711 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 712 found = false;
713
714 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 715 int lvds_reg;
716
c619eed4 717 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 718 lvds_reg = PCH_LVDS;
719 else
720 lvds_reg = LVDS;
1974cad0 721 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 722 clock.p2 = limit->p2.p2_fast;
723 else
724 clock.p2 = limit->p2.p2_slow;
725 } else {
726 if (target < limit->p2.dot_limit)
727 clock.p2 = limit->p2.p2_slow;
728 else
729 clock.p2 = limit->p2.p2_fast;
730 }
731
732 memset(best_clock, 0, sizeof(*best_clock));
733 max_n = limit->n.max;
f77f13e2 734 /* based on hardware requirement, prefer smaller n to precision */
d4906093 735 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 736 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 737 for (clock.m1 = limit->m1.max;
738 clock.m1 >= limit->m1.min; clock.m1--) {
739 for (clock.m2 = limit->m2.max;
740 clock.m2 >= limit->m2.min; clock.m2--) {
741 for (clock.p1 = limit->p1.max;
742 clock.p1 >= limit->p1.min; clock.p1--) {
743 int this_err;
744
2177832f 745 intel_clock(dev, refclk, &clock);
1b894b59
CW		 746 if (!intel_PLL_is_valid(dev, limit,
747 &clock))
d4906093 748 continue;
cec2f356
SP		 749 if (match_clock &&
750 clock.p != match_clock->p)
751 continue;
1b894b59
CW		 752
753 this_err = abs(clock.dot - target);
d4906093
ML		 754 if (this_err < err_most) {
755 *best_clock = clock;
756 err_most = this_err;
757 max_n = clock.n;
758 found = true;
759 }
760 }
761 }
762 }
763 }
2c07245f
ZW		 764 return found;
765}
766
5eb08b69 767static bool
f2b115e6 768intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 769 int target, int refclk, intel_clock_t *match_clock,
770 intel_clock_t *best_clock)
5eb08b69
ZW		 771{
772 struct drm_device *dev = crtc->dev;
773 intel_clock_t clock;
4547668a 774
5eb08b69
ZW		 775 if (target < 200000) {
776 clock.n = 1;
777 clock.p1 = 2;
778 clock.p2 = 10;
779 clock.m1 = 12;
780 clock.m2 = 9;
781 } else {
782 clock.n = 2;
783 clock.p1 = 1;
784 clock.p2 = 10;
785 clock.m1 = 14;
786 clock.m2 = 8;
787 }
788 intel_clock(dev, refclk, &clock);
789 memcpy(best_clock, &clock, sizeof(intel_clock_t));
790 return true;
791}
792
a4fc5ed6
KP		 793/* DisplayPort has only two frequencies, 162MHz and 270MHz */
794static bool
795intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 796 int target, int refclk, intel_clock_t *match_clock,
797 intel_clock_t *best_clock)
a4fc5ed6 798{
5eddb70b
CW		 799 intel_clock_t clock;
800 if (target < 200000) {
801 clock.p1 = 2;
802 clock.p2 = 10;
803 clock.n = 2;
804 clock.m1 = 23;
805 clock.m2 = 8;
806 } else {
807 clock.p1 = 1;
808 clock.p2 = 10;
809 clock.n = 1;
810 clock.m1 = 14;
811 clock.m2 = 2;
812 }
813 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
814 clock.p = (clock.p1 * clock.p2);
815 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
816 clock.vco = 0;
817 memcpy(best_clock, &clock, sizeof(intel_clock_t));
818 return true;
a4fc5ed6 819}
a0c4da24
JB		 820static bool
821intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
822 int target, int refclk, intel_clock_t *match_clock,
823 intel_clock_t *best_clock)
824{
825 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
826 u32 m, n, fastclk;
827 u32 updrate, minupdate, fracbits, p;
828 unsigned long bestppm, ppm, absppm;
829 int dotclk, flag;
830
af447bd3 831 flag = 0;
a0c4da24
JB		 832 dotclk = target * 1000;
833 bestppm = 1000000;
834 ppm = absppm = 0;
835 fastclk = dotclk / (2*100);
836 updrate = 0;
837 minupdate = 19200;
838 fracbits = 1;
839 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
840 bestm1 = bestm2 = bestp1 = bestp2 = 0;
841
842 /* based on hardware requirement, prefer smaller n to precision */
843 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
844 updrate = refclk / n;
845 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
846 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
847 if (p2 > 10)
848 p2 = p2 - 1;
849 p = p1 * p2;
850 /* based on hardware requirement, prefer bigger m1,m2 values */
851 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
852 m2 = (((2*(fastclk * p * n / m1 )) +
853 refclk) / (2*refclk));
854 m = m1 * m2;
855 vco = updrate * m;
856 if (vco >= limit->vco.min && vco < limit->vco.max) {
857 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
858 absppm = (ppm > 0) ? ppm : (-ppm);
859 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
860 bestppm = 0;
861 flag = 1;
862 }
863 if (absppm < bestppm - 10) {
864 bestppm = absppm;
865 flag = 1;
866 }
867 if (flag) {
868 bestn = n;
869 bestm1 = m1;
870 bestm2 = m2;
871 bestp1 = p1;
872 bestp2 = p2;
873 flag = 0;
874 }
875 }
876 }
877 }
878 }
879 }
880 best_clock->n = bestn;
881 best_clock->m1 = bestm1;
882 best_clock->m2 = bestm2;
883 best_clock->p1 = bestp1;
884 best_clock->p2 = bestp2;
885
886 return true;
887}
a4fc5ed6 888
a5c961d1
PZ		 889enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
890 enum pipe pipe)
891{
892 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
893 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
894
3b117c8f 895 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 896}
897
a928d536
PZ		 898static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
899{
900 struct drm_i915_private *dev_priv = dev->dev_private;
901 u32 frame, frame_reg = PIPEFRAME(pipe);
902
903 frame = I915_READ(frame_reg);
904
905 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
906 DRM_DEBUG_KMS("vblank wait timed out\n");
907}
908
9d0498a2
JB		 909/**
910 * intel_wait_for_vblank - wait for vblank on a given pipe
911 * @dev: drm device
912 * @pipe: pipe to wait for
913 *
914 * Wait for vblank to occur on a given pipe. Needed for various bits of
915 * mode setting code.
916 */
917void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 918{
9d0498a2 919 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 920 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 921
a928d536
PZ		 922 if (INTEL_INFO(dev)->gen >= 5) {
923 ironlake_wait_for_vblank(dev, pipe);
924 return;
925 }
926
300387c0
CW		 927 /* Clear existing vblank status. Note this will clear any other
928 * sticky status fields as well.
929 *
930 * This races with i915_driver_irq_handler() with the result
931 * that either function could miss a vblank event. Here it is not
932 * fatal, as we will either wait upon the next vblank interrupt or
933 * timeout. Generally speaking intel_wait_for_vblank() is only
934 * called during modeset at which time the GPU should be idle and
935 * should *not* be performing page flips and thus not waiting on
936 * vblanks...
937 * Currently, the result of us stealing a vblank from the irq
938 * handler is that a single frame will be skipped during swapbuffers.
939 */
940 I915_WRITE(pipestat_reg,
941 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
942
9d0498a2 943 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 944 if (wait_for(I915_READ(pipestat_reg) &
945 PIPE_VBLANK_INTERRUPT_STATUS,
946 50))
9d0498a2
JB		 947 DRM_DEBUG_KMS("vblank wait timed out\n");
948}
949
ab7ad7f6
KP		 950/*
951 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 952 * @dev: drm device
953 * @pipe: pipe to wait for
954 *
955 * After disabling a pipe, we can't wait for vblank in the usual way,
956 * spinning on the vblank interrupt status bit, since we won't actually
957 * see an interrupt when the pipe is disabled.
958 *
ab7ad7f6
KP		 959 * On Gen4 and above:
960 * wait for the pipe register state bit to turn off
961 *
962 * Otherwise:
963 * wait for the display line value to settle (it usually
964 * ends up stopping at the start of the next frame).
58e10eb9 965 *
9d0498a2 966 */
58e10eb9 967void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 968{
969 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 970 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
971 pipe);
ab7ad7f6
KP		 972
973 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 974 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 975
976 /* Wait for the Pipe State to go off */
58e10eb9
CW		 977 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
978 100))
284637d9 979 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 980 } else {
837ba00f 981 u32 last_line, line_mask;
58e10eb9 982 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 983 unsigned long timeout = jiffies + msecs_to_jiffies(100);
984
837ba00f
PZ		 985 if (IS_GEN2(dev))
986 line_mask = DSL_LINEMASK_GEN2;
987 else
988 line_mask = DSL_LINEMASK_GEN3;
989
ab7ad7f6
KP		 990 /* Wait for the display line to settle */
991 do {
837ba00f 992 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 993 mdelay(5);
837ba00f 994 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 995 time_after(timeout, jiffies));
996 if (time_after(jiffies, timeout))
284637d9 997 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 998 }
79e53945
JB		 999}
1000
b0ea7d37
DL		 1001/*
1002 * ibx_digital_port_connected - is the specified port connected?
1003 * @dev_priv: i915 private structure
1004 * @port: the port to test
1005 *
1006 * Returns true if @port is connected, false otherwise.
1007 */
1008bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1009 struct intel_digital_port *port)
1010{
1011 u32 bit;
1012
c36346e3
DL		 1013 if (HAS_PCH_IBX(dev_priv->dev)) {
1014 switch(port->port) {
1015 case PORT_B:
1016 bit = SDE_PORTB_HOTPLUG;
1017 break;
1018 case PORT_C:
1019 bit = SDE_PORTC_HOTPLUG;
1020 break;
1021 case PORT_D:
1022 bit = SDE_PORTD_HOTPLUG;
1023 break;
1024 default:
1025 return true;
1026 }
1027 } else {
1028 switch(port->port) {
1029 case PORT_B:
1030 bit = SDE_PORTB_HOTPLUG_CPT;
1031 break;
1032 case PORT_C:
1033 bit = SDE_PORTC_HOTPLUG_CPT;
1034 break;
1035 case PORT_D:
1036 bit = SDE_PORTD_HOTPLUG_CPT;
1037 break;
1038 default:
1039 return true;
1040 }
b0ea7d37
DL		 1041 }
1042
1043 return I915_READ(SDEISR) & bit;
1044}
1045
b24e7179
JB		 1046static const char *state_string(bool enabled)
1047{
1048 return enabled ? "on" : "off";
1049}
1050
1051/* Only for pre-ILK configs */
1052static void assert_pll(struct drm_i915_private *dev_priv,
1053 enum pipe pipe, bool state)
1054{
1055 int reg;
1056 u32 val;
1057 bool cur_state;
1058
1059 reg = DPLL(pipe);
1060 val = I915_READ(reg);
1061 cur_state = !!(val & DPLL_VCO_ENABLE);
1062 WARN(cur_state != state,
1063 "PLL state assertion failure (expected %s, current %s)\n",
1064 state_string(state), state_string(cur_state));
1065}
1066#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1067#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1068
040484af
JB		 1069/* For ILK+ */
1070static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1071 struct intel_pch_pll *pll,
1072 struct intel_crtc *crtc,
1073 bool state)
040484af 1074{
040484af
JB		 1075 u32 val;
1076 bool cur_state;
1077
9d82aa17
ED		 1078 if (HAS_PCH_LPT(dev_priv->dev)) {
1079 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1080 return;
1081 }
1082
92b27b08
CW		 1083 if (WARN (!pll,
1084 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1085 return;
ee7b9f93 1086
92b27b08
CW		 1087 val = I915_READ(pll->pll_reg);
1088 cur_state = !!(val & DPLL_VCO_ENABLE);
1089 WARN(cur_state != state,
1090 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1091 pll->pll_reg, state_string(state), state_string(cur_state), val);
1092
1093 /* Make sure the selected PLL is correctly attached to the transcoder */
1094 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1095 u32 pch_dpll;
1096
1097 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1098 cur_state = pll->pll_reg == _PCH_DPLL_B;
1099 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1100 "PLL[%d] not attached to this transcoder %d: %08x\n",
1101 cur_state, crtc->pipe, pch_dpll)) {
1102 cur_state = !!(val >> (4*crtc->pipe + 3));
1103 WARN(cur_state != state,
1104 "PLL[%d] not %s on this transcoder %d: %08x\n",
1105 pll->pll_reg == _PCH_DPLL_B,
1106 state_string(state),
1107 crtc->pipe,
1108 val);
1109 }
d3ccbe86 1110 }
040484af 1111}
92b27b08
CW		 1112#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1113#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1114
1115static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1116 enum pipe pipe, bool state)
1117{
1118 int reg;
1119 u32 val;
1120 bool cur_state;
ad80a810
PZ		 1121 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1122 pipe);
040484af 1123
affa9354
PZ		 1124 if (HAS_DDI(dev_priv->dev)) {
1125 /* DDI does not have a specific FDI_TX register */
ad80a810 1126 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1127 val = I915_READ(reg);
ad80a810 1128 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1129 } else {
1130 reg = FDI_TX_CTL(pipe);
1131 val = I915_READ(reg);
1132 cur_state = !!(val & FDI_TX_ENABLE);
1133 }
040484af
JB		 1134 WARN(cur_state != state,
1135 "FDI TX state assertion failure (expected %s, current %s)\n",
1136 state_string(state), state_string(cur_state));
1137}
1138#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1139#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1140
1141static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1142 enum pipe pipe, bool state)
1143{
1144 int reg;
1145 u32 val;
1146 bool cur_state;
1147
d63fa0dc
PZ		 1148 reg = FDI_RX_CTL(pipe);
1149 val = I915_READ(reg);
1150 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1151 WARN(cur_state != state,
1152 "FDI RX state assertion failure (expected %s, current %s)\n",
1153 state_string(state), state_string(cur_state));
1154}
1155#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1156#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1157
1158static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1159 enum pipe pipe)
1160{
1161 int reg;
1162 u32 val;
1163
1164 /* ILK FDI PLL is always enabled */
1165 if (dev_priv->info->gen == 5)
1166 return;
1167
bf507ef7 1168 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1169 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1170 return;
1171
040484af
JB		 1172 reg = FDI_TX_CTL(pipe);
1173 val = I915_READ(reg);
1174 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1175}
1176
1177static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1178 enum pipe pipe)
1179{
1180 int reg;
1181 u32 val;
1182
1183 reg = FDI_RX_CTL(pipe);
1184 val = I915_READ(reg);
1185 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1186}
1187
ea0760cf
JB		 1188static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1189 enum pipe pipe)
1190{
1191 int pp_reg, lvds_reg;
1192 u32 val;
1193 enum pipe panel_pipe = PIPE_A;
0de3b485 1194 bool locked = true;
ea0760cf
JB		 1195
1196 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1197 pp_reg = PCH_PP_CONTROL;
1198 lvds_reg = PCH_LVDS;
1199 } else {
1200 pp_reg = PP_CONTROL;
1201 lvds_reg = LVDS;
1202 }
1203
1204 val = I915_READ(pp_reg);
1205 if (!(val & PANEL_POWER_ON) ||
1206 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1207 locked = false;
1208
1209 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1210 panel_pipe = PIPE_B;
1211
1212 WARN(panel_pipe == pipe && locked,
1213 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1214 pipe_name(pipe));
ea0760cf
JB		 1215}
1216
b840d907
JB		 1217void assert_pipe(struct drm_i915_private *dev_priv,
1218 enum pipe pipe, bool state)
b24e7179
JB		 1219{
1220 int reg;
1221 u32 val;
63d7bbe9 1222 bool cur_state;
702e7a56
PZ		 1223 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1224 pipe);
b24e7179 1225
8e636784
DV		 1226 /* if we need the pipe A quirk it must be always on */
1227 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1228 state = true;
1229
15d199ea
PZ		 1230 if (!intel_using_power_well(dev_priv->dev) &&
1231 cpu_transcoder != TRANSCODER_EDP) {
69310161
PZ		 1232 cur_state = false;
1233 } else {
1234 reg = PIPECONF(cpu_transcoder);
1235 val = I915_READ(reg);
1236 cur_state = !!(val & PIPECONF_ENABLE);
1237 }
1238
63d7bbe9
JB		 1239 WARN(cur_state != state,
1240 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1241 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1242}
1243
931872fc
CW		 1244static void assert_plane(struct drm_i915_private *dev_priv,
1245 enum plane plane, bool state)
b24e7179
JB		 1246{
1247 int reg;
1248 u32 val;
931872fc 1249 bool cur_state;
b24e7179
JB		 1250
1251 reg = DSPCNTR(plane);
1252 val = I915_READ(reg);
931872fc
CW		 1253 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1254 WARN(cur_state != state,
1255 "plane %c assertion failure (expected %s, current %s)\n",
1256 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1257}
1258
931872fc
CW		 1259#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1260#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1261
b24e7179
JB		 1262static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1263 enum pipe pipe)
1264{
1265 int reg, i;
1266 u32 val;
1267 int cur_pipe;
1268
19ec1358 1269 /* Planes are fixed to pipes on ILK+ */
da6ecc5d 1270 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
28c05794
AJ		 1271 reg = DSPCNTR(pipe);
1272 val = I915_READ(reg);
1273 WARN((val & DISPLAY_PLANE_ENABLE),
1274 "plane %c assertion failure, should be disabled but not\n",
1275 plane_name(pipe));
19ec1358 1276 return;
28c05794 1277 }
19ec1358 1278
b24e7179
JB		 1279 /* Need to check both planes against the pipe */
1280 for (i = 0; i < 2; i++) {
1281 reg = DSPCNTR(i);
1282 val = I915_READ(reg);
1283 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1284 DISPPLANE_SEL_PIPE_SHIFT;
1285 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1286 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1287 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1288 }
1289}
1290
19332d7a
JB		 1291static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1292 enum pipe pipe)
1293{
1294 int reg, i;
1295 u32 val;
1296
1297 if (!IS_VALLEYVIEW(dev_priv->dev))
1298 return;
1299
1300 /* Need to check both planes against the pipe */
1301 for (i = 0; i < dev_priv->num_plane; i++) {
1302 reg = SPCNTR(pipe, i);
1303 val = I915_READ(reg);
1304 WARN((val & SP_ENABLE),
1305 "sprite %d assertion failure, should be off on pipe %c but is still active\n",
1306 pipe * 2 + i, pipe_name(pipe));
1307 }
1308}
1309
92f2584a
JB		 1310static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1311{
1312 u32 val;
1313 bool enabled;
1314
9d82aa17
ED		 1315 if (HAS_PCH_LPT(dev_priv->dev)) {
1316 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1317 return;
1318 }
1319
92f2584a
JB		 1320 val = I915_READ(PCH_DREF_CONTROL);
1321 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1322 DREF_SUPERSPREAD_SOURCE_MASK));
1323 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1324}
1325
1326static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1327 enum pipe pipe)
1328{
1329 int reg;
1330 u32 val;
1331 bool enabled;
1332
1333 reg = TRANSCONF(pipe);
1334 val = I915_READ(reg);
1335 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1336 WARN(enabled,
1337 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1338 pipe_name(pipe));
92f2584a
JB		 1339}
1340
4e634389
KP		 1341static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1342 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1343{
1344 if ((val & DP_PORT_EN) == 0)
1345 return false;
1346
1347 if (HAS_PCH_CPT(dev_priv->dev)) {
1348 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1349 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1350 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1351 return false;
1352 } else {
1353 if ((val & DP_PIPE_MASK) != (pipe << 30))
1354 return false;
1355 }
1356 return true;
1357}
1358
1519b995
KP		 1359static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1360 enum pipe pipe, u32 val)
1361{
dc0fa718 1362 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1363 return false;
1364
1365 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1366 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1367 return false;
1368 } else {
dc0fa718 1369 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1370 return false;
1371 }
1372 return true;
1373}
1374
1375static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1376 enum pipe pipe, u32 val)
1377{
1378 if ((val & LVDS_PORT_EN) == 0)
1379 return false;
1380
1381 if (HAS_PCH_CPT(dev_priv->dev)) {
1382 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1383 return false;
1384 } else {
1385 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1386 return false;
1387 }
1388 return true;
1389}
1390
1391static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1392 enum pipe pipe, u32 val)
1393{
1394 if ((val & ADPA_DAC_ENABLE) == 0)
1395 return false;
1396 if (HAS_PCH_CPT(dev_priv->dev)) {
1397 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1398 return false;
1399 } else {
1400 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1401 return false;
1402 }
1403 return true;
1404}
1405
291906f1 1406static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1407 enum pipe pipe, int reg, u32 port_sel)
291906f1 1408{
47a05eca 1409 u32 val = I915_READ(reg);
4e634389 1410 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1411 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1412 reg, pipe_name(pipe));
de9a35ab 1413
75c5da27
DV		 1414 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1415 && (val & DP_PIPEB_SELECT),
de9a35ab 1416 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1417}
1418
1419static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1420 enum pipe pipe, int reg)
1421{
47a05eca 1422 u32 val = I915_READ(reg);
b70ad586 1423 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1424 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1425 reg, pipe_name(pipe));
de9a35ab 1426
dc0fa718 1427 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1428 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1429 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1430}
1431
1432static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1433 enum pipe pipe)
1434{
1435 int reg;
1436 u32 val;
291906f1 1437
f0575e92
KP		 1438 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1439 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1440 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1441
1442 reg = PCH_ADPA;
1443 val = I915_READ(reg);
b70ad586 1444 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1445 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1446 pipe_name(pipe));
291906f1
JB		 1447
1448 reg = PCH_LVDS;
1449 val = I915_READ(reg);
b70ad586 1450 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1451 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1452 pipe_name(pipe));
291906f1 1453
e2debe91
PZ		 1454 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1455 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1456 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1457}
1458
63d7bbe9
JB		 1459/**
1460 * intel_enable_pll - enable a PLL
1461 * @dev_priv: i915 private structure
1462 * @pipe: pipe PLL to enable
1463 *
1464 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1465 * make sure the PLL reg is writable first though, since the panel write
1466 * protect mechanism may be enabled.
1467 *
1468 * Note! This is for pre-ILK only.
7434a255
TR		 1469 *
1470 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1471 */
1472static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1473{
1474 int reg;
1475 u32 val;
1476
58c6eaa2
DV		 1477 assert_pipe_disabled(dev_priv, pipe);
1478
63d7bbe9 1479 /* No really, not for ILK+ */
a0c4da24 1480 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1481
1482 /* PLL is protected by panel, make sure we can write it */
1483 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1484 assert_panel_unlocked(dev_priv, pipe);
1485
1486 reg = DPLL(pipe);
1487 val = I915_READ(reg);
1488 val |= DPLL_VCO_ENABLE;
1489
1490 /* We do this three times for luck */
1491 I915_WRITE(reg, val);
1492 POSTING_READ(reg);
1493 udelay(150); /* wait for warmup */
1494 I915_WRITE(reg, val);
1495 POSTING_READ(reg);
1496 udelay(150); /* wait for warmup */
1497 I915_WRITE(reg, val);
1498 POSTING_READ(reg);
1499 udelay(150); /* wait for warmup */
1500}
1501
1502/**
1503 * intel_disable_pll - disable a PLL
1504 * @dev_priv: i915 private structure
1505 * @pipe: pipe PLL to disable
1506 *
1507 * Disable the PLL for @pipe, making sure the pipe is off first.
1508 *
1509 * Note! This is for pre-ILK only.
1510 */
1511static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1512{
1513 int reg;
1514 u32 val;
1515
1516 /* Don't disable pipe A or pipe A PLLs if needed */
1517 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1518 return;
1519
1520 /* Make sure the pipe isn't still relying on us */
1521 assert_pipe_disabled(dev_priv, pipe);
1522
1523 reg = DPLL(pipe);
1524 val = I915_READ(reg);
1525 val &= ~DPLL_VCO_ENABLE;
1526 I915_WRITE(reg, val);
1527 POSTING_READ(reg);
1528}
1529
a416edef
ED		 1530/* SBI access */
1531static void
988d6ee8
PZ		 1532intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1533 enum intel_sbi_destination destination)
a416edef 1534{
988d6ee8 1535 u32 tmp;
a416edef 1536
09153000 1537 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1538
39fb50f6 1539 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1540 100)) {
1541 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1542 return;
a416edef
ED		 1543 }
1544
988d6ee8
PZ		 1545 I915_WRITE(SBI_ADDR, (reg << 16));
1546 I915_WRITE(SBI_DATA, value);
1547
1548 if (destination == SBI_ICLK)
1549 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1550 else
1551 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1552 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
a416edef 1553
39fb50f6 1554 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1555 100)) {
1556 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
09153000 1557 return;
a416edef 1558 }
a416edef
ED		 1559}
1560
1561static u32
988d6ee8
PZ		 1562intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1563 enum intel_sbi_destination destination)
a416edef 1564{
39fb50f6 1565 u32 value = 0;
09153000 1566 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1567
39fb50f6 1568 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1569 100)) {
1570 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1571 return 0;
a416edef
ED		 1572 }
1573
988d6ee8
PZ		 1574 I915_WRITE(SBI_ADDR, (reg << 16));
1575
1576 if (destination == SBI_ICLK)
1577 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1578 else
1579 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1580 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
a416edef 1581
39fb50f6 1582 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1583 100)) {
1584 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
09153000 1585 return 0;
a416edef
ED		 1586 }
1587
09153000 1588 return I915_READ(SBI_DATA);
a416edef
ED		 1589}
1590
92f2584a 1591/**
b6b4e185 1592 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1593 * @dev_priv: i915 private structure
1594 * @pipe: pipe PLL to enable
1595 *
1596 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1597 * drives the transcoder clock.
1598 */
b6b4e185 1599static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1600{
ee7b9f93 1601 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1602 struct intel_pch_pll *pll;
92f2584a
JB		 1603 int reg;
1604 u32 val;
1605
48da64a8 1606 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1607 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1608 pll = intel_crtc->pch_pll;
1609 if (pll == NULL)
1610 return;
1611
1612 if (WARN_ON(pll->refcount == 0))
1613 return;
ee7b9f93
JB		 1614
1615 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1616 pll->pll_reg, pll->active, pll->on,
1617 intel_crtc->base.base.id);
92f2584a
JB		 1618
1619 /* PCH refclock must be enabled first */
1620 assert_pch_refclk_enabled(dev_priv);
1621
ee7b9f93 1622 if (pll->active++ && pll->on) {
92b27b08 1623 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1624 return;
1625 }
1626
1627 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1628
1629 reg = pll->pll_reg;
92f2584a
JB		 1630 val = I915_READ(reg);
1631 val |= DPLL_VCO_ENABLE;
1632 I915_WRITE(reg, val);
1633 POSTING_READ(reg);
1634 udelay(200);
ee7b9f93
JB		 1635
1636 pll->on = true;
92f2584a
JB		 1637}
1638
ee7b9f93 1639static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1640{
ee7b9f93
JB		 1641 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1642 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1643 int reg;
ee7b9f93 1644 u32 val;
4c609cb8 1645
92f2584a
JB		 1646 /* PCH only available on ILK+ */
1647 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1648 if (pll == NULL)
1649 return;
92f2584a 1650
48da64a8
CW		 1651 if (WARN_ON(pll->refcount == 0))
1652 return;
7a419866 1653
ee7b9f93
JB		 1654 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1655 pll->pll_reg, pll->active, pll->on,
1656 intel_crtc->base.base.id);
7a419866 1657
48da64a8 1658 if (WARN_ON(pll->active == 0)) {
92b27b08 1659 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1660 return;
1661 }
1662
ee7b9f93 1663 if (--pll->active) {
92b27b08 1664 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1665 return;
ee7b9f93
JB		 1666 }
1667
1668 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1669
1670 /* Make sure transcoder isn't still depending on us */
1671 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1672
ee7b9f93 1673 reg = pll->pll_reg;
92f2584a
JB		 1674 val = I915_READ(reg);
1675 val &= ~DPLL_VCO_ENABLE;
1676 I915_WRITE(reg, val);
1677 POSTING_READ(reg);
1678 udelay(200);
ee7b9f93
JB		 1679
1680 pll->on = false;
92f2584a
JB		 1681}
1682
b8a4f404
PZ		 1683static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1684 enum pipe pipe)
040484af 1685{
23670b32 1686 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1687 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1688 uint32_t reg, val, pipeconf_val;
040484af
JB		 1689
1690 /* PCH only available on ILK+ */
1691 BUG_ON(dev_priv->info->gen < 5);
1692
1693 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1694 assert_pch_pll_enabled(dev_priv,
1695 to_intel_crtc(crtc)->pch_pll,
1696 to_intel_crtc(crtc));
040484af
JB		 1697
1698 /* FDI must be feeding us bits for PCH ports */
1699 assert_fdi_tx_enabled(dev_priv, pipe);
1700 assert_fdi_rx_enabled(dev_priv, pipe);
1701
23670b32
DV		 1702 if (HAS_PCH_CPT(dev)) {
1703 /* Workaround: Set the timing override bit before enabling the
1704 * pch transcoder. */
1705 reg = TRANS_CHICKEN2(pipe);
1706 val = I915_READ(reg);
1707 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1708 I915_WRITE(reg, val);
59c859d6 1709 }
23670b32 1710
040484af
JB		 1711 reg = TRANSCONF(pipe);
1712 val = I915_READ(reg);
5f7f726d 1713 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1714
1715 if (HAS_PCH_IBX(dev_priv->dev)) {
1716 /*
1717 * make the BPC in transcoder be consistent with
1718 * that in pipeconf reg.
1719 */
dfd07d72
DV		 1720 val &= ~PIPECONF_BPC_MASK;
1721 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1722 }
5f7f726d
PZ		 1723
1724 val &= ~TRANS_INTERLACE_MASK;
1725 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1726 if (HAS_PCH_IBX(dev_priv->dev) &&
1727 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1728 val |= TRANS_LEGACY_INTERLACED_ILK;
1729 else
1730 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1731 else
1732 val |= TRANS_PROGRESSIVE;
1733
040484af
JB		 1734 I915_WRITE(reg, val | TRANS_ENABLE);
1735 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1736 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1737}
1738
8fb033d7 1739static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1740 enum transcoder cpu_transcoder)
040484af 1741{
8fb033d7 1742 u32 val, pipeconf_val;
8fb033d7
PZ		 1743
1744 /* PCH only available on ILK+ */
1745 BUG_ON(dev_priv->info->gen < 5);
1746
8fb033d7 1747 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1748 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1749 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1750
223a6fdf
PZ		 1751 /* Workaround: set timing override bit. */
1752 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1753 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1754 I915_WRITE(_TRANSA_CHICKEN2, val);
1755
25f3ef11 1756 val = TRANS_ENABLE;
937bb610 1757 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1758
9a76b1c6
PZ		 1759 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1760 PIPECONF_INTERLACED_ILK)
a35f2679 1761 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1762 else
1763 val |= TRANS_PROGRESSIVE;
1764
25f3ef11 1765 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
937bb610
PZ		 1766 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1767 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1768}
1769
b8a4f404
PZ		 1770static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1771 enum pipe pipe)
040484af 1772{
23670b32
DV		 1773 struct drm_device *dev = dev_priv->dev;
1774 uint32_t reg, val;
040484af
JB		 1775
1776 /* FDI relies on the transcoder */
1777 assert_fdi_tx_disabled(dev_priv, pipe);
1778 assert_fdi_rx_disabled(dev_priv, pipe);
1779
291906f1
JB		 1780 /* Ports must be off as well */
1781 assert_pch_ports_disabled(dev_priv, pipe);
1782
040484af
JB		 1783 reg = TRANSCONF(pipe);
1784 val = I915_READ(reg);
1785 val &= ~TRANS_ENABLE;
1786 I915_WRITE(reg, val);
1787 /* wait for PCH transcoder off, transcoder state */
1788 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1789 DRM_ERROR("failed to disable transcoder %d\n", pipe);
23670b32
DV		 1790
1791 if (!HAS_PCH_IBX(dev)) {
1792 /* Workaround: Clear the timing override chicken bit again. */
1793 reg = TRANS_CHICKEN2(pipe);
1794 val = I915_READ(reg);
1795 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1796 I915_WRITE(reg, val);
1797 }
040484af
JB		 1798}
1799
ab4d966c 1800static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1801{
8fb033d7
PZ		 1802 u32 val;
1803
8a52fd9f 1804 val = I915_READ(_TRANSACONF);
8fb033d7 1805 val &= ~TRANS_ENABLE;
8a52fd9f 1806 I915_WRITE(_TRANSACONF, val);
8fb033d7 1807 /* wait for PCH transcoder off, transcoder state */
8a52fd9f
PZ		 1808 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1809 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1810
1811 /* Workaround: clear timing override bit. */
1812 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1813 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1814 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1815}
1816
b24e7179 1817/**
309cfea8 1818 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1819 * @dev_priv: i915 private structure
1820 * @pipe: pipe to enable
040484af 1821 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1822 *
1823 * Enable @pipe, making sure that various hardware specific requirements
1824 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1825 *
1826 * @pipe should be %PIPE_A or %PIPE_B.
1827 *
1828 * Will wait until the pipe is actually running (i.e. first vblank) before
1829 * returning.
1830 */
040484af
JB		 1831static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1832 bool pch_port)
b24e7179 1833{
702e7a56
PZ		 1834 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1835 pipe);
1a240d4d 1836 enum pipe pch_transcoder;
b24e7179
JB		 1837 int reg;
1838 u32 val;
1839
58c6eaa2
DV		 1840 assert_planes_disabled(dev_priv, pipe);
1841 assert_sprites_disabled(dev_priv, pipe);
1842
681e5811 1843 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1844 pch_transcoder = TRANSCODER_A;
1845 else
1846 pch_transcoder = pipe;
1847
b24e7179
JB		 1848 /*
1849 * A pipe without a PLL won't actually be able to drive bits from
1850 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1851 * need the check.
1852 */
1853 if (!HAS_PCH_SPLIT(dev_priv->dev))
1854 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1855 else {
1856 if (pch_port) {
1857 /* if driving the PCH, we need FDI enabled */
cc391bbb 1858 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1859 assert_fdi_tx_pll_enabled(dev_priv,
1860 (enum pipe) cpu_transcoder);
040484af
JB		 1861 }
1862 /* FIXME: assert CPU port conditions for SNB+ */
1863 }
b24e7179 1864
702e7a56 1865 reg = PIPECONF(cpu_transcoder);
b24e7179 1866 val = I915_READ(reg);
00d70b15
CW		 1867 if (val & PIPECONF_ENABLE)
1868 return;
1869
1870 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1871 intel_wait_for_vblank(dev_priv->dev, pipe);
1872}
1873
1874/**
309cfea8 1875 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1876 * @dev_priv: i915 private structure
1877 * @pipe: pipe to disable
1878 *
1879 * Disable @pipe, making sure that various hardware specific requirements
1880 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1881 *
1882 * @pipe should be %PIPE_A or %PIPE_B.
1883 *
1884 * Will wait until the pipe has shut down before returning.
1885 */
1886static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1887 enum pipe pipe)
1888{
702e7a56
PZ		 1889 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1890 pipe);
b24e7179
JB		 1891 int reg;
1892 u32 val;
1893
1894 /*
1895 * Make sure planes won't keep trying to pump pixels to us,
1896 * or we might hang the display.
1897 */
1898 assert_planes_disabled(dev_priv, pipe);
19332d7a 1899 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1900
1901 /* Don't disable pipe A or pipe A PLLs if needed */
1902 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1903 return;
1904
702e7a56 1905 reg = PIPECONF(cpu_transcoder);
b24e7179 1906 val = I915_READ(reg);
00d70b15
CW		 1907 if ((val & PIPECONF_ENABLE) == 0)
1908 return;
1909
1910 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1911 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1912}
1913
d74362c9
KP		 1914/*
1915 * Plane regs are double buffered, going from enabled->disabled needs a
1916 * trigger in order to latch. The display address reg provides this.
1917 */
6f1d69b0 1918void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1919 enum plane plane)
1920{
14f86147
DL		 1921 if (dev_priv->info->gen >= 4)
1922 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1923 else
1924 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1925}
1926
b24e7179
JB		 1927/**
1928 * intel_enable_plane - enable a display plane on a given pipe
1929 * @dev_priv: i915 private structure
1930 * @plane: plane to enable
1931 * @pipe: pipe being fed
1932 *
1933 * Enable @plane on @pipe, making sure that @pipe is running first.
1934 */
1935static void intel_enable_plane(struct drm_i915_private *dev_priv,
1936 enum plane plane, enum pipe pipe)
1937{
1938 int reg;
1939 u32 val;
1940
1941 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1942 assert_pipe_enabled(dev_priv, pipe);
1943
1944 reg = DSPCNTR(plane);
1945 val = I915_READ(reg);
00d70b15
CW		 1946 if (val & DISPLAY_PLANE_ENABLE)
1947 return;
1948
1949 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1950 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1951 intel_wait_for_vblank(dev_priv->dev, pipe);
1952}
1953
b24e7179
JB		 1954/**
1955 * intel_disable_plane - disable a display plane
1956 * @dev_priv: i915 private structure
1957 * @plane: plane to disable
1958 * @pipe: pipe consuming the data
1959 *
1960 * Disable @plane; should be an independent operation.
1961 */
1962static void intel_disable_plane(struct drm_i915_private *dev_priv,
1963 enum plane plane, enum pipe pipe)
1964{
1965 int reg;
1966 u32 val;
1967
1968 reg = DSPCNTR(plane);
1969 val = I915_READ(reg);
00d70b15
CW		 1970 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1971 return;
1972
1973 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1974 intel_flush_display_plane(dev_priv, plane);
1975 intel_wait_for_vblank(dev_priv->dev, pipe);
1976}
1977
693db184
CW		 1978static bool need_vtd_wa(struct drm_device *dev)
1979{
1980#ifdef CONFIG_INTEL_IOMMU
1981 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1982 return true;
1983#endif
1984 return false;
1985}
1986
127bd2ac 1987int
48b956c5 1988intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1989 struct drm_i915_gem_object *obj,
919926ae 1990 struct intel_ring_buffer *pipelined)
6b95a207 1991{
ce453d81 1992 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1993 u32 alignment;
1994 int ret;
1995
05394f39 1996 switch (obj->tiling_mode) {
6b95a207 1997 case I915_TILING_NONE:
534843da
CW		 1998 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1999 alignment = 128 * 1024;
a6c45cf0 2000 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 2001 alignment = 4 * 1024;
2002 else
2003 alignment = 64 * 1024;
6b95a207
KH		 2004 break;
2005 case I915_TILING_X:
2006 /* pin() will align the object as required by fence */
2007 alignment = 0;
2008 break;
2009 case I915_TILING_Y:
8bb6e959
DV		 2010 /* Despite that we check this in framebuffer_init userspace can
2011 * screw us over and change the tiling after the fact. Only
2012 * pinned buffers can't change their tiling. */
2013 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 2014 return -EINVAL;
2015 default:
2016 BUG();
2017 }
2018
693db184
CW		 2019 /* Note that the w/a also requires 64 PTE of padding following the
2020 * bo. We currently fill all unused PTE with the shadow page and so
2021 * we should always have valid PTE following the scanout preventing
2022 * the VT-d warning.
2023 */
2024 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2025 alignment = 256 * 1024;
2026
ce453d81 2027 dev_priv->mm.interruptible = false;
2da3b9b9 2028 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 2029 if (ret)
ce453d81 2030 goto err_interruptible;
6b95a207
KH		 2031
2032 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2033 * fence, whereas 965+ only requires a fence if using
2034 * framebuffer compression. For simplicity, we always install
2035 * a fence as the cost is not that onerous.
2036 */
06d98131 2037 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2038 if (ret)
2039 goto err_unpin;
1690e1eb 2040
9a5a53b3 2041 i915_gem_object_pin_fence(obj);
6b95a207 2042
ce453d81 2043 dev_priv->mm.interruptible = true;
6b95a207 2044 return 0;
48b956c5
CW		 2045
2046err_unpin:
2047 i915_gem_object_unpin(obj);
ce453d81
CW		 2048err_interruptible:
2049 dev_priv->mm.interruptible = true;
48b956c5 2050 return ret;
6b95a207
KH		 2051}
2052
1690e1eb
CW		 2053void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2054{
2055 i915_gem_object_unpin_fence(obj);
2056 i915_gem_object_unpin(obj);
2057}
2058
c2c75131
DV		 2059/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2060 * is assumed to be a power-of-two. */
bc752862
CW		 2061unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2062 unsigned int tiling_mode,
2063 unsigned int cpp,
2064 unsigned int pitch)
c2c75131 2065{
bc752862
CW		 2066 if (tiling_mode != I915_TILING_NONE) {
2067 unsigned int tile_rows, tiles;
c2c75131 2068
bc752862
CW		 2069 tile_rows = *y / 8;
2070 *y %= 8;
c2c75131 2071
bc752862
CW		 2072 tiles = *x / (512/cpp);
2073 *x %= 512/cpp;
2074
2075 return tile_rows * pitch * 8 + tiles * 4096;
2076 } else {
2077 unsigned int offset;
2078
2079 offset = *y * pitch + *x * cpp;
2080 *y = 0;
2081 *x = (offset & 4095) / cpp;
2082 return offset & -4096;
2083 }
c2c75131
DV		 2084}
2085
17638cd6
JB		 2086static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2087 int x, int y)
81255565
JB		 2088{
2089 struct drm_device *dev = crtc->dev;
2090 struct drm_i915_private *dev_priv = dev->dev_private;
2091 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2092 struct intel_framebuffer *intel_fb;
05394f39 2093 struct drm_i915_gem_object *obj;
81255565 2094 int plane = intel_crtc->plane;
e506a0c6 2095 unsigned long linear_offset;
81255565 2096 u32 dspcntr;
5eddb70b 2097 u32 reg;
81255565
JB		 2098
2099 switch (plane) {
2100 case 0:
2101 case 1:
2102 break;
2103 default:
2104 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2105 return -EINVAL;
2106 }
2107
2108 intel_fb = to_intel_framebuffer(fb);
2109 obj = intel_fb->obj;
81255565 2110
5eddb70b
CW		 2111 reg = DSPCNTR(plane);
2112 dspcntr = I915_READ(reg);
81255565
JB		 2113 /* Mask out pixel format bits in case we change it */
2114 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2115 switch (fb->pixel_format) {
2116 case DRM_FORMAT_C8:
81255565
JB		 2117 dspcntr |= DISPPLANE_8BPP;
2118 break;
57779d06
VS		 2119 case DRM_FORMAT_XRGB1555:
2120 case DRM_FORMAT_ARGB1555:
2121 dspcntr |= DISPPLANE_BGRX555;
81255565 2122 break;
57779d06
VS		 2123 case DRM_FORMAT_RGB565:
2124 dspcntr |= DISPPLANE_BGRX565;
2125 break;
2126 case DRM_FORMAT_XRGB8888:
2127 case DRM_FORMAT_ARGB8888:
2128 dspcntr |= DISPPLANE_BGRX888;
2129 break;
2130 case DRM_FORMAT_XBGR8888:
2131 case DRM_FORMAT_ABGR8888:
2132 dspcntr |= DISPPLANE_RGBX888;
2133 break;
2134 case DRM_FORMAT_XRGB2101010:
2135 case DRM_FORMAT_ARGB2101010:
2136 dspcntr |= DISPPLANE_BGRX101010;
2137 break;
2138 case DRM_FORMAT_XBGR2101010:
2139 case DRM_FORMAT_ABGR2101010:
2140 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2141 break;
2142 default:
baba133a 2143 BUG();
81255565 2144 }
57779d06 2145
a6c45cf0 2146 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2147 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2148 dspcntr |= DISPPLANE_TILED;
2149 else
2150 dspcntr &= ~DISPPLANE_TILED;
2151 }
2152
5eddb70b 2153 I915_WRITE(reg, dspcntr);
81255565 2154
e506a0c6 2155 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2156
c2c75131
DV		 2157 if (INTEL_INFO(dev)->gen >= 4) {
2158 intel_crtc->dspaddr_offset =
bc752862
CW		 2159 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2160 fb->bits_per_pixel / 8,
2161 fb->pitches[0]);
c2c75131
DV		 2162 linear_offset -= intel_crtc->dspaddr_offset;
2163 } else {
e506a0c6 2164 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2165 }
e506a0c6
DV		 2166
2167 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2168 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2169 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2170 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2171 I915_MODIFY_DISPBASE(DSPSURF(plane),
2172 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2173 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2174 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2175 } else
e506a0c6 2176 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2177 POSTING_READ(reg);
81255565 2178
17638cd6
JB		 2179 return 0;
2180}
2181
2182static int ironlake_update_plane(struct drm_crtc *crtc,
2183 struct drm_framebuffer *fb, int x, int y)
2184{
2185 struct drm_device *dev = crtc->dev;
2186 struct drm_i915_private *dev_priv = dev->dev_private;
2187 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2188 struct intel_framebuffer *intel_fb;
2189 struct drm_i915_gem_object *obj;
2190 int plane = intel_crtc->plane;
e506a0c6 2191 unsigned long linear_offset;
17638cd6
JB		 2192 u32 dspcntr;
2193 u32 reg;
2194
2195 switch (plane) {
2196 case 0:
2197 case 1:
27f8227b 2198 case 2:
17638cd6
JB		 2199 break;
2200 default:
2201 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2202 return -EINVAL;
2203 }
2204
2205 intel_fb = to_intel_framebuffer(fb);
2206 obj = intel_fb->obj;
2207
2208 reg = DSPCNTR(plane);
2209 dspcntr = I915_READ(reg);
2210 /* Mask out pixel format bits in case we change it */
2211 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2212 switch (fb->pixel_format) {
2213 case DRM_FORMAT_C8:
17638cd6
JB		 2214 dspcntr |= DISPPLANE_8BPP;
2215 break;
57779d06
VS		 2216 case DRM_FORMAT_RGB565:
2217 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2218 break;
57779d06
VS		 2219 case DRM_FORMAT_XRGB8888:
2220 case DRM_FORMAT_ARGB8888:
2221 dspcntr |= DISPPLANE_BGRX888;
2222 break;
2223 case DRM_FORMAT_XBGR8888:
2224 case DRM_FORMAT_ABGR8888:
2225 dspcntr |= DISPPLANE_RGBX888;
2226 break;
2227 case DRM_FORMAT_XRGB2101010:
2228 case DRM_FORMAT_ARGB2101010:
2229 dspcntr |= DISPPLANE_BGRX101010;
2230 break;
2231 case DRM_FORMAT_XBGR2101010:
2232 case DRM_FORMAT_ABGR2101010:
2233 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2234 break;
2235 default:
baba133a 2236 BUG();
17638cd6
JB		 2237 }
2238
2239 if (obj->tiling_mode != I915_TILING_NONE)
2240 dspcntr |= DISPPLANE_TILED;
2241 else
2242 dspcntr &= ~DISPPLANE_TILED;
2243
2244 /* must disable */
2245 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2246
2247 I915_WRITE(reg, dspcntr);
2248
e506a0c6 2249 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2250 intel_crtc->dspaddr_offset =
bc752862
CW		 2251 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2252 fb->bits_per_pixel / 8,
2253 fb->pitches[0]);
c2c75131 2254 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2255
e506a0c6
DV		 2256 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2257 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2258 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2259 I915_MODIFY_DISPBASE(DSPSURF(plane),
2260 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2261 if (IS_HASWELL(dev)) {
2262 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2263 } else {
2264 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2265 I915_WRITE(DSPLINOFF(plane), linear_offset);
2266 }
17638cd6
JB		 2267 POSTING_READ(reg);
2268
2269 return 0;
2270}
2271
2272/* Assume fb object is pinned & idle & fenced and just update base pointers */
2273static int
2274intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2275 int x, int y, enum mode_set_atomic state)
2276{
2277 struct drm_device *dev = crtc->dev;
2278 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2279
6b8e6ed0
CW		 2280 if (dev_priv->display.disable_fbc)
2281 dev_priv->display.disable_fbc(dev);
3dec0095 2282 intel_increase_pllclock(crtc);
81255565 2283
6b8e6ed0 2284 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2285}
2286
96a02917
VS		 2287void intel_display_handle_reset(struct drm_device *dev)
2288{
2289 struct drm_i915_private *dev_priv = dev->dev_private;
2290 struct drm_crtc *crtc;
2291
2292 /*
2293 * Flips in the rings have been nuked by the reset,
2294 * so complete all pending flips so that user space
2295 * will get its events and not get stuck.
2296 *
2297 * Also update the base address of all primary
2298 * planes to the the last fb to make sure we're
2299 * showing the correct fb after a reset.
2300 *
2301 * Need to make two loops over the crtcs so that we
2302 * don't try to grab a crtc mutex before the
2303 * pending_flip_queue really got woken up.
2304 */
2305
2306 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2307 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2308 enum plane plane = intel_crtc->plane;
2309
2310 intel_prepare_page_flip(dev, plane);
2311 intel_finish_page_flip_plane(dev, plane);
2312 }
2313
2314 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2315 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2316
2317 mutex_lock(&crtc->mutex);
2318 if (intel_crtc->active)
2319 dev_priv->display.update_plane(crtc, crtc->fb,
2320 crtc->x, crtc->y);
2321 mutex_unlock(&crtc->mutex);
2322 }
2323}
2324
14667a4b
CW		 2325static int
2326intel_finish_fb(struct drm_framebuffer *old_fb)
2327{
2328 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2329 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2330 bool was_interruptible = dev_priv->mm.interruptible;
2331 int ret;
2332
14667a4b
CW		 2333 /* Big Hammer, we also need to ensure that any pending
2334 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2335 * current scanout is retired before unpinning the old
2336 * framebuffer.
2337 *
2338 * This should only fail upon a hung GPU, in which case we
2339 * can safely continue.
2340 */
2341 dev_priv->mm.interruptible = false;
2342 ret = i915_gem_object_finish_gpu(obj);
2343 dev_priv->mm.interruptible = was_interruptible;
2344
2345 return ret;
2346}
2347
198598d0
VS		 2348static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2349{
2350 struct drm_device *dev = crtc->dev;
2351 struct drm_i915_master_private *master_priv;
2352 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2353
2354 if (!dev->primary->master)
2355 return;
2356
2357 master_priv = dev->primary->master->driver_priv;
2358 if (!master_priv->sarea_priv)
2359 return;
2360
2361 switch (intel_crtc->pipe) {
2362 case 0:
2363 master_priv->sarea_priv->pipeA_x = x;
2364 master_priv->sarea_priv->pipeA_y = y;
2365 break;
2366 case 1:
2367 master_priv->sarea_priv->pipeB_x = x;
2368 master_priv->sarea_priv->pipeB_y = y;
2369 break;
2370 default:
2371 break;
2372 }
2373}
2374
5c3b82e2 2375static int
3c4fdcfb 2376intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2377 struct drm_framebuffer *fb)
79e53945
JB		 2378{
2379 struct drm_device *dev = crtc->dev;
6b8e6ed0 2380 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2381 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2382 struct drm_framebuffer *old_fb;
5c3b82e2 2383 int ret;
79e53945
JB		 2384
2385 /* no fb bound */
94352cf9 2386 if (!fb) {
a5071c2f 2387 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2388 return 0;
2389 }
2390
7eb552ae 2391 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
5826eca5
ED		 2392 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2393 intel_crtc->plane,
7eb552ae 2394 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2395 return -EINVAL;
79e53945
JB		 2396 }
2397
5c3b82e2 2398 mutex_lock(&dev->struct_mutex);
265db958 2399 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2400 to_intel_framebuffer(fb)->obj,
919926ae 2401 NULL);
5c3b82e2
CW		 2402 if (ret != 0) {
2403 mutex_unlock(&dev->struct_mutex);
a5071c2f 2404 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2405 return ret;
2406 }
79e53945 2407
94352cf9 2408 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2409 if (ret) {
94352cf9 2410 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2411 mutex_unlock(&dev->struct_mutex);
a5071c2f 2412 DRM_ERROR("failed to update base address\n");
4e6cfefc 2413 return ret;
79e53945 2414 }
3c4fdcfb 2415
94352cf9
DV		 2416 old_fb = crtc->fb;
2417 crtc->fb = fb;
6c4c86f5
DV		 2418 crtc->x = x;
2419 crtc->y = y;
94352cf9 2420
b7f1de28
CW		 2421 if (old_fb) {
2422 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2423 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2424 }
652c393a 2425
6b8e6ed0 2426 intel_update_fbc(dev);
5c3b82e2 2427 mutex_unlock(&dev->struct_mutex);
79e53945 2428
198598d0 2429 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2430
2431 return 0;
79e53945
JB		 2432}
2433
5e84e1a4
ZW		 2434static void intel_fdi_normal_train(struct drm_crtc *crtc)
2435{
2436 struct drm_device *dev = crtc->dev;
2437 struct drm_i915_private *dev_priv = dev->dev_private;
2438 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2439 int pipe = intel_crtc->pipe;
2440 u32 reg, temp;
2441
2442 /* enable normal train */
2443 reg = FDI_TX_CTL(pipe);
2444 temp = I915_READ(reg);
61e499bf 2445 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2446 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2447 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2448 } else {
2449 temp &= ~FDI_LINK_TRAIN_NONE;
2450 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2451 }
5e84e1a4
ZW		 2452 I915_WRITE(reg, temp);
2453
2454 reg = FDI_RX_CTL(pipe);
2455 temp = I915_READ(reg);
2456 if (HAS_PCH_CPT(dev)) {
2457 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2458 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2459 } else {
2460 temp &= ~FDI_LINK_TRAIN_NONE;
2461 temp |= FDI_LINK_TRAIN_NONE;
2462 }
2463 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2464
2465 /* wait one idle pattern time */
2466 POSTING_READ(reg);
2467 udelay(1000);
357555c0
JB		 2468
2469 /* IVB wants error correction enabled */
2470 if (IS_IVYBRIDGE(dev))
2471 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2472 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2473}
2474
01a415fd
DV		 2475static void ivb_modeset_global_resources(struct drm_device *dev)
2476{
2477 struct drm_i915_private *dev_priv = dev->dev_private;
2478 struct intel_crtc *pipe_B_crtc =
2479 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2480 struct intel_crtc *pipe_C_crtc =
2481 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2482 uint32_t temp;
2483
2484 /* When everything is off disable fdi C so that we could enable fdi B
2485 * with all lanes. XXX: This misses the case where a pipe is not using
2486 * any pch resources and so doesn't need any fdi lanes. */
2487 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2488 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2489 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2490
2491 temp = I915_READ(SOUTH_CHICKEN1);
2492 temp &= ~FDI_BC_BIFURCATION_SELECT;
2493 DRM_DEBUG_KMS("disabling fdi C rx\n");
2494 I915_WRITE(SOUTH_CHICKEN1, temp);
2495 }
2496}
2497
8db9d77b
ZW		 2498/* The FDI link training functions for ILK/Ibexpeak. */
2499static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2500{
2501 struct drm_device *dev = crtc->dev;
2502 struct drm_i915_private *dev_priv = dev->dev_private;
2503 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2504 int pipe = intel_crtc->pipe;
0fc932b8 2505 int plane = intel_crtc->plane;
5eddb70b 2506 u32 reg, temp, tries;
8db9d77b 2507
0fc932b8
JB		 2508 /* FDI needs bits from pipe & plane first */
2509 assert_pipe_enabled(dev_priv, pipe);
2510 assert_plane_enabled(dev_priv, plane);
2511
e1a44743
AJ		 2512 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2513 for train result */
5eddb70b
CW		 2514 reg = FDI_RX_IMR(pipe);
2515 temp = I915_READ(reg);
e1a44743
AJ		 2516 temp &= ~FDI_RX_SYMBOL_LOCK;
2517 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2518 I915_WRITE(reg, temp);
2519 I915_READ(reg);
e1a44743
AJ		 2520 udelay(150);
2521
8db9d77b 2522 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2523 reg = FDI_TX_CTL(pipe);
2524 temp = I915_READ(reg);
77ffb597
AJ		 2525 temp &= ~(7 << 19);
2526 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2527 temp &= ~FDI_LINK_TRAIN_NONE;
2528 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2529 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2530
5eddb70b
CW		 2531 reg = FDI_RX_CTL(pipe);
2532 temp = I915_READ(reg);
8db9d77b
ZW		 2533 temp &= ~FDI_LINK_TRAIN_NONE;
2534 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2535 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2536
2537 POSTING_READ(reg);
8db9d77b
ZW		 2538 udelay(150);
2539
5b2adf89 2540 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2541 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2542 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2543 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2544
5eddb70b 2545 reg = FDI_RX_IIR(pipe);
e1a44743 2546 for (tries = 0; tries < 5; tries++) {
5eddb70b 2547 temp = I915_READ(reg);
8db9d77b
ZW		 2548 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2549
2550 if ((temp & FDI_RX_BIT_LOCK)) {
2551 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2552 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2553 break;
2554 }
8db9d77b 2555 }
e1a44743 2556 if (tries == 5)
5eddb70b 2557 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2558
2559 /* Train 2 */
5eddb70b
CW		 2560 reg = FDI_TX_CTL(pipe);
2561 temp = I915_READ(reg);
8db9d77b
ZW		 2562 temp &= ~FDI_LINK_TRAIN_NONE;
2563 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2564 I915_WRITE(reg, temp);
8db9d77b 2565
5eddb70b
CW		 2566 reg = FDI_RX_CTL(pipe);
2567 temp = I915_READ(reg);
8db9d77b
ZW		 2568 temp &= ~FDI_LINK_TRAIN_NONE;
2569 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2570 I915_WRITE(reg, temp);
8db9d77b 2571
5eddb70b
CW		 2572 POSTING_READ(reg);
2573 udelay(150);
8db9d77b 2574
5eddb70b 2575 reg = FDI_RX_IIR(pipe);
e1a44743 2576 for (tries = 0; tries < 5; tries++) {
5eddb70b 2577 temp = I915_READ(reg);
8db9d77b
ZW		 2578 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2579
2580 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2581 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2582 DRM_DEBUG_KMS("FDI train 2 done.\n");
2583 break;
2584 }
8db9d77b 2585 }
e1a44743 2586 if (tries == 5)
5eddb70b 2587 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2588
2589 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2590
8db9d77b
ZW		 2591}
2592
0206e353 2593static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2594 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2595 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2596 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2597 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2598};
2599
2600/* The FDI link training functions for SNB/Cougarpoint. */
2601static void gen6_fdi_link_train(struct drm_crtc *crtc)
2602{
2603 struct drm_device *dev = crtc->dev;
2604 struct drm_i915_private *dev_priv = dev->dev_private;
2605 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2606 int pipe = intel_crtc->pipe;
fa37d39e 2607 u32 reg, temp, i, retry;
8db9d77b 2608
e1a44743
AJ		 2609 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2610 for train result */
5eddb70b
CW		 2611 reg = FDI_RX_IMR(pipe);
2612 temp = I915_READ(reg);
e1a44743
AJ		 2613 temp &= ~FDI_RX_SYMBOL_LOCK;
2614 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2615 I915_WRITE(reg, temp);
2616
2617 POSTING_READ(reg);
e1a44743
AJ		 2618 udelay(150);
2619
8db9d77b 2620 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2621 reg = FDI_TX_CTL(pipe);
2622 temp = I915_READ(reg);
77ffb597
AJ		 2623 temp &= ~(7 << 19);
2624 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2625 temp &= ~FDI_LINK_TRAIN_NONE;
2626 temp |= FDI_LINK_TRAIN_PATTERN_1;
2627 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2628 /* SNB-B */
2629 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2630 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2631
d74cf324
DV		 2632 I915_WRITE(FDI_RX_MISC(pipe),
2633 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2634
5eddb70b
CW		 2635 reg = FDI_RX_CTL(pipe);
2636 temp = I915_READ(reg);
8db9d77b
ZW		 2637 if (HAS_PCH_CPT(dev)) {
2638 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2639 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2640 } else {
2641 temp &= ~FDI_LINK_TRAIN_NONE;
2642 temp |= FDI_LINK_TRAIN_PATTERN_1;
2643 }
5eddb70b
CW		 2644 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2645
2646 POSTING_READ(reg);
8db9d77b
ZW		 2647 udelay(150);
2648
0206e353 2649 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2650 reg = FDI_TX_CTL(pipe);
2651 temp = I915_READ(reg);
8db9d77b
ZW		 2652 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2653 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2654 I915_WRITE(reg, temp);
2655
2656 POSTING_READ(reg);
8db9d77b
ZW		 2657 udelay(500);
2658
fa37d39e
SP		 2659 for (retry = 0; retry < 5; retry++) {
2660 reg = FDI_RX_IIR(pipe);
2661 temp = I915_READ(reg);
2662 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2663 if (temp & FDI_RX_BIT_LOCK) {
2664 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2665 DRM_DEBUG_KMS("FDI train 1 done.\n");
2666 break;
2667 }
2668 udelay(50);
8db9d77b 2669 }
fa37d39e
SP		 2670 if (retry < 5)
2671 break;
8db9d77b
ZW		 2672 }
2673 if (i == 4)
5eddb70b 2674 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2675
2676 /* Train 2 */
5eddb70b
CW		 2677 reg = FDI_TX_CTL(pipe);
2678 temp = I915_READ(reg);
8db9d77b
ZW		 2679 temp &= ~FDI_LINK_TRAIN_NONE;
2680 temp |= FDI_LINK_TRAIN_PATTERN_2;
2681 if (IS_GEN6(dev)) {
2682 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2683 /* SNB-B */
2684 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2685 }
5eddb70b 2686 I915_WRITE(reg, temp);
8db9d77b 2687
5eddb70b
CW		 2688 reg = FDI_RX_CTL(pipe);
2689 temp = I915_READ(reg);
8db9d77b
ZW		 2690 if (HAS_PCH_CPT(dev)) {
2691 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2692 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2693 } else {
2694 temp &= ~FDI_LINK_TRAIN_NONE;
2695 temp |= FDI_LINK_TRAIN_PATTERN_2;
2696 }
5eddb70b
CW		 2697 I915_WRITE(reg, temp);
2698
2699 POSTING_READ(reg);
8db9d77b
ZW		 2700 udelay(150);
2701
0206e353 2702 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2703 reg = FDI_TX_CTL(pipe);
2704 temp = I915_READ(reg);
8db9d77b
ZW		 2705 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2706 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2707 I915_WRITE(reg, temp);
2708
2709 POSTING_READ(reg);
8db9d77b
ZW		 2710 udelay(500);
2711
fa37d39e
SP		 2712 for (retry = 0; retry < 5; retry++) {
2713 reg = FDI_RX_IIR(pipe);
2714 temp = I915_READ(reg);
2715 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2716 if (temp & FDI_RX_SYMBOL_LOCK) {
2717 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2718 DRM_DEBUG_KMS("FDI train 2 done.\n");
2719 break;
2720 }
2721 udelay(50);
8db9d77b 2722 }
fa37d39e
SP		 2723 if (retry < 5)
2724 break;
8db9d77b
ZW		 2725 }
2726 if (i == 4)
5eddb70b 2727 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2728
2729 DRM_DEBUG_KMS("FDI train done.\n");
2730}
2731
357555c0
JB		 2732/* Manual link training for Ivy Bridge A0 parts */
2733static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2734{
2735 struct drm_device *dev = crtc->dev;
2736 struct drm_i915_private *dev_priv = dev->dev_private;
2737 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2738 int pipe = intel_crtc->pipe;
2739 u32 reg, temp, i;
2740
2741 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2742 for train result */
2743 reg = FDI_RX_IMR(pipe);
2744 temp = I915_READ(reg);
2745 temp &= ~FDI_RX_SYMBOL_LOCK;
2746 temp &= ~FDI_RX_BIT_LOCK;
2747 I915_WRITE(reg, temp);
2748
2749 POSTING_READ(reg);
2750 udelay(150);
2751
01a415fd
DV		 2752 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2753 I915_READ(FDI_RX_IIR(pipe)));
2754
357555c0
JB		 2755 /* enable CPU FDI TX and PCH FDI RX */
2756 reg = FDI_TX_CTL(pipe);
2757 temp = I915_READ(reg);
2758 temp &= ~(7 << 19);
2759 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2760 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2761 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2762 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2763 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2764 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2765 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2766
d74cf324
DV		 2767 I915_WRITE(FDI_RX_MISC(pipe),
2768 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2769
357555c0
JB		 2770 reg = FDI_RX_CTL(pipe);
2771 temp = I915_READ(reg);
2772 temp &= ~FDI_LINK_TRAIN_AUTO;
2773 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2774 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2775 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2776 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2777
2778 POSTING_READ(reg);
2779 udelay(150);
2780
0206e353 2781 for (i = 0; i < 4; i++) {
357555c0
JB		 2782 reg = FDI_TX_CTL(pipe);
2783 temp = I915_READ(reg);
2784 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2785 temp |= snb_b_fdi_train_param[i];
2786 I915_WRITE(reg, temp);
2787
2788 POSTING_READ(reg);
2789 udelay(500);
2790
2791 reg = FDI_RX_IIR(pipe);
2792 temp = I915_READ(reg);
2793 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2794
2795 if (temp & FDI_RX_BIT_LOCK ||
2796 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2797 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2798 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2799 break;
2800 }
2801 }
2802 if (i == 4)
2803 DRM_ERROR("FDI train 1 fail!\n");
2804
2805 /* Train 2 */
2806 reg = FDI_TX_CTL(pipe);
2807 temp = I915_READ(reg);
2808 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2809 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2810 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2811 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2812 I915_WRITE(reg, temp);
2813
2814 reg = FDI_RX_CTL(pipe);
2815 temp = I915_READ(reg);
2816 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2817 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2818 I915_WRITE(reg, temp);
2819
2820 POSTING_READ(reg);
2821 udelay(150);
2822
0206e353 2823 for (i = 0; i < 4; i++) {
357555c0
JB		 2824 reg = FDI_TX_CTL(pipe);
2825 temp = I915_READ(reg);
2826 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2827 temp |= snb_b_fdi_train_param[i];
2828 I915_WRITE(reg, temp);
2829
2830 POSTING_READ(reg);
2831 udelay(500);
2832
2833 reg = FDI_RX_IIR(pipe);
2834 temp = I915_READ(reg);
2835 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2836
2837 if (temp & FDI_RX_SYMBOL_LOCK) {
2838 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2839 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2840 break;
2841 }
2842 }
2843 if (i == 4)
2844 DRM_ERROR("FDI train 2 fail!\n");
2845
2846 DRM_DEBUG_KMS("FDI train done.\n");
2847}
2848
88cefb6c 2849static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2850{
88cefb6c 2851 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2852 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2853 int pipe = intel_crtc->pipe;
5eddb70b 2854 u32 reg, temp;
79e53945 2855
c64e311e 2856
c98e9dcf 2857 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2858 reg = FDI_RX_CTL(pipe);
2859 temp = I915_READ(reg);
2860 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2861 temp |= (intel_crtc->fdi_lanes - 1) << 19;
dfd07d72 2862 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2863 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2864
2865 POSTING_READ(reg);
c98e9dcf
JB		 2866 udelay(200);
2867
2868 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2869 temp = I915_READ(reg);
2870 I915_WRITE(reg, temp | FDI_PCDCLK);
2871
2872 POSTING_READ(reg);
c98e9dcf
JB		 2873 udelay(200);
2874
20749730
PZ		 2875 /* Enable CPU FDI TX PLL, always on for Ironlake */
2876 reg = FDI_TX_CTL(pipe);
2877 temp = I915_READ(reg);
2878 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2879 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2880
20749730
PZ		 2881 POSTING_READ(reg);
2882 udelay(100);
6be4a607 2883 }
0e23b99d
JB		 2884}
2885
88cefb6c
DV		 2886static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2887{
2888 struct drm_device *dev = intel_crtc->base.dev;
2889 struct drm_i915_private *dev_priv = dev->dev_private;
2890 int pipe = intel_crtc->pipe;
2891 u32 reg, temp;
2892
2893 /* Switch from PCDclk to Rawclk */
2894 reg = FDI_RX_CTL(pipe);
2895 temp = I915_READ(reg);
2896 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2897
2898 /* Disable CPU FDI TX PLL */
2899 reg = FDI_TX_CTL(pipe);
2900 temp = I915_READ(reg);
2901 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2902
2903 POSTING_READ(reg);
2904 udelay(100);
2905
2906 reg = FDI_RX_CTL(pipe);
2907 temp = I915_READ(reg);
2908 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2909
2910 /* Wait for the clocks to turn off. */
2911 POSTING_READ(reg);
2912 udelay(100);
2913}
2914
0fc932b8
JB		 2915static void ironlake_fdi_disable(struct drm_crtc *crtc)
2916{
2917 struct drm_device *dev = crtc->dev;
2918 struct drm_i915_private *dev_priv = dev->dev_private;
2919 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2920 int pipe = intel_crtc->pipe;
2921 u32 reg, temp;
2922
2923 /* disable CPU FDI tx and PCH FDI rx */
2924 reg = FDI_TX_CTL(pipe);
2925 temp = I915_READ(reg);
2926 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2927 POSTING_READ(reg);
2928
2929 reg = FDI_RX_CTL(pipe);
2930 temp = I915_READ(reg);
2931 temp &= ~(0x7 << 16);
dfd07d72 2932 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2933 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2934
2935 POSTING_READ(reg);
2936 udelay(100);
2937
2938 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2939 if (HAS_PCH_IBX(dev)) {
2940 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2941 }
0fc932b8
JB		 2942
2943 /* still set train pattern 1 */
2944 reg = FDI_TX_CTL(pipe);
2945 temp = I915_READ(reg);
2946 temp &= ~FDI_LINK_TRAIN_NONE;
2947 temp |= FDI_LINK_TRAIN_PATTERN_1;
2948 I915_WRITE(reg, temp);
2949
2950 reg = FDI_RX_CTL(pipe);
2951 temp = I915_READ(reg);
2952 if (HAS_PCH_CPT(dev)) {
2953 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2954 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2955 } else {
2956 temp &= ~FDI_LINK_TRAIN_NONE;
2957 temp |= FDI_LINK_TRAIN_PATTERN_1;
2958 }
2959 /* BPC in FDI rx is consistent with that in PIPECONF */
2960 temp &= ~(0x07 << 16);
dfd07d72 2961 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2962 I915_WRITE(reg, temp);
2963
2964 POSTING_READ(reg);
2965 udelay(100);
2966}
2967
5bb61643
CW		 2968static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2969{
2970 struct drm_device *dev = crtc->dev;
2971 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2972 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2973 unsigned long flags;
2974 bool pending;
2975
10d83730
VS		 2976 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2977 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2978 return false;
2979
2980 spin_lock_irqsave(&dev->event_lock, flags);
2981 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2982 spin_unlock_irqrestore(&dev->event_lock, flags);
2983
2984 return pending;
2985}
2986
e6c3a2a6
CW		 2987static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2988{
0f91128d 2989 struct drm_device *dev = crtc->dev;
5bb61643 2990 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2991
2992 if (crtc->fb == NULL)
2993 return;
2994
2c10d571
DV		 2995 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2996
5bb61643
CW		 2997 wait_event(dev_priv->pending_flip_queue,
2998 !intel_crtc_has_pending_flip(crtc));
2999
0f91128d
CW		 3000 mutex_lock(&dev->struct_mutex);
3001 intel_finish_fb(crtc->fb);
3002 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 3003}
3004
e615efe4
ED		 3005/* Program iCLKIP clock to the desired frequency */
3006static void lpt_program_iclkip(struct drm_crtc *crtc)
3007{
3008 struct drm_device *dev = crtc->dev;
3009 struct drm_i915_private *dev_priv = dev->dev_private;
3010 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3011 u32 temp;
3012
09153000
DV		 3013 mutex_lock(&dev_priv->dpio_lock);
3014
e615efe4
ED		 3015 /* It is necessary to ungate the pixclk gate prior to programming
3016 * the divisors, and gate it back when it is done.
3017 */
3018 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3019
3020 /* Disable SSCCTL */
3021 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3022 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3023 SBI_SSCCTL_DISABLE,
3024 SBI_ICLK);
e615efe4
ED		 3025
3026 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3027 if (crtc->mode.clock == 20000) {
3028 auxdiv = 1;
3029 divsel = 0x41;
3030 phaseinc = 0x20;
3031 } else {
3032 /* The iCLK virtual clock root frequency is in MHz,
3033 * but the crtc->mode.clock in in KHz. To get the divisors,
3034 * it is necessary to divide one by another, so we
3035 * convert the virtual clock precision to KHz here for higher
3036 * precision.
3037 */
3038 u32 iclk_virtual_root_freq = 172800 * 1000;
3039 u32 iclk_pi_range = 64;
3040 u32 desired_divisor, msb_divisor_value, pi_value;
3041
3042 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3043 msb_divisor_value = desired_divisor / iclk_pi_range;
3044 pi_value = desired_divisor % iclk_pi_range;
3045
3046 auxdiv = 0;
3047 divsel = msb_divisor_value - 2;
3048 phaseinc = pi_value;
3049 }
3050
3051 /* This should not happen with any sane values */
3052 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3053 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3054 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3055 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3056
3057 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3058 crtc->mode.clock,
3059 auxdiv,
3060 divsel,
3061 phasedir,
3062 phaseinc);
3063
3064 /* Program SSCDIVINTPHASE6 */
988d6ee8 3065 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3066 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3067 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3068 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3069 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3070 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3071 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3072 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3073
3074 /* Program SSCAUXDIV */
988d6ee8 3075 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3076 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3077 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3078 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3079
3080 /* Enable modulator and associated divider */
988d6ee8 3081 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3082 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3083 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3084
3085 /* Wait for initialization time */
3086 udelay(24);
3087
3088 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 3089
3090 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 3091}
3092
f67a559d
JB		 3093/*
3094 * Enable PCH resources required for PCH ports:
3095 * - PCH PLLs
3096 * - FDI training & RX/TX
3097 * - update transcoder timings
3098 * - DP transcoding bits
3099 * - transcoder
3100 */
3101static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3102{
3103 struct drm_device *dev = crtc->dev;
3104 struct drm_i915_private *dev_priv = dev->dev_private;
3105 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3106 int pipe = intel_crtc->pipe;
ee7b9f93 3107 u32 reg, temp;
2c07245f 3108
e7e164db
CW		 3109 assert_transcoder_disabled(dev_priv, pipe);
3110
cd986abb
DV		 3111 /* Write the TU size bits before fdi link training, so that error
3112 * detection works. */
3113 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3114 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3115
c98e9dcf 3116 /* For PCH output, training FDI link */
674cf967 3117 dev_priv->display.fdi_link_train(crtc);
2c07245f 3118
572deb37
DV		 3119 /* XXX: pch pll's can be enabled any time before we enable the PCH
3120 * transcoder, and we actually should do this to not upset any PCH
3121 * transcoder that already use the clock when we share it.
3122 *
3123 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3124 * unconditionally resets the pll - we need that to have the right LVDS
3125 * enable sequence. */
b6b4e185 3126 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 3127
303b81e0 3128 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3129 u32 sel;
4b645f14 3130
c98e9dcf 3131 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3132 switch (pipe) {
3133 default:
3134 case 0:
3135 temp |= TRANSA_DPLL_ENABLE;
3136 sel = TRANSA_DPLLB_SEL;
3137 break;
3138 case 1:
3139 temp |= TRANSB_DPLL_ENABLE;
3140 sel = TRANSB_DPLLB_SEL;
3141 break;
3142 case 2:
3143 temp |= TRANSC_DPLL_ENABLE;
3144 sel = TRANSC_DPLLB_SEL;
3145 break;
d64311ab 3146 }
ee7b9f93
JB		 3147 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3148 temp |= sel;
3149 else
3150 temp &= ~sel;
c98e9dcf 3151 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3152 }
5eddb70b 3153
d9b6cb56
JB		 3154 /* set transcoder timing, panel must allow it */
3155 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3156 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3157 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3158 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3159
5eddb70b
CW		 3160 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3161 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3162 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3163 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3164
303b81e0 3165 intel_fdi_normal_train(crtc);
5e84e1a4 3166
c98e9dcf
JB		 3167 /* For PCH DP, enable TRANS_DP_CTL */
3168 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3169 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3170 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3171 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3172 reg = TRANS_DP_CTL(pipe);
3173 temp = I915_READ(reg);
3174 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3175 TRANS_DP_SYNC_MASK |
3176 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3177 temp |= (TRANS_DP_OUTPUT_ENABLE |
3178 TRANS_DP_ENH_FRAMING);
9325c9f0 3179 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3180
3181 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3182 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3183 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3184 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3185
3186 switch (intel_trans_dp_port_sel(crtc)) {
3187 case PCH_DP_B:
5eddb70b 3188 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3189 break;
3190 case PCH_DP_C:
5eddb70b 3191 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3192 break;
3193 case PCH_DP_D:
5eddb70b 3194 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3195 break;
3196 default:
e95d41e1 3197 BUG();
32f9d658 3198 }
2c07245f 3199
5eddb70b 3200 I915_WRITE(reg, temp);
6be4a607 3201 }
b52eb4dc 3202
b8a4f404 3203 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3204}
3205
1507e5bd
PZ		 3206static void lpt_pch_enable(struct drm_crtc *crtc)
3207{
3208 struct drm_device *dev = crtc->dev;
3209 struct drm_i915_private *dev_priv = dev->dev_private;
3210 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3211 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3212
daed2dbb 3213 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3214
8c52b5e8 3215 lpt_program_iclkip(crtc);
1507e5bd 3216
0540e488 3217 /* Set transcoder timing. */
daed2dbb
PZ		 3218 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3219 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3220 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
1507e5bd 3221
daed2dbb
PZ		 3222 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3223 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3224 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3225 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
1507e5bd 3226
937bb610 3227 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3228}
3229
ee7b9f93
JB		 3230static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3231{
3232 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3233
3234 if (pll == NULL)
3235 return;
3236
3237 if (pll->refcount == 0) {
3238 WARN(1, "bad PCH PLL refcount\n");
3239 return;
3240 }
3241
3242 --pll->refcount;
3243 intel_crtc->pch_pll = NULL;
3244}
3245
3246static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3247{
3248 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3249 struct intel_pch_pll *pll;
3250 int i;
3251
3252 pll = intel_crtc->pch_pll;
3253 if (pll) {
3254 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3255 intel_crtc->base.base.id, pll->pll_reg);
3256 goto prepare;
3257 }
3258
98b6bd99
DV		 3259 if (HAS_PCH_IBX(dev_priv->dev)) {
3260 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3261 i = intel_crtc->pipe;
3262 pll = &dev_priv->pch_plls[i];
3263
3264 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3265 intel_crtc->base.base.id, pll->pll_reg);
3266
3267 goto found;
3268 }
3269
ee7b9f93
JB		 3270 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3271 pll = &dev_priv->pch_plls[i];
3272
3273 /* Only want to check enabled timings first */
3274 if (pll->refcount == 0)
3275 continue;
3276
3277 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3278 fp == I915_READ(pll->fp0_reg)) {
3279 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3280 intel_crtc->base.base.id,
3281 pll->pll_reg, pll->refcount, pll->active);
3282
3283 goto found;
3284 }
3285 }
3286
3287 /* Ok no matching timings, maybe there's a free one? */
3288 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3289 pll = &dev_priv->pch_plls[i];
3290 if (pll->refcount == 0) {
3291 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3292 intel_crtc->base.base.id, pll->pll_reg);
3293 goto found;
3294 }
3295 }
3296
3297 return NULL;
3298
3299found:
3300 intel_crtc->pch_pll = pll;
3301 pll->refcount++;
3302 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3303prepare: /* separate function? */
3304 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3305
e04c7350
CW		 3306 /* Wait for the clocks to stabilize before rewriting the regs */
3307 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3308 POSTING_READ(pll->pll_reg);
3309 udelay(150);
e04c7350
CW		 3310
3311 I915_WRITE(pll->fp0_reg, fp);
3312 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3313 pll->on = false;
3314 return pll;
3315}
3316
d4270e57
JB		 3317void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3318{
3319 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3320 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3321 u32 temp;
3322
3323 temp = I915_READ(dslreg);
3324 udelay(500);
3325 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57
JB		 3326 if (wait_for(I915_READ(dslreg) != temp, 5))
3327 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3328 }
3329}
3330
f67a559d
JB		 3331static void ironlake_crtc_enable(struct drm_crtc *crtc)
3332{
3333 struct drm_device *dev = crtc->dev;
3334 struct drm_i915_private *dev_priv = dev->dev_private;
3335 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3336 struct intel_encoder *encoder;
f67a559d
JB		 3337 int pipe = intel_crtc->pipe;
3338 int plane = intel_crtc->plane;
3339 u32 temp;
f67a559d 3340
08a48469
DV		 3341 WARN_ON(!crtc->enabled);
3342
f67a559d
JB		 3343 if (intel_crtc->active)
3344 return;
3345
3346 intel_crtc->active = true;
3347 intel_update_watermarks(dev);
3348
3349 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3350 temp = I915_READ(PCH_LVDS);
3351 if ((temp & LVDS_PORT_EN) == 0)
3352 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3353 }
3354
f67a559d 3355
5bfe2ac0 3356 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3357 /* Note: FDI PLL enabling _must_ be done before we enable the
3358 * cpu pipes, hence this is separate from all the other fdi/pch
3359 * enabling. */
88cefb6c 3360 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3361 } else {
3362 assert_fdi_tx_disabled(dev_priv, pipe);
3363 assert_fdi_rx_disabled(dev_priv, pipe);
3364 }
f67a559d 3365
bf49ec8c
DV		 3366 for_each_encoder_on_crtc(dev, crtc, encoder)
3367 if (encoder->pre_enable)
3368 encoder->pre_enable(encoder);
f67a559d
JB		 3369
3370 /* Enable panel fitting for LVDS */
3371 if (dev_priv->pch_pf_size &&
547dc041
JN		 3372 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3373 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
f67a559d
JB		 3374 /* Force use of hard-coded filter coefficients
3375 * as some pre-programmed values are broken,
3376 * e.g. x201.
3377 */
13888d78
PZ		 3378 if (IS_IVYBRIDGE(dev))
3379 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3380 PF_PIPE_SEL_IVB(pipe));
3381 else
3382 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
9db4a9c7
JB		 3383 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3384 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3385 }
3386
9c54c0dd
JB		 3387 /*
3388 * On ILK+ LUT must be loaded before the pipe is running but with
3389 * clocks enabled
3390 */
3391 intel_crtc_load_lut(crtc);
3392
5bfe2ac0
DV		 3393 intel_enable_pipe(dev_priv, pipe,
3394 intel_crtc->config.has_pch_encoder);
f67a559d
JB		 3395 intel_enable_plane(dev_priv, plane, pipe);
3396
5bfe2ac0 3397 if (intel_crtc->config.has_pch_encoder)
f67a559d 3398 ironlake_pch_enable(crtc);
c98e9dcf 3399
d1ebd816 3400 mutex_lock(&dev->struct_mutex);
bed4a673 3401 intel_update_fbc(dev);
d1ebd816
BW		 3402 mutex_unlock(&dev->struct_mutex);
3403
6b383a7f 3404 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3405
fa5c73b1
DV		 3406 for_each_encoder_on_crtc(dev, crtc, encoder)
3407 encoder->enable(encoder);
61b77ddd
DV		 3408
3409 if (HAS_PCH_CPT(dev))
3410 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3411
3412 /*
3413 * There seems to be a race in PCH platform hw (at least on some
3414 * outputs) where an enabled pipe still completes any pageflip right
3415 * away (as if the pipe is off) instead of waiting for vblank. As soon
3416 * as the first vblank happend, everything works as expected. Hence just
3417 * wait for one vblank before returning to avoid strange things
3418 * happening.
3419 */
3420 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3421}
3422
4f771f10
PZ		 3423static void haswell_crtc_enable(struct drm_crtc *crtc)
3424{
3425 struct drm_device *dev = crtc->dev;
3426 struct drm_i915_private *dev_priv = dev->dev_private;
3427 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3428 struct intel_encoder *encoder;
3429 int pipe = intel_crtc->pipe;
3430 int plane = intel_crtc->plane;
4f771f10
PZ		 3431
3432 WARN_ON(!crtc->enabled);
3433
3434 if (intel_crtc->active)
3435 return;
3436
3437 intel_crtc->active = true;
3438 intel_update_watermarks(dev);
3439
5bfe2ac0 3440 if (intel_crtc->config.has_pch_encoder)
04945641 3441 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3442
3443 for_each_encoder_on_crtc(dev, crtc, encoder)
3444 if (encoder->pre_enable)
3445 encoder->pre_enable(encoder);
3446
1f544388 3447 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3448
1f544388 3449 /* Enable panel fitting for eDP */
547dc041
JN		 3450 if (dev_priv->pch_pf_size &&
3451 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4f771f10
PZ		 3452 /* Force use of hard-coded filter coefficients
3453 * as some pre-programmed values are broken,
3454 * e.g. x201.
3455 */
54075a7d
PZ		 3456 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3457 PF_PIPE_SEL_IVB(pipe));
4f771f10
PZ		 3458 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3459 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3460 }
3461
3462 /*
3463 * On ILK+ LUT must be loaded before the pipe is running but with
3464 * clocks enabled
3465 */
3466 intel_crtc_load_lut(crtc);
3467
1f544388 3468 intel_ddi_set_pipe_settings(crtc);
8228c251 3469 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3470
5bfe2ac0
DV		 3471 intel_enable_pipe(dev_priv, pipe,
3472 intel_crtc->config.has_pch_encoder);
4f771f10
PZ		 3473 intel_enable_plane(dev_priv, plane, pipe);
3474
5bfe2ac0 3475 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3476 lpt_pch_enable(crtc);
4f771f10
PZ		 3477
3478 mutex_lock(&dev->struct_mutex);
3479 intel_update_fbc(dev);
3480 mutex_unlock(&dev->struct_mutex);
3481
3482 intel_crtc_update_cursor(crtc, true);
3483
3484 for_each_encoder_on_crtc(dev, crtc, encoder)
3485 encoder->enable(encoder);
3486
4f771f10
PZ		 3487 /*
3488 * There seems to be a race in PCH platform hw (at least on some
3489 * outputs) where an enabled pipe still completes any pageflip right
3490 * away (as if the pipe is off) instead of waiting for vblank. As soon
3491 * as the first vblank happend, everything works as expected. Hence just
3492 * wait for one vblank before returning to avoid strange things
3493 * happening.
3494 */
3495 intel_wait_for_vblank(dev, intel_crtc->pipe);
3496}
3497
6be4a607
JB		 3498static void ironlake_crtc_disable(struct drm_crtc *crtc)
3499{
3500 struct drm_device *dev = crtc->dev;
3501 struct drm_i915_private *dev_priv = dev->dev_private;
3502 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3503 struct intel_encoder *encoder;
6be4a607
JB		 3504 int pipe = intel_crtc->pipe;
3505 int plane = intel_crtc->plane;
5eddb70b 3506 u32 reg, temp;
b52eb4dc 3507
ef9c3aee 3508
f7abfe8b
CW		 3509 if (!intel_crtc->active)
3510 return;
3511
ea9d758d
DV		 3512 for_each_encoder_on_crtc(dev, crtc, encoder)
3513 encoder->disable(encoder);
3514
e6c3a2a6 3515 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3516 drm_vblank_off(dev, pipe);
6b383a7f 3517 intel_crtc_update_cursor(crtc, false);
5eddb70b 3518
b24e7179 3519 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3520
973d04f9
CW		 3521 if (dev_priv->cfb_plane == plane)
3522 intel_disable_fbc(dev);
2c07245f 3523
b24e7179 3524 intel_disable_pipe(dev_priv, pipe);
32f9d658 3525
6be4a607 3526 /* Disable PF */
9db4a9c7
JB		 3527 I915_WRITE(PF_CTL(pipe), 0);
3528 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3529
bf49ec8c
DV		 3530 for_each_encoder_on_crtc(dev, crtc, encoder)
3531 if (encoder->post_disable)
3532 encoder->post_disable(encoder);
2c07245f 3533
0fc932b8 3534 ironlake_fdi_disable(crtc);
249c0e64 3535
b8a4f404 3536 ironlake_disable_pch_transcoder(dev_priv, pipe);
913d8d11 3537
6be4a607
JB		 3538 if (HAS_PCH_CPT(dev)) {
3539 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3540 reg = TRANS_DP_CTL(pipe);
3541 temp = I915_READ(reg);
3542 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3543 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3544 I915_WRITE(reg, temp);
6be4a607
JB		 3545
3546 /* disable DPLL_SEL */
3547 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3548 switch (pipe) {
3549 case 0:
d64311ab 3550 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3551 break;
3552 case 1:
6be4a607 3553 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3554 break;
3555 case 2:
4b645f14 3556 /* C shares PLL A or B */
d64311ab 3557 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3558 break;
3559 default:
3560 BUG(); /* wtf */
3561 }
6be4a607 3562 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3563 }
e3421a18 3564
6be4a607 3565 /* disable PCH DPLL */
ee7b9f93 3566 intel_disable_pch_pll(intel_crtc);
8db9d77b 3567
88cefb6c 3568 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3569
f7abfe8b 3570 intel_crtc->active = false;
6b383a7f 3571 intel_update_watermarks(dev);
d1ebd816
BW		 3572
3573 mutex_lock(&dev->struct_mutex);
6b383a7f 3574 intel_update_fbc(dev);
d1ebd816 3575 mutex_unlock(&dev->struct_mutex);
6be4a607 3576}
1b3c7a47 3577
4f771f10 3578static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3579{
4f771f10
PZ		 3580 struct drm_device *dev = crtc->dev;
3581 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3582 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3583 struct intel_encoder *encoder;
3584 int pipe = intel_crtc->pipe;
3585 int plane = intel_crtc->plane;
3b117c8f 3586 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3587
4f771f10
PZ		 3588 if (!intel_crtc->active)
3589 return;
3590
3591 for_each_encoder_on_crtc(dev, crtc, encoder)
3592 encoder->disable(encoder);
3593
3594 intel_crtc_wait_for_pending_flips(crtc);
3595 drm_vblank_off(dev, pipe);
3596 intel_crtc_update_cursor(crtc, false);
3597
3598 intel_disable_plane(dev_priv, plane, pipe);
3599
3600 if (dev_priv->cfb_plane == plane)
3601 intel_disable_fbc(dev);
3602
3603 intel_disable_pipe(dev_priv, pipe);
3604
ad80a810 3605 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3606
f7708f78
PZ		 3607 /* XXX: Once we have proper panel fitter state tracking implemented with
3608 * hardware state read/check support we should switch to only disable
3609 * the panel fitter when we know it's used. */
3610 if (intel_using_power_well(dev)) {
3611 I915_WRITE(PF_CTL(pipe), 0);
3612 I915_WRITE(PF_WIN_SZ(pipe), 0);
3613 }
4f771f10 3614
1f544388 3615 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3616
3617 for_each_encoder_on_crtc(dev, crtc, encoder)
3618 if (encoder->post_disable)
3619 encoder->post_disable(encoder);
3620
88adfff1 3621 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3622 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 3623 intel_ddi_fdi_disable(crtc);
83616634 3624 }
4f771f10
PZ		 3625
3626 intel_crtc->active = false;
3627 intel_update_watermarks(dev);
3628
3629 mutex_lock(&dev->struct_mutex);
3630 intel_update_fbc(dev);
3631 mutex_unlock(&dev->struct_mutex);
3632}
3633
ee7b9f93
JB		 3634static void ironlake_crtc_off(struct drm_crtc *crtc)
3635{
3636 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3637 intel_put_pch_pll(intel_crtc);
3638}
3639
6441ab5f
PZ		 3640static void haswell_crtc_off(struct drm_crtc *crtc)
3641{
a5c961d1
PZ		 3642 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3643
3644 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3645 * start using it. */
3b117c8f 3646 intel_crtc->config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
a5c961d1 3647
6441ab5f
PZ		 3648 intel_ddi_put_crtc_pll(crtc);
3649}
3650
02e792fb
DV		 3651static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3652{
02e792fb 3653 if (!enable && intel_crtc->overlay) {
23f09ce3 3654 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3655 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3656
23f09ce3 3657 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3658 dev_priv->mm.interruptible = false;
3659 (void) intel_overlay_switch_off(intel_crtc->overlay);
3660 dev_priv->mm.interruptible = true;
23f09ce3 3661 mutex_unlock(&dev->struct_mutex);
02e792fb 3662 }
02e792fb 3663
5dcdbcb0
CW		 3664 /* Let userspace switch the overlay on again. In most cases userspace
3665 * has to recompute where to put it anyway.
3666 */
02e792fb
DV		 3667}
3668
61bc95c1
EE		 3669/**
3670 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3671 * cursor plane briefly if not already running after enabling the display
3672 * plane.
3673 * This workaround avoids occasional blank screens when self refresh is
3674 * enabled.
3675 */
3676static void
3677g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3678{
3679 u32 cntl = I915_READ(CURCNTR(pipe));
3680
3681 if ((cntl & CURSOR_MODE) == 0) {
3682 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3683
3684 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3685 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3686 intel_wait_for_vblank(dev_priv->dev, pipe);
3687 I915_WRITE(CURCNTR(pipe), cntl);
3688 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3689 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3690 }
3691}
3692
0b8765c6 3693static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3694{
3695 struct drm_device *dev = crtc->dev;
79e53945
JB		 3696 struct drm_i915_private *dev_priv = dev->dev_private;
3697 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3698 struct intel_encoder *encoder;
79e53945 3699 int pipe = intel_crtc->pipe;
80824003 3700 int plane = intel_crtc->plane;
79e53945 3701
08a48469
DV		 3702 WARN_ON(!crtc->enabled);
3703
f7abfe8b
CW		 3704 if (intel_crtc->active)
3705 return;
3706
3707 intel_crtc->active = true;
6b383a7f
CW		 3708 intel_update_watermarks(dev);
3709
63d7bbe9 3710 intel_enable_pll(dev_priv, pipe);
9d6d9f19
MK		 3711
3712 for_each_encoder_on_crtc(dev, crtc, encoder)
3713 if (encoder->pre_enable)
3714 encoder->pre_enable(encoder);
3715
040484af 3716 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3717 intel_enable_plane(dev_priv, plane, pipe);
61bc95c1
EE		 3718 if (IS_G4X(dev))
3719 g4x_fixup_plane(dev_priv, pipe);
79e53945 3720
0b8765c6 3721 intel_crtc_load_lut(crtc);
bed4a673 3722 intel_update_fbc(dev);
79e53945 3723
0b8765c6
JB		 3724 /* Give the overlay scaler a chance to enable if it's on this pipe */
3725 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3726 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3727
fa5c73b1
DV		 3728 for_each_encoder_on_crtc(dev, crtc, encoder)
3729 encoder->enable(encoder);
0b8765c6 3730}
79e53945 3731
87476d63
DV		 3732static void i9xx_pfit_disable(struct intel_crtc *crtc)
3733{
3734 struct drm_device *dev = crtc->base.dev;
3735 struct drm_i915_private *dev_priv = dev->dev_private;
3736 enum pipe pipe;
3737 uint32_t pctl = I915_READ(PFIT_CONTROL);
3738
3739 assert_pipe_disabled(dev_priv, crtc->pipe);
3740
3741 if (INTEL_INFO(dev)->gen >= 4)
3742 pipe = (pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT;
3743 else
3744 pipe = PIPE_B;
3745
3746 if (pipe == crtc->pipe) {
3747 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", pctl);
3748 I915_WRITE(PFIT_CONTROL, 0);
3749 }
3750}
3751
0b8765c6
JB		 3752static void i9xx_crtc_disable(struct drm_crtc *crtc)
3753{
3754 struct drm_device *dev = crtc->dev;
3755 struct drm_i915_private *dev_priv = dev->dev_private;
3756 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3757 struct intel_encoder *encoder;
0b8765c6
JB		 3758 int pipe = intel_crtc->pipe;
3759 int plane = intel_crtc->plane;
ef9c3aee 3760
f7abfe8b
CW		 3761 if (!intel_crtc->active)
3762 return;
3763
ea9d758d
DV		 3764 for_each_encoder_on_crtc(dev, crtc, encoder)
3765 encoder->disable(encoder);
3766
0b8765c6 3767 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3768 intel_crtc_wait_for_pending_flips(crtc);
3769 drm_vblank_off(dev, pipe);
0b8765c6 3770 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3771 intel_crtc_update_cursor(crtc, false);
0b8765c6 3772
973d04f9
CW		 3773 if (dev_priv->cfb_plane == plane)
3774 intel_disable_fbc(dev);
79e53945 3775
b24e7179 3776 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3777 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3778
87476d63 3779 i9xx_pfit_disable(intel_crtc);
24a1f16d 3780
63d7bbe9 3781 intel_disable_pll(dev_priv, pipe);
0b8765c6 3782
f7abfe8b 3783 intel_crtc->active = false;
6b383a7f
CW		 3784 intel_update_fbc(dev);
3785 intel_update_watermarks(dev);
0b8765c6
JB		 3786}
3787
ee7b9f93
JB		 3788static void i9xx_crtc_off(struct drm_crtc *crtc)
3789{
3790}
3791
976f8a20
DV		 3792static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3793 bool enabled)
2c07245f
ZW		 3794{
3795 struct drm_device *dev = crtc->dev;
3796 struct drm_i915_master_private *master_priv;
3797 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3798 int pipe = intel_crtc->pipe;
79e53945
JB		 3799
3800 if (!dev->primary->master)
3801 return;
3802
3803 master_priv = dev->primary->master->driver_priv;
3804 if (!master_priv->sarea_priv)
3805 return;
3806
79e53945
JB		 3807 switch (pipe) {
3808 case 0:
3809 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3810 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3811 break;
3812 case 1:
3813 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3814 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3815 break;
3816 default:
9db4a9c7 3817 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3818 break;
3819 }
79e53945
JB		 3820}
3821
976f8a20
DV		 3822/**
3823 * Sets the power management mode of the pipe and plane.
3824 */
3825void intel_crtc_update_dpms(struct drm_crtc *crtc)
3826{
3827 struct drm_device *dev = crtc->dev;
3828 struct drm_i915_private *dev_priv = dev->dev_private;
3829 struct intel_encoder *intel_encoder;
3830 bool enable = false;
3831
3832 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3833 enable |= intel_encoder->connectors_active;
3834
3835 if (enable)
3836 dev_priv->display.crtc_enable(crtc);
3837 else
3838 dev_priv->display.crtc_disable(crtc);
3839
3840 intel_crtc_update_sarea(crtc, enable);
3841}
3842
cdd59983
CW		 3843static void intel_crtc_disable(struct drm_crtc *crtc)
3844{
cdd59983 3845 struct drm_device *dev = crtc->dev;
976f8a20 3846 struct drm_connector *connector;
ee7b9f93 3847 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3848 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3849
976f8a20
DV		 3850 /* crtc should still be enabled when we disable it. */
3851 WARN_ON(!crtc->enabled);
3852
7b9f35a6 3853 intel_crtc->eld_vld = false;
976f8a20
DV		 3854 dev_priv->display.crtc_disable(crtc);
3855 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3856 dev_priv->display.off(crtc);
3857
931872fc
CW		 3858 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3859 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3860
3861 if (crtc->fb) {
3862 mutex_lock(&dev->struct_mutex);
1690e1eb 3863 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3864 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3865 crtc->fb = NULL;
3866 }
3867
3868 /* Update computed state. */
3869 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3870 if (!connector->encoder || !connector->encoder->crtc)
3871 continue;
3872
3873 if (connector->encoder->crtc != crtc)
3874 continue;
3875
3876 connector->dpms = DRM_MODE_DPMS_OFF;
3877 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3878 }
3879}
3880
a261b246 3881void intel_modeset_disable(struct drm_device *dev)
79e53945 3882{
a261b246
DV		 3883 struct drm_crtc *crtc;
3884
3885 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3886 if (crtc->enabled)
3887 intel_crtc_disable(crtc);
3888 }
79e53945
JB		 3889}
3890
ea5b213a 3891void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3892{
4ef69c7a 3893 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3894
ea5b213a
CW		 3895 drm_encoder_cleanup(encoder);
3896 kfree(intel_encoder);
7e7d76c3
JB		 3897}
3898
5ab432ef
DV		 3899/* Simple dpms helper for encodres with just one connector, no cloning and only
3900 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3901 * state of the entire output pipe. */
3902void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3903{
5ab432ef
DV		 3904 if (mode == DRM_MODE_DPMS_ON) {
3905 encoder->connectors_active = true;
3906
b2cabb0e 3907 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3908 } else {
3909 encoder->connectors_active = false;
3910
b2cabb0e 3911 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3912 }
79e53945
JB		 3913}
3914
0a91ca29
DV		 3915/* Cross check the actual hw state with our own modeset state tracking (and it's
3916 * internal consistency). */
b980514c 3917static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3918{
0a91ca29
DV		 3919 if (connector->get_hw_state(connector)) {
3920 struct intel_encoder *encoder = connector->encoder;
3921 struct drm_crtc *crtc;
3922 bool encoder_enabled;
3923 enum pipe pipe;
3924
3925 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3926 connector->base.base.id,
3927 drm_get_connector_name(&connector->base));
3928
3929 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3930 "wrong connector dpms state\n");
3931 WARN(connector->base.encoder != &encoder->base,
3932 "active connector not linked to encoder\n");
3933 WARN(!encoder->connectors_active,
3934 "encoder->connectors_active not set\n");
3935
3936 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3937 WARN(!encoder_enabled, "encoder not enabled\n");
3938 if (WARN_ON(!encoder->base.crtc))
3939 return;
3940
3941 crtc = encoder->base.crtc;
3942
3943 WARN(!crtc->enabled, "crtc not enabled\n");
3944 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3945 WARN(pipe != to_intel_crtc(crtc)->pipe,
3946 "encoder active on the wrong pipe\n");
3947 }
79e53945
JB		 3948}
3949
5ab432ef
DV		 3950/* Even simpler default implementation, if there's really no special case to
3951 * consider. */
3952void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3953{
5ab432ef 3954 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3955
5ab432ef
DV		 3956 /* All the simple cases only support two dpms states. */
3957 if (mode != DRM_MODE_DPMS_ON)
3958 mode = DRM_MODE_DPMS_OFF;
d4270e57 3959
5ab432ef
DV		 3960 if (mode == connector->dpms)
3961 return;
3962
3963 connector->dpms = mode;
3964
3965 /* Only need to change hw state when actually enabled */
3966 if (encoder->base.crtc)
3967 intel_encoder_dpms(encoder, mode);
3968 else
8af6cf88 3969 WARN_ON(encoder->connectors_active != false);
0a91ca29 3970
b980514c 3971 intel_modeset_check_state(connector->dev);
79e53945
JB		 3972}
3973
f0947c37
DV		 3974/* Simple connector->get_hw_state implementation for encoders that support only
3975 * one connector and no cloning and hence the encoder state determines the state
3976 * of the connector. */
3977bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3978{
24929352 3979 enum pipe pipe = 0;
f0947c37 3980 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3981
f0947c37 3982 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3983}
3984
b8cecdf5
DV		 3985static bool intel_crtc_compute_config(struct drm_crtc *crtc,
3986 struct intel_crtc_config *pipe_config)
79e53945 3987{
2c07245f 3988 struct drm_device *dev = crtc->dev;
b8cecdf5 3989 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 3990
bad720ff 3991 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3992 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 3993 if (pipe_config->requested_mode.clock * 3
3994 > IRONLAKE_FDI_FREQ * 4)
2377b741 3995 return false;
2c07245f 3996 }
89749350 3997
f9bef081
DV		 3998 /* All interlaced capable intel hw wants timings in frames. Note though
3999 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4000 * timings, so we need to be careful not to clobber these.*/
7ae89233 4001 if (!pipe_config->timings_set)
f9bef081 4002 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 4003
44f46b42
CW		 4004 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
4005 * with a hsync front porch of 0.
4006 */
4007 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4008 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4009 return false;
4010
bd080ee5 4011 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4012 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4013 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4014 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4015 * for lvds. */
4016 pipe_config->pipe_bpp = 8*3;
4017 }
4018
79e53945
JB		 4019 return true;
4020}
4021
25eb05fc
JB		 4022static int valleyview_get_display_clock_speed(struct drm_device *dev)
4023{
4024 return 400000; /* FIXME */
4025}
4026
e70236a8
JB		 4027static int i945_get_display_clock_speed(struct drm_device *dev)
4028{
4029 return 400000;
4030}
79e53945 4031
e70236a8 4032static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4033{
e70236a8
JB		 4034 return 333000;
4035}
79e53945 4036
e70236a8
JB		 4037static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4038{
4039 return 200000;
4040}
79e53945 4041
e70236a8
JB		 4042static int i915gm_get_display_clock_speed(struct drm_device *dev)
4043{
4044 u16 gcfgc = 0;
79e53945 4045
e70236a8
JB		 4046 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4047
4048 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4049 return 133000;
4050 else {
4051 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4052 case GC_DISPLAY_CLOCK_333_MHZ:
4053 return 333000;
4054 default:
4055 case GC_DISPLAY_CLOCK_190_200_MHZ:
4056 return 190000;
79e53945 4057 }
e70236a8
JB		 4058 }
4059}
4060
4061static int i865_get_display_clock_speed(struct drm_device *dev)
4062{
4063 return 266000;
4064}
4065
4066static int i855_get_display_clock_speed(struct drm_device *dev)
4067{
4068 u16 hpllcc = 0;
4069 /* Assume that the hardware is in the high speed state. This
4070 * should be the default.
4071 */
4072 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4073 case GC_CLOCK_133_200:
4074 case GC_CLOCK_100_200:
4075 return 200000;
4076 case GC_CLOCK_166_250:
4077 return 250000;
4078 case GC_CLOCK_100_133:
79e53945 4079 return 133000;
e70236a8 4080 }
79e53945 4081
e70236a8
JB		 4082 /* Shouldn't happen */
4083 return 0;
4084}
79e53945 4085
e70236a8
JB		 4086static int i830_get_display_clock_speed(struct drm_device *dev)
4087{
4088 return 133000;
79e53945
JB		 4089}
4090
2c07245f 4091static void
e69d0bc1 4092intel_reduce_ratio(uint32_t *num, uint32_t *den)
2c07245f
ZW		 4093{
4094 while (*num > 0xffffff || *den > 0xffffff) {
4095 *num >>= 1;
4096 *den >>= 1;
4097 }
4098}
4099
e69d0bc1
DV		 4100void
4101intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4102 int pixel_clock, int link_clock,
4103 struct intel_link_m_n *m_n)
2c07245f 4104{
e69d0bc1 4105 m_n->tu = 64;
22ed1113
CW		 4106 m_n->gmch_m = bits_per_pixel * pixel_clock;
4107 m_n->gmch_n = link_clock * nlanes * 8;
e69d0bc1 4108 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
22ed1113
CW		 4109 m_n->link_m = pixel_clock;
4110 m_n->link_n = link_clock;
e69d0bc1 4111 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4112}
4113
a7615030
CW		 4114static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4115{
72bbe58c
KP		 4116 if (i915_panel_use_ssc >= 0)
4117 return i915_panel_use_ssc != 0;
4118 return dev_priv->lvds_use_ssc
435793df 4119 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4120}
4121
a0c4da24
JB		 4122static int vlv_get_refclk(struct drm_crtc *crtc)
4123{
4124 struct drm_device *dev = crtc->dev;
4125 struct drm_i915_private *dev_priv = dev->dev_private;
4126 int refclk = 27000; /* for DP & HDMI */
4127
4128 return 100000; /* only one validated so far */
4129
4130 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4131 refclk = 96000;
4132 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4133 if (intel_panel_use_ssc(dev_priv))
4134 refclk = 100000;
4135 else
4136 refclk = 96000;
4137 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4138 refclk = 100000;
4139 }
4140
4141 return refclk;
4142}
4143
c65d77d8
JB		 4144static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4145{
4146 struct drm_device *dev = crtc->dev;
4147 struct drm_i915_private *dev_priv = dev->dev_private;
4148 int refclk;
4149
a0c4da24
JB		 4150 if (IS_VALLEYVIEW(dev)) {
4151 refclk = vlv_get_refclk(crtc);
4152 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 4153 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4154 refclk = dev_priv->lvds_ssc_freq * 1000;
4155 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4156 refclk / 1000);
4157 } else if (!IS_GEN2(dev)) {
4158 refclk = 96000;
4159 } else {
4160 refclk = 48000;
4161 }
4162
4163 return refclk;
4164}
4165
f47709a9 4166static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc *crtc)
c65d77d8 4167{
f47709a9
DV		 4168 unsigned dotclock = crtc->config.adjusted_mode.clock;
4169 struct dpll *clock = &crtc->config.dpll;
4170
c65d77d8
JB		 4171 /* SDVO TV has fixed PLL values depend on its clock range,
4172 this mirrors vbios setting. */
f47709a9 4173 if (dotclock >= 100000 && dotclock < 140500) {
c65d77d8
JB		 4174 clock->p1 = 2;
4175 clock->p2 = 10;
4176 clock->n = 3;
4177 clock->m1 = 16;
4178 clock->m2 = 8;
f47709a9 4179 } else if (dotclock >= 140500 && dotclock <= 200000) {
c65d77d8
JB		 4180 clock->p1 = 1;
4181 clock->p2 = 10;
4182 clock->n = 6;
4183 clock->m1 = 12;
4184 clock->m2 = 8;
4185 }
f47709a9
DV		 4186
4187 crtc->config.clock_set = true;
c65d77d8
JB		 4188}
4189
f47709a9 4190static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4191 intel_clock_t *reduced_clock)
4192{
f47709a9 4193 struct drm_device *dev = crtc->base.dev;
a7516a05 4194 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4195 int pipe = crtc->pipe;
a7516a05 4196 u32 fp, fp2 = 0;
f47709a9 4197 struct dpll *clock = &crtc->config.dpll;
a7516a05
JB		 4198
4199 if (IS_PINEVIEW(dev)) {
4200 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4201 if (reduced_clock)
4202 fp2 = (1 << reduced_clock->n) << 16 |
4203 reduced_clock->m1 << 8 | reduced_clock->m2;
4204 } else {
4205 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4206 if (reduced_clock)
4207 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4208 reduced_clock->m2;
4209 }
4210
4211 I915_WRITE(FP0(pipe), fp);
4212
f47709a9
DV		 4213 crtc->lowfreq_avail = false;
4214 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4215 reduced_clock && i915_powersave) {
4216 I915_WRITE(FP1(pipe), fp2);
f47709a9 4217 crtc->lowfreq_avail = true;
a7516a05
JB		 4218 } else {
4219 I915_WRITE(FP1(pipe), fp);
4220 }
4221}
4222
03afc4a2
DV		 4223static void intel_dp_set_m_n(struct intel_crtc *crtc)
4224{
4225 if (crtc->config.has_pch_encoder)
4226 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4227 else
4228 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4229}
4230
f47709a9 4231static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4232{
f47709a9 4233 struct drm_device *dev = crtc->base.dev;
a0c4da24 4234 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4235 int pipe = crtc->pipe;
a0c4da24
JB		 4236 u32 dpll, mdiv, pdiv;
4237 u32 bestn, bestm1, bestm2, bestp1, bestp2;
2a8f64ca
VP		 4238 bool is_sdvo;
4239 u32 temp;
a0c4da24 4240
09153000
DV		 4241 mutex_lock(&dev_priv->dpio_lock);
4242
f47709a9
DV		 4243 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4244 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
a0c4da24 4245
2a8f64ca
VP		 4246 dpll = DPLL_VGA_MODE_DIS;
4247 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4248 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4249 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4250
4251 I915_WRITE(DPLL(pipe), dpll);
4252 POSTING_READ(DPLL(pipe));
a0c4da24 4253
f47709a9
DV		 4254 bestn = crtc->config.dpll.n;
4255 bestm1 = crtc->config.dpll.m1;
4256 bestm2 = crtc->config.dpll.m2;
4257 bestp1 = crtc->config.dpll.p1;
4258 bestp2 = crtc->config.dpll.p2;
a0c4da24 4259
2a8f64ca
VP		 4260 /*
4261 * In Valleyview PLL and program lane counter registers are exposed
4262 * through DPIO interface
4263 */
a0c4da24
JB		 4264 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4265 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4266 mdiv |= ((bestn << DPIO_N_SHIFT));
4267 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4268 mdiv |= (1 << DPIO_K_SHIFT);
4269 mdiv |= DPIO_ENABLE_CALIBRATION;
4270 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4271
4272 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4273
2a8f64ca 4274 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
a0c4da24 4275 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
2a8f64ca
VP		 4276 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4277 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
a0c4da24
JB		 4278 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4279
2a8f64ca 4280 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
a0c4da24
JB		 4281
4282 dpll |= DPLL_VCO_ENABLE;
4283 I915_WRITE(DPLL(pipe), dpll);
4284 POSTING_READ(DPLL(pipe));
4285 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4286 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4287
2a8f64ca
VP		 4288 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4289
f47709a9
DV		 4290 if (crtc->config.has_dp_encoder)
4291 intel_dp_set_m_n(crtc);
2a8f64ca
VP		 4292
4293 I915_WRITE(DPLL(pipe), dpll);
4294
4295 /* Wait for the clocks to stabilize. */
4296 POSTING_READ(DPLL(pipe));
4297 udelay(150);
a0c4da24 4298
2a8f64ca
VP		 4299 temp = 0;
4300 if (is_sdvo) {
6cc5f341 4301 temp = 0;
f47709a9
DV		 4302 if (crtc->config.pixel_multiplier > 1) {
4303 temp = (crtc->config.pixel_multiplier - 1)
6cc5f341
DV		 4304 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4305 }
a0c4da24 4306 }
2a8f64ca
VP		 4307 I915_WRITE(DPLL_MD(pipe), temp);
4308 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4309
2a8f64ca 4310 /* Now program lane control registers */
f47709a9
DV		 4311 if(intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)
4312 || intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
2a8f64ca
VP		 4313 temp = 0x1000C4;
4314 if(pipe == 1)
4315 temp |= (1 << 21);
4316 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4317 }
f47709a9
DV		 4318
4319 if(intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) {
2a8f64ca
VP		 4320 temp = 0x1000C4;
4321 if(pipe == 1)
4322 temp |= (1 << 21);
4323 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4324 }
09153000
DV		 4325
4326 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4327}
4328
f47709a9
DV		 4329static void i9xx_update_pll(struct intel_crtc *crtc,
4330 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4331 int num_connectors)
4332{
f47709a9 4333 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4334 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4335 struct intel_encoder *encoder;
f47709a9 4336 int pipe = crtc->pipe;
eb1cbe48
DV		 4337 u32 dpll;
4338 bool is_sdvo;
f47709a9 4339 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4340
f47709a9 4341 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4342
f47709a9
DV		 4343 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4344 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4345
4346 dpll = DPLL_VGA_MODE_DIS;
4347
f47709a9 4348 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4349 dpll |= DPLLB_MODE_LVDS;
4350 else
4351 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4352
eb1cbe48 4353 if (is_sdvo) {
f47709a9 4354 if ((crtc->config.pixel_multiplier > 1) &&
6cc5f341 4355 (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
f47709a9 4356 dpll |= (crtc->config.pixel_multiplier - 1)
6cc5f341 4357 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48
DV		 4358 }
4359 dpll |= DPLL_DVO_HIGH_SPEED;
4360 }
f47709a9 4361 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
eb1cbe48
DV		 4362 dpll |= DPLL_DVO_HIGH_SPEED;
4363
4364 /* compute bitmask from p1 value */
4365 if (IS_PINEVIEW(dev))
4366 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4367 else {
4368 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4369 if (IS_G4X(dev) && reduced_clock)
4370 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4371 }
4372 switch (clock->p2) {
4373 case 5:
4374 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4375 break;
4376 case 7:
4377 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4378 break;
4379 case 10:
4380 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4381 break;
4382 case 14:
4383 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4384 break;
4385 }
4386 if (INTEL_INFO(dev)->gen >= 4)
4387 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4388
f47709a9 4389 if (is_sdvo && intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
eb1cbe48 4390 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4391 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
eb1cbe48
DV		 4392 /* XXX: just matching BIOS for now */
4393 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4394 dpll |= 3;
f47709a9 4395 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4396 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4397 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4398 else
4399 dpll |= PLL_REF_INPUT_DREFCLK;
4400
4401 dpll |= DPLL_VCO_ENABLE;
4402 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4403 POSTING_READ(DPLL(pipe));
4404 udelay(150);
4405
f47709a9 4406 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4407 if (encoder->pre_pll_enable)
4408 encoder->pre_pll_enable(encoder);
eb1cbe48 4409
f47709a9
DV		 4410 if (crtc->config.has_dp_encoder)
4411 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4412
4413 I915_WRITE(DPLL(pipe), dpll);
4414
4415 /* Wait for the clocks to stabilize. */
4416 POSTING_READ(DPLL(pipe));
4417 udelay(150);
4418
4419 if (INTEL_INFO(dev)->gen >= 4) {
4420 u32 temp = 0;
4421 if (is_sdvo) {
6cc5f341 4422 temp = 0;
f47709a9
DV		 4423 if (crtc->config.pixel_multiplier > 1) {
4424 temp = (crtc->config.pixel_multiplier - 1)
6cc5f341
DV		 4425 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4426 }
eb1cbe48
DV		 4427 }
4428 I915_WRITE(DPLL_MD(pipe), temp);
4429 } else {
4430 /* The pixel multiplier can only be updated once the
4431 * DPLL is enabled and the clocks are stable.
4432 *
4433 * So write it again.
4434 */
4435 I915_WRITE(DPLL(pipe), dpll);
4436 }
4437}
4438
f47709a9 4439static void i8xx_update_pll(struct intel_crtc *crtc,
eb1cbe48 4440 struct drm_display_mode *adjusted_mode,
f47709a9 4441 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4442 int num_connectors)
4443{
f47709a9 4444 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4445 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4446 struct intel_encoder *encoder;
f47709a9 4447 int pipe = crtc->pipe;
eb1cbe48 4448 u32 dpll;
f47709a9 4449 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4450
f47709a9 4451 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4452
eb1cbe48
DV		 4453 dpll = DPLL_VGA_MODE_DIS;
4454
f47709a9 4455 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4456 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4457 } else {
4458 if (clock->p1 == 2)
4459 dpll |= PLL_P1_DIVIDE_BY_TWO;
4460 else
4461 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4462 if (clock->p2 == 4)
4463 dpll |= PLL_P2_DIVIDE_BY_4;
4464 }
4465
f47709a9 4466 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4467 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4468 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4469 else
4470 dpll |= PLL_REF_INPUT_DREFCLK;
4471
4472 dpll |= DPLL_VCO_ENABLE;
4473 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4474 POSTING_READ(DPLL(pipe));
4475 udelay(150);
4476
f47709a9 4477 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4478 if (encoder->pre_pll_enable)
4479 encoder->pre_pll_enable(encoder);
eb1cbe48 4480
5b5896e4
DV		 4481 I915_WRITE(DPLL(pipe), dpll);
4482
4483 /* Wait for the clocks to stabilize. */
4484 POSTING_READ(DPLL(pipe));
4485 udelay(150);
4486
eb1cbe48
DV		 4487 /* The pixel multiplier can only be updated once the
4488 * DPLL is enabled and the clocks are stable.
4489 *
4490 * So write it again.
4491 */
4492 I915_WRITE(DPLL(pipe), dpll);
4493}
4494
b0e77b9c
PZ		 4495static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4496 struct drm_display_mode *mode,
4497 struct drm_display_mode *adjusted_mode)
4498{
4499 struct drm_device *dev = intel_crtc->base.dev;
4500 struct drm_i915_private *dev_priv = dev->dev_private;
4501 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4502 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
b0e77b9c
PZ		 4503 uint32_t vsyncshift;
4504
4505 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4506 /* the chip adds 2 halflines automatically */
4507 adjusted_mode->crtc_vtotal -= 1;
4508 adjusted_mode->crtc_vblank_end -= 1;
4509 vsyncshift = adjusted_mode->crtc_hsync_start
4510 - adjusted_mode->crtc_htotal / 2;
4511 } else {
4512 vsyncshift = 0;
4513 }
4514
4515 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4516 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4517
fe2b8f9d 4518 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4519 (adjusted_mode->crtc_hdisplay - 1) |
4520 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4521 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4522 (adjusted_mode->crtc_hblank_start - 1) |
4523 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4524 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4525 (adjusted_mode->crtc_hsync_start - 1) |
4526 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4527
fe2b8f9d 4528 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4529 (adjusted_mode->crtc_vdisplay - 1) |
4530 ((adjusted_mode->crtc_vtotal - 1) << 16));
fe2b8f9d 4531 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c
PZ		 4532 (adjusted_mode->crtc_vblank_start - 1) |
4533 ((adjusted_mode->crtc_vblank_end - 1) << 16));
fe2b8f9d 4534 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4535 (adjusted_mode->crtc_vsync_start - 1) |
4536 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4537
b5e508d4
PZ		 4538 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4539 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4540 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4541 * bits. */
4542 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4543 (pipe == PIPE_B || pipe == PIPE_C))
4544 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4545
b0e77b9c
PZ		 4546 /* pipesrc controls the size that is scaled from, which should
4547 * always be the user's requested size.
4548 */
4549 I915_WRITE(PIPESRC(pipe),
4550 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4551}
4552
84b046f3
DV		 4553static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4554{
4555 struct drm_device *dev = intel_crtc->base.dev;
4556 struct drm_i915_private *dev_priv = dev->dev_private;
4557 uint32_t pipeconf;
4558
4559 pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4560
4561 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4562 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4563 * core speed.
4564 *
4565 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4566 * pipe == 0 check?
4567 */
4568 if (intel_crtc->config.requested_mode.clock >
4569 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4570 pipeconf |= PIPECONF_DOUBLE_WIDE;
4571 else
4572 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4573 }
4574
4575 /* default to 8bpc */
4576 pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
4577 if (intel_crtc->config.has_dp_encoder) {
4578 if (intel_crtc->config.dither) {
4579 pipeconf |= PIPECONF_6BPC |
4580 PIPECONF_DITHER_EN |
4581 PIPECONF_DITHER_TYPE_SP;
4582 }
4583 }
4584
4585 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(&intel_crtc->base,
4586 INTEL_OUTPUT_EDP)) {
4587 if (intel_crtc->config.dither) {
4588 pipeconf |= PIPECONF_6BPC |
4589 PIPECONF_ENABLE |
4590 I965_PIPECONF_ACTIVE;
4591 }
4592 }
4593
4594 if (HAS_PIPE_CXSR(dev)) {
4595 if (intel_crtc->lowfreq_avail) {
4596 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4597 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4598 } else {
4599 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4600 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4601 }
4602 }
4603
4604 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4605 if (!IS_GEN2(dev) &&
4606 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4607 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4608 else
4609 pipeconf |= PIPECONF_PROGRESSIVE;
4610
9c8e09b7
VS		 4611 if (IS_VALLEYVIEW(dev)) {
4612 if (intel_crtc->config.limited_color_range)
4613 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4614 else
4615 pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4616 }
4617
84b046f3
DV		 4618 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4619 POSTING_READ(PIPECONF(intel_crtc->pipe));
4620}
4621
f564048e 4622static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4623 int x, int y,
94352cf9 4624 struct drm_framebuffer *fb)
79e53945
JB		 4625{
4626 struct drm_device *dev = crtc->dev;
4627 struct drm_i915_private *dev_priv = dev->dev_private;
4628 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 4629 struct drm_display_mode *adjusted_mode =
4630 &intel_crtc->config.adjusted_mode;
4631 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4632 int pipe = intel_crtc->pipe;
80824003 4633 int plane = intel_crtc->plane;
c751ce4f 4634 int refclk, num_connectors = 0;
652c393a 4635 intel_clock_t clock, reduced_clock;
84b046f3 4636 u32 dspcntr;
eb1cbe48 4637 bool ok, has_reduced_clock = false, is_sdvo = false;
8b47047b 4638 bool is_lvds = false, is_tv = false;
5eddb70b 4639 struct intel_encoder *encoder;
d4906093 4640 const intel_limit_t *limit;
5c3b82e2 4641 int ret;
79e53945 4642
6c2b7c12 4643 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4644 switch (encoder->type) {
79e53945
JB		 4645 case INTEL_OUTPUT_LVDS:
4646 is_lvds = true;
4647 break;
4648 case INTEL_OUTPUT_SDVO:
7d57382e 4649 case INTEL_OUTPUT_HDMI:
79e53945 4650 is_sdvo = true;
5eddb70b 4651 if (encoder->needs_tv_clock)
e2f0ba97 4652 is_tv = true;
79e53945 4653 break;
79e53945
JB		 4654 case INTEL_OUTPUT_TVOUT:
4655 is_tv = true;
4656 break;
79e53945 4657 }
43565a06 4658
c751ce4f 4659 num_connectors++;
79e53945
JB		 4660 }
4661
c65d77d8 4662 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4663
d4906093
ML		 4664 /*
4665 * Returns a set of divisors for the desired target clock with the given
4666 * refclk, or FALSE. The returned values represent the clock equation:
4667 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4668 */
1b894b59 4669 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4670 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4671 &clock);
79e53945
JB		 4672 if (!ok) {
4673 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4674 return -EINVAL;
79e53945
JB		 4675 }
4676
cda4b7d3 4677 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4678 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4679
ddc9003c 4680 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4681 /*
4682 * Ensure we match the reduced clock's P to the target clock.
4683 * If the clocks don't match, we can't switch the display clock
4684 * by using the FP0/FP1. In such case we will disable the LVDS
4685 * downclock feature.
4686 */
ddc9003c 4687 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4688 dev_priv->lvds_downclock,
4689 refclk,
cec2f356 4690 &clock,
5eddb70b 4691 &reduced_clock);
7026d4ac 4692 }
f47709a9
DV		 4693 /* Compat-code for transition, will disappear. */
4694 if (!intel_crtc->config.clock_set) {
4695 intel_crtc->config.dpll.n = clock.n;
4696 intel_crtc->config.dpll.m1 = clock.m1;
4697 intel_crtc->config.dpll.m2 = clock.m2;
4698 intel_crtc->config.dpll.p1 = clock.p1;
4699 intel_crtc->config.dpll.p2 = clock.p2;
4700 }
7026d4ac 4701
c65d77d8 4702 if (is_sdvo && is_tv)
f47709a9 4703 i9xx_adjust_sdvo_tv_clock(intel_crtc);
7026d4ac 4704
eb1cbe48 4705 if (IS_GEN2(dev))
f47709a9 4706 i8xx_update_pll(intel_crtc, adjusted_mode,
2a8f64ca
VP		 4707 has_reduced_clock ? &reduced_clock : NULL,
4708 num_connectors);
a0c4da24 4709 else if (IS_VALLEYVIEW(dev))
f47709a9 4710 vlv_update_pll(intel_crtc);
79e53945 4711 else
f47709a9 4712 i9xx_update_pll(intel_crtc,
eb1cbe48
DV		 4713 has_reduced_clock ? &reduced_clock : NULL,
4714 num_connectors);
79e53945 4715
79e53945
JB		 4716 /* Set up the display plane register */
4717 dspcntr = DISPPLANE_GAMMA_ENABLE;
4718
da6ecc5d
JB		 4719 if (!IS_VALLEYVIEW(dev)) {
4720 if (pipe == 0)
4721 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4722 else
4723 dspcntr |= DISPPLANE_SEL_PIPE_B;
4724 }
79e53945 4725
28c97730 4726 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4727 drm_mode_debug_printmodeline(mode);
4728
b0e77b9c 4729 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4730
4731 /* pipesrc and dspsize control the size that is scaled from,
4732 * which should always be the user's requested size.
79e53945 4733 */
929c77fb
EA		 4734 I915_WRITE(DSPSIZE(plane),
4735 ((mode->vdisplay - 1) << 16) |
4736 (mode->hdisplay - 1));
4737 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4738
84b046f3
DV		 4739 i9xx_set_pipeconf(intel_crtc);
4740
f564048e
EA		 4741 I915_WRITE(DSPCNTR(plane), dspcntr);
4742 POSTING_READ(DSPCNTR(plane));
4743
94352cf9 4744 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4745
4746 intel_update_watermarks(dev);
4747
f564048e
EA		 4748 return ret;
4749}
4750
0e8ffe1b
DV		 4751static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4752 struct intel_crtc_config *pipe_config)
4753{
4754 struct drm_device *dev = crtc->base.dev;
4755 struct drm_i915_private *dev_priv = dev->dev_private;
4756 uint32_t tmp;
4757
4758 tmp = I915_READ(PIPECONF(crtc->pipe));
4759 if (!(tmp & PIPECONF_ENABLE))
4760 return false;
4761
4762 return true;
4763}
4764
dde86e2d 4765static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4766{
4767 struct drm_i915_private *dev_priv = dev->dev_private;
4768 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4769 struct intel_encoder *encoder;
74cfd7ac 4770 u32 val, final;
13d83a67 4771 bool has_lvds = false;
199e5d79
KP		 4772 bool has_cpu_edp = false;
4773 bool has_pch_edp = false;
4774 bool has_panel = false;
99eb6a01
KP		 4775 bool has_ck505 = false;
4776 bool can_ssc = false;
13d83a67
JB		 4777
4778 /* We need to take the global config into account */
199e5d79
KP		 4779 list_for_each_entry(encoder, &mode_config->encoder_list,
4780 base.head) {
4781 switch (encoder->type) {
4782 case INTEL_OUTPUT_LVDS:
4783 has_panel = true;
4784 has_lvds = true;
4785 break;
4786 case INTEL_OUTPUT_EDP:
4787 has_panel = true;
4788 if (intel_encoder_is_pch_edp(&encoder->base))
4789 has_pch_edp = true;
4790 else
4791 has_cpu_edp = true;
4792 break;
13d83a67
JB		 4793 }
4794 }
4795
99eb6a01
KP		 4796 if (HAS_PCH_IBX(dev)) {
4797 has_ck505 = dev_priv->display_clock_mode;
4798 can_ssc = has_ck505;
4799 } else {
4800 has_ck505 = false;
4801 can_ssc = true;
4802 }
4803
4804 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4805 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4806 has_ck505);
13d83a67
JB		 4807
4808 /* Ironlake: try to setup display ref clock before DPLL
4809 * enabling. This is only under driver's control after
4810 * PCH B stepping, previous chipset stepping should be
4811 * ignoring this setting.
4812 */
74cfd7ac
CW		 4813 val = I915_READ(PCH_DREF_CONTROL);
4814
4815 /* As we must carefully and slowly disable/enable each source in turn,
4816 * compute the final state we want first and check if we need to
4817 * make any changes at all.
4818 */
4819 final = val;
4820 final &= ~DREF_NONSPREAD_SOURCE_MASK;
4821 if (has_ck505)
4822 final |= DREF_NONSPREAD_CK505_ENABLE;
4823 else
4824 final |= DREF_NONSPREAD_SOURCE_ENABLE;
4825
4826 final &= ~DREF_SSC_SOURCE_MASK;
4827 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4828 final &= ~DREF_SSC1_ENABLE;
4829
4830 if (has_panel) {
4831 final |= DREF_SSC_SOURCE_ENABLE;
4832
4833 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4834 final |= DREF_SSC1_ENABLE;
4835
4836 if (has_cpu_edp) {
4837 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4838 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4839 else
4840 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4841 } else
4842 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4843 } else {
4844 final |= DREF_SSC_SOURCE_DISABLE;
4845 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4846 }
4847
4848 if (final == val)
4849 return;
4850
13d83a67 4851 /* Always enable nonspread source */
74cfd7ac 4852 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4853
99eb6a01 4854 if (has_ck505)
74cfd7ac 4855 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 4856 else
74cfd7ac 4857 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4858
199e5d79 4859 if (has_panel) {
74cfd7ac
CW		 4860 val &= ~DREF_SSC_SOURCE_MASK;
4861 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4862
199e5d79 4863 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4864 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4865 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 4866 val |= DREF_SSC1_ENABLE;
e77166b5 4867 } else
74cfd7ac 4868 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4869
4870 /* Get SSC going before enabling the outputs */
74cfd7ac 4871 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 4872 POSTING_READ(PCH_DREF_CONTROL);
4873 udelay(200);
4874
74cfd7ac 4875 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 4876
4877 /* Enable CPU source on CPU attached eDP */
199e5d79 4878 if (has_cpu_edp) {
99eb6a01 4879 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4880 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 4881 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4882 }
13d83a67 4883 else
74cfd7ac 4884 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 4885 } else
74cfd7ac 4886 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 4887
74cfd7ac 4888 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 4889 POSTING_READ(PCH_DREF_CONTROL);
4890 udelay(200);
4891 } else {
4892 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4893
74cfd7ac 4894 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 4895
4896 /* Turn off CPU output */
74cfd7ac 4897 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 4898
74cfd7ac 4899 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 4900 POSTING_READ(PCH_DREF_CONTROL);
4901 udelay(200);
4902
4903 /* Turn off the SSC source */
74cfd7ac
CW		 4904 val &= ~DREF_SSC_SOURCE_MASK;
4905 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 4906
4907 /* Turn off SSC1 */
74cfd7ac 4908 val &= ~DREF_SSC1_ENABLE;
199e5d79 4909
74cfd7ac 4910 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 4911 POSTING_READ(PCH_DREF_CONTROL);
4912 udelay(200);
4913 }
74cfd7ac
CW		 4914
4915 BUG_ON(val != final);
13d83a67
JB		 4916}
4917
dde86e2d
PZ		 4918/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4919static void lpt_init_pch_refclk(struct drm_device *dev)
4920{
4921 struct drm_i915_private *dev_priv = dev->dev_private;
4922 struct drm_mode_config *mode_config = &dev->mode_config;
4923 struct intel_encoder *encoder;
4924 bool has_vga = false;
4925 bool is_sdv = false;
4926 u32 tmp;
4927
4928 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4929 switch (encoder->type) {
4930 case INTEL_OUTPUT_ANALOG:
4931 has_vga = true;
4932 break;
4933 }
4934 }
4935
4936 if (!has_vga)
4937 return;
4938
c00db246
DV		 4939 mutex_lock(&dev_priv->dpio_lock);
4940
dde86e2d
PZ		 4941 /* XXX: Rip out SDV support once Haswell ships for real. */
4942 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
4943 is_sdv = true;
4944
4945 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4946 tmp &= ~SBI_SSCCTL_DISABLE;
4947 tmp |= SBI_SSCCTL_PATHALT;
4948 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4949
4950 udelay(24);
4951
4952 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4953 tmp &= ~SBI_SSCCTL_PATHALT;
4954 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4955
4956 if (!is_sdv) {
4957 tmp = I915_READ(SOUTH_CHICKEN2);
4958 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
4959 I915_WRITE(SOUTH_CHICKEN2, tmp);
4960
4961 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
4962 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
4963 DRM_ERROR("FDI mPHY reset assert timeout\n");
4964
4965 tmp = I915_READ(SOUTH_CHICKEN2);
4966 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
4967 I915_WRITE(SOUTH_CHICKEN2, tmp);
4968
4969 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
4970 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
4971 100))
4972 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
4973 }
4974
4975 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
4976 tmp &= ~(0xFF << 24);
4977 tmp |= (0x12 << 24);
4978 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
4979
dde86e2d
PZ		 4980 if (is_sdv) {
4981 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
4982 tmp |= 0x7FFF;
4983 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
4984 }
4985
4986 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
4987 tmp |= (1 << 11);
4988 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
4989
4990 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
4991 tmp |= (1 << 11);
4992 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
4993
4994 if (is_sdv) {
4995 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
4996 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4997 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
4998
4999 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5000 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5001 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5002
5003 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5004 tmp |= (0x3F << 8);
5005 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5006
5007 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5008 tmp |= (0x3F << 8);
5009 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5010 }
5011
5012 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5013 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5014 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5015
5016 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5017 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5018 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5019
5020 if (!is_sdv) {
5021 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5022 tmp &= ~(7 << 13);
5023 tmp |= (5 << 13);
5024 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5025
5026 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5027 tmp &= ~(7 << 13);
5028 tmp |= (5 << 13);
5029 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5030 }
5031
5032 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5033 tmp &= ~0xFF;
5034 tmp |= 0x1C;
5035 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5036
5037 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5038 tmp &= ~0xFF;
5039 tmp |= 0x1C;
5040 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5041
5042 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5043 tmp &= ~(0xFF << 16);
5044 tmp |= (0x1C << 16);
5045 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5046
5047 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5048 tmp &= ~(0xFF << 16);
5049 tmp |= (0x1C << 16);
5050 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5051
5052 if (!is_sdv) {
5053 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5054 tmp |= (1 << 27);
5055 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5056
5057 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5058 tmp |= (1 << 27);
5059 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5060
5061 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5062 tmp &= ~(0xF << 28);
5063 tmp |= (4 << 28);
5064 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5065
5066 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5067 tmp &= ~(0xF << 28);
5068 tmp |= (4 << 28);
5069 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5070 }
5071
5072 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5073 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5074 tmp |= SBI_DBUFF0_ENABLE;
5075 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5076
5077 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5078}
5079
5080/*
5081 * Initialize reference clocks when the driver loads
5082 */
5083void intel_init_pch_refclk(struct drm_device *dev)
5084{
5085 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5086 ironlake_init_pch_refclk(dev);
5087 else if (HAS_PCH_LPT(dev))
5088 lpt_init_pch_refclk(dev);
5089}
5090
d9d444cb
JB		 5091static int ironlake_get_refclk(struct drm_crtc *crtc)
5092{
5093 struct drm_device *dev = crtc->dev;
5094 struct drm_i915_private *dev_priv = dev->dev_private;
5095 struct intel_encoder *encoder;
d9d444cb
JB		 5096 struct intel_encoder *edp_encoder = NULL;
5097 int num_connectors = 0;
5098 bool is_lvds = false;
5099
6c2b7c12 5100 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5101 switch (encoder->type) {
5102 case INTEL_OUTPUT_LVDS:
5103 is_lvds = true;
5104 break;
5105 case INTEL_OUTPUT_EDP:
5106 edp_encoder = encoder;
5107 break;
5108 }
5109 num_connectors++;
5110 }
5111
5112 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5113 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5114 dev_priv->lvds_ssc_freq);
5115 return dev_priv->lvds_ssc_freq * 1000;
5116 }
5117
5118 return 120000;
5119}
5120
c8203565 5121static void ironlake_set_pipeconf(struct drm_crtc *crtc,
f564048e 5122 struct drm_display_mode *adjusted_mode,
c8203565 5123 bool dither)
79e53945 5124{
c8203565 5125 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5126 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5127 int pipe = intel_crtc->pipe;
c8203565
PZ		 5128 uint32_t val;
5129
5130 val = I915_READ(PIPECONF(pipe));
5131
dfd07d72 5132 val &= ~PIPECONF_BPC_MASK;
965e0c48 5133 switch (intel_crtc->config.pipe_bpp) {
c8203565 5134 case 18:
dfd07d72 5135 val |= PIPECONF_6BPC;
c8203565
PZ		 5136 break;
5137 case 24:
dfd07d72 5138 val |= PIPECONF_8BPC;
c8203565
PZ		 5139 break;
5140 case 30:
dfd07d72 5141 val |= PIPECONF_10BPC;
c8203565
PZ		 5142 break;
5143 case 36:
dfd07d72 5144 val |= PIPECONF_12BPC;
c8203565
PZ		 5145 break;
5146 default:
cc769b62
PZ		 5147 /* Case prevented by intel_choose_pipe_bpp_dither. */
5148 BUG();
c8203565
PZ		 5149 }
5150
5151 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5152 if (dither)
5153 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5154
5155 val &= ~PIPECONF_INTERLACE_MASK;
5156 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5157 val |= PIPECONF_INTERLACED_ILK;
5158 else
5159 val |= PIPECONF_PROGRESSIVE;
5160
50f3b016 5161 if (intel_crtc->config.limited_color_range)
3685a8f3
VS		 5162 val |= PIPECONF_COLOR_RANGE_SELECT;
5163 else
5164 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5165
c8203565
PZ		 5166 I915_WRITE(PIPECONF(pipe), val);
5167 POSTING_READ(PIPECONF(pipe));
5168}
5169
86d3efce
VS		 5170/*
5171 * Set up the pipe CSC unit.
5172 *
5173 * Currently only full range RGB to limited range RGB conversion
5174 * is supported, but eventually this should handle various
5175 * RGB<->YCbCr scenarios as well.
5176 */
50f3b016 5177static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5178{
5179 struct drm_device *dev = crtc->dev;
5180 struct drm_i915_private *dev_priv = dev->dev_private;
5181 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5182 int pipe = intel_crtc->pipe;
5183 uint16_t coeff = 0x7800; /* 1.0 */
5184
5185 /*
5186 * TODO: Check what kind of values actually come out of the pipe
5187 * with these coeff/postoff values and adjust to get the best
5188 * accuracy. Perhaps we even need to take the bpc value into
5189 * consideration.
5190 */
5191
50f3b016 5192 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5193 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5194
5195 /*
5196 * GY/GU and RY/RU should be the other way around according
5197 * to BSpec, but reality doesn't agree. Just set them up in
5198 * a way that results in the correct picture.
5199 */
5200 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5201 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5202
5203 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5204 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5205
5206 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5207 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5208
5209 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5210 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5211 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5212
5213 if (INTEL_INFO(dev)->gen > 6) {
5214 uint16_t postoff = 0;
5215
50f3b016 5216 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5217 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5218
5219 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5220 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5221 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5222
5223 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5224 } else {
5225 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5226
50f3b016 5227 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5228 mode |= CSC_BLACK_SCREEN_OFFSET;
5229
5230 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5231 }
5232}
5233
ee2b0b38
PZ		 5234static void haswell_set_pipeconf(struct drm_crtc *crtc,
5235 struct drm_display_mode *adjusted_mode,
5236 bool dither)
5237{
5238 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5239 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5240 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5241 uint32_t val;
5242
702e7a56 5243 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5244
5245 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5246 if (dither)
5247 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5248
5249 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5250 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5251 val |= PIPECONF_INTERLACED_ILK;
5252 else
5253 val |= PIPECONF_PROGRESSIVE;
5254
702e7a56
PZ		 5255 I915_WRITE(PIPECONF(cpu_transcoder), val);
5256 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5257}
5258
6591c6e4
PZ		 5259static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5260 struct drm_display_mode *adjusted_mode,
5261 intel_clock_t *clock,
5262 bool *has_reduced_clock,
5263 intel_clock_t *reduced_clock)
5264{
5265 struct drm_device *dev = crtc->dev;
5266 struct drm_i915_private *dev_priv = dev->dev_private;
5267 struct intel_encoder *intel_encoder;
5268 int refclk;
d4906093 5269 const intel_limit_t *limit;
6591c6e4 5270 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
79e53945 5271
6591c6e4
PZ		 5272 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5273 switch (intel_encoder->type) {
79e53945
JB		 5274 case INTEL_OUTPUT_LVDS:
5275 is_lvds = true;
5276 break;
5277 case INTEL_OUTPUT_SDVO:
7d57382e 5278 case INTEL_OUTPUT_HDMI:
79e53945 5279 is_sdvo = true;
6591c6e4 5280 if (intel_encoder->needs_tv_clock)
e2f0ba97 5281 is_tv = true;
79e53945 5282 break;
79e53945
JB		 5283 case INTEL_OUTPUT_TVOUT:
5284 is_tv = true;
5285 break;
79e53945
JB		 5286 }
5287 }
5288
d9d444cb 5289 refclk = ironlake_get_refclk(crtc);
79e53945 5290
d4906093
ML		 5291 /*
5292 * Returns a set of divisors for the desired target clock with the given
5293 * refclk, or FALSE. The returned values represent the clock equation:
5294 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5295 */
1b894b59 5296 limit = intel_limit(crtc, refclk);
6591c6e4
PZ		 5297 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5298 clock);
5299 if (!ret)
5300 return false;
cda4b7d3 5301
ddc9003c 5302 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5303 /*
5304 * Ensure we match the reduced clock's P to the target clock.
5305 * If the clocks don't match, we can't switch the display clock
5306 * by using the FP0/FP1. In such case we will disable the LVDS
5307 * downclock feature.
5308 */
6591c6e4
PZ		 5309 *has_reduced_clock = limit->find_pll(limit, crtc,
5310 dev_priv->lvds_downclock,
5311 refclk,
5312 clock,
5313 reduced_clock);
652c393a 5314 }
61e9653f
DV		 5315
5316 if (is_sdvo && is_tv)
f47709a9 5317 i9xx_adjust_sdvo_tv_clock(to_intel_crtc(crtc));
6591c6e4
PZ		 5318
5319 return true;
5320}
5321
01a415fd
DV		 5322static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5323{
5324 struct drm_i915_private *dev_priv = dev->dev_private;
5325 uint32_t temp;
5326
5327 temp = I915_READ(SOUTH_CHICKEN1);
5328 if (temp & FDI_BC_BIFURCATION_SELECT)
5329 return;
5330
5331 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5332 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5333
5334 temp |= FDI_BC_BIFURCATION_SELECT;
5335 DRM_DEBUG_KMS("enabling fdi C rx\n");
5336 I915_WRITE(SOUTH_CHICKEN1, temp);
5337 POSTING_READ(SOUTH_CHICKEN1);
5338}
5339
5340static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5341{
5342 struct drm_device *dev = intel_crtc->base.dev;
5343 struct drm_i915_private *dev_priv = dev->dev_private;
5344 struct intel_crtc *pipe_B_crtc =
5345 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5346
5347 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5348 intel_crtc->pipe, intel_crtc->fdi_lanes);
5349 if (intel_crtc->fdi_lanes > 4) {
5350 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5351 intel_crtc->pipe, intel_crtc->fdi_lanes);
5352 /* Clamp lanes to avoid programming the hw with bogus values. */
5353 intel_crtc->fdi_lanes = 4;
5354
5355 return false;
5356 }
5357
7eb552ae 5358 if (INTEL_INFO(dev)->num_pipes == 2)
01a415fd
DV		 5359 return true;
5360
5361 switch (intel_crtc->pipe) {
5362 case PIPE_A:
5363 return true;
5364 case PIPE_B:
5365 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5366 intel_crtc->fdi_lanes > 2) {
5367 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5368 intel_crtc->pipe, intel_crtc->fdi_lanes);
5369 /* Clamp lanes to avoid programming the hw with bogus values. */
5370 intel_crtc->fdi_lanes = 2;
5371
5372 return false;
5373 }
5374
5375 if (intel_crtc->fdi_lanes > 2)
5376 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5377 else
5378 cpt_enable_fdi_bc_bifurcation(dev);
5379
5380 return true;
5381 case PIPE_C:
5382 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5383 if (intel_crtc->fdi_lanes > 2) {
5384 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5385 intel_crtc->pipe, intel_crtc->fdi_lanes);
5386 /* Clamp lanes to avoid programming the hw with bogus values. */
5387 intel_crtc->fdi_lanes = 2;
5388
5389 return false;
5390 }
5391 } else {
5392 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5393 return false;
5394 }
5395
5396 cpt_enable_fdi_bc_bifurcation(dev);
5397
5398 return true;
5399 default:
5400 BUG();
5401 }
5402}
5403
d4b1931c
PZ		 5404int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5405{
5406 /*
5407 * Account for spread spectrum to avoid
5408 * oversubscribing the link. Max center spread
5409 * is 2.5%; use 5% for safety's sake.
5410 */
5411 u32 bps = target_clock * bpp * 21 / 20;
5412 return bps / (link_bw * 8) + 1;
5413}
5414
6cf86a5e
DV		 5415void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5416 struct intel_link_m_n *m_n)
79e53945 5417{
6cf86a5e
DV		 5418 struct drm_device *dev = crtc->base.dev;
5419 struct drm_i915_private *dev_priv = dev->dev_private;
5420 int pipe = crtc->pipe;
5421
5422 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5423 I915_WRITE(TRANSDATA_N1(pipe), m_n->gmch_n);
5424 I915_WRITE(TRANSDPLINK_M1(pipe), m_n->link_m);
5425 I915_WRITE(TRANSDPLINK_N1(pipe), m_n->link_n);
5426}
5427
5428void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5429 struct intel_link_m_n *m_n)
5430{
5431 struct drm_device *dev = crtc->base.dev;
79e53945 5432 struct drm_i915_private *dev_priv = dev->dev_private;
6cf86a5e 5433 int pipe = crtc->pipe;
3b117c8f 5434 enum transcoder transcoder = crtc->config.cpu_transcoder;
6cf86a5e
DV		 5435
5436 if (INTEL_INFO(dev)->gen >= 5) {
5437 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5438 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5439 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5440 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5441 } else {
5442 I915_WRITE(PIPE_GMCH_DATA_M(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5443 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n->gmch_n);
5444 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n->link_m);
5445 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n->link_n);
5446 }
5447}
5448
5449static void ironlake_fdi_set_m_n(struct drm_crtc *crtc)
5450{
5451 struct drm_device *dev = crtc->dev;
79e53945 5452 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6cc5f341
DV		 5453 struct drm_display_mode *adjusted_mode =
5454 &intel_crtc->config.adjusted_mode;
e69d0bc1 5455 struct intel_link_m_n m_n = {0};
6cc5f341 5456 int target_clock, lane, link_bw;
61e9653f 5457
6cf86a5e
DV		 5458 /* FDI is a binary signal running at ~2.7GHz, encoding
5459 * each output octet as 10 bits. The actual frequency
5460 * is stored as a divider into a 100MHz clock, and the
5461 * mode pixel clock is stored in units of 1KHz.
5462 * Hence the bw of each lane in terms of the mode signal
5463 * is:
5464 */
5465 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
58a27471 5466
df92b1e6
DV		 5467 if (intel_crtc->config.pixel_target_clock)
5468 target_clock = intel_crtc->config.pixel_target_clock;
94bf2ced
DV		 5469 else
5470 target_clock = adjusted_mode->clock;
5471
6cf86a5e
DV		 5472 lane = ironlake_get_lanes_required(target_clock, link_bw,
5473 intel_crtc->config.pipe_bpp);
2c07245f 5474
8febb297
EA		 5475 intel_crtc->fdi_lanes = lane;
5476
6cc5f341
DV		 5477 if (intel_crtc->config.pixel_multiplier > 1)
5478 link_bw *= intel_crtc->config.pixel_multiplier;
965e0c48
DV		 5479 intel_link_compute_m_n(intel_crtc->config.pipe_bpp, lane, target_clock,
5480 link_bw, &m_n);
8febb297 5481
6cf86a5e 5482 intel_cpu_transcoder_set_m_n(intel_crtc, &m_n);
f48d8f23
PZ		 5483}
5484
de13a2e3 5485static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
9a7c7890
DV		 5486 intel_clock_t *clock, u32 *fp,
5487 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5488{
de13a2e3 5489 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5490 struct drm_device *dev = crtc->dev;
5491 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5492 struct intel_encoder *intel_encoder;
5493 uint32_t dpll;
6cc5f341 5494 int factor, num_connectors = 0;
de13a2e3 5495 bool is_lvds = false, is_sdvo = false, is_tv = false;
79e53945 5496
de13a2e3
PZ		 5497 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5498 switch (intel_encoder->type) {
79e53945
JB		 5499 case INTEL_OUTPUT_LVDS:
5500 is_lvds = true;
5501 break;
5502 case INTEL_OUTPUT_SDVO:
7d57382e 5503 case INTEL_OUTPUT_HDMI:
79e53945 5504 is_sdvo = true;
de13a2e3 5505 if (intel_encoder->needs_tv_clock)
e2f0ba97 5506 is_tv = true;
79e53945 5507 break;
79e53945
JB		 5508 case INTEL_OUTPUT_TVOUT:
5509 is_tv = true;
5510 break;
79e53945 5511 }
43565a06 5512
c751ce4f 5513 num_connectors++;
79e53945 5514 }
79e53945 5515
c1858123 5516 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5517 factor = 21;
5518 if (is_lvds) {
5519 if ((intel_panel_use_ssc(dev_priv) &&
5520 dev_priv->lvds_ssc_freq == 100) ||
f0b44056 5521 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297
EA		 5522 factor = 25;
5523 } else if (is_sdvo && is_tv)
5524 factor = 20;
c1858123 5525
de13a2e3 5526 if (clock->m < factor * clock->n)
7d0ac5b7 5527 *fp |= FP_CB_TUNE;
2c07245f 5528
9a7c7890
DV		 5529 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5530 *fp2 |= FP_CB_TUNE;
5531
5eddb70b 5532 dpll = 0;
2c07245f 5533
a07d6787
EA		 5534 if (is_lvds)
5535 dpll |= DPLLB_MODE_LVDS;
5536 else
5537 dpll |= DPLLB_MODE_DAC_SERIAL;
5538 if (is_sdvo) {
6cc5f341
DV		 5539 if (intel_crtc->config.pixel_multiplier > 1) {
5540 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5541 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5542 }
a07d6787
EA		 5543 dpll |= DPLL_DVO_HIGH_SPEED;
5544 }
8b47047b
DV		 5545 if (intel_crtc->config.has_dp_encoder &&
5546 intel_crtc->config.has_pch_encoder)
a07d6787 5547 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5548
a07d6787 5549 /* compute bitmask from p1 value */
de13a2e3 5550 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5551 /* also FPA1 */
de13a2e3 5552 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5553
de13a2e3 5554 switch (clock->p2) {
a07d6787
EA		 5555 case 5:
5556 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5557 break;
5558 case 7:
5559 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5560 break;
5561 case 10:
5562 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5563 break;
5564 case 14:
5565 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5566 break;
79e53945
JB		 5567 }
5568
43565a06
KH		 5569 if (is_sdvo && is_tv)
5570 dpll |= PLL_REF_INPUT_TVCLKINBC;
5571 else if (is_tv)
79e53945 5572 /* XXX: just matching BIOS for now */
43565a06 5573 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5574 dpll |= 3;
a7615030 5575 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5576 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5577 else
5578 dpll |= PLL_REF_INPUT_DREFCLK;
5579
de13a2e3
PZ		 5580 return dpll;
5581}
5582
5583static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5584 int x, int y,
5585 struct drm_framebuffer *fb)
5586{
5587 struct drm_device *dev = crtc->dev;
5588 struct drm_i915_private *dev_priv = dev->dev_private;
5589 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5590 struct drm_display_mode *adjusted_mode =
5591 &intel_crtc->config.adjusted_mode;
5592 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
de13a2e3
PZ		 5593 int pipe = intel_crtc->pipe;
5594 int plane = intel_crtc->plane;
5595 int num_connectors = 0;
5596 intel_clock_t clock, reduced_clock;
5597 u32 dpll, fp = 0, fp2 = 0;
e2f12b07 5598 bool ok, has_reduced_clock = false;
8b47047b 5599 bool is_lvds = false;
de13a2e3 5600 struct intel_encoder *encoder;
de13a2e3 5601 int ret;
01a415fd 5602 bool dither, fdi_config_ok;
de13a2e3
PZ		 5603
5604 for_each_encoder_on_crtc(dev, crtc, encoder) {
5605 switch (encoder->type) {
5606 case INTEL_OUTPUT_LVDS:
5607 is_lvds = true;
5608 break;
de13a2e3
PZ		 5609 }
5610
5611 num_connectors++;
a07d6787 5612 }
79e53945 5613
5dc5298b
PZ		 5614 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5615 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5616
3b117c8f 5617 intel_crtc->config.cpu_transcoder = pipe;
6cf86a5e 5618
de13a2e3
PZ		 5619 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5620 &has_reduced_clock, &reduced_clock);
5621 if (!ok) {
5622 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5623 return -EINVAL;
79e53945 5624 }
f47709a9
DV		 5625 /* Compat-code for transition, will disappear. */
5626 if (!intel_crtc->config.clock_set) {
5627 intel_crtc->config.dpll.n = clock.n;
5628 intel_crtc->config.dpll.m1 = clock.m1;
5629 intel_crtc->config.dpll.m2 = clock.m2;
5630 intel_crtc->config.dpll.p1 = clock.p1;
5631 intel_crtc->config.dpll.p2 = clock.p2;
5632 }
79e53945 5633
de13a2e3
PZ		 5634 /* Ensure that the cursor is valid for the new mode before changing... */
5635 intel_crtc_update_cursor(crtc, true);
5636
5637 /* determine panel color depth */
4e53c2e0 5638 dither = intel_crtc->config.dither;
de13a2e3
PZ		 5639 if (is_lvds && dev_priv->lvds_dither)
5640 dither = true;
5641
5642 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5643 if (has_reduced_clock)
5644 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5645 reduced_clock.m2;
5646
9a7c7890
DV		 5647 dpll = ironlake_compute_dpll(intel_crtc, &clock, &fp, &reduced_clock,
5648 has_reduced_clock ? &fp2 : NULL);
79e53945 5649
f7cb34d4 5650 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5651 drm_mode_debug_printmodeline(mode);
5652
5dc5298b 5653 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5654 if (intel_crtc->config.has_pch_encoder) {
ee7b9f93 5655 struct intel_pch_pll *pll;
4b645f14 5656
ee7b9f93
JB		 5657 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5658 if (pll == NULL) {
5659 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5660 pipe);
4b645f14
JB		 5661 return -EINVAL;
5662 }
ee7b9f93
JB		 5663 } else
5664 intel_put_pch_pll(intel_crtc);
79e53945 5665
03afc4a2
DV		 5666 if (intel_crtc->config.has_dp_encoder)
5667 intel_dp_set_m_n(intel_crtc);
79e53945 5668
dafd226c
DV		 5669 for_each_encoder_on_crtc(dev, crtc, encoder)
5670 if (encoder->pre_pll_enable)
5671 encoder->pre_pll_enable(encoder);
79e53945 5672
ee7b9f93
JB		 5673 if (intel_crtc->pch_pll) {
5674 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5675
32f9d658 5676 /* Wait for the clocks to stabilize. */
ee7b9f93 5677 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5678 udelay(150);
5679
8febb297
EA		 5680 /* The pixel multiplier can only be updated once the
5681 * DPLL is enabled and the clocks are stable.
5682 *
5683 * So write it again.
5684 */
ee7b9f93 5685 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5686 }
79e53945 5687
5eddb70b 5688 intel_crtc->lowfreq_avail = false;
ee7b9f93 5689 if (intel_crtc->pch_pll) {
4b645f14 5690 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5691 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5692 intel_crtc->lowfreq_avail = true;
4b645f14 5693 } else {
ee7b9f93 5694 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5695 }
5696 }
5697
b0e77b9c 5698 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b 5699
01a415fd
DV		 5700 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5701 * ironlake_check_fdi_lanes. */
6cf86a5e
DV		 5702 intel_crtc->fdi_lanes = 0;
5703 if (intel_crtc->config.has_pch_encoder)
5704 ironlake_fdi_set_m_n(crtc);
2c07245f 5705
01a415fd 5706 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
2c07245f 5707
c8203565 5708 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
79e53945 5709
a1f9e77e
PZ		 5710 /* Set up the display plane register */
5711 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5712 POSTING_READ(DSPCNTR(plane));
79e53945 5713
94352cf9 5714 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5715
5716 intel_update_watermarks(dev);
5717
1f8eeabf
ED		 5718 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5719
01a415fd 5720 return fdi_config_ok ? ret : -EINVAL;
79e53945
JB		 5721}
5722
0e8ffe1b
DV		 5723static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5724 struct intel_crtc_config *pipe_config)
5725{
5726 struct drm_device *dev = crtc->base.dev;
5727 struct drm_i915_private *dev_priv = dev->dev_private;
5728 uint32_t tmp;
5729
5730 tmp = I915_READ(PIPECONF(crtc->pipe));
5731 if (!(tmp & PIPECONF_ENABLE))
5732 return false;
5733
88adfff1
DV		 5734 if (I915_READ(TRANSCONF(crtc->pipe)) & TRANS_ENABLE)
5735 pipe_config->has_pch_encoder = true;
5736
0e8ffe1b
DV		 5737 return true;
5738}
5739
d6dd9eb1
DV		 5740static void haswell_modeset_global_resources(struct drm_device *dev)
5741{
5742 struct drm_i915_private *dev_priv = dev->dev_private;
5743 bool enable = false;
5744 struct intel_crtc *crtc;
5745 struct intel_encoder *encoder;
5746
5747 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5748 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5749 enable = true;
5750 /* XXX: Should check for edp transcoder here, but thanks to init
5751 * sequence that's not yet available. Just in case desktop eDP
5752 * on PORT D is possible on haswell, too. */
5753 }
5754
5755 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5756 base.head) {
5757 if (encoder->type != INTEL_OUTPUT_EDP &&
5758 encoder->connectors_active)
5759 enable = true;
5760 }
5761
5762 /* Even the eDP panel fitter is outside the always-on well. */
5763 if (dev_priv->pch_pf_size)
5764 enable = true;
5765
5766 intel_set_power_well(dev, enable);
5767}
5768
09b4ddf9 5769static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 5770 int x, int y,
5771 struct drm_framebuffer *fb)
5772{
5773 struct drm_device *dev = crtc->dev;
5774 struct drm_i915_private *dev_priv = dev->dev_private;
5775 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5776 struct drm_display_mode *adjusted_mode =
5777 &intel_crtc->config.adjusted_mode;
5778 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
09b4ddf9
PZ		 5779 int pipe = intel_crtc->pipe;
5780 int plane = intel_crtc->plane;
5781 int num_connectors = 0;
8b47047b 5782 bool is_cpu_edp = false;
09b4ddf9 5783 struct intel_encoder *encoder;
09b4ddf9
PZ		 5784 int ret;
5785 bool dither;
5786
5787 for_each_encoder_on_crtc(dev, crtc, encoder) {
5788 switch (encoder->type) {
09b4ddf9 5789 case INTEL_OUTPUT_EDP:
09b4ddf9
PZ		 5790 if (!intel_encoder_is_pch_edp(&encoder->base))
5791 is_cpu_edp = true;
5792 break;
5793 }
5794
5795 num_connectors++;
5796 }
5797
bba2181c 5798 if (is_cpu_edp)
3b117c8f 5799 intel_crtc->config.cpu_transcoder = TRANSCODER_EDP;
bba2181c 5800 else
3b117c8f 5801 intel_crtc->config.cpu_transcoder = pipe;
bba2181c 5802
5dc5298b
PZ		 5803 /* We are not sure yet this won't happen. */
5804 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5805 INTEL_PCH_TYPE(dev));
5806
5807 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5808 num_connectors, pipe_name(pipe));
5809
3b117c8f 5810 WARN_ON(I915_READ(PIPECONF(intel_crtc->config.cpu_transcoder)) &
1ce42920
PZ		 5811 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5812
5813 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5814
6441ab5f
PZ		 5815 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5816 return -EINVAL;
5817
09b4ddf9
PZ		 5818 /* Ensure that the cursor is valid for the new mode before changing... */
5819 intel_crtc_update_cursor(crtc, true);
5820
5821 /* determine panel color depth */
4e53c2e0 5822 dither = intel_crtc->config.dither;
09b4ddf9 5823
09b4ddf9
PZ		 5824 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5825 drm_mode_debug_printmodeline(mode);
5826
03afc4a2
DV		 5827 if (intel_crtc->config.has_dp_encoder)
5828 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 5829
5830 intel_crtc->lowfreq_avail = false;
09b4ddf9
PZ		 5831
5832 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5833
6cf86a5e
DV		 5834 if (intel_crtc->config.has_pch_encoder)
5835 ironlake_fdi_set_m_n(crtc);
09b4ddf9 5836
ee2b0b38 5837 haswell_set_pipeconf(crtc, adjusted_mode, dither);
09b4ddf9 5838
50f3b016 5839 intel_set_pipe_csc(crtc);
86d3efce 5840
09b4ddf9 5841 /* Set up the display plane register */
86d3efce 5842 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5843 POSTING_READ(DSPCNTR(plane));
5844
5845 ret = intel_pipe_set_base(crtc, x, y, fb);
5846
5847 intel_update_watermarks(dev);
5848
5849 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5850
1f803ee5 5851 return ret;
79e53945
JB		 5852}
5853
0e8ffe1b
DV		 5854static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5855 struct intel_crtc_config *pipe_config)
5856{
5857 struct drm_device *dev = crtc->base.dev;
5858 struct drm_i915_private *dev_priv = dev->dev_private;
5859 uint32_t tmp;
5860
3b117c8f 5861 tmp = I915_READ(PIPECONF(crtc->config.cpu_transcoder));
0e8ffe1b
DV		 5862 if (!(tmp & PIPECONF_ENABLE))
5863 return false;
5864
88adfff1
DV		 5865 /*
5866 * aswell has only FDI/PCH transcoder A. It is which is connected to
5867 * DDI E. So just check whether this pipe is wired to DDI E and whether
5868 * the PCH transcoder is on.
5869 */
5870 tmp = I915_READ(TRANS_DDI_FUNC_CTL(crtc->pipe));
5871 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
5872 I915_READ(TRANSCONF(PIPE_A)) & TRANS_ENABLE)
5873 pipe_config->has_pch_encoder = true;
5874
5875
0e8ffe1b
DV		 5876 return true;
5877}
5878
f564048e 5879static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 5880 int x, int y,
94352cf9 5881 struct drm_framebuffer *fb)
f564048e
EA		 5882{
5883 struct drm_device *dev = crtc->dev;
5884 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 5885 struct drm_encoder_helper_funcs *encoder_funcs;
5886 struct intel_encoder *encoder;
0b701d27 5887 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5888 struct drm_display_mode *adjusted_mode =
5889 &intel_crtc->config.adjusted_mode;
5890 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 5891 int pipe = intel_crtc->pipe;
f564048e
EA		 5892 int ret;
5893
0b701d27 5894 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5895
b8cecdf5
DV		 5896 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
5897
79e53945 5898 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5899
9256aa19
DV		 5900 if (ret != 0)
5901 return ret;
5902
5903 for_each_encoder_on_crtc(dev, crtc, encoder) {
5904 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5905 encoder->base.base.id,
5906 drm_get_encoder_name(&encoder->base),
5907 mode->base.id, mode->name);
6cc5f341
DV		 5908 if (encoder->mode_set) {
5909 encoder->mode_set(encoder);
5910 } else {
5911 encoder_funcs = encoder->base.helper_private;
5912 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5913 }
9256aa19
DV		 5914 }
5915
5916 return 0;
79e53945
JB		 5917}
5918
3a9627f4
WF		 5919static bool intel_eld_uptodate(struct drm_connector *connector,
5920 int reg_eldv, uint32_t bits_eldv,
5921 int reg_elda, uint32_t bits_elda,
5922 int reg_edid)
5923{
5924 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5925 uint8_t *eld = connector->eld;
5926 uint32_t i;
5927
5928 i = I915_READ(reg_eldv);
5929 i &= bits_eldv;
5930
5931 if (!eld[0])
5932 return !i;
5933
5934 if (!i)
5935 return false;
5936
5937 i = I915_READ(reg_elda);
5938 i &= ~bits_elda;
5939 I915_WRITE(reg_elda, i);
5940
5941 for (i = 0; i < eld[2]; i++)
5942 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5943 return false;
5944
5945 return true;
5946}
5947
e0dac65e
WF		 5948static void g4x_write_eld(struct drm_connector *connector,
5949 struct drm_crtc *crtc)
5950{
5951 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5952 uint8_t *eld = connector->eld;
5953 uint32_t eldv;
5954 uint32_t len;
5955 uint32_t i;
5956
5957 i = I915_READ(G4X_AUD_VID_DID);
5958
5959 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5960 eldv = G4X_ELDV_DEVCL_DEVBLC;
5961 else
5962 eldv = G4X_ELDV_DEVCTG;
5963
3a9627f4
WF		 5964 if (intel_eld_uptodate(connector,
5965 G4X_AUD_CNTL_ST, eldv,
5966 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5967 G4X_HDMIW_HDMIEDID))
5968 return;
5969
e0dac65e
WF		 5970 i = I915_READ(G4X_AUD_CNTL_ST);
5971 i &= ~(eldv | G4X_ELD_ADDR);
5972 len = (i >> 9) & 0x1f; /* ELD buffer size */
5973 I915_WRITE(G4X_AUD_CNTL_ST, i);
5974
5975 if (!eld[0])
5976 return;
5977
5978 len = min_t(uint8_t, eld[2], len);
5979 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5980 for (i = 0; i < len; i++)
5981 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5982
5983 i = I915_READ(G4X_AUD_CNTL_ST);
5984 i |= eldv;
5985 I915_WRITE(G4X_AUD_CNTL_ST, i);
5986}
5987
83358c85
WX		 5988static void haswell_write_eld(struct drm_connector *connector,
5989 struct drm_crtc *crtc)
5990{
5991 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5992 uint8_t *eld = connector->eld;
5993 struct drm_device *dev = crtc->dev;
7b9f35a6 5994 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 5995 uint32_t eldv;
5996 uint32_t i;
5997 int len;
5998 int pipe = to_intel_crtc(crtc)->pipe;
5999 int tmp;
6000
6001 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6002 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6003 int aud_config = HSW_AUD_CFG(pipe);
6004 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6005
6006
6007 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6008
6009 /* Audio output enable */
6010 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6011 tmp = I915_READ(aud_cntrl_st2);
6012 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6013 I915_WRITE(aud_cntrl_st2, tmp);
6014
6015 /* Wait for 1 vertical blank */
6016 intel_wait_for_vblank(dev, pipe);
6017
6018 /* Set ELD valid state */
6019 tmp = I915_READ(aud_cntrl_st2);
6020 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6021 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6022 I915_WRITE(aud_cntrl_st2, tmp);
6023 tmp = I915_READ(aud_cntrl_st2);
6024 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6025
6026 /* Enable HDMI mode */
6027 tmp = I915_READ(aud_config);
6028 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6029 /* clear N_programing_enable and N_value_index */
6030 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6031 I915_WRITE(aud_config, tmp);
6032
6033 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6034
6035 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6036 intel_crtc->eld_vld = true;
83358c85
WX		 6037
6038 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6039 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6040 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6041 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6042 } else
6043 I915_WRITE(aud_config, 0);
6044
6045 if (intel_eld_uptodate(connector,
6046 aud_cntrl_st2, eldv,
6047 aud_cntl_st, IBX_ELD_ADDRESS,
6048 hdmiw_hdmiedid))
6049 return;
6050
6051 i = I915_READ(aud_cntrl_st2);
6052 i &= ~eldv;
6053 I915_WRITE(aud_cntrl_st2, i);
6054
6055 if (!eld[0])
6056 return;
6057
6058 i = I915_READ(aud_cntl_st);
6059 i &= ~IBX_ELD_ADDRESS;
6060 I915_WRITE(aud_cntl_st, i);
6061 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6062 DRM_DEBUG_DRIVER("port num:%d\n", i);
6063
6064 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6065 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6066 for (i = 0; i < len; i++)
6067 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6068
6069 i = I915_READ(aud_cntrl_st2);
6070 i |= eldv;
6071 I915_WRITE(aud_cntrl_st2, i);
6072
6073}
6074
e0dac65e
WF		 6075static void ironlake_write_eld(struct drm_connector *connector,
6076 struct drm_crtc *crtc)
6077{
6078 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6079 uint8_t *eld = connector->eld;
6080 uint32_t eldv;
6081 uint32_t i;
6082 int len;
6083 int hdmiw_hdmiedid;
b6daa025 6084 int aud_config;
e0dac65e
WF		 6085 int aud_cntl_st;
6086 int aud_cntrl_st2;
9b138a83 6087 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6088
b3f33cbf 6089 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6090 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6091 aud_config = IBX_AUD_CFG(pipe);
6092 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6093 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6094 } else {
9b138a83
WX		 6095 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6096 aud_config = CPT_AUD_CFG(pipe);
6097 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6098 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6099 }
6100
9b138a83 6101 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6102
6103 i = I915_READ(aud_cntl_st);
9b138a83 6104 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6105 if (!i) {
6106 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6107 /* operate blindly on all ports */
1202b4c6
WF		 6108 eldv = IBX_ELD_VALIDB;
6109 eldv |= IBX_ELD_VALIDB << 4;
6110 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 6111 } else {
6112 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 6113 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6114 }
6115
3a9627f4
WF		 6116 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6117 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6118 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6119 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6120 } else
6121 I915_WRITE(aud_config, 0);
e0dac65e 6122
3a9627f4
WF		 6123 if (intel_eld_uptodate(connector,
6124 aud_cntrl_st2, eldv,
6125 aud_cntl_st, IBX_ELD_ADDRESS,
6126 hdmiw_hdmiedid))
6127 return;
6128
e0dac65e
WF		 6129 i = I915_READ(aud_cntrl_st2);
6130 i &= ~eldv;
6131 I915_WRITE(aud_cntrl_st2, i);
6132
6133 if (!eld[0])
6134 return;
6135
e0dac65e 6136 i = I915_READ(aud_cntl_st);
1202b4c6 6137 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6138 I915_WRITE(aud_cntl_st, i);
6139
6140 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6141 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6142 for (i = 0; i < len; i++)
6143 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6144
6145 i = I915_READ(aud_cntrl_st2);
6146 i |= eldv;
6147 I915_WRITE(aud_cntrl_st2, i);
6148}
6149
6150void intel_write_eld(struct drm_encoder *encoder,
6151 struct drm_display_mode *mode)
6152{
6153 struct drm_crtc *crtc = encoder->crtc;
6154 struct drm_connector *connector;
6155 struct drm_device *dev = encoder->dev;
6156 struct drm_i915_private *dev_priv = dev->dev_private;
6157
6158 connector = drm_select_eld(encoder, mode);
6159 if (!connector)
6160 return;
6161
6162 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6163 connector->base.id,
6164 drm_get_connector_name(connector),
6165 connector->encoder->base.id,
6166 drm_get_encoder_name(connector->encoder));
6167
6168 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6169
6170 if (dev_priv->display.write_eld)
6171 dev_priv->display.write_eld(connector, crtc);
6172}
6173
79e53945
JB		 6174/** Loads the palette/gamma unit for the CRTC with the prepared values */
6175void intel_crtc_load_lut(struct drm_crtc *crtc)
6176{
6177 struct drm_device *dev = crtc->dev;
6178 struct drm_i915_private *dev_priv = dev->dev_private;
6179 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6180 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6181 int i;
6182
6183 /* The clocks have to be on to load the palette. */
aed3f09d 6184 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6185 return;
6186
f2b115e6 6187 /* use legacy palette for Ironlake */
bad720ff 6188 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6189 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6190
79e53945
JB		 6191 for (i = 0; i < 256; i++) {
6192 I915_WRITE(palreg + 4 * i,
6193 (intel_crtc->lut_r[i] << 16) |
6194 (intel_crtc->lut_g[i] << 8) |
6195 intel_crtc->lut_b[i]);
6196 }
6197}
6198
560b85bb
CW		 6199static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6200{
6201 struct drm_device *dev = crtc->dev;
6202 struct drm_i915_private *dev_priv = dev->dev_private;
6203 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6204 bool visible = base != 0;
6205 u32 cntl;
6206
6207 if (intel_crtc->cursor_visible == visible)
6208 return;
6209
9db4a9c7 6210 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6211 if (visible) {
6212 /* On these chipsets we can only modify the base whilst
6213 * the cursor is disabled.
6214 */
9db4a9c7 6215 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6216
6217 cntl &= ~(CURSOR_FORMAT_MASK);
6218 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6219 cntl |= CURSOR_ENABLE |
6220 CURSOR_GAMMA_ENABLE |
6221 CURSOR_FORMAT_ARGB;
6222 } else
6223 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6224 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6225
6226 intel_crtc->cursor_visible = visible;
6227}
6228
6229static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6230{
6231 struct drm_device *dev = crtc->dev;
6232 struct drm_i915_private *dev_priv = dev->dev_private;
6233 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6234 int pipe = intel_crtc->pipe;
6235 bool visible = base != 0;
6236
6237 if (intel_crtc->cursor_visible != visible) {
548f245b 6238 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6239 if (base) {
6240 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6241 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6242 cntl |= pipe << 28; /* Connect to correct pipe */
6243 } else {
6244 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6245 cntl |= CURSOR_MODE_DISABLE;
6246 }
9db4a9c7 6247 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6248
6249 intel_crtc->cursor_visible = visible;
6250 }
6251 /* and commit changes on next vblank */
9db4a9c7 6252 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6253}
6254
65a21cd6
JB		 6255static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6256{
6257 struct drm_device *dev = crtc->dev;
6258 struct drm_i915_private *dev_priv = dev->dev_private;
6259 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6260 int pipe = intel_crtc->pipe;
6261 bool visible = base != 0;
6262
6263 if (intel_crtc->cursor_visible != visible) {
6264 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6265 if (base) {
6266 cntl &= ~CURSOR_MODE;
6267 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6268 } else {
6269 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6270 cntl |= CURSOR_MODE_DISABLE;
6271 }
86d3efce
VS		 6272 if (IS_HASWELL(dev))
6273 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6274 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6275
6276 intel_crtc->cursor_visible = visible;
6277 }
6278 /* and commit changes on next vblank */
6279 I915_WRITE(CURBASE_IVB(pipe), base);
6280}
6281
cda4b7d3 6282/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6283static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6284 bool on)
cda4b7d3
CW		 6285{
6286 struct drm_device *dev = crtc->dev;
6287 struct drm_i915_private *dev_priv = dev->dev_private;
6288 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6289 int pipe = intel_crtc->pipe;
6290 int x = intel_crtc->cursor_x;
6291 int y = intel_crtc->cursor_y;
560b85bb 6292 u32 base, pos;
cda4b7d3
CW		 6293 bool visible;
6294
6295 pos = 0;
6296
6b383a7f 6297 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6298 base = intel_crtc->cursor_addr;
6299 if (x > (int) crtc->fb->width)
6300 base = 0;
6301
6302 if (y > (int) crtc->fb->height)
6303 base = 0;
6304 } else
6305 base = 0;
6306
6307 if (x < 0) {
6308 if (x + intel_crtc->cursor_width < 0)
6309 base = 0;
6310
6311 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6312 x = -x;
6313 }
6314 pos |= x << CURSOR_X_SHIFT;
6315
6316 if (y < 0) {
6317 if (y + intel_crtc->cursor_height < 0)
6318 base = 0;
6319
6320 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6321 y = -y;
6322 }
6323 pos |= y << CURSOR_Y_SHIFT;
6324
6325 visible = base != 0;
560b85bb 6326 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6327 return;
6328
0cd83aa9 6329 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6330 I915_WRITE(CURPOS_IVB(pipe), pos);
6331 ivb_update_cursor(crtc, base);
6332 } else {
6333 I915_WRITE(CURPOS(pipe), pos);
6334 if (IS_845G(dev) || IS_I865G(dev))
6335 i845_update_cursor(crtc, base);
6336 else
6337 i9xx_update_cursor(crtc, base);
6338 }
cda4b7d3
CW		 6339}
6340
79e53945 6341static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6342 struct drm_file *file,
79e53945
JB		 6343 uint32_t handle,
6344 uint32_t width, uint32_t height)
6345{
6346 struct drm_device *dev = crtc->dev;
6347 struct drm_i915_private *dev_priv = dev->dev_private;
6348 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6349 struct drm_i915_gem_object *obj;
cda4b7d3 6350 uint32_t addr;
3f8bc370 6351 int ret;
79e53945 6352
79e53945
JB		 6353 /* if we want to turn off the cursor ignore width and height */
6354 if (!handle) {
28c97730 6355 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6356 addr = 0;
05394f39 6357 obj = NULL;
5004417d 6358 mutex_lock(&dev->struct_mutex);
3f8bc370 6359 goto finish;
79e53945
JB		 6360 }
6361
6362 /* Currently we only support 64x64 cursors */
6363 if (width != 64 || height != 64) {
6364 DRM_ERROR("we currently only support 64x64 cursors\n");
6365 return -EINVAL;
6366 }
6367
05394f39 6368 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6369 if (&obj->base == NULL)
79e53945
JB		 6370 return -ENOENT;
6371
05394f39 6372 if (obj->base.size < width * height * 4) {
79e53945 6373 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6374 ret = -ENOMEM;
6375 goto fail;
79e53945
JB		 6376 }
6377
71acb5eb 6378 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6379 mutex_lock(&dev->struct_mutex);
b295d1b6 6380 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6381 unsigned alignment;
6382
d9e86c0e
CW		 6383 if (obj->tiling_mode) {
6384 DRM_ERROR("cursor cannot be tiled\n");
6385 ret = -EINVAL;
6386 goto fail_locked;
6387 }
6388
693db184
CW		 6389 /* Note that the w/a also requires 2 PTE of padding following
6390 * the bo. We currently fill all unused PTE with the shadow
6391 * page and so we should always have valid PTE following the
6392 * cursor preventing the VT-d warning.
6393 */
6394 alignment = 0;
6395 if (need_vtd_wa(dev))
6396 alignment = 64*1024;
6397
6398 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6399 if (ret) {
6400 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6401 goto fail_locked;
e7b526bb
CW		 6402 }
6403
d9e86c0e
CW		 6404 ret = i915_gem_object_put_fence(obj);
6405 if (ret) {
2da3b9b9 6406 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6407 goto fail_unpin;
6408 }
6409
05394f39 6410 addr = obj->gtt_offset;
71acb5eb 6411 } else {
6eeefaf3 6412 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6413 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6414 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6415 align);
71acb5eb
DA		 6416 if (ret) {
6417 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6418 goto fail_locked;
71acb5eb 6419 }
05394f39 6420 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6421 }
6422
a6c45cf0 6423 if (IS_GEN2(dev))
14b60391
JB		 6424 I915_WRITE(CURSIZE, (height << 12) | width);
6425
3f8bc370 6426 finish:
3f8bc370 6427 if (intel_crtc->cursor_bo) {
b295d1b6 6428 if (dev_priv->info->cursor_needs_physical) {
05394f39 6429 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6430 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6431 } else
6432 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6433 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6434 }
80824003 6435
7f9872e0 6436 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6437
6438 intel_crtc->cursor_addr = addr;
05394f39 6439 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6440 intel_crtc->cursor_width = width;
6441 intel_crtc->cursor_height = height;
6442
6b383a7f 6443 intel_crtc_update_cursor(crtc, true);
3f8bc370 6444
79e53945 6445 return 0;
e7b526bb 6446fail_unpin:
05394f39 6447 i915_gem_object_unpin(obj);
7f9872e0 6448fail_locked:
34b8686e 6449 mutex_unlock(&dev->struct_mutex);
bc9025bd 6450fail:
05394f39 6451 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6452 return ret;
79e53945
JB		 6453}
6454
6455static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6456{
79e53945 6457 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6458
cda4b7d3
CW		 6459 intel_crtc->cursor_x = x;
6460 intel_crtc->cursor_y = y;
652c393a 6461
6b383a7f 6462 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6463
6464 return 0;
6465}
6466
6467/** Sets the color ramps on behalf of RandR */
6468void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6469 u16 blue, int regno)
6470{
6471 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6472
6473 intel_crtc->lut_r[regno] = red >> 8;
6474 intel_crtc->lut_g[regno] = green >> 8;
6475 intel_crtc->lut_b[regno] = blue >> 8;
6476}
6477
b8c00ac5
DA		 6478void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6479 u16 *blue, int regno)
6480{
6481 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6482
6483 *red = intel_crtc->lut_r[regno] << 8;
6484 *green = intel_crtc->lut_g[regno] << 8;
6485 *blue = intel_crtc->lut_b[regno] << 8;
6486}
6487
79e53945 6488static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6489 u16 *blue, uint32_t start, uint32_t size)
79e53945 6490{
7203425a 6491 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6492 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6493
7203425a 6494 for (i = start; i < end; i++) {
79e53945
JB		 6495 intel_crtc->lut_r[i] = red[i] >> 8;
6496 intel_crtc->lut_g[i] = green[i] >> 8;
6497 intel_crtc->lut_b[i] = blue[i] >> 8;
6498 }
6499
6500 intel_crtc_load_lut(crtc);
6501}
6502
79e53945
JB		 6503/* VESA 640x480x72Hz mode to set on the pipe */
6504static struct drm_display_mode load_detect_mode = {
6505 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6506 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6507};
6508
d2dff872
CW		 6509static struct drm_framebuffer *
6510intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6511 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6512 struct drm_i915_gem_object *obj)
6513{
6514 struct intel_framebuffer *intel_fb;
6515 int ret;
6516
6517 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6518 if (!intel_fb) {
6519 drm_gem_object_unreference_unlocked(&obj->base);
6520 return ERR_PTR(-ENOMEM);
6521 }
6522
6523 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6524 if (ret) {
6525 drm_gem_object_unreference_unlocked(&obj->base);
6526 kfree(intel_fb);
6527 return ERR_PTR(ret);
6528 }
6529
6530 return &intel_fb->base;
6531}
6532
6533static u32
6534intel_framebuffer_pitch_for_width(int width, int bpp)
6535{
6536 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6537 return ALIGN(pitch, 64);
6538}
6539
6540static u32
6541intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6542{
6543 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6544 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6545}
6546
6547static struct drm_framebuffer *
6548intel_framebuffer_create_for_mode(struct drm_device *dev,
6549 struct drm_display_mode *mode,
6550 int depth, int bpp)
6551{
6552 struct drm_i915_gem_object *obj;
0fed39bd 6553 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6554
6555 obj = i915_gem_alloc_object(dev,
6556 intel_framebuffer_size_for_mode(mode, bpp));
6557 if (obj == NULL)
6558 return ERR_PTR(-ENOMEM);
6559
6560 mode_cmd.width = mode->hdisplay;
6561 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6562 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6563 bpp);
5ca0c34a 6564 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6565
6566 return intel_framebuffer_create(dev, &mode_cmd, obj);
6567}
6568
6569static struct drm_framebuffer *
6570mode_fits_in_fbdev(struct drm_device *dev,
6571 struct drm_display_mode *mode)
6572{
6573 struct drm_i915_private *dev_priv = dev->dev_private;
6574 struct drm_i915_gem_object *obj;
6575 struct drm_framebuffer *fb;
6576
6577 if (dev_priv->fbdev == NULL)
6578 return NULL;
6579
6580 obj = dev_priv->fbdev->ifb.obj;
6581 if (obj == NULL)
6582 return NULL;
6583
6584 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6585 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6586 fb->bits_per_pixel))
d2dff872
CW		 6587 return NULL;
6588
01f2c773 6589 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6590 return NULL;
6591
6592 return fb;
6593}
6594
d2434ab7 6595bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6596 struct drm_display_mode *mode,
8261b191 6597 struct intel_load_detect_pipe *old)
79e53945
JB		 6598{
6599 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6600 struct intel_encoder *intel_encoder =
6601 intel_attached_encoder(connector);
79e53945 6602 struct drm_crtc *possible_crtc;
4ef69c7a 6603 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6604 struct drm_crtc *crtc = NULL;
6605 struct drm_device *dev = encoder->dev;
94352cf9 6606 struct drm_framebuffer *fb;
79e53945
JB		 6607 int i = -1;
6608
d2dff872
CW		 6609 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6610 connector->base.id, drm_get_connector_name(connector),
6611 encoder->base.id, drm_get_encoder_name(encoder));
6612
79e53945
JB		 6613 /*
6614 * Algorithm gets a little messy:
7a5e4805 6615 *
79e53945
JB		 6616 * - if the connector already has an assigned crtc, use it (but make
6617 * sure it's on first)
7a5e4805 6618 *
79e53945
JB		 6619 * - try to find the first unused crtc that can drive this connector,
6620 * and use that if we find one
79e53945
JB		 6621 */
6622
6623 /* See if we already have a CRTC for this connector */
6624 if (encoder->crtc) {
6625 crtc = encoder->crtc;
8261b191 6626
7b24056b
DV		 6627 mutex_lock(&crtc->mutex);
6628
24218aac 6629 old->dpms_mode = connector->dpms;
8261b191
CW		 6630 old->load_detect_temp = false;
6631
6632 /* Make sure the crtc and connector are running */
24218aac
DV		 6633 if (connector->dpms != DRM_MODE_DPMS_ON)
6634 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6635
7173188d 6636 return true;
79e53945
JB		 6637 }
6638
6639 /* Find an unused one (if possible) */
6640 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6641 i++;
6642 if (!(encoder->possible_crtcs & (1 << i)))
6643 continue;
6644 if (!possible_crtc->enabled) {
6645 crtc = possible_crtc;
6646 break;
6647 }
79e53945
JB		 6648 }
6649
6650 /*
6651 * If we didn't find an unused CRTC, don't use any.
6652 */
6653 if (!crtc) {
7173188d
CW		 6654 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6655 return false;
79e53945
JB		 6656 }
6657
7b24056b 6658 mutex_lock(&crtc->mutex);
fc303101
DV		 6659 intel_encoder->new_crtc = to_intel_crtc(crtc);
6660 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6661
6662 intel_crtc = to_intel_crtc(crtc);
24218aac 6663 old->dpms_mode = connector->dpms;
8261b191 6664 old->load_detect_temp = true;
d2dff872 6665 old->release_fb = NULL;
79e53945 6666
6492711d
CW		 6667 if (!mode)
6668 mode = &load_detect_mode;
79e53945 6669
d2dff872
CW		 6670 /* We need a framebuffer large enough to accommodate all accesses
6671 * that the plane may generate whilst we perform load detection.
6672 * We can not rely on the fbcon either being present (we get called
6673 * during its initialisation to detect all boot displays, or it may
6674 * not even exist) or that it is large enough to satisfy the
6675 * requested mode.
6676 */
94352cf9
DV		 6677 fb = mode_fits_in_fbdev(dev, mode);
6678 if (fb == NULL) {
d2dff872 6679 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6680 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6681 old->release_fb = fb;
d2dff872
CW		 6682 } else
6683 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6684 if (IS_ERR(fb)) {
d2dff872 6685 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6686 mutex_unlock(&crtc->mutex);
0e8b3d3e 6687 return false;
79e53945 6688 }
79e53945 6689
c0c36b94 6690 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6691 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6692 if (old->release_fb)
6693 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6694 mutex_unlock(&crtc->mutex);
0e8b3d3e 6695 return false;
79e53945 6696 }
7173188d 6697
79e53945 6698 /* let the connector get through one full cycle before testing */
9d0498a2 6699 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6700 return true;
79e53945
JB		 6701}
6702
d2434ab7 6703void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6704 struct intel_load_detect_pipe *old)
79e53945 6705{
d2434ab7
DV		 6706 struct intel_encoder *intel_encoder =
6707 intel_attached_encoder(connector);
4ef69c7a 6708 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6709 struct drm_crtc *crtc = encoder->crtc;
79e53945 6710
d2dff872
CW		 6711 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6712 connector->base.id, drm_get_connector_name(connector),
6713 encoder->base.id, drm_get_encoder_name(encoder));
6714
8261b191 6715 if (old->load_detect_temp) {
fc303101
DV		 6716 to_intel_connector(connector)->new_encoder = NULL;
6717 intel_encoder->new_crtc = NULL;
6718 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6719
36206361
DV		 6720 if (old->release_fb) {
6721 drm_framebuffer_unregister_private(old->release_fb);
6722 drm_framebuffer_unreference(old->release_fb);
6723 }
d2dff872 6724
67c96400 6725 mutex_unlock(&crtc->mutex);
0622a53c 6726 return;
79e53945
JB		 6727 }
6728
c751ce4f 6729 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6730 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6731 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6732
6733 mutex_unlock(&crtc->mutex);
79e53945
JB		 6734}
6735
6736/* Returns the clock of the currently programmed mode of the given pipe. */
6737static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6738{
6739 struct drm_i915_private *dev_priv = dev->dev_private;
6740 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6741 int pipe = intel_crtc->pipe;
548f245b 6742 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6743 u32 fp;
6744 intel_clock_t clock;
6745
6746 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6747 fp = I915_READ(FP0(pipe));
79e53945 6748 else
39adb7a5 6749 fp = I915_READ(FP1(pipe));
79e53945
JB		 6750
6751 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6752 if (IS_PINEVIEW(dev)) {
6753 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6754 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6755 } else {
6756 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6757 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6758 }
6759
a6c45cf0 6760 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6761 if (IS_PINEVIEW(dev))
6762 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6763 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6764 else
6765 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6766 DPLL_FPA01_P1_POST_DIV_SHIFT);
6767
6768 switch (dpll & DPLL_MODE_MASK) {
6769 case DPLLB_MODE_DAC_SERIAL:
6770 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6771 5 : 10;
6772 break;
6773 case DPLLB_MODE_LVDS:
6774 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6775 7 : 14;
6776 break;
6777 default:
28c97730 6778 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6779 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6780 return 0;
6781 }
6782
6783 /* XXX: Handle the 100Mhz refclk */
2177832f 6784 intel_clock(dev, 96000, &clock);
79e53945
JB		 6785 } else {
6786 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6787
6788 if (is_lvds) {
6789 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6790 DPLL_FPA01_P1_POST_DIV_SHIFT);
6791 clock.p2 = 14;
6792
6793 if ((dpll & PLL_REF_INPUT_MASK) ==
6794 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6795 /* XXX: might not be 66MHz */
2177832f 6796 intel_clock(dev, 66000, &clock);
79e53945 6797 } else
2177832f 6798 intel_clock(dev, 48000, &clock);
79e53945
JB		 6799 } else {
6800 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6801 clock.p1 = 2;
6802 else {
6803 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6804 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6805 }
6806 if (dpll & PLL_P2_DIVIDE_BY_4)
6807 clock.p2 = 4;
6808 else
6809 clock.p2 = 2;
6810
2177832f 6811 intel_clock(dev, 48000, &clock);
79e53945
JB		 6812 }
6813 }
6814
6815 /* XXX: It would be nice to validate the clocks, but we can't reuse
6816 * i830PllIsValid() because it relies on the xf86_config connector
6817 * configuration being accurate, which it isn't necessarily.
6818 */
6819
6820 return clock.dot;
6821}
6822
6823/** Returns the currently programmed mode of the given pipe. */
6824struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6825 struct drm_crtc *crtc)
6826{
548f245b 6827 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6828 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 6829 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 6830 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6831 int htot = I915_READ(HTOTAL(cpu_transcoder));
6832 int hsync = I915_READ(HSYNC(cpu_transcoder));
6833 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6834 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6835
6836 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6837 if (!mode)
6838 return NULL;
6839
6840 mode->clock = intel_crtc_clock_get(dev, crtc);
6841 mode->hdisplay = (htot & 0xffff) + 1;
6842 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6843 mode->hsync_start = (hsync & 0xffff) + 1;
6844 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6845 mode->vdisplay = (vtot & 0xffff) + 1;
6846 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6847 mode->vsync_start = (vsync & 0xffff) + 1;
6848 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6849
6850 drm_mode_set_name(mode);
79e53945
JB		 6851
6852 return mode;
6853}
6854
3dec0095 6855static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6856{
6857 struct drm_device *dev = crtc->dev;
6858 drm_i915_private_t *dev_priv = dev->dev_private;
6859 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6860 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6861 int dpll_reg = DPLL(pipe);
6862 int dpll;
652c393a 6863
bad720ff 6864 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6865 return;
6866
6867 if (!dev_priv->lvds_downclock_avail)
6868 return;
6869
dbdc6479 6870 dpll = I915_READ(dpll_reg);
652c393a 6871 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6872 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6873
8ac5a6d5 6874 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6875
6876 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6877 I915_WRITE(dpll_reg, dpll);
9d0498a2 6878 intel_wait_for_vblank(dev, pipe);
dbdc6479 6879
652c393a
JB		 6880 dpll = I915_READ(dpll_reg);
6881 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6882 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6883 }
652c393a
JB		 6884}
6885
6886static void intel_decrease_pllclock(struct drm_crtc *crtc)
6887{
6888 struct drm_device *dev = crtc->dev;
6889 drm_i915_private_t *dev_priv = dev->dev_private;
6890 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6891
bad720ff 6892 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6893 return;
6894
6895 if (!dev_priv->lvds_downclock_avail)
6896 return;
6897
6898 /*
6899 * Since this is called by a timer, we should never get here in
6900 * the manual case.
6901 */
6902 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6903 int pipe = intel_crtc->pipe;
6904 int dpll_reg = DPLL(pipe);
6905 int dpll;
f6e5b160 6906
44d98a61 6907 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6908
8ac5a6d5 6909 assert_panel_unlocked(dev_priv, pipe);
652c393a 6910
dc257cf1 6911 dpll = I915_READ(dpll_reg);
652c393a
JB		 6912 dpll |= DISPLAY_RATE_SELECT_FPA1;
6913 I915_WRITE(dpll_reg, dpll);
9d0498a2 6914 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6915 dpll = I915_READ(dpll_reg);
6916 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6917 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6918 }
6919
6920}
6921
f047e395
CW		 6922void intel_mark_busy(struct drm_device *dev)
6923{
f047e395
CW		 6924 i915_update_gfx_val(dev->dev_private);
6925}
6926
6927void intel_mark_idle(struct drm_device *dev)
652c393a 6928{
652c393a 6929 struct drm_crtc *crtc;
652c393a
JB		 6930
6931 if (!i915_powersave)
6932 return;
6933
652c393a 6934 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6935 if (!crtc->fb)
6936 continue;
6937
725a5b54 6938 intel_decrease_pllclock(crtc);
652c393a 6939 }
652c393a
JB		 6940}
6941
725a5b54 6942void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
652c393a 6943{
f047e395
CW		 6944 struct drm_device *dev = obj->base.dev;
6945 struct drm_crtc *crtc;
652c393a 6946
f047e395 6947 if (!i915_powersave)
acb87dfb
CW		 6948 return;
6949
652c393a
JB		 6950 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6951 if (!crtc->fb)
6952 continue;
6953
f047e395 6954 if (to_intel_framebuffer(crtc->fb)->obj == obj)
725a5b54 6955 intel_increase_pllclock(crtc);
652c393a
JB		 6956 }
6957}
6958
79e53945
JB		 6959static void intel_crtc_destroy(struct drm_crtc *crtc)
6960{
6961 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6962 struct drm_device *dev = crtc->dev;
6963 struct intel_unpin_work *work;
6964 unsigned long flags;
6965
6966 spin_lock_irqsave(&dev->event_lock, flags);
6967 work = intel_crtc->unpin_work;
6968 intel_crtc->unpin_work = NULL;
6969 spin_unlock_irqrestore(&dev->event_lock, flags);
6970
6971 if (work) {
6972 cancel_work_sync(&work->work);
6973 kfree(work);
6974 }
79e53945
JB		 6975
6976 drm_crtc_cleanup(crtc);
67e77c5a 6977
79e53945
JB		 6978 kfree(intel_crtc);
6979}
6980
6b95a207
KH		 6981static void intel_unpin_work_fn(struct work_struct *__work)
6982{
6983 struct intel_unpin_work *work =
6984 container_of(__work, struct intel_unpin_work, work);
b4a98e57 6985 struct drm_device *dev = work->crtc->dev;
6b95a207 6986
b4a98e57 6987 mutex_lock(&dev->struct_mutex);
1690e1eb 6988 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 6989 drm_gem_object_unreference(&work->pending_flip_obj->base);
6990 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6991
b4a98e57
CW		 6992 intel_update_fbc(dev);
6993 mutex_unlock(&dev->struct_mutex);
6994
6995 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
6996 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
6997
6b95a207
KH		 6998 kfree(work);
6999}
7000
1afe3e9d 7001static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7002 struct drm_crtc *crtc)
6b95a207
KH		 7003{
7004 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7006 struct intel_unpin_work *work;
6b95a207
KH		 7007 unsigned long flags;
7008
7009 /* Ignore early vblank irqs */
7010 if (intel_crtc == NULL)
7011 return;
7012
7013 spin_lock_irqsave(&dev->event_lock, flags);
7014 work = intel_crtc->unpin_work;
e7d841ca
CW		 7015
7016 /* Ensure we don't miss a work->pending update ... */
7017 smp_rmb();
7018
7019 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7020 spin_unlock_irqrestore(&dev->event_lock, flags);
7021 return;
7022 }
7023
e7d841ca
CW		 7024 /* and that the unpin work is consistent wrt ->pending. */
7025 smp_rmb();
7026
6b95a207 7027 intel_crtc->unpin_work = NULL;
6b95a207 7028
45a066eb
RC		 7029 if (work->event)
7030 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7031
0af7e4df
MK		 7032 drm_vblank_put(dev, intel_crtc->pipe);
7033
6b95a207
KH		 7034 spin_unlock_irqrestore(&dev->event_lock, flags);
7035
2c10d571 7036 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7037
7038 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7039
7040 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7041}
7042
1afe3e9d
JB		 7043void intel_finish_page_flip(struct drm_device *dev, int pipe)
7044{
7045 drm_i915_private_t *dev_priv = dev->dev_private;
7046 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7047
49b14a5c 7048 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7049}
7050
7051void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7052{
7053 drm_i915_private_t *dev_priv = dev->dev_private;
7054 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7055
49b14a5c 7056 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7057}
7058
6b95a207
KH		 7059void intel_prepare_page_flip(struct drm_device *dev, int plane)
7060{
7061 drm_i915_private_t *dev_priv = dev->dev_private;
7062 struct intel_crtc *intel_crtc =
7063 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7064 unsigned long flags;
7065
e7d841ca
CW		 7066 /* NB: An MMIO update of the plane base pointer will also
7067 * generate a page-flip completion irq, i.e. every modeset
7068 * is also accompanied by a spurious intel_prepare_page_flip().
7069 */
6b95a207 7070 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7071 if (intel_crtc->unpin_work)
7072 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7073 spin_unlock_irqrestore(&dev->event_lock, flags);
7074}
7075
e7d841ca
CW		 7076inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7077{
7078 /* Ensure that the work item is consistent when activating it ... */
7079 smp_wmb();
7080 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7081 /* and that it is marked active as soon as the irq could fire. */
7082 smp_wmb();
7083}
7084
8c9f3aaf
JB		 7085static int intel_gen2_queue_flip(struct drm_device *dev,
7086 struct drm_crtc *crtc,
7087 struct drm_framebuffer *fb,
7088 struct drm_i915_gem_object *obj)
7089{
7090 struct drm_i915_private *dev_priv = dev->dev_private;
7091 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7092 u32 flip_mask;
6d90c952 7093 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7094 int ret;
7095
6d90c952 7096 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7097 if (ret)
83d4092b 7098 goto err;
8c9f3aaf 7099
6d90c952 7100 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7101 if (ret)
83d4092b 7102 goto err_unpin;
8c9f3aaf
JB		 7103
7104 /* Can't queue multiple flips, so wait for the previous
7105 * one to finish before executing the next.
7106 */
7107 if (intel_crtc->plane)
7108 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7109 else
7110 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7111 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7112 intel_ring_emit(ring, MI_NOOP);
7113 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7114 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7115 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7116 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 7117 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7118
7119 intel_mark_page_flip_active(intel_crtc);
6d90c952 7120 intel_ring_advance(ring);
83d4092b
CW		 7121 return 0;
7122
7123err_unpin:
7124 intel_unpin_fb_obj(obj);
7125err:
8c9f3aaf
JB		 7126 return ret;
7127}
7128
7129static int intel_gen3_queue_flip(struct drm_device *dev,
7130 struct drm_crtc *crtc,
7131 struct drm_framebuffer *fb,
7132 struct drm_i915_gem_object *obj)
7133{
7134 struct drm_i915_private *dev_priv = dev->dev_private;
7135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7136 u32 flip_mask;
6d90c952 7137 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7138 int ret;
7139
6d90c952 7140 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7141 if (ret)
83d4092b 7142 goto err;
8c9f3aaf 7143
6d90c952 7144 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7145 if (ret)
83d4092b 7146 goto err_unpin;
8c9f3aaf
JB		 7147
7148 if (intel_crtc->plane)
7149 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7150 else
7151 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7152 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7153 intel_ring_emit(ring, MI_NOOP);
7154 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7155 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7156 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7157 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7158 intel_ring_emit(ring, MI_NOOP);
7159
e7d841ca 7160 intel_mark_page_flip_active(intel_crtc);
6d90c952 7161 intel_ring_advance(ring);
83d4092b
CW		 7162 return 0;
7163
7164err_unpin:
7165 intel_unpin_fb_obj(obj);
7166err:
8c9f3aaf
JB		 7167 return ret;
7168}
7169
7170static int intel_gen4_queue_flip(struct drm_device *dev,
7171 struct drm_crtc *crtc,
7172 struct drm_framebuffer *fb,
7173 struct drm_i915_gem_object *obj)
7174{
7175 struct drm_i915_private *dev_priv = dev->dev_private;
7176 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7177 uint32_t pf, pipesrc;
6d90c952 7178 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7179 int ret;
7180
6d90c952 7181 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7182 if (ret)
83d4092b 7183 goto err;
8c9f3aaf 7184
6d90c952 7185 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7186 if (ret)
83d4092b 7187 goto err_unpin;
8c9f3aaf
JB		 7188
7189 /* i965+ uses the linear or tiled offsets from the
7190 * Display Registers (which do not change across a page-flip)
7191 * so we need only reprogram the base address.
7192 */
6d90c952
DV		 7193 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7194 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7195 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7196 intel_ring_emit(ring,
7197 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7198 obj->tiling_mode);
8c9f3aaf
JB		 7199
7200 /* XXX Enabling the panel-fitter across page-flip is so far
7201 * untested on non-native modes, so ignore it for now.
7202 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7203 */
7204 pf = 0;
7205 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7206 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7207
7208 intel_mark_page_flip_active(intel_crtc);
6d90c952 7209 intel_ring_advance(ring);
83d4092b
CW		 7210 return 0;
7211
7212err_unpin:
7213 intel_unpin_fb_obj(obj);
7214err:
8c9f3aaf
JB		 7215 return ret;
7216}
7217
7218static int intel_gen6_queue_flip(struct drm_device *dev,
7219 struct drm_crtc *crtc,
7220 struct drm_framebuffer *fb,
7221 struct drm_i915_gem_object *obj)
7222{
7223 struct drm_i915_private *dev_priv = dev->dev_private;
7224 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7225 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7226 uint32_t pf, pipesrc;
7227 int ret;
7228
6d90c952 7229 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7230 if (ret)
83d4092b 7231 goto err;
8c9f3aaf 7232
6d90c952 7233 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7234 if (ret)
83d4092b 7235 goto err_unpin;
8c9f3aaf 7236
6d90c952
DV		 7237 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7238 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7239 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7240 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7241
dc257cf1
DV		 7242 /* Contrary to the suggestions in the documentation,
7243 * "Enable Panel Fitter" does not seem to be required when page
7244 * flipping with a non-native mode, and worse causes a normal
7245 * modeset to fail.
7246 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7247 */
7248 pf = 0;
8c9f3aaf 7249 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7250 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7251
7252 intel_mark_page_flip_active(intel_crtc);
6d90c952 7253 intel_ring_advance(ring);
83d4092b
CW		 7254 return 0;
7255
7256err_unpin:
7257 intel_unpin_fb_obj(obj);
7258err:
8c9f3aaf
JB		 7259 return ret;
7260}
7261
7c9017e5
JB		 7262/*
7263 * On gen7 we currently use the blit ring because (in early silicon at least)
7264 * the render ring doesn't give us interrpts for page flip completion, which
7265 * means clients will hang after the first flip is queued. Fortunately the
7266 * blit ring generates interrupts properly, so use it instead.
7267 */
7268static int intel_gen7_queue_flip(struct drm_device *dev,
7269 struct drm_crtc *crtc,
7270 struct drm_framebuffer *fb,
7271 struct drm_i915_gem_object *obj)
7272{
7273 struct drm_i915_private *dev_priv = dev->dev_private;
7274 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7275 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7276 uint32_t plane_bit = 0;
7c9017e5
JB		 7277 int ret;
7278
7279 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7280 if (ret)
83d4092b 7281 goto err;
7c9017e5 7282
cb05d8de
DV		 7283 switch(intel_crtc->plane) {
7284 case PLANE_A:
7285 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7286 break;
7287 case PLANE_B:
7288 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7289 break;
7290 case PLANE_C:
7291 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7292 break;
7293 default:
7294 WARN_ONCE(1, "unknown plane in flip command\n");
7295 ret = -ENODEV;
ab3951eb 7296 goto err_unpin;
cb05d8de
DV		 7297 }
7298
7c9017e5
JB		 7299 ret = intel_ring_begin(ring, 4);
7300 if (ret)
83d4092b 7301 goto err_unpin;
7c9017e5 7302
cb05d8de 7303 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7304 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7305 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7306 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7307
7308 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7309 intel_ring_advance(ring);
83d4092b
CW		 7310 return 0;
7311
7312err_unpin:
7313 intel_unpin_fb_obj(obj);
7314err:
7c9017e5
JB		 7315 return ret;
7316}
7317
8c9f3aaf
JB		 7318static int intel_default_queue_flip(struct drm_device *dev,
7319 struct drm_crtc *crtc,
7320 struct drm_framebuffer *fb,
7321 struct drm_i915_gem_object *obj)
7322{
7323 return -ENODEV;
7324}
7325
6b95a207
KH		 7326static int intel_crtc_page_flip(struct drm_crtc *crtc,
7327 struct drm_framebuffer *fb,
7328 struct drm_pending_vblank_event *event)
7329{
7330 struct drm_device *dev = crtc->dev;
7331 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7332 struct drm_framebuffer *old_fb = crtc->fb;
7333 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7334 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7335 struct intel_unpin_work *work;
8c9f3aaf 7336 unsigned long flags;
52e68630 7337 int ret;
6b95a207 7338
e6a595d2
VS		 7339 /* Can't change pixel format via MI display flips. */
7340 if (fb->pixel_format != crtc->fb->pixel_format)
7341 return -EINVAL;
7342
7343 /*
7344 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7345 * Note that pitch changes could also affect these register.
7346 */
7347 if (INTEL_INFO(dev)->gen > 3 &&
7348 (fb->offsets[0] != crtc->fb->offsets[0] ||
7349 fb->pitches[0] != crtc->fb->pitches[0]))
7350 return -EINVAL;
7351
6b95a207
KH		 7352 work = kzalloc(sizeof *work, GFP_KERNEL);
7353 if (work == NULL)
7354 return -ENOMEM;
7355
6b95a207 7356 work->event = event;
b4a98e57 7357 work->crtc = crtc;
4a35f83b 7358 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7359 INIT_WORK(&work->work, intel_unpin_work_fn);
7360
7317c75e
JB		 7361 ret = drm_vblank_get(dev, intel_crtc->pipe);
7362 if (ret)
7363 goto free_work;
7364
6b95a207
KH		 7365 /* We borrow the event spin lock for protecting unpin_work */
7366 spin_lock_irqsave(&dev->event_lock, flags);
7367 if (intel_crtc->unpin_work) {
7368 spin_unlock_irqrestore(&dev->event_lock, flags);
7369 kfree(work);
7317c75e 7370 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7371
7372 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7373 return -EBUSY;
7374 }
7375 intel_crtc->unpin_work = work;
7376 spin_unlock_irqrestore(&dev->event_lock, flags);
7377
b4a98e57
CW		 7378 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7379 flush_workqueue(dev_priv->wq);
7380
79158103
CW		 7381 ret = i915_mutex_lock_interruptible(dev);
7382 if (ret)
7383 goto cleanup;
6b95a207 7384
75dfca80 7385 /* Reference the objects for the scheduled work. */
05394f39
CW		 7386 drm_gem_object_reference(&work->old_fb_obj->base);
7387 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7388
7389 crtc->fb = fb;
96b099fd 7390
e1f99ce6 7391 work->pending_flip_obj = obj;
e1f99ce6 7392
4e5359cd
SF		 7393 work->enable_stall_check = true;
7394
b4a98e57 7395 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7396 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7397
8c9f3aaf
JB		 7398 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7399 if (ret)
7400 goto cleanup_pending;
6b95a207 7401
7782de3b 7402 intel_disable_fbc(dev);
f047e395 7403 intel_mark_fb_busy(obj);
6b95a207
KH		 7404 mutex_unlock(&dev->struct_mutex);
7405
e5510fac
JB		 7406 trace_i915_flip_request(intel_crtc->plane, obj);
7407
6b95a207 7408 return 0;
96b099fd 7409
8c9f3aaf 7410cleanup_pending:
b4a98e57 7411 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7412 crtc->fb = old_fb;
05394f39
CW		 7413 drm_gem_object_unreference(&work->old_fb_obj->base);
7414 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7415 mutex_unlock(&dev->struct_mutex);
7416
79158103 7417cleanup:
96b099fd
CW		 7418 spin_lock_irqsave(&dev->event_lock, flags);
7419 intel_crtc->unpin_work = NULL;
7420 spin_unlock_irqrestore(&dev->event_lock, flags);
7421
7317c75e
JB		 7422 drm_vblank_put(dev, intel_crtc->pipe);
7423free_work:
96b099fd
CW		 7424 kfree(work);
7425
7426 return ret;
6b95a207
KH		 7427}
7428
f6e5b160 7429static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7430 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7431 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7432};
7433
6ed0f796 7434bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7435{
6ed0f796
DV		 7436 struct intel_encoder *other_encoder;
7437 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7438
6ed0f796
DV		 7439 if (WARN_ON(!crtc))
7440 return false;
7441
7442 list_for_each_entry(other_encoder,
7443 &crtc->dev->mode_config.encoder_list,
7444 base.head) {
7445
7446 if (&other_encoder->new_crtc->base != crtc ||
7447 encoder == other_encoder)
7448 continue;
7449 else
7450 return true;
f47166d2
CW		 7451 }
7452
6ed0f796
DV		 7453 return false;
7454}
47f1c6c9 7455
50f56119
DV		 7456static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7457 struct drm_crtc *crtc)
7458{
7459 struct drm_device *dev;
7460 struct drm_crtc *tmp;
7461 int crtc_mask = 1;
47f1c6c9 7462
50f56119 7463 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7464
50f56119 7465 dev = crtc->dev;
47f1c6c9 7466
50f56119
DV		 7467 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7468 if (tmp == crtc)
7469 break;
7470 crtc_mask <<= 1;
7471 }
47f1c6c9 7472
50f56119
DV		 7473 if (encoder->possible_crtcs & crtc_mask)
7474 return true;
7475 return false;
47f1c6c9 7476}
79e53945 7477
9a935856
DV		 7478/**
7479 * intel_modeset_update_staged_output_state
7480 *
7481 * Updates the staged output configuration state, e.g. after we've read out the
7482 * current hw state.
7483 */
7484static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7485{
9a935856
DV		 7486 struct intel_encoder *encoder;
7487 struct intel_connector *connector;
f6e5b160 7488
9a935856
DV		 7489 list_for_each_entry(connector, &dev->mode_config.connector_list,
7490 base.head) {
7491 connector->new_encoder =
7492 to_intel_encoder(connector->base.encoder);
7493 }
f6e5b160 7494
9a935856
DV		 7495 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7496 base.head) {
7497 encoder->new_crtc =
7498 to_intel_crtc(encoder->base.crtc);
7499 }
f6e5b160
CW		 7500}
7501
9a935856
DV		 7502/**
7503 * intel_modeset_commit_output_state
7504 *
7505 * This function copies the stage display pipe configuration to the real one.
7506 */
7507static void intel_modeset_commit_output_state(struct drm_device *dev)
7508{
7509 struct intel_encoder *encoder;
7510 struct intel_connector *connector;
f6e5b160 7511
9a935856
DV		 7512 list_for_each_entry(connector, &dev->mode_config.connector_list,
7513 base.head) {
7514 connector->base.encoder = &connector->new_encoder->base;
7515 }
f6e5b160 7516
9a935856
DV		 7517 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7518 base.head) {
7519 encoder->base.crtc = &encoder->new_crtc->base;
7520 }
7521}
7522
4e53c2e0
DV		 7523static int
7524pipe_config_set_bpp(struct drm_crtc *crtc,
7525 struct drm_framebuffer *fb,
7526 struct intel_crtc_config *pipe_config)
7527{
7528 struct drm_device *dev = crtc->dev;
7529 struct drm_connector *connector;
7530 int bpp;
7531
d42264b1
DV		 7532 switch (fb->pixel_format) {
7533 case DRM_FORMAT_C8:
4e53c2e0
DV		 7534 bpp = 8*3; /* since we go through a colormap */
7535 break;
d42264b1
DV		 7536 case DRM_FORMAT_XRGB1555:
7537 case DRM_FORMAT_ARGB1555:
7538 /* checked in intel_framebuffer_init already */
7539 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7540 return -EINVAL;
7541 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 7542 bpp = 6*3; /* min is 18bpp */
7543 break;
d42264b1
DV		 7544 case DRM_FORMAT_XBGR8888:
7545 case DRM_FORMAT_ABGR8888:
7546 /* checked in intel_framebuffer_init already */
7547 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7548 return -EINVAL;
7549 case DRM_FORMAT_XRGB8888:
7550 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 7551 bpp = 8*3;
7552 break;
d42264b1
DV		 7553 case DRM_FORMAT_XRGB2101010:
7554 case DRM_FORMAT_ARGB2101010:
7555 case DRM_FORMAT_XBGR2101010:
7556 case DRM_FORMAT_ABGR2101010:
7557 /* checked in intel_framebuffer_init already */
7558 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 7559 return -EINVAL;
4e53c2e0
DV		 7560 bpp = 10*3;
7561 break;
baba133a 7562 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 7563 default:
7564 DRM_DEBUG_KMS("unsupported depth\n");
7565 return -EINVAL;
7566 }
7567
4e53c2e0
DV		 7568 pipe_config->pipe_bpp = bpp;
7569
7570 /* Clamp display bpp to EDID value */
7571 list_for_each_entry(connector, &dev->mode_config.connector_list,
7572 head) {
7573 if (connector->encoder && connector->encoder->crtc != crtc)
7574 continue;
7575
7576 /* Don't use an invalid EDID bpc value */
7577 if (connector->display_info.bpc &&
7578 connector->display_info.bpc * 3 < bpp) {
7579 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7580 bpp, connector->display_info.bpc*3);
7581 pipe_config->pipe_bpp = connector->display_info.bpc*3;
7582 }
7583 }
7584
7585 return bpp;
7586}
7587
b8cecdf5
DV		 7588static struct intel_crtc_config *
7589intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 7590 struct drm_framebuffer *fb,
b8cecdf5 7591 struct drm_display_mode *mode)
ee7b9f93 7592{
7758a113 7593 struct drm_device *dev = crtc->dev;
7758a113
DV		 7594 struct drm_encoder_helper_funcs *encoder_funcs;
7595 struct intel_encoder *encoder;
b8cecdf5 7596 struct intel_crtc_config *pipe_config;
4e53c2e0 7597 int plane_bpp;
ee7b9f93 7598
b8cecdf5
DV		 7599 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7600 if (!pipe_config)
7758a113
DV		 7601 return ERR_PTR(-ENOMEM);
7602
b8cecdf5
DV		 7603 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7604 drm_mode_copy(&pipe_config->requested_mode, mode);
7605
4e53c2e0
DV		 7606 plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
7607 if (plane_bpp < 0)
7608 goto fail;
7609
7758a113
DV		 7610 /* Pass our mode to the connectors and the CRTC to give them a chance to
7611 * adjust it according to limitations or connector properties, and also
7612 * a chance to reject the mode entirely.
47f1c6c9 7613 */
7758a113
DV		 7614 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7615 base.head) {
47f1c6c9 7616
7758a113
DV		 7617 if (&encoder->new_crtc->base != crtc)
7618 continue;
7ae89233
DV		 7619
7620 if (encoder->compute_config) {
7621 if (!(encoder->compute_config(encoder, pipe_config))) {
7622 DRM_DEBUG_KMS("Encoder config failure\n");
7623 goto fail;
7624 }
7625
7626 continue;
7627 }
7628
7758a113 7629 encoder_funcs = encoder->base.helper_private;
b8cecdf5
DV		 7630 if (!(encoder_funcs->mode_fixup(&encoder->base,
7631 &pipe_config->requested_mode,
7632 &pipe_config->adjusted_mode))) {
7758a113
DV		 7633 DRM_DEBUG_KMS("Encoder fixup failed\n");
7634 goto fail;
7635 }
ee7b9f93 7636 }
47f1c6c9 7637
b8cecdf5 7638 if (!(intel_crtc_compute_config(crtc, pipe_config))) {
7758a113
DV		 7639 DRM_DEBUG_KMS("CRTC fixup failed\n");
7640 goto fail;
ee7b9f93 7641 }
7758a113 7642 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
47f1c6c9 7643
4e53c2e0
DV		 7644 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7645 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7646 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7647
b8cecdf5 7648 return pipe_config;
7758a113 7649fail:
b8cecdf5 7650 kfree(pipe_config);
7758a113 7651 return ERR_PTR(-EINVAL);
ee7b9f93 7652}
47f1c6c9 7653
e2e1ed41
DV		 7654/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7655 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7656static void
7657intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7658 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7659{
7660 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7661 struct drm_device *dev = crtc->dev;
7662 struct intel_encoder *encoder;
7663 struct intel_connector *connector;
7664 struct drm_crtc *tmp_crtc;
79e53945 7665
e2e1ed41 7666 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7667
e2e1ed41
DV		 7668 /* Check which crtcs have changed outputs connected to them, these need
7669 * to be part of the prepare_pipes mask. We don't (yet) support global
7670 * modeset across multiple crtcs, so modeset_pipes will only have one
7671 * bit set at most. */
7672 list_for_each_entry(connector, &dev->mode_config.connector_list,
7673 base.head) {
7674 if (connector->base.encoder == &connector->new_encoder->base)
7675 continue;
79e53945 7676
e2e1ed41
DV		 7677 if (connector->base.encoder) {
7678 tmp_crtc = connector->base.encoder->crtc;
7679
7680 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7681 }
7682
7683 if (connector->new_encoder)
7684 *prepare_pipes |=
7685 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7686 }
7687
e2e1ed41
DV		 7688 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7689 base.head) {
7690 if (encoder->base.crtc == &encoder->new_crtc->base)
7691 continue;
7692
7693 if (encoder->base.crtc) {
7694 tmp_crtc = encoder->base.crtc;
7695
7696 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7697 }
7698
7699 if (encoder->new_crtc)
7700 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7701 }
7702
e2e1ed41
DV		 7703 /* Check for any pipes that will be fully disabled ... */
7704 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7705 base.head) {
7706 bool used = false;
22fd0fab 7707
e2e1ed41
DV		 7708 /* Don't try to disable disabled crtcs. */
7709 if (!intel_crtc->base.enabled)
7710 continue;
7e7d76c3 7711
e2e1ed41
DV		 7712 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7713 base.head) {
7714 if (encoder->new_crtc == intel_crtc)
7715 used = true;
7716 }
7717
7718 if (!used)
7719 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7720 }
7721
e2e1ed41
DV		 7722
7723 /* set_mode is also used to update properties on life display pipes. */
7724 intel_crtc = to_intel_crtc(crtc);
7725 if (crtc->enabled)
7726 *prepare_pipes |= 1 << intel_crtc->pipe;
7727
b6c5164d
DV		 7728 /*
7729 * For simplicity do a full modeset on any pipe where the output routing
7730 * changed. We could be more clever, but that would require us to be
7731 * more careful with calling the relevant encoder->mode_set functions.
7732 */
e2e1ed41
DV		 7733 if (*prepare_pipes)
7734 *modeset_pipes = *prepare_pipes;
7735
7736 /* ... and mask these out. */
7737 *modeset_pipes &= ~(*disable_pipes);
7738 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 7739
7740 /*
7741 * HACK: We don't (yet) fully support global modesets. intel_set_config
7742 * obies this rule, but the modeset restore mode of
7743 * intel_modeset_setup_hw_state does not.
7744 */
7745 *modeset_pipes &= 1 << intel_crtc->pipe;
7746 *prepare_pipes &= 1 << intel_crtc->pipe;
47f1c6c9 7747}
79e53945 7748
ea9d758d 7749static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7750{
ea9d758d 7751 struct drm_encoder *encoder;
f6e5b160 7752 struct drm_device *dev = crtc->dev;
f6e5b160 7753
ea9d758d
DV		 7754 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7755 if (encoder->crtc == crtc)
7756 return true;
7757
7758 return false;
7759}
7760
7761static void
7762intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7763{
7764 struct intel_encoder *intel_encoder;
7765 struct intel_crtc *intel_crtc;
7766 struct drm_connector *connector;
7767
7768 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7769 base.head) {
7770 if (!intel_encoder->base.crtc)
7771 continue;
7772
7773 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7774
7775 if (prepare_pipes & (1 << intel_crtc->pipe))
7776 intel_encoder->connectors_active = false;
7777 }
7778
7779 intel_modeset_commit_output_state(dev);
7780
7781 /* Update computed state. */
7782 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7783 base.head) {
7784 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7785 }
7786
7787 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7788 if (!connector->encoder || !connector->encoder->crtc)
7789 continue;
7790
7791 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7792
7793 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7794 struct drm_property *dpms_property =
7795 dev->mode_config.dpms_property;
7796
ea9d758d 7797 connector->dpms = DRM_MODE_DPMS_ON;
662595df 7798 drm_object_property_set_value(&connector->base,
68d34720
DV		 7799 dpms_property,
7800 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7801
7802 intel_encoder = to_intel_encoder(connector->encoder);
7803 intel_encoder->connectors_active = true;
7804 }
7805 }
7806
7807}
7808
25c5b266
DV		 7809#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7810 list_for_each_entry((intel_crtc), \
7811 &(dev)->mode_config.crtc_list, \
7812 base.head) \
7813 if (mask & (1 <<(intel_crtc)->pipe)) \
7814
0e8ffe1b
DV		 7815static bool
7816intel_pipe_config_compare(struct intel_crtc_config *current_config,
7817 struct intel_crtc_config *pipe_config)
7818{
88adfff1
DV		 7819 if (current_config->has_pch_encoder != pipe_config->has_pch_encoder) {
7820 DRM_ERROR("mismatch in has_pch_encoder "
7821 "(expected %i, found %i)\n",
7822 current_config->has_pch_encoder,
7823 pipe_config->has_pch_encoder);
7824 return false;
7825 }
7826
0e8ffe1b
DV		 7827 return true;
7828}
7829
b980514c 7830void
8af6cf88
DV		 7831intel_modeset_check_state(struct drm_device *dev)
7832{
0e8ffe1b 7833 drm_i915_private_t *dev_priv = dev->dev_private;
8af6cf88
DV		 7834 struct intel_crtc *crtc;
7835 struct intel_encoder *encoder;
7836 struct intel_connector *connector;
0e8ffe1b 7837 struct intel_crtc_config pipe_config;
8af6cf88
DV		 7838
7839 list_for_each_entry(connector, &dev->mode_config.connector_list,
7840 base.head) {
7841 /* This also checks the encoder/connector hw state with the
7842 * ->get_hw_state callbacks. */
7843 intel_connector_check_state(connector);
7844
7845 WARN(&connector->new_encoder->base != connector->base.encoder,
7846 "connector's staged encoder doesn't match current encoder\n");
7847 }
7848
7849 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7850 base.head) {
7851 bool enabled = false;
7852 bool active = false;
7853 enum pipe pipe, tracked_pipe;
7854
7855 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7856 encoder->base.base.id,
7857 drm_get_encoder_name(&encoder->base));
7858
7859 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7860 "encoder's stage crtc doesn't match current crtc\n");
7861 WARN(encoder->connectors_active && !encoder->base.crtc,
7862 "encoder's active_connectors set, but no crtc\n");
7863
7864 list_for_each_entry(connector, &dev->mode_config.connector_list,
7865 base.head) {
7866 if (connector->base.encoder != &encoder->base)
7867 continue;
7868 enabled = true;
7869 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7870 active = true;
7871 }
7872 WARN(!!encoder->base.crtc != enabled,
7873 "encoder's enabled state mismatch "
7874 "(expected %i, found %i)\n",
7875 !!encoder->base.crtc, enabled);
7876 WARN(active && !encoder->base.crtc,
7877 "active encoder with no crtc\n");
7878
7879 WARN(encoder->connectors_active != active,
7880 "encoder's computed active state doesn't match tracked active state "
7881 "(expected %i, found %i)\n", active, encoder->connectors_active);
7882
7883 active = encoder->get_hw_state(encoder, &pipe);
7884 WARN(active != encoder->connectors_active,
7885 "encoder's hw state doesn't match sw tracking "
7886 "(expected %i, found %i)\n",
7887 encoder->connectors_active, active);
7888
7889 if (!encoder->base.crtc)
7890 continue;
7891
7892 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7893 WARN(active && pipe != tracked_pipe,
7894 "active encoder's pipe doesn't match"
7895 "(expected %i, found %i)\n",
7896 tracked_pipe, pipe);
7897
7898 }
7899
7900 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7901 base.head) {
7902 bool enabled = false;
7903 bool active = false;
7904
7905 DRM_DEBUG_KMS("[CRTC:%d]\n",
7906 crtc->base.base.id);
7907
7908 WARN(crtc->active && !crtc->base.enabled,
7909 "active crtc, but not enabled in sw tracking\n");
7910
7911 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7912 base.head) {
7913 if (encoder->base.crtc != &crtc->base)
7914 continue;
7915 enabled = true;
7916 if (encoder->connectors_active)
7917 active = true;
7918 }
7919 WARN(active != crtc->active,
7920 "crtc's computed active state doesn't match tracked active state "
7921 "(expected %i, found %i)\n", active, crtc->active);
7922 WARN(enabled != crtc->base.enabled,
7923 "crtc's computed enabled state doesn't match tracked enabled state "
7924 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7925
88adfff1 7926 memset(&pipe_config, 0, sizeof(pipe_config));
0e8ffe1b
DV		 7927 active = dev_priv->display.get_pipe_config(crtc,
7928 &pipe_config);
7929 WARN(crtc->active != active,
7930 "crtc active state doesn't match with hw state "
7931 "(expected %i, found %i)\n", crtc->active, active);
7932
7933 WARN(active &&
7934 !intel_pipe_config_compare(&crtc->config, &pipe_config),
7935 "pipe state doesn't match!\n");
8af6cf88
DV		 7936 }
7937}
7938
f30da187
DV		 7939static int __intel_set_mode(struct drm_crtc *crtc,
7940 struct drm_display_mode *mode,
7941 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 7942{
7943 struct drm_device *dev = crtc->dev;
dbf2b54e 7944 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 7945 struct drm_display_mode *saved_mode, *saved_hwmode;
7946 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 7947 struct intel_crtc *intel_crtc;
7948 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 7949 int ret = 0;
a6778b3c 7950
3ac18232 7951 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 7952 if (!saved_mode)
7953 return -ENOMEM;
3ac18232 7954 saved_hwmode = saved_mode + 1;
a6778b3c 7955
e2e1ed41 7956 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 7957 &prepare_pipes, &disable_pipes);
7958
3ac18232
TG		 7959 *saved_hwmode = crtc->hwmode;
7960 *saved_mode = crtc->mode;
a6778b3c 7961
25c5b266
DV		 7962 /* Hack: Because we don't (yet) support global modeset on multiple
7963 * crtcs, we don't keep track of the new mode for more than one crtc.
7964 * Hence simply check whether any bit is set in modeset_pipes in all the
7965 * pieces of code that are not yet converted to deal with mutliple crtcs
7966 * changing their mode at the same time. */
25c5b266 7967 if (modeset_pipes) {
4e53c2e0 7968 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 7969 if (IS_ERR(pipe_config)) {
7970 ret = PTR_ERR(pipe_config);
7971 pipe_config = NULL;
7972
3ac18232 7973 goto out;
25c5b266 7974 }
25c5b266 7975 }
a6778b3c 7976
460da916
DV		 7977 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7978 modeset_pipes, prepare_pipes, disable_pipes);
7979
7980 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7981 intel_crtc_disable(&intel_crtc->base);
7982
ea9d758d
DV		 7983 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7984 if (intel_crtc->base.enabled)
7985 dev_priv->display.crtc_disable(&intel_crtc->base);
7986 }
a6778b3c 7987
6c4c86f5
DV		 7988 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7989 * to set it here already despite that we pass it down the callchain.
f6e5b160 7990 */
b8cecdf5 7991 if (modeset_pipes) {
3b117c8f 7992 enum transcoder tmp = to_intel_crtc(crtc)->config.cpu_transcoder;
25c5b266 7993 crtc->mode = *mode;
b8cecdf5
DV		 7994 /* mode_set/enable/disable functions rely on a correct pipe
7995 * config. */
7996 to_intel_crtc(crtc)->config = *pipe_config;
3b117c8f 7997 to_intel_crtc(crtc)->config.cpu_transcoder = tmp;
b8cecdf5 7998 }
7758a113 7999
ea9d758d
DV		 8000 /* Only after disabling all output pipelines that will be changed can we
8001 * update the the output configuration. */
8002 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 8003
47fab737
DV		 8004 if (dev_priv->display.modeset_global_resources)
8005 dev_priv->display.modeset_global_resources(dev);
8006
a6778b3c
DV		 8007 /* Set up the DPLL and any encoders state that needs to adjust or depend
8008 * on the DPLL.
f6e5b160 8009 */
25c5b266 8010 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 8011 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 8012 x, y, fb);
8013 if (ret)
8014 goto done;
a6778b3c
DV		 8015 }
8016
8017 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 8018 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8019 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 8020
25c5b266
DV		 8021 if (modeset_pipes) {
8022 /* Store real post-adjustment hardware mode. */
b8cecdf5 8023 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 8024
25c5b266
DV		 8025 /* Calculate and store various constants which
8026 * are later needed by vblank and swap-completion
8027 * timestamping. They are derived from true hwmode.
8028 */
8029 drm_calc_timestamping_constants(crtc);
8030 }
a6778b3c
DV		 8031
8032 /* FIXME: add subpixel order */
8033done:
c0c36b94 8034 if (ret && crtc->enabled) {
3ac18232
TG		 8035 crtc->hwmode = *saved_hwmode;
8036 crtc->mode = *saved_mode;
a6778b3c
DV		 8037 }
8038
3ac18232 8039out:
b8cecdf5 8040 kfree(pipe_config);
3ac18232 8041 kfree(saved_mode);
a6778b3c 8042 return ret;
f6e5b160
CW		 8043}
8044
f30da187
DV		 8045int intel_set_mode(struct drm_crtc *crtc,
8046 struct drm_display_mode *mode,
8047 int x, int y, struct drm_framebuffer *fb)
8048{
8049 int ret;
8050
8051 ret = __intel_set_mode(crtc, mode, x, y, fb);
8052
8053 if (ret == 0)
8054 intel_modeset_check_state(crtc->dev);
8055
8056 return ret;
8057}
8058
c0c36b94
CW		 8059void intel_crtc_restore_mode(struct drm_crtc *crtc)
8060{
8061 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8062}
8063
25c5b266
DV		 8064#undef for_each_intel_crtc_masked
8065
d9e55608
DV		 8066static void intel_set_config_free(struct intel_set_config *config)
8067{
8068 if (!config)
8069 return;
8070
1aa4b628
DV		 8071 kfree(config->save_connector_encoders);
8072 kfree(config->save_encoder_crtcs);
d9e55608
DV		 8073 kfree(config);
8074}
8075
85f9eb71
DV		 8076static int intel_set_config_save_state(struct drm_device *dev,
8077 struct intel_set_config *config)
8078{
85f9eb71
DV		 8079 struct drm_encoder *encoder;
8080 struct drm_connector *connector;
8081 int count;
8082
1aa4b628
DV		 8083 config->save_encoder_crtcs =
8084 kcalloc(dev->mode_config.num_encoder,
8085 sizeof(struct drm_crtc *), GFP_KERNEL);
8086 if (!config->save_encoder_crtcs)
85f9eb71
DV		 8087 return -ENOMEM;
8088
1aa4b628
DV		 8089 config->save_connector_encoders =
8090 kcalloc(dev->mode_config.num_connector,
8091 sizeof(struct drm_encoder *), GFP_KERNEL);
8092 if (!config->save_connector_encoders)
85f9eb71
DV		 8093 return -ENOMEM;
8094
8095 /* Copy data. Note that driver private data is not affected.
8096 * Should anything bad happen only the expected state is
8097 * restored, not the drivers personal bookkeeping.
8098 */
85f9eb71
DV		 8099 count = 0;
8100 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 8101 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 8102 }
8103
8104 count = 0;
8105 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 8106 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 8107 }
8108
8109 return 0;
8110}
8111
8112static void intel_set_config_restore_state(struct drm_device *dev,
8113 struct intel_set_config *config)
8114{
9a935856
DV		 8115 struct intel_encoder *encoder;
8116 struct intel_connector *connector;
85f9eb71
DV		 8117 int count;
8118
85f9eb71 8119 count = 0;
9a935856
DV		 8120 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8121 encoder->new_crtc =
8122 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 8123 }
8124
8125 count = 0;
9a935856
DV		 8126 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8127 connector->new_encoder =
8128 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 8129 }
8130}
8131
5e2b584e
DV		 8132static void
8133intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8134 struct intel_set_config *config)
8135{
8136
8137 /* We should be able to check here if the fb has the same properties
8138 * and then just flip_or_move it */
8139 if (set->crtc->fb != set->fb) {
8140 /* If we have no fb then treat it as a full mode set */
8141 if (set->crtc->fb == NULL) {
8142 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8143 config->mode_changed = true;
8144 } else if (set->fb == NULL) {
8145 config->mode_changed = true;
72f4901e
DV		 8146 } else if (set->fb->pixel_format !=
8147 set->crtc->fb->pixel_format) {
5e2b584e
DV		 8148 config->mode_changed = true;
8149 } else
8150 config->fb_changed = true;
8151 }
8152
835c5873 8153 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 8154 config->fb_changed = true;
8155
8156 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8157 DRM_DEBUG_KMS("modes are different, full mode set\n");
8158 drm_mode_debug_printmodeline(&set->crtc->mode);
8159 drm_mode_debug_printmodeline(set->mode);
8160 config->mode_changed = true;
8161 }
8162}
8163
2e431051 8164static int
9a935856
DV		 8165intel_modeset_stage_output_state(struct drm_device *dev,
8166 struct drm_mode_set *set,
8167 struct intel_set_config *config)
50f56119 8168{
85f9eb71 8169 struct drm_crtc *new_crtc;
9a935856
DV		 8170 struct intel_connector *connector;
8171 struct intel_encoder *encoder;
2e431051 8172 int count, ro;
50f56119 8173
9abdda74 8174 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 8175 * of connectors. For paranoia, double-check this. */
8176 WARN_ON(!set->fb && (set->num_connectors != 0));
8177 WARN_ON(set->fb && (set->num_connectors == 0));
8178
50f56119 8179 count = 0;
9a935856
DV		 8180 list_for_each_entry(connector, &dev->mode_config.connector_list,
8181 base.head) {
8182 /* Otherwise traverse passed in connector list and get encoders
8183 * for them. */
50f56119 8184 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 8185 if (set->connectors[ro] == &connector->base) {
8186 connector->new_encoder = connector->encoder;
50f56119
DV		 8187 break;
8188 }
8189 }
8190
9a935856
DV		 8191 /* If we disable the crtc, disable all its connectors. Also, if
8192 * the connector is on the changing crtc but not on the new
8193 * connector list, disable it. */
8194 if ((!set->fb || ro == set->num_connectors) &&
8195 connector->base.encoder &&
8196 connector->base.encoder->crtc == set->crtc) {
8197 connector->new_encoder = NULL;
8198
8199 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8200 connector->base.base.id,
8201 drm_get_connector_name(&connector->base));
8202 }
8203
8204
8205 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8206 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8207 config->mode_changed = true;
50f56119
DV		 8208 }
8209 }
9a935856 8210 /* connector->new_encoder is now updated for all connectors. */
50f56119 8211
9a935856 8212 /* Update crtc of enabled connectors. */
50f56119 8213 count = 0;
9a935856
DV		 8214 list_for_each_entry(connector, &dev->mode_config.connector_list,
8215 base.head) {
8216 if (!connector->new_encoder)
50f56119
DV		 8217 continue;
8218
9a935856 8219 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8220
8221 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8222 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8223 new_crtc = set->crtc;
8224 }
8225
8226 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8227 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8228 new_crtc)) {
5e2b584e 8229 return -EINVAL;
50f56119 8230 }
9a935856
DV		 8231 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8232
8233 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8234 connector->base.base.id,
8235 drm_get_connector_name(&connector->base),
8236 new_crtc->base.id);
8237 }
8238
8239 /* Check for any encoders that needs to be disabled. */
8240 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8241 base.head) {
8242 list_for_each_entry(connector,
8243 &dev->mode_config.connector_list,
8244 base.head) {
8245 if (connector->new_encoder == encoder) {
8246 WARN_ON(!connector->new_encoder->new_crtc);
8247
8248 goto next_encoder;
8249 }
8250 }
8251 encoder->new_crtc = NULL;
8252next_encoder:
8253 /* Only now check for crtc changes so we don't miss encoders
8254 * that will be disabled. */
8255 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8256 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8257 config->mode_changed = true;
50f56119
DV		 8258 }
8259 }
9a935856 8260 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8261
2e431051
DV		 8262 return 0;
8263}
8264
8265static int intel_crtc_set_config(struct drm_mode_set *set)
8266{
8267 struct drm_device *dev;
2e431051
DV		 8268 struct drm_mode_set save_set;
8269 struct intel_set_config *config;
8270 int ret;
2e431051 8271
8d3e375e
DV		 8272 BUG_ON(!set);
8273 BUG_ON(!set->crtc);
8274 BUG_ON(!set->crtc->helper_private);
2e431051 8275
7e53f3a4
DV		 8276 /* Enforce sane interface api - has been abused by the fb helper. */
8277 BUG_ON(!set->mode && set->fb);
8278 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 8279
2e431051
DV		 8280 if (set->fb) {
8281 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8282 set->crtc->base.id, set->fb->base.id,
8283 (int)set->num_connectors, set->x, set->y);
8284 } else {
8285 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8286 }
8287
8288 dev = set->crtc->dev;
8289
8290 ret = -ENOMEM;
8291 config = kzalloc(sizeof(*config), GFP_KERNEL);
8292 if (!config)
8293 goto out_config;
8294
8295 ret = intel_set_config_save_state(dev, config);
8296 if (ret)
8297 goto out_config;
8298
8299 save_set.crtc = set->crtc;
8300 save_set.mode = &set->crtc->mode;
8301 save_set.x = set->crtc->x;
8302 save_set.y = set->crtc->y;
8303 save_set.fb = set->crtc->fb;
8304
8305 /* Compute whether we need a full modeset, only an fb base update or no
8306 * change at all. In the future we might also check whether only the
8307 * mode changed, e.g. for LVDS where we only change the panel fitter in
8308 * such cases. */
8309 intel_set_config_compute_mode_changes(set, config);
8310
9a935856 8311 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8312 if (ret)
8313 goto fail;
8314
5e2b584e 8315 if (config->mode_changed) {
87f1faa6 8316 if (set->mode) {
50f56119
DV		 8317 DRM_DEBUG_KMS("attempting to set mode from"
8318 " userspace\n");
8319 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 8320 }
8321
c0c36b94
CW		 8322 ret = intel_set_mode(set->crtc, set->mode,
8323 set->x, set->y, set->fb);
8324 if (ret) {
8325 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8326 set->crtc->base.id, ret);
87f1faa6
DV		 8327 goto fail;
8328 }
5e2b584e 8329 } else if (config->fb_changed) {
4878cae2
VS		 8330 intel_crtc_wait_for_pending_flips(set->crtc);
8331
4f660f49 8332 ret = intel_pipe_set_base(set->crtc,
94352cf9 8333 set->x, set->y, set->fb);
50f56119
DV		 8334 }
8335
d9e55608
DV		 8336 intel_set_config_free(config);
8337
50f56119
DV		 8338 return 0;
8339
8340fail:
85f9eb71 8341 intel_set_config_restore_state(dev, config);
50f56119
DV		 8342
8343 /* Try to restore the config */
5e2b584e 8344 if (config->mode_changed &&
c0c36b94
CW		 8345 intel_set_mode(save_set.crtc, save_set.mode,
8346 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8347 DRM_ERROR("failed to restore config after modeset failure\n");
8348
d9e55608
DV		 8349out_config:
8350 intel_set_config_free(config);
50f56119
DV		 8351 return ret;
8352}
f6e5b160
CW		 8353
8354static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8355 .cursor_set = intel_crtc_cursor_set,
8356 .cursor_move = intel_crtc_cursor_move,
8357 .gamma_set = intel_crtc_gamma_set,
50f56119 8358 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8359 .destroy = intel_crtc_destroy,
8360 .page_flip = intel_crtc_page_flip,
8361};
8362
79f689aa
PZ		 8363static void intel_cpu_pll_init(struct drm_device *dev)
8364{
affa9354 8365 if (HAS_DDI(dev))
79f689aa
PZ		 8366 intel_ddi_pll_init(dev);
8367}
8368
ee7b9f93
JB		 8369static void intel_pch_pll_init(struct drm_device *dev)
8370{
8371 drm_i915_private_t *dev_priv = dev->dev_private;
8372 int i;
8373
8374 if (dev_priv->num_pch_pll == 0) {
8375 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8376 return;
8377 }
8378
8379 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8380 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8381 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8382 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8383 }
8384}
8385
b358d0a6 8386static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8387{
22fd0fab 8388 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8389 struct intel_crtc *intel_crtc;
8390 int i;
8391
8392 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8393 if (intel_crtc == NULL)
8394 return;
8395
8396 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8397
8398 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8399 for (i = 0; i < 256; i++) {
8400 intel_crtc->lut_r[i] = i;
8401 intel_crtc->lut_g[i] = i;
8402 intel_crtc->lut_b[i] = i;
8403 }
8404
80824003
JB		 8405 /* Swap pipes & planes for FBC on pre-965 */
8406 intel_crtc->pipe = pipe;
8407 intel_crtc->plane = pipe;
3b117c8f 8408 intel_crtc->config.cpu_transcoder = pipe;
e2e767ab 8409 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8410 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8411 intel_crtc->plane = !pipe;
80824003
JB		 8412 }
8413
22fd0fab
JB		 8414 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8415 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8416 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8417 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8418
79e53945 8419 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8420}
8421
08d7b3d1 8422int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8423 struct drm_file *file)
08d7b3d1 8424{
08d7b3d1 8425 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8426 struct drm_mode_object *drmmode_obj;
8427 struct intel_crtc *crtc;
08d7b3d1 8428
1cff8f6b
DV		 8429 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8430 return -ENODEV;
08d7b3d1 8431
c05422d5
DV		 8432 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8433 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8434
c05422d5 8435 if (!drmmode_obj) {
08d7b3d1
CW		 8436 DRM_ERROR("no such CRTC id\n");
8437 return -EINVAL;
8438 }
8439
c05422d5
DV		 8440 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8441 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8442
c05422d5 8443 return 0;
08d7b3d1
CW		 8444}
8445
66a9278e 8446static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8447{
66a9278e
DV		 8448 struct drm_device *dev = encoder->base.dev;
8449 struct intel_encoder *source_encoder;
79e53945 8450 int index_mask = 0;
79e53945
JB		 8451 int entry = 0;
8452
66a9278e
DV		 8453 list_for_each_entry(source_encoder,
8454 &dev->mode_config.encoder_list, base.head) {
8455
8456 if (encoder == source_encoder)
79e53945 8457 index_mask |= (1 << entry);
66a9278e
DV		 8458
8459 /* Intel hw has only one MUX where enocoders could be cloned. */
8460 if (encoder->cloneable && source_encoder->cloneable)
8461 index_mask |= (1 << entry);
8462
79e53945
JB		 8463 entry++;
8464 }
4ef69c7a 8465
79e53945
JB		 8466 return index_mask;
8467}
8468
4d302442
CW		 8469static bool has_edp_a(struct drm_device *dev)
8470{
8471 struct drm_i915_private *dev_priv = dev->dev_private;
8472
8473 if (!IS_MOBILE(dev))
8474 return false;
8475
8476 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8477 return false;
8478
8479 if (IS_GEN5(dev) &&
8480 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8481 return false;
8482
8483 return true;
8484}
8485
79e53945
JB		 8486static void intel_setup_outputs(struct drm_device *dev)
8487{
725e30ad 8488 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8489 struct intel_encoder *encoder;
cb0953d7 8490 bool dpd_is_edp = false;
f3cfcba6 8491 bool has_lvds;
79e53945 8492
f3cfcba6 8493 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8494 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8495 /* disable the panel fitter on everything but LVDS */
8496 I915_WRITE(PFIT_CONTROL, 0);
8497 }
79e53945 8498
c40c0f5b 8499 if (!IS_ULT(dev))
79935fca 8500 intel_crt_init(dev);
cb0953d7 8501
affa9354 8502 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8503 int found;
8504
8505 /* Haswell uses DDI functions to detect digital outputs */
8506 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8507 /* DDI A only supports eDP */
8508 if (found)
8509 intel_ddi_init(dev, PORT_A);
8510
8511 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8512 * register */
8513 found = I915_READ(SFUSE_STRAP);
8514
8515 if (found & SFUSE_STRAP_DDIB_DETECTED)
8516 intel_ddi_init(dev, PORT_B);
8517 if (found & SFUSE_STRAP_DDIC_DETECTED)
8518 intel_ddi_init(dev, PORT_C);
8519 if (found & SFUSE_STRAP_DDID_DETECTED)
8520 intel_ddi_init(dev, PORT_D);
8521 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8522 int found;
270b3042
DV		 8523 dpd_is_edp = intel_dpd_is_edp(dev);
8524
8525 if (has_edp_a(dev))
8526 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8527
dc0fa718 8528 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 8529 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8530 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8531 if (!found)
e2debe91 8532 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 8533 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8534 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8535 }
8536
dc0fa718 8537 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 8538 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 8539
dc0fa718 8540 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 8541 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 8542
5eb08b69 8543 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8544 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8545
270b3042 8546 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8547 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 8548 } else if (IS_VALLEYVIEW(dev)) {
19c03924 8549 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 8550 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8551 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 8552
dc0fa718 8553 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 8554 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8555 PORT_B);
67cfc203
VS		 8556 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8557 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 8558 }
103a196f 8559 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8560 bool found = false;
7d57382e 8561
e2debe91 8562 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8563 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 8564 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 8565 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8566 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 8567 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 8568 }
27185ae1 8569
b01f2c3a
JB		 8570 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8571 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 8572 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 8573 }
725e30ad 8574 }
13520b05
KH		 8575
8576 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8577
e2debe91 8578 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8579 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 8580 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 8581 }
27185ae1 8582
e2debe91 8583 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 8584
b01f2c3a
JB		 8585 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8586 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 8587 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a
JB		 8588 }
8589 if (SUPPORTS_INTEGRATED_DP(dev)) {
8590 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 8591 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 8592 }
725e30ad 8593 }
27185ae1 8594
b01f2c3a
JB		 8595 if (SUPPORTS_INTEGRATED_DP(dev) &&
8596 (I915_READ(DP_D) & DP_DETECTED)) {
8597 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 8598 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 8599 }
bad720ff 8600 } else if (IS_GEN2(dev))
79e53945
JB		 8601 intel_dvo_init(dev);
8602
103a196f 8603 if (SUPPORTS_TV(dev))
79e53945
JB		 8604 intel_tv_init(dev);
8605
4ef69c7a
CW		 8606 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8607 encoder->base.possible_crtcs = encoder->crtc_mask;
8608 encoder->base.possible_clones =
66a9278e 8609 intel_encoder_clones(encoder);
79e53945 8610 }
47356eb6 8611
dde86e2d 8612 intel_init_pch_refclk(dev);
270b3042
DV		 8613
8614 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8615}
8616
8617static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8618{
8619 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8620
8621 drm_framebuffer_cleanup(fb);
05394f39 8622 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8623
8624 kfree(intel_fb);
8625}
8626
8627static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8628 struct drm_file *file,
79e53945
JB		 8629 unsigned int *handle)
8630{
8631 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8632 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8633
05394f39 8634 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8635}
8636
8637static const struct drm_framebuffer_funcs intel_fb_funcs = {
8638 .destroy = intel_user_framebuffer_destroy,
8639 .create_handle = intel_user_framebuffer_create_handle,
8640};
8641
38651674
DA		 8642int intel_framebuffer_init(struct drm_device *dev,
8643 struct intel_framebuffer *intel_fb,
308e5bcb 8644 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8645 struct drm_i915_gem_object *obj)
79e53945 8646{
79e53945
JB		 8647 int ret;
8648
c16ed4be
CW		 8649 if (obj->tiling_mode == I915_TILING_Y) {
8650 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 8651 return -EINVAL;
c16ed4be 8652 }
57cd6508 8653
c16ed4be
CW		 8654 if (mode_cmd->pitches[0] & 63) {
8655 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8656 mode_cmd->pitches[0]);
57cd6508 8657 return -EINVAL;
c16ed4be 8658 }
57cd6508 8659
5d7bd705 8660 /* FIXME <= Gen4 stride limits are bit unclear */
c16ed4be
CW		 8661 if (mode_cmd->pitches[0] > 32768) {
8662 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8663 mode_cmd->pitches[0]);
5d7bd705 8664 return -EINVAL;
c16ed4be 8665 }
5d7bd705
VS		 8666
8667 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 8668 mode_cmd->pitches[0] != obj->stride) {
8669 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8670 mode_cmd->pitches[0], obj->stride);
5d7bd705 8671 return -EINVAL;
c16ed4be 8672 }
5d7bd705 8673
57779d06 8674 /* Reject formats not supported by any plane early. */
308e5bcb 8675 switch (mode_cmd->pixel_format) {
57779d06 8676 case DRM_FORMAT_C8:
04b3924d
VS		 8677 case DRM_FORMAT_RGB565:
8678 case DRM_FORMAT_XRGB8888:
8679 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8680 break;
8681 case DRM_FORMAT_XRGB1555:
8682 case DRM_FORMAT_ARGB1555:
c16ed4be
CW		 8683 if (INTEL_INFO(dev)->gen > 3) {
8684 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8685 return -EINVAL;
c16ed4be 8686 }
57779d06
VS		 8687 break;
8688 case DRM_FORMAT_XBGR8888:
8689 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8690 case DRM_FORMAT_XRGB2101010:
8691 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8692 case DRM_FORMAT_XBGR2101010:
8693 case DRM_FORMAT_ABGR2101010:
c16ed4be
CW		 8694 if (INTEL_INFO(dev)->gen < 4) {
8695 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8696 return -EINVAL;
c16ed4be 8697 }
b5626747 8698 break;
04b3924d
VS		 8699 case DRM_FORMAT_YUYV:
8700 case DRM_FORMAT_UYVY:
8701 case DRM_FORMAT_YVYU:
8702 case DRM_FORMAT_VYUY:
c16ed4be
CW		 8703 if (INTEL_INFO(dev)->gen < 5) {
8704 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8705 return -EINVAL;
c16ed4be 8706 }
57cd6508
CW		 8707 break;
8708 default:
c16ed4be 8709 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8710 return -EINVAL;
8711 }
8712
90f9a336
VS		 8713 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8714 if (mode_cmd->offsets[0] != 0)
8715 return -EINVAL;
8716
c7d73f6a
DV		 8717 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8718 intel_fb->obj = obj;
8719
79e53945
JB		 8720 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8721 if (ret) {
8722 DRM_ERROR("framebuffer init failed %d\n", ret);
8723 return ret;
8724 }
8725
79e53945
JB		 8726 return 0;
8727}
8728
79e53945
JB		 8729static struct drm_framebuffer *
8730intel_user_framebuffer_create(struct drm_device *dev,
8731 struct drm_file *filp,
308e5bcb 8732 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8733{
05394f39 8734 struct drm_i915_gem_object *obj;
79e53945 8735
308e5bcb
JB		 8736 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8737 mode_cmd->handles[0]));
c8725226 8738 if (&obj->base == NULL)
cce13ff7 8739 return ERR_PTR(-ENOENT);
79e53945 8740
d2dff872 8741 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8742}
8743
79e53945 8744static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8745 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8746 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8747};
8748
e70236a8
JB		 8749/* Set up chip specific display functions */
8750static void intel_init_display(struct drm_device *dev)
8751{
8752 struct drm_i915_private *dev_priv = dev->dev_private;
8753
affa9354 8754 if (HAS_DDI(dev)) {
0e8ffe1b 8755 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 8756 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8757 dev_priv->display.crtc_enable = haswell_crtc_enable;
8758 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 8759 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 8760 dev_priv->display.update_plane = ironlake_update_plane;
8761 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 8762 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 8763 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 8764 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8765 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8766 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8767 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8768 } else {
0e8ffe1b 8769 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 8770 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 8771 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8772 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8773 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8774 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8775 }
e70236a8 8776
e70236a8 8777 /* Returns the core display clock speed */
25eb05fc
JB		 8778 if (IS_VALLEYVIEW(dev))
8779 dev_priv->display.get_display_clock_speed =
8780 valleyview_get_display_clock_speed;
8781 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8782 dev_priv->display.get_display_clock_speed =
8783 i945_get_display_clock_speed;
8784 else if (IS_I915G(dev))
8785 dev_priv->display.get_display_clock_speed =
8786 i915_get_display_clock_speed;
f2b115e6 8787 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8788 dev_priv->display.get_display_clock_speed =
8789 i9xx_misc_get_display_clock_speed;
8790 else if (IS_I915GM(dev))
8791 dev_priv->display.get_display_clock_speed =
8792 i915gm_get_display_clock_speed;
8793 else if (IS_I865G(dev))
8794 dev_priv->display.get_display_clock_speed =
8795 i865_get_display_clock_speed;
f0f8a9ce 8796 else if (IS_I85X(dev))
e70236a8
JB		 8797 dev_priv->display.get_display_clock_speed =
8798 i855_get_display_clock_speed;
8799 else /* 852, 830 */
8800 dev_priv->display.get_display_clock_speed =
8801 i830_get_display_clock_speed;
8802
7f8a8569 8803 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8804 if (IS_GEN5(dev)) {
674cf967 8805 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8806 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8807 } else if (IS_GEN6(dev)) {
674cf967 8808 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8809 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8810 } else if (IS_IVYBRIDGE(dev)) {
8811 /* FIXME: detect B0+ stepping and use auto training */
8812 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 8813 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 8814 dev_priv->display.modeset_global_resources =
8815 ivb_modeset_global_resources;
c82e4d26
ED		 8816 } else if (IS_HASWELL(dev)) {
8817 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 8818 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 8819 dev_priv->display.modeset_global_resources =
8820 haswell_modeset_global_resources;
a0e63c22 8821 }
6067aaea 8822 } else if (IS_G4X(dev)) {
e0dac65e 8823 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8824 }
8c9f3aaf
JB		 8825
8826 /* Default just returns -ENODEV to indicate unsupported */
8827 dev_priv->display.queue_flip = intel_default_queue_flip;
8828
8829 switch (INTEL_INFO(dev)->gen) {
8830 case 2:
8831 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8832 break;
8833
8834 case 3:
8835 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8836 break;
8837
8838 case 4:
8839 case 5:
8840 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8841 break;
8842
8843 case 6:
8844 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8845 break;
7c9017e5
JB		 8846 case 7:
8847 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8848 break;
8c9f3aaf 8849 }
e70236a8
JB		 8850}
8851
b690e96c
JB		 8852/*
8853 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8854 * resume, or other times. This quirk makes sure that's the case for
8855 * affected systems.
8856 */
0206e353 8857static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8858{
8859 struct drm_i915_private *dev_priv = dev->dev_private;
8860
8861 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 8862 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 8863}
8864
435793df
KP		 8865/*
8866 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8867 */
8868static void quirk_ssc_force_disable(struct drm_device *dev)
8869{
8870 struct drm_i915_private *dev_priv = dev->dev_private;
8871 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 8872 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 8873}
8874
4dca20ef 8875/*
5a15ab5b
CE		 8876 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8877 * brightness value
4dca20ef
CE		 8878 */
8879static void quirk_invert_brightness(struct drm_device *dev)
8880{
8881 struct drm_i915_private *dev_priv = dev->dev_private;
8882 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 8883 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 8884}
8885
b690e96c
JB		 8886struct intel_quirk {
8887 int device;
8888 int subsystem_vendor;
8889 int subsystem_device;
8890 void (*hook)(struct drm_device *dev);
8891};
8892
5f85f176
EE		 8893/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8894struct intel_dmi_quirk {
8895 void (*hook)(struct drm_device *dev);
8896 const struct dmi_system_id (*dmi_id_list)[];
8897};
8898
8899static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8900{
8901 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8902 return 1;
8903}
8904
8905static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8906 {
8907 .dmi_id_list = &(const struct dmi_system_id[]) {
8908 {
8909 .callback = intel_dmi_reverse_brightness,
8910 .ident = "NCR Corporation",
8911 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8912 DMI_MATCH(DMI_PRODUCT_NAME, ""),
8913 },
8914 },
8915 { } /* terminating entry */
8916 },
8917 .hook = quirk_invert_brightness,
8918 },
8919};
8920
c43b5634 8921static struct intel_quirk intel_quirks[] = {
b690e96c 8922 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8923 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 8924
b690e96c
JB		 8925 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8926 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8927
b690e96c
JB		 8928 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8929 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8930
ccd0d36e 8931 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 8932 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 8933 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 8934
8935 /* Lenovo U160 cannot use SSC on LVDS */
8936 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 8937
8938 /* Sony Vaio Y cannot use SSC on LVDS */
8939 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 8940
8941 /* Acer Aspire 5734Z must invert backlight brightness */
8942 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 8943
8944 /* Acer/eMachines G725 */
8945 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 8946
8947 /* Acer/eMachines e725 */
8948 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 8949
8950 /* Acer/Packard Bell NCL20 */
8951 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 8952
8953 /* Acer Aspire 4736Z */
8954 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 8955};
8956
8957static void intel_init_quirks(struct drm_device *dev)
8958{
8959 struct pci_dev *d = dev->pdev;
8960 int i;
8961
8962 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8963 struct intel_quirk *q = &intel_quirks[i];
8964
8965 if (d->device == q->device &&
8966 (d->subsystem_vendor == q->subsystem_vendor ||
8967 q->subsystem_vendor == PCI_ANY_ID) &&
8968 (d->subsystem_device == q->subsystem_device ||
8969 q->subsystem_device == PCI_ANY_ID))
8970 q->hook(dev);
8971 }
5f85f176
EE		 8972 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8973 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8974 intel_dmi_quirks[i].hook(dev);
8975 }
b690e96c
JB		 8976}
8977
9cce37f4
JB		 8978/* Disable the VGA plane that we never use */
8979static void i915_disable_vga(struct drm_device *dev)
8980{
8981 struct drm_i915_private *dev_priv = dev->dev_private;
8982 u8 sr1;
766aa1c4 8983 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 8984
8985 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 8986 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 8987 sr1 = inb(VGA_SR_DATA);
8988 outb(sr1 | 1<<5, VGA_SR_DATA);
8989 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8990 udelay(300);
8991
8992 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8993 POSTING_READ(vga_reg);
8994}
8995
f817586c
DV		 8996void intel_modeset_init_hw(struct drm_device *dev)
8997{
fa42e23c 8998 intel_init_power_well(dev);
0232e927 8999
a8f78b58
ED		 9000 intel_prepare_ddi(dev);
9001
f817586c
DV		 9002 intel_init_clock_gating(dev);
9003
79f5b2c7 9004 mutex_lock(&dev->struct_mutex);
8090c6b9 9005 intel_enable_gt_powersave(dev);
79f5b2c7 9006 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 9007}
9008
79e53945
JB		 9009void intel_modeset_init(struct drm_device *dev)
9010{
652c393a 9011 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 9012 int i, j, ret;
79e53945
JB		 9013
9014 drm_mode_config_init(dev);
9015
9016 dev->mode_config.min_width = 0;
9017 dev->mode_config.min_height = 0;
9018
019d96cb
DA		 9019 dev->mode_config.preferred_depth = 24;
9020 dev->mode_config.prefer_shadow = 1;
9021
e6ecefaa 9022 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 9023
b690e96c
JB		 9024 intel_init_quirks(dev);
9025
1fa61106
ED		 9026 intel_init_pm(dev);
9027
e3c74757
BW		 9028 if (INTEL_INFO(dev)->num_pipes == 0)
9029 return;
9030
e70236a8
JB		 9031 intel_init_display(dev);
9032
a6c45cf0
CW		 9033 if (IS_GEN2(dev)) {
9034 dev->mode_config.max_width = 2048;
9035 dev->mode_config.max_height = 2048;
9036 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9037 dev->mode_config.max_width = 4096;
9038 dev->mode_config.max_height = 4096;
79e53945 9039 } else {
a6c45cf0
CW		 9040 dev->mode_config.max_width = 8192;
9041 dev->mode_config.max_height = 8192;
79e53945 9042 }
5d4545ae 9043 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 9044
28c97730 9045 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 9046 INTEL_INFO(dev)->num_pipes,
9047 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 9048
7eb552ae 9049 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
79e53945 9050 intel_crtc_init(dev, i);
7f1f3851
JB		 9051 for (j = 0; j < dev_priv->num_plane; j++) {
9052 ret = intel_plane_init(dev, i, j);
9053 if (ret)
9054 DRM_DEBUG_KMS("pipe %d plane %d init failed: %d\n",
9055 i, j, ret);
9056 }
79e53945
JB		 9057 }
9058
79f689aa 9059 intel_cpu_pll_init(dev);
ee7b9f93
JB		 9060 intel_pch_pll_init(dev);
9061
9cce37f4
JB		 9062 /* Just disable it once at startup */
9063 i915_disable_vga(dev);
79e53945 9064 intel_setup_outputs(dev);
11be49eb
CW		 9065
9066 /* Just in case the BIOS is doing something questionable. */
9067 intel_disable_fbc(dev);
2c7111db
CW		 9068}
9069
24929352
DV		 9070static void
9071intel_connector_break_all_links(struct intel_connector *connector)
9072{
9073 connector->base.dpms = DRM_MODE_DPMS_OFF;
9074 connector->base.encoder = NULL;
9075 connector->encoder->connectors_active = false;
9076 connector->encoder->base.crtc = NULL;
9077}
9078
7fad798e
DV		 9079static void intel_enable_pipe_a(struct drm_device *dev)
9080{
9081 struct intel_connector *connector;
9082 struct drm_connector *crt = NULL;
9083 struct intel_load_detect_pipe load_detect_temp;
9084
9085 /* We can't just switch on the pipe A, we need to set things up with a
9086 * proper mode and output configuration. As a gross hack, enable pipe A
9087 * by enabling the load detect pipe once. */
9088 list_for_each_entry(connector,
9089 &dev->mode_config.connector_list,
9090 base.head) {
9091 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9092 crt = &connector->base;
9093 break;
9094 }
9095 }
9096
9097 if (!crt)
9098 return;
9099
9100 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9101 intel_release_load_detect_pipe(crt, &load_detect_temp);
9102
652c393a 9103
7fad798e
DV		 9104}
9105
fa555837
DV		 9106static bool
9107intel_check_plane_mapping(struct intel_crtc *crtc)
9108{
7eb552ae
BW		 9109 struct drm_device *dev = crtc->base.dev;
9110 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 9111 u32 reg, val;
9112
7eb552ae 9113 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 9114 return true;
9115
9116 reg = DSPCNTR(!crtc->plane);
9117 val = I915_READ(reg);
9118
9119 if ((val & DISPLAY_PLANE_ENABLE) &&
9120 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9121 return false;
9122
9123 return true;
9124}
9125
24929352
DV		 9126static void intel_sanitize_crtc(struct intel_crtc *crtc)
9127{
9128 struct drm_device *dev = crtc->base.dev;
9129 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 9130 u32 reg;
24929352 9131
24929352 9132 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 9133 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 9134 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9135
9136 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 9137 * disable the crtc (and hence change the state) if it is wrong. Note
9138 * that gen4+ has a fixed plane -> pipe mapping. */
9139 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 9140 struct intel_connector *connector;
9141 bool plane;
9142
24929352
DV		 9143 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9144 crtc->base.base.id);
9145
9146 /* Pipe has the wrong plane attached and the plane is active.
9147 * Temporarily change the plane mapping and disable everything
9148 * ... */
9149 plane = crtc->plane;
9150 crtc->plane = !plane;
9151 dev_priv->display.crtc_disable(&crtc->base);
9152 crtc->plane = plane;
9153
9154 /* ... and break all links. */
9155 list_for_each_entry(connector, &dev->mode_config.connector_list,
9156 base.head) {
9157 if (connector->encoder->base.crtc != &crtc->base)
9158 continue;
9159
9160 intel_connector_break_all_links(connector);
9161 }
9162
9163 WARN_ON(crtc->active);
9164 crtc->base.enabled = false;
9165 }
24929352 9166
7fad798e
DV		 9167 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9168 crtc->pipe == PIPE_A && !crtc->active) {
9169 /* BIOS forgot to enable pipe A, this mostly happens after
9170 * resume. Force-enable the pipe to fix this, the update_dpms
9171 * call below we restore the pipe to the right state, but leave
9172 * the required bits on. */
9173 intel_enable_pipe_a(dev);
9174 }
9175
24929352
DV		 9176 /* Adjust the state of the output pipe according to whether we
9177 * have active connectors/encoders. */
9178 intel_crtc_update_dpms(&crtc->base);
9179
9180 if (crtc->active != crtc->base.enabled) {
9181 struct intel_encoder *encoder;
9182
9183 /* This can happen either due to bugs in the get_hw_state
9184 * functions or because the pipe is force-enabled due to the
9185 * pipe A quirk. */
9186 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9187 crtc->base.base.id,
9188 crtc->base.enabled ? "enabled" : "disabled",
9189 crtc->active ? "enabled" : "disabled");
9190
9191 crtc->base.enabled = crtc->active;
9192
9193 /* Because we only establish the connector -> encoder ->
9194 * crtc links if something is active, this means the
9195 * crtc is now deactivated. Break the links. connector
9196 * -> encoder links are only establish when things are
9197 * actually up, hence no need to break them. */
9198 WARN_ON(crtc->active);
9199
9200 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9201 WARN_ON(encoder->connectors_active);
9202 encoder->base.crtc = NULL;
9203 }
9204 }
9205}
9206
9207static void intel_sanitize_encoder(struct intel_encoder *encoder)
9208{
9209 struct intel_connector *connector;
9210 struct drm_device *dev = encoder->base.dev;
9211
9212 /* We need to check both for a crtc link (meaning that the
9213 * encoder is active and trying to read from a pipe) and the
9214 * pipe itself being active. */
9215 bool has_active_crtc = encoder->base.crtc &&
9216 to_intel_crtc(encoder->base.crtc)->active;
9217
9218 if (encoder->connectors_active && !has_active_crtc) {
9219 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9220 encoder->base.base.id,
9221 drm_get_encoder_name(&encoder->base));
9222
9223 /* Connector is active, but has no active pipe. This is
9224 * fallout from our resume register restoring. Disable
9225 * the encoder manually again. */
9226 if (encoder->base.crtc) {
9227 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9228 encoder->base.base.id,
9229 drm_get_encoder_name(&encoder->base));
9230 encoder->disable(encoder);
9231 }
9232
9233 /* Inconsistent output/port/pipe state happens presumably due to
9234 * a bug in one of the get_hw_state functions. Or someplace else
9235 * in our code, like the register restore mess on resume. Clamp
9236 * things to off as a safer default. */
9237 list_for_each_entry(connector,
9238 &dev->mode_config.connector_list,
9239 base.head) {
9240 if (connector->encoder != encoder)
9241 continue;
9242
9243 intel_connector_break_all_links(connector);
9244 }
9245 }
9246 /* Enabled encoders without active connectors will be fixed in
9247 * the crtc fixup. */
9248}
9249
44cec740 9250void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9251{
9252 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9253 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9254
9255 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9256 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9257 i915_disable_vga(dev);
0fde901f
KM		 9258 }
9259}
9260
24929352
DV		 9261/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9262 * and i915 state tracking structures. */
45e2b5f6
DV		 9263void intel_modeset_setup_hw_state(struct drm_device *dev,
9264 bool force_restore)
24929352
DV		 9265{
9266 struct drm_i915_private *dev_priv = dev->dev_private;
9267 enum pipe pipe;
9268 u32 tmp;
b5644d05 9269 struct drm_plane *plane;
24929352
DV		 9270 struct intel_crtc *crtc;
9271 struct intel_encoder *encoder;
9272 struct intel_connector *connector;
9273
affa9354 9274 if (HAS_DDI(dev)) {
e28d54cb
PZ		 9275 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9276
9277 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9278 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9279 case TRANS_DDI_EDP_INPUT_A_ON:
9280 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9281 pipe = PIPE_A;
9282 break;
9283 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9284 pipe = PIPE_B;
9285 break;
9286 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9287 pipe = PIPE_C;
9288 break;
aaa148ec
DL		 9289 default:
9290 /* A bogus value has been programmed, disable
9291 * the transcoder */
9292 WARN(1, "Bogus eDP source %08x\n", tmp);
9293 intel_ddi_disable_transcoder_func(dev_priv,
9294 TRANSCODER_EDP);
9295 goto setup_pipes;
e28d54cb
PZ		 9296 }
9297
9298 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
3b117c8f 9299 crtc->config.cpu_transcoder = TRANSCODER_EDP;
e28d54cb
PZ		 9300
9301 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9302 pipe_name(pipe));
9303 }
9304 }
9305
aaa148ec 9306setup_pipes:
0e8ffe1b
DV		 9307 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9308 base.head) {
3b117c8f 9309 enum transcoder tmp = crtc->config.cpu_transcoder;
88adfff1 9310 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f
DV		 9311 crtc->config.cpu_transcoder = tmp;
9312
0e8ffe1b
DV		 9313 crtc->active = dev_priv->display.get_pipe_config(crtc,
9314 &crtc->config);
24929352
DV		 9315
9316 crtc->base.enabled = crtc->active;
9317
9318 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9319 crtc->base.base.id,
9320 crtc->active ? "enabled" : "disabled");
9321 }
9322
affa9354 9323 if (HAS_DDI(dev))
6441ab5f
PZ		 9324 intel_ddi_setup_hw_pll_state(dev);
9325
24929352
DV		 9326 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9327 base.head) {
9328 pipe = 0;
9329
9330 if (encoder->get_hw_state(encoder, &pipe)) {
9331 encoder->base.crtc =
9332 dev_priv->pipe_to_crtc_mapping[pipe];
9333 } else {
9334 encoder->base.crtc = NULL;
9335 }
9336
9337 encoder->connectors_active = false;
9338 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9339 encoder->base.base.id,
9340 drm_get_encoder_name(&encoder->base),
9341 encoder->base.crtc ? "enabled" : "disabled",
9342 pipe);
9343 }
9344
9345 list_for_each_entry(connector, &dev->mode_config.connector_list,
9346 base.head) {
9347 if (connector->get_hw_state(connector)) {
9348 connector->base.dpms = DRM_MODE_DPMS_ON;
9349 connector->encoder->connectors_active = true;
9350 connector->base.encoder = &connector->encoder->base;
9351 } else {
9352 connector->base.dpms = DRM_MODE_DPMS_OFF;
9353 connector->base.encoder = NULL;
9354 }
9355 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9356 connector->base.base.id,
9357 drm_get_connector_name(&connector->base),
9358 connector->base.encoder ? "enabled" : "disabled");
9359 }
9360
9361 /* HW state is read out, now we need to sanitize this mess. */
9362 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9363 base.head) {
9364 intel_sanitize_encoder(encoder);
9365 }
9366
9367 for_each_pipe(pipe) {
9368 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9369 intel_sanitize_crtc(crtc);
9370 }
9a935856 9371
45e2b5f6 9372 if (force_restore) {
f30da187
DV		 9373 /*
9374 * We need to use raw interfaces for restoring state to avoid
9375 * checking (bogus) intermediate states.
9376 */
45e2b5f6 9377 for_each_pipe(pipe) {
b5644d05
JB		 9378 struct drm_crtc *crtc =
9379 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 9380
9381 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9382 crtc->fb);
45e2b5f6 9383 }
b5644d05
JB		 9384 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9385 intel_plane_restore(plane);
0fde901f
KM		 9386
9387 i915_redisable_vga(dev);
45e2b5f6
DV		 9388 } else {
9389 intel_modeset_update_staged_output_state(dev);
9390 }
8af6cf88
DV		 9391
9392 intel_modeset_check_state(dev);
2e938892
DV		 9393
9394 drm_mode_config_reset(dev);
2c7111db
CW		 9395}
9396
9397void intel_modeset_gem_init(struct drm_device *dev)
9398{
1833b134 9399 intel_modeset_init_hw(dev);
02e792fb
DV		 9400
9401 intel_setup_overlay(dev);
24929352 9402
45e2b5f6 9403 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9404}
9405
9406void intel_modeset_cleanup(struct drm_device *dev)
9407{
652c393a
JB		 9408 struct drm_i915_private *dev_priv = dev->dev_private;
9409 struct drm_crtc *crtc;
9410 struct intel_crtc *intel_crtc;
9411
f87ea761 9412 drm_kms_helper_poll_fini(dev);
652c393a
JB		 9413 mutex_lock(&dev->struct_mutex);
9414
723bfd70
JB		 9415 intel_unregister_dsm_handler();
9416
9417
652c393a
JB		 9418 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9419 /* Skip inactive CRTCs */
9420 if (!crtc->fb)
9421 continue;
9422
9423 intel_crtc = to_intel_crtc(crtc);
3dec0095 9424 intel_increase_pllclock(crtc);
652c393a
JB		 9425 }
9426
973d04f9 9427 intel_disable_fbc(dev);
e70236a8 9428
8090c6b9 9429 intel_disable_gt_powersave(dev);
0cdab21f 9430
930ebb46
DV		 9431 ironlake_teardown_rc6(dev);
9432
57f350b6
JB		 9433 if (IS_VALLEYVIEW(dev))
9434 vlv_init_dpio(dev);
9435
69341a5e
KH		 9436 mutex_unlock(&dev->struct_mutex);
9437
6c0d9350
DV		 9438 /* Disable the irq before mode object teardown, for the irq might
9439 * enqueue unpin/hotplug work. */
9440 drm_irq_uninstall(dev);
9441 cancel_work_sync(&dev_priv->hotplug_work);
c6a828d3 9442 cancel_work_sync(&dev_priv->rps.work);
6c0d9350 9443
1630fe75
CW		 9444 /* flush any delayed tasks or pending work */
9445 flush_scheduled_work();
9446
dc652f90
JN		 9447 /* destroy backlight, if any, before the connectors */
9448 intel_panel_destroy_backlight(dev);
9449
79e53945 9450 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9451
9452 intel_cleanup_overlay(dev);
79e53945
JB		 9453}
9454
f1c79df3
ZW		 9455/*
9456 * Return which encoder is currently attached for connector.
9457 */
df0e9248 9458struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9459{
df0e9248
CW		 9460 return &intel_attached_encoder(connector)->base;
9461}
f1c79df3 9462
df0e9248
CW		 9463void intel_connector_attach_encoder(struct intel_connector *connector,
9464 struct intel_encoder *encoder)
9465{
9466 connector->encoder = encoder;
9467 drm_mode_connector_attach_encoder(&connector->base,
9468 &encoder->base);
79e53945 9469}
28d52043
DA		 9470
9471/*
9472 * set vga decode state - true == enable VGA decode
9473 */
9474int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9475{
9476 struct drm_i915_private *dev_priv = dev->dev_private;
9477 u16 gmch_ctrl;
9478
9479 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9480 if (state)
9481 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9482 else
9483 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9484 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9485 return 0;
9486}
c4a1d9e4
CW		 9487
9488#ifdef CONFIG_DEBUG_FS
9489#include <linux/seq_file.h>
9490
9491struct intel_display_error_state {
9492 struct intel_cursor_error_state {
9493 u32 control;
9494 u32 position;
9495 u32 base;
9496 u32 size;
52331309 9497 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9498
9499 struct intel_pipe_error_state {
9500 u32 conf;
9501 u32 source;
9502
9503 u32 htotal;
9504 u32 hblank;
9505 u32 hsync;
9506 u32 vtotal;
9507 u32 vblank;
9508 u32 vsync;
52331309 9509 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9510
9511 struct intel_plane_error_state {
9512 u32 control;
9513 u32 stride;
9514 u32 size;
9515 u32 pos;
9516 u32 addr;
9517 u32 surface;
9518 u32 tile_offset;
52331309 9519 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9520};
9521
9522struct intel_display_error_state *
9523intel_display_capture_error_state(struct drm_device *dev)
9524{
0206e353 9525 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9526 struct intel_display_error_state *error;
702e7a56 9527 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9528 int i;
9529
9530 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9531 if (error == NULL)
9532 return NULL;
9533
52331309 9534 for_each_pipe(i) {
702e7a56
PZ		 9535 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9536
a18c4c3d
PZ		 9537 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9538 error->cursor[i].control = I915_READ(CURCNTR(i));
9539 error->cursor[i].position = I915_READ(CURPOS(i));
9540 error->cursor[i].base = I915_READ(CURBASE(i));
9541 } else {
9542 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9543 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9544 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9545 }
c4a1d9e4
CW		 9546
9547 error->plane[i].control = I915_READ(DSPCNTR(i));
9548 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 9549 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9550 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 9551 error->plane[i].pos = I915_READ(DSPPOS(i));
9552 }
ca291363
PZ		 9553 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9554 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 9555 if (INTEL_INFO(dev)->gen >= 4) {
9556 error->plane[i].surface = I915_READ(DSPSURF(i));
9557 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9558 }
9559
702e7a56 9560 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9561 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9562 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9563 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9564 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9565 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9566 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9567 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9568 }
9569
9570 return error;
9571}
9572
9573void
9574intel_display_print_error_state(struct seq_file *m,
9575 struct drm_device *dev,
9576 struct intel_display_error_state *error)
9577{
9578 int i;
9579
7eb552ae 9580 seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
52331309 9581 for_each_pipe(i) {
c4a1d9e4
CW		 9582 seq_printf(m, "Pipe [%d]:\n", i);
9583 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9584 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9585 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9586 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9587 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9588 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9589 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9590 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9591
9592 seq_printf(m, "Plane [%d]:\n", i);
9593 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9594 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 9595 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9596 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
80ca378b
PZ		 9597 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9598 }
4b71a570 9599 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
ca291363 9600 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4
CW		 9601 if (INTEL_INFO(dev)->gen >= 4) {
9602 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9603 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9604 }
9605
9606 seq_printf(m, "Cursor [%d]:\n", i);
9607 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9608 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9609 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9610 }
9611}
9612#endif
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