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drm/i915: get mode clock when reading the pipe config v9
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
f1f644dc
JB		 48static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
49 struct intel_crtc_config *pipe_config);
50static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
51 struct intel_crtc_config *pipe_config);
52
79e53945 53typedef struct {
0206e353 54 int min, max;
79e53945
JB		 55} intel_range_t;
56
57typedef struct {
0206e353
AJ		 58 int dot_limit;
59 int p2_slow, p2_fast;
79e53945
JB		 60} intel_p2_t;
61
62#define INTEL_P2_NUM 2
d4906093
ML		 63typedef struct intel_limit intel_limit_t;
64struct intel_limit {
0206e353
AJ		 65 intel_range_t dot, vco, n, m, m1, m2, p, p1;
66 intel_p2_t p2;
d4906093 67};
79e53945 68
2377b741
JB		 69/* FDI */
70#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
71
d2acd215
DV		 72int
73intel_pch_rawclk(struct drm_device *dev)
74{
75 struct drm_i915_private *dev_priv = dev->dev_private;
76
77 WARN_ON(!HAS_PCH_SPLIT(dev));
78
79 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
80}
81
021357ac
CW		 82static inline u32 /* units of 100MHz */
83intel_fdi_link_freq(struct drm_device *dev)
84{
8b99e68c
CW		 85 if (IS_GEN5(dev)) {
86 struct drm_i915_private *dev_priv = dev->dev_private;
87 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
88 } else
89 return 27;
021357ac
CW		 90}
91
e4b36699 92static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 93 .dot = { .min = 25000, .max = 350000 },
94 .vco = { .min = 930000, .max = 1400000 },
95 .n = { .min = 3, .max = 16 },
96 .m = { .min = 96, .max = 140 },
97 .m1 = { .min = 18, .max = 26 },
98 .m2 = { .min = 6, .max = 16 },
99 .p = { .min = 4, .max = 128 },
100 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 101 .p2 = { .dot_limit = 165000,
102 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 103};
104
105static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 106 .dot = { .min = 25000, .max = 350000 },
107 .vco = { .min = 930000, .max = 1400000 },
108 .n = { .min = 3, .max = 16 },
109 .m = { .min = 96, .max = 140 },
110 .m1 = { .min = 18, .max = 26 },
111 .m2 = { .min = 6, .max = 16 },
112 .p = { .min = 4, .max = 128 },
113 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 114 .p2 = { .dot_limit = 165000,
115 .p2_slow = 14, .p2_fast = 7 },
e4b36699 116};
273e27ca 117
e4b36699 118static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 119 .dot = { .min = 20000, .max = 400000 },
120 .vco = { .min = 1400000, .max = 2800000 },
121 .n = { .min = 1, .max = 6 },
122 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 123 .m1 = { .min = 8, .max = 18 },
124 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 125 .p = { .min = 5, .max = 80 },
126 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 127 .p2 = { .dot_limit = 200000,
128 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 129};
130
131static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 132 .dot = { .min = 20000, .max = 400000 },
133 .vco = { .min = 1400000, .max = 2800000 },
134 .n = { .min = 1, .max = 6 },
135 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 136 .m1 = { .min = 8, .max = 18 },
137 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 138 .p = { .min = 7, .max = 98 },
139 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 140 .p2 = { .dot_limit = 112000,
141 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 142};
143
273e27ca 144
e4b36699 145static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 146 .dot = { .min = 25000, .max = 270000 },
147 .vco = { .min = 1750000, .max = 3500000},
148 .n = { .min = 1, .max = 4 },
149 .m = { .min = 104, .max = 138 },
150 .m1 = { .min = 17, .max = 23 },
151 .m2 = { .min = 5, .max = 11 },
152 .p = { .min = 10, .max = 30 },
153 .p1 = { .min = 1, .max = 3},
154 .p2 = { .dot_limit = 270000,
155 .p2_slow = 10,
156 .p2_fast = 10
044c7c41 157 },
e4b36699
KP		 158};
159
160static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 161 .dot = { .min = 22000, .max = 400000 },
162 .vco = { .min = 1750000, .max = 3500000},
163 .n = { .min = 1, .max = 4 },
164 .m = { .min = 104, .max = 138 },
165 .m1 = { .min = 16, .max = 23 },
166 .m2 = { .min = 5, .max = 11 },
167 .p = { .min = 5, .max = 80 },
168 .p1 = { .min = 1, .max = 8},
169 .p2 = { .dot_limit = 165000,
170 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 171};
172
173static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 174 .dot = { .min = 20000, .max = 115000 },
175 .vco = { .min = 1750000, .max = 3500000 },
176 .n = { .min = 1, .max = 3 },
177 .m = { .min = 104, .max = 138 },
178 .m1 = { .min = 17, .max = 23 },
179 .m2 = { .min = 5, .max = 11 },
180 .p = { .min = 28, .max = 112 },
181 .p1 = { .min = 2, .max = 8 },
182 .p2 = { .dot_limit = 0,
183 .p2_slow = 14, .p2_fast = 14
044c7c41 184 },
e4b36699
KP		 185};
186
187static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 188 .dot = { .min = 80000, .max = 224000 },
189 .vco = { .min = 1750000, .max = 3500000 },
190 .n = { .min = 1, .max = 3 },
191 .m = { .min = 104, .max = 138 },
192 .m1 = { .min = 17, .max = 23 },
193 .m2 = { .min = 5, .max = 11 },
194 .p = { .min = 14, .max = 42 },
195 .p1 = { .min = 2, .max = 6 },
196 .p2 = { .dot_limit = 0,
197 .p2_slow = 7, .p2_fast = 7
044c7c41 198 },
e4b36699
KP		 199};
200
f2b115e6 201static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 202 .dot = { .min = 20000, .max = 400000},
203 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 204 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 205 .n = { .min = 3, .max = 6 },
206 .m = { .min = 2, .max = 256 },
273e27ca 207 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 208 .m1 = { .min = 0, .max = 0 },
209 .m2 = { .min = 0, .max = 254 },
210 .p = { .min = 5, .max = 80 },
211 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 212 .p2 = { .dot_limit = 200000,
213 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 214};
215
f2b115e6 216static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 217 .dot = { .min = 20000, .max = 400000 },
218 .vco = { .min = 1700000, .max = 3500000 },
219 .n = { .min = 3, .max = 6 },
220 .m = { .min = 2, .max = 256 },
221 .m1 = { .min = 0, .max = 0 },
222 .m2 = { .min = 0, .max = 254 },
223 .p = { .min = 7, .max = 112 },
224 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 225 .p2 = { .dot_limit = 112000,
226 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 227};
228
273e27ca
EA		 229/* Ironlake / Sandybridge
230 *
231 * We calculate clock using (register_value + 2) for N/M1/M2, so here
232 * the range value for them is (actual_value - 2).
233 */
b91ad0ec 234static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 235 .dot = { .min = 25000, .max = 350000 },
236 .vco = { .min = 1760000, .max = 3510000 },
237 .n = { .min = 1, .max = 5 },
238 .m = { .min = 79, .max = 127 },
239 .m1 = { .min = 12, .max = 22 },
240 .m2 = { .min = 5, .max = 9 },
241 .p = { .min = 5, .max = 80 },
242 .p1 = { .min = 1, .max = 8 },
243 .p2 = { .dot_limit = 225000,
244 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 245};
246
b91ad0ec 247static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 248 .dot = { .min = 25000, .max = 350000 },
249 .vco = { .min = 1760000, .max = 3510000 },
250 .n = { .min = 1, .max = 3 },
251 .m = { .min = 79, .max = 118 },
252 .m1 = { .min = 12, .max = 22 },
253 .m2 = { .min = 5, .max = 9 },
254 .p = { .min = 28, .max = 112 },
255 .p1 = { .min = 2, .max = 8 },
256 .p2 = { .dot_limit = 225000,
257 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 258};
259
260static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 261 .dot = { .min = 25000, .max = 350000 },
262 .vco = { .min = 1760000, .max = 3510000 },
263 .n = { .min = 1, .max = 3 },
264 .m = { .min = 79, .max = 127 },
265 .m1 = { .min = 12, .max = 22 },
266 .m2 = { .min = 5, .max = 9 },
267 .p = { .min = 14, .max = 56 },
268 .p1 = { .min = 2, .max = 8 },
269 .p2 = { .dot_limit = 225000,
270 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 271};
272
273e27ca 273/* LVDS 100mhz refclk limits. */
b91ad0ec 274static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 275 .dot = { .min = 25000, .max = 350000 },
276 .vco = { .min = 1760000, .max = 3510000 },
277 .n = { .min = 1, .max = 2 },
278 .m = { .min = 79, .max = 126 },
279 .m1 = { .min = 12, .max = 22 },
280 .m2 = { .min = 5, .max = 9 },
281 .p = { .min = 28, .max = 112 },
0206e353 282 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 283 .p2 = { .dot_limit = 225000,
284 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 285};
286
287static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 288 .dot = { .min = 25000, .max = 350000 },
289 .vco = { .min = 1760000, .max = 3510000 },
290 .n = { .min = 1, .max = 3 },
291 .m = { .min = 79, .max = 126 },
292 .m1 = { .min = 12, .max = 22 },
293 .m2 = { .min = 5, .max = 9 },
294 .p = { .min = 14, .max = 42 },
0206e353 295 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 296 .p2 = { .dot_limit = 225000,
297 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 298};
299
a0c4da24
JB		 300static const intel_limit_t intel_limits_vlv_dac = {
301 .dot = { .min = 25000, .max = 270000 },
302 .vco = { .min = 4000000, .max = 6000000 },
303 .n = { .min = 1, .max = 7 },
304 .m = { .min = 22, .max = 450 }, /* guess */
305 .m1 = { .min = 2, .max = 3 },
306 .m2 = { .min = 11, .max = 156 },
307 .p = { .min = 10, .max = 30 },
75e53986 308 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 309 .p2 = { .dot_limit = 270000,
310 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 311};
312
313static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 314 .dot = { .min = 25000, .max = 270000 },
315 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 316 .n = { .min = 1, .max = 7 },
317 .m = { .min = 60, .max = 300 }, /* guess */
318 .m1 = { .min = 2, .max = 3 },
319 .m2 = { .min = 11, .max = 156 },
320 .p = { .min = 10, .max = 30 },
321 .p1 = { .min = 2, .max = 3 },
322 .p2 = { .dot_limit = 270000,
323 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 324};
325
326static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 327 .dot = { .min = 25000, .max = 270000 },
328 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 329 .n = { .min = 1, .max = 7 },
74a4dd2e 330 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 331 .m1 = { .min = 2, .max = 3 },
332 .m2 = { .min = 11, .max = 156 },
333 .p = { .min = 10, .max = 30 },
75e53986 334 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 335 .p2 = { .dot_limit = 270000,
336 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 337};
338
1b894b59
CW		 339static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
340 int refclk)
2c07245f 341{
b91ad0ec 342 struct drm_device *dev = crtc->dev;
2c07245f 343 const intel_limit_t *limit;
b91ad0ec
ZW		 344
345 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 346 if (intel_is_dual_link_lvds(dev)) {
1b894b59 347 if (refclk == 100000)
b91ad0ec
ZW		 348 limit = &intel_limits_ironlake_dual_lvds_100m;
349 else
350 limit = &intel_limits_ironlake_dual_lvds;
351 } else {
1b894b59 352 if (refclk == 100000)
b91ad0ec
ZW		 353 limit = &intel_limits_ironlake_single_lvds_100m;
354 else
355 limit = &intel_limits_ironlake_single_lvds;
356 }
c6bb3538 357 } else
b91ad0ec 358 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 359
360 return limit;
361}
362
044c7c41
ML		 363static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
364{
365 struct drm_device *dev = crtc->dev;
044c7c41
ML		 366 const intel_limit_t *limit;
367
368 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 369 if (intel_is_dual_link_lvds(dev))
e4b36699 370 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 371 else
e4b36699 372 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 373 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
374 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 375 limit = &intel_limits_g4x_hdmi;
044c7c41 376 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 377 limit = &intel_limits_g4x_sdvo;
044c7c41 378 } else /* The option is for other outputs */
e4b36699 379 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 380
381 return limit;
382}
383
1b894b59 384static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 385{
386 struct drm_device *dev = crtc->dev;
387 const intel_limit_t *limit;
388
bad720ff 389 if (HAS_PCH_SPLIT(dev))
1b894b59 390 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 391 else if (IS_G4X(dev)) {
044c7c41 392 limit = intel_g4x_limit(crtc);
f2b115e6 393 } else if (IS_PINEVIEW(dev)) {
2177832f 394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 395 limit = &intel_limits_pineview_lvds;
2177832f 396 else
f2b115e6 397 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 398 } else if (IS_VALLEYVIEW(dev)) {
399 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
400 limit = &intel_limits_vlv_dac;
401 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
402 limit = &intel_limits_vlv_hdmi;
403 else
404 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 405 } else if (!IS_GEN2(dev)) {
406 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
407 limit = &intel_limits_i9xx_lvds;
408 else
409 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 410 } else {
411 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 412 limit = &intel_limits_i8xx_lvds;
79e53945 413 else
e4b36699 414 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 415 }
416 return limit;
417}
418
f2b115e6
AJ		 419/* m1 is reserved as 0 in Pineview, n is a ring counter */
420static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 421{
2177832f
SL		 422 clock->m = clock->m2 + 2;
423 clock->p = clock->p1 * clock->p2;
424 clock->vco = refclk * clock->m / clock->n;
425 clock->dot = clock->vco / clock->p;
426}
427
7429e9d4
DV		 428static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
429{
430 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
431}
432
ac58c3f0 433static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 434{
7429e9d4 435 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 436 clock->p = clock->p1 * clock->p2;
437 clock->vco = refclk * clock->m / (clock->n + 2);
438 clock->dot = clock->vco / clock->p;
439}
440
79e53945
JB		 441/**
442 * Returns whether any output on the specified pipe is of the specified type
443 */
4ef69c7a 444bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 445{
4ef69c7a 446 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 447 struct intel_encoder *encoder;
448
6c2b7c12
DV		 449 for_each_encoder_on_crtc(dev, crtc, encoder)
450 if (encoder->type == type)
4ef69c7a
CW		 451 return true;
452
453 return false;
79e53945
JB		 454}
455
7c04d1d9 456#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 457/**
458 * Returns whether the given set of divisors are valid for a given refclk with
459 * the given connectors.
460 */
461
1b894b59
CW		 462static bool intel_PLL_is_valid(struct drm_device *dev,
463 const intel_limit_t *limit,
464 const intel_clock_t *clock)
79e53945 465{
79e53945 466 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 467 INTELPllInvalid("p1 out of range\n");
79e53945 468 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 469 INTELPllInvalid("p out of range\n");
79e53945 470 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 471 INTELPllInvalid("m2 out of range\n");
79e53945 472 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 473 INTELPllInvalid("m1 out of range\n");
f2b115e6 474 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 475 INTELPllInvalid("m1 <= m2\n");
79e53945 476 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 477 INTELPllInvalid("m out of range\n");
79e53945 478 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 479 INTELPllInvalid("n out of range\n");
79e53945 480 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 481 INTELPllInvalid("vco out of range\n");
79e53945
JB		 482 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
483 * connector, etc., rather than just a single range.
484 */
485 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 486 INTELPllInvalid("dot out of range\n");
79e53945
JB		 487
488 return true;
489}
490
d4906093 491static bool
ee9300bb 492i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 493 int target, int refclk, intel_clock_t *match_clock,
494 intel_clock_t *best_clock)
79e53945
JB		 495{
496 struct drm_device *dev = crtc->dev;
79e53945 497 intel_clock_t clock;
79e53945
JB		 498 int err = target;
499
a210b028 500 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 501 /*
a210b028
DV		 502 * For LVDS just rely on its current settings for dual-channel.
503 * We haven't figured out how to reliably set up different
504 * single/dual channel state, if we even can.
79e53945 505 */
1974cad0 506 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 507 clock.p2 = limit->p2.p2_fast;
508 else
509 clock.p2 = limit->p2.p2_slow;
510 } else {
511 if (target < limit->p2.dot_limit)
512 clock.p2 = limit->p2.p2_slow;
513 else
514 clock.p2 = limit->p2.p2_fast;
515 }
516
0206e353 517 memset(best_clock, 0, sizeof(*best_clock));
79e53945 518
42158660
ZY		 519 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
520 clock.m1++) {
521 for (clock.m2 = limit->m2.min;
522 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 523 if (clock.m2 >= clock.m1)
42158660
ZY		 524 break;
525 for (clock.n = limit->n.min;
526 clock.n <= limit->n.max; clock.n++) {
527 for (clock.p1 = limit->p1.min;
528 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 529 int this_err;
530
ac58c3f0
DV		 531 i9xx_clock(refclk, &clock);
532 if (!intel_PLL_is_valid(dev, limit,
533 &clock))
534 continue;
535 if (match_clock &&
536 clock.p != match_clock->p)
537 continue;
538
539 this_err = abs(clock.dot - target);
540 if (this_err < err) {
541 *best_clock = clock;
542 err = this_err;
543 }
544 }
545 }
546 }
547 }
548
549 return (err != target);
550}
551
552static bool
ee9300bb
DV		 553pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
554 int target, int refclk, intel_clock_t *match_clock,
555 intel_clock_t *best_clock)
79e53945
JB		 556{
557 struct drm_device *dev = crtc->dev;
79e53945 558 intel_clock_t clock;
79e53945
JB		 559 int err = target;
560
a210b028 561 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 562 /*
a210b028
DV		 563 * For LVDS just rely on its current settings for dual-channel.
564 * We haven't figured out how to reliably set up different
565 * single/dual channel state, if we even can.
79e53945 566 */
1974cad0 567 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 568 clock.p2 = limit->p2.p2_fast;
569 else
570 clock.p2 = limit->p2.p2_slow;
571 } else {
572 if (target < limit->p2.dot_limit)
573 clock.p2 = limit->p2.p2_slow;
574 else
575 clock.p2 = limit->p2.p2_fast;
576 }
577
0206e353 578 memset(best_clock, 0, sizeof(*best_clock));
79e53945 579
42158660
ZY		 580 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
581 clock.m1++) {
582 for (clock.m2 = limit->m2.min;
583 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 584 for (clock.n = limit->n.min;
585 clock.n <= limit->n.max; clock.n++) {
586 for (clock.p1 = limit->p1.min;
587 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 588 int this_err;
589
ac58c3f0 590 pineview_clock(refclk, &clock);
1b894b59
CW		 591 if (!intel_PLL_is_valid(dev, limit,
592 &clock))
79e53945 593 continue;
cec2f356
SP		 594 if (match_clock &&
595 clock.p != match_clock->p)
596 continue;
79e53945
JB		 597
598 this_err = abs(clock.dot - target);
599 if (this_err < err) {
600 *best_clock = clock;
601 err = this_err;
602 }
603 }
604 }
605 }
606 }
607
608 return (err != target);
609}
610
d4906093 611static bool
ee9300bb
DV		 612g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
613 int target, int refclk, intel_clock_t *match_clock,
614 intel_clock_t *best_clock)
d4906093
ML		 615{
616 struct drm_device *dev = crtc->dev;
d4906093
ML		 617 intel_clock_t clock;
618 int max_n;
619 bool found;
6ba770dc
AJ		 620 /* approximately equals target * 0.00585 */
621 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 622 found = false;
623
624 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 625 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 626 clock.p2 = limit->p2.p2_fast;
627 else
628 clock.p2 = limit->p2.p2_slow;
629 } else {
630 if (target < limit->p2.dot_limit)
631 clock.p2 = limit->p2.p2_slow;
632 else
633 clock.p2 = limit->p2.p2_fast;
634 }
635
636 memset(best_clock, 0, sizeof(*best_clock));
637 max_n = limit->n.max;
f77f13e2 638 /* based on hardware requirement, prefer smaller n to precision */
d4906093 639 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 640 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 641 for (clock.m1 = limit->m1.max;
642 clock.m1 >= limit->m1.min; clock.m1--) {
643 for (clock.m2 = limit->m2.max;
644 clock.m2 >= limit->m2.min; clock.m2--) {
645 for (clock.p1 = limit->p1.max;
646 clock.p1 >= limit->p1.min; clock.p1--) {
647 int this_err;
648
ac58c3f0 649 i9xx_clock(refclk, &clock);
1b894b59
CW		 650 if (!intel_PLL_is_valid(dev, limit,
651 &clock))
d4906093 652 continue;
1b894b59
CW		 653
654 this_err = abs(clock.dot - target);
d4906093
ML		 655 if (this_err < err_most) {
656 *best_clock = clock;
657 err_most = this_err;
658 max_n = clock.n;
659 found = true;
660 }
661 }
662 }
663 }
664 }
2c07245f
ZW		 665 return found;
666}
667
a0c4da24 668static bool
ee9300bb
DV		 669vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
670 int target, int refclk, intel_clock_t *match_clock,
671 intel_clock_t *best_clock)
a0c4da24
JB		 672{
673 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
674 u32 m, n, fastclk;
675 u32 updrate, minupdate, fracbits, p;
676 unsigned long bestppm, ppm, absppm;
677 int dotclk, flag;
678
af447bd3 679 flag = 0;
a0c4da24
JB		 680 dotclk = target * 1000;
681 bestppm = 1000000;
682 ppm = absppm = 0;
683 fastclk = dotclk / (2*100);
684 updrate = 0;
685 minupdate = 19200;
686 fracbits = 1;
687 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
688 bestm1 = bestm2 = bestp1 = bestp2 = 0;
689
690 /* based on hardware requirement, prefer smaller n to precision */
691 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
692 updrate = refclk / n;
693 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
694 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
695 if (p2 > 10)
696 p2 = p2 - 1;
697 p = p1 * p2;
698 /* based on hardware requirement, prefer bigger m1,m2 values */
699 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
700 m2 = (((2*(fastclk * p * n / m1 )) +
701 refclk) / (2*refclk));
702 m = m1 * m2;
703 vco = updrate * m;
704 if (vco >= limit->vco.min && vco < limit->vco.max) {
705 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
706 absppm = (ppm > 0) ? ppm : (-ppm);
707 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
708 bestppm = 0;
709 flag = 1;
710 }
711 if (absppm < bestppm - 10) {
712 bestppm = absppm;
713 flag = 1;
714 }
715 if (flag) {
716 bestn = n;
717 bestm1 = m1;
718 bestm2 = m2;
719 bestp1 = p1;
720 bestp2 = p2;
721 flag = 0;
722 }
723 }
724 }
725 }
726 }
727 }
728 best_clock->n = bestn;
729 best_clock->m1 = bestm1;
730 best_clock->m2 = bestm2;
731 best_clock->p1 = bestp1;
732 best_clock->p2 = bestp2;
733
734 return true;
735}
a4fc5ed6 736
a5c961d1
PZ		 737enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
738 enum pipe pipe)
739{
740 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
741 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
742
3b117c8f 743 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 744}
745
a928d536
PZ		 746static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
747{
748 struct drm_i915_private *dev_priv = dev->dev_private;
749 u32 frame, frame_reg = PIPEFRAME(pipe);
750
751 frame = I915_READ(frame_reg);
752
753 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
754 DRM_DEBUG_KMS("vblank wait timed out\n");
755}
756
9d0498a2
JB		 757/**
758 * intel_wait_for_vblank - wait for vblank on a given pipe
759 * @dev: drm device
760 * @pipe: pipe to wait for
761 *
762 * Wait for vblank to occur on a given pipe. Needed for various bits of
763 * mode setting code.
764 */
765void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 766{
9d0498a2 767 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 768 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 769
a928d536
PZ		 770 if (INTEL_INFO(dev)->gen >= 5) {
771 ironlake_wait_for_vblank(dev, pipe);
772 return;
773 }
774
300387c0
CW		 775 /* Clear existing vblank status. Note this will clear any other
776 * sticky status fields as well.
777 *
778 * This races with i915_driver_irq_handler() with the result
779 * that either function could miss a vblank event. Here it is not
780 * fatal, as we will either wait upon the next vblank interrupt or
781 * timeout. Generally speaking intel_wait_for_vblank() is only
782 * called during modeset at which time the GPU should be idle and
783 * should *not* be performing page flips and thus not waiting on
784 * vblanks...
785 * Currently, the result of us stealing a vblank from the irq
786 * handler is that a single frame will be skipped during swapbuffers.
787 */
788 I915_WRITE(pipestat_reg,
789 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
790
9d0498a2 791 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 792 if (wait_for(I915_READ(pipestat_reg) &
793 PIPE_VBLANK_INTERRUPT_STATUS,
794 50))
9d0498a2
JB		 795 DRM_DEBUG_KMS("vblank wait timed out\n");
796}
797
ab7ad7f6
KP		 798/*
799 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 800 * @dev: drm device
801 * @pipe: pipe to wait for
802 *
803 * After disabling a pipe, we can't wait for vblank in the usual way,
804 * spinning on the vblank interrupt status bit, since we won't actually
805 * see an interrupt when the pipe is disabled.
806 *
ab7ad7f6
KP		 807 * On Gen4 and above:
808 * wait for the pipe register state bit to turn off
809 *
810 * Otherwise:
811 * wait for the display line value to settle (it usually
812 * ends up stopping at the start of the next frame).
58e10eb9 813 *
9d0498a2 814 */
58e10eb9 815void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 816{
817 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 818 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
819 pipe);
ab7ad7f6
KP		 820
821 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 822 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 823
824 /* Wait for the Pipe State to go off */
58e10eb9
CW		 825 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
826 100))
284637d9 827 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 828 } else {
837ba00f 829 u32 last_line, line_mask;
58e10eb9 830 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 831 unsigned long timeout = jiffies + msecs_to_jiffies(100);
832
837ba00f
PZ		 833 if (IS_GEN2(dev))
834 line_mask = DSL_LINEMASK_GEN2;
835 else
836 line_mask = DSL_LINEMASK_GEN3;
837
ab7ad7f6
KP		 838 /* Wait for the display line to settle */
839 do {
837ba00f 840 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 841 mdelay(5);
837ba00f 842 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 843 time_after(timeout, jiffies));
844 if (time_after(jiffies, timeout))
284637d9 845 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 846 }
79e53945
JB		 847}
848
b0ea7d37
DL		 849/*
850 * ibx_digital_port_connected - is the specified port connected?
851 * @dev_priv: i915 private structure
852 * @port: the port to test
853 *
854 * Returns true if @port is connected, false otherwise.
855 */
856bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
857 struct intel_digital_port *port)
858{
859 u32 bit;
860
c36346e3
DL		 861 if (HAS_PCH_IBX(dev_priv->dev)) {
862 switch(port->port) {
863 case PORT_B:
864 bit = SDE_PORTB_HOTPLUG;
865 break;
866 case PORT_C:
867 bit = SDE_PORTC_HOTPLUG;
868 break;
869 case PORT_D:
870 bit = SDE_PORTD_HOTPLUG;
871 break;
872 default:
873 return true;
874 }
875 } else {
876 switch(port->port) {
877 case PORT_B:
878 bit = SDE_PORTB_HOTPLUG_CPT;
879 break;
880 case PORT_C:
881 bit = SDE_PORTC_HOTPLUG_CPT;
882 break;
883 case PORT_D:
884 bit = SDE_PORTD_HOTPLUG_CPT;
885 break;
886 default:
887 return true;
888 }
b0ea7d37
DL		 889 }
890
891 return I915_READ(SDEISR) & bit;
892}
893
b24e7179
JB		 894static const char *state_string(bool enabled)
895{
896 return enabled ? "on" : "off";
897}
898
899/* Only for pre-ILK configs */
55607e8a
DV		 900void assert_pll(struct drm_i915_private *dev_priv,
901 enum pipe pipe, bool state)
b24e7179
JB		 902{
903 int reg;
904 u32 val;
905 bool cur_state;
906
907 reg = DPLL(pipe);
908 val = I915_READ(reg);
909 cur_state = !!(val & DPLL_VCO_ENABLE);
910 WARN(cur_state != state,
911 "PLL state assertion failure (expected %s, current %s)\n",
912 state_string(state), state_string(cur_state));
913}
b24e7179 914
55607e8a 915struct intel_shared_dpll *
e2b78267
DV		 916intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
917{
918 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
919
a43f6e0f 920 if (crtc->config.shared_dpll < 0)
e2b78267
DV		 921 return NULL;
922
a43f6e0f 923 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
e2b78267
DV		 924}
925
040484af 926/* For ILK+ */
55607e8a
DV		 927void assert_shared_dpll(struct drm_i915_private *dev_priv,
928 struct intel_shared_dpll *pll,
929 bool state)
040484af 930{
040484af 931 bool cur_state;
5358901f 932 struct intel_dpll_hw_state hw_state;
040484af 933
9d82aa17
ED		 934 if (HAS_PCH_LPT(dev_priv->dev)) {
935 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
936 return;
937 }
938
92b27b08 939 if (WARN (!pll,
46edb027 940 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 941 return;
ee7b9f93 942
5358901f 943 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
92b27b08 944 WARN(cur_state != state,
5358901f
DV		 945 "%s assertion failure (expected %s, current %s)\n",
946 pll->name, state_string(state), state_string(cur_state));
040484af 947}
040484af
JB		 948
949static void assert_fdi_tx(struct drm_i915_private *dev_priv,
950 enum pipe pipe, bool state)
951{
952 int reg;
953 u32 val;
954 bool cur_state;
ad80a810
PZ		 955 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
956 pipe);
040484af 957
affa9354
PZ		 958 if (HAS_DDI(dev_priv->dev)) {
959 /* DDI does not have a specific FDI_TX register */
ad80a810 960 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 961 val = I915_READ(reg);
ad80a810 962 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 963 } else {
964 reg = FDI_TX_CTL(pipe);
965 val = I915_READ(reg);
966 cur_state = !!(val & FDI_TX_ENABLE);
967 }
040484af
JB		 968 WARN(cur_state != state,
969 "FDI TX state assertion failure (expected %s, current %s)\n",
970 state_string(state), state_string(cur_state));
971}
972#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
973#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
974
975static void assert_fdi_rx(struct drm_i915_private *dev_priv,
976 enum pipe pipe, bool state)
977{
978 int reg;
979 u32 val;
980 bool cur_state;
981
d63fa0dc
PZ		 982 reg = FDI_RX_CTL(pipe);
983 val = I915_READ(reg);
984 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 985 WARN(cur_state != state,
986 "FDI RX state assertion failure (expected %s, current %s)\n",
987 state_string(state), state_string(cur_state));
988}
989#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
990#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
991
992static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
993 enum pipe pipe)
994{
995 int reg;
996 u32 val;
997
998 /* ILK FDI PLL is always enabled */
999 if (dev_priv->info->gen == 5)
1000 return;
1001
bf507ef7 1002 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1003 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1004 return;
1005
040484af
JB		 1006 reg = FDI_TX_CTL(pipe);
1007 val = I915_READ(reg);
1008 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1009}
1010
55607e8a
DV		 1011void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1012 enum pipe pipe, bool state)
040484af
JB		 1013{
1014 int reg;
1015 u32 val;
55607e8a 1016 bool cur_state;
040484af
JB		 1017
1018 reg = FDI_RX_CTL(pipe);
1019 val = I915_READ(reg);
55607e8a
DV		 1020 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1021 WARN(cur_state != state,
1022 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1023 state_string(state), state_string(cur_state));
040484af
JB		 1024}
1025
ea0760cf
JB		 1026static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1027 enum pipe pipe)
1028{
1029 int pp_reg, lvds_reg;
1030 u32 val;
1031 enum pipe panel_pipe = PIPE_A;
0de3b485 1032 bool locked = true;
ea0760cf
JB		 1033
1034 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1035 pp_reg = PCH_PP_CONTROL;
1036 lvds_reg = PCH_LVDS;
1037 } else {
1038 pp_reg = PP_CONTROL;
1039 lvds_reg = LVDS;
1040 }
1041
1042 val = I915_READ(pp_reg);
1043 if (!(val & PANEL_POWER_ON) ||
1044 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1045 locked = false;
1046
1047 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1048 panel_pipe = PIPE_B;
1049
1050 WARN(panel_pipe == pipe && locked,
1051 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1052 pipe_name(pipe));
ea0760cf
JB		 1053}
1054
b840d907
JB		 1055void assert_pipe(struct drm_i915_private *dev_priv,
1056 enum pipe pipe, bool state)
b24e7179
JB		 1057{
1058 int reg;
1059 u32 val;
63d7bbe9 1060 bool cur_state;
702e7a56
PZ		 1061 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1062 pipe);
b24e7179 1063
8e636784
DV		 1064 /* if we need the pipe A quirk it must be always on */
1065 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1066 state = true;
1067
b97186f0
PZ		 1068 if (!intel_display_power_enabled(dev_priv->dev,
1069 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1070 cur_state = false;
1071 } else {
1072 reg = PIPECONF(cpu_transcoder);
1073 val = I915_READ(reg);
1074 cur_state = !!(val & PIPECONF_ENABLE);
1075 }
1076
63d7bbe9
JB		 1077 WARN(cur_state != state,
1078 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1079 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1080}
1081
931872fc
CW		 1082static void assert_plane(struct drm_i915_private *dev_priv,
1083 enum plane plane, bool state)
b24e7179
JB		 1084{
1085 int reg;
1086 u32 val;
931872fc 1087 bool cur_state;
b24e7179
JB		 1088
1089 reg = DSPCNTR(plane);
1090 val = I915_READ(reg);
931872fc
CW		 1091 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1092 WARN(cur_state != state,
1093 "plane %c assertion failure (expected %s, current %s)\n",
1094 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1095}
1096
931872fc
CW		 1097#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1098#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1099
b24e7179
JB		 1100static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1101 enum pipe pipe)
1102{
653e1026 1103 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1104 int reg, i;
1105 u32 val;
1106 int cur_pipe;
1107
653e1026
VS		 1108 /* Primary planes are fixed to pipes on gen4+ */
1109 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1110 reg = DSPCNTR(pipe);
1111 val = I915_READ(reg);
1112 WARN((val & DISPLAY_PLANE_ENABLE),
1113 "plane %c assertion failure, should be disabled but not\n",
1114 plane_name(pipe));
19ec1358 1115 return;
28c05794 1116 }
19ec1358 1117
b24e7179 1118 /* Need to check both planes against the pipe */
653e1026 1119 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
b24e7179
JB		 1120 reg = DSPCNTR(i);
1121 val = I915_READ(reg);
1122 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1123 DISPPLANE_SEL_PIPE_SHIFT;
1124 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1125 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1126 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1127 }
1128}
1129
19332d7a
JB		 1130static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1131 enum pipe pipe)
1132{
20674eef 1133 struct drm_device *dev = dev_priv->dev;
19332d7a
JB		 1134 int reg, i;
1135 u32 val;
1136
20674eef
VS		 1137 if (IS_VALLEYVIEW(dev)) {
1138 for (i = 0; i < dev_priv->num_plane; i++) {
1139 reg = SPCNTR(pipe, i);
1140 val = I915_READ(reg);
1141 WARN((val & SP_ENABLE),
1142 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1143 sprite_name(pipe, i), pipe_name(pipe));
1144 }
1145 } else if (INTEL_INFO(dev)->gen >= 7) {
1146 reg = SPRCTL(pipe);
19332d7a 1147 val = I915_READ(reg);
20674eef 1148 WARN((val & SPRITE_ENABLE),
06da8da2 1149 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1150 plane_name(pipe), pipe_name(pipe));
1151 } else if (INTEL_INFO(dev)->gen >= 5) {
1152 reg = DVSCNTR(pipe);
19332d7a 1153 val = I915_READ(reg);
20674eef 1154 WARN((val & DVS_ENABLE),
06da8da2 1155 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1156 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1157 }
1158}
1159
92f2584a
JB		 1160static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1161{
1162 u32 val;
1163 bool enabled;
1164
9d82aa17
ED		 1165 if (HAS_PCH_LPT(dev_priv->dev)) {
1166 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1167 return;
1168 }
1169
92f2584a
JB		 1170 val = I915_READ(PCH_DREF_CONTROL);
1171 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1172 DREF_SUPERSPREAD_SOURCE_MASK));
1173 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1174}
1175
ab9412ba
DV		 1176static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1177 enum pipe pipe)
92f2584a
JB		 1178{
1179 int reg;
1180 u32 val;
1181 bool enabled;
1182
ab9412ba 1183 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1184 val = I915_READ(reg);
1185 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1186 WARN(enabled,
1187 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1188 pipe_name(pipe));
92f2584a
JB		 1189}
1190
4e634389
KP		 1191static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1192 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1193{
1194 if ((val & DP_PORT_EN) == 0)
1195 return false;
1196
1197 if (HAS_PCH_CPT(dev_priv->dev)) {
1198 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1199 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1200 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1201 return false;
1202 } else {
1203 if ((val & DP_PIPE_MASK) != (pipe << 30))
1204 return false;
1205 }
1206 return true;
1207}
1208
1519b995
KP		 1209static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1210 enum pipe pipe, u32 val)
1211{
dc0fa718 1212 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1213 return false;
1214
1215 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1216 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1217 return false;
1218 } else {
dc0fa718 1219 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1220 return false;
1221 }
1222 return true;
1223}
1224
1225static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1226 enum pipe pipe, u32 val)
1227{
1228 if ((val & LVDS_PORT_EN) == 0)
1229 return false;
1230
1231 if (HAS_PCH_CPT(dev_priv->dev)) {
1232 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1233 return false;
1234 } else {
1235 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1236 return false;
1237 }
1238 return true;
1239}
1240
1241static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1242 enum pipe pipe, u32 val)
1243{
1244 if ((val & ADPA_DAC_ENABLE) == 0)
1245 return false;
1246 if (HAS_PCH_CPT(dev_priv->dev)) {
1247 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1248 return false;
1249 } else {
1250 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1251 return false;
1252 }
1253 return true;
1254}
1255
291906f1 1256static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1257 enum pipe pipe, int reg, u32 port_sel)
291906f1 1258{
47a05eca 1259 u32 val = I915_READ(reg);
4e634389 1260 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1261 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1262 reg, pipe_name(pipe));
de9a35ab 1263
75c5da27
DV		 1264 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1265 && (val & DP_PIPEB_SELECT),
de9a35ab 1266 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1267}
1268
1269static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1270 enum pipe pipe, int reg)
1271{
47a05eca 1272 u32 val = I915_READ(reg);
b70ad586 1273 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1274 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1275 reg, pipe_name(pipe));
de9a35ab 1276
dc0fa718 1277 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1278 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1279 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1280}
1281
1282static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1283 enum pipe pipe)
1284{
1285 int reg;
1286 u32 val;
291906f1 1287
f0575e92
KP		 1288 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1289 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1290 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1291
1292 reg = PCH_ADPA;
1293 val = I915_READ(reg);
b70ad586 1294 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1295 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1296 pipe_name(pipe));
291906f1
JB		 1297
1298 reg = PCH_LVDS;
1299 val = I915_READ(reg);
b70ad586 1300 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1301 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1302 pipe_name(pipe));
291906f1 1303
e2debe91
PZ		 1304 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1305 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1306 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1307}
1308
87442f73
DV		 1309static void vlv_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1310{
1311 int reg;
1312 u32 val;
1313
1314 assert_pipe_disabled(dev_priv, pipe);
1315
1316 /* No really, not for ILK+ */
1317 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1318
1319 /* PLL is protected by panel, make sure we can write it */
1320 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1321 assert_panel_unlocked(dev_priv, pipe);
1322
1323 reg = DPLL(pipe);
1324 val = I915_READ(reg);
1325 val |= DPLL_VCO_ENABLE;
1326
1327 /* We do this three times for luck */
1328 I915_WRITE(reg, val);
1329 POSTING_READ(reg);
1330 udelay(150); /* wait for warmup */
1331 I915_WRITE(reg, val);
1332 POSTING_READ(reg);
1333 udelay(150); /* wait for warmup */
1334 I915_WRITE(reg, val);
1335 POSTING_READ(reg);
1336 udelay(150); /* wait for warmup */
1337}
1338
66e3d5c0 1339static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1340{
66e3d5c0
DV		 1341 struct drm_device *dev = crtc->base.dev;
1342 struct drm_i915_private *dev_priv = dev->dev_private;
1343 int reg = DPLL(crtc->pipe);
1344 u32 dpll = crtc->config.dpll_hw_state.dpll;
63d7bbe9 1345
66e3d5c0 1346 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1347
63d7bbe9 1348 /* No really, not for ILK+ */
87442f73 1349 BUG_ON(dev_priv->info->gen >= 5);
63d7bbe9
JB		 1350
1351 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1352 if (IS_MOBILE(dev) && !IS_I830(dev))
1353 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1354
66e3d5c0
DV		 1355 I915_WRITE(reg, dpll);
1356
1357 /* Wait for the clocks to stabilize. */
1358 POSTING_READ(reg);
1359 udelay(150);
1360
1361 if (INTEL_INFO(dev)->gen >= 4) {
1362 I915_WRITE(DPLL_MD(crtc->pipe),
1363 crtc->config.dpll_hw_state.dpll_md);
1364 } else {
1365 /* The pixel multiplier can only be updated once the
1366 * DPLL is enabled and the clocks are stable.
1367 *
1368 * So write it again.
1369 */
1370 I915_WRITE(reg, dpll);
1371 }
63d7bbe9
JB		 1372
1373 /* We do this three times for luck */
66e3d5c0 1374 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1375 POSTING_READ(reg);
1376 udelay(150); /* wait for warmup */
66e3d5c0 1377 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1378 POSTING_READ(reg);
1379 udelay(150); /* wait for warmup */
66e3d5c0 1380 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1381 POSTING_READ(reg);
1382 udelay(150); /* wait for warmup */
1383}
1384
1385/**
1386 * intel_disable_pll - disable a PLL
1387 * @dev_priv: i915 private structure
1388 * @pipe: pipe PLL to disable
1389 *
1390 * Disable the PLL for @pipe, making sure the pipe is off first.
1391 *
1392 * Note! This is for pre-ILK only.
1393 */
1394static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1395{
1396 int reg;
1397 u32 val;
1398
1399 /* Don't disable pipe A or pipe A PLLs if needed */
1400 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1401 return;
1402
1403 /* Make sure the pipe isn't still relying on us */
1404 assert_pipe_disabled(dev_priv, pipe);
1405
1406 reg = DPLL(pipe);
1407 val = I915_READ(reg);
1408 val &= ~DPLL_VCO_ENABLE;
1409 I915_WRITE(reg, val);
1410 POSTING_READ(reg);
1411}
1412
89b667f8
JB		 1413void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1414{
1415 u32 port_mask;
1416
1417 if (!port)
1418 port_mask = DPLL_PORTB_READY_MASK;
1419 else
1420 port_mask = DPLL_PORTC_READY_MASK;
1421
1422 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1423 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1424 'B' + port, I915_READ(DPLL(0)));
1425}
1426
92f2584a 1427/**
e72f9fbf 1428 * ironlake_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1429 * @dev_priv: i915 private structure
1430 * @pipe: pipe PLL to enable
1431 *
1432 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1433 * drives the transcoder clock.
1434 */
e2b78267 1435static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1436{
e2b78267
DV		 1437 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1438 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1439
48da64a8 1440 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1441 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1442 if (WARN_ON(pll == NULL))
48da64a8
CW		 1443 return;
1444
1445 if (WARN_ON(pll->refcount == 0))
1446 return;
ee7b9f93 1447
46edb027
DV		 1448 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1449 pll->name, pll->active, pll->on,
e2b78267 1450 crtc->base.base.id);
92f2584a 1451
cdbd2316
DV		 1452 if (pll->active++) {
1453 WARN_ON(!pll->on);
e9d6944e 1454 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1455 return;
1456 }
f4a091c7 1457 WARN_ON(pll->on);
ee7b9f93 1458
46edb027 1459 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1460 pll->enable(dev_priv, pll);
ee7b9f93 1461 pll->on = true;
92f2584a
JB		 1462}
1463
e2b78267 1464static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1465{
e2b78267
DV		 1466 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1467 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1468
92f2584a
JB		 1469 /* PCH only available on ILK+ */
1470 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1471 if (WARN_ON(pll == NULL))
ee7b9f93 1472 return;
92f2584a 1473
48da64a8
CW		 1474 if (WARN_ON(pll->refcount == 0))
1475 return;
7a419866 1476
46edb027
DV		 1477 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1478 pll->name, pll->active, pll->on,
e2b78267 1479 crtc->base.base.id);
7a419866 1480
48da64a8 1481 if (WARN_ON(pll->active == 0)) {
e9d6944e 1482 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1483 return;
1484 }
1485
e9d6944e 1486 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1487 WARN_ON(!pll->on);
cdbd2316 1488 if (--pll->active)
7a419866 1489 return;
ee7b9f93 1490
46edb027 1491 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1492 pll->disable(dev_priv, pll);
ee7b9f93 1493 pll->on = false;
92f2584a
JB		 1494}
1495
b8a4f404
PZ		 1496static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1497 enum pipe pipe)
040484af 1498{
23670b32 1499 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1500 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1501 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1502 uint32_t reg, val, pipeconf_val;
040484af
JB		 1503
1504 /* PCH only available on ILK+ */
1505 BUG_ON(dev_priv->info->gen < 5);
1506
1507 /* Make sure PCH DPLL is enabled */
e72f9fbf 1508 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1509 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1510
1511 /* FDI must be feeding us bits for PCH ports */
1512 assert_fdi_tx_enabled(dev_priv, pipe);
1513 assert_fdi_rx_enabled(dev_priv, pipe);
1514
23670b32
DV		 1515 if (HAS_PCH_CPT(dev)) {
1516 /* Workaround: Set the timing override bit before enabling the
1517 * pch transcoder. */
1518 reg = TRANS_CHICKEN2(pipe);
1519 val = I915_READ(reg);
1520 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1521 I915_WRITE(reg, val);
59c859d6 1522 }
23670b32 1523
ab9412ba 1524 reg = PCH_TRANSCONF(pipe);
040484af 1525 val = I915_READ(reg);
5f7f726d 1526 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1527
1528 if (HAS_PCH_IBX(dev_priv->dev)) {
1529 /*
1530 * make the BPC in transcoder be consistent with
1531 * that in pipeconf reg.
1532 */
dfd07d72
DV		 1533 val &= ~PIPECONF_BPC_MASK;
1534 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1535 }
5f7f726d
PZ		 1536
1537 val &= ~TRANS_INTERLACE_MASK;
1538 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1539 if (HAS_PCH_IBX(dev_priv->dev) &&
1540 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1541 val |= TRANS_LEGACY_INTERLACED_ILK;
1542 else
1543 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1544 else
1545 val |= TRANS_PROGRESSIVE;
1546
040484af
JB		 1547 I915_WRITE(reg, val | TRANS_ENABLE);
1548 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1549 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1550}
1551
8fb033d7 1552static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1553 enum transcoder cpu_transcoder)
040484af 1554{
8fb033d7 1555 u32 val, pipeconf_val;
8fb033d7
PZ		 1556
1557 /* PCH only available on ILK+ */
1558 BUG_ON(dev_priv->info->gen < 5);
1559
8fb033d7 1560 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1561 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1562 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1563
223a6fdf
PZ		 1564 /* Workaround: set timing override bit. */
1565 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1566 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1567 I915_WRITE(_TRANSA_CHICKEN2, val);
1568
25f3ef11 1569 val = TRANS_ENABLE;
937bb610 1570 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1571
9a76b1c6
PZ		 1572 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1573 PIPECONF_INTERLACED_ILK)
a35f2679 1574 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1575 else
1576 val |= TRANS_PROGRESSIVE;
1577
ab9412ba
DV		 1578 I915_WRITE(LPT_TRANSCONF, val);
1579 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1580 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1581}
1582
b8a4f404
PZ		 1583static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1584 enum pipe pipe)
040484af 1585{
23670b32
DV		 1586 struct drm_device *dev = dev_priv->dev;
1587 uint32_t reg, val;
040484af
JB		 1588
1589 /* FDI relies on the transcoder */
1590 assert_fdi_tx_disabled(dev_priv, pipe);
1591 assert_fdi_rx_disabled(dev_priv, pipe);
1592
291906f1
JB		 1593 /* Ports must be off as well */
1594 assert_pch_ports_disabled(dev_priv, pipe);
1595
ab9412ba 1596 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1597 val = I915_READ(reg);
1598 val &= ~TRANS_ENABLE;
1599 I915_WRITE(reg, val);
1600 /* wait for PCH transcoder off, transcoder state */
1601 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1602 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1603
1604 if (!HAS_PCH_IBX(dev)) {
1605 /* Workaround: Clear the timing override chicken bit again. */
1606 reg = TRANS_CHICKEN2(pipe);
1607 val = I915_READ(reg);
1608 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1609 I915_WRITE(reg, val);
1610 }
040484af
JB		 1611}
1612
ab4d966c 1613static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1614{
8fb033d7
PZ		 1615 u32 val;
1616
ab9412ba 1617 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1618 val &= ~TRANS_ENABLE;
ab9412ba 1619 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1620 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1621 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1622 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1623
1624 /* Workaround: clear timing override bit. */
1625 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1626 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1627 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1628}
1629
b24e7179 1630/**
309cfea8 1631 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1632 * @dev_priv: i915 private structure
1633 * @pipe: pipe to enable
040484af 1634 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1635 *
1636 * Enable @pipe, making sure that various hardware specific requirements
1637 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1638 *
1639 * @pipe should be %PIPE_A or %PIPE_B.
1640 *
1641 * Will wait until the pipe is actually running (i.e. first vblank) before
1642 * returning.
1643 */
040484af
JB		 1644static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1645 bool pch_port)
b24e7179 1646{
702e7a56
PZ		 1647 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1648 pipe);
1a240d4d 1649 enum pipe pch_transcoder;
b24e7179
JB		 1650 int reg;
1651 u32 val;
1652
58c6eaa2
DV		 1653 assert_planes_disabled(dev_priv, pipe);
1654 assert_sprites_disabled(dev_priv, pipe);
1655
681e5811 1656 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1657 pch_transcoder = TRANSCODER_A;
1658 else
1659 pch_transcoder = pipe;
1660
b24e7179
JB		 1661 /*
1662 * A pipe without a PLL won't actually be able to drive bits from
1663 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1664 * need the check.
1665 */
1666 if (!HAS_PCH_SPLIT(dev_priv->dev))
1667 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1668 else {
1669 if (pch_port) {
1670 /* if driving the PCH, we need FDI enabled */
cc391bbb 1671 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1672 assert_fdi_tx_pll_enabled(dev_priv,
1673 (enum pipe) cpu_transcoder);
040484af
JB		 1674 }
1675 /* FIXME: assert CPU port conditions for SNB+ */
1676 }
b24e7179 1677
702e7a56 1678 reg = PIPECONF(cpu_transcoder);
b24e7179 1679 val = I915_READ(reg);
00d70b15
CW		 1680 if (val & PIPECONF_ENABLE)
1681 return;
1682
1683 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1684 intel_wait_for_vblank(dev_priv->dev, pipe);
1685}
1686
1687/**
309cfea8 1688 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1689 * @dev_priv: i915 private structure
1690 * @pipe: pipe to disable
1691 *
1692 * Disable @pipe, making sure that various hardware specific requirements
1693 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1694 *
1695 * @pipe should be %PIPE_A or %PIPE_B.
1696 *
1697 * Will wait until the pipe has shut down before returning.
1698 */
1699static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1700 enum pipe pipe)
1701{
702e7a56
PZ		 1702 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1703 pipe);
b24e7179
JB		 1704 int reg;
1705 u32 val;
1706
1707 /*
1708 * Make sure planes won't keep trying to pump pixels to us,
1709 * or we might hang the display.
1710 */
1711 assert_planes_disabled(dev_priv, pipe);
19332d7a 1712 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1713
1714 /* Don't disable pipe A or pipe A PLLs if needed */
1715 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1716 return;
1717
702e7a56 1718 reg = PIPECONF(cpu_transcoder);
b24e7179 1719 val = I915_READ(reg);
00d70b15
CW		 1720 if ((val & PIPECONF_ENABLE) == 0)
1721 return;
1722
1723 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1724 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1725}
1726
d74362c9
KP		 1727/*
1728 * Plane regs are double buffered, going from enabled->disabled needs a
1729 * trigger in order to latch. The display address reg provides this.
1730 */
6f1d69b0 1731void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1732 enum plane plane)
1733{
14f86147
DL		 1734 if (dev_priv->info->gen >= 4)
1735 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1736 else
1737 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1738}
1739
b24e7179
JB		 1740/**
1741 * intel_enable_plane - enable a display plane on a given pipe
1742 * @dev_priv: i915 private structure
1743 * @plane: plane to enable
1744 * @pipe: pipe being fed
1745 *
1746 * Enable @plane on @pipe, making sure that @pipe is running first.
1747 */
1748static void intel_enable_plane(struct drm_i915_private *dev_priv,
1749 enum plane plane, enum pipe pipe)
1750{
1751 int reg;
1752 u32 val;
1753
1754 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1755 assert_pipe_enabled(dev_priv, pipe);
1756
1757 reg = DSPCNTR(plane);
1758 val = I915_READ(reg);
00d70b15
CW		 1759 if (val & DISPLAY_PLANE_ENABLE)
1760 return;
1761
1762 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1763 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1764 intel_wait_for_vblank(dev_priv->dev, pipe);
1765}
1766
b24e7179
JB		 1767/**
1768 * intel_disable_plane - disable a display plane
1769 * @dev_priv: i915 private structure
1770 * @plane: plane to disable
1771 * @pipe: pipe consuming the data
1772 *
1773 * Disable @plane; should be an independent operation.
1774 */
1775static void intel_disable_plane(struct drm_i915_private *dev_priv,
1776 enum plane plane, enum pipe pipe)
1777{
1778 int reg;
1779 u32 val;
1780
1781 reg = DSPCNTR(plane);
1782 val = I915_READ(reg);
00d70b15
CW		 1783 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1784 return;
1785
1786 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1787 intel_flush_display_plane(dev_priv, plane);
1788 intel_wait_for_vblank(dev_priv->dev, pipe);
1789}
1790
693db184
CW		 1791static bool need_vtd_wa(struct drm_device *dev)
1792{
1793#ifdef CONFIG_INTEL_IOMMU
1794 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1795 return true;
1796#endif
1797 return false;
1798}
1799
127bd2ac 1800int
48b956c5 1801intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1802 struct drm_i915_gem_object *obj,
919926ae 1803 struct intel_ring_buffer *pipelined)
6b95a207 1804{
ce453d81 1805 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1806 u32 alignment;
1807 int ret;
1808
05394f39 1809 switch (obj->tiling_mode) {
6b95a207 1810 case I915_TILING_NONE:
534843da
CW		 1811 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1812 alignment = 128 * 1024;
a6c45cf0 1813 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1814 alignment = 4 * 1024;
1815 else
1816 alignment = 64 * 1024;
6b95a207
KH		 1817 break;
1818 case I915_TILING_X:
1819 /* pin() will align the object as required by fence */
1820 alignment = 0;
1821 break;
1822 case I915_TILING_Y:
8bb6e959
DV		 1823 /* Despite that we check this in framebuffer_init userspace can
1824 * screw us over and change the tiling after the fact. Only
1825 * pinned buffers can't change their tiling. */
1826 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1827 return -EINVAL;
1828 default:
1829 BUG();
1830 }
1831
693db184
CW		 1832 /* Note that the w/a also requires 64 PTE of padding following the
1833 * bo. We currently fill all unused PTE with the shadow page and so
1834 * we should always have valid PTE following the scanout preventing
1835 * the VT-d warning.
1836 */
1837 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1838 alignment = 256 * 1024;
1839
ce453d81 1840 dev_priv->mm.interruptible = false;
2da3b9b9 1841 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1842 if (ret)
ce453d81 1843 goto err_interruptible;
6b95a207
KH		 1844
1845 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1846 * fence, whereas 965+ only requires a fence if using
1847 * framebuffer compression. For simplicity, we always install
1848 * a fence as the cost is not that onerous.
1849 */
06d98131 1850 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1851 if (ret)
1852 goto err_unpin;
1690e1eb 1853
9a5a53b3 1854 i915_gem_object_pin_fence(obj);
6b95a207 1855
ce453d81 1856 dev_priv->mm.interruptible = true;
6b95a207 1857 return 0;
48b956c5
CW		 1858
1859err_unpin:
1860 i915_gem_object_unpin(obj);
ce453d81
CW		 1861err_interruptible:
1862 dev_priv->mm.interruptible = true;
48b956c5 1863 return ret;
6b95a207
KH		 1864}
1865
1690e1eb
CW		 1866void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1867{
1868 i915_gem_object_unpin_fence(obj);
1869 i915_gem_object_unpin(obj);
1870}
1871
c2c75131
DV		 1872/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1873 * is assumed to be a power-of-two. */
bc752862
CW		 1874unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1875 unsigned int tiling_mode,
1876 unsigned int cpp,
1877 unsigned int pitch)
c2c75131 1878{
bc752862
CW		 1879 if (tiling_mode != I915_TILING_NONE) {
1880 unsigned int tile_rows, tiles;
c2c75131 1881
bc752862
CW		 1882 tile_rows = *y / 8;
1883 *y %= 8;
c2c75131 1884
bc752862
CW		 1885 tiles = *x / (512/cpp);
1886 *x %= 512/cpp;
1887
1888 return tile_rows * pitch * 8 + tiles * 4096;
1889 } else {
1890 unsigned int offset;
1891
1892 offset = *y * pitch + *x * cpp;
1893 *y = 0;
1894 *x = (offset & 4095) / cpp;
1895 return offset & -4096;
1896 }
c2c75131
DV		 1897}
1898
17638cd6
JB		 1899static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1900 int x, int y)
81255565
JB		 1901{
1902 struct drm_device *dev = crtc->dev;
1903 struct drm_i915_private *dev_priv = dev->dev_private;
1904 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1905 struct intel_framebuffer *intel_fb;
05394f39 1906 struct drm_i915_gem_object *obj;
81255565 1907 int plane = intel_crtc->plane;
e506a0c6 1908 unsigned long linear_offset;
81255565 1909 u32 dspcntr;
5eddb70b 1910 u32 reg;
81255565
JB		 1911
1912 switch (plane) {
1913 case 0:
1914 case 1:
1915 break;
1916 default:
84f44ce7 1917 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 1918 return -EINVAL;
1919 }
1920
1921 intel_fb = to_intel_framebuffer(fb);
1922 obj = intel_fb->obj;
81255565 1923
5eddb70b
CW		 1924 reg = DSPCNTR(plane);
1925 dspcntr = I915_READ(reg);
81255565
JB		 1926 /* Mask out pixel format bits in case we change it */
1927 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 1928 switch (fb->pixel_format) {
1929 case DRM_FORMAT_C8:
81255565
JB		 1930 dspcntr |= DISPPLANE_8BPP;
1931 break;
57779d06
VS		 1932 case DRM_FORMAT_XRGB1555:
1933 case DRM_FORMAT_ARGB1555:
1934 dspcntr |= DISPPLANE_BGRX555;
81255565 1935 break;
57779d06
VS		 1936 case DRM_FORMAT_RGB565:
1937 dspcntr |= DISPPLANE_BGRX565;
1938 break;
1939 case DRM_FORMAT_XRGB8888:
1940 case DRM_FORMAT_ARGB8888:
1941 dspcntr |= DISPPLANE_BGRX888;
1942 break;
1943 case DRM_FORMAT_XBGR8888:
1944 case DRM_FORMAT_ABGR8888:
1945 dspcntr |= DISPPLANE_RGBX888;
1946 break;
1947 case DRM_FORMAT_XRGB2101010:
1948 case DRM_FORMAT_ARGB2101010:
1949 dspcntr |= DISPPLANE_BGRX101010;
1950 break;
1951 case DRM_FORMAT_XBGR2101010:
1952 case DRM_FORMAT_ABGR2101010:
1953 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 1954 break;
1955 default:
baba133a 1956 BUG();
81255565 1957 }
57779d06 1958
a6c45cf0 1959 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1960 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1961 dspcntr |= DISPPLANE_TILED;
1962 else
1963 dspcntr &= ~DISPPLANE_TILED;
1964 }
1965
de1aa629
VS		 1966 if (IS_G4X(dev))
1967 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1968
5eddb70b 1969 I915_WRITE(reg, dspcntr);
81255565 1970
e506a0c6 1971 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 1972
c2c75131
DV		 1973 if (INTEL_INFO(dev)->gen >= 4) {
1974 intel_crtc->dspaddr_offset =
bc752862
CW		 1975 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1976 fb->bits_per_pixel / 8,
1977 fb->pitches[0]);
c2c75131
DV		 1978 linear_offset -= intel_crtc->dspaddr_offset;
1979 } else {
e506a0c6 1980 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 1981 }
e506a0c6
DV		 1982
1983 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
1984 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 1985 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 1986 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 1987 I915_MODIFY_DISPBASE(DSPSURF(plane),
1988 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 1989 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 1990 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 1991 } else
e506a0c6 1992 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 1993 POSTING_READ(reg);
81255565 1994
17638cd6
JB		 1995 return 0;
1996}
1997
1998static int ironlake_update_plane(struct drm_crtc *crtc,
1999 struct drm_framebuffer *fb, int x, int y)
2000{
2001 struct drm_device *dev = crtc->dev;
2002 struct drm_i915_private *dev_priv = dev->dev_private;
2003 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2004 struct intel_framebuffer *intel_fb;
2005 struct drm_i915_gem_object *obj;
2006 int plane = intel_crtc->plane;
e506a0c6 2007 unsigned long linear_offset;
17638cd6
JB		 2008 u32 dspcntr;
2009 u32 reg;
2010
2011 switch (plane) {
2012 case 0:
2013 case 1:
27f8227b 2014 case 2:
17638cd6
JB		 2015 break;
2016 default:
84f44ce7 2017 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2018 return -EINVAL;
2019 }
2020
2021 intel_fb = to_intel_framebuffer(fb);
2022 obj = intel_fb->obj;
2023
2024 reg = DSPCNTR(plane);
2025 dspcntr = I915_READ(reg);
2026 /* Mask out pixel format bits in case we change it */
2027 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2028 switch (fb->pixel_format) {
2029 case DRM_FORMAT_C8:
17638cd6
JB		 2030 dspcntr |= DISPPLANE_8BPP;
2031 break;
57779d06
VS		 2032 case DRM_FORMAT_RGB565:
2033 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2034 break;
57779d06
VS		 2035 case DRM_FORMAT_XRGB8888:
2036 case DRM_FORMAT_ARGB8888:
2037 dspcntr |= DISPPLANE_BGRX888;
2038 break;
2039 case DRM_FORMAT_XBGR8888:
2040 case DRM_FORMAT_ABGR8888:
2041 dspcntr |= DISPPLANE_RGBX888;
2042 break;
2043 case DRM_FORMAT_XRGB2101010:
2044 case DRM_FORMAT_ARGB2101010:
2045 dspcntr |= DISPPLANE_BGRX101010;
2046 break;
2047 case DRM_FORMAT_XBGR2101010:
2048 case DRM_FORMAT_ABGR2101010:
2049 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2050 break;
2051 default:
baba133a 2052 BUG();
17638cd6
JB		 2053 }
2054
2055 if (obj->tiling_mode != I915_TILING_NONE)
2056 dspcntr |= DISPPLANE_TILED;
2057 else
2058 dspcntr &= ~DISPPLANE_TILED;
2059
2060 /* must disable */
2061 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2062
2063 I915_WRITE(reg, dspcntr);
2064
e506a0c6 2065 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2066 intel_crtc->dspaddr_offset =
bc752862
CW		 2067 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2068 fb->bits_per_pixel / 8,
2069 fb->pitches[0]);
c2c75131 2070 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2071
e506a0c6
DV		 2072 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2073 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2074 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2075 I915_MODIFY_DISPBASE(DSPSURF(plane),
2076 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2077 if (IS_HASWELL(dev)) {
2078 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2079 } else {
2080 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2081 I915_WRITE(DSPLINOFF(plane), linear_offset);
2082 }
17638cd6
JB		 2083 POSTING_READ(reg);
2084
2085 return 0;
2086}
2087
2088/* Assume fb object is pinned & idle & fenced and just update base pointers */
2089static int
2090intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2091 int x, int y, enum mode_set_atomic state)
2092{
2093 struct drm_device *dev = crtc->dev;
2094 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2095
6b8e6ed0
CW		 2096 if (dev_priv->display.disable_fbc)
2097 dev_priv->display.disable_fbc(dev);
3dec0095 2098 intel_increase_pllclock(crtc);
81255565 2099
6b8e6ed0 2100 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2101}
2102
96a02917
VS		 2103void intel_display_handle_reset(struct drm_device *dev)
2104{
2105 struct drm_i915_private *dev_priv = dev->dev_private;
2106 struct drm_crtc *crtc;
2107
2108 /*
2109 * Flips in the rings have been nuked by the reset,
2110 * so complete all pending flips so that user space
2111 * will get its events and not get stuck.
2112 *
2113 * Also update the base address of all primary
2114 * planes to the the last fb to make sure we're
2115 * showing the correct fb after a reset.
2116 *
2117 * Need to make two loops over the crtcs so that we
2118 * don't try to grab a crtc mutex before the
2119 * pending_flip_queue really got woken up.
2120 */
2121
2122 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2123 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2124 enum plane plane = intel_crtc->plane;
2125
2126 intel_prepare_page_flip(dev, plane);
2127 intel_finish_page_flip_plane(dev, plane);
2128 }
2129
2130 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2131 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2132
2133 mutex_lock(&crtc->mutex);
2134 if (intel_crtc->active)
2135 dev_priv->display.update_plane(crtc, crtc->fb,
2136 crtc->x, crtc->y);
2137 mutex_unlock(&crtc->mutex);
2138 }
2139}
2140
14667a4b
CW		 2141static int
2142intel_finish_fb(struct drm_framebuffer *old_fb)
2143{
2144 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2145 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2146 bool was_interruptible = dev_priv->mm.interruptible;
2147 int ret;
2148
14667a4b
CW		 2149 /* Big Hammer, we also need to ensure that any pending
2150 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2151 * current scanout is retired before unpinning the old
2152 * framebuffer.
2153 *
2154 * This should only fail upon a hung GPU, in which case we
2155 * can safely continue.
2156 */
2157 dev_priv->mm.interruptible = false;
2158 ret = i915_gem_object_finish_gpu(obj);
2159 dev_priv->mm.interruptible = was_interruptible;
2160
2161 return ret;
2162}
2163
198598d0
VS		 2164static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2165{
2166 struct drm_device *dev = crtc->dev;
2167 struct drm_i915_master_private *master_priv;
2168 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2169
2170 if (!dev->primary->master)
2171 return;
2172
2173 master_priv = dev->primary->master->driver_priv;
2174 if (!master_priv->sarea_priv)
2175 return;
2176
2177 switch (intel_crtc->pipe) {
2178 case 0:
2179 master_priv->sarea_priv->pipeA_x = x;
2180 master_priv->sarea_priv->pipeA_y = y;
2181 break;
2182 case 1:
2183 master_priv->sarea_priv->pipeB_x = x;
2184 master_priv->sarea_priv->pipeB_y = y;
2185 break;
2186 default:
2187 break;
2188 }
2189}
2190
5c3b82e2 2191static int
3c4fdcfb 2192intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2193 struct drm_framebuffer *fb)
79e53945
JB		 2194{
2195 struct drm_device *dev = crtc->dev;
6b8e6ed0 2196 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2197 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2198 struct drm_framebuffer *old_fb;
5c3b82e2 2199 int ret;
79e53945
JB		 2200
2201 /* no fb bound */
94352cf9 2202 if (!fb) {
a5071c2f 2203 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2204 return 0;
2205 }
2206
7eb552ae 2207 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2208 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2209 plane_name(intel_crtc->plane),
2210 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2211 return -EINVAL;
79e53945
JB		 2212 }
2213
5c3b82e2 2214 mutex_lock(&dev->struct_mutex);
265db958 2215 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2216 to_intel_framebuffer(fb)->obj,
919926ae 2217 NULL);
5c3b82e2
CW		 2218 if (ret != 0) {
2219 mutex_unlock(&dev->struct_mutex);
a5071c2f 2220 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2221 return ret;
2222 }
79e53945 2223
94352cf9 2224 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2225 if (ret) {
94352cf9 2226 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2227 mutex_unlock(&dev->struct_mutex);
a5071c2f 2228 DRM_ERROR("failed to update base address\n");
4e6cfefc 2229 return ret;
79e53945 2230 }
3c4fdcfb 2231
94352cf9
DV		 2232 old_fb = crtc->fb;
2233 crtc->fb = fb;
6c4c86f5
DV		 2234 crtc->x = x;
2235 crtc->y = y;
94352cf9 2236
b7f1de28 2237 if (old_fb) {
d7697eea
DV		 2238 if (intel_crtc->active && old_fb != fb)
2239 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2240 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2241 }
652c393a 2242
6b8e6ed0 2243 intel_update_fbc(dev);
5c3b82e2 2244 mutex_unlock(&dev->struct_mutex);
79e53945 2245
198598d0 2246 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2247
2248 return 0;
79e53945
JB		 2249}
2250
5e84e1a4
ZW		 2251static void intel_fdi_normal_train(struct drm_crtc *crtc)
2252{
2253 struct drm_device *dev = crtc->dev;
2254 struct drm_i915_private *dev_priv = dev->dev_private;
2255 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2256 int pipe = intel_crtc->pipe;
2257 u32 reg, temp;
2258
2259 /* enable normal train */
2260 reg = FDI_TX_CTL(pipe);
2261 temp = I915_READ(reg);
61e499bf 2262 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2263 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2264 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2265 } else {
2266 temp &= ~FDI_LINK_TRAIN_NONE;
2267 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2268 }
5e84e1a4
ZW		 2269 I915_WRITE(reg, temp);
2270
2271 reg = FDI_RX_CTL(pipe);
2272 temp = I915_READ(reg);
2273 if (HAS_PCH_CPT(dev)) {
2274 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2275 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2276 } else {
2277 temp &= ~FDI_LINK_TRAIN_NONE;
2278 temp |= FDI_LINK_TRAIN_NONE;
2279 }
2280 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2281
2282 /* wait one idle pattern time */
2283 POSTING_READ(reg);
2284 udelay(1000);
357555c0
JB		 2285
2286 /* IVB wants error correction enabled */
2287 if (IS_IVYBRIDGE(dev))
2288 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2289 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2290}
2291
1e833f40
DV		 2292static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2293{
2294 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2295}
2296
01a415fd
DV		 2297static void ivb_modeset_global_resources(struct drm_device *dev)
2298{
2299 struct drm_i915_private *dev_priv = dev->dev_private;
2300 struct intel_crtc *pipe_B_crtc =
2301 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2302 struct intel_crtc *pipe_C_crtc =
2303 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2304 uint32_t temp;
2305
1e833f40
DV		 2306 /*
2307 * When everything is off disable fdi C so that we could enable fdi B
2308 * with all lanes. Note that we don't care about enabled pipes without
2309 * an enabled pch encoder.
2310 */
2311 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2312 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2313 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2314 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2315
2316 temp = I915_READ(SOUTH_CHICKEN1);
2317 temp &= ~FDI_BC_BIFURCATION_SELECT;
2318 DRM_DEBUG_KMS("disabling fdi C rx\n");
2319 I915_WRITE(SOUTH_CHICKEN1, temp);
2320 }
2321}
2322
8db9d77b
ZW		 2323/* The FDI link training functions for ILK/Ibexpeak. */
2324static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2325{
2326 struct drm_device *dev = crtc->dev;
2327 struct drm_i915_private *dev_priv = dev->dev_private;
2328 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2329 int pipe = intel_crtc->pipe;
0fc932b8 2330 int plane = intel_crtc->plane;
5eddb70b 2331 u32 reg, temp, tries;
8db9d77b 2332
0fc932b8
JB		 2333 /* FDI needs bits from pipe & plane first */
2334 assert_pipe_enabled(dev_priv, pipe);
2335 assert_plane_enabled(dev_priv, plane);
2336
e1a44743
AJ		 2337 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2338 for train result */
5eddb70b
CW		 2339 reg = FDI_RX_IMR(pipe);
2340 temp = I915_READ(reg);
e1a44743
AJ		 2341 temp &= ~FDI_RX_SYMBOL_LOCK;
2342 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2343 I915_WRITE(reg, temp);
2344 I915_READ(reg);
e1a44743
AJ		 2345 udelay(150);
2346
8db9d77b 2347 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2348 reg = FDI_TX_CTL(pipe);
2349 temp = I915_READ(reg);
627eb5a3
DV		 2350 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2351 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2352 temp &= ~FDI_LINK_TRAIN_NONE;
2353 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2354 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2355
5eddb70b
CW		 2356 reg = FDI_RX_CTL(pipe);
2357 temp = I915_READ(reg);
8db9d77b
ZW		 2358 temp &= ~FDI_LINK_TRAIN_NONE;
2359 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2360 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2361
2362 POSTING_READ(reg);
8db9d77b
ZW		 2363 udelay(150);
2364
5b2adf89 2365 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2366 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2367 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2368 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2369
5eddb70b 2370 reg = FDI_RX_IIR(pipe);
e1a44743 2371 for (tries = 0; tries < 5; tries++) {
5eddb70b 2372 temp = I915_READ(reg);
8db9d77b
ZW		 2373 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2374
2375 if ((temp & FDI_RX_BIT_LOCK)) {
2376 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2377 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2378 break;
2379 }
8db9d77b 2380 }
e1a44743 2381 if (tries == 5)
5eddb70b 2382 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2383
2384 /* Train 2 */
5eddb70b
CW		 2385 reg = FDI_TX_CTL(pipe);
2386 temp = I915_READ(reg);
8db9d77b
ZW		 2387 temp &= ~FDI_LINK_TRAIN_NONE;
2388 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2389 I915_WRITE(reg, temp);
8db9d77b 2390
5eddb70b
CW		 2391 reg = FDI_RX_CTL(pipe);
2392 temp = I915_READ(reg);
8db9d77b
ZW		 2393 temp &= ~FDI_LINK_TRAIN_NONE;
2394 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2395 I915_WRITE(reg, temp);
8db9d77b 2396
5eddb70b
CW		 2397 POSTING_READ(reg);
2398 udelay(150);
8db9d77b 2399
5eddb70b 2400 reg = FDI_RX_IIR(pipe);
e1a44743 2401 for (tries = 0; tries < 5; tries++) {
5eddb70b 2402 temp = I915_READ(reg);
8db9d77b
ZW		 2403 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2404
2405 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2406 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2407 DRM_DEBUG_KMS("FDI train 2 done.\n");
2408 break;
2409 }
8db9d77b 2410 }
e1a44743 2411 if (tries == 5)
5eddb70b 2412 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2413
2414 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2415
8db9d77b
ZW		 2416}
2417
0206e353 2418static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2419 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2420 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2421 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2422 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2423};
2424
2425/* The FDI link training functions for SNB/Cougarpoint. */
2426static void gen6_fdi_link_train(struct drm_crtc *crtc)
2427{
2428 struct drm_device *dev = crtc->dev;
2429 struct drm_i915_private *dev_priv = dev->dev_private;
2430 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2431 int pipe = intel_crtc->pipe;
fa37d39e 2432 u32 reg, temp, i, retry;
8db9d77b 2433
e1a44743
AJ		 2434 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2435 for train result */
5eddb70b
CW		 2436 reg = FDI_RX_IMR(pipe);
2437 temp = I915_READ(reg);
e1a44743
AJ		 2438 temp &= ~FDI_RX_SYMBOL_LOCK;
2439 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2440 I915_WRITE(reg, temp);
2441
2442 POSTING_READ(reg);
e1a44743
AJ		 2443 udelay(150);
2444
8db9d77b 2445 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2446 reg = FDI_TX_CTL(pipe);
2447 temp = I915_READ(reg);
627eb5a3
DV		 2448 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2449 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2450 temp &= ~FDI_LINK_TRAIN_NONE;
2451 temp |= FDI_LINK_TRAIN_PATTERN_1;
2452 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2453 /* SNB-B */
2454 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2455 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2456
d74cf324
DV		 2457 I915_WRITE(FDI_RX_MISC(pipe),
2458 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2459
5eddb70b
CW		 2460 reg = FDI_RX_CTL(pipe);
2461 temp = I915_READ(reg);
8db9d77b
ZW		 2462 if (HAS_PCH_CPT(dev)) {
2463 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2464 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2465 } else {
2466 temp &= ~FDI_LINK_TRAIN_NONE;
2467 temp |= FDI_LINK_TRAIN_PATTERN_1;
2468 }
5eddb70b
CW		 2469 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2470
2471 POSTING_READ(reg);
8db9d77b
ZW		 2472 udelay(150);
2473
0206e353 2474 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2475 reg = FDI_TX_CTL(pipe);
2476 temp = I915_READ(reg);
8db9d77b
ZW		 2477 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2478 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2479 I915_WRITE(reg, temp);
2480
2481 POSTING_READ(reg);
8db9d77b
ZW		 2482 udelay(500);
2483
fa37d39e
SP		 2484 for (retry = 0; retry < 5; retry++) {
2485 reg = FDI_RX_IIR(pipe);
2486 temp = I915_READ(reg);
2487 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2488 if (temp & FDI_RX_BIT_LOCK) {
2489 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2490 DRM_DEBUG_KMS("FDI train 1 done.\n");
2491 break;
2492 }
2493 udelay(50);
8db9d77b 2494 }
fa37d39e
SP		 2495 if (retry < 5)
2496 break;
8db9d77b
ZW		 2497 }
2498 if (i == 4)
5eddb70b 2499 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2500
2501 /* Train 2 */
5eddb70b
CW		 2502 reg = FDI_TX_CTL(pipe);
2503 temp = I915_READ(reg);
8db9d77b
ZW		 2504 temp &= ~FDI_LINK_TRAIN_NONE;
2505 temp |= FDI_LINK_TRAIN_PATTERN_2;
2506 if (IS_GEN6(dev)) {
2507 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2508 /* SNB-B */
2509 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2510 }
5eddb70b 2511 I915_WRITE(reg, temp);
8db9d77b 2512
5eddb70b
CW		 2513 reg = FDI_RX_CTL(pipe);
2514 temp = I915_READ(reg);
8db9d77b
ZW		 2515 if (HAS_PCH_CPT(dev)) {
2516 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2517 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2518 } else {
2519 temp &= ~FDI_LINK_TRAIN_NONE;
2520 temp |= FDI_LINK_TRAIN_PATTERN_2;
2521 }
5eddb70b
CW		 2522 I915_WRITE(reg, temp);
2523
2524 POSTING_READ(reg);
8db9d77b
ZW		 2525 udelay(150);
2526
0206e353 2527 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2528 reg = FDI_TX_CTL(pipe);
2529 temp = I915_READ(reg);
8db9d77b
ZW		 2530 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2531 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2532 I915_WRITE(reg, temp);
2533
2534 POSTING_READ(reg);
8db9d77b
ZW		 2535 udelay(500);
2536
fa37d39e
SP		 2537 for (retry = 0; retry < 5; retry++) {
2538 reg = FDI_RX_IIR(pipe);
2539 temp = I915_READ(reg);
2540 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2541 if (temp & FDI_RX_SYMBOL_LOCK) {
2542 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2543 DRM_DEBUG_KMS("FDI train 2 done.\n");
2544 break;
2545 }
2546 udelay(50);
8db9d77b 2547 }
fa37d39e
SP		 2548 if (retry < 5)
2549 break;
8db9d77b
ZW		 2550 }
2551 if (i == 4)
5eddb70b 2552 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2553
2554 DRM_DEBUG_KMS("FDI train done.\n");
2555}
2556
357555c0
JB		 2557/* Manual link training for Ivy Bridge A0 parts */
2558static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2559{
2560 struct drm_device *dev = crtc->dev;
2561 struct drm_i915_private *dev_priv = dev->dev_private;
2562 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2563 int pipe = intel_crtc->pipe;
2564 u32 reg, temp, i;
2565
2566 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2567 for train result */
2568 reg = FDI_RX_IMR(pipe);
2569 temp = I915_READ(reg);
2570 temp &= ~FDI_RX_SYMBOL_LOCK;
2571 temp &= ~FDI_RX_BIT_LOCK;
2572 I915_WRITE(reg, temp);
2573
2574 POSTING_READ(reg);
2575 udelay(150);
2576
01a415fd
DV		 2577 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2578 I915_READ(FDI_RX_IIR(pipe)));
2579
357555c0
JB		 2580 /* enable CPU FDI TX and PCH FDI RX */
2581 reg = FDI_TX_CTL(pipe);
2582 temp = I915_READ(reg);
627eb5a3
DV		 2583 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2584 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
357555c0
JB		 2585 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2586 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2587 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2588 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2589 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2590 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2591
d74cf324
DV		 2592 I915_WRITE(FDI_RX_MISC(pipe),
2593 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2594
357555c0
JB		 2595 reg = FDI_RX_CTL(pipe);
2596 temp = I915_READ(reg);
2597 temp &= ~FDI_LINK_TRAIN_AUTO;
2598 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2599 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2600 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2601 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2602
2603 POSTING_READ(reg);
2604 udelay(150);
2605
0206e353 2606 for (i = 0; i < 4; i++) {
357555c0
JB		 2607 reg = FDI_TX_CTL(pipe);
2608 temp = I915_READ(reg);
2609 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2610 temp |= snb_b_fdi_train_param[i];
2611 I915_WRITE(reg, temp);
2612
2613 POSTING_READ(reg);
2614 udelay(500);
2615
2616 reg = FDI_RX_IIR(pipe);
2617 temp = I915_READ(reg);
2618 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2619
2620 if (temp & FDI_RX_BIT_LOCK ||
2621 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2622 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2623 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2624 break;
2625 }
2626 }
2627 if (i == 4)
2628 DRM_ERROR("FDI train 1 fail!\n");
2629
2630 /* Train 2 */
2631 reg = FDI_TX_CTL(pipe);
2632 temp = I915_READ(reg);
2633 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2634 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2635 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2636 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2637 I915_WRITE(reg, temp);
2638
2639 reg = FDI_RX_CTL(pipe);
2640 temp = I915_READ(reg);
2641 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2642 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2643 I915_WRITE(reg, temp);
2644
2645 POSTING_READ(reg);
2646 udelay(150);
2647
0206e353 2648 for (i = 0; i < 4; i++) {
357555c0
JB		 2649 reg = FDI_TX_CTL(pipe);
2650 temp = I915_READ(reg);
2651 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2652 temp |= snb_b_fdi_train_param[i];
2653 I915_WRITE(reg, temp);
2654
2655 POSTING_READ(reg);
2656 udelay(500);
2657
2658 reg = FDI_RX_IIR(pipe);
2659 temp = I915_READ(reg);
2660 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2661
2662 if (temp & FDI_RX_SYMBOL_LOCK) {
2663 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2664 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2665 break;
2666 }
2667 }
2668 if (i == 4)
2669 DRM_ERROR("FDI train 2 fail!\n");
2670
2671 DRM_DEBUG_KMS("FDI train done.\n");
2672}
2673
88cefb6c 2674static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2675{
88cefb6c 2676 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2677 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2678 int pipe = intel_crtc->pipe;
5eddb70b 2679 u32 reg, temp;
79e53945 2680
c64e311e 2681
c98e9dcf 2682 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2683 reg = FDI_RX_CTL(pipe);
2684 temp = I915_READ(reg);
627eb5a3
DV		 2685 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2686 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2687 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2688 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2689
2690 POSTING_READ(reg);
c98e9dcf
JB		 2691 udelay(200);
2692
2693 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2694 temp = I915_READ(reg);
2695 I915_WRITE(reg, temp | FDI_PCDCLK);
2696
2697 POSTING_READ(reg);
c98e9dcf
JB		 2698 udelay(200);
2699
20749730
PZ		 2700 /* Enable CPU FDI TX PLL, always on for Ironlake */
2701 reg = FDI_TX_CTL(pipe);
2702 temp = I915_READ(reg);
2703 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2704 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2705
20749730
PZ		 2706 POSTING_READ(reg);
2707 udelay(100);
6be4a607 2708 }
0e23b99d
JB		 2709}
2710
88cefb6c
DV		 2711static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2712{
2713 struct drm_device *dev = intel_crtc->base.dev;
2714 struct drm_i915_private *dev_priv = dev->dev_private;
2715 int pipe = intel_crtc->pipe;
2716 u32 reg, temp;
2717
2718 /* Switch from PCDclk to Rawclk */
2719 reg = FDI_RX_CTL(pipe);
2720 temp = I915_READ(reg);
2721 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2722
2723 /* Disable CPU FDI TX PLL */
2724 reg = FDI_TX_CTL(pipe);
2725 temp = I915_READ(reg);
2726 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2727
2728 POSTING_READ(reg);
2729 udelay(100);
2730
2731 reg = FDI_RX_CTL(pipe);
2732 temp = I915_READ(reg);
2733 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2734
2735 /* Wait for the clocks to turn off. */
2736 POSTING_READ(reg);
2737 udelay(100);
2738}
2739
0fc932b8
JB		 2740static void ironlake_fdi_disable(struct drm_crtc *crtc)
2741{
2742 struct drm_device *dev = crtc->dev;
2743 struct drm_i915_private *dev_priv = dev->dev_private;
2744 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2745 int pipe = intel_crtc->pipe;
2746 u32 reg, temp;
2747
2748 /* disable CPU FDI tx and PCH FDI rx */
2749 reg = FDI_TX_CTL(pipe);
2750 temp = I915_READ(reg);
2751 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2752 POSTING_READ(reg);
2753
2754 reg = FDI_RX_CTL(pipe);
2755 temp = I915_READ(reg);
2756 temp &= ~(0x7 << 16);
dfd07d72 2757 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2758 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2759
2760 POSTING_READ(reg);
2761 udelay(100);
2762
2763 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2764 if (HAS_PCH_IBX(dev)) {
2765 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2766 }
0fc932b8
JB		 2767
2768 /* still set train pattern 1 */
2769 reg = FDI_TX_CTL(pipe);
2770 temp = I915_READ(reg);
2771 temp &= ~FDI_LINK_TRAIN_NONE;
2772 temp |= FDI_LINK_TRAIN_PATTERN_1;
2773 I915_WRITE(reg, temp);
2774
2775 reg = FDI_RX_CTL(pipe);
2776 temp = I915_READ(reg);
2777 if (HAS_PCH_CPT(dev)) {
2778 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2779 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2780 } else {
2781 temp &= ~FDI_LINK_TRAIN_NONE;
2782 temp |= FDI_LINK_TRAIN_PATTERN_1;
2783 }
2784 /* BPC in FDI rx is consistent with that in PIPECONF */
2785 temp &= ~(0x07 << 16);
dfd07d72 2786 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2787 I915_WRITE(reg, temp);
2788
2789 POSTING_READ(reg);
2790 udelay(100);
2791}
2792
5bb61643
CW		 2793static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2794{
2795 struct drm_device *dev = crtc->dev;
2796 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2797 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2798 unsigned long flags;
2799 bool pending;
2800
10d83730
VS		 2801 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2802 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2803 return false;
2804
2805 spin_lock_irqsave(&dev->event_lock, flags);
2806 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2807 spin_unlock_irqrestore(&dev->event_lock, flags);
2808
2809 return pending;
2810}
2811
e6c3a2a6
CW		 2812static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2813{
0f91128d 2814 struct drm_device *dev = crtc->dev;
5bb61643 2815 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2816
2817 if (crtc->fb == NULL)
2818 return;
2819
2c10d571
DV		 2820 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2821
5bb61643
CW		 2822 wait_event(dev_priv->pending_flip_queue,
2823 !intel_crtc_has_pending_flip(crtc));
2824
0f91128d
CW		 2825 mutex_lock(&dev->struct_mutex);
2826 intel_finish_fb(crtc->fb);
2827 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2828}
2829
e615efe4
ED		 2830/* Program iCLKIP clock to the desired frequency */
2831static void lpt_program_iclkip(struct drm_crtc *crtc)
2832{
2833 struct drm_device *dev = crtc->dev;
2834 struct drm_i915_private *dev_priv = dev->dev_private;
2835 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2836 u32 temp;
2837
09153000
DV		 2838 mutex_lock(&dev_priv->dpio_lock);
2839
e615efe4
ED		 2840 /* It is necessary to ungate the pixclk gate prior to programming
2841 * the divisors, and gate it back when it is done.
2842 */
2843 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2844
2845 /* Disable SSCCTL */
2846 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2847 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2848 SBI_SSCCTL_DISABLE,
2849 SBI_ICLK);
e615efe4
ED		 2850
2851 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2852 if (crtc->mode.clock == 20000) {
2853 auxdiv = 1;
2854 divsel = 0x41;
2855 phaseinc = 0x20;
2856 } else {
2857 /* The iCLK virtual clock root frequency is in MHz,
2858 * but the crtc->mode.clock in in KHz. To get the divisors,
2859 * it is necessary to divide one by another, so we
2860 * convert the virtual clock precision to KHz here for higher
2861 * precision.
2862 */
2863 u32 iclk_virtual_root_freq = 172800 * 1000;
2864 u32 iclk_pi_range = 64;
2865 u32 desired_divisor, msb_divisor_value, pi_value;
2866
2867 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2868 msb_divisor_value = desired_divisor / iclk_pi_range;
2869 pi_value = desired_divisor % iclk_pi_range;
2870
2871 auxdiv = 0;
2872 divsel = msb_divisor_value - 2;
2873 phaseinc = pi_value;
2874 }
2875
2876 /* This should not happen with any sane values */
2877 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2878 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2879 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2880 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2881
2882 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2883 crtc->mode.clock,
2884 auxdiv,
2885 divsel,
2886 phasedir,
2887 phaseinc);
2888
2889 /* Program SSCDIVINTPHASE6 */
988d6ee8 2890 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2891 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2892 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2893 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2894 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2895 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2896 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2897 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2898
2899 /* Program SSCAUXDIV */
988d6ee8 2900 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2901 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2902 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2903 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2904
2905 /* Enable modulator and associated divider */
988d6ee8 2906 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2907 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2908 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2909
2910 /* Wait for initialization time */
2911 udelay(24);
2912
2913 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2914
2915 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2916}
2917
275f01b2
DV		 2918static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2919 enum pipe pch_transcoder)
2920{
2921 struct drm_device *dev = crtc->base.dev;
2922 struct drm_i915_private *dev_priv = dev->dev_private;
2923 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2924
2925 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2926 I915_READ(HTOTAL(cpu_transcoder)));
2927 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2928 I915_READ(HBLANK(cpu_transcoder)));
2929 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2930 I915_READ(HSYNC(cpu_transcoder)));
2931
2932 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2933 I915_READ(VTOTAL(cpu_transcoder)));
2934 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2935 I915_READ(VBLANK(cpu_transcoder)));
2936 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2937 I915_READ(VSYNC(cpu_transcoder)));
2938 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2939 I915_READ(VSYNCSHIFT(cpu_transcoder)));
2940}
2941
f67a559d
JB		 2942/*
2943 * Enable PCH resources required for PCH ports:
2944 * - PCH PLLs
2945 * - FDI training & RX/TX
2946 * - update transcoder timings
2947 * - DP transcoding bits
2948 * - transcoder
2949 */
2950static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2951{
2952 struct drm_device *dev = crtc->dev;
2953 struct drm_i915_private *dev_priv = dev->dev_private;
2954 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2955 int pipe = intel_crtc->pipe;
ee7b9f93 2956 u32 reg, temp;
2c07245f 2957
ab9412ba 2958 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 2959
cd986abb
DV		 2960 /* Write the TU size bits before fdi link training, so that error
2961 * detection works. */
2962 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2963 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2964
c98e9dcf 2965 /* For PCH output, training FDI link */
674cf967 2966 dev_priv->display.fdi_link_train(crtc);
2c07245f 2967
572deb37
DV		 2968 /* XXX: pch pll's can be enabled any time before we enable the PCH
2969 * transcoder, and we actually should do this to not upset any PCH
2970 * transcoder that already use the clock when we share it.
2971 *
e72f9fbf
DV		 2972 * Note that enable_shared_dpll tries to do the right thing, but
2973 * get_shared_dpll unconditionally resets the pll - we need that to have
2974 * the right LVDS enable sequence. */
2975 ironlake_enable_shared_dpll(intel_crtc);
6f13b7b5 2976
303b81e0 2977 if (HAS_PCH_CPT(dev)) {
ee7b9f93 2978 u32 sel;
4b645f14 2979
c98e9dcf 2980 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 2981 temp |= TRANS_DPLL_ENABLE(pipe);
2982 sel = TRANS_DPLLB_SEL(pipe);
a43f6e0f 2983 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 2984 temp |= sel;
2985 else
2986 temp &= ~sel;
c98e9dcf 2987 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2988 }
5eddb70b 2989
d9b6cb56
JB		 2990 /* set transcoder timing, panel must allow it */
2991 assert_panel_unlocked(dev_priv, pipe);
275f01b2 2992 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 2993
303b81e0 2994 intel_fdi_normal_train(crtc);
5e84e1a4 2995
c98e9dcf
JB		 2996 /* For PCH DP, enable TRANS_DP_CTL */
2997 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 2998 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2999 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3000 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3001 reg = TRANS_DP_CTL(pipe);
3002 temp = I915_READ(reg);
3003 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3004 TRANS_DP_SYNC_MASK |
3005 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3006 temp |= (TRANS_DP_OUTPUT_ENABLE |
3007 TRANS_DP_ENH_FRAMING);
9325c9f0 3008 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3009
3010 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3011 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3012 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3013 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3014
3015 switch (intel_trans_dp_port_sel(crtc)) {
3016 case PCH_DP_B:
5eddb70b 3017 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3018 break;
3019 case PCH_DP_C:
5eddb70b 3020 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3021 break;
3022 case PCH_DP_D:
5eddb70b 3023 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3024 break;
3025 default:
e95d41e1 3026 BUG();
32f9d658 3027 }
2c07245f 3028
5eddb70b 3029 I915_WRITE(reg, temp);
6be4a607 3030 }
b52eb4dc 3031
b8a4f404 3032 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3033}
3034
1507e5bd
PZ		 3035static void lpt_pch_enable(struct drm_crtc *crtc)
3036{
3037 struct drm_device *dev = crtc->dev;
3038 struct drm_i915_private *dev_priv = dev->dev_private;
3039 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3040 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3041
ab9412ba 3042 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3043
8c52b5e8 3044 lpt_program_iclkip(crtc);
1507e5bd 3045
0540e488 3046 /* Set transcoder timing. */
275f01b2 3047 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3048
937bb610 3049 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3050}
3051
e2b78267 3052static void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3053{
e2b78267 3054 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 3055
3056 if (pll == NULL)
3057 return;
3058
3059 if (pll->refcount == 0) {
46edb027 3060 WARN(1, "bad %s refcount\n", pll->name);
ee7b9f93
JB		 3061 return;
3062 }
3063
f4a091c7
DV		 3064 if (--pll->refcount == 0) {
3065 WARN_ON(pll->on);
3066 WARN_ON(pll->active);
3067 }
3068
a43f6e0f 3069 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 3070}
3071
b89a1d39 3072static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3073{
e2b78267
DV		 3074 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3075 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3076 enum intel_dpll_id i;
ee7b9f93 3077
ee7b9f93 3078 if (pll) {
46edb027
DV		 3079 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3080 crtc->base.base.id, pll->name);
e2b78267 3081 intel_put_shared_dpll(crtc);
ee7b9f93
JB		 3082 }
3083
98b6bd99
DV		 3084 if (HAS_PCH_IBX(dev_priv->dev)) {
3085 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
e2b78267 3086 i = crtc->pipe;
e72f9fbf 3087 pll = &dev_priv->shared_dplls[i];
98b6bd99 3088
46edb027
DV		 3089 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3090 crtc->base.base.id, pll->name);
98b6bd99
DV		 3091
3092 goto found;
3093 }
3094
e72f9fbf
DV		 3095 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3096 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 3097
3098 /* Only want to check enabled timings first */
3099 if (pll->refcount == 0)
3100 continue;
3101
b89a1d39
DV		 3102 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3103 sizeof(pll->hw_state)) == 0) {
46edb027 3104 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
e2b78267 3105 crtc->base.base.id,
46edb027 3106 pll->name, pll->refcount, pll->active);
ee7b9f93
JB		 3107
3108 goto found;
3109 }
3110 }
3111
3112 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 3113 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3114 pll = &dev_priv->shared_dplls[i];
ee7b9f93 3115 if (pll->refcount == 0) {
46edb027
DV		 3116 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3117 crtc->base.base.id, pll->name);
ee7b9f93
JB		 3118 goto found;
3119 }
3120 }
3121
3122 return NULL;
3123
3124found:
a43f6e0f 3125 crtc->config.shared_dpll = i;
46edb027
DV		 3126 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3127 pipe_name(crtc->pipe));
ee7b9f93 3128
cdbd2316 3129 if (pll->active == 0) {
66e985c0
DV		 3130 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3131 sizeof(pll->hw_state));
3132
46edb027 3133 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
cdbd2316 3134 WARN_ON(pll->on);
e9d6944e 3135 assert_shared_dpll_disabled(dev_priv, pll);
ee7b9f93 3136
15bdd4cf 3137 pll->mode_set(dev_priv, pll);
cdbd2316
DV		 3138 }
3139 pll->refcount++;
e04c7350 3140
ee7b9f93
JB		 3141 return pll;
3142}
3143
a1520318 3144static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3145{
3146 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3147 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3148 u32 temp;
3149
3150 temp = I915_READ(dslreg);
3151 udelay(500);
3152 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3153 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3154 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3155 }
3156}
3157
b074cec8
JB		 3158static void ironlake_pfit_enable(struct intel_crtc *crtc)
3159{
3160 struct drm_device *dev = crtc->base.dev;
3161 struct drm_i915_private *dev_priv = dev->dev_private;
3162 int pipe = crtc->pipe;
3163
0ef37f3f 3164 if (crtc->config.pch_pfit.size) {
b074cec8
JB		 3165 /* Force use of hard-coded filter coefficients
3166 * as some pre-programmed values are broken,
3167 * e.g. x201.
3168 */
3169 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3170 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3171 PF_PIPE_SEL_IVB(pipe));
3172 else
3173 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3174 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3175 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
d4270e57
JB		 3176 }
3177}
3178
bb53d4ae
VS		 3179static void intel_enable_planes(struct drm_crtc *crtc)
3180{
3181 struct drm_device *dev = crtc->dev;
3182 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3183 struct intel_plane *intel_plane;
3184
3185 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3186 if (intel_plane->pipe == pipe)
3187 intel_plane_restore(&intel_plane->base);
3188}
3189
3190static void intel_disable_planes(struct drm_crtc *crtc)
3191{
3192 struct drm_device *dev = crtc->dev;
3193 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3194 struct intel_plane *intel_plane;
3195
3196 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3197 if (intel_plane->pipe == pipe)
3198 intel_plane_disable(&intel_plane->base);
3199}
3200
f67a559d
JB		 3201static void ironlake_crtc_enable(struct drm_crtc *crtc)
3202{
3203 struct drm_device *dev = crtc->dev;
3204 struct drm_i915_private *dev_priv = dev->dev_private;
3205 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3206 struct intel_encoder *encoder;
f67a559d
JB		 3207 int pipe = intel_crtc->pipe;
3208 int plane = intel_crtc->plane;
f67a559d 3209
08a48469
DV		 3210 WARN_ON(!crtc->enabled);
3211
f67a559d
JB		 3212 if (intel_crtc->active)
3213 return;
3214
3215 intel_crtc->active = true;
8664281b
PZ		 3216
3217 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3218 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3219
f67a559d
JB		 3220 intel_update_watermarks(dev);
3221
f6736a1a 3222 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 3223 if (encoder->pre_enable)
3224 encoder->pre_enable(encoder);
f67a559d 3225
5bfe2ac0 3226 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3227 /* Note: FDI PLL enabling _must_ be done before we enable the
3228 * cpu pipes, hence this is separate from all the other fdi/pch
3229 * enabling. */
88cefb6c 3230 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3231 } else {
3232 assert_fdi_tx_disabled(dev_priv, pipe);
3233 assert_fdi_rx_disabled(dev_priv, pipe);
3234 }
f67a559d 3235
b074cec8 3236 ironlake_pfit_enable(intel_crtc);
f67a559d 3237
9c54c0dd
JB		 3238 /*
3239 * On ILK+ LUT must be loaded before the pipe is running but with
3240 * clocks enabled
3241 */
3242 intel_crtc_load_lut(crtc);
3243
5bfe2ac0
DV		 3244 intel_enable_pipe(dev_priv, pipe,
3245 intel_crtc->config.has_pch_encoder);
f67a559d 3246 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3247 intel_enable_planes(crtc);
5c38d48c 3248 intel_crtc_update_cursor(crtc, true);
f67a559d 3249
5bfe2ac0 3250 if (intel_crtc->config.has_pch_encoder)
f67a559d 3251 ironlake_pch_enable(crtc);
c98e9dcf 3252
d1ebd816 3253 mutex_lock(&dev->struct_mutex);
bed4a673 3254 intel_update_fbc(dev);
d1ebd816
BW		 3255 mutex_unlock(&dev->struct_mutex);
3256
fa5c73b1
DV		 3257 for_each_encoder_on_crtc(dev, crtc, encoder)
3258 encoder->enable(encoder);
61b77ddd
DV		 3259
3260 if (HAS_PCH_CPT(dev))
a1520318 3261 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3262
3263 /*
3264 * There seems to be a race in PCH platform hw (at least on some
3265 * outputs) where an enabled pipe still completes any pageflip right
3266 * away (as if the pipe is off) instead of waiting for vblank. As soon
3267 * as the first vblank happend, everything works as expected. Hence just
3268 * wait for one vblank before returning to avoid strange things
3269 * happening.
3270 */
3271 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3272}
3273
42db64ef
PZ		 3274/* IPS only exists on ULT machines and is tied to pipe A. */
3275static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3276{
f5adf94e 3277 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 3278}
3279
3280static void hsw_enable_ips(struct intel_crtc *crtc)
3281{
3282 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3283
3284 if (!crtc->config.ips_enabled)
3285 return;
3286
3287 /* We can only enable IPS after we enable a plane and wait for a vblank.
3288 * We guarantee that the plane is enabled by calling intel_enable_ips
3289 * only after intel_enable_plane. And intel_enable_plane already waits
3290 * for a vblank, so all we need to do here is to enable the IPS bit. */
3291 assert_plane_enabled(dev_priv, crtc->plane);
3292 I915_WRITE(IPS_CTL, IPS_ENABLE);
3293}
3294
3295static void hsw_disable_ips(struct intel_crtc *crtc)
3296{
3297 struct drm_device *dev = crtc->base.dev;
3298 struct drm_i915_private *dev_priv = dev->dev_private;
3299
3300 if (!crtc->config.ips_enabled)
3301 return;
3302
3303 assert_plane_enabled(dev_priv, crtc->plane);
3304 I915_WRITE(IPS_CTL, 0);
3305
3306 /* We need to wait for a vblank before we can disable the plane. */
3307 intel_wait_for_vblank(dev, crtc->pipe);
3308}
3309
4f771f10
PZ		 3310static void haswell_crtc_enable(struct drm_crtc *crtc)
3311{
3312 struct drm_device *dev = crtc->dev;
3313 struct drm_i915_private *dev_priv = dev->dev_private;
3314 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3315 struct intel_encoder *encoder;
3316 int pipe = intel_crtc->pipe;
3317 int plane = intel_crtc->plane;
4f771f10
PZ		 3318
3319 WARN_ON(!crtc->enabled);
3320
3321 if (intel_crtc->active)
3322 return;
3323
3324 intel_crtc->active = true;
8664281b
PZ		 3325
3326 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3327 if (intel_crtc->config.has_pch_encoder)
3328 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3329
4f771f10
PZ		 3330 intel_update_watermarks(dev);
3331
5bfe2ac0 3332 if (intel_crtc->config.has_pch_encoder)
04945641 3333 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3334
3335 for_each_encoder_on_crtc(dev, crtc, encoder)
3336 if (encoder->pre_enable)
3337 encoder->pre_enable(encoder);
3338
1f544388 3339 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3340
b074cec8 3341 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3342
3343 /*
3344 * On ILK+ LUT must be loaded before the pipe is running but with
3345 * clocks enabled
3346 */
3347 intel_crtc_load_lut(crtc);
3348
1f544388 3349 intel_ddi_set_pipe_settings(crtc);
8228c251 3350 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3351
5bfe2ac0
DV		 3352 intel_enable_pipe(dev_priv, pipe,
3353 intel_crtc->config.has_pch_encoder);
4f771f10 3354 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3355 intel_enable_planes(crtc);
5c38d48c 3356 intel_crtc_update_cursor(crtc, true);
4f771f10 3357
42db64ef
PZ		 3358 hsw_enable_ips(intel_crtc);
3359
5bfe2ac0 3360 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3361 lpt_pch_enable(crtc);
4f771f10
PZ		 3362
3363 mutex_lock(&dev->struct_mutex);
3364 intel_update_fbc(dev);
3365 mutex_unlock(&dev->struct_mutex);
3366
4f771f10
PZ		 3367 for_each_encoder_on_crtc(dev, crtc, encoder)
3368 encoder->enable(encoder);
3369
4f771f10
PZ		 3370 /*
3371 * There seems to be a race in PCH platform hw (at least on some
3372 * outputs) where an enabled pipe still completes any pageflip right
3373 * away (as if the pipe is off) instead of waiting for vblank. As soon
3374 * as the first vblank happend, everything works as expected. Hence just
3375 * wait for one vblank before returning to avoid strange things
3376 * happening.
3377 */
3378 intel_wait_for_vblank(dev, intel_crtc->pipe);
3379}
3380
3f8dce3a
DV		 3381static void ironlake_pfit_disable(struct intel_crtc *crtc)
3382{
3383 struct drm_device *dev = crtc->base.dev;
3384 struct drm_i915_private *dev_priv = dev->dev_private;
3385 int pipe = crtc->pipe;
3386
3387 /* To avoid upsetting the power well on haswell only disable the pfit if
3388 * it's in use. The hw state code will make sure we get this right. */
3389 if (crtc->config.pch_pfit.size) {
3390 I915_WRITE(PF_CTL(pipe), 0);
3391 I915_WRITE(PF_WIN_POS(pipe), 0);
3392 I915_WRITE(PF_WIN_SZ(pipe), 0);
3393 }
3394}
3395
6be4a607
JB		 3396static void ironlake_crtc_disable(struct drm_crtc *crtc)
3397{
3398 struct drm_device *dev = crtc->dev;
3399 struct drm_i915_private *dev_priv = dev->dev_private;
3400 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3401 struct intel_encoder *encoder;
6be4a607
JB		 3402 int pipe = intel_crtc->pipe;
3403 int plane = intel_crtc->plane;
5eddb70b 3404 u32 reg, temp;
b52eb4dc 3405
ef9c3aee 3406
f7abfe8b
CW		 3407 if (!intel_crtc->active)
3408 return;
3409
ea9d758d
DV		 3410 for_each_encoder_on_crtc(dev, crtc, encoder)
3411 encoder->disable(encoder);
3412
e6c3a2a6 3413 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3414 drm_vblank_off(dev, pipe);
913d8d11 3415
5c3fe8b0 3416 if (dev_priv->fbc.plane == plane)
973d04f9 3417 intel_disable_fbc(dev);
2c07245f 3418
0d5b8c61 3419 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3420 intel_disable_planes(crtc);
0d5b8c61
VS		 3421 intel_disable_plane(dev_priv, plane, pipe);
3422
d925c59a
DV		 3423 if (intel_crtc->config.has_pch_encoder)
3424 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3425
b24e7179 3426 intel_disable_pipe(dev_priv, pipe);
32f9d658 3427
3f8dce3a 3428 ironlake_pfit_disable(intel_crtc);
2c07245f 3429
bf49ec8c
DV		 3430 for_each_encoder_on_crtc(dev, crtc, encoder)
3431 if (encoder->post_disable)
3432 encoder->post_disable(encoder);
2c07245f 3433
d925c59a
DV		 3434 if (intel_crtc->config.has_pch_encoder) {
3435 ironlake_fdi_disable(crtc);
913d8d11 3436
d925c59a
DV		 3437 ironlake_disable_pch_transcoder(dev_priv, pipe);
3438 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
6be4a607 3439
d925c59a
DV		 3440 if (HAS_PCH_CPT(dev)) {
3441 /* disable TRANS_DP_CTL */
3442 reg = TRANS_DP_CTL(pipe);
3443 temp = I915_READ(reg);
3444 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3445 TRANS_DP_PORT_SEL_MASK);
3446 temp |= TRANS_DP_PORT_SEL_NONE;
3447 I915_WRITE(reg, temp);
3448
3449 /* disable DPLL_SEL */
3450 temp = I915_READ(PCH_DPLL_SEL);
11887397 3451 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 3452 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 3453 }
e3421a18 3454
d925c59a 3455 /* disable PCH DPLL */
e72f9fbf 3456 intel_disable_shared_dpll(intel_crtc);
8db9d77b 3457
d925c59a
DV		 3458 ironlake_fdi_pll_disable(intel_crtc);
3459 }
6b383a7f 3460
f7abfe8b 3461 intel_crtc->active = false;
6b383a7f 3462 intel_update_watermarks(dev);
d1ebd816
BW		 3463
3464 mutex_lock(&dev->struct_mutex);
6b383a7f 3465 intel_update_fbc(dev);
d1ebd816 3466 mutex_unlock(&dev->struct_mutex);
6be4a607 3467}
1b3c7a47 3468
4f771f10 3469static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3470{
4f771f10
PZ		 3471 struct drm_device *dev = crtc->dev;
3472 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3473 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3474 struct intel_encoder *encoder;
3475 int pipe = intel_crtc->pipe;
3476 int plane = intel_crtc->plane;
3b117c8f 3477 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3478
4f771f10
PZ		 3479 if (!intel_crtc->active)
3480 return;
3481
3482 for_each_encoder_on_crtc(dev, crtc, encoder)
3483 encoder->disable(encoder);
3484
3485 intel_crtc_wait_for_pending_flips(crtc);
3486 drm_vblank_off(dev, pipe);
4f771f10 3487
891348b2 3488 /* FBC must be disabled before disabling the plane on HSW. */
5c3fe8b0 3489 if (dev_priv->fbc.plane == plane)
4f771f10
PZ		 3490 intel_disable_fbc(dev);
3491
42db64ef
PZ		 3492 hsw_disable_ips(intel_crtc);
3493
0d5b8c61 3494 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3495 intel_disable_planes(crtc);
891348b2
RV		 3496 intel_disable_plane(dev_priv, plane, pipe);
3497
8664281b
PZ		 3498 if (intel_crtc->config.has_pch_encoder)
3499 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3500 intel_disable_pipe(dev_priv, pipe);
3501
ad80a810 3502 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3503
3f8dce3a 3504 ironlake_pfit_disable(intel_crtc);
4f771f10 3505
1f544388 3506 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3507
3508 for_each_encoder_on_crtc(dev, crtc, encoder)
3509 if (encoder->post_disable)
3510 encoder->post_disable(encoder);
3511
88adfff1 3512 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3513 lpt_disable_pch_transcoder(dev_priv);
8664281b 3514 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3515 intel_ddi_fdi_disable(crtc);
83616634 3516 }
4f771f10
PZ		 3517
3518 intel_crtc->active = false;
3519 intel_update_watermarks(dev);
3520
3521 mutex_lock(&dev->struct_mutex);
3522 intel_update_fbc(dev);
3523 mutex_unlock(&dev->struct_mutex);
3524}
3525
ee7b9f93
JB		 3526static void ironlake_crtc_off(struct drm_crtc *crtc)
3527{
3528 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 3529 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 3530}
3531
6441ab5f
PZ		 3532static void haswell_crtc_off(struct drm_crtc *crtc)
3533{
3534 intel_ddi_put_crtc_pll(crtc);
3535}
3536
02e792fb
DV		 3537static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3538{
02e792fb 3539 if (!enable && intel_crtc->overlay) {
23f09ce3 3540 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3541 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3542
23f09ce3 3543 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3544 dev_priv->mm.interruptible = false;
3545 (void) intel_overlay_switch_off(intel_crtc->overlay);
3546 dev_priv->mm.interruptible = true;
23f09ce3 3547 mutex_unlock(&dev->struct_mutex);
02e792fb 3548 }
02e792fb 3549
5dcdbcb0
CW		 3550 /* Let userspace switch the overlay on again. In most cases userspace
3551 * has to recompute where to put it anyway.
3552 */
02e792fb
DV		 3553}
3554
61bc95c1
EE		 3555/**
3556 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3557 * cursor plane briefly if not already running after enabling the display
3558 * plane.
3559 * This workaround avoids occasional blank screens when self refresh is
3560 * enabled.
3561 */
3562static void
3563g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3564{
3565 u32 cntl = I915_READ(CURCNTR(pipe));
3566
3567 if ((cntl & CURSOR_MODE) == 0) {
3568 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3569
3570 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3571 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3572 intel_wait_for_vblank(dev_priv->dev, pipe);
3573 I915_WRITE(CURCNTR(pipe), cntl);
3574 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3575 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3576 }
3577}
3578
2dd24552
JB		 3579static void i9xx_pfit_enable(struct intel_crtc *crtc)
3580{
3581 struct drm_device *dev = crtc->base.dev;
3582 struct drm_i915_private *dev_priv = dev->dev_private;
3583 struct intel_crtc_config *pipe_config = &crtc->config;
3584
328d8e82 3585 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3586 return;
3587
2dd24552 3588 /*
c0b03411
DV		 3589 * The panel fitter should only be adjusted whilst the pipe is disabled,
3590 * according to register description and PRM.
2dd24552 3591 */
c0b03411
DV		 3592 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3593 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3594
b074cec8
JB		 3595 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3596 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3597
3598 /* Border color in case we don't scale up to the full screen. Black by
3599 * default, change to something else for debugging. */
3600 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3601}
3602
89b667f8
JB		 3603static void valleyview_crtc_enable(struct drm_crtc *crtc)
3604{
3605 struct drm_device *dev = crtc->dev;
3606 struct drm_i915_private *dev_priv = dev->dev_private;
3607 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3608 struct intel_encoder *encoder;
3609 int pipe = intel_crtc->pipe;
3610 int plane = intel_crtc->plane;
3611
3612 WARN_ON(!crtc->enabled);
3613
3614 if (intel_crtc->active)
3615 return;
3616
3617 intel_crtc->active = true;
3618 intel_update_watermarks(dev);
3619
3620 mutex_lock(&dev_priv->dpio_lock);
3621
3622 for_each_encoder_on_crtc(dev, crtc, encoder)
3623 if (encoder->pre_pll_enable)
3624 encoder->pre_pll_enable(encoder);
3625
87442f73 3626 vlv_enable_pll(dev_priv, pipe);
89b667f8
JB		 3627
3628 for_each_encoder_on_crtc(dev, crtc, encoder)
3629 if (encoder->pre_enable)
3630 encoder->pre_enable(encoder);
3631
3632 /* VLV wants encoder enabling _before_ the pipe is up. */
3633 for_each_encoder_on_crtc(dev, crtc, encoder)
3634 encoder->enable(encoder);
3635
2dd24552
JB		 3636 i9xx_pfit_enable(intel_crtc);
3637
63cbb074
VS		 3638 intel_crtc_load_lut(crtc);
3639
89b667f8
JB		 3640 intel_enable_pipe(dev_priv, pipe, false);
3641 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3642 intel_enable_planes(crtc);
5c38d48c 3643 intel_crtc_update_cursor(crtc, true);
89b667f8 3644
89b667f8
JB		 3645 intel_update_fbc(dev);
3646
89b667f8
JB		 3647 mutex_unlock(&dev_priv->dpio_lock);
3648}
3649
0b8765c6 3650static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3651{
3652 struct drm_device *dev = crtc->dev;
79e53945
JB		 3653 struct drm_i915_private *dev_priv = dev->dev_private;
3654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3655 struct intel_encoder *encoder;
79e53945 3656 int pipe = intel_crtc->pipe;
80824003 3657 int plane = intel_crtc->plane;
79e53945 3658
08a48469
DV		 3659 WARN_ON(!crtc->enabled);
3660
f7abfe8b
CW		 3661 if (intel_crtc->active)
3662 return;
3663
3664 intel_crtc->active = true;
6b383a7f
CW		 3665 intel_update_watermarks(dev);
3666
9d6d9f19
MK		 3667 for_each_encoder_on_crtc(dev, crtc, encoder)
3668 if (encoder->pre_enable)
3669 encoder->pre_enable(encoder);
3670
f6736a1a
DV		 3671 i9xx_enable_pll(intel_crtc);
3672
2dd24552
JB		 3673 i9xx_pfit_enable(intel_crtc);
3674
63cbb074
VS		 3675 intel_crtc_load_lut(crtc);
3676
040484af 3677 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3678 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3679 intel_enable_planes(crtc);
22e407d7 3680 /* The fixup needs to happen before cursor is enabled */
61bc95c1
EE		 3681 if (IS_G4X(dev))
3682 g4x_fixup_plane(dev_priv, pipe);
22e407d7 3683 intel_crtc_update_cursor(crtc, true);
79e53945 3684
0b8765c6
JB		 3685 /* Give the overlay scaler a chance to enable if it's on this pipe */
3686 intel_crtc_dpms_overlay(intel_crtc, true);
ef9c3aee 3687
f440eb13 3688 intel_update_fbc(dev);
ef9c3aee 3689
fa5c73b1
DV		 3690 for_each_encoder_on_crtc(dev, crtc, encoder)
3691 encoder->enable(encoder);
0b8765c6 3692}
79e53945 3693
87476d63
DV		 3694static void i9xx_pfit_disable(struct intel_crtc *crtc)
3695{
3696 struct drm_device *dev = crtc->base.dev;
3697 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3698
328d8e82
DV		 3699 if (!crtc->config.gmch_pfit.control)
3700 return;
87476d63 3701
328d8e82 3702 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3703
328d8e82
DV		 3704 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3705 I915_READ(PFIT_CONTROL));
3706 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3707}
3708
0b8765c6
JB		 3709static void i9xx_crtc_disable(struct drm_crtc *crtc)
3710{
3711 struct drm_device *dev = crtc->dev;
3712 struct drm_i915_private *dev_priv = dev->dev_private;
3713 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3714 struct intel_encoder *encoder;
0b8765c6
JB		 3715 int pipe = intel_crtc->pipe;
3716 int plane = intel_crtc->plane;
ef9c3aee 3717
f7abfe8b
CW		 3718 if (!intel_crtc->active)
3719 return;
3720
ea9d758d
DV		 3721 for_each_encoder_on_crtc(dev, crtc, encoder)
3722 encoder->disable(encoder);
3723
0b8765c6 3724 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3725 intel_crtc_wait_for_pending_flips(crtc);
3726 drm_vblank_off(dev, pipe);
0b8765c6 3727
5c3fe8b0 3728 if (dev_priv->fbc.plane == plane)
973d04f9 3729 intel_disable_fbc(dev);
79e53945 3730
0d5b8c61
VS		 3731 intel_crtc_dpms_overlay(intel_crtc, false);
3732 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3733 intel_disable_planes(crtc);
b24e7179 3734 intel_disable_plane(dev_priv, plane, pipe);
0d5b8c61 3735
b24e7179 3736 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3737
87476d63 3738 i9xx_pfit_disable(intel_crtc);
24a1f16d 3739
89b667f8
JB		 3740 for_each_encoder_on_crtc(dev, crtc, encoder)
3741 if (encoder->post_disable)
3742 encoder->post_disable(encoder);
3743
63d7bbe9 3744 intel_disable_pll(dev_priv, pipe);
0b8765c6 3745
f7abfe8b 3746 intel_crtc->active = false;
6b383a7f
CW		 3747 intel_update_fbc(dev);
3748 intel_update_watermarks(dev);
0b8765c6
JB		 3749}
3750
ee7b9f93
JB		 3751static void i9xx_crtc_off(struct drm_crtc *crtc)
3752{
3753}
3754
976f8a20
DV		 3755static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3756 bool enabled)
2c07245f
ZW		 3757{
3758 struct drm_device *dev = crtc->dev;
3759 struct drm_i915_master_private *master_priv;
3760 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3761 int pipe = intel_crtc->pipe;
79e53945
JB		 3762
3763 if (!dev->primary->master)
3764 return;
3765
3766 master_priv = dev->primary->master->driver_priv;
3767 if (!master_priv->sarea_priv)
3768 return;
3769
79e53945
JB		 3770 switch (pipe) {
3771 case 0:
3772 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3773 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3774 break;
3775 case 1:
3776 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3777 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3778 break;
3779 default:
9db4a9c7 3780 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3781 break;
3782 }
79e53945
JB		 3783}
3784
976f8a20
DV		 3785/**
3786 * Sets the power management mode of the pipe and plane.
3787 */
3788void intel_crtc_update_dpms(struct drm_crtc *crtc)
3789{
3790 struct drm_device *dev = crtc->dev;
3791 struct drm_i915_private *dev_priv = dev->dev_private;
3792 struct intel_encoder *intel_encoder;
3793 bool enable = false;
3794
3795 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3796 enable |= intel_encoder->connectors_active;
3797
3798 if (enable)
3799 dev_priv->display.crtc_enable(crtc);
3800 else
3801 dev_priv->display.crtc_disable(crtc);
3802
3803 intel_crtc_update_sarea(crtc, enable);
3804}
3805
cdd59983
CW		 3806static void intel_crtc_disable(struct drm_crtc *crtc)
3807{
cdd59983 3808 struct drm_device *dev = crtc->dev;
976f8a20 3809 struct drm_connector *connector;
ee7b9f93 3810 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3811 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3812
976f8a20
DV		 3813 /* crtc should still be enabled when we disable it. */
3814 WARN_ON(!crtc->enabled);
3815
3816 dev_priv->display.crtc_disable(crtc);
c77bf565 3817 intel_crtc->eld_vld = false;
976f8a20 3818 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3819 dev_priv->display.off(crtc);
3820
931872fc
CW		 3821 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3822 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3823
3824 if (crtc->fb) {
3825 mutex_lock(&dev->struct_mutex);
1690e1eb 3826 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3827 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3828 crtc->fb = NULL;
3829 }
3830
3831 /* Update computed state. */
3832 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3833 if (!connector->encoder || !connector->encoder->crtc)
3834 continue;
3835
3836 if (connector->encoder->crtc != crtc)
3837 continue;
3838
3839 connector->dpms = DRM_MODE_DPMS_OFF;
3840 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3841 }
3842}
3843
a261b246 3844void intel_modeset_disable(struct drm_device *dev)
79e53945 3845{
a261b246
DV		 3846 struct drm_crtc *crtc;
3847
3848 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3849 if (crtc->enabled)
3850 intel_crtc_disable(crtc);
3851 }
79e53945
JB		 3852}
3853
ea5b213a 3854void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3855{
4ef69c7a 3856 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3857
ea5b213a
CW		 3858 drm_encoder_cleanup(encoder);
3859 kfree(intel_encoder);
7e7d76c3
JB		 3860}
3861
5ab432ef
DV		 3862/* Simple dpms helper for encodres with just one connector, no cloning and only
3863 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3864 * state of the entire output pipe. */
3865void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3866{
5ab432ef
DV		 3867 if (mode == DRM_MODE_DPMS_ON) {
3868 encoder->connectors_active = true;
3869
b2cabb0e 3870 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3871 } else {
3872 encoder->connectors_active = false;
3873
b2cabb0e 3874 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3875 }
79e53945
JB		 3876}
3877
0a91ca29
DV		 3878/* Cross check the actual hw state with our own modeset state tracking (and it's
3879 * internal consistency). */
b980514c 3880static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3881{
0a91ca29
DV		 3882 if (connector->get_hw_state(connector)) {
3883 struct intel_encoder *encoder = connector->encoder;
3884 struct drm_crtc *crtc;
3885 bool encoder_enabled;
3886 enum pipe pipe;
3887
3888 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3889 connector->base.base.id,
3890 drm_get_connector_name(&connector->base));
3891
3892 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3893 "wrong connector dpms state\n");
3894 WARN(connector->base.encoder != &encoder->base,
3895 "active connector not linked to encoder\n");
3896 WARN(!encoder->connectors_active,
3897 "encoder->connectors_active not set\n");
3898
3899 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3900 WARN(!encoder_enabled, "encoder not enabled\n");
3901 if (WARN_ON(!encoder->base.crtc))
3902 return;
3903
3904 crtc = encoder->base.crtc;
3905
3906 WARN(!crtc->enabled, "crtc not enabled\n");
3907 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3908 WARN(pipe != to_intel_crtc(crtc)->pipe,
3909 "encoder active on the wrong pipe\n");
3910 }
79e53945
JB		 3911}
3912
5ab432ef
DV		 3913/* Even simpler default implementation, if there's really no special case to
3914 * consider. */
3915void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3916{
5ab432ef 3917 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3918
5ab432ef
DV		 3919 /* All the simple cases only support two dpms states. */
3920 if (mode != DRM_MODE_DPMS_ON)
3921 mode = DRM_MODE_DPMS_OFF;
d4270e57 3922
5ab432ef
DV		 3923 if (mode == connector->dpms)
3924 return;
3925
3926 connector->dpms = mode;
3927
3928 /* Only need to change hw state when actually enabled */
3929 if (encoder->base.crtc)
3930 intel_encoder_dpms(encoder, mode);
3931 else
8af6cf88 3932 WARN_ON(encoder->connectors_active != false);
0a91ca29 3933
b980514c 3934 intel_modeset_check_state(connector->dev);
79e53945
JB		 3935}
3936
f0947c37
DV		 3937/* Simple connector->get_hw_state implementation for encoders that support only
3938 * one connector and no cloning and hence the encoder state determines the state
3939 * of the connector. */
3940bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3941{
24929352 3942 enum pipe pipe = 0;
f0947c37 3943 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3944
f0947c37 3945 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3946}
3947
1857e1da
DV		 3948static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3949 struct intel_crtc_config *pipe_config)
3950{
3951 struct drm_i915_private *dev_priv = dev->dev_private;
3952 struct intel_crtc *pipe_B_crtc =
3953 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3954
3955 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3956 pipe_name(pipe), pipe_config->fdi_lanes);
3957 if (pipe_config->fdi_lanes > 4) {
3958 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3959 pipe_name(pipe), pipe_config->fdi_lanes);
3960 return false;
3961 }
3962
3963 if (IS_HASWELL(dev)) {
3964 if (pipe_config->fdi_lanes > 2) {
3965 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3966 pipe_config->fdi_lanes);
3967 return false;
3968 } else {
3969 return true;
3970 }
3971 }
3972
3973 if (INTEL_INFO(dev)->num_pipes == 2)
3974 return true;
3975
3976 /* Ivybridge 3 pipe is really complicated */
3977 switch (pipe) {
3978 case PIPE_A:
3979 return true;
3980 case PIPE_B:
3981 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
3982 pipe_config->fdi_lanes > 2) {
3983 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3984 pipe_name(pipe), pipe_config->fdi_lanes);
3985 return false;
3986 }
3987 return true;
3988 case PIPE_C:
1e833f40 3989 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 3990 pipe_B_crtc->config.fdi_lanes <= 2) {
3991 if (pipe_config->fdi_lanes > 2) {
3992 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3993 pipe_name(pipe), pipe_config->fdi_lanes);
3994 return false;
3995 }
3996 } else {
3997 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
3998 return false;
3999 }
4000 return true;
4001 default:
4002 BUG();
4003 }
4004}
4005
e29c22c0
DV		 4006#define RETRY 1
4007static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4008 struct intel_crtc_config *pipe_config)
877d48d5 4009{
1857e1da 4010 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 4011 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 4012 int lane, link_bw, fdi_dotclock;
e29c22c0 4013 bool setup_ok, needs_recompute = false;
877d48d5 4014
e29c22c0 4015retry:
877d48d5
DV		 4016 /* FDI is a binary signal running at ~2.7GHz, encoding
4017 * each output octet as 10 bits. The actual frequency
4018 * is stored as a divider into a 100MHz clock, and the
4019 * mode pixel clock is stored in units of 1KHz.
4020 * Hence the bw of each lane in terms of the mode signal
4021 * is:
4022 */
4023 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4024
ff9a6750 4025 fdi_dotclock = adjusted_mode->clock;
ef1b460d 4026 fdi_dotclock /= pipe_config->pixel_multiplier;
877d48d5 4027
2bd89a07 4028 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 4029 pipe_config->pipe_bpp);
4030
4031 pipe_config->fdi_lanes = lane;
4032
2bd89a07 4033 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4034 link_bw, &pipe_config->fdi_m_n);
1857e1da 4035
e29c22c0
DV		 4036 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4037 intel_crtc->pipe, pipe_config);
4038 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4039 pipe_config->pipe_bpp -= 2*3;
4040 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4041 pipe_config->pipe_bpp);
4042 needs_recompute = true;
4043 pipe_config->bw_constrained = true;
4044
4045 goto retry;
4046 }
4047
4048 if (needs_recompute)
4049 return RETRY;
4050
4051 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4052}
4053
42db64ef
PZ		 4054static void hsw_compute_ips_config(struct intel_crtc *crtc,
4055 struct intel_crtc_config *pipe_config)
4056{
3c4ca58c
PZ		 4057 pipe_config->ips_enabled = i915_enable_ips &&
4058 hsw_crtc_supports_ips(crtc) &&
42db64ef
PZ		 4059 pipe_config->pipe_bpp == 24;
4060}
4061
a43f6e0f 4062static int intel_crtc_compute_config(struct intel_crtc *crtc,
e29c22c0 4063 struct intel_crtc_config *pipe_config)
79e53945 4064{
a43f6e0f 4065 struct drm_device *dev = crtc->base.dev;
b8cecdf5 4066 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4067
bad720ff 4068 if (HAS_PCH_SPLIT(dev)) {
2c07245f 4069 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 4070 if (pipe_config->requested_mode.clock * 3
4071 > IRONLAKE_FDI_FREQ * 4)
e29c22c0 4072 return -EINVAL;
2c07245f 4073 }
89749350 4074
f9bef081
DV		 4075 /* All interlaced capable intel hw wants timings in frames. Note though
4076 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4077 * timings, so we need to be careful not to clobber these.*/
7ae89233 4078 if (!pipe_config->timings_set)
f9bef081 4079 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 4080
8693a824
DL		 4081 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4082 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4083 */
4084 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4085 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4086 return -EINVAL;
44f46b42 4087
bd080ee5 4088 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4089 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4090 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4091 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4092 * for lvds. */
4093 pipe_config->pipe_bpp = 8*3;
4094 }
4095
f5adf94e 4096 if (HAS_IPS(dev))
a43f6e0f
DV		 4097 hsw_compute_ips_config(crtc, pipe_config);
4098
4099 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4100 * clock survives for now. */
4101 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4102 pipe_config->shared_dpll = crtc->config.shared_dpll;
42db64ef 4103
877d48d5 4104 if (pipe_config->has_pch_encoder)
a43f6e0f 4105 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 4106
e29c22c0 4107 return 0;
79e53945
JB		 4108}
4109
25eb05fc
JB		 4110static int valleyview_get_display_clock_speed(struct drm_device *dev)
4111{
4112 return 400000; /* FIXME */
4113}
4114
e70236a8
JB		 4115static int i945_get_display_clock_speed(struct drm_device *dev)
4116{
4117 return 400000;
4118}
79e53945 4119
e70236a8 4120static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4121{
e70236a8
JB		 4122 return 333000;
4123}
79e53945 4124
e70236a8
JB		 4125static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4126{
4127 return 200000;
4128}
79e53945 4129
e70236a8
JB		 4130static int i915gm_get_display_clock_speed(struct drm_device *dev)
4131{
4132 u16 gcfgc = 0;
79e53945 4133
e70236a8
JB		 4134 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4135
4136 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4137 return 133000;
4138 else {
4139 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4140 case GC_DISPLAY_CLOCK_333_MHZ:
4141 return 333000;
4142 default:
4143 case GC_DISPLAY_CLOCK_190_200_MHZ:
4144 return 190000;
79e53945 4145 }
e70236a8
JB		 4146 }
4147}
4148
4149static int i865_get_display_clock_speed(struct drm_device *dev)
4150{
4151 return 266000;
4152}
4153
4154static int i855_get_display_clock_speed(struct drm_device *dev)
4155{
4156 u16 hpllcc = 0;
4157 /* Assume that the hardware is in the high speed state. This
4158 * should be the default.
4159 */
4160 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4161 case GC_CLOCK_133_200:
4162 case GC_CLOCK_100_200:
4163 return 200000;
4164 case GC_CLOCK_166_250:
4165 return 250000;
4166 case GC_CLOCK_100_133:
79e53945 4167 return 133000;
e70236a8 4168 }
79e53945 4169
e70236a8
JB		 4170 /* Shouldn't happen */
4171 return 0;
4172}
79e53945 4173
e70236a8
JB		 4174static int i830_get_display_clock_speed(struct drm_device *dev)
4175{
4176 return 133000;
79e53945
JB		 4177}
4178
2c07245f 4179static void
a65851af 4180intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4181{
a65851af
VS		 4182 while (*num > DATA_LINK_M_N_MASK ||
4183 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4184 *num >>= 1;
4185 *den >>= 1;
4186 }
4187}
4188
a65851af
VS		 4189static void compute_m_n(unsigned int m, unsigned int n,
4190 uint32_t *ret_m, uint32_t *ret_n)
4191{
4192 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4193 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4194 intel_reduce_m_n_ratio(ret_m, ret_n);
4195}
4196
e69d0bc1
DV		 4197void
4198intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4199 int pixel_clock, int link_clock,
4200 struct intel_link_m_n *m_n)
2c07245f 4201{
e69d0bc1 4202 m_n->tu = 64;
a65851af
VS		 4203
4204 compute_m_n(bits_per_pixel * pixel_clock,
4205 link_clock * nlanes * 8,
4206 &m_n->gmch_m, &m_n->gmch_n);
4207
4208 compute_m_n(pixel_clock, link_clock,
4209 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4210}
4211
a7615030
CW		 4212static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4213{
72bbe58c
KP		 4214 if (i915_panel_use_ssc >= 0)
4215 return i915_panel_use_ssc != 0;
41aa3448 4216 return dev_priv->vbt.lvds_use_ssc
435793df 4217 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4218}
4219
a0c4da24
JB		 4220static int vlv_get_refclk(struct drm_crtc *crtc)
4221{
4222 struct drm_device *dev = crtc->dev;
4223 struct drm_i915_private *dev_priv = dev->dev_private;
4224 int refclk = 27000; /* for DP & HDMI */
4225
4226 return 100000; /* only one validated so far */
4227
4228 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4229 refclk = 96000;
4230 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4231 if (intel_panel_use_ssc(dev_priv))
4232 refclk = 100000;
4233 else
4234 refclk = 96000;
4235 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4236 refclk = 100000;
4237 }
4238
4239 return refclk;
4240}
4241
c65d77d8
JB		 4242static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4243{
4244 struct drm_device *dev = crtc->dev;
4245 struct drm_i915_private *dev_priv = dev->dev_private;
4246 int refclk;
4247
a0c4da24
JB		 4248 if (IS_VALLEYVIEW(dev)) {
4249 refclk = vlv_get_refclk(crtc);
4250 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4251 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4252 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4253 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4254 refclk / 1000);
4255 } else if (!IS_GEN2(dev)) {
4256 refclk = 96000;
4257 } else {
4258 refclk = 48000;
4259 }
4260
4261 return refclk;
4262}
4263
7429e9d4 4264static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 4265{
7df00d7a 4266 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 4267}
f47709a9 4268
7429e9d4
DV		 4269static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4270{
4271 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 4272}
4273
f47709a9 4274static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4275 intel_clock_t *reduced_clock)
4276{
f47709a9 4277 struct drm_device *dev = crtc->base.dev;
a7516a05 4278 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4279 int pipe = crtc->pipe;
a7516a05
JB		 4280 u32 fp, fp2 = 0;
4281
4282 if (IS_PINEVIEW(dev)) {
7429e9d4 4283 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4284 if (reduced_clock)
7429e9d4 4285 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4286 } else {
7429e9d4 4287 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4288 if (reduced_clock)
7429e9d4 4289 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4290 }
4291
4292 I915_WRITE(FP0(pipe), fp);
8bcc2795 4293 crtc->config.dpll_hw_state.fp0 = fp;
a7516a05 4294
f47709a9
DV		 4295 crtc->lowfreq_avail = false;
4296 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4297 reduced_clock && i915_powersave) {
4298 I915_WRITE(FP1(pipe), fp2);
8bcc2795 4299 crtc->config.dpll_hw_state.fp1 = fp2;
f47709a9 4300 crtc->lowfreq_avail = true;
a7516a05
JB		 4301 } else {
4302 I915_WRITE(FP1(pipe), fp);
8bcc2795 4303 crtc->config.dpll_hw_state.fp1 = fp;
a7516a05
JB		 4304 }
4305}
4306
89b667f8
JB		 4307static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4308{
4309 u32 reg_val;
4310
4311 /*
4312 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4313 * and set it to a reasonable value instead.
4314 */
ae99258f 4315 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8
JB		 4316 reg_val &= 0xffffff00;
4317 reg_val |= 0x00000030;
ae99258f 4318 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4319
ae99258f 4320 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4321 reg_val &= 0x8cffffff;
4322 reg_val = 0x8c000000;
ae99258f 4323 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8 4324
ae99258f 4325 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8 4326 reg_val &= 0xffffff00;
ae99258f 4327 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4328
ae99258f 4329 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4330 reg_val &= 0x00ffffff;
4331 reg_val |= 0xb0000000;
ae99258f 4332 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4333}
4334
b551842d
DV		 4335static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4336 struct intel_link_m_n *m_n)
4337{
4338 struct drm_device *dev = crtc->base.dev;
4339 struct drm_i915_private *dev_priv = dev->dev_private;
4340 int pipe = crtc->pipe;
4341
e3b95f1e
DV		 4342 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4343 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4344 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4345 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4346}
4347
4348static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4349 struct intel_link_m_n *m_n)
4350{
4351 struct drm_device *dev = crtc->base.dev;
4352 struct drm_i915_private *dev_priv = dev->dev_private;
4353 int pipe = crtc->pipe;
4354 enum transcoder transcoder = crtc->config.cpu_transcoder;
4355
4356 if (INTEL_INFO(dev)->gen >= 5) {
4357 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4358 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4359 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4360 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4361 } else {
e3b95f1e
DV		 4362 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4363 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4364 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4365 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4366 }
4367}
4368
03afc4a2
DV		 4369static void intel_dp_set_m_n(struct intel_crtc *crtc)
4370{
4371 if (crtc->config.has_pch_encoder)
4372 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4373 else
4374 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4375}
4376
f47709a9 4377static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4378{
f47709a9 4379 struct drm_device *dev = crtc->base.dev;
a0c4da24 4380 struct drm_i915_private *dev_priv = dev->dev_private;
89b667f8 4381 struct intel_encoder *encoder;
f47709a9 4382 int pipe = crtc->pipe;
89b667f8 4383 u32 dpll, mdiv;
a0c4da24 4384 u32 bestn, bestm1, bestm2, bestp1, bestp2;
89b667f8 4385 bool is_hdmi;
198a037f 4386 u32 coreclk, reg_val, dpll_md;
a0c4da24 4387
09153000
DV		 4388 mutex_lock(&dev_priv->dpio_lock);
4389
89b667f8 4390 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
a0c4da24 4391
f47709a9
DV		 4392 bestn = crtc->config.dpll.n;
4393 bestm1 = crtc->config.dpll.m1;
4394 bestm2 = crtc->config.dpll.m2;
4395 bestp1 = crtc->config.dpll.p1;
4396 bestp2 = crtc->config.dpll.p2;
a0c4da24 4397
89b667f8
JB		 4398 /* See eDP HDMI DPIO driver vbios notes doc */
4399
4400 /* PLL B needs special handling */
4401 if (pipe)
4402 vlv_pllb_recal_opamp(dev_priv);
4403
4404 /* Set up Tx target for periodic Rcomp update */
ae99258f 4405 vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4406
4407 /* Disable target IRef on PLL */
ae99258f 4408 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
89b667f8 4409 reg_val &= 0x00ffffff;
ae99258f 4410 vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4411
4412 /* Disable fast lock */
ae99258f 4413 vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4414
4415 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4416 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4417 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4418 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4419 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4420
4421 /*
4422 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4423 * but we don't support that).
4424 * Note: don't use the DAC post divider as it seems unstable.
4425 */
4426 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ae99258f 4427 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4428
a0c4da24 4429 mdiv |= DPIO_ENABLE_CALIBRATION;
ae99258f 4430 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4431
89b667f8 4432 /* Set HBR and RBR LPF coefficients */
ff9a6750 4433 if (crtc->config.port_clock == 162000 ||
99750bd4 4434 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
89b667f8 4435 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4abb2c39 4436 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
89b667f8
JB		 4437 0x005f0021);
4438 else
4abb2c39 4439 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
89b667f8
JB		 4440 0x00d0000f);
4441
4442 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4443 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4444 /* Use SSC source */
4445 if (!pipe)
ae99258f 4446 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4447 0x0df40000);
4448 else
ae99258f 4449 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4450 0x0df70000);
4451 } else { /* HDMI or VGA */
4452 /* Use bend source */
4453 if (!pipe)
ae99258f 4454 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4455 0x0df70000);
4456 else
ae99258f 4457 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4458 0x0df40000);
4459 }
a0c4da24 4460
ae99258f 4461 coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4462 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4463 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4464 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4465 coreclk |= 0x01000000;
ae99258f 4466 vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4467
ae99258f 4468 vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4469
89b667f8
JB		 4470 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4471 if (encoder->pre_pll_enable)
4472 encoder->pre_pll_enable(encoder);
a0c4da24 4473
89b667f8
JB		 4474 /* Enable DPIO clock input */
4475 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4476 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4477 if (pipe)
4478 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
a0c4da24
JB		 4479
4480 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4481 crtc->config.dpll_hw_state.dpll = dpll;
4482
a0c4da24
JB		 4483 I915_WRITE(DPLL(pipe), dpll);
4484 POSTING_READ(DPLL(pipe));
2a8f64ca 4485 udelay(150);
a0c4da24 4486
a0c4da24
JB		 4487 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4488 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4489
ef1b460d
DV		 4490 dpll_md = (crtc->config.pixel_multiplier - 1)
4491 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795
DV		 4492 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4493
198a037f 4494 I915_WRITE(DPLL_MD(pipe), dpll_md);
2a8f64ca 4495 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4496
89b667f8
JB		 4497 if (crtc->config.has_dp_encoder)
4498 intel_dp_set_m_n(crtc);
09153000
DV		 4499
4500 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4501}
4502
f47709a9
DV		 4503static void i9xx_update_pll(struct intel_crtc *crtc,
4504 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4505 int num_connectors)
4506{
f47709a9 4507 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4508 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 4509 u32 dpll;
4510 bool is_sdvo;
f47709a9 4511 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4512
f47709a9 4513 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4514
f47709a9
DV		 4515 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4516 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4517
4518 dpll = DPLL_VGA_MODE_DIS;
4519
f47709a9 4520 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4521 dpll |= DPLLB_MODE_LVDS;
4522 else
4523 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4524
ef1b460d 4525 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
198a037f
DV		 4526 dpll |= (crtc->config.pixel_multiplier - 1)
4527 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4528 }
198a037f
DV		 4529
4530 if (is_sdvo)
4531 dpll |= DPLL_DVO_HIGH_SPEED;
4532
f47709a9 4533 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
eb1cbe48
DV		 4534 dpll |= DPLL_DVO_HIGH_SPEED;
4535
4536 /* compute bitmask from p1 value */
4537 if (IS_PINEVIEW(dev))
4538 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4539 else {
4540 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4541 if (IS_G4X(dev) && reduced_clock)
4542 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4543 }
4544 switch (clock->p2) {
4545 case 5:
4546 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4547 break;
4548 case 7:
4549 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4550 break;
4551 case 10:
4552 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4553 break;
4554 case 14:
4555 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4556 break;
4557 }
4558 if (INTEL_INFO(dev)->gen >= 4)
4559 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4560
09ede541 4561 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4562 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4563 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4564 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4565 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4566 else
4567 dpll |= PLL_REF_INPUT_DREFCLK;
4568
4569 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4570 crtc->config.dpll_hw_state.dpll = dpll;
4571
eb1cbe48 4572 if (INTEL_INFO(dev)->gen >= 4) {
ef1b460d
DV		 4573 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4574 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795 4575 crtc->config.dpll_hw_state.dpll_md = dpll_md;
eb1cbe48 4576 }
66e3d5c0
DV		 4577
4578 if (crtc->config.has_dp_encoder)
4579 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4580}
4581
f47709a9 4582static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 4583 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4584 int num_connectors)
4585{
f47709a9 4586 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4587 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 4588 u32 dpll;
f47709a9 4589 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4590
f47709a9 4591 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4592
eb1cbe48
DV		 4593 dpll = DPLL_VGA_MODE_DIS;
4594
f47709a9 4595 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4596 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4597 } else {
4598 if (clock->p1 == 2)
4599 dpll |= PLL_P1_DIVIDE_BY_TWO;
4600 else
4601 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4602 if (clock->p2 == 4)
4603 dpll |= PLL_P2_DIVIDE_BY_4;
4604 }
4605
f47709a9 4606 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4607 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4608 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4609 else
4610 dpll |= PLL_REF_INPUT_DREFCLK;
4611
4612 dpll |= DPLL_VCO_ENABLE;
8bcc2795 4613 crtc->config.dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 4614}
4615
8a654f3b 4616static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 4617{
4618 struct drm_device *dev = intel_crtc->base.dev;
4619 struct drm_i915_private *dev_priv = dev->dev_private;
4620 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4621 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV		 4622 struct drm_display_mode *adjusted_mode =
4623 &intel_crtc->config.adjusted_mode;
4624 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4d8a62ea
DV		 4625 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4626
4627 /* We need to be careful not to changed the adjusted mode, for otherwise
4628 * the hw state checker will get angry at the mismatch. */
4629 crtc_vtotal = adjusted_mode->crtc_vtotal;
4630 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4631
4632 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4633 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4634 crtc_vtotal -= 1;
4635 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4636 vsyncshift = adjusted_mode->crtc_hsync_start
4637 - adjusted_mode->crtc_htotal / 2;
4638 } else {
4639 vsyncshift = 0;
4640 }
4641
4642 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4643 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4644
fe2b8f9d 4645 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4646 (adjusted_mode->crtc_hdisplay - 1) |
4647 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4648 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4649 (adjusted_mode->crtc_hblank_start - 1) |
4650 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4651 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4652 (adjusted_mode->crtc_hsync_start - 1) |
4653 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4654
fe2b8f9d 4655 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4656 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4657 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4658 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4659 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4660 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4661 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4662 (adjusted_mode->crtc_vsync_start - 1) |
4663 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4664
b5e508d4
PZ		 4665 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4666 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4667 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4668 * bits. */
4669 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4670 (pipe == PIPE_B || pipe == PIPE_C))
4671 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4672
b0e77b9c
PZ		 4673 /* pipesrc controls the size that is scaled from, which should
4674 * always be the user's requested size.
4675 */
4676 I915_WRITE(PIPESRC(pipe),
4677 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4678}
4679
1bd1bd80
DV		 4680static void intel_get_pipe_timings(struct intel_crtc *crtc,
4681 struct intel_crtc_config *pipe_config)
4682{
4683 struct drm_device *dev = crtc->base.dev;
4684 struct drm_i915_private *dev_priv = dev->dev_private;
4685 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4686 uint32_t tmp;
4687
4688 tmp = I915_READ(HTOTAL(cpu_transcoder));
4689 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4690 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4691 tmp = I915_READ(HBLANK(cpu_transcoder));
4692 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4693 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4694 tmp = I915_READ(HSYNC(cpu_transcoder));
4695 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4696 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4697
4698 tmp = I915_READ(VTOTAL(cpu_transcoder));
4699 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4700 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4701 tmp = I915_READ(VBLANK(cpu_transcoder));
4702 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4703 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4704 tmp = I915_READ(VSYNC(cpu_transcoder));
4705 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4706 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4707
4708 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4709 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4710 pipe_config->adjusted_mode.crtc_vtotal += 1;
4711 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4712 }
4713
4714 tmp = I915_READ(PIPESRC(crtc->pipe));
4715 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4716 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4717}
4718
84b046f3
DV		 4719static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4720{
4721 struct drm_device *dev = intel_crtc->base.dev;
4722 struct drm_i915_private *dev_priv = dev->dev_private;
4723 uint32_t pipeconf;
4724
9f11a9e4 4725 pipeconf = 0;
84b046f3
DV		 4726
4727 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4728 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4729 * core speed.
4730 *
4731 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4732 * pipe == 0 check?
4733 */
4734 if (intel_crtc->config.requested_mode.clock >
4735 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4736 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3
DV		 4737 }
4738
ff9ce46e
DV		 4739 /* only g4x and later have fancy bpc/dither controls */
4740 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e
DV		 4741 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4742 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4743 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4744 PIPECONF_DITHER_TYPE_SP;
84b046f3 4745
ff9ce46e
DV		 4746 switch (intel_crtc->config.pipe_bpp) {
4747 case 18:
4748 pipeconf |= PIPECONF_6BPC;
4749 break;
4750 case 24:
4751 pipeconf |= PIPECONF_8BPC;
4752 break;
4753 case 30:
4754 pipeconf |= PIPECONF_10BPC;
4755 break;
4756 default:
4757 /* Case prevented by intel_choose_pipe_bpp_dither. */
4758 BUG();
84b046f3
DV		 4759 }
4760 }
4761
4762 if (HAS_PIPE_CXSR(dev)) {
4763 if (intel_crtc->lowfreq_avail) {
4764 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4765 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4766 } else {
4767 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 4768 }
4769 }
4770
84b046f3
DV		 4771 if (!IS_GEN2(dev) &&
4772 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4773 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4774 else
4775 pipeconf |= PIPECONF_PROGRESSIVE;
4776
9f11a9e4
DV		 4777 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4778 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 4779
84b046f3
DV		 4780 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4781 POSTING_READ(PIPECONF(intel_crtc->pipe));
4782}
4783
f564048e 4784static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4785 int x, int y,
94352cf9 4786 struct drm_framebuffer *fb)
79e53945
JB		 4787{
4788 struct drm_device *dev = crtc->dev;
4789 struct drm_i915_private *dev_priv = dev->dev_private;
4790 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 4791 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4792 int pipe = intel_crtc->pipe;
80824003 4793 int plane = intel_crtc->plane;
c751ce4f 4794 int refclk, num_connectors = 0;
652c393a 4795 intel_clock_t clock, reduced_clock;
84b046f3 4796 u32 dspcntr;
a16af721
DV		 4797 bool ok, has_reduced_clock = false;
4798 bool is_lvds = false;
5eddb70b 4799 struct intel_encoder *encoder;
d4906093 4800 const intel_limit_t *limit;
5c3b82e2 4801 int ret;
79e53945 4802
6c2b7c12 4803 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4804 switch (encoder->type) {
79e53945
JB		 4805 case INTEL_OUTPUT_LVDS:
4806 is_lvds = true;
4807 break;
79e53945 4808 }
43565a06 4809
c751ce4f 4810 num_connectors++;
79e53945
JB		 4811 }
4812
c65d77d8 4813 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4814
d4906093
ML		 4815 /*
4816 * Returns a set of divisors for the desired target clock with the given
4817 * refclk, or FALSE. The returned values represent the clock equation:
4818 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4819 */
1b894b59 4820 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 4821 ok = dev_priv->display.find_dpll(limit, crtc,
4822 intel_crtc->config.port_clock,
ee9300bb
DV		 4823 refclk, NULL, &clock);
4824 if (!ok && !intel_crtc->config.clock_set) {
79e53945 4825 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4826 return -EINVAL;
79e53945
JB		 4827 }
4828
cda4b7d3 4829 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4830 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4831
ddc9003c 4832 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4833 /*
4834 * Ensure we match the reduced clock's P to the target clock.
4835 * If the clocks don't match, we can't switch the display clock
4836 * by using the FP0/FP1. In such case we will disable the LVDS
4837 * downclock feature.
4838 */
ee9300bb
DV		 4839 has_reduced_clock =
4840 dev_priv->display.find_dpll(limit, crtc,
5eddb70b 4841 dev_priv->lvds_downclock,
ee9300bb 4842 refclk, &clock,
5eddb70b 4843 &reduced_clock);
7026d4ac 4844 }
f47709a9
DV		 4845 /* Compat-code for transition, will disappear. */
4846 if (!intel_crtc->config.clock_set) {
4847 intel_crtc->config.dpll.n = clock.n;
4848 intel_crtc->config.dpll.m1 = clock.m1;
4849 intel_crtc->config.dpll.m2 = clock.m2;
4850 intel_crtc->config.dpll.p1 = clock.p1;
4851 intel_crtc->config.dpll.p2 = clock.p2;
4852 }
7026d4ac 4853
eb1cbe48 4854 if (IS_GEN2(dev))
8a654f3b 4855 i8xx_update_pll(intel_crtc,
2a8f64ca
VP		 4856 has_reduced_clock ? &reduced_clock : NULL,
4857 num_connectors);
a0c4da24 4858 else if (IS_VALLEYVIEW(dev))
f47709a9 4859 vlv_update_pll(intel_crtc);
79e53945 4860 else
f47709a9 4861 i9xx_update_pll(intel_crtc,
eb1cbe48 4862 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4863 num_connectors);
79e53945 4864
79e53945
JB		 4865 /* Set up the display plane register */
4866 dspcntr = DISPPLANE_GAMMA_ENABLE;
4867
da6ecc5d
JB		 4868 if (!IS_VALLEYVIEW(dev)) {
4869 if (pipe == 0)
4870 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4871 else
4872 dspcntr |= DISPPLANE_SEL_PIPE_B;
4873 }
79e53945 4874
8a654f3b 4875 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW		 4876
4877 /* pipesrc and dspsize control the size that is scaled from,
4878 * which should always be the user's requested size.
79e53945 4879 */
929c77fb
EA		 4880 I915_WRITE(DSPSIZE(plane),
4881 ((mode->vdisplay - 1) << 16) |
4882 (mode->hdisplay - 1));
4883 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4884
84b046f3
DV		 4885 i9xx_set_pipeconf(intel_crtc);
4886
f564048e
EA		 4887 I915_WRITE(DSPCNTR(plane), dspcntr);
4888 POSTING_READ(DSPCNTR(plane));
4889
94352cf9 4890 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4891
4892 intel_update_watermarks(dev);
4893
f564048e
EA		 4894 return ret;
4895}
4896
2fa2fe9a
DV		 4897static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4898 struct intel_crtc_config *pipe_config)
4899{
4900 struct drm_device *dev = crtc->base.dev;
4901 struct drm_i915_private *dev_priv = dev->dev_private;
4902 uint32_t tmp;
4903
4904 tmp = I915_READ(PFIT_CONTROL);
4905
4906 if (INTEL_INFO(dev)->gen < 4) {
4907 if (crtc->pipe != PIPE_B)
4908 return;
4909
4910 /* gen2/3 store dither state in pfit control, needs to match */
4911 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
4912 } else {
4913 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4914 return;
4915 }
4916
4917 if (!(tmp & PFIT_ENABLE))
4918 return;
4919
4920 pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
4921 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4922 if (INTEL_INFO(dev)->gen < 5)
4923 pipe_config->gmch_pfit.lvds_border_bits =
4924 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4925}
4926
0e8ffe1b
DV		 4927static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4928 struct intel_crtc_config *pipe_config)
4929{
4930 struct drm_device *dev = crtc->base.dev;
4931 struct drm_i915_private *dev_priv = dev->dev_private;
4932 uint32_t tmp;
4933
eccb140b 4934 pipe_config->cpu_transcoder = crtc->pipe;
c0d43d62 4935 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 4936
0e8ffe1b
DV		 4937 tmp = I915_READ(PIPECONF(crtc->pipe));
4938 if (!(tmp & PIPECONF_ENABLE))
4939 return false;
4940
1bd1bd80
DV		 4941 intel_get_pipe_timings(crtc, pipe_config);
4942
2fa2fe9a
DV		 4943 i9xx_get_pfit_config(crtc, pipe_config);
4944
6c49f241
DV		 4945 if (INTEL_INFO(dev)->gen >= 4) {
4946 tmp = I915_READ(DPLL_MD(crtc->pipe));
4947 pipe_config->pixel_multiplier =
4948 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
4949 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 4950 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 4951 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4952 tmp = I915_READ(DPLL(crtc->pipe));
4953 pipe_config->pixel_multiplier =
4954 ((tmp & SDVO_MULTIPLIER_MASK)
4955 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
4956 } else {
4957 /* Note that on i915G/GM the pixel multiplier is in the sdvo
4958 * port and will be fixed up in the encoder->get_config
4959 * function. */
4960 pipe_config->pixel_multiplier = 1;
4961 }
8bcc2795
DV		 4962 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
4963 if (!IS_VALLEYVIEW(dev)) {
4964 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
4965 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 4966 } else {
4967 /* Mask out read-only status bits. */
4968 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
4969 DPLL_PORTC_READY_MASK |
4970 DPLL_PORTB_READY_MASK);
8bcc2795 4971 }
6c49f241 4972
0e8ffe1b
DV		 4973 return true;
4974}
4975
dde86e2d 4976static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4977{
4978 struct drm_i915_private *dev_priv = dev->dev_private;
4979 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4980 struct intel_encoder *encoder;
74cfd7ac 4981 u32 val, final;
13d83a67 4982 bool has_lvds = false;
199e5d79 4983 bool has_cpu_edp = false;
199e5d79 4984 bool has_panel = false;
99eb6a01
KP		 4985 bool has_ck505 = false;
4986 bool can_ssc = false;
13d83a67
JB		 4987
4988 /* We need to take the global config into account */
199e5d79
KP		 4989 list_for_each_entry(encoder, &mode_config->encoder_list,
4990 base.head) {
4991 switch (encoder->type) {
4992 case INTEL_OUTPUT_LVDS:
4993 has_panel = true;
4994 has_lvds = true;
4995 break;
4996 case INTEL_OUTPUT_EDP:
4997 has_panel = true;
2de6905f 4998 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 4999 has_cpu_edp = true;
5000 break;
13d83a67
JB		 5001 }
5002 }
5003
99eb6a01 5004 if (HAS_PCH_IBX(dev)) {
41aa3448 5005 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5006 can_ssc = has_ck505;
5007 } else {
5008 has_ck505 = false;
5009 can_ssc = true;
5010 }
5011
2de6905f
ID		 5012 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5013 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5014
5015 /* Ironlake: try to setup display ref clock before DPLL
5016 * enabling. This is only under driver's control after
5017 * PCH B stepping, previous chipset stepping should be
5018 * ignoring this setting.
5019 */
74cfd7ac
CW		 5020 val = I915_READ(PCH_DREF_CONTROL);
5021
5022 /* As we must carefully and slowly disable/enable each source in turn,
5023 * compute the final state we want first and check if we need to
5024 * make any changes at all.
5025 */
5026 final = val;
5027 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5028 if (has_ck505)
5029 final |= DREF_NONSPREAD_CK505_ENABLE;
5030 else
5031 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5032
5033 final &= ~DREF_SSC_SOURCE_MASK;
5034 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5035 final &= ~DREF_SSC1_ENABLE;
5036
5037 if (has_panel) {
5038 final |= DREF_SSC_SOURCE_ENABLE;
5039
5040 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5041 final |= DREF_SSC1_ENABLE;
5042
5043 if (has_cpu_edp) {
5044 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5045 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5046 else
5047 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5048 } else
5049 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5050 } else {
5051 final |= DREF_SSC_SOURCE_DISABLE;
5052 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5053 }
5054
5055 if (final == val)
5056 return;
5057
13d83a67 5058 /* Always enable nonspread source */
74cfd7ac 5059 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5060
99eb6a01 5061 if (has_ck505)
74cfd7ac 5062 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5063 else
74cfd7ac 5064 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5065
199e5d79 5066 if (has_panel) {
74cfd7ac
CW		 5067 val &= ~DREF_SSC_SOURCE_MASK;
5068 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5069
199e5d79 5070 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5071 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5072 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5073 val |= DREF_SSC1_ENABLE;
e77166b5 5074 } else
74cfd7ac 5075 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5076
5077 /* Get SSC going before enabling the outputs */
74cfd7ac 5078 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5079 POSTING_READ(PCH_DREF_CONTROL);
5080 udelay(200);
5081
74cfd7ac 5082 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5083
5084 /* Enable CPU source on CPU attached eDP */
199e5d79 5085 if (has_cpu_edp) {
99eb6a01 5086 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5087 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5088 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5089 }
13d83a67 5090 else
74cfd7ac 5091 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5092 } else
74cfd7ac 5093 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5094
74cfd7ac 5095 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5096 POSTING_READ(PCH_DREF_CONTROL);
5097 udelay(200);
5098 } else {
5099 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5100
74cfd7ac 5101 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5102
5103 /* Turn off CPU output */
74cfd7ac 5104 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5105
74cfd7ac 5106 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5107 POSTING_READ(PCH_DREF_CONTROL);
5108 udelay(200);
5109
5110 /* Turn off the SSC source */
74cfd7ac
CW		 5111 val &= ~DREF_SSC_SOURCE_MASK;
5112 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5113
5114 /* Turn off SSC1 */
74cfd7ac 5115 val &= ~DREF_SSC1_ENABLE;
199e5d79 5116
74cfd7ac 5117 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5118 POSTING_READ(PCH_DREF_CONTROL);
5119 udelay(200);
5120 }
74cfd7ac
CW		 5121
5122 BUG_ON(val != final);
13d83a67
JB		 5123}
5124
dde86e2d
PZ		 5125/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5126static void lpt_init_pch_refclk(struct drm_device *dev)
5127{
5128 struct drm_i915_private *dev_priv = dev->dev_private;
5129 struct drm_mode_config *mode_config = &dev->mode_config;
5130 struct intel_encoder *encoder;
5131 bool has_vga = false;
5132 bool is_sdv = false;
5133 u32 tmp;
5134
5135 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5136 switch (encoder->type) {
5137 case INTEL_OUTPUT_ANALOG:
5138 has_vga = true;
5139 break;
5140 }
5141 }
5142
5143 if (!has_vga)
5144 return;
5145
c00db246
DV		 5146 mutex_lock(&dev_priv->dpio_lock);
5147
dde86e2d
PZ		 5148 /* XXX: Rip out SDV support once Haswell ships for real. */
5149 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5150 is_sdv = true;
5151
5152 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5153 tmp &= ~SBI_SSCCTL_DISABLE;
5154 tmp |= SBI_SSCCTL_PATHALT;
5155 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5156
5157 udelay(24);
5158
5159 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5160 tmp &= ~SBI_SSCCTL_PATHALT;
5161 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5162
5163 if (!is_sdv) {
5164 tmp = I915_READ(SOUTH_CHICKEN2);
5165 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5166 I915_WRITE(SOUTH_CHICKEN2, tmp);
5167
5168 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5169 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5170 DRM_ERROR("FDI mPHY reset assert timeout\n");
5171
5172 tmp = I915_READ(SOUTH_CHICKEN2);
5173 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5174 I915_WRITE(SOUTH_CHICKEN2, tmp);
5175
5176 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5177 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5178 100))
5179 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5180 }
5181
5182 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5183 tmp &= ~(0xFF << 24);
5184 tmp |= (0x12 << 24);
5185 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5186
dde86e2d
PZ		 5187 if (is_sdv) {
5188 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5189 tmp |= 0x7FFF;
5190 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5191 }
5192
5193 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5194 tmp |= (1 << 11);
5195 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5196
5197 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5198 tmp |= (1 << 11);
5199 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5200
5201 if (is_sdv) {
5202 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5203 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5204 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5205
5206 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5207 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5208 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5209
5210 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5211 tmp |= (0x3F << 8);
5212 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5213
5214 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5215 tmp |= (0x3F << 8);
5216 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5217 }
5218
5219 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5220 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5221 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5222
5223 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5224 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5225 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5226
5227 if (!is_sdv) {
5228 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5229 tmp &= ~(7 << 13);
5230 tmp |= (5 << 13);
5231 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5232
5233 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5234 tmp &= ~(7 << 13);
5235 tmp |= (5 << 13);
5236 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5237 }
5238
5239 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5240 tmp &= ~0xFF;
5241 tmp |= 0x1C;
5242 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5243
5244 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5245 tmp &= ~0xFF;
5246 tmp |= 0x1C;
5247 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5248
5249 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5250 tmp &= ~(0xFF << 16);
5251 tmp |= (0x1C << 16);
5252 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5253
5254 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5255 tmp &= ~(0xFF << 16);
5256 tmp |= (0x1C << 16);
5257 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5258
5259 if (!is_sdv) {
5260 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5261 tmp |= (1 << 27);
5262 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5263
5264 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5265 tmp |= (1 << 27);
5266 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5267
5268 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5269 tmp &= ~(0xF << 28);
5270 tmp |= (4 << 28);
5271 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5272
5273 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5274 tmp &= ~(0xF << 28);
5275 tmp |= (4 << 28);
5276 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5277 }
5278
5279 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5280 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5281 tmp |= SBI_DBUFF0_ENABLE;
5282 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5283
5284 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5285}
5286
5287/*
5288 * Initialize reference clocks when the driver loads
5289 */
5290void intel_init_pch_refclk(struct drm_device *dev)
5291{
5292 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5293 ironlake_init_pch_refclk(dev);
5294 else if (HAS_PCH_LPT(dev))
5295 lpt_init_pch_refclk(dev);
5296}
5297
d9d444cb
JB		 5298static int ironlake_get_refclk(struct drm_crtc *crtc)
5299{
5300 struct drm_device *dev = crtc->dev;
5301 struct drm_i915_private *dev_priv = dev->dev_private;
5302 struct intel_encoder *encoder;
d9d444cb
JB		 5303 int num_connectors = 0;
5304 bool is_lvds = false;
5305
6c2b7c12 5306 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5307 switch (encoder->type) {
5308 case INTEL_OUTPUT_LVDS:
5309 is_lvds = true;
5310 break;
d9d444cb
JB		 5311 }
5312 num_connectors++;
5313 }
5314
5315 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5316 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5317 dev_priv->vbt.lvds_ssc_freq);
5318 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5319 }
5320
5321 return 120000;
5322}
5323
6ff93609 5324static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5325{
c8203565 5326 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5327 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5328 int pipe = intel_crtc->pipe;
c8203565
PZ		 5329 uint32_t val;
5330
78114071 5331 val = 0;
c8203565 5332
965e0c48 5333 switch (intel_crtc->config.pipe_bpp) {
c8203565 5334 case 18:
dfd07d72 5335 val |= PIPECONF_6BPC;
c8203565
PZ		 5336 break;
5337 case 24:
dfd07d72 5338 val |= PIPECONF_8BPC;
c8203565
PZ		 5339 break;
5340 case 30:
dfd07d72 5341 val |= PIPECONF_10BPC;
c8203565
PZ		 5342 break;
5343 case 36:
dfd07d72 5344 val |= PIPECONF_12BPC;
c8203565
PZ		 5345 break;
5346 default:
cc769b62
PZ		 5347 /* Case prevented by intel_choose_pipe_bpp_dither. */
5348 BUG();
c8203565
PZ		 5349 }
5350
d8b32247 5351 if (intel_crtc->config.dither)
c8203565
PZ		 5352 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5353
6ff93609 5354 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5355 val |= PIPECONF_INTERLACED_ILK;
5356 else
5357 val |= PIPECONF_PROGRESSIVE;
5358
50f3b016 5359 if (intel_crtc->config.limited_color_range)
3685a8f3 5360 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 5361
c8203565
PZ		 5362 I915_WRITE(PIPECONF(pipe), val);
5363 POSTING_READ(PIPECONF(pipe));
5364}
5365
86d3efce
VS		 5366/*
5367 * Set up the pipe CSC unit.
5368 *
5369 * Currently only full range RGB to limited range RGB conversion
5370 * is supported, but eventually this should handle various
5371 * RGB<->YCbCr scenarios as well.
5372 */
50f3b016 5373static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5374{
5375 struct drm_device *dev = crtc->dev;
5376 struct drm_i915_private *dev_priv = dev->dev_private;
5377 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5378 int pipe = intel_crtc->pipe;
5379 uint16_t coeff = 0x7800; /* 1.0 */
5380
5381 /*
5382 * TODO: Check what kind of values actually come out of the pipe
5383 * with these coeff/postoff values and adjust to get the best
5384 * accuracy. Perhaps we even need to take the bpc value into
5385 * consideration.
5386 */
5387
50f3b016 5388 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5389 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5390
5391 /*
5392 * GY/GU and RY/RU should be the other way around according
5393 * to BSpec, but reality doesn't agree. Just set them up in
5394 * a way that results in the correct picture.
5395 */
5396 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5397 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5398
5399 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5400 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5401
5402 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5403 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5404
5405 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5406 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5407 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5408
5409 if (INTEL_INFO(dev)->gen > 6) {
5410 uint16_t postoff = 0;
5411
50f3b016 5412 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5413 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5414
5415 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5416 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5417 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5418
5419 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5420 } else {
5421 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5422
50f3b016 5423 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5424 mode |= CSC_BLACK_SCREEN_OFFSET;
5425
5426 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5427 }
5428}
5429
6ff93609 5430static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5431{
5432 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5433 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5434 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5435 uint32_t val;
5436
3eff4faa 5437 val = 0;
ee2b0b38 5438
d8b32247 5439 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5440 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5441
6ff93609 5442 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5443 val |= PIPECONF_INTERLACED_ILK;
5444 else
5445 val |= PIPECONF_PROGRESSIVE;
5446
702e7a56
PZ		 5447 I915_WRITE(PIPECONF(cpu_transcoder), val);
5448 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 5449
5450 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5451 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
ee2b0b38
PZ		 5452}
5453
6591c6e4 5454static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ		 5455 intel_clock_t *clock,
5456 bool *has_reduced_clock,
5457 intel_clock_t *reduced_clock)
5458{
5459 struct drm_device *dev = crtc->dev;
5460 struct drm_i915_private *dev_priv = dev->dev_private;
5461 struct intel_encoder *intel_encoder;
5462 int refclk;
d4906093 5463 const intel_limit_t *limit;
a16af721 5464 bool ret, is_lvds = false;
79e53945 5465
6591c6e4
PZ		 5466 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5467 switch (intel_encoder->type) {
79e53945
JB		 5468 case INTEL_OUTPUT_LVDS:
5469 is_lvds = true;
5470 break;
79e53945
JB		 5471 }
5472 }
5473
d9d444cb 5474 refclk = ironlake_get_refclk(crtc);
79e53945 5475
d4906093
ML		 5476 /*
5477 * Returns a set of divisors for the desired target clock with the given
5478 * refclk, or FALSE. The returned values represent the clock equation:
5479 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5480 */
1b894b59 5481 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 5482 ret = dev_priv->display.find_dpll(limit, crtc,
5483 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 5484 refclk, NULL, clock);
6591c6e4
PZ		 5485 if (!ret)
5486 return false;
cda4b7d3 5487
ddc9003c 5488 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5489 /*
5490 * Ensure we match the reduced clock's P to the target clock.
5491 * If the clocks don't match, we can't switch the display clock
5492 * by using the FP0/FP1. In such case we will disable the LVDS
5493 * downclock feature.
5494 */
ee9300bb
DV		 5495 *has_reduced_clock =
5496 dev_priv->display.find_dpll(limit, crtc,
5497 dev_priv->lvds_downclock,
5498 refclk, clock,
5499 reduced_clock);
652c393a 5500 }
61e9653f 5501
6591c6e4
PZ		 5502 return true;
5503}
5504
01a415fd
DV		 5505static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5506{
5507 struct drm_i915_private *dev_priv = dev->dev_private;
5508 uint32_t temp;
5509
5510 temp = I915_READ(SOUTH_CHICKEN1);
5511 if (temp & FDI_BC_BIFURCATION_SELECT)
5512 return;
5513
5514 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5515 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5516
5517 temp |= FDI_BC_BIFURCATION_SELECT;
5518 DRM_DEBUG_KMS("enabling fdi C rx\n");
5519 I915_WRITE(SOUTH_CHICKEN1, temp);
5520 POSTING_READ(SOUTH_CHICKEN1);
5521}
5522
ebfd86fd 5523static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
01a415fd
DV		 5524{
5525 struct drm_device *dev = intel_crtc->base.dev;
5526 struct drm_i915_private *dev_priv = dev->dev_private;
01a415fd
DV		 5527
5528 switch (intel_crtc->pipe) {
5529 case PIPE_A:
ebfd86fd 5530 break;
01a415fd 5531 case PIPE_B:
ebfd86fd 5532 if (intel_crtc->config.fdi_lanes > 2)
01a415fd
DV		 5533 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5534 else
5535 cpt_enable_fdi_bc_bifurcation(dev);
5536
ebfd86fd 5537 break;
01a415fd 5538 case PIPE_C:
01a415fd
DV		 5539 cpt_enable_fdi_bc_bifurcation(dev);
5540
ebfd86fd 5541 break;
01a415fd
DV		 5542 default:
5543 BUG();
5544 }
5545}
5546
d4b1931c
PZ		 5547int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5548{
5549 /*
5550 * Account for spread spectrum to avoid
5551 * oversubscribing the link. Max center spread
5552 * is 2.5%; use 5% for safety's sake.
5553 */
5554 u32 bps = target_clock * bpp * 21 / 20;
5555 return bps / (link_bw * 8) + 1;
5556}
5557
7429e9d4 5558static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 5559{
7429e9d4 5560 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 5561}
5562
de13a2e3 5563static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5564 u32 *fp,
9a7c7890 5565 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5566{
de13a2e3 5567 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5568 struct drm_device *dev = crtc->dev;
5569 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5570 struct intel_encoder *intel_encoder;
5571 uint32_t dpll;
6cc5f341 5572 int factor, num_connectors = 0;
09ede541 5573 bool is_lvds = false, is_sdvo = false;
79e53945 5574
de13a2e3
PZ		 5575 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5576 switch (intel_encoder->type) {
79e53945
JB		 5577 case INTEL_OUTPUT_LVDS:
5578 is_lvds = true;
5579 break;
5580 case INTEL_OUTPUT_SDVO:
7d57382e 5581 case INTEL_OUTPUT_HDMI:
79e53945 5582 is_sdvo = true;
79e53945 5583 break;
79e53945 5584 }
43565a06 5585
c751ce4f 5586 num_connectors++;
79e53945 5587 }
79e53945 5588
c1858123 5589 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5590 factor = 21;
5591 if (is_lvds) {
5592 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5593 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5594 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5595 factor = 25;
09ede541 5596 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5597 factor = 20;
c1858123 5598
7429e9d4 5599 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5600 *fp |= FP_CB_TUNE;
2c07245f 5601
9a7c7890
DV		 5602 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5603 *fp2 |= FP_CB_TUNE;
5604
5eddb70b 5605 dpll = 0;
2c07245f 5606
a07d6787
EA		 5607 if (is_lvds)
5608 dpll |= DPLLB_MODE_LVDS;
5609 else
5610 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 5611
ef1b460d
DV		 5612 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5613 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 5614
5615 if (is_sdvo)
5616 dpll |= DPLL_DVO_HIGH_SPEED;
9566e9af 5617 if (intel_crtc->config.has_dp_encoder)
a07d6787 5618 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5619
a07d6787 5620 /* compute bitmask from p1 value */
7429e9d4 5621 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5622 /* also FPA1 */
7429e9d4 5623 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5624
7429e9d4 5625 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5626 case 5:
5627 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5628 break;
5629 case 7:
5630 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5631 break;
5632 case 10:
5633 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5634 break;
5635 case 14:
5636 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5637 break;
79e53945
JB		 5638 }
5639
b4c09f3b 5640 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5641 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5642 else
5643 dpll |= PLL_REF_INPUT_DREFCLK;
5644
959e16d6 5645 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 5646}
5647
5648static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5649 int x, int y,
5650 struct drm_framebuffer *fb)
5651{
5652 struct drm_device *dev = crtc->dev;
5653 struct drm_i915_private *dev_priv = dev->dev_private;
5654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5655 int pipe = intel_crtc->pipe;
5656 int plane = intel_crtc->plane;
5657 int num_connectors = 0;
5658 intel_clock_t clock, reduced_clock;
cbbab5bd 5659 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5660 bool ok, has_reduced_clock = false;
8b47047b 5661 bool is_lvds = false;
de13a2e3 5662 struct intel_encoder *encoder;
e2b78267 5663 struct intel_shared_dpll *pll;
de13a2e3 5664 int ret;
de13a2e3
PZ		 5665
5666 for_each_encoder_on_crtc(dev, crtc, encoder) {
5667 switch (encoder->type) {
5668 case INTEL_OUTPUT_LVDS:
5669 is_lvds = true;
5670 break;
de13a2e3
PZ		 5671 }
5672
5673 num_connectors++;
a07d6787 5674 }
79e53945 5675
5dc5298b
PZ		 5676 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5677 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5678
ff9a6750 5679 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 5680 &has_reduced_clock, &reduced_clock);
ee9300bb 5681 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 5682 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5683 return -EINVAL;
79e53945 5684 }
f47709a9
DV		 5685 /* Compat-code for transition, will disappear. */
5686 if (!intel_crtc->config.clock_set) {
5687 intel_crtc->config.dpll.n = clock.n;
5688 intel_crtc->config.dpll.m1 = clock.m1;
5689 intel_crtc->config.dpll.m2 = clock.m2;
5690 intel_crtc->config.dpll.p1 = clock.p1;
5691 intel_crtc->config.dpll.p2 = clock.p2;
5692 }
79e53945 5693
de13a2e3
PZ		 5694 /* Ensure that the cursor is valid for the new mode before changing... */
5695 intel_crtc_update_cursor(crtc, true);
5696
5dc5298b 5697 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5698 if (intel_crtc->config.has_pch_encoder) {
7429e9d4 5699 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5700 if (has_reduced_clock)
7429e9d4 5701 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5702
7429e9d4 5703 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5704 &fp, &reduced_clock,
5705 has_reduced_clock ? &fp2 : NULL);
5706
959e16d6 5707 intel_crtc->config.dpll_hw_state.dpll = dpll;
66e985c0
DV		 5708 intel_crtc->config.dpll_hw_state.fp0 = fp;
5709 if (has_reduced_clock)
5710 intel_crtc->config.dpll_hw_state.fp1 = fp2;
5711 else
5712 intel_crtc->config.dpll_hw_state.fp1 = fp;
5713
b89a1d39 5714 pll = intel_get_shared_dpll(intel_crtc);
ee7b9f93 5715 if (pll == NULL) {
84f44ce7
VS		 5716 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5717 pipe_name(pipe));
4b645f14
JB		 5718 return -EINVAL;
5719 }
ee7b9f93 5720 } else
e72f9fbf 5721 intel_put_shared_dpll(intel_crtc);
79e53945 5722
03afc4a2
DV		 5723 if (intel_crtc->config.has_dp_encoder)
5724 intel_dp_set_m_n(intel_crtc);
79e53945 5725
bcd644e0
DV		 5726 if (is_lvds && has_reduced_clock && i915_powersave)
5727 intel_crtc->lowfreq_avail = true;
5728 else
5729 intel_crtc->lowfreq_avail = false;
e2b78267
DV		 5730
5731 if (intel_crtc->config.has_pch_encoder) {
5732 pll = intel_crtc_to_shared_dpll(intel_crtc);
5733
652c393a
JB		 5734 }
5735
8a654f3b 5736 intel_set_pipe_timings(intel_crtc);
5eddb70b 5737
ca3a0ff8 5738 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5739 intel_cpu_transcoder_set_m_n(intel_crtc,
5740 &intel_crtc->config.fdi_m_n);
5741 }
2c07245f 5742
ebfd86fd
DV		 5743 if (IS_IVYBRIDGE(dev))
5744 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
79e53945 5745
6ff93609 5746 ironlake_set_pipeconf(crtc);
79e53945 5747
a1f9e77e
PZ		 5748 /* Set up the display plane register */
5749 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5750 POSTING_READ(DSPCNTR(plane));
79e53945 5751
94352cf9 5752 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5753
5754 intel_update_watermarks(dev);
5755
1857e1da 5756 return ret;
79e53945
JB		 5757}
5758
72419203
DV		 5759static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5760 struct intel_crtc_config *pipe_config)
5761{
5762 struct drm_device *dev = crtc->base.dev;
5763 struct drm_i915_private *dev_priv = dev->dev_private;
5764 enum transcoder transcoder = pipe_config->cpu_transcoder;
5765
5766 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5767 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5768 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5769 & ~TU_SIZE_MASK;
5770 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5771 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5772 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5773}
5774
2fa2fe9a
DV		 5775static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5776 struct intel_crtc_config *pipe_config)
5777{
5778 struct drm_device *dev = crtc->base.dev;
5779 struct drm_i915_private *dev_priv = dev->dev_private;
5780 uint32_t tmp;
5781
5782 tmp = I915_READ(PF_CTL(crtc->pipe));
5783
5784 if (tmp & PF_ENABLE) {
5785 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5786 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 5787
5788 /* We currently do not free assignements of panel fitters on
5789 * ivb/hsw (since we don't use the higher upscaling modes which
5790 * differentiates them) so just WARN about this case for now. */
5791 if (IS_GEN7(dev)) {
5792 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5793 PF_PIPE_SEL_IVB(crtc->pipe));
5794 }
2fa2fe9a 5795 }
79e53945
JB		 5796}
5797
0e8ffe1b
DV		 5798static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5799 struct intel_crtc_config *pipe_config)
5800{
5801 struct drm_device *dev = crtc->base.dev;
5802 struct drm_i915_private *dev_priv = dev->dev_private;
5803 uint32_t tmp;
5804
eccb140b 5805 pipe_config->cpu_transcoder = crtc->pipe;
c0d43d62 5806 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5807
0e8ffe1b
DV		 5808 tmp = I915_READ(PIPECONF(crtc->pipe));
5809 if (!(tmp & PIPECONF_ENABLE))
5810 return false;
5811
ab9412ba 5812 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 5813 struct intel_shared_dpll *pll;
5814
88adfff1
DV		 5815 pipe_config->has_pch_encoder = true;
5816
627eb5a3
DV		 5817 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5818 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5819 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5820
5821 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 5822
c0d43d62
DV		 5823 if (HAS_PCH_IBX(dev_priv->dev)) {
5824 pipe_config->shared_dpll = crtc->pipe;
5825 } else {
5826 tmp = I915_READ(PCH_DPLL_SEL);
5827 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5828 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5829 else
5830 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5831 }
66e985c0
DV		 5832
5833 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
5834
5835 WARN_ON(!pll->get_hw_state(dev_priv, pll,
5836 &pipe_config->dpll_hw_state));
c93f54cf
DV		 5837
5838 tmp = pipe_config->dpll_hw_state.dpll;
5839 pipe_config->pixel_multiplier =
5840 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
5841 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6c49f241
DV		 5842 } else {
5843 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 5844 }
5845
1bd1bd80
DV		 5846 intel_get_pipe_timings(crtc, pipe_config);
5847
2fa2fe9a
DV		 5848 ironlake_get_pfit_config(crtc, pipe_config);
5849
0e8ffe1b
DV		 5850 return true;
5851}
5852
d6dd9eb1
DV		 5853static void haswell_modeset_global_resources(struct drm_device *dev)
5854{
d6dd9eb1
DV		 5855 bool enable = false;
5856 struct intel_crtc *crtc;
d6dd9eb1
DV		 5857
5858 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 5859 if (!crtc->base.enabled)
5860 continue;
d6dd9eb1 5861
e7a639c4
DV		 5862 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5863 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 5864 enable = true;
5865 }
5866
d6dd9eb1
DV		 5867 intel_set_power_well(dev, enable);
5868}
5869
09b4ddf9 5870static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 5871 int x, int y,
5872 struct drm_framebuffer *fb)
5873{
5874 struct drm_device *dev = crtc->dev;
5875 struct drm_i915_private *dev_priv = dev->dev_private;
5876 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 5877 int plane = intel_crtc->plane;
09b4ddf9 5878 int ret;
09b4ddf9 5879
ff9a6750 5880 if (!intel_ddi_pll_mode_set(crtc))
6441ab5f
PZ		 5881 return -EINVAL;
5882
09b4ddf9
PZ		 5883 /* Ensure that the cursor is valid for the new mode before changing... */
5884 intel_crtc_update_cursor(crtc, true);
5885
03afc4a2
DV		 5886 if (intel_crtc->config.has_dp_encoder)
5887 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 5888
5889 intel_crtc->lowfreq_avail = false;
09b4ddf9 5890
8a654f3b 5891 intel_set_pipe_timings(intel_crtc);
09b4ddf9 5892
ca3a0ff8 5893 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5894 intel_cpu_transcoder_set_m_n(intel_crtc,
5895 &intel_crtc->config.fdi_m_n);
5896 }
09b4ddf9 5897
6ff93609 5898 haswell_set_pipeconf(crtc);
09b4ddf9 5899
50f3b016 5900 intel_set_pipe_csc(crtc);
86d3efce 5901
09b4ddf9 5902 /* Set up the display plane register */
86d3efce 5903 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5904 POSTING_READ(DSPCNTR(plane));
5905
5906 ret = intel_pipe_set_base(crtc, x, y, fb);
5907
5908 intel_update_watermarks(dev);
5909
1f803ee5 5910 return ret;
79e53945
JB		 5911}
5912
0e8ffe1b
DV		 5913static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5914 struct intel_crtc_config *pipe_config)
5915{
5916 struct drm_device *dev = crtc->base.dev;
5917 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 5918 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 5919 uint32_t tmp;
5920
eccb140b 5921 pipe_config->cpu_transcoder = crtc->pipe;
c0d43d62
DV		 5922 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5923
eccb140b
DV		 5924 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
5925 if (tmp & TRANS_DDI_FUNC_ENABLE) {
5926 enum pipe trans_edp_pipe;
5927 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
5928 default:
5929 WARN(1, "unknown pipe linked to edp transcoder\n");
5930 case TRANS_DDI_EDP_INPUT_A_ONOFF:
5931 case TRANS_DDI_EDP_INPUT_A_ON:
5932 trans_edp_pipe = PIPE_A;
5933 break;
5934 case TRANS_DDI_EDP_INPUT_B_ONOFF:
5935 trans_edp_pipe = PIPE_B;
5936 break;
5937 case TRANS_DDI_EDP_INPUT_C_ONOFF:
5938 trans_edp_pipe = PIPE_C;
5939 break;
5940 }
5941
5942 if (trans_edp_pipe == crtc->pipe)
5943 pipe_config->cpu_transcoder = TRANSCODER_EDP;
5944 }
5945
b97186f0 5946 if (!intel_display_power_enabled(dev,
eccb140b 5947 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 5948 return false;
5949
eccb140b 5950 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 5951 if (!(tmp & PIPECONF_ENABLE))
5952 return false;
5953
88adfff1 5954 /*
f196e6be 5955 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 5956 * DDI E. So just check whether this pipe is wired to DDI E and whether
5957 * the PCH transcoder is on.
5958 */
eccb140b 5959 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 5960 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 5961 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 5962 pipe_config->has_pch_encoder = true;
5963
627eb5a3
DV		 5964 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
5965 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5966 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5967
5968 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 5969 }
5970
1bd1bd80
DV		 5971 intel_get_pipe_timings(crtc, pipe_config);
5972
2fa2fe9a
DV		 5973 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
5974 if (intel_display_power_enabled(dev, pfit_domain))
5975 ironlake_get_pfit_config(crtc, pipe_config);
88adfff1 5976
42db64ef
PZ		 5977 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
5978 (I915_READ(IPS_CTL) & IPS_ENABLE);
5979
6c49f241
DV		 5980 pipe_config->pixel_multiplier = 1;
5981
0e8ffe1b
DV		 5982 return true;
5983}
5984
f564048e 5985static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 5986 int x, int y,
94352cf9 5987 struct drm_framebuffer *fb)
f564048e
EA		 5988{
5989 struct drm_device *dev = crtc->dev;
5990 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 5991 struct drm_encoder_helper_funcs *encoder_funcs;
5992 struct intel_encoder *encoder;
0b701d27 5993 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5994 struct drm_display_mode *adjusted_mode =
5995 &intel_crtc->config.adjusted_mode;
5996 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 5997 int pipe = intel_crtc->pipe;
f564048e
EA		 5998 int ret;
5999
0b701d27 6000 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6001
b8cecdf5
DV		 6002 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6003
79e53945 6004 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6005
9256aa19
DV		 6006 if (ret != 0)
6007 return ret;
6008
6009 for_each_encoder_on_crtc(dev, crtc, encoder) {
6010 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6011 encoder->base.base.id,
6012 drm_get_encoder_name(&encoder->base),
6013 mode->base.id, mode->name);
6cc5f341
DV		 6014 if (encoder->mode_set) {
6015 encoder->mode_set(encoder);
6016 } else {
6017 encoder_funcs = encoder->base.helper_private;
6018 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6019 }
9256aa19
DV		 6020 }
6021
6022 return 0;
79e53945
JB		 6023}
6024
3a9627f4
WF		 6025static bool intel_eld_uptodate(struct drm_connector *connector,
6026 int reg_eldv, uint32_t bits_eldv,
6027 int reg_elda, uint32_t bits_elda,
6028 int reg_edid)
6029{
6030 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6031 uint8_t *eld = connector->eld;
6032 uint32_t i;
6033
6034 i = I915_READ(reg_eldv);
6035 i &= bits_eldv;
6036
6037 if (!eld[0])
6038 return !i;
6039
6040 if (!i)
6041 return false;
6042
6043 i = I915_READ(reg_elda);
6044 i &= ~bits_elda;
6045 I915_WRITE(reg_elda, i);
6046
6047 for (i = 0; i < eld[2]; i++)
6048 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6049 return false;
6050
6051 return true;
6052}
6053
e0dac65e
WF		 6054static void g4x_write_eld(struct drm_connector *connector,
6055 struct drm_crtc *crtc)
6056{
6057 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6058 uint8_t *eld = connector->eld;
6059 uint32_t eldv;
6060 uint32_t len;
6061 uint32_t i;
6062
6063 i = I915_READ(G4X_AUD_VID_DID);
6064
6065 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6066 eldv = G4X_ELDV_DEVCL_DEVBLC;
6067 else
6068 eldv = G4X_ELDV_DEVCTG;
6069
3a9627f4
WF		 6070 if (intel_eld_uptodate(connector,
6071 G4X_AUD_CNTL_ST, eldv,
6072 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6073 G4X_HDMIW_HDMIEDID))
6074 return;
6075
e0dac65e
WF		 6076 i = I915_READ(G4X_AUD_CNTL_ST);
6077 i &= ~(eldv | G4X_ELD_ADDR);
6078 len = (i >> 9) & 0x1f; /* ELD buffer size */
6079 I915_WRITE(G4X_AUD_CNTL_ST, i);
6080
6081 if (!eld[0])
6082 return;
6083
6084 len = min_t(uint8_t, eld[2], len);
6085 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6086 for (i = 0; i < len; i++)
6087 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6088
6089 i = I915_READ(G4X_AUD_CNTL_ST);
6090 i |= eldv;
6091 I915_WRITE(G4X_AUD_CNTL_ST, i);
6092}
6093
83358c85
WX		 6094static void haswell_write_eld(struct drm_connector *connector,
6095 struct drm_crtc *crtc)
6096{
6097 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6098 uint8_t *eld = connector->eld;
6099 struct drm_device *dev = crtc->dev;
7b9f35a6 6100 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6101 uint32_t eldv;
6102 uint32_t i;
6103 int len;
6104 int pipe = to_intel_crtc(crtc)->pipe;
6105 int tmp;
6106
6107 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6108 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6109 int aud_config = HSW_AUD_CFG(pipe);
6110 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6111
6112
6113 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6114
6115 /* Audio output enable */
6116 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6117 tmp = I915_READ(aud_cntrl_st2);
6118 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6119 I915_WRITE(aud_cntrl_st2, tmp);
6120
6121 /* Wait for 1 vertical blank */
6122 intel_wait_for_vblank(dev, pipe);
6123
6124 /* Set ELD valid state */
6125 tmp = I915_READ(aud_cntrl_st2);
6126 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6127 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6128 I915_WRITE(aud_cntrl_st2, tmp);
6129 tmp = I915_READ(aud_cntrl_st2);
6130 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6131
6132 /* Enable HDMI mode */
6133 tmp = I915_READ(aud_config);
6134 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6135 /* clear N_programing_enable and N_value_index */
6136 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6137 I915_WRITE(aud_config, tmp);
6138
6139 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6140
6141 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6142 intel_crtc->eld_vld = true;
83358c85
WX		 6143
6144 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6145 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6146 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6147 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6148 } else
6149 I915_WRITE(aud_config, 0);
6150
6151 if (intel_eld_uptodate(connector,
6152 aud_cntrl_st2, eldv,
6153 aud_cntl_st, IBX_ELD_ADDRESS,
6154 hdmiw_hdmiedid))
6155 return;
6156
6157 i = I915_READ(aud_cntrl_st2);
6158 i &= ~eldv;
6159 I915_WRITE(aud_cntrl_st2, i);
6160
6161 if (!eld[0])
6162 return;
6163
6164 i = I915_READ(aud_cntl_st);
6165 i &= ~IBX_ELD_ADDRESS;
6166 I915_WRITE(aud_cntl_st, i);
6167 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6168 DRM_DEBUG_DRIVER("port num:%d\n", i);
6169
6170 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6171 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6172 for (i = 0; i < len; i++)
6173 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6174
6175 i = I915_READ(aud_cntrl_st2);
6176 i |= eldv;
6177 I915_WRITE(aud_cntrl_st2, i);
6178
6179}
6180
e0dac65e
WF		 6181static void ironlake_write_eld(struct drm_connector *connector,
6182 struct drm_crtc *crtc)
6183{
6184 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6185 uint8_t *eld = connector->eld;
6186 uint32_t eldv;
6187 uint32_t i;
6188 int len;
6189 int hdmiw_hdmiedid;
b6daa025 6190 int aud_config;
e0dac65e
WF		 6191 int aud_cntl_st;
6192 int aud_cntrl_st2;
9b138a83 6193 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6194
b3f33cbf 6195 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6196 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6197 aud_config = IBX_AUD_CFG(pipe);
6198 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6199 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6200 } else {
9b138a83
WX		 6201 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6202 aud_config = CPT_AUD_CFG(pipe);
6203 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6204 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6205 }
6206
9b138a83 6207 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6208
6209 i = I915_READ(aud_cntl_st);
9b138a83 6210 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6211 if (!i) {
6212 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6213 /* operate blindly on all ports */
1202b4c6
WF		 6214 eldv = IBX_ELD_VALIDB;
6215 eldv |= IBX_ELD_VALIDB << 4;
6216 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6217 } else {
2582a850 6218 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6219 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6220 }
6221
3a9627f4
WF		 6222 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6223 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6224 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6225 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6226 } else
6227 I915_WRITE(aud_config, 0);
e0dac65e 6228
3a9627f4
WF		 6229 if (intel_eld_uptodate(connector,
6230 aud_cntrl_st2, eldv,
6231 aud_cntl_st, IBX_ELD_ADDRESS,
6232 hdmiw_hdmiedid))
6233 return;
6234
e0dac65e
WF		 6235 i = I915_READ(aud_cntrl_st2);
6236 i &= ~eldv;
6237 I915_WRITE(aud_cntrl_st2, i);
6238
6239 if (!eld[0])
6240 return;
6241
e0dac65e 6242 i = I915_READ(aud_cntl_st);
1202b4c6 6243 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6244 I915_WRITE(aud_cntl_st, i);
6245
6246 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6247 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6248 for (i = 0; i < len; i++)
6249 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6250
6251 i = I915_READ(aud_cntrl_st2);
6252 i |= eldv;
6253 I915_WRITE(aud_cntrl_st2, i);
6254}
6255
6256void intel_write_eld(struct drm_encoder *encoder,
6257 struct drm_display_mode *mode)
6258{
6259 struct drm_crtc *crtc = encoder->crtc;
6260 struct drm_connector *connector;
6261 struct drm_device *dev = encoder->dev;
6262 struct drm_i915_private *dev_priv = dev->dev_private;
6263
6264 connector = drm_select_eld(encoder, mode);
6265 if (!connector)
6266 return;
6267
6268 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6269 connector->base.id,
6270 drm_get_connector_name(connector),
6271 connector->encoder->base.id,
6272 drm_get_encoder_name(connector->encoder));
6273
6274 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6275
6276 if (dev_priv->display.write_eld)
6277 dev_priv->display.write_eld(connector, crtc);
6278}
6279
79e53945
JB		 6280/** Loads the palette/gamma unit for the CRTC with the prepared values */
6281void intel_crtc_load_lut(struct drm_crtc *crtc)
6282{
6283 struct drm_device *dev = crtc->dev;
6284 struct drm_i915_private *dev_priv = dev->dev_private;
6285 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
42db64ef
PZ		 6286 enum pipe pipe = intel_crtc->pipe;
6287 int palreg = PALETTE(pipe);
79e53945 6288 int i;
42db64ef 6289 bool reenable_ips = false;
79e53945
JB		 6290
6291 /* The clocks have to be on to load the palette. */
aed3f09d 6292 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6293 return;
6294
14420bd0
VS		 6295 if (!HAS_PCH_SPLIT(dev_priv->dev))
6296 assert_pll_enabled(dev_priv, pipe);
6297
f2b115e6 6298 /* use legacy palette for Ironlake */
bad720ff 6299 if (HAS_PCH_SPLIT(dev))
42db64ef
PZ		 6300 palreg = LGC_PALETTE(pipe);
6301
6302 /* Workaround : Do not read or write the pipe palette/gamma data while
6303 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6304 */
6305 if (intel_crtc->config.ips_enabled &&
6306 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6307 GAMMA_MODE_MODE_SPLIT)) {
6308 hsw_disable_ips(intel_crtc);
6309 reenable_ips = true;
6310 }
2c07245f 6311
79e53945
JB		 6312 for (i = 0; i < 256; i++) {
6313 I915_WRITE(palreg + 4 * i,
6314 (intel_crtc->lut_r[i] << 16) |
6315 (intel_crtc->lut_g[i] << 8) |
6316 intel_crtc->lut_b[i]);
6317 }
42db64ef
PZ		 6318
6319 if (reenable_ips)
6320 hsw_enable_ips(intel_crtc);
79e53945
JB		 6321}
6322
560b85bb
CW		 6323static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6324{
6325 struct drm_device *dev = crtc->dev;
6326 struct drm_i915_private *dev_priv = dev->dev_private;
6327 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6328 bool visible = base != 0;
6329 u32 cntl;
6330
6331 if (intel_crtc->cursor_visible == visible)
6332 return;
6333
9db4a9c7 6334 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6335 if (visible) {
6336 /* On these chipsets we can only modify the base whilst
6337 * the cursor is disabled.
6338 */
9db4a9c7 6339 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6340
6341 cntl &= ~(CURSOR_FORMAT_MASK);
6342 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6343 cntl |= CURSOR_ENABLE |
6344 CURSOR_GAMMA_ENABLE |
6345 CURSOR_FORMAT_ARGB;
6346 } else
6347 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6348 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6349
6350 intel_crtc->cursor_visible = visible;
6351}
6352
6353static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6354{
6355 struct drm_device *dev = crtc->dev;
6356 struct drm_i915_private *dev_priv = dev->dev_private;
6357 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6358 int pipe = intel_crtc->pipe;
6359 bool visible = base != 0;
6360
6361 if (intel_crtc->cursor_visible != visible) {
548f245b 6362 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6363 if (base) {
6364 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6365 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6366 cntl |= pipe << 28; /* Connect to correct pipe */
6367 } else {
6368 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6369 cntl |= CURSOR_MODE_DISABLE;
6370 }
9db4a9c7 6371 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6372
6373 intel_crtc->cursor_visible = visible;
6374 }
6375 /* and commit changes on next vblank */
9db4a9c7 6376 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6377}
6378
65a21cd6
JB		 6379static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6380{
6381 struct drm_device *dev = crtc->dev;
6382 struct drm_i915_private *dev_priv = dev->dev_private;
6383 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6384 int pipe = intel_crtc->pipe;
6385 bool visible = base != 0;
6386
6387 if (intel_crtc->cursor_visible != visible) {
6388 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6389 if (base) {
6390 cntl &= ~CURSOR_MODE;
6391 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6392 } else {
6393 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6394 cntl |= CURSOR_MODE_DISABLE;
6395 }
86d3efce
VS		 6396 if (IS_HASWELL(dev))
6397 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6398 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6399
6400 intel_crtc->cursor_visible = visible;
6401 }
6402 /* and commit changes on next vblank */
6403 I915_WRITE(CURBASE_IVB(pipe), base);
6404}
6405
cda4b7d3 6406/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6407static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6408 bool on)
cda4b7d3
CW		 6409{
6410 struct drm_device *dev = crtc->dev;
6411 struct drm_i915_private *dev_priv = dev->dev_private;
6412 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6413 int pipe = intel_crtc->pipe;
6414 int x = intel_crtc->cursor_x;
6415 int y = intel_crtc->cursor_y;
560b85bb 6416 u32 base, pos;
cda4b7d3
CW		 6417 bool visible;
6418
6419 pos = 0;
6420
6b383a7f 6421 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6422 base = intel_crtc->cursor_addr;
6423 if (x > (int) crtc->fb->width)
6424 base = 0;
6425
6426 if (y > (int) crtc->fb->height)
6427 base = 0;
6428 } else
6429 base = 0;
6430
6431 if (x < 0) {
6432 if (x + intel_crtc->cursor_width < 0)
6433 base = 0;
6434
6435 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6436 x = -x;
6437 }
6438 pos |= x << CURSOR_X_SHIFT;
6439
6440 if (y < 0) {
6441 if (y + intel_crtc->cursor_height < 0)
6442 base = 0;
6443
6444 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6445 y = -y;
6446 }
6447 pos |= y << CURSOR_Y_SHIFT;
6448
6449 visible = base != 0;
560b85bb 6450 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6451 return;
6452
0cd83aa9 6453 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6454 I915_WRITE(CURPOS_IVB(pipe), pos);
6455 ivb_update_cursor(crtc, base);
6456 } else {
6457 I915_WRITE(CURPOS(pipe), pos);
6458 if (IS_845G(dev) || IS_I865G(dev))
6459 i845_update_cursor(crtc, base);
6460 else
6461 i9xx_update_cursor(crtc, base);
6462 }
cda4b7d3
CW		 6463}
6464
79e53945 6465static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6466 struct drm_file *file,
79e53945
JB		 6467 uint32_t handle,
6468 uint32_t width, uint32_t height)
6469{
6470 struct drm_device *dev = crtc->dev;
6471 struct drm_i915_private *dev_priv = dev->dev_private;
6472 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6473 struct drm_i915_gem_object *obj;
cda4b7d3 6474 uint32_t addr;
3f8bc370 6475 int ret;
79e53945 6476
79e53945
JB		 6477 /* if we want to turn off the cursor ignore width and height */
6478 if (!handle) {
28c97730 6479 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6480 addr = 0;
05394f39 6481 obj = NULL;
5004417d 6482 mutex_lock(&dev->struct_mutex);
3f8bc370 6483 goto finish;
79e53945
JB		 6484 }
6485
6486 /* Currently we only support 64x64 cursors */
6487 if (width != 64 || height != 64) {
6488 DRM_ERROR("we currently only support 64x64 cursors\n");
6489 return -EINVAL;
6490 }
6491
05394f39 6492 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6493 if (&obj->base == NULL)
79e53945
JB		 6494 return -ENOENT;
6495
05394f39 6496 if (obj->base.size < width * height * 4) {
79e53945 6497 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6498 ret = -ENOMEM;
6499 goto fail;
79e53945
JB		 6500 }
6501
71acb5eb 6502 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6503 mutex_lock(&dev->struct_mutex);
b295d1b6 6504 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6505 unsigned alignment;
6506
d9e86c0e
CW		 6507 if (obj->tiling_mode) {
6508 DRM_ERROR("cursor cannot be tiled\n");
6509 ret = -EINVAL;
6510 goto fail_locked;
6511 }
6512
693db184
CW		 6513 /* Note that the w/a also requires 2 PTE of padding following
6514 * the bo. We currently fill all unused PTE with the shadow
6515 * page and so we should always have valid PTE following the
6516 * cursor preventing the VT-d warning.
6517 */
6518 alignment = 0;
6519 if (need_vtd_wa(dev))
6520 alignment = 64*1024;
6521
6522 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6523 if (ret) {
6524 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6525 goto fail_locked;
e7b526bb
CW		 6526 }
6527
d9e86c0e
CW		 6528 ret = i915_gem_object_put_fence(obj);
6529 if (ret) {
2da3b9b9 6530 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6531 goto fail_unpin;
6532 }
6533
05394f39 6534 addr = obj->gtt_offset;
71acb5eb 6535 } else {
6eeefaf3 6536 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6537 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6538 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6539 align);
71acb5eb
DA		 6540 if (ret) {
6541 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6542 goto fail_locked;
71acb5eb 6543 }
05394f39 6544 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6545 }
6546
a6c45cf0 6547 if (IS_GEN2(dev))
14b60391
JB		 6548 I915_WRITE(CURSIZE, (height << 12) | width);
6549
3f8bc370 6550 finish:
3f8bc370 6551 if (intel_crtc->cursor_bo) {
b295d1b6 6552 if (dev_priv->info->cursor_needs_physical) {
05394f39 6553 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6554 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6555 } else
6556 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6557 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6558 }
80824003 6559
7f9872e0 6560 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6561
6562 intel_crtc->cursor_addr = addr;
05394f39 6563 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6564 intel_crtc->cursor_width = width;
6565 intel_crtc->cursor_height = height;
6566
40ccc72b 6567 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 6568
79e53945 6569 return 0;
e7b526bb 6570fail_unpin:
05394f39 6571 i915_gem_object_unpin(obj);
7f9872e0 6572fail_locked:
34b8686e 6573 mutex_unlock(&dev->struct_mutex);
bc9025bd 6574fail:
05394f39 6575 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6576 return ret;
79e53945
JB		 6577}
6578
6579static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6580{
79e53945 6581 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6582
cda4b7d3
CW		 6583 intel_crtc->cursor_x = x;
6584 intel_crtc->cursor_y = y;
652c393a 6585
40ccc72b 6586 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 6587
6588 return 0;
6589}
6590
6591/** Sets the color ramps on behalf of RandR */
6592void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6593 u16 blue, int regno)
6594{
6595 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6596
6597 intel_crtc->lut_r[regno] = red >> 8;
6598 intel_crtc->lut_g[regno] = green >> 8;
6599 intel_crtc->lut_b[regno] = blue >> 8;
6600}
6601
b8c00ac5
DA		 6602void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6603 u16 *blue, int regno)
6604{
6605 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6606
6607 *red = intel_crtc->lut_r[regno] << 8;
6608 *green = intel_crtc->lut_g[regno] << 8;
6609 *blue = intel_crtc->lut_b[regno] << 8;
6610}
6611
79e53945 6612static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6613 u16 *blue, uint32_t start, uint32_t size)
79e53945 6614{
7203425a 6615 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6616 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6617
7203425a 6618 for (i = start; i < end; i++) {
79e53945
JB		 6619 intel_crtc->lut_r[i] = red[i] >> 8;
6620 intel_crtc->lut_g[i] = green[i] >> 8;
6621 intel_crtc->lut_b[i] = blue[i] >> 8;
6622 }
6623
6624 intel_crtc_load_lut(crtc);
6625}
6626
79e53945
JB		 6627/* VESA 640x480x72Hz mode to set on the pipe */
6628static struct drm_display_mode load_detect_mode = {
6629 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6630 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6631};
6632
d2dff872
CW		 6633static struct drm_framebuffer *
6634intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6635 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6636 struct drm_i915_gem_object *obj)
6637{
6638 struct intel_framebuffer *intel_fb;
6639 int ret;
6640
6641 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6642 if (!intel_fb) {
6643 drm_gem_object_unreference_unlocked(&obj->base);
6644 return ERR_PTR(-ENOMEM);
6645 }
6646
6647 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6648 if (ret) {
6649 drm_gem_object_unreference_unlocked(&obj->base);
6650 kfree(intel_fb);
6651 return ERR_PTR(ret);
6652 }
6653
6654 return &intel_fb->base;
6655}
6656
6657static u32
6658intel_framebuffer_pitch_for_width(int width, int bpp)
6659{
6660 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6661 return ALIGN(pitch, 64);
6662}
6663
6664static u32
6665intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6666{
6667 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6668 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6669}
6670
6671static struct drm_framebuffer *
6672intel_framebuffer_create_for_mode(struct drm_device *dev,
6673 struct drm_display_mode *mode,
6674 int depth, int bpp)
6675{
6676 struct drm_i915_gem_object *obj;
0fed39bd 6677 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6678
6679 obj = i915_gem_alloc_object(dev,
6680 intel_framebuffer_size_for_mode(mode, bpp));
6681 if (obj == NULL)
6682 return ERR_PTR(-ENOMEM);
6683
6684 mode_cmd.width = mode->hdisplay;
6685 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6686 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6687 bpp);
5ca0c34a 6688 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6689
6690 return intel_framebuffer_create(dev, &mode_cmd, obj);
6691}
6692
6693static struct drm_framebuffer *
6694mode_fits_in_fbdev(struct drm_device *dev,
6695 struct drm_display_mode *mode)
6696{
6697 struct drm_i915_private *dev_priv = dev->dev_private;
6698 struct drm_i915_gem_object *obj;
6699 struct drm_framebuffer *fb;
6700
6701 if (dev_priv->fbdev == NULL)
6702 return NULL;
6703
6704 obj = dev_priv->fbdev->ifb.obj;
6705 if (obj == NULL)
6706 return NULL;
6707
6708 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6709 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6710 fb->bits_per_pixel))
d2dff872
CW		 6711 return NULL;
6712
01f2c773 6713 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6714 return NULL;
6715
6716 return fb;
6717}
6718
d2434ab7 6719bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6720 struct drm_display_mode *mode,
8261b191 6721 struct intel_load_detect_pipe *old)
79e53945
JB		 6722{
6723 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6724 struct intel_encoder *intel_encoder =
6725 intel_attached_encoder(connector);
79e53945 6726 struct drm_crtc *possible_crtc;
4ef69c7a 6727 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6728 struct drm_crtc *crtc = NULL;
6729 struct drm_device *dev = encoder->dev;
94352cf9 6730 struct drm_framebuffer *fb;
79e53945
JB		 6731 int i = -1;
6732
d2dff872
CW		 6733 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6734 connector->base.id, drm_get_connector_name(connector),
6735 encoder->base.id, drm_get_encoder_name(encoder));
6736
79e53945
JB		 6737 /*
6738 * Algorithm gets a little messy:
7a5e4805 6739 *
79e53945
JB		 6740 * - if the connector already has an assigned crtc, use it (but make
6741 * sure it's on first)
7a5e4805 6742 *
79e53945
JB		 6743 * - try to find the first unused crtc that can drive this connector,
6744 * and use that if we find one
79e53945
JB		 6745 */
6746
6747 /* See if we already have a CRTC for this connector */
6748 if (encoder->crtc) {
6749 crtc = encoder->crtc;
8261b191 6750
7b24056b
DV		 6751 mutex_lock(&crtc->mutex);
6752
24218aac 6753 old->dpms_mode = connector->dpms;
8261b191
CW		 6754 old->load_detect_temp = false;
6755
6756 /* Make sure the crtc and connector are running */
24218aac
DV		 6757 if (connector->dpms != DRM_MODE_DPMS_ON)
6758 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6759
7173188d 6760 return true;
79e53945
JB		 6761 }
6762
6763 /* Find an unused one (if possible) */
6764 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6765 i++;
6766 if (!(encoder->possible_crtcs & (1 << i)))
6767 continue;
6768 if (!possible_crtc->enabled) {
6769 crtc = possible_crtc;
6770 break;
6771 }
79e53945
JB		 6772 }
6773
6774 /*
6775 * If we didn't find an unused CRTC, don't use any.
6776 */
6777 if (!crtc) {
7173188d
CW		 6778 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6779 return false;
79e53945
JB		 6780 }
6781
7b24056b 6782 mutex_lock(&crtc->mutex);
fc303101
DV		 6783 intel_encoder->new_crtc = to_intel_crtc(crtc);
6784 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6785
6786 intel_crtc = to_intel_crtc(crtc);
24218aac 6787 old->dpms_mode = connector->dpms;
8261b191 6788 old->load_detect_temp = true;
d2dff872 6789 old->release_fb = NULL;
79e53945 6790
6492711d
CW		 6791 if (!mode)
6792 mode = &load_detect_mode;
79e53945 6793
d2dff872
CW		 6794 /* We need a framebuffer large enough to accommodate all accesses
6795 * that the plane may generate whilst we perform load detection.
6796 * We can not rely on the fbcon either being present (we get called
6797 * during its initialisation to detect all boot displays, or it may
6798 * not even exist) or that it is large enough to satisfy the
6799 * requested mode.
6800 */
94352cf9
DV		 6801 fb = mode_fits_in_fbdev(dev, mode);
6802 if (fb == NULL) {
d2dff872 6803 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6804 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6805 old->release_fb = fb;
d2dff872
CW		 6806 } else
6807 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6808 if (IS_ERR(fb)) {
d2dff872 6809 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6810 mutex_unlock(&crtc->mutex);
0e8b3d3e 6811 return false;
79e53945 6812 }
79e53945 6813
c0c36b94 6814 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6815 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6816 if (old->release_fb)
6817 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6818 mutex_unlock(&crtc->mutex);
0e8b3d3e 6819 return false;
79e53945 6820 }
7173188d 6821
79e53945 6822 /* let the connector get through one full cycle before testing */
9d0498a2 6823 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6824 return true;
79e53945
JB		 6825}
6826
d2434ab7 6827void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6828 struct intel_load_detect_pipe *old)
79e53945 6829{
d2434ab7
DV		 6830 struct intel_encoder *intel_encoder =
6831 intel_attached_encoder(connector);
4ef69c7a 6832 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6833 struct drm_crtc *crtc = encoder->crtc;
79e53945 6834
d2dff872
CW		 6835 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6836 connector->base.id, drm_get_connector_name(connector),
6837 encoder->base.id, drm_get_encoder_name(encoder));
6838
8261b191 6839 if (old->load_detect_temp) {
fc303101
DV		 6840 to_intel_connector(connector)->new_encoder = NULL;
6841 intel_encoder->new_crtc = NULL;
6842 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6843
36206361
DV		 6844 if (old->release_fb) {
6845 drm_framebuffer_unregister_private(old->release_fb);
6846 drm_framebuffer_unreference(old->release_fb);
6847 }
d2dff872 6848
67c96400 6849 mutex_unlock(&crtc->mutex);
0622a53c 6850 return;
79e53945
JB		 6851 }
6852
c751ce4f 6853 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6854 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6855 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6856
6857 mutex_unlock(&crtc->mutex);
79e53945
JB		 6858}
6859
6860/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc
JB		 6861static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
6862 struct intel_crtc_config *pipe_config)
79e53945 6863{
f1f644dc 6864 struct drm_device *dev = crtc->base.dev;
79e53945 6865 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 6866 int pipe = pipe_config->cpu_transcoder;
548f245b 6867 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6868 u32 fp;
6869 intel_clock_t clock;
6870
6871 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6872 fp = I915_READ(FP0(pipe));
79e53945 6873 else
39adb7a5 6874 fp = I915_READ(FP1(pipe));
79e53945
JB		 6875
6876 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6877 if (IS_PINEVIEW(dev)) {
6878 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6879 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6880 } else {
6881 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6882 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6883 }
6884
a6c45cf0 6885 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6886 if (IS_PINEVIEW(dev))
6887 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6888 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6889 else
6890 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6891 DPLL_FPA01_P1_POST_DIV_SHIFT);
6892
6893 switch (dpll & DPLL_MODE_MASK) {
6894 case DPLLB_MODE_DAC_SERIAL:
6895 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6896 5 : 10;
6897 break;
6898 case DPLLB_MODE_LVDS:
6899 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6900 7 : 14;
6901 break;
6902 default:
28c97730 6903 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 6904 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc
JB		 6905 pipe_config->adjusted_mode.clock = 0;
6906 return;
79e53945
JB		 6907 }
6908
ac58c3f0
DV		 6909 if (IS_PINEVIEW(dev))
6910 pineview_clock(96000, &clock);
6911 else
6912 i9xx_clock(96000, &clock);
79e53945
JB		 6913 } else {
6914 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6915
6916 if (is_lvds) {
6917 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6918 DPLL_FPA01_P1_POST_DIV_SHIFT);
6919 clock.p2 = 14;
6920
6921 if ((dpll & PLL_REF_INPUT_MASK) ==
6922 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6923 /* XXX: might not be 66MHz */
ac58c3f0 6924 i9xx_clock(66000, &clock);
79e53945 6925 } else
ac58c3f0 6926 i9xx_clock(48000, &clock);
79e53945
JB		 6927 } else {
6928 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6929 clock.p1 = 2;
6930 else {
6931 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6932 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6933 }
6934 if (dpll & PLL_P2_DIVIDE_BY_4)
6935 clock.p2 = 4;
6936 else
6937 clock.p2 = 2;
6938
ac58c3f0 6939 i9xx_clock(48000, &clock);
79e53945
JB		 6940 }
6941 }
6942
f1f644dc
JB		 6943 pipe_config->adjusted_mode.clock = clock.dot *
6944 pipe_config->pixel_multiplier;
6945}
6946
6947static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
6948 struct intel_crtc_config *pipe_config)
6949{
6950 struct drm_device *dev = crtc->base.dev;
6951 struct drm_i915_private *dev_priv = dev->dev_private;
6952 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6953 int link_freq, repeat;
6954 u64 clock;
6955 u32 link_m, link_n;
6956
6957 repeat = pipe_config->pixel_multiplier;
6958
6959 /*
6960 * The calculation for the data clock is:
6961 * pixel_clock = ((m/n)*(link_clock * nr_lanes * repeat))/bpp
6962 * But we want to avoid losing precison if possible, so:
6963 * pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp))
6964 *
6965 * and the link clock is simpler:
6966 * link_clock = (m * link_clock * repeat) / n
6967 */
6968
6969 /*
6970 * We need to get the FDI or DP link clock here to derive
6971 * the M/N dividers.
6972 *
6973 * For FDI, we read it from the BIOS or use a fixed 2.7GHz.
6974 * For DP, it's either 1.62GHz or 2.7GHz.
6975 * We do our calculations in 10*MHz since we don't need much precison.
79e53945 6976 */
f1f644dc
JB		 6977 if (pipe_config->has_pch_encoder)
6978 link_freq = intel_fdi_link_freq(dev) * 10000;
6979 else
6980 link_freq = pipe_config->port_clock;
6981
6982 link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
6983 link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder));
6984
6985 if (!link_m || !link_n)
6986 return;
79e53945 6987
f1f644dc
JB		 6988 clock = ((u64)link_m * (u64)link_freq * (u64)repeat);
6989 do_div(clock, link_n);
6990
6991 pipe_config->adjusted_mode.clock = clock;
79e53945
JB		 6992}
6993
6994/** Returns the currently programmed mode of the given pipe. */
6995struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6996 struct drm_crtc *crtc)
6997{
548f245b 6998 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6999 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 7000 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 7001 struct drm_display_mode *mode;
f1f644dc 7002 struct intel_crtc_config pipe_config;
fe2b8f9d
PZ		 7003 int htot = I915_READ(HTOTAL(cpu_transcoder));
7004 int hsync = I915_READ(HSYNC(cpu_transcoder));
7005 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7006 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 7007
7008 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7009 if (!mode)
7010 return NULL;
7011
f1f644dc
JB		 7012 /*
7013 * Construct a pipe_config sufficient for getting the clock info
7014 * back out of crtc_clock_get.
7015 *
7016 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7017 * to use a real value here instead.
7018 */
7019 pipe_config.cpu_transcoder = intel_crtc->pipe;
7020 pipe_config.pixel_multiplier = 1;
7021 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7022
7023 mode->clock = pipe_config.adjusted_mode.clock;
79e53945
JB		 7024 mode->hdisplay = (htot & 0xffff) + 1;
7025 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7026 mode->hsync_start = (hsync & 0xffff) + 1;
7027 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7028 mode->vdisplay = (vtot & 0xffff) + 1;
7029 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7030 mode->vsync_start = (vsync & 0xffff) + 1;
7031 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7032
7033 drm_mode_set_name(mode);
79e53945
JB		 7034
7035 return mode;
7036}
7037
3dec0095 7038static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7039{
7040 struct drm_device *dev = crtc->dev;
7041 drm_i915_private_t *dev_priv = dev->dev_private;
7042 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7043 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7044 int dpll_reg = DPLL(pipe);
7045 int dpll;
652c393a 7046
bad720ff 7047 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7048 return;
7049
7050 if (!dev_priv->lvds_downclock_avail)
7051 return;
7052
dbdc6479 7053 dpll = I915_READ(dpll_reg);
652c393a 7054 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7055 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7056
8ac5a6d5 7057 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7058
7059 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7060 I915_WRITE(dpll_reg, dpll);
9d0498a2 7061 intel_wait_for_vblank(dev, pipe);
dbdc6479 7062
652c393a
JB		 7063 dpll = I915_READ(dpll_reg);
7064 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7065 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7066 }
652c393a
JB		 7067}
7068
7069static void intel_decrease_pllclock(struct drm_crtc *crtc)
7070{
7071 struct drm_device *dev = crtc->dev;
7072 drm_i915_private_t *dev_priv = dev->dev_private;
7073 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7074
bad720ff 7075 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7076 return;
7077
7078 if (!dev_priv->lvds_downclock_avail)
7079 return;
7080
7081 /*
7082 * Since this is called by a timer, we should never get here in
7083 * the manual case.
7084 */
7085 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7086 int pipe = intel_crtc->pipe;
7087 int dpll_reg = DPLL(pipe);
7088 int dpll;
f6e5b160 7089
44d98a61 7090 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7091
8ac5a6d5 7092 assert_panel_unlocked(dev_priv, pipe);
652c393a 7093
dc257cf1 7094 dpll = I915_READ(dpll_reg);
652c393a
JB		 7095 dpll |= DISPLAY_RATE_SELECT_FPA1;
7096 I915_WRITE(dpll_reg, dpll);
9d0498a2 7097 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7098 dpll = I915_READ(dpll_reg);
7099 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7100 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7101 }
7102
7103}
7104
f047e395
CW		 7105void intel_mark_busy(struct drm_device *dev)
7106{
f047e395
CW		 7107 i915_update_gfx_val(dev->dev_private);
7108}
7109
7110void intel_mark_idle(struct drm_device *dev)
652c393a 7111{
652c393a 7112 struct drm_crtc *crtc;
652c393a
JB		 7113
7114 if (!i915_powersave)
7115 return;
7116
652c393a 7117 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7118 if (!crtc->fb)
7119 continue;
7120
725a5b54 7121 intel_decrease_pllclock(crtc);
652c393a 7122 }
652c393a
JB		 7123}
7124
c65355bb
CW		 7125void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7126 struct intel_ring_buffer *ring)
652c393a 7127{
f047e395
CW		 7128 struct drm_device *dev = obj->base.dev;
7129 struct drm_crtc *crtc;
652c393a 7130
f047e395 7131 if (!i915_powersave)
acb87dfb
CW		 7132 return;
7133
652c393a
JB		 7134 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7135 if (!crtc->fb)
7136 continue;
7137
c65355bb
CW		 7138 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7139 continue;
7140
7141 intel_increase_pllclock(crtc);
7142 if (ring && intel_fbc_enabled(dev))
7143 ring->fbc_dirty = true;
652c393a
JB		 7144 }
7145}
7146
79e53945
JB		 7147static void intel_crtc_destroy(struct drm_crtc *crtc)
7148{
7149 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7150 struct drm_device *dev = crtc->dev;
7151 struct intel_unpin_work *work;
7152 unsigned long flags;
7153
7154 spin_lock_irqsave(&dev->event_lock, flags);
7155 work = intel_crtc->unpin_work;
7156 intel_crtc->unpin_work = NULL;
7157 spin_unlock_irqrestore(&dev->event_lock, flags);
7158
7159 if (work) {
7160 cancel_work_sync(&work->work);
7161 kfree(work);
7162 }
79e53945 7163
40ccc72b
MK		 7164 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7165
79e53945 7166 drm_crtc_cleanup(crtc);
67e77c5a 7167
79e53945
JB		 7168 kfree(intel_crtc);
7169}
7170
6b95a207
KH		 7171static void intel_unpin_work_fn(struct work_struct *__work)
7172{
7173 struct intel_unpin_work *work =
7174 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7175 struct drm_device *dev = work->crtc->dev;
6b95a207 7176
b4a98e57 7177 mutex_lock(&dev->struct_mutex);
1690e1eb 7178 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7179 drm_gem_object_unreference(&work->pending_flip_obj->base);
7180 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7181
b4a98e57
CW		 7182 intel_update_fbc(dev);
7183 mutex_unlock(&dev->struct_mutex);
7184
7185 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7186 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7187
6b95a207
KH		 7188 kfree(work);
7189}
7190
1afe3e9d 7191static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7192 struct drm_crtc *crtc)
6b95a207
KH		 7193{
7194 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7195 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7196 struct intel_unpin_work *work;
6b95a207
KH		 7197 unsigned long flags;
7198
7199 /* Ignore early vblank irqs */
7200 if (intel_crtc == NULL)
7201 return;
7202
7203 spin_lock_irqsave(&dev->event_lock, flags);
7204 work = intel_crtc->unpin_work;
e7d841ca
CW		 7205
7206 /* Ensure we don't miss a work->pending update ... */
7207 smp_rmb();
7208
7209 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7210 spin_unlock_irqrestore(&dev->event_lock, flags);
7211 return;
7212 }
7213
e7d841ca
CW		 7214 /* and that the unpin work is consistent wrt ->pending. */
7215 smp_rmb();
7216
6b95a207 7217 intel_crtc->unpin_work = NULL;
6b95a207 7218
45a066eb
RC		 7219 if (work->event)
7220 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7221
0af7e4df
MK		 7222 drm_vblank_put(dev, intel_crtc->pipe);
7223
6b95a207
KH		 7224 spin_unlock_irqrestore(&dev->event_lock, flags);
7225
2c10d571 7226 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7227
7228 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7229
7230 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7231}
7232
1afe3e9d
JB		 7233void intel_finish_page_flip(struct drm_device *dev, int pipe)
7234{
7235 drm_i915_private_t *dev_priv = dev->dev_private;
7236 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7237
49b14a5c 7238 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7239}
7240
7241void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7242{
7243 drm_i915_private_t *dev_priv = dev->dev_private;
7244 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7245
49b14a5c 7246 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7247}
7248
6b95a207
KH		 7249void intel_prepare_page_flip(struct drm_device *dev, int plane)
7250{
7251 drm_i915_private_t *dev_priv = dev->dev_private;
7252 struct intel_crtc *intel_crtc =
7253 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7254 unsigned long flags;
7255
e7d841ca
CW		 7256 /* NB: An MMIO update of the plane base pointer will also
7257 * generate a page-flip completion irq, i.e. every modeset
7258 * is also accompanied by a spurious intel_prepare_page_flip().
7259 */
6b95a207 7260 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7261 if (intel_crtc->unpin_work)
7262 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7263 spin_unlock_irqrestore(&dev->event_lock, flags);
7264}
7265
e7d841ca
CW		 7266inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7267{
7268 /* Ensure that the work item is consistent when activating it ... */
7269 smp_wmb();
7270 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7271 /* and that it is marked active as soon as the irq could fire. */
7272 smp_wmb();
7273}
7274
8c9f3aaf
JB		 7275static int intel_gen2_queue_flip(struct drm_device *dev,
7276 struct drm_crtc *crtc,
7277 struct drm_framebuffer *fb,
7278 struct drm_i915_gem_object *obj)
7279{
7280 struct drm_i915_private *dev_priv = dev->dev_private;
7281 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7282 u32 flip_mask;
6d90c952 7283 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7284 int ret;
7285
6d90c952 7286 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7287 if (ret)
83d4092b 7288 goto err;
8c9f3aaf 7289
6d90c952 7290 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7291 if (ret)
83d4092b 7292 goto err_unpin;
8c9f3aaf
JB		 7293
7294 /* Can't queue multiple flips, so wait for the previous
7295 * one to finish before executing the next.
7296 */
7297 if (intel_crtc->plane)
7298 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7299 else
7300 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7301 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7302 intel_ring_emit(ring, MI_NOOP);
7303 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7304 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7305 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7306 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 7307 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7308
7309 intel_mark_page_flip_active(intel_crtc);
6d90c952 7310 intel_ring_advance(ring);
83d4092b
CW		 7311 return 0;
7312
7313err_unpin:
7314 intel_unpin_fb_obj(obj);
7315err:
8c9f3aaf
JB		 7316 return ret;
7317}
7318
7319static int intel_gen3_queue_flip(struct drm_device *dev,
7320 struct drm_crtc *crtc,
7321 struct drm_framebuffer *fb,
7322 struct drm_i915_gem_object *obj)
7323{
7324 struct drm_i915_private *dev_priv = dev->dev_private;
7325 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7326 u32 flip_mask;
6d90c952 7327 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7328 int ret;
7329
6d90c952 7330 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7331 if (ret)
83d4092b 7332 goto err;
8c9f3aaf 7333
6d90c952 7334 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7335 if (ret)
83d4092b 7336 goto err_unpin;
8c9f3aaf
JB		 7337
7338 if (intel_crtc->plane)
7339 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7340 else
7341 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7342 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7343 intel_ring_emit(ring, MI_NOOP);
7344 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7345 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7346 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7347 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7348 intel_ring_emit(ring, MI_NOOP);
7349
e7d841ca 7350 intel_mark_page_flip_active(intel_crtc);
6d90c952 7351 intel_ring_advance(ring);
83d4092b
CW		 7352 return 0;
7353
7354err_unpin:
7355 intel_unpin_fb_obj(obj);
7356err:
8c9f3aaf
JB		 7357 return ret;
7358}
7359
7360static int intel_gen4_queue_flip(struct drm_device *dev,
7361 struct drm_crtc *crtc,
7362 struct drm_framebuffer *fb,
7363 struct drm_i915_gem_object *obj)
7364{
7365 struct drm_i915_private *dev_priv = dev->dev_private;
7366 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7367 uint32_t pf, pipesrc;
6d90c952 7368 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7369 int ret;
7370
6d90c952 7371 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7372 if (ret)
83d4092b 7373 goto err;
8c9f3aaf 7374
6d90c952 7375 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7376 if (ret)
83d4092b 7377 goto err_unpin;
8c9f3aaf
JB		 7378
7379 /* i965+ uses the linear or tiled offsets from the
7380 * Display Registers (which do not change across a page-flip)
7381 * so we need only reprogram the base address.
7382 */
6d90c952
DV		 7383 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7384 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7385 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7386 intel_ring_emit(ring,
7387 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7388 obj->tiling_mode);
8c9f3aaf
JB		 7389
7390 /* XXX Enabling the panel-fitter across page-flip is so far
7391 * untested on non-native modes, so ignore it for now.
7392 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7393 */
7394 pf = 0;
7395 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7396 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7397
7398 intel_mark_page_flip_active(intel_crtc);
6d90c952 7399 intel_ring_advance(ring);
83d4092b
CW		 7400 return 0;
7401
7402err_unpin:
7403 intel_unpin_fb_obj(obj);
7404err:
8c9f3aaf
JB		 7405 return ret;
7406}
7407
7408static int intel_gen6_queue_flip(struct drm_device *dev,
7409 struct drm_crtc *crtc,
7410 struct drm_framebuffer *fb,
7411 struct drm_i915_gem_object *obj)
7412{
7413 struct drm_i915_private *dev_priv = dev->dev_private;
7414 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7415 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7416 uint32_t pf, pipesrc;
7417 int ret;
7418
6d90c952 7419 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7420 if (ret)
83d4092b 7421 goto err;
8c9f3aaf 7422
6d90c952 7423 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7424 if (ret)
83d4092b 7425 goto err_unpin;
8c9f3aaf 7426
6d90c952
DV		 7427 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7428 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7429 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7430 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7431
dc257cf1
DV		 7432 /* Contrary to the suggestions in the documentation,
7433 * "Enable Panel Fitter" does not seem to be required when page
7434 * flipping with a non-native mode, and worse causes a normal
7435 * modeset to fail.
7436 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7437 */
7438 pf = 0;
8c9f3aaf 7439 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7440 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7441
7442 intel_mark_page_flip_active(intel_crtc);
6d90c952 7443 intel_ring_advance(ring);
83d4092b
CW		 7444 return 0;
7445
7446err_unpin:
7447 intel_unpin_fb_obj(obj);
7448err:
8c9f3aaf
JB		 7449 return ret;
7450}
7451
7c9017e5
JB		 7452/*
7453 * On gen7 we currently use the blit ring because (in early silicon at least)
7454 * the render ring doesn't give us interrpts for page flip completion, which
7455 * means clients will hang after the first flip is queued. Fortunately the
7456 * blit ring generates interrupts properly, so use it instead.
7457 */
7458static int intel_gen7_queue_flip(struct drm_device *dev,
7459 struct drm_crtc *crtc,
7460 struct drm_framebuffer *fb,
7461 struct drm_i915_gem_object *obj)
7462{
7463 struct drm_i915_private *dev_priv = dev->dev_private;
7464 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7465 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7466 uint32_t plane_bit = 0;
7c9017e5
JB		 7467 int ret;
7468
7469 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7470 if (ret)
83d4092b 7471 goto err;
7c9017e5 7472
cb05d8de
DV		 7473 switch(intel_crtc->plane) {
7474 case PLANE_A:
7475 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7476 break;
7477 case PLANE_B:
7478 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7479 break;
7480 case PLANE_C:
7481 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7482 break;
7483 default:
7484 WARN_ONCE(1, "unknown plane in flip command\n");
7485 ret = -ENODEV;
ab3951eb 7486 goto err_unpin;
cb05d8de
DV		 7487 }
7488
7c9017e5
JB		 7489 ret = intel_ring_begin(ring, 4);
7490 if (ret)
83d4092b 7491 goto err_unpin;
7c9017e5 7492
cb05d8de 7493 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7494 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7495 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7496 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7497
7498 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7499 intel_ring_advance(ring);
83d4092b
CW		 7500 return 0;
7501
7502err_unpin:
7503 intel_unpin_fb_obj(obj);
7504err:
7c9017e5
JB		 7505 return ret;
7506}
7507
8c9f3aaf
JB		 7508static int intel_default_queue_flip(struct drm_device *dev,
7509 struct drm_crtc *crtc,
7510 struct drm_framebuffer *fb,
7511 struct drm_i915_gem_object *obj)
7512{
7513 return -ENODEV;
7514}
7515
6b95a207
KH		 7516static int intel_crtc_page_flip(struct drm_crtc *crtc,
7517 struct drm_framebuffer *fb,
7518 struct drm_pending_vblank_event *event)
7519{
7520 struct drm_device *dev = crtc->dev;
7521 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7522 struct drm_framebuffer *old_fb = crtc->fb;
7523 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7524 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7525 struct intel_unpin_work *work;
8c9f3aaf 7526 unsigned long flags;
52e68630 7527 int ret;
6b95a207 7528
e6a595d2
VS		 7529 /* Can't change pixel format via MI display flips. */
7530 if (fb->pixel_format != crtc->fb->pixel_format)
7531 return -EINVAL;
7532
7533 /*
7534 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7535 * Note that pitch changes could also affect these register.
7536 */
7537 if (INTEL_INFO(dev)->gen > 3 &&
7538 (fb->offsets[0] != crtc->fb->offsets[0] ||
7539 fb->pitches[0] != crtc->fb->pitches[0]))
7540 return -EINVAL;
7541
6b95a207
KH		 7542 work = kzalloc(sizeof *work, GFP_KERNEL);
7543 if (work == NULL)
7544 return -ENOMEM;
7545
6b95a207 7546 work->event = event;
b4a98e57 7547 work->crtc = crtc;
4a35f83b 7548 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7549 INIT_WORK(&work->work, intel_unpin_work_fn);
7550
7317c75e
JB		 7551 ret = drm_vblank_get(dev, intel_crtc->pipe);
7552 if (ret)
7553 goto free_work;
7554
6b95a207
KH		 7555 /* We borrow the event spin lock for protecting unpin_work */
7556 spin_lock_irqsave(&dev->event_lock, flags);
7557 if (intel_crtc->unpin_work) {
7558 spin_unlock_irqrestore(&dev->event_lock, flags);
7559 kfree(work);
7317c75e 7560 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7561
7562 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7563 return -EBUSY;
7564 }
7565 intel_crtc->unpin_work = work;
7566 spin_unlock_irqrestore(&dev->event_lock, flags);
7567
b4a98e57
CW		 7568 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7569 flush_workqueue(dev_priv->wq);
7570
79158103
CW		 7571 ret = i915_mutex_lock_interruptible(dev);
7572 if (ret)
7573 goto cleanup;
6b95a207 7574
75dfca80 7575 /* Reference the objects for the scheduled work. */
05394f39
CW		 7576 drm_gem_object_reference(&work->old_fb_obj->base);
7577 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7578
7579 crtc->fb = fb;
96b099fd 7580
e1f99ce6 7581 work->pending_flip_obj = obj;
e1f99ce6 7582
4e5359cd
SF		 7583 work->enable_stall_check = true;
7584
b4a98e57 7585 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7586 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7587
8c9f3aaf
JB		 7588 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7589 if (ret)
7590 goto cleanup_pending;
6b95a207 7591
7782de3b 7592 intel_disable_fbc(dev);
c65355bb 7593 intel_mark_fb_busy(obj, NULL);
6b95a207
KH		 7594 mutex_unlock(&dev->struct_mutex);
7595
e5510fac
JB		 7596 trace_i915_flip_request(intel_crtc->plane, obj);
7597
6b95a207 7598 return 0;
96b099fd 7599
8c9f3aaf 7600cleanup_pending:
b4a98e57 7601 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7602 crtc->fb = old_fb;
05394f39
CW		 7603 drm_gem_object_unreference(&work->old_fb_obj->base);
7604 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7605 mutex_unlock(&dev->struct_mutex);
7606
79158103 7607cleanup:
96b099fd
CW		 7608 spin_lock_irqsave(&dev->event_lock, flags);
7609 intel_crtc->unpin_work = NULL;
7610 spin_unlock_irqrestore(&dev->event_lock, flags);
7611
7317c75e
JB		 7612 drm_vblank_put(dev, intel_crtc->pipe);
7613free_work:
96b099fd
CW		 7614 kfree(work);
7615
7616 return ret;
6b95a207
KH		 7617}
7618
f6e5b160 7619static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7620 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7621 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7622};
7623
50f56119
DV		 7624static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7625 struct drm_crtc *crtc)
7626{
7627 struct drm_device *dev;
7628 struct drm_crtc *tmp;
7629 int crtc_mask = 1;
47f1c6c9 7630
50f56119 7631 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7632
50f56119 7633 dev = crtc->dev;
47f1c6c9 7634
50f56119
DV		 7635 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7636 if (tmp == crtc)
7637 break;
7638 crtc_mask <<= 1;
7639 }
47f1c6c9 7640
50f56119
DV		 7641 if (encoder->possible_crtcs & crtc_mask)
7642 return true;
7643 return false;
47f1c6c9 7644}
79e53945 7645
9a935856
DV		 7646/**
7647 * intel_modeset_update_staged_output_state
7648 *
7649 * Updates the staged output configuration state, e.g. after we've read out the
7650 * current hw state.
7651 */
7652static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7653{
9a935856
DV		 7654 struct intel_encoder *encoder;
7655 struct intel_connector *connector;
f6e5b160 7656
9a935856
DV		 7657 list_for_each_entry(connector, &dev->mode_config.connector_list,
7658 base.head) {
7659 connector->new_encoder =
7660 to_intel_encoder(connector->base.encoder);
7661 }
f6e5b160 7662
9a935856
DV		 7663 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7664 base.head) {
7665 encoder->new_crtc =
7666 to_intel_crtc(encoder->base.crtc);
7667 }
f6e5b160
CW		 7668}
7669
9a935856
DV		 7670/**
7671 * intel_modeset_commit_output_state
7672 *
7673 * This function copies the stage display pipe configuration to the real one.
7674 */
7675static void intel_modeset_commit_output_state(struct drm_device *dev)
7676{
7677 struct intel_encoder *encoder;
7678 struct intel_connector *connector;
f6e5b160 7679
9a935856
DV		 7680 list_for_each_entry(connector, &dev->mode_config.connector_list,
7681 base.head) {
7682 connector->base.encoder = &connector->new_encoder->base;
7683 }
f6e5b160 7684
9a935856
DV		 7685 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7686 base.head) {
7687 encoder->base.crtc = &encoder->new_crtc->base;
7688 }
7689}
7690
050f7aeb
DV		 7691static void
7692connected_sink_compute_bpp(struct intel_connector * connector,
7693 struct intel_crtc_config *pipe_config)
7694{
7695 int bpp = pipe_config->pipe_bpp;
7696
7697 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7698 connector->base.base.id,
7699 drm_get_connector_name(&connector->base));
7700
7701 /* Don't use an invalid EDID bpc value */
7702 if (connector->base.display_info.bpc &&
7703 connector->base.display_info.bpc * 3 < bpp) {
7704 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7705 bpp, connector->base.display_info.bpc*3);
7706 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7707 }
7708
7709 /* Clamp bpp to 8 on screens without EDID 1.4 */
7710 if (connector->base.display_info.bpc == 0 && bpp > 24) {
7711 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7712 bpp);
7713 pipe_config->pipe_bpp = 24;
7714 }
7715}
7716
4e53c2e0 7717static int
050f7aeb
DV		 7718compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7719 struct drm_framebuffer *fb,
7720 struct intel_crtc_config *pipe_config)
4e53c2e0 7721{
050f7aeb
DV		 7722 struct drm_device *dev = crtc->base.dev;
7723 struct intel_connector *connector;
4e53c2e0
DV		 7724 int bpp;
7725
d42264b1
DV		 7726 switch (fb->pixel_format) {
7727 case DRM_FORMAT_C8:
4e53c2e0
DV		 7728 bpp = 8*3; /* since we go through a colormap */
7729 break;
d42264b1
DV		 7730 case DRM_FORMAT_XRGB1555:
7731 case DRM_FORMAT_ARGB1555:
7732 /* checked in intel_framebuffer_init already */
7733 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7734 return -EINVAL;
7735 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 7736 bpp = 6*3; /* min is 18bpp */
7737 break;
d42264b1
DV		 7738 case DRM_FORMAT_XBGR8888:
7739 case DRM_FORMAT_ABGR8888:
7740 /* checked in intel_framebuffer_init already */
7741 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7742 return -EINVAL;
7743 case DRM_FORMAT_XRGB8888:
7744 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 7745 bpp = 8*3;
7746 break;
d42264b1
DV		 7747 case DRM_FORMAT_XRGB2101010:
7748 case DRM_FORMAT_ARGB2101010:
7749 case DRM_FORMAT_XBGR2101010:
7750 case DRM_FORMAT_ABGR2101010:
7751 /* checked in intel_framebuffer_init already */
7752 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 7753 return -EINVAL;
4e53c2e0
DV		 7754 bpp = 10*3;
7755 break;
baba133a 7756 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 7757 default:
7758 DRM_DEBUG_KMS("unsupported depth\n");
7759 return -EINVAL;
7760 }
7761
4e53c2e0
DV		 7762 pipe_config->pipe_bpp = bpp;
7763
7764 /* Clamp display bpp to EDID value */
7765 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 7766 base.head) {
1b829e05
DV		 7767 if (!connector->new_encoder ||
7768 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 7769 continue;
7770
050f7aeb 7771 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 7772 }
7773
7774 return bpp;
7775}
7776
c0b03411
DV		 7777static void intel_dump_pipe_config(struct intel_crtc *crtc,
7778 struct intel_crtc_config *pipe_config,
7779 const char *context)
7780{
7781 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7782 context, pipe_name(crtc->pipe));
7783
7784 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7785 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7786 pipe_config->pipe_bpp, pipe_config->dither);
7787 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7788 pipe_config->has_pch_encoder,
7789 pipe_config->fdi_lanes,
7790 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7791 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7792 pipe_config->fdi_m_n.tu);
7793 DRM_DEBUG_KMS("requested mode:\n");
7794 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7795 DRM_DEBUG_KMS("adjusted mode:\n");
7796 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7797 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7798 pipe_config->gmch_pfit.control,
7799 pipe_config->gmch_pfit.pgm_ratios,
7800 pipe_config->gmch_pfit.lvds_border_bits);
7801 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7802 pipe_config->pch_pfit.pos,
7803 pipe_config->pch_pfit.size);
42db64ef 7804 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
c0b03411
DV		 7805}
7806
accfc0c5
DV		 7807static bool check_encoder_cloning(struct drm_crtc *crtc)
7808{
7809 int num_encoders = 0;
7810 bool uncloneable_encoders = false;
7811 struct intel_encoder *encoder;
7812
7813 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
7814 base.head) {
7815 if (&encoder->new_crtc->base != crtc)
7816 continue;
7817
7818 num_encoders++;
7819 if (!encoder->cloneable)
7820 uncloneable_encoders = true;
7821 }
7822
7823 return !(num_encoders > 1 && uncloneable_encoders);
7824}
7825
b8cecdf5
DV		 7826static struct intel_crtc_config *
7827intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 7828 struct drm_framebuffer *fb,
b8cecdf5 7829 struct drm_display_mode *mode)
ee7b9f93 7830{
7758a113 7831 struct drm_device *dev = crtc->dev;
7758a113
DV		 7832 struct drm_encoder_helper_funcs *encoder_funcs;
7833 struct intel_encoder *encoder;
b8cecdf5 7834 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 7835 int plane_bpp, ret = -EINVAL;
7836 bool retry = true;
ee7b9f93 7837
accfc0c5
DV		 7838 if (!check_encoder_cloning(crtc)) {
7839 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
7840 return ERR_PTR(-EINVAL);
7841 }
7842
b8cecdf5
DV		 7843 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7844 if (!pipe_config)
7758a113
DV		 7845 return ERR_PTR(-ENOMEM);
7846
b8cecdf5
DV		 7847 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7848 drm_mode_copy(&pipe_config->requested_mode, mode);
eccb140b 7849 pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe;
c0d43d62 7850 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 7851
050f7aeb
DV		 7852 /* Compute a starting value for pipe_config->pipe_bpp taking the source
7853 * plane pixel format and any sink constraints into account. Returns the
7854 * source plane bpp so that dithering can be selected on mismatches
7855 * after encoders and crtc also have had their say. */
7856 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7857 fb, pipe_config);
4e53c2e0
DV		 7858 if (plane_bpp < 0)
7859 goto fail;
7860
e29c22c0 7861encoder_retry:
ef1b460d 7862 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 7863 pipe_config->port_clock = 0;
ef1b460d 7864 pipe_config->pixel_multiplier = 1;
ff9a6750 7865
7758a113
DV		 7866 /* Pass our mode to the connectors and the CRTC to give them a chance to
7867 * adjust it according to limitations or connector properties, and also
7868 * a chance to reject the mode entirely.
47f1c6c9 7869 */
7758a113
DV		 7870 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7871 base.head) {
47f1c6c9 7872
7758a113
DV		 7873 if (&encoder->new_crtc->base != crtc)
7874 continue;
7ae89233
DV		 7875
7876 if (encoder->compute_config) {
7877 if (!(encoder->compute_config(encoder, pipe_config))) {
7878 DRM_DEBUG_KMS("Encoder config failure\n");
7879 goto fail;
7880 }
7881
7882 continue;
7883 }
7884
7758a113 7885 encoder_funcs = encoder->base.helper_private;
b8cecdf5
DV		 7886 if (!(encoder_funcs->mode_fixup(&encoder->base,
7887 &pipe_config->requested_mode,
7888 &pipe_config->adjusted_mode))) {
7758a113
DV		 7889 DRM_DEBUG_KMS("Encoder fixup failed\n");
7890 goto fail;
7891 }
ee7b9f93 7892 }
47f1c6c9 7893
ff9a6750
DV		 7894 /* Set default port clock if not overwritten by the encoder. Needs to be
7895 * done afterwards in case the encoder adjusts the mode. */
7896 if (!pipe_config->port_clock)
7897 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
7898
a43f6e0f 7899 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 7900 if (ret < 0) {
7758a113
DV		 7901 DRM_DEBUG_KMS("CRTC fixup failed\n");
7902 goto fail;
ee7b9f93 7903 }
e29c22c0
DV		 7904
7905 if (ret == RETRY) {
7906 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7907 ret = -EINVAL;
7908 goto fail;
7909 }
7910
7911 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7912 retry = false;
7913 goto encoder_retry;
7914 }
7915
4e53c2e0
DV		 7916 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7917 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7918 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7919
b8cecdf5 7920 return pipe_config;
7758a113 7921fail:
b8cecdf5 7922 kfree(pipe_config);
e29c22c0 7923 return ERR_PTR(ret);
ee7b9f93 7924}
47f1c6c9 7925
e2e1ed41
DV		 7926/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7927 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7928static void
7929intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7930 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7931{
7932 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7933 struct drm_device *dev = crtc->dev;
7934 struct intel_encoder *encoder;
7935 struct intel_connector *connector;
7936 struct drm_crtc *tmp_crtc;
79e53945 7937
e2e1ed41 7938 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7939
e2e1ed41
DV		 7940 /* Check which crtcs have changed outputs connected to them, these need
7941 * to be part of the prepare_pipes mask. We don't (yet) support global
7942 * modeset across multiple crtcs, so modeset_pipes will only have one
7943 * bit set at most. */
7944 list_for_each_entry(connector, &dev->mode_config.connector_list,
7945 base.head) {
7946 if (connector->base.encoder == &connector->new_encoder->base)
7947 continue;
79e53945 7948
e2e1ed41
DV		 7949 if (connector->base.encoder) {
7950 tmp_crtc = connector->base.encoder->crtc;
7951
7952 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7953 }
7954
7955 if (connector->new_encoder)
7956 *prepare_pipes |=
7957 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7958 }
7959
e2e1ed41
DV		 7960 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7961 base.head) {
7962 if (encoder->base.crtc == &encoder->new_crtc->base)
7963 continue;
7964
7965 if (encoder->base.crtc) {
7966 tmp_crtc = encoder->base.crtc;
7967
7968 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7969 }
7970
7971 if (encoder->new_crtc)
7972 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7973 }
7974
e2e1ed41
DV		 7975 /* Check for any pipes that will be fully disabled ... */
7976 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7977 base.head) {
7978 bool used = false;
22fd0fab 7979
e2e1ed41
DV		 7980 /* Don't try to disable disabled crtcs. */
7981 if (!intel_crtc->base.enabled)
7982 continue;
7e7d76c3 7983
e2e1ed41
DV		 7984 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7985 base.head) {
7986 if (encoder->new_crtc == intel_crtc)
7987 used = true;
7988 }
7989
7990 if (!used)
7991 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7992 }
7993
e2e1ed41
DV		 7994
7995 /* set_mode is also used to update properties on life display pipes. */
7996 intel_crtc = to_intel_crtc(crtc);
7997 if (crtc->enabled)
7998 *prepare_pipes |= 1 << intel_crtc->pipe;
7999
b6c5164d
DV		 8000 /*
8001 * For simplicity do a full modeset on any pipe where the output routing
8002 * changed. We could be more clever, but that would require us to be
8003 * more careful with calling the relevant encoder->mode_set functions.
8004 */
e2e1ed41
DV		 8005 if (*prepare_pipes)
8006 *modeset_pipes = *prepare_pipes;
8007
8008 /* ... and mask these out. */
8009 *modeset_pipes &= ~(*disable_pipes);
8010 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 8011
8012 /*
8013 * HACK: We don't (yet) fully support global modesets. intel_set_config
8014 * obies this rule, but the modeset restore mode of
8015 * intel_modeset_setup_hw_state does not.
8016 */
8017 *modeset_pipes &= 1 << intel_crtc->pipe;
8018 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 8019
8020 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8021 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 8022}
79e53945 8023
ea9d758d 8024static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 8025{
ea9d758d 8026 struct drm_encoder *encoder;
f6e5b160 8027 struct drm_device *dev = crtc->dev;
f6e5b160 8028
ea9d758d
DV		 8029 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8030 if (encoder->crtc == crtc)
8031 return true;
8032
8033 return false;
8034}
8035
8036static void
8037intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8038{
8039 struct intel_encoder *intel_encoder;
8040 struct intel_crtc *intel_crtc;
8041 struct drm_connector *connector;
8042
8043 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8044 base.head) {
8045 if (!intel_encoder->base.crtc)
8046 continue;
8047
8048 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8049
8050 if (prepare_pipes & (1 << intel_crtc->pipe))
8051 intel_encoder->connectors_active = false;
8052 }
8053
8054 intel_modeset_commit_output_state(dev);
8055
8056 /* Update computed state. */
8057 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8058 base.head) {
8059 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8060 }
8061
8062 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8063 if (!connector->encoder || !connector->encoder->crtc)
8064 continue;
8065
8066 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8067
8068 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8069 struct drm_property *dpms_property =
8070 dev->mode_config.dpms_property;
8071
ea9d758d 8072 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8073 drm_object_property_set_value(&connector->base,
68d34720
DV		 8074 dpms_property,
8075 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8076
8077 intel_encoder = to_intel_encoder(connector->encoder);
8078 intel_encoder->connectors_active = true;
8079 }
8080 }
8081
8082}
8083
f1f644dc
JB		 8084static bool intel_fuzzy_clock_check(struct intel_crtc_config *cur,
8085 struct intel_crtc_config *new)
8086{
8087 int clock1, clock2, diff;
8088
8089 clock1 = cur->adjusted_mode.clock;
8090 clock2 = new->adjusted_mode.clock;
8091
8092 if (clock1 == clock2)
8093 return true;
8094
8095 if (!clock1 || !clock2)
8096 return false;
8097
8098 diff = abs(clock1 - clock2);
8099
8100 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8101 return true;
8102
8103 return false;
8104}
8105
25c5b266
DV		 8106#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8107 list_for_each_entry((intel_crtc), \
8108 &(dev)->mode_config.crtc_list, \
8109 base.head) \
0973f18f 8110 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8111
0e8ffe1b 8112static bool
2fa2fe9a
DV		 8113intel_pipe_config_compare(struct drm_device *dev,
8114 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8115 struct intel_crtc_config *pipe_config)
8116{
66e985c0
DV		 8117#define PIPE_CONF_CHECK_X(name) \
8118 if (current_config->name != pipe_config->name) { \
8119 DRM_ERROR("mismatch in " #name " " \
8120 "(expected 0x%08x, found 0x%08x)\n", \
8121 current_config->name, \
8122 pipe_config->name); \
8123 return false; \
8124 }
8125
08a24034
DV		 8126#define PIPE_CONF_CHECK_I(name) \
8127 if (current_config->name != pipe_config->name) { \
8128 DRM_ERROR("mismatch in " #name " " \
8129 "(expected %i, found %i)\n", \
8130 current_config->name, \
8131 pipe_config->name); \
8132 return false; \
88adfff1
DV		 8133 }
8134
1bd1bd80
DV		 8135#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8136 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8137 DRM_ERROR("mismatch in " #name " " \
8138 "(expected %i, found %i)\n", \
8139 current_config->name & (mask), \
8140 pipe_config->name & (mask)); \
8141 return false; \
8142 }
8143
bb760063
DV		 8144#define PIPE_CONF_QUIRK(quirk) \
8145 ((current_config->quirks | pipe_config->quirks) & (quirk))
8146
eccb140b
DV		 8147 PIPE_CONF_CHECK_I(cpu_transcoder);
8148
08a24034
DV		 8149 PIPE_CONF_CHECK_I(has_pch_encoder);
8150 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8151 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8152 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8153 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8154 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8155 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8156
1bd1bd80
DV		 8157 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8158 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8159 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8160 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8161 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8162 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8163
8164 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8165 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8166 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8167 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8168 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8169 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8170
c93f54cf 8171 PIPE_CONF_CHECK_I(pixel_multiplier);
6c49f241 8172
1bd1bd80
DV		 8173 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8174 DRM_MODE_FLAG_INTERLACE);
8175
bb760063
DV		 8176 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8177 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8178 DRM_MODE_FLAG_PHSYNC);
8179 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8180 DRM_MODE_FLAG_NHSYNC);
8181 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8182 DRM_MODE_FLAG_PVSYNC);
8183 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8184 DRM_MODE_FLAG_NVSYNC);
8185 }
045ac3b5 8186
1bd1bd80
DV		 8187 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8188 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8189
2fa2fe9a
DV		 8190 PIPE_CONF_CHECK_I(gmch_pfit.control);
8191 /* pfit ratios are autocomputed by the hw on gen4+ */
8192 if (INTEL_INFO(dev)->gen < 4)
8193 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8194 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8195 PIPE_CONF_CHECK_I(pch_pfit.pos);
8196 PIPE_CONF_CHECK_I(pch_pfit.size);
8197
42db64ef
PZ		 8198 PIPE_CONF_CHECK_I(ips_enabled);
8199
c0d43d62 8200 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 8201 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 8202 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 8203 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8204 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
c0d43d62 8205
66e985c0 8206#undef PIPE_CONF_CHECK_X
08a24034 8207#undef PIPE_CONF_CHECK_I
1bd1bd80 8208#undef PIPE_CONF_CHECK_FLAGS
bb760063 8209#undef PIPE_CONF_QUIRK
88adfff1 8210
f1f644dc
JB		 8211 if (!IS_HASWELL(dev)) {
8212 if (!intel_fuzzy_clock_check(current_config, pipe_config)) {
8213 DRM_ERROR("mismatch in clock (expected %d, found %d\n",
8214 current_config->adjusted_mode.clock,
8215 pipe_config->adjusted_mode.clock);
8216 return false;
8217 }
8218 }
8219
0e8ffe1b
DV		 8220 return true;
8221}
8222
91d1b4bd
DV		 8223static void
8224check_connector_state(struct drm_device *dev)
8af6cf88 8225{
8af6cf88
DV		 8226 struct intel_connector *connector;
8227
8228 list_for_each_entry(connector, &dev->mode_config.connector_list,
8229 base.head) {
8230 /* This also checks the encoder/connector hw state with the
8231 * ->get_hw_state callbacks. */
8232 intel_connector_check_state(connector);
8233
8234 WARN(&connector->new_encoder->base != connector->base.encoder,
8235 "connector's staged encoder doesn't match current encoder\n");
8236 }
91d1b4bd
DV		 8237}
8238
8239static void
8240check_encoder_state(struct drm_device *dev)
8241{
8242 struct intel_encoder *encoder;
8243 struct intel_connector *connector;
8af6cf88
DV		 8244
8245 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8246 base.head) {
8247 bool enabled = false;
8248 bool active = false;
8249 enum pipe pipe, tracked_pipe;
8250
8251 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8252 encoder->base.base.id,
8253 drm_get_encoder_name(&encoder->base));
8254
8255 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8256 "encoder's stage crtc doesn't match current crtc\n");
8257 WARN(encoder->connectors_active && !encoder->base.crtc,
8258 "encoder's active_connectors set, but no crtc\n");
8259
8260 list_for_each_entry(connector, &dev->mode_config.connector_list,
8261 base.head) {
8262 if (connector->base.encoder != &encoder->base)
8263 continue;
8264 enabled = true;
8265 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8266 active = true;
8267 }
8268 WARN(!!encoder->base.crtc != enabled,
8269 "encoder's enabled state mismatch "
8270 "(expected %i, found %i)\n",
8271 !!encoder->base.crtc, enabled);
8272 WARN(active && !encoder->base.crtc,
8273 "active encoder with no crtc\n");
8274
8275 WARN(encoder->connectors_active != active,
8276 "encoder's computed active state doesn't match tracked active state "
8277 "(expected %i, found %i)\n", active, encoder->connectors_active);
8278
8279 active = encoder->get_hw_state(encoder, &pipe);
8280 WARN(active != encoder->connectors_active,
8281 "encoder's hw state doesn't match sw tracking "
8282 "(expected %i, found %i)\n",
8283 encoder->connectors_active, active);
8284
8285 if (!encoder->base.crtc)
8286 continue;
8287
8288 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8289 WARN(active && pipe != tracked_pipe,
8290 "active encoder's pipe doesn't match"
8291 "(expected %i, found %i)\n",
8292 tracked_pipe, pipe);
8293
8294 }
91d1b4bd
DV		 8295}
8296
8297static void
8298check_crtc_state(struct drm_device *dev)
8299{
8300 drm_i915_private_t *dev_priv = dev->dev_private;
8301 struct intel_crtc *crtc;
8302 struct intel_encoder *encoder;
8303 struct intel_crtc_config pipe_config;
8af6cf88
DV		 8304
8305 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8306 base.head) {
8307 bool enabled = false;
8308 bool active = false;
8309
045ac3b5
JB		 8310 memset(&pipe_config, 0, sizeof(pipe_config));
8311
8af6cf88
DV		 8312 DRM_DEBUG_KMS("[CRTC:%d]\n",
8313 crtc->base.base.id);
8314
8315 WARN(crtc->active && !crtc->base.enabled,
8316 "active crtc, but not enabled in sw tracking\n");
8317
8318 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8319 base.head) {
8320 if (encoder->base.crtc != &crtc->base)
8321 continue;
8322 enabled = true;
8323 if (encoder->connectors_active)
8324 active = true;
8325 }
6c49f241 8326
8af6cf88
DV		 8327 WARN(active != crtc->active,
8328 "crtc's computed active state doesn't match tracked active state "
8329 "(expected %i, found %i)\n", active, crtc->active);
8330 WARN(enabled != crtc->base.enabled,
8331 "crtc's computed enabled state doesn't match tracked enabled state "
8332 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8333
0e8ffe1b
DV		 8334 active = dev_priv->display.get_pipe_config(crtc,
8335 &pipe_config);
d62cf62a
DV		 8336
8337 /* hw state is inconsistent with the pipe A quirk */
8338 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8339 active = crtc->active;
8340
6c49f241
DV		 8341 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8342 base.head) {
8343 if (encoder->base.crtc != &crtc->base)
8344 continue;
f1f644dc
JB		 8345 if (encoder->get_config &&
8346 dev_priv->display.get_clock) {
6c49f241 8347 encoder->get_config(encoder, &pipe_config);
f1f644dc
JB		 8348 dev_priv->display.get_clock(crtc,
8349 &pipe_config);
8350 }
6c49f241
DV		 8351 }
8352
0e8ffe1b
DV		 8353 WARN(crtc->active != active,
8354 "crtc active state doesn't match with hw state "
8355 "(expected %i, found %i)\n", crtc->active, active);
8356
c0b03411
DV		 8357 if (active &&
8358 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8359 WARN(1, "pipe state doesn't match!\n");
8360 intel_dump_pipe_config(crtc, &pipe_config,
8361 "[hw state]");
8362 intel_dump_pipe_config(crtc, &crtc->config,
8363 "[sw state]");
8364 }
8af6cf88
DV		 8365 }
8366}
8367
91d1b4bd
DV		 8368static void
8369check_shared_dpll_state(struct drm_device *dev)
8370{
8371 drm_i915_private_t *dev_priv = dev->dev_private;
8372 struct intel_crtc *crtc;
8373 struct intel_dpll_hw_state dpll_hw_state;
8374 int i;
5358901f
DV		 8375
8376 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8377 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8378 int enabled_crtcs = 0, active_crtcs = 0;
8379 bool active;
8380
8381 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8382
8383 DRM_DEBUG_KMS("%s\n", pll->name);
8384
8385 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8386
8387 WARN(pll->active > pll->refcount,
8388 "more active pll users than references: %i vs %i\n",
8389 pll->active, pll->refcount);
8390 WARN(pll->active && !pll->on,
8391 "pll in active use but not on in sw tracking\n");
8392 WARN(pll->on != active,
8393 "pll on state mismatch (expected %i, found %i)\n",
8394 pll->on, active);
8395
8396 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8397 base.head) {
8398 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8399 enabled_crtcs++;
8400 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8401 active_crtcs++;
8402 }
8403 WARN(pll->active != active_crtcs,
8404 "pll active crtcs mismatch (expected %i, found %i)\n",
8405 pll->active, active_crtcs);
8406 WARN(pll->refcount != enabled_crtcs,
8407 "pll enabled crtcs mismatch (expected %i, found %i)\n",
8408 pll->refcount, enabled_crtcs);
66e985c0
DV		 8409
8410 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8411 sizeof(dpll_hw_state)),
8412 "pll hw state mismatch\n");
5358901f 8413 }
8af6cf88
DV		 8414}
8415
91d1b4bd
DV		 8416void
8417intel_modeset_check_state(struct drm_device *dev)
8418{
8419 check_connector_state(dev);
8420 check_encoder_state(dev);
8421 check_crtc_state(dev);
8422 check_shared_dpll_state(dev);
8423}
8424
f30da187
DV		 8425static int __intel_set_mode(struct drm_crtc *crtc,
8426 struct drm_display_mode *mode,
8427 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 8428{
8429 struct drm_device *dev = crtc->dev;
dbf2b54e 8430 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 8431 struct drm_display_mode *saved_mode, *saved_hwmode;
8432 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 8433 struct intel_crtc *intel_crtc;
8434 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 8435 int ret = 0;
a6778b3c 8436
3ac18232 8437 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 8438 if (!saved_mode)
8439 return -ENOMEM;
3ac18232 8440 saved_hwmode = saved_mode + 1;
a6778b3c 8441
e2e1ed41 8442 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 8443 &prepare_pipes, &disable_pipes);
8444
3ac18232
TG		 8445 *saved_hwmode = crtc->hwmode;
8446 *saved_mode = crtc->mode;
a6778b3c 8447
25c5b266
DV		 8448 /* Hack: Because we don't (yet) support global modeset on multiple
8449 * crtcs, we don't keep track of the new mode for more than one crtc.
8450 * Hence simply check whether any bit is set in modeset_pipes in all the
8451 * pieces of code that are not yet converted to deal with mutliple crtcs
8452 * changing their mode at the same time. */
25c5b266 8453 if (modeset_pipes) {
4e53c2e0 8454 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 8455 if (IS_ERR(pipe_config)) {
8456 ret = PTR_ERR(pipe_config);
8457 pipe_config = NULL;
8458
3ac18232 8459 goto out;
25c5b266 8460 }
c0b03411
DV		 8461 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8462 "[modeset]");
25c5b266 8463 }
a6778b3c 8464
460da916
DV		 8465 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8466 intel_crtc_disable(&intel_crtc->base);
8467
ea9d758d
DV		 8468 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8469 if (intel_crtc->base.enabled)
8470 dev_priv->display.crtc_disable(&intel_crtc->base);
8471 }
a6778b3c 8472
6c4c86f5
DV		 8473 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8474 * to set it here already despite that we pass it down the callchain.
f6e5b160 8475 */
b8cecdf5 8476 if (modeset_pipes) {
25c5b266 8477 crtc->mode = *mode;
b8cecdf5
DV		 8478 /* mode_set/enable/disable functions rely on a correct pipe
8479 * config. */
8480 to_intel_crtc(crtc)->config = *pipe_config;
8481 }
7758a113 8482
ea9d758d
DV		 8483 /* Only after disabling all output pipelines that will be changed can we
8484 * update the the output configuration. */
8485 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 8486
47fab737
DV		 8487 if (dev_priv->display.modeset_global_resources)
8488 dev_priv->display.modeset_global_resources(dev);
8489
a6778b3c
DV		 8490 /* Set up the DPLL and any encoders state that needs to adjust or depend
8491 * on the DPLL.
f6e5b160 8492 */
25c5b266 8493 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 8494 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 8495 x, y, fb);
8496 if (ret)
8497 goto done;
a6778b3c
DV		 8498 }
8499
8500 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 8501 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8502 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 8503
25c5b266
DV		 8504 if (modeset_pipes) {
8505 /* Store real post-adjustment hardware mode. */
b8cecdf5 8506 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 8507
25c5b266
DV		 8508 /* Calculate and store various constants which
8509 * are later needed by vblank and swap-completion
8510 * timestamping. They are derived from true hwmode.
8511 */
8512 drm_calc_timestamping_constants(crtc);
8513 }
a6778b3c
DV		 8514
8515 /* FIXME: add subpixel order */
8516done:
c0c36b94 8517 if (ret && crtc->enabled) {
3ac18232
TG		 8518 crtc->hwmode = *saved_hwmode;
8519 crtc->mode = *saved_mode;
a6778b3c
DV		 8520 }
8521
3ac18232 8522out:
b8cecdf5 8523 kfree(pipe_config);
3ac18232 8524 kfree(saved_mode);
a6778b3c 8525 return ret;
f6e5b160
CW		 8526}
8527
f30da187
DV		 8528int intel_set_mode(struct drm_crtc *crtc,
8529 struct drm_display_mode *mode,
8530 int x, int y, struct drm_framebuffer *fb)
8531{
8532 int ret;
8533
8534 ret = __intel_set_mode(crtc, mode, x, y, fb);
8535
8536 if (ret == 0)
8537 intel_modeset_check_state(crtc->dev);
8538
8539 return ret;
8540}
8541
c0c36b94
CW		 8542void intel_crtc_restore_mode(struct drm_crtc *crtc)
8543{
8544 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8545}
8546
25c5b266
DV		 8547#undef for_each_intel_crtc_masked
8548
d9e55608
DV		 8549static void intel_set_config_free(struct intel_set_config *config)
8550{
8551 if (!config)
8552 return;
8553
1aa4b628
DV		 8554 kfree(config->save_connector_encoders);
8555 kfree(config->save_encoder_crtcs);
d9e55608
DV		 8556 kfree(config);
8557}
8558
85f9eb71
DV		 8559static int intel_set_config_save_state(struct drm_device *dev,
8560 struct intel_set_config *config)
8561{
85f9eb71
DV		 8562 struct drm_encoder *encoder;
8563 struct drm_connector *connector;
8564 int count;
8565
1aa4b628
DV		 8566 config->save_encoder_crtcs =
8567 kcalloc(dev->mode_config.num_encoder,
8568 sizeof(struct drm_crtc *), GFP_KERNEL);
8569 if (!config->save_encoder_crtcs)
85f9eb71
DV		 8570 return -ENOMEM;
8571
1aa4b628
DV		 8572 config->save_connector_encoders =
8573 kcalloc(dev->mode_config.num_connector,
8574 sizeof(struct drm_encoder *), GFP_KERNEL);
8575 if (!config->save_connector_encoders)
85f9eb71
DV		 8576 return -ENOMEM;
8577
8578 /* Copy data. Note that driver private data is not affected.
8579 * Should anything bad happen only the expected state is
8580 * restored, not the drivers personal bookkeeping.
8581 */
85f9eb71
DV		 8582 count = 0;
8583 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 8584 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 8585 }
8586
8587 count = 0;
8588 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 8589 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 8590 }
8591
8592 return 0;
8593}
8594
8595static void intel_set_config_restore_state(struct drm_device *dev,
8596 struct intel_set_config *config)
8597{
9a935856
DV		 8598 struct intel_encoder *encoder;
8599 struct intel_connector *connector;
85f9eb71
DV		 8600 int count;
8601
85f9eb71 8602 count = 0;
9a935856
DV		 8603 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8604 encoder->new_crtc =
8605 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 8606 }
8607
8608 count = 0;
9a935856
DV		 8609 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8610 connector->new_encoder =
8611 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 8612 }
8613}
8614
e3de42b6
ID		 8615static bool
8616is_crtc_connector_off(struct drm_crtc *crtc, struct drm_connector *connectors,
8617 int num_connectors)
8618{
8619 int i;
8620
8621 for (i = 0; i < num_connectors; i++)
8622 if (connectors[i].encoder &&
8623 connectors[i].encoder->crtc == crtc &&
8624 connectors[i].dpms != DRM_MODE_DPMS_ON)
8625 return true;
8626
8627 return false;
8628}
8629
5e2b584e
DV		 8630static void
8631intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8632 struct intel_set_config *config)
8633{
8634
8635 /* We should be able to check here if the fb has the same properties
8636 * and then just flip_or_move it */
e3de42b6
ID		 8637 if (set->connectors != NULL &&
8638 is_crtc_connector_off(set->crtc, *set->connectors,
8639 set->num_connectors)) {
8640 config->mode_changed = true;
8641 } else if (set->crtc->fb != set->fb) {
5e2b584e
DV		 8642 /* If we have no fb then treat it as a full mode set */
8643 if (set->crtc->fb == NULL) {
8644 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8645 config->mode_changed = true;
8646 } else if (set->fb == NULL) {
8647 config->mode_changed = true;
72f4901e
DV		 8648 } else if (set->fb->pixel_format !=
8649 set->crtc->fb->pixel_format) {
5e2b584e 8650 config->mode_changed = true;
e3de42b6 8651 } else {
5e2b584e 8652 config->fb_changed = true;
e3de42b6 8653 }
5e2b584e
DV		 8654 }
8655
835c5873 8656 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 8657 config->fb_changed = true;
8658
8659 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8660 DRM_DEBUG_KMS("modes are different, full mode set\n");
8661 drm_mode_debug_printmodeline(&set->crtc->mode);
8662 drm_mode_debug_printmodeline(set->mode);
8663 config->mode_changed = true;
8664 }
8665}
8666
2e431051 8667static int
9a935856
DV		 8668intel_modeset_stage_output_state(struct drm_device *dev,
8669 struct drm_mode_set *set,
8670 struct intel_set_config *config)
50f56119 8671{
85f9eb71 8672 struct drm_crtc *new_crtc;
9a935856
DV		 8673 struct intel_connector *connector;
8674 struct intel_encoder *encoder;
2e431051 8675 int count, ro;
50f56119 8676
9abdda74 8677 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 8678 * of connectors. For paranoia, double-check this. */
8679 WARN_ON(!set->fb && (set->num_connectors != 0));
8680 WARN_ON(set->fb && (set->num_connectors == 0));
8681
50f56119 8682 count = 0;
9a935856
DV		 8683 list_for_each_entry(connector, &dev->mode_config.connector_list,
8684 base.head) {
8685 /* Otherwise traverse passed in connector list and get encoders
8686 * for them. */
50f56119 8687 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 8688 if (set->connectors[ro] == &connector->base) {
8689 connector->new_encoder = connector->encoder;
50f56119
DV		 8690 break;
8691 }
8692 }
8693
9a935856
DV		 8694 /* If we disable the crtc, disable all its connectors. Also, if
8695 * the connector is on the changing crtc but not on the new
8696 * connector list, disable it. */
8697 if ((!set->fb || ro == set->num_connectors) &&
8698 connector->base.encoder &&
8699 connector->base.encoder->crtc == set->crtc) {
8700 connector->new_encoder = NULL;
8701
8702 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8703 connector->base.base.id,
8704 drm_get_connector_name(&connector->base));
8705 }
8706
8707
8708 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8709 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8710 config->mode_changed = true;
50f56119
DV		 8711 }
8712 }
9a935856 8713 /* connector->new_encoder is now updated for all connectors. */
50f56119 8714
9a935856 8715 /* Update crtc of enabled connectors. */
50f56119 8716 count = 0;
9a935856
DV		 8717 list_for_each_entry(connector, &dev->mode_config.connector_list,
8718 base.head) {
8719 if (!connector->new_encoder)
50f56119
DV		 8720 continue;
8721
9a935856 8722 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8723
8724 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8725 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8726 new_crtc = set->crtc;
8727 }
8728
8729 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8730 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8731 new_crtc)) {
5e2b584e 8732 return -EINVAL;
50f56119 8733 }
9a935856
DV		 8734 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8735
8736 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8737 connector->base.base.id,
8738 drm_get_connector_name(&connector->base),
8739 new_crtc->base.id);
8740 }
8741
8742 /* Check for any encoders that needs to be disabled. */
8743 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8744 base.head) {
8745 list_for_each_entry(connector,
8746 &dev->mode_config.connector_list,
8747 base.head) {
8748 if (connector->new_encoder == encoder) {
8749 WARN_ON(!connector->new_encoder->new_crtc);
8750
8751 goto next_encoder;
8752 }
8753 }
8754 encoder->new_crtc = NULL;
8755next_encoder:
8756 /* Only now check for crtc changes so we don't miss encoders
8757 * that will be disabled. */
8758 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8759 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8760 config->mode_changed = true;
50f56119
DV		 8761 }
8762 }
9a935856 8763 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8764
2e431051
DV		 8765 return 0;
8766}
8767
8768static int intel_crtc_set_config(struct drm_mode_set *set)
8769{
8770 struct drm_device *dev;
2e431051
DV		 8771 struct drm_mode_set save_set;
8772 struct intel_set_config *config;
8773 int ret;
2e431051 8774
8d3e375e
DV		 8775 BUG_ON(!set);
8776 BUG_ON(!set->crtc);
8777 BUG_ON(!set->crtc->helper_private);
2e431051 8778
7e53f3a4
DV		 8779 /* Enforce sane interface api - has been abused by the fb helper. */
8780 BUG_ON(!set->mode && set->fb);
8781 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 8782
2e431051
DV		 8783 if (set->fb) {
8784 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8785 set->crtc->base.id, set->fb->base.id,
8786 (int)set->num_connectors, set->x, set->y);
8787 } else {
8788 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8789 }
8790
8791 dev = set->crtc->dev;
8792
8793 ret = -ENOMEM;
8794 config = kzalloc(sizeof(*config), GFP_KERNEL);
8795 if (!config)
8796 goto out_config;
8797
8798 ret = intel_set_config_save_state(dev, config);
8799 if (ret)
8800 goto out_config;
8801
8802 save_set.crtc = set->crtc;
8803 save_set.mode = &set->crtc->mode;
8804 save_set.x = set->crtc->x;
8805 save_set.y = set->crtc->y;
8806 save_set.fb = set->crtc->fb;
8807
8808 /* Compute whether we need a full modeset, only an fb base update or no
8809 * change at all. In the future we might also check whether only the
8810 * mode changed, e.g. for LVDS where we only change the panel fitter in
8811 * such cases. */
8812 intel_set_config_compute_mode_changes(set, config);
8813
9a935856 8814 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8815 if (ret)
8816 goto fail;
8817
5e2b584e 8818 if (config->mode_changed) {
c0c36b94
CW		 8819 ret = intel_set_mode(set->crtc, set->mode,
8820 set->x, set->y, set->fb);
5e2b584e 8821 } else if (config->fb_changed) {
4878cae2
VS		 8822 intel_crtc_wait_for_pending_flips(set->crtc);
8823
4f660f49 8824 ret = intel_pipe_set_base(set->crtc,
94352cf9 8825 set->x, set->y, set->fb);
50f56119
DV		 8826 }
8827
2d05eae1 8828 if (ret) {
bf67dfeb
DV		 8829 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
8830 set->crtc->base.id, ret);
50f56119 8831fail:
2d05eae1 8832 intel_set_config_restore_state(dev, config);
50f56119 8833
2d05eae1
CW		 8834 /* Try to restore the config */
8835 if (config->mode_changed &&
8836 intel_set_mode(save_set.crtc, save_set.mode,
8837 save_set.x, save_set.y, save_set.fb))
8838 DRM_ERROR("failed to restore config after modeset failure\n");
8839 }
50f56119 8840
d9e55608
DV		 8841out_config:
8842 intel_set_config_free(config);
50f56119
DV		 8843 return ret;
8844}
f6e5b160
CW		 8845
8846static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8847 .cursor_set = intel_crtc_cursor_set,
8848 .cursor_move = intel_crtc_cursor_move,
8849 .gamma_set = intel_crtc_gamma_set,
50f56119 8850 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8851 .destroy = intel_crtc_destroy,
8852 .page_flip = intel_crtc_page_flip,
8853};
8854
79f689aa
PZ		 8855static void intel_cpu_pll_init(struct drm_device *dev)
8856{
affa9354 8857 if (HAS_DDI(dev))
79f689aa
PZ		 8858 intel_ddi_pll_init(dev);
8859}
8860
5358901f
DV		 8861static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
8862 struct intel_shared_dpll *pll,
8863 struct intel_dpll_hw_state *hw_state)
ee7b9f93 8864{
5358901f 8865 uint32_t val;
ee7b9f93 8866
5358901f 8867 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 8868 hw_state->dpll = val;
8869 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
8870 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 8871
8872 return val & DPLL_VCO_ENABLE;
8873}
8874
15bdd4cf
DV		 8875static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
8876 struct intel_shared_dpll *pll)
8877{
8878 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
8879 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
8880}
8881
e7b903d2
DV		 8882static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
8883 struct intel_shared_dpll *pll)
8884{
e7b903d2
DV		 8885 /* PCH refclock must be enabled first */
8886 assert_pch_refclk_enabled(dev_priv);
8887
15bdd4cf
DV		 8888 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
8889
8890 /* Wait for the clocks to stabilize. */
8891 POSTING_READ(PCH_DPLL(pll->id));
8892 udelay(150);
8893
8894 /* The pixel multiplier can only be updated once the
8895 * DPLL is enabled and the clocks are stable.
8896 *
8897 * So write it again.
8898 */
8899 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
8900 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 8901 udelay(200);
8902}
8903
8904static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
8905 struct intel_shared_dpll *pll)
8906{
8907 struct drm_device *dev = dev_priv->dev;
8908 struct intel_crtc *crtc;
e7b903d2
DV		 8909
8910 /* Make sure no transcoder isn't still depending on us. */
8911 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
8912 if (intel_crtc_to_shared_dpll(crtc) == pll)
8913 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 8914 }
8915
15bdd4cf
DV		 8916 I915_WRITE(PCH_DPLL(pll->id), 0);
8917 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 8918 udelay(200);
8919}
8920
46edb027
DV		 8921static char *ibx_pch_dpll_names[] = {
8922 "PCH DPLL A",
8923 "PCH DPLL B",
8924};
8925
7c74ade1 8926static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 8927{
e7b903d2 8928 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 8929 int i;
8930
7c74ade1 8931 dev_priv->num_shared_dpll = 2;
ee7b9f93 8932
e72f9fbf 8933 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 8934 dev_priv->shared_dplls[i].id = i;
8935 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 8936 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 8937 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
8938 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 8939 dev_priv->shared_dplls[i].get_hw_state =
8940 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 8941 }
8942}
8943
7c74ade1
DV		 8944static void intel_shared_dpll_init(struct drm_device *dev)
8945{
e7b903d2 8946 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1
DV		 8947
8948 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8949 ibx_pch_dpll_init(dev);
8950 else
8951 dev_priv->num_shared_dpll = 0;
8952
8953 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
8954 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
8955 dev_priv->num_shared_dpll);
8956}
8957
b358d0a6 8958static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8959{
22fd0fab 8960 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8961 struct intel_crtc *intel_crtc;
8962 int i;
8963
8964 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8965 if (intel_crtc == NULL)
8966 return;
8967
8968 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8969
8970 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8971 for (i = 0; i < 256; i++) {
8972 intel_crtc->lut_r[i] = i;
8973 intel_crtc->lut_g[i] = i;
8974 intel_crtc->lut_b[i] = i;
8975 }
8976
80824003
JB		 8977 /* Swap pipes & planes for FBC on pre-965 */
8978 intel_crtc->pipe = pipe;
8979 intel_crtc->plane = pipe;
e2e767ab 8980 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8981 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8982 intel_crtc->plane = !pipe;
80824003
JB		 8983 }
8984
22fd0fab
JB		 8985 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8986 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8987 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8988 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8989
79e53945 8990 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8991}
8992
08d7b3d1 8993int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8994 struct drm_file *file)
08d7b3d1 8995{
08d7b3d1 8996 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8997 struct drm_mode_object *drmmode_obj;
8998 struct intel_crtc *crtc;
08d7b3d1 8999
1cff8f6b
DV		 9000 if (!drm_core_check_feature(dev, DRIVER_MODESET))
9001 return -ENODEV;
08d7b3d1 9002
c05422d5
DV		 9003 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9004 DRM_MODE_OBJECT_CRTC);
08d7b3d1 9005
c05422d5 9006 if (!drmmode_obj) {
08d7b3d1
CW		 9007 DRM_ERROR("no such CRTC id\n");
9008 return -EINVAL;
9009 }
9010
c05422d5
DV		 9011 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9012 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 9013
c05422d5 9014 return 0;
08d7b3d1
CW		 9015}
9016
66a9278e 9017static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 9018{
66a9278e
DV		 9019 struct drm_device *dev = encoder->base.dev;
9020 struct intel_encoder *source_encoder;
79e53945 9021 int index_mask = 0;
79e53945
JB		 9022 int entry = 0;
9023
66a9278e
DV		 9024 list_for_each_entry(source_encoder,
9025 &dev->mode_config.encoder_list, base.head) {
9026
9027 if (encoder == source_encoder)
79e53945 9028 index_mask |= (1 << entry);
66a9278e
DV		 9029
9030 /* Intel hw has only one MUX where enocoders could be cloned. */
9031 if (encoder->cloneable && source_encoder->cloneable)
9032 index_mask |= (1 << entry);
9033
79e53945
JB		 9034 entry++;
9035 }
4ef69c7a 9036
79e53945
JB		 9037 return index_mask;
9038}
9039
4d302442
CW		 9040static bool has_edp_a(struct drm_device *dev)
9041{
9042 struct drm_i915_private *dev_priv = dev->dev_private;
9043
9044 if (!IS_MOBILE(dev))
9045 return false;
9046
9047 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9048 return false;
9049
9050 if (IS_GEN5(dev) &&
9051 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9052 return false;
9053
9054 return true;
9055}
9056
79e53945
JB		 9057static void intel_setup_outputs(struct drm_device *dev)
9058{
725e30ad 9059 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 9060 struct intel_encoder *encoder;
cb0953d7 9061 bool dpd_is_edp = false;
79e53945 9062
c9093354 9063 intel_lvds_init(dev);
79e53945 9064
c40c0f5b 9065 if (!IS_ULT(dev))
79935fca 9066 intel_crt_init(dev);
cb0953d7 9067
affa9354 9068 if (HAS_DDI(dev)) {
0e72a5b5
ED		 9069 int found;
9070
9071 /* Haswell uses DDI functions to detect digital outputs */
9072 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9073 /* DDI A only supports eDP */
9074 if (found)
9075 intel_ddi_init(dev, PORT_A);
9076
9077 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9078 * register */
9079 found = I915_READ(SFUSE_STRAP);
9080
9081 if (found & SFUSE_STRAP_DDIB_DETECTED)
9082 intel_ddi_init(dev, PORT_B);
9083 if (found & SFUSE_STRAP_DDIC_DETECTED)
9084 intel_ddi_init(dev, PORT_C);
9085 if (found & SFUSE_STRAP_DDID_DETECTED)
9086 intel_ddi_init(dev, PORT_D);
9087 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 9088 int found;
270b3042
DV		 9089 dpd_is_edp = intel_dpd_is_edp(dev);
9090
9091 if (has_edp_a(dev))
9092 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 9093
dc0fa718 9094 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 9095 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 9096 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 9097 if (!found)
e2debe91 9098 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 9099 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 9100 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 9101 }
9102
dc0fa718 9103 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 9104 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 9105
dc0fa718 9106 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 9107 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 9108
5eb08b69 9109 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 9110 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 9111
270b3042 9112 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 9113 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 9114 } else if (IS_VALLEYVIEW(dev)) {
19c03924 9115 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 9116 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9117 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 9118
dc0fa718 9119 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 9120 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9121 PORT_B);
67cfc203
VS		 9122 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9123 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 9124 }
103a196f 9125 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 9126 bool found = false;
7d57382e 9127
e2debe91 9128 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9129 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 9130 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 9131 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9132 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 9133 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 9134 }
27185ae1 9135
e7281eab 9136 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9137 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 9138 }
13520b05
KH		 9139
9140 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 9141
e2debe91 9142 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9143 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 9144 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 9145 }
27185ae1 9146
e2debe91 9147 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 9148
b01f2c3a
JB		 9149 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9150 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 9151 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 9152 }
e7281eab 9153 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9154 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 9155 }
27185ae1 9156
b01f2c3a 9157 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 9158 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 9159 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 9160 } else if (IS_GEN2(dev))
79e53945
JB		 9161 intel_dvo_init(dev);
9162
103a196f 9163 if (SUPPORTS_TV(dev))
79e53945
JB		 9164 intel_tv_init(dev);
9165
4ef69c7a
CW		 9166 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9167 encoder->base.possible_crtcs = encoder->crtc_mask;
9168 encoder->base.possible_clones =
66a9278e 9169 intel_encoder_clones(encoder);
79e53945 9170 }
47356eb6 9171
dde86e2d 9172 intel_init_pch_refclk(dev);
270b3042
DV		 9173
9174 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 9175}
9176
9177static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9178{
9179 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 9180
9181 drm_framebuffer_cleanup(fb);
05394f39 9182 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 9183
9184 kfree(intel_fb);
9185}
9186
9187static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 9188 struct drm_file *file,
79e53945
JB		 9189 unsigned int *handle)
9190{
9191 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 9192 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 9193
05394f39 9194 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 9195}
9196
9197static const struct drm_framebuffer_funcs intel_fb_funcs = {
9198 .destroy = intel_user_framebuffer_destroy,
9199 .create_handle = intel_user_framebuffer_create_handle,
9200};
9201
38651674
DA		 9202int intel_framebuffer_init(struct drm_device *dev,
9203 struct intel_framebuffer *intel_fb,
308e5bcb 9204 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 9205 struct drm_i915_gem_object *obj)
79e53945 9206{
a35cdaa0 9207 int pitch_limit;
79e53945
JB		 9208 int ret;
9209
c16ed4be
CW		 9210 if (obj->tiling_mode == I915_TILING_Y) {
9211 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 9212 return -EINVAL;
c16ed4be 9213 }
57cd6508 9214
c16ed4be
CW		 9215 if (mode_cmd->pitches[0] & 63) {
9216 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9217 mode_cmd->pitches[0]);
57cd6508 9218 return -EINVAL;
c16ed4be 9219 }
57cd6508 9220
a35cdaa0
CW		 9221 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9222 pitch_limit = 32*1024;
9223 } else if (INTEL_INFO(dev)->gen >= 4) {
9224 if (obj->tiling_mode)
9225 pitch_limit = 16*1024;
9226 else
9227 pitch_limit = 32*1024;
9228 } else if (INTEL_INFO(dev)->gen >= 3) {
9229 if (obj->tiling_mode)
9230 pitch_limit = 8*1024;
9231 else
9232 pitch_limit = 16*1024;
9233 } else
9234 /* XXX DSPC is limited to 4k tiled */
9235 pitch_limit = 8*1024;
9236
9237 if (mode_cmd->pitches[0] > pitch_limit) {
9238 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9239 obj->tiling_mode ? "tiled" : "linear",
9240 mode_cmd->pitches[0], pitch_limit);
5d7bd705 9241 return -EINVAL;
c16ed4be 9242 }
5d7bd705
VS		 9243
9244 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 9245 mode_cmd->pitches[0] != obj->stride) {
9246 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9247 mode_cmd->pitches[0], obj->stride);
5d7bd705 9248 return -EINVAL;
c16ed4be 9249 }
5d7bd705 9250
57779d06 9251 /* Reject formats not supported by any plane early. */
308e5bcb 9252 switch (mode_cmd->pixel_format) {
57779d06 9253 case DRM_FORMAT_C8:
04b3924d
VS		 9254 case DRM_FORMAT_RGB565:
9255 case DRM_FORMAT_XRGB8888:
9256 case DRM_FORMAT_ARGB8888:
57779d06
VS		 9257 break;
9258 case DRM_FORMAT_XRGB1555:
9259 case DRM_FORMAT_ARGB1555:
c16ed4be 9260 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 9261 DRM_DEBUG("unsupported pixel format: %s\n",
9262 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9263 return -EINVAL;
c16ed4be 9264 }
57779d06
VS		 9265 break;
9266 case DRM_FORMAT_XBGR8888:
9267 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 9268 case DRM_FORMAT_XRGB2101010:
9269 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 9270 case DRM_FORMAT_XBGR2101010:
9271 case DRM_FORMAT_ABGR2101010:
c16ed4be 9272 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 9273 DRM_DEBUG("unsupported pixel format: %s\n",
9274 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9275 return -EINVAL;
c16ed4be 9276 }
b5626747 9277 break;
04b3924d
VS		 9278 case DRM_FORMAT_YUYV:
9279 case DRM_FORMAT_UYVY:
9280 case DRM_FORMAT_YVYU:
9281 case DRM_FORMAT_VYUY:
c16ed4be 9282 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 9283 DRM_DEBUG("unsupported pixel format: %s\n",
9284 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9285 return -EINVAL;
c16ed4be 9286 }
57cd6508
CW		 9287 break;
9288 default:
4ee62c76
VS		 9289 DRM_DEBUG("unsupported pixel format: %s\n",
9290 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 9291 return -EINVAL;
9292 }
9293
90f9a336
VS		 9294 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9295 if (mode_cmd->offsets[0] != 0)
9296 return -EINVAL;
9297
c7d73f6a
DV		 9298 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9299 intel_fb->obj = obj;
9300
79e53945
JB		 9301 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9302 if (ret) {
9303 DRM_ERROR("framebuffer init failed %d\n", ret);
9304 return ret;
9305 }
9306
79e53945
JB		 9307 return 0;
9308}
9309
79e53945
JB		 9310static struct drm_framebuffer *
9311intel_user_framebuffer_create(struct drm_device *dev,
9312 struct drm_file *filp,
308e5bcb 9313 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 9314{
05394f39 9315 struct drm_i915_gem_object *obj;
79e53945 9316
308e5bcb
JB		 9317 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9318 mode_cmd->handles[0]));
c8725226 9319 if (&obj->base == NULL)
cce13ff7 9320 return ERR_PTR(-ENOENT);
79e53945 9321
d2dff872 9322 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 9323}
9324
79e53945 9325static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 9326 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 9327 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 9328};
9329
e70236a8
JB		 9330/* Set up chip specific display functions */
9331static void intel_init_display(struct drm_device *dev)
9332{
9333 struct drm_i915_private *dev_priv = dev->dev_private;
9334
ee9300bb
DV		 9335 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9336 dev_priv->display.find_dpll = g4x_find_best_dpll;
9337 else if (IS_VALLEYVIEW(dev))
9338 dev_priv->display.find_dpll = vlv_find_best_dpll;
9339 else if (IS_PINEVIEW(dev))
9340 dev_priv->display.find_dpll = pnv_find_best_dpll;
9341 else
9342 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9343
affa9354 9344 if (HAS_DDI(dev)) {
0e8ffe1b 9345 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 9346 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 9347 dev_priv->display.crtc_enable = haswell_crtc_enable;
9348 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 9349 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 9350 dev_priv->display.update_plane = ironlake_update_plane;
9351 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 9352 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f1f644dc 9353 dev_priv->display.get_clock = ironlake_crtc_clock_get;
f564048e 9354 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 9355 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9356 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 9357 dev_priv->display.off = ironlake_crtc_off;
17638cd6 9358 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 9359 } else if (IS_VALLEYVIEW(dev)) {
9360 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f1f644dc 9361 dev_priv->display.get_clock = i9xx_crtc_clock_get;
89b667f8
JB		 9362 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9363 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9364 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9365 dev_priv->display.off = i9xx_crtc_off;
9366 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9367 } else {
0e8ffe1b 9368 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f1f644dc 9369 dev_priv->display.get_clock = i9xx_crtc_clock_get;
f564048e 9370 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 9371 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9372 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 9373 dev_priv->display.off = i9xx_crtc_off;
17638cd6 9374 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9375 }
e70236a8 9376
e70236a8 9377 /* Returns the core display clock speed */
25eb05fc
JB		 9378 if (IS_VALLEYVIEW(dev))
9379 dev_priv->display.get_display_clock_speed =
9380 valleyview_get_display_clock_speed;
9381 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 9382 dev_priv->display.get_display_clock_speed =
9383 i945_get_display_clock_speed;
9384 else if (IS_I915G(dev))
9385 dev_priv->display.get_display_clock_speed =
9386 i915_get_display_clock_speed;
f2b115e6 9387 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 9388 dev_priv->display.get_display_clock_speed =
9389 i9xx_misc_get_display_clock_speed;
9390 else if (IS_I915GM(dev))
9391 dev_priv->display.get_display_clock_speed =
9392 i915gm_get_display_clock_speed;
9393 else if (IS_I865G(dev))
9394 dev_priv->display.get_display_clock_speed =
9395 i865_get_display_clock_speed;
f0f8a9ce 9396 else if (IS_I85X(dev))
e70236a8
JB		 9397 dev_priv->display.get_display_clock_speed =
9398 i855_get_display_clock_speed;
9399 else /* 852, 830 */
9400 dev_priv->display.get_display_clock_speed =
9401 i830_get_display_clock_speed;
9402
7f8a8569 9403 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 9404 if (IS_GEN5(dev)) {
674cf967 9405 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 9406 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 9407 } else if (IS_GEN6(dev)) {
674cf967 9408 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 9409 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 9410 } else if (IS_IVYBRIDGE(dev)) {
9411 /* FIXME: detect B0+ stepping and use auto training */
9412 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 9413 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 9414 dev_priv->display.modeset_global_resources =
9415 ivb_modeset_global_resources;
c82e4d26
ED		 9416 } else if (IS_HASWELL(dev)) {
9417 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 9418 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 9419 dev_priv->display.modeset_global_resources =
9420 haswell_modeset_global_resources;
a0e63c22 9421 }
6067aaea 9422 } else if (IS_G4X(dev)) {
e0dac65e 9423 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 9424 }
8c9f3aaf
JB		 9425
9426 /* Default just returns -ENODEV to indicate unsupported */
9427 dev_priv->display.queue_flip = intel_default_queue_flip;
9428
9429 switch (INTEL_INFO(dev)->gen) {
9430 case 2:
9431 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9432 break;
9433
9434 case 3:
9435 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9436 break;
9437
9438 case 4:
9439 case 5:
9440 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9441 break;
9442
9443 case 6:
9444 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9445 break;
7c9017e5
JB		 9446 case 7:
9447 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9448 break;
8c9f3aaf 9449 }
e70236a8
JB		 9450}
9451
b690e96c
JB		 9452/*
9453 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9454 * resume, or other times. This quirk makes sure that's the case for
9455 * affected systems.
9456 */
0206e353 9457static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 9458{
9459 struct drm_i915_private *dev_priv = dev->dev_private;
9460
9461 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 9462 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 9463}
9464
435793df
KP		 9465/*
9466 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9467 */
9468static void quirk_ssc_force_disable(struct drm_device *dev)
9469{
9470 struct drm_i915_private *dev_priv = dev->dev_private;
9471 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 9472 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 9473}
9474
4dca20ef 9475/*
5a15ab5b
CE		 9476 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9477 * brightness value
4dca20ef
CE		 9478 */
9479static void quirk_invert_brightness(struct drm_device *dev)
9480{
9481 struct drm_i915_private *dev_priv = dev->dev_private;
9482 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 9483 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 9484}
9485
b690e96c
JB		 9486struct intel_quirk {
9487 int device;
9488 int subsystem_vendor;
9489 int subsystem_device;
9490 void (*hook)(struct drm_device *dev);
9491};
9492
5f85f176
EE		 9493/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9494struct intel_dmi_quirk {
9495 void (*hook)(struct drm_device *dev);
9496 const struct dmi_system_id (*dmi_id_list)[];
9497};
9498
9499static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9500{
9501 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9502 return 1;
9503}
9504
9505static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9506 {
9507 .dmi_id_list = &(const struct dmi_system_id[]) {
9508 {
9509 .callback = intel_dmi_reverse_brightness,
9510 .ident = "NCR Corporation",
9511 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9512 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9513 },
9514 },
9515 { } /* terminating entry */
9516 },
9517 .hook = quirk_invert_brightness,
9518 },
9519};
9520
c43b5634 9521static struct intel_quirk intel_quirks[] = {
b690e96c 9522 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 9523 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 9524
b690e96c
JB		 9525 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9526 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9527
b690e96c
JB		 9528 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9529 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9530
ccd0d36e 9531 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 9532 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 9533 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 9534
9535 /* Lenovo U160 cannot use SSC on LVDS */
9536 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 9537
9538 /* Sony Vaio Y cannot use SSC on LVDS */
9539 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 9540
9541 /* Acer Aspire 5734Z must invert backlight brightness */
9542 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 9543
9544 /* Acer/eMachines G725 */
9545 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 9546
9547 /* Acer/eMachines e725 */
9548 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 9549
9550 /* Acer/Packard Bell NCL20 */
9551 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 9552
9553 /* Acer Aspire 4736Z */
9554 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 9555};
9556
9557static void intel_init_quirks(struct drm_device *dev)
9558{
9559 struct pci_dev *d = dev->pdev;
9560 int i;
9561
9562 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9563 struct intel_quirk *q = &intel_quirks[i];
9564
9565 if (d->device == q->device &&
9566 (d->subsystem_vendor == q->subsystem_vendor ||
9567 q->subsystem_vendor == PCI_ANY_ID) &&
9568 (d->subsystem_device == q->subsystem_device ||
9569 q->subsystem_device == PCI_ANY_ID))
9570 q->hook(dev);
9571 }
5f85f176
EE		 9572 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9573 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9574 intel_dmi_quirks[i].hook(dev);
9575 }
b690e96c
JB		 9576}
9577
9cce37f4
JB		 9578/* Disable the VGA plane that we never use */
9579static void i915_disable_vga(struct drm_device *dev)
9580{
9581 struct drm_i915_private *dev_priv = dev->dev_private;
9582 u8 sr1;
766aa1c4 9583 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 9584
9585 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 9586 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 9587 sr1 = inb(VGA_SR_DATA);
9588 outb(sr1 | 1<<5, VGA_SR_DATA);
9589 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9590 udelay(300);
9591
9592 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9593 POSTING_READ(vga_reg);
9594}
9595
f817586c
DV		 9596void intel_modeset_init_hw(struct drm_device *dev)
9597{
fa42e23c 9598 intel_init_power_well(dev);
0232e927 9599
a8f78b58
ED		 9600 intel_prepare_ddi(dev);
9601
f817586c
DV		 9602 intel_init_clock_gating(dev);
9603
79f5b2c7 9604 mutex_lock(&dev->struct_mutex);
8090c6b9 9605 intel_enable_gt_powersave(dev);
79f5b2c7 9606 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 9607}
9608
7d708ee4
ID		 9609void intel_modeset_suspend_hw(struct drm_device *dev)
9610{
9611 intel_suspend_hw(dev);
9612}
9613
79e53945
JB		 9614void intel_modeset_init(struct drm_device *dev)
9615{
652c393a 9616 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 9617 int i, j, ret;
79e53945
JB		 9618
9619 drm_mode_config_init(dev);
9620
9621 dev->mode_config.min_width = 0;
9622 dev->mode_config.min_height = 0;
9623
019d96cb
DA		 9624 dev->mode_config.preferred_depth = 24;
9625 dev->mode_config.prefer_shadow = 1;
9626
e6ecefaa 9627 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 9628
b690e96c
JB		 9629 intel_init_quirks(dev);
9630
1fa61106
ED		 9631 intel_init_pm(dev);
9632
e3c74757
BW		 9633 if (INTEL_INFO(dev)->num_pipes == 0)
9634 return;
9635
e70236a8
JB		 9636 intel_init_display(dev);
9637
a6c45cf0
CW		 9638 if (IS_GEN2(dev)) {
9639 dev->mode_config.max_width = 2048;
9640 dev->mode_config.max_height = 2048;
9641 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9642 dev->mode_config.max_width = 4096;
9643 dev->mode_config.max_height = 4096;
79e53945 9644 } else {
a6c45cf0
CW		 9645 dev->mode_config.max_width = 8192;
9646 dev->mode_config.max_height = 8192;
79e53945 9647 }
5d4545ae 9648 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 9649
28c97730 9650 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 9651 INTEL_INFO(dev)->num_pipes,
9652 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 9653
7eb552ae 9654 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
79e53945 9655 intel_crtc_init(dev, i);
7f1f3851
JB		 9656 for (j = 0; j < dev_priv->num_plane; j++) {
9657 ret = intel_plane_init(dev, i, j);
9658 if (ret)
06da8da2
VS		 9659 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9660 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 9661 }
79e53945
JB		 9662 }
9663
79f689aa 9664 intel_cpu_pll_init(dev);
e72f9fbf 9665 intel_shared_dpll_init(dev);
ee7b9f93 9666
9cce37f4
JB		 9667 /* Just disable it once at startup */
9668 i915_disable_vga(dev);
79e53945 9669 intel_setup_outputs(dev);
11be49eb
CW		 9670
9671 /* Just in case the BIOS is doing something questionable. */
9672 intel_disable_fbc(dev);
2c7111db
CW		 9673}
9674
24929352
DV		 9675static void
9676intel_connector_break_all_links(struct intel_connector *connector)
9677{
9678 connector->base.dpms = DRM_MODE_DPMS_OFF;
9679 connector->base.encoder = NULL;
9680 connector->encoder->connectors_active = false;
9681 connector->encoder->base.crtc = NULL;
9682}
9683
7fad798e
DV		 9684static void intel_enable_pipe_a(struct drm_device *dev)
9685{
9686 struct intel_connector *connector;
9687 struct drm_connector *crt = NULL;
9688 struct intel_load_detect_pipe load_detect_temp;
9689
9690 /* We can't just switch on the pipe A, we need to set things up with a
9691 * proper mode and output configuration. As a gross hack, enable pipe A
9692 * by enabling the load detect pipe once. */
9693 list_for_each_entry(connector,
9694 &dev->mode_config.connector_list,
9695 base.head) {
9696 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9697 crt = &connector->base;
9698 break;
9699 }
9700 }
9701
9702 if (!crt)
9703 return;
9704
9705 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9706 intel_release_load_detect_pipe(crt, &load_detect_temp);
9707
652c393a 9708
7fad798e
DV		 9709}
9710
fa555837
DV		 9711static bool
9712intel_check_plane_mapping(struct intel_crtc *crtc)
9713{
7eb552ae
BW		 9714 struct drm_device *dev = crtc->base.dev;
9715 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 9716 u32 reg, val;
9717
7eb552ae 9718 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 9719 return true;
9720
9721 reg = DSPCNTR(!crtc->plane);
9722 val = I915_READ(reg);
9723
9724 if ((val & DISPLAY_PLANE_ENABLE) &&
9725 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9726 return false;
9727
9728 return true;
9729}
9730
24929352
DV		 9731static void intel_sanitize_crtc(struct intel_crtc *crtc)
9732{
9733 struct drm_device *dev = crtc->base.dev;
9734 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 9735 u32 reg;
24929352 9736
24929352 9737 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 9738 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 9739 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9740
9741 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 9742 * disable the crtc (and hence change the state) if it is wrong. Note
9743 * that gen4+ has a fixed plane -> pipe mapping. */
9744 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 9745 struct intel_connector *connector;
9746 bool plane;
9747
24929352
DV		 9748 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9749 crtc->base.base.id);
9750
9751 /* Pipe has the wrong plane attached and the plane is active.
9752 * Temporarily change the plane mapping and disable everything
9753 * ... */
9754 plane = crtc->plane;
9755 crtc->plane = !plane;
9756 dev_priv->display.crtc_disable(&crtc->base);
9757 crtc->plane = plane;
9758
9759 /* ... and break all links. */
9760 list_for_each_entry(connector, &dev->mode_config.connector_list,
9761 base.head) {
9762 if (connector->encoder->base.crtc != &crtc->base)
9763 continue;
9764
9765 intel_connector_break_all_links(connector);
9766 }
9767
9768 WARN_ON(crtc->active);
9769 crtc->base.enabled = false;
9770 }
24929352 9771
7fad798e
DV		 9772 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9773 crtc->pipe == PIPE_A && !crtc->active) {
9774 /* BIOS forgot to enable pipe A, this mostly happens after
9775 * resume. Force-enable the pipe to fix this, the update_dpms
9776 * call below we restore the pipe to the right state, but leave
9777 * the required bits on. */
9778 intel_enable_pipe_a(dev);
9779 }
9780
24929352
DV		 9781 /* Adjust the state of the output pipe according to whether we
9782 * have active connectors/encoders. */
9783 intel_crtc_update_dpms(&crtc->base);
9784
9785 if (crtc->active != crtc->base.enabled) {
9786 struct intel_encoder *encoder;
9787
9788 /* This can happen either due to bugs in the get_hw_state
9789 * functions or because the pipe is force-enabled due to the
9790 * pipe A quirk. */
9791 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9792 crtc->base.base.id,
9793 crtc->base.enabled ? "enabled" : "disabled",
9794 crtc->active ? "enabled" : "disabled");
9795
9796 crtc->base.enabled = crtc->active;
9797
9798 /* Because we only establish the connector -> encoder ->
9799 * crtc links if something is active, this means the
9800 * crtc is now deactivated. Break the links. connector
9801 * -> encoder links are only establish when things are
9802 * actually up, hence no need to break them. */
9803 WARN_ON(crtc->active);
9804
9805 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9806 WARN_ON(encoder->connectors_active);
9807 encoder->base.crtc = NULL;
9808 }
9809 }
9810}
9811
9812static void intel_sanitize_encoder(struct intel_encoder *encoder)
9813{
9814 struct intel_connector *connector;
9815 struct drm_device *dev = encoder->base.dev;
9816
9817 /* We need to check both for a crtc link (meaning that the
9818 * encoder is active and trying to read from a pipe) and the
9819 * pipe itself being active. */
9820 bool has_active_crtc = encoder->base.crtc &&
9821 to_intel_crtc(encoder->base.crtc)->active;
9822
9823 if (encoder->connectors_active && !has_active_crtc) {
9824 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9825 encoder->base.base.id,
9826 drm_get_encoder_name(&encoder->base));
9827
9828 /* Connector is active, but has no active pipe. This is
9829 * fallout from our resume register restoring. Disable
9830 * the encoder manually again. */
9831 if (encoder->base.crtc) {
9832 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9833 encoder->base.base.id,
9834 drm_get_encoder_name(&encoder->base));
9835 encoder->disable(encoder);
9836 }
9837
9838 /* Inconsistent output/port/pipe state happens presumably due to
9839 * a bug in one of the get_hw_state functions. Or someplace else
9840 * in our code, like the register restore mess on resume. Clamp
9841 * things to off as a safer default. */
9842 list_for_each_entry(connector,
9843 &dev->mode_config.connector_list,
9844 base.head) {
9845 if (connector->encoder != encoder)
9846 continue;
9847
9848 intel_connector_break_all_links(connector);
9849 }
9850 }
9851 /* Enabled encoders without active connectors will be fixed in
9852 * the crtc fixup. */
9853}
9854
44cec740 9855void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9856{
9857 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9858 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9859
9860 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9861 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9862 i915_disable_vga(dev);
0fde901f
KM		 9863 }
9864}
9865
30e984df 9866static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 9867{
9868 struct drm_i915_private *dev_priv = dev->dev_private;
9869 enum pipe pipe;
24929352
DV		 9870 struct intel_crtc *crtc;
9871 struct intel_encoder *encoder;
9872 struct intel_connector *connector;
5358901f 9873 int i;
24929352 9874
0e8ffe1b
DV		 9875 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9876 base.head) {
88adfff1 9877 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 9878
0e8ffe1b
DV		 9879 crtc->active = dev_priv->display.get_pipe_config(crtc,
9880 &crtc->config);
24929352
DV		 9881
9882 crtc->base.enabled = crtc->active;
9883
9884 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9885 crtc->base.base.id,
9886 crtc->active ? "enabled" : "disabled");
9887 }
9888
5358901f 9889 /* FIXME: Smash this into the new shared dpll infrastructure. */
affa9354 9890 if (HAS_DDI(dev))
6441ab5f
PZ		 9891 intel_ddi_setup_hw_pll_state(dev);
9892
5358901f
DV		 9893 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9894 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9895
9896 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
9897 pll->active = 0;
9898 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9899 base.head) {
9900 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9901 pll->active++;
9902 }
9903 pll->refcount = pll->active;
9904
9905 DRM_DEBUG_KMS("%s hw state readout: refcount %i\n",
9906 pll->name, pll->refcount);
9907 }
9908
24929352
DV		 9909 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9910 base.head) {
9911 pipe = 0;
9912
9913 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 9914 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9915 encoder->base.crtc = &crtc->base;
f1f644dc
JB		 9916 if (encoder->get_config &&
9917 dev_priv->display.get_clock) {
045ac3b5 9918 encoder->get_config(encoder, &crtc->config);
f1f644dc
JB		 9919 dev_priv->display.get_clock(crtc,
9920 &crtc->config);
9921 }
24929352
DV		 9922 } else {
9923 encoder->base.crtc = NULL;
9924 }
9925
9926 encoder->connectors_active = false;
9927 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9928 encoder->base.base.id,
9929 drm_get_encoder_name(&encoder->base),
9930 encoder->base.crtc ? "enabled" : "disabled",
9931 pipe);
9932 }
9933
9934 list_for_each_entry(connector, &dev->mode_config.connector_list,
9935 base.head) {
9936 if (connector->get_hw_state(connector)) {
9937 connector->base.dpms = DRM_MODE_DPMS_ON;
9938 connector->encoder->connectors_active = true;
9939 connector->base.encoder = &connector->encoder->base;
9940 } else {
9941 connector->base.dpms = DRM_MODE_DPMS_OFF;
9942 connector->base.encoder = NULL;
9943 }
9944 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9945 connector->base.base.id,
9946 drm_get_connector_name(&connector->base),
9947 connector->base.encoder ? "enabled" : "disabled");
9948 }
30e984df
DV		 9949}
9950
9951/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9952 * and i915 state tracking structures. */
9953void intel_modeset_setup_hw_state(struct drm_device *dev,
9954 bool force_restore)
9955{
9956 struct drm_i915_private *dev_priv = dev->dev_private;
9957 enum pipe pipe;
9958 struct drm_plane *plane;
9959 struct intel_crtc *crtc;
9960 struct intel_encoder *encoder;
9961
9962 intel_modeset_readout_hw_state(dev);
24929352
DV		 9963
9964 /* HW state is read out, now we need to sanitize this mess. */
9965 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9966 base.head) {
9967 intel_sanitize_encoder(encoder);
9968 }
9969
9970 for_each_pipe(pipe) {
9971 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9972 intel_sanitize_crtc(crtc);
c0b03411 9973 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 9974 }
9a935856 9975
45e2b5f6 9976 if (force_restore) {
f30da187
DV		 9977 /*
9978 * We need to use raw interfaces for restoring state to avoid
9979 * checking (bogus) intermediate states.
9980 */
45e2b5f6 9981 for_each_pipe(pipe) {
b5644d05
JB		 9982 struct drm_crtc *crtc =
9983 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 9984
9985 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9986 crtc->fb);
45e2b5f6 9987 }
b5644d05
JB		 9988 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9989 intel_plane_restore(plane);
0fde901f
KM		 9990
9991 i915_redisable_vga(dev);
45e2b5f6
DV		 9992 } else {
9993 intel_modeset_update_staged_output_state(dev);
9994 }
8af6cf88
DV		 9995
9996 intel_modeset_check_state(dev);
2e938892
DV		 9997
9998 drm_mode_config_reset(dev);
2c7111db
CW		 9999}
10000
10001void intel_modeset_gem_init(struct drm_device *dev)
10002{
1833b134 10003 intel_modeset_init_hw(dev);
02e792fb
DV		 10004
10005 intel_setup_overlay(dev);
24929352 10006
45e2b5f6 10007 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 10008}
10009
10010void intel_modeset_cleanup(struct drm_device *dev)
10011{
652c393a
JB		 10012 struct drm_i915_private *dev_priv = dev->dev_private;
10013 struct drm_crtc *crtc;
10014 struct intel_crtc *intel_crtc;
10015
fd0c0642
DV		 10016 /*
10017 * Interrupts and polling as the first thing to avoid creating havoc.
10018 * Too much stuff here (turning of rps, connectors, ...) would
10019 * experience fancy races otherwise.
10020 */
10021 drm_irq_uninstall(dev);
10022 cancel_work_sync(&dev_priv->hotplug_work);
10023 /*
10024 * Due to the hpd irq storm handling the hotplug work can re-arm the
10025 * poll handlers. Hence disable polling after hpd handling is shut down.
10026 */
f87ea761 10027 drm_kms_helper_poll_fini(dev);
fd0c0642 10028
652c393a
JB		 10029 mutex_lock(&dev->struct_mutex);
10030
723bfd70
JB		 10031 intel_unregister_dsm_handler();
10032
652c393a
JB		 10033 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10034 /* Skip inactive CRTCs */
10035 if (!crtc->fb)
10036 continue;
10037
10038 intel_crtc = to_intel_crtc(crtc);
3dec0095 10039 intel_increase_pllclock(crtc);
652c393a
JB		 10040 }
10041
973d04f9 10042 intel_disable_fbc(dev);
e70236a8 10043
8090c6b9 10044 intel_disable_gt_powersave(dev);
0cdab21f 10045
930ebb46
DV		 10046 ironlake_teardown_rc6(dev);
10047
69341a5e
KH		 10048 mutex_unlock(&dev->struct_mutex);
10049
1630fe75
CW		 10050 /* flush any delayed tasks or pending work */
10051 flush_scheduled_work();
10052
dc652f90
JN		 10053 /* destroy backlight, if any, before the connectors */
10054 intel_panel_destroy_backlight(dev);
10055
79e53945 10056 drm_mode_config_cleanup(dev);
4d7bb011
DV		 10057
10058 intel_cleanup_overlay(dev);
79e53945
JB		 10059}
10060
f1c79df3
ZW		 10061/*
10062 * Return which encoder is currently attached for connector.
10063 */
df0e9248 10064struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 10065{
df0e9248
CW		 10066 return &intel_attached_encoder(connector)->base;
10067}
f1c79df3 10068
df0e9248
CW		 10069void intel_connector_attach_encoder(struct intel_connector *connector,
10070 struct intel_encoder *encoder)
10071{
10072 connector->encoder = encoder;
10073 drm_mode_connector_attach_encoder(&connector->base,
10074 &encoder->base);
79e53945 10075}
28d52043
DA		 10076
10077/*
10078 * set vga decode state - true == enable VGA decode
10079 */
10080int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10081{
10082 struct drm_i915_private *dev_priv = dev->dev_private;
10083 u16 gmch_ctrl;
10084
10085 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10086 if (state)
10087 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10088 else
10089 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10090 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10091 return 0;
10092}
c4a1d9e4
CW		 10093
10094#ifdef CONFIG_DEBUG_FS
10095#include <linux/seq_file.h>
10096
10097struct intel_display_error_state {
ff57f1b0
PZ		 10098
10099 u32 power_well_driver;
10100
c4a1d9e4
CW		 10101 struct intel_cursor_error_state {
10102 u32 control;
10103 u32 position;
10104 u32 base;
10105 u32 size;
52331309 10106 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 10107
10108 struct intel_pipe_error_state {
ff57f1b0 10109 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 10110 u32 conf;
10111 u32 source;
10112
10113 u32 htotal;
10114 u32 hblank;
10115 u32 hsync;
10116 u32 vtotal;
10117 u32 vblank;
10118 u32 vsync;
52331309 10119 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 10120
10121 struct intel_plane_error_state {
10122 u32 control;
10123 u32 stride;
10124 u32 size;
10125 u32 pos;
10126 u32 addr;
10127 u32 surface;
10128 u32 tile_offset;
52331309 10129 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 10130};
10131
10132struct intel_display_error_state *
10133intel_display_capture_error_state(struct drm_device *dev)
10134{
0206e353 10135 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 10136 struct intel_display_error_state *error;
702e7a56 10137 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 10138 int i;
10139
10140 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10141 if (error == NULL)
10142 return NULL;
10143
ff57f1b0
PZ		 10144 if (HAS_POWER_WELL(dev))
10145 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10146
52331309 10147 for_each_pipe(i) {
702e7a56 10148 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
ff57f1b0 10149 error->pipe[i].cpu_transcoder = cpu_transcoder;
702e7a56 10150
a18c4c3d
PZ		 10151 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10152 error->cursor[i].control = I915_READ(CURCNTR(i));
10153 error->cursor[i].position = I915_READ(CURPOS(i));
10154 error->cursor[i].base = I915_READ(CURBASE(i));
10155 } else {
10156 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10157 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10158 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10159 }
c4a1d9e4
CW		 10160
10161 error->plane[i].control = I915_READ(DSPCNTR(i));
10162 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 10163 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 10164 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 10165 error->plane[i].pos = I915_READ(DSPPOS(i));
10166 }
ca291363
PZ		 10167 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10168 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 10169 if (INTEL_INFO(dev)->gen >= 4) {
10170 error->plane[i].surface = I915_READ(DSPSURF(i));
10171 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10172 }
10173
702e7a56 10174 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 10175 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 10176 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10177 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10178 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10179 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10180 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10181 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 10182 }
10183
12d217c7
PZ		 10184 /* In the code above we read the registers without checking if the power
10185 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10186 * prevent the next I915_WRITE from detecting it and printing an error
10187 * message. */
10188 if (HAS_POWER_WELL(dev))
10189 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
10190
c4a1d9e4
CW		 10191 return error;
10192}
10193
edc3d884
MK		 10194#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10195
c4a1d9e4 10196void
edc3d884 10197intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 10198 struct drm_device *dev,
10199 struct intel_display_error_state *error)
10200{
10201 int i;
10202
edc3d884 10203 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 10204 if (HAS_POWER_WELL(dev))
edc3d884 10205 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 10206 error->power_well_driver);
52331309 10207 for_each_pipe(i) {
edc3d884
MK		 10208 err_printf(m, "Pipe [%d]:\n", i);
10209 err_printf(m, " CPU transcoder: %c\n",
ff57f1b0 10210 transcoder_name(error->pipe[i].cpu_transcoder));
edc3d884
MK		 10211 err_printf(m, " CONF: %08x\n", error->pipe[i].conf);
10212 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
10213 err_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
10214 err_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
10215 err_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
10216 err_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
10217 err_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
10218 err_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
10219
10220 err_printf(m, "Plane [%d]:\n", i);
10221 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
10222 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 10223 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 10224 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
10225 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 10226 }
4b71a570 10227 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 10228 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 10229 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 10230 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
10231 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 10232 }
10233
edc3d884
MK		 10234 err_printf(m, "Cursor [%d]:\n", i);
10235 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
10236 err_printf(m, " POS: %08x\n", error->cursor[i].position);
10237 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4
CW		 10238 }
10239}
10240#endif
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