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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
760285e7 DH |
40 | #include <drm/drm_dp_helper.h> |
41 | #include <drm/drm_crtc_helper.h> | |
c0f372b3 | 42 | #include <linux/dma_remapping.h> |
79e53945 | 43 | |
0206e353 | 44 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type); |
3dec0095 | 45 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
6b383a7f | 46 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 JB |
47 | |
48 | typedef struct { | |
0206e353 AJ |
49 | /* given values */ |
50 | int n; | |
51 | int m1, m2; | |
52 | int p1, p2; | |
53 | /* derived values */ | |
54 | int dot; | |
55 | int vco; | |
56 | int m; | |
57 | int p; | |
79e53945 JB |
58 | } intel_clock_t; |
59 | ||
60 | typedef struct { | |
0206e353 | 61 | int min, max; |
79e53945 JB |
62 | } intel_range_t; |
63 | ||
64 | typedef struct { | |
0206e353 AJ |
65 | int dot_limit; |
66 | int p2_slow, p2_fast; | |
79e53945 JB |
67 | } intel_p2_t; |
68 | ||
69 | #define INTEL_P2_NUM 2 | |
d4906093 ML |
70 | typedef struct intel_limit intel_limit_t; |
71 | struct intel_limit { | |
0206e353 AJ |
72 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
73 | intel_p2_t p2; | |
f4808ab8 VS |
74 | /** |
75 | * find_pll() - Find the best values for the PLL | |
76 | * @limit: limits for the PLL | |
77 | * @crtc: current CRTC | |
78 | * @target: target frequency in kHz | |
79 | * @refclk: reference clock frequency in kHz | |
80 | * @match_clock: if provided, @best_clock P divider must | |
81 | * match the P divider from @match_clock | |
82 | * used for LVDS downclocking | |
83 | * @best_clock: best PLL values found | |
84 | * | |
85 | * Returns true on success, false on failure. | |
86 | */ | |
87 | bool (*find_pll)(const intel_limit_t *limit, | |
88 | struct drm_crtc *crtc, | |
89 | int target, int refclk, | |
90 | intel_clock_t *match_clock, | |
91 | intel_clock_t *best_clock); | |
d4906093 | 92 | }; |
79e53945 | 93 | |
2377b741 JB |
94 | /* FDI */ |
95 | #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */ | |
96 | ||
d2acd215 DV |
97 | int |
98 | intel_pch_rawclk(struct drm_device *dev) | |
99 | { | |
100 | struct drm_i915_private *dev_priv = dev->dev_private; | |
101 | ||
102 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
103 | ||
104 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
105 | } | |
106 | ||
d4906093 ML |
107 | static bool |
108 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
109 | int target, int refclk, intel_clock_t *match_clock, |
110 | intel_clock_t *best_clock); | |
d4906093 ML |
111 | static bool |
112 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
113 | int target, int refclk, intel_clock_t *match_clock, |
114 | intel_clock_t *best_clock); | |
79e53945 | 115 | |
a4fc5ed6 KP |
116 | static bool |
117 | intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc, | |
cec2f356 SP |
118 | int target, int refclk, intel_clock_t *match_clock, |
119 | intel_clock_t *best_clock); | |
5eb08b69 | 120 | static bool |
f2b115e6 | 121 | intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc, |
cec2f356 SP |
122 | int target, int refclk, intel_clock_t *match_clock, |
123 | intel_clock_t *best_clock); | |
a4fc5ed6 | 124 | |
a0c4da24 JB |
125 | static bool |
126 | intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc, | |
127 | int target, int refclk, intel_clock_t *match_clock, | |
128 | intel_clock_t *best_clock); | |
129 | ||
021357ac CW |
130 | static inline u32 /* units of 100MHz */ |
131 | intel_fdi_link_freq(struct drm_device *dev) | |
132 | { | |
8b99e68c CW |
133 | if (IS_GEN5(dev)) { |
134 | struct drm_i915_private *dev_priv = dev->dev_private; | |
135 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
136 | } else | |
137 | return 27; | |
021357ac CW |
138 | } |
139 | ||
e4b36699 | 140 | static const intel_limit_t intel_limits_i8xx_dvo = { |
0206e353 AJ |
141 | .dot = { .min = 25000, .max = 350000 }, |
142 | .vco = { .min = 930000, .max = 1400000 }, | |
143 | .n = { .min = 3, .max = 16 }, | |
144 | .m = { .min = 96, .max = 140 }, | |
145 | .m1 = { .min = 18, .max = 26 }, | |
146 | .m2 = { .min = 6, .max = 16 }, | |
147 | .p = { .min = 4, .max = 128 }, | |
148 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
149 | .p2 = { .dot_limit = 165000, |
150 | .p2_slow = 4, .p2_fast = 2 }, | |
d4906093 | 151 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
152 | }; |
153 | ||
154 | static const intel_limit_t intel_limits_i8xx_lvds = { | |
0206e353 AJ |
155 | .dot = { .min = 25000, .max = 350000 }, |
156 | .vco = { .min = 930000, .max = 1400000 }, | |
157 | .n = { .min = 3, .max = 16 }, | |
158 | .m = { .min = 96, .max = 140 }, | |
159 | .m1 = { .min = 18, .max = 26 }, | |
160 | .m2 = { .min = 6, .max = 16 }, | |
161 | .p = { .min = 4, .max = 128 }, | |
162 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
163 | .p2 = { .dot_limit = 165000, |
164 | .p2_slow = 14, .p2_fast = 7 }, | |
d4906093 | 165 | .find_pll = intel_find_best_PLL, |
e4b36699 | 166 | }; |
273e27ca | 167 | |
e4b36699 | 168 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
169 | .dot = { .min = 20000, .max = 400000 }, |
170 | .vco = { .min = 1400000, .max = 2800000 }, | |
171 | .n = { .min = 1, .max = 6 }, | |
172 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
173 | .m1 = { .min = 8, .max = 18 }, |
174 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
175 | .p = { .min = 5, .max = 80 }, |
176 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
177 | .p2 = { .dot_limit = 200000, |
178 | .p2_slow = 10, .p2_fast = 5 }, | |
d4906093 | 179 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
180 | }; |
181 | ||
182 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
183 | .dot = { .min = 20000, .max = 400000 }, |
184 | .vco = { .min = 1400000, .max = 2800000 }, | |
185 | .n = { .min = 1, .max = 6 }, | |
186 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
187 | .m1 = { .min = 8, .max = 18 }, |
188 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
189 | .p = { .min = 7, .max = 98 }, |
190 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
191 | .p2 = { .dot_limit = 112000, |
192 | .p2_slow = 14, .p2_fast = 7 }, | |
d4906093 | 193 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
194 | }; |
195 | ||
273e27ca | 196 | |
e4b36699 | 197 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
198 | .dot = { .min = 25000, .max = 270000 }, |
199 | .vco = { .min = 1750000, .max = 3500000}, | |
200 | .n = { .min = 1, .max = 4 }, | |
201 | .m = { .min = 104, .max = 138 }, | |
202 | .m1 = { .min = 17, .max = 23 }, | |
203 | .m2 = { .min = 5, .max = 11 }, | |
204 | .p = { .min = 10, .max = 30 }, | |
205 | .p1 = { .min = 1, .max = 3}, | |
206 | .p2 = { .dot_limit = 270000, | |
207 | .p2_slow = 10, | |
208 | .p2_fast = 10 | |
044c7c41 | 209 | }, |
d4906093 | 210 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
211 | }; |
212 | ||
213 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
214 | .dot = { .min = 22000, .max = 400000 }, |
215 | .vco = { .min = 1750000, .max = 3500000}, | |
216 | .n = { .min = 1, .max = 4 }, | |
217 | .m = { .min = 104, .max = 138 }, | |
218 | .m1 = { .min = 16, .max = 23 }, | |
219 | .m2 = { .min = 5, .max = 11 }, | |
220 | .p = { .min = 5, .max = 80 }, | |
221 | .p1 = { .min = 1, .max = 8}, | |
222 | .p2 = { .dot_limit = 165000, | |
223 | .p2_slow = 10, .p2_fast = 5 }, | |
d4906093 | 224 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
225 | }; |
226 | ||
227 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
228 | .dot = { .min = 20000, .max = 115000 }, |
229 | .vco = { .min = 1750000, .max = 3500000 }, | |
230 | .n = { .min = 1, .max = 3 }, | |
231 | .m = { .min = 104, .max = 138 }, | |
232 | .m1 = { .min = 17, .max = 23 }, | |
233 | .m2 = { .min = 5, .max = 11 }, | |
234 | .p = { .min = 28, .max = 112 }, | |
235 | .p1 = { .min = 2, .max = 8 }, | |
236 | .p2 = { .dot_limit = 0, | |
237 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 238 | }, |
d4906093 | 239 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
240 | }; |
241 | ||
242 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
243 | .dot = { .min = 80000, .max = 224000 }, |
244 | .vco = { .min = 1750000, .max = 3500000 }, | |
245 | .n = { .min = 1, .max = 3 }, | |
246 | .m = { .min = 104, .max = 138 }, | |
247 | .m1 = { .min = 17, .max = 23 }, | |
248 | .m2 = { .min = 5, .max = 11 }, | |
249 | .p = { .min = 14, .max = 42 }, | |
250 | .p1 = { .min = 2, .max = 6 }, | |
251 | .p2 = { .dot_limit = 0, | |
252 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 253 | }, |
d4906093 | 254 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
255 | }; |
256 | ||
257 | static const intel_limit_t intel_limits_g4x_display_port = { | |
0206e353 AJ |
258 | .dot = { .min = 161670, .max = 227000 }, |
259 | .vco = { .min = 1750000, .max = 3500000}, | |
260 | .n = { .min = 1, .max = 2 }, | |
261 | .m = { .min = 97, .max = 108 }, | |
262 | .m1 = { .min = 0x10, .max = 0x12 }, | |
263 | .m2 = { .min = 0x05, .max = 0x06 }, | |
264 | .p = { .min = 10, .max = 20 }, | |
265 | .p1 = { .min = 1, .max = 2}, | |
266 | .p2 = { .dot_limit = 0, | |
273e27ca | 267 | .p2_slow = 10, .p2_fast = 10 }, |
0206e353 | 268 | .find_pll = intel_find_pll_g4x_dp, |
e4b36699 KP |
269 | }; |
270 | ||
f2b115e6 | 271 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
272 | .dot = { .min = 20000, .max = 400000}, |
273 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 274 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
275 | .n = { .min = 3, .max = 6 }, |
276 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 277 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
278 | .m1 = { .min = 0, .max = 0 }, |
279 | .m2 = { .min = 0, .max = 254 }, | |
280 | .p = { .min = 5, .max = 80 }, | |
281 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
282 | .p2 = { .dot_limit = 200000, |
283 | .p2_slow = 10, .p2_fast = 5 }, | |
6115707b | 284 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
285 | }; |
286 | ||
f2b115e6 | 287 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
288 | .dot = { .min = 20000, .max = 400000 }, |
289 | .vco = { .min = 1700000, .max = 3500000 }, | |
290 | .n = { .min = 3, .max = 6 }, | |
291 | .m = { .min = 2, .max = 256 }, | |
292 | .m1 = { .min = 0, .max = 0 }, | |
293 | .m2 = { .min = 0, .max = 254 }, | |
294 | .p = { .min = 7, .max = 112 }, | |
295 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
296 | .p2 = { .dot_limit = 112000, |
297 | .p2_slow = 14, .p2_fast = 14 }, | |
6115707b | 298 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
299 | }; |
300 | ||
273e27ca EA |
301 | /* Ironlake / Sandybridge |
302 | * | |
303 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
304 | * the range value for them is (actual_value - 2). | |
305 | */ | |
b91ad0ec | 306 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
307 | .dot = { .min = 25000, .max = 350000 }, |
308 | .vco = { .min = 1760000, .max = 3510000 }, | |
309 | .n = { .min = 1, .max = 5 }, | |
310 | .m = { .min = 79, .max = 127 }, | |
311 | .m1 = { .min = 12, .max = 22 }, | |
312 | .m2 = { .min = 5, .max = 9 }, | |
313 | .p = { .min = 5, .max = 80 }, | |
314 | .p1 = { .min = 1, .max = 8 }, | |
315 | .p2 = { .dot_limit = 225000, | |
316 | .p2_slow = 10, .p2_fast = 5 }, | |
4547668a | 317 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
318 | }; |
319 | ||
b91ad0ec | 320 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
321 | .dot = { .min = 25000, .max = 350000 }, |
322 | .vco = { .min = 1760000, .max = 3510000 }, | |
323 | .n = { .min = 1, .max = 3 }, | |
324 | .m = { .min = 79, .max = 118 }, | |
325 | .m1 = { .min = 12, .max = 22 }, | |
326 | .m2 = { .min = 5, .max = 9 }, | |
327 | .p = { .min = 28, .max = 112 }, | |
328 | .p1 = { .min = 2, .max = 8 }, | |
329 | .p2 = { .dot_limit = 225000, | |
330 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
331 | .find_pll = intel_g4x_find_best_PLL, |
332 | }; | |
333 | ||
334 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
335 | .dot = { .min = 25000, .max = 350000 }, |
336 | .vco = { .min = 1760000, .max = 3510000 }, | |
337 | .n = { .min = 1, .max = 3 }, | |
338 | .m = { .min = 79, .max = 127 }, | |
339 | .m1 = { .min = 12, .max = 22 }, | |
340 | .m2 = { .min = 5, .max = 9 }, | |
341 | .p = { .min = 14, .max = 56 }, | |
342 | .p1 = { .min = 2, .max = 8 }, | |
343 | .p2 = { .dot_limit = 225000, | |
344 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
345 | .find_pll = intel_g4x_find_best_PLL, |
346 | }; | |
347 | ||
273e27ca | 348 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 349 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
350 | .dot = { .min = 25000, .max = 350000 }, |
351 | .vco = { .min = 1760000, .max = 3510000 }, | |
352 | .n = { .min = 1, .max = 2 }, | |
353 | .m = { .min = 79, .max = 126 }, | |
354 | .m1 = { .min = 12, .max = 22 }, | |
355 | .m2 = { .min = 5, .max = 9 }, | |
356 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 357 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
358 | .p2 = { .dot_limit = 225000, |
359 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
360 | .find_pll = intel_g4x_find_best_PLL, |
361 | }; | |
362 | ||
363 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
364 | .dot = { .min = 25000, .max = 350000 }, |
365 | .vco = { .min = 1760000, .max = 3510000 }, | |
366 | .n = { .min = 1, .max = 3 }, | |
367 | .m = { .min = 79, .max = 126 }, | |
368 | .m1 = { .min = 12, .max = 22 }, | |
369 | .m2 = { .min = 5, .max = 9 }, | |
370 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 371 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
372 | .p2 = { .dot_limit = 225000, |
373 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
374 | .find_pll = intel_g4x_find_best_PLL, |
375 | }; | |
376 | ||
377 | static const intel_limit_t intel_limits_ironlake_display_port = { | |
0206e353 AJ |
378 | .dot = { .min = 25000, .max = 350000 }, |
379 | .vco = { .min = 1760000, .max = 3510000}, | |
380 | .n = { .min = 1, .max = 2 }, | |
381 | .m = { .min = 81, .max = 90 }, | |
382 | .m1 = { .min = 12, .max = 22 }, | |
383 | .m2 = { .min = 5, .max = 9 }, | |
384 | .p = { .min = 10, .max = 20 }, | |
385 | .p1 = { .min = 1, .max = 2}, | |
386 | .p2 = { .dot_limit = 0, | |
273e27ca | 387 | .p2_slow = 10, .p2_fast = 10 }, |
0206e353 | 388 | .find_pll = intel_find_pll_ironlake_dp, |
79e53945 JB |
389 | }; |
390 | ||
a0c4da24 JB |
391 | static const intel_limit_t intel_limits_vlv_dac = { |
392 | .dot = { .min = 25000, .max = 270000 }, | |
393 | .vco = { .min = 4000000, .max = 6000000 }, | |
394 | .n = { .min = 1, .max = 7 }, | |
395 | .m = { .min = 22, .max = 450 }, /* guess */ | |
396 | .m1 = { .min = 2, .max = 3 }, | |
397 | .m2 = { .min = 11, .max = 156 }, | |
398 | .p = { .min = 10, .max = 30 }, | |
399 | .p1 = { .min = 2, .max = 3 }, | |
400 | .p2 = { .dot_limit = 270000, | |
401 | .p2_slow = 2, .p2_fast = 20 }, | |
402 | .find_pll = intel_vlv_find_best_pll, | |
403 | }; | |
404 | ||
405 | static const intel_limit_t intel_limits_vlv_hdmi = { | |
406 | .dot = { .min = 20000, .max = 165000 }, | |
17dc9257 | 407 | .vco = { .min = 4000000, .max = 5994000}, |
a0c4da24 JB |
408 | .n = { .min = 1, .max = 7 }, |
409 | .m = { .min = 60, .max = 300 }, /* guess */ | |
410 | .m1 = { .min = 2, .max = 3 }, | |
411 | .m2 = { .min = 11, .max = 156 }, | |
412 | .p = { .min = 10, .max = 30 }, | |
413 | .p1 = { .min = 2, .max = 3 }, | |
414 | .p2 = { .dot_limit = 270000, | |
415 | .p2_slow = 2, .p2_fast = 20 }, | |
416 | .find_pll = intel_vlv_find_best_pll, | |
417 | }; | |
418 | ||
419 | static const intel_limit_t intel_limits_vlv_dp = { | |
74a4dd2e VP |
420 | .dot = { .min = 25000, .max = 270000 }, |
421 | .vco = { .min = 4000000, .max = 6000000 }, | |
a0c4da24 | 422 | .n = { .min = 1, .max = 7 }, |
74a4dd2e | 423 | .m = { .min = 22, .max = 450 }, |
a0c4da24 JB |
424 | .m1 = { .min = 2, .max = 3 }, |
425 | .m2 = { .min = 11, .max = 156 }, | |
426 | .p = { .min = 10, .max = 30 }, | |
427 | .p1 = { .min = 2, .max = 3 }, | |
428 | .p2 = { .dot_limit = 270000, | |
429 | .p2_slow = 2, .p2_fast = 20 }, | |
430 | .find_pll = intel_vlv_find_best_pll, | |
431 | }; | |
432 | ||
57f350b6 JB |
433 | u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg) |
434 | { | |
09153000 | 435 | WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); |
57f350b6 | 436 | |
57f350b6 JB |
437 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { |
438 | DRM_ERROR("DPIO idle wait timed out\n"); | |
09153000 | 439 | return 0; |
57f350b6 JB |
440 | } |
441 | ||
442 | I915_WRITE(DPIO_REG, reg); | |
443 | I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID | | |
444 | DPIO_BYTE); | |
445 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { | |
446 | DRM_ERROR("DPIO read wait timed out\n"); | |
09153000 | 447 | return 0; |
57f350b6 | 448 | } |
57f350b6 | 449 | |
09153000 | 450 | return I915_READ(DPIO_DATA); |
57f350b6 JB |
451 | } |
452 | ||
a0c4da24 JB |
453 | static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, |
454 | u32 val) | |
455 | { | |
09153000 | 456 | WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); |
a0c4da24 | 457 | |
a0c4da24 JB |
458 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { |
459 | DRM_ERROR("DPIO idle wait timed out\n"); | |
09153000 | 460 | return; |
a0c4da24 JB |
461 | } |
462 | ||
463 | I915_WRITE(DPIO_DATA, val); | |
464 | I915_WRITE(DPIO_REG, reg); | |
465 | I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID | | |
466 | DPIO_BYTE); | |
467 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) | |
468 | DRM_ERROR("DPIO write wait timed out\n"); | |
a0c4da24 JB |
469 | } |
470 | ||
57f350b6 JB |
471 | static void vlv_init_dpio(struct drm_device *dev) |
472 | { | |
473 | struct drm_i915_private *dev_priv = dev->dev_private; | |
474 | ||
475 | /* Reset the DPIO config */ | |
476 | I915_WRITE(DPIO_CTL, 0); | |
477 | POSTING_READ(DPIO_CTL); | |
478 | I915_WRITE(DPIO_CTL, 1); | |
479 | POSTING_READ(DPIO_CTL); | |
480 | } | |
481 | ||
1b894b59 CW |
482 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
483 | int refclk) | |
2c07245f | 484 | { |
b91ad0ec | 485 | struct drm_device *dev = crtc->dev; |
2c07245f | 486 | const intel_limit_t *limit; |
b91ad0ec ZW |
487 | |
488 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 489 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 490 | if (refclk == 100000) |
b91ad0ec ZW |
491 | limit = &intel_limits_ironlake_dual_lvds_100m; |
492 | else | |
493 | limit = &intel_limits_ironlake_dual_lvds; | |
494 | } else { | |
1b894b59 | 495 | if (refclk == 100000) |
b91ad0ec ZW |
496 | limit = &intel_limits_ironlake_single_lvds_100m; |
497 | else | |
498 | limit = &intel_limits_ironlake_single_lvds; | |
499 | } | |
500 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || | |
547dc041 | 501 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) |
4547668a | 502 | limit = &intel_limits_ironlake_display_port; |
2c07245f | 503 | else |
b91ad0ec | 504 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
505 | |
506 | return limit; | |
507 | } | |
508 | ||
044c7c41 ML |
509 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
510 | { | |
511 | struct drm_device *dev = crtc->dev; | |
044c7c41 ML |
512 | const intel_limit_t *limit; |
513 | ||
514 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 515 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 516 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 517 | else |
e4b36699 | 518 | limit = &intel_limits_g4x_single_channel_lvds; |
044c7c41 ML |
519 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
520 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 521 | limit = &intel_limits_g4x_hdmi; |
044c7c41 | 522 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 523 | limit = &intel_limits_g4x_sdvo; |
0206e353 | 524 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
e4b36699 | 525 | limit = &intel_limits_g4x_display_port; |
044c7c41 | 526 | } else /* The option is for other outputs */ |
e4b36699 | 527 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
528 | |
529 | return limit; | |
530 | } | |
531 | ||
1b894b59 | 532 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
79e53945 JB |
533 | { |
534 | struct drm_device *dev = crtc->dev; | |
535 | const intel_limit_t *limit; | |
536 | ||
bad720ff | 537 | if (HAS_PCH_SPLIT(dev)) |
1b894b59 | 538 | limit = intel_ironlake_limit(crtc, refclk); |
2c07245f | 539 | else if (IS_G4X(dev)) { |
044c7c41 | 540 | limit = intel_g4x_limit(crtc); |
f2b115e6 | 541 | } else if (IS_PINEVIEW(dev)) { |
2177832f | 542 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 543 | limit = &intel_limits_pineview_lvds; |
2177832f | 544 | else |
f2b115e6 | 545 | limit = &intel_limits_pineview_sdvo; |
a0c4da24 JB |
546 | } else if (IS_VALLEYVIEW(dev)) { |
547 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) | |
548 | limit = &intel_limits_vlv_dac; | |
549 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
550 | limit = &intel_limits_vlv_hdmi; | |
551 | else | |
552 | limit = &intel_limits_vlv_dp; | |
a6c45cf0 CW |
553 | } else if (!IS_GEN2(dev)) { |
554 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
555 | limit = &intel_limits_i9xx_lvds; | |
556 | else | |
557 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 JB |
558 | } else { |
559 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
e4b36699 | 560 | limit = &intel_limits_i8xx_lvds; |
79e53945 | 561 | else |
e4b36699 | 562 | limit = &intel_limits_i8xx_dvo; |
79e53945 JB |
563 | } |
564 | return limit; | |
565 | } | |
566 | ||
f2b115e6 AJ |
567 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
568 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 569 | { |
2177832f SL |
570 | clock->m = clock->m2 + 2; |
571 | clock->p = clock->p1 * clock->p2; | |
572 | clock->vco = refclk * clock->m / clock->n; | |
573 | clock->dot = clock->vco / clock->p; | |
574 | } | |
575 | ||
576 | static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock) | |
577 | { | |
f2b115e6 AJ |
578 | if (IS_PINEVIEW(dev)) { |
579 | pineview_clock(refclk, clock); | |
2177832f SL |
580 | return; |
581 | } | |
79e53945 JB |
582 | clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); |
583 | clock->p = clock->p1 * clock->p2; | |
584 | clock->vco = refclk * clock->m / (clock->n + 2); | |
585 | clock->dot = clock->vco / clock->p; | |
586 | } | |
587 | ||
79e53945 JB |
588 | /** |
589 | * Returns whether any output on the specified pipe is of the specified type | |
590 | */ | |
4ef69c7a | 591 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type) |
79e53945 | 592 | { |
4ef69c7a | 593 | struct drm_device *dev = crtc->dev; |
4ef69c7a CW |
594 | struct intel_encoder *encoder; |
595 | ||
6c2b7c12 DV |
596 | for_each_encoder_on_crtc(dev, crtc, encoder) |
597 | if (encoder->type == type) | |
4ef69c7a CW |
598 | return true; |
599 | ||
600 | return false; | |
79e53945 JB |
601 | } |
602 | ||
7c04d1d9 | 603 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
604 | /** |
605 | * Returns whether the given set of divisors are valid for a given refclk with | |
606 | * the given connectors. | |
607 | */ | |
608 | ||
1b894b59 CW |
609 | static bool intel_PLL_is_valid(struct drm_device *dev, |
610 | const intel_limit_t *limit, | |
611 | const intel_clock_t *clock) | |
79e53945 | 612 | { |
79e53945 | 613 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 614 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 615 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
0206e353 | 616 | INTELPllInvalid("p out of range\n"); |
79e53945 | 617 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 618 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 619 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 620 | INTELPllInvalid("m1 out of range\n"); |
f2b115e6 | 621 | if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev)) |
0206e353 | 622 | INTELPllInvalid("m1 <= m2\n"); |
79e53945 | 623 | if (clock->m < limit->m.min || limit->m.max < clock->m) |
0206e353 | 624 | INTELPllInvalid("m out of range\n"); |
79e53945 | 625 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
0206e353 | 626 | INTELPllInvalid("n out of range\n"); |
79e53945 | 627 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 628 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
629 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
630 | * connector, etc., rather than just a single range. | |
631 | */ | |
632 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 633 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
634 | |
635 | return true; | |
636 | } | |
637 | ||
d4906093 ML |
638 | static bool |
639 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
640 | int target, int refclk, intel_clock_t *match_clock, |
641 | intel_clock_t *best_clock) | |
d4906093 | 642 | |
79e53945 JB |
643 | { |
644 | struct drm_device *dev = crtc->dev; | |
79e53945 | 645 | intel_clock_t clock; |
79e53945 JB |
646 | int err = target; |
647 | ||
a210b028 | 648 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 649 | /* |
a210b028 DV |
650 | * For LVDS just rely on its current settings for dual-channel. |
651 | * We haven't figured out how to reliably set up different | |
652 | * single/dual channel state, if we even can. | |
79e53945 | 653 | */ |
1974cad0 | 654 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
655 | clock.p2 = limit->p2.p2_fast; |
656 | else | |
657 | clock.p2 = limit->p2.p2_slow; | |
658 | } else { | |
659 | if (target < limit->p2.dot_limit) | |
660 | clock.p2 = limit->p2.p2_slow; | |
661 | else | |
662 | clock.p2 = limit->p2.p2_fast; | |
663 | } | |
664 | ||
0206e353 | 665 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 666 | |
42158660 ZY |
667 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
668 | clock.m1++) { | |
669 | for (clock.m2 = limit->m2.min; | |
670 | clock.m2 <= limit->m2.max; clock.m2++) { | |
f2b115e6 AJ |
671 | /* m1 is always 0 in Pineview */ |
672 | if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev)) | |
42158660 ZY |
673 | break; |
674 | for (clock.n = limit->n.min; | |
675 | clock.n <= limit->n.max; clock.n++) { | |
676 | for (clock.p1 = limit->p1.min; | |
677 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
678 | int this_err; |
679 | ||
2177832f | 680 | intel_clock(dev, refclk, &clock); |
1b894b59 CW |
681 | if (!intel_PLL_is_valid(dev, limit, |
682 | &clock)) | |
79e53945 | 683 | continue; |
cec2f356 SP |
684 | if (match_clock && |
685 | clock.p != match_clock->p) | |
686 | continue; | |
79e53945 JB |
687 | |
688 | this_err = abs(clock.dot - target); | |
689 | if (this_err < err) { | |
690 | *best_clock = clock; | |
691 | err = this_err; | |
692 | } | |
693 | } | |
694 | } | |
695 | } | |
696 | } | |
697 | ||
698 | return (err != target); | |
699 | } | |
700 | ||
d4906093 ML |
701 | static bool |
702 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
703 | int target, int refclk, intel_clock_t *match_clock, |
704 | intel_clock_t *best_clock) | |
d4906093 ML |
705 | { |
706 | struct drm_device *dev = crtc->dev; | |
d4906093 ML |
707 | intel_clock_t clock; |
708 | int max_n; | |
709 | bool found; | |
6ba770dc AJ |
710 | /* approximately equals target * 0.00585 */ |
711 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
712 | found = false; |
713 | ||
714 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
4547668a ZY |
715 | int lvds_reg; |
716 | ||
c619eed4 | 717 | if (HAS_PCH_SPLIT(dev)) |
4547668a ZY |
718 | lvds_reg = PCH_LVDS; |
719 | else | |
720 | lvds_reg = LVDS; | |
1974cad0 | 721 | if (intel_is_dual_link_lvds(dev)) |
d4906093 ML |
722 | clock.p2 = limit->p2.p2_fast; |
723 | else | |
724 | clock.p2 = limit->p2.p2_slow; | |
725 | } else { | |
726 | if (target < limit->p2.dot_limit) | |
727 | clock.p2 = limit->p2.p2_slow; | |
728 | else | |
729 | clock.p2 = limit->p2.p2_fast; | |
730 | } | |
731 | ||
732 | memset(best_clock, 0, sizeof(*best_clock)); | |
733 | max_n = limit->n.max; | |
f77f13e2 | 734 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 735 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 736 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
737 | for (clock.m1 = limit->m1.max; |
738 | clock.m1 >= limit->m1.min; clock.m1--) { | |
739 | for (clock.m2 = limit->m2.max; | |
740 | clock.m2 >= limit->m2.min; clock.m2--) { | |
741 | for (clock.p1 = limit->p1.max; | |
742 | clock.p1 >= limit->p1.min; clock.p1--) { | |
743 | int this_err; | |
744 | ||
2177832f | 745 | intel_clock(dev, refclk, &clock); |
1b894b59 CW |
746 | if (!intel_PLL_is_valid(dev, limit, |
747 | &clock)) | |
d4906093 | 748 | continue; |
cec2f356 SP |
749 | if (match_clock && |
750 | clock.p != match_clock->p) | |
751 | continue; | |
1b894b59 CW |
752 | |
753 | this_err = abs(clock.dot - target); | |
d4906093 ML |
754 | if (this_err < err_most) { |
755 | *best_clock = clock; | |
756 | err_most = this_err; | |
757 | max_n = clock.n; | |
758 | found = true; | |
759 | } | |
760 | } | |
761 | } | |
762 | } | |
763 | } | |
2c07245f ZW |
764 | return found; |
765 | } | |
766 | ||
5eb08b69 | 767 | static bool |
f2b115e6 | 768 | intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc, |
cec2f356 SP |
769 | int target, int refclk, intel_clock_t *match_clock, |
770 | intel_clock_t *best_clock) | |
5eb08b69 ZW |
771 | { |
772 | struct drm_device *dev = crtc->dev; | |
773 | intel_clock_t clock; | |
4547668a | 774 | |
5eb08b69 ZW |
775 | if (target < 200000) { |
776 | clock.n = 1; | |
777 | clock.p1 = 2; | |
778 | clock.p2 = 10; | |
779 | clock.m1 = 12; | |
780 | clock.m2 = 9; | |
781 | } else { | |
782 | clock.n = 2; | |
783 | clock.p1 = 1; | |
784 | clock.p2 = 10; | |
785 | clock.m1 = 14; | |
786 | clock.m2 = 8; | |
787 | } | |
788 | intel_clock(dev, refclk, &clock); | |
789 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); | |
790 | return true; | |
791 | } | |
792 | ||
a4fc5ed6 KP |
793 | /* DisplayPort has only two frequencies, 162MHz and 270MHz */ |
794 | static bool | |
795 | intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
796 | int target, int refclk, intel_clock_t *match_clock, |
797 | intel_clock_t *best_clock) | |
a4fc5ed6 | 798 | { |
5eddb70b CW |
799 | intel_clock_t clock; |
800 | if (target < 200000) { | |
801 | clock.p1 = 2; | |
802 | clock.p2 = 10; | |
803 | clock.n = 2; | |
804 | clock.m1 = 23; | |
805 | clock.m2 = 8; | |
806 | } else { | |
807 | clock.p1 = 1; | |
808 | clock.p2 = 10; | |
809 | clock.n = 1; | |
810 | clock.m1 = 14; | |
811 | clock.m2 = 2; | |
812 | } | |
813 | clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2); | |
814 | clock.p = (clock.p1 * clock.p2); | |
815 | clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p; | |
816 | clock.vco = 0; | |
817 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); | |
818 | return true; | |
a4fc5ed6 | 819 | } |
a0c4da24 JB |
820 | static bool |
821 | intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc, | |
822 | int target, int refclk, intel_clock_t *match_clock, | |
823 | intel_clock_t *best_clock) | |
824 | { | |
825 | u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2; | |
826 | u32 m, n, fastclk; | |
827 | u32 updrate, minupdate, fracbits, p; | |
828 | unsigned long bestppm, ppm, absppm; | |
829 | int dotclk, flag; | |
830 | ||
af447bd3 | 831 | flag = 0; |
a0c4da24 JB |
832 | dotclk = target * 1000; |
833 | bestppm = 1000000; | |
834 | ppm = absppm = 0; | |
835 | fastclk = dotclk / (2*100); | |
836 | updrate = 0; | |
837 | minupdate = 19200; | |
838 | fracbits = 1; | |
839 | n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0; | |
840 | bestm1 = bestm2 = bestp1 = bestp2 = 0; | |
841 | ||
842 | /* based on hardware requirement, prefer smaller n to precision */ | |
843 | for (n = limit->n.min; n <= ((refclk) / minupdate); n++) { | |
844 | updrate = refclk / n; | |
845 | for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) { | |
846 | for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) { | |
847 | if (p2 > 10) | |
848 | p2 = p2 - 1; | |
849 | p = p1 * p2; | |
850 | /* based on hardware requirement, prefer bigger m1,m2 values */ | |
851 | for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) { | |
852 | m2 = (((2*(fastclk * p * n / m1 )) + | |
853 | refclk) / (2*refclk)); | |
854 | m = m1 * m2; | |
855 | vco = updrate * m; | |
856 | if (vco >= limit->vco.min && vco < limit->vco.max) { | |
857 | ppm = 1000000 * ((vco / p) - fastclk) / fastclk; | |
858 | absppm = (ppm > 0) ? ppm : (-ppm); | |
859 | if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) { | |
860 | bestppm = 0; | |
861 | flag = 1; | |
862 | } | |
863 | if (absppm < bestppm - 10) { | |
864 | bestppm = absppm; | |
865 | flag = 1; | |
866 | } | |
867 | if (flag) { | |
868 | bestn = n; | |
869 | bestm1 = m1; | |
870 | bestm2 = m2; | |
871 | bestp1 = p1; | |
872 | bestp2 = p2; | |
873 | flag = 0; | |
874 | } | |
875 | } | |
876 | } | |
877 | } | |
878 | } | |
879 | } | |
880 | best_clock->n = bestn; | |
881 | best_clock->m1 = bestm1; | |
882 | best_clock->m2 = bestm2; | |
883 | best_clock->p1 = bestp1; | |
884 | best_clock->p2 = bestp2; | |
885 | ||
886 | return true; | |
887 | } | |
a4fc5ed6 | 888 | |
a5c961d1 PZ |
889 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
890 | enum pipe pipe) | |
891 | { | |
892 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
893 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
894 | ||
895 | return intel_crtc->cpu_transcoder; | |
896 | } | |
897 | ||
a928d536 PZ |
898 | static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe) |
899 | { | |
900 | struct drm_i915_private *dev_priv = dev->dev_private; | |
901 | u32 frame, frame_reg = PIPEFRAME(pipe); | |
902 | ||
903 | frame = I915_READ(frame_reg); | |
904 | ||
905 | if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50)) | |
906 | DRM_DEBUG_KMS("vblank wait timed out\n"); | |
907 | } | |
908 | ||
9d0498a2 JB |
909 | /** |
910 | * intel_wait_for_vblank - wait for vblank on a given pipe | |
911 | * @dev: drm device | |
912 | * @pipe: pipe to wait for | |
913 | * | |
914 | * Wait for vblank to occur on a given pipe. Needed for various bits of | |
915 | * mode setting code. | |
916 | */ | |
917 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) | |
79e53945 | 918 | { |
9d0498a2 | 919 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 920 | int pipestat_reg = PIPESTAT(pipe); |
9d0498a2 | 921 | |
a928d536 PZ |
922 | if (INTEL_INFO(dev)->gen >= 5) { |
923 | ironlake_wait_for_vblank(dev, pipe); | |
924 | return; | |
925 | } | |
926 | ||
300387c0 CW |
927 | /* Clear existing vblank status. Note this will clear any other |
928 | * sticky status fields as well. | |
929 | * | |
930 | * This races with i915_driver_irq_handler() with the result | |
931 | * that either function could miss a vblank event. Here it is not | |
932 | * fatal, as we will either wait upon the next vblank interrupt or | |
933 | * timeout. Generally speaking intel_wait_for_vblank() is only | |
934 | * called during modeset at which time the GPU should be idle and | |
935 | * should *not* be performing page flips and thus not waiting on | |
936 | * vblanks... | |
937 | * Currently, the result of us stealing a vblank from the irq | |
938 | * handler is that a single frame will be skipped during swapbuffers. | |
939 | */ | |
940 | I915_WRITE(pipestat_reg, | |
941 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); | |
942 | ||
9d0498a2 | 943 | /* Wait for vblank interrupt bit to set */ |
481b6af3 CW |
944 | if (wait_for(I915_READ(pipestat_reg) & |
945 | PIPE_VBLANK_INTERRUPT_STATUS, | |
946 | 50)) | |
9d0498a2 JB |
947 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
948 | } | |
949 | ||
ab7ad7f6 KP |
950 | /* |
951 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
9d0498a2 JB |
952 | * @dev: drm device |
953 | * @pipe: pipe to wait for | |
954 | * | |
955 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
956 | * spinning on the vblank interrupt status bit, since we won't actually | |
957 | * see an interrupt when the pipe is disabled. | |
958 | * | |
ab7ad7f6 KP |
959 | * On Gen4 and above: |
960 | * wait for the pipe register state bit to turn off | |
961 | * | |
962 | * Otherwise: | |
963 | * wait for the display line value to settle (it usually | |
964 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 965 | * |
9d0498a2 | 966 | */ |
58e10eb9 | 967 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
9d0498a2 JB |
968 | { |
969 | struct drm_i915_private *dev_priv = dev->dev_private; | |
702e7a56 PZ |
970 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
971 | pipe); | |
ab7ad7f6 KP |
972 | |
973 | if (INTEL_INFO(dev)->gen >= 4) { | |
702e7a56 | 974 | int reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
975 | |
976 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
977 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
978 | 100)) | |
284637d9 | 979 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 980 | } else { |
837ba00f | 981 | u32 last_line, line_mask; |
58e10eb9 | 982 | int reg = PIPEDSL(pipe); |
ab7ad7f6 KP |
983 | unsigned long timeout = jiffies + msecs_to_jiffies(100); |
984 | ||
837ba00f PZ |
985 | if (IS_GEN2(dev)) |
986 | line_mask = DSL_LINEMASK_GEN2; | |
987 | else | |
988 | line_mask = DSL_LINEMASK_GEN3; | |
989 | ||
ab7ad7f6 KP |
990 | /* Wait for the display line to settle */ |
991 | do { | |
837ba00f | 992 | last_line = I915_READ(reg) & line_mask; |
ab7ad7f6 | 993 | mdelay(5); |
837ba00f | 994 | } while (((I915_READ(reg) & line_mask) != last_line) && |
ab7ad7f6 KP |
995 | time_after(timeout, jiffies)); |
996 | if (time_after(jiffies, timeout)) | |
284637d9 | 997 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 998 | } |
79e53945 JB |
999 | } |
1000 | ||
b0ea7d37 DL |
1001 | /* |
1002 | * ibx_digital_port_connected - is the specified port connected? | |
1003 | * @dev_priv: i915 private structure | |
1004 | * @port: the port to test | |
1005 | * | |
1006 | * Returns true if @port is connected, false otherwise. | |
1007 | */ | |
1008 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, | |
1009 | struct intel_digital_port *port) | |
1010 | { | |
1011 | u32 bit; | |
1012 | ||
c36346e3 DL |
1013 | if (HAS_PCH_IBX(dev_priv->dev)) { |
1014 | switch(port->port) { | |
1015 | case PORT_B: | |
1016 | bit = SDE_PORTB_HOTPLUG; | |
1017 | break; | |
1018 | case PORT_C: | |
1019 | bit = SDE_PORTC_HOTPLUG; | |
1020 | break; | |
1021 | case PORT_D: | |
1022 | bit = SDE_PORTD_HOTPLUG; | |
1023 | break; | |
1024 | default: | |
1025 | return true; | |
1026 | } | |
1027 | } else { | |
1028 | switch(port->port) { | |
1029 | case PORT_B: | |
1030 | bit = SDE_PORTB_HOTPLUG_CPT; | |
1031 | break; | |
1032 | case PORT_C: | |
1033 | bit = SDE_PORTC_HOTPLUG_CPT; | |
1034 | break; | |
1035 | case PORT_D: | |
1036 | bit = SDE_PORTD_HOTPLUG_CPT; | |
1037 | break; | |
1038 | default: | |
1039 | return true; | |
1040 | } | |
b0ea7d37 DL |
1041 | } |
1042 | ||
1043 | return I915_READ(SDEISR) & bit; | |
1044 | } | |
1045 | ||
b24e7179 JB |
1046 | static const char *state_string(bool enabled) |
1047 | { | |
1048 | return enabled ? "on" : "off"; | |
1049 | } | |
1050 | ||
1051 | /* Only for pre-ILK configs */ | |
1052 | static void assert_pll(struct drm_i915_private *dev_priv, | |
1053 | enum pipe pipe, bool state) | |
1054 | { | |
1055 | int reg; | |
1056 | u32 val; | |
1057 | bool cur_state; | |
1058 | ||
1059 | reg = DPLL(pipe); | |
1060 | val = I915_READ(reg); | |
1061 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
1062 | WARN(cur_state != state, | |
1063 | "PLL state assertion failure (expected %s, current %s)\n", | |
1064 | state_string(state), state_string(cur_state)); | |
1065 | } | |
1066 | #define assert_pll_enabled(d, p) assert_pll(d, p, true) | |
1067 | #define assert_pll_disabled(d, p) assert_pll(d, p, false) | |
1068 | ||
040484af JB |
1069 | /* For ILK+ */ |
1070 | static void assert_pch_pll(struct drm_i915_private *dev_priv, | |
92b27b08 CW |
1071 | struct intel_pch_pll *pll, |
1072 | struct intel_crtc *crtc, | |
1073 | bool state) | |
040484af | 1074 | { |
040484af JB |
1075 | u32 val; |
1076 | bool cur_state; | |
1077 | ||
9d82aa17 ED |
1078 | if (HAS_PCH_LPT(dev_priv->dev)) { |
1079 | DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n"); | |
1080 | return; | |
1081 | } | |
1082 | ||
92b27b08 CW |
1083 | if (WARN (!pll, |
1084 | "asserting PCH PLL %s with no PLL\n", state_string(state))) | |
ee7b9f93 | 1085 | return; |
ee7b9f93 | 1086 | |
92b27b08 CW |
1087 | val = I915_READ(pll->pll_reg); |
1088 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
1089 | WARN(cur_state != state, | |
1090 | "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n", | |
1091 | pll->pll_reg, state_string(state), state_string(cur_state), val); | |
1092 | ||
1093 | /* Make sure the selected PLL is correctly attached to the transcoder */ | |
1094 | if (crtc && HAS_PCH_CPT(dev_priv->dev)) { | |
d3ccbe86 JB |
1095 | u32 pch_dpll; |
1096 | ||
1097 | pch_dpll = I915_READ(PCH_DPLL_SEL); | |
92b27b08 CW |
1098 | cur_state = pll->pll_reg == _PCH_DPLL_B; |
1099 | if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state, | |
1100 | "PLL[%d] not attached to this transcoder %d: %08x\n", | |
1101 | cur_state, crtc->pipe, pch_dpll)) { | |
1102 | cur_state = !!(val >> (4*crtc->pipe + 3)); | |
1103 | WARN(cur_state != state, | |
1104 | "PLL[%d] not %s on this transcoder %d: %08x\n", | |
1105 | pll->pll_reg == _PCH_DPLL_B, | |
1106 | state_string(state), | |
1107 | crtc->pipe, | |
1108 | val); | |
1109 | } | |
d3ccbe86 | 1110 | } |
040484af | 1111 | } |
92b27b08 CW |
1112 | #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true) |
1113 | #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false) | |
040484af JB |
1114 | |
1115 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1116 | enum pipe pipe, bool state) | |
1117 | { | |
1118 | int reg; | |
1119 | u32 val; | |
1120 | bool cur_state; | |
ad80a810 PZ |
1121 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1122 | pipe); | |
040484af | 1123 | |
affa9354 PZ |
1124 | if (HAS_DDI(dev_priv->dev)) { |
1125 | /* DDI does not have a specific FDI_TX register */ | |
ad80a810 | 1126 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
bf507ef7 | 1127 | val = I915_READ(reg); |
ad80a810 | 1128 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 ED |
1129 | } else { |
1130 | reg = FDI_TX_CTL(pipe); | |
1131 | val = I915_READ(reg); | |
1132 | cur_state = !!(val & FDI_TX_ENABLE); | |
1133 | } | |
040484af JB |
1134 | WARN(cur_state != state, |
1135 | "FDI TX state assertion failure (expected %s, current %s)\n", | |
1136 | state_string(state), state_string(cur_state)); | |
1137 | } | |
1138 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1139 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1140 | ||
1141 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1142 | enum pipe pipe, bool state) | |
1143 | { | |
1144 | int reg; | |
1145 | u32 val; | |
1146 | bool cur_state; | |
1147 | ||
d63fa0dc PZ |
1148 | reg = FDI_RX_CTL(pipe); |
1149 | val = I915_READ(reg); | |
1150 | cur_state = !!(val & FDI_RX_ENABLE); | |
040484af JB |
1151 | WARN(cur_state != state, |
1152 | "FDI RX state assertion failure (expected %s, current %s)\n", | |
1153 | state_string(state), state_string(cur_state)); | |
1154 | } | |
1155 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1156 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1157 | ||
1158 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1159 | enum pipe pipe) | |
1160 | { | |
1161 | int reg; | |
1162 | u32 val; | |
1163 | ||
1164 | /* ILK FDI PLL is always enabled */ | |
1165 | if (dev_priv->info->gen == 5) | |
1166 | return; | |
1167 | ||
bf507ef7 | 1168 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1169 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1170 | return; |
1171 | ||
040484af JB |
1172 | reg = FDI_TX_CTL(pipe); |
1173 | val = I915_READ(reg); | |
1174 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); | |
1175 | } | |
1176 | ||
1177 | static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv, | |
1178 | enum pipe pipe) | |
1179 | { | |
1180 | int reg; | |
1181 | u32 val; | |
1182 | ||
1183 | reg = FDI_RX_CTL(pipe); | |
1184 | val = I915_READ(reg); | |
1185 | WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n"); | |
1186 | } | |
1187 | ||
ea0760cf JB |
1188 | static void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1189 | enum pipe pipe) | |
1190 | { | |
1191 | int pp_reg, lvds_reg; | |
1192 | u32 val; | |
1193 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1194 | bool locked = true; |
ea0760cf JB |
1195 | |
1196 | if (HAS_PCH_SPLIT(dev_priv->dev)) { | |
1197 | pp_reg = PCH_PP_CONTROL; | |
1198 | lvds_reg = PCH_LVDS; | |
1199 | } else { | |
1200 | pp_reg = PP_CONTROL; | |
1201 | lvds_reg = LVDS; | |
1202 | } | |
1203 | ||
1204 | val = I915_READ(pp_reg); | |
1205 | if (!(val & PANEL_POWER_ON) || | |
1206 | ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) | |
1207 | locked = false; | |
1208 | ||
1209 | if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) | |
1210 | panel_pipe = PIPE_B; | |
1211 | ||
1212 | WARN(panel_pipe == pipe && locked, | |
1213 | "panel assertion failure, pipe %c regs locked\n", | |
9db4a9c7 | 1214 | pipe_name(pipe)); |
ea0760cf JB |
1215 | } |
1216 | ||
b840d907 JB |
1217 | void assert_pipe(struct drm_i915_private *dev_priv, |
1218 | enum pipe pipe, bool state) | |
b24e7179 JB |
1219 | { |
1220 | int reg; | |
1221 | u32 val; | |
63d7bbe9 | 1222 | bool cur_state; |
702e7a56 PZ |
1223 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1224 | pipe); | |
b24e7179 | 1225 | |
8e636784 DV |
1226 | /* if we need the pipe A quirk it must be always on */ |
1227 | if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
1228 | state = true; | |
1229 | ||
69310161 PZ |
1230 | if (IS_HASWELL(dev_priv->dev) && cpu_transcoder != TRANSCODER_EDP && |
1231 | !(I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_ENABLE)) { | |
1232 | cur_state = false; | |
1233 | } else { | |
1234 | reg = PIPECONF(cpu_transcoder); | |
1235 | val = I915_READ(reg); | |
1236 | cur_state = !!(val & PIPECONF_ENABLE); | |
1237 | } | |
1238 | ||
63d7bbe9 JB |
1239 | WARN(cur_state != state, |
1240 | "pipe %c assertion failure (expected %s, current %s)\n", | |
9db4a9c7 | 1241 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1242 | } |
1243 | ||
931872fc CW |
1244 | static void assert_plane(struct drm_i915_private *dev_priv, |
1245 | enum plane plane, bool state) | |
b24e7179 JB |
1246 | { |
1247 | int reg; | |
1248 | u32 val; | |
931872fc | 1249 | bool cur_state; |
b24e7179 JB |
1250 | |
1251 | reg = DSPCNTR(plane); | |
1252 | val = I915_READ(reg); | |
931872fc CW |
1253 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
1254 | WARN(cur_state != state, | |
1255 | "plane %c assertion failure (expected %s, current %s)\n", | |
1256 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1257 | } |
1258 | ||
931872fc CW |
1259 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1260 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1261 | ||
b24e7179 JB |
1262 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1263 | enum pipe pipe) | |
1264 | { | |
1265 | int reg, i; | |
1266 | u32 val; | |
1267 | int cur_pipe; | |
1268 | ||
19ec1358 | 1269 | /* Planes are fixed to pipes on ILK+ */ |
da6ecc5d | 1270 | if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) { |
28c05794 AJ |
1271 | reg = DSPCNTR(pipe); |
1272 | val = I915_READ(reg); | |
1273 | WARN((val & DISPLAY_PLANE_ENABLE), | |
1274 | "plane %c assertion failure, should be disabled but not\n", | |
1275 | plane_name(pipe)); | |
19ec1358 | 1276 | return; |
28c05794 | 1277 | } |
19ec1358 | 1278 | |
b24e7179 JB |
1279 | /* Need to check both planes against the pipe */ |
1280 | for (i = 0; i < 2; i++) { | |
1281 | reg = DSPCNTR(i); | |
1282 | val = I915_READ(reg); | |
1283 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1284 | DISPPLANE_SEL_PIPE_SHIFT; | |
1285 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, | |
9db4a9c7 JB |
1286 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1287 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1288 | } |
1289 | } | |
1290 | ||
19332d7a JB |
1291 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1292 | enum pipe pipe) | |
1293 | { | |
1294 | int reg, i; | |
1295 | u32 val; | |
1296 | ||
1297 | if (!IS_VALLEYVIEW(dev_priv->dev)) | |
1298 | return; | |
1299 | ||
1300 | /* Need to check both planes against the pipe */ | |
1301 | for (i = 0; i < dev_priv->num_plane; i++) { | |
1302 | reg = SPCNTR(pipe, i); | |
1303 | val = I915_READ(reg); | |
1304 | WARN((val & SP_ENABLE), | |
1305 | "sprite %d assertion failure, should be off on pipe %c but is still active\n", | |
1306 | pipe * 2 + i, pipe_name(pipe)); | |
1307 | } | |
1308 | } | |
1309 | ||
92f2584a JB |
1310 | static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
1311 | { | |
1312 | u32 val; | |
1313 | bool enabled; | |
1314 | ||
9d82aa17 ED |
1315 | if (HAS_PCH_LPT(dev_priv->dev)) { |
1316 | DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n"); | |
1317 | return; | |
1318 | } | |
1319 | ||
92f2584a JB |
1320 | val = I915_READ(PCH_DREF_CONTROL); |
1321 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1322 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
1323 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); | |
1324 | } | |
1325 | ||
1326 | static void assert_transcoder_disabled(struct drm_i915_private *dev_priv, | |
1327 | enum pipe pipe) | |
1328 | { | |
1329 | int reg; | |
1330 | u32 val; | |
1331 | bool enabled; | |
1332 | ||
1333 | reg = TRANSCONF(pipe); | |
1334 | val = I915_READ(reg); | |
1335 | enabled = !!(val & TRANS_ENABLE); | |
9db4a9c7 JB |
1336 | WARN(enabled, |
1337 | "transcoder assertion failed, should be off on pipe %c but is still active\n", | |
1338 | pipe_name(pipe)); | |
92f2584a JB |
1339 | } |
1340 | ||
4e634389 KP |
1341 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1342 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1343 | { |
1344 | if ((val & DP_PORT_EN) == 0) | |
1345 | return false; | |
1346 | ||
1347 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1348 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1349 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1350 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1351 | return false; | |
1352 | } else { | |
1353 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1354 | return false; | |
1355 | } | |
1356 | return true; | |
1357 | } | |
1358 | ||
1519b995 KP |
1359 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1360 | enum pipe pipe, u32 val) | |
1361 | { | |
dc0fa718 | 1362 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1363 | return false; |
1364 | ||
1365 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1366 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 KP |
1367 | return false; |
1368 | } else { | |
dc0fa718 | 1369 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1370 | return false; |
1371 | } | |
1372 | return true; | |
1373 | } | |
1374 | ||
1375 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1376 | enum pipe pipe, u32 val) | |
1377 | { | |
1378 | if ((val & LVDS_PORT_EN) == 0) | |
1379 | return false; | |
1380 | ||
1381 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1382 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1383 | return false; | |
1384 | } else { | |
1385 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1386 | return false; | |
1387 | } | |
1388 | return true; | |
1389 | } | |
1390 | ||
1391 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1392 | enum pipe pipe, u32 val) | |
1393 | { | |
1394 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1395 | return false; | |
1396 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1397 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1398 | return false; | |
1399 | } else { | |
1400 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1401 | return false; | |
1402 | } | |
1403 | return true; | |
1404 | } | |
1405 | ||
291906f1 | 1406 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1407 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1408 | { |
47a05eca | 1409 | u32 val = I915_READ(reg); |
4e634389 | 1410 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1411 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1412 | reg, pipe_name(pipe)); |
de9a35ab | 1413 | |
75c5da27 DV |
1414 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
1415 | && (val & DP_PIPEB_SELECT), | |
de9a35ab | 1416 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1417 | } |
1418 | ||
1419 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1420 | enum pipe pipe, int reg) | |
1421 | { | |
47a05eca | 1422 | u32 val = I915_READ(reg); |
b70ad586 | 1423 | WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1424 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1425 | reg, pipe_name(pipe)); |
de9a35ab | 1426 | |
dc0fa718 | 1427 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1428 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1429 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1430 | } |
1431 | ||
1432 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1433 | enum pipe pipe) | |
1434 | { | |
1435 | int reg; | |
1436 | u32 val; | |
291906f1 | 1437 | |
f0575e92 KP |
1438 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1439 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1440 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1441 | |
1442 | reg = PCH_ADPA; | |
1443 | val = I915_READ(reg); | |
b70ad586 | 1444 | WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1445 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1446 | pipe_name(pipe)); |
291906f1 JB |
1447 | |
1448 | reg = PCH_LVDS; | |
1449 | val = I915_READ(reg); | |
b70ad586 | 1450 | WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1451 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1452 | pipe_name(pipe)); |
291906f1 | 1453 | |
e2debe91 PZ |
1454 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1455 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1456 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1457 | } |
1458 | ||
63d7bbe9 JB |
1459 | /** |
1460 | * intel_enable_pll - enable a PLL | |
1461 | * @dev_priv: i915 private structure | |
1462 | * @pipe: pipe PLL to enable | |
1463 | * | |
1464 | * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to | |
1465 | * make sure the PLL reg is writable first though, since the panel write | |
1466 | * protect mechanism may be enabled. | |
1467 | * | |
1468 | * Note! This is for pre-ILK only. | |
7434a255 TR |
1469 | * |
1470 | * Unfortunately needed by dvo_ns2501 since the dvo depends on it running. | |
63d7bbe9 JB |
1471 | */ |
1472 | static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1473 | { | |
1474 | int reg; | |
1475 | u32 val; | |
1476 | ||
1477 | /* No really, not for ILK+ */ | |
a0c4da24 | 1478 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5); |
63d7bbe9 JB |
1479 | |
1480 | /* PLL is protected by panel, make sure we can write it */ | |
1481 | if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) | |
1482 | assert_panel_unlocked(dev_priv, pipe); | |
1483 | ||
1484 | reg = DPLL(pipe); | |
1485 | val = I915_READ(reg); | |
1486 | val |= DPLL_VCO_ENABLE; | |
1487 | ||
1488 | /* We do this three times for luck */ | |
1489 | I915_WRITE(reg, val); | |
1490 | POSTING_READ(reg); | |
1491 | udelay(150); /* wait for warmup */ | |
1492 | I915_WRITE(reg, val); | |
1493 | POSTING_READ(reg); | |
1494 | udelay(150); /* wait for warmup */ | |
1495 | I915_WRITE(reg, val); | |
1496 | POSTING_READ(reg); | |
1497 | udelay(150); /* wait for warmup */ | |
1498 | } | |
1499 | ||
1500 | /** | |
1501 | * intel_disable_pll - disable a PLL | |
1502 | * @dev_priv: i915 private structure | |
1503 | * @pipe: pipe PLL to disable | |
1504 | * | |
1505 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1506 | * | |
1507 | * Note! This is for pre-ILK only. | |
1508 | */ | |
1509 | static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1510 | { | |
1511 | int reg; | |
1512 | u32 val; | |
1513 | ||
1514 | /* Don't disable pipe A or pipe A PLLs if needed */ | |
1515 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1516 | return; | |
1517 | ||
1518 | /* Make sure the pipe isn't still relying on us */ | |
1519 | assert_pipe_disabled(dev_priv, pipe); | |
1520 | ||
1521 | reg = DPLL(pipe); | |
1522 | val = I915_READ(reg); | |
1523 | val &= ~DPLL_VCO_ENABLE; | |
1524 | I915_WRITE(reg, val); | |
1525 | POSTING_READ(reg); | |
1526 | } | |
1527 | ||
a416edef ED |
1528 | /* SBI access */ |
1529 | static void | |
988d6ee8 PZ |
1530 | intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, |
1531 | enum intel_sbi_destination destination) | |
a416edef | 1532 | { |
988d6ee8 | 1533 | u32 tmp; |
a416edef | 1534 | |
09153000 | 1535 | WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); |
a416edef | 1536 | |
39fb50f6 | 1537 | if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, |
a416edef ED |
1538 | 100)) { |
1539 | DRM_ERROR("timeout waiting for SBI to become ready\n"); | |
09153000 | 1540 | return; |
a416edef ED |
1541 | } |
1542 | ||
988d6ee8 PZ |
1543 | I915_WRITE(SBI_ADDR, (reg << 16)); |
1544 | I915_WRITE(SBI_DATA, value); | |
1545 | ||
1546 | if (destination == SBI_ICLK) | |
1547 | tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR; | |
1548 | else | |
1549 | tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR; | |
1550 | I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp); | |
a416edef | 1551 | |
39fb50f6 | 1552 | if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0, |
a416edef ED |
1553 | 100)) { |
1554 | DRM_ERROR("timeout waiting for SBI to complete write transaction\n"); | |
09153000 | 1555 | return; |
a416edef | 1556 | } |
a416edef ED |
1557 | } |
1558 | ||
1559 | static u32 | |
988d6ee8 PZ |
1560 | intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, |
1561 | enum intel_sbi_destination destination) | |
a416edef | 1562 | { |
39fb50f6 | 1563 | u32 value = 0; |
09153000 | 1564 | WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); |
a416edef | 1565 | |
39fb50f6 | 1566 | if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, |
a416edef ED |
1567 | 100)) { |
1568 | DRM_ERROR("timeout waiting for SBI to become ready\n"); | |
09153000 | 1569 | return 0; |
a416edef ED |
1570 | } |
1571 | ||
988d6ee8 PZ |
1572 | I915_WRITE(SBI_ADDR, (reg << 16)); |
1573 | ||
1574 | if (destination == SBI_ICLK) | |
1575 | value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD; | |
1576 | else | |
1577 | value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD; | |
1578 | I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY); | |
a416edef | 1579 | |
39fb50f6 | 1580 | if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0, |
a416edef ED |
1581 | 100)) { |
1582 | DRM_ERROR("timeout waiting for SBI to complete read transaction\n"); | |
09153000 | 1583 | return 0; |
a416edef ED |
1584 | } |
1585 | ||
09153000 | 1586 | return I915_READ(SBI_DATA); |
a416edef ED |
1587 | } |
1588 | ||
92f2584a | 1589 | /** |
b6b4e185 | 1590 | * ironlake_enable_pch_pll - enable PCH PLL |
92f2584a JB |
1591 | * @dev_priv: i915 private structure |
1592 | * @pipe: pipe PLL to enable | |
1593 | * | |
1594 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1595 | * drives the transcoder clock. | |
1596 | */ | |
b6b4e185 | 1597 | static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc) |
92f2584a | 1598 | { |
ee7b9f93 | 1599 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; |
48da64a8 | 1600 | struct intel_pch_pll *pll; |
92f2584a JB |
1601 | int reg; |
1602 | u32 val; | |
1603 | ||
48da64a8 | 1604 | /* PCH PLLs only available on ILK, SNB and IVB */ |
92f2584a | 1605 | BUG_ON(dev_priv->info->gen < 5); |
48da64a8 CW |
1606 | pll = intel_crtc->pch_pll; |
1607 | if (pll == NULL) | |
1608 | return; | |
1609 | ||
1610 | if (WARN_ON(pll->refcount == 0)) | |
1611 | return; | |
ee7b9f93 JB |
1612 | |
1613 | DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n", | |
1614 | pll->pll_reg, pll->active, pll->on, | |
1615 | intel_crtc->base.base.id); | |
92f2584a JB |
1616 | |
1617 | /* PCH refclock must be enabled first */ | |
1618 | assert_pch_refclk_enabled(dev_priv); | |
1619 | ||
ee7b9f93 | 1620 | if (pll->active++ && pll->on) { |
92b27b08 | 1621 | assert_pch_pll_enabled(dev_priv, pll, NULL); |
ee7b9f93 JB |
1622 | return; |
1623 | } | |
1624 | ||
1625 | DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg); | |
1626 | ||
1627 | reg = pll->pll_reg; | |
92f2584a JB |
1628 | val = I915_READ(reg); |
1629 | val |= DPLL_VCO_ENABLE; | |
1630 | I915_WRITE(reg, val); | |
1631 | POSTING_READ(reg); | |
1632 | udelay(200); | |
ee7b9f93 JB |
1633 | |
1634 | pll->on = true; | |
92f2584a JB |
1635 | } |
1636 | ||
ee7b9f93 | 1637 | static void intel_disable_pch_pll(struct intel_crtc *intel_crtc) |
92f2584a | 1638 | { |
ee7b9f93 JB |
1639 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; |
1640 | struct intel_pch_pll *pll = intel_crtc->pch_pll; | |
92f2584a | 1641 | int reg; |
ee7b9f93 | 1642 | u32 val; |
4c609cb8 | 1643 | |
92f2584a JB |
1644 | /* PCH only available on ILK+ */ |
1645 | BUG_ON(dev_priv->info->gen < 5); | |
ee7b9f93 JB |
1646 | if (pll == NULL) |
1647 | return; | |
92f2584a | 1648 | |
48da64a8 CW |
1649 | if (WARN_ON(pll->refcount == 0)) |
1650 | return; | |
7a419866 | 1651 | |
ee7b9f93 JB |
1652 | DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n", |
1653 | pll->pll_reg, pll->active, pll->on, | |
1654 | intel_crtc->base.base.id); | |
7a419866 | 1655 | |
48da64a8 | 1656 | if (WARN_ON(pll->active == 0)) { |
92b27b08 | 1657 | assert_pch_pll_disabled(dev_priv, pll, NULL); |
48da64a8 CW |
1658 | return; |
1659 | } | |
1660 | ||
ee7b9f93 | 1661 | if (--pll->active) { |
92b27b08 | 1662 | assert_pch_pll_enabled(dev_priv, pll, NULL); |
7a419866 | 1663 | return; |
ee7b9f93 JB |
1664 | } |
1665 | ||
1666 | DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg); | |
1667 | ||
1668 | /* Make sure transcoder isn't still depending on us */ | |
1669 | assert_transcoder_disabled(dev_priv, intel_crtc->pipe); | |
7a419866 | 1670 | |
ee7b9f93 | 1671 | reg = pll->pll_reg; |
92f2584a JB |
1672 | val = I915_READ(reg); |
1673 | val &= ~DPLL_VCO_ENABLE; | |
1674 | I915_WRITE(reg, val); | |
1675 | POSTING_READ(reg); | |
1676 | udelay(200); | |
ee7b9f93 JB |
1677 | |
1678 | pll->on = false; | |
92f2584a JB |
1679 | } |
1680 | ||
b8a4f404 PZ |
1681 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1682 | enum pipe pipe) | |
040484af | 1683 | { |
23670b32 | 1684 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1685 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
23670b32 | 1686 | uint32_t reg, val, pipeconf_val; |
040484af JB |
1687 | |
1688 | /* PCH only available on ILK+ */ | |
1689 | BUG_ON(dev_priv->info->gen < 5); | |
1690 | ||
1691 | /* Make sure PCH DPLL is enabled */ | |
92b27b08 CW |
1692 | assert_pch_pll_enabled(dev_priv, |
1693 | to_intel_crtc(crtc)->pch_pll, | |
1694 | to_intel_crtc(crtc)); | |
040484af JB |
1695 | |
1696 | /* FDI must be feeding us bits for PCH ports */ | |
1697 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1698 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1699 | ||
23670b32 DV |
1700 | if (HAS_PCH_CPT(dev)) { |
1701 | /* Workaround: Set the timing override bit before enabling the | |
1702 | * pch transcoder. */ | |
1703 | reg = TRANS_CHICKEN2(pipe); | |
1704 | val = I915_READ(reg); | |
1705 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1706 | I915_WRITE(reg, val); | |
59c859d6 | 1707 | } |
23670b32 | 1708 | |
040484af JB |
1709 | reg = TRANSCONF(pipe); |
1710 | val = I915_READ(reg); | |
5f7f726d | 1711 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1712 | |
1713 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1714 | /* | |
1715 | * make the BPC in transcoder be consistent with | |
1716 | * that in pipeconf reg. | |
1717 | */ | |
dfd07d72 DV |
1718 | val &= ~PIPECONF_BPC_MASK; |
1719 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1720 | } |
5f7f726d PZ |
1721 | |
1722 | val &= ~TRANS_INTERLACE_MASK; | |
1723 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 PZ |
1724 | if (HAS_PCH_IBX(dev_priv->dev) && |
1725 | intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) | |
1726 | val |= TRANS_LEGACY_INTERLACED_ILK; | |
1727 | else | |
1728 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1729 | else |
1730 | val |= TRANS_PROGRESSIVE; | |
1731 | ||
040484af JB |
1732 | I915_WRITE(reg, val | TRANS_ENABLE); |
1733 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
1734 | DRM_ERROR("failed to enable transcoder %d\n", pipe); | |
1735 | } | |
1736 | ||
8fb033d7 | 1737 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1738 | enum transcoder cpu_transcoder) |
040484af | 1739 | { |
8fb033d7 | 1740 | u32 val, pipeconf_val; |
8fb033d7 PZ |
1741 | |
1742 | /* PCH only available on ILK+ */ | |
1743 | BUG_ON(dev_priv->info->gen < 5); | |
1744 | ||
8fb033d7 | 1745 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1746 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1747 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1748 | |
223a6fdf PZ |
1749 | /* Workaround: set timing override bit. */ |
1750 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1751 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf PZ |
1752 | I915_WRITE(_TRANSA_CHICKEN2, val); |
1753 | ||
25f3ef11 | 1754 | val = TRANS_ENABLE; |
937bb610 | 1755 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1756 | |
9a76b1c6 PZ |
1757 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1758 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1759 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1760 | else |
1761 | val |= TRANS_PROGRESSIVE; | |
1762 | ||
25f3ef11 | 1763 | I915_WRITE(TRANSCONF(TRANSCODER_A), val); |
937bb610 PZ |
1764 | if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100)) |
1765 | DRM_ERROR("Failed to enable PCH transcoder\n"); | |
8fb033d7 PZ |
1766 | } |
1767 | ||
b8a4f404 PZ |
1768 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1769 | enum pipe pipe) | |
040484af | 1770 | { |
23670b32 DV |
1771 | struct drm_device *dev = dev_priv->dev; |
1772 | uint32_t reg, val; | |
040484af JB |
1773 | |
1774 | /* FDI relies on the transcoder */ | |
1775 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1776 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1777 | ||
291906f1 JB |
1778 | /* Ports must be off as well */ |
1779 | assert_pch_ports_disabled(dev_priv, pipe); | |
1780 | ||
040484af JB |
1781 | reg = TRANSCONF(pipe); |
1782 | val = I915_READ(reg); | |
1783 | val &= ~TRANS_ENABLE; | |
1784 | I915_WRITE(reg, val); | |
1785 | /* wait for PCH transcoder off, transcoder state */ | |
1786 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4c9c18c2 | 1787 | DRM_ERROR("failed to disable transcoder %d\n", pipe); |
23670b32 DV |
1788 | |
1789 | if (!HAS_PCH_IBX(dev)) { | |
1790 | /* Workaround: Clear the timing override chicken bit again. */ | |
1791 | reg = TRANS_CHICKEN2(pipe); | |
1792 | val = I915_READ(reg); | |
1793 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1794 | I915_WRITE(reg, val); | |
1795 | } | |
040484af JB |
1796 | } |
1797 | ||
ab4d966c | 1798 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1799 | { |
8fb033d7 PZ |
1800 | u32 val; |
1801 | ||
8a52fd9f | 1802 | val = I915_READ(_TRANSACONF); |
8fb033d7 | 1803 | val &= ~TRANS_ENABLE; |
8a52fd9f | 1804 | I915_WRITE(_TRANSACONF, val); |
8fb033d7 | 1805 | /* wait for PCH transcoder off, transcoder state */ |
8a52fd9f PZ |
1806 | if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50)) |
1807 | DRM_ERROR("Failed to disable PCH transcoder\n"); | |
223a6fdf PZ |
1808 | |
1809 | /* Workaround: clear timing override bit. */ | |
1810 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1811 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf | 1812 | I915_WRITE(_TRANSA_CHICKEN2, val); |
040484af JB |
1813 | } |
1814 | ||
b24e7179 | 1815 | /** |
309cfea8 | 1816 | * intel_enable_pipe - enable a pipe, asserting requirements |
b24e7179 JB |
1817 | * @dev_priv: i915 private structure |
1818 | * @pipe: pipe to enable | |
040484af | 1819 | * @pch_port: on ILK+, is this pipe driving a PCH port or not |
b24e7179 JB |
1820 | * |
1821 | * Enable @pipe, making sure that various hardware specific requirements | |
1822 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. | |
1823 | * | |
1824 | * @pipe should be %PIPE_A or %PIPE_B. | |
1825 | * | |
1826 | * Will wait until the pipe is actually running (i.e. first vblank) before | |
1827 | * returning. | |
1828 | */ | |
040484af JB |
1829 | static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, |
1830 | bool pch_port) | |
b24e7179 | 1831 | { |
702e7a56 PZ |
1832 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1833 | pipe); | |
1a240d4d | 1834 | enum pipe pch_transcoder; |
b24e7179 JB |
1835 | int reg; |
1836 | u32 val; | |
1837 | ||
681e5811 | 1838 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
1839 | pch_transcoder = TRANSCODER_A; |
1840 | else | |
1841 | pch_transcoder = pipe; | |
1842 | ||
b24e7179 JB |
1843 | /* |
1844 | * A pipe without a PLL won't actually be able to drive bits from | |
1845 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1846 | * need the check. | |
1847 | */ | |
1848 | if (!HAS_PCH_SPLIT(dev_priv->dev)) | |
1849 | assert_pll_enabled(dev_priv, pipe); | |
040484af JB |
1850 | else { |
1851 | if (pch_port) { | |
1852 | /* if driving the PCH, we need FDI enabled */ | |
cc391bbb | 1853 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
1854 | assert_fdi_tx_pll_enabled(dev_priv, |
1855 | (enum pipe) cpu_transcoder); | |
040484af JB |
1856 | } |
1857 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1858 | } | |
b24e7179 | 1859 | |
702e7a56 | 1860 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1861 | val = I915_READ(reg); |
00d70b15 CW |
1862 | if (val & PIPECONF_ENABLE) |
1863 | return; | |
1864 | ||
1865 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
b24e7179 JB |
1866 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1867 | } | |
1868 | ||
1869 | /** | |
309cfea8 | 1870 | * intel_disable_pipe - disable a pipe, asserting requirements |
b24e7179 JB |
1871 | * @dev_priv: i915 private structure |
1872 | * @pipe: pipe to disable | |
1873 | * | |
1874 | * Disable @pipe, making sure that various hardware specific requirements | |
1875 | * are met, if applicable, e.g. plane disabled, panel fitter off, etc. | |
1876 | * | |
1877 | * @pipe should be %PIPE_A or %PIPE_B. | |
1878 | * | |
1879 | * Will wait until the pipe has shut down before returning. | |
1880 | */ | |
1881 | static void intel_disable_pipe(struct drm_i915_private *dev_priv, | |
1882 | enum pipe pipe) | |
1883 | { | |
702e7a56 PZ |
1884 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1885 | pipe); | |
b24e7179 JB |
1886 | int reg; |
1887 | u32 val; | |
1888 | ||
1889 | /* | |
1890 | * Make sure planes won't keep trying to pump pixels to us, | |
1891 | * or we might hang the display. | |
1892 | */ | |
1893 | assert_planes_disabled(dev_priv, pipe); | |
19332d7a | 1894 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 JB |
1895 | |
1896 | /* Don't disable pipe A or pipe A PLLs if needed */ | |
1897 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1898 | return; | |
1899 | ||
702e7a56 | 1900 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1901 | val = I915_READ(reg); |
00d70b15 CW |
1902 | if ((val & PIPECONF_ENABLE) == 0) |
1903 | return; | |
1904 | ||
1905 | I915_WRITE(reg, val & ~PIPECONF_ENABLE); | |
b24e7179 JB |
1906 | intel_wait_for_pipe_off(dev_priv->dev, pipe); |
1907 | } | |
1908 | ||
d74362c9 KP |
1909 | /* |
1910 | * Plane regs are double buffered, going from enabled->disabled needs a | |
1911 | * trigger in order to latch. The display address reg provides this. | |
1912 | */ | |
6f1d69b0 | 1913 | void intel_flush_display_plane(struct drm_i915_private *dev_priv, |
d74362c9 KP |
1914 | enum plane plane) |
1915 | { | |
14f86147 DL |
1916 | if (dev_priv->info->gen >= 4) |
1917 | I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane))); | |
1918 | else | |
1919 | I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane))); | |
d74362c9 KP |
1920 | } |
1921 | ||
b24e7179 JB |
1922 | /** |
1923 | * intel_enable_plane - enable a display plane on a given pipe | |
1924 | * @dev_priv: i915 private structure | |
1925 | * @plane: plane to enable | |
1926 | * @pipe: pipe being fed | |
1927 | * | |
1928 | * Enable @plane on @pipe, making sure that @pipe is running first. | |
1929 | */ | |
1930 | static void intel_enable_plane(struct drm_i915_private *dev_priv, | |
1931 | enum plane plane, enum pipe pipe) | |
1932 | { | |
1933 | int reg; | |
1934 | u32 val; | |
1935 | ||
1936 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
1937 | assert_pipe_enabled(dev_priv, pipe); | |
1938 | ||
1939 | reg = DSPCNTR(plane); | |
1940 | val = I915_READ(reg); | |
00d70b15 CW |
1941 | if (val & DISPLAY_PLANE_ENABLE) |
1942 | return; | |
1943 | ||
1944 | I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); | |
d74362c9 | 1945 | intel_flush_display_plane(dev_priv, plane); |
b24e7179 JB |
1946 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1947 | } | |
1948 | ||
b24e7179 JB |
1949 | /** |
1950 | * intel_disable_plane - disable a display plane | |
1951 | * @dev_priv: i915 private structure | |
1952 | * @plane: plane to disable | |
1953 | * @pipe: pipe consuming the data | |
1954 | * | |
1955 | * Disable @plane; should be an independent operation. | |
1956 | */ | |
1957 | static void intel_disable_plane(struct drm_i915_private *dev_priv, | |
1958 | enum plane plane, enum pipe pipe) | |
1959 | { | |
1960 | int reg; | |
1961 | u32 val; | |
1962 | ||
1963 | reg = DSPCNTR(plane); | |
1964 | val = I915_READ(reg); | |
00d70b15 CW |
1965 | if ((val & DISPLAY_PLANE_ENABLE) == 0) |
1966 | return; | |
1967 | ||
1968 | I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); | |
b24e7179 JB |
1969 | intel_flush_display_plane(dev_priv, plane); |
1970 | intel_wait_for_vblank(dev_priv->dev, pipe); | |
1971 | } | |
1972 | ||
693db184 CW |
1973 | static bool need_vtd_wa(struct drm_device *dev) |
1974 | { | |
1975 | #ifdef CONFIG_INTEL_IOMMU | |
1976 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
1977 | return true; | |
1978 | #endif | |
1979 | return false; | |
1980 | } | |
1981 | ||
127bd2ac | 1982 | int |
48b956c5 | 1983 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
05394f39 | 1984 | struct drm_i915_gem_object *obj, |
919926ae | 1985 | struct intel_ring_buffer *pipelined) |
6b95a207 | 1986 | { |
ce453d81 | 1987 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
1988 | u32 alignment; |
1989 | int ret; | |
1990 | ||
05394f39 | 1991 | switch (obj->tiling_mode) { |
6b95a207 | 1992 | case I915_TILING_NONE: |
534843da CW |
1993 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
1994 | alignment = 128 * 1024; | |
a6c45cf0 | 1995 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
1996 | alignment = 4 * 1024; |
1997 | else | |
1998 | alignment = 64 * 1024; | |
6b95a207 KH |
1999 | break; |
2000 | case I915_TILING_X: | |
2001 | /* pin() will align the object as required by fence */ | |
2002 | alignment = 0; | |
2003 | break; | |
2004 | case I915_TILING_Y: | |
8bb6e959 DV |
2005 | /* Despite that we check this in framebuffer_init userspace can |
2006 | * screw us over and change the tiling after the fact. Only | |
2007 | * pinned buffers can't change their tiling. */ | |
2008 | DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n"); | |
6b95a207 KH |
2009 | return -EINVAL; |
2010 | default: | |
2011 | BUG(); | |
2012 | } | |
2013 | ||
693db184 CW |
2014 | /* Note that the w/a also requires 64 PTE of padding following the |
2015 | * bo. We currently fill all unused PTE with the shadow page and so | |
2016 | * we should always have valid PTE following the scanout preventing | |
2017 | * the VT-d warning. | |
2018 | */ | |
2019 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2020 | alignment = 256 * 1024; | |
2021 | ||
ce453d81 | 2022 | dev_priv->mm.interruptible = false; |
2da3b9b9 | 2023 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
48b956c5 | 2024 | if (ret) |
ce453d81 | 2025 | goto err_interruptible; |
6b95a207 KH |
2026 | |
2027 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2028 | * fence, whereas 965+ only requires a fence if using | |
2029 | * framebuffer compression. For simplicity, we always install | |
2030 | * a fence as the cost is not that onerous. | |
2031 | */ | |
06d98131 | 2032 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
2033 | if (ret) |
2034 | goto err_unpin; | |
1690e1eb | 2035 | |
9a5a53b3 | 2036 | i915_gem_object_pin_fence(obj); |
6b95a207 | 2037 | |
ce453d81 | 2038 | dev_priv->mm.interruptible = true; |
6b95a207 | 2039 | return 0; |
48b956c5 CW |
2040 | |
2041 | err_unpin: | |
2042 | i915_gem_object_unpin(obj); | |
ce453d81 CW |
2043 | err_interruptible: |
2044 | dev_priv->mm.interruptible = true; | |
48b956c5 | 2045 | return ret; |
6b95a207 KH |
2046 | } |
2047 | ||
1690e1eb CW |
2048 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
2049 | { | |
2050 | i915_gem_object_unpin_fence(obj); | |
2051 | i915_gem_object_unpin(obj); | |
2052 | } | |
2053 | ||
c2c75131 DV |
2054 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2055 | * is assumed to be a power-of-two. */ | |
bc752862 CW |
2056 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
2057 | unsigned int tiling_mode, | |
2058 | unsigned int cpp, | |
2059 | unsigned int pitch) | |
c2c75131 | 2060 | { |
bc752862 CW |
2061 | if (tiling_mode != I915_TILING_NONE) { |
2062 | unsigned int tile_rows, tiles; | |
c2c75131 | 2063 | |
bc752862 CW |
2064 | tile_rows = *y / 8; |
2065 | *y %= 8; | |
c2c75131 | 2066 | |
bc752862 CW |
2067 | tiles = *x / (512/cpp); |
2068 | *x %= 512/cpp; | |
2069 | ||
2070 | return tile_rows * pitch * 8 + tiles * 4096; | |
2071 | } else { | |
2072 | unsigned int offset; | |
2073 | ||
2074 | offset = *y * pitch + *x * cpp; | |
2075 | *y = 0; | |
2076 | *x = (offset & 4095) / cpp; | |
2077 | return offset & -4096; | |
2078 | } | |
c2c75131 DV |
2079 | } |
2080 | ||
17638cd6 JB |
2081 | static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
2082 | int x, int y) | |
81255565 JB |
2083 | { |
2084 | struct drm_device *dev = crtc->dev; | |
2085 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2086 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2087 | struct intel_framebuffer *intel_fb; | |
05394f39 | 2088 | struct drm_i915_gem_object *obj; |
81255565 | 2089 | int plane = intel_crtc->plane; |
e506a0c6 | 2090 | unsigned long linear_offset; |
81255565 | 2091 | u32 dspcntr; |
5eddb70b | 2092 | u32 reg; |
81255565 JB |
2093 | |
2094 | switch (plane) { | |
2095 | case 0: | |
2096 | case 1: | |
2097 | break; | |
2098 | default: | |
2099 | DRM_ERROR("Can't update plane %d in SAREA\n", plane); | |
2100 | return -EINVAL; | |
2101 | } | |
2102 | ||
2103 | intel_fb = to_intel_framebuffer(fb); | |
2104 | obj = intel_fb->obj; | |
81255565 | 2105 | |
5eddb70b CW |
2106 | reg = DSPCNTR(plane); |
2107 | dspcntr = I915_READ(reg); | |
81255565 JB |
2108 | /* Mask out pixel format bits in case we change it */ |
2109 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
57779d06 VS |
2110 | switch (fb->pixel_format) { |
2111 | case DRM_FORMAT_C8: | |
81255565 JB |
2112 | dspcntr |= DISPPLANE_8BPP; |
2113 | break; | |
57779d06 VS |
2114 | case DRM_FORMAT_XRGB1555: |
2115 | case DRM_FORMAT_ARGB1555: | |
2116 | dspcntr |= DISPPLANE_BGRX555; | |
81255565 | 2117 | break; |
57779d06 VS |
2118 | case DRM_FORMAT_RGB565: |
2119 | dspcntr |= DISPPLANE_BGRX565; | |
2120 | break; | |
2121 | case DRM_FORMAT_XRGB8888: | |
2122 | case DRM_FORMAT_ARGB8888: | |
2123 | dspcntr |= DISPPLANE_BGRX888; | |
2124 | break; | |
2125 | case DRM_FORMAT_XBGR8888: | |
2126 | case DRM_FORMAT_ABGR8888: | |
2127 | dspcntr |= DISPPLANE_RGBX888; | |
2128 | break; | |
2129 | case DRM_FORMAT_XRGB2101010: | |
2130 | case DRM_FORMAT_ARGB2101010: | |
2131 | dspcntr |= DISPPLANE_BGRX101010; | |
2132 | break; | |
2133 | case DRM_FORMAT_XBGR2101010: | |
2134 | case DRM_FORMAT_ABGR2101010: | |
2135 | dspcntr |= DISPPLANE_RGBX101010; | |
81255565 JB |
2136 | break; |
2137 | default: | |
baba133a | 2138 | BUG(); |
81255565 | 2139 | } |
57779d06 | 2140 | |
a6c45cf0 | 2141 | if (INTEL_INFO(dev)->gen >= 4) { |
05394f39 | 2142 | if (obj->tiling_mode != I915_TILING_NONE) |
81255565 JB |
2143 | dspcntr |= DISPPLANE_TILED; |
2144 | else | |
2145 | dspcntr &= ~DISPPLANE_TILED; | |
2146 | } | |
2147 | ||
5eddb70b | 2148 | I915_WRITE(reg, dspcntr); |
81255565 | 2149 | |
e506a0c6 | 2150 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
81255565 | 2151 | |
c2c75131 DV |
2152 | if (INTEL_INFO(dev)->gen >= 4) { |
2153 | intel_crtc->dspaddr_offset = | |
bc752862 CW |
2154 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2155 | fb->bits_per_pixel / 8, | |
2156 | fb->pitches[0]); | |
c2c75131 DV |
2157 | linear_offset -= intel_crtc->dspaddr_offset; |
2158 | } else { | |
e506a0c6 | 2159 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2160 | } |
e506a0c6 DV |
2161 | |
2162 | DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n", | |
2163 | obj->gtt_offset, linear_offset, x, y, fb->pitches[0]); | |
01f2c773 | 2164 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2165 | if (INTEL_INFO(dev)->gen >= 4) { |
c2c75131 DV |
2166 | I915_MODIFY_DISPBASE(DSPSURF(plane), |
2167 | obj->gtt_offset + intel_crtc->dspaddr_offset); | |
5eddb70b | 2168 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2169 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2170 | } else |
e506a0c6 | 2171 | I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset); |
5eddb70b | 2172 | POSTING_READ(reg); |
81255565 | 2173 | |
17638cd6 JB |
2174 | return 0; |
2175 | } | |
2176 | ||
2177 | static int ironlake_update_plane(struct drm_crtc *crtc, | |
2178 | struct drm_framebuffer *fb, int x, int y) | |
2179 | { | |
2180 | struct drm_device *dev = crtc->dev; | |
2181 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2182 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2183 | struct intel_framebuffer *intel_fb; | |
2184 | struct drm_i915_gem_object *obj; | |
2185 | int plane = intel_crtc->plane; | |
e506a0c6 | 2186 | unsigned long linear_offset; |
17638cd6 JB |
2187 | u32 dspcntr; |
2188 | u32 reg; | |
2189 | ||
2190 | switch (plane) { | |
2191 | case 0: | |
2192 | case 1: | |
27f8227b | 2193 | case 2: |
17638cd6 JB |
2194 | break; |
2195 | default: | |
2196 | DRM_ERROR("Can't update plane %d in SAREA\n", plane); | |
2197 | return -EINVAL; | |
2198 | } | |
2199 | ||
2200 | intel_fb = to_intel_framebuffer(fb); | |
2201 | obj = intel_fb->obj; | |
2202 | ||
2203 | reg = DSPCNTR(plane); | |
2204 | dspcntr = I915_READ(reg); | |
2205 | /* Mask out pixel format bits in case we change it */ | |
2206 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
57779d06 VS |
2207 | switch (fb->pixel_format) { |
2208 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2209 | dspcntr |= DISPPLANE_8BPP; |
2210 | break; | |
57779d06 VS |
2211 | case DRM_FORMAT_RGB565: |
2212 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2213 | break; |
57779d06 VS |
2214 | case DRM_FORMAT_XRGB8888: |
2215 | case DRM_FORMAT_ARGB8888: | |
2216 | dspcntr |= DISPPLANE_BGRX888; | |
2217 | break; | |
2218 | case DRM_FORMAT_XBGR8888: | |
2219 | case DRM_FORMAT_ABGR8888: | |
2220 | dspcntr |= DISPPLANE_RGBX888; | |
2221 | break; | |
2222 | case DRM_FORMAT_XRGB2101010: | |
2223 | case DRM_FORMAT_ARGB2101010: | |
2224 | dspcntr |= DISPPLANE_BGRX101010; | |
2225 | break; | |
2226 | case DRM_FORMAT_XBGR2101010: | |
2227 | case DRM_FORMAT_ABGR2101010: | |
2228 | dspcntr |= DISPPLANE_RGBX101010; | |
17638cd6 JB |
2229 | break; |
2230 | default: | |
baba133a | 2231 | BUG(); |
17638cd6 JB |
2232 | } |
2233 | ||
2234 | if (obj->tiling_mode != I915_TILING_NONE) | |
2235 | dspcntr |= DISPPLANE_TILED; | |
2236 | else | |
2237 | dspcntr &= ~DISPPLANE_TILED; | |
2238 | ||
2239 | /* must disable */ | |
2240 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2241 | ||
2242 | I915_WRITE(reg, dspcntr); | |
2243 | ||
e506a0c6 | 2244 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
c2c75131 | 2245 | intel_crtc->dspaddr_offset = |
bc752862 CW |
2246 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2247 | fb->bits_per_pixel / 8, | |
2248 | fb->pitches[0]); | |
c2c75131 | 2249 | linear_offset -= intel_crtc->dspaddr_offset; |
17638cd6 | 2250 | |
e506a0c6 DV |
2251 | DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n", |
2252 | obj->gtt_offset, linear_offset, x, y, fb->pitches[0]); | |
01f2c773 | 2253 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
c2c75131 DV |
2254 | I915_MODIFY_DISPBASE(DSPSURF(plane), |
2255 | obj->gtt_offset + intel_crtc->dspaddr_offset); | |
bc1c91eb DL |
2256 | if (IS_HASWELL(dev)) { |
2257 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); | |
2258 | } else { | |
2259 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2260 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2261 | } | |
17638cd6 JB |
2262 | POSTING_READ(reg); |
2263 | ||
2264 | return 0; | |
2265 | } | |
2266 | ||
2267 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ | |
2268 | static int | |
2269 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
2270 | int x, int y, enum mode_set_atomic state) | |
2271 | { | |
2272 | struct drm_device *dev = crtc->dev; | |
2273 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 2274 | |
6b8e6ed0 CW |
2275 | if (dev_priv->display.disable_fbc) |
2276 | dev_priv->display.disable_fbc(dev); | |
3dec0095 | 2277 | intel_increase_pllclock(crtc); |
81255565 | 2278 | |
6b8e6ed0 | 2279 | return dev_priv->display.update_plane(crtc, fb, x, y); |
81255565 JB |
2280 | } |
2281 | ||
96a02917 VS |
2282 | void intel_display_handle_reset(struct drm_device *dev) |
2283 | { | |
2284 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2285 | struct drm_crtc *crtc; | |
2286 | ||
2287 | /* | |
2288 | * Flips in the rings have been nuked by the reset, | |
2289 | * so complete all pending flips so that user space | |
2290 | * will get its events and not get stuck. | |
2291 | * | |
2292 | * Also update the base address of all primary | |
2293 | * planes to the the last fb to make sure we're | |
2294 | * showing the correct fb after a reset. | |
2295 | * | |
2296 | * Need to make two loops over the crtcs so that we | |
2297 | * don't try to grab a crtc mutex before the | |
2298 | * pending_flip_queue really got woken up. | |
2299 | */ | |
2300 | ||
2301 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2302 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2303 | enum plane plane = intel_crtc->plane; | |
2304 | ||
2305 | intel_prepare_page_flip(dev, plane); | |
2306 | intel_finish_page_flip_plane(dev, plane); | |
2307 | } | |
2308 | ||
2309 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2310 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2311 | ||
2312 | mutex_lock(&crtc->mutex); | |
2313 | if (intel_crtc->active) | |
2314 | dev_priv->display.update_plane(crtc, crtc->fb, | |
2315 | crtc->x, crtc->y); | |
2316 | mutex_unlock(&crtc->mutex); | |
2317 | } | |
2318 | } | |
2319 | ||
14667a4b CW |
2320 | static int |
2321 | intel_finish_fb(struct drm_framebuffer *old_fb) | |
2322 | { | |
2323 | struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; | |
2324 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2325 | bool was_interruptible = dev_priv->mm.interruptible; | |
2326 | int ret; | |
2327 | ||
14667a4b CW |
2328 | /* Big Hammer, we also need to ensure that any pending |
2329 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
2330 | * current scanout is retired before unpinning the old | |
2331 | * framebuffer. | |
2332 | * | |
2333 | * This should only fail upon a hung GPU, in which case we | |
2334 | * can safely continue. | |
2335 | */ | |
2336 | dev_priv->mm.interruptible = false; | |
2337 | ret = i915_gem_object_finish_gpu(obj); | |
2338 | dev_priv->mm.interruptible = was_interruptible; | |
2339 | ||
2340 | return ret; | |
2341 | } | |
2342 | ||
198598d0 VS |
2343 | static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y) |
2344 | { | |
2345 | struct drm_device *dev = crtc->dev; | |
2346 | struct drm_i915_master_private *master_priv; | |
2347 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2348 | ||
2349 | if (!dev->primary->master) | |
2350 | return; | |
2351 | ||
2352 | master_priv = dev->primary->master->driver_priv; | |
2353 | if (!master_priv->sarea_priv) | |
2354 | return; | |
2355 | ||
2356 | switch (intel_crtc->pipe) { | |
2357 | case 0: | |
2358 | master_priv->sarea_priv->pipeA_x = x; | |
2359 | master_priv->sarea_priv->pipeA_y = y; | |
2360 | break; | |
2361 | case 1: | |
2362 | master_priv->sarea_priv->pipeB_x = x; | |
2363 | master_priv->sarea_priv->pipeB_y = y; | |
2364 | break; | |
2365 | default: | |
2366 | break; | |
2367 | } | |
2368 | } | |
2369 | ||
5c3b82e2 | 2370 | static int |
3c4fdcfb | 2371 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
94352cf9 | 2372 | struct drm_framebuffer *fb) |
79e53945 JB |
2373 | { |
2374 | struct drm_device *dev = crtc->dev; | |
6b8e6ed0 | 2375 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 2376 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
94352cf9 | 2377 | struct drm_framebuffer *old_fb; |
5c3b82e2 | 2378 | int ret; |
79e53945 JB |
2379 | |
2380 | /* no fb bound */ | |
94352cf9 | 2381 | if (!fb) { |
a5071c2f | 2382 | DRM_ERROR("No FB bound\n"); |
5c3b82e2 CW |
2383 | return 0; |
2384 | } | |
2385 | ||
7eb552ae | 2386 | if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) { |
5826eca5 ED |
2387 | DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n", |
2388 | intel_crtc->plane, | |
7eb552ae | 2389 | INTEL_INFO(dev)->num_pipes); |
5c3b82e2 | 2390 | return -EINVAL; |
79e53945 JB |
2391 | } |
2392 | ||
5c3b82e2 | 2393 | mutex_lock(&dev->struct_mutex); |
265db958 | 2394 | ret = intel_pin_and_fence_fb_obj(dev, |
94352cf9 | 2395 | to_intel_framebuffer(fb)->obj, |
919926ae | 2396 | NULL); |
5c3b82e2 CW |
2397 | if (ret != 0) { |
2398 | mutex_unlock(&dev->struct_mutex); | |
a5071c2f | 2399 | DRM_ERROR("pin & fence failed\n"); |
5c3b82e2 CW |
2400 | return ret; |
2401 | } | |
79e53945 | 2402 | |
94352cf9 | 2403 | ret = dev_priv->display.update_plane(crtc, fb, x, y); |
4e6cfefc | 2404 | if (ret) { |
94352cf9 | 2405 | intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj); |
5c3b82e2 | 2406 | mutex_unlock(&dev->struct_mutex); |
a5071c2f | 2407 | DRM_ERROR("failed to update base address\n"); |
4e6cfefc | 2408 | return ret; |
79e53945 | 2409 | } |
3c4fdcfb | 2410 | |
94352cf9 DV |
2411 | old_fb = crtc->fb; |
2412 | crtc->fb = fb; | |
6c4c86f5 DV |
2413 | crtc->x = x; |
2414 | crtc->y = y; | |
94352cf9 | 2415 | |
b7f1de28 CW |
2416 | if (old_fb) { |
2417 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
1690e1eb | 2418 | intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); |
b7f1de28 | 2419 | } |
652c393a | 2420 | |
6b8e6ed0 | 2421 | intel_update_fbc(dev); |
5c3b82e2 | 2422 | mutex_unlock(&dev->struct_mutex); |
79e53945 | 2423 | |
198598d0 | 2424 | intel_crtc_update_sarea_pos(crtc, x, y); |
5c3b82e2 CW |
2425 | |
2426 | return 0; | |
79e53945 JB |
2427 | } |
2428 | ||
5e84e1a4 ZW |
2429 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
2430 | { | |
2431 | struct drm_device *dev = crtc->dev; | |
2432 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2433 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2434 | int pipe = intel_crtc->pipe; | |
2435 | u32 reg, temp; | |
2436 | ||
2437 | /* enable normal train */ | |
2438 | reg = FDI_TX_CTL(pipe); | |
2439 | temp = I915_READ(reg); | |
61e499bf | 2440 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
2441 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2442 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
2443 | } else { |
2444 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2445 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 2446 | } |
5e84e1a4 ZW |
2447 | I915_WRITE(reg, temp); |
2448 | ||
2449 | reg = FDI_RX_CTL(pipe); | |
2450 | temp = I915_READ(reg); | |
2451 | if (HAS_PCH_CPT(dev)) { | |
2452 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2453 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
2454 | } else { | |
2455 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2456 | temp |= FDI_LINK_TRAIN_NONE; | |
2457 | } | |
2458 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
2459 | ||
2460 | /* wait one idle pattern time */ | |
2461 | POSTING_READ(reg); | |
2462 | udelay(1000); | |
357555c0 JB |
2463 | |
2464 | /* IVB wants error correction enabled */ | |
2465 | if (IS_IVYBRIDGE(dev)) | |
2466 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
2467 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
2468 | } |
2469 | ||
01a415fd DV |
2470 | static void ivb_modeset_global_resources(struct drm_device *dev) |
2471 | { | |
2472 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2473 | struct intel_crtc *pipe_B_crtc = | |
2474 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
2475 | struct intel_crtc *pipe_C_crtc = | |
2476 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]); | |
2477 | uint32_t temp; | |
2478 | ||
2479 | /* When everything is off disable fdi C so that we could enable fdi B | |
2480 | * with all lanes. XXX: This misses the case where a pipe is not using | |
2481 | * any pch resources and so doesn't need any fdi lanes. */ | |
2482 | if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) { | |
2483 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
2484 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
2485 | ||
2486 | temp = I915_READ(SOUTH_CHICKEN1); | |
2487 | temp &= ~FDI_BC_BIFURCATION_SELECT; | |
2488 | DRM_DEBUG_KMS("disabling fdi C rx\n"); | |
2489 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
2490 | } | |
2491 | } | |
2492 | ||
8db9d77b ZW |
2493 | /* The FDI link training functions for ILK/Ibexpeak. */ |
2494 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
2495 | { | |
2496 | struct drm_device *dev = crtc->dev; | |
2497 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2498 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2499 | int pipe = intel_crtc->pipe; | |
0fc932b8 | 2500 | int plane = intel_crtc->plane; |
5eddb70b | 2501 | u32 reg, temp, tries; |
8db9d77b | 2502 | |
0fc932b8 JB |
2503 | /* FDI needs bits from pipe & plane first */ |
2504 | assert_pipe_enabled(dev_priv, pipe); | |
2505 | assert_plane_enabled(dev_priv, plane); | |
2506 | ||
e1a44743 AJ |
2507 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2508 | for train result */ | |
5eddb70b CW |
2509 | reg = FDI_RX_IMR(pipe); |
2510 | temp = I915_READ(reg); | |
e1a44743 AJ |
2511 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2512 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2513 | I915_WRITE(reg, temp); |
2514 | I915_READ(reg); | |
e1a44743 AJ |
2515 | udelay(150); |
2516 | ||
8db9d77b | 2517 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2518 | reg = FDI_TX_CTL(pipe); |
2519 | temp = I915_READ(reg); | |
77ffb597 AJ |
2520 | temp &= ~(7 << 19); |
2521 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
8db9d77b ZW |
2522 | temp &= ~FDI_LINK_TRAIN_NONE; |
2523 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 2524 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2525 | |
5eddb70b CW |
2526 | reg = FDI_RX_CTL(pipe); |
2527 | temp = I915_READ(reg); | |
8db9d77b ZW |
2528 | temp &= ~FDI_LINK_TRAIN_NONE; |
2529 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
2530 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2531 | ||
2532 | POSTING_READ(reg); | |
8db9d77b ZW |
2533 | udelay(150); |
2534 | ||
5b2adf89 | 2535 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
2536 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
2537 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
2538 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 2539 | |
5eddb70b | 2540 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2541 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2542 | temp = I915_READ(reg); |
8db9d77b ZW |
2543 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2544 | ||
2545 | if ((temp & FDI_RX_BIT_LOCK)) { | |
2546 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 2547 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
2548 | break; |
2549 | } | |
8db9d77b | 2550 | } |
e1a44743 | 2551 | if (tries == 5) |
5eddb70b | 2552 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2553 | |
2554 | /* Train 2 */ | |
5eddb70b CW |
2555 | reg = FDI_TX_CTL(pipe); |
2556 | temp = I915_READ(reg); | |
8db9d77b ZW |
2557 | temp &= ~FDI_LINK_TRAIN_NONE; |
2558 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2559 | I915_WRITE(reg, temp); |
8db9d77b | 2560 | |
5eddb70b CW |
2561 | reg = FDI_RX_CTL(pipe); |
2562 | temp = I915_READ(reg); | |
8db9d77b ZW |
2563 | temp &= ~FDI_LINK_TRAIN_NONE; |
2564 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2565 | I915_WRITE(reg, temp); |
8db9d77b | 2566 | |
5eddb70b CW |
2567 | POSTING_READ(reg); |
2568 | udelay(150); | |
8db9d77b | 2569 | |
5eddb70b | 2570 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2571 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2572 | temp = I915_READ(reg); |
8db9d77b ZW |
2573 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2574 | ||
2575 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 2576 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
2577 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2578 | break; | |
2579 | } | |
8db9d77b | 2580 | } |
e1a44743 | 2581 | if (tries == 5) |
5eddb70b | 2582 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2583 | |
2584 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 2585 | |
8db9d77b ZW |
2586 | } |
2587 | ||
0206e353 | 2588 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
2589 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
2590 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
2591 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
2592 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
2593 | }; | |
2594 | ||
2595 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
2596 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
2597 | { | |
2598 | struct drm_device *dev = crtc->dev; | |
2599 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2600 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2601 | int pipe = intel_crtc->pipe; | |
fa37d39e | 2602 | u32 reg, temp, i, retry; |
8db9d77b | 2603 | |
e1a44743 AJ |
2604 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2605 | for train result */ | |
5eddb70b CW |
2606 | reg = FDI_RX_IMR(pipe); |
2607 | temp = I915_READ(reg); | |
e1a44743 AJ |
2608 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2609 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2610 | I915_WRITE(reg, temp); |
2611 | ||
2612 | POSTING_READ(reg); | |
e1a44743 AJ |
2613 | udelay(150); |
2614 | ||
8db9d77b | 2615 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2616 | reg = FDI_TX_CTL(pipe); |
2617 | temp = I915_READ(reg); | |
77ffb597 AJ |
2618 | temp &= ~(7 << 19); |
2619 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
8db9d77b ZW |
2620 | temp &= ~FDI_LINK_TRAIN_NONE; |
2621 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2622 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2623 | /* SNB-B */ | |
2624 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 2625 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2626 | |
d74cf324 DV |
2627 | I915_WRITE(FDI_RX_MISC(pipe), |
2628 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
2629 | ||
5eddb70b CW |
2630 | reg = FDI_RX_CTL(pipe); |
2631 | temp = I915_READ(reg); | |
8db9d77b ZW |
2632 | if (HAS_PCH_CPT(dev)) { |
2633 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2634 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2635 | } else { | |
2636 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2637 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2638 | } | |
5eddb70b CW |
2639 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2640 | ||
2641 | POSTING_READ(reg); | |
8db9d77b ZW |
2642 | udelay(150); |
2643 | ||
0206e353 | 2644 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2645 | reg = FDI_TX_CTL(pipe); |
2646 | temp = I915_READ(reg); | |
8db9d77b ZW |
2647 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2648 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2649 | I915_WRITE(reg, temp); |
2650 | ||
2651 | POSTING_READ(reg); | |
8db9d77b ZW |
2652 | udelay(500); |
2653 | ||
fa37d39e SP |
2654 | for (retry = 0; retry < 5; retry++) { |
2655 | reg = FDI_RX_IIR(pipe); | |
2656 | temp = I915_READ(reg); | |
2657 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2658 | if (temp & FDI_RX_BIT_LOCK) { | |
2659 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
2660 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
2661 | break; | |
2662 | } | |
2663 | udelay(50); | |
8db9d77b | 2664 | } |
fa37d39e SP |
2665 | if (retry < 5) |
2666 | break; | |
8db9d77b ZW |
2667 | } |
2668 | if (i == 4) | |
5eddb70b | 2669 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2670 | |
2671 | /* Train 2 */ | |
5eddb70b CW |
2672 | reg = FDI_TX_CTL(pipe); |
2673 | temp = I915_READ(reg); | |
8db9d77b ZW |
2674 | temp &= ~FDI_LINK_TRAIN_NONE; |
2675 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2676 | if (IS_GEN6(dev)) { | |
2677 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2678 | /* SNB-B */ | |
2679 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
2680 | } | |
5eddb70b | 2681 | I915_WRITE(reg, temp); |
8db9d77b | 2682 | |
5eddb70b CW |
2683 | reg = FDI_RX_CTL(pipe); |
2684 | temp = I915_READ(reg); | |
8db9d77b ZW |
2685 | if (HAS_PCH_CPT(dev)) { |
2686 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2687 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
2688 | } else { | |
2689 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2690 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2691 | } | |
5eddb70b CW |
2692 | I915_WRITE(reg, temp); |
2693 | ||
2694 | POSTING_READ(reg); | |
8db9d77b ZW |
2695 | udelay(150); |
2696 | ||
0206e353 | 2697 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2698 | reg = FDI_TX_CTL(pipe); |
2699 | temp = I915_READ(reg); | |
8db9d77b ZW |
2700 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2701 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2702 | I915_WRITE(reg, temp); |
2703 | ||
2704 | POSTING_READ(reg); | |
8db9d77b ZW |
2705 | udelay(500); |
2706 | ||
fa37d39e SP |
2707 | for (retry = 0; retry < 5; retry++) { |
2708 | reg = FDI_RX_IIR(pipe); | |
2709 | temp = I915_READ(reg); | |
2710 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2711 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
2712 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
2713 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
2714 | break; | |
2715 | } | |
2716 | udelay(50); | |
8db9d77b | 2717 | } |
fa37d39e SP |
2718 | if (retry < 5) |
2719 | break; | |
8db9d77b ZW |
2720 | } |
2721 | if (i == 4) | |
5eddb70b | 2722 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2723 | |
2724 | DRM_DEBUG_KMS("FDI train done.\n"); | |
2725 | } | |
2726 | ||
357555c0 JB |
2727 | /* Manual link training for Ivy Bridge A0 parts */ |
2728 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
2729 | { | |
2730 | struct drm_device *dev = crtc->dev; | |
2731 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2732 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2733 | int pipe = intel_crtc->pipe; | |
2734 | u32 reg, temp, i; | |
2735 | ||
2736 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
2737 | for train result */ | |
2738 | reg = FDI_RX_IMR(pipe); | |
2739 | temp = I915_READ(reg); | |
2740 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
2741 | temp &= ~FDI_RX_BIT_LOCK; | |
2742 | I915_WRITE(reg, temp); | |
2743 | ||
2744 | POSTING_READ(reg); | |
2745 | udelay(150); | |
2746 | ||
01a415fd DV |
2747 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
2748 | I915_READ(FDI_RX_IIR(pipe))); | |
2749 | ||
357555c0 JB |
2750 | /* enable CPU FDI TX and PCH FDI RX */ |
2751 | reg = FDI_TX_CTL(pipe); | |
2752 | temp = I915_READ(reg); | |
2753 | temp &= ~(7 << 19); | |
2754 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
2755 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
2756 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; | |
2757 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2758 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
c4f9c4c2 | 2759 | temp |= FDI_COMPOSITE_SYNC; |
357555c0 JB |
2760 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
2761 | ||
d74cf324 DV |
2762 | I915_WRITE(FDI_RX_MISC(pipe), |
2763 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
2764 | ||
357555c0 JB |
2765 | reg = FDI_RX_CTL(pipe); |
2766 | temp = I915_READ(reg); | |
2767 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
2768 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2769 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
c4f9c4c2 | 2770 | temp |= FDI_COMPOSITE_SYNC; |
357555c0 JB |
2771 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2772 | ||
2773 | POSTING_READ(reg); | |
2774 | udelay(150); | |
2775 | ||
0206e353 | 2776 | for (i = 0; i < 4; i++) { |
357555c0 JB |
2777 | reg = FDI_TX_CTL(pipe); |
2778 | temp = I915_READ(reg); | |
2779 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2780 | temp |= snb_b_fdi_train_param[i]; | |
2781 | I915_WRITE(reg, temp); | |
2782 | ||
2783 | POSTING_READ(reg); | |
2784 | udelay(500); | |
2785 | ||
2786 | reg = FDI_RX_IIR(pipe); | |
2787 | temp = I915_READ(reg); | |
2788 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2789 | ||
2790 | if (temp & FDI_RX_BIT_LOCK || | |
2791 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
2792 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
01a415fd | 2793 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i); |
357555c0 JB |
2794 | break; |
2795 | } | |
2796 | } | |
2797 | if (i == 4) | |
2798 | DRM_ERROR("FDI train 1 fail!\n"); | |
2799 | ||
2800 | /* Train 2 */ | |
2801 | reg = FDI_TX_CTL(pipe); | |
2802 | temp = I915_READ(reg); | |
2803 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; | |
2804 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
2805 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2806 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
2807 | I915_WRITE(reg, temp); | |
2808 | ||
2809 | reg = FDI_RX_CTL(pipe); | |
2810 | temp = I915_READ(reg); | |
2811 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2812 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
2813 | I915_WRITE(reg, temp); | |
2814 | ||
2815 | POSTING_READ(reg); | |
2816 | udelay(150); | |
2817 | ||
0206e353 | 2818 | for (i = 0; i < 4; i++) { |
357555c0 JB |
2819 | reg = FDI_TX_CTL(pipe); |
2820 | temp = I915_READ(reg); | |
2821 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2822 | temp |= snb_b_fdi_train_param[i]; | |
2823 | I915_WRITE(reg, temp); | |
2824 | ||
2825 | POSTING_READ(reg); | |
2826 | udelay(500); | |
2827 | ||
2828 | reg = FDI_RX_IIR(pipe); | |
2829 | temp = I915_READ(reg); | |
2830 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2831 | ||
2832 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
2833 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
01a415fd | 2834 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i); |
357555c0 JB |
2835 | break; |
2836 | } | |
2837 | } | |
2838 | if (i == 4) | |
2839 | DRM_ERROR("FDI train 2 fail!\n"); | |
2840 | ||
2841 | DRM_DEBUG_KMS("FDI train done.\n"); | |
2842 | } | |
2843 | ||
88cefb6c | 2844 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 2845 | { |
88cefb6c | 2846 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 2847 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 2848 | int pipe = intel_crtc->pipe; |
5eddb70b | 2849 | u32 reg, temp; |
79e53945 | 2850 | |
c64e311e | 2851 | |
c98e9dcf | 2852 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
2853 | reg = FDI_RX_CTL(pipe); |
2854 | temp = I915_READ(reg); | |
2855 | temp &= ~((0x7 << 19) | (0x7 << 16)); | |
c98e9dcf | 2856 | temp |= (intel_crtc->fdi_lanes - 1) << 19; |
dfd07d72 | 2857 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
2858 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
2859 | ||
2860 | POSTING_READ(reg); | |
c98e9dcf JB |
2861 | udelay(200); |
2862 | ||
2863 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
2864 | temp = I915_READ(reg); |
2865 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
2866 | ||
2867 | POSTING_READ(reg); | |
c98e9dcf JB |
2868 | udelay(200); |
2869 | ||
20749730 PZ |
2870 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
2871 | reg = FDI_TX_CTL(pipe); | |
2872 | temp = I915_READ(reg); | |
2873 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
2874 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 2875 | |
20749730 PZ |
2876 | POSTING_READ(reg); |
2877 | udelay(100); | |
6be4a607 | 2878 | } |
0e23b99d JB |
2879 | } |
2880 | ||
88cefb6c DV |
2881 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
2882 | { | |
2883 | struct drm_device *dev = intel_crtc->base.dev; | |
2884 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2885 | int pipe = intel_crtc->pipe; | |
2886 | u32 reg, temp; | |
2887 | ||
2888 | /* Switch from PCDclk to Rawclk */ | |
2889 | reg = FDI_RX_CTL(pipe); | |
2890 | temp = I915_READ(reg); | |
2891 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
2892 | ||
2893 | /* Disable CPU FDI TX PLL */ | |
2894 | reg = FDI_TX_CTL(pipe); | |
2895 | temp = I915_READ(reg); | |
2896 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
2897 | ||
2898 | POSTING_READ(reg); | |
2899 | udelay(100); | |
2900 | ||
2901 | reg = FDI_RX_CTL(pipe); | |
2902 | temp = I915_READ(reg); | |
2903 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
2904 | ||
2905 | /* Wait for the clocks to turn off. */ | |
2906 | POSTING_READ(reg); | |
2907 | udelay(100); | |
2908 | } | |
2909 | ||
0fc932b8 JB |
2910 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
2911 | { | |
2912 | struct drm_device *dev = crtc->dev; | |
2913 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2914 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2915 | int pipe = intel_crtc->pipe; | |
2916 | u32 reg, temp; | |
2917 | ||
2918 | /* disable CPU FDI tx and PCH FDI rx */ | |
2919 | reg = FDI_TX_CTL(pipe); | |
2920 | temp = I915_READ(reg); | |
2921 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
2922 | POSTING_READ(reg); | |
2923 | ||
2924 | reg = FDI_RX_CTL(pipe); | |
2925 | temp = I915_READ(reg); | |
2926 | temp &= ~(0x7 << 16); | |
dfd07d72 | 2927 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
2928 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
2929 | ||
2930 | POSTING_READ(reg); | |
2931 | udelay(100); | |
2932 | ||
2933 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
6f06ce18 JB |
2934 | if (HAS_PCH_IBX(dev)) { |
2935 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); | |
6f06ce18 | 2936 | } |
0fc932b8 JB |
2937 | |
2938 | /* still set train pattern 1 */ | |
2939 | reg = FDI_TX_CTL(pipe); | |
2940 | temp = I915_READ(reg); | |
2941 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2942 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2943 | I915_WRITE(reg, temp); | |
2944 | ||
2945 | reg = FDI_RX_CTL(pipe); | |
2946 | temp = I915_READ(reg); | |
2947 | if (HAS_PCH_CPT(dev)) { | |
2948 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2949 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2950 | } else { | |
2951 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2952 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2953 | } | |
2954 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
2955 | temp &= ~(0x07 << 16); | |
dfd07d72 | 2956 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
2957 | I915_WRITE(reg, temp); |
2958 | ||
2959 | POSTING_READ(reg); | |
2960 | udelay(100); | |
2961 | } | |
2962 | ||
5bb61643 CW |
2963 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
2964 | { | |
2965 | struct drm_device *dev = crtc->dev; | |
2966 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10d83730 | 2967 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5bb61643 CW |
2968 | unsigned long flags; |
2969 | bool pending; | |
2970 | ||
10d83730 VS |
2971 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
2972 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
5bb61643 CW |
2973 | return false; |
2974 | ||
2975 | spin_lock_irqsave(&dev->event_lock, flags); | |
2976 | pending = to_intel_crtc(crtc)->unpin_work != NULL; | |
2977 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
2978 | ||
2979 | return pending; | |
2980 | } | |
2981 | ||
e6c3a2a6 CW |
2982 | static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
2983 | { | |
0f91128d | 2984 | struct drm_device *dev = crtc->dev; |
5bb61643 | 2985 | struct drm_i915_private *dev_priv = dev->dev_private; |
e6c3a2a6 CW |
2986 | |
2987 | if (crtc->fb == NULL) | |
2988 | return; | |
2989 | ||
2c10d571 DV |
2990 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
2991 | ||
5bb61643 CW |
2992 | wait_event(dev_priv->pending_flip_queue, |
2993 | !intel_crtc_has_pending_flip(crtc)); | |
2994 | ||
0f91128d CW |
2995 | mutex_lock(&dev->struct_mutex); |
2996 | intel_finish_fb(crtc->fb); | |
2997 | mutex_unlock(&dev->struct_mutex); | |
e6c3a2a6 CW |
2998 | } |
2999 | ||
e615efe4 ED |
3000 | /* Program iCLKIP clock to the desired frequency */ |
3001 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3002 | { | |
3003 | struct drm_device *dev = crtc->dev; | |
3004 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3005 | u32 divsel, phaseinc, auxdiv, phasedir = 0; | |
3006 | u32 temp; | |
3007 | ||
09153000 DV |
3008 | mutex_lock(&dev_priv->dpio_lock); |
3009 | ||
e615efe4 ED |
3010 | /* It is necessary to ungate the pixclk gate prior to programming |
3011 | * the divisors, and gate it back when it is done. | |
3012 | */ | |
3013 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3014 | ||
3015 | /* Disable SSCCTL */ | |
3016 | intel_sbi_write(dev_priv, SBI_SSCCTL6, | |
988d6ee8 PZ |
3017 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
3018 | SBI_SSCCTL_DISABLE, | |
3019 | SBI_ICLK); | |
e615efe4 ED |
3020 | |
3021 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
3022 | if (crtc->mode.clock == 20000) { | |
3023 | auxdiv = 1; | |
3024 | divsel = 0x41; | |
3025 | phaseinc = 0x20; | |
3026 | } else { | |
3027 | /* The iCLK virtual clock root frequency is in MHz, | |
3028 | * but the crtc->mode.clock in in KHz. To get the divisors, | |
3029 | * it is necessary to divide one by another, so we | |
3030 | * convert the virtual clock precision to KHz here for higher | |
3031 | * precision. | |
3032 | */ | |
3033 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3034 | u32 iclk_pi_range = 64; | |
3035 | u32 desired_divisor, msb_divisor_value, pi_value; | |
3036 | ||
3037 | desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock); | |
3038 | msb_divisor_value = desired_divisor / iclk_pi_range; | |
3039 | pi_value = desired_divisor % iclk_pi_range; | |
3040 | ||
3041 | auxdiv = 0; | |
3042 | divsel = msb_divisor_value - 2; | |
3043 | phaseinc = pi_value; | |
3044 | } | |
3045 | ||
3046 | /* This should not happen with any sane values */ | |
3047 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3048 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3049 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3050 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3051 | ||
3052 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
3053 | crtc->mode.clock, | |
3054 | auxdiv, | |
3055 | divsel, | |
3056 | phasedir, | |
3057 | phaseinc); | |
3058 | ||
3059 | /* Program SSCDIVINTPHASE6 */ | |
988d6ee8 | 3060 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
3061 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
3062 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
3063 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
3064 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
3065 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
3066 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 3067 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
3068 | |
3069 | /* Program SSCAUXDIV */ | |
988d6ee8 | 3070 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
3071 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
3072 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 3073 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
3074 | |
3075 | /* Enable modulator and associated divider */ | |
988d6ee8 | 3076 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 3077 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 3078 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 ED |
3079 | |
3080 | /* Wait for initialization time */ | |
3081 | udelay(24); | |
3082 | ||
3083 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
09153000 DV |
3084 | |
3085 | mutex_unlock(&dev_priv->dpio_lock); | |
e615efe4 ED |
3086 | } |
3087 | ||
f67a559d JB |
3088 | /* |
3089 | * Enable PCH resources required for PCH ports: | |
3090 | * - PCH PLLs | |
3091 | * - FDI training & RX/TX | |
3092 | * - update transcoder timings | |
3093 | * - DP transcoding bits | |
3094 | * - transcoder | |
3095 | */ | |
3096 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
3097 | { |
3098 | struct drm_device *dev = crtc->dev; | |
3099 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3100 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3101 | int pipe = intel_crtc->pipe; | |
ee7b9f93 | 3102 | u32 reg, temp; |
2c07245f | 3103 | |
e7e164db CW |
3104 | assert_transcoder_disabled(dev_priv, pipe); |
3105 | ||
cd986abb DV |
3106 | /* Write the TU size bits before fdi link training, so that error |
3107 | * detection works. */ | |
3108 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
3109 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
3110 | ||
c98e9dcf | 3111 | /* For PCH output, training FDI link */ |
674cf967 | 3112 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 3113 | |
572deb37 DV |
3114 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
3115 | * transcoder, and we actually should do this to not upset any PCH | |
3116 | * transcoder that already use the clock when we share it. | |
3117 | * | |
3118 | * Note that enable_pch_pll tries to do the right thing, but get_pch_pll | |
3119 | * unconditionally resets the pll - we need that to have the right LVDS | |
3120 | * enable sequence. */ | |
b6b4e185 | 3121 | ironlake_enable_pch_pll(intel_crtc); |
6f13b7b5 | 3122 | |
303b81e0 | 3123 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 3124 | u32 sel; |
4b645f14 | 3125 | |
c98e9dcf | 3126 | temp = I915_READ(PCH_DPLL_SEL); |
ee7b9f93 JB |
3127 | switch (pipe) { |
3128 | default: | |
3129 | case 0: | |
3130 | temp |= TRANSA_DPLL_ENABLE; | |
3131 | sel = TRANSA_DPLLB_SEL; | |
3132 | break; | |
3133 | case 1: | |
3134 | temp |= TRANSB_DPLL_ENABLE; | |
3135 | sel = TRANSB_DPLLB_SEL; | |
3136 | break; | |
3137 | case 2: | |
3138 | temp |= TRANSC_DPLL_ENABLE; | |
3139 | sel = TRANSC_DPLLB_SEL; | |
3140 | break; | |
d64311ab | 3141 | } |
ee7b9f93 JB |
3142 | if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B) |
3143 | temp |= sel; | |
3144 | else | |
3145 | temp &= ~sel; | |
c98e9dcf | 3146 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 3147 | } |
5eddb70b | 3148 | |
d9b6cb56 JB |
3149 | /* set transcoder timing, panel must allow it */ |
3150 | assert_panel_unlocked(dev_priv, pipe); | |
5eddb70b CW |
3151 | I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe))); |
3152 | I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe))); | |
3153 | I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe))); | |
8db9d77b | 3154 | |
5eddb70b CW |
3155 | I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe))); |
3156 | I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe))); | |
3157 | I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe))); | |
0529a0d9 | 3158 | I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe))); |
8db9d77b | 3159 | |
303b81e0 | 3160 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 3161 | |
c98e9dcf JB |
3162 | /* For PCH DP, enable TRANS_DP_CTL */ |
3163 | if (HAS_PCH_CPT(dev) && | |
417e822d KP |
3164 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
3165 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
dfd07d72 | 3166 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
5eddb70b CW |
3167 | reg = TRANS_DP_CTL(pipe); |
3168 | temp = I915_READ(reg); | |
3169 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
3170 | TRANS_DP_SYNC_MASK | |
3171 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
3172 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
3173 | TRANS_DP_ENH_FRAMING); | |
9325c9f0 | 3174 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
3175 | |
3176 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 3177 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 3178 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 3179 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
3180 | |
3181 | switch (intel_trans_dp_port_sel(crtc)) { | |
3182 | case PCH_DP_B: | |
5eddb70b | 3183 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
3184 | break; |
3185 | case PCH_DP_C: | |
5eddb70b | 3186 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
3187 | break; |
3188 | case PCH_DP_D: | |
5eddb70b | 3189 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
3190 | break; |
3191 | default: | |
e95d41e1 | 3192 | BUG(); |
32f9d658 | 3193 | } |
2c07245f | 3194 | |
5eddb70b | 3195 | I915_WRITE(reg, temp); |
6be4a607 | 3196 | } |
b52eb4dc | 3197 | |
b8a4f404 | 3198 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
3199 | } |
3200 | ||
1507e5bd PZ |
3201 | static void lpt_pch_enable(struct drm_crtc *crtc) |
3202 | { | |
3203 | struct drm_device *dev = crtc->dev; | |
3204 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3205 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
daed2dbb | 3206 | enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; |
1507e5bd | 3207 | |
daed2dbb | 3208 | assert_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 3209 | |
8c52b5e8 | 3210 | lpt_program_iclkip(crtc); |
1507e5bd | 3211 | |
0540e488 | 3212 | /* Set transcoder timing. */ |
daed2dbb PZ |
3213 | I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder))); |
3214 | I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder))); | |
3215 | I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder))); | |
1507e5bd | 3216 | |
daed2dbb PZ |
3217 | I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder))); |
3218 | I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder))); | |
3219 | I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder))); | |
3220 | I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
1507e5bd | 3221 | |
937bb610 | 3222 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
3223 | } |
3224 | ||
ee7b9f93 JB |
3225 | static void intel_put_pch_pll(struct intel_crtc *intel_crtc) |
3226 | { | |
3227 | struct intel_pch_pll *pll = intel_crtc->pch_pll; | |
3228 | ||
3229 | if (pll == NULL) | |
3230 | return; | |
3231 | ||
3232 | if (pll->refcount == 0) { | |
3233 | WARN(1, "bad PCH PLL refcount\n"); | |
3234 | return; | |
3235 | } | |
3236 | ||
3237 | --pll->refcount; | |
3238 | intel_crtc->pch_pll = NULL; | |
3239 | } | |
3240 | ||
3241 | static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp) | |
3242 | { | |
3243 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; | |
3244 | struct intel_pch_pll *pll; | |
3245 | int i; | |
3246 | ||
3247 | pll = intel_crtc->pch_pll; | |
3248 | if (pll) { | |
3249 | DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n", | |
3250 | intel_crtc->base.base.id, pll->pll_reg); | |
3251 | goto prepare; | |
3252 | } | |
3253 | ||
98b6bd99 DV |
3254 | if (HAS_PCH_IBX(dev_priv->dev)) { |
3255 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
3256 | i = intel_crtc->pipe; | |
3257 | pll = &dev_priv->pch_plls[i]; | |
3258 | ||
3259 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n", | |
3260 | intel_crtc->base.base.id, pll->pll_reg); | |
3261 | ||
3262 | goto found; | |
3263 | } | |
3264 | ||
ee7b9f93 JB |
3265 | for (i = 0; i < dev_priv->num_pch_pll; i++) { |
3266 | pll = &dev_priv->pch_plls[i]; | |
3267 | ||
3268 | /* Only want to check enabled timings first */ | |
3269 | if (pll->refcount == 0) | |
3270 | continue; | |
3271 | ||
3272 | if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) && | |
3273 | fp == I915_READ(pll->fp0_reg)) { | |
3274 | DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n", | |
3275 | intel_crtc->base.base.id, | |
3276 | pll->pll_reg, pll->refcount, pll->active); | |
3277 | ||
3278 | goto found; | |
3279 | } | |
3280 | } | |
3281 | ||
3282 | /* Ok no matching timings, maybe there's a free one? */ | |
3283 | for (i = 0; i < dev_priv->num_pch_pll; i++) { | |
3284 | pll = &dev_priv->pch_plls[i]; | |
3285 | if (pll->refcount == 0) { | |
3286 | DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n", | |
3287 | intel_crtc->base.base.id, pll->pll_reg); | |
3288 | goto found; | |
3289 | } | |
3290 | } | |
3291 | ||
3292 | return NULL; | |
3293 | ||
3294 | found: | |
3295 | intel_crtc->pch_pll = pll; | |
3296 | pll->refcount++; | |
3297 | DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe); | |
3298 | prepare: /* separate function? */ | |
3299 | DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg); | |
ee7b9f93 | 3300 | |
e04c7350 CW |
3301 | /* Wait for the clocks to stabilize before rewriting the regs */ |
3302 | I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE); | |
ee7b9f93 JB |
3303 | POSTING_READ(pll->pll_reg); |
3304 | udelay(150); | |
e04c7350 CW |
3305 | |
3306 | I915_WRITE(pll->fp0_reg, fp); | |
3307 | I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE); | |
ee7b9f93 JB |
3308 | pll->on = false; |
3309 | return pll; | |
3310 | } | |
3311 | ||
d4270e57 JB |
3312 | void intel_cpt_verify_modeset(struct drm_device *dev, int pipe) |
3313 | { | |
3314 | struct drm_i915_private *dev_priv = dev->dev_private; | |
23670b32 | 3315 | int dslreg = PIPEDSL(pipe); |
d4270e57 JB |
3316 | u32 temp; |
3317 | ||
3318 | temp = I915_READ(dslreg); | |
3319 | udelay(500); | |
3320 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 JB |
3321 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
3322 | DRM_ERROR("mode set failed: pipe %d stuck\n", pipe); | |
3323 | } | |
3324 | } | |
3325 | ||
f67a559d JB |
3326 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
3327 | { | |
3328 | struct drm_device *dev = crtc->dev; | |
3329 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3330 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3331 | struct intel_encoder *encoder; |
f67a559d JB |
3332 | int pipe = intel_crtc->pipe; |
3333 | int plane = intel_crtc->plane; | |
3334 | u32 temp; | |
f67a559d | 3335 | |
08a48469 DV |
3336 | WARN_ON(!crtc->enabled); |
3337 | ||
f67a559d JB |
3338 | if (intel_crtc->active) |
3339 | return; | |
3340 | ||
3341 | intel_crtc->active = true; | |
3342 | intel_update_watermarks(dev); | |
3343 | ||
3344 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
3345 | temp = I915_READ(PCH_LVDS); | |
3346 | if ((temp & LVDS_PORT_EN) == 0) | |
3347 | I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN); | |
3348 | } | |
3349 | ||
f67a559d | 3350 | |
5bfe2ac0 | 3351 | if (intel_crtc->config.has_pch_encoder) { |
fff367c7 DV |
3352 | /* Note: FDI PLL enabling _must_ be done before we enable the |
3353 | * cpu pipes, hence this is separate from all the other fdi/pch | |
3354 | * enabling. */ | |
88cefb6c | 3355 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
3356 | } else { |
3357 | assert_fdi_tx_disabled(dev_priv, pipe); | |
3358 | assert_fdi_rx_disabled(dev_priv, pipe); | |
3359 | } | |
f67a559d | 3360 | |
bf49ec8c DV |
3361 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3362 | if (encoder->pre_enable) | |
3363 | encoder->pre_enable(encoder); | |
f67a559d JB |
3364 | |
3365 | /* Enable panel fitting for LVDS */ | |
3366 | if (dev_priv->pch_pf_size && | |
547dc041 JN |
3367 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
3368 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
f67a559d JB |
3369 | /* Force use of hard-coded filter coefficients |
3370 | * as some pre-programmed values are broken, | |
3371 | * e.g. x201. | |
3372 | */ | |
13888d78 PZ |
3373 | if (IS_IVYBRIDGE(dev)) |
3374 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
3375 | PF_PIPE_SEL_IVB(pipe)); | |
3376 | else | |
3377 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
9db4a9c7 JB |
3378 | I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos); |
3379 | I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size); | |
f67a559d JB |
3380 | } |
3381 | ||
9c54c0dd JB |
3382 | /* |
3383 | * On ILK+ LUT must be loaded before the pipe is running but with | |
3384 | * clocks enabled | |
3385 | */ | |
3386 | intel_crtc_load_lut(crtc); | |
3387 | ||
5bfe2ac0 DV |
3388 | intel_enable_pipe(dev_priv, pipe, |
3389 | intel_crtc->config.has_pch_encoder); | |
f67a559d JB |
3390 | intel_enable_plane(dev_priv, plane, pipe); |
3391 | ||
5bfe2ac0 | 3392 | if (intel_crtc->config.has_pch_encoder) |
f67a559d | 3393 | ironlake_pch_enable(crtc); |
c98e9dcf | 3394 | |
d1ebd816 | 3395 | mutex_lock(&dev->struct_mutex); |
bed4a673 | 3396 | intel_update_fbc(dev); |
d1ebd816 BW |
3397 | mutex_unlock(&dev->struct_mutex); |
3398 | ||
6b383a7f | 3399 | intel_crtc_update_cursor(crtc, true); |
ef9c3aee | 3400 | |
fa5c73b1 DV |
3401 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3402 | encoder->enable(encoder); | |
61b77ddd DV |
3403 | |
3404 | if (HAS_PCH_CPT(dev)) | |
3405 | intel_cpt_verify_modeset(dev, intel_crtc->pipe); | |
6ce94100 DV |
3406 | |
3407 | /* | |
3408 | * There seems to be a race in PCH platform hw (at least on some | |
3409 | * outputs) where an enabled pipe still completes any pageflip right | |
3410 | * away (as if the pipe is off) instead of waiting for vblank. As soon | |
3411 | * as the first vblank happend, everything works as expected. Hence just | |
3412 | * wait for one vblank before returning to avoid strange things | |
3413 | * happening. | |
3414 | */ | |
3415 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
6be4a607 JB |
3416 | } |
3417 | ||
4f771f10 PZ |
3418 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
3419 | { | |
3420 | struct drm_device *dev = crtc->dev; | |
3421 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3422 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3423 | struct intel_encoder *encoder; | |
3424 | int pipe = intel_crtc->pipe; | |
3425 | int plane = intel_crtc->plane; | |
4f771f10 PZ |
3426 | |
3427 | WARN_ON(!crtc->enabled); | |
3428 | ||
3429 | if (intel_crtc->active) | |
3430 | return; | |
3431 | ||
3432 | intel_crtc->active = true; | |
3433 | intel_update_watermarks(dev); | |
3434 | ||
5bfe2ac0 | 3435 | if (intel_crtc->config.has_pch_encoder) |
04945641 | 3436 | dev_priv->display.fdi_link_train(crtc); |
4f771f10 PZ |
3437 | |
3438 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
3439 | if (encoder->pre_enable) | |
3440 | encoder->pre_enable(encoder); | |
3441 | ||
1f544388 | 3442 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 3443 | |
1f544388 | 3444 | /* Enable panel fitting for eDP */ |
547dc041 JN |
3445 | if (dev_priv->pch_pf_size && |
3446 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) { | |
4f771f10 PZ |
3447 | /* Force use of hard-coded filter coefficients |
3448 | * as some pre-programmed values are broken, | |
3449 | * e.g. x201. | |
3450 | */ | |
54075a7d PZ |
3451 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | |
3452 | PF_PIPE_SEL_IVB(pipe)); | |
4f771f10 PZ |
3453 | I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos); |
3454 | I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size); | |
3455 | } | |
3456 | ||
3457 | /* | |
3458 | * On ILK+ LUT must be loaded before the pipe is running but with | |
3459 | * clocks enabled | |
3460 | */ | |
3461 | intel_crtc_load_lut(crtc); | |
3462 | ||
1f544388 | 3463 | intel_ddi_set_pipe_settings(crtc); |
8228c251 | 3464 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 3465 | |
5bfe2ac0 DV |
3466 | intel_enable_pipe(dev_priv, pipe, |
3467 | intel_crtc->config.has_pch_encoder); | |
4f771f10 PZ |
3468 | intel_enable_plane(dev_priv, plane, pipe); |
3469 | ||
5bfe2ac0 | 3470 | if (intel_crtc->config.has_pch_encoder) |
1507e5bd | 3471 | lpt_pch_enable(crtc); |
4f771f10 PZ |
3472 | |
3473 | mutex_lock(&dev->struct_mutex); | |
3474 | intel_update_fbc(dev); | |
3475 | mutex_unlock(&dev->struct_mutex); | |
3476 | ||
3477 | intel_crtc_update_cursor(crtc, true); | |
3478 | ||
3479 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
3480 | encoder->enable(encoder); | |
3481 | ||
4f771f10 PZ |
3482 | /* |
3483 | * There seems to be a race in PCH platform hw (at least on some | |
3484 | * outputs) where an enabled pipe still completes any pageflip right | |
3485 | * away (as if the pipe is off) instead of waiting for vblank. As soon | |
3486 | * as the first vblank happend, everything works as expected. Hence just | |
3487 | * wait for one vblank before returning to avoid strange things | |
3488 | * happening. | |
3489 | */ | |
3490 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
3491 | } | |
3492 | ||
6be4a607 JB |
3493 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
3494 | { | |
3495 | struct drm_device *dev = crtc->dev; | |
3496 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3497 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3498 | struct intel_encoder *encoder; |
6be4a607 JB |
3499 | int pipe = intel_crtc->pipe; |
3500 | int plane = intel_crtc->plane; | |
5eddb70b | 3501 | u32 reg, temp; |
b52eb4dc | 3502 | |
ef9c3aee | 3503 | |
f7abfe8b CW |
3504 | if (!intel_crtc->active) |
3505 | return; | |
3506 | ||
ea9d758d DV |
3507 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3508 | encoder->disable(encoder); | |
3509 | ||
e6c3a2a6 | 3510 | intel_crtc_wait_for_pending_flips(crtc); |
6be4a607 | 3511 | drm_vblank_off(dev, pipe); |
6b383a7f | 3512 | intel_crtc_update_cursor(crtc, false); |
5eddb70b | 3513 | |
b24e7179 | 3514 | intel_disable_plane(dev_priv, plane, pipe); |
913d8d11 | 3515 | |
973d04f9 CW |
3516 | if (dev_priv->cfb_plane == plane) |
3517 | intel_disable_fbc(dev); | |
2c07245f | 3518 | |
b24e7179 | 3519 | intel_disable_pipe(dev_priv, pipe); |
32f9d658 | 3520 | |
6be4a607 | 3521 | /* Disable PF */ |
9db4a9c7 JB |
3522 | I915_WRITE(PF_CTL(pipe), 0); |
3523 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
2c07245f | 3524 | |
bf49ec8c DV |
3525 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3526 | if (encoder->post_disable) | |
3527 | encoder->post_disable(encoder); | |
2c07245f | 3528 | |
0fc932b8 | 3529 | ironlake_fdi_disable(crtc); |
249c0e64 | 3530 | |
b8a4f404 | 3531 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
913d8d11 | 3532 | |
6be4a607 JB |
3533 | if (HAS_PCH_CPT(dev)) { |
3534 | /* disable TRANS_DP_CTL */ | |
5eddb70b CW |
3535 | reg = TRANS_DP_CTL(pipe); |
3536 | temp = I915_READ(reg); | |
3537 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK); | |
cb3543c6 | 3538 | temp |= TRANS_DP_PORT_SEL_NONE; |
5eddb70b | 3539 | I915_WRITE(reg, temp); |
6be4a607 JB |
3540 | |
3541 | /* disable DPLL_SEL */ | |
3542 | temp = I915_READ(PCH_DPLL_SEL); | |
9db4a9c7 JB |
3543 | switch (pipe) { |
3544 | case 0: | |
d64311ab | 3545 | temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL); |
9db4a9c7 JB |
3546 | break; |
3547 | case 1: | |
6be4a607 | 3548 | temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); |
9db4a9c7 JB |
3549 | break; |
3550 | case 2: | |
4b645f14 | 3551 | /* C shares PLL A or B */ |
d64311ab | 3552 | temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL); |
9db4a9c7 JB |
3553 | break; |
3554 | default: | |
3555 | BUG(); /* wtf */ | |
3556 | } | |
6be4a607 | 3557 | I915_WRITE(PCH_DPLL_SEL, temp); |
6be4a607 | 3558 | } |
e3421a18 | 3559 | |
6be4a607 | 3560 | /* disable PCH DPLL */ |
ee7b9f93 | 3561 | intel_disable_pch_pll(intel_crtc); |
8db9d77b | 3562 | |
88cefb6c | 3563 | ironlake_fdi_pll_disable(intel_crtc); |
6b383a7f | 3564 | |
f7abfe8b | 3565 | intel_crtc->active = false; |
6b383a7f | 3566 | intel_update_watermarks(dev); |
d1ebd816 BW |
3567 | |
3568 | mutex_lock(&dev->struct_mutex); | |
6b383a7f | 3569 | intel_update_fbc(dev); |
d1ebd816 | 3570 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 3571 | } |
1b3c7a47 | 3572 | |
4f771f10 | 3573 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 3574 | { |
4f771f10 PZ |
3575 | struct drm_device *dev = crtc->dev; |
3576 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 3577 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 PZ |
3578 | struct intel_encoder *encoder; |
3579 | int pipe = intel_crtc->pipe; | |
3580 | int plane = intel_crtc->plane; | |
ad80a810 | 3581 | enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; |
ee7b9f93 | 3582 | |
4f771f10 PZ |
3583 | if (!intel_crtc->active) |
3584 | return; | |
3585 | ||
3586 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
3587 | encoder->disable(encoder); | |
3588 | ||
3589 | intel_crtc_wait_for_pending_flips(crtc); | |
3590 | drm_vblank_off(dev, pipe); | |
3591 | intel_crtc_update_cursor(crtc, false); | |
3592 | ||
3593 | intel_disable_plane(dev_priv, plane, pipe); | |
3594 | ||
3595 | if (dev_priv->cfb_plane == plane) | |
3596 | intel_disable_fbc(dev); | |
3597 | ||
3598 | intel_disable_pipe(dev_priv, pipe); | |
3599 | ||
ad80a810 | 3600 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 PZ |
3601 | |
3602 | /* Disable PF */ | |
3603 | I915_WRITE(PF_CTL(pipe), 0); | |
3604 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
3605 | ||
1f544388 | 3606 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 PZ |
3607 | |
3608 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
3609 | if (encoder->post_disable) | |
3610 | encoder->post_disable(encoder); | |
3611 | ||
88adfff1 | 3612 | if (intel_crtc->config.has_pch_encoder) { |
ab4d966c | 3613 | lpt_disable_pch_transcoder(dev_priv); |
1ad960f2 | 3614 | intel_ddi_fdi_disable(crtc); |
83616634 | 3615 | } |
4f771f10 PZ |
3616 | |
3617 | intel_crtc->active = false; | |
3618 | intel_update_watermarks(dev); | |
3619 | ||
3620 | mutex_lock(&dev->struct_mutex); | |
3621 | intel_update_fbc(dev); | |
3622 | mutex_unlock(&dev->struct_mutex); | |
3623 | } | |
3624 | ||
ee7b9f93 JB |
3625 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
3626 | { | |
3627 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3628 | intel_put_pch_pll(intel_crtc); | |
3629 | } | |
3630 | ||
6441ab5f PZ |
3631 | static void haswell_crtc_off(struct drm_crtc *crtc) |
3632 | { | |
a5c961d1 PZ |
3633 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3634 | ||
3635 | /* Stop saying we're using TRANSCODER_EDP because some other CRTC might | |
3636 | * start using it. */ | |
1a240d4d | 3637 | intel_crtc->cpu_transcoder = (enum transcoder) intel_crtc->pipe; |
a5c961d1 | 3638 | |
6441ab5f PZ |
3639 | intel_ddi_put_crtc_pll(crtc); |
3640 | } | |
3641 | ||
02e792fb DV |
3642 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
3643 | { | |
02e792fb | 3644 | if (!enable && intel_crtc->overlay) { |
23f09ce3 | 3645 | struct drm_device *dev = intel_crtc->base.dev; |
ce453d81 | 3646 | struct drm_i915_private *dev_priv = dev->dev_private; |
03f77ea5 | 3647 | |
23f09ce3 | 3648 | mutex_lock(&dev->struct_mutex); |
ce453d81 CW |
3649 | dev_priv->mm.interruptible = false; |
3650 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
3651 | dev_priv->mm.interruptible = true; | |
23f09ce3 | 3652 | mutex_unlock(&dev->struct_mutex); |
02e792fb | 3653 | } |
02e792fb | 3654 | |
5dcdbcb0 CW |
3655 | /* Let userspace switch the overlay on again. In most cases userspace |
3656 | * has to recompute where to put it anyway. | |
3657 | */ | |
02e792fb DV |
3658 | } |
3659 | ||
61bc95c1 EE |
3660 | /** |
3661 | * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware | |
3662 | * cursor plane briefly if not already running after enabling the display | |
3663 | * plane. | |
3664 | * This workaround avoids occasional blank screens when self refresh is | |
3665 | * enabled. | |
3666 | */ | |
3667 | static void | |
3668 | g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe) | |
3669 | { | |
3670 | u32 cntl = I915_READ(CURCNTR(pipe)); | |
3671 | ||
3672 | if ((cntl & CURSOR_MODE) == 0) { | |
3673 | u32 fw_bcl_self = I915_READ(FW_BLC_SELF); | |
3674 | ||
3675 | I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN); | |
3676 | I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX); | |
3677 | intel_wait_for_vblank(dev_priv->dev, pipe); | |
3678 | I915_WRITE(CURCNTR(pipe), cntl); | |
3679 | I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe))); | |
3680 | I915_WRITE(FW_BLC_SELF, fw_bcl_self); | |
3681 | } | |
3682 | } | |
3683 | ||
0b8765c6 | 3684 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
3685 | { |
3686 | struct drm_device *dev = crtc->dev; | |
79e53945 JB |
3687 | struct drm_i915_private *dev_priv = dev->dev_private; |
3688 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3689 | struct intel_encoder *encoder; |
79e53945 | 3690 | int pipe = intel_crtc->pipe; |
80824003 | 3691 | int plane = intel_crtc->plane; |
79e53945 | 3692 | |
08a48469 DV |
3693 | WARN_ON(!crtc->enabled); |
3694 | ||
f7abfe8b CW |
3695 | if (intel_crtc->active) |
3696 | return; | |
3697 | ||
3698 | intel_crtc->active = true; | |
6b383a7f CW |
3699 | intel_update_watermarks(dev); |
3700 | ||
63d7bbe9 | 3701 | intel_enable_pll(dev_priv, pipe); |
9d6d9f19 MK |
3702 | |
3703 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
3704 | if (encoder->pre_enable) | |
3705 | encoder->pre_enable(encoder); | |
3706 | ||
040484af | 3707 | intel_enable_pipe(dev_priv, pipe, false); |
b24e7179 | 3708 | intel_enable_plane(dev_priv, plane, pipe); |
61bc95c1 EE |
3709 | if (IS_G4X(dev)) |
3710 | g4x_fixup_plane(dev_priv, pipe); | |
79e53945 | 3711 | |
0b8765c6 | 3712 | intel_crtc_load_lut(crtc); |
bed4a673 | 3713 | intel_update_fbc(dev); |
79e53945 | 3714 | |
0b8765c6 JB |
3715 | /* Give the overlay scaler a chance to enable if it's on this pipe */ |
3716 | intel_crtc_dpms_overlay(intel_crtc, true); | |
6b383a7f | 3717 | intel_crtc_update_cursor(crtc, true); |
ef9c3aee | 3718 | |
fa5c73b1 DV |
3719 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3720 | encoder->enable(encoder); | |
0b8765c6 | 3721 | } |
79e53945 | 3722 | |
0b8765c6 JB |
3723 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
3724 | { | |
3725 | struct drm_device *dev = crtc->dev; | |
3726 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3727 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3728 | struct intel_encoder *encoder; |
0b8765c6 JB |
3729 | int pipe = intel_crtc->pipe; |
3730 | int plane = intel_crtc->plane; | |
24a1f16d | 3731 | u32 pctl; |
b690e96c | 3732 | |
ef9c3aee | 3733 | |
f7abfe8b CW |
3734 | if (!intel_crtc->active) |
3735 | return; | |
3736 | ||
ea9d758d DV |
3737 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3738 | encoder->disable(encoder); | |
3739 | ||
0b8765c6 | 3740 | /* Give the overlay scaler a chance to disable if it's on this pipe */ |
e6c3a2a6 CW |
3741 | intel_crtc_wait_for_pending_flips(crtc); |
3742 | drm_vblank_off(dev, pipe); | |
0b8765c6 | 3743 | intel_crtc_dpms_overlay(intel_crtc, false); |
6b383a7f | 3744 | intel_crtc_update_cursor(crtc, false); |
0b8765c6 | 3745 | |
973d04f9 CW |
3746 | if (dev_priv->cfb_plane == plane) |
3747 | intel_disable_fbc(dev); | |
79e53945 | 3748 | |
b24e7179 | 3749 | intel_disable_plane(dev_priv, plane, pipe); |
b24e7179 | 3750 | intel_disable_pipe(dev_priv, pipe); |
24a1f16d MK |
3751 | |
3752 | /* Disable pannel fitter if it is on this pipe. */ | |
3753 | pctl = I915_READ(PFIT_CONTROL); | |
3754 | if ((pctl & PFIT_ENABLE) && | |
3755 | ((pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT) == pipe) | |
3756 | I915_WRITE(PFIT_CONTROL, 0); | |
3757 | ||
63d7bbe9 | 3758 | intel_disable_pll(dev_priv, pipe); |
0b8765c6 | 3759 | |
f7abfe8b | 3760 | intel_crtc->active = false; |
6b383a7f CW |
3761 | intel_update_fbc(dev); |
3762 | intel_update_watermarks(dev); | |
0b8765c6 JB |
3763 | } |
3764 | ||
ee7b9f93 JB |
3765 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
3766 | { | |
3767 | } | |
3768 | ||
976f8a20 DV |
3769 | static void intel_crtc_update_sarea(struct drm_crtc *crtc, |
3770 | bool enabled) | |
2c07245f ZW |
3771 | { |
3772 | struct drm_device *dev = crtc->dev; | |
3773 | struct drm_i915_master_private *master_priv; | |
3774 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3775 | int pipe = intel_crtc->pipe; | |
79e53945 JB |
3776 | |
3777 | if (!dev->primary->master) | |
3778 | return; | |
3779 | ||
3780 | master_priv = dev->primary->master->driver_priv; | |
3781 | if (!master_priv->sarea_priv) | |
3782 | return; | |
3783 | ||
79e53945 JB |
3784 | switch (pipe) { |
3785 | case 0: | |
3786 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; | |
3787 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; | |
3788 | break; | |
3789 | case 1: | |
3790 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; | |
3791 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; | |
3792 | break; | |
3793 | default: | |
9db4a9c7 | 3794 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
79e53945 JB |
3795 | break; |
3796 | } | |
79e53945 JB |
3797 | } |
3798 | ||
976f8a20 DV |
3799 | /** |
3800 | * Sets the power management mode of the pipe and plane. | |
3801 | */ | |
3802 | void intel_crtc_update_dpms(struct drm_crtc *crtc) | |
3803 | { | |
3804 | struct drm_device *dev = crtc->dev; | |
3805 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3806 | struct intel_encoder *intel_encoder; | |
3807 | bool enable = false; | |
3808 | ||
3809 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) | |
3810 | enable |= intel_encoder->connectors_active; | |
3811 | ||
3812 | if (enable) | |
3813 | dev_priv->display.crtc_enable(crtc); | |
3814 | else | |
3815 | dev_priv->display.crtc_disable(crtc); | |
3816 | ||
3817 | intel_crtc_update_sarea(crtc, enable); | |
3818 | } | |
3819 | ||
cdd59983 CW |
3820 | static void intel_crtc_disable(struct drm_crtc *crtc) |
3821 | { | |
cdd59983 | 3822 | struct drm_device *dev = crtc->dev; |
976f8a20 | 3823 | struct drm_connector *connector; |
ee7b9f93 | 3824 | struct drm_i915_private *dev_priv = dev->dev_private; |
7b9f35a6 | 3825 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cdd59983 | 3826 | |
976f8a20 DV |
3827 | /* crtc should still be enabled when we disable it. */ |
3828 | WARN_ON(!crtc->enabled); | |
3829 | ||
7b9f35a6 | 3830 | intel_crtc->eld_vld = false; |
976f8a20 DV |
3831 | dev_priv->display.crtc_disable(crtc); |
3832 | intel_crtc_update_sarea(crtc, false); | |
ee7b9f93 JB |
3833 | dev_priv->display.off(crtc); |
3834 | ||
931872fc CW |
3835 | assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); |
3836 | assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); | |
cdd59983 CW |
3837 | |
3838 | if (crtc->fb) { | |
3839 | mutex_lock(&dev->struct_mutex); | |
1690e1eb | 3840 | intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); |
cdd59983 | 3841 | mutex_unlock(&dev->struct_mutex); |
976f8a20 DV |
3842 | crtc->fb = NULL; |
3843 | } | |
3844 | ||
3845 | /* Update computed state. */ | |
3846 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
3847 | if (!connector->encoder || !connector->encoder->crtc) | |
3848 | continue; | |
3849 | ||
3850 | if (connector->encoder->crtc != crtc) | |
3851 | continue; | |
3852 | ||
3853 | connector->dpms = DRM_MODE_DPMS_OFF; | |
3854 | to_intel_encoder(connector->encoder)->connectors_active = false; | |
cdd59983 CW |
3855 | } |
3856 | } | |
3857 | ||
a261b246 | 3858 | void intel_modeset_disable(struct drm_device *dev) |
79e53945 | 3859 | { |
a261b246 DV |
3860 | struct drm_crtc *crtc; |
3861 | ||
3862 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
3863 | if (crtc->enabled) | |
3864 | intel_crtc_disable(crtc); | |
3865 | } | |
79e53945 JB |
3866 | } |
3867 | ||
ea5b213a | 3868 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 3869 | { |
4ef69c7a | 3870 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 3871 | |
ea5b213a CW |
3872 | drm_encoder_cleanup(encoder); |
3873 | kfree(intel_encoder); | |
7e7d76c3 JB |
3874 | } |
3875 | ||
5ab432ef DV |
3876 | /* Simple dpms helper for encodres with just one connector, no cloning and only |
3877 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the | |
3878 | * state of the entire output pipe. */ | |
3879 | void intel_encoder_dpms(struct intel_encoder *encoder, int mode) | |
7e7d76c3 | 3880 | { |
5ab432ef DV |
3881 | if (mode == DRM_MODE_DPMS_ON) { |
3882 | encoder->connectors_active = true; | |
3883 | ||
b2cabb0e | 3884 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef DV |
3885 | } else { |
3886 | encoder->connectors_active = false; | |
3887 | ||
b2cabb0e | 3888 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef | 3889 | } |
79e53945 JB |
3890 | } |
3891 | ||
0a91ca29 DV |
3892 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
3893 | * internal consistency). */ | |
b980514c | 3894 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 3895 | { |
0a91ca29 DV |
3896 | if (connector->get_hw_state(connector)) { |
3897 | struct intel_encoder *encoder = connector->encoder; | |
3898 | struct drm_crtc *crtc; | |
3899 | bool encoder_enabled; | |
3900 | enum pipe pipe; | |
3901 | ||
3902 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
3903 | connector->base.base.id, | |
3904 | drm_get_connector_name(&connector->base)); | |
3905 | ||
3906 | WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, | |
3907 | "wrong connector dpms state\n"); | |
3908 | WARN(connector->base.encoder != &encoder->base, | |
3909 | "active connector not linked to encoder\n"); | |
3910 | WARN(!encoder->connectors_active, | |
3911 | "encoder->connectors_active not set\n"); | |
3912 | ||
3913 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); | |
3914 | WARN(!encoder_enabled, "encoder not enabled\n"); | |
3915 | if (WARN_ON(!encoder->base.crtc)) | |
3916 | return; | |
3917 | ||
3918 | crtc = encoder->base.crtc; | |
3919 | ||
3920 | WARN(!crtc->enabled, "crtc not enabled\n"); | |
3921 | WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); | |
3922 | WARN(pipe != to_intel_crtc(crtc)->pipe, | |
3923 | "encoder active on the wrong pipe\n"); | |
3924 | } | |
79e53945 JB |
3925 | } |
3926 | ||
5ab432ef DV |
3927 | /* Even simpler default implementation, if there's really no special case to |
3928 | * consider. */ | |
3929 | void intel_connector_dpms(struct drm_connector *connector, int mode) | |
79e53945 | 3930 | { |
5ab432ef | 3931 | struct intel_encoder *encoder = intel_attached_encoder(connector); |
d4270e57 | 3932 | |
5ab432ef DV |
3933 | /* All the simple cases only support two dpms states. */ |
3934 | if (mode != DRM_MODE_DPMS_ON) | |
3935 | mode = DRM_MODE_DPMS_OFF; | |
d4270e57 | 3936 | |
5ab432ef DV |
3937 | if (mode == connector->dpms) |
3938 | return; | |
3939 | ||
3940 | connector->dpms = mode; | |
3941 | ||
3942 | /* Only need to change hw state when actually enabled */ | |
3943 | if (encoder->base.crtc) | |
3944 | intel_encoder_dpms(encoder, mode); | |
3945 | else | |
8af6cf88 | 3946 | WARN_ON(encoder->connectors_active != false); |
0a91ca29 | 3947 | |
b980514c | 3948 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
3949 | } |
3950 | ||
f0947c37 DV |
3951 | /* Simple connector->get_hw_state implementation for encoders that support only |
3952 | * one connector and no cloning and hence the encoder state determines the state | |
3953 | * of the connector. */ | |
3954 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 3955 | { |
24929352 | 3956 | enum pipe pipe = 0; |
f0947c37 | 3957 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 3958 | |
f0947c37 | 3959 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
3960 | } |
3961 | ||
b8cecdf5 DV |
3962 | static bool intel_crtc_compute_config(struct drm_crtc *crtc, |
3963 | struct intel_crtc_config *pipe_config) | |
79e53945 | 3964 | { |
2c07245f | 3965 | struct drm_device *dev = crtc->dev; |
b8cecdf5 | 3966 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
89749350 | 3967 | |
bad720ff | 3968 | if (HAS_PCH_SPLIT(dev)) { |
2c07245f | 3969 | /* FDI link clock is fixed at 2.7G */ |
b8cecdf5 DV |
3970 | if (pipe_config->requested_mode.clock * 3 |
3971 | > IRONLAKE_FDI_FREQ * 4) | |
2377b741 | 3972 | return false; |
2c07245f | 3973 | } |
89749350 | 3974 | |
f9bef081 DV |
3975 | /* All interlaced capable intel hw wants timings in frames. Note though |
3976 | * that intel_lvds_mode_fixup does some funny tricks with the crtc | |
3977 | * timings, so we need to be careful not to clobber these.*/ | |
7ae89233 | 3978 | if (!pipe_config->timings_set) |
f9bef081 | 3979 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
89749350 | 3980 | |
44f46b42 CW |
3981 | /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes |
3982 | * with a hsync front porch of 0. | |
3983 | */ | |
3984 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
3985 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) | |
3986 | return false; | |
3987 | ||
5d2d38dd DV |
3988 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10) { |
3989 | pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */ | |
3990 | } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8) { | |
3991 | /* only a 8bpc pipe, with 6bpc dither through the panel fitter | |
3992 | * for lvds. */ | |
3993 | pipe_config->pipe_bpp = 8*3; | |
3994 | } | |
3995 | ||
79e53945 JB |
3996 | return true; |
3997 | } | |
3998 | ||
25eb05fc JB |
3999 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
4000 | { | |
4001 | return 400000; /* FIXME */ | |
4002 | } | |
4003 | ||
e70236a8 JB |
4004 | static int i945_get_display_clock_speed(struct drm_device *dev) |
4005 | { | |
4006 | return 400000; | |
4007 | } | |
79e53945 | 4008 | |
e70236a8 | 4009 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 4010 | { |
e70236a8 JB |
4011 | return 333000; |
4012 | } | |
79e53945 | 4013 | |
e70236a8 JB |
4014 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
4015 | { | |
4016 | return 200000; | |
4017 | } | |
79e53945 | 4018 | |
e70236a8 JB |
4019 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
4020 | { | |
4021 | u16 gcfgc = 0; | |
79e53945 | 4022 | |
e70236a8 JB |
4023 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
4024 | ||
4025 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
4026 | return 133000; | |
4027 | else { | |
4028 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
4029 | case GC_DISPLAY_CLOCK_333_MHZ: | |
4030 | return 333000; | |
4031 | default: | |
4032 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
4033 | return 190000; | |
79e53945 | 4034 | } |
e70236a8 JB |
4035 | } |
4036 | } | |
4037 | ||
4038 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
4039 | { | |
4040 | return 266000; | |
4041 | } | |
4042 | ||
4043 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
4044 | { | |
4045 | u16 hpllcc = 0; | |
4046 | /* Assume that the hardware is in the high speed state. This | |
4047 | * should be the default. | |
4048 | */ | |
4049 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
4050 | case GC_CLOCK_133_200: | |
4051 | case GC_CLOCK_100_200: | |
4052 | return 200000; | |
4053 | case GC_CLOCK_166_250: | |
4054 | return 250000; | |
4055 | case GC_CLOCK_100_133: | |
79e53945 | 4056 | return 133000; |
e70236a8 | 4057 | } |
79e53945 | 4058 | |
e70236a8 JB |
4059 | /* Shouldn't happen */ |
4060 | return 0; | |
4061 | } | |
79e53945 | 4062 | |
e70236a8 JB |
4063 | static int i830_get_display_clock_speed(struct drm_device *dev) |
4064 | { | |
4065 | return 133000; | |
79e53945 JB |
4066 | } |
4067 | ||
2c07245f | 4068 | static void |
e69d0bc1 | 4069 | intel_reduce_ratio(uint32_t *num, uint32_t *den) |
2c07245f ZW |
4070 | { |
4071 | while (*num > 0xffffff || *den > 0xffffff) { | |
4072 | *num >>= 1; | |
4073 | *den >>= 1; | |
4074 | } | |
4075 | } | |
4076 | ||
e69d0bc1 DV |
4077 | void |
4078 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
4079 | int pixel_clock, int link_clock, | |
4080 | struct intel_link_m_n *m_n) | |
2c07245f | 4081 | { |
e69d0bc1 | 4082 | m_n->tu = 64; |
22ed1113 CW |
4083 | m_n->gmch_m = bits_per_pixel * pixel_clock; |
4084 | m_n->gmch_n = link_clock * nlanes * 8; | |
e69d0bc1 | 4085 | intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); |
22ed1113 CW |
4086 | m_n->link_m = pixel_clock; |
4087 | m_n->link_n = link_clock; | |
e69d0bc1 | 4088 | intel_reduce_ratio(&m_n->link_m, &m_n->link_n); |
2c07245f ZW |
4089 | } |
4090 | ||
a7615030 CW |
4091 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
4092 | { | |
72bbe58c KP |
4093 | if (i915_panel_use_ssc >= 0) |
4094 | return i915_panel_use_ssc != 0; | |
4095 | return dev_priv->lvds_use_ssc | |
435793df | 4096 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
4097 | } |
4098 | ||
a0c4da24 JB |
4099 | static int vlv_get_refclk(struct drm_crtc *crtc) |
4100 | { | |
4101 | struct drm_device *dev = crtc->dev; | |
4102 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4103 | int refclk = 27000; /* for DP & HDMI */ | |
4104 | ||
4105 | return 100000; /* only one validated so far */ | |
4106 | ||
4107 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
4108 | refclk = 96000; | |
4109 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
4110 | if (intel_panel_use_ssc(dev_priv)) | |
4111 | refclk = 100000; | |
4112 | else | |
4113 | refclk = 96000; | |
4114 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) { | |
4115 | refclk = 100000; | |
4116 | } | |
4117 | ||
4118 | return refclk; | |
4119 | } | |
4120 | ||
c65d77d8 JB |
4121 | static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) |
4122 | { | |
4123 | struct drm_device *dev = crtc->dev; | |
4124 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4125 | int refclk; | |
4126 | ||
a0c4da24 JB |
4127 | if (IS_VALLEYVIEW(dev)) { |
4128 | refclk = vlv_get_refclk(crtc); | |
4129 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && | |
c65d77d8 JB |
4130 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
4131 | refclk = dev_priv->lvds_ssc_freq * 1000; | |
4132 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", | |
4133 | refclk / 1000); | |
4134 | } else if (!IS_GEN2(dev)) { | |
4135 | refclk = 96000; | |
4136 | } else { | |
4137 | refclk = 48000; | |
4138 | } | |
4139 | ||
4140 | return refclk; | |
4141 | } | |
4142 | ||
f47709a9 | 4143 | static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc *crtc) |
c65d77d8 | 4144 | { |
f47709a9 DV |
4145 | unsigned dotclock = crtc->config.adjusted_mode.clock; |
4146 | struct dpll *clock = &crtc->config.dpll; | |
4147 | ||
c65d77d8 JB |
4148 | /* SDVO TV has fixed PLL values depend on its clock range, |
4149 | this mirrors vbios setting. */ | |
f47709a9 | 4150 | if (dotclock >= 100000 && dotclock < 140500) { |
c65d77d8 JB |
4151 | clock->p1 = 2; |
4152 | clock->p2 = 10; | |
4153 | clock->n = 3; | |
4154 | clock->m1 = 16; | |
4155 | clock->m2 = 8; | |
f47709a9 | 4156 | } else if (dotclock >= 140500 && dotclock <= 200000) { |
c65d77d8 JB |
4157 | clock->p1 = 1; |
4158 | clock->p2 = 10; | |
4159 | clock->n = 6; | |
4160 | clock->m1 = 12; | |
4161 | clock->m2 = 8; | |
4162 | } | |
f47709a9 DV |
4163 | |
4164 | crtc->config.clock_set = true; | |
c65d77d8 JB |
4165 | } |
4166 | ||
f47709a9 | 4167 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
a7516a05 JB |
4168 | intel_clock_t *reduced_clock) |
4169 | { | |
f47709a9 | 4170 | struct drm_device *dev = crtc->base.dev; |
a7516a05 | 4171 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 4172 | int pipe = crtc->pipe; |
a7516a05 | 4173 | u32 fp, fp2 = 0; |
f47709a9 | 4174 | struct dpll *clock = &crtc->config.dpll; |
a7516a05 JB |
4175 | |
4176 | if (IS_PINEVIEW(dev)) { | |
4177 | fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2; | |
4178 | if (reduced_clock) | |
4179 | fp2 = (1 << reduced_clock->n) << 16 | | |
4180 | reduced_clock->m1 << 8 | reduced_clock->m2; | |
4181 | } else { | |
4182 | fp = clock->n << 16 | clock->m1 << 8 | clock->m2; | |
4183 | if (reduced_clock) | |
4184 | fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 | | |
4185 | reduced_clock->m2; | |
4186 | } | |
4187 | ||
4188 | I915_WRITE(FP0(pipe), fp); | |
4189 | ||
f47709a9 DV |
4190 | crtc->lowfreq_avail = false; |
4191 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && | |
a7516a05 JB |
4192 | reduced_clock && i915_powersave) { |
4193 | I915_WRITE(FP1(pipe), fp2); | |
f47709a9 | 4194 | crtc->lowfreq_avail = true; |
a7516a05 JB |
4195 | } else { |
4196 | I915_WRITE(FP1(pipe), fp); | |
4197 | } | |
4198 | } | |
4199 | ||
03afc4a2 DV |
4200 | static void intel_dp_set_m_n(struct intel_crtc *crtc) |
4201 | { | |
4202 | if (crtc->config.has_pch_encoder) | |
4203 | intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); | |
4204 | else | |
4205 | intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); | |
4206 | } | |
4207 | ||
f47709a9 | 4208 | static void vlv_update_pll(struct intel_crtc *crtc) |
a0c4da24 | 4209 | { |
f47709a9 | 4210 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 4211 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 4212 | int pipe = crtc->pipe; |
a0c4da24 JB |
4213 | u32 dpll, mdiv, pdiv; |
4214 | u32 bestn, bestm1, bestm2, bestp1, bestp2; | |
2a8f64ca VP |
4215 | bool is_sdvo; |
4216 | u32 temp; | |
a0c4da24 | 4217 | |
09153000 DV |
4218 | mutex_lock(&dev_priv->dpio_lock); |
4219 | ||
f47709a9 DV |
4220 | is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) || |
4221 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI); | |
a0c4da24 | 4222 | |
2a8f64ca VP |
4223 | dpll = DPLL_VGA_MODE_DIS; |
4224 | dpll |= DPLL_EXT_BUFFER_ENABLE_VLV; | |
4225 | dpll |= DPLL_REFA_CLK_ENABLE_VLV; | |
4226 | dpll |= DPLL_INTEGRATED_CLOCK_VLV; | |
4227 | ||
4228 | I915_WRITE(DPLL(pipe), dpll); | |
4229 | POSTING_READ(DPLL(pipe)); | |
a0c4da24 | 4230 | |
f47709a9 DV |
4231 | bestn = crtc->config.dpll.n; |
4232 | bestm1 = crtc->config.dpll.m1; | |
4233 | bestm2 = crtc->config.dpll.m2; | |
4234 | bestp1 = crtc->config.dpll.p1; | |
4235 | bestp2 = crtc->config.dpll.p2; | |
a0c4da24 | 4236 | |
2a8f64ca VP |
4237 | /* |
4238 | * In Valleyview PLL and program lane counter registers are exposed | |
4239 | * through DPIO interface | |
4240 | */ | |
a0c4da24 JB |
4241 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
4242 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
4243 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
4244 | mdiv |= (1 << DPIO_POST_DIV_SHIFT); | |
4245 | mdiv |= (1 << DPIO_K_SHIFT); | |
4246 | mdiv |= DPIO_ENABLE_CALIBRATION; | |
4247 | intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv); | |
4248 | ||
4249 | intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000); | |
4250 | ||
2a8f64ca | 4251 | pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) | |
a0c4da24 | 4252 | (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) | |
2a8f64ca VP |
4253 | (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) | |
4254 | (5 << DPIO_CLK_BIAS_CTL_SHIFT); | |
a0c4da24 JB |
4255 | intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv); |
4256 | ||
2a8f64ca | 4257 | intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b); |
a0c4da24 JB |
4258 | |
4259 | dpll |= DPLL_VCO_ENABLE; | |
4260 | I915_WRITE(DPLL(pipe), dpll); | |
4261 | POSTING_READ(DPLL(pipe)); | |
4262 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
4263 | DRM_ERROR("DPLL %d failed to lock\n", pipe); | |
4264 | ||
2a8f64ca VP |
4265 | intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620); |
4266 | ||
f47709a9 DV |
4267 | if (crtc->config.has_dp_encoder) |
4268 | intel_dp_set_m_n(crtc); | |
2a8f64ca VP |
4269 | |
4270 | I915_WRITE(DPLL(pipe), dpll); | |
4271 | ||
4272 | /* Wait for the clocks to stabilize. */ | |
4273 | POSTING_READ(DPLL(pipe)); | |
4274 | udelay(150); | |
a0c4da24 | 4275 | |
2a8f64ca VP |
4276 | temp = 0; |
4277 | if (is_sdvo) { | |
6cc5f341 | 4278 | temp = 0; |
f47709a9 DV |
4279 | if (crtc->config.pixel_multiplier > 1) { |
4280 | temp = (crtc->config.pixel_multiplier - 1) | |
6cc5f341 DV |
4281 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
4282 | } | |
a0c4da24 | 4283 | } |
2a8f64ca VP |
4284 | I915_WRITE(DPLL_MD(pipe), temp); |
4285 | POSTING_READ(DPLL_MD(pipe)); | |
a0c4da24 | 4286 | |
2a8f64ca | 4287 | /* Now program lane control registers */ |
f47709a9 DV |
4288 | if(intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) |
4289 | || intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) { | |
2a8f64ca VP |
4290 | temp = 0x1000C4; |
4291 | if(pipe == 1) | |
4292 | temp |= (1 << 21); | |
4293 | intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp); | |
4294 | } | |
f47709a9 DV |
4295 | |
4296 | if(intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) { | |
2a8f64ca VP |
4297 | temp = 0x1000C4; |
4298 | if(pipe == 1) | |
4299 | temp |= (1 << 21); | |
4300 | intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp); | |
4301 | } | |
09153000 DV |
4302 | |
4303 | mutex_unlock(&dev_priv->dpio_lock); | |
a0c4da24 JB |
4304 | } |
4305 | ||
f47709a9 DV |
4306 | static void i9xx_update_pll(struct intel_crtc *crtc, |
4307 | intel_clock_t *reduced_clock, | |
eb1cbe48 DV |
4308 | int num_connectors) |
4309 | { | |
f47709a9 | 4310 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 4311 | struct drm_i915_private *dev_priv = dev->dev_private; |
dafd226c | 4312 | struct intel_encoder *encoder; |
f47709a9 | 4313 | int pipe = crtc->pipe; |
eb1cbe48 DV |
4314 | u32 dpll; |
4315 | bool is_sdvo; | |
f47709a9 | 4316 | struct dpll *clock = &crtc->config.dpll; |
eb1cbe48 | 4317 | |
f47709a9 | 4318 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 4319 | |
f47709a9 DV |
4320 | is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) || |
4321 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
4322 | |
4323 | dpll = DPLL_VGA_MODE_DIS; | |
4324 | ||
f47709a9 | 4325 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
4326 | dpll |= DPLLB_MODE_LVDS; |
4327 | else | |
4328 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 4329 | |
eb1cbe48 | 4330 | if (is_sdvo) { |
f47709a9 | 4331 | if ((crtc->config.pixel_multiplier > 1) && |
6cc5f341 | 4332 | (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) { |
f47709a9 | 4333 | dpll |= (crtc->config.pixel_multiplier - 1) |
6cc5f341 | 4334 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 DV |
4335 | } |
4336 | dpll |= DPLL_DVO_HIGH_SPEED; | |
4337 | } | |
f47709a9 | 4338 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) |
eb1cbe48 DV |
4339 | dpll |= DPLL_DVO_HIGH_SPEED; |
4340 | ||
4341 | /* compute bitmask from p1 value */ | |
4342 | if (IS_PINEVIEW(dev)) | |
4343 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
4344 | else { | |
4345 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
4346 | if (IS_G4X(dev) && reduced_clock) | |
4347 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
4348 | } | |
4349 | switch (clock->p2) { | |
4350 | case 5: | |
4351 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
4352 | break; | |
4353 | case 7: | |
4354 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
4355 | break; | |
4356 | case 10: | |
4357 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
4358 | break; | |
4359 | case 14: | |
4360 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
4361 | break; | |
4362 | } | |
4363 | if (INTEL_INFO(dev)->gen >= 4) | |
4364 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
4365 | ||
f47709a9 | 4366 | if (is_sdvo && intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT)) |
eb1cbe48 | 4367 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
f47709a9 | 4368 | else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT)) |
eb1cbe48 DV |
4369 | /* XXX: just matching BIOS for now */ |
4370 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ | |
4371 | dpll |= 3; | |
f47709a9 | 4372 | else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
4373 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
4374 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
4375 | else | |
4376 | dpll |= PLL_REF_INPUT_DREFCLK; | |
4377 | ||
4378 | dpll |= DPLL_VCO_ENABLE; | |
4379 | I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); | |
4380 | POSTING_READ(DPLL(pipe)); | |
4381 | udelay(150); | |
4382 | ||
f47709a9 | 4383 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
dafd226c DV |
4384 | if (encoder->pre_pll_enable) |
4385 | encoder->pre_pll_enable(encoder); | |
eb1cbe48 | 4386 | |
f47709a9 DV |
4387 | if (crtc->config.has_dp_encoder) |
4388 | intel_dp_set_m_n(crtc); | |
eb1cbe48 DV |
4389 | |
4390 | I915_WRITE(DPLL(pipe), dpll); | |
4391 | ||
4392 | /* Wait for the clocks to stabilize. */ | |
4393 | POSTING_READ(DPLL(pipe)); | |
4394 | udelay(150); | |
4395 | ||
4396 | if (INTEL_INFO(dev)->gen >= 4) { | |
4397 | u32 temp = 0; | |
4398 | if (is_sdvo) { | |
6cc5f341 | 4399 | temp = 0; |
f47709a9 DV |
4400 | if (crtc->config.pixel_multiplier > 1) { |
4401 | temp = (crtc->config.pixel_multiplier - 1) | |
6cc5f341 DV |
4402 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
4403 | } | |
eb1cbe48 DV |
4404 | } |
4405 | I915_WRITE(DPLL_MD(pipe), temp); | |
4406 | } else { | |
4407 | /* The pixel multiplier can only be updated once the | |
4408 | * DPLL is enabled and the clocks are stable. | |
4409 | * | |
4410 | * So write it again. | |
4411 | */ | |
4412 | I915_WRITE(DPLL(pipe), dpll); | |
4413 | } | |
4414 | } | |
4415 | ||
f47709a9 | 4416 | static void i8xx_update_pll(struct intel_crtc *crtc, |
eb1cbe48 | 4417 | struct drm_display_mode *adjusted_mode, |
f47709a9 | 4418 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
4419 | int num_connectors) |
4420 | { | |
f47709a9 | 4421 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 4422 | struct drm_i915_private *dev_priv = dev->dev_private; |
dafd226c | 4423 | struct intel_encoder *encoder; |
f47709a9 | 4424 | int pipe = crtc->pipe; |
eb1cbe48 | 4425 | u32 dpll; |
f47709a9 | 4426 | struct dpll *clock = &crtc->config.dpll; |
eb1cbe48 | 4427 | |
f47709a9 | 4428 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 4429 | |
eb1cbe48 DV |
4430 | dpll = DPLL_VGA_MODE_DIS; |
4431 | ||
f47709a9 | 4432 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
4433 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
4434 | } else { | |
4435 | if (clock->p1 == 2) | |
4436 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
4437 | else | |
4438 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
4439 | if (clock->p2 == 4) | |
4440 | dpll |= PLL_P2_DIVIDE_BY_4; | |
4441 | } | |
4442 | ||
f47709a9 | 4443 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
4444 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
4445 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
4446 | else | |
4447 | dpll |= PLL_REF_INPUT_DREFCLK; | |
4448 | ||
4449 | dpll |= DPLL_VCO_ENABLE; | |
4450 | I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); | |
4451 | POSTING_READ(DPLL(pipe)); | |
4452 | udelay(150); | |
4453 | ||
f47709a9 | 4454 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
dafd226c DV |
4455 | if (encoder->pre_pll_enable) |
4456 | encoder->pre_pll_enable(encoder); | |
eb1cbe48 | 4457 | |
5b5896e4 DV |
4458 | I915_WRITE(DPLL(pipe), dpll); |
4459 | ||
4460 | /* Wait for the clocks to stabilize. */ | |
4461 | POSTING_READ(DPLL(pipe)); | |
4462 | udelay(150); | |
4463 | ||
eb1cbe48 DV |
4464 | /* The pixel multiplier can only be updated once the |
4465 | * DPLL is enabled and the clocks are stable. | |
4466 | * | |
4467 | * So write it again. | |
4468 | */ | |
4469 | I915_WRITE(DPLL(pipe), dpll); | |
4470 | } | |
4471 | ||
b0e77b9c PZ |
4472 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc, |
4473 | struct drm_display_mode *mode, | |
4474 | struct drm_display_mode *adjusted_mode) | |
4475 | { | |
4476 | struct drm_device *dev = intel_crtc->base.dev; | |
4477 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4478 | enum pipe pipe = intel_crtc->pipe; | |
fe2b8f9d | 4479 | enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; |
b0e77b9c PZ |
4480 | uint32_t vsyncshift; |
4481 | ||
4482 | if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { | |
4483 | /* the chip adds 2 halflines automatically */ | |
4484 | adjusted_mode->crtc_vtotal -= 1; | |
4485 | adjusted_mode->crtc_vblank_end -= 1; | |
4486 | vsyncshift = adjusted_mode->crtc_hsync_start | |
4487 | - adjusted_mode->crtc_htotal / 2; | |
4488 | } else { | |
4489 | vsyncshift = 0; | |
4490 | } | |
4491 | ||
4492 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 4493 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 4494 | |
fe2b8f9d | 4495 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
4496 | (adjusted_mode->crtc_hdisplay - 1) | |
4497 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 4498 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
4499 | (adjusted_mode->crtc_hblank_start - 1) | |
4500 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 4501 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
4502 | (adjusted_mode->crtc_hsync_start - 1) | |
4503 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
4504 | ||
fe2b8f9d | 4505 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c PZ |
4506 | (adjusted_mode->crtc_vdisplay - 1) | |
4507 | ((adjusted_mode->crtc_vtotal - 1) << 16)); | |
fe2b8f9d | 4508 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c PZ |
4509 | (adjusted_mode->crtc_vblank_start - 1) | |
4510 | ((adjusted_mode->crtc_vblank_end - 1) << 16)); | |
fe2b8f9d | 4511 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
4512 | (adjusted_mode->crtc_vsync_start - 1) | |
4513 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
4514 | ||
b5e508d4 PZ |
4515 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
4516 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
4517 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
4518 | * bits. */ | |
4519 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
4520 | (pipe == PIPE_B || pipe == PIPE_C)) | |
4521 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
4522 | ||
b0e77b9c PZ |
4523 | /* pipesrc controls the size that is scaled from, which should |
4524 | * always be the user's requested size. | |
4525 | */ | |
4526 | I915_WRITE(PIPESRC(pipe), | |
4527 | ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); | |
4528 | } | |
4529 | ||
84b046f3 DV |
4530 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
4531 | { | |
4532 | struct drm_device *dev = intel_crtc->base.dev; | |
4533 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4534 | uint32_t pipeconf; | |
4535 | ||
4536 | pipeconf = I915_READ(PIPECONF(intel_crtc->pipe)); | |
4537 | ||
4538 | if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) { | |
4539 | /* Enable pixel doubling when the dot clock is > 90% of the (display) | |
4540 | * core speed. | |
4541 | * | |
4542 | * XXX: No double-wide on 915GM pipe B. Is that the only reason for the | |
4543 | * pipe == 0 check? | |
4544 | */ | |
4545 | if (intel_crtc->config.requested_mode.clock > | |
4546 | dev_priv->display.get_display_clock_speed(dev) * 9 / 10) | |
4547 | pipeconf |= PIPECONF_DOUBLE_WIDE; | |
4548 | else | |
4549 | pipeconf &= ~PIPECONF_DOUBLE_WIDE; | |
4550 | } | |
4551 | ||
4552 | /* default to 8bpc */ | |
4553 | pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN); | |
4554 | if (intel_crtc->config.has_dp_encoder) { | |
4555 | if (intel_crtc->config.dither) { | |
4556 | pipeconf |= PIPECONF_6BPC | | |
4557 | PIPECONF_DITHER_EN | | |
4558 | PIPECONF_DITHER_TYPE_SP; | |
4559 | } | |
4560 | } | |
4561 | ||
4562 | if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(&intel_crtc->base, | |
4563 | INTEL_OUTPUT_EDP)) { | |
4564 | if (intel_crtc->config.dither) { | |
4565 | pipeconf |= PIPECONF_6BPC | | |
4566 | PIPECONF_ENABLE | | |
4567 | I965_PIPECONF_ACTIVE; | |
4568 | } | |
4569 | } | |
4570 | ||
4571 | if (HAS_PIPE_CXSR(dev)) { | |
4572 | if (intel_crtc->lowfreq_avail) { | |
4573 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
4574 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
4575 | } else { | |
4576 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
4577 | pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; | |
4578 | } | |
4579 | } | |
4580 | ||
4581 | pipeconf &= ~PIPECONF_INTERLACE_MASK; | |
4582 | if (!IS_GEN2(dev) && | |
4583 | intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) | |
4584 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; | |
4585 | else | |
4586 | pipeconf |= PIPECONF_PROGRESSIVE; | |
4587 | ||
9c8e09b7 VS |
4588 | if (IS_VALLEYVIEW(dev)) { |
4589 | if (intel_crtc->config.limited_color_range) | |
4590 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; | |
4591 | else | |
4592 | pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT; | |
4593 | } | |
4594 | ||
84b046f3 DV |
4595 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
4596 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
4597 | } | |
4598 | ||
f564048e | 4599 | static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
f564048e | 4600 | int x, int y, |
94352cf9 | 4601 | struct drm_framebuffer *fb) |
79e53945 JB |
4602 | { |
4603 | struct drm_device *dev = crtc->dev; | |
4604 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4605 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b8cecdf5 DV |
4606 | struct drm_display_mode *adjusted_mode = |
4607 | &intel_crtc->config.adjusted_mode; | |
4608 | struct drm_display_mode *mode = &intel_crtc->config.requested_mode; | |
79e53945 | 4609 | int pipe = intel_crtc->pipe; |
80824003 | 4610 | int plane = intel_crtc->plane; |
c751ce4f | 4611 | int refclk, num_connectors = 0; |
652c393a | 4612 | intel_clock_t clock, reduced_clock; |
84b046f3 | 4613 | u32 dspcntr; |
eb1cbe48 | 4614 | bool ok, has_reduced_clock = false, is_sdvo = false; |
8b47047b | 4615 | bool is_lvds = false, is_tv = false; |
5eddb70b | 4616 | struct intel_encoder *encoder; |
d4906093 | 4617 | const intel_limit_t *limit; |
5c3b82e2 | 4618 | int ret; |
79e53945 | 4619 | |
6c2b7c12 | 4620 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5eddb70b | 4621 | switch (encoder->type) { |
79e53945 JB |
4622 | case INTEL_OUTPUT_LVDS: |
4623 | is_lvds = true; | |
4624 | break; | |
4625 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 4626 | case INTEL_OUTPUT_HDMI: |
79e53945 | 4627 | is_sdvo = true; |
5eddb70b | 4628 | if (encoder->needs_tv_clock) |
e2f0ba97 | 4629 | is_tv = true; |
79e53945 | 4630 | break; |
79e53945 JB |
4631 | case INTEL_OUTPUT_TVOUT: |
4632 | is_tv = true; | |
4633 | break; | |
79e53945 | 4634 | } |
43565a06 | 4635 | |
c751ce4f | 4636 | num_connectors++; |
79e53945 JB |
4637 | } |
4638 | ||
c65d77d8 | 4639 | refclk = i9xx_get_refclk(crtc, num_connectors); |
79e53945 | 4640 | |
d4906093 ML |
4641 | /* |
4642 | * Returns a set of divisors for the desired target clock with the given | |
4643 | * refclk, or FALSE. The returned values represent the clock equation: | |
4644 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
4645 | */ | |
1b894b59 | 4646 | limit = intel_limit(crtc, refclk); |
cec2f356 SP |
4647 | ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL, |
4648 | &clock); | |
79e53945 JB |
4649 | if (!ok) { |
4650 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
5c3b82e2 | 4651 | return -EINVAL; |
79e53945 JB |
4652 | } |
4653 | ||
cda4b7d3 | 4654 | /* Ensure that the cursor is valid for the new mode before changing... */ |
6b383a7f | 4655 | intel_crtc_update_cursor(crtc, true); |
cda4b7d3 | 4656 | |
ddc9003c | 4657 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
4658 | /* |
4659 | * Ensure we match the reduced clock's P to the target clock. | |
4660 | * If the clocks don't match, we can't switch the display clock | |
4661 | * by using the FP0/FP1. In such case we will disable the LVDS | |
4662 | * downclock feature. | |
4663 | */ | |
ddc9003c | 4664 | has_reduced_clock = limit->find_pll(limit, crtc, |
5eddb70b CW |
4665 | dev_priv->lvds_downclock, |
4666 | refclk, | |
cec2f356 | 4667 | &clock, |
5eddb70b | 4668 | &reduced_clock); |
7026d4ac | 4669 | } |
f47709a9 DV |
4670 | /* Compat-code for transition, will disappear. */ |
4671 | if (!intel_crtc->config.clock_set) { | |
4672 | intel_crtc->config.dpll.n = clock.n; | |
4673 | intel_crtc->config.dpll.m1 = clock.m1; | |
4674 | intel_crtc->config.dpll.m2 = clock.m2; | |
4675 | intel_crtc->config.dpll.p1 = clock.p1; | |
4676 | intel_crtc->config.dpll.p2 = clock.p2; | |
4677 | } | |
7026d4ac | 4678 | |
c65d77d8 | 4679 | if (is_sdvo && is_tv) |
f47709a9 | 4680 | i9xx_adjust_sdvo_tv_clock(intel_crtc); |
7026d4ac | 4681 | |
eb1cbe48 | 4682 | if (IS_GEN2(dev)) |
f47709a9 | 4683 | i8xx_update_pll(intel_crtc, adjusted_mode, |
2a8f64ca VP |
4684 | has_reduced_clock ? &reduced_clock : NULL, |
4685 | num_connectors); | |
a0c4da24 | 4686 | else if (IS_VALLEYVIEW(dev)) |
f47709a9 | 4687 | vlv_update_pll(intel_crtc); |
79e53945 | 4688 | else |
f47709a9 | 4689 | i9xx_update_pll(intel_crtc, |
eb1cbe48 DV |
4690 | has_reduced_clock ? &reduced_clock : NULL, |
4691 | num_connectors); | |
79e53945 | 4692 | |
79e53945 JB |
4693 | /* Set up the display plane register */ |
4694 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
4695 | ||
da6ecc5d JB |
4696 | if (!IS_VALLEYVIEW(dev)) { |
4697 | if (pipe == 0) | |
4698 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; | |
4699 | else | |
4700 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
4701 | } | |
79e53945 | 4702 | |
28c97730 | 4703 | DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); |
79e53945 JB |
4704 | drm_mode_debug_printmodeline(mode); |
4705 | ||
b0e77b9c | 4706 | intel_set_pipe_timings(intel_crtc, mode, adjusted_mode); |
5eddb70b CW |
4707 | |
4708 | /* pipesrc and dspsize control the size that is scaled from, | |
4709 | * which should always be the user's requested size. | |
79e53945 | 4710 | */ |
929c77fb EA |
4711 | I915_WRITE(DSPSIZE(plane), |
4712 | ((mode->vdisplay - 1) << 16) | | |
4713 | (mode->hdisplay - 1)); | |
4714 | I915_WRITE(DSPPOS(plane), 0); | |
2c07245f | 4715 | |
84b046f3 DV |
4716 | i9xx_set_pipeconf(intel_crtc); |
4717 | ||
929c77fb | 4718 | intel_enable_pipe(dev_priv, pipe, false); |
f564048e EA |
4719 | |
4720 | intel_wait_for_vblank(dev, pipe); | |
4721 | ||
f564048e EA |
4722 | I915_WRITE(DSPCNTR(plane), dspcntr); |
4723 | POSTING_READ(DSPCNTR(plane)); | |
4724 | ||
94352cf9 | 4725 | ret = intel_pipe_set_base(crtc, x, y, fb); |
f564048e EA |
4726 | |
4727 | intel_update_watermarks(dev); | |
4728 | ||
f564048e EA |
4729 | return ret; |
4730 | } | |
4731 | ||
0e8ffe1b DV |
4732 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
4733 | struct intel_crtc_config *pipe_config) | |
4734 | { | |
4735 | struct drm_device *dev = crtc->base.dev; | |
4736 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4737 | uint32_t tmp; | |
4738 | ||
4739 | tmp = I915_READ(PIPECONF(crtc->pipe)); | |
4740 | if (!(tmp & PIPECONF_ENABLE)) | |
4741 | return false; | |
4742 | ||
4743 | return true; | |
4744 | } | |
4745 | ||
dde86e2d | 4746 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
4747 | { |
4748 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4749 | struct drm_mode_config *mode_config = &dev->mode_config; | |
13d83a67 | 4750 | struct intel_encoder *encoder; |
74cfd7ac | 4751 | u32 val, final; |
13d83a67 | 4752 | bool has_lvds = false; |
199e5d79 KP |
4753 | bool has_cpu_edp = false; |
4754 | bool has_pch_edp = false; | |
4755 | bool has_panel = false; | |
99eb6a01 KP |
4756 | bool has_ck505 = false; |
4757 | bool can_ssc = false; | |
13d83a67 JB |
4758 | |
4759 | /* We need to take the global config into account */ | |
199e5d79 KP |
4760 | list_for_each_entry(encoder, &mode_config->encoder_list, |
4761 | base.head) { | |
4762 | switch (encoder->type) { | |
4763 | case INTEL_OUTPUT_LVDS: | |
4764 | has_panel = true; | |
4765 | has_lvds = true; | |
4766 | break; | |
4767 | case INTEL_OUTPUT_EDP: | |
4768 | has_panel = true; | |
4769 | if (intel_encoder_is_pch_edp(&encoder->base)) | |
4770 | has_pch_edp = true; | |
4771 | else | |
4772 | has_cpu_edp = true; | |
4773 | break; | |
13d83a67 JB |
4774 | } |
4775 | } | |
4776 | ||
99eb6a01 KP |
4777 | if (HAS_PCH_IBX(dev)) { |
4778 | has_ck505 = dev_priv->display_clock_mode; | |
4779 | can_ssc = has_ck505; | |
4780 | } else { | |
4781 | has_ck505 = false; | |
4782 | can_ssc = true; | |
4783 | } | |
4784 | ||
4785 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n", | |
4786 | has_panel, has_lvds, has_pch_edp, has_cpu_edp, | |
4787 | has_ck505); | |
13d83a67 JB |
4788 | |
4789 | /* Ironlake: try to setup display ref clock before DPLL | |
4790 | * enabling. This is only under driver's control after | |
4791 | * PCH B stepping, previous chipset stepping should be | |
4792 | * ignoring this setting. | |
4793 | */ | |
74cfd7ac CW |
4794 | val = I915_READ(PCH_DREF_CONTROL); |
4795 | ||
4796 | /* As we must carefully and slowly disable/enable each source in turn, | |
4797 | * compute the final state we want first and check if we need to | |
4798 | * make any changes at all. | |
4799 | */ | |
4800 | final = val; | |
4801 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
4802 | if (has_ck505) | |
4803 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
4804 | else | |
4805 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
4806 | ||
4807 | final &= ~DREF_SSC_SOURCE_MASK; | |
4808 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
4809 | final &= ~DREF_SSC1_ENABLE; | |
4810 | ||
4811 | if (has_panel) { | |
4812 | final |= DREF_SSC_SOURCE_ENABLE; | |
4813 | ||
4814 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
4815 | final |= DREF_SSC1_ENABLE; | |
4816 | ||
4817 | if (has_cpu_edp) { | |
4818 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
4819 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
4820 | else | |
4821 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
4822 | } else | |
4823 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
4824 | } else { | |
4825 | final |= DREF_SSC_SOURCE_DISABLE; | |
4826 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
4827 | } | |
4828 | ||
4829 | if (final == val) | |
4830 | return; | |
4831 | ||
13d83a67 | 4832 | /* Always enable nonspread source */ |
74cfd7ac | 4833 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 4834 | |
99eb6a01 | 4835 | if (has_ck505) |
74cfd7ac | 4836 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 4837 | else |
74cfd7ac | 4838 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 4839 | |
199e5d79 | 4840 | if (has_panel) { |
74cfd7ac CW |
4841 | val &= ~DREF_SSC_SOURCE_MASK; |
4842 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 4843 | |
199e5d79 | 4844 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 4845 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 4846 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 4847 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 4848 | } else |
74cfd7ac | 4849 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
4850 | |
4851 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 4852 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
4853 | POSTING_READ(PCH_DREF_CONTROL); |
4854 | udelay(200); | |
4855 | ||
74cfd7ac | 4856 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
4857 | |
4858 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 4859 | if (has_cpu_edp) { |
99eb6a01 | 4860 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 4861 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 4862 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
199e5d79 | 4863 | } |
13d83a67 | 4864 | else |
74cfd7ac | 4865 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 4866 | } else |
74cfd7ac | 4867 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 4868 | |
74cfd7ac | 4869 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
4870 | POSTING_READ(PCH_DREF_CONTROL); |
4871 | udelay(200); | |
4872 | } else { | |
4873 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
4874 | ||
74cfd7ac | 4875 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
4876 | |
4877 | /* Turn off CPU output */ | |
74cfd7ac | 4878 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 4879 | |
74cfd7ac | 4880 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
4881 | POSTING_READ(PCH_DREF_CONTROL); |
4882 | udelay(200); | |
4883 | ||
4884 | /* Turn off the SSC source */ | |
74cfd7ac CW |
4885 | val &= ~DREF_SSC_SOURCE_MASK; |
4886 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
4887 | |
4888 | /* Turn off SSC1 */ | |
74cfd7ac | 4889 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 4890 | |
74cfd7ac | 4891 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
4892 | POSTING_READ(PCH_DREF_CONTROL); |
4893 | udelay(200); | |
4894 | } | |
74cfd7ac CW |
4895 | |
4896 | BUG_ON(val != final); | |
13d83a67 JB |
4897 | } |
4898 | ||
dde86e2d PZ |
4899 | /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */ |
4900 | static void lpt_init_pch_refclk(struct drm_device *dev) | |
4901 | { | |
4902 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4903 | struct drm_mode_config *mode_config = &dev->mode_config; | |
4904 | struct intel_encoder *encoder; | |
4905 | bool has_vga = false; | |
4906 | bool is_sdv = false; | |
4907 | u32 tmp; | |
4908 | ||
4909 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { | |
4910 | switch (encoder->type) { | |
4911 | case INTEL_OUTPUT_ANALOG: | |
4912 | has_vga = true; | |
4913 | break; | |
4914 | } | |
4915 | } | |
4916 | ||
4917 | if (!has_vga) | |
4918 | return; | |
4919 | ||
c00db246 DV |
4920 | mutex_lock(&dev_priv->dpio_lock); |
4921 | ||
dde86e2d PZ |
4922 | /* XXX: Rip out SDV support once Haswell ships for real. */ |
4923 | if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00) | |
4924 | is_sdv = true; | |
4925 | ||
4926 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
4927 | tmp &= ~SBI_SSCCTL_DISABLE; | |
4928 | tmp |= SBI_SSCCTL_PATHALT; | |
4929 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
4930 | ||
4931 | udelay(24); | |
4932 | ||
4933 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
4934 | tmp &= ~SBI_SSCCTL_PATHALT; | |
4935 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
4936 | ||
4937 | if (!is_sdv) { | |
4938 | tmp = I915_READ(SOUTH_CHICKEN2); | |
4939 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
4940 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
4941 | ||
4942 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & | |
4943 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
4944 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
4945 | ||
4946 | tmp = I915_READ(SOUTH_CHICKEN2); | |
4947 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
4948 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
4949 | ||
4950 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & | |
4951 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, | |
4952 | 100)) | |
4953 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
4954 | } | |
4955 | ||
4956 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
4957 | tmp &= ~(0xFF << 24); | |
4958 | tmp |= (0x12 << 24); | |
4959 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
4960 | ||
dde86e2d PZ |
4961 | if (is_sdv) { |
4962 | tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY); | |
4963 | tmp |= 0x7FFF; | |
4964 | intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY); | |
4965 | } | |
4966 | ||
4967 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); | |
4968 | tmp |= (1 << 11); | |
4969 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
4970 | ||
4971 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
4972 | tmp |= (1 << 11); | |
4973 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
4974 | ||
4975 | if (is_sdv) { | |
4976 | tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY); | |
4977 | tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16); | |
4978 | intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY); | |
4979 | ||
4980 | tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY); | |
4981 | tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16); | |
4982 | intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY); | |
4983 | ||
4984 | tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY); | |
4985 | tmp |= (0x3F << 8); | |
4986 | intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY); | |
4987 | ||
4988 | tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY); | |
4989 | tmp |= (0x3F << 8); | |
4990 | intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY); | |
4991 | } | |
4992 | ||
4993 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); | |
4994 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
4995 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
4996 | ||
4997 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
4998 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
4999 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
5000 | ||
5001 | if (!is_sdv) { | |
5002 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); | |
5003 | tmp &= ~(7 << 13); | |
5004 | tmp |= (5 << 13); | |
5005 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
5006 | ||
5007 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); | |
5008 | tmp &= ~(7 << 13); | |
5009 | tmp |= (5 << 13); | |
5010 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
5011 | } | |
5012 | ||
5013 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
5014 | tmp &= ~0xFF; | |
5015 | tmp |= 0x1C; | |
5016 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
5017 | ||
5018 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
5019 | tmp &= ~0xFF; | |
5020 | tmp |= 0x1C; | |
5021 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
5022 | ||
5023 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
5024 | tmp &= ~(0xFF << 16); | |
5025 | tmp |= (0x1C << 16); | |
5026 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
5027 | ||
5028 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
5029 | tmp &= ~(0xFF << 16); | |
5030 | tmp |= (0x1C << 16); | |
5031 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
5032 | ||
5033 | if (!is_sdv) { | |
5034 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); | |
5035 | tmp |= (1 << 27); | |
5036 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
5037 | ||
5038 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); | |
5039 | tmp |= (1 << 27); | |
5040 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
5041 | ||
5042 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); | |
5043 | tmp &= ~(0xF << 28); | |
5044 | tmp |= (4 << 28); | |
5045 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
5046 | ||
5047 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); | |
5048 | tmp &= ~(0xF << 28); | |
5049 | tmp |= (4 << 28); | |
5050 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
5051 | } | |
5052 | ||
5053 | /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */ | |
5054 | tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK); | |
5055 | tmp |= SBI_DBUFF0_ENABLE; | |
5056 | intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK); | |
c00db246 DV |
5057 | |
5058 | mutex_unlock(&dev_priv->dpio_lock); | |
dde86e2d PZ |
5059 | } |
5060 | ||
5061 | /* | |
5062 | * Initialize reference clocks when the driver loads | |
5063 | */ | |
5064 | void intel_init_pch_refclk(struct drm_device *dev) | |
5065 | { | |
5066 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
5067 | ironlake_init_pch_refclk(dev); | |
5068 | else if (HAS_PCH_LPT(dev)) | |
5069 | lpt_init_pch_refclk(dev); | |
5070 | } | |
5071 | ||
d9d444cb JB |
5072 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
5073 | { | |
5074 | struct drm_device *dev = crtc->dev; | |
5075 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5076 | struct intel_encoder *encoder; | |
d9d444cb JB |
5077 | struct intel_encoder *edp_encoder = NULL; |
5078 | int num_connectors = 0; | |
5079 | bool is_lvds = false; | |
5080 | ||
6c2b7c12 | 5081 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
d9d444cb JB |
5082 | switch (encoder->type) { |
5083 | case INTEL_OUTPUT_LVDS: | |
5084 | is_lvds = true; | |
5085 | break; | |
5086 | case INTEL_OUTPUT_EDP: | |
5087 | edp_encoder = encoder; | |
5088 | break; | |
5089 | } | |
5090 | num_connectors++; | |
5091 | } | |
5092 | ||
5093 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
5094 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", | |
5095 | dev_priv->lvds_ssc_freq); | |
5096 | return dev_priv->lvds_ssc_freq * 1000; | |
5097 | } | |
5098 | ||
5099 | return 120000; | |
5100 | } | |
5101 | ||
c8203565 | 5102 | static void ironlake_set_pipeconf(struct drm_crtc *crtc, |
f564048e | 5103 | struct drm_display_mode *adjusted_mode, |
c8203565 | 5104 | bool dither) |
79e53945 | 5105 | { |
c8203565 | 5106 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
5107 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5108 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
5109 | uint32_t val; |
5110 | ||
5111 | val = I915_READ(PIPECONF(pipe)); | |
5112 | ||
dfd07d72 | 5113 | val &= ~PIPECONF_BPC_MASK; |
965e0c48 | 5114 | switch (intel_crtc->config.pipe_bpp) { |
c8203565 | 5115 | case 18: |
dfd07d72 | 5116 | val |= PIPECONF_6BPC; |
c8203565 PZ |
5117 | break; |
5118 | case 24: | |
dfd07d72 | 5119 | val |= PIPECONF_8BPC; |
c8203565 PZ |
5120 | break; |
5121 | case 30: | |
dfd07d72 | 5122 | val |= PIPECONF_10BPC; |
c8203565 PZ |
5123 | break; |
5124 | case 36: | |
dfd07d72 | 5125 | val |= PIPECONF_12BPC; |
c8203565 PZ |
5126 | break; |
5127 | default: | |
cc769b62 PZ |
5128 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
5129 | BUG(); | |
c8203565 PZ |
5130 | } |
5131 | ||
5132 | val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK); | |
5133 | if (dither) | |
5134 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); | |
5135 | ||
5136 | val &= ~PIPECONF_INTERLACE_MASK; | |
5137 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
5138 | val |= PIPECONF_INTERLACED_ILK; | |
5139 | else | |
5140 | val |= PIPECONF_PROGRESSIVE; | |
5141 | ||
50f3b016 | 5142 | if (intel_crtc->config.limited_color_range) |
3685a8f3 VS |
5143 | val |= PIPECONF_COLOR_RANGE_SELECT; |
5144 | else | |
5145 | val &= ~PIPECONF_COLOR_RANGE_SELECT; | |
5146 | ||
c8203565 PZ |
5147 | I915_WRITE(PIPECONF(pipe), val); |
5148 | POSTING_READ(PIPECONF(pipe)); | |
5149 | } | |
5150 | ||
86d3efce VS |
5151 | /* |
5152 | * Set up the pipe CSC unit. | |
5153 | * | |
5154 | * Currently only full range RGB to limited range RGB conversion | |
5155 | * is supported, but eventually this should handle various | |
5156 | * RGB<->YCbCr scenarios as well. | |
5157 | */ | |
50f3b016 | 5158 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
5159 | { |
5160 | struct drm_device *dev = crtc->dev; | |
5161 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5162 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5163 | int pipe = intel_crtc->pipe; | |
5164 | uint16_t coeff = 0x7800; /* 1.0 */ | |
5165 | ||
5166 | /* | |
5167 | * TODO: Check what kind of values actually come out of the pipe | |
5168 | * with these coeff/postoff values and adjust to get the best | |
5169 | * accuracy. Perhaps we even need to take the bpc value into | |
5170 | * consideration. | |
5171 | */ | |
5172 | ||
50f3b016 | 5173 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
5174 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
5175 | ||
5176 | /* | |
5177 | * GY/GU and RY/RU should be the other way around according | |
5178 | * to BSpec, but reality doesn't agree. Just set them up in | |
5179 | * a way that results in the correct picture. | |
5180 | */ | |
5181 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
5182 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
5183 | ||
5184 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
5185 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
5186 | ||
5187 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
5188 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
5189 | ||
5190 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
5191 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
5192 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
5193 | ||
5194 | if (INTEL_INFO(dev)->gen > 6) { | |
5195 | uint16_t postoff = 0; | |
5196 | ||
50f3b016 | 5197 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
5198 | postoff = (16 * (1 << 13) / 255) & 0x1fff; |
5199 | ||
5200 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
5201 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
5202 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
5203 | ||
5204 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
5205 | } else { | |
5206 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
5207 | ||
50f3b016 | 5208 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
5209 | mode |= CSC_BLACK_SCREEN_OFFSET; |
5210 | ||
5211 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
5212 | } | |
5213 | } | |
5214 | ||
ee2b0b38 PZ |
5215 | static void haswell_set_pipeconf(struct drm_crtc *crtc, |
5216 | struct drm_display_mode *adjusted_mode, | |
5217 | bool dither) | |
5218 | { | |
5219 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
5220 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
702e7a56 | 5221 | enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; |
ee2b0b38 PZ |
5222 | uint32_t val; |
5223 | ||
702e7a56 | 5224 | val = I915_READ(PIPECONF(cpu_transcoder)); |
ee2b0b38 PZ |
5225 | |
5226 | val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK); | |
5227 | if (dither) | |
5228 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); | |
5229 | ||
5230 | val &= ~PIPECONF_INTERLACE_MASK_HSW; | |
5231 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
5232 | val |= PIPECONF_INTERLACED_ILK; | |
5233 | else | |
5234 | val |= PIPECONF_PROGRESSIVE; | |
5235 | ||
702e7a56 PZ |
5236 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
5237 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
ee2b0b38 PZ |
5238 | } |
5239 | ||
6591c6e4 PZ |
5240 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
5241 | struct drm_display_mode *adjusted_mode, | |
5242 | intel_clock_t *clock, | |
5243 | bool *has_reduced_clock, | |
5244 | intel_clock_t *reduced_clock) | |
5245 | { | |
5246 | struct drm_device *dev = crtc->dev; | |
5247 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5248 | struct intel_encoder *intel_encoder; | |
5249 | int refclk; | |
d4906093 | 5250 | const intel_limit_t *limit; |
6591c6e4 | 5251 | bool ret, is_sdvo = false, is_tv = false, is_lvds = false; |
79e53945 | 5252 | |
6591c6e4 PZ |
5253 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
5254 | switch (intel_encoder->type) { | |
79e53945 JB |
5255 | case INTEL_OUTPUT_LVDS: |
5256 | is_lvds = true; | |
5257 | break; | |
5258 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 5259 | case INTEL_OUTPUT_HDMI: |
79e53945 | 5260 | is_sdvo = true; |
6591c6e4 | 5261 | if (intel_encoder->needs_tv_clock) |
e2f0ba97 | 5262 | is_tv = true; |
79e53945 | 5263 | break; |
79e53945 JB |
5264 | case INTEL_OUTPUT_TVOUT: |
5265 | is_tv = true; | |
5266 | break; | |
79e53945 JB |
5267 | } |
5268 | } | |
5269 | ||
d9d444cb | 5270 | refclk = ironlake_get_refclk(crtc); |
79e53945 | 5271 | |
d4906093 ML |
5272 | /* |
5273 | * Returns a set of divisors for the desired target clock with the given | |
5274 | * refclk, or FALSE. The returned values represent the clock equation: | |
5275 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
5276 | */ | |
1b894b59 | 5277 | limit = intel_limit(crtc, refclk); |
6591c6e4 PZ |
5278 | ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL, |
5279 | clock); | |
5280 | if (!ret) | |
5281 | return false; | |
cda4b7d3 | 5282 | |
ddc9003c | 5283 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
5284 | /* |
5285 | * Ensure we match the reduced clock's P to the target clock. | |
5286 | * If the clocks don't match, we can't switch the display clock | |
5287 | * by using the FP0/FP1. In such case we will disable the LVDS | |
5288 | * downclock feature. | |
5289 | */ | |
6591c6e4 PZ |
5290 | *has_reduced_clock = limit->find_pll(limit, crtc, |
5291 | dev_priv->lvds_downclock, | |
5292 | refclk, | |
5293 | clock, | |
5294 | reduced_clock); | |
652c393a | 5295 | } |
61e9653f DV |
5296 | |
5297 | if (is_sdvo && is_tv) | |
f47709a9 | 5298 | i9xx_adjust_sdvo_tv_clock(to_intel_crtc(crtc)); |
6591c6e4 PZ |
5299 | |
5300 | return true; | |
5301 | } | |
5302 | ||
01a415fd DV |
5303 | static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev) |
5304 | { | |
5305 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5306 | uint32_t temp; | |
5307 | ||
5308 | temp = I915_READ(SOUTH_CHICKEN1); | |
5309 | if (temp & FDI_BC_BIFURCATION_SELECT) | |
5310 | return; | |
5311 | ||
5312 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
5313 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
5314 | ||
5315 | temp |= FDI_BC_BIFURCATION_SELECT; | |
5316 | DRM_DEBUG_KMS("enabling fdi C rx\n"); | |
5317 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
5318 | POSTING_READ(SOUTH_CHICKEN1); | |
5319 | } | |
5320 | ||
5321 | static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc) | |
5322 | { | |
5323 | struct drm_device *dev = intel_crtc->base.dev; | |
5324 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5325 | struct intel_crtc *pipe_B_crtc = | |
5326 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
5327 | ||
5328 | DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n", | |
5329 | intel_crtc->pipe, intel_crtc->fdi_lanes); | |
5330 | if (intel_crtc->fdi_lanes > 4) { | |
5331 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n", | |
5332 | intel_crtc->pipe, intel_crtc->fdi_lanes); | |
5333 | /* Clamp lanes to avoid programming the hw with bogus values. */ | |
5334 | intel_crtc->fdi_lanes = 4; | |
5335 | ||
5336 | return false; | |
5337 | } | |
5338 | ||
7eb552ae | 5339 | if (INTEL_INFO(dev)->num_pipes == 2) |
01a415fd DV |
5340 | return true; |
5341 | ||
5342 | switch (intel_crtc->pipe) { | |
5343 | case PIPE_A: | |
5344 | return true; | |
5345 | case PIPE_B: | |
5346 | if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled && | |
5347 | intel_crtc->fdi_lanes > 2) { | |
5348 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n", | |
5349 | intel_crtc->pipe, intel_crtc->fdi_lanes); | |
5350 | /* Clamp lanes to avoid programming the hw with bogus values. */ | |
5351 | intel_crtc->fdi_lanes = 2; | |
5352 | ||
5353 | return false; | |
5354 | } | |
5355 | ||
5356 | if (intel_crtc->fdi_lanes > 2) | |
5357 | WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT); | |
5358 | else | |
5359 | cpt_enable_fdi_bc_bifurcation(dev); | |
5360 | ||
5361 | return true; | |
5362 | case PIPE_C: | |
5363 | if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) { | |
5364 | if (intel_crtc->fdi_lanes > 2) { | |
5365 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n", | |
5366 | intel_crtc->pipe, intel_crtc->fdi_lanes); | |
5367 | /* Clamp lanes to avoid programming the hw with bogus values. */ | |
5368 | intel_crtc->fdi_lanes = 2; | |
5369 | ||
5370 | return false; | |
5371 | } | |
5372 | } else { | |
5373 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); | |
5374 | return false; | |
5375 | } | |
5376 | ||
5377 | cpt_enable_fdi_bc_bifurcation(dev); | |
5378 | ||
5379 | return true; | |
5380 | default: | |
5381 | BUG(); | |
5382 | } | |
5383 | } | |
5384 | ||
d4b1931c PZ |
5385 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
5386 | { | |
5387 | /* | |
5388 | * Account for spread spectrum to avoid | |
5389 | * oversubscribing the link. Max center spread | |
5390 | * is 2.5%; use 5% for safety's sake. | |
5391 | */ | |
5392 | u32 bps = target_clock * bpp * 21 / 20; | |
5393 | return bps / (link_bw * 8) + 1; | |
5394 | } | |
5395 | ||
6cf86a5e DV |
5396 | void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
5397 | struct intel_link_m_n *m_n) | |
79e53945 | 5398 | { |
6cf86a5e DV |
5399 | struct drm_device *dev = crtc->base.dev; |
5400 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5401 | int pipe = crtc->pipe; | |
5402 | ||
5403 | I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
5404 | I915_WRITE(TRANSDATA_N1(pipe), m_n->gmch_n); | |
5405 | I915_WRITE(TRANSDPLINK_M1(pipe), m_n->link_m); | |
5406 | I915_WRITE(TRANSDPLINK_N1(pipe), m_n->link_n); | |
5407 | } | |
5408 | ||
5409 | void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
5410 | struct intel_link_m_n *m_n) | |
5411 | { | |
5412 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 5413 | struct drm_i915_private *dev_priv = dev->dev_private; |
6cf86a5e DV |
5414 | int pipe = crtc->pipe; |
5415 | enum transcoder transcoder = crtc->cpu_transcoder; | |
5416 | ||
5417 | if (INTEL_INFO(dev)->gen >= 5) { | |
5418 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
5419 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
5420 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
5421 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
5422 | } else { | |
5423 | I915_WRITE(PIPE_GMCH_DATA_M(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
5424 | I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n->gmch_n); | |
5425 | I915_WRITE(PIPE_DP_LINK_M(pipe), m_n->link_m); | |
5426 | I915_WRITE(PIPE_DP_LINK_N(pipe), m_n->link_n); | |
5427 | } | |
5428 | } | |
5429 | ||
5430 | static void ironlake_fdi_set_m_n(struct drm_crtc *crtc) | |
5431 | { | |
5432 | struct drm_device *dev = crtc->dev; | |
79e53945 | 5433 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6cc5f341 DV |
5434 | struct drm_display_mode *adjusted_mode = |
5435 | &intel_crtc->config.adjusted_mode; | |
e69d0bc1 | 5436 | struct intel_link_m_n m_n = {0}; |
6cc5f341 | 5437 | int target_clock, lane, link_bw; |
61e9653f | 5438 | |
6cf86a5e DV |
5439 | /* FDI is a binary signal running at ~2.7GHz, encoding |
5440 | * each output octet as 10 bits. The actual frequency | |
5441 | * is stored as a divider into a 100MHz clock, and the | |
5442 | * mode pixel clock is stored in units of 1KHz. | |
5443 | * Hence the bw of each lane in terms of the mode signal | |
5444 | * is: | |
5445 | */ | |
5446 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
58a27471 | 5447 | |
df92b1e6 DV |
5448 | if (intel_crtc->config.pixel_target_clock) |
5449 | target_clock = intel_crtc->config.pixel_target_clock; | |
94bf2ced DV |
5450 | else |
5451 | target_clock = adjusted_mode->clock; | |
5452 | ||
6cf86a5e DV |
5453 | lane = ironlake_get_lanes_required(target_clock, link_bw, |
5454 | intel_crtc->config.pipe_bpp); | |
2c07245f | 5455 | |
8febb297 EA |
5456 | intel_crtc->fdi_lanes = lane; |
5457 | ||
6cc5f341 DV |
5458 | if (intel_crtc->config.pixel_multiplier > 1) |
5459 | link_bw *= intel_crtc->config.pixel_multiplier; | |
965e0c48 DV |
5460 | intel_link_compute_m_n(intel_crtc->config.pipe_bpp, lane, target_clock, |
5461 | link_bw, &m_n); | |
8febb297 | 5462 | |
6cf86a5e | 5463 | intel_cpu_transcoder_set_m_n(intel_crtc, &m_n); |
f48d8f23 PZ |
5464 | } |
5465 | ||
de13a2e3 | 5466 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
9a7c7890 DV |
5467 | intel_clock_t *clock, u32 *fp, |
5468 | intel_clock_t *reduced_clock, u32 *fp2) | |
79e53945 | 5469 | { |
de13a2e3 | 5470 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
5471 | struct drm_device *dev = crtc->dev; |
5472 | struct drm_i915_private *dev_priv = dev->dev_private; | |
de13a2e3 PZ |
5473 | struct intel_encoder *intel_encoder; |
5474 | uint32_t dpll; | |
6cc5f341 | 5475 | int factor, num_connectors = 0; |
de13a2e3 | 5476 | bool is_lvds = false, is_sdvo = false, is_tv = false; |
79e53945 | 5477 | |
de13a2e3 PZ |
5478 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
5479 | switch (intel_encoder->type) { | |
79e53945 JB |
5480 | case INTEL_OUTPUT_LVDS: |
5481 | is_lvds = true; | |
5482 | break; | |
5483 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 5484 | case INTEL_OUTPUT_HDMI: |
79e53945 | 5485 | is_sdvo = true; |
de13a2e3 | 5486 | if (intel_encoder->needs_tv_clock) |
e2f0ba97 | 5487 | is_tv = true; |
79e53945 | 5488 | break; |
79e53945 JB |
5489 | case INTEL_OUTPUT_TVOUT: |
5490 | is_tv = true; | |
5491 | break; | |
79e53945 | 5492 | } |
43565a06 | 5493 | |
c751ce4f | 5494 | num_connectors++; |
79e53945 | 5495 | } |
79e53945 | 5496 | |
c1858123 | 5497 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
5498 | factor = 21; |
5499 | if (is_lvds) { | |
5500 | if ((intel_panel_use_ssc(dev_priv) && | |
5501 | dev_priv->lvds_ssc_freq == 100) || | |
f0b44056 | 5502 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 EA |
5503 | factor = 25; |
5504 | } else if (is_sdvo && is_tv) | |
5505 | factor = 20; | |
c1858123 | 5506 | |
de13a2e3 | 5507 | if (clock->m < factor * clock->n) |
7d0ac5b7 | 5508 | *fp |= FP_CB_TUNE; |
2c07245f | 5509 | |
9a7c7890 DV |
5510 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
5511 | *fp2 |= FP_CB_TUNE; | |
5512 | ||
5eddb70b | 5513 | dpll = 0; |
2c07245f | 5514 | |
a07d6787 EA |
5515 | if (is_lvds) |
5516 | dpll |= DPLLB_MODE_LVDS; | |
5517 | else | |
5518 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
5519 | if (is_sdvo) { | |
6cc5f341 DV |
5520 | if (intel_crtc->config.pixel_multiplier > 1) { |
5521 | dpll |= (intel_crtc->config.pixel_multiplier - 1) | |
5522 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; | |
79e53945 | 5523 | } |
a07d6787 EA |
5524 | dpll |= DPLL_DVO_HIGH_SPEED; |
5525 | } | |
8b47047b DV |
5526 | if (intel_crtc->config.has_dp_encoder && |
5527 | intel_crtc->config.has_pch_encoder) | |
a07d6787 | 5528 | dpll |= DPLL_DVO_HIGH_SPEED; |
79e53945 | 5529 | |
a07d6787 | 5530 | /* compute bitmask from p1 value */ |
de13a2e3 | 5531 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 5532 | /* also FPA1 */ |
de13a2e3 | 5533 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 5534 | |
de13a2e3 | 5535 | switch (clock->p2) { |
a07d6787 EA |
5536 | case 5: |
5537 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
5538 | break; | |
5539 | case 7: | |
5540 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
5541 | break; | |
5542 | case 10: | |
5543 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
5544 | break; | |
5545 | case 14: | |
5546 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
5547 | break; | |
79e53945 JB |
5548 | } |
5549 | ||
43565a06 KH |
5550 | if (is_sdvo && is_tv) |
5551 | dpll |= PLL_REF_INPUT_TVCLKINBC; | |
5552 | else if (is_tv) | |
79e53945 | 5553 | /* XXX: just matching BIOS for now */ |
43565a06 | 5554 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ |
79e53945 | 5555 | dpll |= 3; |
a7615030 | 5556 | else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 5557 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
5558 | else |
5559 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5560 | ||
de13a2e3 PZ |
5561 | return dpll; |
5562 | } | |
5563 | ||
5564 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, | |
de13a2e3 PZ |
5565 | int x, int y, |
5566 | struct drm_framebuffer *fb) | |
5567 | { | |
5568 | struct drm_device *dev = crtc->dev; | |
5569 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5570 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b8cecdf5 DV |
5571 | struct drm_display_mode *adjusted_mode = |
5572 | &intel_crtc->config.adjusted_mode; | |
5573 | struct drm_display_mode *mode = &intel_crtc->config.requested_mode; | |
de13a2e3 PZ |
5574 | int pipe = intel_crtc->pipe; |
5575 | int plane = intel_crtc->plane; | |
5576 | int num_connectors = 0; | |
5577 | intel_clock_t clock, reduced_clock; | |
5578 | u32 dpll, fp = 0, fp2 = 0; | |
e2f12b07 | 5579 | bool ok, has_reduced_clock = false; |
8b47047b | 5580 | bool is_lvds = false; |
de13a2e3 | 5581 | struct intel_encoder *encoder; |
de13a2e3 | 5582 | int ret; |
01a415fd | 5583 | bool dither, fdi_config_ok; |
de13a2e3 PZ |
5584 | |
5585 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
5586 | switch (encoder->type) { | |
5587 | case INTEL_OUTPUT_LVDS: | |
5588 | is_lvds = true; | |
5589 | break; | |
de13a2e3 PZ |
5590 | } |
5591 | ||
5592 | num_connectors++; | |
a07d6787 | 5593 | } |
79e53945 | 5594 | |
5dc5298b PZ |
5595 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
5596 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 5597 | |
6cf86a5e DV |
5598 | intel_crtc->cpu_transcoder = pipe; |
5599 | ||
de13a2e3 PZ |
5600 | ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock, |
5601 | &has_reduced_clock, &reduced_clock); | |
5602 | if (!ok) { | |
5603 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
5604 | return -EINVAL; | |
79e53945 | 5605 | } |
f47709a9 DV |
5606 | /* Compat-code for transition, will disappear. */ |
5607 | if (!intel_crtc->config.clock_set) { | |
5608 | intel_crtc->config.dpll.n = clock.n; | |
5609 | intel_crtc->config.dpll.m1 = clock.m1; | |
5610 | intel_crtc->config.dpll.m2 = clock.m2; | |
5611 | intel_crtc->config.dpll.p1 = clock.p1; | |
5612 | intel_crtc->config.dpll.p2 = clock.p2; | |
5613 | } | |
79e53945 | 5614 | |
de13a2e3 PZ |
5615 | /* Ensure that the cursor is valid for the new mode before changing... */ |
5616 | intel_crtc_update_cursor(crtc, true); | |
5617 | ||
5618 | /* determine panel color depth */ | |
4e53c2e0 | 5619 | dither = intel_crtc->config.dither; |
de13a2e3 PZ |
5620 | if (is_lvds && dev_priv->lvds_dither) |
5621 | dither = true; | |
5622 | ||
5623 | fp = clock.n << 16 | clock.m1 << 8 | clock.m2; | |
5624 | if (has_reduced_clock) | |
5625 | fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 | | |
5626 | reduced_clock.m2; | |
5627 | ||
9a7c7890 DV |
5628 | dpll = ironlake_compute_dpll(intel_crtc, &clock, &fp, &reduced_clock, |
5629 | has_reduced_clock ? &fp2 : NULL); | |
79e53945 | 5630 | |
f7cb34d4 | 5631 | DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe); |
79e53945 JB |
5632 | drm_mode_debug_printmodeline(mode); |
5633 | ||
5dc5298b | 5634 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
8b47047b | 5635 | if (intel_crtc->config.has_pch_encoder) { |
ee7b9f93 | 5636 | struct intel_pch_pll *pll; |
4b645f14 | 5637 | |
ee7b9f93 JB |
5638 | pll = intel_get_pch_pll(intel_crtc, dpll, fp); |
5639 | if (pll == NULL) { | |
5640 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n", | |
5641 | pipe); | |
4b645f14 JB |
5642 | return -EINVAL; |
5643 | } | |
ee7b9f93 JB |
5644 | } else |
5645 | intel_put_pch_pll(intel_crtc); | |
79e53945 | 5646 | |
03afc4a2 DV |
5647 | if (intel_crtc->config.has_dp_encoder) |
5648 | intel_dp_set_m_n(intel_crtc); | |
79e53945 | 5649 | |
dafd226c DV |
5650 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5651 | if (encoder->pre_pll_enable) | |
5652 | encoder->pre_pll_enable(encoder); | |
79e53945 | 5653 | |
ee7b9f93 JB |
5654 | if (intel_crtc->pch_pll) { |
5655 | I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll); | |
5eddb70b | 5656 | |
32f9d658 | 5657 | /* Wait for the clocks to stabilize. */ |
ee7b9f93 | 5658 | POSTING_READ(intel_crtc->pch_pll->pll_reg); |
32f9d658 ZW |
5659 | udelay(150); |
5660 | ||
8febb297 EA |
5661 | /* The pixel multiplier can only be updated once the |
5662 | * DPLL is enabled and the clocks are stable. | |
5663 | * | |
5664 | * So write it again. | |
5665 | */ | |
ee7b9f93 | 5666 | I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll); |
79e53945 | 5667 | } |
79e53945 | 5668 | |
5eddb70b | 5669 | intel_crtc->lowfreq_avail = false; |
ee7b9f93 | 5670 | if (intel_crtc->pch_pll) { |
4b645f14 | 5671 | if (is_lvds && has_reduced_clock && i915_powersave) { |
ee7b9f93 | 5672 | I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2); |
4b645f14 | 5673 | intel_crtc->lowfreq_avail = true; |
4b645f14 | 5674 | } else { |
ee7b9f93 | 5675 | I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp); |
652c393a JB |
5676 | } |
5677 | } | |
5678 | ||
b0e77b9c | 5679 | intel_set_pipe_timings(intel_crtc, mode, adjusted_mode); |
5eddb70b | 5680 | |
01a415fd DV |
5681 | /* Note, this also computes intel_crtc->fdi_lanes which is used below in |
5682 | * ironlake_check_fdi_lanes. */ | |
6cf86a5e DV |
5683 | intel_crtc->fdi_lanes = 0; |
5684 | if (intel_crtc->config.has_pch_encoder) | |
5685 | ironlake_fdi_set_m_n(crtc); | |
2c07245f | 5686 | |
01a415fd | 5687 | fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc); |
2c07245f | 5688 | |
c8203565 | 5689 | ironlake_set_pipeconf(crtc, adjusted_mode, dither); |
79e53945 | 5690 | |
9d0498a2 | 5691 | intel_wait_for_vblank(dev, pipe); |
79e53945 | 5692 | |
a1f9e77e PZ |
5693 | /* Set up the display plane register */ |
5694 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); | |
b24e7179 | 5695 | POSTING_READ(DSPCNTR(plane)); |
79e53945 | 5696 | |
94352cf9 | 5697 | ret = intel_pipe_set_base(crtc, x, y, fb); |
7662c8bd SL |
5698 | |
5699 | intel_update_watermarks(dev); | |
5700 | ||
1f8eeabf ED |
5701 | intel_update_linetime_watermarks(dev, pipe, adjusted_mode); |
5702 | ||
01a415fd | 5703 | return fdi_config_ok ? ret : -EINVAL; |
79e53945 JB |
5704 | } |
5705 | ||
0e8ffe1b DV |
5706 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5707 | struct intel_crtc_config *pipe_config) | |
5708 | { | |
5709 | struct drm_device *dev = crtc->base.dev; | |
5710 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5711 | uint32_t tmp; | |
5712 | ||
5713 | tmp = I915_READ(PIPECONF(crtc->pipe)); | |
5714 | if (!(tmp & PIPECONF_ENABLE)) | |
5715 | return false; | |
5716 | ||
88adfff1 DV |
5717 | if (I915_READ(TRANSCONF(crtc->pipe)) & TRANS_ENABLE) |
5718 | pipe_config->has_pch_encoder = true; | |
5719 | ||
0e8ffe1b DV |
5720 | return true; |
5721 | } | |
5722 | ||
d6dd9eb1 DV |
5723 | static void haswell_modeset_global_resources(struct drm_device *dev) |
5724 | { | |
5725 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5726 | bool enable = false; | |
5727 | struct intel_crtc *crtc; | |
5728 | struct intel_encoder *encoder; | |
5729 | ||
5730 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
5731 | if (crtc->pipe != PIPE_A && crtc->base.enabled) | |
5732 | enable = true; | |
5733 | /* XXX: Should check for edp transcoder here, but thanks to init | |
5734 | * sequence that's not yet available. Just in case desktop eDP | |
5735 | * on PORT D is possible on haswell, too. */ | |
5736 | } | |
5737 | ||
5738 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
5739 | base.head) { | |
5740 | if (encoder->type != INTEL_OUTPUT_EDP && | |
5741 | encoder->connectors_active) | |
5742 | enable = true; | |
5743 | } | |
5744 | ||
5745 | /* Even the eDP panel fitter is outside the always-on well. */ | |
5746 | if (dev_priv->pch_pf_size) | |
5747 | enable = true; | |
5748 | ||
5749 | intel_set_power_well(dev, enable); | |
5750 | } | |
5751 | ||
09b4ddf9 | 5752 | static int haswell_crtc_mode_set(struct drm_crtc *crtc, |
09b4ddf9 PZ |
5753 | int x, int y, |
5754 | struct drm_framebuffer *fb) | |
5755 | { | |
5756 | struct drm_device *dev = crtc->dev; | |
5757 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5758 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b8cecdf5 DV |
5759 | struct drm_display_mode *adjusted_mode = |
5760 | &intel_crtc->config.adjusted_mode; | |
5761 | struct drm_display_mode *mode = &intel_crtc->config.requested_mode; | |
09b4ddf9 PZ |
5762 | int pipe = intel_crtc->pipe; |
5763 | int plane = intel_crtc->plane; | |
5764 | int num_connectors = 0; | |
8b47047b | 5765 | bool is_cpu_edp = false; |
09b4ddf9 | 5766 | struct intel_encoder *encoder; |
09b4ddf9 PZ |
5767 | int ret; |
5768 | bool dither; | |
5769 | ||
5770 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
5771 | switch (encoder->type) { | |
09b4ddf9 | 5772 | case INTEL_OUTPUT_EDP: |
09b4ddf9 PZ |
5773 | if (!intel_encoder_is_pch_edp(&encoder->base)) |
5774 | is_cpu_edp = true; | |
5775 | break; | |
5776 | } | |
5777 | ||
5778 | num_connectors++; | |
5779 | } | |
5780 | ||
bba2181c DV |
5781 | if (is_cpu_edp) |
5782 | intel_crtc->cpu_transcoder = TRANSCODER_EDP; | |
5783 | else | |
5784 | intel_crtc->cpu_transcoder = pipe; | |
5785 | ||
5dc5298b PZ |
5786 | /* We are not sure yet this won't happen. */ |
5787 | WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n", | |
5788 | INTEL_PCH_TYPE(dev)); | |
5789 | ||
5790 | WARN(num_connectors != 1, "%d connectors attached to pipe %c\n", | |
5791 | num_connectors, pipe_name(pipe)); | |
5792 | ||
702e7a56 | 5793 | WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) & |
1ce42920 PZ |
5794 | (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE)); |
5795 | ||
5796 | WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE); | |
5797 | ||
6441ab5f PZ |
5798 | if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock)) |
5799 | return -EINVAL; | |
5800 | ||
09b4ddf9 PZ |
5801 | /* Ensure that the cursor is valid for the new mode before changing... */ |
5802 | intel_crtc_update_cursor(crtc, true); | |
5803 | ||
5804 | /* determine panel color depth */ | |
4e53c2e0 | 5805 | dither = intel_crtc->config.dither; |
09b4ddf9 | 5806 | |
09b4ddf9 PZ |
5807 | DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe); |
5808 | drm_mode_debug_printmodeline(mode); | |
5809 | ||
03afc4a2 DV |
5810 | if (intel_crtc->config.has_dp_encoder) |
5811 | intel_dp_set_m_n(intel_crtc); | |
09b4ddf9 PZ |
5812 | |
5813 | intel_crtc->lowfreq_avail = false; | |
09b4ddf9 PZ |
5814 | |
5815 | intel_set_pipe_timings(intel_crtc, mode, adjusted_mode); | |
5816 | ||
6cf86a5e DV |
5817 | if (intel_crtc->config.has_pch_encoder) |
5818 | ironlake_fdi_set_m_n(crtc); | |
09b4ddf9 | 5819 | |
ee2b0b38 | 5820 | haswell_set_pipeconf(crtc, adjusted_mode, dither); |
09b4ddf9 | 5821 | |
50f3b016 | 5822 | intel_set_pipe_csc(crtc); |
86d3efce | 5823 | |
09b4ddf9 | 5824 | /* Set up the display plane register */ |
86d3efce | 5825 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE); |
09b4ddf9 PZ |
5826 | POSTING_READ(DSPCNTR(plane)); |
5827 | ||
5828 | ret = intel_pipe_set_base(crtc, x, y, fb); | |
5829 | ||
5830 | intel_update_watermarks(dev); | |
5831 | ||
5832 | intel_update_linetime_watermarks(dev, pipe, adjusted_mode); | |
5833 | ||
1f803ee5 | 5834 | return ret; |
79e53945 JB |
5835 | } |
5836 | ||
0e8ffe1b DV |
5837 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5838 | struct intel_crtc_config *pipe_config) | |
5839 | { | |
5840 | struct drm_device *dev = crtc->base.dev; | |
5841 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5842 | uint32_t tmp; | |
5843 | ||
5844 | tmp = I915_READ(PIPECONF(crtc->cpu_transcoder)); | |
5845 | if (!(tmp & PIPECONF_ENABLE)) | |
5846 | return false; | |
5847 | ||
88adfff1 DV |
5848 | /* |
5849 | * aswell has only FDI/PCH transcoder A. It is which is connected to | |
5850 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
5851 | * the PCH transcoder is on. | |
5852 | */ | |
5853 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(crtc->pipe)); | |
5854 | if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) && | |
5855 | I915_READ(TRANSCONF(PIPE_A)) & TRANS_ENABLE) | |
5856 | pipe_config->has_pch_encoder = true; | |
5857 | ||
5858 | ||
0e8ffe1b DV |
5859 | return true; |
5860 | } | |
5861 | ||
f564048e | 5862 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
f564048e | 5863 | int x, int y, |
94352cf9 | 5864 | struct drm_framebuffer *fb) |
f564048e EA |
5865 | { |
5866 | struct drm_device *dev = crtc->dev; | |
5867 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9256aa19 DV |
5868 | struct drm_encoder_helper_funcs *encoder_funcs; |
5869 | struct intel_encoder *encoder; | |
0b701d27 | 5870 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
b8cecdf5 DV |
5871 | struct drm_display_mode *adjusted_mode = |
5872 | &intel_crtc->config.adjusted_mode; | |
5873 | struct drm_display_mode *mode = &intel_crtc->config.requested_mode; | |
0b701d27 | 5874 | int pipe = intel_crtc->pipe; |
f564048e EA |
5875 | int ret; |
5876 | ||
0b701d27 | 5877 | drm_vblank_pre_modeset(dev, pipe); |
7662c8bd | 5878 | |
b8cecdf5 DV |
5879 | ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb); |
5880 | ||
79e53945 | 5881 | drm_vblank_post_modeset(dev, pipe); |
5c3b82e2 | 5882 | |
9256aa19 DV |
5883 | if (ret != 0) |
5884 | return ret; | |
5885 | ||
5886 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
5887 | DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n", | |
5888 | encoder->base.base.id, | |
5889 | drm_get_encoder_name(&encoder->base), | |
5890 | mode->base.id, mode->name); | |
6cc5f341 DV |
5891 | if (encoder->mode_set) { |
5892 | encoder->mode_set(encoder); | |
5893 | } else { | |
5894 | encoder_funcs = encoder->base.helper_private; | |
5895 | encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode); | |
5896 | } | |
9256aa19 DV |
5897 | } |
5898 | ||
5899 | return 0; | |
79e53945 JB |
5900 | } |
5901 | ||
3a9627f4 WF |
5902 | static bool intel_eld_uptodate(struct drm_connector *connector, |
5903 | int reg_eldv, uint32_t bits_eldv, | |
5904 | int reg_elda, uint32_t bits_elda, | |
5905 | int reg_edid) | |
5906 | { | |
5907 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
5908 | uint8_t *eld = connector->eld; | |
5909 | uint32_t i; | |
5910 | ||
5911 | i = I915_READ(reg_eldv); | |
5912 | i &= bits_eldv; | |
5913 | ||
5914 | if (!eld[0]) | |
5915 | return !i; | |
5916 | ||
5917 | if (!i) | |
5918 | return false; | |
5919 | ||
5920 | i = I915_READ(reg_elda); | |
5921 | i &= ~bits_elda; | |
5922 | I915_WRITE(reg_elda, i); | |
5923 | ||
5924 | for (i = 0; i < eld[2]; i++) | |
5925 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) | |
5926 | return false; | |
5927 | ||
5928 | return true; | |
5929 | } | |
5930 | ||
e0dac65e WF |
5931 | static void g4x_write_eld(struct drm_connector *connector, |
5932 | struct drm_crtc *crtc) | |
5933 | { | |
5934 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
5935 | uint8_t *eld = connector->eld; | |
5936 | uint32_t eldv; | |
5937 | uint32_t len; | |
5938 | uint32_t i; | |
5939 | ||
5940 | i = I915_READ(G4X_AUD_VID_DID); | |
5941 | ||
5942 | if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) | |
5943 | eldv = G4X_ELDV_DEVCL_DEVBLC; | |
5944 | else | |
5945 | eldv = G4X_ELDV_DEVCTG; | |
5946 | ||
3a9627f4 WF |
5947 | if (intel_eld_uptodate(connector, |
5948 | G4X_AUD_CNTL_ST, eldv, | |
5949 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR, | |
5950 | G4X_HDMIW_HDMIEDID)) | |
5951 | return; | |
5952 | ||
e0dac65e WF |
5953 | i = I915_READ(G4X_AUD_CNTL_ST); |
5954 | i &= ~(eldv | G4X_ELD_ADDR); | |
5955 | len = (i >> 9) & 0x1f; /* ELD buffer size */ | |
5956 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
5957 | ||
5958 | if (!eld[0]) | |
5959 | return; | |
5960 | ||
5961 | len = min_t(uint8_t, eld[2], len); | |
5962 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
5963 | for (i = 0; i < len; i++) | |
5964 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); | |
5965 | ||
5966 | i = I915_READ(G4X_AUD_CNTL_ST); | |
5967 | i |= eldv; | |
5968 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
5969 | } | |
5970 | ||
83358c85 WX |
5971 | static void haswell_write_eld(struct drm_connector *connector, |
5972 | struct drm_crtc *crtc) | |
5973 | { | |
5974 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
5975 | uint8_t *eld = connector->eld; | |
5976 | struct drm_device *dev = crtc->dev; | |
7b9f35a6 | 5977 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
83358c85 WX |
5978 | uint32_t eldv; |
5979 | uint32_t i; | |
5980 | int len; | |
5981 | int pipe = to_intel_crtc(crtc)->pipe; | |
5982 | int tmp; | |
5983 | ||
5984 | int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe); | |
5985 | int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe); | |
5986 | int aud_config = HSW_AUD_CFG(pipe); | |
5987 | int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD; | |
5988 | ||
5989 | ||
5990 | DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n"); | |
5991 | ||
5992 | /* Audio output enable */ | |
5993 | DRM_DEBUG_DRIVER("HDMI audio: enable codec\n"); | |
5994 | tmp = I915_READ(aud_cntrl_st2); | |
5995 | tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4)); | |
5996 | I915_WRITE(aud_cntrl_st2, tmp); | |
5997 | ||
5998 | /* Wait for 1 vertical blank */ | |
5999 | intel_wait_for_vblank(dev, pipe); | |
6000 | ||
6001 | /* Set ELD valid state */ | |
6002 | tmp = I915_READ(aud_cntrl_st2); | |
6003 | DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp); | |
6004 | tmp |= (AUDIO_ELD_VALID_A << (pipe * 4)); | |
6005 | I915_WRITE(aud_cntrl_st2, tmp); | |
6006 | tmp = I915_READ(aud_cntrl_st2); | |
6007 | DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp); | |
6008 | ||
6009 | /* Enable HDMI mode */ | |
6010 | tmp = I915_READ(aud_config); | |
6011 | DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp); | |
6012 | /* clear N_programing_enable and N_value_index */ | |
6013 | tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE); | |
6014 | I915_WRITE(aud_config, tmp); | |
6015 | ||
6016 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); | |
6017 | ||
6018 | eldv = AUDIO_ELD_VALID_A << (pipe * 4); | |
7b9f35a6 | 6019 | intel_crtc->eld_vld = true; |
83358c85 WX |
6020 | |
6021 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { | |
6022 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
6023 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
6024 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ | |
6025 | } else | |
6026 | I915_WRITE(aud_config, 0); | |
6027 | ||
6028 | if (intel_eld_uptodate(connector, | |
6029 | aud_cntrl_st2, eldv, | |
6030 | aud_cntl_st, IBX_ELD_ADDRESS, | |
6031 | hdmiw_hdmiedid)) | |
6032 | return; | |
6033 | ||
6034 | i = I915_READ(aud_cntrl_st2); | |
6035 | i &= ~eldv; | |
6036 | I915_WRITE(aud_cntrl_st2, i); | |
6037 | ||
6038 | if (!eld[0]) | |
6039 | return; | |
6040 | ||
6041 | i = I915_READ(aud_cntl_st); | |
6042 | i &= ~IBX_ELD_ADDRESS; | |
6043 | I915_WRITE(aud_cntl_st, i); | |
6044 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ | |
6045 | DRM_DEBUG_DRIVER("port num:%d\n", i); | |
6046 | ||
6047 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
6048 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
6049 | for (i = 0; i < len; i++) | |
6050 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
6051 | ||
6052 | i = I915_READ(aud_cntrl_st2); | |
6053 | i |= eldv; | |
6054 | I915_WRITE(aud_cntrl_st2, i); | |
6055 | ||
6056 | } | |
6057 | ||
e0dac65e WF |
6058 | static void ironlake_write_eld(struct drm_connector *connector, |
6059 | struct drm_crtc *crtc) | |
6060 | { | |
6061 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
6062 | uint8_t *eld = connector->eld; | |
6063 | uint32_t eldv; | |
6064 | uint32_t i; | |
6065 | int len; | |
6066 | int hdmiw_hdmiedid; | |
b6daa025 | 6067 | int aud_config; |
e0dac65e WF |
6068 | int aud_cntl_st; |
6069 | int aud_cntrl_st2; | |
9b138a83 | 6070 | int pipe = to_intel_crtc(crtc)->pipe; |
e0dac65e | 6071 | |
b3f33cbf | 6072 | if (HAS_PCH_IBX(connector->dev)) { |
9b138a83 WX |
6073 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); |
6074 | aud_config = IBX_AUD_CFG(pipe); | |
6075 | aud_cntl_st = IBX_AUD_CNTL_ST(pipe); | |
1202b4c6 | 6076 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; |
e0dac65e | 6077 | } else { |
9b138a83 WX |
6078 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); |
6079 | aud_config = CPT_AUD_CFG(pipe); | |
6080 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); | |
1202b4c6 | 6081 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; |
e0dac65e WF |
6082 | } |
6083 | ||
9b138a83 | 6084 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
e0dac65e WF |
6085 | |
6086 | i = I915_READ(aud_cntl_st); | |
9b138a83 | 6087 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ |
e0dac65e WF |
6088 | if (!i) { |
6089 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); | |
6090 | /* operate blindly on all ports */ | |
1202b4c6 WF |
6091 | eldv = IBX_ELD_VALIDB; |
6092 | eldv |= IBX_ELD_VALIDB << 4; | |
6093 | eldv |= IBX_ELD_VALIDB << 8; | |
e0dac65e WF |
6094 | } else { |
6095 | DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i); | |
1202b4c6 | 6096 | eldv = IBX_ELD_VALIDB << ((i - 1) * 4); |
e0dac65e WF |
6097 | } |
6098 | ||
3a9627f4 WF |
6099 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
6100 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
6101 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
b6daa025 WF |
6102 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
6103 | } else | |
6104 | I915_WRITE(aud_config, 0); | |
e0dac65e | 6105 | |
3a9627f4 WF |
6106 | if (intel_eld_uptodate(connector, |
6107 | aud_cntrl_st2, eldv, | |
6108 | aud_cntl_st, IBX_ELD_ADDRESS, | |
6109 | hdmiw_hdmiedid)) | |
6110 | return; | |
6111 | ||
e0dac65e WF |
6112 | i = I915_READ(aud_cntrl_st2); |
6113 | i &= ~eldv; | |
6114 | I915_WRITE(aud_cntrl_st2, i); | |
6115 | ||
6116 | if (!eld[0]) | |
6117 | return; | |
6118 | ||
e0dac65e | 6119 | i = I915_READ(aud_cntl_st); |
1202b4c6 | 6120 | i &= ~IBX_ELD_ADDRESS; |
e0dac65e WF |
6121 | I915_WRITE(aud_cntl_st, i); |
6122 | ||
6123 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
6124 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
6125 | for (i = 0; i < len; i++) | |
6126 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
6127 | ||
6128 | i = I915_READ(aud_cntrl_st2); | |
6129 | i |= eldv; | |
6130 | I915_WRITE(aud_cntrl_st2, i); | |
6131 | } | |
6132 | ||
6133 | void intel_write_eld(struct drm_encoder *encoder, | |
6134 | struct drm_display_mode *mode) | |
6135 | { | |
6136 | struct drm_crtc *crtc = encoder->crtc; | |
6137 | struct drm_connector *connector; | |
6138 | struct drm_device *dev = encoder->dev; | |
6139 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6140 | ||
6141 | connector = drm_select_eld(encoder, mode); | |
6142 | if (!connector) | |
6143 | return; | |
6144 | ||
6145 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", | |
6146 | connector->base.id, | |
6147 | drm_get_connector_name(connector), | |
6148 | connector->encoder->base.id, | |
6149 | drm_get_encoder_name(connector->encoder)); | |
6150 | ||
6151 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; | |
6152 | ||
6153 | if (dev_priv->display.write_eld) | |
6154 | dev_priv->display.write_eld(connector, crtc); | |
6155 | } | |
6156 | ||
79e53945 JB |
6157 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ |
6158 | void intel_crtc_load_lut(struct drm_crtc *crtc) | |
6159 | { | |
6160 | struct drm_device *dev = crtc->dev; | |
6161 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6162 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9db4a9c7 | 6163 | int palreg = PALETTE(intel_crtc->pipe); |
79e53945 JB |
6164 | int i; |
6165 | ||
6166 | /* The clocks have to be on to load the palette. */ | |
aed3f09d | 6167 | if (!crtc->enabled || !intel_crtc->active) |
79e53945 JB |
6168 | return; |
6169 | ||
f2b115e6 | 6170 | /* use legacy palette for Ironlake */ |
bad720ff | 6171 | if (HAS_PCH_SPLIT(dev)) |
9db4a9c7 | 6172 | palreg = LGC_PALETTE(intel_crtc->pipe); |
2c07245f | 6173 | |
79e53945 JB |
6174 | for (i = 0; i < 256; i++) { |
6175 | I915_WRITE(palreg + 4 * i, | |
6176 | (intel_crtc->lut_r[i] << 16) | | |
6177 | (intel_crtc->lut_g[i] << 8) | | |
6178 | intel_crtc->lut_b[i]); | |
6179 | } | |
6180 | } | |
6181 | ||
560b85bb CW |
6182 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
6183 | { | |
6184 | struct drm_device *dev = crtc->dev; | |
6185 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6186 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6187 | bool visible = base != 0; | |
6188 | u32 cntl; | |
6189 | ||
6190 | if (intel_crtc->cursor_visible == visible) | |
6191 | return; | |
6192 | ||
9db4a9c7 | 6193 | cntl = I915_READ(_CURACNTR); |
560b85bb CW |
6194 | if (visible) { |
6195 | /* On these chipsets we can only modify the base whilst | |
6196 | * the cursor is disabled. | |
6197 | */ | |
9db4a9c7 | 6198 | I915_WRITE(_CURABASE, base); |
560b85bb CW |
6199 | |
6200 | cntl &= ~(CURSOR_FORMAT_MASK); | |
6201 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ | |
6202 | cntl |= CURSOR_ENABLE | | |
6203 | CURSOR_GAMMA_ENABLE | | |
6204 | CURSOR_FORMAT_ARGB; | |
6205 | } else | |
6206 | cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); | |
9db4a9c7 | 6207 | I915_WRITE(_CURACNTR, cntl); |
560b85bb CW |
6208 | |
6209 | intel_crtc->cursor_visible = visible; | |
6210 | } | |
6211 | ||
6212 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) | |
6213 | { | |
6214 | struct drm_device *dev = crtc->dev; | |
6215 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6216 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6217 | int pipe = intel_crtc->pipe; | |
6218 | bool visible = base != 0; | |
6219 | ||
6220 | if (intel_crtc->cursor_visible != visible) { | |
548f245b | 6221 | uint32_t cntl = I915_READ(CURCNTR(pipe)); |
560b85bb CW |
6222 | if (base) { |
6223 | cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); | |
6224 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
6225 | cntl |= pipe << 28; /* Connect to correct pipe */ | |
6226 | } else { | |
6227 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
6228 | cntl |= CURSOR_MODE_DISABLE; | |
6229 | } | |
9db4a9c7 | 6230 | I915_WRITE(CURCNTR(pipe), cntl); |
560b85bb CW |
6231 | |
6232 | intel_crtc->cursor_visible = visible; | |
6233 | } | |
6234 | /* and commit changes on next vblank */ | |
9db4a9c7 | 6235 | I915_WRITE(CURBASE(pipe), base); |
560b85bb CW |
6236 | } |
6237 | ||
65a21cd6 JB |
6238 | static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) |
6239 | { | |
6240 | struct drm_device *dev = crtc->dev; | |
6241 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6242 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6243 | int pipe = intel_crtc->pipe; | |
6244 | bool visible = base != 0; | |
6245 | ||
6246 | if (intel_crtc->cursor_visible != visible) { | |
6247 | uint32_t cntl = I915_READ(CURCNTR_IVB(pipe)); | |
6248 | if (base) { | |
6249 | cntl &= ~CURSOR_MODE; | |
6250 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
6251 | } else { | |
6252 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
6253 | cntl |= CURSOR_MODE_DISABLE; | |
6254 | } | |
86d3efce VS |
6255 | if (IS_HASWELL(dev)) |
6256 | cntl |= CURSOR_PIPE_CSC_ENABLE; | |
65a21cd6 JB |
6257 | I915_WRITE(CURCNTR_IVB(pipe), cntl); |
6258 | ||
6259 | intel_crtc->cursor_visible = visible; | |
6260 | } | |
6261 | /* and commit changes on next vblank */ | |
6262 | I915_WRITE(CURBASE_IVB(pipe), base); | |
6263 | } | |
6264 | ||
cda4b7d3 | 6265 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
6266 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
6267 | bool on) | |
cda4b7d3 CW |
6268 | { |
6269 | struct drm_device *dev = crtc->dev; | |
6270 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6271 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6272 | int pipe = intel_crtc->pipe; | |
6273 | int x = intel_crtc->cursor_x; | |
6274 | int y = intel_crtc->cursor_y; | |
560b85bb | 6275 | u32 base, pos; |
cda4b7d3 CW |
6276 | bool visible; |
6277 | ||
6278 | pos = 0; | |
6279 | ||
6b383a7f | 6280 | if (on && crtc->enabled && crtc->fb) { |
cda4b7d3 CW |
6281 | base = intel_crtc->cursor_addr; |
6282 | if (x > (int) crtc->fb->width) | |
6283 | base = 0; | |
6284 | ||
6285 | if (y > (int) crtc->fb->height) | |
6286 | base = 0; | |
6287 | } else | |
6288 | base = 0; | |
6289 | ||
6290 | if (x < 0) { | |
6291 | if (x + intel_crtc->cursor_width < 0) | |
6292 | base = 0; | |
6293 | ||
6294 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
6295 | x = -x; | |
6296 | } | |
6297 | pos |= x << CURSOR_X_SHIFT; | |
6298 | ||
6299 | if (y < 0) { | |
6300 | if (y + intel_crtc->cursor_height < 0) | |
6301 | base = 0; | |
6302 | ||
6303 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
6304 | y = -y; | |
6305 | } | |
6306 | pos |= y << CURSOR_Y_SHIFT; | |
6307 | ||
6308 | visible = base != 0; | |
560b85bb | 6309 | if (!visible && !intel_crtc->cursor_visible) |
cda4b7d3 CW |
6310 | return; |
6311 | ||
0cd83aa9 | 6312 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
65a21cd6 JB |
6313 | I915_WRITE(CURPOS_IVB(pipe), pos); |
6314 | ivb_update_cursor(crtc, base); | |
6315 | } else { | |
6316 | I915_WRITE(CURPOS(pipe), pos); | |
6317 | if (IS_845G(dev) || IS_I865G(dev)) | |
6318 | i845_update_cursor(crtc, base); | |
6319 | else | |
6320 | i9xx_update_cursor(crtc, base); | |
6321 | } | |
cda4b7d3 CW |
6322 | } |
6323 | ||
79e53945 | 6324 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
05394f39 | 6325 | struct drm_file *file, |
79e53945 JB |
6326 | uint32_t handle, |
6327 | uint32_t width, uint32_t height) | |
6328 | { | |
6329 | struct drm_device *dev = crtc->dev; | |
6330 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6331 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
05394f39 | 6332 | struct drm_i915_gem_object *obj; |
cda4b7d3 | 6333 | uint32_t addr; |
3f8bc370 | 6334 | int ret; |
79e53945 | 6335 | |
79e53945 JB |
6336 | /* if we want to turn off the cursor ignore width and height */ |
6337 | if (!handle) { | |
28c97730 | 6338 | DRM_DEBUG_KMS("cursor off\n"); |
3f8bc370 | 6339 | addr = 0; |
05394f39 | 6340 | obj = NULL; |
5004417d | 6341 | mutex_lock(&dev->struct_mutex); |
3f8bc370 | 6342 | goto finish; |
79e53945 JB |
6343 | } |
6344 | ||
6345 | /* Currently we only support 64x64 cursors */ | |
6346 | if (width != 64 || height != 64) { | |
6347 | DRM_ERROR("we currently only support 64x64 cursors\n"); | |
6348 | return -EINVAL; | |
6349 | } | |
6350 | ||
05394f39 | 6351 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 6352 | if (&obj->base == NULL) |
79e53945 JB |
6353 | return -ENOENT; |
6354 | ||
05394f39 | 6355 | if (obj->base.size < width * height * 4) { |
79e53945 | 6356 | DRM_ERROR("buffer is to small\n"); |
34b8686e DA |
6357 | ret = -ENOMEM; |
6358 | goto fail; | |
79e53945 JB |
6359 | } |
6360 | ||
71acb5eb | 6361 | /* we only need to pin inside GTT if cursor is non-phy */ |
7f9872e0 | 6362 | mutex_lock(&dev->struct_mutex); |
b295d1b6 | 6363 | if (!dev_priv->info->cursor_needs_physical) { |
693db184 CW |
6364 | unsigned alignment; |
6365 | ||
d9e86c0e CW |
6366 | if (obj->tiling_mode) { |
6367 | DRM_ERROR("cursor cannot be tiled\n"); | |
6368 | ret = -EINVAL; | |
6369 | goto fail_locked; | |
6370 | } | |
6371 | ||
693db184 CW |
6372 | /* Note that the w/a also requires 2 PTE of padding following |
6373 | * the bo. We currently fill all unused PTE with the shadow | |
6374 | * page and so we should always have valid PTE following the | |
6375 | * cursor preventing the VT-d warning. | |
6376 | */ | |
6377 | alignment = 0; | |
6378 | if (need_vtd_wa(dev)) | |
6379 | alignment = 64*1024; | |
6380 | ||
6381 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL); | |
e7b526bb CW |
6382 | if (ret) { |
6383 | DRM_ERROR("failed to move cursor bo into the GTT\n"); | |
2da3b9b9 | 6384 | goto fail_locked; |
e7b526bb CW |
6385 | } |
6386 | ||
d9e86c0e CW |
6387 | ret = i915_gem_object_put_fence(obj); |
6388 | if (ret) { | |
2da3b9b9 | 6389 | DRM_ERROR("failed to release fence for cursor"); |
d9e86c0e CW |
6390 | goto fail_unpin; |
6391 | } | |
6392 | ||
05394f39 | 6393 | addr = obj->gtt_offset; |
71acb5eb | 6394 | } else { |
6eeefaf3 | 6395 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
05394f39 | 6396 | ret = i915_gem_attach_phys_object(dev, obj, |
6eeefaf3 CW |
6397 | (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, |
6398 | align); | |
71acb5eb DA |
6399 | if (ret) { |
6400 | DRM_ERROR("failed to attach phys object\n"); | |
7f9872e0 | 6401 | goto fail_locked; |
71acb5eb | 6402 | } |
05394f39 | 6403 | addr = obj->phys_obj->handle->busaddr; |
3f8bc370 KH |
6404 | } |
6405 | ||
a6c45cf0 | 6406 | if (IS_GEN2(dev)) |
14b60391 JB |
6407 | I915_WRITE(CURSIZE, (height << 12) | width); |
6408 | ||
3f8bc370 | 6409 | finish: |
3f8bc370 | 6410 | if (intel_crtc->cursor_bo) { |
b295d1b6 | 6411 | if (dev_priv->info->cursor_needs_physical) { |
05394f39 | 6412 | if (intel_crtc->cursor_bo != obj) |
71acb5eb DA |
6413 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); |
6414 | } else | |
6415 | i915_gem_object_unpin(intel_crtc->cursor_bo); | |
05394f39 | 6416 | drm_gem_object_unreference(&intel_crtc->cursor_bo->base); |
3f8bc370 | 6417 | } |
80824003 | 6418 | |
7f9872e0 | 6419 | mutex_unlock(&dev->struct_mutex); |
3f8bc370 KH |
6420 | |
6421 | intel_crtc->cursor_addr = addr; | |
05394f39 | 6422 | intel_crtc->cursor_bo = obj; |
cda4b7d3 CW |
6423 | intel_crtc->cursor_width = width; |
6424 | intel_crtc->cursor_height = height; | |
6425 | ||
6b383a7f | 6426 | intel_crtc_update_cursor(crtc, true); |
3f8bc370 | 6427 | |
79e53945 | 6428 | return 0; |
e7b526bb | 6429 | fail_unpin: |
05394f39 | 6430 | i915_gem_object_unpin(obj); |
7f9872e0 | 6431 | fail_locked: |
34b8686e | 6432 | mutex_unlock(&dev->struct_mutex); |
bc9025bd | 6433 | fail: |
05394f39 | 6434 | drm_gem_object_unreference_unlocked(&obj->base); |
34b8686e | 6435 | return ret; |
79e53945 JB |
6436 | } |
6437 | ||
6438 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | |
6439 | { | |
79e53945 | 6440 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 6441 | |
cda4b7d3 CW |
6442 | intel_crtc->cursor_x = x; |
6443 | intel_crtc->cursor_y = y; | |
652c393a | 6444 | |
6b383a7f | 6445 | intel_crtc_update_cursor(crtc, true); |
79e53945 JB |
6446 | |
6447 | return 0; | |
6448 | } | |
6449 | ||
6450 | /** Sets the color ramps on behalf of RandR */ | |
6451 | void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, | |
6452 | u16 blue, int regno) | |
6453 | { | |
6454 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6455 | ||
6456 | intel_crtc->lut_r[regno] = red >> 8; | |
6457 | intel_crtc->lut_g[regno] = green >> 8; | |
6458 | intel_crtc->lut_b[regno] = blue >> 8; | |
6459 | } | |
6460 | ||
b8c00ac5 DA |
6461 | void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
6462 | u16 *blue, int regno) | |
6463 | { | |
6464 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6465 | ||
6466 | *red = intel_crtc->lut_r[regno] << 8; | |
6467 | *green = intel_crtc->lut_g[regno] << 8; | |
6468 | *blue = intel_crtc->lut_b[regno] << 8; | |
6469 | } | |
6470 | ||
79e53945 | 6471 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 6472 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 6473 | { |
7203425a | 6474 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 6475 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 6476 | |
7203425a | 6477 | for (i = start; i < end; i++) { |
79e53945 JB |
6478 | intel_crtc->lut_r[i] = red[i] >> 8; |
6479 | intel_crtc->lut_g[i] = green[i] >> 8; | |
6480 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
6481 | } | |
6482 | ||
6483 | intel_crtc_load_lut(crtc); | |
6484 | } | |
6485 | ||
79e53945 JB |
6486 | /* VESA 640x480x72Hz mode to set on the pipe */ |
6487 | static struct drm_display_mode load_detect_mode = { | |
6488 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
6489 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
6490 | }; | |
6491 | ||
d2dff872 CW |
6492 | static struct drm_framebuffer * |
6493 | intel_framebuffer_create(struct drm_device *dev, | |
308e5bcb | 6494 | struct drm_mode_fb_cmd2 *mode_cmd, |
d2dff872 CW |
6495 | struct drm_i915_gem_object *obj) |
6496 | { | |
6497 | struct intel_framebuffer *intel_fb; | |
6498 | int ret; | |
6499 | ||
6500 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
6501 | if (!intel_fb) { | |
6502 | drm_gem_object_unreference_unlocked(&obj->base); | |
6503 | return ERR_PTR(-ENOMEM); | |
6504 | } | |
6505 | ||
6506 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
6507 | if (ret) { | |
6508 | drm_gem_object_unreference_unlocked(&obj->base); | |
6509 | kfree(intel_fb); | |
6510 | return ERR_PTR(ret); | |
6511 | } | |
6512 | ||
6513 | return &intel_fb->base; | |
6514 | } | |
6515 | ||
6516 | static u32 | |
6517 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
6518 | { | |
6519 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
6520 | return ALIGN(pitch, 64); | |
6521 | } | |
6522 | ||
6523 | static u32 | |
6524 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
6525 | { | |
6526 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
6527 | return ALIGN(pitch * mode->vdisplay, PAGE_SIZE); | |
6528 | } | |
6529 | ||
6530 | static struct drm_framebuffer * | |
6531 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
6532 | struct drm_display_mode *mode, | |
6533 | int depth, int bpp) | |
6534 | { | |
6535 | struct drm_i915_gem_object *obj; | |
0fed39bd | 6536 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
6537 | |
6538 | obj = i915_gem_alloc_object(dev, | |
6539 | intel_framebuffer_size_for_mode(mode, bpp)); | |
6540 | if (obj == NULL) | |
6541 | return ERR_PTR(-ENOMEM); | |
6542 | ||
6543 | mode_cmd.width = mode->hdisplay; | |
6544 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
6545 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
6546 | bpp); | |
5ca0c34a | 6547 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
6548 | |
6549 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
6550 | } | |
6551 | ||
6552 | static struct drm_framebuffer * | |
6553 | mode_fits_in_fbdev(struct drm_device *dev, | |
6554 | struct drm_display_mode *mode) | |
6555 | { | |
6556 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6557 | struct drm_i915_gem_object *obj; | |
6558 | struct drm_framebuffer *fb; | |
6559 | ||
6560 | if (dev_priv->fbdev == NULL) | |
6561 | return NULL; | |
6562 | ||
6563 | obj = dev_priv->fbdev->ifb.obj; | |
6564 | if (obj == NULL) | |
6565 | return NULL; | |
6566 | ||
6567 | fb = &dev_priv->fbdev->ifb.base; | |
01f2c773 VS |
6568 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
6569 | fb->bits_per_pixel)) | |
d2dff872 CW |
6570 | return NULL; |
6571 | ||
01f2c773 | 6572 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
6573 | return NULL; |
6574 | ||
6575 | return fb; | |
6576 | } | |
6577 | ||
d2434ab7 | 6578 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 6579 | struct drm_display_mode *mode, |
8261b191 | 6580 | struct intel_load_detect_pipe *old) |
79e53945 JB |
6581 | { |
6582 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
6583 | struct intel_encoder *intel_encoder = |
6584 | intel_attached_encoder(connector); | |
79e53945 | 6585 | struct drm_crtc *possible_crtc; |
4ef69c7a | 6586 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
6587 | struct drm_crtc *crtc = NULL; |
6588 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 6589 | struct drm_framebuffer *fb; |
79e53945 JB |
6590 | int i = -1; |
6591 | ||
d2dff872 CW |
6592 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
6593 | connector->base.id, drm_get_connector_name(connector), | |
6594 | encoder->base.id, drm_get_encoder_name(encoder)); | |
6595 | ||
79e53945 JB |
6596 | /* |
6597 | * Algorithm gets a little messy: | |
7a5e4805 | 6598 | * |
79e53945 JB |
6599 | * - if the connector already has an assigned crtc, use it (but make |
6600 | * sure it's on first) | |
7a5e4805 | 6601 | * |
79e53945 JB |
6602 | * - try to find the first unused crtc that can drive this connector, |
6603 | * and use that if we find one | |
79e53945 JB |
6604 | */ |
6605 | ||
6606 | /* See if we already have a CRTC for this connector */ | |
6607 | if (encoder->crtc) { | |
6608 | crtc = encoder->crtc; | |
8261b191 | 6609 | |
7b24056b DV |
6610 | mutex_lock(&crtc->mutex); |
6611 | ||
24218aac | 6612 | old->dpms_mode = connector->dpms; |
8261b191 CW |
6613 | old->load_detect_temp = false; |
6614 | ||
6615 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
6616 | if (connector->dpms != DRM_MODE_DPMS_ON) |
6617 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 6618 | |
7173188d | 6619 | return true; |
79e53945 JB |
6620 | } |
6621 | ||
6622 | /* Find an unused one (if possible) */ | |
6623 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { | |
6624 | i++; | |
6625 | if (!(encoder->possible_crtcs & (1 << i))) | |
6626 | continue; | |
6627 | if (!possible_crtc->enabled) { | |
6628 | crtc = possible_crtc; | |
6629 | break; | |
6630 | } | |
79e53945 JB |
6631 | } |
6632 | ||
6633 | /* | |
6634 | * If we didn't find an unused CRTC, don't use any. | |
6635 | */ | |
6636 | if (!crtc) { | |
7173188d CW |
6637 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
6638 | return false; | |
79e53945 JB |
6639 | } |
6640 | ||
7b24056b | 6641 | mutex_lock(&crtc->mutex); |
fc303101 DV |
6642 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
6643 | to_intel_connector(connector)->new_encoder = intel_encoder; | |
79e53945 JB |
6644 | |
6645 | intel_crtc = to_intel_crtc(crtc); | |
24218aac | 6646 | old->dpms_mode = connector->dpms; |
8261b191 | 6647 | old->load_detect_temp = true; |
d2dff872 | 6648 | old->release_fb = NULL; |
79e53945 | 6649 | |
6492711d CW |
6650 | if (!mode) |
6651 | mode = &load_detect_mode; | |
79e53945 | 6652 | |
d2dff872 CW |
6653 | /* We need a framebuffer large enough to accommodate all accesses |
6654 | * that the plane may generate whilst we perform load detection. | |
6655 | * We can not rely on the fbcon either being present (we get called | |
6656 | * during its initialisation to detect all boot displays, or it may | |
6657 | * not even exist) or that it is large enough to satisfy the | |
6658 | * requested mode. | |
6659 | */ | |
94352cf9 DV |
6660 | fb = mode_fits_in_fbdev(dev, mode); |
6661 | if (fb == NULL) { | |
d2dff872 | 6662 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
6663 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
6664 | old->release_fb = fb; | |
d2dff872 CW |
6665 | } else |
6666 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 6667 | if (IS_ERR(fb)) { |
d2dff872 | 6668 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
7b24056b | 6669 | mutex_unlock(&crtc->mutex); |
0e8b3d3e | 6670 | return false; |
79e53945 | 6671 | } |
79e53945 | 6672 | |
c0c36b94 | 6673 | if (intel_set_mode(crtc, mode, 0, 0, fb)) { |
6492711d | 6674 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
6675 | if (old->release_fb) |
6676 | old->release_fb->funcs->destroy(old->release_fb); | |
7b24056b | 6677 | mutex_unlock(&crtc->mutex); |
0e8b3d3e | 6678 | return false; |
79e53945 | 6679 | } |
7173188d | 6680 | |
79e53945 | 6681 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 6682 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 6683 | return true; |
79e53945 JB |
6684 | } |
6685 | ||
d2434ab7 | 6686 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
8261b191 | 6687 | struct intel_load_detect_pipe *old) |
79e53945 | 6688 | { |
d2434ab7 DV |
6689 | struct intel_encoder *intel_encoder = |
6690 | intel_attached_encoder(connector); | |
4ef69c7a | 6691 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 6692 | struct drm_crtc *crtc = encoder->crtc; |
79e53945 | 6693 | |
d2dff872 CW |
6694 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
6695 | connector->base.id, drm_get_connector_name(connector), | |
6696 | encoder->base.id, drm_get_encoder_name(encoder)); | |
6697 | ||
8261b191 | 6698 | if (old->load_detect_temp) { |
fc303101 DV |
6699 | to_intel_connector(connector)->new_encoder = NULL; |
6700 | intel_encoder->new_crtc = NULL; | |
6701 | intel_set_mode(crtc, NULL, 0, 0, NULL); | |
d2dff872 | 6702 | |
36206361 DV |
6703 | if (old->release_fb) { |
6704 | drm_framebuffer_unregister_private(old->release_fb); | |
6705 | drm_framebuffer_unreference(old->release_fb); | |
6706 | } | |
d2dff872 | 6707 | |
67c96400 | 6708 | mutex_unlock(&crtc->mutex); |
0622a53c | 6709 | return; |
79e53945 JB |
6710 | } |
6711 | ||
c751ce4f | 6712 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
6713 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
6714 | connector->funcs->dpms(connector, old->dpms_mode); | |
7b24056b DV |
6715 | |
6716 | mutex_unlock(&crtc->mutex); | |
79e53945 JB |
6717 | } |
6718 | ||
6719 | /* Returns the clock of the currently programmed mode of the given pipe. */ | |
6720 | static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc) | |
6721 | { | |
6722 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6723 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6724 | int pipe = intel_crtc->pipe; | |
548f245b | 6725 | u32 dpll = I915_READ(DPLL(pipe)); |
79e53945 JB |
6726 | u32 fp; |
6727 | intel_clock_t clock; | |
6728 | ||
6729 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
39adb7a5 | 6730 | fp = I915_READ(FP0(pipe)); |
79e53945 | 6731 | else |
39adb7a5 | 6732 | fp = I915_READ(FP1(pipe)); |
79e53945 JB |
6733 | |
6734 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
6735 | if (IS_PINEVIEW(dev)) { |
6736 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
6737 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
6738 | } else { |
6739 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
6740 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
6741 | } | |
6742 | ||
a6c45cf0 | 6743 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
6744 | if (IS_PINEVIEW(dev)) |
6745 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
6746 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
6747 | else |
6748 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
6749 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
6750 | ||
6751 | switch (dpll & DPLL_MODE_MASK) { | |
6752 | case DPLLB_MODE_DAC_SERIAL: | |
6753 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
6754 | 5 : 10; | |
6755 | break; | |
6756 | case DPLLB_MODE_LVDS: | |
6757 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
6758 | 7 : 14; | |
6759 | break; | |
6760 | default: | |
28c97730 | 6761 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 JB |
6762 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
6763 | return 0; | |
6764 | } | |
6765 | ||
6766 | /* XXX: Handle the 100Mhz refclk */ | |
2177832f | 6767 | intel_clock(dev, 96000, &clock); |
79e53945 JB |
6768 | } else { |
6769 | bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); | |
6770 | ||
6771 | if (is_lvds) { | |
6772 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
6773 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
6774 | clock.p2 = 14; | |
6775 | ||
6776 | if ((dpll & PLL_REF_INPUT_MASK) == | |
6777 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
6778 | /* XXX: might not be 66MHz */ | |
2177832f | 6779 | intel_clock(dev, 66000, &clock); |
79e53945 | 6780 | } else |
2177832f | 6781 | intel_clock(dev, 48000, &clock); |
79e53945 JB |
6782 | } else { |
6783 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
6784 | clock.p1 = 2; | |
6785 | else { | |
6786 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
6787 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
6788 | } | |
6789 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
6790 | clock.p2 = 4; | |
6791 | else | |
6792 | clock.p2 = 2; | |
6793 | ||
2177832f | 6794 | intel_clock(dev, 48000, &clock); |
79e53945 JB |
6795 | } |
6796 | } | |
6797 | ||
6798 | /* XXX: It would be nice to validate the clocks, but we can't reuse | |
6799 | * i830PllIsValid() because it relies on the xf86_config connector | |
6800 | * configuration being accurate, which it isn't necessarily. | |
6801 | */ | |
6802 | ||
6803 | return clock.dot; | |
6804 | } | |
6805 | ||
6806 | /** Returns the currently programmed mode of the given pipe. */ | |
6807 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
6808 | struct drm_crtc *crtc) | |
6809 | { | |
548f245b | 6810 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 6811 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
fe2b8f9d | 6812 | enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; |
79e53945 | 6813 | struct drm_display_mode *mode; |
fe2b8f9d PZ |
6814 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
6815 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
6816 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
6817 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
79e53945 JB |
6818 | |
6819 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
6820 | if (!mode) | |
6821 | return NULL; | |
6822 | ||
6823 | mode->clock = intel_crtc_clock_get(dev, crtc); | |
6824 | mode->hdisplay = (htot & 0xffff) + 1; | |
6825 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
6826 | mode->hsync_start = (hsync & 0xffff) + 1; | |
6827 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
6828 | mode->vdisplay = (vtot & 0xffff) + 1; | |
6829 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
6830 | mode->vsync_start = (vsync & 0xffff) + 1; | |
6831 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
6832 | ||
6833 | drm_mode_set_name(mode); | |
79e53945 JB |
6834 | |
6835 | return mode; | |
6836 | } | |
6837 | ||
3dec0095 | 6838 | static void intel_increase_pllclock(struct drm_crtc *crtc) |
652c393a JB |
6839 | { |
6840 | struct drm_device *dev = crtc->dev; | |
6841 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6842 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6843 | int pipe = intel_crtc->pipe; | |
dbdc6479 JB |
6844 | int dpll_reg = DPLL(pipe); |
6845 | int dpll; | |
652c393a | 6846 | |
bad720ff | 6847 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
6848 | return; |
6849 | ||
6850 | if (!dev_priv->lvds_downclock_avail) | |
6851 | return; | |
6852 | ||
dbdc6479 | 6853 | dpll = I915_READ(dpll_reg); |
652c393a | 6854 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
44d98a61 | 6855 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
652c393a | 6856 | |
8ac5a6d5 | 6857 | assert_panel_unlocked(dev_priv, pipe); |
652c393a JB |
6858 | |
6859 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; | |
6860 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 6861 | intel_wait_for_vblank(dev, pipe); |
dbdc6479 | 6862 | |
652c393a JB |
6863 | dpll = I915_READ(dpll_reg); |
6864 | if (dpll & DISPLAY_RATE_SELECT_FPA1) | |
44d98a61 | 6865 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
652c393a | 6866 | } |
652c393a JB |
6867 | } |
6868 | ||
6869 | static void intel_decrease_pllclock(struct drm_crtc *crtc) | |
6870 | { | |
6871 | struct drm_device *dev = crtc->dev; | |
6872 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6873 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
652c393a | 6874 | |
bad720ff | 6875 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
6876 | return; |
6877 | ||
6878 | if (!dev_priv->lvds_downclock_avail) | |
6879 | return; | |
6880 | ||
6881 | /* | |
6882 | * Since this is called by a timer, we should never get here in | |
6883 | * the manual case. | |
6884 | */ | |
6885 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
dc257cf1 DV |
6886 | int pipe = intel_crtc->pipe; |
6887 | int dpll_reg = DPLL(pipe); | |
6888 | int dpll; | |
f6e5b160 | 6889 | |
44d98a61 | 6890 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a | 6891 | |
8ac5a6d5 | 6892 | assert_panel_unlocked(dev_priv, pipe); |
652c393a | 6893 | |
dc257cf1 | 6894 | dpll = I915_READ(dpll_reg); |
652c393a JB |
6895 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
6896 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 6897 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
6898 | dpll = I915_READ(dpll_reg); |
6899 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 6900 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
6901 | } |
6902 | ||
6903 | } | |
6904 | ||
f047e395 CW |
6905 | void intel_mark_busy(struct drm_device *dev) |
6906 | { | |
f047e395 CW |
6907 | i915_update_gfx_val(dev->dev_private); |
6908 | } | |
6909 | ||
6910 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 6911 | { |
652c393a | 6912 | struct drm_crtc *crtc; |
652c393a JB |
6913 | |
6914 | if (!i915_powersave) | |
6915 | return; | |
6916 | ||
652c393a | 6917 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
652c393a JB |
6918 | if (!crtc->fb) |
6919 | continue; | |
6920 | ||
725a5b54 | 6921 | intel_decrease_pllclock(crtc); |
652c393a | 6922 | } |
652c393a JB |
6923 | } |
6924 | ||
725a5b54 | 6925 | void intel_mark_fb_busy(struct drm_i915_gem_object *obj) |
652c393a | 6926 | { |
f047e395 CW |
6927 | struct drm_device *dev = obj->base.dev; |
6928 | struct drm_crtc *crtc; | |
652c393a | 6929 | |
f047e395 | 6930 | if (!i915_powersave) |
acb87dfb CW |
6931 | return; |
6932 | ||
652c393a JB |
6933 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
6934 | if (!crtc->fb) | |
6935 | continue; | |
6936 | ||
f047e395 | 6937 | if (to_intel_framebuffer(crtc->fb)->obj == obj) |
725a5b54 | 6938 | intel_increase_pllclock(crtc); |
652c393a JB |
6939 | } |
6940 | } | |
6941 | ||
79e53945 JB |
6942 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
6943 | { | |
6944 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
6945 | struct drm_device *dev = crtc->dev; |
6946 | struct intel_unpin_work *work; | |
6947 | unsigned long flags; | |
6948 | ||
6949 | spin_lock_irqsave(&dev->event_lock, flags); | |
6950 | work = intel_crtc->unpin_work; | |
6951 | intel_crtc->unpin_work = NULL; | |
6952 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
6953 | ||
6954 | if (work) { | |
6955 | cancel_work_sync(&work->work); | |
6956 | kfree(work); | |
6957 | } | |
79e53945 JB |
6958 | |
6959 | drm_crtc_cleanup(crtc); | |
67e77c5a | 6960 | |
79e53945 JB |
6961 | kfree(intel_crtc); |
6962 | } | |
6963 | ||
6b95a207 KH |
6964 | static void intel_unpin_work_fn(struct work_struct *__work) |
6965 | { | |
6966 | struct intel_unpin_work *work = | |
6967 | container_of(__work, struct intel_unpin_work, work); | |
b4a98e57 | 6968 | struct drm_device *dev = work->crtc->dev; |
6b95a207 | 6969 | |
b4a98e57 | 6970 | mutex_lock(&dev->struct_mutex); |
1690e1eb | 6971 | intel_unpin_fb_obj(work->old_fb_obj); |
05394f39 CW |
6972 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
6973 | drm_gem_object_unreference(&work->old_fb_obj->base); | |
d9e86c0e | 6974 | |
b4a98e57 CW |
6975 | intel_update_fbc(dev); |
6976 | mutex_unlock(&dev->struct_mutex); | |
6977 | ||
6978 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); | |
6979 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); | |
6980 | ||
6b95a207 KH |
6981 | kfree(work); |
6982 | } | |
6983 | ||
1afe3e9d | 6984 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 6985 | struct drm_crtc *crtc) |
6b95a207 KH |
6986 | { |
6987 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6b95a207 KH |
6988 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6989 | struct intel_unpin_work *work; | |
6b95a207 KH |
6990 | unsigned long flags; |
6991 | ||
6992 | /* Ignore early vblank irqs */ | |
6993 | if (intel_crtc == NULL) | |
6994 | return; | |
6995 | ||
6996 | spin_lock_irqsave(&dev->event_lock, flags); | |
6997 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
6998 | |
6999 | /* Ensure we don't miss a work->pending update ... */ | |
7000 | smp_rmb(); | |
7001 | ||
7002 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
7003 | spin_unlock_irqrestore(&dev->event_lock, flags); |
7004 | return; | |
7005 | } | |
7006 | ||
e7d841ca CW |
7007 | /* and that the unpin work is consistent wrt ->pending. */ |
7008 | smp_rmb(); | |
7009 | ||
6b95a207 | 7010 | intel_crtc->unpin_work = NULL; |
6b95a207 | 7011 | |
45a066eb RC |
7012 | if (work->event) |
7013 | drm_send_vblank_event(dev, intel_crtc->pipe, work->event); | |
6b95a207 | 7014 | |
0af7e4df MK |
7015 | drm_vblank_put(dev, intel_crtc->pipe); |
7016 | ||
6b95a207 KH |
7017 | spin_unlock_irqrestore(&dev->event_lock, flags); |
7018 | ||
2c10d571 | 7019 | wake_up_all(&dev_priv->pending_flip_queue); |
b4a98e57 CW |
7020 | |
7021 | queue_work(dev_priv->wq, &work->work); | |
e5510fac JB |
7022 | |
7023 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); | |
6b95a207 KH |
7024 | } |
7025 | ||
1afe3e9d JB |
7026 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
7027 | { | |
7028 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7029 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
7030 | ||
49b14a5c | 7031 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
7032 | } |
7033 | ||
7034 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
7035 | { | |
7036 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7037 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; | |
7038 | ||
49b14a5c | 7039 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
7040 | } |
7041 | ||
6b95a207 KH |
7042 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
7043 | { | |
7044 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7045 | struct intel_crtc *intel_crtc = | |
7046 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
7047 | unsigned long flags; | |
7048 | ||
e7d841ca CW |
7049 | /* NB: An MMIO update of the plane base pointer will also |
7050 | * generate a page-flip completion irq, i.e. every modeset | |
7051 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
7052 | */ | |
6b95a207 | 7053 | spin_lock_irqsave(&dev->event_lock, flags); |
e7d841ca CW |
7054 | if (intel_crtc->unpin_work) |
7055 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); | |
6b95a207 KH |
7056 | spin_unlock_irqrestore(&dev->event_lock, flags); |
7057 | } | |
7058 | ||
e7d841ca CW |
7059 | inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
7060 | { | |
7061 | /* Ensure that the work item is consistent when activating it ... */ | |
7062 | smp_wmb(); | |
7063 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); | |
7064 | /* and that it is marked active as soon as the irq could fire. */ | |
7065 | smp_wmb(); | |
7066 | } | |
7067 | ||
8c9f3aaf JB |
7068 | static int intel_gen2_queue_flip(struct drm_device *dev, |
7069 | struct drm_crtc *crtc, | |
7070 | struct drm_framebuffer *fb, | |
7071 | struct drm_i915_gem_object *obj) | |
7072 | { | |
7073 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7074 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8c9f3aaf | 7075 | u32 flip_mask; |
6d90c952 | 7076 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
7077 | int ret; |
7078 | ||
6d90c952 | 7079 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 7080 | if (ret) |
83d4092b | 7081 | goto err; |
8c9f3aaf | 7082 | |
6d90c952 | 7083 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 7084 | if (ret) |
83d4092b | 7085 | goto err_unpin; |
8c9f3aaf JB |
7086 | |
7087 | /* Can't queue multiple flips, so wait for the previous | |
7088 | * one to finish before executing the next. | |
7089 | */ | |
7090 | if (intel_crtc->plane) | |
7091 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
7092 | else | |
7093 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
7094 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
7095 | intel_ring_emit(ring, MI_NOOP); | |
7096 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
7097 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
7098 | intel_ring_emit(ring, fb->pitches[0]); | |
e506a0c6 | 7099 | intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); |
6d90c952 | 7100 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca CW |
7101 | |
7102 | intel_mark_page_flip_active(intel_crtc); | |
6d90c952 | 7103 | intel_ring_advance(ring); |
83d4092b CW |
7104 | return 0; |
7105 | ||
7106 | err_unpin: | |
7107 | intel_unpin_fb_obj(obj); | |
7108 | err: | |
8c9f3aaf JB |
7109 | return ret; |
7110 | } | |
7111 | ||
7112 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
7113 | struct drm_crtc *crtc, | |
7114 | struct drm_framebuffer *fb, | |
7115 | struct drm_i915_gem_object *obj) | |
7116 | { | |
7117 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7118 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8c9f3aaf | 7119 | u32 flip_mask; |
6d90c952 | 7120 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
7121 | int ret; |
7122 | ||
6d90c952 | 7123 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 7124 | if (ret) |
83d4092b | 7125 | goto err; |
8c9f3aaf | 7126 | |
6d90c952 | 7127 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 7128 | if (ret) |
83d4092b | 7129 | goto err_unpin; |
8c9f3aaf JB |
7130 | |
7131 | if (intel_crtc->plane) | |
7132 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
7133 | else | |
7134 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
7135 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
7136 | intel_ring_emit(ring, MI_NOOP); | |
7137 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
7138 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
7139 | intel_ring_emit(ring, fb->pitches[0]); | |
e506a0c6 | 7140 | intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); |
6d90c952 DV |
7141 | intel_ring_emit(ring, MI_NOOP); |
7142 | ||
e7d841ca | 7143 | intel_mark_page_flip_active(intel_crtc); |
6d90c952 | 7144 | intel_ring_advance(ring); |
83d4092b CW |
7145 | return 0; |
7146 | ||
7147 | err_unpin: | |
7148 | intel_unpin_fb_obj(obj); | |
7149 | err: | |
8c9f3aaf JB |
7150 | return ret; |
7151 | } | |
7152 | ||
7153 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
7154 | struct drm_crtc *crtc, | |
7155 | struct drm_framebuffer *fb, | |
7156 | struct drm_i915_gem_object *obj) | |
7157 | { | |
7158 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7159 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7160 | uint32_t pf, pipesrc; | |
6d90c952 | 7161 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
7162 | int ret; |
7163 | ||
6d90c952 | 7164 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 7165 | if (ret) |
83d4092b | 7166 | goto err; |
8c9f3aaf | 7167 | |
6d90c952 | 7168 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 7169 | if (ret) |
83d4092b | 7170 | goto err_unpin; |
8c9f3aaf JB |
7171 | |
7172 | /* i965+ uses the linear or tiled offsets from the | |
7173 | * Display Registers (which do not change across a page-flip) | |
7174 | * so we need only reprogram the base address. | |
7175 | */ | |
6d90c952 DV |
7176 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
7177 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
7178 | intel_ring_emit(ring, fb->pitches[0]); | |
c2c75131 DV |
7179 | intel_ring_emit(ring, |
7180 | (obj->gtt_offset + intel_crtc->dspaddr_offset) | | |
7181 | obj->tiling_mode); | |
8c9f3aaf JB |
7182 | |
7183 | /* XXX Enabling the panel-fitter across page-flip is so far | |
7184 | * untested on non-native modes, so ignore it for now. | |
7185 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
7186 | */ | |
7187 | pf = 0; | |
7188 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 7189 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
7190 | |
7191 | intel_mark_page_flip_active(intel_crtc); | |
6d90c952 | 7192 | intel_ring_advance(ring); |
83d4092b CW |
7193 | return 0; |
7194 | ||
7195 | err_unpin: | |
7196 | intel_unpin_fb_obj(obj); | |
7197 | err: | |
8c9f3aaf JB |
7198 | return ret; |
7199 | } | |
7200 | ||
7201 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
7202 | struct drm_crtc *crtc, | |
7203 | struct drm_framebuffer *fb, | |
7204 | struct drm_i915_gem_object *obj) | |
7205 | { | |
7206 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7207 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6d90c952 | 7208 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
7209 | uint32_t pf, pipesrc; |
7210 | int ret; | |
7211 | ||
6d90c952 | 7212 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 7213 | if (ret) |
83d4092b | 7214 | goto err; |
8c9f3aaf | 7215 | |
6d90c952 | 7216 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 7217 | if (ret) |
83d4092b | 7218 | goto err_unpin; |
8c9f3aaf | 7219 | |
6d90c952 DV |
7220 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
7221 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
7222 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
c2c75131 | 7223 | intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); |
8c9f3aaf | 7224 | |
dc257cf1 DV |
7225 | /* Contrary to the suggestions in the documentation, |
7226 | * "Enable Panel Fitter" does not seem to be required when page | |
7227 | * flipping with a non-native mode, and worse causes a normal | |
7228 | * modeset to fail. | |
7229 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
7230 | */ | |
7231 | pf = 0; | |
8c9f3aaf | 7232 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 7233 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
7234 | |
7235 | intel_mark_page_flip_active(intel_crtc); | |
6d90c952 | 7236 | intel_ring_advance(ring); |
83d4092b CW |
7237 | return 0; |
7238 | ||
7239 | err_unpin: | |
7240 | intel_unpin_fb_obj(obj); | |
7241 | err: | |
8c9f3aaf JB |
7242 | return ret; |
7243 | } | |
7244 | ||
7c9017e5 JB |
7245 | /* |
7246 | * On gen7 we currently use the blit ring because (in early silicon at least) | |
7247 | * the render ring doesn't give us interrpts for page flip completion, which | |
7248 | * means clients will hang after the first flip is queued. Fortunately the | |
7249 | * blit ring generates interrupts properly, so use it instead. | |
7250 | */ | |
7251 | static int intel_gen7_queue_flip(struct drm_device *dev, | |
7252 | struct drm_crtc *crtc, | |
7253 | struct drm_framebuffer *fb, | |
7254 | struct drm_i915_gem_object *obj) | |
7255 | { | |
7256 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7257 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7258 | struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; | |
cb05d8de | 7259 | uint32_t plane_bit = 0; |
7c9017e5 JB |
7260 | int ret; |
7261 | ||
7262 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); | |
7263 | if (ret) | |
83d4092b | 7264 | goto err; |
7c9017e5 | 7265 | |
cb05d8de DV |
7266 | switch(intel_crtc->plane) { |
7267 | case PLANE_A: | |
7268 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
7269 | break; | |
7270 | case PLANE_B: | |
7271 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
7272 | break; | |
7273 | case PLANE_C: | |
7274 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
7275 | break; | |
7276 | default: | |
7277 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
7278 | ret = -ENODEV; | |
ab3951eb | 7279 | goto err_unpin; |
cb05d8de DV |
7280 | } |
7281 | ||
7c9017e5 JB |
7282 | ret = intel_ring_begin(ring, 4); |
7283 | if (ret) | |
83d4092b | 7284 | goto err_unpin; |
7c9017e5 | 7285 | |
cb05d8de | 7286 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 7287 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
c2c75131 | 7288 | intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); |
7c9017e5 | 7289 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca CW |
7290 | |
7291 | intel_mark_page_flip_active(intel_crtc); | |
7c9017e5 | 7292 | intel_ring_advance(ring); |
83d4092b CW |
7293 | return 0; |
7294 | ||
7295 | err_unpin: | |
7296 | intel_unpin_fb_obj(obj); | |
7297 | err: | |
7c9017e5 JB |
7298 | return ret; |
7299 | } | |
7300 | ||
8c9f3aaf JB |
7301 | static int intel_default_queue_flip(struct drm_device *dev, |
7302 | struct drm_crtc *crtc, | |
7303 | struct drm_framebuffer *fb, | |
7304 | struct drm_i915_gem_object *obj) | |
7305 | { | |
7306 | return -ENODEV; | |
7307 | } | |
7308 | ||
6b95a207 KH |
7309 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
7310 | struct drm_framebuffer *fb, | |
7311 | struct drm_pending_vblank_event *event) | |
7312 | { | |
7313 | struct drm_device *dev = crtc->dev; | |
7314 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4a35f83b VS |
7315 | struct drm_framebuffer *old_fb = crtc->fb; |
7316 | struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj; | |
6b95a207 KH |
7317 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7318 | struct intel_unpin_work *work; | |
8c9f3aaf | 7319 | unsigned long flags; |
52e68630 | 7320 | int ret; |
6b95a207 | 7321 | |
e6a595d2 VS |
7322 | /* Can't change pixel format via MI display flips. */ |
7323 | if (fb->pixel_format != crtc->fb->pixel_format) | |
7324 | return -EINVAL; | |
7325 | ||
7326 | /* | |
7327 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
7328 | * Note that pitch changes could also affect these register. | |
7329 | */ | |
7330 | if (INTEL_INFO(dev)->gen > 3 && | |
7331 | (fb->offsets[0] != crtc->fb->offsets[0] || | |
7332 | fb->pitches[0] != crtc->fb->pitches[0])) | |
7333 | return -EINVAL; | |
7334 | ||
6b95a207 KH |
7335 | work = kzalloc(sizeof *work, GFP_KERNEL); |
7336 | if (work == NULL) | |
7337 | return -ENOMEM; | |
7338 | ||
6b95a207 | 7339 | work->event = event; |
b4a98e57 | 7340 | work->crtc = crtc; |
4a35f83b | 7341 | work->old_fb_obj = to_intel_framebuffer(old_fb)->obj; |
6b95a207 KH |
7342 | INIT_WORK(&work->work, intel_unpin_work_fn); |
7343 | ||
7317c75e JB |
7344 | ret = drm_vblank_get(dev, intel_crtc->pipe); |
7345 | if (ret) | |
7346 | goto free_work; | |
7347 | ||
6b95a207 KH |
7348 | /* We borrow the event spin lock for protecting unpin_work */ |
7349 | spin_lock_irqsave(&dev->event_lock, flags); | |
7350 | if (intel_crtc->unpin_work) { | |
7351 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
7352 | kfree(work); | |
7317c75e | 7353 | drm_vblank_put(dev, intel_crtc->pipe); |
468f0b44 CW |
7354 | |
7355 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
6b95a207 KH |
7356 | return -EBUSY; |
7357 | } | |
7358 | intel_crtc->unpin_work = work; | |
7359 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
7360 | ||
b4a98e57 CW |
7361 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
7362 | flush_workqueue(dev_priv->wq); | |
7363 | ||
79158103 CW |
7364 | ret = i915_mutex_lock_interruptible(dev); |
7365 | if (ret) | |
7366 | goto cleanup; | |
6b95a207 | 7367 | |
75dfca80 | 7368 | /* Reference the objects for the scheduled work. */ |
05394f39 CW |
7369 | drm_gem_object_reference(&work->old_fb_obj->base); |
7370 | drm_gem_object_reference(&obj->base); | |
6b95a207 KH |
7371 | |
7372 | crtc->fb = fb; | |
96b099fd | 7373 | |
e1f99ce6 | 7374 | work->pending_flip_obj = obj; |
e1f99ce6 | 7375 | |
4e5359cd SF |
7376 | work->enable_stall_check = true; |
7377 | ||
b4a98e57 | 7378 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 7379 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 7380 | |
8c9f3aaf JB |
7381 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj); |
7382 | if (ret) | |
7383 | goto cleanup_pending; | |
6b95a207 | 7384 | |
7782de3b | 7385 | intel_disable_fbc(dev); |
f047e395 | 7386 | intel_mark_fb_busy(obj); |
6b95a207 KH |
7387 | mutex_unlock(&dev->struct_mutex); |
7388 | ||
e5510fac JB |
7389 | trace_i915_flip_request(intel_crtc->plane, obj); |
7390 | ||
6b95a207 | 7391 | return 0; |
96b099fd | 7392 | |
8c9f3aaf | 7393 | cleanup_pending: |
b4a98e57 | 7394 | atomic_dec(&intel_crtc->unpin_work_count); |
4a35f83b | 7395 | crtc->fb = old_fb; |
05394f39 CW |
7396 | drm_gem_object_unreference(&work->old_fb_obj->base); |
7397 | drm_gem_object_unreference(&obj->base); | |
96b099fd CW |
7398 | mutex_unlock(&dev->struct_mutex); |
7399 | ||
79158103 | 7400 | cleanup: |
96b099fd CW |
7401 | spin_lock_irqsave(&dev->event_lock, flags); |
7402 | intel_crtc->unpin_work = NULL; | |
7403 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
7404 | ||
7317c75e JB |
7405 | drm_vblank_put(dev, intel_crtc->pipe); |
7406 | free_work: | |
96b099fd CW |
7407 | kfree(work); |
7408 | ||
7409 | return ret; | |
6b95a207 KH |
7410 | } |
7411 | ||
f6e5b160 | 7412 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
7413 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
7414 | .load_lut = intel_crtc_load_lut, | |
f6e5b160 CW |
7415 | }; |
7416 | ||
6ed0f796 | 7417 | bool intel_encoder_check_is_cloned(struct intel_encoder *encoder) |
47f1c6c9 | 7418 | { |
6ed0f796 DV |
7419 | struct intel_encoder *other_encoder; |
7420 | struct drm_crtc *crtc = &encoder->new_crtc->base; | |
47f1c6c9 | 7421 | |
6ed0f796 DV |
7422 | if (WARN_ON(!crtc)) |
7423 | return false; | |
7424 | ||
7425 | list_for_each_entry(other_encoder, | |
7426 | &crtc->dev->mode_config.encoder_list, | |
7427 | base.head) { | |
7428 | ||
7429 | if (&other_encoder->new_crtc->base != crtc || | |
7430 | encoder == other_encoder) | |
7431 | continue; | |
7432 | else | |
7433 | return true; | |
f47166d2 CW |
7434 | } |
7435 | ||
6ed0f796 DV |
7436 | return false; |
7437 | } | |
47f1c6c9 | 7438 | |
50f56119 DV |
7439 | static bool intel_encoder_crtc_ok(struct drm_encoder *encoder, |
7440 | struct drm_crtc *crtc) | |
7441 | { | |
7442 | struct drm_device *dev; | |
7443 | struct drm_crtc *tmp; | |
7444 | int crtc_mask = 1; | |
47f1c6c9 | 7445 | |
50f56119 | 7446 | WARN(!crtc, "checking null crtc?\n"); |
47f1c6c9 | 7447 | |
50f56119 | 7448 | dev = crtc->dev; |
47f1c6c9 | 7449 | |
50f56119 DV |
7450 | list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) { |
7451 | if (tmp == crtc) | |
7452 | break; | |
7453 | crtc_mask <<= 1; | |
7454 | } | |
47f1c6c9 | 7455 | |
50f56119 DV |
7456 | if (encoder->possible_crtcs & crtc_mask) |
7457 | return true; | |
7458 | return false; | |
47f1c6c9 | 7459 | } |
79e53945 | 7460 | |
9a935856 DV |
7461 | /** |
7462 | * intel_modeset_update_staged_output_state | |
7463 | * | |
7464 | * Updates the staged output configuration state, e.g. after we've read out the | |
7465 | * current hw state. | |
7466 | */ | |
7467 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) | |
f6e5b160 | 7468 | { |
9a935856 DV |
7469 | struct intel_encoder *encoder; |
7470 | struct intel_connector *connector; | |
f6e5b160 | 7471 | |
9a935856 DV |
7472 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
7473 | base.head) { | |
7474 | connector->new_encoder = | |
7475 | to_intel_encoder(connector->base.encoder); | |
7476 | } | |
f6e5b160 | 7477 | |
9a935856 DV |
7478 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
7479 | base.head) { | |
7480 | encoder->new_crtc = | |
7481 | to_intel_crtc(encoder->base.crtc); | |
7482 | } | |
f6e5b160 CW |
7483 | } |
7484 | ||
9a935856 DV |
7485 | /** |
7486 | * intel_modeset_commit_output_state | |
7487 | * | |
7488 | * This function copies the stage display pipe configuration to the real one. | |
7489 | */ | |
7490 | static void intel_modeset_commit_output_state(struct drm_device *dev) | |
7491 | { | |
7492 | struct intel_encoder *encoder; | |
7493 | struct intel_connector *connector; | |
f6e5b160 | 7494 | |
9a935856 DV |
7495 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
7496 | base.head) { | |
7497 | connector->base.encoder = &connector->new_encoder->base; | |
7498 | } | |
f6e5b160 | 7499 | |
9a935856 DV |
7500 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
7501 | base.head) { | |
7502 | encoder->base.crtc = &encoder->new_crtc->base; | |
7503 | } | |
7504 | } | |
7505 | ||
4e53c2e0 DV |
7506 | static int |
7507 | pipe_config_set_bpp(struct drm_crtc *crtc, | |
7508 | struct drm_framebuffer *fb, | |
7509 | struct intel_crtc_config *pipe_config) | |
7510 | { | |
7511 | struct drm_device *dev = crtc->dev; | |
7512 | struct drm_connector *connector; | |
7513 | int bpp; | |
7514 | ||
d42264b1 DV |
7515 | switch (fb->pixel_format) { |
7516 | case DRM_FORMAT_C8: | |
4e53c2e0 DV |
7517 | bpp = 8*3; /* since we go through a colormap */ |
7518 | break; | |
d42264b1 DV |
7519 | case DRM_FORMAT_XRGB1555: |
7520 | case DRM_FORMAT_ARGB1555: | |
7521 | /* checked in intel_framebuffer_init already */ | |
7522 | if (WARN_ON(INTEL_INFO(dev)->gen > 3)) | |
7523 | return -EINVAL; | |
7524 | case DRM_FORMAT_RGB565: | |
4e53c2e0 DV |
7525 | bpp = 6*3; /* min is 18bpp */ |
7526 | break; | |
d42264b1 DV |
7527 | case DRM_FORMAT_XBGR8888: |
7528 | case DRM_FORMAT_ABGR8888: | |
7529 | /* checked in intel_framebuffer_init already */ | |
7530 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
7531 | return -EINVAL; | |
7532 | case DRM_FORMAT_XRGB8888: | |
7533 | case DRM_FORMAT_ARGB8888: | |
4e53c2e0 DV |
7534 | bpp = 8*3; |
7535 | break; | |
d42264b1 DV |
7536 | case DRM_FORMAT_XRGB2101010: |
7537 | case DRM_FORMAT_ARGB2101010: | |
7538 | case DRM_FORMAT_XBGR2101010: | |
7539 | case DRM_FORMAT_ABGR2101010: | |
7540 | /* checked in intel_framebuffer_init already */ | |
7541 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
baba133a | 7542 | return -EINVAL; |
4e53c2e0 DV |
7543 | bpp = 10*3; |
7544 | break; | |
baba133a | 7545 | /* TODO: gen4+ supports 16 bpc floating point, too. */ |
4e53c2e0 DV |
7546 | default: |
7547 | DRM_DEBUG_KMS("unsupported depth\n"); | |
7548 | return -EINVAL; | |
7549 | } | |
7550 | ||
4e53c2e0 DV |
7551 | pipe_config->pipe_bpp = bpp; |
7552 | ||
7553 | /* Clamp display bpp to EDID value */ | |
7554 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
7555 | head) { | |
7556 | if (connector->encoder && connector->encoder->crtc != crtc) | |
7557 | continue; | |
7558 | ||
7559 | /* Don't use an invalid EDID bpc value */ | |
7560 | if (connector->display_info.bpc && | |
7561 | connector->display_info.bpc * 3 < bpp) { | |
7562 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
7563 | bpp, connector->display_info.bpc*3); | |
7564 | pipe_config->pipe_bpp = connector->display_info.bpc*3; | |
7565 | } | |
7566 | } | |
7567 | ||
7568 | return bpp; | |
7569 | } | |
7570 | ||
b8cecdf5 DV |
7571 | static struct intel_crtc_config * |
7572 | intel_modeset_pipe_config(struct drm_crtc *crtc, | |
4e53c2e0 | 7573 | struct drm_framebuffer *fb, |
b8cecdf5 | 7574 | struct drm_display_mode *mode) |
ee7b9f93 | 7575 | { |
7758a113 | 7576 | struct drm_device *dev = crtc->dev; |
7758a113 DV |
7577 | struct drm_encoder_helper_funcs *encoder_funcs; |
7578 | struct intel_encoder *encoder; | |
b8cecdf5 | 7579 | struct intel_crtc_config *pipe_config; |
4e53c2e0 | 7580 | int plane_bpp; |
ee7b9f93 | 7581 | |
b8cecdf5 DV |
7582 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
7583 | if (!pipe_config) | |
7758a113 DV |
7584 | return ERR_PTR(-ENOMEM); |
7585 | ||
b8cecdf5 DV |
7586 | drm_mode_copy(&pipe_config->adjusted_mode, mode); |
7587 | drm_mode_copy(&pipe_config->requested_mode, mode); | |
7588 | ||
4e53c2e0 DV |
7589 | plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config); |
7590 | if (plane_bpp < 0) | |
7591 | goto fail; | |
7592 | ||
7758a113 DV |
7593 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
7594 | * adjust it according to limitations or connector properties, and also | |
7595 | * a chance to reject the mode entirely. | |
47f1c6c9 | 7596 | */ |
7758a113 DV |
7597 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
7598 | base.head) { | |
47f1c6c9 | 7599 | |
7758a113 DV |
7600 | if (&encoder->new_crtc->base != crtc) |
7601 | continue; | |
7ae89233 DV |
7602 | |
7603 | if (encoder->compute_config) { | |
7604 | if (!(encoder->compute_config(encoder, pipe_config))) { | |
7605 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7606 | goto fail; | |
7607 | } | |
7608 | ||
7609 | continue; | |
7610 | } | |
7611 | ||
7758a113 | 7612 | encoder_funcs = encoder->base.helper_private; |
b8cecdf5 DV |
7613 | if (!(encoder_funcs->mode_fixup(&encoder->base, |
7614 | &pipe_config->requested_mode, | |
7615 | &pipe_config->adjusted_mode))) { | |
7758a113 DV |
7616 | DRM_DEBUG_KMS("Encoder fixup failed\n"); |
7617 | goto fail; | |
7618 | } | |
ee7b9f93 | 7619 | } |
47f1c6c9 | 7620 | |
b8cecdf5 | 7621 | if (!(intel_crtc_compute_config(crtc, pipe_config))) { |
7758a113 DV |
7622 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
7623 | goto fail; | |
ee7b9f93 | 7624 | } |
7758a113 | 7625 | DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id); |
47f1c6c9 | 7626 | |
4e53c2e0 DV |
7627 | pipe_config->dither = pipe_config->pipe_bpp != plane_bpp; |
7628 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", | |
7629 | plane_bpp, pipe_config->pipe_bpp, pipe_config->dither); | |
7630 | ||
b8cecdf5 | 7631 | return pipe_config; |
7758a113 | 7632 | fail: |
b8cecdf5 | 7633 | kfree(pipe_config); |
7758a113 | 7634 | return ERR_PTR(-EINVAL); |
ee7b9f93 | 7635 | } |
47f1c6c9 | 7636 | |
e2e1ed41 DV |
7637 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
7638 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ | |
7639 | static void | |
7640 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, | |
7641 | unsigned *prepare_pipes, unsigned *disable_pipes) | |
79e53945 JB |
7642 | { |
7643 | struct intel_crtc *intel_crtc; | |
e2e1ed41 DV |
7644 | struct drm_device *dev = crtc->dev; |
7645 | struct intel_encoder *encoder; | |
7646 | struct intel_connector *connector; | |
7647 | struct drm_crtc *tmp_crtc; | |
79e53945 | 7648 | |
e2e1ed41 | 7649 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
79e53945 | 7650 | |
e2e1ed41 DV |
7651 | /* Check which crtcs have changed outputs connected to them, these need |
7652 | * to be part of the prepare_pipes mask. We don't (yet) support global | |
7653 | * modeset across multiple crtcs, so modeset_pipes will only have one | |
7654 | * bit set at most. */ | |
7655 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
7656 | base.head) { | |
7657 | if (connector->base.encoder == &connector->new_encoder->base) | |
7658 | continue; | |
79e53945 | 7659 | |
e2e1ed41 DV |
7660 | if (connector->base.encoder) { |
7661 | tmp_crtc = connector->base.encoder->crtc; | |
7662 | ||
7663 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
7664 | } | |
7665 | ||
7666 | if (connector->new_encoder) | |
7667 | *prepare_pipes |= | |
7668 | 1 << connector->new_encoder->new_crtc->pipe; | |
79e53945 JB |
7669 | } |
7670 | ||
e2e1ed41 DV |
7671 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
7672 | base.head) { | |
7673 | if (encoder->base.crtc == &encoder->new_crtc->base) | |
7674 | continue; | |
7675 | ||
7676 | if (encoder->base.crtc) { | |
7677 | tmp_crtc = encoder->base.crtc; | |
7678 | ||
7679 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
7680 | } | |
7681 | ||
7682 | if (encoder->new_crtc) | |
7683 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; | |
80824003 JB |
7684 | } |
7685 | ||
e2e1ed41 DV |
7686 | /* Check for any pipes that will be fully disabled ... */ |
7687 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, | |
7688 | base.head) { | |
7689 | bool used = false; | |
22fd0fab | 7690 | |
e2e1ed41 DV |
7691 | /* Don't try to disable disabled crtcs. */ |
7692 | if (!intel_crtc->base.enabled) | |
7693 | continue; | |
7e7d76c3 | 7694 | |
e2e1ed41 DV |
7695 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
7696 | base.head) { | |
7697 | if (encoder->new_crtc == intel_crtc) | |
7698 | used = true; | |
7699 | } | |
7700 | ||
7701 | if (!used) | |
7702 | *disable_pipes |= 1 << intel_crtc->pipe; | |
7e7d76c3 JB |
7703 | } |
7704 | ||
e2e1ed41 DV |
7705 | |
7706 | /* set_mode is also used to update properties on life display pipes. */ | |
7707 | intel_crtc = to_intel_crtc(crtc); | |
7708 | if (crtc->enabled) | |
7709 | *prepare_pipes |= 1 << intel_crtc->pipe; | |
7710 | ||
7711 | /* We only support modeset on one single crtc, hence we need to do that | |
7712 | * only for the passed in crtc iff we change anything else than just | |
7713 | * disable crtcs. | |
7714 | * | |
7715 | * This is actually not true, to be fully compatible with the old crtc | |
7716 | * helper we automatically disable _any_ output (i.e. doesn't need to be | |
7717 | * connected to the crtc we're modesetting on) if it's disconnected. | |
7718 | * Which is a rather nutty api (since changed the output configuration | |
7719 | * without userspace's explicit request can lead to confusion), but | |
7720 | * alas. Hence we currently need to modeset on all pipes we prepare. */ | |
7721 | if (*prepare_pipes) | |
7722 | *modeset_pipes = *prepare_pipes; | |
7723 | ||
7724 | /* ... and mask these out. */ | |
7725 | *modeset_pipes &= ~(*disable_pipes); | |
7726 | *prepare_pipes &= ~(*disable_pipes); | |
47f1c6c9 | 7727 | } |
79e53945 | 7728 | |
ea9d758d | 7729 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
f6e5b160 | 7730 | { |
ea9d758d | 7731 | struct drm_encoder *encoder; |
f6e5b160 | 7732 | struct drm_device *dev = crtc->dev; |
f6e5b160 | 7733 | |
ea9d758d DV |
7734 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
7735 | if (encoder->crtc == crtc) | |
7736 | return true; | |
7737 | ||
7738 | return false; | |
7739 | } | |
7740 | ||
7741 | static void | |
7742 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) | |
7743 | { | |
7744 | struct intel_encoder *intel_encoder; | |
7745 | struct intel_crtc *intel_crtc; | |
7746 | struct drm_connector *connector; | |
7747 | ||
7748 | list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list, | |
7749 | base.head) { | |
7750 | if (!intel_encoder->base.crtc) | |
7751 | continue; | |
7752 | ||
7753 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); | |
7754 | ||
7755 | if (prepare_pipes & (1 << intel_crtc->pipe)) | |
7756 | intel_encoder->connectors_active = false; | |
7757 | } | |
7758 | ||
7759 | intel_modeset_commit_output_state(dev); | |
7760 | ||
7761 | /* Update computed state. */ | |
7762 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, | |
7763 | base.head) { | |
7764 | intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base); | |
7765 | } | |
7766 | ||
7767 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
7768 | if (!connector->encoder || !connector->encoder->crtc) | |
7769 | continue; | |
7770 | ||
7771 | intel_crtc = to_intel_crtc(connector->encoder->crtc); | |
7772 | ||
7773 | if (prepare_pipes & (1 << intel_crtc->pipe)) { | |
68d34720 DV |
7774 | struct drm_property *dpms_property = |
7775 | dev->mode_config.dpms_property; | |
7776 | ||
ea9d758d | 7777 | connector->dpms = DRM_MODE_DPMS_ON; |
662595df | 7778 | drm_object_property_set_value(&connector->base, |
68d34720 DV |
7779 | dpms_property, |
7780 | DRM_MODE_DPMS_ON); | |
ea9d758d DV |
7781 | |
7782 | intel_encoder = to_intel_encoder(connector->encoder); | |
7783 | intel_encoder->connectors_active = true; | |
7784 | } | |
7785 | } | |
7786 | ||
7787 | } | |
7788 | ||
25c5b266 DV |
7789 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
7790 | list_for_each_entry((intel_crtc), \ | |
7791 | &(dev)->mode_config.crtc_list, \ | |
7792 | base.head) \ | |
7793 | if (mask & (1 <<(intel_crtc)->pipe)) \ | |
7794 | ||
0e8ffe1b DV |
7795 | static bool |
7796 | intel_pipe_config_compare(struct intel_crtc_config *current_config, | |
7797 | struct intel_crtc_config *pipe_config) | |
7798 | { | |
88adfff1 DV |
7799 | if (current_config->has_pch_encoder != pipe_config->has_pch_encoder) { |
7800 | DRM_ERROR("mismatch in has_pch_encoder " | |
7801 | "(expected %i, found %i)\n", | |
7802 | current_config->has_pch_encoder, | |
7803 | pipe_config->has_pch_encoder); | |
7804 | return false; | |
7805 | } | |
7806 | ||
0e8ffe1b DV |
7807 | return true; |
7808 | } | |
7809 | ||
b980514c | 7810 | void |
8af6cf88 DV |
7811 | intel_modeset_check_state(struct drm_device *dev) |
7812 | { | |
0e8ffe1b | 7813 | drm_i915_private_t *dev_priv = dev->dev_private; |
8af6cf88 DV |
7814 | struct intel_crtc *crtc; |
7815 | struct intel_encoder *encoder; | |
7816 | struct intel_connector *connector; | |
0e8ffe1b | 7817 | struct intel_crtc_config pipe_config; |
8af6cf88 DV |
7818 | |
7819 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
7820 | base.head) { | |
7821 | /* This also checks the encoder/connector hw state with the | |
7822 | * ->get_hw_state callbacks. */ | |
7823 | intel_connector_check_state(connector); | |
7824 | ||
7825 | WARN(&connector->new_encoder->base != connector->base.encoder, | |
7826 | "connector's staged encoder doesn't match current encoder\n"); | |
7827 | } | |
7828 | ||
7829 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
7830 | base.head) { | |
7831 | bool enabled = false; | |
7832 | bool active = false; | |
7833 | enum pipe pipe, tracked_pipe; | |
7834 | ||
7835 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
7836 | encoder->base.base.id, | |
7837 | drm_get_encoder_name(&encoder->base)); | |
7838 | ||
7839 | WARN(&encoder->new_crtc->base != encoder->base.crtc, | |
7840 | "encoder's stage crtc doesn't match current crtc\n"); | |
7841 | WARN(encoder->connectors_active && !encoder->base.crtc, | |
7842 | "encoder's active_connectors set, but no crtc\n"); | |
7843 | ||
7844 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
7845 | base.head) { | |
7846 | if (connector->base.encoder != &encoder->base) | |
7847 | continue; | |
7848 | enabled = true; | |
7849 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) | |
7850 | active = true; | |
7851 | } | |
7852 | WARN(!!encoder->base.crtc != enabled, | |
7853 | "encoder's enabled state mismatch " | |
7854 | "(expected %i, found %i)\n", | |
7855 | !!encoder->base.crtc, enabled); | |
7856 | WARN(active && !encoder->base.crtc, | |
7857 | "active encoder with no crtc\n"); | |
7858 | ||
7859 | WARN(encoder->connectors_active != active, | |
7860 | "encoder's computed active state doesn't match tracked active state " | |
7861 | "(expected %i, found %i)\n", active, encoder->connectors_active); | |
7862 | ||
7863 | active = encoder->get_hw_state(encoder, &pipe); | |
7864 | WARN(active != encoder->connectors_active, | |
7865 | "encoder's hw state doesn't match sw tracking " | |
7866 | "(expected %i, found %i)\n", | |
7867 | encoder->connectors_active, active); | |
7868 | ||
7869 | if (!encoder->base.crtc) | |
7870 | continue; | |
7871 | ||
7872 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; | |
7873 | WARN(active && pipe != tracked_pipe, | |
7874 | "active encoder's pipe doesn't match" | |
7875 | "(expected %i, found %i)\n", | |
7876 | tracked_pipe, pipe); | |
7877 | ||
7878 | } | |
7879 | ||
7880 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
7881 | base.head) { | |
7882 | bool enabled = false; | |
7883 | bool active = false; | |
7884 | ||
7885 | DRM_DEBUG_KMS("[CRTC:%d]\n", | |
7886 | crtc->base.base.id); | |
7887 | ||
7888 | WARN(crtc->active && !crtc->base.enabled, | |
7889 | "active crtc, but not enabled in sw tracking\n"); | |
7890 | ||
7891 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
7892 | base.head) { | |
7893 | if (encoder->base.crtc != &crtc->base) | |
7894 | continue; | |
7895 | enabled = true; | |
7896 | if (encoder->connectors_active) | |
7897 | active = true; | |
7898 | } | |
7899 | WARN(active != crtc->active, | |
7900 | "crtc's computed active state doesn't match tracked active state " | |
7901 | "(expected %i, found %i)\n", active, crtc->active); | |
7902 | WARN(enabled != crtc->base.enabled, | |
7903 | "crtc's computed enabled state doesn't match tracked enabled state " | |
7904 | "(expected %i, found %i)\n", enabled, crtc->base.enabled); | |
7905 | ||
88adfff1 | 7906 | memset(&pipe_config, 0, sizeof(pipe_config)); |
0e8ffe1b DV |
7907 | active = dev_priv->display.get_pipe_config(crtc, |
7908 | &pipe_config); | |
7909 | WARN(crtc->active != active, | |
7910 | "crtc active state doesn't match with hw state " | |
7911 | "(expected %i, found %i)\n", crtc->active, active); | |
7912 | ||
7913 | WARN(active && | |
7914 | !intel_pipe_config_compare(&crtc->config, &pipe_config), | |
7915 | "pipe state doesn't match!\n"); | |
8af6cf88 DV |
7916 | } |
7917 | } | |
7918 | ||
f30da187 DV |
7919 | static int __intel_set_mode(struct drm_crtc *crtc, |
7920 | struct drm_display_mode *mode, | |
7921 | int x, int y, struct drm_framebuffer *fb) | |
a6778b3c DV |
7922 | { |
7923 | struct drm_device *dev = crtc->dev; | |
dbf2b54e | 7924 | drm_i915_private_t *dev_priv = dev->dev_private; |
b8cecdf5 DV |
7925 | struct drm_display_mode *saved_mode, *saved_hwmode; |
7926 | struct intel_crtc_config *pipe_config = NULL; | |
25c5b266 DV |
7927 | struct intel_crtc *intel_crtc; |
7928 | unsigned disable_pipes, prepare_pipes, modeset_pipes; | |
c0c36b94 | 7929 | int ret = 0; |
a6778b3c | 7930 | |
3ac18232 | 7931 | saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL); |
c0c36b94 CW |
7932 | if (!saved_mode) |
7933 | return -ENOMEM; | |
3ac18232 | 7934 | saved_hwmode = saved_mode + 1; |
a6778b3c | 7935 | |
e2e1ed41 | 7936 | intel_modeset_affected_pipes(crtc, &modeset_pipes, |
25c5b266 DV |
7937 | &prepare_pipes, &disable_pipes); |
7938 | ||
3ac18232 TG |
7939 | *saved_hwmode = crtc->hwmode; |
7940 | *saved_mode = crtc->mode; | |
a6778b3c | 7941 | |
25c5b266 DV |
7942 | /* Hack: Because we don't (yet) support global modeset on multiple |
7943 | * crtcs, we don't keep track of the new mode for more than one crtc. | |
7944 | * Hence simply check whether any bit is set in modeset_pipes in all the | |
7945 | * pieces of code that are not yet converted to deal with mutliple crtcs | |
7946 | * changing their mode at the same time. */ | |
25c5b266 | 7947 | if (modeset_pipes) { |
4e53c2e0 | 7948 | pipe_config = intel_modeset_pipe_config(crtc, fb, mode); |
b8cecdf5 DV |
7949 | if (IS_ERR(pipe_config)) { |
7950 | ret = PTR_ERR(pipe_config); | |
7951 | pipe_config = NULL; | |
7952 | ||
3ac18232 | 7953 | goto out; |
25c5b266 | 7954 | } |
25c5b266 | 7955 | } |
a6778b3c | 7956 | |
460da916 DV |
7957 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", |
7958 | modeset_pipes, prepare_pipes, disable_pipes); | |
7959 | ||
7960 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) | |
7961 | intel_crtc_disable(&intel_crtc->base); | |
7962 | ||
ea9d758d DV |
7963 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
7964 | if (intel_crtc->base.enabled) | |
7965 | dev_priv->display.crtc_disable(&intel_crtc->base); | |
7966 | } | |
a6778b3c | 7967 | |
6c4c86f5 DV |
7968 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
7969 | * to set it here already despite that we pass it down the callchain. | |
f6e5b160 | 7970 | */ |
b8cecdf5 | 7971 | if (modeset_pipes) { |
25c5b266 | 7972 | crtc->mode = *mode; |
b8cecdf5 DV |
7973 | /* mode_set/enable/disable functions rely on a correct pipe |
7974 | * config. */ | |
7975 | to_intel_crtc(crtc)->config = *pipe_config; | |
7976 | } | |
7758a113 | 7977 | |
ea9d758d DV |
7978 | /* Only after disabling all output pipelines that will be changed can we |
7979 | * update the the output configuration. */ | |
7980 | intel_modeset_update_state(dev, prepare_pipes); | |
f6e5b160 | 7981 | |
47fab737 DV |
7982 | if (dev_priv->display.modeset_global_resources) |
7983 | dev_priv->display.modeset_global_resources(dev); | |
7984 | ||
a6778b3c DV |
7985 | /* Set up the DPLL and any encoders state that needs to adjust or depend |
7986 | * on the DPLL. | |
f6e5b160 | 7987 | */ |
25c5b266 | 7988 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
c0c36b94 | 7989 | ret = intel_crtc_mode_set(&intel_crtc->base, |
c0c36b94 CW |
7990 | x, y, fb); |
7991 | if (ret) | |
7992 | goto done; | |
a6778b3c DV |
7993 | } |
7994 | ||
7995 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ | |
25c5b266 DV |
7996 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) |
7997 | dev_priv->display.crtc_enable(&intel_crtc->base); | |
a6778b3c | 7998 | |
25c5b266 DV |
7999 | if (modeset_pipes) { |
8000 | /* Store real post-adjustment hardware mode. */ | |
b8cecdf5 | 8001 | crtc->hwmode = pipe_config->adjusted_mode; |
a6778b3c | 8002 | |
25c5b266 DV |
8003 | /* Calculate and store various constants which |
8004 | * are later needed by vblank and swap-completion | |
8005 | * timestamping. They are derived from true hwmode. | |
8006 | */ | |
8007 | drm_calc_timestamping_constants(crtc); | |
8008 | } | |
a6778b3c DV |
8009 | |
8010 | /* FIXME: add subpixel order */ | |
8011 | done: | |
c0c36b94 | 8012 | if (ret && crtc->enabled) { |
3ac18232 TG |
8013 | crtc->hwmode = *saved_hwmode; |
8014 | crtc->mode = *saved_mode; | |
a6778b3c DV |
8015 | } |
8016 | ||
3ac18232 | 8017 | out: |
b8cecdf5 | 8018 | kfree(pipe_config); |
3ac18232 | 8019 | kfree(saved_mode); |
a6778b3c | 8020 | return ret; |
f6e5b160 CW |
8021 | } |
8022 | ||
f30da187 DV |
8023 | int intel_set_mode(struct drm_crtc *crtc, |
8024 | struct drm_display_mode *mode, | |
8025 | int x, int y, struct drm_framebuffer *fb) | |
8026 | { | |
8027 | int ret; | |
8028 | ||
8029 | ret = __intel_set_mode(crtc, mode, x, y, fb); | |
8030 | ||
8031 | if (ret == 0) | |
8032 | intel_modeset_check_state(crtc->dev); | |
8033 | ||
8034 | return ret; | |
8035 | } | |
8036 | ||
c0c36b94 CW |
8037 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
8038 | { | |
8039 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb); | |
8040 | } | |
8041 | ||
25c5b266 DV |
8042 | #undef for_each_intel_crtc_masked |
8043 | ||
d9e55608 DV |
8044 | static void intel_set_config_free(struct intel_set_config *config) |
8045 | { | |
8046 | if (!config) | |
8047 | return; | |
8048 | ||
1aa4b628 DV |
8049 | kfree(config->save_connector_encoders); |
8050 | kfree(config->save_encoder_crtcs); | |
d9e55608 DV |
8051 | kfree(config); |
8052 | } | |
8053 | ||
85f9eb71 DV |
8054 | static int intel_set_config_save_state(struct drm_device *dev, |
8055 | struct intel_set_config *config) | |
8056 | { | |
85f9eb71 DV |
8057 | struct drm_encoder *encoder; |
8058 | struct drm_connector *connector; | |
8059 | int count; | |
8060 | ||
1aa4b628 DV |
8061 | config->save_encoder_crtcs = |
8062 | kcalloc(dev->mode_config.num_encoder, | |
8063 | sizeof(struct drm_crtc *), GFP_KERNEL); | |
8064 | if (!config->save_encoder_crtcs) | |
85f9eb71 DV |
8065 | return -ENOMEM; |
8066 | ||
1aa4b628 DV |
8067 | config->save_connector_encoders = |
8068 | kcalloc(dev->mode_config.num_connector, | |
8069 | sizeof(struct drm_encoder *), GFP_KERNEL); | |
8070 | if (!config->save_connector_encoders) | |
85f9eb71 DV |
8071 | return -ENOMEM; |
8072 | ||
8073 | /* Copy data. Note that driver private data is not affected. | |
8074 | * Should anything bad happen only the expected state is | |
8075 | * restored, not the drivers personal bookkeeping. | |
8076 | */ | |
85f9eb71 DV |
8077 | count = 0; |
8078 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
1aa4b628 | 8079 | config->save_encoder_crtcs[count++] = encoder->crtc; |
85f9eb71 DV |
8080 | } |
8081 | ||
8082 | count = 0; | |
8083 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1aa4b628 | 8084 | config->save_connector_encoders[count++] = connector->encoder; |
85f9eb71 DV |
8085 | } |
8086 | ||
8087 | return 0; | |
8088 | } | |
8089 | ||
8090 | static void intel_set_config_restore_state(struct drm_device *dev, | |
8091 | struct intel_set_config *config) | |
8092 | { | |
9a935856 DV |
8093 | struct intel_encoder *encoder; |
8094 | struct intel_connector *connector; | |
85f9eb71 DV |
8095 | int count; |
8096 | ||
85f9eb71 | 8097 | count = 0; |
9a935856 DV |
8098 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
8099 | encoder->new_crtc = | |
8100 | to_intel_crtc(config->save_encoder_crtcs[count++]); | |
85f9eb71 DV |
8101 | } |
8102 | ||
8103 | count = 0; | |
9a935856 DV |
8104 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { |
8105 | connector->new_encoder = | |
8106 | to_intel_encoder(config->save_connector_encoders[count++]); | |
85f9eb71 DV |
8107 | } |
8108 | } | |
8109 | ||
5e2b584e DV |
8110 | static void |
8111 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, | |
8112 | struct intel_set_config *config) | |
8113 | { | |
8114 | ||
8115 | /* We should be able to check here if the fb has the same properties | |
8116 | * and then just flip_or_move it */ | |
8117 | if (set->crtc->fb != set->fb) { | |
8118 | /* If we have no fb then treat it as a full mode set */ | |
8119 | if (set->crtc->fb == NULL) { | |
8120 | DRM_DEBUG_KMS("crtc has no fb, full mode set\n"); | |
8121 | config->mode_changed = true; | |
8122 | } else if (set->fb == NULL) { | |
8123 | config->mode_changed = true; | |
72f4901e DV |
8124 | } else if (set->fb->pixel_format != |
8125 | set->crtc->fb->pixel_format) { | |
5e2b584e DV |
8126 | config->mode_changed = true; |
8127 | } else | |
8128 | config->fb_changed = true; | |
8129 | } | |
8130 | ||
835c5873 | 8131 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
5e2b584e DV |
8132 | config->fb_changed = true; |
8133 | ||
8134 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { | |
8135 | DRM_DEBUG_KMS("modes are different, full mode set\n"); | |
8136 | drm_mode_debug_printmodeline(&set->crtc->mode); | |
8137 | drm_mode_debug_printmodeline(set->mode); | |
8138 | config->mode_changed = true; | |
8139 | } | |
8140 | } | |
8141 | ||
2e431051 | 8142 | static int |
9a935856 DV |
8143 | intel_modeset_stage_output_state(struct drm_device *dev, |
8144 | struct drm_mode_set *set, | |
8145 | struct intel_set_config *config) | |
50f56119 | 8146 | { |
85f9eb71 | 8147 | struct drm_crtc *new_crtc; |
9a935856 DV |
8148 | struct intel_connector *connector; |
8149 | struct intel_encoder *encoder; | |
2e431051 | 8150 | int count, ro; |
50f56119 | 8151 | |
9abdda74 | 8152 | /* The upper layers ensure that we either disable a crtc or have a list |
9a935856 DV |
8153 | * of connectors. For paranoia, double-check this. */ |
8154 | WARN_ON(!set->fb && (set->num_connectors != 0)); | |
8155 | WARN_ON(set->fb && (set->num_connectors == 0)); | |
8156 | ||
50f56119 | 8157 | count = 0; |
9a935856 DV |
8158 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8159 | base.head) { | |
8160 | /* Otherwise traverse passed in connector list and get encoders | |
8161 | * for them. */ | |
50f56119 | 8162 | for (ro = 0; ro < set->num_connectors; ro++) { |
9a935856 DV |
8163 | if (set->connectors[ro] == &connector->base) { |
8164 | connector->new_encoder = connector->encoder; | |
50f56119 DV |
8165 | break; |
8166 | } | |
8167 | } | |
8168 | ||
9a935856 DV |
8169 | /* If we disable the crtc, disable all its connectors. Also, if |
8170 | * the connector is on the changing crtc but not on the new | |
8171 | * connector list, disable it. */ | |
8172 | if ((!set->fb || ro == set->num_connectors) && | |
8173 | connector->base.encoder && | |
8174 | connector->base.encoder->crtc == set->crtc) { | |
8175 | connector->new_encoder = NULL; | |
8176 | ||
8177 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", | |
8178 | connector->base.base.id, | |
8179 | drm_get_connector_name(&connector->base)); | |
8180 | } | |
8181 | ||
8182 | ||
8183 | if (&connector->new_encoder->base != connector->base.encoder) { | |
50f56119 | 8184 | DRM_DEBUG_KMS("encoder changed, full mode switch\n"); |
5e2b584e | 8185 | config->mode_changed = true; |
50f56119 DV |
8186 | } |
8187 | } | |
9a935856 | 8188 | /* connector->new_encoder is now updated for all connectors. */ |
50f56119 | 8189 | |
9a935856 | 8190 | /* Update crtc of enabled connectors. */ |
50f56119 | 8191 | count = 0; |
9a935856 DV |
8192 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8193 | base.head) { | |
8194 | if (!connector->new_encoder) | |
50f56119 DV |
8195 | continue; |
8196 | ||
9a935856 | 8197 | new_crtc = connector->new_encoder->base.crtc; |
50f56119 DV |
8198 | |
8199 | for (ro = 0; ro < set->num_connectors; ro++) { | |
9a935856 | 8200 | if (set->connectors[ro] == &connector->base) |
50f56119 DV |
8201 | new_crtc = set->crtc; |
8202 | } | |
8203 | ||
8204 | /* Make sure the new CRTC will work with the encoder */ | |
9a935856 DV |
8205 | if (!intel_encoder_crtc_ok(&connector->new_encoder->base, |
8206 | new_crtc)) { | |
5e2b584e | 8207 | return -EINVAL; |
50f56119 | 8208 | } |
9a935856 DV |
8209 | connector->encoder->new_crtc = to_intel_crtc(new_crtc); |
8210 | ||
8211 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", | |
8212 | connector->base.base.id, | |
8213 | drm_get_connector_name(&connector->base), | |
8214 | new_crtc->base.id); | |
8215 | } | |
8216 | ||
8217 | /* Check for any encoders that needs to be disabled. */ | |
8218 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
8219 | base.head) { | |
8220 | list_for_each_entry(connector, | |
8221 | &dev->mode_config.connector_list, | |
8222 | base.head) { | |
8223 | if (connector->new_encoder == encoder) { | |
8224 | WARN_ON(!connector->new_encoder->new_crtc); | |
8225 | ||
8226 | goto next_encoder; | |
8227 | } | |
8228 | } | |
8229 | encoder->new_crtc = NULL; | |
8230 | next_encoder: | |
8231 | /* Only now check for crtc changes so we don't miss encoders | |
8232 | * that will be disabled. */ | |
8233 | if (&encoder->new_crtc->base != encoder->base.crtc) { | |
50f56119 | 8234 | DRM_DEBUG_KMS("crtc changed, full mode switch\n"); |
5e2b584e | 8235 | config->mode_changed = true; |
50f56119 DV |
8236 | } |
8237 | } | |
9a935856 | 8238 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
50f56119 | 8239 | |
2e431051 DV |
8240 | return 0; |
8241 | } | |
8242 | ||
8243 | static int intel_crtc_set_config(struct drm_mode_set *set) | |
8244 | { | |
8245 | struct drm_device *dev; | |
2e431051 DV |
8246 | struct drm_mode_set save_set; |
8247 | struct intel_set_config *config; | |
8248 | int ret; | |
2e431051 | 8249 | |
8d3e375e DV |
8250 | BUG_ON(!set); |
8251 | BUG_ON(!set->crtc); | |
8252 | BUG_ON(!set->crtc->helper_private); | |
2e431051 | 8253 | |
7e53f3a4 DV |
8254 | /* Enforce sane interface api - has been abused by the fb helper. */ |
8255 | BUG_ON(!set->mode && set->fb); | |
8256 | BUG_ON(set->fb && set->num_connectors == 0); | |
431e50f7 | 8257 | |
2e431051 DV |
8258 | if (set->fb) { |
8259 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", | |
8260 | set->crtc->base.id, set->fb->base.id, | |
8261 | (int)set->num_connectors, set->x, set->y); | |
8262 | } else { | |
8263 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); | |
2e431051 DV |
8264 | } |
8265 | ||
8266 | dev = set->crtc->dev; | |
8267 | ||
8268 | ret = -ENOMEM; | |
8269 | config = kzalloc(sizeof(*config), GFP_KERNEL); | |
8270 | if (!config) | |
8271 | goto out_config; | |
8272 | ||
8273 | ret = intel_set_config_save_state(dev, config); | |
8274 | if (ret) | |
8275 | goto out_config; | |
8276 | ||
8277 | save_set.crtc = set->crtc; | |
8278 | save_set.mode = &set->crtc->mode; | |
8279 | save_set.x = set->crtc->x; | |
8280 | save_set.y = set->crtc->y; | |
8281 | save_set.fb = set->crtc->fb; | |
8282 | ||
8283 | /* Compute whether we need a full modeset, only an fb base update or no | |
8284 | * change at all. In the future we might also check whether only the | |
8285 | * mode changed, e.g. for LVDS where we only change the panel fitter in | |
8286 | * such cases. */ | |
8287 | intel_set_config_compute_mode_changes(set, config); | |
8288 | ||
9a935856 | 8289 | ret = intel_modeset_stage_output_state(dev, set, config); |
2e431051 DV |
8290 | if (ret) |
8291 | goto fail; | |
8292 | ||
5e2b584e | 8293 | if (config->mode_changed) { |
87f1faa6 | 8294 | if (set->mode) { |
50f56119 DV |
8295 | DRM_DEBUG_KMS("attempting to set mode from" |
8296 | " userspace\n"); | |
8297 | drm_mode_debug_printmodeline(set->mode); | |
87f1faa6 DV |
8298 | } |
8299 | ||
c0c36b94 CW |
8300 | ret = intel_set_mode(set->crtc, set->mode, |
8301 | set->x, set->y, set->fb); | |
8302 | if (ret) { | |
8303 | DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n", | |
8304 | set->crtc->base.id, ret); | |
87f1faa6 DV |
8305 | goto fail; |
8306 | } | |
5e2b584e | 8307 | } else if (config->fb_changed) { |
4878cae2 VS |
8308 | intel_crtc_wait_for_pending_flips(set->crtc); |
8309 | ||
4f660f49 | 8310 | ret = intel_pipe_set_base(set->crtc, |
94352cf9 | 8311 | set->x, set->y, set->fb); |
50f56119 DV |
8312 | } |
8313 | ||
d9e55608 DV |
8314 | intel_set_config_free(config); |
8315 | ||
50f56119 DV |
8316 | return 0; |
8317 | ||
8318 | fail: | |
85f9eb71 | 8319 | intel_set_config_restore_state(dev, config); |
50f56119 DV |
8320 | |
8321 | /* Try to restore the config */ | |
5e2b584e | 8322 | if (config->mode_changed && |
c0c36b94 CW |
8323 | intel_set_mode(save_set.crtc, save_set.mode, |
8324 | save_set.x, save_set.y, save_set.fb)) | |
50f56119 DV |
8325 | DRM_ERROR("failed to restore config after modeset failure\n"); |
8326 | ||
d9e55608 DV |
8327 | out_config: |
8328 | intel_set_config_free(config); | |
50f56119 DV |
8329 | return ret; |
8330 | } | |
f6e5b160 CW |
8331 | |
8332 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
f6e5b160 CW |
8333 | .cursor_set = intel_crtc_cursor_set, |
8334 | .cursor_move = intel_crtc_cursor_move, | |
8335 | .gamma_set = intel_crtc_gamma_set, | |
50f56119 | 8336 | .set_config = intel_crtc_set_config, |
f6e5b160 CW |
8337 | .destroy = intel_crtc_destroy, |
8338 | .page_flip = intel_crtc_page_flip, | |
8339 | }; | |
8340 | ||
79f689aa PZ |
8341 | static void intel_cpu_pll_init(struct drm_device *dev) |
8342 | { | |
affa9354 | 8343 | if (HAS_DDI(dev)) |
79f689aa PZ |
8344 | intel_ddi_pll_init(dev); |
8345 | } | |
8346 | ||
ee7b9f93 JB |
8347 | static void intel_pch_pll_init(struct drm_device *dev) |
8348 | { | |
8349 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8350 | int i; | |
8351 | ||
8352 | if (dev_priv->num_pch_pll == 0) { | |
8353 | DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n"); | |
8354 | return; | |
8355 | } | |
8356 | ||
8357 | for (i = 0; i < dev_priv->num_pch_pll; i++) { | |
8358 | dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i); | |
8359 | dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i); | |
8360 | dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i); | |
8361 | } | |
8362 | } | |
8363 | ||
b358d0a6 | 8364 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 8365 | { |
22fd0fab | 8366 | drm_i915_private_t *dev_priv = dev->dev_private; |
79e53945 JB |
8367 | struct intel_crtc *intel_crtc; |
8368 | int i; | |
8369 | ||
8370 | intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); | |
8371 | if (intel_crtc == NULL) | |
8372 | return; | |
8373 | ||
8374 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); | |
8375 | ||
8376 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
8377 | for (i = 0; i < 256; i++) { |
8378 | intel_crtc->lut_r[i] = i; | |
8379 | intel_crtc->lut_g[i] = i; | |
8380 | intel_crtc->lut_b[i] = i; | |
8381 | } | |
8382 | ||
80824003 JB |
8383 | /* Swap pipes & planes for FBC on pre-965 */ |
8384 | intel_crtc->pipe = pipe; | |
8385 | intel_crtc->plane = pipe; | |
a5c961d1 | 8386 | intel_crtc->cpu_transcoder = pipe; |
e2e767ab | 8387 | if (IS_MOBILE(dev) && IS_GEN3(dev)) { |
28c97730 | 8388 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 8389 | intel_crtc->plane = !pipe; |
80824003 JB |
8390 | } |
8391 | ||
22fd0fab JB |
8392 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
8393 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
8394 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
8395 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
8396 | ||
79e53945 | 8397 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
79e53945 JB |
8398 | } |
8399 | ||
08d7b3d1 | 8400 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 8401 | struct drm_file *file) |
08d7b3d1 | 8402 | { |
08d7b3d1 | 8403 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
c05422d5 DV |
8404 | struct drm_mode_object *drmmode_obj; |
8405 | struct intel_crtc *crtc; | |
08d7b3d1 | 8406 | |
1cff8f6b DV |
8407 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
8408 | return -ENODEV; | |
08d7b3d1 | 8409 | |
c05422d5 DV |
8410 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
8411 | DRM_MODE_OBJECT_CRTC); | |
08d7b3d1 | 8412 | |
c05422d5 | 8413 | if (!drmmode_obj) { |
08d7b3d1 CW |
8414 | DRM_ERROR("no such CRTC id\n"); |
8415 | return -EINVAL; | |
8416 | } | |
8417 | ||
c05422d5 DV |
8418 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
8419 | pipe_from_crtc_id->pipe = crtc->pipe; | |
08d7b3d1 | 8420 | |
c05422d5 | 8421 | return 0; |
08d7b3d1 CW |
8422 | } |
8423 | ||
66a9278e | 8424 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 8425 | { |
66a9278e DV |
8426 | struct drm_device *dev = encoder->base.dev; |
8427 | struct intel_encoder *source_encoder; | |
79e53945 | 8428 | int index_mask = 0; |
79e53945 JB |
8429 | int entry = 0; |
8430 | ||
66a9278e DV |
8431 | list_for_each_entry(source_encoder, |
8432 | &dev->mode_config.encoder_list, base.head) { | |
8433 | ||
8434 | if (encoder == source_encoder) | |
79e53945 | 8435 | index_mask |= (1 << entry); |
66a9278e DV |
8436 | |
8437 | /* Intel hw has only one MUX where enocoders could be cloned. */ | |
8438 | if (encoder->cloneable && source_encoder->cloneable) | |
8439 | index_mask |= (1 << entry); | |
8440 | ||
79e53945 JB |
8441 | entry++; |
8442 | } | |
4ef69c7a | 8443 | |
79e53945 JB |
8444 | return index_mask; |
8445 | } | |
8446 | ||
4d302442 CW |
8447 | static bool has_edp_a(struct drm_device *dev) |
8448 | { | |
8449 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8450 | ||
8451 | if (!IS_MOBILE(dev)) | |
8452 | return false; | |
8453 | ||
8454 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
8455 | return false; | |
8456 | ||
8457 | if (IS_GEN5(dev) && | |
8458 | (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE)) | |
8459 | return false; | |
8460 | ||
8461 | return true; | |
8462 | } | |
8463 | ||
79e53945 JB |
8464 | static void intel_setup_outputs(struct drm_device *dev) |
8465 | { | |
725e30ad | 8466 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 8467 | struct intel_encoder *encoder; |
cb0953d7 | 8468 | bool dpd_is_edp = false; |
f3cfcba6 | 8469 | bool has_lvds; |
79e53945 | 8470 | |
f3cfcba6 | 8471 | has_lvds = intel_lvds_init(dev); |
c5d1b51d CW |
8472 | if (!has_lvds && !HAS_PCH_SPLIT(dev)) { |
8473 | /* disable the panel fitter on everything but LVDS */ | |
8474 | I915_WRITE(PFIT_CONTROL, 0); | |
8475 | } | |
79e53945 | 8476 | |
affa9354 | 8477 | if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES))) |
79935fca | 8478 | intel_crt_init(dev); |
cb0953d7 | 8479 | |
affa9354 | 8480 | if (HAS_DDI(dev)) { |
0e72a5b5 ED |
8481 | int found; |
8482 | ||
8483 | /* Haswell uses DDI functions to detect digital outputs */ | |
8484 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; | |
8485 | /* DDI A only supports eDP */ | |
8486 | if (found) | |
8487 | intel_ddi_init(dev, PORT_A); | |
8488 | ||
8489 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
8490 | * register */ | |
8491 | found = I915_READ(SFUSE_STRAP); | |
8492 | ||
8493 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
8494 | intel_ddi_init(dev, PORT_B); | |
8495 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
8496 | intel_ddi_init(dev, PORT_C); | |
8497 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
8498 | intel_ddi_init(dev, PORT_D); | |
8499 | } else if (HAS_PCH_SPLIT(dev)) { | |
cb0953d7 | 8500 | int found; |
270b3042 DV |
8501 | dpd_is_edp = intel_dpd_is_edp(dev); |
8502 | ||
8503 | if (has_edp_a(dev)) | |
8504 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 8505 | |
dc0fa718 | 8506 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 8507 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 8508 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 | 8509 | if (!found) |
e2debe91 | 8510 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 8511 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 8512 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
8513 | } |
8514 | ||
dc0fa718 | 8515 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 8516 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 8517 | |
dc0fa718 | 8518 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 8519 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 8520 | |
5eb08b69 | 8521 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 8522 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 8523 | |
270b3042 | 8524 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 8525 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
4a87d65d | 8526 | } else if (IS_VALLEYVIEW(dev)) { |
19c03924 | 8527 | /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */ |
67cfc203 VS |
8528 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED) |
8529 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); | |
19c03924 | 8530 | |
dc0fa718 | 8531 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) { |
e2debe91 PZ |
8532 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, |
8533 | PORT_B); | |
67cfc203 VS |
8534 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED) |
8535 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); | |
4a87d65d | 8536 | } |
103a196f | 8537 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 8538 | bool found = false; |
7d57382e | 8539 | |
e2debe91 | 8540 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 8541 | DRM_DEBUG_KMS("probing SDVOB\n"); |
e2debe91 | 8542 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
b01f2c3a JB |
8543 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
8544 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
e2debe91 | 8545 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 8546 | } |
27185ae1 | 8547 | |
b01f2c3a JB |
8548 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) { |
8549 | DRM_DEBUG_KMS("probing DP_B\n"); | |
ab9d7c30 | 8550 | intel_dp_init(dev, DP_B, PORT_B); |
b01f2c3a | 8551 | } |
725e30ad | 8552 | } |
13520b05 KH |
8553 | |
8554 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 8555 | |
e2debe91 | 8556 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 8557 | DRM_DEBUG_KMS("probing SDVOC\n"); |
e2debe91 | 8558 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
b01f2c3a | 8559 | } |
27185ae1 | 8560 | |
e2debe91 | 8561 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 8562 | |
b01f2c3a JB |
8563 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
8564 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
e2debe91 | 8565 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a JB |
8566 | } |
8567 | if (SUPPORTS_INTEGRATED_DP(dev)) { | |
8568 | DRM_DEBUG_KMS("probing DP_C\n"); | |
ab9d7c30 | 8569 | intel_dp_init(dev, DP_C, PORT_C); |
b01f2c3a | 8570 | } |
725e30ad | 8571 | } |
27185ae1 | 8572 | |
b01f2c3a JB |
8573 | if (SUPPORTS_INTEGRATED_DP(dev) && |
8574 | (I915_READ(DP_D) & DP_DETECTED)) { | |
8575 | DRM_DEBUG_KMS("probing DP_D\n"); | |
ab9d7c30 | 8576 | intel_dp_init(dev, DP_D, PORT_D); |
b01f2c3a | 8577 | } |
bad720ff | 8578 | } else if (IS_GEN2(dev)) |
79e53945 JB |
8579 | intel_dvo_init(dev); |
8580 | ||
103a196f | 8581 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
8582 | intel_tv_init(dev); |
8583 | ||
4ef69c7a CW |
8584 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
8585 | encoder->base.possible_crtcs = encoder->crtc_mask; | |
8586 | encoder->base.possible_clones = | |
66a9278e | 8587 | intel_encoder_clones(encoder); |
79e53945 | 8588 | } |
47356eb6 | 8589 | |
dde86e2d | 8590 | intel_init_pch_refclk(dev); |
270b3042 DV |
8591 | |
8592 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
8593 | } |
8594 | ||
8595 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
8596 | { | |
8597 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
79e53945 JB |
8598 | |
8599 | drm_framebuffer_cleanup(fb); | |
05394f39 | 8600 | drm_gem_object_unreference_unlocked(&intel_fb->obj->base); |
79e53945 JB |
8601 | |
8602 | kfree(intel_fb); | |
8603 | } | |
8604 | ||
8605 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 8606 | struct drm_file *file, |
79e53945 JB |
8607 | unsigned int *handle) |
8608 | { | |
8609 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 8610 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 8611 | |
05394f39 | 8612 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
8613 | } |
8614 | ||
8615 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
8616 | .destroy = intel_user_framebuffer_destroy, | |
8617 | .create_handle = intel_user_framebuffer_create_handle, | |
8618 | }; | |
8619 | ||
38651674 DA |
8620 | int intel_framebuffer_init(struct drm_device *dev, |
8621 | struct intel_framebuffer *intel_fb, | |
308e5bcb | 8622 | struct drm_mode_fb_cmd2 *mode_cmd, |
05394f39 | 8623 | struct drm_i915_gem_object *obj) |
79e53945 | 8624 | { |
79e53945 JB |
8625 | int ret; |
8626 | ||
c16ed4be CW |
8627 | if (obj->tiling_mode == I915_TILING_Y) { |
8628 | DRM_DEBUG("hardware does not support tiling Y\n"); | |
57cd6508 | 8629 | return -EINVAL; |
c16ed4be | 8630 | } |
57cd6508 | 8631 | |
c16ed4be CW |
8632 | if (mode_cmd->pitches[0] & 63) { |
8633 | DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n", | |
8634 | mode_cmd->pitches[0]); | |
57cd6508 | 8635 | return -EINVAL; |
c16ed4be | 8636 | } |
57cd6508 | 8637 | |
5d7bd705 | 8638 | /* FIXME <= Gen4 stride limits are bit unclear */ |
c16ed4be CW |
8639 | if (mode_cmd->pitches[0] > 32768) { |
8640 | DRM_DEBUG("pitch (%d) must be at less than 32768\n", | |
8641 | mode_cmd->pitches[0]); | |
5d7bd705 | 8642 | return -EINVAL; |
c16ed4be | 8643 | } |
5d7bd705 VS |
8644 | |
8645 | if (obj->tiling_mode != I915_TILING_NONE && | |
c16ed4be CW |
8646 | mode_cmd->pitches[0] != obj->stride) { |
8647 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
8648 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 8649 | return -EINVAL; |
c16ed4be | 8650 | } |
5d7bd705 | 8651 | |
57779d06 | 8652 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 8653 | switch (mode_cmd->pixel_format) { |
57779d06 | 8654 | case DRM_FORMAT_C8: |
04b3924d VS |
8655 | case DRM_FORMAT_RGB565: |
8656 | case DRM_FORMAT_XRGB8888: | |
8657 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
8658 | break; |
8659 | case DRM_FORMAT_XRGB1555: | |
8660 | case DRM_FORMAT_ARGB1555: | |
c16ed4be CW |
8661 | if (INTEL_INFO(dev)->gen > 3) { |
8662 | DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format); | |
57779d06 | 8663 | return -EINVAL; |
c16ed4be | 8664 | } |
57779d06 VS |
8665 | break; |
8666 | case DRM_FORMAT_XBGR8888: | |
8667 | case DRM_FORMAT_ABGR8888: | |
04b3924d VS |
8668 | case DRM_FORMAT_XRGB2101010: |
8669 | case DRM_FORMAT_ARGB2101010: | |
57779d06 VS |
8670 | case DRM_FORMAT_XBGR2101010: |
8671 | case DRM_FORMAT_ABGR2101010: | |
c16ed4be CW |
8672 | if (INTEL_INFO(dev)->gen < 4) { |
8673 | DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format); | |
57779d06 | 8674 | return -EINVAL; |
c16ed4be | 8675 | } |
b5626747 | 8676 | break; |
04b3924d VS |
8677 | case DRM_FORMAT_YUYV: |
8678 | case DRM_FORMAT_UYVY: | |
8679 | case DRM_FORMAT_YVYU: | |
8680 | case DRM_FORMAT_VYUY: | |
c16ed4be CW |
8681 | if (INTEL_INFO(dev)->gen < 5) { |
8682 | DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format); | |
57779d06 | 8683 | return -EINVAL; |
c16ed4be | 8684 | } |
57cd6508 CW |
8685 | break; |
8686 | default: | |
c16ed4be | 8687 | DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format); |
57cd6508 CW |
8688 | return -EINVAL; |
8689 | } | |
8690 | ||
90f9a336 VS |
8691 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
8692 | if (mode_cmd->offsets[0] != 0) | |
8693 | return -EINVAL; | |
8694 | ||
c7d73f6a DV |
8695 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
8696 | intel_fb->obj = obj; | |
8697 | ||
79e53945 JB |
8698 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
8699 | if (ret) { | |
8700 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
8701 | return ret; | |
8702 | } | |
8703 | ||
79e53945 JB |
8704 | return 0; |
8705 | } | |
8706 | ||
79e53945 JB |
8707 | static struct drm_framebuffer * |
8708 | intel_user_framebuffer_create(struct drm_device *dev, | |
8709 | struct drm_file *filp, | |
308e5bcb | 8710 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 8711 | { |
05394f39 | 8712 | struct drm_i915_gem_object *obj; |
79e53945 | 8713 | |
308e5bcb JB |
8714 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
8715 | mode_cmd->handles[0])); | |
c8725226 | 8716 | if (&obj->base == NULL) |
cce13ff7 | 8717 | return ERR_PTR(-ENOENT); |
79e53945 | 8718 | |
d2dff872 | 8719 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
8720 | } |
8721 | ||
79e53945 | 8722 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 8723 | .fb_create = intel_user_framebuffer_create, |
eb1f8e4f | 8724 | .output_poll_changed = intel_fb_output_poll_changed, |
79e53945 JB |
8725 | }; |
8726 | ||
e70236a8 JB |
8727 | /* Set up chip specific display functions */ |
8728 | static void intel_init_display(struct drm_device *dev) | |
8729 | { | |
8730 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8731 | ||
affa9354 | 8732 | if (HAS_DDI(dev)) { |
0e8ffe1b | 8733 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
09b4ddf9 | 8734 | dev_priv->display.crtc_mode_set = haswell_crtc_mode_set; |
4f771f10 PZ |
8735 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
8736 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
6441ab5f | 8737 | dev_priv->display.off = haswell_crtc_off; |
09b4ddf9 PZ |
8738 | dev_priv->display.update_plane = ironlake_update_plane; |
8739 | } else if (HAS_PCH_SPLIT(dev)) { | |
0e8ffe1b | 8740 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
f564048e | 8741 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
76e5a89c DV |
8742 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
8743 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
ee7b9f93 | 8744 | dev_priv->display.off = ironlake_crtc_off; |
17638cd6 | 8745 | dev_priv->display.update_plane = ironlake_update_plane; |
f564048e | 8746 | } else { |
0e8ffe1b | 8747 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
f564048e | 8748 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
76e5a89c DV |
8749 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
8750 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
ee7b9f93 | 8751 | dev_priv->display.off = i9xx_crtc_off; |
17638cd6 | 8752 | dev_priv->display.update_plane = i9xx_update_plane; |
f564048e | 8753 | } |
e70236a8 | 8754 | |
e70236a8 | 8755 | /* Returns the core display clock speed */ |
25eb05fc JB |
8756 | if (IS_VALLEYVIEW(dev)) |
8757 | dev_priv->display.get_display_clock_speed = | |
8758 | valleyview_get_display_clock_speed; | |
8759 | else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) | |
e70236a8 JB |
8760 | dev_priv->display.get_display_clock_speed = |
8761 | i945_get_display_clock_speed; | |
8762 | else if (IS_I915G(dev)) | |
8763 | dev_priv->display.get_display_clock_speed = | |
8764 | i915_get_display_clock_speed; | |
f2b115e6 | 8765 | else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev)) |
e70236a8 JB |
8766 | dev_priv->display.get_display_clock_speed = |
8767 | i9xx_misc_get_display_clock_speed; | |
8768 | else if (IS_I915GM(dev)) | |
8769 | dev_priv->display.get_display_clock_speed = | |
8770 | i915gm_get_display_clock_speed; | |
8771 | else if (IS_I865G(dev)) | |
8772 | dev_priv->display.get_display_clock_speed = | |
8773 | i865_get_display_clock_speed; | |
f0f8a9ce | 8774 | else if (IS_I85X(dev)) |
e70236a8 JB |
8775 | dev_priv->display.get_display_clock_speed = |
8776 | i855_get_display_clock_speed; | |
8777 | else /* 852, 830 */ | |
8778 | dev_priv->display.get_display_clock_speed = | |
8779 | i830_get_display_clock_speed; | |
8780 | ||
7f8a8569 | 8781 | if (HAS_PCH_SPLIT(dev)) { |
f00a3ddf | 8782 | if (IS_GEN5(dev)) { |
674cf967 | 8783 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
e0dac65e | 8784 | dev_priv->display.write_eld = ironlake_write_eld; |
1398261a | 8785 | } else if (IS_GEN6(dev)) { |
674cf967 | 8786 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
e0dac65e | 8787 | dev_priv->display.write_eld = ironlake_write_eld; |
357555c0 JB |
8788 | } else if (IS_IVYBRIDGE(dev)) { |
8789 | /* FIXME: detect B0+ stepping and use auto training */ | |
8790 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
e0dac65e | 8791 | dev_priv->display.write_eld = ironlake_write_eld; |
01a415fd DV |
8792 | dev_priv->display.modeset_global_resources = |
8793 | ivb_modeset_global_resources; | |
c82e4d26 ED |
8794 | } else if (IS_HASWELL(dev)) { |
8795 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; | |
83358c85 | 8796 | dev_priv->display.write_eld = haswell_write_eld; |
d6dd9eb1 DV |
8797 | dev_priv->display.modeset_global_resources = |
8798 | haswell_modeset_global_resources; | |
a0e63c22 | 8799 | } |
6067aaea | 8800 | } else if (IS_G4X(dev)) { |
e0dac65e | 8801 | dev_priv->display.write_eld = g4x_write_eld; |
e70236a8 | 8802 | } |
8c9f3aaf JB |
8803 | |
8804 | /* Default just returns -ENODEV to indicate unsupported */ | |
8805 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
8806 | ||
8807 | switch (INTEL_INFO(dev)->gen) { | |
8808 | case 2: | |
8809 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
8810 | break; | |
8811 | ||
8812 | case 3: | |
8813 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
8814 | break; | |
8815 | ||
8816 | case 4: | |
8817 | case 5: | |
8818 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
8819 | break; | |
8820 | ||
8821 | case 6: | |
8822 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
8823 | break; | |
7c9017e5 JB |
8824 | case 7: |
8825 | dev_priv->display.queue_flip = intel_gen7_queue_flip; | |
8826 | break; | |
8c9f3aaf | 8827 | } |
e70236a8 JB |
8828 | } |
8829 | ||
b690e96c JB |
8830 | /* |
8831 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
8832 | * resume, or other times. This quirk makes sure that's the case for | |
8833 | * affected systems. | |
8834 | */ | |
0206e353 | 8835 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
8836 | { |
8837 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8838 | ||
8839 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 8840 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
8841 | } |
8842 | ||
435793df KP |
8843 | /* |
8844 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
8845 | */ | |
8846 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
8847 | { | |
8848 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8849 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 8850 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
8851 | } |
8852 | ||
4dca20ef | 8853 | /* |
5a15ab5b CE |
8854 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
8855 | * brightness value | |
4dca20ef CE |
8856 | */ |
8857 | static void quirk_invert_brightness(struct drm_device *dev) | |
8858 | { | |
8859 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8860 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 8861 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
8862 | } |
8863 | ||
b690e96c JB |
8864 | struct intel_quirk { |
8865 | int device; | |
8866 | int subsystem_vendor; | |
8867 | int subsystem_device; | |
8868 | void (*hook)(struct drm_device *dev); | |
8869 | }; | |
8870 | ||
5f85f176 EE |
8871 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
8872 | struct intel_dmi_quirk { | |
8873 | void (*hook)(struct drm_device *dev); | |
8874 | const struct dmi_system_id (*dmi_id_list)[]; | |
8875 | }; | |
8876 | ||
8877 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
8878 | { | |
8879 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
8880 | return 1; | |
8881 | } | |
8882 | ||
8883 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
8884 | { | |
8885 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
8886 | { | |
8887 | .callback = intel_dmi_reverse_brightness, | |
8888 | .ident = "NCR Corporation", | |
8889 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
8890 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
8891 | }, | |
8892 | }, | |
8893 | { } /* terminating entry */ | |
8894 | }, | |
8895 | .hook = quirk_invert_brightness, | |
8896 | }, | |
8897 | }; | |
8898 | ||
c43b5634 | 8899 | static struct intel_quirk intel_quirks[] = { |
b690e96c | 8900 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
0206e353 | 8901 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
b690e96c | 8902 | |
b690e96c JB |
8903 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
8904 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
8905 | ||
b690e96c JB |
8906 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
8907 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
8908 | ||
ccd0d36e | 8909 | /* 830/845 need to leave pipe A & dpll A up */ |
b690e96c | 8910 | { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
dcdaed6e | 8911 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
435793df KP |
8912 | |
8913 | /* Lenovo U160 cannot use SSC on LVDS */ | |
8914 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
8915 | |
8916 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
8917 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b CE |
8918 | |
8919 | /* Acer Aspire 5734Z must invert backlight brightness */ | |
8920 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
1ffff603 JN |
8921 | |
8922 | /* Acer/eMachines G725 */ | |
8923 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
01e3a8fe JN |
8924 | |
8925 | /* Acer/eMachines e725 */ | |
8926 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
5559ecad JN |
8927 | |
8928 | /* Acer/Packard Bell NCL20 */ | |
8929 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
ac4199e0 DV |
8930 | |
8931 | /* Acer Aspire 4736Z */ | |
8932 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
b690e96c JB |
8933 | }; |
8934 | ||
8935 | static void intel_init_quirks(struct drm_device *dev) | |
8936 | { | |
8937 | struct pci_dev *d = dev->pdev; | |
8938 | int i; | |
8939 | ||
8940 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
8941 | struct intel_quirk *q = &intel_quirks[i]; | |
8942 | ||
8943 | if (d->device == q->device && | |
8944 | (d->subsystem_vendor == q->subsystem_vendor || | |
8945 | q->subsystem_vendor == PCI_ANY_ID) && | |
8946 | (d->subsystem_device == q->subsystem_device || | |
8947 | q->subsystem_device == PCI_ANY_ID)) | |
8948 | q->hook(dev); | |
8949 | } | |
5f85f176 EE |
8950 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
8951 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
8952 | intel_dmi_quirks[i].hook(dev); | |
8953 | } | |
b690e96c JB |
8954 | } |
8955 | ||
9cce37f4 JB |
8956 | /* Disable the VGA plane that we never use */ |
8957 | static void i915_disable_vga(struct drm_device *dev) | |
8958 | { | |
8959 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8960 | u8 sr1; | |
766aa1c4 | 8961 | u32 vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 JB |
8962 | |
8963 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); | |
3fdcf431 | 8964 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
8965 | sr1 = inb(VGA_SR_DATA); |
8966 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
8967 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
8968 | udelay(300); | |
8969 | ||
8970 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); | |
8971 | POSTING_READ(vga_reg); | |
8972 | } | |
8973 | ||
f817586c DV |
8974 | void intel_modeset_init_hw(struct drm_device *dev) |
8975 | { | |
fa42e23c | 8976 | intel_init_power_well(dev); |
0232e927 | 8977 | |
a8f78b58 ED |
8978 | intel_prepare_ddi(dev); |
8979 | ||
f817586c DV |
8980 | intel_init_clock_gating(dev); |
8981 | ||
79f5b2c7 | 8982 | mutex_lock(&dev->struct_mutex); |
8090c6b9 | 8983 | intel_enable_gt_powersave(dev); |
79f5b2c7 | 8984 | mutex_unlock(&dev->struct_mutex); |
f817586c DV |
8985 | } |
8986 | ||
79e53945 JB |
8987 | void intel_modeset_init(struct drm_device *dev) |
8988 | { | |
652c393a | 8989 | struct drm_i915_private *dev_priv = dev->dev_private; |
7f1f3851 | 8990 | int i, j, ret; |
79e53945 JB |
8991 | |
8992 | drm_mode_config_init(dev); | |
8993 | ||
8994 | dev->mode_config.min_width = 0; | |
8995 | dev->mode_config.min_height = 0; | |
8996 | ||
019d96cb DA |
8997 | dev->mode_config.preferred_depth = 24; |
8998 | dev->mode_config.prefer_shadow = 1; | |
8999 | ||
e6ecefaa | 9000 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 9001 | |
b690e96c JB |
9002 | intel_init_quirks(dev); |
9003 | ||
1fa61106 ED |
9004 | intel_init_pm(dev); |
9005 | ||
e3c74757 BW |
9006 | if (INTEL_INFO(dev)->num_pipes == 0) |
9007 | return; | |
9008 | ||
e70236a8 JB |
9009 | intel_init_display(dev); |
9010 | ||
a6c45cf0 CW |
9011 | if (IS_GEN2(dev)) { |
9012 | dev->mode_config.max_width = 2048; | |
9013 | dev->mode_config.max_height = 2048; | |
9014 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
9015 | dev->mode_config.max_width = 4096; |
9016 | dev->mode_config.max_height = 4096; | |
79e53945 | 9017 | } else { |
a6c45cf0 CW |
9018 | dev->mode_config.max_width = 8192; |
9019 | dev->mode_config.max_height = 8192; | |
79e53945 | 9020 | } |
5d4545ae | 9021 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 9022 | |
28c97730 | 9023 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
9024 | INTEL_INFO(dev)->num_pipes, |
9025 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 9026 | |
7eb552ae | 9027 | for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) { |
79e53945 | 9028 | intel_crtc_init(dev, i); |
7f1f3851 JB |
9029 | for (j = 0; j < dev_priv->num_plane; j++) { |
9030 | ret = intel_plane_init(dev, i, j); | |
9031 | if (ret) | |
9032 | DRM_DEBUG_KMS("pipe %d plane %d init failed: %d\n", | |
9033 | i, j, ret); | |
9034 | } | |
79e53945 JB |
9035 | } |
9036 | ||
79f689aa | 9037 | intel_cpu_pll_init(dev); |
ee7b9f93 JB |
9038 | intel_pch_pll_init(dev); |
9039 | ||
9cce37f4 JB |
9040 | /* Just disable it once at startup */ |
9041 | i915_disable_vga(dev); | |
79e53945 | 9042 | intel_setup_outputs(dev); |
11be49eb CW |
9043 | |
9044 | /* Just in case the BIOS is doing something questionable. */ | |
9045 | intel_disable_fbc(dev); | |
2c7111db CW |
9046 | } |
9047 | ||
24929352 DV |
9048 | static void |
9049 | intel_connector_break_all_links(struct intel_connector *connector) | |
9050 | { | |
9051 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
9052 | connector->base.encoder = NULL; | |
9053 | connector->encoder->connectors_active = false; | |
9054 | connector->encoder->base.crtc = NULL; | |
9055 | } | |
9056 | ||
7fad798e DV |
9057 | static void intel_enable_pipe_a(struct drm_device *dev) |
9058 | { | |
9059 | struct intel_connector *connector; | |
9060 | struct drm_connector *crt = NULL; | |
9061 | struct intel_load_detect_pipe load_detect_temp; | |
9062 | ||
9063 | /* We can't just switch on the pipe A, we need to set things up with a | |
9064 | * proper mode and output configuration. As a gross hack, enable pipe A | |
9065 | * by enabling the load detect pipe once. */ | |
9066 | list_for_each_entry(connector, | |
9067 | &dev->mode_config.connector_list, | |
9068 | base.head) { | |
9069 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { | |
9070 | crt = &connector->base; | |
9071 | break; | |
9072 | } | |
9073 | } | |
9074 | ||
9075 | if (!crt) | |
9076 | return; | |
9077 | ||
9078 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp)) | |
9079 | intel_release_load_detect_pipe(crt, &load_detect_temp); | |
9080 | ||
652c393a | 9081 | |
7fad798e DV |
9082 | } |
9083 | ||
fa555837 DV |
9084 | static bool |
9085 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
9086 | { | |
7eb552ae BW |
9087 | struct drm_device *dev = crtc->base.dev; |
9088 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 DV |
9089 | u32 reg, val; |
9090 | ||
7eb552ae | 9091 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
9092 | return true; |
9093 | ||
9094 | reg = DSPCNTR(!crtc->plane); | |
9095 | val = I915_READ(reg); | |
9096 | ||
9097 | if ((val & DISPLAY_PLANE_ENABLE) && | |
9098 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
9099 | return false; | |
9100 | ||
9101 | return true; | |
9102 | } | |
9103 | ||
24929352 DV |
9104 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
9105 | { | |
9106 | struct drm_device *dev = crtc->base.dev; | |
9107 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 | 9108 | u32 reg; |
24929352 | 9109 | |
24929352 | 9110 | /* Clear any frame start delays used for debugging left by the BIOS */ |
702e7a56 | 9111 | reg = PIPECONF(crtc->cpu_transcoder); |
24929352 DV |
9112 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
9113 | ||
9114 | /* We need to sanitize the plane -> pipe mapping first because this will | |
fa555837 DV |
9115 | * disable the crtc (and hence change the state) if it is wrong. Note |
9116 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
9117 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
9118 | struct intel_connector *connector; |
9119 | bool plane; | |
9120 | ||
24929352 DV |
9121 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
9122 | crtc->base.base.id); | |
9123 | ||
9124 | /* Pipe has the wrong plane attached and the plane is active. | |
9125 | * Temporarily change the plane mapping and disable everything | |
9126 | * ... */ | |
9127 | plane = crtc->plane; | |
9128 | crtc->plane = !plane; | |
9129 | dev_priv->display.crtc_disable(&crtc->base); | |
9130 | crtc->plane = plane; | |
9131 | ||
9132 | /* ... and break all links. */ | |
9133 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
9134 | base.head) { | |
9135 | if (connector->encoder->base.crtc != &crtc->base) | |
9136 | continue; | |
9137 | ||
9138 | intel_connector_break_all_links(connector); | |
9139 | } | |
9140 | ||
9141 | WARN_ON(crtc->active); | |
9142 | crtc->base.enabled = false; | |
9143 | } | |
24929352 | 9144 | |
7fad798e DV |
9145 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
9146 | crtc->pipe == PIPE_A && !crtc->active) { | |
9147 | /* BIOS forgot to enable pipe A, this mostly happens after | |
9148 | * resume. Force-enable the pipe to fix this, the update_dpms | |
9149 | * call below we restore the pipe to the right state, but leave | |
9150 | * the required bits on. */ | |
9151 | intel_enable_pipe_a(dev); | |
9152 | } | |
9153 | ||
24929352 DV |
9154 | /* Adjust the state of the output pipe according to whether we |
9155 | * have active connectors/encoders. */ | |
9156 | intel_crtc_update_dpms(&crtc->base); | |
9157 | ||
9158 | if (crtc->active != crtc->base.enabled) { | |
9159 | struct intel_encoder *encoder; | |
9160 | ||
9161 | /* This can happen either due to bugs in the get_hw_state | |
9162 | * functions or because the pipe is force-enabled due to the | |
9163 | * pipe A quirk. */ | |
9164 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
9165 | crtc->base.base.id, | |
9166 | crtc->base.enabled ? "enabled" : "disabled", | |
9167 | crtc->active ? "enabled" : "disabled"); | |
9168 | ||
9169 | crtc->base.enabled = crtc->active; | |
9170 | ||
9171 | /* Because we only establish the connector -> encoder -> | |
9172 | * crtc links if something is active, this means the | |
9173 | * crtc is now deactivated. Break the links. connector | |
9174 | * -> encoder links are only establish when things are | |
9175 | * actually up, hence no need to break them. */ | |
9176 | WARN_ON(crtc->active); | |
9177 | ||
9178 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { | |
9179 | WARN_ON(encoder->connectors_active); | |
9180 | encoder->base.crtc = NULL; | |
9181 | } | |
9182 | } | |
9183 | } | |
9184 | ||
9185 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
9186 | { | |
9187 | struct intel_connector *connector; | |
9188 | struct drm_device *dev = encoder->base.dev; | |
9189 | ||
9190 | /* We need to check both for a crtc link (meaning that the | |
9191 | * encoder is active and trying to read from a pipe) and the | |
9192 | * pipe itself being active. */ | |
9193 | bool has_active_crtc = encoder->base.crtc && | |
9194 | to_intel_crtc(encoder->base.crtc)->active; | |
9195 | ||
9196 | if (encoder->connectors_active && !has_active_crtc) { | |
9197 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", | |
9198 | encoder->base.base.id, | |
9199 | drm_get_encoder_name(&encoder->base)); | |
9200 | ||
9201 | /* Connector is active, but has no active pipe. This is | |
9202 | * fallout from our resume register restoring. Disable | |
9203 | * the encoder manually again. */ | |
9204 | if (encoder->base.crtc) { | |
9205 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
9206 | encoder->base.base.id, | |
9207 | drm_get_encoder_name(&encoder->base)); | |
9208 | encoder->disable(encoder); | |
9209 | } | |
9210 | ||
9211 | /* Inconsistent output/port/pipe state happens presumably due to | |
9212 | * a bug in one of the get_hw_state functions. Or someplace else | |
9213 | * in our code, like the register restore mess on resume. Clamp | |
9214 | * things to off as a safer default. */ | |
9215 | list_for_each_entry(connector, | |
9216 | &dev->mode_config.connector_list, | |
9217 | base.head) { | |
9218 | if (connector->encoder != encoder) | |
9219 | continue; | |
9220 | ||
9221 | intel_connector_break_all_links(connector); | |
9222 | } | |
9223 | } | |
9224 | /* Enabled encoders without active connectors will be fixed in | |
9225 | * the crtc fixup. */ | |
9226 | } | |
9227 | ||
44cec740 | 9228 | void i915_redisable_vga(struct drm_device *dev) |
0fde901f KM |
9229 | { |
9230 | struct drm_i915_private *dev_priv = dev->dev_private; | |
766aa1c4 | 9231 | u32 vga_reg = i915_vgacntrl_reg(dev); |
0fde901f KM |
9232 | |
9233 | if (I915_READ(vga_reg) != VGA_DISP_DISABLE) { | |
9234 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
209d5211 | 9235 | i915_disable_vga(dev); |
0fde901f KM |
9236 | } |
9237 | } | |
9238 | ||
24929352 DV |
9239 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm |
9240 | * and i915 state tracking structures. */ | |
45e2b5f6 DV |
9241 | void intel_modeset_setup_hw_state(struct drm_device *dev, |
9242 | bool force_restore) | |
24929352 DV |
9243 | { |
9244 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9245 | enum pipe pipe; | |
9246 | u32 tmp; | |
b5644d05 | 9247 | struct drm_plane *plane; |
24929352 DV |
9248 | struct intel_crtc *crtc; |
9249 | struct intel_encoder *encoder; | |
9250 | struct intel_connector *connector; | |
9251 | ||
affa9354 | 9252 | if (HAS_DDI(dev)) { |
e28d54cb PZ |
9253 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
9254 | ||
9255 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
9256 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
9257 | case TRANS_DDI_EDP_INPUT_A_ON: | |
9258 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
9259 | pipe = PIPE_A; | |
9260 | break; | |
9261 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
9262 | pipe = PIPE_B; | |
9263 | break; | |
9264 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
9265 | pipe = PIPE_C; | |
9266 | break; | |
aaa148ec DL |
9267 | default: |
9268 | /* A bogus value has been programmed, disable | |
9269 | * the transcoder */ | |
9270 | WARN(1, "Bogus eDP source %08x\n", tmp); | |
9271 | intel_ddi_disable_transcoder_func(dev_priv, | |
9272 | TRANSCODER_EDP); | |
9273 | goto setup_pipes; | |
e28d54cb PZ |
9274 | } |
9275 | ||
9276 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
9277 | crtc->cpu_transcoder = TRANSCODER_EDP; | |
9278 | ||
9279 | DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n", | |
9280 | pipe_name(pipe)); | |
9281 | } | |
9282 | } | |
9283 | ||
aaa148ec | 9284 | setup_pipes: |
0e8ffe1b DV |
9285 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
9286 | base.head) { | |
88adfff1 | 9287 | memset(&crtc->config, 0, sizeof(crtc->config)); |
0e8ffe1b DV |
9288 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
9289 | &crtc->config); | |
24929352 DV |
9290 | |
9291 | crtc->base.enabled = crtc->active; | |
9292 | ||
9293 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
9294 | crtc->base.base.id, | |
9295 | crtc->active ? "enabled" : "disabled"); | |
9296 | } | |
9297 | ||
affa9354 | 9298 | if (HAS_DDI(dev)) |
6441ab5f PZ |
9299 | intel_ddi_setup_hw_pll_state(dev); |
9300 | ||
24929352 DV |
9301 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9302 | base.head) { | |
9303 | pipe = 0; | |
9304 | ||
9305 | if (encoder->get_hw_state(encoder, &pipe)) { | |
9306 | encoder->base.crtc = | |
9307 | dev_priv->pipe_to_crtc_mapping[pipe]; | |
9308 | } else { | |
9309 | encoder->base.crtc = NULL; | |
9310 | } | |
9311 | ||
9312 | encoder->connectors_active = false; | |
9313 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n", | |
9314 | encoder->base.base.id, | |
9315 | drm_get_encoder_name(&encoder->base), | |
9316 | encoder->base.crtc ? "enabled" : "disabled", | |
9317 | pipe); | |
9318 | } | |
9319 | ||
9320 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
9321 | base.head) { | |
9322 | if (connector->get_hw_state(connector)) { | |
9323 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
9324 | connector->encoder->connectors_active = true; | |
9325 | connector->base.encoder = &connector->encoder->base; | |
9326 | } else { | |
9327 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
9328 | connector->base.encoder = NULL; | |
9329 | } | |
9330 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
9331 | connector->base.base.id, | |
9332 | drm_get_connector_name(&connector->base), | |
9333 | connector->base.encoder ? "enabled" : "disabled"); | |
9334 | } | |
9335 | ||
9336 | /* HW state is read out, now we need to sanitize this mess. */ | |
9337 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
9338 | base.head) { | |
9339 | intel_sanitize_encoder(encoder); | |
9340 | } | |
9341 | ||
9342 | for_each_pipe(pipe) { | |
9343 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
9344 | intel_sanitize_crtc(crtc); | |
9345 | } | |
9a935856 | 9346 | |
45e2b5f6 | 9347 | if (force_restore) { |
f30da187 DV |
9348 | /* |
9349 | * We need to use raw interfaces for restoring state to avoid | |
9350 | * checking (bogus) intermediate states. | |
9351 | */ | |
45e2b5f6 | 9352 | for_each_pipe(pipe) { |
b5644d05 JB |
9353 | struct drm_crtc *crtc = |
9354 | dev_priv->pipe_to_crtc_mapping[pipe]; | |
f30da187 DV |
9355 | |
9356 | __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, | |
9357 | crtc->fb); | |
45e2b5f6 | 9358 | } |
b5644d05 JB |
9359 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) |
9360 | intel_plane_restore(plane); | |
0fde901f KM |
9361 | |
9362 | i915_redisable_vga(dev); | |
45e2b5f6 DV |
9363 | } else { |
9364 | intel_modeset_update_staged_output_state(dev); | |
9365 | } | |
8af6cf88 DV |
9366 | |
9367 | intel_modeset_check_state(dev); | |
2e938892 DV |
9368 | |
9369 | drm_mode_config_reset(dev); | |
2c7111db CW |
9370 | } |
9371 | ||
9372 | void intel_modeset_gem_init(struct drm_device *dev) | |
9373 | { | |
1833b134 | 9374 | intel_modeset_init_hw(dev); |
02e792fb DV |
9375 | |
9376 | intel_setup_overlay(dev); | |
24929352 | 9377 | |
45e2b5f6 | 9378 | intel_modeset_setup_hw_state(dev, false); |
79e53945 JB |
9379 | } |
9380 | ||
9381 | void intel_modeset_cleanup(struct drm_device *dev) | |
9382 | { | |
652c393a JB |
9383 | struct drm_i915_private *dev_priv = dev->dev_private; |
9384 | struct drm_crtc *crtc; | |
9385 | struct intel_crtc *intel_crtc; | |
9386 | ||
f87ea761 | 9387 | drm_kms_helper_poll_fini(dev); |
652c393a JB |
9388 | mutex_lock(&dev->struct_mutex); |
9389 | ||
723bfd70 JB |
9390 | intel_unregister_dsm_handler(); |
9391 | ||
9392 | ||
652c393a JB |
9393 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
9394 | /* Skip inactive CRTCs */ | |
9395 | if (!crtc->fb) | |
9396 | continue; | |
9397 | ||
9398 | intel_crtc = to_intel_crtc(crtc); | |
3dec0095 | 9399 | intel_increase_pllclock(crtc); |
652c393a JB |
9400 | } |
9401 | ||
973d04f9 | 9402 | intel_disable_fbc(dev); |
e70236a8 | 9403 | |
8090c6b9 | 9404 | intel_disable_gt_powersave(dev); |
0cdab21f | 9405 | |
930ebb46 DV |
9406 | ironlake_teardown_rc6(dev); |
9407 | ||
57f350b6 JB |
9408 | if (IS_VALLEYVIEW(dev)) |
9409 | vlv_init_dpio(dev); | |
9410 | ||
69341a5e KH |
9411 | mutex_unlock(&dev->struct_mutex); |
9412 | ||
6c0d9350 DV |
9413 | /* Disable the irq before mode object teardown, for the irq might |
9414 | * enqueue unpin/hotplug work. */ | |
9415 | drm_irq_uninstall(dev); | |
9416 | cancel_work_sync(&dev_priv->hotplug_work); | |
c6a828d3 | 9417 | cancel_work_sync(&dev_priv->rps.work); |
6c0d9350 | 9418 | |
1630fe75 CW |
9419 | /* flush any delayed tasks or pending work */ |
9420 | flush_scheduled_work(); | |
9421 | ||
79e53945 | 9422 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
9423 | |
9424 | intel_cleanup_overlay(dev); | |
79e53945 JB |
9425 | } |
9426 | ||
f1c79df3 ZW |
9427 | /* |
9428 | * Return which encoder is currently attached for connector. | |
9429 | */ | |
df0e9248 | 9430 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 9431 | { |
df0e9248 CW |
9432 | return &intel_attached_encoder(connector)->base; |
9433 | } | |
f1c79df3 | 9434 | |
df0e9248 CW |
9435 | void intel_connector_attach_encoder(struct intel_connector *connector, |
9436 | struct intel_encoder *encoder) | |
9437 | { | |
9438 | connector->encoder = encoder; | |
9439 | drm_mode_connector_attach_encoder(&connector->base, | |
9440 | &encoder->base); | |
79e53945 | 9441 | } |
28d52043 DA |
9442 | |
9443 | /* | |
9444 | * set vga decode state - true == enable VGA decode | |
9445 | */ | |
9446 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
9447 | { | |
9448 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9449 | u16 gmch_ctrl; | |
9450 | ||
9451 | pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl); | |
9452 | if (state) | |
9453 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
9454 | else | |
9455 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
9456 | pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl); | |
9457 | return 0; | |
9458 | } | |
c4a1d9e4 CW |
9459 | |
9460 | #ifdef CONFIG_DEBUG_FS | |
9461 | #include <linux/seq_file.h> | |
9462 | ||
9463 | struct intel_display_error_state { | |
9464 | struct intel_cursor_error_state { | |
9465 | u32 control; | |
9466 | u32 position; | |
9467 | u32 base; | |
9468 | u32 size; | |
52331309 | 9469 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
9470 | |
9471 | struct intel_pipe_error_state { | |
9472 | u32 conf; | |
9473 | u32 source; | |
9474 | ||
9475 | u32 htotal; | |
9476 | u32 hblank; | |
9477 | u32 hsync; | |
9478 | u32 vtotal; | |
9479 | u32 vblank; | |
9480 | u32 vsync; | |
52331309 | 9481 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
9482 | |
9483 | struct intel_plane_error_state { | |
9484 | u32 control; | |
9485 | u32 stride; | |
9486 | u32 size; | |
9487 | u32 pos; | |
9488 | u32 addr; | |
9489 | u32 surface; | |
9490 | u32 tile_offset; | |
52331309 | 9491 | } plane[I915_MAX_PIPES]; |
c4a1d9e4 CW |
9492 | }; |
9493 | ||
9494 | struct intel_display_error_state * | |
9495 | intel_display_capture_error_state(struct drm_device *dev) | |
9496 | { | |
0206e353 | 9497 | drm_i915_private_t *dev_priv = dev->dev_private; |
c4a1d9e4 | 9498 | struct intel_display_error_state *error; |
702e7a56 | 9499 | enum transcoder cpu_transcoder; |
c4a1d9e4 CW |
9500 | int i; |
9501 | ||
9502 | error = kmalloc(sizeof(*error), GFP_ATOMIC); | |
9503 | if (error == NULL) | |
9504 | return NULL; | |
9505 | ||
52331309 | 9506 | for_each_pipe(i) { |
702e7a56 PZ |
9507 | cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i); |
9508 | ||
a18c4c3d PZ |
9509 | if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) { |
9510 | error->cursor[i].control = I915_READ(CURCNTR(i)); | |
9511 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
9512 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
9513 | } else { | |
9514 | error->cursor[i].control = I915_READ(CURCNTR_IVB(i)); | |
9515 | error->cursor[i].position = I915_READ(CURPOS_IVB(i)); | |
9516 | error->cursor[i].base = I915_READ(CURBASE_IVB(i)); | |
9517 | } | |
c4a1d9e4 CW |
9518 | |
9519 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
9520 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 9521 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 9522 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
9523 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
9524 | } | |
ca291363 PZ |
9525 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
9526 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
9527 | if (INTEL_INFO(dev)->gen >= 4) { |
9528 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
9529 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
9530 | } | |
9531 | ||
702e7a56 | 9532 | error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder)); |
c4a1d9e4 | 9533 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
fe2b8f9d PZ |
9534 | error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); |
9535 | error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
9536 | error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
9537 | error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
9538 | error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
9539 | error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
9540 | } |
9541 | ||
9542 | return error; | |
9543 | } | |
9544 | ||
9545 | void | |
9546 | intel_display_print_error_state(struct seq_file *m, | |
9547 | struct drm_device *dev, | |
9548 | struct intel_display_error_state *error) | |
9549 | { | |
9550 | int i; | |
9551 | ||
7eb552ae | 9552 | seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
52331309 | 9553 | for_each_pipe(i) { |
c4a1d9e4 CW |
9554 | seq_printf(m, "Pipe [%d]:\n", i); |
9555 | seq_printf(m, " CONF: %08x\n", error->pipe[i].conf); | |
9556 | seq_printf(m, " SRC: %08x\n", error->pipe[i].source); | |
9557 | seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal); | |
9558 | seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank); | |
9559 | seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync); | |
9560 | seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal); | |
9561 | seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank); | |
9562 | seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync); | |
9563 | ||
9564 | seq_printf(m, "Plane [%d]:\n", i); | |
9565 | seq_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
9566 | seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 9567 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 9568 | seq_printf(m, " SIZE: %08x\n", error->plane[i].size); |
80ca378b PZ |
9569 | seq_printf(m, " POS: %08x\n", error->plane[i].pos); |
9570 | } | |
4b71a570 | 9571 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
ca291363 | 9572 | seq_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 CW |
9573 | if (INTEL_INFO(dev)->gen >= 4) { |
9574 | seq_printf(m, " SURF: %08x\n", error->plane[i].surface); | |
9575 | seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
9576 | } | |
9577 | ||
9578 | seq_printf(m, "Cursor [%d]:\n", i); | |
9579 | seq_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
9580 | seq_printf(m, " POS: %08x\n", error->cursor[i].position); | |
9581 | seq_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
9582 | } | |
9583 | } | |
9584 | #endif |