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i915/vlv: untangle integrated clock source handling v4
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
3dec0095 44static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 45static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 46
f1f644dc
JB		 47static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
48 struct intel_crtc_config *pipe_config);
18442d08
VS		 49static void ironlake_pch_clock_get(struct intel_crtc *crtc,
50 struct intel_crtc_config *pipe_config);
f1f644dc 51
e7457a9a
DL		 52static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
53 int x, int y, struct drm_framebuffer *old_fb);
54
55
79e53945 56typedef struct {
0206e353 57 int min, max;
79e53945
JB		 58} intel_range_t;
59
60typedef struct {
0206e353
AJ		 61 int dot_limit;
62 int p2_slow, p2_fast;
79e53945
JB		 63} intel_p2_t;
64
d4906093
ML		 65typedef struct intel_limit intel_limit_t;
66struct intel_limit {
0206e353
AJ		 67 intel_range_t dot, vco, n, m, m1, m2, p, p1;
68 intel_p2_t p2;
d4906093 69};
79e53945 70
d2acd215
DV		 71int
72intel_pch_rawclk(struct drm_device *dev)
73{
74 struct drm_i915_private *dev_priv = dev->dev_private;
75
76 WARN_ON(!HAS_PCH_SPLIT(dev));
77
78 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
79}
80
021357ac
CW		 81static inline u32 /* units of 100MHz */
82intel_fdi_link_freq(struct drm_device *dev)
83{
8b99e68c
CW		 84 if (IS_GEN5(dev)) {
85 struct drm_i915_private *dev_priv = dev->dev_private;
86 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
87 } else
88 return 27;
021357ac
CW		 89}
90
5d536e28 91static const intel_limit_t intel_limits_i8xx_dac = {
0206e353
AJ		 92 .dot = { .min = 25000, .max = 350000 },
93 .vco = { .min = 930000, .max = 1400000 },
94 .n = { .min = 3, .max = 16 },
95 .m = { .min = 96, .max = 140 },
96 .m1 = { .min = 18, .max = 26 },
97 .m2 = { .min = 6, .max = 16 },
98 .p = { .min = 4, .max = 128 },
99 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 100 .p2 = { .dot_limit = 165000,
101 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 102};
103
5d536e28
DV		 104static const intel_limit_t intel_limits_i8xx_dvo = {
105 .dot = { .min = 25000, .max = 350000 },
106 .vco = { .min = 930000, .max = 1400000 },
107 .n = { .min = 3, .max = 16 },
108 .m = { .min = 96, .max = 140 },
109 .m1 = { .min = 18, .max = 26 },
110 .m2 = { .min = 6, .max = 16 },
111 .p = { .min = 4, .max = 128 },
112 .p1 = { .min = 2, .max = 33 },
113 .p2 = { .dot_limit = 165000,
114 .p2_slow = 4, .p2_fast = 4 },
115};
116
e4b36699 117static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 118 .dot = { .min = 25000, .max = 350000 },
119 .vco = { .min = 930000, .max = 1400000 },
120 .n = { .min = 3, .max = 16 },
121 .m = { .min = 96, .max = 140 },
122 .m1 = { .min = 18, .max = 26 },
123 .m2 = { .min = 6, .max = 16 },
124 .p = { .min = 4, .max = 128 },
125 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 126 .p2 = { .dot_limit = 165000,
127 .p2_slow = 14, .p2_fast = 7 },
e4b36699 128};
273e27ca 129
e4b36699 130static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 131 .dot = { .min = 20000, .max = 400000 },
132 .vco = { .min = 1400000, .max = 2800000 },
133 .n = { .min = 1, .max = 6 },
134 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 135 .m1 = { .min = 8, .max = 18 },
136 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 137 .p = { .min = 5, .max = 80 },
138 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 139 .p2 = { .dot_limit = 200000,
140 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 141};
142
143static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 144 .dot = { .min = 20000, .max = 400000 },
145 .vco = { .min = 1400000, .max = 2800000 },
146 .n = { .min = 1, .max = 6 },
147 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 148 .m1 = { .min = 8, .max = 18 },
149 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 150 .p = { .min = 7, .max = 98 },
151 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 152 .p2 = { .dot_limit = 112000,
153 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 154};
155
273e27ca 156
e4b36699 157static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 158 .dot = { .min = 25000, .max = 270000 },
159 .vco = { .min = 1750000, .max = 3500000},
160 .n = { .min = 1, .max = 4 },
161 .m = { .min = 104, .max = 138 },
162 .m1 = { .min = 17, .max = 23 },
163 .m2 = { .min = 5, .max = 11 },
164 .p = { .min = 10, .max = 30 },
165 .p1 = { .min = 1, .max = 3},
166 .p2 = { .dot_limit = 270000,
167 .p2_slow = 10,
168 .p2_fast = 10
044c7c41 169 },
e4b36699
KP		 170};
171
172static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 173 .dot = { .min = 22000, .max = 400000 },
174 .vco = { .min = 1750000, .max = 3500000},
175 .n = { .min = 1, .max = 4 },
176 .m = { .min = 104, .max = 138 },
177 .m1 = { .min = 16, .max = 23 },
178 .m2 = { .min = 5, .max = 11 },
179 .p = { .min = 5, .max = 80 },
180 .p1 = { .min = 1, .max = 8},
181 .p2 = { .dot_limit = 165000,
182 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 183};
184
185static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 186 .dot = { .min = 20000, .max = 115000 },
187 .vco = { .min = 1750000, .max = 3500000 },
188 .n = { .min = 1, .max = 3 },
189 .m = { .min = 104, .max = 138 },
190 .m1 = { .min = 17, .max = 23 },
191 .m2 = { .min = 5, .max = 11 },
192 .p = { .min = 28, .max = 112 },
193 .p1 = { .min = 2, .max = 8 },
194 .p2 = { .dot_limit = 0,
195 .p2_slow = 14, .p2_fast = 14
044c7c41 196 },
e4b36699
KP		 197};
198
199static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 200 .dot = { .min = 80000, .max = 224000 },
201 .vco = { .min = 1750000, .max = 3500000 },
202 .n = { .min = 1, .max = 3 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 17, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 14, .max = 42 },
207 .p1 = { .min = 2, .max = 6 },
208 .p2 = { .dot_limit = 0,
209 .p2_slow = 7, .p2_fast = 7
044c7c41 210 },
e4b36699
KP		 211};
212
f2b115e6 213static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 214 .dot = { .min = 20000, .max = 400000},
215 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 216 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 217 .n = { .min = 3, .max = 6 },
218 .m = { .min = 2, .max = 256 },
273e27ca 219 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 220 .m1 = { .min = 0, .max = 0 },
221 .m2 = { .min = 0, .max = 254 },
222 .p = { .min = 5, .max = 80 },
223 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 224 .p2 = { .dot_limit = 200000,
225 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 226};
227
f2b115e6 228static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 229 .dot = { .min = 20000, .max = 400000 },
230 .vco = { .min = 1700000, .max = 3500000 },
231 .n = { .min = 3, .max = 6 },
232 .m = { .min = 2, .max = 256 },
233 .m1 = { .min = 0, .max = 0 },
234 .m2 = { .min = 0, .max = 254 },
235 .p = { .min = 7, .max = 112 },
236 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 237 .p2 = { .dot_limit = 112000,
238 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 239};
240
273e27ca
EA		 241/* Ironlake / Sandybridge
242 *
243 * We calculate clock using (register_value + 2) for N/M1/M2, so here
244 * the range value for them is (actual_value - 2).
245 */
b91ad0ec 246static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 247 .dot = { .min = 25000, .max = 350000 },
248 .vco = { .min = 1760000, .max = 3510000 },
249 .n = { .min = 1, .max = 5 },
250 .m = { .min = 79, .max = 127 },
251 .m1 = { .min = 12, .max = 22 },
252 .m2 = { .min = 5, .max = 9 },
253 .p = { .min = 5, .max = 80 },
254 .p1 = { .min = 1, .max = 8 },
255 .p2 = { .dot_limit = 225000,
256 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 257};
258
b91ad0ec 259static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 260 .dot = { .min = 25000, .max = 350000 },
261 .vco = { .min = 1760000, .max = 3510000 },
262 .n = { .min = 1, .max = 3 },
263 .m = { .min = 79, .max = 118 },
264 .m1 = { .min = 12, .max = 22 },
265 .m2 = { .min = 5, .max = 9 },
266 .p = { .min = 28, .max = 112 },
267 .p1 = { .min = 2, .max = 8 },
268 .p2 = { .dot_limit = 225000,
269 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 270};
271
272static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 273 .dot = { .min = 25000, .max = 350000 },
274 .vco = { .min = 1760000, .max = 3510000 },
275 .n = { .min = 1, .max = 3 },
276 .m = { .min = 79, .max = 127 },
277 .m1 = { .min = 12, .max = 22 },
278 .m2 = { .min = 5, .max = 9 },
279 .p = { .min = 14, .max = 56 },
280 .p1 = { .min = 2, .max = 8 },
281 .p2 = { .dot_limit = 225000,
282 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 283};
284
273e27ca 285/* LVDS 100mhz refclk limits. */
b91ad0ec 286static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 287 .dot = { .min = 25000, .max = 350000 },
288 .vco = { .min = 1760000, .max = 3510000 },
289 .n = { .min = 1, .max = 2 },
290 .m = { .min = 79, .max = 126 },
291 .m1 = { .min = 12, .max = 22 },
292 .m2 = { .min = 5, .max = 9 },
293 .p = { .min = 28, .max = 112 },
0206e353 294 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 295 .p2 = { .dot_limit = 225000,
296 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 297};
298
299static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 300 .dot = { .min = 25000, .max = 350000 },
301 .vco = { .min = 1760000, .max = 3510000 },
302 .n = { .min = 1, .max = 3 },
303 .m = { .min = 79, .max = 126 },
304 .m1 = { .min = 12, .max = 22 },
305 .m2 = { .min = 5, .max = 9 },
306 .p = { .min = 14, .max = 42 },
0206e353 307 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 308 .p2 = { .dot_limit = 225000,
309 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 310};
311
a0c4da24
JB		 312static const intel_limit_t intel_limits_vlv_dac = {
313 .dot = { .min = 25000, .max = 270000 },
314 .vco = { .min = 4000000, .max = 6000000 },
315 .n = { .min = 1, .max = 7 },
316 .m = { .min = 22, .max = 450 }, /* guess */
317 .m1 = { .min = 2, .max = 3 },
318 .m2 = { .min = 11, .max = 156 },
319 .p = { .min = 10, .max = 30 },
75e53986 320 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 321 .p2 = { .dot_limit = 270000,
322 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 323};
324
325static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 326 .dot = { .min = 25000, .max = 270000 },
327 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 328 .n = { .min = 1, .max = 7 },
329 .m = { .min = 60, .max = 300 }, /* guess */
330 .m1 = { .min = 2, .max = 3 },
331 .m2 = { .min = 11, .max = 156 },
332 .p = { .min = 10, .max = 30 },
333 .p1 = { .min = 2, .max = 3 },
334 .p2 = { .dot_limit = 270000,
335 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 336};
337
e0638cdf
PZ		 338/**
339 * Returns whether any output on the specified pipe is of the specified type
340 */
341static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
342{
343 struct drm_device *dev = crtc->dev;
344 struct intel_encoder *encoder;
345
346 for_each_encoder_on_crtc(dev, crtc, encoder)
347 if (encoder->type == type)
348 return true;
349
350 return false;
351}
352
1b894b59
CW		 353static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
354 int refclk)
2c07245f 355{
b91ad0ec 356 struct drm_device *dev = crtc->dev;
2c07245f 357 const intel_limit_t *limit;
b91ad0ec
ZW		 358
359 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 360 if (intel_is_dual_link_lvds(dev)) {
1b894b59 361 if (refclk == 100000)
b91ad0ec
ZW		 362 limit = &intel_limits_ironlake_dual_lvds_100m;
363 else
364 limit = &intel_limits_ironlake_dual_lvds;
365 } else {
1b894b59 366 if (refclk == 100000)
b91ad0ec
ZW		 367 limit = &intel_limits_ironlake_single_lvds_100m;
368 else
369 limit = &intel_limits_ironlake_single_lvds;
370 }
c6bb3538 371 } else
b91ad0ec 372 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 373
374 return limit;
375}
376
044c7c41
ML		 377static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
378{
379 struct drm_device *dev = crtc->dev;
044c7c41
ML		 380 const intel_limit_t *limit;
381
382 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 383 if (intel_is_dual_link_lvds(dev))
e4b36699 384 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 385 else
e4b36699 386 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 387 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
388 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 389 limit = &intel_limits_g4x_hdmi;
044c7c41 390 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 391 limit = &intel_limits_g4x_sdvo;
044c7c41 392 } else /* The option is for other outputs */
e4b36699 393 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 394
395 return limit;
396}
397
1b894b59 398static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 399{
400 struct drm_device *dev = crtc->dev;
401 const intel_limit_t *limit;
402
bad720ff 403 if (HAS_PCH_SPLIT(dev))
1b894b59 404 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 405 else if (IS_G4X(dev)) {
044c7c41 406 limit = intel_g4x_limit(crtc);
f2b115e6 407 } else if (IS_PINEVIEW(dev)) {
2177832f 408 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 409 limit = &intel_limits_pineview_lvds;
2177832f 410 else
f2b115e6 411 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 412 } else if (IS_VALLEYVIEW(dev)) {
413 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
414 limit = &intel_limits_vlv_dac;
a0c4da24 415 else
65ce4bf5 416 limit = &intel_limits_vlv_hdmi;
a6c45cf0
CW		 417 } else if (!IS_GEN2(dev)) {
418 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
419 limit = &intel_limits_i9xx_lvds;
420 else
421 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 422 } else {
423 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 424 limit = &intel_limits_i8xx_lvds;
5d536e28 425 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
e4b36699 426 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 427 else
428 limit = &intel_limits_i8xx_dac;
79e53945
JB		 429 }
430 return limit;
431}
432
f2b115e6
AJ		 433/* m1 is reserved as 0 in Pineview, n is a ring counter */
434static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 435{
2177832f
SL		 436 clock->m = clock->m2 + 2;
437 clock->p = clock->p1 * clock->p2;
438 clock->vco = refclk * clock->m / clock->n;
439 clock->dot = clock->vco / clock->p;
440}
441
7429e9d4
DV		 442static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
443{
444 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
445}
446
ac58c3f0 447static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 448{
7429e9d4 449 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 450 clock->p = clock->p1 * clock->p2;
451 clock->vco = refclk * clock->m / (clock->n + 2);
452 clock->dot = clock->vco / clock->p;
453}
454
7c04d1d9 455#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 456/**
457 * Returns whether the given set of divisors are valid for a given refclk with
458 * the given connectors.
459 */
460
1b894b59
CW		 461static bool intel_PLL_is_valid(struct drm_device *dev,
462 const intel_limit_t *limit,
463 const intel_clock_t *clock)
79e53945 464{
79e53945 465 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 466 INTELPllInvalid("p1 out of range\n");
79e53945 467 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 468 INTELPllInvalid("p out of range\n");
79e53945 469 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 470 INTELPllInvalid("m2 out of range\n");
79e53945 471 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 472 INTELPllInvalid("m1 out of range\n");
f2b115e6 473 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 474 INTELPllInvalid("m1 <= m2\n");
79e53945 475 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 476 INTELPllInvalid("m out of range\n");
79e53945 477 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 478 INTELPllInvalid("n out of range\n");
79e53945 479 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 480 INTELPllInvalid("vco out of range\n");
79e53945
JB		 481 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
482 * connector, etc., rather than just a single range.
483 */
484 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 485 INTELPllInvalid("dot out of range\n");
79e53945
JB		 486
487 return true;
488}
489
d4906093 490static bool
ee9300bb 491i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 492 int target, int refclk, intel_clock_t *match_clock,
493 intel_clock_t *best_clock)
79e53945
JB		 494{
495 struct drm_device *dev = crtc->dev;
79e53945 496 intel_clock_t clock;
79e53945
JB		 497 int err = target;
498
a210b028 499 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 500 /*
a210b028
DV		 501 * For LVDS just rely on its current settings for dual-channel.
502 * We haven't figured out how to reliably set up different
503 * single/dual channel state, if we even can.
79e53945 504 */
1974cad0 505 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 506 clock.p2 = limit->p2.p2_fast;
507 else
508 clock.p2 = limit->p2.p2_slow;
509 } else {
510 if (target < limit->p2.dot_limit)
511 clock.p2 = limit->p2.p2_slow;
512 else
513 clock.p2 = limit->p2.p2_fast;
514 }
515
0206e353 516 memset(best_clock, 0, sizeof(*best_clock));
79e53945 517
42158660
ZY		 518 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
519 clock.m1++) {
520 for (clock.m2 = limit->m2.min;
521 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 522 if (clock.m2 >= clock.m1)
42158660
ZY		 523 break;
524 for (clock.n = limit->n.min;
525 clock.n <= limit->n.max; clock.n++) {
526 for (clock.p1 = limit->p1.min;
527 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 528 int this_err;
529
ac58c3f0
DV		 530 i9xx_clock(refclk, &clock);
531 if (!intel_PLL_is_valid(dev, limit,
532 &clock))
533 continue;
534 if (match_clock &&
535 clock.p != match_clock->p)
536 continue;
537
538 this_err = abs(clock.dot - target);
539 if (this_err < err) {
540 *best_clock = clock;
541 err = this_err;
542 }
543 }
544 }
545 }
546 }
547
548 return (err != target);
549}
550
551static bool
ee9300bb
DV		 552pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
553 int target, int refclk, intel_clock_t *match_clock,
554 intel_clock_t *best_clock)
79e53945
JB		 555{
556 struct drm_device *dev = crtc->dev;
79e53945 557 intel_clock_t clock;
79e53945
JB		 558 int err = target;
559
a210b028 560 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 561 /*
a210b028
DV		 562 * For LVDS just rely on its current settings for dual-channel.
563 * We haven't figured out how to reliably set up different
564 * single/dual channel state, if we even can.
79e53945 565 */
1974cad0 566 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 567 clock.p2 = limit->p2.p2_fast;
568 else
569 clock.p2 = limit->p2.p2_slow;
570 } else {
571 if (target < limit->p2.dot_limit)
572 clock.p2 = limit->p2.p2_slow;
573 else
574 clock.p2 = limit->p2.p2_fast;
575 }
576
0206e353 577 memset(best_clock, 0, sizeof(*best_clock));
79e53945 578
42158660
ZY		 579 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
580 clock.m1++) {
581 for (clock.m2 = limit->m2.min;
582 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 583 for (clock.n = limit->n.min;
584 clock.n <= limit->n.max; clock.n++) {
585 for (clock.p1 = limit->p1.min;
586 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 587 int this_err;
588
ac58c3f0 589 pineview_clock(refclk, &clock);
1b894b59
CW		 590 if (!intel_PLL_is_valid(dev, limit,
591 &clock))
79e53945 592 continue;
cec2f356
SP		 593 if (match_clock &&
594 clock.p != match_clock->p)
595 continue;
79e53945
JB		 596
597 this_err = abs(clock.dot - target);
598 if (this_err < err) {
599 *best_clock = clock;
600 err = this_err;
601 }
602 }
603 }
604 }
605 }
606
607 return (err != target);
608}
609
d4906093 610static bool
ee9300bb
DV		 611g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
612 int target, int refclk, intel_clock_t *match_clock,
613 intel_clock_t *best_clock)
d4906093
ML		 614{
615 struct drm_device *dev = crtc->dev;
d4906093
ML		 616 intel_clock_t clock;
617 int max_n;
618 bool found;
6ba770dc
AJ		 619 /* approximately equals target * 0.00585 */
620 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 621 found = false;
622
623 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 624 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 625 clock.p2 = limit->p2.p2_fast;
626 else
627 clock.p2 = limit->p2.p2_slow;
628 } else {
629 if (target < limit->p2.dot_limit)
630 clock.p2 = limit->p2.p2_slow;
631 else
632 clock.p2 = limit->p2.p2_fast;
633 }
634
635 memset(best_clock, 0, sizeof(*best_clock));
636 max_n = limit->n.max;
f77f13e2 637 /* based on hardware requirement, prefer smaller n to precision */
d4906093 638 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 639 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 640 for (clock.m1 = limit->m1.max;
641 clock.m1 >= limit->m1.min; clock.m1--) {
642 for (clock.m2 = limit->m2.max;
643 clock.m2 >= limit->m2.min; clock.m2--) {
644 for (clock.p1 = limit->p1.max;
645 clock.p1 >= limit->p1.min; clock.p1--) {
646 int this_err;
647
ac58c3f0 648 i9xx_clock(refclk, &clock);
1b894b59
CW		 649 if (!intel_PLL_is_valid(dev, limit,
650 &clock))
d4906093 651 continue;
1b894b59
CW		 652
653 this_err = abs(clock.dot - target);
d4906093
ML		 654 if (this_err < err_most) {
655 *best_clock = clock;
656 err_most = this_err;
657 max_n = clock.n;
658 found = true;
659 }
660 }
661 }
662 }
663 }
2c07245f
ZW		 664 return found;
665}
666
a0c4da24 667static bool
ee9300bb
DV		 668vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
669 int target, int refclk, intel_clock_t *match_clock,
670 intel_clock_t *best_clock)
a0c4da24
JB		 671{
672 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
673 u32 m, n, fastclk;
f3f08572 674 u32 updrate, minupdate, p;
a0c4da24
JB		 675 unsigned long bestppm, ppm, absppm;
676 int dotclk, flag;
677
af447bd3 678 flag = 0;
a0c4da24
JB		 679 dotclk = target * 1000;
680 bestppm = 1000000;
681 ppm = absppm = 0;
682 fastclk = dotclk / (2*100);
683 updrate = 0;
684 minupdate = 19200;
a0c4da24
JB		 685 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
686 bestm1 = bestm2 = bestp1 = bestp2 = 0;
687
688 /* based on hardware requirement, prefer smaller n to precision */
689 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
690 updrate = refclk / n;
691 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
692 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
693 if (p2 > 10)
694 p2 = p2 - 1;
695 p = p1 * p2;
696 /* based on hardware requirement, prefer bigger m1,m2 values */
697 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
5de56df5 698 m2 = DIV_ROUND_CLOSEST(fastclk * p * n, refclk * m1);
a0c4da24
JB		 699 m = m1 * m2;
700 vco = updrate * m;
43b0ac53
VS		 701
702 if (vco < limit->vco.min || vco >= limit->vco.max)
703 continue;
704
705 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
706 absppm = (ppm > 0) ? ppm : (-ppm);
707 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
708 bestppm = 0;
709 flag = 1;
710 }
711 if (absppm < bestppm - 10) {
712 bestppm = absppm;
713 flag = 1;
714 }
715 if (flag) {
716 bestn = n;
717 bestm1 = m1;
718 bestm2 = m2;
719 bestp1 = p1;
720 bestp2 = p2;
721 flag = 0;
a0c4da24
JB		 722 }
723 }
724 }
725 }
726 }
727 best_clock->n = bestn;
728 best_clock->m1 = bestm1;
729 best_clock->m2 = bestm2;
730 best_clock->p1 = bestp1;
731 best_clock->p2 = bestp2;
732
733 return true;
734}
a4fc5ed6 735
20ddf665
VS		 736bool intel_crtc_active(struct drm_crtc *crtc)
737{
738 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
739
740 /* Be paranoid as we can arrive here with only partial
741 * state retrieved from the hardware during setup.
742 *
241bfc38 743 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 744 * as Haswell has gained clock readout/fastboot support.
745 *
746 * We can ditch the crtc->fb check as soon as we can
747 * properly reconstruct framebuffers.
748 */
749 return intel_crtc->active && crtc->fb &&
241bfc38 750 intel_crtc->config.adjusted_mode.crtc_clock;
20ddf665
VS		 751}
752
a5c961d1
PZ		 753enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
754 enum pipe pipe)
755{
756 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
757 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
758
3b117c8f 759 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 760}
761
a928d536
PZ		 762static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
763{
764 struct drm_i915_private *dev_priv = dev->dev_private;
765 u32 frame, frame_reg = PIPEFRAME(pipe);
766
767 frame = I915_READ(frame_reg);
768
769 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
770 DRM_DEBUG_KMS("vblank wait timed out\n");
771}
772
9d0498a2
JB		 773/**
774 * intel_wait_for_vblank - wait for vblank on a given pipe
775 * @dev: drm device
776 * @pipe: pipe to wait for
777 *
778 * Wait for vblank to occur on a given pipe. Needed for various bits of
779 * mode setting code.
780 */
781void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 782{
9d0498a2 783 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 784 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 785
a928d536
PZ		 786 if (INTEL_INFO(dev)->gen >= 5) {
787 ironlake_wait_for_vblank(dev, pipe);
788 return;
789 }
790
300387c0
CW		 791 /* Clear existing vblank status. Note this will clear any other
792 * sticky status fields as well.
793 *
794 * This races with i915_driver_irq_handler() with the result
795 * that either function could miss a vblank event. Here it is not
796 * fatal, as we will either wait upon the next vblank interrupt or
797 * timeout. Generally speaking intel_wait_for_vblank() is only
798 * called during modeset at which time the GPU should be idle and
799 * should *not* be performing page flips and thus not waiting on
800 * vblanks...
801 * Currently, the result of us stealing a vblank from the irq
802 * handler is that a single frame will be skipped during swapbuffers.
803 */
804 I915_WRITE(pipestat_reg,
805 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
806
9d0498a2 807 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 808 if (wait_for(I915_READ(pipestat_reg) &
809 PIPE_VBLANK_INTERRUPT_STATUS,
810 50))
9d0498a2
JB		 811 DRM_DEBUG_KMS("vblank wait timed out\n");
812}
813
ab7ad7f6
KP		 814/*
815 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 816 * @dev: drm device
817 * @pipe: pipe to wait for
818 *
819 * After disabling a pipe, we can't wait for vblank in the usual way,
820 * spinning on the vblank interrupt status bit, since we won't actually
821 * see an interrupt when the pipe is disabled.
822 *
ab7ad7f6
KP		 823 * On Gen4 and above:
824 * wait for the pipe register state bit to turn off
825 *
826 * Otherwise:
827 * wait for the display line value to settle (it usually
828 * ends up stopping at the start of the next frame).
58e10eb9 829 *
9d0498a2 830 */
58e10eb9 831void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 832{
833 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 834 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
835 pipe);
ab7ad7f6
KP		 836
837 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 838 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 839
840 /* Wait for the Pipe State to go off */
58e10eb9
CW		 841 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
842 100))
284637d9 843 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 844 } else {
837ba00f 845 u32 last_line, line_mask;
58e10eb9 846 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 847 unsigned long timeout = jiffies + msecs_to_jiffies(100);
848
837ba00f
PZ		 849 if (IS_GEN2(dev))
850 line_mask = DSL_LINEMASK_GEN2;
851 else
852 line_mask = DSL_LINEMASK_GEN3;
853
ab7ad7f6
KP		 854 /* Wait for the display line to settle */
855 do {
837ba00f 856 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 857 mdelay(5);
837ba00f 858 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 859 time_after(timeout, jiffies));
860 if (time_after(jiffies, timeout))
284637d9 861 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 862 }
79e53945
JB		 863}
864
b0ea7d37
DL		 865/*
866 * ibx_digital_port_connected - is the specified port connected?
867 * @dev_priv: i915 private structure
868 * @port: the port to test
869 *
870 * Returns true if @port is connected, false otherwise.
871 */
872bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
873 struct intel_digital_port *port)
874{
875 u32 bit;
876
c36346e3
DL		 877 if (HAS_PCH_IBX(dev_priv->dev)) {
878 switch(port->port) {
879 case PORT_B:
880 bit = SDE_PORTB_HOTPLUG;
881 break;
882 case PORT_C:
883 bit = SDE_PORTC_HOTPLUG;
884 break;
885 case PORT_D:
886 bit = SDE_PORTD_HOTPLUG;
887 break;
888 default:
889 return true;
890 }
891 } else {
892 switch(port->port) {
893 case PORT_B:
894 bit = SDE_PORTB_HOTPLUG_CPT;
895 break;
896 case PORT_C:
897 bit = SDE_PORTC_HOTPLUG_CPT;
898 break;
899 case PORT_D:
900 bit = SDE_PORTD_HOTPLUG_CPT;
901 break;
902 default:
903 return true;
904 }
b0ea7d37
DL		 905 }
906
907 return I915_READ(SDEISR) & bit;
908}
909
b24e7179
JB		 910static const char *state_string(bool enabled)
911{
912 return enabled ? "on" : "off";
913}
914
915/* Only for pre-ILK configs */
55607e8a
DV		 916void assert_pll(struct drm_i915_private *dev_priv,
917 enum pipe pipe, bool state)
b24e7179
JB		 918{
919 int reg;
920 u32 val;
921 bool cur_state;
922
923 reg = DPLL(pipe);
924 val = I915_READ(reg);
925 cur_state = !!(val & DPLL_VCO_ENABLE);
926 WARN(cur_state != state,
927 "PLL state assertion failure (expected %s, current %s)\n",
928 state_string(state), state_string(cur_state));
929}
b24e7179 930
23538ef1
JN		 931/* XXX: the dsi pll is shared between MIPI DSI ports */
932static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
933{
934 u32 val;
935 bool cur_state;
936
937 mutex_lock(&dev_priv->dpio_lock);
938 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
939 mutex_unlock(&dev_priv->dpio_lock);
940
941 cur_state = val & DSI_PLL_VCO_EN;
942 WARN(cur_state != state,
943 "DSI PLL state assertion failure (expected %s, current %s)\n",
944 state_string(state), state_string(cur_state));
945}
946#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
947#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
948
55607e8a 949struct intel_shared_dpll *
e2b78267
DV		 950intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
951{
952 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
953
a43f6e0f 954 if (crtc->config.shared_dpll < 0)
e2b78267
DV		 955 return NULL;
956
a43f6e0f 957 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
e2b78267
DV		 958}
959
040484af 960/* For ILK+ */
55607e8a
DV		 961void assert_shared_dpll(struct drm_i915_private *dev_priv,
962 struct intel_shared_dpll *pll,
963 bool state)
040484af 964{
040484af 965 bool cur_state;
5358901f 966 struct intel_dpll_hw_state hw_state;
040484af 967
9d82aa17
ED		 968 if (HAS_PCH_LPT(dev_priv->dev)) {
969 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
970 return;
971 }
972
92b27b08 973 if (WARN (!pll,
46edb027 974 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 975 return;
ee7b9f93 976
5358901f 977 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
92b27b08 978 WARN(cur_state != state,
5358901f
DV		 979 "%s assertion failure (expected %s, current %s)\n",
980 pll->name, state_string(state), state_string(cur_state));
040484af 981}
040484af
JB		 982
983static void assert_fdi_tx(struct drm_i915_private *dev_priv,
984 enum pipe pipe, bool state)
985{
986 int reg;
987 u32 val;
988 bool cur_state;
ad80a810
PZ		 989 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
990 pipe);
040484af 991
affa9354
PZ		 992 if (HAS_DDI(dev_priv->dev)) {
993 /* DDI does not have a specific FDI_TX register */
ad80a810 994 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 995 val = I915_READ(reg);
ad80a810 996 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 997 } else {
998 reg = FDI_TX_CTL(pipe);
999 val = I915_READ(reg);
1000 cur_state = !!(val & FDI_TX_ENABLE);
1001 }
040484af
JB		 1002 WARN(cur_state != state,
1003 "FDI TX state assertion failure (expected %s, current %s)\n",
1004 state_string(state), state_string(cur_state));
1005}
1006#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1007#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1008
1009static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1010 enum pipe pipe, bool state)
1011{
1012 int reg;
1013 u32 val;
1014 bool cur_state;
1015
d63fa0dc
PZ		 1016 reg = FDI_RX_CTL(pipe);
1017 val = I915_READ(reg);
1018 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1019 WARN(cur_state != state,
1020 "FDI RX state assertion failure (expected %s, current %s)\n",
1021 state_string(state), state_string(cur_state));
1022}
1023#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1024#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1025
1026static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1027 enum pipe pipe)
1028{
1029 int reg;
1030 u32 val;
1031
1032 /* ILK FDI PLL is always enabled */
1033 if (dev_priv->info->gen == 5)
1034 return;
1035
bf507ef7 1036 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1037 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1038 return;
1039
040484af
JB		 1040 reg = FDI_TX_CTL(pipe);
1041 val = I915_READ(reg);
1042 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1043}
1044
55607e8a
DV		 1045void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1046 enum pipe pipe, bool state)
040484af
JB		 1047{
1048 int reg;
1049 u32 val;
55607e8a 1050 bool cur_state;
040484af
JB		 1051
1052 reg = FDI_RX_CTL(pipe);
1053 val = I915_READ(reg);
55607e8a
DV		 1054 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1055 WARN(cur_state != state,
1056 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1057 state_string(state), state_string(cur_state));
040484af
JB		 1058}
1059
ea0760cf
JB		 1060static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1061 enum pipe pipe)
1062{
1063 int pp_reg, lvds_reg;
1064 u32 val;
1065 enum pipe panel_pipe = PIPE_A;
0de3b485 1066 bool locked = true;
ea0760cf
JB		 1067
1068 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1069 pp_reg = PCH_PP_CONTROL;
1070 lvds_reg = PCH_LVDS;
1071 } else {
1072 pp_reg = PP_CONTROL;
1073 lvds_reg = LVDS;
1074 }
1075
1076 val = I915_READ(pp_reg);
1077 if (!(val & PANEL_POWER_ON) ||
1078 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1079 locked = false;
1080
1081 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1082 panel_pipe = PIPE_B;
1083
1084 WARN(panel_pipe == pipe && locked,
1085 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1086 pipe_name(pipe));
ea0760cf
JB		 1087}
1088
93ce0ba6
JN		 1089static void assert_cursor(struct drm_i915_private *dev_priv,
1090 enum pipe pipe, bool state)
1091{
1092 struct drm_device *dev = dev_priv->dev;
1093 bool cur_state;
1094
1095 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1096 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1097 else if (IS_845G(dev) || IS_I865G(dev))
1098 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1099 else
1100 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1101
1102 WARN(cur_state != state,
1103 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1104 pipe_name(pipe), state_string(state), state_string(cur_state));
1105}
1106#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1107#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1108
b840d907
JB		 1109void assert_pipe(struct drm_i915_private *dev_priv,
1110 enum pipe pipe, bool state)
b24e7179
JB		 1111{
1112 int reg;
1113 u32 val;
63d7bbe9 1114 bool cur_state;
702e7a56
PZ		 1115 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1116 pipe);
b24e7179 1117
8e636784
DV		 1118 /* if we need the pipe A quirk it must be always on */
1119 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1120 state = true;
1121
b97186f0
PZ		 1122 if (!intel_display_power_enabled(dev_priv->dev,
1123 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1124 cur_state = false;
1125 } else {
1126 reg = PIPECONF(cpu_transcoder);
1127 val = I915_READ(reg);
1128 cur_state = !!(val & PIPECONF_ENABLE);
1129 }
1130
63d7bbe9
JB		 1131 WARN(cur_state != state,
1132 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1133 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1134}
1135
931872fc
CW		 1136static void assert_plane(struct drm_i915_private *dev_priv,
1137 enum plane plane, bool state)
b24e7179
JB		 1138{
1139 int reg;
1140 u32 val;
931872fc 1141 bool cur_state;
b24e7179
JB		 1142
1143 reg = DSPCNTR(plane);
1144 val = I915_READ(reg);
931872fc
CW		 1145 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1146 WARN(cur_state != state,
1147 "plane %c assertion failure (expected %s, current %s)\n",
1148 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1149}
1150
931872fc
CW		 1151#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1152#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1153
b24e7179
JB		 1154static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1155 enum pipe pipe)
1156{
653e1026 1157 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1158 int reg, i;
1159 u32 val;
1160 int cur_pipe;
1161
653e1026
VS		 1162 /* Primary planes are fixed to pipes on gen4+ */
1163 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1164 reg = DSPCNTR(pipe);
1165 val = I915_READ(reg);
1166 WARN((val & DISPLAY_PLANE_ENABLE),
1167 "plane %c assertion failure, should be disabled but not\n",
1168 plane_name(pipe));
19ec1358 1169 return;
28c05794 1170 }
19ec1358 1171
b24e7179 1172 /* Need to check both planes against the pipe */
08e2a7de 1173 for_each_pipe(i) {
b24e7179
JB		 1174 reg = DSPCNTR(i);
1175 val = I915_READ(reg);
1176 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1177 DISPPLANE_SEL_PIPE_SHIFT;
1178 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1179 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1180 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1181 }
1182}
1183
19332d7a
JB		 1184static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1185 enum pipe pipe)
1186{
20674eef 1187 struct drm_device *dev = dev_priv->dev;
19332d7a
JB		 1188 int reg, i;
1189 u32 val;
1190
20674eef
VS		 1191 if (IS_VALLEYVIEW(dev)) {
1192 for (i = 0; i < dev_priv->num_plane; i++) {
1193 reg = SPCNTR(pipe, i);
1194 val = I915_READ(reg);
1195 WARN((val & SP_ENABLE),
1196 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1197 sprite_name(pipe, i), pipe_name(pipe));
1198 }
1199 } else if (INTEL_INFO(dev)->gen >= 7) {
1200 reg = SPRCTL(pipe);
19332d7a 1201 val = I915_READ(reg);
20674eef 1202 WARN((val & SPRITE_ENABLE),
06da8da2 1203 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1204 plane_name(pipe), pipe_name(pipe));
1205 } else if (INTEL_INFO(dev)->gen >= 5) {
1206 reg = DVSCNTR(pipe);
19332d7a 1207 val = I915_READ(reg);
20674eef 1208 WARN((val & DVS_ENABLE),
06da8da2 1209 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1210 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1211 }
1212}
1213
92f2584a
JB		 1214static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1215{
1216 u32 val;
1217 bool enabled;
1218
9d82aa17
ED		 1219 if (HAS_PCH_LPT(dev_priv->dev)) {
1220 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1221 return;
1222 }
1223
92f2584a
JB		 1224 val = I915_READ(PCH_DREF_CONTROL);
1225 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1226 DREF_SUPERSPREAD_SOURCE_MASK));
1227 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1228}
1229
ab9412ba
DV		 1230static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1231 enum pipe pipe)
92f2584a
JB		 1232{
1233 int reg;
1234 u32 val;
1235 bool enabled;
1236
ab9412ba 1237 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1238 val = I915_READ(reg);
1239 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1240 WARN(enabled,
1241 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1242 pipe_name(pipe));
92f2584a
JB		 1243}
1244
4e634389
KP		 1245static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1246 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1247{
1248 if ((val & DP_PORT_EN) == 0)
1249 return false;
1250
1251 if (HAS_PCH_CPT(dev_priv->dev)) {
1252 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1253 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1254 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1255 return false;
1256 } else {
1257 if ((val & DP_PIPE_MASK) != (pipe << 30))
1258 return false;
1259 }
1260 return true;
1261}
1262
1519b995
KP		 1263static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1264 enum pipe pipe, u32 val)
1265{
dc0fa718 1266 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1267 return false;
1268
1269 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1270 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1271 return false;
1272 } else {
dc0fa718 1273 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1274 return false;
1275 }
1276 return true;
1277}
1278
1279static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1280 enum pipe pipe, u32 val)
1281{
1282 if ((val & LVDS_PORT_EN) == 0)
1283 return false;
1284
1285 if (HAS_PCH_CPT(dev_priv->dev)) {
1286 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1287 return false;
1288 } else {
1289 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1290 return false;
1291 }
1292 return true;
1293}
1294
1295static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1296 enum pipe pipe, u32 val)
1297{
1298 if ((val & ADPA_DAC_ENABLE) == 0)
1299 return false;
1300 if (HAS_PCH_CPT(dev_priv->dev)) {
1301 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1302 return false;
1303 } else {
1304 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1305 return false;
1306 }
1307 return true;
1308}
1309
291906f1 1310static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1311 enum pipe pipe, int reg, u32 port_sel)
291906f1 1312{
47a05eca 1313 u32 val = I915_READ(reg);
4e634389 1314 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1315 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1316 reg, pipe_name(pipe));
de9a35ab 1317
75c5da27
DV		 1318 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1319 && (val & DP_PIPEB_SELECT),
de9a35ab 1320 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1321}
1322
1323static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1324 enum pipe pipe, int reg)
1325{
47a05eca 1326 u32 val = I915_READ(reg);
b70ad586 1327 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1328 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1329 reg, pipe_name(pipe));
de9a35ab 1330
dc0fa718 1331 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1332 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1333 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1334}
1335
1336static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1337 enum pipe pipe)
1338{
1339 int reg;
1340 u32 val;
291906f1 1341
f0575e92
KP		 1342 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1343 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1344 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1345
1346 reg = PCH_ADPA;
1347 val = I915_READ(reg);
b70ad586 1348 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1349 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1350 pipe_name(pipe));
291906f1
JB		 1351
1352 reg = PCH_LVDS;
1353 val = I915_READ(reg);
b70ad586 1354 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1355 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1356 pipe_name(pipe));
291906f1 1357
e2debe91
PZ		 1358 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1359 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1360 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1361}
1362
426115cf 1363static void vlv_enable_pll(struct intel_crtc *crtc)
87442f73 1364{
426115cf
DV		 1365 struct drm_device *dev = crtc->base.dev;
1366 struct drm_i915_private *dev_priv = dev->dev_private;
1367 int reg = DPLL(crtc->pipe);
1368 u32 dpll = crtc->config.dpll_hw_state.dpll;
87442f73 1369
426115cf 1370 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1371
1372 /* No really, not for ILK+ */
1373 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1374
1375 /* PLL is protected by panel, make sure we can write it */
1376 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
426115cf 1377 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1378
426115cf
DV		 1379 I915_WRITE(reg, dpll);
1380 POSTING_READ(reg);
1381 udelay(150);
1382
1383 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1384 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1385
1386 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1387 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1388
1389 /* We do this three times for luck */
426115cf 1390 I915_WRITE(reg, dpll);
87442f73
DV		 1391 POSTING_READ(reg);
1392 udelay(150); /* wait for warmup */
426115cf 1393 I915_WRITE(reg, dpll);
87442f73
DV		 1394 POSTING_READ(reg);
1395 udelay(150); /* wait for warmup */
426115cf 1396 I915_WRITE(reg, dpll);
87442f73
DV		 1397 POSTING_READ(reg);
1398 udelay(150); /* wait for warmup */
1399}
1400
66e3d5c0 1401static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1402{
66e3d5c0
DV		 1403 struct drm_device *dev = crtc->base.dev;
1404 struct drm_i915_private *dev_priv = dev->dev_private;
1405 int reg = DPLL(crtc->pipe);
1406 u32 dpll = crtc->config.dpll_hw_state.dpll;
63d7bbe9 1407
66e3d5c0 1408 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1409
63d7bbe9 1410 /* No really, not for ILK+ */
87442f73 1411 BUG_ON(dev_priv->info->gen >= 5);
63d7bbe9
JB		 1412
1413 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1414 if (IS_MOBILE(dev) && !IS_I830(dev))
1415 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1416
66e3d5c0
DV		 1417 I915_WRITE(reg, dpll);
1418
1419 /* Wait for the clocks to stabilize. */
1420 POSTING_READ(reg);
1421 udelay(150);
1422
1423 if (INTEL_INFO(dev)->gen >= 4) {
1424 I915_WRITE(DPLL_MD(crtc->pipe),
1425 crtc->config.dpll_hw_state.dpll_md);
1426 } else {
1427 /* The pixel multiplier can only be updated once the
1428 * DPLL is enabled and the clocks are stable.
1429 *
1430 * So write it again.
1431 */
1432 I915_WRITE(reg, dpll);
1433 }
63d7bbe9
JB		 1434
1435 /* We do this three times for luck */
66e3d5c0 1436 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1437 POSTING_READ(reg);
1438 udelay(150); /* wait for warmup */
66e3d5c0 1439 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1440 POSTING_READ(reg);
1441 udelay(150); /* wait for warmup */
66e3d5c0 1442 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1443 POSTING_READ(reg);
1444 udelay(150); /* wait for warmup */
1445}
1446
1447/**
50b44a44 1448 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1449 * @dev_priv: i915 private structure
1450 * @pipe: pipe PLL to disable
1451 *
1452 * Disable the PLL for @pipe, making sure the pipe is off first.
1453 *
1454 * Note! This is for pre-ILK only.
1455 */
50b44a44 1456static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9 1457{
63d7bbe9
JB		 1458 /* Don't disable pipe A or pipe A PLLs if needed */
1459 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1460 return;
1461
1462 /* Make sure the pipe isn't still relying on us */
1463 assert_pipe_disabled(dev_priv, pipe);
1464
50b44a44
DV		 1465 I915_WRITE(DPLL(pipe), 0);
1466 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1467}
1468
f6071166
JB		 1469static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1470{
1471 u32 val = 0;
1472
1473 /* Make sure the pipe isn't still relying on us */
1474 assert_pipe_disabled(dev_priv, pipe);
1475
1476 /* Leave integrated clock source enabled */
1477 if (pipe == PIPE_B)
1478 val = DPLL_INTEGRATED_CRI_CLK_VLV;
1479 I915_WRITE(DPLL(pipe), val);
1480 POSTING_READ(DPLL(pipe));
1481}
1482
89b667f8
JB		 1483void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1484{
1485 u32 port_mask;
1486
1487 if (!port)
1488 port_mask = DPLL_PORTB_READY_MASK;
1489 else
1490 port_mask = DPLL_PORTC_READY_MASK;
1491
1492 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1493 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1494 'B' + port, I915_READ(DPLL(0)));
1495}
1496
92f2584a 1497/**
e72f9fbf 1498 * ironlake_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1499 * @dev_priv: i915 private structure
1500 * @pipe: pipe PLL to enable
1501 *
1502 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1503 * drives the transcoder clock.
1504 */
e2b78267 1505static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1506{
e2b78267
DV		 1507 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1508 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1509
48da64a8 1510 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1511 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1512 if (WARN_ON(pll == NULL))
48da64a8
CW		 1513 return;
1514
1515 if (WARN_ON(pll->refcount == 0))
1516 return;
ee7b9f93 1517
46edb027
DV		 1518 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1519 pll->name, pll->active, pll->on,
e2b78267 1520 crtc->base.base.id);
92f2584a 1521
cdbd2316
DV		 1522 if (pll->active++) {
1523 WARN_ON(!pll->on);
e9d6944e 1524 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1525 return;
1526 }
f4a091c7 1527 WARN_ON(pll->on);
ee7b9f93 1528
46edb027 1529 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1530 pll->enable(dev_priv, pll);
ee7b9f93 1531 pll->on = true;
92f2584a
JB		 1532}
1533
e2b78267 1534static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1535{
e2b78267
DV		 1536 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1537 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1538
92f2584a
JB		 1539 /* PCH only available on ILK+ */
1540 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1541 if (WARN_ON(pll == NULL))
ee7b9f93 1542 return;
92f2584a 1543
48da64a8
CW		 1544 if (WARN_ON(pll->refcount == 0))
1545 return;
7a419866 1546
46edb027
DV		 1547 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1548 pll->name, pll->active, pll->on,
e2b78267 1549 crtc->base.base.id);
7a419866 1550
48da64a8 1551 if (WARN_ON(pll->active == 0)) {
e9d6944e 1552 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1553 return;
1554 }
1555
e9d6944e 1556 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1557 WARN_ON(!pll->on);
cdbd2316 1558 if (--pll->active)
7a419866 1559 return;
ee7b9f93 1560
46edb027 1561 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1562 pll->disable(dev_priv, pll);
ee7b9f93 1563 pll->on = false;
92f2584a
JB		 1564}
1565
b8a4f404
PZ		 1566static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1567 enum pipe pipe)
040484af 1568{
23670b32 1569 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1570 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1571 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1572 uint32_t reg, val, pipeconf_val;
040484af
JB		 1573
1574 /* PCH only available on ILK+ */
1575 BUG_ON(dev_priv->info->gen < 5);
1576
1577 /* Make sure PCH DPLL is enabled */
e72f9fbf 1578 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1579 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1580
1581 /* FDI must be feeding us bits for PCH ports */
1582 assert_fdi_tx_enabled(dev_priv, pipe);
1583 assert_fdi_rx_enabled(dev_priv, pipe);
1584
23670b32
DV		 1585 if (HAS_PCH_CPT(dev)) {
1586 /* Workaround: Set the timing override bit before enabling the
1587 * pch transcoder. */
1588 reg = TRANS_CHICKEN2(pipe);
1589 val = I915_READ(reg);
1590 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1591 I915_WRITE(reg, val);
59c859d6 1592 }
23670b32 1593
ab9412ba 1594 reg = PCH_TRANSCONF(pipe);
040484af 1595 val = I915_READ(reg);
5f7f726d 1596 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1597
1598 if (HAS_PCH_IBX(dev_priv->dev)) {
1599 /*
1600 * make the BPC in transcoder be consistent with
1601 * that in pipeconf reg.
1602 */
dfd07d72
DV		 1603 val &= ~PIPECONF_BPC_MASK;
1604 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1605 }
5f7f726d
PZ		 1606
1607 val &= ~TRANS_INTERLACE_MASK;
1608 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1609 if (HAS_PCH_IBX(dev_priv->dev) &&
1610 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1611 val |= TRANS_LEGACY_INTERLACED_ILK;
1612 else
1613 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1614 else
1615 val |= TRANS_PROGRESSIVE;
1616
040484af
JB		 1617 I915_WRITE(reg, val | TRANS_ENABLE);
1618 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1619 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1620}
1621
8fb033d7 1622static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1623 enum transcoder cpu_transcoder)
040484af 1624{
8fb033d7 1625 u32 val, pipeconf_val;
8fb033d7
PZ		 1626
1627 /* PCH only available on ILK+ */
1628 BUG_ON(dev_priv->info->gen < 5);
1629
8fb033d7 1630 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1631 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1632 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1633
223a6fdf
PZ		 1634 /* Workaround: set timing override bit. */
1635 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1636 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1637 I915_WRITE(_TRANSA_CHICKEN2, val);
1638
25f3ef11 1639 val = TRANS_ENABLE;
937bb610 1640 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1641
9a76b1c6
PZ		 1642 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1643 PIPECONF_INTERLACED_ILK)
a35f2679 1644 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1645 else
1646 val |= TRANS_PROGRESSIVE;
1647
ab9412ba
DV		 1648 I915_WRITE(LPT_TRANSCONF, val);
1649 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1650 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1651}
1652
b8a4f404
PZ		 1653static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1654 enum pipe pipe)
040484af 1655{
23670b32
DV		 1656 struct drm_device *dev = dev_priv->dev;
1657 uint32_t reg, val;
040484af
JB		 1658
1659 /* FDI relies on the transcoder */
1660 assert_fdi_tx_disabled(dev_priv, pipe);
1661 assert_fdi_rx_disabled(dev_priv, pipe);
1662
291906f1
JB		 1663 /* Ports must be off as well */
1664 assert_pch_ports_disabled(dev_priv, pipe);
1665
ab9412ba 1666 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1667 val = I915_READ(reg);
1668 val &= ~TRANS_ENABLE;
1669 I915_WRITE(reg, val);
1670 /* wait for PCH transcoder off, transcoder state */
1671 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1672 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1673
1674 if (!HAS_PCH_IBX(dev)) {
1675 /* Workaround: Clear the timing override chicken bit again. */
1676 reg = TRANS_CHICKEN2(pipe);
1677 val = I915_READ(reg);
1678 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1679 I915_WRITE(reg, val);
1680 }
040484af
JB		 1681}
1682
ab4d966c 1683static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1684{
8fb033d7
PZ		 1685 u32 val;
1686
ab9412ba 1687 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1688 val &= ~TRANS_ENABLE;
ab9412ba 1689 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1690 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1691 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1692 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1693
1694 /* Workaround: clear timing override bit. */
1695 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1696 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1697 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1698}
1699
b24e7179 1700/**
309cfea8 1701 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1702 * @dev_priv: i915 private structure
1703 * @pipe: pipe to enable
040484af 1704 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1705 *
1706 * Enable @pipe, making sure that various hardware specific requirements
1707 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1708 *
1709 * @pipe should be %PIPE_A or %PIPE_B.
1710 *
1711 * Will wait until the pipe is actually running (i.e. first vblank) before
1712 * returning.
1713 */
040484af 1714static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
23538ef1 1715 bool pch_port, bool dsi)
b24e7179 1716{
702e7a56
PZ		 1717 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1718 pipe);
1a240d4d 1719 enum pipe pch_transcoder;
b24e7179
JB		 1720 int reg;
1721 u32 val;
1722
58c6eaa2 1723 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 1724 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 1725 assert_sprites_disabled(dev_priv, pipe);
1726
681e5811 1727 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1728 pch_transcoder = TRANSCODER_A;
1729 else
1730 pch_transcoder = pipe;
1731
b24e7179
JB		 1732 /*
1733 * A pipe without a PLL won't actually be able to drive bits from
1734 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1735 * need the check.
1736 */
1737 if (!HAS_PCH_SPLIT(dev_priv->dev))
23538ef1
JN		 1738 if (dsi)
1739 assert_dsi_pll_enabled(dev_priv);
1740 else
1741 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1742 else {
1743 if (pch_port) {
1744 /* if driving the PCH, we need FDI enabled */
cc391bbb 1745 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1746 assert_fdi_tx_pll_enabled(dev_priv,
1747 (enum pipe) cpu_transcoder);
040484af
JB		 1748 }
1749 /* FIXME: assert CPU port conditions for SNB+ */
1750 }
b24e7179 1751
702e7a56 1752 reg = PIPECONF(cpu_transcoder);
b24e7179 1753 val = I915_READ(reg);
00d70b15
CW		 1754 if (val & PIPECONF_ENABLE)
1755 return;
1756
1757 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1758 intel_wait_for_vblank(dev_priv->dev, pipe);
1759}
1760
1761/**
309cfea8 1762 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1763 * @dev_priv: i915 private structure
1764 * @pipe: pipe to disable
1765 *
1766 * Disable @pipe, making sure that various hardware specific requirements
1767 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1768 *
1769 * @pipe should be %PIPE_A or %PIPE_B.
1770 *
1771 * Will wait until the pipe has shut down before returning.
1772 */
1773static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1774 enum pipe pipe)
1775{
702e7a56
PZ		 1776 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1777 pipe);
b24e7179
JB		 1778 int reg;
1779 u32 val;
1780
1781 /*
1782 * Make sure planes won't keep trying to pump pixels to us,
1783 * or we might hang the display.
1784 */
1785 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 1786 assert_cursor_disabled(dev_priv, pipe);
19332d7a 1787 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1788
1789 /* Don't disable pipe A or pipe A PLLs if needed */
1790 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1791 return;
1792
702e7a56 1793 reg = PIPECONF(cpu_transcoder);
b24e7179 1794 val = I915_READ(reg);
00d70b15
CW		 1795 if ((val & PIPECONF_ENABLE) == 0)
1796 return;
1797
1798 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1799 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1800}
1801
d74362c9
KP		 1802/*
1803 * Plane regs are double buffered, going from enabled->disabled needs a
1804 * trigger in order to latch. The display address reg provides this.
1805 */
6f1d69b0 1806void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1807 enum plane plane)
1808{
14f86147
DL		 1809 if (dev_priv->info->gen >= 4)
1810 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1811 else
1812 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1813}
1814
b24e7179
JB		 1815/**
1816 * intel_enable_plane - enable a display plane on a given pipe
1817 * @dev_priv: i915 private structure
1818 * @plane: plane to enable
1819 * @pipe: pipe being fed
1820 *
1821 * Enable @plane on @pipe, making sure that @pipe is running first.
1822 */
1823static void intel_enable_plane(struct drm_i915_private *dev_priv,
1824 enum plane plane, enum pipe pipe)
1825{
1826 int reg;
1827 u32 val;
1828
1829 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1830 assert_pipe_enabled(dev_priv, pipe);
1831
1832 reg = DSPCNTR(plane);
1833 val = I915_READ(reg);
00d70b15
CW		 1834 if (val & DISPLAY_PLANE_ENABLE)
1835 return;
1836
1837 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1838 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1839 intel_wait_for_vblank(dev_priv->dev, pipe);
1840}
1841
b24e7179
JB		 1842/**
1843 * intel_disable_plane - disable a display plane
1844 * @dev_priv: i915 private structure
1845 * @plane: plane to disable
1846 * @pipe: pipe consuming the data
1847 *
1848 * Disable @plane; should be an independent operation.
1849 */
1850static void intel_disable_plane(struct drm_i915_private *dev_priv,
1851 enum plane plane, enum pipe pipe)
1852{
1853 int reg;
1854 u32 val;
1855
1856 reg = DSPCNTR(plane);
1857 val = I915_READ(reg);
00d70b15
CW		 1858 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1859 return;
1860
1861 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1862 intel_flush_display_plane(dev_priv, plane);
1863 intel_wait_for_vblank(dev_priv->dev, pipe);
1864}
1865
693db184
CW		 1866static bool need_vtd_wa(struct drm_device *dev)
1867{
1868#ifdef CONFIG_INTEL_IOMMU
1869 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1870 return true;
1871#endif
1872 return false;
1873}
1874
127bd2ac 1875int
48b956c5 1876intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1877 struct drm_i915_gem_object *obj,
919926ae 1878 struct intel_ring_buffer *pipelined)
6b95a207 1879{
ce453d81 1880 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1881 u32 alignment;
1882 int ret;
1883
05394f39 1884 switch (obj->tiling_mode) {
6b95a207 1885 case I915_TILING_NONE:
534843da
CW		 1886 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1887 alignment = 128 * 1024;
a6c45cf0 1888 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1889 alignment = 4 * 1024;
1890 else
1891 alignment = 64 * 1024;
6b95a207
KH		 1892 break;
1893 case I915_TILING_X:
1894 /* pin() will align the object as required by fence */
1895 alignment = 0;
1896 break;
1897 case I915_TILING_Y:
8bb6e959
DV		 1898 /* Despite that we check this in framebuffer_init userspace can
1899 * screw us over and change the tiling after the fact. Only
1900 * pinned buffers can't change their tiling. */
1901 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1902 return -EINVAL;
1903 default:
1904 BUG();
1905 }
1906
693db184
CW		 1907 /* Note that the w/a also requires 64 PTE of padding following the
1908 * bo. We currently fill all unused PTE with the shadow page and so
1909 * we should always have valid PTE following the scanout preventing
1910 * the VT-d warning.
1911 */
1912 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1913 alignment = 256 * 1024;
1914
ce453d81 1915 dev_priv->mm.interruptible = false;
2da3b9b9 1916 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1917 if (ret)
ce453d81 1918 goto err_interruptible;
6b95a207
KH		 1919
1920 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1921 * fence, whereas 965+ only requires a fence if using
1922 * framebuffer compression. For simplicity, we always install
1923 * a fence as the cost is not that onerous.
1924 */
06d98131 1925 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1926 if (ret)
1927 goto err_unpin;
1690e1eb 1928
9a5a53b3 1929 i915_gem_object_pin_fence(obj);
6b95a207 1930
ce453d81 1931 dev_priv->mm.interruptible = true;
6b95a207 1932 return 0;
48b956c5
CW		 1933
1934err_unpin:
cc98b413 1935 i915_gem_object_unpin_from_display_plane(obj);
ce453d81
CW		 1936err_interruptible:
1937 dev_priv->mm.interruptible = true;
48b956c5 1938 return ret;
6b95a207
KH		 1939}
1940
1690e1eb
CW		 1941void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1942{
1943 i915_gem_object_unpin_fence(obj);
cc98b413 1944 i915_gem_object_unpin_from_display_plane(obj);
1690e1eb
CW		 1945}
1946
c2c75131
DV		 1947/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1948 * is assumed to be a power-of-two. */
bc752862
CW		 1949unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1950 unsigned int tiling_mode,
1951 unsigned int cpp,
1952 unsigned int pitch)
c2c75131 1953{
bc752862
CW		 1954 if (tiling_mode != I915_TILING_NONE) {
1955 unsigned int tile_rows, tiles;
c2c75131 1956
bc752862
CW		 1957 tile_rows = *y / 8;
1958 *y %= 8;
c2c75131 1959
bc752862
CW		 1960 tiles = *x / (512/cpp);
1961 *x %= 512/cpp;
1962
1963 return tile_rows * pitch * 8 + tiles * 4096;
1964 } else {
1965 unsigned int offset;
1966
1967 offset = *y * pitch + *x * cpp;
1968 *y = 0;
1969 *x = (offset & 4095) / cpp;
1970 return offset & -4096;
1971 }
c2c75131
DV		 1972}
1973
17638cd6
JB		 1974static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1975 int x, int y)
81255565
JB		 1976{
1977 struct drm_device *dev = crtc->dev;
1978 struct drm_i915_private *dev_priv = dev->dev_private;
1979 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1980 struct intel_framebuffer *intel_fb;
05394f39 1981 struct drm_i915_gem_object *obj;
81255565 1982 int plane = intel_crtc->plane;
e506a0c6 1983 unsigned long linear_offset;
81255565 1984 u32 dspcntr;
5eddb70b 1985 u32 reg;
81255565
JB		 1986
1987 switch (plane) {
1988 case 0:
1989 case 1:
1990 break;
1991 default:
84f44ce7 1992 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 1993 return -EINVAL;
1994 }
1995
1996 intel_fb = to_intel_framebuffer(fb);
1997 obj = intel_fb->obj;
81255565 1998
5eddb70b
CW		 1999 reg = DSPCNTR(plane);
2000 dspcntr = I915_READ(reg);
81255565
JB		 2001 /* Mask out pixel format bits in case we change it */
2002 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2003 switch (fb->pixel_format) {
2004 case DRM_FORMAT_C8:
81255565
JB		 2005 dspcntr |= DISPPLANE_8BPP;
2006 break;
57779d06
VS		 2007 case DRM_FORMAT_XRGB1555:
2008 case DRM_FORMAT_ARGB1555:
2009 dspcntr |= DISPPLANE_BGRX555;
81255565 2010 break;
57779d06
VS		 2011 case DRM_FORMAT_RGB565:
2012 dspcntr |= DISPPLANE_BGRX565;
2013 break;
2014 case DRM_FORMAT_XRGB8888:
2015 case DRM_FORMAT_ARGB8888:
2016 dspcntr |= DISPPLANE_BGRX888;
2017 break;
2018 case DRM_FORMAT_XBGR8888:
2019 case DRM_FORMAT_ABGR8888:
2020 dspcntr |= DISPPLANE_RGBX888;
2021 break;
2022 case DRM_FORMAT_XRGB2101010:
2023 case DRM_FORMAT_ARGB2101010:
2024 dspcntr |= DISPPLANE_BGRX101010;
2025 break;
2026 case DRM_FORMAT_XBGR2101010:
2027 case DRM_FORMAT_ABGR2101010:
2028 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2029 break;
2030 default:
baba133a 2031 BUG();
81255565 2032 }
57779d06 2033
a6c45cf0 2034 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2035 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2036 dspcntr |= DISPPLANE_TILED;
2037 else
2038 dspcntr &= ~DISPPLANE_TILED;
2039 }
2040
de1aa629
VS		 2041 if (IS_G4X(dev))
2042 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2043
5eddb70b 2044 I915_WRITE(reg, dspcntr);
81255565 2045
e506a0c6 2046 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2047
c2c75131
DV		 2048 if (INTEL_INFO(dev)->gen >= 4) {
2049 intel_crtc->dspaddr_offset =
bc752862
CW		 2050 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2051 fb->bits_per_pixel / 8,
2052 fb->pitches[0]);
c2c75131
DV		 2053 linear_offset -= intel_crtc->dspaddr_offset;
2054 } else {
e506a0c6 2055 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2056 }
e506a0c6 2057
f343c5f6
BW		 2058 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2059 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2060 fb->pitches[0]);
01f2c773 2061 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2062 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131 2063 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2064 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2065 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2066 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2067 } else
f343c5f6 2068 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2069 POSTING_READ(reg);
81255565 2070
17638cd6
JB		 2071 return 0;
2072}
2073
2074static int ironlake_update_plane(struct drm_crtc *crtc,
2075 struct drm_framebuffer *fb, int x, int y)
2076{
2077 struct drm_device *dev = crtc->dev;
2078 struct drm_i915_private *dev_priv = dev->dev_private;
2079 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2080 struct intel_framebuffer *intel_fb;
2081 struct drm_i915_gem_object *obj;
2082 int plane = intel_crtc->plane;
e506a0c6 2083 unsigned long linear_offset;
17638cd6
JB		 2084 u32 dspcntr;
2085 u32 reg;
2086
2087 switch (plane) {
2088 case 0:
2089 case 1:
27f8227b 2090 case 2:
17638cd6
JB		 2091 break;
2092 default:
84f44ce7 2093 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2094 return -EINVAL;
2095 }
2096
2097 intel_fb = to_intel_framebuffer(fb);
2098 obj = intel_fb->obj;
2099
2100 reg = DSPCNTR(plane);
2101 dspcntr = I915_READ(reg);
2102 /* Mask out pixel format bits in case we change it */
2103 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2104 switch (fb->pixel_format) {
2105 case DRM_FORMAT_C8:
17638cd6
JB		 2106 dspcntr |= DISPPLANE_8BPP;
2107 break;
57779d06
VS		 2108 case DRM_FORMAT_RGB565:
2109 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2110 break;
57779d06
VS		 2111 case DRM_FORMAT_XRGB8888:
2112 case DRM_FORMAT_ARGB8888:
2113 dspcntr |= DISPPLANE_BGRX888;
2114 break;
2115 case DRM_FORMAT_XBGR8888:
2116 case DRM_FORMAT_ABGR8888:
2117 dspcntr |= DISPPLANE_RGBX888;
2118 break;
2119 case DRM_FORMAT_XRGB2101010:
2120 case DRM_FORMAT_ARGB2101010:
2121 dspcntr |= DISPPLANE_BGRX101010;
2122 break;
2123 case DRM_FORMAT_XBGR2101010:
2124 case DRM_FORMAT_ABGR2101010:
2125 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2126 break;
2127 default:
baba133a 2128 BUG();
17638cd6
JB		 2129 }
2130
2131 if (obj->tiling_mode != I915_TILING_NONE)
2132 dspcntr |= DISPPLANE_TILED;
2133 else
2134 dspcntr &= ~DISPPLANE_TILED;
2135
1f5d76db
PZ		 2136 if (IS_HASWELL(dev))
2137 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2138 else
2139 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6
JB		 2140
2141 I915_WRITE(reg, dspcntr);
2142
e506a0c6 2143 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2144 intel_crtc->dspaddr_offset =
bc752862
CW		 2145 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2146 fb->bits_per_pixel / 8,
2147 fb->pitches[0]);
c2c75131 2148 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2149
f343c5f6
BW		 2150 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2151 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2152 fb->pitches[0]);
01f2c773 2153 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131 2154 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2155 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2156 if (IS_HASWELL(dev)) {
2157 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2158 } else {
2159 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2160 I915_WRITE(DSPLINOFF(plane), linear_offset);
2161 }
17638cd6
JB		 2162 POSTING_READ(reg);
2163
2164 return 0;
2165}
2166
2167/* Assume fb object is pinned & idle & fenced and just update base pointers */
2168static int
2169intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2170 int x, int y, enum mode_set_atomic state)
2171{
2172 struct drm_device *dev = crtc->dev;
2173 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2174
6b8e6ed0
CW		 2175 if (dev_priv->display.disable_fbc)
2176 dev_priv->display.disable_fbc(dev);
3dec0095 2177 intel_increase_pllclock(crtc);
81255565 2178
6b8e6ed0 2179 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2180}
2181
96a02917
VS		 2182void intel_display_handle_reset(struct drm_device *dev)
2183{
2184 struct drm_i915_private *dev_priv = dev->dev_private;
2185 struct drm_crtc *crtc;
2186
2187 /*
2188 * Flips in the rings have been nuked by the reset,
2189 * so complete all pending flips so that user space
2190 * will get its events and not get stuck.
2191 *
2192 * Also update the base address of all primary
2193 * planes to the the last fb to make sure we're
2194 * showing the correct fb after a reset.
2195 *
2196 * Need to make two loops over the crtcs so that we
2197 * don't try to grab a crtc mutex before the
2198 * pending_flip_queue really got woken up.
2199 */
2200
2201 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2202 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2203 enum plane plane = intel_crtc->plane;
2204
2205 intel_prepare_page_flip(dev, plane);
2206 intel_finish_page_flip_plane(dev, plane);
2207 }
2208
2209 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2210 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2211
2212 mutex_lock(&crtc->mutex);
2213 if (intel_crtc->active)
2214 dev_priv->display.update_plane(crtc, crtc->fb,
2215 crtc->x, crtc->y);
2216 mutex_unlock(&crtc->mutex);
2217 }
2218}
2219
14667a4b
CW		 2220static int
2221intel_finish_fb(struct drm_framebuffer *old_fb)
2222{
2223 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2224 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2225 bool was_interruptible = dev_priv->mm.interruptible;
2226 int ret;
2227
14667a4b
CW		 2228 /* Big Hammer, we also need to ensure that any pending
2229 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2230 * current scanout is retired before unpinning the old
2231 * framebuffer.
2232 *
2233 * This should only fail upon a hung GPU, in which case we
2234 * can safely continue.
2235 */
2236 dev_priv->mm.interruptible = false;
2237 ret = i915_gem_object_finish_gpu(obj);
2238 dev_priv->mm.interruptible = was_interruptible;
2239
2240 return ret;
2241}
2242
198598d0
VS		 2243static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2244{
2245 struct drm_device *dev = crtc->dev;
2246 struct drm_i915_master_private *master_priv;
2247 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2248
2249 if (!dev->primary->master)
2250 return;
2251
2252 master_priv = dev->primary->master->driver_priv;
2253 if (!master_priv->sarea_priv)
2254 return;
2255
2256 switch (intel_crtc->pipe) {
2257 case 0:
2258 master_priv->sarea_priv->pipeA_x = x;
2259 master_priv->sarea_priv->pipeA_y = y;
2260 break;
2261 case 1:
2262 master_priv->sarea_priv->pipeB_x = x;
2263 master_priv->sarea_priv->pipeB_y = y;
2264 break;
2265 default:
2266 break;
2267 }
2268}
2269
5c3b82e2 2270static int
3c4fdcfb 2271intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2272 struct drm_framebuffer *fb)
79e53945
JB		 2273{
2274 struct drm_device *dev = crtc->dev;
6b8e6ed0 2275 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2276 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2277 struct drm_framebuffer *old_fb;
5c3b82e2 2278 int ret;
79e53945
JB		 2279
2280 /* no fb bound */
94352cf9 2281 if (!fb) {
a5071c2f 2282 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2283 return 0;
2284 }
2285
7eb552ae 2286 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2287 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2288 plane_name(intel_crtc->plane),
2289 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2290 return -EINVAL;
79e53945
JB		 2291 }
2292
5c3b82e2 2293 mutex_lock(&dev->struct_mutex);
265db958 2294 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2295 to_intel_framebuffer(fb)->obj,
919926ae 2296 NULL);
5c3b82e2
CW		 2297 if (ret != 0) {
2298 mutex_unlock(&dev->struct_mutex);
a5071c2f 2299 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2300 return ret;
2301 }
79e53945 2302
4d6a3e63
JB		 2303 /* Update pipe size and adjust fitter if needed */
2304 if (i915_fastboot) {
2305 I915_WRITE(PIPESRC(intel_crtc->pipe),
2306 ((crtc->mode.hdisplay - 1) << 16) |
2307 (crtc->mode.vdisplay - 1));
fd4daa9c 2308 if (!intel_crtc->config.pch_pfit.enabled &&
4d6a3e63
JB		 2309 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2310 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2311 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2312 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2313 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2314 }
2315 }
2316
94352cf9 2317 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2318 if (ret) {
94352cf9 2319 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2320 mutex_unlock(&dev->struct_mutex);
a5071c2f 2321 DRM_ERROR("failed to update base address\n");
4e6cfefc 2322 return ret;
79e53945 2323 }
3c4fdcfb 2324
94352cf9
DV		 2325 old_fb = crtc->fb;
2326 crtc->fb = fb;
6c4c86f5
DV		 2327 crtc->x = x;
2328 crtc->y = y;
94352cf9 2329
b7f1de28 2330 if (old_fb) {
d7697eea
DV		 2331 if (intel_crtc->active && old_fb != fb)
2332 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2333 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2334 }
652c393a 2335
6b8e6ed0 2336 intel_update_fbc(dev);
4906557e 2337 intel_edp_psr_update(dev);
5c3b82e2 2338 mutex_unlock(&dev->struct_mutex);
79e53945 2339
198598d0 2340 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2341
2342 return 0;
79e53945
JB		 2343}
2344
5e84e1a4
ZW		 2345static void intel_fdi_normal_train(struct drm_crtc *crtc)
2346{
2347 struct drm_device *dev = crtc->dev;
2348 struct drm_i915_private *dev_priv = dev->dev_private;
2349 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2350 int pipe = intel_crtc->pipe;
2351 u32 reg, temp;
2352
2353 /* enable normal train */
2354 reg = FDI_TX_CTL(pipe);
2355 temp = I915_READ(reg);
61e499bf 2356 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2357 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2358 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2359 } else {
2360 temp &= ~FDI_LINK_TRAIN_NONE;
2361 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2362 }
5e84e1a4
ZW		 2363 I915_WRITE(reg, temp);
2364
2365 reg = FDI_RX_CTL(pipe);
2366 temp = I915_READ(reg);
2367 if (HAS_PCH_CPT(dev)) {
2368 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2369 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2370 } else {
2371 temp &= ~FDI_LINK_TRAIN_NONE;
2372 temp |= FDI_LINK_TRAIN_NONE;
2373 }
2374 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2375
2376 /* wait one idle pattern time */
2377 POSTING_READ(reg);
2378 udelay(1000);
357555c0
JB		 2379
2380 /* IVB wants error correction enabled */
2381 if (IS_IVYBRIDGE(dev))
2382 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2383 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2384}
2385
1e833f40
DV		 2386static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2387{
2388 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2389}
2390
01a415fd
DV		 2391static void ivb_modeset_global_resources(struct drm_device *dev)
2392{
2393 struct drm_i915_private *dev_priv = dev->dev_private;
2394 struct intel_crtc *pipe_B_crtc =
2395 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2396 struct intel_crtc *pipe_C_crtc =
2397 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2398 uint32_t temp;
2399
1e833f40
DV		 2400 /*
2401 * When everything is off disable fdi C so that we could enable fdi B
2402 * with all lanes. Note that we don't care about enabled pipes without
2403 * an enabled pch encoder.
2404 */
2405 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2406 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2407 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2408 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2409
2410 temp = I915_READ(SOUTH_CHICKEN1);
2411 temp &= ~FDI_BC_BIFURCATION_SELECT;
2412 DRM_DEBUG_KMS("disabling fdi C rx\n");
2413 I915_WRITE(SOUTH_CHICKEN1, temp);
2414 }
2415}
2416
8db9d77b
ZW		 2417/* The FDI link training functions for ILK/Ibexpeak. */
2418static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2419{
2420 struct drm_device *dev = crtc->dev;
2421 struct drm_i915_private *dev_priv = dev->dev_private;
2422 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2423 int pipe = intel_crtc->pipe;
0fc932b8 2424 int plane = intel_crtc->plane;
5eddb70b 2425 u32 reg, temp, tries;
8db9d77b 2426
0fc932b8
JB		 2427 /* FDI needs bits from pipe & plane first */
2428 assert_pipe_enabled(dev_priv, pipe);
2429 assert_plane_enabled(dev_priv, plane);
2430
e1a44743
AJ		 2431 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2432 for train result */
5eddb70b
CW		 2433 reg = FDI_RX_IMR(pipe);
2434 temp = I915_READ(reg);
e1a44743
AJ		 2435 temp &= ~FDI_RX_SYMBOL_LOCK;
2436 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2437 I915_WRITE(reg, temp);
2438 I915_READ(reg);
e1a44743
AJ		 2439 udelay(150);
2440
8db9d77b 2441 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2442 reg = FDI_TX_CTL(pipe);
2443 temp = I915_READ(reg);
627eb5a3
DV		 2444 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2445 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2446 temp &= ~FDI_LINK_TRAIN_NONE;
2447 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2448 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2449
5eddb70b
CW		 2450 reg = FDI_RX_CTL(pipe);
2451 temp = I915_READ(reg);
8db9d77b
ZW		 2452 temp &= ~FDI_LINK_TRAIN_NONE;
2453 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2454 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2455
2456 POSTING_READ(reg);
8db9d77b
ZW		 2457 udelay(150);
2458
5b2adf89 2459 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2460 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2461 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2462 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2463
5eddb70b 2464 reg = FDI_RX_IIR(pipe);
e1a44743 2465 for (tries = 0; tries < 5; tries++) {
5eddb70b 2466 temp = I915_READ(reg);
8db9d77b
ZW		 2467 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2468
2469 if ((temp & FDI_RX_BIT_LOCK)) {
2470 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2471 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2472 break;
2473 }
8db9d77b 2474 }
e1a44743 2475 if (tries == 5)
5eddb70b 2476 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2477
2478 /* Train 2 */
5eddb70b
CW		 2479 reg = FDI_TX_CTL(pipe);
2480 temp = I915_READ(reg);
8db9d77b
ZW		 2481 temp &= ~FDI_LINK_TRAIN_NONE;
2482 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2483 I915_WRITE(reg, temp);
8db9d77b 2484
5eddb70b
CW		 2485 reg = FDI_RX_CTL(pipe);
2486 temp = I915_READ(reg);
8db9d77b
ZW		 2487 temp &= ~FDI_LINK_TRAIN_NONE;
2488 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2489 I915_WRITE(reg, temp);
8db9d77b 2490
5eddb70b
CW		 2491 POSTING_READ(reg);
2492 udelay(150);
8db9d77b 2493
5eddb70b 2494 reg = FDI_RX_IIR(pipe);
e1a44743 2495 for (tries = 0; tries < 5; tries++) {
5eddb70b 2496 temp = I915_READ(reg);
8db9d77b
ZW		 2497 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2498
2499 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2500 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2501 DRM_DEBUG_KMS("FDI train 2 done.\n");
2502 break;
2503 }
8db9d77b 2504 }
e1a44743 2505 if (tries == 5)
5eddb70b 2506 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2507
2508 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2509
8db9d77b
ZW		 2510}
2511
0206e353 2512static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2513 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2514 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2515 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2516 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2517};
2518
2519/* The FDI link training functions for SNB/Cougarpoint. */
2520static void gen6_fdi_link_train(struct drm_crtc *crtc)
2521{
2522 struct drm_device *dev = crtc->dev;
2523 struct drm_i915_private *dev_priv = dev->dev_private;
2524 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2525 int pipe = intel_crtc->pipe;
fa37d39e 2526 u32 reg, temp, i, retry;
8db9d77b 2527
e1a44743
AJ		 2528 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2529 for train result */
5eddb70b
CW		 2530 reg = FDI_RX_IMR(pipe);
2531 temp = I915_READ(reg);
e1a44743
AJ		 2532 temp &= ~FDI_RX_SYMBOL_LOCK;
2533 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2534 I915_WRITE(reg, temp);
2535
2536 POSTING_READ(reg);
e1a44743
AJ		 2537 udelay(150);
2538
8db9d77b 2539 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2540 reg = FDI_TX_CTL(pipe);
2541 temp = I915_READ(reg);
627eb5a3
DV		 2542 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2543 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2544 temp &= ~FDI_LINK_TRAIN_NONE;
2545 temp |= FDI_LINK_TRAIN_PATTERN_1;
2546 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2547 /* SNB-B */
2548 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2549 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2550
d74cf324
DV		 2551 I915_WRITE(FDI_RX_MISC(pipe),
2552 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2553
5eddb70b
CW		 2554 reg = FDI_RX_CTL(pipe);
2555 temp = I915_READ(reg);
8db9d77b
ZW		 2556 if (HAS_PCH_CPT(dev)) {
2557 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2558 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2559 } else {
2560 temp &= ~FDI_LINK_TRAIN_NONE;
2561 temp |= FDI_LINK_TRAIN_PATTERN_1;
2562 }
5eddb70b
CW		 2563 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2564
2565 POSTING_READ(reg);
8db9d77b
ZW		 2566 udelay(150);
2567
0206e353 2568 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2569 reg = FDI_TX_CTL(pipe);
2570 temp = I915_READ(reg);
8db9d77b
ZW		 2571 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2572 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2573 I915_WRITE(reg, temp);
2574
2575 POSTING_READ(reg);
8db9d77b
ZW		 2576 udelay(500);
2577
fa37d39e
SP		 2578 for (retry = 0; retry < 5; retry++) {
2579 reg = FDI_RX_IIR(pipe);
2580 temp = I915_READ(reg);
2581 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2582 if (temp & FDI_RX_BIT_LOCK) {
2583 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2584 DRM_DEBUG_KMS("FDI train 1 done.\n");
2585 break;
2586 }
2587 udelay(50);
8db9d77b 2588 }
fa37d39e
SP		 2589 if (retry < 5)
2590 break;
8db9d77b
ZW		 2591 }
2592 if (i == 4)
5eddb70b 2593 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2594
2595 /* Train 2 */
5eddb70b
CW		 2596 reg = FDI_TX_CTL(pipe);
2597 temp = I915_READ(reg);
8db9d77b
ZW		 2598 temp &= ~FDI_LINK_TRAIN_NONE;
2599 temp |= FDI_LINK_TRAIN_PATTERN_2;
2600 if (IS_GEN6(dev)) {
2601 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2602 /* SNB-B */
2603 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2604 }
5eddb70b 2605 I915_WRITE(reg, temp);
8db9d77b 2606
5eddb70b
CW		 2607 reg = FDI_RX_CTL(pipe);
2608 temp = I915_READ(reg);
8db9d77b
ZW		 2609 if (HAS_PCH_CPT(dev)) {
2610 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2611 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2612 } else {
2613 temp &= ~FDI_LINK_TRAIN_NONE;
2614 temp |= FDI_LINK_TRAIN_PATTERN_2;
2615 }
5eddb70b
CW		 2616 I915_WRITE(reg, temp);
2617
2618 POSTING_READ(reg);
8db9d77b
ZW		 2619 udelay(150);
2620
0206e353 2621 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2622 reg = FDI_TX_CTL(pipe);
2623 temp = I915_READ(reg);
8db9d77b
ZW		 2624 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2625 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2626 I915_WRITE(reg, temp);
2627
2628 POSTING_READ(reg);
8db9d77b
ZW		 2629 udelay(500);
2630
fa37d39e
SP		 2631 for (retry = 0; retry < 5; retry++) {
2632 reg = FDI_RX_IIR(pipe);
2633 temp = I915_READ(reg);
2634 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2635 if (temp & FDI_RX_SYMBOL_LOCK) {
2636 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2637 DRM_DEBUG_KMS("FDI train 2 done.\n");
2638 break;
2639 }
2640 udelay(50);
8db9d77b 2641 }
fa37d39e
SP		 2642 if (retry < 5)
2643 break;
8db9d77b
ZW		 2644 }
2645 if (i == 4)
5eddb70b 2646 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2647
2648 DRM_DEBUG_KMS("FDI train done.\n");
2649}
2650
357555c0
JB		 2651/* Manual link training for Ivy Bridge A0 parts */
2652static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2653{
2654 struct drm_device *dev = crtc->dev;
2655 struct drm_i915_private *dev_priv = dev->dev_private;
2656 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2657 int pipe = intel_crtc->pipe;
139ccd3f 2658 u32 reg, temp, i, j;
357555c0
JB		 2659
2660 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2661 for train result */
2662 reg = FDI_RX_IMR(pipe);
2663 temp = I915_READ(reg);
2664 temp &= ~FDI_RX_SYMBOL_LOCK;
2665 temp &= ~FDI_RX_BIT_LOCK;
2666 I915_WRITE(reg, temp);
2667
2668 POSTING_READ(reg);
2669 udelay(150);
2670
01a415fd
DV		 2671 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2672 I915_READ(FDI_RX_IIR(pipe)));
2673
139ccd3f
JB		 2674 /* Try each vswing and preemphasis setting twice before moving on */
2675 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2676 /* disable first in case we need to retry */
2677 reg = FDI_TX_CTL(pipe);
2678 temp = I915_READ(reg);
2679 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2680 temp &= ~FDI_TX_ENABLE;
2681 I915_WRITE(reg, temp);
357555c0 2682
139ccd3f
JB		 2683 reg = FDI_RX_CTL(pipe);
2684 temp = I915_READ(reg);
2685 temp &= ~FDI_LINK_TRAIN_AUTO;
2686 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2687 temp &= ~FDI_RX_ENABLE;
2688 I915_WRITE(reg, temp);
357555c0 2689
139ccd3f 2690 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 2691 reg = FDI_TX_CTL(pipe);
2692 temp = I915_READ(reg);
139ccd3f
JB		 2693 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2694 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2695 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 2696 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 2697 temp |= snb_b_fdi_train_param[j/2];
2698 temp |= FDI_COMPOSITE_SYNC;
2699 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 2700
139ccd3f
JB		 2701 I915_WRITE(FDI_RX_MISC(pipe),
2702 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 2703
139ccd3f 2704 reg = FDI_RX_CTL(pipe);
357555c0 2705 temp = I915_READ(reg);
139ccd3f
JB		 2706 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2707 temp |= FDI_COMPOSITE_SYNC;
2708 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 2709
139ccd3f
JB		 2710 POSTING_READ(reg);
2711 udelay(1); /* should be 0.5us */
357555c0 2712
139ccd3f
JB		 2713 for (i = 0; i < 4; i++) {
2714 reg = FDI_RX_IIR(pipe);
2715 temp = I915_READ(reg);
2716 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2717
139ccd3f
JB		 2718 if (temp & FDI_RX_BIT_LOCK ||
2719 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2720 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2721 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2722 i);
2723 break;
2724 }
2725 udelay(1); /* should be 0.5us */
2726 }
2727 if (i == 4) {
2728 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2729 continue;
2730 }
357555c0 2731
139ccd3f 2732 /* Train 2 */
357555c0
JB		 2733 reg = FDI_TX_CTL(pipe);
2734 temp = I915_READ(reg);
139ccd3f
JB		 2735 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2736 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2737 I915_WRITE(reg, temp);
2738
2739 reg = FDI_RX_CTL(pipe);
2740 temp = I915_READ(reg);
2741 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2742 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 2743 I915_WRITE(reg, temp);
2744
2745 POSTING_READ(reg);
139ccd3f 2746 udelay(2); /* should be 1.5us */
357555c0 2747
139ccd3f
JB		 2748 for (i = 0; i < 4; i++) {
2749 reg = FDI_RX_IIR(pipe);
2750 temp = I915_READ(reg);
2751 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2752
139ccd3f
JB		 2753 if (temp & FDI_RX_SYMBOL_LOCK ||
2754 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2755 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2756 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2757 i);
2758 goto train_done;
2759 }
2760 udelay(2); /* should be 1.5us */
357555c0 2761 }
139ccd3f
JB		 2762 if (i == 4)
2763 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 2764 }
357555c0 2765
139ccd3f 2766train_done:
357555c0
JB		 2767 DRM_DEBUG_KMS("FDI train done.\n");
2768}
2769
88cefb6c 2770static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2771{
88cefb6c 2772 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2773 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2774 int pipe = intel_crtc->pipe;
5eddb70b 2775 u32 reg, temp;
79e53945 2776
c64e311e 2777
c98e9dcf 2778 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2779 reg = FDI_RX_CTL(pipe);
2780 temp = I915_READ(reg);
627eb5a3
DV		 2781 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2782 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2783 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2784 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2785
2786 POSTING_READ(reg);
c98e9dcf
JB		 2787 udelay(200);
2788
2789 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2790 temp = I915_READ(reg);
2791 I915_WRITE(reg, temp | FDI_PCDCLK);
2792
2793 POSTING_READ(reg);
c98e9dcf
JB		 2794 udelay(200);
2795
20749730
PZ		 2796 /* Enable CPU FDI TX PLL, always on for Ironlake */
2797 reg = FDI_TX_CTL(pipe);
2798 temp = I915_READ(reg);
2799 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2800 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2801
20749730
PZ		 2802 POSTING_READ(reg);
2803 udelay(100);
6be4a607 2804 }
0e23b99d
JB		 2805}
2806
88cefb6c
DV		 2807static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2808{
2809 struct drm_device *dev = intel_crtc->base.dev;
2810 struct drm_i915_private *dev_priv = dev->dev_private;
2811 int pipe = intel_crtc->pipe;
2812 u32 reg, temp;
2813
2814 /* Switch from PCDclk to Rawclk */
2815 reg = FDI_RX_CTL(pipe);
2816 temp = I915_READ(reg);
2817 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2818
2819 /* Disable CPU FDI TX PLL */
2820 reg = FDI_TX_CTL(pipe);
2821 temp = I915_READ(reg);
2822 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2823
2824 POSTING_READ(reg);
2825 udelay(100);
2826
2827 reg = FDI_RX_CTL(pipe);
2828 temp = I915_READ(reg);
2829 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2830
2831 /* Wait for the clocks to turn off. */
2832 POSTING_READ(reg);
2833 udelay(100);
2834}
2835
0fc932b8
JB		 2836static void ironlake_fdi_disable(struct drm_crtc *crtc)
2837{
2838 struct drm_device *dev = crtc->dev;
2839 struct drm_i915_private *dev_priv = dev->dev_private;
2840 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2841 int pipe = intel_crtc->pipe;
2842 u32 reg, temp;
2843
2844 /* disable CPU FDI tx and PCH FDI rx */
2845 reg = FDI_TX_CTL(pipe);
2846 temp = I915_READ(reg);
2847 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2848 POSTING_READ(reg);
2849
2850 reg = FDI_RX_CTL(pipe);
2851 temp = I915_READ(reg);
2852 temp &= ~(0x7 << 16);
dfd07d72 2853 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2854 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2855
2856 POSTING_READ(reg);
2857 udelay(100);
2858
2859 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2860 if (HAS_PCH_IBX(dev)) {
2861 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2862 }
0fc932b8
JB		 2863
2864 /* still set train pattern 1 */
2865 reg = FDI_TX_CTL(pipe);
2866 temp = I915_READ(reg);
2867 temp &= ~FDI_LINK_TRAIN_NONE;
2868 temp |= FDI_LINK_TRAIN_PATTERN_1;
2869 I915_WRITE(reg, temp);
2870
2871 reg = FDI_RX_CTL(pipe);
2872 temp = I915_READ(reg);
2873 if (HAS_PCH_CPT(dev)) {
2874 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2875 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2876 } else {
2877 temp &= ~FDI_LINK_TRAIN_NONE;
2878 temp |= FDI_LINK_TRAIN_PATTERN_1;
2879 }
2880 /* BPC in FDI rx is consistent with that in PIPECONF */
2881 temp &= ~(0x07 << 16);
dfd07d72 2882 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2883 I915_WRITE(reg, temp);
2884
2885 POSTING_READ(reg);
2886 udelay(100);
2887}
2888
5bb61643
CW		 2889static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2890{
2891 struct drm_device *dev = crtc->dev;
2892 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2893 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2894 unsigned long flags;
2895 bool pending;
2896
10d83730
VS		 2897 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2898 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2899 return false;
2900
2901 spin_lock_irqsave(&dev->event_lock, flags);
2902 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2903 spin_unlock_irqrestore(&dev->event_lock, flags);
2904
2905 return pending;
2906}
2907
e6c3a2a6
CW		 2908static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2909{
0f91128d 2910 struct drm_device *dev = crtc->dev;
5bb61643 2911 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2912
2913 if (crtc->fb == NULL)
2914 return;
2915
2c10d571
DV		 2916 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2917
5bb61643
CW		 2918 wait_event(dev_priv->pending_flip_queue,
2919 !intel_crtc_has_pending_flip(crtc));
2920
0f91128d
CW		 2921 mutex_lock(&dev->struct_mutex);
2922 intel_finish_fb(crtc->fb);
2923 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2924}
2925
e615efe4
ED		 2926/* Program iCLKIP clock to the desired frequency */
2927static void lpt_program_iclkip(struct drm_crtc *crtc)
2928{
2929 struct drm_device *dev = crtc->dev;
2930 struct drm_i915_private *dev_priv = dev->dev_private;
241bfc38 2931 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
e615efe4
ED		 2932 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2933 u32 temp;
2934
09153000
DV		 2935 mutex_lock(&dev_priv->dpio_lock);
2936
e615efe4
ED		 2937 /* It is necessary to ungate the pixclk gate prior to programming
2938 * the divisors, and gate it back when it is done.
2939 */
2940 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2941
2942 /* Disable SSCCTL */
2943 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2944 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2945 SBI_SSCCTL_DISABLE,
2946 SBI_ICLK);
e615efe4
ED		 2947
2948 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 2949 if (clock == 20000) {
e615efe4
ED		 2950 auxdiv = 1;
2951 divsel = 0x41;
2952 phaseinc = 0x20;
2953 } else {
2954 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 2955 * but the adjusted_mode->crtc_clock in in KHz. To get the
2956 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 2957 * convert the virtual clock precision to KHz here for higher
2958 * precision.
2959 */
2960 u32 iclk_virtual_root_freq = 172800 * 1000;
2961 u32 iclk_pi_range = 64;
2962 u32 desired_divisor, msb_divisor_value, pi_value;
2963
12d7ceed 2964 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 2965 msb_divisor_value = desired_divisor / iclk_pi_range;
2966 pi_value = desired_divisor % iclk_pi_range;
2967
2968 auxdiv = 0;
2969 divsel = msb_divisor_value - 2;
2970 phaseinc = pi_value;
2971 }
2972
2973 /* This should not happen with any sane values */
2974 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2975 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2976 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2977 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2978
2979 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 2980 clock,
e615efe4
ED		 2981 auxdiv,
2982 divsel,
2983 phasedir,
2984 phaseinc);
2985
2986 /* Program SSCDIVINTPHASE6 */
988d6ee8 2987 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2988 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2989 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2990 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2991 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2992 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2993 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2994 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2995
2996 /* Program SSCAUXDIV */
988d6ee8 2997 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2998 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2999 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3000 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3001
3002 /* Enable modulator and associated divider */
988d6ee8 3003 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3004 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3005 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3006
3007 /* Wait for initialization time */
3008 udelay(24);
3009
3010 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 3011
3012 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 3013}
3014
275f01b2
DV		 3015static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3016 enum pipe pch_transcoder)
3017{
3018 struct drm_device *dev = crtc->base.dev;
3019 struct drm_i915_private *dev_priv = dev->dev_private;
3020 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3021
3022 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3023 I915_READ(HTOTAL(cpu_transcoder)));
3024 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3025 I915_READ(HBLANK(cpu_transcoder)));
3026 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3027 I915_READ(HSYNC(cpu_transcoder)));
3028
3029 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3030 I915_READ(VTOTAL(cpu_transcoder)));
3031 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3032 I915_READ(VBLANK(cpu_transcoder)));
3033 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3034 I915_READ(VSYNC(cpu_transcoder)));
3035 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3036 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3037}
3038
f67a559d
JB		 3039/*
3040 * Enable PCH resources required for PCH ports:
3041 * - PCH PLLs
3042 * - FDI training & RX/TX
3043 * - update transcoder timings
3044 * - DP transcoding bits
3045 * - transcoder
3046 */
3047static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3048{
3049 struct drm_device *dev = crtc->dev;
3050 struct drm_i915_private *dev_priv = dev->dev_private;
3051 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3052 int pipe = intel_crtc->pipe;
ee7b9f93 3053 u32 reg, temp;
2c07245f 3054
ab9412ba 3055 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 3056
cd986abb
DV		 3057 /* Write the TU size bits before fdi link training, so that error
3058 * detection works. */
3059 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3060 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3061
c98e9dcf 3062 /* For PCH output, training FDI link */
674cf967 3063 dev_priv->display.fdi_link_train(crtc);
2c07245f 3064
3ad8a208
DV		 3065 /* We need to program the right clock selection before writing the pixel
3066 * mutliplier into the DPLL. */
303b81e0 3067 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3068 u32 sel;
4b645f14 3069
c98e9dcf 3070 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 3071 temp |= TRANS_DPLL_ENABLE(pipe);
3072 sel = TRANS_DPLLB_SEL(pipe);
a43f6e0f 3073 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 3074 temp |= sel;
3075 else
3076 temp &= ~sel;
c98e9dcf 3077 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3078 }
5eddb70b 3079
3ad8a208
DV		 3080 /* XXX: pch pll's can be enabled any time before we enable the PCH
3081 * transcoder, and we actually should do this to not upset any PCH
3082 * transcoder that already use the clock when we share it.
3083 *
3084 * Note that enable_shared_dpll tries to do the right thing, but
3085 * get_shared_dpll unconditionally resets the pll - we need that to have
3086 * the right LVDS enable sequence. */
3087 ironlake_enable_shared_dpll(intel_crtc);
3088
d9b6cb56
JB		 3089 /* set transcoder timing, panel must allow it */
3090 assert_panel_unlocked(dev_priv, pipe);
275f01b2 3091 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 3092
303b81e0 3093 intel_fdi_normal_train(crtc);
5e84e1a4 3094
c98e9dcf
JB		 3095 /* For PCH DP, enable TRANS_DP_CTL */
3096 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3097 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3098 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3099 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3100 reg = TRANS_DP_CTL(pipe);
3101 temp = I915_READ(reg);
3102 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3103 TRANS_DP_SYNC_MASK |
3104 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3105 temp |= (TRANS_DP_OUTPUT_ENABLE |
3106 TRANS_DP_ENH_FRAMING);
9325c9f0 3107 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3108
3109 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3110 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3111 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3112 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3113
3114 switch (intel_trans_dp_port_sel(crtc)) {
3115 case PCH_DP_B:
5eddb70b 3116 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3117 break;
3118 case PCH_DP_C:
5eddb70b 3119 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3120 break;
3121 case PCH_DP_D:
5eddb70b 3122 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3123 break;
3124 default:
e95d41e1 3125 BUG();
32f9d658 3126 }
2c07245f 3127
5eddb70b 3128 I915_WRITE(reg, temp);
6be4a607 3129 }
b52eb4dc 3130
b8a4f404 3131 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3132}
3133
1507e5bd
PZ		 3134static void lpt_pch_enable(struct drm_crtc *crtc)
3135{
3136 struct drm_device *dev = crtc->dev;
3137 struct drm_i915_private *dev_priv = dev->dev_private;
3138 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3139 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3140
ab9412ba 3141 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3142
8c52b5e8 3143 lpt_program_iclkip(crtc);
1507e5bd 3144
0540e488 3145 /* Set transcoder timing. */
275f01b2 3146 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3147
937bb610 3148 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3149}
3150
e2b78267 3151static void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3152{
e2b78267 3153 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 3154
3155 if (pll == NULL)
3156 return;
3157
3158 if (pll->refcount == 0) {
46edb027 3159 WARN(1, "bad %s refcount\n", pll->name);
ee7b9f93
JB		 3160 return;
3161 }
3162
f4a091c7
DV		 3163 if (--pll->refcount == 0) {
3164 WARN_ON(pll->on);
3165 WARN_ON(pll->active);
3166 }
3167
a43f6e0f 3168 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 3169}
3170
b89a1d39 3171static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3172{
e2b78267
DV		 3173 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3174 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3175 enum intel_dpll_id i;
ee7b9f93 3176
ee7b9f93 3177 if (pll) {
46edb027
DV		 3178 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3179 crtc->base.base.id, pll->name);
e2b78267 3180 intel_put_shared_dpll(crtc);
ee7b9f93
JB		 3181 }
3182
98b6bd99
DV		 3183 if (HAS_PCH_IBX(dev_priv->dev)) {
3184 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 3185 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 3186 pll = &dev_priv->shared_dplls[i];
98b6bd99 3187
46edb027
DV		 3188 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3189 crtc->base.base.id, pll->name);
98b6bd99
DV		 3190
3191 goto found;
3192 }
3193
e72f9fbf
DV		 3194 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3195 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 3196
3197 /* Only want to check enabled timings first */
3198 if (pll->refcount == 0)
3199 continue;
3200
b89a1d39
DV		 3201 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3202 sizeof(pll->hw_state)) == 0) {
46edb027 3203 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
e2b78267 3204 crtc->base.base.id,
46edb027 3205 pll->name, pll->refcount, pll->active);
ee7b9f93
JB		 3206
3207 goto found;
3208 }
3209 }
3210
3211 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 3212 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3213 pll = &dev_priv->shared_dplls[i];
ee7b9f93 3214 if (pll->refcount == 0) {
46edb027
DV		 3215 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3216 crtc->base.base.id, pll->name);
ee7b9f93
JB		 3217 goto found;
3218 }
3219 }
3220
3221 return NULL;
3222
3223found:
a43f6e0f 3224 crtc->config.shared_dpll = i;
46edb027
DV		 3225 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3226 pipe_name(crtc->pipe));
ee7b9f93 3227
cdbd2316 3228 if (pll->active == 0) {
66e985c0
DV		 3229 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3230 sizeof(pll->hw_state));
3231
46edb027 3232 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
cdbd2316 3233 WARN_ON(pll->on);
e9d6944e 3234 assert_shared_dpll_disabled(dev_priv, pll);
ee7b9f93 3235
15bdd4cf 3236 pll->mode_set(dev_priv, pll);
cdbd2316
DV		 3237 }
3238 pll->refcount++;
e04c7350 3239
ee7b9f93
JB		 3240 return pll;
3241}
3242
a1520318 3243static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3244{
3245 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3246 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3247 u32 temp;
3248
3249 temp = I915_READ(dslreg);
3250 udelay(500);
3251 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3252 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3253 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3254 }
3255}
3256
b074cec8
JB		 3257static void ironlake_pfit_enable(struct intel_crtc *crtc)
3258{
3259 struct drm_device *dev = crtc->base.dev;
3260 struct drm_i915_private *dev_priv = dev->dev_private;
3261 int pipe = crtc->pipe;
3262
fd4daa9c 3263 if (crtc->config.pch_pfit.enabled) {
b074cec8
JB		 3264 /* Force use of hard-coded filter coefficients
3265 * as some pre-programmed values are broken,
3266 * e.g. x201.
3267 */
3268 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3269 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3270 PF_PIPE_SEL_IVB(pipe));
3271 else
3272 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3273 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3274 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
d4270e57
JB		 3275 }
3276}
3277
bb53d4ae
VS		 3278static void intel_enable_planes(struct drm_crtc *crtc)
3279{
3280 struct drm_device *dev = crtc->dev;
3281 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3282 struct intel_plane *intel_plane;
3283
3284 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3285 if (intel_plane->pipe == pipe)
3286 intel_plane_restore(&intel_plane->base);
3287}
3288
3289static void intel_disable_planes(struct drm_crtc *crtc)
3290{
3291 struct drm_device *dev = crtc->dev;
3292 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3293 struct intel_plane *intel_plane;
3294
3295 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3296 if (intel_plane->pipe == pipe)
3297 intel_plane_disable(&intel_plane->base);
3298}
3299
d77e4531
PZ		 3300static void hsw_enable_ips(struct intel_crtc *crtc)
3301{
3302 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3303
3304 if (!crtc->config.ips_enabled)
3305 return;
3306
3307 /* We can only enable IPS after we enable a plane and wait for a vblank.
3308 * We guarantee that the plane is enabled by calling intel_enable_ips
3309 * only after intel_enable_plane. And intel_enable_plane already waits
3310 * for a vblank, so all we need to do here is to enable the IPS bit. */
3311 assert_plane_enabled(dev_priv, crtc->plane);
3312 I915_WRITE(IPS_CTL, IPS_ENABLE);
3313}
3314
3315static void hsw_disable_ips(struct intel_crtc *crtc)
3316{
3317 struct drm_device *dev = crtc->base.dev;
3318 struct drm_i915_private *dev_priv = dev->dev_private;
3319
3320 if (!crtc->config.ips_enabled)
3321 return;
3322
3323 assert_plane_enabled(dev_priv, crtc->plane);
3324 I915_WRITE(IPS_CTL, 0);
3325 POSTING_READ(IPS_CTL);
3326
3327 /* We need to wait for a vblank before we can disable the plane. */
3328 intel_wait_for_vblank(dev, crtc->pipe);
3329}
3330
3331/** Loads the palette/gamma unit for the CRTC with the prepared values */
3332static void intel_crtc_load_lut(struct drm_crtc *crtc)
3333{
3334 struct drm_device *dev = crtc->dev;
3335 struct drm_i915_private *dev_priv = dev->dev_private;
3336 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3337 enum pipe pipe = intel_crtc->pipe;
3338 int palreg = PALETTE(pipe);
3339 int i;
3340 bool reenable_ips = false;
3341
3342 /* The clocks have to be on to load the palette. */
3343 if (!crtc->enabled || !intel_crtc->active)
3344 return;
3345
3346 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3347 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3348 assert_dsi_pll_enabled(dev_priv);
3349 else
3350 assert_pll_enabled(dev_priv, pipe);
3351 }
3352
3353 /* use legacy palette for Ironlake */
3354 if (HAS_PCH_SPLIT(dev))
3355 palreg = LGC_PALETTE(pipe);
3356
3357 /* Workaround : Do not read or write the pipe palette/gamma data while
3358 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3359 */
3360 if (intel_crtc->config.ips_enabled &&
3361 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3362 GAMMA_MODE_MODE_SPLIT)) {
3363 hsw_disable_ips(intel_crtc);
3364 reenable_ips = true;
3365 }
3366
3367 for (i = 0; i < 256; i++) {
3368 I915_WRITE(palreg + 4 * i,
3369 (intel_crtc->lut_r[i] << 16) |
3370 (intel_crtc->lut_g[i] << 8) |
3371 intel_crtc->lut_b[i]);
3372 }
3373
3374 if (reenable_ips)
3375 hsw_enable_ips(intel_crtc);
3376}
3377
f67a559d
JB		 3378static void ironlake_crtc_enable(struct drm_crtc *crtc)
3379{
3380 struct drm_device *dev = crtc->dev;
3381 struct drm_i915_private *dev_priv = dev->dev_private;
3382 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3383 struct intel_encoder *encoder;
f67a559d
JB		 3384 int pipe = intel_crtc->pipe;
3385 int plane = intel_crtc->plane;
f67a559d 3386
08a48469
DV		 3387 WARN_ON(!crtc->enabled);
3388
f67a559d
JB		 3389 if (intel_crtc->active)
3390 return;
3391
3392 intel_crtc->active = true;
8664281b
PZ		 3393
3394 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3395 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3396
f6736a1a 3397 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 3398 if (encoder->pre_enable)
3399 encoder->pre_enable(encoder);
f67a559d 3400
5bfe2ac0 3401 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3402 /* Note: FDI PLL enabling _must_ be done before we enable the
3403 * cpu pipes, hence this is separate from all the other fdi/pch
3404 * enabling. */
88cefb6c 3405 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3406 } else {
3407 assert_fdi_tx_disabled(dev_priv, pipe);
3408 assert_fdi_rx_disabled(dev_priv, pipe);
3409 }
f67a559d 3410
b074cec8 3411 ironlake_pfit_enable(intel_crtc);
f67a559d 3412
9c54c0dd
JB		 3413 /*
3414 * On ILK+ LUT must be loaded before the pipe is running but with
3415 * clocks enabled
3416 */
3417 intel_crtc_load_lut(crtc);
3418
f37fcc2a 3419 intel_update_watermarks(crtc);
5bfe2ac0 3420 intel_enable_pipe(dev_priv, pipe,
23538ef1 3421 intel_crtc->config.has_pch_encoder, false);
f67a559d 3422 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3423 intel_enable_planes(crtc);
5c38d48c 3424 intel_crtc_update_cursor(crtc, true);
f67a559d 3425
5bfe2ac0 3426 if (intel_crtc->config.has_pch_encoder)
f67a559d 3427 ironlake_pch_enable(crtc);
c98e9dcf 3428
d1ebd816 3429 mutex_lock(&dev->struct_mutex);
bed4a673 3430 intel_update_fbc(dev);
d1ebd816
BW		 3431 mutex_unlock(&dev->struct_mutex);
3432
fa5c73b1
DV		 3433 for_each_encoder_on_crtc(dev, crtc, encoder)
3434 encoder->enable(encoder);
61b77ddd
DV		 3435
3436 if (HAS_PCH_CPT(dev))
a1520318 3437 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3438
3439 /*
3440 * There seems to be a race in PCH platform hw (at least on some
3441 * outputs) where an enabled pipe still completes any pageflip right
3442 * away (as if the pipe is off) instead of waiting for vblank. As soon
3443 * as the first vblank happend, everything works as expected. Hence just
3444 * wait for one vblank before returning to avoid strange things
3445 * happening.
3446 */
3447 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3448}
3449
42db64ef
PZ		 3450/* IPS only exists on ULT machines and is tied to pipe A. */
3451static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3452{
f5adf94e 3453 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 3454}
3455
4f771f10
PZ		 3456static void haswell_crtc_enable(struct drm_crtc *crtc)
3457{
3458 struct drm_device *dev = crtc->dev;
3459 struct drm_i915_private *dev_priv = dev->dev_private;
3460 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3461 struct intel_encoder *encoder;
3462 int pipe = intel_crtc->pipe;
3463 int plane = intel_crtc->plane;
4f771f10
PZ		 3464
3465 WARN_ON(!crtc->enabled);
3466
3467 if (intel_crtc->active)
3468 return;
3469
3470 intel_crtc->active = true;
8664281b
PZ		 3471
3472 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3473 if (intel_crtc->config.has_pch_encoder)
3474 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3475
5bfe2ac0 3476 if (intel_crtc->config.has_pch_encoder)
04945641 3477 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3478
3479 for_each_encoder_on_crtc(dev, crtc, encoder)
3480 if (encoder->pre_enable)
3481 encoder->pre_enable(encoder);
3482
1f544388 3483 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3484
b074cec8 3485 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3486
3487 /*
3488 * On ILK+ LUT must be loaded before the pipe is running but with
3489 * clocks enabled
3490 */
3491 intel_crtc_load_lut(crtc);
3492
1f544388 3493 intel_ddi_set_pipe_settings(crtc);
8228c251 3494 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3495
f37fcc2a 3496 intel_update_watermarks(crtc);
5bfe2ac0 3497 intel_enable_pipe(dev_priv, pipe,
23538ef1 3498 intel_crtc->config.has_pch_encoder, false);
4f771f10 3499 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3500 intel_enable_planes(crtc);
5c38d48c 3501 intel_crtc_update_cursor(crtc, true);
4f771f10 3502
42db64ef
PZ		 3503 hsw_enable_ips(intel_crtc);
3504
5bfe2ac0 3505 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3506 lpt_pch_enable(crtc);
4f771f10
PZ		 3507
3508 mutex_lock(&dev->struct_mutex);
3509 intel_update_fbc(dev);
3510 mutex_unlock(&dev->struct_mutex);
3511
8807e55b 3512 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 3513 encoder->enable(encoder);
8807e55b
JN		 3514 intel_opregion_notify_encoder(encoder, true);
3515 }
4f771f10 3516
4f771f10
PZ		 3517 /*
3518 * There seems to be a race in PCH platform hw (at least on some
3519 * outputs) where an enabled pipe still completes any pageflip right
3520 * away (as if the pipe is off) instead of waiting for vblank. As soon
3521 * as the first vblank happend, everything works as expected. Hence just
3522 * wait for one vblank before returning to avoid strange things
3523 * happening.
3524 */
3525 intel_wait_for_vblank(dev, intel_crtc->pipe);
3526}
3527
3f8dce3a
DV		 3528static void ironlake_pfit_disable(struct intel_crtc *crtc)
3529{
3530 struct drm_device *dev = crtc->base.dev;
3531 struct drm_i915_private *dev_priv = dev->dev_private;
3532 int pipe = crtc->pipe;
3533
3534 /* To avoid upsetting the power well on haswell only disable the pfit if
3535 * it's in use. The hw state code will make sure we get this right. */
fd4daa9c 3536 if (crtc->config.pch_pfit.enabled) {
3f8dce3a
DV		 3537 I915_WRITE(PF_CTL(pipe), 0);
3538 I915_WRITE(PF_WIN_POS(pipe), 0);
3539 I915_WRITE(PF_WIN_SZ(pipe), 0);
3540 }
3541}
3542
6be4a607
JB		 3543static void ironlake_crtc_disable(struct drm_crtc *crtc)
3544{
3545 struct drm_device *dev = crtc->dev;
3546 struct drm_i915_private *dev_priv = dev->dev_private;
3547 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3548 struct intel_encoder *encoder;
6be4a607
JB		 3549 int pipe = intel_crtc->pipe;
3550 int plane = intel_crtc->plane;
5eddb70b 3551 u32 reg, temp;
b52eb4dc 3552
ef9c3aee 3553
f7abfe8b
CW		 3554 if (!intel_crtc->active)
3555 return;
3556
ea9d758d
DV		 3557 for_each_encoder_on_crtc(dev, crtc, encoder)
3558 encoder->disable(encoder);
3559
e6c3a2a6 3560 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3561 drm_vblank_off(dev, pipe);
913d8d11 3562
5c3fe8b0 3563 if (dev_priv->fbc.plane == plane)
973d04f9 3564 intel_disable_fbc(dev);
2c07245f 3565
0d5b8c61 3566 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3567 intel_disable_planes(crtc);
0d5b8c61
VS		 3568 intel_disable_plane(dev_priv, plane, pipe);
3569
d925c59a
DV		 3570 if (intel_crtc->config.has_pch_encoder)
3571 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3572
b24e7179 3573 intel_disable_pipe(dev_priv, pipe);
32f9d658 3574
3f8dce3a 3575 ironlake_pfit_disable(intel_crtc);
2c07245f 3576
bf49ec8c
DV		 3577 for_each_encoder_on_crtc(dev, crtc, encoder)
3578 if (encoder->post_disable)
3579 encoder->post_disable(encoder);
2c07245f 3580
d925c59a
DV		 3581 if (intel_crtc->config.has_pch_encoder) {
3582 ironlake_fdi_disable(crtc);
913d8d11 3583
d925c59a
DV		 3584 ironlake_disable_pch_transcoder(dev_priv, pipe);
3585 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
6be4a607 3586
d925c59a
DV		 3587 if (HAS_PCH_CPT(dev)) {
3588 /* disable TRANS_DP_CTL */
3589 reg = TRANS_DP_CTL(pipe);
3590 temp = I915_READ(reg);
3591 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3592 TRANS_DP_PORT_SEL_MASK);
3593 temp |= TRANS_DP_PORT_SEL_NONE;
3594 I915_WRITE(reg, temp);
3595
3596 /* disable DPLL_SEL */
3597 temp = I915_READ(PCH_DPLL_SEL);
11887397 3598 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 3599 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 3600 }
e3421a18 3601
d925c59a 3602 /* disable PCH DPLL */
e72f9fbf 3603 intel_disable_shared_dpll(intel_crtc);
8db9d77b 3604
d925c59a
DV		 3605 ironlake_fdi_pll_disable(intel_crtc);
3606 }
6b383a7f 3607
f7abfe8b 3608 intel_crtc->active = false;
46ba614c 3609 intel_update_watermarks(crtc);
d1ebd816
BW		 3610
3611 mutex_lock(&dev->struct_mutex);
6b383a7f 3612 intel_update_fbc(dev);
d1ebd816 3613 mutex_unlock(&dev->struct_mutex);
6be4a607 3614}
1b3c7a47 3615
4f771f10 3616static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3617{
4f771f10
PZ		 3618 struct drm_device *dev = crtc->dev;
3619 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3620 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3621 struct intel_encoder *encoder;
3622 int pipe = intel_crtc->pipe;
3623 int plane = intel_crtc->plane;
3b117c8f 3624 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3625
4f771f10
PZ		 3626 if (!intel_crtc->active)
3627 return;
3628
8807e55b
JN		 3629 for_each_encoder_on_crtc(dev, crtc, encoder) {
3630 intel_opregion_notify_encoder(encoder, false);
4f771f10 3631 encoder->disable(encoder);
8807e55b 3632 }
4f771f10
PZ		 3633
3634 intel_crtc_wait_for_pending_flips(crtc);
3635 drm_vblank_off(dev, pipe);
4f771f10 3636
891348b2 3637 /* FBC must be disabled before disabling the plane on HSW. */
5c3fe8b0 3638 if (dev_priv->fbc.plane == plane)
4f771f10
PZ		 3639 intel_disable_fbc(dev);
3640
42db64ef
PZ		 3641 hsw_disable_ips(intel_crtc);
3642
0d5b8c61 3643 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3644 intel_disable_planes(crtc);
891348b2
RV		 3645 intel_disable_plane(dev_priv, plane, pipe);
3646
8664281b
PZ		 3647 if (intel_crtc->config.has_pch_encoder)
3648 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3649 intel_disable_pipe(dev_priv, pipe);
3650
ad80a810 3651 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3652
3f8dce3a 3653 ironlake_pfit_disable(intel_crtc);
4f771f10 3654
1f544388 3655 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3656
3657 for_each_encoder_on_crtc(dev, crtc, encoder)
3658 if (encoder->post_disable)
3659 encoder->post_disable(encoder);
3660
88adfff1 3661 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3662 lpt_disable_pch_transcoder(dev_priv);
8664281b 3663 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3664 intel_ddi_fdi_disable(crtc);
83616634 3665 }
4f771f10
PZ		 3666
3667 intel_crtc->active = false;
46ba614c 3668 intel_update_watermarks(crtc);
4f771f10
PZ		 3669
3670 mutex_lock(&dev->struct_mutex);
3671 intel_update_fbc(dev);
3672 mutex_unlock(&dev->struct_mutex);
3673}
3674
ee7b9f93
JB		 3675static void ironlake_crtc_off(struct drm_crtc *crtc)
3676{
3677 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 3678 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 3679}
3680
6441ab5f
PZ		 3681static void haswell_crtc_off(struct drm_crtc *crtc)
3682{
3683 intel_ddi_put_crtc_pll(crtc);
3684}
3685
02e792fb
DV		 3686static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3687{
02e792fb 3688 if (!enable && intel_crtc->overlay) {
23f09ce3 3689 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3690 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3691
23f09ce3 3692 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3693 dev_priv->mm.interruptible = false;
3694 (void) intel_overlay_switch_off(intel_crtc->overlay);
3695 dev_priv->mm.interruptible = true;
23f09ce3 3696 mutex_unlock(&dev->struct_mutex);
02e792fb 3697 }
02e792fb 3698
5dcdbcb0
CW		 3699 /* Let userspace switch the overlay on again. In most cases userspace
3700 * has to recompute where to put it anyway.
3701 */
02e792fb
DV		 3702}
3703
61bc95c1
EE		 3704/**
3705 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3706 * cursor plane briefly if not already running after enabling the display
3707 * plane.
3708 * This workaround avoids occasional blank screens when self refresh is
3709 * enabled.
3710 */
3711static void
3712g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3713{
3714 u32 cntl = I915_READ(CURCNTR(pipe));
3715
3716 if ((cntl & CURSOR_MODE) == 0) {
3717 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3718
3719 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3720 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3721 intel_wait_for_vblank(dev_priv->dev, pipe);
3722 I915_WRITE(CURCNTR(pipe), cntl);
3723 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3724 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3725 }
3726}
3727
2dd24552
JB		 3728static void i9xx_pfit_enable(struct intel_crtc *crtc)
3729{
3730 struct drm_device *dev = crtc->base.dev;
3731 struct drm_i915_private *dev_priv = dev->dev_private;
3732 struct intel_crtc_config *pipe_config = &crtc->config;
3733
328d8e82 3734 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3735 return;
3736
2dd24552 3737 /*
c0b03411
DV		 3738 * The panel fitter should only be adjusted whilst the pipe is disabled,
3739 * according to register description and PRM.
2dd24552 3740 */
c0b03411
DV		 3741 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3742 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3743
b074cec8
JB		 3744 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3745 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3746
3747 /* Border color in case we don't scale up to the full screen. Black by
3748 * default, change to something else for debugging. */
3749 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3750}
3751
89b667f8
JB		 3752static void valleyview_crtc_enable(struct drm_crtc *crtc)
3753{
3754 struct drm_device *dev = crtc->dev;
3755 struct drm_i915_private *dev_priv = dev->dev_private;
3756 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3757 struct intel_encoder *encoder;
3758 int pipe = intel_crtc->pipe;
3759 int plane = intel_crtc->plane;
23538ef1 3760 bool is_dsi;
89b667f8
JB		 3761
3762 WARN_ON(!crtc->enabled);
3763
3764 if (intel_crtc->active)
3765 return;
3766
3767 intel_crtc->active = true;
89b667f8 3768
89b667f8
JB		 3769 for_each_encoder_on_crtc(dev, crtc, encoder)
3770 if (encoder->pre_pll_enable)
3771 encoder->pre_pll_enable(encoder);
3772
23538ef1
JN		 3773 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
3774
e9fd1c02
JN		 3775 if (!is_dsi)
3776 vlv_enable_pll(intel_crtc);
89b667f8
JB		 3777
3778 for_each_encoder_on_crtc(dev, crtc, encoder)
3779 if (encoder->pre_enable)
3780 encoder->pre_enable(encoder);
3781
2dd24552
JB		 3782 i9xx_pfit_enable(intel_crtc);
3783
63cbb074
VS		 3784 intel_crtc_load_lut(crtc);
3785
f37fcc2a 3786 intel_update_watermarks(crtc);
23538ef1 3787 intel_enable_pipe(dev_priv, pipe, false, is_dsi);
89b667f8 3788 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3789 intel_enable_planes(crtc);
5c38d48c 3790 intel_crtc_update_cursor(crtc, true);
89b667f8 3791
89b667f8 3792 intel_update_fbc(dev);
5004945f
JN		 3793
3794 for_each_encoder_on_crtc(dev, crtc, encoder)
3795 encoder->enable(encoder);
89b667f8
JB		 3796}
3797
0b8765c6 3798static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3799{
3800 struct drm_device *dev = crtc->dev;
79e53945
JB		 3801 struct drm_i915_private *dev_priv = dev->dev_private;
3802 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3803 struct intel_encoder *encoder;
79e53945 3804 int pipe = intel_crtc->pipe;
80824003 3805 int plane = intel_crtc->plane;
79e53945 3806
08a48469
DV		 3807 WARN_ON(!crtc->enabled);
3808
f7abfe8b
CW		 3809 if (intel_crtc->active)
3810 return;
3811
3812 intel_crtc->active = true;
6b383a7f 3813
9d6d9f19
MK		 3814 for_each_encoder_on_crtc(dev, crtc, encoder)
3815 if (encoder->pre_enable)
3816 encoder->pre_enable(encoder);
3817
f6736a1a
DV		 3818 i9xx_enable_pll(intel_crtc);
3819
2dd24552
JB		 3820 i9xx_pfit_enable(intel_crtc);
3821
63cbb074
VS		 3822 intel_crtc_load_lut(crtc);
3823
f37fcc2a 3824 intel_update_watermarks(crtc);
23538ef1 3825 intel_enable_pipe(dev_priv, pipe, false, false);
b24e7179 3826 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3827 intel_enable_planes(crtc);
22e407d7 3828 /* The fixup needs to happen before cursor is enabled */
61bc95c1
EE		 3829 if (IS_G4X(dev))
3830 g4x_fixup_plane(dev_priv, pipe);
22e407d7 3831 intel_crtc_update_cursor(crtc, true);
79e53945 3832
0b8765c6
JB		 3833 /* Give the overlay scaler a chance to enable if it's on this pipe */
3834 intel_crtc_dpms_overlay(intel_crtc, true);
ef9c3aee 3835
f440eb13 3836 intel_update_fbc(dev);
ef9c3aee 3837
fa5c73b1
DV		 3838 for_each_encoder_on_crtc(dev, crtc, encoder)
3839 encoder->enable(encoder);
0b8765c6 3840}
79e53945 3841
87476d63
DV		 3842static void i9xx_pfit_disable(struct intel_crtc *crtc)
3843{
3844 struct drm_device *dev = crtc->base.dev;
3845 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3846
328d8e82
DV		 3847 if (!crtc->config.gmch_pfit.control)
3848 return;
87476d63 3849
328d8e82 3850 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3851
328d8e82
DV		 3852 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3853 I915_READ(PFIT_CONTROL));
3854 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3855}
3856
0b8765c6
JB		 3857static void i9xx_crtc_disable(struct drm_crtc *crtc)
3858{
3859 struct drm_device *dev = crtc->dev;
3860 struct drm_i915_private *dev_priv = dev->dev_private;
3861 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3862 struct intel_encoder *encoder;
0b8765c6
JB		 3863 int pipe = intel_crtc->pipe;
3864 int plane = intel_crtc->plane;
ef9c3aee 3865
f7abfe8b
CW		 3866 if (!intel_crtc->active)
3867 return;
3868
ea9d758d
DV		 3869 for_each_encoder_on_crtc(dev, crtc, encoder)
3870 encoder->disable(encoder);
3871
0b8765c6 3872 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3873 intel_crtc_wait_for_pending_flips(crtc);
3874 drm_vblank_off(dev, pipe);
0b8765c6 3875
5c3fe8b0 3876 if (dev_priv->fbc.plane == plane)
973d04f9 3877 intel_disable_fbc(dev);
79e53945 3878
0d5b8c61
VS		 3879 intel_crtc_dpms_overlay(intel_crtc, false);
3880 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3881 intel_disable_planes(crtc);
b24e7179 3882 intel_disable_plane(dev_priv, plane, pipe);
0d5b8c61 3883
b24e7179 3884 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3885
87476d63 3886 i9xx_pfit_disable(intel_crtc);
24a1f16d 3887
89b667f8
JB		 3888 for_each_encoder_on_crtc(dev, crtc, encoder)
3889 if (encoder->post_disable)
3890 encoder->post_disable(encoder);
3891
f6071166
JB		 3892 if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3893 vlv_disable_pll(dev_priv, pipe);
3894 else if (!IS_VALLEYVIEW(dev))
e9fd1c02 3895 i9xx_disable_pll(dev_priv, pipe);
0b8765c6 3896
f7abfe8b 3897 intel_crtc->active = false;
46ba614c 3898 intel_update_watermarks(crtc);
f37fcc2a 3899
6b383a7f 3900 intel_update_fbc(dev);
0b8765c6
JB		 3901}
3902
ee7b9f93
JB		 3903static void i9xx_crtc_off(struct drm_crtc *crtc)
3904{
3905}
3906
976f8a20
DV		 3907static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3908 bool enabled)
2c07245f
ZW		 3909{
3910 struct drm_device *dev = crtc->dev;
3911 struct drm_i915_master_private *master_priv;
3912 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3913 int pipe = intel_crtc->pipe;
79e53945
JB		 3914
3915 if (!dev->primary->master)
3916 return;
3917
3918 master_priv = dev->primary->master->driver_priv;
3919 if (!master_priv->sarea_priv)
3920 return;
3921
79e53945
JB		 3922 switch (pipe) {
3923 case 0:
3924 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3925 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3926 break;
3927 case 1:
3928 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3929 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3930 break;
3931 default:
9db4a9c7 3932 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3933 break;
3934 }
79e53945
JB		 3935}
3936
976f8a20
DV		 3937/**
3938 * Sets the power management mode of the pipe and plane.
3939 */
3940void intel_crtc_update_dpms(struct drm_crtc *crtc)
3941{
3942 struct drm_device *dev = crtc->dev;
3943 struct drm_i915_private *dev_priv = dev->dev_private;
3944 struct intel_encoder *intel_encoder;
3945 bool enable = false;
3946
3947 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3948 enable |= intel_encoder->connectors_active;
3949
3950 if (enable)
3951 dev_priv->display.crtc_enable(crtc);
3952 else
3953 dev_priv->display.crtc_disable(crtc);
3954
3955 intel_crtc_update_sarea(crtc, enable);
3956}
3957
cdd59983
CW		 3958static void intel_crtc_disable(struct drm_crtc *crtc)
3959{
cdd59983 3960 struct drm_device *dev = crtc->dev;
976f8a20 3961 struct drm_connector *connector;
ee7b9f93 3962 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3963 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3964
976f8a20
DV		 3965 /* crtc should still be enabled when we disable it. */
3966 WARN_ON(!crtc->enabled);
3967
3968 dev_priv->display.crtc_disable(crtc);
c77bf565 3969 intel_crtc->eld_vld = false;
976f8a20 3970 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3971 dev_priv->display.off(crtc);
3972
931872fc 3973 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
93ce0ba6 3974 assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
931872fc 3975 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3976
3977 if (crtc->fb) {
3978 mutex_lock(&dev->struct_mutex);
1690e1eb 3979 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3980 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3981 crtc->fb = NULL;
3982 }
3983
3984 /* Update computed state. */
3985 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3986 if (!connector->encoder || !connector->encoder->crtc)
3987 continue;
3988
3989 if (connector->encoder->crtc != crtc)
3990 continue;
3991
3992 connector->dpms = DRM_MODE_DPMS_OFF;
3993 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3994 }
3995}
3996
ea5b213a 3997void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3998{
4ef69c7a 3999 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 4000
ea5b213a
CW		 4001 drm_encoder_cleanup(encoder);
4002 kfree(intel_encoder);
7e7d76c3
JB		 4003}
4004
9237329d 4005/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 4006 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4007 * state of the entire output pipe. */
9237329d 4008static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 4009{
5ab432ef
DV		 4010 if (mode == DRM_MODE_DPMS_ON) {
4011 encoder->connectors_active = true;
4012
b2cabb0e 4013 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 4014 } else {
4015 encoder->connectors_active = false;
4016
b2cabb0e 4017 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 4018 }
79e53945
JB		 4019}
4020
0a91ca29
DV		 4021/* Cross check the actual hw state with our own modeset state tracking (and it's
4022 * internal consistency). */
b980514c 4023static void intel_connector_check_state(struct intel_connector *connector)
79e53945 4024{
0a91ca29
DV		 4025 if (connector->get_hw_state(connector)) {
4026 struct intel_encoder *encoder = connector->encoder;
4027 struct drm_crtc *crtc;
4028 bool encoder_enabled;
4029 enum pipe pipe;
4030
4031 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4032 connector->base.base.id,
4033 drm_get_connector_name(&connector->base));
4034
4035 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4036 "wrong connector dpms state\n");
4037 WARN(connector->base.encoder != &encoder->base,
4038 "active connector not linked to encoder\n");
4039 WARN(!encoder->connectors_active,
4040 "encoder->connectors_active not set\n");
4041
4042 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4043 WARN(!encoder_enabled, "encoder not enabled\n");
4044 if (WARN_ON(!encoder->base.crtc))
4045 return;
4046
4047 crtc = encoder->base.crtc;
4048
4049 WARN(!crtc->enabled, "crtc not enabled\n");
4050 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4051 WARN(pipe != to_intel_crtc(crtc)->pipe,
4052 "encoder active on the wrong pipe\n");
4053 }
79e53945
JB		 4054}
4055
5ab432ef
DV		 4056/* Even simpler default implementation, if there's really no special case to
4057 * consider. */
4058void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 4059{
5ab432ef 4060 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 4061
5ab432ef
DV		 4062 /* All the simple cases only support two dpms states. */
4063 if (mode != DRM_MODE_DPMS_ON)
4064 mode = DRM_MODE_DPMS_OFF;
d4270e57 4065
5ab432ef
DV		 4066 if (mode == connector->dpms)
4067 return;
4068
4069 connector->dpms = mode;
4070
4071 /* Only need to change hw state when actually enabled */
4072 if (encoder->base.crtc)
4073 intel_encoder_dpms(encoder, mode);
4074 else
8af6cf88 4075 WARN_ON(encoder->connectors_active != false);
0a91ca29 4076
b980514c 4077 intel_modeset_check_state(connector->dev);
79e53945
JB		 4078}
4079
f0947c37
DV		 4080/* Simple connector->get_hw_state implementation for encoders that support only
4081 * one connector and no cloning and hence the encoder state determines the state
4082 * of the connector. */
4083bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 4084{
24929352 4085 enum pipe pipe = 0;
f0947c37 4086 struct intel_encoder *encoder = connector->encoder;
ea5b213a 4087
f0947c37 4088 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 4089}
4090
1857e1da
DV		 4091static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4092 struct intel_crtc_config *pipe_config)
4093{
4094 struct drm_i915_private *dev_priv = dev->dev_private;
4095 struct intel_crtc *pipe_B_crtc =
4096 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4097
4098 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4099 pipe_name(pipe), pipe_config->fdi_lanes);
4100 if (pipe_config->fdi_lanes > 4) {
4101 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4102 pipe_name(pipe), pipe_config->fdi_lanes);
4103 return false;
4104 }
4105
4106 if (IS_HASWELL(dev)) {
4107 if (pipe_config->fdi_lanes > 2) {
4108 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4109 pipe_config->fdi_lanes);
4110 return false;
4111 } else {
4112 return true;
4113 }
4114 }
4115
4116 if (INTEL_INFO(dev)->num_pipes == 2)
4117 return true;
4118
4119 /* Ivybridge 3 pipe is really complicated */
4120 switch (pipe) {
4121 case PIPE_A:
4122 return true;
4123 case PIPE_B:
4124 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4125 pipe_config->fdi_lanes > 2) {
4126 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4127 pipe_name(pipe), pipe_config->fdi_lanes);
4128 return false;
4129 }
4130 return true;
4131 case PIPE_C:
1e833f40 4132 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 4133 pipe_B_crtc->config.fdi_lanes <= 2) {
4134 if (pipe_config->fdi_lanes > 2) {
4135 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4136 pipe_name(pipe), pipe_config->fdi_lanes);
4137 return false;
4138 }
4139 } else {
4140 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4141 return false;
4142 }
4143 return true;
4144 default:
4145 BUG();
4146 }
4147}
4148
e29c22c0
DV		 4149#define RETRY 1
4150static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4151 struct intel_crtc_config *pipe_config)
877d48d5 4152{
1857e1da 4153 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 4154 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 4155 int lane, link_bw, fdi_dotclock;
e29c22c0 4156 bool setup_ok, needs_recompute = false;
877d48d5 4157
e29c22c0 4158retry:
877d48d5
DV		 4159 /* FDI is a binary signal running at ~2.7GHz, encoding
4160 * each output octet as 10 bits. The actual frequency
4161 * is stored as a divider into a 100MHz clock, and the
4162 * mode pixel clock is stored in units of 1KHz.
4163 * Hence the bw of each lane in terms of the mode signal
4164 * is:
4165 */
4166 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4167
241bfc38 4168 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 4169
2bd89a07 4170 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 4171 pipe_config->pipe_bpp);
4172
4173 pipe_config->fdi_lanes = lane;
4174
2bd89a07 4175 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4176 link_bw, &pipe_config->fdi_m_n);
1857e1da 4177
e29c22c0
DV		 4178 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4179 intel_crtc->pipe, pipe_config);
4180 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4181 pipe_config->pipe_bpp -= 2*3;
4182 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4183 pipe_config->pipe_bpp);
4184 needs_recompute = true;
4185 pipe_config->bw_constrained = true;
4186
4187 goto retry;
4188 }
4189
4190 if (needs_recompute)
4191 return RETRY;
4192
4193 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4194}
4195
42db64ef
PZ		 4196static void hsw_compute_ips_config(struct intel_crtc *crtc,
4197 struct intel_crtc_config *pipe_config)
4198{
3c4ca58c
PZ		 4199 pipe_config->ips_enabled = i915_enable_ips &&
4200 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 4201 pipe_config->pipe_bpp <= 24;
42db64ef
PZ		 4202}
4203
a43f6e0f 4204static int intel_crtc_compute_config(struct intel_crtc *crtc,
e29c22c0 4205 struct intel_crtc_config *pipe_config)
79e53945 4206{
a43f6e0f 4207 struct drm_device *dev = crtc->base.dev;
b8cecdf5 4208 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4209
ad3a4479 4210 /* FIXME should check pixel clock limits on all platforms */
cf532bb2
VS		 4211 if (INTEL_INFO(dev)->gen < 4) {
4212 struct drm_i915_private *dev_priv = dev->dev_private;
4213 int clock_limit =
4214 dev_priv->display.get_display_clock_speed(dev);
4215
4216 /*
4217 * Enable pixel doubling when the dot clock
4218 * is > 90% of the (display) core speed.
4219 *
b397c96b
VS		 4220 * GDG double wide on either pipe,
4221 * otherwise pipe A only.
cf532bb2 4222 */
b397c96b 4223 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 4224 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 4225 clock_limit *= 2;
cf532bb2 4226 pipe_config->double_wide = true;
ad3a4479
VS		 4227 }
4228
241bfc38 4229 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 4230 return -EINVAL;
2c07245f 4231 }
89749350 4232
1d1d0e27
VS		 4233 /*
4234 * Pipe horizontal size must be even in:
4235 * - DVO ganged mode
4236 * - LVDS dual channel mode
4237 * - Double wide pipe
4238 */
4239 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4240 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4241 pipe_config->pipe_src_w &= ~1;
4242
8693a824
DL		 4243 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4244 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4245 */
4246 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4247 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4248 return -EINVAL;
44f46b42 4249
bd080ee5 4250 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4251 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4252 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4253 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4254 * for lvds. */
4255 pipe_config->pipe_bpp = 8*3;
4256 }
4257
f5adf94e 4258 if (HAS_IPS(dev))
a43f6e0f
DV		 4259 hsw_compute_ips_config(crtc, pipe_config);
4260
4261 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4262 * clock survives for now. */
4263 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4264 pipe_config->shared_dpll = crtc->config.shared_dpll;
42db64ef 4265
877d48d5 4266 if (pipe_config->has_pch_encoder)
a43f6e0f 4267 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 4268
e29c22c0 4269 return 0;
79e53945
JB		 4270}
4271
25eb05fc
JB		 4272static int valleyview_get_display_clock_speed(struct drm_device *dev)
4273{
4274 return 400000; /* FIXME */
4275}
4276
e70236a8
JB		 4277static int i945_get_display_clock_speed(struct drm_device *dev)
4278{
4279 return 400000;
4280}
79e53945 4281
e70236a8 4282static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4283{
e70236a8
JB		 4284 return 333000;
4285}
79e53945 4286
e70236a8
JB		 4287static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4288{
4289 return 200000;
4290}
79e53945 4291
257a7ffc
DV		 4292static int pnv_get_display_clock_speed(struct drm_device *dev)
4293{
4294 u16 gcfgc = 0;
4295
4296 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4297
4298 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4299 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4300 return 267000;
4301 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4302 return 333000;
4303 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4304 return 444000;
4305 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4306 return 200000;
4307 default:
4308 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4309 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4310 return 133000;
4311 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4312 return 167000;
4313 }
4314}
4315
e70236a8
JB		 4316static int i915gm_get_display_clock_speed(struct drm_device *dev)
4317{
4318 u16 gcfgc = 0;
79e53945 4319
e70236a8
JB		 4320 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4321
4322 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4323 return 133000;
4324 else {
4325 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4326 case GC_DISPLAY_CLOCK_333_MHZ:
4327 return 333000;
4328 default:
4329 case GC_DISPLAY_CLOCK_190_200_MHZ:
4330 return 190000;
79e53945 4331 }
e70236a8
JB		 4332 }
4333}
4334
4335static int i865_get_display_clock_speed(struct drm_device *dev)
4336{
4337 return 266000;
4338}
4339
4340static int i855_get_display_clock_speed(struct drm_device *dev)
4341{
4342 u16 hpllcc = 0;
4343 /* Assume that the hardware is in the high speed state. This
4344 * should be the default.
4345 */
4346 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4347 case GC_CLOCK_133_200:
4348 case GC_CLOCK_100_200:
4349 return 200000;
4350 case GC_CLOCK_166_250:
4351 return 250000;
4352 case GC_CLOCK_100_133:
79e53945 4353 return 133000;
e70236a8 4354 }
79e53945 4355
e70236a8
JB		 4356 /* Shouldn't happen */
4357 return 0;
4358}
79e53945 4359
e70236a8
JB		 4360static int i830_get_display_clock_speed(struct drm_device *dev)
4361{
4362 return 133000;
79e53945
JB		 4363}
4364
2c07245f 4365static void
a65851af 4366intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4367{
a65851af
VS		 4368 while (*num > DATA_LINK_M_N_MASK ||
4369 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4370 *num >>= 1;
4371 *den >>= 1;
4372 }
4373}
4374
a65851af
VS		 4375static void compute_m_n(unsigned int m, unsigned int n,
4376 uint32_t *ret_m, uint32_t *ret_n)
4377{
4378 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4379 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4380 intel_reduce_m_n_ratio(ret_m, ret_n);
4381}
4382
e69d0bc1
DV		 4383void
4384intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4385 int pixel_clock, int link_clock,
4386 struct intel_link_m_n *m_n)
2c07245f 4387{
e69d0bc1 4388 m_n->tu = 64;
a65851af
VS		 4389
4390 compute_m_n(bits_per_pixel * pixel_clock,
4391 link_clock * nlanes * 8,
4392 &m_n->gmch_m, &m_n->gmch_n);
4393
4394 compute_m_n(pixel_clock, link_clock,
4395 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4396}
4397
a7615030
CW		 4398static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4399{
72bbe58c
KP		 4400 if (i915_panel_use_ssc >= 0)
4401 return i915_panel_use_ssc != 0;
41aa3448 4402 return dev_priv->vbt.lvds_use_ssc
435793df 4403 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4404}
4405
c65d77d8
JB		 4406static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4407{
4408 struct drm_device *dev = crtc->dev;
4409 struct drm_i915_private *dev_priv = dev->dev_private;
4410 int refclk;
4411
a0c4da24 4412 if (IS_VALLEYVIEW(dev)) {
9a0ea498 4413 refclk = 100000;
a0c4da24 4414 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4415 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4416 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4417 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4418 refclk / 1000);
4419 } else if (!IS_GEN2(dev)) {
4420 refclk = 96000;
4421 } else {
4422 refclk = 48000;
4423 }
4424
4425 return refclk;
4426}
4427
7429e9d4 4428static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 4429{
7df00d7a 4430 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 4431}
f47709a9 4432
7429e9d4
DV		 4433static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4434{
4435 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 4436}
4437
f47709a9 4438static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4439 intel_clock_t *reduced_clock)
4440{
f47709a9 4441 struct drm_device *dev = crtc->base.dev;
a7516a05 4442 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4443 int pipe = crtc->pipe;
a7516a05
JB		 4444 u32 fp, fp2 = 0;
4445
4446 if (IS_PINEVIEW(dev)) {
7429e9d4 4447 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4448 if (reduced_clock)
7429e9d4 4449 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4450 } else {
7429e9d4 4451 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4452 if (reduced_clock)
7429e9d4 4453 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4454 }
4455
4456 I915_WRITE(FP0(pipe), fp);
8bcc2795 4457 crtc->config.dpll_hw_state.fp0 = fp;
a7516a05 4458
f47709a9
DV		 4459 crtc->lowfreq_avail = false;
4460 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4461 reduced_clock && i915_powersave) {
4462 I915_WRITE(FP1(pipe), fp2);
8bcc2795 4463 crtc->config.dpll_hw_state.fp1 = fp2;
f47709a9 4464 crtc->lowfreq_avail = true;
a7516a05
JB		 4465 } else {
4466 I915_WRITE(FP1(pipe), fp);
8bcc2795 4467 crtc->config.dpll_hw_state.fp1 = fp;
a7516a05
JB		 4468 }
4469}
4470
5e69f97f
CML		 4471static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4472 pipe)
89b667f8
JB		 4473{
4474 u32 reg_val;
4475
4476 /*
4477 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4478 * and set it to a reasonable value instead.
4479 */
5e69f97f 4480 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
89b667f8
JB		 4481 reg_val &= 0xffffff00;
4482 reg_val |= 0x00000030;
5e69f97f 4483 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
89b667f8 4484
5e69f97f 4485 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
89b667f8
JB		 4486 reg_val &= 0x8cffffff;
4487 reg_val = 0x8c000000;
5e69f97f 4488 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
89b667f8 4489
5e69f97f 4490 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
89b667f8 4491 reg_val &= 0xffffff00;
5e69f97f 4492 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
89b667f8 4493
5e69f97f 4494 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
89b667f8
JB		 4495 reg_val &= 0x00ffffff;
4496 reg_val |= 0xb0000000;
5e69f97f 4497 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4498}
4499
b551842d
DV		 4500static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4501 struct intel_link_m_n *m_n)
4502{
4503 struct drm_device *dev = crtc->base.dev;
4504 struct drm_i915_private *dev_priv = dev->dev_private;
4505 int pipe = crtc->pipe;
4506
e3b95f1e
DV		 4507 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4508 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4509 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4510 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4511}
4512
4513static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4514 struct intel_link_m_n *m_n)
4515{
4516 struct drm_device *dev = crtc->base.dev;
4517 struct drm_i915_private *dev_priv = dev->dev_private;
4518 int pipe = crtc->pipe;
4519 enum transcoder transcoder = crtc->config.cpu_transcoder;
4520
4521 if (INTEL_INFO(dev)->gen >= 5) {
4522 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4523 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4524 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4525 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4526 } else {
e3b95f1e
DV		 4527 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4528 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4529 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4530 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4531 }
4532}
4533
03afc4a2
DV		 4534static void intel_dp_set_m_n(struct intel_crtc *crtc)
4535{
4536 if (crtc->config.has_pch_encoder)
4537 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4538 else
4539 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4540}
4541
f47709a9 4542static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4543{
f47709a9 4544 struct drm_device *dev = crtc->base.dev;
a0c4da24 4545 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4546 int pipe = crtc->pipe;
89b667f8 4547 u32 dpll, mdiv;
a0c4da24 4548 u32 bestn, bestm1, bestm2, bestp1, bestp2;
198a037f 4549 u32 coreclk, reg_val, dpll_md;
a0c4da24 4550
09153000
DV		 4551 mutex_lock(&dev_priv->dpio_lock);
4552
f47709a9
DV		 4553 bestn = crtc->config.dpll.n;
4554 bestm1 = crtc->config.dpll.m1;
4555 bestm2 = crtc->config.dpll.m2;
4556 bestp1 = crtc->config.dpll.p1;
4557 bestp2 = crtc->config.dpll.p2;
a0c4da24 4558
89b667f8
JB		 4559 /* See eDP HDMI DPIO driver vbios notes doc */
4560
4561 /* PLL B needs special handling */
4562 if (pipe)
5e69f97f 4563 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 4564
4565 /* Set up Tx target for periodic Rcomp update */
5e69f97f 4566 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4567
4568 /* Disable target IRef on PLL */
5e69f97f 4569 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe));
89b667f8 4570 reg_val &= 0x00ffffff;
5e69f97f 4571 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4572
4573 /* Disable fast lock */
5e69f97f 4574 vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4575
4576 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4577 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4578 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4579 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4580 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4581
4582 /*
4583 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4584 * but we don't support that).
4585 * Note: don't use the DAC post divider as it seems unstable.
4586 */
4587 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5e69f97f 4588 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
a0c4da24 4589
a0c4da24 4590 mdiv |= DPIO_ENABLE_CALIBRATION;
5e69f97f 4591 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
a0c4da24 4592
89b667f8 4593 /* Set HBR and RBR LPF coefficients */
ff9a6750 4594 if (crtc->config.port_clock == 162000 ||
99750bd4 4595 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
89b667f8 4596 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5e69f97f 4597 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
885b0120 4598 0x009f0003);
89b667f8 4599 else
5e69f97f 4600 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
89b667f8
JB		 4601 0x00d0000f);
4602
4603 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4604 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4605 /* Use SSC source */
4606 if (!pipe)
5e69f97f 4607 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4608 0x0df40000);
4609 else
5e69f97f 4610 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4611 0x0df70000);
4612 } else { /* HDMI or VGA */
4613 /* Use bend source */
4614 if (!pipe)
5e69f97f 4615 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4616 0x0df70000);
4617 else
5e69f97f 4618 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4619 0x0df40000);
4620 }
a0c4da24 4621
5e69f97f 4622 coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4623 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4624 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4625 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4626 coreclk |= 0x01000000;
5e69f97f 4627 vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4628
5e69f97f 4629 vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4630
89b667f8
JB		 4631 /* Enable DPIO clock input */
4632 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4633 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
f6071166
JB		 4634 /* We should never disable this, set it here for state tracking */
4635 if (pipe == PIPE_B)
89b667f8 4636 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
a0c4da24 4637 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4638 crtc->config.dpll_hw_state.dpll = dpll;
4639
ef1b460d
DV		 4640 dpll_md = (crtc->config.pixel_multiplier - 1)
4641 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795
DV		 4642 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4643
89b667f8
JB		 4644 if (crtc->config.has_dp_encoder)
4645 intel_dp_set_m_n(crtc);
09153000
DV		 4646
4647 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4648}
4649
f47709a9
DV		 4650static void i9xx_update_pll(struct intel_crtc *crtc,
4651 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4652 int num_connectors)
4653{
f47709a9 4654 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4655 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 4656 u32 dpll;
4657 bool is_sdvo;
f47709a9 4658 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4659
f47709a9 4660 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4661
f47709a9
DV		 4662 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4663 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4664
4665 dpll = DPLL_VGA_MODE_DIS;
4666
f47709a9 4667 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4668 dpll |= DPLLB_MODE_LVDS;
4669 else
4670 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4671
ef1b460d 4672 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
198a037f
DV		 4673 dpll |= (crtc->config.pixel_multiplier - 1)
4674 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4675 }
198a037f
DV		 4676
4677 if (is_sdvo)
4a33e48d 4678 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 4679
f47709a9 4680 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4a33e48d 4681 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 4682
4683 /* compute bitmask from p1 value */
4684 if (IS_PINEVIEW(dev))
4685 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4686 else {
4687 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4688 if (IS_G4X(dev) && reduced_clock)
4689 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4690 }
4691 switch (clock->p2) {
4692 case 5:
4693 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4694 break;
4695 case 7:
4696 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4697 break;
4698 case 10:
4699 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4700 break;
4701 case 14:
4702 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4703 break;
4704 }
4705 if (INTEL_INFO(dev)->gen >= 4)
4706 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4707
09ede541 4708 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4709 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4710 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4711 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4712 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4713 else
4714 dpll |= PLL_REF_INPUT_DREFCLK;
4715
4716 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4717 crtc->config.dpll_hw_state.dpll = dpll;
4718
eb1cbe48 4719 if (INTEL_INFO(dev)->gen >= 4) {
ef1b460d
DV		 4720 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4721 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795 4722 crtc->config.dpll_hw_state.dpll_md = dpll_md;
eb1cbe48 4723 }
66e3d5c0
DV		 4724
4725 if (crtc->config.has_dp_encoder)
4726 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4727}
4728
f47709a9 4729static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 4730 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4731 int num_connectors)
4732{
f47709a9 4733 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4734 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 4735 u32 dpll;
f47709a9 4736 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4737
f47709a9 4738 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4739
eb1cbe48
DV		 4740 dpll = DPLL_VGA_MODE_DIS;
4741
f47709a9 4742 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4743 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4744 } else {
4745 if (clock->p1 == 2)
4746 dpll |= PLL_P1_DIVIDE_BY_TWO;
4747 else
4748 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4749 if (clock->p2 == 4)
4750 dpll |= PLL_P2_DIVIDE_BY_4;
4751 }
4752
4a33e48d
DV		 4753 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4754 dpll |= DPLL_DVO_2X_MODE;
4755
f47709a9 4756 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4757 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4758 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4759 else
4760 dpll |= PLL_REF_INPUT_DREFCLK;
4761
4762 dpll |= DPLL_VCO_ENABLE;
8bcc2795 4763 crtc->config.dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 4764}
4765
8a654f3b 4766static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 4767{
4768 struct drm_device *dev = intel_crtc->base.dev;
4769 struct drm_i915_private *dev_priv = dev->dev_private;
4770 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4771 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV		 4772 struct drm_display_mode *adjusted_mode =
4773 &intel_crtc->config.adjusted_mode;
4d8a62ea
DV		 4774 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4775
4776 /* We need to be careful not to changed the adjusted mode, for otherwise
4777 * the hw state checker will get angry at the mismatch. */
4778 crtc_vtotal = adjusted_mode->crtc_vtotal;
4779 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4780
4781 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4782 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4783 crtc_vtotal -= 1;
4784 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4785 vsyncshift = adjusted_mode->crtc_hsync_start
4786 - adjusted_mode->crtc_htotal / 2;
4787 } else {
4788 vsyncshift = 0;
4789 }
4790
4791 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4792 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4793
fe2b8f9d 4794 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4795 (adjusted_mode->crtc_hdisplay - 1) |
4796 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4797 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4798 (adjusted_mode->crtc_hblank_start - 1) |
4799 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4800 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4801 (adjusted_mode->crtc_hsync_start - 1) |
4802 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4803
fe2b8f9d 4804 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4805 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4806 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4807 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4808 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4809 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4810 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4811 (adjusted_mode->crtc_vsync_start - 1) |
4812 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4813
b5e508d4
PZ		 4814 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4815 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4816 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4817 * bits. */
4818 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4819 (pipe == PIPE_B || pipe == PIPE_C))
4820 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4821
b0e77b9c
PZ		 4822 /* pipesrc controls the size that is scaled from, which should
4823 * always be the user's requested size.
4824 */
4825 I915_WRITE(PIPESRC(pipe),
37327abd
VS		 4826 ((intel_crtc->config.pipe_src_w - 1) << 16) |
4827 (intel_crtc->config.pipe_src_h - 1));
b0e77b9c
PZ		 4828}
4829
1bd1bd80
DV		 4830static void intel_get_pipe_timings(struct intel_crtc *crtc,
4831 struct intel_crtc_config *pipe_config)
4832{
4833 struct drm_device *dev = crtc->base.dev;
4834 struct drm_i915_private *dev_priv = dev->dev_private;
4835 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4836 uint32_t tmp;
4837
4838 tmp = I915_READ(HTOTAL(cpu_transcoder));
4839 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4840 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4841 tmp = I915_READ(HBLANK(cpu_transcoder));
4842 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4843 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4844 tmp = I915_READ(HSYNC(cpu_transcoder));
4845 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4846 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4847
4848 tmp = I915_READ(VTOTAL(cpu_transcoder));
4849 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4850 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4851 tmp = I915_READ(VBLANK(cpu_transcoder));
4852 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4853 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4854 tmp = I915_READ(VSYNC(cpu_transcoder));
4855 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4856 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4857
4858 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4859 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4860 pipe_config->adjusted_mode.crtc_vtotal += 1;
4861 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4862 }
4863
4864 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 4865 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
4866 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
4867
4868 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
4869 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 4870}
4871
babea61d
JB		 4872static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4873 struct intel_crtc_config *pipe_config)
4874{
4875 struct drm_crtc *crtc = &intel_crtc->base;
4876
4877 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4878 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4879 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4880 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4881
4882 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4883 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4884 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4885 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4886
4887 crtc->mode.flags = pipe_config->adjusted_mode.flags;
4888
241bfc38 4889 crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock;
babea61d
JB		 4890 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4891}
4892
84b046f3
DV		 4893static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4894{
4895 struct drm_device *dev = intel_crtc->base.dev;
4896 struct drm_i915_private *dev_priv = dev->dev_private;
4897 uint32_t pipeconf;
4898
9f11a9e4 4899 pipeconf = 0;
84b046f3 4900
67c72a12
DV		 4901 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
4902 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
4903 pipeconf |= PIPECONF_ENABLE;
4904
cf532bb2
VS		 4905 if (intel_crtc->config.double_wide)
4906 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 4907
ff9ce46e
DV		 4908 /* only g4x and later have fancy bpc/dither controls */
4909 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e
DV		 4910 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4911 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4912 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4913 PIPECONF_DITHER_TYPE_SP;
84b046f3 4914
ff9ce46e
DV		 4915 switch (intel_crtc->config.pipe_bpp) {
4916 case 18:
4917 pipeconf |= PIPECONF_6BPC;
4918 break;
4919 case 24:
4920 pipeconf |= PIPECONF_8BPC;
4921 break;
4922 case 30:
4923 pipeconf |= PIPECONF_10BPC;
4924 break;
4925 default:
4926 /* Case prevented by intel_choose_pipe_bpp_dither. */
4927 BUG();
84b046f3
DV		 4928 }
4929 }
4930
4931 if (HAS_PIPE_CXSR(dev)) {
4932 if (intel_crtc->lowfreq_avail) {
4933 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4934 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4935 } else {
4936 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 4937 }
4938 }
4939
84b046f3
DV		 4940 if (!IS_GEN2(dev) &&
4941 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4942 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4943 else
4944 pipeconf |= PIPECONF_PROGRESSIVE;
4945
9f11a9e4
DV		 4946 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4947 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 4948
84b046f3
DV		 4949 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4950 POSTING_READ(PIPECONF(intel_crtc->pipe));
4951}
4952
f564048e 4953static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4954 int x, int y,
94352cf9 4955 struct drm_framebuffer *fb)
79e53945
JB		 4956{
4957 struct drm_device *dev = crtc->dev;
4958 struct drm_i915_private *dev_priv = dev->dev_private;
4959 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4960 int pipe = intel_crtc->pipe;
80824003 4961 int plane = intel_crtc->plane;
c751ce4f 4962 int refclk, num_connectors = 0;
652c393a 4963 intel_clock_t clock, reduced_clock;
84b046f3 4964 u32 dspcntr;
a16af721 4965 bool ok, has_reduced_clock = false;
e9fd1c02 4966 bool is_lvds = false, is_dsi = false;
5eddb70b 4967 struct intel_encoder *encoder;
d4906093 4968 const intel_limit_t *limit;
5c3b82e2 4969 int ret;
79e53945 4970
6c2b7c12 4971 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4972 switch (encoder->type) {
79e53945
JB		 4973 case INTEL_OUTPUT_LVDS:
4974 is_lvds = true;
4975 break;
e9fd1c02
JN		 4976 case INTEL_OUTPUT_DSI:
4977 is_dsi = true;
4978 break;
79e53945 4979 }
43565a06 4980
c751ce4f 4981 num_connectors++;
79e53945
JB		 4982 }
4983
f2335330
JN		 4984 if (is_dsi)
4985 goto skip_dpll;
4986
4987 if (!intel_crtc->config.clock_set) {
4988 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4989
e9fd1c02
JN		 4990 /*
4991 * Returns a set of divisors for the desired target clock with
4992 * the given refclk, or FALSE. The returned values represent
4993 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
4994 * 2) / p1 / p2.
4995 */
4996 limit = intel_limit(crtc, refclk);
4997 ok = dev_priv->display.find_dpll(limit, crtc,
4998 intel_crtc->config.port_clock,
4999 refclk, NULL, &clock);
f2335330 5000 if (!ok) {
e9fd1c02
JN		 5001 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5002 return -EINVAL;
5003 }
79e53945 5004
f2335330
JN		 5005 if (is_lvds && dev_priv->lvds_downclock_avail) {
5006 /*
5007 * Ensure we match the reduced clock's P to the target
5008 * clock. If the clocks don't match, we can't switch
5009 * the display clock by using the FP0/FP1. In such case
5010 * we will disable the LVDS downclock feature.
5011 */
5012 has_reduced_clock =
5013 dev_priv->display.find_dpll(limit, crtc,
5014 dev_priv->lvds_downclock,
5015 refclk, &clock,
5016 &reduced_clock);
5017 }
5018 /* Compat-code for transition, will disappear. */
f47709a9
DV		 5019 intel_crtc->config.dpll.n = clock.n;
5020 intel_crtc->config.dpll.m1 = clock.m1;
5021 intel_crtc->config.dpll.m2 = clock.m2;
5022 intel_crtc->config.dpll.p1 = clock.p1;
5023 intel_crtc->config.dpll.p2 = clock.p2;
5024 }
7026d4ac 5025
e9fd1c02 5026 if (IS_GEN2(dev)) {
8a654f3b 5027 i8xx_update_pll(intel_crtc,
2a8f64ca
VP		 5028 has_reduced_clock ? &reduced_clock : NULL,
5029 num_connectors);
e9fd1c02 5030 } else if (IS_VALLEYVIEW(dev)) {
f2335330 5031 vlv_update_pll(intel_crtc);
e9fd1c02 5032 } else {
f47709a9 5033 i9xx_update_pll(intel_crtc,
eb1cbe48 5034 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 5035 num_connectors);
e9fd1c02 5036 }
79e53945 5037
f2335330 5038skip_dpll:
79e53945
JB		 5039 /* Set up the display plane register */
5040 dspcntr = DISPPLANE_GAMMA_ENABLE;
5041
da6ecc5d
JB		 5042 if (!IS_VALLEYVIEW(dev)) {
5043 if (pipe == 0)
5044 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5045 else
5046 dspcntr |= DISPPLANE_SEL_PIPE_B;
5047 }
79e53945 5048
8a654f3b 5049 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW		 5050
5051 /* pipesrc and dspsize control the size that is scaled from,
5052 * which should always be the user's requested size.
79e53945 5053 */
929c77fb 5054 I915_WRITE(DSPSIZE(plane),
37327abd
VS		 5055 ((intel_crtc->config.pipe_src_h - 1) << 16) |
5056 (intel_crtc->config.pipe_src_w - 1));
929c77fb 5057 I915_WRITE(DSPPOS(plane), 0);
2c07245f 5058
84b046f3
DV		 5059 i9xx_set_pipeconf(intel_crtc);
5060
f564048e
EA		 5061 I915_WRITE(DSPCNTR(plane), dspcntr);
5062 POSTING_READ(DSPCNTR(plane));
5063
94352cf9 5064 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e 5065
f564048e
EA		 5066 return ret;
5067}
5068
2fa2fe9a
DV		 5069static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5070 struct intel_crtc_config *pipe_config)
5071{
5072 struct drm_device *dev = crtc->base.dev;
5073 struct drm_i915_private *dev_priv = dev->dev_private;
5074 uint32_t tmp;
5075
5076 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 5077 if (!(tmp & PFIT_ENABLE))
5078 return;
2fa2fe9a 5079
06922821 5080 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 5081 if (INTEL_INFO(dev)->gen < 4) {
5082 if (crtc->pipe != PIPE_B)
5083 return;
2fa2fe9a
DV		 5084 } else {
5085 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5086 return;
5087 }
5088
06922821 5089 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 5090 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5091 if (INTEL_INFO(dev)->gen < 5)
5092 pipe_config->gmch_pfit.lvds_border_bits =
5093 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5094}
5095
acbec814
JB		 5096static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5097 struct intel_crtc_config *pipe_config)
5098{
5099 struct drm_device *dev = crtc->base.dev;
5100 struct drm_i915_private *dev_priv = dev->dev_private;
5101 int pipe = pipe_config->cpu_transcoder;
5102 intel_clock_t clock;
5103 u32 mdiv;
662c6ecb 5104 int refclk = 100000;
acbec814
JB		 5105
5106 mutex_lock(&dev_priv->dpio_lock);
5107 mdiv = vlv_dpio_read(dev_priv, pipe, DPIO_DIV(pipe));
5108 mutex_unlock(&dev_priv->dpio_lock);
5109
5110 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5111 clock.m2 = mdiv & DPIO_M2DIV_MASK;
5112 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5113 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5114 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5115
662c6ecb
CW		 5116 clock.vco = refclk * clock.m1 * clock.m2 / clock.n;
5117 clock.dot = 2 * clock.vco / (clock.p1 * clock.p2);
acbec814
JB		 5118
5119 pipe_config->port_clock = clock.dot / 10;
5120}
5121
0e8ffe1b
DV		 5122static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5123 struct intel_crtc_config *pipe_config)
5124{
5125 struct drm_device *dev = crtc->base.dev;
5126 struct drm_i915_private *dev_priv = dev->dev_private;
5127 uint32_t tmp;
5128
e143a21c 5129 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 5130 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5131
0e8ffe1b
DV		 5132 tmp = I915_READ(PIPECONF(crtc->pipe));
5133 if (!(tmp & PIPECONF_ENABLE))
5134 return false;
5135
42571aef
VS		 5136 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5137 switch (tmp & PIPECONF_BPC_MASK) {
5138 case PIPECONF_6BPC:
5139 pipe_config->pipe_bpp = 18;
5140 break;
5141 case PIPECONF_8BPC:
5142 pipe_config->pipe_bpp = 24;
5143 break;
5144 case PIPECONF_10BPC:
5145 pipe_config->pipe_bpp = 30;
5146 break;
5147 default:
5148 break;
5149 }
5150 }
5151
282740f7
VS		 5152 if (INTEL_INFO(dev)->gen < 4)
5153 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5154
1bd1bd80
DV		 5155 intel_get_pipe_timings(crtc, pipe_config);
5156
2fa2fe9a
DV		 5157 i9xx_get_pfit_config(crtc, pipe_config);
5158
6c49f241
DV		 5159 if (INTEL_INFO(dev)->gen >= 4) {
5160 tmp = I915_READ(DPLL_MD(crtc->pipe));
5161 pipe_config->pixel_multiplier =
5162 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5163 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 5164 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 5165 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5166 tmp = I915_READ(DPLL(crtc->pipe));
5167 pipe_config->pixel_multiplier =
5168 ((tmp & SDVO_MULTIPLIER_MASK)
5169 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5170 } else {
5171 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5172 * port and will be fixed up in the encoder->get_config
5173 * function. */
5174 pipe_config->pixel_multiplier = 1;
5175 }
8bcc2795
DV		 5176 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5177 if (!IS_VALLEYVIEW(dev)) {
5178 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5179 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 5180 } else {
5181 /* Mask out read-only status bits. */
5182 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5183 DPLL_PORTC_READY_MASK |
5184 DPLL_PORTB_READY_MASK);
8bcc2795 5185 }
6c49f241 5186
acbec814
JB		 5187 if (IS_VALLEYVIEW(dev))
5188 vlv_crtc_clock_get(crtc, pipe_config);
5189 else
5190 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 5191
0e8ffe1b
DV		 5192 return true;
5193}
5194
dde86e2d 5195static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5196{
5197 struct drm_i915_private *dev_priv = dev->dev_private;
5198 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5199 struct intel_encoder *encoder;
74cfd7ac 5200 u32 val, final;
13d83a67 5201 bool has_lvds = false;
199e5d79 5202 bool has_cpu_edp = false;
199e5d79 5203 bool has_panel = false;
99eb6a01
KP		 5204 bool has_ck505 = false;
5205 bool can_ssc = false;
13d83a67
JB		 5206
5207 /* We need to take the global config into account */
199e5d79
KP		 5208 list_for_each_entry(encoder, &mode_config->encoder_list,
5209 base.head) {
5210 switch (encoder->type) {
5211 case INTEL_OUTPUT_LVDS:
5212 has_panel = true;
5213 has_lvds = true;
5214 break;
5215 case INTEL_OUTPUT_EDP:
5216 has_panel = true;
2de6905f 5217 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5218 has_cpu_edp = true;
5219 break;
13d83a67
JB		 5220 }
5221 }
5222
99eb6a01 5223 if (HAS_PCH_IBX(dev)) {
41aa3448 5224 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5225 can_ssc = has_ck505;
5226 } else {
5227 has_ck505 = false;
5228 can_ssc = true;
5229 }
5230
2de6905f
ID		 5231 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5232 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5233
5234 /* Ironlake: try to setup display ref clock before DPLL
5235 * enabling. This is only under driver's control after
5236 * PCH B stepping, previous chipset stepping should be
5237 * ignoring this setting.
5238 */
74cfd7ac
CW		 5239 val = I915_READ(PCH_DREF_CONTROL);
5240
5241 /* As we must carefully and slowly disable/enable each source in turn,
5242 * compute the final state we want first and check if we need to
5243 * make any changes at all.
5244 */
5245 final = val;
5246 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5247 if (has_ck505)
5248 final |= DREF_NONSPREAD_CK505_ENABLE;
5249 else
5250 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5251
5252 final &= ~DREF_SSC_SOURCE_MASK;
5253 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5254 final &= ~DREF_SSC1_ENABLE;
5255
5256 if (has_panel) {
5257 final |= DREF_SSC_SOURCE_ENABLE;
5258
5259 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5260 final |= DREF_SSC1_ENABLE;
5261
5262 if (has_cpu_edp) {
5263 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5264 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5265 else
5266 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5267 } else
5268 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5269 } else {
5270 final |= DREF_SSC_SOURCE_DISABLE;
5271 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5272 }
5273
5274 if (final == val)
5275 return;
5276
13d83a67 5277 /* Always enable nonspread source */
74cfd7ac 5278 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5279
99eb6a01 5280 if (has_ck505)
74cfd7ac 5281 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5282 else
74cfd7ac 5283 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5284
199e5d79 5285 if (has_panel) {
74cfd7ac
CW		 5286 val &= ~DREF_SSC_SOURCE_MASK;
5287 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5288
199e5d79 5289 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5290 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5291 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5292 val |= DREF_SSC1_ENABLE;
e77166b5 5293 } else
74cfd7ac 5294 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5295
5296 /* Get SSC going before enabling the outputs */
74cfd7ac 5297 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5298 POSTING_READ(PCH_DREF_CONTROL);
5299 udelay(200);
5300
74cfd7ac 5301 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5302
5303 /* Enable CPU source on CPU attached eDP */
199e5d79 5304 if (has_cpu_edp) {
99eb6a01 5305 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5306 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5307 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5308 }
13d83a67 5309 else
74cfd7ac 5310 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5311 } else
74cfd7ac 5312 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5313
74cfd7ac 5314 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5315 POSTING_READ(PCH_DREF_CONTROL);
5316 udelay(200);
5317 } else {
5318 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5319
74cfd7ac 5320 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5321
5322 /* Turn off CPU output */
74cfd7ac 5323 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5324
74cfd7ac 5325 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5326 POSTING_READ(PCH_DREF_CONTROL);
5327 udelay(200);
5328
5329 /* Turn off the SSC source */
74cfd7ac
CW		 5330 val &= ~DREF_SSC_SOURCE_MASK;
5331 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5332
5333 /* Turn off SSC1 */
74cfd7ac 5334 val &= ~DREF_SSC1_ENABLE;
199e5d79 5335
74cfd7ac 5336 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5337 POSTING_READ(PCH_DREF_CONTROL);
5338 udelay(200);
5339 }
74cfd7ac
CW		 5340
5341 BUG_ON(val != final);
13d83a67
JB		 5342}
5343
f31f2d55 5344static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 5345{
f31f2d55 5346 uint32_t tmp;
dde86e2d 5347
0ff066a9
PZ		 5348 tmp = I915_READ(SOUTH_CHICKEN2);
5349 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5350 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5351
0ff066a9
PZ		 5352 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5353 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5354 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 5355
0ff066a9
PZ		 5356 tmp = I915_READ(SOUTH_CHICKEN2);
5357 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5358 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5359
0ff066a9
PZ		 5360 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5361 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5362 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 5363}
5364
5365/* WaMPhyProgramming:hsw */
5366static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5367{
5368 uint32_t tmp;
dde86e2d
PZ		 5369
5370 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5371 tmp &= ~(0xFF << 24);
5372 tmp |= (0x12 << 24);
5373 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5374
dde86e2d
PZ		 5375 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5376 tmp |= (1 << 11);
5377 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5378
5379 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5380 tmp |= (1 << 11);
5381 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5382
dde86e2d
PZ		 5383 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5384 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5385 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5386
5387 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5388 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5389 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5390
0ff066a9
PZ		 5391 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5392 tmp &= ~(7 << 13);
5393 tmp |= (5 << 13);
5394 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 5395
0ff066a9
PZ		 5396 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5397 tmp &= ~(7 << 13);
5398 tmp |= (5 << 13);
5399 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 5400
5401 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5402 tmp &= ~0xFF;
5403 tmp |= 0x1C;
5404 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5405
5406 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5407 tmp &= ~0xFF;
5408 tmp |= 0x1C;
5409 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5410
5411 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5412 tmp &= ~(0xFF << 16);
5413 tmp |= (0x1C << 16);
5414 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5415
5416 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5417 tmp &= ~(0xFF << 16);
5418 tmp |= (0x1C << 16);
5419 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5420
0ff066a9
PZ		 5421 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5422 tmp |= (1 << 27);
5423 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 5424
0ff066a9
PZ		 5425 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5426 tmp |= (1 << 27);
5427 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 5428
0ff066a9
PZ		 5429 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5430 tmp &= ~(0xF << 28);
5431 tmp |= (4 << 28);
5432 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 5433
0ff066a9
PZ		 5434 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5435 tmp &= ~(0xF << 28);
5436 tmp |= (4 << 28);
5437 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 5438}
5439
2fa86a1f
PZ		 5440/* Implements 3 different sequences from BSpec chapter "Display iCLK
5441 * Programming" based on the parameters passed:
5442 * - Sequence to enable CLKOUT_DP
5443 * - Sequence to enable CLKOUT_DP without spread
5444 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5445 */
5446static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5447 bool with_fdi)
f31f2d55
PZ		 5448{
5449 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 5450 uint32_t reg, tmp;
5451
5452 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5453 with_spread = true;
5454 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5455 with_fdi, "LP PCH doesn't have FDI\n"))
5456 with_fdi = false;
f31f2d55
PZ		 5457
5458 mutex_lock(&dev_priv->dpio_lock);
5459
5460 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5461 tmp &= ~SBI_SSCCTL_DISABLE;
5462 tmp |= SBI_SSCCTL_PATHALT;
5463 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5464
5465 udelay(24);
5466
2fa86a1f
PZ		 5467 if (with_spread) {
5468 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5469 tmp &= ~SBI_SSCCTL_PATHALT;
5470 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 5471
2fa86a1f
PZ		 5472 if (with_fdi) {
5473 lpt_reset_fdi_mphy(dev_priv);
5474 lpt_program_fdi_mphy(dev_priv);
5475 }
5476 }
dde86e2d 5477
2fa86a1f
PZ		 5478 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5479 SBI_GEN0 : SBI_DBUFF0;
5480 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5481 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5482 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
DV		 5483
5484 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5485}
5486
47701c3b
PZ		 5487/* Sequence to disable CLKOUT_DP */
5488static void lpt_disable_clkout_dp(struct drm_device *dev)
5489{
5490 struct drm_i915_private *dev_priv = dev->dev_private;
5491 uint32_t reg, tmp;
5492
5493 mutex_lock(&dev_priv->dpio_lock);
5494
5495 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5496 SBI_GEN0 : SBI_DBUFF0;
5497 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5498 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5499 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5500
5501 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5502 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5503 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5504 tmp |= SBI_SSCCTL_PATHALT;
5505 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5506 udelay(32);
5507 }
5508 tmp |= SBI_SSCCTL_DISABLE;
5509 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5510 }
5511
5512 mutex_unlock(&dev_priv->dpio_lock);
5513}
5514
bf8fa3d3
PZ		 5515static void lpt_init_pch_refclk(struct drm_device *dev)
5516{
5517 struct drm_mode_config *mode_config = &dev->mode_config;
5518 struct intel_encoder *encoder;
5519 bool has_vga = false;
5520
5521 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5522 switch (encoder->type) {
5523 case INTEL_OUTPUT_ANALOG:
5524 has_vga = true;
5525 break;
5526 }
5527 }
5528
47701c3b
PZ		 5529 if (has_vga)
5530 lpt_enable_clkout_dp(dev, true, true);
5531 else
5532 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 5533}
5534
dde86e2d
PZ		 5535/*
5536 * Initialize reference clocks when the driver loads
5537 */
5538void intel_init_pch_refclk(struct drm_device *dev)
5539{
5540 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5541 ironlake_init_pch_refclk(dev);
5542 else if (HAS_PCH_LPT(dev))
5543 lpt_init_pch_refclk(dev);
5544}
5545
d9d444cb
JB		 5546static int ironlake_get_refclk(struct drm_crtc *crtc)
5547{
5548 struct drm_device *dev = crtc->dev;
5549 struct drm_i915_private *dev_priv = dev->dev_private;
5550 struct intel_encoder *encoder;
d9d444cb
JB		 5551 int num_connectors = 0;
5552 bool is_lvds = false;
5553
6c2b7c12 5554 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5555 switch (encoder->type) {
5556 case INTEL_OUTPUT_LVDS:
5557 is_lvds = true;
5558 break;
d9d444cb
JB		 5559 }
5560 num_connectors++;
5561 }
5562
5563 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5564 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5565 dev_priv->vbt.lvds_ssc_freq);
5566 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5567 }
5568
5569 return 120000;
5570}
5571
6ff93609 5572static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5573{
c8203565 5574 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5575 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5576 int pipe = intel_crtc->pipe;
c8203565
PZ		 5577 uint32_t val;
5578
78114071 5579 val = 0;
c8203565 5580
965e0c48 5581 switch (intel_crtc->config.pipe_bpp) {
c8203565 5582 case 18:
dfd07d72 5583 val |= PIPECONF_6BPC;
c8203565
PZ		 5584 break;
5585 case 24:
dfd07d72 5586 val |= PIPECONF_8BPC;
c8203565
PZ		 5587 break;
5588 case 30:
dfd07d72 5589 val |= PIPECONF_10BPC;
c8203565
PZ		 5590 break;
5591 case 36:
dfd07d72 5592 val |= PIPECONF_12BPC;
c8203565
PZ		 5593 break;
5594 default:
cc769b62
PZ		 5595 /* Case prevented by intel_choose_pipe_bpp_dither. */
5596 BUG();
c8203565
PZ		 5597 }
5598
d8b32247 5599 if (intel_crtc->config.dither)
c8203565
PZ		 5600 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5601
6ff93609 5602 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5603 val |= PIPECONF_INTERLACED_ILK;
5604 else
5605 val |= PIPECONF_PROGRESSIVE;
5606
50f3b016 5607 if (intel_crtc->config.limited_color_range)
3685a8f3 5608 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 5609
c8203565
PZ		 5610 I915_WRITE(PIPECONF(pipe), val);
5611 POSTING_READ(PIPECONF(pipe));
5612}
5613
86d3efce
VS		 5614/*
5615 * Set up the pipe CSC unit.
5616 *
5617 * Currently only full range RGB to limited range RGB conversion
5618 * is supported, but eventually this should handle various
5619 * RGB<->YCbCr scenarios as well.
5620 */
50f3b016 5621static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5622{
5623 struct drm_device *dev = crtc->dev;
5624 struct drm_i915_private *dev_priv = dev->dev_private;
5625 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5626 int pipe = intel_crtc->pipe;
5627 uint16_t coeff = 0x7800; /* 1.0 */
5628
5629 /*
5630 * TODO: Check what kind of values actually come out of the pipe
5631 * with these coeff/postoff values and adjust to get the best
5632 * accuracy. Perhaps we even need to take the bpc value into
5633 * consideration.
5634 */
5635
50f3b016 5636 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5637 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5638
5639 /*
5640 * GY/GU and RY/RU should be the other way around according
5641 * to BSpec, but reality doesn't agree. Just set them up in
5642 * a way that results in the correct picture.
5643 */
5644 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5645 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5646
5647 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5648 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5649
5650 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5651 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5652
5653 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5654 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5655 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5656
5657 if (INTEL_INFO(dev)->gen > 6) {
5658 uint16_t postoff = 0;
5659
50f3b016 5660 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5661 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5662
5663 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5664 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5665 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5666
5667 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5668 } else {
5669 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5670
50f3b016 5671 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5672 mode |= CSC_BLACK_SCREEN_OFFSET;
5673
5674 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5675 }
5676}
5677
6ff93609 5678static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5679{
5680 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5681 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5682 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5683 uint32_t val;
5684
3eff4faa 5685 val = 0;
ee2b0b38 5686
d8b32247 5687 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5688 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5689
6ff93609 5690 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5691 val |= PIPECONF_INTERLACED_ILK;
5692 else
5693 val |= PIPECONF_PROGRESSIVE;
5694
702e7a56
PZ		 5695 I915_WRITE(PIPECONF(cpu_transcoder), val);
5696 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 5697
5698 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5699 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
ee2b0b38
PZ		 5700}
5701
6591c6e4 5702static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ		 5703 intel_clock_t *clock,
5704 bool *has_reduced_clock,
5705 intel_clock_t *reduced_clock)
5706{
5707 struct drm_device *dev = crtc->dev;
5708 struct drm_i915_private *dev_priv = dev->dev_private;
5709 struct intel_encoder *intel_encoder;
5710 int refclk;
d4906093 5711 const intel_limit_t *limit;
a16af721 5712 bool ret, is_lvds = false;
79e53945 5713
6591c6e4
PZ		 5714 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5715 switch (intel_encoder->type) {
79e53945
JB		 5716 case INTEL_OUTPUT_LVDS:
5717 is_lvds = true;
5718 break;
79e53945
JB		 5719 }
5720 }
5721
d9d444cb 5722 refclk = ironlake_get_refclk(crtc);
79e53945 5723
d4906093
ML		 5724 /*
5725 * Returns a set of divisors for the desired target clock with the given
5726 * refclk, or FALSE. The returned values represent the clock equation:
5727 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5728 */
1b894b59 5729 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 5730 ret = dev_priv->display.find_dpll(limit, crtc,
5731 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 5732 refclk, NULL, clock);
6591c6e4
PZ		 5733 if (!ret)
5734 return false;
cda4b7d3 5735
ddc9003c 5736 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5737 /*
5738 * Ensure we match the reduced clock's P to the target clock.
5739 * If the clocks don't match, we can't switch the display clock
5740 * by using the FP0/FP1. In such case we will disable the LVDS
5741 * downclock feature.
5742 */
ee9300bb
DV		 5743 *has_reduced_clock =
5744 dev_priv->display.find_dpll(limit, crtc,
5745 dev_priv->lvds_downclock,
5746 refclk, clock,
5747 reduced_clock);
652c393a 5748 }
61e9653f 5749
6591c6e4
PZ		 5750 return true;
5751}
5752
01a415fd
DV		 5753static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5754{
5755 struct drm_i915_private *dev_priv = dev->dev_private;
5756 uint32_t temp;
5757
5758 temp = I915_READ(SOUTH_CHICKEN1);
5759 if (temp & FDI_BC_BIFURCATION_SELECT)
5760 return;
5761
5762 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5763 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5764
5765 temp |= FDI_BC_BIFURCATION_SELECT;
5766 DRM_DEBUG_KMS("enabling fdi C rx\n");
5767 I915_WRITE(SOUTH_CHICKEN1, temp);
5768 POSTING_READ(SOUTH_CHICKEN1);
5769}
5770
ebfd86fd 5771static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
01a415fd
DV		 5772{
5773 struct drm_device *dev = intel_crtc->base.dev;
5774 struct drm_i915_private *dev_priv = dev->dev_private;
01a415fd
DV		 5775
5776 switch (intel_crtc->pipe) {
5777 case PIPE_A:
ebfd86fd 5778 break;
01a415fd 5779 case PIPE_B:
ebfd86fd 5780 if (intel_crtc->config.fdi_lanes > 2)
01a415fd
DV		 5781 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5782 else
5783 cpt_enable_fdi_bc_bifurcation(dev);
5784
ebfd86fd 5785 break;
01a415fd 5786 case PIPE_C:
01a415fd
DV		 5787 cpt_enable_fdi_bc_bifurcation(dev);
5788
ebfd86fd 5789 break;
01a415fd
DV		 5790 default:
5791 BUG();
5792 }
5793}
5794
d4b1931c
PZ		 5795int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5796{
5797 /*
5798 * Account for spread spectrum to avoid
5799 * oversubscribing the link. Max center spread
5800 * is 2.5%; use 5% for safety's sake.
5801 */
5802 u32 bps = target_clock * bpp * 21 / 20;
5803 return bps / (link_bw * 8) + 1;
5804}
5805
7429e9d4 5806static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 5807{
7429e9d4 5808 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 5809}
5810
de13a2e3 5811static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5812 u32 *fp,
9a7c7890 5813 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5814{
de13a2e3 5815 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5816 struct drm_device *dev = crtc->dev;
5817 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5818 struct intel_encoder *intel_encoder;
5819 uint32_t dpll;
6cc5f341 5820 int factor, num_connectors = 0;
09ede541 5821 bool is_lvds = false, is_sdvo = false;
79e53945 5822
de13a2e3
PZ		 5823 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5824 switch (intel_encoder->type) {
79e53945
JB		 5825 case INTEL_OUTPUT_LVDS:
5826 is_lvds = true;
5827 break;
5828 case INTEL_OUTPUT_SDVO:
7d57382e 5829 case INTEL_OUTPUT_HDMI:
79e53945 5830 is_sdvo = true;
79e53945 5831 break;
79e53945 5832 }
43565a06 5833
c751ce4f 5834 num_connectors++;
79e53945 5835 }
79e53945 5836
c1858123 5837 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5838 factor = 21;
5839 if (is_lvds) {
5840 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5841 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5842 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5843 factor = 25;
09ede541 5844 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5845 factor = 20;
c1858123 5846
7429e9d4 5847 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5848 *fp |= FP_CB_TUNE;
2c07245f 5849
9a7c7890
DV		 5850 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5851 *fp2 |= FP_CB_TUNE;
5852
5eddb70b 5853 dpll = 0;
2c07245f 5854
a07d6787
EA		 5855 if (is_lvds)
5856 dpll |= DPLLB_MODE_LVDS;
5857 else
5858 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 5859
ef1b460d
DV		 5860 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5861 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 5862
5863 if (is_sdvo)
4a33e48d 5864 dpll |= DPLL_SDVO_HIGH_SPEED;
9566e9af 5865 if (intel_crtc->config.has_dp_encoder)
4a33e48d 5866 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 5867
a07d6787 5868 /* compute bitmask from p1 value */
7429e9d4 5869 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5870 /* also FPA1 */
7429e9d4 5871 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5872
7429e9d4 5873 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5874 case 5:
5875 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5876 break;
5877 case 7:
5878 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5879 break;
5880 case 10:
5881 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5882 break;
5883 case 14:
5884 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5885 break;
79e53945
JB		 5886 }
5887
b4c09f3b 5888 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5889 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5890 else
5891 dpll |= PLL_REF_INPUT_DREFCLK;
5892
959e16d6 5893 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 5894}
5895
5896static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5897 int x, int y,
5898 struct drm_framebuffer *fb)
5899{
5900 struct drm_device *dev = crtc->dev;
5901 struct drm_i915_private *dev_priv = dev->dev_private;
5902 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5903 int pipe = intel_crtc->pipe;
5904 int plane = intel_crtc->plane;
5905 int num_connectors = 0;
5906 intel_clock_t clock, reduced_clock;
cbbab5bd 5907 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5908 bool ok, has_reduced_clock = false;
8b47047b 5909 bool is_lvds = false;
de13a2e3 5910 struct intel_encoder *encoder;
e2b78267 5911 struct intel_shared_dpll *pll;
de13a2e3 5912 int ret;
de13a2e3
PZ		 5913
5914 for_each_encoder_on_crtc(dev, crtc, encoder) {
5915 switch (encoder->type) {
5916 case INTEL_OUTPUT_LVDS:
5917 is_lvds = true;
5918 break;
de13a2e3
PZ		 5919 }
5920
5921 num_connectors++;
a07d6787 5922 }
79e53945 5923
5dc5298b
PZ		 5924 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5925 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5926
ff9a6750 5927 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 5928 &has_reduced_clock, &reduced_clock);
ee9300bb 5929 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 5930 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5931 return -EINVAL;
79e53945 5932 }
f47709a9
DV		 5933 /* Compat-code for transition, will disappear. */
5934 if (!intel_crtc->config.clock_set) {
5935 intel_crtc->config.dpll.n = clock.n;
5936 intel_crtc->config.dpll.m1 = clock.m1;
5937 intel_crtc->config.dpll.m2 = clock.m2;
5938 intel_crtc->config.dpll.p1 = clock.p1;
5939 intel_crtc->config.dpll.p2 = clock.p2;
5940 }
79e53945 5941
5dc5298b 5942 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5943 if (intel_crtc->config.has_pch_encoder) {
7429e9d4 5944 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5945 if (has_reduced_clock)
7429e9d4 5946 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5947
7429e9d4 5948 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5949 &fp, &reduced_clock,
5950 has_reduced_clock ? &fp2 : NULL);
5951
959e16d6 5952 intel_crtc->config.dpll_hw_state.dpll = dpll;
66e985c0
DV		 5953 intel_crtc->config.dpll_hw_state.fp0 = fp;
5954 if (has_reduced_clock)
5955 intel_crtc->config.dpll_hw_state.fp1 = fp2;
5956 else
5957 intel_crtc->config.dpll_hw_state.fp1 = fp;
5958
b89a1d39 5959 pll = intel_get_shared_dpll(intel_crtc);
ee7b9f93 5960 if (pll == NULL) {
84f44ce7
VS		 5961 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5962 pipe_name(pipe));
4b645f14
JB		 5963 return -EINVAL;
5964 }
ee7b9f93 5965 } else
e72f9fbf 5966 intel_put_shared_dpll(intel_crtc);
79e53945 5967
03afc4a2
DV		 5968 if (intel_crtc->config.has_dp_encoder)
5969 intel_dp_set_m_n(intel_crtc);
79e53945 5970
bcd644e0
DV		 5971 if (is_lvds && has_reduced_clock && i915_powersave)
5972 intel_crtc->lowfreq_avail = true;
5973 else
5974 intel_crtc->lowfreq_avail = false;
e2b78267
DV		 5975
5976 if (intel_crtc->config.has_pch_encoder) {
5977 pll = intel_crtc_to_shared_dpll(intel_crtc);
5978
652c393a
JB		 5979 }
5980
8a654f3b 5981 intel_set_pipe_timings(intel_crtc);
5eddb70b 5982
ca3a0ff8 5983 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5984 intel_cpu_transcoder_set_m_n(intel_crtc,
5985 &intel_crtc->config.fdi_m_n);
5986 }
2c07245f 5987
ebfd86fd
DV		 5988 if (IS_IVYBRIDGE(dev))
5989 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
79e53945 5990
6ff93609 5991 ironlake_set_pipeconf(crtc);
79e53945 5992
a1f9e77e
PZ		 5993 /* Set up the display plane register */
5994 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5995 POSTING_READ(DSPCNTR(plane));
79e53945 5996
94352cf9 5997 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd 5998
1857e1da 5999 return ret;
79e53945
JB		 6000}
6001
eb14cb74
VS		 6002static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6003 struct intel_link_m_n *m_n)
6004{
6005 struct drm_device *dev = crtc->base.dev;
6006 struct drm_i915_private *dev_priv = dev->dev_private;
6007 enum pipe pipe = crtc->pipe;
6008
6009 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6010 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6011 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6012 & ~TU_SIZE_MASK;
6013 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6014 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6015 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6016}
6017
6018static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6019 enum transcoder transcoder,
6020 struct intel_link_m_n *m_n)
72419203
DV		 6021{
6022 struct drm_device *dev = crtc->base.dev;
6023 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 6024 enum pipe pipe = crtc->pipe;
72419203 6025
eb14cb74
VS		 6026 if (INTEL_INFO(dev)->gen >= 5) {
6027 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6028 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6029 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6030 & ~TU_SIZE_MASK;
6031 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6032 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6033 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6034 } else {
6035 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6036 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6037 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6038 & ~TU_SIZE_MASK;
6039 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6040 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6041 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6042 }
6043}
6044
6045void intel_dp_get_m_n(struct intel_crtc *crtc,
6046 struct intel_crtc_config *pipe_config)
6047{
6048 if (crtc->config.has_pch_encoder)
6049 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6050 else
6051 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6052 &pipe_config->dp_m_n);
6053}
72419203 6054
eb14cb74
VS		 6055static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6056 struct intel_crtc_config *pipe_config)
6057{
6058 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6059 &pipe_config->fdi_m_n);
72419203
DV		 6060}
6061
2fa2fe9a
DV		 6062static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6063 struct intel_crtc_config *pipe_config)
6064{
6065 struct drm_device *dev = crtc->base.dev;
6066 struct drm_i915_private *dev_priv = dev->dev_private;
6067 uint32_t tmp;
6068
6069 tmp = I915_READ(PF_CTL(crtc->pipe));
6070
6071 if (tmp & PF_ENABLE) {
fd4daa9c 6072 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 6073 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6074 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 6075
6076 /* We currently do not free assignements of panel fitters on
6077 * ivb/hsw (since we don't use the higher upscaling modes which
6078 * differentiates them) so just WARN about this case for now. */
6079 if (IS_GEN7(dev)) {
6080 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6081 PF_PIPE_SEL_IVB(crtc->pipe));
6082 }
2fa2fe9a 6083 }
79e53945
JB		 6084}
6085
0e8ffe1b
DV		 6086static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6087 struct intel_crtc_config *pipe_config)
6088{
6089 struct drm_device *dev = crtc->base.dev;
6090 struct drm_i915_private *dev_priv = dev->dev_private;
6091 uint32_t tmp;
6092
e143a21c 6093 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 6094 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 6095
0e8ffe1b
DV		 6096 tmp = I915_READ(PIPECONF(crtc->pipe));
6097 if (!(tmp & PIPECONF_ENABLE))
6098 return false;
6099
42571aef
VS		 6100 switch (tmp & PIPECONF_BPC_MASK) {
6101 case PIPECONF_6BPC:
6102 pipe_config->pipe_bpp = 18;
6103 break;
6104 case PIPECONF_8BPC:
6105 pipe_config->pipe_bpp = 24;
6106 break;
6107 case PIPECONF_10BPC:
6108 pipe_config->pipe_bpp = 30;
6109 break;
6110 case PIPECONF_12BPC:
6111 pipe_config->pipe_bpp = 36;
6112 break;
6113 default:
6114 break;
6115 }
6116
ab9412ba 6117 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 6118 struct intel_shared_dpll *pll;
6119
88adfff1
DV		 6120 pipe_config->has_pch_encoder = true;
6121
627eb5a3
DV		 6122 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6123 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6124 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6125
6126 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 6127
c0d43d62 6128 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 6129 pipe_config->shared_dpll =
6130 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 6131 } else {
6132 tmp = I915_READ(PCH_DPLL_SEL);
6133 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6134 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6135 else
6136 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6137 }
66e985c0
DV		 6138
6139 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6140
6141 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6142 &pipe_config->dpll_hw_state));
c93f54cf
DV		 6143
6144 tmp = pipe_config->dpll_hw_state.dpll;
6145 pipe_config->pixel_multiplier =
6146 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6147 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 6148
6149 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 6150 } else {
6151 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 6152 }
6153
1bd1bd80
DV		 6154 intel_get_pipe_timings(crtc, pipe_config);
6155
2fa2fe9a
DV		 6156 ironlake_get_pfit_config(crtc, pipe_config);
6157
0e8ffe1b
DV		 6158 return true;
6159}
6160
be256dc7
PZ		 6161static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6162{
6163 struct drm_device *dev = dev_priv->dev;
6164 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6165 struct intel_crtc *crtc;
6166 unsigned long irqflags;
bd633a7c 6167 uint32_t val;
be256dc7
PZ		 6168
6169 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6170 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
6171 pipe_name(crtc->pipe));
6172
6173 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6174 WARN(plls->spll_refcount, "SPLL enabled\n");
6175 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6176 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6177 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6178 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6179 "CPU PWM1 enabled\n");
6180 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6181 "CPU PWM2 enabled\n");
6182 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6183 "PCH PWM1 enabled\n");
6184 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6185 "Utility pin enabled\n");
6186 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6187
6188 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6189 val = I915_READ(DEIMR);
6190 WARN((val & ~DE_PCH_EVENT_IVB) != val,
6191 "Unexpected DEIMR bits enabled: 0x%x\n", val);
6192 val = I915_READ(SDEIMR);
bd633a7c 6193 WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
be256dc7
PZ		 6194 "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6195 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6196}
6197
6198/*
6199 * This function implements pieces of two sequences from BSpec:
6200 * - Sequence for display software to disable LCPLL
6201 * - Sequence for display software to allow package C8+
6202 * The steps implemented here are just the steps that actually touch the LCPLL
6203 * register. Callers should take care of disabling all the display engine
6204 * functions, doing the mode unset, fixing interrupts, etc.
6205 */
6ff58d53
PZ		 6206static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6207 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 6208{
6209 uint32_t val;
6210
6211 assert_can_disable_lcpll(dev_priv);
6212
6213 val = I915_READ(LCPLL_CTL);
6214
6215 if (switch_to_fclk) {
6216 val |= LCPLL_CD_SOURCE_FCLK;
6217 I915_WRITE(LCPLL_CTL, val);
6218
6219 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6220 LCPLL_CD_SOURCE_FCLK_DONE, 1))
6221 DRM_ERROR("Switching to FCLK failed\n");
6222
6223 val = I915_READ(LCPLL_CTL);
6224 }
6225
6226 val |= LCPLL_PLL_DISABLE;
6227 I915_WRITE(LCPLL_CTL, val);
6228 POSTING_READ(LCPLL_CTL);
6229
6230 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6231 DRM_ERROR("LCPLL still locked\n");
6232
6233 val = I915_READ(D_COMP);
6234 val |= D_COMP_COMP_DISABLE;
515b2392
PZ		 6235 mutex_lock(&dev_priv->rps.hw_lock);
6236 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6237 DRM_ERROR("Failed to disable D_COMP\n");
6238 mutex_unlock(&dev_priv->rps.hw_lock);
be256dc7
PZ		 6239 POSTING_READ(D_COMP);
6240 ndelay(100);
6241
6242 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6243 DRM_ERROR("D_COMP RCOMP still in progress\n");
6244
6245 if (allow_power_down) {
6246 val = I915_READ(LCPLL_CTL);
6247 val |= LCPLL_POWER_DOWN_ALLOW;
6248 I915_WRITE(LCPLL_CTL, val);
6249 POSTING_READ(LCPLL_CTL);
6250 }
6251}
6252
6253/*
6254 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6255 * source.
6256 */
6ff58d53 6257static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 6258{
6259 uint32_t val;
6260
6261 val = I915_READ(LCPLL_CTL);
6262
6263 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6264 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6265 return;
6266
215733fa
PZ		 6267 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6268 * we'll hang the machine! */
6269 dev_priv->uncore.funcs.force_wake_get(dev_priv);
6270
be256dc7
PZ		 6271 if (val & LCPLL_POWER_DOWN_ALLOW) {
6272 val &= ~LCPLL_POWER_DOWN_ALLOW;
6273 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 6274 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 6275 }
6276
6277 val = I915_READ(D_COMP);
6278 val |= D_COMP_COMP_FORCE;
6279 val &= ~D_COMP_COMP_DISABLE;
515b2392
PZ		 6280 mutex_lock(&dev_priv->rps.hw_lock);
6281 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6282 DRM_ERROR("Failed to enable D_COMP\n");
6283 mutex_unlock(&dev_priv->rps.hw_lock);
35d8f2eb 6284 POSTING_READ(D_COMP);
be256dc7
PZ		 6285
6286 val = I915_READ(LCPLL_CTL);
6287 val &= ~LCPLL_PLL_DISABLE;
6288 I915_WRITE(LCPLL_CTL, val);
6289
6290 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6291 DRM_ERROR("LCPLL not locked yet\n");
6292
6293 if (val & LCPLL_CD_SOURCE_FCLK) {
6294 val = I915_READ(LCPLL_CTL);
6295 val &= ~LCPLL_CD_SOURCE_FCLK;
6296 I915_WRITE(LCPLL_CTL, val);
6297
6298 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6299 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6300 DRM_ERROR("Switching back to LCPLL failed\n");
6301 }
215733fa
PZ		 6302
6303 dev_priv->uncore.funcs.force_wake_put(dev_priv);
be256dc7
PZ		 6304}
6305
c67a470b
PZ		 6306void hsw_enable_pc8_work(struct work_struct *__work)
6307{
6308 struct drm_i915_private *dev_priv =
6309 container_of(to_delayed_work(__work), struct drm_i915_private,
6310 pc8.enable_work);
6311 struct drm_device *dev = dev_priv->dev;
6312 uint32_t val;
6313
6314 if (dev_priv->pc8.enabled)
6315 return;
6316
6317 DRM_DEBUG_KMS("Enabling package C8+\n");
6318
6319 dev_priv->pc8.enabled = true;
6320
6321 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6322 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6323 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6324 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6325 }
6326
6327 lpt_disable_clkout_dp(dev);
6328 hsw_pc8_disable_interrupts(dev);
6329 hsw_disable_lcpll(dev_priv, true, true);
6330}
6331
6332static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6333{
6334 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6335 WARN(dev_priv->pc8.disable_count < 1,
6336 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6337
6338 dev_priv->pc8.disable_count--;
6339 if (dev_priv->pc8.disable_count != 0)
6340 return;
6341
6342 schedule_delayed_work(&dev_priv->pc8.enable_work,
90058745 6343 msecs_to_jiffies(i915_pc8_timeout));
c67a470b
PZ		 6344}
6345
6346static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6347{
6348 struct drm_device *dev = dev_priv->dev;
6349 uint32_t val;
6350
6351 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6352 WARN(dev_priv->pc8.disable_count < 0,
6353 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6354
6355 dev_priv->pc8.disable_count++;
6356 if (dev_priv->pc8.disable_count != 1)
6357 return;
6358
6359 cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6360 if (!dev_priv->pc8.enabled)
6361 return;
6362
6363 DRM_DEBUG_KMS("Disabling package C8+\n");
6364
6365 hsw_restore_lcpll(dev_priv);
6366 hsw_pc8_restore_interrupts(dev);
6367 lpt_init_pch_refclk(dev);
6368
6369 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6370 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6371 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6372 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6373 }
6374
6375 intel_prepare_ddi(dev);
6376 i915_gem_init_swizzling(dev);
6377 mutex_lock(&dev_priv->rps.hw_lock);
6378 gen6_update_ring_freq(dev);
6379 mutex_unlock(&dev_priv->rps.hw_lock);
6380 dev_priv->pc8.enabled = false;
6381}
6382
6383void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6384{
6385 mutex_lock(&dev_priv->pc8.lock);
6386 __hsw_enable_package_c8(dev_priv);
6387 mutex_unlock(&dev_priv->pc8.lock);
6388}
6389
6390void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6391{
6392 mutex_lock(&dev_priv->pc8.lock);
6393 __hsw_disable_package_c8(dev_priv);
6394 mutex_unlock(&dev_priv->pc8.lock);
6395}
6396
6397static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6398{
6399 struct drm_device *dev = dev_priv->dev;
6400 struct intel_crtc *crtc;
6401 uint32_t val;
6402
6403 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6404 if (crtc->base.enabled)
6405 return false;
6406
6407 /* This case is still possible since we have the i915.disable_power_well
6408 * parameter and also the KVMr or something else might be requesting the
6409 * power well. */
6410 val = I915_READ(HSW_PWR_WELL_DRIVER);
6411 if (val != 0) {
6412 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6413 return false;
6414 }
6415
6416 return true;
6417}
6418
6419/* Since we're called from modeset_global_resources there's no way to
6420 * symmetrically increase and decrease the refcount, so we use
6421 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6422 * or not.
6423 */
6424static void hsw_update_package_c8(struct drm_device *dev)
6425{
6426 struct drm_i915_private *dev_priv = dev->dev_private;
6427 bool allow;
6428
6429 if (!i915_enable_pc8)
6430 return;
6431
6432 mutex_lock(&dev_priv->pc8.lock);
6433
6434 allow = hsw_can_enable_package_c8(dev_priv);
6435
6436 if (allow == dev_priv->pc8.requirements_met)
6437 goto done;
6438
6439 dev_priv->pc8.requirements_met = allow;
6440
6441 if (allow)
6442 __hsw_enable_package_c8(dev_priv);
6443 else
6444 __hsw_disable_package_c8(dev_priv);
6445
6446done:
6447 mutex_unlock(&dev_priv->pc8.lock);
6448}
6449
6450static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6451{
6452 if (!dev_priv->pc8.gpu_idle) {
6453 dev_priv->pc8.gpu_idle = true;
6454 hsw_enable_package_c8(dev_priv);
6455 }
6456}
6457
6458static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6459{
6460 if (dev_priv->pc8.gpu_idle) {
6461 dev_priv->pc8.gpu_idle = false;
6462 hsw_disable_package_c8(dev_priv);
6463 }
be256dc7
PZ		 6464}
6465
d6dd9eb1
DV		 6466static void haswell_modeset_global_resources(struct drm_device *dev)
6467{
d6dd9eb1
DV		 6468 bool enable = false;
6469 struct intel_crtc *crtc;
d6dd9eb1
DV		 6470
6471 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 6472 if (!crtc->base.enabled)
6473 continue;
d6dd9eb1 6474
fd4daa9c 6475 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.enabled ||
e7a639c4 6476 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 6477 enable = true;
6478 }
6479
d6dd9eb1 6480 intel_set_power_well(dev, enable);
c67a470b
PZ		 6481
6482 hsw_update_package_c8(dev);
d6dd9eb1
DV		 6483}
6484
09b4ddf9 6485static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 6486 int x, int y,
6487 struct drm_framebuffer *fb)
6488{
6489 struct drm_device *dev = crtc->dev;
6490 struct drm_i915_private *dev_priv = dev->dev_private;
6491 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 6492 int plane = intel_crtc->plane;
09b4ddf9 6493 int ret;
09b4ddf9 6494
ff9a6750 6495 if (!intel_ddi_pll_mode_set(crtc))
6441ab5f
PZ		 6496 return -EINVAL;
6497
03afc4a2
DV		 6498 if (intel_crtc->config.has_dp_encoder)
6499 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 6500
6501 intel_crtc->lowfreq_avail = false;
09b4ddf9 6502
8a654f3b 6503 intel_set_pipe_timings(intel_crtc);
09b4ddf9 6504
ca3a0ff8 6505 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 6506 intel_cpu_transcoder_set_m_n(intel_crtc,
6507 &intel_crtc->config.fdi_m_n);
6508 }
09b4ddf9 6509
6ff93609 6510 haswell_set_pipeconf(crtc);
09b4ddf9 6511
50f3b016 6512 intel_set_pipe_csc(crtc);
86d3efce 6513
09b4ddf9 6514 /* Set up the display plane register */
86d3efce 6515 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 6516 POSTING_READ(DSPCNTR(plane));
6517
6518 ret = intel_pipe_set_base(crtc, x, y, fb);
6519
1f803ee5 6520 return ret;
79e53945
JB		 6521}
6522
0e8ffe1b
DV		 6523static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6524 struct intel_crtc_config *pipe_config)
6525{
6526 struct drm_device *dev = crtc->base.dev;
6527 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 6528 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 6529 uint32_t tmp;
6530
e143a21c 6531 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 6532 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6533
eccb140b
DV		 6534 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6535 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6536 enum pipe trans_edp_pipe;
6537 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6538 default:
6539 WARN(1, "unknown pipe linked to edp transcoder\n");
6540 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6541 case TRANS_DDI_EDP_INPUT_A_ON:
6542 trans_edp_pipe = PIPE_A;
6543 break;
6544 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6545 trans_edp_pipe = PIPE_B;
6546 break;
6547 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6548 trans_edp_pipe = PIPE_C;
6549 break;
6550 }
6551
6552 if (trans_edp_pipe == crtc->pipe)
6553 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6554 }
6555
b97186f0 6556 if (!intel_display_power_enabled(dev,
eccb140b 6557 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 6558 return false;
6559
eccb140b 6560 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 6561 if (!(tmp & PIPECONF_ENABLE))
6562 return false;
6563
88adfff1 6564 /*
f196e6be 6565 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 6566 * DDI E. So just check whether this pipe is wired to DDI E and whether
6567 * the PCH transcoder is on.
6568 */
eccb140b 6569 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 6570 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 6571 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 6572 pipe_config->has_pch_encoder = true;
6573
627eb5a3
DV		 6574 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6575 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6576 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6577
6578 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 6579 }
6580
1bd1bd80
DV		 6581 intel_get_pipe_timings(crtc, pipe_config);
6582
2fa2fe9a
DV		 6583 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6584 if (intel_display_power_enabled(dev, pfit_domain))
6585 ironlake_get_pfit_config(crtc, pipe_config);
88adfff1 6586
42db64ef
PZ		 6587 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6588 (I915_READ(IPS_CTL) & IPS_ENABLE);
6589
6c49f241
DV		 6590 pipe_config->pixel_multiplier = 1;
6591
0e8ffe1b
DV		 6592 return true;
6593}
6594
f564048e 6595static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6596 int x, int y,
94352cf9 6597 struct drm_framebuffer *fb)
f564048e
EA		 6598{
6599 struct drm_device *dev = crtc->dev;
6600 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19 6601 struct intel_encoder *encoder;
0b701d27 6602 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 6603 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6604 int pipe = intel_crtc->pipe;
f564048e
EA		 6605 int ret;
6606
0b701d27 6607 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6608
b8cecdf5
DV		 6609 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6610
79e53945 6611 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6612
9256aa19
DV		 6613 if (ret != 0)
6614 return ret;
6615
6616 for_each_encoder_on_crtc(dev, crtc, encoder) {
6617 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6618 encoder->base.base.id,
6619 drm_get_encoder_name(&encoder->base),
6620 mode->base.id, mode->name);
36f2d1f1 6621 encoder->mode_set(encoder);
9256aa19
DV		 6622 }
6623
6624 return 0;
79e53945
JB		 6625}
6626
3a9627f4
WF		 6627static bool intel_eld_uptodate(struct drm_connector *connector,
6628 int reg_eldv, uint32_t bits_eldv,
6629 int reg_elda, uint32_t bits_elda,
6630 int reg_edid)
6631{
6632 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6633 uint8_t *eld = connector->eld;
6634 uint32_t i;
6635
6636 i = I915_READ(reg_eldv);
6637 i &= bits_eldv;
6638
6639 if (!eld[0])
6640 return !i;
6641
6642 if (!i)
6643 return false;
6644
6645 i = I915_READ(reg_elda);
6646 i &= ~bits_elda;
6647 I915_WRITE(reg_elda, i);
6648
6649 for (i = 0; i < eld[2]; i++)
6650 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6651 return false;
6652
6653 return true;
6654}
6655
e0dac65e
WF		 6656static void g4x_write_eld(struct drm_connector *connector,
6657 struct drm_crtc *crtc)
6658{
6659 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6660 uint8_t *eld = connector->eld;
6661 uint32_t eldv;
6662 uint32_t len;
6663 uint32_t i;
6664
6665 i = I915_READ(G4X_AUD_VID_DID);
6666
6667 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6668 eldv = G4X_ELDV_DEVCL_DEVBLC;
6669 else
6670 eldv = G4X_ELDV_DEVCTG;
6671
3a9627f4
WF		 6672 if (intel_eld_uptodate(connector,
6673 G4X_AUD_CNTL_ST, eldv,
6674 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6675 G4X_HDMIW_HDMIEDID))
6676 return;
6677
e0dac65e
WF		 6678 i = I915_READ(G4X_AUD_CNTL_ST);
6679 i &= ~(eldv | G4X_ELD_ADDR);
6680 len = (i >> 9) & 0x1f; /* ELD buffer size */
6681 I915_WRITE(G4X_AUD_CNTL_ST, i);
6682
6683 if (!eld[0])
6684 return;
6685
6686 len = min_t(uint8_t, eld[2], len);
6687 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6688 for (i = 0; i < len; i++)
6689 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6690
6691 i = I915_READ(G4X_AUD_CNTL_ST);
6692 i |= eldv;
6693 I915_WRITE(G4X_AUD_CNTL_ST, i);
6694}
6695
83358c85
WX		 6696static void haswell_write_eld(struct drm_connector *connector,
6697 struct drm_crtc *crtc)
6698{
6699 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6700 uint8_t *eld = connector->eld;
6701 struct drm_device *dev = crtc->dev;
7b9f35a6 6702 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6703 uint32_t eldv;
6704 uint32_t i;
6705 int len;
6706 int pipe = to_intel_crtc(crtc)->pipe;
6707 int tmp;
6708
6709 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6710 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6711 int aud_config = HSW_AUD_CFG(pipe);
6712 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6713
6714
6715 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6716
6717 /* Audio output enable */
6718 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6719 tmp = I915_READ(aud_cntrl_st2);
6720 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6721 I915_WRITE(aud_cntrl_st2, tmp);
6722
6723 /* Wait for 1 vertical blank */
6724 intel_wait_for_vblank(dev, pipe);
6725
6726 /* Set ELD valid state */
6727 tmp = I915_READ(aud_cntrl_st2);
7e7cb34f 6728 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
83358c85
WX		 6729 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6730 I915_WRITE(aud_cntrl_st2, tmp);
6731 tmp = I915_READ(aud_cntrl_st2);
7e7cb34f 6732 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
83358c85
WX		 6733
6734 /* Enable HDMI mode */
6735 tmp = I915_READ(aud_config);
7e7cb34f 6736 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
83358c85
WX		 6737 /* clear N_programing_enable and N_value_index */
6738 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6739 I915_WRITE(aud_config, tmp);
6740
6741 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6742
6743 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6744 intel_crtc->eld_vld = true;
83358c85
WX		 6745
6746 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6747 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6748 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6749 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6750 } else
6751 I915_WRITE(aud_config, 0);
6752
6753 if (intel_eld_uptodate(connector,
6754 aud_cntrl_st2, eldv,
6755 aud_cntl_st, IBX_ELD_ADDRESS,
6756 hdmiw_hdmiedid))
6757 return;
6758
6759 i = I915_READ(aud_cntrl_st2);
6760 i &= ~eldv;
6761 I915_WRITE(aud_cntrl_st2, i);
6762
6763 if (!eld[0])
6764 return;
6765
6766 i = I915_READ(aud_cntl_st);
6767 i &= ~IBX_ELD_ADDRESS;
6768 I915_WRITE(aud_cntl_st, i);
6769 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6770 DRM_DEBUG_DRIVER("port num:%d\n", i);
6771
6772 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6773 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6774 for (i = 0; i < len; i++)
6775 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6776
6777 i = I915_READ(aud_cntrl_st2);
6778 i |= eldv;
6779 I915_WRITE(aud_cntrl_st2, i);
6780
6781}
6782
e0dac65e
WF		 6783static void ironlake_write_eld(struct drm_connector *connector,
6784 struct drm_crtc *crtc)
6785{
6786 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6787 uint8_t *eld = connector->eld;
6788 uint32_t eldv;
6789 uint32_t i;
6790 int len;
6791 int hdmiw_hdmiedid;
b6daa025 6792 int aud_config;
e0dac65e
WF		 6793 int aud_cntl_st;
6794 int aud_cntrl_st2;
9b138a83 6795 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6796
b3f33cbf 6797 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6798 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6799 aud_config = IBX_AUD_CFG(pipe);
6800 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6801 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6802 } else {
9b138a83
WX		 6803 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6804 aud_config = CPT_AUD_CFG(pipe);
6805 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6806 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6807 }
6808
9b138a83 6809 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6810
6811 i = I915_READ(aud_cntl_st);
9b138a83 6812 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6813 if (!i) {
6814 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6815 /* operate blindly on all ports */
1202b4c6
WF		 6816 eldv = IBX_ELD_VALIDB;
6817 eldv |= IBX_ELD_VALIDB << 4;
6818 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6819 } else {
2582a850 6820 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6821 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6822 }
6823
3a9627f4
WF		 6824 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6825 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6826 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6827 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6828 } else
6829 I915_WRITE(aud_config, 0);
e0dac65e 6830
3a9627f4
WF		 6831 if (intel_eld_uptodate(connector,
6832 aud_cntrl_st2, eldv,
6833 aud_cntl_st, IBX_ELD_ADDRESS,
6834 hdmiw_hdmiedid))
6835 return;
6836
e0dac65e
WF		 6837 i = I915_READ(aud_cntrl_st2);
6838 i &= ~eldv;
6839 I915_WRITE(aud_cntrl_st2, i);
6840
6841 if (!eld[0])
6842 return;
6843
e0dac65e 6844 i = I915_READ(aud_cntl_st);
1202b4c6 6845 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6846 I915_WRITE(aud_cntl_st, i);
6847
6848 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6849 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6850 for (i = 0; i < len; i++)
6851 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6852
6853 i = I915_READ(aud_cntrl_st2);
6854 i |= eldv;
6855 I915_WRITE(aud_cntrl_st2, i);
6856}
6857
6858void intel_write_eld(struct drm_encoder *encoder,
6859 struct drm_display_mode *mode)
6860{
6861 struct drm_crtc *crtc = encoder->crtc;
6862 struct drm_connector *connector;
6863 struct drm_device *dev = encoder->dev;
6864 struct drm_i915_private *dev_priv = dev->dev_private;
6865
6866 connector = drm_select_eld(encoder, mode);
6867 if (!connector)
6868 return;
6869
6870 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6871 connector->base.id,
6872 drm_get_connector_name(connector),
6873 connector->encoder->base.id,
6874 drm_get_encoder_name(connector->encoder));
6875
6876 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6877
6878 if (dev_priv->display.write_eld)
6879 dev_priv->display.write_eld(connector, crtc);
6880}
6881
560b85bb
CW		 6882static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6883{
6884 struct drm_device *dev = crtc->dev;
6885 struct drm_i915_private *dev_priv = dev->dev_private;
6886 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6887 bool visible = base != 0;
6888 u32 cntl;
6889
6890 if (intel_crtc->cursor_visible == visible)
6891 return;
6892
9db4a9c7 6893 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6894 if (visible) {
6895 /* On these chipsets we can only modify the base whilst
6896 * the cursor is disabled.
6897 */
9db4a9c7 6898 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6899
6900 cntl &= ~(CURSOR_FORMAT_MASK);
6901 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6902 cntl |= CURSOR_ENABLE |
6903 CURSOR_GAMMA_ENABLE |
6904 CURSOR_FORMAT_ARGB;
6905 } else
6906 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6907 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6908
6909 intel_crtc->cursor_visible = visible;
6910}
6911
6912static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6913{
6914 struct drm_device *dev = crtc->dev;
6915 struct drm_i915_private *dev_priv = dev->dev_private;
6916 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6917 int pipe = intel_crtc->pipe;
6918 bool visible = base != 0;
6919
6920 if (intel_crtc->cursor_visible != visible) {
548f245b 6921 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6922 if (base) {
6923 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6924 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6925 cntl |= pipe << 28; /* Connect to correct pipe */
6926 } else {
6927 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6928 cntl |= CURSOR_MODE_DISABLE;
6929 }
9db4a9c7 6930 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6931
6932 intel_crtc->cursor_visible = visible;
6933 }
6934 /* and commit changes on next vblank */
9db4a9c7 6935 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6936}
6937
65a21cd6
JB		 6938static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6939{
6940 struct drm_device *dev = crtc->dev;
6941 struct drm_i915_private *dev_priv = dev->dev_private;
6942 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6943 int pipe = intel_crtc->pipe;
6944 bool visible = base != 0;
6945
6946 if (intel_crtc->cursor_visible != visible) {
6947 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6948 if (base) {
6949 cntl &= ~CURSOR_MODE;
6950 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6951 } else {
6952 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6953 cntl |= CURSOR_MODE_DISABLE;
6954 }
1f5d76db 6955 if (IS_HASWELL(dev)) {
86d3efce 6956 cntl |= CURSOR_PIPE_CSC_ENABLE;
1f5d76db
PZ		 6957 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
6958 }
65a21cd6
JB		 6959 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6960
6961 intel_crtc->cursor_visible = visible;
6962 }
6963 /* and commit changes on next vblank */
6964 I915_WRITE(CURBASE_IVB(pipe), base);
6965}
6966
cda4b7d3 6967/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6968static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6969 bool on)
cda4b7d3
CW		 6970{
6971 struct drm_device *dev = crtc->dev;
6972 struct drm_i915_private *dev_priv = dev->dev_private;
6973 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6974 int pipe = intel_crtc->pipe;
6975 int x = intel_crtc->cursor_x;
6976 int y = intel_crtc->cursor_y;
d6e4db15 6977 u32 base = 0, pos = 0;
cda4b7d3
CW		 6978 bool visible;
6979
d6e4db15 6980 if (on)
cda4b7d3 6981 base = intel_crtc->cursor_addr;
cda4b7d3 6982
d6e4db15
VS		 6983 if (x >= intel_crtc->config.pipe_src_w)
6984 base = 0;
6985
6986 if (y >= intel_crtc->config.pipe_src_h)
cda4b7d3
CW		 6987 base = 0;
6988
6989 if (x < 0) {
efc9064e 6990 if (x + intel_crtc->cursor_width <= 0)
cda4b7d3
CW		 6991 base = 0;
6992
6993 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6994 x = -x;
6995 }
6996 pos |= x << CURSOR_X_SHIFT;
6997
6998 if (y < 0) {
efc9064e 6999 if (y + intel_crtc->cursor_height <= 0)
cda4b7d3
CW		 7000 base = 0;
7001
7002 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7003 y = -y;
7004 }
7005 pos |= y << CURSOR_Y_SHIFT;
7006
7007 visible = base != 0;
560b85bb 7008 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 7009 return;
7010
0cd83aa9 7011 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 7012 I915_WRITE(CURPOS_IVB(pipe), pos);
7013 ivb_update_cursor(crtc, base);
7014 } else {
7015 I915_WRITE(CURPOS(pipe), pos);
7016 if (IS_845G(dev) || IS_I865G(dev))
7017 i845_update_cursor(crtc, base);
7018 else
7019 i9xx_update_cursor(crtc, base);
7020 }
cda4b7d3
CW		 7021}
7022
79e53945 7023static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 7024 struct drm_file *file,
79e53945
JB		 7025 uint32_t handle,
7026 uint32_t width, uint32_t height)
7027{
7028 struct drm_device *dev = crtc->dev;
7029 struct drm_i915_private *dev_priv = dev->dev_private;
7030 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 7031 struct drm_i915_gem_object *obj;
cda4b7d3 7032 uint32_t addr;
3f8bc370 7033 int ret;
79e53945 7034
79e53945
JB		 7035 /* if we want to turn off the cursor ignore width and height */
7036 if (!handle) {
28c97730 7037 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 7038 addr = 0;
05394f39 7039 obj = NULL;
5004417d 7040 mutex_lock(&dev->struct_mutex);
3f8bc370 7041 goto finish;
79e53945
JB		 7042 }
7043
7044 /* Currently we only support 64x64 cursors */
7045 if (width != 64 || height != 64) {
7046 DRM_ERROR("we currently only support 64x64 cursors\n");
7047 return -EINVAL;
7048 }
7049
05394f39 7050 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 7051 if (&obj->base == NULL)
79e53945
JB		 7052 return -ENOENT;
7053
05394f39 7054 if (obj->base.size < width * height * 4) {
79e53945 7055 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 7056 ret = -ENOMEM;
7057 goto fail;
79e53945
JB		 7058 }
7059
71acb5eb 7060 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 7061 mutex_lock(&dev->struct_mutex);
b295d1b6 7062 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 7063 unsigned alignment;
7064
d9e86c0e
CW		 7065 if (obj->tiling_mode) {
7066 DRM_ERROR("cursor cannot be tiled\n");
7067 ret = -EINVAL;
7068 goto fail_locked;
7069 }
7070
693db184
CW		 7071 /* Note that the w/a also requires 2 PTE of padding following
7072 * the bo. We currently fill all unused PTE with the shadow
7073 * page and so we should always have valid PTE following the
7074 * cursor preventing the VT-d warning.
7075 */
7076 alignment = 0;
7077 if (need_vtd_wa(dev))
7078 alignment = 64*1024;
7079
7080 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 7081 if (ret) {
7082 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 7083 goto fail_locked;
e7b526bb
CW		 7084 }
7085
d9e86c0e
CW		 7086 ret = i915_gem_object_put_fence(obj);
7087 if (ret) {
2da3b9b9 7088 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 7089 goto fail_unpin;
7090 }
7091
f343c5f6 7092 addr = i915_gem_obj_ggtt_offset(obj);
71acb5eb 7093 } else {
6eeefaf3 7094 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 7095 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 7096 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7097 align);
71acb5eb
DA		 7098 if (ret) {
7099 DRM_ERROR("failed to attach phys object\n");
7f9872e0 7100 goto fail_locked;
71acb5eb 7101 }
05394f39 7102 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 7103 }
7104
a6c45cf0 7105 if (IS_GEN2(dev))
14b60391
JB		 7106 I915_WRITE(CURSIZE, (height << 12) | width);
7107
3f8bc370 7108 finish:
3f8bc370 7109 if (intel_crtc->cursor_bo) {
b295d1b6 7110 if (dev_priv->info->cursor_needs_physical) {
05394f39 7111 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 7112 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7113 } else
cc98b413 7114 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
05394f39 7115 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 7116 }
80824003 7117
7f9872e0 7118 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 7119
7120 intel_crtc->cursor_addr = addr;
05394f39 7121 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 7122 intel_crtc->cursor_width = width;
7123 intel_crtc->cursor_height = height;
7124
f2f5f771
VS		 7125 if (intel_crtc->active)
7126 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 7127
79e53945 7128 return 0;
e7b526bb 7129fail_unpin:
cc98b413 7130 i915_gem_object_unpin_from_display_plane(obj);
7f9872e0 7131fail_locked:
34b8686e 7132 mutex_unlock(&dev->struct_mutex);
bc9025bd 7133fail:
05394f39 7134 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 7135 return ret;
79e53945
JB		 7136}
7137
7138static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7139{
79e53945 7140 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7141
cda4b7d3
CW		 7142 intel_crtc->cursor_x = x;
7143 intel_crtc->cursor_y = y;
652c393a 7144
f2f5f771
VS		 7145 if (intel_crtc->active)
7146 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 7147
7148 return 0;
b8c00ac5
DA		 7149}
7150
79e53945 7151static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 7152 u16 *blue, uint32_t start, uint32_t size)
79e53945 7153{
7203425a 7154 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 7155 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7156
7203425a 7157 for (i = start; i < end; i++) {
79e53945
JB		 7158 intel_crtc->lut_r[i] = red[i] >> 8;
7159 intel_crtc->lut_g[i] = green[i] >> 8;
7160 intel_crtc->lut_b[i] = blue[i] >> 8;
7161 }
7162
7163 intel_crtc_load_lut(crtc);
7164}
7165
79e53945
JB		 7166/* VESA 640x480x72Hz mode to set on the pipe */
7167static struct drm_display_mode load_detect_mode = {
7168 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7169 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7170};
7171
d2dff872
CW		 7172static struct drm_framebuffer *
7173intel_framebuffer_create(struct drm_device *dev,
308e5bcb 7174 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 7175 struct drm_i915_gem_object *obj)
7176{
7177 struct intel_framebuffer *intel_fb;
7178 int ret;
7179
7180 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7181 if (!intel_fb) {
7182 drm_gem_object_unreference_unlocked(&obj->base);
7183 return ERR_PTR(-ENOMEM);
7184 }
7185
7186 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7187 if (ret) {
7188 drm_gem_object_unreference_unlocked(&obj->base);
7189 kfree(intel_fb);
7190 return ERR_PTR(ret);
7191 }
7192
7193 return &intel_fb->base;
7194}
7195
7196static u32
7197intel_framebuffer_pitch_for_width(int width, int bpp)
7198{
7199 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7200 return ALIGN(pitch, 64);
7201}
7202
7203static u32
7204intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7205{
7206 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7207 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7208}
7209
7210static struct drm_framebuffer *
7211intel_framebuffer_create_for_mode(struct drm_device *dev,
7212 struct drm_display_mode *mode,
7213 int depth, int bpp)
7214{
7215 struct drm_i915_gem_object *obj;
0fed39bd 7216 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 7217
7218 obj = i915_gem_alloc_object(dev,
7219 intel_framebuffer_size_for_mode(mode, bpp));
7220 if (obj == NULL)
7221 return ERR_PTR(-ENOMEM);
7222
7223 mode_cmd.width = mode->hdisplay;
7224 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 7225 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7226 bpp);
5ca0c34a 7227 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 7228
7229 return intel_framebuffer_create(dev, &mode_cmd, obj);
7230}
7231
7232static struct drm_framebuffer *
7233mode_fits_in_fbdev(struct drm_device *dev,
7234 struct drm_display_mode *mode)
7235{
7236 struct drm_i915_private *dev_priv = dev->dev_private;
7237 struct drm_i915_gem_object *obj;
7238 struct drm_framebuffer *fb;
7239
7240 if (dev_priv->fbdev == NULL)
7241 return NULL;
7242
7243 obj = dev_priv->fbdev->ifb.obj;
7244 if (obj == NULL)
7245 return NULL;
7246
7247 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 7248 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7249 fb->bits_per_pixel))
d2dff872
CW		 7250 return NULL;
7251
01f2c773 7252 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 7253 return NULL;
7254
7255 return fb;
7256}
7257
d2434ab7 7258bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 7259 struct drm_display_mode *mode,
8261b191 7260 struct intel_load_detect_pipe *old)
79e53945
JB		 7261{
7262 struct intel_crtc *intel_crtc;
d2434ab7
DV		 7263 struct intel_encoder *intel_encoder =
7264 intel_attached_encoder(connector);
79e53945 7265 struct drm_crtc *possible_crtc;
4ef69c7a 7266 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 7267 struct drm_crtc *crtc = NULL;
7268 struct drm_device *dev = encoder->dev;
94352cf9 7269 struct drm_framebuffer *fb;
79e53945
JB		 7270 int i = -1;
7271
d2dff872
CW		 7272 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7273 connector->base.id, drm_get_connector_name(connector),
7274 encoder->base.id, drm_get_encoder_name(encoder));
7275
79e53945
JB		 7276 /*
7277 * Algorithm gets a little messy:
7a5e4805 7278 *
79e53945
JB		 7279 * - if the connector already has an assigned crtc, use it (but make
7280 * sure it's on first)
7a5e4805 7281 *
79e53945
JB		 7282 * - try to find the first unused crtc that can drive this connector,
7283 * and use that if we find one
79e53945
JB		 7284 */
7285
7286 /* See if we already have a CRTC for this connector */
7287 if (encoder->crtc) {
7288 crtc = encoder->crtc;
8261b191 7289
7b24056b
DV		 7290 mutex_lock(&crtc->mutex);
7291
24218aac 7292 old->dpms_mode = connector->dpms;
8261b191
CW		 7293 old->load_detect_temp = false;
7294
7295 /* Make sure the crtc and connector are running */
24218aac
DV		 7296 if (connector->dpms != DRM_MODE_DPMS_ON)
7297 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 7298
7173188d 7299 return true;
79e53945
JB		 7300 }
7301
7302 /* Find an unused one (if possible) */
7303 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7304 i++;
7305 if (!(encoder->possible_crtcs & (1 << i)))
7306 continue;
7307 if (!possible_crtc->enabled) {
7308 crtc = possible_crtc;
7309 break;
7310 }
79e53945
JB		 7311 }
7312
7313 /*
7314 * If we didn't find an unused CRTC, don't use any.
7315 */
7316 if (!crtc) {
7173188d
CW		 7317 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7318 return false;
79e53945
JB		 7319 }
7320
7b24056b 7321 mutex_lock(&crtc->mutex);
fc303101
DV		 7322 intel_encoder->new_crtc = to_intel_crtc(crtc);
7323 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 7324
7325 intel_crtc = to_intel_crtc(crtc);
24218aac 7326 old->dpms_mode = connector->dpms;
8261b191 7327 old->load_detect_temp = true;
d2dff872 7328 old->release_fb = NULL;
79e53945 7329
6492711d
CW		 7330 if (!mode)
7331 mode = &load_detect_mode;
79e53945 7332
d2dff872
CW		 7333 /* We need a framebuffer large enough to accommodate all accesses
7334 * that the plane may generate whilst we perform load detection.
7335 * We can not rely on the fbcon either being present (we get called
7336 * during its initialisation to detect all boot displays, or it may
7337 * not even exist) or that it is large enough to satisfy the
7338 * requested mode.
7339 */
94352cf9
DV		 7340 fb = mode_fits_in_fbdev(dev, mode);
7341 if (fb == NULL) {
d2dff872 7342 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 7343 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7344 old->release_fb = fb;
d2dff872
CW		 7345 } else
7346 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 7347 if (IS_ERR(fb)) {
d2dff872 7348 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 7349 mutex_unlock(&crtc->mutex);
0e8b3d3e 7350 return false;
79e53945 7351 }
79e53945 7352
c0c36b94 7353 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 7354 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 7355 if (old->release_fb)
7356 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 7357 mutex_unlock(&crtc->mutex);
0e8b3d3e 7358 return false;
79e53945 7359 }
7173188d 7360
79e53945 7361 /* let the connector get through one full cycle before testing */
9d0498a2 7362 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 7363 return true;
79e53945
JB		 7364}
7365
d2434ab7 7366void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 7367 struct intel_load_detect_pipe *old)
79e53945 7368{
d2434ab7
DV		 7369 struct intel_encoder *intel_encoder =
7370 intel_attached_encoder(connector);
4ef69c7a 7371 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 7372 struct drm_crtc *crtc = encoder->crtc;
79e53945 7373
d2dff872
CW		 7374 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7375 connector->base.id, drm_get_connector_name(connector),
7376 encoder->base.id, drm_get_encoder_name(encoder));
7377
8261b191 7378 if (old->load_detect_temp) {
fc303101
DV		 7379 to_intel_connector(connector)->new_encoder = NULL;
7380 intel_encoder->new_crtc = NULL;
7381 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 7382
36206361
DV		 7383 if (old->release_fb) {
7384 drm_framebuffer_unregister_private(old->release_fb);
7385 drm_framebuffer_unreference(old->release_fb);
7386 }
d2dff872 7387
67c96400 7388 mutex_unlock(&crtc->mutex);
0622a53c 7389 return;
79e53945
JB		 7390 }
7391
c751ce4f 7392 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 7393 if (old->dpms_mode != DRM_MODE_DPMS_ON)
7394 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 7395
7396 mutex_unlock(&crtc->mutex);
79e53945
JB		 7397}
7398
da4a1efa
VS		 7399static int i9xx_pll_refclk(struct drm_device *dev,
7400 const struct intel_crtc_config *pipe_config)
7401{
7402 struct drm_i915_private *dev_priv = dev->dev_private;
7403 u32 dpll = pipe_config->dpll_hw_state.dpll;
7404
7405 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7406 return dev_priv->vbt.lvds_ssc_freq * 1000;
7407 else if (HAS_PCH_SPLIT(dev))
7408 return 120000;
7409 else if (!IS_GEN2(dev))
7410 return 96000;
7411 else
7412 return 48000;
7413}
7414
79e53945 7415/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc
JB		 7416static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7417 struct intel_crtc_config *pipe_config)
79e53945 7418{
f1f644dc 7419 struct drm_device *dev = crtc->base.dev;
79e53945 7420 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 7421 int pipe = pipe_config->cpu_transcoder;
293623f7 7422 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 7423 u32 fp;
7424 intel_clock_t clock;
da4a1efa 7425 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 7426
7427 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 7428 fp = pipe_config->dpll_hw_state.fp0;
79e53945 7429 else
293623f7 7430 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 7431
7432 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 7433 if (IS_PINEVIEW(dev)) {
7434 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7435 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 7436 } else {
7437 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7438 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7439 }
7440
a6c45cf0 7441 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 7442 if (IS_PINEVIEW(dev))
7443 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7444 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 7445 else
7446 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 7447 DPLL_FPA01_P1_POST_DIV_SHIFT);
7448
7449 switch (dpll & DPLL_MODE_MASK) {
7450 case DPLLB_MODE_DAC_SERIAL:
7451 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7452 5 : 10;
7453 break;
7454 case DPLLB_MODE_LVDS:
7455 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7456 7 : 14;
7457 break;
7458 default:
28c97730 7459 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 7460 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 7461 return;
79e53945
JB		 7462 }
7463
ac58c3f0 7464 if (IS_PINEVIEW(dev))
da4a1efa 7465 pineview_clock(refclk, &clock);
ac58c3f0 7466 else
da4a1efa 7467 i9xx_clock(refclk, &clock);
79e53945
JB		 7468 } else {
7469 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7470
7471 if (is_lvds) {
7472 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7473 DPLL_FPA01_P1_POST_DIV_SHIFT);
7474 clock.p2 = 14;
79e53945
JB		 7475 } else {
7476 if (dpll & PLL_P1_DIVIDE_BY_TWO)
7477 clock.p1 = 2;
7478 else {
7479 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7480 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7481 }
7482 if (dpll & PLL_P2_DIVIDE_BY_4)
7483 clock.p2 = 4;
7484 else
7485 clock.p2 = 2;
79e53945 7486 }
da4a1efa
VS		 7487
7488 i9xx_clock(refclk, &clock);
79e53945
JB		 7489 }
7490
18442d08
VS		 7491 /*
7492 * This value includes pixel_multiplier. We will use
241bfc38 7493 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 7494 * encoder's get_config() function.
7495 */
7496 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 7497}
7498
6878da05
VS		 7499int intel_dotclock_calculate(int link_freq,
7500 const struct intel_link_m_n *m_n)
f1f644dc 7501{
f1f644dc
JB		 7502 /*
7503 * The calculation for the data clock is:
1041a02f 7504 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 7505 * But we want to avoid losing precison if possible, so:
1041a02f 7506 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 7507 *
7508 * and the link clock is simpler:
1041a02f 7509 * link_clock = (m * link_clock) / n
f1f644dc
JB		 7510 */
7511
6878da05
VS		 7512 if (!m_n->link_n)
7513 return 0;
f1f644dc 7514
6878da05
VS		 7515 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
7516}
f1f644dc 7517
18442d08
VS		 7518static void ironlake_pch_clock_get(struct intel_crtc *crtc,
7519 struct intel_crtc_config *pipe_config)
6878da05
VS		 7520{
7521 struct drm_device *dev = crtc->base.dev;
79e53945 7522
18442d08
VS		 7523 /* read out port_clock from the DPLL */
7524 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 7525
f1f644dc 7526 /*
18442d08 7527 * This value does not include pixel_multiplier.
241bfc38 7528 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 7529 * agree once we know their relationship in the encoder's
7530 * get_config() function.
79e53945 7531 */
241bfc38 7532 pipe_config->adjusted_mode.crtc_clock =
18442d08
VS		 7533 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
7534 &pipe_config->fdi_m_n);
79e53945
JB		 7535}
7536
7537/** Returns the currently programmed mode of the given pipe. */
7538struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7539 struct drm_crtc *crtc)
7540{
548f245b 7541 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 7542 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 7543 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 7544 struct drm_display_mode *mode;
f1f644dc 7545 struct intel_crtc_config pipe_config;
fe2b8f9d
PZ		 7546 int htot = I915_READ(HTOTAL(cpu_transcoder));
7547 int hsync = I915_READ(HSYNC(cpu_transcoder));
7548 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7549 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 7550 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 7551
7552 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7553 if (!mode)
7554 return NULL;
7555
f1f644dc
JB		 7556 /*
7557 * Construct a pipe_config sufficient for getting the clock info
7558 * back out of crtc_clock_get.
7559 *
7560 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7561 * to use a real value here instead.
7562 */
293623f7 7563 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 7564 pipe_config.pixel_multiplier = 1;
293623f7
VS		 7565 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
7566 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
7567 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 7568 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7569
773ae034 7570 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 7571 mode->hdisplay = (htot & 0xffff) + 1;
7572 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7573 mode->hsync_start = (hsync & 0xffff) + 1;
7574 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7575 mode->vdisplay = (vtot & 0xffff) + 1;
7576 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7577 mode->vsync_start = (vsync & 0xffff) + 1;
7578 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7579
7580 drm_mode_set_name(mode);
79e53945
JB		 7581
7582 return mode;
7583}
7584
3dec0095 7585static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7586{
7587 struct drm_device *dev = crtc->dev;
7588 drm_i915_private_t *dev_priv = dev->dev_private;
7589 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7590 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7591 int dpll_reg = DPLL(pipe);
7592 int dpll;
652c393a 7593
bad720ff 7594 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7595 return;
7596
7597 if (!dev_priv->lvds_downclock_avail)
7598 return;
7599
dbdc6479 7600 dpll = I915_READ(dpll_reg);
652c393a 7601 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7602 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7603
8ac5a6d5 7604 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7605
7606 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7607 I915_WRITE(dpll_reg, dpll);
9d0498a2 7608 intel_wait_for_vblank(dev, pipe);
dbdc6479 7609
652c393a
JB		 7610 dpll = I915_READ(dpll_reg);
7611 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7612 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7613 }
652c393a
JB		 7614}
7615
7616static void intel_decrease_pllclock(struct drm_crtc *crtc)
7617{
7618 struct drm_device *dev = crtc->dev;
7619 drm_i915_private_t *dev_priv = dev->dev_private;
7620 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7621
bad720ff 7622 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7623 return;
7624
7625 if (!dev_priv->lvds_downclock_avail)
7626 return;
7627
7628 /*
7629 * Since this is called by a timer, we should never get here in
7630 * the manual case.
7631 */
7632 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7633 int pipe = intel_crtc->pipe;
7634 int dpll_reg = DPLL(pipe);
7635 int dpll;
f6e5b160 7636
44d98a61 7637 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7638
8ac5a6d5 7639 assert_panel_unlocked(dev_priv, pipe);
652c393a 7640
dc257cf1 7641 dpll = I915_READ(dpll_reg);
652c393a
JB		 7642 dpll |= DISPLAY_RATE_SELECT_FPA1;
7643 I915_WRITE(dpll_reg, dpll);
9d0498a2 7644 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7645 dpll = I915_READ(dpll_reg);
7646 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7647 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7648 }
7649
7650}
7651
f047e395
CW		 7652void intel_mark_busy(struct drm_device *dev)
7653{
c67a470b
PZ		 7654 struct drm_i915_private *dev_priv = dev->dev_private;
7655
7656 hsw_package_c8_gpu_busy(dev_priv);
7657 i915_update_gfx_val(dev_priv);
f047e395
CW		 7658}
7659
7660void intel_mark_idle(struct drm_device *dev)
652c393a 7661{
c67a470b 7662 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 7663 struct drm_crtc *crtc;
652c393a 7664
c67a470b
PZ		 7665 hsw_package_c8_gpu_idle(dev_priv);
7666
652c393a
JB		 7667 if (!i915_powersave)
7668 return;
7669
652c393a 7670 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7671 if (!crtc->fb)
7672 continue;
7673
725a5b54 7674 intel_decrease_pllclock(crtc);
652c393a 7675 }
652c393a
JB		 7676}
7677
c65355bb
CW		 7678void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7679 struct intel_ring_buffer *ring)
652c393a 7680{
f047e395
CW		 7681 struct drm_device *dev = obj->base.dev;
7682 struct drm_crtc *crtc;
652c393a 7683
f047e395 7684 if (!i915_powersave)
acb87dfb
CW		 7685 return;
7686
652c393a
JB		 7687 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7688 if (!crtc->fb)
7689 continue;
7690
c65355bb
CW		 7691 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7692 continue;
7693
7694 intel_increase_pllclock(crtc);
7695 if (ring && intel_fbc_enabled(dev))
7696 ring->fbc_dirty = true;
652c393a
JB		 7697 }
7698}
7699
79e53945
JB		 7700static void intel_crtc_destroy(struct drm_crtc *crtc)
7701{
7702 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7703 struct drm_device *dev = crtc->dev;
7704 struct intel_unpin_work *work;
7705 unsigned long flags;
7706
7707 spin_lock_irqsave(&dev->event_lock, flags);
7708 work = intel_crtc->unpin_work;
7709 intel_crtc->unpin_work = NULL;
7710 spin_unlock_irqrestore(&dev->event_lock, flags);
7711
7712 if (work) {
7713 cancel_work_sync(&work->work);
7714 kfree(work);
7715 }
79e53945 7716
40ccc72b
MK		 7717 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7718
79e53945 7719 drm_crtc_cleanup(crtc);
67e77c5a 7720
79e53945
JB		 7721 kfree(intel_crtc);
7722}
7723
6b95a207
KH		 7724static void intel_unpin_work_fn(struct work_struct *__work)
7725{
7726 struct intel_unpin_work *work =
7727 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7728 struct drm_device *dev = work->crtc->dev;
6b95a207 7729
b4a98e57 7730 mutex_lock(&dev->struct_mutex);
1690e1eb 7731 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7732 drm_gem_object_unreference(&work->pending_flip_obj->base);
7733 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7734
b4a98e57
CW		 7735 intel_update_fbc(dev);
7736 mutex_unlock(&dev->struct_mutex);
7737
7738 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7739 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7740
6b95a207
KH		 7741 kfree(work);
7742}
7743
1afe3e9d 7744static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7745 struct drm_crtc *crtc)
6b95a207
KH		 7746{
7747 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7748 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7749 struct intel_unpin_work *work;
6b95a207
KH		 7750 unsigned long flags;
7751
7752 /* Ignore early vblank irqs */
7753 if (intel_crtc == NULL)
7754 return;
7755
7756 spin_lock_irqsave(&dev->event_lock, flags);
7757 work = intel_crtc->unpin_work;
e7d841ca
CW		 7758
7759 /* Ensure we don't miss a work->pending update ... */
7760 smp_rmb();
7761
7762 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7763 spin_unlock_irqrestore(&dev->event_lock, flags);
7764 return;
7765 }
7766
e7d841ca
CW		 7767 /* and that the unpin work is consistent wrt ->pending. */
7768 smp_rmb();
7769
6b95a207 7770 intel_crtc->unpin_work = NULL;
6b95a207 7771
45a066eb
RC		 7772 if (work->event)
7773 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7774
0af7e4df
MK		 7775 drm_vblank_put(dev, intel_crtc->pipe);
7776
6b95a207
KH		 7777 spin_unlock_irqrestore(&dev->event_lock, flags);
7778
2c10d571 7779 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7780
7781 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7782
7783 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7784}
7785
1afe3e9d
JB		 7786void intel_finish_page_flip(struct drm_device *dev, int pipe)
7787{
7788 drm_i915_private_t *dev_priv = dev->dev_private;
7789 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7790
49b14a5c 7791 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7792}
7793
7794void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7795{
7796 drm_i915_private_t *dev_priv = dev->dev_private;
7797 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7798
49b14a5c 7799 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7800}
7801
6b95a207
KH		 7802void intel_prepare_page_flip(struct drm_device *dev, int plane)
7803{
7804 drm_i915_private_t *dev_priv = dev->dev_private;
7805 struct intel_crtc *intel_crtc =
7806 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7807 unsigned long flags;
7808
e7d841ca
CW		 7809 /* NB: An MMIO update of the plane base pointer will also
7810 * generate a page-flip completion irq, i.e. every modeset
7811 * is also accompanied by a spurious intel_prepare_page_flip().
7812 */
6b95a207 7813 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7814 if (intel_crtc->unpin_work)
7815 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7816 spin_unlock_irqrestore(&dev->event_lock, flags);
7817}
7818
e7d841ca
CW		 7819inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7820{
7821 /* Ensure that the work item is consistent when activating it ... */
7822 smp_wmb();
7823 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7824 /* and that it is marked active as soon as the irq could fire. */
7825 smp_wmb();
7826}
7827
8c9f3aaf
JB		 7828static int intel_gen2_queue_flip(struct drm_device *dev,
7829 struct drm_crtc *crtc,
7830 struct drm_framebuffer *fb,
ed8d1975
KP		 7831 struct drm_i915_gem_object *obj,
7832 uint32_t flags)
8c9f3aaf
JB		 7833{
7834 struct drm_i915_private *dev_priv = dev->dev_private;
7835 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7836 u32 flip_mask;
6d90c952 7837 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7838 int ret;
7839
6d90c952 7840 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7841 if (ret)
83d4092b 7842 goto err;
8c9f3aaf 7843
6d90c952 7844 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7845 if (ret)
83d4092b 7846 goto err_unpin;
8c9f3aaf
JB		 7847
7848 /* Can't queue multiple flips, so wait for the previous
7849 * one to finish before executing the next.
7850 */
7851 if (intel_crtc->plane)
7852 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7853 else
7854 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7855 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7856 intel_ring_emit(ring, MI_NOOP);
7857 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7858 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7859 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7860 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952 7861 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7862
7863 intel_mark_page_flip_active(intel_crtc);
09246732 7864 __intel_ring_advance(ring);
83d4092b
CW		 7865 return 0;
7866
7867err_unpin:
7868 intel_unpin_fb_obj(obj);
7869err:
8c9f3aaf
JB		 7870 return ret;
7871}
7872
7873static int intel_gen3_queue_flip(struct drm_device *dev,
7874 struct drm_crtc *crtc,
7875 struct drm_framebuffer *fb,
ed8d1975
KP		 7876 struct drm_i915_gem_object *obj,
7877 uint32_t flags)
8c9f3aaf
JB		 7878{
7879 struct drm_i915_private *dev_priv = dev->dev_private;
7880 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7881 u32 flip_mask;
6d90c952 7882 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7883 int ret;
7884
6d90c952 7885 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7886 if (ret)
83d4092b 7887 goto err;
8c9f3aaf 7888
6d90c952 7889 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7890 if (ret)
83d4092b 7891 goto err_unpin;
8c9f3aaf
JB		 7892
7893 if (intel_crtc->plane)
7894 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7895 else
7896 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7897 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7898 intel_ring_emit(ring, MI_NOOP);
7899 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7900 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7901 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7902 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952
DV		 7903 intel_ring_emit(ring, MI_NOOP);
7904
e7d841ca 7905 intel_mark_page_flip_active(intel_crtc);
09246732 7906 __intel_ring_advance(ring);
83d4092b
CW		 7907 return 0;
7908
7909err_unpin:
7910 intel_unpin_fb_obj(obj);
7911err:
8c9f3aaf
JB		 7912 return ret;
7913}
7914
7915static int intel_gen4_queue_flip(struct drm_device *dev,
7916 struct drm_crtc *crtc,
7917 struct drm_framebuffer *fb,
ed8d1975
KP		 7918 struct drm_i915_gem_object *obj,
7919 uint32_t flags)
8c9f3aaf
JB		 7920{
7921 struct drm_i915_private *dev_priv = dev->dev_private;
7922 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7923 uint32_t pf, pipesrc;
6d90c952 7924 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7925 int ret;
7926
6d90c952 7927 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7928 if (ret)
83d4092b 7929 goto err;
8c9f3aaf 7930
6d90c952 7931 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7932 if (ret)
83d4092b 7933 goto err_unpin;
8c9f3aaf
JB		 7934
7935 /* i965+ uses the linear or tiled offsets from the
7936 * Display Registers (which do not change across a page-flip)
7937 * so we need only reprogram the base address.
7938 */
6d90c952
DV		 7939 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7940 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7941 intel_ring_emit(ring, fb->pitches[0]);
c2c75131 7942 intel_ring_emit(ring,
f343c5f6 7943 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
c2c75131 7944 obj->tiling_mode);
8c9f3aaf
JB		 7945
7946 /* XXX Enabling the panel-fitter across page-flip is so far
7947 * untested on non-native modes, so ignore it for now.
7948 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7949 */
7950 pf = 0;
7951 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7952 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7953
7954 intel_mark_page_flip_active(intel_crtc);
09246732 7955 __intel_ring_advance(ring);
83d4092b
CW		 7956 return 0;
7957
7958err_unpin:
7959 intel_unpin_fb_obj(obj);
7960err:
8c9f3aaf
JB		 7961 return ret;
7962}
7963
7964static int intel_gen6_queue_flip(struct drm_device *dev,
7965 struct drm_crtc *crtc,
7966 struct drm_framebuffer *fb,
ed8d1975
KP		 7967 struct drm_i915_gem_object *obj,
7968 uint32_t flags)
8c9f3aaf
JB		 7969{
7970 struct drm_i915_private *dev_priv = dev->dev_private;
7971 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7972 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7973 uint32_t pf, pipesrc;
7974 int ret;
7975
6d90c952 7976 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7977 if (ret)
83d4092b 7978 goto err;
8c9f3aaf 7979
6d90c952 7980 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7981 if (ret)
83d4092b 7982 goto err_unpin;
8c9f3aaf 7983
6d90c952
DV		 7984 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7985 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7986 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
f343c5f6 7987 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8c9f3aaf 7988
dc257cf1
DV		 7989 /* Contrary to the suggestions in the documentation,
7990 * "Enable Panel Fitter" does not seem to be required when page
7991 * flipping with a non-native mode, and worse causes a normal
7992 * modeset to fail.
7993 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7994 */
7995 pf = 0;
8c9f3aaf 7996 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7997 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7998
7999 intel_mark_page_flip_active(intel_crtc);
09246732 8000 __intel_ring_advance(ring);
83d4092b
CW		 8001 return 0;
8002
8003err_unpin:
8004 intel_unpin_fb_obj(obj);
8005err:
8c9f3aaf
JB		 8006 return ret;
8007}
8008
7c9017e5
JB		 8009static int intel_gen7_queue_flip(struct drm_device *dev,
8010 struct drm_crtc *crtc,
8011 struct drm_framebuffer *fb,
ed8d1975
KP		 8012 struct drm_i915_gem_object *obj,
8013 uint32_t flags)
7c9017e5
JB		 8014{
8015 struct drm_i915_private *dev_priv = dev->dev_private;
8016 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ffe74d75 8017 struct intel_ring_buffer *ring;
cb05d8de 8018 uint32_t plane_bit = 0;
ffe74d75
CW		 8019 int len, ret;
8020
8021 ring = obj->ring;
1c5fd085 8022 if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
ffe74d75 8023 ring = &dev_priv->ring[BCS];
7c9017e5
JB		 8024
8025 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8026 if (ret)
83d4092b 8027 goto err;
7c9017e5 8028
cb05d8de
DV		 8029 switch(intel_crtc->plane) {
8030 case PLANE_A:
8031 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8032 break;
8033 case PLANE_B:
8034 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8035 break;
8036 case PLANE_C:
8037 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8038 break;
8039 default:
8040 WARN_ONCE(1, "unknown plane in flip command\n");
8041 ret = -ENODEV;
ab3951eb 8042 goto err_unpin;
cb05d8de
DV		 8043 }
8044
ffe74d75
CW		 8045 len = 4;
8046 if (ring->id == RCS)
8047 len += 6;
8048
8049 ret = intel_ring_begin(ring, len);
7c9017e5 8050 if (ret)
83d4092b 8051 goto err_unpin;
7c9017e5 8052
ffe74d75
CW		 8053 /* Unmask the flip-done completion message. Note that the bspec says that
8054 * we should do this for both the BCS and RCS, and that we must not unmask
8055 * more than one flip event at any time (or ensure that one flip message
8056 * can be sent by waiting for flip-done prior to queueing new flips).
8057 * Experimentation says that BCS works despite DERRMR masking all
8058 * flip-done completion events and that unmasking all planes at once
8059 * for the RCS also doesn't appear to drop events. Setting the DERRMR
8060 * to zero does lead to lockups within MI_DISPLAY_FLIP.
8061 */
8062 if (ring->id == RCS) {
8063 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8064 intel_ring_emit(ring, DERRMR);
8065 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8066 DERRMR_PIPEB_PRI_FLIP_DONE |
8067 DERRMR_PIPEC_PRI_FLIP_DONE));
8068 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
8069 intel_ring_emit(ring, DERRMR);
8070 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8071 }
8072
cb05d8de 8073 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 8074 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
f343c5f6 8075 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7c9017e5 8076 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 8077
8078 intel_mark_page_flip_active(intel_crtc);
09246732 8079 __intel_ring_advance(ring);
83d4092b
CW		 8080 return 0;
8081
8082err_unpin:
8083 intel_unpin_fb_obj(obj);
8084err:
7c9017e5
JB		 8085 return ret;
8086}
8087
8c9f3aaf
JB		 8088static int intel_default_queue_flip(struct drm_device *dev,
8089 struct drm_crtc *crtc,
8090 struct drm_framebuffer *fb,
ed8d1975
KP		 8091 struct drm_i915_gem_object *obj,
8092 uint32_t flags)
8c9f3aaf
JB		 8093{
8094 return -ENODEV;
8095}
8096
6b95a207
KH		 8097static int intel_crtc_page_flip(struct drm_crtc *crtc,
8098 struct drm_framebuffer *fb,
ed8d1975
KP		 8099 struct drm_pending_vblank_event *event,
8100 uint32_t page_flip_flags)
6b95a207
KH		 8101{
8102 struct drm_device *dev = crtc->dev;
8103 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 8104 struct drm_framebuffer *old_fb = crtc->fb;
8105 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 8106 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8107 struct intel_unpin_work *work;
8c9f3aaf 8108 unsigned long flags;
52e68630 8109 int ret;
6b95a207 8110
e6a595d2
VS		 8111 /* Can't change pixel format via MI display flips. */
8112 if (fb->pixel_format != crtc->fb->pixel_format)
8113 return -EINVAL;
8114
8115 /*
8116 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8117 * Note that pitch changes could also affect these register.
8118 */
8119 if (INTEL_INFO(dev)->gen > 3 &&
8120 (fb->offsets[0] != crtc->fb->offsets[0] ||
8121 fb->pitches[0] != crtc->fb->pitches[0]))
8122 return -EINVAL;
8123
b14c5679 8124 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 8125 if (work == NULL)
8126 return -ENOMEM;
8127
6b95a207 8128 work->event = event;
b4a98e57 8129 work->crtc = crtc;
4a35f83b 8130 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 8131 INIT_WORK(&work->work, intel_unpin_work_fn);
8132
7317c75e
JB		 8133 ret = drm_vblank_get(dev, intel_crtc->pipe);
8134 if (ret)
8135 goto free_work;
8136
6b95a207
KH		 8137 /* We borrow the event spin lock for protecting unpin_work */
8138 spin_lock_irqsave(&dev->event_lock, flags);
8139 if (intel_crtc->unpin_work) {
8140 spin_unlock_irqrestore(&dev->event_lock, flags);
8141 kfree(work);
7317c75e 8142 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 8143
8144 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 8145 return -EBUSY;
8146 }
8147 intel_crtc->unpin_work = work;
8148 spin_unlock_irqrestore(&dev->event_lock, flags);
8149
b4a98e57
CW		 8150 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8151 flush_workqueue(dev_priv->wq);
8152
79158103
CW		 8153 ret = i915_mutex_lock_interruptible(dev);
8154 if (ret)
8155 goto cleanup;
6b95a207 8156
75dfca80 8157 /* Reference the objects for the scheduled work. */
05394f39
CW		 8158 drm_gem_object_reference(&work->old_fb_obj->base);
8159 drm_gem_object_reference(&obj->base);
6b95a207
KH		 8160
8161 crtc->fb = fb;
96b099fd 8162
e1f99ce6 8163 work->pending_flip_obj = obj;
e1f99ce6 8164
4e5359cd
SF		 8165 work->enable_stall_check = true;
8166
b4a98e57 8167 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 8168 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 8169
ed8d1975 8170 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8c9f3aaf
JB		 8171 if (ret)
8172 goto cleanup_pending;
6b95a207 8173
7782de3b 8174 intel_disable_fbc(dev);
c65355bb 8175 intel_mark_fb_busy(obj, NULL);
6b95a207
KH		 8176 mutex_unlock(&dev->struct_mutex);
8177
e5510fac
JB		 8178 trace_i915_flip_request(intel_crtc->plane, obj);
8179
6b95a207 8180 return 0;
96b099fd 8181
8c9f3aaf 8182cleanup_pending:
b4a98e57 8183 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 8184 crtc->fb = old_fb;
05394f39
CW		 8185 drm_gem_object_unreference(&work->old_fb_obj->base);
8186 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 8187 mutex_unlock(&dev->struct_mutex);
8188
79158103 8189cleanup:
96b099fd
CW		 8190 spin_lock_irqsave(&dev->event_lock, flags);
8191 intel_crtc->unpin_work = NULL;
8192 spin_unlock_irqrestore(&dev->event_lock, flags);
8193
7317c75e
JB		 8194 drm_vblank_put(dev, intel_crtc->pipe);
8195free_work:
96b099fd
CW		 8196 kfree(work);
8197
8198 return ret;
6b95a207
KH		 8199}
8200
f6e5b160 8201static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 8202 .mode_set_base_atomic = intel_pipe_set_base_atomic,
8203 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 8204};
8205
50f56119
DV		 8206static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8207 struct drm_crtc *crtc)
8208{
8209 struct drm_device *dev;
8210 struct drm_crtc *tmp;
8211 int crtc_mask = 1;
47f1c6c9 8212
50f56119 8213 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 8214
50f56119 8215 dev = crtc->dev;
47f1c6c9 8216
50f56119
DV		 8217 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8218 if (tmp == crtc)
8219 break;
8220 crtc_mask <<= 1;
8221 }
47f1c6c9 8222
50f56119
DV		 8223 if (encoder->possible_crtcs & crtc_mask)
8224 return true;
8225 return false;
47f1c6c9 8226}
79e53945 8227
9a935856
DV		 8228/**
8229 * intel_modeset_update_staged_output_state
8230 *
8231 * Updates the staged output configuration state, e.g. after we've read out the
8232 * current hw state.
8233 */
8234static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 8235{
9a935856
DV		 8236 struct intel_encoder *encoder;
8237 struct intel_connector *connector;
f6e5b160 8238
9a935856
DV		 8239 list_for_each_entry(connector, &dev->mode_config.connector_list,
8240 base.head) {
8241 connector->new_encoder =
8242 to_intel_encoder(connector->base.encoder);
8243 }
f6e5b160 8244
9a935856
DV		 8245 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8246 base.head) {
8247 encoder->new_crtc =
8248 to_intel_crtc(encoder->base.crtc);
8249 }
f6e5b160
CW		 8250}
8251
9a935856
DV		 8252/**
8253 * intel_modeset_commit_output_state
8254 *
8255 * This function copies the stage display pipe configuration to the real one.
8256 */
8257static void intel_modeset_commit_output_state(struct drm_device *dev)
8258{
8259 struct intel_encoder *encoder;
8260 struct intel_connector *connector;
f6e5b160 8261
9a935856
DV		 8262 list_for_each_entry(connector, &dev->mode_config.connector_list,
8263 base.head) {
8264 connector->base.encoder = &connector->new_encoder->base;
8265 }
f6e5b160 8266
9a935856
DV		 8267 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8268 base.head) {
8269 encoder->base.crtc = &encoder->new_crtc->base;
8270 }
8271}
8272
050f7aeb
DV		 8273static void
8274connected_sink_compute_bpp(struct intel_connector * connector,
8275 struct intel_crtc_config *pipe_config)
8276{
8277 int bpp = pipe_config->pipe_bpp;
8278
8279 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8280 connector->base.base.id,
8281 drm_get_connector_name(&connector->base));
8282
8283 /* Don't use an invalid EDID bpc value */
8284 if (connector->base.display_info.bpc &&
8285 connector->base.display_info.bpc * 3 < bpp) {
8286 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8287 bpp, connector->base.display_info.bpc*3);
8288 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8289 }
8290
8291 /* Clamp bpp to 8 on screens without EDID 1.4 */
8292 if (connector->base.display_info.bpc == 0 && bpp > 24) {
8293 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8294 bpp);
8295 pipe_config->pipe_bpp = 24;
8296 }
8297}
8298
4e53c2e0 8299static int
050f7aeb
DV		 8300compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8301 struct drm_framebuffer *fb,
8302 struct intel_crtc_config *pipe_config)
4e53c2e0 8303{
050f7aeb
DV		 8304 struct drm_device *dev = crtc->base.dev;
8305 struct intel_connector *connector;
4e53c2e0
DV		 8306 int bpp;
8307
d42264b1
DV		 8308 switch (fb->pixel_format) {
8309 case DRM_FORMAT_C8:
4e53c2e0
DV		 8310 bpp = 8*3; /* since we go through a colormap */
8311 break;
d42264b1
DV		 8312 case DRM_FORMAT_XRGB1555:
8313 case DRM_FORMAT_ARGB1555:
8314 /* checked in intel_framebuffer_init already */
8315 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8316 return -EINVAL;
8317 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 8318 bpp = 6*3; /* min is 18bpp */
8319 break;
d42264b1
DV		 8320 case DRM_FORMAT_XBGR8888:
8321 case DRM_FORMAT_ABGR8888:
8322 /* checked in intel_framebuffer_init already */
8323 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8324 return -EINVAL;
8325 case DRM_FORMAT_XRGB8888:
8326 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 8327 bpp = 8*3;
8328 break;
d42264b1
DV		 8329 case DRM_FORMAT_XRGB2101010:
8330 case DRM_FORMAT_ARGB2101010:
8331 case DRM_FORMAT_XBGR2101010:
8332 case DRM_FORMAT_ABGR2101010:
8333 /* checked in intel_framebuffer_init already */
8334 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 8335 return -EINVAL;
4e53c2e0
DV		 8336 bpp = 10*3;
8337 break;
baba133a 8338 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 8339 default:
8340 DRM_DEBUG_KMS("unsupported depth\n");
8341 return -EINVAL;
8342 }
8343
4e53c2e0
DV		 8344 pipe_config->pipe_bpp = bpp;
8345
8346 /* Clamp display bpp to EDID value */
8347 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 8348 base.head) {
1b829e05
DV		 8349 if (!connector->new_encoder ||
8350 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 8351 continue;
8352
050f7aeb 8353 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 8354 }
8355
8356 return bpp;
8357}
8358
644db711
DV		 8359static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
8360{
8361 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8362 "type: 0x%x flags: 0x%x\n",
1342830c 8363 mode->crtc_clock,
644db711
DV		 8364 mode->crtc_hdisplay, mode->crtc_hsync_start,
8365 mode->crtc_hsync_end, mode->crtc_htotal,
8366 mode->crtc_vdisplay, mode->crtc_vsync_start,
8367 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
8368}
8369
c0b03411
DV		 8370static void intel_dump_pipe_config(struct intel_crtc *crtc,
8371 struct intel_crtc_config *pipe_config,
8372 const char *context)
8373{
8374 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8375 context, pipe_name(crtc->pipe));
8376
8377 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8378 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8379 pipe_config->pipe_bpp, pipe_config->dither);
8380 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8381 pipe_config->has_pch_encoder,
8382 pipe_config->fdi_lanes,
8383 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8384 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8385 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 8386 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8387 pipe_config->has_dp_encoder,
8388 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8389 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8390 pipe_config->dp_m_n.tu);
c0b03411
DV		 8391 DRM_DEBUG_KMS("requested mode:\n");
8392 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8393 DRM_DEBUG_KMS("adjusted mode:\n");
8394 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
644db711 8395 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
d71b8d4a 8396 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 8397 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8398 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
c0b03411
DV		 8399 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8400 pipe_config->gmch_pfit.control,
8401 pipe_config->gmch_pfit.pgm_ratios,
8402 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 8403 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 8404 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 8405 pipe_config->pch_pfit.size,
8406 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 8407 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 8408 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
c0b03411
DV		 8409}
8410
accfc0c5
DV		 8411static bool check_encoder_cloning(struct drm_crtc *crtc)
8412{
8413 int num_encoders = 0;
8414 bool uncloneable_encoders = false;
8415 struct intel_encoder *encoder;
8416
8417 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8418 base.head) {
8419 if (&encoder->new_crtc->base != crtc)
8420 continue;
8421
8422 num_encoders++;
8423 if (!encoder->cloneable)
8424 uncloneable_encoders = true;
8425 }
8426
8427 return !(num_encoders > 1 && uncloneable_encoders);
8428}
8429
b8cecdf5
DV		 8430static struct intel_crtc_config *
8431intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 8432 struct drm_framebuffer *fb,
b8cecdf5 8433 struct drm_display_mode *mode)
ee7b9f93 8434{
7758a113 8435 struct drm_device *dev = crtc->dev;
7758a113 8436 struct intel_encoder *encoder;
b8cecdf5 8437 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 8438 int plane_bpp, ret = -EINVAL;
8439 bool retry = true;
ee7b9f93 8440
accfc0c5
DV		 8441 if (!check_encoder_cloning(crtc)) {
8442 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8443 return ERR_PTR(-EINVAL);
8444 }
8445
b8cecdf5
DV		 8446 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8447 if (!pipe_config)
7758a113
DV		 8448 return ERR_PTR(-ENOMEM);
8449
b8cecdf5
DV		 8450 drm_mode_copy(&pipe_config->adjusted_mode, mode);
8451 drm_mode_copy(&pipe_config->requested_mode, mode);
37327abd 8452
e143a21c
DV		 8453 pipe_config->cpu_transcoder =
8454 (enum transcoder) to_intel_crtc(crtc)->pipe;
c0d43d62 8455 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 8456
2960bc9c
ID		 8457 /*
8458 * Sanitize sync polarity flags based on requested ones. If neither
8459 * positive or negative polarity is requested, treat this as meaning
8460 * negative polarity.
8461 */
8462 if (!(pipe_config->adjusted_mode.flags &
8463 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8464 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8465
8466 if (!(pipe_config->adjusted_mode.flags &
8467 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8468 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8469
050f7aeb
DV		 8470 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8471 * plane pixel format and any sink constraints into account. Returns the
8472 * source plane bpp so that dithering can be selected on mismatches
8473 * after encoders and crtc also have had their say. */
8474 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8475 fb, pipe_config);
4e53c2e0
DV		 8476 if (plane_bpp < 0)
8477 goto fail;
8478
e29c22c0 8479encoder_retry:
ef1b460d 8480 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 8481 pipe_config->port_clock = 0;
ef1b460d 8482 pipe_config->pixel_multiplier = 1;
ff9a6750 8483
135c81b8 8484 /* Fill in default crtc timings, allow encoders to overwrite them. */
6ce70f5e 8485 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
135c81b8 8486
350a10ca
DL		 8487 /* set_crtcinfo() may have adjusted hdisplay/vdisplay */
8488 pipe_config->pipe_src_w = pipe_config->adjusted_mode.crtc_hdisplay;
8489 pipe_config->pipe_src_h = pipe_config->adjusted_mode.crtc_vdisplay;
8490
7758a113
DV		 8491 /* Pass our mode to the connectors and the CRTC to give them a chance to
8492 * adjust it according to limitations or connector properties, and also
8493 * a chance to reject the mode entirely.
47f1c6c9 8494 */
7758a113
DV		 8495 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8496 base.head) {
47f1c6c9 8497
7758a113
DV		 8498 if (&encoder->new_crtc->base != crtc)
8499 continue;
7ae89233 8500
efea6e8e
DV		 8501 if (!(encoder->compute_config(encoder, pipe_config))) {
8502 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 8503 goto fail;
8504 }
ee7b9f93 8505 }
47f1c6c9 8506
ff9a6750
DV		 8507 /* Set default port clock if not overwritten by the encoder. Needs to be
8508 * done afterwards in case the encoder adjusts the mode. */
8509 if (!pipe_config->port_clock)
241bfc38
DL		 8510 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
8511 * pipe_config->pixel_multiplier;
ff9a6750 8512
a43f6e0f 8513 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 8514 if (ret < 0) {
7758a113
DV		 8515 DRM_DEBUG_KMS("CRTC fixup failed\n");
8516 goto fail;
ee7b9f93 8517 }
e29c22c0
DV		 8518
8519 if (ret == RETRY) {
8520 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8521 ret = -EINVAL;
8522 goto fail;
8523 }
8524
8525 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8526 retry = false;
8527 goto encoder_retry;
8528 }
8529
4e53c2e0
DV		 8530 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8531 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8532 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8533
b8cecdf5 8534 return pipe_config;
7758a113 8535fail:
b8cecdf5 8536 kfree(pipe_config);
e29c22c0 8537 return ERR_PTR(ret);
ee7b9f93 8538}
47f1c6c9 8539
e2e1ed41
DV		 8540/* Computes which crtcs are affected and sets the relevant bits in the mask. For
8541 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8542static void
8543intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8544 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 8545{
8546 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 8547 struct drm_device *dev = crtc->dev;
8548 struct intel_encoder *encoder;
8549 struct intel_connector *connector;
8550 struct drm_crtc *tmp_crtc;
79e53945 8551
e2e1ed41 8552 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 8553
e2e1ed41
DV		 8554 /* Check which crtcs have changed outputs connected to them, these need
8555 * to be part of the prepare_pipes mask. We don't (yet) support global
8556 * modeset across multiple crtcs, so modeset_pipes will only have one
8557 * bit set at most. */
8558 list_for_each_entry(connector, &dev->mode_config.connector_list,
8559 base.head) {
8560 if (connector->base.encoder == &connector->new_encoder->base)
8561 continue;
79e53945 8562
e2e1ed41
DV		 8563 if (connector->base.encoder) {
8564 tmp_crtc = connector->base.encoder->crtc;
8565
8566 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8567 }
8568
8569 if (connector->new_encoder)
8570 *prepare_pipes |=
8571 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 8572 }
8573
e2e1ed41
DV		 8574 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8575 base.head) {
8576 if (encoder->base.crtc == &encoder->new_crtc->base)
8577 continue;
8578
8579 if (encoder->base.crtc) {
8580 tmp_crtc = encoder->base.crtc;
8581
8582 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8583 }
8584
8585 if (encoder->new_crtc)
8586 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 8587 }
8588
e2e1ed41
DV		 8589 /* Check for any pipes that will be fully disabled ... */
8590 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8591 base.head) {
8592 bool used = false;
22fd0fab 8593
e2e1ed41
DV		 8594 /* Don't try to disable disabled crtcs. */
8595 if (!intel_crtc->base.enabled)
8596 continue;
7e7d76c3 8597
e2e1ed41
DV		 8598 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8599 base.head) {
8600 if (encoder->new_crtc == intel_crtc)
8601 used = true;
8602 }
8603
8604 if (!used)
8605 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 8606 }
8607
e2e1ed41
DV		 8608
8609 /* set_mode is also used to update properties on life display pipes. */
8610 intel_crtc = to_intel_crtc(crtc);
8611 if (crtc->enabled)
8612 *prepare_pipes |= 1 << intel_crtc->pipe;
8613
b6c5164d
DV		 8614 /*
8615 * For simplicity do a full modeset on any pipe where the output routing
8616 * changed. We could be more clever, but that would require us to be
8617 * more careful with calling the relevant encoder->mode_set functions.
8618 */
e2e1ed41
DV		 8619 if (*prepare_pipes)
8620 *modeset_pipes = *prepare_pipes;
8621
8622 /* ... and mask these out. */
8623 *modeset_pipes &= ~(*disable_pipes);
8624 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 8625
8626 /*
8627 * HACK: We don't (yet) fully support global modesets. intel_set_config
8628 * obies this rule, but the modeset restore mode of
8629 * intel_modeset_setup_hw_state does not.
8630 */
8631 *modeset_pipes &= 1 << intel_crtc->pipe;
8632 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 8633
8634 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8635 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 8636}
79e53945 8637
ea9d758d 8638static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 8639{
ea9d758d 8640 struct drm_encoder *encoder;
f6e5b160 8641 struct drm_device *dev = crtc->dev;
f6e5b160 8642
ea9d758d
DV		 8643 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8644 if (encoder->crtc == crtc)
8645 return true;
8646
8647 return false;
8648}
8649
8650static void
8651intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8652{
8653 struct intel_encoder *intel_encoder;
8654 struct intel_crtc *intel_crtc;
8655 struct drm_connector *connector;
8656
8657 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8658 base.head) {
8659 if (!intel_encoder->base.crtc)
8660 continue;
8661
8662 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8663
8664 if (prepare_pipes & (1 << intel_crtc->pipe))
8665 intel_encoder->connectors_active = false;
8666 }
8667
8668 intel_modeset_commit_output_state(dev);
8669
8670 /* Update computed state. */
8671 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8672 base.head) {
8673 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8674 }
8675
8676 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8677 if (!connector->encoder || !connector->encoder->crtc)
8678 continue;
8679
8680 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8681
8682 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8683 struct drm_property *dpms_property =
8684 dev->mode_config.dpms_property;
8685
ea9d758d 8686 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8687 drm_object_property_set_value(&connector->base,
68d34720
DV		 8688 dpms_property,
8689 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8690
8691 intel_encoder = to_intel_encoder(connector->encoder);
8692 intel_encoder->connectors_active = true;
8693 }
8694 }
8695
8696}
8697
3bd26263 8698static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 8699{
3bd26263 8700 int diff;
f1f644dc
JB		 8701
8702 if (clock1 == clock2)
8703 return true;
8704
8705 if (!clock1 || !clock2)
8706 return false;
8707
8708 diff = abs(clock1 - clock2);
8709
8710 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8711 return true;
8712
8713 return false;
8714}
8715
25c5b266
DV		 8716#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8717 list_for_each_entry((intel_crtc), \
8718 &(dev)->mode_config.crtc_list, \
8719 base.head) \
0973f18f 8720 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8721
0e8ffe1b 8722static bool
2fa2fe9a
DV		 8723intel_pipe_config_compare(struct drm_device *dev,
8724 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8725 struct intel_crtc_config *pipe_config)
8726{
66e985c0
DV		 8727#define PIPE_CONF_CHECK_X(name) \
8728 if (current_config->name != pipe_config->name) { \
8729 DRM_ERROR("mismatch in " #name " " \
8730 "(expected 0x%08x, found 0x%08x)\n", \
8731 current_config->name, \
8732 pipe_config->name); \
8733 return false; \
8734 }
8735
08a24034
DV		 8736#define PIPE_CONF_CHECK_I(name) \
8737 if (current_config->name != pipe_config->name) { \
8738 DRM_ERROR("mismatch in " #name " " \
8739 "(expected %i, found %i)\n", \
8740 current_config->name, \
8741 pipe_config->name); \
8742 return false; \
88adfff1
DV		 8743 }
8744
1bd1bd80
DV		 8745#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8746 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 8747 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 8748 "(expected %i, found %i)\n", \
8749 current_config->name & (mask), \
8750 pipe_config->name & (mask)); \
8751 return false; \
8752 }
8753
5e550656
VS		 8754#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
8755 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
8756 DRM_ERROR("mismatch in " #name " " \
8757 "(expected %i, found %i)\n", \
8758 current_config->name, \
8759 pipe_config->name); \
8760 return false; \
8761 }
8762
bb760063
DV		 8763#define PIPE_CONF_QUIRK(quirk) \
8764 ((current_config->quirks | pipe_config->quirks) & (quirk))
8765
eccb140b
DV		 8766 PIPE_CONF_CHECK_I(cpu_transcoder);
8767
08a24034
DV		 8768 PIPE_CONF_CHECK_I(has_pch_encoder);
8769 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8770 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8771 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8772 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8773 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8774 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8775
eb14cb74
VS		 8776 PIPE_CONF_CHECK_I(has_dp_encoder);
8777 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
8778 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
8779 PIPE_CONF_CHECK_I(dp_m_n.link_m);
8780 PIPE_CONF_CHECK_I(dp_m_n.link_n);
8781 PIPE_CONF_CHECK_I(dp_m_n.tu);
8782
1bd1bd80
DV		 8783 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8784 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8785 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8786 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8787 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8788 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8789
8790 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8791 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8792 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8793 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8794 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8795 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8796
c93f54cf 8797 PIPE_CONF_CHECK_I(pixel_multiplier);
6c49f241 8798
1bd1bd80
DV		 8799 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8800 DRM_MODE_FLAG_INTERLACE);
8801
bb760063
DV		 8802 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8803 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8804 DRM_MODE_FLAG_PHSYNC);
8805 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8806 DRM_MODE_FLAG_NHSYNC);
8807 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8808 DRM_MODE_FLAG_PVSYNC);
8809 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8810 DRM_MODE_FLAG_NVSYNC);
8811 }
045ac3b5 8812
37327abd
VS		 8813 PIPE_CONF_CHECK_I(pipe_src_w);
8814 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 8815
2fa2fe9a
DV		 8816 PIPE_CONF_CHECK_I(gmch_pfit.control);
8817 /* pfit ratios are autocomputed by the hw on gen4+ */
8818 if (INTEL_INFO(dev)->gen < 4)
8819 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8820 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
fd4daa9c
CW		 8821 PIPE_CONF_CHECK_I(pch_pfit.enabled);
8822 if (current_config->pch_pfit.enabled) {
8823 PIPE_CONF_CHECK_I(pch_pfit.pos);
8824 PIPE_CONF_CHECK_I(pch_pfit.size);
8825 }
2fa2fe9a 8826
42db64ef
PZ		 8827 PIPE_CONF_CHECK_I(ips_enabled);
8828
282740f7
VS		 8829 PIPE_CONF_CHECK_I(double_wide);
8830
c0d43d62 8831 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 8832 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 8833 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 8834 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8835 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
c0d43d62 8836
42571aef
VS		 8837 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
8838 PIPE_CONF_CHECK_I(pipe_bpp);
8839
d71b8d4a 8840 if (!IS_HASWELL(dev)) {
241bfc38 8841 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
d71b8d4a
VS		 8842 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
8843 }
5e550656 8844
66e985c0 8845#undef PIPE_CONF_CHECK_X
08a24034 8846#undef PIPE_CONF_CHECK_I
1bd1bd80 8847#undef PIPE_CONF_CHECK_FLAGS
5e550656 8848#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 8849#undef PIPE_CONF_QUIRK
88adfff1 8850
0e8ffe1b
DV		 8851 return true;
8852}
8853
91d1b4bd
DV		 8854static void
8855check_connector_state(struct drm_device *dev)
8af6cf88 8856{
8af6cf88
DV		 8857 struct intel_connector *connector;
8858
8859 list_for_each_entry(connector, &dev->mode_config.connector_list,
8860 base.head) {
8861 /* This also checks the encoder/connector hw state with the
8862 * ->get_hw_state callbacks. */
8863 intel_connector_check_state(connector);
8864
8865 WARN(&connector->new_encoder->base != connector->base.encoder,
8866 "connector's staged encoder doesn't match current encoder\n");
8867 }
91d1b4bd
DV		 8868}
8869
8870static void
8871check_encoder_state(struct drm_device *dev)
8872{
8873 struct intel_encoder *encoder;
8874 struct intel_connector *connector;
8af6cf88
DV		 8875
8876 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8877 base.head) {
8878 bool enabled = false;
8879 bool active = false;
8880 enum pipe pipe, tracked_pipe;
8881
8882 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8883 encoder->base.base.id,
8884 drm_get_encoder_name(&encoder->base));
8885
8886 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8887 "encoder's stage crtc doesn't match current crtc\n");
8888 WARN(encoder->connectors_active && !encoder->base.crtc,
8889 "encoder's active_connectors set, but no crtc\n");
8890
8891 list_for_each_entry(connector, &dev->mode_config.connector_list,
8892 base.head) {
8893 if (connector->base.encoder != &encoder->base)
8894 continue;
8895 enabled = true;
8896 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8897 active = true;
8898 }
8899 WARN(!!encoder->base.crtc != enabled,
8900 "encoder's enabled state mismatch "
8901 "(expected %i, found %i)\n",
8902 !!encoder->base.crtc, enabled);
8903 WARN(active && !encoder->base.crtc,
8904 "active encoder with no crtc\n");
8905
8906 WARN(encoder->connectors_active != active,
8907 "encoder's computed active state doesn't match tracked active state "
8908 "(expected %i, found %i)\n", active, encoder->connectors_active);
8909
8910 active = encoder->get_hw_state(encoder, &pipe);
8911 WARN(active != encoder->connectors_active,
8912 "encoder's hw state doesn't match sw tracking "
8913 "(expected %i, found %i)\n",
8914 encoder->connectors_active, active);
8915
8916 if (!encoder->base.crtc)
8917 continue;
8918
8919 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8920 WARN(active && pipe != tracked_pipe,
8921 "active encoder's pipe doesn't match"
8922 "(expected %i, found %i)\n",
8923 tracked_pipe, pipe);
8924
8925 }
91d1b4bd
DV		 8926}
8927
8928static void
8929check_crtc_state(struct drm_device *dev)
8930{
8931 drm_i915_private_t *dev_priv = dev->dev_private;
8932 struct intel_crtc *crtc;
8933 struct intel_encoder *encoder;
8934 struct intel_crtc_config pipe_config;
8af6cf88
DV		 8935
8936 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8937 base.head) {
8938 bool enabled = false;
8939 bool active = false;
8940
045ac3b5
JB		 8941 memset(&pipe_config, 0, sizeof(pipe_config));
8942
8af6cf88
DV		 8943 DRM_DEBUG_KMS("[CRTC:%d]\n",
8944 crtc->base.base.id);
8945
8946 WARN(crtc->active && !crtc->base.enabled,
8947 "active crtc, but not enabled in sw tracking\n");
8948
8949 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8950 base.head) {
8951 if (encoder->base.crtc != &crtc->base)
8952 continue;
8953 enabled = true;
8954 if (encoder->connectors_active)
8955 active = true;
8956 }
6c49f241 8957
8af6cf88
DV		 8958 WARN(active != crtc->active,
8959 "crtc's computed active state doesn't match tracked active state "
8960 "(expected %i, found %i)\n", active, crtc->active);
8961 WARN(enabled != crtc->base.enabled,
8962 "crtc's computed enabled state doesn't match tracked enabled state "
8963 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8964
0e8ffe1b
DV		 8965 active = dev_priv->display.get_pipe_config(crtc,
8966 &pipe_config);
d62cf62a
DV		 8967
8968 /* hw state is inconsistent with the pipe A quirk */
8969 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8970 active = crtc->active;
8971
6c49f241
DV		 8972 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8973 base.head) {
3eaba51c 8974 enum pipe pipe;
6c49f241
DV		 8975 if (encoder->base.crtc != &crtc->base)
8976 continue;
3eaba51c
VS		 8977 if (encoder->get_config &&
8978 encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 8979 encoder->get_config(encoder, &pipe_config);
8980 }
8981
0e8ffe1b
DV		 8982 WARN(crtc->active != active,
8983 "crtc active state doesn't match with hw state "
8984 "(expected %i, found %i)\n", crtc->active, active);
8985
c0b03411
DV		 8986 if (active &&
8987 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8988 WARN(1, "pipe state doesn't match!\n");
8989 intel_dump_pipe_config(crtc, &pipe_config,
8990 "[hw state]");
8991 intel_dump_pipe_config(crtc, &crtc->config,
8992 "[sw state]");
8993 }
8af6cf88
DV		 8994 }
8995}
8996
91d1b4bd
DV		 8997static void
8998check_shared_dpll_state(struct drm_device *dev)
8999{
9000 drm_i915_private_t *dev_priv = dev->dev_private;
9001 struct intel_crtc *crtc;
9002 struct intel_dpll_hw_state dpll_hw_state;
9003 int i;
5358901f
DV		 9004
9005 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9006 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9007 int enabled_crtcs = 0, active_crtcs = 0;
9008 bool active;
9009
9010 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9011
9012 DRM_DEBUG_KMS("%s\n", pll->name);
9013
9014 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9015
9016 WARN(pll->active > pll->refcount,
9017 "more active pll users than references: %i vs %i\n",
9018 pll->active, pll->refcount);
9019 WARN(pll->active && !pll->on,
9020 "pll in active use but not on in sw tracking\n");
35c95375
DV		 9021 WARN(pll->on && !pll->active,
9022 "pll in on but not on in use in sw tracking\n");
5358901f
DV		 9023 WARN(pll->on != active,
9024 "pll on state mismatch (expected %i, found %i)\n",
9025 pll->on, active);
9026
9027 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9028 base.head) {
9029 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9030 enabled_crtcs++;
9031 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9032 active_crtcs++;
9033 }
9034 WARN(pll->active != active_crtcs,
9035 "pll active crtcs mismatch (expected %i, found %i)\n",
9036 pll->active, active_crtcs);
9037 WARN(pll->refcount != enabled_crtcs,
9038 "pll enabled crtcs mismatch (expected %i, found %i)\n",
9039 pll->refcount, enabled_crtcs);
66e985c0
DV		 9040
9041 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9042 sizeof(dpll_hw_state)),
9043 "pll hw state mismatch\n");
5358901f 9044 }
8af6cf88
DV		 9045}
9046
91d1b4bd
DV		 9047void
9048intel_modeset_check_state(struct drm_device *dev)
9049{
9050 check_connector_state(dev);
9051 check_encoder_state(dev);
9052 check_crtc_state(dev);
9053 check_shared_dpll_state(dev);
9054}
9055
18442d08
VS		 9056void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9057 int dotclock)
9058{
9059 /*
9060 * FDI already provided one idea for the dotclock.
9061 * Yell if the encoder disagrees.
9062 */
241bfc38 9063 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
18442d08 9064 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
241bfc38 9065 pipe_config->adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 9066}
9067
f30da187
DV		 9068static int __intel_set_mode(struct drm_crtc *crtc,
9069 struct drm_display_mode *mode,
9070 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 9071{
9072 struct drm_device *dev = crtc->dev;
dbf2b54e 9073 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 9074 struct drm_display_mode *saved_mode, *saved_hwmode;
9075 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 9076 struct intel_crtc *intel_crtc;
9077 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 9078 int ret = 0;
a6778b3c 9079
a1e22653 9080 saved_mode = kcalloc(2, sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 9081 if (!saved_mode)
9082 return -ENOMEM;
3ac18232 9083 saved_hwmode = saved_mode + 1;
a6778b3c 9084
e2e1ed41 9085 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 9086 &prepare_pipes, &disable_pipes);
9087
3ac18232
TG		 9088 *saved_hwmode = crtc->hwmode;
9089 *saved_mode = crtc->mode;
a6778b3c 9090
25c5b266
DV		 9091 /* Hack: Because we don't (yet) support global modeset on multiple
9092 * crtcs, we don't keep track of the new mode for more than one crtc.
9093 * Hence simply check whether any bit is set in modeset_pipes in all the
9094 * pieces of code that are not yet converted to deal with mutliple crtcs
9095 * changing their mode at the same time. */
25c5b266 9096 if (modeset_pipes) {
4e53c2e0 9097 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 9098 if (IS_ERR(pipe_config)) {
9099 ret = PTR_ERR(pipe_config);
9100 pipe_config = NULL;
9101
3ac18232 9102 goto out;
25c5b266 9103 }
c0b03411
DV		 9104 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9105 "[modeset]");
25c5b266 9106 }
a6778b3c 9107
460da916
DV		 9108 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9109 intel_crtc_disable(&intel_crtc->base);
9110
ea9d758d
DV		 9111 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9112 if (intel_crtc->base.enabled)
9113 dev_priv->display.crtc_disable(&intel_crtc->base);
9114 }
a6778b3c 9115
6c4c86f5
DV		 9116 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9117 * to set it here already despite that we pass it down the callchain.
f6e5b160 9118 */
b8cecdf5 9119 if (modeset_pipes) {
25c5b266 9120 crtc->mode = *mode;
b8cecdf5
DV		 9121 /* mode_set/enable/disable functions rely on a correct pipe
9122 * config. */
9123 to_intel_crtc(crtc)->config = *pipe_config;
9124 }
7758a113 9125
ea9d758d
DV		 9126 /* Only after disabling all output pipelines that will be changed can we
9127 * update the the output configuration. */
9128 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 9129
47fab737
DV		 9130 if (dev_priv->display.modeset_global_resources)
9131 dev_priv->display.modeset_global_resources(dev);
9132
a6778b3c
DV		 9133 /* Set up the DPLL and any encoders state that needs to adjust or depend
9134 * on the DPLL.
f6e5b160 9135 */
25c5b266 9136 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 9137 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 9138 x, y, fb);
9139 if (ret)
9140 goto done;
a6778b3c
DV		 9141 }
9142
9143 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 9144 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9145 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 9146
25c5b266
DV		 9147 if (modeset_pipes) {
9148 /* Store real post-adjustment hardware mode. */
b8cecdf5 9149 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 9150
25c5b266
DV		 9151 /* Calculate and store various constants which
9152 * are later needed by vblank and swap-completion
9153 * timestamping. They are derived from true hwmode.
9154 */
9155 drm_calc_timestamping_constants(crtc);
9156 }
a6778b3c
DV		 9157
9158 /* FIXME: add subpixel order */
9159done:
c0c36b94 9160 if (ret && crtc->enabled) {
3ac18232
TG		 9161 crtc->hwmode = *saved_hwmode;
9162 crtc->mode = *saved_mode;
a6778b3c
DV		 9163 }
9164
3ac18232 9165out:
b8cecdf5 9166 kfree(pipe_config);
3ac18232 9167 kfree(saved_mode);
a6778b3c 9168 return ret;
f6e5b160
CW		 9169}
9170
e7457a9a
DL		 9171static int intel_set_mode(struct drm_crtc *crtc,
9172 struct drm_display_mode *mode,
9173 int x, int y, struct drm_framebuffer *fb)
f30da187
DV		 9174{
9175 int ret;
9176
9177 ret = __intel_set_mode(crtc, mode, x, y, fb);
9178
9179 if (ret == 0)
9180 intel_modeset_check_state(crtc->dev);
9181
9182 return ret;
9183}
9184
c0c36b94
CW		 9185void intel_crtc_restore_mode(struct drm_crtc *crtc)
9186{
9187 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9188}
9189
25c5b266
DV		 9190#undef for_each_intel_crtc_masked
9191
d9e55608
DV		 9192static void intel_set_config_free(struct intel_set_config *config)
9193{
9194 if (!config)
9195 return;
9196
1aa4b628
DV		 9197 kfree(config->save_connector_encoders);
9198 kfree(config->save_encoder_crtcs);
d9e55608
DV		 9199 kfree(config);
9200}
9201
85f9eb71
DV		 9202static int intel_set_config_save_state(struct drm_device *dev,
9203 struct intel_set_config *config)
9204{
85f9eb71
DV		 9205 struct drm_encoder *encoder;
9206 struct drm_connector *connector;
9207 int count;
9208
1aa4b628
DV		 9209 config->save_encoder_crtcs =
9210 kcalloc(dev->mode_config.num_encoder,
9211 sizeof(struct drm_crtc *), GFP_KERNEL);
9212 if (!config->save_encoder_crtcs)
85f9eb71
DV		 9213 return -ENOMEM;
9214
1aa4b628
DV		 9215 config->save_connector_encoders =
9216 kcalloc(dev->mode_config.num_connector,
9217 sizeof(struct drm_encoder *), GFP_KERNEL);
9218 if (!config->save_connector_encoders)
85f9eb71
DV		 9219 return -ENOMEM;
9220
9221 /* Copy data. Note that driver private data is not affected.
9222 * Should anything bad happen only the expected state is
9223 * restored, not the drivers personal bookkeeping.
9224 */
85f9eb71
DV		 9225 count = 0;
9226 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 9227 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 9228 }
9229
9230 count = 0;
9231 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 9232 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 9233 }
9234
9235 return 0;
9236}
9237
9238static void intel_set_config_restore_state(struct drm_device *dev,
9239 struct intel_set_config *config)
9240{
9a935856
DV		 9241 struct intel_encoder *encoder;
9242 struct intel_connector *connector;
85f9eb71
DV		 9243 int count;
9244
85f9eb71 9245 count = 0;
9a935856
DV		 9246 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9247 encoder->new_crtc =
9248 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 9249 }
9250
9251 count = 0;
9a935856
DV		 9252 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9253 connector->new_encoder =
9254 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 9255 }
9256}
9257
e3de42b6 9258static bool
2e57f47d 9259is_crtc_connector_off(struct drm_mode_set *set)
e3de42b6
ID		 9260{
9261 int i;
9262
2e57f47d
CW		 9263 if (set->num_connectors == 0)
9264 return false;
9265
9266 if (WARN_ON(set->connectors == NULL))
9267 return false;
9268
9269 for (i = 0; i < set->num_connectors; i++)
9270 if (set->connectors[i]->encoder &&
9271 set->connectors[i]->encoder->crtc == set->crtc &&
9272 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
e3de42b6
ID		 9273 return true;
9274
9275 return false;
9276}
9277
5e2b584e
DV		 9278static void
9279intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9280 struct intel_set_config *config)
9281{
9282
9283 /* We should be able to check here if the fb has the same properties
9284 * and then just flip_or_move it */
2e57f47d
CW		 9285 if (is_crtc_connector_off(set)) {
9286 config->mode_changed = true;
e3de42b6 9287 } else if (set->crtc->fb != set->fb) {
5e2b584e
DV		 9288 /* If we have no fb then treat it as a full mode set */
9289 if (set->crtc->fb == NULL) {
319d9827
JB		 9290 struct intel_crtc *intel_crtc =
9291 to_intel_crtc(set->crtc);
9292
9293 if (intel_crtc->active && i915_fastboot) {
9294 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9295 config->fb_changed = true;
9296 } else {
9297 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9298 config->mode_changed = true;
9299 }
5e2b584e
DV		 9300 } else if (set->fb == NULL) {
9301 config->mode_changed = true;
72f4901e
DV		 9302 } else if (set->fb->pixel_format !=
9303 set->crtc->fb->pixel_format) {
5e2b584e 9304 config->mode_changed = true;
e3de42b6 9305 } else {
5e2b584e 9306 config->fb_changed = true;
e3de42b6 9307 }
5e2b584e
DV		 9308 }
9309
835c5873 9310 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 9311 config->fb_changed = true;
9312
9313 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9314 DRM_DEBUG_KMS("modes are different, full mode set\n");
9315 drm_mode_debug_printmodeline(&set->crtc->mode);
9316 drm_mode_debug_printmodeline(set->mode);
9317 config->mode_changed = true;
9318 }
a1d95703
CW		 9319
9320 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9321 set->crtc->base.id, config->mode_changed, config->fb_changed);
5e2b584e
DV		 9322}
9323
2e431051 9324static int
9a935856
DV		 9325intel_modeset_stage_output_state(struct drm_device *dev,
9326 struct drm_mode_set *set,
9327 struct intel_set_config *config)
50f56119 9328{
85f9eb71 9329 struct drm_crtc *new_crtc;
9a935856
DV		 9330 struct intel_connector *connector;
9331 struct intel_encoder *encoder;
f3f08572 9332 int ro;
50f56119 9333
9abdda74 9334 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 9335 * of connectors. For paranoia, double-check this. */
9336 WARN_ON(!set->fb && (set->num_connectors != 0));
9337 WARN_ON(set->fb && (set->num_connectors == 0));
9338
9a935856
DV		 9339 list_for_each_entry(connector, &dev->mode_config.connector_list,
9340 base.head) {
9341 /* Otherwise traverse passed in connector list and get encoders
9342 * for them. */
50f56119 9343 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 9344 if (set->connectors[ro] == &connector->base) {
9345 connector->new_encoder = connector->encoder;
50f56119
DV		 9346 break;
9347 }
9348 }
9349
9a935856
DV		 9350 /* If we disable the crtc, disable all its connectors. Also, if
9351 * the connector is on the changing crtc but not on the new
9352 * connector list, disable it. */
9353 if ((!set->fb || ro == set->num_connectors) &&
9354 connector->base.encoder &&
9355 connector->base.encoder->crtc == set->crtc) {
9356 connector->new_encoder = NULL;
9357
9358 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9359 connector->base.base.id,
9360 drm_get_connector_name(&connector->base));
9361 }
9362
9363
9364 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 9365 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 9366 config->mode_changed = true;
50f56119
DV		 9367 }
9368 }
9a935856 9369 /* connector->new_encoder is now updated for all connectors. */
50f56119 9370
9a935856 9371 /* Update crtc of enabled connectors. */
9a935856
DV		 9372 list_for_each_entry(connector, &dev->mode_config.connector_list,
9373 base.head) {
9374 if (!connector->new_encoder)
50f56119
DV		 9375 continue;
9376
9a935856 9377 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 9378
9379 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 9380 if (set->connectors[ro] == &connector->base)
50f56119
DV		 9381 new_crtc = set->crtc;
9382 }
9383
9384 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 9385 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9386 new_crtc)) {
5e2b584e 9387 return -EINVAL;
50f56119 9388 }
9a935856
DV		 9389 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9390
9391 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9392 connector->base.base.id,
9393 drm_get_connector_name(&connector->base),
9394 new_crtc->base.id);
9395 }
9396
9397 /* Check for any encoders that needs to be disabled. */
9398 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9399 base.head) {
9400 list_for_each_entry(connector,
9401 &dev->mode_config.connector_list,
9402 base.head) {
9403 if (connector->new_encoder == encoder) {
9404 WARN_ON(!connector->new_encoder->new_crtc);
9405
9406 goto next_encoder;
9407 }
9408 }
9409 encoder->new_crtc = NULL;
9410next_encoder:
9411 /* Only now check for crtc changes so we don't miss encoders
9412 * that will be disabled. */
9413 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 9414 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 9415 config->mode_changed = true;
50f56119
DV		 9416 }
9417 }
9a935856 9418 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 9419
2e431051
DV		 9420 return 0;
9421}
9422
9423static int intel_crtc_set_config(struct drm_mode_set *set)
9424{
9425 struct drm_device *dev;
2e431051
DV		 9426 struct drm_mode_set save_set;
9427 struct intel_set_config *config;
9428 int ret;
2e431051 9429
8d3e375e
DV		 9430 BUG_ON(!set);
9431 BUG_ON(!set->crtc);
9432 BUG_ON(!set->crtc->helper_private);
2e431051 9433
7e53f3a4
DV		 9434 /* Enforce sane interface api - has been abused by the fb helper. */
9435 BUG_ON(!set->mode && set->fb);
9436 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 9437
2e431051
DV		 9438 if (set->fb) {
9439 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9440 set->crtc->base.id, set->fb->base.id,
9441 (int)set->num_connectors, set->x, set->y);
9442 } else {
9443 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 9444 }
9445
9446 dev = set->crtc->dev;
9447
9448 ret = -ENOMEM;
9449 config = kzalloc(sizeof(*config), GFP_KERNEL);
9450 if (!config)
9451 goto out_config;
9452
9453 ret = intel_set_config_save_state(dev, config);
9454 if (ret)
9455 goto out_config;
9456
9457 save_set.crtc = set->crtc;
9458 save_set.mode = &set->crtc->mode;
9459 save_set.x = set->crtc->x;
9460 save_set.y = set->crtc->y;
9461 save_set.fb = set->crtc->fb;
9462
9463 /* Compute whether we need a full modeset, only an fb base update or no
9464 * change at all. In the future we might also check whether only the
9465 * mode changed, e.g. for LVDS where we only change the panel fitter in
9466 * such cases. */
9467 intel_set_config_compute_mode_changes(set, config);
9468
9a935856 9469 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 9470 if (ret)
9471 goto fail;
9472
5e2b584e 9473 if (config->mode_changed) {
c0c36b94
CW		 9474 ret = intel_set_mode(set->crtc, set->mode,
9475 set->x, set->y, set->fb);
5e2b584e 9476 } else if (config->fb_changed) {
4878cae2
VS		 9477 intel_crtc_wait_for_pending_flips(set->crtc);
9478
4f660f49 9479 ret = intel_pipe_set_base(set->crtc,
94352cf9 9480 set->x, set->y, set->fb);
50f56119
DV		 9481 }
9482
2d05eae1 9483 if (ret) {
bf67dfeb
DV		 9484 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9485 set->crtc->base.id, ret);
50f56119 9486fail:
2d05eae1 9487 intel_set_config_restore_state(dev, config);
50f56119 9488
2d05eae1
CW		 9489 /* Try to restore the config */
9490 if (config->mode_changed &&
9491 intel_set_mode(save_set.crtc, save_set.mode,
9492 save_set.x, save_set.y, save_set.fb))
9493 DRM_ERROR("failed to restore config after modeset failure\n");
9494 }
50f56119 9495
d9e55608
DV		 9496out_config:
9497 intel_set_config_free(config);
50f56119
DV		 9498 return ret;
9499}
f6e5b160
CW		 9500
9501static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 9502 .cursor_set = intel_crtc_cursor_set,
9503 .cursor_move = intel_crtc_cursor_move,
9504 .gamma_set = intel_crtc_gamma_set,
50f56119 9505 .set_config = intel_crtc_set_config,
f6e5b160
CW		 9506 .destroy = intel_crtc_destroy,
9507 .page_flip = intel_crtc_page_flip,
9508};
9509
79f689aa
PZ		 9510static void intel_cpu_pll_init(struct drm_device *dev)
9511{
affa9354 9512 if (HAS_DDI(dev))
79f689aa
PZ		 9513 intel_ddi_pll_init(dev);
9514}
9515
5358901f
DV		 9516static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9517 struct intel_shared_dpll *pll,
9518 struct intel_dpll_hw_state *hw_state)
ee7b9f93 9519{
5358901f 9520 uint32_t val;
ee7b9f93 9521
5358901f 9522 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 9523 hw_state->dpll = val;
9524 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9525 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 9526
9527 return val & DPLL_VCO_ENABLE;
9528}
9529
15bdd4cf
DV		 9530static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9531 struct intel_shared_dpll *pll)
9532{
9533 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9534 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9535}
9536
e7b903d2
DV		 9537static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9538 struct intel_shared_dpll *pll)
9539{
e7b903d2
DV		 9540 /* PCH refclock must be enabled first */
9541 assert_pch_refclk_enabled(dev_priv);
9542
15bdd4cf
DV		 9543 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9544
9545 /* Wait for the clocks to stabilize. */
9546 POSTING_READ(PCH_DPLL(pll->id));
9547 udelay(150);
9548
9549 /* The pixel multiplier can only be updated once the
9550 * DPLL is enabled and the clocks are stable.
9551 *
9552 * So write it again.
9553 */
9554 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9555 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9556 udelay(200);
9557}
9558
9559static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9560 struct intel_shared_dpll *pll)
9561{
9562 struct drm_device *dev = dev_priv->dev;
9563 struct intel_crtc *crtc;
e7b903d2
DV		 9564
9565 /* Make sure no transcoder isn't still depending on us. */
9566 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9567 if (intel_crtc_to_shared_dpll(crtc) == pll)
9568 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 9569 }
9570
15bdd4cf
DV		 9571 I915_WRITE(PCH_DPLL(pll->id), 0);
9572 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9573 udelay(200);
9574}
9575
46edb027
DV		 9576static char *ibx_pch_dpll_names[] = {
9577 "PCH DPLL A",
9578 "PCH DPLL B",
9579};
9580
7c74ade1 9581static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 9582{
e7b903d2 9583 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 9584 int i;
9585
7c74ade1 9586 dev_priv->num_shared_dpll = 2;
ee7b9f93 9587
e72f9fbf 9588 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 9589 dev_priv->shared_dplls[i].id = i;
9590 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 9591 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 9592 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9593 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 9594 dev_priv->shared_dplls[i].get_hw_state =
9595 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 9596 }
9597}
9598
7c74ade1
DV		 9599static void intel_shared_dpll_init(struct drm_device *dev)
9600{
e7b903d2 9601 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1
DV		 9602
9603 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9604 ibx_pch_dpll_init(dev);
9605 else
9606 dev_priv->num_shared_dpll = 0;
9607
9608 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9609 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9610 dev_priv->num_shared_dpll);
9611}
9612
b358d0a6 9613static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 9614{
22fd0fab 9615 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 9616 struct intel_crtc *intel_crtc;
9617 int i;
9618
955382f3 9619 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 9620 if (intel_crtc == NULL)
9621 return;
9622
9623 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9624
9625 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 9626 for (i = 0; i < 256; i++) {
9627 intel_crtc->lut_r[i] = i;
9628 intel_crtc->lut_g[i] = i;
9629 intel_crtc->lut_b[i] = i;
9630 }
9631
80824003
JB		 9632 /* Swap pipes & planes for FBC on pre-965 */
9633 intel_crtc->pipe = pipe;
9634 intel_crtc->plane = pipe;
e2e767ab 9635 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 9636 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 9637 intel_crtc->plane = !pipe;
80824003
JB		 9638 }
9639
22fd0fab
JB		 9640 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9641 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9642 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9643 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9644
79e53945 9645 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 9646}
9647
08d7b3d1 9648int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 9649 struct drm_file *file)
08d7b3d1 9650{
08d7b3d1 9651 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 9652 struct drm_mode_object *drmmode_obj;
9653 struct intel_crtc *crtc;
08d7b3d1 9654
1cff8f6b
DV		 9655 if (!drm_core_check_feature(dev, DRIVER_MODESET))
9656 return -ENODEV;
08d7b3d1 9657
c05422d5
DV		 9658 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9659 DRM_MODE_OBJECT_CRTC);
08d7b3d1 9660
c05422d5 9661 if (!drmmode_obj) {
08d7b3d1
CW		 9662 DRM_ERROR("no such CRTC id\n");
9663 return -EINVAL;
9664 }
9665
c05422d5
DV		 9666 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9667 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 9668
c05422d5 9669 return 0;
08d7b3d1
CW		 9670}
9671
66a9278e 9672static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 9673{
66a9278e
DV		 9674 struct drm_device *dev = encoder->base.dev;
9675 struct intel_encoder *source_encoder;
79e53945 9676 int index_mask = 0;
79e53945
JB		 9677 int entry = 0;
9678
66a9278e
DV		 9679 list_for_each_entry(source_encoder,
9680 &dev->mode_config.encoder_list, base.head) {
9681
9682 if (encoder == source_encoder)
79e53945 9683 index_mask |= (1 << entry);
66a9278e
DV		 9684
9685 /* Intel hw has only one MUX where enocoders could be cloned. */
9686 if (encoder->cloneable && source_encoder->cloneable)
9687 index_mask |= (1 << entry);
9688
79e53945
JB		 9689 entry++;
9690 }
4ef69c7a 9691
79e53945
JB		 9692 return index_mask;
9693}
9694
4d302442
CW		 9695static bool has_edp_a(struct drm_device *dev)
9696{
9697 struct drm_i915_private *dev_priv = dev->dev_private;
9698
9699 if (!IS_MOBILE(dev))
9700 return false;
9701
9702 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9703 return false;
9704
9705 if (IS_GEN5(dev) &&
9706 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9707 return false;
9708
9709 return true;
9710}
9711
79e53945
JB		 9712static void intel_setup_outputs(struct drm_device *dev)
9713{
725e30ad 9714 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 9715 struct intel_encoder *encoder;
cb0953d7 9716 bool dpd_is_edp = false;
79e53945 9717
c9093354 9718 intel_lvds_init(dev);
79e53945 9719
c40c0f5b 9720 if (!IS_ULT(dev))
79935fca 9721 intel_crt_init(dev);
cb0953d7 9722
affa9354 9723 if (HAS_DDI(dev)) {
0e72a5b5
ED		 9724 int found;
9725
9726 /* Haswell uses DDI functions to detect digital outputs */
9727 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9728 /* DDI A only supports eDP */
9729 if (found)
9730 intel_ddi_init(dev, PORT_A);
9731
9732 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9733 * register */
9734 found = I915_READ(SFUSE_STRAP);
9735
9736 if (found & SFUSE_STRAP_DDIB_DETECTED)
9737 intel_ddi_init(dev, PORT_B);
9738 if (found & SFUSE_STRAP_DDIC_DETECTED)
9739 intel_ddi_init(dev, PORT_C);
9740 if (found & SFUSE_STRAP_DDID_DETECTED)
9741 intel_ddi_init(dev, PORT_D);
9742 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 9743 int found;
270b3042
DV		 9744 dpd_is_edp = intel_dpd_is_edp(dev);
9745
9746 if (has_edp_a(dev))
9747 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 9748
dc0fa718 9749 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 9750 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 9751 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 9752 if (!found)
e2debe91 9753 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 9754 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 9755 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 9756 }
9757
dc0fa718 9758 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 9759 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 9760
dc0fa718 9761 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 9762 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 9763
5eb08b69 9764 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 9765 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 9766
270b3042 9767 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 9768 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 9769 } else if (IS_VALLEYVIEW(dev)) {
19c03924 9770 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
6f6005a5
JB		 9771 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
9772 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
9773 PORT_C);
9774 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9775 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
9776 PORT_C);
9777 }
19c03924 9778
dc0fa718 9779 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 9780 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9781 PORT_B);
67cfc203
VS		 9782 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9783 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 9784 }
3cfca973
JN		 9785
9786 intel_dsi_init(dev);
103a196f 9787 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 9788 bool found = false;
7d57382e 9789
e2debe91 9790 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9791 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 9792 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 9793 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9794 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 9795 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 9796 }
27185ae1 9797
e7281eab 9798 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9799 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 9800 }
13520b05
KH		 9801
9802 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 9803
e2debe91 9804 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9805 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 9806 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 9807 }
27185ae1 9808
e2debe91 9809 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 9810
b01f2c3a
JB		 9811 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9812 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 9813 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 9814 }
e7281eab 9815 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9816 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 9817 }
27185ae1 9818
b01f2c3a 9819 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 9820 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 9821 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 9822 } else if (IS_GEN2(dev))
79e53945
JB		 9823 intel_dvo_init(dev);
9824
103a196f 9825 if (SUPPORTS_TV(dev))
79e53945
JB		 9826 intel_tv_init(dev);
9827
4ef69c7a
CW		 9828 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9829 encoder->base.possible_crtcs = encoder->crtc_mask;
9830 encoder->base.possible_clones =
66a9278e 9831 intel_encoder_clones(encoder);
79e53945 9832 }
47356eb6 9833
dde86e2d 9834 intel_init_pch_refclk(dev);
270b3042
DV		 9835
9836 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 9837}
9838
ddfe1567
CW		 9839void intel_framebuffer_fini(struct intel_framebuffer *fb)
9840{
9841 drm_framebuffer_cleanup(&fb->base);
9842 drm_gem_object_unreference_unlocked(&fb->obj->base);
9843}
9844
79e53945
JB		 9845static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9846{
9847 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 9848
ddfe1567 9849 intel_framebuffer_fini(intel_fb);
79e53945
JB		 9850 kfree(intel_fb);
9851}
9852
9853static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 9854 struct drm_file *file,
79e53945
JB		 9855 unsigned int *handle)
9856{
9857 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 9858 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 9859
05394f39 9860 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 9861}
9862
9863static const struct drm_framebuffer_funcs intel_fb_funcs = {
9864 .destroy = intel_user_framebuffer_destroy,
9865 .create_handle = intel_user_framebuffer_create_handle,
9866};
9867
38651674
DA		 9868int intel_framebuffer_init(struct drm_device *dev,
9869 struct intel_framebuffer *intel_fb,
308e5bcb 9870 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 9871 struct drm_i915_gem_object *obj)
79e53945 9872{
a35cdaa0 9873 int pitch_limit;
79e53945
JB		 9874 int ret;
9875
c16ed4be
CW		 9876 if (obj->tiling_mode == I915_TILING_Y) {
9877 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 9878 return -EINVAL;
c16ed4be 9879 }
57cd6508 9880
c16ed4be
CW		 9881 if (mode_cmd->pitches[0] & 63) {
9882 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9883 mode_cmd->pitches[0]);
57cd6508 9884 return -EINVAL;
c16ed4be 9885 }
57cd6508 9886
a35cdaa0
CW		 9887 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9888 pitch_limit = 32*1024;
9889 } else if (INTEL_INFO(dev)->gen >= 4) {
9890 if (obj->tiling_mode)
9891 pitch_limit = 16*1024;
9892 else
9893 pitch_limit = 32*1024;
9894 } else if (INTEL_INFO(dev)->gen >= 3) {
9895 if (obj->tiling_mode)
9896 pitch_limit = 8*1024;
9897 else
9898 pitch_limit = 16*1024;
9899 } else
9900 /* XXX DSPC is limited to 4k tiled */
9901 pitch_limit = 8*1024;
9902
9903 if (mode_cmd->pitches[0] > pitch_limit) {
9904 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9905 obj->tiling_mode ? "tiled" : "linear",
9906 mode_cmd->pitches[0], pitch_limit);
5d7bd705 9907 return -EINVAL;
c16ed4be 9908 }
5d7bd705
VS		 9909
9910 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 9911 mode_cmd->pitches[0] != obj->stride) {
9912 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9913 mode_cmd->pitches[0], obj->stride);
5d7bd705 9914 return -EINVAL;
c16ed4be 9915 }
5d7bd705 9916
57779d06 9917 /* Reject formats not supported by any plane early. */
308e5bcb 9918 switch (mode_cmd->pixel_format) {
57779d06 9919 case DRM_FORMAT_C8:
04b3924d
VS		 9920 case DRM_FORMAT_RGB565:
9921 case DRM_FORMAT_XRGB8888:
9922 case DRM_FORMAT_ARGB8888:
57779d06
VS		 9923 break;
9924 case DRM_FORMAT_XRGB1555:
9925 case DRM_FORMAT_ARGB1555:
c16ed4be 9926 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 9927 DRM_DEBUG("unsupported pixel format: %s\n",
9928 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9929 return -EINVAL;
c16ed4be 9930 }
57779d06
VS		 9931 break;
9932 case DRM_FORMAT_XBGR8888:
9933 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 9934 case DRM_FORMAT_XRGB2101010:
9935 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 9936 case DRM_FORMAT_XBGR2101010:
9937 case DRM_FORMAT_ABGR2101010:
c16ed4be 9938 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 9939 DRM_DEBUG("unsupported pixel format: %s\n",
9940 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9941 return -EINVAL;
c16ed4be 9942 }
b5626747 9943 break;
04b3924d
VS		 9944 case DRM_FORMAT_YUYV:
9945 case DRM_FORMAT_UYVY:
9946 case DRM_FORMAT_YVYU:
9947 case DRM_FORMAT_VYUY:
c16ed4be 9948 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 9949 DRM_DEBUG("unsupported pixel format: %s\n",
9950 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9951 return -EINVAL;
c16ed4be 9952 }
57cd6508
CW		 9953 break;
9954 default:
4ee62c76
VS		 9955 DRM_DEBUG("unsupported pixel format: %s\n",
9956 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 9957 return -EINVAL;
9958 }
9959
90f9a336
VS		 9960 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9961 if (mode_cmd->offsets[0] != 0)
9962 return -EINVAL;
9963
c7d73f6a
DV		 9964 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9965 intel_fb->obj = obj;
9966
79e53945
JB		 9967 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9968 if (ret) {
9969 DRM_ERROR("framebuffer init failed %d\n", ret);
9970 return ret;
9971 }
9972
79e53945
JB		 9973 return 0;
9974}
9975
79e53945
JB		 9976static struct drm_framebuffer *
9977intel_user_framebuffer_create(struct drm_device *dev,
9978 struct drm_file *filp,
308e5bcb 9979 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 9980{
05394f39 9981 struct drm_i915_gem_object *obj;
79e53945 9982
308e5bcb
JB		 9983 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9984 mode_cmd->handles[0]));
c8725226 9985 if (&obj->base == NULL)
cce13ff7 9986 return ERR_PTR(-ENOENT);
79e53945 9987
d2dff872 9988 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 9989}
9990
79e53945 9991static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 9992 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 9993 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 9994};
9995
e70236a8
JB		 9996/* Set up chip specific display functions */
9997static void intel_init_display(struct drm_device *dev)
9998{
9999 struct drm_i915_private *dev_priv = dev->dev_private;
10000
ee9300bb
DV		 10001 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
10002 dev_priv->display.find_dpll = g4x_find_best_dpll;
10003 else if (IS_VALLEYVIEW(dev))
10004 dev_priv->display.find_dpll = vlv_find_best_dpll;
10005 else if (IS_PINEVIEW(dev))
10006 dev_priv->display.find_dpll = pnv_find_best_dpll;
10007 else
10008 dev_priv->display.find_dpll = i9xx_find_best_dpll;
10009
affa9354 10010 if (HAS_DDI(dev)) {
0e8ffe1b 10011 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 10012 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 10013 dev_priv->display.crtc_enable = haswell_crtc_enable;
10014 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 10015 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 10016 dev_priv->display.update_plane = ironlake_update_plane;
10017 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 10018 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 10019 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 10020 dev_priv->display.crtc_enable = ironlake_crtc_enable;
10021 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 10022 dev_priv->display.off = ironlake_crtc_off;
17638cd6 10023 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 10024 } else if (IS_VALLEYVIEW(dev)) {
10025 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10026 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10027 dev_priv->display.crtc_enable = valleyview_crtc_enable;
10028 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10029 dev_priv->display.off = i9xx_crtc_off;
10030 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 10031 } else {
0e8ffe1b 10032 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 10033 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 10034 dev_priv->display.crtc_enable = i9xx_crtc_enable;
10035 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 10036 dev_priv->display.off = i9xx_crtc_off;
17638cd6 10037 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 10038 }
e70236a8 10039
e70236a8 10040 /* Returns the core display clock speed */
25eb05fc
JB		 10041 if (IS_VALLEYVIEW(dev))
10042 dev_priv->display.get_display_clock_speed =
10043 valleyview_get_display_clock_speed;
10044 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 10045 dev_priv->display.get_display_clock_speed =
10046 i945_get_display_clock_speed;
10047 else if (IS_I915G(dev))
10048 dev_priv->display.get_display_clock_speed =
10049 i915_get_display_clock_speed;
257a7ffc 10050 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 10051 dev_priv->display.get_display_clock_speed =
10052 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 10053 else if (IS_PINEVIEW(dev))
10054 dev_priv->display.get_display_clock_speed =
10055 pnv_get_display_clock_speed;
e70236a8
JB		 10056 else if (IS_I915GM(dev))
10057 dev_priv->display.get_display_clock_speed =
10058 i915gm_get_display_clock_speed;
10059 else if (IS_I865G(dev))
10060 dev_priv->display.get_display_clock_speed =
10061 i865_get_display_clock_speed;
f0f8a9ce 10062 else if (IS_I85X(dev))
e70236a8
JB		 10063 dev_priv->display.get_display_clock_speed =
10064 i855_get_display_clock_speed;
10065 else /* 852, 830 */
10066 dev_priv->display.get_display_clock_speed =
10067 i830_get_display_clock_speed;
10068
7f8a8569 10069 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 10070 if (IS_GEN5(dev)) {
674cf967 10071 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 10072 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 10073 } else if (IS_GEN6(dev)) {
674cf967 10074 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 10075 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 10076 } else if (IS_IVYBRIDGE(dev)) {
10077 /* FIXME: detect B0+ stepping and use auto training */
10078 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 10079 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 10080 dev_priv->display.modeset_global_resources =
10081 ivb_modeset_global_resources;
c82e4d26
ED		 10082 } else if (IS_HASWELL(dev)) {
10083 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 10084 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 10085 dev_priv->display.modeset_global_resources =
10086 haswell_modeset_global_resources;
a0e63c22 10087 }
6067aaea 10088 } else if (IS_G4X(dev)) {
e0dac65e 10089 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 10090 }
8c9f3aaf
JB		 10091
10092 /* Default just returns -ENODEV to indicate unsupported */
10093 dev_priv->display.queue_flip = intel_default_queue_flip;
10094
10095 switch (INTEL_INFO(dev)->gen) {
10096 case 2:
10097 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10098 break;
10099
10100 case 3:
10101 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10102 break;
10103
10104 case 4:
10105 case 5:
10106 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10107 break;
10108
10109 case 6:
10110 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10111 break;
7c9017e5
JB		 10112 case 7:
10113 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10114 break;
8c9f3aaf 10115 }
e70236a8
JB		 10116}
10117
b690e96c
JB		 10118/*
10119 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10120 * resume, or other times. This quirk makes sure that's the case for
10121 * affected systems.
10122 */
0206e353 10123static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 10124{
10125 struct drm_i915_private *dev_priv = dev->dev_private;
10126
10127 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 10128 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 10129}
10130
435793df
KP		 10131/*
10132 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10133 */
10134static void quirk_ssc_force_disable(struct drm_device *dev)
10135{
10136 struct drm_i915_private *dev_priv = dev->dev_private;
10137 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 10138 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 10139}
10140
4dca20ef 10141/*
5a15ab5b
CE		 10142 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10143 * brightness value
4dca20ef
CE		 10144 */
10145static void quirk_invert_brightness(struct drm_device *dev)
10146{
10147 struct drm_i915_private *dev_priv = dev->dev_private;
10148 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 10149 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 10150}
10151
e85843be
KM		 10152/*
10153 * Some machines (Dell XPS13) suffer broken backlight controls if
10154 * BLM_PCH_PWM_ENABLE is set.
10155 */
10156static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
10157{
10158 struct drm_i915_private *dev_priv = dev->dev_private;
10159 dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
10160 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
10161}
10162
b690e96c
JB		 10163struct intel_quirk {
10164 int device;
10165 int subsystem_vendor;
10166 int subsystem_device;
10167 void (*hook)(struct drm_device *dev);
10168};
10169
5f85f176
EE		 10170/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10171struct intel_dmi_quirk {
10172 void (*hook)(struct drm_device *dev);
10173 const struct dmi_system_id (*dmi_id_list)[];
10174};
10175
10176static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10177{
10178 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10179 return 1;
10180}
10181
10182static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10183 {
10184 .dmi_id_list = &(const struct dmi_system_id[]) {
10185 {
10186 .callback = intel_dmi_reverse_brightness,
10187 .ident = "NCR Corporation",
10188 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10189 DMI_MATCH(DMI_PRODUCT_NAME, ""),
10190 },
10191 },
10192 { } /* terminating entry */
10193 },
10194 .hook = quirk_invert_brightness,
10195 },
10196};
10197
c43b5634 10198static struct intel_quirk intel_quirks[] = {
b690e96c 10199 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 10200 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 10201
b690e96c
JB		 10202 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10203 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10204
b690e96c
JB		 10205 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10206 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10207
ccd0d36e 10208 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 10209 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 10210 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 10211
10212 /* Lenovo U160 cannot use SSC on LVDS */
10213 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 10214
10215 /* Sony Vaio Y cannot use SSC on LVDS */
10216 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 10217
ee1452d7
JN		 10218 /*
10219 * All GM45 Acer (and its brands eMachines and Packard Bell) laptops
10220 * seem to use inverted backlight PWM.
10221 */
10222 { 0x2a42, 0x1025, PCI_ANY_ID, quirk_invert_brightness },
e85843be
KM		 10223
10224 /* Dell XPS13 HD Sandy Bridge */
10225 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10226 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10227 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
b690e96c
JB		 10228};
10229
10230static void intel_init_quirks(struct drm_device *dev)
10231{
10232 struct pci_dev *d = dev->pdev;
10233 int i;
10234
10235 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10236 struct intel_quirk *q = &intel_quirks[i];
10237
10238 if (d->device == q->device &&
10239 (d->subsystem_vendor == q->subsystem_vendor ||
10240 q->subsystem_vendor == PCI_ANY_ID) &&
10241 (d->subsystem_device == q->subsystem_device ||
10242 q->subsystem_device == PCI_ANY_ID))
10243 q->hook(dev);
10244 }
5f85f176
EE		 10245 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10246 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10247 intel_dmi_quirks[i].hook(dev);
10248 }
b690e96c
JB		 10249}
10250
9cce37f4
JB		 10251/* Disable the VGA plane that we never use */
10252static void i915_disable_vga(struct drm_device *dev)
10253{
10254 struct drm_i915_private *dev_priv = dev->dev_private;
10255 u8 sr1;
766aa1c4 10256 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 10257
10258 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 10259 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 10260 sr1 = inb(VGA_SR_DATA);
10261 outb(sr1 | 1<<5, VGA_SR_DATA);
10262 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10263 udelay(300);
10264
10265 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10266 POSTING_READ(vga_reg);
10267}
10268
6e1b4fda 10269static void i915_enable_vga_mem(struct drm_device *dev)
81b5c7bc
AW		 10270{
10271 /* Enable VGA memory on Intel HD */
10272 if (HAS_PCH_SPLIT(dev)) {
10273 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10274 outb(inb(VGA_MSR_READ) | VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10275 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10276 VGA_RSRC_LEGACY_MEM |
10277 VGA_RSRC_NORMAL_IO |
10278 VGA_RSRC_NORMAL_MEM);
10279 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10280 }
10281}
10282
6e1b4fda
VS		 10283void i915_disable_vga_mem(struct drm_device *dev)
10284{
10285 /* Disable VGA memory on Intel HD */
10286 if (HAS_PCH_SPLIT(dev)) {
10287 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10288 outb(inb(VGA_MSR_READ) & ~VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10289 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10290 VGA_RSRC_NORMAL_IO |
10291 VGA_RSRC_NORMAL_MEM);
10292 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10293 }
10294}
10295
f817586c
DV		 10296void intel_modeset_init_hw(struct drm_device *dev)
10297{
f6071166
JB		 10298 struct drm_i915_private *dev_priv = dev->dev_private;
10299
a8f78b58
ED		 10300 intel_prepare_ddi(dev);
10301
f817586c
DV		 10302 intel_init_clock_gating(dev);
10303
f6071166
JB		 10304 /* Enable the CRI clock source so we can get at the display */
10305 if (IS_VALLEYVIEW(dev))
10306 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
10307 DPLL_INTEGRATED_CRI_CLK_VLV);
10308
79f5b2c7 10309 mutex_lock(&dev->struct_mutex);
8090c6b9 10310 intel_enable_gt_powersave(dev);
79f5b2c7 10311 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 10312}
10313
7d708ee4
ID		 10314void intel_modeset_suspend_hw(struct drm_device *dev)
10315{
10316 intel_suspend_hw(dev);
10317}
10318
79e53945
JB		 10319void intel_modeset_init(struct drm_device *dev)
10320{
652c393a 10321 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 10322 int i, j, ret;
79e53945
JB		 10323
10324 drm_mode_config_init(dev);
10325
10326 dev->mode_config.min_width = 0;
10327 dev->mode_config.min_height = 0;
10328
019d96cb
DA		 10329 dev->mode_config.preferred_depth = 24;
10330 dev->mode_config.prefer_shadow = 1;
10331
e6ecefaa 10332 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 10333
b690e96c
JB		 10334 intel_init_quirks(dev);
10335
1fa61106
ED		 10336 intel_init_pm(dev);
10337
e3c74757
BW		 10338 if (INTEL_INFO(dev)->num_pipes == 0)
10339 return;
10340
e70236a8
JB		 10341 intel_init_display(dev);
10342
a6c45cf0
CW		 10343 if (IS_GEN2(dev)) {
10344 dev->mode_config.max_width = 2048;
10345 dev->mode_config.max_height = 2048;
10346 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 10347 dev->mode_config.max_width = 4096;
10348 dev->mode_config.max_height = 4096;
79e53945 10349 } else {
a6c45cf0
CW		 10350 dev->mode_config.max_width = 8192;
10351 dev->mode_config.max_height = 8192;
79e53945 10352 }
5d4545ae 10353 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 10354
28c97730 10355 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 10356 INTEL_INFO(dev)->num_pipes,
10357 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 10358
08e2a7de 10359 for_each_pipe(i) {
79e53945 10360 intel_crtc_init(dev, i);
7f1f3851
JB		 10361 for (j = 0; j < dev_priv->num_plane; j++) {
10362 ret = intel_plane_init(dev, i, j);
10363 if (ret)
06da8da2
VS		 10364 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10365 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 10366 }
79e53945
JB		 10367 }
10368
79f689aa 10369 intel_cpu_pll_init(dev);
e72f9fbf 10370 intel_shared_dpll_init(dev);
ee7b9f93 10371
9cce37f4
JB		 10372 /* Just disable it once at startup */
10373 i915_disable_vga(dev);
79e53945 10374 intel_setup_outputs(dev);
11be49eb
CW		 10375
10376 /* Just in case the BIOS is doing something questionable. */
10377 intel_disable_fbc(dev);
2c7111db
CW		 10378}
10379
24929352
DV		 10380static void
10381intel_connector_break_all_links(struct intel_connector *connector)
10382{
10383 connector->base.dpms = DRM_MODE_DPMS_OFF;
10384 connector->base.encoder = NULL;
10385 connector->encoder->connectors_active = false;
10386 connector->encoder->base.crtc = NULL;
10387}
10388
7fad798e
DV		 10389static void intel_enable_pipe_a(struct drm_device *dev)
10390{
10391 struct intel_connector *connector;
10392 struct drm_connector *crt = NULL;
10393 struct intel_load_detect_pipe load_detect_temp;
10394
10395 /* We can't just switch on the pipe A, we need to set things up with a
10396 * proper mode and output configuration. As a gross hack, enable pipe A
10397 * by enabling the load detect pipe once. */
10398 list_for_each_entry(connector,
10399 &dev->mode_config.connector_list,
10400 base.head) {
10401 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10402 crt = &connector->base;
10403 break;
10404 }
10405 }
10406
10407 if (!crt)
10408 return;
10409
10410 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10411 intel_release_load_detect_pipe(crt, &load_detect_temp);
10412
652c393a 10413
7fad798e
DV		 10414}
10415
fa555837
DV		 10416static bool
10417intel_check_plane_mapping(struct intel_crtc *crtc)
10418{
7eb552ae
BW		 10419 struct drm_device *dev = crtc->base.dev;
10420 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 10421 u32 reg, val;
10422
7eb552ae 10423 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 10424 return true;
10425
10426 reg = DSPCNTR(!crtc->plane);
10427 val = I915_READ(reg);
10428
10429 if ((val & DISPLAY_PLANE_ENABLE) &&
10430 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10431 return false;
10432
10433 return true;
10434}
10435
24929352
DV		 10436static void intel_sanitize_crtc(struct intel_crtc *crtc)
10437{
10438 struct drm_device *dev = crtc->base.dev;
10439 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 10440 u32 reg;
24929352 10441
24929352 10442 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 10443 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 10444 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10445
10446 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 10447 * disable the crtc (and hence change the state) if it is wrong. Note
10448 * that gen4+ has a fixed plane -> pipe mapping. */
10449 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 10450 struct intel_connector *connector;
10451 bool plane;
10452
24929352
DV		 10453 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10454 crtc->base.base.id);
10455
10456 /* Pipe has the wrong plane attached and the plane is active.
10457 * Temporarily change the plane mapping and disable everything
10458 * ... */
10459 plane = crtc->plane;
10460 crtc->plane = !plane;
10461 dev_priv->display.crtc_disable(&crtc->base);
10462 crtc->plane = plane;
10463
10464 /* ... and break all links. */
10465 list_for_each_entry(connector, &dev->mode_config.connector_list,
10466 base.head) {
10467 if (connector->encoder->base.crtc != &crtc->base)
10468 continue;
10469
10470 intel_connector_break_all_links(connector);
10471 }
10472
10473 WARN_ON(crtc->active);
10474 crtc->base.enabled = false;
10475 }
24929352 10476
7fad798e
DV		 10477 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10478 crtc->pipe == PIPE_A && !crtc->active) {
10479 /* BIOS forgot to enable pipe A, this mostly happens after
10480 * resume. Force-enable the pipe to fix this, the update_dpms
10481 * call below we restore the pipe to the right state, but leave
10482 * the required bits on. */
10483 intel_enable_pipe_a(dev);
10484 }
10485
24929352
DV		 10486 /* Adjust the state of the output pipe according to whether we
10487 * have active connectors/encoders. */
10488 intel_crtc_update_dpms(&crtc->base);
10489
10490 if (crtc->active != crtc->base.enabled) {
10491 struct intel_encoder *encoder;
10492
10493 /* This can happen either due to bugs in the get_hw_state
10494 * functions or because the pipe is force-enabled due to the
10495 * pipe A quirk. */
10496 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10497 crtc->base.base.id,
10498 crtc->base.enabled ? "enabled" : "disabled",
10499 crtc->active ? "enabled" : "disabled");
10500
10501 crtc->base.enabled = crtc->active;
10502
10503 /* Because we only establish the connector -> encoder ->
10504 * crtc links if something is active, this means the
10505 * crtc is now deactivated. Break the links. connector
10506 * -> encoder links are only establish when things are
10507 * actually up, hence no need to break them. */
10508 WARN_ON(crtc->active);
10509
10510 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10511 WARN_ON(encoder->connectors_active);
10512 encoder->base.crtc = NULL;
10513 }
10514 }
10515}
10516
10517static void intel_sanitize_encoder(struct intel_encoder *encoder)
10518{
10519 struct intel_connector *connector;
10520 struct drm_device *dev = encoder->base.dev;
10521
10522 /* We need to check both for a crtc link (meaning that the
10523 * encoder is active and trying to read from a pipe) and the
10524 * pipe itself being active. */
10525 bool has_active_crtc = encoder->base.crtc &&
10526 to_intel_crtc(encoder->base.crtc)->active;
10527
10528 if (encoder->connectors_active && !has_active_crtc) {
10529 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10530 encoder->base.base.id,
10531 drm_get_encoder_name(&encoder->base));
10532
10533 /* Connector is active, but has no active pipe. This is
10534 * fallout from our resume register restoring. Disable
10535 * the encoder manually again. */
10536 if (encoder->base.crtc) {
10537 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10538 encoder->base.base.id,
10539 drm_get_encoder_name(&encoder->base));
10540 encoder->disable(encoder);
10541 }
10542
10543 /* Inconsistent output/port/pipe state happens presumably due to
10544 * a bug in one of the get_hw_state functions. Or someplace else
10545 * in our code, like the register restore mess on resume. Clamp
10546 * things to off as a safer default. */
10547 list_for_each_entry(connector,
10548 &dev->mode_config.connector_list,
10549 base.head) {
10550 if (connector->encoder != encoder)
10551 continue;
10552
10553 intel_connector_break_all_links(connector);
10554 }
10555 }
10556 /* Enabled encoders without active connectors will be fixed in
10557 * the crtc fixup. */
10558}
10559
44cec740 10560void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 10561{
10562 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 10563 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 10564
8dc8a27c
PZ		 10565 /* This function can be called both from intel_modeset_setup_hw_state or
10566 * at a very early point in our resume sequence, where the power well
10567 * structures are not yet restored. Since this function is at a very
10568 * paranoid "someone might have enabled VGA while we were not looking"
10569 * level, just check if the power well is enabled instead of trying to
10570 * follow the "don't touch the power well if we don't need it" policy
10571 * the rest of the driver uses. */
10572 if (HAS_POWER_WELL(dev) &&
6aedd1f5 10573 (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
8dc8a27c
PZ		 10574 return;
10575
0fde901f
KM		 10576 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
10577 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 10578 i915_disable_vga(dev);
6e1b4fda 10579 i915_disable_vga_mem(dev);
0fde901f
KM		 10580 }
10581}
10582
30e984df 10583static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 10584{
10585 struct drm_i915_private *dev_priv = dev->dev_private;
10586 enum pipe pipe;
24929352
DV		 10587 struct intel_crtc *crtc;
10588 struct intel_encoder *encoder;
10589 struct intel_connector *connector;
5358901f 10590 int i;
24929352 10591
0e8ffe1b
DV		 10592 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10593 base.head) {
88adfff1 10594 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 10595
0e8ffe1b
DV		 10596 crtc->active = dev_priv->display.get_pipe_config(crtc,
10597 &crtc->config);
24929352
DV		 10598
10599 crtc->base.enabled = crtc->active;
10600
10601 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10602 crtc->base.base.id,
10603 crtc->active ? "enabled" : "disabled");
10604 }
10605
5358901f 10606 /* FIXME: Smash this into the new shared dpll infrastructure. */
affa9354 10607 if (HAS_DDI(dev))
6441ab5f
PZ		 10608 intel_ddi_setup_hw_pll_state(dev);
10609
5358901f
DV		 10610 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10611 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10612
10613 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10614 pll->active = 0;
10615 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10616 base.head) {
10617 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10618 pll->active++;
10619 }
10620 pll->refcount = pll->active;
10621
35c95375
DV		 10622 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10623 pll->name, pll->refcount, pll->on);
5358901f
DV		 10624 }
10625
24929352
DV		 10626 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10627 base.head) {
10628 pipe = 0;
10629
10630 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 10631 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10632 encoder->base.crtc = &crtc->base;
510d5f2f 10633 if (encoder->get_config)
045ac3b5 10634 encoder->get_config(encoder, &crtc->config);
24929352
DV		 10635 } else {
10636 encoder->base.crtc = NULL;
10637 }
10638
10639 encoder->connectors_active = false;
10640 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10641 encoder->base.base.id,
10642 drm_get_encoder_name(&encoder->base),
10643 encoder->base.crtc ? "enabled" : "disabled",
10644 pipe);
10645 }
10646
10647 list_for_each_entry(connector, &dev->mode_config.connector_list,
10648 base.head) {
10649 if (connector->get_hw_state(connector)) {
10650 connector->base.dpms = DRM_MODE_DPMS_ON;
10651 connector->encoder->connectors_active = true;
10652 connector->base.encoder = &connector->encoder->base;
10653 } else {
10654 connector->base.dpms = DRM_MODE_DPMS_OFF;
10655 connector->base.encoder = NULL;
10656 }
10657 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10658 connector->base.base.id,
10659 drm_get_connector_name(&connector->base),
10660 connector->base.encoder ? "enabled" : "disabled");
10661 }
30e984df
DV		 10662}
10663
10664/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10665 * and i915 state tracking structures. */
10666void intel_modeset_setup_hw_state(struct drm_device *dev,
10667 bool force_restore)
10668{
10669 struct drm_i915_private *dev_priv = dev->dev_private;
10670 enum pipe pipe;
30e984df
DV		 10671 struct intel_crtc *crtc;
10672 struct intel_encoder *encoder;
35c95375 10673 int i;
30e984df
DV		 10674
10675 intel_modeset_readout_hw_state(dev);
24929352 10676
babea61d
JB		 10677 /*
10678 * Now that we have the config, copy it to each CRTC struct
10679 * Note that this could go away if we move to using crtc_config
10680 * checking everywhere.
10681 */
10682 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10683 base.head) {
10684 if (crtc->active && i915_fastboot) {
10685 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10686
10687 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10688 crtc->base.base.id);
10689 drm_mode_debug_printmodeline(&crtc->base.mode);
10690 }
10691 }
10692
24929352
DV		 10693 /* HW state is read out, now we need to sanitize this mess. */
10694 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10695 base.head) {
10696 intel_sanitize_encoder(encoder);
10697 }
10698
10699 for_each_pipe(pipe) {
10700 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10701 intel_sanitize_crtc(crtc);
c0b03411 10702 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 10703 }
9a935856 10704
35c95375
DV		 10705 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10706 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10707
10708 if (!pll->on || pll->active)
10709 continue;
10710
10711 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10712
10713 pll->disable(dev_priv, pll);
10714 pll->on = false;
10715 }
10716
45e2b5f6 10717 if (force_restore) {
7d0bc1ea
VS		 10718 i915_redisable_vga(dev);
10719
f30da187
DV		 10720 /*
10721 * We need to use raw interfaces for restoring state to avoid
10722 * checking (bogus) intermediate states.
10723 */
45e2b5f6 10724 for_each_pipe(pipe) {
b5644d05
JB		 10725 struct drm_crtc *crtc =
10726 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 10727
10728 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10729 crtc->fb);
45e2b5f6
DV		 10730 }
10731 } else {
10732 intel_modeset_update_staged_output_state(dev);
10733 }
8af6cf88
DV		 10734
10735 intel_modeset_check_state(dev);
2e938892
DV		 10736
10737 drm_mode_config_reset(dev);
2c7111db
CW		 10738}
10739
10740void intel_modeset_gem_init(struct drm_device *dev)
10741{
1833b134 10742 intel_modeset_init_hw(dev);
02e792fb
DV		 10743
10744 intel_setup_overlay(dev);
24929352 10745
45e2b5f6 10746 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 10747}
10748
10749void intel_modeset_cleanup(struct drm_device *dev)
10750{
652c393a
JB		 10751 struct drm_i915_private *dev_priv = dev->dev_private;
10752 struct drm_crtc *crtc;
d9255d57 10753 struct drm_connector *connector;
652c393a 10754
fd0c0642
DV		 10755 /*
10756 * Interrupts and polling as the first thing to avoid creating havoc.
10757 * Too much stuff here (turning of rps, connectors, ...) would
10758 * experience fancy races otherwise.
10759 */
10760 drm_irq_uninstall(dev);
10761 cancel_work_sync(&dev_priv->hotplug_work);
10762 /*
10763 * Due to the hpd irq storm handling the hotplug work can re-arm the
10764 * poll handlers. Hence disable polling after hpd handling is shut down.
10765 */
f87ea761 10766 drm_kms_helper_poll_fini(dev);
fd0c0642 10767
652c393a
JB		 10768 mutex_lock(&dev->struct_mutex);
10769
723bfd70
JB		 10770 intel_unregister_dsm_handler();
10771
652c393a
JB		 10772 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10773 /* Skip inactive CRTCs */
10774 if (!crtc->fb)
10775 continue;
10776
3dec0095 10777 intel_increase_pllclock(crtc);
652c393a
JB		 10778 }
10779
973d04f9 10780 intel_disable_fbc(dev);
e70236a8 10781
6e1b4fda 10782 i915_enable_vga_mem(dev);
81b5c7bc 10783
8090c6b9 10784 intel_disable_gt_powersave(dev);
0cdab21f 10785
930ebb46
DV		 10786 ironlake_teardown_rc6(dev);
10787
69341a5e
KH		 10788 mutex_unlock(&dev->struct_mutex);
10789
1630fe75
CW		 10790 /* flush any delayed tasks or pending work */
10791 flush_scheduled_work();
10792
dc652f90
JN		 10793 /* destroy backlight, if any, before the connectors */
10794 intel_panel_destroy_backlight(dev);
10795
d9255d57
PZ		 10796 /* destroy the sysfs files before encoders/connectors */
10797 list_for_each_entry(connector, &dev->mode_config.connector_list, head)
10798 drm_sysfs_connector_remove(connector);
10799
79e53945 10800 drm_mode_config_cleanup(dev);
4d7bb011
DV		 10801
10802 intel_cleanup_overlay(dev);
79e53945
JB		 10803}
10804
f1c79df3
ZW		 10805/*
10806 * Return which encoder is currently attached for connector.
10807 */
df0e9248 10808struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 10809{
df0e9248
CW		 10810 return &intel_attached_encoder(connector)->base;
10811}
f1c79df3 10812
df0e9248
CW		 10813void intel_connector_attach_encoder(struct intel_connector *connector,
10814 struct intel_encoder *encoder)
10815{
10816 connector->encoder = encoder;
10817 drm_mode_connector_attach_encoder(&connector->base,
10818 &encoder->base);
79e53945 10819}
28d52043
DA		 10820
10821/*
10822 * set vga decode state - true == enable VGA decode
10823 */
10824int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10825{
10826 struct drm_i915_private *dev_priv = dev->dev_private;
10827 u16 gmch_ctrl;
10828
10829 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10830 if (state)
10831 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10832 else
10833 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10834 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10835 return 0;
10836}
c4a1d9e4 10837
c4a1d9e4 10838struct intel_display_error_state {
ff57f1b0
PZ		 10839
10840 u32 power_well_driver;
10841
63b66e5b
CW		 10842 int num_transcoders;
10843
c4a1d9e4
CW		 10844 struct intel_cursor_error_state {
10845 u32 control;
10846 u32 position;
10847 u32 base;
10848 u32 size;
52331309 10849 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 10850
10851 struct intel_pipe_error_state {
c4a1d9e4 10852 u32 source;
52331309 10853 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 10854
10855 struct intel_plane_error_state {
10856 u32 control;
10857 u32 stride;
10858 u32 size;
10859 u32 pos;
10860 u32 addr;
10861 u32 surface;
10862 u32 tile_offset;
52331309 10863 } plane[I915_MAX_PIPES];
63b66e5b
CW		 10864
10865 struct intel_transcoder_error_state {
10866 enum transcoder cpu_transcoder;
10867
10868 u32 conf;
10869
10870 u32 htotal;
10871 u32 hblank;
10872 u32 hsync;
10873 u32 vtotal;
10874 u32 vblank;
10875 u32 vsync;
10876 } transcoder[4];
c4a1d9e4
CW		 10877};
10878
10879struct intel_display_error_state *
10880intel_display_capture_error_state(struct drm_device *dev)
10881{
0206e353 10882 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 10883 struct intel_display_error_state *error;
63b66e5b
CW		 10884 int transcoders[] = {
10885 TRANSCODER_A,
10886 TRANSCODER_B,
10887 TRANSCODER_C,
10888 TRANSCODER_EDP,
10889 };
c4a1d9e4
CW		 10890 int i;
10891
63b66e5b
CW		 10892 if (INTEL_INFO(dev)->num_pipes == 0)
10893 return NULL;
10894
c4a1d9e4
CW		 10895 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10896 if (error == NULL)
10897 return NULL;
10898
ff57f1b0
PZ		 10899 if (HAS_POWER_WELL(dev))
10900 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10901
52331309 10902 for_each_pipe(i) {
a18c4c3d
PZ		 10903 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10904 error->cursor[i].control = I915_READ(CURCNTR(i));
10905 error->cursor[i].position = I915_READ(CURPOS(i));
10906 error->cursor[i].base = I915_READ(CURBASE(i));
10907 } else {
10908 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10909 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10910 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10911 }
c4a1d9e4
CW		 10912
10913 error->plane[i].control = I915_READ(DSPCNTR(i));
10914 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 10915 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 10916 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 10917 error->plane[i].pos = I915_READ(DSPPOS(i));
10918 }
ca291363
PZ		 10919 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10920 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 10921 if (INTEL_INFO(dev)->gen >= 4) {
10922 error->plane[i].surface = I915_READ(DSPSURF(i));
10923 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10924 }
10925
c4a1d9e4 10926 error->pipe[i].source = I915_READ(PIPESRC(i));
63b66e5b
CW		 10927 }
10928
10929 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
10930 if (HAS_DDI(dev_priv->dev))
10931 error->num_transcoders++; /* Account for eDP. */
10932
10933 for (i = 0; i < error->num_transcoders; i++) {
10934 enum transcoder cpu_transcoder = transcoders[i];
10935
10936 error->transcoder[i].cpu_transcoder = cpu_transcoder;
10937
10938 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10939 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10940 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10941 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10942 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10943 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10944 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 10945 }
10946
12d217c7
PZ		 10947 /* In the code above we read the registers without checking if the power
10948 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10949 * prevent the next I915_WRITE from detecting it and printing an error
10950 * message. */
907b28c5 10951 intel_uncore_clear_errors(dev);
12d217c7 10952
c4a1d9e4
CW		 10953 return error;
10954}
10955
edc3d884
MK		 10956#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10957
c4a1d9e4 10958void
edc3d884 10959intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 10960 struct drm_device *dev,
10961 struct intel_display_error_state *error)
10962{
10963 int i;
10964
63b66e5b
CW		 10965 if (!error)
10966 return;
10967
edc3d884 10968 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 10969 if (HAS_POWER_WELL(dev))
edc3d884 10970 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 10971 error->power_well_driver);
52331309 10972 for_each_pipe(i) {
edc3d884 10973 err_printf(m, "Pipe [%d]:\n", i);
edc3d884 10974 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
edc3d884
MK		 10975
10976 err_printf(m, "Plane [%d]:\n", i);
10977 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
10978 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 10979 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 10980 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
10981 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 10982 }
4b71a570 10983 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 10984 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 10985 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 10986 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
10987 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 10988 }
10989
edc3d884
MK		 10990 err_printf(m, "Cursor [%d]:\n", i);
10991 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
10992 err_printf(m, " POS: %08x\n", error->cursor[i].position);
10993 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 10994 }
63b66e5b
CW		 10995
10996 for (i = 0; i < error->num_transcoders; i++) {
10997 err_printf(m, " CPU transcoder: %c\n",
10998 transcoder_name(error->transcoder[i].cpu_transcoder));
10999 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
11000 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
11001 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
11002 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
11003 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
11004 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
11005 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
11006 }
c4a1d9e4 11007}
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