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drm/i915: disable sdvo pixel multiplier cross-check for HAS_PCH_SPLIT
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
79e53945 48typedef struct {
0206e353 49 int min, max;
79e53945
JB		 50} intel_range_t;
51
52typedef struct {
0206e353
AJ		 53 int dot_limit;
54 int p2_slow, p2_fast;
79e53945
JB		 55} intel_p2_t;
56
57#define INTEL_P2_NUM 2
d4906093
ML		 58typedef struct intel_limit intel_limit_t;
59struct intel_limit {
0206e353
AJ		 60 intel_range_t dot, vco, n, m, m1, m2, p, p1;
61 intel_p2_t p2;
d4906093 62};
79e53945 63
2377b741
JB		 64/* FDI */
65#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
66
d2acd215
DV		 67int
68intel_pch_rawclk(struct drm_device *dev)
69{
70 struct drm_i915_private *dev_priv = dev->dev_private;
71
72 WARN_ON(!HAS_PCH_SPLIT(dev));
73
74 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
75}
76
021357ac
CW		 77static inline u32 /* units of 100MHz */
78intel_fdi_link_freq(struct drm_device *dev)
79{
8b99e68c
CW		 80 if (IS_GEN5(dev)) {
81 struct drm_i915_private *dev_priv = dev->dev_private;
82 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
83 } else
84 return 27;
021357ac
CW		 85}
86
e4b36699 87static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 88 .dot = { .min = 25000, .max = 350000 },
89 .vco = { .min = 930000, .max = 1400000 },
90 .n = { .min = 3, .max = 16 },
91 .m = { .min = 96, .max = 140 },
92 .m1 = { .min = 18, .max = 26 },
93 .m2 = { .min = 6, .max = 16 },
94 .p = { .min = 4, .max = 128 },
95 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 96 .p2 = { .dot_limit = 165000,
97 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 98};
99
100static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 101 .dot = { .min = 25000, .max = 350000 },
102 .vco = { .min = 930000, .max = 1400000 },
103 .n = { .min = 3, .max = 16 },
104 .m = { .min = 96, .max = 140 },
105 .m1 = { .min = 18, .max = 26 },
106 .m2 = { .min = 6, .max = 16 },
107 .p = { .min = 4, .max = 128 },
108 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 109 .p2 = { .dot_limit = 165000,
110 .p2_slow = 14, .p2_fast = 7 },
e4b36699 111};
273e27ca 112
e4b36699 113static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 114 .dot = { .min = 20000, .max = 400000 },
115 .vco = { .min = 1400000, .max = 2800000 },
116 .n = { .min = 1, .max = 6 },
117 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 118 .m1 = { .min = 8, .max = 18 },
119 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 120 .p = { .min = 5, .max = 80 },
121 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 122 .p2 = { .dot_limit = 200000,
123 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 124};
125
126static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 127 .dot = { .min = 20000, .max = 400000 },
128 .vco = { .min = 1400000, .max = 2800000 },
129 .n = { .min = 1, .max = 6 },
130 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 131 .m1 = { .min = 8, .max = 18 },
132 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 133 .p = { .min = 7, .max = 98 },
134 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 135 .p2 = { .dot_limit = 112000,
136 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 137};
138
273e27ca 139
e4b36699 140static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 141 .dot = { .min = 25000, .max = 270000 },
142 .vco = { .min = 1750000, .max = 3500000},
143 .n = { .min = 1, .max = 4 },
144 .m = { .min = 104, .max = 138 },
145 .m1 = { .min = 17, .max = 23 },
146 .m2 = { .min = 5, .max = 11 },
147 .p = { .min = 10, .max = 30 },
148 .p1 = { .min = 1, .max = 3},
149 .p2 = { .dot_limit = 270000,
150 .p2_slow = 10,
151 .p2_fast = 10
044c7c41 152 },
e4b36699
KP		 153};
154
155static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 156 .dot = { .min = 22000, .max = 400000 },
157 .vco = { .min = 1750000, .max = 3500000},
158 .n = { .min = 1, .max = 4 },
159 .m = { .min = 104, .max = 138 },
160 .m1 = { .min = 16, .max = 23 },
161 .m2 = { .min = 5, .max = 11 },
162 .p = { .min = 5, .max = 80 },
163 .p1 = { .min = 1, .max = 8},
164 .p2 = { .dot_limit = 165000,
165 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 166};
167
168static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 169 .dot = { .min = 20000, .max = 115000 },
170 .vco = { .min = 1750000, .max = 3500000 },
171 .n = { .min = 1, .max = 3 },
172 .m = { .min = 104, .max = 138 },
173 .m1 = { .min = 17, .max = 23 },
174 .m2 = { .min = 5, .max = 11 },
175 .p = { .min = 28, .max = 112 },
176 .p1 = { .min = 2, .max = 8 },
177 .p2 = { .dot_limit = 0,
178 .p2_slow = 14, .p2_fast = 14
044c7c41 179 },
e4b36699
KP		 180};
181
182static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 183 .dot = { .min = 80000, .max = 224000 },
184 .vco = { .min = 1750000, .max = 3500000 },
185 .n = { .min = 1, .max = 3 },
186 .m = { .min = 104, .max = 138 },
187 .m1 = { .min = 17, .max = 23 },
188 .m2 = { .min = 5, .max = 11 },
189 .p = { .min = 14, .max = 42 },
190 .p1 = { .min = 2, .max = 6 },
191 .p2 = { .dot_limit = 0,
192 .p2_slow = 7, .p2_fast = 7
044c7c41 193 },
e4b36699
KP		 194};
195
f2b115e6 196static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 197 .dot = { .min = 20000, .max = 400000},
198 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 199 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 200 .n = { .min = 3, .max = 6 },
201 .m = { .min = 2, .max = 256 },
273e27ca 202 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 203 .m1 = { .min = 0, .max = 0 },
204 .m2 = { .min = 0, .max = 254 },
205 .p = { .min = 5, .max = 80 },
206 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 207 .p2 = { .dot_limit = 200000,
208 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 209};
210
f2b115e6 211static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 212 .dot = { .min = 20000, .max = 400000 },
213 .vco = { .min = 1700000, .max = 3500000 },
214 .n = { .min = 3, .max = 6 },
215 .m = { .min = 2, .max = 256 },
216 .m1 = { .min = 0, .max = 0 },
217 .m2 = { .min = 0, .max = 254 },
218 .p = { .min = 7, .max = 112 },
219 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 220 .p2 = { .dot_limit = 112000,
221 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 222};
223
273e27ca
EA		 224/* Ironlake / Sandybridge
225 *
226 * We calculate clock using (register_value + 2) for N/M1/M2, so here
227 * the range value for them is (actual_value - 2).
228 */
b91ad0ec 229static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 230 .dot = { .min = 25000, .max = 350000 },
231 .vco = { .min = 1760000, .max = 3510000 },
232 .n = { .min = 1, .max = 5 },
233 .m = { .min = 79, .max = 127 },
234 .m1 = { .min = 12, .max = 22 },
235 .m2 = { .min = 5, .max = 9 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8 },
238 .p2 = { .dot_limit = 225000,
239 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 240};
241
b91ad0ec 242static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 243 .dot = { .min = 25000, .max = 350000 },
244 .vco = { .min = 1760000, .max = 3510000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 79, .max = 118 },
247 .m1 = { .min = 12, .max = 22 },
248 .m2 = { .min = 5, .max = 9 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 225000,
252 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 253};
254
255static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 256 .dot = { .min = 25000, .max = 350000 },
257 .vco = { .min = 1760000, .max = 3510000 },
258 .n = { .min = 1, .max = 3 },
259 .m = { .min = 79, .max = 127 },
260 .m1 = { .min = 12, .max = 22 },
261 .m2 = { .min = 5, .max = 9 },
262 .p = { .min = 14, .max = 56 },
263 .p1 = { .min = 2, .max = 8 },
264 .p2 = { .dot_limit = 225000,
265 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 266};
267
273e27ca 268/* LVDS 100mhz refclk limits. */
b91ad0ec 269static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 270 .dot = { .min = 25000, .max = 350000 },
271 .vco = { .min = 1760000, .max = 3510000 },
272 .n = { .min = 1, .max = 2 },
273 .m = { .min = 79, .max = 126 },
274 .m1 = { .min = 12, .max = 22 },
275 .m2 = { .min = 5, .max = 9 },
276 .p = { .min = 28, .max = 112 },
0206e353 277 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 278 .p2 = { .dot_limit = 225000,
279 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 280};
281
282static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 283 .dot = { .min = 25000, .max = 350000 },
284 .vco = { .min = 1760000, .max = 3510000 },
285 .n = { .min = 1, .max = 3 },
286 .m = { .min = 79, .max = 126 },
287 .m1 = { .min = 12, .max = 22 },
288 .m2 = { .min = 5, .max = 9 },
289 .p = { .min = 14, .max = 42 },
0206e353 290 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 291 .p2 = { .dot_limit = 225000,
292 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 293};
294
a0c4da24
JB		 295static const intel_limit_t intel_limits_vlv_dac = {
296 .dot = { .min = 25000, .max = 270000 },
297 .vco = { .min = 4000000, .max = 6000000 },
298 .n = { .min = 1, .max = 7 },
299 .m = { .min = 22, .max = 450 }, /* guess */
300 .m1 = { .min = 2, .max = 3 },
301 .m2 = { .min = 11, .max = 156 },
302 .p = { .min = 10, .max = 30 },
75e53986 303 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 304 .p2 = { .dot_limit = 270000,
305 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 306};
307
308static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 309 .dot = { .min = 25000, .max = 270000 },
310 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 311 .n = { .min = 1, .max = 7 },
312 .m = { .min = 60, .max = 300 }, /* guess */
313 .m1 = { .min = 2, .max = 3 },
314 .m2 = { .min = 11, .max = 156 },
315 .p = { .min = 10, .max = 30 },
316 .p1 = { .min = 2, .max = 3 },
317 .p2 = { .dot_limit = 270000,
318 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 319};
320
321static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 322 .dot = { .min = 25000, .max = 270000 },
323 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 324 .n = { .min = 1, .max = 7 },
74a4dd2e 325 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 326 .m1 = { .min = 2, .max = 3 },
327 .m2 = { .min = 11, .max = 156 },
328 .p = { .min = 10, .max = 30 },
75e53986 329 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 330 .p2 = { .dot_limit = 270000,
331 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 332};
333
1b894b59
CW		 334static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
335 int refclk)
2c07245f 336{
b91ad0ec 337 struct drm_device *dev = crtc->dev;
2c07245f 338 const intel_limit_t *limit;
b91ad0ec
ZW		 339
340 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 341 if (intel_is_dual_link_lvds(dev)) {
1b894b59 342 if (refclk == 100000)
b91ad0ec
ZW		 343 limit = &intel_limits_ironlake_dual_lvds_100m;
344 else
345 limit = &intel_limits_ironlake_dual_lvds;
346 } else {
1b894b59 347 if (refclk == 100000)
b91ad0ec
ZW		 348 limit = &intel_limits_ironlake_single_lvds_100m;
349 else
350 limit = &intel_limits_ironlake_single_lvds;
351 }
c6bb3538 352 } else
b91ad0ec 353 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 354
355 return limit;
356}
357
044c7c41
ML		 358static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
359{
360 struct drm_device *dev = crtc->dev;
044c7c41
ML		 361 const intel_limit_t *limit;
362
363 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 364 if (intel_is_dual_link_lvds(dev))
e4b36699 365 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 366 else
e4b36699 367 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 368 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
369 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 370 limit = &intel_limits_g4x_hdmi;
044c7c41 371 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 372 limit = &intel_limits_g4x_sdvo;
044c7c41 373 } else /* The option is for other outputs */
e4b36699 374 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 375
376 return limit;
377}
378
1b894b59 379static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 380{
381 struct drm_device *dev = crtc->dev;
382 const intel_limit_t *limit;
383
bad720ff 384 if (HAS_PCH_SPLIT(dev))
1b894b59 385 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 386 else if (IS_G4X(dev)) {
044c7c41 387 limit = intel_g4x_limit(crtc);
f2b115e6 388 } else if (IS_PINEVIEW(dev)) {
2177832f 389 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 390 limit = &intel_limits_pineview_lvds;
2177832f 391 else
f2b115e6 392 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 393 } else if (IS_VALLEYVIEW(dev)) {
394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
395 limit = &intel_limits_vlv_dac;
396 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
397 limit = &intel_limits_vlv_hdmi;
398 else
399 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 400 } else if (!IS_GEN2(dev)) {
401 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
402 limit = &intel_limits_i9xx_lvds;
403 else
404 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 405 } else {
406 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 407 limit = &intel_limits_i8xx_lvds;
79e53945 408 else
e4b36699 409 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 410 }
411 return limit;
412}
413
f2b115e6
AJ		 414/* m1 is reserved as 0 in Pineview, n is a ring counter */
415static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 416{
2177832f
SL		 417 clock->m = clock->m2 + 2;
418 clock->p = clock->p1 * clock->p2;
419 clock->vco = refclk * clock->m / clock->n;
420 clock->dot = clock->vco / clock->p;
421}
422
7429e9d4
DV		 423static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
424{
425 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
426}
427
ac58c3f0 428static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 429{
7429e9d4 430 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 431 clock->p = clock->p1 * clock->p2;
432 clock->vco = refclk * clock->m / (clock->n + 2);
433 clock->dot = clock->vco / clock->p;
434}
435
79e53945
JB		 436/**
437 * Returns whether any output on the specified pipe is of the specified type
438 */
4ef69c7a 439bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 440{
4ef69c7a 441 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 442 struct intel_encoder *encoder;
443
6c2b7c12
DV		 444 for_each_encoder_on_crtc(dev, crtc, encoder)
445 if (encoder->type == type)
4ef69c7a
CW		 446 return true;
447
448 return false;
79e53945
JB		 449}
450
7c04d1d9 451#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 452/**
453 * Returns whether the given set of divisors are valid for a given refclk with
454 * the given connectors.
455 */
456
1b894b59
CW		 457static bool intel_PLL_is_valid(struct drm_device *dev,
458 const intel_limit_t *limit,
459 const intel_clock_t *clock)
79e53945 460{
79e53945 461 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 462 INTELPllInvalid("p1 out of range\n");
79e53945 463 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 464 INTELPllInvalid("p out of range\n");
79e53945 465 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 466 INTELPllInvalid("m2 out of range\n");
79e53945 467 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 468 INTELPllInvalid("m1 out of range\n");
f2b115e6 469 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 470 INTELPllInvalid("m1 <= m2\n");
79e53945 471 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 472 INTELPllInvalid("m out of range\n");
79e53945 473 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 474 INTELPllInvalid("n out of range\n");
79e53945 475 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 476 INTELPllInvalid("vco out of range\n");
79e53945
JB		 477 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
478 * connector, etc., rather than just a single range.
479 */
480 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 481 INTELPllInvalid("dot out of range\n");
79e53945
JB		 482
483 return true;
484}
485
d4906093 486static bool
ee9300bb 487i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 488 int target, int refclk, intel_clock_t *match_clock,
489 intel_clock_t *best_clock)
ac58c3f0
DV		 490{
491 struct drm_device *dev = crtc->dev;
492 intel_clock_t clock;
493 int err = target;
494
495 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
496 /*
497 * For LVDS just rely on its current settings for dual-channel.
498 * We haven't figured out how to reliably set up different
499 * single/dual channel state, if we even can.
500 */
501 if (intel_is_dual_link_lvds(dev))
502 clock.p2 = limit->p2.p2_fast;
503 else
504 clock.p2 = limit->p2.p2_slow;
505 } else {
506 if (target < limit->p2.dot_limit)
507 clock.p2 = limit->p2.p2_slow;
508 else
509 clock.p2 = limit->p2.p2_fast;
510 }
511
512 memset(best_clock, 0, sizeof(*best_clock));
513
514 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
515 clock.m1++) {
516 for (clock.m2 = limit->m2.min;
517 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 518 if (clock.m2 >= clock.m1)
ac58c3f0
DV		 519 break;
520 for (clock.n = limit->n.min;
521 clock.n <= limit->n.max; clock.n++) {
522 for (clock.p1 = limit->p1.min;
523 clock.p1 <= limit->p1.max; clock.p1++) {
524 int this_err;
d4906093 525
ac58c3f0
DV		 526 i9xx_clock(refclk, &clock);
527 if (!intel_PLL_is_valid(dev, limit,
528 &clock))
529 continue;
530 if (match_clock &&
531 clock.p != match_clock->p)
532 continue;
533
534 this_err = abs(clock.dot - target);
535 if (this_err < err) {
536 *best_clock = clock;
537 err = this_err;
538 }
539 }
540 }
541 }
542 }
543
544 return (err != target);
545}
546
547static bool
ee9300bb
DV		 548pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
549 int target, int refclk, intel_clock_t *match_clock,
550 intel_clock_t *best_clock)
79e53945
JB		 551{
552 struct drm_device *dev = crtc->dev;
79e53945 553 intel_clock_t clock;
79e53945
JB		 554 int err = target;
555
a210b028 556 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 557 /*
a210b028
DV		 558 * For LVDS just rely on its current settings for dual-channel.
559 * We haven't figured out how to reliably set up different
560 * single/dual channel state, if we even can.
79e53945 561 */
1974cad0 562 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 563 clock.p2 = limit->p2.p2_fast;
564 else
565 clock.p2 = limit->p2.p2_slow;
566 } else {
567 if (target < limit->p2.dot_limit)
568 clock.p2 = limit->p2.p2_slow;
569 else
570 clock.p2 = limit->p2.p2_fast;
571 }
572
0206e353 573 memset(best_clock, 0, sizeof(*best_clock));
79e53945 574
42158660
ZY		 575 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
576 clock.m1++) {
577 for (clock.m2 = limit->m2.min;
578 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 579 for (clock.n = limit->n.min;
580 clock.n <= limit->n.max; clock.n++) {
581 for (clock.p1 = limit->p1.min;
582 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 583 int this_err;
584
ac58c3f0 585 pineview_clock(refclk, &clock);
1b894b59
CW		 586 if (!intel_PLL_is_valid(dev, limit,
587 &clock))
79e53945 588 continue;
cec2f356
SP		 589 if (match_clock &&
590 clock.p != match_clock->p)
591 continue;
79e53945
JB		 592
593 this_err = abs(clock.dot - target);
594 if (this_err < err) {
595 *best_clock = clock;
596 err = this_err;
597 }
598 }
599 }
600 }
601 }
602
603 return (err != target);
604}
605
d4906093 606static bool
ee9300bb
DV		 607g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
608 int target, int refclk, intel_clock_t *match_clock,
609 intel_clock_t *best_clock)
d4906093
ML		 610{
611 struct drm_device *dev = crtc->dev;
d4906093
ML		 612 intel_clock_t clock;
613 int max_n;
614 bool found;
6ba770dc
AJ		 615 /* approximately equals target * 0.00585 */
616 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 617 found = false;
618
619 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 620 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 621 clock.p2 = limit->p2.p2_fast;
622 else
623 clock.p2 = limit->p2.p2_slow;
624 } else {
625 if (target < limit->p2.dot_limit)
626 clock.p2 = limit->p2.p2_slow;
627 else
628 clock.p2 = limit->p2.p2_fast;
629 }
630
631 memset(best_clock, 0, sizeof(*best_clock));
632 max_n = limit->n.max;
f77f13e2 633 /* based on hardware requirement, prefer smaller n to precision */
d4906093 634 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 635 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 636 for (clock.m1 = limit->m1.max;
637 clock.m1 >= limit->m1.min; clock.m1--) {
638 for (clock.m2 = limit->m2.max;
639 clock.m2 >= limit->m2.min; clock.m2--) {
640 for (clock.p1 = limit->p1.max;
641 clock.p1 >= limit->p1.min; clock.p1--) {
642 int this_err;
643
ac58c3f0 644 i9xx_clock(refclk, &clock);
1b894b59
CW		 645 if (!intel_PLL_is_valid(dev, limit,
646 &clock))
d4906093 647 continue;
1b894b59
CW		 648
649 this_err = abs(clock.dot - target);
d4906093
ML		 650 if (this_err < err_most) {
651 *best_clock = clock;
652 err_most = this_err;
653 max_n = clock.n;
654 found = true;
655 }
656 }
657 }
658 }
659 }
2c07245f
ZW		 660 return found;
661}
662
a0c4da24 663static bool
ee9300bb
DV		 664vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
665 int target, int refclk, intel_clock_t *match_clock,
666 intel_clock_t *best_clock)
a0c4da24
JB		 667{
668 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
669 u32 m, n, fastclk;
670 u32 updrate, minupdate, fracbits, p;
671 unsigned long bestppm, ppm, absppm;
672 int dotclk, flag;
673
af447bd3 674 flag = 0;
a0c4da24
JB		 675 dotclk = target * 1000;
676 bestppm = 1000000;
677 ppm = absppm = 0;
678 fastclk = dotclk / (2*100);
679 updrate = 0;
680 minupdate = 19200;
681 fracbits = 1;
682 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
683 bestm1 = bestm2 = bestp1 = bestp2 = 0;
684
685 /* based on hardware requirement, prefer smaller n to precision */
686 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
687 updrate = refclk / n;
688 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
689 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
690 if (p2 > 10)
691 p2 = p2 - 1;
692 p = p1 * p2;
693 /* based on hardware requirement, prefer bigger m1,m2 values */
694 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
695 m2 = (((2*(fastclk * p * n / m1 )) +
696 refclk) / (2*refclk));
697 m = m1 * m2;
698 vco = updrate * m;
699 if (vco >= limit->vco.min && vco < limit->vco.max) {
700 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
701 absppm = (ppm > 0) ? ppm : (-ppm);
702 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
703 bestppm = 0;
704 flag = 1;
705 }
706 if (absppm < bestppm - 10) {
707 bestppm = absppm;
708 flag = 1;
709 }
710 if (flag) {
711 bestn = n;
712 bestm1 = m1;
713 bestm2 = m2;
714 bestp1 = p1;
715 bestp2 = p2;
716 flag = 0;
717 }
718 }
719 }
720 }
721 }
722 }
723 best_clock->n = bestn;
724 best_clock->m1 = bestm1;
725 best_clock->m2 = bestm2;
726 best_clock->p1 = bestp1;
727 best_clock->p2 = bestp2;
728
729 return true;
730}
a4fc5ed6 731
a5c961d1
PZ		 732enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
733 enum pipe pipe)
734{
735 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
737
3b117c8f 738 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 739}
740
a928d536
PZ		 741static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
742{
743 struct drm_i915_private *dev_priv = dev->dev_private;
744 u32 frame, frame_reg = PIPEFRAME(pipe);
745
746 frame = I915_READ(frame_reg);
747
748 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
749 DRM_DEBUG_KMS("vblank wait timed out\n");
750}
751
9d0498a2
JB		 752/**
753 * intel_wait_for_vblank - wait for vblank on a given pipe
754 * @dev: drm device
755 * @pipe: pipe to wait for
756 *
757 * Wait for vblank to occur on a given pipe. Needed for various bits of
758 * mode setting code.
759 */
760void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 761{
9d0498a2 762 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 763 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 764
a928d536
PZ		 765 if (INTEL_INFO(dev)->gen >= 5) {
766 ironlake_wait_for_vblank(dev, pipe);
767 return;
768 }
769
300387c0
CW		 770 /* Clear existing vblank status. Note this will clear any other
771 * sticky status fields as well.
772 *
773 * This races with i915_driver_irq_handler() with the result
774 * that either function could miss a vblank event. Here it is not
775 * fatal, as we will either wait upon the next vblank interrupt or
776 * timeout. Generally speaking intel_wait_for_vblank() is only
777 * called during modeset at which time the GPU should be idle and
778 * should *not* be performing page flips and thus not waiting on
779 * vblanks...
780 * Currently, the result of us stealing a vblank from the irq
781 * handler is that a single frame will be skipped during swapbuffers.
782 */
783 I915_WRITE(pipestat_reg,
784 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
785
9d0498a2 786 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 787 if (wait_for(I915_READ(pipestat_reg) &
788 PIPE_VBLANK_INTERRUPT_STATUS,
789 50))
9d0498a2
JB		 790 DRM_DEBUG_KMS("vblank wait timed out\n");
791}
792
ab7ad7f6
KP		 793/*
794 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 795 * @dev: drm device
796 * @pipe: pipe to wait for
797 *
798 * After disabling a pipe, we can't wait for vblank in the usual way,
799 * spinning on the vblank interrupt status bit, since we won't actually
800 * see an interrupt when the pipe is disabled.
801 *
ab7ad7f6
KP		 802 * On Gen4 and above:
803 * wait for the pipe register state bit to turn off
804 *
805 * Otherwise:
806 * wait for the display line value to settle (it usually
807 * ends up stopping at the start of the next frame).
58e10eb9 808 *
9d0498a2 809 */
58e10eb9 810void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 811{
812 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 813 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
814 pipe);
ab7ad7f6
KP		 815
816 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 817 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 818
819 /* Wait for the Pipe State to go off */
58e10eb9
CW		 820 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
821 100))
284637d9 822 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 823 } else {
837ba00f 824 u32 last_line, line_mask;
58e10eb9 825 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 826 unsigned long timeout = jiffies + msecs_to_jiffies(100);
827
837ba00f
PZ		 828 if (IS_GEN2(dev))
829 line_mask = DSL_LINEMASK_GEN2;
830 else
831 line_mask = DSL_LINEMASK_GEN3;
832
ab7ad7f6
KP		 833 /* Wait for the display line to settle */
834 do {
837ba00f 835 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 836 mdelay(5);
837ba00f 837 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 838 time_after(timeout, jiffies));
839 if (time_after(jiffies, timeout))
284637d9 840 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 841 }
79e53945
JB		 842}
843
b0ea7d37
DL		 844/*
845 * ibx_digital_port_connected - is the specified port connected?
846 * @dev_priv: i915 private structure
847 * @port: the port to test
848 *
849 * Returns true if @port is connected, false otherwise.
850 */
851bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
852 struct intel_digital_port *port)
853{
854 u32 bit;
855
c36346e3
DL		 856 if (HAS_PCH_IBX(dev_priv->dev)) {
857 switch(port->port) {
858 case PORT_B:
859 bit = SDE_PORTB_HOTPLUG;
860 break;
861 case PORT_C:
862 bit = SDE_PORTC_HOTPLUG;
863 break;
864 case PORT_D:
865 bit = SDE_PORTD_HOTPLUG;
866 break;
867 default:
868 return true;
869 }
870 } else {
871 switch(port->port) {
872 case PORT_B:
873 bit = SDE_PORTB_HOTPLUG_CPT;
874 break;
875 case PORT_C:
876 bit = SDE_PORTC_HOTPLUG_CPT;
877 break;
878 case PORT_D:
879 bit = SDE_PORTD_HOTPLUG_CPT;
880 break;
881 default:
882 return true;
883 }
b0ea7d37
DL		 884 }
885
886 return I915_READ(SDEISR) & bit;
887}
888
b24e7179
JB		 889static const char *state_string(bool enabled)
890{
891 return enabled ? "on" : "off";
892}
893
894/* Only for pre-ILK configs */
895static void assert_pll(struct drm_i915_private *dev_priv,
896 enum pipe pipe, bool state)
897{
898 int reg;
899 u32 val;
900 bool cur_state;
901
902 reg = DPLL(pipe);
903 val = I915_READ(reg);
904 cur_state = !!(val & DPLL_VCO_ENABLE);
905 WARN(cur_state != state,
906 "PLL state assertion failure (expected %s, current %s)\n",
907 state_string(state), state_string(cur_state));
908}
909#define assert_pll_enabled(d, p) assert_pll(d, p, true)
910#define assert_pll_disabled(d, p) assert_pll(d, p, false)
911
e2b78267
DV		 912static struct intel_shared_dpll *
913intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
914{
915 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
916
a43f6e0f 917 if (crtc->config.shared_dpll < 0)
e2b78267
DV		 918 return NULL;
919
a43f6e0f 920 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
e2b78267
DV		 921}
922
040484af 923/* For ILK+ */
e72f9fbf
DV		 924static void assert_shared_dpll(struct drm_i915_private *dev_priv,
925 struct intel_shared_dpll *pll,
e72f9fbf 926 bool state)
040484af 927{
040484af
JB		 928 u32 val;
929 bool cur_state;
930
9d82aa17
ED		 931 if (HAS_PCH_LPT(dev_priv->dev)) {
932 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
933 return;
934 }
935
92b27b08 936 if (WARN (!pll,
46edb027 937 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 938 return;
ee7b9f93 939
e9a632a5 940 val = I915_READ(PCH_DPLL(pll->id));
92b27b08
CW		 941 cur_state = !!(val & DPLL_VCO_ENABLE);
942 WARN(cur_state != state,
46edb027
DV		 943 "%s assertion failure (expected %s, current %s), val=%08x\n",
944 pll->name, state_string(state), state_string(cur_state), val);
040484af 945}
e9d6944e
DV		 946#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
947#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
040484af
JB		 948
949static void assert_fdi_tx(struct drm_i915_private *dev_priv,
950 enum pipe pipe, bool state)
951{
952 int reg;
953 u32 val;
954 bool cur_state;
ad80a810
PZ		 955 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
956 pipe);
040484af 957
affa9354
PZ		 958 if (HAS_DDI(dev_priv->dev)) {
959 /* DDI does not have a specific FDI_TX register */
ad80a810 960 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 961 val = I915_READ(reg);
ad80a810 962 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 963 } else {
964 reg = FDI_TX_CTL(pipe);
965 val = I915_READ(reg);
966 cur_state = !!(val & FDI_TX_ENABLE);
967 }
040484af
JB		 968 WARN(cur_state != state,
969 "FDI TX state assertion failure (expected %s, current %s)\n",
970 state_string(state), state_string(cur_state));
971}
972#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
973#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
974
975static void assert_fdi_rx(struct drm_i915_private *dev_priv,
976 enum pipe pipe, bool state)
977{
978 int reg;
979 u32 val;
980 bool cur_state;
981
d63fa0dc
PZ		 982 reg = FDI_RX_CTL(pipe);
983 val = I915_READ(reg);
984 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 985 WARN(cur_state != state,
986 "FDI RX state assertion failure (expected %s, current %s)\n",
987 state_string(state), state_string(cur_state));
988}
989#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
990#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
991
992static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
993 enum pipe pipe)
994{
995 int reg;
996 u32 val;
997
998 /* ILK FDI PLL is always enabled */
999 if (dev_priv->info->gen == 5)
1000 return;
1001
bf507ef7 1002 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1003 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1004 return;
1005
040484af
JB		 1006 reg = FDI_TX_CTL(pipe);
1007 val = I915_READ(reg);
1008 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1009}
1010
1011static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1012 enum pipe pipe)
1013{
1014 int reg;
1015 u32 val;
1016
1017 reg = FDI_RX_CTL(pipe);
1018 val = I915_READ(reg);
1019 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1020}
1021
ea0760cf
JB		 1022static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1023 enum pipe pipe)
1024{
1025 int pp_reg, lvds_reg;
1026 u32 val;
1027 enum pipe panel_pipe = PIPE_A;
0de3b485 1028 bool locked = true;
ea0760cf
JB		 1029
1030 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1031 pp_reg = PCH_PP_CONTROL;
1032 lvds_reg = PCH_LVDS;
1033 } else {
1034 pp_reg = PP_CONTROL;
1035 lvds_reg = LVDS;
1036 }
1037
1038 val = I915_READ(pp_reg);
1039 if (!(val & PANEL_POWER_ON) ||
1040 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1041 locked = false;
1042
1043 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1044 panel_pipe = PIPE_B;
1045
1046 WARN(panel_pipe == pipe && locked,
1047 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1048 pipe_name(pipe));
ea0760cf
JB		 1049}
1050
b840d907
JB		 1051void assert_pipe(struct drm_i915_private *dev_priv,
1052 enum pipe pipe, bool state)
b24e7179
JB		 1053{
1054 int reg;
1055 u32 val;
63d7bbe9 1056 bool cur_state;
702e7a56
PZ		 1057 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1058 pipe);
b24e7179 1059
8e636784
DV		 1060 /* if we need the pipe A quirk it must be always on */
1061 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1062 state = true;
1063
b97186f0
PZ		 1064 if (!intel_display_power_enabled(dev_priv->dev,
1065 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1066 cur_state = false;
1067 } else {
1068 reg = PIPECONF(cpu_transcoder);
1069 val = I915_READ(reg);
1070 cur_state = !!(val & PIPECONF_ENABLE);
1071 }
1072
63d7bbe9
JB		 1073 WARN(cur_state != state,
1074 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1075 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1076}
1077
931872fc
CW		 1078static void assert_plane(struct drm_i915_private *dev_priv,
1079 enum plane plane, bool state)
b24e7179
JB		 1080{
1081 int reg;
1082 u32 val;
931872fc 1083 bool cur_state;
b24e7179
JB		 1084
1085 reg = DSPCNTR(plane);
1086 val = I915_READ(reg);
931872fc
CW		 1087 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1088 WARN(cur_state != state,
1089 "plane %c assertion failure (expected %s, current %s)\n",
1090 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1091}
1092
931872fc
CW		 1093#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1094#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1095
b24e7179
JB		 1096static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1097 enum pipe pipe)
1098{
653e1026 1099 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1100 int reg, i;
1101 u32 val;
1102 int cur_pipe;
1103
653e1026
VS		 1104 /* Primary planes are fixed to pipes on gen4+ */
1105 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1106 reg = DSPCNTR(pipe);
1107 val = I915_READ(reg);
1108 WARN((val & DISPLAY_PLANE_ENABLE),
1109 "plane %c assertion failure, should be disabled but not\n",
1110 plane_name(pipe));
19ec1358 1111 return;
28c05794 1112 }
19ec1358 1113
b24e7179 1114 /* Need to check both planes against the pipe */
653e1026 1115 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
b24e7179
JB		 1116 reg = DSPCNTR(i);
1117 val = I915_READ(reg);
1118 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1119 DISPPLANE_SEL_PIPE_SHIFT;
1120 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1121 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1122 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1123 }
1124}
1125
19332d7a
JB		 1126static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1127 enum pipe pipe)
1128{
20674eef 1129 struct drm_device *dev = dev_priv->dev;
19332d7a
JB		 1130 int reg, i;
1131 u32 val;
1132
20674eef
VS		 1133 if (IS_VALLEYVIEW(dev)) {
1134 for (i = 0; i < dev_priv->num_plane; i++) {
1135 reg = SPCNTR(pipe, i);
1136 val = I915_READ(reg);
1137 WARN((val & SP_ENABLE),
1138 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1139 sprite_name(pipe, i), pipe_name(pipe));
1140 }
1141 } else if (INTEL_INFO(dev)->gen >= 7) {
1142 reg = SPRCTL(pipe);
1143 val = I915_READ(reg);
1144 WARN((val & SPRITE_ENABLE),
1145 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1146 plane_name(pipe), pipe_name(pipe));
1147 } else if (INTEL_INFO(dev)->gen >= 5) {
1148 reg = DVSCNTR(pipe);
19332d7a 1149 val = I915_READ(reg);
20674eef 1150 WARN((val & DVS_ENABLE),
06da8da2 1151 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1152 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1153 }
1154}
1155
92f2584a
JB		 1156static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1157{
1158 u32 val;
1159 bool enabled;
1160
9d82aa17
ED		 1161 if (HAS_PCH_LPT(dev_priv->dev)) {
1162 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1163 return;
1164 }
1165
92f2584a
JB		 1166 val = I915_READ(PCH_DREF_CONTROL);
1167 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1168 DREF_SUPERSPREAD_SOURCE_MASK));
1169 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1170}
1171
ab9412ba
DV		 1172static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1173 enum pipe pipe)
92f2584a
JB		 1174{
1175 int reg;
1176 u32 val;
1177 bool enabled;
1178
ab9412ba 1179 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1180 val = I915_READ(reg);
1181 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1182 WARN(enabled,
1183 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1184 pipe_name(pipe));
92f2584a
JB		 1185}
1186
4e634389
KP		 1187static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1188 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1189{
1190 if ((val & DP_PORT_EN) == 0)
1191 return false;
1192
1193 if (HAS_PCH_CPT(dev_priv->dev)) {
1194 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1195 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1196 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1197 return false;
1198 } else {
1199 if ((val & DP_PIPE_MASK) != (pipe << 30))
1200 return false;
1201 }
1202 return true;
1203}
1204
1519b995
KP		 1205static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1206 enum pipe pipe, u32 val)
1207{
dc0fa718 1208 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1209 return false;
1210
1211 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1212 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1213 return false;
1214 } else {
dc0fa718 1215 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1216 return false;
1217 }
1218 return true;
1219}
1220
1221static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1222 enum pipe pipe, u32 val)
1223{
1224 if ((val & LVDS_PORT_EN) == 0)
1225 return false;
1226
1227 if (HAS_PCH_CPT(dev_priv->dev)) {
1228 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1229 return false;
1230 } else {
1231 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1232 return false;
1233 }
1234 return true;
1235}
1236
1237static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1238 enum pipe pipe, u32 val)
1239{
1240 if ((val & ADPA_DAC_ENABLE) == 0)
1241 return false;
1242 if (HAS_PCH_CPT(dev_priv->dev)) {
1243 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1244 return false;
1245 } else {
1246 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1247 return false;
1248 }
1249 return true;
1250}
1251
291906f1 1252static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1253 enum pipe pipe, int reg, u32 port_sel)
291906f1 1254{
47a05eca 1255 u32 val = I915_READ(reg);
4e634389 1256 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1257 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1258 reg, pipe_name(pipe));
de9a35ab 1259
75c5da27
DV		 1260 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1261 && (val & DP_PIPEB_SELECT),
de9a35ab 1262 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1263}
1264
1265static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1266 enum pipe pipe, int reg)
1267{
47a05eca 1268 u32 val = I915_READ(reg);
b70ad586 1269 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1270 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1271 reg, pipe_name(pipe));
de9a35ab 1272
dc0fa718 1273 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1274 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1275 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1276}
1277
1278static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1279 enum pipe pipe)
1280{
1281 int reg;
1282 u32 val;
291906f1 1283
f0575e92
KP		 1284 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1285 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1286 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1287
1288 reg = PCH_ADPA;
1289 val = I915_READ(reg);
b70ad586 1290 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1291 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1292 pipe_name(pipe));
291906f1
JB		 1293
1294 reg = PCH_LVDS;
1295 val = I915_READ(reg);
b70ad586 1296 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1297 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1298 pipe_name(pipe));
291906f1 1299
e2debe91
PZ		 1300 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1301 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1302 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1303}
1304
63d7bbe9
JB		 1305/**
1306 * intel_enable_pll - enable a PLL
1307 * @dev_priv: i915 private structure
1308 * @pipe: pipe PLL to enable
1309 *
1310 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1311 * make sure the PLL reg is writable first though, since the panel write
1312 * protect mechanism may be enabled.
1313 *
1314 * Note! This is for pre-ILK only.
7434a255
TR		 1315 *
1316 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1317 */
1318static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1319{
1320 int reg;
1321 u32 val;
1322
58c6eaa2
DV		 1323 assert_pipe_disabled(dev_priv, pipe);
1324
63d7bbe9 1325 /* No really, not for ILK+ */
a0c4da24 1326 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1327
1328 /* PLL is protected by panel, make sure we can write it */
1329 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1330 assert_panel_unlocked(dev_priv, pipe);
1331
1332 reg = DPLL(pipe);
1333 val = I915_READ(reg);
1334 val |= DPLL_VCO_ENABLE;
1335
1336 /* We do this three times for luck */
1337 I915_WRITE(reg, val);
1338 POSTING_READ(reg);
1339 udelay(150); /* wait for warmup */
1340 I915_WRITE(reg, val);
1341 POSTING_READ(reg);
1342 udelay(150); /* wait for warmup */
1343 I915_WRITE(reg, val);
1344 POSTING_READ(reg);
1345 udelay(150); /* wait for warmup */
1346}
1347
1348/**
1349 * intel_disable_pll - disable a PLL
1350 * @dev_priv: i915 private structure
1351 * @pipe: pipe PLL to disable
1352 *
1353 * Disable the PLL for @pipe, making sure the pipe is off first.
1354 *
1355 * Note! This is for pre-ILK only.
1356 */
1357static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1358{
1359 int reg;
1360 u32 val;
1361
1362 /* Don't disable pipe A or pipe A PLLs if needed */
1363 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1364 return;
1365
1366 /* Make sure the pipe isn't still relying on us */
1367 assert_pipe_disabled(dev_priv, pipe);
1368
1369 reg = DPLL(pipe);
1370 val = I915_READ(reg);
1371 val &= ~DPLL_VCO_ENABLE;
1372 I915_WRITE(reg, val);
1373 POSTING_READ(reg);
1374}
1375
89b667f8
JB		 1376void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1377{
1378 u32 port_mask;
1379
1380 if (!port)
1381 port_mask = DPLL_PORTB_READY_MASK;
1382 else
1383 port_mask = DPLL_PORTC_READY_MASK;
1384
1385 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1386 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1387 'B' + port, I915_READ(DPLL(0)));
1388}
1389
92f2584a 1390/**
e72f9fbf 1391 * ironlake_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1392 * @dev_priv: i915 private structure
1393 * @pipe: pipe PLL to enable
1394 *
1395 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1396 * drives the transcoder clock.
1397 */
e2b78267 1398static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1399{
e2b78267
DV		 1400 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1401 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1402
48da64a8 1403 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1404 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1405 if (pll == NULL)
1406 return;
1407
1408 if (WARN_ON(pll->refcount == 0))
1409 return;
ee7b9f93 1410
46edb027
DV		 1411 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1412 pll->name, pll->active, pll->on,
e2b78267 1413 crtc->base.base.id);
92f2584a 1414
cdbd2316
DV		 1415 if (pll->active++) {
1416 WARN_ON(!pll->on);
e9d6944e 1417 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1418 return;
1419 }
f4a091c7 1420 WARN_ON(pll->on);
ee7b9f93 1421
46edb027 1422 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1423 pll->enable(dev_priv, pll);
ee7b9f93 1424 pll->on = true;
92f2584a
JB		 1425}
1426
e2b78267 1427static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1428{
e2b78267
DV		 1429 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1430 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1431
92f2584a
JB		 1432 /* PCH only available on ILK+ */
1433 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1434 if (pll == NULL)
1435 return;
92f2584a 1436
48da64a8
CW		 1437 if (WARN_ON(pll->refcount == 0))
1438 return;
7a419866 1439
46edb027
DV		 1440 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1441 pll->name, pll->active, pll->on,
e2b78267 1442 crtc->base.base.id);
7a419866 1443
48da64a8 1444 if (WARN_ON(pll->active == 0)) {
e9d6944e 1445 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1446 return;
1447 }
1448
e9d6944e 1449 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1450 WARN_ON(!pll->on);
cdbd2316 1451 if (--pll->active)
7a419866 1452 return;
ee7b9f93 1453
46edb027 1454 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1455 pll->disable(dev_priv, pll);
ee7b9f93 1456 pll->on = false;
92f2584a
JB		 1457}
1458
b8a4f404
PZ		 1459static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1460 enum pipe pipe)
040484af 1461{
23670b32 1462 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1463 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1464 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1465 uint32_t reg, val, pipeconf_val;
040484af
JB		 1466
1467 /* PCH only available on ILK+ */
1468 BUG_ON(dev_priv->info->gen < 5);
1469
1470 /* Make sure PCH DPLL is enabled */
e72f9fbf 1471 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1472 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1473
1474 /* FDI must be feeding us bits for PCH ports */
1475 assert_fdi_tx_enabled(dev_priv, pipe);
1476 assert_fdi_rx_enabled(dev_priv, pipe);
1477
23670b32
DV		 1478 if (HAS_PCH_CPT(dev)) {
1479 /* Workaround: Set the timing override bit before enabling the
1480 * pch transcoder. */
1481 reg = TRANS_CHICKEN2(pipe);
1482 val = I915_READ(reg);
1483 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1484 I915_WRITE(reg, val);
59c859d6 1485 }
23670b32 1486
ab9412ba 1487 reg = PCH_TRANSCONF(pipe);
040484af 1488 val = I915_READ(reg);
5f7f726d 1489 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1490
1491 if (HAS_PCH_IBX(dev_priv->dev)) {
1492 /*
1493 * make the BPC in transcoder be consistent with
1494 * that in pipeconf reg.
1495 */
dfd07d72
DV		 1496 val &= ~PIPECONF_BPC_MASK;
1497 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1498 }
5f7f726d
PZ		 1499
1500 val &= ~TRANS_INTERLACE_MASK;
1501 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1502 if (HAS_PCH_IBX(dev_priv->dev) &&
1503 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1504 val |= TRANS_LEGACY_INTERLACED_ILK;
1505 else
1506 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1507 else
1508 val |= TRANS_PROGRESSIVE;
1509
040484af
JB		 1510 I915_WRITE(reg, val | TRANS_ENABLE);
1511 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1512 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1513}
1514
8fb033d7 1515static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1516 enum transcoder cpu_transcoder)
040484af 1517{
8fb033d7 1518 u32 val, pipeconf_val;
8fb033d7
PZ		 1519
1520 /* PCH only available on ILK+ */
1521 BUG_ON(dev_priv->info->gen < 5);
1522
8fb033d7 1523 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1524 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1525 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1526
223a6fdf
PZ		 1527 /* Workaround: set timing override bit. */
1528 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1529 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1530 I915_WRITE(_TRANSA_CHICKEN2, val);
1531
25f3ef11 1532 val = TRANS_ENABLE;
937bb610 1533 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1534
9a76b1c6
PZ		 1535 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1536 PIPECONF_INTERLACED_ILK)
a35f2679 1537 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1538 else
1539 val |= TRANS_PROGRESSIVE;
1540
ab9412ba
DV		 1541 I915_WRITE(LPT_TRANSCONF, val);
1542 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1543 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1544}
1545
b8a4f404
PZ		 1546static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1547 enum pipe pipe)
040484af 1548{
23670b32
DV		 1549 struct drm_device *dev = dev_priv->dev;
1550 uint32_t reg, val;
040484af
JB		 1551
1552 /* FDI relies on the transcoder */
1553 assert_fdi_tx_disabled(dev_priv, pipe);
1554 assert_fdi_rx_disabled(dev_priv, pipe);
1555
291906f1
JB		 1556 /* Ports must be off as well */
1557 assert_pch_ports_disabled(dev_priv, pipe);
1558
ab9412ba 1559 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1560 val = I915_READ(reg);
1561 val &= ~TRANS_ENABLE;
1562 I915_WRITE(reg, val);
1563 /* wait for PCH transcoder off, transcoder state */
1564 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1565 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1566
1567 if (!HAS_PCH_IBX(dev)) {
1568 /* Workaround: Clear the timing override chicken bit again. */
1569 reg = TRANS_CHICKEN2(pipe);
1570 val = I915_READ(reg);
1571 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1572 I915_WRITE(reg, val);
1573 }
040484af
JB		 1574}
1575
ab4d966c 1576static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1577{
8fb033d7
PZ		 1578 u32 val;
1579
ab9412ba 1580 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1581 val &= ~TRANS_ENABLE;
ab9412ba 1582 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1583 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1584 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1585 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1586
1587 /* Workaround: clear timing override bit. */
1588 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1589 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1590 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1591}
1592
b24e7179 1593/**
309cfea8 1594 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1595 * @dev_priv: i915 private structure
1596 * @pipe: pipe to enable
040484af 1597 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1598 *
1599 * Enable @pipe, making sure that various hardware specific requirements
1600 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1601 *
1602 * @pipe should be %PIPE_A or %PIPE_B.
1603 *
1604 * Will wait until the pipe is actually running (i.e. first vblank) before
1605 * returning.
1606 */
040484af
JB		 1607static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1608 bool pch_port)
b24e7179 1609{
702e7a56
PZ		 1610 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1611 pipe);
1a240d4d 1612 enum pipe pch_transcoder;
b24e7179
JB		 1613 int reg;
1614 u32 val;
1615
58c6eaa2
DV		 1616 assert_planes_disabled(dev_priv, pipe);
1617 assert_sprites_disabled(dev_priv, pipe);
1618
681e5811 1619 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1620 pch_transcoder = TRANSCODER_A;
1621 else
1622 pch_transcoder = pipe;
1623
b24e7179
JB		 1624 /*
1625 * A pipe without a PLL won't actually be able to drive bits from
1626 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1627 * need the check.
1628 */
1629 if (!HAS_PCH_SPLIT(dev_priv->dev))
1630 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1631 else {
1632 if (pch_port) {
1633 /* if driving the PCH, we need FDI enabled */
cc391bbb 1634 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1635 assert_fdi_tx_pll_enabled(dev_priv,
1636 (enum pipe) cpu_transcoder);
040484af
JB		 1637 }
1638 /* FIXME: assert CPU port conditions for SNB+ */
1639 }
b24e7179 1640
702e7a56 1641 reg = PIPECONF(cpu_transcoder);
b24e7179 1642 val = I915_READ(reg);
00d70b15
CW		 1643 if (val & PIPECONF_ENABLE)
1644 return;
1645
1646 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1647 intel_wait_for_vblank(dev_priv->dev, pipe);
1648}
1649
1650/**
309cfea8 1651 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1652 * @dev_priv: i915 private structure
1653 * @pipe: pipe to disable
1654 *
1655 * Disable @pipe, making sure that various hardware specific requirements
1656 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1657 *
1658 * @pipe should be %PIPE_A or %PIPE_B.
1659 *
1660 * Will wait until the pipe has shut down before returning.
1661 */
1662static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1663 enum pipe pipe)
1664{
702e7a56
PZ		 1665 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1666 pipe);
b24e7179
JB		 1667 int reg;
1668 u32 val;
1669
1670 /*
1671 * Make sure planes won't keep trying to pump pixels to us,
1672 * or we might hang the display.
1673 */
1674 assert_planes_disabled(dev_priv, pipe);
19332d7a 1675 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1676
1677 /* Don't disable pipe A or pipe A PLLs if needed */
1678 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1679 return;
1680
702e7a56 1681 reg = PIPECONF(cpu_transcoder);
b24e7179 1682 val = I915_READ(reg);
00d70b15
CW		 1683 if ((val & PIPECONF_ENABLE) == 0)
1684 return;
1685
1686 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1687 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1688}
1689
d74362c9
KP		 1690/*
1691 * Plane regs are double buffered, going from enabled->disabled needs a
1692 * trigger in order to latch. The display address reg provides this.
1693 */
6f1d69b0 1694void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1695 enum plane plane)
1696{
14f86147
DL		 1697 if (dev_priv->info->gen >= 4)
1698 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1699 else
1700 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1701}
1702
b24e7179
JB		 1703/**
1704 * intel_enable_plane - enable a display plane on a given pipe
1705 * @dev_priv: i915 private structure
1706 * @plane: plane to enable
1707 * @pipe: pipe being fed
1708 *
1709 * Enable @plane on @pipe, making sure that @pipe is running first.
1710 */
1711static void intel_enable_plane(struct drm_i915_private *dev_priv,
1712 enum plane plane, enum pipe pipe)
1713{
1714 int reg;
1715 u32 val;
1716
1717 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1718 assert_pipe_enabled(dev_priv, pipe);
1719
1720 reg = DSPCNTR(plane);
1721 val = I915_READ(reg);
00d70b15
CW		 1722 if (val & DISPLAY_PLANE_ENABLE)
1723 return;
1724
1725 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1726 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1727 intel_wait_for_vblank(dev_priv->dev, pipe);
1728}
1729
b24e7179
JB		 1730/**
1731 * intel_disable_plane - disable a display plane
1732 * @dev_priv: i915 private structure
1733 * @plane: plane to disable
1734 * @pipe: pipe consuming the data
1735 *
1736 * Disable @plane; should be an independent operation.
1737 */
1738static void intel_disable_plane(struct drm_i915_private *dev_priv,
1739 enum plane plane, enum pipe pipe)
1740{
1741 int reg;
1742 u32 val;
1743
1744 reg = DSPCNTR(plane);
1745 val = I915_READ(reg);
00d70b15
CW		 1746 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1747 return;
1748
1749 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1750 intel_flush_display_plane(dev_priv, plane);
1751 intel_wait_for_vblank(dev_priv->dev, pipe);
1752}
1753
693db184
CW		 1754static bool need_vtd_wa(struct drm_device *dev)
1755{
1756#ifdef CONFIG_INTEL_IOMMU
1757 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1758 return true;
1759#endif
1760 return false;
1761}
1762
127bd2ac 1763int
48b956c5 1764intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1765 struct drm_i915_gem_object *obj,
919926ae 1766 struct intel_ring_buffer *pipelined)
6b95a207 1767{
ce453d81 1768 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1769 u32 alignment;
1770 int ret;
1771
05394f39 1772 switch (obj->tiling_mode) {
6b95a207 1773 case I915_TILING_NONE:
534843da
CW		 1774 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1775 alignment = 128 * 1024;
a6c45cf0 1776 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1777 alignment = 4 * 1024;
1778 else
1779 alignment = 64 * 1024;
6b95a207
KH		 1780 break;
1781 case I915_TILING_X:
1782 /* pin() will align the object as required by fence */
1783 alignment = 0;
1784 break;
1785 case I915_TILING_Y:
8bb6e959
DV		 1786 /* Despite that we check this in framebuffer_init userspace can
1787 * screw us over and change the tiling after the fact. Only
1788 * pinned buffers can't change their tiling. */
1789 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1790 return -EINVAL;
1791 default:
1792 BUG();
1793 }
1794
693db184
CW		 1795 /* Note that the w/a also requires 64 PTE of padding following the
1796 * bo. We currently fill all unused PTE with the shadow page and so
1797 * we should always have valid PTE following the scanout preventing
1798 * the VT-d warning.
1799 */
1800 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1801 alignment = 256 * 1024;
1802
ce453d81 1803 dev_priv->mm.interruptible = false;
2da3b9b9 1804 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1805 if (ret)
ce453d81 1806 goto err_interruptible;
6b95a207
KH		 1807
1808 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1809 * fence, whereas 965+ only requires a fence if using
1810 * framebuffer compression. For simplicity, we always install
1811 * a fence as the cost is not that onerous.
1812 */
06d98131 1813 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1814 if (ret)
1815 goto err_unpin;
1690e1eb 1816
9a5a53b3 1817 i915_gem_object_pin_fence(obj);
6b95a207 1818
ce453d81 1819 dev_priv->mm.interruptible = true;
6b95a207 1820 return 0;
48b956c5
CW		 1821
1822err_unpin:
1823 i915_gem_object_unpin(obj);
ce453d81
CW		 1824err_interruptible:
1825 dev_priv->mm.interruptible = true;
48b956c5 1826 return ret;
6b95a207
KH		 1827}
1828
1690e1eb
CW		 1829void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1830{
1831 i915_gem_object_unpin_fence(obj);
1832 i915_gem_object_unpin(obj);
1833}
1834
c2c75131
DV		 1835/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1836 * is assumed to be a power-of-two. */
bc752862
CW		 1837unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1838 unsigned int tiling_mode,
1839 unsigned int cpp,
1840 unsigned int pitch)
c2c75131 1841{
bc752862
CW		 1842 if (tiling_mode != I915_TILING_NONE) {
1843 unsigned int tile_rows, tiles;
c2c75131 1844
bc752862
CW		 1845 tile_rows = *y / 8;
1846 *y %= 8;
c2c75131 1847
bc752862
CW		 1848 tiles = *x / (512/cpp);
1849 *x %= 512/cpp;
1850
1851 return tile_rows * pitch * 8 + tiles * 4096;
1852 } else {
1853 unsigned int offset;
1854
1855 offset = *y * pitch + *x * cpp;
1856 *y = 0;
1857 *x = (offset & 4095) / cpp;
1858 return offset & -4096;
1859 }
c2c75131
DV		 1860}
1861
17638cd6
JB		 1862static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1863 int x, int y)
81255565
JB		 1864{
1865 struct drm_device *dev = crtc->dev;
1866 struct drm_i915_private *dev_priv = dev->dev_private;
1867 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1868 struct intel_framebuffer *intel_fb;
05394f39 1869 struct drm_i915_gem_object *obj;
81255565 1870 int plane = intel_crtc->plane;
e506a0c6 1871 unsigned long linear_offset;
81255565 1872 u32 dspcntr;
5eddb70b 1873 u32 reg;
81255565
JB		 1874
1875 switch (plane) {
1876 case 0:
1877 case 1:
1878 break;
1879 default:
84f44ce7 1880 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 1881 return -EINVAL;
1882 }
1883
1884 intel_fb = to_intel_framebuffer(fb);
1885 obj = intel_fb->obj;
81255565 1886
5eddb70b
CW		 1887 reg = DSPCNTR(plane);
1888 dspcntr = I915_READ(reg);
81255565
JB		 1889 /* Mask out pixel format bits in case we change it */
1890 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 1891 switch (fb->pixel_format) {
1892 case DRM_FORMAT_C8:
81255565
JB		 1893 dspcntr |= DISPPLANE_8BPP;
1894 break;
57779d06
VS		 1895 case DRM_FORMAT_XRGB1555:
1896 case DRM_FORMAT_ARGB1555:
1897 dspcntr |= DISPPLANE_BGRX555;
81255565 1898 break;
57779d06
VS		 1899 case DRM_FORMAT_RGB565:
1900 dspcntr |= DISPPLANE_BGRX565;
1901 break;
1902 case DRM_FORMAT_XRGB8888:
1903 case DRM_FORMAT_ARGB8888:
1904 dspcntr |= DISPPLANE_BGRX888;
1905 break;
1906 case DRM_FORMAT_XBGR8888:
1907 case DRM_FORMAT_ABGR8888:
1908 dspcntr |= DISPPLANE_RGBX888;
1909 break;
1910 case DRM_FORMAT_XRGB2101010:
1911 case DRM_FORMAT_ARGB2101010:
1912 dspcntr |= DISPPLANE_BGRX101010;
1913 break;
1914 case DRM_FORMAT_XBGR2101010:
1915 case DRM_FORMAT_ABGR2101010:
1916 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 1917 break;
1918 default:
baba133a 1919 BUG();
81255565 1920 }
57779d06 1921
a6c45cf0 1922 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1923 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1924 dspcntr |= DISPPLANE_TILED;
1925 else
1926 dspcntr &= ~DISPPLANE_TILED;
1927 }
1928
de1aa629
VS		 1929 if (IS_G4X(dev))
1930 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1931
5eddb70b 1932 I915_WRITE(reg, dspcntr);
81255565 1933
e506a0c6 1934 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 1935
c2c75131
DV		 1936 if (INTEL_INFO(dev)->gen >= 4) {
1937 intel_crtc->dspaddr_offset =
bc752862
CW		 1938 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1939 fb->bits_per_pixel / 8,
1940 fb->pitches[0]);
c2c75131
DV		 1941 linear_offset -= intel_crtc->dspaddr_offset;
1942 } else {
e506a0c6 1943 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 1944 }
e506a0c6
DV		 1945
1946 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
1947 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 1948 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 1949 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 1950 I915_MODIFY_DISPBASE(DSPSURF(plane),
1951 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 1952 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 1953 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 1954 } else
e506a0c6 1955 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 1956 POSTING_READ(reg);
81255565 1957
17638cd6
JB		 1958 return 0;
1959}
1960
1961static int ironlake_update_plane(struct drm_crtc *crtc,
1962 struct drm_framebuffer *fb, int x, int y)
1963{
1964 struct drm_device *dev = crtc->dev;
1965 struct drm_i915_private *dev_priv = dev->dev_private;
1966 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1967 struct intel_framebuffer *intel_fb;
1968 struct drm_i915_gem_object *obj;
1969 int plane = intel_crtc->plane;
e506a0c6 1970 unsigned long linear_offset;
17638cd6
JB		 1971 u32 dspcntr;
1972 u32 reg;
1973
1974 switch (plane) {
1975 case 0:
1976 case 1:
27f8227b 1977 case 2:
17638cd6
JB		 1978 break;
1979 default:
84f44ce7 1980 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 1981 return -EINVAL;
1982 }
1983
1984 intel_fb = to_intel_framebuffer(fb);
1985 obj = intel_fb->obj;
1986
1987 reg = DSPCNTR(plane);
1988 dspcntr = I915_READ(reg);
1989 /* Mask out pixel format bits in case we change it */
1990 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 1991 switch (fb->pixel_format) {
1992 case DRM_FORMAT_C8:
17638cd6
JB		 1993 dspcntr |= DISPPLANE_8BPP;
1994 break;
57779d06
VS		 1995 case DRM_FORMAT_RGB565:
1996 dspcntr |= DISPPLANE_BGRX565;
17638cd6 1997 break;
57779d06
VS		 1998 case DRM_FORMAT_XRGB8888:
1999 case DRM_FORMAT_ARGB8888:
2000 dspcntr |= DISPPLANE_BGRX888;
2001 break;
2002 case DRM_FORMAT_XBGR8888:
2003 case DRM_FORMAT_ABGR8888:
2004 dspcntr |= DISPPLANE_RGBX888;
2005 break;
2006 case DRM_FORMAT_XRGB2101010:
2007 case DRM_FORMAT_ARGB2101010:
2008 dspcntr |= DISPPLANE_BGRX101010;
2009 break;
2010 case DRM_FORMAT_XBGR2101010:
2011 case DRM_FORMAT_ABGR2101010:
2012 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2013 break;
2014 default:
baba133a 2015 BUG();
17638cd6
JB		 2016 }
2017
2018 if (obj->tiling_mode != I915_TILING_NONE)
2019 dspcntr |= DISPPLANE_TILED;
2020 else
2021 dspcntr &= ~DISPPLANE_TILED;
2022
2023 /* must disable */
2024 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2025
2026 I915_WRITE(reg, dspcntr);
2027
e506a0c6 2028 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2029 intel_crtc->dspaddr_offset =
bc752862
CW		 2030 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2031 fb->bits_per_pixel / 8,
2032 fb->pitches[0]);
c2c75131 2033 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2034
e506a0c6
DV		 2035 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2036 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2037 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2038 I915_MODIFY_DISPBASE(DSPSURF(plane),
2039 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2040 if (IS_HASWELL(dev)) {
2041 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2042 } else {
2043 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2044 I915_WRITE(DSPLINOFF(plane), linear_offset);
2045 }
17638cd6
JB		 2046 POSTING_READ(reg);
2047
2048 return 0;
2049}
2050
2051/* Assume fb object is pinned & idle & fenced and just update base pointers */
2052static int
2053intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2054 int x, int y, enum mode_set_atomic state)
2055{
2056 struct drm_device *dev = crtc->dev;
2057 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2058
6b8e6ed0
CW		 2059 if (dev_priv->display.disable_fbc)
2060 dev_priv->display.disable_fbc(dev);
3dec0095 2061 intel_increase_pllclock(crtc);
81255565 2062
6b8e6ed0 2063 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2064}
2065
96a02917
VS		 2066void intel_display_handle_reset(struct drm_device *dev)
2067{
2068 struct drm_i915_private *dev_priv = dev->dev_private;
2069 struct drm_crtc *crtc;
2070
2071 /*
2072 * Flips in the rings have been nuked by the reset,
2073 * so complete all pending flips so that user space
2074 * will get its events and not get stuck.
2075 *
2076 * Also update the base address of all primary
2077 * planes to the the last fb to make sure we're
2078 * showing the correct fb after a reset.
2079 *
2080 * Need to make two loops over the crtcs so that we
2081 * don't try to grab a crtc mutex before the
2082 * pending_flip_queue really got woken up.
2083 */
2084
2085 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2086 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2087 enum plane plane = intel_crtc->plane;
2088
2089 intel_prepare_page_flip(dev, plane);
2090 intel_finish_page_flip_plane(dev, plane);
2091 }
2092
2093 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2094 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2095
2096 mutex_lock(&crtc->mutex);
2097 if (intel_crtc->active)
2098 dev_priv->display.update_plane(crtc, crtc->fb,
2099 crtc->x, crtc->y);
2100 mutex_unlock(&crtc->mutex);
2101 }
2102}
2103
14667a4b
CW		 2104static int
2105intel_finish_fb(struct drm_framebuffer *old_fb)
2106{
2107 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2108 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2109 bool was_interruptible = dev_priv->mm.interruptible;
2110 int ret;
2111
14667a4b
CW		 2112 /* Big Hammer, we also need to ensure that any pending
2113 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2114 * current scanout is retired before unpinning the old
2115 * framebuffer.
2116 *
2117 * This should only fail upon a hung GPU, in which case we
2118 * can safely continue.
2119 */
2120 dev_priv->mm.interruptible = false;
2121 ret = i915_gem_object_finish_gpu(obj);
2122 dev_priv->mm.interruptible = was_interruptible;
2123
2124 return ret;
2125}
2126
198598d0
VS		 2127static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2128{
2129 struct drm_device *dev = crtc->dev;
2130 struct drm_i915_master_private *master_priv;
2131 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2132
2133 if (!dev->primary->master)
2134 return;
2135
2136 master_priv = dev->primary->master->driver_priv;
2137 if (!master_priv->sarea_priv)
2138 return;
2139
2140 switch (intel_crtc->pipe) {
2141 case 0:
2142 master_priv->sarea_priv->pipeA_x = x;
2143 master_priv->sarea_priv->pipeA_y = y;
2144 break;
2145 case 1:
2146 master_priv->sarea_priv->pipeB_x = x;
2147 master_priv->sarea_priv->pipeB_y = y;
2148 break;
2149 default:
2150 break;
2151 }
2152}
2153
5c3b82e2 2154static int
3c4fdcfb 2155intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2156 struct drm_framebuffer *fb)
79e53945
JB		 2157{
2158 struct drm_device *dev = crtc->dev;
6b8e6ed0 2159 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2160 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2161 struct drm_framebuffer *old_fb;
5c3b82e2 2162 int ret;
79e53945
JB		 2163
2164 /* no fb bound */
94352cf9 2165 if (!fb) {
a5071c2f 2166 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2167 return 0;
2168 }
2169
7eb552ae 2170 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2171 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2172 plane_name(intel_crtc->plane),
2173 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2174 return -EINVAL;
79e53945
JB		 2175 }
2176
5c3b82e2 2177 mutex_lock(&dev->struct_mutex);
265db958 2178 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2179 to_intel_framebuffer(fb)->obj,
919926ae 2180 NULL);
5c3b82e2
CW		 2181 if (ret != 0) {
2182 mutex_unlock(&dev->struct_mutex);
a5071c2f 2183 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2184 return ret;
2185 }
79e53945 2186
94352cf9 2187 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2188 if (ret) {
94352cf9 2189 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2190 mutex_unlock(&dev->struct_mutex);
a5071c2f 2191 DRM_ERROR("failed to update base address\n");
4e6cfefc 2192 return ret;
79e53945 2193 }
3c4fdcfb 2194
94352cf9
DV		 2195 old_fb = crtc->fb;
2196 crtc->fb = fb;
6c4c86f5
DV		 2197 crtc->x = x;
2198 crtc->y = y;
94352cf9 2199
b7f1de28 2200 if (old_fb) {
d7697eea
DV		 2201 if (intel_crtc->active && old_fb != fb)
2202 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2203 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2204 }
652c393a 2205
6b8e6ed0 2206 intel_update_fbc(dev);
5c3b82e2 2207 mutex_unlock(&dev->struct_mutex);
79e53945 2208
198598d0 2209 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2210
2211 return 0;
79e53945
JB		 2212}
2213
5e84e1a4
ZW		 2214static void intel_fdi_normal_train(struct drm_crtc *crtc)
2215{
2216 struct drm_device *dev = crtc->dev;
2217 struct drm_i915_private *dev_priv = dev->dev_private;
2218 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2219 int pipe = intel_crtc->pipe;
2220 u32 reg, temp;
2221
2222 /* enable normal train */
2223 reg = FDI_TX_CTL(pipe);
2224 temp = I915_READ(reg);
61e499bf 2225 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2226 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2227 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2228 } else {
2229 temp &= ~FDI_LINK_TRAIN_NONE;
2230 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2231 }
5e84e1a4
ZW		 2232 I915_WRITE(reg, temp);
2233
2234 reg = FDI_RX_CTL(pipe);
2235 temp = I915_READ(reg);
2236 if (HAS_PCH_CPT(dev)) {
2237 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2238 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2239 } else {
2240 temp &= ~FDI_LINK_TRAIN_NONE;
2241 temp |= FDI_LINK_TRAIN_NONE;
2242 }
2243 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2244
2245 /* wait one idle pattern time */
2246 POSTING_READ(reg);
2247 udelay(1000);
357555c0
JB		 2248
2249 /* IVB wants error correction enabled */
2250 if (IS_IVYBRIDGE(dev))
2251 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2252 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2253}
2254
1e833f40
DV		 2255static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2256{
2257 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2258}
2259
01a415fd
DV		 2260static void ivb_modeset_global_resources(struct drm_device *dev)
2261{
2262 struct drm_i915_private *dev_priv = dev->dev_private;
2263 struct intel_crtc *pipe_B_crtc =
2264 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2265 struct intel_crtc *pipe_C_crtc =
2266 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2267 uint32_t temp;
2268
1e833f40
DV		 2269 /*
2270 * When everything is off disable fdi C so that we could enable fdi B
2271 * with all lanes. Note that we don't care about enabled pipes without
2272 * an enabled pch encoder.
2273 */
2274 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2275 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2276 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2277 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2278
2279 temp = I915_READ(SOUTH_CHICKEN1);
2280 temp &= ~FDI_BC_BIFURCATION_SELECT;
2281 DRM_DEBUG_KMS("disabling fdi C rx\n");
2282 I915_WRITE(SOUTH_CHICKEN1, temp);
2283 }
2284}
2285
8db9d77b
ZW		 2286/* The FDI link training functions for ILK/Ibexpeak. */
2287static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2288{
2289 struct drm_device *dev = crtc->dev;
2290 struct drm_i915_private *dev_priv = dev->dev_private;
2291 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2292 int pipe = intel_crtc->pipe;
0fc932b8 2293 int plane = intel_crtc->plane;
5eddb70b 2294 u32 reg, temp, tries;
8db9d77b 2295
0fc932b8
JB		 2296 /* FDI needs bits from pipe & plane first */
2297 assert_pipe_enabled(dev_priv, pipe);
2298 assert_plane_enabled(dev_priv, plane);
2299
e1a44743
AJ		 2300 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2301 for train result */
5eddb70b
CW		 2302 reg = FDI_RX_IMR(pipe);
2303 temp = I915_READ(reg);
e1a44743
AJ		 2304 temp &= ~FDI_RX_SYMBOL_LOCK;
2305 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2306 I915_WRITE(reg, temp);
2307 I915_READ(reg);
e1a44743
AJ		 2308 udelay(150);
2309
8db9d77b 2310 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2311 reg = FDI_TX_CTL(pipe);
2312 temp = I915_READ(reg);
627eb5a3
DV		 2313 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2314 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2315 temp &= ~FDI_LINK_TRAIN_NONE;
2316 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2317 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2318
5eddb70b
CW		 2319 reg = FDI_RX_CTL(pipe);
2320 temp = I915_READ(reg);
8db9d77b
ZW		 2321 temp &= ~FDI_LINK_TRAIN_NONE;
2322 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2323 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2324
2325 POSTING_READ(reg);
8db9d77b
ZW		 2326 udelay(150);
2327
5b2adf89 2328 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2329 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2330 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2331 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2332
5eddb70b 2333 reg = FDI_RX_IIR(pipe);
e1a44743 2334 for (tries = 0; tries < 5; tries++) {
5eddb70b 2335 temp = I915_READ(reg);
8db9d77b
ZW		 2336 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2337
2338 if ((temp & FDI_RX_BIT_LOCK)) {
2339 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2340 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2341 break;
2342 }
8db9d77b 2343 }
e1a44743 2344 if (tries == 5)
5eddb70b 2345 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2346
2347 /* Train 2 */
5eddb70b
CW		 2348 reg = FDI_TX_CTL(pipe);
2349 temp = I915_READ(reg);
8db9d77b
ZW		 2350 temp &= ~FDI_LINK_TRAIN_NONE;
2351 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2352 I915_WRITE(reg, temp);
8db9d77b 2353
5eddb70b
CW		 2354 reg = FDI_RX_CTL(pipe);
2355 temp = I915_READ(reg);
8db9d77b
ZW		 2356 temp &= ~FDI_LINK_TRAIN_NONE;
2357 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2358 I915_WRITE(reg, temp);
8db9d77b 2359
5eddb70b
CW		 2360 POSTING_READ(reg);
2361 udelay(150);
8db9d77b 2362
5eddb70b 2363 reg = FDI_RX_IIR(pipe);
e1a44743 2364 for (tries = 0; tries < 5; tries++) {
5eddb70b 2365 temp = I915_READ(reg);
8db9d77b
ZW		 2366 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2367
2368 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2369 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2370 DRM_DEBUG_KMS("FDI train 2 done.\n");
2371 break;
2372 }
8db9d77b 2373 }
e1a44743 2374 if (tries == 5)
5eddb70b 2375 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2376
2377 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2378
8db9d77b
ZW		 2379}
2380
0206e353 2381static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2382 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2383 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2384 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2385 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2386};
2387
2388/* The FDI link training functions for SNB/Cougarpoint. */
2389static void gen6_fdi_link_train(struct drm_crtc *crtc)
2390{
2391 struct drm_device *dev = crtc->dev;
2392 struct drm_i915_private *dev_priv = dev->dev_private;
2393 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2394 int pipe = intel_crtc->pipe;
fa37d39e 2395 u32 reg, temp, i, retry;
8db9d77b 2396
e1a44743
AJ		 2397 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2398 for train result */
5eddb70b
CW		 2399 reg = FDI_RX_IMR(pipe);
2400 temp = I915_READ(reg);
e1a44743
AJ		 2401 temp &= ~FDI_RX_SYMBOL_LOCK;
2402 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2403 I915_WRITE(reg, temp);
2404
2405 POSTING_READ(reg);
e1a44743
AJ		 2406 udelay(150);
2407
8db9d77b 2408 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2409 reg = FDI_TX_CTL(pipe);
2410 temp = I915_READ(reg);
627eb5a3
DV		 2411 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2412 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2413 temp &= ~FDI_LINK_TRAIN_NONE;
2414 temp |= FDI_LINK_TRAIN_PATTERN_1;
2415 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2416 /* SNB-B */
2417 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2418 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2419
d74cf324
DV		 2420 I915_WRITE(FDI_RX_MISC(pipe),
2421 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2422
5eddb70b
CW		 2423 reg = FDI_RX_CTL(pipe);
2424 temp = I915_READ(reg);
8db9d77b
ZW		 2425 if (HAS_PCH_CPT(dev)) {
2426 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2427 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2428 } else {
2429 temp &= ~FDI_LINK_TRAIN_NONE;
2430 temp |= FDI_LINK_TRAIN_PATTERN_1;
2431 }
5eddb70b
CW		 2432 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2433
2434 POSTING_READ(reg);
8db9d77b
ZW		 2435 udelay(150);
2436
0206e353 2437 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2438 reg = FDI_TX_CTL(pipe);
2439 temp = I915_READ(reg);
8db9d77b
ZW		 2440 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2441 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2442 I915_WRITE(reg, temp);
2443
2444 POSTING_READ(reg);
8db9d77b
ZW		 2445 udelay(500);
2446
fa37d39e
SP		 2447 for (retry = 0; retry < 5; retry++) {
2448 reg = FDI_RX_IIR(pipe);
2449 temp = I915_READ(reg);
2450 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2451 if (temp & FDI_RX_BIT_LOCK) {
2452 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2453 DRM_DEBUG_KMS("FDI train 1 done.\n");
2454 break;
2455 }
2456 udelay(50);
8db9d77b 2457 }
fa37d39e
SP		 2458 if (retry < 5)
2459 break;
8db9d77b
ZW		 2460 }
2461 if (i == 4)
5eddb70b 2462 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2463
2464 /* Train 2 */
5eddb70b
CW		 2465 reg = FDI_TX_CTL(pipe);
2466 temp = I915_READ(reg);
8db9d77b
ZW		 2467 temp &= ~FDI_LINK_TRAIN_NONE;
2468 temp |= FDI_LINK_TRAIN_PATTERN_2;
2469 if (IS_GEN6(dev)) {
2470 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2471 /* SNB-B */
2472 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2473 }
5eddb70b 2474 I915_WRITE(reg, temp);
8db9d77b 2475
5eddb70b
CW		 2476 reg = FDI_RX_CTL(pipe);
2477 temp = I915_READ(reg);
8db9d77b
ZW		 2478 if (HAS_PCH_CPT(dev)) {
2479 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2480 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2481 } else {
2482 temp &= ~FDI_LINK_TRAIN_NONE;
2483 temp |= FDI_LINK_TRAIN_PATTERN_2;
2484 }
5eddb70b
CW		 2485 I915_WRITE(reg, temp);
2486
2487 POSTING_READ(reg);
8db9d77b
ZW		 2488 udelay(150);
2489
0206e353 2490 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2491 reg = FDI_TX_CTL(pipe);
2492 temp = I915_READ(reg);
8db9d77b
ZW		 2493 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2494 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2495 I915_WRITE(reg, temp);
2496
2497 POSTING_READ(reg);
8db9d77b
ZW		 2498 udelay(500);
2499
fa37d39e
SP		 2500 for (retry = 0; retry < 5; retry++) {
2501 reg = FDI_RX_IIR(pipe);
2502 temp = I915_READ(reg);
2503 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2504 if (temp & FDI_RX_SYMBOL_LOCK) {
2505 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2506 DRM_DEBUG_KMS("FDI train 2 done.\n");
2507 break;
2508 }
2509 udelay(50);
8db9d77b 2510 }
fa37d39e
SP		 2511 if (retry < 5)
2512 break;
8db9d77b
ZW		 2513 }
2514 if (i == 4)
5eddb70b 2515 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2516
2517 DRM_DEBUG_KMS("FDI train done.\n");
2518}
2519
357555c0
JB		 2520/* Manual link training for Ivy Bridge A0 parts */
2521static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2522{
2523 struct drm_device *dev = crtc->dev;
2524 struct drm_i915_private *dev_priv = dev->dev_private;
2525 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2526 int pipe = intel_crtc->pipe;
2527 u32 reg, temp, i;
2528
2529 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2530 for train result */
2531 reg = FDI_RX_IMR(pipe);
2532 temp = I915_READ(reg);
2533 temp &= ~FDI_RX_SYMBOL_LOCK;
2534 temp &= ~FDI_RX_BIT_LOCK;
2535 I915_WRITE(reg, temp);
2536
2537 POSTING_READ(reg);
2538 udelay(150);
2539
01a415fd
DV		 2540 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2541 I915_READ(FDI_RX_IIR(pipe)));
2542
357555c0
JB		 2543 /* enable CPU FDI TX and PCH FDI RX */
2544 reg = FDI_TX_CTL(pipe);
2545 temp = I915_READ(reg);
627eb5a3
DV		 2546 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2547 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
357555c0
JB		 2548 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2549 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2550 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2551 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2552 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2553 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2554
d74cf324
DV		 2555 I915_WRITE(FDI_RX_MISC(pipe),
2556 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2557
357555c0
JB		 2558 reg = FDI_RX_CTL(pipe);
2559 temp = I915_READ(reg);
2560 temp &= ~FDI_LINK_TRAIN_AUTO;
2561 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2562 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2563 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2564 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2565
2566 POSTING_READ(reg);
2567 udelay(150);
2568
0206e353 2569 for (i = 0; i < 4; i++) {
357555c0
JB		 2570 reg = FDI_TX_CTL(pipe);
2571 temp = I915_READ(reg);
2572 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2573 temp |= snb_b_fdi_train_param[i];
2574 I915_WRITE(reg, temp);
2575
2576 POSTING_READ(reg);
2577 udelay(500);
2578
2579 reg = FDI_RX_IIR(pipe);
2580 temp = I915_READ(reg);
2581 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2582
2583 if (temp & FDI_RX_BIT_LOCK ||
2584 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2585 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2586 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2587 break;
2588 }
2589 }
2590 if (i == 4)
2591 DRM_ERROR("FDI train 1 fail!\n");
2592
2593 /* Train 2 */
2594 reg = FDI_TX_CTL(pipe);
2595 temp = I915_READ(reg);
2596 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2597 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2598 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2599 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2600 I915_WRITE(reg, temp);
2601
2602 reg = FDI_RX_CTL(pipe);
2603 temp = I915_READ(reg);
2604 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2605 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2606 I915_WRITE(reg, temp);
2607
2608 POSTING_READ(reg);
2609 udelay(150);
2610
0206e353 2611 for (i = 0; i < 4; i++) {
357555c0
JB		 2612 reg = FDI_TX_CTL(pipe);
2613 temp = I915_READ(reg);
2614 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2615 temp |= snb_b_fdi_train_param[i];
2616 I915_WRITE(reg, temp);
2617
2618 POSTING_READ(reg);
2619 udelay(500);
2620
2621 reg = FDI_RX_IIR(pipe);
2622 temp = I915_READ(reg);
2623 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2624
2625 if (temp & FDI_RX_SYMBOL_LOCK) {
2626 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2627 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2628 break;
2629 }
2630 }
2631 if (i == 4)
2632 DRM_ERROR("FDI train 2 fail!\n");
2633
2634 DRM_DEBUG_KMS("FDI train done.\n");
2635}
2636
88cefb6c 2637static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2638{
88cefb6c 2639 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2640 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2641 int pipe = intel_crtc->pipe;
5eddb70b 2642 u32 reg, temp;
79e53945 2643
c64e311e 2644
c98e9dcf 2645 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2646 reg = FDI_RX_CTL(pipe);
2647 temp = I915_READ(reg);
627eb5a3
DV		 2648 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2649 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2650 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2651 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2652
2653 POSTING_READ(reg);
c98e9dcf
JB		 2654 udelay(200);
2655
2656 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2657 temp = I915_READ(reg);
2658 I915_WRITE(reg, temp | FDI_PCDCLK);
2659
2660 POSTING_READ(reg);
c98e9dcf
JB		 2661 udelay(200);
2662
20749730
PZ		 2663 /* Enable CPU FDI TX PLL, always on for Ironlake */
2664 reg = FDI_TX_CTL(pipe);
2665 temp = I915_READ(reg);
2666 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2667 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2668
20749730
PZ		 2669 POSTING_READ(reg);
2670 udelay(100);
6be4a607 2671 }
0e23b99d
JB		 2672}
2673
88cefb6c
DV		 2674static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2675{
2676 struct drm_device *dev = intel_crtc->base.dev;
2677 struct drm_i915_private *dev_priv = dev->dev_private;
2678 int pipe = intel_crtc->pipe;
2679 u32 reg, temp;
2680
2681 /* Switch from PCDclk to Rawclk */
2682 reg = FDI_RX_CTL(pipe);
2683 temp = I915_READ(reg);
2684 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2685
2686 /* Disable CPU FDI TX PLL */
2687 reg = FDI_TX_CTL(pipe);
2688 temp = I915_READ(reg);
2689 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2690
2691 POSTING_READ(reg);
2692 udelay(100);
2693
2694 reg = FDI_RX_CTL(pipe);
2695 temp = I915_READ(reg);
2696 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2697
2698 /* Wait for the clocks to turn off. */
2699 POSTING_READ(reg);
2700 udelay(100);
2701}
2702
0fc932b8
JB		 2703static void ironlake_fdi_disable(struct drm_crtc *crtc)
2704{
2705 struct drm_device *dev = crtc->dev;
2706 struct drm_i915_private *dev_priv = dev->dev_private;
2707 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2708 int pipe = intel_crtc->pipe;
2709 u32 reg, temp;
2710
2711 /* disable CPU FDI tx and PCH FDI rx */
2712 reg = FDI_TX_CTL(pipe);
2713 temp = I915_READ(reg);
2714 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2715 POSTING_READ(reg);
2716
2717 reg = FDI_RX_CTL(pipe);
2718 temp = I915_READ(reg);
2719 temp &= ~(0x7 << 16);
dfd07d72 2720 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2721 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2722
2723 POSTING_READ(reg);
2724 udelay(100);
2725
2726 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2727 if (HAS_PCH_IBX(dev)) {
2728 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2729 }
0fc932b8
JB		 2730
2731 /* still set train pattern 1 */
2732 reg = FDI_TX_CTL(pipe);
2733 temp = I915_READ(reg);
2734 temp &= ~FDI_LINK_TRAIN_NONE;
2735 temp |= FDI_LINK_TRAIN_PATTERN_1;
2736 I915_WRITE(reg, temp);
2737
2738 reg = FDI_RX_CTL(pipe);
2739 temp = I915_READ(reg);
2740 if (HAS_PCH_CPT(dev)) {
2741 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2742 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2743 } else {
2744 temp &= ~FDI_LINK_TRAIN_NONE;
2745 temp |= FDI_LINK_TRAIN_PATTERN_1;
2746 }
2747 /* BPC in FDI rx is consistent with that in PIPECONF */
2748 temp &= ~(0x07 << 16);
dfd07d72 2749 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2750 I915_WRITE(reg, temp);
2751
2752 POSTING_READ(reg);
2753 udelay(100);
2754}
2755
5bb61643
CW		 2756static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2757{
2758 struct drm_device *dev = crtc->dev;
2759 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2760 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2761 unsigned long flags;
2762 bool pending;
2763
10d83730
VS		 2764 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2765 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2766 return false;
2767
2768 spin_lock_irqsave(&dev->event_lock, flags);
2769 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2770 spin_unlock_irqrestore(&dev->event_lock, flags);
2771
2772 return pending;
2773}
2774
e6c3a2a6
CW		 2775static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2776{
0f91128d 2777 struct drm_device *dev = crtc->dev;
5bb61643 2778 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2779
2780 if (crtc->fb == NULL)
2781 return;
2782
2c10d571
DV		 2783 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2784
5bb61643
CW		 2785 wait_event(dev_priv->pending_flip_queue,
2786 !intel_crtc_has_pending_flip(crtc));
2787
0f91128d
CW		 2788 mutex_lock(&dev->struct_mutex);
2789 intel_finish_fb(crtc->fb);
2790 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2791}
2792
e615efe4
ED		 2793/* Program iCLKIP clock to the desired frequency */
2794static void lpt_program_iclkip(struct drm_crtc *crtc)
2795{
2796 struct drm_device *dev = crtc->dev;
2797 struct drm_i915_private *dev_priv = dev->dev_private;
2798 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2799 u32 temp;
2800
09153000
DV		 2801 mutex_lock(&dev_priv->dpio_lock);
2802
e615efe4
ED		 2803 /* It is necessary to ungate the pixclk gate prior to programming
2804 * the divisors, and gate it back when it is done.
2805 */
2806 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2807
2808 /* Disable SSCCTL */
2809 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2810 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2811 SBI_SSCCTL_DISABLE,
2812 SBI_ICLK);
e615efe4
ED		 2813
2814 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2815 if (crtc->mode.clock == 20000) {
2816 auxdiv = 1;
2817 divsel = 0x41;
2818 phaseinc = 0x20;
2819 } else {
2820 /* The iCLK virtual clock root frequency is in MHz,
2821 * but the crtc->mode.clock in in KHz. To get the divisors,
2822 * it is necessary to divide one by another, so we
2823 * convert the virtual clock precision to KHz here for higher
2824 * precision.
2825 */
2826 u32 iclk_virtual_root_freq = 172800 * 1000;
2827 u32 iclk_pi_range = 64;
2828 u32 desired_divisor, msb_divisor_value, pi_value;
2829
2830 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2831 msb_divisor_value = desired_divisor / iclk_pi_range;
2832 pi_value = desired_divisor % iclk_pi_range;
2833
2834 auxdiv = 0;
2835 divsel = msb_divisor_value - 2;
2836 phaseinc = pi_value;
2837 }
2838
2839 /* This should not happen with any sane values */
2840 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2841 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2842 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2843 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2844
2845 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2846 crtc->mode.clock,
2847 auxdiv,
2848 divsel,
2849 phasedir,
2850 phaseinc);
2851
2852 /* Program SSCDIVINTPHASE6 */
988d6ee8 2853 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2854 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2855 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2856 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2857 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2858 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2859 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2860 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2861
2862 /* Program SSCAUXDIV */
988d6ee8 2863 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2864 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2865 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2866 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2867
2868 /* Enable modulator and associated divider */
988d6ee8 2869 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2870 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2871 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2872
2873 /* Wait for initialization time */
2874 udelay(24);
2875
2876 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2877
2878 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2879}
2880
275f01b2
DV		 2881static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2882 enum pipe pch_transcoder)
2883{
2884 struct drm_device *dev = crtc->base.dev;
2885 struct drm_i915_private *dev_priv = dev->dev_private;
2886 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2887
2888 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2889 I915_READ(HTOTAL(cpu_transcoder)));
2890 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2891 I915_READ(HBLANK(cpu_transcoder)));
2892 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2893 I915_READ(HSYNC(cpu_transcoder)));
2894
2895 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2896 I915_READ(VTOTAL(cpu_transcoder)));
2897 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2898 I915_READ(VBLANK(cpu_transcoder)));
2899 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2900 I915_READ(VSYNC(cpu_transcoder)));
2901 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2902 I915_READ(VSYNCSHIFT(cpu_transcoder)));
2903}
2904
f67a559d
JB		 2905/*
2906 * Enable PCH resources required for PCH ports:
2907 * - PCH PLLs
2908 * - FDI training & RX/TX
2909 * - update transcoder timings
2910 * - DP transcoding bits
2911 * - transcoder
2912 */
2913static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2914{
2915 struct drm_device *dev = crtc->dev;
2916 struct drm_i915_private *dev_priv = dev->dev_private;
2917 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2918 int pipe = intel_crtc->pipe;
ee7b9f93 2919 u32 reg, temp;
2c07245f 2920
ab9412ba 2921 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 2922
cd986abb
DV		 2923 /* Write the TU size bits before fdi link training, so that error
2924 * detection works. */
2925 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2926 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2927
c98e9dcf 2928 /* For PCH output, training FDI link */
674cf967 2929 dev_priv->display.fdi_link_train(crtc);
2c07245f 2930
572deb37
DV		 2931 /* XXX: pch pll's can be enabled any time before we enable the PCH
2932 * transcoder, and we actually should do this to not upset any PCH
2933 * transcoder that already use the clock when we share it.
2934 *
e72f9fbf
DV		 2935 * Note that enable_shared_dpll tries to do the right thing, but
2936 * get_shared_dpll unconditionally resets the pll - we need that to have
2937 * the right LVDS enable sequence. */
2938 ironlake_enable_shared_dpll(intel_crtc);
6f13b7b5 2939
303b81e0 2940 if (HAS_PCH_CPT(dev)) {
ee7b9f93 2941 u32 sel;
4b645f14 2942
c98e9dcf 2943 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 2944 temp |= TRANS_DPLL_ENABLE(pipe);
2945 sel = TRANS_DPLLB_SEL(pipe);
a43f6e0f 2946 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 2947 temp |= sel;
2948 else
2949 temp &= ~sel;
c98e9dcf 2950 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2951 }
5eddb70b 2952
d9b6cb56
JB		 2953 /* set transcoder timing, panel must allow it */
2954 assert_panel_unlocked(dev_priv, pipe);
275f01b2 2955 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 2956
303b81e0 2957 intel_fdi_normal_train(crtc);
5e84e1a4 2958
c98e9dcf
JB		 2959 /* For PCH DP, enable TRANS_DP_CTL */
2960 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 2961 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2962 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 2963 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 2964 reg = TRANS_DP_CTL(pipe);
2965 temp = I915_READ(reg);
2966 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 2967 TRANS_DP_SYNC_MASK |
2968 TRANS_DP_BPC_MASK);
5eddb70b
CW		 2969 temp |= (TRANS_DP_OUTPUT_ENABLE |
2970 TRANS_DP_ENH_FRAMING);
9325c9f0 2971 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 2972
2973 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 2974 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 2975 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 2976 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 2977
2978 switch (intel_trans_dp_port_sel(crtc)) {
2979 case PCH_DP_B:
5eddb70b 2980 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 2981 break;
2982 case PCH_DP_C:
5eddb70b 2983 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 2984 break;
2985 case PCH_DP_D:
5eddb70b 2986 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 2987 break;
2988 default:
e95d41e1 2989 BUG();
32f9d658 2990 }
2c07245f 2991
5eddb70b 2992 I915_WRITE(reg, temp);
6be4a607 2993 }
b52eb4dc 2994
b8a4f404 2995 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 2996}
2997
1507e5bd
PZ		 2998static void lpt_pch_enable(struct drm_crtc *crtc)
2999{
3000 struct drm_device *dev = crtc->dev;
3001 struct drm_i915_private *dev_priv = dev->dev_private;
3002 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3003 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3004
ab9412ba 3005 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3006
8c52b5e8 3007 lpt_program_iclkip(crtc);
1507e5bd 3008
0540e488 3009 /* Set transcoder timing. */
275f01b2 3010 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3011
937bb610 3012 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3013}
3014
e2b78267 3015static void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3016{
e2b78267 3017 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 3018
3019 if (pll == NULL)
3020 return;
3021
3022 if (pll->refcount == 0) {
46edb027 3023 WARN(1, "bad %s refcount\n", pll->name);
ee7b9f93
JB		 3024 return;
3025 }
3026
f4a091c7
DV		 3027 if (--pll->refcount == 0) {
3028 WARN_ON(pll->on);
3029 WARN_ON(pll->active);
3030 }
3031
a43f6e0f 3032 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 3033}
3034
e2b78267 3035static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, u32 dpll, u32 fp)
ee7b9f93 3036{
e2b78267
DV		 3037 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3038 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3039 enum intel_dpll_id i;
ee7b9f93 3040
ee7b9f93 3041 if (pll) {
46edb027
DV		 3042 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3043 crtc->base.base.id, pll->name);
e2b78267 3044 intel_put_shared_dpll(crtc);
ee7b9f93
JB		 3045 }
3046
98b6bd99
DV		 3047 if (HAS_PCH_IBX(dev_priv->dev)) {
3048 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
e2b78267 3049 i = crtc->pipe;
e72f9fbf 3050 pll = &dev_priv->shared_dplls[i];
98b6bd99 3051
46edb027
DV		 3052 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3053 crtc->base.base.id, pll->name);
98b6bd99
DV		 3054
3055 goto found;
3056 }
3057
e72f9fbf
DV		 3058 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3059 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 3060
3061 /* Only want to check enabled timings first */
3062 if (pll->refcount == 0)
3063 continue;
3064
e9a632a5
DV		 3065 if (dpll == (I915_READ(PCH_DPLL(pll->id)) & 0x7fffffff) &&
3066 fp == I915_READ(PCH_FP0(pll->id))) {
46edb027 3067 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
e2b78267 3068 crtc->base.base.id,
46edb027 3069 pll->name, pll->refcount, pll->active);
ee7b9f93
JB		 3070
3071 goto found;
3072 }
3073 }
3074
3075 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 3076 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3077 pll = &dev_priv->shared_dplls[i];
ee7b9f93 3078 if (pll->refcount == 0) {
46edb027
DV		 3079 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3080 crtc->base.base.id, pll->name);
ee7b9f93
JB		 3081 goto found;
3082 }
3083 }
3084
3085 return NULL;
3086
3087found:
a43f6e0f 3088 crtc->config.shared_dpll = i;
46edb027
DV		 3089 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3090 pipe_name(crtc->pipe));
cdbd2316 3091 if (pll->active == 0) {
46edb027 3092 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
cdbd2316 3093 WARN_ON(pll->on);
e9d6944e 3094 assert_shared_dpll_disabled(dev_priv, pll);
ee7b9f93 3095
cdbd2316 3096 /* Wait for the clocks to stabilize before rewriting the regs */
e9a632a5
DV		 3097 I915_WRITE(PCH_DPLL(pll->id), dpll & ~DPLL_VCO_ENABLE);
3098 POSTING_READ(PCH_DPLL(pll->id));
cdbd2316
DV		 3099 udelay(150);
3100
e9a632a5
DV		 3101 I915_WRITE(PCH_FP0(pll->id), fp);
3102 I915_WRITE(PCH_DPLL(pll->id), dpll & ~DPLL_VCO_ENABLE);
cdbd2316
DV		 3103 }
3104 pll->refcount++;
e04c7350 3105
ee7b9f93
JB		 3106 return pll;
3107}
3108
a1520318 3109static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3110{
3111 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3112 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3113 u32 temp;
3114
3115 temp = I915_READ(dslreg);
3116 udelay(500);
3117 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3118 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3119 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3120 }
3121}
3122
b074cec8
JB		 3123static void ironlake_pfit_enable(struct intel_crtc *crtc)
3124{
3125 struct drm_device *dev = crtc->base.dev;
3126 struct drm_i915_private *dev_priv = dev->dev_private;
3127 int pipe = crtc->pipe;
3128
0ef37f3f 3129 if (crtc->config.pch_pfit.size) {
b074cec8
JB		 3130 /* Force use of hard-coded filter coefficients
3131 * as some pre-programmed values are broken,
3132 * e.g. x201.
3133 */
3134 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3135 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3136 PF_PIPE_SEL_IVB(pipe));
3137 else
3138 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3139 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3140 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3141 }
3142}
3143
bb53d4ae
VS		 3144static void intel_enable_planes(struct drm_crtc *crtc)
3145{
3146 struct drm_device *dev = crtc->dev;
3147 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3148 struct intel_plane *intel_plane;
3149
3150 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3151 if (intel_plane->pipe == pipe)
3152 intel_plane_restore(&intel_plane->base);
3153}
3154
3155static void intel_disable_planes(struct drm_crtc *crtc)
3156{
3157 struct drm_device *dev = crtc->dev;
3158 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3159 struct intel_plane *intel_plane;
3160
3161 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3162 if (intel_plane->pipe == pipe)
3163 intel_plane_disable(&intel_plane->base);
3164}
3165
f67a559d
JB		 3166static void ironlake_crtc_enable(struct drm_crtc *crtc)
3167{
3168 struct drm_device *dev = crtc->dev;
3169 struct drm_i915_private *dev_priv = dev->dev_private;
3170 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3171 struct intel_encoder *encoder;
f67a559d
JB		 3172 int pipe = intel_crtc->pipe;
3173 int plane = intel_crtc->plane;
3174 u32 temp;
f67a559d 3175
08a48469
DV		 3176 WARN_ON(!crtc->enabled);
3177
f67a559d
JB		 3178 if (intel_crtc->active)
3179 return;
3180
3181 intel_crtc->active = true;
8664281b
PZ		 3182
3183 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3184 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3185
f67a559d
JB		 3186 intel_update_watermarks(dev);
3187
3188 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3189 temp = I915_READ(PCH_LVDS);
3190 if ((temp & LVDS_PORT_EN) == 0)
3191 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3192 }
3193
f67a559d 3194
5bfe2ac0 3195 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3196 /* Note: FDI PLL enabling _must_ be done before we enable the
3197 * cpu pipes, hence this is separate from all the other fdi/pch
3198 * enabling. */
88cefb6c 3199 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3200 } else {
3201 assert_fdi_tx_disabled(dev_priv, pipe);
3202 assert_fdi_rx_disabled(dev_priv, pipe);
3203 }
f67a559d 3204
bf49ec8c
DV		 3205 for_each_encoder_on_crtc(dev, crtc, encoder)
3206 if (encoder->pre_enable)
3207 encoder->pre_enable(encoder);
f67a559d
JB		 3208
3209 /* Enable panel fitting for LVDS */
b074cec8 3210 ironlake_pfit_enable(intel_crtc);
f67a559d 3211
9c54c0dd
JB		 3212 /*
3213 * On ILK+ LUT must be loaded before the pipe is running but with
3214 * clocks enabled
3215 */
3216 intel_crtc_load_lut(crtc);
3217
5bfe2ac0
DV		 3218 intel_enable_pipe(dev_priv, pipe,
3219 intel_crtc->config.has_pch_encoder);
f67a559d 3220 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3221 intel_enable_planes(crtc);
5c38d48c 3222 intel_crtc_update_cursor(crtc, true);
f67a559d 3223
5bfe2ac0 3224 if (intel_crtc->config.has_pch_encoder)
f67a559d 3225 ironlake_pch_enable(crtc);
c98e9dcf 3226
d1ebd816 3227 mutex_lock(&dev->struct_mutex);
bed4a673 3228 intel_update_fbc(dev);
d1ebd816
BW		 3229 mutex_unlock(&dev->struct_mutex);
3230
fa5c73b1
DV		 3231 for_each_encoder_on_crtc(dev, crtc, encoder)
3232 encoder->enable(encoder);
61b77ddd
DV		 3233
3234 if (HAS_PCH_CPT(dev))
a1520318 3235 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3236
3237 /*
3238 * There seems to be a race in PCH platform hw (at least on some
3239 * outputs) where an enabled pipe still completes any pageflip right
3240 * away (as if the pipe is off) instead of waiting for vblank. As soon
3241 * as the first vblank happend, everything works as expected. Hence just
3242 * wait for one vblank before returning to avoid strange things
3243 * happening.
3244 */
3245 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3246}
3247
42db64ef
PZ		 3248/* IPS only exists on ULT machines and is tied to pipe A. */
3249static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3250{
3251 return IS_ULT(crtc->base.dev) && crtc->pipe == PIPE_A;
3252}
3253
3254static void hsw_enable_ips(struct intel_crtc *crtc)
3255{
3256 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3257
3258 if (!crtc->config.ips_enabled)
3259 return;
3260
3261 /* We can only enable IPS after we enable a plane and wait for a vblank.
3262 * We guarantee that the plane is enabled by calling intel_enable_ips
3263 * only after intel_enable_plane. And intel_enable_plane already waits
3264 * for a vblank, so all we need to do here is to enable the IPS bit. */
3265 assert_plane_enabled(dev_priv, crtc->plane);
3266 I915_WRITE(IPS_CTL, IPS_ENABLE);
3267}
3268
3269static void hsw_disable_ips(struct intel_crtc *crtc)
3270{
3271 struct drm_device *dev = crtc->base.dev;
3272 struct drm_i915_private *dev_priv = dev->dev_private;
3273
3274 if (!crtc->config.ips_enabled)
3275 return;
3276
3277 assert_plane_enabled(dev_priv, crtc->plane);
3278 I915_WRITE(IPS_CTL, 0);
3279
3280 /* We need to wait for a vblank before we can disable the plane. */
3281 intel_wait_for_vblank(dev, crtc->pipe);
3282}
3283
4f771f10
PZ		 3284static void haswell_crtc_enable(struct drm_crtc *crtc)
3285{
3286 struct drm_device *dev = crtc->dev;
3287 struct drm_i915_private *dev_priv = dev->dev_private;
3288 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3289 struct intel_encoder *encoder;
3290 int pipe = intel_crtc->pipe;
3291 int plane = intel_crtc->plane;
4f771f10
PZ		 3292
3293 WARN_ON(!crtc->enabled);
3294
3295 if (intel_crtc->active)
3296 return;
3297
3298 intel_crtc->active = true;
8664281b
PZ		 3299
3300 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3301 if (intel_crtc->config.has_pch_encoder)
3302 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3303
4f771f10
PZ		 3304 intel_update_watermarks(dev);
3305
5bfe2ac0 3306 if (intel_crtc->config.has_pch_encoder)
04945641 3307 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3308
3309 for_each_encoder_on_crtc(dev, crtc, encoder)
3310 if (encoder->pre_enable)
3311 encoder->pre_enable(encoder);
3312
1f544388 3313 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3314
1f544388 3315 /* Enable panel fitting for eDP */
b074cec8 3316 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3317
3318 /*
3319 * On ILK+ LUT must be loaded before the pipe is running but with
3320 * clocks enabled
3321 */
3322 intel_crtc_load_lut(crtc);
3323
1f544388 3324 intel_ddi_set_pipe_settings(crtc);
8228c251 3325 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3326
5bfe2ac0
DV		 3327 intel_enable_pipe(dev_priv, pipe,
3328 intel_crtc->config.has_pch_encoder);
4f771f10 3329 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3330 intel_enable_planes(crtc);
5c38d48c 3331 intel_crtc_update_cursor(crtc, true);
4f771f10 3332
42db64ef
PZ		 3333 hsw_enable_ips(intel_crtc);
3334
5bfe2ac0 3335 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3336 lpt_pch_enable(crtc);
4f771f10
PZ		 3337
3338 mutex_lock(&dev->struct_mutex);
3339 intel_update_fbc(dev);
3340 mutex_unlock(&dev->struct_mutex);
3341
4f771f10
PZ		 3342 for_each_encoder_on_crtc(dev, crtc, encoder)
3343 encoder->enable(encoder);
3344
4f771f10
PZ		 3345 /*
3346 * There seems to be a race in PCH platform hw (at least on some
3347 * outputs) where an enabled pipe still completes any pageflip right
3348 * away (as if the pipe is off) instead of waiting for vblank. As soon
3349 * as the first vblank happend, everything works as expected. Hence just
3350 * wait for one vblank before returning to avoid strange things
3351 * happening.
3352 */
3353 intel_wait_for_vblank(dev, intel_crtc->pipe);
3354}
3355
3f8dce3a
DV		 3356static void ironlake_pfit_disable(struct intel_crtc *crtc)
3357{
3358 struct drm_device *dev = crtc->base.dev;
3359 struct drm_i915_private *dev_priv = dev->dev_private;
3360 int pipe = crtc->pipe;
3361
3362 /* To avoid upsetting the power well on haswell only disable the pfit if
3363 * it's in use. The hw state code will make sure we get this right. */
3364 if (crtc->config.pch_pfit.size) {
3365 I915_WRITE(PF_CTL(pipe), 0);
3366 I915_WRITE(PF_WIN_POS(pipe), 0);
3367 I915_WRITE(PF_WIN_SZ(pipe), 0);
3368 }
3369}
3370
6be4a607
JB		 3371static void ironlake_crtc_disable(struct drm_crtc *crtc)
3372{
3373 struct drm_device *dev = crtc->dev;
3374 struct drm_i915_private *dev_priv = dev->dev_private;
3375 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3376 struct intel_encoder *encoder;
6be4a607
JB		 3377 int pipe = intel_crtc->pipe;
3378 int plane = intel_crtc->plane;
5eddb70b 3379 u32 reg, temp;
b52eb4dc 3380
ef9c3aee 3381
f7abfe8b
CW		 3382 if (!intel_crtc->active)
3383 return;
3384
ea9d758d
DV		 3385 for_each_encoder_on_crtc(dev, crtc, encoder)
3386 encoder->disable(encoder);
3387
e6c3a2a6 3388 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3389 drm_vblank_off(dev, pipe);
913d8d11 3390
973d04f9
CW		 3391 if (dev_priv->cfb_plane == plane)
3392 intel_disable_fbc(dev);
2c07245f 3393
0d5b8c61 3394 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3395 intel_disable_planes(crtc);
0d5b8c61
VS		 3396 intel_disable_plane(dev_priv, plane, pipe);
3397
d925c59a
DV		 3398 if (intel_crtc->config.has_pch_encoder)
3399 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3400
b24e7179 3401 intel_disable_pipe(dev_priv, pipe);
32f9d658 3402
3f8dce3a 3403 ironlake_pfit_disable(intel_crtc);
2c07245f 3404
bf49ec8c
DV		 3405 for_each_encoder_on_crtc(dev, crtc, encoder)
3406 if (encoder->post_disable)
3407 encoder->post_disable(encoder);
2c07245f 3408
d925c59a
DV		 3409 if (intel_crtc->config.has_pch_encoder) {
3410 ironlake_fdi_disable(crtc);
249c0e64 3411
d925c59a
DV		 3412 ironlake_disable_pch_transcoder(dev_priv, pipe);
3413 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
913d8d11 3414
d925c59a
DV		 3415 if (HAS_PCH_CPT(dev)) {
3416 /* disable TRANS_DP_CTL */
3417 reg = TRANS_DP_CTL(pipe);
3418 temp = I915_READ(reg);
3419 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3420 TRANS_DP_PORT_SEL_MASK);
3421 temp |= TRANS_DP_PORT_SEL_NONE;
3422 I915_WRITE(reg, temp);
3423
3424 /* disable DPLL_SEL */
3425 temp = I915_READ(PCH_DPLL_SEL);
11887397 3426 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 3427 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 3428 }
e3421a18 3429
d925c59a 3430 /* disable PCH DPLL */
e72f9fbf 3431 intel_disable_shared_dpll(intel_crtc);
8db9d77b 3432
d925c59a
DV		 3433 ironlake_fdi_pll_disable(intel_crtc);
3434 }
6b383a7f 3435
f7abfe8b 3436 intel_crtc->active = false;
6b383a7f 3437 intel_update_watermarks(dev);
d1ebd816
BW		 3438
3439 mutex_lock(&dev->struct_mutex);
6b383a7f 3440 intel_update_fbc(dev);
d1ebd816 3441 mutex_unlock(&dev->struct_mutex);
6be4a607 3442}
1b3c7a47 3443
4f771f10 3444static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3445{
4f771f10
PZ		 3446 struct drm_device *dev = crtc->dev;
3447 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3448 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3449 struct intel_encoder *encoder;
3450 int pipe = intel_crtc->pipe;
3451 int plane = intel_crtc->plane;
3b117c8f 3452 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3453
4f771f10
PZ		 3454 if (!intel_crtc->active)
3455 return;
3456
3457 for_each_encoder_on_crtc(dev, crtc, encoder)
3458 encoder->disable(encoder);
3459
3460 intel_crtc_wait_for_pending_flips(crtc);
3461 drm_vblank_off(dev, pipe);
4f771f10 3462
891348b2 3463 /* FBC must be disabled before disabling the plane on HSW. */
4f771f10
PZ		 3464 if (dev_priv->cfb_plane == plane)
3465 intel_disable_fbc(dev);
3466
42db64ef
PZ		 3467 hsw_disable_ips(intel_crtc);
3468
0d5b8c61 3469 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3470 intel_disable_planes(crtc);
891348b2
RV		 3471 intel_disable_plane(dev_priv, plane, pipe);
3472
8664281b
PZ		 3473 if (intel_crtc->config.has_pch_encoder)
3474 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3475 intel_disable_pipe(dev_priv, pipe);
3476
ad80a810 3477 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3478
3f8dce3a 3479 ironlake_pfit_disable(intel_crtc);
4f771f10 3480
1f544388 3481 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3482
3483 for_each_encoder_on_crtc(dev, crtc, encoder)
3484 if (encoder->post_disable)
3485 encoder->post_disable(encoder);
3486
88adfff1 3487 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3488 lpt_disable_pch_transcoder(dev_priv);
8664281b 3489 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3490 intel_ddi_fdi_disable(crtc);
83616634 3491 }
4f771f10
PZ		 3492
3493 intel_crtc->active = false;
3494 intel_update_watermarks(dev);
3495
3496 mutex_lock(&dev->struct_mutex);
3497 intel_update_fbc(dev);
3498 mutex_unlock(&dev->struct_mutex);
3499}
3500
ee7b9f93
JB		 3501static void ironlake_crtc_off(struct drm_crtc *crtc)
3502{
3503 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 3504 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 3505}
3506
6441ab5f
PZ		 3507static void haswell_crtc_off(struct drm_crtc *crtc)
3508{
3509 intel_ddi_put_crtc_pll(crtc);
3510}
3511
02e792fb
DV		 3512static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3513{
02e792fb 3514 if (!enable && intel_crtc->overlay) {
23f09ce3 3515 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3516 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3517
23f09ce3 3518 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3519 dev_priv->mm.interruptible = false;
3520 (void) intel_overlay_switch_off(intel_crtc->overlay);
3521 dev_priv->mm.interruptible = true;
23f09ce3 3522 mutex_unlock(&dev->struct_mutex);
02e792fb 3523 }
02e792fb 3524
5dcdbcb0
CW		 3525 /* Let userspace switch the overlay on again. In most cases userspace
3526 * has to recompute where to put it anyway.
3527 */
02e792fb
DV		 3528}
3529
61bc95c1
EE		 3530/**
3531 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3532 * cursor plane briefly if not already running after enabling the display
3533 * plane.
3534 * This workaround avoids occasional blank screens when self refresh is
3535 * enabled.
3536 */
3537static void
3538g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3539{
3540 u32 cntl = I915_READ(CURCNTR(pipe));
3541
3542 if ((cntl & CURSOR_MODE) == 0) {
3543 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3544
3545 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3546 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3547 intel_wait_for_vblank(dev_priv->dev, pipe);
3548 I915_WRITE(CURCNTR(pipe), cntl);
3549 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3550 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3551 }
3552}
3553
2dd24552
JB		 3554static void i9xx_pfit_enable(struct intel_crtc *crtc)
3555{
3556 struct drm_device *dev = crtc->base.dev;
3557 struct drm_i915_private *dev_priv = dev->dev_private;
3558 struct intel_crtc_config *pipe_config = &crtc->config;
3559
328d8e82 3560 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3561 return;
3562
2dd24552 3563 /*
c0b03411
DV		 3564 * The panel fitter should only be adjusted whilst the pipe is disabled,
3565 * according to register description and PRM.
2dd24552 3566 */
c0b03411
DV		 3567 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3568 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3569
b074cec8
JB		 3570 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3571 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3572
3573 /* Border color in case we don't scale up to the full screen. Black by
3574 * default, change to something else for debugging. */
3575 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3576}
3577
89b667f8
JB		 3578static void valleyview_crtc_enable(struct drm_crtc *crtc)
3579{
3580 struct drm_device *dev = crtc->dev;
3581 struct drm_i915_private *dev_priv = dev->dev_private;
3582 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3583 struct intel_encoder *encoder;
3584 int pipe = intel_crtc->pipe;
3585 int plane = intel_crtc->plane;
3586
3587 WARN_ON(!crtc->enabled);
3588
3589 if (intel_crtc->active)
3590 return;
3591
3592 intel_crtc->active = true;
3593 intel_update_watermarks(dev);
3594
3595 mutex_lock(&dev_priv->dpio_lock);
3596
3597 for_each_encoder_on_crtc(dev, crtc, encoder)
3598 if (encoder->pre_pll_enable)
3599 encoder->pre_pll_enable(encoder);
3600
3601 intel_enable_pll(dev_priv, pipe);
3602
3603 for_each_encoder_on_crtc(dev, crtc, encoder)
3604 if (encoder->pre_enable)
3605 encoder->pre_enable(encoder);
3606
3607 /* VLV wants encoder enabling _before_ the pipe is up. */
3608 for_each_encoder_on_crtc(dev, crtc, encoder)
3609 encoder->enable(encoder);
3610
2dd24552
JB		 3611 /* Enable panel fitting for eDP */
3612 i9xx_pfit_enable(intel_crtc);
3613
63cbb074
VS		 3614 intel_crtc_load_lut(crtc);
3615
89b667f8
JB		 3616 intel_enable_pipe(dev_priv, pipe, false);
3617 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3618 intel_enable_planes(crtc);
5c38d48c 3619 intel_crtc_update_cursor(crtc, true);
89b667f8 3620
f440eb13
VS		 3621 intel_update_fbc(dev);
3622
89b667f8
JB		 3623 mutex_unlock(&dev_priv->dpio_lock);
3624}
3625
0b8765c6 3626static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3627{
3628 struct drm_device *dev = crtc->dev;
79e53945
JB		 3629 struct drm_i915_private *dev_priv = dev->dev_private;
3630 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3631 struct intel_encoder *encoder;
79e53945 3632 int pipe = intel_crtc->pipe;
80824003 3633 int plane = intel_crtc->plane;
79e53945 3634
08a48469
DV		 3635 WARN_ON(!crtc->enabled);
3636
f7abfe8b
CW		 3637 if (intel_crtc->active)
3638 return;
3639
3640 intel_crtc->active = true;
6b383a7f
CW		 3641 intel_update_watermarks(dev);
3642
63d7bbe9 3643 intel_enable_pll(dev_priv, pipe);
9d6d9f19
MK		 3644
3645 for_each_encoder_on_crtc(dev, crtc, encoder)
3646 if (encoder->pre_enable)
3647 encoder->pre_enable(encoder);
3648
2dd24552
JB		 3649 /* Enable panel fitting for LVDS */
3650 i9xx_pfit_enable(intel_crtc);
3651
63cbb074
VS		 3652 intel_crtc_load_lut(crtc);
3653
040484af 3654 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3655 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3656 intel_enable_planes(crtc);
22e407d7 3657 /* The fixup needs to happen before cursor is enabled */
61bc95c1
EE		 3658 if (IS_G4X(dev))
3659 g4x_fixup_plane(dev_priv, pipe);
22e407d7 3660 intel_crtc_update_cursor(crtc, true);
79e53945 3661
0b8765c6
JB		 3662 /* Give the overlay scaler a chance to enable if it's on this pipe */
3663 intel_crtc_dpms_overlay(intel_crtc, true);
ef9c3aee 3664
f440eb13
VS		 3665 intel_update_fbc(dev);
3666
fa5c73b1
DV		 3667 for_each_encoder_on_crtc(dev, crtc, encoder)
3668 encoder->enable(encoder);
0b8765c6 3669}
79e53945 3670
87476d63
DV		 3671static void i9xx_pfit_disable(struct intel_crtc *crtc)
3672{
3673 struct drm_device *dev = crtc->base.dev;
3674 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3675
328d8e82
DV		 3676 if (!crtc->config.gmch_pfit.control)
3677 return;
87476d63 3678
328d8e82 3679 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3680
328d8e82
DV		 3681 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3682 I915_READ(PFIT_CONTROL));
3683 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3684}
3685
0b8765c6
JB		 3686static void i9xx_crtc_disable(struct drm_crtc *crtc)
3687{
3688 struct drm_device *dev = crtc->dev;
3689 struct drm_i915_private *dev_priv = dev->dev_private;
3690 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3691 struct intel_encoder *encoder;
0b8765c6
JB		 3692 int pipe = intel_crtc->pipe;
3693 int plane = intel_crtc->plane;
ef9c3aee 3694
f7abfe8b
CW		 3695 if (!intel_crtc->active)
3696 return;
3697
ea9d758d
DV		 3698 for_each_encoder_on_crtc(dev, crtc, encoder)
3699 encoder->disable(encoder);
3700
0b8765c6 3701 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3702 intel_crtc_wait_for_pending_flips(crtc);
3703 drm_vblank_off(dev, pipe);
0b8765c6 3704
973d04f9
CW		 3705 if (dev_priv->cfb_plane == plane)
3706 intel_disable_fbc(dev);
79e53945 3707
0d5b8c61
VS		 3708 intel_crtc_dpms_overlay(intel_crtc, false);
3709 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3710 intel_disable_planes(crtc);
b24e7179 3711 intel_disable_plane(dev_priv, plane, pipe);
0d5b8c61 3712
b24e7179 3713 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3714
87476d63 3715 i9xx_pfit_disable(intel_crtc);
24a1f16d 3716
89b667f8
JB		 3717 for_each_encoder_on_crtc(dev, crtc, encoder)
3718 if (encoder->post_disable)
3719 encoder->post_disable(encoder);
3720
63d7bbe9 3721 intel_disable_pll(dev_priv, pipe);
0b8765c6 3722
f7abfe8b 3723 intel_crtc->active = false;
6b383a7f
CW		 3724 intel_update_fbc(dev);
3725 intel_update_watermarks(dev);
0b8765c6
JB		 3726}
3727
ee7b9f93
JB		 3728static void i9xx_crtc_off(struct drm_crtc *crtc)
3729{
3730}
3731
976f8a20
DV		 3732static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3733 bool enabled)
2c07245f
ZW		 3734{
3735 struct drm_device *dev = crtc->dev;
3736 struct drm_i915_master_private *master_priv;
3737 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3738 int pipe = intel_crtc->pipe;
79e53945
JB		 3739
3740 if (!dev->primary->master)
3741 return;
3742
3743 master_priv = dev->primary->master->driver_priv;
3744 if (!master_priv->sarea_priv)
3745 return;
3746
79e53945
JB		 3747 switch (pipe) {
3748 case 0:
3749 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3750 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3751 break;
3752 case 1:
3753 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3754 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3755 break;
3756 default:
9db4a9c7 3757 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3758 break;
3759 }
79e53945
JB		 3760}
3761
976f8a20
DV		 3762/**
3763 * Sets the power management mode of the pipe and plane.
3764 */
3765void intel_crtc_update_dpms(struct drm_crtc *crtc)
3766{
3767 struct drm_device *dev = crtc->dev;
3768 struct drm_i915_private *dev_priv = dev->dev_private;
3769 struct intel_encoder *intel_encoder;
3770 bool enable = false;
3771
3772 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3773 enable |= intel_encoder->connectors_active;
3774
3775 if (enable)
3776 dev_priv->display.crtc_enable(crtc);
3777 else
3778 dev_priv->display.crtc_disable(crtc);
3779
3780 intel_crtc_update_sarea(crtc, enable);
3781}
3782
cdd59983
CW		 3783static void intel_crtc_disable(struct drm_crtc *crtc)
3784{
cdd59983 3785 struct drm_device *dev = crtc->dev;
976f8a20 3786 struct drm_connector *connector;
ee7b9f93 3787 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3788 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3789
976f8a20
DV		 3790 /* crtc should still be enabled when we disable it. */
3791 WARN_ON(!crtc->enabled);
3792
3793 dev_priv->display.crtc_disable(crtc);
c77bf565 3794 intel_crtc->eld_vld = false;
976f8a20 3795 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3796 dev_priv->display.off(crtc);
3797
931872fc
CW		 3798 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3799 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3800
3801 if (crtc->fb) {
3802 mutex_lock(&dev->struct_mutex);
1690e1eb 3803 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3804 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3805 crtc->fb = NULL;
3806 }
3807
3808 /* Update computed state. */
3809 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3810 if (!connector->encoder || !connector->encoder->crtc)
3811 continue;
3812
3813 if (connector->encoder->crtc != crtc)
3814 continue;
3815
3816 connector->dpms = DRM_MODE_DPMS_OFF;
3817 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3818 }
3819}
3820
a261b246 3821void intel_modeset_disable(struct drm_device *dev)
79e53945 3822{
a261b246
DV		 3823 struct drm_crtc *crtc;
3824
3825 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3826 if (crtc->enabled)
3827 intel_crtc_disable(crtc);
3828 }
79e53945
JB		 3829}
3830
ea5b213a 3831void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3832{
4ef69c7a 3833 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3834
ea5b213a
CW		 3835 drm_encoder_cleanup(encoder);
3836 kfree(intel_encoder);
7e7d76c3
JB		 3837}
3838
5ab432ef
DV		 3839/* Simple dpms helper for encodres with just one connector, no cloning and only
3840 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3841 * state of the entire output pipe. */
3842void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3843{
5ab432ef
DV		 3844 if (mode == DRM_MODE_DPMS_ON) {
3845 encoder->connectors_active = true;
3846
b2cabb0e 3847 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3848 } else {
3849 encoder->connectors_active = false;
3850
b2cabb0e 3851 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3852 }
79e53945
JB		 3853}
3854
0a91ca29
DV		 3855/* Cross check the actual hw state with our own modeset state tracking (and it's
3856 * internal consistency). */
b980514c 3857static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3858{
0a91ca29
DV		 3859 if (connector->get_hw_state(connector)) {
3860 struct intel_encoder *encoder = connector->encoder;
3861 struct drm_crtc *crtc;
3862 bool encoder_enabled;
3863 enum pipe pipe;
3864
3865 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3866 connector->base.base.id,
3867 drm_get_connector_name(&connector->base));
3868
3869 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3870 "wrong connector dpms state\n");
3871 WARN(connector->base.encoder != &encoder->base,
3872 "active connector not linked to encoder\n");
3873 WARN(!encoder->connectors_active,
3874 "encoder->connectors_active not set\n");
3875
3876 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3877 WARN(!encoder_enabled, "encoder not enabled\n");
3878 if (WARN_ON(!encoder->base.crtc))
3879 return;
3880
3881 crtc = encoder->base.crtc;
3882
3883 WARN(!crtc->enabled, "crtc not enabled\n");
3884 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3885 WARN(pipe != to_intel_crtc(crtc)->pipe,
3886 "encoder active on the wrong pipe\n");
3887 }
79e53945
JB		 3888}
3889
5ab432ef
DV		 3890/* Even simpler default implementation, if there's really no special case to
3891 * consider. */
3892void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3893{
5ab432ef 3894 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3895
5ab432ef
DV		 3896 /* All the simple cases only support two dpms states. */
3897 if (mode != DRM_MODE_DPMS_ON)
3898 mode = DRM_MODE_DPMS_OFF;
d4270e57 3899
5ab432ef
DV		 3900 if (mode == connector->dpms)
3901 return;
3902
3903 connector->dpms = mode;
3904
3905 /* Only need to change hw state when actually enabled */
3906 if (encoder->base.crtc)
3907 intel_encoder_dpms(encoder, mode);
3908 else
8af6cf88 3909 WARN_ON(encoder->connectors_active != false);
0a91ca29 3910
b980514c 3911 intel_modeset_check_state(connector->dev);
79e53945
JB		 3912}
3913
f0947c37
DV		 3914/* Simple connector->get_hw_state implementation for encoders that support only
3915 * one connector and no cloning and hence the encoder state determines the state
3916 * of the connector. */
3917bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3918{
24929352 3919 enum pipe pipe = 0;
f0947c37 3920 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3921
f0947c37 3922 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3923}
3924
1857e1da
DV		 3925static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3926 struct intel_crtc_config *pipe_config)
3927{
3928 struct drm_i915_private *dev_priv = dev->dev_private;
3929 struct intel_crtc *pipe_B_crtc =
3930 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3931
3932 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3933 pipe_name(pipe), pipe_config->fdi_lanes);
3934 if (pipe_config->fdi_lanes > 4) {
3935 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3936 pipe_name(pipe), pipe_config->fdi_lanes);
3937 return false;
3938 }
3939
3940 if (IS_HASWELL(dev)) {
3941 if (pipe_config->fdi_lanes > 2) {
3942 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3943 pipe_config->fdi_lanes);
3944 return false;
3945 } else {
3946 return true;
3947 }
3948 }
3949
3950 if (INTEL_INFO(dev)->num_pipes == 2)
3951 return true;
3952
3953 /* Ivybridge 3 pipe is really complicated */
3954 switch (pipe) {
3955 case PIPE_A:
3956 return true;
3957 case PIPE_B:
3958 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
3959 pipe_config->fdi_lanes > 2) {
3960 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3961 pipe_name(pipe), pipe_config->fdi_lanes);
3962 return false;
3963 }
3964 return true;
3965 case PIPE_C:
1e833f40 3966 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 3967 pipe_B_crtc->config.fdi_lanes <= 2) {
3968 if (pipe_config->fdi_lanes > 2) {
3969 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3970 pipe_name(pipe), pipe_config->fdi_lanes);
3971 return false;
3972 }
3973 } else {
3974 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
3975 return false;
3976 }
3977 return true;
3978 default:
3979 BUG();
3980 }
3981}
3982
e29c22c0
DV		 3983#define RETRY 1
3984static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
3985 struct intel_crtc_config *pipe_config)
877d48d5 3986{
1857e1da 3987 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 3988 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 3989 int lane, link_bw, fdi_dotclock;
e29c22c0 3990 bool setup_ok, needs_recompute = false;
877d48d5 3991
e29c22c0 3992retry:
877d48d5
DV		 3993 /* FDI is a binary signal running at ~2.7GHz, encoding
3994 * each output octet as 10 bits. The actual frequency
3995 * is stored as a divider into a 100MHz clock, and the
3996 * mode pixel clock is stored in units of 1KHz.
3997 * Hence the bw of each lane in terms of the mode signal
3998 * is:
3999 */
4000 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4001
ff9a6750 4002 fdi_dotclock = adjusted_mode->clock;
ef1b460d 4003 fdi_dotclock /= pipe_config->pixel_multiplier;
2bd89a07
DV		 4004
4005 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 4006 pipe_config->pipe_bpp);
4007
4008 pipe_config->fdi_lanes = lane;
4009
2bd89a07 4010 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4011 link_bw, &pipe_config->fdi_m_n);
1857e1da 4012
e29c22c0
DV		 4013 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4014 intel_crtc->pipe, pipe_config);
4015 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4016 pipe_config->pipe_bpp -= 2*3;
4017 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4018 pipe_config->pipe_bpp);
4019 needs_recompute = true;
4020 pipe_config->bw_constrained = true;
4021
4022 goto retry;
4023 }
4024
4025 if (needs_recompute)
4026 return RETRY;
4027
4028 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4029}
4030
42db64ef
PZ		 4031static void hsw_compute_ips_config(struct intel_crtc *crtc,
4032 struct intel_crtc_config *pipe_config)
4033{
3c4ca58c
PZ		 4034 pipe_config->ips_enabled = i915_enable_ips &&
4035 hsw_crtc_supports_ips(crtc) &&
42db64ef
PZ		 4036 pipe_config->pipe_bpp == 24;
4037}
4038
a43f6e0f 4039static int intel_crtc_compute_config(struct intel_crtc *crtc,
e29c22c0 4040 struct intel_crtc_config *pipe_config)
79e53945 4041{
a43f6e0f 4042 struct drm_device *dev = crtc->base.dev;
b8cecdf5 4043 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4044
bad720ff 4045 if (HAS_PCH_SPLIT(dev)) {
2c07245f 4046 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 4047 if (pipe_config->requested_mode.clock * 3
4048 > IRONLAKE_FDI_FREQ * 4)
e29c22c0 4049 return -EINVAL;
2c07245f 4050 }
89749350 4051
f9bef081
DV		 4052 /* All interlaced capable intel hw wants timings in frames. Note though
4053 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4054 * timings, so we need to be careful not to clobber these.*/
7ae89233 4055 if (!pipe_config->timings_set)
f9bef081 4056 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 4057
8693a824
DL		 4058 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4059 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4060 */
4061 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4062 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4063 return -EINVAL;
44f46b42 4064
bd080ee5 4065 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4066 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4067 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4068 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4069 * for lvds. */
4070 pipe_config->pipe_bpp = 8*3;
4071 }
4072
42db64ef 4073 if (IS_HASWELL(dev))
a43f6e0f
DV		 4074 hsw_compute_ips_config(crtc, pipe_config);
4075
4076 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4077 * clock survives for now. */
4078 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4079 pipe_config->shared_dpll = crtc->config.shared_dpll;
42db64ef 4080
877d48d5 4081 if (pipe_config->has_pch_encoder)
a43f6e0f 4082 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 4083
e29c22c0 4084 return 0;
79e53945
JB		 4085}
4086
25eb05fc
JB		 4087static int valleyview_get_display_clock_speed(struct drm_device *dev)
4088{
4089 return 400000; /* FIXME */
4090}
4091
e70236a8
JB		 4092static int i945_get_display_clock_speed(struct drm_device *dev)
4093{
4094 return 400000;
4095}
79e53945 4096
e70236a8 4097static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4098{
e70236a8
JB		 4099 return 333000;
4100}
79e53945 4101
e70236a8
JB		 4102static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4103{
4104 return 200000;
4105}
79e53945 4106
e70236a8
JB		 4107static int i915gm_get_display_clock_speed(struct drm_device *dev)
4108{
4109 u16 gcfgc = 0;
79e53945 4110
e70236a8
JB		 4111 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4112
4113 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4114 return 133000;
4115 else {
4116 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4117 case GC_DISPLAY_CLOCK_333_MHZ:
4118 return 333000;
4119 default:
4120 case GC_DISPLAY_CLOCK_190_200_MHZ:
4121 return 190000;
79e53945 4122 }
e70236a8
JB		 4123 }
4124}
4125
4126static int i865_get_display_clock_speed(struct drm_device *dev)
4127{
4128 return 266000;
4129}
4130
4131static int i855_get_display_clock_speed(struct drm_device *dev)
4132{
4133 u16 hpllcc = 0;
4134 /* Assume that the hardware is in the high speed state. This
4135 * should be the default.
4136 */
4137 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4138 case GC_CLOCK_133_200:
4139 case GC_CLOCK_100_200:
4140 return 200000;
4141 case GC_CLOCK_166_250:
4142 return 250000;
4143 case GC_CLOCK_100_133:
79e53945 4144 return 133000;
e70236a8 4145 }
79e53945 4146
e70236a8
JB		 4147 /* Shouldn't happen */
4148 return 0;
4149}
79e53945 4150
e70236a8
JB		 4151static int i830_get_display_clock_speed(struct drm_device *dev)
4152{
4153 return 133000;
79e53945
JB		 4154}
4155
2c07245f 4156static void
a65851af 4157intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4158{
a65851af
VS		 4159 while (*num > DATA_LINK_M_N_MASK ||
4160 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4161 *num >>= 1;
4162 *den >>= 1;
4163 }
4164}
4165
a65851af
VS		 4166static void compute_m_n(unsigned int m, unsigned int n,
4167 uint32_t *ret_m, uint32_t *ret_n)
4168{
4169 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4170 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4171 intel_reduce_m_n_ratio(ret_m, ret_n);
4172}
4173
e69d0bc1
DV		 4174void
4175intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4176 int pixel_clock, int link_clock,
4177 struct intel_link_m_n *m_n)
2c07245f 4178{
e69d0bc1 4179 m_n->tu = 64;
a65851af
VS		 4180
4181 compute_m_n(bits_per_pixel * pixel_clock,
4182 link_clock * nlanes * 8,
4183 &m_n->gmch_m, &m_n->gmch_n);
4184
4185 compute_m_n(pixel_clock, link_clock,
4186 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4187}
4188
a7615030
CW		 4189static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4190{
72bbe58c
KP		 4191 if (i915_panel_use_ssc >= 0)
4192 return i915_panel_use_ssc != 0;
41aa3448 4193 return dev_priv->vbt.lvds_use_ssc
435793df 4194 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4195}
4196
a0c4da24
JB		 4197static int vlv_get_refclk(struct drm_crtc *crtc)
4198{
4199 struct drm_device *dev = crtc->dev;
4200 struct drm_i915_private *dev_priv = dev->dev_private;
4201 int refclk = 27000; /* for DP & HDMI */
4202
4203 return 100000; /* only one validated so far */
4204
4205 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4206 refclk = 96000;
4207 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4208 if (intel_panel_use_ssc(dev_priv))
4209 refclk = 100000;
4210 else
4211 refclk = 96000;
4212 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4213 refclk = 100000;
4214 }
4215
4216 return refclk;
4217}
4218
c65d77d8
JB		 4219static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4220{
4221 struct drm_device *dev = crtc->dev;
4222 struct drm_i915_private *dev_priv = dev->dev_private;
4223 int refclk;
4224
a0c4da24
JB		 4225 if (IS_VALLEYVIEW(dev)) {
4226 refclk = vlv_get_refclk(crtc);
4227 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4228 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4229 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4230 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4231 refclk / 1000);
4232 } else if (!IS_GEN2(dev)) {
4233 refclk = 96000;
4234 } else {
4235 refclk = 48000;
4236 }
4237
4238 return refclk;
4239}
4240
7429e9d4
DV		 4241static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4242{
4243 return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2;
4244}
4245
4246static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4247{
4248 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4249}
4250
f47709a9 4251static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4252 intel_clock_t *reduced_clock)
4253{
f47709a9 4254 struct drm_device *dev = crtc->base.dev;
a7516a05 4255 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4256 int pipe = crtc->pipe;
a7516a05
JB		 4257 u32 fp, fp2 = 0;
4258
4259 if (IS_PINEVIEW(dev)) {
7429e9d4 4260 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4261 if (reduced_clock)
7429e9d4 4262 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4263 } else {
7429e9d4 4264 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4265 if (reduced_clock)
7429e9d4 4266 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4267 }
4268
4269 I915_WRITE(FP0(pipe), fp);
4270
f47709a9
DV		 4271 crtc->lowfreq_avail = false;
4272 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4273 reduced_clock && i915_powersave) {
4274 I915_WRITE(FP1(pipe), fp2);
f47709a9 4275 crtc->lowfreq_avail = true;
a7516a05
JB		 4276 } else {
4277 I915_WRITE(FP1(pipe), fp);
4278 }
4279}
4280
89b667f8
JB		 4281static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4282{
4283 u32 reg_val;
4284
4285 /*
4286 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4287 * and set it to a reasonable value instead.
4288 */
ae99258f 4289 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8
JB		 4290 reg_val &= 0xffffff00;
4291 reg_val |= 0x00000030;
ae99258f 4292 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4293
ae99258f 4294 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4295 reg_val &= 0x8cffffff;
4296 reg_val = 0x8c000000;
ae99258f 4297 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8 4298
ae99258f 4299 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8 4300 reg_val &= 0xffffff00;
ae99258f 4301 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4302
ae99258f 4303 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4304 reg_val &= 0x00ffffff;
4305 reg_val |= 0xb0000000;
ae99258f 4306 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4307}
4308
b551842d
DV		 4309static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4310 struct intel_link_m_n *m_n)
4311{
4312 struct drm_device *dev = crtc->base.dev;
4313 struct drm_i915_private *dev_priv = dev->dev_private;
4314 int pipe = crtc->pipe;
4315
e3b95f1e
DV		 4316 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4317 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4318 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4319 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4320}
4321
4322static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4323 struct intel_link_m_n *m_n)
4324{
4325 struct drm_device *dev = crtc->base.dev;
4326 struct drm_i915_private *dev_priv = dev->dev_private;
4327 int pipe = crtc->pipe;
4328 enum transcoder transcoder = crtc->config.cpu_transcoder;
4329
4330 if (INTEL_INFO(dev)->gen >= 5) {
4331 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4332 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4333 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4334 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4335 } else {
e3b95f1e
DV		 4336 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4337 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4338 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4339 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4340 }
4341}
4342
03afc4a2
DV		 4343static void intel_dp_set_m_n(struct intel_crtc *crtc)
4344{
4345 if (crtc->config.has_pch_encoder)
4346 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4347 else
4348 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4349}
4350
f47709a9 4351static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4352{
f47709a9 4353 struct drm_device *dev = crtc->base.dev;
a0c4da24 4354 struct drm_i915_private *dev_priv = dev->dev_private;
89b667f8 4355 struct intel_encoder *encoder;
f47709a9 4356 int pipe = crtc->pipe;
89b667f8 4357 u32 dpll, mdiv;
a0c4da24 4358 u32 bestn, bestm1, bestm2, bestp1, bestp2;
89b667f8 4359 bool is_hdmi;
198a037f 4360 u32 coreclk, reg_val, dpll_md;
a0c4da24 4361
09153000
DV		 4362 mutex_lock(&dev_priv->dpio_lock);
4363
89b667f8 4364 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
a0c4da24 4365
f47709a9
DV		 4366 bestn = crtc->config.dpll.n;
4367 bestm1 = crtc->config.dpll.m1;
4368 bestm2 = crtc->config.dpll.m2;
4369 bestp1 = crtc->config.dpll.p1;
4370 bestp2 = crtc->config.dpll.p2;
a0c4da24 4371
89b667f8
JB		 4372 /* See eDP HDMI DPIO driver vbios notes doc */
4373
4374 /* PLL B needs special handling */
4375 if (pipe)
4376 vlv_pllb_recal_opamp(dev_priv);
4377
4378 /* Set up Tx target for periodic Rcomp update */
ae99258f 4379 vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4380
4381 /* Disable target IRef on PLL */
ae99258f 4382 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
89b667f8 4383 reg_val &= 0x00ffffff;
ae99258f 4384 vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4385
4386 /* Disable fast lock */
ae99258f 4387 vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4388
4389 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4390 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4391 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4392 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4393 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4394
4395 /*
4396 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4397 * but we don't support that).
4398 * Note: don't use the DAC post divider as it seems unstable.
4399 */
4400 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ae99258f 4401 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4402
89b667f8 4403 mdiv |= DPIO_ENABLE_CALIBRATION;
ae99258f 4404 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4405
89b667f8 4406 /* Set HBR and RBR LPF coefficients */
ff9a6750 4407 if (crtc->config.port_clock == 162000 ||
89b667f8 4408 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
ae99258f 4409 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
89b667f8
JB		 4410 0x005f0021);
4411 else
ae99258f 4412 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
89b667f8
JB		 4413 0x00d0000f);
4414
4415 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4416 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4417 /* Use SSC source */
4418 if (!pipe)
ae99258f 4419 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4420 0x0df40000);
4421 else
ae99258f 4422 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4423 0x0df70000);
4424 } else { /* HDMI or VGA */
4425 /* Use bend source */
4426 if (!pipe)
ae99258f 4427 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4428 0x0df70000);
4429 else
ae99258f 4430 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4431 0x0df40000);
4432 }
a0c4da24 4433
ae99258f 4434 coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4435 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4436 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4437 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4438 coreclk |= 0x01000000;
ae99258f 4439 vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4440
ae99258f 4441 vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4442
89b667f8
JB		 4443 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4444 if (encoder->pre_pll_enable)
4445 encoder->pre_pll_enable(encoder);
2a8f64ca 4446
89b667f8
JB		 4447 /* Enable DPIO clock input */
4448 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4449 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4450 if (pipe)
4451 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
2a8f64ca 4452
89b667f8 4453 dpll |= DPLL_VCO_ENABLE;
2a8f64ca 4454 I915_WRITE(DPLL(pipe), dpll);
2a8f64ca
VP		 4455 POSTING_READ(DPLL(pipe));
4456 udelay(150);
a0c4da24 4457
89b667f8
JB		 4458 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4459 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4460
ef1b460d
DV		 4461 dpll_md = (crtc->config.pixel_multiplier - 1)
4462 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
198a037f
DV		 4463 I915_WRITE(DPLL_MD(pipe), dpll_md);
4464 POSTING_READ(DPLL_MD(pipe));
f47709a9 4465
89b667f8
JB		 4466 if (crtc->config.has_dp_encoder)
4467 intel_dp_set_m_n(crtc);
09153000
DV		 4468
4469 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4470}
4471
f47709a9
DV		 4472static void i9xx_update_pll(struct intel_crtc *crtc,
4473 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4474 int num_connectors)
4475{
f47709a9 4476 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4477 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4478 struct intel_encoder *encoder;
f47709a9 4479 int pipe = crtc->pipe;
eb1cbe48
DV		 4480 u32 dpll;
4481 bool is_sdvo;
f47709a9 4482 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4483
f47709a9 4484 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4485
f47709a9
DV		 4486 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4487 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4488
4489 dpll = DPLL_VGA_MODE_DIS;
4490
f47709a9 4491 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4492 dpll |= DPLLB_MODE_LVDS;
4493 else
4494 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4495
ef1b460d 4496 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
198a037f
DV		 4497 dpll |= (crtc->config.pixel_multiplier - 1)
4498 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4499 }
198a037f
DV		 4500
4501 if (is_sdvo)
4502 dpll |= DPLL_DVO_HIGH_SPEED;
4503
f47709a9 4504 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
eb1cbe48
DV		 4505 dpll |= DPLL_DVO_HIGH_SPEED;
4506
4507 /* compute bitmask from p1 value */
4508 if (IS_PINEVIEW(dev))
4509 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4510 else {
4511 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4512 if (IS_G4X(dev) && reduced_clock)
4513 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4514 }
4515 switch (clock->p2) {
4516 case 5:
4517 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4518 break;
4519 case 7:
4520 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4521 break;
4522 case 10:
4523 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4524 break;
4525 case 14:
4526 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4527 break;
4528 }
4529 if (INTEL_INFO(dev)->gen >= 4)
4530 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4531
09ede541 4532 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4533 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4534 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4535 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4536 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4537 else
4538 dpll |= PLL_REF_INPUT_DREFCLK;
4539
4540 dpll |= DPLL_VCO_ENABLE;
4541 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4542 POSTING_READ(DPLL(pipe));
4543 udelay(150);
4544
f47709a9 4545 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4546 if (encoder->pre_pll_enable)
4547 encoder->pre_pll_enable(encoder);
eb1cbe48 4548
f47709a9
DV		 4549 if (crtc->config.has_dp_encoder)
4550 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4551
4552 I915_WRITE(DPLL(pipe), dpll);
4553
4554 /* Wait for the clocks to stabilize. */
4555 POSTING_READ(DPLL(pipe));
4556 udelay(150);
4557
4558 if (INTEL_INFO(dev)->gen >= 4) {
ef1b460d
DV		 4559 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4560 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
198a037f 4561 I915_WRITE(DPLL_MD(pipe), dpll_md);
eb1cbe48
DV		 4562 } else {
4563 /* The pixel multiplier can only be updated once the
4564 * DPLL is enabled and the clocks are stable.
4565 *
4566 * So write it again.
4567 */
4568 I915_WRITE(DPLL(pipe), dpll);
4569 }
4570}
4571
f47709a9 4572static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 4573 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4574 int num_connectors)
4575{
f47709a9 4576 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4577 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4578 struct intel_encoder *encoder;
f47709a9 4579 int pipe = crtc->pipe;
eb1cbe48 4580 u32 dpll;
f47709a9 4581 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4582
f47709a9 4583 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4584
eb1cbe48
DV		 4585 dpll = DPLL_VGA_MODE_DIS;
4586
f47709a9 4587 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4588 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4589 } else {
4590 if (clock->p1 == 2)
4591 dpll |= PLL_P1_DIVIDE_BY_TWO;
4592 else
4593 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4594 if (clock->p2 == 4)
4595 dpll |= PLL_P2_DIVIDE_BY_4;
4596 }
4597
f47709a9 4598 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4599 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4600 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4601 else
4602 dpll |= PLL_REF_INPUT_DREFCLK;
4603
4604 dpll |= DPLL_VCO_ENABLE;
4605 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4606 POSTING_READ(DPLL(pipe));
4607 udelay(150);
4608
f47709a9 4609 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4610 if (encoder->pre_pll_enable)
4611 encoder->pre_pll_enable(encoder);
eb1cbe48 4612
5b5896e4
DV		 4613 I915_WRITE(DPLL(pipe), dpll);
4614
4615 /* Wait for the clocks to stabilize. */
4616 POSTING_READ(DPLL(pipe));
4617 udelay(150);
4618
eb1cbe48
DV		 4619 /* The pixel multiplier can only be updated once the
4620 * DPLL is enabled and the clocks are stable.
4621 *
4622 * So write it again.
4623 */
4624 I915_WRITE(DPLL(pipe), dpll);
4625}
4626
8a654f3b 4627static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 4628{
4629 struct drm_device *dev = intel_crtc->base.dev;
4630 struct drm_i915_private *dev_priv = dev->dev_private;
4631 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4632 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV		 4633 struct drm_display_mode *adjusted_mode =
4634 &intel_crtc->config.adjusted_mode;
4635 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4d8a62ea
DV		 4636 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4637
4638 /* We need to be careful not to changed the adjusted mode, for otherwise
4639 * the hw state checker will get angry at the mismatch. */
4640 crtc_vtotal = adjusted_mode->crtc_vtotal;
4641 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4642
4643 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4644 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4645 crtc_vtotal -= 1;
4646 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4647 vsyncshift = adjusted_mode->crtc_hsync_start
4648 - adjusted_mode->crtc_htotal / 2;
4649 } else {
4650 vsyncshift = 0;
4651 }
4652
4653 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4654 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4655
fe2b8f9d 4656 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4657 (adjusted_mode->crtc_hdisplay - 1) |
4658 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4659 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4660 (adjusted_mode->crtc_hblank_start - 1) |
4661 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4662 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4663 (adjusted_mode->crtc_hsync_start - 1) |
4664 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4665
fe2b8f9d 4666 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4667 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4668 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4669 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4670 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4671 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4672 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4673 (adjusted_mode->crtc_vsync_start - 1) |
4674 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4675
b5e508d4
PZ		 4676 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4677 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4678 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4679 * bits. */
4680 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4681 (pipe == PIPE_B || pipe == PIPE_C))
4682 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4683
b0e77b9c
PZ		 4684 /* pipesrc controls the size that is scaled from, which should
4685 * always be the user's requested size.
4686 */
4687 I915_WRITE(PIPESRC(pipe),
4688 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4689}
4690
1bd1bd80
DV		 4691static void intel_get_pipe_timings(struct intel_crtc *crtc,
4692 struct intel_crtc_config *pipe_config)
4693{
4694 struct drm_device *dev = crtc->base.dev;
4695 struct drm_i915_private *dev_priv = dev->dev_private;
4696 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4697 uint32_t tmp;
4698
4699 tmp = I915_READ(HTOTAL(cpu_transcoder));
4700 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4701 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4702 tmp = I915_READ(HBLANK(cpu_transcoder));
4703 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4704 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4705 tmp = I915_READ(HSYNC(cpu_transcoder));
4706 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4707 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4708
4709 tmp = I915_READ(VTOTAL(cpu_transcoder));
4710 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4711 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4712 tmp = I915_READ(VBLANK(cpu_transcoder));
4713 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4714 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4715 tmp = I915_READ(VSYNC(cpu_transcoder));
4716 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4717 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4718
4719 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4720 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4721 pipe_config->adjusted_mode.crtc_vtotal += 1;
4722 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4723 }
4724
4725 tmp = I915_READ(PIPESRC(crtc->pipe));
4726 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4727 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4728}
4729
84b046f3
DV		 4730static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4731{
4732 struct drm_device *dev = intel_crtc->base.dev;
4733 struct drm_i915_private *dev_priv = dev->dev_private;
4734 uint32_t pipeconf;
4735
4736 pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4737
4738 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4739 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4740 * core speed.
4741 *
4742 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4743 * pipe == 0 check?
4744 */
4745 if (intel_crtc->config.requested_mode.clock >
4746 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4747 pipeconf |= PIPECONF_DOUBLE_WIDE;
4748 else
4749 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4750 }
4751
ff9ce46e
DV		 4752 /* only g4x and later have fancy bpc/dither controls */
4753 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4754 pipeconf &= ~(PIPECONF_BPC_MASK |
4755 PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4756
4757 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4758 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4759 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4760 PIPECONF_DITHER_TYPE_SP;
84b046f3 4761
ff9ce46e
DV		 4762 switch (intel_crtc->config.pipe_bpp) {
4763 case 18:
4764 pipeconf |= PIPECONF_6BPC;
4765 break;
4766 case 24:
4767 pipeconf |= PIPECONF_8BPC;
4768 break;
4769 case 30:
4770 pipeconf |= PIPECONF_10BPC;
4771 break;
4772 default:
4773 /* Case prevented by intel_choose_pipe_bpp_dither. */
4774 BUG();
84b046f3
DV		 4775 }
4776 }
4777
4778 if (HAS_PIPE_CXSR(dev)) {
4779 if (intel_crtc->lowfreq_avail) {
4780 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4781 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4782 } else {
4783 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4784 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4785 }
4786 }
4787
4788 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4789 if (!IS_GEN2(dev) &&
4790 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4791 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4792 else
4793 pipeconf |= PIPECONF_PROGRESSIVE;
4794
9c8e09b7
VS		 4795 if (IS_VALLEYVIEW(dev)) {
4796 if (intel_crtc->config.limited_color_range)
4797 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4798 else
4799 pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4800 }
4801
84b046f3
DV		 4802 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4803 POSTING_READ(PIPECONF(intel_crtc->pipe));
4804}
4805
f564048e 4806static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4807 int x, int y,
94352cf9 4808 struct drm_framebuffer *fb)
79e53945
JB		 4809{
4810 struct drm_device *dev = crtc->dev;
4811 struct drm_i915_private *dev_priv = dev->dev_private;
4812 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 4813 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4814 int pipe = intel_crtc->pipe;
80824003 4815 int plane = intel_crtc->plane;
c751ce4f 4816 int refclk, num_connectors = 0;
652c393a 4817 intel_clock_t clock, reduced_clock;
84b046f3 4818 u32 dspcntr;
a16af721
DV		 4819 bool ok, has_reduced_clock = false;
4820 bool is_lvds = false;
5eddb70b 4821 struct intel_encoder *encoder;
d4906093 4822 const intel_limit_t *limit;
5c3b82e2 4823 int ret;
79e53945 4824
6c2b7c12 4825 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4826 switch (encoder->type) {
79e53945
JB		 4827 case INTEL_OUTPUT_LVDS:
4828 is_lvds = true;
4829 break;
79e53945 4830 }
43565a06 4831
c751ce4f 4832 num_connectors++;
79e53945
JB		 4833 }
4834
c65d77d8 4835 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4836
d4906093
ML		 4837 /*
4838 * Returns a set of divisors for the desired target clock with the given
4839 * refclk, or FALSE. The returned values represent the clock equation:
4840 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4841 */
1b894b59 4842 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 4843 ok = dev_priv->display.find_dpll(limit, crtc,
4844 intel_crtc->config.port_clock,
ee9300bb
DV		 4845 refclk, NULL, &clock);
4846 if (!ok && !intel_crtc->config.clock_set) {
79e53945 4847 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4848 return -EINVAL;
79e53945
JB		 4849 }
4850
cda4b7d3 4851 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4852 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4853
ddc9003c 4854 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4855 /*
4856 * Ensure we match the reduced clock's P to the target clock.
4857 * If the clocks don't match, we can't switch the display clock
4858 * by using the FP0/FP1. In such case we will disable the LVDS
4859 * downclock feature.
4860 */
ee9300bb
DV		 4861 has_reduced_clock =
4862 dev_priv->display.find_dpll(limit, crtc,
5eddb70b 4863 dev_priv->lvds_downclock,
ee9300bb 4864 refclk, &clock,
5eddb70b 4865 &reduced_clock);
7026d4ac 4866 }
f47709a9
DV		 4867 /* Compat-code for transition, will disappear. */
4868 if (!intel_crtc->config.clock_set) {
4869 intel_crtc->config.dpll.n = clock.n;
4870 intel_crtc->config.dpll.m1 = clock.m1;
4871 intel_crtc->config.dpll.m2 = clock.m2;
4872 intel_crtc->config.dpll.p1 = clock.p1;
4873 intel_crtc->config.dpll.p2 = clock.p2;
4874 }
7026d4ac 4875
eb1cbe48 4876 if (IS_GEN2(dev))
8a654f3b 4877 i8xx_update_pll(intel_crtc,
2a8f64ca
VP		 4878 has_reduced_clock ? &reduced_clock : NULL,
4879 num_connectors);
a0c4da24 4880 else if (IS_VALLEYVIEW(dev))
f47709a9 4881 vlv_update_pll(intel_crtc);
79e53945 4882 else
f47709a9 4883 i9xx_update_pll(intel_crtc,
eb1cbe48 4884 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4885 num_connectors);
79e53945 4886
79e53945
JB		 4887 /* Set up the display plane register */
4888 dspcntr = DISPPLANE_GAMMA_ENABLE;
4889
da6ecc5d
JB		 4890 if (!IS_VALLEYVIEW(dev)) {
4891 if (pipe == 0)
4892 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4893 else
4894 dspcntr |= DISPPLANE_SEL_PIPE_B;
4895 }
79e53945 4896
8a654f3b 4897 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW		 4898
4899 /* pipesrc and dspsize control the size that is scaled from,
4900 * which should always be the user's requested size.
79e53945 4901 */
929c77fb
EA		 4902 I915_WRITE(DSPSIZE(plane),
4903 ((mode->vdisplay - 1) << 16) |
4904 (mode->hdisplay - 1));
4905 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4906
84b046f3
DV		 4907 i9xx_set_pipeconf(intel_crtc);
4908
f564048e
EA		 4909 I915_WRITE(DSPCNTR(plane), dspcntr);
4910 POSTING_READ(DSPCNTR(plane));
4911
94352cf9 4912 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4913
4914 intel_update_watermarks(dev);
4915
f564048e
EA		 4916 return ret;
4917}
4918
2fa2fe9a
DV		 4919static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4920 struct intel_crtc_config *pipe_config)
4921{
4922 struct drm_device *dev = crtc->base.dev;
4923 struct drm_i915_private *dev_priv = dev->dev_private;
4924 uint32_t tmp;
4925
4926 tmp = I915_READ(PFIT_CONTROL);
4927
4928 if (INTEL_INFO(dev)->gen < 4) {
4929 if (crtc->pipe != PIPE_B)
4930 return;
4931
4932 /* gen2/3 store dither state in pfit control, needs to match */
4933 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
4934 } else {
4935 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4936 return;
4937 }
4938
4939 if (!(tmp & PFIT_ENABLE))
4940 return;
4941
4942 pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
4943 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4944 if (INTEL_INFO(dev)->gen < 5)
4945 pipe_config->gmch_pfit.lvds_border_bits =
4946 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4947}
4948
0e8ffe1b
DV		 4949static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4950 struct intel_crtc_config *pipe_config)
4951{
4952 struct drm_device *dev = crtc->base.dev;
4953 struct drm_i915_private *dev_priv = dev->dev_private;
4954 uint32_t tmp;
4955
eccb140b 4956 pipe_config->cpu_transcoder = crtc->pipe;
c0d43d62 4957 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 4958
0e8ffe1b
DV		 4959 tmp = I915_READ(PIPECONF(crtc->pipe));
4960 if (!(tmp & PIPECONF_ENABLE))
4961 return false;
4962
1bd1bd80
DV		 4963 intel_get_pipe_timings(crtc, pipe_config);
4964
2fa2fe9a
DV		 4965 i9xx_get_pfit_config(crtc, pipe_config);
4966
6c49f241
DV		 4967 if (INTEL_INFO(dev)->gen >= 4) {
4968 tmp = I915_READ(DPLL_MD(crtc->pipe));
4969 pipe_config->pixel_multiplier =
4970 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
4971 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
4972 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4973 tmp = I915_READ(DPLL(crtc->pipe));
4974 pipe_config->pixel_multiplier =
4975 ((tmp & SDVO_MULTIPLIER_MASK)
4976 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
4977 } else {
4978 /* Note that on i915G/GM the pixel multiplier is in the sdvo
4979 * port and will be fixed up in the encoder->get_config
4980 * function. */
4981 pipe_config->pixel_multiplier = 1;
4982 }
4983
0e8ffe1b
DV		 4984 return true;
4985}
4986
dde86e2d 4987static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4988{
4989 struct drm_i915_private *dev_priv = dev->dev_private;
4990 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4991 struct intel_encoder *encoder;
74cfd7ac 4992 u32 val, final;
13d83a67 4993 bool has_lvds = false;
199e5d79 4994 bool has_cpu_edp = false;
199e5d79 4995 bool has_panel = false;
99eb6a01
KP		 4996 bool has_ck505 = false;
4997 bool can_ssc = false;
13d83a67
JB		 4998
4999 /* We need to take the global config into account */
199e5d79
KP		 5000 list_for_each_entry(encoder, &mode_config->encoder_list,
5001 base.head) {
5002 switch (encoder->type) {
5003 case INTEL_OUTPUT_LVDS:
5004 has_panel = true;
5005 has_lvds = true;
5006 break;
5007 case INTEL_OUTPUT_EDP:
5008 has_panel = true;
2de6905f 5009 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5010 has_cpu_edp = true;
5011 break;
13d83a67
JB		 5012 }
5013 }
5014
99eb6a01 5015 if (HAS_PCH_IBX(dev)) {
41aa3448 5016 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5017 can_ssc = has_ck505;
5018 } else {
5019 has_ck505 = false;
5020 can_ssc = true;
5021 }
5022
2de6905f
ID		 5023 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5024 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5025
5026 /* Ironlake: try to setup display ref clock before DPLL
5027 * enabling. This is only under driver's control after
5028 * PCH B stepping, previous chipset stepping should be
5029 * ignoring this setting.
5030 */
74cfd7ac
CW		 5031 val = I915_READ(PCH_DREF_CONTROL);
5032
5033 /* As we must carefully and slowly disable/enable each source in turn,
5034 * compute the final state we want first and check if we need to
5035 * make any changes at all.
5036 */
5037 final = val;
5038 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5039 if (has_ck505)
5040 final |= DREF_NONSPREAD_CK505_ENABLE;
5041 else
5042 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5043
5044 final &= ~DREF_SSC_SOURCE_MASK;
5045 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5046 final &= ~DREF_SSC1_ENABLE;
5047
5048 if (has_panel) {
5049 final |= DREF_SSC_SOURCE_ENABLE;
5050
5051 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5052 final |= DREF_SSC1_ENABLE;
5053
5054 if (has_cpu_edp) {
5055 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5056 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5057 else
5058 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5059 } else
5060 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5061 } else {
5062 final |= DREF_SSC_SOURCE_DISABLE;
5063 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5064 }
5065
5066 if (final == val)
5067 return;
5068
13d83a67 5069 /* Always enable nonspread source */
74cfd7ac 5070 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5071
99eb6a01 5072 if (has_ck505)
74cfd7ac 5073 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5074 else
74cfd7ac 5075 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5076
199e5d79 5077 if (has_panel) {
74cfd7ac
CW		 5078 val &= ~DREF_SSC_SOURCE_MASK;
5079 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5080
199e5d79 5081 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5082 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5083 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5084 val |= DREF_SSC1_ENABLE;
e77166b5 5085 } else
74cfd7ac 5086 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5087
5088 /* Get SSC going before enabling the outputs */
74cfd7ac 5089 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5090 POSTING_READ(PCH_DREF_CONTROL);
5091 udelay(200);
5092
74cfd7ac 5093 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5094
5095 /* Enable CPU source on CPU attached eDP */
199e5d79 5096 if (has_cpu_edp) {
99eb6a01 5097 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5098 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5099 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5100 }
13d83a67 5101 else
74cfd7ac 5102 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5103 } else
74cfd7ac 5104 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5105
74cfd7ac 5106 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5107 POSTING_READ(PCH_DREF_CONTROL);
5108 udelay(200);
5109 } else {
5110 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5111
74cfd7ac 5112 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5113
5114 /* Turn off CPU output */
74cfd7ac 5115 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5116
74cfd7ac 5117 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5118 POSTING_READ(PCH_DREF_CONTROL);
5119 udelay(200);
5120
5121 /* Turn off the SSC source */
74cfd7ac
CW		 5122 val &= ~DREF_SSC_SOURCE_MASK;
5123 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5124
5125 /* Turn off SSC1 */
74cfd7ac 5126 val &= ~DREF_SSC1_ENABLE;
199e5d79 5127
74cfd7ac 5128 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5129 POSTING_READ(PCH_DREF_CONTROL);
5130 udelay(200);
5131 }
74cfd7ac
CW		 5132
5133 BUG_ON(val != final);
13d83a67
JB		 5134}
5135
dde86e2d
PZ		 5136/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5137static void lpt_init_pch_refclk(struct drm_device *dev)
5138{
5139 struct drm_i915_private *dev_priv = dev->dev_private;
5140 struct drm_mode_config *mode_config = &dev->mode_config;
5141 struct intel_encoder *encoder;
5142 bool has_vga = false;
5143 bool is_sdv = false;
5144 u32 tmp;
5145
5146 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5147 switch (encoder->type) {
5148 case INTEL_OUTPUT_ANALOG:
5149 has_vga = true;
5150 break;
5151 }
5152 }
5153
5154 if (!has_vga)
5155 return;
5156
c00db246
DV		 5157 mutex_lock(&dev_priv->dpio_lock);
5158
dde86e2d
PZ		 5159 /* XXX: Rip out SDV support once Haswell ships for real. */
5160 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5161 is_sdv = true;
5162
5163 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5164 tmp &= ~SBI_SSCCTL_DISABLE;
5165 tmp |= SBI_SSCCTL_PATHALT;
5166 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5167
5168 udelay(24);
5169
5170 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5171 tmp &= ~SBI_SSCCTL_PATHALT;
5172 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5173
5174 if (!is_sdv) {
5175 tmp = I915_READ(SOUTH_CHICKEN2);
5176 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5177 I915_WRITE(SOUTH_CHICKEN2, tmp);
5178
5179 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5180 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5181 DRM_ERROR("FDI mPHY reset assert timeout\n");
5182
5183 tmp = I915_READ(SOUTH_CHICKEN2);
5184 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5185 I915_WRITE(SOUTH_CHICKEN2, tmp);
5186
5187 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5188 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5189 100))
5190 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5191 }
5192
5193 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5194 tmp &= ~(0xFF << 24);
5195 tmp |= (0x12 << 24);
5196 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5197
dde86e2d
PZ		 5198 if (is_sdv) {
5199 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5200 tmp |= 0x7FFF;
5201 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5202 }
5203
5204 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5205 tmp |= (1 << 11);
5206 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5207
5208 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5209 tmp |= (1 << 11);
5210 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5211
5212 if (is_sdv) {
5213 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5214 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5215 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5216
5217 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5218 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5219 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5220
5221 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5222 tmp |= (0x3F << 8);
5223 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5224
5225 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5226 tmp |= (0x3F << 8);
5227 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5228 }
5229
5230 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5231 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5232 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5233
5234 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5235 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5236 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5237
5238 if (!is_sdv) {
5239 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5240 tmp &= ~(7 << 13);
5241 tmp |= (5 << 13);
5242 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5243
5244 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5245 tmp &= ~(7 << 13);
5246 tmp |= (5 << 13);
5247 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5248 }
5249
5250 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5251 tmp &= ~0xFF;
5252 tmp |= 0x1C;
5253 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5254
5255 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5256 tmp &= ~0xFF;
5257 tmp |= 0x1C;
5258 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5259
5260 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5261 tmp &= ~(0xFF << 16);
5262 tmp |= (0x1C << 16);
5263 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5264
5265 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5266 tmp &= ~(0xFF << 16);
5267 tmp |= (0x1C << 16);
5268 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5269
5270 if (!is_sdv) {
5271 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5272 tmp |= (1 << 27);
5273 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5274
5275 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5276 tmp |= (1 << 27);
5277 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5278
5279 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5280 tmp &= ~(0xF << 28);
5281 tmp |= (4 << 28);
5282 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5283
5284 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5285 tmp &= ~(0xF << 28);
5286 tmp |= (4 << 28);
5287 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5288 }
5289
5290 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5291 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5292 tmp |= SBI_DBUFF0_ENABLE;
5293 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5294
5295 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5296}
5297
5298/*
5299 * Initialize reference clocks when the driver loads
5300 */
5301void intel_init_pch_refclk(struct drm_device *dev)
5302{
5303 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5304 ironlake_init_pch_refclk(dev);
5305 else if (HAS_PCH_LPT(dev))
5306 lpt_init_pch_refclk(dev);
5307}
5308
d9d444cb
JB		 5309static int ironlake_get_refclk(struct drm_crtc *crtc)
5310{
5311 struct drm_device *dev = crtc->dev;
5312 struct drm_i915_private *dev_priv = dev->dev_private;
5313 struct intel_encoder *encoder;
d9d444cb
JB		 5314 int num_connectors = 0;
5315 bool is_lvds = false;
5316
6c2b7c12 5317 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5318 switch (encoder->type) {
5319 case INTEL_OUTPUT_LVDS:
5320 is_lvds = true;
5321 break;
d9d444cb
JB		 5322 }
5323 num_connectors++;
5324 }
5325
5326 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5327 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5328 dev_priv->vbt.lvds_ssc_freq);
5329 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5330 }
5331
5332 return 120000;
5333}
5334
6ff93609 5335static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5336{
c8203565 5337 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5338 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5339 int pipe = intel_crtc->pipe;
c8203565
PZ		 5340 uint32_t val;
5341
5342 val = I915_READ(PIPECONF(pipe));
5343
dfd07d72 5344 val &= ~PIPECONF_BPC_MASK;
965e0c48 5345 switch (intel_crtc->config.pipe_bpp) {
c8203565 5346 case 18:
dfd07d72 5347 val |= PIPECONF_6BPC;
c8203565
PZ		 5348 break;
5349 case 24:
dfd07d72 5350 val |= PIPECONF_8BPC;
c8203565
PZ		 5351 break;
5352 case 30:
dfd07d72 5353 val |= PIPECONF_10BPC;
c8203565
PZ		 5354 break;
5355 case 36:
dfd07d72 5356 val |= PIPECONF_12BPC;
c8203565
PZ		 5357 break;
5358 default:
cc769b62
PZ		 5359 /* Case prevented by intel_choose_pipe_bpp_dither. */
5360 BUG();
c8203565
PZ		 5361 }
5362
5363 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
d8b32247 5364 if (intel_crtc->config.dither)
c8203565
PZ		 5365 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5366
5367 val &= ~PIPECONF_INTERLACE_MASK;
6ff93609 5368 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5369 val |= PIPECONF_INTERLACED_ILK;
5370 else
5371 val |= PIPECONF_PROGRESSIVE;
5372
50f3b016 5373 if (intel_crtc->config.limited_color_range)
3685a8f3
VS		 5374 val |= PIPECONF_COLOR_RANGE_SELECT;
5375 else
5376 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5377
c8203565
PZ		 5378 I915_WRITE(PIPECONF(pipe), val);
5379 POSTING_READ(PIPECONF(pipe));
5380}
5381
86d3efce
VS		 5382/*
5383 * Set up the pipe CSC unit.
5384 *
5385 * Currently only full range RGB to limited range RGB conversion
5386 * is supported, but eventually this should handle various
5387 * RGB<->YCbCr scenarios as well.
5388 */
50f3b016 5389static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5390{
5391 struct drm_device *dev = crtc->dev;
5392 struct drm_i915_private *dev_priv = dev->dev_private;
5393 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5394 int pipe = intel_crtc->pipe;
5395 uint16_t coeff = 0x7800; /* 1.0 */
5396
5397 /*
5398 * TODO: Check what kind of values actually come out of the pipe
5399 * with these coeff/postoff values and adjust to get the best
5400 * accuracy. Perhaps we even need to take the bpc value into
5401 * consideration.
5402 */
5403
50f3b016 5404 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5405 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5406
5407 /*
5408 * GY/GU and RY/RU should be the other way around according
5409 * to BSpec, but reality doesn't agree. Just set them up in
5410 * a way that results in the correct picture.
5411 */
5412 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5413 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5414
5415 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5416 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5417
5418 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5419 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5420
5421 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5422 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5423 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5424
5425 if (INTEL_INFO(dev)->gen > 6) {
5426 uint16_t postoff = 0;
5427
50f3b016 5428 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5429 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5430
5431 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5432 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5433 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5434
5435 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5436 } else {
5437 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5438
50f3b016 5439 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5440 mode |= CSC_BLACK_SCREEN_OFFSET;
5441
5442 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5443 }
5444}
5445
6ff93609 5446static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5447{
5448 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5449 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5450 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5451 uint32_t val;
5452
702e7a56 5453 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5454
5455 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
d8b32247 5456 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5457 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5458
5459 val &= ~PIPECONF_INTERLACE_MASK_HSW;
6ff93609 5460 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5461 val |= PIPECONF_INTERLACED_ILK;
5462 else
5463 val |= PIPECONF_PROGRESSIVE;
5464
702e7a56
PZ		 5465 I915_WRITE(PIPECONF(cpu_transcoder), val);
5466 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5467}
5468
6591c6e4 5469static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ		 5470 intel_clock_t *clock,
5471 bool *has_reduced_clock,
5472 intel_clock_t *reduced_clock)
5473{
5474 struct drm_device *dev = crtc->dev;
5475 struct drm_i915_private *dev_priv = dev->dev_private;
5476 struct intel_encoder *intel_encoder;
5477 int refclk;
d4906093 5478 const intel_limit_t *limit;
a16af721 5479 bool ret, is_lvds = false;
79e53945 5480
6591c6e4
PZ		 5481 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5482 switch (intel_encoder->type) {
79e53945
JB		 5483 case INTEL_OUTPUT_LVDS:
5484 is_lvds = true;
5485 break;
79e53945
JB		 5486 }
5487 }
5488
d9d444cb 5489 refclk = ironlake_get_refclk(crtc);
79e53945 5490
d4906093
ML		 5491 /*
5492 * Returns a set of divisors for the desired target clock with the given
5493 * refclk, or FALSE. The returned values represent the clock equation:
5494 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5495 */
1b894b59 5496 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 5497 ret = dev_priv->display.find_dpll(limit, crtc,
5498 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 5499 refclk, NULL, clock);
6591c6e4
PZ		 5500 if (!ret)
5501 return false;
cda4b7d3 5502
ddc9003c 5503 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5504 /*
5505 * Ensure we match the reduced clock's P to the target clock.
5506 * If the clocks don't match, we can't switch the display clock
5507 * by using the FP0/FP1. In such case we will disable the LVDS
5508 * downclock feature.
5509 */
ee9300bb
DV		 5510 *has_reduced_clock =
5511 dev_priv->display.find_dpll(limit, crtc,
5512 dev_priv->lvds_downclock,
5513 refclk, clock,
5514 reduced_clock);
652c393a 5515 }
61e9653f 5516
6591c6e4
PZ		 5517 return true;
5518}
5519
01a415fd
DV		 5520static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5521{
5522 struct drm_i915_private *dev_priv = dev->dev_private;
5523 uint32_t temp;
5524
5525 temp = I915_READ(SOUTH_CHICKEN1);
5526 if (temp & FDI_BC_BIFURCATION_SELECT)
5527 return;
5528
5529 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5530 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5531
5532 temp |= FDI_BC_BIFURCATION_SELECT;
5533 DRM_DEBUG_KMS("enabling fdi C rx\n");
5534 I915_WRITE(SOUTH_CHICKEN1, temp);
5535 POSTING_READ(SOUTH_CHICKEN1);
5536}
5537
ebfd86fd
DV		 5538static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5539{
5540 struct drm_device *dev = intel_crtc->base.dev;
5541 struct drm_i915_private *dev_priv = dev->dev_private;
5542
5543 switch (intel_crtc->pipe) {
5544 case PIPE_A:
5545 break;
5546 case PIPE_B:
5547 if (intel_crtc->config.fdi_lanes > 2)
5548 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5549 else
5550 cpt_enable_fdi_bc_bifurcation(dev);
5551
5552 break;
5553 case PIPE_C:
01a415fd
DV		 5554 cpt_enable_fdi_bc_bifurcation(dev);
5555
ebfd86fd 5556 break;
01a415fd
DV		 5557 default:
5558 BUG();
5559 }
5560}
5561
d4b1931c
PZ		 5562int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5563{
5564 /*
5565 * Account for spread spectrum to avoid
5566 * oversubscribing the link. Max center spread
5567 * is 2.5%; use 5% for safety's sake.
5568 */
5569 u32 bps = target_clock * bpp * 21 / 20;
5570 return bps / (link_bw * 8) + 1;
5571}
5572
7429e9d4
DV		 5573static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5574{
5575 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5576}
5577
de13a2e3 5578static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5579 u32 *fp,
9a7c7890 5580 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5581{
de13a2e3 5582 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5583 struct drm_device *dev = crtc->dev;
5584 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5585 struct intel_encoder *intel_encoder;
5586 uint32_t dpll;
6cc5f341 5587 int factor, num_connectors = 0;
09ede541 5588 bool is_lvds = false, is_sdvo = false;
79e53945 5589
de13a2e3
PZ		 5590 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5591 switch (intel_encoder->type) {
79e53945
JB		 5592 case INTEL_OUTPUT_LVDS:
5593 is_lvds = true;
5594 break;
5595 case INTEL_OUTPUT_SDVO:
7d57382e 5596 case INTEL_OUTPUT_HDMI:
79e53945
JB		 5597 is_sdvo = true;
5598 break;
79e53945 5599 }
43565a06 5600
c751ce4f 5601 num_connectors++;
79e53945 5602 }
79e53945 5603
c1858123 5604 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5605 factor = 21;
5606 if (is_lvds) {
5607 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5608 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5609 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5610 factor = 25;
09ede541 5611 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5612 factor = 20;
c1858123 5613
7429e9d4 5614 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5615 *fp |= FP_CB_TUNE;
2c07245f 5616
9a7c7890
DV		 5617 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5618 *fp2 |= FP_CB_TUNE;
5619
5eddb70b 5620 dpll = 0;
2c07245f 5621
a07d6787
EA		 5622 if (is_lvds)
5623 dpll |= DPLLB_MODE_LVDS;
5624 else
5625 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 5626
ef1b460d
DV		 5627 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5628 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 5629
5630 if (is_sdvo)
5631 dpll |= DPLL_DVO_HIGH_SPEED;
9566e9af 5632 if (intel_crtc->config.has_dp_encoder)
a07d6787 5633 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5634
a07d6787 5635 /* compute bitmask from p1 value */
7429e9d4 5636 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5637 /* also FPA1 */
7429e9d4 5638 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5639
7429e9d4 5640 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5641 case 5:
5642 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5643 break;
5644 case 7:
5645 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5646 break;
5647 case 10:
5648 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5649 break;
5650 case 14:
5651 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5652 break;
79e53945
JB		 5653 }
5654
b4c09f3b 5655 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5656 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5657 else
5658 dpll |= PLL_REF_INPUT_DREFCLK;
5659
de13a2e3
PZ		 5660 return dpll;
5661}
5662
5663static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5664 int x, int y,
5665 struct drm_framebuffer *fb)
5666{
5667 struct drm_device *dev = crtc->dev;
5668 struct drm_i915_private *dev_priv = dev->dev_private;
5669 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5670 int pipe = intel_crtc->pipe;
5671 int plane = intel_crtc->plane;
5672 int num_connectors = 0;
5673 intel_clock_t clock, reduced_clock;
cbbab5bd 5674 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5675 bool ok, has_reduced_clock = false;
8b47047b 5676 bool is_lvds = false;
de13a2e3 5677 struct intel_encoder *encoder;
e2b78267 5678 struct intel_shared_dpll *pll;
de13a2e3 5679 int ret;
de13a2e3
PZ		 5680
5681 for_each_encoder_on_crtc(dev, crtc, encoder) {
5682 switch (encoder->type) {
5683 case INTEL_OUTPUT_LVDS:
5684 is_lvds = true;
5685 break;
de13a2e3
PZ		 5686 }
5687
5688 num_connectors++;
a07d6787 5689 }
79e53945 5690
5dc5298b
PZ		 5691 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5692 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5693
ff9a6750 5694 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 5695 &has_reduced_clock, &reduced_clock);
ee9300bb 5696 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 5697 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5698 return -EINVAL;
79e53945 5699 }
f47709a9
DV		 5700 /* Compat-code for transition, will disappear. */
5701 if (!intel_crtc->config.clock_set) {
5702 intel_crtc->config.dpll.n = clock.n;
5703 intel_crtc->config.dpll.m1 = clock.m1;
5704 intel_crtc->config.dpll.m2 = clock.m2;
5705 intel_crtc->config.dpll.p1 = clock.p1;
5706 intel_crtc->config.dpll.p2 = clock.p2;
5707 }
79e53945 5708
de13a2e3
PZ		 5709 /* Ensure that the cursor is valid for the new mode before changing... */
5710 intel_crtc_update_cursor(crtc, true);
5711
5dc5298b 5712 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5713 if (intel_crtc->config.has_pch_encoder) {
7429e9d4 5714 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5715 if (has_reduced_clock)
7429e9d4 5716 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5717
7429e9d4 5718 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5719 &fp, &reduced_clock,
5720 has_reduced_clock ? &fp2 : NULL);
5721
e72f9fbf 5722 pll = intel_get_shared_dpll(intel_crtc, dpll, fp);
ee7b9f93 5723 if (pll == NULL) {
84f44ce7
VS		 5724 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5725 pipe_name(pipe));
4b645f14
JB		 5726 return -EINVAL;
5727 }
ee7b9f93 5728 } else
e72f9fbf 5729 intel_put_shared_dpll(intel_crtc);
79e53945 5730
03afc4a2
DV		 5731 if (intel_crtc->config.has_dp_encoder)
5732 intel_dp_set_m_n(intel_crtc);
79e53945 5733
dafd226c
DV		 5734 for_each_encoder_on_crtc(dev, crtc, encoder)
5735 if (encoder->pre_pll_enable)
5736 encoder->pre_pll_enable(encoder);
79e53945 5737
e2b78267
DV		 5738 intel_crtc->lowfreq_avail = false;
5739
5740 if (intel_crtc->config.has_pch_encoder) {
5741 pll = intel_crtc_to_shared_dpll(intel_crtc);
5742
e9a632a5 5743 I915_WRITE(PCH_DPLL(pll->id), dpll);
5eddb70b 5744
32f9d658 5745 /* Wait for the clocks to stabilize. */
e9a632a5 5746 POSTING_READ(PCH_DPLL(pll->id));
32f9d658
ZW		 5747 udelay(150);
5748
8febb297
EA		 5749 /* The pixel multiplier can only be updated once the
5750 * DPLL is enabled and the clocks are stable.
5751 *
5752 * So write it again.
5753 */
e9a632a5 5754 I915_WRITE(PCH_DPLL(pll->id), dpll);
79e53945 5755
4b645f14 5756 if (is_lvds && has_reduced_clock && i915_powersave) {
e9a632a5 5757 I915_WRITE(PCH_FP1(pll->id), fp2);
4b645f14 5758 intel_crtc->lowfreq_avail = true;
4b645f14 5759 } else {
e9a632a5 5760 I915_WRITE(PCH_FP1(pll->id), fp);
652c393a
JB		 5761 }
5762 }
5763
8a654f3b 5764 intel_set_pipe_timings(intel_crtc);
5eddb70b 5765
ca3a0ff8 5766 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5767 intel_cpu_transcoder_set_m_n(intel_crtc,
5768 &intel_crtc->config.fdi_m_n);
5769 }
2c07245f 5770
ebfd86fd
DV		 5771 if (IS_IVYBRIDGE(dev))
5772 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
2c07245f 5773
6ff93609 5774 ironlake_set_pipeconf(crtc);
79e53945 5775
a1f9e77e
PZ		 5776 /* Set up the display plane register */
5777 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5778 POSTING_READ(DSPCNTR(plane));
79e53945 5779
94352cf9 5780 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5781
5782 intel_update_watermarks(dev);
5783
1857e1da 5784 return ret;
79e53945
JB		 5785}
5786
72419203
DV		 5787static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5788 struct intel_crtc_config *pipe_config)
5789{
5790 struct drm_device *dev = crtc->base.dev;
5791 struct drm_i915_private *dev_priv = dev->dev_private;
5792 enum transcoder transcoder = pipe_config->cpu_transcoder;
5793
5794 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5795 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5796 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5797 & ~TU_SIZE_MASK;
5798 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5799 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5800 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5801}
5802
2fa2fe9a
DV		 5803static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5804 struct intel_crtc_config *pipe_config)
5805{
5806 struct drm_device *dev = crtc->base.dev;
5807 struct drm_i915_private *dev_priv = dev->dev_private;
5808 uint32_t tmp;
5809
5810 tmp = I915_READ(PF_CTL(crtc->pipe));
5811
5812 if (tmp & PF_ENABLE) {
5813 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5814 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 5815
5816 /* We currently do not free assignements of panel fitters on
5817 * ivb/hsw (since we don't use the higher upscaling modes which
5818 * differentiates them) so just WARN about this case for now. */
5819 if (IS_GEN7(dev)) {
5820 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5821 PF_PIPE_SEL_IVB(crtc->pipe));
5822 }
2fa2fe9a
DV		 5823 }
5824}
5825
0e8ffe1b
DV		 5826static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5827 struct intel_crtc_config *pipe_config)
5828{
5829 struct drm_device *dev = crtc->base.dev;
5830 struct drm_i915_private *dev_priv = dev->dev_private;
5831 uint32_t tmp;
5832
eccb140b 5833 pipe_config->cpu_transcoder = crtc->pipe;
c0d43d62 5834 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5835
0e8ffe1b
DV		 5836 tmp = I915_READ(PIPECONF(crtc->pipe));
5837 if (!(tmp & PIPECONF_ENABLE))
5838 return false;
5839
ab9412ba 5840 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
88adfff1
DV		 5841 pipe_config->has_pch_encoder = true;
5842
627eb5a3
DV		 5843 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5844 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5845 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5846
5847 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241
DV		 5848
5849 /* XXX: Can't properly read out the pch dpll pixel multiplier
5850 * since we don't have state tracking for pch clocks yet. */
5851 pipe_config->pixel_multiplier = 1;
c0d43d62
DV		 5852
5853 if (HAS_PCH_IBX(dev_priv->dev)) {
5854 pipe_config->shared_dpll = crtc->pipe;
5855 } else {
5856 tmp = I915_READ(PCH_DPLL_SEL);
5857 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5858 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5859 else
5860 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5861 }
6c49f241
DV		 5862 } else {
5863 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 5864 }
5865
1bd1bd80
DV		 5866 intel_get_pipe_timings(crtc, pipe_config);
5867
2fa2fe9a
DV		 5868 ironlake_get_pfit_config(crtc, pipe_config);
5869
0e8ffe1b
DV		 5870 return true;
5871}
5872
d6dd9eb1
DV		 5873static void haswell_modeset_global_resources(struct drm_device *dev)
5874{
d6dd9eb1
DV		 5875 bool enable = false;
5876 struct intel_crtc *crtc;
d6dd9eb1
DV		 5877
5878 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 5879 if (!crtc->base.enabled)
5880 continue;
d6dd9eb1 5881
e7a639c4
DV		 5882 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5883 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 5884 enable = true;
5885 }
5886
d6dd9eb1
DV		 5887 intel_set_power_well(dev, enable);
5888}
5889
09b4ddf9 5890static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 5891 int x, int y,
5892 struct drm_framebuffer *fb)
5893{
5894 struct drm_device *dev = crtc->dev;
5895 struct drm_i915_private *dev_priv = dev->dev_private;
5896 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 5897 int plane = intel_crtc->plane;
09b4ddf9 5898 int ret;
09b4ddf9 5899
ff9a6750 5900 if (!intel_ddi_pll_mode_set(crtc))
6441ab5f
PZ		 5901 return -EINVAL;
5902
09b4ddf9
PZ		 5903 /* Ensure that the cursor is valid for the new mode before changing... */
5904 intel_crtc_update_cursor(crtc, true);
5905
03afc4a2
DV		 5906 if (intel_crtc->config.has_dp_encoder)
5907 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 5908
5909 intel_crtc->lowfreq_avail = false;
09b4ddf9 5910
8a654f3b 5911 intel_set_pipe_timings(intel_crtc);
09b4ddf9 5912
ca3a0ff8 5913 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5914 intel_cpu_transcoder_set_m_n(intel_crtc,
5915 &intel_crtc->config.fdi_m_n);
5916 }
09b4ddf9 5917
6ff93609 5918 haswell_set_pipeconf(crtc);
09b4ddf9 5919
50f3b016 5920 intel_set_pipe_csc(crtc);
86d3efce 5921
09b4ddf9 5922 /* Set up the display plane register */
86d3efce 5923 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5924 POSTING_READ(DSPCNTR(plane));
5925
5926 ret = intel_pipe_set_base(crtc, x, y, fb);
5927
5928 intel_update_watermarks(dev);
5929
1f803ee5 5930 return ret;
79e53945
JB		 5931}
5932
0e8ffe1b
DV		 5933static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5934 struct intel_crtc_config *pipe_config)
5935{
5936 struct drm_device *dev = crtc->base.dev;
5937 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 5938 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 5939 uint32_t tmp;
5940
eccb140b 5941 pipe_config->cpu_transcoder = crtc->pipe;
c0d43d62
DV		 5942 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5943
eccb140b
DV		 5944 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
5945 if (tmp & TRANS_DDI_FUNC_ENABLE) {
5946 enum pipe trans_edp_pipe;
5947 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
5948 default:
5949 WARN(1, "unknown pipe linked to edp transcoder\n");
5950 case TRANS_DDI_EDP_INPUT_A_ONOFF:
5951 case TRANS_DDI_EDP_INPUT_A_ON:
5952 trans_edp_pipe = PIPE_A;
5953 break;
5954 case TRANS_DDI_EDP_INPUT_B_ONOFF:
5955 trans_edp_pipe = PIPE_B;
5956 break;
5957 case TRANS_DDI_EDP_INPUT_C_ONOFF:
5958 trans_edp_pipe = PIPE_C;
5959 break;
5960 }
5961
5962 if (trans_edp_pipe == crtc->pipe)
5963 pipe_config->cpu_transcoder = TRANSCODER_EDP;
5964 }
5965
b97186f0 5966 if (!intel_display_power_enabled(dev,
eccb140b 5967 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 5968 return false;
5969
eccb140b 5970 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 5971 if (!(tmp & PIPECONF_ENABLE))
5972 return false;
5973
88adfff1 5974 /*
f196e6be 5975 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 5976 * DDI E. So just check whether this pipe is wired to DDI E and whether
5977 * the PCH transcoder is on.
5978 */
eccb140b 5979 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 5980 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 5981 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 5982 pipe_config->has_pch_encoder = true;
5983
627eb5a3
DV		 5984 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
5985 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5986 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5987
5988 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 5989 }
5990
1bd1bd80
DV		 5991 intel_get_pipe_timings(crtc, pipe_config);
5992
2fa2fe9a
DV		 5993 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
5994 if (intel_display_power_enabled(dev, pfit_domain))
5995 ironlake_get_pfit_config(crtc, pipe_config);
5996
42db64ef
PZ		 5997 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
5998 (I915_READ(IPS_CTL) & IPS_ENABLE);
5999
6c49f241
DV		 6000 pipe_config->pixel_multiplier = 1;
6001
0e8ffe1b
DV		 6002 return true;
6003}
6004
f564048e 6005static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6006 int x, int y,
94352cf9 6007 struct drm_framebuffer *fb)
f564048e
EA		 6008{
6009 struct drm_device *dev = crtc->dev;
6010 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 6011 struct drm_encoder_helper_funcs *encoder_funcs;
6012 struct intel_encoder *encoder;
0b701d27 6013 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 6014 struct drm_display_mode *adjusted_mode =
6015 &intel_crtc->config.adjusted_mode;
6016 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6017 int pipe = intel_crtc->pipe;
f564048e
EA		 6018 int ret;
6019
0b701d27 6020 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6021
b8cecdf5
DV		 6022 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6023
79e53945 6024 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6025
9256aa19
DV		 6026 if (ret != 0)
6027 return ret;
6028
6029 for_each_encoder_on_crtc(dev, crtc, encoder) {
6030 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6031 encoder->base.base.id,
6032 drm_get_encoder_name(&encoder->base),
6033 mode->base.id, mode->name);
6cc5f341
DV		 6034 if (encoder->mode_set) {
6035 encoder->mode_set(encoder);
6036 } else {
6037 encoder_funcs = encoder->base.helper_private;
6038 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6039 }
9256aa19
DV		 6040 }
6041
6042 return 0;
79e53945
JB		 6043}
6044
3a9627f4
WF		 6045static bool intel_eld_uptodate(struct drm_connector *connector,
6046 int reg_eldv, uint32_t bits_eldv,
6047 int reg_elda, uint32_t bits_elda,
6048 int reg_edid)
6049{
6050 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6051 uint8_t *eld = connector->eld;
6052 uint32_t i;
6053
6054 i = I915_READ(reg_eldv);
6055 i &= bits_eldv;
6056
6057 if (!eld[0])
6058 return !i;
6059
6060 if (!i)
6061 return false;
6062
6063 i = I915_READ(reg_elda);
6064 i &= ~bits_elda;
6065 I915_WRITE(reg_elda, i);
6066
6067 for (i = 0; i < eld[2]; i++)
6068 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6069 return false;
6070
6071 return true;
6072}
6073
e0dac65e
WF		 6074static void g4x_write_eld(struct drm_connector *connector,
6075 struct drm_crtc *crtc)
6076{
6077 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6078 uint8_t *eld = connector->eld;
6079 uint32_t eldv;
6080 uint32_t len;
6081 uint32_t i;
6082
6083 i = I915_READ(G4X_AUD_VID_DID);
6084
6085 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6086 eldv = G4X_ELDV_DEVCL_DEVBLC;
6087 else
6088 eldv = G4X_ELDV_DEVCTG;
6089
3a9627f4
WF		 6090 if (intel_eld_uptodate(connector,
6091 G4X_AUD_CNTL_ST, eldv,
6092 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6093 G4X_HDMIW_HDMIEDID))
6094 return;
6095
e0dac65e
WF		 6096 i = I915_READ(G4X_AUD_CNTL_ST);
6097 i &= ~(eldv | G4X_ELD_ADDR);
6098 len = (i >> 9) & 0x1f; /* ELD buffer size */
6099 I915_WRITE(G4X_AUD_CNTL_ST, i);
6100
6101 if (!eld[0])
6102 return;
6103
6104 len = min_t(uint8_t, eld[2], len);
6105 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6106 for (i = 0; i < len; i++)
6107 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6108
6109 i = I915_READ(G4X_AUD_CNTL_ST);
6110 i |= eldv;
6111 I915_WRITE(G4X_AUD_CNTL_ST, i);
6112}
6113
83358c85
WX		 6114static void haswell_write_eld(struct drm_connector *connector,
6115 struct drm_crtc *crtc)
6116{
6117 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6118 uint8_t *eld = connector->eld;
6119 struct drm_device *dev = crtc->dev;
7b9f35a6 6120 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6121 uint32_t eldv;
6122 uint32_t i;
6123 int len;
6124 int pipe = to_intel_crtc(crtc)->pipe;
6125 int tmp;
6126
6127 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6128 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6129 int aud_config = HSW_AUD_CFG(pipe);
6130 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6131
6132
6133 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6134
6135 /* Audio output enable */
6136 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6137 tmp = I915_READ(aud_cntrl_st2);
6138 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6139 I915_WRITE(aud_cntrl_st2, tmp);
6140
6141 /* Wait for 1 vertical blank */
6142 intel_wait_for_vblank(dev, pipe);
6143
6144 /* Set ELD valid state */
6145 tmp = I915_READ(aud_cntrl_st2);
6146 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6147 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6148 I915_WRITE(aud_cntrl_st2, tmp);
6149 tmp = I915_READ(aud_cntrl_st2);
6150 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6151
6152 /* Enable HDMI mode */
6153 tmp = I915_READ(aud_config);
6154 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6155 /* clear N_programing_enable and N_value_index */
6156 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6157 I915_WRITE(aud_config, tmp);
6158
6159 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6160
6161 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6162 intel_crtc->eld_vld = true;
83358c85
WX		 6163
6164 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6165 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6166 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6167 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6168 } else
6169 I915_WRITE(aud_config, 0);
6170
6171 if (intel_eld_uptodate(connector,
6172 aud_cntrl_st2, eldv,
6173 aud_cntl_st, IBX_ELD_ADDRESS,
6174 hdmiw_hdmiedid))
6175 return;
6176
6177 i = I915_READ(aud_cntrl_st2);
6178 i &= ~eldv;
6179 I915_WRITE(aud_cntrl_st2, i);
6180
6181 if (!eld[0])
6182 return;
6183
6184 i = I915_READ(aud_cntl_st);
6185 i &= ~IBX_ELD_ADDRESS;
6186 I915_WRITE(aud_cntl_st, i);
6187 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6188 DRM_DEBUG_DRIVER("port num:%d\n", i);
6189
6190 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6191 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6192 for (i = 0; i < len; i++)
6193 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6194
6195 i = I915_READ(aud_cntrl_st2);
6196 i |= eldv;
6197 I915_WRITE(aud_cntrl_st2, i);
6198
6199}
6200
e0dac65e
WF		 6201static void ironlake_write_eld(struct drm_connector *connector,
6202 struct drm_crtc *crtc)
6203{
6204 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6205 uint8_t *eld = connector->eld;
6206 uint32_t eldv;
6207 uint32_t i;
6208 int len;
6209 int hdmiw_hdmiedid;
b6daa025 6210 int aud_config;
e0dac65e
WF		 6211 int aud_cntl_st;
6212 int aud_cntrl_st2;
9b138a83 6213 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6214
b3f33cbf 6215 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6216 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6217 aud_config = IBX_AUD_CFG(pipe);
6218 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6219 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6220 } else {
9b138a83
WX		 6221 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6222 aud_config = CPT_AUD_CFG(pipe);
6223 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6224 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6225 }
6226
9b138a83 6227 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6228
6229 i = I915_READ(aud_cntl_st);
9b138a83 6230 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6231 if (!i) {
6232 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6233 /* operate blindly on all ports */
1202b4c6
WF		 6234 eldv = IBX_ELD_VALIDB;
6235 eldv |= IBX_ELD_VALIDB << 4;
6236 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6237 } else {
2582a850 6238 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6239 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6240 }
6241
3a9627f4
WF		 6242 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6243 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6244 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6245 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6246 } else
6247 I915_WRITE(aud_config, 0);
e0dac65e 6248
3a9627f4
WF		 6249 if (intel_eld_uptodate(connector,
6250 aud_cntrl_st2, eldv,
6251 aud_cntl_st, IBX_ELD_ADDRESS,
6252 hdmiw_hdmiedid))
6253 return;
6254
e0dac65e
WF		 6255 i = I915_READ(aud_cntrl_st2);
6256 i &= ~eldv;
6257 I915_WRITE(aud_cntrl_st2, i);
6258
6259 if (!eld[0])
6260 return;
6261
e0dac65e 6262 i = I915_READ(aud_cntl_st);
1202b4c6 6263 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6264 I915_WRITE(aud_cntl_st, i);
6265
6266 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6267 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6268 for (i = 0; i < len; i++)
6269 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6270
6271 i = I915_READ(aud_cntrl_st2);
6272 i |= eldv;
6273 I915_WRITE(aud_cntrl_st2, i);
6274}
6275
6276void intel_write_eld(struct drm_encoder *encoder,
6277 struct drm_display_mode *mode)
6278{
6279 struct drm_crtc *crtc = encoder->crtc;
6280 struct drm_connector *connector;
6281 struct drm_device *dev = encoder->dev;
6282 struct drm_i915_private *dev_priv = dev->dev_private;
6283
6284 connector = drm_select_eld(encoder, mode);
6285 if (!connector)
6286 return;
6287
6288 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6289 connector->base.id,
6290 drm_get_connector_name(connector),
6291 connector->encoder->base.id,
6292 drm_get_encoder_name(connector->encoder));
6293
6294 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6295
6296 if (dev_priv->display.write_eld)
6297 dev_priv->display.write_eld(connector, crtc);
6298}
6299
79e53945
JB		 6300/** Loads the palette/gamma unit for the CRTC with the prepared values */
6301void intel_crtc_load_lut(struct drm_crtc *crtc)
6302{
6303 struct drm_device *dev = crtc->dev;
6304 struct drm_i915_private *dev_priv = dev->dev_private;
6305 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
42db64ef
PZ		 6306 enum pipe pipe = intel_crtc->pipe;
6307 int palreg = PALETTE(pipe);
79e53945 6308 int i;
42db64ef 6309 bool reenable_ips = false;
79e53945
JB		 6310
6311 /* The clocks have to be on to load the palette. */
aed3f09d 6312 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6313 return;
6314
14420bd0
VS		 6315 if (!HAS_PCH_SPLIT(dev_priv->dev))
6316 assert_pll_enabled(dev_priv, pipe);
6317
f2b115e6 6318 /* use legacy palette for Ironlake */
bad720ff 6319 if (HAS_PCH_SPLIT(dev))
42db64ef
PZ		 6320 palreg = LGC_PALETTE(pipe);
6321
6322 /* Workaround : Do not read or write the pipe palette/gamma data while
6323 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6324 */
6325 if (intel_crtc->config.ips_enabled &&
6326 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6327 GAMMA_MODE_MODE_SPLIT)) {
6328 hsw_disable_ips(intel_crtc);
6329 reenable_ips = true;
6330 }
2c07245f 6331
79e53945
JB		 6332 for (i = 0; i < 256; i++) {
6333 I915_WRITE(palreg + 4 * i,
6334 (intel_crtc->lut_r[i] << 16) |
6335 (intel_crtc->lut_g[i] << 8) |
6336 intel_crtc->lut_b[i]);
6337 }
42db64ef
PZ		 6338
6339 if (reenable_ips)
6340 hsw_enable_ips(intel_crtc);
79e53945
JB		 6341}
6342
560b85bb
CW		 6343static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6344{
6345 struct drm_device *dev = crtc->dev;
6346 struct drm_i915_private *dev_priv = dev->dev_private;
6347 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6348 bool visible = base != 0;
6349 u32 cntl;
6350
6351 if (intel_crtc->cursor_visible == visible)
6352 return;
6353
9db4a9c7 6354 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6355 if (visible) {
6356 /* On these chipsets we can only modify the base whilst
6357 * the cursor is disabled.
6358 */
9db4a9c7 6359 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6360
6361 cntl &= ~(CURSOR_FORMAT_MASK);
6362 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6363 cntl |= CURSOR_ENABLE |
6364 CURSOR_GAMMA_ENABLE |
6365 CURSOR_FORMAT_ARGB;
6366 } else
6367 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6368 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6369
6370 intel_crtc->cursor_visible = visible;
6371}
6372
6373static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6374{
6375 struct drm_device *dev = crtc->dev;
6376 struct drm_i915_private *dev_priv = dev->dev_private;
6377 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6378 int pipe = intel_crtc->pipe;
6379 bool visible = base != 0;
6380
6381 if (intel_crtc->cursor_visible != visible) {
548f245b 6382 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6383 if (base) {
6384 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6385 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6386 cntl |= pipe << 28; /* Connect to correct pipe */
6387 } else {
6388 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6389 cntl |= CURSOR_MODE_DISABLE;
6390 }
9db4a9c7 6391 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6392
6393 intel_crtc->cursor_visible = visible;
6394 }
6395 /* and commit changes on next vblank */
9db4a9c7 6396 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6397}
6398
65a21cd6
JB		 6399static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6400{
6401 struct drm_device *dev = crtc->dev;
6402 struct drm_i915_private *dev_priv = dev->dev_private;
6403 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6404 int pipe = intel_crtc->pipe;
6405 bool visible = base != 0;
6406
6407 if (intel_crtc->cursor_visible != visible) {
6408 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6409 if (base) {
6410 cntl &= ~CURSOR_MODE;
6411 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6412 } else {
6413 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6414 cntl |= CURSOR_MODE_DISABLE;
6415 }
86d3efce
VS		 6416 if (IS_HASWELL(dev))
6417 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6418 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6419
6420 intel_crtc->cursor_visible = visible;
6421 }
6422 /* and commit changes on next vblank */
6423 I915_WRITE(CURBASE_IVB(pipe), base);
6424}
6425
cda4b7d3 6426/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6427static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6428 bool on)
cda4b7d3
CW		 6429{
6430 struct drm_device *dev = crtc->dev;
6431 struct drm_i915_private *dev_priv = dev->dev_private;
6432 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6433 int pipe = intel_crtc->pipe;
6434 int x = intel_crtc->cursor_x;
6435 int y = intel_crtc->cursor_y;
560b85bb 6436 u32 base, pos;
cda4b7d3
CW		 6437 bool visible;
6438
6439 pos = 0;
6440
6b383a7f 6441 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6442 base = intel_crtc->cursor_addr;
6443 if (x > (int) crtc->fb->width)
6444 base = 0;
6445
6446 if (y > (int) crtc->fb->height)
6447 base = 0;
6448 } else
6449 base = 0;
6450
6451 if (x < 0) {
6452 if (x + intel_crtc->cursor_width < 0)
6453 base = 0;
6454
6455 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6456 x = -x;
6457 }
6458 pos |= x << CURSOR_X_SHIFT;
6459
6460 if (y < 0) {
6461 if (y + intel_crtc->cursor_height < 0)
6462 base = 0;
6463
6464 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6465 y = -y;
6466 }
6467 pos |= y << CURSOR_Y_SHIFT;
6468
6469 visible = base != 0;
560b85bb 6470 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6471 return;
6472
0cd83aa9 6473 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6474 I915_WRITE(CURPOS_IVB(pipe), pos);
6475 ivb_update_cursor(crtc, base);
6476 } else {
6477 I915_WRITE(CURPOS(pipe), pos);
6478 if (IS_845G(dev) || IS_I865G(dev))
6479 i845_update_cursor(crtc, base);
6480 else
6481 i9xx_update_cursor(crtc, base);
6482 }
cda4b7d3
CW		 6483}
6484
79e53945 6485static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6486 struct drm_file *file,
79e53945
JB		 6487 uint32_t handle,
6488 uint32_t width, uint32_t height)
6489{
6490 struct drm_device *dev = crtc->dev;
6491 struct drm_i915_private *dev_priv = dev->dev_private;
6492 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6493 struct drm_i915_gem_object *obj;
cda4b7d3 6494 uint32_t addr;
3f8bc370 6495 int ret;
79e53945 6496
79e53945
JB		 6497 /* if we want to turn off the cursor ignore width and height */
6498 if (!handle) {
28c97730 6499 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6500 addr = 0;
05394f39 6501 obj = NULL;
5004417d 6502 mutex_lock(&dev->struct_mutex);
3f8bc370 6503 goto finish;
79e53945
JB		 6504 }
6505
6506 /* Currently we only support 64x64 cursors */
6507 if (width != 64 || height != 64) {
6508 DRM_ERROR("we currently only support 64x64 cursors\n");
6509 return -EINVAL;
6510 }
6511
05394f39 6512 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6513 if (&obj->base == NULL)
79e53945
JB		 6514 return -ENOENT;
6515
05394f39 6516 if (obj->base.size < width * height * 4) {
79e53945 6517 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6518 ret = -ENOMEM;
6519 goto fail;
79e53945
JB		 6520 }
6521
71acb5eb 6522 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6523 mutex_lock(&dev->struct_mutex);
b295d1b6 6524 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6525 unsigned alignment;
6526
d9e86c0e
CW		 6527 if (obj->tiling_mode) {
6528 DRM_ERROR("cursor cannot be tiled\n");
6529 ret = -EINVAL;
6530 goto fail_locked;
6531 }
6532
693db184
CW		 6533 /* Note that the w/a also requires 2 PTE of padding following
6534 * the bo. We currently fill all unused PTE with the shadow
6535 * page and so we should always have valid PTE following the
6536 * cursor preventing the VT-d warning.
6537 */
6538 alignment = 0;
6539 if (need_vtd_wa(dev))
6540 alignment = 64*1024;
6541
6542 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6543 if (ret) {
6544 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6545 goto fail_locked;
e7b526bb
CW		 6546 }
6547
d9e86c0e
CW		 6548 ret = i915_gem_object_put_fence(obj);
6549 if (ret) {
2da3b9b9 6550 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6551 goto fail_unpin;
6552 }
6553
05394f39 6554 addr = obj->gtt_offset;
71acb5eb 6555 } else {
6eeefaf3 6556 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6557 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6558 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6559 align);
71acb5eb
DA		 6560 if (ret) {
6561 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6562 goto fail_locked;
71acb5eb 6563 }
05394f39 6564 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6565 }
6566
a6c45cf0 6567 if (IS_GEN2(dev))
14b60391
JB		 6568 I915_WRITE(CURSIZE, (height << 12) | width);
6569
3f8bc370 6570 finish:
3f8bc370 6571 if (intel_crtc->cursor_bo) {
b295d1b6 6572 if (dev_priv->info->cursor_needs_physical) {
05394f39 6573 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6574 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6575 } else
6576 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6577 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6578 }
80824003 6579
7f9872e0 6580 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6581
6582 intel_crtc->cursor_addr = addr;
05394f39 6583 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6584 intel_crtc->cursor_width = width;
6585 intel_crtc->cursor_height = height;
6586
40ccc72b 6587 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 6588
79e53945 6589 return 0;
e7b526bb 6590fail_unpin:
05394f39 6591 i915_gem_object_unpin(obj);
7f9872e0 6592fail_locked:
34b8686e 6593 mutex_unlock(&dev->struct_mutex);
bc9025bd 6594fail:
05394f39 6595 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6596 return ret;
79e53945
JB		 6597}
6598
6599static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6600{
79e53945 6601 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6602
cda4b7d3
CW		 6603 intel_crtc->cursor_x = x;
6604 intel_crtc->cursor_y = y;
652c393a 6605
40ccc72b 6606 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 6607
6608 return 0;
6609}
6610
6611/** Sets the color ramps on behalf of RandR */
6612void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6613 u16 blue, int regno)
6614{
6615 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6616
6617 intel_crtc->lut_r[regno] = red >> 8;
6618 intel_crtc->lut_g[regno] = green >> 8;
6619 intel_crtc->lut_b[regno] = blue >> 8;
6620}
6621
b8c00ac5
DA		 6622void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6623 u16 *blue, int regno)
6624{
6625 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6626
6627 *red = intel_crtc->lut_r[regno] << 8;
6628 *green = intel_crtc->lut_g[regno] << 8;
6629 *blue = intel_crtc->lut_b[regno] << 8;
6630}
6631
79e53945 6632static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6633 u16 *blue, uint32_t start, uint32_t size)
79e53945 6634{
7203425a 6635 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6636 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6637
7203425a 6638 for (i = start; i < end; i++) {
79e53945
JB		 6639 intel_crtc->lut_r[i] = red[i] >> 8;
6640 intel_crtc->lut_g[i] = green[i] >> 8;
6641 intel_crtc->lut_b[i] = blue[i] >> 8;
6642 }
6643
6644 intel_crtc_load_lut(crtc);
6645}
6646
79e53945
JB		 6647/* VESA 640x480x72Hz mode to set on the pipe */
6648static struct drm_display_mode load_detect_mode = {
6649 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6650 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6651};
6652
d2dff872
CW		 6653static struct drm_framebuffer *
6654intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6655 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6656 struct drm_i915_gem_object *obj)
6657{
6658 struct intel_framebuffer *intel_fb;
6659 int ret;
6660
6661 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6662 if (!intel_fb) {
6663 drm_gem_object_unreference_unlocked(&obj->base);
6664 return ERR_PTR(-ENOMEM);
6665 }
6666
6667 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6668 if (ret) {
6669 drm_gem_object_unreference_unlocked(&obj->base);
6670 kfree(intel_fb);
6671 return ERR_PTR(ret);
6672 }
6673
6674 return &intel_fb->base;
6675}
6676
6677static u32
6678intel_framebuffer_pitch_for_width(int width, int bpp)
6679{
6680 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6681 return ALIGN(pitch, 64);
6682}
6683
6684static u32
6685intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6686{
6687 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6688 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6689}
6690
6691static struct drm_framebuffer *
6692intel_framebuffer_create_for_mode(struct drm_device *dev,
6693 struct drm_display_mode *mode,
6694 int depth, int bpp)
6695{
6696 struct drm_i915_gem_object *obj;
0fed39bd 6697 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6698
6699 obj = i915_gem_alloc_object(dev,
6700 intel_framebuffer_size_for_mode(mode, bpp));
6701 if (obj == NULL)
6702 return ERR_PTR(-ENOMEM);
6703
6704 mode_cmd.width = mode->hdisplay;
6705 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6706 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6707 bpp);
5ca0c34a 6708 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6709
6710 return intel_framebuffer_create(dev, &mode_cmd, obj);
6711}
6712
6713static struct drm_framebuffer *
6714mode_fits_in_fbdev(struct drm_device *dev,
6715 struct drm_display_mode *mode)
6716{
6717 struct drm_i915_private *dev_priv = dev->dev_private;
6718 struct drm_i915_gem_object *obj;
6719 struct drm_framebuffer *fb;
6720
6721 if (dev_priv->fbdev == NULL)
6722 return NULL;
6723
6724 obj = dev_priv->fbdev->ifb.obj;
6725 if (obj == NULL)
6726 return NULL;
6727
6728 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6729 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6730 fb->bits_per_pixel))
d2dff872
CW		 6731 return NULL;
6732
01f2c773 6733 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6734 return NULL;
6735
6736 return fb;
6737}
6738
d2434ab7 6739bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6740 struct drm_display_mode *mode,
8261b191 6741 struct intel_load_detect_pipe *old)
79e53945
JB		 6742{
6743 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6744 struct intel_encoder *intel_encoder =
6745 intel_attached_encoder(connector);
79e53945 6746 struct drm_crtc *possible_crtc;
4ef69c7a 6747 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6748 struct drm_crtc *crtc = NULL;
6749 struct drm_device *dev = encoder->dev;
94352cf9 6750 struct drm_framebuffer *fb;
79e53945
JB		 6751 int i = -1;
6752
d2dff872
CW		 6753 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6754 connector->base.id, drm_get_connector_name(connector),
6755 encoder->base.id, drm_get_encoder_name(encoder));
6756
79e53945
JB		 6757 /*
6758 * Algorithm gets a little messy:
7a5e4805 6759 *
79e53945
JB		 6760 * - if the connector already has an assigned crtc, use it (but make
6761 * sure it's on first)
7a5e4805 6762 *
79e53945
JB		 6763 * - try to find the first unused crtc that can drive this connector,
6764 * and use that if we find one
79e53945
JB		 6765 */
6766
6767 /* See if we already have a CRTC for this connector */
6768 if (encoder->crtc) {
6769 crtc = encoder->crtc;
8261b191 6770
7b24056b
DV		 6771 mutex_lock(&crtc->mutex);
6772
24218aac 6773 old->dpms_mode = connector->dpms;
8261b191
CW		 6774 old->load_detect_temp = false;
6775
6776 /* Make sure the crtc and connector are running */
24218aac
DV		 6777 if (connector->dpms != DRM_MODE_DPMS_ON)
6778 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6779
7173188d 6780 return true;
79e53945
JB		 6781 }
6782
6783 /* Find an unused one (if possible) */
6784 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6785 i++;
6786 if (!(encoder->possible_crtcs & (1 << i)))
6787 continue;
6788 if (!possible_crtc->enabled) {
6789 crtc = possible_crtc;
6790 break;
6791 }
79e53945
JB		 6792 }
6793
6794 /*
6795 * If we didn't find an unused CRTC, don't use any.
6796 */
6797 if (!crtc) {
7173188d
CW		 6798 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6799 return false;
79e53945
JB		 6800 }
6801
7b24056b 6802 mutex_lock(&crtc->mutex);
fc303101
DV		 6803 intel_encoder->new_crtc = to_intel_crtc(crtc);
6804 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6805
6806 intel_crtc = to_intel_crtc(crtc);
24218aac 6807 old->dpms_mode = connector->dpms;
8261b191 6808 old->load_detect_temp = true;
d2dff872 6809 old->release_fb = NULL;
79e53945 6810
6492711d
CW		 6811 if (!mode)
6812 mode = &load_detect_mode;
79e53945 6813
d2dff872
CW		 6814 /* We need a framebuffer large enough to accommodate all accesses
6815 * that the plane may generate whilst we perform load detection.
6816 * We can not rely on the fbcon either being present (we get called
6817 * during its initialisation to detect all boot displays, or it may
6818 * not even exist) or that it is large enough to satisfy the
6819 * requested mode.
6820 */
94352cf9
DV		 6821 fb = mode_fits_in_fbdev(dev, mode);
6822 if (fb == NULL) {
d2dff872 6823 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6824 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6825 old->release_fb = fb;
d2dff872
CW		 6826 } else
6827 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6828 if (IS_ERR(fb)) {
d2dff872 6829 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6830 mutex_unlock(&crtc->mutex);
0e8b3d3e 6831 return false;
79e53945 6832 }
79e53945 6833
c0c36b94 6834 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6835 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6836 if (old->release_fb)
6837 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6838 mutex_unlock(&crtc->mutex);
0e8b3d3e 6839 return false;
79e53945 6840 }
7173188d 6841
79e53945 6842 /* let the connector get through one full cycle before testing */
9d0498a2 6843 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6844 return true;
79e53945
JB		 6845}
6846
d2434ab7 6847void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6848 struct intel_load_detect_pipe *old)
79e53945 6849{
d2434ab7
DV		 6850 struct intel_encoder *intel_encoder =
6851 intel_attached_encoder(connector);
4ef69c7a 6852 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6853 struct drm_crtc *crtc = encoder->crtc;
79e53945 6854
d2dff872
CW		 6855 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6856 connector->base.id, drm_get_connector_name(connector),
6857 encoder->base.id, drm_get_encoder_name(encoder));
6858
8261b191 6859 if (old->load_detect_temp) {
fc303101
DV		 6860 to_intel_connector(connector)->new_encoder = NULL;
6861 intel_encoder->new_crtc = NULL;
6862 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6863
36206361
DV		 6864 if (old->release_fb) {
6865 drm_framebuffer_unregister_private(old->release_fb);
6866 drm_framebuffer_unreference(old->release_fb);
6867 }
d2dff872 6868
67c96400 6869 mutex_unlock(&crtc->mutex);
0622a53c 6870 return;
79e53945
JB		 6871 }
6872
c751ce4f 6873 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6874 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6875 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6876
6877 mutex_unlock(&crtc->mutex);
79e53945
JB		 6878}
6879
6880/* Returns the clock of the currently programmed mode of the given pipe. */
6881static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6882{
6883 struct drm_i915_private *dev_priv = dev->dev_private;
6884 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6885 int pipe = intel_crtc->pipe;
548f245b 6886 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6887 u32 fp;
6888 intel_clock_t clock;
6889
6890 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6891 fp = I915_READ(FP0(pipe));
79e53945 6892 else
39adb7a5 6893 fp = I915_READ(FP1(pipe));
79e53945
JB		 6894
6895 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6896 if (IS_PINEVIEW(dev)) {
6897 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6898 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6899 } else {
6900 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6901 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6902 }
6903
a6c45cf0 6904 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6905 if (IS_PINEVIEW(dev))
6906 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6907 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6908 else
6909 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6910 DPLL_FPA01_P1_POST_DIV_SHIFT);
6911
6912 switch (dpll & DPLL_MODE_MASK) {
6913 case DPLLB_MODE_DAC_SERIAL:
6914 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6915 5 : 10;
6916 break;
6917 case DPLLB_MODE_LVDS:
6918 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6919 7 : 14;
6920 break;
6921 default:
28c97730 6922 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6923 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6924 return 0;
6925 }
6926
ac58c3f0
DV		 6927 if (IS_PINEVIEW(dev))
6928 pineview_clock(96000, &clock);
6929 else
6930 i9xx_clock(96000, &clock);
79e53945
JB		 6931 } else {
6932 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6933
6934 if (is_lvds) {
6935 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6936 DPLL_FPA01_P1_POST_DIV_SHIFT);
6937 clock.p2 = 14;
6938
6939 if ((dpll & PLL_REF_INPUT_MASK) ==
6940 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6941 /* XXX: might not be 66MHz */
ac58c3f0 6942 i9xx_clock(66000, &clock);
79e53945 6943 } else
ac58c3f0 6944 i9xx_clock(48000, &clock);
79e53945
JB		 6945 } else {
6946 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6947 clock.p1 = 2;
6948 else {
6949 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6950 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6951 }
6952 if (dpll & PLL_P2_DIVIDE_BY_4)
6953 clock.p2 = 4;
6954 else
6955 clock.p2 = 2;
6956
ac58c3f0 6957 i9xx_clock(48000, &clock);
79e53945
JB		 6958 }
6959 }
6960
6961 /* XXX: It would be nice to validate the clocks, but we can't reuse
6962 * i830PllIsValid() because it relies on the xf86_config connector
6963 * configuration being accurate, which it isn't necessarily.
6964 */
6965
6966 return clock.dot;
6967}
6968
6969/** Returns the currently programmed mode of the given pipe. */
6970struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6971 struct drm_crtc *crtc)
6972{
548f245b 6973 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6974 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 6975 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 6976 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6977 int htot = I915_READ(HTOTAL(cpu_transcoder));
6978 int hsync = I915_READ(HSYNC(cpu_transcoder));
6979 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6980 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6981
6982 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6983 if (!mode)
6984 return NULL;
6985
6986 mode->clock = intel_crtc_clock_get(dev, crtc);
6987 mode->hdisplay = (htot & 0xffff) + 1;
6988 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6989 mode->hsync_start = (hsync & 0xffff) + 1;
6990 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6991 mode->vdisplay = (vtot & 0xffff) + 1;
6992 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6993 mode->vsync_start = (vsync & 0xffff) + 1;
6994 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6995
6996 drm_mode_set_name(mode);
79e53945
JB		 6997
6998 return mode;
6999}
7000
3dec0095 7001static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7002{
7003 struct drm_device *dev = crtc->dev;
7004 drm_i915_private_t *dev_priv = dev->dev_private;
7005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7006 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7007 int dpll_reg = DPLL(pipe);
7008 int dpll;
652c393a 7009
bad720ff 7010 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7011 return;
7012
7013 if (!dev_priv->lvds_downclock_avail)
7014 return;
7015
dbdc6479 7016 dpll = I915_READ(dpll_reg);
652c393a 7017 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7018 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7019
8ac5a6d5 7020 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7021
7022 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7023 I915_WRITE(dpll_reg, dpll);
9d0498a2 7024 intel_wait_for_vblank(dev, pipe);
dbdc6479 7025
652c393a
JB		 7026 dpll = I915_READ(dpll_reg);
7027 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7028 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7029 }
652c393a
JB		 7030}
7031
7032static void intel_decrease_pllclock(struct drm_crtc *crtc)
7033{
7034 struct drm_device *dev = crtc->dev;
7035 drm_i915_private_t *dev_priv = dev->dev_private;
7036 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7037
bad720ff 7038 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7039 return;
7040
7041 if (!dev_priv->lvds_downclock_avail)
7042 return;
7043
7044 /*
7045 * Since this is called by a timer, we should never get here in
7046 * the manual case.
7047 */
7048 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7049 int pipe = intel_crtc->pipe;
7050 int dpll_reg = DPLL(pipe);
7051 int dpll;
f6e5b160 7052
44d98a61 7053 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7054
8ac5a6d5 7055 assert_panel_unlocked(dev_priv, pipe);
652c393a 7056
dc257cf1 7057 dpll = I915_READ(dpll_reg);
652c393a
JB		 7058 dpll |= DISPLAY_RATE_SELECT_FPA1;
7059 I915_WRITE(dpll_reg, dpll);
9d0498a2 7060 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7061 dpll = I915_READ(dpll_reg);
7062 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7063 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7064 }
7065
7066}
7067
f047e395
CW		 7068void intel_mark_busy(struct drm_device *dev)
7069{
f047e395
CW		 7070 i915_update_gfx_val(dev->dev_private);
7071}
7072
7073void intel_mark_idle(struct drm_device *dev)
652c393a 7074{
652c393a 7075 struct drm_crtc *crtc;
652c393a
JB		 7076
7077 if (!i915_powersave)
7078 return;
7079
652c393a 7080 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7081 if (!crtc->fb)
7082 continue;
7083
725a5b54 7084 intel_decrease_pllclock(crtc);
652c393a 7085 }
652c393a
JB		 7086}
7087
c65355bb
CW		 7088void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7089 struct intel_ring_buffer *ring)
652c393a 7090{
f047e395
CW		 7091 struct drm_device *dev = obj->base.dev;
7092 struct drm_crtc *crtc;
652c393a 7093
f047e395 7094 if (!i915_powersave)
acb87dfb
CW		 7095 return;
7096
652c393a
JB		 7097 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7098 if (!crtc->fb)
7099 continue;
7100
c65355bb
CW		 7101 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7102 continue;
7103
7104 intel_increase_pllclock(crtc);
7105 if (ring && intel_fbc_enabled(dev))
7106 ring->fbc_dirty = true;
652c393a
JB		 7107 }
7108}
7109
79e53945
JB		 7110static void intel_crtc_destroy(struct drm_crtc *crtc)
7111{
7112 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7113 struct drm_device *dev = crtc->dev;
7114 struct intel_unpin_work *work;
7115 unsigned long flags;
7116
7117 spin_lock_irqsave(&dev->event_lock, flags);
7118 work = intel_crtc->unpin_work;
7119 intel_crtc->unpin_work = NULL;
7120 spin_unlock_irqrestore(&dev->event_lock, flags);
7121
7122 if (work) {
7123 cancel_work_sync(&work->work);
7124 kfree(work);
7125 }
79e53945 7126
40ccc72b
MK		 7127 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7128
79e53945 7129 drm_crtc_cleanup(crtc);
67e77c5a 7130
79e53945
JB		 7131 kfree(intel_crtc);
7132}
7133
6b95a207
KH		 7134static void intel_unpin_work_fn(struct work_struct *__work)
7135{
7136 struct intel_unpin_work *work =
7137 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7138 struct drm_device *dev = work->crtc->dev;
6b95a207 7139
b4a98e57 7140 mutex_lock(&dev->struct_mutex);
1690e1eb 7141 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7142 drm_gem_object_unreference(&work->pending_flip_obj->base);
7143 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7144
b4a98e57
CW		 7145 intel_update_fbc(dev);
7146 mutex_unlock(&dev->struct_mutex);
7147
7148 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7149 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7150
6b95a207
KH		 7151 kfree(work);
7152}
7153
1afe3e9d 7154static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7155 struct drm_crtc *crtc)
6b95a207
KH		 7156{
7157 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7158 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7159 struct intel_unpin_work *work;
6b95a207
KH		 7160 unsigned long flags;
7161
7162 /* Ignore early vblank irqs */
7163 if (intel_crtc == NULL)
7164 return;
7165
7166 spin_lock_irqsave(&dev->event_lock, flags);
7167 work = intel_crtc->unpin_work;
e7d841ca
CW		 7168
7169 /* Ensure we don't miss a work->pending update ... */
7170 smp_rmb();
7171
7172 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7173 spin_unlock_irqrestore(&dev->event_lock, flags);
7174 return;
7175 }
7176
e7d841ca
CW		 7177 /* and that the unpin work is consistent wrt ->pending. */
7178 smp_rmb();
7179
6b95a207 7180 intel_crtc->unpin_work = NULL;
6b95a207 7181
45a066eb
RC		 7182 if (work->event)
7183 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7184
0af7e4df
MK		 7185 drm_vblank_put(dev, intel_crtc->pipe);
7186
6b95a207
KH		 7187 spin_unlock_irqrestore(&dev->event_lock, flags);
7188
2c10d571 7189 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7190
7191 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7192
7193 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7194}
7195
1afe3e9d
JB		 7196void intel_finish_page_flip(struct drm_device *dev, int pipe)
7197{
7198 drm_i915_private_t *dev_priv = dev->dev_private;
7199 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7200
49b14a5c 7201 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7202}
7203
7204void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7205{
7206 drm_i915_private_t *dev_priv = dev->dev_private;
7207 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7208
49b14a5c 7209 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7210}
7211
6b95a207
KH		 7212void intel_prepare_page_flip(struct drm_device *dev, int plane)
7213{
7214 drm_i915_private_t *dev_priv = dev->dev_private;
7215 struct intel_crtc *intel_crtc =
7216 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7217 unsigned long flags;
7218
e7d841ca
CW		 7219 /* NB: An MMIO update of the plane base pointer will also
7220 * generate a page-flip completion irq, i.e. every modeset
7221 * is also accompanied by a spurious intel_prepare_page_flip().
7222 */
6b95a207 7223 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7224 if (intel_crtc->unpin_work)
7225 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7226 spin_unlock_irqrestore(&dev->event_lock, flags);
7227}
7228
e7d841ca
CW		 7229inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7230{
7231 /* Ensure that the work item is consistent when activating it ... */
7232 smp_wmb();
7233 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7234 /* and that it is marked active as soon as the irq could fire. */
7235 smp_wmb();
7236}
7237
8c9f3aaf
JB		 7238static int intel_gen2_queue_flip(struct drm_device *dev,
7239 struct drm_crtc *crtc,
7240 struct drm_framebuffer *fb,
7241 struct drm_i915_gem_object *obj)
7242{
7243 struct drm_i915_private *dev_priv = dev->dev_private;
7244 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7245 u32 flip_mask;
6d90c952 7246 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7247 int ret;
7248
6d90c952 7249 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7250 if (ret)
83d4092b 7251 goto err;
8c9f3aaf 7252
6d90c952 7253 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7254 if (ret)
83d4092b 7255 goto err_unpin;
8c9f3aaf
JB		 7256
7257 /* Can't queue multiple flips, so wait for the previous
7258 * one to finish before executing the next.
7259 */
7260 if (intel_crtc->plane)
7261 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7262 else
7263 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7264 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7265 intel_ring_emit(ring, MI_NOOP);
7266 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7267 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7268 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7269 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 7270 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7271
7272 intel_mark_page_flip_active(intel_crtc);
6d90c952 7273 intel_ring_advance(ring);
83d4092b
CW		 7274 return 0;
7275
7276err_unpin:
7277 intel_unpin_fb_obj(obj);
7278err:
8c9f3aaf
JB		 7279 return ret;
7280}
7281
7282static int intel_gen3_queue_flip(struct drm_device *dev,
7283 struct drm_crtc *crtc,
7284 struct drm_framebuffer *fb,
7285 struct drm_i915_gem_object *obj)
7286{
7287 struct drm_i915_private *dev_priv = dev->dev_private;
7288 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7289 u32 flip_mask;
6d90c952 7290 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7291 int ret;
7292
6d90c952 7293 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7294 if (ret)
83d4092b 7295 goto err;
8c9f3aaf 7296
6d90c952 7297 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7298 if (ret)
83d4092b 7299 goto err_unpin;
8c9f3aaf
JB		 7300
7301 if (intel_crtc->plane)
7302 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7303 else
7304 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7305 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7306 intel_ring_emit(ring, MI_NOOP);
7307 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7308 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7309 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7310 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7311 intel_ring_emit(ring, MI_NOOP);
7312
e7d841ca 7313 intel_mark_page_flip_active(intel_crtc);
6d90c952 7314 intel_ring_advance(ring);
83d4092b
CW		 7315 return 0;
7316
7317err_unpin:
7318 intel_unpin_fb_obj(obj);
7319err:
8c9f3aaf
JB		 7320 return ret;
7321}
7322
7323static int intel_gen4_queue_flip(struct drm_device *dev,
7324 struct drm_crtc *crtc,
7325 struct drm_framebuffer *fb,
7326 struct drm_i915_gem_object *obj)
7327{
7328 struct drm_i915_private *dev_priv = dev->dev_private;
7329 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7330 uint32_t pf, pipesrc;
6d90c952 7331 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7332 int ret;
7333
6d90c952 7334 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7335 if (ret)
83d4092b 7336 goto err;
8c9f3aaf 7337
6d90c952 7338 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7339 if (ret)
83d4092b 7340 goto err_unpin;
8c9f3aaf
JB		 7341
7342 /* i965+ uses the linear or tiled offsets from the
7343 * Display Registers (which do not change across a page-flip)
7344 * so we need only reprogram the base address.
7345 */
6d90c952
DV		 7346 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7347 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7348 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7349 intel_ring_emit(ring,
7350 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7351 obj->tiling_mode);
8c9f3aaf
JB		 7352
7353 /* XXX Enabling the panel-fitter across page-flip is so far
7354 * untested on non-native modes, so ignore it for now.
7355 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7356 */
7357 pf = 0;
7358 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7359 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7360
7361 intel_mark_page_flip_active(intel_crtc);
6d90c952 7362 intel_ring_advance(ring);
83d4092b
CW		 7363 return 0;
7364
7365err_unpin:
7366 intel_unpin_fb_obj(obj);
7367err:
8c9f3aaf
JB		 7368 return ret;
7369}
7370
7371static int intel_gen6_queue_flip(struct drm_device *dev,
7372 struct drm_crtc *crtc,
7373 struct drm_framebuffer *fb,
7374 struct drm_i915_gem_object *obj)
7375{
7376 struct drm_i915_private *dev_priv = dev->dev_private;
7377 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7378 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7379 uint32_t pf, pipesrc;
7380 int ret;
7381
6d90c952 7382 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7383 if (ret)
83d4092b 7384 goto err;
8c9f3aaf 7385
6d90c952 7386 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7387 if (ret)
83d4092b 7388 goto err_unpin;
8c9f3aaf 7389
6d90c952
DV		 7390 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7391 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7392 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7393 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7394
dc257cf1
DV		 7395 /* Contrary to the suggestions in the documentation,
7396 * "Enable Panel Fitter" does not seem to be required when page
7397 * flipping with a non-native mode, and worse causes a normal
7398 * modeset to fail.
7399 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7400 */
7401 pf = 0;
8c9f3aaf 7402 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7403 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7404
7405 intel_mark_page_flip_active(intel_crtc);
6d90c952 7406 intel_ring_advance(ring);
83d4092b
CW		 7407 return 0;
7408
7409err_unpin:
7410 intel_unpin_fb_obj(obj);
7411err:
8c9f3aaf
JB		 7412 return ret;
7413}
7414
7c9017e5
JB		 7415/*
7416 * On gen7 we currently use the blit ring because (in early silicon at least)
7417 * the render ring doesn't give us interrpts for page flip completion, which
7418 * means clients will hang after the first flip is queued. Fortunately the
7419 * blit ring generates interrupts properly, so use it instead.
7420 */
7421static int intel_gen7_queue_flip(struct drm_device *dev,
7422 struct drm_crtc *crtc,
7423 struct drm_framebuffer *fb,
7424 struct drm_i915_gem_object *obj)
7425{
7426 struct drm_i915_private *dev_priv = dev->dev_private;
7427 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7428 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7429 uint32_t plane_bit = 0;
7c9017e5
JB		 7430 int ret;
7431
7432 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7433 if (ret)
83d4092b 7434 goto err;
7c9017e5 7435
cb05d8de
DV		 7436 switch(intel_crtc->plane) {
7437 case PLANE_A:
7438 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7439 break;
7440 case PLANE_B:
7441 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7442 break;
7443 case PLANE_C:
7444 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7445 break;
7446 default:
7447 WARN_ONCE(1, "unknown plane in flip command\n");
7448 ret = -ENODEV;
ab3951eb 7449 goto err_unpin;
cb05d8de
DV		 7450 }
7451
7c9017e5
JB		 7452 ret = intel_ring_begin(ring, 4);
7453 if (ret)
83d4092b 7454 goto err_unpin;
7c9017e5 7455
cb05d8de 7456 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7457 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7458 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7459 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7460
7461 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7462 intel_ring_advance(ring);
83d4092b
CW		 7463 return 0;
7464
7465err_unpin:
7466 intel_unpin_fb_obj(obj);
7467err:
7c9017e5
JB		 7468 return ret;
7469}
7470
8c9f3aaf
JB		 7471static int intel_default_queue_flip(struct drm_device *dev,
7472 struct drm_crtc *crtc,
7473 struct drm_framebuffer *fb,
7474 struct drm_i915_gem_object *obj)
7475{
7476 return -ENODEV;
7477}
7478
6b95a207
KH		 7479static int intel_crtc_page_flip(struct drm_crtc *crtc,
7480 struct drm_framebuffer *fb,
7481 struct drm_pending_vblank_event *event)
7482{
7483 struct drm_device *dev = crtc->dev;
7484 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7485 struct drm_framebuffer *old_fb = crtc->fb;
7486 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7487 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7488 struct intel_unpin_work *work;
8c9f3aaf 7489 unsigned long flags;
52e68630 7490 int ret;
6b95a207 7491
e6a595d2
VS		 7492 /* Can't change pixel format via MI display flips. */
7493 if (fb->pixel_format != crtc->fb->pixel_format)
7494 return -EINVAL;
7495
7496 /*
7497 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7498 * Note that pitch changes could also affect these register.
7499 */
7500 if (INTEL_INFO(dev)->gen > 3 &&
7501 (fb->offsets[0] != crtc->fb->offsets[0] ||
7502 fb->pitches[0] != crtc->fb->pitches[0]))
7503 return -EINVAL;
7504
6b95a207
KH		 7505 work = kzalloc(sizeof *work, GFP_KERNEL);
7506 if (work == NULL)
7507 return -ENOMEM;
7508
6b95a207 7509 work->event = event;
b4a98e57 7510 work->crtc = crtc;
4a35f83b 7511 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7512 INIT_WORK(&work->work, intel_unpin_work_fn);
7513
7317c75e
JB		 7514 ret = drm_vblank_get(dev, intel_crtc->pipe);
7515 if (ret)
7516 goto free_work;
7517
6b95a207
KH		 7518 /* We borrow the event spin lock for protecting unpin_work */
7519 spin_lock_irqsave(&dev->event_lock, flags);
7520 if (intel_crtc->unpin_work) {
7521 spin_unlock_irqrestore(&dev->event_lock, flags);
7522 kfree(work);
7317c75e 7523 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7524
7525 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7526 return -EBUSY;
7527 }
7528 intel_crtc->unpin_work = work;
7529 spin_unlock_irqrestore(&dev->event_lock, flags);
7530
b4a98e57
CW		 7531 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7532 flush_workqueue(dev_priv->wq);
7533
79158103
CW		 7534 ret = i915_mutex_lock_interruptible(dev);
7535 if (ret)
7536 goto cleanup;
6b95a207 7537
75dfca80 7538 /* Reference the objects for the scheduled work. */
05394f39
CW		 7539 drm_gem_object_reference(&work->old_fb_obj->base);
7540 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7541
7542 crtc->fb = fb;
96b099fd 7543
e1f99ce6 7544 work->pending_flip_obj = obj;
e1f99ce6 7545
4e5359cd
SF		 7546 work->enable_stall_check = true;
7547
b4a98e57 7548 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7549 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7550
8c9f3aaf
JB		 7551 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7552 if (ret)
7553 goto cleanup_pending;
6b95a207 7554
7782de3b 7555 intel_disable_fbc(dev);
c65355bb 7556 intel_mark_fb_busy(obj, NULL);
6b95a207
KH		 7557 mutex_unlock(&dev->struct_mutex);
7558
e5510fac
JB		 7559 trace_i915_flip_request(intel_crtc->plane, obj);
7560
6b95a207 7561 return 0;
96b099fd 7562
8c9f3aaf 7563cleanup_pending:
b4a98e57 7564 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7565 crtc->fb = old_fb;
05394f39
CW		 7566 drm_gem_object_unreference(&work->old_fb_obj->base);
7567 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7568 mutex_unlock(&dev->struct_mutex);
7569
79158103 7570cleanup:
96b099fd
CW		 7571 spin_lock_irqsave(&dev->event_lock, flags);
7572 intel_crtc->unpin_work = NULL;
7573 spin_unlock_irqrestore(&dev->event_lock, flags);
7574
7317c75e
JB		 7575 drm_vblank_put(dev, intel_crtc->pipe);
7576free_work:
96b099fd
CW		 7577 kfree(work);
7578
7579 return ret;
6b95a207
KH		 7580}
7581
f6e5b160 7582static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7583 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7584 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7585};
7586
50f56119
DV		 7587static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7588 struct drm_crtc *crtc)
7589{
7590 struct drm_device *dev;
7591 struct drm_crtc *tmp;
7592 int crtc_mask = 1;
47f1c6c9 7593
50f56119 7594 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7595
50f56119 7596 dev = crtc->dev;
47f1c6c9 7597
50f56119
DV		 7598 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7599 if (tmp == crtc)
7600 break;
7601 crtc_mask <<= 1;
7602 }
47f1c6c9 7603
50f56119
DV		 7604 if (encoder->possible_crtcs & crtc_mask)
7605 return true;
7606 return false;
47f1c6c9 7607}
79e53945 7608
9a935856
DV		 7609/**
7610 * intel_modeset_update_staged_output_state
7611 *
7612 * Updates the staged output configuration state, e.g. after we've read out the
7613 * current hw state.
7614 */
7615static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7616{
9a935856
DV		 7617 struct intel_encoder *encoder;
7618 struct intel_connector *connector;
f6e5b160 7619
9a935856
DV		 7620 list_for_each_entry(connector, &dev->mode_config.connector_list,
7621 base.head) {
7622 connector->new_encoder =
7623 to_intel_encoder(connector->base.encoder);
7624 }
f6e5b160 7625
9a935856
DV		 7626 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7627 base.head) {
7628 encoder->new_crtc =
7629 to_intel_crtc(encoder->base.crtc);
7630 }
f6e5b160
CW		 7631}
7632
9a935856
DV		 7633/**
7634 * intel_modeset_commit_output_state
7635 *
7636 * This function copies the stage display pipe configuration to the real one.
7637 */
7638static void intel_modeset_commit_output_state(struct drm_device *dev)
7639{
7640 struct intel_encoder *encoder;
7641 struct intel_connector *connector;
f6e5b160 7642
9a935856
DV		 7643 list_for_each_entry(connector, &dev->mode_config.connector_list,
7644 base.head) {
7645 connector->base.encoder = &connector->new_encoder->base;
7646 }
f6e5b160 7647
9a935856
DV		 7648 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7649 base.head) {
7650 encoder->base.crtc = &encoder->new_crtc->base;
7651 }
7652}
7653
050f7aeb
DV		 7654static void
7655connected_sink_compute_bpp(struct intel_connector * connector,
7656 struct intel_crtc_config *pipe_config)
7657{
7658 int bpp = pipe_config->pipe_bpp;
7659
7660 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7661 connector->base.base.id,
7662 drm_get_connector_name(&connector->base));
7663
7664 /* Don't use an invalid EDID bpc value */
7665 if (connector->base.display_info.bpc &&
7666 connector->base.display_info.bpc * 3 < bpp) {
7667 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7668 bpp, connector->base.display_info.bpc*3);
7669 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7670 }
7671
7672 /* Clamp bpp to 8 on screens without EDID 1.4 */
7673 if (connector->base.display_info.bpc == 0 && bpp > 24) {
7674 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7675 bpp);
7676 pipe_config->pipe_bpp = 24;
7677 }
7678}
7679
4e53c2e0 7680static int
050f7aeb
DV		 7681compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7682 struct drm_framebuffer *fb,
7683 struct intel_crtc_config *pipe_config)
4e53c2e0 7684{
050f7aeb
DV		 7685 struct drm_device *dev = crtc->base.dev;
7686 struct intel_connector *connector;
4e53c2e0
DV		 7687 int bpp;
7688
d42264b1
DV		 7689 switch (fb->pixel_format) {
7690 case DRM_FORMAT_C8:
4e53c2e0
DV		 7691 bpp = 8*3; /* since we go through a colormap */
7692 break;
d42264b1
DV		 7693 case DRM_FORMAT_XRGB1555:
7694 case DRM_FORMAT_ARGB1555:
7695 /* checked in intel_framebuffer_init already */
7696 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7697 return -EINVAL;
7698 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 7699 bpp = 6*3; /* min is 18bpp */
7700 break;
d42264b1
DV		 7701 case DRM_FORMAT_XBGR8888:
7702 case DRM_FORMAT_ABGR8888:
7703 /* checked in intel_framebuffer_init already */
7704 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7705 return -EINVAL;
7706 case DRM_FORMAT_XRGB8888:
7707 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 7708 bpp = 8*3;
7709 break;
d42264b1
DV		 7710 case DRM_FORMAT_XRGB2101010:
7711 case DRM_FORMAT_ARGB2101010:
7712 case DRM_FORMAT_XBGR2101010:
7713 case DRM_FORMAT_ABGR2101010:
7714 /* checked in intel_framebuffer_init already */
7715 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 7716 return -EINVAL;
4e53c2e0
DV		 7717 bpp = 10*3;
7718 break;
baba133a 7719 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 7720 default:
7721 DRM_DEBUG_KMS("unsupported depth\n");
7722 return -EINVAL;
7723 }
7724
4e53c2e0
DV		 7725 pipe_config->pipe_bpp = bpp;
7726
7727 /* Clamp display bpp to EDID value */
7728 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 7729 base.head) {
1b829e05
DV		 7730 if (!connector->new_encoder ||
7731 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 7732 continue;
7733
050f7aeb 7734 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 7735 }
7736
7737 return bpp;
7738}
7739
c0b03411
DV		 7740static void intel_dump_pipe_config(struct intel_crtc *crtc,
7741 struct intel_crtc_config *pipe_config,
7742 const char *context)
7743{
7744 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7745 context, pipe_name(crtc->pipe));
7746
7747 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7748 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7749 pipe_config->pipe_bpp, pipe_config->dither);
7750 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7751 pipe_config->has_pch_encoder,
7752 pipe_config->fdi_lanes,
7753 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7754 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7755 pipe_config->fdi_m_n.tu);
7756 DRM_DEBUG_KMS("requested mode:\n");
7757 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7758 DRM_DEBUG_KMS("adjusted mode:\n");
7759 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7760 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7761 pipe_config->gmch_pfit.control,
7762 pipe_config->gmch_pfit.pgm_ratios,
7763 pipe_config->gmch_pfit.lvds_border_bits);
7764 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7765 pipe_config->pch_pfit.pos,
7766 pipe_config->pch_pfit.size);
42db64ef 7767 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
c0b03411
DV		 7768}
7769
accfc0c5
DV		 7770static bool check_encoder_cloning(struct drm_crtc *crtc)
7771{
7772 int num_encoders = 0;
7773 bool uncloneable_encoders = false;
7774 struct intel_encoder *encoder;
7775
7776 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
7777 base.head) {
7778 if (&encoder->new_crtc->base != crtc)
7779 continue;
7780
7781 num_encoders++;
7782 if (!encoder->cloneable)
7783 uncloneable_encoders = true;
7784 }
7785
7786 return !(num_encoders > 1 && uncloneable_encoders);
7787}
7788
b8cecdf5
DV		 7789static struct intel_crtc_config *
7790intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 7791 struct drm_framebuffer *fb,
b8cecdf5 7792 struct drm_display_mode *mode)
ee7b9f93 7793{
7758a113 7794 struct drm_device *dev = crtc->dev;
7758a113
DV		 7795 struct drm_encoder_helper_funcs *encoder_funcs;
7796 struct intel_encoder *encoder;
b8cecdf5 7797 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 7798 int plane_bpp, ret = -EINVAL;
7799 bool retry = true;
ee7b9f93 7800
accfc0c5
DV		 7801 if (!check_encoder_cloning(crtc)) {
7802 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
7803 return ERR_PTR(-EINVAL);
7804 }
7805
b8cecdf5
DV		 7806 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7807 if (!pipe_config)
7758a113
DV		 7808 return ERR_PTR(-ENOMEM);
7809
b8cecdf5
DV		 7810 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7811 drm_mode_copy(&pipe_config->requested_mode, mode);
eccb140b 7812 pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe;
c0d43d62 7813 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 7814
050f7aeb
DV		 7815 /* Compute a starting value for pipe_config->pipe_bpp taking the source
7816 * plane pixel format and any sink constraints into account. Returns the
7817 * source plane bpp so that dithering can be selected on mismatches
7818 * after encoders and crtc also have had their say. */
7819 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7820 fb, pipe_config);
4e53c2e0
DV		 7821 if (plane_bpp < 0)
7822 goto fail;
7823
e29c22c0 7824encoder_retry:
ef1b460d 7825 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 7826 pipe_config->port_clock = 0;
ef1b460d 7827 pipe_config->pixel_multiplier = 1;
ff9a6750 7828
7758a113
DV		 7829 /* Pass our mode to the connectors and the CRTC to give them a chance to
7830 * adjust it according to limitations or connector properties, and also
7831 * a chance to reject the mode entirely.
47f1c6c9 7832 */
7758a113
DV		 7833 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7834 base.head) {
47f1c6c9 7835
7758a113
DV		 7836 if (&encoder->new_crtc->base != crtc)
7837 continue;
7ae89233
DV		 7838
7839 if (encoder->compute_config) {
7840 if (!(encoder->compute_config(encoder, pipe_config))) {
7841 DRM_DEBUG_KMS("Encoder config failure\n");
7842 goto fail;
7843 }
7844
7845 continue;
7846 }
7847
7758a113 7848 encoder_funcs = encoder->base.helper_private;
b8cecdf5
DV		 7849 if (!(encoder_funcs->mode_fixup(&encoder->base,
7850 &pipe_config->requested_mode,
7851 &pipe_config->adjusted_mode))) {
7758a113
DV		 7852 DRM_DEBUG_KMS("Encoder fixup failed\n");
7853 goto fail;
7854 }
ee7b9f93 7855 }
47f1c6c9 7856
ff9a6750
DV		 7857 /* Set default port clock if not overwritten by the encoder. Needs to be
7858 * done afterwards in case the encoder adjusts the mode. */
7859 if (!pipe_config->port_clock)
7860 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
7861
a43f6e0f 7862 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 7863 if (ret < 0) {
7758a113
DV		 7864 DRM_DEBUG_KMS("CRTC fixup failed\n");
7865 goto fail;
ee7b9f93 7866 }
e29c22c0
DV		 7867
7868 if (ret == RETRY) {
7869 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7870 ret = -EINVAL;
7871 goto fail;
7872 }
7873
7874 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7875 retry = false;
7876 goto encoder_retry;
7877 }
7878
4e53c2e0
DV		 7879 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7880 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7881 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7882
b8cecdf5 7883 return pipe_config;
7758a113 7884fail:
b8cecdf5 7885 kfree(pipe_config);
e29c22c0 7886 return ERR_PTR(ret);
ee7b9f93 7887}
47f1c6c9 7888
e2e1ed41
DV		 7889/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7890 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7891static void
7892intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7893 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7894{
7895 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7896 struct drm_device *dev = crtc->dev;
7897 struct intel_encoder *encoder;
7898 struct intel_connector *connector;
7899 struct drm_crtc *tmp_crtc;
79e53945 7900
e2e1ed41 7901 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7902
e2e1ed41
DV		 7903 /* Check which crtcs have changed outputs connected to them, these need
7904 * to be part of the prepare_pipes mask. We don't (yet) support global
7905 * modeset across multiple crtcs, so modeset_pipes will only have one
7906 * bit set at most. */
7907 list_for_each_entry(connector, &dev->mode_config.connector_list,
7908 base.head) {
7909 if (connector->base.encoder == &connector->new_encoder->base)
7910 continue;
79e53945 7911
e2e1ed41
DV		 7912 if (connector->base.encoder) {
7913 tmp_crtc = connector->base.encoder->crtc;
7914
7915 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7916 }
7917
7918 if (connector->new_encoder)
7919 *prepare_pipes |=
7920 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7921 }
7922
e2e1ed41
DV		 7923 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7924 base.head) {
7925 if (encoder->base.crtc == &encoder->new_crtc->base)
7926 continue;
7927
7928 if (encoder->base.crtc) {
7929 tmp_crtc = encoder->base.crtc;
7930
7931 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7932 }
7933
7934 if (encoder->new_crtc)
7935 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7936 }
7937
e2e1ed41
DV		 7938 /* Check for any pipes that will be fully disabled ... */
7939 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7940 base.head) {
7941 bool used = false;
22fd0fab 7942
e2e1ed41
DV		 7943 /* Don't try to disable disabled crtcs. */
7944 if (!intel_crtc->base.enabled)
7945 continue;
7e7d76c3 7946
e2e1ed41
DV		 7947 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7948 base.head) {
7949 if (encoder->new_crtc == intel_crtc)
7950 used = true;
7951 }
7952
7953 if (!used)
7954 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7955 }
7956
e2e1ed41
DV		 7957
7958 /* set_mode is also used to update properties on life display pipes. */
7959 intel_crtc = to_intel_crtc(crtc);
7960 if (crtc->enabled)
7961 *prepare_pipes |= 1 << intel_crtc->pipe;
7962
b6c5164d
DV		 7963 /*
7964 * For simplicity do a full modeset on any pipe where the output routing
7965 * changed. We could be more clever, but that would require us to be
7966 * more careful with calling the relevant encoder->mode_set functions.
7967 */
e2e1ed41
DV		 7968 if (*prepare_pipes)
7969 *modeset_pipes = *prepare_pipes;
7970
7971 /* ... and mask these out. */
7972 *modeset_pipes &= ~(*disable_pipes);
7973 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 7974
7975 /*
7976 * HACK: We don't (yet) fully support global modesets. intel_set_config
7977 * obies this rule, but the modeset restore mode of
7978 * intel_modeset_setup_hw_state does not.
7979 */
7980 *modeset_pipes &= 1 << intel_crtc->pipe;
7981 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 7982
7983 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7984 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 7985}
79e53945 7986
ea9d758d 7987static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7988{
ea9d758d 7989 struct drm_encoder *encoder;
f6e5b160 7990 struct drm_device *dev = crtc->dev;
f6e5b160 7991
ea9d758d
DV		 7992 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7993 if (encoder->crtc == crtc)
7994 return true;
7995
7996 return false;
7997}
7998
7999static void
8000intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8001{
8002 struct intel_encoder *intel_encoder;
8003 struct intel_crtc *intel_crtc;
8004 struct drm_connector *connector;
8005
8006 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8007 base.head) {
8008 if (!intel_encoder->base.crtc)
8009 continue;
8010
8011 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8012
8013 if (prepare_pipes & (1 << intel_crtc->pipe))
8014 intel_encoder->connectors_active = false;
8015 }
8016
8017 intel_modeset_commit_output_state(dev);
8018
8019 /* Update computed state. */
8020 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8021 base.head) {
8022 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8023 }
8024
8025 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8026 if (!connector->encoder || !connector->encoder->crtc)
8027 continue;
8028
8029 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8030
8031 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8032 struct drm_property *dpms_property =
8033 dev->mode_config.dpms_property;
8034
ea9d758d 8035 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8036 drm_object_property_set_value(&connector->base,
68d34720
DV		 8037 dpms_property,
8038 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8039
8040 intel_encoder = to_intel_encoder(connector->encoder);
8041 intel_encoder->connectors_active = true;
8042 }
8043 }
8044
8045}
8046
25c5b266
DV		 8047#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8048 list_for_each_entry((intel_crtc), \
8049 &(dev)->mode_config.crtc_list, \
8050 base.head) \
0973f18f 8051 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8052
0e8ffe1b 8053static bool
2fa2fe9a
DV		 8054intel_pipe_config_compare(struct drm_device *dev,
8055 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8056 struct intel_crtc_config *pipe_config)
8057{
08a24034
DV		 8058#define PIPE_CONF_CHECK_I(name) \
8059 if (current_config->name != pipe_config->name) { \
8060 DRM_ERROR("mismatch in " #name " " \
8061 "(expected %i, found %i)\n", \
8062 current_config->name, \
8063 pipe_config->name); \
8064 return false; \
88adfff1
DV		 8065 }
8066
1bd1bd80
DV		 8067#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8068 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8069 DRM_ERROR("mismatch in " #name " " \
8070 "(expected %i, found %i)\n", \
8071 current_config->name & (mask), \
8072 pipe_config->name & (mask)); \
8073 return false; \
8074 }
8075
bb760063
DV		 8076#define PIPE_CONF_QUIRK(quirk) \
8077 ((current_config->quirks | pipe_config->quirks) & (quirk))
8078
eccb140b
DV		 8079 PIPE_CONF_CHECK_I(cpu_transcoder);
8080
08a24034
DV		 8081 PIPE_CONF_CHECK_I(has_pch_encoder);
8082 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8083 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8084 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8085 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8086 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8087 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8088
1bd1bd80
DV		 8089 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8090 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8091 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8092 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8093 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8094 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8095
8096 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8097 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8098 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8099 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8100 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8101 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8102
6c49f241
DV		 8103 if (!HAS_PCH_SPLIT(dev))
8104 PIPE_CONF_CHECK_I(pixel_multiplier);
8105
1bd1bd80
DV		 8106 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8107 DRM_MODE_FLAG_INTERLACE);
8108
bb760063
DV		 8109 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8110 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8111 DRM_MODE_FLAG_PHSYNC);
8112 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8113 DRM_MODE_FLAG_NHSYNC);
8114 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8115 DRM_MODE_FLAG_PVSYNC);
8116 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8117 DRM_MODE_FLAG_NVSYNC);
8118 }
045ac3b5 8119
1bd1bd80
DV		 8120 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8121 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8122
2fa2fe9a
DV		 8123 PIPE_CONF_CHECK_I(gmch_pfit.control);
8124 /* pfit ratios are autocomputed by the hw on gen4+ */
8125 if (INTEL_INFO(dev)->gen < 4)
8126 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8127 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8128 PIPE_CONF_CHECK_I(pch_pfit.pos);
8129 PIPE_CONF_CHECK_I(pch_pfit.size);
8130
42db64ef
PZ		 8131 PIPE_CONF_CHECK_I(ips_enabled);
8132
c0d43d62
DV		 8133 PIPE_CONF_CHECK_I(shared_dpll);
8134
08a24034 8135#undef PIPE_CONF_CHECK_I
1bd1bd80 8136#undef PIPE_CONF_CHECK_FLAGS
bb760063 8137#undef PIPE_CONF_QUIRK
627eb5a3 8138
0e8ffe1b
DV		 8139 return true;
8140}
8141
b980514c 8142void
8af6cf88
DV		 8143intel_modeset_check_state(struct drm_device *dev)
8144{
0e8ffe1b 8145 drm_i915_private_t *dev_priv = dev->dev_private;
8af6cf88
DV		 8146 struct intel_crtc *crtc;
8147 struct intel_encoder *encoder;
8148 struct intel_connector *connector;
0e8ffe1b 8149 struct intel_crtc_config pipe_config;
8af6cf88
DV		 8150
8151 list_for_each_entry(connector, &dev->mode_config.connector_list,
8152 base.head) {
8153 /* This also checks the encoder/connector hw state with the
8154 * ->get_hw_state callbacks. */
8155 intel_connector_check_state(connector);
8156
8157 WARN(&connector->new_encoder->base != connector->base.encoder,
8158 "connector's staged encoder doesn't match current encoder\n");
8159 }
8160
8161 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8162 base.head) {
8163 bool enabled = false;
8164 bool active = false;
8165 enum pipe pipe, tracked_pipe;
8166
8167 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8168 encoder->base.base.id,
8169 drm_get_encoder_name(&encoder->base));
8170
8171 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8172 "encoder's stage crtc doesn't match current crtc\n");
8173 WARN(encoder->connectors_active && !encoder->base.crtc,
8174 "encoder's active_connectors set, but no crtc\n");
8175
8176 list_for_each_entry(connector, &dev->mode_config.connector_list,
8177 base.head) {
8178 if (connector->base.encoder != &encoder->base)
8179 continue;
8180 enabled = true;
8181 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8182 active = true;
8183 }
8184 WARN(!!encoder->base.crtc != enabled,
8185 "encoder's enabled state mismatch "
8186 "(expected %i, found %i)\n",
8187 !!encoder->base.crtc, enabled);
8188 WARN(active && !encoder->base.crtc,
8189 "active encoder with no crtc\n");
8190
8191 WARN(encoder->connectors_active != active,
8192 "encoder's computed active state doesn't match tracked active state "
8193 "(expected %i, found %i)\n", active, encoder->connectors_active);
8194
8195 active = encoder->get_hw_state(encoder, &pipe);
8196 WARN(active != encoder->connectors_active,
8197 "encoder's hw state doesn't match sw tracking "
8198 "(expected %i, found %i)\n",
8199 encoder->connectors_active, active);
8200
8201 if (!encoder->base.crtc)
8202 continue;
8203
8204 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8205 WARN(active && pipe != tracked_pipe,
8206 "active encoder's pipe doesn't match"
8207 "(expected %i, found %i)\n",
8208 tracked_pipe, pipe);
8209
8210 }
8211
8212 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8213 base.head) {
8214 bool enabled = false;
8215 bool active = false;
8216
045ac3b5
JB		 8217 memset(&pipe_config, 0, sizeof(pipe_config));
8218
8af6cf88
DV		 8219 DRM_DEBUG_KMS("[CRTC:%d]\n",
8220 crtc->base.base.id);
8221
8222 WARN(crtc->active && !crtc->base.enabled,
8223 "active crtc, but not enabled in sw tracking\n");
8224
8225 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8226 base.head) {
8227 if (encoder->base.crtc != &crtc->base)
8228 continue;
8229 enabled = true;
8230 if (encoder->connectors_active)
8231 active = true;
8232 }
6c49f241 8233
8af6cf88
DV		 8234 WARN(active != crtc->active,
8235 "crtc's computed active state doesn't match tracked active state "
8236 "(expected %i, found %i)\n", active, crtc->active);
8237 WARN(enabled != crtc->base.enabled,
8238 "crtc's computed enabled state doesn't match tracked enabled state "
8239 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8240
0e8ffe1b
DV		 8241 active = dev_priv->display.get_pipe_config(crtc,
8242 &pipe_config);
6c49f241
DV		 8243 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8244 base.head) {
8245 if (encoder->base.crtc != &crtc->base)
8246 continue;
8247 if (encoder->get_config)
8248 encoder->get_config(encoder, &pipe_config);
8249 }
8250
0e8ffe1b
DV		 8251 WARN(crtc->active != active,
8252 "crtc active state doesn't match with hw state "
8253 "(expected %i, found %i)\n", crtc->active, active);
8254
c0b03411
DV		 8255 if (active &&
8256 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8257 WARN(1, "pipe state doesn't match!\n");
8258 intel_dump_pipe_config(crtc, &pipe_config,
8259 "[hw state]");
8260 intel_dump_pipe_config(crtc, &crtc->config,
8261 "[sw state]");
8262 }
8af6cf88
DV		 8263 }
8264}
8265
f30da187
DV		 8266static int __intel_set_mode(struct drm_crtc *crtc,
8267 struct drm_display_mode *mode,
8268 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 8269{
8270 struct drm_device *dev = crtc->dev;
dbf2b54e 8271 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 8272 struct drm_display_mode *saved_mode, *saved_hwmode;
8273 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 8274 struct intel_crtc *intel_crtc;
8275 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 8276 int ret = 0;
a6778b3c 8277
3ac18232 8278 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 8279 if (!saved_mode)
8280 return -ENOMEM;
3ac18232 8281 saved_hwmode = saved_mode + 1;
a6778b3c 8282
e2e1ed41 8283 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 8284 &prepare_pipes, &disable_pipes);
8285
3ac18232
TG		 8286 *saved_hwmode = crtc->hwmode;
8287 *saved_mode = crtc->mode;
a6778b3c 8288
25c5b266
DV		 8289 /* Hack: Because we don't (yet) support global modeset on multiple
8290 * crtcs, we don't keep track of the new mode for more than one crtc.
8291 * Hence simply check whether any bit is set in modeset_pipes in all the
8292 * pieces of code that are not yet converted to deal with mutliple crtcs
8293 * changing their mode at the same time. */
25c5b266 8294 if (modeset_pipes) {
4e53c2e0 8295 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 8296 if (IS_ERR(pipe_config)) {
8297 ret = PTR_ERR(pipe_config);
8298 pipe_config = NULL;
8299
3ac18232 8300 goto out;
25c5b266 8301 }
c0b03411
DV		 8302 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8303 "[modeset]");
25c5b266 8304 }
a6778b3c 8305
460da916
DV		 8306 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8307 intel_crtc_disable(&intel_crtc->base);
8308
ea9d758d
DV		 8309 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8310 if (intel_crtc->base.enabled)
8311 dev_priv->display.crtc_disable(&intel_crtc->base);
8312 }
a6778b3c 8313
6c4c86f5
DV		 8314 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8315 * to set it here already despite that we pass it down the callchain.
f6e5b160 8316 */
b8cecdf5 8317 if (modeset_pipes) {
25c5b266 8318 crtc->mode = *mode;
b8cecdf5
DV		 8319 /* mode_set/enable/disable functions rely on a correct pipe
8320 * config. */
8321 to_intel_crtc(crtc)->config = *pipe_config;
8322 }
7758a113 8323
ea9d758d
DV		 8324 /* Only after disabling all output pipelines that will be changed can we
8325 * update the the output configuration. */
8326 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 8327
47fab737
DV		 8328 if (dev_priv->display.modeset_global_resources)
8329 dev_priv->display.modeset_global_resources(dev);
8330
a6778b3c
DV		 8331 /* Set up the DPLL and any encoders state that needs to adjust or depend
8332 * on the DPLL.
f6e5b160 8333 */
25c5b266 8334 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 8335 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 8336 x, y, fb);
8337 if (ret)
8338 goto done;
a6778b3c
DV		 8339 }
8340
8341 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 8342 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8343 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 8344
25c5b266
DV		 8345 if (modeset_pipes) {
8346 /* Store real post-adjustment hardware mode. */
b8cecdf5 8347 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 8348
25c5b266
DV		 8349 /* Calculate and store various constants which
8350 * are later needed by vblank and swap-completion
8351 * timestamping. They are derived from true hwmode.
8352 */
8353 drm_calc_timestamping_constants(crtc);
8354 }
a6778b3c
DV		 8355
8356 /* FIXME: add subpixel order */
8357done:
c0c36b94 8358 if (ret && crtc->enabled) {
3ac18232
TG		 8359 crtc->hwmode = *saved_hwmode;
8360 crtc->mode = *saved_mode;
a6778b3c
DV		 8361 }
8362
3ac18232 8363out:
b8cecdf5 8364 kfree(pipe_config);
3ac18232 8365 kfree(saved_mode);
a6778b3c 8366 return ret;
f6e5b160
CW		 8367}
8368
f30da187
DV		 8369int intel_set_mode(struct drm_crtc *crtc,
8370 struct drm_display_mode *mode,
8371 int x, int y, struct drm_framebuffer *fb)
8372{
8373 int ret;
8374
8375 ret = __intel_set_mode(crtc, mode, x, y, fb);
8376
8377 if (ret == 0)
8378 intel_modeset_check_state(crtc->dev);
8379
8380 return ret;
8381}
8382
c0c36b94
CW		 8383void intel_crtc_restore_mode(struct drm_crtc *crtc)
8384{
8385 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8386}
8387
25c5b266
DV		 8388#undef for_each_intel_crtc_masked
8389
d9e55608
DV		 8390static void intel_set_config_free(struct intel_set_config *config)
8391{
8392 if (!config)
8393 return;
8394
1aa4b628
DV		 8395 kfree(config->save_connector_encoders);
8396 kfree(config->save_encoder_crtcs);
d9e55608
DV		 8397 kfree(config);
8398}
8399
85f9eb71
DV		 8400static int intel_set_config_save_state(struct drm_device *dev,
8401 struct intel_set_config *config)
8402{
85f9eb71
DV		 8403 struct drm_encoder *encoder;
8404 struct drm_connector *connector;
8405 int count;
8406
1aa4b628
DV		 8407 config->save_encoder_crtcs =
8408 kcalloc(dev->mode_config.num_encoder,
8409 sizeof(struct drm_crtc *), GFP_KERNEL);
8410 if (!config->save_encoder_crtcs)
85f9eb71
DV		 8411 return -ENOMEM;
8412
1aa4b628
DV		 8413 config->save_connector_encoders =
8414 kcalloc(dev->mode_config.num_connector,
8415 sizeof(struct drm_encoder *), GFP_KERNEL);
8416 if (!config->save_connector_encoders)
85f9eb71
DV		 8417 return -ENOMEM;
8418
8419 /* Copy data. Note that driver private data is not affected.
8420 * Should anything bad happen only the expected state is
8421 * restored, not the drivers personal bookkeeping.
8422 */
85f9eb71
DV		 8423 count = 0;
8424 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 8425 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 8426 }
8427
8428 count = 0;
8429 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 8430 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 8431 }
8432
8433 return 0;
8434}
8435
8436static void intel_set_config_restore_state(struct drm_device *dev,
8437 struct intel_set_config *config)
8438{
9a935856
DV		 8439 struct intel_encoder *encoder;
8440 struct intel_connector *connector;
85f9eb71
DV		 8441 int count;
8442
85f9eb71 8443 count = 0;
9a935856
DV		 8444 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8445 encoder->new_crtc =
8446 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 8447 }
8448
8449 count = 0;
9a935856
DV		 8450 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8451 connector->new_encoder =
8452 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 8453 }
8454}
8455
5e2b584e
DV		 8456static void
8457intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8458 struct intel_set_config *config)
8459{
8460
8461 /* We should be able to check here if the fb has the same properties
8462 * and then just flip_or_move it */
8463 if (set->crtc->fb != set->fb) {
8464 /* If we have no fb then treat it as a full mode set */
8465 if (set->crtc->fb == NULL) {
8466 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8467 config->mode_changed = true;
8468 } else if (set->fb == NULL) {
8469 config->mode_changed = true;
72f4901e
DV		 8470 } else if (set->fb->pixel_format !=
8471 set->crtc->fb->pixel_format) {
5e2b584e
DV		 8472 config->mode_changed = true;
8473 } else
8474 config->fb_changed = true;
8475 }
8476
835c5873 8477 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 8478 config->fb_changed = true;
8479
8480 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8481 DRM_DEBUG_KMS("modes are different, full mode set\n");
8482 drm_mode_debug_printmodeline(&set->crtc->mode);
8483 drm_mode_debug_printmodeline(set->mode);
8484 config->mode_changed = true;
8485 }
8486}
8487
2e431051 8488static int
9a935856
DV		 8489intel_modeset_stage_output_state(struct drm_device *dev,
8490 struct drm_mode_set *set,
8491 struct intel_set_config *config)
50f56119 8492{
85f9eb71 8493 struct drm_crtc *new_crtc;
9a935856
DV		 8494 struct intel_connector *connector;
8495 struct intel_encoder *encoder;
2e431051 8496 int count, ro;
50f56119 8497
9abdda74 8498 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 8499 * of connectors. For paranoia, double-check this. */
8500 WARN_ON(!set->fb && (set->num_connectors != 0));
8501 WARN_ON(set->fb && (set->num_connectors == 0));
8502
50f56119 8503 count = 0;
9a935856
DV		 8504 list_for_each_entry(connector, &dev->mode_config.connector_list,
8505 base.head) {
8506 /* Otherwise traverse passed in connector list and get encoders
8507 * for them. */
50f56119 8508 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 8509 if (set->connectors[ro] == &connector->base) {
8510 connector->new_encoder = connector->encoder;
50f56119
DV		 8511 break;
8512 }
8513 }
8514
9a935856
DV		 8515 /* If we disable the crtc, disable all its connectors. Also, if
8516 * the connector is on the changing crtc but not on the new
8517 * connector list, disable it. */
8518 if ((!set->fb || ro == set->num_connectors) &&
8519 connector->base.encoder &&
8520 connector->base.encoder->crtc == set->crtc) {
8521 connector->new_encoder = NULL;
8522
8523 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8524 connector->base.base.id,
8525 drm_get_connector_name(&connector->base));
8526 }
8527
8528
8529 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8530 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8531 config->mode_changed = true;
50f56119
DV		 8532 }
8533 }
9a935856 8534 /* connector->new_encoder is now updated for all connectors. */
50f56119 8535
9a935856 8536 /* Update crtc of enabled connectors. */
50f56119 8537 count = 0;
9a935856
DV		 8538 list_for_each_entry(connector, &dev->mode_config.connector_list,
8539 base.head) {
8540 if (!connector->new_encoder)
50f56119
DV		 8541 continue;
8542
9a935856 8543 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8544
8545 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8546 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8547 new_crtc = set->crtc;
8548 }
8549
8550 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8551 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8552 new_crtc)) {
5e2b584e 8553 return -EINVAL;
50f56119 8554 }
9a935856
DV		 8555 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8556
8557 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8558 connector->base.base.id,
8559 drm_get_connector_name(&connector->base),
8560 new_crtc->base.id);
8561 }
8562
8563 /* Check for any encoders that needs to be disabled. */
8564 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8565 base.head) {
8566 list_for_each_entry(connector,
8567 &dev->mode_config.connector_list,
8568 base.head) {
8569 if (connector->new_encoder == encoder) {
8570 WARN_ON(!connector->new_encoder->new_crtc);
8571
8572 goto next_encoder;
8573 }
8574 }
8575 encoder->new_crtc = NULL;
8576next_encoder:
8577 /* Only now check for crtc changes so we don't miss encoders
8578 * that will be disabled. */
8579 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8580 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8581 config->mode_changed = true;
50f56119
DV		 8582 }
8583 }
9a935856 8584 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8585
2e431051
DV		 8586 return 0;
8587}
8588
8589static int intel_crtc_set_config(struct drm_mode_set *set)
8590{
8591 struct drm_device *dev;
2e431051
DV		 8592 struct drm_mode_set save_set;
8593 struct intel_set_config *config;
8594 int ret;
2e431051 8595
8d3e375e
DV		 8596 BUG_ON(!set);
8597 BUG_ON(!set->crtc);
8598 BUG_ON(!set->crtc->helper_private);
2e431051 8599
7e53f3a4
DV		 8600 /* Enforce sane interface api - has been abused by the fb helper. */
8601 BUG_ON(!set->mode && set->fb);
8602 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 8603
2e431051
DV		 8604 if (set->fb) {
8605 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8606 set->crtc->base.id, set->fb->base.id,
8607 (int)set->num_connectors, set->x, set->y);
8608 } else {
8609 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8610 }
8611
8612 dev = set->crtc->dev;
8613
8614 ret = -ENOMEM;
8615 config = kzalloc(sizeof(*config), GFP_KERNEL);
8616 if (!config)
8617 goto out_config;
8618
8619 ret = intel_set_config_save_state(dev, config);
8620 if (ret)
8621 goto out_config;
8622
8623 save_set.crtc = set->crtc;
8624 save_set.mode = &set->crtc->mode;
8625 save_set.x = set->crtc->x;
8626 save_set.y = set->crtc->y;
8627 save_set.fb = set->crtc->fb;
8628
8629 /* Compute whether we need a full modeset, only an fb base update or no
8630 * change at all. In the future we might also check whether only the
8631 * mode changed, e.g. for LVDS where we only change the panel fitter in
8632 * such cases. */
8633 intel_set_config_compute_mode_changes(set, config);
8634
9a935856 8635 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8636 if (ret)
8637 goto fail;
8638
5e2b584e 8639 if (config->mode_changed) {
c0c36b94
CW		 8640 ret = intel_set_mode(set->crtc, set->mode,
8641 set->x, set->y, set->fb);
8642 if (ret) {
8643 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8644 set->crtc->base.id, ret);
87f1faa6
DV		 8645 goto fail;
8646 }
5e2b584e 8647 } else if (config->fb_changed) {
4878cae2
VS		 8648 intel_crtc_wait_for_pending_flips(set->crtc);
8649
4f660f49 8650 ret = intel_pipe_set_base(set->crtc,
94352cf9 8651 set->x, set->y, set->fb);
50f56119
DV		 8652 }
8653
d9e55608
DV		 8654 intel_set_config_free(config);
8655
50f56119
DV		 8656 return 0;
8657
8658fail:
85f9eb71 8659 intel_set_config_restore_state(dev, config);
50f56119
DV		 8660
8661 /* Try to restore the config */
5e2b584e 8662 if (config->mode_changed &&
c0c36b94
CW		 8663 intel_set_mode(save_set.crtc, save_set.mode,
8664 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8665 DRM_ERROR("failed to restore config after modeset failure\n");
8666
d9e55608
DV		 8667out_config:
8668 intel_set_config_free(config);
50f56119
DV		 8669 return ret;
8670}
f6e5b160
CW		 8671
8672static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8673 .cursor_set = intel_crtc_cursor_set,
8674 .cursor_move = intel_crtc_cursor_move,
8675 .gamma_set = intel_crtc_gamma_set,
50f56119 8676 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8677 .destroy = intel_crtc_destroy,
8678 .page_flip = intel_crtc_page_flip,
8679};
8680
79f689aa
PZ		 8681static void intel_cpu_pll_init(struct drm_device *dev)
8682{
affa9354 8683 if (HAS_DDI(dev))
79f689aa
PZ		 8684 intel_ddi_pll_init(dev);
8685}
8686
e7b903d2
DV		 8687static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
8688 struct intel_shared_dpll *pll)
8689{
8690 uint32_t reg, val;
8691
8692 /* PCH refclock must be enabled first */
8693 assert_pch_refclk_enabled(dev_priv);
8694
8695 reg = PCH_DPLL(pll->id);
8696 val = I915_READ(reg);
8697 val |= DPLL_VCO_ENABLE;
8698 I915_WRITE(reg, val);
8699 POSTING_READ(reg);
8700 udelay(200);
8701}
8702
8703static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
8704 struct intel_shared_dpll *pll)
8705{
8706 struct drm_device *dev = dev_priv->dev;
8707 struct intel_crtc *crtc;
8708 uint32_t reg, val;
8709
8710 /* Make sure no transcoder isn't still depending on us. */
8711 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
8712 if (intel_crtc_to_shared_dpll(crtc) == pll)
8713 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
8714 }
8715
8716 reg = PCH_DPLL(pll->id);
8717 val = I915_READ(reg);
8718 val &= ~DPLL_VCO_ENABLE;
8719 I915_WRITE(reg, val);
8720 POSTING_READ(reg);
8721 udelay(200);
8722}
8723
46edb027
DV		 8724static char *ibx_pch_dpll_names[] = {
8725 "PCH DPLL A",
8726 "PCH DPLL B",
8727};
8728
7c74ade1 8729static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 8730{
e7b903d2 8731 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 8732 int i;
8733
7c74ade1 8734 dev_priv->num_shared_dpll = 2;
ee7b9f93 8735
e72f9fbf 8736 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 8737 dev_priv->shared_dplls[i].id = i;
8738 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
e7b903d2
DV		 8739 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
8740 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
ee7b9f93
JB		 8741 }
8742}
8743
7c74ade1
DV		 8744static void intel_shared_dpll_init(struct drm_device *dev)
8745{
e7b903d2 8746 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1
DV		 8747
8748 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8749 ibx_pch_dpll_init(dev);
8750 else
8751 dev_priv->num_shared_dpll = 0;
8752
8753 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
8754 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
8755 dev_priv->num_shared_dpll);
8756}
8757
b358d0a6 8758static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8759{
22fd0fab 8760 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8761 struct intel_crtc *intel_crtc;
8762 int i;
8763
8764 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8765 if (intel_crtc == NULL)
8766 return;
8767
8768 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8769
8770 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8771 for (i = 0; i < 256; i++) {
8772 intel_crtc->lut_r[i] = i;
8773 intel_crtc->lut_g[i] = i;
8774 intel_crtc->lut_b[i] = i;
8775 }
8776
80824003
JB		 8777 /* Swap pipes & planes for FBC on pre-965 */
8778 intel_crtc->pipe = pipe;
8779 intel_crtc->plane = pipe;
e2e767ab 8780 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8781 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8782 intel_crtc->plane = !pipe;
80824003
JB		 8783 }
8784
22fd0fab
JB		 8785 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8786 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8787 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8788 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8789
79e53945 8790 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8791}
8792
08d7b3d1 8793int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8794 struct drm_file *file)
08d7b3d1 8795{
08d7b3d1 8796 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8797 struct drm_mode_object *drmmode_obj;
8798 struct intel_crtc *crtc;
08d7b3d1 8799
1cff8f6b
DV		 8800 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8801 return -ENODEV;
08d7b3d1 8802
c05422d5
DV		 8803 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8804 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8805
c05422d5 8806 if (!drmmode_obj) {
08d7b3d1
CW		 8807 DRM_ERROR("no such CRTC id\n");
8808 return -EINVAL;
8809 }
8810
c05422d5
DV		 8811 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8812 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8813
c05422d5 8814 return 0;
08d7b3d1
CW		 8815}
8816
66a9278e 8817static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8818{
66a9278e
DV		 8819 struct drm_device *dev = encoder->base.dev;
8820 struct intel_encoder *source_encoder;
79e53945 8821 int index_mask = 0;
79e53945
JB		 8822 int entry = 0;
8823
66a9278e
DV		 8824 list_for_each_entry(source_encoder,
8825 &dev->mode_config.encoder_list, base.head) {
8826
8827 if (encoder == source_encoder)
79e53945 8828 index_mask |= (1 << entry);
66a9278e
DV		 8829
8830 /* Intel hw has only one MUX where enocoders could be cloned. */
8831 if (encoder->cloneable && source_encoder->cloneable)
8832 index_mask |= (1 << entry);
8833
79e53945
JB		 8834 entry++;
8835 }
4ef69c7a 8836
79e53945
JB		 8837 return index_mask;
8838}
8839
4d302442
CW		 8840static bool has_edp_a(struct drm_device *dev)
8841{
8842 struct drm_i915_private *dev_priv = dev->dev_private;
8843
8844 if (!IS_MOBILE(dev))
8845 return false;
8846
8847 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8848 return false;
8849
8850 if (IS_GEN5(dev) &&
8851 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8852 return false;
8853
8854 return true;
8855}
8856
79e53945
JB		 8857static void intel_setup_outputs(struct drm_device *dev)
8858{
725e30ad 8859 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8860 struct intel_encoder *encoder;
cb0953d7 8861 bool dpd_is_edp = false;
f3cfcba6 8862 bool has_lvds;
79e53945 8863
f3cfcba6 8864 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8865 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8866 /* disable the panel fitter on everything but LVDS */
8867 I915_WRITE(PFIT_CONTROL, 0);
8868 }
79e53945 8869
c40c0f5b 8870 if (!IS_ULT(dev))
79935fca 8871 intel_crt_init(dev);
cb0953d7 8872
affa9354 8873 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8874 int found;
8875
8876 /* Haswell uses DDI functions to detect digital outputs */
8877 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8878 /* DDI A only supports eDP */
8879 if (found)
8880 intel_ddi_init(dev, PORT_A);
8881
8882 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8883 * register */
8884 found = I915_READ(SFUSE_STRAP);
8885
8886 if (found & SFUSE_STRAP_DDIB_DETECTED)
8887 intel_ddi_init(dev, PORT_B);
8888 if (found & SFUSE_STRAP_DDIC_DETECTED)
8889 intel_ddi_init(dev, PORT_C);
8890 if (found & SFUSE_STRAP_DDID_DETECTED)
8891 intel_ddi_init(dev, PORT_D);
8892 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8893 int found;
270b3042
DV		 8894 dpd_is_edp = intel_dpd_is_edp(dev);
8895
8896 if (has_edp_a(dev))
8897 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8898
dc0fa718 8899 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 8900 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8901 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8902 if (!found)
e2debe91 8903 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 8904 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8905 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8906 }
8907
dc0fa718 8908 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 8909 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 8910
dc0fa718 8911 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 8912 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 8913
5eb08b69 8914 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8915 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8916
270b3042 8917 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8918 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 8919 } else if (IS_VALLEYVIEW(dev)) {
19c03924 8920 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 8921 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8922 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 8923
dc0fa718 8924 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 8925 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8926 PORT_B);
67cfc203
VS		 8927 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8928 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 8929 }
103a196f 8930 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8931 bool found = false;
7d57382e 8932
e2debe91 8933 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8934 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 8935 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 8936 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8937 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 8938 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 8939 }
27185ae1 8940
e7281eab 8941 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 8942 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 8943 }
13520b05
KH		 8944
8945 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8946
e2debe91 8947 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8948 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 8949 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 8950 }
27185ae1 8951
e2debe91 8952 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 8953
b01f2c3a
JB		 8954 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8955 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 8956 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 8957 }
e7281eab 8958 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 8959 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 8960 }
27185ae1 8961
b01f2c3a 8962 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 8963 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 8964 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 8965 } else if (IS_GEN2(dev))
79e53945
JB		 8966 intel_dvo_init(dev);
8967
103a196f 8968 if (SUPPORTS_TV(dev))
79e53945
JB		 8969 intel_tv_init(dev);
8970
4ef69c7a
CW		 8971 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8972 encoder->base.possible_crtcs = encoder->crtc_mask;
8973 encoder->base.possible_clones =
66a9278e 8974 intel_encoder_clones(encoder);
79e53945 8975 }
47356eb6 8976
dde86e2d 8977 intel_init_pch_refclk(dev);
270b3042
DV		 8978
8979 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8980}
8981
8982static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8983{
8984 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8985
8986 drm_framebuffer_cleanup(fb);
05394f39 8987 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8988
8989 kfree(intel_fb);
8990}
8991
8992static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8993 struct drm_file *file,
79e53945
JB		 8994 unsigned int *handle)
8995{
8996 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8997 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8998
05394f39 8999 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 9000}
9001
9002static const struct drm_framebuffer_funcs intel_fb_funcs = {
9003 .destroy = intel_user_framebuffer_destroy,
9004 .create_handle = intel_user_framebuffer_create_handle,
9005};
9006
38651674
DA		 9007int intel_framebuffer_init(struct drm_device *dev,
9008 struct intel_framebuffer *intel_fb,
308e5bcb 9009 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 9010 struct drm_i915_gem_object *obj)
79e53945 9011{
79e53945
JB		 9012 int ret;
9013
c16ed4be
CW		 9014 if (obj->tiling_mode == I915_TILING_Y) {
9015 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 9016 return -EINVAL;
c16ed4be 9017 }
57cd6508 9018
c16ed4be
CW		 9019 if (mode_cmd->pitches[0] & 63) {
9020 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9021 mode_cmd->pitches[0]);
57cd6508 9022 return -EINVAL;
c16ed4be 9023 }
57cd6508 9024
5d7bd705 9025 /* FIXME <= Gen4 stride limits are bit unclear */
c16ed4be
CW		 9026 if (mode_cmd->pitches[0] > 32768) {
9027 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
9028 mode_cmd->pitches[0]);
5d7bd705 9029 return -EINVAL;
c16ed4be 9030 }
5d7bd705
VS		 9031
9032 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 9033 mode_cmd->pitches[0] != obj->stride) {
9034 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9035 mode_cmd->pitches[0], obj->stride);
5d7bd705 9036 return -EINVAL;
c16ed4be 9037 }
5d7bd705 9038
57779d06 9039 /* Reject formats not supported by any plane early. */
308e5bcb 9040 switch (mode_cmd->pixel_format) {
57779d06 9041 case DRM_FORMAT_C8:
04b3924d
VS		 9042 case DRM_FORMAT_RGB565:
9043 case DRM_FORMAT_XRGB8888:
9044 case DRM_FORMAT_ARGB8888:
57779d06
VS		 9045 break;
9046 case DRM_FORMAT_XRGB1555:
9047 case DRM_FORMAT_ARGB1555:
c16ed4be
CW		 9048 if (INTEL_INFO(dev)->gen > 3) {
9049 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 9050 return -EINVAL;
c16ed4be 9051 }
57779d06
VS		 9052 break;
9053 case DRM_FORMAT_XBGR8888:
9054 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 9055 case DRM_FORMAT_XRGB2101010:
9056 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 9057 case DRM_FORMAT_XBGR2101010:
9058 case DRM_FORMAT_ABGR2101010:
c16ed4be
CW		 9059 if (INTEL_INFO(dev)->gen < 4) {
9060 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 9061 return -EINVAL;
c16ed4be 9062 }
b5626747 9063 break;
04b3924d
VS		 9064 case DRM_FORMAT_YUYV:
9065 case DRM_FORMAT_UYVY:
9066 case DRM_FORMAT_YVYU:
9067 case DRM_FORMAT_VYUY:
c16ed4be
CW		 9068 if (INTEL_INFO(dev)->gen < 5) {
9069 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 9070 return -EINVAL;
c16ed4be 9071 }
57cd6508
CW		 9072 break;
9073 default:
c16ed4be 9074 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 9075 return -EINVAL;
9076 }
9077
90f9a336
VS		 9078 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9079 if (mode_cmd->offsets[0] != 0)
9080 return -EINVAL;
9081
c7d73f6a
DV		 9082 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9083 intel_fb->obj = obj;
9084
79e53945
JB		 9085 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9086 if (ret) {
9087 DRM_ERROR("framebuffer init failed %d\n", ret);
9088 return ret;
9089 }
9090
79e53945
JB		 9091 return 0;
9092}
9093
79e53945
JB		 9094static struct drm_framebuffer *
9095intel_user_framebuffer_create(struct drm_device *dev,
9096 struct drm_file *filp,
308e5bcb 9097 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 9098{
05394f39 9099 struct drm_i915_gem_object *obj;
79e53945 9100
308e5bcb
JB		 9101 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9102 mode_cmd->handles[0]));
c8725226 9103 if (&obj->base == NULL)
cce13ff7 9104 return ERR_PTR(-ENOENT);
79e53945 9105
d2dff872 9106 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 9107}
9108
79e53945 9109static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 9110 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 9111 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 9112};
9113
e70236a8
JB		 9114/* Set up chip specific display functions */
9115static void intel_init_display(struct drm_device *dev)
9116{
9117 struct drm_i915_private *dev_priv = dev->dev_private;
9118
ee9300bb
DV		 9119 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9120 dev_priv->display.find_dpll = g4x_find_best_dpll;
9121 else if (IS_VALLEYVIEW(dev))
9122 dev_priv->display.find_dpll = vlv_find_best_dpll;
9123 else if (IS_PINEVIEW(dev))
9124 dev_priv->display.find_dpll = pnv_find_best_dpll;
9125 else
9126 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9127
affa9354 9128 if (HAS_DDI(dev)) {
0e8ffe1b 9129 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 9130 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 9131 dev_priv->display.crtc_enable = haswell_crtc_enable;
9132 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 9133 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 9134 dev_priv->display.update_plane = ironlake_update_plane;
9135 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 9136 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 9137 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 9138 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9139 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 9140 dev_priv->display.off = ironlake_crtc_off;
17638cd6 9141 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 9142 } else if (IS_VALLEYVIEW(dev)) {
9143 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9144 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9145 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9146 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9147 dev_priv->display.off = i9xx_crtc_off;
9148 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9149 } else {
0e8ffe1b 9150 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 9151 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 9152 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9153 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 9154 dev_priv->display.off = i9xx_crtc_off;
17638cd6 9155 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9156 }
e70236a8 9157
e70236a8 9158 /* Returns the core display clock speed */
25eb05fc
JB		 9159 if (IS_VALLEYVIEW(dev))
9160 dev_priv->display.get_display_clock_speed =
9161 valleyview_get_display_clock_speed;
9162 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 9163 dev_priv->display.get_display_clock_speed =
9164 i945_get_display_clock_speed;
9165 else if (IS_I915G(dev))
9166 dev_priv->display.get_display_clock_speed =
9167 i915_get_display_clock_speed;
f2b115e6 9168 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 9169 dev_priv->display.get_display_clock_speed =
9170 i9xx_misc_get_display_clock_speed;
9171 else if (IS_I915GM(dev))
9172 dev_priv->display.get_display_clock_speed =
9173 i915gm_get_display_clock_speed;
9174 else if (IS_I865G(dev))
9175 dev_priv->display.get_display_clock_speed =
9176 i865_get_display_clock_speed;
f0f8a9ce 9177 else if (IS_I85X(dev))
e70236a8
JB		 9178 dev_priv->display.get_display_clock_speed =
9179 i855_get_display_clock_speed;
9180 else /* 852, 830 */
9181 dev_priv->display.get_display_clock_speed =
9182 i830_get_display_clock_speed;
9183
7f8a8569 9184 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 9185 if (IS_GEN5(dev)) {
674cf967 9186 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 9187 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 9188 } else if (IS_GEN6(dev)) {
674cf967 9189 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 9190 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 9191 } else if (IS_IVYBRIDGE(dev)) {
9192 /* FIXME: detect B0+ stepping and use auto training */
9193 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 9194 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 9195 dev_priv->display.modeset_global_resources =
9196 ivb_modeset_global_resources;
c82e4d26
ED		 9197 } else if (IS_HASWELL(dev)) {
9198 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 9199 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 9200 dev_priv->display.modeset_global_resources =
9201 haswell_modeset_global_resources;
a0e63c22 9202 }
6067aaea 9203 } else if (IS_G4X(dev)) {
e0dac65e 9204 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 9205 }
8c9f3aaf
JB		 9206
9207 /* Default just returns -ENODEV to indicate unsupported */
9208 dev_priv->display.queue_flip = intel_default_queue_flip;
9209
9210 switch (INTEL_INFO(dev)->gen) {
9211 case 2:
9212 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9213 break;
9214
9215 case 3:
9216 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9217 break;
9218
9219 case 4:
9220 case 5:
9221 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9222 break;
9223
9224 case 6:
9225 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9226 break;
7c9017e5
JB		 9227 case 7:
9228 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9229 break;
8c9f3aaf 9230 }
e70236a8
JB		 9231}
9232
b690e96c
JB		 9233/*
9234 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9235 * resume, or other times. This quirk makes sure that's the case for
9236 * affected systems.
9237 */
0206e353 9238static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 9239{
9240 struct drm_i915_private *dev_priv = dev->dev_private;
9241
9242 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 9243 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 9244}
9245
435793df
KP		 9246/*
9247 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9248 */
9249static void quirk_ssc_force_disable(struct drm_device *dev)
9250{
9251 struct drm_i915_private *dev_priv = dev->dev_private;
9252 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 9253 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 9254}
9255
4dca20ef 9256/*
5a15ab5b
CE		 9257 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9258 * brightness value
4dca20ef
CE		 9259 */
9260static void quirk_invert_brightness(struct drm_device *dev)
9261{
9262 struct drm_i915_private *dev_priv = dev->dev_private;
9263 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 9264 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 9265}
9266
b690e96c
JB		 9267struct intel_quirk {
9268 int device;
9269 int subsystem_vendor;
9270 int subsystem_device;
9271 void (*hook)(struct drm_device *dev);
9272};
9273
5f85f176
EE		 9274/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9275struct intel_dmi_quirk {
9276 void (*hook)(struct drm_device *dev);
9277 const struct dmi_system_id (*dmi_id_list)[];
9278};
9279
9280static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9281{
9282 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9283 return 1;
9284}
9285
9286static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9287 {
9288 .dmi_id_list = &(const struct dmi_system_id[]) {
9289 {
9290 .callback = intel_dmi_reverse_brightness,
9291 .ident = "NCR Corporation",
9292 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9293 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9294 },
9295 },
9296 { } /* terminating entry */
9297 },
9298 .hook = quirk_invert_brightness,
9299 },
9300};
9301
c43b5634 9302static struct intel_quirk intel_quirks[] = {
b690e96c 9303 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 9304 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 9305
b690e96c
JB		 9306 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9307 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9308
b690e96c
JB		 9309 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9310 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9311
ccd0d36e 9312 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 9313 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 9314 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 9315
9316 /* Lenovo U160 cannot use SSC on LVDS */
9317 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 9318
9319 /* Sony Vaio Y cannot use SSC on LVDS */
9320 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 9321
9322 /* Acer Aspire 5734Z must invert backlight brightness */
9323 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 9324
9325 /* Acer/eMachines G725 */
9326 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 9327
9328 /* Acer/eMachines e725 */
9329 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 9330
9331 /* Acer/Packard Bell NCL20 */
9332 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 9333
9334 /* Acer Aspire 4736Z */
9335 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 9336};
9337
9338static void intel_init_quirks(struct drm_device *dev)
9339{
9340 struct pci_dev *d = dev->pdev;
9341 int i;
9342
9343 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9344 struct intel_quirk *q = &intel_quirks[i];
9345
9346 if (d->device == q->device &&
9347 (d->subsystem_vendor == q->subsystem_vendor ||
9348 q->subsystem_vendor == PCI_ANY_ID) &&
9349 (d->subsystem_device == q->subsystem_device ||
9350 q->subsystem_device == PCI_ANY_ID))
9351 q->hook(dev);
9352 }
5f85f176
EE		 9353 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9354 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9355 intel_dmi_quirks[i].hook(dev);
9356 }
b690e96c
JB		 9357}
9358
9cce37f4
JB		 9359/* Disable the VGA plane that we never use */
9360static void i915_disable_vga(struct drm_device *dev)
9361{
9362 struct drm_i915_private *dev_priv = dev->dev_private;
9363 u8 sr1;
766aa1c4 9364 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 9365
9366 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 9367 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 9368 sr1 = inb(VGA_SR_DATA);
9369 outb(sr1 | 1<<5, VGA_SR_DATA);
9370 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9371 udelay(300);
9372
9373 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9374 POSTING_READ(vga_reg);
9375}
9376
f817586c
DV		 9377void intel_modeset_init_hw(struct drm_device *dev)
9378{
fa42e23c 9379 intel_init_power_well(dev);
0232e927 9380
a8f78b58
ED		 9381 intel_prepare_ddi(dev);
9382
f817586c
DV		 9383 intel_init_clock_gating(dev);
9384
79f5b2c7 9385 mutex_lock(&dev->struct_mutex);
8090c6b9 9386 intel_enable_gt_powersave(dev);
79f5b2c7 9387 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 9388}
9389
7d708ee4
ID		 9390void intel_modeset_suspend_hw(struct drm_device *dev)
9391{
9392 intel_suspend_hw(dev);
9393}
9394
79e53945
JB		 9395void intel_modeset_init(struct drm_device *dev)
9396{
652c393a 9397 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 9398 int i, j, ret;
79e53945
JB		 9399
9400 drm_mode_config_init(dev);
9401
9402 dev->mode_config.min_width = 0;
9403 dev->mode_config.min_height = 0;
9404
019d96cb
DA		 9405 dev->mode_config.preferred_depth = 24;
9406 dev->mode_config.prefer_shadow = 1;
9407
e6ecefaa 9408 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 9409
b690e96c
JB		 9410 intel_init_quirks(dev);
9411
1fa61106
ED		 9412 intel_init_pm(dev);
9413
e3c74757
BW		 9414 if (INTEL_INFO(dev)->num_pipes == 0)
9415 return;
9416
e70236a8
JB		 9417 intel_init_display(dev);
9418
a6c45cf0
CW		 9419 if (IS_GEN2(dev)) {
9420 dev->mode_config.max_width = 2048;
9421 dev->mode_config.max_height = 2048;
9422 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9423 dev->mode_config.max_width = 4096;
9424 dev->mode_config.max_height = 4096;
79e53945 9425 } else {
a6c45cf0
CW		 9426 dev->mode_config.max_width = 8192;
9427 dev->mode_config.max_height = 8192;
79e53945 9428 }
5d4545ae 9429 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 9430
28c97730 9431 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 9432 INTEL_INFO(dev)->num_pipes,
9433 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 9434
7eb552ae 9435 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
79e53945 9436 intel_crtc_init(dev, i);
7f1f3851
JB		 9437 for (j = 0; j < dev_priv->num_plane; j++) {
9438 ret = intel_plane_init(dev, i, j);
9439 if (ret)
06da8da2
VS		 9440 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9441 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 9442 }
79e53945
JB		 9443 }
9444
79f689aa 9445 intel_cpu_pll_init(dev);
e72f9fbf 9446 intel_shared_dpll_init(dev);
ee7b9f93 9447
9cce37f4
JB		 9448 /* Just disable it once at startup */
9449 i915_disable_vga(dev);
79e53945 9450 intel_setup_outputs(dev);
11be49eb
CW		 9451
9452 /* Just in case the BIOS is doing something questionable. */
9453 intel_disable_fbc(dev);
2c7111db
CW		 9454}
9455
24929352
DV		 9456static void
9457intel_connector_break_all_links(struct intel_connector *connector)
9458{
9459 connector->base.dpms = DRM_MODE_DPMS_OFF;
9460 connector->base.encoder = NULL;
9461 connector->encoder->connectors_active = false;
9462 connector->encoder->base.crtc = NULL;
9463}
9464
7fad798e
DV		 9465static void intel_enable_pipe_a(struct drm_device *dev)
9466{
9467 struct intel_connector *connector;
9468 struct drm_connector *crt = NULL;
9469 struct intel_load_detect_pipe load_detect_temp;
9470
9471 /* We can't just switch on the pipe A, we need to set things up with a
9472 * proper mode and output configuration. As a gross hack, enable pipe A
9473 * by enabling the load detect pipe once. */
9474 list_for_each_entry(connector,
9475 &dev->mode_config.connector_list,
9476 base.head) {
9477 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9478 crt = &connector->base;
9479 break;
9480 }
9481 }
9482
9483 if (!crt)
9484 return;
9485
9486 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9487 intel_release_load_detect_pipe(crt, &load_detect_temp);
9488
652c393a 9489
7fad798e
DV		 9490}
9491
fa555837
DV		 9492static bool
9493intel_check_plane_mapping(struct intel_crtc *crtc)
9494{
7eb552ae
BW		 9495 struct drm_device *dev = crtc->base.dev;
9496 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 9497 u32 reg, val;
9498
7eb552ae 9499 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 9500 return true;
9501
9502 reg = DSPCNTR(!crtc->plane);
9503 val = I915_READ(reg);
9504
9505 if ((val & DISPLAY_PLANE_ENABLE) &&
9506 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9507 return false;
9508
9509 return true;
9510}
9511
24929352
DV		 9512static void intel_sanitize_crtc(struct intel_crtc *crtc)
9513{
9514 struct drm_device *dev = crtc->base.dev;
9515 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 9516 u32 reg;
24929352 9517
24929352 9518 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 9519 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 9520 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9521
9522 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 9523 * disable the crtc (and hence change the state) if it is wrong. Note
9524 * that gen4+ has a fixed plane -> pipe mapping. */
9525 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 9526 struct intel_connector *connector;
9527 bool plane;
9528
24929352
DV		 9529 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9530 crtc->base.base.id);
9531
9532 /* Pipe has the wrong plane attached and the plane is active.
9533 * Temporarily change the plane mapping and disable everything
9534 * ... */
9535 plane = crtc->plane;
9536 crtc->plane = !plane;
9537 dev_priv->display.crtc_disable(&crtc->base);
9538 crtc->plane = plane;
9539
9540 /* ... and break all links. */
9541 list_for_each_entry(connector, &dev->mode_config.connector_list,
9542 base.head) {
9543 if (connector->encoder->base.crtc != &crtc->base)
9544 continue;
9545
9546 intel_connector_break_all_links(connector);
9547 }
9548
9549 WARN_ON(crtc->active);
9550 crtc->base.enabled = false;
9551 }
24929352 9552
7fad798e
DV		 9553 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9554 crtc->pipe == PIPE_A && !crtc->active) {
9555 /* BIOS forgot to enable pipe A, this mostly happens after
9556 * resume. Force-enable the pipe to fix this, the update_dpms
9557 * call below we restore the pipe to the right state, but leave
9558 * the required bits on. */
9559 intel_enable_pipe_a(dev);
9560 }
9561
24929352
DV		 9562 /* Adjust the state of the output pipe according to whether we
9563 * have active connectors/encoders. */
9564 intel_crtc_update_dpms(&crtc->base);
9565
9566 if (crtc->active != crtc->base.enabled) {
9567 struct intel_encoder *encoder;
9568
9569 /* This can happen either due to bugs in the get_hw_state
9570 * functions or because the pipe is force-enabled due to the
9571 * pipe A quirk. */
9572 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9573 crtc->base.base.id,
9574 crtc->base.enabled ? "enabled" : "disabled",
9575 crtc->active ? "enabled" : "disabled");
9576
9577 crtc->base.enabled = crtc->active;
9578
9579 /* Because we only establish the connector -> encoder ->
9580 * crtc links if something is active, this means the
9581 * crtc is now deactivated. Break the links. connector
9582 * -> encoder links are only establish when things are
9583 * actually up, hence no need to break them. */
9584 WARN_ON(crtc->active);
9585
9586 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9587 WARN_ON(encoder->connectors_active);
9588 encoder->base.crtc = NULL;
9589 }
9590 }
9591}
9592
9593static void intel_sanitize_encoder(struct intel_encoder *encoder)
9594{
9595 struct intel_connector *connector;
9596 struct drm_device *dev = encoder->base.dev;
9597
9598 /* We need to check both for a crtc link (meaning that the
9599 * encoder is active and trying to read from a pipe) and the
9600 * pipe itself being active. */
9601 bool has_active_crtc = encoder->base.crtc &&
9602 to_intel_crtc(encoder->base.crtc)->active;
9603
9604 if (encoder->connectors_active && !has_active_crtc) {
9605 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9606 encoder->base.base.id,
9607 drm_get_encoder_name(&encoder->base));
9608
9609 /* Connector is active, but has no active pipe. This is
9610 * fallout from our resume register restoring. Disable
9611 * the encoder manually again. */
9612 if (encoder->base.crtc) {
9613 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9614 encoder->base.base.id,
9615 drm_get_encoder_name(&encoder->base));
9616 encoder->disable(encoder);
9617 }
9618
9619 /* Inconsistent output/port/pipe state happens presumably due to
9620 * a bug in one of the get_hw_state functions. Or someplace else
9621 * in our code, like the register restore mess on resume. Clamp
9622 * things to off as a safer default. */
9623 list_for_each_entry(connector,
9624 &dev->mode_config.connector_list,
9625 base.head) {
9626 if (connector->encoder != encoder)
9627 continue;
9628
9629 intel_connector_break_all_links(connector);
9630 }
9631 }
9632 /* Enabled encoders without active connectors will be fixed in
9633 * the crtc fixup. */
9634}
9635
44cec740 9636void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9637{
9638 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9639 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9640
9641 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9642 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9643 i915_disable_vga(dev);
0fde901f
KM		 9644 }
9645}
9646
24929352
DV		 9647/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9648 * and i915 state tracking structures. */
45e2b5f6
DV		 9649void intel_modeset_setup_hw_state(struct drm_device *dev,
9650 bool force_restore)
24929352
DV		 9651{
9652 struct drm_i915_private *dev_priv = dev->dev_private;
9653 enum pipe pipe;
b5644d05 9654 struct drm_plane *plane;
24929352
DV		 9655 struct intel_crtc *crtc;
9656 struct intel_encoder *encoder;
9657 struct intel_connector *connector;
9658
0e8ffe1b
DV		 9659 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9660 base.head) {
88adfff1 9661 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 9662
0e8ffe1b
DV		 9663 crtc->active = dev_priv->display.get_pipe_config(crtc,
9664 &crtc->config);
24929352
DV		 9665
9666 crtc->base.enabled = crtc->active;
9667
9668 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9669 crtc->base.base.id,
9670 crtc->active ? "enabled" : "disabled");
9671 }
9672
affa9354 9673 if (HAS_DDI(dev))
6441ab5f
PZ		 9674 intel_ddi_setup_hw_pll_state(dev);
9675
24929352
DV		 9676 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9677 base.head) {
9678 pipe = 0;
9679
9680 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 9681 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9682 encoder->base.crtc = &crtc->base;
9683 if (encoder->get_config)
9684 encoder->get_config(encoder, &crtc->config);
24929352
DV		 9685 } else {
9686 encoder->base.crtc = NULL;
9687 }
9688
9689 encoder->connectors_active = false;
9690 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9691 encoder->base.base.id,
9692 drm_get_encoder_name(&encoder->base),
9693 encoder->base.crtc ? "enabled" : "disabled",
9694 pipe);
9695 }
9696
9697 list_for_each_entry(connector, &dev->mode_config.connector_list,
9698 base.head) {
9699 if (connector->get_hw_state(connector)) {
9700 connector->base.dpms = DRM_MODE_DPMS_ON;
9701 connector->encoder->connectors_active = true;
9702 connector->base.encoder = &connector->encoder->base;
9703 } else {
9704 connector->base.dpms = DRM_MODE_DPMS_OFF;
9705 connector->base.encoder = NULL;
9706 }
9707 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9708 connector->base.base.id,
9709 drm_get_connector_name(&connector->base),
9710 connector->base.encoder ? "enabled" : "disabled");
9711 }
9712
9713 /* HW state is read out, now we need to sanitize this mess. */
9714 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9715 base.head) {
9716 intel_sanitize_encoder(encoder);
9717 }
9718
9719 for_each_pipe(pipe) {
9720 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9721 intel_sanitize_crtc(crtc);
c0b03411 9722 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 9723 }
9a935856 9724
45e2b5f6 9725 if (force_restore) {
f30da187
DV		 9726 /*
9727 * We need to use raw interfaces for restoring state to avoid
9728 * checking (bogus) intermediate states.
9729 */
45e2b5f6 9730 for_each_pipe(pipe) {
b5644d05
JB		 9731 struct drm_crtc *crtc =
9732 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 9733
9734 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9735 crtc->fb);
45e2b5f6 9736 }
b5644d05
JB		 9737 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9738 intel_plane_restore(plane);
0fde901f
KM		 9739
9740 i915_redisable_vga(dev);
45e2b5f6
DV		 9741 } else {
9742 intel_modeset_update_staged_output_state(dev);
9743 }
8af6cf88
DV		 9744
9745 intel_modeset_check_state(dev);
2e938892
DV		 9746
9747 drm_mode_config_reset(dev);
2c7111db
CW		 9748}
9749
9750void intel_modeset_gem_init(struct drm_device *dev)
9751{
1833b134 9752 intel_modeset_init_hw(dev);
02e792fb
DV		 9753
9754 intel_setup_overlay(dev);
24929352 9755
45e2b5f6 9756 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9757}
9758
9759void intel_modeset_cleanup(struct drm_device *dev)
9760{
652c393a
JB		 9761 struct drm_i915_private *dev_priv = dev->dev_private;
9762 struct drm_crtc *crtc;
9763 struct intel_crtc *intel_crtc;
9764
fd0c0642
DV		 9765 /*
9766 * Interrupts and polling as the first thing to avoid creating havoc.
9767 * Too much stuff here (turning of rps, connectors, ...) would
9768 * experience fancy races otherwise.
9769 */
9770 drm_irq_uninstall(dev);
9771 cancel_work_sync(&dev_priv->hotplug_work);
9772 /*
9773 * Due to the hpd irq storm handling the hotplug work can re-arm the
9774 * poll handlers. Hence disable polling after hpd handling is shut down.
9775 */
f87ea761 9776 drm_kms_helper_poll_fini(dev);
fd0c0642 9777
652c393a
JB		 9778 mutex_lock(&dev->struct_mutex);
9779
723bfd70
JB		 9780 intel_unregister_dsm_handler();
9781
652c393a
JB		 9782 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9783 /* Skip inactive CRTCs */
9784 if (!crtc->fb)
9785 continue;
9786
9787 intel_crtc = to_intel_crtc(crtc);
3dec0095 9788 intel_increase_pllclock(crtc);
652c393a
JB		 9789 }
9790
973d04f9 9791 intel_disable_fbc(dev);
e70236a8 9792
8090c6b9 9793 intel_disable_gt_powersave(dev);
0cdab21f 9794
930ebb46
DV		 9795 ironlake_teardown_rc6(dev);
9796
69341a5e
KH		 9797 mutex_unlock(&dev->struct_mutex);
9798
1630fe75
CW		 9799 /* flush any delayed tasks or pending work */
9800 flush_scheduled_work();
9801
dc652f90
JN		 9802 /* destroy backlight, if any, before the connectors */
9803 intel_panel_destroy_backlight(dev);
9804
79e53945 9805 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9806
9807 intel_cleanup_overlay(dev);
79e53945
JB		 9808}
9809
f1c79df3
ZW		 9810/*
9811 * Return which encoder is currently attached for connector.
9812 */
df0e9248 9813struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9814{
df0e9248
CW		 9815 return &intel_attached_encoder(connector)->base;
9816}
f1c79df3 9817
df0e9248
CW		 9818void intel_connector_attach_encoder(struct intel_connector *connector,
9819 struct intel_encoder *encoder)
9820{
9821 connector->encoder = encoder;
9822 drm_mode_connector_attach_encoder(&connector->base,
9823 &encoder->base);
79e53945 9824}
28d52043
DA		 9825
9826/*
9827 * set vga decode state - true == enable VGA decode
9828 */
9829int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9830{
9831 struct drm_i915_private *dev_priv = dev->dev_private;
9832 u16 gmch_ctrl;
9833
9834 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9835 if (state)
9836 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9837 else
9838 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9839 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9840 return 0;
9841}
c4a1d9e4
CW		 9842
9843#ifdef CONFIG_DEBUG_FS
9844#include <linux/seq_file.h>
9845
9846struct intel_display_error_state {
ff57f1b0
PZ		 9847
9848 u32 power_well_driver;
9849
c4a1d9e4
CW		 9850 struct intel_cursor_error_state {
9851 u32 control;
9852 u32 position;
9853 u32 base;
9854 u32 size;
52331309 9855 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9856
9857 struct intel_pipe_error_state {
ff57f1b0 9858 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9859 u32 conf;
9860 u32 source;
9861
9862 u32 htotal;
9863 u32 hblank;
9864 u32 hsync;
9865 u32 vtotal;
9866 u32 vblank;
9867 u32 vsync;
52331309 9868 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9869
9870 struct intel_plane_error_state {
9871 u32 control;
9872 u32 stride;
9873 u32 size;
9874 u32 pos;
9875 u32 addr;
9876 u32 surface;
9877 u32 tile_offset;
52331309 9878 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9879};
9880
9881struct intel_display_error_state *
9882intel_display_capture_error_state(struct drm_device *dev)
9883{
0206e353 9884 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9885 struct intel_display_error_state *error;
702e7a56 9886 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9887 int i;
9888
9889 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9890 if (error == NULL)
9891 return NULL;
9892
ff57f1b0
PZ		 9893 if (HAS_POWER_WELL(dev))
9894 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
9895
52331309 9896 for_each_pipe(i) {
702e7a56 9897 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
ff57f1b0 9898 error->pipe[i].cpu_transcoder = cpu_transcoder;
702e7a56 9899
a18c4c3d
PZ		 9900 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9901 error->cursor[i].control = I915_READ(CURCNTR(i));
9902 error->cursor[i].position = I915_READ(CURPOS(i));
9903 error->cursor[i].base = I915_READ(CURBASE(i));
9904 } else {
9905 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9906 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9907 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9908 }
c4a1d9e4
CW		 9909
9910 error->plane[i].control = I915_READ(DSPCNTR(i));
9911 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 9912 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9913 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 9914 error->plane[i].pos = I915_READ(DSPPOS(i));
9915 }
ca291363
PZ		 9916 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9917 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 9918 if (INTEL_INFO(dev)->gen >= 4) {
9919 error->plane[i].surface = I915_READ(DSPSURF(i));
9920 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9921 }
9922
702e7a56 9923 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9924 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9925 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9926 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9927 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9928 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9929 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9930 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9931 }
9932
12d217c7
PZ		 9933 /* In the code above we read the registers without checking if the power
9934 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
9935 * prevent the next I915_WRITE from detecting it and printing an error
9936 * message. */
9937 if (HAS_POWER_WELL(dev))
9938 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
9939
c4a1d9e4
CW		 9940 return error;
9941}
9942
edc3d884
MK		 9943#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
9944
c4a1d9e4 9945void
edc3d884 9946intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 9947 struct drm_device *dev,
9948 struct intel_display_error_state *error)
9949{
9950 int i;
9951
edc3d884 9952 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 9953 if (HAS_POWER_WELL(dev))
edc3d884 9954 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 9955 error->power_well_driver);
52331309 9956 for_each_pipe(i) {
edc3d884
MK		 9957 err_printf(m, "Pipe [%d]:\n", i);
9958 err_printf(m, " CPU transcoder: %c\n",
ff57f1b0 9959 transcoder_name(error->pipe[i].cpu_transcoder));
edc3d884
MK		 9960 err_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9961 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
9962 err_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9963 err_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9964 err_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9965 err_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9966 err_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9967 err_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9968
9969 err_printf(m, "Plane [%d]:\n", i);
9970 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
9971 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 9972 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 9973 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
9974 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 9975 }
4b71a570 9976 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 9977 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 9978 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 9979 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
9980 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 9981 }
9982
edc3d884
MK		 9983 err_printf(m, "Cursor [%d]:\n", i);
9984 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9985 err_printf(m, " POS: %08x\n", error->cursor[i].position);
9986 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4
CW		 9987 }
9988}
9989#endif
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