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a4fc5ed6 KP |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Keith Packard <keithp@keithp.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include <linux/i2c.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
2d1a8a48 | 30 | #include <linux/export.h> |
611032bf | 31 | #include <linux/types.h> |
01527b31 CT |
32 | #include <linux/notifier.h> |
33 | #include <linux/reboot.h> | |
611032bf | 34 | #include <asm/byteorder.h> |
760285e7 | 35 | #include <drm/drmP.h> |
c6f95f27 | 36 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
37 | #include <drm/drm_crtc.h> |
38 | #include <drm/drm_crtc_helper.h> | |
39 | #include <drm/drm_edid.h> | |
a4fc5ed6 | 40 | #include "intel_drv.h" |
760285e7 | 41 | #include <drm/i915_drm.h> |
a4fc5ed6 | 42 | #include "i915_drv.h" |
a4fc5ed6 | 43 | |
a4fc5ed6 KP |
44 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) |
45 | ||
559be30c TP |
46 | /* Compliance test status bits */ |
47 | #define INTEL_DP_RESOLUTION_SHIFT_MASK 0 | |
48 | #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK) | |
49 | #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK) | |
50 | #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK) | |
51 | ||
9dd4ffdf | 52 | struct dp_link_dpll { |
840b32b7 | 53 | int clock; |
9dd4ffdf CML |
54 | struct dpll dpll; |
55 | }; | |
56 | ||
57 | static const struct dp_link_dpll gen4_dpll[] = { | |
840b32b7 | 58 | { 162000, |
9dd4ffdf | 59 | { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, |
840b32b7 | 60 | { 270000, |
9dd4ffdf CML |
61 | { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } |
62 | }; | |
63 | ||
64 | static const struct dp_link_dpll pch_dpll[] = { | |
840b32b7 | 65 | { 162000, |
9dd4ffdf | 66 | { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, |
840b32b7 | 67 | { 270000, |
9dd4ffdf CML |
68 | { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } |
69 | }; | |
70 | ||
65ce4bf5 | 71 | static const struct dp_link_dpll vlv_dpll[] = { |
840b32b7 | 72 | { 162000, |
58f6e632 | 73 | { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, |
840b32b7 | 74 | { 270000, |
65ce4bf5 CML |
75 | { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } |
76 | }; | |
77 | ||
ef9348c8 CML |
78 | /* |
79 | * CHV supports eDP 1.4 that have more link rates. | |
80 | * Below only provides the fixed rate but exclude variable rate. | |
81 | */ | |
82 | static const struct dp_link_dpll chv_dpll[] = { | |
83 | /* | |
84 | * CHV requires to program fractional division for m2. | |
85 | * m2 is stored in fixed point format using formula below | |
86 | * (m2_int << 22) | m2_fraction | |
87 | */ | |
840b32b7 | 88 | { 162000, /* m2_int = 32, m2_fraction = 1677722 */ |
ef9348c8 | 89 | { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } }, |
840b32b7 | 90 | { 270000, /* m2_int = 27, m2_fraction = 0 */ |
ef9348c8 | 91 | { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, |
840b32b7 | 92 | { 540000, /* m2_int = 27, m2_fraction = 0 */ |
ef9348c8 CML |
93 | { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } } |
94 | }; | |
637a9c63 | 95 | |
64987fc5 SJ |
96 | static const int bxt_rates[] = { 162000, 216000, 243000, 270000, |
97 | 324000, 432000, 540000 }; | |
637a9c63 | 98 | static const int skl_rates[] = { 162000, 216000, 270000, |
f4896f15 VS |
99 | 324000, 432000, 540000 }; |
100 | static const int default_rates[] = { 162000, 270000, 540000 }; | |
ef9348c8 | 101 | |
cfcb0fc9 | 102 | /** |
01a7507f | 103 | * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH) |
cfcb0fc9 JB |
104 | * @intel_dp: DP struct |
105 | * | |
106 | * If a CPU or PCH DP output is attached to an eDP panel, this function | |
107 | * will return true, and false otherwise. | |
108 | */ | |
01a7507f | 109 | bool intel_dp_is_edp(struct intel_dp *intel_dp) |
cfcb0fc9 | 110 | { |
da63a9f2 PZ |
111 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
112 | ||
113 | return intel_dig_port->base.type == INTEL_OUTPUT_EDP; | |
cfcb0fc9 JB |
114 | } |
115 | ||
68b4d824 | 116 | static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) |
cfcb0fc9 | 117 | { |
68b4d824 ID |
118 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
119 | ||
120 | return intel_dig_port->base.base.dev; | |
cfcb0fc9 JB |
121 | } |
122 | ||
df0e9248 CW |
123 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
124 | { | |
fa90ecef | 125 | return enc_to_intel_dp(&intel_attached_encoder(connector)->base); |
df0e9248 CW |
126 | } |
127 | ||
ea5b213a | 128 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
1e0560e0 | 129 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp); |
4be73780 | 130 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
093e3f13 | 131 | static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp); |
a8c3344e VS |
132 | static void vlv_steal_power_sequencer(struct drm_device *dev, |
133 | enum pipe pipe); | |
f21a2198 | 134 | static void intel_dp_unset_edid(struct intel_dp *intel_dp); |
a4fc5ed6 | 135 | |
68f357cb JN |
136 | static int intel_dp_num_rates(u8 link_bw_code) |
137 | { | |
138 | switch (link_bw_code) { | |
139 | default: | |
140 | WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", | |
141 | link_bw_code); | |
142 | case DP_LINK_BW_1_62: | |
143 | return 1; | |
144 | case DP_LINK_BW_2_7: | |
145 | return 2; | |
146 | case DP_LINK_BW_5_4: | |
147 | return 3; | |
148 | } | |
149 | } | |
150 | ||
151 | /* update sink rates from dpcd */ | |
152 | static void intel_dp_set_sink_rates(struct intel_dp *intel_dp) | |
153 | { | |
154 | int i, num_rates; | |
155 | ||
156 | num_rates = intel_dp_num_rates(intel_dp->dpcd[DP_MAX_LINK_RATE]); | |
157 | ||
158 | for (i = 0; i < num_rates; i++) | |
159 | intel_dp->sink_rates[i] = default_rates[i]; | |
160 | ||
161 | intel_dp->num_sink_rates = num_rates; | |
162 | } | |
163 | ||
540b0b7f JN |
164 | /* Theoretical max between source and sink */ |
165 | static int intel_dp_max_common_rate(struct intel_dp *intel_dp) | |
a4fc5ed6 | 166 | { |
540b0b7f | 167 | return intel_dp->common_rates[intel_dp->num_common_rates - 1]; |
a4fc5ed6 KP |
168 | } |
169 | ||
540b0b7f JN |
170 | /* Theoretical max between source and sink */ |
171 | static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp) | |
eeb6324d PZ |
172 | { |
173 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
540b0b7f JN |
174 | int source_max = intel_dig_port->max_lanes; |
175 | int sink_max = drm_dp_max_lane_count(intel_dp->dpcd); | |
eeb6324d PZ |
176 | |
177 | return min(source_max, sink_max); | |
178 | } | |
179 | ||
3d65a735 | 180 | int intel_dp_max_lane_count(struct intel_dp *intel_dp) |
540b0b7f JN |
181 | { |
182 | return intel_dp->max_link_lane_count; | |
183 | } | |
184 | ||
22a2c8e0 | 185 | int |
c898261c | 186 | intel_dp_link_required(int pixel_clock, int bpp) |
a4fc5ed6 | 187 | { |
fd81c44e DP |
188 | /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */ |
189 | return DIV_ROUND_UP(pixel_clock * bpp, 8); | |
a4fc5ed6 KP |
190 | } |
191 | ||
22a2c8e0 | 192 | int |
fe27d53e DA |
193 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) |
194 | { | |
fd81c44e DP |
195 | /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the |
196 | * link rate that is generally expressed in Gbps. Since, 8 bits of data | |
197 | * is transmitted every LS_Clk per lane, there is no need to account for | |
198 | * the channel encoding that is done in the PHY layer here. | |
199 | */ | |
200 | ||
201 | return max_link_clock * max_lanes; | |
fe27d53e DA |
202 | } |
203 | ||
70ec0645 MK |
204 | static int |
205 | intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp) | |
206 | { | |
207 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
208 | struct intel_encoder *encoder = &intel_dig_port->base; | |
209 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
210 | int max_dotclk = dev_priv->max_dotclk_freq; | |
211 | int ds_max_dotclk; | |
212 | ||
213 | int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; | |
214 | ||
215 | if (type != DP_DS_PORT_TYPE_VGA) | |
216 | return max_dotclk; | |
217 | ||
218 | ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd, | |
219 | intel_dp->downstream_ports); | |
220 | ||
221 | if (ds_max_dotclk != 0) | |
222 | max_dotclk = min(max_dotclk, ds_max_dotclk); | |
223 | ||
224 | return max_dotclk; | |
225 | } | |
226 | ||
55cfc580 JN |
227 | static void |
228 | intel_dp_set_source_rates(struct intel_dp *intel_dp) | |
40dba341 NM |
229 | { |
230 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
231 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); | |
55cfc580 | 232 | const int *source_rates; |
40dba341 NM |
233 | int size; |
234 | ||
55cfc580 JN |
235 | /* This should only be done once */ |
236 | WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates); | |
237 | ||
cc3f90f0 | 238 | if (IS_GEN9_LP(dev_priv)) { |
55cfc580 | 239 | source_rates = bxt_rates; |
40dba341 | 240 | size = ARRAY_SIZE(bxt_rates); |
b976dc53 | 241 | } else if (IS_GEN9_BC(dev_priv)) { |
55cfc580 | 242 | source_rates = skl_rates; |
40dba341 NM |
243 | size = ARRAY_SIZE(skl_rates); |
244 | } else { | |
55cfc580 | 245 | source_rates = default_rates; |
40dba341 NM |
246 | size = ARRAY_SIZE(default_rates); |
247 | } | |
248 | ||
249 | /* This depends on the fact that 5.4 is last value in the array */ | |
250 | if (!intel_dp_source_supports_hbr2(intel_dp)) | |
251 | size--; | |
252 | ||
55cfc580 JN |
253 | intel_dp->source_rates = source_rates; |
254 | intel_dp->num_source_rates = size; | |
40dba341 NM |
255 | } |
256 | ||
257 | static int intersect_rates(const int *source_rates, int source_len, | |
258 | const int *sink_rates, int sink_len, | |
259 | int *common_rates) | |
260 | { | |
261 | int i = 0, j = 0, k = 0; | |
262 | ||
263 | while (i < source_len && j < sink_len) { | |
264 | if (source_rates[i] == sink_rates[j]) { | |
265 | if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES)) | |
266 | return k; | |
267 | common_rates[k] = source_rates[i]; | |
268 | ++k; | |
269 | ++i; | |
270 | ++j; | |
271 | } else if (source_rates[i] < sink_rates[j]) { | |
272 | ++i; | |
273 | } else { | |
274 | ++j; | |
275 | } | |
276 | } | |
277 | return k; | |
278 | } | |
279 | ||
8001b754 JN |
280 | /* return index of rate in rates array, or -1 if not found */ |
281 | static int intel_dp_rate_index(const int *rates, int len, int rate) | |
282 | { | |
283 | int i; | |
284 | ||
285 | for (i = 0; i < len; i++) | |
286 | if (rate == rates[i]) | |
287 | return i; | |
288 | ||
289 | return -1; | |
290 | } | |
291 | ||
975ee5fc | 292 | static void intel_dp_set_common_rates(struct intel_dp *intel_dp) |
40dba341 | 293 | { |
975ee5fc | 294 | WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates); |
40dba341 | 295 | |
975ee5fc JN |
296 | intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates, |
297 | intel_dp->num_source_rates, | |
298 | intel_dp->sink_rates, | |
299 | intel_dp->num_sink_rates, | |
300 | intel_dp->common_rates); | |
301 | ||
302 | /* Paranoia, there should always be something in common. */ | |
303 | if (WARN_ON(intel_dp->num_common_rates == 0)) { | |
304 | intel_dp->common_rates[0] = default_rates[0]; | |
305 | intel_dp->num_common_rates = 1; | |
306 | } | |
307 | } | |
308 | ||
309 | /* get length of common rates potentially limited by max_rate */ | |
310 | static int intel_dp_common_len_rate_limit(struct intel_dp *intel_dp, | |
311 | int max_rate) | |
312 | { | |
313 | const int *common_rates = intel_dp->common_rates; | |
314 | int i, common_len = intel_dp->num_common_rates; | |
68f357cb JN |
315 | |
316 | /* Limit results by potentially reduced max rate */ | |
317 | for (i = 0; i < common_len; i++) { | |
318 | if (common_rates[common_len - i - 1] <= max_rate) | |
319 | return common_len - i; | |
320 | } | |
40dba341 | 321 | |
68f357cb | 322 | return 0; |
40dba341 NM |
323 | } |
324 | ||
14c562c0 MN |
325 | static bool intel_dp_link_params_valid(struct intel_dp *intel_dp) |
326 | { | |
327 | /* | |
328 | * FIXME: we need to synchronize the current link parameters with | |
329 | * hardware readout. Currently fast link training doesn't work on | |
330 | * boot-up. | |
331 | */ | |
332 | if (intel_dp->link_rate == 0 || | |
333 | intel_dp->link_rate > intel_dp->max_link_rate) | |
334 | return false; | |
335 | ||
336 | if (intel_dp->lane_count == 0 || | |
337 | intel_dp->lane_count > intel_dp_max_lane_count(intel_dp)) | |
338 | return false; | |
339 | ||
340 | return true; | |
341 | } | |
342 | ||
fdb14d33 MN |
343 | int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, |
344 | int link_rate, uint8_t lane_count) | |
345 | { | |
b1810a74 | 346 | int index; |
fdb14d33 | 347 | |
b1810a74 JN |
348 | index = intel_dp_rate_index(intel_dp->common_rates, |
349 | intel_dp->num_common_rates, | |
350 | link_rate); | |
351 | if (index > 0) { | |
e6c0c64a JN |
352 | intel_dp->max_link_rate = intel_dp->common_rates[index - 1]; |
353 | intel_dp->max_link_lane_count = lane_count; | |
fdb14d33 | 354 | } else if (lane_count > 1) { |
540b0b7f | 355 | intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); |
e6c0c64a | 356 | intel_dp->max_link_lane_count = lane_count >> 1; |
fdb14d33 MN |
357 | } else { |
358 | DRM_ERROR("Link Training Unsuccessful\n"); | |
359 | return -1; | |
360 | } | |
361 | ||
362 | return 0; | |
363 | } | |
364 | ||
c19de8eb | 365 | static enum drm_mode_status |
a4fc5ed6 KP |
366 | intel_dp_mode_valid(struct drm_connector *connector, |
367 | struct drm_display_mode *mode) | |
368 | { | |
df0e9248 | 369 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
dd06f90e JN |
370 | struct intel_connector *intel_connector = to_intel_connector(connector); |
371 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
36008365 DV |
372 | int target_clock = mode->clock; |
373 | int max_rate, mode_rate, max_lanes, max_link_clock; | |
70ec0645 MK |
374 | int max_dotclk; |
375 | ||
376 | max_dotclk = intel_dp_downstream_max_dotclock(intel_dp); | |
a4fc5ed6 | 377 | |
01a7507f | 378 | if (intel_dp_is_edp(intel_dp) && fixed_mode) { |
dd06f90e | 379 | if (mode->hdisplay > fixed_mode->hdisplay) |
7de56f43 ZY |
380 | return MODE_PANEL; |
381 | ||
dd06f90e | 382 | if (mode->vdisplay > fixed_mode->vdisplay) |
7de56f43 | 383 | return MODE_PANEL; |
03afc4a2 DV |
384 | |
385 | target_clock = fixed_mode->clock; | |
7de56f43 ZY |
386 | } |
387 | ||
50fec21a | 388 | max_link_clock = intel_dp_max_link_rate(intel_dp); |
eeb6324d | 389 | max_lanes = intel_dp_max_lane_count(intel_dp); |
36008365 DV |
390 | |
391 | max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); | |
392 | mode_rate = intel_dp_link_required(target_clock, 18); | |
393 | ||
799487f5 | 394 | if (mode_rate > max_rate || target_clock > max_dotclk) |
c4867936 | 395 | return MODE_CLOCK_HIGH; |
a4fc5ed6 KP |
396 | |
397 | if (mode->clock < 10000) | |
398 | return MODE_CLOCK_LOW; | |
399 | ||
0af78a2b DV |
400 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
401 | return MODE_H_ILLEGAL; | |
402 | ||
a4fc5ed6 KP |
403 | return MODE_OK; |
404 | } | |
405 | ||
a4f1289e | 406 | uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes) |
a4fc5ed6 KP |
407 | { |
408 | int i; | |
409 | uint32_t v = 0; | |
410 | ||
411 | if (src_bytes > 4) | |
412 | src_bytes = 4; | |
413 | for (i = 0; i < src_bytes; i++) | |
414 | v |= ((uint32_t) src[i]) << ((3-i) * 8); | |
415 | return v; | |
416 | } | |
417 | ||
c2af70e2 | 418 | static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) |
a4fc5ed6 KP |
419 | { |
420 | int i; | |
421 | if (dst_bytes > 4) | |
422 | dst_bytes = 4; | |
423 | for (i = 0; i < dst_bytes; i++) | |
424 | dst[i] = src >> ((3-i) * 8); | |
425 | } | |
426 | ||
bf13e81b JN |
427 | static void |
428 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, | |
36b5f425 | 429 | struct intel_dp *intel_dp); |
bf13e81b JN |
430 | static void |
431 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, | |
5d5ab2d2 VS |
432 | struct intel_dp *intel_dp, |
433 | bool force_disable_vdd); | |
335f752b ID |
434 | static void |
435 | intel_dp_pps_init(struct drm_device *dev, struct intel_dp *intel_dp); | |
bf13e81b | 436 | |
773538e8 VS |
437 | static void pps_lock(struct intel_dp *intel_dp) |
438 | { | |
439 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
440 | struct intel_encoder *encoder = &intel_dig_port->base; | |
441 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 442 | struct drm_i915_private *dev_priv = to_i915(dev); |
773538e8 VS |
443 | |
444 | /* | |
445 | * See vlv_power_sequencer_reset() why we need | |
446 | * a power domain reference here. | |
447 | */ | |
5432fcaf | 448 | intel_display_power_get(dev_priv, intel_dp->aux_power_domain); |
773538e8 VS |
449 | |
450 | mutex_lock(&dev_priv->pps_mutex); | |
451 | } | |
452 | ||
453 | static void pps_unlock(struct intel_dp *intel_dp) | |
454 | { | |
455 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
456 | struct intel_encoder *encoder = &intel_dig_port->base; | |
457 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 458 | struct drm_i915_private *dev_priv = to_i915(dev); |
773538e8 VS |
459 | |
460 | mutex_unlock(&dev_priv->pps_mutex); | |
461 | ||
5432fcaf | 462 | intel_display_power_put(dev_priv, intel_dp->aux_power_domain); |
773538e8 VS |
463 | } |
464 | ||
961a0db0 VS |
465 | static void |
466 | vlv_power_sequencer_kick(struct intel_dp *intel_dp) | |
467 | { | |
468 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
30ad9814 | 469 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
961a0db0 | 470 | enum pipe pipe = intel_dp->pps_pipe; |
0047eedc VS |
471 | bool pll_enabled, release_cl_override = false; |
472 | enum dpio_phy phy = DPIO_PHY(pipe); | |
473 | enum dpio_channel ch = vlv_pipe_to_channel(pipe); | |
961a0db0 VS |
474 | uint32_t DP; |
475 | ||
476 | if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN, | |
477 | "skipping pipe %c power seqeuncer kick due to port %c being active\n", | |
478 | pipe_name(pipe), port_name(intel_dig_port->port))) | |
479 | return; | |
480 | ||
481 | DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n", | |
482 | pipe_name(pipe), port_name(intel_dig_port->port)); | |
483 | ||
484 | /* Preserve the BIOS-computed detected bit. This is | |
485 | * supposed to be read-only. | |
486 | */ | |
487 | DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; | |
488 | DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; | |
489 | DP |= DP_PORT_WIDTH(1); | |
490 | DP |= DP_LINK_TRAIN_PAT_1; | |
491 | ||
920a14b2 | 492 | if (IS_CHERRYVIEW(dev_priv)) |
961a0db0 VS |
493 | DP |= DP_PIPE_SELECT_CHV(pipe); |
494 | else if (pipe == PIPE_B) | |
495 | DP |= DP_PIPEB_SELECT; | |
496 | ||
d288f65f VS |
497 | pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE; |
498 | ||
499 | /* | |
500 | * The DPLL for the pipe must be enabled for this to work. | |
501 | * So enable temporarily it if it's not already enabled. | |
502 | */ | |
0047eedc | 503 | if (!pll_enabled) { |
920a14b2 | 504 | release_cl_override = IS_CHERRYVIEW(dev_priv) && |
0047eedc VS |
505 | !chv_phy_powergate_ch(dev_priv, phy, ch, true); |
506 | ||
30ad9814 | 507 | if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ? |
3f36b937 TU |
508 | &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) { |
509 | DRM_ERROR("Failed to force on pll for pipe %c!\n", | |
510 | pipe_name(pipe)); | |
511 | return; | |
512 | } | |
0047eedc | 513 | } |
d288f65f | 514 | |
961a0db0 VS |
515 | /* |
516 | * Similar magic as in intel_dp_enable_port(). | |
517 | * We _must_ do this port enable + disable trick | |
518 | * to make this power seqeuencer lock onto the port. | |
519 | * Otherwise even VDD force bit won't work. | |
520 | */ | |
521 | I915_WRITE(intel_dp->output_reg, DP); | |
522 | POSTING_READ(intel_dp->output_reg); | |
523 | ||
524 | I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN); | |
525 | POSTING_READ(intel_dp->output_reg); | |
526 | ||
527 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); | |
528 | POSTING_READ(intel_dp->output_reg); | |
d288f65f | 529 | |
0047eedc | 530 | if (!pll_enabled) { |
30ad9814 | 531 | vlv_force_pll_off(dev_priv, pipe); |
0047eedc VS |
532 | |
533 | if (release_cl_override) | |
534 | chv_phy_powergate_ch(dev_priv, phy, ch, false); | |
535 | } | |
961a0db0 VS |
536 | } |
537 | ||
9f2bdb00 VS |
538 | static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv) |
539 | { | |
540 | struct intel_encoder *encoder; | |
541 | unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); | |
542 | ||
543 | /* | |
544 | * We don't have power sequencer currently. | |
545 | * Pick one that's not used by other ports. | |
546 | */ | |
547 | for_each_intel_encoder(&dev_priv->drm, encoder) { | |
548 | struct intel_dp *intel_dp; | |
549 | ||
550 | if (encoder->type != INTEL_OUTPUT_DP && | |
551 | encoder->type != INTEL_OUTPUT_EDP) | |
552 | continue; | |
553 | ||
554 | intel_dp = enc_to_intel_dp(&encoder->base); | |
555 | ||
556 | if (encoder->type == INTEL_OUTPUT_EDP) { | |
557 | WARN_ON(intel_dp->active_pipe != INVALID_PIPE && | |
558 | intel_dp->active_pipe != intel_dp->pps_pipe); | |
559 | ||
560 | if (intel_dp->pps_pipe != INVALID_PIPE) | |
561 | pipes &= ~(1 << intel_dp->pps_pipe); | |
562 | } else { | |
563 | WARN_ON(intel_dp->pps_pipe != INVALID_PIPE); | |
564 | ||
565 | if (intel_dp->active_pipe != INVALID_PIPE) | |
566 | pipes &= ~(1 << intel_dp->active_pipe); | |
567 | } | |
568 | } | |
569 | ||
570 | if (pipes == 0) | |
571 | return INVALID_PIPE; | |
572 | ||
573 | return ffs(pipes) - 1; | |
574 | } | |
575 | ||
bf13e81b JN |
576 | static enum pipe |
577 | vlv_power_sequencer_pipe(struct intel_dp *intel_dp) | |
578 | { | |
579 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
bf13e81b | 580 | struct drm_device *dev = intel_dig_port->base.base.dev; |
fac5e23e | 581 | struct drm_i915_private *dev_priv = to_i915(dev); |
a8c3344e | 582 | enum pipe pipe; |
bf13e81b | 583 | |
e39b999a | 584 | lockdep_assert_held(&dev_priv->pps_mutex); |
bf13e81b | 585 | |
a8c3344e | 586 | /* We should never land here with regular DP ports */ |
01a7507f | 587 | WARN_ON(!intel_dp_is_edp(intel_dp)); |
a8c3344e | 588 | |
9f2bdb00 VS |
589 | WARN_ON(intel_dp->active_pipe != INVALID_PIPE && |
590 | intel_dp->active_pipe != intel_dp->pps_pipe); | |
591 | ||
a4a5d2f8 VS |
592 | if (intel_dp->pps_pipe != INVALID_PIPE) |
593 | return intel_dp->pps_pipe; | |
594 | ||
9f2bdb00 | 595 | pipe = vlv_find_free_pps(dev_priv); |
a4a5d2f8 VS |
596 | |
597 | /* | |
598 | * Didn't find one. This should not happen since there | |
599 | * are two power sequencers and up to two eDP ports. | |
600 | */ | |
9f2bdb00 | 601 | if (WARN_ON(pipe == INVALID_PIPE)) |
a8c3344e | 602 | pipe = PIPE_A; |
a4a5d2f8 | 603 | |
a8c3344e VS |
604 | vlv_steal_power_sequencer(dev, pipe); |
605 | intel_dp->pps_pipe = pipe; | |
a4a5d2f8 VS |
606 | |
607 | DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n", | |
608 | pipe_name(intel_dp->pps_pipe), | |
609 | port_name(intel_dig_port->port)); | |
610 | ||
611 | /* init power sequencer on this pipe and port */ | |
36b5f425 | 612 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
5d5ab2d2 | 613 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, true); |
a4a5d2f8 | 614 | |
961a0db0 VS |
615 | /* |
616 | * Even vdd force doesn't work until we've made | |
617 | * the power sequencer lock in on the port. | |
618 | */ | |
619 | vlv_power_sequencer_kick(intel_dp); | |
a4a5d2f8 VS |
620 | |
621 | return intel_dp->pps_pipe; | |
622 | } | |
623 | ||
78597996 ID |
624 | static int |
625 | bxt_power_sequencer_idx(struct intel_dp *intel_dp) | |
626 | { | |
627 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
628 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 629 | struct drm_i915_private *dev_priv = to_i915(dev); |
78597996 ID |
630 | |
631 | lockdep_assert_held(&dev_priv->pps_mutex); | |
632 | ||
633 | /* We should never land here with regular DP ports */ | |
01a7507f | 634 | WARN_ON(!intel_dp_is_edp(intel_dp)); |
78597996 ID |
635 | |
636 | /* | |
637 | * TODO: BXT has 2 PPS instances. The correct port->PPS instance | |
638 | * mapping needs to be retrieved from VBT, for now just hard-code to | |
639 | * use instance #0 always. | |
640 | */ | |
641 | if (!intel_dp->pps_reset) | |
642 | return 0; | |
643 | ||
644 | intel_dp->pps_reset = false; | |
645 | ||
646 | /* | |
647 | * Only the HW needs to be reprogrammed, the SW state is fixed and | |
648 | * has been setup during connector init. | |
649 | */ | |
5d5ab2d2 | 650 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false); |
78597996 ID |
651 | |
652 | return 0; | |
653 | } | |
654 | ||
6491ab27 VS |
655 | typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv, |
656 | enum pipe pipe); | |
657 | ||
658 | static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv, | |
659 | enum pipe pipe) | |
660 | { | |
44cb734c | 661 | return I915_READ(PP_STATUS(pipe)) & PP_ON; |
6491ab27 VS |
662 | } |
663 | ||
664 | static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv, | |
665 | enum pipe pipe) | |
666 | { | |
44cb734c | 667 | return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD; |
6491ab27 VS |
668 | } |
669 | ||
670 | static bool vlv_pipe_any(struct drm_i915_private *dev_priv, | |
671 | enum pipe pipe) | |
672 | { | |
673 | return true; | |
674 | } | |
bf13e81b | 675 | |
a4a5d2f8 | 676 | static enum pipe |
6491ab27 VS |
677 | vlv_initial_pps_pipe(struct drm_i915_private *dev_priv, |
678 | enum port port, | |
679 | vlv_pipe_check pipe_check) | |
a4a5d2f8 VS |
680 | { |
681 | enum pipe pipe; | |
bf13e81b | 682 | |
bf13e81b | 683 | for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { |
44cb734c | 684 | u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) & |
bf13e81b | 685 | PANEL_PORT_SELECT_MASK; |
a4a5d2f8 VS |
686 | |
687 | if (port_sel != PANEL_PORT_SELECT_VLV(port)) | |
688 | continue; | |
689 | ||
6491ab27 VS |
690 | if (!pipe_check(dev_priv, pipe)) |
691 | continue; | |
692 | ||
a4a5d2f8 | 693 | return pipe; |
bf13e81b JN |
694 | } |
695 | ||
a4a5d2f8 VS |
696 | return INVALID_PIPE; |
697 | } | |
698 | ||
699 | static void | |
700 | vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp) | |
701 | { | |
702 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
703 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 704 | struct drm_i915_private *dev_priv = to_i915(dev); |
a4a5d2f8 VS |
705 | enum port port = intel_dig_port->port; |
706 | ||
707 | lockdep_assert_held(&dev_priv->pps_mutex); | |
708 | ||
709 | /* try to find a pipe with this port selected */ | |
6491ab27 VS |
710 | /* first pick one where the panel is on */ |
711 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, | |
712 | vlv_pipe_has_pp_on); | |
713 | /* didn't find one? pick one where vdd is on */ | |
714 | if (intel_dp->pps_pipe == INVALID_PIPE) | |
715 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, | |
716 | vlv_pipe_has_vdd_on); | |
717 | /* didn't find one? pick one with just the correct port */ | |
718 | if (intel_dp->pps_pipe == INVALID_PIPE) | |
719 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, | |
720 | vlv_pipe_any); | |
a4a5d2f8 VS |
721 | |
722 | /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */ | |
723 | if (intel_dp->pps_pipe == INVALID_PIPE) { | |
724 | DRM_DEBUG_KMS("no initial power sequencer for port %c\n", | |
725 | port_name(port)); | |
726 | return; | |
bf13e81b JN |
727 | } |
728 | ||
a4a5d2f8 VS |
729 | DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n", |
730 | port_name(port), pipe_name(intel_dp->pps_pipe)); | |
731 | ||
36b5f425 | 732 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
5d5ab2d2 | 733 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false); |
bf13e81b JN |
734 | } |
735 | ||
78597996 | 736 | void intel_power_sequencer_reset(struct drm_i915_private *dev_priv) |
773538e8 | 737 | { |
91c8a326 | 738 | struct drm_device *dev = &dev_priv->drm; |
773538e8 VS |
739 | struct intel_encoder *encoder; |
740 | ||
920a14b2 | 741 | if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && |
cc3f90f0 | 742 | !IS_GEN9_LP(dev_priv))) |
773538e8 VS |
743 | return; |
744 | ||
745 | /* | |
746 | * We can't grab pps_mutex here due to deadlock with power_domain | |
747 | * mutex when power_domain functions are called while holding pps_mutex. | |
748 | * That also means that in order to use pps_pipe the code needs to | |
749 | * hold both a power domain reference and pps_mutex, and the power domain | |
750 | * reference get/put must be done while _not_ holding pps_mutex. | |
751 | * pps_{lock,unlock}() do these steps in the correct order, so one | |
752 | * should use them always. | |
753 | */ | |
754 | ||
19c8054c | 755 | for_each_intel_encoder(dev, encoder) { |
773538e8 VS |
756 | struct intel_dp *intel_dp; |
757 | ||
9f2bdb00 VS |
758 | if (encoder->type != INTEL_OUTPUT_DP && |
759 | encoder->type != INTEL_OUTPUT_EDP) | |
773538e8 VS |
760 | continue; |
761 | ||
762 | intel_dp = enc_to_intel_dp(&encoder->base); | |
9f2bdb00 VS |
763 | |
764 | WARN_ON(intel_dp->active_pipe != INVALID_PIPE); | |
765 | ||
766 | if (encoder->type != INTEL_OUTPUT_EDP) | |
767 | continue; | |
768 | ||
cc3f90f0 | 769 | if (IS_GEN9_LP(dev_priv)) |
78597996 ID |
770 | intel_dp->pps_reset = true; |
771 | else | |
772 | intel_dp->pps_pipe = INVALID_PIPE; | |
773538e8 | 773 | } |
bf13e81b JN |
774 | } |
775 | ||
8e8232d5 ID |
776 | struct pps_registers { |
777 | i915_reg_t pp_ctrl; | |
778 | i915_reg_t pp_stat; | |
779 | i915_reg_t pp_on; | |
780 | i915_reg_t pp_off; | |
781 | i915_reg_t pp_div; | |
782 | }; | |
783 | ||
784 | static void intel_pps_get_registers(struct drm_i915_private *dev_priv, | |
785 | struct intel_dp *intel_dp, | |
786 | struct pps_registers *regs) | |
787 | { | |
44cb734c ID |
788 | int pps_idx = 0; |
789 | ||
8e8232d5 ID |
790 | memset(regs, 0, sizeof(*regs)); |
791 | ||
cc3f90f0 | 792 | if (IS_GEN9_LP(dev_priv)) |
44cb734c ID |
793 | pps_idx = bxt_power_sequencer_idx(intel_dp); |
794 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
795 | pps_idx = vlv_power_sequencer_pipe(intel_dp); | |
8e8232d5 | 796 | |
44cb734c ID |
797 | regs->pp_ctrl = PP_CONTROL(pps_idx); |
798 | regs->pp_stat = PP_STATUS(pps_idx); | |
799 | regs->pp_on = PP_ON_DELAYS(pps_idx); | |
800 | regs->pp_off = PP_OFF_DELAYS(pps_idx); | |
938361e7 | 801 | if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv)) |
44cb734c | 802 | regs->pp_div = PP_DIVISOR(pps_idx); |
8e8232d5 ID |
803 | } |
804 | ||
f0f59a00 VS |
805 | static i915_reg_t |
806 | _pp_ctrl_reg(struct intel_dp *intel_dp) | |
bf13e81b | 807 | { |
8e8232d5 | 808 | struct pps_registers regs; |
bf13e81b | 809 | |
8e8232d5 ID |
810 | intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp, |
811 | ®s); | |
812 | ||
813 | return regs.pp_ctrl; | |
bf13e81b JN |
814 | } |
815 | ||
f0f59a00 VS |
816 | static i915_reg_t |
817 | _pp_stat_reg(struct intel_dp *intel_dp) | |
bf13e81b | 818 | { |
8e8232d5 | 819 | struct pps_registers regs; |
bf13e81b | 820 | |
8e8232d5 ID |
821 | intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp, |
822 | ®s); | |
823 | ||
824 | return regs.pp_stat; | |
bf13e81b JN |
825 | } |
826 | ||
01527b31 CT |
827 | /* Reboot notifier handler to shutdown panel power to guarantee T12 timing |
828 | This function only applicable when panel PM state is not to be tracked */ | |
829 | static int edp_notify_handler(struct notifier_block *this, unsigned long code, | |
830 | void *unused) | |
831 | { | |
832 | struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp), | |
833 | edp_notifier); | |
834 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
fac5e23e | 835 | struct drm_i915_private *dev_priv = to_i915(dev); |
01527b31 | 836 | |
01a7507f | 837 | if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART) |
01527b31 CT |
838 | return 0; |
839 | ||
773538e8 | 840 | pps_lock(intel_dp); |
e39b999a | 841 | |
920a14b2 | 842 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
e39b999a | 843 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
f0f59a00 | 844 | i915_reg_t pp_ctrl_reg, pp_div_reg; |
649636ef | 845 | u32 pp_div; |
e39b999a | 846 | |
44cb734c ID |
847 | pp_ctrl_reg = PP_CONTROL(pipe); |
848 | pp_div_reg = PP_DIVISOR(pipe); | |
01527b31 CT |
849 | pp_div = I915_READ(pp_div_reg); |
850 | pp_div &= PP_REFERENCE_DIVIDER_MASK; | |
851 | ||
852 | /* 0x1F write to PP_DIV_REG sets max cycle delay */ | |
853 | I915_WRITE(pp_div_reg, pp_div | 0x1F); | |
854 | I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); | |
855 | msleep(intel_dp->panel_power_cycle_delay); | |
856 | } | |
857 | ||
773538e8 | 858 | pps_unlock(intel_dp); |
e39b999a | 859 | |
01527b31 CT |
860 | return 0; |
861 | } | |
862 | ||
4be73780 | 863 | static bool edp_have_panel_power(struct intel_dp *intel_dp) |
ebf33b18 | 864 | { |
30add22d | 865 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 866 | struct drm_i915_private *dev_priv = to_i915(dev); |
ebf33b18 | 867 | |
e39b999a VS |
868 | lockdep_assert_held(&dev_priv->pps_mutex); |
869 | ||
920a14b2 | 870 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
9a42356b VS |
871 | intel_dp->pps_pipe == INVALID_PIPE) |
872 | return false; | |
873 | ||
bf13e81b | 874 | return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; |
ebf33b18 KP |
875 | } |
876 | ||
4be73780 | 877 | static bool edp_have_panel_vdd(struct intel_dp *intel_dp) |
ebf33b18 | 878 | { |
30add22d | 879 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 880 | struct drm_i915_private *dev_priv = to_i915(dev); |
ebf33b18 | 881 | |
e39b999a VS |
882 | lockdep_assert_held(&dev_priv->pps_mutex); |
883 | ||
920a14b2 | 884 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
9a42356b VS |
885 | intel_dp->pps_pipe == INVALID_PIPE) |
886 | return false; | |
887 | ||
773538e8 | 888 | return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD; |
ebf33b18 KP |
889 | } |
890 | ||
9b984dae KP |
891 | static void |
892 | intel_dp_check_edp(struct intel_dp *intel_dp) | |
893 | { | |
30add22d | 894 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 895 | struct drm_i915_private *dev_priv = to_i915(dev); |
ebf33b18 | 896 | |
01a7507f | 897 | if (!intel_dp_is_edp(intel_dp)) |
9b984dae | 898 | return; |
453c5420 | 899 | |
4be73780 | 900 | if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { |
9b984dae KP |
901 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); |
902 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", | |
bf13e81b JN |
903 | I915_READ(_pp_stat_reg(intel_dp)), |
904 | I915_READ(_pp_ctrl_reg(intel_dp))); | |
9b984dae KP |
905 | } |
906 | } | |
907 | ||
9ee32fea DV |
908 | static uint32_t |
909 | intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) | |
910 | { | |
911 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
912 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 913 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 914 | i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
9ee32fea DV |
915 | uint32_t status; |
916 | bool done; | |
917 | ||
ef04f00d | 918 | #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
9ee32fea | 919 | if (has_aux_irq) |
b18ac466 | 920 | done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, |
3598706b | 921 | msecs_to_jiffies_timeout(10)); |
9ee32fea | 922 | else |
713a6b66 | 923 | done = wait_for(C, 10) == 0; |
9ee32fea DV |
924 | if (!done) |
925 | DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", | |
926 | has_aux_irq); | |
927 | #undef C | |
928 | ||
929 | return status; | |
930 | } | |
931 | ||
6ffb1be7 | 932 | static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
a4fc5ed6 | 933 | { |
174edf1f | 934 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
e7dc33f3 | 935 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
9ee32fea | 936 | |
a457f54b VS |
937 | if (index) |
938 | return 0; | |
939 | ||
ec5b01dd DL |
940 | /* |
941 | * The clock divider is based off the hrawclk, and would like to run at | |
a457f54b | 942 | * 2MHz. So, take the hrawclk value and divide by 2000 and use that |
a4fc5ed6 | 943 | */ |
a457f54b | 944 | return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000); |
ec5b01dd DL |
945 | } |
946 | ||
947 | static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) | |
948 | { | |
949 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
a457f54b | 950 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
ec5b01dd DL |
951 | |
952 | if (index) | |
953 | return 0; | |
954 | ||
a457f54b VS |
955 | /* |
956 | * The clock divider is based off the cdclk or PCH rawclk, and would | |
957 | * like to run at 2MHz. So, take the cdclk or PCH rawclk value and | |
958 | * divide by 2000 and use that | |
959 | */ | |
e7dc33f3 | 960 | if (intel_dig_port->port == PORT_A) |
49cd97a3 | 961 | return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000); |
e7dc33f3 VS |
962 | else |
963 | return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000); | |
ec5b01dd DL |
964 | } |
965 | ||
966 | static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) | |
967 | { | |
968 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
a457f54b | 969 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
ec5b01dd | 970 | |
a457f54b | 971 | if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) { |
2c55c336 | 972 | /* Workaround for non-ULT HSW */ |
bc86625a CW |
973 | switch (index) { |
974 | case 0: return 63; | |
975 | case 1: return 72; | |
976 | default: return 0; | |
977 | } | |
2c55c336 | 978 | } |
a457f54b VS |
979 | |
980 | return ilk_get_aux_clock_divider(intel_dp, index); | |
b84a1cf8 RV |
981 | } |
982 | ||
b6b5e383 DL |
983 | static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
984 | { | |
985 | /* | |
986 | * SKL doesn't need us to program the AUX clock divider (Hardware will | |
987 | * derive the clock from CDCLK automatically). We still implement the | |
988 | * get_aux_clock_divider vfunc to plug-in into the existing code. | |
989 | */ | |
990 | return index ? 0 : 1; | |
991 | } | |
992 | ||
6ffb1be7 VS |
993 | static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp, |
994 | bool has_aux_irq, | |
995 | int send_bytes, | |
996 | uint32_t aux_clock_divider) | |
5ed12a19 DL |
997 | { |
998 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
8652744b TU |
999 | struct drm_i915_private *dev_priv = |
1000 | to_i915(intel_dig_port->base.base.dev); | |
5ed12a19 DL |
1001 | uint32_t precharge, timeout; |
1002 | ||
8652744b | 1003 | if (IS_GEN6(dev_priv)) |
5ed12a19 DL |
1004 | precharge = 3; |
1005 | else | |
1006 | precharge = 5; | |
1007 | ||
8652744b | 1008 | if (IS_BROADWELL(dev_priv) && intel_dig_port->port == PORT_A) |
5ed12a19 DL |
1009 | timeout = DP_AUX_CH_CTL_TIME_OUT_600us; |
1010 | else | |
1011 | timeout = DP_AUX_CH_CTL_TIME_OUT_400us; | |
1012 | ||
1013 | return DP_AUX_CH_CTL_SEND_BUSY | | |
788d4433 | 1014 | DP_AUX_CH_CTL_DONE | |
5ed12a19 | 1015 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | |
788d4433 | 1016 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
5ed12a19 | 1017 | timeout | |
788d4433 | 1018 | DP_AUX_CH_CTL_RECEIVE_ERROR | |
5ed12a19 DL |
1019 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
1020 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | | |
788d4433 | 1021 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); |
5ed12a19 DL |
1022 | } |
1023 | ||
b9ca5fad DL |
1024 | static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp, |
1025 | bool has_aux_irq, | |
1026 | int send_bytes, | |
1027 | uint32_t unused) | |
1028 | { | |
1029 | return DP_AUX_CH_CTL_SEND_BUSY | | |
1030 | DP_AUX_CH_CTL_DONE | | |
1031 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | | |
1032 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
1033 | DP_AUX_CH_CTL_TIME_OUT_1600us | | |
1034 | DP_AUX_CH_CTL_RECEIVE_ERROR | | |
1035 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | | |
d4dcbdce | 1036 | DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) | |
b9ca5fad DL |
1037 | DP_AUX_CH_CTL_SYNC_PULSE_SKL(32); |
1038 | } | |
1039 | ||
b84a1cf8 RV |
1040 | static int |
1041 | intel_dp_aux_ch(struct intel_dp *intel_dp, | |
bd9f74a5 | 1042 | const uint8_t *send, int send_bytes, |
b84a1cf8 RV |
1043 | uint8_t *recv, int recv_size) |
1044 | { | |
1045 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
0031fb96 TU |
1046 | struct drm_i915_private *dev_priv = |
1047 | to_i915(intel_dig_port->base.base.dev); | |
f0f59a00 | 1048 | i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
bc86625a | 1049 | uint32_t aux_clock_divider; |
b84a1cf8 RV |
1050 | int i, ret, recv_bytes; |
1051 | uint32_t status; | |
5ed12a19 | 1052 | int try, clock = 0; |
0031fb96 | 1053 | bool has_aux_irq = HAS_AUX_IRQ(dev_priv); |
884f19e9 JN |
1054 | bool vdd; |
1055 | ||
773538e8 | 1056 | pps_lock(intel_dp); |
e39b999a | 1057 | |
72c3500a VS |
1058 | /* |
1059 | * We will be called with VDD already enabled for dpcd/edid/oui reads. | |
1060 | * In such cases we want to leave VDD enabled and it's up to upper layers | |
1061 | * to turn it off. But for eg. i2c-dev access we need to turn it on/off | |
1062 | * ourselves. | |
1063 | */ | |
1e0560e0 | 1064 | vdd = edp_panel_vdd_on(intel_dp); |
b84a1cf8 RV |
1065 | |
1066 | /* dp aux is extremely sensitive to irq latency, hence request the | |
1067 | * lowest possible wakeup latency and so prevent the cpu from going into | |
1068 | * deep sleep states. | |
1069 | */ | |
1070 | pm_qos_update_request(&dev_priv->pm_qos, 0); | |
1071 | ||
1072 | intel_dp_check_edp(intel_dp); | |
5eb08b69 | 1073 | |
11bee43e JB |
1074 | /* Try to wait for any previous AUX channel activity */ |
1075 | for (try = 0; try < 3; try++) { | |
ef04f00d | 1076 | status = I915_READ_NOTRACE(ch_ctl); |
11bee43e JB |
1077 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
1078 | break; | |
1079 | msleep(1); | |
1080 | } | |
1081 | ||
1082 | if (try == 3) { | |
02196c77 MK |
1083 | static u32 last_status = -1; |
1084 | const u32 status = I915_READ(ch_ctl); | |
1085 | ||
1086 | if (status != last_status) { | |
1087 | WARN(1, "dp_aux_ch not started status 0x%08x\n", | |
1088 | status); | |
1089 | last_status = status; | |
1090 | } | |
1091 | ||
9ee32fea DV |
1092 | ret = -EBUSY; |
1093 | goto out; | |
4f7f7b7e CW |
1094 | } |
1095 | ||
46a5ae9f PZ |
1096 | /* Only 5 data registers! */ |
1097 | if (WARN_ON(send_bytes > 20 || recv_size > 20)) { | |
1098 | ret = -E2BIG; | |
1099 | goto out; | |
1100 | } | |
1101 | ||
ec5b01dd | 1102 | while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { |
153b1100 DL |
1103 | u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, |
1104 | has_aux_irq, | |
1105 | send_bytes, | |
1106 | aux_clock_divider); | |
5ed12a19 | 1107 | |
bc86625a CW |
1108 | /* Must try at least 3 times according to DP spec */ |
1109 | for (try = 0; try < 5; try++) { | |
1110 | /* Load the send data into the aux channel data registers */ | |
1111 | for (i = 0; i < send_bytes; i += 4) | |
330e20ec | 1112 | I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2], |
a4f1289e RV |
1113 | intel_dp_pack_aux(send + i, |
1114 | send_bytes - i)); | |
bc86625a CW |
1115 | |
1116 | /* Send the command and wait for it to complete */ | |
5ed12a19 | 1117 | I915_WRITE(ch_ctl, send_ctl); |
bc86625a CW |
1118 | |
1119 | status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); | |
1120 | ||
1121 | /* Clear done status and any errors */ | |
1122 | I915_WRITE(ch_ctl, | |
1123 | status | | |
1124 | DP_AUX_CH_CTL_DONE | | |
1125 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
1126 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
1127 | ||
74ebf294 | 1128 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) |
bc86625a | 1129 | continue; |
74ebf294 TP |
1130 | |
1131 | /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2 | |
1132 | * 400us delay required for errors and timeouts | |
1133 | * Timeout errors from the HW already meet this | |
1134 | * requirement so skip to next iteration | |
1135 | */ | |
1136 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { | |
1137 | usleep_range(400, 500); | |
bc86625a | 1138 | continue; |
74ebf294 | 1139 | } |
bc86625a | 1140 | if (status & DP_AUX_CH_CTL_DONE) |
e058c945 | 1141 | goto done; |
bc86625a | 1142 | } |
a4fc5ed6 KP |
1143 | } |
1144 | ||
a4fc5ed6 | 1145 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
1ae8c0a5 | 1146 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
9ee32fea DV |
1147 | ret = -EBUSY; |
1148 | goto out; | |
a4fc5ed6 KP |
1149 | } |
1150 | ||
e058c945 | 1151 | done: |
a4fc5ed6 KP |
1152 | /* Check for timeout or receive error. |
1153 | * Timeouts occur when the sink is not connected | |
1154 | */ | |
a5b3da54 | 1155 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
1ae8c0a5 | 1156 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
9ee32fea DV |
1157 | ret = -EIO; |
1158 | goto out; | |
a5b3da54 | 1159 | } |
1ae8c0a5 KP |
1160 | |
1161 | /* Timeouts occur when the device isn't connected, so they're | |
1162 | * "normal" -- don't fill the kernel log with these */ | |
a5b3da54 | 1163 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
a5570fe5 | 1164 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
9ee32fea DV |
1165 | ret = -ETIMEDOUT; |
1166 | goto out; | |
a4fc5ed6 KP |
1167 | } |
1168 | ||
1169 | /* Unload any bytes sent back from the other side */ | |
1170 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> | |
1171 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); | |
14e01889 RV |
1172 | |
1173 | /* | |
1174 | * By BSpec: "Message sizes of 0 or >20 are not allowed." | |
1175 | * We have no idea of what happened so we return -EBUSY so | |
1176 | * drm layer takes care for the necessary retries. | |
1177 | */ | |
1178 | if (recv_bytes == 0 || recv_bytes > 20) { | |
1179 | DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n", | |
1180 | recv_bytes); | |
1181 | /* | |
1182 | * FIXME: This patch was created on top of a series that | |
1183 | * organize the retries at drm level. There EBUSY should | |
1184 | * also take care for 1ms wait before retrying. | |
1185 | * That aux retries re-org is still needed and after that is | |
1186 | * merged we remove this sleep from here. | |
1187 | */ | |
1188 | usleep_range(1000, 1500); | |
1189 | ret = -EBUSY; | |
1190 | goto out; | |
1191 | } | |
1192 | ||
a4fc5ed6 KP |
1193 | if (recv_bytes > recv_size) |
1194 | recv_bytes = recv_size; | |
0206e353 | 1195 | |
4f7f7b7e | 1196 | for (i = 0; i < recv_bytes; i += 4) |
330e20ec | 1197 | intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]), |
a4f1289e | 1198 | recv + i, recv_bytes - i); |
a4fc5ed6 | 1199 | |
9ee32fea DV |
1200 | ret = recv_bytes; |
1201 | out: | |
1202 | pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); | |
1203 | ||
884f19e9 JN |
1204 | if (vdd) |
1205 | edp_panel_vdd_off(intel_dp, false); | |
1206 | ||
773538e8 | 1207 | pps_unlock(intel_dp); |
e39b999a | 1208 | |
9ee32fea | 1209 | return ret; |
a4fc5ed6 KP |
1210 | } |
1211 | ||
a6c8aff0 JN |
1212 | #define BARE_ADDRESS_SIZE 3 |
1213 | #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) | |
9d1a1031 JN |
1214 | static ssize_t |
1215 | intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) | |
a4fc5ed6 | 1216 | { |
9d1a1031 JN |
1217 | struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); |
1218 | uint8_t txbuf[20], rxbuf[20]; | |
1219 | size_t txsize, rxsize; | |
a4fc5ed6 | 1220 | int ret; |
a4fc5ed6 | 1221 | |
d2d9cbbd VS |
1222 | txbuf[0] = (msg->request << 4) | |
1223 | ((msg->address >> 16) & 0xf); | |
1224 | txbuf[1] = (msg->address >> 8) & 0xff; | |
9d1a1031 JN |
1225 | txbuf[2] = msg->address & 0xff; |
1226 | txbuf[3] = msg->size - 1; | |
46a5ae9f | 1227 | |
9d1a1031 JN |
1228 | switch (msg->request & ~DP_AUX_I2C_MOT) { |
1229 | case DP_AUX_NATIVE_WRITE: | |
1230 | case DP_AUX_I2C_WRITE: | |
c1e74122 | 1231 | case DP_AUX_I2C_WRITE_STATUS_UPDATE: |
a6c8aff0 | 1232 | txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; |
a1ddefd8 | 1233 | rxsize = 2; /* 0 or 1 data bytes */ |
f51a44b9 | 1234 | |
9d1a1031 JN |
1235 | if (WARN_ON(txsize > 20)) |
1236 | return -E2BIG; | |
a4fc5ed6 | 1237 | |
dd788090 VS |
1238 | WARN_ON(!msg->buffer != !msg->size); |
1239 | ||
d81a67cc ID |
1240 | if (msg->buffer) |
1241 | memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); | |
a4fc5ed6 | 1242 | |
9d1a1031 JN |
1243 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
1244 | if (ret > 0) { | |
1245 | msg->reply = rxbuf[0] >> 4; | |
a4fc5ed6 | 1246 | |
a1ddefd8 JN |
1247 | if (ret > 1) { |
1248 | /* Number of bytes written in a short write. */ | |
1249 | ret = clamp_t(int, rxbuf[1], 0, msg->size); | |
1250 | } else { | |
1251 | /* Return payload size. */ | |
1252 | ret = msg->size; | |
1253 | } | |
9d1a1031 JN |
1254 | } |
1255 | break; | |
46a5ae9f | 1256 | |
9d1a1031 JN |
1257 | case DP_AUX_NATIVE_READ: |
1258 | case DP_AUX_I2C_READ: | |
a6c8aff0 | 1259 | txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; |
9d1a1031 | 1260 | rxsize = msg->size + 1; |
a4fc5ed6 | 1261 | |
9d1a1031 JN |
1262 | if (WARN_ON(rxsize > 20)) |
1263 | return -E2BIG; | |
a4fc5ed6 | 1264 | |
9d1a1031 JN |
1265 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
1266 | if (ret > 0) { | |
1267 | msg->reply = rxbuf[0] >> 4; | |
1268 | /* | |
1269 | * Assume happy day, and copy the data. The caller is | |
1270 | * expected to check msg->reply before touching it. | |
1271 | * | |
1272 | * Return payload size. | |
1273 | */ | |
1274 | ret--; | |
1275 | memcpy(msg->buffer, rxbuf + 1, ret); | |
a4fc5ed6 | 1276 | } |
9d1a1031 JN |
1277 | break; |
1278 | ||
1279 | default: | |
1280 | ret = -EINVAL; | |
1281 | break; | |
a4fc5ed6 | 1282 | } |
f51a44b9 | 1283 | |
9d1a1031 | 1284 | return ret; |
a4fc5ed6 KP |
1285 | } |
1286 | ||
8f7ce038 VS |
1287 | static enum port intel_aux_port(struct drm_i915_private *dev_priv, |
1288 | enum port port) | |
1289 | { | |
1290 | const struct ddi_vbt_port_info *info = | |
1291 | &dev_priv->vbt.ddi_port_info[port]; | |
1292 | enum port aux_port; | |
1293 | ||
1294 | if (!info->alternate_aux_channel) { | |
1295 | DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n", | |
1296 | port_name(port), port_name(port)); | |
1297 | return port; | |
1298 | } | |
1299 | ||
1300 | switch (info->alternate_aux_channel) { | |
1301 | case DP_AUX_A: | |
1302 | aux_port = PORT_A; | |
1303 | break; | |
1304 | case DP_AUX_B: | |
1305 | aux_port = PORT_B; | |
1306 | break; | |
1307 | case DP_AUX_C: | |
1308 | aux_port = PORT_C; | |
1309 | break; | |
1310 | case DP_AUX_D: | |
1311 | aux_port = PORT_D; | |
1312 | break; | |
1313 | default: | |
1314 | MISSING_CASE(info->alternate_aux_channel); | |
1315 | aux_port = PORT_A; | |
1316 | break; | |
1317 | } | |
1318 | ||
1319 | DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n", | |
1320 | port_name(aux_port), port_name(port)); | |
1321 | ||
1322 | return aux_port; | |
1323 | } | |
1324 | ||
f0f59a00 | 1325 | static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv, |
c8a89b08 | 1326 | enum port port) |
da00bdcf VS |
1327 | { |
1328 | switch (port) { | |
1329 | case PORT_B: | |
1330 | case PORT_C: | |
1331 | case PORT_D: | |
1332 | return DP_AUX_CH_CTL(port); | |
1333 | default: | |
1334 | MISSING_CASE(port); | |
1335 | return DP_AUX_CH_CTL(PORT_B); | |
1336 | } | |
1337 | } | |
1338 | ||
f0f59a00 | 1339 | static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv, |
c8a89b08 | 1340 | enum port port, int index) |
330e20ec VS |
1341 | { |
1342 | switch (port) { | |
1343 | case PORT_B: | |
1344 | case PORT_C: | |
1345 | case PORT_D: | |
1346 | return DP_AUX_CH_DATA(port, index); | |
1347 | default: | |
1348 | MISSING_CASE(port); | |
1349 | return DP_AUX_CH_DATA(PORT_B, index); | |
1350 | } | |
1351 | } | |
1352 | ||
f0f59a00 | 1353 | static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv, |
c8a89b08 | 1354 | enum port port) |
da00bdcf VS |
1355 | { |
1356 | switch (port) { | |
1357 | case PORT_A: | |
1358 | return DP_AUX_CH_CTL(port); | |
1359 | case PORT_B: | |
1360 | case PORT_C: | |
1361 | case PORT_D: | |
1362 | return PCH_DP_AUX_CH_CTL(port); | |
1363 | default: | |
1364 | MISSING_CASE(port); | |
1365 | return DP_AUX_CH_CTL(PORT_A); | |
1366 | } | |
1367 | } | |
1368 | ||
f0f59a00 | 1369 | static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv, |
c8a89b08 | 1370 | enum port port, int index) |
330e20ec VS |
1371 | { |
1372 | switch (port) { | |
1373 | case PORT_A: | |
1374 | return DP_AUX_CH_DATA(port, index); | |
1375 | case PORT_B: | |
1376 | case PORT_C: | |
1377 | case PORT_D: | |
1378 | return PCH_DP_AUX_CH_DATA(port, index); | |
1379 | default: | |
1380 | MISSING_CASE(port); | |
1381 | return DP_AUX_CH_DATA(PORT_A, index); | |
1382 | } | |
1383 | } | |
1384 | ||
f0f59a00 | 1385 | static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv, |
c8a89b08 | 1386 | enum port port) |
da00bdcf | 1387 | { |
da00bdcf VS |
1388 | switch (port) { |
1389 | case PORT_A: | |
1390 | case PORT_B: | |
1391 | case PORT_C: | |
1392 | case PORT_D: | |
1393 | return DP_AUX_CH_CTL(port); | |
1394 | default: | |
1395 | MISSING_CASE(port); | |
1396 | return DP_AUX_CH_CTL(PORT_A); | |
1397 | } | |
1398 | } | |
1399 | ||
f0f59a00 | 1400 | static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv, |
c8a89b08 | 1401 | enum port port, int index) |
330e20ec | 1402 | { |
330e20ec VS |
1403 | switch (port) { |
1404 | case PORT_A: | |
1405 | case PORT_B: | |
1406 | case PORT_C: | |
1407 | case PORT_D: | |
1408 | return DP_AUX_CH_DATA(port, index); | |
1409 | default: | |
1410 | MISSING_CASE(port); | |
1411 | return DP_AUX_CH_DATA(PORT_A, index); | |
1412 | } | |
1413 | } | |
1414 | ||
f0f59a00 | 1415 | static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv, |
c8a89b08 | 1416 | enum port port) |
330e20ec VS |
1417 | { |
1418 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
1419 | return skl_aux_ctl_reg(dev_priv, port); | |
1420 | else if (HAS_PCH_SPLIT(dev_priv)) | |
1421 | return ilk_aux_ctl_reg(dev_priv, port); | |
1422 | else | |
1423 | return g4x_aux_ctl_reg(dev_priv, port); | |
1424 | } | |
1425 | ||
f0f59a00 | 1426 | static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv, |
c8a89b08 | 1427 | enum port port, int index) |
330e20ec VS |
1428 | { |
1429 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
1430 | return skl_aux_data_reg(dev_priv, port, index); | |
1431 | else if (HAS_PCH_SPLIT(dev_priv)) | |
1432 | return ilk_aux_data_reg(dev_priv, port, index); | |
1433 | else | |
1434 | return g4x_aux_data_reg(dev_priv, port, index); | |
1435 | } | |
1436 | ||
1437 | static void intel_aux_reg_init(struct intel_dp *intel_dp) | |
1438 | { | |
1439 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); | |
8f7ce038 VS |
1440 | enum port port = intel_aux_port(dev_priv, |
1441 | dp_to_dig_port(intel_dp)->port); | |
330e20ec VS |
1442 | int i; |
1443 | ||
1444 | intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port); | |
1445 | for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++) | |
1446 | intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i); | |
1447 | } | |
1448 | ||
9d1a1031 | 1449 | static void |
a121f4e5 VS |
1450 | intel_dp_aux_fini(struct intel_dp *intel_dp) |
1451 | { | |
a121f4e5 VS |
1452 | kfree(intel_dp->aux.name); |
1453 | } | |
1454 | ||
7a418e34 | 1455 | static void |
b6339585 | 1456 | intel_dp_aux_init(struct intel_dp *intel_dp) |
9d1a1031 | 1457 | { |
33ad6626 JN |
1458 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1459 | enum port port = intel_dig_port->port; | |
ab2c0672 | 1460 | |
330e20ec | 1461 | intel_aux_reg_init(intel_dp); |
7a418e34 | 1462 | drm_dp_aux_init(&intel_dp->aux); |
8316f337 | 1463 | |
7a418e34 | 1464 | /* Failure to allocate our preferred name is not critical */ |
a121f4e5 | 1465 | intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port)); |
9d1a1031 | 1466 | intel_dp->aux.transfer = intel_dp_aux_transfer; |
a4fc5ed6 KP |
1467 | } |
1468 | ||
e588fa18 | 1469 | bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp) |
ed63baaf | 1470 | { |
e588fa18 | 1471 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
577c5430 | 1472 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
e588fa18 | 1473 | |
577c5430 NM |
1474 | if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) || |
1475 | IS_BROADWELL(dev_priv) || (INTEL_GEN(dev_priv) >= 9)) | |
ed63baaf TS |
1476 | return true; |
1477 | else | |
1478 | return false; | |
1479 | } | |
1480 | ||
c6bb3538 DV |
1481 | static void |
1482 | intel_dp_set_clock(struct intel_encoder *encoder, | |
840b32b7 | 1483 | struct intel_crtc_state *pipe_config) |
c6bb3538 DV |
1484 | { |
1485 | struct drm_device *dev = encoder->base.dev; | |
6e266956 | 1486 | struct drm_i915_private *dev_priv = to_i915(dev); |
9dd4ffdf CML |
1487 | const struct dp_link_dpll *divisor = NULL; |
1488 | int i, count = 0; | |
c6bb3538 | 1489 | |
9beb5fea | 1490 | if (IS_G4X(dev_priv)) { |
9dd4ffdf CML |
1491 | divisor = gen4_dpll; |
1492 | count = ARRAY_SIZE(gen4_dpll); | |
6e266956 | 1493 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
9dd4ffdf CML |
1494 | divisor = pch_dpll; |
1495 | count = ARRAY_SIZE(pch_dpll); | |
920a14b2 | 1496 | } else if (IS_CHERRYVIEW(dev_priv)) { |
ef9348c8 CML |
1497 | divisor = chv_dpll; |
1498 | count = ARRAY_SIZE(chv_dpll); | |
11a914c2 | 1499 | } else if (IS_VALLEYVIEW(dev_priv)) { |
65ce4bf5 CML |
1500 | divisor = vlv_dpll; |
1501 | count = ARRAY_SIZE(vlv_dpll); | |
c6bb3538 | 1502 | } |
9dd4ffdf CML |
1503 | |
1504 | if (divisor && count) { | |
1505 | for (i = 0; i < count; i++) { | |
840b32b7 | 1506 | if (pipe_config->port_clock == divisor[i].clock) { |
9dd4ffdf CML |
1507 | pipe_config->dpll = divisor[i].dpll; |
1508 | pipe_config->clock_set = true; | |
1509 | break; | |
1510 | } | |
1511 | } | |
c6bb3538 DV |
1512 | } |
1513 | } | |
1514 | ||
0336400e VS |
1515 | static void snprintf_int_array(char *str, size_t len, |
1516 | const int *array, int nelem) | |
1517 | { | |
1518 | int i; | |
1519 | ||
1520 | str[0] = '\0'; | |
1521 | ||
1522 | for (i = 0; i < nelem; i++) { | |
b2f505be | 1523 | int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]); |
0336400e VS |
1524 | if (r >= len) |
1525 | return; | |
1526 | str += r; | |
1527 | len -= r; | |
1528 | } | |
1529 | } | |
1530 | ||
1531 | static void intel_dp_print_rates(struct intel_dp *intel_dp) | |
1532 | { | |
0336400e VS |
1533 | char str[128]; /* FIXME: too big for stack? */ |
1534 | ||
1535 | if ((drm_debug & DRM_UT_KMS) == 0) | |
1536 | return; | |
1537 | ||
55cfc580 JN |
1538 | snprintf_int_array(str, sizeof(str), |
1539 | intel_dp->source_rates, intel_dp->num_source_rates); | |
0336400e VS |
1540 | DRM_DEBUG_KMS("source rates: %s\n", str); |
1541 | ||
68f357cb JN |
1542 | snprintf_int_array(str, sizeof(str), |
1543 | intel_dp->sink_rates, intel_dp->num_sink_rates); | |
0336400e VS |
1544 | DRM_DEBUG_KMS("sink rates: %s\n", str); |
1545 | ||
975ee5fc JN |
1546 | snprintf_int_array(str, sizeof(str), |
1547 | intel_dp->common_rates, intel_dp->num_common_rates); | |
94ca719e | 1548 | DRM_DEBUG_KMS("common rates: %s\n", str); |
0336400e VS |
1549 | } |
1550 | ||
50fec21a VS |
1551 | int |
1552 | intel_dp_max_link_rate(struct intel_dp *intel_dp) | |
1553 | { | |
50fec21a VS |
1554 | int len; |
1555 | ||
e6c0c64a | 1556 | len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate); |
50fec21a VS |
1557 | if (WARN_ON(len <= 0)) |
1558 | return 162000; | |
1559 | ||
975ee5fc | 1560 | return intel_dp->common_rates[len - 1]; |
50fec21a VS |
1561 | } |
1562 | ||
ed4e9c1d VS |
1563 | int intel_dp_rate_select(struct intel_dp *intel_dp, int rate) |
1564 | { | |
8001b754 JN |
1565 | int i = intel_dp_rate_index(intel_dp->sink_rates, |
1566 | intel_dp->num_sink_rates, rate); | |
b5c72b20 JN |
1567 | |
1568 | if (WARN_ON(i < 0)) | |
1569 | i = 0; | |
1570 | ||
1571 | return i; | |
ed4e9c1d VS |
1572 | } |
1573 | ||
94223d04 ACO |
1574 | void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, |
1575 | uint8_t *link_bw, uint8_t *rate_select) | |
04a60f9f | 1576 | { |
68f357cb JN |
1577 | /* eDP 1.4 rate select method. */ |
1578 | if (intel_dp->use_rate_select) { | |
04a60f9f VS |
1579 | *link_bw = 0; |
1580 | *rate_select = | |
1581 | intel_dp_rate_select(intel_dp, port_clock); | |
1582 | } else { | |
1583 | *link_bw = drm_dp_link_rate_to_bw_code(port_clock); | |
1584 | *rate_select = 0; | |
1585 | } | |
1586 | } | |
1587 | ||
f580bea9 JN |
1588 | static int intel_dp_compute_bpp(struct intel_dp *intel_dp, |
1589 | struct intel_crtc_state *pipe_config) | |
f9bb705e MK |
1590 | { |
1591 | int bpp, bpc; | |
1592 | ||
1593 | bpp = pipe_config->pipe_bpp; | |
1594 | bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports); | |
1595 | ||
1596 | if (bpc > 0) | |
1597 | bpp = min(bpp, 3*bpc); | |
1598 | ||
611032bf MN |
1599 | /* For DP Compliance we override the computed bpp for the pipe */ |
1600 | if (intel_dp->compliance.test_data.bpc != 0) { | |
1601 | pipe_config->pipe_bpp = 3*intel_dp->compliance.test_data.bpc; | |
1602 | pipe_config->dither_force_disable = pipe_config->pipe_bpp == 6*3; | |
1603 | DRM_DEBUG_KMS("Setting pipe_bpp to %d\n", | |
1604 | pipe_config->pipe_bpp); | |
1605 | } | |
f9bb705e MK |
1606 | return bpp; |
1607 | } | |
1608 | ||
9081fd90 JB |
1609 | static bool intel_edp_compare_alt_mode(struct drm_display_mode *m1, |
1610 | struct drm_display_mode *m2) | |
1611 | { | |
1612 | bool bres = false; | |
1613 | ||
1614 | if (m1 && m2) | |
1615 | bres = (m1->hdisplay == m2->hdisplay && | |
1616 | m1->hsync_start == m2->hsync_start && | |
1617 | m1->hsync_end == m2->hsync_end && | |
1618 | m1->htotal == m2->htotal && | |
1619 | m1->vdisplay == m2->vdisplay && | |
1620 | m1->vsync_start == m2->vsync_start && | |
1621 | m1->vsync_end == m2->vsync_end && | |
1622 | m1->vtotal == m2->vtotal); | |
1623 | return bres; | |
1624 | } | |
1625 | ||
00c09d70 | 1626 | bool |
5bfe2ac0 | 1627 | intel_dp_compute_config(struct intel_encoder *encoder, |
0a478c27 ML |
1628 | struct intel_crtc_state *pipe_config, |
1629 | struct drm_connector_state *conn_state) | |
a4fc5ed6 | 1630 | { |
dd11bc10 | 1631 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2d112de7 | 1632 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
5bfe2ac0 | 1633 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 1634 | enum port port = dp_to_dig_port(intel_dp)->port; |
84556d58 | 1635 | struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); |
dd06f90e | 1636 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
8f647a01 ML |
1637 | struct intel_digital_connector_state *intel_conn_state = |
1638 | to_intel_digital_connector_state(conn_state); | |
a4fc5ed6 | 1639 | int lane_count, clock; |
56071a20 | 1640 | int min_lane_count = 1; |
eeb6324d | 1641 | int max_lane_count = intel_dp_max_lane_count(intel_dp); |
06ea66b6 | 1642 | /* Conveniently, the link BW constants become indices with a shift...*/ |
56071a20 | 1643 | int min_clock = 0; |
a8f3ef61 | 1644 | int max_clock; |
083f9560 | 1645 | int bpp, mode_rate; |
ff9a6750 | 1646 | int link_avail, link_clock; |
94ca719e | 1647 | int common_len; |
04a60f9f | 1648 | uint8_t link_bw, rate_select; |
b31e85ed JN |
1649 | bool reduce_m_n = drm_dp_has_quirk(&intel_dp->desc, |
1650 | DP_DPCD_QUIRK_LIMITED_M_N); | |
a8f3ef61 | 1651 | |
975ee5fc | 1652 | common_len = intel_dp_common_len_rate_limit(intel_dp, |
e6c0c64a | 1653 | intel_dp->max_link_rate); |
a8f3ef61 SJ |
1654 | |
1655 | /* No common link rates between source and sink */ | |
94ca719e | 1656 | WARN_ON(common_len <= 0); |
a8f3ef61 | 1657 | |
94ca719e | 1658 | max_clock = common_len - 1; |
a4fc5ed6 | 1659 | |
4f8036a2 | 1660 | if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A) |
5bfe2ac0 DV |
1661 | pipe_config->has_pch_encoder = true; |
1662 | ||
f769cd24 | 1663 | pipe_config->has_drrs = false; |
e6b72c94 ML |
1664 | if (port == PORT_A) |
1665 | pipe_config->has_audio = false; | |
8f647a01 | 1666 | else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) |
e6b72c94 ML |
1667 | pipe_config->has_audio = intel_dp->has_audio; |
1668 | else | |
8f647a01 | 1669 | pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON; |
a4fc5ed6 | 1670 | |
01a7507f | 1671 | if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
9081fd90 JB |
1672 | struct drm_display_mode *panel_mode = |
1673 | intel_connector->panel.alt_fixed_mode; | |
1674 | struct drm_display_mode *req_mode = &pipe_config->base.mode; | |
1675 | ||
1676 | if (!intel_edp_compare_alt_mode(req_mode, panel_mode)) | |
1677 | panel_mode = intel_connector->panel.fixed_mode; | |
1678 | ||
1679 | drm_mode_debug_printmodeline(panel_mode); | |
1680 | ||
1681 | intel_fixed_panel_mode(panel_mode, adjusted_mode); | |
a1b2278e | 1682 | |
dd11bc10 | 1683 | if (INTEL_GEN(dev_priv) >= 9) { |
a1b2278e | 1684 | int ret; |
e435d6e5 | 1685 | ret = skl_update_scaler_crtc(pipe_config); |
a1b2278e CK |
1686 | if (ret) |
1687 | return ret; | |
1688 | } | |
1689 | ||
49cff963 | 1690 | if (HAS_GMCH_DISPLAY(dev_priv)) |
2dd24552 | 1691 | intel_gmch_panel_fitting(intel_crtc, pipe_config, |
eead06df | 1692 | conn_state->scaling_mode); |
2dd24552 | 1693 | else |
b074cec8 | 1694 | intel_pch_panel_fitting(intel_crtc, pipe_config, |
eead06df | 1695 | conn_state->scaling_mode); |
0d3a1bee ZY |
1696 | } |
1697 | ||
cb1793ce | 1698 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
0af78a2b DV |
1699 | return false; |
1700 | ||
da15f7cb MN |
1701 | /* Use values requested by Compliance Test Request */ |
1702 | if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) { | |
ec990e21 JN |
1703 | int index; |
1704 | ||
1705 | index = intel_dp_rate_index(intel_dp->common_rates, | |
1706 | intel_dp->num_common_rates, | |
1707 | intel_dp->compliance.test_link_rate); | |
1708 | if (index >= 0) | |
1709 | min_clock = max_clock = index; | |
da15f7cb MN |
1710 | min_lane_count = max_lane_count = intel_dp->compliance.test_lane_count; |
1711 | } | |
083f9560 | 1712 | DRM_DEBUG_KMS("DP link computation with max lane count %i " |
a8f3ef61 | 1713 | "max bw %d pixel clock %iKHz\n", |
975ee5fc | 1714 | max_lane_count, intel_dp->common_rates[max_clock], |
241bfc38 | 1715 | adjusted_mode->crtc_clock); |
083f9560 | 1716 | |
36008365 DV |
1717 | /* Walk through all bpp values. Luckily they're all nicely spaced with 2 |
1718 | * bpc in between. */ | |
f9bb705e | 1719 | bpp = intel_dp_compute_bpp(intel_dp, pipe_config); |
01a7507f | 1720 | if (intel_dp_is_edp(intel_dp)) { |
22ce5628 TS |
1721 | |
1722 | /* Get bpp from vbt only for panels that dont have bpp in edid */ | |
1723 | if (intel_connector->base.display_info.bpc == 0 && | |
6aa23e65 | 1724 | (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) { |
56071a20 | 1725 | DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", |
6aa23e65 JN |
1726 | dev_priv->vbt.edp.bpp); |
1727 | bpp = dev_priv->vbt.edp.bpp; | |
56071a20 JN |
1728 | } |
1729 | ||
344c5bbc JN |
1730 | /* |
1731 | * Use the maximum clock and number of lanes the eDP panel | |
1732 | * advertizes being capable of. The panels are generally | |
1733 | * designed to support only a single clock and lane | |
1734 | * configuration, and typically these values correspond to the | |
1735 | * native resolution of the panel. | |
1736 | */ | |
1737 | min_lane_count = max_lane_count; | |
1738 | min_clock = max_clock; | |
7984211e | 1739 | } |
657445fe | 1740 | |
36008365 | 1741 | for (; bpp >= 6*3; bpp -= 2*3) { |
241bfc38 DL |
1742 | mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, |
1743 | bpp); | |
36008365 | 1744 | |
c6930992 | 1745 | for (clock = min_clock; clock <= max_clock; clock++) { |
a8f3ef61 SJ |
1746 | for (lane_count = min_lane_count; |
1747 | lane_count <= max_lane_count; | |
1748 | lane_count <<= 1) { | |
1749 | ||
975ee5fc | 1750 | link_clock = intel_dp->common_rates[clock]; |
36008365 DV |
1751 | link_avail = intel_dp_max_data_rate(link_clock, |
1752 | lane_count); | |
1753 | ||
1754 | if (mode_rate <= link_avail) { | |
1755 | goto found; | |
1756 | } | |
1757 | } | |
1758 | } | |
1759 | } | |
c4867936 | 1760 | |
36008365 | 1761 | return false; |
3685a8f3 | 1762 | |
36008365 | 1763 | found: |
8f647a01 | 1764 | if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { |
55bc60db VS |
1765 | /* |
1766 | * See: | |
1767 | * CEA-861-E - 5.1 Default Encoding Parameters | |
1768 | * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry | |
1769 | */ | |
0f2a2a75 | 1770 | pipe_config->limited_color_range = |
c8127cf0 VS |
1771 | bpp != 18 && |
1772 | drm_default_rgb_quant_range(adjusted_mode) == | |
1773 | HDMI_QUANTIZATION_RANGE_LIMITED; | |
0f2a2a75 VS |
1774 | } else { |
1775 | pipe_config->limited_color_range = | |
8f647a01 | 1776 | intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED; |
55bc60db VS |
1777 | } |
1778 | ||
90a6b7b0 | 1779 | pipe_config->lane_count = lane_count; |
a8f3ef61 | 1780 | |
657445fe | 1781 | pipe_config->pipe_bpp = bpp; |
975ee5fc | 1782 | pipe_config->port_clock = intel_dp->common_rates[clock]; |
a4fc5ed6 | 1783 | |
04a60f9f VS |
1784 | intel_dp_compute_rate(intel_dp, pipe_config->port_clock, |
1785 | &link_bw, &rate_select); | |
1786 | ||
1787 | DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n", | |
1788 | link_bw, rate_select, pipe_config->lane_count, | |
ff9a6750 | 1789 | pipe_config->port_clock, bpp); |
36008365 DV |
1790 | DRM_DEBUG_KMS("DP link bw required %i available %i\n", |
1791 | mode_rate, link_avail); | |
a4fc5ed6 | 1792 | |
03afc4a2 | 1793 | intel_link_compute_m_n(bpp, lane_count, |
241bfc38 DL |
1794 | adjusted_mode->crtc_clock, |
1795 | pipe_config->port_clock, | |
b31e85ed JN |
1796 | &pipe_config->dp_m_n, |
1797 | reduce_m_n); | |
9d1a455b | 1798 | |
439d7ac0 | 1799 | if (intel_connector->panel.downclock_mode != NULL && |
96178eeb | 1800 | dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) { |
f769cd24 | 1801 | pipe_config->has_drrs = true; |
439d7ac0 PB |
1802 | intel_link_compute_m_n(bpp, lane_count, |
1803 | intel_connector->panel.downclock_mode->clock, | |
1804 | pipe_config->port_clock, | |
b31e85ed JN |
1805 | &pipe_config->dp_m2_n2, |
1806 | reduce_m_n); | |
439d7ac0 PB |
1807 | } |
1808 | ||
14d41b3b VS |
1809 | /* |
1810 | * DPLL0 VCO may need to be adjusted to get the correct | |
1811 | * clock for eDP. This will affect cdclk as well. | |
1812 | */ | |
01a7507f | 1813 | if (intel_dp_is_edp(intel_dp) && IS_GEN9_BC(dev_priv)) { |
14d41b3b VS |
1814 | int vco; |
1815 | ||
1816 | switch (pipe_config->port_clock / 2) { | |
1817 | case 108000: | |
1818 | case 216000: | |
63911d72 | 1819 | vco = 8640000; |
14d41b3b VS |
1820 | break; |
1821 | default: | |
63911d72 | 1822 | vco = 8100000; |
14d41b3b VS |
1823 | break; |
1824 | } | |
1825 | ||
bb0f4aab | 1826 | to_intel_atomic_state(pipe_config->base.state)->cdclk.logical.vco = vco; |
14d41b3b VS |
1827 | } |
1828 | ||
4f8036a2 | 1829 | if (!HAS_DDI(dev_priv)) |
840b32b7 | 1830 | intel_dp_set_clock(encoder, pipe_config); |
c6bb3538 | 1831 | |
03afc4a2 | 1832 | return true; |
a4fc5ed6 KP |
1833 | } |
1834 | ||
901c2daf | 1835 | void intel_dp_set_link_params(struct intel_dp *intel_dp, |
dfa10480 ACO |
1836 | int link_rate, uint8_t lane_count, |
1837 | bool link_mst) | |
901c2daf | 1838 | { |
dfa10480 ACO |
1839 | intel_dp->link_rate = link_rate; |
1840 | intel_dp->lane_count = lane_count; | |
1841 | intel_dp->link_mst = link_mst; | |
901c2daf VS |
1842 | } |
1843 | ||
85cb48a1 ML |
1844 | static void intel_dp_prepare(struct intel_encoder *encoder, |
1845 | struct intel_crtc_state *pipe_config) | |
a4fc5ed6 | 1846 | { |
b934223d | 1847 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 1848 | struct drm_i915_private *dev_priv = to_i915(dev); |
b934223d | 1849 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 1850 | enum port port = dp_to_dig_port(intel_dp)->port; |
b934223d | 1851 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
85cb48a1 | 1852 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
a4fc5ed6 | 1853 | |
dfa10480 ACO |
1854 | intel_dp_set_link_params(intel_dp, pipe_config->port_clock, |
1855 | pipe_config->lane_count, | |
1856 | intel_crtc_has_type(pipe_config, | |
1857 | INTEL_OUTPUT_DP_MST)); | |
901c2daf | 1858 | |
417e822d | 1859 | /* |
1a2eb460 | 1860 | * There are four kinds of DP registers: |
417e822d KP |
1861 | * |
1862 | * IBX PCH | |
1a2eb460 KP |
1863 | * SNB CPU |
1864 | * IVB CPU | |
417e822d KP |
1865 | * CPT PCH |
1866 | * | |
1867 | * IBX PCH and CPU are the same for almost everything, | |
1868 | * except that the CPU DP PLL is configured in this | |
1869 | * register | |
1870 | * | |
1871 | * CPT PCH is quite different, having many bits moved | |
1872 | * to the TRANS_DP_CTL register instead. That | |
1873 | * configuration happens (oddly) in ironlake_pch_enable | |
1874 | */ | |
9c9e7927 | 1875 | |
417e822d KP |
1876 | /* Preserve the BIOS-computed detected bit. This is |
1877 | * supposed to be read-only. | |
1878 | */ | |
1879 | intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; | |
a4fc5ed6 | 1880 | |
417e822d | 1881 | /* Handle DP bits in common between all three register formats */ |
417e822d | 1882 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
85cb48a1 | 1883 | intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count); |
a4fc5ed6 | 1884 | |
417e822d | 1885 | /* Split out the IBX/CPU vs CPT settings */ |
32f9d658 | 1886 | |
5db94019 | 1887 | if (IS_GEN7(dev_priv) && port == PORT_A) { |
1a2eb460 KP |
1888 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
1889 | intel_dp->DP |= DP_SYNC_HS_HIGH; | |
1890 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
1891 | intel_dp->DP |= DP_SYNC_VS_HIGH; | |
1892 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; | |
1893 | ||
6aba5b6c | 1894 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
1a2eb460 KP |
1895 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
1896 | ||
7c62a164 | 1897 | intel_dp->DP |= crtc->pipe << 29; |
6e266956 | 1898 | } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) { |
e3ef4479 VS |
1899 | u32 trans_dp; |
1900 | ||
39e5fa88 | 1901 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
e3ef4479 VS |
1902 | |
1903 | trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); | |
1904 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) | |
1905 | trans_dp |= TRANS_DP_ENH_FRAMING; | |
1906 | else | |
1907 | trans_dp &= ~TRANS_DP_ENH_FRAMING; | |
1908 | I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp); | |
39e5fa88 | 1909 | } else { |
c99f53f7 | 1910 | if (IS_G4X(dev_priv) && pipe_config->limited_color_range) |
0f2a2a75 | 1911 | intel_dp->DP |= DP_COLOR_RANGE_16_235; |
417e822d KP |
1912 | |
1913 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
1914 | intel_dp->DP |= DP_SYNC_HS_HIGH; | |
1915 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
1916 | intel_dp->DP |= DP_SYNC_VS_HIGH; | |
1917 | intel_dp->DP |= DP_LINK_TRAIN_OFF; | |
1918 | ||
6aba5b6c | 1919 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
417e822d KP |
1920 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
1921 | ||
920a14b2 | 1922 | if (IS_CHERRYVIEW(dev_priv)) |
44f37d1f | 1923 | intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe); |
39e5fa88 VS |
1924 | else if (crtc->pipe == PIPE_B) |
1925 | intel_dp->DP |= DP_PIPEB_SELECT; | |
32f9d658 | 1926 | } |
a4fc5ed6 KP |
1927 | } |
1928 | ||
ffd6749d PZ |
1929 | #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
1930 | #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) | |
99ea7127 | 1931 | |
1a5ef5b7 PZ |
1932 | #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) |
1933 | #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) | |
99ea7127 | 1934 | |
ffd6749d PZ |
1935 | #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) |
1936 | #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) | |
99ea7127 | 1937 | |
de9c1b6b ID |
1938 | static void intel_pps_verify_state(struct drm_i915_private *dev_priv, |
1939 | struct intel_dp *intel_dp); | |
1940 | ||
4be73780 | 1941 | static void wait_panel_status(struct intel_dp *intel_dp, |
99ea7127 KP |
1942 | u32 mask, |
1943 | u32 value) | |
bd943159 | 1944 | { |
30add22d | 1945 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 1946 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 1947 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
453c5420 | 1948 | |
e39b999a VS |
1949 | lockdep_assert_held(&dev_priv->pps_mutex); |
1950 | ||
de9c1b6b ID |
1951 | intel_pps_verify_state(dev_priv, intel_dp); |
1952 | ||
bf13e81b JN |
1953 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1954 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); | |
32ce697c | 1955 | |
99ea7127 | 1956 | DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", |
453c5420 JB |
1957 | mask, value, |
1958 | I915_READ(pp_stat_reg), | |
1959 | I915_READ(pp_ctrl_reg)); | |
32ce697c | 1960 | |
9036ff06 CW |
1961 | if (intel_wait_for_register(dev_priv, |
1962 | pp_stat_reg, mask, value, | |
1963 | 5000)) | |
99ea7127 | 1964 | DRM_ERROR("Panel status timeout: status %08x control %08x\n", |
453c5420 JB |
1965 | I915_READ(pp_stat_reg), |
1966 | I915_READ(pp_ctrl_reg)); | |
54c136d4 CW |
1967 | |
1968 | DRM_DEBUG_KMS("Wait complete\n"); | |
99ea7127 | 1969 | } |
32ce697c | 1970 | |
4be73780 | 1971 | static void wait_panel_on(struct intel_dp *intel_dp) |
99ea7127 KP |
1972 | { |
1973 | DRM_DEBUG_KMS("Wait for panel power on\n"); | |
4be73780 | 1974 | wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); |
bd943159 KP |
1975 | } |
1976 | ||
4be73780 | 1977 | static void wait_panel_off(struct intel_dp *intel_dp) |
99ea7127 KP |
1978 | { |
1979 | DRM_DEBUG_KMS("Wait for panel power off time\n"); | |
4be73780 | 1980 | wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); |
99ea7127 KP |
1981 | } |
1982 | ||
4be73780 | 1983 | static void wait_panel_power_cycle(struct intel_dp *intel_dp) |
99ea7127 | 1984 | { |
d28d4731 AK |
1985 | ktime_t panel_power_on_time; |
1986 | s64 panel_power_off_duration; | |
1987 | ||
99ea7127 | 1988 | DRM_DEBUG_KMS("Wait for panel power cycle\n"); |
dce56b3c | 1989 | |
d28d4731 AK |
1990 | /* take the difference of currrent time and panel power off time |
1991 | * and then make panel wait for t11_t12 if needed. */ | |
1992 | panel_power_on_time = ktime_get_boottime(); | |
1993 | panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time); | |
1994 | ||
dce56b3c PZ |
1995 | /* When we disable the VDD override bit last we have to do the manual |
1996 | * wait. */ | |
d28d4731 AK |
1997 | if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay) |
1998 | wait_remaining_ms_from_jiffies(jiffies, | |
1999 | intel_dp->panel_power_cycle_delay - panel_power_off_duration); | |
dce56b3c | 2000 | |
4be73780 | 2001 | wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); |
99ea7127 KP |
2002 | } |
2003 | ||
4be73780 | 2004 | static void wait_backlight_on(struct intel_dp *intel_dp) |
dce56b3c PZ |
2005 | { |
2006 | wait_remaining_ms_from_jiffies(intel_dp->last_power_on, | |
2007 | intel_dp->backlight_on_delay); | |
2008 | } | |
2009 | ||
4be73780 | 2010 | static void edp_wait_backlight_off(struct intel_dp *intel_dp) |
dce56b3c PZ |
2011 | { |
2012 | wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, | |
2013 | intel_dp->backlight_off_delay); | |
2014 | } | |
99ea7127 | 2015 | |
832dd3c1 KP |
2016 | /* Read the current pp_control value, unlocking the register if it |
2017 | * is locked | |
2018 | */ | |
2019 | ||
453c5420 | 2020 | static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) |
832dd3c1 | 2021 | { |
453c5420 | 2022 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 2023 | struct drm_i915_private *dev_priv = to_i915(dev); |
453c5420 | 2024 | u32 control; |
832dd3c1 | 2025 | |
e39b999a VS |
2026 | lockdep_assert_held(&dev_priv->pps_mutex); |
2027 | ||
bf13e81b | 2028 | control = I915_READ(_pp_ctrl_reg(intel_dp)); |
8090ba8c ID |
2029 | if (WARN_ON(!HAS_DDI(dev_priv) && |
2030 | (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) { | |
b0a08bec VK |
2031 | control &= ~PANEL_UNLOCK_MASK; |
2032 | control |= PANEL_UNLOCK_REGS; | |
2033 | } | |
832dd3c1 | 2034 | return control; |
bd943159 KP |
2035 | } |
2036 | ||
951468f3 VS |
2037 | /* |
2038 | * Must be paired with edp_panel_vdd_off(). | |
2039 | * Must hold pps_mutex around the whole on/off sequence. | |
2040 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. | |
2041 | */ | |
1e0560e0 | 2042 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp) |
5d613501 | 2043 | { |
30add22d | 2044 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
4e6e1a54 | 2045 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
fac5e23e | 2046 | struct drm_i915_private *dev_priv = to_i915(dev); |
5d613501 | 2047 | u32 pp; |
f0f59a00 | 2048 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
adddaaf4 | 2049 | bool need_to_disable = !intel_dp->want_panel_vdd; |
5d613501 | 2050 | |
e39b999a VS |
2051 | lockdep_assert_held(&dev_priv->pps_mutex); |
2052 | ||
01a7507f | 2053 | if (!intel_dp_is_edp(intel_dp)) |
adddaaf4 | 2054 | return false; |
bd943159 | 2055 | |
2c623c11 | 2056 | cancel_delayed_work(&intel_dp->panel_vdd_work); |
bd943159 | 2057 | intel_dp->want_panel_vdd = true; |
99ea7127 | 2058 | |
4be73780 | 2059 | if (edp_have_panel_vdd(intel_dp)) |
adddaaf4 | 2060 | return need_to_disable; |
b0665d57 | 2061 | |
5432fcaf | 2062 | intel_display_power_get(dev_priv, intel_dp->aux_power_domain); |
e9cb81a2 | 2063 | |
3936fcf4 VS |
2064 | DRM_DEBUG_KMS("Turning eDP port %c VDD on\n", |
2065 | port_name(intel_dig_port->port)); | |
bd943159 | 2066 | |
4be73780 DV |
2067 | if (!edp_have_panel_power(intel_dp)) |
2068 | wait_panel_power_cycle(intel_dp); | |
99ea7127 | 2069 | |
453c5420 | 2070 | pp = ironlake_get_pp_control(intel_dp); |
5d613501 | 2071 | pp |= EDP_FORCE_VDD; |
ebf33b18 | 2072 | |
bf13e81b JN |
2073 | pp_stat_reg = _pp_stat_reg(intel_dp); |
2074 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); | |
453c5420 JB |
2075 | |
2076 | I915_WRITE(pp_ctrl_reg, pp); | |
2077 | POSTING_READ(pp_ctrl_reg); | |
2078 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", | |
2079 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); | |
ebf33b18 KP |
2080 | /* |
2081 | * If the panel wasn't on, delay before accessing aux channel | |
2082 | */ | |
4be73780 | 2083 | if (!edp_have_panel_power(intel_dp)) { |
3936fcf4 VS |
2084 | DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n", |
2085 | port_name(intel_dig_port->port)); | |
f01eca2e | 2086 | msleep(intel_dp->panel_power_up_delay); |
f01eca2e | 2087 | } |
adddaaf4 JN |
2088 | |
2089 | return need_to_disable; | |
2090 | } | |
2091 | ||
951468f3 VS |
2092 | /* |
2093 | * Must be paired with intel_edp_panel_vdd_off() or | |
2094 | * intel_edp_panel_off(). | |
2095 | * Nested calls to these functions are not allowed since | |
2096 | * we drop the lock. Caller must use some higher level | |
2097 | * locking to prevent nested calls from other threads. | |
2098 | */ | |
b80d6c78 | 2099 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) |
adddaaf4 | 2100 | { |
c695b6b6 | 2101 | bool vdd; |
adddaaf4 | 2102 | |
01a7507f | 2103 | if (!intel_dp_is_edp(intel_dp)) |
c695b6b6 VS |
2104 | return; |
2105 | ||
773538e8 | 2106 | pps_lock(intel_dp); |
c695b6b6 | 2107 | vdd = edp_panel_vdd_on(intel_dp); |
773538e8 | 2108 | pps_unlock(intel_dp); |
c695b6b6 | 2109 | |
e2c719b7 | 2110 | I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n", |
3936fcf4 | 2111 | port_name(dp_to_dig_port(intel_dp)->port)); |
5d613501 JB |
2112 | } |
2113 | ||
4be73780 | 2114 | static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) |
5d613501 | 2115 | { |
30add22d | 2116 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 2117 | struct drm_i915_private *dev_priv = to_i915(dev); |
be2c9196 VS |
2118 | struct intel_digital_port *intel_dig_port = |
2119 | dp_to_dig_port(intel_dp); | |
5d613501 | 2120 | u32 pp; |
f0f59a00 | 2121 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
5d613501 | 2122 | |
e39b999a | 2123 | lockdep_assert_held(&dev_priv->pps_mutex); |
a0e99e68 | 2124 | |
15e899a0 | 2125 | WARN_ON(intel_dp->want_panel_vdd); |
4e6e1a54 | 2126 | |
15e899a0 | 2127 | if (!edp_have_panel_vdd(intel_dp)) |
be2c9196 | 2128 | return; |
b0665d57 | 2129 | |
3936fcf4 VS |
2130 | DRM_DEBUG_KMS("Turning eDP port %c VDD off\n", |
2131 | port_name(intel_dig_port->port)); | |
bd943159 | 2132 | |
be2c9196 VS |
2133 | pp = ironlake_get_pp_control(intel_dp); |
2134 | pp &= ~EDP_FORCE_VDD; | |
453c5420 | 2135 | |
be2c9196 VS |
2136 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
2137 | pp_stat_reg = _pp_stat_reg(intel_dp); | |
99ea7127 | 2138 | |
be2c9196 VS |
2139 | I915_WRITE(pp_ctrl_reg, pp); |
2140 | POSTING_READ(pp_ctrl_reg); | |
90791a5c | 2141 | |
be2c9196 VS |
2142 | /* Make sure sequencer is idle before allowing subsequent activity */ |
2143 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", | |
2144 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); | |
e9cb81a2 | 2145 | |
5a162e22 | 2146 | if ((pp & PANEL_POWER_ON) == 0) |
d28d4731 | 2147 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
e9cb81a2 | 2148 | |
5432fcaf | 2149 | intel_display_power_put(dev_priv, intel_dp->aux_power_domain); |
bd943159 | 2150 | } |
5d613501 | 2151 | |
4be73780 | 2152 | static void edp_panel_vdd_work(struct work_struct *__work) |
bd943159 KP |
2153 | { |
2154 | struct intel_dp *intel_dp = container_of(to_delayed_work(__work), | |
2155 | struct intel_dp, panel_vdd_work); | |
bd943159 | 2156 | |
773538e8 | 2157 | pps_lock(intel_dp); |
15e899a0 VS |
2158 | if (!intel_dp->want_panel_vdd) |
2159 | edp_panel_vdd_off_sync(intel_dp); | |
773538e8 | 2160 | pps_unlock(intel_dp); |
bd943159 KP |
2161 | } |
2162 | ||
aba86890 ID |
2163 | static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp) |
2164 | { | |
2165 | unsigned long delay; | |
2166 | ||
2167 | /* | |
2168 | * Queue the timer to fire a long time from now (relative to the power | |
2169 | * down delay) to keep the panel power up across a sequence of | |
2170 | * operations. | |
2171 | */ | |
2172 | delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5); | |
2173 | schedule_delayed_work(&intel_dp->panel_vdd_work, delay); | |
2174 | } | |
2175 | ||
951468f3 VS |
2176 | /* |
2177 | * Must be paired with edp_panel_vdd_on(). | |
2178 | * Must hold pps_mutex around the whole on/off sequence. | |
2179 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. | |
2180 | */ | |
4be73780 | 2181 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) |
bd943159 | 2182 | { |
fac5e23e | 2183 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
e39b999a VS |
2184 | |
2185 | lockdep_assert_held(&dev_priv->pps_mutex); | |
2186 | ||
01a7507f | 2187 | if (!intel_dp_is_edp(intel_dp)) |
97af61f5 | 2188 | return; |
5d613501 | 2189 | |
e2c719b7 | 2190 | I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on", |
3936fcf4 | 2191 | port_name(dp_to_dig_port(intel_dp)->port)); |
f2e8b18a | 2192 | |
bd943159 KP |
2193 | intel_dp->want_panel_vdd = false; |
2194 | ||
aba86890 | 2195 | if (sync) |
4be73780 | 2196 | edp_panel_vdd_off_sync(intel_dp); |
aba86890 ID |
2197 | else |
2198 | edp_panel_vdd_schedule_off(intel_dp); | |
5d613501 JB |
2199 | } |
2200 | ||
9f0fb5be | 2201 | static void edp_panel_on(struct intel_dp *intel_dp) |
9934c132 | 2202 | { |
30add22d | 2203 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 2204 | struct drm_i915_private *dev_priv = to_i915(dev); |
99ea7127 | 2205 | u32 pp; |
f0f59a00 | 2206 | i915_reg_t pp_ctrl_reg; |
9934c132 | 2207 | |
9f0fb5be VS |
2208 | lockdep_assert_held(&dev_priv->pps_mutex); |
2209 | ||
01a7507f | 2210 | if (!intel_dp_is_edp(intel_dp)) |
bd943159 | 2211 | return; |
99ea7127 | 2212 | |
3936fcf4 VS |
2213 | DRM_DEBUG_KMS("Turn eDP port %c panel power on\n", |
2214 | port_name(dp_to_dig_port(intel_dp)->port)); | |
e39b999a | 2215 | |
e7a89ace VS |
2216 | if (WARN(edp_have_panel_power(intel_dp), |
2217 | "eDP port %c panel power already on\n", | |
2218 | port_name(dp_to_dig_port(intel_dp)->port))) | |
9f0fb5be | 2219 | return; |
9934c132 | 2220 | |
4be73780 | 2221 | wait_panel_power_cycle(intel_dp); |
37c6c9b0 | 2222 | |
bf13e81b | 2223 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 | 2224 | pp = ironlake_get_pp_control(intel_dp); |
5db94019 | 2225 | if (IS_GEN5(dev_priv)) { |
05ce1a49 KP |
2226 | /* ILK workaround: disable reset around power sequence */ |
2227 | pp &= ~PANEL_POWER_RESET; | |
bf13e81b JN |
2228 | I915_WRITE(pp_ctrl_reg, pp); |
2229 | POSTING_READ(pp_ctrl_reg); | |
05ce1a49 | 2230 | } |
37c6c9b0 | 2231 | |
5a162e22 | 2232 | pp |= PANEL_POWER_ON; |
5db94019 | 2233 | if (!IS_GEN5(dev_priv)) |
99ea7127 KP |
2234 | pp |= PANEL_POWER_RESET; |
2235 | ||
453c5420 JB |
2236 | I915_WRITE(pp_ctrl_reg, pp); |
2237 | POSTING_READ(pp_ctrl_reg); | |
9934c132 | 2238 | |
4be73780 | 2239 | wait_panel_on(intel_dp); |
dce56b3c | 2240 | intel_dp->last_power_on = jiffies; |
9934c132 | 2241 | |
5db94019 | 2242 | if (IS_GEN5(dev_priv)) { |
05ce1a49 | 2243 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
bf13e81b JN |
2244 | I915_WRITE(pp_ctrl_reg, pp); |
2245 | POSTING_READ(pp_ctrl_reg); | |
05ce1a49 | 2246 | } |
9f0fb5be | 2247 | } |
e39b999a | 2248 | |
9f0fb5be VS |
2249 | void intel_edp_panel_on(struct intel_dp *intel_dp) |
2250 | { | |
01a7507f | 2251 | if (!intel_dp_is_edp(intel_dp)) |
9f0fb5be VS |
2252 | return; |
2253 | ||
2254 | pps_lock(intel_dp); | |
2255 | edp_panel_on(intel_dp); | |
773538e8 | 2256 | pps_unlock(intel_dp); |
9934c132 JB |
2257 | } |
2258 | ||
9f0fb5be VS |
2259 | |
2260 | static void edp_panel_off(struct intel_dp *intel_dp) | |
9934c132 | 2261 | { |
30add22d | 2262 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 2263 | struct drm_i915_private *dev_priv = to_i915(dev); |
99ea7127 | 2264 | u32 pp; |
f0f59a00 | 2265 | i915_reg_t pp_ctrl_reg; |
9934c132 | 2266 | |
9f0fb5be VS |
2267 | lockdep_assert_held(&dev_priv->pps_mutex); |
2268 | ||
01a7507f | 2269 | if (!intel_dp_is_edp(intel_dp)) |
97af61f5 | 2270 | return; |
37c6c9b0 | 2271 | |
3936fcf4 VS |
2272 | DRM_DEBUG_KMS("Turn eDP port %c panel power off\n", |
2273 | port_name(dp_to_dig_port(intel_dp)->port)); | |
37c6c9b0 | 2274 | |
3936fcf4 VS |
2275 | WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n", |
2276 | port_name(dp_to_dig_port(intel_dp)->port)); | |
24f3e092 | 2277 | |
453c5420 | 2278 | pp = ironlake_get_pp_control(intel_dp); |
35a38556 DV |
2279 | /* We need to switch off panel power _and_ force vdd, for otherwise some |
2280 | * panels get very unhappy and cease to work. */ | |
5a162e22 | 2281 | pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD | |
b3064154 | 2282 | EDP_BLC_ENABLE); |
453c5420 | 2283 | |
bf13e81b | 2284 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 | 2285 | |
849e39f5 PZ |
2286 | intel_dp->want_panel_vdd = false; |
2287 | ||
453c5420 JB |
2288 | I915_WRITE(pp_ctrl_reg, pp); |
2289 | POSTING_READ(pp_ctrl_reg); | |
9934c132 | 2290 | |
4be73780 | 2291 | wait_panel_off(intel_dp); |
348d7438 | 2292 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
849e39f5 PZ |
2293 | |
2294 | /* We got a reference when we enabled the VDD. */ | |
5432fcaf | 2295 | intel_display_power_put(dev_priv, intel_dp->aux_power_domain); |
9f0fb5be | 2296 | } |
e39b999a | 2297 | |
9f0fb5be VS |
2298 | void intel_edp_panel_off(struct intel_dp *intel_dp) |
2299 | { | |
01a7507f | 2300 | if (!intel_dp_is_edp(intel_dp)) |
9f0fb5be | 2301 | return; |
e39b999a | 2302 | |
9f0fb5be VS |
2303 | pps_lock(intel_dp); |
2304 | edp_panel_off(intel_dp); | |
773538e8 | 2305 | pps_unlock(intel_dp); |
9934c132 JB |
2306 | } |
2307 | ||
1250d107 JN |
2308 | /* Enable backlight in the panel power control. */ |
2309 | static void _intel_edp_backlight_on(struct intel_dp *intel_dp) | |
32f9d658 | 2310 | { |
da63a9f2 PZ |
2311 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2312 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 2313 | struct drm_i915_private *dev_priv = to_i915(dev); |
32f9d658 | 2314 | u32 pp; |
f0f59a00 | 2315 | i915_reg_t pp_ctrl_reg; |
32f9d658 | 2316 | |
01cb9ea6 JB |
2317 | /* |
2318 | * If we enable the backlight right away following a panel power | |
2319 | * on, we may see slight flicker as the panel syncs with the eDP | |
2320 | * link. So delay a bit to make sure the image is solid before | |
2321 | * allowing it to appear. | |
2322 | */ | |
4be73780 | 2323 | wait_backlight_on(intel_dp); |
e39b999a | 2324 | |
773538e8 | 2325 | pps_lock(intel_dp); |
e39b999a | 2326 | |
453c5420 | 2327 | pp = ironlake_get_pp_control(intel_dp); |
32f9d658 | 2328 | pp |= EDP_BLC_ENABLE; |
453c5420 | 2329 | |
bf13e81b | 2330 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 JB |
2331 | |
2332 | I915_WRITE(pp_ctrl_reg, pp); | |
2333 | POSTING_READ(pp_ctrl_reg); | |
e39b999a | 2334 | |
773538e8 | 2335 | pps_unlock(intel_dp); |
32f9d658 ZW |
2336 | } |
2337 | ||
1250d107 | 2338 | /* Enable backlight PWM and backlight PP control. */ |
b037d58f ML |
2339 | void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state, |
2340 | const struct drm_connector_state *conn_state) | |
1250d107 | 2341 | { |
b037d58f ML |
2342 | struct intel_dp *intel_dp = enc_to_intel_dp(conn_state->best_encoder); |
2343 | ||
01a7507f | 2344 | if (!intel_dp_is_edp(intel_dp)) |
1250d107 JN |
2345 | return; |
2346 | ||
2347 | DRM_DEBUG_KMS("\n"); | |
2348 | ||
b037d58f | 2349 | intel_panel_enable_backlight(crtc_state, conn_state); |
1250d107 JN |
2350 | _intel_edp_backlight_on(intel_dp); |
2351 | } | |
2352 | ||
2353 | /* Disable backlight in the panel power control. */ | |
2354 | static void _intel_edp_backlight_off(struct intel_dp *intel_dp) | |
32f9d658 | 2355 | { |
30add22d | 2356 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 2357 | struct drm_i915_private *dev_priv = to_i915(dev); |
32f9d658 | 2358 | u32 pp; |
f0f59a00 | 2359 | i915_reg_t pp_ctrl_reg; |
32f9d658 | 2360 | |
01a7507f | 2361 | if (!intel_dp_is_edp(intel_dp)) |
f01eca2e KP |
2362 | return; |
2363 | ||
773538e8 | 2364 | pps_lock(intel_dp); |
e39b999a | 2365 | |
453c5420 | 2366 | pp = ironlake_get_pp_control(intel_dp); |
32f9d658 | 2367 | pp &= ~EDP_BLC_ENABLE; |
453c5420 | 2368 | |
bf13e81b | 2369 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 JB |
2370 | |
2371 | I915_WRITE(pp_ctrl_reg, pp); | |
2372 | POSTING_READ(pp_ctrl_reg); | |
f7d2323c | 2373 | |
773538e8 | 2374 | pps_unlock(intel_dp); |
e39b999a VS |
2375 | |
2376 | intel_dp->last_backlight_off = jiffies; | |
f7d2323c | 2377 | edp_wait_backlight_off(intel_dp); |
1250d107 | 2378 | } |
f7d2323c | 2379 | |
1250d107 | 2380 | /* Disable backlight PP control and backlight PWM. */ |
b037d58f | 2381 | void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state) |
1250d107 | 2382 | { |
b037d58f ML |
2383 | struct intel_dp *intel_dp = enc_to_intel_dp(old_conn_state->best_encoder); |
2384 | ||
01a7507f | 2385 | if (!intel_dp_is_edp(intel_dp)) |
1250d107 JN |
2386 | return; |
2387 | ||
2388 | DRM_DEBUG_KMS("\n"); | |
f7d2323c | 2389 | |
1250d107 | 2390 | _intel_edp_backlight_off(intel_dp); |
b037d58f | 2391 | intel_panel_disable_backlight(old_conn_state); |
32f9d658 | 2392 | } |
a4fc5ed6 | 2393 | |
73580fb7 JN |
2394 | /* |
2395 | * Hook for controlling the panel power control backlight through the bl_power | |
2396 | * sysfs attribute. Take care to handle multiple calls. | |
2397 | */ | |
2398 | static void intel_edp_backlight_power(struct intel_connector *connector, | |
2399 | bool enable) | |
2400 | { | |
2401 | struct intel_dp *intel_dp = intel_attached_dp(&connector->base); | |
e39b999a VS |
2402 | bool is_enabled; |
2403 | ||
773538e8 | 2404 | pps_lock(intel_dp); |
e39b999a | 2405 | is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE; |
773538e8 | 2406 | pps_unlock(intel_dp); |
73580fb7 JN |
2407 | |
2408 | if (is_enabled == enable) | |
2409 | return; | |
2410 | ||
23ba9373 JN |
2411 | DRM_DEBUG_KMS("panel power control backlight %s\n", |
2412 | enable ? "enable" : "disable"); | |
73580fb7 JN |
2413 | |
2414 | if (enable) | |
2415 | _intel_edp_backlight_on(intel_dp); | |
2416 | else | |
2417 | _intel_edp_backlight_off(intel_dp); | |
2418 | } | |
2419 | ||
64e1077a VS |
2420 | static void assert_dp_port(struct intel_dp *intel_dp, bool state) |
2421 | { | |
2422 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
2423 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); | |
2424 | bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN; | |
2425 | ||
2426 | I915_STATE_WARN(cur_state != state, | |
2427 | "DP port %c state assertion failure (expected %s, current %s)\n", | |
2428 | port_name(dig_port->port), | |
87ad3212 | 2429 | onoff(state), onoff(cur_state)); |
64e1077a VS |
2430 | } |
2431 | #define assert_dp_port_disabled(d) assert_dp_port((d), false) | |
2432 | ||
2433 | static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state) | |
2434 | { | |
2435 | bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE; | |
2436 | ||
2437 | I915_STATE_WARN(cur_state != state, | |
2438 | "eDP PLL state assertion failure (expected %s, current %s)\n", | |
87ad3212 | 2439 | onoff(state), onoff(cur_state)); |
64e1077a VS |
2440 | } |
2441 | #define assert_edp_pll_enabled(d) assert_edp_pll((d), true) | |
2442 | #define assert_edp_pll_disabled(d) assert_edp_pll((d), false) | |
2443 | ||
85cb48a1 ML |
2444 | static void ironlake_edp_pll_on(struct intel_dp *intel_dp, |
2445 | struct intel_crtc_state *pipe_config) | |
d240f20f | 2446 | { |
85cb48a1 | 2447 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); |
64e1077a | 2448 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
d240f20f | 2449 | |
64e1077a VS |
2450 | assert_pipe_disabled(dev_priv, crtc->pipe); |
2451 | assert_dp_port_disabled(intel_dp); | |
2452 | assert_edp_pll_disabled(dev_priv); | |
2bd2ad64 | 2453 | |
abfce949 | 2454 | DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n", |
85cb48a1 | 2455 | pipe_config->port_clock); |
abfce949 VS |
2456 | |
2457 | intel_dp->DP &= ~DP_PLL_FREQ_MASK; | |
2458 | ||
85cb48a1 | 2459 | if (pipe_config->port_clock == 162000) |
abfce949 VS |
2460 | intel_dp->DP |= DP_PLL_FREQ_162MHZ; |
2461 | else | |
2462 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; | |
2463 | ||
2464 | I915_WRITE(DP_A, intel_dp->DP); | |
2465 | POSTING_READ(DP_A); | |
2466 | udelay(500); | |
2467 | ||
6b23f3e8 VS |
2468 | /* |
2469 | * [DevILK] Work around required when enabling DP PLL | |
2470 | * while a pipe is enabled going to FDI: | |
2471 | * 1. Wait for the start of vertical blank on the enabled pipe going to FDI | |
2472 | * 2. Program DP PLL enable | |
2473 | */ | |
2474 | if (IS_GEN5(dev_priv)) | |
0f0f74bc | 2475 | intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe); |
6b23f3e8 | 2476 | |
0767935e | 2477 | intel_dp->DP |= DP_PLL_ENABLE; |
6fec7662 | 2478 | |
0767935e | 2479 | I915_WRITE(DP_A, intel_dp->DP); |
298b0b39 JB |
2480 | POSTING_READ(DP_A); |
2481 | udelay(200); | |
d240f20f JB |
2482 | } |
2483 | ||
2bd2ad64 | 2484 | static void ironlake_edp_pll_off(struct intel_dp *intel_dp) |
d240f20f | 2485 | { |
da63a9f2 | 2486 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
64e1077a VS |
2487 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); |
2488 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
d240f20f | 2489 | |
64e1077a VS |
2490 | assert_pipe_disabled(dev_priv, crtc->pipe); |
2491 | assert_dp_port_disabled(intel_dp); | |
2492 | assert_edp_pll_enabled(dev_priv); | |
2bd2ad64 | 2493 | |
abfce949 VS |
2494 | DRM_DEBUG_KMS("disabling eDP PLL\n"); |
2495 | ||
6fec7662 | 2496 | intel_dp->DP &= ~DP_PLL_ENABLE; |
0767935e | 2497 | |
6fec7662 | 2498 | I915_WRITE(DP_A, intel_dp->DP); |
1af5fa1b | 2499 | POSTING_READ(DP_A); |
d240f20f JB |
2500 | udelay(200); |
2501 | } | |
2502 | ||
c7ad3810 | 2503 | /* If the sink supports it, try to set the power state appropriately */ |
c19b0669 | 2504 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) |
c7ad3810 JB |
2505 | { |
2506 | int ret, i; | |
2507 | ||
2508 | /* Should have a valid DPCD by this point */ | |
2509 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) | |
2510 | return; | |
2511 | ||
2512 | if (mode != DRM_MODE_DPMS_ON) { | |
9d1a1031 JN |
2513 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
2514 | DP_SET_POWER_D3); | |
c7ad3810 | 2515 | } else { |
357c0ae9 ID |
2516 | struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp); |
2517 | ||
c7ad3810 JB |
2518 | /* |
2519 | * When turning on, we need to retry for 1ms to give the sink | |
2520 | * time to wake up. | |
2521 | */ | |
2522 | for (i = 0; i < 3; i++) { | |
9d1a1031 JN |
2523 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
2524 | DP_SET_POWER_D0); | |
c7ad3810 JB |
2525 | if (ret == 1) |
2526 | break; | |
2527 | msleep(1); | |
2528 | } | |
357c0ae9 ID |
2529 | |
2530 | if (ret == 1 && lspcon->active) | |
2531 | lspcon_wait_pcon_mode(lspcon); | |
c7ad3810 | 2532 | } |
f9cac721 JN |
2533 | |
2534 | if (ret != 1) | |
2535 | DRM_DEBUG_KMS("failed to %s sink power state\n", | |
2536 | mode == DRM_MODE_DPMS_ON ? "enable" : "disable"); | |
c7ad3810 JB |
2537 | } |
2538 | ||
19d8fe15 DV |
2539 | static bool intel_dp_get_hw_state(struct intel_encoder *encoder, |
2540 | enum pipe *pipe) | |
d240f20f | 2541 | { |
19d8fe15 | 2542 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 2543 | enum port port = dp_to_dig_port(intel_dp)->port; |
19d8fe15 | 2544 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 2545 | struct drm_i915_private *dev_priv = to_i915(dev); |
6d129bea | 2546 | u32 tmp; |
6fa9a5ec | 2547 | bool ret; |
6d129bea | 2548 | |
79f255a0 ACO |
2549 | if (!intel_display_power_get_if_enabled(dev_priv, |
2550 | encoder->power_domain)) | |
6d129bea ID |
2551 | return false; |
2552 | ||
6fa9a5ec ID |
2553 | ret = false; |
2554 | ||
6d129bea | 2555 | tmp = I915_READ(intel_dp->output_reg); |
19d8fe15 DV |
2556 | |
2557 | if (!(tmp & DP_PORT_EN)) | |
6fa9a5ec | 2558 | goto out; |
19d8fe15 | 2559 | |
5db94019 | 2560 | if (IS_GEN7(dev_priv) && port == PORT_A) { |
19d8fe15 | 2561 | *pipe = PORT_TO_PIPE_CPT(tmp); |
6e266956 | 2562 | } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) { |
adc289d7 | 2563 | enum pipe p; |
19d8fe15 | 2564 | |
adc289d7 VS |
2565 | for_each_pipe(dev_priv, p) { |
2566 | u32 trans_dp = I915_READ(TRANS_DP_CTL(p)); | |
2567 | if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) { | |
2568 | *pipe = p; | |
6fa9a5ec ID |
2569 | ret = true; |
2570 | ||
2571 | goto out; | |
19d8fe15 DV |
2572 | } |
2573 | } | |
19d8fe15 | 2574 | |
4a0833ec | 2575 | DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", |
f0f59a00 | 2576 | i915_mmio_reg_offset(intel_dp->output_reg)); |
920a14b2 | 2577 | } else if (IS_CHERRYVIEW(dev_priv)) { |
39e5fa88 VS |
2578 | *pipe = DP_PORT_TO_PIPE_CHV(tmp); |
2579 | } else { | |
2580 | *pipe = PORT_TO_PIPE(tmp); | |
4a0833ec | 2581 | } |
d240f20f | 2582 | |
6fa9a5ec ID |
2583 | ret = true; |
2584 | ||
2585 | out: | |
79f255a0 | 2586 | intel_display_power_put(dev_priv, encoder->power_domain); |
6fa9a5ec ID |
2587 | |
2588 | return ret; | |
19d8fe15 | 2589 | } |
d240f20f | 2590 | |
045ac3b5 | 2591 | static void intel_dp_get_config(struct intel_encoder *encoder, |
5cec258b | 2592 | struct intel_crtc_state *pipe_config) |
045ac3b5 JB |
2593 | { |
2594 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
045ac3b5 | 2595 | u32 tmp, flags = 0; |
63000ef6 | 2596 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 2597 | struct drm_i915_private *dev_priv = to_i915(dev); |
63000ef6 XZ |
2598 | enum port port = dp_to_dig_port(intel_dp)->port; |
2599 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
045ac3b5 | 2600 | |
9ed109a7 | 2601 | tmp = I915_READ(intel_dp->output_reg); |
9fcb1704 JN |
2602 | |
2603 | pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A; | |
9ed109a7 | 2604 | |
6e266956 | 2605 | if (HAS_PCH_CPT(dev_priv) && port != PORT_A) { |
b81e34c2 VS |
2606 | u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); |
2607 | ||
2608 | if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH) | |
63000ef6 XZ |
2609 | flags |= DRM_MODE_FLAG_PHSYNC; |
2610 | else | |
2611 | flags |= DRM_MODE_FLAG_NHSYNC; | |
045ac3b5 | 2612 | |
b81e34c2 | 2613 | if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH) |
63000ef6 XZ |
2614 | flags |= DRM_MODE_FLAG_PVSYNC; |
2615 | else | |
2616 | flags |= DRM_MODE_FLAG_NVSYNC; | |
2617 | } else { | |
39e5fa88 | 2618 | if (tmp & DP_SYNC_HS_HIGH) |
63000ef6 XZ |
2619 | flags |= DRM_MODE_FLAG_PHSYNC; |
2620 | else | |
2621 | flags |= DRM_MODE_FLAG_NHSYNC; | |
045ac3b5 | 2622 | |
39e5fa88 | 2623 | if (tmp & DP_SYNC_VS_HIGH) |
63000ef6 XZ |
2624 | flags |= DRM_MODE_FLAG_PVSYNC; |
2625 | else | |
2626 | flags |= DRM_MODE_FLAG_NVSYNC; | |
2627 | } | |
045ac3b5 | 2628 | |
2d112de7 | 2629 | pipe_config->base.adjusted_mode.flags |= flags; |
f1f644dc | 2630 | |
c99f53f7 | 2631 | if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235) |
8c875fca VS |
2632 | pipe_config->limited_color_range = true; |
2633 | ||
90a6b7b0 VS |
2634 | pipe_config->lane_count = |
2635 | ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1; | |
2636 | ||
eb14cb74 VS |
2637 | intel_dp_get_m_n(crtc, pipe_config); |
2638 | ||
18442d08 | 2639 | if (port == PORT_A) { |
b377e0df | 2640 | if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ) |
f1f644dc JB |
2641 | pipe_config->port_clock = 162000; |
2642 | else | |
2643 | pipe_config->port_clock = 270000; | |
2644 | } | |
18442d08 | 2645 | |
e3b247da VS |
2646 | pipe_config->base.adjusted_mode.crtc_clock = |
2647 | intel_dotclock_calculate(pipe_config->port_clock, | |
2648 | &pipe_config->dp_m_n); | |
7f16e5c1 | 2649 | |
01a7507f | 2650 | if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp && |
6aa23e65 | 2651 | pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { |
c6cd2ee2 JN |
2652 | /* |
2653 | * This is a big fat ugly hack. | |
2654 | * | |
2655 | * Some machines in UEFI boot mode provide us a VBT that has 18 | |
2656 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons | |
2657 | * unknown we fail to light up. Yet the same BIOS boots up with | |
2658 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as | |
2659 | * max, not what it tells us to use. | |
2660 | * | |
2661 | * Note: This will still be broken if the eDP panel is not lit | |
2662 | * up by the BIOS, and thus we can't get the mode at module | |
2663 | * load. | |
2664 | */ | |
2665 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", | |
6aa23e65 JN |
2666 | pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); |
2667 | dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; | |
c6cd2ee2 | 2668 | } |
045ac3b5 JB |
2669 | } |
2670 | ||
fd6bbda9 ML |
2671 | static void intel_disable_dp(struct intel_encoder *encoder, |
2672 | struct intel_crtc_state *old_crtc_state, | |
2673 | struct drm_connector_state *old_conn_state) | |
d240f20f | 2674 | { |
e8cb4558 | 2675 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
85cb48a1 | 2676 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
495a5bb8 | 2677 | |
85cb48a1 | 2678 | if (old_crtc_state->has_audio) |
495a5bb8 | 2679 | intel_audio_codec_disable(encoder); |
6cb49835 | 2680 | |
85cb48a1 | 2681 | if (HAS_PSR(dev_priv) && !HAS_DDI(dev_priv)) |
b32c6f48 RV |
2682 | intel_psr_disable(intel_dp); |
2683 | ||
6cb49835 DV |
2684 | /* Make sure the panel is off before trying to change the mode. But also |
2685 | * ensure that we have vdd while we switch off the panel. */ | |
24f3e092 | 2686 | intel_edp_panel_vdd_on(intel_dp); |
b037d58f | 2687 | intel_edp_backlight_off(old_conn_state); |
81c5f47e WJS |
2688 | if (!(dev_priv->quirks & QUIRK_SKIP_DP_DPMS_D3)) |
2689 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); | |
4be73780 | 2690 | intel_edp_panel_off(intel_dp); |
3739850b | 2691 | |
08aff3fe | 2692 | /* disable the port before the pipe on g4x */ |
85cb48a1 | 2693 | if (INTEL_GEN(dev_priv) < 5) |
3739850b | 2694 | intel_dp_link_down(intel_dp); |
d240f20f JB |
2695 | } |
2696 | ||
fd6bbda9 ML |
2697 | static void ilk_post_disable_dp(struct intel_encoder *encoder, |
2698 | struct intel_crtc_state *old_crtc_state, | |
2699 | struct drm_connector_state *old_conn_state) | |
d240f20f | 2700 | { |
2bd2ad64 | 2701 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
982a3866 | 2702 | enum port port = dp_to_dig_port(intel_dp)->port; |
2bd2ad64 | 2703 | |
49277c31 | 2704 | intel_dp_link_down(intel_dp); |
abfce949 VS |
2705 | |
2706 | /* Only ilk+ has port A */ | |
08aff3fe VS |
2707 | if (port == PORT_A) |
2708 | ironlake_edp_pll_off(intel_dp); | |
49277c31 VS |
2709 | } |
2710 | ||
fd6bbda9 ML |
2711 | static void vlv_post_disable_dp(struct intel_encoder *encoder, |
2712 | struct intel_crtc_state *old_crtc_state, | |
2713 | struct drm_connector_state *old_conn_state) | |
49277c31 VS |
2714 | { |
2715 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
2716 | ||
2717 | intel_dp_link_down(intel_dp); | |
2bd2ad64 DV |
2718 | } |
2719 | ||
fd6bbda9 ML |
2720 | static void chv_post_disable_dp(struct intel_encoder *encoder, |
2721 | struct intel_crtc_state *old_crtc_state, | |
2722 | struct drm_connector_state *old_conn_state) | |
a8f327fb VS |
2723 | { |
2724 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
2725 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 2726 | struct drm_i915_private *dev_priv = to_i915(dev); |
97fd4d5c | 2727 | |
a8f327fb VS |
2728 | intel_dp_link_down(intel_dp); |
2729 | ||
2730 | mutex_lock(&dev_priv->sb_lock); | |
2731 | ||
2732 | /* Assert data lane reset */ | |
2733 | chv_data_lane_soft_reset(encoder, true); | |
580d3811 | 2734 | |
a580516d | 2735 | mutex_unlock(&dev_priv->sb_lock); |
580d3811 VS |
2736 | } |
2737 | ||
7b13b58a VS |
2738 | static void |
2739 | _intel_dp_set_link_train(struct intel_dp *intel_dp, | |
2740 | uint32_t *DP, | |
2741 | uint8_t dp_train_pat) | |
2742 | { | |
2743 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
2744 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 2745 | struct drm_i915_private *dev_priv = to_i915(dev); |
7b13b58a VS |
2746 | enum port port = intel_dig_port->port; |
2747 | ||
8b0878a0 PD |
2748 | if (dp_train_pat & DP_TRAINING_PATTERN_MASK) |
2749 | DRM_DEBUG_KMS("Using DP training pattern TPS%d\n", | |
2750 | dp_train_pat & DP_TRAINING_PATTERN_MASK); | |
2751 | ||
4f8036a2 | 2752 | if (HAS_DDI(dev_priv)) { |
7b13b58a VS |
2753 | uint32_t temp = I915_READ(DP_TP_CTL(port)); |
2754 | ||
2755 | if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) | |
2756 | temp |= DP_TP_CTL_SCRAMBLE_DISABLE; | |
2757 | else | |
2758 | temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; | |
2759 | ||
2760 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; | |
2761 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2762 | case DP_TRAINING_PATTERN_DISABLE: | |
2763 | temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; | |
2764 | ||
2765 | break; | |
2766 | case DP_TRAINING_PATTERN_1: | |
2767 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
2768 | break; | |
2769 | case DP_TRAINING_PATTERN_2: | |
2770 | temp |= DP_TP_CTL_LINK_TRAIN_PAT2; | |
2771 | break; | |
2772 | case DP_TRAINING_PATTERN_3: | |
2773 | temp |= DP_TP_CTL_LINK_TRAIN_PAT3; | |
2774 | break; | |
2775 | } | |
2776 | I915_WRITE(DP_TP_CTL(port), temp); | |
2777 | ||
5db94019 | 2778 | } else if ((IS_GEN7(dev_priv) && port == PORT_A) || |
6e266956 | 2779 | (HAS_PCH_CPT(dev_priv) && port != PORT_A)) { |
7b13b58a VS |
2780 | *DP &= ~DP_LINK_TRAIN_MASK_CPT; |
2781 | ||
2782 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2783 | case DP_TRAINING_PATTERN_DISABLE: | |
2784 | *DP |= DP_LINK_TRAIN_OFF_CPT; | |
2785 | break; | |
2786 | case DP_TRAINING_PATTERN_1: | |
2787 | *DP |= DP_LINK_TRAIN_PAT_1_CPT; | |
2788 | break; | |
2789 | case DP_TRAINING_PATTERN_2: | |
2790 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; | |
2791 | break; | |
2792 | case DP_TRAINING_PATTERN_3: | |
8b0878a0 | 2793 | DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n"); |
7b13b58a VS |
2794 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
2795 | break; | |
2796 | } | |
2797 | ||
2798 | } else { | |
920a14b2 | 2799 | if (IS_CHERRYVIEW(dev_priv)) |
7b13b58a VS |
2800 | *DP &= ~DP_LINK_TRAIN_MASK_CHV; |
2801 | else | |
2802 | *DP &= ~DP_LINK_TRAIN_MASK; | |
2803 | ||
2804 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2805 | case DP_TRAINING_PATTERN_DISABLE: | |
2806 | *DP |= DP_LINK_TRAIN_OFF; | |
2807 | break; | |
2808 | case DP_TRAINING_PATTERN_1: | |
2809 | *DP |= DP_LINK_TRAIN_PAT_1; | |
2810 | break; | |
2811 | case DP_TRAINING_PATTERN_2: | |
2812 | *DP |= DP_LINK_TRAIN_PAT_2; | |
2813 | break; | |
2814 | case DP_TRAINING_PATTERN_3: | |
920a14b2 | 2815 | if (IS_CHERRYVIEW(dev_priv)) { |
7b13b58a VS |
2816 | *DP |= DP_LINK_TRAIN_PAT_3_CHV; |
2817 | } else { | |
8b0878a0 | 2818 | DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n"); |
7b13b58a VS |
2819 | *DP |= DP_LINK_TRAIN_PAT_2; |
2820 | } | |
2821 | break; | |
2822 | } | |
2823 | } | |
2824 | } | |
2825 | ||
85cb48a1 ML |
2826 | static void intel_dp_enable_port(struct intel_dp *intel_dp, |
2827 | struct intel_crtc_state *old_crtc_state) | |
7b13b58a VS |
2828 | { |
2829 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
fac5e23e | 2830 | struct drm_i915_private *dev_priv = to_i915(dev); |
7b13b58a | 2831 | |
7b13b58a | 2832 | /* enable with pattern 1 (as per spec) */ |
7b13b58a | 2833 | |
8b0878a0 | 2834 | intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1); |
7b713f50 VS |
2835 | |
2836 | /* | |
2837 | * Magic for VLV/CHV. We _must_ first set up the register | |
2838 | * without actually enabling the port, and then do another | |
2839 | * write to enable the port. Otherwise link training will | |
2840 | * fail when the power sequencer is freshly used for this port. | |
2841 | */ | |
2842 | intel_dp->DP |= DP_PORT_EN; | |
85cb48a1 | 2843 | if (old_crtc_state->has_audio) |
6fec7662 | 2844 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
7b713f50 VS |
2845 | |
2846 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); | |
2847 | POSTING_READ(intel_dp->output_reg); | |
580d3811 VS |
2848 | } |
2849 | ||
85cb48a1 | 2850 | static void intel_enable_dp(struct intel_encoder *encoder, |
bbf35e9d ML |
2851 | struct intel_crtc_state *pipe_config, |
2852 | struct drm_connector_state *conn_state) | |
d240f20f | 2853 | { |
e8cb4558 DV |
2854 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2855 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 2856 | struct drm_i915_private *dev_priv = to_i915(dev); |
c1dec79a | 2857 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
e8cb4558 | 2858 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
d6fbdd15 | 2859 | enum pipe pipe = crtc->pipe; |
5d613501 | 2860 | |
0c33d8d7 DV |
2861 | if (WARN_ON(dp_reg & DP_PORT_EN)) |
2862 | return; | |
5d613501 | 2863 | |
093e3f13 VS |
2864 | pps_lock(intel_dp); |
2865 | ||
920a14b2 | 2866 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
093e3f13 VS |
2867 | vlv_init_panel_power_sequencer(intel_dp); |
2868 | ||
85cb48a1 | 2869 | intel_dp_enable_port(intel_dp, pipe_config); |
093e3f13 VS |
2870 | |
2871 | edp_panel_vdd_on(intel_dp); | |
2872 | edp_panel_on(intel_dp); | |
2873 | edp_panel_vdd_off(intel_dp, true); | |
2874 | ||
2875 | pps_unlock(intel_dp); | |
2876 | ||
920a14b2 | 2877 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
e0fce78f VS |
2878 | unsigned int lane_mask = 0x0; |
2879 | ||
920a14b2 | 2880 | if (IS_CHERRYVIEW(dev_priv)) |
85cb48a1 | 2881 | lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count); |
e0fce78f | 2882 | |
9b6de0a1 VS |
2883 | vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp), |
2884 | lane_mask); | |
e0fce78f | 2885 | } |
61234fa5 | 2886 | |
f01eca2e | 2887 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
33a34e4e | 2888 | intel_dp_start_link_train(intel_dp); |
3ab9c637 | 2889 | intel_dp_stop_link_train(intel_dp); |
c1dec79a | 2890 | |
85cb48a1 | 2891 | if (pipe_config->has_audio) { |
c1dec79a | 2892 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", |
d6fbdd15 | 2893 | pipe_name(pipe)); |
bbf35e9d | 2894 | intel_audio_codec_enable(encoder, pipe_config, conn_state); |
c1dec79a | 2895 | } |
ab1f90f9 | 2896 | } |
89b667f8 | 2897 | |
fd6bbda9 ML |
2898 | static void g4x_enable_dp(struct intel_encoder *encoder, |
2899 | struct intel_crtc_state *pipe_config, | |
2900 | struct drm_connector_state *conn_state) | |
ecff4f3b | 2901 | { |
bbf35e9d | 2902 | intel_enable_dp(encoder, pipe_config, conn_state); |
b037d58f | 2903 | intel_edp_backlight_on(pipe_config, conn_state); |
ab1f90f9 | 2904 | } |
89b667f8 | 2905 | |
fd6bbda9 ML |
2906 | static void vlv_enable_dp(struct intel_encoder *encoder, |
2907 | struct intel_crtc_state *pipe_config, | |
2908 | struct drm_connector_state *conn_state) | |
ab1f90f9 | 2909 | { |
828f5c6e JN |
2910 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2911 | ||
b037d58f | 2912 | intel_edp_backlight_on(pipe_config, conn_state); |
b32c6f48 | 2913 | intel_psr_enable(intel_dp); |
d240f20f JB |
2914 | } |
2915 | ||
fd6bbda9 ML |
2916 | static void g4x_pre_enable_dp(struct intel_encoder *encoder, |
2917 | struct intel_crtc_state *pipe_config, | |
2918 | struct drm_connector_state *conn_state) | |
ab1f90f9 JN |
2919 | { |
2920 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
d6fbdd15 | 2921 | enum port port = dp_to_dig_port(intel_dp)->port; |
ab1f90f9 | 2922 | |
85cb48a1 | 2923 | intel_dp_prepare(encoder, pipe_config); |
8ac33ed3 | 2924 | |
d41f1efb | 2925 | /* Only ilk+ has port A */ |
abfce949 | 2926 | if (port == PORT_A) |
85cb48a1 | 2927 | ironlake_edp_pll_on(intel_dp, pipe_config); |
ab1f90f9 JN |
2928 | } |
2929 | ||
83b84597 VS |
2930 | static void vlv_detach_power_sequencer(struct intel_dp *intel_dp) |
2931 | { | |
2932 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
fac5e23e | 2933 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
83b84597 | 2934 | enum pipe pipe = intel_dp->pps_pipe; |
44cb734c | 2935 | i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe); |
83b84597 | 2936 | |
9f2bdb00 VS |
2937 | WARN_ON(intel_dp->active_pipe != INVALID_PIPE); |
2938 | ||
d158694f VS |
2939 | if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) |
2940 | return; | |
2941 | ||
83b84597 VS |
2942 | edp_panel_vdd_off_sync(intel_dp); |
2943 | ||
2944 | /* | |
2945 | * VLV seems to get confused when multiple power seqeuencers | |
2946 | * have the same port selected (even if only one has power/vdd | |
2947 | * enabled). The failure manifests as vlv_wait_port_ready() failing | |
2948 | * CHV on the other hand doesn't seem to mind having the same port | |
2949 | * selected in multiple power seqeuencers, but let's clear the | |
2950 | * port select always when logically disconnecting a power sequencer | |
2951 | * from a port. | |
2952 | */ | |
2953 | DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n", | |
2954 | pipe_name(pipe), port_name(intel_dig_port->port)); | |
2955 | I915_WRITE(pp_on_reg, 0); | |
2956 | POSTING_READ(pp_on_reg); | |
2957 | ||
2958 | intel_dp->pps_pipe = INVALID_PIPE; | |
2959 | } | |
2960 | ||
a4a5d2f8 VS |
2961 | static void vlv_steal_power_sequencer(struct drm_device *dev, |
2962 | enum pipe pipe) | |
2963 | { | |
fac5e23e | 2964 | struct drm_i915_private *dev_priv = to_i915(dev); |
a4a5d2f8 VS |
2965 | struct intel_encoder *encoder; |
2966 | ||
2967 | lockdep_assert_held(&dev_priv->pps_mutex); | |
2968 | ||
19c8054c | 2969 | for_each_intel_encoder(dev, encoder) { |
a4a5d2f8 | 2970 | struct intel_dp *intel_dp; |
773538e8 | 2971 | enum port port; |
a4a5d2f8 | 2972 | |
9f2bdb00 VS |
2973 | if (encoder->type != INTEL_OUTPUT_DP && |
2974 | encoder->type != INTEL_OUTPUT_EDP) | |
a4a5d2f8 VS |
2975 | continue; |
2976 | ||
2977 | intel_dp = enc_to_intel_dp(&encoder->base); | |
773538e8 | 2978 | port = dp_to_dig_port(intel_dp)->port; |
a4a5d2f8 | 2979 | |
9f2bdb00 VS |
2980 | WARN(intel_dp->active_pipe == pipe, |
2981 | "stealing pipe %c power sequencer from active (e)DP port %c\n", | |
2982 | pipe_name(pipe), port_name(port)); | |
2983 | ||
a4a5d2f8 VS |
2984 | if (intel_dp->pps_pipe != pipe) |
2985 | continue; | |
2986 | ||
2987 | DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n", | |
773538e8 | 2988 | pipe_name(pipe), port_name(port)); |
a4a5d2f8 VS |
2989 | |
2990 | /* make sure vdd is off before we steal it */ | |
83b84597 | 2991 | vlv_detach_power_sequencer(intel_dp); |
a4a5d2f8 VS |
2992 | } |
2993 | } | |
2994 | ||
2995 | static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp) | |
2996 | { | |
2997 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
2998 | struct intel_encoder *encoder = &intel_dig_port->base; | |
2999 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 3000 | struct drm_i915_private *dev_priv = to_i915(dev); |
a4a5d2f8 | 3001 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
a4a5d2f8 VS |
3002 | |
3003 | lockdep_assert_held(&dev_priv->pps_mutex); | |
3004 | ||
9f2bdb00 | 3005 | WARN_ON(intel_dp->active_pipe != INVALID_PIPE); |
093e3f13 | 3006 | |
9f2bdb00 VS |
3007 | if (intel_dp->pps_pipe != INVALID_PIPE && |
3008 | intel_dp->pps_pipe != crtc->pipe) { | |
3009 | /* | |
3010 | * If another power sequencer was being used on this | |
3011 | * port previously make sure to turn off vdd there while | |
3012 | * we still have control of it. | |
3013 | */ | |
83b84597 | 3014 | vlv_detach_power_sequencer(intel_dp); |
9f2bdb00 | 3015 | } |
a4a5d2f8 VS |
3016 | |
3017 | /* | |
3018 | * We may be stealing the power | |
3019 | * sequencer from another port. | |
3020 | */ | |
3021 | vlv_steal_power_sequencer(dev, crtc->pipe); | |
3022 | ||
9f2bdb00 VS |
3023 | intel_dp->active_pipe = crtc->pipe; |
3024 | ||
01a7507f | 3025 | if (!intel_dp_is_edp(intel_dp)) |
9f2bdb00 VS |
3026 | return; |
3027 | ||
a4a5d2f8 VS |
3028 | /* now it's all ours */ |
3029 | intel_dp->pps_pipe = crtc->pipe; | |
3030 | ||
3031 | DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n", | |
3032 | pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port)); | |
3033 | ||
3034 | /* init power sequencer on this pipe and port */ | |
36b5f425 | 3035 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
5d5ab2d2 | 3036 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, true); |
a4a5d2f8 VS |
3037 | } |
3038 | ||
fd6bbda9 ML |
3039 | static void vlv_pre_enable_dp(struct intel_encoder *encoder, |
3040 | struct intel_crtc_state *pipe_config, | |
3041 | struct drm_connector_state *conn_state) | |
a4fc5ed6 | 3042 | { |
5f68c275 | 3043 | vlv_phy_pre_encoder_enable(encoder); |
ab1f90f9 | 3044 | |
bbf35e9d | 3045 | intel_enable_dp(encoder, pipe_config, conn_state); |
89b667f8 JB |
3046 | } |
3047 | ||
fd6bbda9 ML |
3048 | static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder, |
3049 | struct intel_crtc_state *pipe_config, | |
3050 | struct drm_connector_state *conn_state) | |
89b667f8 | 3051 | { |
85cb48a1 | 3052 | intel_dp_prepare(encoder, pipe_config); |
8ac33ed3 | 3053 | |
6da2e616 | 3054 | vlv_phy_pre_pll_enable(encoder); |
a4fc5ed6 KP |
3055 | } |
3056 | ||
fd6bbda9 ML |
3057 | static void chv_pre_enable_dp(struct intel_encoder *encoder, |
3058 | struct intel_crtc_state *pipe_config, | |
3059 | struct drm_connector_state *conn_state) | |
e4a1d846 | 3060 | { |
e7d2a717 | 3061 | chv_phy_pre_encoder_enable(encoder); |
e4a1d846 | 3062 | |
bbf35e9d | 3063 | intel_enable_dp(encoder, pipe_config, conn_state); |
b0b33846 VS |
3064 | |
3065 | /* Second common lane will stay alive on its own now */ | |
e7d2a717 | 3066 | chv_phy_release_cl2_override(encoder); |
e4a1d846 CML |
3067 | } |
3068 | ||
fd6bbda9 ML |
3069 | static void chv_dp_pre_pll_enable(struct intel_encoder *encoder, |
3070 | struct intel_crtc_state *pipe_config, | |
3071 | struct drm_connector_state *conn_state) | |
9197c88b | 3072 | { |
85cb48a1 | 3073 | intel_dp_prepare(encoder, pipe_config); |
625695f8 | 3074 | |
419b1b7a | 3075 | chv_phy_pre_pll_enable(encoder); |
9197c88b VS |
3076 | } |
3077 | ||
fd6bbda9 ML |
3078 | static void chv_dp_post_pll_disable(struct intel_encoder *encoder, |
3079 | struct intel_crtc_state *pipe_config, | |
3080 | struct drm_connector_state *conn_state) | |
d6db995f | 3081 | { |
204970b5 | 3082 | chv_phy_post_pll_disable(encoder); |
d6db995f VS |
3083 | } |
3084 | ||
a4fc5ed6 KP |
3085 | /* |
3086 | * Fetch AUX CH registers 0x202 - 0x207 which contain | |
3087 | * link status information | |
3088 | */ | |
94223d04 | 3089 | bool |
93f62dad | 3090 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
a4fc5ed6 | 3091 | { |
9f085ebb L |
3092 | return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status, |
3093 | DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; | |
a4fc5ed6 KP |
3094 | } |
3095 | ||
97da2ef4 NV |
3096 | static bool intel_dp_get_y_cord_status(struct intel_dp *intel_dp) |
3097 | { | |
3098 | uint8_t psr_caps = 0; | |
3099 | ||
9bacd4b1 ID |
3100 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_CAPS, &psr_caps) != 1) |
3101 | return false; | |
97da2ef4 NV |
3102 | return psr_caps & DP_PSR2_SU_Y_COORDINATE_REQUIRED; |
3103 | } | |
3104 | ||
3105 | static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp) | |
3106 | { | |
3107 | uint8_t dprx = 0; | |
3108 | ||
9bacd4b1 ID |
3109 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST, |
3110 | &dprx) != 1) | |
3111 | return false; | |
97da2ef4 NV |
3112 | return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED; |
3113 | } | |
3114 | ||
a76f73dc | 3115 | static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp) |
340c93c0 NV |
3116 | { |
3117 | uint8_t alpm_caps = 0; | |
3118 | ||
9bacd4b1 ID |
3119 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, |
3120 | &alpm_caps) != 1) | |
3121 | return false; | |
340c93c0 NV |
3122 | return alpm_caps & DP_ALPM_CAP; |
3123 | } | |
3124 | ||
1100244e | 3125 | /* These are source-specific values. */ |
94223d04 | 3126 | uint8_t |
1a2eb460 | 3127 | intel_dp_voltage_max(struct intel_dp *intel_dp) |
a4fc5ed6 | 3128 | { |
dd11bc10 | 3129 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
bc7d38a4 | 3130 | enum port port = dp_to_dig_port(intel_dp)->port; |
1a2eb460 | 3131 | |
cc3f90f0 | 3132 | if (IS_GEN9_LP(dev_priv)) |
9314726b | 3133 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
dd11bc10 | 3134 | else if (INTEL_GEN(dev_priv) >= 9) { |
ffe5111e VS |
3135 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
3136 | return intel_ddi_dp_voltage_max(encoder); | |
920a14b2 | 3137 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
bd60018a | 3138 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
5db94019 | 3139 | else if (IS_GEN7(dev_priv) && port == PORT_A) |
bd60018a | 3140 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
6e266956 | 3141 | else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) |
bd60018a | 3142 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
1a2eb460 | 3143 | else |
bd60018a | 3144 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
1a2eb460 KP |
3145 | } |
3146 | ||
94223d04 | 3147 | uint8_t |
1a2eb460 KP |
3148 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) |
3149 | { | |
8652744b | 3150 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
bc7d38a4 | 3151 | enum port port = dp_to_dig_port(intel_dp)->port; |
1a2eb460 | 3152 | |
8652744b | 3153 | if (INTEL_GEN(dev_priv) >= 9) { |
5a9d1f1a DL |
3154 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3155 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: | |
3156 | return DP_TRAIN_PRE_EMPH_LEVEL_3; | |
3157 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
3158 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3159 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
3160 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
7ad14a29 SJ |
3161 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
3162 | return DP_TRAIN_PRE_EMPH_LEVEL_0; | |
5a9d1f1a DL |
3163 | default: |
3164 | return DP_TRAIN_PRE_EMPH_LEVEL_0; | |
3165 | } | |
8652744b | 3166 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
d6c0d722 | 3167 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a SJ |
3168 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3169 | return DP_TRAIN_PRE_EMPH_LEVEL_3; | |
3170 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
3171 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3172 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
3173 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
3174 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: | |
d6c0d722 | 3175 | default: |
bd60018a | 3176 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
d6c0d722 | 3177 | } |
8652744b | 3178 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
e2fa6fba | 3179 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a SJ |
3180 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3181 | return DP_TRAIN_PRE_EMPH_LEVEL_3; | |
3182 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
3183 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3184 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
3185 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
3186 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: | |
e2fa6fba | 3187 | default: |
bd60018a | 3188 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
e2fa6fba | 3189 | } |
8652744b | 3190 | } else if (IS_GEN7(dev_priv) && port == PORT_A) { |
1a2eb460 | 3191 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a SJ |
3192 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3193 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3194 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
3195 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
3196 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
1a2eb460 | 3197 | default: |
bd60018a | 3198 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
1a2eb460 KP |
3199 | } |
3200 | } else { | |
3201 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a SJ |
3202 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3203 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3204 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
3205 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3206 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
3207 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
3208 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: | |
1a2eb460 | 3209 | default: |
bd60018a | 3210 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
1a2eb460 | 3211 | } |
a4fc5ed6 KP |
3212 | } |
3213 | } | |
3214 | ||
5829975c | 3215 | static uint32_t vlv_signal_levels(struct intel_dp *intel_dp) |
e2fa6fba | 3216 | { |
53d98725 | 3217 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
e2fa6fba P |
3218 | unsigned long demph_reg_value, preemph_reg_value, |
3219 | uniqtranscale_reg_value; | |
3220 | uint8_t train_set = intel_dp->train_set[0]; | |
e2fa6fba P |
3221 | |
3222 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { | |
bd60018a | 3223 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
e2fa6fba P |
3224 | preemph_reg_value = 0x0004000; |
3225 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 3226 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
3227 | demph_reg_value = 0x2B405555; |
3228 | uniqtranscale_reg_value = 0x552AB83A; | |
3229 | break; | |
bd60018a | 3230 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e2fa6fba P |
3231 | demph_reg_value = 0x2B404040; |
3232 | uniqtranscale_reg_value = 0x5548B83A; | |
3233 | break; | |
bd60018a | 3234 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e2fa6fba P |
3235 | demph_reg_value = 0x2B245555; |
3236 | uniqtranscale_reg_value = 0x5560B83A; | |
3237 | break; | |
bd60018a | 3238 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
e2fa6fba P |
3239 | demph_reg_value = 0x2B405555; |
3240 | uniqtranscale_reg_value = 0x5598DA3A; | |
3241 | break; | |
3242 | default: | |
3243 | return 0; | |
3244 | } | |
3245 | break; | |
bd60018a | 3246 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
e2fa6fba P |
3247 | preemph_reg_value = 0x0002000; |
3248 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 3249 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
3250 | demph_reg_value = 0x2B404040; |
3251 | uniqtranscale_reg_value = 0x5552B83A; | |
3252 | break; | |
bd60018a | 3253 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e2fa6fba P |
3254 | demph_reg_value = 0x2B404848; |
3255 | uniqtranscale_reg_value = 0x5580B83A; | |
3256 | break; | |
bd60018a | 3257 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e2fa6fba P |
3258 | demph_reg_value = 0x2B404040; |
3259 | uniqtranscale_reg_value = 0x55ADDA3A; | |
3260 | break; | |
3261 | default: | |
3262 | return 0; | |
3263 | } | |
3264 | break; | |
bd60018a | 3265 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
e2fa6fba P |
3266 | preemph_reg_value = 0x0000000; |
3267 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 3268 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
3269 | demph_reg_value = 0x2B305555; |
3270 | uniqtranscale_reg_value = 0x5570B83A; | |
3271 | break; | |
bd60018a | 3272 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e2fa6fba P |
3273 | demph_reg_value = 0x2B2B4040; |
3274 | uniqtranscale_reg_value = 0x55ADDA3A; | |
3275 | break; | |
3276 | default: | |
3277 | return 0; | |
3278 | } | |
3279 | break; | |
bd60018a | 3280 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
e2fa6fba P |
3281 | preemph_reg_value = 0x0006000; |
3282 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 3283 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
3284 | demph_reg_value = 0x1B405555; |
3285 | uniqtranscale_reg_value = 0x55ADDA3A; | |
3286 | break; | |
3287 | default: | |
3288 | return 0; | |
3289 | } | |
3290 | break; | |
3291 | default: | |
3292 | return 0; | |
3293 | } | |
3294 | ||
53d98725 ACO |
3295 | vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value, |
3296 | uniqtranscale_reg_value, 0); | |
e2fa6fba P |
3297 | |
3298 | return 0; | |
3299 | } | |
3300 | ||
5829975c | 3301 | static uint32_t chv_signal_levels(struct intel_dp *intel_dp) |
e4a1d846 | 3302 | { |
b7fa22d8 ACO |
3303 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
3304 | u32 deemph_reg_value, margin_reg_value; | |
3305 | bool uniq_trans_scale = false; | |
e4a1d846 | 3306 | uint8_t train_set = intel_dp->train_set[0]; |
e4a1d846 CML |
3307 | |
3308 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { | |
bd60018a | 3309 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
e4a1d846 | 3310 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3311 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3312 | deemph_reg_value = 128; |
3313 | margin_reg_value = 52; | |
3314 | break; | |
bd60018a | 3315 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e4a1d846 CML |
3316 | deemph_reg_value = 128; |
3317 | margin_reg_value = 77; | |
3318 | break; | |
bd60018a | 3319 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e4a1d846 CML |
3320 | deemph_reg_value = 128; |
3321 | margin_reg_value = 102; | |
3322 | break; | |
bd60018a | 3323 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
e4a1d846 CML |
3324 | deemph_reg_value = 128; |
3325 | margin_reg_value = 154; | |
b7fa22d8 | 3326 | uniq_trans_scale = true; |
e4a1d846 CML |
3327 | break; |
3328 | default: | |
3329 | return 0; | |
3330 | } | |
3331 | break; | |
bd60018a | 3332 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
e4a1d846 | 3333 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3334 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3335 | deemph_reg_value = 85; |
3336 | margin_reg_value = 78; | |
3337 | break; | |
bd60018a | 3338 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e4a1d846 CML |
3339 | deemph_reg_value = 85; |
3340 | margin_reg_value = 116; | |
3341 | break; | |
bd60018a | 3342 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e4a1d846 CML |
3343 | deemph_reg_value = 85; |
3344 | margin_reg_value = 154; | |
3345 | break; | |
3346 | default: | |
3347 | return 0; | |
3348 | } | |
3349 | break; | |
bd60018a | 3350 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
e4a1d846 | 3351 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3352 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3353 | deemph_reg_value = 64; |
3354 | margin_reg_value = 104; | |
3355 | break; | |
bd60018a | 3356 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e4a1d846 CML |
3357 | deemph_reg_value = 64; |
3358 | margin_reg_value = 154; | |
3359 | break; | |
3360 | default: | |
3361 | return 0; | |
3362 | } | |
3363 | break; | |
bd60018a | 3364 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
e4a1d846 | 3365 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3366 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3367 | deemph_reg_value = 43; |
3368 | margin_reg_value = 154; | |
3369 | break; | |
3370 | default: | |
3371 | return 0; | |
3372 | } | |
3373 | break; | |
3374 | default: | |
3375 | return 0; | |
3376 | } | |
3377 | ||
b7fa22d8 ACO |
3378 | chv_set_phy_signal_level(encoder, deemph_reg_value, |
3379 | margin_reg_value, uniq_trans_scale); | |
e4a1d846 CML |
3380 | |
3381 | return 0; | |
3382 | } | |
3383 | ||
a4fc5ed6 | 3384 | static uint32_t |
5829975c | 3385 | gen4_signal_levels(uint8_t train_set) |
a4fc5ed6 | 3386 | { |
3cf2efb1 | 3387 | uint32_t signal_levels = 0; |
a4fc5ed6 | 3388 | |
3cf2efb1 | 3389 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3390 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
a4fc5ed6 KP |
3391 | default: |
3392 | signal_levels |= DP_VOLTAGE_0_4; | |
3393 | break; | |
bd60018a | 3394 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
a4fc5ed6 KP |
3395 | signal_levels |= DP_VOLTAGE_0_6; |
3396 | break; | |
bd60018a | 3397 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
a4fc5ed6 KP |
3398 | signal_levels |= DP_VOLTAGE_0_8; |
3399 | break; | |
bd60018a | 3400 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
a4fc5ed6 KP |
3401 | signal_levels |= DP_VOLTAGE_1_2; |
3402 | break; | |
3403 | } | |
3cf2efb1 | 3404 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
bd60018a | 3405 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
a4fc5ed6 KP |
3406 | default: |
3407 | signal_levels |= DP_PRE_EMPHASIS_0; | |
3408 | break; | |
bd60018a | 3409 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
a4fc5ed6 KP |
3410 | signal_levels |= DP_PRE_EMPHASIS_3_5; |
3411 | break; | |
bd60018a | 3412 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
a4fc5ed6 KP |
3413 | signal_levels |= DP_PRE_EMPHASIS_6; |
3414 | break; | |
bd60018a | 3415 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
a4fc5ed6 KP |
3416 | signal_levels |= DP_PRE_EMPHASIS_9_5; |
3417 | break; | |
3418 | } | |
3419 | return signal_levels; | |
3420 | } | |
3421 | ||
e3421a18 ZW |
3422 | /* Gen6's DP voltage swing and pre-emphasis control */ |
3423 | static uint32_t | |
5829975c | 3424 | gen6_edp_signal_levels(uint8_t train_set) |
e3421a18 | 3425 | { |
3c5a62b5 YL |
3426 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
3427 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
3428 | switch (signal_levels) { | |
bd60018a SJ |
3429 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3430 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: | |
3c5a62b5 | 3431 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
bd60018a | 3432 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3c5a62b5 | 3433 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; |
bd60018a SJ |
3434 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
3435 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: | |
3c5a62b5 | 3436 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; |
bd60018a SJ |
3437 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3438 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: | |
3c5a62b5 | 3439 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; |
bd60018a SJ |
3440 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3441 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: | |
3c5a62b5 | 3442 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; |
e3421a18 | 3443 | default: |
3c5a62b5 YL |
3444 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
3445 | "0x%x\n", signal_levels); | |
3446 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; | |
e3421a18 ZW |
3447 | } |
3448 | } | |
3449 | ||
1a2eb460 KP |
3450 | /* Gen7's DP voltage swing and pre-emphasis control */ |
3451 | static uint32_t | |
5829975c | 3452 | gen7_edp_signal_levels(uint8_t train_set) |
1a2eb460 KP |
3453 | { |
3454 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | | |
3455 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
3456 | switch (signal_levels) { | |
bd60018a | 3457 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
1a2eb460 | 3458 | return EDP_LINK_TRAIN_400MV_0DB_IVB; |
bd60018a | 3459 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
1a2eb460 | 3460 | return EDP_LINK_TRAIN_400MV_3_5DB_IVB; |
bd60018a | 3461 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
1a2eb460 KP |
3462 | return EDP_LINK_TRAIN_400MV_6DB_IVB; |
3463 | ||
bd60018a | 3464 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
1a2eb460 | 3465 | return EDP_LINK_TRAIN_600MV_0DB_IVB; |
bd60018a | 3466 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
1a2eb460 KP |
3467 | return EDP_LINK_TRAIN_600MV_3_5DB_IVB; |
3468 | ||
bd60018a | 3469 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
1a2eb460 | 3470 | return EDP_LINK_TRAIN_800MV_0DB_IVB; |
bd60018a | 3471 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
1a2eb460 KP |
3472 | return EDP_LINK_TRAIN_800MV_3_5DB_IVB; |
3473 | ||
3474 | default: | |
3475 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" | |
3476 | "0x%x\n", signal_levels); | |
3477 | return EDP_LINK_TRAIN_500MV_0DB_IVB; | |
3478 | } | |
3479 | } | |
3480 | ||
94223d04 | 3481 | void |
f4eb692e | 3482 | intel_dp_set_signal_levels(struct intel_dp *intel_dp) |
f0a3424e PZ |
3483 | { |
3484 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
bc7d38a4 | 3485 | enum port port = intel_dig_port->port; |
f0a3424e | 3486 | struct drm_device *dev = intel_dig_port->base.base.dev; |
b905a915 | 3487 | struct drm_i915_private *dev_priv = to_i915(dev); |
f8896f5d | 3488 | uint32_t signal_levels, mask = 0; |
f0a3424e PZ |
3489 | uint8_t train_set = intel_dp->train_set[0]; |
3490 | ||
4f8036a2 | 3491 | if (HAS_DDI(dev_priv)) { |
f8896f5d DW |
3492 | signal_levels = ddi_signal_levels(intel_dp); |
3493 | ||
cf54ca8b | 3494 | if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv)) |
f8896f5d DW |
3495 | signal_levels = 0; |
3496 | else | |
3497 | mask = DDI_BUF_EMP_MASK; | |
920a14b2 | 3498 | } else if (IS_CHERRYVIEW(dev_priv)) { |
5829975c | 3499 | signal_levels = chv_signal_levels(intel_dp); |
11a914c2 | 3500 | } else if (IS_VALLEYVIEW(dev_priv)) { |
5829975c | 3501 | signal_levels = vlv_signal_levels(intel_dp); |
5db94019 | 3502 | } else if (IS_GEN7(dev_priv) && port == PORT_A) { |
5829975c | 3503 | signal_levels = gen7_edp_signal_levels(train_set); |
f0a3424e | 3504 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; |
5db94019 | 3505 | } else if (IS_GEN6(dev_priv) && port == PORT_A) { |
5829975c | 3506 | signal_levels = gen6_edp_signal_levels(train_set); |
f0a3424e PZ |
3507 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; |
3508 | } else { | |
5829975c | 3509 | signal_levels = gen4_signal_levels(train_set); |
f0a3424e PZ |
3510 | mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; |
3511 | } | |
3512 | ||
96fb9f9b VK |
3513 | if (mask) |
3514 | DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); | |
3515 | ||
3516 | DRM_DEBUG_KMS("Using vswing level %d\n", | |
3517 | train_set & DP_TRAIN_VOLTAGE_SWING_MASK); | |
3518 | DRM_DEBUG_KMS("Using pre-emphasis level %d\n", | |
3519 | (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> | |
3520 | DP_TRAIN_PRE_EMPHASIS_SHIFT); | |
f0a3424e | 3521 | |
f4eb692e | 3522 | intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels; |
b905a915 ACO |
3523 | |
3524 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); | |
3525 | POSTING_READ(intel_dp->output_reg); | |
f0a3424e PZ |
3526 | } |
3527 | ||
94223d04 | 3528 | void |
e9c176d5 ACO |
3529 | intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, |
3530 | uint8_t dp_train_pat) | |
a4fc5ed6 | 3531 | { |
174edf1f | 3532 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
90a6b7b0 VS |
3533 | struct drm_i915_private *dev_priv = |
3534 | to_i915(intel_dig_port->base.base.dev); | |
a4fc5ed6 | 3535 | |
f4eb692e | 3536 | _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat); |
47ea7542 | 3537 | |
f4eb692e | 3538 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
ea5b213a | 3539 | POSTING_READ(intel_dp->output_reg); |
e9c176d5 ACO |
3540 | } |
3541 | ||
94223d04 | 3542 | void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) |
3ab9c637 ID |
3543 | { |
3544 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
3545 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 3546 | struct drm_i915_private *dev_priv = to_i915(dev); |
3ab9c637 ID |
3547 | enum port port = intel_dig_port->port; |
3548 | uint32_t val; | |
3549 | ||
4f8036a2 | 3550 | if (!HAS_DDI(dev_priv)) |
3ab9c637 ID |
3551 | return; |
3552 | ||
3553 | val = I915_READ(DP_TP_CTL(port)); | |
3554 | val &= ~DP_TP_CTL_LINK_TRAIN_MASK; | |
3555 | val |= DP_TP_CTL_LINK_TRAIN_IDLE; | |
3556 | I915_WRITE(DP_TP_CTL(port), val); | |
3557 | ||
3558 | /* | |
3559 | * On PORT_A we can have only eDP in SST mode. There the only reason | |
3560 | * we need to set idle transmission mode is to work around a HW issue | |
3561 | * where we enable the pipe while not in idle link-training mode. | |
3562 | * In this case there is requirement to wait for a minimum number of | |
3563 | * idle patterns to be sent. | |
3564 | */ | |
3565 | if (port == PORT_A) | |
3566 | return; | |
3567 | ||
a767017f CW |
3568 | if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port), |
3569 | DP_TP_STATUS_IDLE_DONE, | |
3570 | DP_TP_STATUS_IDLE_DONE, | |
3571 | 1)) | |
3ab9c637 ID |
3572 | DRM_ERROR("Timed out waiting for DP idle patterns\n"); |
3573 | } | |
3574 | ||
a4fc5ed6 | 3575 | static void |
ea5b213a | 3576 | intel_dp_link_down(struct intel_dp *intel_dp) |
a4fc5ed6 | 3577 | { |
da63a9f2 | 3578 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1612c8bd | 3579 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); |
bc7d38a4 | 3580 | enum port port = intel_dig_port->port; |
da63a9f2 | 3581 | struct drm_device *dev = intel_dig_port->base.base.dev; |
fac5e23e | 3582 | struct drm_i915_private *dev_priv = to_i915(dev); |
ea5b213a | 3583 | uint32_t DP = intel_dp->DP; |
a4fc5ed6 | 3584 | |
4f8036a2 | 3585 | if (WARN_ON(HAS_DDI(dev_priv))) |
c19b0669 PZ |
3586 | return; |
3587 | ||
0c33d8d7 | 3588 | if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) |
1b39d6f3 CW |
3589 | return; |
3590 | ||
28c97730 | 3591 | DRM_DEBUG_KMS("\n"); |
32f9d658 | 3592 | |
5db94019 | 3593 | if ((IS_GEN7(dev_priv) && port == PORT_A) || |
6e266956 | 3594 | (HAS_PCH_CPT(dev_priv) && port != PORT_A)) { |
e3421a18 | 3595 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
1612c8bd | 3596 | DP |= DP_LINK_TRAIN_PAT_IDLE_CPT; |
e3421a18 | 3597 | } else { |
920a14b2 | 3598 | if (IS_CHERRYVIEW(dev_priv)) |
aad3d14d VS |
3599 | DP &= ~DP_LINK_TRAIN_MASK_CHV; |
3600 | else | |
3601 | DP &= ~DP_LINK_TRAIN_MASK; | |
1612c8bd | 3602 | DP |= DP_LINK_TRAIN_PAT_IDLE; |
e3421a18 | 3603 | } |
1612c8bd | 3604 | I915_WRITE(intel_dp->output_reg, DP); |
fe255d00 | 3605 | POSTING_READ(intel_dp->output_reg); |
5eb08b69 | 3606 | |
1612c8bd VS |
3607 | DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); |
3608 | I915_WRITE(intel_dp->output_reg, DP); | |
3609 | POSTING_READ(intel_dp->output_reg); | |
3610 | ||
3611 | /* | |
3612 | * HW workaround for IBX, we need to move the port | |
3613 | * to transcoder A after disabling it to allow the | |
3614 | * matching HDMI port to be enabled on transcoder A. | |
3615 | */ | |
6e266956 | 3616 | if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) { |
0c241d5b VS |
3617 | /* |
3618 | * We get CPU/PCH FIFO underruns on the other pipe when | |
3619 | * doing the workaround. Sweep them under the rug. | |
3620 | */ | |
3621 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
3622 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
3623 | ||
1612c8bd VS |
3624 | /* always enable with pattern 1 (as per spec) */ |
3625 | DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK); | |
3626 | DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1; | |
3627 | I915_WRITE(intel_dp->output_reg, DP); | |
3628 | POSTING_READ(intel_dp->output_reg); | |
3629 | ||
3630 | DP &= ~DP_PORT_EN; | |
5bddd17f | 3631 | I915_WRITE(intel_dp->output_reg, DP); |
0ca09685 | 3632 | POSTING_READ(intel_dp->output_reg); |
0c241d5b | 3633 | |
0f0f74bc | 3634 | intel_wait_for_vblank_if_active(dev_priv, PIPE_A); |
0c241d5b VS |
3635 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
3636 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); | |
5bddd17f EA |
3637 | } |
3638 | ||
f01eca2e | 3639 | msleep(intel_dp->panel_power_down_delay); |
6fec7662 VS |
3640 | |
3641 | intel_dp->DP = DP; | |
9f2bdb00 VS |
3642 | |
3643 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { | |
3644 | pps_lock(intel_dp); | |
3645 | intel_dp->active_pipe = INVALID_PIPE; | |
3646 | pps_unlock(intel_dp); | |
3647 | } | |
a4fc5ed6 KP |
3648 | } |
3649 | ||
24e807e7 | 3650 | bool |
fe5a66f9 | 3651 | intel_dp_read_dpcd(struct intel_dp *intel_dp) |
92fd8fd1 | 3652 | { |
9f085ebb L |
3653 | if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd, |
3654 | sizeof(intel_dp->dpcd)) < 0) | |
edb39244 | 3655 | return false; /* aux transfer failed */ |
92fd8fd1 | 3656 | |
a8e98153 | 3657 | DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd); |
577c7a50 | 3658 | |
fe5a66f9 VS |
3659 | return intel_dp->dpcd[DP_DPCD_REV] != 0; |
3660 | } | |
edb39244 | 3661 | |
fe5a66f9 VS |
3662 | static bool |
3663 | intel_edp_init_dpcd(struct intel_dp *intel_dp) | |
3664 | { | |
3665 | struct drm_i915_private *dev_priv = | |
3666 | to_i915(dp_to_dig_port(intel_dp)->base.base.dev); | |
30d9aa42 | 3667 | |
fe5a66f9 VS |
3668 | /* this function is meant to be called only once */ |
3669 | WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0); | |
30d9aa42 | 3670 | |
fe5a66f9 | 3671 | if (!intel_dp_read_dpcd(intel_dp)) |
30d9aa42 SS |
3672 | return false; |
3673 | ||
84c36753 JN |
3674 | drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, |
3675 | drm_dp_is_branch(intel_dp->dpcd)); | |
12a47a42 | 3676 | |
fe5a66f9 VS |
3677 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) |
3678 | dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] & | |
3679 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; | |
474d1ec4 | 3680 | |
fe5a66f9 VS |
3681 | /* Check if the panel supports PSR */ |
3682 | drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, | |
3683 | intel_dp->psr_dpcd, | |
3684 | sizeof(intel_dp->psr_dpcd)); | |
3685 | if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { | |
3686 | dev_priv->psr.sink_support = true; | |
3687 | DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); | |
3688 | } | |
86ee27b5 | 3689 | |
fe5a66f9 VS |
3690 | if (INTEL_GEN(dev_priv) >= 9 && |
3691 | (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) { | |
3692 | uint8_t frame_sync_cap; | |
3693 | ||
3694 | dev_priv->psr.sink_support = true; | |
9bacd4b1 ID |
3695 | if (drm_dp_dpcd_readb(&intel_dp->aux, |
3696 | DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP, | |
3697 | &frame_sync_cap) != 1) | |
3698 | frame_sync_cap = 0; | |
fe5a66f9 VS |
3699 | dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false; |
3700 | /* PSR2 needs frame sync as well */ | |
3701 | dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync; | |
3702 | DRM_DEBUG_KMS("PSR2 %s on sink", | |
3703 | dev_priv->psr.psr2_support ? "supported" : "not supported"); | |
97da2ef4 NV |
3704 | |
3705 | if (dev_priv->psr.psr2_support) { | |
3706 | dev_priv->psr.y_cord_support = | |
3707 | intel_dp_get_y_cord_status(intel_dp); | |
3708 | dev_priv->psr.colorimetry_support = | |
3709 | intel_dp_get_colorimetry_status(intel_dp); | |
340c93c0 NV |
3710 | dev_priv->psr.alpm = |
3711 | intel_dp_get_alpm_status(intel_dp); | |
97da2ef4 NV |
3712 | } |
3713 | ||
50003939 JN |
3714 | } |
3715 | ||
41d444df JN |
3716 | /* |
3717 | * Read the eDP display control registers. | |
3718 | * | |
3719 | * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in | |
3720 | * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it | |
3721 | * set, but require eDP 1.4+ detection (e.g. for supported link rates | |
3722 | * method). The display control registers should read zero if they're | |
3723 | * not supported anyway. | |
3724 | */ | |
3725 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV, | |
f7170e2e DC |
3726 | intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) == |
3727 | sizeof(intel_dp->edp_dpcd)) | |
fe5a66f9 VS |
3728 | DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd), |
3729 | intel_dp->edp_dpcd); | |
06ea66b6 | 3730 | |
fc0f8e25 | 3731 | /* Intermediate frequency support */ |
fe5a66f9 | 3732 | if (intel_dp->edp_dpcd[0] >= 0x03) { /* eDp v1.4 or higher */ |
94ca719e | 3733 | __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; |
ea2d8a42 VS |
3734 | int i; |
3735 | ||
9f085ebb L |
3736 | drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES, |
3737 | sink_rates, sizeof(sink_rates)); | |
ea2d8a42 | 3738 | |
94ca719e VS |
3739 | for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { |
3740 | int val = le16_to_cpu(sink_rates[i]); | |
ea2d8a42 VS |
3741 | |
3742 | if (val == 0) | |
3743 | break; | |
3744 | ||
fd81c44e DP |
3745 | /* Value read multiplied by 200kHz gives the per-lane |
3746 | * link rate in kHz. The source rates are, however, | |
3747 | * stored in terms of LS_Clk kHz. The full conversion | |
3748 | * back to symbols is | |
3749 | * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte) | |
3750 | */ | |
af77b974 | 3751 | intel_dp->sink_rates[i] = (val * 200) / 10; |
ea2d8a42 | 3752 | } |
94ca719e | 3753 | intel_dp->num_sink_rates = i; |
fc0f8e25 | 3754 | } |
0336400e | 3755 | |
68f357cb JN |
3756 | if (intel_dp->num_sink_rates) |
3757 | intel_dp->use_rate_select = true; | |
3758 | else | |
3759 | intel_dp_set_sink_rates(intel_dp); | |
3760 | ||
975ee5fc JN |
3761 | intel_dp_set_common_rates(intel_dp); |
3762 | ||
fe5a66f9 VS |
3763 | return true; |
3764 | } | |
3765 | ||
3766 | ||
3767 | static bool | |
3768 | intel_dp_get_dpcd(struct intel_dp *intel_dp) | |
3769 | { | |
27dbefb9 JN |
3770 | u8 sink_count; |
3771 | ||
fe5a66f9 VS |
3772 | if (!intel_dp_read_dpcd(intel_dp)) |
3773 | return false; | |
3774 | ||
68f357cb | 3775 | /* Don't clobber cached eDP rates. */ |
01a7507f | 3776 | if (!intel_dp_is_edp(intel_dp)) { |
68f357cb | 3777 | intel_dp_set_sink_rates(intel_dp); |
975ee5fc JN |
3778 | intel_dp_set_common_rates(intel_dp); |
3779 | } | |
68f357cb | 3780 | |
27dbefb9 | 3781 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT, &sink_count) <= 0) |
fe5a66f9 VS |
3782 | return false; |
3783 | ||
3784 | /* | |
3785 | * Sink count can change between short pulse hpd hence | |
3786 | * a member variable in intel_dp will track any changes | |
3787 | * between short pulse interrupts. | |
3788 | */ | |
27dbefb9 | 3789 | intel_dp->sink_count = DP_GET_SINK_COUNT(sink_count); |
fe5a66f9 VS |
3790 | |
3791 | /* | |
3792 | * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that | |
3793 | * a dongle is present but no display. Unless we require to know | |
3794 | * if a dongle is present or not, we don't need to update | |
3795 | * downstream port information. So, an early return here saves | |
3796 | * time from performing other operations which are not required. | |
3797 | */ | |
01a7507f | 3798 | if (!intel_dp_is_edp(intel_dp) && !intel_dp->sink_count) |
fe5a66f9 | 3799 | return false; |
0336400e | 3800 | |
c726ad01 | 3801 | if (!drm_dp_is_branch(intel_dp->dpcd)) |
edb39244 AJ |
3802 | return true; /* native DP sink */ |
3803 | ||
3804 | if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) | |
3805 | return true; /* no per-port downstream info */ | |
3806 | ||
9f085ebb L |
3807 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, |
3808 | intel_dp->downstream_ports, | |
3809 | DP_MAX_DOWNSTREAM_PORTS) < 0) | |
edb39244 AJ |
3810 | return false; /* downstream port status fetch failed */ |
3811 | ||
3812 | return true; | |
92fd8fd1 KP |
3813 | } |
3814 | ||
0e32b39c | 3815 | static bool |
c4e3170a | 3816 | intel_dp_can_mst(struct intel_dp *intel_dp) |
0e32b39c | 3817 | { |
010b9b39 | 3818 | u8 mstm_cap; |
0e32b39c | 3819 | |
7cc96139 NS |
3820 | if (!i915.enable_dp_mst) |
3821 | return false; | |
3822 | ||
0e32b39c DA |
3823 | if (!intel_dp->can_mst) |
3824 | return false; | |
3825 | ||
3826 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x12) | |
3827 | return false; | |
3828 | ||
010b9b39 | 3829 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1) |
c4e3170a | 3830 | return false; |
0e32b39c | 3831 | |
010b9b39 | 3832 | return mstm_cap & DP_MST_CAP; |
c4e3170a VS |
3833 | } |
3834 | ||
3835 | static void | |
3836 | intel_dp_configure_mst(struct intel_dp *intel_dp) | |
3837 | { | |
3838 | if (!i915.enable_dp_mst) | |
3839 | return; | |
3840 | ||
3841 | if (!intel_dp->can_mst) | |
3842 | return; | |
3843 | ||
3844 | intel_dp->is_mst = intel_dp_can_mst(intel_dp); | |
3845 | ||
3846 | if (intel_dp->is_mst) | |
3847 | DRM_DEBUG_KMS("Sink is MST capable\n"); | |
3848 | else | |
3849 | DRM_DEBUG_KMS("Sink is not MST capable\n"); | |
3850 | ||
3851 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, | |
3852 | intel_dp->is_mst); | |
0e32b39c DA |
3853 | } |
3854 | ||
e5a1cab5 | 3855 | static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp) |
d2e216d0 | 3856 | { |
082dcc7c | 3857 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
0f0f74bc | 3858 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
082dcc7c | 3859 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
ad9dc91b | 3860 | u8 buf; |
e5a1cab5 | 3861 | int ret = 0; |
c6297843 RV |
3862 | int count = 0; |
3863 | int attempts = 10; | |
d2e216d0 | 3864 | |
082dcc7c RV |
3865 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) { |
3866 | DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); | |
e5a1cab5 RV |
3867 | ret = -EIO; |
3868 | goto out; | |
4373f0f2 PZ |
3869 | } |
3870 | ||
082dcc7c | 3871 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
e5a1cab5 | 3872 | buf & ~DP_TEST_SINK_START) < 0) { |
082dcc7c | 3873 | DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); |
e5a1cab5 RV |
3874 | ret = -EIO; |
3875 | goto out; | |
3876 | } | |
d2e216d0 | 3877 | |
c6297843 | 3878 | do { |
0f0f74bc | 3879 | intel_wait_for_vblank(dev_priv, intel_crtc->pipe); |
c6297843 RV |
3880 | |
3881 | if (drm_dp_dpcd_readb(&intel_dp->aux, | |
3882 | DP_TEST_SINK_MISC, &buf) < 0) { | |
3883 | ret = -EIO; | |
3884 | goto out; | |
3885 | } | |
3886 | count = buf & DP_TEST_COUNT_MASK; | |
3887 | } while (--attempts && count); | |
3888 | ||
3889 | if (attempts == 0) { | |
dc5a9037 | 3890 | DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n"); |
c6297843 RV |
3891 | ret = -ETIMEDOUT; |
3892 | } | |
3893 | ||
e5a1cab5 | 3894 | out: |
082dcc7c | 3895 | hsw_enable_ips(intel_crtc); |
e5a1cab5 | 3896 | return ret; |
082dcc7c RV |
3897 | } |
3898 | ||
3899 | static int intel_dp_sink_crc_start(struct intel_dp *intel_dp) | |
3900 | { | |
3901 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
0f0f74bc | 3902 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
082dcc7c RV |
3903 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
3904 | u8 buf; | |
e5a1cab5 RV |
3905 | int ret; |
3906 | ||
082dcc7c RV |
3907 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0) |
3908 | return -EIO; | |
3909 | ||
3910 | if (!(buf & DP_TEST_CRC_SUPPORTED)) | |
3911 | return -ENOTTY; | |
3912 | ||
3913 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) | |
3914 | return -EIO; | |
3915 | ||
6d8175da RV |
3916 | if (buf & DP_TEST_SINK_START) { |
3917 | ret = intel_dp_sink_crc_stop(intel_dp); | |
3918 | if (ret) | |
3919 | return ret; | |
3920 | } | |
3921 | ||
082dcc7c | 3922 | hsw_disable_ips(intel_crtc); |
1dda5f93 | 3923 | |
9d1a1031 | 3924 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
082dcc7c RV |
3925 | buf | DP_TEST_SINK_START) < 0) { |
3926 | hsw_enable_ips(intel_crtc); | |
3927 | return -EIO; | |
4373f0f2 PZ |
3928 | } |
3929 | ||
0f0f74bc | 3930 | intel_wait_for_vblank(dev_priv, intel_crtc->pipe); |
082dcc7c RV |
3931 | return 0; |
3932 | } | |
3933 | ||
3934 | int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc) | |
3935 | { | |
3936 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
0f0f74bc | 3937 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
082dcc7c RV |
3938 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
3939 | u8 buf; | |
621d4c76 | 3940 | int count, ret; |
082dcc7c | 3941 | int attempts = 6; |
082dcc7c RV |
3942 | |
3943 | ret = intel_dp_sink_crc_start(intel_dp); | |
3944 | if (ret) | |
3945 | return ret; | |
3946 | ||
ad9dc91b | 3947 | do { |
0f0f74bc | 3948 | intel_wait_for_vblank(dev_priv, intel_crtc->pipe); |
621d4c76 | 3949 | |
1dda5f93 | 3950 | if (drm_dp_dpcd_readb(&intel_dp->aux, |
4373f0f2 PZ |
3951 | DP_TEST_SINK_MISC, &buf) < 0) { |
3952 | ret = -EIO; | |
afe0d67e | 3953 | goto stop; |
4373f0f2 | 3954 | } |
621d4c76 | 3955 | count = buf & DP_TEST_COUNT_MASK; |
aabc95dc | 3956 | |
7e38eeff | 3957 | } while (--attempts && count == 0); |
ad9dc91b RV |
3958 | |
3959 | if (attempts == 0) { | |
7e38eeff RV |
3960 | DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n"); |
3961 | ret = -ETIMEDOUT; | |
3962 | goto stop; | |
3963 | } | |
3964 | ||
3965 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) { | |
3966 | ret = -EIO; | |
3967 | goto stop; | |
ad9dc91b | 3968 | } |
d2e216d0 | 3969 | |
afe0d67e | 3970 | stop: |
082dcc7c | 3971 | intel_dp_sink_crc_stop(intel_dp); |
4373f0f2 | 3972 | return ret; |
d2e216d0 RV |
3973 | } |
3974 | ||
a60f0e38 JB |
3975 | static bool |
3976 | intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) | |
3977 | { | |
010b9b39 JN |
3978 | return drm_dp_dpcd_readb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, |
3979 | sink_irq_vector) == 1; | |
a60f0e38 JB |
3980 | } |
3981 | ||
0e32b39c DA |
3982 | static bool |
3983 | intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) | |
3984 | { | |
3985 | int ret; | |
3986 | ||
9f085ebb | 3987 | ret = drm_dp_dpcd_read(&intel_dp->aux, |
0e32b39c DA |
3988 | DP_SINK_COUNT_ESI, |
3989 | sink_irq_vector, 14); | |
3990 | if (ret != 14) | |
3991 | return false; | |
3992 | ||
3993 | return true; | |
3994 | } | |
3995 | ||
c5d5ab7a TP |
3996 | static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp) |
3997 | { | |
da15f7cb MN |
3998 | int status = 0; |
3999 | int min_lane_count = 1; | |
da15f7cb MN |
4000 | int link_rate_index, test_link_rate; |
4001 | uint8_t test_lane_count, test_link_bw; | |
4002 | /* (DP CTS 1.2) | |
4003 | * 4.3.1.11 | |
4004 | */ | |
4005 | /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */ | |
4006 | status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT, | |
4007 | &test_lane_count); | |
4008 | ||
4009 | if (status <= 0) { | |
4010 | DRM_DEBUG_KMS("Lane count read failed\n"); | |
4011 | return DP_TEST_NAK; | |
4012 | } | |
4013 | test_lane_count &= DP_MAX_LANE_COUNT_MASK; | |
4014 | /* Validate the requested lane count */ | |
4015 | if (test_lane_count < min_lane_count || | |
e6c0c64a | 4016 | test_lane_count > intel_dp->max_link_lane_count) |
da15f7cb MN |
4017 | return DP_TEST_NAK; |
4018 | ||
4019 | status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE, | |
4020 | &test_link_bw); | |
4021 | if (status <= 0) { | |
4022 | DRM_DEBUG_KMS("Link Rate read failed\n"); | |
4023 | return DP_TEST_NAK; | |
4024 | } | |
4025 | /* Validate the requested link rate */ | |
4026 | test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw); | |
b1810a74 JN |
4027 | link_rate_index = intel_dp_rate_index(intel_dp->common_rates, |
4028 | intel_dp->num_common_rates, | |
4029 | test_link_rate); | |
da15f7cb MN |
4030 | if (link_rate_index < 0) |
4031 | return DP_TEST_NAK; | |
4032 | ||
4033 | intel_dp->compliance.test_lane_count = test_lane_count; | |
4034 | intel_dp->compliance.test_link_rate = test_link_rate; | |
4035 | ||
4036 | return DP_TEST_ACK; | |
c5d5ab7a TP |
4037 | } |
4038 | ||
4039 | static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp) | |
4040 | { | |
611032bf | 4041 | uint8_t test_pattern; |
010b9b39 | 4042 | uint8_t test_misc; |
611032bf MN |
4043 | __be16 h_width, v_height; |
4044 | int status = 0; | |
4045 | ||
4046 | /* Read the TEST_PATTERN (DP CTS 3.1.5) */ | |
010b9b39 JN |
4047 | status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN, |
4048 | &test_pattern); | |
611032bf MN |
4049 | if (status <= 0) { |
4050 | DRM_DEBUG_KMS("Test pattern read failed\n"); | |
4051 | return DP_TEST_NAK; | |
4052 | } | |
4053 | if (test_pattern != DP_COLOR_RAMP) | |
4054 | return DP_TEST_NAK; | |
4055 | ||
4056 | status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI, | |
4057 | &h_width, 2); | |
4058 | if (status <= 0) { | |
4059 | DRM_DEBUG_KMS("H Width read failed\n"); | |
4060 | return DP_TEST_NAK; | |
4061 | } | |
4062 | ||
4063 | status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI, | |
4064 | &v_height, 2); | |
4065 | if (status <= 0) { | |
4066 | DRM_DEBUG_KMS("V Height read failed\n"); | |
4067 | return DP_TEST_NAK; | |
4068 | } | |
4069 | ||
010b9b39 JN |
4070 | status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0, |
4071 | &test_misc); | |
611032bf MN |
4072 | if (status <= 0) { |
4073 | DRM_DEBUG_KMS("TEST MISC read failed\n"); | |
4074 | return DP_TEST_NAK; | |
4075 | } | |
4076 | if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB) | |
4077 | return DP_TEST_NAK; | |
4078 | if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA) | |
4079 | return DP_TEST_NAK; | |
4080 | switch (test_misc & DP_TEST_BIT_DEPTH_MASK) { | |
4081 | case DP_TEST_BIT_DEPTH_6: | |
4082 | intel_dp->compliance.test_data.bpc = 6; | |
4083 | break; | |
4084 | case DP_TEST_BIT_DEPTH_8: | |
4085 | intel_dp->compliance.test_data.bpc = 8; | |
4086 | break; | |
4087 | default: | |
4088 | return DP_TEST_NAK; | |
4089 | } | |
4090 | ||
4091 | intel_dp->compliance.test_data.video_pattern = test_pattern; | |
4092 | intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width); | |
4093 | intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height); | |
4094 | /* Set test active flag here so userspace doesn't interrupt things */ | |
4095 | intel_dp->compliance.test_active = 1; | |
4096 | ||
4097 | return DP_TEST_ACK; | |
c5d5ab7a TP |
4098 | } |
4099 | ||
4100 | static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp) | |
a60f0e38 | 4101 | { |
b48a5ba9 | 4102 | uint8_t test_result = DP_TEST_ACK; |
559be30c TP |
4103 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
4104 | struct drm_connector *connector = &intel_connector->base; | |
4105 | ||
4106 | if (intel_connector->detect_edid == NULL || | |
ac6f2e29 | 4107 | connector->edid_corrupt || |
559be30c TP |
4108 | intel_dp->aux.i2c_defer_count > 6) { |
4109 | /* Check EDID read for NACKs, DEFERs and corruption | |
4110 | * (DP CTS 1.2 Core r1.1) | |
4111 | * 4.2.2.4 : Failed EDID read, I2C_NAK | |
4112 | * 4.2.2.5 : Failed EDID read, I2C_DEFER | |
4113 | * 4.2.2.6 : EDID corruption detected | |
4114 | * Use failsafe mode for all cases | |
4115 | */ | |
4116 | if (intel_dp->aux.i2c_nack_count > 0 || | |
4117 | intel_dp->aux.i2c_defer_count > 0) | |
4118 | DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n", | |
4119 | intel_dp->aux.i2c_nack_count, | |
4120 | intel_dp->aux.i2c_defer_count); | |
c1617abc | 4121 | intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE; |
559be30c | 4122 | } else { |
f79b468e TS |
4123 | struct edid *block = intel_connector->detect_edid; |
4124 | ||
4125 | /* We have to write the checksum | |
4126 | * of the last block read | |
4127 | */ | |
4128 | block += intel_connector->detect_edid->extensions; | |
4129 | ||
010b9b39 JN |
4130 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM, |
4131 | block->checksum) <= 0) | |
559be30c TP |
4132 | DRM_DEBUG_KMS("Failed to write EDID checksum\n"); |
4133 | ||
4134 | test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE; | |
b48a5ba9 | 4135 | intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED; |
559be30c TP |
4136 | } |
4137 | ||
4138 | /* Set test active flag here so userspace doesn't interrupt things */ | |
c1617abc | 4139 | intel_dp->compliance.test_active = 1; |
559be30c | 4140 | |
c5d5ab7a TP |
4141 | return test_result; |
4142 | } | |
4143 | ||
4144 | static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) | |
a60f0e38 | 4145 | { |
c5d5ab7a TP |
4146 | uint8_t test_result = DP_TEST_NAK; |
4147 | return test_result; | |
4148 | } | |
4149 | ||
4150 | static void intel_dp_handle_test_request(struct intel_dp *intel_dp) | |
4151 | { | |
4152 | uint8_t response = DP_TEST_NAK; | |
5ec63bbd JN |
4153 | uint8_t request = 0; |
4154 | int status; | |
c5d5ab7a | 4155 | |
5ec63bbd | 4156 | status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request); |
c5d5ab7a TP |
4157 | if (status <= 0) { |
4158 | DRM_DEBUG_KMS("Could not read test request from sink\n"); | |
4159 | goto update_status; | |
4160 | } | |
4161 | ||
5ec63bbd | 4162 | switch (request) { |
c5d5ab7a TP |
4163 | case DP_TEST_LINK_TRAINING: |
4164 | DRM_DEBUG_KMS("LINK_TRAINING test requested\n"); | |
c5d5ab7a TP |
4165 | response = intel_dp_autotest_link_training(intel_dp); |
4166 | break; | |
4167 | case DP_TEST_LINK_VIDEO_PATTERN: | |
4168 | DRM_DEBUG_KMS("TEST_PATTERN test requested\n"); | |
c5d5ab7a TP |
4169 | response = intel_dp_autotest_video_pattern(intel_dp); |
4170 | break; | |
4171 | case DP_TEST_LINK_EDID_READ: | |
4172 | DRM_DEBUG_KMS("EDID test requested\n"); | |
c5d5ab7a TP |
4173 | response = intel_dp_autotest_edid(intel_dp); |
4174 | break; | |
4175 | case DP_TEST_LINK_PHY_TEST_PATTERN: | |
4176 | DRM_DEBUG_KMS("PHY_PATTERN test requested\n"); | |
c5d5ab7a TP |
4177 | response = intel_dp_autotest_phy_pattern(intel_dp); |
4178 | break; | |
4179 | default: | |
5ec63bbd | 4180 | DRM_DEBUG_KMS("Invalid test request '%02x'\n", request); |
c5d5ab7a TP |
4181 | break; |
4182 | } | |
4183 | ||
5ec63bbd JN |
4184 | if (response & DP_TEST_ACK) |
4185 | intel_dp->compliance.test_type = request; | |
4186 | ||
c5d5ab7a | 4187 | update_status: |
5ec63bbd | 4188 | status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response); |
c5d5ab7a TP |
4189 | if (status <= 0) |
4190 | DRM_DEBUG_KMS("Could not write test response to sink\n"); | |
a60f0e38 JB |
4191 | } |
4192 | ||
0e32b39c DA |
4193 | static int |
4194 | intel_dp_check_mst_status(struct intel_dp *intel_dp) | |
4195 | { | |
4196 | bool bret; | |
4197 | ||
4198 | if (intel_dp->is_mst) { | |
4199 | u8 esi[16] = { 0 }; | |
4200 | int ret = 0; | |
4201 | int retry; | |
4202 | bool handled; | |
4203 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); | |
4204 | go_again: | |
4205 | if (bret == true) { | |
4206 | ||
4207 | /* check link status - esi[10] = 0x200c */ | |
19e0b4ca | 4208 | if (intel_dp->active_mst_links && |
901c2daf | 4209 | !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) { |
0e32b39c DA |
4210 | DRM_DEBUG_KMS("channel EQ not ok, retraining\n"); |
4211 | intel_dp_start_link_train(intel_dp); | |
0e32b39c DA |
4212 | intel_dp_stop_link_train(intel_dp); |
4213 | } | |
4214 | ||
6f34cc39 | 4215 | DRM_DEBUG_KMS("got esi %3ph\n", esi); |
0e32b39c DA |
4216 | ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled); |
4217 | ||
4218 | if (handled) { | |
4219 | for (retry = 0; retry < 3; retry++) { | |
4220 | int wret; | |
4221 | wret = drm_dp_dpcd_write(&intel_dp->aux, | |
4222 | DP_SINK_COUNT_ESI+1, | |
4223 | &esi[1], 3); | |
4224 | if (wret == 3) { | |
4225 | break; | |
4226 | } | |
4227 | } | |
4228 | ||
4229 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); | |
4230 | if (bret == true) { | |
6f34cc39 | 4231 | DRM_DEBUG_KMS("got esi2 %3ph\n", esi); |
0e32b39c DA |
4232 | goto go_again; |
4233 | } | |
4234 | } else | |
4235 | ret = 0; | |
4236 | ||
4237 | return ret; | |
4238 | } else { | |
4239 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
4240 | DRM_DEBUG_KMS("failed to get ESI - device may have failed\n"); | |
4241 | intel_dp->is_mst = false; | |
4242 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); | |
4243 | /* send a hotplug event */ | |
4244 | drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev); | |
4245 | } | |
4246 | } | |
4247 | return -EINVAL; | |
4248 | } | |
4249 | ||
bfd02b3c VS |
4250 | static void |
4251 | intel_dp_retrain_link(struct intel_dp *intel_dp) | |
4252 | { | |
4253 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; | |
4254 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
4255 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
4256 | ||
4257 | /* Suppress underruns caused by re-training */ | |
4258 | intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); | |
4259 | if (crtc->config->has_pch_encoder) | |
4260 | intel_set_pch_fifo_underrun_reporting(dev_priv, | |
4261 | intel_crtc_pch_transcoder(crtc), false); | |
4262 | ||
4263 | intel_dp_start_link_train(intel_dp); | |
4264 | intel_dp_stop_link_train(intel_dp); | |
4265 | ||
4266 | /* Keep underrun reporting disabled until things are stable */ | |
0f0f74bc | 4267 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
bfd02b3c VS |
4268 | |
4269 | intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); | |
4270 | if (crtc->config->has_pch_encoder) | |
4271 | intel_set_pch_fifo_underrun_reporting(dev_priv, | |
4272 | intel_crtc_pch_transcoder(crtc), true); | |
4273 | } | |
4274 | ||
5c9114d0 SS |
4275 | static void |
4276 | intel_dp_check_link_status(struct intel_dp *intel_dp) | |
4277 | { | |
4278 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; | |
4279 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
4280 | u8 link_status[DP_LINK_STATUS_SIZE]; | |
4281 | ||
4282 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); | |
4283 | ||
4284 | if (!intel_dp_get_link_status(intel_dp, link_status)) { | |
4285 | DRM_ERROR("Failed to get link status\n"); | |
4286 | return; | |
4287 | } | |
4288 | ||
4289 | if (!intel_encoder->base.crtc) | |
4290 | return; | |
4291 | ||
4292 | if (!to_intel_crtc(intel_encoder->base.crtc)->active) | |
4293 | return; | |
4294 | ||
14c562c0 MN |
4295 | /* |
4296 | * Validate the cached values of intel_dp->link_rate and | |
4297 | * intel_dp->lane_count before attempting to retrain. | |
4298 | */ | |
4299 | if (!intel_dp_link_params_valid(intel_dp)) | |
d4cb3fd9 MA |
4300 | return; |
4301 | ||
da15f7cb MN |
4302 | /* Retrain if Channel EQ or CR not ok */ |
4303 | if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { | |
5c9114d0 SS |
4304 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", |
4305 | intel_encoder->base.name); | |
bfd02b3c VS |
4306 | |
4307 | intel_dp_retrain_link(intel_dp); | |
5c9114d0 SS |
4308 | } |
4309 | } | |
4310 | ||
a4fc5ed6 KP |
4311 | /* |
4312 | * According to DP spec | |
4313 | * 5.1.2: | |
4314 | * 1. Read DPCD | |
4315 | * 2. Configure link according to Receiver Capabilities | |
4316 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 | |
4317 | * 4. Check link status on receipt of hot-plug interrupt | |
39ff747b SS |
4318 | * |
4319 | * intel_dp_short_pulse - handles short pulse interrupts | |
4320 | * when full detection is not required. | |
4321 | * Returns %true if short pulse is handled and full detection | |
4322 | * is NOT required and %false otherwise. | |
a4fc5ed6 | 4323 | */ |
39ff747b | 4324 | static bool |
5c9114d0 | 4325 | intel_dp_short_pulse(struct intel_dp *intel_dp) |
a4fc5ed6 | 4326 | { |
5b215bcf | 4327 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
da15f7cb | 4328 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
65fbb4e7 | 4329 | u8 sink_irq_vector = 0; |
39ff747b SS |
4330 | u8 old_sink_count = intel_dp->sink_count; |
4331 | bool ret; | |
5b215bcf | 4332 | |
4df6960e SS |
4333 | /* |
4334 | * Clearing compliance test variables to allow capturing | |
4335 | * of values for next automated test request. | |
4336 | */ | |
c1617abc | 4337 | memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); |
4df6960e | 4338 | |
39ff747b SS |
4339 | /* |
4340 | * Now read the DPCD to see if it's actually running | |
4341 | * If the current value of sink count doesn't match with | |
4342 | * the value that was stored earlier or dpcd read failed | |
4343 | * we need to do full detection | |
4344 | */ | |
4345 | ret = intel_dp_get_dpcd(intel_dp); | |
4346 | ||
4347 | if ((old_sink_count != intel_dp->sink_count) || !ret) { | |
4348 | /* No need to proceed if we are going to do full detect */ | |
4349 | return false; | |
59cd09e1 JB |
4350 | } |
4351 | ||
a60f0e38 JB |
4352 | /* Try to read the source of the interrupt */ |
4353 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && | |
65fbb4e7 VS |
4354 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) && |
4355 | sink_irq_vector != 0) { | |
a60f0e38 | 4356 | /* Clear interrupt source */ |
9d1a1031 JN |
4357 | drm_dp_dpcd_writeb(&intel_dp->aux, |
4358 | DP_DEVICE_SERVICE_IRQ_VECTOR, | |
4359 | sink_irq_vector); | |
a60f0e38 JB |
4360 | |
4361 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) | |
da15f7cb | 4362 | intel_dp_handle_test_request(intel_dp); |
a60f0e38 JB |
4363 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) |
4364 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); | |
4365 | } | |
4366 | ||
5c9114d0 SS |
4367 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
4368 | intel_dp_check_link_status(intel_dp); | |
4369 | drm_modeset_unlock(&dev->mode_config.connection_mutex); | |
da15f7cb MN |
4370 | if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) { |
4371 | DRM_DEBUG_KMS("Link Training Compliance Test requested\n"); | |
4372 | /* Send a Hotplug Uevent to userspace to start modeset */ | |
4373 | drm_kms_helper_hotplug_event(intel_encoder->base.dev); | |
4374 | } | |
39ff747b SS |
4375 | |
4376 | return true; | |
a4fc5ed6 | 4377 | } |
a4fc5ed6 | 4378 | |
caf9ab24 | 4379 | /* XXX this is probably wrong for multiple downstream ports */ |
71ba9000 | 4380 | static enum drm_connector_status |
26d61aad | 4381 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
71ba9000 | 4382 | { |
e393d0d6 | 4383 | struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp); |
caf9ab24 | 4384 | uint8_t *dpcd = intel_dp->dpcd; |
caf9ab24 AJ |
4385 | uint8_t type; |
4386 | ||
e393d0d6 ID |
4387 | if (lspcon->active) |
4388 | lspcon_resume(lspcon); | |
4389 | ||
caf9ab24 AJ |
4390 | if (!intel_dp_get_dpcd(intel_dp)) |
4391 | return connector_status_disconnected; | |
4392 | ||
01a7507f | 4393 | if (intel_dp_is_edp(intel_dp)) |
1034ce70 SS |
4394 | return connector_status_connected; |
4395 | ||
caf9ab24 | 4396 | /* if there's no downstream port, we're done */ |
c726ad01 | 4397 | if (!drm_dp_is_branch(dpcd)) |
26d61aad | 4398 | return connector_status_connected; |
caf9ab24 AJ |
4399 | |
4400 | /* If we're HPD-aware, SINK_COUNT changes dynamically */ | |
c9ff160b JN |
4401 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
4402 | intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { | |
9d1a1031 | 4403 | |
30d9aa42 SS |
4404 | return intel_dp->sink_count ? |
4405 | connector_status_connected : connector_status_disconnected; | |
caf9ab24 AJ |
4406 | } |
4407 | ||
c4e3170a VS |
4408 | if (intel_dp_can_mst(intel_dp)) |
4409 | return connector_status_connected; | |
4410 | ||
caf9ab24 | 4411 | /* If no HPD, poke DDC gently */ |
0b99836f | 4412 | if (drm_probe_ddc(&intel_dp->aux.ddc)) |
26d61aad | 4413 | return connector_status_connected; |
caf9ab24 AJ |
4414 | |
4415 | /* Well we tried, say unknown for unreliable port types */ | |
c9ff160b JN |
4416 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { |
4417 | type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; | |
4418 | if (type == DP_DS_PORT_TYPE_VGA || | |
4419 | type == DP_DS_PORT_TYPE_NON_EDID) | |
4420 | return connector_status_unknown; | |
4421 | } else { | |
4422 | type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & | |
4423 | DP_DWN_STRM_PORT_TYPE_MASK; | |
4424 | if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || | |
4425 | type == DP_DWN_STRM_PORT_TYPE_OTHER) | |
4426 | return connector_status_unknown; | |
4427 | } | |
caf9ab24 AJ |
4428 | |
4429 | /* Anything else is out of spec, warn and ignore */ | |
4430 | DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); | |
26d61aad | 4431 | return connector_status_disconnected; |
71ba9000 AJ |
4432 | } |
4433 | ||
d410b56d CW |
4434 | static enum drm_connector_status |
4435 | edp_detect(struct intel_dp *intel_dp) | |
4436 | { | |
4437 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
1650be74 | 4438 | struct drm_i915_private *dev_priv = to_i915(dev); |
d410b56d CW |
4439 | enum drm_connector_status status; |
4440 | ||
1650be74 | 4441 | status = intel_panel_detect(dev_priv); |
d410b56d CW |
4442 | if (status == connector_status_unknown) |
4443 | status = connector_status_connected; | |
4444 | ||
4445 | return status; | |
4446 | } | |
4447 | ||
b93433cc JN |
4448 | static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, |
4449 | struct intel_digital_port *port) | |
5eb08b69 | 4450 | { |
b93433cc | 4451 | u32 bit; |
01cb9ea6 | 4452 | |
0df53b77 JN |
4453 | switch (port->port) { |
4454 | case PORT_A: | |
4455 | return true; | |
4456 | case PORT_B: | |
4457 | bit = SDE_PORTB_HOTPLUG; | |
4458 | break; | |
4459 | case PORT_C: | |
4460 | bit = SDE_PORTC_HOTPLUG; | |
4461 | break; | |
4462 | case PORT_D: | |
4463 | bit = SDE_PORTD_HOTPLUG; | |
4464 | break; | |
4465 | default: | |
4466 | MISSING_CASE(port->port); | |
4467 | return false; | |
4468 | } | |
4469 | ||
4470 | return I915_READ(SDEISR) & bit; | |
4471 | } | |
4472 | ||
4473 | static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv, | |
4474 | struct intel_digital_port *port) | |
4475 | { | |
4476 | u32 bit; | |
4477 | ||
4478 | switch (port->port) { | |
4479 | case PORT_A: | |
4480 | return true; | |
4481 | case PORT_B: | |
4482 | bit = SDE_PORTB_HOTPLUG_CPT; | |
4483 | break; | |
4484 | case PORT_C: | |
4485 | bit = SDE_PORTC_HOTPLUG_CPT; | |
4486 | break; | |
4487 | case PORT_D: | |
4488 | bit = SDE_PORTD_HOTPLUG_CPT; | |
4489 | break; | |
a78695d3 JN |
4490 | case PORT_E: |
4491 | bit = SDE_PORTE_HOTPLUG_SPT; | |
4492 | break; | |
0df53b77 JN |
4493 | default: |
4494 | MISSING_CASE(port->port); | |
4495 | return false; | |
b93433cc | 4496 | } |
1b469639 | 4497 | |
b93433cc | 4498 | return I915_READ(SDEISR) & bit; |
5eb08b69 ZW |
4499 | } |
4500 | ||
7e66bcf2 | 4501 | static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv, |
1d245987 | 4502 | struct intel_digital_port *port) |
a4fc5ed6 | 4503 | { |
9642c81c | 4504 | u32 bit; |
5eb08b69 | 4505 | |
9642c81c JN |
4506 | switch (port->port) { |
4507 | case PORT_B: | |
4508 | bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; | |
4509 | break; | |
4510 | case PORT_C: | |
4511 | bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; | |
4512 | break; | |
4513 | case PORT_D: | |
4514 | bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; | |
4515 | break; | |
4516 | default: | |
4517 | MISSING_CASE(port->port); | |
4518 | return false; | |
4519 | } | |
4520 | ||
4521 | return I915_READ(PORT_HOTPLUG_STAT) & bit; | |
4522 | } | |
4523 | ||
0780cd36 VS |
4524 | static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv, |
4525 | struct intel_digital_port *port) | |
9642c81c JN |
4526 | { |
4527 | u32 bit; | |
4528 | ||
4529 | switch (port->port) { | |
4530 | case PORT_B: | |
0780cd36 | 4531 | bit = PORTB_HOTPLUG_LIVE_STATUS_GM45; |
9642c81c JN |
4532 | break; |
4533 | case PORT_C: | |
0780cd36 | 4534 | bit = PORTC_HOTPLUG_LIVE_STATUS_GM45; |
9642c81c JN |
4535 | break; |
4536 | case PORT_D: | |
0780cd36 | 4537 | bit = PORTD_HOTPLUG_LIVE_STATUS_GM45; |
9642c81c JN |
4538 | break; |
4539 | default: | |
4540 | MISSING_CASE(port->port); | |
4541 | return false; | |
a4fc5ed6 KP |
4542 | } |
4543 | ||
1d245987 | 4544 | return I915_READ(PORT_HOTPLUG_STAT) & bit; |
2a592bec DA |
4545 | } |
4546 | ||
e464bfde | 4547 | static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv, |
e2ec35a5 | 4548 | struct intel_digital_port *intel_dig_port) |
e464bfde | 4549 | { |
e2ec35a5 SJ |
4550 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
4551 | enum port port; | |
e464bfde JN |
4552 | u32 bit; |
4553 | ||
e2ec35a5 SJ |
4554 | intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port); |
4555 | switch (port) { | |
e464bfde JN |
4556 | case PORT_A: |
4557 | bit = BXT_DE_PORT_HP_DDIA; | |
4558 | break; | |
4559 | case PORT_B: | |
4560 | bit = BXT_DE_PORT_HP_DDIB; | |
4561 | break; | |
4562 | case PORT_C: | |
4563 | bit = BXT_DE_PORT_HP_DDIC; | |
4564 | break; | |
4565 | default: | |
e2ec35a5 | 4566 | MISSING_CASE(port); |
e464bfde JN |
4567 | return false; |
4568 | } | |
4569 | ||
4570 | return I915_READ(GEN8_DE_PORT_ISR) & bit; | |
4571 | } | |
4572 | ||
7e66bcf2 JN |
4573 | /* |
4574 | * intel_digital_port_connected - is the specified port connected? | |
4575 | * @dev_priv: i915 private structure | |
4576 | * @port: the port to test | |
4577 | * | |
4578 | * Return %true if @port is connected, %false otherwise. | |
4579 | */ | |
390b4e00 ID |
4580 | bool intel_digital_port_connected(struct drm_i915_private *dev_priv, |
4581 | struct intel_digital_port *port) | |
7e66bcf2 | 4582 | { |
0df53b77 | 4583 | if (HAS_PCH_IBX(dev_priv)) |
7e66bcf2 | 4584 | return ibx_digital_port_connected(dev_priv, port); |
22824fac | 4585 | else if (HAS_PCH_SPLIT(dev_priv)) |
0df53b77 | 4586 | return cpt_digital_port_connected(dev_priv, port); |
cc3f90f0 | 4587 | else if (IS_GEN9_LP(dev_priv)) |
e464bfde | 4588 | return bxt_digital_port_connected(dev_priv, port); |
0780cd36 VS |
4589 | else if (IS_GM45(dev_priv)) |
4590 | return gm45_digital_port_connected(dev_priv, port); | |
7e66bcf2 JN |
4591 | else |
4592 | return g4x_digital_port_connected(dev_priv, port); | |
4593 | } | |
4594 | ||
8c241fef | 4595 | static struct edid * |
beb60608 | 4596 | intel_dp_get_edid(struct intel_dp *intel_dp) |
8c241fef | 4597 | { |
beb60608 | 4598 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
d6f24d0f | 4599 | |
9cd300e0 JN |
4600 | /* use cached edid if we have one */ |
4601 | if (intel_connector->edid) { | |
9cd300e0 JN |
4602 | /* invalid edid */ |
4603 | if (IS_ERR(intel_connector->edid)) | |
d6f24d0f JB |
4604 | return NULL; |
4605 | ||
55e9edeb | 4606 | return drm_edid_duplicate(intel_connector->edid); |
beb60608 CW |
4607 | } else |
4608 | return drm_get_edid(&intel_connector->base, | |
4609 | &intel_dp->aux.ddc); | |
4610 | } | |
8c241fef | 4611 | |
beb60608 CW |
4612 | static void |
4613 | intel_dp_set_edid(struct intel_dp *intel_dp) | |
4614 | { | |
4615 | struct intel_connector *intel_connector = intel_dp->attached_connector; | |
4616 | struct edid *edid; | |
8c241fef | 4617 | |
f21a2198 | 4618 | intel_dp_unset_edid(intel_dp); |
beb60608 CW |
4619 | edid = intel_dp_get_edid(intel_dp); |
4620 | intel_connector->detect_edid = edid; | |
4621 | ||
e6b72c94 | 4622 | intel_dp->has_audio = drm_detect_monitor_audio(edid); |
8c241fef KP |
4623 | } |
4624 | ||
beb60608 CW |
4625 | static void |
4626 | intel_dp_unset_edid(struct intel_dp *intel_dp) | |
8c241fef | 4627 | { |
beb60608 | 4628 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
8c241fef | 4629 | |
beb60608 CW |
4630 | kfree(intel_connector->detect_edid); |
4631 | intel_connector->detect_edid = NULL; | |
9cd300e0 | 4632 | |
beb60608 CW |
4633 | intel_dp->has_audio = false; |
4634 | } | |
d6f24d0f | 4635 | |
6c5ed5ae | 4636 | static int |
f21a2198 | 4637 | intel_dp_long_pulse(struct intel_connector *intel_connector) |
a9756bb5 | 4638 | { |
f21a2198 | 4639 | struct drm_connector *connector = &intel_connector->base; |
a9756bb5 | 4640 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
d63885da PZ |
4641 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
4642 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
fa90ecef | 4643 | struct drm_device *dev = connector->dev; |
a9756bb5 | 4644 | enum drm_connector_status status; |
65fbb4e7 | 4645 | u8 sink_irq_vector = 0; |
a9756bb5 | 4646 | |
6c5ed5ae ML |
4647 | WARN_ON(!drm_modeset_is_locked(&connector->dev->mode_config.connection_mutex)); |
4648 | ||
5432fcaf | 4649 | intel_display_power_get(to_i915(dev), intel_dp->aux_power_domain); |
a9756bb5 | 4650 | |
d410b56d | 4651 | /* Can't disconnect eDP, but you can close the lid... */ |
01a7507f | 4652 | if (intel_dp_is_edp(intel_dp)) |
d410b56d | 4653 | status = edp_detect(intel_dp); |
c555a81d ACO |
4654 | else if (intel_digital_port_connected(to_i915(dev), |
4655 | dp_to_dig_port(intel_dp))) | |
4656 | status = intel_dp_detect_dpcd(intel_dp); | |
a9756bb5 | 4657 | else |
c555a81d ACO |
4658 | status = connector_status_disconnected; |
4659 | ||
5cb651a7 | 4660 | if (status == connector_status_disconnected) { |
c1617abc | 4661 | memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); |
4df6960e | 4662 | |
0e505a08 | 4663 | if (intel_dp->is_mst) { |
4664 | DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", | |
4665 | intel_dp->is_mst, | |
4666 | intel_dp->mst_mgr.mst_state); | |
4667 | intel_dp->is_mst = false; | |
4668 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, | |
4669 | intel_dp->is_mst); | |
4670 | } | |
4671 | ||
c8c8fb33 | 4672 | goto out; |
4df6960e | 4673 | } |
a9756bb5 | 4674 | |
f21a2198 | 4675 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
cca0502b | 4676 | intel_encoder->type = INTEL_OUTPUT_DP; |
f21a2198 | 4677 | |
fe5a66f9 VS |
4678 | DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n", |
4679 | yesno(intel_dp_source_supports_hbr2(intel_dp)), | |
4680 | yesno(drm_dp_tps3_supported(intel_dp->dpcd))); | |
4681 | ||
d7e8ef02 | 4682 | if (intel_dp->reset_link_params) { |
540b0b7f JN |
4683 | /* Initial max link lane count */ |
4684 | intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp); | |
f482984a | 4685 | |
540b0b7f JN |
4686 | /* Initial max link rate */ |
4687 | intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); | |
d7e8ef02 MN |
4688 | |
4689 | intel_dp->reset_link_params = false; | |
4690 | } | |
f482984a | 4691 | |
fe5a66f9 VS |
4692 | intel_dp_print_rates(intel_dp); |
4693 | ||
84c36753 JN |
4694 | drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, |
4695 | drm_dp_is_branch(intel_dp->dpcd)); | |
0e390a33 | 4696 | |
c4e3170a VS |
4697 | intel_dp_configure_mst(intel_dp); |
4698 | ||
4699 | if (intel_dp->is_mst) { | |
f21a2198 SS |
4700 | /* |
4701 | * If we are in MST mode then this connector | |
4702 | * won't appear connected or have anything | |
4703 | * with EDID on it | |
4704 | */ | |
0e32b39c DA |
4705 | status = connector_status_disconnected; |
4706 | goto out; | |
1a36147b VS |
4707 | } else { |
4708 | /* | |
4709 | * If display is now connected check links status, | |
4710 | * there has been known issues of link loss triggerring | |
4711 | * long pulse. | |
4712 | * | |
4713 | * Some sinks (eg. ASUS PB287Q) seem to perform some | |
4714 | * weird HPD ping pong during modesets. So we can apparently | |
4715 | * end up with HPD going low during a modeset, and then | |
4716 | * going back up soon after. And once that happens we must | |
4717 | * retrain the link to get a picture. That's in case no | |
4718 | * userspace component reacted to intermittent HPD dip. | |
4719 | */ | |
7d23e3c3 | 4720 | intel_dp_check_link_status(intel_dp); |
0e32b39c DA |
4721 | } |
4722 | ||
4df6960e SS |
4723 | /* |
4724 | * Clearing NACK and defer counts to get their exact values | |
4725 | * while reading EDID which are required by Compliance tests | |
4726 | * 4.2.2.4 and 4.2.2.5 | |
4727 | */ | |
4728 | intel_dp->aux.i2c_nack_count = 0; | |
4729 | intel_dp->aux.i2c_defer_count = 0; | |
4730 | ||
beb60608 | 4731 | intel_dp_set_edid(intel_dp); |
01a7507f | 4732 | if (intel_dp_is_edp(intel_dp) || intel_connector->detect_edid) |
5cb651a7 | 4733 | status = connector_status_connected; |
7d23e3c3 | 4734 | intel_dp->detect_done = true; |
c8c8fb33 | 4735 | |
09b1eb13 TP |
4736 | /* Try to read the source of the interrupt */ |
4737 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && | |
65fbb4e7 VS |
4738 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) && |
4739 | sink_irq_vector != 0) { | |
09b1eb13 TP |
4740 | /* Clear interrupt source */ |
4741 | drm_dp_dpcd_writeb(&intel_dp->aux, | |
4742 | DP_DEVICE_SERVICE_IRQ_VECTOR, | |
4743 | sink_irq_vector); | |
4744 | ||
4745 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) | |
4746 | intel_dp_handle_test_request(intel_dp); | |
4747 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) | |
4748 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); | |
4749 | } | |
4750 | ||
c8c8fb33 | 4751 | out: |
5cb651a7 | 4752 | if (status != connector_status_connected && !intel_dp->is_mst) |
f21a2198 | 4753 | intel_dp_unset_edid(intel_dp); |
7d23e3c3 | 4754 | |
5432fcaf | 4755 | intel_display_power_put(to_i915(dev), intel_dp->aux_power_domain); |
5cb651a7 | 4756 | return status; |
f21a2198 SS |
4757 | } |
4758 | ||
6c5ed5ae ML |
4759 | static int |
4760 | intel_dp_detect(struct drm_connector *connector, | |
4761 | struct drm_modeset_acquire_ctx *ctx, | |
4762 | bool force) | |
f21a2198 SS |
4763 | { |
4764 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
6c5ed5ae | 4765 | int status = connector->status; |
f21a2198 SS |
4766 | |
4767 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
4768 | connector->base.id, connector->name); | |
4769 | ||
7d23e3c3 SS |
4770 | /* If full detect is not performed yet, do a full detect */ |
4771 | if (!intel_dp->detect_done) | |
5cb651a7 | 4772 | status = intel_dp_long_pulse(intel_dp->attached_connector); |
7d23e3c3 SS |
4773 | |
4774 | intel_dp->detect_done = false; | |
f21a2198 | 4775 | |
5cb651a7 | 4776 | return status; |
a4fc5ed6 KP |
4777 | } |
4778 | ||
beb60608 CW |
4779 | static void |
4780 | intel_dp_force(struct drm_connector *connector) | |
a4fc5ed6 | 4781 | { |
df0e9248 | 4782 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
beb60608 | 4783 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
25f78f58 | 4784 | struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); |
a4fc5ed6 | 4785 | |
beb60608 CW |
4786 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
4787 | connector->base.id, connector->name); | |
4788 | intel_dp_unset_edid(intel_dp); | |
a4fc5ed6 | 4789 | |
beb60608 CW |
4790 | if (connector->status != connector_status_connected) |
4791 | return; | |
671dedd2 | 4792 | |
5432fcaf | 4793 | intel_display_power_get(dev_priv, intel_dp->aux_power_domain); |
beb60608 CW |
4794 | |
4795 | intel_dp_set_edid(intel_dp); | |
4796 | ||
5432fcaf | 4797 | intel_display_power_put(dev_priv, intel_dp->aux_power_domain); |
beb60608 CW |
4798 | |
4799 | if (intel_encoder->type != INTEL_OUTPUT_EDP) | |
cca0502b | 4800 | intel_encoder->type = INTEL_OUTPUT_DP; |
beb60608 CW |
4801 | } |
4802 | ||
4803 | static int intel_dp_get_modes(struct drm_connector *connector) | |
4804 | { | |
4805 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
4806 | struct edid *edid; | |
4807 | ||
4808 | edid = intel_connector->detect_edid; | |
4809 | if (edid) { | |
4810 | int ret = intel_connector_update_modes(connector, edid); | |
4811 | if (ret) | |
4812 | return ret; | |
4813 | } | |
32f9d658 | 4814 | |
f8779fda | 4815 | /* if eDP has no EDID, fall back to fixed mode */ |
01a7507f | 4816 | if (intel_dp_is_edp(intel_attached_dp(connector)) && |
beb60608 | 4817 | intel_connector->panel.fixed_mode) { |
f8779fda | 4818 | struct drm_display_mode *mode; |
beb60608 CW |
4819 | |
4820 | mode = drm_mode_duplicate(connector->dev, | |
dd06f90e | 4821 | intel_connector->panel.fixed_mode); |
f8779fda | 4822 | if (mode) { |
32f9d658 ZW |
4823 | drm_mode_probed_add(connector, mode); |
4824 | return 1; | |
4825 | } | |
4826 | } | |
beb60608 | 4827 | |
32f9d658 | 4828 | return 0; |
a4fc5ed6 KP |
4829 | } |
4830 | ||
7a418e34 CW |
4831 | static int |
4832 | intel_dp_connector_register(struct drm_connector *connector) | |
4833 | { | |
4834 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
1ebaa0b9 CW |
4835 | int ret; |
4836 | ||
4837 | ret = intel_connector_register(connector); | |
4838 | if (ret) | |
4839 | return ret; | |
7a418e34 CW |
4840 | |
4841 | i915_debugfs_connector_add(connector); | |
4842 | ||
4843 | DRM_DEBUG_KMS("registering %s bus for %s\n", | |
4844 | intel_dp->aux.name, connector->kdev->kobj.name); | |
4845 | ||
4846 | intel_dp->aux.dev = connector->kdev; | |
4847 | return drm_dp_aux_register(&intel_dp->aux); | |
4848 | } | |
4849 | ||
c191eca1 CW |
4850 | static void |
4851 | intel_dp_connector_unregister(struct drm_connector *connector) | |
4852 | { | |
4853 | drm_dp_aux_unregister(&intel_attached_dp(connector)->aux); | |
4854 | intel_connector_unregister(connector); | |
4855 | } | |
4856 | ||
a4fc5ed6 | 4857 | static void |
73845adf | 4858 | intel_dp_connector_destroy(struct drm_connector *connector) |
a4fc5ed6 | 4859 | { |
1d508706 | 4860 | struct intel_connector *intel_connector = to_intel_connector(connector); |
aaa6fd2a | 4861 | |
10e972d3 | 4862 | kfree(intel_connector->detect_edid); |
beb60608 | 4863 | |
9cd300e0 JN |
4864 | if (!IS_ERR_OR_NULL(intel_connector->edid)) |
4865 | kfree(intel_connector->edid); | |
4866 | ||
01a7507f JN |
4867 | /* |
4868 | * Can't call intel_dp_is_edp() since the encoder may have been | |
4869 | * destroyed already. | |
4870 | */ | |
acd8db10 | 4871 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) |
1d508706 | 4872 | intel_panel_fini(&intel_connector->panel); |
aaa6fd2a | 4873 | |
a4fc5ed6 | 4874 | drm_connector_cleanup(connector); |
55f78c43 | 4875 | kfree(connector); |
a4fc5ed6 KP |
4876 | } |
4877 | ||
00c09d70 | 4878 | void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
24d05927 | 4879 | { |
da63a9f2 PZ |
4880 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
4881 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
24d05927 | 4882 | |
0e32b39c | 4883 | intel_dp_mst_encoder_cleanup(intel_dig_port); |
01a7507f | 4884 | if (intel_dp_is_edp(intel_dp)) { |
bd943159 | 4885 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
951468f3 VS |
4886 | /* |
4887 | * vdd might still be enabled do to the delayed vdd off. | |
4888 | * Make sure vdd is actually turned off here. | |
4889 | */ | |
773538e8 | 4890 | pps_lock(intel_dp); |
4be73780 | 4891 | edp_panel_vdd_off_sync(intel_dp); |
773538e8 VS |
4892 | pps_unlock(intel_dp); |
4893 | ||
01527b31 CT |
4894 | if (intel_dp->edp_notifier.notifier_call) { |
4895 | unregister_reboot_notifier(&intel_dp->edp_notifier); | |
4896 | intel_dp->edp_notifier.notifier_call = NULL; | |
4897 | } | |
bd943159 | 4898 | } |
99681886 CW |
4899 | |
4900 | intel_dp_aux_fini(intel_dp); | |
4901 | ||
c8bd0e49 | 4902 | drm_encoder_cleanup(encoder); |
da63a9f2 | 4903 | kfree(intel_dig_port); |
24d05927 DV |
4904 | } |
4905 | ||
bf93ba67 | 4906 | void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder) |
07f9cd0b ID |
4907 | { |
4908 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
4909 | ||
01a7507f | 4910 | if (!intel_dp_is_edp(intel_dp)) |
07f9cd0b ID |
4911 | return; |
4912 | ||
951468f3 VS |
4913 | /* |
4914 | * vdd might still be enabled do to the delayed vdd off. | |
4915 | * Make sure vdd is actually turned off here. | |
4916 | */ | |
afa4e53a | 4917 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
773538e8 | 4918 | pps_lock(intel_dp); |
07f9cd0b | 4919 | edp_panel_vdd_off_sync(intel_dp); |
773538e8 | 4920 | pps_unlock(intel_dp); |
07f9cd0b ID |
4921 | } |
4922 | ||
49e6bc51 VS |
4923 | static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp) |
4924 | { | |
4925 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
4926 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 4927 | struct drm_i915_private *dev_priv = to_i915(dev); |
49e6bc51 VS |
4928 | |
4929 | lockdep_assert_held(&dev_priv->pps_mutex); | |
4930 | ||
4931 | if (!edp_have_panel_vdd(intel_dp)) | |
4932 | return; | |
4933 | ||
4934 | /* | |
4935 | * The VDD bit needs a power domain reference, so if the bit is | |
4936 | * already enabled when we boot or resume, grab this reference and | |
4937 | * schedule a vdd off, so we don't hold on to the reference | |
4938 | * indefinitely. | |
4939 | */ | |
4940 | DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n"); | |
5432fcaf | 4941 | intel_display_power_get(dev_priv, intel_dp->aux_power_domain); |
49e6bc51 VS |
4942 | |
4943 | edp_panel_vdd_schedule_off(intel_dp); | |
4944 | } | |
4945 | ||
9f2bdb00 VS |
4946 | static enum pipe vlv_active_pipe(struct intel_dp *intel_dp) |
4947 | { | |
4948 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); | |
4949 | ||
4950 | if ((intel_dp->DP & DP_PORT_EN) == 0) | |
4951 | return INVALID_PIPE; | |
4952 | ||
4953 | if (IS_CHERRYVIEW(dev_priv)) | |
4954 | return DP_PORT_TO_PIPE_CHV(intel_dp->DP); | |
4955 | else | |
4956 | return PORT_TO_PIPE(intel_dp->DP); | |
4957 | } | |
4958 | ||
bf93ba67 | 4959 | void intel_dp_encoder_reset(struct drm_encoder *encoder) |
6d93c0c4 | 4960 | { |
64989ca4 | 4961 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
dd75f6dd ID |
4962 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
4963 | struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp); | |
64989ca4 VS |
4964 | |
4965 | if (!HAS_DDI(dev_priv)) | |
4966 | intel_dp->DP = I915_READ(intel_dp->output_reg); | |
49e6bc51 | 4967 | |
dd75f6dd | 4968 | if (lspcon->active) |
910530c0 SS |
4969 | lspcon_resume(lspcon); |
4970 | ||
d7e8ef02 MN |
4971 | intel_dp->reset_link_params = true; |
4972 | ||
49e6bc51 VS |
4973 | pps_lock(intel_dp); |
4974 | ||
9f2bdb00 VS |
4975 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
4976 | intel_dp->active_pipe = vlv_active_pipe(intel_dp); | |
4977 | ||
01a7507f | 4978 | if (intel_dp_is_edp(intel_dp)) { |
9f2bdb00 VS |
4979 | /* Reinit the power sequencer, in case BIOS did something with it. */ |
4980 | intel_dp_pps_init(encoder->dev, intel_dp); | |
4981 | intel_edp_panel_vdd_sanitize(intel_dp); | |
4982 | } | |
49e6bc51 VS |
4983 | |
4984 | pps_unlock(intel_dp); | |
6d93c0c4 ID |
4985 | } |
4986 | ||
a4fc5ed6 | 4987 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
4d688a2a | 4988 | .dpms = drm_atomic_helper_connector_dpms, |
beb60608 | 4989 | .force = intel_dp_force, |
a4fc5ed6 | 4990 | .fill_modes = drm_helper_probe_single_connector_modes, |
8f647a01 ML |
4991 | .set_property = drm_atomic_helper_connector_set_property, |
4992 | .atomic_get_property = intel_digital_connector_atomic_get_property, | |
4993 | .atomic_set_property = intel_digital_connector_atomic_set_property, | |
7a418e34 | 4994 | .late_register = intel_dp_connector_register, |
c191eca1 | 4995 | .early_unregister = intel_dp_connector_unregister, |
73845adf | 4996 | .destroy = intel_dp_connector_destroy, |
c6f95f27 | 4997 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
8f647a01 | 4998 | .atomic_duplicate_state = intel_digital_connector_duplicate_state, |
a4fc5ed6 KP |
4999 | }; |
5000 | ||
5001 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { | |
6c5ed5ae | 5002 | .detect_ctx = intel_dp_detect, |
a4fc5ed6 KP |
5003 | .get_modes = intel_dp_get_modes, |
5004 | .mode_valid = intel_dp_mode_valid, | |
8f647a01 | 5005 | .atomic_check = intel_digital_connector_atomic_check, |
a4fc5ed6 KP |
5006 | }; |
5007 | ||
a4fc5ed6 | 5008 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
6d93c0c4 | 5009 | .reset = intel_dp_encoder_reset, |
24d05927 | 5010 | .destroy = intel_dp_encoder_destroy, |
a4fc5ed6 KP |
5011 | }; |
5012 | ||
b2c5c181 | 5013 | enum irqreturn |
13cf5504 DA |
5014 | intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) |
5015 | { | |
5016 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
0e32b39c | 5017 | struct drm_device *dev = intel_dig_port->base.base.dev; |
fac5e23e | 5018 | struct drm_i915_private *dev_priv = to_i915(dev); |
b2c5c181 | 5019 | enum irqreturn ret = IRQ_NONE; |
1c767b33 | 5020 | |
2540058f TI |
5021 | if (intel_dig_port->base.type != INTEL_OUTPUT_EDP && |
5022 | intel_dig_port->base.type != INTEL_OUTPUT_HDMI) | |
cca0502b | 5023 | intel_dig_port->base.type = INTEL_OUTPUT_DP; |
13cf5504 | 5024 | |
7a7f84cc VS |
5025 | if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) { |
5026 | /* | |
5027 | * vdd off can generate a long pulse on eDP which | |
5028 | * would require vdd on to handle it, and thus we | |
5029 | * would end up in an endless cycle of | |
5030 | * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..." | |
5031 | */ | |
5032 | DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n", | |
5033 | port_name(intel_dig_port->port)); | |
a8b3d52f | 5034 | return IRQ_HANDLED; |
7a7f84cc VS |
5035 | } |
5036 | ||
26fbb774 VS |
5037 | DRM_DEBUG_KMS("got hpd irq on port %c - %s\n", |
5038 | port_name(intel_dig_port->port), | |
0e32b39c | 5039 | long_hpd ? "long" : "short"); |
13cf5504 | 5040 | |
27d4efc5 | 5041 | if (long_hpd) { |
d7e8ef02 | 5042 | intel_dp->reset_link_params = true; |
27d4efc5 VS |
5043 | intel_dp->detect_done = false; |
5044 | return IRQ_NONE; | |
5045 | } | |
5046 | ||
5432fcaf | 5047 | intel_display_power_get(dev_priv, intel_dp->aux_power_domain); |
1c767b33 | 5048 | |
27d4efc5 VS |
5049 | if (intel_dp->is_mst) { |
5050 | if (intel_dp_check_mst_status(intel_dp) == -EINVAL) { | |
5051 | /* | |
5052 | * If we were in MST mode, and device is not | |
5053 | * there, get out of MST mode | |
5054 | */ | |
5055 | DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", | |
5056 | intel_dp->is_mst, intel_dp->mst_mgr.mst_state); | |
5057 | intel_dp->is_mst = false; | |
5058 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, | |
5059 | intel_dp->is_mst); | |
5060 | intel_dp->detect_done = false; | |
5061 | goto put_power; | |
0e32b39c | 5062 | } |
27d4efc5 | 5063 | } |
0e32b39c | 5064 | |
27d4efc5 VS |
5065 | if (!intel_dp->is_mst) { |
5066 | if (!intel_dp_short_pulse(intel_dp)) { | |
5067 | intel_dp->detect_done = false; | |
5068 | goto put_power; | |
39ff747b | 5069 | } |
0e32b39c | 5070 | } |
b2c5c181 DV |
5071 | |
5072 | ret = IRQ_HANDLED; | |
5073 | ||
1c767b33 | 5074 | put_power: |
5432fcaf | 5075 | intel_display_power_put(dev_priv, intel_dp->aux_power_domain); |
1c767b33 ID |
5076 | |
5077 | return ret; | |
13cf5504 DA |
5078 | } |
5079 | ||
477ec328 | 5080 | /* check the VBT to see whether the eDP is on another port */ |
a3b29673 | 5081 | bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port) |
36e83a18 | 5082 | { |
53ce81a7 VS |
5083 | /* |
5084 | * eDP not supported on g4x. so bail out early just | |
5085 | * for a bit extra safety in case the VBT is bonkers. | |
5086 | */ | |
dd11bc10 | 5087 | if (INTEL_GEN(dev_priv) < 5) |
53ce81a7 VS |
5088 | return false; |
5089 | ||
a98d9c1d | 5090 | if (INTEL_GEN(dev_priv) < 9 && port == PORT_A) |
3b32a35b VS |
5091 | return true; |
5092 | ||
951d9efe | 5093 | return intel_bios_is_port_edp(dev_priv, port); |
36e83a18 ZY |
5094 | } |
5095 | ||
200819ab | 5096 | static void |
f684960e CW |
5097 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) |
5098 | { | |
8b45330a | 5099 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
53b41837 | 5100 | |
3f43c48d | 5101 | intel_attach_force_audio_property(connector); |
e953fd7b | 5102 | intel_attach_broadcast_rgb_property(connector); |
53b41837 | 5103 | |
01a7507f | 5104 | if (intel_dp_is_edp(intel_dp)) { |
8b45330a ML |
5105 | u32 allowed_scalers; |
5106 | ||
5107 | allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN); | |
5108 | if (!HAS_GMCH_DISPLAY(dev_priv)) | |
5109 | allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER); | |
5110 | ||
5111 | drm_connector_attach_scaling_mode_property(connector, allowed_scalers); | |
5112 | ||
eead06df | 5113 | connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT; |
8b45330a | 5114 | |
53b41837 | 5115 | } |
f684960e CW |
5116 | } |
5117 | ||
dada1a9f ID |
5118 | static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) |
5119 | { | |
d28d4731 | 5120 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
dada1a9f ID |
5121 | intel_dp->last_power_on = jiffies; |
5122 | intel_dp->last_backlight_off = jiffies; | |
5123 | } | |
5124 | ||
67a54566 | 5125 | static void |
54648618 ID |
5126 | intel_pps_readout_hw_state(struct drm_i915_private *dev_priv, |
5127 | struct intel_dp *intel_dp, struct edp_power_seq *seq) | |
67a54566 | 5128 | { |
b0a08bec | 5129 | u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0; |
8e8232d5 | 5130 | struct pps_registers regs; |
453c5420 | 5131 | |
8e8232d5 | 5132 | intel_pps_get_registers(dev_priv, intel_dp, ®s); |
67a54566 DV |
5133 | |
5134 | /* Workaround: Need to write PP_CONTROL with the unlock key as | |
5135 | * the very first thing. */ | |
b0a08bec | 5136 | pp_ctl = ironlake_get_pp_control(intel_dp); |
67a54566 | 5137 | |
8e8232d5 ID |
5138 | pp_on = I915_READ(regs.pp_on); |
5139 | pp_off = I915_READ(regs.pp_off); | |
938361e7 | 5140 | if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv)) { |
8e8232d5 ID |
5141 | I915_WRITE(regs.pp_ctrl, pp_ctl); |
5142 | pp_div = I915_READ(regs.pp_div); | |
b0a08bec | 5143 | } |
67a54566 DV |
5144 | |
5145 | /* Pull timing values out of registers */ | |
54648618 ID |
5146 | seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> |
5147 | PANEL_POWER_UP_DELAY_SHIFT; | |
67a54566 | 5148 | |
54648618 ID |
5149 | seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> |
5150 | PANEL_LIGHT_ON_DELAY_SHIFT; | |
67a54566 | 5151 | |
54648618 ID |
5152 | seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> |
5153 | PANEL_LIGHT_OFF_DELAY_SHIFT; | |
67a54566 | 5154 | |
54648618 ID |
5155 | seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> |
5156 | PANEL_POWER_DOWN_DELAY_SHIFT; | |
67a54566 | 5157 | |
938361e7 | 5158 | if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) { |
b0a08bec VK |
5159 | u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >> |
5160 | BXT_POWER_CYCLE_DELAY_SHIFT; | |
5161 | if (tmp > 0) | |
54648618 | 5162 | seq->t11_t12 = (tmp - 1) * 1000; |
b0a08bec | 5163 | else |
54648618 | 5164 | seq->t11_t12 = 0; |
b0a08bec | 5165 | } else { |
54648618 | 5166 | seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> |
67a54566 | 5167 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; |
b0a08bec | 5168 | } |
54648618 ID |
5169 | } |
5170 | ||
de9c1b6b ID |
5171 | static void |
5172 | intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq) | |
5173 | { | |
5174 | DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", | |
5175 | state_name, | |
5176 | seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12); | |
5177 | } | |
5178 | ||
5179 | static void | |
5180 | intel_pps_verify_state(struct drm_i915_private *dev_priv, | |
5181 | struct intel_dp *intel_dp) | |
5182 | { | |
5183 | struct edp_power_seq hw; | |
5184 | struct edp_power_seq *sw = &intel_dp->pps_delays; | |
5185 | ||
5186 | intel_pps_readout_hw_state(dev_priv, intel_dp, &hw); | |
5187 | ||
5188 | if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 || | |
5189 | hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) { | |
5190 | DRM_ERROR("PPS state mismatch\n"); | |
5191 | intel_pps_dump_state("sw", sw); | |
5192 | intel_pps_dump_state("hw", &hw); | |
5193 | } | |
5194 | } | |
5195 | ||
54648618 ID |
5196 | static void |
5197 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, | |
5198 | struct intel_dp *intel_dp) | |
5199 | { | |
fac5e23e | 5200 | struct drm_i915_private *dev_priv = to_i915(dev); |
54648618 ID |
5201 | struct edp_power_seq cur, vbt, spec, |
5202 | *final = &intel_dp->pps_delays; | |
5203 | ||
5204 | lockdep_assert_held(&dev_priv->pps_mutex); | |
5205 | ||
5206 | /* already initialized? */ | |
5207 | if (final->t11_t12 != 0) | |
5208 | return; | |
5209 | ||
5210 | intel_pps_readout_hw_state(dev_priv, intel_dp, &cur); | |
67a54566 | 5211 | |
de9c1b6b | 5212 | intel_pps_dump_state("cur", &cur); |
67a54566 | 5213 | |
6aa23e65 | 5214 | vbt = dev_priv->vbt.edp.pps; |
67a54566 DV |
5215 | |
5216 | /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of | |
5217 | * our hw here, which are all in 100usec. */ | |
5218 | spec.t1_t3 = 210 * 10; | |
5219 | spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ | |
5220 | spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ | |
5221 | spec.t10 = 500 * 10; | |
5222 | /* This one is special and actually in units of 100ms, but zero | |
5223 | * based in the hw (so we need to add 100 ms). But the sw vbt | |
5224 | * table multiplies it with 1000 to make it in units of 100usec, | |
5225 | * too. */ | |
5226 | spec.t11_t12 = (510 + 100) * 10; | |
5227 | ||
de9c1b6b | 5228 | intel_pps_dump_state("vbt", &vbt); |
67a54566 DV |
5229 | |
5230 | /* Use the max of the register settings and vbt. If both are | |
5231 | * unset, fall back to the spec limits. */ | |
36b5f425 | 5232 | #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \ |
67a54566 DV |
5233 | spec.field : \ |
5234 | max(cur.field, vbt.field)) | |
5235 | assign_final(t1_t3); | |
5236 | assign_final(t8); | |
5237 | assign_final(t9); | |
5238 | assign_final(t10); | |
5239 | assign_final(t11_t12); | |
5240 | #undef assign_final | |
5241 | ||
36b5f425 | 5242 | #define get_delay(field) (DIV_ROUND_UP(final->field, 10)) |
67a54566 DV |
5243 | intel_dp->panel_power_up_delay = get_delay(t1_t3); |
5244 | intel_dp->backlight_on_delay = get_delay(t8); | |
5245 | intel_dp->backlight_off_delay = get_delay(t9); | |
5246 | intel_dp->panel_power_down_delay = get_delay(t10); | |
5247 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); | |
5248 | #undef get_delay | |
5249 | ||
f30d26e4 JN |
5250 | DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", |
5251 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, | |
5252 | intel_dp->panel_power_cycle_delay); | |
5253 | ||
5254 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", | |
5255 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); | |
de9c1b6b ID |
5256 | |
5257 | /* | |
5258 | * We override the HW backlight delays to 1 because we do manual waits | |
5259 | * on them. For T8, even BSpec recommends doing it. For T9, if we | |
5260 | * don't do this, we'll end up waiting for the backlight off delay | |
5261 | * twice: once when we do the manual sleep, and once when we disable | |
5262 | * the panel and wait for the PP_STATUS bit to become zero. | |
5263 | */ | |
5264 | final->t8 = 1; | |
5265 | final->t9 = 1; | |
f30d26e4 JN |
5266 | } |
5267 | ||
5268 | static void | |
5269 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, | |
5d5ab2d2 VS |
5270 | struct intel_dp *intel_dp, |
5271 | bool force_disable_vdd) | |
f30d26e4 | 5272 | { |
fac5e23e | 5273 | struct drm_i915_private *dev_priv = to_i915(dev); |
453c5420 | 5274 | u32 pp_on, pp_off, pp_div, port_sel = 0; |
e7dc33f3 | 5275 | int div = dev_priv->rawclk_freq / 1000; |
8e8232d5 | 5276 | struct pps_registers regs; |
ad933b56 | 5277 | enum port port = dp_to_dig_port(intel_dp)->port; |
36b5f425 | 5278 | const struct edp_power_seq *seq = &intel_dp->pps_delays; |
453c5420 | 5279 | |
e39b999a | 5280 | lockdep_assert_held(&dev_priv->pps_mutex); |
453c5420 | 5281 | |
8e8232d5 | 5282 | intel_pps_get_registers(dev_priv, intel_dp, ®s); |
453c5420 | 5283 | |
5d5ab2d2 VS |
5284 | /* |
5285 | * On some VLV machines the BIOS can leave the VDD | |
5286 | * enabled even on power seqeuencers which aren't | |
5287 | * hooked up to any port. This would mess up the | |
5288 | * power domain tracking the first time we pick | |
5289 | * one of these power sequencers for use since | |
5290 | * edp_panel_vdd_on() would notice that the VDD was | |
5291 | * already on and therefore wouldn't grab the power | |
5292 | * domain reference. Disable VDD first to avoid this. | |
5293 | * This also avoids spuriously turning the VDD on as | |
5294 | * soon as the new power seqeuencer gets initialized. | |
5295 | */ | |
5296 | if (force_disable_vdd) { | |
5297 | u32 pp = ironlake_get_pp_control(intel_dp); | |
5298 | ||
5299 | WARN(pp & PANEL_POWER_ON, "Panel power already on\n"); | |
5300 | ||
5301 | if (pp & EDP_FORCE_VDD) | |
5302 | DRM_DEBUG_KMS("VDD already on, disabling first\n"); | |
5303 | ||
5304 | pp &= ~EDP_FORCE_VDD; | |
5305 | ||
5306 | I915_WRITE(regs.pp_ctrl, pp); | |
5307 | } | |
5308 | ||
f30d26e4 | 5309 | pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | |
de9c1b6b ID |
5310 | (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT); |
5311 | pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) | | |
f30d26e4 | 5312 | (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); |
67a54566 DV |
5313 | /* Compute the divisor for the pp clock, simply match the Bspec |
5314 | * formula. */ | |
938361e7 | 5315 | if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) { |
8e8232d5 | 5316 | pp_div = I915_READ(regs.pp_ctrl); |
b0a08bec VK |
5317 | pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK; |
5318 | pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000) | |
5319 | << BXT_POWER_CYCLE_DELAY_SHIFT); | |
5320 | } else { | |
5321 | pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; | |
5322 | pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) | |
5323 | << PANEL_POWER_CYCLE_DELAY_SHIFT); | |
5324 | } | |
67a54566 DV |
5325 | |
5326 | /* Haswell doesn't have any port selection bits for the panel | |
5327 | * power sequencer any more. */ | |
920a14b2 | 5328 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
ad933b56 | 5329 | port_sel = PANEL_PORT_SELECT_VLV(port); |
6e266956 | 5330 | } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { |
ad933b56 | 5331 | if (port == PORT_A) |
a24c144c | 5332 | port_sel = PANEL_PORT_SELECT_DPA; |
67a54566 | 5333 | else |
a24c144c | 5334 | port_sel = PANEL_PORT_SELECT_DPD; |
67a54566 DV |
5335 | } |
5336 | ||
453c5420 JB |
5337 | pp_on |= port_sel; |
5338 | ||
8e8232d5 ID |
5339 | I915_WRITE(regs.pp_on, pp_on); |
5340 | I915_WRITE(regs.pp_off, pp_off); | |
938361e7 | 5341 | if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) |
8e8232d5 | 5342 | I915_WRITE(regs.pp_ctrl, pp_div); |
b0a08bec | 5343 | else |
8e8232d5 | 5344 | I915_WRITE(regs.pp_div, pp_div); |
67a54566 | 5345 | |
67a54566 | 5346 | DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", |
8e8232d5 ID |
5347 | I915_READ(regs.pp_on), |
5348 | I915_READ(regs.pp_off), | |
938361e7 | 5349 | (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) ? |
8e8232d5 ID |
5350 | (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) : |
5351 | I915_READ(regs.pp_div)); | |
f684960e CW |
5352 | } |
5353 | ||
335f752b ID |
5354 | static void intel_dp_pps_init(struct drm_device *dev, |
5355 | struct intel_dp *intel_dp) | |
5356 | { | |
920a14b2 TU |
5357 | struct drm_i915_private *dev_priv = to_i915(dev); |
5358 | ||
5359 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { | |
335f752b ID |
5360 | vlv_initial_power_sequencer_setup(intel_dp); |
5361 | } else { | |
5362 | intel_dp_init_panel_power_sequencer(dev, intel_dp); | |
5d5ab2d2 | 5363 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false); |
335f752b ID |
5364 | } |
5365 | } | |
5366 | ||
b33a2815 VK |
5367 | /** |
5368 | * intel_dp_set_drrs_state - program registers for RR switch to take effect | |
5423adf1 | 5369 | * @dev_priv: i915 device |
e896402c | 5370 | * @crtc_state: a pointer to the active intel_crtc_state |
b33a2815 VK |
5371 | * @refresh_rate: RR to be programmed |
5372 | * | |
5373 | * This function gets called when refresh rate (RR) has to be changed from | |
5374 | * one frequency to another. Switches can be between high and low RR | |
5375 | * supported by the panel or to any other RR based on media playback (in | |
5376 | * this case, RR value needs to be passed from user space). | |
5377 | * | |
5378 | * The caller of this function needs to take a lock on dev_priv->drrs. | |
5379 | */ | |
85cb48a1 ML |
5380 | static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv, |
5381 | struct intel_crtc_state *crtc_state, | |
5382 | int refresh_rate) | |
439d7ac0 | 5383 | { |
439d7ac0 | 5384 | struct intel_encoder *encoder; |
96178eeb VK |
5385 | struct intel_digital_port *dig_port = NULL; |
5386 | struct intel_dp *intel_dp = dev_priv->drrs.dp; | |
85cb48a1 | 5387 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
96178eeb | 5388 | enum drrs_refresh_rate_type index = DRRS_HIGH_RR; |
439d7ac0 PB |
5389 | |
5390 | if (refresh_rate <= 0) { | |
5391 | DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n"); | |
5392 | return; | |
5393 | } | |
5394 | ||
96178eeb VK |
5395 | if (intel_dp == NULL) { |
5396 | DRM_DEBUG_KMS("DRRS not supported.\n"); | |
439d7ac0 PB |
5397 | return; |
5398 | } | |
5399 | ||
1fcc9d1c | 5400 | /* |
e4d59f6b RV |
5401 | * FIXME: This needs proper synchronization with psr state for some |
5402 | * platforms that cannot have PSR and DRRS enabled at the same time. | |
1fcc9d1c | 5403 | */ |
439d7ac0 | 5404 | |
96178eeb VK |
5405 | dig_port = dp_to_dig_port(intel_dp); |
5406 | encoder = &dig_port->base; | |
723f9aab | 5407 | intel_crtc = to_intel_crtc(encoder->base.crtc); |
439d7ac0 PB |
5408 | |
5409 | if (!intel_crtc) { | |
5410 | DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n"); | |
5411 | return; | |
5412 | } | |
5413 | ||
96178eeb | 5414 | if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) { |
439d7ac0 PB |
5415 | DRM_DEBUG_KMS("Only Seamless DRRS supported.\n"); |
5416 | return; | |
5417 | } | |
5418 | ||
96178eeb VK |
5419 | if (intel_dp->attached_connector->panel.downclock_mode->vrefresh == |
5420 | refresh_rate) | |
439d7ac0 PB |
5421 | index = DRRS_LOW_RR; |
5422 | ||
96178eeb | 5423 | if (index == dev_priv->drrs.refresh_rate_type) { |
439d7ac0 PB |
5424 | DRM_DEBUG_KMS( |
5425 | "DRRS requested for previously set RR...ignoring\n"); | |
5426 | return; | |
5427 | } | |
5428 | ||
85cb48a1 | 5429 | if (!crtc_state->base.active) { |
439d7ac0 PB |
5430 | DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n"); |
5431 | return; | |
5432 | } | |
5433 | ||
85cb48a1 | 5434 | if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) { |
a4c30b1d VK |
5435 | switch (index) { |
5436 | case DRRS_HIGH_RR: | |
5437 | intel_dp_set_m_n(intel_crtc, M1_N1); | |
5438 | break; | |
5439 | case DRRS_LOW_RR: | |
5440 | intel_dp_set_m_n(intel_crtc, M2_N2); | |
5441 | break; | |
5442 | case DRRS_MAX_RR: | |
5443 | default: | |
5444 | DRM_ERROR("Unsupported refreshrate type\n"); | |
5445 | } | |
85cb48a1 ML |
5446 | } else if (INTEL_GEN(dev_priv) > 6) { |
5447 | i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder); | |
649636ef | 5448 | u32 val; |
a4c30b1d | 5449 | |
649636ef | 5450 | val = I915_READ(reg); |
439d7ac0 | 5451 | if (index > DRRS_HIGH_RR) { |
85cb48a1 | 5452 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
6fa7aec1 VK |
5453 | val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV; |
5454 | else | |
5455 | val |= PIPECONF_EDP_RR_MODE_SWITCH; | |
439d7ac0 | 5456 | } else { |
85cb48a1 | 5457 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
6fa7aec1 VK |
5458 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV; |
5459 | else | |
5460 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH; | |
439d7ac0 PB |
5461 | } |
5462 | I915_WRITE(reg, val); | |
5463 | } | |
5464 | ||
4e9ac947 VK |
5465 | dev_priv->drrs.refresh_rate_type = index; |
5466 | ||
5467 | DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate); | |
5468 | } | |
5469 | ||
b33a2815 VK |
5470 | /** |
5471 | * intel_edp_drrs_enable - init drrs struct if supported | |
5472 | * @intel_dp: DP struct | |
5423adf1 | 5473 | * @crtc_state: A pointer to the active crtc state. |
b33a2815 VK |
5474 | * |
5475 | * Initializes frontbuffer_bits and drrs.dp | |
5476 | */ | |
85cb48a1 ML |
5477 | void intel_edp_drrs_enable(struct intel_dp *intel_dp, |
5478 | struct intel_crtc_state *crtc_state) | |
c395578e VK |
5479 | { |
5480 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
fac5e23e | 5481 | struct drm_i915_private *dev_priv = to_i915(dev); |
c395578e | 5482 | |
85cb48a1 | 5483 | if (!crtc_state->has_drrs) { |
c395578e VK |
5484 | DRM_DEBUG_KMS("Panel doesn't support DRRS\n"); |
5485 | return; | |
5486 | } | |
5487 | ||
5488 | mutex_lock(&dev_priv->drrs.mutex); | |
5489 | if (WARN_ON(dev_priv->drrs.dp)) { | |
5490 | DRM_ERROR("DRRS already enabled\n"); | |
5491 | goto unlock; | |
5492 | } | |
5493 | ||
5494 | dev_priv->drrs.busy_frontbuffer_bits = 0; | |
5495 | ||
5496 | dev_priv->drrs.dp = intel_dp; | |
5497 | ||
5498 | unlock: | |
5499 | mutex_unlock(&dev_priv->drrs.mutex); | |
5500 | } | |
5501 | ||
b33a2815 VK |
5502 | /** |
5503 | * intel_edp_drrs_disable - Disable DRRS | |
5504 | * @intel_dp: DP struct | |
5423adf1 | 5505 | * @old_crtc_state: Pointer to old crtc_state. |
b33a2815 VK |
5506 | * |
5507 | */ | |
85cb48a1 ML |
5508 | void intel_edp_drrs_disable(struct intel_dp *intel_dp, |
5509 | struct intel_crtc_state *old_crtc_state) | |
c395578e VK |
5510 | { |
5511 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
fac5e23e | 5512 | struct drm_i915_private *dev_priv = to_i915(dev); |
c395578e | 5513 | |
85cb48a1 | 5514 | if (!old_crtc_state->has_drrs) |
c395578e VK |
5515 | return; |
5516 | ||
5517 | mutex_lock(&dev_priv->drrs.mutex); | |
5518 | if (!dev_priv->drrs.dp) { | |
5519 | mutex_unlock(&dev_priv->drrs.mutex); | |
5520 | return; | |
5521 | } | |
5522 | ||
5523 | if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) | |
85cb48a1 ML |
5524 | intel_dp_set_drrs_state(dev_priv, old_crtc_state, |
5525 | intel_dp->attached_connector->panel.fixed_mode->vrefresh); | |
c395578e VK |
5526 | |
5527 | dev_priv->drrs.dp = NULL; | |
5528 | mutex_unlock(&dev_priv->drrs.mutex); | |
5529 | ||
5530 | cancel_delayed_work_sync(&dev_priv->drrs.work); | |
5531 | } | |
5532 | ||
4e9ac947 VK |
5533 | static void intel_edp_drrs_downclock_work(struct work_struct *work) |
5534 | { | |
5535 | struct drm_i915_private *dev_priv = | |
5536 | container_of(work, typeof(*dev_priv), drrs.work.work); | |
5537 | struct intel_dp *intel_dp; | |
5538 | ||
5539 | mutex_lock(&dev_priv->drrs.mutex); | |
5540 | ||
5541 | intel_dp = dev_priv->drrs.dp; | |
5542 | ||
5543 | if (!intel_dp) | |
5544 | goto unlock; | |
5545 | ||
439d7ac0 | 5546 | /* |
4e9ac947 VK |
5547 | * The delayed work can race with an invalidate hence we need to |
5548 | * recheck. | |
439d7ac0 PB |
5549 | */ |
5550 | ||
4e9ac947 VK |
5551 | if (dev_priv->drrs.busy_frontbuffer_bits) |
5552 | goto unlock; | |
439d7ac0 | 5553 | |
85cb48a1 ML |
5554 | if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) { |
5555 | struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc; | |
5556 | ||
5557 | intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config, | |
5558 | intel_dp->attached_connector->panel.downclock_mode->vrefresh); | |
5559 | } | |
439d7ac0 | 5560 | |
4e9ac947 | 5561 | unlock: |
4e9ac947 | 5562 | mutex_unlock(&dev_priv->drrs.mutex); |
439d7ac0 PB |
5563 | } |
5564 | ||
b33a2815 | 5565 | /** |
0ddfd203 | 5566 | * intel_edp_drrs_invalidate - Disable Idleness DRRS |
5748b6a1 | 5567 | * @dev_priv: i915 device |
b33a2815 VK |
5568 | * @frontbuffer_bits: frontbuffer plane tracking bits |
5569 | * | |
0ddfd203 R |
5570 | * This function gets called everytime rendering on the given planes start. |
5571 | * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR). | |
b33a2815 VK |
5572 | * |
5573 | * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. | |
5574 | */ | |
5748b6a1 CW |
5575 | void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv, |
5576 | unsigned int frontbuffer_bits) | |
a93fad0f | 5577 | { |
a93fad0f VK |
5578 | struct drm_crtc *crtc; |
5579 | enum pipe pipe; | |
5580 | ||
9da7d693 | 5581 | if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) |
a93fad0f VK |
5582 | return; |
5583 | ||
88f933a8 | 5584 | cancel_delayed_work(&dev_priv->drrs.work); |
3954e733 | 5585 | |
a93fad0f | 5586 | mutex_lock(&dev_priv->drrs.mutex); |
9da7d693 DV |
5587 | if (!dev_priv->drrs.dp) { |
5588 | mutex_unlock(&dev_priv->drrs.mutex); | |
5589 | return; | |
5590 | } | |
5591 | ||
a93fad0f VK |
5592 | crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; |
5593 | pipe = to_intel_crtc(crtc)->pipe; | |
5594 | ||
c1d038c6 DV |
5595 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); |
5596 | dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits; | |
5597 | ||
0ddfd203 | 5598 | /* invalidate means busy screen hence upclock */ |
c1d038c6 | 5599 | if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
85cb48a1 ML |
5600 | intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config, |
5601 | dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh); | |
a93fad0f | 5602 | |
a93fad0f VK |
5603 | mutex_unlock(&dev_priv->drrs.mutex); |
5604 | } | |
5605 | ||
b33a2815 | 5606 | /** |
0ddfd203 | 5607 | * intel_edp_drrs_flush - Restart Idleness DRRS |
5748b6a1 | 5608 | * @dev_priv: i915 device |
b33a2815 VK |
5609 | * @frontbuffer_bits: frontbuffer plane tracking bits |
5610 | * | |
0ddfd203 R |
5611 | * This function gets called every time rendering on the given planes has |
5612 | * completed or flip on a crtc is completed. So DRRS should be upclocked | |
5613 | * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again, | |
5614 | * if no other planes are dirty. | |
b33a2815 VK |
5615 | * |
5616 | * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. | |
5617 | */ | |
5748b6a1 CW |
5618 | void intel_edp_drrs_flush(struct drm_i915_private *dev_priv, |
5619 | unsigned int frontbuffer_bits) | |
a93fad0f | 5620 | { |
a93fad0f VK |
5621 | struct drm_crtc *crtc; |
5622 | enum pipe pipe; | |
5623 | ||
9da7d693 | 5624 | if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) |
a93fad0f VK |
5625 | return; |
5626 | ||
88f933a8 | 5627 | cancel_delayed_work(&dev_priv->drrs.work); |
3954e733 | 5628 | |
a93fad0f | 5629 | mutex_lock(&dev_priv->drrs.mutex); |
9da7d693 DV |
5630 | if (!dev_priv->drrs.dp) { |
5631 | mutex_unlock(&dev_priv->drrs.mutex); | |
5632 | return; | |
5633 | } | |
5634 | ||
a93fad0f VK |
5635 | crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; |
5636 | pipe = to_intel_crtc(crtc)->pipe; | |
c1d038c6 DV |
5637 | |
5638 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); | |
a93fad0f VK |
5639 | dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits; |
5640 | ||
0ddfd203 | 5641 | /* flush means busy screen hence upclock */ |
c1d038c6 | 5642 | if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
85cb48a1 ML |
5643 | intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config, |
5644 | dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh); | |
0ddfd203 R |
5645 | |
5646 | /* | |
5647 | * flush also means no more activity hence schedule downclock, if all | |
5648 | * other fbs are quiescent too | |
5649 | */ | |
5650 | if (!dev_priv->drrs.busy_frontbuffer_bits) | |
a93fad0f VK |
5651 | schedule_delayed_work(&dev_priv->drrs.work, |
5652 | msecs_to_jiffies(1000)); | |
5653 | mutex_unlock(&dev_priv->drrs.mutex); | |
5654 | } | |
5655 | ||
b33a2815 VK |
5656 | /** |
5657 | * DOC: Display Refresh Rate Switching (DRRS) | |
5658 | * | |
5659 | * Display Refresh Rate Switching (DRRS) is a power conservation feature | |
5660 | * which enables swtching between low and high refresh rates, | |
5661 | * dynamically, based on the usage scenario. This feature is applicable | |
5662 | * for internal panels. | |
5663 | * | |
5664 | * Indication that the panel supports DRRS is given by the panel EDID, which | |
5665 | * would list multiple refresh rates for one resolution. | |
5666 | * | |
5667 | * DRRS is of 2 types - static and seamless. | |
5668 | * Static DRRS involves changing refresh rate (RR) by doing a full modeset | |
5669 | * (may appear as a blink on screen) and is used in dock-undock scenario. | |
5670 | * Seamless DRRS involves changing RR without any visual effect to the user | |
5671 | * and can be used during normal system usage. This is done by programming | |
5672 | * certain registers. | |
5673 | * | |
5674 | * Support for static/seamless DRRS may be indicated in the VBT based on | |
5675 | * inputs from the panel spec. | |
5676 | * | |
5677 | * DRRS saves power by switching to low RR based on usage scenarios. | |
5678 | * | |
2e7a5701 DV |
5679 | * The implementation is based on frontbuffer tracking implementation. When |
5680 | * there is a disturbance on the screen triggered by user activity or a periodic | |
5681 | * system activity, DRRS is disabled (RR is changed to high RR). When there is | |
5682 | * no movement on screen, after a timeout of 1 second, a switch to low RR is | |
5683 | * made. | |
5684 | * | |
5685 | * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate() | |
5686 | * and intel_edp_drrs_flush() are called. | |
b33a2815 VK |
5687 | * |
5688 | * DRRS can be further extended to support other internal panels and also | |
5689 | * the scenario of video playback wherein RR is set based on the rate | |
5690 | * requested by userspace. | |
5691 | */ | |
5692 | ||
5693 | /** | |
5694 | * intel_dp_drrs_init - Init basic DRRS work and mutex. | |
5695 | * @intel_connector: eDP connector | |
5696 | * @fixed_mode: preferred mode of panel | |
5697 | * | |
5698 | * This function is called only once at driver load to initialize basic | |
5699 | * DRRS stuff. | |
5700 | * | |
5701 | * Returns: | |
5702 | * Downclock mode if panel supports it, else return NULL. | |
5703 | * DRRS support is determined by the presence of downclock mode (apart | |
5704 | * from VBT setting). | |
5705 | */ | |
4f9db5b5 | 5706 | static struct drm_display_mode * |
96178eeb VK |
5707 | intel_dp_drrs_init(struct intel_connector *intel_connector, |
5708 | struct drm_display_mode *fixed_mode) | |
4f9db5b5 PB |
5709 | { |
5710 | struct drm_connector *connector = &intel_connector->base; | |
96178eeb | 5711 | struct drm_device *dev = connector->dev; |
fac5e23e | 5712 | struct drm_i915_private *dev_priv = to_i915(dev); |
4f9db5b5 PB |
5713 | struct drm_display_mode *downclock_mode = NULL; |
5714 | ||
9da7d693 DV |
5715 | INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work); |
5716 | mutex_init(&dev_priv->drrs.mutex); | |
5717 | ||
dd11bc10 | 5718 | if (INTEL_GEN(dev_priv) <= 6) { |
4f9db5b5 PB |
5719 | DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); |
5720 | return NULL; | |
5721 | } | |
5722 | ||
5723 | if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { | |
4079b8d1 | 5724 | DRM_DEBUG_KMS("VBT doesn't support DRRS\n"); |
4f9db5b5 PB |
5725 | return NULL; |
5726 | } | |
5727 | ||
5728 | downclock_mode = intel_find_panel_downclock | |
a318b4c4 | 5729 | (dev_priv, fixed_mode, connector); |
4f9db5b5 PB |
5730 | |
5731 | if (!downclock_mode) { | |
a1d26342 | 5732 | DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n"); |
4f9db5b5 PB |
5733 | return NULL; |
5734 | } | |
5735 | ||
96178eeb | 5736 | dev_priv->drrs.type = dev_priv->vbt.drrs_type; |
4f9db5b5 | 5737 | |
96178eeb | 5738 | dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR; |
4079b8d1 | 5739 | DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n"); |
4f9db5b5 PB |
5740 | return downclock_mode; |
5741 | } | |
5742 | ||
ed92f0b2 | 5743 | static bool intel_edp_init_connector(struct intel_dp *intel_dp, |
36b5f425 | 5744 | struct intel_connector *intel_connector) |
ed92f0b2 PZ |
5745 | { |
5746 | struct drm_connector *connector = &intel_connector->base; | |
5747 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
63635217 PZ |
5748 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
5749 | struct drm_device *dev = intel_encoder->base.dev; | |
fac5e23e | 5750 | struct drm_i915_private *dev_priv = to_i915(dev); |
ed92f0b2 | 5751 | struct drm_display_mode *fixed_mode = NULL; |
9081fd90 | 5752 | struct drm_display_mode *alt_fixed_mode = NULL; |
4f9db5b5 | 5753 | struct drm_display_mode *downclock_mode = NULL; |
ed92f0b2 PZ |
5754 | bool has_dpcd; |
5755 | struct drm_display_mode *scan; | |
5756 | struct edid *edid; | |
6517d273 | 5757 | enum pipe pipe = INVALID_PIPE; |
ed92f0b2 | 5758 | |
01a7507f | 5759 | if (!intel_dp_is_edp(intel_dp)) |
ed92f0b2 PZ |
5760 | return true; |
5761 | ||
97a824e1 ID |
5762 | /* |
5763 | * On IBX/CPT we may get here with LVDS already registered. Since the | |
5764 | * driver uses the only internal power sequencer available for both | |
5765 | * eDP and LVDS bail out early in this case to prevent interfering | |
5766 | * with an already powered-on LVDS power sequencer. | |
5767 | */ | |
5768 | if (intel_get_lvds_encoder(dev)) { | |
5769 | WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))); | |
5770 | DRM_INFO("LVDS was detected, not registering eDP\n"); | |
5771 | ||
5772 | return false; | |
5773 | } | |
5774 | ||
49e6bc51 | 5775 | pps_lock(intel_dp); |
b4d06ede ID |
5776 | |
5777 | intel_dp_init_panel_power_timestamps(intel_dp); | |
335f752b | 5778 | intel_dp_pps_init(dev, intel_dp); |
49e6bc51 | 5779 | intel_edp_panel_vdd_sanitize(intel_dp); |
b4d06ede | 5780 | |
49e6bc51 | 5781 | pps_unlock(intel_dp); |
63635217 | 5782 | |
ed92f0b2 | 5783 | /* Cache DPCD and EDID for edp. */ |
fe5a66f9 | 5784 | has_dpcd = intel_edp_init_dpcd(intel_dp); |
ed92f0b2 | 5785 | |
fe5a66f9 | 5786 | if (!has_dpcd) { |
ed92f0b2 PZ |
5787 | /* if this fails, presume the device is a ghost */ |
5788 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); | |
b4d06ede | 5789 | goto out_vdd_off; |
ed92f0b2 PZ |
5790 | } |
5791 | ||
060c8778 | 5792 | mutex_lock(&dev->mode_config.mutex); |
0b99836f | 5793 | edid = drm_get_edid(connector, &intel_dp->aux.ddc); |
ed92f0b2 PZ |
5794 | if (edid) { |
5795 | if (drm_add_edid_modes(connector, edid)) { | |
5796 | drm_mode_connector_update_edid_property(connector, | |
5797 | edid); | |
5798 | drm_edid_to_eld(connector, edid); | |
5799 | } else { | |
5800 | kfree(edid); | |
5801 | edid = ERR_PTR(-EINVAL); | |
5802 | } | |
5803 | } else { | |
5804 | edid = ERR_PTR(-ENOENT); | |
5805 | } | |
5806 | intel_connector->edid = edid; | |
5807 | ||
9081fd90 | 5808 | /* prefer fixed mode from EDID if available, save an alt mode also */ |
ed92f0b2 PZ |
5809 | list_for_each_entry(scan, &connector->probed_modes, head) { |
5810 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { | |
5811 | fixed_mode = drm_mode_duplicate(dev, scan); | |
4f9db5b5 | 5812 | downclock_mode = intel_dp_drrs_init( |
4f9db5b5 | 5813 | intel_connector, fixed_mode); |
9081fd90 JB |
5814 | } else if (!alt_fixed_mode) { |
5815 | alt_fixed_mode = drm_mode_duplicate(dev, scan); | |
ed92f0b2 PZ |
5816 | } |
5817 | } | |
5818 | ||
5819 | /* fallback to VBT if available for eDP */ | |
5820 | if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { | |
5821 | fixed_mode = drm_mode_duplicate(dev, | |
5822 | dev_priv->vbt.lfp_lvds_vbt_mode); | |
df457245 | 5823 | if (fixed_mode) { |
ed92f0b2 | 5824 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
df457245 VS |
5825 | connector->display_info.width_mm = fixed_mode->width_mm; |
5826 | connector->display_info.height_mm = fixed_mode->height_mm; | |
5827 | } | |
ed92f0b2 | 5828 | } |
060c8778 | 5829 | mutex_unlock(&dev->mode_config.mutex); |
ed92f0b2 | 5830 | |
920a14b2 | 5831 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
01527b31 CT |
5832 | intel_dp->edp_notifier.notifier_call = edp_notify_handler; |
5833 | register_reboot_notifier(&intel_dp->edp_notifier); | |
6517d273 VS |
5834 | |
5835 | /* | |
5836 | * Figure out the current pipe for the initial backlight setup. | |
5837 | * If the current pipe isn't valid, try the PPS pipe, and if that | |
5838 | * fails just assume pipe A. | |
5839 | */ | |
9f2bdb00 | 5840 | pipe = vlv_active_pipe(intel_dp); |
6517d273 VS |
5841 | |
5842 | if (pipe != PIPE_A && pipe != PIPE_B) | |
5843 | pipe = intel_dp->pps_pipe; | |
5844 | ||
5845 | if (pipe != PIPE_A && pipe != PIPE_B) | |
5846 | pipe = PIPE_A; | |
5847 | ||
5848 | DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n", | |
5849 | pipe_name(pipe)); | |
01527b31 CT |
5850 | } |
5851 | ||
9081fd90 JB |
5852 | intel_panel_init(&intel_connector->panel, fixed_mode, alt_fixed_mode, |
5853 | downclock_mode); | |
5507faeb | 5854 | intel_connector->panel.backlight.power = intel_edp_backlight_power; |
6517d273 | 5855 | intel_panel_setup_backlight(connector, pipe); |
ed92f0b2 PZ |
5856 | |
5857 | return true; | |
b4d06ede ID |
5858 | |
5859 | out_vdd_off: | |
5860 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); | |
5861 | /* | |
5862 | * vdd might still be enabled do to the delayed vdd off. | |
5863 | * Make sure vdd is actually turned off here. | |
5864 | */ | |
5865 | pps_lock(intel_dp); | |
5866 | edp_panel_vdd_off_sync(intel_dp); | |
5867 | pps_unlock(intel_dp); | |
5868 | ||
5869 | return false; | |
ed92f0b2 PZ |
5870 | } |
5871 | ||
5432fcaf | 5872 | /* Set up the hotplug pin and aux power domain. */ |
b71953a1 ACO |
5873 | static void |
5874 | intel_dp_init_connector_port_info(struct intel_digital_port *intel_dig_port) | |
5875 | { | |
5876 | struct intel_encoder *encoder = &intel_dig_port->base; | |
5432fcaf | 5877 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
b71953a1 | 5878 | |
b71953a1 ACO |
5879 | switch (intel_dig_port->port) { |
5880 | case PORT_A: | |
5881 | encoder->hpd_pin = HPD_PORT_A; | |
5432fcaf | 5882 | intel_dp->aux_power_domain = POWER_DOMAIN_AUX_A; |
b71953a1 ACO |
5883 | break; |
5884 | case PORT_B: | |
5885 | encoder->hpd_pin = HPD_PORT_B; | |
5432fcaf | 5886 | intel_dp->aux_power_domain = POWER_DOMAIN_AUX_B; |
b71953a1 ACO |
5887 | break; |
5888 | case PORT_C: | |
5889 | encoder->hpd_pin = HPD_PORT_C; | |
5432fcaf | 5890 | intel_dp->aux_power_domain = POWER_DOMAIN_AUX_C; |
b71953a1 ACO |
5891 | break; |
5892 | case PORT_D: | |
5893 | encoder->hpd_pin = HPD_PORT_D; | |
5432fcaf | 5894 | intel_dp->aux_power_domain = POWER_DOMAIN_AUX_D; |
b71953a1 ACO |
5895 | break; |
5896 | case PORT_E: | |
5897 | encoder->hpd_pin = HPD_PORT_E; | |
5432fcaf ACO |
5898 | |
5899 | /* FIXME: Check VBT for actual wiring of PORT E */ | |
5900 | intel_dp->aux_power_domain = POWER_DOMAIN_AUX_D; | |
b71953a1 ACO |
5901 | break; |
5902 | default: | |
5903 | MISSING_CASE(intel_dig_port->port); | |
5904 | } | |
5905 | } | |
5906 | ||
9301397a MN |
5907 | static void intel_dp_modeset_retry_work_fn(struct work_struct *work) |
5908 | { | |
5909 | struct intel_connector *intel_connector; | |
5910 | struct drm_connector *connector; | |
5911 | ||
5912 | intel_connector = container_of(work, typeof(*intel_connector), | |
5913 | modeset_retry_work); | |
5914 | connector = &intel_connector->base; | |
5915 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id, | |
5916 | connector->name); | |
5917 | ||
5918 | /* Grab the locks before changing connector property*/ | |
5919 | mutex_lock(&connector->dev->mode_config.mutex); | |
5920 | /* Set connector link status to BAD and send a Uevent to notify | |
5921 | * userspace to do a modeset. | |
5922 | */ | |
5923 | drm_mode_connector_set_link_status_property(connector, | |
5924 | DRM_MODE_LINK_STATUS_BAD); | |
5925 | mutex_unlock(&connector->dev->mode_config.mutex); | |
5926 | /* Send Hotplug uevent so userspace can reprobe */ | |
5927 | drm_kms_helper_hotplug_event(connector->dev); | |
5928 | } | |
5929 | ||
16c25533 | 5930 | bool |
f0fec3f2 PZ |
5931 | intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
5932 | struct intel_connector *intel_connector) | |
a4fc5ed6 | 5933 | { |
f0fec3f2 PZ |
5934 | struct drm_connector *connector = &intel_connector->base; |
5935 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
5936 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
5937 | struct drm_device *dev = intel_encoder->base.dev; | |
fac5e23e | 5938 | struct drm_i915_private *dev_priv = to_i915(dev); |
174edf1f | 5939 | enum port port = intel_dig_port->port; |
7a418e34 | 5940 | int type; |
a4fc5ed6 | 5941 | |
9301397a MN |
5942 | /* Initialize the work for modeset in case of link train failure */ |
5943 | INIT_WORK(&intel_connector->modeset_retry_work, | |
5944 | intel_dp_modeset_retry_work_fn); | |
5945 | ||
ccb1a831 VS |
5946 | if (WARN(intel_dig_port->max_lanes < 1, |
5947 | "Not enough lanes (%d) for DP on port %c\n", | |
5948 | intel_dig_port->max_lanes, port_name(port))) | |
5949 | return false; | |
5950 | ||
55cfc580 JN |
5951 | intel_dp_set_source_rates(intel_dp); |
5952 | ||
d7e8ef02 | 5953 | intel_dp->reset_link_params = true; |
a4a5d2f8 | 5954 | intel_dp->pps_pipe = INVALID_PIPE; |
9f2bdb00 | 5955 | intel_dp->active_pipe = INVALID_PIPE; |
a4a5d2f8 | 5956 | |
ec5b01dd | 5957 | /* intel_dp vfuncs */ |
dd11bc10 | 5958 | if (INTEL_GEN(dev_priv) >= 9) |
b6b5e383 | 5959 | intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; |
8652744b | 5960 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
ec5b01dd | 5961 | intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; |
6e266956 | 5962 | else if (HAS_PCH_SPLIT(dev_priv)) |
ec5b01dd DL |
5963 | intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; |
5964 | else | |
6ffb1be7 | 5965 | intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider; |
ec5b01dd | 5966 | |
dd11bc10 | 5967 | if (INTEL_GEN(dev_priv) >= 9) |
b9ca5fad DL |
5968 | intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; |
5969 | else | |
6ffb1be7 | 5970 | intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl; |
153b1100 | 5971 | |
4f8036a2 | 5972 | if (HAS_DDI(dev_priv)) |
ad64217b ACO |
5973 | intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain; |
5974 | ||
0767935e DV |
5975 | /* Preserve the current hw state. */ |
5976 | intel_dp->DP = I915_READ(intel_dp->output_reg); | |
dd06f90e | 5977 | intel_dp->attached_connector = intel_connector; |
3d3dc149 | 5978 | |
a3b29673 | 5979 | if (intel_dp_is_port_edp(dev_priv, port)) |
b329530c | 5980 | type = DRM_MODE_CONNECTOR_eDP; |
3b32a35b VS |
5981 | else |
5982 | type = DRM_MODE_CONNECTOR_DisplayPort; | |
b329530c | 5983 | |
9f2bdb00 VS |
5984 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
5985 | intel_dp->active_pipe = vlv_active_pipe(intel_dp); | |
5986 | ||
f7d24902 ID |
5987 | /* |
5988 | * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but | |
5989 | * for DP the encoder type can be set by the caller to | |
5990 | * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. | |
5991 | */ | |
5992 | if (type == DRM_MODE_CONNECTOR_eDP) | |
5993 | intel_encoder->type = INTEL_OUTPUT_EDP; | |
5994 | ||
c17ed5b5 | 5995 | /* eDP only on port B and/or C on vlv/chv */ |
920a14b2 | 5996 | if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
01a7507f JN |
5997 | intel_dp_is_edp(intel_dp) && |
5998 | port != PORT_B && port != PORT_C)) | |
c17ed5b5 VS |
5999 | return false; |
6000 | ||
e7281eab ID |
6001 | DRM_DEBUG_KMS("Adding %s connector on port %c\n", |
6002 | type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", | |
6003 | port_name(port)); | |
6004 | ||
b329530c | 6005 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
a4fc5ed6 KP |
6006 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
6007 | ||
a4fc5ed6 KP |
6008 | connector->interlace_allowed = true; |
6009 | connector->doublescan_allowed = 0; | |
6010 | ||
5432fcaf ACO |
6011 | intel_dp_init_connector_port_info(intel_dig_port); |
6012 | ||
b6339585 | 6013 | intel_dp_aux_init(intel_dp); |
7a418e34 | 6014 | |
f0fec3f2 | 6015 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, |
4be73780 | 6016 | edp_panel_vdd_work); |
a4fc5ed6 | 6017 | |
df0e9248 | 6018 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
a4fc5ed6 | 6019 | |
4f8036a2 | 6020 | if (HAS_DDI(dev_priv)) |
bcbc889b PZ |
6021 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
6022 | else | |
6023 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
6024 | ||
0e32b39c | 6025 | /* init MST on ports that can support it */ |
01a7507f | 6026 | if (HAS_DP_MST(dev_priv) && !intel_dp_is_edp(intel_dp) && |
0c9b3715 JN |
6027 | (port == PORT_B || port == PORT_C || port == PORT_D)) |
6028 | intel_dp_mst_encoder_init(intel_dig_port, | |
6029 | intel_connector->base.base.id); | |
0e32b39c | 6030 | |
36b5f425 | 6031 | if (!intel_edp_init_connector(intel_dp, intel_connector)) { |
a121f4e5 VS |
6032 | intel_dp_aux_fini(intel_dp); |
6033 | intel_dp_mst_encoder_cleanup(intel_dig_port); | |
6034 | goto fail; | |
b2f246a8 | 6035 | } |
32f9d658 | 6036 | |
f684960e CW |
6037 | intel_dp_add_properties(intel_dp, connector); |
6038 | ||
a4fc5ed6 KP |
6039 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
6040 | * 0xd. Failure to do so will result in spurious interrupts being | |
6041 | * generated on the port when a cable is not attached. | |
6042 | */ | |
50a0bc90 | 6043 | if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) { |
a4fc5ed6 KP |
6044 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
6045 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
6046 | } | |
16c25533 PZ |
6047 | |
6048 | return true; | |
a121f4e5 VS |
6049 | |
6050 | fail: | |
a121f4e5 VS |
6051 | drm_connector_cleanup(connector); |
6052 | ||
6053 | return false; | |
a4fc5ed6 | 6054 | } |
f0fec3f2 | 6055 | |
c39055b0 | 6056 | bool intel_dp_init(struct drm_i915_private *dev_priv, |
457c52d8 CW |
6057 | i915_reg_t output_reg, |
6058 | enum port port) | |
f0fec3f2 PZ |
6059 | { |
6060 | struct intel_digital_port *intel_dig_port; | |
6061 | struct intel_encoder *intel_encoder; | |
6062 | struct drm_encoder *encoder; | |
6063 | struct intel_connector *intel_connector; | |
6064 | ||
b14c5679 | 6065 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
f0fec3f2 | 6066 | if (!intel_dig_port) |
457c52d8 | 6067 | return false; |
f0fec3f2 | 6068 | |
08d9bc92 | 6069 | intel_connector = intel_connector_alloc(); |
11aee0f6 SM |
6070 | if (!intel_connector) |
6071 | goto err_connector_alloc; | |
f0fec3f2 PZ |
6072 | |
6073 | intel_encoder = &intel_dig_port->base; | |
6074 | encoder = &intel_encoder->base; | |
6075 | ||
c39055b0 ACO |
6076 | if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base, |
6077 | &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS, | |
6078 | "DP %c", port_name(port))) | |
893da0c9 | 6079 | goto err_encoder_init; |
f0fec3f2 | 6080 | |
5bfe2ac0 | 6081 | intel_encoder->compute_config = intel_dp_compute_config; |
00c09d70 | 6082 | intel_encoder->disable = intel_disable_dp; |
00c09d70 | 6083 | intel_encoder->get_hw_state = intel_dp_get_hw_state; |
045ac3b5 | 6084 | intel_encoder->get_config = intel_dp_get_config; |
07f9cd0b | 6085 | intel_encoder->suspend = intel_dp_encoder_suspend; |
920a14b2 | 6086 | if (IS_CHERRYVIEW(dev_priv)) { |
9197c88b | 6087 | intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; |
e4a1d846 CML |
6088 | intel_encoder->pre_enable = chv_pre_enable_dp; |
6089 | intel_encoder->enable = vlv_enable_dp; | |
580d3811 | 6090 | intel_encoder->post_disable = chv_post_disable_dp; |
d6db995f | 6091 | intel_encoder->post_pll_disable = chv_dp_post_pll_disable; |
11a914c2 | 6092 | } else if (IS_VALLEYVIEW(dev_priv)) { |
ecff4f3b | 6093 | intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; |
ab1f90f9 JN |
6094 | intel_encoder->pre_enable = vlv_pre_enable_dp; |
6095 | intel_encoder->enable = vlv_enable_dp; | |
49277c31 | 6096 | intel_encoder->post_disable = vlv_post_disable_dp; |
ab1f90f9 | 6097 | } else { |
ecff4f3b JN |
6098 | intel_encoder->pre_enable = g4x_pre_enable_dp; |
6099 | intel_encoder->enable = g4x_enable_dp; | |
dd11bc10 | 6100 | if (INTEL_GEN(dev_priv) >= 5) |
08aff3fe | 6101 | intel_encoder->post_disable = ilk_post_disable_dp; |
ab1f90f9 | 6102 | } |
f0fec3f2 | 6103 | |
174edf1f | 6104 | intel_dig_port->port = port; |
f0fec3f2 | 6105 | intel_dig_port->dp.output_reg = output_reg; |
ccb1a831 | 6106 | intel_dig_port->max_lanes = 4; |
f0fec3f2 | 6107 | |
cca0502b | 6108 | intel_encoder->type = INTEL_OUTPUT_DP; |
79f255a0 | 6109 | intel_encoder->power_domain = intel_port_to_power_domain(port); |
920a14b2 | 6110 | if (IS_CHERRYVIEW(dev_priv)) { |
882ec384 VS |
6111 | if (port == PORT_D) |
6112 | intel_encoder->crtc_mask = 1 << 2; | |
6113 | else | |
6114 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
6115 | } else { | |
6116 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
6117 | } | |
bc079e8b | 6118 | intel_encoder->cloneable = 0; |
03cdc1d4 | 6119 | intel_encoder->port = port; |
f0fec3f2 | 6120 | |
13cf5504 | 6121 | intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; |
5fcece80 | 6122 | dev_priv->hotplug.irq_port[port] = intel_dig_port; |
13cf5504 | 6123 | |
11aee0f6 SM |
6124 | if (!intel_dp_init_connector(intel_dig_port, intel_connector)) |
6125 | goto err_init_connector; | |
6126 | ||
457c52d8 | 6127 | return true; |
11aee0f6 SM |
6128 | |
6129 | err_init_connector: | |
6130 | drm_encoder_cleanup(encoder); | |
893da0c9 | 6131 | err_encoder_init: |
11aee0f6 SM |
6132 | kfree(intel_connector); |
6133 | err_connector_alloc: | |
6134 | kfree(intel_dig_port); | |
457c52d8 | 6135 | return false; |
f0fec3f2 | 6136 | } |
0e32b39c DA |
6137 | |
6138 | void intel_dp_mst_suspend(struct drm_device *dev) | |
6139 | { | |
fac5e23e | 6140 | struct drm_i915_private *dev_priv = to_i915(dev); |
0e32b39c DA |
6141 | int i; |
6142 | ||
6143 | /* disable MST */ | |
6144 | for (i = 0; i < I915_MAX_PORTS; i++) { | |
5fcece80 | 6145 | struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; |
5aa56969 VS |
6146 | |
6147 | if (!intel_dig_port || !intel_dig_port->dp.can_mst) | |
0e32b39c DA |
6148 | continue; |
6149 | ||
5aa56969 VS |
6150 | if (intel_dig_port->dp.is_mst) |
6151 | drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr); | |
0e32b39c DA |
6152 | } |
6153 | } | |
6154 | ||
6155 | void intel_dp_mst_resume(struct drm_device *dev) | |
6156 | { | |
fac5e23e | 6157 | struct drm_i915_private *dev_priv = to_i915(dev); |
0e32b39c DA |
6158 | int i; |
6159 | ||
6160 | for (i = 0; i < I915_MAX_PORTS; i++) { | |
5fcece80 | 6161 | struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; |
5aa56969 | 6162 | int ret; |
0e32b39c | 6163 | |
5aa56969 VS |
6164 | if (!intel_dig_port || !intel_dig_port->dp.can_mst) |
6165 | continue; | |
0e32b39c | 6166 | |
5aa56969 VS |
6167 | ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr); |
6168 | if (ret) | |
6169 | intel_dp_check_mst_status(&intel_dig_port->dp); | |
0e32b39c DA |
6170 | } |
6171 | } |