2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/types.h>
32 #include <linux/notifier.h>
33 #include <linux/reboot.h>
34 #include <asm/byteorder.h>
36 #include <drm/drm_atomic_helper.h>
37 #include <drm/drm_crtc.h>
38 #include <drm/drm_crtc_helper.h>
39 #include <drm/drm_edid.h>
40 #include "intel_drv.h"
41 #include <drm/i915_drm.h>
44 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
46 /* Compliance test status bits */
47 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
48 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
49 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
50 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
57 static const struct dp_link_dpll gen4_dpll
[] = {
59 { .p1
= 2, .p2
= 10, .n
= 2, .m1
= 23, .m2
= 8 } },
61 { .p1
= 1, .p2
= 10, .n
= 1, .m1
= 14, .m2
= 2 } }
64 static const struct dp_link_dpll pch_dpll
[] = {
66 { .p1
= 2, .p2
= 10, .n
= 1, .m1
= 12, .m2
= 9 } },
68 { .p1
= 1, .p2
= 10, .n
= 2, .m1
= 14, .m2
= 8 } }
71 static const struct dp_link_dpll vlv_dpll
[] = {
73 { .p1
= 3, .p2
= 2, .n
= 5, .m1
= 3, .m2
= 81 } },
75 { .p1
= 2, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 27 } }
79 * CHV supports eDP 1.4 that have more link rates.
80 * Below only provides the fixed rate but exclude variable rate.
82 static const struct dp_link_dpll chv_dpll
[] = {
84 * CHV requires to program fractional division for m2.
85 * m2 is stored in fixed point format using formula below
86 * (m2_int << 22) | m2_fraction
88 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
89 { .p1
= 4, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 0x819999a } },
90 { 270000, /* m2_int = 27, m2_fraction = 0 */
91 { .p1
= 4, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } },
92 { 540000, /* m2_int = 27, m2_fraction = 0 */
93 { .p1
= 2, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } }
96 static const int bxt_rates
[] = { 162000, 216000, 243000, 270000,
97 324000, 432000, 540000 };
98 static const int skl_rates
[] = { 162000, 216000, 270000,
99 324000, 432000, 540000 };
100 static const int default_rates
[] = { 162000, 270000, 540000 };
103 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
104 * @intel_dp: DP struct
106 * If a CPU or PCH DP output is attached to an eDP panel, this function
107 * will return true, and false otherwise.
109 bool intel_dp_is_edp(struct intel_dp
*intel_dp
)
111 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
113 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
116 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
118 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
120 return intel_dig_port
->base
.base
.dev
;
123 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
125 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
128 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
129 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
);
130 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
131 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
);
132 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
134 static void intel_dp_unset_edid(struct intel_dp
*intel_dp
);
136 static int intel_dp_num_rates(u8 link_bw_code
)
138 switch (link_bw_code
) {
140 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
142 case DP_LINK_BW_1_62
:
151 /* update sink rates from dpcd */
152 static void intel_dp_set_sink_rates(struct intel_dp
*intel_dp
)
156 num_rates
= intel_dp_num_rates(intel_dp
->dpcd
[DP_MAX_LINK_RATE
]);
158 for (i
= 0; i
< num_rates
; i
++)
159 intel_dp
->sink_rates
[i
] = default_rates
[i
];
161 intel_dp
->num_sink_rates
= num_rates
;
164 /* Theoretical max between source and sink */
165 static int intel_dp_max_common_rate(struct intel_dp
*intel_dp
)
167 return intel_dp
->common_rates
[intel_dp
->num_common_rates
- 1];
170 /* Theoretical max between source and sink */
171 static int intel_dp_max_common_lane_count(struct intel_dp
*intel_dp
)
173 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
174 int source_max
= intel_dig_port
->max_lanes
;
175 int sink_max
= drm_dp_max_lane_count(intel_dp
->dpcd
);
177 return min(source_max
, sink_max
);
180 int intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
182 return intel_dp
->max_link_lane_count
;
186 intel_dp_link_required(int pixel_clock
, int bpp
)
188 /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
189 return DIV_ROUND_UP(pixel_clock
* bpp
, 8);
193 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
195 /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
196 * link rate that is generally expressed in Gbps. Since, 8 bits of data
197 * is transmitted every LS_Clk per lane, there is no need to account for
198 * the channel encoding that is done in the PHY layer here.
201 return max_link_clock
* max_lanes
;
205 intel_dp_downstream_max_dotclock(struct intel_dp
*intel_dp
)
207 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
208 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
209 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
210 int max_dotclk
= dev_priv
->max_dotclk_freq
;
213 int type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
215 if (type
!= DP_DS_PORT_TYPE_VGA
)
218 ds_max_dotclk
= drm_dp_downstream_max_clock(intel_dp
->dpcd
,
219 intel_dp
->downstream_ports
);
221 if (ds_max_dotclk
!= 0)
222 max_dotclk
= min(max_dotclk
, ds_max_dotclk
);
228 intel_dp_set_source_rates(struct intel_dp
*intel_dp
)
230 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
231 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
232 const int *source_rates
;
235 /* This should only be done once */
236 WARN_ON(intel_dp
->source_rates
|| intel_dp
->num_source_rates
);
238 if (IS_GEN9_LP(dev_priv
)) {
239 source_rates
= bxt_rates
;
240 size
= ARRAY_SIZE(bxt_rates
);
241 } else if (IS_GEN9_BC(dev_priv
)) {
242 source_rates
= skl_rates
;
243 size
= ARRAY_SIZE(skl_rates
);
245 source_rates
= default_rates
;
246 size
= ARRAY_SIZE(default_rates
);
249 /* This depends on the fact that 5.4 is last value in the array */
250 if (!intel_dp_source_supports_hbr2(intel_dp
))
253 intel_dp
->source_rates
= source_rates
;
254 intel_dp
->num_source_rates
= size
;
257 static int intersect_rates(const int *source_rates
, int source_len
,
258 const int *sink_rates
, int sink_len
,
261 int i
= 0, j
= 0, k
= 0;
263 while (i
< source_len
&& j
< sink_len
) {
264 if (source_rates
[i
] == sink_rates
[j
]) {
265 if (WARN_ON(k
>= DP_MAX_SUPPORTED_RATES
))
267 common_rates
[k
] = source_rates
[i
];
271 } else if (source_rates
[i
] < sink_rates
[j
]) {
280 /* return index of rate in rates array, or -1 if not found */
281 static int intel_dp_rate_index(const int *rates
, int len
, int rate
)
285 for (i
= 0; i
< len
; i
++)
286 if (rate
== rates
[i
])
292 static void intel_dp_set_common_rates(struct intel_dp
*intel_dp
)
294 WARN_ON(!intel_dp
->num_source_rates
|| !intel_dp
->num_sink_rates
);
296 intel_dp
->num_common_rates
= intersect_rates(intel_dp
->source_rates
,
297 intel_dp
->num_source_rates
,
298 intel_dp
->sink_rates
,
299 intel_dp
->num_sink_rates
,
300 intel_dp
->common_rates
);
302 /* Paranoia, there should always be something in common. */
303 if (WARN_ON(intel_dp
->num_common_rates
== 0)) {
304 intel_dp
->common_rates
[0] = default_rates
[0];
305 intel_dp
->num_common_rates
= 1;
309 /* get length of common rates potentially limited by max_rate */
310 static int intel_dp_common_len_rate_limit(struct intel_dp
*intel_dp
,
313 const int *common_rates
= intel_dp
->common_rates
;
314 int i
, common_len
= intel_dp
->num_common_rates
;
316 /* Limit results by potentially reduced max rate */
317 for (i
= 0; i
< common_len
; i
++) {
318 if (common_rates
[common_len
- i
- 1] <= max_rate
)
319 return common_len
- i
;
325 static bool intel_dp_link_params_valid(struct intel_dp
*intel_dp
)
328 * FIXME: we need to synchronize the current link parameters with
329 * hardware readout. Currently fast link training doesn't work on
332 if (intel_dp
->link_rate
== 0 ||
333 intel_dp
->link_rate
> intel_dp
->max_link_rate
)
336 if (intel_dp
->lane_count
== 0 ||
337 intel_dp
->lane_count
> intel_dp_max_lane_count(intel_dp
))
343 int intel_dp_get_link_train_fallback_values(struct intel_dp
*intel_dp
,
344 int link_rate
, uint8_t lane_count
)
348 index
= intel_dp_rate_index(intel_dp
->common_rates
,
349 intel_dp
->num_common_rates
,
352 intel_dp
->max_link_rate
= intel_dp
->common_rates
[index
- 1];
353 intel_dp
->max_link_lane_count
= lane_count
;
354 } else if (lane_count
> 1) {
355 intel_dp
->max_link_rate
= intel_dp_max_common_rate(intel_dp
);
356 intel_dp
->max_link_lane_count
= lane_count
>> 1;
358 DRM_ERROR("Link Training Unsuccessful\n");
365 static enum drm_mode_status
366 intel_dp_mode_valid(struct drm_connector
*connector
,
367 struct drm_display_mode
*mode
)
369 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
370 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
371 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
372 int target_clock
= mode
->clock
;
373 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
376 max_dotclk
= intel_dp_downstream_max_dotclock(intel_dp
);
378 if (intel_dp_is_edp(intel_dp
) && fixed_mode
) {
379 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
382 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
385 target_clock
= fixed_mode
->clock
;
388 max_link_clock
= intel_dp_max_link_rate(intel_dp
);
389 max_lanes
= intel_dp_max_lane_count(intel_dp
);
391 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
392 mode_rate
= intel_dp_link_required(target_clock
, 18);
394 if (mode_rate
> max_rate
|| target_clock
> max_dotclk
)
395 return MODE_CLOCK_HIGH
;
397 if (mode
->clock
< 10000)
398 return MODE_CLOCK_LOW
;
400 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
401 return MODE_H_ILLEGAL
;
406 uint32_t intel_dp_pack_aux(const uint8_t *src
, int src_bytes
)
413 for (i
= 0; i
< src_bytes
; i
++)
414 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
418 static void intel_dp_unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
423 for (i
= 0; i
< dst_bytes
; i
++)
424 dst
[i
] = src
>> ((3-i
) * 8);
428 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
429 struct intel_dp
*intel_dp
);
431 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
432 struct intel_dp
*intel_dp
,
433 bool force_disable_vdd
);
435 intel_dp_pps_init(struct drm_device
*dev
, struct intel_dp
*intel_dp
);
437 static void pps_lock(struct intel_dp
*intel_dp
)
439 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
440 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
441 struct drm_device
*dev
= encoder
->base
.dev
;
442 struct drm_i915_private
*dev_priv
= to_i915(dev
);
445 * See vlv_power_sequencer_reset() why we need
446 * a power domain reference here.
448 intel_display_power_get(dev_priv
, intel_dp
->aux_power_domain
);
450 mutex_lock(&dev_priv
->pps_mutex
);
453 static void pps_unlock(struct intel_dp
*intel_dp
)
455 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
456 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
457 struct drm_device
*dev
= encoder
->base
.dev
;
458 struct drm_i915_private
*dev_priv
= to_i915(dev
);
460 mutex_unlock(&dev_priv
->pps_mutex
);
462 intel_display_power_put(dev_priv
, intel_dp
->aux_power_domain
);
466 vlv_power_sequencer_kick(struct intel_dp
*intel_dp
)
468 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
469 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
470 enum pipe pipe
= intel_dp
->pps_pipe
;
471 bool pll_enabled
, release_cl_override
= false;
472 enum dpio_phy phy
= DPIO_PHY(pipe
);
473 enum dpio_channel ch
= vlv_pipe_to_channel(pipe
);
476 if (WARN(I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
,
477 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
478 pipe_name(pipe
), port_name(intel_dig_port
->port
)))
481 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
482 pipe_name(pipe
), port_name(intel_dig_port
->port
));
484 /* Preserve the BIOS-computed detected bit. This is
485 * supposed to be read-only.
487 DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
488 DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
489 DP
|= DP_PORT_WIDTH(1);
490 DP
|= DP_LINK_TRAIN_PAT_1
;
492 if (IS_CHERRYVIEW(dev_priv
))
493 DP
|= DP_PIPE_SELECT_CHV(pipe
);
494 else if (pipe
== PIPE_B
)
495 DP
|= DP_PIPEB_SELECT
;
497 pll_enabled
= I915_READ(DPLL(pipe
)) & DPLL_VCO_ENABLE
;
500 * The DPLL for the pipe must be enabled for this to work.
501 * So enable temporarily it if it's not already enabled.
504 release_cl_override
= IS_CHERRYVIEW(dev_priv
) &&
505 !chv_phy_powergate_ch(dev_priv
, phy
, ch
, true);
507 if (vlv_force_pll_on(dev_priv
, pipe
, IS_CHERRYVIEW(dev_priv
) ?
508 &chv_dpll
[0].dpll
: &vlv_dpll
[0].dpll
)) {
509 DRM_ERROR("Failed to force on pll for pipe %c!\n",
516 * Similar magic as in intel_dp_enable_port().
517 * We _must_ do this port enable + disable trick
518 * to make this power seqeuencer lock onto the port.
519 * Otherwise even VDD force bit won't work.
521 I915_WRITE(intel_dp
->output_reg
, DP
);
522 POSTING_READ(intel_dp
->output_reg
);
524 I915_WRITE(intel_dp
->output_reg
, DP
| DP_PORT_EN
);
525 POSTING_READ(intel_dp
->output_reg
);
527 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
528 POSTING_READ(intel_dp
->output_reg
);
531 vlv_force_pll_off(dev_priv
, pipe
);
533 if (release_cl_override
)
534 chv_phy_powergate_ch(dev_priv
, phy
, ch
, false);
538 static enum pipe
vlv_find_free_pps(struct drm_i915_private
*dev_priv
)
540 struct intel_encoder
*encoder
;
541 unsigned int pipes
= (1 << PIPE_A
) | (1 << PIPE_B
);
544 * We don't have power sequencer currently.
545 * Pick one that's not used by other ports.
547 for_each_intel_encoder(&dev_priv
->drm
, encoder
) {
548 struct intel_dp
*intel_dp
;
550 if (encoder
->type
!= INTEL_OUTPUT_DP
&&
551 encoder
->type
!= INTEL_OUTPUT_EDP
)
554 intel_dp
= enc_to_intel_dp(&encoder
->base
);
556 if (encoder
->type
== INTEL_OUTPUT_EDP
) {
557 WARN_ON(intel_dp
->active_pipe
!= INVALID_PIPE
&&
558 intel_dp
->active_pipe
!= intel_dp
->pps_pipe
);
560 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
561 pipes
&= ~(1 << intel_dp
->pps_pipe
);
563 WARN_ON(intel_dp
->pps_pipe
!= INVALID_PIPE
);
565 if (intel_dp
->active_pipe
!= INVALID_PIPE
)
566 pipes
&= ~(1 << intel_dp
->active_pipe
);
573 return ffs(pipes
) - 1;
577 vlv_power_sequencer_pipe(struct intel_dp
*intel_dp
)
579 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
580 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
581 struct drm_i915_private
*dev_priv
= to_i915(dev
);
584 lockdep_assert_held(&dev_priv
->pps_mutex
);
586 /* We should never land here with regular DP ports */
587 WARN_ON(!intel_dp_is_edp(intel_dp
));
589 WARN_ON(intel_dp
->active_pipe
!= INVALID_PIPE
&&
590 intel_dp
->active_pipe
!= intel_dp
->pps_pipe
);
592 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
593 return intel_dp
->pps_pipe
;
595 pipe
= vlv_find_free_pps(dev_priv
);
598 * Didn't find one. This should not happen since there
599 * are two power sequencers and up to two eDP ports.
601 if (WARN_ON(pipe
== INVALID_PIPE
))
604 vlv_steal_power_sequencer(dev
, pipe
);
605 intel_dp
->pps_pipe
= pipe
;
607 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
608 pipe_name(intel_dp
->pps_pipe
),
609 port_name(intel_dig_port
->port
));
611 /* init power sequencer on this pipe and port */
612 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
613 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
, true);
616 * Even vdd force doesn't work until we've made
617 * the power sequencer lock in on the port.
619 vlv_power_sequencer_kick(intel_dp
);
621 return intel_dp
->pps_pipe
;
625 bxt_power_sequencer_idx(struct intel_dp
*intel_dp
)
627 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
628 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
629 struct drm_i915_private
*dev_priv
= to_i915(dev
);
631 lockdep_assert_held(&dev_priv
->pps_mutex
);
633 /* We should never land here with regular DP ports */
634 WARN_ON(!intel_dp_is_edp(intel_dp
));
637 * TODO: BXT has 2 PPS instances. The correct port->PPS instance
638 * mapping needs to be retrieved from VBT, for now just hard-code to
639 * use instance #0 always.
641 if (!intel_dp
->pps_reset
)
644 intel_dp
->pps_reset
= false;
647 * Only the HW needs to be reprogrammed, the SW state is fixed and
648 * has been setup during connector init.
650 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
, false);
655 typedef bool (*vlv_pipe_check
)(struct drm_i915_private
*dev_priv
,
658 static bool vlv_pipe_has_pp_on(struct drm_i915_private
*dev_priv
,
661 return I915_READ(PP_STATUS(pipe
)) & PP_ON
;
664 static bool vlv_pipe_has_vdd_on(struct drm_i915_private
*dev_priv
,
667 return I915_READ(PP_CONTROL(pipe
)) & EDP_FORCE_VDD
;
670 static bool vlv_pipe_any(struct drm_i915_private
*dev_priv
,
677 vlv_initial_pps_pipe(struct drm_i915_private
*dev_priv
,
679 vlv_pipe_check pipe_check
)
683 for (pipe
= PIPE_A
; pipe
<= PIPE_B
; pipe
++) {
684 u32 port_sel
= I915_READ(PP_ON_DELAYS(pipe
)) &
685 PANEL_PORT_SELECT_MASK
;
687 if (port_sel
!= PANEL_PORT_SELECT_VLV(port
))
690 if (!pipe_check(dev_priv
, pipe
))
700 vlv_initial_power_sequencer_setup(struct intel_dp
*intel_dp
)
702 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
703 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
704 struct drm_i915_private
*dev_priv
= to_i915(dev
);
705 enum port port
= intel_dig_port
->port
;
707 lockdep_assert_held(&dev_priv
->pps_mutex
);
709 /* try to find a pipe with this port selected */
710 /* first pick one where the panel is on */
711 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
713 /* didn't find one? pick one where vdd is on */
714 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
715 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
716 vlv_pipe_has_vdd_on
);
717 /* didn't find one? pick one with just the correct port */
718 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
719 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
722 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
723 if (intel_dp
->pps_pipe
== INVALID_PIPE
) {
724 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
729 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
730 port_name(port
), pipe_name(intel_dp
->pps_pipe
));
732 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
733 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
, false);
736 void intel_power_sequencer_reset(struct drm_i915_private
*dev_priv
)
738 struct drm_device
*dev
= &dev_priv
->drm
;
739 struct intel_encoder
*encoder
;
741 if (WARN_ON(!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
) &&
742 !IS_GEN9_LP(dev_priv
)))
746 * We can't grab pps_mutex here due to deadlock with power_domain
747 * mutex when power_domain functions are called while holding pps_mutex.
748 * That also means that in order to use pps_pipe the code needs to
749 * hold both a power domain reference and pps_mutex, and the power domain
750 * reference get/put must be done while _not_ holding pps_mutex.
751 * pps_{lock,unlock}() do these steps in the correct order, so one
752 * should use them always.
755 for_each_intel_encoder(dev
, encoder
) {
756 struct intel_dp
*intel_dp
;
758 if (encoder
->type
!= INTEL_OUTPUT_DP
&&
759 encoder
->type
!= INTEL_OUTPUT_EDP
)
762 intel_dp
= enc_to_intel_dp(&encoder
->base
);
764 WARN_ON(intel_dp
->active_pipe
!= INVALID_PIPE
);
766 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
769 if (IS_GEN9_LP(dev_priv
))
770 intel_dp
->pps_reset
= true;
772 intel_dp
->pps_pipe
= INVALID_PIPE
;
776 struct pps_registers
{
784 static void intel_pps_get_registers(struct drm_i915_private
*dev_priv
,
785 struct intel_dp
*intel_dp
,
786 struct pps_registers
*regs
)
790 memset(regs
, 0, sizeof(*regs
));
792 if (IS_GEN9_LP(dev_priv
))
793 pps_idx
= bxt_power_sequencer_idx(intel_dp
);
794 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
795 pps_idx
= vlv_power_sequencer_pipe(intel_dp
);
797 regs
->pp_ctrl
= PP_CONTROL(pps_idx
);
798 regs
->pp_stat
= PP_STATUS(pps_idx
);
799 regs
->pp_on
= PP_ON_DELAYS(pps_idx
);
800 regs
->pp_off
= PP_OFF_DELAYS(pps_idx
);
801 if (!IS_GEN9_LP(dev_priv
) && !HAS_PCH_CNP(dev_priv
))
802 regs
->pp_div
= PP_DIVISOR(pps_idx
);
806 _pp_ctrl_reg(struct intel_dp
*intel_dp
)
808 struct pps_registers regs
;
810 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp
)), intel_dp
,
817 _pp_stat_reg(struct intel_dp
*intel_dp
)
819 struct pps_registers regs
;
821 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp
)), intel_dp
,
827 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
828 This function only applicable when panel PM state is not to be tracked */
829 static int edp_notify_handler(struct notifier_block
*this, unsigned long code
,
832 struct intel_dp
*intel_dp
= container_of(this, typeof(* intel_dp
),
834 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
835 struct drm_i915_private
*dev_priv
= to_i915(dev
);
837 if (!intel_dp_is_edp(intel_dp
) || code
!= SYS_RESTART
)
842 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
843 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
844 i915_reg_t pp_ctrl_reg
, pp_div_reg
;
847 pp_ctrl_reg
= PP_CONTROL(pipe
);
848 pp_div_reg
= PP_DIVISOR(pipe
);
849 pp_div
= I915_READ(pp_div_reg
);
850 pp_div
&= PP_REFERENCE_DIVIDER_MASK
;
852 /* 0x1F write to PP_DIV_REG sets max cycle delay */
853 I915_WRITE(pp_div_reg
, pp_div
| 0x1F);
854 I915_WRITE(pp_ctrl_reg
, PANEL_UNLOCK_REGS
| PANEL_POWER_OFF
);
855 msleep(intel_dp
->panel_power_cycle_delay
);
858 pps_unlock(intel_dp
);
863 static bool edp_have_panel_power(struct intel_dp
*intel_dp
)
865 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
866 struct drm_i915_private
*dev_priv
= to_i915(dev
);
868 lockdep_assert_held(&dev_priv
->pps_mutex
);
870 if ((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
871 intel_dp
->pps_pipe
== INVALID_PIPE
)
874 return (I915_READ(_pp_stat_reg(intel_dp
)) & PP_ON
) != 0;
877 static bool edp_have_panel_vdd(struct intel_dp
*intel_dp
)
879 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
880 struct drm_i915_private
*dev_priv
= to_i915(dev
);
882 lockdep_assert_held(&dev_priv
->pps_mutex
);
884 if ((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
885 intel_dp
->pps_pipe
== INVALID_PIPE
)
888 return I915_READ(_pp_ctrl_reg(intel_dp
)) & EDP_FORCE_VDD
;
892 intel_dp_check_edp(struct intel_dp
*intel_dp
)
894 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
895 struct drm_i915_private
*dev_priv
= to_i915(dev
);
897 if (!intel_dp_is_edp(intel_dp
))
900 if (!edp_have_panel_power(intel_dp
) && !edp_have_panel_vdd(intel_dp
)) {
901 WARN(1, "eDP powered off while attempting aux channel communication.\n");
902 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
903 I915_READ(_pp_stat_reg(intel_dp
)),
904 I915_READ(_pp_ctrl_reg(intel_dp
)));
909 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
911 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
912 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
913 struct drm_i915_private
*dev_priv
= to_i915(dev
);
914 i915_reg_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
918 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
920 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
921 msecs_to_jiffies_timeout(10));
923 done
= wait_for(C
, 10) == 0;
925 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
932 static uint32_t g4x_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
934 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
935 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
941 * The clock divider is based off the hrawclk, and would like to run at
942 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
944 return DIV_ROUND_CLOSEST(dev_priv
->rawclk_freq
, 2000);
947 static uint32_t ilk_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
949 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
950 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
956 * The clock divider is based off the cdclk or PCH rawclk, and would
957 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
958 * divide by 2000 and use that
960 if (intel_dig_port
->port
== PORT_A
)
961 return DIV_ROUND_CLOSEST(dev_priv
->cdclk
.hw
.cdclk
, 2000);
963 return DIV_ROUND_CLOSEST(dev_priv
->rawclk_freq
, 2000);
966 static uint32_t hsw_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
968 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
969 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
971 if (intel_dig_port
->port
!= PORT_A
&& HAS_PCH_LPT_H(dev_priv
)) {
972 /* Workaround for non-ULT HSW */
980 return ilk_get_aux_clock_divider(intel_dp
, index
);
983 static uint32_t skl_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
986 * SKL doesn't need us to program the AUX clock divider (Hardware will
987 * derive the clock from CDCLK automatically). We still implement the
988 * get_aux_clock_divider vfunc to plug-in into the existing code.
990 return index
? 0 : 1;
993 static uint32_t g4x_get_aux_send_ctl(struct intel_dp
*intel_dp
,
996 uint32_t aux_clock_divider
)
998 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
999 struct drm_i915_private
*dev_priv
=
1000 to_i915(intel_dig_port
->base
.base
.dev
);
1001 uint32_t precharge
, timeout
;
1003 if (IS_GEN6(dev_priv
))
1008 if (IS_BROADWELL(dev_priv
) && intel_dig_port
->port
== PORT_A
)
1009 timeout
= DP_AUX_CH_CTL_TIME_OUT_600us
;
1011 timeout
= DP_AUX_CH_CTL_TIME_OUT_400us
;
1013 return DP_AUX_CH_CTL_SEND_BUSY
|
1014 DP_AUX_CH_CTL_DONE
|
1015 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
1016 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
1018 DP_AUX_CH_CTL_RECEIVE_ERROR
|
1019 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
1020 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
1021 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
);
1024 static uint32_t skl_get_aux_send_ctl(struct intel_dp
*intel_dp
,
1029 return DP_AUX_CH_CTL_SEND_BUSY
|
1030 DP_AUX_CH_CTL_DONE
|
1031 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
1032 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
1033 DP_AUX_CH_CTL_TIME_OUT_1600us
|
1034 DP_AUX_CH_CTL_RECEIVE_ERROR
|
1035 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
1036 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1037 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1041 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
1042 const uint8_t *send
, int send_bytes
,
1043 uint8_t *recv
, int recv_size
)
1045 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1046 struct drm_i915_private
*dev_priv
=
1047 to_i915(intel_dig_port
->base
.base
.dev
);
1048 i915_reg_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
1049 uint32_t aux_clock_divider
;
1050 int i
, ret
, recv_bytes
;
1053 bool has_aux_irq
= HAS_AUX_IRQ(dev_priv
);
1059 * We will be called with VDD already enabled for dpcd/edid/oui reads.
1060 * In such cases we want to leave VDD enabled and it's up to upper layers
1061 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1064 vdd
= edp_panel_vdd_on(intel_dp
);
1066 /* dp aux is extremely sensitive to irq latency, hence request the
1067 * lowest possible wakeup latency and so prevent the cpu from going into
1068 * deep sleep states.
1070 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
1072 intel_dp_check_edp(intel_dp
);
1074 /* Try to wait for any previous AUX channel activity */
1075 for (try = 0; try < 3; try++) {
1076 status
= I915_READ_NOTRACE(ch_ctl
);
1077 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
1083 static u32 last_status
= -1;
1084 const u32 status
= I915_READ(ch_ctl
);
1086 if (status
!= last_status
) {
1087 WARN(1, "dp_aux_ch not started status 0x%08x\n",
1089 last_status
= status
;
1096 /* Only 5 data registers! */
1097 if (WARN_ON(send_bytes
> 20 || recv_size
> 20)) {
1102 while ((aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, clock
++))) {
1103 u32 send_ctl
= intel_dp
->get_aux_send_ctl(intel_dp
,
1108 /* Must try at least 3 times according to DP spec */
1109 for (try = 0; try < 5; try++) {
1110 /* Load the send data into the aux channel data registers */
1111 for (i
= 0; i
< send_bytes
; i
+= 4)
1112 I915_WRITE(intel_dp
->aux_ch_data_reg
[i
>> 2],
1113 intel_dp_pack_aux(send
+ i
,
1116 /* Send the command and wait for it to complete */
1117 I915_WRITE(ch_ctl
, send_ctl
);
1119 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
1121 /* Clear done status and any errors */
1124 DP_AUX_CH_CTL_DONE
|
1125 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
1126 DP_AUX_CH_CTL_RECEIVE_ERROR
);
1128 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
)
1131 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1132 * 400us delay required for errors and timeouts
1133 * Timeout errors from the HW already meet this
1134 * requirement so skip to next iteration
1136 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
1137 usleep_range(400, 500);
1140 if (status
& DP_AUX_CH_CTL_DONE
)
1145 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
1146 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
1152 /* Check for timeout or receive error.
1153 * Timeouts occur when the sink is not connected
1155 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
1156 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
1161 /* Timeouts occur when the device isn't connected, so they're
1162 * "normal" -- don't fill the kernel log with these */
1163 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
1164 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
1169 /* Unload any bytes sent back from the other side */
1170 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
1171 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
1174 * By BSpec: "Message sizes of 0 or >20 are not allowed."
1175 * We have no idea of what happened so we return -EBUSY so
1176 * drm layer takes care for the necessary retries.
1178 if (recv_bytes
== 0 || recv_bytes
> 20) {
1179 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1182 * FIXME: This patch was created on top of a series that
1183 * organize the retries at drm level. There EBUSY should
1184 * also take care for 1ms wait before retrying.
1185 * That aux retries re-org is still needed and after that is
1186 * merged we remove this sleep from here.
1188 usleep_range(1000, 1500);
1193 if (recv_bytes
> recv_size
)
1194 recv_bytes
= recv_size
;
1196 for (i
= 0; i
< recv_bytes
; i
+= 4)
1197 intel_dp_unpack_aux(I915_READ(intel_dp
->aux_ch_data_reg
[i
>> 2]),
1198 recv
+ i
, recv_bytes
- i
);
1202 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
1205 edp_panel_vdd_off(intel_dp
, false);
1207 pps_unlock(intel_dp
);
1212 #define BARE_ADDRESS_SIZE 3
1213 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
1215 intel_dp_aux_transfer(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*msg
)
1217 struct intel_dp
*intel_dp
= container_of(aux
, struct intel_dp
, aux
);
1218 uint8_t txbuf
[20], rxbuf
[20];
1219 size_t txsize
, rxsize
;
1222 txbuf
[0] = (msg
->request
<< 4) |
1223 ((msg
->address
>> 16) & 0xf);
1224 txbuf
[1] = (msg
->address
>> 8) & 0xff;
1225 txbuf
[2] = msg
->address
& 0xff;
1226 txbuf
[3] = msg
->size
- 1;
1228 switch (msg
->request
& ~DP_AUX_I2C_MOT
) {
1229 case DP_AUX_NATIVE_WRITE
:
1230 case DP_AUX_I2C_WRITE
:
1231 case DP_AUX_I2C_WRITE_STATUS_UPDATE
:
1232 txsize
= msg
->size
? HEADER_SIZE
+ msg
->size
: BARE_ADDRESS_SIZE
;
1233 rxsize
= 2; /* 0 or 1 data bytes */
1235 if (WARN_ON(txsize
> 20))
1238 WARN_ON(!msg
->buffer
!= !msg
->size
);
1241 memcpy(txbuf
+ HEADER_SIZE
, msg
->buffer
, msg
->size
);
1243 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
1245 msg
->reply
= rxbuf
[0] >> 4;
1248 /* Number of bytes written in a short write. */
1249 ret
= clamp_t(int, rxbuf
[1], 0, msg
->size
);
1251 /* Return payload size. */
1257 case DP_AUX_NATIVE_READ
:
1258 case DP_AUX_I2C_READ
:
1259 txsize
= msg
->size
? HEADER_SIZE
: BARE_ADDRESS_SIZE
;
1260 rxsize
= msg
->size
+ 1;
1262 if (WARN_ON(rxsize
> 20))
1265 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
1267 msg
->reply
= rxbuf
[0] >> 4;
1269 * Assume happy day, and copy the data. The caller is
1270 * expected to check msg->reply before touching it.
1272 * Return payload size.
1275 memcpy(msg
->buffer
, rxbuf
+ 1, ret
);
1287 static enum port
intel_aux_port(struct drm_i915_private
*dev_priv
,
1290 const struct ddi_vbt_port_info
*info
=
1291 &dev_priv
->vbt
.ddi_port_info
[port
];
1294 if (!info
->alternate_aux_channel
) {
1295 DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n",
1296 port_name(port
), port_name(port
));
1300 switch (info
->alternate_aux_channel
) {
1314 MISSING_CASE(info
->alternate_aux_channel
);
1319 DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n",
1320 port_name(aux_port
), port_name(port
));
1325 static i915_reg_t
g4x_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1332 return DP_AUX_CH_CTL(port
);
1335 return DP_AUX_CH_CTL(PORT_B
);
1339 static i915_reg_t
g4x_aux_data_reg(struct drm_i915_private
*dev_priv
,
1340 enum port port
, int index
)
1346 return DP_AUX_CH_DATA(port
, index
);
1349 return DP_AUX_CH_DATA(PORT_B
, index
);
1353 static i915_reg_t
ilk_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1358 return DP_AUX_CH_CTL(port
);
1362 return PCH_DP_AUX_CH_CTL(port
);
1365 return DP_AUX_CH_CTL(PORT_A
);
1369 static i915_reg_t
ilk_aux_data_reg(struct drm_i915_private
*dev_priv
,
1370 enum port port
, int index
)
1374 return DP_AUX_CH_DATA(port
, index
);
1378 return PCH_DP_AUX_CH_DATA(port
, index
);
1381 return DP_AUX_CH_DATA(PORT_A
, index
);
1385 static i915_reg_t
skl_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1393 return DP_AUX_CH_CTL(port
);
1396 return DP_AUX_CH_CTL(PORT_A
);
1400 static i915_reg_t
skl_aux_data_reg(struct drm_i915_private
*dev_priv
,
1401 enum port port
, int index
)
1408 return DP_AUX_CH_DATA(port
, index
);
1411 return DP_AUX_CH_DATA(PORT_A
, index
);
1415 static i915_reg_t
intel_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1418 if (INTEL_INFO(dev_priv
)->gen
>= 9)
1419 return skl_aux_ctl_reg(dev_priv
, port
);
1420 else if (HAS_PCH_SPLIT(dev_priv
))
1421 return ilk_aux_ctl_reg(dev_priv
, port
);
1423 return g4x_aux_ctl_reg(dev_priv
, port
);
1426 static i915_reg_t
intel_aux_data_reg(struct drm_i915_private
*dev_priv
,
1427 enum port port
, int index
)
1429 if (INTEL_INFO(dev_priv
)->gen
>= 9)
1430 return skl_aux_data_reg(dev_priv
, port
, index
);
1431 else if (HAS_PCH_SPLIT(dev_priv
))
1432 return ilk_aux_data_reg(dev_priv
, port
, index
);
1434 return g4x_aux_data_reg(dev_priv
, port
, index
);
1437 static void intel_aux_reg_init(struct intel_dp
*intel_dp
)
1439 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
1440 enum port port
= intel_aux_port(dev_priv
,
1441 dp_to_dig_port(intel_dp
)->port
);
1444 intel_dp
->aux_ch_ctl_reg
= intel_aux_ctl_reg(dev_priv
, port
);
1445 for (i
= 0; i
< ARRAY_SIZE(intel_dp
->aux_ch_data_reg
); i
++)
1446 intel_dp
->aux_ch_data_reg
[i
] = intel_aux_data_reg(dev_priv
, port
, i
);
1450 intel_dp_aux_fini(struct intel_dp
*intel_dp
)
1452 kfree(intel_dp
->aux
.name
);
1456 intel_dp_aux_init(struct intel_dp
*intel_dp
)
1458 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1459 enum port port
= intel_dig_port
->port
;
1461 intel_aux_reg_init(intel_dp
);
1462 drm_dp_aux_init(&intel_dp
->aux
);
1464 /* Failure to allocate our preferred name is not critical */
1465 intel_dp
->aux
.name
= kasprintf(GFP_KERNEL
, "DPDDC-%c", port_name(port
));
1466 intel_dp
->aux
.transfer
= intel_dp_aux_transfer
;
1469 bool intel_dp_source_supports_hbr2(struct intel_dp
*intel_dp
)
1471 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1472 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
1474 if ((IS_HASWELL(dev_priv
) && !IS_HSW_ULX(dev_priv
)) ||
1475 IS_BROADWELL(dev_priv
) || (INTEL_GEN(dev_priv
) >= 9))
1482 intel_dp_set_clock(struct intel_encoder
*encoder
,
1483 struct intel_crtc_state
*pipe_config
)
1485 struct drm_device
*dev
= encoder
->base
.dev
;
1486 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1487 const struct dp_link_dpll
*divisor
= NULL
;
1490 if (IS_G4X(dev_priv
)) {
1491 divisor
= gen4_dpll
;
1492 count
= ARRAY_SIZE(gen4_dpll
);
1493 } else if (HAS_PCH_SPLIT(dev_priv
)) {
1495 count
= ARRAY_SIZE(pch_dpll
);
1496 } else if (IS_CHERRYVIEW(dev_priv
)) {
1498 count
= ARRAY_SIZE(chv_dpll
);
1499 } else if (IS_VALLEYVIEW(dev_priv
)) {
1501 count
= ARRAY_SIZE(vlv_dpll
);
1504 if (divisor
&& count
) {
1505 for (i
= 0; i
< count
; i
++) {
1506 if (pipe_config
->port_clock
== divisor
[i
].clock
) {
1507 pipe_config
->dpll
= divisor
[i
].dpll
;
1508 pipe_config
->clock_set
= true;
1515 static void snprintf_int_array(char *str
, size_t len
,
1516 const int *array
, int nelem
)
1522 for (i
= 0; i
< nelem
; i
++) {
1523 int r
= snprintf(str
, len
, "%s%d", i
? ", " : "", array
[i
]);
1531 static void intel_dp_print_rates(struct intel_dp
*intel_dp
)
1533 char str
[128]; /* FIXME: too big for stack? */
1535 if ((drm_debug
& DRM_UT_KMS
) == 0)
1538 snprintf_int_array(str
, sizeof(str
),
1539 intel_dp
->source_rates
, intel_dp
->num_source_rates
);
1540 DRM_DEBUG_KMS("source rates: %s\n", str
);
1542 snprintf_int_array(str
, sizeof(str
),
1543 intel_dp
->sink_rates
, intel_dp
->num_sink_rates
);
1544 DRM_DEBUG_KMS("sink rates: %s\n", str
);
1546 snprintf_int_array(str
, sizeof(str
),
1547 intel_dp
->common_rates
, intel_dp
->num_common_rates
);
1548 DRM_DEBUG_KMS("common rates: %s\n", str
);
1552 intel_dp_max_link_rate(struct intel_dp
*intel_dp
)
1556 len
= intel_dp_common_len_rate_limit(intel_dp
, intel_dp
->max_link_rate
);
1557 if (WARN_ON(len
<= 0))
1560 return intel_dp
->common_rates
[len
- 1];
1563 int intel_dp_rate_select(struct intel_dp
*intel_dp
, int rate
)
1565 int i
= intel_dp_rate_index(intel_dp
->sink_rates
,
1566 intel_dp
->num_sink_rates
, rate
);
1574 void intel_dp_compute_rate(struct intel_dp
*intel_dp
, int port_clock
,
1575 uint8_t *link_bw
, uint8_t *rate_select
)
1577 /* eDP 1.4 rate select method. */
1578 if (intel_dp
->use_rate_select
) {
1581 intel_dp_rate_select(intel_dp
, port_clock
);
1583 *link_bw
= drm_dp_link_rate_to_bw_code(port_clock
);
1588 static int intel_dp_compute_bpp(struct intel_dp
*intel_dp
,
1589 struct intel_crtc_state
*pipe_config
)
1593 bpp
= pipe_config
->pipe_bpp
;
1594 bpc
= drm_dp_downstream_max_bpc(intel_dp
->dpcd
, intel_dp
->downstream_ports
);
1597 bpp
= min(bpp
, 3*bpc
);
1599 /* For DP Compliance we override the computed bpp for the pipe */
1600 if (intel_dp
->compliance
.test_data
.bpc
!= 0) {
1601 pipe_config
->pipe_bpp
= 3*intel_dp
->compliance
.test_data
.bpc
;
1602 pipe_config
->dither_force_disable
= pipe_config
->pipe_bpp
== 6*3;
1603 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n",
1604 pipe_config
->pipe_bpp
);
1609 static bool intel_edp_compare_alt_mode(struct drm_display_mode
*m1
,
1610 struct drm_display_mode
*m2
)
1615 bres
= (m1
->hdisplay
== m2
->hdisplay
&&
1616 m1
->hsync_start
== m2
->hsync_start
&&
1617 m1
->hsync_end
== m2
->hsync_end
&&
1618 m1
->htotal
== m2
->htotal
&&
1619 m1
->vdisplay
== m2
->vdisplay
&&
1620 m1
->vsync_start
== m2
->vsync_start
&&
1621 m1
->vsync_end
== m2
->vsync_end
&&
1622 m1
->vtotal
== m2
->vtotal
);
1627 intel_dp_compute_config(struct intel_encoder
*encoder
,
1628 struct intel_crtc_state
*pipe_config
,
1629 struct drm_connector_state
*conn_state
)
1631 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1632 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1633 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1634 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1635 struct intel_crtc
*intel_crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
1636 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
1637 struct intel_digital_connector_state
*intel_conn_state
=
1638 to_intel_digital_connector_state(conn_state
);
1639 int lane_count
, clock
;
1640 int min_lane_count
= 1;
1641 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
1642 /* Conveniently, the link BW constants become indices with a shift...*/
1646 int link_avail
, link_clock
;
1648 uint8_t link_bw
, rate_select
;
1649 bool reduce_m_n
= drm_dp_has_quirk(&intel_dp
->desc
,
1650 DP_DPCD_QUIRK_LIMITED_M_N
);
1652 common_len
= intel_dp_common_len_rate_limit(intel_dp
,
1653 intel_dp
->max_link_rate
);
1655 /* No common link rates between source and sink */
1656 WARN_ON(common_len
<= 0);
1658 max_clock
= common_len
- 1;
1660 if (HAS_PCH_SPLIT(dev_priv
) && !HAS_DDI(dev_priv
) && port
!= PORT_A
)
1661 pipe_config
->has_pch_encoder
= true;
1663 pipe_config
->has_drrs
= false;
1665 pipe_config
->has_audio
= false;
1666 else if (intel_conn_state
->force_audio
== HDMI_AUDIO_AUTO
)
1667 pipe_config
->has_audio
= intel_dp
->has_audio
;
1669 pipe_config
->has_audio
= intel_conn_state
->force_audio
== HDMI_AUDIO_ON
;
1671 if (intel_dp_is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
1672 struct drm_display_mode
*panel_mode
=
1673 intel_connector
->panel
.alt_fixed_mode
;
1674 struct drm_display_mode
*req_mode
= &pipe_config
->base
.mode
;
1676 if (!intel_edp_compare_alt_mode(req_mode
, panel_mode
))
1677 panel_mode
= intel_connector
->panel
.fixed_mode
;
1679 drm_mode_debug_printmodeline(panel_mode
);
1681 intel_fixed_panel_mode(panel_mode
, adjusted_mode
);
1683 if (INTEL_GEN(dev_priv
) >= 9) {
1685 ret
= skl_update_scaler_crtc(pipe_config
);
1690 if (HAS_GMCH_DISPLAY(dev_priv
))
1691 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
1692 conn_state
->scaling_mode
);
1694 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
1695 conn_state
->scaling_mode
);
1698 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
1701 /* Use values requested by Compliance Test Request */
1702 if (intel_dp
->compliance
.test_type
== DP_TEST_LINK_TRAINING
) {
1705 index
= intel_dp_rate_index(intel_dp
->common_rates
,
1706 intel_dp
->num_common_rates
,
1707 intel_dp
->compliance
.test_link_rate
);
1709 min_clock
= max_clock
= index
;
1710 min_lane_count
= max_lane_count
= intel_dp
->compliance
.test_lane_count
;
1712 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1713 "max bw %d pixel clock %iKHz\n",
1714 max_lane_count
, intel_dp
->common_rates
[max_clock
],
1715 adjusted_mode
->crtc_clock
);
1717 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1718 * bpc in between. */
1719 bpp
= intel_dp_compute_bpp(intel_dp
, pipe_config
);
1720 if (intel_dp_is_edp(intel_dp
)) {
1722 /* Get bpp from vbt only for panels that dont have bpp in edid */
1723 if (intel_connector
->base
.display_info
.bpc
== 0 &&
1724 (dev_priv
->vbt
.edp
.bpp
&& dev_priv
->vbt
.edp
.bpp
< bpp
)) {
1725 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1726 dev_priv
->vbt
.edp
.bpp
);
1727 bpp
= dev_priv
->vbt
.edp
.bpp
;
1731 * Use the maximum clock and number of lanes the eDP panel
1732 * advertizes being capable of. The panels are generally
1733 * designed to support only a single clock and lane
1734 * configuration, and typically these values correspond to the
1735 * native resolution of the panel.
1737 min_lane_count
= max_lane_count
;
1738 min_clock
= max_clock
;
1741 for (; bpp
>= 6*3; bpp
-= 2*3) {
1742 mode_rate
= intel_dp_link_required(adjusted_mode
->crtc_clock
,
1745 for (clock
= min_clock
; clock
<= max_clock
; clock
++) {
1746 for (lane_count
= min_lane_count
;
1747 lane_count
<= max_lane_count
;
1750 link_clock
= intel_dp
->common_rates
[clock
];
1751 link_avail
= intel_dp_max_data_rate(link_clock
,
1754 if (mode_rate
<= link_avail
) {
1764 if (intel_conn_state
->broadcast_rgb
== INTEL_BROADCAST_RGB_AUTO
) {
1767 * CEA-861-E - 5.1 Default Encoding Parameters
1768 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1770 pipe_config
->limited_color_range
=
1772 drm_default_rgb_quant_range(adjusted_mode
) ==
1773 HDMI_QUANTIZATION_RANGE_LIMITED
;
1775 pipe_config
->limited_color_range
=
1776 intel_conn_state
->broadcast_rgb
== INTEL_BROADCAST_RGB_LIMITED
;
1779 pipe_config
->lane_count
= lane_count
;
1781 pipe_config
->pipe_bpp
= bpp
;
1782 pipe_config
->port_clock
= intel_dp
->common_rates
[clock
];
1784 intel_dp_compute_rate(intel_dp
, pipe_config
->port_clock
,
1785 &link_bw
, &rate_select
);
1787 DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1788 link_bw
, rate_select
, pipe_config
->lane_count
,
1789 pipe_config
->port_clock
, bpp
);
1790 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1791 mode_rate
, link_avail
);
1793 intel_link_compute_m_n(bpp
, lane_count
,
1794 adjusted_mode
->crtc_clock
,
1795 pipe_config
->port_clock
,
1796 &pipe_config
->dp_m_n
,
1799 if (intel_connector
->panel
.downclock_mode
!= NULL
&&
1800 dev_priv
->drrs
.type
== SEAMLESS_DRRS_SUPPORT
) {
1801 pipe_config
->has_drrs
= true;
1802 intel_link_compute_m_n(bpp
, lane_count
,
1803 intel_connector
->panel
.downclock_mode
->clock
,
1804 pipe_config
->port_clock
,
1805 &pipe_config
->dp_m2_n2
,
1810 * DPLL0 VCO may need to be adjusted to get the correct
1811 * clock for eDP. This will affect cdclk as well.
1813 if (intel_dp_is_edp(intel_dp
) && IS_GEN9_BC(dev_priv
)) {
1816 switch (pipe_config
->port_clock
/ 2) {
1826 to_intel_atomic_state(pipe_config
->base
.state
)->cdclk
.logical
.vco
= vco
;
1829 if (!HAS_DDI(dev_priv
))
1830 intel_dp_set_clock(encoder
, pipe_config
);
1835 void intel_dp_set_link_params(struct intel_dp
*intel_dp
,
1836 int link_rate
, uint8_t lane_count
,
1839 intel_dp
->link_rate
= link_rate
;
1840 intel_dp
->lane_count
= lane_count
;
1841 intel_dp
->link_mst
= link_mst
;
1844 static void intel_dp_prepare(struct intel_encoder
*encoder
,
1845 struct intel_crtc_state
*pipe_config
)
1847 struct drm_device
*dev
= encoder
->base
.dev
;
1848 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1849 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1850 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1851 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1852 const struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1854 intel_dp_set_link_params(intel_dp
, pipe_config
->port_clock
,
1855 pipe_config
->lane_count
,
1856 intel_crtc_has_type(pipe_config
,
1857 INTEL_OUTPUT_DP_MST
));
1860 * There are four kinds of DP registers:
1867 * IBX PCH and CPU are the same for almost everything,
1868 * except that the CPU DP PLL is configured in this
1871 * CPT PCH is quite different, having many bits moved
1872 * to the TRANS_DP_CTL register instead. That
1873 * configuration happens (oddly) in ironlake_pch_enable
1876 /* Preserve the BIOS-computed detected bit. This is
1877 * supposed to be read-only.
1879 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
1881 /* Handle DP bits in common between all three register formats */
1882 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
1883 intel_dp
->DP
|= DP_PORT_WIDTH(pipe_config
->lane_count
);
1885 /* Split out the IBX/CPU vs CPT settings */
1887 if (IS_GEN7(dev_priv
) && port
== PORT_A
) {
1888 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1889 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1890 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1891 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1892 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1894 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1895 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1897 intel_dp
->DP
|= crtc
->pipe
<< 29;
1898 } else if (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
) {
1901 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1903 trans_dp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
1904 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1905 trans_dp
|= TRANS_DP_ENH_FRAMING
;
1907 trans_dp
&= ~TRANS_DP_ENH_FRAMING
;
1908 I915_WRITE(TRANS_DP_CTL(crtc
->pipe
), trans_dp
);
1910 if (IS_G4X(dev_priv
) && pipe_config
->limited_color_range
)
1911 intel_dp
->DP
|= DP_COLOR_RANGE_16_235
;
1913 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1914 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1915 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1916 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1917 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
1919 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1920 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1922 if (IS_CHERRYVIEW(dev_priv
))
1923 intel_dp
->DP
|= DP_PIPE_SELECT_CHV(crtc
->pipe
);
1924 else if (crtc
->pipe
== PIPE_B
)
1925 intel_dp
->DP
|= DP_PIPEB_SELECT
;
1929 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1930 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1932 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1933 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1935 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1936 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1938 static void intel_pps_verify_state(struct drm_i915_private
*dev_priv
,
1939 struct intel_dp
*intel_dp
);
1941 static void wait_panel_status(struct intel_dp
*intel_dp
,
1945 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1946 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1947 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
1949 lockdep_assert_held(&dev_priv
->pps_mutex
);
1951 intel_pps_verify_state(dev_priv
, intel_dp
);
1953 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1954 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1956 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1958 I915_READ(pp_stat_reg
),
1959 I915_READ(pp_ctrl_reg
));
1961 if (intel_wait_for_register(dev_priv
,
1962 pp_stat_reg
, mask
, value
,
1964 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1965 I915_READ(pp_stat_reg
),
1966 I915_READ(pp_ctrl_reg
));
1968 DRM_DEBUG_KMS("Wait complete\n");
1971 static void wait_panel_on(struct intel_dp
*intel_dp
)
1973 DRM_DEBUG_KMS("Wait for panel power on\n");
1974 wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
1977 static void wait_panel_off(struct intel_dp
*intel_dp
)
1979 DRM_DEBUG_KMS("Wait for panel power off time\n");
1980 wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
1983 static void wait_panel_power_cycle(struct intel_dp
*intel_dp
)
1985 ktime_t panel_power_on_time
;
1986 s64 panel_power_off_duration
;
1988 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1990 /* take the difference of currrent time and panel power off time
1991 * and then make panel wait for t11_t12 if needed. */
1992 panel_power_on_time
= ktime_get_boottime();
1993 panel_power_off_duration
= ktime_ms_delta(panel_power_on_time
, intel_dp
->panel_power_off_time
);
1995 /* When we disable the VDD override bit last we have to do the manual
1997 if (panel_power_off_duration
< (s64
)intel_dp
->panel_power_cycle_delay
)
1998 wait_remaining_ms_from_jiffies(jiffies
,
1999 intel_dp
->panel_power_cycle_delay
- panel_power_off_duration
);
2001 wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
2004 static void wait_backlight_on(struct intel_dp
*intel_dp
)
2006 wait_remaining_ms_from_jiffies(intel_dp
->last_power_on
,
2007 intel_dp
->backlight_on_delay
);
2010 static void edp_wait_backlight_off(struct intel_dp
*intel_dp
)
2012 wait_remaining_ms_from_jiffies(intel_dp
->last_backlight_off
,
2013 intel_dp
->backlight_off_delay
);
2016 /* Read the current pp_control value, unlocking the register if it
2020 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
2022 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2023 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2026 lockdep_assert_held(&dev_priv
->pps_mutex
);
2028 control
= I915_READ(_pp_ctrl_reg(intel_dp
));
2029 if (WARN_ON(!HAS_DDI(dev_priv
) &&
2030 (control
& PANEL_UNLOCK_MASK
) != PANEL_UNLOCK_REGS
)) {
2031 control
&= ~PANEL_UNLOCK_MASK
;
2032 control
|= PANEL_UNLOCK_REGS
;
2038 * Must be paired with edp_panel_vdd_off().
2039 * Must hold pps_mutex around the whole on/off sequence.
2040 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2042 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
)
2044 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2045 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2046 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2048 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
2049 bool need_to_disable
= !intel_dp
->want_panel_vdd
;
2051 lockdep_assert_held(&dev_priv
->pps_mutex
);
2053 if (!intel_dp_is_edp(intel_dp
))
2056 cancel_delayed_work(&intel_dp
->panel_vdd_work
);
2057 intel_dp
->want_panel_vdd
= true;
2059 if (edp_have_panel_vdd(intel_dp
))
2060 return need_to_disable
;
2062 intel_display_power_get(dev_priv
, intel_dp
->aux_power_domain
);
2064 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
2065 port_name(intel_dig_port
->port
));
2067 if (!edp_have_panel_power(intel_dp
))
2068 wait_panel_power_cycle(intel_dp
);
2070 pp
= ironlake_get_pp_control(intel_dp
);
2071 pp
|= EDP_FORCE_VDD
;
2073 pp_stat_reg
= _pp_stat_reg(intel_dp
);
2074 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2076 I915_WRITE(pp_ctrl_reg
, pp
);
2077 POSTING_READ(pp_ctrl_reg
);
2078 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2079 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
2081 * If the panel wasn't on, delay before accessing aux channel
2083 if (!edp_have_panel_power(intel_dp
)) {
2084 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
2085 port_name(intel_dig_port
->port
));
2086 msleep(intel_dp
->panel_power_up_delay
);
2089 return need_to_disable
;
2093 * Must be paired with intel_edp_panel_vdd_off() or
2094 * intel_edp_panel_off().
2095 * Nested calls to these functions are not allowed since
2096 * we drop the lock. Caller must use some higher level
2097 * locking to prevent nested calls from other threads.
2099 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
2103 if (!intel_dp_is_edp(intel_dp
))
2107 vdd
= edp_panel_vdd_on(intel_dp
);
2108 pps_unlock(intel_dp
);
2110 I915_STATE_WARN(!vdd
, "eDP port %c VDD already requested on\n",
2111 port_name(dp_to_dig_port(intel_dp
)->port
));
2114 static void edp_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
2116 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2117 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2118 struct intel_digital_port
*intel_dig_port
=
2119 dp_to_dig_port(intel_dp
);
2121 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
2123 lockdep_assert_held(&dev_priv
->pps_mutex
);
2125 WARN_ON(intel_dp
->want_panel_vdd
);
2127 if (!edp_have_panel_vdd(intel_dp
))
2130 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2131 port_name(intel_dig_port
->port
));
2133 pp
= ironlake_get_pp_control(intel_dp
);
2134 pp
&= ~EDP_FORCE_VDD
;
2136 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2137 pp_stat_reg
= _pp_stat_reg(intel_dp
);
2139 I915_WRITE(pp_ctrl_reg
, pp
);
2140 POSTING_READ(pp_ctrl_reg
);
2142 /* Make sure sequencer is idle before allowing subsequent activity */
2143 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2144 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
2146 if ((pp
& PANEL_POWER_ON
) == 0)
2147 intel_dp
->panel_power_off_time
= ktime_get_boottime();
2149 intel_display_power_put(dev_priv
, intel_dp
->aux_power_domain
);
2152 static void edp_panel_vdd_work(struct work_struct
*__work
)
2154 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
2155 struct intel_dp
, panel_vdd_work
);
2158 if (!intel_dp
->want_panel_vdd
)
2159 edp_panel_vdd_off_sync(intel_dp
);
2160 pps_unlock(intel_dp
);
2163 static void edp_panel_vdd_schedule_off(struct intel_dp
*intel_dp
)
2165 unsigned long delay
;
2168 * Queue the timer to fire a long time from now (relative to the power
2169 * down delay) to keep the panel power up across a sequence of
2172 delay
= msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5);
2173 schedule_delayed_work(&intel_dp
->panel_vdd_work
, delay
);
2177 * Must be paired with edp_panel_vdd_on().
2178 * Must hold pps_mutex around the whole on/off sequence.
2179 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2181 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
2183 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
2185 lockdep_assert_held(&dev_priv
->pps_mutex
);
2187 if (!intel_dp_is_edp(intel_dp
))
2190 I915_STATE_WARN(!intel_dp
->want_panel_vdd
, "eDP port %c VDD not forced on",
2191 port_name(dp_to_dig_port(intel_dp
)->port
));
2193 intel_dp
->want_panel_vdd
= false;
2196 edp_panel_vdd_off_sync(intel_dp
);
2198 edp_panel_vdd_schedule_off(intel_dp
);
2201 static void edp_panel_on(struct intel_dp
*intel_dp
)
2203 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2204 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2206 i915_reg_t pp_ctrl_reg
;
2208 lockdep_assert_held(&dev_priv
->pps_mutex
);
2210 if (!intel_dp_is_edp(intel_dp
))
2213 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2214 port_name(dp_to_dig_port(intel_dp
)->port
));
2216 if (WARN(edp_have_panel_power(intel_dp
),
2217 "eDP port %c panel power already on\n",
2218 port_name(dp_to_dig_port(intel_dp
)->port
)))
2221 wait_panel_power_cycle(intel_dp
);
2223 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2224 pp
= ironlake_get_pp_control(intel_dp
);
2225 if (IS_GEN5(dev_priv
)) {
2226 /* ILK workaround: disable reset around power sequence */
2227 pp
&= ~PANEL_POWER_RESET
;
2228 I915_WRITE(pp_ctrl_reg
, pp
);
2229 POSTING_READ(pp_ctrl_reg
);
2232 pp
|= PANEL_POWER_ON
;
2233 if (!IS_GEN5(dev_priv
))
2234 pp
|= PANEL_POWER_RESET
;
2236 I915_WRITE(pp_ctrl_reg
, pp
);
2237 POSTING_READ(pp_ctrl_reg
);
2239 wait_panel_on(intel_dp
);
2240 intel_dp
->last_power_on
= jiffies
;
2242 if (IS_GEN5(dev_priv
)) {
2243 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
2244 I915_WRITE(pp_ctrl_reg
, pp
);
2245 POSTING_READ(pp_ctrl_reg
);
2249 void intel_edp_panel_on(struct intel_dp
*intel_dp
)
2251 if (!intel_dp_is_edp(intel_dp
))
2255 edp_panel_on(intel_dp
);
2256 pps_unlock(intel_dp
);
2260 static void edp_panel_off(struct intel_dp
*intel_dp
)
2262 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2263 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2265 i915_reg_t pp_ctrl_reg
;
2267 lockdep_assert_held(&dev_priv
->pps_mutex
);
2269 if (!intel_dp_is_edp(intel_dp
))
2272 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2273 port_name(dp_to_dig_port(intel_dp
)->port
));
2275 WARN(!intel_dp
->want_panel_vdd
, "Need eDP port %c VDD to turn off panel\n",
2276 port_name(dp_to_dig_port(intel_dp
)->port
));
2278 pp
= ironlake_get_pp_control(intel_dp
);
2279 /* We need to switch off panel power _and_ force vdd, for otherwise some
2280 * panels get very unhappy and cease to work. */
2281 pp
&= ~(PANEL_POWER_ON
| PANEL_POWER_RESET
| EDP_FORCE_VDD
|
2284 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2286 intel_dp
->want_panel_vdd
= false;
2288 I915_WRITE(pp_ctrl_reg
, pp
);
2289 POSTING_READ(pp_ctrl_reg
);
2291 wait_panel_off(intel_dp
);
2292 intel_dp
->panel_power_off_time
= ktime_get_boottime();
2294 /* We got a reference when we enabled the VDD. */
2295 intel_display_power_put(dev_priv
, intel_dp
->aux_power_domain
);
2298 void intel_edp_panel_off(struct intel_dp
*intel_dp
)
2300 if (!intel_dp_is_edp(intel_dp
))
2304 edp_panel_off(intel_dp
);
2305 pps_unlock(intel_dp
);
2308 /* Enable backlight in the panel power control. */
2309 static void _intel_edp_backlight_on(struct intel_dp
*intel_dp
)
2311 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2312 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2313 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2315 i915_reg_t pp_ctrl_reg
;
2318 * If we enable the backlight right away following a panel power
2319 * on, we may see slight flicker as the panel syncs with the eDP
2320 * link. So delay a bit to make sure the image is solid before
2321 * allowing it to appear.
2323 wait_backlight_on(intel_dp
);
2327 pp
= ironlake_get_pp_control(intel_dp
);
2328 pp
|= EDP_BLC_ENABLE
;
2330 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2332 I915_WRITE(pp_ctrl_reg
, pp
);
2333 POSTING_READ(pp_ctrl_reg
);
2335 pps_unlock(intel_dp
);
2338 /* Enable backlight PWM and backlight PP control. */
2339 void intel_edp_backlight_on(const struct intel_crtc_state
*crtc_state
,
2340 const struct drm_connector_state
*conn_state
)
2342 struct intel_dp
*intel_dp
= enc_to_intel_dp(conn_state
->best_encoder
);
2344 if (!intel_dp_is_edp(intel_dp
))
2347 DRM_DEBUG_KMS("\n");
2349 intel_panel_enable_backlight(crtc_state
, conn_state
);
2350 _intel_edp_backlight_on(intel_dp
);
2353 /* Disable backlight in the panel power control. */
2354 static void _intel_edp_backlight_off(struct intel_dp
*intel_dp
)
2356 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2357 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2359 i915_reg_t pp_ctrl_reg
;
2361 if (!intel_dp_is_edp(intel_dp
))
2366 pp
= ironlake_get_pp_control(intel_dp
);
2367 pp
&= ~EDP_BLC_ENABLE
;
2369 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2371 I915_WRITE(pp_ctrl_reg
, pp
);
2372 POSTING_READ(pp_ctrl_reg
);
2374 pps_unlock(intel_dp
);
2376 intel_dp
->last_backlight_off
= jiffies
;
2377 edp_wait_backlight_off(intel_dp
);
2380 /* Disable backlight PP control and backlight PWM. */
2381 void intel_edp_backlight_off(const struct drm_connector_state
*old_conn_state
)
2383 struct intel_dp
*intel_dp
= enc_to_intel_dp(old_conn_state
->best_encoder
);
2385 if (!intel_dp_is_edp(intel_dp
))
2388 DRM_DEBUG_KMS("\n");
2390 _intel_edp_backlight_off(intel_dp
);
2391 intel_panel_disable_backlight(old_conn_state
);
2395 * Hook for controlling the panel power control backlight through the bl_power
2396 * sysfs attribute. Take care to handle multiple calls.
2398 static void intel_edp_backlight_power(struct intel_connector
*connector
,
2401 struct intel_dp
*intel_dp
= intel_attached_dp(&connector
->base
);
2405 is_enabled
= ironlake_get_pp_control(intel_dp
) & EDP_BLC_ENABLE
;
2406 pps_unlock(intel_dp
);
2408 if (is_enabled
== enable
)
2411 DRM_DEBUG_KMS("panel power control backlight %s\n",
2412 enable
? "enable" : "disable");
2415 _intel_edp_backlight_on(intel_dp
);
2417 _intel_edp_backlight_off(intel_dp
);
2420 static void assert_dp_port(struct intel_dp
*intel_dp
, bool state
)
2422 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2423 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
2424 bool cur_state
= I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
;
2426 I915_STATE_WARN(cur_state
!= state
,
2427 "DP port %c state assertion failure (expected %s, current %s)\n",
2428 port_name(dig_port
->port
),
2429 onoff(state
), onoff(cur_state
));
2431 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2433 static void assert_edp_pll(struct drm_i915_private
*dev_priv
, bool state
)
2435 bool cur_state
= I915_READ(DP_A
) & DP_PLL_ENABLE
;
2437 I915_STATE_WARN(cur_state
!= state
,
2438 "eDP PLL state assertion failure (expected %s, current %s)\n",
2439 onoff(state
), onoff(cur_state
));
2441 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2442 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2444 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
,
2445 struct intel_crtc_state
*pipe_config
)
2447 struct intel_crtc
*crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
2448 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2450 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
2451 assert_dp_port_disabled(intel_dp
);
2452 assert_edp_pll_disabled(dev_priv
);
2454 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2455 pipe_config
->port_clock
);
2457 intel_dp
->DP
&= ~DP_PLL_FREQ_MASK
;
2459 if (pipe_config
->port_clock
== 162000)
2460 intel_dp
->DP
|= DP_PLL_FREQ_162MHZ
;
2462 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
2464 I915_WRITE(DP_A
, intel_dp
->DP
);
2469 * [DevILK] Work around required when enabling DP PLL
2470 * while a pipe is enabled going to FDI:
2471 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2472 * 2. Program DP PLL enable
2474 if (IS_GEN5(dev_priv
))
2475 intel_wait_for_vblank_if_active(dev_priv
, !crtc
->pipe
);
2477 intel_dp
->DP
|= DP_PLL_ENABLE
;
2479 I915_WRITE(DP_A
, intel_dp
->DP
);
2484 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
2486 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2487 struct intel_crtc
*crtc
= to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
2488 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2490 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
2491 assert_dp_port_disabled(intel_dp
);
2492 assert_edp_pll_enabled(dev_priv
);
2494 DRM_DEBUG_KMS("disabling eDP PLL\n");
2496 intel_dp
->DP
&= ~DP_PLL_ENABLE
;
2498 I915_WRITE(DP_A
, intel_dp
->DP
);
2503 /* If the sink supports it, try to set the power state appropriately */
2504 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
2508 /* Should have a valid DPCD by this point */
2509 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
2512 if (mode
!= DRM_MODE_DPMS_ON
) {
2513 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2516 struct intel_lspcon
*lspcon
= dp_to_lspcon(intel_dp
);
2519 * When turning on, we need to retry for 1ms to give the sink
2522 for (i
= 0; i
< 3; i
++) {
2523 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2530 if (ret
== 1 && lspcon
->active
)
2531 lspcon_wait_pcon_mode(lspcon
);
2535 DRM_DEBUG_KMS("failed to %s sink power state\n",
2536 mode
== DRM_MODE_DPMS_ON
? "enable" : "disable");
2539 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
2542 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2543 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2544 struct drm_device
*dev
= encoder
->base
.dev
;
2545 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2549 if (!intel_display_power_get_if_enabled(dev_priv
,
2550 encoder
->power_domain
))
2555 tmp
= I915_READ(intel_dp
->output_reg
);
2557 if (!(tmp
& DP_PORT_EN
))
2560 if (IS_GEN7(dev_priv
) && port
== PORT_A
) {
2561 *pipe
= PORT_TO_PIPE_CPT(tmp
);
2562 } else if (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
) {
2565 for_each_pipe(dev_priv
, p
) {
2566 u32 trans_dp
= I915_READ(TRANS_DP_CTL(p
));
2567 if (TRANS_DP_PIPE_TO_PORT(trans_dp
) == port
) {
2575 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2576 i915_mmio_reg_offset(intel_dp
->output_reg
));
2577 } else if (IS_CHERRYVIEW(dev_priv
)) {
2578 *pipe
= DP_PORT_TO_PIPE_CHV(tmp
);
2580 *pipe
= PORT_TO_PIPE(tmp
);
2586 intel_display_power_put(dev_priv
, encoder
->power_domain
);
2591 static void intel_dp_get_config(struct intel_encoder
*encoder
,
2592 struct intel_crtc_state
*pipe_config
)
2594 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2596 struct drm_device
*dev
= encoder
->base
.dev
;
2597 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2598 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2599 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2601 tmp
= I915_READ(intel_dp
->output_reg
);
2603 pipe_config
->has_audio
= tmp
& DP_AUDIO_OUTPUT_ENABLE
&& port
!= PORT_A
;
2605 if (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
) {
2606 u32 trans_dp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
2608 if (trans_dp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
2609 flags
|= DRM_MODE_FLAG_PHSYNC
;
2611 flags
|= DRM_MODE_FLAG_NHSYNC
;
2613 if (trans_dp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
2614 flags
|= DRM_MODE_FLAG_PVSYNC
;
2616 flags
|= DRM_MODE_FLAG_NVSYNC
;
2618 if (tmp
& DP_SYNC_HS_HIGH
)
2619 flags
|= DRM_MODE_FLAG_PHSYNC
;
2621 flags
|= DRM_MODE_FLAG_NHSYNC
;
2623 if (tmp
& DP_SYNC_VS_HIGH
)
2624 flags
|= DRM_MODE_FLAG_PVSYNC
;
2626 flags
|= DRM_MODE_FLAG_NVSYNC
;
2629 pipe_config
->base
.adjusted_mode
.flags
|= flags
;
2631 if (IS_G4X(dev_priv
) && tmp
& DP_COLOR_RANGE_16_235
)
2632 pipe_config
->limited_color_range
= true;
2634 pipe_config
->lane_count
=
2635 ((tmp
& DP_PORT_WIDTH_MASK
) >> DP_PORT_WIDTH_SHIFT
) + 1;
2637 intel_dp_get_m_n(crtc
, pipe_config
);
2639 if (port
== PORT_A
) {
2640 if ((I915_READ(DP_A
) & DP_PLL_FREQ_MASK
) == DP_PLL_FREQ_162MHZ
)
2641 pipe_config
->port_clock
= 162000;
2643 pipe_config
->port_clock
= 270000;
2646 pipe_config
->base
.adjusted_mode
.crtc_clock
=
2647 intel_dotclock_calculate(pipe_config
->port_clock
,
2648 &pipe_config
->dp_m_n
);
2650 if (intel_dp_is_edp(intel_dp
) && dev_priv
->vbt
.edp
.bpp
&&
2651 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp
.bpp
) {
2653 * This is a big fat ugly hack.
2655 * Some machines in UEFI boot mode provide us a VBT that has 18
2656 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2657 * unknown we fail to light up. Yet the same BIOS boots up with
2658 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2659 * max, not what it tells us to use.
2661 * Note: This will still be broken if the eDP panel is not lit
2662 * up by the BIOS, and thus we can't get the mode at module
2665 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2666 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp
.bpp
);
2667 dev_priv
->vbt
.edp
.bpp
= pipe_config
->pipe_bpp
;
2671 static void intel_disable_dp(struct intel_encoder
*encoder
,
2672 struct intel_crtc_state
*old_crtc_state
,
2673 struct drm_connector_state
*old_conn_state
)
2675 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2676 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2678 if (old_crtc_state
->has_audio
)
2679 intel_audio_codec_disable(encoder
);
2681 if (HAS_PSR(dev_priv
) && !HAS_DDI(dev_priv
))
2682 intel_psr_disable(intel_dp
);
2684 /* Make sure the panel is off before trying to change the mode. But also
2685 * ensure that we have vdd while we switch off the panel. */
2686 intel_edp_panel_vdd_on(intel_dp
);
2687 intel_edp_backlight_off(old_conn_state
);
2688 if (!(dev_priv
->quirks
& QUIRK_SKIP_DP_DPMS_D3
))
2689 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
2690 intel_edp_panel_off(intel_dp
);
2692 /* disable the port before the pipe on g4x */
2693 if (INTEL_GEN(dev_priv
) < 5)
2694 intel_dp_link_down(intel_dp
);
2697 static void ilk_post_disable_dp(struct intel_encoder
*encoder
,
2698 struct intel_crtc_state
*old_crtc_state
,
2699 struct drm_connector_state
*old_conn_state
)
2701 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2702 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2704 intel_dp_link_down(intel_dp
);
2706 /* Only ilk+ has port A */
2708 ironlake_edp_pll_off(intel_dp
);
2711 static void vlv_post_disable_dp(struct intel_encoder
*encoder
,
2712 struct intel_crtc_state
*old_crtc_state
,
2713 struct drm_connector_state
*old_conn_state
)
2715 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2717 intel_dp_link_down(intel_dp
);
2720 static void chv_post_disable_dp(struct intel_encoder
*encoder
,
2721 struct intel_crtc_state
*old_crtc_state
,
2722 struct drm_connector_state
*old_conn_state
)
2724 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2725 struct drm_device
*dev
= encoder
->base
.dev
;
2726 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2728 intel_dp_link_down(intel_dp
);
2730 mutex_lock(&dev_priv
->sb_lock
);
2732 /* Assert data lane reset */
2733 chv_data_lane_soft_reset(encoder
, true);
2735 mutex_unlock(&dev_priv
->sb_lock
);
2739 _intel_dp_set_link_train(struct intel_dp
*intel_dp
,
2741 uint8_t dp_train_pat
)
2743 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2744 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2745 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2746 enum port port
= intel_dig_port
->port
;
2748 if (dp_train_pat
& DP_TRAINING_PATTERN_MASK
)
2749 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
2750 dp_train_pat
& DP_TRAINING_PATTERN_MASK
);
2752 if (HAS_DDI(dev_priv
)) {
2753 uint32_t temp
= I915_READ(DP_TP_CTL(port
));
2755 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
2756 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
2758 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
2760 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2761 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2762 case DP_TRAINING_PATTERN_DISABLE
:
2763 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
2766 case DP_TRAINING_PATTERN_1
:
2767 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2769 case DP_TRAINING_PATTERN_2
:
2770 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
2772 case DP_TRAINING_PATTERN_3
:
2773 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
2776 I915_WRITE(DP_TP_CTL(port
), temp
);
2778 } else if ((IS_GEN7(dev_priv
) && port
== PORT_A
) ||
2779 (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
)) {
2780 *DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2782 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2783 case DP_TRAINING_PATTERN_DISABLE
:
2784 *DP
|= DP_LINK_TRAIN_OFF_CPT
;
2786 case DP_TRAINING_PATTERN_1
:
2787 *DP
|= DP_LINK_TRAIN_PAT_1_CPT
;
2789 case DP_TRAINING_PATTERN_2
:
2790 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2792 case DP_TRAINING_PATTERN_3
:
2793 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2794 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2799 if (IS_CHERRYVIEW(dev_priv
))
2800 *DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
2802 *DP
&= ~DP_LINK_TRAIN_MASK
;
2804 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2805 case DP_TRAINING_PATTERN_DISABLE
:
2806 *DP
|= DP_LINK_TRAIN_OFF
;
2808 case DP_TRAINING_PATTERN_1
:
2809 *DP
|= DP_LINK_TRAIN_PAT_1
;
2811 case DP_TRAINING_PATTERN_2
:
2812 *DP
|= DP_LINK_TRAIN_PAT_2
;
2814 case DP_TRAINING_PATTERN_3
:
2815 if (IS_CHERRYVIEW(dev_priv
)) {
2816 *DP
|= DP_LINK_TRAIN_PAT_3_CHV
;
2818 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2819 *DP
|= DP_LINK_TRAIN_PAT_2
;
2826 static void intel_dp_enable_port(struct intel_dp
*intel_dp
,
2827 struct intel_crtc_state
*old_crtc_state
)
2829 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2830 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2832 /* enable with pattern 1 (as per spec) */
2834 intel_dp_program_link_training_pattern(intel_dp
, DP_TRAINING_PATTERN_1
);
2837 * Magic for VLV/CHV. We _must_ first set up the register
2838 * without actually enabling the port, and then do another
2839 * write to enable the port. Otherwise link training will
2840 * fail when the power sequencer is freshly used for this port.
2842 intel_dp
->DP
|= DP_PORT_EN
;
2843 if (old_crtc_state
->has_audio
)
2844 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
2846 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2847 POSTING_READ(intel_dp
->output_reg
);
2850 static void intel_enable_dp(struct intel_encoder
*encoder
,
2851 struct intel_crtc_state
*pipe_config
,
2852 struct drm_connector_state
*conn_state
)
2854 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2855 struct drm_device
*dev
= encoder
->base
.dev
;
2856 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2857 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2858 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
2859 enum pipe pipe
= crtc
->pipe
;
2861 if (WARN_ON(dp_reg
& DP_PORT_EN
))
2866 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
2867 vlv_init_panel_power_sequencer(intel_dp
);
2869 intel_dp_enable_port(intel_dp
, pipe_config
);
2871 edp_panel_vdd_on(intel_dp
);
2872 edp_panel_on(intel_dp
);
2873 edp_panel_vdd_off(intel_dp
, true);
2875 pps_unlock(intel_dp
);
2877 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
2878 unsigned int lane_mask
= 0x0;
2880 if (IS_CHERRYVIEW(dev_priv
))
2881 lane_mask
= intel_dp_unused_lane_mask(pipe_config
->lane_count
);
2883 vlv_wait_port_ready(dev_priv
, dp_to_dig_port(intel_dp
),
2887 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
2888 intel_dp_start_link_train(intel_dp
);
2889 intel_dp_stop_link_train(intel_dp
);
2891 if (pipe_config
->has_audio
) {
2892 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2894 intel_audio_codec_enable(encoder
, pipe_config
, conn_state
);
2898 static void g4x_enable_dp(struct intel_encoder
*encoder
,
2899 struct intel_crtc_state
*pipe_config
,
2900 struct drm_connector_state
*conn_state
)
2902 intel_enable_dp(encoder
, pipe_config
, conn_state
);
2903 intel_edp_backlight_on(pipe_config
, conn_state
);
2906 static void vlv_enable_dp(struct intel_encoder
*encoder
,
2907 struct intel_crtc_state
*pipe_config
,
2908 struct drm_connector_state
*conn_state
)
2910 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2912 intel_edp_backlight_on(pipe_config
, conn_state
);
2913 intel_psr_enable(intel_dp
);
2916 static void g4x_pre_enable_dp(struct intel_encoder
*encoder
,
2917 struct intel_crtc_state
*pipe_config
,
2918 struct drm_connector_state
*conn_state
)
2920 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2921 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2923 intel_dp_prepare(encoder
, pipe_config
);
2925 /* Only ilk+ has port A */
2927 ironlake_edp_pll_on(intel_dp
, pipe_config
);
2930 static void vlv_detach_power_sequencer(struct intel_dp
*intel_dp
)
2932 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2933 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
2934 enum pipe pipe
= intel_dp
->pps_pipe
;
2935 i915_reg_t pp_on_reg
= PP_ON_DELAYS(pipe
);
2937 WARN_ON(intel_dp
->active_pipe
!= INVALID_PIPE
);
2939 if (WARN_ON(pipe
!= PIPE_A
&& pipe
!= PIPE_B
))
2942 edp_panel_vdd_off_sync(intel_dp
);
2945 * VLV seems to get confused when multiple power seqeuencers
2946 * have the same port selected (even if only one has power/vdd
2947 * enabled). The failure manifests as vlv_wait_port_ready() failing
2948 * CHV on the other hand doesn't seem to mind having the same port
2949 * selected in multiple power seqeuencers, but let's clear the
2950 * port select always when logically disconnecting a power sequencer
2953 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2954 pipe_name(pipe
), port_name(intel_dig_port
->port
));
2955 I915_WRITE(pp_on_reg
, 0);
2956 POSTING_READ(pp_on_reg
);
2958 intel_dp
->pps_pipe
= INVALID_PIPE
;
2961 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
2964 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2965 struct intel_encoder
*encoder
;
2967 lockdep_assert_held(&dev_priv
->pps_mutex
);
2969 for_each_intel_encoder(dev
, encoder
) {
2970 struct intel_dp
*intel_dp
;
2973 if (encoder
->type
!= INTEL_OUTPUT_DP
&&
2974 encoder
->type
!= INTEL_OUTPUT_EDP
)
2977 intel_dp
= enc_to_intel_dp(&encoder
->base
);
2978 port
= dp_to_dig_port(intel_dp
)->port
;
2980 WARN(intel_dp
->active_pipe
== pipe
,
2981 "stealing pipe %c power sequencer from active (e)DP port %c\n",
2982 pipe_name(pipe
), port_name(port
));
2984 if (intel_dp
->pps_pipe
!= pipe
)
2987 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2988 pipe_name(pipe
), port_name(port
));
2990 /* make sure vdd is off before we steal it */
2991 vlv_detach_power_sequencer(intel_dp
);
2995 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
)
2997 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2998 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
2999 struct drm_device
*dev
= encoder
->base
.dev
;
3000 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3001 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
3003 lockdep_assert_held(&dev_priv
->pps_mutex
);
3005 WARN_ON(intel_dp
->active_pipe
!= INVALID_PIPE
);
3007 if (intel_dp
->pps_pipe
!= INVALID_PIPE
&&
3008 intel_dp
->pps_pipe
!= crtc
->pipe
) {
3010 * If another power sequencer was being used on this
3011 * port previously make sure to turn off vdd there while
3012 * we still have control of it.
3014 vlv_detach_power_sequencer(intel_dp
);
3018 * We may be stealing the power
3019 * sequencer from another port.
3021 vlv_steal_power_sequencer(dev
, crtc
->pipe
);
3023 intel_dp
->active_pipe
= crtc
->pipe
;
3025 if (!intel_dp_is_edp(intel_dp
))
3028 /* now it's all ours */
3029 intel_dp
->pps_pipe
= crtc
->pipe
;
3031 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
3032 pipe_name(intel_dp
->pps_pipe
), port_name(intel_dig_port
->port
));
3034 /* init power sequencer on this pipe and port */
3035 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
3036 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
, true);
3039 static void vlv_pre_enable_dp(struct intel_encoder
*encoder
,
3040 struct intel_crtc_state
*pipe_config
,
3041 struct drm_connector_state
*conn_state
)
3043 vlv_phy_pre_encoder_enable(encoder
);
3045 intel_enable_dp(encoder
, pipe_config
, conn_state
);
3048 static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder
,
3049 struct intel_crtc_state
*pipe_config
,
3050 struct drm_connector_state
*conn_state
)
3052 intel_dp_prepare(encoder
, pipe_config
);
3054 vlv_phy_pre_pll_enable(encoder
);
3057 static void chv_pre_enable_dp(struct intel_encoder
*encoder
,
3058 struct intel_crtc_state
*pipe_config
,
3059 struct drm_connector_state
*conn_state
)
3061 chv_phy_pre_encoder_enable(encoder
);
3063 intel_enable_dp(encoder
, pipe_config
, conn_state
);
3065 /* Second common lane will stay alive on its own now */
3066 chv_phy_release_cl2_override(encoder
);
3069 static void chv_dp_pre_pll_enable(struct intel_encoder
*encoder
,
3070 struct intel_crtc_state
*pipe_config
,
3071 struct drm_connector_state
*conn_state
)
3073 intel_dp_prepare(encoder
, pipe_config
);
3075 chv_phy_pre_pll_enable(encoder
);
3078 static void chv_dp_post_pll_disable(struct intel_encoder
*encoder
,
3079 struct intel_crtc_state
*pipe_config
,
3080 struct drm_connector_state
*conn_state
)
3082 chv_phy_post_pll_disable(encoder
);
3086 * Fetch AUX CH registers 0x202 - 0x207 which contain
3087 * link status information
3090 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
3092 return drm_dp_dpcd_read(&intel_dp
->aux
, DP_LANE0_1_STATUS
, link_status
,
3093 DP_LINK_STATUS_SIZE
) == DP_LINK_STATUS_SIZE
;
3096 static bool intel_dp_get_y_cord_status(struct intel_dp
*intel_dp
)
3098 uint8_t psr_caps
= 0;
3100 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_PSR_CAPS
, &psr_caps
) != 1)
3102 return psr_caps
& DP_PSR2_SU_Y_COORDINATE_REQUIRED
;
3105 static bool intel_dp_get_colorimetry_status(struct intel_dp
*intel_dp
)
3109 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_DPRX_FEATURE_ENUMERATION_LIST
,
3112 return dprx
& DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED
;
3115 static bool intel_dp_get_alpm_status(struct intel_dp
*intel_dp
)
3117 uint8_t alpm_caps
= 0;
3119 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_RECEIVER_ALPM_CAP
,
3122 return alpm_caps
& DP_ALPM_CAP
;
3125 /* These are source-specific values. */
3127 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
3129 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
3130 enum port port
= dp_to_dig_port(intel_dp
)->port
;
3132 if (IS_GEN9_LP(dev_priv
))
3133 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
3134 else if (INTEL_GEN(dev_priv
) >= 9) {
3135 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
3136 return intel_ddi_dp_voltage_max(encoder
);
3137 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
3138 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
3139 else if (IS_GEN7(dev_priv
) && port
== PORT_A
)
3140 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
3141 else if (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
)
3142 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
3144 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
3148 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
3150 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
3151 enum port port
= dp_to_dig_port(intel_dp
)->port
;
3153 if (INTEL_GEN(dev_priv
) >= 9) {
3154 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3155 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3156 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3157 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3158 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3159 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3160 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3161 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3162 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3164 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3166 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
3167 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3168 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3169 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3170 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3171 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3172 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3173 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3174 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3176 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3178 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
3179 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3180 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3181 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3182 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3183 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3184 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3185 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3186 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3188 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3190 } else if (IS_GEN7(dev_priv
) && port
== PORT_A
) {
3191 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3192 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3193 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3194 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3195 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3196 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3198 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3201 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3202 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3203 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3204 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3205 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3206 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3207 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3208 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3210 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3215 static uint32_t vlv_signal_levels(struct intel_dp
*intel_dp
)
3217 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
3218 unsigned long demph_reg_value
, preemph_reg_value
,
3219 uniqtranscale_reg_value
;
3220 uint8_t train_set
= intel_dp
->train_set
[0];
3222 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3223 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3224 preemph_reg_value
= 0x0004000;
3225 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3226 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3227 demph_reg_value
= 0x2B405555;
3228 uniqtranscale_reg_value
= 0x552AB83A;
3230 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3231 demph_reg_value
= 0x2B404040;
3232 uniqtranscale_reg_value
= 0x5548B83A;
3234 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3235 demph_reg_value
= 0x2B245555;
3236 uniqtranscale_reg_value
= 0x5560B83A;
3238 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3239 demph_reg_value
= 0x2B405555;
3240 uniqtranscale_reg_value
= 0x5598DA3A;
3246 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3247 preemph_reg_value
= 0x0002000;
3248 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3249 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3250 demph_reg_value
= 0x2B404040;
3251 uniqtranscale_reg_value
= 0x5552B83A;
3253 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3254 demph_reg_value
= 0x2B404848;
3255 uniqtranscale_reg_value
= 0x5580B83A;
3257 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3258 demph_reg_value
= 0x2B404040;
3259 uniqtranscale_reg_value
= 0x55ADDA3A;
3265 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3266 preemph_reg_value
= 0x0000000;
3267 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3268 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3269 demph_reg_value
= 0x2B305555;
3270 uniqtranscale_reg_value
= 0x5570B83A;
3272 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3273 demph_reg_value
= 0x2B2B4040;
3274 uniqtranscale_reg_value
= 0x55ADDA3A;
3280 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3281 preemph_reg_value
= 0x0006000;
3282 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3283 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3284 demph_reg_value
= 0x1B405555;
3285 uniqtranscale_reg_value
= 0x55ADDA3A;
3295 vlv_set_phy_signal_level(encoder
, demph_reg_value
, preemph_reg_value
,
3296 uniqtranscale_reg_value
, 0);
3301 static uint32_t chv_signal_levels(struct intel_dp
*intel_dp
)
3303 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
3304 u32 deemph_reg_value
, margin_reg_value
;
3305 bool uniq_trans_scale
= false;
3306 uint8_t train_set
= intel_dp
->train_set
[0];
3308 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3309 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3310 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3311 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3312 deemph_reg_value
= 128;
3313 margin_reg_value
= 52;
3315 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3316 deemph_reg_value
= 128;
3317 margin_reg_value
= 77;
3319 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3320 deemph_reg_value
= 128;
3321 margin_reg_value
= 102;
3323 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3324 deemph_reg_value
= 128;
3325 margin_reg_value
= 154;
3326 uniq_trans_scale
= true;
3332 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3333 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3334 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3335 deemph_reg_value
= 85;
3336 margin_reg_value
= 78;
3338 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3339 deemph_reg_value
= 85;
3340 margin_reg_value
= 116;
3342 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3343 deemph_reg_value
= 85;
3344 margin_reg_value
= 154;
3350 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3351 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3352 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3353 deemph_reg_value
= 64;
3354 margin_reg_value
= 104;
3356 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3357 deemph_reg_value
= 64;
3358 margin_reg_value
= 154;
3364 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3365 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3366 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3367 deemph_reg_value
= 43;
3368 margin_reg_value
= 154;
3378 chv_set_phy_signal_level(encoder
, deemph_reg_value
,
3379 margin_reg_value
, uniq_trans_scale
);
3385 gen4_signal_levels(uint8_t train_set
)
3387 uint32_t signal_levels
= 0;
3389 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3390 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3392 signal_levels
|= DP_VOLTAGE_0_4
;
3394 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3395 signal_levels
|= DP_VOLTAGE_0_6
;
3397 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3398 signal_levels
|= DP_VOLTAGE_0_8
;
3400 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3401 signal_levels
|= DP_VOLTAGE_1_2
;
3404 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3405 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3407 signal_levels
|= DP_PRE_EMPHASIS_0
;
3409 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3410 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
3412 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3413 signal_levels
|= DP_PRE_EMPHASIS_6
;
3415 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3416 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
3419 return signal_levels
;
3422 /* Gen6's DP voltage swing and pre-emphasis control */
3424 gen6_edp_signal_levels(uint8_t train_set
)
3426 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3427 DP_TRAIN_PRE_EMPHASIS_MASK
);
3428 switch (signal_levels
) {
3429 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3430 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3431 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3432 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3433 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
3434 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3435 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3436 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
3437 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3438 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3439 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
3440 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3441 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3442 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
3444 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3445 "0x%x\n", signal_levels
);
3446 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3450 /* Gen7's DP voltage swing and pre-emphasis control */
3452 gen7_edp_signal_levels(uint8_t train_set
)
3454 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3455 DP_TRAIN_PRE_EMPHASIS_MASK
);
3456 switch (signal_levels
) {
3457 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3458 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
3459 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3460 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
3461 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3462 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
3464 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3465 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
3466 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3467 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
3469 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3470 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
3471 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3472 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
3475 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3476 "0x%x\n", signal_levels
);
3477 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
3482 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
)
3484 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3485 enum port port
= intel_dig_port
->port
;
3486 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3487 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3488 uint32_t signal_levels
, mask
= 0;
3489 uint8_t train_set
= intel_dp
->train_set
[0];
3491 if (HAS_DDI(dev_priv
)) {
3492 signal_levels
= ddi_signal_levels(intel_dp
);
3494 if (IS_GEN9_LP(dev_priv
) || IS_CANNONLAKE(dev_priv
))
3497 mask
= DDI_BUF_EMP_MASK
;
3498 } else if (IS_CHERRYVIEW(dev_priv
)) {
3499 signal_levels
= chv_signal_levels(intel_dp
);
3500 } else if (IS_VALLEYVIEW(dev_priv
)) {
3501 signal_levels
= vlv_signal_levels(intel_dp
);
3502 } else if (IS_GEN7(dev_priv
) && port
== PORT_A
) {
3503 signal_levels
= gen7_edp_signal_levels(train_set
);
3504 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
3505 } else if (IS_GEN6(dev_priv
) && port
== PORT_A
) {
3506 signal_levels
= gen6_edp_signal_levels(train_set
);
3507 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
3509 signal_levels
= gen4_signal_levels(train_set
);
3510 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
3514 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
3516 DRM_DEBUG_KMS("Using vswing level %d\n",
3517 train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
);
3518 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3519 (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) >>
3520 DP_TRAIN_PRE_EMPHASIS_SHIFT
);
3522 intel_dp
->DP
= (intel_dp
->DP
& ~mask
) | signal_levels
;
3524 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
3525 POSTING_READ(intel_dp
->output_reg
);
3529 intel_dp_program_link_training_pattern(struct intel_dp
*intel_dp
,
3530 uint8_t dp_train_pat
)
3532 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3533 struct drm_i915_private
*dev_priv
=
3534 to_i915(intel_dig_port
->base
.base
.dev
);
3536 _intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
, dp_train_pat
);
3538 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
3539 POSTING_READ(intel_dp
->output_reg
);
3542 void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
3544 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3545 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3546 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3547 enum port port
= intel_dig_port
->port
;
3550 if (!HAS_DDI(dev_priv
))
3553 val
= I915_READ(DP_TP_CTL(port
));
3554 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
3555 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
3556 I915_WRITE(DP_TP_CTL(port
), val
);
3559 * On PORT_A we can have only eDP in SST mode. There the only reason
3560 * we need to set idle transmission mode is to work around a HW issue
3561 * where we enable the pipe while not in idle link-training mode.
3562 * In this case there is requirement to wait for a minimum number of
3563 * idle patterns to be sent.
3568 if (intel_wait_for_register(dev_priv
,DP_TP_STATUS(port
),
3569 DP_TP_STATUS_IDLE_DONE
,
3570 DP_TP_STATUS_IDLE_DONE
,
3572 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3576 intel_dp_link_down(struct intel_dp
*intel_dp
)
3578 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3579 struct intel_crtc
*crtc
= to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3580 enum port port
= intel_dig_port
->port
;
3581 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3582 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3583 uint32_t DP
= intel_dp
->DP
;
3585 if (WARN_ON(HAS_DDI(dev_priv
)))
3588 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
3591 DRM_DEBUG_KMS("\n");
3593 if ((IS_GEN7(dev_priv
) && port
== PORT_A
) ||
3594 (HAS_PCH_CPT(dev_priv
) && port
!= PORT_A
)) {
3595 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
3596 DP
|= DP_LINK_TRAIN_PAT_IDLE_CPT
;
3598 if (IS_CHERRYVIEW(dev_priv
))
3599 DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
3601 DP
&= ~DP_LINK_TRAIN_MASK
;
3602 DP
|= DP_LINK_TRAIN_PAT_IDLE
;
3604 I915_WRITE(intel_dp
->output_reg
, DP
);
3605 POSTING_READ(intel_dp
->output_reg
);
3607 DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
3608 I915_WRITE(intel_dp
->output_reg
, DP
);
3609 POSTING_READ(intel_dp
->output_reg
);
3612 * HW workaround for IBX, we need to move the port
3613 * to transcoder A after disabling it to allow the
3614 * matching HDMI port to be enabled on transcoder A.
3616 if (HAS_PCH_IBX(dev_priv
) && crtc
->pipe
== PIPE_B
&& port
!= PORT_A
) {
3618 * We get CPU/PCH FIFO underruns on the other pipe when
3619 * doing the workaround. Sweep them under the rug.
3621 intel_set_cpu_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
3622 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
3624 /* always enable with pattern 1 (as per spec) */
3625 DP
&= ~(DP_PIPEB_SELECT
| DP_LINK_TRAIN_MASK
);
3626 DP
|= DP_PORT_EN
| DP_LINK_TRAIN_PAT_1
;
3627 I915_WRITE(intel_dp
->output_reg
, DP
);
3628 POSTING_READ(intel_dp
->output_reg
);
3631 I915_WRITE(intel_dp
->output_reg
, DP
);
3632 POSTING_READ(intel_dp
->output_reg
);
3634 intel_wait_for_vblank_if_active(dev_priv
, PIPE_A
);
3635 intel_set_cpu_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
3636 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
3639 msleep(intel_dp
->panel_power_down_delay
);
3643 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
3645 intel_dp
->active_pipe
= INVALID_PIPE
;
3646 pps_unlock(intel_dp
);
3651 intel_dp_read_dpcd(struct intel_dp
*intel_dp
)
3653 if (drm_dp_dpcd_read(&intel_dp
->aux
, 0x000, intel_dp
->dpcd
,
3654 sizeof(intel_dp
->dpcd
)) < 0)
3655 return false; /* aux transfer failed */
3657 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp
->dpcd
), intel_dp
->dpcd
);
3659 return intel_dp
->dpcd
[DP_DPCD_REV
] != 0;
3663 intel_edp_init_dpcd(struct intel_dp
*intel_dp
)
3665 struct drm_i915_private
*dev_priv
=
3666 to_i915(dp_to_dig_port(intel_dp
)->base
.base
.dev
);
3668 /* this function is meant to be called only once */
3669 WARN_ON(intel_dp
->dpcd
[DP_DPCD_REV
] != 0);
3671 if (!intel_dp_read_dpcd(intel_dp
))
3674 drm_dp_read_desc(&intel_dp
->aux
, &intel_dp
->desc
,
3675 drm_dp_is_branch(intel_dp
->dpcd
));
3677 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
3678 dev_priv
->no_aux_handshake
= intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
3679 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
3681 /* Check if the panel supports PSR */
3682 drm_dp_dpcd_read(&intel_dp
->aux
, DP_PSR_SUPPORT
,
3684 sizeof(intel_dp
->psr_dpcd
));
3685 if (intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
) {
3686 dev_priv
->psr
.sink_support
= true;
3687 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3690 if (INTEL_GEN(dev_priv
) >= 9 &&
3691 (intel_dp
->psr_dpcd
[0] & DP_PSR2_IS_SUPPORTED
)) {
3692 uint8_t frame_sync_cap
;
3694 dev_priv
->psr
.sink_support
= true;
3695 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
3696 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP
,
3697 &frame_sync_cap
) != 1)
3699 dev_priv
->psr
.aux_frame_sync
= frame_sync_cap
? true : false;
3700 /* PSR2 needs frame sync as well */
3701 dev_priv
->psr
.psr2_support
= dev_priv
->psr
.aux_frame_sync
;
3702 DRM_DEBUG_KMS("PSR2 %s on sink",
3703 dev_priv
->psr
.psr2_support
? "supported" : "not supported");
3705 if (dev_priv
->psr
.psr2_support
) {
3706 dev_priv
->psr
.y_cord_support
=
3707 intel_dp_get_y_cord_status(intel_dp
);
3708 dev_priv
->psr
.colorimetry_support
=
3709 intel_dp_get_colorimetry_status(intel_dp
);
3710 dev_priv
->psr
.alpm
=
3711 intel_dp_get_alpm_status(intel_dp
);
3717 * Read the eDP display control registers.
3719 * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
3720 * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
3721 * set, but require eDP 1.4+ detection (e.g. for supported link rates
3722 * method). The display control registers should read zero if they're
3723 * not supported anyway.
3725 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_EDP_DPCD_REV
,
3726 intel_dp
->edp_dpcd
, sizeof(intel_dp
->edp_dpcd
)) ==
3727 sizeof(intel_dp
->edp_dpcd
))
3728 DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp
->edp_dpcd
),
3729 intel_dp
->edp_dpcd
);
3731 /* Intermediate frequency support */
3732 if (intel_dp
->edp_dpcd
[0] >= 0x03) { /* eDp v1.4 or higher */
3733 __le16 sink_rates
[DP_MAX_SUPPORTED_RATES
];
3736 drm_dp_dpcd_read(&intel_dp
->aux
, DP_SUPPORTED_LINK_RATES
,
3737 sink_rates
, sizeof(sink_rates
));
3739 for (i
= 0; i
< ARRAY_SIZE(sink_rates
); i
++) {
3740 int val
= le16_to_cpu(sink_rates
[i
]);
3745 /* Value read multiplied by 200kHz gives the per-lane
3746 * link rate in kHz. The source rates are, however,
3747 * stored in terms of LS_Clk kHz. The full conversion
3748 * back to symbols is
3749 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
3751 intel_dp
->sink_rates
[i
] = (val
* 200) / 10;
3753 intel_dp
->num_sink_rates
= i
;
3756 if (intel_dp
->num_sink_rates
)
3757 intel_dp
->use_rate_select
= true;
3759 intel_dp_set_sink_rates(intel_dp
);
3761 intel_dp_set_common_rates(intel_dp
);
3768 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
3772 if (!intel_dp_read_dpcd(intel_dp
))
3775 /* Don't clobber cached eDP rates. */
3776 if (!intel_dp_is_edp(intel_dp
)) {
3777 intel_dp_set_sink_rates(intel_dp
);
3778 intel_dp_set_common_rates(intel_dp
);
3781 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_SINK_COUNT
, &sink_count
) <= 0)
3785 * Sink count can change between short pulse hpd hence
3786 * a member variable in intel_dp will track any changes
3787 * between short pulse interrupts.
3789 intel_dp
->sink_count
= DP_GET_SINK_COUNT(sink_count
);
3792 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3793 * a dongle is present but no display. Unless we require to know
3794 * if a dongle is present or not, we don't need to update
3795 * downstream port information. So, an early return here saves
3796 * time from performing other operations which are not required.
3798 if (!intel_dp_is_edp(intel_dp
) && !intel_dp
->sink_count
)
3801 if (!drm_dp_is_branch(intel_dp
->dpcd
))
3802 return true; /* native DP sink */
3804 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
3805 return true; /* no per-port downstream info */
3807 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_DOWNSTREAM_PORT_0
,
3808 intel_dp
->downstream_ports
,
3809 DP_MAX_DOWNSTREAM_PORTS
) < 0)
3810 return false; /* downstream port status fetch failed */
3816 intel_dp_can_mst(struct intel_dp
*intel_dp
)
3820 if (!i915
.enable_dp_mst
)
3823 if (!intel_dp
->can_mst
)
3826 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x12)
3829 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_MSTM_CAP
, &mstm_cap
) != 1)
3832 return mstm_cap
& DP_MST_CAP
;
3836 intel_dp_configure_mst(struct intel_dp
*intel_dp
)
3838 if (!i915
.enable_dp_mst
)
3841 if (!intel_dp
->can_mst
)
3844 intel_dp
->is_mst
= intel_dp_can_mst(intel_dp
);
3846 if (intel_dp
->is_mst
)
3847 DRM_DEBUG_KMS("Sink is MST capable\n");
3849 DRM_DEBUG_KMS("Sink is not MST capable\n");
3851 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
3855 static int intel_dp_sink_crc_stop(struct intel_dp
*intel_dp
)
3857 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3858 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
3859 struct intel_crtc
*intel_crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
3865 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0) {
3866 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3871 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3872 buf
& ~DP_TEST_SINK_START
) < 0) {
3873 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3879 intel_wait_for_vblank(dev_priv
, intel_crtc
->pipe
);
3881 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
3882 DP_TEST_SINK_MISC
, &buf
) < 0) {
3886 count
= buf
& DP_TEST_COUNT_MASK
;
3887 } while (--attempts
&& count
);
3889 if (attempts
== 0) {
3890 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
3895 hsw_enable_ips(intel_crtc
);
3899 static int intel_dp_sink_crc_start(struct intel_dp
*intel_dp
)
3901 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3902 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
3903 struct intel_crtc
*intel_crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
3907 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, &buf
) < 0)
3910 if (!(buf
& DP_TEST_CRC_SUPPORTED
))
3913 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0)
3916 if (buf
& DP_TEST_SINK_START
) {
3917 ret
= intel_dp_sink_crc_stop(intel_dp
);
3922 hsw_disable_ips(intel_crtc
);
3924 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3925 buf
| DP_TEST_SINK_START
) < 0) {
3926 hsw_enable_ips(intel_crtc
);
3930 intel_wait_for_vblank(dev_priv
, intel_crtc
->pipe
);
3934 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
)
3936 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3937 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
3938 struct intel_crtc
*intel_crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
3943 ret
= intel_dp_sink_crc_start(intel_dp
);
3948 intel_wait_for_vblank(dev_priv
, intel_crtc
->pipe
);
3950 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
3951 DP_TEST_SINK_MISC
, &buf
) < 0) {
3955 count
= buf
& DP_TEST_COUNT_MASK
;
3957 } while (--attempts
&& count
== 0);
3959 if (attempts
== 0) {
3960 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3965 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_CRC_R_CR
, crc
, 6) < 0) {
3971 intel_dp_sink_crc_stop(intel_dp
);
3976 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3978 return drm_dp_dpcd_readb(&intel_dp
->aux
, DP_DEVICE_SERVICE_IRQ_VECTOR
,
3979 sink_irq_vector
) == 1;
3983 intel_dp_get_sink_irq_esi(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3987 ret
= drm_dp_dpcd_read(&intel_dp
->aux
,
3989 sink_irq_vector
, 14);
3996 static uint8_t intel_dp_autotest_link_training(struct intel_dp
*intel_dp
)
3999 int min_lane_count
= 1;
4000 int link_rate_index
, test_link_rate
;
4001 uint8_t test_lane_count
, test_link_bw
;
4005 /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
4006 status
= drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_LANE_COUNT
,
4010 DRM_DEBUG_KMS("Lane count read failed\n");
4013 test_lane_count
&= DP_MAX_LANE_COUNT_MASK
;
4014 /* Validate the requested lane count */
4015 if (test_lane_count
< min_lane_count
||
4016 test_lane_count
> intel_dp
->max_link_lane_count
)
4019 status
= drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_LINK_RATE
,
4022 DRM_DEBUG_KMS("Link Rate read failed\n");
4025 /* Validate the requested link rate */
4026 test_link_rate
= drm_dp_bw_code_to_link_rate(test_link_bw
);
4027 link_rate_index
= intel_dp_rate_index(intel_dp
->common_rates
,
4028 intel_dp
->num_common_rates
,
4030 if (link_rate_index
< 0)
4033 intel_dp
->compliance
.test_lane_count
= test_lane_count
;
4034 intel_dp
->compliance
.test_link_rate
= test_link_rate
;
4039 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp
*intel_dp
)
4041 uint8_t test_pattern
;
4043 __be16 h_width
, v_height
;
4046 /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4047 status
= drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_PATTERN
,
4050 DRM_DEBUG_KMS("Test pattern read failed\n");
4053 if (test_pattern
!= DP_COLOR_RAMP
)
4056 status
= drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_H_WIDTH_HI
,
4059 DRM_DEBUG_KMS("H Width read failed\n");
4063 status
= drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_V_HEIGHT_HI
,
4066 DRM_DEBUG_KMS("V Height read failed\n");
4070 status
= drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_MISC0
,
4073 DRM_DEBUG_KMS("TEST MISC read failed\n");
4076 if ((test_misc
& DP_TEST_COLOR_FORMAT_MASK
) != DP_COLOR_FORMAT_RGB
)
4078 if (test_misc
& DP_TEST_DYNAMIC_RANGE_CEA
)
4080 switch (test_misc
& DP_TEST_BIT_DEPTH_MASK
) {
4081 case DP_TEST_BIT_DEPTH_6
:
4082 intel_dp
->compliance
.test_data
.bpc
= 6;
4084 case DP_TEST_BIT_DEPTH_8
:
4085 intel_dp
->compliance
.test_data
.bpc
= 8;
4091 intel_dp
->compliance
.test_data
.video_pattern
= test_pattern
;
4092 intel_dp
->compliance
.test_data
.hdisplay
= be16_to_cpu(h_width
);
4093 intel_dp
->compliance
.test_data
.vdisplay
= be16_to_cpu(v_height
);
4094 /* Set test active flag here so userspace doesn't interrupt things */
4095 intel_dp
->compliance
.test_active
= 1;
4100 static uint8_t intel_dp_autotest_edid(struct intel_dp
*intel_dp
)
4102 uint8_t test_result
= DP_TEST_ACK
;
4103 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4104 struct drm_connector
*connector
= &intel_connector
->base
;
4106 if (intel_connector
->detect_edid
== NULL
||
4107 connector
->edid_corrupt
||
4108 intel_dp
->aux
.i2c_defer_count
> 6) {
4109 /* Check EDID read for NACKs, DEFERs and corruption
4110 * (DP CTS 1.2 Core r1.1)
4111 * 4.2.2.4 : Failed EDID read, I2C_NAK
4112 * 4.2.2.5 : Failed EDID read, I2C_DEFER
4113 * 4.2.2.6 : EDID corruption detected
4114 * Use failsafe mode for all cases
4116 if (intel_dp
->aux
.i2c_nack_count
> 0 ||
4117 intel_dp
->aux
.i2c_defer_count
> 0)
4118 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4119 intel_dp
->aux
.i2c_nack_count
,
4120 intel_dp
->aux
.i2c_defer_count
);
4121 intel_dp
->compliance
.test_data
.edid
= INTEL_DP_RESOLUTION_FAILSAFE
;
4123 struct edid
*block
= intel_connector
->detect_edid
;
4125 /* We have to write the checksum
4126 * of the last block read
4128 block
+= intel_connector
->detect_edid
->extensions
;
4130 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_EDID_CHECKSUM
,
4131 block
->checksum
) <= 0)
4132 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4134 test_result
= DP_TEST_ACK
| DP_TEST_EDID_CHECKSUM_WRITE
;
4135 intel_dp
->compliance
.test_data
.edid
= INTEL_DP_RESOLUTION_PREFERRED
;
4138 /* Set test active flag here so userspace doesn't interrupt things */
4139 intel_dp
->compliance
.test_active
= 1;
4144 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp
*intel_dp
)
4146 uint8_t test_result
= DP_TEST_NAK
;
4150 static void intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
4152 uint8_t response
= DP_TEST_NAK
;
4153 uint8_t request
= 0;
4156 status
= drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_REQUEST
, &request
);
4158 DRM_DEBUG_KMS("Could not read test request from sink\n");
4163 case DP_TEST_LINK_TRAINING
:
4164 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4165 response
= intel_dp_autotest_link_training(intel_dp
);
4167 case DP_TEST_LINK_VIDEO_PATTERN
:
4168 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4169 response
= intel_dp_autotest_video_pattern(intel_dp
);
4171 case DP_TEST_LINK_EDID_READ
:
4172 DRM_DEBUG_KMS("EDID test requested\n");
4173 response
= intel_dp_autotest_edid(intel_dp
);
4175 case DP_TEST_LINK_PHY_TEST_PATTERN
:
4176 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4177 response
= intel_dp_autotest_phy_pattern(intel_dp
);
4180 DRM_DEBUG_KMS("Invalid test request '%02x'\n", request
);
4184 if (response
& DP_TEST_ACK
)
4185 intel_dp
->compliance
.test_type
= request
;
4188 status
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_RESPONSE
, response
);
4190 DRM_DEBUG_KMS("Could not write test response to sink\n");
4194 intel_dp_check_mst_status(struct intel_dp
*intel_dp
)
4198 if (intel_dp
->is_mst
) {
4203 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
4207 /* check link status - esi[10] = 0x200c */
4208 if (intel_dp
->active_mst_links
&&
4209 !drm_dp_channel_eq_ok(&esi
[10], intel_dp
->lane_count
)) {
4210 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4211 intel_dp_start_link_train(intel_dp
);
4212 intel_dp_stop_link_train(intel_dp
);
4215 DRM_DEBUG_KMS("got esi %3ph\n", esi
);
4216 ret
= drm_dp_mst_hpd_irq(&intel_dp
->mst_mgr
, esi
, &handled
);
4219 for (retry
= 0; retry
< 3; retry
++) {
4221 wret
= drm_dp_dpcd_write(&intel_dp
->aux
,
4222 DP_SINK_COUNT_ESI
+1,
4229 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
4231 DRM_DEBUG_KMS("got esi2 %3ph\n", esi
);
4239 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4240 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4241 intel_dp
->is_mst
= false;
4242 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
4243 /* send a hotplug event */
4244 drm_kms_helper_hotplug_event(intel_dig_port
->base
.base
.dev
);
4251 intel_dp_retrain_link(struct intel_dp
*intel_dp
)
4253 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
4254 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
4255 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
4257 /* Suppress underruns caused by re-training */
4258 intel_set_cpu_fifo_underrun_reporting(dev_priv
, crtc
->pipe
, false);
4259 if (crtc
->config
->has_pch_encoder
)
4260 intel_set_pch_fifo_underrun_reporting(dev_priv
,
4261 intel_crtc_pch_transcoder(crtc
), false);
4263 intel_dp_start_link_train(intel_dp
);
4264 intel_dp_stop_link_train(intel_dp
);
4266 /* Keep underrun reporting disabled until things are stable */
4267 intel_wait_for_vblank(dev_priv
, crtc
->pipe
);
4269 intel_set_cpu_fifo_underrun_reporting(dev_priv
, crtc
->pipe
, true);
4270 if (crtc
->config
->has_pch_encoder
)
4271 intel_set_pch_fifo_underrun_reporting(dev_priv
,
4272 intel_crtc_pch_transcoder(crtc
), true);
4276 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
4278 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4279 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4280 u8 link_status
[DP_LINK_STATUS_SIZE
];
4282 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
4284 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
4285 DRM_ERROR("Failed to get link status\n");
4289 if (!intel_encoder
->base
.crtc
)
4292 if (!to_intel_crtc(intel_encoder
->base
.crtc
)->active
)
4296 * Validate the cached values of intel_dp->link_rate and
4297 * intel_dp->lane_count before attempting to retrain.
4299 if (!intel_dp_link_params_valid(intel_dp
))
4302 /* Retrain if Channel EQ or CR not ok */
4303 if (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
4304 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4305 intel_encoder
->base
.name
);
4307 intel_dp_retrain_link(intel_dp
);
4312 * According to DP spec
4315 * 2. Configure link according to Receiver Capabilities
4316 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4317 * 4. Check link status on receipt of hot-plug interrupt
4319 * intel_dp_short_pulse - handles short pulse interrupts
4320 * when full detection is not required.
4321 * Returns %true if short pulse is handled and full detection
4322 * is NOT required and %false otherwise.
4325 intel_dp_short_pulse(struct intel_dp
*intel_dp
)
4327 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4328 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4329 u8 sink_irq_vector
= 0;
4330 u8 old_sink_count
= intel_dp
->sink_count
;
4334 * Clearing compliance test variables to allow capturing
4335 * of values for next automated test request.
4337 memset(&intel_dp
->compliance
, 0, sizeof(intel_dp
->compliance
));
4340 * Now read the DPCD to see if it's actually running
4341 * If the current value of sink count doesn't match with
4342 * the value that was stored earlier or dpcd read failed
4343 * we need to do full detection
4345 ret
= intel_dp_get_dpcd(intel_dp
);
4347 if ((old_sink_count
!= intel_dp
->sink_count
) || !ret
) {
4348 /* No need to proceed if we are going to do full detect */
4352 /* Try to read the source of the interrupt */
4353 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4354 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
) &&
4355 sink_irq_vector
!= 0) {
4356 /* Clear interrupt source */
4357 drm_dp_dpcd_writeb(&intel_dp
->aux
,
4358 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4361 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4362 intel_dp_handle_test_request(intel_dp
);
4363 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4364 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4367 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
4368 intel_dp_check_link_status(intel_dp
);
4369 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
4370 if (intel_dp
->compliance
.test_type
== DP_TEST_LINK_TRAINING
) {
4371 DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
4372 /* Send a Hotplug Uevent to userspace to start modeset */
4373 drm_kms_helper_hotplug_event(intel_encoder
->base
.dev
);
4379 /* XXX this is probably wrong for multiple downstream ports */
4380 static enum drm_connector_status
4381 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
4383 struct intel_lspcon
*lspcon
= dp_to_lspcon(intel_dp
);
4384 uint8_t *dpcd
= intel_dp
->dpcd
;
4388 lspcon_resume(lspcon
);
4390 if (!intel_dp_get_dpcd(intel_dp
))
4391 return connector_status_disconnected
;
4393 if (intel_dp_is_edp(intel_dp
))
4394 return connector_status_connected
;
4396 /* if there's no downstream port, we're done */
4397 if (!drm_dp_is_branch(dpcd
))
4398 return connector_status_connected
;
4400 /* If we're HPD-aware, SINK_COUNT changes dynamically */
4401 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4402 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
) {
4404 return intel_dp
->sink_count
?
4405 connector_status_connected
: connector_status_disconnected
;
4408 if (intel_dp_can_mst(intel_dp
))
4409 return connector_status_connected
;
4411 /* If no HPD, poke DDC gently */
4412 if (drm_probe_ddc(&intel_dp
->aux
.ddc
))
4413 return connector_status_connected
;
4415 /* Well we tried, say unknown for unreliable port types */
4416 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
4417 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
4418 if (type
== DP_DS_PORT_TYPE_VGA
||
4419 type
== DP_DS_PORT_TYPE_NON_EDID
)
4420 return connector_status_unknown
;
4422 type
= intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
4423 DP_DWN_STRM_PORT_TYPE_MASK
;
4424 if (type
== DP_DWN_STRM_PORT_TYPE_ANALOG
||
4425 type
== DP_DWN_STRM_PORT_TYPE_OTHER
)
4426 return connector_status_unknown
;
4429 /* Anything else is out of spec, warn and ignore */
4430 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4431 return connector_status_disconnected
;
4434 static enum drm_connector_status
4435 edp_detect(struct intel_dp
*intel_dp
)
4437 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4438 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4439 enum drm_connector_status status
;
4441 status
= intel_panel_detect(dev_priv
);
4442 if (status
== connector_status_unknown
)
4443 status
= connector_status_connected
;
4448 static bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
4449 struct intel_digital_port
*port
)
4453 switch (port
->port
) {
4457 bit
= SDE_PORTB_HOTPLUG
;
4460 bit
= SDE_PORTC_HOTPLUG
;
4463 bit
= SDE_PORTD_HOTPLUG
;
4466 MISSING_CASE(port
->port
);
4470 return I915_READ(SDEISR
) & bit
;
4473 static bool cpt_digital_port_connected(struct drm_i915_private
*dev_priv
,
4474 struct intel_digital_port
*port
)
4478 switch (port
->port
) {
4482 bit
= SDE_PORTB_HOTPLUG_CPT
;
4485 bit
= SDE_PORTC_HOTPLUG_CPT
;
4488 bit
= SDE_PORTD_HOTPLUG_CPT
;
4491 bit
= SDE_PORTE_HOTPLUG_SPT
;
4494 MISSING_CASE(port
->port
);
4498 return I915_READ(SDEISR
) & bit
;
4501 static bool g4x_digital_port_connected(struct drm_i915_private
*dev_priv
,
4502 struct intel_digital_port
*port
)
4506 switch (port
->port
) {
4508 bit
= PORTB_HOTPLUG_LIVE_STATUS_G4X
;
4511 bit
= PORTC_HOTPLUG_LIVE_STATUS_G4X
;
4514 bit
= PORTD_HOTPLUG_LIVE_STATUS_G4X
;
4517 MISSING_CASE(port
->port
);
4521 return I915_READ(PORT_HOTPLUG_STAT
) & bit
;
4524 static bool gm45_digital_port_connected(struct drm_i915_private
*dev_priv
,
4525 struct intel_digital_port
*port
)
4529 switch (port
->port
) {
4531 bit
= PORTB_HOTPLUG_LIVE_STATUS_GM45
;
4534 bit
= PORTC_HOTPLUG_LIVE_STATUS_GM45
;
4537 bit
= PORTD_HOTPLUG_LIVE_STATUS_GM45
;
4540 MISSING_CASE(port
->port
);
4544 return I915_READ(PORT_HOTPLUG_STAT
) & bit
;
4547 static bool bxt_digital_port_connected(struct drm_i915_private
*dev_priv
,
4548 struct intel_digital_port
*intel_dig_port
)
4550 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4554 intel_hpd_pin_to_port(intel_encoder
->hpd_pin
, &port
);
4557 bit
= BXT_DE_PORT_HP_DDIA
;
4560 bit
= BXT_DE_PORT_HP_DDIB
;
4563 bit
= BXT_DE_PORT_HP_DDIC
;
4570 return I915_READ(GEN8_DE_PORT_ISR
) & bit
;
4574 * intel_digital_port_connected - is the specified port connected?
4575 * @dev_priv: i915 private structure
4576 * @port: the port to test
4578 * Return %true if @port is connected, %false otherwise.
4580 bool intel_digital_port_connected(struct drm_i915_private
*dev_priv
,
4581 struct intel_digital_port
*port
)
4583 if (HAS_PCH_IBX(dev_priv
))
4584 return ibx_digital_port_connected(dev_priv
, port
);
4585 else if (HAS_PCH_SPLIT(dev_priv
))
4586 return cpt_digital_port_connected(dev_priv
, port
);
4587 else if (IS_GEN9_LP(dev_priv
))
4588 return bxt_digital_port_connected(dev_priv
, port
);
4589 else if (IS_GM45(dev_priv
))
4590 return gm45_digital_port_connected(dev_priv
, port
);
4592 return g4x_digital_port_connected(dev_priv
, port
);
4595 static struct edid
*
4596 intel_dp_get_edid(struct intel_dp
*intel_dp
)
4598 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4600 /* use cached edid if we have one */
4601 if (intel_connector
->edid
) {
4603 if (IS_ERR(intel_connector
->edid
))
4606 return drm_edid_duplicate(intel_connector
->edid
);
4608 return drm_get_edid(&intel_connector
->base
,
4609 &intel_dp
->aux
.ddc
);
4613 intel_dp_set_edid(struct intel_dp
*intel_dp
)
4615 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4618 intel_dp_unset_edid(intel_dp
);
4619 edid
= intel_dp_get_edid(intel_dp
);
4620 intel_connector
->detect_edid
= edid
;
4622 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
4626 intel_dp_unset_edid(struct intel_dp
*intel_dp
)
4628 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4630 kfree(intel_connector
->detect_edid
);
4631 intel_connector
->detect_edid
= NULL
;
4633 intel_dp
->has_audio
= false;
4637 intel_dp_long_pulse(struct intel_connector
*intel_connector
)
4639 struct drm_connector
*connector
= &intel_connector
->base
;
4640 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4641 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4642 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4643 struct drm_device
*dev
= connector
->dev
;
4644 enum drm_connector_status status
;
4645 u8 sink_irq_vector
= 0;
4647 WARN_ON(!drm_modeset_is_locked(&connector
->dev
->mode_config
.connection_mutex
));
4649 intel_display_power_get(to_i915(dev
), intel_dp
->aux_power_domain
);
4651 /* Can't disconnect eDP, but you can close the lid... */
4652 if (intel_dp_is_edp(intel_dp
))
4653 status
= edp_detect(intel_dp
);
4654 else if (intel_digital_port_connected(to_i915(dev
),
4655 dp_to_dig_port(intel_dp
)))
4656 status
= intel_dp_detect_dpcd(intel_dp
);
4658 status
= connector_status_disconnected
;
4660 if (status
== connector_status_disconnected
) {
4661 memset(&intel_dp
->compliance
, 0, sizeof(intel_dp
->compliance
));
4663 if (intel_dp
->is_mst
) {
4664 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4666 intel_dp
->mst_mgr
.mst_state
);
4667 intel_dp
->is_mst
= false;
4668 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
4675 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4676 intel_encoder
->type
= INTEL_OUTPUT_DP
;
4678 DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
4679 yesno(intel_dp_source_supports_hbr2(intel_dp
)),
4680 yesno(drm_dp_tps3_supported(intel_dp
->dpcd
)));
4682 if (intel_dp
->reset_link_params
) {
4683 /* Initial max link lane count */
4684 intel_dp
->max_link_lane_count
= intel_dp_max_common_lane_count(intel_dp
);
4686 /* Initial max link rate */
4687 intel_dp
->max_link_rate
= intel_dp_max_common_rate(intel_dp
);
4689 intel_dp
->reset_link_params
= false;
4692 intel_dp_print_rates(intel_dp
);
4694 drm_dp_read_desc(&intel_dp
->aux
, &intel_dp
->desc
,
4695 drm_dp_is_branch(intel_dp
->dpcd
));
4697 intel_dp_configure_mst(intel_dp
);
4699 if (intel_dp
->is_mst
) {
4701 * If we are in MST mode then this connector
4702 * won't appear connected or have anything
4705 status
= connector_status_disconnected
;
4709 * If display is now connected check links status,
4710 * there has been known issues of link loss triggerring
4713 * Some sinks (eg. ASUS PB287Q) seem to perform some
4714 * weird HPD ping pong during modesets. So we can apparently
4715 * end up with HPD going low during a modeset, and then
4716 * going back up soon after. And once that happens we must
4717 * retrain the link to get a picture. That's in case no
4718 * userspace component reacted to intermittent HPD dip.
4720 intel_dp_check_link_status(intel_dp
);
4724 * Clearing NACK and defer counts to get their exact values
4725 * while reading EDID which are required by Compliance tests
4726 * 4.2.2.4 and 4.2.2.5
4728 intel_dp
->aux
.i2c_nack_count
= 0;
4729 intel_dp
->aux
.i2c_defer_count
= 0;
4731 intel_dp_set_edid(intel_dp
);
4732 if (intel_dp_is_edp(intel_dp
) || intel_connector
->detect_edid
)
4733 status
= connector_status_connected
;
4734 intel_dp
->detect_done
= true;
4736 /* Try to read the source of the interrupt */
4737 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4738 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
) &&
4739 sink_irq_vector
!= 0) {
4740 /* Clear interrupt source */
4741 drm_dp_dpcd_writeb(&intel_dp
->aux
,
4742 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4745 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4746 intel_dp_handle_test_request(intel_dp
);
4747 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4748 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4752 if (status
!= connector_status_connected
&& !intel_dp
->is_mst
)
4753 intel_dp_unset_edid(intel_dp
);
4755 intel_display_power_put(to_i915(dev
), intel_dp
->aux_power_domain
);
4760 intel_dp_detect(struct drm_connector
*connector
,
4761 struct drm_modeset_acquire_ctx
*ctx
,
4764 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4765 int status
= connector
->status
;
4767 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4768 connector
->base
.id
, connector
->name
);
4770 /* If full detect is not performed yet, do a full detect */
4771 if (!intel_dp
->detect_done
)
4772 status
= intel_dp_long_pulse(intel_dp
->attached_connector
);
4774 intel_dp
->detect_done
= false;
4780 intel_dp_force(struct drm_connector
*connector
)
4782 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4783 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4784 struct drm_i915_private
*dev_priv
= to_i915(intel_encoder
->base
.dev
);
4786 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4787 connector
->base
.id
, connector
->name
);
4788 intel_dp_unset_edid(intel_dp
);
4790 if (connector
->status
!= connector_status_connected
)
4793 intel_display_power_get(dev_priv
, intel_dp
->aux_power_domain
);
4795 intel_dp_set_edid(intel_dp
);
4797 intel_display_power_put(dev_priv
, intel_dp
->aux_power_domain
);
4799 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4800 intel_encoder
->type
= INTEL_OUTPUT_DP
;
4803 static int intel_dp_get_modes(struct drm_connector
*connector
)
4805 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4808 edid
= intel_connector
->detect_edid
;
4810 int ret
= intel_connector_update_modes(connector
, edid
);
4815 /* if eDP has no EDID, fall back to fixed mode */
4816 if (intel_dp_is_edp(intel_attached_dp(connector
)) &&
4817 intel_connector
->panel
.fixed_mode
) {
4818 struct drm_display_mode
*mode
;
4820 mode
= drm_mode_duplicate(connector
->dev
,
4821 intel_connector
->panel
.fixed_mode
);
4823 drm_mode_probed_add(connector
, mode
);
4832 intel_dp_connector_register(struct drm_connector
*connector
)
4834 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4837 ret
= intel_connector_register(connector
);
4841 i915_debugfs_connector_add(connector
);
4843 DRM_DEBUG_KMS("registering %s bus for %s\n",
4844 intel_dp
->aux
.name
, connector
->kdev
->kobj
.name
);
4846 intel_dp
->aux
.dev
= connector
->kdev
;
4847 return drm_dp_aux_register(&intel_dp
->aux
);
4851 intel_dp_connector_unregister(struct drm_connector
*connector
)
4853 drm_dp_aux_unregister(&intel_attached_dp(connector
)->aux
);
4854 intel_connector_unregister(connector
);
4858 intel_dp_connector_destroy(struct drm_connector
*connector
)
4860 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4862 kfree(intel_connector
->detect_edid
);
4864 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
4865 kfree(intel_connector
->edid
);
4868 * Can't call intel_dp_is_edp() since the encoder may have been
4869 * destroyed already.
4871 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
4872 intel_panel_fini(&intel_connector
->panel
);
4874 drm_connector_cleanup(connector
);
4878 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
4880 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
4881 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4883 intel_dp_mst_encoder_cleanup(intel_dig_port
);
4884 if (intel_dp_is_edp(intel_dp
)) {
4885 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4887 * vdd might still be enabled do to the delayed vdd off.
4888 * Make sure vdd is actually turned off here.
4891 edp_panel_vdd_off_sync(intel_dp
);
4892 pps_unlock(intel_dp
);
4894 if (intel_dp
->edp_notifier
.notifier_call
) {
4895 unregister_reboot_notifier(&intel_dp
->edp_notifier
);
4896 intel_dp
->edp_notifier
.notifier_call
= NULL
;
4900 intel_dp_aux_fini(intel_dp
);
4902 drm_encoder_cleanup(encoder
);
4903 kfree(intel_dig_port
);
4906 void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder
)
4908 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4910 if (!intel_dp_is_edp(intel_dp
))
4914 * vdd might still be enabled do to the delayed vdd off.
4915 * Make sure vdd is actually turned off here.
4917 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4919 edp_panel_vdd_off_sync(intel_dp
);
4920 pps_unlock(intel_dp
);
4923 static void intel_edp_panel_vdd_sanitize(struct intel_dp
*intel_dp
)
4925 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4926 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4927 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4929 lockdep_assert_held(&dev_priv
->pps_mutex
);
4931 if (!edp_have_panel_vdd(intel_dp
))
4935 * The VDD bit needs a power domain reference, so if the bit is
4936 * already enabled when we boot or resume, grab this reference and
4937 * schedule a vdd off, so we don't hold on to the reference
4940 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4941 intel_display_power_get(dev_priv
, intel_dp
->aux_power_domain
);
4943 edp_panel_vdd_schedule_off(intel_dp
);
4946 static enum pipe
vlv_active_pipe(struct intel_dp
*intel_dp
)
4948 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
4950 if ((intel_dp
->DP
& DP_PORT_EN
) == 0)
4951 return INVALID_PIPE
;
4953 if (IS_CHERRYVIEW(dev_priv
))
4954 return DP_PORT_TO_PIPE_CHV(intel_dp
->DP
);
4956 return PORT_TO_PIPE(intel_dp
->DP
);
4959 void intel_dp_encoder_reset(struct drm_encoder
*encoder
)
4961 struct drm_i915_private
*dev_priv
= to_i915(encoder
->dev
);
4962 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
4963 struct intel_lspcon
*lspcon
= dp_to_lspcon(intel_dp
);
4965 if (!HAS_DDI(dev_priv
))
4966 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
4969 lspcon_resume(lspcon
);
4971 intel_dp
->reset_link_params
= true;
4975 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
4976 intel_dp
->active_pipe
= vlv_active_pipe(intel_dp
);
4978 if (intel_dp_is_edp(intel_dp
)) {
4979 /* Reinit the power sequencer, in case BIOS did something with it. */
4980 intel_dp_pps_init(encoder
->dev
, intel_dp
);
4981 intel_edp_panel_vdd_sanitize(intel_dp
);
4984 pps_unlock(intel_dp
);
4987 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
4988 .dpms
= drm_atomic_helper_connector_dpms
,
4989 .force
= intel_dp_force
,
4990 .fill_modes
= drm_helper_probe_single_connector_modes
,
4991 .set_property
= drm_atomic_helper_connector_set_property
,
4992 .atomic_get_property
= intel_digital_connector_atomic_get_property
,
4993 .atomic_set_property
= intel_digital_connector_atomic_set_property
,
4994 .late_register
= intel_dp_connector_register
,
4995 .early_unregister
= intel_dp_connector_unregister
,
4996 .destroy
= intel_dp_connector_destroy
,
4997 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
4998 .atomic_duplicate_state
= intel_digital_connector_duplicate_state
,
5001 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
5002 .detect_ctx
= intel_dp_detect
,
5003 .get_modes
= intel_dp_get_modes
,
5004 .mode_valid
= intel_dp_mode_valid
,
5005 .atomic_check
= intel_digital_connector_atomic_check
,
5008 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
5009 .reset
= intel_dp_encoder_reset
,
5010 .destroy
= intel_dp_encoder_destroy
,
5014 intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
, bool long_hpd
)
5016 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
5017 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
5018 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5019 enum irqreturn ret
= IRQ_NONE
;
5021 if (intel_dig_port
->base
.type
!= INTEL_OUTPUT_EDP
&&
5022 intel_dig_port
->base
.type
!= INTEL_OUTPUT_HDMI
)
5023 intel_dig_port
->base
.type
= INTEL_OUTPUT_DP
;
5025 if (long_hpd
&& intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
) {
5027 * vdd off can generate a long pulse on eDP which
5028 * would require vdd on to handle it, and thus we
5029 * would end up in an endless cycle of
5030 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
5032 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
5033 port_name(intel_dig_port
->port
));
5037 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
5038 port_name(intel_dig_port
->port
),
5039 long_hpd
? "long" : "short");
5042 intel_dp
->reset_link_params
= true;
5043 intel_dp
->detect_done
= false;
5047 intel_display_power_get(dev_priv
, intel_dp
->aux_power_domain
);
5049 if (intel_dp
->is_mst
) {
5050 if (intel_dp_check_mst_status(intel_dp
) == -EINVAL
) {
5052 * If we were in MST mode, and device is not
5053 * there, get out of MST mode
5055 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5056 intel_dp
->is_mst
, intel_dp
->mst_mgr
.mst_state
);
5057 intel_dp
->is_mst
= false;
5058 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
5060 intel_dp
->detect_done
= false;
5065 if (!intel_dp
->is_mst
) {
5066 if (!intel_dp_short_pulse(intel_dp
)) {
5067 intel_dp
->detect_done
= false;
5075 intel_display_power_put(dev_priv
, intel_dp
->aux_power_domain
);
5080 /* check the VBT to see whether the eDP is on another port */
5081 bool intel_dp_is_port_edp(struct drm_i915_private
*dev_priv
, enum port port
)
5084 * eDP not supported on g4x. so bail out early just
5085 * for a bit extra safety in case the VBT is bonkers.
5087 if (INTEL_GEN(dev_priv
) < 5)
5090 if (INTEL_GEN(dev_priv
) < 9 && port
== PORT_A
)
5093 return intel_bios_is_port_edp(dev_priv
, port
);
5097 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
5099 struct drm_i915_private
*dev_priv
= to_i915(connector
->dev
);
5101 intel_attach_force_audio_property(connector
);
5102 intel_attach_broadcast_rgb_property(connector
);
5104 if (intel_dp_is_edp(intel_dp
)) {
5105 u32 allowed_scalers
;
5107 allowed_scalers
= BIT(DRM_MODE_SCALE_ASPECT
) | BIT(DRM_MODE_SCALE_FULLSCREEN
);
5108 if (!HAS_GMCH_DISPLAY(dev_priv
))
5109 allowed_scalers
|= BIT(DRM_MODE_SCALE_CENTER
);
5111 drm_connector_attach_scaling_mode_property(connector
, allowed_scalers
);
5113 connector
->state
->scaling_mode
= DRM_MODE_SCALE_ASPECT
;
5118 static void intel_dp_init_panel_power_timestamps(struct intel_dp
*intel_dp
)
5120 intel_dp
->panel_power_off_time
= ktime_get_boottime();
5121 intel_dp
->last_power_on
= jiffies
;
5122 intel_dp
->last_backlight_off
= jiffies
;
5126 intel_pps_readout_hw_state(struct drm_i915_private
*dev_priv
,
5127 struct intel_dp
*intel_dp
, struct edp_power_seq
*seq
)
5129 u32 pp_on
, pp_off
, pp_div
= 0, pp_ctl
= 0;
5130 struct pps_registers regs
;
5132 intel_pps_get_registers(dev_priv
, intel_dp
, ®s
);
5134 /* Workaround: Need to write PP_CONTROL with the unlock key as
5135 * the very first thing. */
5136 pp_ctl
= ironlake_get_pp_control(intel_dp
);
5138 pp_on
= I915_READ(regs
.pp_on
);
5139 pp_off
= I915_READ(regs
.pp_off
);
5140 if (!IS_GEN9_LP(dev_priv
) && !HAS_PCH_CNP(dev_priv
)) {
5141 I915_WRITE(regs
.pp_ctrl
, pp_ctl
);
5142 pp_div
= I915_READ(regs
.pp_div
);
5145 /* Pull timing values out of registers */
5146 seq
->t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
5147 PANEL_POWER_UP_DELAY_SHIFT
;
5149 seq
->t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
5150 PANEL_LIGHT_ON_DELAY_SHIFT
;
5152 seq
->t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
5153 PANEL_LIGHT_OFF_DELAY_SHIFT
;
5155 seq
->t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
5156 PANEL_POWER_DOWN_DELAY_SHIFT
;
5158 if (IS_GEN9_LP(dev_priv
) || HAS_PCH_CNP(dev_priv
)) {
5159 u16 tmp
= (pp_ctl
& BXT_POWER_CYCLE_DELAY_MASK
) >>
5160 BXT_POWER_CYCLE_DELAY_SHIFT
;
5162 seq
->t11_t12
= (tmp
- 1) * 1000;
5166 seq
->t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
5167 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
5172 intel_pps_dump_state(const char *state_name
, const struct edp_power_seq
*seq
)
5174 DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5176 seq
->t1_t3
, seq
->t8
, seq
->t9
, seq
->t10
, seq
->t11_t12
);
5180 intel_pps_verify_state(struct drm_i915_private
*dev_priv
,
5181 struct intel_dp
*intel_dp
)
5183 struct edp_power_seq hw
;
5184 struct edp_power_seq
*sw
= &intel_dp
->pps_delays
;
5186 intel_pps_readout_hw_state(dev_priv
, intel_dp
, &hw
);
5188 if (hw
.t1_t3
!= sw
->t1_t3
|| hw
.t8
!= sw
->t8
|| hw
.t9
!= sw
->t9
||
5189 hw
.t10
!= sw
->t10
|| hw
.t11_t12
!= sw
->t11_t12
) {
5190 DRM_ERROR("PPS state mismatch\n");
5191 intel_pps_dump_state("sw", sw
);
5192 intel_pps_dump_state("hw", &hw
);
5197 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
5198 struct intel_dp
*intel_dp
)
5200 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5201 struct edp_power_seq cur
, vbt
, spec
,
5202 *final
= &intel_dp
->pps_delays
;
5204 lockdep_assert_held(&dev_priv
->pps_mutex
);
5206 /* already initialized? */
5207 if (final
->t11_t12
!= 0)
5210 intel_pps_readout_hw_state(dev_priv
, intel_dp
, &cur
);
5212 intel_pps_dump_state("cur", &cur
);
5214 vbt
= dev_priv
->vbt
.edp
.pps
;
5216 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5217 * our hw here, which are all in 100usec. */
5218 spec
.t1_t3
= 210 * 10;
5219 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
5220 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
5221 spec
.t10
= 500 * 10;
5222 /* This one is special and actually in units of 100ms, but zero
5223 * based in the hw (so we need to add 100 ms). But the sw vbt
5224 * table multiplies it with 1000 to make it in units of 100usec,
5226 spec
.t11_t12
= (510 + 100) * 10;
5228 intel_pps_dump_state("vbt", &vbt
);
5230 /* Use the max of the register settings and vbt. If both are
5231 * unset, fall back to the spec limits. */
5232 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
5234 max(cur.field, vbt.field))
5235 assign_final(t1_t3
);
5239 assign_final(t11_t12
);
5242 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
5243 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
5244 intel_dp
->backlight_on_delay
= get_delay(t8
);
5245 intel_dp
->backlight_off_delay
= get_delay(t9
);
5246 intel_dp
->panel_power_down_delay
= get_delay(t10
);
5247 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
5250 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5251 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
5252 intel_dp
->panel_power_cycle_delay
);
5254 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5255 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
5258 * We override the HW backlight delays to 1 because we do manual waits
5259 * on them. For T8, even BSpec recommends doing it. For T9, if we
5260 * don't do this, we'll end up waiting for the backlight off delay
5261 * twice: once when we do the manual sleep, and once when we disable
5262 * the panel and wait for the PP_STATUS bit to become zero.
5269 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
5270 struct intel_dp
*intel_dp
,
5271 bool force_disable_vdd
)
5273 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5274 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
5275 int div
= dev_priv
->rawclk_freq
/ 1000;
5276 struct pps_registers regs
;
5277 enum port port
= dp_to_dig_port(intel_dp
)->port
;
5278 const struct edp_power_seq
*seq
= &intel_dp
->pps_delays
;
5280 lockdep_assert_held(&dev_priv
->pps_mutex
);
5282 intel_pps_get_registers(dev_priv
, intel_dp
, ®s
);
5285 * On some VLV machines the BIOS can leave the VDD
5286 * enabled even on power seqeuencers which aren't
5287 * hooked up to any port. This would mess up the
5288 * power domain tracking the first time we pick
5289 * one of these power sequencers for use since
5290 * edp_panel_vdd_on() would notice that the VDD was
5291 * already on and therefore wouldn't grab the power
5292 * domain reference. Disable VDD first to avoid this.
5293 * This also avoids spuriously turning the VDD on as
5294 * soon as the new power seqeuencer gets initialized.
5296 if (force_disable_vdd
) {
5297 u32 pp
= ironlake_get_pp_control(intel_dp
);
5299 WARN(pp
& PANEL_POWER_ON
, "Panel power already on\n");
5301 if (pp
& EDP_FORCE_VDD
)
5302 DRM_DEBUG_KMS("VDD already on, disabling first\n");
5304 pp
&= ~EDP_FORCE_VDD
;
5306 I915_WRITE(regs
.pp_ctrl
, pp
);
5309 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
5310 (seq
->t8
<< PANEL_LIGHT_ON_DELAY_SHIFT
);
5311 pp_off
= (seq
->t9
<< PANEL_LIGHT_OFF_DELAY_SHIFT
) |
5312 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
5313 /* Compute the divisor for the pp clock, simply match the Bspec
5315 if (IS_GEN9_LP(dev_priv
) || HAS_PCH_CNP(dev_priv
)) {
5316 pp_div
= I915_READ(regs
.pp_ctrl
);
5317 pp_div
&= ~BXT_POWER_CYCLE_DELAY_MASK
;
5318 pp_div
|= (DIV_ROUND_UP((seq
->t11_t12
+ 1), 1000)
5319 << BXT_POWER_CYCLE_DELAY_SHIFT
);
5321 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
5322 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
5323 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
5326 /* Haswell doesn't have any port selection bits for the panel
5327 * power sequencer any more. */
5328 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
5329 port_sel
= PANEL_PORT_SELECT_VLV(port
);
5330 } else if (HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
)) {
5332 port_sel
= PANEL_PORT_SELECT_DPA
;
5334 port_sel
= PANEL_PORT_SELECT_DPD
;
5339 I915_WRITE(regs
.pp_on
, pp_on
);
5340 I915_WRITE(regs
.pp_off
, pp_off
);
5341 if (IS_GEN9_LP(dev_priv
) || HAS_PCH_CNP(dev_priv
))
5342 I915_WRITE(regs
.pp_ctrl
, pp_div
);
5344 I915_WRITE(regs
.pp_div
, pp_div
);
5346 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5347 I915_READ(regs
.pp_on
),
5348 I915_READ(regs
.pp_off
),
5349 (IS_GEN9_LP(dev_priv
) || HAS_PCH_CNP(dev_priv
)) ?
5350 (I915_READ(regs
.pp_ctrl
) & BXT_POWER_CYCLE_DELAY_MASK
) :
5351 I915_READ(regs
.pp_div
));
5354 static void intel_dp_pps_init(struct drm_device
*dev
,
5355 struct intel_dp
*intel_dp
)
5357 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5359 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
5360 vlv_initial_power_sequencer_setup(intel_dp
);
5362 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
5363 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
, false);
5368 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5369 * @dev_priv: i915 device
5370 * @crtc_state: a pointer to the active intel_crtc_state
5371 * @refresh_rate: RR to be programmed
5373 * This function gets called when refresh rate (RR) has to be changed from
5374 * one frequency to another. Switches can be between high and low RR
5375 * supported by the panel or to any other RR based on media playback (in
5376 * this case, RR value needs to be passed from user space).
5378 * The caller of this function needs to take a lock on dev_priv->drrs.
5380 static void intel_dp_set_drrs_state(struct drm_i915_private
*dev_priv
,
5381 struct intel_crtc_state
*crtc_state
,
5384 struct intel_encoder
*encoder
;
5385 struct intel_digital_port
*dig_port
= NULL
;
5386 struct intel_dp
*intel_dp
= dev_priv
->drrs
.dp
;
5387 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
5388 enum drrs_refresh_rate_type index
= DRRS_HIGH_RR
;
5390 if (refresh_rate
<= 0) {
5391 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5395 if (intel_dp
== NULL
) {
5396 DRM_DEBUG_KMS("DRRS not supported.\n");
5401 * FIXME: This needs proper synchronization with psr state for some
5402 * platforms that cannot have PSR and DRRS enabled at the same time.
5405 dig_port
= dp_to_dig_port(intel_dp
);
5406 encoder
= &dig_port
->base
;
5407 intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
5410 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5414 if (dev_priv
->drrs
.type
< SEAMLESS_DRRS_SUPPORT
) {
5415 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5419 if (intel_dp
->attached_connector
->panel
.downclock_mode
->vrefresh
==
5421 index
= DRRS_LOW_RR
;
5423 if (index
== dev_priv
->drrs
.refresh_rate_type
) {
5425 "DRRS requested for previously set RR...ignoring\n");
5429 if (!crtc_state
->base
.active
) {
5430 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5434 if (INTEL_GEN(dev_priv
) >= 8 && !IS_CHERRYVIEW(dev_priv
)) {
5437 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5440 intel_dp_set_m_n(intel_crtc
, M2_N2
);
5444 DRM_ERROR("Unsupported refreshrate type\n");
5446 } else if (INTEL_GEN(dev_priv
) > 6) {
5447 i915_reg_t reg
= PIPECONF(crtc_state
->cpu_transcoder
);
5450 val
= I915_READ(reg
);
5451 if (index
> DRRS_HIGH_RR
) {
5452 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
5453 val
|= PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
5455 val
|= PIPECONF_EDP_RR_MODE_SWITCH
;
5457 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
5458 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
5460 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH
;
5462 I915_WRITE(reg
, val
);
5465 dev_priv
->drrs
.refresh_rate_type
= index
;
5467 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate
);
5471 * intel_edp_drrs_enable - init drrs struct if supported
5472 * @intel_dp: DP struct
5473 * @crtc_state: A pointer to the active crtc state.
5475 * Initializes frontbuffer_bits and drrs.dp
5477 void intel_edp_drrs_enable(struct intel_dp
*intel_dp
,
5478 struct intel_crtc_state
*crtc_state
)
5480 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
5481 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5483 if (!crtc_state
->has_drrs
) {
5484 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5488 mutex_lock(&dev_priv
->drrs
.mutex
);
5489 if (WARN_ON(dev_priv
->drrs
.dp
)) {
5490 DRM_ERROR("DRRS already enabled\n");
5494 dev_priv
->drrs
.busy_frontbuffer_bits
= 0;
5496 dev_priv
->drrs
.dp
= intel_dp
;
5499 mutex_unlock(&dev_priv
->drrs
.mutex
);
5503 * intel_edp_drrs_disable - Disable DRRS
5504 * @intel_dp: DP struct
5505 * @old_crtc_state: Pointer to old crtc_state.
5508 void intel_edp_drrs_disable(struct intel_dp
*intel_dp
,
5509 struct intel_crtc_state
*old_crtc_state
)
5511 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
5512 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5514 if (!old_crtc_state
->has_drrs
)
5517 mutex_lock(&dev_priv
->drrs
.mutex
);
5518 if (!dev_priv
->drrs
.dp
) {
5519 mutex_unlock(&dev_priv
->drrs
.mutex
);
5523 if (dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5524 intel_dp_set_drrs_state(dev_priv
, old_crtc_state
,
5525 intel_dp
->attached_connector
->panel
.fixed_mode
->vrefresh
);
5527 dev_priv
->drrs
.dp
= NULL
;
5528 mutex_unlock(&dev_priv
->drrs
.mutex
);
5530 cancel_delayed_work_sync(&dev_priv
->drrs
.work
);
5533 static void intel_edp_drrs_downclock_work(struct work_struct
*work
)
5535 struct drm_i915_private
*dev_priv
=
5536 container_of(work
, typeof(*dev_priv
), drrs
.work
.work
);
5537 struct intel_dp
*intel_dp
;
5539 mutex_lock(&dev_priv
->drrs
.mutex
);
5541 intel_dp
= dev_priv
->drrs
.dp
;
5547 * The delayed work can race with an invalidate hence we need to
5551 if (dev_priv
->drrs
.busy_frontbuffer_bits
)
5554 if (dev_priv
->drrs
.refresh_rate_type
!= DRRS_LOW_RR
) {
5555 struct drm_crtc
*crtc
= dp_to_dig_port(intel_dp
)->base
.base
.crtc
;
5557 intel_dp_set_drrs_state(dev_priv
, to_intel_crtc(crtc
)->config
,
5558 intel_dp
->attached_connector
->panel
.downclock_mode
->vrefresh
);
5562 mutex_unlock(&dev_priv
->drrs
.mutex
);
5566 * intel_edp_drrs_invalidate - Disable Idleness DRRS
5567 * @dev_priv: i915 device
5568 * @frontbuffer_bits: frontbuffer plane tracking bits
5570 * This function gets called everytime rendering on the given planes start.
5571 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5573 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5575 void intel_edp_drrs_invalidate(struct drm_i915_private
*dev_priv
,
5576 unsigned int frontbuffer_bits
)
5578 struct drm_crtc
*crtc
;
5581 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
5584 cancel_delayed_work(&dev_priv
->drrs
.work
);
5586 mutex_lock(&dev_priv
->drrs
.mutex
);
5587 if (!dev_priv
->drrs
.dp
) {
5588 mutex_unlock(&dev_priv
->drrs
.mutex
);
5592 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
5593 pipe
= to_intel_crtc(crtc
)->pipe
;
5595 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
5596 dev_priv
->drrs
.busy_frontbuffer_bits
|= frontbuffer_bits
;
5598 /* invalidate means busy screen hence upclock */
5599 if (frontbuffer_bits
&& dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5600 intel_dp_set_drrs_state(dev_priv
, to_intel_crtc(crtc
)->config
,
5601 dev_priv
->drrs
.dp
->attached_connector
->panel
.fixed_mode
->vrefresh
);
5603 mutex_unlock(&dev_priv
->drrs
.mutex
);
5607 * intel_edp_drrs_flush - Restart Idleness DRRS
5608 * @dev_priv: i915 device
5609 * @frontbuffer_bits: frontbuffer plane tracking bits
5611 * This function gets called every time rendering on the given planes has
5612 * completed or flip on a crtc is completed. So DRRS should be upclocked
5613 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5614 * if no other planes are dirty.
5616 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5618 void intel_edp_drrs_flush(struct drm_i915_private
*dev_priv
,
5619 unsigned int frontbuffer_bits
)
5621 struct drm_crtc
*crtc
;
5624 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
5627 cancel_delayed_work(&dev_priv
->drrs
.work
);
5629 mutex_lock(&dev_priv
->drrs
.mutex
);
5630 if (!dev_priv
->drrs
.dp
) {
5631 mutex_unlock(&dev_priv
->drrs
.mutex
);
5635 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
5636 pipe
= to_intel_crtc(crtc
)->pipe
;
5638 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
5639 dev_priv
->drrs
.busy_frontbuffer_bits
&= ~frontbuffer_bits
;
5641 /* flush means busy screen hence upclock */
5642 if (frontbuffer_bits
&& dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5643 intel_dp_set_drrs_state(dev_priv
, to_intel_crtc(crtc
)->config
,
5644 dev_priv
->drrs
.dp
->attached_connector
->panel
.fixed_mode
->vrefresh
);
5647 * flush also means no more activity hence schedule downclock, if all
5648 * other fbs are quiescent too
5650 if (!dev_priv
->drrs
.busy_frontbuffer_bits
)
5651 schedule_delayed_work(&dev_priv
->drrs
.work
,
5652 msecs_to_jiffies(1000));
5653 mutex_unlock(&dev_priv
->drrs
.mutex
);
5657 * DOC: Display Refresh Rate Switching (DRRS)
5659 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5660 * which enables swtching between low and high refresh rates,
5661 * dynamically, based on the usage scenario. This feature is applicable
5662 * for internal panels.
5664 * Indication that the panel supports DRRS is given by the panel EDID, which
5665 * would list multiple refresh rates for one resolution.
5667 * DRRS is of 2 types - static and seamless.
5668 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5669 * (may appear as a blink on screen) and is used in dock-undock scenario.
5670 * Seamless DRRS involves changing RR without any visual effect to the user
5671 * and can be used during normal system usage. This is done by programming
5672 * certain registers.
5674 * Support for static/seamless DRRS may be indicated in the VBT based on
5675 * inputs from the panel spec.
5677 * DRRS saves power by switching to low RR based on usage scenarios.
5679 * The implementation is based on frontbuffer tracking implementation. When
5680 * there is a disturbance on the screen triggered by user activity or a periodic
5681 * system activity, DRRS is disabled (RR is changed to high RR). When there is
5682 * no movement on screen, after a timeout of 1 second, a switch to low RR is
5685 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5686 * and intel_edp_drrs_flush() are called.
5688 * DRRS can be further extended to support other internal panels and also
5689 * the scenario of video playback wherein RR is set based on the rate
5690 * requested by userspace.
5694 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5695 * @intel_connector: eDP connector
5696 * @fixed_mode: preferred mode of panel
5698 * This function is called only once at driver load to initialize basic
5702 * Downclock mode if panel supports it, else return NULL.
5703 * DRRS support is determined by the presence of downclock mode (apart
5704 * from VBT setting).
5706 static struct drm_display_mode
*
5707 intel_dp_drrs_init(struct intel_connector
*intel_connector
,
5708 struct drm_display_mode
*fixed_mode
)
5710 struct drm_connector
*connector
= &intel_connector
->base
;
5711 struct drm_device
*dev
= connector
->dev
;
5712 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5713 struct drm_display_mode
*downclock_mode
= NULL
;
5715 INIT_DELAYED_WORK(&dev_priv
->drrs
.work
, intel_edp_drrs_downclock_work
);
5716 mutex_init(&dev_priv
->drrs
.mutex
);
5718 if (INTEL_GEN(dev_priv
) <= 6) {
5719 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5723 if (dev_priv
->vbt
.drrs_type
!= SEAMLESS_DRRS_SUPPORT
) {
5724 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5728 downclock_mode
= intel_find_panel_downclock
5729 (dev_priv
, fixed_mode
, connector
);
5731 if (!downclock_mode
) {
5732 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5736 dev_priv
->drrs
.type
= dev_priv
->vbt
.drrs_type
;
5738 dev_priv
->drrs
.refresh_rate_type
= DRRS_HIGH_RR
;
5739 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5740 return downclock_mode
;
5743 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
5744 struct intel_connector
*intel_connector
)
5746 struct drm_connector
*connector
= &intel_connector
->base
;
5747 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
5748 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5749 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5750 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5751 struct drm_display_mode
*fixed_mode
= NULL
;
5752 struct drm_display_mode
*alt_fixed_mode
= NULL
;
5753 struct drm_display_mode
*downclock_mode
= NULL
;
5755 struct drm_display_mode
*scan
;
5757 enum pipe pipe
= INVALID_PIPE
;
5759 if (!intel_dp_is_edp(intel_dp
))
5763 * On IBX/CPT we may get here with LVDS already registered. Since the
5764 * driver uses the only internal power sequencer available for both
5765 * eDP and LVDS bail out early in this case to prevent interfering
5766 * with an already powered-on LVDS power sequencer.
5768 if (intel_get_lvds_encoder(dev
)) {
5769 WARN_ON(!(HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
)));
5770 DRM_INFO("LVDS was detected, not registering eDP\n");
5777 intel_dp_init_panel_power_timestamps(intel_dp
);
5778 intel_dp_pps_init(dev
, intel_dp
);
5779 intel_edp_panel_vdd_sanitize(intel_dp
);
5781 pps_unlock(intel_dp
);
5783 /* Cache DPCD and EDID for edp. */
5784 has_dpcd
= intel_edp_init_dpcd(intel_dp
);
5787 /* if this fails, presume the device is a ghost */
5788 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5792 mutex_lock(&dev
->mode_config
.mutex
);
5793 edid
= drm_get_edid(connector
, &intel_dp
->aux
.ddc
);
5795 if (drm_add_edid_modes(connector
, edid
)) {
5796 drm_mode_connector_update_edid_property(connector
,
5798 drm_edid_to_eld(connector
, edid
);
5801 edid
= ERR_PTR(-EINVAL
);
5804 edid
= ERR_PTR(-ENOENT
);
5806 intel_connector
->edid
= edid
;
5808 /* prefer fixed mode from EDID if available, save an alt mode also */
5809 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
5810 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
5811 fixed_mode
= drm_mode_duplicate(dev
, scan
);
5812 downclock_mode
= intel_dp_drrs_init(
5813 intel_connector
, fixed_mode
);
5814 } else if (!alt_fixed_mode
) {
5815 alt_fixed_mode
= drm_mode_duplicate(dev
, scan
);
5819 /* fallback to VBT if available for eDP */
5820 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
5821 fixed_mode
= drm_mode_duplicate(dev
,
5822 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
5824 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
5825 connector
->display_info
.width_mm
= fixed_mode
->width_mm
;
5826 connector
->display_info
.height_mm
= fixed_mode
->height_mm
;
5829 mutex_unlock(&dev
->mode_config
.mutex
);
5831 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
5832 intel_dp
->edp_notifier
.notifier_call
= edp_notify_handler
;
5833 register_reboot_notifier(&intel_dp
->edp_notifier
);
5836 * Figure out the current pipe for the initial backlight setup.
5837 * If the current pipe isn't valid, try the PPS pipe, and if that
5838 * fails just assume pipe A.
5840 pipe
= vlv_active_pipe(intel_dp
);
5842 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
5843 pipe
= intel_dp
->pps_pipe
;
5845 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
5848 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5852 intel_panel_init(&intel_connector
->panel
, fixed_mode
, alt_fixed_mode
,
5854 intel_connector
->panel
.backlight
.power
= intel_edp_backlight_power
;
5855 intel_panel_setup_backlight(connector
, pipe
);
5860 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
5862 * vdd might still be enabled do to the delayed vdd off.
5863 * Make sure vdd is actually turned off here.
5866 edp_panel_vdd_off_sync(intel_dp
);
5867 pps_unlock(intel_dp
);
5872 /* Set up the hotplug pin and aux power domain. */
5874 intel_dp_init_connector_port_info(struct intel_digital_port
*intel_dig_port
)
5876 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
5877 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
5879 switch (intel_dig_port
->port
) {
5881 encoder
->hpd_pin
= HPD_PORT_A
;
5882 intel_dp
->aux_power_domain
= POWER_DOMAIN_AUX_A
;
5885 encoder
->hpd_pin
= HPD_PORT_B
;
5886 intel_dp
->aux_power_domain
= POWER_DOMAIN_AUX_B
;
5889 encoder
->hpd_pin
= HPD_PORT_C
;
5890 intel_dp
->aux_power_domain
= POWER_DOMAIN_AUX_C
;
5893 encoder
->hpd_pin
= HPD_PORT_D
;
5894 intel_dp
->aux_power_domain
= POWER_DOMAIN_AUX_D
;
5897 encoder
->hpd_pin
= HPD_PORT_E
;
5899 /* FIXME: Check VBT for actual wiring of PORT E */
5900 intel_dp
->aux_power_domain
= POWER_DOMAIN_AUX_D
;
5903 MISSING_CASE(intel_dig_port
->port
);
5907 static void intel_dp_modeset_retry_work_fn(struct work_struct
*work
)
5909 struct intel_connector
*intel_connector
;
5910 struct drm_connector
*connector
;
5912 intel_connector
= container_of(work
, typeof(*intel_connector
),
5913 modeset_retry_work
);
5914 connector
= &intel_connector
->base
;
5915 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector
->base
.id
,
5918 /* Grab the locks before changing connector property*/
5919 mutex_lock(&connector
->dev
->mode_config
.mutex
);
5920 /* Set connector link status to BAD and send a Uevent to notify
5921 * userspace to do a modeset.
5923 drm_mode_connector_set_link_status_property(connector
,
5924 DRM_MODE_LINK_STATUS_BAD
);
5925 mutex_unlock(&connector
->dev
->mode_config
.mutex
);
5926 /* Send Hotplug uevent so userspace can reprobe */
5927 drm_kms_helper_hotplug_event(connector
->dev
);
5931 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
5932 struct intel_connector
*intel_connector
)
5934 struct drm_connector
*connector
= &intel_connector
->base
;
5935 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
5936 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5937 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5938 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5939 enum port port
= intel_dig_port
->port
;
5942 /* Initialize the work for modeset in case of link train failure */
5943 INIT_WORK(&intel_connector
->modeset_retry_work
,
5944 intel_dp_modeset_retry_work_fn
);
5946 if (WARN(intel_dig_port
->max_lanes
< 1,
5947 "Not enough lanes (%d) for DP on port %c\n",
5948 intel_dig_port
->max_lanes
, port_name(port
)))
5951 intel_dp_set_source_rates(intel_dp
);
5953 intel_dp
->reset_link_params
= true;
5954 intel_dp
->pps_pipe
= INVALID_PIPE
;
5955 intel_dp
->active_pipe
= INVALID_PIPE
;
5957 /* intel_dp vfuncs */
5958 if (INTEL_GEN(dev_priv
) >= 9)
5959 intel_dp
->get_aux_clock_divider
= skl_get_aux_clock_divider
;
5960 else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
5961 intel_dp
->get_aux_clock_divider
= hsw_get_aux_clock_divider
;
5962 else if (HAS_PCH_SPLIT(dev_priv
))
5963 intel_dp
->get_aux_clock_divider
= ilk_get_aux_clock_divider
;
5965 intel_dp
->get_aux_clock_divider
= g4x_get_aux_clock_divider
;
5967 if (INTEL_GEN(dev_priv
) >= 9)
5968 intel_dp
->get_aux_send_ctl
= skl_get_aux_send_ctl
;
5970 intel_dp
->get_aux_send_ctl
= g4x_get_aux_send_ctl
;
5972 if (HAS_DDI(dev_priv
))
5973 intel_dp
->prepare_link_retrain
= intel_ddi_prepare_link_retrain
;
5975 /* Preserve the current hw state. */
5976 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
5977 intel_dp
->attached_connector
= intel_connector
;
5979 if (intel_dp_is_port_edp(dev_priv
, port
))
5980 type
= DRM_MODE_CONNECTOR_eDP
;
5982 type
= DRM_MODE_CONNECTOR_DisplayPort
;
5984 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
5985 intel_dp
->active_pipe
= vlv_active_pipe(intel_dp
);
5988 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5989 * for DP the encoder type can be set by the caller to
5990 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5992 if (type
== DRM_MODE_CONNECTOR_eDP
)
5993 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
5995 /* eDP only on port B and/or C on vlv/chv */
5996 if (WARN_ON((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
5997 intel_dp_is_edp(intel_dp
) &&
5998 port
!= PORT_B
&& port
!= PORT_C
))
6001 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
6002 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
6005 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
6006 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
6008 connector
->interlace_allowed
= true;
6009 connector
->doublescan_allowed
= 0;
6011 intel_dp_init_connector_port_info(intel_dig_port
);
6013 intel_dp_aux_init(intel_dp
);
6015 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
6016 edp_panel_vdd_work
);
6018 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
6020 if (HAS_DDI(dev_priv
))
6021 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
6023 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
6025 /* init MST on ports that can support it */
6026 if (HAS_DP_MST(dev_priv
) && !intel_dp_is_edp(intel_dp
) &&
6027 (port
== PORT_B
|| port
== PORT_C
|| port
== PORT_D
))
6028 intel_dp_mst_encoder_init(intel_dig_port
,
6029 intel_connector
->base
.base
.id
);
6031 if (!intel_edp_init_connector(intel_dp
, intel_connector
)) {
6032 intel_dp_aux_fini(intel_dp
);
6033 intel_dp_mst_encoder_cleanup(intel_dig_port
);
6037 intel_dp_add_properties(intel_dp
, connector
);
6039 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
6040 * 0xd. Failure to do so will result in spurious interrupts being
6041 * generated on the port when a cable is not attached.
6043 if (IS_G4X(dev_priv
) && !IS_GM45(dev_priv
)) {
6044 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
6045 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
6051 drm_connector_cleanup(connector
);
6056 bool intel_dp_init(struct drm_i915_private
*dev_priv
,
6057 i915_reg_t output_reg
,
6060 struct intel_digital_port
*intel_dig_port
;
6061 struct intel_encoder
*intel_encoder
;
6062 struct drm_encoder
*encoder
;
6063 struct intel_connector
*intel_connector
;
6065 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
6066 if (!intel_dig_port
)
6069 intel_connector
= intel_connector_alloc();
6070 if (!intel_connector
)
6071 goto err_connector_alloc
;
6073 intel_encoder
= &intel_dig_port
->base
;
6074 encoder
= &intel_encoder
->base
;
6076 if (drm_encoder_init(&dev_priv
->drm
, &intel_encoder
->base
,
6077 &intel_dp_enc_funcs
, DRM_MODE_ENCODER_TMDS
,
6078 "DP %c", port_name(port
)))
6079 goto err_encoder_init
;
6081 intel_encoder
->compute_config
= intel_dp_compute_config
;
6082 intel_encoder
->disable
= intel_disable_dp
;
6083 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
6084 intel_encoder
->get_config
= intel_dp_get_config
;
6085 intel_encoder
->suspend
= intel_dp_encoder_suspend
;
6086 if (IS_CHERRYVIEW(dev_priv
)) {
6087 intel_encoder
->pre_pll_enable
= chv_dp_pre_pll_enable
;
6088 intel_encoder
->pre_enable
= chv_pre_enable_dp
;
6089 intel_encoder
->enable
= vlv_enable_dp
;
6090 intel_encoder
->post_disable
= chv_post_disable_dp
;
6091 intel_encoder
->post_pll_disable
= chv_dp_post_pll_disable
;
6092 } else if (IS_VALLEYVIEW(dev_priv
)) {
6093 intel_encoder
->pre_pll_enable
= vlv_dp_pre_pll_enable
;
6094 intel_encoder
->pre_enable
= vlv_pre_enable_dp
;
6095 intel_encoder
->enable
= vlv_enable_dp
;
6096 intel_encoder
->post_disable
= vlv_post_disable_dp
;
6098 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
6099 intel_encoder
->enable
= g4x_enable_dp
;
6100 if (INTEL_GEN(dev_priv
) >= 5)
6101 intel_encoder
->post_disable
= ilk_post_disable_dp
;
6104 intel_dig_port
->port
= port
;
6105 intel_dig_port
->dp
.output_reg
= output_reg
;
6106 intel_dig_port
->max_lanes
= 4;
6108 intel_encoder
->type
= INTEL_OUTPUT_DP
;
6109 intel_encoder
->power_domain
= intel_port_to_power_domain(port
);
6110 if (IS_CHERRYVIEW(dev_priv
)) {
6112 intel_encoder
->crtc_mask
= 1 << 2;
6114 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
6116 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
6118 intel_encoder
->cloneable
= 0;
6119 intel_encoder
->port
= port
;
6121 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
6122 dev_priv
->hotplug
.irq_port
[port
] = intel_dig_port
;
6124 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
))
6125 goto err_init_connector
;
6130 drm_encoder_cleanup(encoder
);
6132 kfree(intel_connector
);
6133 err_connector_alloc
:
6134 kfree(intel_dig_port
);
6138 void intel_dp_mst_suspend(struct drm_device
*dev
)
6140 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6144 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
6145 struct intel_digital_port
*intel_dig_port
= dev_priv
->hotplug
.irq_port
[i
];
6147 if (!intel_dig_port
|| !intel_dig_port
->dp
.can_mst
)
6150 if (intel_dig_port
->dp
.is_mst
)
6151 drm_dp_mst_topology_mgr_suspend(&intel_dig_port
->dp
.mst_mgr
);
6155 void intel_dp_mst_resume(struct drm_device
*dev
)
6157 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6160 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
6161 struct intel_digital_port
*intel_dig_port
= dev_priv
->hotplug
.irq_port
[i
];
6164 if (!intel_dig_port
|| !intel_dig_port
->dp
.can_mst
)
6167 ret
= drm_dp_mst_topology_mgr_resume(&intel_dig_port
->dp
.mst_mgr
);
6169 intel_dp_check_mst_status(&intel_dig_port
->dp
);