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79e53945 JB |
1 | /* |
2 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright (c) 2007-2008 Intel Corporation | |
4 | * Jesse Barnes <jesse.barnes@intel.com> | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the next | |
14 | * paragraph) shall be included in all copies or substantial portions of the | |
15 | * Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
23 | * IN THE SOFTWARE. | |
24 | */ | |
25 | #ifndef __INTEL_DRV_H__ | |
26 | #define __INTEL_DRV_H__ | |
27 | ||
d1d70677 | 28 | #include <linux/async.h> |
79e53945 | 29 | #include <linux/i2c.h> |
178f736a | 30 | #include <linux/hdmi.h> |
e6017571 | 31 | #include <linux/sched/clock.h> |
760285e7 | 32 | #include <drm/i915_drm.h> |
80824003 | 33 | #include "i915_drv.h" |
760285e7 DH |
34 | #include <drm/drm_crtc.h> |
35 | #include <drm/drm_crtc_helper.h> | |
9338203c | 36 | #include <drm/drm_encoder.h> |
760285e7 | 37 | #include <drm/drm_fb_helper.h> |
b1ba124d | 38 | #include <drm/drm_dp_dual_mode_helper.h> |
0e32b39c | 39 | #include <drm/drm_dp_mst_helper.h> |
eeca778a | 40 | #include <drm/drm_rect.h> |
10f81c19 | 41 | #include <drm/drm_atomic.h> |
9c229127 | 42 | #include <media/cec-notifier.h> |
913d8d11 | 43 | |
1d5bfac9 | 44 | /** |
23fdbdd7 | 45 | * __wait_for - magic wait macro |
1d5bfac9 | 46 | * |
23fdbdd7 SP |
47 | * Macro to help avoid open coding check/wait/timeout patterns. Note that it's |
48 | * important that we check the condition again after having timed out, since the | |
49 | * timeout could be due to preemption or similar and we've never had a chance to | |
50 | * check the condition before the timeout. | |
1d5bfac9 | 51 | */ |
23fdbdd7 | 52 | #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \ |
3085982c | 53 | const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \ |
a54b1873 | 54 | long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \ |
b0876afd | 55 | int ret__; \ |
290b20a6 | 56 | might_sleep(); \ |
b0876afd | 57 | for (;;) { \ |
3085982c | 58 | const bool expired__ = ktime_after(ktime_get_raw(), end__); \ |
23fdbdd7 | 59 | OP; \ |
1c3c1dc6 MK |
60 | /* Guarantee COND check prior to timeout */ \ |
61 | barrier(); \ | |
b0876afd DG |
62 | if (COND) { \ |
63 | ret__ = 0; \ | |
64 | break; \ | |
65 | } \ | |
66 | if (expired__) { \ | |
67 | ret__ = -ETIMEDOUT; \ | |
913d8d11 CW |
68 | break; \ |
69 | } \ | |
a54b1873 CW |
70 | usleep_range(wait__, wait__ * 2); \ |
71 | if (wait__ < (Wmax)) \ | |
72 | wait__ <<= 1; \ | |
913d8d11 CW |
73 | } \ |
74 | ret__; \ | |
75 | }) | |
76 | ||
23fdbdd7 SP |
77 | #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \ |
78 | (Wmax)) | |
79 | #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000) | |
3f177625 | 80 | |
0351b939 TU |
81 | /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */ |
82 | #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT) | |
18f4b843 | 83 | # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic()) |
0351b939 | 84 | #else |
18f4b843 | 85 | # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0) |
0351b939 TU |
86 | #endif |
87 | ||
18f4b843 TU |
88 | #define _wait_for_atomic(COND, US, ATOMIC) \ |
89 | ({ \ | |
90 | int cpu, ret, timeout = (US) * 1000; \ | |
91 | u64 base; \ | |
92 | _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \ | |
18f4b843 TU |
93 | if (!(ATOMIC)) { \ |
94 | preempt_disable(); \ | |
95 | cpu = smp_processor_id(); \ | |
96 | } \ | |
97 | base = local_clock(); \ | |
98 | for (;;) { \ | |
99 | u64 now = local_clock(); \ | |
100 | if (!(ATOMIC)) \ | |
101 | preempt_enable(); \ | |
1c3c1dc6 MK |
102 | /* Guarantee COND check prior to timeout */ \ |
103 | barrier(); \ | |
18f4b843 TU |
104 | if (COND) { \ |
105 | ret = 0; \ | |
106 | break; \ | |
107 | } \ | |
108 | if (now - base >= timeout) { \ | |
109 | ret = -ETIMEDOUT; \ | |
0351b939 TU |
110 | break; \ |
111 | } \ | |
112 | cpu_relax(); \ | |
18f4b843 TU |
113 | if (!(ATOMIC)) { \ |
114 | preempt_disable(); \ | |
115 | if (unlikely(cpu != smp_processor_id())) { \ | |
116 | timeout -= now - base; \ | |
117 | cpu = smp_processor_id(); \ | |
118 | base = local_clock(); \ | |
119 | } \ | |
120 | } \ | |
0351b939 | 121 | } \ |
18f4b843 TU |
122 | ret; \ |
123 | }) | |
124 | ||
125 | #define wait_for_us(COND, US) \ | |
126 | ({ \ | |
127 | int ret__; \ | |
128 | BUILD_BUG_ON(!__builtin_constant_p(US)); \ | |
129 | if ((US) > 10) \ | |
a54b1873 | 130 | ret__ = _wait_for((COND), (US), 10, 10); \ |
18f4b843 TU |
131 | else \ |
132 | ret__ = _wait_for_atomic((COND), (US), 0); \ | |
0351b939 TU |
133 | ret__; \ |
134 | }) | |
135 | ||
939cf46c TU |
136 | #define wait_for_atomic_us(COND, US) \ |
137 | ({ \ | |
138 | BUILD_BUG_ON(!__builtin_constant_p(US)); \ | |
139 | BUILD_BUG_ON((US) > 50000); \ | |
140 | _wait_for_atomic((COND), (US), 1); \ | |
141 | }) | |
142 | ||
143 | #define wait_for_atomic(COND, MS) wait_for_atomic_us((COND), (MS) * 1000) | |
481b6af3 | 144 | |
49938ac4 JN |
145 | #define KHz(x) (1000 * (x)) |
146 | #define MHz(x) KHz(1000 * (x)) | |
021357ac | 147 | |
aa9664ff MK |
148 | #define KBps(x) (1000 * (x)) |
149 | #define MBps(x) KBps(1000 * (x)) | |
150 | #define GBps(x) ((u64)1000 * MBps((x))) | |
151 | ||
79e53945 JB |
152 | /* |
153 | * Display related stuff | |
154 | */ | |
155 | ||
156 | /* store information about an Ixxx DVO */ | |
157 | /* The i830->i865 use multiple DVOs with multiple i2cs */ | |
158 | /* the i915, i945 have a single sDVO i2c bus - which is different */ | |
159 | #define MAX_OUTPUTS 6 | |
160 | /* maximum connectors per crtcs in the mode set */ | |
79e53945 JB |
161 | |
162 | #define INTEL_I2C_BUS_DVO 1 | |
163 | #define INTEL_I2C_BUS_SDVO 2 | |
164 | ||
165 | /* these are outputs from the chip - integrated only | |
166 | external chips are via DVO or SDVO output */ | |
6847d71b PZ |
167 | enum intel_output_type { |
168 | INTEL_OUTPUT_UNUSED = 0, | |
169 | INTEL_OUTPUT_ANALOG = 1, | |
170 | INTEL_OUTPUT_DVO = 2, | |
171 | INTEL_OUTPUT_SDVO = 3, | |
172 | INTEL_OUTPUT_LVDS = 4, | |
173 | INTEL_OUTPUT_TVOUT = 5, | |
174 | INTEL_OUTPUT_HDMI = 6, | |
cca0502b | 175 | INTEL_OUTPUT_DP = 7, |
6847d71b PZ |
176 | INTEL_OUTPUT_EDP = 8, |
177 | INTEL_OUTPUT_DSI = 9, | |
7e732cac | 178 | INTEL_OUTPUT_DDI = 10, |
6847d71b PZ |
179 | INTEL_OUTPUT_DP_MST = 11, |
180 | }; | |
79e53945 JB |
181 | |
182 | #define INTEL_DVO_CHIP_NONE 0 | |
183 | #define INTEL_DVO_CHIP_LVDS 1 | |
184 | #define INTEL_DVO_CHIP_TMDS 2 | |
185 | #define INTEL_DVO_CHIP_TVOUT 4 | |
186 | ||
dfba2e2d SK |
187 | #define INTEL_DSI_VIDEO_MODE 0 |
188 | #define INTEL_DSI_COMMAND_MODE 1 | |
72ffa333 | 189 | |
79e53945 JB |
190 | struct intel_framebuffer { |
191 | struct drm_framebuffer base; | |
2d7a215f | 192 | struct intel_rotation_info rot_info; |
6687c906 VS |
193 | |
194 | /* for each plane in the normal GTT view */ | |
195 | struct { | |
196 | unsigned int x, y; | |
197 | } normal[2]; | |
198 | /* for each plane in the rotated GTT view */ | |
199 | struct { | |
200 | unsigned int x, y; | |
201 | unsigned int pitch; /* pixels */ | |
202 | } rotated[2]; | |
79e53945 JB |
203 | }; |
204 | ||
37811fcc CW |
205 | struct intel_fbdev { |
206 | struct drm_fb_helper helper; | |
8bcd4553 | 207 | struct intel_framebuffer *fb; |
058d88c4 | 208 | struct i915_vma *vma; |
5935485f | 209 | unsigned long vma_flags; |
43cee314 | 210 | async_cookie_t cookie; |
d978ef14 | 211 | int preferred_bpp; |
e8a8fedd LP |
212 | |
213 | /* Whether or not fbdev hpd processing is temporarily suspended */ | |
214 | bool hpd_suspended : 1; | |
215 | /* Set when a hotplug was received while HPD processing was | |
216 | * suspended | |
217 | */ | |
218 | bool hpd_waiting : 1; | |
219 | ||
220 | /* Protects hpd_suspended */ | |
221 | struct mutex hpd_lock; | |
37811fcc | 222 | }; |
79e53945 | 223 | |
4211bdba ID |
224 | enum intel_hotplug_state { |
225 | INTEL_HOTPLUG_UNCHANGED, | |
226 | INTEL_HOTPLUG_CHANGED, | |
227 | INTEL_HOTPLUG_RETRY, | |
228 | }; | |
229 | ||
21d40d37 | 230 | struct intel_encoder { |
4ef69c7a | 231 | struct drm_encoder base; |
9a935856 | 232 | |
6847d71b | 233 | enum intel_output_type type; |
03cdc1d4 | 234 | enum port port; |
bc079e8b | 235 | unsigned int cloneable; |
4211bdba ID |
236 | enum intel_hotplug_state (*hotplug)(struct intel_encoder *encoder, |
237 | struct intel_connector *connector, | |
238 | bool irq_received); | |
7e732cac VS |
239 | enum intel_output_type (*compute_output_type)(struct intel_encoder *, |
240 | struct intel_crtc_state *, | |
241 | struct drm_connector_state *); | |
7ae89233 | 242 | bool (*compute_config)(struct intel_encoder *, |
0a478c27 ML |
243 | struct intel_crtc_state *, |
244 | struct drm_connector_state *); | |
fd6bbda9 | 245 | void (*pre_pll_enable)(struct intel_encoder *, |
5f88a9c6 VS |
246 | const struct intel_crtc_state *, |
247 | const struct drm_connector_state *); | |
fd6bbda9 | 248 | void (*pre_enable)(struct intel_encoder *, |
5f88a9c6 VS |
249 | const struct intel_crtc_state *, |
250 | const struct drm_connector_state *); | |
fd6bbda9 | 251 | void (*enable)(struct intel_encoder *, |
5f88a9c6 VS |
252 | const struct intel_crtc_state *, |
253 | const struct drm_connector_state *); | |
fd6bbda9 | 254 | void (*disable)(struct intel_encoder *, |
5f88a9c6 VS |
255 | const struct intel_crtc_state *, |
256 | const struct drm_connector_state *); | |
fd6bbda9 | 257 | void (*post_disable)(struct intel_encoder *, |
5f88a9c6 VS |
258 | const struct intel_crtc_state *, |
259 | const struct drm_connector_state *); | |
fd6bbda9 | 260 | void (*post_pll_disable)(struct intel_encoder *, |
5f88a9c6 VS |
261 | const struct intel_crtc_state *, |
262 | const struct drm_connector_state *); | |
f0947c37 DV |
263 | /* Read out the current hw state of this connector, returning true if |
264 | * the encoder is active. If the encoder is enabled it also set the pipe | |
265 | * it is connected to in the pipe parameter. */ | |
266 | bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe); | |
045ac3b5 | 267 | /* Reconstructs the equivalent mode flags for the current hardware |
fdafa9e2 | 268 | * state. This must be called _after_ display->get_pipe_config has |
63000ef6 XZ |
269 | * pre-filled the pipe config. Note that intel_encoder->base.crtc must |
270 | * be set correctly before calling this function. */ | |
045ac3b5 | 271 | void (*get_config)(struct intel_encoder *, |
5cec258b | 272 | struct intel_crtc_state *pipe_config); |
62b69566 ACO |
273 | /* Returns a mask of power domains that need to be referenced as part |
274 | * of the hardware state readout code. */ | |
52528055 ID |
275 | u64 (*get_power_domains)(struct intel_encoder *encoder, |
276 | struct intel_crtc_state *crtc_state); | |
07f9cd0b ID |
277 | /* |
278 | * Called during system suspend after all pending requests for the | |
279 | * encoder are flushed (for example for DP AUX transactions) and | |
280 | * device interrupts are disabled. | |
281 | */ | |
282 | void (*suspend)(struct intel_encoder *); | |
f8aed700 | 283 | int crtc_mask; |
1d843f9d | 284 | enum hpd_pin hpd_pin; |
79f255a0 | 285 | enum intel_display_power_domain power_domain; |
f1a3acea PD |
286 | /* for communication with audio component; protected by av_mutex */ |
287 | const struct drm_connector *audio_connector; | |
79e53945 JB |
288 | }; |
289 | ||
1d508706 | 290 | struct intel_panel { |
dd06f90e | 291 | struct drm_display_mode *fixed_mode; |
ec9ed197 | 292 | struct drm_display_mode *downclock_mode; |
58c68779 JN |
293 | |
294 | /* backlight */ | |
295 | struct { | |
c91c9f32 | 296 | bool present; |
58c68779 | 297 | u32 level; |
6dda730e | 298 | u32 min; |
7bd688cd | 299 | u32 max; |
58c68779 | 300 | bool enabled; |
636baebf JN |
301 | bool combination_mode; /* gen 2/4 only */ |
302 | bool active_low_pwm; | |
32b421e7 | 303 | bool alternate_pwm_increment; /* lpt+ */ |
b029e66f SK |
304 | |
305 | /* PWM chip */ | |
022e4e52 SK |
306 | bool util_pin_active_low; /* bxt+ */ |
307 | u8 controller; /* bxt+ only */ | |
b029e66f SK |
308 | struct pwm_device *pwm; |
309 | ||
58c68779 | 310 | struct backlight_device *device; |
ab656bb9 | 311 | |
5507faeb JN |
312 | /* Connector and platform specific backlight functions */ |
313 | int (*setup)(struct intel_connector *connector, enum pipe pipe); | |
314 | uint32_t (*get)(struct intel_connector *connector); | |
7d025e08 ML |
315 | void (*set)(const struct drm_connector_state *conn_state, uint32_t level); |
316 | void (*disable)(const struct drm_connector_state *conn_state); | |
317 | void (*enable)(const struct intel_crtc_state *crtc_state, | |
318 | const struct drm_connector_state *conn_state); | |
5507faeb JN |
319 | uint32_t (*hz_to_pwm)(struct intel_connector *connector, |
320 | uint32_t hz); | |
321 | void (*power)(struct intel_connector *, bool enable); | |
322 | } backlight; | |
1d508706 JN |
323 | }; |
324 | ||
b6ca3eee VS |
325 | struct intel_digital_port; |
326 | ||
ee5e5e7a SP |
327 | /* |
328 | * This structure serves as a translation layer between the generic HDCP code | |
329 | * and the bus-specific code. What that means is that HDCP over HDMI differs | |
330 | * from HDCP over DP, so to account for these differences, we need to | |
331 | * communicate with the receiver through this shim. | |
332 | * | |
333 | * For completeness, the 2 buses differ in the following ways: | |
334 | * - DP AUX vs. DDC | |
335 | * HDCP registers on the receiver are set via DP AUX for DP, and | |
336 | * they are set via DDC for HDMI. | |
337 | * - Receiver register offsets | |
338 | * The offsets of the registers are different for DP vs. HDMI | |
339 | * - Receiver register masks/offsets | |
340 | * For instance, the ready bit for the KSV fifo is in a different | |
341 | * place on DP vs HDMI | |
342 | * - Receiver register names | |
343 | * Seriously. In the DP spec, the 16-bit register containing | |
344 | * downstream information is called BINFO, on HDMI it's called | |
345 | * BSTATUS. To confuse matters further, DP has a BSTATUS register | |
346 | * with a completely different definition. | |
347 | * - KSV FIFO | |
348 | * On HDMI, the ksv fifo is read all at once, whereas on DP it must | |
349 | * be read 3 keys at a time | |
350 | * - Aksv output | |
351 | * Since Aksv is hidden in hardware, there's different procedures | |
352 | * to send it over DP AUX vs DDC | |
353 | */ | |
354 | struct intel_hdcp_shim { | |
355 | /* Outputs the transmitter's An and Aksv values to the receiver. */ | |
356 | int (*write_an_aksv)(struct intel_digital_port *intel_dig_port, u8 *an); | |
357 | ||
358 | /* Reads the receiver's key selection vector */ | |
359 | int (*read_bksv)(struct intel_digital_port *intel_dig_port, u8 *bksv); | |
360 | ||
361 | /* | |
362 | * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The | |
363 | * definitions are the same in the respective specs, but the names are | |
364 | * different. Call it BSTATUS since that's the name the HDMI spec | |
365 | * uses and it was there first. | |
366 | */ | |
367 | int (*read_bstatus)(struct intel_digital_port *intel_dig_port, | |
368 | u8 *bstatus); | |
369 | ||
370 | /* Determines whether a repeater is present downstream */ | |
371 | int (*repeater_present)(struct intel_digital_port *intel_dig_port, | |
372 | bool *repeater_present); | |
373 | ||
374 | /* Reads the receiver's Ri' value */ | |
375 | int (*read_ri_prime)(struct intel_digital_port *intel_dig_port, u8 *ri); | |
376 | ||
377 | /* Determines if the receiver's KSV FIFO is ready for consumption */ | |
378 | int (*read_ksv_ready)(struct intel_digital_port *intel_dig_port, | |
379 | bool *ksv_ready); | |
380 | ||
381 | /* Reads the ksv fifo for num_downstream devices */ | |
382 | int (*read_ksv_fifo)(struct intel_digital_port *intel_dig_port, | |
383 | int num_downstream, u8 *ksv_fifo); | |
384 | ||
385 | /* Reads a 32-bit part of V' from the receiver */ | |
386 | int (*read_v_prime_part)(struct intel_digital_port *intel_dig_port, | |
387 | int i, u32 *part); | |
388 | ||
389 | /* Enables HDCP signalling on the port */ | |
390 | int (*toggle_signalling)(struct intel_digital_port *intel_dig_port, | |
391 | bool enable); | |
392 | ||
393 | /* Ensures the link is still protected */ | |
394 | bool (*check_link)(struct intel_digital_port *intel_dig_port); | |
791a98dd R |
395 | |
396 | /* Detects panel's hdcp capability. This is optional for HDMI. */ | |
397 | int (*hdcp_capable)(struct intel_digital_port *intel_dig_port, | |
398 | bool *hdcp_capable); | |
ee5e5e7a SP |
399 | }; |
400 | ||
d3dacc70 R |
401 | struct intel_hdcp { |
402 | const struct intel_hdcp_shim *shim; | |
403 | /* Mutex for hdcp state of the connector */ | |
404 | struct mutex mutex; | |
405 | u64 value; | |
406 | struct delayed_work check_work; | |
407 | struct work_struct prop_work; | |
408 | }; | |
409 | ||
5daa55eb ZW |
410 | struct intel_connector { |
411 | struct drm_connector base; | |
9a935856 DV |
412 | /* |
413 | * The fixed encoder this connector is connected to. | |
414 | */ | |
df0e9248 | 415 | struct intel_encoder *encoder; |
9a935856 | 416 | |
8e1b56a4 JN |
417 | /* ACPI device id for ACPI and driver cooperation */ |
418 | u32 acpi_device_id; | |
419 | ||
f0947c37 DV |
420 | /* Reads out the current hw, returning true if the connector is enabled |
421 | * and active (i.e. dpms ON state). */ | |
422 | bool (*get_hw_state)(struct intel_connector *); | |
1d508706 JN |
423 | |
424 | /* Panel info for eDP and LVDS */ | |
425 | struct intel_panel panel; | |
9cd300e0 JN |
426 | |
427 | /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */ | |
428 | struct edid *edid; | |
beb60608 | 429 | struct edid *detect_edid; |
821450c6 EE |
430 | |
431 | /* since POLL and HPD connectors may use the same HPD line keep the native | |
432 | state of connector->polled in case hotplug storm detection changes it */ | |
433 | u8 polled; | |
0e32b39c DA |
434 | |
435 | void *port; /* store this opaque as its illegal to dereference it */ | |
436 | ||
437 | struct intel_dp *mst_port; | |
9301397a MN |
438 | |
439 | /* Work struct to schedule a uevent on link train failure */ | |
440 | struct work_struct modeset_retry_work; | |
ee5e5e7a | 441 | |
d3dacc70 | 442 | struct intel_hdcp hdcp; |
5daa55eb ZW |
443 | }; |
444 | ||
11c1a9ec ML |
445 | struct intel_digital_connector_state { |
446 | struct drm_connector_state base; | |
447 | ||
448 | enum hdmi_force_audio force_audio; | |
449 | int broadcast_rgb; | |
450 | }; | |
451 | ||
452 | #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base) | |
453 | ||
9e2c8475 | 454 | struct dpll { |
80ad9206 VS |
455 | /* given values */ |
456 | int n; | |
457 | int m1, m2; | |
458 | int p1, p2; | |
459 | /* derived values */ | |
460 | int dot; | |
461 | int vco; | |
462 | int m; | |
463 | int p; | |
9e2c8475 | 464 | }; |
80ad9206 | 465 | |
de419ab6 ML |
466 | struct intel_atomic_state { |
467 | struct drm_atomic_state base; | |
468 | ||
bb0f4aab VS |
469 | struct { |
470 | /* | |
471 | * Logical state of cdclk (used for all scaling, watermark, | |
472 | * etc. calculations and checks). This is computed as if all | |
473 | * enabled crtcs were active. | |
474 | */ | |
475 | struct intel_cdclk_state logical; | |
476 | ||
477 | /* | |
478 | * Actual state of cdclk, can be different from the logical | |
479 | * state only when all crtc's are DPMS off. | |
480 | */ | |
481 | struct intel_cdclk_state actual; | |
385e40fe VS |
482 | |
483 | int force_min_cdclk; | |
484 | bool force_min_cdclk_changed; | |
90402bab VS |
485 | /* pipe to which cd2x update is synchronized */ |
486 | enum pipe pipe; | |
bb0f4aab | 487 | } cdclk; |
1a617b77 | 488 | |
565602d7 ML |
489 | bool dpll_set, modeset; |
490 | ||
8b4a7d05 MR |
491 | /* |
492 | * Does this transaction change the pipes that are active? This mask | |
493 | * tracks which CRTC's have changed their active state at the end of | |
494 | * the transaction (not counting the temporary disable during modesets). | |
495 | * This mask should only be non-zero when intel_state->modeset is true, | |
496 | * but the converse is not necessarily true; simply changing a mode may | |
497 | * not flip the final active status of any CRTC's | |
498 | */ | |
499 | unsigned int active_pipe_changes; | |
500 | ||
565602d7 | 501 | unsigned int active_crtcs; |
d305e061 VS |
502 | /* minimum acceptable cdclk for each pipe */ |
503 | int min_cdclk[I915_MAX_PIPES]; | |
53e9bf5e VS |
504 | /* minimum acceptable voltage level for each pipe */ |
505 | u8 min_voltage_level[I915_MAX_PIPES]; | |
565602d7 | 506 | |
2c42e535 | 507 | struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS]; |
ed4a6a7c MR |
508 | |
509 | /* | |
510 | * Current watermarks can't be trusted during hardware readout, so | |
511 | * don't bother calculating intermediate watermarks. | |
512 | */ | |
513 | bool skip_intermediate_wm; | |
98d39494 | 514 | |
60548c55 CW |
515 | bool rps_interactive; |
516 | ||
98d39494 | 517 | /* Gen9+ only */ |
60f8e873 | 518 | struct skl_ddb_values wm_results; |
c004a90b CW |
519 | |
520 | struct i915_sw_fence commit_ready; | |
eb955eee CW |
521 | |
522 | struct llist_node freed; | |
de419ab6 ML |
523 | }; |
524 | ||
eeca778a | 525 | struct intel_plane_state { |
2b875c22 | 526 | struct drm_plane_state base; |
f5929c53 | 527 | struct i915_ggtt_view view; |
be1e3415 | 528 | struct i915_vma *vma; |
5935485f CW |
529 | unsigned long flags; |
530 | #define PLANE_HAS_FENCE BIT(0) | |
32b7eeec | 531 | |
b63a16f6 VS |
532 | struct { |
533 | u32 offset; | |
df79cf44 VS |
534 | /* |
535 | * Plane stride in: | |
536 | * bytes for 0/180 degree rotation | |
537 | * pixels for 90/270 degree rotation | |
538 | */ | |
539 | u32 stride; | |
b63a16f6 | 540 | int x, y; |
c11ada07 | 541 | } color_plane[2]; |
b63a16f6 | 542 | |
a0864d59 VS |
543 | /* plane control register */ |
544 | u32 ctl; | |
545 | ||
4036c78c JA |
546 | /* plane color control register */ |
547 | u32 color_ctl; | |
548 | ||
be41e336 CK |
549 | /* |
550 | * scaler_id | |
551 | * = -1 : not using a scaler | |
552 | * >= 0 : using a scalers | |
553 | * | |
554 | * plane requiring a scaler: | |
555 | * - During check_plane, its bit is set in | |
556 | * crtc_state->scaler_state.scaler_users by calling helper function | |
86adf9d7 | 557 | * update_scaler_plane. |
be41e336 CK |
558 | * - scaler_id indicates the scaler it got assigned. |
559 | * | |
560 | * plane doesn't require a scaler: | |
561 | * - this can happen when scaling is no more required or plane simply | |
562 | * got disabled. | |
563 | * - During check_plane, corresponding bit is reset in | |
564 | * crtc_state->scaler_state.scaler_users by calling helper function | |
86adf9d7 | 565 | * update_scaler_plane. |
be41e336 CK |
566 | */ |
567 | int scaler_id; | |
818ed961 | 568 | |
1ab554b0 ML |
569 | /* |
570 | * linked_plane: | |
571 | * | |
572 | * ICL planar formats require 2 planes that are updated as pairs. | |
573 | * This member is used to make sure the other plane is also updated | |
574 | * when required, and for update_slave() to find the correct | |
575 | * plane_state to pass as argument. | |
576 | */ | |
577 | struct intel_plane *linked_plane; | |
578 | ||
579 | /* | |
580 | * slave: | |
581 | * If set don't update use the linked plane's state for updating | |
582 | * this plane during atomic commit with the update_slave() callback. | |
583 | * | |
584 | * It's also used by the watermark code to ignore wm calculations on | |
585 | * this plane. They're calculated by the linked plane's wm code. | |
586 | */ | |
587 | u32 slave; | |
588 | ||
818ed961 | 589 | struct drm_intel_sprite_colorkey ckey; |
eeca778a GP |
590 | }; |
591 | ||
5724dbd1 | 592 | struct intel_initial_plane_config { |
2d14030b | 593 | struct intel_framebuffer *fb; |
49af449b | 594 | unsigned int tiling; |
46f297fb JB |
595 | int size; |
596 | u32 base; | |
f43348a3 | 597 | u8 rotation; |
46f297fb JB |
598 | }; |
599 | ||
be41e336 CK |
600 | #define SKL_MIN_SRC_W 8 |
601 | #define SKL_MAX_SRC_W 4096 | |
602 | #define SKL_MIN_SRC_H 8 | |
6156a456 | 603 | #define SKL_MAX_SRC_H 4096 |
be41e336 CK |
604 | #define SKL_MIN_DST_W 8 |
605 | #define SKL_MAX_DST_W 4096 | |
606 | #define SKL_MIN_DST_H 8 | |
6156a456 | 607 | #define SKL_MAX_DST_H 4096 |
323301af NM |
608 | #define ICL_MAX_SRC_W 5120 |
609 | #define ICL_MAX_SRC_H 4096 | |
610 | #define ICL_MAX_DST_W 5120 | |
611 | #define ICL_MAX_DST_H 4096 | |
77224cd5 CK |
612 | #define SKL_MIN_YUV_420_SRC_W 16 |
613 | #define SKL_MIN_YUV_420_SRC_H 16 | |
be41e336 CK |
614 | |
615 | struct intel_scaler { | |
be41e336 CK |
616 | int in_use; |
617 | uint32_t mode; | |
618 | }; | |
619 | ||
620 | struct intel_crtc_scaler_state { | |
621 | #define SKL_NUM_SCALERS 2 | |
622 | struct intel_scaler scalers[SKL_NUM_SCALERS]; | |
623 | ||
624 | /* | |
625 | * scaler_users: keeps track of users requesting scalers on this crtc. | |
626 | * | |
627 | * If a bit is set, a user is using a scaler. | |
628 | * Here user can be a plane or crtc as defined below: | |
629 | * bits 0-30 - plane (bit position is index from drm_plane_index) | |
630 | * bit 31 - crtc | |
631 | * | |
632 | * Instead of creating a new index to cover planes and crtc, using | |
633 | * existing drm_plane_index for planes which is well less than 31 | |
634 | * planes and bit 31 for crtc. This should be fine to cover all | |
635 | * our platforms. | |
636 | * | |
637 | * intel_atomic_setup_scalers will setup available scalers to users | |
638 | * requesting scalers. It will gracefully fail if request exceeds | |
639 | * avilability. | |
640 | */ | |
641 | #define SKL_CRTC_INDEX 31 | |
642 | unsigned scaler_users; | |
643 | ||
644 | /* scaler used by crtc for panel fitting purpose */ | |
645 | int scaler_id; | |
646 | }; | |
647 | ||
1ed51de9 DV |
648 | /* drm_mode->private_flags */ |
649 | #define I915_MODE_FLAG_INHERITED 1 | |
aec0246f US |
650 | /* Flag to get scanline using frame time stamps */ |
651 | #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1) | |
1ed51de9 | 652 | |
4e0963c7 MR |
653 | struct intel_pipe_wm { |
654 | struct intel_wm_level wm[5]; | |
655 | uint32_t linetime; | |
656 | bool fbc_wm_enabled; | |
657 | bool pipe_enabled; | |
658 | bool sprites_enabled; | |
659 | bool sprites_scaled; | |
660 | }; | |
661 | ||
a62163e9 | 662 | struct skl_plane_wm { |
4e0963c7 | 663 | struct skl_wm_level wm[8]; |
942aa2d0 | 664 | struct skl_wm_level uv_wm[8]; |
4e0963c7 | 665 | struct skl_wm_level trans_wm; |
b879d58f | 666 | bool is_planar; |
a62163e9 L |
667 | }; |
668 | ||
669 | struct skl_pipe_wm { | |
670 | struct skl_plane_wm planes[I915_MAX_PLANES]; | |
4e0963c7 MR |
671 | uint32_t linetime; |
672 | }; | |
673 | ||
855c79f5 VS |
674 | enum vlv_wm_level { |
675 | VLV_WM_LEVEL_PM2, | |
676 | VLV_WM_LEVEL_PM5, | |
677 | VLV_WM_LEVEL_DDR_DVFS, | |
678 | NUM_VLV_WM_LEVELS, | |
679 | }; | |
680 | ||
681 | struct vlv_wm_state { | |
114d7dc0 VS |
682 | struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS]; |
683 | struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS]; | |
855c79f5 | 684 | uint8_t num_levels; |
855c79f5 VS |
685 | bool cxsr; |
686 | }; | |
687 | ||
814e7f0b VS |
688 | struct vlv_fifo_state { |
689 | u16 plane[I915_MAX_PLANES]; | |
690 | }; | |
691 | ||
04548cba VS |
692 | enum g4x_wm_level { |
693 | G4X_WM_LEVEL_NORMAL, | |
694 | G4X_WM_LEVEL_SR, | |
695 | G4X_WM_LEVEL_HPLL, | |
696 | NUM_G4X_WM_LEVELS, | |
697 | }; | |
698 | ||
699 | struct g4x_wm_state { | |
700 | struct g4x_pipe_wm wm; | |
701 | struct g4x_sr_wm sr; | |
702 | struct g4x_sr_wm hpll; | |
703 | bool cxsr; | |
704 | bool hpll_en; | |
705 | bool fbc_en; | |
706 | }; | |
707 | ||
e8f1f02e MR |
708 | struct intel_crtc_wm_state { |
709 | union { | |
710 | struct { | |
711 | /* | |
712 | * Intermediate watermarks; these can be | |
713 | * programmed immediately since they satisfy | |
714 | * both the current configuration we're | |
715 | * switching away from and the new | |
716 | * configuration we're switching to. | |
717 | */ | |
718 | struct intel_pipe_wm intermediate; | |
719 | ||
720 | /* | |
721 | * Optimal watermarks, programmed post-vblank | |
722 | * when this state is committed. | |
723 | */ | |
724 | struct intel_pipe_wm optimal; | |
725 | } ilk; | |
726 | ||
727 | struct { | |
728 | /* gen9+ only needs 1-step wm programming */ | |
729 | struct skl_pipe_wm optimal; | |
ce0ba283 | 730 | struct skl_ddb_entry ddb; |
ff43bc37 VS |
731 | struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES]; |
732 | struct skl_ddb_entry plane_ddb_uv[I915_MAX_PLANES]; | |
e8f1f02e | 733 | } skl; |
855c79f5 VS |
734 | |
735 | struct { | |
5012e604 | 736 | /* "raw" watermarks (not inverted) */ |
114d7dc0 | 737 | struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS]; |
4841da51 VS |
738 | /* intermediate watermarks (inverted) */ |
739 | struct vlv_wm_state intermediate; | |
855c79f5 VS |
740 | /* optimal watermarks (inverted) */ |
741 | struct vlv_wm_state optimal; | |
814e7f0b VS |
742 | /* display FIFO split */ |
743 | struct vlv_fifo_state fifo_state; | |
855c79f5 | 744 | } vlv; |
04548cba VS |
745 | |
746 | struct { | |
747 | /* "raw" watermarks */ | |
748 | struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS]; | |
749 | /* intermediate watermarks */ | |
750 | struct g4x_wm_state intermediate; | |
751 | /* optimal watermarks */ | |
752 | struct g4x_wm_state optimal; | |
753 | } g4x; | |
e8f1f02e MR |
754 | }; |
755 | ||
756 | /* | |
757 | * Platforms with two-step watermark programming will need to | |
758 | * update watermark programming post-vblank to switch from the | |
759 | * safe intermediate watermarks to the optimal final | |
760 | * watermarks. | |
761 | */ | |
762 | bool need_postvbl_update; | |
763 | }; | |
764 | ||
d9facae6 SS |
765 | enum intel_output_format { |
766 | INTEL_OUTPUT_FORMAT_INVALID, | |
767 | INTEL_OUTPUT_FORMAT_RGB, | |
33b7f3ee | 768 | INTEL_OUTPUT_FORMAT_YCBCR420, |
8c79f844 | 769 | INTEL_OUTPUT_FORMAT_YCBCR444, |
d9facae6 SS |
770 | }; |
771 | ||
5cec258b | 772 | struct intel_crtc_state { |
2d112de7 ACO |
773 | struct drm_crtc_state base; |
774 | ||
bb760063 DV |
775 | /** |
776 | * quirks - bitfield with hw state readout quirks | |
777 | * | |
778 | * For various reasons the hw state readout code might not be able to | |
779 | * completely faithfully read out the current state. These cases are | |
780 | * tracked with quirk flags so that fastboot and state checker can act | |
781 | * accordingly. | |
782 | */ | |
9953599b | 783 | #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */ |
bb760063 DV |
784 | unsigned long quirks; |
785 | ||
cd202f69 | 786 | unsigned fb_bits; /* framebuffers to flip */ |
ab1d3a0e ML |
787 | bool update_pipe; /* can a fast modeset be performed? */ |
788 | bool disable_cxsr; | |
caed361d | 789 | bool update_wm_pre, update_wm_post; /* watermarks are updated */ |
e8861675 | 790 | bool fb_changed; /* fb on any of the planes is changed */ |
236c48e6 | 791 | bool fifo_changed; /* FIFO split is changed */ |
bfd16b2a | 792 | |
37327abd VS |
793 | /* Pipe source size (ie. panel fitter input size) |
794 | * All planes will be positioned inside this space, | |
795 | * and get clipped at the edges. */ | |
796 | int pipe_src_w, pipe_src_h; | |
797 | ||
a7d1b3f4 VS |
798 | /* |
799 | * Pipe pixel rate, adjusted for | |
800 | * panel fitter/pipe scaler downscaling. | |
801 | */ | |
802 | unsigned int pixel_rate; | |
803 | ||
5bfe2ac0 DV |
804 | /* Whether to set up the PCH/FDI. Note that we never allow sharing |
805 | * between pch encoders and cpu encoders. */ | |
806 | bool has_pch_encoder; | |
50f3b016 | 807 | |
e43823ec JB |
808 | /* Are we sending infoframes on the attached port */ |
809 | bool has_infoframe; | |
810 | ||
3b117c8f | 811 | /* CPU Transcoder for the pipe. Currently this can only differ from the |
4d1de975 JN |
812 | * pipe on Haswell and later (where we have a special eDP transcoder) |
813 | * and Broxton (where we have special DSI transcoders). */ | |
3b117c8f DV |
814 | enum transcoder cpu_transcoder; |
815 | ||
50f3b016 DV |
816 | /* |
817 | * Use reduced/limited/broadcast rbg range, compressing from the full | |
818 | * range fed into the crtcs. | |
819 | */ | |
820 | bool limited_color_range; | |
821 | ||
253c84c8 VS |
822 | /* Bitmask of encoder types (enum intel_output_type) |
823 | * driven by the pipe. | |
824 | */ | |
825 | unsigned int output_types; | |
826 | ||
6897b4b5 DV |
827 | /* Whether we should send NULL infoframes. Required for audio. */ |
828 | bool has_hdmi_sink; | |
829 | ||
9ed109a7 DV |
830 | /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or |
831 | * has_dp_encoder is set. */ | |
832 | bool has_audio; | |
833 | ||
d8b32247 DV |
834 | /* |
835 | * Enable dithering, used when the selected pipe bpp doesn't match the | |
836 | * plane bpp. | |
837 | */ | |
965e0c48 | 838 | bool dither; |
f47709a9 | 839 | |
611032bf MN |
840 | /* |
841 | * Dither gets enabled for 18bpp which causes CRC mismatch errors for | |
842 | * compliance video pattern tests. | |
843 | * Disable dither only if it is a compliance test request for | |
844 | * 18bpp. | |
845 | */ | |
846 | bool dither_force_disable; | |
847 | ||
f47709a9 DV |
848 | /* Controls for the clock computation, to override various stages. */ |
849 | bool clock_set; | |
850 | ||
09ede541 DV |
851 | /* SDVO TV has a bunch of special case. To make multifunction encoders |
852 | * work correctly, we need to track this at runtime.*/ | |
853 | bool sdvo_tv_clock; | |
854 | ||
e29c22c0 DV |
855 | /* |
856 | * crtc bandwidth limit, don't increase pipe bpp or clock if not really | |
857 | * required. This is set in the 2nd loop of calling encoder's | |
858 | * ->compute_config if the first pick doesn't work out. | |
859 | */ | |
860 | bool bw_constrained; | |
861 | ||
f47709a9 DV |
862 | /* Settings for the intel dpll used on pretty much everything but |
863 | * haswell. */ | |
80ad9206 | 864 | struct dpll dpll; |
f47709a9 | 865 | |
8106ddbd ACO |
866 | /* Selected dpll when shared or NULL. */ |
867 | struct intel_shared_dpll *shared_dpll; | |
a43f6e0f | 868 | |
66e985c0 DV |
869 | /* Actual register state of the dpll, for shared dpll cross-checking. */ |
870 | struct intel_dpll_hw_state dpll_hw_state; | |
871 | ||
47eacbab VS |
872 | /* DSI PLL registers */ |
873 | struct { | |
874 | u32 ctrl, div; | |
875 | } dsi_pll; | |
876 | ||
965e0c48 | 877 | int pipe_bpp; |
6cf86a5e | 878 | struct intel_link_m_n dp_m_n; |
ff9a6750 | 879 | |
439d7ac0 PB |
880 | /* m2_n2 for eDP downclock */ |
881 | struct intel_link_m_n dp_m2_n2; | |
f769cd24 | 882 | bool has_drrs; |
439d7ac0 | 883 | |
4d90f2d5 VS |
884 | bool has_psr; |
885 | bool has_psr2; | |
886 | ||
ff9a6750 DV |
887 | /* |
888 | * Frequence the dpll for the port should run at. Differs from the | |
3c52f4eb VS |
889 | * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also |
890 | * already multiplied by pixel_multiplier. | |
df92b1e6 | 891 | */ |
ff9a6750 DV |
892 | int port_clock; |
893 | ||
6cc5f341 DV |
894 | /* Used by SDVO (and if we ever fix it, HDMI). */ |
895 | unsigned pixel_multiplier; | |
2dd24552 | 896 | |
90a6b7b0 VS |
897 | uint8_t lane_count; |
898 | ||
95a7a2ae ID |
899 | /* |
900 | * Used by platforms having DP/HDMI PHY with programmable lane | |
901 | * latency optimization. | |
902 | */ | |
903 | uint8_t lane_lat_optim_mask; | |
904 | ||
53e9bf5e VS |
905 | /* minimum acceptable voltage level */ |
906 | u8 min_voltage_level; | |
907 | ||
2dd24552 | 908 | /* Panel fitter controls for gen2-gen4 + VLV */ |
b074cec8 JB |
909 | struct { |
910 | u32 control; | |
911 | u32 pgm_ratios; | |
68fc8742 | 912 | u32 lvds_border_bits; |
b074cec8 JB |
913 | } gmch_pfit; |
914 | ||
915 | /* Panel fitter placement and size for Ironlake+ */ | |
916 | struct { | |
917 | u32 pos; | |
918 | u32 size; | |
fd4daa9c | 919 | bool enabled; |
fabf6e51 | 920 | bool force_thru; |
b074cec8 | 921 | } pch_pfit; |
33d29b14 | 922 | |
ca3a0ff8 | 923 | /* FDI configuration, only valid if has_pch_encoder is set. */ |
33d29b14 | 924 | int fdi_lanes; |
ca3a0ff8 | 925 | struct intel_link_m_n fdi_m_n; |
42db64ef PZ |
926 | |
927 | bool ips_enabled; | |
6e644626 | 928 | bool ips_force_disable; |
cf532bb2 | 929 | |
f51be2e0 PZ |
930 | bool enable_fbc; |
931 | ||
cf532bb2 | 932 | bool double_wide; |
0e32b39c | 933 | |
0e32b39c | 934 | int pbn; |
be41e336 CK |
935 | |
936 | struct intel_crtc_scaler_state scaler_state; | |
99d736a2 ML |
937 | |
938 | /* w/a for waiting 2 vblanks during crtc enable */ | |
939 | enum pipe hsw_workaround_pipe; | |
d21fbe87 MR |
940 | |
941 | /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */ | |
942 | bool disable_lp_wm; | |
4e0963c7 | 943 | |
e8f1f02e | 944 | struct intel_crtc_wm_state wm; |
05dc698c LL |
945 | |
946 | /* Gamma mode programmed on the pipe */ | |
947 | uint32_t gamma_mode; | |
e9728bd8 VS |
948 | |
949 | /* bitmask of visible planes (enum plane_id) */ | |
950 | u8 active_planes; | |
8e021151 | 951 | u8 nv12_planes; |
15953637 | 952 | |
afbd8a72 VS |
953 | /* bitmask of planes that will be updated during the commit */ |
954 | u8 update_planes; | |
955 | ||
15953637 SS |
956 | /* HDMI scrambling status */ |
957 | bool hdmi_scrambling; | |
958 | ||
959 | /* HDMI High TMDS char rate ratio */ | |
960 | bool hdmi_high_tmds_clock_ratio; | |
60436fd4 | 961 | |
d9facae6 SS |
962 | /* Output format RGB/YCBCR etc */ |
963 | enum intel_output_format output_format; | |
668b6c17 SS |
964 | |
965 | /* Output down scaling is done in LSPCON device */ | |
966 | bool lspcon_downsampling; | |
7b610f1f MN |
967 | |
968 | /* Display Stream compression state */ | |
969 | struct { | |
970 | bool compression_enable; | |
971 | bool dsc_split; | |
972 | u16 compressed_bpp; | |
973 | u8 slice_count; | |
974 | } dsc_params; | |
975 | struct drm_dsc_config dp_dsc_cfg; | |
240999cf AS |
976 | |
977 | /* Forward Error correction State */ | |
978 | bool fec_enable; | |
b8cecdf5 DV |
979 | }; |
980 | ||
79e53945 JB |
981 | struct intel_crtc { |
982 | struct drm_crtc base; | |
80824003 | 983 | enum pipe pipe; |
08a48469 DV |
984 | /* |
985 | * Whether the crtc and the connected output pipeline is active. Implies | |
986 | * that crtc->enabled is set, i.e. the current mode configuration has | |
987 | * some outputs connected to this crtc. | |
08a48469 DV |
988 | */ |
989 | bool active; | |
d97d7b48 | 990 | u8 plane_ids_mask; |
d8fc70b7 | 991 | unsigned long long enabled_power_domains; |
02e792fb | 992 | struct intel_overlay *overlay; |
cda4b7d3 | 993 | |
6e3c9717 | 994 | struct intel_crtc_state *config; |
b8cecdf5 | 995 | |
8af29b0c CW |
996 | /* global reset count when the last flip was submitted */ |
997 | unsigned int reset_count; | |
5a21b665 | 998 | |
8664281b PZ |
999 | /* Access to these should be protected by dev_priv->irq_lock. */ |
1000 | bool cpu_fifo_underrun_disabled; | |
1001 | bool pch_fifo_underrun_disabled; | |
0b2ae6d7 VS |
1002 | |
1003 | /* per-pipe watermark state */ | |
1004 | struct { | |
1005 | /* watermarks currently being used */ | |
4e0963c7 MR |
1006 | union { |
1007 | struct intel_pipe_wm ilk; | |
7eb4941f | 1008 | struct vlv_wm_state vlv; |
04548cba | 1009 | struct g4x_wm_state g4x; |
4e0963c7 | 1010 | } active; |
0b2ae6d7 | 1011 | } wm; |
8d7849db | 1012 | |
80715b2f | 1013 | int scanline_offset; |
32b7eeec | 1014 | |
eb120ef6 JB |
1015 | struct { |
1016 | unsigned start_vbl_count; | |
1017 | ktime_t start_vbl_time; | |
1018 | int min_vbl, max_vbl; | |
1019 | int scanline_start; | |
1020 | } debug; | |
85a62bf9 | 1021 | |
be41e336 CK |
1022 | /* scalers available on this crtc */ |
1023 | int num_scalers; | |
79e53945 JB |
1024 | }; |
1025 | ||
b840d907 JB |
1026 | struct intel_plane { |
1027 | struct drm_plane base; | |
ed15030d | 1028 | enum i9xx_plane_id i9xx_plane; |
b14e5848 | 1029 | enum plane_id id; |
b840d907 | 1030 | enum pipe pipe; |
cf1805e6 | 1031 | bool has_fbc; |
a38189c5 | 1032 | bool has_ccs; |
a9ff8714 | 1033 | uint32_t frontbuffer_bit; |
526682e9 | 1034 | |
cd5dcbf1 VS |
1035 | struct { |
1036 | u32 base, cntl, size; | |
1037 | } cursor; | |
1038 | ||
8e7d688b MR |
1039 | /* |
1040 | * NOTE: Do not place new plane state fields here (e.g., when adding | |
1041 | * new plane properties). New runtime state should now be placed in | |
2fde1391 | 1042 | * the intel_plane_state structure and accessed via plane_state. |
8e7d688b MR |
1043 | */ |
1044 | ||
ddd5713d VS |
1045 | unsigned int (*max_stride)(struct intel_plane *plane, |
1046 | u32 pixel_format, u64 modifier, | |
1047 | unsigned int rotation); | |
282dbf9b | 1048 | void (*update_plane)(struct intel_plane *plane, |
2fde1391 ML |
1049 | const struct intel_crtc_state *crtc_state, |
1050 | const struct intel_plane_state *plane_state); | |
1ab554b0 ML |
1051 | void (*update_slave)(struct intel_plane *plane, |
1052 | const struct intel_crtc_state *crtc_state, | |
1053 | const struct intel_plane_state *plane_state); | |
282dbf9b | 1054 | void (*disable_plane)(struct intel_plane *plane, |
0dd14be3 | 1055 | const struct intel_crtc_state *crtc_state); |
eade6c89 | 1056 | bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe); |
eb0f5044 VS |
1057 | int (*check_plane)(struct intel_crtc_state *crtc_state, |
1058 | struct intel_plane_state *plane_state); | |
b840d907 JB |
1059 | }; |
1060 | ||
b445e3b0 | 1061 | struct intel_watermark_params { |
ae9400ca TU |
1062 | u16 fifo_size; |
1063 | u16 max_wm; | |
1064 | u8 default_wm; | |
1065 | u8 guard_size; | |
1066 | u8 cacheline_size; | |
b445e3b0 ED |
1067 | }; |
1068 | ||
1069 | struct cxsr_latency { | |
c13fb778 TU |
1070 | bool is_desktop : 1; |
1071 | bool is_ddr3 : 1; | |
44a655ca TU |
1072 | u16 fsb_freq; |
1073 | u16 mem_freq; | |
1074 | u16 display_sr; | |
1075 | u16 display_hpll_disable; | |
1076 | u16 cursor_sr; | |
1077 | u16 cursor_hpll_disable; | |
b445e3b0 ED |
1078 | }; |
1079 | ||
de419ab6 | 1080 | #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base) |
79e53945 | 1081 | #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) |
10f81c19 | 1082 | #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base) |
5daa55eb | 1083 | #define to_intel_connector(x) container_of(x, struct intel_connector, base) |
4ef69c7a | 1084 | #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) |
79e53945 | 1085 | #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) |
b840d907 | 1086 | #define to_intel_plane(x) container_of(x, struct intel_plane, base) |
ea2c67bb | 1087 | #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base) |
a268bcd7 | 1088 | #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL) |
79e53945 | 1089 | |
f5bbfca3 | 1090 | struct intel_hdmi { |
f0f59a00 | 1091 | i915_reg_t hdmi_reg; |
f5bbfca3 | 1092 | int ddc_bus; |
b1ba124d VS |
1093 | struct { |
1094 | enum drm_dp_dual_mode_type type; | |
1095 | int max_tmds_clock; | |
1096 | } dp_dual_mode; | |
f5bbfca3 ED |
1097 | bool has_hdmi_sink; |
1098 | bool has_audio; | |
abedc077 | 1099 | bool rgb_quant_range_selectable; |
d8b4c43a | 1100 | struct intel_connector *attached_connector; |
9c229127 | 1101 | struct cec_notifier *cec_notifier; |
f5bbfca3 ED |
1102 | }; |
1103 | ||
0e32b39c | 1104 | struct intel_dp_mst_encoder; |
b091cd92 | 1105 | #define DP_MAX_DOWNSTREAM_PORTS 0x10 |
54d63ca6 | 1106 | |
fe3cd48d R |
1107 | /* |
1108 | * enum link_m_n_set: | |
1109 | * When platform provides two set of M_N registers for dp, we can | |
1110 | * program them and switch between them incase of DRRS. | |
1111 | * But When only one such register is provided, we have to program the | |
1112 | * required divider value on that registers itself based on the DRRS state. | |
1113 | * | |
1114 | * M1_N1 : Program dp_m_n on M1_N1 registers | |
1115 | * dp_m2_n2 on M2_N2 registers (If supported) | |
1116 | * | |
1117 | * M2_N2 : Program dp_m2_n2 on M1_N1 registers | |
1118 | * M2_N2 registers are not supported | |
1119 | */ | |
1120 | ||
1121 | enum link_m_n_set { | |
1122 | /* Sets the m1_n1 and m2_n2 */ | |
1123 | M1_N1 = 0, | |
1124 | M2_N2 | |
1125 | }; | |
1126 | ||
c1617abc MN |
1127 | struct intel_dp_compliance_data { |
1128 | unsigned long edid; | |
611032bf MN |
1129 | uint8_t video_pattern; |
1130 | uint16_t hdisplay, vdisplay; | |
1131 | uint8_t bpc; | |
c1617abc MN |
1132 | }; |
1133 | ||
1134 | struct intel_dp_compliance { | |
1135 | unsigned long test_type; | |
1136 | struct intel_dp_compliance_data test_data; | |
1137 | bool test_active; | |
da15f7cb MN |
1138 | int test_link_rate; |
1139 | u8 test_lane_count; | |
c1617abc MN |
1140 | }; |
1141 | ||
54d63ca6 | 1142 | struct intel_dp { |
f0f59a00 | 1143 | i915_reg_t output_reg; |
54d63ca6 | 1144 | uint32_t DP; |
901c2daf VS |
1145 | int link_rate; |
1146 | uint8_t lane_count; | |
30d9aa42 | 1147 | uint8_t sink_count; |
64ee2fd2 | 1148 | bool link_mst; |
edb2e530 | 1149 | bool link_trained; |
54d63ca6 | 1150 | bool has_audio; |
d7e8ef02 | 1151 | bool reset_link_params; |
54d63ca6 | 1152 | uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; |
2293bb5c | 1153 | uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; |
b091cd92 | 1154 | uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; |
86ee27b5 | 1155 | uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]; |
93ac092f | 1156 | u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]; |
08cadae8 | 1157 | u8 fec_capable; |
55cfc580 JN |
1158 | /* source rates */ |
1159 | int num_source_rates; | |
1160 | const int *source_rates; | |
68f357cb JN |
1161 | /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */ |
1162 | int num_sink_rates; | |
94ca719e | 1163 | int sink_rates[DP_MAX_SUPPORTED_RATES]; |
68f357cb | 1164 | bool use_rate_select; |
975ee5fc JN |
1165 | /* intersection of source and sink rates */ |
1166 | int num_common_rates; | |
1167 | int common_rates[DP_MAX_SUPPORTED_RATES]; | |
e6c0c64a JN |
1168 | /* Max lane count for the current link */ |
1169 | int max_link_lane_count; | |
1170 | /* Max rate for the current link */ | |
1171 | int max_link_rate; | |
7b3fc170 | 1172 | /* sink or branch descriptor */ |
84c36753 | 1173 | struct drm_dp_desc desc; |
9d1a1031 | 1174 | struct drm_dp_aux aux; |
54d63ca6 SK |
1175 | uint8_t train_set[4]; |
1176 | int panel_power_up_delay; | |
1177 | int panel_power_down_delay; | |
1178 | int panel_power_cycle_delay; | |
1179 | int backlight_on_delay; | |
1180 | int backlight_off_delay; | |
54d63ca6 SK |
1181 | struct delayed_work panel_vdd_work; |
1182 | bool want_panel_vdd; | |
dce56b3c PZ |
1183 | unsigned long last_power_on; |
1184 | unsigned long last_backlight_off; | |
d28d4731 | 1185 | ktime_t panel_power_off_time; |
5d42f82a | 1186 | |
01527b31 CT |
1187 | struct notifier_block edp_notifier; |
1188 | ||
a4a5d2f8 VS |
1189 | /* |
1190 | * Pipe whose power sequencer is currently locked into | |
1191 | * this port. Only relevant on VLV/CHV. | |
1192 | */ | |
1193 | enum pipe pps_pipe; | |
9f2bdb00 VS |
1194 | /* |
1195 | * Pipe currently driving the port. Used for preventing | |
1196 | * the use of the PPS for any pipe currentrly driving | |
1197 | * external DP as that will mess things up on VLV. | |
1198 | */ | |
1199 | enum pipe active_pipe; | |
78597996 ID |
1200 | /* |
1201 | * Set if the sequencer may be reset due to a power transition, | |
1202 | * requiring a reinitialization. Only relevant on BXT. | |
1203 | */ | |
1204 | bool pps_reset; | |
36b5f425 | 1205 | struct edp_power_seq pps_delays; |
a4a5d2f8 | 1206 | |
0e32b39c DA |
1207 | bool can_mst; /* this port supports mst */ |
1208 | bool is_mst; | |
19e0b4ca | 1209 | int active_mst_links; |
0e32b39c | 1210 | /* connector directly attached - won't be use for modeset in mst world */ |
dd06f90e | 1211 | struct intel_connector *attached_connector; |
ec5b01dd | 1212 | |
0e32b39c DA |
1213 | /* mst connector list */ |
1214 | struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES]; | |
1215 | struct drm_dp_mst_topology_mgr mst_mgr; | |
1216 | ||
ec5b01dd | 1217 | uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index); |
153b1100 DL |
1218 | /* |
1219 | * This function returns the value we have to program the AUX_CTL | |
1220 | * register with to kick off an AUX transaction. | |
1221 | */ | |
1222 | uint32_t (*get_aux_send_ctl)(struct intel_dp *dp, | |
153b1100 DL |
1223 | int send_bytes, |
1224 | uint32_t aux_clock_divider); | |
ad64217b | 1225 | |
4904fa66 VS |
1226 | i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp); |
1227 | i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index); | |
1228 | ||
ad64217b ACO |
1229 | /* This is called before a link training is starterd */ |
1230 | void (*prepare_link_retrain)(struct intel_dp *intel_dp); | |
1231 | ||
c5d5ab7a | 1232 | /* Displayport compliance testing */ |
c1617abc | 1233 | struct intel_dp_compliance compliance; |
54d63ca6 SK |
1234 | }; |
1235 | ||
96e35598 SS |
1236 | enum lspcon_vendor { |
1237 | LSPCON_VENDOR_MCA, | |
1238 | LSPCON_VENDOR_PARADE | |
1239 | }; | |
1240 | ||
dbe9e61b SS |
1241 | struct intel_lspcon { |
1242 | bool active; | |
1243 | enum drm_lspcon_mode mode; | |
96e35598 | 1244 | enum lspcon_vendor vendor; |
dbe9e61b SS |
1245 | }; |
1246 | ||
da63a9f2 PZ |
1247 | struct intel_digital_port { |
1248 | struct intel_encoder base; | |
bcf53de4 | 1249 | u32 saved_port_bits; |
da63a9f2 PZ |
1250 | struct intel_dp dp; |
1251 | struct intel_hdmi hdmi; | |
dbe9e61b | 1252 | struct intel_lspcon lspcon; |
b2c5c181 | 1253 | enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool); |
b0b33846 | 1254 | bool release_cl2_override; |
ccb1a831 | 1255 | uint8_t max_lanes; |
563d22a0 ID |
1256 | /* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */ |
1257 | enum aux_ch aux_ch; | |
62b69566 | 1258 | enum intel_display_power_domain ddi_io_power_domain; |
6075546f | 1259 | enum tc_port_type tc_type; |
f99be1b3 | 1260 | |
790ea70c | 1261 | void (*write_infoframe)(struct intel_encoder *encoder, |
f99be1b3 | 1262 | const struct intel_crtc_state *crtc_state, |
1d776538 | 1263 | unsigned int type, |
f99be1b3 | 1264 | const void *frame, ssize_t len); |
790ea70c | 1265 | void (*set_infoframes)(struct intel_encoder *encoder, |
f99be1b3 VS |
1266 | bool enable, |
1267 | const struct intel_crtc_state *crtc_state, | |
1268 | const struct drm_connector_state *conn_state); | |
790ea70c | 1269 | bool (*infoframe_enabled)(struct intel_encoder *encoder, |
f99be1b3 | 1270 | const struct intel_crtc_state *pipe_config); |
da63a9f2 PZ |
1271 | }; |
1272 | ||
0e32b39c DA |
1273 | struct intel_dp_mst_encoder { |
1274 | struct intel_encoder base; | |
1275 | enum pipe pipe; | |
1276 | struct intel_digital_port *primary; | |
0552f765 | 1277 | struct intel_connector *connector; |
0e32b39c DA |
1278 | }; |
1279 | ||
65d64cc5 | 1280 | static inline enum dpio_channel |
89b667f8 JB |
1281 | vlv_dport_to_channel(struct intel_digital_port *dport) |
1282 | { | |
8f4f2797 | 1283 | switch (dport->base.port) { |
89b667f8 | 1284 | case PORT_B: |
00fc31b7 | 1285 | case PORT_D: |
e4607fcf | 1286 | return DPIO_CH0; |
89b667f8 | 1287 | case PORT_C: |
e4607fcf | 1288 | return DPIO_CH1; |
89b667f8 JB |
1289 | default: |
1290 | BUG(); | |
1291 | } | |
1292 | } | |
1293 | ||
65d64cc5 VS |
1294 | static inline enum dpio_phy |
1295 | vlv_dport_to_phy(struct intel_digital_port *dport) | |
1296 | { | |
8f4f2797 | 1297 | switch (dport->base.port) { |
65d64cc5 VS |
1298 | case PORT_B: |
1299 | case PORT_C: | |
1300 | return DPIO_PHY0; | |
1301 | case PORT_D: | |
1302 | return DPIO_PHY1; | |
1303 | default: | |
1304 | BUG(); | |
1305 | } | |
1306 | } | |
1307 | ||
1308 | static inline enum dpio_channel | |
eb69b0e5 CML |
1309 | vlv_pipe_to_channel(enum pipe pipe) |
1310 | { | |
1311 | switch (pipe) { | |
1312 | case PIPE_A: | |
1313 | case PIPE_C: | |
1314 | return DPIO_CH0; | |
1315 | case PIPE_B: | |
1316 | return DPIO_CH1; | |
1317 | default: | |
1318 | BUG(); | |
1319 | } | |
1320 | } | |
1321 | ||
e2af48c6 | 1322 | static inline struct intel_crtc * |
b91eb5cc | 1323 | intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) |
f875c15a | 1324 | { |
f875c15a CW |
1325 | return dev_priv->pipe_to_crtc_mapping[pipe]; |
1326 | } | |
1327 | ||
e2af48c6 | 1328 | static inline struct intel_crtc * |
ed15030d | 1329 | intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane) |
417ae147 | 1330 | { |
417ae147 CW |
1331 | return dev_priv->plane_to_crtc_mapping[plane]; |
1332 | } | |
1333 | ||
5f1aae65 | 1334 | struct intel_load_detect_pipe { |
edde3617 | 1335 | struct drm_atomic_state *restore_state; |
5f1aae65 | 1336 | }; |
79e53945 | 1337 | |
5f1aae65 PZ |
1338 | static inline struct intel_encoder * |
1339 | intel_attached_encoder(struct drm_connector *connector) | |
df0e9248 CW |
1340 | { |
1341 | return to_intel_connector(connector)->encoder; | |
1342 | } | |
1343 | ||
4ef03f83 | 1344 | static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder) |
da63a9f2 | 1345 | { |
4ef03f83 | 1346 | switch (encoder->type) { |
7e732cac | 1347 | case INTEL_OUTPUT_DDI: |
9a5da00b ACO |
1348 | case INTEL_OUTPUT_DP: |
1349 | case INTEL_OUTPUT_EDP: | |
1350 | case INTEL_OUTPUT_HDMI: | |
4ef03f83 VS |
1351 | return true; |
1352 | default: | |
1353 | return false; | |
1354 | } | |
1355 | } | |
1356 | ||
1357 | static inline struct intel_digital_port * | |
1358 | enc_to_dig_port(struct drm_encoder *encoder) | |
1359 | { | |
1360 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
1361 | ||
1362 | if (intel_encoder_is_dig_port(intel_encoder)) | |
9a5da00b ACO |
1363 | return container_of(encoder, struct intel_digital_port, |
1364 | base.base); | |
4ef03f83 | 1365 | else |
9a5da00b | 1366 | return NULL; |
9ff8c9ba ID |
1367 | } |
1368 | ||
bdc93fe0 R |
1369 | static inline struct intel_digital_port * |
1370 | conn_to_dig_port(struct intel_connector *connector) | |
1371 | { | |
1372 | return enc_to_dig_port(&intel_attached_encoder(&connector->base)->base); | |
1373 | } | |
1374 | ||
0e32b39c DA |
1375 | static inline struct intel_dp_mst_encoder * |
1376 | enc_to_mst(struct drm_encoder *encoder) | |
1377 | { | |
1378 | return container_of(encoder, struct intel_dp_mst_encoder, base.base); | |
1379 | } | |
1380 | ||
9ff8c9ba ID |
1381 | static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) |
1382 | { | |
1383 | return &enc_to_dig_port(encoder)->dp; | |
da63a9f2 PZ |
1384 | } |
1385 | ||
14aa521c VS |
1386 | static inline bool intel_encoder_is_dp(struct intel_encoder *encoder) |
1387 | { | |
1388 | switch (encoder->type) { | |
1389 | case INTEL_OUTPUT_DP: | |
1390 | case INTEL_OUTPUT_EDP: | |
1391 | return true; | |
1392 | case INTEL_OUTPUT_DDI: | |
1393 | /* Skip pure HDMI/DVI DDI encoders */ | |
1394 | return i915_mmio_reg_valid(enc_to_intel_dp(&encoder->base)->output_reg); | |
1395 | default: | |
1396 | return false; | |
1397 | } | |
1398 | } | |
1399 | ||
06c812d7 SS |
1400 | static inline struct intel_lspcon * |
1401 | enc_to_intel_lspcon(struct drm_encoder *encoder) | |
1402 | { | |
1403 | return &enc_to_dig_port(encoder)->lspcon; | |
1404 | } | |
1405 | ||
da63a9f2 PZ |
1406 | static inline struct intel_digital_port * |
1407 | dp_to_dig_port(struct intel_dp *intel_dp) | |
1408 | { | |
1409 | return container_of(intel_dp, struct intel_digital_port, dp); | |
1410 | } | |
1411 | ||
dd75f6dd ID |
1412 | static inline struct intel_lspcon * |
1413 | dp_to_lspcon(struct intel_dp *intel_dp) | |
1414 | { | |
1415 | return &dp_to_dig_port(intel_dp)->lspcon; | |
1416 | } | |
1417 | ||
de25eb7f RV |
1418 | static inline struct drm_i915_private * |
1419 | dp_to_i915(struct intel_dp *intel_dp) | |
1420 | { | |
1421 | return to_i915(dp_to_dig_port(intel_dp)->base.base.dev); | |
1422 | } | |
1423 | ||
da63a9f2 PZ |
1424 | static inline struct intel_digital_port * |
1425 | hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) | |
1426 | { | |
1427 | return container_of(intel_hdmi, struct intel_digital_port, hdmi); | |
7739c33b PZ |
1428 | } |
1429 | ||
1ab554b0 ML |
1430 | static inline struct intel_plane_state * |
1431 | intel_atomic_get_plane_state(struct intel_atomic_state *state, | |
1432 | struct intel_plane *plane) | |
1433 | { | |
1434 | struct drm_plane_state *ret = | |
1435 | drm_atomic_get_plane_state(&state->base, &plane->base); | |
1436 | ||
1437 | if (IS_ERR(ret)) | |
1438 | return ERR_CAST(ret); | |
1439 | ||
1440 | return to_intel_plane_state(ret); | |
1441 | } | |
1442 | ||
1443 | static inline struct intel_plane_state * | |
1444 | intel_atomic_get_old_plane_state(struct intel_atomic_state *state, | |
1445 | struct intel_plane *plane) | |
1446 | { | |
1447 | return to_intel_plane_state(drm_atomic_get_old_plane_state(&state->base, | |
1448 | &plane->base)); | |
1449 | } | |
1450 | ||
b2b55502 VS |
1451 | static inline struct intel_plane_state * |
1452 | intel_atomic_get_new_plane_state(struct intel_atomic_state *state, | |
1453 | struct intel_plane *plane) | |
1454 | { | |
1455 | return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base, | |
1456 | &plane->base)); | |
1457 | } | |
1458 | ||
7b510451 VS |
1459 | static inline struct intel_crtc_state * |
1460 | intel_atomic_get_old_crtc_state(struct intel_atomic_state *state, | |
1461 | struct intel_crtc *crtc) | |
1462 | { | |
1463 | return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base, | |
1464 | &crtc->base)); | |
1465 | } | |
1466 | ||
d3a8fb32 VS |
1467 | static inline struct intel_crtc_state * |
1468 | intel_atomic_get_new_crtc_state(struct intel_atomic_state *state, | |
1469 | struct intel_crtc *crtc) | |
1470 | { | |
1471 | return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base, | |
1472 | &crtc->base)); | |
1473 | } | |
1474 | ||
47339cd9 | 1475 | /* intel_fifo_underrun.c */ |
a72e4c9f | 1476 | bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv, |
87440425 | 1477 | enum pipe pipe, bool enable); |
a72e4c9f | 1478 | bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv, |
a2196033 | 1479 | enum pipe pch_transcoder, |
87440425 | 1480 | bool enable); |
1f7247c0 DV |
1481 | void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, |
1482 | enum pipe pipe); | |
1483 | void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, | |
a2196033 | 1484 | enum pipe pch_transcoder); |
aca7b684 VS |
1485 | void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv); |
1486 | void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv); | |
47339cd9 DV |
1487 | |
1488 | /* i915_irq.c */ | |
480c8033 DV |
1489 | void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
1490 | void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); | |
f4e9af4f AG |
1491 | void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask); |
1492 | void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask); | |
d02b98b8 | 1493 | void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv); |
dc97997a | 1494 | void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv); |
91d14251 TU |
1495 | void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv); |
1496 | void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv); | |
1300b4f8 CW |
1497 | |
1498 | static inline u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915, | |
1499 | u32 mask) | |
1500 | { | |
562d9bae | 1501 | return mask & ~i915->gt_pm.rps.pm_intrmsk_mbz; |
1300b4f8 CW |
1502 | } |
1503 | ||
b963291c DV |
1504 | void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv); |
1505 | void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv); | |
9df7575f JB |
1506 | static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv) |
1507 | { | |
1508 | /* | |
1509 | * We only use drm_irq_uninstall() at unload and VT switch, so | |
1510 | * this is the only thing we need to check. | |
1511 | */ | |
ad1443f0 | 1512 | return dev_priv->runtime_pm.irqs_enabled; |
9df7575f JB |
1513 | } |
1514 | ||
a225f079 | 1515 | int intel_get_crtc_scanline(struct intel_crtc *crtc); |
4c6c03be | 1516 | void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, |
001bd2cb | 1517 | u8 pipe_mask); |
aae8ba84 | 1518 | void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv, |
001bd2cb | 1519 | u8 pipe_mask); |
26705e20 SAK |
1520 | void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv); |
1521 | void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv); | |
1522 | void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv); | |
5f1aae65 | 1523 | |
5f1aae65 | 1524 | /* intel_crt.c */ |
6102a8ee VS |
1525 | bool intel_crt_port_enabled(struct drm_i915_private *dev_priv, |
1526 | i915_reg_t adpa_reg, enum pipe *pipe); | |
c39055b0 | 1527 | void intel_crt_init(struct drm_i915_private *dev_priv); |
9504a892 | 1528 | void intel_crt_reset(struct drm_encoder *encoder); |
5f1aae65 PZ |
1529 | |
1530 | /* intel_ddi.c */ | |
b7076546 | 1531 | void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder, |
5f88a9c6 VS |
1532 | const struct intel_crtc_state *old_crtc_state, |
1533 | const struct drm_connector_state *old_conn_state); | |
dc4a1094 ACO |
1534 | void hsw_fdi_link_train(struct intel_crtc *crtc, |
1535 | const struct intel_crtc_state *crtc_state); | |
c39055b0 | 1536 | void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port); |
87440425 | 1537 | bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe); |
3dc38eea | 1538 | void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state); |
90c3e219 | 1539 | void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state); |
3dc38eea ACO |
1540 | void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state); |
1541 | void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state); | |
3dc38eea | 1542 | void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state); |
ad64217b | 1543 | void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp); |
87440425 | 1544 | bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector); |
87440425 | 1545 | void intel_ddi_get_config(struct intel_encoder *encoder, |
5cec258b | 1546 | struct intel_crtc_state *pipe_config); |
5f1aae65 | 1547 | |
3dc38eea ACO |
1548 | void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state, |
1549 | bool state); | |
53e9bf5e VS |
1550 | void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, |
1551 | struct intel_crtc_state *crtc_state); | |
d509af6c | 1552 | u32 bxt_signal_levels(struct intel_dp *intel_dp); |
f8896f5d | 1553 | uint32_t ddi_signal_levels(struct intel_dp *intel_dp); |
ffe5111e | 1554 | u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder); |
4718a365 VS |
1555 | u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, |
1556 | u8 voltage_swing); | |
2320175f SP |
1557 | int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder, |
1558 | bool enable); | |
70332ac5 | 1559 | void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder); |
8327af28 VK |
1560 | int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv, |
1561 | enum intel_dpll_id pll_id); | |
ffe5111e | 1562 | |
d88c4afd | 1563 | unsigned int intel_fb_align_height(const struct drm_framebuffer *fb, |
5d2a1950 | 1564 | int color_plane, unsigned int height); |
b680c37a | 1565 | |
7c10a2b5 | 1566 | /* intel_audio.c */ |
88212941 | 1567 | void intel_init_audio_hooks(struct drm_i915_private *dev_priv); |
bbf35e9d ML |
1568 | void intel_audio_codec_enable(struct intel_encoder *encoder, |
1569 | const struct intel_crtc_state *crtc_state, | |
1570 | const struct drm_connector_state *conn_state); | |
8ec47de2 VS |
1571 | void intel_audio_codec_disable(struct intel_encoder *encoder, |
1572 | const struct intel_crtc_state *old_crtc_state, | |
1573 | const struct drm_connector_state *old_conn_state); | |
58fddc28 ID |
1574 | void i915_audio_component_init(struct drm_i915_private *dev_priv); |
1575 | void i915_audio_component_cleanup(struct drm_i915_private *dev_priv); | |
eef57324 JA |
1576 | void intel_audio_init(struct drm_i915_private *dev_priv); |
1577 | void intel_audio_deinit(struct drm_i915_private *dev_priv); | |
7c10a2b5 | 1578 | |
7ff89ca2 | 1579 | /* intel_cdclk.c */ |
d305e061 | 1580 | int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state); |
e1cd3325 PZ |
1581 | void skl_init_cdclk(struct drm_i915_private *dev_priv); |
1582 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv); | |
d8d4a512 VS |
1583 | void cnl_init_cdclk(struct drm_i915_private *dev_priv); |
1584 | void cnl_uninit_cdclk(struct drm_i915_private *dev_priv); | |
e1cd3325 PZ |
1585 | void bxt_init_cdclk(struct drm_i915_private *dev_priv); |
1586 | void bxt_uninit_cdclk(struct drm_i915_private *dev_priv); | |
186a277e PZ |
1587 | void icl_init_cdclk(struct drm_i915_private *dev_priv); |
1588 | void icl_uninit_cdclk(struct drm_i915_private *dev_priv); | |
7ff89ca2 VS |
1589 | void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv); |
1590 | void intel_update_max_cdclk(struct drm_i915_private *dev_priv); | |
1591 | void intel_update_cdclk(struct drm_i915_private *dev_priv); | |
1592 | void intel_update_rawclk(struct drm_i915_private *dev_priv); | |
90402bab VS |
1593 | bool intel_cdclk_needs_cd2x_update(struct drm_i915_private *dev_priv, |
1594 | const struct intel_cdclk_state *a, | |
1595 | const struct intel_cdclk_state *b); | |
64600bd5 | 1596 | bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a, |
49cd97a3 | 1597 | const struct intel_cdclk_state *b); |
64600bd5 VS |
1598 | bool intel_cdclk_changed(const struct intel_cdclk_state *a, |
1599 | const struct intel_cdclk_state *b); | |
b9611004 | 1600 | void intel_cdclk_swap_state(struct intel_atomic_state *state); |
90402bab VS |
1601 | void |
1602 | intel_set_cdclk_pre_plane_update(struct drm_i915_private *dev_priv, | |
1603 | const struct intel_cdclk_state *old_state, | |
1604 | const struct intel_cdclk_state *new_state, | |
1605 | enum pipe pipe); | |
1606 | void | |
1607 | intel_set_cdclk_post_plane_update(struct drm_i915_private *dev_priv, | |
1608 | const struct intel_cdclk_state *old_state, | |
1609 | const struct intel_cdclk_state *new_state, | |
1610 | enum pipe pipe); | |
cfddadc9 VS |
1611 | void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state, |
1612 | const char *context); | |
7ff89ca2 | 1613 | |
b680c37a | 1614 | /* intel_display.c */ |
2ee0da16 VS |
1615 | void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); |
1616 | void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); | |
a2196033 | 1617 | enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc); |
49cd97a3 | 1618 | int vlv_get_hpll_vco(struct drm_i915_private *dev_priv); |
c30fec65 VS |
1619 | int vlv_get_cck_clock(struct drm_i915_private *dev_priv, |
1620 | const char *name, u32 reg, int ref_freq); | |
7ff89ca2 VS |
1621 | int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, |
1622 | const char *name, u32 reg); | |
b7076546 ML |
1623 | void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv); |
1624 | void lpt_disable_iclkip(struct drm_i915_private *dev_priv); | |
88212941 | 1625 | void intel_init_display_hooks(struct drm_i915_private *dev_priv); |
6687c906 | 1626 | unsigned int intel_fb_xy_to_linear(int x, int y, |
2949056c VS |
1627 | const struct intel_plane_state *state, |
1628 | int plane); | |
6687c906 | 1629 | void intel_add_fb_offsets(int *x, int *y, |
2949056c | 1630 | const struct intel_plane_state *state, int plane); |
1663b9d6 | 1631 | unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info); |
49d73912 | 1632 | bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv); |
7d993739 TU |
1633 | void intel_mark_busy(struct drm_i915_private *dev_priv); |
1634 | void intel_mark_idle(struct drm_i915_private *dev_priv); | |
70e0bd74 | 1635 | int intel_display_suspend(struct drm_device *dev); |
8090ba8c | 1636 | void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv); |
87440425 | 1637 | void intel_encoder_destroy(struct drm_encoder *encoder); |
de330815 VS |
1638 | struct drm_display_mode * |
1639 | intel_encoder_current_mode(struct intel_encoder *encoder); | |
176597a1 | 1640 | bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port); |
ac213c1b PZ |
1641 | bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port); |
1642 | enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, | |
1643 | enum port port); | |
6a20fe7b VS |
1644 | int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, |
1645 | struct drm_file *file_priv); | |
87440425 PZ |
1646 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
1647 | enum pipe pipe); | |
2d84d2b3 VS |
1648 | static inline bool |
1649 | intel_crtc_has_type(const struct intel_crtc_state *crtc_state, | |
1650 | enum intel_output_type type) | |
1651 | { | |
1652 | return crtc_state->output_types & (1 << type); | |
1653 | } | |
37a5650b VS |
1654 | static inline bool |
1655 | intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state) | |
1656 | { | |
1657 | return crtc_state->output_types & | |
cca0502b | 1658 | ((1 << INTEL_OUTPUT_DP) | |
37a5650b VS |
1659 | (1 << INTEL_OUTPUT_DP_MST) | |
1660 | (1 << INTEL_OUTPUT_EDP)); | |
1661 | } | |
4f905cf9 | 1662 | static inline void |
0f0f74bc | 1663 | intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe) |
4f905cf9 | 1664 | { |
0f0f74bc | 1665 | drm_wait_one_vblank(&dev_priv->drm, pipe); |
4f905cf9 | 1666 | } |
0c241d5b | 1667 | static inline void |
0f0f74bc | 1668 | intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe) |
0c241d5b | 1669 | { |
b91eb5cc | 1670 | const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
0c241d5b VS |
1671 | |
1672 | if (crtc->active) | |
0f0f74bc | 1673 | intel_wait_for_vblank(dev_priv, pipe); |
0c241d5b | 1674 | } |
a2991414 ML |
1675 | |
1676 | u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc); | |
1677 | ||
87440425 | 1678 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); |
e4607fcf | 1679 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1680 | struct intel_digital_port *dport, |
1681 | unsigned int expected_mask); | |
6c5ed5ae | 1682 | int intel_get_load_detect_pipe(struct drm_connector *connector, |
bacdcd55 | 1683 | const struct drm_display_mode *mode, |
6c5ed5ae ML |
1684 | struct intel_load_detect_pipe *old, |
1685 | struct drm_modeset_acquire_ctx *ctx); | |
87440425 | 1686 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
1687 | struct intel_load_detect_pipe *old, |
1688 | struct drm_modeset_acquire_ctx *ctx); | |
058d88c4 | 1689 | struct i915_vma * |
5935485f | 1690 | intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, |
f5929c53 | 1691 | const struct i915_ggtt_view *view, |
f7a02ad7 | 1692 | bool uses_fence, |
5935485f CW |
1693 | unsigned long *out_flags); |
1694 | void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags); | |
a8bb6818 | 1695 | struct drm_framebuffer * |
24dbf51a CW |
1696 | intel_framebuffer_create(struct drm_i915_gem_object *obj, |
1697 | struct drm_mode_fb_cmd2 *mode_cmd); | |
6beb8c23 | 1698 | int intel_prepare_plane_fb(struct drm_plane *plane, |
1832040d | 1699 | struct drm_plane_state *new_state); |
38f3ce3a | 1700 | void intel_cleanup_plane_fb(struct drm_plane *plane, |
1832040d | 1701 | struct drm_plane_state *old_state); |
a98b3431 MR |
1702 | int intel_plane_atomic_get_property(struct drm_plane *plane, |
1703 | const struct drm_plane_state *state, | |
1704 | struct drm_property *property, | |
1705 | uint64_t *val); | |
1706 | int intel_plane_atomic_set_property(struct drm_plane *plane, | |
1707 | struct drm_plane_state *state, | |
1708 | struct drm_property *property, | |
1709 | uint64_t val); | |
b2b55502 VS |
1710 | int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state, |
1711 | struct drm_crtc_state *crtc_state, | |
1712 | const struct intel_plane_state *old_plane_state, | |
da20eabd | 1713 | struct drm_plane_state *plane_state); |
716c2e55 | 1714 | |
7abd4b35 ACO |
1715 | void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1716 | enum pipe pipe); | |
1717 | ||
30ad9814 | 1718 | int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, |
3f36b937 | 1719 | const struct dpll *dpll); |
30ad9814 | 1720 | void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe); |
8802e5b6 | 1721 | int lpt_get_iclkip(struct drm_i915_private *dev_priv); |
d288f65f | 1722 | |
716c2e55 | 1723 | /* modesetting asserts */ |
b680c37a DV |
1724 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1725 | enum pipe pipe); | |
55607e8a DV |
1726 | void assert_pll(struct drm_i915_private *dev_priv, |
1727 | enum pipe pipe, bool state); | |
1728 | #define assert_pll_enabled(d, p) assert_pll(d, p, true) | |
1729 | #define assert_pll_disabled(d, p) assert_pll(d, p, false) | |
8563b1e8 LL |
1730 | void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state); |
1731 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1732 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
55607e8a DV |
1733 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1734 | enum pipe pipe, bool state); | |
1735 | #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true) | |
1736 | #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false) | |
87440425 | 1737 | void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state); |
b840d907 JB |
1738 | #define assert_pipe_enabled(d, p) assert_pipe(d, p, true) |
1739 | #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) | |
c033666a CW |
1740 | void intel_prepare_reset(struct drm_i915_private *dev_priv); |
1741 | void intel_finish_reset(struct drm_i915_private *dev_priv); | |
a14cb6fc PZ |
1742 | void hsw_enable_pc8(struct drm_i915_private *dev_priv); |
1743 | void hsw_disable_pc8(struct drm_i915_private *dev_priv); | |
da2f41d1 | 1744 | void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv); |
664326f8 SK |
1745 | void bxt_enable_dc9(struct drm_i915_private *dev_priv); |
1746 | void bxt_disable_dc9(struct drm_i915_private *dev_priv); | |
f62c79b3 | 1747 | void gen9_enable_dc5(struct drm_i915_private *dev_priv); |
c89e39f3 | 1748 | unsigned int skl_cdclk_get_vco(unsigned int freq); |
3e68928b | 1749 | void skl_enable_dc6(struct drm_i915_private *dev_priv); |
87440425 | 1750 | void intel_dp_get_m_n(struct intel_crtc *crtc, |
5cec258b | 1751 | struct intel_crtc_state *pipe_config); |
4c354754 ML |
1752 | void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, |
1753 | enum link_m_n_set m_n); | |
87440425 | 1754 | int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); |
5ab7b0b7 | 1755 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
9e2c8475 ACO |
1756 | struct dpll *best_clock); |
1757 | int chv_calc_dpll_params(int refclk, struct dpll *pll_clock); | |
dccbea3b | 1758 | |
525b9311 | 1759 | bool intel_crtc_active(struct intel_crtc *crtc); |
24f28450 | 1760 | bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state); |
199ea381 ML |
1761 | void hsw_enable_ips(const struct intel_crtc_state *crtc_state); |
1762 | void hsw_disable_ips(const struct intel_crtc_state *crtc_state); | |
79f255a0 | 1763 | enum intel_display_power_domain intel_port_to_power_domain(enum port port); |
337837ac ID |
1764 | enum intel_display_power_domain |
1765 | intel_aux_power_domain(struct intel_digital_port *dig_port); | |
f6a83288 | 1766 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 1767 | struct intel_crtc_state *pipe_config); |
d52ad9cb ML |
1768 | void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, |
1769 | struct intel_crtc_state *crtc_state); | |
86adf9d7 | 1770 | |
e7a278a3 | 1771 | u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center); |
e435d6e5 | 1772 | int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state); |
4e0b83a5 VS |
1773 | int skl_max_scale(const struct intel_crtc_state *crtc_state, |
1774 | u32 pixel_format); | |
8ea30864 | 1775 | |
be1e3415 CW |
1776 | static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state) |
1777 | { | |
1778 | return i915_ggtt_offset(state->vma); | |
1779 | } | |
dedf278c | 1780 | |
4036c78c JA |
1781 | u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state, |
1782 | const struct intel_plane_state *plane_state); | |
2e881264 VS |
1783 | u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, |
1784 | const struct intel_plane_state *plane_state); | |
38f24f21 | 1785 | u32 glk_color_ctl(const struct intel_plane_state *plane_state); |
df79cf44 VS |
1786 | u32 skl_plane_stride(const struct intel_plane_state *plane_state, |
1787 | int plane); | |
73266595 | 1788 | int skl_check_plane_surface(struct intel_plane_state *plane_state); |
f9407ae1 | 1789 | int i9xx_check_plane_surface(struct intel_plane_state *plane_state); |
ddf34319 | 1790 | int skl_format_to_fourcc(int format, bool rgb_order, bool alpha); |
ddd5713d VS |
1791 | unsigned int i9xx_plane_max_stride(struct intel_plane *plane, |
1792 | u32 pixel_format, u64 modifier, | |
1793 | unsigned int rotation); | |
121920fa | 1794 | |
360fa66a | 1795 | /* intel_connector.c */ |
1c21348d JN |
1796 | int intel_connector_init(struct intel_connector *connector); |
1797 | struct intel_connector *intel_connector_alloc(void); | |
1798 | void intel_connector_free(struct intel_connector *connector); | |
1799 | void intel_connector_destroy(struct drm_connector *connector); | |
1800 | int intel_connector_register(struct drm_connector *connector); | |
1801 | void intel_connector_unregister(struct drm_connector *connector); | |
1802 | void intel_connector_attach_encoder(struct intel_connector *connector, | |
1803 | struct intel_encoder *encoder); | |
1804 | bool intel_connector_get_hw_state(struct intel_connector *connector); | |
046c9bca | 1805 | enum pipe intel_connector_get_pipe(struct intel_connector *connector); |
360fa66a JN |
1806 | int intel_connector_update_modes(struct drm_connector *connector, |
1807 | struct edid *edid); | |
1808 | int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter); | |
1809 | void intel_attach_force_audio_property(struct drm_connector *connector); | |
1810 | void intel_attach_broadcast_rgb_property(struct drm_connector *connector); | |
1811 | void intel_attach_aspect_ratio_property(struct drm_connector *connector); | |
1812 | ||
eb805623 | 1813 | /* intel_csr.c */ |
f4448375 | 1814 | void intel_csr_ucode_init(struct drm_i915_private *); |
2abc525b | 1815 | void intel_csr_load_program(struct drm_i915_private *); |
f4448375 | 1816 | void intel_csr_ucode_fini(struct drm_i915_private *); |
f74ed08d ID |
1817 | void intel_csr_ucode_suspend(struct drm_i915_private *); |
1818 | void intel_csr_ucode_resume(struct drm_i915_private *); | |
eb805623 | 1819 | |
5f1aae65 | 1820 | /* intel_dp.c */ |
59b74c49 VS |
1821 | bool intel_dp_port_enabled(struct drm_i915_private *dev_priv, |
1822 | i915_reg_t dp_reg, enum port port, | |
1823 | enum pipe *pipe); | |
c39055b0 ACO |
1824 | bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg, |
1825 | enum port port); | |
87440425 PZ |
1826 | bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
1827 | struct intel_connector *intel_connector); | |
901c2daf | 1828 | void intel_dp_set_link_params(struct intel_dp *intel_dp, |
dfa10480 ACO |
1829 | int link_rate, uint8_t lane_count, |
1830 | bool link_mst); | |
fdb14d33 MN |
1831 | int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, |
1832 | int link_rate, uint8_t lane_count); | |
87440425 | 1833 | void intel_dp_start_link_train(struct intel_dp *intel_dp); |
87440425 | 1834 | void intel_dp_stop_link_train(struct intel_dp *intel_dp); |
c85d200e VS |
1835 | int intel_dp_retrain_link(struct intel_encoder *encoder, |
1836 | struct drm_modeset_acquire_ctx *ctx); | |
87440425 | 1837 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode); |
2279298d GS |
1838 | void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp, |
1839 | const struct intel_crtc_state *crtc_state, | |
1840 | bool enable); | |
bf93ba67 ID |
1841 | void intel_dp_encoder_reset(struct drm_encoder *encoder); |
1842 | void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder); | |
87440425 | 1843 | void intel_dp_encoder_destroy(struct drm_encoder *encoder); |
87440425 | 1844 | bool intel_dp_compute_config(struct intel_encoder *encoder, |
0a478c27 ML |
1845 | struct intel_crtc_state *pipe_config, |
1846 | struct drm_connector_state *conn_state); | |
1853a9da | 1847 | bool intel_dp_is_edp(struct intel_dp *intel_dp); |
7b91bf7f | 1848 | bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port); |
b2c5c181 DV |
1849 | enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, |
1850 | bool long_hpd); | |
b037d58f ML |
1851 | void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state, |
1852 | const struct drm_connector_state *conn_state); | |
1853 | void intel_edp_backlight_off(const struct drm_connector_state *conn_state); | |
24f3e092 | 1854 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp); |
4be73780 DV |
1855 | void intel_edp_panel_on(struct intel_dp *intel_dp); |
1856 | void intel_edp_panel_off(struct intel_dp *intel_dp); | |
1a4313d1 VS |
1857 | void intel_dp_mst_suspend(struct drm_i915_private *dev_priv); |
1858 | void intel_dp_mst_resume(struct drm_i915_private *dev_priv); | |
50fec21a | 1859 | int intel_dp_max_link_rate(struct intel_dp *intel_dp); |
3d65a735 | 1860 | int intel_dp_max_lane_count(struct intel_dp *intel_dp); |
ed4e9c1d | 1861 | int intel_dp_rate_select(struct intel_dp *intel_dp, int rate); |
0e32b39c | 1862 | void intel_dp_hot_plug(struct intel_encoder *intel_encoder); |
78597996 | 1863 | void intel_power_sequencer_reset(struct drm_i915_private *dev_priv); |
0bc12bcb | 1864 | uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes); |
4a3b8769 | 1865 | void intel_plane_destroy(struct drm_plane *plane); |
85cb48a1 | 1866 | void intel_edp_drrs_enable(struct intel_dp *intel_dp, |
5f88a9c6 | 1867 | const struct intel_crtc_state *crtc_state); |
85cb48a1 | 1868 | void intel_edp_drrs_disable(struct intel_dp *intel_dp, |
5f88a9c6 | 1869 | const struct intel_crtc_state *crtc_state); |
5748b6a1 CW |
1870 | void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv, |
1871 | unsigned int frontbuffer_bits); | |
1872 | void intel_edp_drrs_flush(struct drm_i915_private *dev_priv, | |
1873 | unsigned int frontbuffer_bits); | |
0bc12bcb | 1874 | |
94223d04 ACO |
1875 | void |
1876 | intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, | |
1877 | uint8_t dp_train_pat); | |
1878 | void | |
1879 | intel_dp_set_signal_levels(struct intel_dp *intel_dp); | |
1880 | void intel_dp_set_idle_link_train(struct intel_dp *intel_dp); | |
1881 | uint8_t | |
1882 | intel_dp_voltage_max(struct intel_dp *intel_dp); | |
1883 | uint8_t | |
1884 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing); | |
1885 | void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, | |
1886 | uint8_t *link_bw, uint8_t *rate_select); | |
e588fa18 | 1887 | bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp); |
2edd5327 | 1888 | bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp); |
94223d04 ACO |
1889 | bool |
1890 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]); | |
d9218c8f MN |
1891 | uint16_t intel_dp_dsc_get_output_bpp(int link_clock, uint8_t lane_count, |
1892 | int mode_clock, int mode_hdisplay); | |
1893 | uint8_t intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int mode_clock, | |
1894 | int mode_hdisplay); | |
94223d04 | 1895 | |
168243c1 GS |
1896 | /* intel_vdsc.c */ |
1897 | int intel_dp_compute_dsc_params(struct intel_dp *intel_dp, | |
1898 | struct intel_crtc_state *pipe_config); | |
a24c62f9 MN |
1899 | enum intel_display_power_domain |
1900 | intel_dsc_power_domain(const struct intel_crtc_state *crtc_state); | |
168243c1 | 1901 | |
419b1b7a ACO |
1902 | static inline unsigned int intel_dp_unused_lane_mask(int lane_count) |
1903 | { | |
1904 | return ~((1 << lane_count) - 1) & 0xf; | |
1905 | } | |
1906 | ||
24e807e7 | 1907 | bool intel_dp_read_dpcd(struct intel_dp *intel_dp); |
22a2c8e0 DP |
1908 | int intel_dp_link_required(int pixel_clock, int bpp); |
1909 | int intel_dp_max_data_rate(int max_link_clock, int max_lanes); | |
7533eb4f | 1910 | bool intel_digital_port_connected(struct intel_encoder *encoder); |
24e807e7 | 1911 | |
e7156c83 YA |
1912 | /* intel_dp_aux_backlight.c */ |
1913 | int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector); | |
1914 | ||
0e32b39c DA |
1915 | /* intel_dp_mst.c */ |
1916 | int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id); | |
1917 | void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port); | |
ca3589c1 | 1918 | /* vlv_dsi.c */ |
e518634b | 1919 | void vlv_dsi_init(struct drm_i915_private *dev_priv); |
5f1aae65 | 1920 | |
bf4d57ff MC |
1921 | /* icl_dsi.c */ |
1922 | void icl_dsi_init(struct drm_i915_private *dev_priv); | |
1923 | ||
90198355 JN |
1924 | /* intel_dsi_dcs_backlight.c */ |
1925 | int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector); | |
5f1aae65 PZ |
1926 | |
1927 | /* intel_dvo.c */ | |
c39055b0 | 1928 | void intel_dvo_init(struct drm_i915_private *dev_priv); |
19625e85 L |
1929 | /* intel_hotplug.c */ |
1930 | void intel_hpd_poll_init(struct drm_i915_private *dev_priv); | |
4211bdba ID |
1931 | enum intel_hotplug_state intel_encoder_hotplug(struct intel_encoder *encoder, |
1932 | struct intel_connector *connector, | |
1933 | bool irq_received); | |
5f1aae65 | 1934 | |
0632fef6 | 1935 | /* legacy fbdev emulation in intel_fbdev.c */ |
0695726e | 1936 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
4520f53a | 1937 | extern int intel_fbdev_init(struct drm_device *dev); |
e00bf696 | 1938 | extern void intel_fbdev_initial_config_async(struct drm_device *dev); |
4f256d82 DV |
1939 | extern void intel_fbdev_unregister(struct drm_i915_private *dev_priv); |
1940 | extern void intel_fbdev_fini(struct drm_i915_private *dev_priv); | |
82e3b8c1 | 1941 | extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous); |
0632fef6 DV |
1942 | extern void intel_fbdev_output_poll_changed(struct drm_device *dev); |
1943 | extern void intel_fbdev_restore_mode(struct drm_device *dev); | |
4520f53a DV |
1944 | #else |
1945 | static inline int intel_fbdev_init(struct drm_device *dev) | |
1946 | { | |
1947 | return 0; | |
1948 | } | |
5f1aae65 | 1949 | |
e00bf696 | 1950 | static inline void intel_fbdev_initial_config_async(struct drm_device *dev) |
4520f53a DV |
1951 | { |
1952 | } | |
1953 | ||
4f256d82 DV |
1954 | static inline void intel_fbdev_unregister(struct drm_i915_private *dev_priv) |
1955 | { | |
1956 | } | |
1957 | ||
1958 | static inline void intel_fbdev_fini(struct drm_i915_private *dev_priv) | |
4520f53a DV |
1959 | { |
1960 | } | |
1961 | ||
82e3b8c1 | 1962 | static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous) |
4520f53a DV |
1963 | { |
1964 | } | |
1965 | ||
d9c409d6 JN |
1966 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
1967 | { | |
1968 | } | |
1969 | ||
0632fef6 | 1970 | static inline void intel_fbdev_restore_mode(struct drm_device *dev) |
4520f53a DV |
1971 | { |
1972 | } | |
1973 | #endif | |
5f1aae65 | 1974 | |
7ff0ebcc | 1975 | /* intel_fbc.c */ |
f51be2e0 | 1976 | void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv, |
dd57602e | 1977 | struct intel_atomic_state *state); |
0e631adc | 1978 | bool intel_fbc_is_active(struct drm_i915_private *dev_priv); |
faf68d92 ML |
1979 | void intel_fbc_pre_update(struct intel_crtc *crtc, |
1980 | struct intel_crtc_state *crtc_state, | |
1981 | struct intel_plane_state *plane_state); | |
1eb52238 | 1982 | void intel_fbc_post_update(struct intel_crtc *crtc); |
7ff0ebcc | 1983 | void intel_fbc_init(struct drm_i915_private *dev_priv); |
010cf73d | 1984 | void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv); |
faf68d92 ML |
1985 | void intel_fbc_enable(struct intel_crtc *crtc, |
1986 | struct intel_crtc_state *crtc_state, | |
1987 | struct intel_plane_state *plane_state); | |
c937ab3e PZ |
1988 | void intel_fbc_disable(struct intel_crtc *crtc); |
1989 | void intel_fbc_global_disable(struct drm_i915_private *dev_priv); | |
dbef0f15 PZ |
1990 | void intel_fbc_invalidate(struct drm_i915_private *dev_priv, |
1991 | unsigned int frontbuffer_bits, | |
1992 | enum fb_op_origin origin); | |
1993 | void intel_fbc_flush(struct drm_i915_private *dev_priv, | |
6f4551fe | 1994 | unsigned int frontbuffer_bits, enum fb_op_origin origin); |
7733b49b | 1995 | void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv); |
61a585d6 | 1996 | void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv); |
d52ad9cb | 1997 | int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv); |
7ff0ebcc | 1998 | |
5f1aae65 | 1999 | /* intel_hdmi.c */ |
c39055b0 ACO |
2000 | void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg, |
2001 | enum port port); | |
87440425 PZ |
2002 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
2003 | struct intel_connector *intel_connector); | |
2004 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder); | |
2005 | bool intel_hdmi_compute_config(struct intel_encoder *encoder, | |
0a478c27 ML |
2006 | struct intel_crtc_state *pipe_config, |
2007 | struct drm_connector_state *conn_state); | |
277ab5ab | 2008 | bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder, |
15953637 SS |
2009 | struct drm_connector *connector, |
2010 | bool high_tmds_clock_ratio, | |
2011 | bool scrambling); | |
b2ccb822 | 2012 | void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable); |
385e4de0 | 2013 | void intel_infoframe_init(struct intel_digital_port *intel_dig_port); |
5f1aae65 | 2014 | |
5f1aae65 | 2015 | /* intel_lvds.c */ |
a44628b9 VS |
2016 | bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv, |
2017 | i915_reg_t lvds_reg, enum pipe *pipe); | |
c39055b0 | 2018 | void intel_lvds_init(struct drm_i915_private *dev_priv); |
97a824e1 | 2019 | struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev); |
87440425 | 2020 | bool intel_is_dual_link_lvds(struct drm_device *dev); |
5f1aae65 | 2021 | |
5f1aae65 | 2022 | /* intel_overlay.c */ |
58db08a7 JRS |
2023 | void intel_overlay_setup(struct drm_i915_private *dev_priv); |
2024 | void intel_overlay_cleanup(struct drm_i915_private *dev_priv); | |
87440425 | 2025 | int intel_overlay_switch_off(struct intel_overlay *overlay); |
1ee8da6d CW |
2026 | int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data, |
2027 | struct drm_file *file_priv); | |
2028 | int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data, | |
2029 | struct drm_file *file_priv); | |
1362b776 | 2030 | void intel_overlay_reset(struct drm_i915_private *dev_priv); |
5f1aae65 PZ |
2031 | |
2032 | ||
2033 | /* intel_panel.c */ | |
87440425 | 2034 | int intel_panel_init(struct intel_panel *panel, |
4b6ed685 VK |
2035 | struct drm_display_mode *fixed_mode, |
2036 | struct drm_display_mode *downclock_mode); | |
87440425 PZ |
2037 | void intel_panel_fini(struct intel_panel *panel); |
2038 | void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode, | |
2039 | struct drm_display_mode *adjusted_mode); | |
2040 | void intel_pch_panel_fitting(struct intel_crtc *crtc, | |
5cec258b | 2041 | struct intel_crtc_state *pipe_config, |
87440425 PZ |
2042 | int fitting_mode); |
2043 | void intel_gmch_panel_fitting(struct intel_crtc *crtc, | |
5cec258b | 2044 | struct intel_crtc_state *pipe_config, |
87440425 | 2045 | int fitting_mode); |
90d7cd24 | 2046 | void intel_panel_set_backlight_acpi(const struct drm_connector_state *conn_state, |
6dda730e | 2047 | u32 level, u32 max); |
fda9ee98 CW |
2048 | int intel_panel_setup_backlight(struct drm_connector *connector, |
2049 | enum pipe pipe); | |
b037d58f ML |
2050 | void intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state, |
2051 | const struct drm_connector_state *conn_state); | |
2052 | void intel_panel_disable_backlight(const struct drm_connector_state *old_conn_state); | |
ec9ed197 | 2053 | extern struct drm_display_mode *intel_find_panel_downclock( |
a318b4c4 | 2054 | struct drm_i915_private *dev_priv, |
ec9ed197 VK |
2055 | struct drm_display_mode *fixed_mode, |
2056 | struct drm_connector *connector); | |
e63d87c0 CW |
2057 | |
2058 | #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE) | |
1ebaa0b9 | 2059 | int intel_backlight_device_register(struct intel_connector *connector); |
e63d87c0 CW |
2060 | void intel_backlight_device_unregister(struct intel_connector *connector); |
2061 | #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */ | |
2de2d0b0 | 2062 | static inline int intel_backlight_device_register(struct intel_connector *connector) |
1ebaa0b9 CW |
2063 | { |
2064 | return 0; | |
2065 | } | |
e63d87c0 CW |
2066 | static inline void intel_backlight_device_unregister(struct intel_connector *connector) |
2067 | { | |
2068 | } | |
2069 | #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */ | |
0962c3c9 | 2070 | |
ee5e5e7a SP |
2071 | /* intel_hdcp.c */ |
2072 | void intel_hdcp_atomic_check(struct drm_connector *connector, | |
2073 | struct drm_connector_state *old_state, | |
2074 | struct drm_connector_state *new_state); | |
2075 | int intel_hdcp_init(struct intel_connector *connector, | |
2076 | const struct intel_hdcp_shim *hdcp_shim); | |
2077 | int intel_hdcp_enable(struct intel_connector *connector); | |
2078 | int intel_hdcp_disable(struct intel_connector *connector); | |
2079 | int intel_hdcp_check_link(struct intel_connector *connector); | |
fdddd08c | 2080 | bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port); |
bdc93fe0 | 2081 | bool intel_hdcp_capable(struct intel_connector *connector); |
5f1aae65 | 2082 | |
0bc12bcb | 2083 | /* intel_psr.c */ |
4371d896 | 2084 | #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support) |
77fe36ff | 2085 | void intel_psr_init_dpcd(struct intel_dp *intel_dp); |
d2419ffc VS |
2086 | void intel_psr_enable(struct intel_dp *intel_dp, |
2087 | const struct intel_crtc_state *crtc_state); | |
2088 | void intel_psr_disable(struct intel_dp *intel_dp, | |
2089 | const struct intel_crtc_state *old_crtc_state); | |
c44301fc ML |
2090 | int intel_psr_set_debugfs_mode(struct drm_i915_private *dev_priv, |
2091 | struct drm_modeset_acquire_ctx *ctx, | |
2092 | u64 value); | |
5748b6a1 | 2093 | void intel_psr_invalidate(struct drm_i915_private *dev_priv, |
5baf63cc RV |
2094 | unsigned frontbuffer_bits, |
2095 | enum fb_op_origin origin); | |
5748b6a1 | 2096 | void intel_psr_flush(struct drm_i915_private *dev_priv, |
169de131 RV |
2097 | unsigned frontbuffer_bits, |
2098 | enum fb_op_origin origin); | |
c39055b0 | 2099 | void intel_psr_init(struct drm_i915_private *dev_priv); |
4d90f2d5 VS |
2100 | void intel_psr_compute_config(struct intel_dp *intel_dp, |
2101 | struct intel_crtc_state *crtc_state); | |
1aeb1b5f | 2102 | void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug); |
54fd3149 | 2103 | void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir); |
cc3054ff | 2104 | void intel_psr_short_pulse(struct intel_dp *intel_dp); |
63ec132d DP |
2105 | int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state, |
2106 | u32 *out_value); | |
2f8e7ea9 | 2107 | bool intel_psr_enabled(struct intel_dp *intel_dp); |
0bc12bcb | 2108 | |
593a21a0 | 2109 | /* intel_quirks.c */ |
27a981b6 | 2110 | void intel_init_quirks(struct drm_i915_private *dev_priv); |
593a21a0 | 2111 | |
9c065a7d DV |
2112 | /* intel_runtime_pm.c */ |
2113 | int intel_power_domains_init(struct drm_i915_private *); | |
f28ec6f4 | 2114 | void intel_power_domains_cleanup(struct drm_i915_private *dev_priv); |
73dfc227 | 2115 | void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume); |
48a287ed | 2116 | void intel_power_domains_fini_hw(struct drm_i915_private *dev_priv); |
3e68928b AM |
2117 | void icl_display_core_init(struct drm_i915_private *dev_priv, bool resume); |
2118 | void icl_display_core_uninit(struct drm_i915_private *dev_priv); | |
2cd9a689 ID |
2119 | void intel_power_domains_enable(struct drm_i915_private *dev_priv); |
2120 | void intel_power_domains_disable(struct drm_i915_private *dev_priv); | |
2121 | ||
2122 | enum i915_drm_suspend_mode { | |
2123 | I915_DRM_SUSPEND_IDLE, | |
2124 | I915_DRM_SUSPEND_MEM, | |
2125 | I915_DRM_SUSPEND_HIBERNATE, | |
2126 | }; | |
2127 | ||
2128 | void intel_power_domains_suspend(struct drm_i915_private *dev_priv, | |
2129 | enum i915_drm_suspend_mode); | |
2130 | void intel_power_domains_resume(struct drm_i915_private *dev_priv); | |
d7d7c9ee ID |
2131 | void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume); |
2132 | void bxt_display_core_uninit(struct drm_i915_private *dev_priv); | |
f458ebbc | 2133 | void intel_runtime_pm_enable(struct drm_i915_private *dev_priv); |
07d80572 | 2134 | void intel_runtime_pm_disable(struct drm_i915_private *dev_priv); |
9895ad03 DS |
2135 | const char * |
2136 | intel_display_power_domain_str(enum intel_display_power_domain domain); | |
9c065a7d | 2137 | |
f458ebbc DV |
2138 | bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, |
2139 | enum intel_display_power_domain domain); | |
2140 | bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, | |
2141 | enum intel_display_power_domain domain); | |
9c065a7d DV |
2142 | void intel_display_power_get(struct drm_i915_private *dev_priv, |
2143 | enum intel_display_power_domain domain); | |
09731280 ID |
2144 | bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv, |
2145 | enum intel_display_power_domain domain); | |
9c065a7d DV |
2146 | void intel_display_power_put(struct drm_i915_private *dev_priv, |
2147 | enum intel_display_power_domain domain); | |
aa9664ff MK |
2148 | void icl_dbuf_slices_update(struct drm_i915_private *dev_priv, |
2149 | u8 req_slices); | |
da5827c3 ID |
2150 | |
2151 | static inline void | |
2152 | assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv) | |
2153 | { | |
ad1443f0 | 2154 | WARN_ONCE(dev_priv->runtime_pm.suspended, |
da5827c3 ID |
2155 | "Device suspended during HW access\n"); |
2156 | } | |
2157 | ||
2158 | static inline void | |
2159 | assert_rpm_wakelock_held(struct drm_i915_private *dev_priv) | |
2160 | { | |
2161 | assert_rpm_device_not_suspended(dev_priv); | |
ad1443f0 | 2162 | WARN_ONCE(!atomic_read(&dev_priv->runtime_pm.wakeref_count), |
1f58c8e7 | 2163 | "RPM wakelock ref not held during HW access"); |
da5827c3 ID |
2164 | } |
2165 | ||
1f814dac ID |
2166 | /** |
2167 | * disable_rpm_wakeref_asserts - disable the RPM assert checks | |
2168 | * @dev_priv: i915 device instance | |
2169 | * | |
2170 | * This function disable asserts that check if we hold an RPM wakelock | |
2171 | * reference, while keeping the device-not-suspended checks still enabled. | |
2172 | * It's meant to be used only in special circumstances where our rule about | |
2173 | * the wakelock refcount wrt. the device power state doesn't hold. According | |
2174 | * to this rule at any point where we access the HW or want to keep the HW in | |
2175 | * an active state we must hold an RPM wakelock reference acquired via one of | |
2176 | * the intel_runtime_pm_get() helpers. Currently there are a few special spots | |
2177 | * where this rule doesn't hold: the IRQ and suspend/resume handlers, the | |
2178 | * forcewake release timer, and the GPU RPS and hangcheck works. All other | |
2179 | * users should avoid using this function. | |
2180 | * | |
2181 | * Any calls to this function must have a symmetric call to | |
2182 | * enable_rpm_wakeref_asserts(). | |
2183 | */ | |
2184 | static inline void | |
2185 | disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv) | |
2186 | { | |
ad1443f0 | 2187 | atomic_inc(&dev_priv->runtime_pm.wakeref_count); |
1f814dac ID |
2188 | } |
2189 | ||
2190 | /** | |
2191 | * enable_rpm_wakeref_asserts - re-enable the RPM assert checks | |
2192 | * @dev_priv: i915 device instance | |
2193 | * | |
2194 | * This function re-enables the RPM assert checks after disabling them with | |
2195 | * disable_rpm_wakeref_asserts. It's meant to be used only in special | |
2196 | * circumstances otherwise its use should be avoided. | |
2197 | * | |
2198 | * Any calls to this function must have a symmetric call to | |
2199 | * disable_rpm_wakeref_asserts(). | |
2200 | */ | |
2201 | static inline void | |
2202 | enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv) | |
2203 | { | |
ad1443f0 | 2204 | atomic_dec(&dev_priv->runtime_pm.wakeref_count); |
1f814dac ID |
2205 | } |
2206 | ||
9c065a7d | 2207 | void intel_runtime_pm_get(struct drm_i915_private *dev_priv); |
09731280 | 2208 | bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv); |
9c065a7d DV |
2209 | void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv); |
2210 | void intel_runtime_pm_put(struct drm_i915_private *dev_priv); | |
2211 | ||
e0fce78f VS |
2212 | void chv_phy_powergate_lanes(struct intel_encoder *encoder, |
2213 | bool override, unsigned int mask); | |
b0b33846 VS |
2214 | bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, |
2215 | enum dpio_channel ch, bool override); | |
e0fce78f VS |
2216 | |
2217 | ||
5f1aae65 | 2218 | /* intel_pm.c */ |
46f16e63 | 2219 | void intel_init_clock_gating(struct drm_i915_private *dev_priv); |
712bf364 | 2220 | void intel_suspend_hw(struct drm_i915_private *dev_priv); |
5db94019 | 2221 | int ilk_wm_max_level(const struct drm_i915_private *dev_priv); |
432081bc | 2222 | void intel_update_watermarks(struct intel_crtc *crtc); |
62d75df7 | 2223 | void intel_init_pm(struct drm_i915_private *dev_priv); |
bb400da9 | 2224 | void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv); |
192aa181 | 2225 | void intel_pm_setup(struct drm_i915_private *dev_priv); |
87440425 PZ |
2226 | void intel_gpu_ips_init(struct drm_i915_private *dev_priv); |
2227 | void intel_gpu_ips_teardown(void); | |
dc97997a | 2228 | void intel_init_gt_powersave(struct drm_i915_private *dev_priv); |
54b4f68f CW |
2229 | void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv); |
2230 | void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv); | |
dc97997a CW |
2231 | void intel_enable_gt_powersave(struct drm_i915_private *dev_priv); |
2232 | void intel_disable_gt_powersave(struct drm_i915_private *dev_priv); | |
54b4f68f | 2233 | void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv); |
43cf3bf0 CW |
2234 | void gen6_rps_busy(struct drm_i915_private *dev_priv); |
2235 | void gen6_rps_reset_ei(struct drm_i915_private *dev_priv); | |
076e29f2 | 2236 | void gen6_rps_idle(struct drm_i915_private *dev_priv); |
e61e0f51 | 2237 | void gen6_rps_boost(struct i915_request *rq, struct intel_rps_client *rps); |
04548cba | 2238 | void g4x_wm_get_hw_state(struct drm_device *dev); |
6eb1a681 | 2239 | void vlv_wm_get_hw_state(struct drm_device *dev); |
243e6a44 | 2240 | void ilk_wm_get_hw_state(struct drm_device *dev); |
3078999f | 2241 | void skl_wm_get_hw_state(struct drm_device *dev); |
ff43bc37 VS |
2242 | void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc, |
2243 | struct skl_ddb_entry *ddb_y, | |
2244 | struct skl_ddb_entry *ddb_uv); | |
08db6652 DL |
2245 | void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, |
2246 | struct skl_ddb_allocation *ddb /* out */); | |
bf9d99ad | 2247 | void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc, |
2248 | struct skl_pipe_wm *out); | |
04548cba | 2249 | void g4x_wm_sanitize(struct drm_i915_private *dev_priv); |
602ae835 | 2250 | void vlv_wm_sanitize(struct drm_i915_private *dev_priv); |
16dcdc4e PZ |
2251 | bool intel_can_enable_sagv(struct drm_atomic_state *state); |
2252 | int intel_enable_sagv(struct drm_i915_private *dev_priv); | |
2253 | int intel_disable_sagv(struct drm_i915_private *dev_priv); | |
45ece230 | 2254 | bool skl_wm_level_equals(const struct skl_wm_level *l1, |
2255 | const struct skl_wm_level *l2); | |
53cc6880 VS |
2256 | bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb, |
2257 | const struct skl_ddb_entry entries[], | |
2258 | int num_entries, int ignore_idx); | |
ff43bc37 VS |
2259 | void skl_write_plane_wm(struct intel_plane *plane, |
2260 | const struct intel_crtc_state *crtc_state); | |
2261 | void skl_write_cursor_wm(struct intel_plane *plane, | |
2262 | const struct intel_crtc_state *crtc_state); | |
ed4a6a7c | 2263 | bool ilk_disable_lp_wm(struct drm_device *dev); |
73b0ca8e MK |
2264 | int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc, |
2265 | struct intel_crtc_state *cstate); | |
2503a0fe KM |
2266 | void intel_init_ipc(struct drm_i915_private *dev_priv); |
2267 | void intel_enable_ipc(struct drm_i915_private *dev_priv); | |
72662e10 | 2268 | |
5f1aae65 | 2269 | /* intel_sdvo.c */ |
76203467 VS |
2270 | bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv, |
2271 | i915_reg_t sdvo_reg, enum pipe *pipe); | |
c39055b0 | 2272 | bool intel_sdvo_init(struct drm_i915_private *dev_priv, |
f0f59a00 | 2273 | i915_reg_t reg, enum port port); |
96a02917 | 2274 | |
2b28bb1b | 2275 | |
5f1aae65 | 2276 | /* intel_sprite.c */ |
dfd2e9ab VS |
2277 | int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode, |
2278 | int usecs); | |
580503c7 | 2279 | struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv, |
b079bd17 | 2280 | enum pipe pipe, int plane); |
6a20fe7b VS |
2281 | int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data, |
2282 | struct drm_file *file_priv); | |
d3a8fb32 VS |
2283 | void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state); |
2284 | void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state); | |
fc3fed5d | 2285 | int intel_plane_check_stride(const struct intel_plane_state *plane_state); |
4e0b83a5 | 2286 | int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state); |
25721f82 | 2287 | int chv_plane_check_rotation(const struct intel_plane_state *plane_state); |
b7c80600 VS |
2288 | struct intel_plane * |
2289 | skl_universal_plane_create(struct drm_i915_private *dev_priv, | |
2290 | enum pipe pipe, enum plane_id plane_id); | |
5f1aae65 | 2291 | |
1ab554b0 ML |
2292 | static inline bool icl_is_nv12_y_plane(enum plane_id id) |
2293 | { | |
2294 | /* Don't need to do a gen check, these planes are only available on gen11 */ | |
2295 | if (id == PLANE_SPRITE4 || id == PLANE_SPRITE5) | |
2296 | return true; | |
2297 | ||
2298 | return false; | |
2299 | } | |
2300 | ||
b1554e23 ML |
2301 | static inline bool icl_is_hdr_plane(struct intel_plane *plane) |
2302 | { | |
2303 | if (INTEL_GEN(to_i915(plane->base.dev)) < 11) | |
2304 | return false; | |
2305 | ||
2306 | return plane->id < PLANE_SPRITE2; | |
2307 | } | |
2308 | ||
5f1aae65 | 2309 | /* intel_tv.c */ |
c39055b0 | 2310 | void intel_tv_init(struct drm_i915_private *dev_priv); |
20ddf665 | 2311 | |
ea2c67bb | 2312 | /* intel_atomic.c */ |
11c1a9ec ML |
2313 | int intel_digital_connector_atomic_get_property(struct drm_connector *connector, |
2314 | const struct drm_connector_state *state, | |
2315 | struct drm_property *property, | |
2316 | uint64_t *val); | |
2317 | int intel_digital_connector_atomic_set_property(struct drm_connector *connector, | |
2318 | struct drm_connector_state *state, | |
2319 | struct drm_property *property, | |
2320 | uint64_t val); | |
2321 | int intel_digital_connector_atomic_check(struct drm_connector *conn, | |
2322 | struct drm_connector_state *new_state); | |
2323 | struct drm_connector_state * | |
2324 | intel_digital_connector_duplicate_state(struct drm_connector *connector); | |
2325 | ||
1356837e MR |
2326 | struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc); |
2327 | void intel_crtc_destroy_state(struct drm_crtc *crtc, | |
2328 | struct drm_crtc_state *state); | |
de419ab6 ML |
2329 | struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev); |
2330 | void intel_atomic_state_clear(struct drm_atomic_state *); | |
de419ab6 | 2331 | |
10f81c19 ACO |
2332 | static inline struct intel_crtc_state * |
2333 | intel_atomic_get_crtc_state(struct drm_atomic_state *state, | |
2334 | struct intel_crtc *crtc) | |
2335 | { | |
2336 | struct drm_crtc_state *crtc_state; | |
2337 | crtc_state = drm_atomic_get_crtc_state(state, &crtc->base); | |
2338 | if (IS_ERR(crtc_state)) | |
0b6cc188 | 2339 | return ERR_CAST(crtc_state); |
10f81c19 ACO |
2340 | |
2341 | return to_intel_crtc_state(crtc_state); | |
2342 | } | |
e3bddded | 2343 | |
6ebc6923 ACO |
2344 | int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv, |
2345 | struct intel_crtc *intel_crtc, | |
2346 | struct intel_crtc_state *crtc_state); | |
5ee67f1c MR |
2347 | |
2348 | /* intel_atomic_plane.c */ | |
87b94026 ML |
2349 | struct intel_plane *intel_plane_alloc(void); |
2350 | void intel_plane_free(struct intel_plane *plane); | |
ea2c67bb MR |
2351 | struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane); |
2352 | void intel_plane_destroy_state(struct drm_plane *plane, | |
2353 | struct drm_plane_state *state); | |
2354 | extern const struct drm_plane_helper_funcs intel_plane_helper_funcs; | |
5f2e5112 VS |
2355 | void skl_update_planes_on_crtc(struct intel_atomic_state *state, |
2356 | struct intel_crtc *crtc); | |
2357 | void i9xx_update_planes_on_crtc(struct intel_atomic_state *state, | |
2358 | struct intel_crtc *crtc); | |
b2b55502 VS |
2359 | int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state, |
2360 | struct intel_crtc_state *crtc_state, | |
2361 | const struct intel_plane_state *old_plane_state, | |
f79f2692 | 2362 | struct intel_plane_state *intel_state); |
ea2c67bb | 2363 | |
8563b1e8 LL |
2364 | /* intel_color.c */ |
2365 | void intel_color_init(struct drm_crtc *crtc); | |
82cf435b | 2366 | int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state); |
b95c5321 ML |
2367 | void intel_color_set_csc(struct drm_crtc_state *crtc_state); |
2368 | void intel_color_load_luts(struct drm_crtc_state *crtc_state); | |
8563b1e8 | 2369 | |
dbe9e61b SS |
2370 | /* intel_lspcon.c */ |
2371 | bool lspcon_init(struct intel_digital_port *intel_dig_port); | |
910530c0 | 2372 | void lspcon_resume(struct intel_lspcon *lspcon); |
357c0ae9 | 2373 | void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon); |
7cbf19fd SS |
2374 | void lspcon_write_infoframe(struct intel_encoder *encoder, |
2375 | const struct intel_crtc_state *crtc_state, | |
2376 | unsigned int type, | |
2377 | const void *buf, ssize_t len); | |
06c812d7 SS |
2378 | void lspcon_set_infoframes(struct intel_encoder *encoder, |
2379 | bool enable, | |
2380 | const struct intel_crtc_state *crtc_state, | |
2381 | const struct drm_connector_state *conn_state); | |
2382 | bool lspcon_infoframe_enabled(struct intel_encoder *encoder, | |
2383 | const struct intel_crtc_state *pipe_config); | |
668b6c17 SS |
2384 | void lspcon_ycbcr420_config(struct drm_connector *connector, |
2385 | struct intel_crtc_state *crtc_state); | |
731035fe TV |
2386 | |
2387 | /* intel_pipe_crc.c */ | |
8c6b709d | 2388 | #ifdef CONFIG_DEBUG_FS |
c0811a7d | 2389 | int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name); |
a8c20833 MK |
2390 | int intel_crtc_verify_crc_source(struct drm_crtc *crtc, |
2391 | const char *source_name, size_t *values_cnt); | |
260bc551 MK |
2392 | const char *const *intel_crtc_get_crc_sources(struct drm_crtc *crtc, |
2393 | size_t *count); | |
033b7a23 ML |
2394 | void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc); |
2395 | void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc); | |
8c6b709d TV |
2396 | #else |
2397 | #define intel_crtc_set_crc_source NULL | |
a8c20833 | 2398 | #define intel_crtc_verify_crc_source NULL |
260bc551 | 2399 | #define intel_crtc_get_crc_sources NULL |
033b7a23 ML |
2400 | static inline void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc) |
2401 | { | |
2402 | } | |
2403 | ||
2404 | static inline void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc) | |
2405 | { | |
2406 | } | |
8c6b709d | 2407 | #endif |
79e53945 | 2408 | #endif /* __INTEL_DRV_H__ */ |