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drm/i915: don't call Haswell PCH code when we can't or don't need
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_drv.h
CommitLineData
79e53945
JB		 1/*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 */
25#ifndef __INTEL_DRV_H__
26#define __INTEL_DRV_H__
27
28#include <linux/i2c.h>
760285e7 29#include <drm/i915_drm.h>
80824003 30#include "i915_drv.h"
760285e7
DH		 31#include <drm/drm_crtc.h>
32#include <drm/drm_crtc_helper.h>
33#include <drm/drm_fb_helper.h>
612a9aab 34#include <drm/drm_dp_helper.h>
913d8d11 35
481b6af3 36#define _wait_for(COND, MS, W) ({ \
913d8d11
CW		 37 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
38 int ret__ = 0; \
0206e353 39 while (!(COND)) { \
913d8d11
CW		 40 if (time_after(jiffies, timeout__)) { \
41 ret__ = -ETIMEDOUT; \
42 break; \
43 } \
0cc2764c
BW		 44 if (W && drm_can_sleep()) { \
45 msleep(W); \
46 } else { \
47 cpu_relax(); \
48 } \
913d8d11
CW		 49 } \
50 ret__; \
51})
52
57f350b6 53#define wait_for_atomic_us(COND, US) ({ \
bcf9dcc1
CW		 54 unsigned long timeout__ = jiffies + usecs_to_jiffies(US); \
55 int ret__ = 0; \
56 while (!(COND)) { \
57 if (time_after(jiffies, timeout__)) { \
58 ret__ = -ETIMEDOUT; \
59 break; \
60 } \
61 cpu_relax(); \
62 } \
63 ret__; \
57f350b6
JB		 64})
65
481b6af3
CW		 66#define wait_for(COND, MS) _wait_for(COND, MS, 1)
67#define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
68
021357ac
CW		 69#define KHz(x) (1000*x)
70#define MHz(x) KHz(1000*x)
71
79e53945
JB		 72/*
73 * Display related stuff
74 */
75
76/* store information about an Ixxx DVO */
77/* The i830->i865 use multiple DVOs with multiple i2cs */
78/* the i915, i945 have a single sDVO i2c bus - which is different */
79#define MAX_OUTPUTS 6
80/* maximum connectors per crtcs in the mode set */
81#define INTELFB_CONN_LIMIT 4
82
83#define INTEL_I2C_BUS_DVO 1
84#define INTEL_I2C_BUS_SDVO 2
85
86/* these are outputs from the chip - integrated only
87 external chips are via DVO or SDVO output */
88#define INTEL_OUTPUT_UNUSED 0
89#define INTEL_OUTPUT_ANALOG 1
90#define INTEL_OUTPUT_DVO 2
91#define INTEL_OUTPUT_SDVO 3
92#define INTEL_OUTPUT_LVDS 4
93#define INTEL_OUTPUT_TVOUT 5
7d57382e 94#define INTEL_OUTPUT_HDMI 6
a4fc5ed6 95#define INTEL_OUTPUT_DISPLAYPORT 7
32f9d658 96#define INTEL_OUTPUT_EDP 8
79e53945
JB		 97
98#define INTEL_DVO_CHIP_NONE 0
99#define INTEL_DVO_CHIP_LVDS 1
100#define INTEL_DVO_CHIP_TMDS 2
101#define INTEL_DVO_CHIP_TVOUT 4
102
6c9547ff
CW		 103/* drm_display_mode->private_flags */
104#define INTEL_MODE_PIXEL_MULTIPLIER_SHIFT (0x0)
105#define INTEL_MODE_PIXEL_MULTIPLIER_MASK (0xf << INTEL_MODE_PIXEL_MULTIPLIER_SHIFT)
3b5c78a3 106#define INTEL_MODE_DP_FORCE_6BPC (0x10)
f9bef081
DV		 107/* This flag must be set by the encoder's mode_fixup if it changes the crtc
108 * timings in the mode to prevent the crtc fixup from overwriting them.
109 * Currently only lvds needs that. */
110#define INTEL_MODE_CRTC_TIMINGS_SET (0x20)
6c9547ff
CW		 111
112static inline void
113intel_mode_set_pixel_multiplier(struct drm_display_mode *mode,
114 int multiplier)
115{
116 mode->clock *= multiplier;
117 mode->private_flags |= multiplier;
118}
119
120static inline int
121intel_mode_get_pixel_multiplier(const struct drm_display_mode *mode)
122{
123 return (mode->private_flags & INTEL_MODE_PIXEL_MULTIPLIER_MASK) >> INTEL_MODE_PIXEL_MULTIPLIER_SHIFT;
124}
125
79e53945
JB		 126struct intel_framebuffer {
127 struct drm_framebuffer base;
05394f39 128 struct drm_i915_gem_object *obj;
79e53945
JB		 129};
130
37811fcc
CW		 131struct intel_fbdev {
132 struct drm_fb_helper helper;
133 struct intel_framebuffer ifb;
134 struct list_head fbdev_list;
135 struct drm_display_mode *our_mode;
136};
79e53945 137
21d40d37 138struct intel_encoder {
4ef69c7a 139 struct drm_encoder base;
9a935856
DV		 140 /*
141 * The new crtc this encoder will be driven from. Only differs from
142 * base->crtc while a modeset is in progress.
143 */
144 struct intel_crtc *new_crtc;
145
79e53945 146 int type;
e2f0ba97 147 bool needs_tv_clock;
66a9278e
DV		 148 /*
149 * Intel hw has only one MUX where encoders could be clone, hence a
150 * simple flag is enough to compute the possible_clones mask.
151 */
152 bool cloneable;
5ab432ef 153 bool connectors_active;
21d40d37 154 void (*hot_plug)(struct intel_encoder *);
bf49ec8c 155 void (*pre_enable)(struct intel_encoder *);
ef9c3aee
DV		 156 void (*enable)(struct intel_encoder *);
157 void (*disable)(struct intel_encoder *);
bf49ec8c 158 void (*post_disable)(struct intel_encoder *);
f0947c37
DV		 159 /* Read out the current hw state of this connector, returning true if
160 * the encoder is active. If the encoder is enabled it also set the pipe
161 * it is connected to in the pipe parameter. */
162 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
f8aed700 163 int crtc_mask;
79e53945
JB		 164};
165
1d508706 166struct intel_panel {
dd06f90e 167 struct drm_display_mode *fixed_mode;
1d508706
JN		 168};
169
5daa55eb
ZW		 170struct intel_connector {
171 struct drm_connector base;
9a935856
DV		 172 /*
173 * The fixed encoder this connector is connected to.
174 */
df0e9248 175 struct intel_encoder *encoder;
9a935856
DV		 176
177 /*
178 * The new encoder this connector will be driven. Only differs from
179 * encoder while a modeset is in progress.
180 */
181 struct intel_encoder *new_encoder;
182
f0947c37
DV		 183 /* Reads out the current hw, returning true if the connector is enabled
184 * and active (i.e. dpms ON state). */
185 bool (*get_hw_state)(struct intel_connector *);
1d508706
JN		 186
187 /* Panel info for eDP and LVDS */
188 struct intel_panel panel;
9cd300e0
JN		 189
190 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
191 struct edid *edid;
5daa55eb
ZW		 192};
193
79e53945
JB		 194struct intel_crtc {
195 struct drm_crtc base;
80824003
JB		 196 enum pipe pipe;
197 enum plane plane;
79e53945 198 u8 lut_r[256], lut_g[256], lut_b[256];
08a48469
DV		 199 /*
200 * Whether the crtc and the connected output pipeline is active. Implies
201 * that crtc->enabled is set, i.e. the current mode configuration has
202 * some outputs connected to this crtc.
08a48469
DV		 203 */
204 bool active;
93314b5b 205 bool primary_disabled; /* is the crtc obscured by a plane? */
652c393a 206 bool lowfreq_avail;
02e792fb 207 struct intel_overlay *overlay;
6b95a207 208 struct intel_unpin_work *unpin_work;
77ffb597 209 int fdi_lanes;
cda4b7d3 210
e506a0c6
DV		 211 /* Display surface base address adjustement for pageflips. Note that on
212 * gen4+ this only adjusts up to a tile, offsets within a tile are
213 * handled in the hw itself (with the TILEOFF register). */
214 unsigned long dspaddr_offset;
215
05394f39 216 struct drm_i915_gem_object *cursor_bo;
cda4b7d3
CW		 217 uint32_t cursor_addr;
218 int16_t cursor_x, cursor_y;
219 int16_t cursor_width, cursor_height;
6b383a7f 220 bool cursor_visible;
5a354204 221 unsigned int bpp;
4b645f14 222
ee7b9f93
JB		 223 /* We can share PLLs across outputs if the timings match */
224 struct intel_pch_pll *pch_pll;
6441ab5f 225 uint32_t ddi_pll_sel;
79e53945
JB		 226};
227
b840d907
JB		 228struct intel_plane {
229 struct drm_plane base;
230 enum pipe pipe;
231 struct drm_i915_gem_object *obj;
2d354c34 232 bool can_scale;
b840d907
JB		 233 int max_downscale;
234 u32 lut_r[1024], lut_g[1024], lut_b[1024];
235 void (*update_plane)(struct drm_plane *plane,
236 struct drm_framebuffer *fb,
237 struct drm_i915_gem_object *obj,
238 int crtc_x, int crtc_y,
239 unsigned int crtc_w, unsigned int crtc_h,
240 uint32_t x, uint32_t y,
241 uint32_t src_w, uint32_t src_h);
242 void (*disable_plane)(struct drm_plane *plane);
8ea30864
JB		 243 int (*update_colorkey)(struct drm_plane *plane,
244 struct drm_intel_sprite_colorkey *key);
245 void (*get_colorkey)(struct drm_plane *plane,
246 struct drm_intel_sprite_colorkey *key);
b840d907
JB		 247};
248
b445e3b0
ED		 249struct intel_watermark_params {
250 unsigned long fifo_size;
251 unsigned long max_wm;
252 unsigned long default_wm;
253 unsigned long guard_size;
254 unsigned long cacheline_size;
255};
256
257struct cxsr_latency {
258 int is_desktop;
259 int is_ddr3;
260 unsigned long fsb_freq;
261 unsigned long mem_freq;
262 unsigned long display_sr;
263 unsigned long display_hpll_disable;
264 unsigned long cursor_sr;
265 unsigned long cursor_hpll_disable;
266};
267
79e53945 268#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
5daa55eb 269#define to_intel_connector(x) container_of(x, struct intel_connector, base)
4ef69c7a 270#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
79e53945 271#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
b840d907 272#define to_intel_plane(x) container_of(x, struct intel_plane, base)
79e53945 273
45187ace
JB		 274#define DIP_HEADER_SIZE 5
275
3c17fe4b
DH		 276#define DIP_TYPE_AVI 0x82
277#define DIP_VERSION_AVI 0x2
278#define DIP_LEN_AVI 13
c846b619
PZ		 279#define DIP_AVI_PR_1 0
280#define DIP_AVI_PR_2 1
3c17fe4b 281
26005210 282#define DIP_TYPE_SPD 0x83
c0864cb3
JB		 283#define DIP_VERSION_SPD 0x1
284#define DIP_LEN_SPD 25
285#define DIP_SPD_UNKNOWN 0
286#define DIP_SPD_DSTB 0x1
287#define DIP_SPD_DVDP 0x2
288#define DIP_SPD_DVHS 0x3
289#define DIP_SPD_HDDVR 0x4
290#define DIP_SPD_DVC 0x5
291#define DIP_SPD_DSC 0x6
292#define DIP_SPD_VCD 0x7
293#define DIP_SPD_GAME 0x8
294#define DIP_SPD_PC 0x9
295#define DIP_SPD_BD 0xa
296#define DIP_SPD_SCD 0xb
297
3c17fe4b
DH		 298struct dip_infoframe {
299 uint8_t type; /* HB0 */
300 uint8_t ver; /* HB1 */
301 uint8_t len; /* HB2 - body len, not including checksum */
302 uint8_t ecc; /* Header ECC */
303 uint8_t checksum; /* PB0 */
304 union {
305 struct {
306 /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */
307 uint8_t Y_A_B_S;
308 /* PB2 - C 7:6, M 5:4, R 3:0 */
309 uint8_t C_M_R;
310 /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */
311 uint8_t ITC_EC_Q_SC;
312 /* PB4 - VIC 6:0 */
313 uint8_t VIC;
0aa534df
PZ		 314 /* PB5 - YQ 7:6, CN 5:4, PR 3:0 */
315 uint8_t YQ_CN_PR;
3c17fe4b
DH		 316 /* PB6 to PB13 */
317 uint16_t top_bar_end;
318 uint16_t bottom_bar_start;
319 uint16_t left_bar_end;
320 uint16_t right_bar_start;
81014b9d 321 } __attribute__ ((packed)) avi;
c0864cb3
JB		 322 struct {
323 uint8_t vn[8];
324 uint8_t pd[16];
325 uint8_t sdi;
81014b9d 326 } __attribute__ ((packed)) spd;
3c17fe4b
DH		 327 uint8_t payload[27];
328 } __attribute__ ((packed)) body;
329} __attribute__((packed));
330
f5bbfca3
ED		 331struct intel_hdmi {
332 struct intel_encoder base;
333 u32 sdvox_reg;
334 int ddc_bus;
335 int ddi_port;
336 uint32_t color_range;
337 bool has_hdmi_sink;
338 bool has_audio;
339 enum hdmi_force_audio force_audio;
340 void (*write_infoframe)(struct drm_encoder *encoder,
341 struct dip_infoframe *frame);
687f4d06
PZ		 342 void (*set_infoframes)(struct drm_encoder *encoder,
343 struct drm_display_mode *adjusted_mode);
f5bbfca3
ED		 344};
345
b091cd92 346#define DP_MAX_DOWNSTREAM_PORTS 0x10
54d63ca6
SK		 347#define DP_LINK_CONFIGURATION_SIZE 9
348
349struct intel_dp {
350 struct intel_encoder base;
351 uint32_t output_reg;
352 uint32_t DP;
353 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
354 bool has_audio;
355 enum hdmi_force_audio force_audio;
ab9d7c30 356 enum port port;
54d63ca6 357 uint32_t color_range;
54d63ca6
SK		 358 uint8_t link_bw;
359 uint8_t lane_count;
360 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
b091cd92 361 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
54d63ca6
SK		 362 struct i2c_adapter adapter;
363 struct i2c_algo_dp_aux_data algo;
364 bool is_pch_edp;
365 uint8_t train_set[4];
366 int panel_power_up_delay;
367 int panel_power_down_delay;
368 int panel_power_cycle_delay;
369 int backlight_on_delay;
370 int backlight_off_delay;
54d63ca6
SK		 371 struct delayed_work panel_vdd_work;
372 bool want_panel_vdd;
dd06f90e 373 struct intel_connector *attached_connector;
54d63ca6
SK		 374};
375
f875c15a
CW		 376static inline struct drm_crtc *
377intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
378{
379 struct drm_i915_private *dev_priv = dev->dev_private;
380 return dev_priv->pipe_to_crtc_mapping[pipe];
381}
382
417ae147
CW		 383static inline struct drm_crtc *
384intel_get_crtc_for_plane(struct drm_device *dev, int plane)
385{
386 struct drm_i915_private *dev_priv = dev->dev_private;
387 return dev_priv->plane_to_crtc_mapping[plane];
388}
389
4e5359cd
SF		 390struct intel_unpin_work {
391 struct work_struct work;
392 struct drm_device *dev;
05394f39
CW		 393 struct drm_i915_gem_object *old_fb_obj;
394 struct drm_i915_gem_object *pending_flip_obj;
4e5359cd
SF		 395 struct drm_pending_vblank_event *event;
396 int pending;
397 bool enable_stall_check;
398};
399
1630fe75
CW		 400struct intel_fbc_work {
401 struct delayed_work work;
402 struct drm_crtc *crtc;
403 struct drm_framebuffer *fb;
404 int interval;
405};
406
d2acd215
DV		 407int intel_pch_rawclk(struct drm_device *dev);
408
4eab8136
JN		 409int intel_connector_update_modes(struct drm_connector *connector,
410 struct edid *edid);
335af9a2 411int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
f0217c42 412
3f43c48d 413extern void intel_attach_force_audio_property(struct drm_connector *connector);
e953fd7b
CW		 414extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
415
79e53945 416extern void intel_crt_init(struct drm_device *dev);
08d644ad
DV		 417extern void intel_hdmi_init(struct drm_device *dev,
418 int sdvox_reg, enum port port);
f5bbfca3 419extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
f5bbfca3 420extern void intel_dip_infoframe_csum(struct dip_infoframe *avi_if);
eef4eacb
DV		 421extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg,
422 bool is_sdvob);
79e53945
JB		 423extern void intel_dvo_init(struct drm_device *dev);
424extern void intel_tv_init(struct drm_device *dev);
f047e395
CW		 425extern void intel_mark_busy(struct drm_device *dev);
426extern void intel_mark_idle(struct drm_device *dev);
427extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj);
428extern void intel_mark_fb_idle(struct drm_i915_gem_object *obj);
c5d1b51d 429extern bool intel_lvds_init(struct drm_device *dev);
ab9d7c30
PZ		 430extern void intel_dp_init(struct drm_device *dev, int output_reg,
431 enum port port);
a4fc5ed6
KP		 432void
433intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
434 struct drm_display_mode *adjusted_mode);
247d89f6 435extern void intel_dp_init_link_config(struct intel_dp *intel_dp);
c19b0669
PZ		 436extern void intel_dp_start_link_train(struct intel_dp *intel_dp);
437extern void intel_dp_complete_link_train(struct intel_dp *intel_dp);
438extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
cb0953d7 439extern bool intel_dpd_is_edp(struct drm_device *dev);
0206e353 440extern void intel_edp_link_config(struct intel_encoder *, int *, int *);
94bf2ced
DV		 441extern int intel_edp_target_clock(struct intel_encoder *,
442 struct drm_display_mode *mode);
814948ad 443extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder);
b840d907 444extern int intel_plane_init(struct drm_device *dev, enum pipe pipe);
6f1d69b0
ED		 445extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
446 enum plane plane);
32f9d658 447
a9573556 448/* intel_panel.c */
dd06f90e
JN		 449extern int intel_panel_init(struct intel_panel *panel,
450 struct drm_display_mode *fixed_mode);
1d508706
JN		 451extern void intel_panel_fini(struct intel_panel *panel);
452
1d8e1c75
CW		 453extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
454 struct drm_display_mode *adjusted_mode);
455extern void intel_pch_panel_fitting(struct drm_device *dev,
456 int fitting_mode,
cb1793ce 457 const struct drm_display_mode *mode,
1d8e1c75 458 struct drm_display_mode *adjusted_mode);
a9573556 459extern u32 intel_panel_get_max_backlight(struct drm_device *dev);
a9573556 460extern void intel_panel_set_backlight(struct drm_device *dev, u32 level);
0657b6b1 461extern int intel_panel_setup_backlight(struct drm_connector *connector);
24ded204
DV		 462extern void intel_panel_enable_backlight(struct drm_device *dev,
463 enum pipe pipe);
47356eb6 464extern void intel_panel_disable_backlight(struct drm_device *dev);
aaa6fd2a 465extern void intel_panel_destroy_backlight(struct drm_device *dev);
fe16d949 466extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1d8e1c75 467
d9e55608 468struct intel_set_config {
1aa4b628
DV		 469 struct drm_encoder **save_connector_encoders;
470 struct drm_crtc **save_encoder_crtcs;
5e2b584e
DV		 471
472 bool fb_changed;
473 bool mode_changed;
d9e55608
DV		 474};
475
a6778b3c
DV		 476extern bool intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
477 int x, int y, struct drm_framebuffer *old_fb);
a261b246 478extern void intel_modeset_disable(struct drm_device *dev);
79e53945 479extern void intel_crtc_load_lut(struct drm_crtc *crtc);
b2cabb0e 480extern void intel_crtc_update_dpms(struct drm_crtc *crtc);
1f703855 481extern void intel_encoder_noop(struct drm_encoder *encoder);
ea5b213a 482extern void intel_encoder_destroy(struct drm_encoder *encoder);
5ab432ef 483extern void intel_encoder_dpms(struct intel_encoder *encoder, int mode);
6ed0f796 484extern bool intel_encoder_check_is_cloned(struct intel_encoder *encoder);
5ab432ef 485extern void intel_connector_dpms(struct drm_connector *, int mode);
f0947c37 486extern bool intel_connector_get_hw_state(struct intel_connector *connector);
b980514c
DV		 487extern void intel_modeset_check_state(struct drm_device *dev);
488
79e53945 489
df0e9248
CW		 490static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector)
491{
492 return to_intel_connector(connector)->encoder;
493}
494
7739c33b
PZ		 495static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
496{
497 return container_of(encoder, struct intel_dp, base.base);
498}
499
df0e9248
CW		 500extern void intel_connector_attach_encoder(struct intel_connector *connector,
501 struct intel_encoder *encoder);
502extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
79e53945
JB		 503
504extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
505 struct drm_crtc *crtc);
08d7b3d1
CW		 506int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
507 struct drm_file *file_priv);
9d0498a2 508extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
58e10eb9 509extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
8261b191
CW		 510
511struct intel_load_detect_pipe {
d2dff872 512 struct drm_framebuffer *release_fb;
8261b191
CW		 513 bool load_detect_temp;
514 int dpms_mode;
515};
d2434ab7 516extern bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 517 struct drm_display_mode *mode,
8261b191 518 struct intel_load_detect_pipe *old);
d2434ab7 519extern void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 520 struct intel_load_detect_pipe *old);
79e53945 521
79e53945
JB		 522extern void intelfb_restore(void);
523extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
524 u16 blue, int regno);
b8c00ac5
DA		 525extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
526 u16 *blue, int regno);
0cdab21f 527extern void intel_enable_clock_gating(struct drm_device *dev);
79e53945 528
127bd2ac 529extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 530 struct drm_i915_gem_object *obj,
919926ae 531 struct intel_ring_buffer *pipelined);
1690e1eb 532extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
127bd2ac 533
38651674
DA		 534extern int intel_framebuffer_init(struct drm_device *dev,
535 struct intel_framebuffer *ifb,
308e5bcb 536 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 537 struct drm_i915_gem_object *obj);
38651674
DA		 538extern int intel_fbdev_init(struct drm_device *dev);
539extern void intel_fbdev_fini(struct drm_device *dev);
3fa016a0 540extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
6b95a207
KH		 541extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
542extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
1afe3e9d 543extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
6b95a207 544
02e792fb
DV		 545extern void intel_setup_overlay(struct drm_device *dev);
546extern void intel_cleanup_overlay(struct drm_device *dev);
ce453d81 547extern int intel_overlay_switch_off(struct intel_overlay *overlay);
02e792fb
DV		 548extern int intel_overlay_put_image(struct drm_device *dev, void *data,
549 struct drm_file *file_priv);
550extern int intel_overlay_attrs(struct drm_device *dev, void *data,
551 struct drm_file *file_priv);
4abe3520 552
eb1f8e4f 553extern void intel_fb_output_poll_changed(struct drm_device *dev);
e8e7a2b8 554extern void intel_fb_restore_mode(struct drm_device *dev);
645c62a5 555
b840d907
JB		 556extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
557 bool state);
558#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
559#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
560
645c62a5 561extern void intel_init_clock_gating(struct drm_device *dev);
e0dac65e
WF		 562extern void intel_write_eld(struct drm_encoder *encoder,
563 struct drm_display_mode *mode);
d4270e57 564extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
45244b87 565extern void intel_prepare_ddi(struct drm_device *dev);
c82e4d26 566extern void hsw_fdi_link_train(struct drm_crtc *crtc);
0e72a5b5 567extern void intel_ddi_init(struct drm_device *dev, enum port port);
d4270e57 568
b840d907 569/* For use by IVB LP watermark workaround in intel_sprite.c */
f681fa23 570extern void intel_update_watermarks(struct drm_device *dev);
b840d907
JB		 571extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
572 uint32_t sprite_width,
573 int pixel_size);
1f8eeabf
ED		 574extern void intel_update_linetime_watermarks(struct drm_device *dev, int pipe,
575 struct drm_display_mode *mode);
8ea30864
JB		 576
577extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
578 struct drm_file *file_priv);
579extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
580 struct drm_file *file_priv);
581
57f350b6
JB		 582extern u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg);
583
85208be0 584/* Power-related functions, located in intel_pm.c */
1fa61106 585extern void intel_init_pm(struct drm_device *dev);
85208be0 586/* FBC */
85208be0
ED		 587extern bool intel_fbc_enabled(struct drm_device *dev);
588extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
589extern void intel_update_fbc(struct drm_device *dev);
eb48eb00
DV		 590/* IPS */
591extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
592extern void intel_gpu_ips_teardown(void);
85208be0 593
0232e927 594extern void intel_init_power_wells(struct drm_device *dev);
8090c6b9
DV		 595extern void intel_enable_gt_powersave(struct drm_device *dev);
596extern void intel_disable_gt_powersave(struct drm_device *dev);
6590190d 597extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv);
930ebb46 598extern void ironlake_teardown_rc6(struct drm_device *dev);
b3daeaef 599
5ab432ef
DV		 600extern void intel_enable_ddi(struct intel_encoder *encoder);
601extern void intel_disable_ddi(struct intel_encoder *encoder);
85234cdc
DV		 602extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
603 enum pipe *pipe);
72662e10
ED		 604extern void intel_ddi_mode_set(struct drm_encoder *encoder,
605 struct drm_display_mode *mode,
606 struct drm_display_mode *adjusted_mode);
79f689aa 607extern void intel_ddi_pll_init(struct drm_device *dev);
8d9ddbcb
PZ		 608extern void intel_ddi_enable_pipe_func(struct drm_crtc *crtc);
609extern void intel_ddi_disable_pipe_func(struct drm_i915_private *dev_priv,
610 enum pipe pipe);
fc914639
PZ		 611extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
612extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
6441ab5f
PZ		 613extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
614extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock);
615extern void intel_ddi_pre_enable(struct intel_encoder *intel_encoder);
616extern void intel_ddi_post_disable(struct intel_encoder *intel_encoder);
617extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
dae84799 618extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
c19b0669 619extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
72662e10 620
79e53945 621#endif /* __INTEL_DRV_H__ */
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