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drm/i915: Set initial seqno value close to wrap boundary
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_drv.h
CommitLineData
79e53945
JB		 1/*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 */
25#ifndef __INTEL_DRV_H__
26#define __INTEL_DRV_H__
27
28#include <linux/i2c.h>
760285e7 29#include <drm/i915_drm.h>
80824003 30#include "i915_drv.h"
760285e7
DH		 31#include <drm/drm_crtc.h>
32#include <drm/drm_crtc_helper.h>
33#include <drm/drm_fb_helper.h>
612a9aab 34#include <drm/drm_dp_helper.h>
913d8d11 35
481b6af3 36#define _wait_for(COND, MS, W) ({ \
913d8d11
CW		 37 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
38 int ret__ = 0; \
0206e353 39 while (!(COND)) { \
913d8d11
CW		 40 if (time_after(jiffies, timeout__)) { \
41 ret__ = -ETIMEDOUT; \
42 break; \
43 } \
0cc2764c
BW		 44 if (W && drm_can_sleep()) { \
45 msleep(W); \
46 } else { \
47 cpu_relax(); \
48 } \
913d8d11
CW		 49 } \
50 ret__; \
51})
52
57f350b6 53#define wait_for_atomic_us(COND, US) ({ \
bcf9dcc1
CW		 54 unsigned long timeout__ = jiffies + usecs_to_jiffies(US); \
55 int ret__ = 0; \
56 while (!(COND)) { \
57 if (time_after(jiffies, timeout__)) { \
58 ret__ = -ETIMEDOUT; \
59 break; \
60 } \
61 cpu_relax(); \
62 } \
63 ret__; \
57f350b6
JB		 64})
65
481b6af3
CW		 66#define wait_for(COND, MS) _wait_for(COND, MS, 1)
67#define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
68
021357ac
CW		 69#define KHz(x) (1000*x)
70#define MHz(x) KHz(1000*x)
71
79e53945
JB		 72/*
73 * Display related stuff
74 */
75
76/* store information about an Ixxx DVO */
77/* The i830->i865 use multiple DVOs with multiple i2cs */
78/* the i915, i945 have a single sDVO i2c bus - which is different */
79#define MAX_OUTPUTS 6
80/* maximum connectors per crtcs in the mode set */
81#define INTELFB_CONN_LIMIT 4
82
83#define INTEL_I2C_BUS_DVO 1
84#define INTEL_I2C_BUS_SDVO 2
85
86/* these are outputs from the chip - integrated only
87 external chips are via DVO or SDVO output */
88#define INTEL_OUTPUT_UNUSED 0
89#define INTEL_OUTPUT_ANALOG 1
90#define INTEL_OUTPUT_DVO 2
91#define INTEL_OUTPUT_SDVO 3
92#define INTEL_OUTPUT_LVDS 4
93#define INTEL_OUTPUT_TVOUT 5
7d57382e 94#define INTEL_OUTPUT_HDMI 6
a4fc5ed6 95#define INTEL_OUTPUT_DISPLAYPORT 7
32f9d658 96#define INTEL_OUTPUT_EDP 8
00c09d70 97#define INTEL_OUTPUT_UNKNOWN 9
79e53945
JB		 98
99#define INTEL_DVO_CHIP_NONE 0
100#define INTEL_DVO_CHIP_LVDS 1
101#define INTEL_DVO_CHIP_TMDS 2
102#define INTEL_DVO_CHIP_TVOUT 4
103
6c9547ff
CW		 104/* drm_display_mode->private_flags */
105#define INTEL_MODE_PIXEL_MULTIPLIER_SHIFT (0x0)
106#define INTEL_MODE_PIXEL_MULTIPLIER_MASK (0xf << INTEL_MODE_PIXEL_MULTIPLIER_SHIFT)
3b5c78a3 107#define INTEL_MODE_DP_FORCE_6BPC (0x10)
f9bef081
DV		 108/* This flag must be set by the encoder's mode_fixup if it changes the crtc
109 * timings in the mode to prevent the crtc fixup from overwriting them.
110 * Currently only lvds needs that. */
111#define INTEL_MODE_CRTC_TIMINGS_SET (0x20)
6c9547ff
CW		 112
113static inline void
114intel_mode_set_pixel_multiplier(struct drm_display_mode *mode,
115 int multiplier)
116{
117 mode->clock *= multiplier;
118 mode->private_flags |= multiplier;
119}
120
121static inline int
122intel_mode_get_pixel_multiplier(const struct drm_display_mode *mode)
123{
124 return (mode->private_flags & INTEL_MODE_PIXEL_MULTIPLIER_MASK) >> INTEL_MODE_PIXEL_MULTIPLIER_SHIFT;
125}
126
79e53945
JB		 127struct intel_framebuffer {
128 struct drm_framebuffer base;
05394f39 129 struct drm_i915_gem_object *obj;
79e53945
JB		 130};
131
37811fcc
CW		 132struct intel_fbdev {
133 struct drm_fb_helper helper;
134 struct intel_framebuffer ifb;
135 struct list_head fbdev_list;
136 struct drm_display_mode *our_mode;
137};
79e53945 138
21d40d37 139struct intel_encoder {
4ef69c7a 140 struct drm_encoder base;
9a935856
DV		 141 /*
142 * The new crtc this encoder will be driven from. Only differs from
143 * base->crtc while a modeset is in progress.
144 */
145 struct intel_crtc *new_crtc;
146
79e53945 147 int type;
e2f0ba97 148 bool needs_tv_clock;
66a9278e
DV		 149 /*
150 * Intel hw has only one MUX where encoders could be clone, hence a
151 * simple flag is enough to compute the possible_clones mask.
152 */
153 bool cloneable;
5ab432ef 154 bool connectors_active;
21d40d37 155 void (*hot_plug)(struct intel_encoder *);
dafd226c 156 void (*pre_pll_enable)(struct intel_encoder *);
bf49ec8c 157 void (*pre_enable)(struct intel_encoder *);
ef9c3aee
DV		 158 void (*enable)(struct intel_encoder *);
159 void (*disable)(struct intel_encoder *);
bf49ec8c 160 void (*post_disable)(struct intel_encoder *);
f0947c37
DV		 161 /* Read out the current hw state of this connector, returning true if
162 * the encoder is active. If the encoder is enabled it also set the pipe
163 * it is connected to in the pipe parameter. */
164 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
f8aed700 165 int crtc_mask;
79e53945
JB		 166};
167
1d508706 168struct intel_panel {
dd06f90e 169 struct drm_display_mode *fixed_mode;
4d891523 170 int fitting_mode;
1d508706
JN		 171};
172
5daa55eb
ZW		 173struct intel_connector {
174 struct drm_connector base;
9a935856
DV		 175 /*
176 * The fixed encoder this connector is connected to.
177 */
df0e9248 178 struct intel_encoder *encoder;
9a935856
DV		 179
180 /*
181 * The new encoder this connector will be driven. Only differs from
182 * encoder while a modeset is in progress.
183 */
184 struct intel_encoder *new_encoder;
185
f0947c37
DV		 186 /* Reads out the current hw, returning true if the connector is enabled
187 * and active (i.e. dpms ON state). */
188 bool (*get_hw_state)(struct intel_connector *);
1d508706
JN		 189
190 /* Panel info for eDP and LVDS */
191 struct intel_panel panel;
9cd300e0
JN		 192
193 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
194 struct edid *edid;
5daa55eb
ZW		 195};
196
79e53945
JB		 197struct intel_crtc {
198 struct drm_crtc base;
80824003
JB		 199 enum pipe pipe;
200 enum plane plane;
a5c961d1 201 enum transcoder cpu_transcoder;
79e53945 202 u8 lut_r[256], lut_g[256], lut_b[256];
08a48469
DV		 203 /*
204 * Whether the crtc and the connected output pipeline is active. Implies
205 * that crtc->enabled is set, i.e. the current mode configuration has
206 * some outputs connected to this crtc.
08a48469
DV		 207 */
208 bool active;
93314b5b 209 bool primary_disabled; /* is the crtc obscured by a plane? */
652c393a 210 bool lowfreq_avail;
02e792fb 211 struct intel_overlay *overlay;
6b95a207 212 struct intel_unpin_work *unpin_work;
77ffb597 213 int fdi_lanes;
cda4b7d3 214
b4a98e57
CW		 215 atomic_t unpin_work_count;
216
e506a0c6
DV		 217 /* Display surface base address adjustement for pageflips. Note that on
218 * gen4+ this only adjusts up to a tile, offsets within a tile are
219 * handled in the hw itself (with the TILEOFF register). */
220 unsigned long dspaddr_offset;
221
05394f39 222 struct drm_i915_gem_object *cursor_bo;
cda4b7d3
CW		 223 uint32_t cursor_addr;
224 int16_t cursor_x, cursor_y;
225 int16_t cursor_width, cursor_height;
6b383a7f 226 bool cursor_visible;
5a354204 227 unsigned int bpp;
4b645f14 228
ee7b9f93
JB		 229 /* We can share PLLs across outputs if the timings match */
230 struct intel_pch_pll *pch_pll;
6441ab5f 231 uint32_t ddi_pll_sel;
79e53945
JB		 232};
233
b840d907
JB		 234struct intel_plane {
235 struct drm_plane base;
236 enum pipe pipe;
237 struct drm_i915_gem_object *obj;
2d354c34 238 bool can_scale;
b840d907
JB		 239 int max_downscale;
240 u32 lut_r[1024], lut_g[1024], lut_b[1024];
241 void (*update_plane)(struct drm_plane *plane,
242 struct drm_framebuffer *fb,
243 struct drm_i915_gem_object *obj,
244 int crtc_x, int crtc_y,
245 unsigned int crtc_w, unsigned int crtc_h,
246 uint32_t x, uint32_t y,
247 uint32_t src_w, uint32_t src_h);
248 void (*disable_plane)(struct drm_plane *plane);
8ea30864
JB		 249 int (*update_colorkey)(struct drm_plane *plane,
250 struct drm_intel_sprite_colorkey *key);
251 void (*get_colorkey)(struct drm_plane *plane,
252 struct drm_intel_sprite_colorkey *key);
b840d907
JB		 253};
254
b445e3b0
ED		 255struct intel_watermark_params {
256 unsigned long fifo_size;
257 unsigned long max_wm;
258 unsigned long default_wm;
259 unsigned long guard_size;
260 unsigned long cacheline_size;
261};
262
263struct cxsr_latency {
264 int is_desktop;
265 int is_ddr3;
266 unsigned long fsb_freq;
267 unsigned long mem_freq;
268 unsigned long display_sr;
269 unsigned long display_hpll_disable;
270 unsigned long cursor_sr;
271 unsigned long cursor_hpll_disable;
272};
273
79e53945 274#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
5daa55eb 275#define to_intel_connector(x) container_of(x, struct intel_connector, base)
4ef69c7a 276#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
79e53945 277#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
b840d907 278#define to_intel_plane(x) container_of(x, struct intel_plane, base)
79e53945 279
45187ace
JB		 280#define DIP_HEADER_SIZE 5
281
3c17fe4b
DH		 282#define DIP_TYPE_AVI 0x82
283#define DIP_VERSION_AVI 0x2
284#define DIP_LEN_AVI 13
c846b619
PZ		 285#define DIP_AVI_PR_1 0
286#define DIP_AVI_PR_2 1
3c17fe4b 287
26005210 288#define DIP_TYPE_SPD 0x83
c0864cb3
JB		 289#define DIP_VERSION_SPD 0x1
290#define DIP_LEN_SPD 25
291#define DIP_SPD_UNKNOWN 0
292#define DIP_SPD_DSTB 0x1
293#define DIP_SPD_DVDP 0x2
294#define DIP_SPD_DVHS 0x3
295#define DIP_SPD_HDDVR 0x4
296#define DIP_SPD_DVC 0x5
297#define DIP_SPD_DSC 0x6
298#define DIP_SPD_VCD 0x7
299#define DIP_SPD_GAME 0x8
300#define DIP_SPD_PC 0x9
301#define DIP_SPD_BD 0xa
302#define DIP_SPD_SCD 0xb
303
3c17fe4b
DH		 304struct dip_infoframe {
305 uint8_t type; /* HB0 */
306 uint8_t ver; /* HB1 */
307 uint8_t len; /* HB2 - body len, not including checksum */
308 uint8_t ecc; /* Header ECC */
309 uint8_t checksum; /* PB0 */
310 union {
311 struct {
312 /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */
313 uint8_t Y_A_B_S;
314 /* PB2 - C 7:6, M 5:4, R 3:0 */
315 uint8_t C_M_R;
316 /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */
317 uint8_t ITC_EC_Q_SC;
318 /* PB4 - VIC 6:0 */
319 uint8_t VIC;
0aa534df
PZ		 320 /* PB5 - YQ 7:6, CN 5:4, PR 3:0 */
321 uint8_t YQ_CN_PR;
3c17fe4b
DH		 322 /* PB6 to PB13 */
323 uint16_t top_bar_end;
324 uint16_t bottom_bar_start;
325 uint16_t left_bar_end;
326 uint16_t right_bar_start;
81014b9d 327 } __attribute__ ((packed)) avi;
c0864cb3
JB		 328 struct {
329 uint8_t vn[8];
330 uint8_t pd[16];
331 uint8_t sdi;
81014b9d 332 } __attribute__ ((packed)) spd;
3c17fe4b
DH		 333 uint8_t payload[27];
334 } __attribute__ ((packed)) body;
335} __attribute__((packed));
336
f5bbfca3 337struct intel_hdmi {
f5bbfca3
ED		 338 u32 sdvox_reg;
339 int ddc_bus;
f5bbfca3
ED		 340 uint32_t color_range;
341 bool has_hdmi_sink;
342 bool has_audio;
343 enum hdmi_force_audio force_audio;
344 void (*write_infoframe)(struct drm_encoder *encoder,
345 struct dip_infoframe *frame);
687f4d06
PZ		 346 void (*set_infoframes)(struct drm_encoder *encoder,
347 struct drm_display_mode *adjusted_mode);
f5bbfca3
ED		 348};
349
b091cd92 350#define DP_MAX_DOWNSTREAM_PORTS 0x10
54d63ca6
SK		 351#define DP_LINK_CONFIGURATION_SIZE 9
352
353struct intel_dp {
54d63ca6
SK		 354 uint32_t output_reg;
355 uint32_t DP;
356 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
357 bool has_audio;
358 enum hdmi_force_audio force_audio;
359 uint32_t color_range;
54d63ca6
SK		 360 uint8_t link_bw;
361 uint8_t lane_count;
362 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
b091cd92 363 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
54d63ca6
SK		 364 struct i2c_adapter adapter;
365 struct i2c_algo_dp_aux_data algo;
366 bool is_pch_edp;
367 uint8_t train_set[4];
368 int panel_power_up_delay;
369 int panel_power_down_delay;
370 int panel_power_cycle_delay;
371 int backlight_on_delay;
372 int backlight_off_delay;
54d63ca6
SK		 373 struct delayed_work panel_vdd_work;
374 bool want_panel_vdd;
dd06f90e 375 struct intel_connector *attached_connector;
54d63ca6
SK		 376};
377
da63a9f2
PZ		 378struct intel_digital_port {
379 struct intel_encoder base;
174edf1f 380 enum port port;
da63a9f2
PZ		 381 struct intel_dp dp;
382 struct intel_hdmi hdmi;
383};
384
f875c15a
CW		 385static inline struct drm_crtc *
386intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
387{
388 struct drm_i915_private *dev_priv = dev->dev_private;
389 return dev_priv->pipe_to_crtc_mapping[pipe];
390}
391
417ae147
CW		 392static inline struct drm_crtc *
393intel_get_crtc_for_plane(struct drm_device *dev, int plane)
394{
395 struct drm_i915_private *dev_priv = dev->dev_private;
396 return dev_priv->plane_to_crtc_mapping[plane];
397}
398
4e5359cd
SF		 399struct intel_unpin_work {
400 struct work_struct work;
b4a98e57 401 struct drm_crtc *crtc;
05394f39
CW		 402 struct drm_i915_gem_object *old_fb_obj;
403 struct drm_i915_gem_object *pending_flip_obj;
4e5359cd
SF		 404 struct drm_pending_vblank_event *event;
405 int pending;
406 bool enable_stall_check;
407};
408
1630fe75
CW		 409struct intel_fbc_work {
410 struct delayed_work work;
411 struct drm_crtc *crtc;
412 struct drm_framebuffer *fb;
413 int interval;
414};
415
d2acd215
DV		 416int intel_pch_rawclk(struct drm_device *dev);
417
4eab8136
JN		 418int intel_connector_update_modes(struct drm_connector *connector,
419 struct edid *edid);
335af9a2 420int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
f0217c42 421
3f43c48d 422extern void intel_attach_force_audio_property(struct drm_connector *connector);
e953fd7b
CW		 423extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
424
79e53945 425extern void intel_crt_init(struct drm_device *dev);
08d644ad
DV		 426extern void intel_hdmi_init(struct drm_device *dev,
427 int sdvox_reg, enum port port);
00c09d70
PZ		 428extern void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
429 struct intel_connector *intel_connector);
f5bbfca3 430extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
00c09d70
PZ		 431extern bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
432 const struct drm_display_mode *mode,
433 struct drm_display_mode *adjusted_mode);
f5bbfca3 434extern void intel_dip_infoframe_csum(struct dip_infoframe *avi_if);
eef4eacb
DV		 435extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg,
436 bool is_sdvob);
79e53945
JB		 437extern void intel_dvo_init(struct drm_device *dev);
438extern void intel_tv_init(struct drm_device *dev);
f047e395
CW		 439extern void intel_mark_busy(struct drm_device *dev);
440extern void intel_mark_idle(struct drm_device *dev);
441extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj);
442extern void intel_mark_fb_idle(struct drm_i915_gem_object *obj);
c5d1b51d 443extern bool intel_lvds_init(struct drm_device *dev);
1974cad0 444extern bool intel_is_dual_link_lvds(struct drm_device *dev);
ab9d7c30
PZ		 445extern void intel_dp_init(struct drm_device *dev, int output_reg,
446 enum port port);
00c09d70
PZ		 447extern void intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
448 struct intel_connector *intel_connector);
a4fc5ed6
KP		 449void
450intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
451 struct drm_display_mode *adjusted_mode);
247d89f6 452extern void intel_dp_init_link_config(struct intel_dp *intel_dp);
c19b0669
PZ		 453extern void intel_dp_start_link_train(struct intel_dp *intel_dp);
454extern void intel_dp_complete_link_train(struct intel_dp *intel_dp);
455extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
00c09d70
PZ		 456extern void intel_dp_encoder_destroy(struct drm_encoder *encoder);
457extern void intel_dp_check_link_status(struct intel_dp *intel_dp);
458extern bool intel_dp_mode_fixup(struct drm_encoder *encoder,
459 const struct drm_display_mode *mode,
460 struct drm_display_mode *adjusted_mode);
cb0953d7 461extern bool intel_dpd_is_edp(struct drm_device *dev);
d6c50ff8
PZ		 462extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp);
463extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp);
82a4d9c0
PZ		 464extern void ironlake_edp_panel_on(struct intel_dp *intel_dp);
465extern void ironlake_edp_panel_off(struct intel_dp *intel_dp);
466extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
467extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
0206e353 468extern void intel_edp_link_config(struct intel_encoder *, int *, int *);
94bf2ced
DV		 469extern int intel_edp_target_clock(struct intel_encoder *,
470 struct drm_display_mode *mode);
814948ad 471extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder);
b840d907 472extern int intel_plane_init(struct drm_device *dev, enum pipe pipe);
6f1d69b0
ED		 473extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
474 enum plane plane);
32f9d658 475
a9573556 476/* intel_panel.c */
dd06f90e
JN		 477extern int intel_panel_init(struct intel_panel *panel,
478 struct drm_display_mode *fixed_mode);
1d508706
JN		 479extern void intel_panel_fini(struct intel_panel *panel);
480
1d8e1c75
CW		 481extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
482 struct drm_display_mode *adjusted_mode);
483extern void intel_pch_panel_fitting(struct drm_device *dev,
484 int fitting_mode,
cb1793ce 485 const struct drm_display_mode *mode,
1d8e1c75 486 struct drm_display_mode *adjusted_mode);
a9573556 487extern u32 intel_panel_get_max_backlight(struct drm_device *dev);
a9573556 488extern void intel_panel_set_backlight(struct drm_device *dev, u32 level);
0657b6b1 489extern int intel_panel_setup_backlight(struct drm_connector *connector);
24ded204
DV		 490extern void intel_panel_enable_backlight(struct drm_device *dev,
491 enum pipe pipe);
47356eb6 492extern void intel_panel_disable_backlight(struct drm_device *dev);
aaa6fd2a 493extern void intel_panel_destroy_backlight(struct drm_device *dev);
fe16d949 494extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1d8e1c75 495
d9e55608 496struct intel_set_config {
1aa4b628
DV		 497 struct drm_encoder **save_connector_encoders;
498 struct drm_crtc **save_encoder_crtcs;
5e2b584e
DV		 499
500 bool fb_changed;
501 bool mode_changed;
d9e55608
DV		 502};
503
a6778b3c
DV		 504extern bool intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
505 int x, int y, struct drm_framebuffer *old_fb);
a261b246 506extern void intel_modeset_disable(struct drm_device *dev);
79e53945 507extern void intel_crtc_load_lut(struct drm_crtc *crtc);
b2cabb0e 508extern void intel_crtc_update_dpms(struct drm_crtc *crtc);
1f703855 509extern void intel_encoder_noop(struct drm_encoder *encoder);
ea5b213a 510extern void intel_encoder_destroy(struct drm_encoder *encoder);
5ab432ef 511extern void intel_encoder_dpms(struct intel_encoder *encoder, int mode);
6ed0f796 512extern bool intel_encoder_check_is_cloned(struct intel_encoder *encoder);
5ab432ef 513extern void intel_connector_dpms(struct drm_connector *, int mode);
f0947c37 514extern bool intel_connector_get_hw_state(struct intel_connector *connector);
b980514c
DV		 515extern void intel_modeset_check_state(struct drm_device *dev);
516
79e53945 517
df0e9248
CW		 518static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector)
519{
520 return to_intel_connector(connector)->encoder;
521}
522
7739c33b
PZ		 523static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
524{
da63a9f2
PZ		 525 struct intel_digital_port *intel_dig_port =
526 container_of(encoder, struct intel_digital_port, base.base);
527 return &intel_dig_port->dp;
528}
529
530static inline struct intel_digital_port *
531enc_to_dig_port(struct drm_encoder *encoder)
532{
533 return container_of(encoder, struct intel_digital_port, base.base);
534}
535
536static inline struct intel_digital_port *
537dp_to_dig_port(struct intel_dp *intel_dp)
538{
539 return container_of(intel_dp, struct intel_digital_port, dp);
540}
541
542static inline struct intel_digital_port *
543hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
544{
545 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
7739c33b
PZ		 546}
547
df0e9248
CW		 548extern void intel_connector_attach_encoder(struct intel_connector *connector,
549 struct intel_encoder *encoder);
550extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
79e53945
JB		 551
552extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
553 struct drm_crtc *crtc);
08d7b3d1
CW		 554int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
555 struct drm_file *file_priv);
a5c961d1
PZ		 556extern enum transcoder
557intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
558 enum pipe pipe);
9d0498a2 559extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
58e10eb9 560extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
8261b191
CW		 561
562struct intel_load_detect_pipe {
d2dff872 563 struct drm_framebuffer *release_fb;
8261b191
CW		 564 bool load_detect_temp;
565 int dpms_mode;
566};
d2434ab7 567extern bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 568 struct drm_display_mode *mode,
8261b191 569 struct intel_load_detect_pipe *old);
d2434ab7 570extern void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 571 struct intel_load_detect_pipe *old);
79e53945 572
79e53945
JB		 573extern void intelfb_restore(void);
574extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
575 u16 blue, int regno);
b8c00ac5
DA		 576extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
577 u16 *blue, int regno);
0cdab21f 578extern void intel_enable_clock_gating(struct drm_device *dev);
79e53945 579
127bd2ac 580extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 581 struct drm_i915_gem_object *obj,
919926ae 582 struct intel_ring_buffer *pipelined);
1690e1eb 583extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
127bd2ac 584
38651674
DA		 585extern int intel_framebuffer_init(struct drm_device *dev,
586 struct intel_framebuffer *ifb,
308e5bcb 587 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 588 struct drm_i915_gem_object *obj);
38651674
DA		 589extern int intel_fbdev_init(struct drm_device *dev);
590extern void intel_fbdev_fini(struct drm_device *dev);
3fa016a0 591extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
6b95a207
KH		 592extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
593extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
1afe3e9d 594extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
6b95a207 595
02e792fb
DV		 596extern void intel_setup_overlay(struct drm_device *dev);
597extern void intel_cleanup_overlay(struct drm_device *dev);
ce453d81 598extern int intel_overlay_switch_off(struct intel_overlay *overlay);
02e792fb
DV		 599extern int intel_overlay_put_image(struct drm_device *dev, void *data,
600 struct drm_file *file_priv);
601extern int intel_overlay_attrs(struct drm_device *dev, void *data,
602 struct drm_file *file_priv);
4abe3520 603
eb1f8e4f 604extern void intel_fb_output_poll_changed(struct drm_device *dev);
e8e7a2b8 605extern void intel_fb_restore_mode(struct drm_device *dev);
645c62a5 606
b840d907
JB		 607extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
608 bool state);
609#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
610#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
611
645c62a5 612extern void intel_init_clock_gating(struct drm_device *dev);
e0dac65e
WF		 613extern void intel_write_eld(struct drm_encoder *encoder,
614 struct drm_display_mode *mode);
d4270e57 615extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
45244b87 616extern void intel_prepare_ddi(struct drm_device *dev);
c82e4d26 617extern void hsw_fdi_link_train(struct drm_crtc *crtc);
0e72a5b5 618extern void intel_ddi_init(struct drm_device *dev, enum port port);
d4270e57 619
b840d907 620/* For use by IVB LP watermark workaround in intel_sprite.c */
f681fa23 621extern void intel_update_watermarks(struct drm_device *dev);
b840d907
JB		 622extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
623 uint32_t sprite_width,
624 int pixel_size);
1f8eeabf
ED		 625extern void intel_update_linetime_watermarks(struct drm_device *dev, int pipe,
626 struct drm_display_mode *mode);
8ea30864 627
5a35e99e
DL		 628extern unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
629 unsigned int bpp,
630 unsigned int pitch);
631
8ea30864
JB		 632extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
633 struct drm_file *file_priv);
634extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
635 struct drm_file *file_priv);
636
57f350b6
JB		 637extern u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg);
638
85208be0 639/* Power-related functions, located in intel_pm.c */
1fa61106 640extern void intel_init_pm(struct drm_device *dev);
85208be0 641/* FBC */
85208be0
ED		 642extern bool intel_fbc_enabled(struct drm_device *dev);
643extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
644extern void intel_update_fbc(struct drm_device *dev);
eb48eb00
DV		 645/* IPS */
646extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
647extern void intel_gpu_ips_teardown(void);
85208be0 648
0232e927 649extern void intel_init_power_wells(struct drm_device *dev);
8090c6b9
DV		 650extern void intel_enable_gt_powersave(struct drm_device *dev);
651extern void intel_disable_gt_powersave(struct drm_device *dev);
6590190d 652extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv);
930ebb46 653extern void ironlake_teardown_rc6(struct drm_device *dev);
b3daeaef 654
85234cdc
DV		 655extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
656 enum pipe *pipe);
b8fc2f6a 657extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
79f689aa 658extern void intel_ddi_pll_init(struct drm_device *dev);
8d9ddbcb 659extern void intel_ddi_enable_pipe_func(struct drm_crtc *crtc);
ad80a810
PZ		 660extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
661 enum transcoder cpu_transcoder);
fc914639
PZ		 662extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
663extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
6441ab5f
PZ		 664extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
665extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock);
6441ab5f 666extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
dae84799 667extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
c19b0669 668extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
1ad960f2
PZ		 669extern bool
670intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
671extern void intel_ddi_fdi_disable(struct drm_crtc *crtc);
72662e10 672
79e53945 673#endif /* __INTEL_DRV_H__ */
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