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drm/i915: Fix CAGF for HSW
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_drv.h
CommitLineData
79e53945
JB		 1/*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 */
25#ifndef __INTEL_DRV_H__
26#define __INTEL_DRV_H__
27
28#include <linux/i2c.h>
760285e7 29#include <drm/i915_drm.h>
80824003 30#include "i915_drv.h"
760285e7
DH		 31#include <drm/drm_crtc.h>
32#include <drm/drm_crtc_helper.h>
33#include <drm/drm_fb_helper.h>
612a9aab 34#include <drm/drm_dp_helper.h>
913d8d11 35
481b6af3 36#define _wait_for(COND, MS, W) ({ \
913d8d11
CW		 37 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
38 int ret__ = 0; \
0206e353 39 while (!(COND)) { \
913d8d11
CW		 40 if (time_after(jiffies, timeout__)) { \
41 ret__ = -ETIMEDOUT; \
42 break; \
43 } \
0cc2764c
BW		 44 if (W && drm_can_sleep()) { \
45 msleep(W); \
46 } else { \
47 cpu_relax(); \
48 } \
913d8d11
CW		 49 } \
50 ret__; \
51})
52
57f350b6 53#define wait_for_atomic_us(COND, US) ({ \
bcf9dcc1
CW		 54 unsigned long timeout__ = jiffies + usecs_to_jiffies(US); \
55 int ret__ = 0; \
56 while (!(COND)) { \
57 if (time_after(jiffies, timeout__)) { \
58 ret__ = -ETIMEDOUT; \
59 break; \
60 } \
61 cpu_relax(); \
62 } \
63 ret__; \
57f350b6
JB		 64})
65
481b6af3
CW		 66#define wait_for(COND, MS) _wait_for(COND, MS, 1)
67#define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
68
021357ac
CW		 69#define KHz(x) (1000*x)
70#define MHz(x) KHz(1000*x)
71
79e53945
JB		 72/*
73 * Display related stuff
74 */
75
76/* store information about an Ixxx DVO */
77/* The i830->i865 use multiple DVOs with multiple i2cs */
78/* the i915, i945 have a single sDVO i2c bus - which is different */
79#define MAX_OUTPUTS 6
80/* maximum connectors per crtcs in the mode set */
81#define INTELFB_CONN_LIMIT 4
82
83#define INTEL_I2C_BUS_DVO 1
84#define INTEL_I2C_BUS_SDVO 2
85
86/* these are outputs from the chip - integrated only
87 external chips are via DVO or SDVO output */
88#define INTEL_OUTPUT_UNUSED 0
89#define INTEL_OUTPUT_ANALOG 1
90#define INTEL_OUTPUT_DVO 2
91#define INTEL_OUTPUT_SDVO 3
92#define INTEL_OUTPUT_LVDS 4
93#define INTEL_OUTPUT_TVOUT 5
7d57382e 94#define INTEL_OUTPUT_HDMI 6
a4fc5ed6 95#define INTEL_OUTPUT_DISPLAYPORT 7
32f9d658 96#define INTEL_OUTPUT_EDP 8
00c09d70 97#define INTEL_OUTPUT_UNKNOWN 9
79e53945
JB		 98
99#define INTEL_DVO_CHIP_NONE 0
100#define INTEL_DVO_CHIP_LVDS 1
101#define INTEL_DVO_CHIP_TMDS 2
102#define INTEL_DVO_CHIP_TVOUT 4
103
6c9547ff
CW		 104/* drm_display_mode->private_flags */
105#define INTEL_MODE_PIXEL_MULTIPLIER_SHIFT (0x0)
106#define INTEL_MODE_PIXEL_MULTIPLIER_MASK (0xf << INTEL_MODE_PIXEL_MULTIPLIER_SHIFT)
3b5c78a3 107#define INTEL_MODE_DP_FORCE_6BPC (0x10)
f9bef081
DV		 108/* This flag must be set by the encoder's mode_fixup if it changes the crtc
109 * timings in the mode to prevent the crtc fixup from overwriting them.
110 * Currently only lvds needs that. */
111#define INTEL_MODE_CRTC_TIMINGS_SET (0x20)
3685a8f3
VS		 112/*
113 * Set when limited 16-235 (as opposed to full 0-255) RGB color range is
114 * to be used.
115 */
116#define INTEL_MODE_LIMITED_COLOR_RANGE (0x40)
6c9547ff
CW		 117
118static inline void
119intel_mode_set_pixel_multiplier(struct drm_display_mode *mode,
120 int multiplier)
121{
122 mode->clock *= multiplier;
123 mode->private_flags |= multiplier;
124}
125
126static inline int
127intel_mode_get_pixel_multiplier(const struct drm_display_mode *mode)
128{
129 return (mode->private_flags & INTEL_MODE_PIXEL_MULTIPLIER_MASK) >> INTEL_MODE_PIXEL_MULTIPLIER_SHIFT;
130}
131
79e53945
JB		 132struct intel_framebuffer {
133 struct drm_framebuffer base;
05394f39 134 struct drm_i915_gem_object *obj;
79e53945
JB		 135};
136
37811fcc
CW		 137struct intel_fbdev {
138 struct drm_fb_helper helper;
139 struct intel_framebuffer ifb;
140 struct list_head fbdev_list;
141 struct drm_display_mode *our_mode;
142};
79e53945 143
21d40d37 144struct intel_encoder {
4ef69c7a 145 struct drm_encoder base;
9a935856
DV		 146 /*
147 * The new crtc this encoder will be driven from. Only differs from
148 * base->crtc while a modeset is in progress.
149 */
150 struct intel_crtc *new_crtc;
151
79e53945 152 int type;
e2f0ba97 153 bool needs_tv_clock;
66a9278e
DV		 154 /*
155 * Intel hw has only one MUX where encoders could be clone, hence a
156 * simple flag is enough to compute the possible_clones mask.
157 */
158 bool cloneable;
5ab432ef 159 bool connectors_active;
21d40d37 160 void (*hot_plug)(struct intel_encoder *);
dafd226c 161 void (*pre_pll_enable)(struct intel_encoder *);
bf49ec8c 162 void (*pre_enable)(struct intel_encoder *);
ef9c3aee
DV		 163 void (*enable)(struct intel_encoder *);
164 void (*disable)(struct intel_encoder *);
bf49ec8c 165 void (*post_disable)(struct intel_encoder *);
f0947c37
DV		 166 /* Read out the current hw state of this connector, returning true if
167 * the encoder is active. If the encoder is enabled it also set the pipe
168 * it is connected to in the pipe parameter. */
169 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
f8aed700 170 int crtc_mask;
79e53945
JB		 171};
172
1d508706 173struct intel_panel {
dd06f90e 174 struct drm_display_mode *fixed_mode;
4d891523 175 int fitting_mode;
1d508706
JN		 176};
177
5daa55eb
ZW		 178struct intel_connector {
179 struct drm_connector base;
9a935856
DV		 180 /*
181 * The fixed encoder this connector is connected to.
182 */
df0e9248 183 struct intel_encoder *encoder;
9a935856
DV		 184
185 /*
186 * The new encoder this connector will be driven. Only differs from
187 * encoder while a modeset is in progress.
188 */
189 struct intel_encoder *new_encoder;
190
f0947c37
DV		 191 /* Reads out the current hw, returning true if the connector is enabled
192 * and active (i.e. dpms ON state). */
193 bool (*get_hw_state)(struct intel_connector *);
1d508706
JN		 194
195 /* Panel info for eDP and LVDS */
196 struct intel_panel panel;
9cd300e0
JN		 197
198 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
199 struct edid *edid;
5daa55eb
ZW		 200};
201
79e53945
JB		 202struct intel_crtc {
203 struct drm_crtc base;
80824003
JB		 204 enum pipe pipe;
205 enum plane plane;
a5c961d1 206 enum transcoder cpu_transcoder;
79e53945 207 u8 lut_r[256], lut_g[256], lut_b[256];
08a48469
DV		 208 /*
209 * Whether the crtc and the connected output pipeline is active. Implies
210 * that crtc->enabled is set, i.e. the current mode configuration has
211 * some outputs connected to this crtc.
08a48469
DV		 212 */
213 bool active;
7b9f35a6 214 bool eld_vld;
93314b5b 215 bool primary_disabled; /* is the crtc obscured by a plane? */
652c393a 216 bool lowfreq_avail;
02e792fb 217 struct intel_overlay *overlay;
6b95a207 218 struct intel_unpin_work *unpin_work;
77ffb597 219 int fdi_lanes;
cda4b7d3 220
b4a98e57
CW		 221 atomic_t unpin_work_count;
222
e506a0c6
DV		 223 /* Display surface base address adjustement for pageflips. Note that on
224 * gen4+ this only adjusts up to a tile, offsets within a tile are
225 * handled in the hw itself (with the TILEOFF register). */
226 unsigned long dspaddr_offset;
227
05394f39 228 struct drm_i915_gem_object *cursor_bo;
cda4b7d3
CW		 229 uint32_t cursor_addr;
230 int16_t cursor_x, cursor_y;
231 int16_t cursor_width, cursor_height;
6b383a7f 232 bool cursor_visible;
5a354204 233 unsigned int bpp;
4b645f14 234
ee7b9f93
JB		 235 /* We can share PLLs across outputs if the timings match */
236 struct intel_pch_pll *pch_pll;
6441ab5f 237 uint32_t ddi_pll_sel;
79e53945
JB		 238};
239
b840d907
JB		 240struct intel_plane {
241 struct drm_plane base;
242 enum pipe pipe;
243 struct drm_i915_gem_object *obj;
2d354c34 244 bool can_scale;
b840d907
JB		 245 int max_downscale;
246 u32 lut_r[1024], lut_g[1024], lut_b[1024];
247 void (*update_plane)(struct drm_plane *plane,
248 struct drm_framebuffer *fb,
249 struct drm_i915_gem_object *obj,
250 int crtc_x, int crtc_y,
251 unsigned int crtc_w, unsigned int crtc_h,
252 uint32_t x, uint32_t y,
253 uint32_t src_w, uint32_t src_h);
254 void (*disable_plane)(struct drm_plane *plane);
8ea30864
JB		 255 int (*update_colorkey)(struct drm_plane *plane,
256 struct drm_intel_sprite_colorkey *key);
257 void (*get_colorkey)(struct drm_plane *plane,
258 struct drm_intel_sprite_colorkey *key);
b840d907
JB		 259};
260
b445e3b0
ED		 261struct intel_watermark_params {
262 unsigned long fifo_size;
263 unsigned long max_wm;
264 unsigned long default_wm;
265 unsigned long guard_size;
266 unsigned long cacheline_size;
267};
268
269struct cxsr_latency {
270 int is_desktop;
271 int is_ddr3;
272 unsigned long fsb_freq;
273 unsigned long mem_freq;
274 unsigned long display_sr;
275 unsigned long display_hpll_disable;
276 unsigned long cursor_sr;
277 unsigned long cursor_hpll_disable;
278};
279
79e53945 280#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
5daa55eb 281#define to_intel_connector(x) container_of(x, struct intel_connector, base)
4ef69c7a 282#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
79e53945 283#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
b840d907 284#define to_intel_plane(x) container_of(x, struct intel_plane, base)
79e53945 285
45187ace
JB		 286#define DIP_HEADER_SIZE 5
287
3c17fe4b
DH		 288#define DIP_TYPE_AVI 0x82
289#define DIP_VERSION_AVI 0x2
290#define DIP_LEN_AVI 13
c846b619
PZ		 291#define DIP_AVI_PR_1 0
292#define DIP_AVI_PR_2 1
abedc077
VS		 293#define DIP_AVI_RGB_QUANT_RANGE_DEFAULT (0 << 2)
294#define DIP_AVI_RGB_QUANT_RANGE_LIMITED (1 << 2)
295#define DIP_AVI_RGB_QUANT_RANGE_FULL (2 << 2)
3c17fe4b 296
26005210 297#define DIP_TYPE_SPD 0x83
c0864cb3
JB		 298#define DIP_VERSION_SPD 0x1
299#define DIP_LEN_SPD 25
300#define DIP_SPD_UNKNOWN 0
301#define DIP_SPD_DSTB 0x1
302#define DIP_SPD_DVDP 0x2
303#define DIP_SPD_DVHS 0x3
304#define DIP_SPD_HDDVR 0x4
305#define DIP_SPD_DVC 0x5
306#define DIP_SPD_DSC 0x6
307#define DIP_SPD_VCD 0x7
308#define DIP_SPD_GAME 0x8
309#define DIP_SPD_PC 0x9
310#define DIP_SPD_BD 0xa
311#define DIP_SPD_SCD 0xb
312
3c17fe4b
DH		 313struct dip_infoframe {
314 uint8_t type; /* HB0 */
315 uint8_t ver; /* HB1 */
316 uint8_t len; /* HB2 - body len, not including checksum */
317 uint8_t ecc; /* Header ECC */
318 uint8_t checksum; /* PB0 */
319 union {
320 struct {
321 /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */
322 uint8_t Y_A_B_S;
323 /* PB2 - C 7:6, M 5:4, R 3:0 */
324 uint8_t C_M_R;
325 /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */
326 uint8_t ITC_EC_Q_SC;
327 /* PB4 - VIC 6:0 */
328 uint8_t VIC;
0aa534df
PZ		 329 /* PB5 - YQ 7:6, CN 5:4, PR 3:0 */
330 uint8_t YQ_CN_PR;
3c17fe4b
DH		 331 /* PB6 to PB13 */
332 uint16_t top_bar_end;
333 uint16_t bottom_bar_start;
334 uint16_t left_bar_end;
335 uint16_t right_bar_start;
81014b9d 336 } __attribute__ ((packed)) avi;
c0864cb3
JB		 337 struct {
338 uint8_t vn[8];
339 uint8_t pd[16];
340 uint8_t sdi;
81014b9d 341 } __attribute__ ((packed)) spd;
3c17fe4b
DH		 342 uint8_t payload[27];
343 } __attribute__ ((packed)) body;
344} __attribute__((packed));
345
f5bbfca3 346struct intel_hdmi {
f5bbfca3
ED		 347 u32 sdvox_reg;
348 int ddc_bus;
f5bbfca3 349 uint32_t color_range;
55bc60db 350 bool color_range_auto;
f5bbfca3
ED		 351 bool has_hdmi_sink;
352 bool has_audio;
353 enum hdmi_force_audio force_audio;
abedc077 354 bool rgb_quant_range_selectable;
f5bbfca3
ED		 355 void (*write_infoframe)(struct drm_encoder *encoder,
356 struct dip_infoframe *frame);
687f4d06
PZ		 357 void (*set_infoframes)(struct drm_encoder *encoder,
358 struct drm_display_mode *adjusted_mode);
f5bbfca3
ED		 359};
360
b091cd92 361#define DP_MAX_DOWNSTREAM_PORTS 0x10
54d63ca6
SK		 362#define DP_LINK_CONFIGURATION_SIZE 9
363
364struct intel_dp {
54d63ca6
SK		 365 uint32_t output_reg;
366 uint32_t DP;
367 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
368 bool has_audio;
369 enum hdmi_force_audio force_audio;
370 uint32_t color_range;
55bc60db 371 bool color_range_auto;
54d63ca6
SK		 372 uint8_t link_bw;
373 uint8_t lane_count;
374 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
b091cd92 375 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
54d63ca6
SK		 376 struct i2c_adapter adapter;
377 struct i2c_algo_dp_aux_data algo;
378 bool is_pch_edp;
379 uint8_t train_set[4];
380 int panel_power_up_delay;
381 int panel_power_down_delay;
382 int panel_power_cycle_delay;
383 int backlight_on_delay;
384 int backlight_off_delay;
54d63ca6
SK		 385 struct delayed_work panel_vdd_work;
386 bool want_panel_vdd;
dd06f90e 387 struct intel_connector *attached_connector;
54d63ca6
SK		 388};
389
da63a9f2
PZ		 390struct intel_digital_port {
391 struct intel_encoder base;
174edf1f 392 enum port port;
da63a9f2
PZ		 393 struct intel_dp dp;
394 struct intel_hdmi hdmi;
395};
396
f875c15a
CW		 397static inline struct drm_crtc *
398intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
399{
400 struct drm_i915_private *dev_priv = dev->dev_private;
401 return dev_priv->pipe_to_crtc_mapping[pipe];
402}
403
417ae147
CW		 404static inline struct drm_crtc *
405intel_get_crtc_for_plane(struct drm_device *dev, int plane)
406{
407 struct drm_i915_private *dev_priv = dev->dev_private;
408 return dev_priv->plane_to_crtc_mapping[plane];
409}
410
4e5359cd
SF		 411struct intel_unpin_work {
412 struct work_struct work;
b4a98e57 413 struct drm_crtc *crtc;
05394f39
CW		 414 struct drm_i915_gem_object *old_fb_obj;
415 struct drm_i915_gem_object *pending_flip_obj;
4e5359cd 416 struct drm_pending_vblank_event *event;
e7d841ca
CW		 417 atomic_t pending;
418#define INTEL_FLIP_INACTIVE 0
419#define INTEL_FLIP_PENDING 1
420#define INTEL_FLIP_COMPLETE 2
4e5359cd
SF		 421 bool enable_stall_check;
422};
423
1630fe75
CW		 424struct intel_fbc_work {
425 struct delayed_work work;
426 struct drm_crtc *crtc;
427 struct drm_framebuffer *fb;
428 int interval;
429};
430
d2acd215
DV		 431int intel_pch_rawclk(struct drm_device *dev);
432
4eab8136
JN		 433int intel_connector_update_modes(struct drm_connector *connector,
434 struct edid *edid);
335af9a2 435int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
f0217c42 436
3f43c48d 437extern void intel_attach_force_audio_property(struct drm_connector *connector);
e953fd7b
CW		 438extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
439
79e53945 440extern void intel_crt_init(struct drm_device *dev);
08d644ad
DV		 441extern void intel_hdmi_init(struct drm_device *dev,
442 int sdvox_reg, enum port port);
00c09d70
PZ		 443extern void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
444 struct intel_connector *intel_connector);
f5bbfca3 445extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
00c09d70
PZ		 446extern bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
447 const struct drm_display_mode *mode,
448 struct drm_display_mode *adjusted_mode);
f5bbfca3 449extern void intel_dip_infoframe_csum(struct dip_infoframe *avi_if);
eef4eacb
DV		 450extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg,
451 bool is_sdvob);
79e53945
JB		 452extern void intel_dvo_init(struct drm_device *dev);
453extern void intel_tv_init(struct drm_device *dev);
f047e395
CW		 454extern void intel_mark_busy(struct drm_device *dev);
455extern void intel_mark_idle(struct drm_device *dev);
456extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj);
457extern void intel_mark_fb_idle(struct drm_i915_gem_object *obj);
c5d1b51d 458extern bool intel_lvds_init(struct drm_device *dev);
1974cad0 459extern bool intel_is_dual_link_lvds(struct drm_device *dev);
ab9d7c30
PZ		 460extern void intel_dp_init(struct drm_device *dev, int output_reg,
461 enum port port);
00c09d70
PZ		 462extern void intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
463 struct intel_connector *intel_connector);
a4fc5ed6
KP		 464void
465intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
466 struct drm_display_mode *adjusted_mode);
247d89f6 467extern void intel_dp_init_link_config(struct intel_dp *intel_dp);
c19b0669
PZ		 468extern void intel_dp_start_link_train(struct intel_dp *intel_dp);
469extern void intel_dp_complete_link_train(struct intel_dp *intel_dp);
470extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
00c09d70
PZ		 471extern void intel_dp_encoder_destroy(struct drm_encoder *encoder);
472extern void intel_dp_check_link_status(struct intel_dp *intel_dp);
473extern bool intel_dp_mode_fixup(struct drm_encoder *encoder,
474 const struct drm_display_mode *mode,
475 struct drm_display_mode *adjusted_mode);
cb0953d7 476extern bool intel_dpd_is_edp(struct drm_device *dev);
d6c50ff8
PZ		 477extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp);
478extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp);
82a4d9c0
PZ		 479extern void ironlake_edp_panel_on(struct intel_dp *intel_dp);
480extern void ironlake_edp_panel_off(struct intel_dp *intel_dp);
481extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
482extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
0206e353 483extern void intel_edp_link_config(struct intel_encoder *, int *, int *);
94bf2ced
DV		 484extern int intel_edp_target_clock(struct intel_encoder *,
485 struct drm_display_mode *mode);
814948ad 486extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder);
b840d907 487extern int intel_plane_init(struct drm_device *dev, enum pipe pipe);
6f1d69b0
ED		 488extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
489 enum plane plane);
32f9d658 490
a9573556 491/* intel_panel.c */
dd06f90e
JN		 492extern int intel_panel_init(struct intel_panel *panel,
493 struct drm_display_mode *fixed_mode);
1d508706
JN		 494extern void intel_panel_fini(struct intel_panel *panel);
495
1d8e1c75
CW		 496extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
497 struct drm_display_mode *adjusted_mode);
498extern void intel_pch_panel_fitting(struct drm_device *dev,
499 int fitting_mode,
cb1793ce 500 const struct drm_display_mode *mode,
1d8e1c75 501 struct drm_display_mode *adjusted_mode);
a9573556 502extern u32 intel_panel_get_max_backlight(struct drm_device *dev);
a9573556 503extern void intel_panel_set_backlight(struct drm_device *dev, u32 level);
0657b6b1 504extern int intel_panel_setup_backlight(struct drm_connector *connector);
24ded204
DV		 505extern void intel_panel_enable_backlight(struct drm_device *dev,
506 enum pipe pipe);
47356eb6 507extern void intel_panel_disable_backlight(struct drm_device *dev);
aaa6fd2a 508extern void intel_panel_destroy_backlight(struct drm_device *dev);
fe16d949 509extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1d8e1c75 510
d9e55608 511struct intel_set_config {
1aa4b628
DV		 512 struct drm_encoder **save_connector_encoders;
513 struct drm_crtc **save_encoder_crtcs;
5e2b584e
DV		 514
515 bool fb_changed;
516 bool mode_changed;
d9e55608
DV		 517};
518
c0c36b94
CW		 519extern int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
520 int x, int y, struct drm_framebuffer *old_fb);
a261b246 521extern void intel_modeset_disable(struct drm_device *dev);
c0c36b94 522extern void intel_crtc_restore_mode(struct drm_crtc *crtc);
79e53945 523extern void intel_crtc_load_lut(struct drm_crtc *crtc);
b2cabb0e 524extern void intel_crtc_update_dpms(struct drm_crtc *crtc);
1f703855 525extern void intel_encoder_noop(struct drm_encoder *encoder);
ea5b213a 526extern void intel_encoder_destroy(struct drm_encoder *encoder);
5ab432ef 527extern void intel_encoder_dpms(struct intel_encoder *encoder, int mode);
6ed0f796 528extern bool intel_encoder_check_is_cloned(struct intel_encoder *encoder);
5ab432ef 529extern void intel_connector_dpms(struct drm_connector *, int mode);
f0947c37 530extern bool intel_connector_get_hw_state(struct intel_connector *connector);
b980514c
DV		 531extern void intel_modeset_check_state(struct drm_device *dev);
532
79e53945 533
df0e9248
CW		 534static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector)
535{
536 return to_intel_connector(connector)->encoder;
537}
538
7739c33b
PZ		 539static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
540{
da63a9f2
PZ		 541 struct intel_digital_port *intel_dig_port =
542 container_of(encoder, struct intel_digital_port, base.base);
543 return &intel_dig_port->dp;
544}
545
546static inline struct intel_digital_port *
547enc_to_dig_port(struct drm_encoder *encoder)
548{
549 return container_of(encoder, struct intel_digital_port, base.base);
550}
551
552static inline struct intel_digital_port *
553dp_to_dig_port(struct intel_dp *intel_dp)
554{
555 return container_of(intel_dp, struct intel_digital_port, dp);
556}
557
558static inline struct intel_digital_port *
559hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
560{
561 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
7739c33b
PZ		 562}
563
b0ea7d37
DL		 564bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
565 struct intel_digital_port *port);
566
df0e9248
CW		 567extern void intel_connector_attach_encoder(struct intel_connector *connector,
568 struct intel_encoder *encoder);
569extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
79e53945
JB		 570
571extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
572 struct drm_crtc *crtc);
08d7b3d1
CW		 573int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
574 struct drm_file *file_priv);
a5c961d1
PZ		 575extern enum transcoder
576intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
577 enum pipe pipe);
9d0498a2 578extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
58e10eb9 579extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
d4b1931c 580extern int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
8261b191
CW		 581
582struct intel_load_detect_pipe {
d2dff872 583 struct drm_framebuffer *release_fb;
8261b191
CW		 584 bool load_detect_temp;
585 int dpms_mode;
586};
d2434ab7 587extern bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 588 struct drm_display_mode *mode,
8261b191 589 struct intel_load_detect_pipe *old);
d2434ab7 590extern void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 591 struct intel_load_detect_pipe *old);
79e53945 592
79e53945
JB		 593extern void intelfb_restore(void);
594extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
595 u16 blue, int regno);
b8c00ac5
DA		 596extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
597 u16 *blue, int regno);
0cdab21f 598extern void intel_enable_clock_gating(struct drm_device *dev);
79e53945 599
127bd2ac 600extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 601 struct drm_i915_gem_object *obj,
919926ae 602 struct intel_ring_buffer *pipelined);
1690e1eb 603extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
127bd2ac 604
38651674
DA		 605extern int intel_framebuffer_init(struct drm_device *dev,
606 struct intel_framebuffer *ifb,
308e5bcb 607 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 608 struct drm_i915_gem_object *obj);
38651674 609extern int intel_fbdev_init(struct drm_device *dev);
20afbda2 610extern void intel_fbdev_initial_config(struct drm_device *dev);
38651674 611extern void intel_fbdev_fini(struct drm_device *dev);
3fa016a0 612extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
6b95a207
KH		 613extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
614extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
1afe3e9d 615extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
6b95a207 616
02e792fb
DV		 617extern void intel_setup_overlay(struct drm_device *dev);
618extern void intel_cleanup_overlay(struct drm_device *dev);
ce453d81 619extern int intel_overlay_switch_off(struct intel_overlay *overlay);
02e792fb
DV		 620extern int intel_overlay_put_image(struct drm_device *dev, void *data,
621 struct drm_file *file_priv);
622extern int intel_overlay_attrs(struct drm_device *dev, void *data,
623 struct drm_file *file_priv);
4abe3520 624
eb1f8e4f 625extern void intel_fb_output_poll_changed(struct drm_device *dev);
e8e7a2b8 626extern void intel_fb_restore_mode(struct drm_device *dev);
645c62a5 627
b840d907
JB		 628extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
629 bool state);
630#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
631#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
632
645c62a5 633extern void intel_init_clock_gating(struct drm_device *dev);
e0dac65e
WF		 634extern void intel_write_eld(struct drm_encoder *encoder,
635 struct drm_display_mode *mode);
d4270e57 636extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
45244b87 637extern void intel_prepare_ddi(struct drm_device *dev);
c82e4d26 638extern void hsw_fdi_link_train(struct drm_crtc *crtc);
0e72a5b5 639extern void intel_ddi_init(struct drm_device *dev, enum port port);
d4270e57 640
b840d907 641/* For use by IVB LP watermark workaround in intel_sprite.c */
f681fa23 642extern void intel_update_watermarks(struct drm_device *dev);
b840d907
JB		 643extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
644 uint32_t sprite_width,
645 int pixel_size);
1f8eeabf
ED		 646extern void intel_update_linetime_watermarks(struct drm_device *dev, int pipe,
647 struct drm_display_mode *mode);
8ea30864 648
5a35e99e
DL		 649extern unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
650 unsigned int bpp,
651 unsigned int pitch);
652
8ea30864
JB		 653extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
654 struct drm_file *file_priv);
655extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
656 struct drm_file *file_priv);
657
57f350b6
JB		 658extern u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg);
659
85208be0 660/* Power-related functions, located in intel_pm.c */
1fa61106 661extern void intel_init_pm(struct drm_device *dev);
85208be0 662/* FBC */
85208be0
ED		 663extern bool intel_fbc_enabled(struct drm_device *dev);
664extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
665extern void intel_update_fbc(struct drm_device *dev);
eb48eb00
DV		 666/* IPS */
667extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
668extern void intel_gpu_ips_teardown(void);
85208be0 669
fa42e23c 670extern void intel_init_power_well(struct drm_device *dev);
cb10799c 671extern void intel_set_power_well(struct drm_device *dev, bool enable);
8090c6b9
DV		 672extern void intel_enable_gt_powersave(struct drm_device *dev);
673extern void intel_disable_gt_powersave(struct drm_device *dev);
6590190d 674extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv);
930ebb46 675extern void ironlake_teardown_rc6(struct drm_device *dev);
b3daeaef 676
85234cdc
DV		 677extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
678 enum pipe *pipe);
b8fc2f6a 679extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
79f689aa 680extern void intel_ddi_pll_init(struct drm_device *dev);
8d9ddbcb 681extern void intel_ddi_enable_pipe_func(struct drm_crtc *crtc);
ad80a810
PZ		 682extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
683 enum transcoder cpu_transcoder);
fc914639
PZ		 684extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
685extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
6441ab5f
PZ		 686extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
687extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock);
6441ab5f 688extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
dae84799 689extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
c19b0669 690extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
1ad960f2
PZ		 691extern bool
692intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
693extern void intel_ddi_fdi_disable(struct drm_crtc *crtc);
72662e10 694
79e53945 695#endif /* __INTEL_DRV_H__ */
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