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7d57382e EA |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2009 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Jesse Barnes <jesse.barnes@intel.com> | |
27 | */ | |
28 | ||
29 | #include <linux/i2c.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
7d57382e | 31 | #include <linux/delay.h> |
178f736a | 32 | #include <linux/hdmi.h> |
760285e7 | 33 | #include <drm/drmP.h> |
c6f95f27 | 34 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
35 | #include <drm/drm_crtc.h> |
36 | #include <drm/drm_edid.h> | |
15953637 | 37 | #include <drm/drm_scdc_helper.h> |
7d57382e | 38 | #include "intel_drv.h" |
760285e7 | 39 | #include <drm/i915_drm.h> |
46d196ec | 40 | #include <drm/intel_lpe_audio.h> |
7d57382e EA |
41 | #include "i915_drv.h" |
42 | ||
30add22d PZ |
43 | static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) |
44 | { | |
da63a9f2 | 45 | return hdmi_to_dig_port(intel_hdmi)->base.base.dev; |
30add22d PZ |
46 | } |
47 | ||
afba0188 DV |
48 | static void |
49 | assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) | |
50 | { | |
30add22d | 51 | struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); |
fac5e23e | 52 | struct drm_i915_private *dev_priv = to_i915(dev); |
afba0188 DV |
53 | uint32_t enabled_bits; |
54 | ||
4f8036a2 | 55 | enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; |
afba0188 | 56 | |
b242b7f7 | 57 | WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, |
afba0188 DV |
58 | "HDMI port enabled, expecting disabled\n"); |
59 | } | |
60 | ||
f5bbfca3 | 61 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
ea5b213a | 62 | { |
da63a9f2 PZ |
63 | struct intel_digital_port *intel_dig_port = |
64 | container_of(encoder, struct intel_digital_port, base.base); | |
65 | return &intel_dig_port->hdmi; | |
ea5b213a CW |
66 | } |
67 | ||
df0e9248 CW |
68 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
69 | { | |
da63a9f2 | 70 | return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base); |
df0e9248 CW |
71 | } |
72 | ||
1d776538 | 73 | static u32 g4x_infoframe_index(unsigned int type) |
3c17fe4b | 74 | { |
178f736a DL |
75 | switch (type) { |
76 | case HDMI_INFOFRAME_TYPE_AVI: | |
ed517fbb | 77 | return VIDEO_DIP_SELECT_AVI; |
178f736a | 78 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 79 | return VIDEO_DIP_SELECT_SPD; |
c8bb75af LD |
80 | case HDMI_INFOFRAME_TYPE_VENDOR: |
81 | return VIDEO_DIP_SELECT_VENDOR; | |
45187ace | 82 | default: |
ffc85dab | 83 | MISSING_CASE(type); |
ed517fbb | 84 | return 0; |
45187ace | 85 | } |
45187ace JB |
86 | } |
87 | ||
1d776538 | 88 | static u32 g4x_infoframe_enable(unsigned int type) |
45187ace | 89 | { |
178f736a DL |
90 | switch (type) { |
91 | case HDMI_INFOFRAME_TYPE_AVI: | |
ed517fbb | 92 | return VIDEO_DIP_ENABLE_AVI; |
178f736a | 93 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 94 | return VIDEO_DIP_ENABLE_SPD; |
c8bb75af LD |
95 | case HDMI_INFOFRAME_TYPE_VENDOR: |
96 | return VIDEO_DIP_ENABLE_VENDOR; | |
fa193ff7 | 97 | default: |
ffc85dab | 98 | MISSING_CASE(type); |
ed517fbb | 99 | return 0; |
fa193ff7 | 100 | } |
fa193ff7 PZ |
101 | } |
102 | ||
1d776538 | 103 | static u32 hsw_infoframe_enable(unsigned int type) |
2da8af54 | 104 | { |
178f736a | 105 | switch (type) { |
1d776538 VS |
106 | case DP_SDP_VSC: |
107 | return VIDEO_DIP_ENABLE_VSC_HSW; | |
178f736a | 108 | case HDMI_INFOFRAME_TYPE_AVI: |
2da8af54 | 109 | return VIDEO_DIP_ENABLE_AVI_HSW; |
178f736a | 110 | case HDMI_INFOFRAME_TYPE_SPD: |
2da8af54 | 111 | return VIDEO_DIP_ENABLE_SPD_HSW; |
c8bb75af LD |
112 | case HDMI_INFOFRAME_TYPE_VENDOR: |
113 | return VIDEO_DIP_ENABLE_VS_HSW; | |
2da8af54 | 114 | default: |
ffc85dab | 115 | MISSING_CASE(type); |
2da8af54 PZ |
116 | return 0; |
117 | } | |
118 | } | |
119 | ||
f0f59a00 VS |
120 | static i915_reg_t |
121 | hsw_dip_data_reg(struct drm_i915_private *dev_priv, | |
122 | enum transcoder cpu_transcoder, | |
1d776538 | 123 | unsigned int type, |
f0f59a00 | 124 | int i) |
2da8af54 | 125 | { |
178f736a | 126 | switch (type) { |
1d776538 VS |
127 | case DP_SDP_VSC: |
128 | return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i); | |
178f736a | 129 | case HDMI_INFOFRAME_TYPE_AVI: |
436c6d4a | 130 | return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i); |
178f736a | 131 | case HDMI_INFOFRAME_TYPE_SPD: |
436c6d4a | 132 | return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i); |
c8bb75af | 133 | case HDMI_INFOFRAME_TYPE_VENDOR: |
436c6d4a | 134 | return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i); |
2da8af54 | 135 | default: |
ffc85dab | 136 | MISSING_CASE(type); |
f0f59a00 | 137 | return INVALID_MMIO_REG; |
2da8af54 PZ |
138 | } |
139 | } | |
140 | ||
a3da1df7 | 141 | static void g4x_write_infoframe(struct drm_encoder *encoder, |
ac240288 | 142 | const struct intel_crtc_state *crtc_state, |
1d776538 | 143 | unsigned int type, |
fff63867 | 144 | const void *frame, ssize_t len) |
45187ace | 145 | { |
fff63867 | 146 | const uint32_t *data = frame; |
3c17fe4b | 147 | struct drm_device *dev = encoder->dev; |
fac5e23e | 148 | struct drm_i915_private *dev_priv = to_i915(dev); |
22509ec8 | 149 | u32 val = I915_READ(VIDEO_DIP_CTL); |
178f736a | 150 | int i; |
3c17fe4b | 151 | |
822974ae PZ |
152 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
153 | ||
1d4f85ac | 154 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 155 | val |= g4x_infoframe_index(type); |
22509ec8 | 156 | |
178f736a | 157 | val &= ~g4x_infoframe_enable(type); |
45187ace | 158 | |
22509ec8 | 159 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b | 160 | |
9d9740f0 | 161 | mmiowb(); |
45187ace | 162 | for (i = 0; i < len; i += 4) { |
3c17fe4b DH |
163 | I915_WRITE(VIDEO_DIP_DATA, *data); |
164 | data++; | |
165 | } | |
adf00b26 PZ |
166 | /* Write every possible data byte to force correct ECC calculation. */ |
167 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
168 | I915_WRITE(VIDEO_DIP_DATA, 0); | |
9d9740f0 | 169 | mmiowb(); |
3c17fe4b | 170 | |
178f736a | 171 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 172 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 173 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 174 | |
22509ec8 | 175 | I915_WRITE(VIDEO_DIP_CTL, val); |
9d9740f0 | 176 | POSTING_READ(VIDEO_DIP_CTL); |
3c17fe4b DH |
177 | } |
178 | ||
cda0aaaf VS |
179 | static bool g4x_infoframe_enabled(struct drm_encoder *encoder, |
180 | const struct intel_crtc_state *pipe_config) | |
e43823ec | 181 | { |
cda0aaaf | 182 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
89a35ecd | 183 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
e43823ec JB |
184 | u32 val = I915_READ(VIDEO_DIP_CTL); |
185 | ||
ec1dc603 VS |
186 | if ((val & VIDEO_DIP_ENABLE) == 0) |
187 | return false; | |
89a35ecd | 188 | |
ec1dc603 VS |
189 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) |
190 | return false; | |
191 | ||
192 | return val & (VIDEO_DIP_ENABLE_AVI | | |
193 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); | |
e43823ec JB |
194 | } |
195 | ||
fdf1250a | 196 | static void ibx_write_infoframe(struct drm_encoder *encoder, |
ac240288 | 197 | const struct intel_crtc_state *crtc_state, |
1d776538 | 198 | unsigned int type, |
fff63867 | 199 | const void *frame, ssize_t len) |
fdf1250a | 200 | { |
fff63867 | 201 | const uint32_t *data = frame; |
fdf1250a | 202 | struct drm_device *dev = encoder->dev; |
fac5e23e | 203 | struct drm_i915_private *dev_priv = to_i915(dev); |
ac240288 | 204 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
f0f59a00 | 205 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
fdf1250a | 206 | u32 val = I915_READ(reg); |
f0f59a00 | 207 | int i; |
fdf1250a | 208 | |
822974ae PZ |
209 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
210 | ||
fdf1250a | 211 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 212 | val |= g4x_infoframe_index(type); |
fdf1250a | 213 | |
178f736a | 214 | val &= ~g4x_infoframe_enable(type); |
fdf1250a PZ |
215 | |
216 | I915_WRITE(reg, val); | |
217 | ||
9d9740f0 | 218 | mmiowb(); |
fdf1250a PZ |
219 | for (i = 0; i < len; i += 4) { |
220 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
221 | data++; | |
222 | } | |
adf00b26 PZ |
223 | /* Write every possible data byte to force correct ECC calculation. */ |
224 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
225 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 226 | mmiowb(); |
fdf1250a | 227 | |
178f736a | 228 | val |= g4x_infoframe_enable(type); |
fdf1250a | 229 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 230 | val |= VIDEO_DIP_FREQ_VSYNC; |
fdf1250a PZ |
231 | |
232 | I915_WRITE(reg, val); | |
9d9740f0 | 233 | POSTING_READ(reg); |
fdf1250a PZ |
234 | } |
235 | ||
cda0aaaf VS |
236 | static bool ibx_infoframe_enabled(struct drm_encoder *encoder, |
237 | const struct intel_crtc_state *pipe_config) | |
e43823ec | 238 | { |
cda0aaaf | 239 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
052f62f7 | 240 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
cda0aaaf VS |
241 | enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; |
242 | i915_reg_t reg = TVIDEO_DIP_CTL(pipe); | |
e43823ec JB |
243 | u32 val = I915_READ(reg); |
244 | ||
ec1dc603 VS |
245 | if ((val & VIDEO_DIP_ENABLE) == 0) |
246 | return false; | |
247 | ||
248 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) | |
249 | return false; | |
052f62f7 | 250 | |
ec1dc603 VS |
251 | return val & (VIDEO_DIP_ENABLE_AVI | |
252 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
253 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
e43823ec JB |
254 | } |
255 | ||
fdf1250a | 256 | static void cpt_write_infoframe(struct drm_encoder *encoder, |
ac240288 | 257 | const struct intel_crtc_state *crtc_state, |
1d776538 | 258 | unsigned int type, |
fff63867 | 259 | const void *frame, ssize_t len) |
b055c8f3 | 260 | { |
fff63867 | 261 | const uint32_t *data = frame; |
b055c8f3 | 262 | struct drm_device *dev = encoder->dev; |
fac5e23e | 263 | struct drm_i915_private *dev_priv = to_i915(dev); |
ac240288 | 264 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
f0f59a00 | 265 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 266 | u32 val = I915_READ(reg); |
f0f59a00 | 267 | int i; |
b055c8f3 | 268 | |
822974ae PZ |
269 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
270 | ||
64a8fc01 | 271 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 272 | val |= g4x_infoframe_index(type); |
45187ace | 273 | |
ecb97851 PZ |
274 | /* The DIP control register spec says that we need to update the AVI |
275 | * infoframe without clearing its enable bit */ | |
178f736a DL |
276 | if (type != HDMI_INFOFRAME_TYPE_AVI) |
277 | val &= ~g4x_infoframe_enable(type); | |
ecb97851 | 278 | |
22509ec8 | 279 | I915_WRITE(reg, val); |
45187ace | 280 | |
9d9740f0 | 281 | mmiowb(); |
45187ace | 282 | for (i = 0; i < len; i += 4) { |
b055c8f3 JB |
283 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
284 | data++; | |
285 | } | |
adf00b26 PZ |
286 | /* Write every possible data byte to force correct ECC calculation. */ |
287 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
288 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 289 | mmiowb(); |
b055c8f3 | 290 | |
178f736a | 291 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 292 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 293 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 294 | |
22509ec8 | 295 | I915_WRITE(reg, val); |
9d9740f0 | 296 | POSTING_READ(reg); |
45187ace | 297 | } |
90b107c8 | 298 | |
cda0aaaf VS |
299 | static bool cpt_infoframe_enabled(struct drm_encoder *encoder, |
300 | const struct intel_crtc_state *pipe_config) | |
e43823ec | 301 | { |
cda0aaaf VS |
302 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
303 | enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; | |
304 | u32 val = I915_READ(TVIDEO_DIP_CTL(pipe)); | |
e43823ec | 305 | |
ec1dc603 VS |
306 | if ((val & VIDEO_DIP_ENABLE) == 0) |
307 | return false; | |
308 | ||
309 | return val & (VIDEO_DIP_ENABLE_AVI | | |
310 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
311 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
e43823ec JB |
312 | } |
313 | ||
90b107c8 | 314 | static void vlv_write_infoframe(struct drm_encoder *encoder, |
ac240288 | 315 | const struct intel_crtc_state *crtc_state, |
1d776538 | 316 | unsigned int type, |
fff63867 | 317 | const void *frame, ssize_t len) |
90b107c8 | 318 | { |
fff63867 | 319 | const uint32_t *data = frame; |
90b107c8 | 320 | struct drm_device *dev = encoder->dev; |
fac5e23e | 321 | struct drm_i915_private *dev_priv = to_i915(dev); |
ac240288 | 322 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
f0f59a00 | 323 | i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 324 | u32 val = I915_READ(reg); |
f0f59a00 | 325 | int i; |
90b107c8 | 326 | |
822974ae PZ |
327 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
328 | ||
90b107c8 | 329 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 330 | val |= g4x_infoframe_index(type); |
22509ec8 | 331 | |
178f736a | 332 | val &= ~g4x_infoframe_enable(type); |
90b107c8 | 333 | |
22509ec8 | 334 | I915_WRITE(reg, val); |
90b107c8 | 335 | |
9d9740f0 | 336 | mmiowb(); |
90b107c8 SK |
337 | for (i = 0; i < len; i += 4) { |
338 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
339 | data++; | |
340 | } | |
adf00b26 PZ |
341 | /* Write every possible data byte to force correct ECC calculation. */ |
342 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
343 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 344 | mmiowb(); |
90b107c8 | 345 | |
178f736a | 346 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 347 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 348 | val |= VIDEO_DIP_FREQ_VSYNC; |
90b107c8 | 349 | |
22509ec8 | 350 | I915_WRITE(reg, val); |
9d9740f0 | 351 | POSTING_READ(reg); |
90b107c8 SK |
352 | } |
353 | ||
cda0aaaf VS |
354 | static bool vlv_infoframe_enabled(struct drm_encoder *encoder, |
355 | const struct intel_crtc_state *pipe_config) | |
e43823ec | 356 | { |
cda0aaaf | 357 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
535afa2e | 358 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
cda0aaaf VS |
359 | enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; |
360 | u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe)); | |
e43823ec | 361 | |
ec1dc603 VS |
362 | if ((val & VIDEO_DIP_ENABLE) == 0) |
363 | return false; | |
364 | ||
365 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) | |
366 | return false; | |
535afa2e | 367 | |
ec1dc603 VS |
368 | return val & (VIDEO_DIP_ENABLE_AVI | |
369 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
370 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
e43823ec JB |
371 | } |
372 | ||
8c5f5f7c | 373 | static void hsw_write_infoframe(struct drm_encoder *encoder, |
ac240288 | 374 | const struct intel_crtc_state *crtc_state, |
1d776538 | 375 | unsigned int type, |
fff63867 | 376 | const void *frame, ssize_t len) |
8c5f5f7c | 377 | { |
fff63867 | 378 | const uint32_t *data = frame; |
2da8af54 | 379 | struct drm_device *dev = encoder->dev; |
fac5e23e | 380 | struct drm_i915_private *dev_priv = to_i915(dev); |
ac240288 | 381 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
f0f59a00 VS |
382 | i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); |
383 | i915_reg_t data_reg; | |
1d776538 VS |
384 | int data_size = type == DP_SDP_VSC ? |
385 | VIDEO_DIP_VSC_DATA_SIZE : VIDEO_DIP_DATA_SIZE; | |
178f736a | 386 | int i; |
2da8af54 | 387 | u32 val = I915_READ(ctl_reg); |
8c5f5f7c | 388 | |
436c6d4a | 389 | data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0); |
2da8af54 | 390 | |
178f736a | 391 | val &= ~hsw_infoframe_enable(type); |
2da8af54 PZ |
392 | I915_WRITE(ctl_reg, val); |
393 | ||
9d9740f0 | 394 | mmiowb(); |
2da8af54 | 395 | for (i = 0; i < len; i += 4) { |
436c6d4a VS |
396 | I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, |
397 | type, i >> 2), *data); | |
2da8af54 PZ |
398 | data++; |
399 | } | |
adf00b26 | 400 | /* Write every possible data byte to force correct ECC calculation. */ |
1d776538 | 401 | for (; i < data_size; i += 4) |
436c6d4a VS |
402 | I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, |
403 | type, i >> 2), 0); | |
9d9740f0 | 404 | mmiowb(); |
8c5f5f7c | 405 | |
178f736a | 406 | val |= hsw_infoframe_enable(type); |
2da8af54 | 407 | I915_WRITE(ctl_reg, val); |
9d9740f0 | 408 | POSTING_READ(ctl_reg); |
8c5f5f7c ED |
409 | } |
410 | ||
cda0aaaf VS |
411 | static bool hsw_infoframe_enabled(struct drm_encoder *encoder, |
412 | const struct intel_crtc_state *pipe_config) | |
e43823ec | 413 | { |
cda0aaaf VS |
414 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
415 | u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); | |
e43823ec | 416 | |
ec1dc603 VS |
417 | return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | |
418 | VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | | |
419 | VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); | |
e43823ec JB |
420 | } |
421 | ||
5adaea79 DL |
422 | /* |
423 | * The data we write to the DIP data buffer registers is 1 byte bigger than the | |
424 | * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting | |
425 | * at 0). It's also a byte used by DisplayPort so the same DIP registers can be | |
426 | * used for both technologies. | |
427 | * | |
428 | * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 | |
429 | * DW1: DB3 | DB2 | DB1 | DB0 | |
430 | * DW2: DB7 | DB6 | DB5 | DB4 | |
431 | * DW3: ... | |
432 | * | |
433 | * (HB is Header Byte, DB is Data Byte) | |
434 | * | |
435 | * The hdmi pack() functions don't know about that hardware specific hole so we | |
436 | * trick them by giving an offset into the buffer and moving back the header | |
437 | * bytes by one. | |
438 | */ | |
9198ee5b | 439 | static void intel_write_infoframe(struct drm_encoder *encoder, |
ac240288 | 440 | const struct intel_crtc_state *crtc_state, |
9198ee5b | 441 | union hdmi_infoframe *frame) |
45187ace | 442 | { |
f99be1b3 | 443 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
5adaea79 DL |
444 | uint8_t buffer[VIDEO_DIP_DATA_SIZE]; |
445 | ssize_t len; | |
45187ace | 446 | |
5adaea79 DL |
447 | /* see comment above for the reason for this offset */ |
448 | len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1); | |
449 | if (len < 0) | |
450 | return; | |
451 | ||
452 | /* Insert the 'hole' (see big comment above) at position 3 */ | |
453 | buffer[0] = buffer[1]; | |
454 | buffer[1] = buffer[2]; | |
455 | buffer[2] = buffer[3]; | |
456 | buffer[3] = 0; | |
457 | len++; | |
45187ace | 458 | |
f99be1b3 | 459 | intel_dig_port->write_infoframe(encoder, crtc_state, frame->any.type, buffer, len); |
45187ace JB |
460 | } |
461 | ||
687f4d06 | 462 | static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, |
ac240288 | 463 | const struct intel_crtc_state *crtc_state) |
45187ace | 464 | { |
abedc077 | 465 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
779c4c28 VS |
466 | const struct drm_display_mode *adjusted_mode = |
467 | &crtc_state->base.adjusted_mode; | |
0c1f528c SS |
468 | struct drm_connector *connector = &intel_hdmi->attached_connector->base; |
469 | bool is_hdmi2_sink = connector->display_info.hdmi.scdc.supported; | |
5adaea79 DL |
470 | union hdmi_infoframe frame; |
471 | int ret; | |
45187ace | 472 | |
5adaea79 | 473 | ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, |
0c1f528c SS |
474 | adjusted_mode, |
475 | is_hdmi2_sink); | |
5adaea79 DL |
476 | if (ret < 0) { |
477 | DRM_ERROR("couldn't fill AVI infoframe\n"); | |
478 | return; | |
479 | } | |
c846b619 | 480 | |
2d8bd2bf SS |
481 | if (crtc_state->ycbcr420) |
482 | frame.avi.colorspace = HDMI_COLORSPACE_YUV420; | |
483 | else | |
484 | frame.avi.colorspace = HDMI_COLORSPACE_RGB; | |
485 | ||
779c4c28 | 486 | drm_hdmi_avi_infoframe_quant_range(&frame.avi, adjusted_mode, |
a2ce26f8 VS |
487 | crtc_state->limited_color_range ? |
488 | HDMI_QUANTIZATION_RANGE_LIMITED : | |
489 | HDMI_QUANTIZATION_RANGE_FULL, | |
9271c0ca VS |
490 | intel_hdmi->rgb_quant_range_selectable, |
491 | is_hdmi2_sink); | |
abedc077 | 492 | |
2d8bd2bf | 493 | /* TODO: handle pixel repetition for YCBCR420 outputs */ |
ac240288 | 494 | intel_write_infoframe(encoder, crtc_state, &frame); |
b055c8f3 JB |
495 | } |
496 | ||
ac240288 ML |
497 | static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder, |
498 | const struct intel_crtc_state *crtc_state) | |
c0864cb3 | 499 | { |
5adaea79 DL |
500 | union hdmi_infoframe frame; |
501 | int ret; | |
502 | ||
503 | ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx"); | |
504 | if (ret < 0) { | |
505 | DRM_ERROR("couldn't fill SPD infoframe\n"); | |
506 | return; | |
507 | } | |
c0864cb3 | 508 | |
5adaea79 | 509 | frame.spd.sdi = HDMI_SPD_SDI_PC; |
c0864cb3 | 510 | |
ac240288 | 511 | intel_write_infoframe(encoder, crtc_state, &frame); |
c0864cb3 JB |
512 | } |
513 | ||
c8bb75af LD |
514 | static void |
515 | intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder, | |
ac240288 | 516 | const struct intel_crtc_state *crtc_state) |
c8bb75af LD |
517 | { |
518 | union hdmi_infoframe frame; | |
519 | int ret; | |
520 | ||
521 | ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi, | |
ac240288 | 522 | &crtc_state->base.adjusted_mode); |
c8bb75af LD |
523 | if (ret < 0) |
524 | return; | |
525 | ||
ac240288 | 526 | intel_write_infoframe(encoder, crtc_state, &frame); |
c8bb75af LD |
527 | } |
528 | ||
687f4d06 | 529 | static void g4x_set_infoframes(struct drm_encoder *encoder, |
6897b4b5 | 530 | bool enable, |
ac240288 ML |
531 | const struct intel_crtc_state *crtc_state, |
532 | const struct drm_connector_state *conn_state) | |
687f4d06 | 533 | { |
fac5e23e | 534 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
69fde0a6 VS |
535 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
536 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
f0f59a00 | 537 | i915_reg_t reg = VIDEO_DIP_CTL; |
0c14c7f9 | 538 | u32 val = I915_READ(reg); |
822cdc52 | 539 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 540 | |
afba0188 DV |
541 | assert_hdmi_port_disabled(intel_hdmi); |
542 | ||
0c14c7f9 PZ |
543 | /* If the registers were not initialized yet, they might be zeroes, |
544 | * which means we're selecting the AVI DIP and we're setting its | |
545 | * frequency to once. This seems to really confuse the HW and make | |
546 | * things stop working (the register spec says the AVI always needs to | |
547 | * be sent every VSync). So here we avoid writing to the register more | |
548 | * than we need and also explicitly select the AVI DIP and explicitly | |
549 | * set its frequency to every VSync. Avoiding to write it twice seems to | |
550 | * be enough to solve the problem, but being defensive shouldn't hurt us | |
551 | * either. */ | |
552 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
553 | ||
6897b4b5 | 554 | if (!enable) { |
0c14c7f9 PZ |
555 | if (!(val & VIDEO_DIP_ENABLE)) |
556 | return; | |
0be6f0c8 VS |
557 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
558 | DRM_DEBUG_KMS("video DIP still enabled on port %c\n", | |
559 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
560 | return; | |
561 | } | |
562 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | | |
563 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); | |
0c14c7f9 | 564 | I915_WRITE(reg, val); |
9d9740f0 | 565 | POSTING_READ(reg); |
0c14c7f9 PZ |
566 | return; |
567 | } | |
568 | ||
72b78c9d PZ |
569 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
570 | if (val & VIDEO_DIP_ENABLE) { | |
0be6f0c8 VS |
571 | DRM_DEBUG_KMS("video DIP already enabled on port %c\n", |
572 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
573 | return; | |
72b78c9d PZ |
574 | } |
575 | val &= ~VIDEO_DIP_PORT_MASK; | |
576 | val |= port; | |
577 | } | |
578 | ||
822974ae | 579 | val |= VIDEO_DIP_ENABLE; |
0be6f0c8 VS |
580 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
581 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); | |
822974ae | 582 | |
f278d972 | 583 | I915_WRITE(reg, val); |
9d9740f0 | 584 | POSTING_READ(reg); |
f278d972 | 585 | |
ac240288 ML |
586 | intel_hdmi_set_avi_infoframe(encoder, crtc_state); |
587 | intel_hdmi_set_spd_infoframe(encoder, crtc_state); | |
588 | intel_hdmi_set_hdmi_infoframe(encoder, crtc_state); | |
687f4d06 PZ |
589 | } |
590 | ||
ac240288 | 591 | static bool hdmi_sink_is_deep_color(const struct drm_connector_state *conn_state) |
6d67415f | 592 | { |
ac240288 | 593 | struct drm_connector *connector = conn_state->connector; |
6d67415f VS |
594 | |
595 | /* | |
596 | * HDMI cloning is only supported on g4x which doesn't | |
597 | * support deep color or GCP infoframes anyway so no | |
598 | * need to worry about multiple HDMI sinks here. | |
599 | */ | |
6d67415f | 600 | |
ac240288 | 601 | return connector->display_info.bpc > 8; |
6d67415f VS |
602 | } |
603 | ||
12aa3290 VS |
604 | /* |
605 | * Determine if default_phase=1 can be indicated in the GCP infoframe. | |
606 | * | |
607 | * From HDMI specification 1.4a: | |
608 | * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0 | |
609 | * - The first pixel following each Video Data Period shall have a pixel packing phase of 0 | |
610 | * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase | |
611 | * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing | |
612 | * phase of 0 | |
613 | */ | |
614 | static bool gcp_default_phase_possible(int pipe_bpp, | |
615 | const struct drm_display_mode *mode) | |
616 | { | |
617 | unsigned int pixels_per_group; | |
618 | ||
619 | switch (pipe_bpp) { | |
620 | case 30: | |
621 | /* 4 pixels in 5 clocks */ | |
622 | pixels_per_group = 4; | |
623 | break; | |
624 | case 36: | |
625 | /* 2 pixels in 3 clocks */ | |
626 | pixels_per_group = 2; | |
627 | break; | |
628 | case 48: | |
629 | /* 1 pixel in 2 clocks */ | |
630 | pixels_per_group = 1; | |
631 | break; | |
632 | default: | |
633 | /* phase information not relevant for 8bpc */ | |
634 | return false; | |
635 | } | |
636 | ||
637 | return mode->crtc_hdisplay % pixels_per_group == 0 && | |
638 | mode->crtc_htotal % pixels_per_group == 0 && | |
639 | mode->crtc_hblank_start % pixels_per_group == 0 && | |
640 | mode->crtc_hblank_end % pixels_per_group == 0 && | |
641 | mode->crtc_hsync_start % pixels_per_group == 0 && | |
642 | mode->crtc_hsync_end % pixels_per_group == 0 && | |
643 | ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 || | |
644 | mode->crtc_htotal/2 % pixels_per_group == 0); | |
645 | } | |
646 | ||
ac240288 ML |
647 | static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder, |
648 | const struct intel_crtc_state *crtc_state, | |
649 | const struct drm_connector_state *conn_state) | |
6d67415f | 650 | { |
fac5e23e | 651 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
ac240288 | 652 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
f0f59a00 VS |
653 | i915_reg_t reg; |
654 | u32 val = 0; | |
6d67415f VS |
655 | |
656 | if (HAS_DDI(dev_priv)) | |
ac240288 | 657 | reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); |
666a4537 | 658 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
6d67415f | 659 | reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); |
2d1fe073 | 660 | else if (HAS_PCH_SPLIT(dev_priv)) |
6d67415f VS |
661 | reg = TVIDEO_DIP_GCP(crtc->pipe); |
662 | else | |
663 | return false; | |
664 | ||
665 | /* Indicate color depth whenever the sink supports deep color */ | |
ac240288 | 666 | if (hdmi_sink_is_deep_color(conn_state)) |
6d67415f VS |
667 | val |= GCP_COLOR_INDICATION; |
668 | ||
12aa3290 | 669 | /* Enable default_phase whenever the display mode is suitably aligned */ |
ac240288 ML |
670 | if (gcp_default_phase_possible(crtc_state->pipe_bpp, |
671 | &crtc_state->base.adjusted_mode)) | |
12aa3290 VS |
672 | val |= GCP_DEFAULT_PHASE_ENABLE; |
673 | ||
6d67415f VS |
674 | I915_WRITE(reg, val); |
675 | ||
676 | return val != 0; | |
677 | } | |
678 | ||
687f4d06 | 679 | static void ibx_set_infoframes(struct drm_encoder *encoder, |
6897b4b5 | 680 | bool enable, |
ac240288 ML |
681 | const struct intel_crtc_state *crtc_state, |
682 | const struct drm_connector_state *conn_state) | |
687f4d06 | 683 | { |
fac5e23e | 684 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
ac240288 | 685 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
69fde0a6 VS |
686 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
687 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
f0f59a00 | 688 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
0c14c7f9 | 689 | u32 val = I915_READ(reg); |
822cdc52 | 690 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 691 | |
afba0188 DV |
692 | assert_hdmi_port_disabled(intel_hdmi); |
693 | ||
0c14c7f9 PZ |
694 | /* See the big comment in g4x_set_infoframes() */ |
695 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
696 | ||
6897b4b5 | 697 | if (!enable) { |
0c14c7f9 PZ |
698 | if (!(val & VIDEO_DIP_ENABLE)) |
699 | return; | |
0be6f0c8 VS |
700 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
701 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
702 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
0c14c7f9 | 703 | I915_WRITE(reg, val); |
9d9740f0 | 704 | POSTING_READ(reg); |
0c14c7f9 PZ |
705 | return; |
706 | } | |
707 | ||
72b78c9d | 708 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
0be6f0c8 VS |
709 | WARN(val & VIDEO_DIP_ENABLE, |
710 | "DIP already enabled on port %c\n", | |
711 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
72b78c9d PZ |
712 | val &= ~VIDEO_DIP_PORT_MASK; |
713 | val |= port; | |
714 | } | |
715 | ||
822974ae | 716 | val |= VIDEO_DIP_ENABLE; |
0be6f0c8 VS |
717 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
718 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
719 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 720 | |
ac240288 | 721 | if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) |
6d67415f VS |
722 | val |= VIDEO_DIP_ENABLE_GCP; |
723 | ||
f278d972 | 724 | I915_WRITE(reg, val); |
9d9740f0 | 725 | POSTING_READ(reg); |
f278d972 | 726 | |
ac240288 ML |
727 | intel_hdmi_set_avi_infoframe(encoder, crtc_state); |
728 | intel_hdmi_set_spd_infoframe(encoder, crtc_state); | |
729 | intel_hdmi_set_hdmi_infoframe(encoder, crtc_state); | |
687f4d06 PZ |
730 | } |
731 | ||
732 | static void cpt_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 733 | bool enable, |
ac240288 ML |
734 | const struct intel_crtc_state *crtc_state, |
735 | const struct drm_connector_state *conn_state) | |
687f4d06 | 736 | { |
fac5e23e | 737 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
ac240288 | 738 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
0c14c7f9 | 739 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
f0f59a00 | 740 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
0c14c7f9 PZ |
741 | u32 val = I915_READ(reg); |
742 | ||
afba0188 DV |
743 | assert_hdmi_port_disabled(intel_hdmi); |
744 | ||
0c14c7f9 PZ |
745 | /* See the big comment in g4x_set_infoframes() */ |
746 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
747 | ||
6897b4b5 | 748 | if (!enable) { |
0c14c7f9 PZ |
749 | if (!(val & VIDEO_DIP_ENABLE)) |
750 | return; | |
0be6f0c8 VS |
751 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
752 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
753 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
0c14c7f9 | 754 | I915_WRITE(reg, val); |
9d9740f0 | 755 | POSTING_READ(reg); |
0c14c7f9 PZ |
756 | return; |
757 | } | |
758 | ||
822974ae PZ |
759 | /* Set both together, unset both together: see the spec. */ |
760 | val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; | |
0dd87d20 | 761 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
0be6f0c8 | 762 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); |
822974ae | 763 | |
ac240288 | 764 | if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) |
6d67415f VS |
765 | val |= VIDEO_DIP_ENABLE_GCP; |
766 | ||
822974ae | 767 | I915_WRITE(reg, val); |
9d9740f0 | 768 | POSTING_READ(reg); |
822974ae | 769 | |
ac240288 ML |
770 | intel_hdmi_set_avi_infoframe(encoder, crtc_state); |
771 | intel_hdmi_set_spd_infoframe(encoder, crtc_state); | |
772 | intel_hdmi_set_hdmi_infoframe(encoder, crtc_state); | |
687f4d06 PZ |
773 | } |
774 | ||
775 | static void vlv_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 776 | bool enable, |
ac240288 ML |
777 | const struct intel_crtc_state *crtc_state, |
778 | const struct drm_connector_state *conn_state) | |
687f4d06 | 779 | { |
fac5e23e | 780 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
6a2b8021 | 781 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
ac240288 | 782 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
0c14c7f9 | 783 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
f0f59a00 | 784 | i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
0c14c7f9 | 785 | u32 val = I915_READ(reg); |
6a2b8021 | 786 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 787 | |
afba0188 DV |
788 | assert_hdmi_port_disabled(intel_hdmi); |
789 | ||
0c14c7f9 PZ |
790 | /* See the big comment in g4x_set_infoframes() */ |
791 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
792 | ||
6897b4b5 | 793 | if (!enable) { |
0c14c7f9 PZ |
794 | if (!(val & VIDEO_DIP_ENABLE)) |
795 | return; | |
0be6f0c8 VS |
796 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
797 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
798 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
0c14c7f9 | 799 | I915_WRITE(reg, val); |
9d9740f0 | 800 | POSTING_READ(reg); |
0c14c7f9 PZ |
801 | return; |
802 | } | |
803 | ||
6a2b8021 | 804 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
0be6f0c8 VS |
805 | WARN(val & VIDEO_DIP_ENABLE, |
806 | "DIP already enabled on port %c\n", | |
807 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
6a2b8021 JB |
808 | val &= ~VIDEO_DIP_PORT_MASK; |
809 | val |= port; | |
810 | } | |
811 | ||
822974ae | 812 | val |= VIDEO_DIP_ENABLE; |
0be6f0c8 VS |
813 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
814 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
815 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 816 | |
ac240288 | 817 | if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) |
6d67415f VS |
818 | val |= VIDEO_DIP_ENABLE_GCP; |
819 | ||
822974ae | 820 | I915_WRITE(reg, val); |
9d9740f0 | 821 | POSTING_READ(reg); |
822974ae | 822 | |
ac240288 ML |
823 | intel_hdmi_set_avi_infoframe(encoder, crtc_state); |
824 | intel_hdmi_set_spd_infoframe(encoder, crtc_state); | |
825 | intel_hdmi_set_hdmi_infoframe(encoder, crtc_state); | |
687f4d06 PZ |
826 | } |
827 | ||
828 | static void hsw_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 829 | bool enable, |
ac240288 ML |
830 | const struct intel_crtc_state *crtc_state, |
831 | const struct drm_connector_state *conn_state) | |
687f4d06 | 832 | { |
fac5e23e | 833 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
0c14c7f9 | 834 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
ac240288 | 835 | i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder); |
0dd87d20 | 836 | u32 val = I915_READ(reg); |
0c14c7f9 | 837 | |
afba0188 DV |
838 | assert_hdmi_port_disabled(intel_hdmi); |
839 | ||
0be6f0c8 VS |
840 | val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | |
841 | VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | | |
842 | VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); | |
843 | ||
6897b4b5 | 844 | if (!enable) { |
0be6f0c8 | 845 | I915_WRITE(reg, val); |
9d9740f0 | 846 | POSTING_READ(reg); |
0c14c7f9 PZ |
847 | return; |
848 | } | |
849 | ||
ac240288 | 850 | if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) |
6d67415f VS |
851 | val |= VIDEO_DIP_ENABLE_GCP_HSW; |
852 | ||
0dd87d20 | 853 | I915_WRITE(reg, val); |
9d9740f0 | 854 | POSTING_READ(reg); |
0dd87d20 | 855 | |
ac240288 ML |
856 | intel_hdmi_set_avi_infoframe(encoder, crtc_state); |
857 | intel_hdmi_set_spd_infoframe(encoder, crtc_state); | |
858 | intel_hdmi_set_hdmi_infoframe(encoder, crtc_state); | |
687f4d06 PZ |
859 | } |
860 | ||
b2ccb822 VS |
861 | void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable) |
862 | { | |
863 | struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi)); | |
864 | struct i2c_adapter *adapter = | |
865 | intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); | |
866 | ||
867 | if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI) | |
868 | return; | |
869 | ||
870 | DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n", | |
871 | enable ? "Enabling" : "Disabling"); | |
872 | ||
873 | drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type, | |
874 | adapter, enable); | |
875 | } | |
876 | ||
ac240288 ML |
877 | static void intel_hdmi_prepare(struct intel_encoder *encoder, |
878 | const struct intel_crtc_state *crtc_state) | |
7d57382e | 879 | { |
c59423a3 | 880 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 881 | struct drm_i915_private *dev_priv = to_i915(dev); |
ac240288 | 882 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
c59423a3 | 883 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
ac240288 | 884 | const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode; |
b242b7f7 | 885 | u32 hdmi_val; |
7d57382e | 886 | |
b2ccb822 VS |
887 | intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); |
888 | ||
b242b7f7 | 889 | hdmi_val = SDVO_ENCODING_HDMI; |
ac240288 | 890 | if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range) |
0f2a2a75 | 891 | hdmi_val |= HDMI_COLOR_RANGE_16_235; |
b599c0bc | 892 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
b242b7f7 | 893 | hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; |
b599c0bc | 894 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
b242b7f7 | 895 | hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; |
7d57382e | 896 | |
ac240288 | 897 | if (crtc_state->pipe_bpp > 24) |
4f3a8bc7 | 898 | hdmi_val |= HDMI_COLOR_FORMAT_12bpc; |
020f6704 | 899 | else |
4f3a8bc7 | 900 | hdmi_val |= SDVO_COLOR_FORMAT_8bpc; |
020f6704 | 901 | |
ac240288 | 902 | if (crtc_state->has_hdmi_sink) |
dc0fa718 | 903 | hdmi_val |= HDMI_MODE_SELECT_HDMI; |
2e3d6006 | 904 | |
6e266956 | 905 | if (HAS_PCH_CPT(dev_priv)) |
c59423a3 | 906 | hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); |
920a14b2 | 907 | else if (IS_CHERRYVIEW(dev_priv)) |
44f37d1f | 908 | hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); |
dc0fa718 | 909 | else |
c59423a3 | 910 | hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); |
7d57382e | 911 | |
b242b7f7 PZ |
912 | I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val); |
913 | POSTING_READ(intel_hdmi->hdmi_reg); | |
7d57382e EA |
914 | } |
915 | ||
85234cdc DV |
916 | static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, |
917 | enum pipe *pipe) | |
7d57382e | 918 | { |
85234cdc | 919 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 920 | struct drm_i915_private *dev_priv = to_i915(dev); |
85234cdc DV |
921 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
922 | u32 tmp; | |
5b092174 | 923 | bool ret; |
85234cdc | 924 | |
79f255a0 ACO |
925 | if (!intel_display_power_get_if_enabled(dev_priv, |
926 | encoder->power_domain)) | |
6d129bea ID |
927 | return false; |
928 | ||
5b092174 ID |
929 | ret = false; |
930 | ||
b242b7f7 | 931 | tmp = I915_READ(intel_hdmi->hdmi_reg); |
85234cdc DV |
932 | |
933 | if (!(tmp & SDVO_ENABLE)) | |
5b092174 | 934 | goto out; |
85234cdc | 935 | |
6e266956 | 936 | if (HAS_PCH_CPT(dev_priv)) |
85234cdc | 937 | *pipe = PORT_TO_PIPE_CPT(tmp); |
920a14b2 | 938 | else if (IS_CHERRYVIEW(dev_priv)) |
71485e0a | 939 | *pipe = SDVO_PORT_TO_PIPE_CHV(tmp); |
85234cdc DV |
940 | else |
941 | *pipe = PORT_TO_PIPE(tmp); | |
942 | ||
5b092174 ID |
943 | ret = true; |
944 | ||
945 | out: | |
79f255a0 | 946 | intel_display_power_put(dev_priv, encoder->power_domain); |
5b092174 ID |
947 | |
948 | return ret; | |
85234cdc DV |
949 | } |
950 | ||
045ac3b5 | 951 | static void intel_hdmi_get_config(struct intel_encoder *encoder, |
5cec258b | 952 | struct intel_crtc_state *pipe_config) |
045ac3b5 JB |
953 | { |
954 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
f99be1b3 | 955 | struct intel_digital_port *intel_dig_port = hdmi_to_dig_port(intel_hdmi); |
8c875fca | 956 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 957 | struct drm_i915_private *dev_priv = to_i915(dev); |
045ac3b5 | 958 | u32 tmp, flags = 0; |
18442d08 | 959 | int dotclock; |
045ac3b5 JB |
960 | |
961 | tmp = I915_READ(intel_hdmi->hdmi_reg); | |
962 | ||
963 | if (tmp & SDVO_HSYNC_ACTIVE_HIGH) | |
964 | flags |= DRM_MODE_FLAG_PHSYNC; | |
965 | else | |
966 | flags |= DRM_MODE_FLAG_NHSYNC; | |
967 | ||
968 | if (tmp & SDVO_VSYNC_ACTIVE_HIGH) | |
969 | flags |= DRM_MODE_FLAG_PVSYNC; | |
970 | else | |
971 | flags |= DRM_MODE_FLAG_NVSYNC; | |
972 | ||
6897b4b5 DV |
973 | if (tmp & HDMI_MODE_SELECT_HDMI) |
974 | pipe_config->has_hdmi_sink = true; | |
975 | ||
f99be1b3 | 976 | if (intel_dig_port->infoframe_enabled(&encoder->base, pipe_config)) |
e43823ec JB |
977 | pipe_config->has_infoframe = true; |
978 | ||
c84db770 | 979 | if (tmp & SDVO_AUDIO_ENABLE) |
9ed109a7 DV |
980 | pipe_config->has_audio = true; |
981 | ||
6e266956 | 982 | if (!HAS_PCH_SPLIT(dev_priv) && |
8c875fca VS |
983 | tmp & HDMI_COLOR_RANGE_16_235) |
984 | pipe_config->limited_color_range = true; | |
985 | ||
2d112de7 | 986 | pipe_config->base.adjusted_mode.flags |= flags; |
18442d08 VS |
987 | |
988 | if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) | |
989 | dotclock = pipe_config->port_clock * 2 / 3; | |
990 | else | |
991 | dotclock = pipe_config->port_clock; | |
992 | ||
be69a133 VS |
993 | if (pipe_config->pixel_multiplier) |
994 | dotclock /= pipe_config->pixel_multiplier; | |
995 | ||
2d112de7 | 996 | pipe_config->base.adjusted_mode.crtc_clock = dotclock; |
d4d6279a ACO |
997 | |
998 | pipe_config->lane_count = 4; | |
045ac3b5 JB |
999 | } |
1000 | ||
df18e721 | 1001 | static void intel_enable_hdmi_audio(struct intel_encoder *encoder, |
5f88a9c6 VS |
1002 | const struct intel_crtc_state *pipe_config, |
1003 | const struct drm_connector_state *conn_state) | |
d1b1589c | 1004 | { |
ac240288 | 1005 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); |
d1b1589c | 1006 | |
ac240288 | 1007 | WARN_ON(!pipe_config->has_hdmi_sink); |
d1b1589c VS |
1008 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", |
1009 | pipe_name(crtc->pipe)); | |
bbf35e9d | 1010 | intel_audio_codec_enable(encoder, pipe_config, conn_state); |
d1b1589c VS |
1011 | } |
1012 | ||
fd6bbda9 | 1013 | static void g4x_enable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
1014 | const struct intel_crtc_state *pipe_config, |
1015 | const struct drm_connector_state *conn_state) | |
7d57382e | 1016 | { |
5ab432ef | 1017 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 1018 | struct drm_i915_private *dev_priv = to_i915(dev); |
5ab432ef | 1019 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
7d57382e EA |
1020 | u32 temp; |
1021 | ||
b242b7f7 | 1022 | temp = I915_READ(intel_hdmi->hdmi_reg); |
d8a2d0e0 | 1023 | |
bf868c7d | 1024 | temp |= SDVO_ENABLE; |
df18e721 | 1025 | if (pipe_config->has_audio) |
bf868c7d | 1026 | temp |= SDVO_AUDIO_ENABLE; |
7a87c289 | 1027 | |
bf868c7d VS |
1028 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1029 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1030 | ||
df18e721 ML |
1031 | if (pipe_config->has_audio) |
1032 | intel_enable_hdmi_audio(encoder, pipe_config, conn_state); | |
bf868c7d VS |
1033 | } |
1034 | ||
fd6bbda9 | 1035 | static void ibx_enable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
1036 | const struct intel_crtc_state *pipe_config, |
1037 | const struct drm_connector_state *conn_state) | |
bf868c7d VS |
1038 | { |
1039 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 1040 | struct drm_i915_private *dev_priv = to_i915(dev); |
bf868c7d VS |
1041 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
1042 | u32 temp; | |
1043 | ||
1044 | temp = I915_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 | 1045 | |
bf868c7d | 1046 | temp |= SDVO_ENABLE; |
ac240288 | 1047 | if (pipe_config->has_audio) |
bf868c7d | 1048 | temp |= SDVO_AUDIO_ENABLE; |
5ab432ef | 1049 | |
bf868c7d VS |
1050 | /* |
1051 | * HW workaround, need to write this twice for issue | |
1052 | * that may result in first write getting masked. | |
1053 | */ | |
1054 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1055 | POSTING_READ(intel_hdmi->hdmi_reg); | |
b242b7f7 PZ |
1056 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1057 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef | 1058 | |
bf868c7d VS |
1059 | /* |
1060 | * HW workaround, need to toggle enable bit off and on | |
1061 | * for 12bpc with pixel repeat. | |
1062 | * | |
1063 | * FIXME: BSpec says this should be done at the end of | |
1064 | * of the modeset sequence, so not sure if this isn't too soon. | |
5ab432ef | 1065 | */ |
df18e721 ML |
1066 | if (pipe_config->pipe_bpp > 24 && |
1067 | pipe_config->pixel_multiplier > 1) { | |
bf868c7d VS |
1068 | I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); |
1069 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1070 | ||
1071 | /* | |
1072 | * HW workaround, need to write this twice for issue | |
1073 | * that may result in first write getting masked. | |
1074 | */ | |
1075 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1076 | POSTING_READ(intel_hdmi->hdmi_reg); | |
b242b7f7 PZ |
1077 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1078 | POSTING_READ(intel_hdmi->hdmi_reg); | |
7d57382e | 1079 | } |
c1dec79a | 1080 | |
df18e721 ML |
1081 | if (pipe_config->has_audio) |
1082 | intel_enable_hdmi_audio(encoder, pipe_config, conn_state); | |
d1b1589c VS |
1083 | } |
1084 | ||
fd6bbda9 | 1085 | static void cpt_enable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
1086 | const struct intel_crtc_state *pipe_config, |
1087 | const struct drm_connector_state *conn_state) | |
d1b1589c VS |
1088 | { |
1089 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 1090 | struct drm_i915_private *dev_priv = to_i915(dev); |
ac240288 | 1091 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); |
d1b1589c VS |
1092 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
1093 | enum pipe pipe = crtc->pipe; | |
1094 | u32 temp; | |
1095 | ||
1096 | temp = I915_READ(intel_hdmi->hdmi_reg); | |
1097 | ||
1098 | temp |= SDVO_ENABLE; | |
df18e721 | 1099 | if (pipe_config->has_audio) |
d1b1589c VS |
1100 | temp |= SDVO_AUDIO_ENABLE; |
1101 | ||
1102 | /* | |
1103 | * WaEnableHDMI8bpcBefore12bpc:snb,ivb | |
1104 | * | |
1105 | * The procedure for 12bpc is as follows: | |
1106 | * 1. disable HDMI clock gating | |
1107 | * 2. enable HDMI with 8bpc | |
1108 | * 3. enable HDMI with 12bpc | |
1109 | * 4. enable HDMI clock gating | |
1110 | */ | |
1111 | ||
df18e721 | 1112 | if (pipe_config->pipe_bpp > 24) { |
d1b1589c VS |
1113 | I915_WRITE(TRANS_CHICKEN1(pipe), |
1114 | I915_READ(TRANS_CHICKEN1(pipe)) | | |
1115 | TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); | |
1116 | ||
1117 | temp &= ~SDVO_COLOR_FORMAT_MASK; | |
1118 | temp |= SDVO_COLOR_FORMAT_8bpc; | |
c1dec79a | 1119 | } |
d1b1589c VS |
1120 | |
1121 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1122 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1123 | ||
df18e721 | 1124 | if (pipe_config->pipe_bpp > 24) { |
d1b1589c VS |
1125 | temp &= ~SDVO_COLOR_FORMAT_MASK; |
1126 | temp |= HDMI_COLOR_FORMAT_12bpc; | |
1127 | ||
1128 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1129 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1130 | ||
1131 | I915_WRITE(TRANS_CHICKEN1(pipe), | |
1132 | I915_READ(TRANS_CHICKEN1(pipe)) & | |
1133 | ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); | |
1134 | } | |
1135 | ||
df18e721 ML |
1136 | if (pipe_config->has_audio) |
1137 | intel_enable_hdmi_audio(encoder, pipe_config, conn_state); | |
b76cf76b | 1138 | } |
89b667f8 | 1139 | |
fd6bbda9 | 1140 | static void vlv_enable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
1141 | const struct intel_crtc_state *pipe_config, |
1142 | const struct drm_connector_state *conn_state) | |
b76cf76b | 1143 | { |
5ab432ef DV |
1144 | } |
1145 | ||
fd6bbda9 | 1146 | static void intel_disable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
1147 | const struct intel_crtc_state *old_crtc_state, |
1148 | const struct drm_connector_state *old_conn_state) | |
5ab432ef DV |
1149 | { |
1150 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 1151 | struct drm_i915_private *dev_priv = to_i915(dev); |
5ab432ef | 1152 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
f99be1b3 VS |
1153 | struct intel_digital_port *intel_dig_port = |
1154 | hdmi_to_dig_port(intel_hdmi); | |
ac240288 | 1155 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
5ab432ef | 1156 | u32 temp; |
5ab432ef | 1157 | |
b242b7f7 | 1158 | temp = I915_READ(intel_hdmi->hdmi_reg); |
5ab432ef | 1159 | |
1612c8bd | 1160 | temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE); |
b242b7f7 PZ |
1161 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1162 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1612c8bd VS |
1163 | |
1164 | /* | |
1165 | * HW workaround for IBX, we need to move the port | |
1166 | * to transcoder A after disabling it to allow the | |
1167 | * matching DP port to be enabled on transcoder A. | |
1168 | */ | |
6e266956 | 1169 | if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { |
0c241d5b VS |
1170 | /* |
1171 | * We get CPU/PCH FIFO underruns on the other pipe when | |
1172 | * doing the workaround. Sweep them under the rug. | |
1173 | */ | |
1174 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
1175 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
1176 | ||
1612c8bd VS |
1177 | temp &= ~SDVO_PIPE_B_SELECT; |
1178 | temp |= SDVO_ENABLE; | |
1179 | /* | |
1180 | * HW workaround, need to write this twice for issue | |
1181 | * that may result in first write getting masked. | |
1182 | */ | |
1183 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1184 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1185 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1186 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1187 | ||
1188 | temp &= ~SDVO_ENABLE; | |
1189 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1190 | POSTING_READ(intel_hdmi->hdmi_reg); | |
0c241d5b | 1191 | |
0f0f74bc | 1192 | intel_wait_for_vblank_if_active(dev_priv, PIPE_A); |
0c241d5b VS |
1193 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
1194 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); | |
1612c8bd | 1195 | } |
6d67415f | 1196 | |
f99be1b3 VS |
1197 | intel_dig_port->set_infoframes(&encoder->base, false, |
1198 | old_crtc_state, old_conn_state); | |
b2ccb822 VS |
1199 | |
1200 | intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); | |
7d57382e EA |
1201 | } |
1202 | ||
fd6bbda9 | 1203 | static void g4x_disable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
1204 | const struct intel_crtc_state *old_crtc_state, |
1205 | const struct drm_connector_state *old_conn_state) | |
a4790cec | 1206 | { |
df18e721 | 1207 | if (old_crtc_state->has_audio) |
a4790cec VS |
1208 | intel_audio_codec_disable(encoder); |
1209 | ||
fd6bbda9 | 1210 | intel_disable_hdmi(encoder, old_crtc_state, old_conn_state); |
a4790cec VS |
1211 | } |
1212 | ||
fd6bbda9 | 1213 | static void pch_disable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
1214 | const struct intel_crtc_state *old_crtc_state, |
1215 | const struct drm_connector_state *old_conn_state) | |
a4790cec | 1216 | { |
df18e721 | 1217 | if (old_crtc_state->has_audio) |
a4790cec VS |
1218 | intel_audio_codec_disable(encoder); |
1219 | } | |
1220 | ||
fd6bbda9 | 1221 | static void pch_post_disable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
1222 | const struct intel_crtc_state *old_crtc_state, |
1223 | const struct drm_connector_state *old_conn_state) | |
a4790cec | 1224 | { |
fd6bbda9 | 1225 | intel_disable_hdmi(encoder, old_crtc_state, old_conn_state); |
a4790cec VS |
1226 | } |
1227 | ||
b1ba124d | 1228 | static int intel_hdmi_source_max_tmds_clock(struct drm_i915_private *dev_priv) |
7d148ef5 | 1229 | { |
b1ba124d | 1230 | if (IS_G4X(dev_priv)) |
7d148ef5 | 1231 | return 165000; |
14292b7f SS |
1232 | else if (IS_GEMINILAKE(dev_priv)) |
1233 | return 594000; | |
b1ba124d | 1234 | else if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) |
7d148ef5 DV |
1235 | return 300000; |
1236 | else | |
1237 | return 225000; | |
1238 | } | |
1239 | ||
b1ba124d | 1240 | static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, |
7a5ca19f ML |
1241 | bool respect_downstream_limits, |
1242 | bool force_dvi) | |
b1ba124d VS |
1243 | { |
1244 | struct drm_device *dev = intel_hdmi_to_dev(hdmi); | |
1245 | int max_tmds_clock = intel_hdmi_source_max_tmds_clock(to_i915(dev)); | |
1246 | ||
1247 | if (respect_downstream_limits) { | |
8cadab0a VS |
1248 | struct intel_connector *connector = hdmi->attached_connector; |
1249 | const struct drm_display_info *info = &connector->base.display_info; | |
1250 | ||
b1ba124d VS |
1251 | if (hdmi->dp_dual_mode.max_tmds_clock) |
1252 | max_tmds_clock = min(max_tmds_clock, | |
1253 | hdmi->dp_dual_mode.max_tmds_clock); | |
8cadab0a VS |
1254 | |
1255 | if (info->max_tmds_clock) | |
1256 | max_tmds_clock = min(max_tmds_clock, | |
1257 | info->max_tmds_clock); | |
7a5ca19f | 1258 | else if (!hdmi->has_hdmi_sink || force_dvi) |
b1ba124d VS |
1259 | max_tmds_clock = min(max_tmds_clock, 165000); |
1260 | } | |
1261 | ||
1262 | return max_tmds_clock; | |
1263 | } | |
1264 | ||
e64e739e VS |
1265 | static enum drm_mode_status |
1266 | hdmi_port_clock_valid(struct intel_hdmi *hdmi, | |
7a5ca19f ML |
1267 | int clock, bool respect_downstream_limits, |
1268 | bool force_dvi) | |
e64e739e | 1269 | { |
e2d214ae | 1270 | struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi)); |
e64e739e VS |
1271 | |
1272 | if (clock < 25000) | |
1273 | return MODE_CLOCK_LOW; | |
7a5ca19f | 1274 | if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, force_dvi)) |
e64e739e VS |
1275 | return MODE_CLOCK_HIGH; |
1276 | ||
5e6ccc0b | 1277 | /* BXT DPLL can't generate 223-240 MHz */ |
cc3f90f0 | 1278 | if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000) |
5e6ccc0b VS |
1279 | return MODE_CLOCK_RANGE; |
1280 | ||
1281 | /* CHV DPLL can't generate 216-240 MHz */ | |
e2d214ae | 1282 | if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000) |
e64e739e VS |
1283 | return MODE_CLOCK_RANGE; |
1284 | ||
1285 | return MODE_OK; | |
1286 | } | |
1287 | ||
c19de8eb DL |
1288 | static enum drm_mode_status |
1289 | intel_hdmi_mode_valid(struct drm_connector *connector, | |
1290 | struct drm_display_mode *mode) | |
7d57382e | 1291 | { |
e64e739e VS |
1292 | struct intel_hdmi *hdmi = intel_attached_hdmi(connector); |
1293 | struct drm_device *dev = intel_hdmi_to_dev(hdmi); | |
49cff963 | 1294 | struct drm_i915_private *dev_priv = to_i915(dev); |
e64e739e VS |
1295 | enum drm_mode_status status; |
1296 | int clock; | |
587bf496 | 1297 | int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; |
7a5ca19f ML |
1298 | bool force_dvi = |
1299 | READ_ONCE(to_intel_digital_connector_state(connector->state)->force_audio) == HDMI_AUDIO_OFF_DVI; | |
e64e739e VS |
1300 | |
1301 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
1302 | return MODE_NO_DBLESCAN; | |
697c4078 | 1303 | |
e64e739e | 1304 | clock = mode->clock; |
587bf496 MK |
1305 | |
1306 | if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) | |
1307 | clock *= 2; | |
1308 | ||
1309 | if (clock > max_dotclk) | |
1310 | return MODE_CLOCK_HIGH; | |
1311 | ||
697c4078 CT |
1312 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
1313 | clock *= 2; | |
1314 | ||
b22ca995 SS |
1315 | if (drm_mode_is_420_only(&connector->display_info, mode)) |
1316 | clock /= 2; | |
1317 | ||
e64e739e | 1318 | /* check if we can do 8bpc */ |
7a5ca19f | 1319 | status = hdmi_port_clock_valid(hdmi, clock, true, force_dvi); |
7d57382e | 1320 | |
e64e739e | 1321 | /* if we can't do 8bpc we may still be able to do 12bpc */ |
7a5ca19f ML |
1322 | if (!HAS_GMCH_DISPLAY(dev_priv) && status != MODE_OK && hdmi->has_hdmi_sink && !force_dvi) |
1323 | status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true, force_dvi); | |
7d57382e | 1324 | |
e64e739e | 1325 | return status; |
7d57382e EA |
1326 | } |
1327 | ||
5f88a9c6 | 1328 | static bool hdmi_12bpc_possible(const struct intel_crtc_state *crtc_state) |
71800632 | 1329 | { |
c750bdd3 VS |
1330 | struct drm_i915_private *dev_priv = |
1331 | to_i915(crtc_state->base.crtc->dev); | |
1332 | struct drm_atomic_state *state = crtc_state->base.state; | |
1333 | struct drm_connector_state *connector_state; | |
1334 | struct drm_connector *connector; | |
1335 | int i; | |
71800632 | 1336 | |
c750bdd3 | 1337 | if (HAS_GMCH_DISPLAY(dev_priv)) |
71800632 VS |
1338 | return false; |
1339 | ||
71800632 VS |
1340 | /* |
1341 | * HDMI 12bpc affects the clocks, so it's only possible | |
1342 | * when not cloning with other encoder types. | |
1343 | */ | |
c750bdd3 VS |
1344 | if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI) |
1345 | return false; | |
1346 | ||
fe5f6b1f | 1347 | for_each_new_connector_in_state(state, connector, connector_state, i) { |
c750bdd3 VS |
1348 | const struct drm_display_info *info = &connector->display_info; |
1349 | ||
1350 | if (connector_state->crtc != crtc_state->base.crtc) | |
1351 | continue; | |
1352 | ||
60436fd4 SS |
1353 | if (crtc_state->ycbcr420) { |
1354 | const struct drm_hdmi_info *hdmi = &info->hdmi; | |
1355 | ||
1356 | if (!(hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36)) | |
1357 | return false; | |
1358 | } else { | |
1359 | if (!(info->edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_36)) | |
1360 | return false; | |
1361 | } | |
c750bdd3 VS |
1362 | } |
1363 | ||
46649d8b ACO |
1364 | /* Display Wa #1139 */ |
1365 | if (IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) && | |
1366 | crtc_state->base.adjusted_mode.htotal > 5460) | |
1367 | return false; | |
1368 | ||
c750bdd3 | 1369 | return true; |
71800632 VS |
1370 | } |
1371 | ||
60436fd4 SS |
1372 | static bool |
1373 | intel_hdmi_ycbcr420_config(struct drm_connector *connector, | |
1374 | struct intel_crtc_state *config, | |
1375 | int *clock_12bpc, int *clock_8bpc) | |
1376 | { | |
e5c05931 SS |
1377 | struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc); |
1378 | ||
60436fd4 SS |
1379 | if (!connector->ycbcr_420_allowed) { |
1380 | DRM_ERROR("Platform doesn't support YCBCR420 output\n"); | |
1381 | return false; | |
1382 | } | |
1383 | ||
1384 | /* YCBCR420 TMDS rate requirement is half the pixel clock */ | |
1385 | config->port_clock /= 2; | |
1386 | *clock_12bpc /= 2; | |
1387 | *clock_8bpc /= 2; | |
1388 | config->ycbcr420 = true; | |
e5c05931 SS |
1389 | |
1390 | /* YCBCR 420 output conversion needs a scaler */ | |
1391 | if (skl_update_scaler_crtc(config)) { | |
1392 | DRM_DEBUG_KMS("Scaler allocation for output failed\n"); | |
1393 | return false; | |
1394 | } | |
1395 | ||
1396 | intel_pch_panel_fitting(intel_crtc, config, | |
1397 | DRM_MODE_SCALE_FULLSCREEN); | |
1398 | ||
60436fd4 SS |
1399 | return true; |
1400 | } | |
1401 | ||
5bfe2ac0 | 1402 | bool intel_hdmi_compute_config(struct intel_encoder *encoder, |
0a478c27 ML |
1403 | struct intel_crtc_state *pipe_config, |
1404 | struct drm_connector_state *conn_state) | |
7d57382e | 1405 | { |
5bfe2ac0 | 1406 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
4f8036a2 | 1407 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2d112de7 | 1408 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
60436fd4 SS |
1409 | struct drm_connector *connector = conn_state->connector; |
1410 | struct drm_scdc *scdc = &connector->display_info.hdmi.scdc; | |
7a5ca19f ML |
1411 | struct intel_digital_connector_state *intel_conn_state = |
1412 | to_intel_digital_connector_state(conn_state); | |
e64e739e VS |
1413 | int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock; |
1414 | int clock_12bpc = clock_8bpc * 3 / 2; | |
e29c22c0 | 1415 | int desired_bpp; |
7a5ca19f | 1416 | bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI; |
3685a8f3 | 1417 | |
7a5ca19f | 1418 | pipe_config->has_hdmi_sink = !force_dvi && intel_hdmi->has_hdmi_sink; |
6897b4b5 | 1419 | |
e43823ec JB |
1420 | if (pipe_config->has_hdmi_sink) |
1421 | pipe_config->has_infoframe = true; | |
1422 | ||
7a5ca19f | 1423 | if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { |
55bc60db | 1424 | /* See CEA-861-E - 5.1 Default Encoding Parameters */ |
0f2a2a75 VS |
1425 | pipe_config->limited_color_range = |
1426 | pipe_config->has_hdmi_sink && | |
c8127cf0 VS |
1427 | drm_default_rgb_quant_range(adjusted_mode) == |
1428 | HDMI_QUANTIZATION_RANGE_LIMITED; | |
0f2a2a75 VS |
1429 | } else { |
1430 | pipe_config->limited_color_range = | |
7a5ca19f | 1431 | intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED; |
55bc60db VS |
1432 | } |
1433 | ||
697c4078 CT |
1434 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) { |
1435 | pipe_config->pixel_multiplier = 2; | |
e64e739e | 1436 | clock_8bpc *= 2; |
3320e37f | 1437 | clock_12bpc *= 2; |
697c4078 CT |
1438 | } |
1439 | ||
60436fd4 SS |
1440 | if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) { |
1441 | if (!intel_hdmi_ycbcr420_config(connector, pipe_config, | |
1442 | &clock_12bpc, &clock_8bpc)) { | |
1443 | DRM_ERROR("Can't support YCBCR420 output\n"); | |
1444 | return false; | |
1445 | } | |
1446 | } | |
1447 | ||
4f8036a2 | 1448 | if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv)) |
5bfe2ac0 DV |
1449 | pipe_config->has_pch_encoder = true; |
1450 | ||
7a5ca19f ML |
1451 | if (pipe_config->has_hdmi_sink) { |
1452 | if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) | |
1453 | pipe_config->has_audio = intel_hdmi->has_audio; | |
1454 | else | |
1455 | pipe_config->has_audio = | |
1456 | intel_conn_state->force_audio == HDMI_AUDIO_ON; | |
1457 | } | |
9ed109a7 | 1458 | |
4e53c2e0 DV |
1459 | /* |
1460 | * HDMI is either 12 or 8, so if the display lets 10bpc sneak | |
1461 | * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi | |
325b9d04 DV |
1462 | * outputs. We also need to check that the higher clock still fits |
1463 | * within limits. | |
4e53c2e0 | 1464 | */ |
7a5ca19f ML |
1465 | if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink && !force_dvi && |
1466 | hdmi_port_clock_valid(intel_hdmi, clock_12bpc, true, force_dvi) == MODE_OK && | |
7a0baa62 | 1467 | hdmi_12bpc_possible(pipe_config)) { |
e29c22c0 DV |
1468 | DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n"); |
1469 | desired_bpp = 12*3; | |
325b9d04 DV |
1470 | |
1471 | /* Need to adjust the port link by 1.5x for 12bpc. */ | |
ff9a6750 | 1472 | pipe_config->port_clock = clock_12bpc; |
4e53c2e0 | 1473 | } else { |
e29c22c0 DV |
1474 | DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n"); |
1475 | desired_bpp = 8*3; | |
e64e739e VS |
1476 | |
1477 | pipe_config->port_clock = clock_8bpc; | |
e29c22c0 DV |
1478 | } |
1479 | ||
1480 | if (!pipe_config->bw_constrained) { | |
b64b7a60 | 1481 | DRM_DEBUG_KMS("forcing pipe bpp to %i for HDMI\n", desired_bpp); |
e29c22c0 | 1482 | pipe_config->pipe_bpp = desired_bpp; |
4e53c2e0 DV |
1483 | } |
1484 | ||
e64e739e | 1485 | if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock, |
7a5ca19f | 1486 | false, force_dvi) != MODE_OK) { |
e64e739e | 1487 | DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n"); |
325b9d04 DV |
1488 | return false; |
1489 | } | |
1490 | ||
28b468a0 | 1491 | /* Set user selected PAR to incoming mode's member */ |
0e9f25d0 | 1492 | adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio; |
28b468a0 | 1493 | |
d4d6279a ACO |
1494 | pipe_config->lane_count = 4; |
1495 | ||
15953637 SS |
1496 | if (scdc->scrambling.supported && IS_GEMINILAKE(dev_priv)) { |
1497 | if (scdc->scrambling.low_rates) | |
1498 | pipe_config->hdmi_scrambling = true; | |
1499 | ||
1500 | if (pipe_config->port_clock > 340000) { | |
1501 | pipe_config->hdmi_scrambling = true; | |
1502 | pipe_config->hdmi_high_tmds_clock_ratio = true; | |
1503 | } | |
1504 | } | |
1505 | ||
7d57382e EA |
1506 | return true; |
1507 | } | |
1508 | ||
953ece69 CW |
1509 | static void |
1510 | intel_hdmi_unset_edid(struct drm_connector *connector) | |
9dff6af8 | 1511 | { |
df0e9248 | 1512 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
9dff6af8 | 1513 | |
953ece69 CW |
1514 | intel_hdmi->has_hdmi_sink = false; |
1515 | intel_hdmi->has_audio = false; | |
1516 | intel_hdmi->rgb_quant_range_selectable = false; | |
1517 | ||
b1ba124d VS |
1518 | intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE; |
1519 | intel_hdmi->dp_dual_mode.max_tmds_clock = 0; | |
1520 | ||
953ece69 CW |
1521 | kfree(to_intel_connector(connector)->detect_edid); |
1522 | to_intel_connector(connector)->detect_edid = NULL; | |
1523 | } | |
1524 | ||
b1ba124d | 1525 | static void |
d6199256 | 1526 | intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid) |
b1ba124d VS |
1527 | { |
1528 | struct drm_i915_private *dev_priv = to_i915(connector->dev); | |
1529 | struct intel_hdmi *hdmi = intel_attached_hdmi(connector); | |
d6199256 | 1530 | enum port port = hdmi_to_dig_port(hdmi)->port; |
b1ba124d VS |
1531 | struct i2c_adapter *adapter = |
1532 | intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); | |
1533 | enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter); | |
1534 | ||
d6199256 VS |
1535 | /* |
1536 | * Type 1 DVI adaptors are not required to implement any | |
1537 | * registers, so we can't always detect their presence. | |
1538 | * Ideally we should be able to check the state of the | |
1539 | * CONFIG1 pin, but no such luck on our hardware. | |
1540 | * | |
1541 | * The only method left to us is to check the VBT to see | |
1542 | * if the port is a dual mode capable DP port. But let's | |
1543 | * only do that when we sucesfully read the EDID, to avoid | |
1544 | * confusing log messages about DP dual mode adaptors when | |
1545 | * there's nothing connected to the port. | |
1546 | */ | |
1547 | if (type == DRM_DP_DUAL_MODE_UNKNOWN) { | |
1548 | if (has_edid && | |
1549 | intel_bios_is_port_dp_dual_mode(dev_priv, port)) { | |
1550 | DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n"); | |
1551 | type = DRM_DP_DUAL_MODE_TYPE1_DVI; | |
1552 | } else { | |
1553 | type = DRM_DP_DUAL_MODE_NONE; | |
1554 | } | |
1555 | } | |
1556 | ||
1557 | if (type == DRM_DP_DUAL_MODE_NONE) | |
b1ba124d VS |
1558 | return; |
1559 | ||
1560 | hdmi->dp_dual_mode.type = type; | |
1561 | hdmi->dp_dual_mode.max_tmds_clock = | |
1562 | drm_dp_dual_mode_max_tmds_clock(type, adapter); | |
1563 | ||
1564 | DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n", | |
1565 | drm_dp_get_dual_mode_type_name(type), | |
1566 | hdmi->dp_dual_mode.max_tmds_clock); | |
1567 | } | |
1568 | ||
953ece69 | 1569 | static bool |
23f889bd | 1570 | intel_hdmi_set_edid(struct drm_connector *connector) |
953ece69 CW |
1571 | { |
1572 | struct drm_i915_private *dev_priv = to_i915(connector->dev); | |
1573 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
23f889bd | 1574 | struct edid *edid; |
953ece69 | 1575 | bool connected = false; |
164c8598 | 1576 | |
23f889bd | 1577 | intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); |
671dedd2 | 1578 | |
23f889bd DW |
1579 | edid = drm_get_edid(connector, |
1580 | intel_gmbus_get_adapter(dev_priv, | |
1581 | intel_hdmi->ddc_bus)); | |
2ded9e27 | 1582 | |
23f889bd | 1583 | intel_hdmi_dp_dual_mode_detect(connector, edid != NULL); |
b1ba124d | 1584 | |
23f889bd | 1585 | intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); |
30ad48b7 | 1586 | |
953ece69 CW |
1587 | to_intel_connector(connector)->detect_edid = edid; |
1588 | if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { | |
1589 | intel_hdmi->rgb_quant_range_selectable = | |
1590 | drm_rgb_quant_range_selectable(edid); | |
1591 | ||
1592 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); | |
7a5ca19f | 1593 | intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid); |
953ece69 CW |
1594 | |
1595 | connected = true; | |
55b7d6e8 CW |
1596 | } |
1597 | ||
953ece69 CW |
1598 | return connected; |
1599 | } | |
1600 | ||
8166fcea DV |
1601 | static enum drm_connector_status |
1602 | intel_hdmi_detect(struct drm_connector *connector, bool force) | |
953ece69 | 1603 | { |
8166fcea | 1604 | enum drm_connector_status status; |
8166fcea | 1605 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
953ece69 | 1606 | |
8166fcea DV |
1607 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
1608 | connector->base.id, connector->name); | |
1609 | ||
29bb94bb ID |
1610 | intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); |
1611 | ||
8166fcea | 1612 | intel_hdmi_unset_edid(connector); |
0b5e88dc | 1613 | |
23f889bd | 1614 | if (intel_hdmi_set_edid(connector)) { |
953ece69 CW |
1615 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
1616 | ||
1617 | hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; | |
1618 | status = connector_status_connected; | |
8166fcea | 1619 | } else |
953ece69 | 1620 | status = connector_status_disconnected; |
671dedd2 | 1621 | |
29bb94bb ID |
1622 | intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); |
1623 | ||
2ded9e27 | 1624 | return status; |
7d57382e EA |
1625 | } |
1626 | ||
953ece69 CW |
1627 | static void |
1628 | intel_hdmi_force(struct drm_connector *connector) | |
7d57382e | 1629 | { |
953ece69 | 1630 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
7d57382e | 1631 | |
953ece69 CW |
1632 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
1633 | connector->base.id, connector->name); | |
7d57382e | 1634 | |
953ece69 | 1635 | intel_hdmi_unset_edid(connector); |
671dedd2 | 1636 | |
953ece69 CW |
1637 | if (connector->status != connector_status_connected) |
1638 | return; | |
671dedd2 | 1639 | |
23f889bd | 1640 | intel_hdmi_set_edid(connector); |
953ece69 CW |
1641 | hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; |
1642 | } | |
671dedd2 | 1643 | |
953ece69 CW |
1644 | static int intel_hdmi_get_modes(struct drm_connector *connector) |
1645 | { | |
1646 | struct edid *edid; | |
1647 | ||
1648 | edid = to_intel_connector(connector)->detect_edid; | |
1649 | if (edid == NULL) | |
1650 | return 0; | |
671dedd2 | 1651 | |
953ece69 | 1652 | return intel_connector_update_modes(connector, edid); |
7d57382e EA |
1653 | } |
1654 | ||
fd6bbda9 | 1655 | static void intel_hdmi_pre_enable(struct intel_encoder *encoder, |
5f88a9c6 VS |
1656 | const struct intel_crtc_state *pipe_config, |
1657 | const struct drm_connector_state *conn_state) | |
13732ba7 | 1658 | { |
f99be1b3 VS |
1659 | struct intel_digital_port *intel_dig_port = |
1660 | enc_to_dig_port(&encoder->base); | |
13732ba7 | 1661 | |
ac240288 | 1662 | intel_hdmi_prepare(encoder, pipe_config); |
4cde8a21 | 1663 | |
f99be1b3 VS |
1664 | intel_dig_port->set_infoframes(&encoder->base, |
1665 | pipe_config->has_infoframe, | |
1666 | pipe_config, conn_state); | |
13732ba7 JB |
1667 | } |
1668 | ||
fd6bbda9 | 1669 | static void vlv_hdmi_pre_enable(struct intel_encoder *encoder, |
5f88a9c6 VS |
1670 | const struct intel_crtc_state *pipe_config, |
1671 | const struct drm_connector_state *conn_state) | |
89b667f8 JB |
1672 | { |
1673 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1674 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 1675 | struct drm_i915_private *dev_priv = to_i915(dev); |
5f68c275 ACO |
1676 | |
1677 | vlv_phy_pre_encoder_enable(encoder); | |
b76cf76b | 1678 | |
53d98725 ACO |
1679 | /* HDMI 1.0V-2dB */ |
1680 | vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a, | |
1681 | 0x2b247878); | |
1682 | ||
f99be1b3 VS |
1683 | dport->set_infoframes(&encoder->base, |
1684 | pipe_config->has_infoframe, | |
1685 | pipe_config, conn_state); | |
13732ba7 | 1686 | |
fd6bbda9 | 1687 | g4x_enable_hdmi(encoder, pipe_config, conn_state); |
b76cf76b | 1688 | |
9b6de0a1 | 1689 | vlv_wait_port_ready(dev_priv, dport, 0x0); |
89b667f8 JB |
1690 | } |
1691 | ||
fd6bbda9 | 1692 | static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder, |
5f88a9c6 VS |
1693 | const struct intel_crtc_state *pipe_config, |
1694 | const struct drm_connector_state *conn_state) | |
89b667f8 | 1695 | { |
ac240288 | 1696 | intel_hdmi_prepare(encoder, pipe_config); |
4cde8a21 | 1697 | |
6da2e616 | 1698 | vlv_phy_pre_pll_enable(encoder); |
89b667f8 JB |
1699 | } |
1700 | ||
fd6bbda9 | 1701 | static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder, |
5f88a9c6 VS |
1702 | const struct intel_crtc_state *pipe_config, |
1703 | const struct drm_connector_state *conn_state) | |
9197c88b | 1704 | { |
ac240288 | 1705 | intel_hdmi_prepare(encoder, pipe_config); |
625695f8 | 1706 | |
419b1b7a | 1707 | chv_phy_pre_pll_enable(encoder); |
9197c88b VS |
1708 | } |
1709 | ||
fd6bbda9 | 1710 | static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder, |
5f88a9c6 VS |
1711 | const struct intel_crtc_state *old_crtc_state, |
1712 | const struct drm_connector_state *old_conn_state) | |
d6db995f | 1713 | { |
204970b5 | 1714 | chv_phy_post_pll_disable(encoder); |
d6db995f VS |
1715 | } |
1716 | ||
fd6bbda9 | 1717 | static void vlv_hdmi_post_disable(struct intel_encoder *encoder, |
5f88a9c6 VS |
1718 | const struct intel_crtc_state *old_crtc_state, |
1719 | const struct drm_connector_state *old_conn_state) | |
89b667f8 | 1720 | { |
89b667f8 | 1721 | /* Reset lanes to avoid HDMI flicker (VLV w/a) */ |
0f572ebe | 1722 | vlv_phy_reset_lanes(encoder); |
89b667f8 JB |
1723 | } |
1724 | ||
fd6bbda9 | 1725 | static void chv_hdmi_post_disable(struct intel_encoder *encoder, |
5f88a9c6 VS |
1726 | const struct intel_crtc_state *old_crtc_state, |
1727 | const struct drm_connector_state *old_conn_state) | |
580d3811 | 1728 | { |
580d3811 | 1729 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 1730 | struct drm_i915_private *dev_priv = to_i915(dev); |
580d3811 | 1731 | |
a580516d | 1732 | mutex_lock(&dev_priv->sb_lock); |
580d3811 | 1733 | |
a8f327fb VS |
1734 | /* Assert data lane reset */ |
1735 | chv_data_lane_soft_reset(encoder, true); | |
580d3811 | 1736 | |
a580516d | 1737 | mutex_unlock(&dev_priv->sb_lock); |
580d3811 VS |
1738 | } |
1739 | ||
fd6bbda9 | 1740 | static void chv_hdmi_pre_enable(struct intel_encoder *encoder, |
5f88a9c6 VS |
1741 | const struct intel_crtc_state *pipe_config, |
1742 | const struct drm_connector_state *conn_state) | |
e4a1d846 CML |
1743 | { |
1744 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1745 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 1746 | struct drm_i915_private *dev_priv = to_i915(dev); |
2e523e98 | 1747 | |
e7d2a717 | 1748 | chv_phy_pre_encoder_enable(encoder); |
a02ef3c7 | 1749 | |
e4a1d846 CML |
1750 | /* FIXME: Program the support xxx V-dB */ |
1751 | /* Use 800mV-0dB */ | |
b7fa22d8 | 1752 | chv_set_phy_signal_level(encoder, 128, 102, false); |
e4a1d846 | 1753 | |
f99be1b3 VS |
1754 | dport->set_infoframes(&encoder->base, |
1755 | pipe_config->has_infoframe, | |
1756 | pipe_config, conn_state); | |
b4eb1564 | 1757 | |
fd6bbda9 | 1758 | g4x_enable_hdmi(encoder, pipe_config, conn_state); |
e4a1d846 | 1759 | |
9b6de0a1 | 1760 | vlv_wait_port_ready(dev_priv, dport, 0x0); |
b0b33846 VS |
1761 | |
1762 | /* Second common lane will stay alive on its own now */ | |
e7d2a717 | 1763 | chv_phy_release_cl2_override(encoder); |
e4a1d846 CML |
1764 | } |
1765 | ||
7d57382e EA |
1766 | static void intel_hdmi_destroy(struct drm_connector *connector) |
1767 | { | |
10e972d3 | 1768 | kfree(to_intel_connector(connector)->detect_edid); |
7d57382e | 1769 | drm_connector_cleanup(connector); |
674e2d08 | 1770 | kfree(connector); |
7d57382e EA |
1771 | } |
1772 | ||
7d57382e | 1773 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { |
7d57382e | 1774 | .detect = intel_hdmi_detect, |
953ece69 | 1775 | .force = intel_hdmi_force, |
7d57382e | 1776 | .fill_modes = drm_helper_probe_single_connector_modes, |
7a5ca19f ML |
1777 | .atomic_get_property = intel_digital_connector_atomic_get_property, |
1778 | .atomic_set_property = intel_digital_connector_atomic_set_property, | |
1ebaa0b9 | 1779 | .late_register = intel_connector_register, |
c191eca1 | 1780 | .early_unregister = intel_connector_unregister, |
7d57382e | 1781 | .destroy = intel_hdmi_destroy, |
c6f95f27 | 1782 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
7a5ca19f | 1783 | .atomic_duplicate_state = intel_digital_connector_duplicate_state, |
7d57382e EA |
1784 | }; |
1785 | ||
1786 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { | |
1787 | .get_modes = intel_hdmi_get_modes, | |
1788 | .mode_valid = intel_hdmi_mode_valid, | |
7a5ca19f | 1789 | .atomic_check = intel_digital_connector_atomic_check, |
7d57382e EA |
1790 | }; |
1791 | ||
7d57382e | 1792 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
ea5b213a | 1793 | .destroy = intel_encoder_destroy, |
7d57382e EA |
1794 | }; |
1795 | ||
55b7d6e8 CW |
1796 | static void |
1797 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) | |
1798 | { | |
3f43c48d | 1799 | intel_attach_force_audio_property(connector); |
e953fd7b | 1800 | intel_attach_broadcast_rgb_property(connector); |
94a11ddc | 1801 | intel_attach_aspect_ratio_property(connector); |
0e9f25d0 | 1802 | connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE; |
55b7d6e8 CW |
1803 | } |
1804 | ||
15953637 SS |
1805 | /* |
1806 | * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup | |
1807 | * @encoder: intel_encoder | |
1808 | * @connector: drm_connector | |
1809 | * @high_tmds_clock_ratio = bool to indicate if the function needs to set | |
1810 | * or reset the high tmds clock ratio for scrambling | |
1811 | * @scrambling: bool to Indicate if the function needs to set or reset | |
1812 | * sink scrambling | |
1813 | * | |
1814 | * This function handles scrambling on HDMI 2.0 capable sinks. | |
1815 | * If required clock rate is > 340 Mhz && scrambling is supported by sink | |
1816 | * it enables scrambling. This should be called before enabling the HDMI | |
1817 | * 2.0 port, as the sink can choose to disable the scrambling if it doesn't | |
1818 | * detect a scrambled clock within 100 ms. | |
1819 | */ | |
1820 | void intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder, | |
1821 | struct drm_connector *connector, | |
1822 | bool high_tmds_clock_ratio, | |
1823 | bool scrambling) | |
1824 | { | |
1825 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
1826 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
1827 | struct drm_scrambling *sink_scrambling = | |
1828 | &connector->display_info.hdmi.scdc.scrambling; | |
1829 | struct i2c_adapter *adptr = intel_gmbus_get_adapter(dev_priv, | |
1830 | intel_hdmi->ddc_bus); | |
1831 | bool ret; | |
1832 | ||
1833 | if (!sink_scrambling->supported) | |
1834 | return; | |
1835 | ||
1836 | DRM_DEBUG_KMS("Setting sink scrambling for enc:%s connector:%s\n", | |
1837 | encoder->base.name, connector->name); | |
1838 | ||
1839 | /* Set TMDS bit clock ratio to 1/40 or 1/10 */ | |
1840 | ret = drm_scdc_set_high_tmds_clock_ratio(adptr, high_tmds_clock_ratio); | |
1841 | if (!ret) { | |
1842 | DRM_ERROR("Set TMDS ratio failed\n"); | |
1843 | return; | |
1844 | } | |
1845 | ||
1846 | /* Enable/disable sink scrambling */ | |
1847 | ret = drm_scdc_set_scrambling(adptr, scrambling); | |
1848 | if (!ret) { | |
1849 | DRM_ERROR("Set sink scrambling failed\n"); | |
1850 | return; | |
1851 | } | |
1852 | ||
1853 | DRM_DEBUG_KMS("sink scrambling handled\n"); | |
1854 | } | |
1855 | ||
cec3bb01 | 1856 | static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) |
e4ab73a1 | 1857 | { |
e4ab73a1 VS |
1858 | u8 ddc_pin; |
1859 | ||
cec3bb01 AS |
1860 | switch (port) { |
1861 | case PORT_B: | |
1862 | ddc_pin = GMBUS_PIN_DPB; | |
1863 | break; | |
1864 | case PORT_C: | |
1865 | ddc_pin = GMBUS_PIN_DPC; | |
1866 | break; | |
1867 | case PORT_D: | |
1868 | ddc_pin = GMBUS_PIN_DPD_CHV; | |
1869 | break; | |
1870 | default: | |
1871 | MISSING_CASE(port); | |
1872 | ddc_pin = GMBUS_PIN_DPB; | |
1873 | break; | |
e4ab73a1 | 1874 | } |
cec3bb01 AS |
1875 | return ddc_pin; |
1876 | } | |
1877 | ||
1878 | static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) | |
1879 | { | |
1880 | u8 ddc_pin; | |
e4ab73a1 VS |
1881 | |
1882 | switch (port) { | |
1883 | case PORT_B: | |
cec3bb01 | 1884 | ddc_pin = GMBUS_PIN_1_BXT; |
e4ab73a1 VS |
1885 | break; |
1886 | case PORT_C: | |
cec3bb01 AS |
1887 | ddc_pin = GMBUS_PIN_2_BXT; |
1888 | break; | |
1889 | default: | |
1890 | MISSING_CASE(port); | |
1891 | ddc_pin = GMBUS_PIN_1_BXT; | |
1892 | break; | |
1893 | } | |
1894 | return ddc_pin; | |
1895 | } | |
1896 | ||
1897 | static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv, | |
1898 | enum port port) | |
1899 | { | |
1900 | u8 ddc_pin; | |
1901 | ||
1902 | switch (port) { | |
1903 | case PORT_B: | |
1904 | ddc_pin = GMBUS_PIN_1_BXT; | |
1905 | break; | |
1906 | case PORT_C: | |
1907 | ddc_pin = GMBUS_PIN_2_BXT; | |
e4ab73a1 VS |
1908 | break; |
1909 | case PORT_D: | |
cec3bb01 AS |
1910 | ddc_pin = GMBUS_PIN_4_CNP; |
1911 | break; | |
1912 | default: | |
1913 | MISSING_CASE(port); | |
1914 | ddc_pin = GMBUS_PIN_1_BXT; | |
1915 | break; | |
1916 | } | |
1917 | return ddc_pin; | |
1918 | } | |
1919 | ||
1920 | static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv, | |
1921 | enum port port) | |
1922 | { | |
1923 | u8 ddc_pin; | |
1924 | ||
1925 | switch (port) { | |
1926 | case PORT_B: | |
1927 | ddc_pin = GMBUS_PIN_DPB; | |
1928 | break; | |
1929 | case PORT_C: | |
1930 | ddc_pin = GMBUS_PIN_DPC; | |
1931 | break; | |
1932 | case PORT_D: | |
1933 | ddc_pin = GMBUS_PIN_DPD; | |
e4ab73a1 VS |
1934 | break; |
1935 | default: | |
1936 | MISSING_CASE(port); | |
1937 | ddc_pin = GMBUS_PIN_DPB; | |
1938 | break; | |
1939 | } | |
cec3bb01 AS |
1940 | return ddc_pin; |
1941 | } | |
1942 | ||
1943 | static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv, | |
1944 | enum port port) | |
1945 | { | |
1946 | const struct ddi_vbt_port_info *info = | |
1947 | &dev_priv->vbt.ddi_port_info[port]; | |
1948 | u8 ddc_pin; | |
1949 | ||
1950 | if (info->alternate_ddc_pin) { | |
1951 | DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n", | |
1952 | info->alternate_ddc_pin, port_name(port)); | |
1953 | return info->alternate_ddc_pin; | |
1954 | } | |
1955 | ||
1956 | if (IS_CHERRYVIEW(dev_priv)) | |
1957 | ddc_pin = chv_port_to_ddc_pin(dev_priv, port); | |
1958 | else if (IS_GEN9_LP(dev_priv)) | |
1959 | ddc_pin = bxt_port_to_ddc_pin(dev_priv, port); | |
1960 | else if (HAS_PCH_CNP(dev_priv)) | |
1961 | ddc_pin = cnp_port_to_ddc_pin(dev_priv, port); | |
1962 | else | |
1963 | ddc_pin = g4x_port_to_ddc_pin(dev_priv, port); | |
e4ab73a1 VS |
1964 | |
1965 | DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n", | |
1966 | ddc_pin, port_name(port)); | |
1967 | ||
1968 | return ddc_pin; | |
1969 | } | |
1970 | ||
385e4de0 VS |
1971 | void intel_infoframe_init(struct intel_digital_port *intel_dig_port) |
1972 | { | |
1973 | struct drm_i915_private *dev_priv = | |
1974 | to_i915(intel_dig_port->base.base.dev); | |
1975 | ||
1976 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { | |
1977 | intel_dig_port->write_infoframe = vlv_write_infoframe; | |
1978 | intel_dig_port->set_infoframes = vlv_set_infoframes; | |
1979 | intel_dig_port->infoframe_enabled = vlv_infoframe_enabled; | |
1980 | } else if (IS_G4X(dev_priv)) { | |
1981 | intel_dig_port->write_infoframe = g4x_write_infoframe; | |
1982 | intel_dig_port->set_infoframes = g4x_set_infoframes; | |
1983 | intel_dig_port->infoframe_enabled = g4x_infoframe_enabled; | |
1984 | } else if (HAS_DDI(dev_priv)) { | |
1985 | intel_dig_port->write_infoframe = hsw_write_infoframe; | |
1986 | intel_dig_port->set_infoframes = hsw_set_infoframes; | |
1987 | intel_dig_port->infoframe_enabled = hsw_infoframe_enabled; | |
1988 | } else if (HAS_PCH_IBX(dev_priv)) { | |
1989 | intel_dig_port->write_infoframe = ibx_write_infoframe; | |
1990 | intel_dig_port->set_infoframes = ibx_set_infoframes; | |
1991 | intel_dig_port->infoframe_enabled = ibx_infoframe_enabled; | |
1992 | } else { | |
1993 | intel_dig_port->write_infoframe = cpt_write_infoframe; | |
1994 | intel_dig_port->set_infoframes = cpt_set_infoframes; | |
1995 | intel_dig_port->infoframe_enabled = cpt_infoframe_enabled; | |
1996 | } | |
1997 | } | |
1998 | ||
00c09d70 PZ |
1999 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
2000 | struct intel_connector *intel_connector) | |
7d57382e | 2001 | { |
b9cb234c PZ |
2002 | struct drm_connector *connector = &intel_connector->base; |
2003 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
2004 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
2005 | struct drm_device *dev = intel_encoder->base.dev; | |
fac5e23e | 2006 | struct drm_i915_private *dev_priv = to_i915(dev); |
174edf1f | 2007 | enum port port = intel_dig_port->port; |
373a3cf7 | 2008 | |
22f35042 VS |
2009 | DRM_DEBUG_KMS("Adding HDMI connector on port %c\n", |
2010 | port_name(port)); | |
2011 | ||
ccb1a831 VS |
2012 | if (WARN(intel_dig_port->max_lanes < 4, |
2013 | "Not enough lanes (%d) for HDMI on port %c\n", | |
2014 | intel_dig_port->max_lanes, port_name(port))) | |
2015 | return; | |
2016 | ||
7d57382e | 2017 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
8d91104a | 2018 | DRM_MODE_CONNECTOR_HDMIA); |
7d57382e EA |
2019 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
2020 | ||
c3febcc4 | 2021 | connector->interlace_allowed = 1; |
7d57382e | 2022 | connector->doublescan_allowed = 0; |
573e74ad | 2023 | connector->stereo_allowed = 1; |
66a9278e | 2024 | |
eadc2e51 SS |
2025 | if (IS_GEMINILAKE(dev_priv)) |
2026 | connector->ycbcr_420_allowed = true; | |
2027 | ||
e4ab73a1 VS |
2028 | intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port); |
2029 | ||
f761bef2 | 2030 | if (WARN_ON(port == PORT_A)) |
e4ab73a1 | 2031 | return; |
f761bef2 | 2032 | intel_encoder->hpd_pin = intel_hpd_pin(port); |
7d57382e | 2033 | |
4f8036a2 | 2034 | if (HAS_DDI(dev_priv)) |
bcbc889b PZ |
2035 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
2036 | else | |
2037 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
b9cb234c PZ |
2038 | |
2039 | intel_hdmi_add_properties(intel_hdmi, connector); | |
2040 | ||
2041 | intel_connector_attach_encoder(intel_connector, intel_encoder); | |
d8b4c43a | 2042 | intel_hdmi->attached_connector = intel_connector; |
b9cb234c PZ |
2043 | |
2044 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written | |
2045 | * 0xd. Failure to do so will result in spurious interrupts being | |
2046 | * generated on the port when a cable is not attached. | |
2047 | */ | |
50a0bc90 | 2048 | if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) { |
b9cb234c PZ |
2049 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
2050 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
2051 | } | |
2052 | } | |
2053 | ||
c39055b0 | 2054 | void intel_hdmi_init(struct drm_i915_private *dev_priv, |
f0f59a00 | 2055 | i915_reg_t hdmi_reg, enum port port) |
b9cb234c PZ |
2056 | { |
2057 | struct intel_digital_port *intel_dig_port; | |
2058 | struct intel_encoder *intel_encoder; | |
b9cb234c PZ |
2059 | struct intel_connector *intel_connector; |
2060 | ||
b14c5679 | 2061 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
b9cb234c PZ |
2062 | if (!intel_dig_port) |
2063 | return; | |
2064 | ||
08d9bc92 | 2065 | intel_connector = intel_connector_alloc(); |
b9cb234c PZ |
2066 | if (!intel_connector) { |
2067 | kfree(intel_dig_port); | |
2068 | return; | |
2069 | } | |
2070 | ||
2071 | intel_encoder = &intel_dig_port->base; | |
b9cb234c | 2072 | |
c39055b0 ACO |
2073 | drm_encoder_init(&dev_priv->drm, &intel_encoder->base, |
2074 | &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS, | |
2075 | "HDMI %c", port_name(port)); | |
00c09d70 | 2076 | |
5bfe2ac0 | 2077 | intel_encoder->compute_config = intel_hdmi_compute_config; |
6e266956 | 2078 | if (HAS_PCH_SPLIT(dev_priv)) { |
a4790cec VS |
2079 | intel_encoder->disable = pch_disable_hdmi; |
2080 | intel_encoder->post_disable = pch_post_disable_hdmi; | |
2081 | } else { | |
2082 | intel_encoder->disable = g4x_disable_hdmi; | |
2083 | } | |
00c09d70 | 2084 | intel_encoder->get_hw_state = intel_hdmi_get_hw_state; |
045ac3b5 | 2085 | intel_encoder->get_config = intel_hdmi_get_config; |
920a14b2 | 2086 | if (IS_CHERRYVIEW(dev_priv)) { |
9197c88b | 2087 | intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable; |
e4a1d846 CML |
2088 | intel_encoder->pre_enable = chv_hdmi_pre_enable; |
2089 | intel_encoder->enable = vlv_enable_hdmi; | |
580d3811 | 2090 | intel_encoder->post_disable = chv_hdmi_post_disable; |
d6db995f | 2091 | intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable; |
11a914c2 | 2092 | } else if (IS_VALLEYVIEW(dev_priv)) { |
9514ac6e CML |
2093 | intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; |
2094 | intel_encoder->pre_enable = vlv_hdmi_pre_enable; | |
b76cf76b | 2095 | intel_encoder->enable = vlv_enable_hdmi; |
9514ac6e | 2096 | intel_encoder->post_disable = vlv_hdmi_post_disable; |
b76cf76b | 2097 | } else { |
13732ba7 | 2098 | intel_encoder->pre_enable = intel_hdmi_pre_enable; |
6e266956 | 2099 | if (HAS_PCH_CPT(dev_priv)) |
d1b1589c | 2100 | intel_encoder->enable = cpt_enable_hdmi; |
6e266956 | 2101 | else if (HAS_PCH_IBX(dev_priv)) |
bf868c7d | 2102 | intel_encoder->enable = ibx_enable_hdmi; |
d1b1589c | 2103 | else |
bf868c7d | 2104 | intel_encoder->enable = g4x_enable_hdmi; |
89b667f8 | 2105 | } |
5ab432ef | 2106 | |
b9cb234c | 2107 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
79f255a0 | 2108 | intel_encoder->power_domain = intel_port_to_power_domain(port); |
03cdc1d4 | 2109 | intel_encoder->port = port; |
920a14b2 | 2110 | if (IS_CHERRYVIEW(dev_priv)) { |
882ec384 VS |
2111 | if (port == PORT_D) |
2112 | intel_encoder->crtc_mask = 1 << 2; | |
2113 | else | |
2114 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
2115 | } else { | |
2116 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
2117 | } | |
301ea74a | 2118 | intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG; |
c6f1495d VS |
2119 | /* |
2120 | * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems | |
2121 | * to work on real hardware. And since g4x can send infoframes to | |
2122 | * only one port anyway, nothing is lost by allowing it. | |
2123 | */ | |
9beb5fea | 2124 | if (IS_G4X(dev_priv)) |
c6f1495d | 2125 | intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI; |
7d57382e | 2126 | |
174edf1f | 2127 | intel_dig_port->port = port; |
b242b7f7 | 2128 | intel_dig_port->hdmi.hdmi_reg = hdmi_reg; |
f0f59a00 | 2129 | intel_dig_port->dp.output_reg = INVALID_MMIO_REG; |
ccb1a831 | 2130 | intel_dig_port->max_lanes = 4; |
55b7d6e8 | 2131 | |
385e4de0 VS |
2132 | intel_infoframe_init(intel_dig_port); |
2133 | ||
b9cb234c | 2134 | intel_hdmi_init_connector(intel_dig_port, intel_connector); |
7d57382e | 2135 | } |