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b20385f1 OM |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * Michel Thierry <michel.thierry@intel.com> | |
26 | * Thomas Daniel <thomas.daniel@intel.com> | |
27 | * Oscar Mateo <oscar.mateo@intel.com> | |
28 | * | |
29 | */ | |
30 | ||
73e4d07f OM |
31 | /** |
32 | * DOC: Logical Rings, Logical Ring Contexts and Execlists | |
33 | * | |
34 | * Motivation: | |
b20385f1 OM |
35 | * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts". |
36 | * These expanded contexts enable a number of new abilities, especially | |
37 | * "Execlists" (also implemented in this file). | |
38 | * | |
73e4d07f OM |
39 | * One of the main differences with the legacy HW contexts is that logical |
40 | * ring contexts incorporate many more things to the context's state, like | |
41 | * PDPs or ringbuffer control registers: | |
42 | * | |
43 | * The reason why PDPs are included in the context is straightforward: as | |
44 | * PPGTTs (per-process GTTs) are actually per-context, having the PDPs | |
45 | * contained there mean you don't need to do a ppgtt->switch_mm yourself, | |
46 | * instead, the GPU will do it for you on the context switch. | |
47 | * | |
48 | * But, what about the ringbuffer control registers (head, tail, etc..)? | |
49 | * shouldn't we just need a set of those per engine command streamer? This is | |
50 | * where the name "Logical Rings" starts to make sense: by virtualizing the | |
51 | * rings, the engine cs shifts to a new "ring buffer" with every context | |
52 | * switch. When you want to submit a workload to the GPU you: A) choose your | |
53 | * context, B) find its appropriate virtualized ring, C) write commands to it | |
54 | * and then, finally, D) tell the GPU to switch to that context. | |
55 | * | |
56 | * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch | |
57 | * to a contexts is via a context execution list, ergo "Execlists". | |
58 | * | |
59 | * LRC implementation: | |
60 | * Regarding the creation of contexts, we have: | |
61 | * | |
62 | * - One global default context. | |
63 | * - One local default context for each opened fd. | |
64 | * - One local extra context for each context create ioctl call. | |
65 | * | |
66 | * Now that ringbuffers belong per-context (and not per-engine, like before) | |
67 | * and that contexts are uniquely tied to a given engine (and not reusable, | |
68 | * like before) we need: | |
69 | * | |
70 | * - One ringbuffer per-engine inside each context. | |
71 | * - One backing object per-engine inside each context. | |
72 | * | |
73 | * The global default context starts its life with these new objects fully | |
74 | * allocated and populated. The local default context for each opened fd is | |
75 | * more complex, because we don't know at creation time which engine is going | |
76 | * to use them. To handle this, we have implemented a deferred creation of LR | |
77 | * contexts: | |
78 | * | |
79 | * The local context starts its life as a hollow or blank holder, that only | |
80 | * gets populated for a given engine once we receive an execbuffer. If later | |
81 | * on we receive another execbuffer ioctl for the same context but a different | |
82 | * engine, we allocate/populate a new ringbuffer and context backing object and | |
83 | * so on. | |
84 | * | |
85 | * Finally, regarding local contexts created using the ioctl call: as they are | |
86 | * only allowed with the render ring, we can allocate & populate them right | |
87 | * away (no need to defer anything, at least for now). | |
88 | * | |
89 | * Execlists implementation: | |
b20385f1 OM |
90 | * Execlists are the new method by which, on gen8+ hardware, workloads are |
91 | * submitted for execution (as opposed to the legacy, ringbuffer-based, method). | |
73e4d07f OM |
92 | * This method works as follows: |
93 | * | |
94 | * When a request is committed, its commands (the BB start and any leading or | |
95 | * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer | |
96 | * for the appropriate context. The tail pointer in the hardware context is not | |
97 | * updated at this time, but instead, kept by the driver in the ringbuffer | |
98 | * structure. A structure representing this request is added to a request queue | |
99 | * for the appropriate engine: this structure contains a copy of the context's | |
100 | * tail after the request was written to the ring buffer and a pointer to the | |
101 | * context itself. | |
102 | * | |
103 | * If the engine's request queue was empty before the request was added, the | |
104 | * queue is processed immediately. Otherwise the queue will be processed during | |
105 | * a context switch interrupt. In any case, elements on the queue will get sent | |
106 | * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a | |
107 | * globally unique 20-bits submission ID. | |
108 | * | |
109 | * When execution of a request completes, the GPU updates the context status | |
110 | * buffer with a context complete event and generates a context switch interrupt. | |
111 | * During the interrupt handling, the driver examines the events in the buffer: | |
112 | * for each context complete event, if the announced ID matches that on the head | |
113 | * of the request queue, then that request is retired and removed from the queue. | |
114 | * | |
115 | * After processing, if any requests were retired and the queue is not empty | |
116 | * then a new execution list can be submitted. The two requests at the front of | |
117 | * the queue are next to be submitted but since a context may not occur twice in | |
118 | * an execution list, if subsequent requests have the same ID as the first then | |
119 | * the two requests must be combined. This is done simply by discarding requests | |
120 | * at the head of the queue until either only one requests is left (in which case | |
121 | * we use a NULL second context) or the first two requests have unique IDs. | |
122 | * | |
123 | * By always executing the first two requests in the queue the driver ensures | |
124 | * that the GPU is kept as busy as possible. In the case where a single context | |
125 | * completes but a second context is still executing, the request for this second | |
126 | * context will be at the head of the queue when we remove the first one. This | |
127 | * request will then be resubmitted along with a new request for a different context, | |
128 | * which will cause the hardware to continue executing the second request and queue | |
129 | * the new request (the GPU detects the condition of a context getting preempted | |
130 | * with the same context and optimizes the context switch flow by not doing | |
131 | * preemption, but just sampling the new tail pointer). | |
132 | * | |
b20385f1 OM |
133 | */ |
134 | ||
135 | #include <drm/drmP.h> | |
136 | #include <drm/i915_drm.h> | |
137 | #include "i915_drv.h" | |
127f1003 | 138 | |
468c6816 | 139 | #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE) |
8c857917 OM |
140 | #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE) |
141 | #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE) | |
142 | ||
143 | #define GEN8_LR_CONTEXT_ALIGN 4096 | |
144 | ||
e981e7b1 TD |
145 | #define RING_EXECLIST_QFULL (1 << 0x2) |
146 | #define RING_EXECLIST1_VALID (1 << 0x3) | |
147 | #define RING_EXECLIST0_VALID (1 << 0x4) | |
148 | #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE) | |
149 | #define RING_EXECLIST1_ACTIVE (1 << 0x11) | |
150 | #define RING_EXECLIST0_ACTIVE (1 << 0x12) | |
151 | ||
152 | #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0) | |
153 | #define GEN8_CTX_STATUS_PREEMPTED (1 << 1) | |
154 | #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2) | |
155 | #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3) | |
156 | #define GEN8_CTX_STATUS_COMPLETE (1 << 4) | |
157 | #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15) | |
8670d6f9 OM |
158 | |
159 | #define CTX_LRI_HEADER_0 0x01 | |
160 | #define CTX_CONTEXT_CONTROL 0x02 | |
161 | #define CTX_RING_HEAD 0x04 | |
162 | #define CTX_RING_TAIL 0x06 | |
163 | #define CTX_RING_BUFFER_START 0x08 | |
164 | #define CTX_RING_BUFFER_CONTROL 0x0a | |
165 | #define CTX_BB_HEAD_U 0x0c | |
166 | #define CTX_BB_HEAD_L 0x0e | |
167 | #define CTX_BB_STATE 0x10 | |
168 | #define CTX_SECOND_BB_HEAD_U 0x12 | |
169 | #define CTX_SECOND_BB_HEAD_L 0x14 | |
170 | #define CTX_SECOND_BB_STATE 0x16 | |
171 | #define CTX_BB_PER_CTX_PTR 0x18 | |
172 | #define CTX_RCS_INDIRECT_CTX 0x1a | |
173 | #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c | |
174 | #define CTX_LRI_HEADER_1 0x21 | |
175 | #define CTX_CTX_TIMESTAMP 0x22 | |
176 | #define CTX_PDP3_UDW 0x24 | |
177 | #define CTX_PDP3_LDW 0x26 | |
178 | #define CTX_PDP2_UDW 0x28 | |
179 | #define CTX_PDP2_LDW 0x2a | |
180 | #define CTX_PDP1_UDW 0x2c | |
181 | #define CTX_PDP1_LDW 0x2e | |
182 | #define CTX_PDP0_UDW 0x30 | |
183 | #define CTX_PDP0_LDW 0x32 | |
184 | #define CTX_LRI_HEADER_2 0x41 | |
185 | #define CTX_R_PWR_CLK_STATE 0x42 | |
186 | #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44 | |
187 | ||
84b790f8 BW |
188 | #define GEN8_CTX_VALID (1<<0) |
189 | #define GEN8_CTX_FORCE_PD_RESTORE (1<<1) | |
190 | #define GEN8_CTX_FORCE_RESTORE (1<<2) | |
191 | #define GEN8_CTX_L3LLC_COHERENT (1<<5) | |
192 | #define GEN8_CTX_PRIVILEGE (1<<8) | |
193 | enum { | |
194 | ADVANCED_CONTEXT = 0, | |
195 | LEGACY_CONTEXT, | |
196 | ADVANCED_AD_CONTEXT, | |
197 | LEGACY_64B_CONTEXT | |
198 | }; | |
199 | #define GEN8_CTX_MODE_SHIFT 3 | |
200 | enum { | |
201 | FAULT_AND_HANG = 0, | |
202 | FAULT_AND_HALT, /* Debug only */ | |
203 | FAULT_AND_STREAM, | |
204 | FAULT_AND_CONTINUE /* Unsupported */ | |
205 | }; | |
206 | #define GEN8_CTX_ID_SHIFT 32 | |
207 | ||
73e4d07f OM |
208 | /** |
209 | * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists | |
210 | * @dev: DRM device. | |
211 | * @enable_execlists: value of i915.enable_execlists module parameter. | |
212 | * | |
213 | * Only certain platforms support Execlists (the prerequisites being | |
214 | * support for Logical Ring Contexts and Aliasing PPGTT or better), | |
215 | * and only when enabled via module parameter. | |
216 | * | |
217 | * Return: 1 if Execlists is supported and has to be enabled. | |
218 | */ | |
127f1003 OM |
219 | int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists) |
220 | { | |
bd84b1e9 DV |
221 | WARN_ON(i915.enable_ppgtt == -1); |
222 | ||
70ee45e1 DL |
223 | if (INTEL_INFO(dev)->gen >= 9) |
224 | return 1; | |
225 | ||
127f1003 OM |
226 | if (enable_execlists == 0) |
227 | return 0; | |
228 | ||
14bf993e OM |
229 | if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) && |
230 | i915.use_mmio_flip >= 0) | |
127f1003 OM |
231 | return 1; |
232 | ||
233 | return 0; | |
234 | } | |
ede7d42b | 235 | |
73e4d07f OM |
236 | /** |
237 | * intel_execlists_ctx_id() - get the Execlists Context ID | |
238 | * @ctx_obj: Logical Ring Context backing object. | |
239 | * | |
240 | * Do not confuse with ctx->id! Unfortunately we have a name overload | |
241 | * here: the old context ID we pass to userspace as a handler so that | |
242 | * they can refer to a context, and the new context ID we pass to the | |
243 | * ELSP so that the GPU can inform us of the context status via | |
244 | * interrupts. | |
245 | * | |
246 | * Return: 20-bits globally unique context ID. | |
247 | */ | |
84b790f8 BW |
248 | u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj) |
249 | { | |
250 | u32 lrca = i915_gem_obj_ggtt_offset(ctx_obj); | |
251 | ||
252 | /* LRCA is required to be 4K aligned so the more significant 20 bits | |
253 | * are globally unique */ | |
254 | return lrca >> 12; | |
255 | } | |
256 | ||
257 | static uint64_t execlists_ctx_descriptor(struct drm_i915_gem_object *ctx_obj) | |
258 | { | |
259 | uint64_t desc; | |
260 | uint64_t lrca = i915_gem_obj_ggtt_offset(ctx_obj); | |
acdd884a MT |
261 | |
262 | WARN_ON(lrca & 0xFFFFFFFF00000FFFULL); | |
84b790f8 BW |
263 | |
264 | desc = GEN8_CTX_VALID; | |
265 | desc |= LEGACY_CONTEXT << GEN8_CTX_MODE_SHIFT; | |
266 | desc |= GEN8_CTX_L3LLC_COHERENT; | |
267 | desc |= GEN8_CTX_PRIVILEGE; | |
268 | desc |= lrca; | |
269 | desc |= (u64)intel_execlists_ctx_id(ctx_obj) << GEN8_CTX_ID_SHIFT; | |
270 | ||
271 | /* TODO: WaDisableLiteRestore when we start using semaphore | |
272 | * signalling between Command Streamers */ | |
273 | /* desc |= GEN8_CTX_FORCE_RESTORE; */ | |
274 | ||
275 | return desc; | |
276 | } | |
277 | ||
278 | static void execlists_elsp_write(struct intel_engine_cs *ring, | |
279 | struct drm_i915_gem_object *ctx_obj0, | |
280 | struct drm_i915_gem_object *ctx_obj1) | |
281 | { | |
6e7cc470 TU |
282 | struct drm_device *dev = ring->dev; |
283 | struct drm_i915_private *dev_priv = dev->dev_private; | |
84b790f8 BW |
284 | uint64_t temp = 0; |
285 | uint32_t desc[4]; | |
e981e7b1 | 286 | unsigned long flags; |
84b790f8 BW |
287 | |
288 | /* XXX: You must always write both descriptors in the order below. */ | |
289 | if (ctx_obj1) | |
290 | temp = execlists_ctx_descriptor(ctx_obj1); | |
291 | else | |
292 | temp = 0; | |
293 | desc[1] = (u32)(temp >> 32); | |
294 | desc[0] = (u32)temp; | |
295 | ||
296 | temp = execlists_ctx_descriptor(ctx_obj0); | |
297 | desc[3] = (u32)(temp >> 32); | |
298 | desc[2] = (u32)temp; | |
299 | ||
e981e7b1 TD |
300 | /* Set Force Wakeup bit to prevent GT from entering C6 while ELSP writes |
301 | * are in progress. | |
302 | * | |
303 | * The other problem is that we can't just call gen6_gt_force_wake_get() | |
304 | * because that function calls intel_runtime_pm_get(), which might sleep. | |
305 | * Instead, we do the runtime_pm_get/put when creating/destroying requests. | |
306 | */ | |
307 | spin_lock_irqsave(&dev_priv->uncore.lock, flags); | |
6e7cc470 | 308 | if (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen >= 9) { |
a01b0e94 D |
309 | if (dev_priv->uncore.fw_rendercount++ == 0) |
310 | dev_priv->uncore.funcs.force_wake_get(dev_priv, | |
311 | FORCEWAKE_RENDER); | |
312 | if (dev_priv->uncore.fw_mediacount++ == 0) | |
313 | dev_priv->uncore.funcs.force_wake_get(dev_priv, | |
314 | FORCEWAKE_MEDIA); | |
6e7cc470 TU |
315 | if (INTEL_INFO(dev)->gen >= 9) { |
316 | if (dev_priv->uncore.fw_blittercount++ == 0) | |
317 | dev_priv->uncore.funcs.force_wake_get(dev_priv, | |
318 | FORCEWAKE_BLITTER); | |
319 | } | |
a01b0e94 D |
320 | } else { |
321 | if (dev_priv->uncore.forcewake_count++ == 0) | |
322 | dev_priv->uncore.funcs.force_wake_get(dev_priv, | |
323 | FORCEWAKE_ALL); | |
324 | } | |
e981e7b1 | 325 | spin_unlock_irqrestore(&dev_priv->uncore.lock, flags); |
84b790f8 BW |
326 | |
327 | I915_WRITE(RING_ELSP(ring), desc[1]); | |
328 | I915_WRITE(RING_ELSP(ring), desc[0]); | |
329 | I915_WRITE(RING_ELSP(ring), desc[3]); | |
330 | /* The context is automatically loaded after the following */ | |
331 | I915_WRITE(RING_ELSP(ring), desc[2]); | |
332 | ||
333 | /* ELSP is a wo register, so use another nearby reg for posting instead */ | |
334 | POSTING_READ(RING_EXECLIST_STATUS(ring)); | |
335 | ||
e981e7b1 TD |
336 | /* Release Force Wakeup (see the big comment above). */ |
337 | spin_lock_irqsave(&dev_priv->uncore.lock, flags); | |
6e7cc470 | 338 | if (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen >= 9) { |
a01b0e94 D |
339 | if (--dev_priv->uncore.fw_rendercount == 0) |
340 | dev_priv->uncore.funcs.force_wake_put(dev_priv, | |
341 | FORCEWAKE_RENDER); | |
342 | if (--dev_priv->uncore.fw_mediacount == 0) | |
343 | dev_priv->uncore.funcs.force_wake_put(dev_priv, | |
344 | FORCEWAKE_MEDIA); | |
6e7cc470 TU |
345 | if (INTEL_INFO(dev)->gen >= 9) { |
346 | if (--dev_priv->uncore.fw_blittercount == 0) | |
347 | dev_priv->uncore.funcs.force_wake_put(dev_priv, | |
348 | FORCEWAKE_BLITTER); | |
349 | } | |
a01b0e94 D |
350 | } else { |
351 | if (--dev_priv->uncore.forcewake_count == 0) | |
352 | dev_priv->uncore.funcs.force_wake_put(dev_priv, | |
353 | FORCEWAKE_ALL); | |
354 | } | |
355 | ||
e981e7b1 | 356 | spin_unlock_irqrestore(&dev_priv->uncore.lock, flags); |
84b790f8 BW |
357 | } |
358 | ||
ae1250b9 OM |
359 | static int execlists_ctx_write_tail(struct drm_i915_gem_object *ctx_obj, u32 tail) |
360 | { | |
361 | struct page *page; | |
362 | uint32_t *reg_state; | |
363 | ||
364 | page = i915_gem_object_get_page(ctx_obj, 1); | |
365 | reg_state = kmap_atomic(page); | |
366 | ||
367 | reg_state[CTX_RING_TAIL+1] = tail; | |
368 | ||
369 | kunmap_atomic(reg_state); | |
370 | ||
371 | return 0; | |
372 | } | |
373 | ||
cd0707cb DG |
374 | static void execlists_submit_contexts(struct intel_engine_cs *ring, |
375 | struct intel_context *to0, u32 tail0, | |
376 | struct intel_context *to1, u32 tail1) | |
84b790f8 BW |
377 | { |
378 | struct drm_i915_gem_object *ctx_obj0; | |
379 | struct drm_i915_gem_object *ctx_obj1 = NULL; | |
380 | ||
381 | ctx_obj0 = to0->engine[ring->id].state; | |
382 | BUG_ON(!ctx_obj0); | |
acdd884a | 383 | WARN_ON(!i915_gem_obj_is_pinned(ctx_obj0)); |
84b790f8 | 384 | |
ae1250b9 OM |
385 | execlists_ctx_write_tail(ctx_obj0, tail0); |
386 | ||
84b790f8 BW |
387 | if (to1) { |
388 | ctx_obj1 = to1->engine[ring->id].state; | |
389 | BUG_ON(!ctx_obj1); | |
acdd884a | 390 | WARN_ON(!i915_gem_obj_is_pinned(ctx_obj1)); |
ae1250b9 OM |
391 | |
392 | execlists_ctx_write_tail(ctx_obj1, tail1); | |
84b790f8 BW |
393 | } |
394 | ||
395 | execlists_elsp_write(ring, ctx_obj0, ctx_obj1); | |
84b790f8 BW |
396 | } |
397 | ||
acdd884a MT |
398 | static void execlists_context_unqueue(struct intel_engine_cs *ring) |
399 | { | |
400 | struct intel_ctx_submit_request *req0 = NULL, *req1 = NULL; | |
401 | struct intel_ctx_submit_request *cursor = NULL, *tmp = NULL; | |
e981e7b1 TD |
402 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
403 | ||
404 | assert_spin_locked(&ring->execlist_lock); | |
acdd884a MT |
405 | |
406 | if (list_empty(&ring->execlist_queue)) | |
407 | return; | |
408 | ||
409 | /* Try to read in pairs */ | |
410 | list_for_each_entry_safe(cursor, tmp, &ring->execlist_queue, | |
411 | execlist_link) { | |
412 | if (!req0) { | |
413 | req0 = cursor; | |
414 | } else if (req0->ctx == cursor->ctx) { | |
415 | /* Same ctx: ignore first request, as second request | |
416 | * will update tail past first request's workload */ | |
e1fee72c | 417 | cursor->elsp_submitted = req0->elsp_submitted; |
acdd884a | 418 | list_del(&req0->execlist_link); |
e981e7b1 | 419 | queue_work(dev_priv->wq, &req0->work); |
acdd884a MT |
420 | req0 = cursor; |
421 | } else { | |
422 | req1 = cursor; | |
423 | break; | |
424 | } | |
425 | } | |
426 | ||
e1fee72c OM |
427 | WARN_ON(req1 && req1->elsp_submitted); |
428 | ||
cd0707cb DG |
429 | execlists_submit_contexts(ring, req0->ctx, req0->tail, |
430 | req1 ? req1->ctx : NULL, | |
431 | req1 ? req1->tail : 0); | |
e1fee72c OM |
432 | |
433 | req0->elsp_submitted++; | |
434 | if (req1) | |
435 | req1->elsp_submitted++; | |
acdd884a MT |
436 | } |
437 | ||
e981e7b1 TD |
438 | static bool execlists_check_remove_request(struct intel_engine_cs *ring, |
439 | u32 request_id) | |
440 | { | |
441 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
442 | struct intel_ctx_submit_request *head_req; | |
443 | ||
444 | assert_spin_locked(&ring->execlist_lock); | |
445 | ||
446 | head_req = list_first_entry_or_null(&ring->execlist_queue, | |
447 | struct intel_ctx_submit_request, | |
448 | execlist_link); | |
449 | ||
450 | if (head_req != NULL) { | |
451 | struct drm_i915_gem_object *ctx_obj = | |
452 | head_req->ctx->engine[ring->id].state; | |
453 | if (intel_execlists_ctx_id(ctx_obj) == request_id) { | |
e1fee72c OM |
454 | WARN(head_req->elsp_submitted == 0, |
455 | "Never submitted head request\n"); | |
456 | ||
457 | if (--head_req->elsp_submitted <= 0) { | |
458 | list_del(&head_req->execlist_link); | |
459 | queue_work(dev_priv->wq, &head_req->work); | |
460 | return true; | |
461 | } | |
e981e7b1 TD |
462 | } |
463 | } | |
464 | ||
465 | return false; | |
466 | } | |
467 | ||
73e4d07f OM |
468 | /** |
469 | * intel_execlists_handle_ctx_events() - handle Context Switch interrupts | |
470 | * @ring: Engine Command Streamer to handle. | |
471 | * | |
472 | * Check the unread Context Status Buffers and manage the submission of new | |
473 | * contexts to the ELSP accordingly. | |
474 | */ | |
e981e7b1 TD |
475 | void intel_execlists_handle_ctx_events(struct intel_engine_cs *ring) |
476 | { | |
477 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
478 | u32 status_pointer; | |
479 | u8 read_pointer; | |
480 | u8 write_pointer; | |
481 | u32 status; | |
482 | u32 status_id; | |
483 | u32 submit_contexts = 0; | |
484 | ||
485 | status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring)); | |
486 | ||
487 | read_pointer = ring->next_context_status_buffer; | |
488 | write_pointer = status_pointer & 0x07; | |
489 | if (read_pointer > write_pointer) | |
490 | write_pointer += 6; | |
491 | ||
492 | spin_lock(&ring->execlist_lock); | |
493 | ||
494 | while (read_pointer < write_pointer) { | |
495 | read_pointer++; | |
496 | status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + | |
497 | (read_pointer % 6) * 8); | |
498 | status_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + | |
499 | (read_pointer % 6) * 8 + 4); | |
500 | ||
e1fee72c OM |
501 | if (status & GEN8_CTX_STATUS_PREEMPTED) { |
502 | if (status & GEN8_CTX_STATUS_LITE_RESTORE) { | |
503 | if (execlists_check_remove_request(ring, status_id)) | |
504 | WARN(1, "Lite Restored request removed from queue\n"); | |
505 | } else | |
506 | WARN(1, "Preemption without Lite Restore\n"); | |
507 | } | |
508 | ||
509 | if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) || | |
510 | (status & GEN8_CTX_STATUS_ELEMENT_SWITCH)) { | |
e981e7b1 TD |
511 | if (execlists_check_remove_request(ring, status_id)) |
512 | submit_contexts++; | |
513 | } | |
514 | } | |
515 | ||
516 | if (submit_contexts != 0) | |
517 | execlists_context_unqueue(ring); | |
518 | ||
519 | spin_unlock(&ring->execlist_lock); | |
520 | ||
521 | WARN(submit_contexts > 2, "More than two context complete events?\n"); | |
522 | ring->next_context_status_buffer = write_pointer % 6; | |
523 | ||
524 | I915_WRITE(RING_CONTEXT_STATUS_PTR(ring), | |
525 | ((u32)ring->next_context_status_buffer & 0x07) << 8); | |
526 | } | |
527 | ||
528 | static void execlists_free_request_task(struct work_struct *work) | |
529 | { | |
530 | struct intel_ctx_submit_request *req = | |
531 | container_of(work, struct intel_ctx_submit_request, work); | |
532 | struct drm_device *dev = req->ring->dev; | |
533 | struct drm_i915_private *dev_priv = dev->dev_private; | |
534 | ||
535 | intel_runtime_pm_put(dev_priv); | |
536 | ||
537 | mutex_lock(&dev->struct_mutex); | |
538 | i915_gem_context_unreference(req->ctx); | |
539 | mutex_unlock(&dev->struct_mutex); | |
540 | ||
541 | kfree(req); | |
542 | } | |
543 | ||
acdd884a MT |
544 | static int execlists_context_queue(struct intel_engine_cs *ring, |
545 | struct intel_context *to, | |
546 | u32 tail) | |
547 | { | |
f1ad5a1f | 548 | struct intel_ctx_submit_request *req = NULL, *cursor; |
e981e7b1 | 549 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
acdd884a | 550 | unsigned long flags; |
f1ad5a1f | 551 | int num_elements = 0; |
acdd884a MT |
552 | |
553 | req = kzalloc(sizeof(*req), GFP_KERNEL); | |
554 | if (req == NULL) | |
555 | return -ENOMEM; | |
556 | req->ctx = to; | |
557 | i915_gem_context_reference(req->ctx); | |
558 | req->ring = ring; | |
559 | req->tail = tail; | |
e981e7b1 TD |
560 | INIT_WORK(&req->work, execlists_free_request_task); |
561 | ||
562 | intel_runtime_pm_get(dev_priv); | |
acdd884a MT |
563 | |
564 | spin_lock_irqsave(&ring->execlist_lock, flags); | |
565 | ||
f1ad5a1f OM |
566 | list_for_each_entry(cursor, &ring->execlist_queue, execlist_link) |
567 | if (++num_elements > 2) | |
568 | break; | |
569 | ||
570 | if (num_elements > 2) { | |
571 | struct intel_ctx_submit_request *tail_req; | |
572 | ||
573 | tail_req = list_last_entry(&ring->execlist_queue, | |
574 | struct intel_ctx_submit_request, | |
575 | execlist_link); | |
576 | ||
577 | if (to == tail_req->ctx) { | |
578 | WARN(tail_req->elsp_submitted != 0, | |
579 | "More than 2 already-submitted reqs queued\n"); | |
580 | list_del(&tail_req->execlist_link); | |
581 | queue_work(dev_priv->wq, &tail_req->work); | |
582 | } | |
583 | } | |
584 | ||
acdd884a | 585 | list_add_tail(&req->execlist_link, &ring->execlist_queue); |
f1ad5a1f | 586 | if (num_elements == 0) |
acdd884a MT |
587 | execlists_context_unqueue(ring); |
588 | ||
589 | spin_unlock_irqrestore(&ring->execlist_lock, flags); | |
590 | ||
591 | return 0; | |
592 | } | |
593 | ||
ba8b7ccb OM |
594 | static int logical_ring_invalidate_all_caches(struct intel_ringbuffer *ringbuf) |
595 | { | |
596 | struct intel_engine_cs *ring = ringbuf->ring; | |
597 | uint32_t flush_domains; | |
598 | int ret; | |
599 | ||
600 | flush_domains = 0; | |
601 | if (ring->gpu_caches_dirty) | |
602 | flush_domains = I915_GEM_GPU_DOMAINS; | |
603 | ||
604 | ret = ring->emit_flush(ringbuf, I915_GEM_GPU_DOMAINS, flush_domains); | |
605 | if (ret) | |
606 | return ret; | |
607 | ||
608 | ring->gpu_caches_dirty = false; | |
609 | return 0; | |
610 | } | |
611 | ||
612 | static int execlists_move_to_gpu(struct intel_ringbuffer *ringbuf, | |
613 | struct list_head *vmas) | |
614 | { | |
615 | struct intel_engine_cs *ring = ringbuf->ring; | |
616 | struct i915_vma *vma; | |
617 | uint32_t flush_domains = 0; | |
618 | bool flush_chipset = false; | |
619 | int ret; | |
620 | ||
621 | list_for_each_entry(vma, vmas, exec_list) { | |
622 | struct drm_i915_gem_object *obj = vma->obj; | |
623 | ||
624 | ret = i915_gem_object_sync(obj, ring); | |
625 | if (ret) | |
626 | return ret; | |
627 | ||
628 | if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) | |
629 | flush_chipset |= i915_gem_clflush_object(obj, false); | |
630 | ||
631 | flush_domains |= obj->base.write_domain; | |
632 | } | |
633 | ||
634 | if (flush_domains & I915_GEM_DOMAIN_GTT) | |
635 | wmb(); | |
636 | ||
637 | /* Unconditionally invalidate gpu caches and ensure that we do flush | |
638 | * any residual writes from the previous batch. | |
639 | */ | |
640 | return logical_ring_invalidate_all_caches(ringbuf); | |
641 | } | |
642 | ||
73e4d07f OM |
643 | /** |
644 | * execlists_submission() - submit a batchbuffer for execution, Execlists style | |
645 | * @dev: DRM device. | |
646 | * @file: DRM file. | |
647 | * @ring: Engine Command Streamer to submit to. | |
648 | * @ctx: Context to employ for this submission. | |
649 | * @args: execbuffer call arguments. | |
650 | * @vmas: list of vmas. | |
651 | * @batch_obj: the batchbuffer to submit. | |
652 | * @exec_start: batchbuffer start virtual address pointer. | |
653 | * @flags: translated execbuffer call flags. | |
654 | * | |
655 | * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts | |
656 | * away the submission details of the execbuffer ioctl call. | |
657 | * | |
658 | * Return: non-zero if the submission fails. | |
659 | */ | |
454afebd OM |
660 | int intel_execlists_submission(struct drm_device *dev, struct drm_file *file, |
661 | struct intel_engine_cs *ring, | |
662 | struct intel_context *ctx, | |
663 | struct drm_i915_gem_execbuffer2 *args, | |
664 | struct list_head *vmas, | |
665 | struct drm_i915_gem_object *batch_obj, | |
666 | u64 exec_start, u32 flags) | |
667 | { | |
ba8b7ccb OM |
668 | struct drm_i915_private *dev_priv = dev->dev_private; |
669 | struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf; | |
670 | int instp_mode; | |
671 | u32 instp_mask; | |
672 | int ret; | |
673 | ||
674 | instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK; | |
675 | instp_mask = I915_EXEC_CONSTANTS_MASK; | |
676 | switch (instp_mode) { | |
677 | case I915_EXEC_CONSTANTS_REL_GENERAL: | |
678 | case I915_EXEC_CONSTANTS_ABSOLUTE: | |
679 | case I915_EXEC_CONSTANTS_REL_SURFACE: | |
680 | if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) { | |
681 | DRM_DEBUG("non-0 rel constants mode on non-RCS\n"); | |
682 | return -EINVAL; | |
683 | } | |
684 | ||
685 | if (instp_mode != dev_priv->relative_constants_mode) { | |
686 | if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) { | |
687 | DRM_DEBUG("rel surface constants mode invalid on gen5+\n"); | |
688 | return -EINVAL; | |
689 | } | |
690 | ||
691 | /* The HW changed the meaning on this bit on gen6 */ | |
692 | instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; | |
693 | } | |
694 | break; | |
695 | default: | |
696 | DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode); | |
697 | return -EINVAL; | |
698 | } | |
699 | ||
700 | if (args->num_cliprects != 0) { | |
701 | DRM_DEBUG("clip rectangles are only valid on pre-gen5\n"); | |
702 | return -EINVAL; | |
703 | } else { | |
704 | if (args->DR4 == 0xffffffff) { | |
705 | DRM_DEBUG("UXA submitting garbage DR4, fixing up\n"); | |
706 | args->DR4 = 0; | |
707 | } | |
708 | ||
709 | if (args->DR1 || args->DR4 || args->cliprects_ptr) { | |
710 | DRM_DEBUG("0 cliprects but dirt in cliprects fields\n"); | |
711 | return -EINVAL; | |
712 | } | |
713 | } | |
714 | ||
715 | if (args->flags & I915_EXEC_GEN7_SOL_RESET) { | |
716 | DRM_DEBUG("sol reset is gen7 only\n"); | |
717 | return -EINVAL; | |
718 | } | |
719 | ||
720 | ret = execlists_move_to_gpu(ringbuf, vmas); | |
721 | if (ret) | |
722 | return ret; | |
723 | ||
724 | if (ring == &dev_priv->ring[RCS] && | |
725 | instp_mode != dev_priv->relative_constants_mode) { | |
726 | ret = intel_logical_ring_begin(ringbuf, 4); | |
727 | if (ret) | |
728 | return ret; | |
729 | ||
730 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
731 | intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1)); | |
732 | intel_logical_ring_emit(ringbuf, INSTPM); | |
733 | intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode); | |
734 | intel_logical_ring_advance(ringbuf); | |
735 | ||
736 | dev_priv->relative_constants_mode = instp_mode; | |
737 | } | |
738 | ||
739 | ret = ring->emit_bb_start(ringbuf, exec_start, flags); | |
740 | if (ret) | |
741 | return ret; | |
742 | ||
743 | i915_gem_execbuffer_move_to_active(vmas, ring); | |
744 | i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj); | |
745 | ||
454afebd OM |
746 | return 0; |
747 | } | |
748 | ||
749 | void intel_logical_ring_stop(struct intel_engine_cs *ring) | |
750 | { | |
9832b9da OM |
751 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
752 | int ret; | |
753 | ||
754 | if (!intel_ring_initialized(ring)) | |
755 | return; | |
756 | ||
757 | ret = intel_ring_idle(ring); | |
758 | if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error)) | |
759 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", | |
760 | ring->name, ret); | |
761 | ||
762 | /* TODO: Is this correct with Execlists enabled? */ | |
763 | I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING)); | |
764 | if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) { | |
765 | DRM_ERROR("%s :timed out trying to stop ring\n", ring->name); | |
766 | return; | |
767 | } | |
768 | I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING)); | |
454afebd OM |
769 | } |
770 | ||
48e29f55 OM |
771 | int logical_ring_flush_all_caches(struct intel_ringbuffer *ringbuf) |
772 | { | |
773 | struct intel_engine_cs *ring = ringbuf->ring; | |
774 | int ret; | |
775 | ||
776 | if (!ring->gpu_caches_dirty) | |
777 | return 0; | |
778 | ||
779 | ret = ring->emit_flush(ringbuf, 0, I915_GEM_GPU_DOMAINS); | |
780 | if (ret) | |
781 | return ret; | |
782 | ||
783 | ring->gpu_caches_dirty = false; | |
784 | return 0; | |
785 | } | |
786 | ||
73e4d07f OM |
787 | /** |
788 | * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload | |
789 | * @ringbuf: Logical Ringbuffer to advance. | |
790 | * | |
791 | * The tail is updated in our logical ringbuffer struct, not in the actual context. What | |
792 | * really happens during submission is that the context and current tail will be placed | |
793 | * on a queue waiting for the ELSP to be ready to accept a new context submission. At that | |
794 | * point, the tail *inside* the context is updated and the ELSP written to. | |
795 | */ | |
82e104cc OM |
796 | void intel_logical_ring_advance_and_submit(struct intel_ringbuffer *ringbuf) |
797 | { | |
84b790f8 BW |
798 | struct intel_engine_cs *ring = ringbuf->ring; |
799 | struct intel_context *ctx = ringbuf->FIXME_lrc_ctx; | |
800 | ||
82e104cc OM |
801 | intel_logical_ring_advance(ringbuf); |
802 | ||
84b790f8 | 803 | if (intel_ring_stopped(ring)) |
82e104cc OM |
804 | return; |
805 | ||
acdd884a | 806 | execlists_context_queue(ring, ctx, ringbuf->tail); |
82e104cc OM |
807 | } |
808 | ||
48e29f55 OM |
809 | static int logical_ring_alloc_seqno(struct intel_engine_cs *ring, |
810 | struct intel_context *ctx) | |
82e104cc OM |
811 | { |
812 | if (ring->outstanding_lazy_seqno) | |
813 | return 0; | |
814 | ||
815 | if (ring->preallocated_lazy_request == NULL) { | |
816 | struct drm_i915_gem_request *request; | |
817 | ||
818 | request = kmalloc(sizeof(*request), GFP_KERNEL); | |
819 | if (request == NULL) | |
820 | return -ENOMEM; | |
821 | ||
48e29f55 OM |
822 | /* Hold a reference to the context this request belongs to |
823 | * (we will need it when the time comes to emit/retire the | |
824 | * request). | |
825 | */ | |
826 | request->ctx = ctx; | |
827 | i915_gem_context_reference(request->ctx); | |
828 | ||
82e104cc OM |
829 | ring->preallocated_lazy_request = request; |
830 | } | |
831 | ||
832 | return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno); | |
833 | } | |
834 | ||
835 | static int logical_ring_wait_request(struct intel_ringbuffer *ringbuf, | |
836 | int bytes) | |
837 | { | |
838 | struct intel_engine_cs *ring = ringbuf->ring; | |
839 | struct drm_i915_gem_request *request; | |
840 | u32 seqno = 0; | |
841 | int ret; | |
842 | ||
843 | if (ringbuf->last_retired_head != -1) { | |
844 | ringbuf->head = ringbuf->last_retired_head; | |
845 | ringbuf->last_retired_head = -1; | |
846 | ||
847 | ringbuf->space = intel_ring_space(ringbuf); | |
848 | if (ringbuf->space >= bytes) | |
849 | return 0; | |
850 | } | |
851 | ||
852 | list_for_each_entry(request, &ring->request_list, list) { | |
853 | if (__intel_ring_space(request->tail, ringbuf->tail, | |
854 | ringbuf->size) >= bytes) { | |
855 | seqno = request->seqno; | |
856 | break; | |
857 | } | |
858 | } | |
859 | ||
860 | if (seqno == 0) | |
861 | return -ENOSPC; | |
862 | ||
863 | ret = i915_wait_seqno(ring, seqno); | |
864 | if (ret) | |
865 | return ret; | |
866 | ||
82e104cc OM |
867 | i915_gem_retire_requests_ring(ring); |
868 | ringbuf->head = ringbuf->last_retired_head; | |
869 | ringbuf->last_retired_head = -1; | |
870 | ||
871 | ringbuf->space = intel_ring_space(ringbuf); | |
872 | return 0; | |
873 | } | |
874 | ||
875 | static int logical_ring_wait_for_space(struct intel_ringbuffer *ringbuf, | |
876 | int bytes) | |
877 | { | |
878 | struct intel_engine_cs *ring = ringbuf->ring; | |
879 | struct drm_device *dev = ring->dev; | |
880 | struct drm_i915_private *dev_priv = dev->dev_private; | |
881 | unsigned long end; | |
882 | int ret; | |
883 | ||
884 | ret = logical_ring_wait_request(ringbuf, bytes); | |
885 | if (ret != -ENOSPC) | |
886 | return ret; | |
887 | ||
888 | /* Force the context submission in case we have been skipping it */ | |
889 | intel_logical_ring_advance_and_submit(ringbuf); | |
890 | ||
891 | /* With GEM the hangcheck timer should kick us out of the loop, | |
892 | * leaving it early runs the risk of corrupting GEM state (due | |
893 | * to running on almost untested codepaths). But on resume | |
894 | * timers don't work yet, so prevent a complete hang in that | |
895 | * case by choosing an insanely large timeout. */ | |
896 | end = jiffies + 60 * HZ; | |
897 | ||
898 | do { | |
899 | ringbuf->head = I915_READ_HEAD(ring); | |
900 | ringbuf->space = intel_ring_space(ringbuf); | |
901 | if (ringbuf->space >= bytes) { | |
902 | ret = 0; | |
903 | break; | |
904 | } | |
905 | ||
906 | msleep(1); | |
907 | ||
908 | if (dev_priv->mm.interruptible && signal_pending(current)) { | |
909 | ret = -ERESTARTSYS; | |
910 | break; | |
911 | } | |
912 | ||
913 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, | |
914 | dev_priv->mm.interruptible); | |
915 | if (ret) | |
916 | break; | |
917 | ||
918 | if (time_after(jiffies, end)) { | |
919 | ret = -EBUSY; | |
920 | break; | |
921 | } | |
922 | } while (1); | |
923 | ||
924 | return ret; | |
925 | } | |
926 | ||
927 | static int logical_ring_wrap_buffer(struct intel_ringbuffer *ringbuf) | |
928 | { | |
929 | uint32_t __iomem *virt; | |
930 | int rem = ringbuf->size - ringbuf->tail; | |
931 | ||
932 | if (ringbuf->space < rem) { | |
933 | int ret = logical_ring_wait_for_space(ringbuf, rem); | |
934 | ||
935 | if (ret) | |
936 | return ret; | |
937 | } | |
938 | ||
939 | virt = ringbuf->virtual_start + ringbuf->tail; | |
940 | rem /= 4; | |
941 | while (rem--) | |
942 | iowrite32(MI_NOOP, virt++); | |
943 | ||
944 | ringbuf->tail = 0; | |
945 | ringbuf->space = intel_ring_space(ringbuf); | |
946 | ||
947 | return 0; | |
948 | } | |
949 | ||
950 | static int logical_ring_prepare(struct intel_ringbuffer *ringbuf, int bytes) | |
951 | { | |
952 | int ret; | |
953 | ||
954 | if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) { | |
955 | ret = logical_ring_wrap_buffer(ringbuf); | |
956 | if (unlikely(ret)) | |
957 | return ret; | |
958 | } | |
959 | ||
960 | if (unlikely(ringbuf->space < bytes)) { | |
961 | ret = logical_ring_wait_for_space(ringbuf, bytes); | |
962 | if (unlikely(ret)) | |
963 | return ret; | |
964 | } | |
965 | ||
966 | return 0; | |
967 | } | |
968 | ||
73e4d07f OM |
969 | /** |
970 | * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands | |
971 | * | |
972 | * @ringbuf: Logical ringbuffer. | |
973 | * @num_dwords: number of DWORDs that we plan to write to the ringbuffer. | |
974 | * | |
975 | * The ringbuffer might not be ready to accept the commands right away (maybe it needs to | |
976 | * be wrapped, or wait a bit for the tail to be updated). This function takes care of that | |
977 | * and also preallocates a request (every workload submission is still mediated through | |
978 | * requests, same as it did with legacy ringbuffer submission). | |
979 | * | |
980 | * Return: non-zero if the ringbuffer is not ready to be written to. | |
981 | */ | |
82e104cc OM |
982 | int intel_logical_ring_begin(struct intel_ringbuffer *ringbuf, int num_dwords) |
983 | { | |
984 | struct intel_engine_cs *ring = ringbuf->ring; | |
985 | struct drm_device *dev = ring->dev; | |
986 | struct drm_i915_private *dev_priv = dev->dev_private; | |
987 | int ret; | |
988 | ||
989 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, | |
990 | dev_priv->mm.interruptible); | |
991 | if (ret) | |
992 | return ret; | |
993 | ||
994 | ret = logical_ring_prepare(ringbuf, num_dwords * sizeof(uint32_t)); | |
995 | if (ret) | |
996 | return ret; | |
997 | ||
998 | /* Preallocate the olr before touching the ring */ | |
48e29f55 | 999 | ret = logical_ring_alloc_seqno(ring, ringbuf->FIXME_lrc_ctx); |
82e104cc OM |
1000 | if (ret) |
1001 | return ret; | |
1002 | ||
1003 | ringbuf->space -= num_dwords * sizeof(uint32_t); | |
1004 | return 0; | |
1005 | } | |
1006 | ||
771b9a53 MT |
1007 | static int intel_logical_ring_workarounds_emit(struct intel_engine_cs *ring, |
1008 | struct intel_context *ctx) | |
1009 | { | |
1010 | int ret, i; | |
1011 | struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf; | |
1012 | struct drm_device *dev = ring->dev; | |
1013 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1014 | struct i915_workarounds *w = &dev_priv->workarounds; | |
1015 | ||
1016 | if (WARN_ON(w->count == 0)) | |
1017 | return 0; | |
1018 | ||
1019 | ring->gpu_caches_dirty = true; | |
1020 | ret = logical_ring_flush_all_caches(ringbuf); | |
1021 | if (ret) | |
1022 | return ret; | |
1023 | ||
1024 | ret = intel_logical_ring_begin(ringbuf, w->count * 2 + 2); | |
1025 | if (ret) | |
1026 | return ret; | |
1027 | ||
1028 | intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count)); | |
1029 | for (i = 0; i < w->count; i++) { | |
1030 | intel_logical_ring_emit(ringbuf, w->reg[i].addr); | |
1031 | intel_logical_ring_emit(ringbuf, w->reg[i].value); | |
1032 | } | |
1033 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
1034 | ||
1035 | intel_logical_ring_advance(ringbuf); | |
1036 | ||
1037 | ring->gpu_caches_dirty = true; | |
1038 | ret = logical_ring_flush_all_caches(ringbuf); | |
1039 | if (ret) | |
1040 | return ret; | |
1041 | ||
1042 | return 0; | |
1043 | } | |
1044 | ||
9b1136d5 OM |
1045 | static int gen8_init_common_ring(struct intel_engine_cs *ring) |
1046 | { | |
1047 | struct drm_device *dev = ring->dev; | |
1048 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1049 | ||
73d477f6 OM |
1050 | I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask)); |
1051 | I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff); | |
1052 | ||
9b1136d5 OM |
1053 | I915_WRITE(RING_MODE_GEN7(ring), |
1054 | _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) | | |
1055 | _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)); | |
1056 | POSTING_READ(RING_MODE_GEN7(ring)); | |
1057 | DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring->name); | |
1058 | ||
1059 | memset(&ring->hangcheck, 0, sizeof(ring->hangcheck)); | |
1060 | ||
1061 | return 0; | |
1062 | } | |
1063 | ||
1064 | static int gen8_init_render_ring(struct intel_engine_cs *ring) | |
1065 | { | |
1066 | struct drm_device *dev = ring->dev; | |
1067 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1068 | int ret; | |
1069 | ||
1070 | ret = gen8_init_common_ring(ring); | |
1071 | if (ret) | |
1072 | return ret; | |
1073 | ||
1074 | /* We need to disable the AsyncFlip performance optimisations in order | |
1075 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
1076 | * programmed to '1' on all products. | |
1077 | * | |
1078 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv | |
1079 | */ | |
1080 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); | |
1081 | ||
1082 | ret = intel_init_pipe_control(ring); | |
1083 | if (ret) | |
1084 | return ret; | |
1085 | ||
1086 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); | |
1087 | ||
771b9a53 | 1088 | return init_workarounds_ring(ring); |
9b1136d5 OM |
1089 | } |
1090 | ||
15648585 OM |
1091 | static int gen8_emit_bb_start(struct intel_ringbuffer *ringbuf, |
1092 | u64 offset, unsigned flags) | |
1093 | { | |
15648585 OM |
1094 | bool ppgtt = !(flags & I915_DISPATCH_SECURE); |
1095 | int ret; | |
1096 | ||
1097 | ret = intel_logical_ring_begin(ringbuf, 4); | |
1098 | if (ret) | |
1099 | return ret; | |
1100 | ||
1101 | /* FIXME(BDW): Address space and security selectors. */ | |
1102 | intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8)); | |
1103 | intel_logical_ring_emit(ringbuf, lower_32_bits(offset)); | |
1104 | intel_logical_ring_emit(ringbuf, upper_32_bits(offset)); | |
1105 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
1106 | intel_logical_ring_advance(ringbuf); | |
1107 | ||
1108 | return 0; | |
1109 | } | |
1110 | ||
73d477f6 OM |
1111 | static bool gen8_logical_ring_get_irq(struct intel_engine_cs *ring) |
1112 | { | |
1113 | struct drm_device *dev = ring->dev; | |
1114 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1115 | unsigned long flags; | |
1116 | ||
7cd512f1 | 1117 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
73d477f6 OM |
1118 | return false; |
1119 | ||
1120 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1121 | if (ring->irq_refcount++ == 0) { | |
1122 | I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask)); | |
1123 | POSTING_READ(RING_IMR(ring->mmio_base)); | |
1124 | } | |
1125 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1126 | ||
1127 | return true; | |
1128 | } | |
1129 | ||
1130 | static void gen8_logical_ring_put_irq(struct intel_engine_cs *ring) | |
1131 | { | |
1132 | struct drm_device *dev = ring->dev; | |
1133 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1134 | unsigned long flags; | |
1135 | ||
1136 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1137 | if (--ring->irq_refcount == 0) { | |
1138 | I915_WRITE_IMR(ring, ~ring->irq_keep_mask); | |
1139 | POSTING_READ(RING_IMR(ring->mmio_base)); | |
1140 | } | |
1141 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1142 | } | |
1143 | ||
4712274c OM |
1144 | static int gen8_emit_flush(struct intel_ringbuffer *ringbuf, |
1145 | u32 invalidate_domains, | |
1146 | u32 unused) | |
1147 | { | |
1148 | struct intel_engine_cs *ring = ringbuf->ring; | |
1149 | struct drm_device *dev = ring->dev; | |
1150 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1151 | uint32_t cmd; | |
1152 | int ret; | |
1153 | ||
1154 | ret = intel_logical_ring_begin(ringbuf, 4); | |
1155 | if (ret) | |
1156 | return ret; | |
1157 | ||
1158 | cmd = MI_FLUSH_DW + 1; | |
1159 | ||
1160 | if (ring == &dev_priv->ring[VCS]) { | |
1161 | if (invalidate_domains & I915_GEM_GPU_DOMAINS) | |
1162 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD | | |
1163 | MI_FLUSH_DW_STORE_INDEX | | |
1164 | MI_FLUSH_DW_OP_STOREDW; | |
1165 | } else { | |
1166 | if (invalidate_domains & I915_GEM_DOMAIN_RENDER) | |
1167 | cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX | | |
1168 | MI_FLUSH_DW_OP_STOREDW; | |
1169 | } | |
1170 | ||
1171 | intel_logical_ring_emit(ringbuf, cmd); | |
1172 | intel_logical_ring_emit(ringbuf, | |
1173 | I915_GEM_HWS_SCRATCH_ADDR | | |
1174 | MI_FLUSH_DW_USE_GTT); | |
1175 | intel_logical_ring_emit(ringbuf, 0); /* upper addr */ | |
1176 | intel_logical_ring_emit(ringbuf, 0); /* value */ | |
1177 | intel_logical_ring_advance(ringbuf); | |
1178 | ||
1179 | return 0; | |
1180 | } | |
1181 | ||
1182 | static int gen8_emit_flush_render(struct intel_ringbuffer *ringbuf, | |
1183 | u32 invalidate_domains, | |
1184 | u32 flush_domains) | |
1185 | { | |
1186 | struct intel_engine_cs *ring = ringbuf->ring; | |
1187 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; | |
1188 | u32 flags = 0; | |
1189 | int ret; | |
1190 | ||
1191 | flags |= PIPE_CONTROL_CS_STALL; | |
1192 | ||
1193 | if (flush_domains) { | |
1194 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
1195 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
1196 | } | |
1197 | ||
1198 | if (invalidate_domains) { | |
1199 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
1200 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
1201 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
1202 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
1203 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
1204 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
1205 | flags |= PIPE_CONTROL_QW_WRITE; | |
1206 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
1207 | } | |
1208 | ||
1209 | ret = intel_logical_ring_begin(ringbuf, 6); | |
1210 | if (ret) | |
1211 | return ret; | |
1212 | ||
1213 | intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6)); | |
1214 | intel_logical_ring_emit(ringbuf, flags); | |
1215 | intel_logical_ring_emit(ringbuf, scratch_addr); | |
1216 | intel_logical_ring_emit(ringbuf, 0); | |
1217 | intel_logical_ring_emit(ringbuf, 0); | |
1218 | intel_logical_ring_emit(ringbuf, 0); | |
1219 | intel_logical_ring_advance(ringbuf); | |
1220 | ||
1221 | return 0; | |
1222 | } | |
1223 | ||
e94e37ad OM |
1224 | static u32 gen8_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
1225 | { | |
1226 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); | |
1227 | } | |
1228 | ||
1229 | static void gen8_set_seqno(struct intel_engine_cs *ring, u32 seqno) | |
1230 | { | |
1231 | intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno); | |
1232 | } | |
1233 | ||
4da46e1e OM |
1234 | static int gen8_emit_request(struct intel_ringbuffer *ringbuf) |
1235 | { | |
1236 | struct intel_engine_cs *ring = ringbuf->ring; | |
1237 | u32 cmd; | |
1238 | int ret; | |
1239 | ||
1240 | ret = intel_logical_ring_begin(ringbuf, 6); | |
1241 | if (ret) | |
1242 | return ret; | |
1243 | ||
1244 | cmd = MI_STORE_DWORD_IMM_GEN8; | |
1245 | cmd |= MI_GLOBAL_GTT; | |
1246 | ||
1247 | intel_logical_ring_emit(ringbuf, cmd); | |
1248 | intel_logical_ring_emit(ringbuf, | |
1249 | (ring->status_page.gfx_addr + | |
1250 | (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT))); | |
1251 | intel_logical_ring_emit(ringbuf, 0); | |
1252 | intel_logical_ring_emit(ringbuf, ring->outstanding_lazy_seqno); | |
1253 | intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT); | |
1254 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
1255 | intel_logical_ring_advance_and_submit(ringbuf); | |
1256 | ||
1257 | return 0; | |
1258 | } | |
1259 | ||
73e4d07f OM |
1260 | /** |
1261 | * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer | |
1262 | * | |
1263 | * @ring: Engine Command Streamer. | |
1264 | * | |
1265 | */ | |
454afebd OM |
1266 | void intel_logical_ring_cleanup(struct intel_engine_cs *ring) |
1267 | { | |
6402c330 | 1268 | struct drm_i915_private *dev_priv; |
9832b9da | 1269 | |
48d82387 OM |
1270 | if (!intel_ring_initialized(ring)) |
1271 | return; | |
1272 | ||
6402c330 JH |
1273 | dev_priv = ring->dev->dev_private; |
1274 | ||
9832b9da OM |
1275 | intel_logical_ring_stop(ring); |
1276 | WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0); | |
48d82387 OM |
1277 | ring->preallocated_lazy_request = NULL; |
1278 | ring->outstanding_lazy_seqno = 0; | |
1279 | ||
1280 | if (ring->cleanup) | |
1281 | ring->cleanup(ring); | |
1282 | ||
1283 | i915_cmd_parser_fini_ring(ring); | |
1284 | ||
1285 | if (ring->status_page.obj) { | |
1286 | kunmap(sg_page(ring->status_page.obj->pages->sgl)); | |
1287 | ring->status_page.obj = NULL; | |
1288 | } | |
454afebd OM |
1289 | } |
1290 | ||
1291 | static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *ring) | |
1292 | { | |
48d82387 | 1293 | int ret; |
48d82387 OM |
1294 | |
1295 | /* Intentionally left blank. */ | |
1296 | ring->buffer = NULL; | |
1297 | ||
1298 | ring->dev = dev; | |
1299 | INIT_LIST_HEAD(&ring->active_list); | |
1300 | INIT_LIST_HEAD(&ring->request_list); | |
1301 | init_waitqueue_head(&ring->irq_queue); | |
1302 | ||
acdd884a MT |
1303 | INIT_LIST_HEAD(&ring->execlist_queue); |
1304 | spin_lock_init(&ring->execlist_lock); | |
e981e7b1 | 1305 | ring->next_context_status_buffer = 0; |
acdd884a | 1306 | |
48d82387 OM |
1307 | ret = i915_cmd_parser_init_ring(ring); |
1308 | if (ret) | |
1309 | return ret; | |
1310 | ||
1311 | if (ring->init) { | |
1312 | ret = ring->init(ring); | |
1313 | if (ret) | |
1314 | return ret; | |
1315 | } | |
1316 | ||
564ddb2f OM |
1317 | ret = intel_lr_context_deferred_create(ring->default_context, ring); |
1318 | ||
1319 | return ret; | |
454afebd OM |
1320 | } |
1321 | ||
1322 | static int logical_render_ring_init(struct drm_device *dev) | |
1323 | { | |
1324 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1325 | struct intel_engine_cs *ring = &dev_priv->ring[RCS]; | |
1326 | ||
1327 | ring->name = "render ring"; | |
1328 | ring->id = RCS; | |
1329 | ring->mmio_base = RENDER_RING_BASE; | |
1330 | ring->irq_enable_mask = | |
1331 | GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT; | |
73d477f6 OM |
1332 | ring->irq_keep_mask = |
1333 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT; | |
1334 | if (HAS_L3_DPF(dev)) | |
1335 | ring->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT; | |
454afebd | 1336 | |
9b1136d5 | 1337 | ring->init = gen8_init_render_ring; |
771b9a53 | 1338 | ring->init_context = intel_logical_ring_workarounds_emit; |
9b1136d5 | 1339 | ring->cleanup = intel_fini_pipe_control; |
e94e37ad OM |
1340 | ring->get_seqno = gen8_get_seqno; |
1341 | ring->set_seqno = gen8_set_seqno; | |
4da46e1e | 1342 | ring->emit_request = gen8_emit_request; |
4712274c | 1343 | ring->emit_flush = gen8_emit_flush_render; |
73d477f6 OM |
1344 | ring->irq_get = gen8_logical_ring_get_irq; |
1345 | ring->irq_put = gen8_logical_ring_put_irq; | |
15648585 | 1346 | ring->emit_bb_start = gen8_emit_bb_start; |
9b1136d5 | 1347 | |
454afebd OM |
1348 | return logical_ring_init(dev, ring); |
1349 | } | |
1350 | ||
1351 | static int logical_bsd_ring_init(struct drm_device *dev) | |
1352 | { | |
1353 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1354 | struct intel_engine_cs *ring = &dev_priv->ring[VCS]; | |
1355 | ||
1356 | ring->name = "bsd ring"; | |
1357 | ring->id = VCS; | |
1358 | ring->mmio_base = GEN6_BSD_RING_BASE; | |
1359 | ring->irq_enable_mask = | |
1360 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; | |
73d477f6 OM |
1361 | ring->irq_keep_mask = |
1362 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; | |
454afebd | 1363 | |
9b1136d5 | 1364 | ring->init = gen8_init_common_ring; |
e94e37ad OM |
1365 | ring->get_seqno = gen8_get_seqno; |
1366 | ring->set_seqno = gen8_set_seqno; | |
4da46e1e | 1367 | ring->emit_request = gen8_emit_request; |
4712274c | 1368 | ring->emit_flush = gen8_emit_flush; |
73d477f6 OM |
1369 | ring->irq_get = gen8_logical_ring_get_irq; |
1370 | ring->irq_put = gen8_logical_ring_put_irq; | |
15648585 | 1371 | ring->emit_bb_start = gen8_emit_bb_start; |
9b1136d5 | 1372 | |
454afebd OM |
1373 | return logical_ring_init(dev, ring); |
1374 | } | |
1375 | ||
1376 | static int logical_bsd2_ring_init(struct drm_device *dev) | |
1377 | { | |
1378 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1379 | struct intel_engine_cs *ring = &dev_priv->ring[VCS2]; | |
1380 | ||
1381 | ring->name = "bds2 ring"; | |
1382 | ring->id = VCS2; | |
1383 | ring->mmio_base = GEN8_BSD2_RING_BASE; | |
1384 | ring->irq_enable_mask = | |
1385 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; | |
73d477f6 OM |
1386 | ring->irq_keep_mask = |
1387 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; | |
454afebd | 1388 | |
9b1136d5 | 1389 | ring->init = gen8_init_common_ring; |
e94e37ad OM |
1390 | ring->get_seqno = gen8_get_seqno; |
1391 | ring->set_seqno = gen8_set_seqno; | |
4da46e1e | 1392 | ring->emit_request = gen8_emit_request; |
4712274c | 1393 | ring->emit_flush = gen8_emit_flush; |
73d477f6 OM |
1394 | ring->irq_get = gen8_logical_ring_get_irq; |
1395 | ring->irq_put = gen8_logical_ring_put_irq; | |
15648585 | 1396 | ring->emit_bb_start = gen8_emit_bb_start; |
9b1136d5 | 1397 | |
454afebd OM |
1398 | return logical_ring_init(dev, ring); |
1399 | } | |
1400 | ||
1401 | static int logical_blt_ring_init(struct drm_device *dev) | |
1402 | { | |
1403 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1404 | struct intel_engine_cs *ring = &dev_priv->ring[BCS]; | |
1405 | ||
1406 | ring->name = "blitter ring"; | |
1407 | ring->id = BCS; | |
1408 | ring->mmio_base = BLT_RING_BASE; | |
1409 | ring->irq_enable_mask = | |
1410 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; | |
73d477f6 OM |
1411 | ring->irq_keep_mask = |
1412 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT; | |
454afebd | 1413 | |
9b1136d5 | 1414 | ring->init = gen8_init_common_ring; |
e94e37ad OM |
1415 | ring->get_seqno = gen8_get_seqno; |
1416 | ring->set_seqno = gen8_set_seqno; | |
4da46e1e | 1417 | ring->emit_request = gen8_emit_request; |
4712274c | 1418 | ring->emit_flush = gen8_emit_flush; |
73d477f6 OM |
1419 | ring->irq_get = gen8_logical_ring_get_irq; |
1420 | ring->irq_put = gen8_logical_ring_put_irq; | |
15648585 | 1421 | ring->emit_bb_start = gen8_emit_bb_start; |
9b1136d5 | 1422 | |
454afebd OM |
1423 | return logical_ring_init(dev, ring); |
1424 | } | |
1425 | ||
1426 | static int logical_vebox_ring_init(struct drm_device *dev) | |
1427 | { | |
1428 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1429 | struct intel_engine_cs *ring = &dev_priv->ring[VECS]; | |
1430 | ||
1431 | ring->name = "video enhancement ring"; | |
1432 | ring->id = VECS; | |
1433 | ring->mmio_base = VEBOX_RING_BASE; | |
1434 | ring->irq_enable_mask = | |
1435 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; | |
73d477f6 OM |
1436 | ring->irq_keep_mask = |
1437 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT; | |
454afebd | 1438 | |
9b1136d5 | 1439 | ring->init = gen8_init_common_ring; |
e94e37ad OM |
1440 | ring->get_seqno = gen8_get_seqno; |
1441 | ring->set_seqno = gen8_set_seqno; | |
4da46e1e | 1442 | ring->emit_request = gen8_emit_request; |
4712274c | 1443 | ring->emit_flush = gen8_emit_flush; |
73d477f6 OM |
1444 | ring->irq_get = gen8_logical_ring_get_irq; |
1445 | ring->irq_put = gen8_logical_ring_put_irq; | |
15648585 | 1446 | ring->emit_bb_start = gen8_emit_bb_start; |
9b1136d5 | 1447 | |
454afebd OM |
1448 | return logical_ring_init(dev, ring); |
1449 | } | |
1450 | ||
73e4d07f OM |
1451 | /** |
1452 | * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers | |
1453 | * @dev: DRM device. | |
1454 | * | |
1455 | * This function inits the engines for an Execlists submission style (the equivalent in the | |
1456 | * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for | |
1457 | * those engines that are present in the hardware. | |
1458 | * | |
1459 | * Return: non-zero if the initialization failed. | |
1460 | */ | |
454afebd OM |
1461 | int intel_logical_rings_init(struct drm_device *dev) |
1462 | { | |
1463 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1464 | int ret; | |
1465 | ||
1466 | ret = logical_render_ring_init(dev); | |
1467 | if (ret) | |
1468 | return ret; | |
1469 | ||
1470 | if (HAS_BSD(dev)) { | |
1471 | ret = logical_bsd_ring_init(dev); | |
1472 | if (ret) | |
1473 | goto cleanup_render_ring; | |
1474 | } | |
1475 | ||
1476 | if (HAS_BLT(dev)) { | |
1477 | ret = logical_blt_ring_init(dev); | |
1478 | if (ret) | |
1479 | goto cleanup_bsd_ring; | |
1480 | } | |
1481 | ||
1482 | if (HAS_VEBOX(dev)) { | |
1483 | ret = logical_vebox_ring_init(dev); | |
1484 | if (ret) | |
1485 | goto cleanup_blt_ring; | |
1486 | } | |
1487 | ||
1488 | if (HAS_BSD2(dev)) { | |
1489 | ret = logical_bsd2_ring_init(dev); | |
1490 | if (ret) | |
1491 | goto cleanup_vebox_ring; | |
1492 | } | |
1493 | ||
1494 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); | |
1495 | if (ret) | |
1496 | goto cleanup_bsd2_ring; | |
1497 | ||
1498 | return 0; | |
1499 | ||
1500 | cleanup_bsd2_ring: | |
1501 | intel_logical_ring_cleanup(&dev_priv->ring[VCS2]); | |
1502 | cleanup_vebox_ring: | |
1503 | intel_logical_ring_cleanup(&dev_priv->ring[VECS]); | |
1504 | cleanup_blt_ring: | |
1505 | intel_logical_ring_cleanup(&dev_priv->ring[BCS]); | |
1506 | cleanup_bsd_ring: | |
1507 | intel_logical_ring_cleanup(&dev_priv->ring[VCS]); | |
1508 | cleanup_render_ring: | |
1509 | intel_logical_ring_cleanup(&dev_priv->ring[RCS]); | |
1510 | ||
1511 | return ret; | |
1512 | } | |
1513 | ||
564ddb2f OM |
1514 | int intel_lr_context_render_state_init(struct intel_engine_cs *ring, |
1515 | struct intel_context *ctx) | |
1516 | { | |
1517 | struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf; | |
1518 | struct render_state so; | |
1519 | struct drm_i915_file_private *file_priv = ctx->file_priv; | |
1520 | struct drm_file *file = file_priv ? file_priv->file : NULL; | |
1521 | int ret; | |
1522 | ||
1523 | ret = i915_gem_render_state_prepare(ring, &so); | |
1524 | if (ret) | |
1525 | return ret; | |
1526 | ||
1527 | if (so.rodata == NULL) | |
1528 | return 0; | |
1529 | ||
1530 | ret = ring->emit_bb_start(ringbuf, | |
1531 | so.ggtt_offset, | |
1532 | I915_DISPATCH_SECURE); | |
1533 | if (ret) | |
1534 | goto out; | |
1535 | ||
1536 | i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), ring); | |
1537 | ||
1538 | ret = __i915_add_request(ring, file, so.obj, NULL); | |
1539 | /* intel_logical_ring_add_request moves object to inactive if it | |
1540 | * fails */ | |
1541 | out: | |
1542 | i915_gem_render_state_fini(&so); | |
1543 | return ret; | |
1544 | } | |
1545 | ||
8670d6f9 OM |
1546 | static int |
1547 | populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj, | |
1548 | struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf) | |
1549 | { | |
2d965536 TD |
1550 | struct drm_device *dev = ring->dev; |
1551 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8670d6f9 | 1552 | struct drm_i915_gem_object *ring_obj = ringbuf->obj; |
ae6c4806 | 1553 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
8670d6f9 OM |
1554 | struct page *page; |
1555 | uint32_t *reg_state; | |
1556 | int ret; | |
1557 | ||
2d965536 TD |
1558 | if (!ppgtt) |
1559 | ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1560 | ||
8670d6f9 OM |
1561 | ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true); |
1562 | if (ret) { | |
1563 | DRM_DEBUG_DRIVER("Could not set to CPU domain\n"); | |
1564 | return ret; | |
1565 | } | |
1566 | ||
1567 | ret = i915_gem_object_get_pages(ctx_obj); | |
1568 | if (ret) { | |
1569 | DRM_DEBUG_DRIVER("Could not get object pages\n"); | |
1570 | return ret; | |
1571 | } | |
1572 | ||
1573 | i915_gem_object_pin_pages(ctx_obj); | |
1574 | ||
1575 | /* The second page of the context object contains some fields which must | |
1576 | * be set up prior to the first execution. */ | |
1577 | page = i915_gem_object_get_page(ctx_obj, 1); | |
1578 | reg_state = kmap_atomic(page); | |
1579 | ||
1580 | /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM | |
1581 | * commands followed by (reg, value) pairs. The values we are setting here are | |
1582 | * only for the first context restore: on a subsequent save, the GPU will | |
1583 | * recreate this batchbuffer with new values (including all the missing | |
1584 | * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */ | |
1585 | if (ring->id == RCS) | |
1586 | reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(14); | |
1587 | else | |
1588 | reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(11); | |
1589 | reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED; | |
1590 | reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring); | |
1591 | reg_state[CTX_CONTEXT_CONTROL+1] = | |
1592 | _MASKED_BIT_ENABLE((1<<3) | MI_RESTORE_INHIBIT); | |
1593 | reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base); | |
1594 | reg_state[CTX_RING_HEAD+1] = 0; | |
1595 | reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base); | |
1596 | reg_state[CTX_RING_TAIL+1] = 0; | |
1597 | reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base); | |
1598 | reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(ring_obj); | |
1599 | reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base); | |
1600 | reg_state[CTX_RING_BUFFER_CONTROL+1] = | |
1601 | ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID; | |
1602 | reg_state[CTX_BB_HEAD_U] = ring->mmio_base + 0x168; | |
1603 | reg_state[CTX_BB_HEAD_U+1] = 0; | |
1604 | reg_state[CTX_BB_HEAD_L] = ring->mmio_base + 0x140; | |
1605 | reg_state[CTX_BB_HEAD_L+1] = 0; | |
1606 | reg_state[CTX_BB_STATE] = ring->mmio_base + 0x110; | |
1607 | reg_state[CTX_BB_STATE+1] = (1<<5); | |
1608 | reg_state[CTX_SECOND_BB_HEAD_U] = ring->mmio_base + 0x11c; | |
1609 | reg_state[CTX_SECOND_BB_HEAD_U+1] = 0; | |
1610 | reg_state[CTX_SECOND_BB_HEAD_L] = ring->mmio_base + 0x114; | |
1611 | reg_state[CTX_SECOND_BB_HEAD_L+1] = 0; | |
1612 | reg_state[CTX_SECOND_BB_STATE] = ring->mmio_base + 0x118; | |
1613 | reg_state[CTX_SECOND_BB_STATE+1] = 0; | |
1614 | if (ring->id == RCS) { | |
1615 | /* TODO: according to BSpec, the register state context | |
1616 | * for CHV does not have these. OTOH, these registers do | |
1617 | * exist in CHV. I'm waiting for a clarification */ | |
1618 | reg_state[CTX_BB_PER_CTX_PTR] = ring->mmio_base + 0x1c0; | |
1619 | reg_state[CTX_BB_PER_CTX_PTR+1] = 0; | |
1620 | reg_state[CTX_RCS_INDIRECT_CTX] = ring->mmio_base + 0x1c4; | |
1621 | reg_state[CTX_RCS_INDIRECT_CTX+1] = 0; | |
1622 | reg_state[CTX_RCS_INDIRECT_CTX_OFFSET] = ring->mmio_base + 0x1c8; | |
1623 | reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = 0; | |
1624 | } | |
1625 | reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9); | |
1626 | reg_state[CTX_LRI_HEADER_1] |= MI_LRI_FORCE_POSTED; | |
1627 | reg_state[CTX_CTX_TIMESTAMP] = ring->mmio_base + 0x3a8; | |
1628 | reg_state[CTX_CTX_TIMESTAMP+1] = 0; | |
1629 | reg_state[CTX_PDP3_UDW] = GEN8_RING_PDP_UDW(ring, 3); | |
1630 | reg_state[CTX_PDP3_LDW] = GEN8_RING_PDP_LDW(ring, 3); | |
1631 | reg_state[CTX_PDP2_UDW] = GEN8_RING_PDP_UDW(ring, 2); | |
1632 | reg_state[CTX_PDP2_LDW] = GEN8_RING_PDP_LDW(ring, 2); | |
1633 | reg_state[CTX_PDP1_UDW] = GEN8_RING_PDP_UDW(ring, 1); | |
1634 | reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1); | |
1635 | reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0); | |
1636 | reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0); | |
1637 | reg_state[CTX_PDP3_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[3]); | |
1638 | reg_state[CTX_PDP3_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[3]); | |
1639 | reg_state[CTX_PDP2_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[2]); | |
1640 | reg_state[CTX_PDP2_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[2]); | |
1641 | reg_state[CTX_PDP1_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[1]); | |
1642 | reg_state[CTX_PDP1_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[1]); | |
1643 | reg_state[CTX_PDP0_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[0]); | |
1644 | reg_state[CTX_PDP0_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[0]); | |
1645 | if (ring->id == RCS) { | |
1646 | reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1); | |
1647 | reg_state[CTX_R_PWR_CLK_STATE] = 0x20c8; | |
1648 | reg_state[CTX_R_PWR_CLK_STATE+1] = 0; | |
1649 | } | |
1650 | ||
1651 | kunmap_atomic(reg_state); | |
1652 | ||
1653 | ctx_obj->dirty = 1; | |
1654 | set_page_dirty(page); | |
1655 | i915_gem_object_unpin_pages(ctx_obj); | |
1656 | ||
1657 | return 0; | |
1658 | } | |
1659 | ||
73e4d07f OM |
1660 | /** |
1661 | * intel_lr_context_free() - free the LRC specific bits of a context | |
1662 | * @ctx: the LR context to free. | |
1663 | * | |
1664 | * The real context freeing is done in i915_gem_context_free: this only | |
1665 | * takes care of the bits that are LRC related: the per-engine backing | |
1666 | * objects and the logical ringbuffer. | |
1667 | */ | |
ede7d42b OM |
1668 | void intel_lr_context_free(struct intel_context *ctx) |
1669 | { | |
8c857917 OM |
1670 | int i; |
1671 | ||
1672 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
1673 | struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state; | |
84c2377f OM |
1674 | struct intel_ringbuffer *ringbuf = ctx->engine[i].ringbuf; |
1675 | ||
8c857917 | 1676 | if (ctx_obj) { |
84c2377f OM |
1677 | intel_destroy_ringbuffer_obj(ringbuf); |
1678 | kfree(ringbuf); | |
8c857917 OM |
1679 | i915_gem_object_ggtt_unpin(ctx_obj); |
1680 | drm_gem_object_unreference(&ctx_obj->base); | |
1681 | } | |
1682 | } | |
1683 | } | |
1684 | ||
1685 | static uint32_t get_lr_context_size(struct intel_engine_cs *ring) | |
1686 | { | |
1687 | int ret = 0; | |
1688 | ||
468c6816 | 1689 | WARN_ON(INTEL_INFO(ring->dev)->gen < 8); |
8c857917 OM |
1690 | |
1691 | switch (ring->id) { | |
1692 | case RCS: | |
468c6816 MN |
1693 | if (INTEL_INFO(ring->dev)->gen >= 9) |
1694 | ret = GEN9_LR_CONTEXT_RENDER_SIZE; | |
1695 | else | |
1696 | ret = GEN8_LR_CONTEXT_RENDER_SIZE; | |
8c857917 OM |
1697 | break; |
1698 | case VCS: | |
1699 | case BCS: | |
1700 | case VECS: | |
1701 | case VCS2: | |
1702 | ret = GEN8_LR_CONTEXT_OTHER_SIZE; | |
1703 | break; | |
1704 | } | |
1705 | ||
1706 | return ret; | |
ede7d42b OM |
1707 | } |
1708 | ||
1df06b75 TD |
1709 | static int lrc_setup_hardware_status_page(struct intel_engine_cs *ring, |
1710 | struct drm_i915_gem_object *default_ctx_obj) | |
1711 | { | |
1712 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
1713 | ||
1714 | /* The status page is offset 0 from the default context object | |
1715 | * in LRC mode. */ | |
1716 | ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(default_ctx_obj); | |
1717 | ring->status_page.page_addr = | |
1718 | kmap(sg_page(default_ctx_obj->pages->sgl)); | |
1719 | if (ring->status_page.page_addr == NULL) | |
1720 | return -ENOMEM; | |
1721 | ring->status_page.obj = default_ctx_obj; | |
1722 | ||
1723 | I915_WRITE(RING_HWS_PGA(ring->mmio_base), | |
1724 | (u32)ring->status_page.gfx_addr); | |
1725 | POSTING_READ(RING_HWS_PGA(ring->mmio_base)); | |
1726 | ||
1727 | return 0; | |
1728 | } | |
1729 | ||
73e4d07f OM |
1730 | /** |
1731 | * intel_lr_context_deferred_create() - create the LRC specific bits of a context | |
1732 | * @ctx: LR context to create. | |
1733 | * @ring: engine to be used with the context. | |
1734 | * | |
1735 | * This function can be called more than once, with different engines, if we plan | |
1736 | * to use the context with them. The context backing objects and the ringbuffers | |
1737 | * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why | |
1738 | * the creation is a deferred call: it's better to make sure first that we need to use | |
1739 | * a given ring with the context. | |
1740 | * | |
32197aab | 1741 | * Return: non-zero on error. |
73e4d07f | 1742 | */ |
ede7d42b OM |
1743 | int intel_lr_context_deferred_create(struct intel_context *ctx, |
1744 | struct intel_engine_cs *ring) | |
1745 | { | |
8c857917 OM |
1746 | struct drm_device *dev = ring->dev; |
1747 | struct drm_i915_gem_object *ctx_obj; | |
1748 | uint32_t context_size; | |
84c2377f | 1749 | struct intel_ringbuffer *ringbuf; |
8c857917 OM |
1750 | int ret; |
1751 | ||
ede7d42b | 1752 | WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL); |
48d82387 OM |
1753 | if (ctx->engine[ring->id].state) |
1754 | return 0; | |
ede7d42b | 1755 | |
8c857917 OM |
1756 | context_size = round_up(get_lr_context_size(ring), 4096); |
1757 | ||
1758 | ctx_obj = i915_gem_alloc_context_obj(dev, context_size); | |
1759 | if (IS_ERR(ctx_obj)) { | |
1760 | ret = PTR_ERR(ctx_obj); | |
1761 | DRM_DEBUG_DRIVER("Alloc LRC backing obj failed: %d\n", ret); | |
1762 | return ret; | |
1763 | } | |
1764 | ||
1765 | ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN, 0); | |
1766 | if (ret) { | |
1767 | DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n", ret); | |
1768 | drm_gem_object_unreference(&ctx_obj->base); | |
1769 | return ret; | |
1770 | } | |
1771 | ||
84c2377f OM |
1772 | ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL); |
1773 | if (!ringbuf) { | |
1774 | DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n", | |
1775 | ring->name); | |
1776 | i915_gem_object_ggtt_unpin(ctx_obj); | |
1777 | drm_gem_object_unreference(&ctx_obj->base); | |
1778 | ret = -ENOMEM; | |
1779 | return ret; | |
1780 | } | |
1781 | ||
0c7dd53b | 1782 | ringbuf->ring = ring; |
582d67f0 OM |
1783 | ringbuf->FIXME_lrc_ctx = ctx; |
1784 | ||
84c2377f OM |
1785 | ringbuf->size = 32 * PAGE_SIZE; |
1786 | ringbuf->effective_size = ringbuf->size; | |
1787 | ringbuf->head = 0; | |
1788 | ringbuf->tail = 0; | |
1789 | ringbuf->space = ringbuf->size; | |
1790 | ringbuf->last_retired_head = -1; | |
1791 | ||
1792 | /* TODO: For now we put this in the mappable region so that we can reuse | |
1793 | * the existing ringbuffer code which ioremaps it. When we start | |
1794 | * creating many contexts, this will no longer work and we must switch | |
1795 | * to a kmapish interface. | |
1796 | */ | |
1797 | ret = intel_alloc_ringbuffer_obj(dev, ringbuf); | |
1798 | if (ret) { | |
1799 | DRM_DEBUG_DRIVER("Failed to allocate ringbuffer obj %s: %d\n", | |
1800 | ring->name, ret); | |
8670d6f9 OM |
1801 | goto error; |
1802 | } | |
1803 | ||
1804 | ret = populate_lr_context(ctx, ctx_obj, ring, ringbuf); | |
1805 | if (ret) { | |
1806 | DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret); | |
1807 | intel_destroy_ringbuffer_obj(ringbuf); | |
1808 | goto error; | |
84c2377f OM |
1809 | } |
1810 | ||
1811 | ctx->engine[ring->id].ringbuf = ringbuf; | |
8c857917 | 1812 | ctx->engine[ring->id].state = ctx_obj; |
ede7d42b | 1813 | |
564ddb2f | 1814 | if (ctx == ring->default_context) { |
1df06b75 TD |
1815 | ret = lrc_setup_hardware_status_page(ring, ctx_obj); |
1816 | if (ret) { | |
1817 | DRM_ERROR("Failed to setup hardware status page\n"); | |
1818 | goto error; | |
1819 | } | |
564ddb2f OM |
1820 | } |
1821 | ||
1822 | if (ring->id == RCS && !ctx->rcs_initialized) { | |
771b9a53 MT |
1823 | if (ring->init_context) { |
1824 | ret = ring->init_context(ring, ctx); | |
1825 | if (ret) | |
1826 | DRM_ERROR("ring init context: %d\n", ret); | |
1827 | } | |
1828 | ||
564ddb2f OM |
1829 | ret = intel_lr_context_render_state_init(ring, ctx); |
1830 | if (ret) { | |
1831 | DRM_ERROR("Init render state failed: %d\n", ret); | |
1832 | ctx->engine[ring->id].ringbuf = NULL; | |
1833 | ctx->engine[ring->id].state = NULL; | |
1834 | intel_destroy_ringbuffer_obj(ringbuf); | |
1835 | goto error; | |
1836 | } | |
1837 | ctx->rcs_initialized = true; | |
1838 | } | |
1839 | ||
ede7d42b | 1840 | return 0; |
8670d6f9 OM |
1841 | |
1842 | error: | |
1843 | kfree(ringbuf); | |
1844 | i915_gem_object_ggtt_unpin(ctx_obj); | |
1845 | drm_gem_object_unreference(&ctx_obj->base); | |
1846 | return ret; | |
ede7d42b | 1847 | } |