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b20385f1 OM |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * Michel Thierry <michel.thierry@intel.com> | |
26 | * Thomas Daniel <thomas.daniel@intel.com> | |
27 | * Oscar Mateo <oscar.mateo@intel.com> | |
28 | * | |
29 | */ | |
30 | ||
73e4d07f OM |
31 | /** |
32 | * DOC: Logical Rings, Logical Ring Contexts and Execlists | |
33 | * | |
34 | * Motivation: | |
b20385f1 OM |
35 | * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts". |
36 | * These expanded contexts enable a number of new abilities, especially | |
37 | * "Execlists" (also implemented in this file). | |
38 | * | |
73e4d07f OM |
39 | * One of the main differences with the legacy HW contexts is that logical |
40 | * ring contexts incorporate many more things to the context's state, like | |
41 | * PDPs or ringbuffer control registers: | |
42 | * | |
43 | * The reason why PDPs are included in the context is straightforward: as | |
44 | * PPGTTs (per-process GTTs) are actually per-context, having the PDPs | |
45 | * contained there mean you don't need to do a ppgtt->switch_mm yourself, | |
46 | * instead, the GPU will do it for you on the context switch. | |
47 | * | |
48 | * But, what about the ringbuffer control registers (head, tail, etc..)? | |
49 | * shouldn't we just need a set of those per engine command streamer? This is | |
50 | * where the name "Logical Rings" starts to make sense: by virtualizing the | |
51 | * rings, the engine cs shifts to a new "ring buffer" with every context | |
52 | * switch. When you want to submit a workload to the GPU you: A) choose your | |
53 | * context, B) find its appropriate virtualized ring, C) write commands to it | |
54 | * and then, finally, D) tell the GPU to switch to that context. | |
55 | * | |
56 | * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch | |
57 | * to a contexts is via a context execution list, ergo "Execlists". | |
58 | * | |
59 | * LRC implementation: | |
60 | * Regarding the creation of contexts, we have: | |
61 | * | |
62 | * - One global default context. | |
63 | * - One local default context for each opened fd. | |
64 | * - One local extra context for each context create ioctl call. | |
65 | * | |
66 | * Now that ringbuffers belong per-context (and not per-engine, like before) | |
67 | * and that contexts are uniquely tied to a given engine (and not reusable, | |
68 | * like before) we need: | |
69 | * | |
70 | * - One ringbuffer per-engine inside each context. | |
71 | * - One backing object per-engine inside each context. | |
72 | * | |
73 | * The global default context starts its life with these new objects fully | |
74 | * allocated and populated. The local default context for each opened fd is | |
75 | * more complex, because we don't know at creation time which engine is going | |
76 | * to use them. To handle this, we have implemented a deferred creation of LR | |
77 | * contexts: | |
78 | * | |
79 | * The local context starts its life as a hollow or blank holder, that only | |
80 | * gets populated for a given engine once we receive an execbuffer. If later | |
81 | * on we receive another execbuffer ioctl for the same context but a different | |
82 | * engine, we allocate/populate a new ringbuffer and context backing object and | |
83 | * so on. | |
84 | * | |
85 | * Finally, regarding local contexts created using the ioctl call: as they are | |
86 | * only allowed with the render ring, we can allocate & populate them right | |
87 | * away (no need to defer anything, at least for now). | |
88 | * | |
89 | * Execlists implementation: | |
b20385f1 OM |
90 | * Execlists are the new method by which, on gen8+ hardware, workloads are |
91 | * submitted for execution (as opposed to the legacy, ringbuffer-based, method). | |
73e4d07f OM |
92 | * This method works as follows: |
93 | * | |
94 | * When a request is committed, its commands (the BB start and any leading or | |
95 | * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer | |
96 | * for the appropriate context. The tail pointer in the hardware context is not | |
97 | * updated at this time, but instead, kept by the driver in the ringbuffer | |
98 | * structure. A structure representing this request is added to a request queue | |
99 | * for the appropriate engine: this structure contains a copy of the context's | |
100 | * tail after the request was written to the ring buffer and a pointer to the | |
101 | * context itself. | |
102 | * | |
103 | * If the engine's request queue was empty before the request was added, the | |
104 | * queue is processed immediately. Otherwise the queue will be processed during | |
105 | * a context switch interrupt. In any case, elements on the queue will get sent | |
106 | * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a | |
107 | * globally unique 20-bits submission ID. | |
108 | * | |
109 | * When execution of a request completes, the GPU updates the context status | |
110 | * buffer with a context complete event and generates a context switch interrupt. | |
111 | * During the interrupt handling, the driver examines the events in the buffer: | |
112 | * for each context complete event, if the announced ID matches that on the head | |
113 | * of the request queue, then that request is retired and removed from the queue. | |
114 | * | |
115 | * After processing, if any requests were retired and the queue is not empty | |
116 | * then a new execution list can be submitted. The two requests at the front of | |
117 | * the queue are next to be submitted but since a context may not occur twice in | |
118 | * an execution list, if subsequent requests have the same ID as the first then | |
119 | * the two requests must be combined. This is done simply by discarding requests | |
120 | * at the head of the queue until either only one requests is left (in which case | |
121 | * we use a NULL second context) or the first two requests have unique IDs. | |
122 | * | |
123 | * By always executing the first two requests in the queue the driver ensures | |
124 | * that the GPU is kept as busy as possible. In the case where a single context | |
125 | * completes but a second context is still executing, the request for this second | |
126 | * context will be at the head of the queue when we remove the first one. This | |
127 | * request will then be resubmitted along with a new request for a different context, | |
128 | * which will cause the hardware to continue executing the second request and queue | |
129 | * the new request (the GPU detects the condition of a context getting preempted | |
130 | * with the same context and optimizes the context switch flow by not doing | |
131 | * preemption, but just sampling the new tail pointer). | |
132 | * | |
b20385f1 OM |
133 | */ |
134 | ||
135 | #include <drm/drmP.h> | |
136 | #include <drm/i915_drm.h> | |
137 | #include "i915_drv.h" | |
3bbaba0c | 138 | #include "intel_mocs.h" |
127f1003 | 139 | |
468c6816 | 140 | #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE) |
8c857917 OM |
141 | #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE) |
142 | #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE) | |
143 | ||
e981e7b1 TD |
144 | #define RING_EXECLIST_QFULL (1 << 0x2) |
145 | #define RING_EXECLIST1_VALID (1 << 0x3) | |
146 | #define RING_EXECLIST0_VALID (1 << 0x4) | |
147 | #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE) | |
148 | #define RING_EXECLIST1_ACTIVE (1 << 0x11) | |
149 | #define RING_EXECLIST0_ACTIVE (1 << 0x12) | |
150 | ||
151 | #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0) | |
152 | #define GEN8_CTX_STATUS_PREEMPTED (1 << 1) | |
153 | #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2) | |
154 | #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3) | |
155 | #define GEN8_CTX_STATUS_COMPLETE (1 << 4) | |
156 | #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15) | |
8670d6f9 OM |
157 | |
158 | #define CTX_LRI_HEADER_0 0x01 | |
159 | #define CTX_CONTEXT_CONTROL 0x02 | |
160 | #define CTX_RING_HEAD 0x04 | |
161 | #define CTX_RING_TAIL 0x06 | |
162 | #define CTX_RING_BUFFER_START 0x08 | |
163 | #define CTX_RING_BUFFER_CONTROL 0x0a | |
164 | #define CTX_BB_HEAD_U 0x0c | |
165 | #define CTX_BB_HEAD_L 0x0e | |
166 | #define CTX_BB_STATE 0x10 | |
167 | #define CTX_SECOND_BB_HEAD_U 0x12 | |
168 | #define CTX_SECOND_BB_HEAD_L 0x14 | |
169 | #define CTX_SECOND_BB_STATE 0x16 | |
170 | #define CTX_BB_PER_CTX_PTR 0x18 | |
171 | #define CTX_RCS_INDIRECT_CTX 0x1a | |
172 | #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c | |
173 | #define CTX_LRI_HEADER_1 0x21 | |
174 | #define CTX_CTX_TIMESTAMP 0x22 | |
175 | #define CTX_PDP3_UDW 0x24 | |
176 | #define CTX_PDP3_LDW 0x26 | |
177 | #define CTX_PDP2_UDW 0x28 | |
178 | #define CTX_PDP2_LDW 0x2a | |
179 | #define CTX_PDP1_UDW 0x2c | |
180 | #define CTX_PDP1_LDW 0x2e | |
181 | #define CTX_PDP0_UDW 0x30 | |
182 | #define CTX_PDP0_LDW 0x32 | |
183 | #define CTX_LRI_HEADER_2 0x41 | |
184 | #define CTX_R_PWR_CLK_STATE 0x42 | |
185 | #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44 | |
186 | ||
84b790f8 BW |
187 | #define GEN8_CTX_VALID (1<<0) |
188 | #define GEN8_CTX_FORCE_PD_RESTORE (1<<1) | |
189 | #define GEN8_CTX_FORCE_RESTORE (1<<2) | |
190 | #define GEN8_CTX_L3LLC_COHERENT (1<<5) | |
191 | #define GEN8_CTX_PRIVILEGE (1<<8) | |
e5815a2e MT |
192 | |
193 | #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) { \ | |
d852c7bf | 194 | const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \ |
e5815a2e MT |
195 | reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \ |
196 | reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \ | |
197 | } | |
198 | ||
84b790f8 BW |
199 | enum { |
200 | ADVANCED_CONTEXT = 0, | |
201 | LEGACY_CONTEXT, | |
202 | ADVANCED_AD_CONTEXT, | |
203 | LEGACY_64B_CONTEXT | |
204 | }; | |
205 | #define GEN8_CTX_MODE_SHIFT 3 | |
206 | enum { | |
207 | FAULT_AND_HANG = 0, | |
208 | FAULT_AND_HALT, /* Debug only */ | |
209 | FAULT_AND_STREAM, | |
210 | FAULT_AND_CONTINUE /* Unsupported */ | |
211 | }; | |
212 | #define GEN8_CTX_ID_SHIFT 32 | |
17ee950d | 213 | #define CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17 |
84b790f8 | 214 | |
8ba319da | 215 | static int intel_lr_context_pin(struct drm_i915_gem_request *rq); |
7ba717cf | 216 | |
73e4d07f OM |
217 | /** |
218 | * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists | |
219 | * @dev: DRM device. | |
220 | * @enable_execlists: value of i915.enable_execlists module parameter. | |
221 | * | |
222 | * Only certain platforms support Execlists (the prerequisites being | |
27401d12 | 223 | * support for Logical Ring Contexts and Aliasing PPGTT or better). |
73e4d07f OM |
224 | * |
225 | * Return: 1 if Execlists is supported and has to be enabled. | |
226 | */ | |
127f1003 OM |
227 | int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists) |
228 | { | |
bd84b1e9 DV |
229 | WARN_ON(i915.enable_ppgtt == -1); |
230 | ||
70ee45e1 DL |
231 | if (INTEL_INFO(dev)->gen >= 9) |
232 | return 1; | |
233 | ||
127f1003 OM |
234 | if (enable_execlists == 0) |
235 | return 0; | |
236 | ||
14bf993e OM |
237 | if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) && |
238 | i915.use_mmio_flip >= 0) | |
127f1003 OM |
239 | return 1; |
240 | ||
241 | return 0; | |
242 | } | |
ede7d42b | 243 | |
73e4d07f OM |
244 | /** |
245 | * intel_execlists_ctx_id() - get the Execlists Context ID | |
246 | * @ctx_obj: Logical Ring Context backing object. | |
247 | * | |
248 | * Do not confuse with ctx->id! Unfortunately we have a name overload | |
249 | * here: the old context ID we pass to userspace as a handler so that | |
250 | * they can refer to a context, and the new context ID we pass to the | |
251 | * ELSP so that the GPU can inform us of the context status via | |
252 | * interrupts. | |
253 | * | |
254 | * Return: 20-bits globally unique context ID. | |
255 | */ | |
84b790f8 BW |
256 | u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj) |
257 | { | |
258 | u32 lrca = i915_gem_obj_ggtt_offset(ctx_obj); | |
259 | ||
260 | /* LRCA is required to be 4K aligned so the more significant 20 bits | |
261 | * are globally unique */ | |
262 | return lrca >> 12; | |
263 | } | |
264 | ||
8ee36152 | 265 | static uint64_t execlists_ctx_descriptor(struct drm_i915_gem_request *rq) |
84b790f8 | 266 | { |
8ee36152 | 267 | struct intel_engine_cs *ring = rq->ring; |
203a571b | 268 | struct drm_device *dev = ring->dev; |
8ee36152 | 269 | struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state; |
84b790f8 BW |
270 | uint64_t desc; |
271 | uint64_t lrca = i915_gem_obj_ggtt_offset(ctx_obj); | |
acdd884a MT |
272 | |
273 | WARN_ON(lrca & 0xFFFFFFFF00000FFFULL); | |
84b790f8 BW |
274 | |
275 | desc = GEN8_CTX_VALID; | |
276 | desc |= LEGACY_CONTEXT << GEN8_CTX_MODE_SHIFT; | |
51847fb9 AS |
277 | if (IS_GEN8(ctx_obj->base.dev)) |
278 | desc |= GEN8_CTX_L3LLC_COHERENT; | |
84b790f8 BW |
279 | desc |= GEN8_CTX_PRIVILEGE; |
280 | desc |= lrca; | |
281 | desc |= (u64)intel_execlists_ctx_id(ctx_obj) << GEN8_CTX_ID_SHIFT; | |
282 | ||
283 | /* TODO: WaDisableLiteRestore when we start using semaphore | |
284 | * signalling between Command Streamers */ | |
285 | /* desc |= GEN8_CTX_FORCE_RESTORE; */ | |
286 | ||
203a571b NH |
287 | /* WaEnableForceRestoreInCtxtDescForVCS:skl */ |
288 | if (IS_GEN9(dev) && | |
289 | INTEL_REVID(dev) <= SKL_REVID_B0 && | |
290 | (ring->id == BCS || ring->id == VCS || | |
291 | ring->id == VECS || ring->id == VCS2)) | |
292 | desc |= GEN8_CTX_FORCE_RESTORE; | |
293 | ||
84b790f8 BW |
294 | return desc; |
295 | } | |
296 | ||
cc3c4253 MK |
297 | static void execlists_elsp_write(struct drm_i915_gem_request *rq0, |
298 | struct drm_i915_gem_request *rq1) | |
84b790f8 | 299 | { |
cc3c4253 MK |
300 | |
301 | struct intel_engine_cs *ring = rq0->ring; | |
6e7cc470 TU |
302 | struct drm_device *dev = ring->dev; |
303 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1cff8cc3 | 304 | uint64_t desc[2]; |
84b790f8 | 305 | |
1cff8cc3 MK |
306 | if (rq1) { |
307 | desc[1] = execlists_ctx_descriptor(rq1); | |
308 | rq1->elsp_submitted++; | |
309 | } else { | |
310 | desc[1] = 0; | |
311 | } | |
84b790f8 | 312 | |
1cff8cc3 MK |
313 | desc[0] = execlists_ctx_descriptor(rq0); |
314 | rq0->elsp_submitted++; | |
84b790f8 | 315 | |
1cff8cc3 | 316 | /* You must always write both descriptors in the order below. */ |
a6111f7b CW |
317 | spin_lock(&dev_priv->uncore.lock); |
318 | intel_uncore_forcewake_get__locked(dev_priv, FORCEWAKE_ALL); | |
1cff8cc3 MK |
319 | I915_WRITE_FW(RING_ELSP(ring), upper_32_bits(desc[1])); |
320 | I915_WRITE_FW(RING_ELSP(ring), lower_32_bits(desc[1])); | |
6daccb0b | 321 | |
1cff8cc3 | 322 | I915_WRITE_FW(RING_ELSP(ring), upper_32_bits(desc[0])); |
84b790f8 | 323 | /* The context is automatically loaded after the following */ |
1cff8cc3 | 324 | I915_WRITE_FW(RING_ELSP(ring), lower_32_bits(desc[0])); |
84b790f8 | 325 | |
1cff8cc3 | 326 | /* ELSP is a wo register, use another nearby reg for posting */ |
a6111f7b CW |
327 | POSTING_READ_FW(RING_EXECLIST_STATUS(ring)); |
328 | intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL); | |
329 | spin_unlock(&dev_priv->uncore.lock); | |
84b790f8 BW |
330 | } |
331 | ||
05d9824b | 332 | static int execlists_update_context(struct drm_i915_gem_request *rq) |
ae1250b9 | 333 | { |
05d9824b MK |
334 | struct intel_engine_cs *ring = rq->ring; |
335 | struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt; | |
336 | struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state; | |
337 | struct drm_i915_gem_object *rb_obj = rq->ringbuf->obj; | |
ae1250b9 OM |
338 | struct page *page; |
339 | uint32_t *reg_state; | |
340 | ||
05d9824b MK |
341 | BUG_ON(!ctx_obj); |
342 | WARN_ON(!i915_gem_obj_is_pinned(ctx_obj)); | |
343 | WARN_ON(!i915_gem_obj_is_pinned(rb_obj)); | |
344 | ||
ae1250b9 OM |
345 | page = i915_gem_object_get_page(ctx_obj, 1); |
346 | reg_state = kmap_atomic(page); | |
347 | ||
05d9824b MK |
348 | reg_state[CTX_RING_TAIL+1] = rq->tail; |
349 | reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(rb_obj); | |
ae1250b9 | 350 | |
d7b2633d MT |
351 | /* True PPGTT with dynamic page allocation: update PDP registers and |
352 | * point the unallocated PDPs to the scratch page | |
353 | */ | |
354 | if (ppgtt) { | |
355 | ASSIGN_CTX_PDP(ppgtt, reg_state, 3); | |
356 | ASSIGN_CTX_PDP(ppgtt, reg_state, 2); | |
357 | ASSIGN_CTX_PDP(ppgtt, reg_state, 1); | |
358 | ASSIGN_CTX_PDP(ppgtt, reg_state, 0); | |
359 | } | |
360 | ||
ae1250b9 OM |
361 | kunmap_atomic(reg_state); |
362 | ||
363 | return 0; | |
364 | } | |
365 | ||
d8cb8875 MK |
366 | static void execlists_submit_requests(struct drm_i915_gem_request *rq0, |
367 | struct drm_i915_gem_request *rq1) | |
84b790f8 | 368 | { |
05d9824b | 369 | execlists_update_context(rq0); |
d8cb8875 | 370 | |
cc3c4253 | 371 | if (rq1) |
05d9824b | 372 | execlists_update_context(rq1); |
84b790f8 | 373 | |
cc3c4253 | 374 | execlists_elsp_write(rq0, rq1); |
84b790f8 BW |
375 | } |
376 | ||
acdd884a MT |
377 | static void execlists_context_unqueue(struct intel_engine_cs *ring) |
378 | { | |
6d3d8274 NH |
379 | struct drm_i915_gem_request *req0 = NULL, *req1 = NULL; |
380 | struct drm_i915_gem_request *cursor = NULL, *tmp = NULL; | |
e981e7b1 TD |
381 | |
382 | assert_spin_locked(&ring->execlist_lock); | |
acdd884a | 383 | |
779949f4 PA |
384 | /* |
385 | * If irqs are not active generate a warning as batches that finish | |
386 | * without the irqs may get lost and a GPU Hang may occur. | |
387 | */ | |
388 | WARN_ON(!intel_irqs_enabled(ring->dev->dev_private)); | |
389 | ||
acdd884a MT |
390 | if (list_empty(&ring->execlist_queue)) |
391 | return; | |
392 | ||
393 | /* Try to read in pairs */ | |
394 | list_for_each_entry_safe(cursor, tmp, &ring->execlist_queue, | |
395 | execlist_link) { | |
396 | if (!req0) { | |
397 | req0 = cursor; | |
6d3d8274 | 398 | } else if (req0->ctx == cursor->ctx) { |
acdd884a MT |
399 | /* Same ctx: ignore first request, as second request |
400 | * will update tail past first request's workload */ | |
e1fee72c | 401 | cursor->elsp_submitted = req0->elsp_submitted; |
acdd884a | 402 | list_del(&req0->execlist_link); |
c86ee3a9 TD |
403 | list_add_tail(&req0->execlist_link, |
404 | &ring->execlist_retired_req_list); | |
acdd884a MT |
405 | req0 = cursor; |
406 | } else { | |
407 | req1 = cursor; | |
408 | break; | |
409 | } | |
410 | } | |
411 | ||
53292cdb MT |
412 | if (IS_GEN8(ring->dev) || IS_GEN9(ring->dev)) { |
413 | /* | |
414 | * WaIdleLiteRestore: make sure we never cause a lite | |
415 | * restore with HEAD==TAIL | |
416 | */ | |
d63f820f | 417 | if (req0->elsp_submitted) { |
53292cdb MT |
418 | /* |
419 | * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL | |
420 | * as we resubmit the request. See gen8_emit_request() | |
421 | * for where we prepare the padding after the end of the | |
422 | * request. | |
423 | */ | |
424 | struct intel_ringbuffer *ringbuf; | |
425 | ||
426 | ringbuf = req0->ctx->engine[ring->id].ringbuf; | |
427 | req0->tail += 8; | |
428 | req0->tail &= ringbuf->size - 1; | |
429 | } | |
430 | } | |
431 | ||
e1fee72c OM |
432 | WARN_ON(req1 && req1->elsp_submitted); |
433 | ||
d8cb8875 | 434 | execlists_submit_requests(req0, req1); |
acdd884a MT |
435 | } |
436 | ||
e981e7b1 TD |
437 | static bool execlists_check_remove_request(struct intel_engine_cs *ring, |
438 | u32 request_id) | |
439 | { | |
6d3d8274 | 440 | struct drm_i915_gem_request *head_req; |
e981e7b1 TD |
441 | |
442 | assert_spin_locked(&ring->execlist_lock); | |
443 | ||
444 | head_req = list_first_entry_or_null(&ring->execlist_queue, | |
6d3d8274 | 445 | struct drm_i915_gem_request, |
e981e7b1 TD |
446 | execlist_link); |
447 | ||
448 | if (head_req != NULL) { | |
449 | struct drm_i915_gem_object *ctx_obj = | |
6d3d8274 | 450 | head_req->ctx->engine[ring->id].state; |
e981e7b1 | 451 | if (intel_execlists_ctx_id(ctx_obj) == request_id) { |
e1fee72c OM |
452 | WARN(head_req->elsp_submitted == 0, |
453 | "Never submitted head request\n"); | |
454 | ||
455 | if (--head_req->elsp_submitted <= 0) { | |
456 | list_del(&head_req->execlist_link); | |
c86ee3a9 TD |
457 | list_add_tail(&head_req->execlist_link, |
458 | &ring->execlist_retired_req_list); | |
e1fee72c OM |
459 | return true; |
460 | } | |
e981e7b1 TD |
461 | } |
462 | } | |
463 | ||
464 | return false; | |
465 | } | |
466 | ||
73e4d07f | 467 | /** |
3f7531c3 | 468 | * intel_lrc_irq_handler() - handle Context Switch interrupts |
73e4d07f OM |
469 | * @ring: Engine Command Streamer to handle. |
470 | * | |
471 | * Check the unread Context Status Buffers and manage the submission of new | |
472 | * contexts to the ELSP accordingly. | |
473 | */ | |
3f7531c3 | 474 | void intel_lrc_irq_handler(struct intel_engine_cs *ring) |
e981e7b1 TD |
475 | { |
476 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
477 | u32 status_pointer; | |
478 | u8 read_pointer; | |
479 | u8 write_pointer; | |
480 | u32 status; | |
481 | u32 status_id; | |
482 | u32 submit_contexts = 0; | |
483 | ||
484 | status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring)); | |
485 | ||
486 | read_pointer = ring->next_context_status_buffer; | |
487 | write_pointer = status_pointer & 0x07; | |
488 | if (read_pointer > write_pointer) | |
489 | write_pointer += 6; | |
490 | ||
491 | spin_lock(&ring->execlist_lock); | |
492 | ||
493 | while (read_pointer < write_pointer) { | |
494 | read_pointer++; | |
495 | status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + | |
496 | (read_pointer % 6) * 8); | |
497 | status_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + | |
498 | (read_pointer % 6) * 8 + 4); | |
499 | ||
031a8936 MK |
500 | if (status & GEN8_CTX_STATUS_IDLE_ACTIVE) |
501 | continue; | |
502 | ||
e1fee72c OM |
503 | if (status & GEN8_CTX_STATUS_PREEMPTED) { |
504 | if (status & GEN8_CTX_STATUS_LITE_RESTORE) { | |
505 | if (execlists_check_remove_request(ring, status_id)) | |
506 | WARN(1, "Lite Restored request removed from queue\n"); | |
507 | } else | |
508 | WARN(1, "Preemption without Lite Restore\n"); | |
509 | } | |
510 | ||
511 | if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) || | |
512 | (status & GEN8_CTX_STATUS_ELEMENT_SWITCH)) { | |
e981e7b1 TD |
513 | if (execlists_check_remove_request(ring, status_id)) |
514 | submit_contexts++; | |
515 | } | |
516 | } | |
517 | ||
518 | if (submit_contexts != 0) | |
519 | execlists_context_unqueue(ring); | |
520 | ||
521 | spin_unlock(&ring->execlist_lock); | |
522 | ||
523 | WARN(submit_contexts > 2, "More than two context complete events?\n"); | |
524 | ring->next_context_status_buffer = write_pointer % 6; | |
525 | ||
526 | I915_WRITE(RING_CONTEXT_STATUS_PTR(ring), | |
cc53699b | 527 | _MASKED_FIELD(0x07 << 8, ((u32)ring->next_context_status_buffer & 0x07) << 8)); |
e981e7b1 TD |
528 | } |
529 | ||
ae70797d | 530 | static int execlists_context_queue(struct drm_i915_gem_request *request) |
acdd884a | 531 | { |
ae70797d | 532 | struct intel_engine_cs *ring = request->ring; |
6d3d8274 | 533 | struct drm_i915_gem_request *cursor; |
f1ad5a1f | 534 | int num_elements = 0; |
acdd884a | 535 | |
ae70797d | 536 | if (request->ctx != ring->default_context) |
8ba319da | 537 | intel_lr_context_pin(request); |
9bb1af44 JH |
538 | |
539 | i915_gem_request_reference(request); | |
540 | ||
ae70797d | 541 | request->tail = request->ringbuf->tail; |
2d12955a | 542 | |
b5eba372 | 543 | spin_lock_irq(&ring->execlist_lock); |
acdd884a | 544 | |
f1ad5a1f OM |
545 | list_for_each_entry(cursor, &ring->execlist_queue, execlist_link) |
546 | if (++num_elements > 2) | |
547 | break; | |
548 | ||
549 | if (num_elements > 2) { | |
6d3d8274 | 550 | struct drm_i915_gem_request *tail_req; |
f1ad5a1f OM |
551 | |
552 | tail_req = list_last_entry(&ring->execlist_queue, | |
6d3d8274 | 553 | struct drm_i915_gem_request, |
f1ad5a1f OM |
554 | execlist_link); |
555 | ||
ae70797d | 556 | if (request->ctx == tail_req->ctx) { |
f1ad5a1f | 557 | WARN(tail_req->elsp_submitted != 0, |
7ba717cf | 558 | "More than 2 already-submitted reqs queued\n"); |
f1ad5a1f | 559 | list_del(&tail_req->execlist_link); |
c86ee3a9 TD |
560 | list_add_tail(&tail_req->execlist_link, |
561 | &ring->execlist_retired_req_list); | |
f1ad5a1f OM |
562 | } |
563 | } | |
564 | ||
6d3d8274 | 565 | list_add_tail(&request->execlist_link, &ring->execlist_queue); |
f1ad5a1f | 566 | if (num_elements == 0) |
acdd884a MT |
567 | execlists_context_unqueue(ring); |
568 | ||
b5eba372 | 569 | spin_unlock_irq(&ring->execlist_lock); |
acdd884a MT |
570 | |
571 | return 0; | |
572 | } | |
573 | ||
2f20055d | 574 | static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request *req) |
ba8b7ccb | 575 | { |
2f20055d | 576 | struct intel_engine_cs *ring = req->ring; |
ba8b7ccb OM |
577 | uint32_t flush_domains; |
578 | int ret; | |
579 | ||
580 | flush_domains = 0; | |
581 | if (ring->gpu_caches_dirty) | |
582 | flush_domains = I915_GEM_GPU_DOMAINS; | |
583 | ||
7deb4d39 | 584 | ret = ring->emit_flush(req, I915_GEM_GPU_DOMAINS, flush_domains); |
ba8b7ccb OM |
585 | if (ret) |
586 | return ret; | |
587 | ||
588 | ring->gpu_caches_dirty = false; | |
589 | return 0; | |
590 | } | |
591 | ||
535fbe82 | 592 | static int execlists_move_to_gpu(struct drm_i915_gem_request *req, |
ba8b7ccb OM |
593 | struct list_head *vmas) |
594 | { | |
535fbe82 | 595 | const unsigned other_rings = ~intel_ring_flag(req->ring); |
ba8b7ccb OM |
596 | struct i915_vma *vma; |
597 | uint32_t flush_domains = 0; | |
598 | bool flush_chipset = false; | |
599 | int ret; | |
600 | ||
601 | list_for_each_entry(vma, vmas, exec_list) { | |
602 | struct drm_i915_gem_object *obj = vma->obj; | |
603 | ||
03ade511 | 604 | if (obj->active & other_rings) { |
91af127f | 605 | ret = i915_gem_object_sync(obj, req->ring, &req); |
03ade511 CW |
606 | if (ret) |
607 | return ret; | |
608 | } | |
ba8b7ccb OM |
609 | |
610 | if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) | |
611 | flush_chipset |= i915_gem_clflush_object(obj, false); | |
612 | ||
613 | flush_domains |= obj->base.write_domain; | |
614 | } | |
615 | ||
616 | if (flush_domains & I915_GEM_DOMAIN_GTT) | |
617 | wmb(); | |
618 | ||
619 | /* Unconditionally invalidate gpu caches and ensure that we do flush | |
620 | * any residual writes from the previous batch. | |
621 | */ | |
2f20055d | 622 | return logical_ring_invalidate_all_caches(req); |
ba8b7ccb OM |
623 | } |
624 | ||
40e895ce | 625 | int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request) |
bc0dce3f | 626 | { |
bc0dce3f JH |
627 | int ret; |
628 | ||
f3cc01f0 MK |
629 | request->ringbuf = request->ctx->engine[request->ring->id].ringbuf; |
630 | ||
40e895ce | 631 | if (request->ctx != request->ring->default_context) { |
8ba319da | 632 | ret = intel_lr_context_pin(request); |
6689cb2b | 633 | if (ret) |
bc0dce3f | 634 | return ret; |
bc0dce3f JH |
635 | } |
636 | ||
bc0dce3f JH |
637 | return 0; |
638 | } | |
639 | ||
ae70797d | 640 | static int logical_ring_wait_for_space(struct drm_i915_gem_request *req, |
595e1eeb | 641 | int bytes) |
bc0dce3f | 642 | { |
ae70797d JH |
643 | struct intel_ringbuffer *ringbuf = req->ringbuf; |
644 | struct intel_engine_cs *ring = req->ring; | |
645 | struct drm_i915_gem_request *target; | |
b4716185 CW |
646 | unsigned space; |
647 | int ret; | |
bc0dce3f JH |
648 | |
649 | if (intel_ring_space(ringbuf) >= bytes) | |
650 | return 0; | |
651 | ||
79bbcc29 JH |
652 | /* The whole point of reserving space is to not wait! */ |
653 | WARN_ON(ringbuf->reserved_in_use); | |
654 | ||
ae70797d | 655 | list_for_each_entry(target, &ring->request_list, list) { |
bc0dce3f JH |
656 | /* |
657 | * The request queue is per-engine, so can contain requests | |
658 | * from multiple ringbuffers. Here, we must ignore any that | |
659 | * aren't from the ringbuffer we're considering. | |
660 | */ | |
ae70797d | 661 | if (target->ringbuf != ringbuf) |
bc0dce3f JH |
662 | continue; |
663 | ||
664 | /* Would completion of this request free enough space? */ | |
ae70797d | 665 | space = __intel_ring_space(target->postfix, ringbuf->tail, |
b4716185 CW |
666 | ringbuf->size); |
667 | if (space >= bytes) | |
bc0dce3f | 668 | break; |
bc0dce3f JH |
669 | } |
670 | ||
ae70797d | 671 | if (WARN_ON(&target->list == &ring->request_list)) |
bc0dce3f JH |
672 | return -ENOSPC; |
673 | ||
ae70797d | 674 | ret = i915_wait_request(target); |
bc0dce3f JH |
675 | if (ret) |
676 | return ret; | |
677 | ||
b4716185 CW |
678 | ringbuf->space = space; |
679 | return 0; | |
bc0dce3f JH |
680 | } |
681 | ||
682 | /* | |
683 | * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload | |
ae70797d | 684 | * @request: Request to advance the logical ringbuffer of. |
bc0dce3f JH |
685 | * |
686 | * The tail is updated in our logical ringbuffer struct, not in the actual context. What | |
687 | * really happens during submission is that the context and current tail will be placed | |
688 | * on a queue waiting for the ELSP to be ready to accept a new context submission. At that | |
689 | * point, the tail *inside* the context is updated and the ELSP written to. | |
690 | */ | |
691 | static void | |
ae70797d | 692 | intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request) |
bc0dce3f | 693 | { |
ae70797d | 694 | struct intel_engine_cs *ring = request->ring; |
bc0dce3f | 695 | |
ae70797d | 696 | intel_logical_ring_advance(request->ringbuf); |
bc0dce3f JH |
697 | |
698 | if (intel_ring_stopped(ring)) | |
699 | return; | |
700 | ||
ae70797d | 701 | execlists_context_queue(request); |
bc0dce3f JH |
702 | } |
703 | ||
79bbcc29 | 704 | static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf) |
bc0dce3f JH |
705 | { |
706 | uint32_t __iomem *virt; | |
707 | int rem = ringbuf->size - ringbuf->tail; | |
708 | ||
bc0dce3f JH |
709 | virt = ringbuf->virtual_start + ringbuf->tail; |
710 | rem /= 4; | |
711 | while (rem--) | |
712 | iowrite32(MI_NOOP, virt++); | |
713 | ||
714 | ringbuf->tail = 0; | |
715 | intel_ring_update_space(ringbuf); | |
bc0dce3f JH |
716 | } |
717 | ||
ae70797d | 718 | static int logical_ring_prepare(struct drm_i915_gem_request *req, int bytes) |
bc0dce3f | 719 | { |
ae70797d | 720 | struct intel_ringbuffer *ringbuf = req->ringbuf; |
79bbcc29 JH |
721 | int remain_usable = ringbuf->effective_size - ringbuf->tail; |
722 | int remain_actual = ringbuf->size - ringbuf->tail; | |
723 | int ret, total_bytes, wait_bytes = 0; | |
724 | bool need_wrap = false; | |
29b1b415 | 725 | |
79bbcc29 JH |
726 | if (ringbuf->reserved_in_use) |
727 | total_bytes = bytes; | |
728 | else | |
729 | total_bytes = bytes + ringbuf->reserved_size; | |
29b1b415 | 730 | |
79bbcc29 JH |
731 | if (unlikely(bytes > remain_usable)) { |
732 | /* | |
733 | * Not enough space for the basic request. So need to flush | |
734 | * out the remainder and then wait for base + reserved. | |
735 | */ | |
736 | wait_bytes = remain_actual + total_bytes; | |
737 | need_wrap = true; | |
738 | } else { | |
739 | if (unlikely(total_bytes > remain_usable)) { | |
740 | /* | |
741 | * The base request will fit but the reserved space | |
742 | * falls off the end. So only need to to wait for the | |
743 | * reserved size after flushing out the remainder. | |
744 | */ | |
745 | wait_bytes = remain_actual + ringbuf->reserved_size; | |
746 | need_wrap = true; | |
747 | } else if (total_bytes > ringbuf->space) { | |
748 | /* No wrapping required, just waiting. */ | |
749 | wait_bytes = total_bytes; | |
29b1b415 | 750 | } |
bc0dce3f JH |
751 | } |
752 | ||
79bbcc29 JH |
753 | if (wait_bytes) { |
754 | ret = logical_ring_wait_for_space(req, wait_bytes); | |
bc0dce3f JH |
755 | if (unlikely(ret)) |
756 | return ret; | |
79bbcc29 JH |
757 | |
758 | if (need_wrap) | |
759 | __wrap_ring_buffer(ringbuf); | |
bc0dce3f JH |
760 | } |
761 | ||
762 | return 0; | |
763 | } | |
764 | ||
765 | /** | |
766 | * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands | |
767 | * | |
4d616a29 | 768 | * @request: The request to start some new work for |
4d78c8dc | 769 | * @ctx: Logical ring context whose ringbuffer is being prepared. |
bc0dce3f JH |
770 | * @num_dwords: number of DWORDs that we plan to write to the ringbuffer. |
771 | * | |
772 | * The ringbuffer might not be ready to accept the commands right away (maybe it needs to | |
773 | * be wrapped, or wait a bit for the tail to be updated). This function takes care of that | |
774 | * and also preallocates a request (every workload submission is still mediated through | |
775 | * requests, same as it did with legacy ringbuffer submission). | |
776 | * | |
777 | * Return: non-zero if the ringbuffer is not ready to be written to. | |
778 | */ | |
3bbaba0c | 779 | int intel_logical_ring_begin(struct drm_i915_gem_request *req, int num_dwords) |
bc0dce3f | 780 | { |
4d616a29 | 781 | struct drm_i915_private *dev_priv; |
bc0dce3f JH |
782 | int ret; |
783 | ||
4d616a29 JH |
784 | WARN_ON(req == NULL); |
785 | dev_priv = req->ring->dev->dev_private; | |
786 | ||
bc0dce3f JH |
787 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
788 | dev_priv->mm.interruptible); | |
789 | if (ret) | |
790 | return ret; | |
791 | ||
ae70797d | 792 | ret = logical_ring_prepare(req, num_dwords * sizeof(uint32_t)); |
bc0dce3f JH |
793 | if (ret) |
794 | return ret; | |
795 | ||
4d616a29 | 796 | req->ringbuf->space -= num_dwords * sizeof(uint32_t); |
bc0dce3f JH |
797 | return 0; |
798 | } | |
799 | ||
ccd98fe4 JH |
800 | int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request) |
801 | { | |
802 | /* | |
803 | * The first call merely notes the reserve request and is common for | |
804 | * all back ends. The subsequent localised _begin() call actually | |
805 | * ensures that the reservation is available. Without the begin, if | |
806 | * the request creator immediately submitted the request without | |
807 | * adding any commands to it then there might not actually be | |
808 | * sufficient room for the submission commands. | |
809 | */ | |
810 | intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST); | |
811 | ||
812 | return intel_logical_ring_begin(request, 0); | |
813 | } | |
814 | ||
73e4d07f OM |
815 | /** |
816 | * execlists_submission() - submit a batchbuffer for execution, Execlists style | |
817 | * @dev: DRM device. | |
818 | * @file: DRM file. | |
819 | * @ring: Engine Command Streamer to submit to. | |
820 | * @ctx: Context to employ for this submission. | |
821 | * @args: execbuffer call arguments. | |
822 | * @vmas: list of vmas. | |
823 | * @batch_obj: the batchbuffer to submit. | |
824 | * @exec_start: batchbuffer start virtual address pointer. | |
8e004efc | 825 | * @dispatch_flags: translated execbuffer call flags. |
73e4d07f OM |
826 | * |
827 | * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts | |
828 | * away the submission details of the execbuffer ioctl call. | |
829 | * | |
830 | * Return: non-zero if the submission fails. | |
831 | */ | |
5f19e2bf | 832 | int intel_execlists_submission(struct i915_execbuffer_params *params, |
454afebd | 833 | struct drm_i915_gem_execbuffer2 *args, |
5f19e2bf | 834 | struct list_head *vmas) |
454afebd | 835 | { |
5f19e2bf JH |
836 | struct drm_device *dev = params->dev; |
837 | struct intel_engine_cs *ring = params->ring; | |
ba8b7ccb | 838 | struct drm_i915_private *dev_priv = dev->dev_private; |
5f19e2bf JH |
839 | struct intel_ringbuffer *ringbuf = params->ctx->engine[ring->id].ringbuf; |
840 | u64 exec_start; | |
ba8b7ccb OM |
841 | int instp_mode; |
842 | u32 instp_mask; | |
843 | int ret; | |
844 | ||
845 | instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK; | |
846 | instp_mask = I915_EXEC_CONSTANTS_MASK; | |
847 | switch (instp_mode) { | |
848 | case I915_EXEC_CONSTANTS_REL_GENERAL: | |
849 | case I915_EXEC_CONSTANTS_ABSOLUTE: | |
850 | case I915_EXEC_CONSTANTS_REL_SURFACE: | |
851 | if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) { | |
852 | DRM_DEBUG("non-0 rel constants mode on non-RCS\n"); | |
853 | return -EINVAL; | |
854 | } | |
855 | ||
856 | if (instp_mode != dev_priv->relative_constants_mode) { | |
857 | if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) { | |
858 | DRM_DEBUG("rel surface constants mode invalid on gen5+\n"); | |
859 | return -EINVAL; | |
860 | } | |
861 | ||
862 | /* The HW changed the meaning on this bit on gen6 */ | |
863 | instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; | |
864 | } | |
865 | break; | |
866 | default: | |
867 | DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode); | |
868 | return -EINVAL; | |
869 | } | |
870 | ||
871 | if (args->num_cliprects != 0) { | |
872 | DRM_DEBUG("clip rectangles are only valid on pre-gen5\n"); | |
873 | return -EINVAL; | |
874 | } else { | |
875 | if (args->DR4 == 0xffffffff) { | |
876 | DRM_DEBUG("UXA submitting garbage DR4, fixing up\n"); | |
877 | args->DR4 = 0; | |
878 | } | |
879 | ||
880 | if (args->DR1 || args->DR4 || args->cliprects_ptr) { | |
881 | DRM_DEBUG("0 cliprects but dirt in cliprects fields\n"); | |
882 | return -EINVAL; | |
883 | } | |
884 | } | |
885 | ||
886 | if (args->flags & I915_EXEC_GEN7_SOL_RESET) { | |
887 | DRM_DEBUG("sol reset is gen7 only\n"); | |
888 | return -EINVAL; | |
889 | } | |
890 | ||
535fbe82 | 891 | ret = execlists_move_to_gpu(params->request, vmas); |
ba8b7ccb OM |
892 | if (ret) |
893 | return ret; | |
894 | ||
895 | if (ring == &dev_priv->ring[RCS] && | |
896 | instp_mode != dev_priv->relative_constants_mode) { | |
4d616a29 | 897 | ret = intel_logical_ring_begin(params->request, 4); |
ba8b7ccb OM |
898 | if (ret) |
899 | return ret; | |
900 | ||
901 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
902 | intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1)); | |
903 | intel_logical_ring_emit(ringbuf, INSTPM); | |
904 | intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode); | |
905 | intel_logical_ring_advance(ringbuf); | |
906 | ||
907 | dev_priv->relative_constants_mode = instp_mode; | |
908 | } | |
909 | ||
5f19e2bf JH |
910 | exec_start = params->batch_obj_vm_offset + |
911 | args->batch_start_offset; | |
912 | ||
be795fc1 | 913 | ret = ring->emit_bb_start(params->request, exec_start, params->dispatch_flags); |
ba8b7ccb OM |
914 | if (ret) |
915 | return ret; | |
916 | ||
95c24161 | 917 | trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags); |
5e4be7bd | 918 | |
8a8edb59 | 919 | i915_gem_execbuffer_move_to_active(vmas, params->request); |
adeca76d | 920 | i915_gem_execbuffer_retire_commands(params); |
ba8b7ccb | 921 | |
454afebd OM |
922 | return 0; |
923 | } | |
924 | ||
c86ee3a9 TD |
925 | void intel_execlists_retire_requests(struct intel_engine_cs *ring) |
926 | { | |
6d3d8274 | 927 | struct drm_i915_gem_request *req, *tmp; |
c86ee3a9 TD |
928 | struct list_head retired_list; |
929 | ||
930 | WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex)); | |
931 | if (list_empty(&ring->execlist_retired_req_list)) | |
932 | return; | |
933 | ||
934 | INIT_LIST_HEAD(&retired_list); | |
b5eba372 | 935 | spin_lock_irq(&ring->execlist_lock); |
c86ee3a9 | 936 | list_replace_init(&ring->execlist_retired_req_list, &retired_list); |
b5eba372 | 937 | spin_unlock_irq(&ring->execlist_lock); |
c86ee3a9 TD |
938 | |
939 | list_for_each_entry_safe(req, tmp, &retired_list, execlist_link) { | |
6d3d8274 | 940 | struct intel_context *ctx = req->ctx; |
7ba717cf TD |
941 | struct drm_i915_gem_object *ctx_obj = |
942 | ctx->engine[ring->id].state; | |
943 | ||
944 | if (ctx_obj && (ctx != ring->default_context)) | |
8ba319da | 945 | intel_lr_context_unpin(req); |
c86ee3a9 | 946 | list_del(&req->execlist_link); |
f8210795 | 947 | i915_gem_request_unreference(req); |
c86ee3a9 TD |
948 | } |
949 | } | |
950 | ||
454afebd OM |
951 | void intel_logical_ring_stop(struct intel_engine_cs *ring) |
952 | { | |
9832b9da OM |
953 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
954 | int ret; | |
955 | ||
956 | if (!intel_ring_initialized(ring)) | |
957 | return; | |
958 | ||
959 | ret = intel_ring_idle(ring); | |
960 | if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error)) | |
961 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", | |
962 | ring->name, ret); | |
963 | ||
964 | /* TODO: Is this correct with Execlists enabled? */ | |
965 | I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING)); | |
966 | if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) { | |
967 | DRM_ERROR("%s :timed out trying to stop ring\n", ring->name); | |
968 | return; | |
969 | } | |
970 | I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING)); | |
454afebd OM |
971 | } |
972 | ||
4866d729 | 973 | int logical_ring_flush_all_caches(struct drm_i915_gem_request *req) |
48e29f55 | 974 | { |
4866d729 | 975 | struct intel_engine_cs *ring = req->ring; |
48e29f55 OM |
976 | int ret; |
977 | ||
978 | if (!ring->gpu_caches_dirty) | |
979 | return 0; | |
980 | ||
7deb4d39 | 981 | ret = ring->emit_flush(req, 0, I915_GEM_GPU_DOMAINS); |
48e29f55 OM |
982 | if (ret) |
983 | return ret; | |
984 | ||
985 | ring->gpu_caches_dirty = false; | |
986 | return 0; | |
987 | } | |
988 | ||
8ba319da | 989 | static int intel_lr_context_pin(struct drm_i915_gem_request *rq) |
dcb4c12a | 990 | { |
8ba319da MK |
991 | struct intel_engine_cs *ring = rq->ring; |
992 | struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state; | |
993 | struct intel_ringbuffer *ringbuf = rq->ringbuf; | |
dcb4c12a OM |
994 | int ret = 0; |
995 | ||
996 | WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex)); | |
8ba319da | 997 | if (rq->ctx->engine[ring->id].pin_count++ == 0) { |
dcb4c12a OM |
998 | ret = i915_gem_obj_ggtt_pin(ctx_obj, |
999 | GEN8_LR_CONTEXT_ALIGN, 0); | |
1000 | if (ret) | |
a7cbedec | 1001 | goto reset_pin_count; |
7ba717cf TD |
1002 | |
1003 | ret = intel_pin_and_map_ringbuffer_obj(ring->dev, ringbuf); | |
1004 | if (ret) | |
1005 | goto unpin_ctx_obj; | |
903ecd0b CW |
1006 | |
1007 | ctx_obj->dirty = true; | |
dcb4c12a OM |
1008 | } |
1009 | ||
7ba717cf TD |
1010 | return ret; |
1011 | ||
1012 | unpin_ctx_obj: | |
1013 | i915_gem_object_ggtt_unpin(ctx_obj); | |
a7cbedec | 1014 | reset_pin_count: |
8ba319da | 1015 | rq->ctx->engine[ring->id].pin_count = 0; |
7ba717cf | 1016 | |
dcb4c12a OM |
1017 | return ret; |
1018 | } | |
1019 | ||
8ba319da | 1020 | void intel_lr_context_unpin(struct drm_i915_gem_request *rq) |
dcb4c12a | 1021 | { |
8ba319da MK |
1022 | struct intel_engine_cs *ring = rq->ring; |
1023 | struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state; | |
1024 | struct intel_ringbuffer *ringbuf = rq->ringbuf; | |
dcb4c12a OM |
1025 | |
1026 | if (ctx_obj) { | |
1027 | WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex)); | |
8ba319da | 1028 | if (--rq->ctx->engine[ring->id].pin_count == 0) { |
7ba717cf | 1029 | intel_unpin_ringbuffer_obj(ringbuf); |
dcb4c12a | 1030 | i915_gem_object_ggtt_unpin(ctx_obj); |
7ba717cf | 1031 | } |
dcb4c12a OM |
1032 | } |
1033 | } | |
1034 | ||
e2be4faf | 1035 | static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req) |
771b9a53 MT |
1036 | { |
1037 | int ret, i; | |
e2be4faf JH |
1038 | struct intel_engine_cs *ring = req->ring; |
1039 | struct intel_ringbuffer *ringbuf = req->ringbuf; | |
771b9a53 MT |
1040 | struct drm_device *dev = ring->dev; |
1041 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1042 | struct i915_workarounds *w = &dev_priv->workarounds; | |
1043 | ||
e6c1abb7 | 1044 | if (WARN_ON_ONCE(w->count == 0)) |
771b9a53 MT |
1045 | return 0; |
1046 | ||
1047 | ring->gpu_caches_dirty = true; | |
4866d729 | 1048 | ret = logical_ring_flush_all_caches(req); |
771b9a53 MT |
1049 | if (ret) |
1050 | return ret; | |
1051 | ||
4d616a29 | 1052 | ret = intel_logical_ring_begin(req, w->count * 2 + 2); |
771b9a53 MT |
1053 | if (ret) |
1054 | return ret; | |
1055 | ||
1056 | intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count)); | |
1057 | for (i = 0; i < w->count; i++) { | |
1058 | intel_logical_ring_emit(ringbuf, w->reg[i].addr); | |
1059 | intel_logical_ring_emit(ringbuf, w->reg[i].value); | |
1060 | } | |
1061 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
1062 | ||
1063 | intel_logical_ring_advance(ringbuf); | |
1064 | ||
1065 | ring->gpu_caches_dirty = true; | |
4866d729 | 1066 | ret = logical_ring_flush_all_caches(req); |
771b9a53 MT |
1067 | if (ret) |
1068 | return ret; | |
1069 | ||
1070 | return 0; | |
1071 | } | |
1072 | ||
83b8a982 | 1073 | #define wa_ctx_emit(batch, index, cmd) \ |
17ee950d | 1074 | do { \ |
83b8a982 AS |
1075 | int __index = (index)++; \ |
1076 | if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \ | |
17ee950d AS |
1077 | return -ENOSPC; \ |
1078 | } \ | |
83b8a982 | 1079 | batch[__index] = (cmd); \ |
17ee950d AS |
1080 | } while (0) |
1081 | ||
9e000847 AS |
1082 | |
1083 | /* | |
1084 | * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after | |
1085 | * PIPE_CONTROL instruction. This is required for the flush to happen correctly | |
1086 | * but there is a slight complication as this is applied in WA batch where the | |
1087 | * values are only initialized once so we cannot take register value at the | |
1088 | * beginning and reuse it further; hence we save its value to memory, upload a | |
1089 | * constant value with bit21 set and then we restore it back with the saved value. | |
1090 | * To simplify the WA, a constant value is formed by using the default value | |
1091 | * of this register. This shouldn't be a problem because we are only modifying | |
1092 | * it for a short period and this batch in non-premptible. We can ofcourse | |
1093 | * use additional instructions that read the actual value of the register | |
1094 | * at that time and set our bit of interest but it makes the WA complicated. | |
1095 | * | |
1096 | * This WA is also required for Gen9 so extracting as a function avoids | |
1097 | * code duplication. | |
1098 | */ | |
1099 | static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *ring, | |
1100 | uint32_t *const batch, | |
1101 | uint32_t index) | |
1102 | { | |
1103 | uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES); | |
1104 | ||
a4106a78 AS |
1105 | /* |
1106 | * WaDisableLSQCROPERFforOCL:skl | |
1107 | * This WA is implemented in skl_init_clock_gating() but since | |
1108 | * this batch updates GEN8_L3SQCREG4 with default value we need to | |
1109 | * set this bit here to retain the WA during flush. | |
1110 | */ | |
1111 | if (IS_SKYLAKE(ring->dev) && INTEL_REVID(ring->dev) <= SKL_REVID_E0) | |
1112 | l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS; | |
1113 | ||
83b8a982 AS |
1114 | wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8(1) | |
1115 | MI_SRM_LRM_GLOBAL_GTT)); | |
1116 | wa_ctx_emit(batch, index, GEN8_L3SQCREG4); | |
1117 | wa_ctx_emit(batch, index, ring->scratch.gtt_offset + 256); | |
1118 | wa_ctx_emit(batch, index, 0); | |
1119 | ||
1120 | wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); | |
1121 | wa_ctx_emit(batch, index, GEN8_L3SQCREG4); | |
1122 | wa_ctx_emit(batch, index, l3sqc4_flush); | |
1123 | ||
1124 | wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6)); | |
1125 | wa_ctx_emit(batch, index, (PIPE_CONTROL_CS_STALL | | |
1126 | PIPE_CONTROL_DC_FLUSH_ENABLE)); | |
1127 | wa_ctx_emit(batch, index, 0); | |
1128 | wa_ctx_emit(batch, index, 0); | |
1129 | wa_ctx_emit(batch, index, 0); | |
1130 | wa_ctx_emit(batch, index, 0); | |
1131 | ||
1132 | wa_ctx_emit(batch, index, (MI_LOAD_REGISTER_MEM_GEN8(1) | | |
1133 | MI_SRM_LRM_GLOBAL_GTT)); | |
1134 | wa_ctx_emit(batch, index, GEN8_L3SQCREG4); | |
1135 | wa_ctx_emit(batch, index, ring->scratch.gtt_offset + 256); | |
1136 | wa_ctx_emit(batch, index, 0); | |
9e000847 AS |
1137 | |
1138 | return index; | |
1139 | } | |
1140 | ||
17ee950d AS |
1141 | static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb *wa_ctx, |
1142 | uint32_t offset, | |
1143 | uint32_t start_alignment) | |
1144 | { | |
1145 | return wa_ctx->offset = ALIGN(offset, start_alignment); | |
1146 | } | |
1147 | ||
1148 | static inline int wa_ctx_end(struct i915_wa_ctx_bb *wa_ctx, | |
1149 | uint32_t offset, | |
1150 | uint32_t size_alignment) | |
1151 | { | |
1152 | wa_ctx->size = offset - wa_ctx->offset; | |
1153 | ||
1154 | WARN(wa_ctx->size % size_alignment, | |
1155 | "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n", | |
1156 | wa_ctx->size, size_alignment); | |
1157 | return 0; | |
1158 | } | |
1159 | ||
1160 | /** | |
1161 | * gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA | |
1162 | * | |
1163 | * @ring: only applicable for RCS | |
1164 | * @wa_ctx: structure representing wa_ctx | |
1165 | * offset: specifies start of the batch, should be cache-aligned. This is updated | |
1166 | * with the offset value received as input. | |
1167 | * size: size of the batch in DWORDS but HW expects in terms of cachelines | |
1168 | * @batch: page in which WA are loaded | |
1169 | * @offset: This field specifies the start of the batch, it should be | |
1170 | * cache-aligned otherwise it is adjusted accordingly. | |
1171 | * Typically we only have one indirect_ctx and per_ctx batch buffer which are | |
1172 | * initialized at the beginning and shared across all contexts but this field | |
1173 | * helps us to have multiple batches at different offsets and select them based | |
1174 | * on a criteria. At the moment this batch always start at the beginning of the page | |
1175 | * and at this point we don't have multiple wa_ctx batch buffers. | |
1176 | * | |
1177 | * The number of WA applied are not known at the beginning; we use this field | |
1178 | * to return the no of DWORDS written. | |
4d78c8dc | 1179 | * |
17ee950d AS |
1180 | * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END |
1181 | * so it adds NOOPs as padding to make it cacheline aligned. | |
1182 | * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together | |
1183 | * makes a complete batch buffer. | |
1184 | * | |
1185 | * Return: non-zero if we exceed the PAGE_SIZE limit. | |
1186 | */ | |
1187 | ||
1188 | static int gen8_init_indirectctx_bb(struct intel_engine_cs *ring, | |
1189 | struct i915_wa_ctx_bb *wa_ctx, | |
1190 | uint32_t *const batch, | |
1191 | uint32_t *offset) | |
1192 | { | |
0160f055 | 1193 | uint32_t scratch_addr; |
17ee950d AS |
1194 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); |
1195 | ||
7ad00d1a | 1196 | /* WaDisableCtxRestoreArbitration:bdw,chv */ |
83b8a982 | 1197 | wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE); |
17ee950d | 1198 | |
c82435bb AS |
1199 | /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */ |
1200 | if (IS_BROADWELL(ring->dev)) { | |
9e000847 AS |
1201 | index = gen8_emit_flush_coherentl3_wa(ring, batch, index); |
1202 | if (index < 0) | |
1203 | return index; | |
c82435bb AS |
1204 | } |
1205 | ||
0160f055 AS |
1206 | /* WaClearSlmSpaceAtContextSwitch:bdw,chv */ |
1207 | /* Actual scratch location is at 128 bytes offset */ | |
1208 | scratch_addr = ring->scratch.gtt_offset + 2*CACHELINE_BYTES; | |
1209 | ||
83b8a982 AS |
1210 | wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6)); |
1211 | wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 | | |
1212 | PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1213 | PIPE_CONTROL_CS_STALL | | |
1214 | PIPE_CONTROL_QW_WRITE)); | |
1215 | wa_ctx_emit(batch, index, scratch_addr); | |
1216 | wa_ctx_emit(batch, index, 0); | |
1217 | wa_ctx_emit(batch, index, 0); | |
1218 | wa_ctx_emit(batch, index, 0); | |
0160f055 | 1219 | |
17ee950d AS |
1220 | /* Pad to end of cacheline */ |
1221 | while (index % CACHELINE_DWORDS) | |
83b8a982 | 1222 | wa_ctx_emit(batch, index, MI_NOOP); |
17ee950d AS |
1223 | |
1224 | /* | |
1225 | * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because | |
1226 | * execution depends on the length specified in terms of cache lines | |
1227 | * in the register CTX_RCS_INDIRECT_CTX | |
1228 | */ | |
1229 | ||
1230 | return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS); | |
1231 | } | |
1232 | ||
1233 | /** | |
1234 | * gen8_init_perctx_bb() - initialize per ctx batch with WA | |
1235 | * | |
1236 | * @ring: only applicable for RCS | |
1237 | * @wa_ctx: structure representing wa_ctx | |
1238 | * offset: specifies start of the batch, should be cache-aligned. | |
1239 | * size: size of the batch in DWORDS but HW expects in terms of cachelines | |
4d78c8dc | 1240 | * @batch: page in which WA are loaded |
17ee950d AS |
1241 | * @offset: This field specifies the start of this batch. |
1242 | * This batch is started immediately after indirect_ctx batch. Since we ensure | |
1243 | * that indirect_ctx ends on a cacheline this batch is aligned automatically. | |
1244 | * | |
1245 | * The number of DWORDS written are returned using this field. | |
1246 | * | |
1247 | * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding | |
1248 | * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant. | |
1249 | */ | |
1250 | static int gen8_init_perctx_bb(struct intel_engine_cs *ring, | |
1251 | struct i915_wa_ctx_bb *wa_ctx, | |
1252 | uint32_t *const batch, | |
1253 | uint32_t *offset) | |
1254 | { | |
1255 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); | |
1256 | ||
7ad00d1a | 1257 | /* WaDisableCtxRestoreArbitration:bdw,chv */ |
83b8a982 | 1258 | wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE); |
7ad00d1a | 1259 | |
83b8a982 | 1260 | wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END); |
17ee950d AS |
1261 | |
1262 | return wa_ctx_end(wa_ctx, *offset = index, 1); | |
1263 | } | |
1264 | ||
0504cffc AS |
1265 | static int gen9_init_indirectctx_bb(struct intel_engine_cs *ring, |
1266 | struct i915_wa_ctx_bb *wa_ctx, | |
1267 | uint32_t *const batch, | |
1268 | uint32_t *offset) | |
1269 | { | |
a4106a78 | 1270 | int ret; |
0907c8f7 | 1271 | struct drm_device *dev = ring->dev; |
0504cffc AS |
1272 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); |
1273 | ||
0907c8f7 AS |
1274 | /* WaDisableCtxRestoreArbitration:skl,bxt */ |
1275 | if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_D0)) || | |
1276 | (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0))) | |
1277 | wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE); | |
0504cffc | 1278 | |
a4106a78 AS |
1279 | /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */ |
1280 | ret = gen8_emit_flush_coherentl3_wa(ring, batch, index); | |
1281 | if (ret < 0) | |
1282 | return ret; | |
1283 | index = ret; | |
1284 | ||
0504cffc AS |
1285 | /* Pad to end of cacheline */ |
1286 | while (index % CACHELINE_DWORDS) | |
1287 | wa_ctx_emit(batch, index, MI_NOOP); | |
1288 | ||
1289 | return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS); | |
1290 | } | |
1291 | ||
1292 | static int gen9_init_perctx_bb(struct intel_engine_cs *ring, | |
1293 | struct i915_wa_ctx_bb *wa_ctx, | |
1294 | uint32_t *const batch, | |
1295 | uint32_t *offset) | |
1296 | { | |
0907c8f7 | 1297 | struct drm_device *dev = ring->dev; |
0504cffc AS |
1298 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); |
1299 | ||
9b01435d AS |
1300 | /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */ |
1301 | if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_B0)) || | |
1302 | (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0))) { | |
1303 | wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); | |
1304 | wa_ctx_emit(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0); | |
1305 | wa_ctx_emit(batch, index, | |
1306 | _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING)); | |
1307 | wa_ctx_emit(batch, index, MI_NOOP); | |
1308 | } | |
1309 | ||
0907c8f7 AS |
1310 | /* WaDisableCtxRestoreArbitration:skl,bxt */ |
1311 | if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_D0)) || | |
1312 | (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0))) | |
1313 | wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE); | |
1314 | ||
0504cffc AS |
1315 | wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END); |
1316 | ||
1317 | return wa_ctx_end(wa_ctx, *offset = index, 1); | |
1318 | } | |
1319 | ||
17ee950d AS |
1320 | static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *ring, u32 size) |
1321 | { | |
1322 | int ret; | |
1323 | ||
1324 | ring->wa_ctx.obj = i915_gem_alloc_object(ring->dev, PAGE_ALIGN(size)); | |
1325 | if (!ring->wa_ctx.obj) { | |
1326 | DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n"); | |
1327 | return -ENOMEM; | |
1328 | } | |
1329 | ||
1330 | ret = i915_gem_obj_ggtt_pin(ring->wa_ctx.obj, PAGE_SIZE, 0); | |
1331 | if (ret) { | |
1332 | DRM_DEBUG_DRIVER("pin LRC WA ctx backing obj failed: %d\n", | |
1333 | ret); | |
1334 | drm_gem_object_unreference(&ring->wa_ctx.obj->base); | |
1335 | return ret; | |
1336 | } | |
1337 | ||
1338 | return 0; | |
1339 | } | |
1340 | ||
1341 | static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs *ring) | |
1342 | { | |
1343 | if (ring->wa_ctx.obj) { | |
1344 | i915_gem_object_ggtt_unpin(ring->wa_ctx.obj); | |
1345 | drm_gem_object_unreference(&ring->wa_ctx.obj->base); | |
1346 | ring->wa_ctx.obj = NULL; | |
1347 | } | |
1348 | } | |
1349 | ||
1350 | static int intel_init_workaround_bb(struct intel_engine_cs *ring) | |
1351 | { | |
1352 | int ret; | |
1353 | uint32_t *batch; | |
1354 | uint32_t offset; | |
1355 | struct page *page; | |
1356 | struct i915_ctx_workarounds *wa_ctx = &ring->wa_ctx; | |
1357 | ||
1358 | WARN_ON(ring->id != RCS); | |
1359 | ||
5e60d790 | 1360 | /* update this when WA for higher Gen are added */ |
0504cffc AS |
1361 | if (INTEL_INFO(ring->dev)->gen > 9) { |
1362 | DRM_ERROR("WA batch buffer is not initialized for Gen%d\n", | |
1363 | INTEL_INFO(ring->dev)->gen); | |
5e60d790 | 1364 | return 0; |
0504cffc | 1365 | } |
5e60d790 | 1366 | |
c4db7599 AS |
1367 | /* some WA perform writes to scratch page, ensure it is valid */ |
1368 | if (ring->scratch.obj == NULL) { | |
1369 | DRM_ERROR("scratch page not allocated for %s\n", ring->name); | |
1370 | return -EINVAL; | |
1371 | } | |
1372 | ||
17ee950d AS |
1373 | ret = lrc_setup_wa_ctx_obj(ring, PAGE_SIZE); |
1374 | if (ret) { | |
1375 | DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret); | |
1376 | return ret; | |
1377 | } | |
1378 | ||
1379 | page = i915_gem_object_get_page(wa_ctx->obj, 0); | |
1380 | batch = kmap_atomic(page); | |
1381 | offset = 0; | |
1382 | ||
1383 | if (INTEL_INFO(ring->dev)->gen == 8) { | |
1384 | ret = gen8_init_indirectctx_bb(ring, | |
1385 | &wa_ctx->indirect_ctx, | |
1386 | batch, | |
1387 | &offset); | |
1388 | if (ret) | |
1389 | goto out; | |
1390 | ||
1391 | ret = gen8_init_perctx_bb(ring, | |
1392 | &wa_ctx->per_ctx, | |
1393 | batch, | |
1394 | &offset); | |
1395 | if (ret) | |
1396 | goto out; | |
0504cffc AS |
1397 | } else if (INTEL_INFO(ring->dev)->gen == 9) { |
1398 | ret = gen9_init_indirectctx_bb(ring, | |
1399 | &wa_ctx->indirect_ctx, | |
1400 | batch, | |
1401 | &offset); | |
1402 | if (ret) | |
1403 | goto out; | |
1404 | ||
1405 | ret = gen9_init_perctx_bb(ring, | |
1406 | &wa_ctx->per_ctx, | |
1407 | batch, | |
1408 | &offset); | |
1409 | if (ret) | |
1410 | goto out; | |
17ee950d AS |
1411 | } |
1412 | ||
1413 | out: | |
1414 | kunmap_atomic(batch); | |
1415 | if (ret) | |
1416 | lrc_destroy_wa_ctx_obj(ring); | |
1417 | ||
1418 | return ret; | |
1419 | } | |
1420 | ||
9b1136d5 OM |
1421 | static int gen8_init_common_ring(struct intel_engine_cs *ring) |
1422 | { | |
1423 | struct drm_device *dev = ring->dev; | |
1424 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1425 | ||
73d477f6 OM |
1426 | I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask)); |
1427 | I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff); | |
1428 | ||
2e5356da AS |
1429 | if (ring->status_page.obj) { |
1430 | I915_WRITE(RING_HWS_PGA(ring->mmio_base), | |
1431 | (u32)ring->status_page.gfx_addr); | |
1432 | POSTING_READ(RING_HWS_PGA(ring->mmio_base)); | |
1433 | } | |
1434 | ||
9b1136d5 OM |
1435 | I915_WRITE(RING_MODE_GEN7(ring), |
1436 | _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) | | |
1437 | _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)); | |
1438 | POSTING_READ(RING_MODE_GEN7(ring)); | |
c0a03a2e | 1439 | ring->next_context_status_buffer = 0; |
9b1136d5 OM |
1440 | DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring->name); |
1441 | ||
1442 | memset(&ring->hangcheck, 0, sizeof(ring->hangcheck)); | |
1443 | ||
1444 | return 0; | |
1445 | } | |
1446 | ||
1447 | static int gen8_init_render_ring(struct intel_engine_cs *ring) | |
1448 | { | |
1449 | struct drm_device *dev = ring->dev; | |
1450 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1451 | int ret; | |
1452 | ||
1453 | ret = gen8_init_common_ring(ring); | |
1454 | if (ret) | |
1455 | return ret; | |
1456 | ||
1457 | /* We need to disable the AsyncFlip performance optimisations in order | |
1458 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
1459 | * programmed to '1' on all products. | |
1460 | * | |
1461 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv | |
1462 | */ | |
1463 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); | |
1464 | ||
9b1136d5 OM |
1465 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
1466 | ||
771b9a53 | 1467 | return init_workarounds_ring(ring); |
9b1136d5 OM |
1468 | } |
1469 | ||
82ef822e DL |
1470 | static int gen9_init_render_ring(struct intel_engine_cs *ring) |
1471 | { | |
1472 | int ret; | |
1473 | ||
1474 | ret = gen8_init_common_ring(ring); | |
1475 | if (ret) | |
1476 | return ret; | |
1477 | ||
1478 | return init_workarounds_ring(ring); | |
1479 | } | |
1480 | ||
7a01a0a2 MT |
1481 | static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req) |
1482 | { | |
1483 | struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt; | |
1484 | struct intel_engine_cs *ring = req->ring; | |
1485 | struct intel_ringbuffer *ringbuf = req->ringbuf; | |
1486 | const int num_lri_cmds = GEN8_LEGACY_PDPES * 2; | |
1487 | int i, ret; | |
1488 | ||
1489 | ret = intel_logical_ring_begin(req, num_lri_cmds * 2 + 2); | |
1490 | if (ret) | |
1491 | return ret; | |
1492 | ||
1493 | intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(num_lri_cmds)); | |
1494 | for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) { | |
1495 | const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i); | |
1496 | ||
1497 | intel_logical_ring_emit(ringbuf, GEN8_RING_PDP_UDW(ring, i)); | |
1498 | intel_logical_ring_emit(ringbuf, upper_32_bits(pd_daddr)); | |
1499 | intel_logical_ring_emit(ringbuf, GEN8_RING_PDP_LDW(ring, i)); | |
1500 | intel_logical_ring_emit(ringbuf, lower_32_bits(pd_daddr)); | |
1501 | } | |
1502 | ||
1503 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
1504 | intel_logical_ring_advance(ringbuf); | |
1505 | ||
1506 | return 0; | |
1507 | } | |
1508 | ||
be795fc1 | 1509 | static int gen8_emit_bb_start(struct drm_i915_gem_request *req, |
8e004efc | 1510 | u64 offset, unsigned dispatch_flags) |
15648585 | 1511 | { |
be795fc1 | 1512 | struct intel_ringbuffer *ringbuf = req->ringbuf; |
8e004efc | 1513 | bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE); |
15648585 OM |
1514 | int ret; |
1515 | ||
7a01a0a2 MT |
1516 | /* Don't rely in hw updating PDPs, specially in lite-restore. |
1517 | * Ideally, we should set Force PD Restore in ctx descriptor, | |
1518 | * but we can't. Force Restore would be a second option, but | |
1519 | * it is unsafe in case of lite-restore (because the ctx is | |
1520 | * not idle). */ | |
1521 | if (req->ctx->ppgtt && | |
1522 | (intel_ring_flag(req->ring) & req->ctx->ppgtt->pd_dirty_rings)) { | |
1523 | ret = intel_logical_ring_emit_pdps(req); | |
1524 | if (ret) | |
1525 | return ret; | |
1526 | ||
1527 | req->ctx->ppgtt->pd_dirty_rings &= ~intel_ring_flag(req->ring); | |
1528 | } | |
1529 | ||
4d616a29 | 1530 | ret = intel_logical_ring_begin(req, 4); |
15648585 OM |
1531 | if (ret) |
1532 | return ret; | |
1533 | ||
1534 | /* FIXME(BDW): Address space and security selectors. */ | |
6922528a AJ |
1535 | intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 | |
1536 | (ppgtt<<8) | | |
1537 | (dispatch_flags & I915_DISPATCH_RS ? | |
1538 | MI_BATCH_RESOURCE_STREAMER : 0)); | |
15648585 OM |
1539 | intel_logical_ring_emit(ringbuf, lower_32_bits(offset)); |
1540 | intel_logical_ring_emit(ringbuf, upper_32_bits(offset)); | |
1541 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
1542 | intel_logical_ring_advance(ringbuf); | |
1543 | ||
1544 | return 0; | |
1545 | } | |
1546 | ||
73d477f6 OM |
1547 | static bool gen8_logical_ring_get_irq(struct intel_engine_cs *ring) |
1548 | { | |
1549 | struct drm_device *dev = ring->dev; | |
1550 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1551 | unsigned long flags; | |
1552 | ||
7cd512f1 | 1553 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
73d477f6 OM |
1554 | return false; |
1555 | ||
1556 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1557 | if (ring->irq_refcount++ == 0) { | |
1558 | I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask)); | |
1559 | POSTING_READ(RING_IMR(ring->mmio_base)); | |
1560 | } | |
1561 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1562 | ||
1563 | return true; | |
1564 | } | |
1565 | ||
1566 | static void gen8_logical_ring_put_irq(struct intel_engine_cs *ring) | |
1567 | { | |
1568 | struct drm_device *dev = ring->dev; | |
1569 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1570 | unsigned long flags; | |
1571 | ||
1572 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1573 | if (--ring->irq_refcount == 0) { | |
1574 | I915_WRITE_IMR(ring, ~ring->irq_keep_mask); | |
1575 | POSTING_READ(RING_IMR(ring->mmio_base)); | |
1576 | } | |
1577 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1578 | } | |
1579 | ||
7deb4d39 | 1580 | static int gen8_emit_flush(struct drm_i915_gem_request *request, |
4712274c OM |
1581 | u32 invalidate_domains, |
1582 | u32 unused) | |
1583 | { | |
7deb4d39 | 1584 | struct intel_ringbuffer *ringbuf = request->ringbuf; |
4712274c OM |
1585 | struct intel_engine_cs *ring = ringbuf->ring; |
1586 | struct drm_device *dev = ring->dev; | |
1587 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1588 | uint32_t cmd; | |
1589 | int ret; | |
1590 | ||
4d616a29 | 1591 | ret = intel_logical_ring_begin(request, 4); |
4712274c OM |
1592 | if (ret) |
1593 | return ret; | |
1594 | ||
1595 | cmd = MI_FLUSH_DW + 1; | |
1596 | ||
f0a1fb10 CW |
1597 | /* We always require a command barrier so that subsequent |
1598 | * commands, such as breadcrumb interrupts, are strictly ordered | |
1599 | * wrt the contents of the write cache being flushed to memory | |
1600 | * (and thus being coherent from the CPU). | |
1601 | */ | |
1602 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
1603 | ||
1604 | if (invalidate_domains & I915_GEM_GPU_DOMAINS) { | |
1605 | cmd |= MI_INVALIDATE_TLB; | |
1606 | if (ring == &dev_priv->ring[VCS]) | |
1607 | cmd |= MI_INVALIDATE_BSD; | |
4712274c OM |
1608 | } |
1609 | ||
1610 | intel_logical_ring_emit(ringbuf, cmd); | |
1611 | intel_logical_ring_emit(ringbuf, | |
1612 | I915_GEM_HWS_SCRATCH_ADDR | | |
1613 | MI_FLUSH_DW_USE_GTT); | |
1614 | intel_logical_ring_emit(ringbuf, 0); /* upper addr */ | |
1615 | intel_logical_ring_emit(ringbuf, 0); /* value */ | |
1616 | intel_logical_ring_advance(ringbuf); | |
1617 | ||
1618 | return 0; | |
1619 | } | |
1620 | ||
7deb4d39 | 1621 | static int gen8_emit_flush_render(struct drm_i915_gem_request *request, |
4712274c OM |
1622 | u32 invalidate_domains, |
1623 | u32 flush_domains) | |
1624 | { | |
7deb4d39 | 1625 | struct intel_ringbuffer *ringbuf = request->ringbuf; |
4712274c OM |
1626 | struct intel_engine_cs *ring = ringbuf->ring; |
1627 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; | |
9647ff36 | 1628 | bool vf_flush_wa; |
4712274c OM |
1629 | u32 flags = 0; |
1630 | int ret; | |
1631 | ||
1632 | flags |= PIPE_CONTROL_CS_STALL; | |
1633 | ||
1634 | if (flush_domains) { | |
1635 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
1636 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
1637 | } | |
1638 | ||
1639 | if (invalidate_domains) { | |
1640 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
1641 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
1642 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
1643 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
1644 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
1645 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
1646 | flags |= PIPE_CONTROL_QW_WRITE; | |
1647 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
1648 | } | |
1649 | ||
9647ff36 ID |
1650 | /* |
1651 | * On GEN9+ Before VF_CACHE_INVALIDATE we need to emit a NULL pipe | |
1652 | * control. | |
1653 | */ | |
1654 | vf_flush_wa = INTEL_INFO(ring->dev)->gen >= 9 && | |
1655 | flags & PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
1656 | ||
4d616a29 | 1657 | ret = intel_logical_ring_begin(request, vf_flush_wa ? 12 : 6); |
4712274c OM |
1658 | if (ret) |
1659 | return ret; | |
1660 | ||
9647ff36 ID |
1661 | if (vf_flush_wa) { |
1662 | intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6)); | |
1663 | intel_logical_ring_emit(ringbuf, 0); | |
1664 | intel_logical_ring_emit(ringbuf, 0); | |
1665 | intel_logical_ring_emit(ringbuf, 0); | |
1666 | intel_logical_ring_emit(ringbuf, 0); | |
1667 | intel_logical_ring_emit(ringbuf, 0); | |
1668 | } | |
1669 | ||
4712274c OM |
1670 | intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6)); |
1671 | intel_logical_ring_emit(ringbuf, flags); | |
1672 | intel_logical_ring_emit(ringbuf, scratch_addr); | |
1673 | intel_logical_ring_emit(ringbuf, 0); | |
1674 | intel_logical_ring_emit(ringbuf, 0); | |
1675 | intel_logical_ring_emit(ringbuf, 0); | |
1676 | intel_logical_ring_advance(ringbuf); | |
1677 | ||
1678 | return 0; | |
1679 | } | |
1680 | ||
e94e37ad OM |
1681 | static u32 gen8_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
1682 | { | |
1683 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); | |
1684 | } | |
1685 | ||
1686 | static void gen8_set_seqno(struct intel_engine_cs *ring, u32 seqno) | |
1687 | { | |
1688 | intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno); | |
1689 | } | |
1690 | ||
c4e76638 | 1691 | static int gen8_emit_request(struct drm_i915_gem_request *request) |
4da46e1e | 1692 | { |
c4e76638 | 1693 | struct intel_ringbuffer *ringbuf = request->ringbuf; |
4da46e1e OM |
1694 | struct intel_engine_cs *ring = ringbuf->ring; |
1695 | u32 cmd; | |
1696 | int ret; | |
1697 | ||
53292cdb MT |
1698 | /* |
1699 | * Reserve space for 2 NOOPs at the end of each request to be | |
1700 | * used as a workaround for not being allowed to do lite | |
1701 | * restore with HEAD==TAIL (WaIdleLiteRestore). | |
1702 | */ | |
4d616a29 | 1703 | ret = intel_logical_ring_begin(request, 8); |
4da46e1e OM |
1704 | if (ret) |
1705 | return ret; | |
1706 | ||
8edfbb8b | 1707 | cmd = MI_STORE_DWORD_IMM_GEN4; |
4da46e1e OM |
1708 | cmd |= MI_GLOBAL_GTT; |
1709 | ||
1710 | intel_logical_ring_emit(ringbuf, cmd); | |
1711 | intel_logical_ring_emit(ringbuf, | |
1712 | (ring->status_page.gfx_addr + | |
1713 | (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT))); | |
1714 | intel_logical_ring_emit(ringbuf, 0); | |
c4e76638 | 1715 | intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request)); |
4da46e1e OM |
1716 | intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT); |
1717 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
ae70797d | 1718 | intel_logical_ring_advance_and_submit(request); |
4da46e1e | 1719 | |
53292cdb MT |
1720 | /* |
1721 | * Here we add two extra NOOPs as padding to avoid | |
1722 | * lite restore of a context with HEAD==TAIL. | |
1723 | */ | |
1724 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
1725 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
1726 | intel_logical_ring_advance(ringbuf); | |
1727 | ||
4da46e1e OM |
1728 | return 0; |
1729 | } | |
1730 | ||
be01363f | 1731 | static int intel_lr_context_render_state_init(struct drm_i915_gem_request *req) |
cef437ad | 1732 | { |
cef437ad | 1733 | struct render_state so; |
cef437ad DL |
1734 | int ret; |
1735 | ||
be01363f | 1736 | ret = i915_gem_render_state_prepare(req->ring, &so); |
cef437ad DL |
1737 | if (ret) |
1738 | return ret; | |
1739 | ||
1740 | if (so.rodata == NULL) | |
1741 | return 0; | |
1742 | ||
be795fc1 | 1743 | ret = req->ring->emit_bb_start(req, so.ggtt_offset, |
be01363f | 1744 | I915_DISPATCH_SECURE); |
cef437ad DL |
1745 | if (ret) |
1746 | goto out; | |
1747 | ||
84e81020 AS |
1748 | ret = req->ring->emit_bb_start(req, |
1749 | (so.ggtt_offset + so.aux_batch_offset), | |
1750 | I915_DISPATCH_SECURE); | |
1751 | if (ret) | |
1752 | goto out; | |
1753 | ||
b2af0376 | 1754 | i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), req); |
cef437ad | 1755 | |
cef437ad DL |
1756 | out: |
1757 | i915_gem_render_state_fini(&so); | |
1758 | return ret; | |
1759 | } | |
1760 | ||
8753181e | 1761 | static int gen8_init_rcs_context(struct drm_i915_gem_request *req) |
e7778be1 TD |
1762 | { |
1763 | int ret; | |
1764 | ||
e2be4faf | 1765 | ret = intel_logical_ring_workarounds_emit(req); |
e7778be1 TD |
1766 | if (ret) |
1767 | return ret; | |
1768 | ||
3bbaba0c PA |
1769 | ret = intel_rcs_context_init_mocs(req); |
1770 | /* | |
1771 | * Failing to program the MOCS is non-fatal.The system will not | |
1772 | * run at peak performance. So generate an error and carry on. | |
1773 | */ | |
1774 | if (ret) | |
1775 | DRM_ERROR("MOCS failed to program: expect performance issues.\n"); | |
1776 | ||
be01363f | 1777 | return intel_lr_context_render_state_init(req); |
e7778be1 TD |
1778 | } |
1779 | ||
73e4d07f OM |
1780 | /** |
1781 | * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer | |
1782 | * | |
1783 | * @ring: Engine Command Streamer. | |
1784 | * | |
1785 | */ | |
454afebd OM |
1786 | void intel_logical_ring_cleanup(struct intel_engine_cs *ring) |
1787 | { | |
6402c330 | 1788 | struct drm_i915_private *dev_priv; |
9832b9da | 1789 | |
48d82387 OM |
1790 | if (!intel_ring_initialized(ring)) |
1791 | return; | |
1792 | ||
6402c330 JH |
1793 | dev_priv = ring->dev->dev_private; |
1794 | ||
9832b9da OM |
1795 | intel_logical_ring_stop(ring); |
1796 | WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0); | |
48d82387 OM |
1797 | |
1798 | if (ring->cleanup) | |
1799 | ring->cleanup(ring); | |
1800 | ||
1801 | i915_cmd_parser_fini_ring(ring); | |
06fbca71 | 1802 | i915_gem_batch_pool_fini(&ring->batch_pool); |
48d82387 OM |
1803 | |
1804 | if (ring->status_page.obj) { | |
1805 | kunmap(sg_page(ring->status_page.obj->pages->sgl)); | |
1806 | ring->status_page.obj = NULL; | |
1807 | } | |
17ee950d AS |
1808 | |
1809 | lrc_destroy_wa_ctx_obj(ring); | |
454afebd OM |
1810 | } |
1811 | ||
1812 | static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *ring) | |
1813 | { | |
48d82387 | 1814 | int ret; |
48d82387 OM |
1815 | |
1816 | /* Intentionally left blank. */ | |
1817 | ring->buffer = NULL; | |
1818 | ||
1819 | ring->dev = dev; | |
1820 | INIT_LIST_HEAD(&ring->active_list); | |
1821 | INIT_LIST_HEAD(&ring->request_list); | |
06fbca71 | 1822 | i915_gem_batch_pool_init(dev, &ring->batch_pool); |
48d82387 OM |
1823 | init_waitqueue_head(&ring->irq_queue); |
1824 | ||
acdd884a | 1825 | INIT_LIST_HEAD(&ring->execlist_queue); |
c86ee3a9 | 1826 | INIT_LIST_HEAD(&ring->execlist_retired_req_list); |
acdd884a MT |
1827 | spin_lock_init(&ring->execlist_lock); |
1828 | ||
48d82387 OM |
1829 | ret = i915_cmd_parser_init_ring(ring); |
1830 | if (ret) | |
1831 | return ret; | |
1832 | ||
564ddb2f OM |
1833 | ret = intel_lr_context_deferred_create(ring->default_context, ring); |
1834 | ||
1835 | return ret; | |
454afebd OM |
1836 | } |
1837 | ||
1838 | static int logical_render_ring_init(struct drm_device *dev) | |
1839 | { | |
1840 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1841 | struct intel_engine_cs *ring = &dev_priv->ring[RCS]; | |
99be1dfe | 1842 | int ret; |
454afebd OM |
1843 | |
1844 | ring->name = "render ring"; | |
1845 | ring->id = RCS; | |
1846 | ring->mmio_base = RENDER_RING_BASE; | |
1847 | ring->irq_enable_mask = | |
1848 | GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT; | |
73d477f6 OM |
1849 | ring->irq_keep_mask = |
1850 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT; | |
1851 | if (HAS_L3_DPF(dev)) | |
1852 | ring->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT; | |
454afebd | 1853 | |
82ef822e DL |
1854 | if (INTEL_INFO(dev)->gen >= 9) |
1855 | ring->init_hw = gen9_init_render_ring; | |
1856 | else | |
1857 | ring->init_hw = gen8_init_render_ring; | |
e7778be1 | 1858 | ring->init_context = gen8_init_rcs_context; |
9b1136d5 | 1859 | ring->cleanup = intel_fini_pipe_control; |
e94e37ad OM |
1860 | ring->get_seqno = gen8_get_seqno; |
1861 | ring->set_seqno = gen8_set_seqno; | |
4da46e1e | 1862 | ring->emit_request = gen8_emit_request; |
4712274c | 1863 | ring->emit_flush = gen8_emit_flush_render; |
73d477f6 OM |
1864 | ring->irq_get = gen8_logical_ring_get_irq; |
1865 | ring->irq_put = gen8_logical_ring_put_irq; | |
15648585 | 1866 | ring->emit_bb_start = gen8_emit_bb_start; |
9b1136d5 | 1867 | |
99be1dfe | 1868 | ring->dev = dev; |
c4db7599 AS |
1869 | |
1870 | ret = intel_init_pipe_control(ring); | |
99be1dfe DV |
1871 | if (ret) |
1872 | return ret; | |
1873 | ||
17ee950d AS |
1874 | ret = intel_init_workaround_bb(ring); |
1875 | if (ret) { | |
1876 | /* | |
1877 | * We continue even if we fail to initialize WA batch | |
1878 | * because we only expect rare glitches but nothing | |
1879 | * critical to prevent us from using GPU | |
1880 | */ | |
1881 | DRM_ERROR("WA batch buffer initialization failed: %d\n", | |
1882 | ret); | |
1883 | } | |
1884 | ||
c4db7599 AS |
1885 | ret = logical_ring_init(dev, ring); |
1886 | if (ret) { | |
17ee950d | 1887 | lrc_destroy_wa_ctx_obj(ring); |
c4db7599 | 1888 | } |
17ee950d AS |
1889 | |
1890 | return ret; | |
454afebd OM |
1891 | } |
1892 | ||
1893 | static int logical_bsd_ring_init(struct drm_device *dev) | |
1894 | { | |
1895 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1896 | struct intel_engine_cs *ring = &dev_priv->ring[VCS]; | |
1897 | ||
1898 | ring->name = "bsd ring"; | |
1899 | ring->id = VCS; | |
1900 | ring->mmio_base = GEN6_BSD_RING_BASE; | |
1901 | ring->irq_enable_mask = | |
1902 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; | |
73d477f6 OM |
1903 | ring->irq_keep_mask = |
1904 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; | |
454afebd | 1905 | |
ecfe00d8 | 1906 | ring->init_hw = gen8_init_common_ring; |
e94e37ad OM |
1907 | ring->get_seqno = gen8_get_seqno; |
1908 | ring->set_seqno = gen8_set_seqno; | |
4da46e1e | 1909 | ring->emit_request = gen8_emit_request; |
4712274c | 1910 | ring->emit_flush = gen8_emit_flush; |
73d477f6 OM |
1911 | ring->irq_get = gen8_logical_ring_get_irq; |
1912 | ring->irq_put = gen8_logical_ring_put_irq; | |
15648585 | 1913 | ring->emit_bb_start = gen8_emit_bb_start; |
9b1136d5 | 1914 | |
454afebd OM |
1915 | return logical_ring_init(dev, ring); |
1916 | } | |
1917 | ||
1918 | static int logical_bsd2_ring_init(struct drm_device *dev) | |
1919 | { | |
1920 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1921 | struct intel_engine_cs *ring = &dev_priv->ring[VCS2]; | |
1922 | ||
1923 | ring->name = "bds2 ring"; | |
1924 | ring->id = VCS2; | |
1925 | ring->mmio_base = GEN8_BSD2_RING_BASE; | |
1926 | ring->irq_enable_mask = | |
1927 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; | |
73d477f6 OM |
1928 | ring->irq_keep_mask = |
1929 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; | |
454afebd | 1930 | |
ecfe00d8 | 1931 | ring->init_hw = gen8_init_common_ring; |
e94e37ad OM |
1932 | ring->get_seqno = gen8_get_seqno; |
1933 | ring->set_seqno = gen8_set_seqno; | |
4da46e1e | 1934 | ring->emit_request = gen8_emit_request; |
4712274c | 1935 | ring->emit_flush = gen8_emit_flush; |
73d477f6 OM |
1936 | ring->irq_get = gen8_logical_ring_get_irq; |
1937 | ring->irq_put = gen8_logical_ring_put_irq; | |
15648585 | 1938 | ring->emit_bb_start = gen8_emit_bb_start; |
9b1136d5 | 1939 | |
454afebd OM |
1940 | return logical_ring_init(dev, ring); |
1941 | } | |
1942 | ||
1943 | static int logical_blt_ring_init(struct drm_device *dev) | |
1944 | { | |
1945 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1946 | struct intel_engine_cs *ring = &dev_priv->ring[BCS]; | |
1947 | ||
1948 | ring->name = "blitter ring"; | |
1949 | ring->id = BCS; | |
1950 | ring->mmio_base = BLT_RING_BASE; | |
1951 | ring->irq_enable_mask = | |
1952 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; | |
73d477f6 OM |
1953 | ring->irq_keep_mask = |
1954 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT; | |
454afebd | 1955 | |
ecfe00d8 | 1956 | ring->init_hw = gen8_init_common_ring; |
e94e37ad OM |
1957 | ring->get_seqno = gen8_get_seqno; |
1958 | ring->set_seqno = gen8_set_seqno; | |
4da46e1e | 1959 | ring->emit_request = gen8_emit_request; |
4712274c | 1960 | ring->emit_flush = gen8_emit_flush; |
73d477f6 OM |
1961 | ring->irq_get = gen8_logical_ring_get_irq; |
1962 | ring->irq_put = gen8_logical_ring_put_irq; | |
15648585 | 1963 | ring->emit_bb_start = gen8_emit_bb_start; |
9b1136d5 | 1964 | |
454afebd OM |
1965 | return logical_ring_init(dev, ring); |
1966 | } | |
1967 | ||
1968 | static int logical_vebox_ring_init(struct drm_device *dev) | |
1969 | { | |
1970 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1971 | struct intel_engine_cs *ring = &dev_priv->ring[VECS]; | |
1972 | ||
1973 | ring->name = "video enhancement ring"; | |
1974 | ring->id = VECS; | |
1975 | ring->mmio_base = VEBOX_RING_BASE; | |
1976 | ring->irq_enable_mask = | |
1977 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; | |
73d477f6 OM |
1978 | ring->irq_keep_mask = |
1979 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT; | |
454afebd | 1980 | |
ecfe00d8 | 1981 | ring->init_hw = gen8_init_common_ring; |
e94e37ad OM |
1982 | ring->get_seqno = gen8_get_seqno; |
1983 | ring->set_seqno = gen8_set_seqno; | |
4da46e1e | 1984 | ring->emit_request = gen8_emit_request; |
4712274c | 1985 | ring->emit_flush = gen8_emit_flush; |
73d477f6 OM |
1986 | ring->irq_get = gen8_logical_ring_get_irq; |
1987 | ring->irq_put = gen8_logical_ring_put_irq; | |
15648585 | 1988 | ring->emit_bb_start = gen8_emit_bb_start; |
9b1136d5 | 1989 | |
454afebd OM |
1990 | return logical_ring_init(dev, ring); |
1991 | } | |
1992 | ||
73e4d07f OM |
1993 | /** |
1994 | * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers | |
1995 | * @dev: DRM device. | |
1996 | * | |
1997 | * This function inits the engines for an Execlists submission style (the equivalent in the | |
1998 | * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for | |
1999 | * those engines that are present in the hardware. | |
2000 | * | |
2001 | * Return: non-zero if the initialization failed. | |
2002 | */ | |
454afebd OM |
2003 | int intel_logical_rings_init(struct drm_device *dev) |
2004 | { | |
2005 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2006 | int ret; | |
2007 | ||
2008 | ret = logical_render_ring_init(dev); | |
2009 | if (ret) | |
2010 | return ret; | |
2011 | ||
2012 | if (HAS_BSD(dev)) { | |
2013 | ret = logical_bsd_ring_init(dev); | |
2014 | if (ret) | |
2015 | goto cleanup_render_ring; | |
2016 | } | |
2017 | ||
2018 | if (HAS_BLT(dev)) { | |
2019 | ret = logical_blt_ring_init(dev); | |
2020 | if (ret) | |
2021 | goto cleanup_bsd_ring; | |
2022 | } | |
2023 | ||
2024 | if (HAS_VEBOX(dev)) { | |
2025 | ret = logical_vebox_ring_init(dev); | |
2026 | if (ret) | |
2027 | goto cleanup_blt_ring; | |
2028 | } | |
2029 | ||
2030 | if (HAS_BSD2(dev)) { | |
2031 | ret = logical_bsd2_ring_init(dev); | |
2032 | if (ret) | |
2033 | goto cleanup_vebox_ring; | |
2034 | } | |
2035 | ||
2036 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); | |
2037 | if (ret) | |
2038 | goto cleanup_bsd2_ring; | |
2039 | ||
2040 | return 0; | |
2041 | ||
2042 | cleanup_bsd2_ring: | |
2043 | intel_logical_ring_cleanup(&dev_priv->ring[VCS2]); | |
2044 | cleanup_vebox_ring: | |
2045 | intel_logical_ring_cleanup(&dev_priv->ring[VECS]); | |
2046 | cleanup_blt_ring: | |
2047 | intel_logical_ring_cleanup(&dev_priv->ring[BCS]); | |
2048 | cleanup_bsd_ring: | |
2049 | intel_logical_ring_cleanup(&dev_priv->ring[VCS]); | |
2050 | cleanup_render_ring: | |
2051 | intel_logical_ring_cleanup(&dev_priv->ring[RCS]); | |
2052 | ||
2053 | return ret; | |
2054 | } | |
2055 | ||
0cea6502 JM |
2056 | static u32 |
2057 | make_rpcs(struct drm_device *dev) | |
2058 | { | |
2059 | u32 rpcs = 0; | |
2060 | ||
2061 | /* | |
2062 | * No explicit RPCS request is needed to ensure full | |
2063 | * slice/subslice/EU enablement prior to Gen9. | |
2064 | */ | |
2065 | if (INTEL_INFO(dev)->gen < 9) | |
2066 | return 0; | |
2067 | ||
2068 | /* | |
2069 | * Starting in Gen9, render power gating can leave | |
2070 | * slice/subslice/EU in a partially enabled state. We | |
2071 | * must make an explicit request through RPCS for full | |
2072 | * enablement. | |
2073 | */ | |
2074 | if (INTEL_INFO(dev)->has_slice_pg) { | |
2075 | rpcs |= GEN8_RPCS_S_CNT_ENABLE; | |
2076 | rpcs |= INTEL_INFO(dev)->slice_total << | |
2077 | GEN8_RPCS_S_CNT_SHIFT; | |
2078 | rpcs |= GEN8_RPCS_ENABLE; | |
2079 | } | |
2080 | ||
2081 | if (INTEL_INFO(dev)->has_subslice_pg) { | |
2082 | rpcs |= GEN8_RPCS_SS_CNT_ENABLE; | |
2083 | rpcs |= INTEL_INFO(dev)->subslice_per_slice << | |
2084 | GEN8_RPCS_SS_CNT_SHIFT; | |
2085 | rpcs |= GEN8_RPCS_ENABLE; | |
2086 | } | |
2087 | ||
2088 | if (INTEL_INFO(dev)->has_eu_pg) { | |
2089 | rpcs |= INTEL_INFO(dev)->eu_per_subslice << | |
2090 | GEN8_RPCS_EU_MIN_SHIFT; | |
2091 | rpcs |= INTEL_INFO(dev)->eu_per_subslice << | |
2092 | GEN8_RPCS_EU_MAX_SHIFT; | |
2093 | rpcs |= GEN8_RPCS_ENABLE; | |
2094 | } | |
2095 | ||
2096 | return rpcs; | |
2097 | } | |
2098 | ||
8670d6f9 OM |
2099 | static int |
2100 | populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj, | |
2101 | struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf) | |
2102 | { | |
2d965536 TD |
2103 | struct drm_device *dev = ring->dev; |
2104 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ae6c4806 | 2105 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
8670d6f9 OM |
2106 | struct page *page; |
2107 | uint32_t *reg_state; | |
2108 | int ret; | |
2109 | ||
2d965536 TD |
2110 | if (!ppgtt) |
2111 | ppgtt = dev_priv->mm.aliasing_ppgtt; | |
2112 | ||
8670d6f9 OM |
2113 | ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true); |
2114 | if (ret) { | |
2115 | DRM_DEBUG_DRIVER("Could not set to CPU domain\n"); | |
2116 | return ret; | |
2117 | } | |
2118 | ||
2119 | ret = i915_gem_object_get_pages(ctx_obj); | |
2120 | if (ret) { | |
2121 | DRM_DEBUG_DRIVER("Could not get object pages\n"); | |
2122 | return ret; | |
2123 | } | |
2124 | ||
2125 | i915_gem_object_pin_pages(ctx_obj); | |
2126 | ||
2127 | /* The second page of the context object contains some fields which must | |
2128 | * be set up prior to the first execution. */ | |
2129 | page = i915_gem_object_get_page(ctx_obj, 1); | |
2130 | reg_state = kmap_atomic(page); | |
2131 | ||
2132 | /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM | |
2133 | * commands followed by (reg, value) pairs. The values we are setting here are | |
2134 | * only for the first context restore: on a subsequent save, the GPU will | |
2135 | * recreate this batchbuffer with new values (including all the missing | |
2136 | * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */ | |
2137 | if (ring->id == RCS) | |
2138 | reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(14); | |
2139 | else | |
2140 | reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(11); | |
2141 | reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED; | |
2142 | reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring); | |
2143 | reg_state[CTX_CONTEXT_CONTROL+1] = | |
5baa22c5 | 2144 | _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH | |
6922528a AJ |
2145 | CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT | |
2146 | CTX_CTRL_RS_CTX_ENABLE); | |
8670d6f9 OM |
2147 | reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base); |
2148 | reg_state[CTX_RING_HEAD+1] = 0; | |
2149 | reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base); | |
2150 | reg_state[CTX_RING_TAIL+1] = 0; | |
2151 | reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base); | |
7ba717cf TD |
2152 | /* Ring buffer start address is not known until the buffer is pinned. |
2153 | * It is written to the context image in execlists_update_context() | |
2154 | */ | |
8670d6f9 OM |
2155 | reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base); |
2156 | reg_state[CTX_RING_BUFFER_CONTROL+1] = | |
2157 | ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID; | |
2158 | reg_state[CTX_BB_HEAD_U] = ring->mmio_base + 0x168; | |
2159 | reg_state[CTX_BB_HEAD_U+1] = 0; | |
2160 | reg_state[CTX_BB_HEAD_L] = ring->mmio_base + 0x140; | |
2161 | reg_state[CTX_BB_HEAD_L+1] = 0; | |
2162 | reg_state[CTX_BB_STATE] = ring->mmio_base + 0x110; | |
2163 | reg_state[CTX_BB_STATE+1] = (1<<5); | |
2164 | reg_state[CTX_SECOND_BB_HEAD_U] = ring->mmio_base + 0x11c; | |
2165 | reg_state[CTX_SECOND_BB_HEAD_U+1] = 0; | |
2166 | reg_state[CTX_SECOND_BB_HEAD_L] = ring->mmio_base + 0x114; | |
2167 | reg_state[CTX_SECOND_BB_HEAD_L+1] = 0; | |
2168 | reg_state[CTX_SECOND_BB_STATE] = ring->mmio_base + 0x118; | |
2169 | reg_state[CTX_SECOND_BB_STATE+1] = 0; | |
2170 | if (ring->id == RCS) { | |
8670d6f9 OM |
2171 | reg_state[CTX_BB_PER_CTX_PTR] = ring->mmio_base + 0x1c0; |
2172 | reg_state[CTX_BB_PER_CTX_PTR+1] = 0; | |
2173 | reg_state[CTX_RCS_INDIRECT_CTX] = ring->mmio_base + 0x1c4; | |
2174 | reg_state[CTX_RCS_INDIRECT_CTX+1] = 0; | |
2175 | reg_state[CTX_RCS_INDIRECT_CTX_OFFSET] = ring->mmio_base + 0x1c8; | |
2176 | reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = 0; | |
17ee950d AS |
2177 | if (ring->wa_ctx.obj) { |
2178 | struct i915_ctx_workarounds *wa_ctx = &ring->wa_ctx; | |
2179 | uint32_t ggtt_offset = i915_gem_obj_ggtt_offset(wa_ctx->obj); | |
2180 | ||
2181 | reg_state[CTX_RCS_INDIRECT_CTX+1] = | |
2182 | (ggtt_offset + wa_ctx->indirect_ctx.offset * sizeof(uint32_t)) | | |
2183 | (wa_ctx->indirect_ctx.size / CACHELINE_DWORDS); | |
2184 | ||
2185 | reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = | |
2186 | CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT << 6; | |
2187 | ||
2188 | reg_state[CTX_BB_PER_CTX_PTR+1] = | |
2189 | (ggtt_offset + wa_ctx->per_ctx.offset * sizeof(uint32_t)) | | |
2190 | 0x01; | |
2191 | } | |
8670d6f9 OM |
2192 | } |
2193 | reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9); | |
2194 | reg_state[CTX_LRI_HEADER_1] |= MI_LRI_FORCE_POSTED; | |
2195 | reg_state[CTX_CTX_TIMESTAMP] = ring->mmio_base + 0x3a8; | |
2196 | reg_state[CTX_CTX_TIMESTAMP+1] = 0; | |
2197 | reg_state[CTX_PDP3_UDW] = GEN8_RING_PDP_UDW(ring, 3); | |
2198 | reg_state[CTX_PDP3_LDW] = GEN8_RING_PDP_LDW(ring, 3); | |
2199 | reg_state[CTX_PDP2_UDW] = GEN8_RING_PDP_UDW(ring, 2); | |
2200 | reg_state[CTX_PDP2_LDW] = GEN8_RING_PDP_LDW(ring, 2); | |
2201 | reg_state[CTX_PDP1_UDW] = GEN8_RING_PDP_UDW(ring, 1); | |
2202 | reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1); | |
2203 | reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0); | |
2204 | reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0); | |
d7b2633d MT |
2205 | |
2206 | /* With dynamic page allocation, PDPs may not be allocated at this point, | |
2207 | * Point the unallocated PDPs to the scratch page | |
e5815a2e MT |
2208 | */ |
2209 | ASSIGN_CTX_PDP(ppgtt, reg_state, 3); | |
2210 | ASSIGN_CTX_PDP(ppgtt, reg_state, 2); | |
2211 | ASSIGN_CTX_PDP(ppgtt, reg_state, 1); | |
2212 | ASSIGN_CTX_PDP(ppgtt, reg_state, 0); | |
8670d6f9 OM |
2213 | if (ring->id == RCS) { |
2214 | reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1); | |
0cea6502 JM |
2215 | reg_state[CTX_R_PWR_CLK_STATE] = GEN8_R_PWR_CLK_STATE; |
2216 | reg_state[CTX_R_PWR_CLK_STATE+1] = make_rpcs(dev); | |
8670d6f9 OM |
2217 | } |
2218 | ||
2219 | kunmap_atomic(reg_state); | |
2220 | ||
2221 | ctx_obj->dirty = 1; | |
2222 | set_page_dirty(page); | |
2223 | i915_gem_object_unpin_pages(ctx_obj); | |
2224 | ||
2225 | return 0; | |
2226 | } | |
2227 | ||
73e4d07f OM |
2228 | /** |
2229 | * intel_lr_context_free() - free the LRC specific bits of a context | |
2230 | * @ctx: the LR context to free. | |
2231 | * | |
2232 | * The real context freeing is done in i915_gem_context_free: this only | |
2233 | * takes care of the bits that are LRC related: the per-engine backing | |
2234 | * objects and the logical ringbuffer. | |
2235 | */ | |
ede7d42b OM |
2236 | void intel_lr_context_free(struct intel_context *ctx) |
2237 | { | |
8c857917 OM |
2238 | int i; |
2239 | ||
2240 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
2241 | struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state; | |
84c2377f | 2242 | |
8c857917 | 2243 | if (ctx_obj) { |
dcb4c12a OM |
2244 | struct intel_ringbuffer *ringbuf = |
2245 | ctx->engine[i].ringbuf; | |
2246 | struct intel_engine_cs *ring = ringbuf->ring; | |
2247 | ||
7ba717cf TD |
2248 | if (ctx == ring->default_context) { |
2249 | intel_unpin_ringbuffer_obj(ringbuf); | |
2250 | i915_gem_object_ggtt_unpin(ctx_obj); | |
2251 | } | |
a7cbedec | 2252 | WARN_ON(ctx->engine[ring->id].pin_count); |
84c2377f OM |
2253 | intel_destroy_ringbuffer_obj(ringbuf); |
2254 | kfree(ringbuf); | |
8c857917 OM |
2255 | drm_gem_object_unreference(&ctx_obj->base); |
2256 | } | |
2257 | } | |
2258 | } | |
2259 | ||
2260 | static uint32_t get_lr_context_size(struct intel_engine_cs *ring) | |
2261 | { | |
2262 | int ret = 0; | |
2263 | ||
468c6816 | 2264 | WARN_ON(INTEL_INFO(ring->dev)->gen < 8); |
8c857917 OM |
2265 | |
2266 | switch (ring->id) { | |
2267 | case RCS: | |
468c6816 MN |
2268 | if (INTEL_INFO(ring->dev)->gen >= 9) |
2269 | ret = GEN9_LR_CONTEXT_RENDER_SIZE; | |
2270 | else | |
2271 | ret = GEN8_LR_CONTEXT_RENDER_SIZE; | |
8c857917 OM |
2272 | break; |
2273 | case VCS: | |
2274 | case BCS: | |
2275 | case VECS: | |
2276 | case VCS2: | |
2277 | ret = GEN8_LR_CONTEXT_OTHER_SIZE; | |
2278 | break; | |
2279 | } | |
2280 | ||
2281 | return ret; | |
ede7d42b OM |
2282 | } |
2283 | ||
70b0ea86 | 2284 | static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring, |
1df06b75 TD |
2285 | struct drm_i915_gem_object *default_ctx_obj) |
2286 | { | |
2287 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
2288 | ||
2289 | /* The status page is offset 0 from the default context object | |
2290 | * in LRC mode. */ | |
2291 | ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(default_ctx_obj); | |
2292 | ring->status_page.page_addr = | |
2293 | kmap(sg_page(default_ctx_obj->pages->sgl)); | |
1df06b75 TD |
2294 | ring->status_page.obj = default_ctx_obj; |
2295 | ||
2296 | I915_WRITE(RING_HWS_PGA(ring->mmio_base), | |
2297 | (u32)ring->status_page.gfx_addr); | |
2298 | POSTING_READ(RING_HWS_PGA(ring->mmio_base)); | |
1df06b75 TD |
2299 | } |
2300 | ||
73e4d07f OM |
2301 | /** |
2302 | * intel_lr_context_deferred_create() - create the LRC specific bits of a context | |
2303 | * @ctx: LR context to create. | |
2304 | * @ring: engine to be used with the context. | |
2305 | * | |
2306 | * This function can be called more than once, with different engines, if we plan | |
2307 | * to use the context with them. The context backing objects and the ringbuffers | |
2308 | * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why | |
2309 | * the creation is a deferred call: it's better to make sure first that we need to use | |
2310 | * a given ring with the context. | |
2311 | * | |
32197aab | 2312 | * Return: non-zero on error. |
73e4d07f | 2313 | */ |
ede7d42b OM |
2314 | int intel_lr_context_deferred_create(struct intel_context *ctx, |
2315 | struct intel_engine_cs *ring) | |
2316 | { | |
dcb4c12a | 2317 | const bool is_global_default_ctx = (ctx == ring->default_context); |
8c857917 OM |
2318 | struct drm_device *dev = ring->dev; |
2319 | struct drm_i915_gem_object *ctx_obj; | |
2320 | uint32_t context_size; | |
84c2377f | 2321 | struct intel_ringbuffer *ringbuf; |
8c857917 OM |
2322 | int ret; |
2323 | ||
ede7d42b | 2324 | WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL); |
bfc882b4 | 2325 | WARN_ON(ctx->engine[ring->id].state); |
ede7d42b | 2326 | |
8c857917 OM |
2327 | context_size = round_up(get_lr_context_size(ring), 4096); |
2328 | ||
149c86e7 | 2329 | ctx_obj = i915_gem_alloc_object(dev, context_size); |
3126a660 DC |
2330 | if (!ctx_obj) { |
2331 | DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n"); | |
2332 | return -ENOMEM; | |
8c857917 OM |
2333 | } |
2334 | ||
dcb4c12a OM |
2335 | if (is_global_default_ctx) { |
2336 | ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN, 0); | |
2337 | if (ret) { | |
2338 | DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n", | |
2339 | ret); | |
2340 | drm_gem_object_unreference(&ctx_obj->base); | |
2341 | return ret; | |
2342 | } | |
8c857917 OM |
2343 | } |
2344 | ||
84c2377f OM |
2345 | ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL); |
2346 | if (!ringbuf) { | |
2347 | DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n", | |
2348 | ring->name); | |
84c2377f | 2349 | ret = -ENOMEM; |
7ba717cf | 2350 | goto error_unpin_ctx; |
84c2377f OM |
2351 | } |
2352 | ||
0c7dd53b | 2353 | ringbuf->ring = ring; |
582d67f0 | 2354 | |
84c2377f OM |
2355 | ringbuf->size = 32 * PAGE_SIZE; |
2356 | ringbuf->effective_size = ringbuf->size; | |
2357 | ringbuf->head = 0; | |
2358 | ringbuf->tail = 0; | |
84c2377f | 2359 | ringbuf->last_retired_head = -1; |
ebd0fd4b | 2360 | intel_ring_update_space(ringbuf); |
84c2377f | 2361 | |
7ba717cf TD |
2362 | if (ringbuf->obj == NULL) { |
2363 | ret = intel_alloc_ringbuffer_obj(dev, ringbuf); | |
2364 | if (ret) { | |
2365 | DRM_DEBUG_DRIVER( | |
2366 | "Failed to allocate ringbuffer obj %s: %d\n", | |
84c2377f | 2367 | ring->name, ret); |
7ba717cf TD |
2368 | goto error_free_rbuf; |
2369 | } | |
2370 | ||
2371 | if (is_global_default_ctx) { | |
2372 | ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf); | |
2373 | if (ret) { | |
2374 | DRM_ERROR( | |
2375 | "Failed to pin and map ringbuffer %s: %d\n", | |
2376 | ring->name, ret); | |
2377 | goto error_destroy_rbuf; | |
2378 | } | |
2379 | } | |
2380 | ||
8670d6f9 OM |
2381 | } |
2382 | ||
2383 | ret = populate_lr_context(ctx, ctx_obj, ring, ringbuf); | |
2384 | if (ret) { | |
2385 | DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret); | |
8670d6f9 | 2386 | goto error; |
84c2377f OM |
2387 | } |
2388 | ||
2389 | ctx->engine[ring->id].ringbuf = ringbuf; | |
8c857917 | 2390 | ctx->engine[ring->id].state = ctx_obj; |
ede7d42b | 2391 | |
70b0ea86 DV |
2392 | if (ctx == ring->default_context) |
2393 | lrc_setup_hardware_status_page(ring, ctx_obj); | |
e7778be1 | 2394 | else if (ring->id == RCS && !ctx->rcs_initialized) { |
771b9a53 | 2395 | if (ring->init_context) { |
76c39168 JH |
2396 | struct drm_i915_gem_request *req; |
2397 | ||
2398 | ret = i915_gem_request_alloc(ring, ctx, &req); | |
2399 | if (ret) | |
2400 | return ret; | |
2401 | ||
8753181e | 2402 | ret = ring->init_context(req); |
e7778be1 | 2403 | if (ret) { |
771b9a53 | 2404 | DRM_ERROR("ring init context: %d\n", ret); |
76c39168 | 2405 | i915_gem_request_cancel(req); |
e7778be1 TD |
2406 | ctx->engine[ring->id].ringbuf = NULL; |
2407 | ctx->engine[ring->id].state = NULL; | |
2408 | goto error; | |
2409 | } | |
76c39168 | 2410 | |
75289874 | 2411 | i915_add_request_no_flush(req); |
771b9a53 MT |
2412 | } |
2413 | ||
564ddb2f OM |
2414 | ctx->rcs_initialized = true; |
2415 | } | |
2416 | ||
ede7d42b | 2417 | return 0; |
8670d6f9 OM |
2418 | |
2419 | error: | |
7ba717cf TD |
2420 | if (is_global_default_ctx) |
2421 | intel_unpin_ringbuffer_obj(ringbuf); | |
2422 | error_destroy_rbuf: | |
2423 | intel_destroy_ringbuffer_obj(ringbuf); | |
2424 | error_free_rbuf: | |
8670d6f9 | 2425 | kfree(ringbuf); |
7ba717cf | 2426 | error_unpin_ctx: |
dcb4c12a OM |
2427 | if (is_global_default_ctx) |
2428 | i915_gem_object_ggtt_unpin(ctx_obj); | |
8670d6f9 OM |
2429 | drm_gem_object_unreference(&ctx_obj->base); |
2430 | return ret; | |
ede7d42b | 2431 | } |
3e5b6f05 TD |
2432 | |
2433 | void intel_lr_context_reset(struct drm_device *dev, | |
2434 | struct intel_context *ctx) | |
2435 | { | |
2436 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2437 | struct intel_engine_cs *ring; | |
2438 | int i; | |
2439 | ||
2440 | for_each_ring(ring, dev_priv, i) { | |
2441 | struct drm_i915_gem_object *ctx_obj = | |
2442 | ctx->engine[ring->id].state; | |
2443 | struct intel_ringbuffer *ringbuf = | |
2444 | ctx->engine[ring->id].ringbuf; | |
2445 | uint32_t *reg_state; | |
2446 | struct page *page; | |
2447 | ||
2448 | if (!ctx_obj) | |
2449 | continue; | |
2450 | ||
2451 | if (i915_gem_object_get_pages(ctx_obj)) { | |
2452 | WARN(1, "Failed get_pages for context obj\n"); | |
2453 | continue; | |
2454 | } | |
2455 | page = i915_gem_object_get_page(ctx_obj, 1); | |
2456 | reg_state = kmap_atomic(page); | |
2457 | ||
2458 | reg_state[CTX_RING_HEAD+1] = 0; | |
2459 | reg_state[CTX_RING_TAIL+1] = 0; | |
2460 | ||
2461 | kunmap_atomic(reg_state); | |
2462 | ||
2463 | ringbuf->head = 0; | |
2464 | ringbuf->tail = 0; | |
2465 | } | |
2466 | } |