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b20385f1 OM |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * Michel Thierry <michel.thierry@intel.com> | |
26 | * Thomas Daniel <thomas.daniel@intel.com> | |
27 | * Oscar Mateo <oscar.mateo@intel.com> | |
28 | * | |
29 | */ | |
30 | ||
31 | /* | |
32 | * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts". | |
33 | * These expanded contexts enable a number of new abilities, especially | |
34 | * "Execlists" (also implemented in this file). | |
35 | * | |
36 | * Execlists are the new method by which, on gen8+ hardware, workloads are | |
37 | * submitted for execution (as opposed to the legacy, ringbuffer-based, method). | |
38 | */ | |
39 | ||
40 | #include <drm/drmP.h> | |
41 | #include <drm/i915_drm.h> | |
42 | #include "i915_drv.h" | |
127f1003 | 43 | |
8c857917 OM |
44 | #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE) |
45 | #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE) | |
46 | ||
47 | #define GEN8_LR_CONTEXT_ALIGN 4096 | |
48 | ||
8670d6f9 | 49 | #define RING_ELSP(ring) ((ring)->mmio_base+0x230) |
84b790f8 | 50 | #define RING_EXECLIST_STATUS(ring) ((ring)->mmio_base+0x234) |
8670d6f9 | 51 | #define RING_CONTEXT_CONTROL(ring) ((ring)->mmio_base+0x244) |
e981e7b1 TD |
52 | #define RING_CONTEXT_STATUS_BUF(ring) ((ring)->mmio_base+0x370) |
53 | #define RING_CONTEXT_STATUS_PTR(ring) ((ring)->mmio_base+0x3a0) | |
54 | ||
55 | #define RING_EXECLIST_QFULL (1 << 0x2) | |
56 | #define RING_EXECLIST1_VALID (1 << 0x3) | |
57 | #define RING_EXECLIST0_VALID (1 << 0x4) | |
58 | #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE) | |
59 | #define RING_EXECLIST1_ACTIVE (1 << 0x11) | |
60 | #define RING_EXECLIST0_ACTIVE (1 << 0x12) | |
61 | ||
62 | #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0) | |
63 | #define GEN8_CTX_STATUS_PREEMPTED (1 << 1) | |
64 | #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2) | |
65 | #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3) | |
66 | #define GEN8_CTX_STATUS_COMPLETE (1 << 4) | |
67 | #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15) | |
8670d6f9 OM |
68 | |
69 | #define CTX_LRI_HEADER_0 0x01 | |
70 | #define CTX_CONTEXT_CONTROL 0x02 | |
71 | #define CTX_RING_HEAD 0x04 | |
72 | #define CTX_RING_TAIL 0x06 | |
73 | #define CTX_RING_BUFFER_START 0x08 | |
74 | #define CTX_RING_BUFFER_CONTROL 0x0a | |
75 | #define CTX_BB_HEAD_U 0x0c | |
76 | #define CTX_BB_HEAD_L 0x0e | |
77 | #define CTX_BB_STATE 0x10 | |
78 | #define CTX_SECOND_BB_HEAD_U 0x12 | |
79 | #define CTX_SECOND_BB_HEAD_L 0x14 | |
80 | #define CTX_SECOND_BB_STATE 0x16 | |
81 | #define CTX_BB_PER_CTX_PTR 0x18 | |
82 | #define CTX_RCS_INDIRECT_CTX 0x1a | |
83 | #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c | |
84 | #define CTX_LRI_HEADER_1 0x21 | |
85 | #define CTX_CTX_TIMESTAMP 0x22 | |
86 | #define CTX_PDP3_UDW 0x24 | |
87 | #define CTX_PDP3_LDW 0x26 | |
88 | #define CTX_PDP2_UDW 0x28 | |
89 | #define CTX_PDP2_LDW 0x2a | |
90 | #define CTX_PDP1_UDW 0x2c | |
91 | #define CTX_PDP1_LDW 0x2e | |
92 | #define CTX_PDP0_UDW 0x30 | |
93 | #define CTX_PDP0_LDW 0x32 | |
94 | #define CTX_LRI_HEADER_2 0x41 | |
95 | #define CTX_R_PWR_CLK_STATE 0x42 | |
96 | #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44 | |
97 | ||
84b790f8 BW |
98 | #define GEN8_CTX_VALID (1<<0) |
99 | #define GEN8_CTX_FORCE_PD_RESTORE (1<<1) | |
100 | #define GEN8_CTX_FORCE_RESTORE (1<<2) | |
101 | #define GEN8_CTX_L3LLC_COHERENT (1<<5) | |
102 | #define GEN8_CTX_PRIVILEGE (1<<8) | |
103 | enum { | |
104 | ADVANCED_CONTEXT = 0, | |
105 | LEGACY_CONTEXT, | |
106 | ADVANCED_AD_CONTEXT, | |
107 | LEGACY_64B_CONTEXT | |
108 | }; | |
109 | #define GEN8_CTX_MODE_SHIFT 3 | |
110 | enum { | |
111 | FAULT_AND_HANG = 0, | |
112 | FAULT_AND_HALT, /* Debug only */ | |
113 | FAULT_AND_STREAM, | |
114 | FAULT_AND_CONTINUE /* Unsupported */ | |
115 | }; | |
116 | #define GEN8_CTX_ID_SHIFT 32 | |
117 | ||
127f1003 OM |
118 | int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists) |
119 | { | |
bd84b1e9 DV |
120 | WARN_ON(i915.enable_ppgtt == -1); |
121 | ||
127f1003 OM |
122 | if (enable_execlists == 0) |
123 | return 0; | |
124 | ||
14bf993e OM |
125 | if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) && |
126 | i915.use_mmio_flip >= 0) | |
127f1003 OM |
127 | return 1; |
128 | ||
129 | return 0; | |
130 | } | |
ede7d42b | 131 | |
84b790f8 BW |
132 | u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj) |
133 | { | |
134 | u32 lrca = i915_gem_obj_ggtt_offset(ctx_obj); | |
135 | ||
136 | /* LRCA is required to be 4K aligned so the more significant 20 bits | |
137 | * are globally unique */ | |
138 | return lrca >> 12; | |
139 | } | |
140 | ||
141 | static uint64_t execlists_ctx_descriptor(struct drm_i915_gem_object *ctx_obj) | |
142 | { | |
143 | uint64_t desc; | |
144 | uint64_t lrca = i915_gem_obj_ggtt_offset(ctx_obj); | |
acdd884a MT |
145 | |
146 | WARN_ON(lrca & 0xFFFFFFFF00000FFFULL); | |
84b790f8 BW |
147 | |
148 | desc = GEN8_CTX_VALID; | |
149 | desc |= LEGACY_CONTEXT << GEN8_CTX_MODE_SHIFT; | |
150 | desc |= GEN8_CTX_L3LLC_COHERENT; | |
151 | desc |= GEN8_CTX_PRIVILEGE; | |
152 | desc |= lrca; | |
153 | desc |= (u64)intel_execlists_ctx_id(ctx_obj) << GEN8_CTX_ID_SHIFT; | |
154 | ||
155 | /* TODO: WaDisableLiteRestore when we start using semaphore | |
156 | * signalling between Command Streamers */ | |
157 | /* desc |= GEN8_CTX_FORCE_RESTORE; */ | |
158 | ||
159 | return desc; | |
160 | } | |
161 | ||
162 | static void execlists_elsp_write(struct intel_engine_cs *ring, | |
163 | struct drm_i915_gem_object *ctx_obj0, | |
164 | struct drm_i915_gem_object *ctx_obj1) | |
165 | { | |
166 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
167 | uint64_t temp = 0; | |
168 | uint32_t desc[4]; | |
e981e7b1 | 169 | unsigned long flags; |
84b790f8 BW |
170 | |
171 | /* XXX: You must always write both descriptors in the order below. */ | |
172 | if (ctx_obj1) | |
173 | temp = execlists_ctx_descriptor(ctx_obj1); | |
174 | else | |
175 | temp = 0; | |
176 | desc[1] = (u32)(temp >> 32); | |
177 | desc[0] = (u32)temp; | |
178 | ||
179 | temp = execlists_ctx_descriptor(ctx_obj0); | |
180 | desc[3] = (u32)(temp >> 32); | |
181 | desc[2] = (u32)temp; | |
182 | ||
e981e7b1 TD |
183 | /* Set Force Wakeup bit to prevent GT from entering C6 while ELSP writes |
184 | * are in progress. | |
185 | * | |
186 | * The other problem is that we can't just call gen6_gt_force_wake_get() | |
187 | * because that function calls intel_runtime_pm_get(), which might sleep. | |
188 | * Instead, we do the runtime_pm_get/put when creating/destroying requests. | |
189 | */ | |
190 | spin_lock_irqsave(&dev_priv->uncore.lock, flags); | |
191 | if (dev_priv->uncore.forcewake_count++ == 0) | |
192 | dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL); | |
193 | spin_unlock_irqrestore(&dev_priv->uncore.lock, flags); | |
84b790f8 BW |
194 | |
195 | I915_WRITE(RING_ELSP(ring), desc[1]); | |
196 | I915_WRITE(RING_ELSP(ring), desc[0]); | |
197 | I915_WRITE(RING_ELSP(ring), desc[3]); | |
198 | /* The context is automatically loaded after the following */ | |
199 | I915_WRITE(RING_ELSP(ring), desc[2]); | |
200 | ||
201 | /* ELSP is a wo register, so use another nearby reg for posting instead */ | |
202 | POSTING_READ(RING_EXECLIST_STATUS(ring)); | |
203 | ||
e981e7b1 TD |
204 | /* Release Force Wakeup (see the big comment above). */ |
205 | spin_lock_irqsave(&dev_priv->uncore.lock, flags); | |
206 | if (--dev_priv->uncore.forcewake_count == 0) | |
207 | dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL); | |
208 | spin_unlock_irqrestore(&dev_priv->uncore.lock, flags); | |
84b790f8 BW |
209 | } |
210 | ||
ae1250b9 OM |
211 | static int execlists_ctx_write_tail(struct drm_i915_gem_object *ctx_obj, u32 tail) |
212 | { | |
213 | struct page *page; | |
214 | uint32_t *reg_state; | |
215 | ||
216 | page = i915_gem_object_get_page(ctx_obj, 1); | |
217 | reg_state = kmap_atomic(page); | |
218 | ||
219 | reg_state[CTX_RING_TAIL+1] = tail; | |
220 | ||
221 | kunmap_atomic(reg_state); | |
222 | ||
223 | return 0; | |
224 | } | |
225 | ||
84b790f8 BW |
226 | static int execlists_submit_context(struct intel_engine_cs *ring, |
227 | struct intel_context *to0, u32 tail0, | |
228 | struct intel_context *to1, u32 tail1) | |
229 | { | |
230 | struct drm_i915_gem_object *ctx_obj0; | |
231 | struct drm_i915_gem_object *ctx_obj1 = NULL; | |
232 | ||
233 | ctx_obj0 = to0->engine[ring->id].state; | |
234 | BUG_ON(!ctx_obj0); | |
acdd884a | 235 | WARN_ON(!i915_gem_obj_is_pinned(ctx_obj0)); |
84b790f8 | 236 | |
ae1250b9 OM |
237 | execlists_ctx_write_tail(ctx_obj0, tail0); |
238 | ||
84b790f8 BW |
239 | if (to1) { |
240 | ctx_obj1 = to1->engine[ring->id].state; | |
241 | BUG_ON(!ctx_obj1); | |
acdd884a | 242 | WARN_ON(!i915_gem_obj_is_pinned(ctx_obj1)); |
ae1250b9 OM |
243 | |
244 | execlists_ctx_write_tail(ctx_obj1, tail1); | |
84b790f8 BW |
245 | } |
246 | ||
247 | execlists_elsp_write(ring, ctx_obj0, ctx_obj1); | |
248 | ||
249 | return 0; | |
250 | } | |
251 | ||
acdd884a MT |
252 | static void execlists_context_unqueue(struct intel_engine_cs *ring) |
253 | { | |
254 | struct intel_ctx_submit_request *req0 = NULL, *req1 = NULL; | |
255 | struct intel_ctx_submit_request *cursor = NULL, *tmp = NULL; | |
e981e7b1 TD |
256 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
257 | ||
258 | assert_spin_locked(&ring->execlist_lock); | |
acdd884a MT |
259 | |
260 | if (list_empty(&ring->execlist_queue)) | |
261 | return; | |
262 | ||
263 | /* Try to read in pairs */ | |
264 | list_for_each_entry_safe(cursor, tmp, &ring->execlist_queue, | |
265 | execlist_link) { | |
266 | if (!req0) { | |
267 | req0 = cursor; | |
268 | } else if (req0->ctx == cursor->ctx) { | |
269 | /* Same ctx: ignore first request, as second request | |
270 | * will update tail past first request's workload */ | |
e1fee72c | 271 | cursor->elsp_submitted = req0->elsp_submitted; |
acdd884a | 272 | list_del(&req0->execlist_link); |
e981e7b1 | 273 | queue_work(dev_priv->wq, &req0->work); |
acdd884a MT |
274 | req0 = cursor; |
275 | } else { | |
276 | req1 = cursor; | |
277 | break; | |
278 | } | |
279 | } | |
280 | ||
e1fee72c OM |
281 | WARN_ON(req1 && req1->elsp_submitted); |
282 | ||
acdd884a MT |
283 | WARN_ON(execlists_submit_context(ring, req0->ctx, req0->tail, |
284 | req1 ? req1->ctx : NULL, | |
285 | req1 ? req1->tail : 0)); | |
e1fee72c OM |
286 | |
287 | req0->elsp_submitted++; | |
288 | if (req1) | |
289 | req1->elsp_submitted++; | |
acdd884a MT |
290 | } |
291 | ||
e981e7b1 TD |
292 | static bool execlists_check_remove_request(struct intel_engine_cs *ring, |
293 | u32 request_id) | |
294 | { | |
295 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
296 | struct intel_ctx_submit_request *head_req; | |
297 | ||
298 | assert_spin_locked(&ring->execlist_lock); | |
299 | ||
300 | head_req = list_first_entry_or_null(&ring->execlist_queue, | |
301 | struct intel_ctx_submit_request, | |
302 | execlist_link); | |
303 | ||
304 | if (head_req != NULL) { | |
305 | struct drm_i915_gem_object *ctx_obj = | |
306 | head_req->ctx->engine[ring->id].state; | |
307 | if (intel_execlists_ctx_id(ctx_obj) == request_id) { | |
e1fee72c OM |
308 | WARN(head_req->elsp_submitted == 0, |
309 | "Never submitted head request\n"); | |
310 | ||
311 | if (--head_req->elsp_submitted <= 0) { | |
312 | list_del(&head_req->execlist_link); | |
313 | queue_work(dev_priv->wq, &head_req->work); | |
314 | return true; | |
315 | } | |
e981e7b1 TD |
316 | } |
317 | } | |
318 | ||
319 | return false; | |
320 | } | |
321 | ||
322 | void intel_execlists_handle_ctx_events(struct intel_engine_cs *ring) | |
323 | { | |
324 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
325 | u32 status_pointer; | |
326 | u8 read_pointer; | |
327 | u8 write_pointer; | |
328 | u32 status; | |
329 | u32 status_id; | |
330 | u32 submit_contexts = 0; | |
331 | ||
332 | status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring)); | |
333 | ||
334 | read_pointer = ring->next_context_status_buffer; | |
335 | write_pointer = status_pointer & 0x07; | |
336 | if (read_pointer > write_pointer) | |
337 | write_pointer += 6; | |
338 | ||
339 | spin_lock(&ring->execlist_lock); | |
340 | ||
341 | while (read_pointer < write_pointer) { | |
342 | read_pointer++; | |
343 | status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + | |
344 | (read_pointer % 6) * 8); | |
345 | status_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + | |
346 | (read_pointer % 6) * 8 + 4); | |
347 | ||
e1fee72c OM |
348 | if (status & GEN8_CTX_STATUS_PREEMPTED) { |
349 | if (status & GEN8_CTX_STATUS_LITE_RESTORE) { | |
350 | if (execlists_check_remove_request(ring, status_id)) | |
351 | WARN(1, "Lite Restored request removed from queue\n"); | |
352 | } else | |
353 | WARN(1, "Preemption without Lite Restore\n"); | |
354 | } | |
355 | ||
356 | if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) || | |
357 | (status & GEN8_CTX_STATUS_ELEMENT_SWITCH)) { | |
e981e7b1 TD |
358 | if (execlists_check_remove_request(ring, status_id)) |
359 | submit_contexts++; | |
360 | } | |
361 | } | |
362 | ||
363 | if (submit_contexts != 0) | |
364 | execlists_context_unqueue(ring); | |
365 | ||
366 | spin_unlock(&ring->execlist_lock); | |
367 | ||
368 | WARN(submit_contexts > 2, "More than two context complete events?\n"); | |
369 | ring->next_context_status_buffer = write_pointer % 6; | |
370 | ||
371 | I915_WRITE(RING_CONTEXT_STATUS_PTR(ring), | |
372 | ((u32)ring->next_context_status_buffer & 0x07) << 8); | |
373 | } | |
374 | ||
375 | static void execlists_free_request_task(struct work_struct *work) | |
376 | { | |
377 | struct intel_ctx_submit_request *req = | |
378 | container_of(work, struct intel_ctx_submit_request, work); | |
379 | struct drm_device *dev = req->ring->dev; | |
380 | struct drm_i915_private *dev_priv = dev->dev_private; | |
381 | ||
382 | intel_runtime_pm_put(dev_priv); | |
383 | ||
384 | mutex_lock(&dev->struct_mutex); | |
385 | i915_gem_context_unreference(req->ctx); | |
386 | mutex_unlock(&dev->struct_mutex); | |
387 | ||
388 | kfree(req); | |
389 | } | |
390 | ||
acdd884a MT |
391 | static int execlists_context_queue(struct intel_engine_cs *ring, |
392 | struct intel_context *to, | |
393 | u32 tail) | |
394 | { | |
395 | struct intel_ctx_submit_request *req = NULL; | |
e981e7b1 | 396 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
acdd884a MT |
397 | unsigned long flags; |
398 | bool was_empty; | |
399 | ||
400 | req = kzalloc(sizeof(*req), GFP_KERNEL); | |
401 | if (req == NULL) | |
402 | return -ENOMEM; | |
403 | req->ctx = to; | |
404 | i915_gem_context_reference(req->ctx); | |
405 | req->ring = ring; | |
406 | req->tail = tail; | |
e981e7b1 TD |
407 | INIT_WORK(&req->work, execlists_free_request_task); |
408 | ||
409 | intel_runtime_pm_get(dev_priv); | |
acdd884a MT |
410 | |
411 | spin_lock_irqsave(&ring->execlist_lock, flags); | |
412 | ||
413 | was_empty = list_empty(&ring->execlist_queue); | |
414 | list_add_tail(&req->execlist_link, &ring->execlist_queue); | |
415 | if (was_empty) | |
416 | execlists_context_unqueue(ring); | |
417 | ||
418 | spin_unlock_irqrestore(&ring->execlist_lock, flags); | |
419 | ||
420 | return 0; | |
421 | } | |
422 | ||
ba8b7ccb OM |
423 | static int logical_ring_invalidate_all_caches(struct intel_ringbuffer *ringbuf) |
424 | { | |
425 | struct intel_engine_cs *ring = ringbuf->ring; | |
426 | uint32_t flush_domains; | |
427 | int ret; | |
428 | ||
429 | flush_domains = 0; | |
430 | if (ring->gpu_caches_dirty) | |
431 | flush_domains = I915_GEM_GPU_DOMAINS; | |
432 | ||
433 | ret = ring->emit_flush(ringbuf, I915_GEM_GPU_DOMAINS, flush_domains); | |
434 | if (ret) | |
435 | return ret; | |
436 | ||
437 | ring->gpu_caches_dirty = false; | |
438 | return 0; | |
439 | } | |
440 | ||
441 | static int execlists_move_to_gpu(struct intel_ringbuffer *ringbuf, | |
442 | struct list_head *vmas) | |
443 | { | |
444 | struct intel_engine_cs *ring = ringbuf->ring; | |
445 | struct i915_vma *vma; | |
446 | uint32_t flush_domains = 0; | |
447 | bool flush_chipset = false; | |
448 | int ret; | |
449 | ||
450 | list_for_each_entry(vma, vmas, exec_list) { | |
451 | struct drm_i915_gem_object *obj = vma->obj; | |
452 | ||
453 | ret = i915_gem_object_sync(obj, ring); | |
454 | if (ret) | |
455 | return ret; | |
456 | ||
457 | if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) | |
458 | flush_chipset |= i915_gem_clflush_object(obj, false); | |
459 | ||
460 | flush_domains |= obj->base.write_domain; | |
461 | } | |
462 | ||
463 | if (flush_domains & I915_GEM_DOMAIN_GTT) | |
464 | wmb(); | |
465 | ||
466 | /* Unconditionally invalidate gpu caches and ensure that we do flush | |
467 | * any residual writes from the previous batch. | |
468 | */ | |
469 | return logical_ring_invalidate_all_caches(ringbuf); | |
470 | } | |
471 | ||
454afebd OM |
472 | int intel_execlists_submission(struct drm_device *dev, struct drm_file *file, |
473 | struct intel_engine_cs *ring, | |
474 | struct intel_context *ctx, | |
475 | struct drm_i915_gem_execbuffer2 *args, | |
476 | struct list_head *vmas, | |
477 | struct drm_i915_gem_object *batch_obj, | |
478 | u64 exec_start, u32 flags) | |
479 | { | |
ba8b7ccb OM |
480 | struct drm_i915_private *dev_priv = dev->dev_private; |
481 | struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf; | |
482 | int instp_mode; | |
483 | u32 instp_mask; | |
484 | int ret; | |
485 | ||
486 | instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK; | |
487 | instp_mask = I915_EXEC_CONSTANTS_MASK; | |
488 | switch (instp_mode) { | |
489 | case I915_EXEC_CONSTANTS_REL_GENERAL: | |
490 | case I915_EXEC_CONSTANTS_ABSOLUTE: | |
491 | case I915_EXEC_CONSTANTS_REL_SURFACE: | |
492 | if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) { | |
493 | DRM_DEBUG("non-0 rel constants mode on non-RCS\n"); | |
494 | return -EINVAL; | |
495 | } | |
496 | ||
497 | if (instp_mode != dev_priv->relative_constants_mode) { | |
498 | if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) { | |
499 | DRM_DEBUG("rel surface constants mode invalid on gen5+\n"); | |
500 | return -EINVAL; | |
501 | } | |
502 | ||
503 | /* The HW changed the meaning on this bit on gen6 */ | |
504 | instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; | |
505 | } | |
506 | break; | |
507 | default: | |
508 | DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode); | |
509 | return -EINVAL; | |
510 | } | |
511 | ||
512 | if (args->num_cliprects != 0) { | |
513 | DRM_DEBUG("clip rectangles are only valid on pre-gen5\n"); | |
514 | return -EINVAL; | |
515 | } else { | |
516 | if (args->DR4 == 0xffffffff) { | |
517 | DRM_DEBUG("UXA submitting garbage DR4, fixing up\n"); | |
518 | args->DR4 = 0; | |
519 | } | |
520 | ||
521 | if (args->DR1 || args->DR4 || args->cliprects_ptr) { | |
522 | DRM_DEBUG("0 cliprects but dirt in cliprects fields\n"); | |
523 | return -EINVAL; | |
524 | } | |
525 | } | |
526 | ||
527 | if (args->flags & I915_EXEC_GEN7_SOL_RESET) { | |
528 | DRM_DEBUG("sol reset is gen7 only\n"); | |
529 | return -EINVAL; | |
530 | } | |
531 | ||
532 | ret = execlists_move_to_gpu(ringbuf, vmas); | |
533 | if (ret) | |
534 | return ret; | |
535 | ||
536 | if (ring == &dev_priv->ring[RCS] && | |
537 | instp_mode != dev_priv->relative_constants_mode) { | |
538 | ret = intel_logical_ring_begin(ringbuf, 4); | |
539 | if (ret) | |
540 | return ret; | |
541 | ||
542 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
543 | intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1)); | |
544 | intel_logical_ring_emit(ringbuf, INSTPM); | |
545 | intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode); | |
546 | intel_logical_ring_advance(ringbuf); | |
547 | ||
548 | dev_priv->relative_constants_mode = instp_mode; | |
549 | } | |
550 | ||
551 | ret = ring->emit_bb_start(ringbuf, exec_start, flags); | |
552 | if (ret) | |
553 | return ret; | |
554 | ||
555 | i915_gem_execbuffer_move_to_active(vmas, ring); | |
556 | i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj); | |
557 | ||
454afebd OM |
558 | return 0; |
559 | } | |
560 | ||
561 | void intel_logical_ring_stop(struct intel_engine_cs *ring) | |
562 | { | |
9832b9da OM |
563 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
564 | int ret; | |
565 | ||
566 | if (!intel_ring_initialized(ring)) | |
567 | return; | |
568 | ||
569 | ret = intel_ring_idle(ring); | |
570 | if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error)) | |
571 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", | |
572 | ring->name, ret); | |
573 | ||
574 | /* TODO: Is this correct with Execlists enabled? */ | |
575 | I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING)); | |
576 | if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) { | |
577 | DRM_ERROR("%s :timed out trying to stop ring\n", ring->name); | |
578 | return; | |
579 | } | |
580 | I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING)); | |
454afebd OM |
581 | } |
582 | ||
48e29f55 OM |
583 | int logical_ring_flush_all_caches(struct intel_ringbuffer *ringbuf) |
584 | { | |
585 | struct intel_engine_cs *ring = ringbuf->ring; | |
586 | int ret; | |
587 | ||
588 | if (!ring->gpu_caches_dirty) | |
589 | return 0; | |
590 | ||
591 | ret = ring->emit_flush(ringbuf, 0, I915_GEM_GPU_DOMAINS); | |
592 | if (ret) | |
593 | return ret; | |
594 | ||
595 | ring->gpu_caches_dirty = false; | |
596 | return 0; | |
597 | } | |
598 | ||
82e104cc OM |
599 | void intel_logical_ring_advance_and_submit(struct intel_ringbuffer *ringbuf) |
600 | { | |
84b790f8 BW |
601 | struct intel_engine_cs *ring = ringbuf->ring; |
602 | struct intel_context *ctx = ringbuf->FIXME_lrc_ctx; | |
603 | ||
82e104cc OM |
604 | intel_logical_ring_advance(ringbuf); |
605 | ||
84b790f8 | 606 | if (intel_ring_stopped(ring)) |
82e104cc OM |
607 | return; |
608 | ||
acdd884a | 609 | execlists_context_queue(ring, ctx, ringbuf->tail); |
82e104cc OM |
610 | } |
611 | ||
48e29f55 OM |
612 | static int logical_ring_alloc_seqno(struct intel_engine_cs *ring, |
613 | struct intel_context *ctx) | |
82e104cc OM |
614 | { |
615 | if (ring->outstanding_lazy_seqno) | |
616 | return 0; | |
617 | ||
618 | if (ring->preallocated_lazy_request == NULL) { | |
619 | struct drm_i915_gem_request *request; | |
620 | ||
621 | request = kmalloc(sizeof(*request), GFP_KERNEL); | |
622 | if (request == NULL) | |
623 | return -ENOMEM; | |
624 | ||
48e29f55 OM |
625 | /* Hold a reference to the context this request belongs to |
626 | * (we will need it when the time comes to emit/retire the | |
627 | * request). | |
628 | */ | |
629 | request->ctx = ctx; | |
630 | i915_gem_context_reference(request->ctx); | |
631 | ||
82e104cc OM |
632 | ring->preallocated_lazy_request = request; |
633 | } | |
634 | ||
635 | return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno); | |
636 | } | |
637 | ||
638 | static int logical_ring_wait_request(struct intel_ringbuffer *ringbuf, | |
639 | int bytes) | |
640 | { | |
641 | struct intel_engine_cs *ring = ringbuf->ring; | |
642 | struct drm_i915_gem_request *request; | |
643 | u32 seqno = 0; | |
644 | int ret; | |
645 | ||
646 | if (ringbuf->last_retired_head != -1) { | |
647 | ringbuf->head = ringbuf->last_retired_head; | |
648 | ringbuf->last_retired_head = -1; | |
649 | ||
650 | ringbuf->space = intel_ring_space(ringbuf); | |
651 | if (ringbuf->space >= bytes) | |
652 | return 0; | |
653 | } | |
654 | ||
655 | list_for_each_entry(request, &ring->request_list, list) { | |
656 | if (__intel_ring_space(request->tail, ringbuf->tail, | |
657 | ringbuf->size) >= bytes) { | |
658 | seqno = request->seqno; | |
659 | break; | |
660 | } | |
661 | } | |
662 | ||
663 | if (seqno == 0) | |
664 | return -ENOSPC; | |
665 | ||
666 | ret = i915_wait_seqno(ring, seqno); | |
667 | if (ret) | |
668 | return ret; | |
669 | ||
82e104cc OM |
670 | i915_gem_retire_requests_ring(ring); |
671 | ringbuf->head = ringbuf->last_retired_head; | |
672 | ringbuf->last_retired_head = -1; | |
673 | ||
674 | ringbuf->space = intel_ring_space(ringbuf); | |
675 | return 0; | |
676 | } | |
677 | ||
678 | static int logical_ring_wait_for_space(struct intel_ringbuffer *ringbuf, | |
679 | int bytes) | |
680 | { | |
681 | struct intel_engine_cs *ring = ringbuf->ring; | |
682 | struct drm_device *dev = ring->dev; | |
683 | struct drm_i915_private *dev_priv = dev->dev_private; | |
684 | unsigned long end; | |
685 | int ret; | |
686 | ||
687 | ret = logical_ring_wait_request(ringbuf, bytes); | |
688 | if (ret != -ENOSPC) | |
689 | return ret; | |
690 | ||
691 | /* Force the context submission in case we have been skipping it */ | |
692 | intel_logical_ring_advance_and_submit(ringbuf); | |
693 | ||
694 | /* With GEM the hangcheck timer should kick us out of the loop, | |
695 | * leaving it early runs the risk of corrupting GEM state (due | |
696 | * to running on almost untested codepaths). But on resume | |
697 | * timers don't work yet, so prevent a complete hang in that | |
698 | * case by choosing an insanely large timeout. */ | |
699 | end = jiffies + 60 * HZ; | |
700 | ||
701 | do { | |
702 | ringbuf->head = I915_READ_HEAD(ring); | |
703 | ringbuf->space = intel_ring_space(ringbuf); | |
704 | if (ringbuf->space >= bytes) { | |
705 | ret = 0; | |
706 | break; | |
707 | } | |
708 | ||
709 | msleep(1); | |
710 | ||
711 | if (dev_priv->mm.interruptible && signal_pending(current)) { | |
712 | ret = -ERESTARTSYS; | |
713 | break; | |
714 | } | |
715 | ||
716 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, | |
717 | dev_priv->mm.interruptible); | |
718 | if (ret) | |
719 | break; | |
720 | ||
721 | if (time_after(jiffies, end)) { | |
722 | ret = -EBUSY; | |
723 | break; | |
724 | } | |
725 | } while (1); | |
726 | ||
727 | return ret; | |
728 | } | |
729 | ||
730 | static int logical_ring_wrap_buffer(struct intel_ringbuffer *ringbuf) | |
731 | { | |
732 | uint32_t __iomem *virt; | |
733 | int rem = ringbuf->size - ringbuf->tail; | |
734 | ||
735 | if (ringbuf->space < rem) { | |
736 | int ret = logical_ring_wait_for_space(ringbuf, rem); | |
737 | ||
738 | if (ret) | |
739 | return ret; | |
740 | } | |
741 | ||
742 | virt = ringbuf->virtual_start + ringbuf->tail; | |
743 | rem /= 4; | |
744 | while (rem--) | |
745 | iowrite32(MI_NOOP, virt++); | |
746 | ||
747 | ringbuf->tail = 0; | |
748 | ringbuf->space = intel_ring_space(ringbuf); | |
749 | ||
750 | return 0; | |
751 | } | |
752 | ||
753 | static int logical_ring_prepare(struct intel_ringbuffer *ringbuf, int bytes) | |
754 | { | |
755 | int ret; | |
756 | ||
757 | if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) { | |
758 | ret = logical_ring_wrap_buffer(ringbuf); | |
759 | if (unlikely(ret)) | |
760 | return ret; | |
761 | } | |
762 | ||
763 | if (unlikely(ringbuf->space < bytes)) { | |
764 | ret = logical_ring_wait_for_space(ringbuf, bytes); | |
765 | if (unlikely(ret)) | |
766 | return ret; | |
767 | } | |
768 | ||
769 | return 0; | |
770 | } | |
771 | ||
772 | int intel_logical_ring_begin(struct intel_ringbuffer *ringbuf, int num_dwords) | |
773 | { | |
774 | struct intel_engine_cs *ring = ringbuf->ring; | |
775 | struct drm_device *dev = ring->dev; | |
776 | struct drm_i915_private *dev_priv = dev->dev_private; | |
777 | int ret; | |
778 | ||
779 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, | |
780 | dev_priv->mm.interruptible); | |
781 | if (ret) | |
782 | return ret; | |
783 | ||
784 | ret = logical_ring_prepare(ringbuf, num_dwords * sizeof(uint32_t)); | |
785 | if (ret) | |
786 | return ret; | |
787 | ||
788 | /* Preallocate the olr before touching the ring */ | |
48e29f55 | 789 | ret = logical_ring_alloc_seqno(ring, ringbuf->FIXME_lrc_ctx); |
82e104cc OM |
790 | if (ret) |
791 | return ret; | |
792 | ||
793 | ringbuf->space -= num_dwords * sizeof(uint32_t); | |
794 | return 0; | |
795 | } | |
796 | ||
9b1136d5 OM |
797 | static int gen8_init_common_ring(struct intel_engine_cs *ring) |
798 | { | |
799 | struct drm_device *dev = ring->dev; | |
800 | struct drm_i915_private *dev_priv = dev->dev_private; | |
801 | ||
73d477f6 OM |
802 | I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask)); |
803 | I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff); | |
804 | ||
9b1136d5 OM |
805 | I915_WRITE(RING_MODE_GEN7(ring), |
806 | _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) | | |
807 | _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)); | |
808 | POSTING_READ(RING_MODE_GEN7(ring)); | |
809 | DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring->name); | |
810 | ||
811 | memset(&ring->hangcheck, 0, sizeof(ring->hangcheck)); | |
812 | ||
813 | return 0; | |
814 | } | |
815 | ||
816 | static int gen8_init_render_ring(struct intel_engine_cs *ring) | |
817 | { | |
818 | struct drm_device *dev = ring->dev; | |
819 | struct drm_i915_private *dev_priv = dev->dev_private; | |
820 | int ret; | |
821 | ||
822 | ret = gen8_init_common_ring(ring); | |
823 | if (ret) | |
824 | return ret; | |
825 | ||
826 | /* We need to disable the AsyncFlip performance optimisations in order | |
827 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
828 | * programmed to '1' on all products. | |
829 | * | |
830 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv | |
831 | */ | |
832 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); | |
833 | ||
834 | ret = intel_init_pipe_control(ring); | |
835 | if (ret) | |
836 | return ret; | |
837 | ||
838 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); | |
839 | ||
840 | return ret; | |
841 | } | |
842 | ||
15648585 OM |
843 | static int gen8_emit_bb_start(struct intel_ringbuffer *ringbuf, |
844 | u64 offset, unsigned flags) | |
845 | { | |
15648585 OM |
846 | bool ppgtt = !(flags & I915_DISPATCH_SECURE); |
847 | int ret; | |
848 | ||
849 | ret = intel_logical_ring_begin(ringbuf, 4); | |
850 | if (ret) | |
851 | return ret; | |
852 | ||
853 | /* FIXME(BDW): Address space and security selectors. */ | |
854 | intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8)); | |
855 | intel_logical_ring_emit(ringbuf, lower_32_bits(offset)); | |
856 | intel_logical_ring_emit(ringbuf, upper_32_bits(offset)); | |
857 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
858 | intel_logical_ring_advance(ringbuf); | |
859 | ||
860 | return 0; | |
861 | } | |
862 | ||
73d477f6 OM |
863 | static bool gen8_logical_ring_get_irq(struct intel_engine_cs *ring) |
864 | { | |
865 | struct drm_device *dev = ring->dev; | |
866 | struct drm_i915_private *dev_priv = dev->dev_private; | |
867 | unsigned long flags; | |
868 | ||
869 | if (!dev->irq_enabled) | |
870 | return false; | |
871 | ||
872 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
873 | if (ring->irq_refcount++ == 0) { | |
874 | I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask)); | |
875 | POSTING_READ(RING_IMR(ring->mmio_base)); | |
876 | } | |
877 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
878 | ||
879 | return true; | |
880 | } | |
881 | ||
882 | static void gen8_logical_ring_put_irq(struct intel_engine_cs *ring) | |
883 | { | |
884 | struct drm_device *dev = ring->dev; | |
885 | struct drm_i915_private *dev_priv = dev->dev_private; | |
886 | unsigned long flags; | |
887 | ||
888 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
889 | if (--ring->irq_refcount == 0) { | |
890 | I915_WRITE_IMR(ring, ~ring->irq_keep_mask); | |
891 | POSTING_READ(RING_IMR(ring->mmio_base)); | |
892 | } | |
893 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
894 | } | |
895 | ||
4712274c OM |
896 | static int gen8_emit_flush(struct intel_ringbuffer *ringbuf, |
897 | u32 invalidate_domains, | |
898 | u32 unused) | |
899 | { | |
900 | struct intel_engine_cs *ring = ringbuf->ring; | |
901 | struct drm_device *dev = ring->dev; | |
902 | struct drm_i915_private *dev_priv = dev->dev_private; | |
903 | uint32_t cmd; | |
904 | int ret; | |
905 | ||
906 | ret = intel_logical_ring_begin(ringbuf, 4); | |
907 | if (ret) | |
908 | return ret; | |
909 | ||
910 | cmd = MI_FLUSH_DW + 1; | |
911 | ||
912 | if (ring == &dev_priv->ring[VCS]) { | |
913 | if (invalidate_domains & I915_GEM_GPU_DOMAINS) | |
914 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD | | |
915 | MI_FLUSH_DW_STORE_INDEX | | |
916 | MI_FLUSH_DW_OP_STOREDW; | |
917 | } else { | |
918 | if (invalidate_domains & I915_GEM_DOMAIN_RENDER) | |
919 | cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX | | |
920 | MI_FLUSH_DW_OP_STOREDW; | |
921 | } | |
922 | ||
923 | intel_logical_ring_emit(ringbuf, cmd); | |
924 | intel_logical_ring_emit(ringbuf, | |
925 | I915_GEM_HWS_SCRATCH_ADDR | | |
926 | MI_FLUSH_DW_USE_GTT); | |
927 | intel_logical_ring_emit(ringbuf, 0); /* upper addr */ | |
928 | intel_logical_ring_emit(ringbuf, 0); /* value */ | |
929 | intel_logical_ring_advance(ringbuf); | |
930 | ||
931 | return 0; | |
932 | } | |
933 | ||
934 | static int gen8_emit_flush_render(struct intel_ringbuffer *ringbuf, | |
935 | u32 invalidate_domains, | |
936 | u32 flush_domains) | |
937 | { | |
938 | struct intel_engine_cs *ring = ringbuf->ring; | |
939 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; | |
940 | u32 flags = 0; | |
941 | int ret; | |
942 | ||
943 | flags |= PIPE_CONTROL_CS_STALL; | |
944 | ||
945 | if (flush_domains) { | |
946 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
947 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
948 | } | |
949 | ||
950 | if (invalidate_domains) { | |
951 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
952 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
953 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
954 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
955 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
956 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
957 | flags |= PIPE_CONTROL_QW_WRITE; | |
958 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
959 | } | |
960 | ||
961 | ret = intel_logical_ring_begin(ringbuf, 6); | |
962 | if (ret) | |
963 | return ret; | |
964 | ||
965 | intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6)); | |
966 | intel_logical_ring_emit(ringbuf, flags); | |
967 | intel_logical_ring_emit(ringbuf, scratch_addr); | |
968 | intel_logical_ring_emit(ringbuf, 0); | |
969 | intel_logical_ring_emit(ringbuf, 0); | |
970 | intel_logical_ring_emit(ringbuf, 0); | |
971 | intel_logical_ring_advance(ringbuf); | |
972 | ||
973 | return 0; | |
974 | } | |
975 | ||
e94e37ad OM |
976 | static u32 gen8_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
977 | { | |
978 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); | |
979 | } | |
980 | ||
981 | static void gen8_set_seqno(struct intel_engine_cs *ring, u32 seqno) | |
982 | { | |
983 | intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno); | |
984 | } | |
985 | ||
4da46e1e OM |
986 | static int gen8_emit_request(struct intel_ringbuffer *ringbuf) |
987 | { | |
988 | struct intel_engine_cs *ring = ringbuf->ring; | |
989 | u32 cmd; | |
990 | int ret; | |
991 | ||
992 | ret = intel_logical_ring_begin(ringbuf, 6); | |
993 | if (ret) | |
994 | return ret; | |
995 | ||
996 | cmd = MI_STORE_DWORD_IMM_GEN8; | |
997 | cmd |= MI_GLOBAL_GTT; | |
998 | ||
999 | intel_logical_ring_emit(ringbuf, cmd); | |
1000 | intel_logical_ring_emit(ringbuf, | |
1001 | (ring->status_page.gfx_addr + | |
1002 | (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT))); | |
1003 | intel_logical_ring_emit(ringbuf, 0); | |
1004 | intel_logical_ring_emit(ringbuf, ring->outstanding_lazy_seqno); | |
1005 | intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT); | |
1006 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
1007 | intel_logical_ring_advance_and_submit(ringbuf); | |
1008 | ||
1009 | return 0; | |
1010 | } | |
1011 | ||
454afebd OM |
1012 | void intel_logical_ring_cleanup(struct intel_engine_cs *ring) |
1013 | { | |
9832b9da OM |
1014 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
1015 | ||
48d82387 OM |
1016 | if (!intel_ring_initialized(ring)) |
1017 | return; | |
1018 | ||
9832b9da OM |
1019 | intel_logical_ring_stop(ring); |
1020 | WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0); | |
48d82387 OM |
1021 | ring->preallocated_lazy_request = NULL; |
1022 | ring->outstanding_lazy_seqno = 0; | |
1023 | ||
1024 | if (ring->cleanup) | |
1025 | ring->cleanup(ring); | |
1026 | ||
1027 | i915_cmd_parser_fini_ring(ring); | |
1028 | ||
1029 | if (ring->status_page.obj) { | |
1030 | kunmap(sg_page(ring->status_page.obj->pages->sgl)); | |
1031 | ring->status_page.obj = NULL; | |
1032 | } | |
454afebd OM |
1033 | } |
1034 | ||
1035 | static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *ring) | |
1036 | { | |
48d82387 OM |
1037 | int ret; |
1038 | struct intel_context *dctx = ring->default_context; | |
1039 | struct drm_i915_gem_object *dctx_obj; | |
1040 | ||
1041 | /* Intentionally left blank. */ | |
1042 | ring->buffer = NULL; | |
1043 | ||
1044 | ring->dev = dev; | |
1045 | INIT_LIST_HEAD(&ring->active_list); | |
1046 | INIT_LIST_HEAD(&ring->request_list); | |
1047 | init_waitqueue_head(&ring->irq_queue); | |
1048 | ||
acdd884a MT |
1049 | INIT_LIST_HEAD(&ring->execlist_queue); |
1050 | spin_lock_init(&ring->execlist_lock); | |
e981e7b1 | 1051 | ring->next_context_status_buffer = 0; |
acdd884a | 1052 | |
48d82387 OM |
1053 | ret = intel_lr_context_deferred_create(dctx, ring); |
1054 | if (ret) | |
1055 | return ret; | |
1056 | ||
1057 | /* The status page is offset 0 from the context object in LRCs. */ | |
1058 | dctx_obj = dctx->engine[ring->id].state; | |
1059 | ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(dctx_obj); | |
1060 | ring->status_page.page_addr = kmap(sg_page(dctx_obj->pages->sgl)); | |
1061 | if (ring->status_page.page_addr == NULL) | |
1062 | return -ENOMEM; | |
1063 | ring->status_page.obj = dctx_obj; | |
1064 | ||
1065 | ret = i915_cmd_parser_init_ring(ring); | |
1066 | if (ret) | |
1067 | return ret; | |
1068 | ||
1069 | if (ring->init) { | |
1070 | ret = ring->init(ring); | |
1071 | if (ret) | |
1072 | return ret; | |
1073 | } | |
1074 | ||
454afebd OM |
1075 | return 0; |
1076 | } | |
1077 | ||
1078 | static int logical_render_ring_init(struct drm_device *dev) | |
1079 | { | |
1080 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1081 | struct intel_engine_cs *ring = &dev_priv->ring[RCS]; | |
1082 | ||
1083 | ring->name = "render ring"; | |
1084 | ring->id = RCS; | |
1085 | ring->mmio_base = RENDER_RING_BASE; | |
1086 | ring->irq_enable_mask = | |
1087 | GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT; | |
73d477f6 OM |
1088 | ring->irq_keep_mask = |
1089 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT; | |
1090 | if (HAS_L3_DPF(dev)) | |
1091 | ring->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT; | |
454afebd | 1092 | |
9b1136d5 OM |
1093 | ring->init = gen8_init_render_ring; |
1094 | ring->cleanup = intel_fini_pipe_control; | |
e94e37ad OM |
1095 | ring->get_seqno = gen8_get_seqno; |
1096 | ring->set_seqno = gen8_set_seqno; | |
4da46e1e | 1097 | ring->emit_request = gen8_emit_request; |
4712274c | 1098 | ring->emit_flush = gen8_emit_flush_render; |
73d477f6 OM |
1099 | ring->irq_get = gen8_logical_ring_get_irq; |
1100 | ring->irq_put = gen8_logical_ring_put_irq; | |
15648585 | 1101 | ring->emit_bb_start = gen8_emit_bb_start; |
9b1136d5 | 1102 | |
454afebd OM |
1103 | return logical_ring_init(dev, ring); |
1104 | } | |
1105 | ||
1106 | static int logical_bsd_ring_init(struct drm_device *dev) | |
1107 | { | |
1108 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1109 | struct intel_engine_cs *ring = &dev_priv->ring[VCS]; | |
1110 | ||
1111 | ring->name = "bsd ring"; | |
1112 | ring->id = VCS; | |
1113 | ring->mmio_base = GEN6_BSD_RING_BASE; | |
1114 | ring->irq_enable_mask = | |
1115 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; | |
73d477f6 OM |
1116 | ring->irq_keep_mask = |
1117 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; | |
454afebd | 1118 | |
9b1136d5 | 1119 | ring->init = gen8_init_common_ring; |
e94e37ad OM |
1120 | ring->get_seqno = gen8_get_seqno; |
1121 | ring->set_seqno = gen8_set_seqno; | |
4da46e1e | 1122 | ring->emit_request = gen8_emit_request; |
4712274c | 1123 | ring->emit_flush = gen8_emit_flush; |
73d477f6 OM |
1124 | ring->irq_get = gen8_logical_ring_get_irq; |
1125 | ring->irq_put = gen8_logical_ring_put_irq; | |
15648585 | 1126 | ring->emit_bb_start = gen8_emit_bb_start; |
9b1136d5 | 1127 | |
454afebd OM |
1128 | return logical_ring_init(dev, ring); |
1129 | } | |
1130 | ||
1131 | static int logical_bsd2_ring_init(struct drm_device *dev) | |
1132 | { | |
1133 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1134 | struct intel_engine_cs *ring = &dev_priv->ring[VCS2]; | |
1135 | ||
1136 | ring->name = "bds2 ring"; | |
1137 | ring->id = VCS2; | |
1138 | ring->mmio_base = GEN8_BSD2_RING_BASE; | |
1139 | ring->irq_enable_mask = | |
1140 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; | |
73d477f6 OM |
1141 | ring->irq_keep_mask = |
1142 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; | |
454afebd | 1143 | |
9b1136d5 | 1144 | ring->init = gen8_init_common_ring; |
e94e37ad OM |
1145 | ring->get_seqno = gen8_get_seqno; |
1146 | ring->set_seqno = gen8_set_seqno; | |
4da46e1e | 1147 | ring->emit_request = gen8_emit_request; |
4712274c | 1148 | ring->emit_flush = gen8_emit_flush; |
73d477f6 OM |
1149 | ring->irq_get = gen8_logical_ring_get_irq; |
1150 | ring->irq_put = gen8_logical_ring_put_irq; | |
15648585 | 1151 | ring->emit_bb_start = gen8_emit_bb_start; |
9b1136d5 | 1152 | |
454afebd OM |
1153 | return logical_ring_init(dev, ring); |
1154 | } | |
1155 | ||
1156 | static int logical_blt_ring_init(struct drm_device *dev) | |
1157 | { | |
1158 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1159 | struct intel_engine_cs *ring = &dev_priv->ring[BCS]; | |
1160 | ||
1161 | ring->name = "blitter ring"; | |
1162 | ring->id = BCS; | |
1163 | ring->mmio_base = BLT_RING_BASE; | |
1164 | ring->irq_enable_mask = | |
1165 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; | |
73d477f6 OM |
1166 | ring->irq_keep_mask = |
1167 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT; | |
454afebd | 1168 | |
9b1136d5 | 1169 | ring->init = gen8_init_common_ring; |
e94e37ad OM |
1170 | ring->get_seqno = gen8_get_seqno; |
1171 | ring->set_seqno = gen8_set_seqno; | |
4da46e1e | 1172 | ring->emit_request = gen8_emit_request; |
4712274c | 1173 | ring->emit_flush = gen8_emit_flush; |
73d477f6 OM |
1174 | ring->irq_get = gen8_logical_ring_get_irq; |
1175 | ring->irq_put = gen8_logical_ring_put_irq; | |
15648585 | 1176 | ring->emit_bb_start = gen8_emit_bb_start; |
9b1136d5 | 1177 | |
454afebd OM |
1178 | return logical_ring_init(dev, ring); |
1179 | } | |
1180 | ||
1181 | static int logical_vebox_ring_init(struct drm_device *dev) | |
1182 | { | |
1183 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1184 | struct intel_engine_cs *ring = &dev_priv->ring[VECS]; | |
1185 | ||
1186 | ring->name = "video enhancement ring"; | |
1187 | ring->id = VECS; | |
1188 | ring->mmio_base = VEBOX_RING_BASE; | |
1189 | ring->irq_enable_mask = | |
1190 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; | |
73d477f6 OM |
1191 | ring->irq_keep_mask = |
1192 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT; | |
454afebd | 1193 | |
9b1136d5 | 1194 | ring->init = gen8_init_common_ring; |
e94e37ad OM |
1195 | ring->get_seqno = gen8_get_seqno; |
1196 | ring->set_seqno = gen8_set_seqno; | |
4da46e1e | 1197 | ring->emit_request = gen8_emit_request; |
4712274c | 1198 | ring->emit_flush = gen8_emit_flush; |
73d477f6 OM |
1199 | ring->irq_get = gen8_logical_ring_get_irq; |
1200 | ring->irq_put = gen8_logical_ring_put_irq; | |
15648585 | 1201 | ring->emit_bb_start = gen8_emit_bb_start; |
9b1136d5 | 1202 | |
454afebd OM |
1203 | return logical_ring_init(dev, ring); |
1204 | } | |
1205 | ||
1206 | int intel_logical_rings_init(struct drm_device *dev) | |
1207 | { | |
1208 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1209 | int ret; | |
1210 | ||
1211 | ret = logical_render_ring_init(dev); | |
1212 | if (ret) | |
1213 | return ret; | |
1214 | ||
1215 | if (HAS_BSD(dev)) { | |
1216 | ret = logical_bsd_ring_init(dev); | |
1217 | if (ret) | |
1218 | goto cleanup_render_ring; | |
1219 | } | |
1220 | ||
1221 | if (HAS_BLT(dev)) { | |
1222 | ret = logical_blt_ring_init(dev); | |
1223 | if (ret) | |
1224 | goto cleanup_bsd_ring; | |
1225 | } | |
1226 | ||
1227 | if (HAS_VEBOX(dev)) { | |
1228 | ret = logical_vebox_ring_init(dev); | |
1229 | if (ret) | |
1230 | goto cleanup_blt_ring; | |
1231 | } | |
1232 | ||
1233 | if (HAS_BSD2(dev)) { | |
1234 | ret = logical_bsd2_ring_init(dev); | |
1235 | if (ret) | |
1236 | goto cleanup_vebox_ring; | |
1237 | } | |
1238 | ||
1239 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); | |
1240 | if (ret) | |
1241 | goto cleanup_bsd2_ring; | |
1242 | ||
1243 | return 0; | |
1244 | ||
1245 | cleanup_bsd2_ring: | |
1246 | intel_logical_ring_cleanup(&dev_priv->ring[VCS2]); | |
1247 | cleanup_vebox_ring: | |
1248 | intel_logical_ring_cleanup(&dev_priv->ring[VECS]); | |
1249 | cleanup_blt_ring: | |
1250 | intel_logical_ring_cleanup(&dev_priv->ring[BCS]); | |
1251 | cleanup_bsd_ring: | |
1252 | intel_logical_ring_cleanup(&dev_priv->ring[VCS]); | |
1253 | cleanup_render_ring: | |
1254 | intel_logical_ring_cleanup(&dev_priv->ring[RCS]); | |
1255 | ||
1256 | return ret; | |
1257 | } | |
1258 | ||
8670d6f9 OM |
1259 | static int |
1260 | populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj, | |
1261 | struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf) | |
1262 | { | |
1263 | struct drm_i915_gem_object *ring_obj = ringbuf->obj; | |
ae6c4806 | 1264 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
8670d6f9 OM |
1265 | struct page *page; |
1266 | uint32_t *reg_state; | |
1267 | int ret; | |
1268 | ||
1269 | ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true); | |
1270 | if (ret) { | |
1271 | DRM_DEBUG_DRIVER("Could not set to CPU domain\n"); | |
1272 | return ret; | |
1273 | } | |
1274 | ||
1275 | ret = i915_gem_object_get_pages(ctx_obj); | |
1276 | if (ret) { | |
1277 | DRM_DEBUG_DRIVER("Could not get object pages\n"); | |
1278 | return ret; | |
1279 | } | |
1280 | ||
1281 | i915_gem_object_pin_pages(ctx_obj); | |
1282 | ||
1283 | /* The second page of the context object contains some fields which must | |
1284 | * be set up prior to the first execution. */ | |
1285 | page = i915_gem_object_get_page(ctx_obj, 1); | |
1286 | reg_state = kmap_atomic(page); | |
1287 | ||
1288 | /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM | |
1289 | * commands followed by (reg, value) pairs. The values we are setting here are | |
1290 | * only for the first context restore: on a subsequent save, the GPU will | |
1291 | * recreate this batchbuffer with new values (including all the missing | |
1292 | * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */ | |
1293 | if (ring->id == RCS) | |
1294 | reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(14); | |
1295 | else | |
1296 | reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(11); | |
1297 | reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED; | |
1298 | reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring); | |
1299 | reg_state[CTX_CONTEXT_CONTROL+1] = | |
1300 | _MASKED_BIT_ENABLE((1<<3) | MI_RESTORE_INHIBIT); | |
1301 | reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base); | |
1302 | reg_state[CTX_RING_HEAD+1] = 0; | |
1303 | reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base); | |
1304 | reg_state[CTX_RING_TAIL+1] = 0; | |
1305 | reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base); | |
1306 | reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(ring_obj); | |
1307 | reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base); | |
1308 | reg_state[CTX_RING_BUFFER_CONTROL+1] = | |
1309 | ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID; | |
1310 | reg_state[CTX_BB_HEAD_U] = ring->mmio_base + 0x168; | |
1311 | reg_state[CTX_BB_HEAD_U+1] = 0; | |
1312 | reg_state[CTX_BB_HEAD_L] = ring->mmio_base + 0x140; | |
1313 | reg_state[CTX_BB_HEAD_L+1] = 0; | |
1314 | reg_state[CTX_BB_STATE] = ring->mmio_base + 0x110; | |
1315 | reg_state[CTX_BB_STATE+1] = (1<<5); | |
1316 | reg_state[CTX_SECOND_BB_HEAD_U] = ring->mmio_base + 0x11c; | |
1317 | reg_state[CTX_SECOND_BB_HEAD_U+1] = 0; | |
1318 | reg_state[CTX_SECOND_BB_HEAD_L] = ring->mmio_base + 0x114; | |
1319 | reg_state[CTX_SECOND_BB_HEAD_L+1] = 0; | |
1320 | reg_state[CTX_SECOND_BB_STATE] = ring->mmio_base + 0x118; | |
1321 | reg_state[CTX_SECOND_BB_STATE+1] = 0; | |
1322 | if (ring->id == RCS) { | |
1323 | /* TODO: according to BSpec, the register state context | |
1324 | * for CHV does not have these. OTOH, these registers do | |
1325 | * exist in CHV. I'm waiting for a clarification */ | |
1326 | reg_state[CTX_BB_PER_CTX_PTR] = ring->mmio_base + 0x1c0; | |
1327 | reg_state[CTX_BB_PER_CTX_PTR+1] = 0; | |
1328 | reg_state[CTX_RCS_INDIRECT_CTX] = ring->mmio_base + 0x1c4; | |
1329 | reg_state[CTX_RCS_INDIRECT_CTX+1] = 0; | |
1330 | reg_state[CTX_RCS_INDIRECT_CTX_OFFSET] = ring->mmio_base + 0x1c8; | |
1331 | reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = 0; | |
1332 | } | |
1333 | reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9); | |
1334 | reg_state[CTX_LRI_HEADER_1] |= MI_LRI_FORCE_POSTED; | |
1335 | reg_state[CTX_CTX_TIMESTAMP] = ring->mmio_base + 0x3a8; | |
1336 | reg_state[CTX_CTX_TIMESTAMP+1] = 0; | |
1337 | reg_state[CTX_PDP3_UDW] = GEN8_RING_PDP_UDW(ring, 3); | |
1338 | reg_state[CTX_PDP3_LDW] = GEN8_RING_PDP_LDW(ring, 3); | |
1339 | reg_state[CTX_PDP2_UDW] = GEN8_RING_PDP_UDW(ring, 2); | |
1340 | reg_state[CTX_PDP2_LDW] = GEN8_RING_PDP_LDW(ring, 2); | |
1341 | reg_state[CTX_PDP1_UDW] = GEN8_RING_PDP_UDW(ring, 1); | |
1342 | reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1); | |
1343 | reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0); | |
1344 | reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0); | |
1345 | reg_state[CTX_PDP3_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[3]); | |
1346 | reg_state[CTX_PDP3_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[3]); | |
1347 | reg_state[CTX_PDP2_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[2]); | |
1348 | reg_state[CTX_PDP2_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[2]); | |
1349 | reg_state[CTX_PDP1_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[1]); | |
1350 | reg_state[CTX_PDP1_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[1]); | |
1351 | reg_state[CTX_PDP0_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[0]); | |
1352 | reg_state[CTX_PDP0_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[0]); | |
1353 | if (ring->id == RCS) { | |
1354 | reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1); | |
1355 | reg_state[CTX_R_PWR_CLK_STATE] = 0x20c8; | |
1356 | reg_state[CTX_R_PWR_CLK_STATE+1] = 0; | |
1357 | } | |
1358 | ||
1359 | kunmap_atomic(reg_state); | |
1360 | ||
1361 | ctx_obj->dirty = 1; | |
1362 | set_page_dirty(page); | |
1363 | i915_gem_object_unpin_pages(ctx_obj); | |
1364 | ||
1365 | return 0; | |
1366 | } | |
1367 | ||
ede7d42b OM |
1368 | void intel_lr_context_free(struct intel_context *ctx) |
1369 | { | |
8c857917 OM |
1370 | int i; |
1371 | ||
1372 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
1373 | struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state; | |
84c2377f OM |
1374 | struct intel_ringbuffer *ringbuf = ctx->engine[i].ringbuf; |
1375 | ||
8c857917 | 1376 | if (ctx_obj) { |
84c2377f OM |
1377 | intel_destroy_ringbuffer_obj(ringbuf); |
1378 | kfree(ringbuf); | |
8c857917 OM |
1379 | i915_gem_object_ggtt_unpin(ctx_obj); |
1380 | drm_gem_object_unreference(&ctx_obj->base); | |
1381 | } | |
1382 | } | |
1383 | } | |
1384 | ||
1385 | static uint32_t get_lr_context_size(struct intel_engine_cs *ring) | |
1386 | { | |
1387 | int ret = 0; | |
1388 | ||
1389 | WARN_ON(INTEL_INFO(ring->dev)->gen != 8); | |
1390 | ||
1391 | switch (ring->id) { | |
1392 | case RCS: | |
1393 | ret = GEN8_LR_CONTEXT_RENDER_SIZE; | |
1394 | break; | |
1395 | case VCS: | |
1396 | case BCS: | |
1397 | case VECS: | |
1398 | case VCS2: | |
1399 | ret = GEN8_LR_CONTEXT_OTHER_SIZE; | |
1400 | break; | |
1401 | } | |
1402 | ||
1403 | return ret; | |
ede7d42b OM |
1404 | } |
1405 | ||
1406 | int intel_lr_context_deferred_create(struct intel_context *ctx, | |
1407 | struct intel_engine_cs *ring) | |
1408 | { | |
8c857917 OM |
1409 | struct drm_device *dev = ring->dev; |
1410 | struct drm_i915_gem_object *ctx_obj; | |
1411 | uint32_t context_size; | |
84c2377f | 1412 | struct intel_ringbuffer *ringbuf; |
8c857917 OM |
1413 | int ret; |
1414 | ||
ede7d42b | 1415 | WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL); |
48d82387 OM |
1416 | if (ctx->engine[ring->id].state) |
1417 | return 0; | |
ede7d42b | 1418 | |
8c857917 OM |
1419 | context_size = round_up(get_lr_context_size(ring), 4096); |
1420 | ||
1421 | ctx_obj = i915_gem_alloc_context_obj(dev, context_size); | |
1422 | if (IS_ERR(ctx_obj)) { | |
1423 | ret = PTR_ERR(ctx_obj); | |
1424 | DRM_DEBUG_DRIVER("Alloc LRC backing obj failed: %d\n", ret); | |
1425 | return ret; | |
1426 | } | |
1427 | ||
1428 | ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN, 0); | |
1429 | if (ret) { | |
1430 | DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n", ret); | |
1431 | drm_gem_object_unreference(&ctx_obj->base); | |
1432 | return ret; | |
1433 | } | |
1434 | ||
84c2377f OM |
1435 | ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL); |
1436 | if (!ringbuf) { | |
1437 | DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n", | |
1438 | ring->name); | |
1439 | i915_gem_object_ggtt_unpin(ctx_obj); | |
1440 | drm_gem_object_unreference(&ctx_obj->base); | |
1441 | ret = -ENOMEM; | |
1442 | return ret; | |
1443 | } | |
1444 | ||
0c7dd53b | 1445 | ringbuf->ring = ring; |
582d67f0 OM |
1446 | ringbuf->FIXME_lrc_ctx = ctx; |
1447 | ||
84c2377f OM |
1448 | ringbuf->size = 32 * PAGE_SIZE; |
1449 | ringbuf->effective_size = ringbuf->size; | |
1450 | ringbuf->head = 0; | |
1451 | ringbuf->tail = 0; | |
1452 | ringbuf->space = ringbuf->size; | |
1453 | ringbuf->last_retired_head = -1; | |
1454 | ||
1455 | /* TODO: For now we put this in the mappable region so that we can reuse | |
1456 | * the existing ringbuffer code which ioremaps it. When we start | |
1457 | * creating many contexts, this will no longer work and we must switch | |
1458 | * to a kmapish interface. | |
1459 | */ | |
1460 | ret = intel_alloc_ringbuffer_obj(dev, ringbuf); | |
1461 | if (ret) { | |
1462 | DRM_DEBUG_DRIVER("Failed to allocate ringbuffer obj %s: %d\n", | |
1463 | ring->name, ret); | |
8670d6f9 OM |
1464 | goto error; |
1465 | } | |
1466 | ||
1467 | ret = populate_lr_context(ctx, ctx_obj, ring, ringbuf); | |
1468 | if (ret) { | |
1469 | DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret); | |
1470 | intel_destroy_ringbuffer_obj(ringbuf); | |
1471 | goto error; | |
84c2377f OM |
1472 | } |
1473 | ||
1474 | ctx->engine[ring->id].ringbuf = ringbuf; | |
8c857917 | 1475 | ctx->engine[ring->id].state = ctx_obj; |
ede7d42b OM |
1476 | |
1477 | return 0; | |
8670d6f9 OM |
1478 | |
1479 | error: | |
1480 | kfree(ringbuf); | |
1481 | i915_gem_object_ggtt_unpin(ctx_obj); | |
1482 | drm_gem_object_unreference(&ctx_obj->base); | |
1483 | return ret; | |
ede7d42b | 1484 | } |