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gpu: Add export.h as required to drivers/gpu files.
[mirror_ubuntu-disco-kernel.git] / drivers / gpu / drm / i915 / intel_sdvo.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
79e53945 30#include <linux/delay.h>
2d1a8a48 31#include <linux/export.h>
79e53945
JB		 32#include "drmP.h"
33#include "drm.h"
34#include "drm_crtc.h"
2b8d33f7 35#include "drm_edid.h"
ea5b213a 36#include "intel_drv.h"
79e53945
JB		 37#include "i915_drm.h"
38#include "i915_drv.h"
39#include "intel_sdvo_regs.h"
40
14571b4c
ZW		 41#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
42#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
43#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
44#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0)
45
46#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
0206e353 47 SDVO_TV_MASK)
14571b4c
ZW		 48
49#define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
13946743 50#define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
14571b4c 51#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
32aad86f 52#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
14571b4c 53
79e53945 54
2e88e40b 55static const char *tv_format_names[] = {
ce6feabd
ZY		 56 "NTSC_M" , "NTSC_J" , "NTSC_443",
57 "PAL_B" , "PAL_D" , "PAL_G" ,
58 "PAL_H" , "PAL_I" , "PAL_M" ,
59 "PAL_N" , "PAL_NC" , "PAL_60" ,
60 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
61 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
62 "SECAM_60"
63};
64
65#define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
66
ea5b213a
CW		 67struct intel_sdvo {
68 struct intel_encoder base;
69
f899fc64 70 struct i2c_adapter *i2c;
f9c10a9b 71 u8 slave_addr;
e2f0ba97 72
e957d772
CW		 73 struct i2c_adapter ddc;
74
e2f0ba97 75 /* Register for the SDVO device: SDVOB or SDVOC */
c751ce4f 76 int sdvo_reg;
79e53945 77
e2f0ba97
JB		 78 /* Active outputs controlled by this SDVO output */
79 uint16_t controlled_output;
79e53945 80
e2f0ba97
JB		 81 /*
82 * Capabilities of the SDVO device returned by
83 * i830_sdvo_get_capabilities()
84 */
79e53945 85 struct intel_sdvo_caps caps;
e2f0ba97
JB		 86
87 /* Pixel clock limitations reported by the SDVO device, in kHz */
79e53945
JB		 88 int pixel_clock_min, pixel_clock_max;
89
fb7a46f3 90 /*
91 * For multiple function SDVO device,
92 * this is for current attached outputs.
93 */
94 uint16_t attached_output;
95
cc68c81a
SF		 96 /*
97 * Hotplug activation bits for this device
98 */
99 uint8_t hotplug_active[2];
100
e953fd7b
CW		 101 /**
102 * This is used to select the color range of RBG outputs in HDMI mode.
103 * It is only valid when using TMDS encoding and 8 bit per color mode.
104 */
105 uint32_t color_range;
106
e2f0ba97
JB		 107 /**
108 * This is set if we're going to treat the device as TV-out.
109 *
110 * While we have these nice friendly flags for output types that ought
111 * to decide this for us, the S-Video output on our HDMI+S-Video card
112 * shows up as RGB1 (VGA).
113 */
114 bool is_tv;
115
ce6feabd 116 /* This is for current tv format name */
40039750 117 int tv_format_index;
ce6feabd 118
e2f0ba97
JB		 119 /**
120 * This is set if we treat the device as HDMI, instead of DVI.
121 */
122 bool is_hdmi;
da79de97
CW		 123 bool has_hdmi_monitor;
124 bool has_hdmi_audio;
12682a97 125
7086c87f 126 /**
6c9547ff
CW		 127 * This is set if we detect output of sdvo device as LVDS and
128 * have a valid fixed mode to use with the panel.
7086c87f
ML		 129 */
130 bool is_lvds;
e2f0ba97 131
12682a97 132 /**
133 * This is sdvo fixed pannel mode pointer
134 */
135 struct drm_display_mode *sdvo_lvds_fixed_mode;
136
c751ce4f 137 /* DDC bus used by this SDVO encoder */
e2f0ba97
JB		 138 uint8_t ddc_bus;
139
6c9547ff
CW		 140 /* Input timings for adjusted_mode */
141 struct intel_sdvo_dtd input_dtd;
14571b4c
ZW		 142};
143
144struct intel_sdvo_connector {
615fb93f
CW		 145 struct intel_connector base;
146
14571b4c
ZW		 147 /* Mark the type of connector */
148 uint16_t output_flag;
149
7f36e7ed
CW		 150 int force_audio;
151
14571b4c 152 /* This contains all current supported TV format */
40039750 153 u8 tv_format_supported[TV_FORMAT_NUM];
14571b4c 154 int format_supported_num;
c5521706 155 struct drm_property *tv_format;
14571b4c 156
b9219c5e 157 /* add the property for the SDVO-TV */
c5521706
CW		 158 struct drm_property *left;
159 struct drm_property *right;
160 struct drm_property *top;
161 struct drm_property *bottom;
162 struct drm_property *hpos;
163 struct drm_property *vpos;
164 struct drm_property *contrast;
165 struct drm_property *saturation;
166 struct drm_property *hue;
167 struct drm_property *sharpness;
168 struct drm_property *flicker_filter;
169 struct drm_property *flicker_filter_adaptive;
170 struct drm_property *flicker_filter_2d;
171 struct drm_property *tv_chroma_filter;
172 struct drm_property *tv_luma_filter;
e044218a 173 struct drm_property *dot_crawl;
b9219c5e
ZY		 174
175 /* add the property for the SDVO-TV/LVDS */
c5521706 176 struct drm_property *brightness;
b9219c5e
ZY		 177
178 /* Add variable to record current setting for the above property */
179 u32 left_margin, right_margin, top_margin, bottom_margin;
c5521706 180
b9219c5e
ZY		 181 /* this is to get the range of margin.*/
182 u32 max_hscan, max_vscan;
183 u32 max_hpos, cur_hpos;
184 u32 max_vpos, cur_vpos;
185 u32 cur_brightness, max_brightness;
186 u32 cur_contrast, max_contrast;
187 u32 cur_saturation, max_saturation;
188 u32 cur_hue, max_hue;
c5521706
CW		 189 u32 cur_sharpness, max_sharpness;
190 u32 cur_flicker_filter, max_flicker_filter;
191 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
192 u32 cur_flicker_filter_2d, max_flicker_filter_2d;
193 u32 cur_tv_chroma_filter, max_tv_chroma_filter;
194 u32 cur_tv_luma_filter, max_tv_luma_filter;
e044218a 195 u32 cur_dot_crawl, max_dot_crawl;
79e53945
JB		 196};
197
890f3359 198static struct intel_sdvo *to_intel_sdvo(struct drm_encoder *encoder)
ea5b213a 199{
4ef69c7a 200 return container_of(encoder, struct intel_sdvo, base.base);
ea5b213a
CW		 201}
202
df0e9248
CW		 203static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
204{
205 return container_of(intel_attached_encoder(connector),
206 struct intel_sdvo, base);
207}
208
615fb93f
CW		 209static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
210{
211 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
212}
213
fb7a46f3 214static bool
ea5b213a 215intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
32aad86f
CW		 216static bool
217intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
218 struct intel_sdvo_connector *intel_sdvo_connector,
219 int type);
220static bool
221intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
222 struct intel_sdvo_connector *intel_sdvo_connector);
fb7a46f3 223
79e53945
JB		 224/**
225 * Writes the SDVOB or SDVOC with the given value, but always writes both
226 * SDVOB and SDVOC to work around apparent hardware issues (according to
227 * comments in the BIOS).
228 */
ea5b213a 229static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
79e53945 230{
4ef69c7a 231 struct drm_device *dev = intel_sdvo->base.base.dev;
79e53945 232 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 233 u32 bval = val, cval = val;
234 int i;
235
ea5b213a
CW		 236 if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
237 I915_WRITE(intel_sdvo->sdvo_reg, val);
238 I915_READ(intel_sdvo->sdvo_reg);
461ed3ca
ZY		 239 return;
240 }
241
ea5b213a 242 if (intel_sdvo->sdvo_reg == SDVOB) {
79e53945
JB		 243 cval = I915_READ(SDVOC);
244 } else {
245 bval = I915_READ(SDVOB);
246 }
247 /*
248 * Write the registers twice for luck. Sometimes,
249 * writing them only once doesn't appear to 'stick'.
250 * The BIOS does this too. Yay, magic
251 */
252 for (i = 0; i < 2; i++)
253 {
254 I915_WRITE(SDVOB, bval);
255 I915_READ(SDVOB);
256 I915_WRITE(SDVOC, cval);
257 I915_READ(SDVOC);
258 }
259}
260
32aad86f 261static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
79e53945 262{
79e53945
JB		 263 struct i2c_msg msgs[] = {
264 {
e957d772 265 .addr = intel_sdvo->slave_addr,
79e53945
JB		 266 .flags = 0,
267 .len = 1,
e957d772 268 .buf = &addr,
79e53945
JB		 269 },
270 {
e957d772 271 .addr = intel_sdvo->slave_addr,
79e53945
JB		 272 .flags = I2C_M_RD,
273 .len = 1,
e957d772 274 .buf = ch,
79e53945
JB		 275 }
276 };
32aad86f 277 int ret;
79e53945 278
f899fc64 279 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
79e53945 280 return true;
79e53945 281
8a4c47f3 282 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
79e53945
JB		 283 return false;
284}
285
79e53945
JB		 286#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
287/** Mapping of command numbers to names, for debug output */
005568be 288static const struct _sdvo_cmd_name {
e2f0ba97 289 u8 cmd;
2e88e40b 290 const char *name;
79e53945 291} sdvo_cmd_names[] = {
0206e353
AJ		 292 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
293 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
294 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
295 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
296 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
297 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
335
336 /* Add the op code for SDVO enhancements */
337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
381
382 /* HDMI op code */
383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
388 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
400 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
79e53945
JB		 403};
404
461ed3ca 405#define IS_SDVOB(reg) (reg == SDVOB || reg == PCH_SDVOB)
ea5b213a 406#define SDVO_NAME(svdo) (IS_SDVOB((svdo)->sdvo_reg) ? "SDVOB" : "SDVOC")
79e53945 407
ea5b213a 408static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
32aad86f 409 const void *args, int args_len)
79e53945 410{
79e53945
JB		 411 int i;
412
8a4c47f3 413 DRM_DEBUG_KMS("%s: W: %02X ",
ea5b213a 414 SDVO_NAME(intel_sdvo), cmd);
79e53945 415 for (i = 0; i < args_len; i++)
342dc382 416 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
79e53945 417 for (; i < 8; i++)
342dc382 418 DRM_LOG_KMS(" ");
04ad327f 419 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
79e53945 420 if (cmd == sdvo_cmd_names[i].cmd) {
342dc382 421 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
79e53945
JB		 422 break;
423 }
424 }
04ad327f 425 if (i == ARRAY_SIZE(sdvo_cmd_names))
342dc382 426 DRM_LOG_KMS("(%02X)", cmd);
427 DRM_LOG_KMS("\n");
79e53945 428}
79e53945 429
e957d772
CW		 430static const char *cmd_status_names[] = {
431 "Power on",
432 "Success",
433 "Not supported",
434 "Invalid arg",
435 "Pending",
436 "Target not specified",
437 "Scaling not supported"
438};
439
32aad86f
CW		 440static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
441 const void *args, int args_len)
79e53945 442{
e957d772
CW		 443 u8 buf[args_len*2 + 2], status;
444 struct i2c_msg msgs[args_len + 3];
445 int i, ret;
79e53945 446
ea5b213a 447 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
79e53945
JB		 448
449 for (i = 0; i < args_len; i++) {
e957d772
CW		 450 msgs[i].addr = intel_sdvo->slave_addr;
451 msgs[i].flags = 0;
452 msgs[i].len = 2;
453 msgs[i].buf = buf + 2 *i;
454 buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
455 buf[2*i + 1] = ((u8*)args)[i];
456 }
457 msgs[i].addr = intel_sdvo->slave_addr;
458 msgs[i].flags = 0;
459 msgs[i].len = 2;
460 msgs[i].buf = buf + 2*i;
461 buf[2*i + 0] = SDVO_I2C_OPCODE;
462 buf[2*i + 1] = cmd;
463
464 /* the following two are to read the response */
465 status = SDVO_I2C_CMD_STATUS;
466 msgs[i+1].addr = intel_sdvo->slave_addr;
467 msgs[i+1].flags = 0;
468 msgs[i+1].len = 1;
469 msgs[i+1].buf = &status;
470
471 msgs[i+2].addr = intel_sdvo->slave_addr;
472 msgs[i+2].flags = I2C_M_RD;
473 msgs[i+2].len = 1;
474 msgs[i+2].buf = &status;
475
476 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
477 if (ret < 0) {
478 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
479 return false;
480 }
481 if (ret != i+3) {
482 /* failure in I2C transfer */
483 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
484 return false;
485 }
486
e957d772 487 return true;
79e53945
JB		 488}
489
b5c616a7
CW		 490static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
491 void *response, int response_len)
79e53945 492{
b5c616a7
CW		 493 u8 retry = 5;
494 u8 status;
33b52961 495 int i;
79e53945 496
d121a5d2
CW		 497 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
498
b5c616a7
CW		 499 /*
500 * The documentation states that all commands will be
501 * processed within 15µs, and that we need only poll
502 * the status byte a maximum of 3 times in order for the
503 * command to be complete.
504 *
505 * Check 5 times in case the hardware failed to read the docs.
506 */
d121a5d2
CW		 507 if (!intel_sdvo_read_byte(intel_sdvo,
508 SDVO_I2C_CMD_STATUS,
509 &status))
510 goto log_fail;
511
512 while (status == SDVO_CMD_STATUS_PENDING && retry--) {
513 udelay(15);
b5c616a7
CW		 514 if (!intel_sdvo_read_byte(intel_sdvo,
515 SDVO_I2C_CMD_STATUS,
516 &status))
d121a5d2
CW		 517 goto log_fail;
518 }
b5c616a7 519
79e53945 520 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
342dc382 521 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
79e53945 522 else
342dc382 523 DRM_LOG_KMS("(??? %d)", status);
79e53945 524
b5c616a7
CW		 525 if (status != SDVO_CMD_STATUS_SUCCESS)
526 goto log_fail;
79e53945 527
b5c616a7
CW		 528 /* Read the command response */
529 for (i = 0; i < response_len; i++) {
530 if (!intel_sdvo_read_byte(intel_sdvo,
531 SDVO_I2C_RETURN_0 + i,
532 &((u8 *)response)[i]))
533 goto log_fail;
e957d772 534 DRM_LOG_KMS(" %02X", ((u8 *)response)[i]);
b5c616a7 535 }
b5c616a7 536 DRM_LOG_KMS("\n");
b5c616a7 537 return true;
79e53945 538
b5c616a7 539log_fail:
d121a5d2 540 DRM_LOG_KMS("... failed\n");
b5c616a7 541 return false;
79e53945
JB		 542}
543
b358d0a6 544static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
79e53945
JB		 545{
546 if (mode->clock >= 100000)
547 return 1;
548 else if (mode->clock >= 50000)
549 return 2;
550 else
551 return 4;
552}
553
e957d772
CW		 554static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
555 u8 ddc_bus)
79e53945 556{
d121a5d2 557 /* This must be the immediately preceding write before the i2c xfer */
e957d772
CW		 558 return intel_sdvo_write_cmd(intel_sdvo,
559 SDVO_CMD_SET_CONTROL_BUS_SWITCH,
560 &ddc_bus, 1);
79e53945
JB		 561}
562
32aad86f 563static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
79e53945 564{
d121a5d2
CW		 565 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
566 return false;
567
568 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
32aad86f 569}
79e53945 570
32aad86f
CW		 571static bool
572intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
573{
574 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
575 return false;
79e53945 576
32aad86f
CW		 577 return intel_sdvo_read_response(intel_sdvo, value, len);
578}
79e53945 579
32aad86f
CW		 580static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
581{
582 struct intel_sdvo_set_target_input_args targets = {0};
583 return intel_sdvo_set_value(intel_sdvo,
584 SDVO_CMD_SET_TARGET_INPUT,
585 &targets, sizeof(targets));
79e53945
JB		 586}
587
588/**
589 * Return whether each input is trained.
590 *
591 * This function is making an assumption about the layout of the response,
592 * which should be checked against the docs.
593 */
ea5b213a 594static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
79e53945
JB		 595{
596 struct intel_sdvo_get_trained_inputs_response response;
79e53945 597
1a3665c8 598 BUILD_BUG_ON(sizeof(response) != 1);
32aad86f
CW		 599 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
600 &response, sizeof(response)))
79e53945
JB		 601 return false;
602
603 *input_1 = response.input0_trained;
604 *input_2 = response.input1_trained;
605 return true;
606}
607
ea5b213a 608static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
79e53945
JB		 609 u16 outputs)
610{
32aad86f
CW		 611 return intel_sdvo_set_value(intel_sdvo,
612 SDVO_CMD_SET_ACTIVE_OUTPUTS,
613 &outputs, sizeof(outputs));
79e53945
JB		 614}
615
ea5b213a 616static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
79e53945
JB		 617 int mode)
618{
32aad86f 619 u8 state = SDVO_ENCODER_STATE_ON;
79e53945
JB		 620
621 switch (mode) {
622 case DRM_MODE_DPMS_ON:
623 state = SDVO_ENCODER_STATE_ON;
624 break;
625 case DRM_MODE_DPMS_STANDBY:
626 state = SDVO_ENCODER_STATE_STANDBY;
627 break;
628 case DRM_MODE_DPMS_SUSPEND:
629 state = SDVO_ENCODER_STATE_SUSPEND;
630 break;
631 case DRM_MODE_DPMS_OFF:
632 state = SDVO_ENCODER_STATE_OFF;
633 break;
634 }
635
32aad86f
CW		 636 return intel_sdvo_set_value(intel_sdvo,
637 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
79e53945
JB		 638}
639
ea5b213a 640static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
79e53945
JB		 641 int *clock_min,
642 int *clock_max)
643{
644 struct intel_sdvo_pixel_clock_range clocks;
79e53945 645
1a3665c8 646 BUILD_BUG_ON(sizeof(clocks) != 4);
32aad86f
CW		 647 if (!intel_sdvo_get_value(intel_sdvo,
648 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
649 &clocks, sizeof(clocks)))
79e53945
JB		 650 return false;
651
652 /* Convert the values from units of 10 kHz to kHz. */
653 *clock_min = clocks.min * 10;
654 *clock_max = clocks.max * 10;
79e53945
JB		 655 return true;
656}
657
ea5b213a 658static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
79e53945
JB		 659 u16 outputs)
660{
32aad86f
CW		 661 return intel_sdvo_set_value(intel_sdvo,
662 SDVO_CMD_SET_TARGET_OUTPUT,
663 &outputs, sizeof(outputs));
79e53945
JB		 664}
665
ea5b213a 666static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
79e53945
JB		 667 struct intel_sdvo_dtd *dtd)
668{
32aad86f
CW		 669 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
670 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
79e53945
JB		 671}
672
ea5b213a 673static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 674 struct intel_sdvo_dtd *dtd)
675{
ea5b213a 676 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 677 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
678}
679
ea5b213a 680static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 681 struct intel_sdvo_dtd *dtd)
682{
ea5b213a 683 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 684 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
685}
686
e2f0ba97 687static bool
ea5b213a 688intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 689 uint16_t clock,
690 uint16_t width,
691 uint16_t height)
692{
693 struct intel_sdvo_preferred_input_timing_args args;
e2f0ba97 694
e642c6f1 695 memset(&args, 0, sizeof(args));
e2f0ba97
JB		 696 args.clock = clock;
697 args.width = width;
698 args.height = height;
e642c6f1 699 args.interlace = 0;
12682a97 700
ea5b213a
CW		 701 if (intel_sdvo->is_lvds &&
702 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
703 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
12682a97 704 args.scaled = 1;
705
32aad86f
CW		 706 return intel_sdvo_set_value(intel_sdvo,
707 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
708 &args, sizeof(args));
e2f0ba97
JB		 709}
710
ea5b213a 711static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 712 struct intel_sdvo_dtd *dtd)
713{
1a3665c8
CW		 714 BUILD_BUG_ON(sizeof(dtd->part1) != 8);
715 BUILD_BUG_ON(sizeof(dtd->part2) != 8);
32aad86f
CW		 716 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
717 &dtd->part1, sizeof(dtd->part1)) &&
718 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
719 &dtd->part2, sizeof(dtd->part2));
e2f0ba97 720}
79e53945 721
ea5b213a 722static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
79e53945 723{
32aad86f 724 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
79e53945
JB		 725}
726
e2f0ba97 727static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
32aad86f 728 const struct drm_display_mode *mode)
79e53945 729{
e2f0ba97
JB		 730 uint16_t width, height;
731 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
732 uint16_t h_sync_offset, v_sync_offset;
79e53945
JB		 733
734 width = mode->crtc_hdisplay;
735 height = mode->crtc_vdisplay;
736
737 /* do some mode translations */
738 h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
739 h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
740
741 v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
742 v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
743
744 h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
745 v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
746
e2f0ba97
JB		 747 dtd->part1.clock = mode->clock / 10;
748 dtd->part1.h_active = width & 0xff;
749 dtd->part1.h_blank = h_blank_len & 0xff;
750 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
79e53945 751 ((h_blank_len >> 8) & 0xf);
e2f0ba97
JB		 752 dtd->part1.v_active = height & 0xff;
753 dtd->part1.v_blank = v_blank_len & 0xff;
754 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
79e53945
JB		 755 ((v_blank_len >> 8) & 0xf);
756
171a9e96 757 dtd->part2.h_sync_off = h_sync_offset & 0xff;
e2f0ba97
JB		 758 dtd->part2.h_sync_width = h_sync_len & 0xff;
759 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
79e53945 760 (v_sync_len & 0xf);
e2f0ba97 761 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
79e53945
JB		 762 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
763 ((v_sync_len & 0x30) >> 4);
764
e2f0ba97 765 dtd->part2.dtd_flags = 0x18;
79e53945 766 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
e2f0ba97 767 dtd->part2.dtd_flags |= 0x2;
79e53945 768 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
e2f0ba97
JB		 769 dtd->part2.dtd_flags |= 0x4;
770
771 dtd->part2.sdvo_flags = 0;
772 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
773 dtd->part2.reserved = 0;
774}
775
776static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
32aad86f 777 const struct intel_sdvo_dtd *dtd)
e2f0ba97 778{
e2f0ba97
JB		 779 mode->hdisplay = dtd->part1.h_active;
780 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
781 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
171a9e96 782 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
e2f0ba97
JB		 783 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
784 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
785 mode->htotal = mode->hdisplay + dtd->part1.h_blank;
786 mode->htotal += (dtd->part1.h_high & 0xf) << 8;
787
788 mode->vdisplay = dtd->part1.v_active;
789 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
790 mode->vsync_start = mode->vdisplay;
791 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
171a9e96 792 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
e2f0ba97
JB		 793 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
794 mode->vsync_end = mode->vsync_start +
795 (dtd->part2.v_sync_off_width & 0xf);
796 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
797 mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
798 mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
799
800 mode->clock = dtd->part1.clock * 10;
801
171a9e96 802 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
e2f0ba97
JB		 803 if (dtd->part2.dtd_flags & 0x2)
804 mode->flags |= DRM_MODE_FLAG_PHSYNC;
805 if (dtd->part2.dtd_flags & 0x4)
806 mode->flags |= DRM_MODE_FLAG_PVSYNC;
807}
808
e27d8538 809static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
e2f0ba97 810{
e27d8538 811 struct intel_sdvo_encode encode;
e2f0ba97 812
1a3665c8 813 BUILD_BUG_ON(sizeof(encode) != 2);
e27d8538
CW		 814 return intel_sdvo_get_value(intel_sdvo,
815 SDVO_CMD_GET_SUPP_ENCODE,
816 &encode, sizeof(encode));
e2f0ba97
JB		 817}
818
ea5b213a 819static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
c751ce4f 820 uint8_t mode)
e2f0ba97 821{
32aad86f 822 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
e2f0ba97
JB		 823}
824
ea5b213a 825static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 826 uint8_t mode)
827{
32aad86f 828 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
e2f0ba97
JB		 829}
830
831#if 0
ea5b213a 832static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 833{
834 int i, j;
835 uint8_t set_buf_index[2];
836 uint8_t av_split;
837 uint8_t buf_size;
838 uint8_t buf[48];
839 uint8_t *pos;
840
32aad86f 841 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
e2f0ba97
JB		 842
843 for (i = 0; i <= av_split; i++) {
844 set_buf_index[0] = i; set_buf_index[1] = 0;
c751ce4f 845 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
e2f0ba97 846 set_buf_index, 2);
c751ce4f
EA		 847 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
848 intel_sdvo_read_response(encoder, &buf_size, 1);
e2f0ba97
JB		 849
850 pos = buf;
851 for (j = 0; j <= buf_size; j += 8) {
c751ce4f 852 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
e2f0ba97 853 NULL, 0);
c751ce4f 854 intel_sdvo_read_response(encoder, pos, 8);
e2f0ba97
JB		 855 pos += 8;
856 }
857 }
858}
859#endif
860
3c17fe4b 861static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 862{
863 struct dip_infoframe avi_if = {
864 .type = DIP_TYPE_AVI,
3c17fe4b 865 .ver = DIP_VERSION_AVI,
e2f0ba97
JB		 866 .len = DIP_LEN_AVI,
867 };
3c17fe4b
DH		 868 uint8_t tx_rate = SDVO_HBUF_TX_VSYNC;
869 uint8_t set_buf_index[2] = { 1, 0 };
870 uint64_t *data = (uint64_t *)&avi_if;
871 unsigned i;
872
873 intel_dip_infoframe_csum(&avi_if);
874
d121a5d2
CW		 875 if (!intel_sdvo_set_value(intel_sdvo,
876 SDVO_CMD_SET_HBUF_INDEX,
3c17fe4b
DH		 877 set_buf_index, 2))
878 return false;
879
880 for (i = 0; i < sizeof(avi_if); i += 8) {
d121a5d2
CW		 881 if (!intel_sdvo_set_value(intel_sdvo,
882 SDVO_CMD_SET_HBUF_DATA,
3c17fe4b
DH		 883 data, 8))
884 return false;
885 data++;
886 }
e2f0ba97 887
d121a5d2
CW		 888 return intel_sdvo_set_value(intel_sdvo,
889 SDVO_CMD_SET_HBUF_TXRATE,
3c17fe4b 890 &tx_rate, 1);
e2f0ba97
JB		 891}
892
32aad86f 893static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
7026d4ac 894{
ce6feabd 895 struct intel_sdvo_tv_format format;
40039750 896 uint32_t format_map;
ce6feabd 897
40039750 898 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 899 memset(&format, 0, sizeof(format));
32aad86f 900 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
ce6feabd 901
32aad86f
CW		 902 BUILD_BUG_ON(sizeof(format) != 6);
903 return intel_sdvo_set_value(intel_sdvo,
904 SDVO_CMD_SET_TV_FORMAT,
905 &format, sizeof(format));
7026d4ac
ZW		 906}
907
32aad86f
CW		 908static bool
909intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
910 struct drm_display_mode *mode)
e2f0ba97 911{
32aad86f 912 struct intel_sdvo_dtd output_dtd;
79e53945 913
32aad86f
CW		 914 if (!intel_sdvo_set_target_output(intel_sdvo,
915 intel_sdvo->attached_output))
916 return false;
e2f0ba97 917
32aad86f
CW		 918 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
919 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
920 return false;
e2f0ba97 921
32aad86f
CW		 922 return true;
923}
924
925static bool
926intel_sdvo_set_input_timings_for_mode(struct intel_sdvo *intel_sdvo,
927 struct drm_display_mode *mode,
928 struct drm_display_mode *adjusted_mode)
929{
32aad86f
CW		 930 /* Reset the input timing to the screen. Assume always input 0. */
931 if (!intel_sdvo_set_target_input(intel_sdvo))
932 return false;
e2f0ba97 933
32aad86f
CW		 934 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
935 mode->clock / 10,
936 mode->hdisplay,
937 mode->vdisplay))
938 return false;
e2f0ba97 939
32aad86f 940 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
6c9547ff 941 &intel_sdvo->input_dtd))
32aad86f 942 return false;
e2f0ba97 943
6c9547ff 944 intel_sdvo_get_mode_from_dtd(adjusted_mode, &intel_sdvo->input_dtd);
79e53945 945
32aad86f 946 drm_mode_set_crtcinfo(adjusted_mode, 0);
32aad86f
CW		 947 return true;
948}
12682a97 949
32aad86f
CW		 950static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
951 struct drm_display_mode *mode,
952 struct drm_display_mode *adjusted_mode)
953{
890f3359 954 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
6c9547ff 955 int multiplier;
12682a97 956
32aad86f
CW		 957 /* We need to construct preferred input timings based on our
958 * output timings. To do that, we have to set the output
959 * timings, even though this isn't really the right place in
960 * the sequence to do it. Oh well.
961 */
962 if (intel_sdvo->is_tv) {
963 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
964 return false;
12682a97 965
c74696b9
PR		 966 (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo,
967 mode,
968 adjusted_mode);
ea5b213a 969 } else if (intel_sdvo->is_lvds) {
32aad86f 970 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
6c9547ff 971 intel_sdvo->sdvo_lvds_fixed_mode))
e2f0ba97 972 return false;
12682a97 973
c74696b9
PR		 974 (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo,
975 mode,
976 adjusted_mode);
e2f0ba97 977 }
32aad86f
CW		 978
979 /* Make the CRTC code factor in the SDVO pixel multiplier. The
6c9547ff 980 * SDVO device will factor out the multiplier during mode_set.
32aad86f 981 */
6c9547ff
CW		 982 multiplier = intel_sdvo_get_pixel_multiplier(adjusted_mode);
983 intel_mode_set_pixel_multiplier(adjusted_mode, multiplier);
32aad86f 984
e2f0ba97
JB		 985 return true;
986}
987
988static void intel_sdvo_mode_set(struct drm_encoder *encoder,
989 struct drm_display_mode *mode,
990 struct drm_display_mode *adjusted_mode)
991{
992 struct drm_device *dev = encoder->dev;
993 struct drm_i915_private *dev_priv = dev->dev_private;
994 struct drm_crtc *crtc = encoder->crtc;
995 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
890f3359 996 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
6c9547ff 997 u32 sdvox;
e2f0ba97
JB		 998 struct intel_sdvo_in_out_map in_out;
999 struct intel_sdvo_dtd input_dtd;
6c9547ff
CW		 1000 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
1001 int rate;
e2f0ba97
JB		 1002
1003 if (!mode)
1004 return;
1005
1006 /* First, set the input mapping for the first input to our controlled
1007 * output. This is only correct if we're a single-input device, in
1008 * which case the first input is the output from the appropriate SDVO
1009 * channel on the motherboard. In a two-input device, the first input
1010 * will be SDVOB and the second SDVOC.
1011 */
ea5b213a 1012 in_out.in0 = intel_sdvo->attached_output;
e2f0ba97
JB		 1013 in_out.in1 = 0;
1014
c74696b9
PR		 1015 intel_sdvo_set_value(intel_sdvo,
1016 SDVO_CMD_SET_IN_OUT_MAP,
1017 &in_out, sizeof(in_out));
e2f0ba97 1018
6c9547ff
CW		 1019 /* Set the output timings to the screen */
1020 if (!intel_sdvo_set_target_output(intel_sdvo,
1021 intel_sdvo->attached_output))
1022 return;
e2f0ba97 1023
7026d4ac 1024 /* We have tried to get input timing in mode_fixup, and filled into
6c9547ff 1025 * adjusted_mode.
e2f0ba97 1026 */
6c9547ff
CW		 1027 if (intel_sdvo->is_tv || intel_sdvo->is_lvds) {
1028 input_dtd = intel_sdvo->input_dtd;
1029 } else {
e2f0ba97 1030 /* Set the output timing to the screen */
32aad86f
CW		 1031 if (!intel_sdvo_set_target_output(intel_sdvo,
1032 intel_sdvo->attached_output))
1033 return;
1034
6c9547ff 1035 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
c74696b9 1036 (void) intel_sdvo_set_output_timing(intel_sdvo, &input_dtd);
e2f0ba97 1037 }
79e53945
JB		 1038
1039 /* Set the input timing to the screen. Assume always input 0. */
32aad86f
CW		 1040 if (!intel_sdvo_set_target_input(intel_sdvo))
1041 return;
79e53945 1042
97aaf910
CW		 1043 if (intel_sdvo->has_hdmi_monitor) {
1044 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
1045 intel_sdvo_set_colorimetry(intel_sdvo,
1046 SDVO_COLORIMETRY_RGB256);
1047 intel_sdvo_set_avi_infoframe(intel_sdvo);
1048 } else
1049 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
7026d4ac 1050
6c9547ff
CW		 1051 if (intel_sdvo->is_tv &&
1052 !intel_sdvo_set_tv_format(intel_sdvo))
1053 return;
e2f0ba97 1054
c74696b9 1055 (void) intel_sdvo_set_input_timing(intel_sdvo, &input_dtd);
79e53945 1056
6c9547ff
CW		 1057 switch (pixel_multiplier) {
1058 default:
32aad86f
CW		 1059 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1060 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1061 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
79e53945 1062 }
32aad86f
CW		 1063 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1064 return;
79e53945
JB		 1065
1066 /* Set the SDVO control regs. */
a6c45cf0 1067 if (INTEL_INFO(dev)->gen >= 4) {
6714afb1 1068 sdvox = 0;
e953fd7b
CW		 1069 if (intel_sdvo->is_hdmi)
1070 sdvox |= intel_sdvo->color_range;
6714afb1
CW		 1071 if (INTEL_INFO(dev)->gen < 5)
1072 sdvox |= SDVO_BORDER_ENABLE;
81a14b46
AJ		 1073 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1074 sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
1075 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1076 sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
e2f0ba97 1077 } else {
6c9547ff 1078 sdvox = I915_READ(intel_sdvo->sdvo_reg);
ea5b213a 1079 switch (intel_sdvo->sdvo_reg) {
e2f0ba97
JB		 1080 case SDVOB:
1081 sdvox &= SDVOB_PRESERVE_MASK;
1082 break;
1083 case SDVOC:
1084 sdvox &= SDVOC_PRESERVE_MASK;
1085 break;
1086 }
1087 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1088 }
79e53945
JB		 1089 if (intel_crtc->pipe == 1)
1090 sdvox |= SDVO_PIPE_B_SELECT;
da79de97 1091 if (intel_sdvo->has_hdmi_audio)
6c9547ff 1092 sdvox |= SDVO_AUDIO_ENABLE;
79e53945 1093
a6c45cf0 1094 if (INTEL_INFO(dev)->gen >= 4) {
e2f0ba97
JB		 1095 /* done in crtc_mode_set as the dpll_md reg must be written early */
1096 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1097 /* done in crtc_mode_set as it lives inside the dpll register */
79e53945 1098 } else {
6c9547ff 1099 sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT;
79e53945
JB		 1100 }
1101
6714afb1
CW		 1102 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
1103 INTEL_INFO(dev)->gen < 5)
12682a97 1104 sdvox |= SDVO_STALL_SELECT;
ea5b213a 1105 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
79e53945
JB		 1106}
1107
1108static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1109{
1110 struct drm_device *dev = encoder->dev;
1111 struct drm_i915_private *dev_priv = dev->dev_private;
890f3359 1112 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
9d0498a2 1113 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
79e53945
JB		 1114 u32 temp;
1115
1116 if (mode != DRM_MODE_DPMS_ON) {
ea5b213a 1117 intel_sdvo_set_active_outputs(intel_sdvo, 0);
79e53945 1118 if (0)
ea5b213a 1119 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
79e53945
JB		 1120
1121 if (mode == DRM_MODE_DPMS_OFF) {
ea5b213a 1122 temp = I915_READ(intel_sdvo->sdvo_reg);
79e53945 1123 if ((temp & SDVO_ENABLE) != 0) {
ea5b213a 1124 intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
79e53945
JB		 1125 }
1126 }
1127 } else {
1128 bool input1, input2;
1129 int i;
1130 u8 status;
1131
ea5b213a 1132 temp = I915_READ(intel_sdvo->sdvo_reg);
79e53945 1133 if ((temp & SDVO_ENABLE) == 0)
ea5b213a 1134 intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
79e53945 1135 for (i = 0; i < 2; i++)
9d0498a2 1136 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 1137
32aad86f 1138 status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
79e53945
JB		 1139 /* Warn if the device reported failure to sync.
1140 * A lot of SDVO devices fail to notify of sync, but it's
1141 * a given it the status is a success, we succeeded.
1142 */
1143 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
8a4c47f3 1144 DRM_DEBUG_KMS("First %s output reported failure to "
ea5b213a 1145 "sync\n", SDVO_NAME(intel_sdvo));
79e53945
JB		 1146 }
1147
1148 if (0)
ea5b213a
CW		 1149 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
1150 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
79e53945
JB		 1151 }
1152 return;
1153}
1154
79e53945
JB		 1155static int intel_sdvo_mode_valid(struct drm_connector *connector,
1156 struct drm_display_mode *mode)
1157{
df0e9248 1158 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
79e53945
JB		 1159
1160 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1161 return MODE_NO_DBLESCAN;
1162
ea5b213a 1163 if (intel_sdvo->pixel_clock_min > mode->clock)
79e53945
JB		 1164 return MODE_CLOCK_LOW;
1165
ea5b213a 1166 if (intel_sdvo->pixel_clock_max < mode->clock)
79e53945
JB		 1167 return MODE_CLOCK_HIGH;
1168
8545423a 1169 if (intel_sdvo->is_lvds) {
ea5b213a 1170 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
12682a97 1171 return MODE_PANEL;
1172
ea5b213a 1173 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
12682a97 1174 return MODE_PANEL;
1175 }
1176
79e53945
JB		 1177 return MODE_OK;
1178}
1179
ea5b213a 1180static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
79e53945 1181{
1a3665c8 1182 BUILD_BUG_ON(sizeof(*caps) != 8);
e957d772
CW		 1183 if (!intel_sdvo_get_value(intel_sdvo,
1184 SDVO_CMD_GET_DEVICE_CAPS,
1185 caps, sizeof(*caps)))
1186 return false;
1187
1188 DRM_DEBUG_KMS("SDVO capabilities:\n"
1189 " vendor_id: %d\n"
1190 " device_id: %d\n"
1191 " device_rev_id: %d\n"
1192 " sdvo_version_major: %d\n"
1193 " sdvo_version_minor: %d\n"
1194 " sdvo_inputs_mask: %d\n"
1195 " smooth_scaling: %d\n"
1196 " sharp_scaling: %d\n"
1197 " up_scaling: %d\n"
1198 " down_scaling: %d\n"
1199 " stall_support: %d\n"
1200 " output_flags: %d\n",
1201 caps->vendor_id,
1202 caps->device_id,
1203 caps->device_rev_id,
1204 caps->sdvo_version_major,
1205 caps->sdvo_version_minor,
1206 caps->sdvo_inputs_mask,
1207 caps->smooth_scaling,
1208 caps->sharp_scaling,
1209 caps->up_scaling,
1210 caps->down_scaling,
1211 caps->stall_support,
1212 caps->output_flags);
1213
1214 return true;
79e53945
JB		 1215}
1216
cc68c81a 1217static int intel_sdvo_supports_hotplug(struct intel_sdvo *intel_sdvo)
79e53945
JB		 1218{
1219 u8 response[2];
79e53945 1220
32aad86f
CW		 1221 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1222 &response, 2) && response[0];
79e53945
JB		 1223}
1224
cc68c81a 1225static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
79e53945 1226{
cc68c81a 1227 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
79e53945 1228
cc68c81a 1229 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &intel_sdvo->hotplug_active, 2);
79e53945
JB		 1230}
1231
fb7a46f3 1232static bool
ea5b213a 1233intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
fb7a46f3 1234{
bc65212c 1235 /* Is there more than one type of output? */
2294488d 1236 return hweight16(intel_sdvo->caps.output_flags) > 1;
fb7a46f3 1237}
1238
f899fc64 1239static struct edid *
e957d772 1240intel_sdvo_get_edid(struct drm_connector *connector)
f899fc64 1241{
e957d772
CW		 1242 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
1243 return drm_get_edid(connector, &sdvo->ddc);
f899fc64
CW		 1244}
1245
ff482d83
CW		 1246/* Mac mini hack -- use the same DDC as the analog connector */
1247static struct edid *
1248intel_sdvo_get_analog_edid(struct drm_connector *connector)
1249{
f899fc64 1250 struct drm_i915_private *dev_priv = connector->dev->dev_private;
ff482d83 1251
0c1dab89
CW		 1252 return drm_get_edid(connector,
1253 &dev_priv->gmbus[dev_priv->crt_ddc_pin].adapter);
ff482d83
CW		 1254}
1255
2b8d33f7 1256enum drm_connector_status
8bf38485 1257intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
9dff6af8 1258{
df0e9248 1259 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
9d1a903d
CW		 1260 enum drm_connector_status status;
1261 struct edid *edid;
9dff6af8 1262
e957d772 1263 edid = intel_sdvo_get_edid(connector);
57cdaf90 1264
ea5b213a 1265 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
e957d772 1266 u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
9d1a903d 1267
7c3f0a27
ZY		 1268 /*
1269 * Don't use the 1 as the argument of DDC bus switch to get
1270 * the EDID. It is used for SDVO SPD ROM.
1271 */
9d1a903d 1272 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
e957d772
CW		 1273 intel_sdvo->ddc_bus = ddc;
1274 edid = intel_sdvo_get_edid(connector);
1275 if (edid)
7c3f0a27 1276 break;
7c3f0a27 1277 }
e957d772
CW		 1278 /*
1279 * If we found the EDID on the other bus,
1280 * assume that is the correct DDC bus.
1281 */
1282 if (edid == NULL)
1283 intel_sdvo->ddc_bus = saved_ddc;
7c3f0a27 1284 }
9d1a903d
CW		 1285
1286 /*
1287 * When there is no edid and no monitor is connected with VGA
1288 * port, try to use the CRT ddc to read the EDID for DVI-connector.
57cdaf90 1289 */
ff482d83
CW		 1290 if (edid == NULL)
1291 edid = intel_sdvo_get_analog_edid(connector);
149c36a3 1292
2f551c84 1293 status = connector_status_unknown;
9dff6af8 1294 if (edid != NULL) {
149c36a3 1295 /* DDC bus is shared, match EDID to connector type */
9d1a903d
CW		 1296 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
1297 status = connector_status_connected;
da79de97
CW		 1298 if (intel_sdvo->is_hdmi) {
1299 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
1300 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
1301 }
13946743
CW		 1302 } else
1303 status = connector_status_disconnected;
149c36a3 1304 connector->display_info.raw_edid = NULL;
9d1a903d
CW		 1305 kfree(edid);
1306 }
7f36e7ed
CW		 1307
1308 if (status == connector_status_connected) {
1309 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1310 if (intel_sdvo_connector->force_audio)
da79de97 1311 intel_sdvo->has_hdmi_audio = intel_sdvo_connector->force_audio > 0;
7f36e7ed
CW		 1312 }
1313
2b8d33f7 1314 return status;
9dff6af8
ML		 1315}
1316
7b334fcb 1317static enum drm_connector_status
930a9e28 1318intel_sdvo_detect(struct drm_connector *connector, bool force)
79e53945 1319{
fb7a46f3 1320 uint16_t response;
df0e9248 1321 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1322 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
14571b4c 1323 enum drm_connector_status ret;
79e53945 1324
32aad86f 1325 if (!intel_sdvo_write_cmd(intel_sdvo,
e957d772 1326 SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0))
32aad86f 1327 return connector_status_unknown;
ba84cd1f
CW		 1328
1329 /* add 30ms delay when the output type might be TV */
1330 if (intel_sdvo->caps.output_flags &
1331 (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_CVBS0))
d09c23de 1332 mdelay(30);
ba84cd1f 1333
32aad86f
CW		 1334 if (!intel_sdvo_read_response(intel_sdvo, &response, 2))
1335 return connector_status_unknown;
79e53945 1336
e957d772
CW		 1337 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
1338 response & 0xff, response >> 8,
1339 intel_sdvo_connector->output_flag);
e2f0ba97 1340
fb7a46f3 1341 if (response == 0)
79e53945 1342 return connector_status_disconnected;
fb7a46f3 1343
ea5b213a 1344 intel_sdvo->attached_output = response;
14571b4c 1345
97aaf910
CW		 1346 intel_sdvo->has_hdmi_monitor = false;
1347 intel_sdvo->has_hdmi_audio = false;
1348
615fb93f 1349 if ((intel_sdvo_connector->output_flag & response) == 0)
14571b4c 1350 ret = connector_status_disconnected;
13946743 1351 else if (IS_TMDS(intel_sdvo_connector))
8bf38485 1352 ret = intel_sdvo_tmds_sink_detect(connector);
13946743
CW		 1353 else {
1354 struct edid *edid;
1355
1356 /* if we have an edid check it matches the connection */
1357 edid = intel_sdvo_get_edid(connector);
1358 if (edid == NULL)
1359 edid = intel_sdvo_get_analog_edid(connector);
1360 if (edid != NULL) {
1361 if (edid->input & DRM_EDID_INPUT_DIGITAL)
1362 ret = connector_status_disconnected;
1363 else
1364 ret = connector_status_connected;
1365 connector->display_info.raw_edid = NULL;
1366 kfree(edid);
1367 } else
1368 ret = connector_status_connected;
1369 }
14571b4c
ZW		 1370
1371 /* May update encoder flag for like clock for SDVO TV, etc.*/
1372 if (ret == connector_status_connected) {
ea5b213a
CW		 1373 intel_sdvo->is_tv = false;
1374 intel_sdvo->is_lvds = false;
1375 intel_sdvo->base.needs_tv_clock = false;
14571b4c
ZW		 1376
1377 if (response & SDVO_TV_MASK) {
ea5b213a
CW		 1378 intel_sdvo->is_tv = true;
1379 intel_sdvo->base.needs_tv_clock = true;
14571b4c
ZW		 1380 }
1381 if (response & SDVO_LVDS_MASK)
8545423a 1382 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
fb7a46f3 1383 }
14571b4c
ZW		 1384
1385 return ret;
79e53945
JB		 1386}
1387
e2f0ba97 1388static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
79e53945 1389{
ff482d83 1390 struct edid *edid;
79e53945
JB		 1391
1392 /* set the bus switch and get the modes */
e957d772 1393 edid = intel_sdvo_get_edid(connector);
79e53945 1394
57cdaf90
KP		 1395 /*
1396 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1397 * link between analog and digital outputs. So, if the regular SDVO
1398 * DDC fails, check to see if the analog output is disconnected, in
1399 * which case we'll look there for the digital DDC data.
e2f0ba97 1400 */
f899fc64
CW		 1401 if (edid == NULL)
1402 edid = intel_sdvo_get_analog_edid(connector);
1403
ff482d83 1404 if (edid != NULL) {
13946743
CW		 1405 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1406 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
1407 bool connector_is_digital = !!IS_TMDS(intel_sdvo_connector);
1408
1409 if (connector_is_digital == monitor_is_digital) {
0c1dab89
CW		 1410 drm_mode_connector_update_edid_property(connector, edid);
1411 drm_add_edid_modes(connector, edid);
1412 }
13946743 1413
ff482d83
CW		 1414 connector->display_info.raw_edid = NULL;
1415 kfree(edid);
e2f0ba97 1416 }
e2f0ba97
JB		 1417}
1418
1419/*
1420 * Set of SDVO TV modes.
1421 * Note! This is in reply order (see loop in get_tv_modes).
1422 * XXX: all 60Hz refresh?
1423 */
b1f559ec 1424static const struct drm_display_mode sdvo_tv_modes[] = {
7026d4ac
ZW		 1425 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1426 416, 0, 200, 201, 232, 233, 0,
e2f0ba97 1427 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1428 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1429 416, 0, 240, 241, 272, 273, 0,
e2f0ba97 1430 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1431 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1432 496, 0, 300, 301, 332, 333, 0,
e2f0ba97 1433 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1434 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1435 736, 0, 350, 351, 382, 383, 0,
e2f0ba97 1436 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1437 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1438 736, 0, 400, 401, 432, 433, 0,
e2f0ba97 1439 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1440 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1441 736, 0, 480, 481, 512, 513, 0,
e2f0ba97 1442 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1443 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1444 800, 0, 480, 481, 512, 513, 0,
e2f0ba97 1445 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1446 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1447 800, 0, 576, 577, 608, 609, 0,
e2f0ba97 1448 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1449 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1450 816, 0, 350, 351, 382, 383, 0,
e2f0ba97 1451 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1452 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1453 816, 0, 400, 401, 432, 433, 0,
e2f0ba97 1454 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1455 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1456 816, 0, 480, 481, 512, 513, 0,
e2f0ba97 1457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1458 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1459 816, 0, 540, 541, 572, 573, 0,
e2f0ba97 1460 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1461 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1462 816, 0, 576, 577, 608, 609, 0,
e2f0ba97 1463 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1464 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1465 864, 0, 576, 577, 608, 609, 0,
e2f0ba97 1466 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1467 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1468 896, 0, 600, 601, 632, 633, 0,
e2f0ba97 1469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1470 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1471 928, 0, 624, 625, 656, 657, 0,
e2f0ba97 1472 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1473 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1474 1016, 0, 766, 767, 798, 799, 0,
e2f0ba97 1475 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1476 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1477 1120, 0, 768, 769, 800, 801, 0,
e2f0ba97 1478 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1479 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1480 1376, 0, 1024, 1025, 1056, 1057, 0,
e2f0ba97
JB		 1481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1482};
1483
1484static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1485{
df0e9248 1486 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7026d4ac 1487 struct intel_sdvo_sdtv_resolution_request tv_res;
ce6feabd
ZY		 1488 uint32_t reply = 0, format_map = 0;
1489 int i;
e2f0ba97
JB		 1490
1491 /* Read the list of supported input resolutions for the selected TV
1492 * format.
1493 */
40039750 1494 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 1495 memcpy(&tv_res, &format_map,
32aad86f 1496 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
ce6feabd 1497
32aad86f
CW		 1498 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
1499 return;
ce6feabd 1500
32aad86f 1501 BUILD_BUG_ON(sizeof(tv_res) != 3);
e957d772
CW		 1502 if (!intel_sdvo_write_cmd(intel_sdvo,
1503 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
32aad86f
CW		 1504 &tv_res, sizeof(tv_res)))
1505 return;
1506 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
e2f0ba97
JB		 1507 return;
1508
1509 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
7026d4ac
ZW		 1510 if (reply & (1 << i)) {
1511 struct drm_display_mode *nmode;
1512 nmode = drm_mode_duplicate(connector->dev,
32aad86f 1513 &sdvo_tv_modes[i]);
7026d4ac
ZW		 1514 if (nmode)
1515 drm_mode_probed_add(connector, nmode);
1516 }
e2f0ba97
JB		 1517}
1518
7086c87f
ML		 1519static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1520{
df0e9248 1521 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7086c87f 1522 struct drm_i915_private *dev_priv = connector->dev->dev_private;
12682a97 1523 struct drm_display_mode *newmode;
7086c87f
ML		 1524
1525 /*
1526 * Attempt to get the mode list from DDC.
1527 * Assume that the preferred modes are
1528 * arranged in priority order.
1529 */
f899fc64 1530 intel_ddc_get_modes(connector, intel_sdvo->i2c);
7086c87f 1531 if (list_empty(&connector->probed_modes) == false)
12682a97 1532 goto end;
7086c87f
ML		 1533
1534 /* Fetch modes from VBT */
1535 if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
7086c87f
ML		 1536 newmode = drm_mode_duplicate(connector->dev,
1537 dev_priv->sdvo_lvds_vbt_mode);
1538 if (newmode != NULL) {
1539 /* Guarantee the mode is preferred */
1540 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1541 DRM_MODE_TYPE_DRIVER);
1542 drm_mode_probed_add(connector, newmode);
1543 }
1544 }
12682a97 1545
1546end:
1547 list_for_each_entry(newmode, &connector->probed_modes, head) {
1548 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
ea5b213a 1549 intel_sdvo->sdvo_lvds_fixed_mode =
12682a97 1550 drm_mode_duplicate(connector->dev, newmode);
6c9547ff
CW		 1551
1552 drm_mode_set_crtcinfo(intel_sdvo->sdvo_lvds_fixed_mode,
1553 0);
1554
8545423a 1555 intel_sdvo->is_lvds = true;
12682a97 1556 break;
1557 }
1558 }
1559
7086c87f
ML		 1560}
1561
e2f0ba97
JB		 1562static int intel_sdvo_get_modes(struct drm_connector *connector)
1563{
615fb93f 1564 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e2f0ba97 1565
615fb93f 1566 if (IS_TV(intel_sdvo_connector))
e2f0ba97 1567 intel_sdvo_get_tv_modes(connector);
615fb93f 1568 else if (IS_LVDS(intel_sdvo_connector))
7086c87f 1569 intel_sdvo_get_lvds_modes(connector);
e2f0ba97
JB		 1570 else
1571 intel_sdvo_get_ddc_modes(connector);
1572
32aad86f 1573 return !list_empty(&connector->probed_modes);
79e53945
JB		 1574}
1575
fcc8d672
CW		 1576static void
1577intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
b9219c5e 1578{
615fb93f 1579 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
b9219c5e
ZY		 1580 struct drm_device *dev = connector->dev;
1581
c5521706
CW		 1582 if (intel_sdvo_connector->left)
1583 drm_property_destroy(dev, intel_sdvo_connector->left);
1584 if (intel_sdvo_connector->right)
1585 drm_property_destroy(dev, intel_sdvo_connector->right);
1586 if (intel_sdvo_connector->top)
1587 drm_property_destroy(dev, intel_sdvo_connector->top);
1588 if (intel_sdvo_connector->bottom)
1589 drm_property_destroy(dev, intel_sdvo_connector->bottom);
1590 if (intel_sdvo_connector->hpos)
1591 drm_property_destroy(dev, intel_sdvo_connector->hpos);
1592 if (intel_sdvo_connector->vpos)
1593 drm_property_destroy(dev, intel_sdvo_connector->vpos);
1594 if (intel_sdvo_connector->saturation)
1595 drm_property_destroy(dev, intel_sdvo_connector->saturation);
1596 if (intel_sdvo_connector->contrast)
1597 drm_property_destroy(dev, intel_sdvo_connector->contrast);
1598 if (intel_sdvo_connector->hue)
1599 drm_property_destroy(dev, intel_sdvo_connector->hue);
1600 if (intel_sdvo_connector->sharpness)
1601 drm_property_destroy(dev, intel_sdvo_connector->sharpness);
1602 if (intel_sdvo_connector->flicker_filter)
1603 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
1604 if (intel_sdvo_connector->flicker_filter_2d)
1605 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
1606 if (intel_sdvo_connector->flicker_filter_adaptive)
1607 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
1608 if (intel_sdvo_connector->tv_luma_filter)
1609 drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
1610 if (intel_sdvo_connector->tv_chroma_filter)
1611 drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
e044218a
CW		 1612 if (intel_sdvo_connector->dot_crawl)
1613 drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
c5521706
CW		 1614 if (intel_sdvo_connector->brightness)
1615 drm_property_destroy(dev, intel_sdvo_connector->brightness);
b9219c5e
ZY		 1616}
1617
79e53945
JB		 1618static void intel_sdvo_destroy(struct drm_connector *connector)
1619{
615fb93f 1620 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
79e53945 1621
c5521706 1622 if (intel_sdvo_connector->tv_format)
ce6feabd 1623 drm_property_destroy(connector->dev,
c5521706 1624 intel_sdvo_connector->tv_format);
b9219c5e 1625
d2a82a6f 1626 intel_sdvo_destroy_enhance_property(connector);
79e53945
JB		 1627 drm_sysfs_connector_remove(connector);
1628 drm_connector_cleanup(connector);
d2a82a6f 1629 kfree(connector);
79e53945
JB		 1630}
1631
1aad7ac0
CW		 1632static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
1633{
1634 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1635 struct edid *edid;
1636 bool has_audio = false;
1637
1638 if (!intel_sdvo->is_hdmi)
1639 return false;
1640
1641 edid = intel_sdvo_get_edid(connector);
1642 if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
1643 has_audio = drm_detect_monitor_audio(edid);
1644
1645 return has_audio;
1646}
1647
ce6feabd
ZY		 1648static int
1649intel_sdvo_set_property(struct drm_connector *connector,
1650 struct drm_property *property,
1651 uint64_t val)
1652{
df0e9248 1653 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1654 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e953fd7b 1655 struct drm_i915_private *dev_priv = connector->dev->dev_private;
b9219c5e 1656 uint16_t temp_value;
32aad86f
CW		 1657 uint8_t cmd;
1658 int ret;
ce6feabd
ZY		 1659
1660 ret = drm_connector_property_set_value(connector, property, val);
32aad86f
CW		 1661 if (ret)
1662 return ret;
ce6feabd 1663
3f43c48d 1664 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 1665 int i = val;
1666 bool has_audio;
1667
1668 if (i == intel_sdvo_connector->force_audio)
7f36e7ed
CW		 1669 return 0;
1670
1aad7ac0 1671 intel_sdvo_connector->force_audio = i;
7f36e7ed 1672
1aad7ac0
CW		 1673 if (i == 0)
1674 has_audio = intel_sdvo_detect_hdmi_audio(connector);
1675 else
1676 has_audio = i > 0;
7f36e7ed 1677
1aad7ac0 1678 if (has_audio == intel_sdvo->has_hdmi_audio)
7f36e7ed 1679 return 0;
7f36e7ed 1680
1aad7ac0 1681 intel_sdvo->has_hdmi_audio = has_audio;
7f36e7ed
CW		 1682 goto done;
1683 }
1684
e953fd7b
CW		 1685 if (property == dev_priv->broadcast_rgb_property) {
1686 if (val == !!intel_sdvo->color_range)
7f36e7ed
CW		 1687 return 0;
1688
e953fd7b 1689 intel_sdvo->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
7f36e7ed
CW		 1690 goto done;
1691 }
1692
c5521706
CW		 1693#define CHECK_PROPERTY(name, NAME) \
1694 if (intel_sdvo_connector->name == property) { \
1695 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
1696 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
1697 cmd = SDVO_CMD_SET_##NAME; \
1698 intel_sdvo_connector->cur_##name = temp_value; \
1699 goto set_value; \
1700 }
1701
1702 if (property == intel_sdvo_connector->tv_format) {
32aad86f
CW		 1703 if (val >= TV_FORMAT_NUM)
1704 return -EINVAL;
1705
40039750 1706 if (intel_sdvo->tv_format_index ==
615fb93f 1707 intel_sdvo_connector->tv_format_supported[val])
32aad86f 1708 return 0;
ce6feabd 1709
40039750 1710 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
c5521706 1711 goto done;
32aad86f 1712 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
b9219c5e 1713 temp_value = val;
c5521706 1714 if (intel_sdvo_connector->left == property) {
b9219c5e 1715 drm_connector_property_set_value(connector,
c5521706 1716 intel_sdvo_connector->right, val);
615fb93f 1717 if (intel_sdvo_connector->left_margin == temp_value)
32aad86f 1718 return 0;
b9219c5e 1719
615fb93f
CW		 1720 intel_sdvo_connector->left_margin = temp_value;
1721 intel_sdvo_connector->right_margin = temp_value;
1722 temp_value = intel_sdvo_connector->max_hscan -
c5521706 1723 intel_sdvo_connector->left_margin;
b9219c5e 1724 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 1725 goto set_value;
1726 } else if (intel_sdvo_connector->right == property) {
b9219c5e 1727 drm_connector_property_set_value(connector,
c5521706 1728 intel_sdvo_connector->left, val);
615fb93f 1729 if (intel_sdvo_connector->right_margin == temp_value)
32aad86f 1730 return 0;
b9219c5e 1731
615fb93f
CW		 1732 intel_sdvo_connector->left_margin = temp_value;
1733 intel_sdvo_connector->right_margin = temp_value;
1734 temp_value = intel_sdvo_connector->max_hscan -
1735 intel_sdvo_connector->left_margin;
b9219c5e 1736 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 1737 goto set_value;
1738 } else if (intel_sdvo_connector->top == property) {
b9219c5e 1739 drm_connector_property_set_value(connector,
c5521706 1740 intel_sdvo_connector->bottom, val);
615fb93f 1741 if (intel_sdvo_connector->top_margin == temp_value)
32aad86f 1742 return 0;
b9219c5e 1743
615fb93f
CW		 1744 intel_sdvo_connector->top_margin = temp_value;
1745 intel_sdvo_connector->bottom_margin = temp_value;
1746 temp_value = intel_sdvo_connector->max_vscan -
c5521706 1747 intel_sdvo_connector->top_margin;
b9219c5e 1748 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 1749 goto set_value;
1750 } else if (intel_sdvo_connector->bottom == property) {
b9219c5e 1751 drm_connector_property_set_value(connector,
c5521706 1752 intel_sdvo_connector->top, val);
615fb93f 1753 if (intel_sdvo_connector->bottom_margin == temp_value)
32aad86f
CW		 1754 return 0;
1755
615fb93f
CW		 1756 intel_sdvo_connector->top_margin = temp_value;
1757 intel_sdvo_connector->bottom_margin = temp_value;
1758 temp_value = intel_sdvo_connector->max_vscan -
c5521706 1759 intel_sdvo_connector->top_margin;
b9219c5e 1760 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 1761 goto set_value;
1762 }
1763 CHECK_PROPERTY(hpos, HPOS)
1764 CHECK_PROPERTY(vpos, VPOS)
1765 CHECK_PROPERTY(saturation, SATURATION)
1766 CHECK_PROPERTY(contrast, CONTRAST)
1767 CHECK_PROPERTY(hue, HUE)
1768 CHECK_PROPERTY(brightness, BRIGHTNESS)
1769 CHECK_PROPERTY(sharpness, SHARPNESS)
1770 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
1771 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
1772 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
1773 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
1774 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
e044218a 1775 CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
c5521706 1776 }
b9219c5e 1777
c5521706 1778 return -EINVAL; /* unknown property */
b9219c5e 1779
c5521706
CW		 1780set_value:
1781 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
1782 return -EIO;
b9219c5e 1783
b9219c5e 1784
c5521706 1785done:
df0e9248
CW		 1786 if (intel_sdvo->base.base.crtc) {
1787 struct drm_crtc *crtc = intel_sdvo->base.base.crtc;
ce6feabd 1788 drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
c5521706
CW		 1789 crtc->y, crtc->fb);
1790 }
1791
32aad86f 1792 return 0;
c5521706 1793#undef CHECK_PROPERTY
ce6feabd
ZY		 1794}
1795
79e53945
JB		 1796static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
1797 .dpms = intel_sdvo_dpms,
1798 .mode_fixup = intel_sdvo_mode_fixup,
1799 .prepare = intel_encoder_prepare,
1800 .mode_set = intel_sdvo_mode_set,
1801 .commit = intel_encoder_commit,
1802};
1803
1804static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
c9fb15f6 1805 .dpms = drm_helper_connector_dpms,
79e53945
JB		 1806 .detect = intel_sdvo_detect,
1807 .fill_modes = drm_helper_probe_single_connector_modes,
ce6feabd 1808 .set_property = intel_sdvo_set_property,
79e53945
JB		 1809 .destroy = intel_sdvo_destroy,
1810};
1811
1812static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
1813 .get_modes = intel_sdvo_get_modes,
1814 .mode_valid = intel_sdvo_mode_valid,
df0e9248 1815 .best_encoder = intel_best_encoder,
79e53945
JB		 1816};
1817
b358d0a6 1818static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
79e53945 1819{
890f3359 1820 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
d2a82a6f 1821
ea5b213a 1822 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
d2a82a6f 1823 drm_mode_destroy(encoder->dev,
ea5b213a 1824 intel_sdvo->sdvo_lvds_fixed_mode);
d2a82a6f 1825
e957d772 1826 i2c_del_adapter(&intel_sdvo->ddc);
ea5b213a 1827 intel_encoder_destroy(encoder);
79e53945
JB		 1828}
1829
1830static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
1831 .destroy = intel_sdvo_enc_destroy,
1832};
1833
b66d8424
CW		 1834static void
1835intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
1836{
1837 uint16_t mask = 0;
1838 unsigned int num_bits;
1839
1840 /* Make a mask of outputs less than or equal to our own priority in the
1841 * list.
1842 */
1843 switch (sdvo->controlled_output) {
1844 case SDVO_OUTPUT_LVDS1:
1845 mask |= SDVO_OUTPUT_LVDS1;
1846 case SDVO_OUTPUT_LVDS0:
1847 mask |= SDVO_OUTPUT_LVDS0;
1848 case SDVO_OUTPUT_TMDS1:
1849 mask |= SDVO_OUTPUT_TMDS1;
1850 case SDVO_OUTPUT_TMDS0:
1851 mask |= SDVO_OUTPUT_TMDS0;
1852 case SDVO_OUTPUT_RGB1:
1853 mask |= SDVO_OUTPUT_RGB1;
1854 case SDVO_OUTPUT_RGB0:
1855 mask |= SDVO_OUTPUT_RGB0;
1856 break;
1857 }
1858
1859 /* Count bits to find what number we are in the priority list. */
1860 mask &= sdvo->caps.output_flags;
1861 num_bits = hweight16(mask);
1862 /* If more than 3 outputs, default to DDC bus 3 for now. */
1863 if (num_bits > 3)
1864 num_bits = 3;
1865
1866 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
1867 sdvo->ddc_bus = 1 << num_bits;
1868}
79e53945 1869
e2f0ba97
JB		 1870/**
1871 * Choose the appropriate DDC bus for control bus switch command for this
1872 * SDVO output based on the controlled output.
1873 *
1874 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
1875 * outputs, then LVDS outputs.
1876 */
1877static void
b1083333 1878intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
ea5b213a 1879 struct intel_sdvo *sdvo, u32 reg)
e2f0ba97 1880{
b1083333 1881 struct sdvo_device_mapping *mapping;
e2f0ba97 1882
b1083333
AJ		 1883 if (IS_SDVOB(reg))
1884 mapping = &(dev_priv->sdvo_mappings[0]);
1885 else
1886 mapping = &(dev_priv->sdvo_mappings[1]);
e2f0ba97 1887
b66d8424
CW		 1888 if (mapping->initialized)
1889 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
1890 else
1891 intel_sdvo_guess_ddc_bus(sdvo);
e2f0ba97
JB		 1892}
1893
e957d772
CW		 1894static void
1895intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
1896 struct intel_sdvo *sdvo, u32 reg)
1897{
1898 struct sdvo_device_mapping *mapping;
46eb3036 1899 u8 pin;
e957d772
CW		 1900
1901 if (IS_SDVOB(reg))
1902 mapping = &dev_priv->sdvo_mappings[0];
1903 else
1904 mapping = &dev_priv->sdvo_mappings[1];
1905
1906 pin = GMBUS_PORT_DPB;
46eb3036 1907 if (mapping->initialized)
e957d772 1908 pin = mapping->i2c_pin;
e957d772 1909
63abf3ed
CW		 1910 if (pin < GMBUS_NUM_PORTS) {
1911 sdvo->i2c = &dev_priv->gmbus[pin].adapter;
d5090b96 1912 intel_gmbus_set_speed(sdvo->i2c, GMBUS_RATE_1MHZ);
63abf3ed 1913 intel_gmbus_force_bit(sdvo->i2c, true);
46eb3036 1914 } else {
63abf3ed 1915 sdvo->i2c = &dev_priv->gmbus[GMBUS_PORT_DPB].adapter;
46eb3036 1916 }
e957d772
CW		 1917}
1918
e2f0ba97 1919static bool
e27d8538 1920intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
e2f0ba97 1921{
97aaf910 1922 return intel_sdvo_check_supp_encode(intel_sdvo);
e2f0ba97
JB		 1923}
1924
714605e4 1925static u8
c751ce4f 1926intel_sdvo_get_slave_addr(struct drm_device *dev, int sdvo_reg)
714605e4 1927{
1928 struct drm_i915_private *dev_priv = dev->dev_private;
1929 struct sdvo_device_mapping *my_mapping, *other_mapping;
1930
461ed3ca 1931 if (IS_SDVOB(sdvo_reg)) {
714605e4 1932 my_mapping = &dev_priv->sdvo_mappings[0];
1933 other_mapping = &dev_priv->sdvo_mappings[1];
1934 } else {
1935 my_mapping = &dev_priv->sdvo_mappings[1];
1936 other_mapping = &dev_priv->sdvo_mappings[0];
1937 }
1938
1939 /* If the BIOS described our SDVO device, take advantage of it. */
1940 if (my_mapping->slave_addr)
1941 return my_mapping->slave_addr;
1942
1943 /* If the BIOS only described a different SDVO device, use the
1944 * address that it isn't using.
1945 */
1946 if (other_mapping->slave_addr) {
1947 if (other_mapping->slave_addr == 0x70)
1948 return 0x72;
1949 else
1950 return 0x70;
1951 }
1952
1953 /* No SDVO device info is found for another DVO port,
1954 * so use mapping assumption we had before BIOS parsing.
1955 */
461ed3ca 1956 if (IS_SDVOB(sdvo_reg))
714605e4 1957 return 0x70;
1958 else
1959 return 0x72;
1960}
1961
14571b4c 1962static void
df0e9248
CW		 1963intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
1964 struct intel_sdvo *encoder)
14571b4c 1965{
df0e9248
CW		 1966 drm_connector_init(encoder->base.base.dev,
1967 &connector->base.base,
1968 &intel_sdvo_connector_funcs,
1969 connector->base.base.connector_type);
6070a4a9 1970
df0e9248
CW		 1971 drm_connector_helper_add(&connector->base.base,
1972 &intel_sdvo_connector_helper_funcs);
14571b4c 1973
df0e9248
CW		 1974 connector->base.base.interlace_allowed = 0;
1975 connector->base.base.doublescan_allowed = 0;
1976 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
14571b4c 1977
df0e9248
CW		 1978 intel_connector_attach_encoder(&connector->base, &encoder->base);
1979 drm_sysfs_connector_add(&connector->base.base);
14571b4c 1980}
6070a4a9 1981
7f36e7ed
CW		 1982static void
1983intel_sdvo_add_hdmi_properties(struct intel_sdvo_connector *connector)
1984{
1985 struct drm_device *dev = connector->base.base.dev;
1986
3f43c48d 1987 intel_attach_force_audio_property(&connector->base.base);
e953fd7b
CW		 1988 if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev))
1989 intel_attach_broadcast_rgb_property(&connector->base.base);
7f36e7ed
CW		 1990}
1991
fb7a46f3 1992static bool
ea5b213a 1993intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
fb7a46f3 1994{
4ef69c7a 1995 struct drm_encoder *encoder = &intel_sdvo->base.base;
14571b4c 1996 struct drm_connector *connector;
cc68c81a 1997 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
14571b4c 1998 struct intel_connector *intel_connector;
615fb93f 1999 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2000
615fb93f
CW		 2001 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2002 if (!intel_sdvo_connector)
14571b4c
ZW		 2003 return false;
2004
14571b4c 2005 if (device == 0) {
ea5b213a 2006 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
615fb93f 2007 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
14571b4c 2008 } else if (device == 1) {
ea5b213a 2009 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
615fb93f 2010 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
14571b4c
ZW		 2011 }
2012
615fb93f 2013 intel_connector = &intel_sdvo_connector->base;
14571b4c 2014 connector = &intel_connector->base;
cc68c81a
SF		 2015 if (intel_sdvo_supports_hotplug(intel_sdvo) & (1 << device)) {
2016 connector->polled = DRM_CONNECTOR_POLL_HPD;
2017 intel_sdvo->hotplug_active[0] |= 1 << device;
2018 /* Some SDVO devices have one-shot hotplug interrupts.
2019 * Ensure that they get re-enabled when an interrupt happens.
2020 */
2021 intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
2022 intel_sdvo_enable_hotplug(intel_encoder);
2023 }
2024 else
2025 connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
14571b4c
ZW		 2026 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2027 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2028
e27d8538 2029 if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
14571b4c 2030 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
e27d8538 2031 intel_sdvo->is_hdmi = true;
14571b4c 2032 }
ea5b213a
CW		 2033 intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2034 (1 << INTEL_ANALOG_CLONE_BIT));
14571b4c 2035
df0e9248 2036 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
f797d221
CW		 2037 if (intel_sdvo->is_hdmi)
2038 intel_sdvo_add_hdmi_properties(intel_sdvo_connector);
14571b4c
ZW		 2039
2040 return true;
2041}
2042
2043static bool
ea5b213a 2044intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
14571b4c 2045{
4ef69c7a
CW		 2046 struct drm_encoder *encoder = &intel_sdvo->base.base;
2047 struct drm_connector *connector;
2048 struct intel_connector *intel_connector;
2049 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2050
615fb93f
CW		 2051 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2052 if (!intel_sdvo_connector)
2053 return false;
14571b4c 2054
615fb93f 2055 intel_connector = &intel_sdvo_connector->base;
4ef69c7a
CW		 2056 connector = &intel_connector->base;
2057 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2058 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
14571b4c 2059
4ef69c7a
CW		 2060 intel_sdvo->controlled_output |= type;
2061 intel_sdvo_connector->output_flag = type;
14571b4c 2062
4ef69c7a
CW		 2063 intel_sdvo->is_tv = true;
2064 intel_sdvo->base.needs_tv_clock = true;
2065 intel_sdvo->base.clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
14571b4c 2066
df0e9248 2067 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
14571b4c 2068
4ef69c7a 2069 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
32aad86f 2070 goto err;
14571b4c 2071
4ef69c7a 2072 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f 2073 goto err;
14571b4c 2074
4ef69c7a 2075 return true;
32aad86f
CW		 2076
2077err:
123d5c01 2078 intel_sdvo_destroy(connector);
32aad86f 2079 return false;
14571b4c
ZW		 2080}
2081
2082static bool
ea5b213a 2083intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2084{
4ef69c7a
CW		 2085 struct drm_encoder *encoder = &intel_sdvo->base.base;
2086 struct drm_connector *connector;
2087 struct intel_connector *intel_connector;
2088 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2089
615fb93f
CW		 2090 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2091 if (!intel_sdvo_connector)
2092 return false;
14571b4c 2093
615fb93f 2094 intel_connector = &intel_sdvo_connector->base;
4ef69c7a 2095 connector = &intel_connector->base;
eb1f8e4f 2096 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
4ef69c7a
CW		 2097 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2098 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2099
2100 if (device == 0) {
2101 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2102 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2103 } else if (device == 1) {
2104 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2105 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2106 }
2107
2108 intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
ea5b213a 2109 (1 << INTEL_ANALOG_CLONE_BIT));
14571b4c 2110
df0e9248
CW		 2111 intel_sdvo_connector_init(intel_sdvo_connector,
2112 intel_sdvo);
4ef69c7a 2113 return true;
14571b4c
ZW		 2114}
2115
2116static bool
ea5b213a 2117intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2118{
4ef69c7a
CW		 2119 struct drm_encoder *encoder = &intel_sdvo->base.base;
2120 struct drm_connector *connector;
2121 struct intel_connector *intel_connector;
2122 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2123
615fb93f
CW		 2124 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2125 if (!intel_sdvo_connector)
2126 return false;
14571b4c 2127
615fb93f
CW		 2128 intel_connector = &intel_sdvo_connector->base;
2129 connector = &intel_connector->base;
4ef69c7a
CW		 2130 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2131 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2132
2133 if (device == 0) {
2134 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2135 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2136 } else if (device == 1) {
2137 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2138 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2139 }
2140
2141 intel_sdvo->base.clone_mask = ((1 << INTEL_ANALOG_CLONE_BIT) |
ea5b213a 2142 (1 << INTEL_SDVO_LVDS_CLONE_BIT));
14571b4c 2143
df0e9248 2144 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
4ef69c7a 2145 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f
CW		 2146 goto err;
2147
2148 return true;
2149
2150err:
123d5c01 2151 intel_sdvo_destroy(connector);
32aad86f 2152 return false;
14571b4c
ZW		 2153}
2154
2155static bool
ea5b213a 2156intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
14571b4c 2157{
ea5b213a
CW		 2158 intel_sdvo->is_tv = false;
2159 intel_sdvo->base.needs_tv_clock = false;
2160 intel_sdvo->is_lvds = false;
fb7a46f3 2161
14571b4c 2162 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
fb7a46f3 2163
14571b4c 2164 if (flags & SDVO_OUTPUT_TMDS0)
ea5b213a 2165 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
14571b4c
ZW		 2166 return false;
2167
2168 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
ea5b213a 2169 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
14571b4c
ZW		 2170 return false;
2171
2172 /* TV has no XXX1 function block */
a1f4b7ff 2173 if (flags & SDVO_OUTPUT_SVID0)
ea5b213a 2174 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
14571b4c
ZW		 2175 return false;
2176
2177 if (flags & SDVO_OUTPUT_CVBS0)
ea5b213a 2178 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
14571b4c 2179 return false;
fb7a46f3 2180
14571b4c 2181 if (flags & SDVO_OUTPUT_RGB0)
ea5b213a 2182 if (!intel_sdvo_analog_init(intel_sdvo, 0))
14571b4c
ZW		 2183 return false;
2184
2185 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
ea5b213a 2186 if (!intel_sdvo_analog_init(intel_sdvo, 1))
14571b4c
ZW		 2187 return false;
2188
2189 if (flags & SDVO_OUTPUT_LVDS0)
ea5b213a 2190 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
14571b4c
ZW		 2191 return false;
2192
2193 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
ea5b213a 2194 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
14571b4c 2195 return false;
fb7a46f3 2196
14571b4c 2197 if ((flags & SDVO_OUTPUT_MASK) == 0) {
fb7a46f3 2198 unsigned char bytes[2];
2199
ea5b213a
CW		 2200 intel_sdvo->controlled_output = 0;
2201 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
51c8b407 2202 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
ea5b213a 2203 SDVO_NAME(intel_sdvo),
51c8b407 2204 bytes[0], bytes[1]);
14571b4c 2205 return false;
fb7a46f3 2206 }
27f8227b 2207 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
fb7a46f3 2208
14571b4c 2209 return true;
fb7a46f3 2210}
2211
32aad86f
CW		 2212static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2213 struct intel_sdvo_connector *intel_sdvo_connector,
2214 int type)
ce6feabd 2215{
4ef69c7a 2216 struct drm_device *dev = intel_sdvo->base.base.dev;
ce6feabd
ZY		 2217 struct intel_sdvo_tv_format format;
2218 uint32_t format_map, i;
ce6feabd 2219
32aad86f
CW		 2220 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2221 return false;
ce6feabd 2222
1a3665c8 2223 BUILD_BUG_ON(sizeof(format) != 6);
32aad86f
CW		 2224 if (!intel_sdvo_get_value(intel_sdvo,
2225 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2226 &format, sizeof(format)))
2227 return false;
ce6feabd 2228
32aad86f 2229 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
ce6feabd
ZY		 2230
2231 if (format_map == 0)
32aad86f 2232 return false;
ce6feabd 2233
615fb93f 2234 intel_sdvo_connector->format_supported_num = 0;
ce6feabd 2235 for (i = 0 ; i < TV_FORMAT_NUM; i++)
40039750
CW		 2236 if (format_map & (1 << i))
2237 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
ce6feabd
ZY		 2238
2239
c5521706 2240 intel_sdvo_connector->tv_format =
32aad86f
CW		 2241 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2242 "mode", intel_sdvo_connector->format_supported_num);
c5521706 2243 if (!intel_sdvo_connector->tv_format)
fcc8d672 2244 return false;
ce6feabd 2245
615fb93f 2246 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
ce6feabd 2247 drm_property_add_enum(
c5521706 2248 intel_sdvo_connector->tv_format, i,
40039750 2249 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
ce6feabd 2250
40039750 2251 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
32aad86f 2252 drm_connector_attach_property(&intel_sdvo_connector->base.base,
c5521706 2253 intel_sdvo_connector->tv_format, 0);
32aad86f 2254 return true;
ce6feabd
ZY		 2255
2256}
2257
c5521706
CW		 2258#define ENHANCEMENT(name, NAME) do { \
2259 if (enhancements.name) { \
2260 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2261 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2262 return false; \
2263 intel_sdvo_connector->max_##name = data_value[0]; \
2264 intel_sdvo_connector->cur_##name = response; \
2265 intel_sdvo_connector->name = \
2266 drm_property_create(dev, DRM_MODE_PROP_RANGE, #name, 2); \
2267 if (!intel_sdvo_connector->name) return false; \
2268 intel_sdvo_connector->name->values[0] = 0; \
2269 intel_sdvo_connector->name->values[1] = data_value[0]; \
2270 drm_connector_attach_property(connector, \
2271 intel_sdvo_connector->name, \
2272 intel_sdvo_connector->cur_##name); \
2273 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2274 data_value[0], data_value[1], response); \
2275 } \
0206e353 2276} while (0)
c5521706
CW		 2277
2278static bool
2279intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
2280 struct intel_sdvo_connector *intel_sdvo_connector,
2281 struct intel_sdvo_enhancements_reply enhancements)
b9219c5e 2282{
4ef69c7a 2283 struct drm_device *dev = intel_sdvo->base.base.dev;
32aad86f 2284 struct drm_connector *connector = &intel_sdvo_connector->base.base;
b9219c5e
ZY		 2285 uint16_t response, data_value[2];
2286
c5521706
CW		 2287 /* when horizontal overscan is supported, Add the left/right property */
2288 if (enhancements.overscan_h) {
2289 if (!intel_sdvo_get_value(intel_sdvo,
2290 SDVO_CMD_GET_MAX_OVERSCAN_H,
2291 &data_value, 4))
2292 return false;
32aad86f 2293
c5521706
CW		 2294 if (!intel_sdvo_get_value(intel_sdvo,
2295 SDVO_CMD_GET_OVERSCAN_H,
2296 &response, 2))
2297 return false;
fcc8d672 2298
c5521706
CW		 2299 intel_sdvo_connector->max_hscan = data_value[0];
2300 intel_sdvo_connector->left_margin = data_value[0] - response;
2301 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
2302 intel_sdvo_connector->left =
2303 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2304 "left_margin", 2);
2305 if (!intel_sdvo_connector->left)
2306 return false;
fcc8d672 2307
c5521706
CW		 2308 intel_sdvo_connector->left->values[0] = 0;
2309 intel_sdvo_connector->left->values[1] = data_value[0];
2310 drm_connector_attach_property(connector,
2311 intel_sdvo_connector->left,
2312 intel_sdvo_connector->left_margin);
fcc8d672 2313
c5521706
CW		 2314 intel_sdvo_connector->right =
2315 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2316 "right_margin", 2);
2317 if (!intel_sdvo_connector->right)
2318 return false;
32aad86f 2319
c5521706
CW		 2320 intel_sdvo_connector->right->values[0] = 0;
2321 intel_sdvo_connector->right->values[1] = data_value[0];
2322 drm_connector_attach_property(connector,
2323 intel_sdvo_connector->right,
2324 intel_sdvo_connector->right_margin);
2325 DRM_DEBUG_KMS("h_overscan: max %d, "
2326 "default %d, current %d\n",
2327 data_value[0], data_value[1], response);
2328 }
32aad86f 2329
c5521706
CW		 2330 if (enhancements.overscan_v) {
2331 if (!intel_sdvo_get_value(intel_sdvo,
2332 SDVO_CMD_GET_MAX_OVERSCAN_V,
2333 &data_value, 4))
2334 return false;
fcc8d672 2335
c5521706
CW		 2336 if (!intel_sdvo_get_value(intel_sdvo,
2337 SDVO_CMD_GET_OVERSCAN_V,
2338 &response, 2))
2339 return false;
32aad86f 2340
c5521706
CW		 2341 intel_sdvo_connector->max_vscan = data_value[0];
2342 intel_sdvo_connector->top_margin = data_value[0] - response;
2343 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
2344 intel_sdvo_connector->top =
2345 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2346 "top_margin", 2);
2347 if (!intel_sdvo_connector->top)
2348 return false;
32aad86f 2349
c5521706
CW		 2350 intel_sdvo_connector->top->values[0] = 0;
2351 intel_sdvo_connector->top->values[1] = data_value[0];
2352 drm_connector_attach_property(connector,
2353 intel_sdvo_connector->top,
2354 intel_sdvo_connector->top_margin);
fcc8d672 2355
c5521706
CW		 2356 intel_sdvo_connector->bottom =
2357 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2358 "bottom_margin", 2);
2359 if (!intel_sdvo_connector->bottom)
2360 return false;
32aad86f 2361
c5521706
CW		 2362 intel_sdvo_connector->bottom->values[0] = 0;
2363 intel_sdvo_connector->bottom->values[1] = data_value[0];
2364 drm_connector_attach_property(connector,
2365 intel_sdvo_connector->bottom,
2366 intel_sdvo_connector->bottom_margin);
2367 DRM_DEBUG_KMS("v_overscan: max %d, "
2368 "default %d, current %d\n",
2369 data_value[0], data_value[1], response);
2370 }
32aad86f 2371
c5521706
CW		 2372 ENHANCEMENT(hpos, HPOS);
2373 ENHANCEMENT(vpos, VPOS);
2374 ENHANCEMENT(saturation, SATURATION);
2375 ENHANCEMENT(contrast, CONTRAST);
2376 ENHANCEMENT(hue, HUE);
2377 ENHANCEMENT(sharpness, SHARPNESS);
2378 ENHANCEMENT(brightness, BRIGHTNESS);
2379 ENHANCEMENT(flicker_filter, FLICKER_FILTER);
2380 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
2381 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
2382 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
2383 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
fcc8d672 2384
e044218a
CW		 2385 if (enhancements.dot_crawl) {
2386 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
2387 return false;
2388
2389 intel_sdvo_connector->max_dot_crawl = 1;
2390 intel_sdvo_connector->cur_dot_crawl = response & 0x1;
2391 intel_sdvo_connector->dot_crawl =
2392 drm_property_create(dev, DRM_MODE_PROP_RANGE, "dot_crawl", 2);
2393 if (!intel_sdvo_connector->dot_crawl)
2394 return false;
2395
2396 intel_sdvo_connector->dot_crawl->values[0] = 0;
2397 intel_sdvo_connector->dot_crawl->values[1] = 1;
2398 drm_connector_attach_property(connector,
2399 intel_sdvo_connector->dot_crawl,
2400 intel_sdvo_connector->cur_dot_crawl);
2401 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
2402 }
2403
c5521706
CW		 2404 return true;
2405}
32aad86f 2406
c5521706
CW		 2407static bool
2408intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
2409 struct intel_sdvo_connector *intel_sdvo_connector,
2410 struct intel_sdvo_enhancements_reply enhancements)
2411{
4ef69c7a 2412 struct drm_device *dev = intel_sdvo->base.base.dev;
c5521706
CW		 2413 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2414 uint16_t response, data_value[2];
32aad86f 2415
c5521706 2416 ENHANCEMENT(brightness, BRIGHTNESS);
fcc8d672 2417
c5521706
CW		 2418 return true;
2419}
2420#undef ENHANCEMENT
32aad86f 2421
c5521706
CW		 2422static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2423 struct intel_sdvo_connector *intel_sdvo_connector)
2424{
2425 union {
2426 struct intel_sdvo_enhancements_reply reply;
2427 uint16_t response;
2428 } enhancements;
32aad86f 2429
1a3665c8
CW		 2430 BUILD_BUG_ON(sizeof(enhancements) != 2);
2431
cf9a2f3a
CW		 2432 enhancements.response = 0;
2433 intel_sdvo_get_value(intel_sdvo,
2434 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2435 &enhancements, sizeof(enhancements));
c5521706
CW		 2436 if (enhancements.response == 0) {
2437 DRM_DEBUG_KMS("No enhancement is supported\n");
2438 return true;
b9219c5e 2439 }
32aad86f 2440
c5521706
CW		 2441 if (IS_TV(intel_sdvo_connector))
2442 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
0206e353 2443 else if (IS_LVDS(intel_sdvo_connector))
c5521706
CW		 2444 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2445 else
2446 return true;
e957d772
CW		 2447}
2448
2449static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
2450 struct i2c_msg *msgs,
2451 int num)
2452{
2453 struct intel_sdvo *sdvo = adapter->algo_data;
fcc8d672 2454
e957d772
CW		 2455 if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
2456 return -EIO;
2457
2458 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
2459}
2460
2461static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
2462{
2463 struct intel_sdvo *sdvo = adapter->algo_data;
2464 return sdvo->i2c->algo->functionality(sdvo->i2c);
2465}
2466
2467static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
2468 .master_xfer = intel_sdvo_ddc_proxy_xfer,
2469 .functionality = intel_sdvo_ddc_proxy_func
2470};
2471
2472static bool
2473intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
2474 struct drm_device *dev)
2475{
2476 sdvo->ddc.owner = THIS_MODULE;
2477 sdvo->ddc.class = I2C_CLASS_DDC;
2478 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
2479 sdvo->ddc.dev.parent = &dev->pdev->dev;
2480 sdvo->ddc.algo_data = sdvo;
2481 sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
2482
2483 return i2c_add_adapter(&sdvo->ddc) == 0;
b9219c5e
ZY		 2484}
2485
c751ce4f 2486bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg)
79e53945 2487{
b01f2c3a 2488 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 2489 struct intel_encoder *intel_encoder;
ea5b213a 2490 struct intel_sdvo *intel_sdvo;
79e53945 2491 int i;
79e53945 2492
ea5b213a
CW		 2493 intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
2494 if (!intel_sdvo)
7d57382e 2495 return false;
79e53945 2496
56184e3d
CW		 2497 intel_sdvo->sdvo_reg = sdvo_reg;
2498 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, sdvo_reg) >> 1;
2499 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg);
e957d772
CW		 2500 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev)) {
2501 kfree(intel_sdvo);
2502 return false;
2503 }
2504
56184e3d 2505 /* encoder type will be decided later */
ea5b213a 2506 intel_encoder = &intel_sdvo->base;
21d40d37 2507 intel_encoder->type = INTEL_OUTPUT_SDVO;
373a3cf7 2508 drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
79e53945 2509
79e53945
JB		 2510 /* Read the regs to test if we can talk to the device */
2511 for (i = 0; i < 0x40; i++) {
f899fc64
CW		 2512 u8 byte;
2513
2514 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
8a4c47f3 2515 DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n",
461ed3ca 2516 IS_SDVOB(sdvo_reg) ? 'B' : 'C');
f899fc64 2517 goto err;
79e53945
JB		 2518 }
2519 }
2520
f899fc64 2521 if (IS_SDVOB(sdvo_reg))
b01f2c3a 2522 dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS;
f899fc64 2523 else
b01f2c3a 2524 dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS;
619ac3b7 2525
4ef69c7a 2526 drm_encoder_helper_add(&intel_encoder->base, &intel_sdvo_helper_funcs);
14571b4c 2527
af901ca1 2528 /* In default case sdvo lvds is false */
32aad86f 2529 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
f899fc64 2530 goto err;
79e53945 2531
cc68c81a
SF		 2532 /* Set up hotplug command - note paranoia about contents of reply.
2533 * We assume that the hardware is in a sane state, and only touch
2534 * the bits we think we understand.
2535 */
2536 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG,
2537 &intel_sdvo->hotplug_active, 2);
2538 intel_sdvo->hotplug_active[0] &= ~0x3;
2539
ea5b213a
CW		 2540 if (intel_sdvo_output_setup(intel_sdvo,
2541 intel_sdvo->caps.output_flags) != true) {
51c8b407 2542 DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n",
461ed3ca 2543 IS_SDVOB(sdvo_reg) ? 'B' : 'C');
f899fc64 2544 goto err;
79e53945
JB		 2545 }
2546
ea5b213a 2547 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
e2f0ba97 2548
79e53945 2549 /* Set the input timing to the screen. Assume always input 0. */
32aad86f 2550 if (!intel_sdvo_set_target_input(intel_sdvo))
f899fc64 2551 goto err;
79e53945 2552
32aad86f
CW		 2553 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
2554 &intel_sdvo->pixel_clock_min,
2555 &intel_sdvo->pixel_clock_max))
f899fc64 2556 goto err;
79e53945 2557
8a4c47f3 2558 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
342dc382 2559 "clock range %dMHz - %dMHz, "
2560 "input 1: %c, input 2: %c, "
2561 "output 1: %c, output 2: %c\n",
ea5b213a
CW		 2562 SDVO_NAME(intel_sdvo),
2563 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
2564 intel_sdvo->caps.device_rev_id,
2565 intel_sdvo->pixel_clock_min / 1000,
2566 intel_sdvo->pixel_clock_max / 1000,
2567 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2568 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
342dc382 2569 /* check currently supported outputs */
ea5b213a 2570 intel_sdvo->caps.output_flags &
79e53945 2571 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
ea5b213a 2572 intel_sdvo->caps.output_flags &
79e53945 2573 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
7d57382e 2574 return true;
79e53945 2575
f899fc64 2576err:
373a3cf7 2577 drm_encoder_cleanup(&intel_encoder->base);
e957d772 2578 i2c_del_adapter(&intel_sdvo->ddc);
ea5b213a 2579 kfree(intel_sdvo);
79e53945 2580
7d57382e 2581 return false;
79e53945 2582}
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