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drm/i915: Subclass intel_connector.
[mirror_ubuntu-disco-kernel.git] / drivers / gpu / drm / i915 / intel_sdvo.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
79e53945
JB		 30#include <linux/delay.h>
31#include "drmP.h"
32#include "drm.h"
33#include "drm_crtc.h"
2b8d33f7 34#include "drm_edid.h"
ea5b213a 35#include "intel_drv.h"
79e53945
JB		 36#include "i915_drm.h"
37#include "i915_drv.h"
38#include "intel_sdvo_regs.h"
39
14571b4c
ZW		 40#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
41#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
42#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
43#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0)
44
45#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
46 SDVO_TV_MASK)
47
48#define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
49#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
50
79e53945 51
ce6feabd
ZY		 52static char *tv_format_names[] = {
53 "NTSC_M" , "NTSC_J" , "NTSC_443",
54 "PAL_B" , "PAL_D" , "PAL_G" ,
55 "PAL_H" , "PAL_I" , "PAL_M" ,
56 "PAL_N" , "PAL_NC" , "PAL_60" ,
57 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
58 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
59 "SECAM_60"
60};
61
62#define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
63
ea5b213a
CW		 64struct intel_sdvo {
65 struct intel_encoder base;
66
f9c10a9b 67 u8 slave_addr;
e2f0ba97
JB		 68
69 /* Register for the SDVO device: SDVOB or SDVOC */
c751ce4f 70 int sdvo_reg;
79e53945 71
e2f0ba97
JB		 72 /* Active outputs controlled by this SDVO output */
73 uint16_t controlled_output;
79e53945 74
e2f0ba97
JB		 75 /*
76 * Capabilities of the SDVO device returned by
77 * i830_sdvo_get_capabilities()
78 */
79e53945 79 struct intel_sdvo_caps caps;
e2f0ba97
JB		 80
81 /* Pixel clock limitations reported by the SDVO device, in kHz */
79e53945
JB		 82 int pixel_clock_min, pixel_clock_max;
83
fb7a46f3 84 /*
85 * For multiple function SDVO device,
86 * this is for current attached outputs.
87 */
88 uint16_t attached_output;
89
e2f0ba97
JB		 90 /**
91 * This is set if we're going to treat the device as TV-out.
92 *
93 * While we have these nice friendly flags for output types that ought
94 * to decide this for us, the S-Video output on our HDMI+S-Video card
95 * shows up as RGB1 (VGA).
96 */
97 bool is_tv;
98
ce6feabd
ZY		 99 /* This is for current tv format name */
100 char *tv_format_name;
101
e2f0ba97
JB		 102 /**
103 * This is set if we treat the device as HDMI, instead of DVI.
104 */
105 bool is_hdmi;
12682a97 106
7086c87f
ML		 107 /**
108 * This is set if we detect output of sdvo device as LVDS.
109 */
110 bool is_lvds;
e2f0ba97 111
12682a97 112 /**
113 * This is sdvo flags for input timing.
114 */
115 uint8_t sdvo_flags;
116
117 /**
118 * This is sdvo fixed pannel mode pointer
119 */
120 struct drm_display_mode *sdvo_lvds_fixed_mode;
121
e2f0ba97
JB		 122 /*
123 * supported encoding mode, used to determine whether HDMI is
124 * supported
125 */
126 struct intel_sdvo_encode encode;
127
c751ce4f 128 /* DDC bus used by this SDVO encoder */
e2f0ba97
JB		 129 uint8_t ddc_bus;
130
57cdaf90
KP		 131 /* Mac mini hack -- use the same DDC as the analog connector */
132 struct i2c_adapter *analog_ddc_bus;
133
14571b4c
ZW		 134};
135
136struct intel_sdvo_connector {
615fb93f
CW		 137 struct intel_connector base;
138
14571b4c
ZW		 139 /* Mark the type of connector */
140 uint16_t output_flag;
141
142 /* This contains all current supported TV format */
143 char *tv_format_supported[TV_FORMAT_NUM];
144 int format_supported_num;
145 struct drm_property *tv_format_property;
146 struct drm_property *tv_format_name_property[TV_FORMAT_NUM];
147
148 /**
149 * Returned SDTV resolutions allowed for the current format, if the
150 * device reported it.
151 */
152 struct intel_sdvo_sdtv_resolution_reply sdtv_resolutions;
153
b9219c5e
ZY		 154 /* add the property for the SDVO-TV */
155 struct drm_property *left_property;
156 struct drm_property *right_property;
157 struct drm_property *top_property;
158 struct drm_property *bottom_property;
159 struct drm_property *hpos_property;
160 struct drm_property *vpos_property;
161
162 /* add the property for the SDVO-TV/LVDS */
163 struct drm_property *brightness_property;
164 struct drm_property *contrast_property;
165 struct drm_property *saturation_property;
166 struct drm_property *hue_property;
167
168 /* Add variable to record current setting for the above property */
169 u32 left_margin, right_margin, top_margin, bottom_margin;
170 /* this is to get the range of margin.*/
171 u32 max_hscan, max_vscan;
172 u32 max_hpos, cur_hpos;
173 u32 max_vpos, cur_vpos;
174 u32 cur_brightness, max_brightness;
175 u32 cur_contrast, max_contrast;
176 u32 cur_saturation, max_saturation;
177 u32 cur_hue, max_hue;
79e53945
JB		 178};
179
ea5b213a
CW		 180static struct intel_sdvo *enc_to_intel_sdvo(struct drm_encoder *encoder)
181{
182 return container_of(enc_to_intel_encoder(encoder), struct intel_sdvo, base);
183}
184
615fb93f
CW		 185static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
186{
187 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
188}
189
fb7a46f3 190static bool
ea5b213a 191intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
14571b4c
ZW		 192static void
193intel_sdvo_tv_create_property(struct drm_connector *connector, int type);
194static void
195intel_sdvo_create_enhance_property(struct drm_connector *connector);
fb7a46f3 196
79e53945
JB		 197/**
198 * Writes the SDVOB or SDVOC with the given value, but always writes both
199 * SDVOB and SDVOC to work around apparent hardware issues (according to
200 * comments in the BIOS).
201 */
ea5b213a 202static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
79e53945 203{
ea5b213a 204 struct drm_device *dev = intel_sdvo->base.enc.dev;
79e53945 205 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 206 u32 bval = val, cval = val;
207 int i;
208
ea5b213a
CW		 209 if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
210 I915_WRITE(intel_sdvo->sdvo_reg, val);
211 I915_READ(intel_sdvo->sdvo_reg);
461ed3ca
ZY		 212 return;
213 }
214
ea5b213a 215 if (intel_sdvo->sdvo_reg == SDVOB) {
79e53945
JB		 216 cval = I915_READ(SDVOC);
217 } else {
218 bval = I915_READ(SDVOB);
219 }
220 /*
221 * Write the registers twice for luck. Sometimes,
222 * writing them only once doesn't appear to 'stick'.
223 * The BIOS does this too. Yay, magic
224 */
225 for (i = 0; i < 2; i++)
226 {
227 I915_WRITE(SDVOB, bval);
228 I915_READ(SDVOB);
229 I915_WRITE(SDVOC, cval);
230 I915_READ(SDVOC);
231 }
232}
233
ea5b213a 234static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr,
79e53945
JB		 235 u8 *ch)
236{
79e53945
JB		 237 u8 out_buf[2];
238 u8 buf[2];
239 int ret;
240
241 struct i2c_msg msgs[] = {
242 {
ea5b213a 243 .addr = intel_sdvo->slave_addr >> 1,
79e53945
JB		 244 .flags = 0,
245 .len = 1,
246 .buf = out_buf,
247 },
248 {
ea5b213a 249 .addr = intel_sdvo->slave_addr >> 1,
79e53945
JB		 250 .flags = I2C_M_RD,
251 .len = 1,
252 .buf = buf,
253 }
254 };
255
256 out_buf[0] = addr;
257 out_buf[1] = 0;
258
ea5b213a 259 if ((ret = i2c_transfer(intel_sdvo->base.i2c_bus, msgs, 2)) == 2)
79e53945
JB		 260 {
261 *ch = buf[0];
262 return true;
263 }
264
8a4c47f3 265 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
79e53945
JB		 266 return false;
267}
268
ea5b213a 269static bool intel_sdvo_write_byte(struct intel_sdvo *intel_sdvo, int addr,
79e53945
JB		 270 u8 ch)
271{
272 u8 out_buf[2];
273 struct i2c_msg msgs[] = {
274 {
ea5b213a 275 .addr = intel_sdvo->slave_addr >> 1,
79e53945
JB		 276 .flags = 0,
277 .len = 2,
278 .buf = out_buf,
279 }
280 };
281
282 out_buf[0] = addr;
283 out_buf[1] = ch;
284
ea5b213a 285 if (i2c_transfer(intel_sdvo->base.i2c_bus, msgs, 1) == 1)
79e53945
JB		 286 {
287 return true;
288 }
289 return false;
290}
291
292#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
293/** Mapping of command numbers to names, for debug output */
005568be 294static const struct _sdvo_cmd_name {
e2f0ba97
JB		 295 u8 cmd;
296 char *name;
79e53945
JB		 297} sdvo_cmd_names[] = {
298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
e2f0ba97
JB		 333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
79e53945 337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
e2f0ba97
JB		 338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
b9219c5e
ZY		 341 /* Add the op code for SDVO enhancements */
342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_POSITION_H),
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POSITION_H),
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_POSITION_H),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_POSITION_V),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POSITION_V),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_POSITION_V),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
e2f0ba97
JB		 366 /* HDMI op code */
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
79e53945
JB		 387};
388
461ed3ca 389#define IS_SDVOB(reg) (reg == SDVOB || reg == PCH_SDVOB)
ea5b213a 390#define SDVO_NAME(svdo) (IS_SDVOB((svdo)->sdvo_reg) ? "SDVOB" : "SDVOC")
79e53945 391
ea5b213a 392static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
79e53945
JB		 393 void *args, int args_len)
394{
79e53945
JB		 395 int i;
396
8a4c47f3 397 DRM_DEBUG_KMS("%s: W: %02X ",
ea5b213a 398 SDVO_NAME(intel_sdvo), cmd);
79e53945 399 for (i = 0; i < args_len; i++)
342dc382 400 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
79e53945 401 for (; i < 8; i++)
342dc382 402 DRM_LOG_KMS(" ");
04ad327f 403 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
79e53945 404 if (cmd == sdvo_cmd_names[i].cmd) {
342dc382 405 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
79e53945
JB		 406 break;
407 }
408 }
04ad327f 409 if (i == ARRAY_SIZE(sdvo_cmd_names))
342dc382 410 DRM_LOG_KMS("(%02X)", cmd);
411 DRM_LOG_KMS("\n");
79e53945 412}
79e53945 413
ea5b213a 414static void intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
79e53945
JB		 415 void *args, int args_len)
416{
417 int i;
418
ea5b213a 419 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
79e53945
JB		 420
421 for (i = 0; i < args_len; i++) {
ea5b213a 422 intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_ARG_0 - i,
79e53945
JB		 423 ((u8*)args)[i]);
424 }
425
ea5b213a 426 intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_OPCODE, cmd);
79e53945
JB		 427}
428
79e53945
JB		 429static const char *cmd_status_names[] = {
430 "Power on",
431 "Success",
432 "Not supported",
433 "Invalid arg",
434 "Pending",
435 "Target not specified",
436 "Scaling not supported"
437};
438
ea5b213a 439static void intel_sdvo_debug_response(struct intel_sdvo *intel_sdvo,
79e53945
JB		 440 void *response, int response_len,
441 u8 status)
442{
33b52961 443 int i;
79e53945 444
ea5b213a 445 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
79e53945 446 for (i = 0; i < response_len; i++)
342dc382 447 DRM_LOG_KMS("%02X ", ((u8 *)response)[i]);
79e53945 448 for (; i < 8; i++)
342dc382 449 DRM_LOG_KMS(" ");
79e53945 450 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
342dc382 451 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
79e53945 452 else
342dc382 453 DRM_LOG_KMS("(??? %d)", status);
454 DRM_LOG_KMS("\n");
79e53945 455}
79e53945 456
ea5b213a 457static u8 intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
79e53945
JB		 458 void *response, int response_len)
459{
460 int i;
461 u8 status;
462 u8 retry = 50;
463
464 while (retry--) {
465 /* Read the command response */
466 for (i = 0; i < response_len; i++) {
ea5b213a 467 intel_sdvo_read_byte(intel_sdvo,
79e53945
JB		 468 SDVO_I2C_RETURN_0 + i,
469 &((u8 *)response)[i]);
470 }
471
472 /* read the return status */
ea5b213a 473 intel_sdvo_read_byte(intel_sdvo, SDVO_I2C_CMD_STATUS,
79e53945
JB		 474 &status);
475
ea5b213a 476 intel_sdvo_debug_response(intel_sdvo, response, response_len,
79e53945
JB		 477 status);
478 if (status != SDVO_CMD_STATUS_PENDING)
479 return status;
480
481 mdelay(50);
482 }
483
484 return status;
485}
486
b358d0a6 487static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
79e53945
JB		 488{
489 if (mode->clock >= 100000)
490 return 1;
491 else if (mode->clock >= 50000)
492 return 2;
493 else
494 return 4;
495}
496
497/**
6a304caf
ZY		 498 * Try to read the response after issuie the DDC switch command. But it
499 * is noted that we must do the action of reading response and issuing DDC
500 * switch command in one I2C transaction. Otherwise when we try to start
501 * another I2C transaction after issuing the DDC bus switch, it will be
502 * switched to the internal SDVO register.
79e53945 503 */
ea5b213a 504static void intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
b358d0a6 505 u8 target)
79e53945 506{
6a304caf
ZY		 507 u8 out_buf[2], cmd_buf[2], ret_value[2], ret;
508 struct i2c_msg msgs[] = {
509 {
ea5b213a 510 .addr = intel_sdvo->slave_addr >> 1,
6a304caf
ZY		 511 .flags = 0,
512 .len = 2,
513 .buf = out_buf,
514 },
515 /* the following two are to read the response */
516 {
ea5b213a 517 .addr = intel_sdvo->slave_addr >> 1,
6a304caf
ZY		 518 .flags = 0,
519 .len = 1,
520 .buf = cmd_buf,
521 },
522 {
ea5b213a 523 .addr = intel_sdvo->slave_addr >> 1,
6a304caf
ZY		 524 .flags = I2C_M_RD,
525 .len = 1,
526 .buf = ret_value,
527 },
528 };
529
ea5b213a 530 intel_sdvo_debug_write(intel_sdvo, SDVO_CMD_SET_CONTROL_BUS_SWITCH,
6a304caf
ZY		 531 &target, 1);
532 /* write the DDC switch command argument */
ea5b213a 533 intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_ARG_0, target);
6a304caf
ZY		 534
535 out_buf[0] = SDVO_I2C_OPCODE;
536 out_buf[1] = SDVO_CMD_SET_CONTROL_BUS_SWITCH;
537 cmd_buf[0] = SDVO_I2C_CMD_STATUS;
538 cmd_buf[1] = 0;
539 ret_value[0] = 0;
540 ret_value[1] = 0;
541
ea5b213a 542 ret = i2c_transfer(intel_sdvo->base.i2c_bus, msgs, 3);
6a304caf
ZY		 543 if (ret != 3) {
544 /* failure in I2C transfer */
545 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
546 return;
547 }
548 if (ret_value[0] != SDVO_CMD_STATUS_SUCCESS) {
549 DRM_DEBUG_KMS("DDC switch command returns response %d\n",
550 ret_value[0]);
551 return;
552 }
553 return;
79e53945
JB		 554}
555
ea5b213a 556static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo, bool target_0, bool target_1)
79e53945
JB		 557{
558 struct intel_sdvo_set_target_input_args targets = {0};
559 u8 status;
560
561 if (target_0 && target_1)
562 return SDVO_CMD_STATUS_NOTSUPP;
563
564 if (target_1)
565 targets.target_1 = 1;
566
ea5b213a 567 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_TARGET_INPUT, &targets,
79e53945
JB		 568 sizeof(targets));
569
ea5b213a 570 status = intel_sdvo_read_response(intel_sdvo, NULL, 0);
79e53945
JB		 571
572 return (status == SDVO_CMD_STATUS_SUCCESS);
573}
574
575/**
576 * Return whether each input is trained.
577 *
578 * This function is making an assumption about the layout of the response,
579 * which should be checked against the docs.
580 */
ea5b213a 581static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
79e53945
JB		 582{
583 struct intel_sdvo_get_trained_inputs_response response;
584 u8 status;
585
ea5b213a
CW		 586 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS, NULL, 0);
587 status = intel_sdvo_read_response(intel_sdvo, &response, sizeof(response));
79e53945
JB		 588 if (status != SDVO_CMD_STATUS_SUCCESS)
589 return false;
590
591 *input_1 = response.input0_trained;
592 *input_2 = response.input1_trained;
593 return true;
594}
595
ea5b213a 596static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
79e53945
JB		 597 u16 outputs)
598{
599 u8 status;
600
ea5b213a 601 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_OUTPUTS, &outputs,
79e53945 602 sizeof(outputs));
ea5b213a 603 status = intel_sdvo_read_response(intel_sdvo, NULL, 0);
79e53945
JB		 604 return (status == SDVO_CMD_STATUS_SUCCESS);
605}
606
ea5b213a 607static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
79e53945
JB		 608 int mode)
609{
610 u8 status, state = SDVO_ENCODER_STATE_ON;
611
612 switch (mode) {
613 case DRM_MODE_DPMS_ON:
614 state = SDVO_ENCODER_STATE_ON;
615 break;
616 case DRM_MODE_DPMS_STANDBY:
617 state = SDVO_ENCODER_STATE_STANDBY;
618 break;
619 case DRM_MODE_DPMS_SUSPEND:
620 state = SDVO_ENCODER_STATE_SUSPEND;
621 break;
622 case DRM_MODE_DPMS_OFF:
623 state = SDVO_ENCODER_STATE_OFF;
624 break;
625 }
626
ea5b213a 627 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ENCODER_POWER_STATE, &state,
79e53945 628 sizeof(state));
ea5b213a 629 status = intel_sdvo_read_response(intel_sdvo, NULL, 0);
79e53945
JB		 630
631 return (status == SDVO_CMD_STATUS_SUCCESS);
632}
633
ea5b213a 634static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
79e53945
JB		 635 int *clock_min,
636 int *clock_max)
637{
638 struct intel_sdvo_pixel_clock_range clocks;
639 u8 status;
640
ea5b213a 641 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
79e53945
JB		 642 NULL, 0);
643
ea5b213a 644 status = intel_sdvo_read_response(intel_sdvo, &clocks, sizeof(clocks));
79e53945
JB		 645
646 if (status != SDVO_CMD_STATUS_SUCCESS)
647 return false;
648
649 /* Convert the values from units of 10 kHz to kHz. */
650 *clock_min = clocks.min * 10;
651 *clock_max = clocks.max * 10;
652
653 return true;
654}
655
ea5b213a 656static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
79e53945
JB		 657 u16 outputs)
658{
659 u8 status;
660
ea5b213a 661 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_TARGET_OUTPUT, &outputs,
79e53945
JB		 662 sizeof(outputs));
663
ea5b213a 664 status = intel_sdvo_read_response(intel_sdvo, NULL, 0);
79e53945
JB		 665 return (status == SDVO_CMD_STATUS_SUCCESS);
666}
667
ea5b213a 668static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
79e53945
JB		 669 struct intel_sdvo_dtd *dtd)
670{
671 u8 status;
672
ea5b213a
CW		 673 intel_sdvo_write_cmd(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1));
674 status = intel_sdvo_read_response(intel_sdvo, NULL, 0);
79e53945
JB		 675 if (status != SDVO_CMD_STATUS_SUCCESS)
676 return false;
677
ea5b213a
CW		 678 intel_sdvo_write_cmd(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
679 status = intel_sdvo_read_response(intel_sdvo, NULL, 0);
79e53945
JB		 680 if (status != SDVO_CMD_STATUS_SUCCESS)
681 return false;
682
683 return true;
684}
685
ea5b213a 686static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 687 struct intel_sdvo_dtd *dtd)
688{
ea5b213a 689 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 690 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
691}
692
ea5b213a 693static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 694 struct intel_sdvo_dtd *dtd)
695{
ea5b213a 696 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 697 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
698}
699
e2f0ba97 700static bool
ea5b213a 701intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 702 uint16_t clock,
703 uint16_t width,
704 uint16_t height)
705{
706 struct intel_sdvo_preferred_input_timing_args args;
707 uint8_t status;
708
e642c6f1 709 memset(&args, 0, sizeof(args));
e2f0ba97
JB		 710 args.clock = clock;
711 args.width = width;
712 args.height = height;
e642c6f1 713 args.interlace = 0;
12682a97 714
ea5b213a
CW		 715 if (intel_sdvo->is_lvds &&
716 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
717 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
12682a97 718 args.scaled = 1;
719
ea5b213a 720 intel_sdvo_write_cmd(intel_sdvo,
c751ce4f 721 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
e2f0ba97 722 &args, sizeof(args));
ea5b213a 723 status = intel_sdvo_read_response(intel_sdvo, NULL, 0);
e2f0ba97
JB		 724 if (status != SDVO_CMD_STATUS_SUCCESS)
725 return false;
726
727 return true;
728}
729
ea5b213a 730static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 731 struct intel_sdvo_dtd *dtd)
732{
733 bool status;
734
ea5b213a 735 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
e2f0ba97
JB		 736 NULL, 0);
737
ea5b213a 738 status = intel_sdvo_read_response(intel_sdvo, &dtd->part1,
e2f0ba97
JB		 739 sizeof(dtd->part1));
740 if (status != SDVO_CMD_STATUS_SUCCESS)
741 return false;
742
ea5b213a 743 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
e2f0ba97
JB		 744 NULL, 0);
745
ea5b213a 746 status = intel_sdvo_read_response(intel_sdvo, &dtd->part2,
e2f0ba97
JB		 747 sizeof(dtd->part2));
748 if (status != SDVO_CMD_STATUS_SUCCESS)
749 return false;
750
751 return false;
752}
79e53945 753
ea5b213a 754static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
79e53945
JB		 755{
756 u8 status;
757
ea5b213a
CW		 758 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
759 status = intel_sdvo_read_response(intel_sdvo, NULL, 0);
79e53945
JB		 760 if (status != SDVO_CMD_STATUS_SUCCESS)
761 return false;
762
763 return true;
764}
765
e2f0ba97
JB		 766static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
767 struct drm_display_mode *mode)
79e53945 768{
e2f0ba97
JB		 769 uint16_t width, height;
770 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
771 uint16_t h_sync_offset, v_sync_offset;
79e53945
JB		 772
773 width = mode->crtc_hdisplay;
774 height = mode->crtc_vdisplay;
775
776 /* do some mode translations */
777 h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
778 h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
779
780 v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
781 v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
782
783 h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
784 v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
785
e2f0ba97
JB		 786 dtd->part1.clock = mode->clock / 10;
787 dtd->part1.h_active = width & 0xff;
788 dtd->part1.h_blank = h_blank_len & 0xff;
789 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
79e53945 790 ((h_blank_len >> 8) & 0xf);
e2f0ba97
JB		 791 dtd->part1.v_active = height & 0xff;
792 dtd->part1.v_blank = v_blank_len & 0xff;
793 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
79e53945
JB		 794 ((v_blank_len >> 8) & 0xf);
795
171a9e96 796 dtd->part2.h_sync_off = h_sync_offset & 0xff;
e2f0ba97
JB		 797 dtd->part2.h_sync_width = h_sync_len & 0xff;
798 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
79e53945 799 (v_sync_len & 0xf);
e2f0ba97 800 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
79e53945
JB		 801 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
802 ((v_sync_len & 0x30) >> 4);
803
e2f0ba97 804 dtd->part2.dtd_flags = 0x18;
79e53945 805 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
e2f0ba97 806 dtd->part2.dtd_flags |= 0x2;
79e53945 807 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
e2f0ba97
JB		 808 dtd->part2.dtd_flags |= 0x4;
809
810 dtd->part2.sdvo_flags = 0;
811 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
812 dtd->part2.reserved = 0;
813}
814
815static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
816 struct intel_sdvo_dtd *dtd)
817{
e2f0ba97
JB		 818 mode->hdisplay = dtd->part1.h_active;
819 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
820 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
171a9e96 821 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
e2f0ba97
JB		 822 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
823 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
824 mode->htotal = mode->hdisplay + dtd->part1.h_blank;
825 mode->htotal += (dtd->part1.h_high & 0xf) << 8;
826
827 mode->vdisplay = dtd->part1.v_active;
828 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
829 mode->vsync_start = mode->vdisplay;
830 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
171a9e96 831 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
e2f0ba97
JB		 832 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
833 mode->vsync_end = mode->vsync_start +
834 (dtd->part2.v_sync_off_width & 0xf);
835 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
836 mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
837 mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
838
839 mode->clock = dtd->part1.clock * 10;
840
171a9e96 841 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
e2f0ba97
JB		 842 if (dtd->part2.dtd_flags & 0x2)
843 mode->flags |= DRM_MODE_FLAG_PHSYNC;
844 if (dtd->part2.dtd_flags & 0x4)
845 mode->flags |= DRM_MODE_FLAG_PVSYNC;
846}
847
ea5b213a 848static bool intel_sdvo_get_supp_encode(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 849 struct intel_sdvo_encode *encode)
850{
851 uint8_t status;
852
ea5b213a
CW		 853 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_SUPP_ENCODE, NULL, 0);
854 status = intel_sdvo_read_response(intel_sdvo, encode, sizeof(*encode));
e2f0ba97
JB		 855 if (status != SDVO_CMD_STATUS_SUCCESS) { /* non-support means DVI */
856 memset(encode, 0, sizeof(*encode));
857 return false;
858 }
859
860 return true;
861}
862
ea5b213a 863static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
c751ce4f 864 uint8_t mode)
e2f0ba97
JB		 865{
866 uint8_t status;
867
ea5b213a
CW		 868 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
869 status = intel_sdvo_read_response(intel_sdvo, NULL, 0);
e2f0ba97
JB		 870
871 return (status == SDVO_CMD_STATUS_SUCCESS);
872}
873
ea5b213a 874static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 875 uint8_t mode)
876{
877 uint8_t status;
878
ea5b213a
CW		 879 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
880 status = intel_sdvo_read_response(intel_sdvo, NULL, 0);
e2f0ba97
JB		 881
882 return (status == SDVO_CMD_STATUS_SUCCESS);
883}
884
885#if 0
ea5b213a 886static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 887{
888 int i, j;
889 uint8_t set_buf_index[2];
890 uint8_t av_split;
891 uint8_t buf_size;
892 uint8_t buf[48];
893 uint8_t *pos;
894
c751ce4f
EA		 895 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, NULL, 0);
896 intel_sdvo_read_response(encoder, &av_split, 1);
e2f0ba97
JB		 897
898 for (i = 0; i <= av_split; i++) {
899 set_buf_index[0] = i; set_buf_index[1] = 0;
c751ce4f 900 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
e2f0ba97 901 set_buf_index, 2);
c751ce4f
EA		 902 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
903 intel_sdvo_read_response(encoder, &buf_size, 1);
e2f0ba97
JB		 904
905 pos = buf;
906 for (j = 0; j <= buf_size; j += 8) {
c751ce4f 907 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
e2f0ba97 908 NULL, 0);
c751ce4f 909 intel_sdvo_read_response(encoder, pos, 8);
e2f0ba97
JB		 910 pos += 8;
911 }
912 }
913}
914#endif
915
ea5b213a 916static void intel_sdvo_set_hdmi_buf(struct intel_sdvo *intel_sdvo,
c751ce4f
EA		 917 int index,
918 uint8_t *data, int8_t size, uint8_t tx_rate)
e2f0ba97
JB		 919{
920 uint8_t set_buf_index[2];
921
922 set_buf_index[0] = index;
923 set_buf_index[1] = 0;
924
ea5b213a 925 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_INDEX,
c751ce4f 926 set_buf_index, 2);
e2f0ba97
JB		 927
928 for (; size > 0; size -= 8) {
ea5b213a 929 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_DATA, data, 8);
e2f0ba97
JB		 930 data += 8;
931 }
932
ea5b213a 933 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1);
e2f0ba97
JB		 934}
935
936static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data, uint8_t size)
937{
938 uint8_t csum = 0;
939 int i;
940
941 for (i = 0; i < size; i++)
942 csum += data[i];
943
944 return 0x100 - csum;
945}
946
947#define DIP_TYPE_AVI 0x82
948#define DIP_VERSION_AVI 0x2
949#define DIP_LEN_AVI 13
950
951struct dip_infoframe {
952 uint8_t type;
953 uint8_t version;
954 uint8_t len;
955 uint8_t checksum;
956 union {
957 struct {
958 /* Packet Byte #1 */
959 uint8_t S:2;
960 uint8_t B:2;
961 uint8_t A:1;
962 uint8_t Y:2;
963 uint8_t rsvd1:1;
964 /* Packet Byte #2 */
965 uint8_t R:4;
966 uint8_t M:2;
967 uint8_t C:2;
968 /* Packet Byte #3 */
969 uint8_t SC:2;
970 uint8_t Q:2;
971 uint8_t EC:3;
972 uint8_t ITC:1;
973 /* Packet Byte #4 */
974 uint8_t VIC:7;
975 uint8_t rsvd2:1;
976 /* Packet Byte #5 */
977 uint8_t PR:4;
978 uint8_t rsvd3:4;
979 /* Packet Byte #6~13 */
980 uint16_t top_bar_end;
981 uint16_t bottom_bar_start;
982 uint16_t left_bar_end;
983 uint16_t right_bar_start;
984 } avi;
985 struct {
986 /* Packet Byte #1 */
987 uint8_t channel_count:3;
988 uint8_t rsvd1:1;
989 uint8_t coding_type:4;
990 /* Packet Byte #2 */
991 uint8_t sample_size:2; /* SS0, SS1 */
992 uint8_t sample_frequency:3;
993 uint8_t rsvd2:3;
994 /* Packet Byte #3 */
995 uint8_t coding_type_private:5;
996 uint8_t rsvd3:3;
997 /* Packet Byte #4 */
998 uint8_t channel_allocation;
999 /* Packet Byte #5 */
1000 uint8_t rsvd4:3;
1001 uint8_t level_shift:4;
1002 uint8_t downmix_inhibit:1;
1003 } audio;
1004 uint8_t payload[28];
1005 } __attribute__ ((packed)) u;
1006} __attribute__((packed));
1007
ea5b213a 1008static void intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 1009 struct drm_display_mode * mode)
1010{
1011 struct dip_infoframe avi_if = {
1012 .type = DIP_TYPE_AVI,
1013 .version = DIP_VERSION_AVI,
1014 .len = DIP_LEN_AVI,
1015 };
1016
1017 avi_if.checksum = intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if,
1018 4 + avi_if.len);
ea5b213a 1019 intel_sdvo_set_hdmi_buf(intel_sdvo, 1, (uint8_t *)&avi_if,
c751ce4f 1020 4 + avi_if.len,
e2f0ba97
JB		 1021 SDVO_HBUF_TX_VSYNC);
1022}
1023
ea5b213a 1024static void intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
7026d4ac 1025{
ce6feabd
ZY		 1026
1027 struct intel_sdvo_tv_format format;
ce6feabd
ZY		 1028 uint32_t format_map, i;
1029 uint8_t status;
7026d4ac 1030
ce6feabd 1031 for (i = 0; i < TV_FORMAT_NUM; i++)
ea5b213a 1032 if (tv_format_names[i] == intel_sdvo->tv_format_name)
ce6feabd
ZY		 1033 break;
1034
1035 format_map = 1 << i;
1036 memset(&format, 0, sizeof(format));
1037 memcpy(&format, &format_map, sizeof(format_map) > sizeof(format) ?
1038 sizeof(format) : sizeof(format_map));
1039
ea5b213a 1040 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_TV_FORMAT, &format,
ce6feabd
ZY		 1041 sizeof(format));
1042
ea5b213a 1043 status = intel_sdvo_read_response(intel_sdvo, NULL, 0);
ce6feabd 1044 if (status != SDVO_CMD_STATUS_SUCCESS)
b9219c5e 1045 DRM_DEBUG_KMS("%s: Failed to set TV format\n",
ea5b213a 1046 SDVO_NAME(intel_sdvo));
7026d4ac
ZW		 1047}
1048
e2f0ba97
JB		 1049static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
1050 struct drm_display_mode *mode,
1051 struct drm_display_mode *adjusted_mode)
1052{
ea5b213a 1053 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
79e53945 1054
ea5b213a 1055 if (intel_sdvo->is_tv) {
e2f0ba97
JB		 1056 struct intel_sdvo_dtd output_dtd;
1057 bool success;
1058
1059 /* We need to construct preferred input timings based on our
1060 * output timings. To do that, we have to set the output
1061 * timings, even though this isn't really the right place in
1062 * the sequence to do it. Oh well.
1063 */
1064
1065
1066 /* Set output timings */
1067 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
ea5b213a
CW		 1068 intel_sdvo_set_target_output(intel_sdvo,
1069 intel_sdvo->attached_output);
1070 intel_sdvo_set_output_timing(intel_sdvo, &output_dtd);
e2f0ba97
JB		 1071
1072 /* Set the input timing to the screen. Assume always input 0. */
ea5b213a 1073 intel_sdvo_set_target_input(intel_sdvo, true, false);
e2f0ba97
JB		 1074
1075
ea5b213a 1076 success = intel_sdvo_create_preferred_input_timing(intel_sdvo,
e2f0ba97
JB		 1077 mode->clock / 10,
1078 mode->hdisplay,
1079 mode->vdisplay);
1080 if (success) {
1081 struct intel_sdvo_dtd input_dtd;
79e53945 1082
ea5b213a 1083 intel_sdvo_get_preferred_input_timing(intel_sdvo,
e2f0ba97
JB		 1084 &input_dtd);
1085 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
ea5b213a 1086 intel_sdvo->sdvo_flags = input_dtd.part2.sdvo_flags;
12682a97 1087
1088 drm_mode_set_crtcinfo(adjusted_mode, 0);
1089
1090 mode->clock = adjusted_mode->clock;
1091
1092 adjusted_mode->clock *=
1093 intel_sdvo_get_pixel_multiplier(mode);
1094 } else {
1095 return false;
1096 }
ea5b213a 1097 } else if (intel_sdvo->is_lvds) {
12682a97 1098 struct intel_sdvo_dtd output_dtd;
1099 bool success;
1100
ea5b213a 1101 drm_mode_set_crtcinfo(intel_sdvo->sdvo_lvds_fixed_mode, 0);
12682a97 1102 /* Set output timings */
1103 intel_sdvo_get_dtd_from_mode(&output_dtd,
ea5b213a 1104 intel_sdvo->sdvo_lvds_fixed_mode);
12682a97 1105
ea5b213a
CW		 1106 intel_sdvo_set_target_output(intel_sdvo,
1107 intel_sdvo->attached_output);
1108 intel_sdvo_set_output_timing(intel_sdvo, &output_dtd);
12682a97 1109
1110 /* Set the input timing to the screen. Assume always input 0. */
ea5b213a 1111 intel_sdvo_set_target_input(intel_sdvo, true, false);
12682a97 1112
1113
1114 success = intel_sdvo_create_preferred_input_timing(
ea5b213a 1115 intel_sdvo,
12682a97 1116 mode->clock / 10,
1117 mode->hdisplay,
1118 mode->vdisplay);
1119
1120 if (success) {
1121 struct intel_sdvo_dtd input_dtd;
1122
ea5b213a 1123 intel_sdvo_get_preferred_input_timing(intel_sdvo,
12682a97 1124 &input_dtd);
1125 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
ea5b213a 1126 intel_sdvo->sdvo_flags = input_dtd.part2.sdvo_flags;
e2f0ba97 1127
7026d4ac
ZW		 1128 drm_mode_set_crtcinfo(adjusted_mode, 0);
1129
1130 mode->clock = adjusted_mode->clock;
1131
1132 adjusted_mode->clock *=
1133 intel_sdvo_get_pixel_multiplier(mode);
e2f0ba97
JB		 1134 } else {
1135 return false;
1136 }
12682a97 1137
1138 } else {
1139 /* Make the CRTC code factor in the SDVO pixel multiplier. The
1140 * SDVO device will be told of the multiplier during mode_set.
1141 */
1142 adjusted_mode->clock *= intel_sdvo_get_pixel_multiplier(mode);
e2f0ba97
JB		 1143 }
1144 return true;
1145}
1146
1147static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1148 struct drm_display_mode *mode,
1149 struct drm_display_mode *adjusted_mode)
1150{
1151 struct drm_device *dev = encoder->dev;
1152 struct drm_i915_private *dev_priv = dev->dev_private;
1153 struct drm_crtc *crtc = encoder->crtc;
1154 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ea5b213a 1155 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
e2f0ba97
JB		 1156 u32 sdvox = 0;
1157 int sdvo_pixel_multiply;
1158 struct intel_sdvo_in_out_map in_out;
1159 struct intel_sdvo_dtd input_dtd;
1160 u8 status;
1161
1162 if (!mode)
1163 return;
1164
1165 /* First, set the input mapping for the first input to our controlled
1166 * output. This is only correct if we're a single-input device, in
1167 * which case the first input is the output from the appropriate SDVO
1168 * channel on the motherboard. In a two-input device, the first input
1169 * will be SDVOB and the second SDVOC.
1170 */
ea5b213a 1171 in_out.in0 = intel_sdvo->attached_output;
e2f0ba97
JB		 1172 in_out.in1 = 0;
1173
ea5b213a 1174 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_IN_OUT_MAP,
e2f0ba97 1175 &in_out, sizeof(in_out));
ea5b213a 1176 status = intel_sdvo_read_response(intel_sdvo, NULL, 0);
e2f0ba97 1177
ea5b213a
CW		 1178 if (intel_sdvo->is_hdmi) {
1179 intel_sdvo_set_avi_infoframe(intel_sdvo, mode);
e2f0ba97
JB		 1180 sdvox |= SDVO_AUDIO_ENABLE;
1181 }
1182
7026d4ac
ZW		 1183 /* We have tried to get input timing in mode_fixup, and filled into
1184 adjusted_mode */
ea5b213a 1185 if (intel_sdvo->is_tv || intel_sdvo->is_lvds) {
7026d4ac 1186 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
ea5b213a 1187 input_dtd.part2.sdvo_flags = intel_sdvo->sdvo_flags;
12682a97 1188 } else
7026d4ac 1189 intel_sdvo_get_dtd_from_mode(&input_dtd, mode);
e2f0ba97
JB		 1190
1191 /* If it's a TV, we already set the output timing in mode_fixup.
1192 * Otherwise, the output timing is equal to the input timing.
1193 */
ea5b213a 1194 if (!intel_sdvo->is_tv && !intel_sdvo->is_lvds) {
e2f0ba97 1195 /* Set the output timing to the screen */
ea5b213a
CW		 1196 intel_sdvo_set_target_output(intel_sdvo,
1197 intel_sdvo->attached_output);
1198 intel_sdvo_set_output_timing(intel_sdvo, &input_dtd);
e2f0ba97 1199 }
79e53945
JB		 1200
1201 /* Set the input timing to the screen. Assume always input 0. */
ea5b213a 1202 intel_sdvo_set_target_input(intel_sdvo, true, false);
79e53945 1203
ea5b213a
CW		 1204 if (intel_sdvo->is_tv)
1205 intel_sdvo_set_tv_format(intel_sdvo);
7026d4ac 1206
e2f0ba97 1207 /* We would like to use intel_sdvo_create_preferred_input_timing() to
79e53945
JB		 1208 * provide the device with a timing it can support, if it supports that
1209 * feature. However, presumably we would need to adjust the CRTC to
1210 * output the preferred timing, and we don't support that currently.
1211 */
e2f0ba97 1212#if 0
c751ce4f 1213 success = intel_sdvo_create_preferred_input_timing(encoder, clock,
e2f0ba97
JB		 1214 width, height);
1215 if (success) {
1216 struct intel_sdvo_dtd *input_dtd;
1217
c751ce4f
EA		 1218 intel_sdvo_get_preferred_input_timing(encoder, &input_dtd);
1219 intel_sdvo_set_input_timing(encoder, &input_dtd);
e2f0ba97
JB		 1220 }
1221#else
ea5b213a 1222 intel_sdvo_set_input_timing(intel_sdvo, &input_dtd);
e2f0ba97 1223#endif
79e53945
JB		 1224
1225 switch (intel_sdvo_get_pixel_multiplier(mode)) {
1226 case 1:
ea5b213a 1227 intel_sdvo_set_clock_rate_mult(intel_sdvo,
79e53945
JB		 1228 SDVO_CLOCK_RATE_MULT_1X);
1229 break;
1230 case 2:
ea5b213a 1231 intel_sdvo_set_clock_rate_mult(intel_sdvo,
79e53945
JB		 1232 SDVO_CLOCK_RATE_MULT_2X);
1233 break;
1234 case 4:
ea5b213a 1235 intel_sdvo_set_clock_rate_mult(intel_sdvo,
79e53945
JB		 1236 SDVO_CLOCK_RATE_MULT_4X);
1237 break;
1238 }
1239
1240 /* Set the SDVO control regs. */
e2f0ba97 1241 if (IS_I965G(dev)) {
81a14b46
AJ		 1242 sdvox |= SDVO_BORDER_ENABLE;
1243 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1244 sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
1245 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1246 sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
e2f0ba97 1247 } else {
ea5b213a
CW		 1248 sdvox |= I915_READ(intel_sdvo->sdvo_reg);
1249 switch (intel_sdvo->sdvo_reg) {
e2f0ba97
JB		 1250 case SDVOB:
1251 sdvox &= SDVOB_PRESERVE_MASK;
1252 break;
1253 case SDVOC:
1254 sdvox &= SDVOC_PRESERVE_MASK;
1255 break;
1256 }
1257 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1258 }
79e53945
JB		 1259 if (intel_crtc->pipe == 1)
1260 sdvox |= SDVO_PIPE_B_SELECT;
1261
1262 sdvo_pixel_multiply = intel_sdvo_get_pixel_multiplier(mode);
1263 if (IS_I965G(dev)) {
e2f0ba97
JB		 1264 /* done in crtc_mode_set as the dpll_md reg must be written early */
1265 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1266 /* done in crtc_mode_set as it lives inside the dpll register */
79e53945
JB		 1267 } else {
1268 sdvox |= (sdvo_pixel_multiply - 1) << SDVO_PORT_MULTIPLY_SHIFT;
1269 }
1270
ea5b213a 1271 if (intel_sdvo->sdvo_flags & SDVO_NEED_TO_STALL)
12682a97 1272 sdvox |= SDVO_STALL_SELECT;
ea5b213a 1273 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
79e53945
JB		 1274}
1275
1276static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1277{
1278 struct drm_device *dev = encoder->dev;
1279 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 1280 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
79e53945
JB		 1281 u32 temp;
1282
1283 if (mode != DRM_MODE_DPMS_ON) {
ea5b213a 1284 intel_sdvo_set_active_outputs(intel_sdvo, 0);
79e53945 1285 if (0)
ea5b213a 1286 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
79e53945
JB		 1287
1288 if (mode == DRM_MODE_DPMS_OFF) {
ea5b213a 1289 temp = I915_READ(intel_sdvo->sdvo_reg);
79e53945 1290 if ((temp & SDVO_ENABLE) != 0) {
ea5b213a 1291 intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
79e53945
JB		 1292 }
1293 }
1294 } else {
1295 bool input1, input2;
1296 int i;
1297 u8 status;
1298
ea5b213a 1299 temp = I915_READ(intel_sdvo->sdvo_reg);
79e53945 1300 if ((temp & SDVO_ENABLE) == 0)
ea5b213a 1301 intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
79e53945
JB		 1302 for (i = 0; i < 2; i++)
1303 intel_wait_for_vblank(dev);
1304
ea5b213a 1305 status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1,
79e53945
JB		 1306 &input2);
1307
1308
1309 /* Warn if the device reported failure to sync.
1310 * A lot of SDVO devices fail to notify of sync, but it's
1311 * a given it the status is a success, we succeeded.
1312 */
1313 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
8a4c47f3 1314 DRM_DEBUG_KMS("First %s output reported failure to "
ea5b213a 1315 "sync\n", SDVO_NAME(intel_sdvo));
79e53945
JB		 1316 }
1317
1318 if (0)
ea5b213a
CW		 1319 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
1320 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
79e53945
JB		 1321 }
1322 return;
1323}
1324
79e53945
JB		 1325static int intel_sdvo_mode_valid(struct drm_connector *connector,
1326 struct drm_display_mode *mode)
1327{
d2a82a6f 1328 struct drm_encoder *encoder = intel_attached_encoder(connector);
ea5b213a 1329 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
79e53945
JB		 1330
1331 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1332 return MODE_NO_DBLESCAN;
1333
ea5b213a 1334 if (intel_sdvo->pixel_clock_min > mode->clock)
79e53945
JB		 1335 return MODE_CLOCK_LOW;
1336
ea5b213a 1337 if (intel_sdvo->pixel_clock_max < mode->clock)
79e53945
JB		 1338 return MODE_CLOCK_HIGH;
1339
ea5b213a
CW		 1340 if (intel_sdvo->is_lvds == true) {
1341 if (intel_sdvo->sdvo_lvds_fixed_mode == NULL)
12682a97 1342 return MODE_PANEL;
1343
ea5b213a 1344 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
12682a97 1345 return MODE_PANEL;
1346
ea5b213a 1347 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
12682a97 1348 return MODE_PANEL;
1349 }
1350
79e53945
JB		 1351 return MODE_OK;
1352}
1353
ea5b213a 1354static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
79e53945
JB		 1355{
1356 u8 status;
1357
ea5b213a
CW		 1358 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_DEVICE_CAPS, NULL, 0);
1359 status = intel_sdvo_read_response(intel_sdvo, caps, sizeof(*caps));
79e53945
JB		 1360 if (status != SDVO_CMD_STATUS_SUCCESS)
1361 return false;
1362
1363 return true;
1364}
1365
d2a82a6f
ZW		 1366/* No use! */
1367#if 0
79e53945
JB		 1368struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB)
1369{
1370 struct drm_connector *connector = NULL;
ea5b213a
CW		 1371 struct intel_sdvo *iout = NULL;
1372 struct intel_sdvo *sdvo;
79e53945
JB		 1373
1374 /* find the sdvo connector */
1375 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
ea5b213a 1376 iout = to_intel_sdvo(connector);
79e53945
JB		 1377
1378 if (iout->type != INTEL_OUTPUT_SDVO)
1379 continue;
1380
1381 sdvo = iout->dev_priv;
1382
c751ce4f 1383 if (sdvo->sdvo_reg == SDVOB && sdvoB)
79e53945
JB		 1384 return connector;
1385
c751ce4f 1386 if (sdvo->sdvo_reg == SDVOC && !sdvoB)
79e53945
JB		 1387 return connector;
1388
1389 }
1390
1391 return NULL;
1392}
1393
1394int intel_sdvo_supports_hotplug(struct drm_connector *connector)
1395{
1396 u8 response[2];
1397 u8 status;
ea5b213a 1398 struct intel_sdvo *intel_sdvo;
8a4c47f3 1399 DRM_DEBUG_KMS("\n");
79e53945
JB		 1400
1401 if (!connector)
1402 return 0;
1403
ea5b213a 1404 intel_sdvo = to_intel_sdvo(connector);
79e53945 1405
ea5b213a
CW		 1406 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1407 status = intel_sdvo_read_response(intel_sdvo, &response, 2);
79e53945
JB		 1408
1409 if (response[0] !=0)
1410 return 1;
1411
1412 return 0;
1413}
1414
1415void intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
1416{
1417 u8 response[2];
1418 u8 status;
ea5b213a 1419 struct intel_sdvo *intel_sdvo = to_intel_sdvo(connector);
79e53945 1420
ea5b213a
CW		 1421 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1422 intel_sdvo_read_response(intel_sdvo, &response, 2);
79e53945
JB		 1423
1424 if (on) {
ea5b213a
CW		 1425 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1426 status = intel_sdvo_read_response(intel_sdvo, &response, 2);
79e53945 1427
ea5b213a 1428 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
79e53945
JB		 1429 } else {
1430 response[0] = 0;
1431 response[1] = 0;
ea5b213a 1432 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
79e53945
JB		 1433 }
1434
ea5b213a
CW		 1435 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1436 intel_sdvo_read_response(intel_sdvo, &response, 2);
79e53945 1437}
d2a82a6f 1438#endif
79e53945 1439
fb7a46f3 1440static bool
ea5b213a 1441intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
fb7a46f3 1442{
fb7a46f3 1443 int caps = 0;
1444
ea5b213a 1445 if (intel_sdvo->caps.output_flags &
fb7a46f3 1446 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1))
1447 caps++;
ea5b213a 1448 if (intel_sdvo->caps.output_flags &
fb7a46f3 1449 (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1))
1450 caps++;
ea5b213a 1451 if (intel_sdvo->caps.output_flags &
19e1f888 1452 (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_SVID1))
fb7a46f3 1453 caps++;
ea5b213a 1454 if (intel_sdvo->caps.output_flags &
fb7a46f3 1455 (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_CVBS1))
1456 caps++;
ea5b213a 1457 if (intel_sdvo->caps.output_flags &
fb7a46f3 1458 (SDVO_OUTPUT_YPRPB0 | SDVO_OUTPUT_YPRPB1))
1459 caps++;
1460
ea5b213a 1461 if (intel_sdvo->caps.output_flags &
fb7a46f3 1462 (SDVO_OUTPUT_SCART0 | SDVO_OUTPUT_SCART1))
1463 caps++;
1464
ea5b213a 1465 if (intel_sdvo->caps.output_flags &
fb7a46f3 1466 (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1))
1467 caps++;
1468
1469 return (caps > 1);
1470}
1471
57cdaf90
KP		 1472static struct drm_connector *
1473intel_find_analog_connector(struct drm_device *dev)
1474{
1475 struct drm_connector *connector;
d2a82a6f 1476 struct drm_encoder *encoder;
ea5b213a 1477 struct intel_sdvo *intel_sdvo;
57cdaf90 1478
d2a82a6f 1479 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
ea5b213a
CW		 1480 intel_sdvo = enc_to_intel_sdvo(encoder);
1481 if (intel_sdvo->base.type == INTEL_OUTPUT_ANALOG) {
d2a82a6f 1482 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
90a78e8f 1483 if (encoder == intel_attached_encoder(connector))
d2a82a6f
ZW		 1484 return connector;
1485 }
1486 }
57cdaf90
KP		 1487 }
1488 return NULL;
1489}
1490
1491static int
1492intel_analog_is_connected(struct drm_device *dev)
1493{
1494 struct drm_connector *analog_connector;
1495 analog_connector = intel_find_analog_connector(dev);
1496
1497 if (!analog_connector)
1498 return false;
1499
1500 if (analog_connector->funcs->detect(analog_connector) ==
1501 connector_status_disconnected)
1502 return false;
1503
1504 return true;
1505}
1506
2b8d33f7 1507enum drm_connector_status
149c36a3 1508intel_sdvo_hdmi_sink_detect(struct drm_connector *connector)
9dff6af8 1509{
d2a82a6f 1510 struct drm_encoder *encoder = intel_attached_encoder(connector);
ea5b213a 1511 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
615fb93f 1512 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
2b8d33f7 1513 enum drm_connector_status status = connector_status_connected;
9dff6af8
ML		 1514 struct edid *edid = NULL;
1515
ea5b213a 1516 edid = drm_get_edid(connector, intel_sdvo->base.ddc_bus);
57cdaf90 1517
7c3f0a27 1518 /* This is only applied to SDVO cards with multiple outputs */
ea5b213a 1519 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
7c3f0a27 1520 uint8_t saved_ddc, temp_ddc;
ea5b213a
CW		 1521 saved_ddc = intel_sdvo->ddc_bus;
1522 temp_ddc = intel_sdvo->ddc_bus >> 1;
7c3f0a27
ZY		 1523 /*
1524 * Don't use the 1 as the argument of DDC bus switch to get
1525 * the EDID. It is used for SDVO SPD ROM.
1526 */
1527 while(temp_ddc > 1) {
ea5b213a
CW		 1528 intel_sdvo->ddc_bus = temp_ddc;
1529 edid = drm_get_edid(connector, intel_sdvo->base.ddc_bus);
7c3f0a27
ZY		 1530 if (edid) {
1531 /*
1532 * When we can get the EDID, maybe it is the
1533 * correct DDC bus. Update it.
1534 */
ea5b213a 1535 intel_sdvo->ddc_bus = temp_ddc;
7c3f0a27
ZY		 1536 break;
1537 }
1538 temp_ddc >>= 1;
1539 }
1540 if (edid == NULL)
ea5b213a 1541 intel_sdvo->ddc_bus = saved_ddc;
7c3f0a27 1542 }
57cdaf90
KP		 1543 /* when there is no edid and no monitor is connected with VGA
1544 * port, try to use the CRT ddc to read the EDID for DVI-connector
1545 */
ea5b213a 1546 if (edid == NULL && intel_sdvo->analog_ddc_bus &&
d2a82a6f 1547 !intel_analog_is_connected(connector->dev))
ea5b213a 1548 edid = drm_get_edid(connector, intel_sdvo->analog_ddc_bus);
149c36a3 1549
9dff6af8 1550 if (edid != NULL) {
149c36a3 1551 bool is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
615fb93f 1552 bool need_digital = !!(intel_sdvo_connector->output_flag & SDVO_TMDS_MASK);
2b8d33f7 1553
149c36a3
AJ		 1554 /* DDC bus is shared, match EDID to connector type */
1555 if (is_digital && need_digital)
ea5b213a 1556 intel_sdvo->is_hdmi = drm_detect_hdmi_monitor(edid);
149c36a3
AJ		 1557 else if (is_digital != need_digital)
1558 status = connector_status_disconnected;
2b8d33f7 1559
149c36a3
AJ		 1560 connector->display_info.raw_edid = NULL;
1561 } else
2b8d33f7 1562 status = connector_status_disconnected;
149c36a3
AJ		 1563
1564 kfree(edid);
2b8d33f7 1565
1566 return status;
9dff6af8
ML		 1567}
1568
79e53945
JB		 1569static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connector)
1570{
fb7a46f3 1571 uint16_t response;
79e53945 1572 u8 status;
d2a82a6f 1573 struct drm_encoder *encoder = intel_attached_encoder(connector);
ea5b213a 1574 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
615fb93f 1575 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
14571b4c 1576 enum drm_connector_status ret;
79e53945 1577
ea5b213a 1578 intel_sdvo_write_cmd(intel_sdvo,
ce6feabd 1579 SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0);
ea5b213a 1580 if (intel_sdvo->is_tv) {
d09c23de
ZY		 1581 /* add 30ms delay when the output type is SDVO-TV */
1582 mdelay(30);
1583 }
ea5b213a 1584 status = intel_sdvo_read_response(intel_sdvo, &response, 2);
79e53945 1585
51c8b407 1586 DRM_DEBUG_KMS("SDVO response %d %d\n", response & 0xff, response >> 8);
e2f0ba97
JB		 1587
1588 if (status != SDVO_CMD_STATUS_SUCCESS)
1589 return connector_status_unknown;
1590
fb7a46f3 1591 if (response == 0)
79e53945 1592 return connector_status_disconnected;
fb7a46f3 1593
ea5b213a 1594 intel_sdvo->attached_output = response;
14571b4c 1595
615fb93f 1596 if ((intel_sdvo_connector->output_flag & response) == 0)
14571b4c 1597 ret = connector_status_disconnected;
149c36a3
AJ		 1598 else if (response & SDVO_TMDS_MASK)
1599 ret = intel_sdvo_hdmi_sink_detect(connector);
14571b4c
ZW		 1600 else
1601 ret = connector_status_connected;
1602
1603 /* May update encoder flag for like clock for SDVO TV, etc.*/
1604 if (ret == connector_status_connected) {
ea5b213a
CW		 1605 intel_sdvo->is_tv = false;
1606 intel_sdvo->is_lvds = false;
1607 intel_sdvo->base.needs_tv_clock = false;
14571b4c
ZW		 1608
1609 if (response & SDVO_TV_MASK) {
ea5b213a
CW		 1610 intel_sdvo->is_tv = true;
1611 intel_sdvo->base.needs_tv_clock = true;
14571b4c
ZW		 1612 }
1613 if (response & SDVO_LVDS_MASK)
ea5b213a 1614 intel_sdvo->is_lvds = true;
fb7a46f3 1615 }
14571b4c
ZW		 1616
1617 return ret;
79e53945
JB		 1618}
1619
e2f0ba97 1620static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
79e53945 1621{
d2a82a6f 1622 struct drm_encoder *encoder = intel_attached_encoder(connector);
ea5b213a 1623 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
57cdaf90 1624 int num_modes;
79e53945
JB		 1625
1626 /* set the bus switch and get the modes */
ea5b213a 1627 num_modes = intel_ddc_get_modes(connector, intel_sdvo->base.ddc_bus);
79e53945 1628
57cdaf90
KP		 1629 /*
1630 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1631 * link between analog and digital outputs. So, if the regular SDVO
1632 * DDC fails, check to see if the analog output is disconnected, in
1633 * which case we'll look there for the digital DDC data.
e2f0ba97 1634 */
57cdaf90 1635 if (num_modes == 0 &&
ea5b213a 1636 intel_sdvo->analog_ddc_bus &&
d2a82a6f 1637 !intel_analog_is_connected(connector->dev)) {
57cdaf90
KP		 1638 /* Switch to the analog ddc bus and try that
1639 */
ea5b213a 1640 (void) intel_ddc_get_modes(connector, intel_sdvo->analog_ddc_bus);
e2f0ba97 1641 }
e2f0ba97
JB		 1642}
1643
1644/*
1645 * Set of SDVO TV modes.
1646 * Note! This is in reply order (see loop in get_tv_modes).
1647 * XXX: all 60Hz refresh?
1648 */
1649struct drm_display_mode sdvo_tv_modes[] = {
7026d4ac
ZW		 1650 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1651 416, 0, 200, 201, 232, 233, 0,
e2f0ba97 1652 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1653 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1654 416, 0, 240, 241, 272, 273, 0,
e2f0ba97 1655 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1656 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1657 496, 0, 300, 301, 332, 333, 0,
e2f0ba97 1658 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1659 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1660 736, 0, 350, 351, 382, 383, 0,
e2f0ba97 1661 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1662 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1663 736, 0, 400, 401, 432, 433, 0,
e2f0ba97 1664 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1665 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1666 736, 0, 480, 481, 512, 513, 0,
e2f0ba97 1667 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1668 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1669 800, 0, 480, 481, 512, 513, 0,
e2f0ba97 1670 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1671 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1672 800, 0, 576, 577, 608, 609, 0,
e2f0ba97 1673 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1674 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1675 816, 0, 350, 351, 382, 383, 0,
e2f0ba97 1676 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1677 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1678 816, 0, 400, 401, 432, 433, 0,
e2f0ba97 1679 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1680 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1681 816, 0, 480, 481, 512, 513, 0,
e2f0ba97 1682 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1683 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1684 816, 0, 540, 541, 572, 573, 0,
e2f0ba97 1685 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1686 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1687 816, 0, 576, 577, 608, 609, 0,
e2f0ba97 1688 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1689 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1690 864, 0, 576, 577, 608, 609, 0,
e2f0ba97 1691 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1692 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1693 896, 0, 600, 601, 632, 633, 0,
e2f0ba97 1694 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1695 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1696 928, 0, 624, 625, 656, 657, 0,
e2f0ba97 1697 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1698 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1699 1016, 0, 766, 767, 798, 799, 0,
e2f0ba97 1700 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1701 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1702 1120, 0, 768, 769, 800, 801, 0,
e2f0ba97 1703 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1704 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1705 1376, 0, 1024, 1025, 1056, 1057, 0,
e2f0ba97
JB		 1706 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1707};
1708
1709static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1710{
d2a82a6f 1711 struct drm_encoder *encoder = intel_attached_encoder(connector);
ea5b213a 1712 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
7026d4ac 1713 struct intel_sdvo_sdtv_resolution_request tv_res;
ce6feabd
ZY		 1714 uint32_t reply = 0, format_map = 0;
1715 int i;
e2f0ba97 1716 uint8_t status;
e2f0ba97 1717
e2f0ba97
JB		 1718
1719 /* Read the list of supported input resolutions for the selected TV
1720 * format.
1721 */
ce6feabd 1722 for (i = 0; i < TV_FORMAT_NUM; i++)
ea5b213a 1723 if (tv_format_names[i] == intel_sdvo->tv_format_name)
ce6feabd
ZY		 1724 break;
1725
1726 format_map = (1 << i);
1727 memcpy(&tv_res, &format_map,
1728 sizeof(struct intel_sdvo_sdtv_resolution_request) >
1729 sizeof(format_map) ? sizeof(format_map) :
1730 sizeof(struct intel_sdvo_sdtv_resolution_request));
1731
ea5b213a 1732 intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output);
ce6feabd 1733
ea5b213a 1734 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
7026d4ac 1735 &tv_res, sizeof(tv_res));
ea5b213a 1736 status = intel_sdvo_read_response(intel_sdvo, &reply, 3);
e2f0ba97
JB		 1737 if (status != SDVO_CMD_STATUS_SUCCESS)
1738 return;
1739
1740 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
7026d4ac
ZW		 1741 if (reply & (1 << i)) {
1742 struct drm_display_mode *nmode;
1743 nmode = drm_mode_duplicate(connector->dev,
1744 &sdvo_tv_modes[i]);
1745 if (nmode)
1746 drm_mode_probed_add(connector, nmode);
1747 }
ce6feabd 1748
e2f0ba97
JB		 1749}
1750
7086c87f
ML		 1751static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1752{
d2a82a6f 1753 struct drm_encoder *encoder = intel_attached_encoder(connector);
ea5b213a 1754 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
7086c87f 1755 struct drm_i915_private *dev_priv = connector->dev->dev_private;
12682a97 1756 struct drm_display_mode *newmode;
7086c87f
ML		 1757
1758 /*
1759 * Attempt to get the mode list from DDC.
1760 * Assume that the preferred modes are
1761 * arranged in priority order.
1762 */
ea5b213a 1763 intel_ddc_get_modes(connector, intel_sdvo->base.ddc_bus);
7086c87f 1764 if (list_empty(&connector->probed_modes) == false)
12682a97 1765 goto end;
7086c87f
ML		 1766
1767 /* Fetch modes from VBT */
1768 if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
7086c87f
ML		 1769 newmode = drm_mode_duplicate(connector->dev,
1770 dev_priv->sdvo_lvds_vbt_mode);
1771 if (newmode != NULL) {
1772 /* Guarantee the mode is preferred */
1773 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1774 DRM_MODE_TYPE_DRIVER);
1775 drm_mode_probed_add(connector, newmode);
1776 }
1777 }
12682a97 1778
1779end:
1780 list_for_each_entry(newmode, &connector->probed_modes, head) {
1781 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
ea5b213a 1782 intel_sdvo->sdvo_lvds_fixed_mode =
12682a97 1783 drm_mode_duplicate(connector->dev, newmode);
1784 break;
1785 }
1786 }
1787
7086c87f
ML		 1788}
1789
e2f0ba97
JB		 1790static int intel_sdvo_get_modes(struct drm_connector *connector)
1791{
615fb93f 1792 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e2f0ba97 1793
615fb93f 1794 if (IS_TV(intel_sdvo_connector))
e2f0ba97 1795 intel_sdvo_get_tv_modes(connector);
615fb93f 1796 else if (IS_LVDS(intel_sdvo_connector))
7086c87f 1797 intel_sdvo_get_lvds_modes(connector);
e2f0ba97
JB		 1798 else
1799 intel_sdvo_get_ddc_modes(connector);
1800
79e53945
JB		 1801 if (list_empty(&connector->probed_modes))
1802 return 0;
1803 return 1;
1804}
1805
b9219c5e
ZY		 1806static
1807void intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
1808{
615fb93f 1809 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
b9219c5e
ZY		 1810 struct drm_device *dev = connector->dev;
1811
615fb93f
CW		 1812 if (IS_TV(intel_sdvo_connector)) {
1813 if (intel_sdvo_connector->left_property)
1814 drm_property_destroy(dev, intel_sdvo_connector->left_property);
1815 if (intel_sdvo_connector->right_property)
1816 drm_property_destroy(dev, intel_sdvo_connector->right_property);
1817 if (intel_sdvo_connector->top_property)
1818 drm_property_destroy(dev, intel_sdvo_connector->top_property);
1819 if (intel_sdvo_connector->bottom_property)
1820 drm_property_destroy(dev, intel_sdvo_connector->bottom_property);
1821 if (intel_sdvo_connector->hpos_property)
1822 drm_property_destroy(dev, intel_sdvo_connector->hpos_property);
1823 if (intel_sdvo_connector->vpos_property)
1824 drm_property_destroy(dev, intel_sdvo_connector->vpos_property);
1825 if (intel_sdvo_connector->saturation_property)
b9219c5e 1826 drm_property_destroy(dev,
615fb93f
CW		 1827 intel_sdvo_connector->saturation_property);
1828 if (intel_sdvo_connector->contrast_property)
b9219c5e 1829 drm_property_destroy(dev,
615fb93f
CW		 1830 intel_sdvo_connector->contrast_property);
1831 if (intel_sdvo_connector->hue_property)
1832 drm_property_destroy(dev, intel_sdvo_connector->hue_property);
b9219c5e 1833 }
615fb93f
CW		 1834 if (IS_TV(intel_sdvo_connector) || IS_LVDS(intel_sdvo_connector)) {
1835 if (intel_sdvo_connector->brightness_property)
b9219c5e 1836 drm_property_destroy(dev,
615fb93f 1837 intel_sdvo_connector->brightness_property);
b9219c5e
ZY		 1838 }
1839 return;
1840}
1841
79e53945
JB		 1842static void intel_sdvo_destroy(struct drm_connector *connector)
1843{
615fb93f 1844 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
79e53945 1845
615fb93f 1846 if (intel_sdvo_connector->tv_format_property)
ce6feabd 1847 drm_property_destroy(connector->dev,
615fb93f 1848 intel_sdvo_connector->tv_format_property);
b9219c5e 1849
d2a82a6f 1850 intel_sdvo_destroy_enhance_property(connector);
79e53945
JB		 1851 drm_sysfs_connector_remove(connector);
1852 drm_connector_cleanup(connector);
d2a82a6f 1853 kfree(connector);
79e53945
JB		 1854}
1855
ce6feabd
ZY		 1856static int
1857intel_sdvo_set_property(struct drm_connector *connector,
1858 struct drm_property *property,
1859 uint64_t val)
1860{
d2a82a6f 1861 struct drm_encoder *encoder = intel_attached_encoder(connector);
ea5b213a 1862 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
615fb93f 1863 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
ce6feabd
ZY		 1864 struct drm_crtc *crtc = encoder->crtc;
1865 int ret = 0;
1866 bool changed = false;
b9219c5e
ZY		 1867 uint8_t cmd, status;
1868 uint16_t temp_value;
ce6feabd
ZY		 1869
1870 ret = drm_connector_property_set_value(connector, property, val);
1871 if (ret < 0)
1872 goto out;
1873
615fb93f 1874 if (property == intel_sdvo_connector->tv_format_property) {
ce6feabd
ZY		 1875 if (val >= TV_FORMAT_NUM) {
1876 ret = -EINVAL;
1877 goto out;
1878 }
ea5b213a 1879 if (intel_sdvo->tv_format_name ==
615fb93f 1880 intel_sdvo_connector->tv_format_supported[val])
ce6feabd
ZY		 1881 goto out;
1882
615fb93f 1883 intel_sdvo->tv_format_name = intel_sdvo_connector->tv_format_supported[val];
ce6feabd 1884 changed = true;
ce6feabd
ZY		 1885 }
1886
615fb93f 1887 if (IS_TV(intel_sdvo_connector) || IS_LVDS(intel_sdvo_connector)) {
b9219c5e
ZY		 1888 cmd = 0;
1889 temp_value = val;
615fb93f 1890 if (intel_sdvo_connector->left_property == property) {
b9219c5e 1891 drm_connector_property_set_value(connector,
615fb93f
CW		 1892 intel_sdvo_connector->right_property, val);
1893 if (intel_sdvo_connector->left_margin == temp_value)
b9219c5e
ZY		 1894 goto out;
1895
615fb93f
CW		 1896 intel_sdvo_connector->left_margin = temp_value;
1897 intel_sdvo_connector->right_margin = temp_value;
1898 temp_value = intel_sdvo_connector->max_hscan -
1899 intel_sdvo_connector->left_margin;
b9219c5e 1900 cmd = SDVO_CMD_SET_OVERSCAN_H;
615fb93f 1901 } else if (intel_sdvo_connector->right_property == property) {
b9219c5e 1902 drm_connector_property_set_value(connector,
615fb93f
CW		 1903 intel_sdvo_connector->left_property, val);
1904 if (intel_sdvo_connector->right_margin == temp_value)
b9219c5e
ZY		 1905 goto out;
1906
615fb93f
CW		 1907 intel_sdvo_connector->left_margin = temp_value;
1908 intel_sdvo_connector->right_margin = temp_value;
1909 temp_value = intel_sdvo_connector->max_hscan -
1910 intel_sdvo_connector->left_margin;
b9219c5e 1911 cmd = SDVO_CMD_SET_OVERSCAN_H;
615fb93f 1912 } else if (intel_sdvo_connector->top_property == property) {
b9219c5e 1913 drm_connector_property_set_value(connector,
615fb93f
CW		 1914 intel_sdvo_connector->bottom_property, val);
1915 if (intel_sdvo_connector->top_margin == temp_value)
b9219c5e
ZY		 1916 goto out;
1917
615fb93f
CW		 1918 intel_sdvo_connector->top_margin = temp_value;
1919 intel_sdvo_connector->bottom_margin = temp_value;
1920 temp_value = intel_sdvo_connector->max_vscan -
1921 intel_sdvo_connector->top_margin;
b9219c5e 1922 cmd = SDVO_CMD_SET_OVERSCAN_V;
615fb93f 1923 } else if (intel_sdvo_connector->bottom_property == property) {
b9219c5e 1924 drm_connector_property_set_value(connector,
615fb93f
CW		 1925 intel_sdvo_connector->top_property, val);
1926 if (intel_sdvo_connector->bottom_margin == temp_value)
b9219c5e 1927 goto out;
615fb93f
CW		 1928 intel_sdvo_connector->top_margin = temp_value;
1929 intel_sdvo_connector->bottom_margin = temp_value;
1930 temp_value = intel_sdvo_connector->max_vscan -
1931 intel_sdvo_connector->top_margin;
b9219c5e 1932 cmd = SDVO_CMD_SET_OVERSCAN_V;
615fb93f
CW		 1933 } else if (intel_sdvo_connector->hpos_property == property) {
1934 if (intel_sdvo_connector->cur_hpos == temp_value)
b9219c5e
ZY		 1935 goto out;
1936
1937 cmd = SDVO_CMD_SET_POSITION_H;
615fb93f
CW		 1938 intel_sdvo_connector->cur_hpos = temp_value;
1939 } else if (intel_sdvo_connector->vpos_property == property) {
1940 if (intel_sdvo_connector->cur_vpos == temp_value)
b9219c5e
ZY		 1941 goto out;
1942
1943 cmd = SDVO_CMD_SET_POSITION_V;
615fb93f
CW		 1944 intel_sdvo_connector->cur_vpos = temp_value;
1945 } else if (intel_sdvo_connector->saturation_property == property) {
1946 if (intel_sdvo_connector->cur_saturation == temp_value)
b9219c5e
ZY		 1947 goto out;
1948
1949 cmd = SDVO_CMD_SET_SATURATION;
615fb93f
CW		 1950 intel_sdvo_connector->cur_saturation = temp_value;
1951 } else if (intel_sdvo_connector->contrast_property == property) {
1952 if (intel_sdvo_connector->cur_contrast == temp_value)
b9219c5e
ZY		 1953 goto out;
1954
1955 cmd = SDVO_CMD_SET_CONTRAST;
615fb93f
CW		 1956 intel_sdvo_connector->cur_contrast = temp_value;
1957 } else if (intel_sdvo_connector->hue_property == property) {
1958 if (intel_sdvo_connector->cur_hue == temp_value)
b9219c5e
ZY		 1959 goto out;
1960
1961 cmd = SDVO_CMD_SET_HUE;
615fb93f
CW		 1962 intel_sdvo_connector->cur_hue = temp_value;
1963 } else if (intel_sdvo_connector->brightness_property == property) {
1964 if (intel_sdvo_connector->cur_brightness == temp_value)
b9219c5e
ZY		 1965 goto out;
1966
1967 cmd = SDVO_CMD_SET_BRIGHTNESS;
615fb93f 1968 intel_sdvo_connector->cur_brightness = temp_value;
b9219c5e
ZY		 1969 }
1970 if (cmd) {
ea5b213a
CW		 1971 intel_sdvo_write_cmd(intel_sdvo, cmd, &temp_value, 2);
1972 status = intel_sdvo_read_response(intel_sdvo,
b9219c5e
ZY		 1973 NULL, 0);
1974 if (status != SDVO_CMD_STATUS_SUCCESS) {
1975 DRM_DEBUG_KMS("Incorrect SDVO command \n");
1976 return -EINVAL;
1977 }
1978 changed = true;
1979 }
1980 }
ce6feabd
ZY		 1981 if (changed && crtc)
1982 drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
1983 crtc->y, crtc->fb);
1984out:
1985 return ret;
1986}
1987
79e53945
JB		 1988static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
1989 .dpms = intel_sdvo_dpms,
1990 .mode_fixup = intel_sdvo_mode_fixup,
1991 .prepare = intel_encoder_prepare,
1992 .mode_set = intel_sdvo_mode_set,
1993 .commit = intel_encoder_commit,
1994};
1995
1996static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
c9fb15f6 1997 .dpms = drm_helper_connector_dpms,
79e53945
JB		 1998 .detect = intel_sdvo_detect,
1999 .fill_modes = drm_helper_probe_single_connector_modes,
ce6feabd 2000 .set_property = intel_sdvo_set_property,
79e53945
JB		 2001 .destroy = intel_sdvo_destroy,
2002};
2003
2004static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
2005 .get_modes = intel_sdvo_get_modes,
2006 .mode_valid = intel_sdvo_mode_valid,
d2a82a6f 2007 .best_encoder = intel_attached_encoder,
79e53945
JB		 2008};
2009
b358d0a6 2010static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
79e53945 2011{
ea5b213a 2012 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
d2a82a6f 2013
ea5b213a
CW		 2014 if (intel_sdvo->analog_ddc_bus)
2015 intel_i2c_destroy(intel_sdvo->analog_ddc_bus);
d2a82a6f 2016
ea5b213a 2017 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
d2a82a6f 2018 drm_mode_destroy(encoder->dev,
ea5b213a 2019 intel_sdvo->sdvo_lvds_fixed_mode);
d2a82a6f 2020
ea5b213a 2021 intel_encoder_destroy(encoder);
79e53945
JB		 2022}
2023
2024static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
2025 .destroy = intel_sdvo_enc_destroy,
2026};
2027
2028
e2f0ba97
JB		 2029/**
2030 * Choose the appropriate DDC bus for control bus switch command for this
2031 * SDVO output based on the controlled output.
2032 *
2033 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
2034 * outputs, then LVDS outputs.
2035 */
2036static void
b1083333 2037intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
ea5b213a 2038 struct intel_sdvo *sdvo, u32 reg)
e2f0ba97 2039{
b1083333 2040 struct sdvo_device_mapping *mapping;
e2f0ba97 2041
b1083333
AJ		 2042 if (IS_SDVOB(reg))
2043 mapping = &(dev_priv->sdvo_mappings[0]);
2044 else
2045 mapping = &(dev_priv->sdvo_mappings[1]);
e2f0ba97 2046
b1083333 2047 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
e2f0ba97
JB		 2048}
2049
2050static bool
ea5b213a 2051intel_sdvo_get_digital_encoding_mode(struct intel_sdvo *intel_sdvo, int device)
e2f0ba97 2052{
e2f0ba97
JB		 2053 uint8_t status;
2054
14571b4c 2055 if (device == 0)
ea5b213a 2056 intel_sdvo_set_target_output(intel_sdvo, SDVO_OUTPUT_TMDS0);
14571b4c 2057 else
ea5b213a 2058 intel_sdvo_set_target_output(intel_sdvo, SDVO_OUTPUT_TMDS1);
e2f0ba97 2059
ea5b213a
CW		 2060 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_ENCODE, NULL, 0);
2061 status = intel_sdvo_read_response(intel_sdvo, &intel_sdvo->is_hdmi, 1);
e2f0ba97
JB		 2062 if (status != SDVO_CMD_STATUS_SUCCESS)
2063 return false;
2064 return true;
2065}
2066
ea5b213a
CW		 2067static struct intel_sdvo *
2068intel_sdvo_chan_to_intel_sdvo(struct intel_i2c_chan *chan)
619ac3b7
ML		 2069{
2070 struct drm_device *dev = chan->drm_dev;
d2a82a6f 2071 struct drm_encoder *encoder;
619ac3b7 2072
d2a82a6f 2073 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
ea5b213a
CW		 2074 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
2075 if (intel_sdvo->base.ddc_bus == &chan->adapter)
2076 return intel_sdvo;
619ac3b7 2077 }
ea5b213a
CW		 2078
2079 return NULL;;
619ac3b7
ML		 2080}
2081
2082static int intel_sdvo_master_xfer(struct i2c_adapter *i2c_adap,
2083 struct i2c_msg msgs[], int num)
2084{
ea5b213a 2085 struct intel_sdvo *intel_sdvo;
619ac3b7 2086 struct i2c_algo_bit_data *algo_data;
f9c10a9b 2087 const struct i2c_algorithm *algo;
619ac3b7
ML		 2088
2089 algo_data = (struct i2c_algo_bit_data *)i2c_adap->algo_data;
ea5b213a
CW		 2090 intel_sdvo =
2091 intel_sdvo_chan_to_intel_sdvo((struct intel_i2c_chan *)
2092 (algo_data->data));
2093 if (intel_sdvo == NULL)
619ac3b7
ML		 2094 return -EINVAL;
2095
ea5b213a 2096 algo = intel_sdvo->base.i2c_bus->algo;
619ac3b7 2097
ea5b213a 2098 intel_sdvo_set_control_bus_switch(intel_sdvo, intel_sdvo->ddc_bus);
619ac3b7
ML		 2099 return algo->master_xfer(i2c_adap, msgs, num);
2100}
2101
2102static struct i2c_algorithm intel_sdvo_i2c_bit_algo = {
2103 .master_xfer = intel_sdvo_master_xfer,
2104};
2105
714605e4 2106static u8
c751ce4f 2107intel_sdvo_get_slave_addr(struct drm_device *dev, int sdvo_reg)
714605e4 2108{
2109 struct drm_i915_private *dev_priv = dev->dev_private;
2110 struct sdvo_device_mapping *my_mapping, *other_mapping;
2111
461ed3ca 2112 if (IS_SDVOB(sdvo_reg)) {
714605e4 2113 my_mapping = &dev_priv->sdvo_mappings[0];
2114 other_mapping = &dev_priv->sdvo_mappings[1];
2115 } else {
2116 my_mapping = &dev_priv->sdvo_mappings[1];
2117 other_mapping = &dev_priv->sdvo_mappings[0];
2118 }
2119
2120 /* If the BIOS described our SDVO device, take advantage of it. */
2121 if (my_mapping->slave_addr)
2122 return my_mapping->slave_addr;
2123
2124 /* If the BIOS only described a different SDVO device, use the
2125 * address that it isn't using.
2126 */
2127 if (other_mapping->slave_addr) {
2128 if (other_mapping->slave_addr == 0x70)
2129 return 0x72;
2130 else
2131 return 0x70;
2132 }
2133
2134 /* No SDVO device info is found for another DVO port,
2135 * so use mapping assumption we had before BIOS parsing.
2136 */
461ed3ca 2137 if (IS_SDVOB(sdvo_reg))
714605e4 2138 return 0x70;
2139 else
2140 return 0x72;
2141}
2142
14571b4c
ZW		 2143static void
2144intel_sdvo_connector_create (struct drm_encoder *encoder,
2145 struct drm_connector *connector)
2146{
2147 drm_connector_init(encoder->dev, connector, &intel_sdvo_connector_funcs,
2148 connector->connector_type);
6070a4a9 2149
14571b4c
ZW		 2150 drm_connector_helper_add(connector, &intel_sdvo_connector_helper_funcs);
2151
2152 connector->interlace_allowed = 0;
2153 connector->doublescan_allowed = 0;
2154 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
2155
2156 drm_mode_connector_attach_encoder(connector, encoder);
2157 drm_sysfs_connector_add(connector);
2158}
6070a4a9 2159
fb7a46f3 2160static bool
ea5b213a 2161intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
fb7a46f3 2162{
ea5b213a 2163 struct drm_encoder *encoder = &intel_sdvo->base.enc;
14571b4c
ZW		 2164 struct drm_connector *connector;
2165 struct intel_connector *intel_connector;
615fb93f 2166 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2167
615fb93f
CW		 2168 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2169 if (!intel_sdvo_connector)
14571b4c
ZW		 2170 return false;
2171
14571b4c 2172 if (device == 0) {
ea5b213a 2173 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
615fb93f 2174 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
14571b4c 2175 } else if (device == 1) {
ea5b213a 2176 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
615fb93f 2177 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
14571b4c
ZW		 2178 }
2179
615fb93f 2180 intel_connector = &intel_sdvo_connector->base;
14571b4c 2181 connector = &intel_connector->base;
eb1f8e4f 2182 connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
14571b4c
ZW		 2183 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2184 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2185
ea5b213a
CW		 2186 if (intel_sdvo_get_supp_encode(intel_sdvo, &intel_sdvo->encode)
2187 && intel_sdvo_get_digital_encoding_mode(intel_sdvo, device)
2188 && intel_sdvo->is_hdmi) {
14571b4c 2189 /* enable hdmi encoding mode if supported */
ea5b213a
CW		 2190 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
2191 intel_sdvo_set_colorimetry(intel_sdvo,
14571b4c
ZW		 2192 SDVO_COLORIMETRY_RGB256);
2193 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
2194 }
ea5b213a
CW		 2195 intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2196 (1 << INTEL_ANALOG_CLONE_BIT));
14571b4c
ZW		 2197
2198 intel_sdvo_connector_create(encoder, connector);
2199
2200 return true;
2201}
2202
2203static bool
ea5b213a 2204intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
14571b4c 2205{
ea5b213a 2206 struct drm_encoder *encoder = &intel_sdvo->base.enc;
14571b4c
ZW		 2207 struct drm_connector *connector;
2208 struct intel_connector *intel_connector;
615fb93f 2209 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2210
615fb93f
CW		 2211 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2212 if (!intel_sdvo_connector)
2213 return false;
14571b4c 2214
615fb93f 2215 intel_connector = &intel_sdvo_connector->base;
14571b4c
ZW		 2216 connector = &intel_connector->base;
2217 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2218 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
14571b4c 2219
ea5b213a 2220 intel_sdvo->controlled_output |= type;
615fb93f 2221 intel_sdvo_connector->output_flag = type;
14571b4c 2222
ea5b213a
CW		 2223 intel_sdvo->is_tv = true;
2224 intel_sdvo->base.needs_tv_clock = true;
2225 intel_sdvo->base.clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
14571b4c
ZW		 2226
2227 intel_sdvo_connector_create(encoder, connector);
2228
2229 intel_sdvo_tv_create_property(connector, type);
2230
2231 intel_sdvo_create_enhance_property(connector);
2232
2233 return true;
2234}
2235
2236static bool
ea5b213a 2237intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2238{
ea5b213a 2239 struct drm_encoder *encoder = &intel_sdvo->base.enc;
14571b4c
ZW		 2240 struct drm_connector *connector;
2241 struct intel_connector *intel_connector;
615fb93f 2242 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2243
615fb93f
CW		 2244 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2245 if (!intel_sdvo_connector)
2246 return false;
14571b4c 2247
615fb93f 2248 intel_connector = &intel_sdvo_connector->base;
14571b4c 2249 connector = &intel_connector->base;
eb1f8e4f 2250 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
14571b4c
ZW		 2251 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2252 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
14571b4c
ZW		 2253
2254 if (device == 0) {
ea5b213a 2255 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
615fb93f 2256 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
14571b4c 2257 } else if (device == 1) {
ea5b213a 2258 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
615fb93f 2259 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
14571b4c
ZW		 2260 }
2261
ea5b213a
CW		 2262 intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2263 (1 << INTEL_ANALOG_CLONE_BIT));
14571b4c
ZW		 2264
2265 intel_sdvo_connector_create(encoder, connector);
2266 return true;
2267}
2268
2269static bool
ea5b213a 2270intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2271{
ea5b213a 2272 struct drm_encoder *encoder = &intel_sdvo->base.enc;
14571b4c
ZW		 2273 struct drm_connector *connector;
2274 struct intel_connector *intel_connector;
615fb93f 2275 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2276
615fb93f
CW		 2277 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2278 if (!intel_sdvo_connector)
2279 return false;
14571b4c 2280
615fb93f
CW		 2281 intel_connector = &intel_sdvo_connector->base;
2282 connector = &intel_connector->base;
14571b4c
ZW		 2283 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2284 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
14571b4c 2285
ea5b213a 2286 intel_sdvo->is_lvds = true;
14571b4c
ZW		 2287
2288 if (device == 0) {
ea5b213a 2289 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
615fb93f 2290 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
14571b4c 2291 } else if (device == 1) {
ea5b213a 2292 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
615fb93f 2293 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
14571b4c
ZW		 2294 }
2295
ea5b213a
CW		 2296 intel_sdvo->base.clone_mask = ((1 << INTEL_ANALOG_CLONE_BIT) |
2297 (1 << INTEL_SDVO_LVDS_CLONE_BIT));
14571b4c
ZW		 2298
2299 intel_sdvo_connector_create(encoder, connector);
2300 intel_sdvo_create_enhance_property(connector);
2301 return true;
2302}
2303
2304static bool
ea5b213a 2305intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
14571b4c 2306{
ea5b213a
CW		 2307 intel_sdvo->is_tv = false;
2308 intel_sdvo->base.needs_tv_clock = false;
2309 intel_sdvo->is_lvds = false;
fb7a46f3 2310
14571b4c 2311 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
fb7a46f3 2312
14571b4c 2313 if (flags & SDVO_OUTPUT_TMDS0)
ea5b213a 2314 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
14571b4c
ZW		 2315 return false;
2316
2317 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
ea5b213a 2318 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
14571b4c
ZW		 2319 return false;
2320
2321 /* TV has no XXX1 function block */
a1f4b7ff 2322 if (flags & SDVO_OUTPUT_SVID0)
ea5b213a 2323 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
14571b4c
ZW		 2324 return false;
2325
2326 if (flags & SDVO_OUTPUT_CVBS0)
ea5b213a 2327 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
14571b4c 2328 return false;
fb7a46f3 2329
14571b4c 2330 if (flags & SDVO_OUTPUT_RGB0)
ea5b213a 2331 if (!intel_sdvo_analog_init(intel_sdvo, 0))
14571b4c
ZW		 2332 return false;
2333
2334 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
ea5b213a 2335 if (!intel_sdvo_analog_init(intel_sdvo, 1))
14571b4c
ZW		 2336 return false;
2337
2338 if (flags & SDVO_OUTPUT_LVDS0)
ea5b213a 2339 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
14571b4c
ZW		 2340 return false;
2341
2342 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
ea5b213a 2343 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
14571b4c 2344 return false;
fb7a46f3 2345
14571b4c 2346 if ((flags & SDVO_OUTPUT_MASK) == 0) {
fb7a46f3 2347 unsigned char bytes[2];
2348
ea5b213a
CW		 2349 intel_sdvo->controlled_output = 0;
2350 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
51c8b407 2351 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
ea5b213a 2352 SDVO_NAME(intel_sdvo),
51c8b407 2353 bytes[0], bytes[1]);
14571b4c 2354 return false;
fb7a46f3 2355 }
ea5b213a 2356 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1);
fb7a46f3 2357
14571b4c 2358 return true;
fb7a46f3 2359}
2360
14571b4c 2361static void intel_sdvo_tv_create_property(struct drm_connector *connector, int type)
ce6feabd 2362{
d2a82a6f 2363 struct drm_encoder *encoder = intel_attached_encoder(connector);
ea5b213a 2364 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
615fb93f 2365 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
ce6feabd
ZY		 2366 struct intel_sdvo_tv_format format;
2367 uint32_t format_map, i;
2368 uint8_t status;
2369
ea5b213a 2370 intel_sdvo_set_target_output(intel_sdvo, type);
ce6feabd 2371
ea5b213a 2372 intel_sdvo_write_cmd(intel_sdvo,
ce6feabd 2373 SDVO_CMD_GET_SUPPORTED_TV_FORMATS, NULL, 0);
ea5b213a 2374 status = intel_sdvo_read_response(intel_sdvo,
ce6feabd
ZY		 2375 &format, sizeof(format));
2376 if (status != SDVO_CMD_STATUS_SUCCESS)
2377 return;
2378
2379 memcpy(&format_map, &format, sizeof(format) > sizeof(format_map) ?
2380 sizeof(format_map) : sizeof(format));
2381
2382 if (format_map == 0)
2383 return;
2384
615fb93f 2385 intel_sdvo_connector->format_supported_num = 0;
ce6feabd
ZY		 2386 for (i = 0 ; i < TV_FORMAT_NUM; i++)
2387 if (format_map & (1 << i)) {
615fb93f
CW		 2388 intel_sdvo_connector->tv_format_supported
2389 [intel_sdvo_connector->format_supported_num++] =
ce6feabd
ZY		 2390 tv_format_names[i];
2391 }
2392
2393
615fb93f 2394 intel_sdvo_connector->tv_format_property =
ce6feabd
ZY		 2395 drm_property_create(
2396 connector->dev, DRM_MODE_PROP_ENUM,
615fb93f 2397 "mode", intel_sdvo_connector->format_supported_num);
ce6feabd 2398
615fb93f 2399 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
ce6feabd 2400 drm_property_add_enum(
615fb93f
CW		 2401 intel_sdvo_connector->tv_format_property, i,
2402 i, intel_sdvo_connector->tv_format_supported[i]);
ce6feabd 2403
615fb93f 2404 intel_sdvo->tv_format_name = intel_sdvo_connector->tv_format_supported[0];
ce6feabd 2405 drm_connector_attach_property(
615fb93f 2406 connector, intel_sdvo_connector->tv_format_property, 0);
ce6feabd
ZY		 2407
2408}
2409
b9219c5e
ZY		 2410static void intel_sdvo_create_enhance_property(struct drm_connector *connector)
2411{
d2a82a6f 2412 struct drm_encoder *encoder = intel_attached_encoder(connector);
ea5b213a 2413 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
615fb93f 2414 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
b9219c5e
ZY		 2415 struct intel_sdvo_enhancements_reply sdvo_data;
2416 struct drm_device *dev = connector->dev;
2417 uint8_t status;
2418 uint16_t response, data_value[2];
2419
ea5b213a 2420 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
b9219c5e 2421 NULL, 0);
ea5b213a 2422 status = intel_sdvo_read_response(intel_sdvo, &sdvo_data,
b9219c5e
ZY		 2423 sizeof(sdvo_data));
2424 if (status != SDVO_CMD_STATUS_SUCCESS) {
2425 DRM_DEBUG_KMS(" incorrect response is returned\n");
2426 return;
2427 }
2428 response = *((uint16_t *)&sdvo_data);
2429 if (!response) {
2430 DRM_DEBUG_KMS("No enhancement is supported\n");
2431 return;
2432 }
ea5b213a 2433 if (IS_TV(intel_sdvo_connector)) {
b9219c5e
ZY		 2434 /* when horizontal overscan is supported, Add the left/right
2435 * property
2436 */
2437 if (sdvo_data.overscan_h) {
ea5b213a 2438 intel_sdvo_write_cmd(intel_sdvo,
b9219c5e 2439 SDVO_CMD_GET_MAX_OVERSCAN_H, NULL, 0);
ea5b213a 2440 status = intel_sdvo_read_response(intel_sdvo,
b9219c5e
ZY		 2441 &data_value, 4);
2442 if (status != SDVO_CMD_STATUS_SUCCESS) {
2443 DRM_DEBUG_KMS("Incorrect SDVO max "
2444 "h_overscan\n");
2445 return;
2446 }
ea5b213a 2447 intel_sdvo_write_cmd(intel_sdvo,
b9219c5e 2448 SDVO_CMD_GET_OVERSCAN_H, NULL, 0);
ea5b213a 2449 status = intel_sdvo_read_response(intel_sdvo,
b9219c5e
ZY		 2450 &response, 2);
2451 if (status != SDVO_CMD_STATUS_SUCCESS) {
2452 DRM_DEBUG_KMS("Incorrect SDVO h_overscan\n");
2453 return;
2454 }
ea5b213a
CW		 2455 intel_sdvo_connector->max_hscan = data_value[0];
2456 intel_sdvo_connector->left_margin = data_value[0] - response;
2457 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
2458 intel_sdvo_connector->left_property =
b9219c5e
ZY		 2459 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2460 "left_margin", 2);
ea5b213a
CW		 2461 intel_sdvo_connector->left_property->values[0] = 0;
2462 intel_sdvo_connector->left_property->values[1] = data_value[0];
b9219c5e 2463 drm_connector_attach_property(connector,
ea5b213a
CW		 2464 intel_sdvo_connector->left_property,
2465 intel_sdvo_connector->left_margin);
2466 intel_sdvo_connector->right_property =
b9219c5e
ZY		 2467 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2468 "right_margin", 2);
ea5b213a
CW		 2469 intel_sdvo_connector->right_property->values[0] = 0;
2470 intel_sdvo_connector->right_property->values[1] = data_value[0];
b9219c5e 2471 drm_connector_attach_property(connector,
ea5b213a
CW		 2472 intel_sdvo_connector->right_property,
2473 intel_sdvo_connector->right_margin);
b9219c5e
ZY		 2474 DRM_DEBUG_KMS("h_overscan: max %d, "
2475 "default %d, current %d\n",
2476 data_value[0], data_value[1], response);
2477 }
2478 if (sdvo_data.overscan_v) {
ea5b213a 2479 intel_sdvo_write_cmd(intel_sdvo,
b9219c5e 2480 SDVO_CMD_GET_MAX_OVERSCAN_V, NULL, 0);
ea5b213a 2481 status = intel_sdvo_read_response(intel_sdvo,
b9219c5e
ZY		 2482 &data_value, 4);
2483 if (status != SDVO_CMD_STATUS_SUCCESS) {
2484 DRM_DEBUG_KMS("Incorrect SDVO max "
2485 "v_overscan\n");
2486 return;
2487 }
ea5b213a 2488 intel_sdvo_write_cmd(intel_sdvo,
b9219c5e 2489 SDVO_CMD_GET_OVERSCAN_V, NULL, 0);
ea5b213a 2490 status = intel_sdvo_read_response(intel_sdvo,
b9219c5e
ZY		 2491 &response, 2);
2492 if (status != SDVO_CMD_STATUS_SUCCESS) {
2493 DRM_DEBUG_KMS("Incorrect SDVO v_overscan\n");
2494 return;
2495 }
ea5b213a
CW		 2496 intel_sdvo_connector->max_vscan = data_value[0];
2497 intel_sdvo_connector->top_margin = data_value[0] - response;
2498 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
2499 intel_sdvo_connector->top_property =
b9219c5e
ZY		 2500 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2501 "top_margin", 2);
ea5b213a
CW		 2502 intel_sdvo_connector->top_property->values[0] = 0;
2503 intel_sdvo_connector->top_property->values[1] = data_value[0];
b9219c5e 2504 drm_connector_attach_property(connector,
ea5b213a
CW		 2505 intel_sdvo_connector->top_property,
2506 intel_sdvo_connector->top_margin);
2507 intel_sdvo_connector->bottom_property =
b9219c5e
ZY		 2508 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2509 "bottom_margin", 2);
ea5b213a
CW		 2510 intel_sdvo_connector->bottom_property->values[0] = 0;
2511 intel_sdvo_connector->bottom_property->values[1] = data_value[0];
b9219c5e 2512 drm_connector_attach_property(connector,
ea5b213a
CW		 2513 intel_sdvo_connector->bottom_property,
2514 intel_sdvo_connector->bottom_margin);
b9219c5e
ZY		 2515 DRM_DEBUG_KMS("v_overscan: max %d, "
2516 "default %d, current %d\n",
2517 data_value[0], data_value[1], response);
2518 }
2519 if (sdvo_data.position_h) {
ea5b213a 2520 intel_sdvo_write_cmd(intel_sdvo,
b9219c5e 2521 SDVO_CMD_GET_MAX_POSITION_H, NULL, 0);
ea5b213a 2522 status = intel_sdvo_read_response(intel_sdvo,
b9219c5e
ZY		 2523 &data_value, 4);
2524 if (status != SDVO_CMD_STATUS_SUCCESS) {
2525 DRM_DEBUG_KMS("Incorrect SDVO Max h_pos\n");
2526 return;
2527 }
ea5b213a 2528 intel_sdvo_write_cmd(intel_sdvo,
b9219c5e 2529 SDVO_CMD_GET_POSITION_H, NULL, 0);
ea5b213a 2530 status = intel_sdvo_read_response(intel_sdvo,
b9219c5e
ZY		 2531 &response, 2);
2532 if (status != SDVO_CMD_STATUS_SUCCESS) {
2533 DRM_DEBUG_KMS("Incorrect SDVO get h_postion\n");
2534 return;
2535 }
ea5b213a
CW		 2536 intel_sdvo_connector->max_hpos = data_value[0];
2537 intel_sdvo_connector->cur_hpos = response;
2538 intel_sdvo_connector->hpos_property =
b9219c5e
ZY		 2539 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2540 "hpos", 2);
ea5b213a
CW		 2541 intel_sdvo_connector->hpos_property->values[0] = 0;
2542 intel_sdvo_connector->hpos_property->values[1] = data_value[0];
b9219c5e 2543 drm_connector_attach_property(connector,
ea5b213a
CW		 2544 intel_sdvo_connector->hpos_property,
2545 intel_sdvo_connector->cur_hpos);
b9219c5e
ZY		 2546 DRM_DEBUG_KMS("h_position: max %d, "
2547 "default %d, current %d\n",
2548 data_value[0], data_value[1], response);
2549 }
2550 if (sdvo_data.position_v) {
ea5b213a 2551 intel_sdvo_write_cmd(intel_sdvo,
b9219c5e 2552 SDVO_CMD_GET_MAX_POSITION_V, NULL, 0);
ea5b213a 2553 status = intel_sdvo_read_response(intel_sdvo,
b9219c5e
ZY		 2554 &data_value, 4);
2555 if (status != SDVO_CMD_STATUS_SUCCESS) {
2556 DRM_DEBUG_KMS("Incorrect SDVO Max v_pos\n");
2557 return;
2558 }
ea5b213a 2559 intel_sdvo_write_cmd(intel_sdvo,
b9219c5e 2560 SDVO_CMD_GET_POSITION_V, NULL, 0);
ea5b213a 2561 status = intel_sdvo_read_response(intel_sdvo,
b9219c5e
ZY		 2562 &response, 2);
2563 if (status != SDVO_CMD_STATUS_SUCCESS) {
2564 DRM_DEBUG_KMS("Incorrect SDVO get v_postion\n");
2565 return;
2566 }
ea5b213a
CW		 2567 intel_sdvo_connector->max_vpos = data_value[0];
2568 intel_sdvo_connector->cur_vpos = response;
2569 intel_sdvo_connector->vpos_property =
b9219c5e
ZY		 2570 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2571 "vpos", 2);
ea5b213a
CW		 2572 intel_sdvo_connector->vpos_property->values[0] = 0;
2573 intel_sdvo_connector->vpos_property->values[1] = data_value[0];
b9219c5e 2574 drm_connector_attach_property(connector,
ea5b213a
CW		 2575 intel_sdvo_connector->vpos_property,
2576 intel_sdvo_connector->cur_vpos);
b9219c5e
ZY		 2577 DRM_DEBUG_KMS("v_position: max %d, "
2578 "default %d, current %d\n",
2579 data_value[0], data_value[1], response);
2580 }
b9219c5e 2581 if (sdvo_data.saturation) {
ea5b213a 2582 intel_sdvo_write_cmd(intel_sdvo,
b9219c5e 2583 SDVO_CMD_GET_MAX_SATURATION, NULL, 0);
ea5b213a 2584 status = intel_sdvo_read_response(intel_sdvo,
b9219c5e
ZY		 2585 &data_value, 4);
2586 if (status != SDVO_CMD_STATUS_SUCCESS) {
2587 DRM_DEBUG_KMS("Incorrect SDVO Max sat\n");
2588 return;
2589 }
ea5b213a 2590 intel_sdvo_write_cmd(intel_sdvo,
b9219c5e 2591 SDVO_CMD_GET_SATURATION, NULL, 0);
ea5b213a 2592 status = intel_sdvo_read_response(intel_sdvo,
b9219c5e
ZY		 2593 &response, 2);
2594 if (status != SDVO_CMD_STATUS_SUCCESS) {
2595 DRM_DEBUG_KMS("Incorrect SDVO get sat\n");
2596 return;
2597 }
ea5b213a
CW		 2598 intel_sdvo_connector->max_saturation = data_value[0];
2599 intel_sdvo_connector->cur_saturation = response;
2600 intel_sdvo_connector->saturation_property =
b9219c5e
ZY		 2601 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2602 "saturation", 2);
ea5b213a
CW		 2603 intel_sdvo_connector->saturation_property->values[0] = 0;
2604 intel_sdvo_connector->saturation_property->values[1] =
b9219c5e
ZY		 2605 data_value[0];
2606 drm_connector_attach_property(connector,
ea5b213a
CW		 2607 intel_sdvo_connector->saturation_property,
2608 intel_sdvo_connector->cur_saturation);
b9219c5e
ZY		 2609 DRM_DEBUG_KMS("saturation: max %d, "
2610 "default %d, current %d\n",
2611 data_value[0], data_value[1], response);
2612 }
2613 if (sdvo_data.contrast) {
ea5b213a 2614 intel_sdvo_write_cmd(intel_sdvo,
b9219c5e 2615 SDVO_CMD_GET_MAX_CONTRAST, NULL, 0);
ea5b213a 2616 status = intel_sdvo_read_response(intel_sdvo,
b9219c5e
ZY		 2617 &data_value, 4);
2618 if (status != SDVO_CMD_STATUS_SUCCESS) {
2619 DRM_DEBUG_KMS("Incorrect SDVO Max contrast\n");
2620 return;
2621 }
ea5b213a 2622 intel_sdvo_write_cmd(intel_sdvo,
b9219c5e 2623 SDVO_CMD_GET_CONTRAST, NULL, 0);
ea5b213a 2624 status = intel_sdvo_read_response(intel_sdvo,
b9219c5e
ZY		 2625 &response, 2);
2626 if (status != SDVO_CMD_STATUS_SUCCESS) {
2627 DRM_DEBUG_KMS("Incorrect SDVO get contrast\n");
2628 return;
2629 }
ea5b213a
CW		 2630 intel_sdvo_connector->max_contrast = data_value[0];
2631 intel_sdvo_connector->cur_contrast = response;
2632 intel_sdvo_connector->contrast_property =
b9219c5e
ZY		 2633 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2634 "contrast", 2);
ea5b213a
CW		 2635 intel_sdvo_connector->contrast_property->values[0] = 0;
2636 intel_sdvo_connector->contrast_property->values[1] = data_value[0];
b9219c5e 2637 drm_connector_attach_property(connector,
ea5b213a
CW		 2638 intel_sdvo_connector->contrast_property,
2639 intel_sdvo_connector->cur_contrast);
b9219c5e
ZY		 2640 DRM_DEBUG_KMS("contrast: max %d, "
2641 "default %d, current %d\n",
2642 data_value[0], data_value[1], response);
2643 }
2644 if (sdvo_data.hue) {
ea5b213a 2645 intel_sdvo_write_cmd(intel_sdvo,
b9219c5e 2646 SDVO_CMD_GET_MAX_HUE, NULL, 0);
ea5b213a 2647 status = intel_sdvo_read_response(intel_sdvo,
b9219c5e
ZY		 2648 &data_value, 4);
2649 if (status != SDVO_CMD_STATUS_SUCCESS) {
2650 DRM_DEBUG_KMS("Incorrect SDVO Max hue\n");
2651 return;
2652 }
ea5b213a 2653 intel_sdvo_write_cmd(intel_sdvo,
b9219c5e 2654 SDVO_CMD_GET_HUE, NULL, 0);
ea5b213a 2655 status = intel_sdvo_read_response(intel_sdvo,
b9219c5e
ZY		 2656 &response, 2);
2657 if (status != SDVO_CMD_STATUS_SUCCESS) {
2658 DRM_DEBUG_KMS("Incorrect SDVO get hue\n");
2659 return;
2660 }
ea5b213a
CW		 2661 intel_sdvo_connector->max_hue = data_value[0];
2662 intel_sdvo_connector->cur_hue = response;
2663 intel_sdvo_connector->hue_property =
b9219c5e
ZY		 2664 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2665 "hue", 2);
ea5b213a
CW		 2666 intel_sdvo_connector->hue_property->values[0] = 0;
2667 intel_sdvo_connector->hue_property->values[1] =
b9219c5e
ZY		 2668 data_value[0];
2669 drm_connector_attach_property(connector,
ea5b213a
CW		 2670 intel_sdvo_connector->hue_property,
2671 intel_sdvo_connector->cur_hue);
b9219c5e
ZY		 2672 DRM_DEBUG_KMS("hue: max %d, default %d, current %d\n",
2673 data_value[0], data_value[1], response);
2674 }
2675 }
ea5b213a 2676 if (IS_TV(intel_sdvo_connector) || IS_LVDS(intel_sdvo_connector)) {
b9219c5e 2677 if (sdvo_data.brightness) {
ea5b213a 2678 intel_sdvo_write_cmd(intel_sdvo,
b9219c5e 2679 SDVO_CMD_GET_MAX_BRIGHTNESS, NULL, 0);
ea5b213a 2680 status = intel_sdvo_read_response(intel_sdvo,
b9219c5e
ZY		 2681 &data_value, 4);
2682 if (status != SDVO_CMD_STATUS_SUCCESS) {
2683 DRM_DEBUG_KMS("Incorrect SDVO Max bright\n");
2684 return;
2685 }
ea5b213a 2686 intel_sdvo_write_cmd(intel_sdvo,
b9219c5e 2687 SDVO_CMD_GET_BRIGHTNESS, NULL, 0);
ea5b213a 2688 status = intel_sdvo_read_response(intel_sdvo,
b9219c5e
ZY		 2689 &response, 2);
2690 if (status != SDVO_CMD_STATUS_SUCCESS) {
2691 DRM_DEBUG_KMS("Incorrect SDVO get brigh\n");
2692 return;
2693 }
ea5b213a
CW		 2694 intel_sdvo_connector->max_brightness = data_value[0];
2695 intel_sdvo_connector->cur_brightness = response;
2696 intel_sdvo_connector->brightness_property =
b9219c5e
ZY		 2697 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2698 "brightness", 2);
ea5b213a
CW		 2699 intel_sdvo_connector->brightness_property->values[0] = 0;
2700 intel_sdvo_connector->brightness_property->values[1] =
b9219c5e
ZY		 2701 data_value[0];
2702 drm_connector_attach_property(connector,
ea5b213a
CW		 2703 intel_sdvo_connector->brightness_property,
2704 intel_sdvo_connector->cur_brightness);
b9219c5e
ZY		 2705 DRM_DEBUG_KMS("brightness: max %d, "
2706 "default %d, current %d\n",
2707 data_value[0], data_value[1], response);
2708 }
2709 }
2710 return;
2711}
2712
c751ce4f 2713bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg)
79e53945 2714{
b01f2c3a 2715 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 2716 struct intel_encoder *intel_encoder;
ea5b213a 2717 struct intel_sdvo *intel_sdvo;
79e53945
JB		 2718 u8 ch[0x40];
2719 int i;
461ed3ca 2720 u32 i2c_reg, ddc_reg, analog_ddc_reg;
79e53945 2721
ea5b213a
CW		 2722 intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
2723 if (!intel_sdvo)
7d57382e 2724 return false;
79e53945 2725
ea5b213a 2726 intel_sdvo->sdvo_reg = sdvo_reg;
308cd3a2 2727
ea5b213a 2728 intel_encoder = &intel_sdvo->base;
21d40d37 2729 intel_encoder->type = INTEL_OUTPUT_SDVO;
79e53945 2730
461ed3ca
ZY		 2731 if (HAS_PCH_SPLIT(dev)) {
2732 i2c_reg = PCH_GPIOE;
2733 ddc_reg = PCH_GPIOE;
2734 analog_ddc_reg = PCH_GPIOA;
2735 } else {
2736 i2c_reg = GPIOE;
2737 ddc_reg = GPIOE;
2738 analog_ddc_reg = GPIOA;
2739 }
2740
79e53945 2741 /* setup the DDC bus. */
461ed3ca
ZY		 2742 if (IS_SDVOB(sdvo_reg))
2743 intel_encoder->i2c_bus = intel_i2c_create(dev, i2c_reg, "SDVOCTRL_E for SDVOB");
308cd3a2 2744 else
461ed3ca 2745 intel_encoder->i2c_bus = intel_i2c_create(dev, i2c_reg, "SDVOCTRL_E for SDVOC");
308cd3a2 2746
21d40d37 2747 if (!intel_encoder->i2c_bus)
ad5b2a6d 2748 goto err_inteloutput;
79e53945 2749
ea5b213a 2750 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, sdvo_reg);
79e53945 2751
308cd3a2 2752 /* Save the bit-banging i2c functionality for use by the DDC wrapper */
21d40d37 2753 intel_sdvo_i2c_bit_algo.functionality = intel_encoder->i2c_bus->algo->functionality;
79e53945 2754
79e53945
JB		 2755 /* Read the regs to test if we can talk to the device */
2756 for (i = 0; i < 0x40; i++) {
ea5b213a 2757 if (!intel_sdvo_read_byte(intel_sdvo, i, &ch[i])) {
8a4c47f3 2758 DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n",
461ed3ca 2759 IS_SDVOB(sdvo_reg) ? 'B' : 'C');
79e53945
JB		 2760 goto err_i2c;
2761 }
2762 }
2763
619ac3b7 2764 /* setup the DDC bus. */
461ed3ca
ZY		 2765 if (IS_SDVOB(sdvo_reg)) {
2766 intel_encoder->ddc_bus = intel_i2c_create(dev, ddc_reg, "SDVOB DDC BUS");
ea5b213a 2767 intel_sdvo->analog_ddc_bus = intel_i2c_create(dev, analog_ddc_reg,
57cdaf90 2768 "SDVOB/VGA DDC BUS");
b01f2c3a 2769 dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS;
57cdaf90 2770 } else {
461ed3ca 2771 intel_encoder->ddc_bus = intel_i2c_create(dev, ddc_reg, "SDVOC DDC BUS");
ea5b213a 2772 intel_sdvo->analog_ddc_bus = intel_i2c_create(dev, analog_ddc_reg,
57cdaf90 2773 "SDVOC/VGA DDC BUS");
b01f2c3a 2774 dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS;
57cdaf90 2775 }
619ac3b7 2776
21d40d37 2777 if (intel_encoder->ddc_bus == NULL)
619ac3b7
ML		 2778 goto err_i2c;
2779
308cd3a2 2780 /* Wrap with our custom algo which switches to DDC mode */
21d40d37 2781 intel_encoder->ddc_bus->algo = &intel_sdvo_i2c_bit_algo;
619ac3b7 2782
14571b4c
ZW		 2783 /* encoder type will be decided later */
2784 drm_encoder_init(dev, &intel_encoder->enc, &intel_sdvo_enc_funcs, 0);
2785 drm_encoder_helper_add(&intel_encoder->enc, &intel_sdvo_helper_funcs);
2786
af901ca1 2787 /* In default case sdvo lvds is false */
ea5b213a 2788 intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps);
79e53945 2789
ea5b213a
CW		 2790 if (intel_sdvo_output_setup(intel_sdvo,
2791 intel_sdvo->caps.output_flags) != true) {
51c8b407 2792 DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n",
461ed3ca 2793 IS_SDVOB(sdvo_reg) ? 'B' : 'C');
79e53945
JB		 2794 goto err_i2c;
2795 }
2796
ea5b213a 2797 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
e2f0ba97 2798
79e53945 2799 /* Set the input timing to the screen. Assume always input 0. */
ea5b213a 2800 intel_sdvo_set_target_input(intel_sdvo, true, false);
79e53945 2801
ea5b213a
CW		 2802 intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
2803 &intel_sdvo->pixel_clock_min,
2804 &intel_sdvo->pixel_clock_max);
79e53945
JB		 2805
2806
8a4c47f3 2807 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
342dc382 2808 "clock range %dMHz - %dMHz, "
2809 "input 1: %c, input 2: %c, "
2810 "output 1: %c, output 2: %c\n",
ea5b213a
CW		 2811 SDVO_NAME(intel_sdvo),
2812 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
2813 intel_sdvo->caps.device_rev_id,
2814 intel_sdvo->pixel_clock_min / 1000,
2815 intel_sdvo->pixel_clock_max / 1000,
2816 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2817 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
342dc382 2818 /* check currently supported outputs */
ea5b213a 2819 intel_sdvo->caps.output_flags &
79e53945 2820 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
ea5b213a 2821 intel_sdvo->caps.output_flags &
79e53945
JB		 2822 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
2823
7d57382e 2824 return true;
79e53945
JB		 2825
2826err_i2c:
ea5b213a
CW		 2827 if (intel_sdvo->analog_ddc_bus != NULL)
2828 intel_i2c_destroy(intel_sdvo->analog_ddc_bus);
21d40d37
EA		 2829 if (intel_encoder->ddc_bus != NULL)
2830 intel_i2c_destroy(intel_encoder->ddc_bus);
2831 if (intel_encoder->i2c_bus != NULL)
2832 intel_i2c_destroy(intel_encoder->i2c_bus);
ad5b2a6d 2833err_inteloutput:
ea5b213a 2834 kfree(intel_sdvo);
79e53945 2835
7d57382e 2836 return false;
79e53945 2837}
Ubuntu Disco kernel mirror for Proxmox VE and PMG