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drm/i915/sdvo: Add missing TV filters
[mirror_ubuntu-disco-kernel.git] / drivers / gpu / drm / i915 / intel_sdvo.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
79e53945
JB		 30#include <linux/delay.h>
31#include "drmP.h"
32#include "drm.h"
33#include "drm_crtc.h"
2b8d33f7 34#include "drm_edid.h"
ea5b213a 35#include "intel_drv.h"
79e53945
JB		 36#include "i915_drm.h"
37#include "i915_drv.h"
38#include "intel_sdvo_regs.h"
39
14571b4c
ZW		 40#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
41#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
42#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
43#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0)
44
45#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
46 SDVO_TV_MASK)
47
48#define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
49#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
32aad86f 50#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
14571b4c 51
79e53945 52
ce6feabd
ZY		 53static char *tv_format_names[] = {
54 "NTSC_M" , "NTSC_J" , "NTSC_443",
55 "PAL_B" , "PAL_D" , "PAL_G" ,
56 "PAL_H" , "PAL_I" , "PAL_M" ,
57 "PAL_N" , "PAL_NC" , "PAL_60" ,
58 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
59 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
60 "SECAM_60"
61};
62
63#define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
64
ea5b213a
CW		 65struct intel_sdvo {
66 struct intel_encoder base;
67
f9c10a9b 68 u8 slave_addr;
e2f0ba97
JB		 69
70 /* Register for the SDVO device: SDVOB or SDVOC */
c751ce4f 71 int sdvo_reg;
79e53945 72
e2f0ba97
JB		 73 /* Active outputs controlled by this SDVO output */
74 uint16_t controlled_output;
79e53945 75
e2f0ba97
JB		 76 /*
77 * Capabilities of the SDVO device returned by
78 * i830_sdvo_get_capabilities()
79 */
79e53945 80 struct intel_sdvo_caps caps;
e2f0ba97
JB		 81
82 /* Pixel clock limitations reported by the SDVO device, in kHz */
79e53945
JB		 83 int pixel_clock_min, pixel_clock_max;
84
fb7a46f3 85 /*
86 * For multiple function SDVO device,
87 * this is for current attached outputs.
88 */
89 uint16_t attached_output;
90
e2f0ba97
JB		 91 /**
92 * This is set if we're going to treat the device as TV-out.
93 *
94 * While we have these nice friendly flags for output types that ought
95 * to decide this for us, the S-Video output on our HDMI+S-Video card
96 * shows up as RGB1 (VGA).
97 */
98 bool is_tv;
99
ce6feabd 100 /* This is for current tv format name */
40039750 101 int tv_format_index;
ce6feabd 102
e2f0ba97
JB		 103 /**
104 * This is set if we treat the device as HDMI, instead of DVI.
105 */
106 bool is_hdmi;
12682a97 107
7086c87f
ML		 108 /**
109 * This is set if we detect output of sdvo device as LVDS.
110 */
111 bool is_lvds;
e2f0ba97 112
12682a97 113 /**
114 * This is sdvo flags for input timing.
115 */
116 uint8_t sdvo_flags;
117
118 /**
119 * This is sdvo fixed pannel mode pointer
120 */
121 struct drm_display_mode *sdvo_lvds_fixed_mode;
122
e2f0ba97
JB		 123 /*
124 * supported encoding mode, used to determine whether HDMI is
125 * supported
126 */
127 struct intel_sdvo_encode encode;
128
c751ce4f 129 /* DDC bus used by this SDVO encoder */
e2f0ba97
JB		 130 uint8_t ddc_bus;
131
57cdaf90
KP		 132 /* Mac mini hack -- use the same DDC as the analog connector */
133 struct i2c_adapter *analog_ddc_bus;
134
14571b4c
ZW		 135};
136
137struct intel_sdvo_connector {
615fb93f
CW		 138 struct intel_connector base;
139
14571b4c
ZW		 140 /* Mark the type of connector */
141 uint16_t output_flag;
142
143 /* This contains all current supported TV format */
40039750 144 u8 tv_format_supported[TV_FORMAT_NUM];
14571b4c 145 int format_supported_num;
c5521706 146 struct drm_property *tv_format;
14571b4c 147
b9219c5e 148 /* add the property for the SDVO-TV */
c5521706
CW		 149 struct drm_property *left;
150 struct drm_property *right;
151 struct drm_property *top;
152 struct drm_property *bottom;
153 struct drm_property *hpos;
154 struct drm_property *vpos;
155 struct drm_property *contrast;
156 struct drm_property *saturation;
157 struct drm_property *hue;
158 struct drm_property *sharpness;
159 struct drm_property *flicker_filter;
160 struct drm_property *flicker_filter_adaptive;
161 struct drm_property *flicker_filter_2d;
162 struct drm_property *tv_chroma_filter;
163 struct drm_property *tv_luma_filter;
b9219c5e
ZY		 164
165 /* add the property for the SDVO-TV/LVDS */
c5521706 166 struct drm_property *brightness;
b9219c5e
ZY		 167
168 /* Add variable to record current setting for the above property */
169 u32 left_margin, right_margin, top_margin, bottom_margin;
c5521706 170
b9219c5e
ZY		 171 /* this is to get the range of margin.*/
172 u32 max_hscan, max_vscan;
173 u32 max_hpos, cur_hpos;
174 u32 max_vpos, cur_vpos;
175 u32 cur_brightness, max_brightness;
176 u32 cur_contrast, max_contrast;
177 u32 cur_saturation, max_saturation;
178 u32 cur_hue, max_hue;
c5521706
CW		 179 u32 cur_sharpness, max_sharpness;
180 u32 cur_flicker_filter, max_flicker_filter;
181 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
182 u32 cur_flicker_filter_2d, max_flicker_filter_2d;
183 u32 cur_tv_chroma_filter, max_tv_chroma_filter;
184 u32 cur_tv_luma_filter, max_tv_luma_filter;
79e53945
JB		 185};
186
ea5b213a
CW		 187static struct intel_sdvo *enc_to_intel_sdvo(struct drm_encoder *encoder)
188{
189 return container_of(enc_to_intel_encoder(encoder), struct intel_sdvo, base);
190}
191
615fb93f
CW		 192static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
193{
194 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
195}
196
fb7a46f3 197static bool
ea5b213a 198intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
32aad86f
CW		 199static bool
200intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
201 struct intel_sdvo_connector *intel_sdvo_connector,
202 int type);
203static bool
204intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
205 struct intel_sdvo_connector *intel_sdvo_connector);
fb7a46f3 206
79e53945
JB		 207/**
208 * Writes the SDVOB or SDVOC with the given value, but always writes both
209 * SDVOB and SDVOC to work around apparent hardware issues (according to
210 * comments in the BIOS).
211 */
ea5b213a 212static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
79e53945 213{
ea5b213a 214 struct drm_device *dev = intel_sdvo->base.enc.dev;
79e53945 215 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 216 u32 bval = val, cval = val;
217 int i;
218
ea5b213a
CW		 219 if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
220 I915_WRITE(intel_sdvo->sdvo_reg, val);
221 I915_READ(intel_sdvo->sdvo_reg);
461ed3ca
ZY		 222 return;
223 }
224
ea5b213a 225 if (intel_sdvo->sdvo_reg == SDVOB) {
79e53945
JB		 226 cval = I915_READ(SDVOC);
227 } else {
228 bval = I915_READ(SDVOB);
229 }
230 /*
231 * Write the registers twice for luck. Sometimes,
232 * writing them only once doesn't appear to 'stick'.
233 * The BIOS does this too. Yay, magic
234 */
235 for (i = 0; i < 2; i++)
236 {
237 I915_WRITE(SDVOB, bval);
238 I915_READ(SDVOB);
239 I915_WRITE(SDVOC, cval);
240 I915_READ(SDVOC);
241 }
242}
243
32aad86f 244static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
79e53945 245{
32aad86f 246 u8 out_buf[2] = { addr, 0 };
79e53945 247 u8 buf[2];
79e53945
JB		 248 struct i2c_msg msgs[] = {
249 {
ea5b213a 250 .addr = intel_sdvo->slave_addr >> 1,
79e53945
JB		 251 .flags = 0,
252 .len = 1,
253 .buf = out_buf,
254 },
255 {
ea5b213a 256 .addr = intel_sdvo->slave_addr >> 1,
79e53945
JB		 257 .flags = I2C_M_RD,
258 .len = 1,
259 .buf = buf,
260 }
261 };
32aad86f 262 int ret;
79e53945 263
ea5b213a 264 if ((ret = i2c_transfer(intel_sdvo->base.i2c_bus, msgs, 2)) == 2)
79e53945
JB		 265 {
266 *ch = buf[0];
267 return true;
268 }
269
8a4c47f3 270 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
79e53945
JB		 271 return false;
272}
273
32aad86f 274static bool intel_sdvo_write_byte(struct intel_sdvo *intel_sdvo, int addr, u8 ch)
79e53945 275{
32aad86f 276 u8 out_buf[2] = { addr, ch };
79e53945
JB		 277 struct i2c_msg msgs[] = {
278 {
ea5b213a 279 .addr = intel_sdvo->slave_addr >> 1,
79e53945
JB		 280 .flags = 0,
281 .len = 2,
282 .buf = out_buf,
283 }
284 };
285
32aad86f 286 return i2c_transfer(intel_sdvo->base.i2c_bus, msgs, 1) == 1;
79e53945
JB		 287}
288
289#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
290/** Mapping of command numbers to names, for debug output */
005568be 291static const struct _sdvo_cmd_name {
e2f0ba97
JB		 292 u8 cmd;
293 char *name;
79e53945
JB		 294} sdvo_cmd_names[] = {
295 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
296 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
297 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
e2f0ba97
JB		 330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
79e53945 334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
e2f0ba97
JB		 335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
c5521706 338
b9219c5e 339 /* Add the op code for SDVO enhancements */
c5521706
CW		 340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
b9219c5e
ZY		 346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
c5521706
CW		 364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
384
e2f0ba97
JB		 385 /* HDMI op code */
386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
388 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
400 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
404 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
405 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
79e53945
JB		 406};
407
461ed3ca 408#define IS_SDVOB(reg) (reg == SDVOB || reg == PCH_SDVOB)
ea5b213a 409#define SDVO_NAME(svdo) (IS_SDVOB((svdo)->sdvo_reg) ? "SDVOB" : "SDVOC")
79e53945 410
ea5b213a 411static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
32aad86f 412 const void *args, int args_len)
79e53945 413{
79e53945
JB		 414 int i;
415
8a4c47f3 416 DRM_DEBUG_KMS("%s: W: %02X ",
ea5b213a 417 SDVO_NAME(intel_sdvo), cmd);
79e53945 418 for (i = 0; i < args_len; i++)
342dc382 419 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
79e53945 420 for (; i < 8; i++)
342dc382 421 DRM_LOG_KMS(" ");
04ad327f 422 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
79e53945 423 if (cmd == sdvo_cmd_names[i].cmd) {
342dc382 424 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
79e53945
JB		 425 break;
426 }
427 }
04ad327f 428 if (i == ARRAY_SIZE(sdvo_cmd_names))
342dc382 429 DRM_LOG_KMS("(%02X)", cmd);
430 DRM_LOG_KMS("\n");
79e53945 431}
79e53945 432
32aad86f
CW		 433static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
434 const void *args, int args_len)
79e53945
JB		 435{
436 int i;
437
ea5b213a 438 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
79e53945
JB		 439
440 for (i = 0; i < args_len; i++) {
32aad86f
CW		 441 if (!intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_ARG_0 - i,
442 ((u8*)args)[i]))
443 return false;
79e53945
JB		 444 }
445
32aad86f 446 return intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_OPCODE, cmd);
79e53945
JB		 447}
448
79e53945
JB		 449static const char *cmd_status_names[] = {
450 "Power on",
451 "Success",
452 "Not supported",
453 "Invalid arg",
454 "Pending",
455 "Target not specified",
456 "Scaling not supported"
457};
458
ea5b213a 459static void intel_sdvo_debug_response(struct intel_sdvo *intel_sdvo,
79e53945
JB		 460 void *response, int response_len,
461 u8 status)
462{
33b52961 463 int i;
79e53945 464
ea5b213a 465 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
79e53945 466 for (i = 0; i < response_len; i++)
342dc382 467 DRM_LOG_KMS("%02X ", ((u8 *)response)[i]);
79e53945 468 for (; i < 8; i++)
342dc382 469 DRM_LOG_KMS(" ");
79e53945 470 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
342dc382 471 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
79e53945 472 else
342dc382 473 DRM_LOG_KMS("(??? %d)", status);
474 DRM_LOG_KMS("\n");
79e53945 475}
79e53945 476
32aad86f
CW		 477static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
478 void *response, int response_len)
79e53945
JB		 479{
480 int i;
481 u8 status;
482 u8 retry = 50;
483
484 while (retry--) {
485 /* Read the command response */
486 for (i = 0; i < response_len; i++) {
32aad86f
CW		 487 if (!intel_sdvo_read_byte(intel_sdvo,
488 SDVO_I2C_RETURN_0 + i,
489 &((u8 *)response)[i]))
490 return false;
79e53945
JB		 491 }
492
493 /* read the return status */
32aad86f
CW		 494 if (!intel_sdvo_read_byte(intel_sdvo, SDVO_I2C_CMD_STATUS,
495 &status))
496 return false;
79e53945 497
ea5b213a 498 intel_sdvo_debug_response(intel_sdvo, response, response_len,
79e53945
JB		 499 status);
500 if (status != SDVO_CMD_STATUS_PENDING)
32aad86f 501 break;
79e53945
JB		 502
503 mdelay(50);
504 }
505
32aad86f 506 return status == SDVO_CMD_STATUS_SUCCESS;
79e53945
JB		 507}
508
b358d0a6 509static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
79e53945
JB		 510{
511 if (mode->clock >= 100000)
512 return 1;
513 else if (mode->clock >= 50000)
514 return 2;
515 else
516 return 4;
517}
518
519/**
6a304caf
ZY		 520 * Try to read the response after issuie the DDC switch command. But it
521 * is noted that we must do the action of reading response and issuing DDC
522 * switch command in one I2C transaction. Otherwise when we try to start
523 * another I2C transaction after issuing the DDC bus switch, it will be
524 * switched to the internal SDVO register.
79e53945 525 */
ea5b213a 526static void intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
b358d0a6 527 u8 target)
79e53945 528{
6a304caf
ZY		 529 u8 out_buf[2], cmd_buf[2], ret_value[2], ret;
530 struct i2c_msg msgs[] = {
531 {
ea5b213a 532 .addr = intel_sdvo->slave_addr >> 1,
6a304caf
ZY		 533 .flags = 0,
534 .len = 2,
535 .buf = out_buf,
536 },
537 /* the following two are to read the response */
538 {
ea5b213a 539 .addr = intel_sdvo->slave_addr >> 1,
6a304caf
ZY		 540 .flags = 0,
541 .len = 1,
542 .buf = cmd_buf,
543 },
544 {
ea5b213a 545 .addr = intel_sdvo->slave_addr >> 1,
6a304caf
ZY		 546 .flags = I2C_M_RD,
547 .len = 1,
548 .buf = ret_value,
549 },
550 };
551
ea5b213a 552 intel_sdvo_debug_write(intel_sdvo, SDVO_CMD_SET_CONTROL_BUS_SWITCH,
6a304caf
ZY		 553 &target, 1);
554 /* write the DDC switch command argument */
ea5b213a 555 intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_ARG_0, target);
6a304caf
ZY		 556
557 out_buf[0] = SDVO_I2C_OPCODE;
558 out_buf[1] = SDVO_CMD_SET_CONTROL_BUS_SWITCH;
559 cmd_buf[0] = SDVO_I2C_CMD_STATUS;
560 cmd_buf[1] = 0;
561 ret_value[0] = 0;
562 ret_value[1] = 0;
563
ea5b213a 564 ret = i2c_transfer(intel_sdvo->base.i2c_bus, msgs, 3);
6a304caf
ZY		 565 if (ret != 3) {
566 /* failure in I2C transfer */
567 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
568 return;
569 }
570 if (ret_value[0] != SDVO_CMD_STATUS_SUCCESS) {
571 DRM_DEBUG_KMS("DDC switch command returns response %d\n",
572 ret_value[0]);
573 return;
574 }
575 return;
79e53945
JB		 576}
577
32aad86f 578static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
79e53945 579{
32aad86f
CW		 580 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
581 return false;
79e53945 582
32aad86f
CW		 583 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
584}
79e53945 585
32aad86f
CW		 586static bool
587intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
588{
589 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
590 return false;
79e53945 591
32aad86f
CW		 592 return intel_sdvo_read_response(intel_sdvo, value, len);
593}
79e53945 594
32aad86f
CW		 595static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
596{
597 struct intel_sdvo_set_target_input_args targets = {0};
598 return intel_sdvo_set_value(intel_sdvo,
599 SDVO_CMD_SET_TARGET_INPUT,
600 &targets, sizeof(targets));
79e53945
JB		 601}
602
603/**
604 * Return whether each input is trained.
605 *
606 * This function is making an assumption about the layout of the response,
607 * which should be checked against the docs.
608 */
ea5b213a 609static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
79e53945
JB		 610{
611 struct intel_sdvo_get_trained_inputs_response response;
79e53945 612
32aad86f
CW		 613 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
614 &response, sizeof(response)))
79e53945
JB		 615 return false;
616
617 *input_1 = response.input0_trained;
618 *input_2 = response.input1_trained;
619 return true;
620}
621
ea5b213a 622static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
79e53945
JB		 623 u16 outputs)
624{
32aad86f
CW		 625 return intel_sdvo_set_value(intel_sdvo,
626 SDVO_CMD_SET_ACTIVE_OUTPUTS,
627 &outputs, sizeof(outputs));
79e53945
JB		 628}
629
ea5b213a 630static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
79e53945
JB		 631 int mode)
632{
32aad86f 633 u8 state = SDVO_ENCODER_STATE_ON;
79e53945
JB		 634
635 switch (mode) {
636 case DRM_MODE_DPMS_ON:
637 state = SDVO_ENCODER_STATE_ON;
638 break;
639 case DRM_MODE_DPMS_STANDBY:
640 state = SDVO_ENCODER_STATE_STANDBY;
641 break;
642 case DRM_MODE_DPMS_SUSPEND:
643 state = SDVO_ENCODER_STATE_SUSPEND;
644 break;
645 case DRM_MODE_DPMS_OFF:
646 state = SDVO_ENCODER_STATE_OFF;
647 break;
648 }
649
32aad86f
CW		 650 return intel_sdvo_set_value(intel_sdvo,
651 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
79e53945
JB		 652}
653
ea5b213a 654static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
79e53945
JB		 655 int *clock_min,
656 int *clock_max)
657{
658 struct intel_sdvo_pixel_clock_range clocks;
79e53945 659
32aad86f
CW		 660 if (!intel_sdvo_get_value(intel_sdvo,
661 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
662 &clocks, sizeof(clocks)))
79e53945
JB		 663 return false;
664
665 /* Convert the values from units of 10 kHz to kHz. */
666 *clock_min = clocks.min * 10;
667 *clock_max = clocks.max * 10;
79e53945
JB		 668 return true;
669}
670
ea5b213a 671static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
79e53945
JB		 672 u16 outputs)
673{
32aad86f
CW		 674 return intel_sdvo_set_value(intel_sdvo,
675 SDVO_CMD_SET_TARGET_OUTPUT,
676 &outputs, sizeof(outputs));
79e53945
JB		 677}
678
ea5b213a 679static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
79e53945
JB		 680 struct intel_sdvo_dtd *dtd)
681{
32aad86f
CW		 682 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
683 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
79e53945
JB		 684}
685
ea5b213a 686static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 687 struct intel_sdvo_dtd *dtd)
688{
ea5b213a 689 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 690 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
691}
692
ea5b213a 693static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 694 struct intel_sdvo_dtd *dtd)
695{
ea5b213a 696 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 697 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
698}
699
e2f0ba97 700static bool
ea5b213a 701intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 702 uint16_t clock,
703 uint16_t width,
704 uint16_t height)
705{
706 struct intel_sdvo_preferred_input_timing_args args;
e2f0ba97 707
e642c6f1 708 memset(&args, 0, sizeof(args));
e2f0ba97
JB		 709 args.clock = clock;
710 args.width = width;
711 args.height = height;
e642c6f1 712 args.interlace = 0;
12682a97 713
ea5b213a
CW		 714 if (intel_sdvo->is_lvds &&
715 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
716 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
12682a97 717 args.scaled = 1;
718
32aad86f
CW		 719 return intel_sdvo_set_value(intel_sdvo,
720 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
721 &args, sizeof(args));
e2f0ba97
JB		 722}
723
ea5b213a 724static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 725 struct intel_sdvo_dtd *dtd)
726{
32aad86f
CW		 727 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
728 &dtd->part1, sizeof(dtd->part1)) &&
729 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
730 &dtd->part2, sizeof(dtd->part2));
e2f0ba97 731}
79e53945 732
ea5b213a 733static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
79e53945 734{
32aad86f 735 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
79e53945
JB		 736}
737
e2f0ba97 738static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
32aad86f 739 const struct drm_display_mode *mode)
79e53945 740{
e2f0ba97
JB		 741 uint16_t width, height;
742 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
743 uint16_t h_sync_offset, v_sync_offset;
79e53945
JB		 744
745 width = mode->crtc_hdisplay;
746 height = mode->crtc_vdisplay;
747
748 /* do some mode translations */
749 h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
750 h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
751
752 v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
753 v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
754
755 h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
756 v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
757
e2f0ba97
JB		 758 dtd->part1.clock = mode->clock / 10;
759 dtd->part1.h_active = width & 0xff;
760 dtd->part1.h_blank = h_blank_len & 0xff;
761 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
79e53945 762 ((h_blank_len >> 8) & 0xf);
e2f0ba97
JB		 763 dtd->part1.v_active = height & 0xff;
764 dtd->part1.v_blank = v_blank_len & 0xff;
765 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
79e53945
JB		 766 ((v_blank_len >> 8) & 0xf);
767
171a9e96 768 dtd->part2.h_sync_off = h_sync_offset & 0xff;
e2f0ba97
JB		 769 dtd->part2.h_sync_width = h_sync_len & 0xff;
770 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
79e53945 771 (v_sync_len & 0xf);
e2f0ba97 772 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
79e53945
JB		 773 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
774 ((v_sync_len & 0x30) >> 4);
775
e2f0ba97 776 dtd->part2.dtd_flags = 0x18;
79e53945 777 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
e2f0ba97 778 dtd->part2.dtd_flags |= 0x2;
79e53945 779 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
e2f0ba97
JB		 780 dtd->part2.dtd_flags |= 0x4;
781
782 dtd->part2.sdvo_flags = 0;
783 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
784 dtd->part2.reserved = 0;
785}
786
787static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
32aad86f 788 const struct intel_sdvo_dtd *dtd)
e2f0ba97 789{
e2f0ba97
JB		 790 mode->hdisplay = dtd->part1.h_active;
791 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
792 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
171a9e96 793 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
e2f0ba97
JB		 794 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
795 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
796 mode->htotal = mode->hdisplay + dtd->part1.h_blank;
797 mode->htotal += (dtd->part1.h_high & 0xf) << 8;
798
799 mode->vdisplay = dtd->part1.v_active;
800 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
801 mode->vsync_start = mode->vdisplay;
802 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
171a9e96 803 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
e2f0ba97
JB		 804 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
805 mode->vsync_end = mode->vsync_start +
806 (dtd->part2.v_sync_off_width & 0xf);
807 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
808 mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
809 mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
810
811 mode->clock = dtd->part1.clock * 10;
812
171a9e96 813 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
e2f0ba97
JB		 814 if (dtd->part2.dtd_flags & 0x2)
815 mode->flags |= DRM_MODE_FLAG_PHSYNC;
816 if (dtd->part2.dtd_flags & 0x4)
817 mode->flags |= DRM_MODE_FLAG_PVSYNC;
818}
819
ea5b213a 820static bool intel_sdvo_get_supp_encode(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 821 struct intel_sdvo_encode *encode)
822{
32aad86f
CW		 823 if (intel_sdvo_get_value(intel_sdvo,
824 SDVO_CMD_GET_SUPP_ENCODE,
825 encode, sizeof(*encode)))
826 return true;
e2f0ba97 827
32aad86f
CW		 828 /* non-support means DVI */
829 memset(encode, 0, sizeof(*encode));
830 return false;
e2f0ba97
JB		 831}
832
ea5b213a 833static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
c751ce4f 834 uint8_t mode)
e2f0ba97 835{
32aad86f 836 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
e2f0ba97
JB		 837}
838
ea5b213a 839static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 840 uint8_t mode)
841{
32aad86f 842 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
e2f0ba97
JB		 843}
844
845#if 0
ea5b213a 846static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 847{
848 int i, j;
849 uint8_t set_buf_index[2];
850 uint8_t av_split;
851 uint8_t buf_size;
852 uint8_t buf[48];
853 uint8_t *pos;
854
32aad86f 855 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
e2f0ba97
JB		 856
857 for (i = 0; i <= av_split; i++) {
858 set_buf_index[0] = i; set_buf_index[1] = 0;
c751ce4f 859 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
e2f0ba97 860 set_buf_index, 2);
c751ce4f
EA		 861 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
862 intel_sdvo_read_response(encoder, &buf_size, 1);
e2f0ba97
JB		 863
864 pos = buf;
865 for (j = 0; j <= buf_size; j += 8) {
c751ce4f 866 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
e2f0ba97 867 NULL, 0);
c751ce4f 868 intel_sdvo_read_response(encoder, pos, 8);
e2f0ba97
JB		 869 pos += 8;
870 }
871 }
872}
873#endif
874
32aad86f 875static bool intel_sdvo_set_hdmi_buf(struct intel_sdvo *intel_sdvo,
c751ce4f
EA		 876 int index,
877 uint8_t *data, int8_t size, uint8_t tx_rate)
e2f0ba97
JB		 878{
879 uint8_t set_buf_index[2];
880
881 set_buf_index[0] = index;
882 set_buf_index[1] = 0;
883
32aad86f
CW		 884 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_INDEX,
885 set_buf_index, 2))
886 return false;
e2f0ba97
JB		 887
888 for (; size > 0; size -= 8) {
32aad86f
CW		 889 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_DATA, data, 8))
890 return false;
891
e2f0ba97
JB		 892 data += 8;
893 }
894
32aad86f 895 return intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1);
e2f0ba97
JB		 896}
897
898static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data, uint8_t size)
899{
900 uint8_t csum = 0;
901 int i;
902
903 for (i = 0; i < size; i++)
904 csum += data[i];
905
906 return 0x100 - csum;
907}
908
909#define DIP_TYPE_AVI 0x82
910#define DIP_VERSION_AVI 0x2
911#define DIP_LEN_AVI 13
912
913struct dip_infoframe {
914 uint8_t type;
915 uint8_t version;
916 uint8_t len;
917 uint8_t checksum;
918 union {
919 struct {
920 /* Packet Byte #1 */
921 uint8_t S:2;
922 uint8_t B:2;
923 uint8_t A:1;
924 uint8_t Y:2;
925 uint8_t rsvd1:1;
926 /* Packet Byte #2 */
927 uint8_t R:4;
928 uint8_t M:2;
929 uint8_t C:2;
930 /* Packet Byte #3 */
931 uint8_t SC:2;
932 uint8_t Q:2;
933 uint8_t EC:3;
934 uint8_t ITC:1;
935 /* Packet Byte #4 */
936 uint8_t VIC:7;
937 uint8_t rsvd2:1;
938 /* Packet Byte #5 */
939 uint8_t PR:4;
940 uint8_t rsvd3:4;
941 /* Packet Byte #6~13 */
942 uint16_t top_bar_end;
943 uint16_t bottom_bar_start;
944 uint16_t left_bar_end;
945 uint16_t right_bar_start;
946 } avi;
947 struct {
948 /* Packet Byte #1 */
949 uint8_t channel_count:3;
950 uint8_t rsvd1:1;
951 uint8_t coding_type:4;
952 /* Packet Byte #2 */
953 uint8_t sample_size:2; /* SS0, SS1 */
954 uint8_t sample_frequency:3;
955 uint8_t rsvd2:3;
956 /* Packet Byte #3 */
957 uint8_t coding_type_private:5;
958 uint8_t rsvd3:3;
959 /* Packet Byte #4 */
960 uint8_t channel_allocation;
961 /* Packet Byte #5 */
962 uint8_t rsvd4:3;
963 uint8_t level_shift:4;
964 uint8_t downmix_inhibit:1;
965 } audio;
966 uint8_t payload[28];
967 } __attribute__ ((packed)) u;
968} __attribute__((packed));
969
32aad86f 970static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 971 struct drm_display_mode * mode)
972{
973 struct dip_infoframe avi_if = {
974 .type = DIP_TYPE_AVI,
975 .version = DIP_VERSION_AVI,
976 .len = DIP_LEN_AVI,
977 };
978
979 avi_if.checksum = intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if,
980 4 + avi_if.len);
32aad86f
CW		 981 return intel_sdvo_set_hdmi_buf(intel_sdvo, 1, (uint8_t *)&avi_if,
982 4 + avi_if.len,
983 SDVO_HBUF_TX_VSYNC);
e2f0ba97
JB		 984}
985
32aad86f 986static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
7026d4ac 987{
ce6feabd 988 struct intel_sdvo_tv_format format;
40039750 989 uint32_t format_map;
ce6feabd 990
40039750 991 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 992 memset(&format, 0, sizeof(format));
32aad86f 993 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
ce6feabd 994
32aad86f
CW		 995 BUILD_BUG_ON(sizeof(format) != 6);
996 return intel_sdvo_set_value(intel_sdvo,
997 SDVO_CMD_SET_TV_FORMAT,
998 &format, sizeof(format));
7026d4ac
ZW		 999}
1000
32aad86f
CW		 1001static bool
1002intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
1003 struct drm_display_mode *mode)
e2f0ba97 1004{
32aad86f 1005 struct intel_sdvo_dtd output_dtd;
79e53945 1006
32aad86f
CW		 1007 if (!intel_sdvo_set_target_output(intel_sdvo,
1008 intel_sdvo->attached_output))
1009 return false;
e2f0ba97 1010
32aad86f
CW		 1011 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1012 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1013 return false;
e2f0ba97 1014
32aad86f
CW		 1015 return true;
1016}
1017
1018static bool
1019intel_sdvo_set_input_timings_for_mode(struct intel_sdvo *intel_sdvo,
1020 struct drm_display_mode *mode,
1021 struct drm_display_mode *adjusted_mode)
1022{
1023 struct intel_sdvo_dtd input_dtd;
e2f0ba97 1024
32aad86f
CW		 1025 /* Reset the input timing to the screen. Assume always input 0. */
1026 if (!intel_sdvo_set_target_input(intel_sdvo))
1027 return false;
e2f0ba97 1028
32aad86f
CW		 1029 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
1030 mode->clock / 10,
1031 mode->hdisplay,
1032 mode->vdisplay))
1033 return false;
e2f0ba97 1034
32aad86f
CW		 1035 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
1036 &input_dtd))
1037 return false;
e2f0ba97 1038
32aad86f
CW		 1039 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
1040 intel_sdvo->sdvo_flags = input_dtd.part2.sdvo_flags;
79e53945 1041
32aad86f
CW		 1042 drm_mode_set_crtcinfo(adjusted_mode, 0);
1043 mode->clock = adjusted_mode->clock;
1044 return true;
1045}
12682a97 1046
32aad86f
CW		 1047static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
1048 struct drm_display_mode *mode,
1049 struct drm_display_mode *adjusted_mode)
1050{
1051 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
12682a97 1052
32aad86f
CW		 1053 /* We need to construct preferred input timings based on our
1054 * output timings. To do that, we have to set the output
1055 * timings, even though this isn't really the right place in
1056 * the sequence to do it. Oh well.
1057 */
1058 if (intel_sdvo->is_tv) {
1059 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
1060 return false;
12682a97 1061
32aad86f 1062 if (!intel_sdvo_set_input_timings_for_mode(intel_sdvo, mode, adjusted_mode))
12682a97 1063 return false;
ea5b213a 1064 } else if (intel_sdvo->is_lvds) {
ea5b213a 1065 drm_mode_set_crtcinfo(intel_sdvo->sdvo_lvds_fixed_mode, 0);
e2f0ba97 1066
32aad86f
CW		 1067 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
1068 intel_sdvo->sdvo_lvds_fixed_mode))
e2f0ba97 1069 return false;
12682a97 1070
32aad86f
CW		 1071 if (!intel_sdvo_set_input_timings_for_mode(intel_sdvo, mode, adjusted_mode))
1072 return false;
e2f0ba97 1073 }
32aad86f
CW		 1074
1075 /* Make the CRTC code factor in the SDVO pixel multiplier. The
1076 * SDVO device will be told of the multiplier during mode_set.
1077 */
1078 adjusted_mode->clock *= intel_sdvo_get_pixel_multiplier(mode);
1079
e2f0ba97
JB		 1080 return true;
1081}
1082
1083static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1084 struct drm_display_mode *mode,
1085 struct drm_display_mode *adjusted_mode)
1086{
1087 struct drm_device *dev = encoder->dev;
1088 struct drm_i915_private *dev_priv = dev->dev_private;
1089 struct drm_crtc *crtc = encoder->crtc;
1090 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ea5b213a 1091 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
e2f0ba97 1092 u32 sdvox = 0;
32aad86f 1093 int sdvo_pixel_multiply, rate;
e2f0ba97
JB		 1094 struct intel_sdvo_in_out_map in_out;
1095 struct intel_sdvo_dtd input_dtd;
e2f0ba97
JB		 1096
1097 if (!mode)
1098 return;
1099
1100 /* First, set the input mapping for the first input to our controlled
1101 * output. This is only correct if we're a single-input device, in
1102 * which case the first input is the output from the appropriate SDVO
1103 * channel on the motherboard. In a two-input device, the first input
1104 * will be SDVOB and the second SDVOC.
1105 */
ea5b213a 1106 in_out.in0 = intel_sdvo->attached_output;
e2f0ba97
JB		 1107 in_out.in1 = 0;
1108
32aad86f
CW		 1109 if (!intel_sdvo_set_value(intel_sdvo,
1110 SDVO_CMD_SET_IN_OUT_MAP,
1111 &in_out, sizeof(in_out)))
1112 return;
e2f0ba97 1113
ea5b213a 1114 if (intel_sdvo->is_hdmi) {
32aad86f
CW		 1115 if (!intel_sdvo_set_avi_infoframe(intel_sdvo, mode))
1116 return;
1117
e2f0ba97
JB		 1118 sdvox |= SDVO_AUDIO_ENABLE;
1119 }
1120
7026d4ac
ZW		 1121 /* We have tried to get input timing in mode_fixup, and filled into
1122 adjusted_mode */
ea5b213a 1123 if (intel_sdvo->is_tv || intel_sdvo->is_lvds) {
7026d4ac 1124 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
ea5b213a 1125 input_dtd.part2.sdvo_flags = intel_sdvo->sdvo_flags;
12682a97 1126 } else
7026d4ac 1127 intel_sdvo_get_dtd_from_mode(&input_dtd, mode);
e2f0ba97
JB		 1128
1129 /* If it's a TV, we already set the output timing in mode_fixup.
1130 * Otherwise, the output timing is equal to the input timing.
1131 */
ea5b213a 1132 if (!intel_sdvo->is_tv && !intel_sdvo->is_lvds) {
e2f0ba97 1133 /* Set the output timing to the screen */
32aad86f
CW		 1134 if (!intel_sdvo_set_target_output(intel_sdvo,
1135 intel_sdvo->attached_output))
1136 return;
1137
1138 if (!intel_sdvo_set_output_timing(intel_sdvo, &input_dtd))
1139 return;
e2f0ba97 1140 }
79e53945
JB		 1141
1142 /* Set the input timing to the screen. Assume always input 0. */
32aad86f
CW		 1143 if (!intel_sdvo_set_target_input(intel_sdvo))
1144 return;
79e53945 1145
32aad86f
CW		 1146 if (intel_sdvo->is_tv) {
1147 if (!intel_sdvo_set_tv_format(intel_sdvo))
1148 return;
1149 }
7026d4ac 1150
e2f0ba97 1151 /* We would like to use intel_sdvo_create_preferred_input_timing() to
79e53945
JB		 1152 * provide the device with a timing it can support, if it supports that
1153 * feature. However, presumably we would need to adjust the CRTC to
1154 * output the preferred timing, and we don't support that currently.
1155 */
e2f0ba97 1156#if 0
c751ce4f 1157 success = intel_sdvo_create_preferred_input_timing(encoder, clock,
e2f0ba97
JB		 1158 width, height);
1159 if (success) {
1160 struct intel_sdvo_dtd *input_dtd;
1161
c751ce4f
EA		 1162 intel_sdvo_get_preferred_input_timing(encoder, &input_dtd);
1163 intel_sdvo_set_input_timing(encoder, &input_dtd);
e2f0ba97
JB		 1164 }
1165#else
32aad86f
CW		 1166 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
1167 return;
e2f0ba97 1168#endif
79e53945 1169
32aad86f
CW		 1170 sdvo_pixel_multiply = intel_sdvo_get_pixel_multiplier(mode);
1171 switch (sdvo_pixel_multiply) {
1172 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1173 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1174 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
79e53945 1175 }
32aad86f
CW		 1176 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1177 return;
79e53945
JB		 1178
1179 /* Set the SDVO control regs. */
e2f0ba97 1180 if (IS_I965G(dev)) {
81a14b46
AJ		 1181 sdvox |= SDVO_BORDER_ENABLE;
1182 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1183 sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
1184 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1185 sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
e2f0ba97 1186 } else {
ea5b213a
CW		 1187 sdvox |= I915_READ(intel_sdvo->sdvo_reg);
1188 switch (intel_sdvo->sdvo_reg) {
e2f0ba97
JB		 1189 case SDVOB:
1190 sdvox &= SDVOB_PRESERVE_MASK;
1191 break;
1192 case SDVOC:
1193 sdvox &= SDVOC_PRESERVE_MASK;
1194 break;
1195 }
1196 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1197 }
79e53945
JB		 1198 if (intel_crtc->pipe == 1)
1199 sdvox |= SDVO_PIPE_B_SELECT;
1200
79e53945 1201 if (IS_I965G(dev)) {
e2f0ba97
JB		 1202 /* done in crtc_mode_set as the dpll_md reg must be written early */
1203 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1204 /* done in crtc_mode_set as it lives inside the dpll register */
79e53945
JB		 1205 } else {
1206 sdvox |= (sdvo_pixel_multiply - 1) << SDVO_PORT_MULTIPLY_SHIFT;
1207 }
1208
ea5b213a 1209 if (intel_sdvo->sdvo_flags & SDVO_NEED_TO_STALL)
12682a97 1210 sdvox |= SDVO_STALL_SELECT;
ea5b213a 1211 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
79e53945
JB		 1212}
1213
1214static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1215{
1216 struct drm_device *dev = encoder->dev;
1217 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 1218 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
79e53945
JB		 1219 u32 temp;
1220
1221 if (mode != DRM_MODE_DPMS_ON) {
ea5b213a 1222 intel_sdvo_set_active_outputs(intel_sdvo, 0);
79e53945 1223 if (0)
ea5b213a 1224 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
79e53945
JB		 1225
1226 if (mode == DRM_MODE_DPMS_OFF) {
ea5b213a 1227 temp = I915_READ(intel_sdvo->sdvo_reg);
79e53945 1228 if ((temp & SDVO_ENABLE) != 0) {
ea5b213a 1229 intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
79e53945
JB		 1230 }
1231 }
1232 } else {
1233 bool input1, input2;
1234 int i;
1235 u8 status;
1236
ea5b213a 1237 temp = I915_READ(intel_sdvo->sdvo_reg);
79e53945 1238 if ((temp & SDVO_ENABLE) == 0)
ea5b213a 1239 intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
79e53945
JB		 1240 for (i = 0; i < 2; i++)
1241 intel_wait_for_vblank(dev);
1242
32aad86f 1243 status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
79e53945
JB		 1244 /* Warn if the device reported failure to sync.
1245 * A lot of SDVO devices fail to notify of sync, but it's
1246 * a given it the status is a success, we succeeded.
1247 */
1248 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
8a4c47f3 1249 DRM_DEBUG_KMS("First %s output reported failure to "
ea5b213a 1250 "sync\n", SDVO_NAME(intel_sdvo));
79e53945
JB		 1251 }
1252
1253 if (0)
ea5b213a
CW		 1254 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
1255 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
79e53945
JB		 1256 }
1257 return;
1258}
1259
79e53945
JB		 1260static int intel_sdvo_mode_valid(struct drm_connector *connector,
1261 struct drm_display_mode *mode)
1262{
d2a82a6f 1263 struct drm_encoder *encoder = intel_attached_encoder(connector);
ea5b213a 1264 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
79e53945
JB		 1265
1266 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1267 return MODE_NO_DBLESCAN;
1268
ea5b213a 1269 if (intel_sdvo->pixel_clock_min > mode->clock)
79e53945
JB		 1270 return MODE_CLOCK_LOW;
1271
ea5b213a 1272 if (intel_sdvo->pixel_clock_max < mode->clock)
79e53945
JB		 1273 return MODE_CLOCK_HIGH;
1274
ea5b213a
CW		 1275 if (intel_sdvo->is_lvds == true) {
1276 if (intel_sdvo->sdvo_lvds_fixed_mode == NULL)
12682a97 1277 return MODE_PANEL;
1278
ea5b213a 1279 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
12682a97 1280 return MODE_PANEL;
1281
ea5b213a 1282 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
12682a97 1283 return MODE_PANEL;
1284 }
1285
79e53945
JB		 1286 return MODE_OK;
1287}
1288
ea5b213a 1289static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
79e53945 1290{
32aad86f 1291 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DEVICE_CAPS, caps, sizeof(*caps));
79e53945
JB		 1292}
1293
d2a82a6f
ZW		 1294/* No use! */
1295#if 0
79e53945
JB		 1296struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB)
1297{
1298 struct drm_connector *connector = NULL;
ea5b213a
CW		 1299 struct intel_sdvo *iout = NULL;
1300 struct intel_sdvo *sdvo;
79e53945
JB		 1301
1302 /* find the sdvo connector */
1303 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
ea5b213a 1304 iout = to_intel_sdvo(connector);
79e53945
JB		 1305
1306 if (iout->type != INTEL_OUTPUT_SDVO)
1307 continue;
1308
1309 sdvo = iout->dev_priv;
1310
c751ce4f 1311 if (sdvo->sdvo_reg == SDVOB && sdvoB)
79e53945
JB		 1312 return connector;
1313
c751ce4f 1314 if (sdvo->sdvo_reg == SDVOC && !sdvoB)
79e53945
JB		 1315 return connector;
1316
1317 }
1318
1319 return NULL;
1320}
1321
1322int intel_sdvo_supports_hotplug(struct drm_connector *connector)
1323{
1324 u8 response[2];
1325 u8 status;
ea5b213a 1326 struct intel_sdvo *intel_sdvo;
8a4c47f3 1327 DRM_DEBUG_KMS("\n");
79e53945
JB		 1328
1329 if (!connector)
1330 return 0;
1331
ea5b213a 1332 intel_sdvo = to_intel_sdvo(connector);
79e53945 1333
32aad86f
CW		 1334 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1335 &response, 2) && response[0];
79e53945
JB		 1336}
1337
1338void intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
1339{
1340 u8 response[2];
1341 u8 status;
ea5b213a 1342 struct intel_sdvo *intel_sdvo = to_intel_sdvo(connector);
79e53945 1343
ea5b213a
CW		 1344 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1345 intel_sdvo_read_response(intel_sdvo, &response, 2);
79e53945
JB		 1346
1347 if (on) {
ea5b213a
CW		 1348 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1349 status = intel_sdvo_read_response(intel_sdvo, &response, 2);
79e53945 1350
ea5b213a 1351 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
79e53945
JB		 1352 } else {
1353 response[0] = 0;
1354 response[1] = 0;
ea5b213a 1355 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
79e53945
JB		 1356 }
1357
ea5b213a
CW		 1358 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1359 intel_sdvo_read_response(intel_sdvo, &response, 2);
79e53945 1360}
d2a82a6f 1361#endif
79e53945 1362
fb7a46f3 1363static bool
ea5b213a 1364intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
fb7a46f3 1365{
fb7a46f3 1366 int caps = 0;
1367
ea5b213a 1368 if (intel_sdvo->caps.output_flags &
fb7a46f3 1369 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1))
1370 caps++;
ea5b213a 1371 if (intel_sdvo->caps.output_flags &
fb7a46f3 1372 (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1))
1373 caps++;
ea5b213a 1374 if (intel_sdvo->caps.output_flags &
19e1f888 1375 (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_SVID1))
fb7a46f3 1376 caps++;
ea5b213a 1377 if (intel_sdvo->caps.output_flags &
fb7a46f3 1378 (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_CVBS1))
1379 caps++;
ea5b213a 1380 if (intel_sdvo->caps.output_flags &
fb7a46f3 1381 (SDVO_OUTPUT_YPRPB0 | SDVO_OUTPUT_YPRPB1))
1382 caps++;
1383
ea5b213a 1384 if (intel_sdvo->caps.output_flags &
fb7a46f3 1385 (SDVO_OUTPUT_SCART0 | SDVO_OUTPUT_SCART1))
1386 caps++;
1387
ea5b213a 1388 if (intel_sdvo->caps.output_flags &
fb7a46f3 1389 (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1))
1390 caps++;
1391
1392 return (caps > 1);
1393}
1394
57cdaf90
KP		 1395static struct drm_connector *
1396intel_find_analog_connector(struct drm_device *dev)
1397{
1398 struct drm_connector *connector;
d2a82a6f 1399 struct drm_encoder *encoder;
ea5b213a 1400 struct intel_sdvo *intel_sdvo;
57cdaf90 1401
d2a82a6f 1402 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
ea5b213a
CW		 1403 intel_sdvo = enc_to_intel_sdvo(encoder);
1404 if (intel_sdvo->base.type == INTEL_OUTPUT_ANALOG) {
d2a82a6f 1405 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
90a78e8f 1406 if (encoder == intel_attached_encoder(connector))
d2a82a6f
ZW		 1407 return connector;
1408 }
1409 }
57cdaf90
KP		 1410 }
1411 return NULL;
1412}
1413
1414static int
1415intel_analog_is_connected(struct drm_device *dev)
1416{
1417 struct drm_connector *analog_connector;
57cdaf90 1418
32aad86f 1419 analog_connector = intel_find_analog_connector(dev);
57cdaf90
KP		 1420 if (!analog_connector)
1421 return false;
1422
1423 if (analog_connector->funcs->detect(analog_connector) ==
1424 connector_status_disconnected)
1425 return false;
1426
1427 return true;
1428}
1429
2b8d33f7 1430enum drm_connector_status
149c36a3 1431intel_sdvo_hdmi_sink_detect(struct drm_connector *connector)
9dff6af8 1432{
d2a82a6f 1433 struct drm_encoder *encoder = intel_attached_encoder(connector);
ea5b213a 1434 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
615fb93f 1435 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
2b8d33f7 1436 enum drm_connector_status status = connector_status_connected;
9dff6af8
ML		 1437 struct edid *edid = NULL;
1438
ea5b213a 1439 edid = drm_get_edid(connector, intel_sdvo->base.ddc_bus);
57cdaf90 1440
7c3f0a27 1441 /* This is only applied to SDVO cards with multiple outputs */
ea5b213a 1442 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
7c3f0a27 1443 uint8_t saved_ddc, temp_ddc;
ea5b213a
CW		 1444 saved_ddc = intel_sdvo->ddc_bus;
1445 temp_ddc = intel_sdvo->ddc_bus >> 1;
7c3f0a27
ZY		 1446 /*
1447 * Don't use the 1 as the argument of DDC bus switch to get
1448 * the EDID. It is used for SDVO SPD ROM.
1449 */
1450 while(temp_ddc > 1) {
ea5b213a
CW		 1451 intel_sdvo->ddc_bus = temp_ddc;
1452 edid = drm_get_edid(connector, intel_sdvo->base.ddc_bus);
7c3f0a27
ZY		 1453 if (edid) {
1454 /*
1455 * When we can get the EDID, maybe it is the
1456 * correct DDC bus. Update it.
1457 */
ea5b213a 1458 intel_sdvo->ddc_bus = temp_ddc;
7c3f0a27
ZY		 1459 break;
1460 }
1461 temp_ddc >>= 1;
1462 }
1463 if (edid == NULL)
ea5b213a 1464 intel_sdvo->ddc_bus = saved_ddc;
7c3f0a27 1465 }
57cdaf90
KP		 1466 /* when there is no edid and no monitor is connected with VGA
1467 * port, try to use the CRT ddc to read the EDID for DVI-connector
1468 */
ea5b213a 1469 if (edid == NULL && intel_sdvo->analog_ddc_bus &&
d2a82a6f 1470 !intel_analog_is_connected(connector->dev))
ea5b213a 1471 edid = drm_get_edid(connector, intel_sdvo->analog_ddc_bus);
149c36a3 1472
9dff6af8 1473 if (edid != NULL) {
149c36a3 1474 bool is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
615fb93f 1475 bool need_digital = !!(intel_sdvo_connector->output_flag & SDVO_TMDS_MASK);
2b8d33f7 1476
149c36a3
AJ		 1477 /* DDC bus is shared, match EDID to connector type */
1478 if (is_digital && need_digital)
ea5b213a 1479 intel_sdvo->is_hdmi = drm_detect_hdmi_monitor(edid);
149c36a3
AJ		 1480 else if (is_digital != need_digital)
1481 status = connector_status_disconnected;
2b8d33f7 1482
149c36a3
AJ		 1483 connector->display_info.raw_edid = NULL;
1484 } else
2b8d33f7 1485 status = connector_status_disconnected;
149c36a3
AJ		 1486
1487 kfree(edid);
2b8d33f7 1488
1489 return status;
9dff6af8
ML		 1490}
1491
79e53945
JB		 1492static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connector)
1493{
fb7a46f3 1494 uint16_t response;
d2a82a6f 1495 struct drm_encoder *encoder = intel_attached_encoder(connector);
ea5b213a 1496 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
615fb93f 1497 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
14571b4c 1498 enum drm_connector_status ret;
79e53945 1499
32aad86f
CW		 1500 if (!intel_sdvo_write_cmd(intel_sdvo,
1501 SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0))
1502 return connector_status_unknown;
ea5b213a 1503 if (intel_sdvo->is_tv) {
d09c23de
ZY		 1504 /* add 30ms delay when the output type is SDVO-TV */
1505 mdelay(30);
1506 }
32aad86f
CW		 1507 if (!intel_sdvo_read_response(intel_sdvo, &response, 2))
1508 return connector_status_unknown;
79e53945 1509
51c8b407 1510 DRM_DEBUG_KMS("SDVO response %d %d\n", response & 0xff, response >> 8);
e2f0ba97 1511
fb7a46f3 1512 if (response == 0)
79e53945 1513 return connector_status_disconnected;
fb7a46f3 1514
ea5b213a 1515 intel_sdvo->attached_output = response;
14571b4c 1516
615fb93f 1517 if ((intel_sdvo_connector->output_flag & response) == 0)
14571b4c 1518 ret = connector_status_disconnected;
149c36a3
AJ		 1519 else if (response & SDVO_TMDS_MASK)
1520 ret = intel_sdvo_hdmi_sink_detect(connector);
14571b4c
ZW		 1521 else
1522 ret = connector_status_connected;
1523
1524 /* May update encoder flag for like clock for SDVO TV, etc.*/
1525 if (ret == connector_status_connected) {
ea5b213a
CW		 1526 intel_sdvo->is_tv = false;
1527 intel_sdvo->is_lvds = false;
1528 intel_sdvo->base.needs_tv_clock = false;
14571b4c
ZW		 1529
1530 if (response & SDVO_TV_MASK) {
ea5b213a
CW		 1531 intel_sdvo->is_tv = true;
1532 intel_sdvo->base.needs_tv_clock = true;
14571b4c
ZW		 1533 }
1534 if (response & SDVO_LVDS_MASK)
ea5b213a 1535 intel_sdvo->is_lvds = true;
fb7a46f3 1536 }
14571b4c
ZW		 1537
1538 return ret;
79e53945
JB		 1539}
1540
e2f0ba97 1541static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
79e53945 1542{
d2a82a6f 1543 struct drm_encoder *encoder = intel_attached_encoder(connector);
ea5b213a 1544 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
57cdaf90 1545 int num_modes;
79e53945
JB		 1546
1547 /* set the bus switch and get the modes */
ea5b213a 1548 num_modes = intel_ddc_get_modes(connector, intel_sdvo->base.ddc_bus);
79e53945 1549
57cdaf90
KP		 1550 /*
1551 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1552 * link between analog and digital outputs. So, if the regular SDVO
1553 * DDC fails, check to see if the analog output is disconnected, in
1554 * which case we'll look there for the digital DDC data.
e2f0ba97 1555 */
57cdaf90 1556 if (num_modes == 0 &&
ea5b213a 1557 intel_sdvo->analog_ddc_bus &&
d2a82a6f 1558 !intel_analog_is_connected(connector->dev)) {
57cdaf90
KP		 1559 /* Switch to the analog ddc bus and try that
1560 */
ea5b213a 1561 (void) intel_ddc_get_modes(connector, intel_sdvo->analog_ddc_bus);
e2f0ba97 1562 }
e2f0ba97
JB		 1563}
1564
1565/*
1566 * Set of SDVO TV modes.
1567 * Note! This is in reply order (see loop in get_tv_modes).
1568 * XXX: all 60Hz refresh?
1569 */
1570struct drm_display_mode sdvo_tv_modes[] = {
7026d4ac
ZW		 1571 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1572 416, 0, 200, 201, 232, 233, 0,
e2f0ba97 1573 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1574 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1575 416, 0, 240, 241, 272, 273, 0,
e2f0ba97 1576 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1577 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1578 496, 0, 300, 301, 332, 333, 0,
e2f0ba97 1579 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1580 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1581 736, 0, 350, 351, 382, 383, 0,
e2f0ba97 1582 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1583 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1584 736, 0, 400, 401, 432, 433, 0,
e2f0ba97 1585 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1586 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1587 736, 0, 480, 481, 512, 513, 0,
e2f0ba97 1588 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1589 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1590 800, 0, 480, 481, 512, 513, 0,
e2f0ba97 1591 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1592 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1593 800, 0, 576, 577, 608, 609, 0,
e2f0ba97 1594 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1595 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1596 816, 0, 350, 351, 382, 383, 0,
e2f0ba97 1597 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1598 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1599 816, 0, 400, 401, 432, 433, 0,
e2f0ba97 1600 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1601 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1602 816, 0, 480, 481, 512, 513, 0,
e2f0ba97 1603 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1604 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1605 816, 0, 540, 541, 572, 573, 0,
e2f0ba97 1606 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1607 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1608 816, 0, 576, 577, 608, 609, 0,
e2f0ba97 1609 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1610 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1611 864, 0, 576, 577, 608, 609, 0,
e2f0ba97 1612 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1613 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1614 896, 0, 600, 601, 632, 633, 0,
e2f0ba97 1615 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1616 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1617 928, 0, 624, 625, 656, 657, 0,
e2f0ba97 1618 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1619 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1620 1016, 0, 766, 767, 798, 799, 0,
e2f0ba97 1621 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1622 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1623 1120, 0, 768, 769, 800, 801, 0,
e2f0ba97 1624 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1625 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1626 1376, 0, 1024, 1025, 1056, 1057, 0,
e2f0ba97
JB		 1627 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1628};
1629
1630static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1631{
d2a82a6f 1632 struct drm_encoder *encoder = intel_attached_encoder(connector);
ea5b213a 1633 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
7026d4ac 1634 struct intel_sdvo_sdtv_resolution_request tv_res;
ce6feabd
ZY		 1635 uint32_t reply = 0, format_map = 0;
1636 int i;
e2f0ba97
JB		 1637
1638 /* Read the list of supported input resolutions for the selected TV
1639 * format.
1640 */
40039750 1641 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 1642 memcpy(&tv_res, &format_map,
32aad86f 1643 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
ce6feabd 1644
32aad86f
CW		 1645 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
1646 return;
ce6feabd 1647
32aad86f
CW		 1648 BUILD_BUG_ON(sizeof(tv_res) != 3);
1649 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
1650 &tv_res, sizeof(tv_res)))
1651 return;
1652 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
e2f0ba97
JB		 1653 return;
1654
1655 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
7026d4ac
ZW		 1656 if (reply & (1 << i)) {
1657 struct drm_display_mode *nmode;
1658 nmode = drm_mode_duplicate(connector->dev,
32aad86f 1659 &sdvo_tv_modes[i]);
7026d4ac
ZW		 1660 if (nmode)
1661 drm_mode_probed_add(connector, nmode);
1662 }
e2f0ba97
JB		 1663}
1664
7086c87f
ML		 1665static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1666{
d2a82a6f 1667 struct drm_encoder *encoder = intel_attached_encoder(connector);
ea5b213a 1668 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
7086c87f 1669 struct drm_i915_private *dev_priv = connector->dev->dev_private;
12682a97 1670 struct drm_display_mode *newmode;
7086c87f
ML		 1671
1672 /*
1673 * Attempt to get the mode list from DDC.
1674 * Assume that the preferred modes are
1675 * arranged in priority order.
1676 */
ea5b213a 1677 intel_ddc_get_modes(connector, intel_sdvo->base.ddc_bus);
7086c87f 1678 if (list_empty(&connector->probed_modes) == false)
12682a97 1679 goto end;
7086c87f
ML		 1680
1681 /* Fetch modes from VBT */
1682 if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
7086c87f
ML		 1683 newmode = drm_mode_duplicate(connector->dev,
1684 dev_priv->sdvo_lvds_vbt_mode);
1685 if (newmode != NULL) {
1686 /* Guarantee the mode is preferred */
1687 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1688 DRM_MODE_TYPE_DRIVER);
1689 drm_mode_probed_add(connector, newmode);
1690 }
1691 }
12682a97 1692
1693end:
1694 list_for_each_entry(newmode, &connector->probed_modes, head) {
1695 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
ea5b213a 1696 intel_sdvo->sdvo_lvds_fixed_mode =
12682a97 1697 drm_mode_duplicate(connector->dev, newmode);
1698 break;
1699 }
1700 }
1701
7086c87f
ML		 1702}
1703
e2f0ba97
JB		 1704static int intel_sdvo_get_modes(struct drm_connector *connector)
1705{
615fb93f 1706 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e2f0ba97 1707
615fb93f 1708 if (IS_TV(intel_sdvo_connector))
e2f0ba97 1709 intel_sdvo_get_tv_modes(connector);
615fb93f 1710 else if (IS_LVDS(intel_sdvo_connector))
7086c87f 1711 intel_sdvo_get_lvds_modes(connector);
e2f0ba97
JB		 1712 else
1713 intel_sdvo_get_ddc_modes(connector);
1714
32aad86f 1715 return !list_empty(&connector->probed_modes);
79e53945
JB		 1716}
1717
fcc8d672
CW		 1718static void
1719intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
b9219c5e 1720{
615fb93f 1721 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
b9219c5e
ZY		 1722 struct drm_device *dev = connector->dev;
1723
c5521706
CW		 1724 if (intel_sdvo_connector->left)
1725 drm_property_destroy(dev, intel_sdvo_connector->left);
1726 if (intel_sdvo_connector->right)
1727 drm_property_destroy(dev, intel_sdvo_connector->right);
1728 if (intel_sdvo_connector->top)
1729 drm_property_destroy(dev, intel_sdvo_connector->top);
1730 if (intel_sdvo_connector->bottom)
1731 drm_property_destroy(dev, intel_sdvo_connector->bottom);
1732 if (intel_sdvo_connector->hpos)
1733 drm_property_destroy(dev, intel_sdvo_connector->hpos);
1734 if (intel_sdvo_connector->vpos)
1735 drm_property_destroy(dev, intel_sdvo_connector->vpos);
1736 if (intel_sdvo_connector->saturation)
1737 drm_property_destroy(dev, intel_sdvo_connector->saturation);
1738 if (intel_sdvo_connector->contrast)
1739 drm_property_destroy(dev, intel_sdvo_connector->contrast);
1740 if (intel_sdvo_connector->hue)
1741 drm_property_destroy(dev, intel_sdvo_connector->hue);
1742 if (intel_sdvo_connector->sharpness)
1743 drm_property_destroy(dev, intel_sdvo_connector->sharpness);
1744 if (intel_sdvo_connector->flicker_filter)
1745 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
1746 if (intel_sdvo_connector->flicker_filter_2d)
1747 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
1748 if (intel_sdvo_connector->flicker_filter_adaptive)
1749 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
1750 if (intel_sdvo_connector->tv_luma_filter)
1751 drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
1752 if (intel_sdvo_connector->tv_chroma_filter)
1753 drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
1754 if (intel_sdvo_connector->brightness)
1755 drm_property_destroy(dev, intel_sdvo_connector->brightness);
b9219c5e
ZY		 1756}
1757
79e53945
JB		 1758static void intel_sdvo_destroy(struct drm_connector *connector)
1759{
615fb93f 1760 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
79e53945 1761
c5521706 1762 if (intel_sdvo_connector->tv_format)
ce6feabd 1763 drm_property_destroy(connector->dev,
c5521706 1764 intel_sdvo_connector->tv_format);
b9219c5e 1765
d2a82a6f 1766 intel_sdvo_destroy_enhance_property(connector);
79e53945
JB		 1767 drm_sysfs_connector_remove(connector);
1768 drm_connector_cleanup(connector);
d2a82a6f 1769 kfree(connector);
79e53945
JB		 1770}
1771
ce6feabd
ZY		 1772static int
1773intel_sdvo_set_property(struct drm_connector *connector,
1774 struct drm_property *property,
1775 uint64_t val)
1776{
d2a82a6f 1777 struct drm_encoder *encoder = intel_attached_encoder(connector);
ea5b213a 1778 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
615fb93f 1779 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
b9219c5e 1780 uint16_t temp_value;
32aad86f
CW		 1781 uint8_t cmd;
1782 int ret;
ce6feabd
ZY		 1783
1784 ret = drm_connector_property_set_value(connector, property, val);
32aad86f
CW		 1785 if (ret)
1786 return ret;
ce6feabd 1787
c5521706
CW		 1788#define CHECK_PROPERTY(name, NAME) \
1789 if (intel_sdvo_connector->name == property) { \
1790 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
1791 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
1792 cmd = SDVO_CMD_SET_##NAME; \
1793 intel_sdvo_connector->cur_##name = temp_value; \
1794 goto set_value; \
1795 }
1796
1797 if (property == intel_sdvo_connector->tv_format) {
32aad86f
CW		 1798 if (val >= TV_FORMAT_NUM)
1799 return -EINVAL;
1800
40039750 1801 if (intel_sdvo->tv_format_index ==
615fb93f 1802 intel_sdvo_connector->tv_format_supported[val])
32aad86f 1803 return 0;
ce6feabd 1804
40039750 1805 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
c5521706 1806 goto done;
32aad86f 1807 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
b9219c5e 1808 temp_value = val;
c5521706 1809 if (intel_sdvo_connector->left == property) {
b9219c5e 1810 drm_connector_property_set_value(connector,
c5521706 1811 intel_sdvo_connector->right, val);
615fb93f 1812 if (intel_sdvo_connector->left_margin == temp_value)
32aad86f 1813 return 0;
b9219c5e 1814
615fb93f
CW		 1815 intel_sdvo_connector->left_margin = temp_value;
1816 intel_sdvo_connector->right_margin = temp_value;
1817 temp_value = intel_sdvo_connector->max_hscan -
c5521706 1818 intel_sdvo_connector->left_margin;
b9219c5e 1819 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 1820 goto set_value;
1821 } else if (intel_sdvo_connector->right == property) {
b9219c5e 1822 drm_connector_property_set_value(connector,
c5521706 1823 intel_sdvo_connector->left, val);
615fb93f 1824 if (intel_sdvo_connector->right_margin == temp_value)
32aad86f 1825 return 0;
b9219c5e 1826
615fb93f
CW		 1827 intel_sdvo_connector->left_margin = temp_value;
1828 intel_sdvo_connector->right_margin = temp_value;
1829 temp_value = intel_sdvo_connector->max_hscan -
1830 intel_sdvo_connector->left_margin;
b9219c5e 1831 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 1832 goto set_value;
1833 } else if (intel_sdvo_connector->top == property) {
b9219c5e 1834 drm_connector_property_set_value(connector,
c5521706 1835 intel_sdvo_connector->bottom, val);
615fb93f 1836 if (intel_sdvo_connector->top_margin == temp_value)
32aad86f 1837 return 0;
b9219c5e 1838
615fb93f
CW		 1839 intel_sdvo_connector->top_margin = temp_value;
1840 intel_sdvo_connector->bottom_margin = temp_value;
1841 temp_value = intel_sdvo_connector->max_vscan -
c5521706 1842 intel_sdvo_connector->top_margin;
b9219c5e 1843 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 1844 goto set_value;
1845 } else if (intel_sdvo_connector->bottom == property) {
b9219c5e 1846 drm_connector_property_set_value(connector,
c5521706 1847 intel_sdvo_connector->top, val);
615fb93f 1848 if (intel_sdvo_connector->bottom_margin == temp_value)
32aad86f
CW		 1849 return 0;
1850
615fb93f
CW		 1851 intel_sdvo_connector->top_margin = temp_value;
1852 intel_sdvo_connector->bottom_margin = temp_value;
1853 temp_value = intel_sdvo_connector->max_vscan -
c5521706 1854 intel_sdvo_connector->top_margin;
b9219c5e 1855 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 1856 goto set_value;
1857 }
1858 CHECK_PROPERTY(hpos, HPOS)
1859 CHECK_PROPERTY(vpos, VPOS)
1860 CHECK_PROPERTY(saturation, SATURATION)
1861 CHECK_PROPERTY(contrast, CONTRAST)
1862 CHECK_PROPERTY(hue, HUE)
1863 CHECK_PROPERTY(brightness, BRIGHTNESS)
1864 CHECK_PROPERTY(sharpness, SHARPNESS)
1865 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
1866 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
1867 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
1868 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
1869 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
1870 }
b9219c5e 1871
c5521706 1872 return -EINVAL; /* unknown property */
b9219c5e 1873
c5521706
CW		 1874set_value:
1875 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
1876 return -EIO;
b9219c5e 1877
b9219c5e 1878
c5521706
CW		 1879done:
1880 if (encoder->crtc) {
1881 struct drm_crtc *crtc = encoder->crtc;
32aad86f 1882
ce6feabd 1883 drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
c5521706
CW		 1884 crtc->y, crtc->fb);
1885 }
1886
32aad86f 1887 return 0;
c5521706 1888#undef CHECK_PROPERTY
ce6feabd
ZY		 1889}
1890
79e53945
JB		 1891static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
1892 .dpms = intel_sdvo_dpms,
1893 .mode_fixup = intel_sdvo_mode_fixup,
1894 .prepare = intel_encoder_prepare,
1895 .mode_set = intel_sdvo_mode_set,
1896 .commit = intel_encoder_commit,
1897};
1898
1899static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
c9fb15f6 1900 .dpms = drm_helper_connector_dpms,
79e53945
JB		 1901 .detect = intel_sdvo_detect,
1902 .fill_modes = drm_helper_probe_single_connector_modes,
ce6feabd 1903 .set_property = intel_sdvo_set_property,
79e53945
JB		 1904 .destroy = intel_sdvo_destroy,
1905};
1906
1907static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
1908 .get_modes = intel_sdvo_get_modes,
1909 .mode_valid = intel_sdvo_mode_valid,
d2a82a6f 1910 .best_encoder = intel_attached_encoder,
79e53945
JB		 1911};
1912
b358d0a6 1913static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
79e53945 1914{
ea5b213a 1915 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
d2a82a6f 1916
ea5b213a
CW		 1917 if (intel_sdvo->analog_ddc_bus)
1918 intel_i2c_destroy(intel_sdvo->analog_ddc_bus);
d2a82a6f 1919
ea5b213a 1920 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
d2a82a6f 1921 drm_mode_destroy(encoder->dev,
ea5b213a 1922 intel_sdvo->sdvo_lvds_fixed_mode);
d2a82a6f 1923
ea5b213a 1924 intel_encoder_destroy(encoder);
79e53945
JB		 1925}
1926
1927static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
1928 .destroy = intel_sdvo_enc_destroy,
1929};
1930
1931
e2f0ba97
JB		 1932/**
1933 * Choose the appropriate DDC bus for control bus switch command for this
1934 * SDVO output based on the controlled output.
1935 *
1936 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
1937 * outputs, then LVDS outputs.
1938 */
1939static void
b1083333 1940intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
ea5b213a 1941 struct intel_sdvo *sdvo, u32 reg)
e2f0ba97 1942{
b1083333 1943 struct sdvo_device_mapping *mapping;
e2f0ba97 1944
b1083333
AJ		 1945 if (IS_SDVOB(reg))
1946 mapping = &(dev_priv->sdvo_mappings[0]);
1947 else
1948 mapping = &(dev_priv->sdvo_mappings[1]);
e2f0ba97 1949
b1083333 1950 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
e2f0ba97
JB		 1951}
1952
1953static bool
ea5b213a 1954intel_sdvo_get_digital_encoding_mode(struct intel_sdvo *intel_sdvo, int device)
e2f0ba97 1955{
32aad86f
CW		 1956 return intel_sdvo_set_target_output(intel_sdvo,
1957 device == 0 ? SDVO_OUTPUT_TMDS0 : SDVO_OUTPUT_TMDS1) &&
1958 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE,
1959 &intel_sdvo->is_hdmi, 1);
e2f0ba97
JB		 1960}
1961
ea5b213a
CW		 1962static struct intel_sdvo *
1963intel_sdvo_chan_to_intel_sdvo(struct intel_i2c_chan *chan)
619ac3b7
ML		 1964{
1965 struct drm_device *dev = chan->drm_dev;
d2a82a6f 1966 struct drm_encoder *encoder;
619ac3b7 1967
d2a82a6f 1968 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
ea5b213a
CW		 1969 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
1970 if (intel_sdvo->base.ddc_bus == &chan->adapter)
1971 return intel_sdvo;
619ac3b7 1972 }
ea5b213a 1973
32aad86f 1974 return NULL;
619ac3b7
ML		 1975}
1976
1977static int intel_sdvo_master_xfer(struct i2c_adapter *i2c_adap,
1978 struct i2c_msg msgs[], int num)
1979{
ea5b213a 1980 struct intel_sdvo *intel_sdvo;
619ac3b7 1981 struct i2c_algo_bit_data *algo_data;
f9c10a9b 1982 const struct i2c_algorithm *algo;
619ac3b7
ML		 1983
1984 algo_data = (struct i2c_algo_bit_data *)i2c_adap->algo_data;
ea5b213a
CW		 1985 intel_sdvo =
1986 intel_sdvo_chan_to_intel_sdvo((struct intel_i2c_chan *)
1987 (algo_data->data));
1988 if (intel_sdvo == NULL)
619ac3b7
ML		 1989 return -EINVAL;
1990
ea5b213a 1991 algo = intel_sdvo->base.i2c_bus->algo;
619ac3b7 1992
ea5b213a 1993 intel_sdvo_set_control_bus_switch(intel_sdvo, intel_sdvo->ddc_bus);
619ac3b7
ML		 1994 return algo->master_xfer(i2c_adap, msgs, num);
1995}
1996
1997static struct i2c_algorithm intel_sdvo_i2c_bit_algo = {
1998 .master_xfer = intel_sdvo_master_xfer,
1999};
2000
714605e4 2001static u8
c751ce4f 2002intel_sdvo_get_slave_addr(struct drm_device *dev, int sdvo_reg)
714605e4 2003{
2004 struct drm_i915_private *dev_priv = dev->dev_private;
2005 struct sdvo_device_mapping *my_mapping, *other_mapping;
2006
461ed3ca 2007 if (IS_SDVOB(sdvo_reg)) {
714605e4 2008 my_mapping = &dev_priv->sdvo_mappings[0];
2009 other_mapping = &dev_priv->sdvo_mappings[1];
2010 } else {
2011 my_mapping = &dev_priv->sdvo_mappings[1];
2012 other_mapping = &dev_priv->sdvo_mappings[0];
2013 }
2014
2015 /* If the BIOS described our SDVO device, take advantage of it. */
2016 if (my_mapping->slave_addr)
2017 return my_mapping->slave_addr;
2018
2019 /* If the BIOS only described a different SDVO device, use the
2020 * address that it isn't using.
2021 */
2022 if (other_mapping->slave_addr) {
2023 if (other_mapping->slave_addr == 0x70)
2024 return 0x72;
2025 else
2026 return 0x70;
2027 }
2028
2029 /* No SDVO device info is found for another DVO port,
2030 * so use mapping assumption we had before BIOS parsing.
2031 */
461ed3ca 2032 if (IS_SDVOB(sdvo_reg))
714605e4 2033 return 0x70;
2034 else
2035 return 0x72;
2036}
2037
14571b4c 2038static void
32aad86f
CW		 2039intel_sdvo_connector_init(struct drm_encoder *encoder,
2040 struct drm_connector *connector)
14571b4c
ZW		 2041{
2042 drm_connector_init(encoder->dev, connector, &intel_sdvo_connector_funcs,
2043 connector->connector_type);
6070a4a9 2044
14571b4c
ZW		 2045 drm_connector_helper_add(connector, &intel_sdvo_connector_helper_funcs);
2046
2047 connector->interlace_allowed = 0;
2048 connector->doublescan_allowed = 0;
2049 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
2050
2051 drm_mode_connector_attach_encoder(connector, encoder);
2052 drm_sysfs_connector_add(connector);
2053}
6070a4a9 2054
fb7a46f3 2055static bool
ea5b213a 2056intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
fb7a46f3 2057{
ea5b213a 2058 struct drm_encoder *encoder = &intel_sdvo->base.enc;
14571b4c
ZW		 2059 struct drm_connector *connector;
2060 struct intel_connector *intel_connector;
615fb93f 2061 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2062
615fb93f
CW		 2063 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2064 if (!intel_sdvo_connector)
14571b4c
ZW		 2065 return false;
2066
14571b4c 2067 if (device == 0) {
ea5b213a 2068 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
615fb93f 2069 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
14571b4c 2070 } else if (device == 1) {
ea5b213a 2071 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
615fb93f 2072 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
14571b4c
ZW		 2073 }
2074
615fb93f 2075 intel_connector = &intel_sdvo_connector->base;
14571b4c 2076 connector = &intel_connector->base;
eb1f8e4f 2077 connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
14571b4c
ZW		 2078 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2079 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2080
ea5b213a
CW		 2081 if (intel_sdvo_get_supp_encode(intel_sdvo, &intel_sdvo->encode)
2082 && intel_sdvo_get_digital_encoding_mode(intel_sdvo, device)
2083 && intel_sdvo->is_hdmi) {
14571b4c 2084 /* enable hdmi encoding mode if supported */
ea5b213a
CW		 2085 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
2086 intel_sdvo_set_colorimetry(intel_sdvo,
14571b4c
ZW		 2087 SDVO_COLORIMETRY_RGB256);
2088 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
2089 }
ea5b213a
CW		 2090 intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2091 (1 << INTEL_ANALOG_CLONE_BIT));
14571b4c 2092
32aad86f 2093 intel_sdvo_connector_init(encoder, connector);
14571b4c
ZW		 2094
2095 return true;
2096}
2097
2098static bool
ea5b213a 2099intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
14571b4c 2100{
ea5b213a 2101 struct drm_encoder *encoder = &intel_sdvo->base.enc;
14571b4c
ZW		 2102 struct drm_connector *connector;
2103 struct intel_connector *intel_connector;
615fb93f 2104 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2105
615fb93f
CW		 2106 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2107 if (!intel_sdvo_connector)
2108 return false;
14571b4c 2109
615fb93f 2110 intel_connector = &intel_sdvo_connector->base;
14571b4c
ZW		 2111 connector = &intel_connector->base;
2112 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2113 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
14571b4c 2114
ea5b213a 2115 intel_sdvo->controlled_output |= type;
615fb93f 2116 intel_sdvo_connector->output_flag = type;
14571b4c 2117
ea5b213a
CW		 2118 intel_sdvo->is_tv = true;
2119 intel_sdvo->base.needs_tv_clock = true;
2120 intel_sdvo->base.clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
14571b4c 2121
32aad86f 2122 intel_sdvo_connector_init(encoder, connector);
14571b4c 2123
32aad86f
CW		 2124 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
2125 goto err;
14571b4c 2126
32aad86f
CW		 2127 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
2128 goto err;
14571b4c
ZW		 2129
2130 return true;
32aad86f
CW		 2131
2132err:
fcc8d672 2133 intel_sdvo_destroy_enhance_property(connector);
32aad86f
CW		 2134 kfree(intel_sdvo_connector);
2135 return false;
14571b4c
ZW		 2136}
2137
2138static bool
ea5b213a 2139intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2140{
ea5b213a 2141 struct drm_encoder *encoder = &intel_sdvo->base.enc;
14571b4c
ZW		 2142 struct drm_connector *connector;
2143 struct intel_connector *intel_connector;
615fb93f 2144 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2145
615fb93f
CW		 2146 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2147 if (!intel_sdvo_connector)
2148 return false;
14571b4c 2149
615fb93f 2150 intel_connector = &intel_sdvo_connector->base;
14571b4c 2151 connector = &intel_connector->base;
eb1f8e4f 2152 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
14571b4c
ZW		 2153 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2154 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
14571b4c
ZW		 2155
2156 if (device == 0) {
ea5b213a 2157 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
615fb93f 2158 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
14571b4c 2159 } else if (device == 1) {
ea5b213a 2160 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
615fb93f 2161 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
14571b4c
ZW		 2162 }
2163
ea5b213a
CW		 2164 intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2165 (1 << INTEL_ANALOG_CLONE_BIT));
14571b4c 2166
32aad86f 2167 intel_sdvo_connector_init(encoder, connector);
14571b4c
ZW		 2168 return true;
2169}
2170
2171static bool
ea5b213a 2172intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2173{
ea5b213a 2174 struct drm_encoder *encoder = &intel_sdvo->base.enc;
14571b4c
ZW		 2175 struct drm_connector *connector;
2176 struct intel_connector *intel_connector;
615fb93f 2177 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2178
615fb93f
CW		 2179 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2180 if (!intel_sdvo_connector)
2181 return false;
14571b4c 2182
615fb93f
CW		 2183 intel_connector = &intel_sdvo_connector->base;
2184 connector = &intel_connector->base;
14571b4c
ZW		 2185 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2186 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
14571b4c 2187
ea5b213a 2188 intel_sdvo->is_lvds = true;
14571b4c
ZW		 2189
2190 if (device == 0) {
ea5b213a 2191 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
615fb93f 2192 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
14571b4c 2193 } else if (device == 1) {
ea5b213a 2194 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
615fb93f 2195 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
14571b4c
ZW		 2196 }
2197
ea5b213a
CW		 2198 intel_sdvo->base.clone_mask = ((1 << INTEL_ANALOG_CLONE_BIT) |
2199 (1 << INTEL_SDVO_LVDS_CLONE_BIT));
14571b4c 2200
32aad86f
CW		 2201 intel_sdvo_connector_init(encoder, connector);
2202 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
2203 goto err;
2204
2205 return true;
2206
2207err:
fcc8d672 2208 intel_sdvo_destroy_enhance_property(connector);
32aad86f
CW		 2209 kfree(intel_sdvo_connector);
2210 return false;
14571b4c
ZW		 2211}
2212
2213static bool
ea5b213a 2214intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
14571b4c 2215{
ea5b213a
CW		 2216 intel_sdvo->is_tv = false;
2217 intel_sdvo->base.needs_tv_clock = false;
2218 intel_sdvo->is_lvds = false;
fb7a46f3 2219
14571b4c 2220 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
fb7a46f3 2221
14571b4c 2222 if (flags & SDVO_OUTPUT_TMDS0)
ea5b213a 2223 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
14571b4c
ZW		 2224 return false;
2225
2226 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
ea5b213a 2227 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
14571b4c
ZW		 2228 return false;
2229
2230 /* TV has no XXX1 function block */
a1f4b7ff 2231 if (flags & SDVO_OUTPUT_SVID0)
ea5b213a 2232 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
14571b4c
ZW		 2233 return false;
2234
2235 if (flags & SDVO_OUTPUT_CVBS0)
ea5b213a 2236 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
14571b4c 2237 return false;
fb7a46f3 2238
14571b4c 2239 if (flags & SDVO_OUTPUT_RGB0)
ea5b213a 2240 if (!intel_sdvo_analog_init(intel_sdvo, 0))
14571b4c
ZW		 2241 return false;
2242
2243 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
ea5b213a 2244 if (!intel_sdvo_analog_init(intel_sdvo, 1))
14571b4c
ZW		 2245 return false;
2246
2247 if (flags & SDVO_OUTPUT_LVDS0)
ea5b213a 2248 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
14571b4c
ZW		 2249 return false;
2250
2251 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
ea5b213a 2252 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
14571b4c 2253 return false;
fb7a46f3 2254
14571b4c 2255 if ((flags & SDVO_OUTPUT_MASK) == 0) {
fb7a46f3 2256 unsigned char bytes[2];
2257
ea5b213a
CW		 2258 intel_sdvo->controlled_output = 0;
2259 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
51c8b407 2260 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
ea5b213a 2261 SDVO_NAME(intel_sdvo),
51c8b407 2262 bytes[0], bytes[1]);
14571b4c 2263 return false;
fb7a46f3 2264 }
ea5b213a 2265 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1);
fb7a46f3 2266
14571b4c 2267 return true;
fb7a46f3 2268}
2269
32aad86f
CW		 2270static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2271 struct intel_sdvo_connector *intel_sdvo_connector,
2272 int type)
ce6feabd 2273{
32aad86f 2274 struct drm_device *dev = intel_sdvo->base.enc.dev;
ce6feabd
ZY		 2275 struct intel_sdvo_tv_format format;
2276 uint32_t format_map, i;
ce6feabd 2277
32aad86f
CW		 2278 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2279 return false;
ce6feabd 2280
32aad86f
CW		 2281 if (!intel_sdvo_get_value(intel_sdvo,
2282 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2283 &format, sizeof(format)))
2284 return false;
ce6feabd 2285
32aad86f 2286 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
ce6feabd
ZY		 2287
2288 if (format_map == 0)
32aad86f 2289 return false;
ce6feabd 2290
615fb93f 2291 intel_sdvo_connector->format_supported_num = 0;
ce6feabd 2292 for (i = 0 ; i < TV_FORMAT_NUM; i++)
40039750
CW		 2293 if (format_map & (1 << i))
2294 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
ce6feabd
ZY		 2295
2296
c5521706 2297 intel_sdvo_connector->tv_format =
32aad86f
CW		 2298 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2299 "mode", intel_sdvo_connector->format_supported_num);
c5521706 2300 if (!intel_sdvo_connector->tv_format)
fcc8d672 2301 return false;
ce6feabd 2302
615fb93f 2303 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
ce6feabd 2304 drm_property_add_enum(
c5521706 2305 intel_sdvo_connector->tv_format, i,
40039750 2306 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
ce6feabd 2307
40039750 2308 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
32aad86f 2309 drm_connector_attach_property(&intel_sdvo_connector->base.base,
c5521706 2310 intel_sdvo_connector->tv_format, 0);
32aad86f 2311 return true;
ce6feabd
ZY		 2312
2313}
2314
c5521706
CW		 2315#define ENHANCEMENT(name, NAME) do { \
2316 if (enhancements.name) { \
2317 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2318 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2319 return false; \
2320 intel_sdvo_connector->max_##name = data_value[0]; \
2321 intel_sdvo_connector->cur_##name = response; \
2322 intel_sdvo_connector->name = \
2323 drm_property_create(dev, DRM_MODE_PROP_RANGE, #name, 2); \
2324 if (!intel_sdvo_connector->name) return false; \
2325 intel_sdvo_connector->name->values[0] = 0; \
2326 intel_sdvo_connector->name->values[1] = data_value[0]; \
2327 drm_connector_attach_property(connector, \
2328 intel_sdvo_connector->name, \
2329 intel_sdvo_connector->cur_##name); \
2330 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2331 data_value[0], data_value[1], response); \
2332 } \
2333} while(0)
2334
2335static bool
2336intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
2337 struct intel_sdvo_connector *intel_sdvo_connector,
2338 struct intel_sdvo_enhancements_reply enhancements)
b9219c5e 2339{
32aad86f
CW		 2340 struct drm_device *dev = intel_sdvo->base.enc.dev;
2341 struct drm_connector *connector = &intel_sdvo_connector->base.base;
b9219c5e
ZY		 2342 uint16_t response, data_value[2];
2343
c5521706
CW		 2344 /* when horizontal overscan is supported, Add the left/right property */
2345 if (enhancements.overscan_h) {
2346 if (!intel_sdvo_get_value(intel_sdvo,
2347 SDVO_CMD_GET_MAX_OVERSCAN_H,
2348 &data_value, 4))
2349 return false;
32aad86f 2350
c5521706
CW		 2351 if (!intel_sdvo_get_value(intel_sdvo,
2352 SDVO_CMD_GET_OVERSCAN_H,
2353 &response, 2))
2354 return false;
fcc8d672 2355
c5521706
CW		 2356 intel_sdvo_connector->max_hscan = data_value[0];
2357 intel_sdvo_connector->left_margin = data_value[0] - response;
2358 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
2359 intel_sdvo_connector->left =
2360 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2361 "left_margin", 2);
2362 if (!intel_sdvo_connector->left)
2363 return false;
fcc8d672 2364
c5521706
CW		 2365 intel_sdvo_connector->left->values[0] = 0;
2366 intel_sdvo_connector->left->values[1] = data_value[0];
2367 drm_connector_attach_property(connector,
2368 intel_sdvo_connector->left,
2369 intel_sdvo_connector->left_margin);
fcc8d672 2370
c5521706
CW		 2371 intel_sdvo_connector->right =
2372 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2373 "right_margin", 2);
2374 if (!intel_sdvo_connector->right)
2375 return false;
32aad86f 2376
c5521706
CW		 2377 intel_sdvo_connector->right->values[0] = 0;
2378 intel_sdvo_connector->right->values[1] = data_value[0];
2379 drm_connector_attach_property(connector,
2380 intel_sdvo_connector->right,
2381 intel_sdvo_connector->right_margin);
2382 DRM_DEBUG_KMS("h_overscan: max %d, "
2383 "default %d, current %d\n",
2384 data_value[0], data_value[1], response);
2385 }
32aad86f 2386
c5521706
CW		 2387 if (enhancements.overscan_v) {
2388 if (!intel_sdvo_get_value(intel_sdvo,
2389 SDVO_CMD_GET_MAX_OVERSCAN_V,
2390 &data_value, 4))
2391 return false;
fcc8d672 2392
c5521706
CW		 2393 if (!intel_sdvo_get_value(intel_sdvo,
2394 SDVO_CMD_GET_OVERSCAN_V,
2395 &response, 2))
2396 return false;
32aad86f 2397
c5521706
CW		 2398 intel_sdvo_connector->max_vscan = data_value[0];
2399 intel_sdvo_connector->top_margin = data_value[0] - response;
2400 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
2401 intel_sdvo_connector->top =
2402 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2403 "top_margin", 2);
2404 if (!intel_sdvo_connector->top)
2405 return false;
32aad86f 2406
c5521706
CW		 2407 intel_sdvo_connector->top->values[0] = 0;
2408 intel_sdvo_connector->top->values[1] = data_value[0];
2409 drm_connector_attach_property(connector,
2410 intel_sdvo_connector->top,
2411 intel_sdvo_connector->top_margin);
fcc8d672 2412
c5521706
CW		 2413 intel_sdvo_connector->bottom =
2414 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2415 "bottom_margin", 2);
2416 if (!intel_sdvo_connector->bottom)
2417 return false;
32aad86f 2418
c5521706
CW		 2419 intel_sdvo_connector->bottom->values[0] = 0;
2420 intel_sdvo_connector->bottom->values[1] = data_value[0];
2421 drm_connector_attach_property(connector,
2422 intel_sdvo_connector->bottom,
2423 intel_sdvo_connector->bottom_margin);
2424 DRM_DEBUG_KMS("v_overscan: max %d, "
2425 "default %d, current %d\n",
2426 data_value[0], data_value[1], response);
2427 }
32aad86f 2428
c5521706
CW		 2429 ENHANCEMENT(hpos, HPOS);
2430 ENHANCEMENT(vpos, VPOS);
2431 ENHANCEMENT(saturation, SATURATION);
2432 ENHANCEMENT(contrast, CONTRAST);
2433 ENHANCEMENT(hue, HUE);
2434 ENHANCEMENT(sharpness, SHARPNESS);
2435 ENHANCEMENT(brightness, BRIGHTNESS);
2436 ENHANCEMENT(flicker_filter, FLICKER_FILTER);
2437 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
2438 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
2439 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
2440 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
fcc8d672 2441
c5521706
CW		 2442 return true;
2443}
32aad86f 2444
c5521706
CW		 2445static bool
2446intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
2447 struct intel_sdvo_connector *intel_sdvo_connector,
2448 struct intel_sdvo_enhancements_reply enhancements)
2449{
2450 struct drm_device *dev = intel_sdvo->base.enc.dev;
2451 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2452 uint16_t response, data_value[2];
32aad86f 2453
c5521706 2454 ENHANCEMENT(brightness, BRIGHTNESS);
fcc8d672 2455
c5521706
CW		 2456 return true;
2457}
2458#undef ENHANCEMENT
32aad86f 2459
c5521706
CW		 2460static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2461 struct intel_sdvo_connector *intel_sdvo_connector)
2462{
2463 union {
2464 struct intel_sdvo_enhancements_reply reply;
2465 uint16_t response;
2466 } enhancements;
32aad86f 2467
c5521706
CW		 2468 if (!intel_sdvo_get_value(intel_sdvo,
2469 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2470 &enhancements, sizeof(enhancements)))
2471 return false;
fcc8d672 2472
c5521706
CW		 2473 if (enhancements.response == 0) {
2474 DRM_DEBUG_KMS("No enhancement is supported\n");
2475 return true;
b9219c5e 2476 }
32aad86f 2477
c5521706
CW		 2478 if (IS_TV(intel_sdvo_connector))
2479 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2480 else if(IS_LVDS(intel_sdvo_connector))
2481 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2482 else
2483 return true;
fcc8d672 2484
b9219c5e
ZY		 2485}
2486
c751ce4f 2487bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg)
79e53945 2488{
b01f2c3a 2489 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 2490 struct intel_encoder *intel_encoder;
ea5b213a 2491 struct intel_sdvo *intel_sdvo;
79e53945
JB		 2492 u8 ch[0x40];
2493 int i;
461ed3ca 2494 u32 i2c_reg, ddc_reg, analog_ddc_reg;
79e53945 2495
ea5b213a
CW		 2496 intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
2497 if (!intel_sdvo)
7d57382e 2498 return false;
79e53945 2499
ea5b213a 2500 intel_sdvo->sdvo_reg = sdvo_reg;
308cd3a2 2501
ea5b213a 2502 intel_encoder = &intel_sdvo->base;
21d40d37 2503 intel_encoder->type = INTEL_OUTPUT_SDVO;
79e53945 2504
461ed3ca
ZY		 2505 if (HAS_PCH_SPLIT(dev)) {
2506 i2c_reg = PCH_GPIOE;
2507 ddc_reg = PCH_GPIOE;
2508 analog_ddc_reg = PCH_GPIOA;
2509 } else {
2510 i2c_reg = GPIOE;
2511 ddc_reg = GPIOE;
2512 analog_ddc_reg = GPIOA;
2513 }
2514
79e53945 2515 /* setup the DDC bus. */
461ed3ca
ZY		 2516 if (IS_SDVOB(sdvo_reg))
2517 intel_encoder->i2c_bus = intel_i2c_create(dev, i2c_reg, "SDVOCTRL_E for SDVOB");
308cd3a2 2518 else
461ed3ca 2519 intel_encoder->i2c_bus = intel_i2c_create(dev, i2c_reg, "SDVOCTRL_E for SDVOC");
308cd3a2 2520
21d40d37 2521 if (!intel_encoder->i2c_bus)
ad5b2a6d 2522 goto err_inteloutput;
79e53945 2523
ea5b213a 2524 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, sdvo_reg);
79e53945 2525
308cd3a2 2526 /* Save the bit-banging i2c functionality for use by the DDC wrapper */
21d40d37 2527 intel_sdvo_i2c_bit_algo.functionality = intel_encoder->i2c_bus->algo->functionality;
79e53945 2528
79e53945
JB		 2529 /* Read the regs to test if we can talk to the device */
2530 for (i = 0; i < 0x40; i++) {
ea5b213a 2531 if (!intel_sdvo_read_byte(intel_sdvo, i, &ch[i])) {
8a4c47f3 2532 DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n",
461ed3ca 2533 IS_SDVOB(sdvo_reg) ? 'B' : 'C');
79e53945
JB		 2534 goto err_i2c;
2535 }
2536 }
2537
619ac3b7 2538 /* setup the DDC bus. */
461ed3ca
ZY		 2539 if (IS_SDVOB(sdvo_reg)) {
2540 intel_encoder->ddc_bus = intel_i2c_create(dev, ddc_reg, "SDVOB DDC BUS");
ea5b213a 2541 intel_sdvo->analog_ddc_bus = intel_i2c_create(dev, analog_ddc_reg,
57cdaf90 2542 "SDVOB/VGA DDC BUS");
b01f2c3a 2543 dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS;
57cdaf90 2544 } else {
461ed3ca 2545 intel_encoder->ddc_bus = intel_i2c_create(dev, ddc_reg, "SDVOC DDC BUS");
ea5b213a 2546 intel_sdvo->analog_ddc_bus = intel_i2c_create(dev, analog_ddc_reg,
57cdaf90 2547 "SDVOC/VGA DDC BUS");
b01f2c3a 2548 dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS;
57cdaf90 2549 }
32aad86f 2550 if (intel_encoder->ddc_bus == NULL || intel_sdvo->analog_ddc_bus == NULL)
619ac3b7
ML		 2551 goto err_i2c;
2552
308cd3a2 2553 /* Wrap with our custom algo which switches to DDC mode */
21d40d37 2554 intel_encoder->ddc_bus->algo = &intel_sdvo_i2c_bit_algo;
619ac3b7 2555
14571b4c
ZW		 2556 /* encoder type will be decided later */
2557 drm_encoder_init(dev, &intel_encoder->enc, &intel_sdvo_enc_funcs, 0);
2558 drm_encoder_helper_add(&intel_encoder->enc, &intel_sdvo_helper_funcs);
2559
af901ca1 2560 /* In default case sdvo lvds is false */
32aad86f
CW		 2561 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
2562 goto err_enc;
79e53945 2563
ea5b213a
CW		 2564 if (intel_sdvo_output_setup(intel_sdvo,
2565 intel_sdvo->caps.output_flags) != true) {
51c8b407 2566 DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n",
461ed3ca 2567 IS_SDVOB(sdvo_reg) ? 'B' : 'C');
32aad86f 2568 goto err_enc;
79e53945
JB		 2569 }
2570
ea5b213a 2571 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
e2f0ba97 2572
79e53945 2573 /* Set the input timing to the screen. Assume always input 0. */
32aad86f
CW		 2574 if (!intel_sdvo_set_target_input(intel_sdvo))
2575 goto err_enc;
79e53945 2576
32aad86f
CW		 2577 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
2578 &intel_sdvo->pixel_clock_min,
2579 &intel_sdvo->pixel_clock_max))
2580 goto err_enc;
79e53945 2581
8a4c47f3 2582 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
342dc382 2583 "clock range %dMHz - %dMHz, "
2584 "input 1: %c, input 2: %c, "
2585 "output 1: %c, output 2: %c\n",
ea5b213a
CW		 2586 SDVO_NAME(intel_sdvo),
2587 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
2588 intel_sdvo->caps.device_rev_id,
2589 intel_sdvo->pixel_clock_min / 1000,
2590 intel_sdvo->pixel_clock_max / 1000,
2591 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2592 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
342dc382 2593 /* check currently supported outputs */
ea5b213a 2594 intel_sdvo->caps.output_flags &
79e53945 2595 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
ea5b213a 2596 intel_sdvo->caps.output_flags &
79e53945 2597 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
7d57382e 2598 return true;
79e53945 2599
32aad86f
CW		 2600err_enc:
2601 drm_encoder_cleanup(&intel_encoder->enc);
79e53945 2602err_i2c:
ea5b213a
CW		 2603 if (intel_sdvo->analog_ddc_bus != NULL)
2604 intel_i2c_destroy(intel_sdvo->analog_ddc_bus);
21d40d37
EA		 2605 if (intel_encoder->ddc_bus != NULL)
2606 intel_i2c_destroy(intel_encoder->ddc_bus);
2607 if (intel_encoder->i2c_bus != NULL)
2608 intel_i2c_destroy(intel_encoder->i2c_bus);
ad5b2a6d 2609err_inteloutput:
ea5b213a 2610 kfree(intel_sdvo);
79e53945 2611
7d57382e 2612 return false;
79e53945 2613}
Ubuntu Disco kernel mirror for Proxmox VE and PMG