]>
Commit | Line | Data |
---|---|---|
b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
7974dd1b BS |
2 | #ifndef __NVKM_DEVICE_TEGRA_H__ |
3 | #define __NVKM_DEVICE_TEGRA_H__ | |
4 | #include <core/device.h> | |
43a70661 | 5 | #include <core/mm.h> |
7974dd1b BS |
6 | |
7 | struct nvkm_device_tegra { | |
e396ecd1 | 8 | const struct nvkm_device_tegra_func *func; |
7974dd1b BS |
9 | struct nvkm_device device; |
10 | struct platform_device *pdev; | |
2b700825 | 11 | int irq; |
43a70661 BS |
12 | |
13 | struct reset_control *rst; | |
14 | struct clk *clk; | |
34440ed6 | 15 | struct clk *clk_ref; |
43a70661 BS |
16 | struct clk *clk_pwr; |
17 | ||
18 | struct regulator *vdd; | |
19 | ||
20 | struct { | |
21 | /* | |
22 | * Protects accesses to mm from subsystems | |
23 | */ | |
24 | struct mutex mutex; | |
25 | ||
26 | struct nvkm_mm mm; | |
27 | struct iommu_domain *domain; | |
28 | unsigned long pgshift; | |
29 | } iommu; | |
30 | ||
31 | int gpu_speedo; | |
d2680907 | 32 | int gpu_speedo_id; |
7974dd1b BS |
33 | }; |
34 | ||
e396ecd1 AC |
35 | struct nvkm_device_tegra_func { |
36 | /* | |
37 | * If an IOMMU is used, indicates which address bit will trigger a | |
38 | * IOMMU translation when set (when this bit is not set, IOMMU is | |
39 | * bypassed). A value of 0 means an IOMMU is never used. | |
40 | */ | |
41 | u8 iommu_bit; | |
34440ed6 AC |
42 | /* |
43 | * Whether the chip requires a reference clock | |
44 | */ | |
45 | bool require_ref_clk; | |
e6e1817a AC |
46 | /* |
47 | * Whether the chip requires the VDD regulator | |
48 | */ | |
49 | bool require_vdd; | |
e396ecd1 AC |
50 | }; |
51 | ||
52 | int nvkm_device_tegra_new(const struct nvkm_device_tegra_func *, | |
53 | struct platform_device *, | |
7974dd1b BS |
54 | const char *cfg, const char *dbg, |
55 | bool detect, bool mmio, u64 subdev_mask, | |
56 | struct nvkm_device **); | |
57 | #endif |