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Merge tag 'drm-misc-next-2018-06-21' of git://anongit.freedesktop.org/drm/drm-misc...
[mirror_ubuntu-disco-kernel.git] / drivers / gpu / drm / panel / panel-simple.c
CommitLineData
280921de
TR		 1/*
2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24#include <linux/backlight.h>
cfdf0549 25#include <linux/gpio/consumer.h>
280921de 26#include <linux/module.h>
280921de
TR		 27#include <linux/of_platform.h>
28#include <linux/platform_device.h>
29#include <linux/regulator/consumer.h>
30
31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
210fcd9d 33#include <drm/drm_mipi_dsi.h>
280921de
TR		 34#include <drm/drm_panel.h>
35
a5d3e625
PZ		 36#include <video/display_timing.h>
37#include <video/videomode.h>
38
280921de
TR		 39struct panel_desc {
40 const struct drm_display_mode *modes;
41 unsigned int num_modes;
a5d3e625
PZ		 42 const struct display_timing *timings;
43 unsigned int num_timings;
280921de 44
0208d511
SM		 45 unsigned int bpc;
46
85533e3b
UÖ		 47 /**
48 * @width: width (in millimeters) of the panel's active display area
49 * @height: height (in millimeters) of the panel's active display area
50 */
280921de
TR		 51 struct {
52 unsigned int width;
53 unsigned int height;
54 } size;
f673c37e
AK		 55
56 /**
57 * @prepare: the time (in milliseconds) that it takes for the panel to
58 * become ready and start receiving video data
59 * @enable: the time (in milliseconds) that it takes for the panel to
60 * display the first valid frame after starting to receive
61 * video data
62 * @disable: the time (in milliseconds) that it takes for the panel to
63 * turn the display off (no content is visible)
64 * @unprepare: the time (in milliseconds) that it takes for the panel
65 * to power itself down completely
66 */
67 struct {
68 unsigned int prepare;
69 unsigned int enable;
70 unsigned int disable;
71 unsigned int unprepare;
72 } delay;
795f7ab3
BB		 73
74 u32 bus_format;
f0aa0838 75 u32 bus_flags;
280921de
TR		 76};
77
280921de
TR		 78struct panel_simple {
79 struct drm_panel base;
613a633e 80 bool prepared;
280921de
TR		 81 bool enabled;
82
83 const struct panel_desc *desc;
84
85 struct backlight_device *backlight;
86 struct regulator *supply;
87 struct i2c_adapter *ddc;
88
cfdf0549 89 struct gpio_desc *enable_gpio;
280921de
TR		 90};
91
92static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
93{
94 return container_of(panel, struct panel_simple, base);
95}
96
97static int panel_simple_get_fixed_modes(struct panel_simple *panel)
98{
99 struct drm_connector *connector = panel->base.connector;
100 struct drm_device *drm = panel->base.drm;
101 struct drm_display_mode *mode;
102 unsigned int i, num = 0;
103
104 if (!panel->desc)
105 return 0;
106
a5d3e625
PZ		 107 for (i = 0; i < panel->desc->num_timings; i++) {
108 const struct display_timing *dt = &panel->desc->timings[i];
109 struct videomode vm;
110
111 videomode_from_timing(dt, &vm);
112 mode = drm_mode_create(drm);
113 if (!mode) {
114 dev_err(drm->dev, "failed to add mode %ux%u\n",
115 dt->hactive.typ, dt->vactive.typ);
116 continue;
117 }
118
119 drm_display_mode_from_videomode(&vm, mode);
cda55372
BB		 120
121 mode->type |= DRM_MODE_TYPE_DRIVER;
122
230c5b44 123 if (panel->desc->num_timings == 1)
cda55372
BB		 124 mode->type |= DRM_MODE_TYPE_PREFERRED;
125
a5d3e625
PZ		 126 drm_mode_probed_add(connector, mode);
127 num++;
128 }
129
280921de
TR		 130 for (i = 0; i < panel->desc->num_modes; i++) {
131 const struct drm_display_mode *m = &panel->desc->modes[i];
132
133 mode = drm_mode_duplicate(drm, m);
134 if (!mode) {
135 dev_err(drm->dev, "failed to add mode %ux%u@%u\n",
136 m->hdisplay, m->vdisplay, m->vrefresh);
137 continue;
138 }
139
cda55372
BB		 140 mode->type |= DRM_MODE_TYPE_DRIVER;
141
142 if (panel->desc->num_modes == 1)
143 mode->type |= DRM_MODE_TYPE_PREFERRED;
144
280921de
TR		 145 drm_mode_set_name(mode);
146
147 drm_mode_probed_add(connector, mode);
148 num++;
149 }
150
0208d511 151 connector->display_info.bpc = panel->desc->bpc;
280921de
TR		 152 connector->display_info.width_mm = panel->desc->size.width;
153 connector->display_info.height_mm = panel->desc->size.height;
795f7ab3
BB		 154 if (panel->desc->bus_format)
155 drm_display_info_set_bus_formats(&connector->display_info,
156 &panel->desc->bus_format, 1);
f0aa0838 157 connector->display_info.bus_flags = panel->desc->bus_flags;
280921de
TR		 158
159 return num;
160}
161
162static int panel_simple_disable(struct drm_panel *panel)
163{
164 struct panel_simple *p = to_panel_simple(panel);
165
166 if (!p->enabled)
167 return 0;
168
169 if (p->backlight) {
170 p->backlight->props.power = FB_BLANK_POWERDOWN;
e4aa3428 171 p->backlight->props.state |= BL_CORE_FBBLANK;
280921de
TR		 172 backlight_update_status(p->backlight);
173 }
174
f673c37e
AK		 175 if (p->desc->delay.disable)
176 msleep(p->desc->delay.disable);
177
280921de
TR		 178 p->enabled = false;
179
180 return 0;
181}
182
c0e1d170
AK		 183static int panel_simple_unprepare(struct drm_panel *panel)
184{
613a633e
AK		 185 struct panel_simple *p = to_panel_simple(panel);
186
187 if (!p->prepared)
188 return 0;
189
756b918d 190 gpiod_set_value_cansleep(p->enable_gpio, 0);
613a633e
AK		 191
192 regulator_disable(p->supply);
193
f673c37e
AK		 194 if (p->desc->delay.unprepare)
195 msleep(p->desc->delay.unprepare);
196
613a633e 197 p->prepared = false;
c0e1d170 198
c0e1d170
AK		 199 return 0;
200}
201
613a633e 202static int panel_simple_prepare(struct drm_panel *panel)
280921de
TR		 203{
204 struct panel_simple *p = to_panel_simple(panel);
205 int err;
206
613a633e 207 if (p->prepared)
280921de
TR		 208 return 0;
209
210 err = regulator_enable(p->supply);
211 if (err < 0) {
212 dev_err(panel->dev, "failed to enable supply: %d\n", err);
213 return err;
214 }
215
756b918d 216 gpiod_set_value_cansleep(p->enable_gpio, 1);
280921de 217
f673c37e
AK		 218 if (p->desc->delay.prepare)
219 msleep(p->desc->delay.prepare);
220
613a633e
AK		 221 p->prepared = true;
222
223 return 0;
224}
225
226static int panel_simple_enable(struct drm_panel *panel)
227{
228 struct panel_simple *p = to_panel_simple(panel);
229
230 if (p->enabled)
231 return 0;
232
f673c37e
AK		 233 if (p->desc->delay.enable)
234 msleep(p->desc->delay.enable);
235
280921de 236 if (p->backlight) {
e4aa3428 237 p->backlight->props.state &= ~BL_CORE_FBBLANK;
280921de
TR		 238 p->backlight->props.power = FB_BLANK_UNBLANK;
239 backlight_update_status(p->backlight);
240 }
241
242 p->enabled = true;
243
244 return 0;
245}
246
247static int panel_simple_get_modes(struct drm_panel *panel)
248{
249 struct panel_simple *p = to_panel_simple(panel);
250 int num = 0;
251
252 /* probe EDID if a DDC bus is available */
253 if (p->ddc) {
254 struct edid *edid = drm_get_edid(panel->connector, p->ddc);
70bf6878 255 drm_mode_connector_update_edid_property(panel->connector, edid);
280921de
TR		 256 if (edid) {
257 num += drm_add_edid_modes(panel->connector, edid);
258 kfree(edid);
259 }
260 }
261
262 /* add hard-coded panel modes */
263 num += panel_simple_get_fixed_modes(p);
264
265 return num;
266}
267
a5d3e625
PZ		 268static int panel_simple_get_timings(struct drm_panel *panel,
269 unsigned int num_timings,
270 struct display_timing *timings)
271{
272 struct panel_simple *p = to_panel_simple(panel);
273 unsigned int i;
274
275 if (p->desc->num_timings < num_timings)
276 num_timings = p->desc->num_timings;
277
278 if (timings)
279 for (i = 0; i < num_timings; i++)
280 timings[i] = p->desc->timings[i];
281
282 return p->desc->num_timings;
283}
284
280921de
TR		 285static const struct drm_panel_funcs panel_simple_funcs = {
286 .disable = panel_simple_disable,
c0e1d170
AK		 287 .unprepare = panel_simple_unprepare,
288 .prepare = panel_simple_prepare,
280921de
TR		 289 .enable = panel_simple_enable,
290 .get_modes = panel_simple_get_modes,
a5d3e625 291 .get_timings = panel_simple_get_timings,
280921de
TR		 292};
293
294static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
295{
296 struct device_node *backlight, *ddc;
297 struct panel_simple *panel;
280921de
TR		 298 int err;
299
300 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
301 if (!panel)
302 return -ENOMEM;
303
304 panel->enabled = false;
613a633e 305 panel->prepared = false;
280921de
TR		 306 panel->desc = desc;
307
308 panel->supply = devm_regulator_get(dev, "power");
309 if (IS_ERR(panel->supply))
310 return PTR_ERR(panel->supply);
311
a61400d8
AC		 312 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
313 GPIOD_OUT_LOW);
cfdf0549
AC		 314 if (IS_ERR(panel->enable_gpio)) {
315 err = PTR_ERR(panel->enable_gpio);
b8e93807
FE		 316 if (err != -EPROBE_DEFER)
317 dev_err(dev, "failed to request GPIO: %d\n", err);
9746c619
AC		 318 return err;
319 }
280921de 320
280921de
TR		 321 backlight = of_parse_phandle(dev->of_node, "backlight", 0);
322 if (backlight) {
323 panel->backlight = of_find_backlight_by_node(backlight);
324 of_node_put(backlight);
325
cfdf0549
AC		 326 if (!panel->backlight)
327 return -EPROBE_DEFER;
280921de
TR		 328 }
329
330 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
331 if (ddc) {
332 panel->ddc = of_find_i2c_adapter_by_node(ddc);
333 of_node_put(ddc);
334
335 if (!panel->ddc) {
336 err = -EPROBE_DEFER;
337 goto free_backlight;
338 }
339 }
340
341 drm_panel_init(&panel->base);
342 panel->base.dev = dev;
343 panel->base.funcs = &panel_simple_funcs;
344
345 err = drm_panel_add(&panel->base);
346 if (err < 0)
347 goto free_ddc;
348
349 dev_set_drvdata(dev, panel);
350
351 return 0;
352
353free_ddc:
354 if (panel->ddc)
355 put_device(&panel->ddc->dev);
356free_backlight:
357 if (panel->backlight)
358 put_device(&panel->backlight->dev);
280921de
TR		 359
360 return err;
361}
362
363static int panel_simple_remove(struct device *dev)
364{
365 struct panel_simple *panel = dev_get_drvdata(dev);
366
280921de
TR		 367 drm_panel_remove(&panel->base);
368
369 panel_simple_disable(&panel->base);
f3621a8e 370 panel_simple_unprepare(&panel->base);
280921de
TR		 371
372 if (panel->ddc)
373 put_device(&panel->ddc->dev);
374
375 if (panel->backlight)
376 put_device(&panel->backlight->dev);
377
280921de
TR		 378 return 0;
379}
380
d02fd93e
TR		 381static void panel_simple_shutdown(struct device *dev)
382{
383 struct panel_simple *panel = dev_get_drvdata(dev);
384
385 panel_simple_disable(&panel->base);
f3621a8e 386 panel_simple_unprepare(&panel->base);
d02fd93e
TR		 387}
388
966fea78
YF		 389static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
390 .clock = 9000,
391 .hdisplay = 480,
392 .hsync_start = 480 + 2,
393 .hsync_end = 480 + 2 + 41,
394 .htotal = 480 + 2 + 41 + 2,
395 .vdisplay = 272,
396 .vsync_start = 272 + 2,
397 .vsync_end = 272 + 2 + 10,
398 .vtotal = 272 + 2 + 10 + 2,
399 .vrefresh = 60,
400 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
401};
402
403static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
404 .modes = &ampire_am_480272h3tmqw_t01h_mode,
405 .num_modes = 1,
406 .bpc = 8,
407 .size = {
408 .width = 105,
409 .height = 67,
410 },
411 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
412};
413
1c550fa1
PZ		 414static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
415 .clock = 33333,
416 .hdisplay = 800,
417 .hsync_start = 800 + 0,
418 .hsync_end = 800 + 0 + 255,
419 .htotal = 800 + 0 + 255 + 0,
420 .vdisplay = 480,
421 .vsync_start = 480 + 2,
422 .vsync_end = 480 + 2 + 45,
423 .vtotal = 480 + 2 + 45 + 0,
424 .vrefresh = 60,
425 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
426};
427
428static const struct panel_desc ampire_am800480r3tmqwa1h = {
429 .modes = &ampire_am800480r3tmqwa1h_mode,
430 .num_modes = 1,
431 .bpc = 6,
432 .size = {
433 .width = 152,
434 .height = 91,
435 },
436 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
437};
438
280921de
TR		 439static const struct drm_display_mode auo_b101aw03_mode = {
440 .clock = 51450,
441 .hdisplay = 1024,
442 .hsync_start = 1024 + 156,
443 .hsync_end = 1024 + 156 + 8,
444 .htotal = 1024 + 156 + 8 + 156,
445 .vdisplay = 600,
446 .vsync_start = 600 + 16,
447 .vsync_end = 600 + 16 + 6,
448 .vtotal = 600 + 16 + 6 + 16,
449 .vrefresh = 60,
450};
451
452static const struct panel_desc auo_b101aw03 = {
453 .modes = &auo_b101aw03_mode,
454 .num_modes = 1,
0208d511 455 .bpc = 6,
280921de
TR		 456 .size = {
457 .width = 223,
458 .height = 125,
459 },
460};
461
a531bc3d
HL		 462static const struct drm_display_mode auo_b101ean01_mode = {
463 .clock = 72500,
464 .hdisplay = 1280,
465 .hsync_start = 1280 + 119,
466 .hsync_end = 1280 + 119 + 32,
467 .htotal = 1280 + 119 + 32 + 21,
468 .vdisplay = 800,
469 .vsync_start = 800 + 4,
470 .vsync_end = 800 + 4 + 20,
471 .vtotal = 800 + 4 + 20 + 8,
472 .vrefresh = 60,
473};
474
475static const struct panel_desc auo_b101ean01 = {
476 .modes = &auo_b101ean01_mode,
477 .num_modes = 1,
478 .bpc = 6,
479 .size = {
480 .width = 217,
481 .height = 136,
482 },
483};
484
dac746e0
RC		 485static const struct drm_display_mode auo_b101xtn01_mode = {
486 .clock = 72000,
487 .hdisplay = 1366,
488 .hsync_start = 1366 + 20,
489 .hsync_end = 1366 + 20 + 70,
490 .htotal = 1366 + 20 + 70,
491 .vdisplay = 768,
492 .vsync_start = 768 + 14,
493 .vsync_end = 768 + 14 + 42,
494 .vtotal = 768 + 14 + 42,
495 .vrefresh = 60,
496 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
497};
498
499static const struct panel_desc auo_b101xtn01 = {
500 .modes = &auo_b101xtn01_mode,
501 .num_modes = 1,
502 .bpc = 6,
503 .size = {
504 .width = 223,
505 .height = 125,
506 },
507};
508
e35e305e
AK		 509static const struct drm_display_mode auo_b116xw03_mode = {
510 .clock = 70589,
511 .hdisplay = 1366,
512 .hsync_start = 1366 + 40,
513 .hsync_end = 1366 + 40 + 40,
514 .htotal = 1366 + 40 + 40 + 32,
515 .vdisplay = 768,
516 .vsync_start = 768 + 10,
517 .vsync_end = 768 + 10 + 12,
518 .vtotal = 768 + 10 + 12 + 6,
519 .vrefresh = 60,
520};
521
522static const struct panel_desc auo_b116xw03 = {
523 .modes = &auo_b116xw03_mode,
524 .num_modes = 1,
525 .bpc = 6,
526 .size = {
527 .width = 256,
528 .height = 144,
529 },
530};
531
a333f7ad
SM		 532static const struct drm_display_mode auo_b133xtn01_mode = {
533 .clock = 69500,
534 .hdisplay = 1366,
535 .hsync_start = 1366 + 48,
536 .hsync_end = 1366 + 48 + 32,
537 .htotal = 1366 + 48 + 32 + 20,
538 .vdisplay = 768,
539 .vsync_start = 768 + 3,
540 .vsync_end = 768 + 3 + 6,
541 .vtotal = 768 + 3 + 6 + 13,
542 .vrefresh = 60,
543};
544
545static const struct panel_desc auo_b133xtn01 = {
546 .modes = &auo_b133xtn01_mode,
547 .num_modes = 1,
0208d511 548 .bpc = 6,
a333f7ad
SM		 549 .size = {
550 .width = 293,
551 .height = 165,
552 },
553};
554
3e51d609
AK		 555static const struct drm_display_mode auo_b133htn01_mode = {
556 .clock = 150660,
557 .hdisplay = 1920,
558 .hsync_start = 1920 + 172,
559 .hsync_end = 1920 + 172 + 80,
560 .htotal = 1920 + 172 + 80 + 60,
561 .vdisplay = 1080,
562 .vsync_start = 1080 + 25,
563 .vsync_end = 1080 + 25 + 10,
564 .vtotal = 1080 + 25 + 10 + 10,
565 .vrefresh = 60,
566};
567
568static const struct panel_desc auo_b133htn01 = {
569 .modes = &auo_b133htn01_mode,
570 .num_modes = 1,
d7a839cd 571 .bpc = 6,
3e51d609
AK		 572 .size = {
573 .width = 293,
574 .height = 165,
575 },
576 .delay = {
577 .prepare = 105,
578 .enable = 20,
579 .unprepare = 50,
580 },
581};
582
bccfaffb
LM		 583static const struct display_timing auo_g070vvn01_timings = {
584 .pixelclock = { 33300000, 34209000, 45000000 },
585 .hactive = { 800, 800, 800 },
586 .hfront_porch = { 20, 40, 200 },
587 .hback_porch = { 87, 40, 1 },
588 .hsync_len = { 1, 48, 87 },
589 .vactive = { 480, 480, 480 },
590 .vfront_porch = { 5, 13, 200 },
591 .vback_porch = { 31, 31, 29 },
592 .vsync_len = { 1, 1, 3 },
593};
594
595static const struct panel_desc auo_g070vvn01 = {
596 .timings = &auo_g070vvn01_timings,
597 .num_timings = 1,
598 .bpc = 8,
599 .size = {
600 .width = 152,
601 .height = 91,
602 },
603 .delay = {
604 .prepare = 200,
605 .enable = 50,
606 .disable = 50,
607 .unprepare = 1000,
608 },
609};
610
4451c287
CF		 611static const struct drm_display_mode auo_g104sn02_mode = {
612 .clock = 40000,
613 .hdisplay = 800,
614 .hsync_start = 800 + 40,
615 .hsync_end = 800 + 40 + 216,
616 .htotal = 800 + 40 + 216 + 128,
617 .vdisplay = 600,
618 .vsync_start = 600 + 10,
619 .vsync_end = 600 + 10 + 35,
620 .vtotal = 600 + 10 + 35 + 2,
621 .vrefresh = 60,
622};
623
624static const struct panel_desc auo_g104sn02 = {
625 .modes = &auo_g104sn02_mode,
626 .num_modes = 1,
627 .bpc = 8,
628 .size = {
629 .width = 211,
630 .height = 158,
631 },
632};
633
697035c6
LS		 634static const struct display_timing auo_g133han01_timings = {
635 .pixelclock = { 134000000, 141200000, 149000000 },
636 .hactive = { 1920, 1920, 1920 },
637 .hfront_porch = { 39, 58, 77 },
638 .hback_porch = { 59, 88, 117 },
639 .hsync_len = { 28, 42, 56 },
640 .vactive = { 1080, 1080, 1080 },
641 .vfront_porch = { 3, 8, 11 },
642 .vback_porch = { 5, 14, 19 },
643 .vsync_len = { 4, 14, 19 },
644};
645
646static const struct panel_desc auo_g133han01 = {
647 .timings = &auo_g133han01_timings,
648 .num_timings = 1,
649 .bpc = 8,
650 .size = {
651 .width = 293,
652 .height = 165,
653 },
654 .delay = {
655 .prepare = 200,
656 .enable = 50,
657 .disable = 50,
658 .unprepare = 1000,
659 },
660 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
661};
662
8c31f603
LS		 663static const struct display_timing auo_g185han01_timings = {
664 .pixelclock = { 120000000, 144000000, 175000000 },
665 .hactive = { 1920, 1920, 1920 },
666 .hfront_porch = { 18, 60, 74 },
667 .hback_porch = { 12, 44, 54 },
668 .hsync_len = { 10, 24, 32 },
669 .vactive = { 1080, 1080, 1080 },
670 .vfront_porch = { 6, 10, 40 },
671 .vback_porch = { 2, 5, 20 },
672 .vsync_len = { 2, 5, 20 },
673};
674
675static const struct panel_desc auo_g185han01 = {
676 .timings = &auo_g185han01_timings,
677 .num_timings = 1,
678 .bpc = 8,
679 .size = {
680 .width = 409,
681 .height = 230,
682 },
683 .delay = {
684 .prepare = 50,
685 .enable = 200,
686 .disable = 110,
687 .unprepare = 1000,
688 },
689 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
690};
691
70c0d5b7
LS		 692static const struct display_timing auo_p320hvn03_timings = {
693 .pixelclock = { 106000000, 148500000, 164000000 },
694 .hactive = { 1920, 1920, 1920 },
695 .hfront_porch = { 25, 50, 130 },
696 .hback_porch = { 25, 50, 130 },
697 .hsync_len = { 20, 40, 105 },
698 .vactive = { 1080, 1080, 1080 },
699 .vfront_porch = { 8, 17, 150 },
700 .vback_porch = { 8, 17, 150 },
701 .vsync_len = { 4, 11, 100 },
702};
703
704static const struct panel_desc auo_p320hvn03 = {
705 .timings = &auo_p320hvn03_timings,
706 .num_timings = 1,
707 .bpc = 8,
708 .size = {
709 .width = 698,
710 .height = 393,
711 },
712 .delay = {
713 .prepare = 1,
714 .enable = 450,
715 .unprepare = 500,
716 },
2554f154 717 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
70c0d5b7
LS		 718};
719
7ee933a1
HS		 720static const struct drm_display_mode auo_t215hvn01_mode = {
721 .clock = 148800,
722 .hdisplay = 1920,
723 .hsync_start = 1920 + 88,
724 .hsync_end = 1920 + 88 + 44,
725 .htotal = 1920 + 88 + 44 + 148,
726 .vdisplay = 1080,
727 .vsync_start = 1080 + 4,
728 .vsync_end = 1080 + 4 + 5,
729 .vtotal = 1080 + 4 + 5 + 36,
730 .vrefresh = 60,
731};
732
733static const struct panel_desc auo_t215hvn01 = {
734 .modes = &auo_t215hvn01_mode,
735 .num_modes = 1,
736 .bpc = 8,
737 .size = {
738 .width = 430,
739 .height = 270,
740 },
741 .delay = {
742 .disable = 5,
743 .unprepare = 1000,
744 }
745};
746
d47df633
PZ		 747static const struct drm_display_mode avic_tm070ddh03_mode = {
748 .clock = 51200,
749 .hdisplay = 1024,
750 .hsync_start = 1024 + 160,
751 .hsync_end = 1024 + 160 + 4,
752 .htotal = 1024 + 160 + 4 + 156,
753 .vdisplay = 600,
754 .vsync_start = 600 + 17,
755 .vsync_end = 600 + 17 + 1,
756 .vtotal = 600 + 17 + 1 + 17,
757 .vrefresh = 60,
758};
759
760static const struct panel_desc avic_tm070ddh03 = {
761 .modes = &avic_tm070ddh03_mode,
762 .num_modes = 1,
763 .bpc = 8,
764 .size = {
765 .width = 154,
766 .height = 90,
767 },
768 .delay = {
769 .prepare = 20,
770 .enable = 200,
771 .disable = 200,
772 },
773};
774
cac1a411
CW		 775static const struct drm_display_mode boe_nv101wxmn51_modes[] = {
776 {
777 .clock = 71900,
778 .hdisplay = 1280,
779 .hsync_start = 1280 + 48,
780 .hsync_end = 1280 + 48 + 32,
781 .htotal = 1280 + 48 + 32 + 80,
782 .vdisplay = 800,
783 .vsync_start = 800 + 3,
784 .vsync_end = 800 + 3 + 5,
785 .vtotal = 800 + 3 + 5 + 24,
786 .vrefresh = 60,
787 },
788 {
789 .clock = 57500,
790 .hdisplay = 1280,
791 .hsync_start = 1280 + 48,
792 .hsync_end = 1280 + 48 + 32,
793 .htotal = 1280 + 48 + 32 + 80,
794 .vdisplay = 800,
795 .vsync_start = 800 + 3,
796 .vsync_end = 800 + 3 + 5,
797 .vtotal = 800 + 3 + 5 + 24,
798 .vrefresh = 48,
799 },
800};
801
802static const struct panel_desc boe_nv101wxmn51 = {
803 .modes = boe_nv101wxmn51_modes,
804 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes),
805 .bpc = 8,
806 .size = {
807 .width = 217,
808 .height = 136,
809 },
810 .delay = {
811 .prepare = 210,
812 .enable = 50,
813 .unprepare = 160,
814 },
815};
816
2cb35c80
RL		 817static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
818 .clock = 66770,
819 .hdisplay = 800,
820 .hsync_start = 800 + 49,
821 .hsync_end = 800 + 49 + 33,
822 .htotal = 800 + 49 + 33 + 17,
823 .vdisplay = 1280,
824 .vsync_start = 1280 + 1,
825 .vsync_end = 1280 + 1 + 7,
826 .vtotal = 1280 + 1 + 7 + 15,
827 .vrefresh = 60,
828 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
829};
830
831static const struct panel_desc chunghwa_claa070wp03xg = {
832 .modes = &chunghwa_claa070wp03xg_mode,
833 .num_modes = 1,
834 .bpc = 6,
835 .size = {
836 .width = 94,
837 .height = 150,
838 },
839};
840
4c930757
SW		 841static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
842 .clock = 72070,
843 .hdisplay = 1366,
844 .hsync_start = 1366 + 58,
845 .hsync_end = 1366 + 58 + 58,
846 .htotal = 1366 + 58 + 58 + 58,
847 .vdisplay = 768,
848 .vsync_start = 768 + 4,
849 .vsync_end = 768 + 4 + 4,
850 .vtotal = 768 + 4 + 4 + 4,
851 .vrefresh = 60,
852};
853
854static const struct panel_desc chunghwa_claa101wa01a = {
855 .modes = &chunghwa_claa101wa01a_mode,
856 .num_modes = 1,
0208d511 857 .bpc = 6,
4c930757
SW		 858 .size = {
859 .width = 220,
860 .height = 120,
861 },
862};
863
280921de
TR		 864static const struct drm_display_mode chunghwa_claa101wb01_mode = {
865 .clock = 69300,
866 .hdisplay = 1366,
867 .hsync_start = 1366 + 48,
868 .hsync_end = 1366 + 48 + 32,
869 .htotal = 1366 + 48 + 32 + 20,
870 .vdisplay = 768,
871 .vsync_start = 768 + 16,
872 .vsync_end = 768 + 16 + 8,
873 .vtotal = 768 + 16 + 8 + 16,
874 .vrefresh = 60,
875};
876
877static const struct panel_desc chunghwa_claa101wb01 = {
878 .modes = &chunghwa_claa101wb01_mode,
879 .num_modes = 1,
0208d511 880 .bpc = 6,
280921de
TR		 881 .size = {
882 .width = 223,
883 .height = 125,
884 },
885};
886
26ab0065
SA		 887static const struct drm_display_mode edt_et057090dhu_mode = {
888 .clock = 25175,
889 .hdisplay = 640,
890 .hsync_start = 640 + 16,
891 .hsync_end = 640 + 16 + 30,
892 .htotal = 640 + 16 + 30 + 114,
893 .vdisplay = 480,
894 .vsync_start = 480 + 10,
895 .vsync_end = 480 + 10 + 3,
896 .vtotal = 480 + 10 + 3 + 32,
897 .vrefresh = 60,
898 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
899};
900
901static const struct panel_desc edt_et057090dhu = {
902 .modes = &edt_et057090dhu_mode,
903 .num_modes = 1,
0208d511 904 .bpc = 6,
26ab0065
SA		 905 .size = {
906 .width = 115,
907 .height = 86,
908 },
eaeebffa
SA		 909 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
910 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
26ab0065
SA		 911};
912
fff5de45
PZ		 913static const struct drm_display_mode edt_etm0700g0dh6_mode = {
914 .clock = 33260,
915 .hdisplay = 800,
916 .hsync_start = 800 + 40,
917 .hsync_end = 800 + 40 + 128,
918 .htotal = 800 + 40 + 128 + 88,
919 .vdisplay = 480,
920 .vsync_start = 480 + 10,
921 .vsync_end = 480 + 10 + 2,
922 .vtotal = 480 + 10 + 2 + 33,
923 .vrefresh = 60,
924 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
925};
926
927static const struct panel_desc edt_etm0700g0dh6 = {
928 .modes = &edt_etm0700g0dh6_mode,
929 .num_modes = 1,
0208d511 930 .bpc = 6,
fff5de45
PZ		 931 .size = {
932 .width = 152,
933 .height = 91,
934 },
eaeebffa
SA		 935 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
936 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
fff5de45
PZ		 937};
938
102932b0
BB		 939static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
940 .clock = 32260,
941 .hdisplay = 800,
942 .hsync_start = 800 + 168,
943 .hsync_end = 800 + 168 + 64,
944 .htotal = 800 + 168 + 64 + 88,
945 .vdisplay = 480,
946 .vsync_start = 480 + 37,
947 .vsync_end = 480 + 37 + 2,
948 .vtotal = 480 + 37 + 2 + 8,
949 .vrefresh = 60,
950};
951
952static const struct panel_desc foxlink_fl500wvr00_a0t = {
953 .modes = &foxlink_fl500wvr00_a0t_mode,
954 .num_modes = 1,
d7a839cd 955 .bpc = 8,
102932b0
BB		 956 .size = {
957 .width = 108,
958 .height = 65,
959 },
bb276cb3 960 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
102932b0
BB		 961};
962
d435a2af
PZ		 963static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
964 .clock = 9000,
965 .hdisplay = 480,
966 .hsync_start = 480 + 5,
967 .hsync_end = 480 + 5 + 1,
968 .htotal = 480 + 5 + 1 + 40,
969 .vdisplay = 272,
970 .vsync_start = 272 + 8,
971 .vsync_end = 272 + 8 + 1,
972 .vtotal = 272 + 8 + 1 + 8,
973 .vrefresh = 60,
974};
975
976static const struct panel_desc giantplus_gpg482739qs5 = {
977 .modes = &giantplus_gpg482739qs5_mode,
978 .num_modes = 1,
979 .bpc = 8,
980 .size = {
981 .width = 95,
982 .height = 54,
983 },
33536a09 984 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
d435a2af
PZ		 985};
986
ab07725a
PZ		 987static const struct display_timing hannstar_hsd070pww1_timing = {
988 .pixelclock = { 64300000, 71100000, 82000000 },
989 .hactive = { 1280, 1280, 1280 },
990 .hfront_porch = { 1, 1, 10 },
991 .hback_porch = { 1, 1, 10 },
d901d2ba
PZ		 992 /*
993 * According to the data sheet, the minimum horizontal blanking interval
994 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
995 * minimum working horizontal blanking interval to be 60 clocks.
996 */
997 .hsync_len = { 58, 158, 661 },
ab07725a
PZ		 998 .vactive = { 800, 800, 800 },
999 .vfront_porch = { 1, 1, 10 },
1000 .vback_porch = { 1, 1, 10 },
1001 .vsync_len = { 1, 21, 203 },
1002 .flags = DISPLAY_FLAGS_DE_HIGH,
a853205e
PZ		 1003};
1004
1005static const struct panel_desc hannstar_hsd070pww1 = {
ab07725a
PZ		 1006 .timings = &hannstar_hsd070pww1_timing,
1007 .num_timings = 1,
a853205e
PZ		 1008 .bpc = 6,
1009 .size = {
1010 .width = 151,
1011 .height = 94,
1012 },
58d6a7bc 1013 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
a853205e
PZ		 1014};
1015
c0d607e5
EN		 1016static const struct display_timing hannstar_hsd100pxn1_timing = {
1017 .pixelclock = { 55000000, 65000000, 75000000 },
1018 .hactive = { 1024, 1024, 1024 },
1019 .hfront_porch = { 40, 40, 40 },
1020 .hback_porch = { 220, 220, 220 },
1021 .hsync_len = { 20, 60, 100 },
1022 .vactive = { 768, 768, 768 },
1023 .vfront_porch = { 7, 7, 7 },
1024 .vback_porch = { 21, 21, 21 },
1025 .vsync_len = { 10, 10, 10 },
1026 .flags = DISPLAY_FLAGS_DE_HIGH,
1027};
1028
1029static const struct panel_desc hannstar_hsd100pxn1 = {
1030 .timings = &hannstar_hsd100pxn1_timing,
1031 .num_timings = 1,
1032 .bpc = 6,
1033 .size = {
1034 .width = 203,
1035 .height = 152,
1036 },
4946b043 1037 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
c0d607e5
EN		 1038};
1039
61ac0bf8
LS		 1040static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
1041 .clock = 33333,
1042 .hdisplay = 800,
1043 .hsync_start = 800 + 85,
1044 .hsync_end = 800 + 85 + 86,
1045 .htotal = 800 + 85 + 86 + 85,
1046 .vdisplay = 480,
1047 .vsync_start = 480 + 16,
1048 .vsync_end = 480 + 16 + 13,
1049 .vtotal = 480 + 16 + 13 + 16,
1050 .vrefresh = 60,
1051};
1052
1053static const struct panel_desc hitachi_tx23d38vm0caa = {
1054 .modes = &hitachi_tx23d38vm0caa_mode,
1055 .num_modes = 1,
1056 .bpc = 6,
1057 .size = {
1058 .width = 195,
1059 .height = 117,
1060 },
6c684e3b
PZ		 1061 .delay = {
1062 .enable = 160,
1063 .disable = 160,
1064 },
61ac0bf8
LS		 1065};
1066
41bcceb4
NF		 1067static const struct drm_display_mode innolux_at043tn24_mode = {
1068 .clock = 9000,
1069 .hdisplay = 480,
1070 .hsync_start = 480 + 2,
1071 .hsync_end = 480 + 2 + 41,
1072 .htotal = 480 + 2 + 41 + 2,
1073 .vdisplay = 272,
1074 .vsync_start = 272 + 2,
a483159d
PZ		 1075 .vsync_end = 272 + 2 + 10,
1076 .vtotal = 272 + 2 + 10 + 2,
41bcceb4
NF		 1077 .vrefresh = 60,
1078 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1079};
1080
1081static const struct panel_desc innolux_at043tn24 = {
1082 .modes = &innolux_at043tn24_mode,
1083 .num_modes = 1,
1084 .bpc = 8,
1085 .size = {
1086 .width = 95,
1087 .height = 54,
1088 },
1089 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
6560279c 1090 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
41bcceb4
NF		 1091};
1092
4fc24ab3
RB		 1093static const struct drm_display_mode innolux_at070tn92_mode = {
1094 .clock = 33333,
1095 .hdisplay = 800,
1096 .hsync_start = 800 + 210,
1097 .hsync_end = 800 + 210 + 20,
1098 .htotal = 800 + 210 + 20 + 46,
1099 .vdisplay = 480,
1100 .vsync_start = 480 + 22,
1101 .vsync_end = 480 + 22 + 10,
1102 .vtotal = 480 + 22 + 23 + 10,
1103 .vrefresh = 60,
1104};
1105
1106static const struct panel_desc innolux_at070tn92 = {
1107 .modes = &innolux_at070tn92_mode,
1108 .num_modes = 1,
1109 .size = {
1110 .width = 154,
1111 .height = 86,
1112 },
1113 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1114};
1115
1e29b840
MO		 1116static const struct display_timing innolux_g101ice_l01_timing = {
1117 .pixelclock = { 60400000, 71100000, 74700000 },
1118 .hactive = { 1280, 1280, 1280 },
1119 .hfront_porch = { 41, 80, 100 },
1120 .hback_porch = { 40, 79, 99 },
1121 .hsync_len = { 1, 1, 1 },
1122 .vactive = { 800, 800, 800 },
1123 .vfront_porch = { 5, 11, 14 },
1124 .vback_porch = { 4, 11, 14 },
1125 .vsync_len = { 1, 1, 1 },
1126 .flags = DISPLAY_FLAGS_DE_HIGH,
1127};
1128
1129static const struct panel_desc innolux_g101ice_l01 = {
1130 .timings = &innolux_g101ice_l01_timing,
1131 .num_timings = 1,
1132 .bpc = 8,
1133 .size = {
1134 .width = 217,
1135 .height = 135,
1136 },
1137 .delay = {
1138 .enable = 200,
1139 .disable = 200,
1140 },
1141 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1142};
1143
4ae13e48
LS		 1144static const struct display_timing innolux_g121i1_l01_timing = {
1145 .pixelclock = { 67450000, 71000000, 74550000 },
1146 .hactive = { 1280, 1280, 1280 },
1147 .hfront_porch = { 40, 80, 160 },
1148 .hback_porch = { 39, 79, 159 },
1149 .hsync_len = { 1, 1, 1 },
1150 .vactive = { 800, 800, 800 },
1151 .vfront_porch = { 5, 11, 100 },
1152 .vback_porch = { 4, 11, 99 },
1153 .vsync_len = { 1, 1, 1 },
d731f661
LS		 1154};
1155
1156static const struct panel_desc innolux_g121i1_l01 = {
4ae13e48
LS		 1157 .timings = &innolux_g121i1_l01_timing,
1158 .num_timings = 1,
d731f661
LS		 1159 .bpc = 6,
1160 .size = {
1161 .width = 261,
1162 .height = 163,
1163 },
4ae13e48
LS		 1164 .delay = {
1165 .enable = 200,
1166 .disable = 20,
1167 },
1168 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
d731f661
LS		 1169};
1170
f8fa17ba
AB		 1171static const struct drm_display_mode innolux_g121x1_l03_mode = {
1172 .clock = 65000,
1173 .hdisplay = 1024,
1174 .hsync_start = 1024 + 0,
1175 .hsync_end = 1024 + 1,
1176 .htotal = 1024 + 0 + 1 + 320,
1177 .vdisplay = 768,
1178 .vsync_start = 768 + 38,
1179 .vsync_end = 768 + 38 + 1,
1180 .vtotal = 768 + 38 + 1 + 0,
1181 .vrefresh = 60,
2e8c5eb9 1182 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
f8fa17ba
AB		 1183};
1184
1185static const struct panel_desc innolux_g121x1_l03 = {
1186 .modes = &innolux_g121x1_l03_mode,
1187 .num_modes = 1,
1188 .bpc = 6,
1189 .size = {
1190 .width = 246,
1191 .height = 185,
1192 },
1193 .delay = {
1194 .enable = 200,
1195 .unprepare = 200,
1196 .disable = 400,
1197 },
1198};
1199
0a2288c0 1200static const struct drm_display_mode innolux_n116bge_mode = {
7fe8c777 1201 .clock = 76420,
0a2288c0 1202 .hdisplay = 1366,
7fe8c777
DK		 1203 .hsync_start = 1366 + 136,
1204 .hsync_end = 1366 + 136 + 30,
1205 .htotal = 1366 + 136 + 30 + 60,
0a2288c0
TR		 1206 .vdisplay = 768,
1207 .vsync_start = 768 + 8,
7fe8c777
DK		 1208 .vsync_end = 768 + 8 + 12,
1209 .vtotal = 768 + 8 + 12 + 12,
0a2288c0
TR		 1210 .vrefresh = 60,
1211 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1212};
1213
1214static const struct panel_desc innolux_n116bge = {
1215 .modes = &innolux_n116bge_mode,
1216 .num_modes = 1,
1217 .bpc = 6,
1218 .size = {
1219 .width = 256,
1220 .height = 144,
1221 },
1222};
1223
ea44739d
AB		 1224static const struct drm_display_mode innolux_n156bge_l21_mode = {
1225 .clock = 69300,
1226 .hdisplay = 1366,
1227 .hsync_start = 1366 + 16,
1228 .hsync_end = 1366 + 16 + 34,
1229 .htotal = 1366 + 16 + 34 + 50,
1230 .vdisplay = 768,
1231 .vsync_start = 768 + 2,
1232 .vsync_end = 768 + 2 + 6,
1233 .vtotal = 768 + 2 + 6 + 12,
1234 .vrefresh = 60,
1235};
1236
1237static const struct panel_desc innolux_n156bge_l21 = {
1238 .modes = &innolux_n156bge_l21_mode,
1239 .num_modes = 1,
0208d511 1240 .bpc = 6,
ea44739d
AB		 1241 .size = {
1242 .width = 344,
1243 .height = 193,
1244 },
1245};
1246
da50bd42 1247static const struct drm_display_mode innolux_tv123wam_mode = {
1248 .clock = 206016,
1249 .hdisplay = 2160,
1250 .hsync_start = 2160 + 48,
1251 .hsync_end = 2160 + 48 + 32,
1252 .htotal = 2160 + 48 + 32 + 80,
1253 .vdisplay = 1440,
1254 .vsync_start = 1440 + 3,
1255 .vsync_end = 1440 + 3 + 10,
1256 .vtotal = 1440 + 3 + 10 + 27,
1257 .vrefresh = 60,
1258 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
1259};
1260
1261static const struct panel_desc innolux_tv123wam = {
1262 .modes = &innolux_tv123wam_mode,
1263 .num_modes = 1,
1264 .bpc = 8,
1265 .size = {
1266 .width = 259,
1267 .height = 173,
1268 },
1269};
1270
bccac3f1
MG		 1271static const struct drm_display_mode innolux_zj070na_01p_mode = {
1272 .clock = 51501,
1273 .hdisplay = 1024,
1274 .hsync_start = 1024 + 128,
1275 .hsync_end = 1024 + 128 + 64,
1276 .htotal = 1024 + 128 + 64 + 128,
1277 .vdisplay = 600,
1278 .vsync_start = 600 + 16,
1279 .vsync_end = 600 + 16 + 4,
1280 .vtotal = 600 + 16 + 4 + 16,
1281 .vrefresh = 60,
1282};
1283
1284static const struct panel_desc innolux_zj070na_01p = {
1285 .modes = &innolux_zj070na_01p_mode,
1286 .num_modes = 1,
1287 .bpc = 6,
1288 .size = {
81598846
TR		 1289 .width = 154,
1290 .height = 90,
bccac3f1
MG		 1291 },
1292};
1293
8cfe8341
JT		 1294static const struct display_timing koe_tx31d200vm0baa_timing = {
1295 .pixelclock = { 39600000, 43200000, 48000000 },
1296 .hactive = { 1280, 1280, 1280 },
1297 .hfront_porch = { 16, 36, 56 },
1298 .hback_porch = { 16, 36, 56 },
1299 .hsync_len = { 8, 8, 8 },
1300 .vactive = { 480, 480, 480 },
c9b6be7d
SA		 1301 .vfront_porch = { 6, 21, 33 },
1302 .vback_porch = { 6, 21, 33 },
8cfe8341
JT		 1303 .vsync_len = { 8, 8, 8 },
1304 .flags = DISPLAY_FLAGS_DE_HIGH,
1305};
1306
1307static const struct panel_desc koe_tx31d200vm0baa = {
1308 .timings = &koe_tx31d200vm0baa_timing,
1309 .num_timings = 1,
1310 .bpc = 6,
1311 .size = {
1312 .width = 292,
1313 .height = 109,
1314 },
1315 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1316};
1317
8def22e5
LS		 1318static const struct display_timing kyo_tcg121xglp_timing = {
1319 .pixelclock = { 52000000, 65000000, 71000000 },
1320 .hactive = { 1024, 1024, 1024 },
1321 .hfront_porch = { 2, 2, 2 },
1322 .hback_porch = { 2, 2, 2 },
1323 .hsync_len = { 86, 124, 244 },
1324 .vactive = { 768, 768, 768 },
1325 .vfront_porch = { 2, 2, 2 },
1326 .vback_porch = { 2, 2, 2 },
1327 .vsync_len = { 6, 34, 73 },
1328 .flags = DISPLAY_FLAGS_DE_HIGH,
1329};
1330
1331static const struct panel_desc kyo_tcg121xglp = {
1332 .timings = &kyo_tcg121xglp_timing,
1333 .num_timings = 1,
1334 .bpc = 8,
1335 .size = {
1336 .width = 246,
1337 .height = 184,
1338 },
1339 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1340};
1341
dd015002
HS		 1342static const struct drm_display_mode lg_lb070wv8_mode = {
1343 .clock = 33246,
1344 .hdisplay = 800,
1345 .hsync_start = 800 + 88,
1346 .hsync_end = 800 + 88 + 80,
1347 .htotal = 800 + 88 + 80 + 88,
1348 .vdisplay = 480,
1349 .vsync_start = 480 + 10,
1350 .vsync_end = 480 + 10 + 25,
1351 .vtotal = 480 + 10 + 25 + 10,
1352 .vrefresh = 60,
1353};
1354
1355static const struct panel_desc lg_lb070wv8 = {
1356 .modes = &lg_lb070wv8_mode,
1357 .num_modes = 1,
1358 .bpc = 16,
1359 .size = {
1360 .width = 151,
1361 .height = 91,
1362 },
1363 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1364};
1365
c5ece402
YY		 1366static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
1367 .clock = 200000,
1368 .hdisplay = 1536,
1369 .hsync_start = 1536 + 12,
1370 .hsync_end = 1536 + 12 + 16,
1371 .htotal = 1536 + 12 + 16 + 48,
1372 .vdisplay = 2048,
1373 .vsync_start = 2048 + 8,
1374 .vsync_end = 2048 + 8 + 4,
1375 .vtotal = 2048 + 8 + 4 + 8,
1376 .vrefresh = 60,
1377 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1378};
1379
1380static const struct panel_desc lg_lp079qx1_sp0v = {
1381 .modes = &lg_lp079qx1_sp0v_mode,
1382 .num_modes = 1,
1383 .size = {
1384 .width = 129,
1385 .height = 171,
1386 },
1387};
1388
0355dde2
YY		 1389static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
1390 .clock = 205210,
1391 .hdisplay = 2048,
1392 .hsync_start = 2048 + 150,
1393 .hsync_end = 2048 + 150 + 5,
1394 .htotal = 2048 + 150 + 5 + 5,
1395 .vdisplay = 1536,
1396 .vsync_start = 1536 + 3,
1397 .vsync_end = 1536 + 3 + 1,
1398 .vtotal = 1536 + 3 + 1 + 9,
1399 .vrefresh = 60,
1400};
1401
1402static const struct panel_desc lg_lp097qx1_spa1 = {
1403 .modes = &lg_lp097qx1_spa1_mode,
1404 .num_modes = 1,
1405 .size = {
1406 .width = 208,
1407 .height = 147,
1408 },
1409};
1410
690d8fa7
JS		 1411static const struct drm_display_mode lg_lp120up1_mode = {
1412 .clock = 162300,
1413 .hdisplay = 1920,
1414 .hsync_start = 1920 + 40,
1415 .hsync_end = 1920 + 40 + 40,
1416 .htotal = 1920 + 40 + 40+ 80,
1417 .vdisplay = 1280,
1418 .vsync_start = 1280 + 4,
1419 .vsync_end = 1280 + 4 + 4,
1420 .vtotal = 1280 + 4 + 4 + 12,
1421 .vrefresh = 60,
1422};
1423
1424static const struct panel_desc lg_lp120up1 = {
1425 .modes = &lg_lp120up1_mode,
1426 .num_modes = 1,
1427 .bpc = 8,
1428 .size = {
1429 .width = 267,
1430 .height = 183,
1431 },
1432};
1433
ec7c5653
TR		 1434static const struct drm_display_mode lg_lp129qe_mode = {
1435 .clock = 285250,
1436 .hdisplay = 2560,
1437 .hsync_start = 2560 + 48,
1438 .hsync_end = 2560 + 48 + 32,
1439 .htotal = 2560 + 48 + 32 + 80,
1440 .vdisplay = 1700,
1441 .vsync_start = 1700 + 3,
1442 .vsync_end = 1700 + 3 + 10,
1443 .vtotal = 1700 + 3 + 10 + 36,
1444 .vrefresh = 60,
1445};
1446
1447static const struct panel_desc lg_lp129qe = {
1448 .modes = &lg_lp129qe_mode,
1449 .num_modes = 1,
0208d511 1450 .bpc = 8,
ec7c5653
TR		 1451 .size = {
1452 .width = 272,
1453 .height = 181,
1454 },
1455};
1456
65c766ca
LM		 1457static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
1458 .clock = 30400,
1459 .hdisplay = 800,
1460 .hsync_start = 800 + 0,
1461 .hsync_end = 800 + 1,
1462 .htotal = 800 + 0 + 1 + 160,
1463 .vdisplay = 480,
1464 .vsync_start = 480 + 0,
1465 .vsync_end = 480 + 48 + 1,
1466 .vtotal = 480 + 48 + 1 + 0,
1467 .vrefresh = 60,
1468 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1469};
1470
1471static const struct panel_desc mitsubishi_aa070mc01 = {
1472 .modes = &mitsubishi_aa070mc01_mode,
1473 .num_modes = 1,
1474 .bpc = 8,
1475 .size = {
1476 .width = 152,
1477 .height = 91,
1478 },
1479
1480 .delay = {
1481 .enable = 200,
1482 .unprepare = 200,
1483 .disable = 400,
1484 },
1485 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1486 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1487};
1488
01bacc13
LS		 1489static const struct display_timing nec_nl12880bc20_05_timing = {
1490 .pixelclock = { 67000000, 71000000, 75000000 },
1491 .hactive = { 1280, 1280, 1280 },
1492 .hfront_porch = { 2, 30, 30 },
1493 .hback_porch = { 6, 100, 100 },
1494 .hsync_len = { 2, 30, 30 },
1495 .vactive = { 800, 800, 800 },
1496 .vfront_porch = { 5, 5, 5 },
1497 .vback_porch = { 11, 11, 11 },
1498 .vsync_len = { 7, 7, 7 },
1499};
1500
1501static const struct panel_desc nec_nl12880bc20_05 = {
1502 .timings = &nec_nl12880bc20_05_timing,
1503 .num_timings = 1,
1504 .bpc = 8,
1505 .size = {
1506 .width = 261,
1507 .height = 163,
1508 },
1509 .delay = {
1510 .enable = 50,
1511 .disable = 50,
1512 },
1513 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1514};
1515
c6e87f91 1516static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
1517 .clock = 10870,
1518 .hdisplay = 480,
1519 .hsync_start = 480 + 2,
1520 .hsync_end = 480 + 2 + 41,
1521 .htotal = 480 + 2 + 41 + 2,
1522 .vdisplay = 272,
1523 .vsync_start = 272 + 2,
1524 .vsync_end = 272 + 2 + 4,
1525 .vtotal = 272 + 2 + 4 + 2,
1526 .vrefresh = 74,
4bc390c6 1527 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
c6e87f91 1528};
1529
1530static const struct panel_desc nec_nl4827hc19_05b = {
1531 .modes = &nec_nl4827hc19_05b_mode,
1532 .num_modes = 1,
1533 .bpc = 8,
1534 .size = {
1535 .width = 95,
1536 .height = 54,
1537 },
2c80661d
SA		 1538 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1539 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
c6e87f91 1540};
1541
e6c2f066
MR		 1542static const struct drm_display_mode netron_dy_e231732_mode = {
1543 .clock = 66000,
1544 .hdisplay = 1024,
1545 .hsync_start = 1024 + 160,
1546 .hsync_end = 1024 + 160 + 70,
1547 .htotal = 1024 + 160 + 70 + 90,
1548 .vdisplay = 600,
1549 .vsync_start = 600 + 127,
1550 .vsync_end = 600 + 127 + 20,
1551 .vtotal = 600 + 127 + 20 + 3,
1552 .vrefresh = 60,
1553};
1554
1555static const struct panel_desc netron_dy_e231732 = {
1556 .modes = &netron_dy_e231732_mode,
1557 .num_modes = 1,
1558 .size = {
1559 .width = 154,
1560 .height = 87,
1561 },
1562 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1563};
1564
4177fa66
LS		 1565static const struct display_timing nlt_nl192108ac18_02d_timing = {
1566 .pixelclock = { 130000000, 148350000, 163000000 },
1567 .hactive = { 1920, 1920, 1920 },
1568 .hfront_porch = { 80, 100, 100 },
1569 .hback_porch = { 100, 120, 120 },
1570 .hsync_len = { 50, 60, 60 },
1571 .vactive = { 1080, 1080, 1080 },
1572 .vfront_porch = { 12, 30, 30 },
1573 .vback_porch = { 4, 10, 10 },
1574 .vsync_len = { 4, 5, 5 },
1575};
1576
1577static const struct panel_desc nlt_nl192108ac18_02d = {
1578 .timings = &nlt_nl192108ac18_02d_timing,
1579 .num_timings = 1,
1580 .bpc = 8,
1581 .size = {
1582 .width = 344,
1583 .height = 194,
1584 },
1585 .delay = {
1586 .unprepare = 500,
1587 },
1588 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1589};
1590
05ec0e45
FL		 1591static const struct drm_display_mode nvd_9128_mode = {
1592 .clock = 29500,
1593 .hdisplay = 800,
1594 .hsync_start = 800 + 130,
1595 .hsync_end = 800 + 130 + 98,
1596 .htotal = 800 + 0 + 130 + 98,
1597 .vdisplay = 480,
1598 .vsync_start = 480 + 10,
1599 .vsync_end = 480 + 10 + 50,
1600 .vtotal = 480 + 0 + 10 + 50,
1601};
1602
1603static const struct panel_desc nvd_9128 = {
1604 .modes = &nvd_9128_mode,
1605 .num_modes = 1,
1606 .bpc = 8,
1607 .size = {
1608 .width = 156,
1609 .height = 88,
1610 },
1611 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1612};
1613
a99fb626
GB		 1614static const struct display_timing okaya_rs800480t_7x0gp_timing = {
1615 .pixelclock = { 30000000, 30000000, 40000000 },
1616 .hactive = { 800, 800, 800 },
1617 .hfront_porch = { 40, 40, 40 },
1618 .hback_porch = { 40, 40, 40 },
1619 .hsync_len = { 1, 48, 48 },
1620 .vactive = { 480, 480, 480 },
1621 .vfront_porch = { 13, 13, 13 },
1622 .vback_porch = { 29, 29, 29 },
1623 .vsync_len = { 3, 3, 3 },
1624 .flags = DISPLAY_FLAGS_DE_HIGH,
1625};
1626
1627static const struct panel_desc okaya_rs800480t_7x0gp = {
1628 .timings = &okaya_rs800480t_7x0gp_timing,
1629 .num_timings = 1,
1630 .bpc = 6,
1631 .size = {
1632 .width = 154,
1633 .height = 87,
1634 },
1635 .delay = {
1636 .prepare = 41,
1637 .enable = 50,
1638 .unprepare = 41,
1639 .disable = 50,
1640 },
1641 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1642};
1643
cf5c9e6d
MR		 1644static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
1645 .clock = 9000,
1646 .hdisplay = 480,
1647 .hsync_start = 480 + 5,
1648 .hsync_end = 480 + 5 + 30,
1649 .htotal = 480 + 5 + 30 + 10,
1650 .vdisplay = 272,
1651 .vsync_start = 272 + 8,
1652 .vsync_end = 272 + 8 + 5,
1653 .vtotal = 272 + 8 + 5 + 3,
1654 .vrefresh = 60,
1655};
1656
1657static const struct panel_desc olimex_lcd_olinuxino_43ts = {
1658 .modes = &olimex_lcd_olinuxino_43ts_mode,
1659 .num_modes = 1,
1660 .size = {
30c6d7ab
JL		 1661 .width = 95,
1662 .height = 54,
cf5c9e6d 1663 },
5c2a7c6b 1664 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
cf5c9e6d
MR		 1665};
1666
e8b6f561
EA		 1667/*
1668 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
1669 * pixel clocks, but this is the timing that was being used in the Adafruit
1670 * installation instructions.
1671 */
1672static const struct drm_display_mode ontat_yx700wv03_mode = {
1673 .clock = 29500,
1674 .hdisplay = 800,
1675 .hsync_start = 824,
1676 .hsync_end = 896,
1677 .htotal = 992,
1678 .vdisplay = 480,
1679 .vsync_start = 483,
1680 .vsync_end = 493,
1681 .vtotal = 500,
1682 .vrefresh = 60,
1683 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1684};
1685
1686/*
1687 * Specification at:
1688 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
1689 */
1690static const struct panel_desc ontat_yx700wv03 = {
1691 .modes = &ontat_yx700wv03_mode,
1692 .num_modes = 1,
1693 .bpc = 8,
1694 .size = {
1695 .width = 154,
1696 .height = 83,
1697 },
5651e5e0 1698 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
e8b6f561
EA		 1699};
1700
725c9d40
PZ		 1701static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
1702 .clock = 25000,
1703 .hdisplay = 480,
1704 .hsync_start = 480 + 10,
1705 .hsync_end = 480 + 10 + 10,
1706 .htotal = 480 + 10 + 10 + 15,
1707 .vdisplay = 800,
1708 .vsync_start = 800 + 3,
1709 .vsync_end = 800 + 3 + 3,
1710 .vtotal = 800 + 3 + 3 + 3,
1711 .vrefresh = 60,
1712};
1713
1714static const struct panel_desc ortustech_com43h4m85ulc = {
1715 .modes = &ortustech_com43h4m85ulc_mode,
1716 .num_modes = 1,
1717 .bpc = 8,
1718 .size = {
1719 .width = 56,
1720 .height = 93,
1721 },
1722 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
e0932f9d 1723 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
725c9d40
PZ		 1724};
1725
d2a6f0f5
JW		 1726static const struct drm_display_mode qd43003c0_40_mode = {
1727 .clock = 9000,
1728 .hdisplay = 480,
1729 .hsync_start = 480 + 8,
1730 .hsync_end = 480 + 8 + 4,
1731 .htotal = 480 + 8 + 4 + 39,
1732 .vdisplay = 272,
1733 .vsync_start = 272 + 4,
1734 .vsync_end = 272 + 4 + 10,
1735 .vtotal = 272 + 4 + 10 + 2,
1736 .vrefresh = 60,
1737};
1738
1739static const struct panel_desc qd43003c0_40 = {
1740 .modes = &qd43003c0_40_mode,
1741 .num_modes = 1,
1742 .bpc = 8,
1743 .size = {
1744 .width = 95,
1745 .height = 53,
1746 },
1747 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1748};
1749
0330eaf3
YY		 1750static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
1751 .clock = 271560,
1752 .hdisplay = 2560,
1753 .hsync_start = 2560 + 48,
1754 .hsync_end = 2560 + 48 + 32,
1755 .htotal = 2560 + 48 + 32 + 80,
1756 .vdisplay = 1600,
1757 .vsync_start = 1600 + 2,
1758 .vsync_end = 1600 + 2 + 5,
1759 .vtotal = 1600 + 2 + 5 + 57,
1760 .vrefresh = 60,
1761};
1762
1763static const struct panel_desc samsung_lsn122dl01_c01 = {
1764 .modes = &samsung_lsn122dl01_c01_mode,
1765 .num_modes = 1,
1766 .size = {
1767 .width = 263,
1768 .height = 164,
1769 },
1770};
1771
6d54e3d2
MD		 1772static const struct drm_display_mode samsung_ltn101nt05_mode = {
1773 .clock = 54030,
1774 .hdisplay = 1024,
1775 .hsync_start = 1024 + 24,
1776 .hsync_end = 1024 + 24 + 136,
1777 .htotal = 1024 + 24 + 136 + 160,
1778 .vdisplay = 600,
1779 .vsync_start = 600 + 3,
1780 .vsync_end = 600 + 3 + 6,
1781 .vtotal = 600 + 3 + 6 + 61,
1782 .vrefresh = 60,
1783};
1784
1785static const struct panel_desc samsung_ltn101nt05 = {
1786 .modes = &samsung_ltn101nt05_mode,
1787 .num_modes = 1,
0208d511 1788 .bpc = 6,
6d54e3d2 1789 .size = {
81598846
TR		 1790 .width = 223,
1791 .height = 125,
6d54e3d2
MD		 1792 },
1793};
1794
0c934306
SM		 1795static const struct drm_display_mode samsung_ltn140at29_301_mode = {
1796 .clock = 76300,
1797 .hdisplay = 1366,
1798 .hsync_start = 1366 + 64,
1799 .hsync_end = 1366 + 64 + 48,
1800 .htotal = 1366 + 64 + 48 + 128,
1801 .vdisplay = 768,
1802 .vsync_start = 768 + 2,
1803 .vsync_end = 768 + 2 + 5,
1804 .vtotal = 768 + 2 + 5 + 17,
1805 .vrefresh = 60,
1806};
1807
1808static const struct panel_desc samsung_ltn140at29_301 = {
1809 .modes = &samsung_ltn140at29_301_mode,
1810 .num_modes = 1,
1811 .bpc = 6,
1812 .size = {
1813 .width = 320,
1814 .height = 187,
1815 },
1816};
1817
592aa02b
JC		 1818static const struct display_timing sharp_lq101k1ly04_timing = {
1819 .pixelclock = { 60000000, 65000000, 80000000 },
1820 .hactive = { 1280, 1280, 1280 },
1821 .hfront_porch = { 20, 20, 20 },
1822 .hback_porch = { 20, 20, 20 },
1823 .hsync_len = { 10, 10, 10 },
1824 .vactive = { 800, 800, 800 },
1825 .vfront_porch = { 4, 4, 4 },
1826 .vback_porch = { 4, 4, 4 },
1827 .vsync_len = { 4, 4, 4 },
1828 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
1829};
1830
1831static const struct panel_desc sharp_lq101k1ly04 = {
1832 .timings = &sharp_lq101k1ly04_timing,
1833 .num_timings = 1,
1834 .bpc = 8,
1835 .size = {
1836 .width = 217,
1837 .height = 136,
1838 },
1839 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
1840};
1841
9f7bae2d
SP		 1842static const struct display_timing sharp_lq123p1jx31_timing = {
1843 .pixelclock = { 252750000, 252750000, 266604720 },
1844 .hactive = { 2400, 2400, 2400 },
1845 .hfront_porch = { 48, 48, 48 },
1846 .hback_porch = { 80, 80, 84 },
1847 .hsync_len = { 32, 32, 32 },
1848 .vactive = { 1600, 1600, 1600 },
1849 .vfront_porch = { 3, 3, 3 },
1850 .vback_porch = { 33, 33, 120 },
1851 .vsync_len = { 10, 10, 10 },
1852 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
739c7de9
YY		 1853};
1854
1855static const struct panel_desc sharp_lq123p1jx31 = {
9f7bae2d
SP		 1856 .timings = &sharp_lq123p1jx31_timing,
1857 .num_timings = 1,
5466a631 1858 .bpc = 8,
739c7de9
YY		 1859 .size = {
1860 .width = 259,
1861 .height = 173,
1862 },
a42f6e3f
YY		 1863 .delay = {
1864 .prepare = 110,
1865 .enable = 50,
1866 .unprepare = 550,
1867 },
739c7de9
YY		 1868};
1869
0f9cdd74
GL		 1870static const struct drm_display_mode sharp_lq150x1lg11_mode = {
1871 .clock = 71100,
1872 .hdisplay = 1024,
1873 .hsync_start = 1024 + 168,
1874 .hsync_end = 1024 + 168 + 64,
1875 .htotal = 1024 + 168 + 64 + 88,
1876 .vdisplay = 768,
1877 .vsync_start = 768 + 37,
1878 .vsync_end = 768 + 37 + 2,
1879 .vtotal = 768 + 37 + 2 + 8,
1880 .vrefresh = 60,
1881};
1882
1883static const struct panel_desc sharp_lq150x1lg11 = {
1884 .modes = &sharp_lq150x1lg11_mode,
1885 .num_modes = 1,
1886 .bpc = 6,
1887 .size = {
1888 .width = 304,
1889 .height = 228,
1890 },
1891 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
1892};
1893
9c6615bc
BB		 1894static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
1895 .clock = 33300,
1896 .hdisplay = 800,
1897 .hsync_start = 800 + 1,
1898 .hsync_end = 800 + 1 + 64,
1899 .htotal = 800 + 1 + 64 + 64,
1900 .vdisplay = 480,
1901 .vsync_start = 480 + 1,
1902 .vsync_end = 480 + 1 + 23,
1903 .vtotal = 480 + 1 + 23 + 22,
1904 .vrefresh = 60,
1905};
1906
1907static const struct panel_desc shelly_sca07010_bfn_lnn = {
1908 .modes = &shelly_sca07010_bfn_lnn_mode,
1909 .num_modes = 1,
1910 .size = {
1911 .width = 152,
1912 .height = 91,
1913 },
1914 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1915};
1916
9bb34c4c
DA		 1917static const struct drm_display_mode starry_kr122ea0sra_mode = {
1918 .clock = 147000,
1919 .hdisplay = 1920,
1920 .hsync_start = 1920 + 16,
1921 .hsync_end = 1920 + 16 + 16,
1922 .htotal = 1920 + 16 + 16 + 32,
1923 .vdisplay = 1200,
1924 .vsync_start = 1200 + 15,
1925 .vsync_end = 1200 + 15 + 2,
1926 .vtotal = 1200 + 15 + 2 + 18,
1927 .vrefresh = 60,
1928 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1929};
1930
1931static const struct panel_desc starry_kr122ea0sra = {
1932 .modes = &starry_kr122ea0sra_mode,
1933 .num_modes = 1,
1934 .size = {
1935 .width = 263,
1936 .height = 164,
1937 },
c46b924b
BN		 1938 .delay = {
1939 .prepare = 10 + 200,
1940 .enable = 50,
1941 .unprepare = 10 + 500,
1942 },
9bb34c4c
DA		 1943};
1944
adb973ef
GB		 1945static const struct display_timing tianma_tm070jdhg30_timing = {
1946 .pixelclock = { 62600000, 68200000, 78100000 },
1947 .hactive = { 1280, 1280, 1280 },
1948 .hfront_porch = { 15, 64, 159 },
1949 .hback_porch = { 5, 5, 5 },
1950 .hsync_len = { 1, 1, 256 },
1951 .vactive = { 800, 800, 800 },
1952 .vfront_porch = { 3, 40, 99 },
1953 .vback_porch = { 2, 2, 2 },
1954 .vsync_len = { 1, 1, 128 },
1955 .flags = DISPLAY_FLAGS_DE_HIGH,
1956};
1957
1958static const struct panel_desc tianma_tm070jdhg30 = {
1959 .timings = &tianma_tm070jdhg30_timing,
1960 .num_timings = 1,
1961 .bpc = 8,
1962 .size = {
1963 .width = 151,
1964 .height = 95,
1965 },
1966 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1967};
1968
870a0b12
LM		 1969static const struct display_timing tianma_tm070rvhg71_timing = {
1970 .pixelclock = { 27700000, 29200000, 39600000 },
1971 .hactive = { 800, 800, 800 },
1972 .hfront_porch = { 12, 40, 212 },
1973 .hback_porch = { 88, 88, 88 },
1974 .hsync_len = { 1, 1, 40 },
1975 .vactive = { 480, 480, 480 },
1976 .vfront_porch = { 1, 13, 88 },
1977 .vback_porch = { 32, 32, 32 },
1978 .vsync_len = { 1, 1, 3 },
1979 .flags = DISPLAY_FLAGS_DE_HIGH,
1980};
1981
1982static const struct panel_desc tianma_tm070rvhg71 = {
1983 .timings = &tianma_tm070rvhg71_timing,
1984 .num_timings = 1,
1985 .bpc = 8,
1986 .size = {
1987 .width = 154,
1988 .height = 86,
1989 },
1990 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1991};
1992
06e733e4
LS		 1993static const struct drm_display_mode toshiba_lt089ac29000_mode = {
1994 .clock = 79500,
1995 .hdisplay = 1280,
1996 .hsync_start = 1280 + 192,
1997 .hsync_end = 1280 + 192 + 128,
1998 .htotal = 1280 + 192 + 128 + 64,
1999 .vdisplay = 768,
2000 .vsync_start = 768 + 20,
2001 .vsync_end = 768 + 20 + 7,
2002 .vtotal = 768 + 20 + 7 + 3,
2003 .vrefresh = 60,
2004};
2005
2006static const struct panel_desc toshiba_lt089ac29000 = {
2007 .modes = &toshiba_lt089ac29000_mode,
2008 .num_modes = 1,
2009 .size = {
2010 .width = 194,
2011 .height = 116,
2012 },
2013 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2014 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
2015};
2016
227e4f40
BD		 2017static const struct drm_display_mode tpk_f07a_0102_mode = {
2018 .clock = 33260,
2019 .hdisplay = 800,
2020 .hsync_start = 800 + 40,
2021 .hsync_end = 800 + 40 + 128,
2022 .htotal = 800 + 40 + 128 + 88,
2023 .vdisplay = 480,
2024 .vsync_start = 480 + 10,
2025 .vsync_end = 480 + 10 + 2,
2026 .vtotal = 480 + 10 + 2 + 33,
2027 .vrefresh = 60,
2028};
2029
2030static const struct panel_desc tpk_f07a_0102 = {
2031 .modes = &tpk_f07a_0102_mode,
2032 .num_modes = 1,
2033 .size = {
2034 .width = 152,
2035 .height = 91,
2036 },
2037 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
2038};
2039
2040static const struct drm_display_mode tpk_f10a_0102_mode = {
2041 .clock = 45000,
2042 .hdisplay = 1024,
2043 .hsync_start = 1024 + 176,
2044 .hsync_end = 1024 + 176 + 5,
2045 .htotal = 1024 + 176 + 5 + 88,
2046 .vdisplay = 600,
2047 .vsync_start = 600 + 20,
2048 .vsync_end = 600 + 20 + 5,
2049 .vtotal = 600 + 20 + 5 + 25,
2050 .vrefresh = 60,
2051};
2052
2053static const struct panel_desc tpk_f10a_0102 = {
2054 .modes = &tpk_f10a_0102_mode,
2055 .num_modes = 1,
2056 .size = {
2057 .width = 223,
2058 .height = 125,
2059 },
2060};
2061
06a9dc65
MS		 2062static const struct display_timing urt_umsh_8596md_timing = {
2063 .pixelclock = { 33260000, 33260000, 33260000 },
2064 .hactive = { 800, 800, 800 },
2065 .hfront_porch = { 41, 41, 41 },
2066 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
2067 .hsync_len = { 71, 128, 128 },
2068 .vactive = { 480, 480, 480 },
2069 .vfront_porch = { 10, 10, 10 },
2070 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
2071 .vsync_len = { 2, 2, 2 },
2072 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
2073 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
2074};
2075
2076static const struct panel_desc urt_umsh_8596md_lvds = {
2077 .timings = &urt_umsh_8596md_timing,
2078 .num_timings = 1,
2079 .bpc = 6,
2080 .size = {
2081 .width = 152,
2082 .height = 91,
2083 },
2084 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2085};
2086
2087static const struct panel_desc urt_umsh_8596md_parallel = {
2088 .timings = &urt_umsh_8596md_timing,
2089 .num_timings = 1,
2090 .bpc = 6,
2091 .size = {
2092 .width = 152,
2093 .height = 91,
2094 },
2095 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2096};
2097
e4bac408
RG		 2098static const struct drm_display_mode winstar_wf35ltiacd_mode = {
2099 .clock = 6410,
2100 .hdisplay = 320,
2101 .hsync_start = 320 + 20,
2102 .hsync_end = 320 + 20 + 30,
2103 .htotal = 320 + 20 + 30 + 38,
2104 .vdisplay = 240,
2105 .vsync_start = 240 + 4,
2106 .vsync_end = 240 + 4 + 3,
2107 .vtotal = 240 + 4 + 3 + 15,
2108 .vrefresh = 60,
2109 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2110};
2111
2112static const struct panel_desc winstar_wf35ltiacd = {
2113 .modes = &winstar_wf35ltiacd_mode,
2114 .num_modes = 1,
2115 .bpc = 8,
2116 .size = {
2117 .width = 70,
2118 .height = 53,
2119 },
2120 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2121};
2122
280921de
TR		 2123static const struct of_device_id platform_of_match[] = {
2124 {
966fea78
YF		 2125 .compatible = "ampire,am-480272h3tmqw-t01h",
2126 .data = &ampire_am_480272h3tmqw_t01h,
2127 }, {
1c550fa1
PZ		 2128 .compatible = "ampire,am800480r3tmqwa1h",
2129 .data = &ampire_am800480r3tmqwa1h,
2130 }, {
280921de
TR		 2131 .compatible = "auo,b101aw03",
2132 .data = &auo_b101aw03,
a531bc3d
HL		 2133 }, {
2134 .compatible = "auo,b101ean01",
2135 .data = &auo_b101ean01,
dac746e0
RC		 2136 }, {
2137 .compatible = "auo,b101xtn01",
2138 .data = &auo_b101xtn01,
e35e305e
AK		 2139 }, {
2140 .compatible = "auo,b116xw03",
2141 .data = &auo_b116xw03,
3e51d609
AK		 2142 }, {
2143 .compatible = "auo,b133htn01",
2144 .data = &auo_b133htn01,
a333f7ad
SM		 2145 }, {
2146 .compatible = "auo,b133xtn01",
2147 .data = &auo_b133xtn01,
bccfaffb
LM		 2148 }, {
2149 .compatible = "auo,g070vvn01",
2150 .data = &auo_g070vvn01,
4451c287
CF		 2151 }, {
2152 .compatible = "auo,g104sn02",
2153 .data = &auo_g104sn02,
697035c6
LS		 2154 }, {
2155 .compatible = "auo,g133han01",
2156 .data = &auo_g133han01,
8c31f603
LS		 2157 }, {
2158 .compatible = "auo,g185han01",
2159 .data = &auo_g185han01,
70c0d5b7
LS		 2160 }, {
2161 .compatible = "auo,p320hvn03",
2162 .data = &auo_p320hvn03,
7ee933a1
HS		 2163 }, {
2164 .compatible = "auo,t215hvn01",
2165 .data = &auo_t215hvn01,
d47df633
PZ		 2166 }, {
2167 .compatible = "avic,tm070ddh03",
2168 .data = &avic_tm070ddh03,
cac1a411
CW		 2169 }, {
2170 .compatible = "boe,nv101wxmn51",
2171 .data = &boe_nv101wxmn51,
2cb35c80
RL		 2172 }, {
2173 .compatible = "chunghwa,claa070wp03xg",
2174 .data = &chunghwa_claa070wp03xg,
4c930757
SW		 2175 }, {
2176 .compatible = "chunghwa,claa101wa01a",
2177 .data = &chunghwa_claa101wa01a
280921de
TR		 2178 }, {
2179 .compatible = "chunghwa,claa101wb01",
2180 .data = &chunghwa_claa101wb01
26ab0065
SA		 2181 }, {
2182 .compatible = "edt,et057090dhu",
2183 .data = &edt_et057090dhu,
fff5de45
PZ		 2184 }, {
2185 .compatible = "edt,et070080dh6",
2186 .data = &edt_etm0700g0dh6,
2187 }, {
2188 .compatible = "edt,etm0700g0dh6",
2189 .data = &edt_etm0700g0dh6,
102932b0
BB		 2190 }, {
2191 .compatible = "foxlink,fl500wvr00-a0t",
2192 .data = &foxlink_fl500wvr00_a0t,
d435a2af
PZ		 2193 }, {
2194 .compatible = "giantplus,gpg482739qs5",
2195 .data = &giantplus_gpg482739qs5
a853205e
PZ		 2196 }, {
2197 .compatible = "hannstar,hsd070pww1",
2198 .data = &hannstar_hsd070pww1,
c0d607e5
EN		 2199 }, {
2200 .compatible = "hannstar,hsd100pxn1",
2201 .data = &hannstar_hsd100pxn1,
61ac0bf8
LS		 2202 }, {
2203 .compatible = "hit,tx23d38vm0caa",
2204 .data = &hitachi_tx23d38vm0caa
41bcceb4
NF		 2205 }, {
2206 .compatible = "innolux,at043tn24",
2207 .data = &innolux_at043tn24,
4fc24ab3
RB		 2208 }, {
2209 .compatible = "innolux,at070tn92",
2210 .data = &innolux_at070tn92,
1e29b840
MO		 2211 }, {
2212 .compatible ="innolux,g101ice-l01",
2213 .data = &innolux_g101ice_l01
d731f661
LS		 2214 }, {
2215 .compatible ="innolux,g121i1-l01",
2216 .data = &innolux_g121i1_l01
f8fa17ba
AB		 2217 }, {
2218 .compatible = "innolux,g121x1-l03",
2219 .data = &innolux_g121x1_l03,
0a2288c0
TR		 2220 }, {
2221 .compatible = "innolux,n116bge",
2222 .data = &innolux_n116bge,
ea44739d
AB		 2223 }, {
2224 .compatible = "innolux,n156bge-l21",
2225 .data = &innolux_n156bge_l21,
da50bd42 2226 }, {
2227 .compatible = "innolux,tv123wam",
2228 .data = &innolux_tv123wam,
bccac3f1
MG		 2229 }, {
2230 .compatible = "innolux,zj070na-01p",
2231 .data = &innolux_zj070na_01p,
8cfe8341
JT		 2232 }, {
2233 .compatible = "koe,tx31d200vm0baa",
2234 .data = &koe_tx31d200vm0baa,
8def22e5
LS		 2235 }, {
2236 .compatible = "kyo,tcg121xglp",
2237 .data = &kyo_tcg121xglp,
dd015002
HS		 2238 }, {
2239 .compatible = "lg,lb070wv8",
2240 .data = &lg_lb070wv8,
c5ece402
YY		 2241 }, {
2242 .compatible = "lg,lp079qx1-sp0v",
2243 .data = &lg_lp079qx1_sp0v,
0355dde2
YY		 2244 }, {
2245 .compatible = "lg,lp097qx1-spa1",
2246 .data = &lg_lp097qx1_spa1,
690d8fa7
JS		 2247 }, {
2248 .compatible = "lg,lp120up1",
2249 .data = &lg_lp120up1,
ec7c5653
TR		 2250 }, {
2251 .compatible = "lg,lp129qe",
2252 .data = &lg_lp129qe,
65c766ca
LM		 2253 }, {
2254 .compatible = "mitsubishi,aa070mc01-ca1",
2255 .data = &mitsubishi_aa070mc01,
01bacc13
LS		 2256 }, {
2257 .compatible = "nec,nl12880bc20-05",
2258 .data = &nec_nl12880bc20_05,
c6e87f91 2259 }, {
2260 .compatible = "nec,nl4827hc19-05b",
2261 .data = &nec_nl4827hc19_05b,
e6c2f066
MR		 2262 }, {
2263 .compatible = "netron-dy,e231732",
2264 .data = &netron_dy_e231732,
4177fa66
LS		 2265 }, {
2266 .compatible = "nlt,nl192108ac18-02d",
2267 .data = &nlt_nl192108ac18_02d,
05ec0e45
FL		 2268 }, {
2269 .compatible = "nvd,9128",
2270 .data = &nvd_9128,
a99fb626
GB		 2271 }, {
2272 .compatible = "okaya,rs800480t-7x0gp",
2273 .data = &okaya_rs800480t_7x0gp,
cf5c9e6d
MR		 2274 }, {
2275 .compatible = "olimex,lcd-olinuxino-43-ts",
2276 .data = &olimex_lcd_olinuxino_43ts,
e8b6f561
EA		 2277 }, {
2278 .compatible = "ontat,yx700wv03",
2279 .data = &ontat_yx700wv03,
725c9d40
PZ		 2280 }, {
2281 .compatible = "ortustech,com43h4m85ulc",
2282 .data = &ortustech_com43h4m85ulc,
d2a6f0f5
JW		 2283 }, {
2284 .compatible = "qiaodian,qd43003c0-40",
2285 .data = &qd43003c0_40,
0330eaf3
YY		 2286 }, {
2287 .compatible = "samsung,lsn122dl01-c01",
2288 .data = &samsung_lsn122dl01_c01,
6d54e3d2
MD		 2289 }, {
2290 .compatible = "samsung,ltn101nt05",
2291 .data = &samsung_ltn101nt05,
0c934306
SM		 2292 }, {
2293 .compatible = "samsung,ltn140at29-301",
2294 .data = &samsung_ltn140at29_301,
592aa02b
JC		 2295 }, {
2296 .compatible = "sharp,lq101k1ly04",
2297 .data = &sharp_lq101k1ly04,
739c7de9
YY		 2298 }, {
2299 .compatible = "sharp,lq123p1jx31",
2300 .data = &sharp_lq123p1jx31,
0f9cdd74
GL		 2301 }, {
2302 .compatible = "sharp,lq150x1lg11",
2303 .data = &sharp_lq150x1lg11,
9c6615bc
BB		 2304 }, {
2305 .compatible = "shelly,sca07010-bfn-lnn",
2306 .data = &shelly_sca07010_bfn_lnn,
9bb34c4c
DA		 2307 }, {
2308 .compatible = "starry,kr122ea0sra",
2309 .data = &starry_kr122ea0sra,
adb973ef
GB		 2310 }, {
2311 .compatible = "tianma,tm070jdhg30",
2312 .data = &tianma_tm070jdhg30,
870a0b12
LM		 2313 }, {
2314 .compatible = "tianma,tm070rvhg71",
2315 .data = &tianma_tm070rvhg71,
06e733e4
LS		 2316 }, {
2317 .compatible = "toshiba,lt089ac29000",
2318 .data = &toshiba_lt089ac29000,
227e4f40
BD		 2319 }, {
2320 .compatible = "tpk,f07a-0102",
2321 .data = &tpk_f07a_0102,
2322 }, {
2323 .compatible = "tpk,f10a-0102",
2324 .data = &tpk_f10a_0102,
06a9dc65
MS		 2325 }, {
2326 .compatible = "urt,umsh-8596md-t",
2327 .data = &urt_umsh_8596md_parallel,
2328 }, {
2329 .compatible = "urt,umsh-8596md-1t",
2330 .data = &urt_umsh_8596md_parallel,
2331 }, {
2332 .compatible = "urt,umsh-8596md-7t",
2333 .data = &urt_umsh_8596md_parallel,
2334 }, {
2335 .compatible = "urt,umsh-8596md-11t",
2336 .data = &urt_umsh_8596md_lvds,
2337 }, {
2338 .compatible = "urt,umsh-8596md-19t",
2339 .data = &urt_umsh_8596md_lvds,
2340 }, {
2341 .compatible = "urt,umsh-8596md-20t",
2342 .data = &urt_umsh_8596md_parallel,
e4bac408
RG		 2343 }, {
2344 .compatible = "winstar,wf35ltiacd",
2345 .data = &winstar_wf35ltiacd,
280921de
TR		 2346 }, {
2347 /* sentinel */
2348 }
2349};
2350MODULE_DEVICE_TABLE(of, platform_of_match);
2351
2352static int panel_simple_platform_probe(struct platform_device *pdev)
2353{
2354 const struct of_device_id *id;
2355
2356 id = of_match_node(platform_of_match, pdev->dev.of_node);
2357 if (!id)
2358 return -ENODEV;
2359
2360 return panel_simple_probe(&pdev->dev, id->data);
2361}
2362
2363static int panel_simple_platform_remove(struct platform_device *pdev)
2364{
2365 return panel_simple_remove(&pdev->dev);
2366}
2367
d02fd93e
TR		 2368static void panel_simple_platform_shutdown(struct platform_device *pdev)
2369{
2370 panel_simple_shutdown(&pdev->dev);
2371}
2372
280921de
TR		 2373static struct platform_driver panel_simple_platform_driver = {
2374 .driver = {
2375 .name = "panel-simple",
280921de
TR		 2376 .of_match_table = platform_of_match,
2377 },
2378 .probe = panel_simple_platform_probe,
2379 .remove = panel_simple_platform_remove,
d02fd93e 2380 .shutdown = panel_simple_platform_shutdown,
280921de
TR		 2381};
2382
210fcd9d
TR		 2383struct panel_desc_dsi {
2384 struct panel_desc desc;
2385
462658b8 2386 unsigned long flags;
210fcd9d
TR		 2387 enum mipi_dsi_pixel_format format;
2388 unsigned int lanes;
2389};
2390
d718d79e
TR		 2391static const struct drm_display_mode auo_b080uan01_mode = {
2392 .clock = 154500,
2393 .hdisplay = 1200,
2394 .hsync_start = 1200 + 62,
2395 .hsync_end = 1200 + 62 + 4,
2396 .htotal = 1200 + 62 + 4 + 62,
2397 .vdisplay = 1920,
2398 .vsync_start = 1920 + 9,
2399 .vsync_end = 1920 + 9 + 2,
2400 .vtotal = 1920 + 9 + 2 + 8,
2401 .vrefresh = 60,
2402};
2403
2404static const struct panel_desc_dsi auo_b080uan01 = {
2405 .desc = {
2406 .modes = &auo_b080uan01_mode,
2407 .num_modes = 1,
2408 .bpc = 8,
2409 .size = {
2410 .width = 108,
2411 .height = 272,
2412 },
2413 },
2414 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
2415 .format = MIPI_DSI_FMT_RGB888,
2416 .lanes = 4,
2417};
2418
c8521969
CZ		 2419static const struct drm_display_mode boe_tv080wum_nl0_mode = {
2420 .clock = 160000,
2421 .hdisplay = 1200,
2422 .hsync_start = 1200 + 120,
2423 .hsync_end = 1200 + 120 + 20,
2424 .htotal = 1200 + 120 + 20 + 21,
2425 .vdisplay = 1920,
2426 .vsync_start = 1920 + 21,
2427 .vsync_end = 1920 + 21 + 3,
2428 .vtotal = 1920 + 21 + 3 + 18,
2429 .vrefresh = 60,
2430 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2431};
2432
2433static const struct panel_desc_dsi boe_tv080wum_nl0 = {
2434 .desc = {
2435 .modes = &boe_tv080wum_nl0_mode,
2436 .num_modes = 1,
2437 .size = {
2438 .width = 107,
2439 .height = 172,
2440 },
2441 },
2442 .flags = MIPI_DSI_MODE_VIDEO |
2443 MIPI_DSI_MODE_VIDEO_BURST |
2444 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
2445 .format = MIPI_DSI_FMT_RGB888,
2446 .lanes = 4,
2447};
2448
712ac1ba
AC		 2449static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
2450 .clock = 71000,
2451 .hdisplay = 800,
2452 .hsync_start = 800 + 32,
2453 .hsync_end = 800 + 32 + 1,
2454 .htotal = 800 + 32 + 1 + 57,
2455 .vdisplay = 1280,
2456 .vsync_start = 1280 + 28,
2457 .vsync_end = 1280 + 28 + 1,
2458 .vtotal = 1280 + 28 + 1 + 14,
2459 .vrefresh = 60,
2460};
2461
2462static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
2463 .desc = {
2464 .modes = &lg_ld070wx3_sl01_mode,
2465 .num_modes = 1,
d7a839cd 2466 .bpc = 8,
712ac1ba
AC		 2467 .size = {
2468 .width = 94,
2469 .height = 151,
2470 },
2471 },
5e4cc278 2472 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
712ac1ba
AC		 2473 .format = MIPI_DSI_FMT_RGB888,
2474 .lanes = 4,
2475};
2476
499ce85a
AC		 2477static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
2478 .clock = 67000,
2479 .hdisplay = 720,
2480 .hsync_start = 720 + 12,
2481 .hsync_end = 720 + 12 + 4,
2482 .htotal = 720 + 12 + 4 + 112,
2483 .vdisplay = 1280,
2484 .vsync_start = 1280 + 8,
2485 .vsync_end = 1280 + 8 + 4,
2486 .vtotal = 1280 + 8 + 4 + 12,
2487 .vrefresh = 60,
2488};
2489
2490static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
2491 .desc = {
2492 .modes = &lg_lh500wx1_sd03_mode,
2493 .num_modes = 1,
d7a839cd 2494 .bpc = 8,
499ce85a
AC		 2495 .size = {
2496 .width = 62,
2497 .height = 110,
2498 },
2499 },
2500 .flags = MIPI_DSI_MODE_VIDEO,
2501 .format = MIPI_DSI_FMT_RGB888,
2502 .lanes = 4,
2503};
2504
280921de
TR		 2505static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
2506 .clock = 157200,
2507 .hdisplay = 1920,
2508 .hsync_start = 1920 + 154,
2509 .hsync_end = 1920 + 154 + 16,
2510 .htotal = 1920 + 154 + 16 + 32,
2511 .vdisplay = 1200,
2512 .vsync_start = 1200 + 17,
2513 .vsync_end = 1200 + 17 + 2,
2514 .vtotal = 1200 + 17 + 2 + 16,
2515 .vrefresh = 60,
2516};
2517
210fcd9d
TR		 2518static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
2519 .desc = {
2520 .modes = &panasonic_vvx10f004b00_mode,
2521 .num_modes = 1,
d7a839cd 2522 .bpc = 8,
210fcd9d
TR		 2523 .size = {
2524 .width = 217,
2525 .height = 136,
2526 },
280921de 2527 },
5e4cc278
AC		 2528 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
2529 MIPI_DSI_CLOCK_NON_CONTINUOUS,
210fcd9d
TR		 2530 .format = MIPI_DSI_FMT_RGB888,
2531 .lanes = 4,
2532};
2533
2534static const struct of_device_id dsi_of_match[] = {
2535 {
d718d79e
TR		 2536 .compatible = "auo,b080uan01",
2537 .data = &auo_b080uan01
c8521969
CZ		 2538 }, {
2539 .compatible = "boe,tv080wum-nl0",
2540 .data = &boe_tv080wum_nl0
d718d79e 2541 }, {
712ac1ba
AC		 2542 .compatible = "lg,ld070wx3-sl01",
2543 .data = &lg_ld070wx3_sl01
2544 }, {
499ce85a
AC		 2545 .compatible = "lg,lh500wx1-sd03",
2546 .data = &lg_lh500wx1_sd03
2547 }, {
210fcd9d
TR		 2548 .compatible = "panasonic,vvx10f004b00",
2549 .data = &panasonic_vvx10f004b00
2550 }, {
2551 /* sentinel */
2552 }
2553};
2554MODULE_DEVICE_TABLE(of, dsi_of_match);
2555
2556static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
2557{
2558 const struct panel_desc_dsi *desc;
2559 const struct of_device_id *id;
2560 int err;
2561
2562 id = of_match_node(dsi_of_match, dsi->dev.of_node);
2563 if (!id)
2564 return -ENODEV;
2565
2566 desc = id->data;
2567
2568 err = panel_simple_probe(&dsi->dev, &desc->desc);
2569 if (err < 0)
2570 return err;
2571
462658b8 2572 dsi->mode_flags = desc->flags;
210fcd9d
TR		 2573 dsi->format = desc->format;
2574 dsi->lanes = desc->lanes;
2575
2576 return mipi_dsi_attach(dsi);
2577}
2578
2579static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
2580{
2581 int err;
2582
2583 err = mipi_dsi_detach(dsi);
2584 if (err < 0)
2585 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
2586
2587 return panel_simple_remove(&dsi->dev);
2588}
2589
d02fd93e
TR		 2590static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
2591{
2592 panel_simple_shutdown(&dsi->dev);
2593}
2594
210fcd9d
TR		 2595static struct mipi_dsi_driver panel_simple_dsi_driver = {
2596 .driver = {
2597 .name = "panel-simple-dsi",
210fcd9d
TR		 2598 .of_match_table = dsi_of_match,
2599 },
2600 .probe = panel_simple_dsi_probe,
2601 .remove = panel_simple_dsi_remove,
d02fd93e 2602 .shutdown = panel_simple_dsi_shutdown,
280921de
TR		 2603};
2604
2605static int __init panel_simple_init(void)
2606{
210fcd9d
TR		 2607 int err;
2608
2609 err = platform_driver_register(&panel_simple_platform_driver);
2610 if (err < 0)
2611 return err;
2612
2613 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
2614 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
2615 if (err < 0)
2616 return err;
2617 }
2618
2619 return 0;
280921de
TR		 2620}
2621module_init(panel_simple_init);
2622
2623static void __exit panel_simple_exit(void)
2624{
210fcd9d
TR		 2625 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
2626 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
2627
280921de
TR		 2628 platform_driver_unregister(&panel_simple_platform_driver);
2629}
2630module_exit(panel_simple_exit);
2631
2632MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
2633MODULE_DESCRIPTION("DRM Driver for Simple Panels");
2634MODULE_LICENSE("GPL and additional rights");
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