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UBUNTU: Ubuntu-5.0.0-29.31
[mirror_ubuntu-disco-kernel.git] / drivers / gpu / drm / panel / panel-simple.c
CommitLineData
280921de
TR		 1/*
2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24#include <linux/backlight.h>
cfdf0549 25#include <linux/gpio/consumer.h>
280921de 26#include <linux/module.h>
280921de
TR		 27#include <linux/of_platform.h>
28#include <linux/platform_device.h>
29#include <linux/regulator/consumer.h>
30
31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
210fcd9d 33#include <drm/drm_mipi_dsi.h>
280921de
TR		 34#include <drm/drm_panel.h>
35
a5d3e625
PZ		 36#include <video/display_timing.h>
37#include <video/videomode.h>
38
280921de
TR		 39struct panel_desc {
40 const struct drm_display_mode *modes;
41 unsigned int num_modes;
a5d3e625
PZ		 42 const struct display_timing *timings;
43 unsigned int num_timings;
280921de 44
0208d511
SM		 45 unsigned int bpc;
46
85533e3b
UÖ		 47 /**
48 * @width: width (in millimeters) of the panel's active display area
49 * @height: height (in millimeters) of the panel's active display area
50 */
280921de
TR		 51 struct {
52 unsigned int width;
53 unsigned int height;
54 } size;
f673c37e
AK		 55
56 /**
57 * @prepare: the time (in milliseconds) that it takes for the panel to
58 * become ready and start receiving video data
2ed3e951
DA		 59 * @hpd_absent_delay: Add this to the prepare delay if we know Hot
60 * Plug Detect isn't used.
f673c37e
AK		 61 * @enable: the time (in milliseconds) that it takes for the panel to
62 * display the first valid frame after starting to receive
63 * video data
64 * @disable: the time (in milliseconds) that it takes for the panel to
65 * turn the display off (no content is visible)
66 * @unprepare: the time (in milliseconds) that it takes for the panel
67 * to power itself down completely
68 */
69 struct {
70 unsigned int prepare;
2ed3e951 71 unsigned int hpd_absent_delay;
f673c37e
AK		 72 unsigned int enable;
73 unsigned int disable;
74 unsigned int unprepare;
75 } delay;
795f7ab3
BB		 76
77 u32 bus_format;
f0aa0838 78 u32 bus_flags;
280921de
TR		 79};
80
280921de
TR		 81struct panel_simple {
82 struct drm_panel base;
613a633e 83 bool prepared;
280921de 84 bool enabled;
2ed3e951 85 bool no_hpd;
280921de
TR		 86
87 const struct panel_desc *desc;
88
89 struct backlight_device *backlight;
90 struct regulator *supply;
91 struct i2c_adapter *ddc;
92
cfdf0549 93 struct gpio_desc *enable_gpio;
280921de
TR		 94};
95
96static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
97{
98 return container_of(panel, struct panel_simple, base);
99}
100
101static int panel_simple_get_fixed_modes(struct panel_simple *panel)
102{
103 struct drm_connector *connector = panel->base.connector;
104 struct drm_device *drm = panel->base.drm;
105 struct drm_display_mode *mode;
106 unsigned int i, num = 0;
107
108 if (!panel->desc)
109 return 0;
110
a5d3e625
PZ		 111 for (i = 0; i < panel->desc->num_timings; i++) {
112 const struct display_timing *dt = &panel->desc->timings[i];
113 struct videomode vm;
114
115 videomode_from_timing(dt, &vm);
116 mode = drm_mode_create(drm);
117 if (!mode) {
118 dev_err(drm->dev, "failed to add mode %ux%u\n",
119 dt->hactive.typ, dt->vactive.typ);
120 continue;
121 }
122
123 drm_display_mode_from_videomode(&vm, mode);
cda55372
BB		 124
125 mode->type |= DRM_MODE_TYPE_DRIVER;
126
230c5b44 127 if (panel->desc->num_timings == 1)
cda55372
BB		 128 mode->type |= DRM_MODE_TYPE_PREFERRED;
129
a5d3e625
PZ		 130 drm_mode_probed_add(connector, mode);
131 num++;
132 }
133
280921de
TR		 134 for (i = 0; i < panel->desc->num_modes; i++) {
135 const struct drm_display_mode *m = &panel->desc->modes[i];
136
137 mode = drm_mode_duplicate(drm, m);
138 if (!mode) {
139 dev_err(drm->dev, "failed to add mode %ux%u@%u\n",
140 m->hdisplay, m->vdisplay, m->vrefresh);
141 continue;
142 }
143
cda55372
BB		 144 mode->type |= DRM_MODE_TYPE_DRIVER;
145
146 if (panel->desc->num_modes == 1)
147 mode->type |= DRM_MODE_TYPE_PREFERRED;
148
280921de
TR		 149 drm_mode_set_name(mode);
150
151 drm_mode_probed_add(connector, mode);
152 num++;
153 }
154
0208d511 155 connector->display_info.bpc = panel->desc->bpc;
280921de
TR		 156 connector->display_info.width_mm = panel->desc->size.width;
157 connector->display_info.height_mm = panel->desc->size.height;
795f7ab3
BB		 158 if (panel->desc->bus_format)
159 drm_display_info_set_bus_formats(&connector->display_info,
160 &panel->desc->bus_format, 1);
f0aa0838 161 connector->display_info.bus_flags = panel->desc->bus_flags;
280921de
TR		 162
163 return num;
164}
165
166static int panel_simple_disable(struct drm_panel *panel)
167{
168 struct panel_simple *p = to_panel_simple(panel);
169
170 if (!p->enabled)
171 return 0;
172
173 if (p->backlight) {
174 p->backlight->props.power = FB_BLANK_POWERDOWN;
e4aa3428 175 p->backlight->props.state |= BL_CORE_FBBLANK;
280921de
TR		 176 backlight_update_status(p->backlight);
177 }
178
f673c37e
AK		 179 if (p->desc->delay.disable)
180 msleep(p->desc->delay.disable);
181
280921de
TR		 182 p->enabled = false;
183
184 return 0;
185}
186
c0e1d170
AK		 187static int panel_simple_unprepare(struct drm_panel *panel)
188{
613a633e
AK		 189 struct panel_simple *p = to_panel_simple(panel);
190
191 if (!p->prepared)
192 return 0;
193
756b918d 194 gpiod_set_value_cansleep(p->enable_gpio, 0);
613a633e
AK		 195
196 regulator_disable(p->supply);
197
f673c37e
AK		 198 if (p->desc->delay.unprepare)
199 msleep(p->desc->delay.unprepare);
200
613a633e 201 p->prepared = false;
c0e1d170 202
c0e1d170
AK		 203 return 0;
204}
205
613a633e 206static int panel_simple_prepare(struct drm_panel *panel)
280921de
TR		 207{
208 struct panel_simple *p = to_panel_simple(panel);
2ed3e951 209 unsigned int delay;
280921de
TR		 210 int err;
211
613a633e 212 if (p->prepared)
280921de
TR		 213 return 0;
214
215 err = regulator_enable(p->supply);
216 if (err < 0) {
217 dev_err(panel->dev, "failed to enable supply: %d\n", err);
218 return err;
219 }
220
756b918d 221 gpiod_set_value_cansleep(p->enable_gpio, 1);
280921de 222
2ed3e951
DA		 223 delay = p->desc->delay.prepare;
224 if (p->no_hpd)
225 delay += p->desc->delay.hpd_absent_delay;
226 if (delay)
227 msleep(delay);
f673c37e 228
613a633e
AK		 229 p->prepared = true;
230
231 return 0;
232}
233
234static int panel_simple_enable(struct drm_panel *panel)
235{
236 struct panel_simple *p = to_panel_simple(panel);
237
238 if (p->enabled)
239 return 0;
240
f673c37e
AK		 241 if (p->desc->delay.enable)
242 msleep(p->desc->delay.enable);
243
280921de 244 if (p->backlight) {
e4aa3428 245 p->backlight->props.state &= ~BL_CORE_FBBLANK;
280921de
TR		 246 p->backlight->props.power = FB_BLANK_UNBLANK;
247 backlight_update_status(p->backlight);
248 }
249
250 p->enabled = true;
251
252 return 0;
253}
254
255static int panel_simple_get_modes(struct drm_panel *panel)
256{
257 struct panel_simple *p = to_panel_simple(panel);
258 int num = 0;
259
260 /* probe EDID if a DDC bus is available */
261 if (p->ddc) {
262 struct edid *edid = drm_get_edid(panel->connector, p->ddc);
c555f023 263 drm_connector_update_edid_property(panel->connector, edid);
280921de
TR		 264 if (edid) {
265 num += drm_add_edid_modes(panel->connector, edid);
266 kfree(edid);
267 }
268 }
269
270 /* add hard-coded panel modes */
271 num += panel_simple_get_fixed_modes(p);
272
273 return num;
274}
275
a5d3e625
PZ		 276static int panel_simple_get_timings(struct drm_panel *panel,
277 unsigned int num_timings,
278 struct display_timing *timings)
279{
280 struct panel_simple *p = to_panel_simple(panel);
281 unsigned int i;
282
283 if (p->desc->num_timings < num_timings)
284 num_timings = p->desc->num_timings;
285
286 if (timings)
287 for (i = 0; i < num_timings; i++)
288 timings[i] = p->desc->timings[i];
289
290 return p->desc->num_timings;
291}
292
280921de
TR		 293static const struct drm_panel_funcs panel_simple_funcs = {
294 .disable = panel_simple_disable,
c0e1d170
AK		 295 .unprepare = panel_simple_unprepare,
296 .prepare = panel_simple_prepare,
280921de
TR		 297 .enable = panel_simple_enable,
298 .get_modes = panel_simple_get_modes,
a5d3e625 299 .get_timings = panel_simple_get_timings,
280921de
TR		 300};
301
302static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
303{
304 struct device_node *backlight, *ddc;
305 struct panel_simple *panel;
280921de
TR		 306 int err;
307
308 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
309 if (!panel)
310 return -ENOMEM;
311
312 panel->enabled = false;
613a633e 313 panel->prepared = false;
280921de
TR		 314 panel->desc = desc;
315
2ed3e951
DA		 316 panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd");
317
280921de
TR		 318 panel->supply = devm_regulator_get(dev, "power");
319 if (IS_ERR(panel->supply))
320 return PTR_ERR(panel->supply);
321
a61400d8
AC		 322 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
323 GPIOD_OUT_LOW);
cfdf0549
AC		 324 if (IS_ERR(panel->enable_gpio)) {
325 err = PTR_ERR(panel->enable_gpio);
b8e93807
FE		 326 if (err != -EPROBE_DEFER)
327 dev_err(dev, "failed to request GPIO: %d\n", err);
9746c619
AC		 328 return err;
329 }
280921de 330
280921de
TR		 331 backlight = of_parse_phandle(dev->of_node, "backlight", 0);
332 if (backlight) {
333 panel->backlight = of_find_backlight_by_node(backlight);
334 of_node_put(backlight);
335
cfdf0549
AC		 336 if (!panel->backlight)
337 return -EPROBE_DEFER;
280921de
TR		 338 }
339
340 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
341 if (ddc) {
342 panel->ddc = of_find_i2c_adapter_by_node(ddc);
343 of_node_put(ddc);
344
345 if (!panel->ddc) {
346 err = -EPROBE_DEFER;
347 goto free_backlight;
348 }
349 }
350
351 drm_panel_init(&panel->base);
352 panel->base.dev = dev;
353 panel->base.funcs = &panel_simple_funcs;
354
355 err = drm_panel_add(&panel->base);
356 if (err < 0)
357 goto free_ddc;
358
359 dev_set_drvdata(dev, panel);
360
361 return 0;
362
363free_ddc:
364 if (panel->ddc)
365 put_device(&panel->ddc->dev);
366free_backlight:
367 if (panel->backlight)
368 put_device(&panel->backlight->dev);
280921de
TR		 369
370 return err;
371}
372
373static int panel_simple_remove(struct device *dev)
374{
375 struct panel_simple *panel = dev_get_drvdata(dev);
376
280921de
TR		 377 drm_panel_remove(&panel->base);
378
379 panel_simple_disable(&panel->base);
f3621a8e 380 panel_simple_unprepare(&panel->base);
280921de
TR		 381
382 if (panel->ddc)
383 put_device(&panel->ddc->dev);
384
385 if (panel->backlight)
386 put_device(&panel->backlight->dev);
387
280921de
TR		 388 return 0;
389}
390
d02fd93e
TR		 391static void panel_simple_shutdown(struct device *dev)
392{
393 struct panel_simple *panel = dev_get_drvdata(dev);
394
395 panel_simple_disable(&panel->base);
f3621a8e 396 panel_simple_unprepare(&panel->base);
d02fd93e
TR		 397}
398
966fea78
YF		 399static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
400 .clock = 9000,
401 .hdisplay = 480,
402 .hsync_start = 480 + 2,
403 .hsync_end = 480 + 2 + 41,
404 .htotal = 480 + 2 + 41 + 2,
405 .vdisplay = 272,
406 .vsync_start = 272 + 2,
407 .vsync_end = 272 + 2 + 10,
408 .vtotal = 272 + 2 + 10 + 2,
409 .vrefresh = 60,
410 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
411};
412
413static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
414 .modes = &ampire_am_480272h3tmqw_t01h_mode,
415 .num_modes = 1,
416 .bpc = 8,
417 .size = {
418 .width = 105,
419 .height = 67,
420 },
421 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
422};
423
1c550fa1
PZ		 424static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
425 .clock = 33333,
426 .hdisplay = 800,
427 .hsync_start = 800 + 0,
428 .hsync_end = 800 + 0 + 255,
429 .htotal = 800 + 0 + 255 + 0,
430 .vdisplay = 480,
431 .vsync_start = 480 + 2,
432 .vsync_end = 480 + 2 + 45,
433 .vtotal = 480 + 2 + 45 + 0,
434 .vrefresh = 60,
435 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
436};
437
438static const struct panel_desc ampire_am800480r3tmqwa1h = {
439 .modes = &ampire_am800480r3tmqwa1h_mode,
440 .num_modes = 1,
441 .bpc = 6,
442 .size = {
443 .width = 152,
444 .height = 91,
445 },
446 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
447};
448
280921de
TR		 449static const struct drm_display_mode auo_b101aw03_mode = {
450 .clock = 51450,
451 .hdisplay = 1024,
452 .hsync_start = 1024 + 156,
453 .hsync_end = 1024 + 156 + 8,
454 .htotal = 1024 + 156 + 8 + 156,
455 .vdisplay = 600,
456 .vsync_start = 600 + 16,
457 .vsync_end = 600 + 16 + 6,
458 .vtotal = 600 + 16 + 6 + 16,
459 .vrefresh = 60,
460};
461
462static const struct panel_desc auo_b101aw03 = {
463 .modes = &auo_b101aw03_mode,
464 .num_modes = 1,
0208d511 465 .bpc = 6,
280921de
TR		 466 .size = {
467 .width = 223,
468 .height = 125,
469 },
470};
471
a531bc3d
HL		 472static const struct drm_display_mode auo_b101ean01_mode = {
473 .clock = 72500,
474 .hdisplay = 1280,
475 .hsync_start = 1280 + 119,
476 .hsync_end = 1280 + 119 + 32,
477 .htotal = 1280 + 119 + 32 + 21,
478 .vdisplay = 800,
479 .vsync_start = 800 + 4,
480 .vsync_end = 800 + 4 + 20,
481 .vtotal = 800 + 4 + 20 + 8,
482 .vrefresh = 60,
483};
484
485static const struct panel_desc auo_b101ean01 = {
486 .modes = &auo_b101ean01_mode,
487 .num_modes = 1,
488 .bpc = 6,
489 .size = {
490 .width = 217,
491 .height = 136,
492 },
493};
494
dac746e0
RC		 495static const struct drm_display_mode auo_b101xtn01_mode = {
496 .clock = 72000,
497 .hdisplay = 1366,
498 .hsync_start = 1366 + 20,
499 .hsync_end = 1366 + 20 + 70,
500 .htotal = 1366 + 20 + 70,
501 .vdisplay = 768,
502 .vsync_start = 768 + 14,
503 .vsync_end = 768 + 14 + 42,
504 .vtotal = 768 + 14 + 42,
505 .vrefresh = 60,
506 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
507};
508
509static const struct panel_desc auo_b101xtn01 = {
510 .modes = &auo_b101xtn01_mode,
511 .num_modes = 1,
512 .bpc = 6,
513 .size = {
514 .width = 223,
515 .height = 125,
516 },
517};
518
e35e305e
AK		 519static const struct drm_display_mode auo_b116xw03_mode = {
520 .clock = 70589,
521 .hdisplay = 1366,
522 .hsync_start = 1366 + 40,
523 .hsync_end = 1366 + 40 + 40,
524 .htotal = 1366 + 40 + 40 + 32,
525 .vdisplay = 768,
526 .vsync_start = 768 + 10,
527 .vsync_end = 768 + 10 + 12,
528 .vtotal = 768 + 10 + 12 + 6,
529 .vrefresh = 60,
530};
531
532static const struct panel_desc auo_b116xw03 = {
533 .modes = &auo_b116xw03_mode,
534 .num_modes = 1,
535 .bpc = 6,
536 .size = {
537 .width = 256,
538 .height = 144,
539 },
540};
541
a333f7ad
SM		 542static const struct drm_display_mode auo_b133xtn01_mode = {
543 .clock = 69500,
544 .hdisplay = 1366,
545 .hsync_start = 1366 + 48,
546 .hsync_end = 1366 + 48 + 32,
547 .htotal = 1366 + 48 + 32 + 20,
548 .vdisplay = 768,
549 .vsync_start = 768 + 3,
550 .vsync_end = 768 + 3 + 6,
551 .vtotal = 768 + 3 + 6 + 13,
552 .vrefresh = 60,
553};
554
555static const struct panel_desc auo_b133xtn01 = {
556 .modes = &auo_b133xtn01_mode,
557 .num_modes = 1,
0208d511 558 .bpc = 6,
a333f7ad
SM		 559 .size = {
560 .width = 293,
561 .height = 165,
562 },
563};
564
3e51d609
AK		 565static const struct drm_display_mode auo_b133htn01_mode = {
566 .clock = 150660,
567 .hdisplay = 1920,
568 .hsync_start = 1920 + 172,
569 .hsync_end = 1920 + 172 + 80,
570 .htotal = 1920 + 172 + 80 + 60,
571 .vdisplay = 1080,
572 .vsync_start = 1080 + 25,
573 .vsync_end = 1080 + 25 + 10,
574 .vtotal = 1080 + 25 + 10 + 10,
575 .vrefresh = 60,
576};
577
578static const struct panel_desc auo_b133htn01 = {
579 .modes = &auo_b133htn01_mode,
580 .num_modes = 1,
d7a839cd 581 .bpc = 6,
3e51d609
AK		 582 .size = {
583 .width = 293,
584 .height = 165,
585 },
586 .delay = {
587 .prepare = 105,
588 .enable = 20,
589 .unprepare = 50,
590 },
591};
592
bccfaffb
LM		 593static const struct display_timing auo_g070vvn01_timings = {
594 .pixelclock = { 33300000, 34209000, 45000000 },
595 .hactive = { 800, 800, 800 },
596 .hfront_porch = { 20, 40, 200 },
597 .hback_porch = { 87, 40, 1 },
598 .hsync_len = { 1, 48, 87 },
599 .vactive = { 480, 480, 480 },
600 .vfront_porch = { 5, 13, 200 },
601 .vback_porch = { 31, 31, 29 },
602 .vsync_len = { 1, 1, 3 },
603};
604
605static const struct panel_desc auo_g070vvn01 = {
606 .timings = &auo_g070vvn01_timings,
607 .num_timings = 1,
608 .bpc = 8,
609 .size = {
610 .width = 152,
611 .height = 91,
612 },
613 .delay = {
614 .prepare = 200,
615 .enable = 50,
616 .disable = 50,
617 .unprepare = 1000,
618 },
619};
620
4fb86404
AG		 621static const struct drm_display_mode auo_g101evn010_mode = {
622 .clock = 68930,
623 .hdisplay = 1280,
624 .hsync_start = 1280 + 82,
625 .hsync_end = 1280 + 82 + 2,
626 .htotal = 1280 + 82 + 2 + 84,
627 .vdisplay = 800,
628 .vsync_start = 800 + 8,
629 .vsync_end = 800 + 8 + 2,
630 .vtotal = 800 + 8 + 2 + 6,
631 .vrefresh = 60,
632};
633
634static const struct panel_desc auo_g101evn010 = {
635 .modes = &auo_g101evn010_mode,
636 .num_modes = 1,
637 .bpc = 6,
638 .size = {
639 .width = 216,
640 .height = 135,
641 },
642 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
643};
644
4451c287
CF		 645static const struct drm_display_mode auo_g104sn02_mode = {
646 .clock = 40000,
647 .hdisplay = 800,
648 .hsync_start = 800 + 40,
649 .hsync_end = 800 + 40 + 216,
650 .htotal = 800 + 40 + 216 + 128,
651 .vdisplay = 600,
652 .vsync_start = 600 + 10,
653 .vsync_end = 600 + 10 + 35,
654 .vtotal = 600 + 10 + 35 + 2,
655 .vrefresh = 60,
656};
657
658static const struct panel_desc auo_g104sn02 = {
659 .modes = &auo_g104sn02_mode,
660 .num_modes = 1,
661 .bpc = 8,
662 .size = {
663 .width = 211,
664 .height = 158,
665 },
666};
667
697035c6
LS		 668static const struct display_timing auo_g133han01_timings = {
669 .pixelclock = { 134000000, 141200000, 149000000 },
670 .hactive = { 1920, 1920, 1920 },
671 .hfront_porch = { 39, 58, 77 },
672 .hback_porch = { 59, 88, 117 },
673 .hsync_len = { 28, 42, 56 },
674 .vactive = { 1080, 1080, 1080 },
675 .vfront_porch = { 3, 8, 11 },
676 .vback_porch = { 5, 14, 19 },
677 .vsync_len = { 4, 14, 19 },
678};
679
680static const struct panel_desc auo_g133han01 = {
681 .timings = &auo_g133han01_timings,
682 .num_timings = 1,
683 .bpc = 8,
684 .size = {
685 .width = 293,
686 .height = 165,
687 },
688 .delay = {
689 .prepare = 200,
690 .enable = 50,
691 .disable = 50,
692 .unprepare = 1000,
693 },
694 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
695};
696
8c31f603
LS		 697static const struct display_timing auo_g185han01_timings = {
698 .pixelclock = { 120000000, 144000000, 175000000 },
699 .hactive = { 1920, 1920, 1920 },
700 .hfront_porch = { 18, 60, 74 },
701 .hback_porch = { 12, 44, 54 },
702 .hsync_len = { 10, 24, 32 },
703 .vactive = { 1080, 1080, 1080 },
704 .vfront_porch = { 6, 10, 40 },
705 .vback_porch = { 2, 5, 20 },
706 .vsync_len = { 2, 5, 20 },
707};
708
709static const struct panel_desc auo_g185han01 = {
710 .timings = &auo_g185han01_timings,
711 .num_timings = 1,
712 .bpc = 8,
713 .size = {
714 .width = 409,
715 .height = 230,
716 },
717 .delay = {
718 .prepare = 50,
719 .enable = 200,
720 .disable = 110,
721 .unprepare = 1000,
722 },
723 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
724};
725
70c0d5b7
LS		 726static const struct display_timing auo_p320hvn03_timings = {
727 .pixelclock = { 106000000, 148500000, 164000000 },
728 .hactive = { 1920, 1920, 1920 },
729 .hfront_porch = { 25, 50, 130 },
730 .hback_porch = { 25, 50, 130 },
731 .hsync_len = { 20, 40, 105 },
732 .vactive = { 1080, 1080, 1080 },
733 .vfront_porch = { 8, 17, 150 },
734 .vback_porch = { 8, 17, 150 },
735 .vsync_len = { 4, 11, 100 },
736};
737
738static const struct panel_desc auo_p320hvn03 = {
739 .timings = &auo_p320hvn03_timings,
740 .num_timings = 1,
741 .bpc = 8,
742 .size = {
743 .width = 698,
744 .height = 393,
745 },
746 .delay = {
747 .prepare = 1,
748 .enable = 450,
749 .unprepare = 500,
750 },
2554f154 751 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
70c0d5b7
LS		 752};
753
7ee933a1
HS		 754static const struct drm_display_mode auo_t215hvn01_mode = {
755 .clock = 148800,
756 .hdisplay = 1920,
757 .hsync_start = 1920 + 88,
758 .hsync_end = 1920 + 88 + 44,
759 .htotal = 1920 + 88 + 44 + 148,
760 .vdisplay = 1080,
761 .vsync_start = 1080 + 4,
762 .vsync_end = 1080 + 4 + 5,
763 .vtotal = 1080 + 4 + 5 + 36,
764 .vrefresh = 60,
765};
766
767static const struct panel_desc auo_t215hvn01 = {
768 .modes = &auo_t215hvn01_mode,
769 .num_modes = 1,
770 .bpc = 8,
771 .size = {
772 .width = 430,
773 .height = 270,
774 },
775 .delay = {
776 .disable = 5,
777 .unprepare = 1000,
778 }
779};
780
d47df633
PZ		 781static const struct drm_display_mode avic_tm070ddh03_mode = {
782 .clock = 51200,
783 .hdisplay = 1024,
784 .hsync_start = 1024 + 160,
785 .hsync_end = 1024 + 160 + 4,
786 .htotal = 1024 + 160 + 4 + 156,
787 .vdisplay = 600,
788 .vsync_start = 600 + 17,
789 .vsync_end = 600 + 17 + 1,
790 .vtotal = 600 + 17 + 1 + 17,
791 .vrefresh = 60,
792};
793
794static const struct panel_desc avic_tm070ddh03 = {
795 .modes = &avic_tm070ddh03_mode,
796 .num_modes = 1,
797 .bpc = 8,
798 .size = {
799 .width = 154,
800 .height = 90,
801 },
802 .delay = {
803 .prepare = 20,
804 .enable = 200,
805 .disable = 200,
806 },
807};
808
7ad8b41c
CYT		 809static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
810 .clock = 30000,
811 .hdisplay = 800,
812 .hsync_start = 800 + 40,
813 .hsync_end = 800 + 40 + 48,
814 .htotal = 800 + 40 + 48 + 40,
815 .vdisplay = 480,
816 .vsync_start = 480 + 13,
817 .vsync_end = 480 + 13 + 3,
818 .vtotal = 480 + 13 + 3 + 29,
819};
820
821static const struct panel_desc bananapi_s070wv20_ct16 = {
822 .modes = &bananapi_s070wv20_ct16_mode,
823 .num_modes = 1,
824 .bpc = 6,
825 .size = {
826 .width = 154,
827 .height = 86,
828 },
829};
830
ae8cf41b 831static const struct drm_display_mode boe_hv070wsa_mode = {
e077e2f5 832 .clock = 42105,
ae8cf41b 833 .hdisplay = 1024,
e077e2f5
AH		 834 .hsync_start = 1024 + 30,
835 .hsync_end = 1024 + 30 + 30,
836 .htotal = 1024 + 30 + 30 + 30,
ae8cf41b 837 .vdisplay = 600,
e077e2f5
AH		 838 .vsync_start = 600 + 10,
839 .vsync_end = 600 + 10 + 10,
840 .vtotal = 600 + 10 + 10 + 10,
ae8cf41b
AH		 841 .vrefresh = 60,
842};
843
844static const struct panel_desc boe_hv070wsa = {
845 .modes = &boe_hv070wsa_mode,
846 .num_modes = 1,
847 .size = {
848 .width = 154,
849 .height = 90,
850 },
851};
852
cac1a411
CW		 853static const struct drm_display_mode boe_nv101wxmn51_modes[] = {
854 {
855 .clock = 71900,
856 .hdisplay = 1280,
857 .hsync_start = 1280 + 48,
858 .hsync_end = 1280 + 48 + 32,
859 .htotal = 1280 + 48 + 32 + 80,
860 .vdisplay = 800,
861 .vsync_start = 800 + 3,
862 .vsync_end = 800 + 3 + 5,
863 .vtotal = 800 + 3 + 5 + 24,
864 .vrefresh = 60,
865 },
866 {
867 .clock = 57500,
868 .hdisplay = 1280,
869 .hsync_start = 1280 + 48,
870 .hsync_end = 1280 + 48 + 32,
871 .htotal = 1280 + 48 + 32 + 80,
872 .vdisplay = 800,
873 .vsync_start = 800 + 3,
874 .vsync_end = 800 + 3 + 5,
875 .vtotal = 800 + 3 + 5 + 24,
876 .vrefresh = 48,
877 },
878};
879
880static const struct panel_desc boe_nv101wxmn51 = {
881 .modes = boe_nv101wxmn51_modes,
882 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes),
883 .bpc = 8,
884 .size = {
885 .width = 217,
886 .height = 136,
887 },
888 .delay = {
889 .prepare = 210,
890 .enable = 50,
891 .unprepare = 160,
892 },
893};
894
e58edce6
GB		 895static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
896 .clock = 9000,
897 .hdisplay = 480,
898 .hsync_start = 480 + 5,
899 .hsync_end = 480 + 5 + 5,
900 .htotal = 480 + 5 + 5 + 40,
901 .vdisplay = 272,
902 .vsync_start = 272 + 8,
903 .vsync_end = 272 + 8 + 8,
904 .vtotal = 272 + 8 + 8 + 8,
905 .vrefresh = 60,
906 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
907};
908
909static const struct panel_desc cdtech_s043wq26h_ct7 = {
910 .modes = &cdtech_s043wq26h_ct7_mode,
911 .num_modes = 1,
912 .bpc = 8,
913 .size = {
914 .width = 95,
915 .height = 54,
916 },
917 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
918};
919
982f944e
GB		 920static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
921 .clock = 35000,
922 .hdisplay = 800,
923 .hsync_start = 800 + 40,
924 .hsync_end = 800 + 40 + 40,
925 .htotal = 800 + 40 + 40 + 48,
926 .vdisplay = 480,
927 .vsync_start = 480 + 29,
928 .vsync_end = 480 + 29 + 13,
929 .vtotal = 480 + 29 + 13 + 3,
930 .vrefresh = 60,
931 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
932};
933
934static const struct panel_desc cdtech_s070wv95_ct16 = {
935 .modes = &cdtech_s070wv95_ct16_mode,
936 .num_modes = 1,
937 .bpc = 8,
938 .size = {
939 .width = 154,
940 .height = 85,
941 },
942};
943
2cb35c80
RL		 944static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
945 .clock = 66770,
946 .hdisplay = 800,
947 .hsync_start = 800 + 49,
948 .hsync_end = 800 + 49 + 33,
949 .htotal = 800 + 49 + 33 + 17,
950 .vdisplay = 1280,
951 .vsync_start = 1280 + 1,
952 .vsync_end = 1280 + 1 + 7,
953 .vtotal = 1280 + 1 + 7 + 15,
954 .vrefresh = 60,
955 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
956};
957
958static const struct panel_desc chunghwa_claa070wp03xg = {
959 .modes = &chunghwa_claa070wp03xg_mode,
960 .num_modes = 1,
961 .bpc = 6,
962 .size = {
963 .width = 94,
964 .height = 150,
965 },
966};
967
4c930757
SW		 968static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
969 .clock = 72070,
970 .hdisplay = 1366,
971 .hsync_start = 1366 + 58,
972 .hsync_end = 1366 + 58 + 58,
973 .htotal = 1366 + 58 + 58 + 58,
974 .vdisplay = 768,
975 .vsync_start = 768 + 4,
976 .vsync_end = 768 + 4 + 4,
977 .vtotal = 768 + 4 + 4 + 4,
978 .vrefresh = 60,
979};
980
981static const struct panel_desc chunghwa_claa101wa01a = {
982 .modes = &chunghwa_claa101wa01a_mode,
983 .num_modes = 1,
0208d511 984 .bpc = 6,
4c930757
SW		 985 .size = {
986 .width = 220,
987 .height = 120,
988 },
989};
990
280921de
TR		 991static const struct drm_display_mode chunghwa_claa101wb01_mode = {
992 .clock = 69300,
993 .hdisplay = 1366,
994 .hsync_start = 1366 + 48,
995 .hsync_end = 1366 + 48 + 32,
996 .htotal = 1366 + 48 + 32 + 20,
997 .vdisplay = 768,
998 .vsync_start = 768 + 16,
999 .vsync_end = 768 + 16 + 8,
1000 .vtotal = 768 + 16 + 8 + 16,
1001 .vrefresh = 60,
1002};
1003
1004static const struct panel_desc chunghwa_claa101wb01 = {
1005 .modes = &chunghwa_claa101wb01_mode,
1006 .num_modes = 1,
0208d511 1007 .bpc = 6,
280921de
TR		 1008 .size = {
1009 .width = 223,
1010 .height = 125,
1011 },
1012};
1013
97ceb1fb
MV		 1014static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
1015 .clock = 33260,
1016 .hdisplay = 800,
1017 .hsync_start = 800 + 40,
1018 .hsync_end = 800 + 40 + 128,
1019 .htotal = 800 + 40 + 128 + 88,
1020 .vdisplay = 480,
1021 .vsync_start = 480 + 10,
1022 .vsync_end = 480 + 10 + 2,
1023 .vtotal = 480 + 10 + 2 + 33,
1024 .vrefresh = 60,
1025 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1026};
1027
1028static const struct panel_desc dataimage_scf0700c48ggu18 = {
1029 .modes = &dataimage_scf0700c48ggu18_mode,
1030 .num_modes = 1,
1031 .bpc = 8,
1032 .size = {
1033 .width = 152,
1034 .height = 91,
1035 },
1036 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1037 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
1038};
1039
0ca0c827
PZ		 1040static const struct display_timing dlc_dlc0700yzg_1_timing = {
1041 .pixelclock = { 45000000, 51200000, 57000000 },
1042 .hactive = { 1024, 1024, 1024 },
1043 .hfront_porch = { 100, 106, 113 },
1044 .hback_porch = { 100, 106, 113 },
1045 .hsync_len = { 100, 108, 114 },
1046 .vactive = { 600, 600, 600 },
1047 .vfront_porch = { 8, 11, 15 },
1048 .vback_porch = { 8, 11, 15 },
1049 .vsync_len = { 9, 13, 15 },
1050 .flags = DISPLAY_FLAGS_DE_HIGH,
1051};
1052
1053static const struct panel_desc dlc_dlc0700yzg_1 = {
1054 .timings = &dlc_dlc0700yzg_1_timing,
1055 .num_timings = 1,
1056 .bpc = 6,
1057 .size = {
1058 .width = 154,
1059 .height = 86,
1060 },
1061 .delay = {
1062 .prepare = 30,
1063 .enable = 200,
1064 .disable = 200,
1065 },
1066 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1067};
1068
6cbe7cd1
MF		 1069static const struct display_timing dlc_dlc1010gig_timing = {
1070 .pixelclock = { 68900000, 71100000, 73400000 },
1071 .hactive = { 1280, 1280, 1280 },
1072 .hfront_porch = { 43, 53, 63 },
1073 .hback_porch = { 43, 53, 63 },
1074 .hsync_len = { 44, 54, 64 },
1075 .vactive = { 800, 800, 800 },
1076 .vfront_porch = { 5, 8, 11 },
1077 .vback_porch = { 5, 8, 11 },
1078 .vsync_len = { 5, 7, 11 },
1079 .flags = DISPLAY_FLAGS_DE_HIGH,
1080};
1081
1082static const struct panel_desc dlc_dlc1010gig = {
1083 .timings = &dlc_dlc1010gig_timing,
1084 .num_timings = 1,
1085 .bpc = 8,
1086 .size = {
1087 .width = 216,
1088 .height = 135,
1089 },
1090 .delay = {
1091 .prepare = 60,
1092 .enable = 150,
1093 .disable = 100,
1094 .unprepare = 60,
1095 },
1096 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1097};
1098
26ab0065
SA		 1099static const struct drm_display_mode edt_et057090dhu_mode = {
1100 .clock = 25175,
1101 .hdisplay = 640,
1102 .hsync_start = 640 + 16,
1103 .hsync_end = 640 + 16 + 30,
1104 .htotal = 640 + 16 + 30 + 114,
1105 .vdisplay = 480,
1106 .vsync_start = 480 + 10,
1107 .vsync_end = 480 + 10 + 3,
1108 .vtotal = 480 + 10 + 3 + 32,
1109 .vrefresh = 60,
1110 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1111};
1112
1113static const struct panel_desc edt_et057090dhu = {
1114 .modes = &edt_et057090dhu_mode,
1115 .num_modes = 1,
0208d511 1116 .bpc = 6,
26ab0065
SA		 1117 .size = {
1118 .width = 115,
1119 .height = 86,
1120 },
eaeebffa
SA		 1121 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1122 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
26ab0065
SA		 1123};
1124
fff5de45
PZ		 1125static const struct drm_display_mode edt_etm0700g0dh6_mode = {
1126 .clock = 33260,
1127 .hdisplay = 800,
1128 .hsync_start = 800 + 40,
1129 .hsync_end = 800 + 40 + 128,
1130 .htotal = 800 + 40 + 128 + 88,
1131 .vdisplay = 480,
1132 .vsync_start = 480 + 10,
1133 .vsync_end = 480 + 10 + 2,
1134 .vtotal = 480 + 10 + 2 + 33,
1135 .vrefresh = 60,
1136 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1137};
1138
1139static const struct panel_desc edt_etm0700g0dh6 = {
1140 .modes = &edt_etm0700g0dh6_mode,
1141 .num_modes = 1,
0208d511 1142 .bpc = 6,
fff5de45
PZ		 1143 .size = {
1144 .width = 152,
1145 .height = 91,
1146 },
eaeebffa
SA		 1147 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1148 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
fff5de45
PZ		 1149};
1150
aa7e6455
JT		 1151static const struct panel_desc edt_etm0700g0bdh6 = {
1152 .modes = &edt_etm0700g0dh6_mode,
1153 .num_modes = 1,
1154 .bpc = 6,
1155 .size = {
1156 .width = 152,
1157 .height = 91,
1158 },
1159 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1160 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
1161};
1162
102932b0
BB		 1163static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
1164 .clock = 32260,
1165 .hdisplay = 800,
1166 .hsync_start = 800 + 168,
1167 .hsync_end = 800 + 168 + 64,
1168 .htotal = 800 + 168 + 64 + 88,
1169 .vdisplay = 480,
1170 .vsync_start = 480 + 37,
1171 .vsync_end = 480 + 37 + 2,
1172 .vtotal = 480 + 37 + 2 + 8,
1173 .vrefresh = 60,
1174};
1175
1176static const struct panel_desc foxlink_fl500wvr00_a0t = {
1177 .modes = &foxlink_fl500wvr00_a0t_mode,
1178 .num_modes = 1,
d7a839cd 1179 .bpc = 8,
102932b0
BB		 1180 .size = {
1181 .width = 108,
1182 .height = 65,
1183 },
bb276cb3 1184 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
102932b0
BB		 1185};
1186
d435a2af
PZ		 1187static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
1188 .clock = 9000,
1189 .hdisplay = 480,
1190 .hsync_start = 480 + 5,
1191 .hsync_end = 480 + 5 + 1,
1192 .htotal = 480 + 5 + 1 + 40,
1193 .vdisplay = 272,
1194 .vsync_start = 272 + 8,
1195 .vsync_end = 272 + 8 + 1,
1196 .vtotal = 272 + 8 + 1 + 8,
1197 .vrefresh = 60,
1198};
1199
1200static const struct panel_desc giantplus_gpg482739qs5 = {
1201 .modes = &giantplus_gpg482739qs5_mode,
1202 .num_modes = 1,
1203 .bpc = 8,
1204 .size = {
1205 .width = 95,
1206 .height = 54,
1207 },
33536a09 1208 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
d435a2af
PZ		 1209};
1210
ab07725a
PZ		 1211static const struct display_timing hannstar_hsd070pww1_timing = {
1212 .pixelclock = { 64300000, 71100000, 82000000 },
1213 .hactive = { 1280, 1280, 1280 },
1214 .hfront_porch = { 1, 1, 10 },
1215 .hback_porch = { 1, 1, 10 },
d901d2ba
PZ		 1216 /*
1217 * According to the data sheet, the minimum horizontal blanking interval
1218 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
1219 * minimum working horizontal blanking interval to be 60 clocks.
1220 */
1221 .hsync_len = { 58, 158, 661 },
ab07725a
PZ		 1222 .vactive = { 800, 800, 800 },
1223 .vfront_porch = { 1, 1, 10 },
1224 .vback_porch = { 1, 1, 10 },
1225 .vsync_len = { 1, 21, 203 },
1226 .flags = DISPLAY_FLAGS_DE_HIGH,
a853205e
PZ		 1227};
1228
1229static const struct panel_desc hannstar_hsd070pww1 = {
ab07725a
PZ		 1230 .timings = &hannstar_hsd070pww1_timing,
1231 .num_timings = 1,
a853205e
PZ		 1232 .bpc = 6,
1233 .size = {
1234 .width = 151,
1235 .height = 94,
1236 },
58d6a7bc 1237 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
a853205e
PZ		 1238};
1239
c0d607e5
EN		 1240static const struct display_timing hannstar_hsd100pxn1_timing = {
1241 .pixelclock = { 55000000, 65000000, 75000000 },
1242 .hactive = { 1024, 1024, 1024 },
1243 .hfront_porch = { 40, 40, 40 },
1244 .hback_porch = { 220, 220, 220 },
1245 .hsync_len = { 20, 60, 100 },
1246 .vactive = { 768, 768, 768 },
1247 .vfront_porch = { 7, 7, 7 },
1248 .vback_porch = { 21, 21, 21 },
1249 .vsync_len = { 10, 10, 10 },
1250 .flags = DISPLAY_FLAGS_DE_HIGH,
1251};
1252
1253static const struct panel_desc hannstar_hsd100pxn1 = {
1254 .timings = &hannstar_hsd100pxn1_timing,
1255 .num_timings = 1,
1256 .bpc = 6,
1257 .size = {
1258 .width = 203,
1259 .height = 152,
1260 },
4946b043 1261 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
c0d607e5
EN		 1262};
1263
61ac0bf8
LS		 1264static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
1265 .clock = 33333,
1266 .hdisplay = 800,
1267 .hsync_start = 800 + 85,
1268 .hsync_end = 800 + 85 + 86,
1269 .htotal = 800 + 85 + 86 + 85,
1270 .vdisplay = 480,
1271 .vsync_start = 480 + 16,
1272 .vsync_end = 480 + 16 + 13,
1273 .vtotal = 480 + 16 + 13 + 16,
1274 .vrefresh = 60,
1275};
1276
1277static const struct panel_desc hitachi_tx23d38vm0caa = {
1278 .modes = &hitachi_tx23d38vm0caa_mode,
1279 .num_modes = 1,
1280 .bpc = 6,
1281 .size = {
1282 .width = 195,
1283 .height = 117,
1284 },
6c684e3b
PZ		 1285 .delay = {
1286 .enable = 160,
1287 .disable = 160,
1288 },
61ac0bf8
LS		 1289};
1290
41bcceb4
NF		 1291static const struct drm_display_mode innolux_at043tn24_mode = {
1292 .clock = 9000,
1293 .hdisplay = 480,
1294 .hsync_start = 480 + 2,
1295 .hsync_end = 480 + 2 + 41,
1296 .htotal = 480 + 2 + 41 + 2,
1297 .vdisplay = 272,
1298 .vsync_start = 272 + 2,
a483159d
PZ		 1299 .vsync_end = 272 + 2 + 10,
1300 .vtotal = 272 + 2 + 10 + 2,
41bcceb4
NF		 1301 .vrefresh = 60,
1302 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1303};
1304
1305static const struct panel_desc innolux_at043tn24 = {
1306 .modes = &innolux_at043tn24_mode,
1307 .num_modes = 1,
1308 .bpc = 8,
1309 .size = {
1310 .width = 95,
1311 .height = 54,
1312 },
1313 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
6560279c 1314 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
41bcceb4
NF		 1315};
1316
4fc24ab3
RB		 1317static const struct drm_display_mode innolux_at070tn92_mode = {
1318 .clock = 33333,
1319 .hdisplay = 800,
1320 .hsync_start = 800 + 210,
1321 .hsync_end = 800 + 210 + 20,
1322 .htotal = 800 + 210 + 20 + 46,
1323 .vdisplay = 480,
1324 .vsync_start = 480 + 22,
1325 .vsync_end = 480 + 22 + 10,
1326 .vtotal = 480 + 22 + 23 + 10,
1327 .vrefresh = 60,
1328};
1329
1330static const struct panel_desc innolux_at070tn92 = {
1331 .modes = &innolux_at070tn92_mode,
1332 .num_modes = 1,
1333 .size = {
1334 .width = 154,
1335 .height = 86,
1336 },
1337 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1338};
1339
a5d2ade6
CF		 1340static const struct display_timing innolux_g070y2_l01_timing = {
1341 .pixelclock = { 28000000, 29500000, 32000000 },
1342 .hactive = { 800, 800, 800 },
1343 .hfront_porch = { 61, 91, 141 },
1344 .hback_porch = { 60, 90, 140 },
1345 .hsync_len = { 12, 12, 12 },
1346 .vactive = { 480, 480, 480 },
1347 .vfront_porch = { 4, 9, 30 },
1348 .vback_porch = { 4, 8, 28 },
1349 .vsync_len = { 2, 2, 2 },
1350 .flags = DISPLAY_FLAGS_DE_HIGH,
1351};
1352
1353static const struct panel_desc innolux_g070y2_l01 = {
1354 .timings = &innolux_g070y2_l01_timing,
1355 .num_timings = 1,
1356 .bpc = 6,
1357 .size = {
1358 .width = 152,
1359 .height = 91,
1360 },
1361 .delay = {
1362 .prepare = 10,
1363 .enable = 100,
1364 .disable = 100,
1365 .unprepare = 800,
1366 },
1367 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1368};
1369
1e29b840
MO		 1370static const struct display_timing innolux_g101ice_l01_timing = {
1371 .pixelclock = { 60400000, 71100000, 74700000 },
1372 .hactive = { 1280, 1280, 1280 },
1373 .hfront_porch = { 41, 80, 100 },
1374 .hback_porch = { 40, 79, 99 },
1375 .hsync_len = { 1, 1, 1 },
1376 .vactive = { 800, 800, 800 },
1377 .vfront_porch = { 5, 11, 14 },
1378 .vback_porch = { 4, 11, 14 },
1379 .vsync_len = { 1, 1, 1 },
1380 .flags = DISPLAY_FLAGS_DE_HIGH,
1381};
1382
1383static const struct panel_desc innolux_g101ice_l01 = {
1384 .timings = &innolux_g101ice_l01_timing,
1385 .num_timings = 1,
1386 .bpc = 8,
1387 .size = {
1388 .width = 217,
1389 .height = 135,
1390 },
1391 .delay = {
1392 .enable = 200,
1393 .disable = 200,
1394 },
1395 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1396};
1397
4ae13e48
LS		 1398static const struct display_timing innolux_g121i1_l01_timing = {
1399 .pixelclock = { 67450000, 71000000, 74550000 },
1400 .hactive = { 1280, 1280, 1280 },
1401 .hfront_porch = { 40, 80, 160 },
1402 .hback_porch = { 39, 79, 159 },
1403 .hsync_len = { 1, 1, 1 },
1404 .vactive = { 800, 800, 800 },
1405 .vfront_porch = { 5, 11, 100 },
1406 .vback_porch = { 4, 11, 99 },
1407 .vsync_len = { 1, 1, 1 },
d731f661
LS		 1408};
1409
1410static const struct panel_desc innolux_g121i1_l01 = {
4ae13e48
LS		 1411 .timings = &innolux_g121i1_l01_timing,
1412 .num_timings = 1,
d731f661
LS		 1413 .bpc = 6,
1414 .size = {
1415 .width = 261,
1416 .height = 163,
1417 },
4ae13e48
LS		 1418 .delay = {
1419 .enable = 200,
1420 .disable = 20,
1421 },
1422 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
d731f661
LS		 1423};
1424
f8fa17ba
AB		 1425static const struct drm_display_mode innolux_g121x1_l03_mode = {
1426 .clock = 65000,
1427 .hdisplay = 1024,
1428 .hsync_start = 1024 + 0,
1429 .hsync_end = 1024 + 1,
1430 .htotal = 1024 + 0 + 1 + 320,
1431 .vdisplay = 768,
1432 .vsync_start = 768 + 38,
1433 .vsync_end = 768 + 38 + 1,
1434 .vtotal = 768 + 38 + 1 + 0,
1435 .vrefresh = 60,
2e8c5eb9 1436 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
f8fa17ba
AB		 1437};
1438
1439static const struct panel_desc innolux_g121x1_l03 = {
1440 .modes = &innolux_g121x1_l03_mode,
1441 .num_modes = 1,
1442 .bpc = 6,
1443 .size = {
1444 .width = 246,
1445 .height = 185,
1446 },
1447 .delay = {
1448 .enable = 200,
1449 .unprepare = 200,
1450 .disable = 400,
1451 },
1452};
1453
0a2288c0 1454static const struct drm_display_mode innolux_n116bge_mode = {
7fe8c777 1455 .clock = 76420,
0a2288c0 1456 .hdisplay = 1366,
7fe8c777
DK		 1457 .hsync_start = 1366 + 136,
1458 .hsync_end = 1366 + 136 + 30,
1459 .htotal = 1366 + 136 + 30 + 60,
0a2288c0
TR		 1460 .vdisplay = 768,
1461 .vsync_start = 768 + 8,
7fe8c777
DK		 1462 .vsync_end = 768 + 8 + 12,
1463 .vtotal = 768 + 8 + 12 + 12,
0a2288c0
TR		 1464 .vrefresh = 60,
1465 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1466};
1467
1468static const struct panel_desc innolux_n116bge = {
1469 .modes = &innolux_n116bge_mode,
1470 .num_modes = 1,
1471 .bpc = 6,
1472 .size = {
1473 .width = 256,
1474 .height = 144,
1475 },
1476};
1477
ea44739d
AB		 1478static const struct drm_display_mode innolux_n156bge_l21_mode = {
1479 .clock = 69300,
1480 .hdisplay = 1366,
1481 .hsync_start = 1366 + 16,
1482 .hsync_end = 1366 + 16 + 34,
1483 .htotal = 1366 + 16 + 34 + 50,
1484 .vdisplay = 768,
1485 .vsync_start = 768 + 2,
1486 .vsync_end = 768 + 2 + 6,
1487 .vtotal = 768 + 2 + 6 + 12,
1488 .vrefresh = 60,
1489};
1490
1491static const struct panel_desc innolux_n156bge_l21 = {
1492 .modes = &innolux_n156bge_l21_mode,
1493 .num_modes = 1,
0208d511 1494 .bpc = 6,
ea44739d
AB		 1495 .size = {
1496 .width = 344,
1497 .height = 193,
1498 },
1499};
1500
8f054b6f 1501static const struct drm_display_mode innolux_p120zdg_bf1_mode = {
da50bd42 1502 .clock = 206016,
1503 .hdisplay = 2160,
1504 .hsync_start = 2160 + 48,
1505 .hsync_end = 2160 + 48 + 32,
1506 .htotal = 2160 + 48 + 32 + 80,
1507 .vdisplay = 1440,
1508 .vsync_start = 1440 + 3,
1509 .vsync_end = 1440 + 3 + 10,
1510 .vtotal = 1440 + 3 + 10 + 27,
1511 .vrefresh = 60,
1512 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
1513};
1514
8f054b6f
DA		 1515static const struct panel_desc innolux_p120zdg_bf1 = {
1516 .modes = &innolux_p120zdg_bf1_mode,
da50bd42 1517 .num_modes = 1,
1518 .bpc = 8,
1519 .size = {
8f054b6f
DA		 1520 .width = 254,
1521 .height = 169,
da50bd42 1522 },
22fd99e9 1523 .delay = {
625d3b5c 1524 .hpd_absent_delay = 200,
22fd99e9
SP		 1525 .unprepare = 500,
1526 },
da50bd42 1527};
1528
bccac3f1
MG		 1529static const struct drm_display_mode innolux_zj070na_01p_mode = {
1530 .clock = 51501,
1531 .hdisplay = 1024,
1532 .hsync_start = 1024 + 128,
1533 .hsync_end = 1024 + 128 + 64,
1534 .htotal = 1024 + 128 + 64 + 128,
1535 .vdisplay = 600,
1536 .vsync_start = 600 + 16,
1537 .vsync_end = 600 + 16 + 4,
1538 .vtotal = 600 + 16 + 4 + 16,
1539 .vrefresh = 60,
1540};
1541
1542static const struct panel_desc innolux_zj070na_01p = {
1543 .modes = &innolux_zj070na_01p_mode,
1544 .num_modes = 1,
1545 .bpc = 6,
1546 .size = {
81598846
TR		 1547 .width = 154,
1548 .height = 90,
bccac3f1
MG		 1549 },
1550};
1551
8cfe8341
JT		 1552static const struct display_timing koe_tx31d200vm0baa_timing = {
1553 .pixelclock = { 39600000, 43200000, 48000000 },
1554 .hactive = { 1280, 1280, 1280 },
1555 .hfront_porch = { 16, 36, 56 },
1556 .hback_porch = { 16, 36, 56 },
1557 .hsync_len = { 8, 8, 8 },
1558 .vactive = { 480, 480, 480 },
c9b6be7d
SA		 1559 .vfront_porch = { 6, 21, 33 },
1560 .vback_porch = { 6, 21, 33 },
8cfe8341
JT		 1561 .vsync_len = { 8, 8, 8 },
1562 .flags = DISPLAY_FLAGS_DE_HIGH,
1563};
1564
1565static const struct panel_desc koe_tx31d200vm0baa = {
1566 .timings = &koe_tx31d200vm0baa_timing,
1567 .num_timings = 1,
1568 .bpc = 6,
1569 .size = {
1570 .width = 292,
1571 .height = 109,
1572 },
1573 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1574};
1575
8def22e5
LS		 1576static const struct display_timing kyo_tcg121xglp_timing = {
1577 .pixelclock = { 52000000, 65000000, 71000000 },
1578 .hactive = { 1024, 1024, 1024 },
1579 .hfront_porch = { 2, 2, 2 },
1580 .hback_porch = { 2, 2, 2 },
1581 .hsync_len = { 86, 124, 244 },
1582 .vactive = { 768, 768, 768 },
1583 .vfront_porch = { 2, 2, 2 },
1584 .vback_porch = { 2, 2, 2 },
1585 .vsync_len = { 6, 34, 73 },
1586 .flags = DISPLAY_FLAGS_DE_HIGH,
1587};
1588
1589static const struct panel_desc kyo_tcg121xglp = {
1590 .timings = &kyo_tcg121xglp_timing,
1591 .num_timings = 1,
1592 .bpc = 8,
1593 .size = {
1594 .width = 246,
1595 .height = 184,
1596 },
1597 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1598};
1599
dd015002
HS		 1600static const struct drm_display_mode lg_lb070wv8_mode = {
1601 .clock = 33246,
1602 .hdisplay = 800,
1603 .hsync_start = 800 + 88,
1604 .hsync_end = 800 + 88 + 80,
1605 .htotal = 800 + 88 + 80 + 88,
1606 .vdisplay = 480,
1607 .vsync_start = 480 + 10,
1608 .vsync_end = 480 + 10 + 25,
1609 .vtotal = 480 + 10 + 25 + 10,
1610 .vrefresh = 60,
1611};
1612
1613static const struct panel_desc lg_lb070wv8 = {
1614 .modes = &lg_lb070wv8_mode,
1615 .num_modes = 1,
1616 .bpc = 16,
1617 .size = {
1618 .width = 151,
1619 .height = 91,
1620 },
1621 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1622};
1623
c5ece402
YY		 1624static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
1625 .clock = 200000,
1626 .hdisplay = 1536,
1627 .hsync_start = 1536 + 12,
1628 .hsync_end = 1536 + 12 + 16,
1629 .htotal = 1536 + 12 + 16 + 48,
1630 .vdisplay = 2048,
1631 .vsync_start = 2048 + 8,
1632 .vsync_end = 2048 + 8 + 4,
1633 .vtotal = 2048 + 8 + 4 + 8,
1634 .vrefresh = 60,
1635 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1636};
1637
1638static const struct panel_desc lg_lp079qx1_sp0v = {
1639 .modes = &lg_lp079qx1_sp0v_mode,
1640 .num_modes = 1,
1641 .size = {
1642 .width = 129,
1643 .height = 171,
1644 },
1645};
1646
0355dde2
YY		 1647static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
1648 .clock = 205210,
1649 .hdisplay = 2048,
1650 .hsync_start = 2048 + 150,
1651 .hsync_end = 2048 + 150 + 5,
1652 .htotal = 2048 + 150 + 5 + 5,
1653 .vdisplay = 1536,
1654 .vsync_start = 1536 + 3,
1655 .vsync_end = 1536 + 3 + 1,
1656 .vtotal = 1536 + 3 + 1 + 9,
1657 .vrefresh = 60,
1658};
1659
1660static const struct panel_desc lg_lp097qx1_spa1 = {
1661 .modes = &lg_lp097qx1_spa1_mode,
1662 .num_modes = 1,
1663 .size = {
1664 .width = 208,
1665 .height = 147,
1666 },
1667};
1668
690d8fa7
JS		 1669static const struct drm_display_mode lg_lp120up1_mode = {
1670 .clock = 162300,
1671 .hdisplay = 1920,
1672 .hsync_start = 1920 + 40,
1673 .hsync_end = 1920 + 40 + 40,
1674 .htotal = 1920 + 40 + 40+ 80,
1675 .vdisplay = 1280,
1676 .vsync_start = 1280 + 4,
1677 .vsync_end = 1280 + 4 + 4,
1678 .vtotal = 1280 + 4 + 4 + 12,
1679 .vrefresh = 60,
1680};
1681
1682static const struct panel_desc lg_lp120up1 = {
1683 .modes = &lg_lp120up1_mode,
1684 .num_modes = 1,
1685 .bpc = 8,
1686 .size = {
1687 .width = 267,
1688 .height = 183,
1689 },
1690};
1691
ec7c5653
TR		 1692static const struct drm_display_mode lg_lp129qe_mode = {
1693 .clock = 285250,
1694 .hdisplay = 2560,
1695 .hsync_start = 2560 + 48,
1696 .hsync_end = 2560 + 48 + 32,
1697 .htotal = 2560 + 48 + 32 + 80,
1698 .vdisplay = 1700,
1699 .vsync_start = 1700 + 3,
1700 .vsync_end = 1700 + 3 + 10,
1701 .vtotal = 1700 + 3 + 10 + 36,
1702 .vrefresh = 60,
1703};
1704
1705static const struct panel_desc lg_lp129qe = {
1706 .modes = &lg_lp129qe_mode,
1707 .num_modes = 1,
0208d511 1708 .bpc = 8,
ec7c5653
TR		 1709 .size = {
1710 .width = 272,
1711 .height = 181,
1712 },
1713};
1714
65c766ca
LM		 1715static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
1716 .clock = 30400,
1717 .hdisplay = 800,
1718 .hsync_start = 800 + 0,
1719 .hsync_end = 800 + 1,
1720 .htotal = 800 + 0 + 1 + 160,
1721 .vdisplay = 480,
1722 .vsync_start = 480 + 0,
1723 .vsync_end = 480 + 48 + 1,
1724 .vtotal = 480 + 48 + 1 + 0,
1725 .vrefresh = 60,
1726 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1727};
1728
1729static const struct panel_desc mitsubishi_aa070mc01 = {
1730 .modes = &mitsubishi_aa070mc01_mode,
1731 .num_modes = 1,
1732 .bpc = 8,
1733 .size = {
1734 .width = 152,
1735 .height = 91,
1736 },
1737
1738 .delay = {
1739 .enable = 200,
1740 .unprepare = 200,
1741 .disable = 400,
1742 },
1743 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1744 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1745};
1746
01bacc13
LS		 1747static const struct display_timing nec_nl12880bc20_05_timing = {
1748 .pixelclock = { 67000000, 71000000, 75000000 },
1749 .hactive = { 1280, 1280, 1280 },
1750 .hfront_porch = { 2, 30, 30 },
1751 .hback_porch = { 6, 100, 100 },
1752 .hsync_len = { 2, 30, 30 },
1753 .vactive = { 800, 800, 800 },
1754 .vfront_porch = { 5, 5, 5 },
1755 .vback_porch = { 11, 11, 11 },
1756 .vsync_len = { 7, 7, 7 },
1757};
1758
1759static const struct panel_desc nec_nl12880bc20_05 = {
1760 .timings = &nec_nl12880bc20_05_timing,
1761 .num_timings = 1,
1762 .bpc = 8,
1763 .size = {
1764 .width = 261,
1765 .height = 163,
1766 },
1767 .delay = {
1768 .enable = 50,
1769 .disable = 50,
1770 },
1771 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1772};
1773
c6e87f91 1774static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
1775 .clock = 10870,
1776 .hdisplay = 480,
1777 .hsync_start = 480 + 2,
1778 .hsync_end = 480 + 2 + 41,
1779 .htotal = 480 + 2 + 41 + 2,
1780 .vdisplay = 272,
1781 .vsync_start = 272 + 2,
1782 .vsync_end = 272 + 2 + 4,
1783 .vtotal = 272 + 2 + 4 + 2,
1784 .vrefresh = 74,
4bc390c6 1785 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
c6e87f91 1786};
1787
1788static const struct panel_desc nec_nl4827hc19_05b = {
1789 .modes = &nec_nl4827hc19_05b_mode,
1790 .num_modes = 1,
1791 .bpc = 8,
1792 .size = {
1793 .width = 95,
1794 .height = 54,
1795 },
2c80661d
SA		 1796 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1797 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
c6e87f91 1798};
1799
e6c2f066
MR		 1800static const struct drm_display_mode netron_dy_e231732_mode = {
1801 .clock = 66000,
1802 .hdisplay = 1024,
1803 .hsync_start = 1024 + 160,
1804 .hsync_end = 1024 + 160 + 70,
1805 .htotal = 1024 + 160 + 70 + 90,
1806 .vdisplay = 600,
1807 .vsync_start = 600 + 127,
1808 .vsync_end = 600 + 127 + 20,
1809 .vtotal = 600 + 127 + 20 + 3,
1810 .vrefresh = 60,
1811};
1812
1813static const struct panel_desc netron_dy_e231732 = {
1814 .modes = &netron_dy_e231732_mode,
1815 .num_modes = 1,
1816 .size = {
1817 .width = 154,
1818 .height = 87,
1819 },
1820 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1821};
1822
3b39ad7a
TV		 1823static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
1824 .clock = 9000,
1825 .hdisplay = 480,
1826 .hsync_start = 480 + 2,
1827 .hsync_end = 480 + 2 + 41,
1828 .htotal = 480 + 2 + 41 + 2,
1829 .vdisplay = 272,
1830 .vsync_start = 272 + 2,
1831 .vsync_end = 272 + 2 + 10,
1832 .vtotal = 272 + 2 + 10 + 2,
1833 .vrefresh = 60,
1834 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1835};
1836
1837static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
1838 .modes = &newhaven_nhd_43_480272ef_atxl_mode,
1839 .num_modes = 1,
1840 .bpc = 8,
1841 .size = {
1842 .width = 95,
1843 .height = 54,
1844 },
1845 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1846 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE |
1847 DRM_BUS_FLAG_SYNC_POSEDGE,
1848};
1849
4177fa66
LS		 1850static const struct display_timing nlt_nl192108ac18_02d_timing = {
1851 .pixelclock = { 130000000, 148350000, 163000000 },
1852 .hactive = { 1920, 1920, 1920 },
1853 .hfront_porch = { 80, 100, 100 },
1854 .hback_porch = { 100, 120, 120 },
1855 .hsync_len = { 50, 60, 60 },
1856 .vactive = { 1080, 1080, 1080 },
1857 .vfront_porch = { 12, 30, 30 },
1858 .vback_porch = { 4, 10, 10 },
1859 .vsync_len = { 4, 5, 5 },
1860};
1861
1862static const struct panel_desc nlt_nl192108ac18_02d = {
1863 .timings = &nlt_nl192108ac18_02d_timing,
1864 .num_timings = 1,
1865 .bpc = 8,
1866 .size = {
1867 .width = 344,
1868 .height = 194,
1869 },
1870 .delay = {
1871 .unprepare = 500,
1872 },
1873 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1874};
1875
05ec0e45
FL		 1876static const struct drm_display_mode nvd_9128_mode = {
1877 .clock = 29500,
1878 .hdisplay = 800,
1879 .hsync_start = 800 + 130,
1880 .hsync_end = 800 + 130 + 98,
1881 .htotal = 800 + 0 + 130 + 98,
1882 .vdisplay = 480,
1883 .vsync_start = 480 + 10,
1884 .vsync_end = 480 + 10 + 50,
1885 .vtotal = 480 + 0 + 10 + 50,
1886};
1887
1888static const struct panel_desc nvd_9128 = {
1889 .modes = &nvd_9128_mode,
1890 .num_modes = 1,
1891 .bpc = 8,
1892 .size = {
1893 .width = 156,
1894 .height = 88,
1895 },
1896 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1897};
1898
a99fb626
GB		 1899static const struct display_timing okaya_rs800480t_7x0gp_timing = {
1900 .pixelclock = { 30000000, 30000000, 40000000 },
1901 .hactive = { 800, 800, 800 },
1902 .hfront_porch = { 40, 40, 40 },
1903 .hback_porch = { 40, 40, 40 },
1904 .hsync_len = { 1, 48, 48 },
1905 .vactive = { 480, 480, 480 },
1906 .vfront_porch = { 13, 13, 13 },
1907 .vback_porch = { 29, 29, 29 },
1908 .vsync_len = { 3, 3, 3 },
1909 .flags = DISPLAY_FLAGS_DE_HIGH,
1910};
1911
1912static const struct panel_desc okaya_rs800480t_7x0gp = {
1913 .timings = &okaya_rs800480t_7x0gp_timing,
1914 .num_timings = 1,
1915 .bpc = 6,
1916 .size = {
1917 .width = 154,
1918 .height = 87,
1919 },
1920 .delay = {
1921 .prepare = 41,
1922 .enable = 50,
1923 .unprepare = 41,
1924 .disable = 50,
1925 },
1926 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1927};
1928
cf5c9e6d
MR		 1929static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
1930 .clock = 9000,
1931 .hdisplay = 480,
1932 .hsync_start = 480 + 5,
1933 .hsync_end = 480 + 5 + 30,
1934 .htotal = 480 + 5 + 30 + 10,
1935 .vdisplay = 272,
1936 .vsync_start = 272 + 8,
1937 .vsync_end = 272 + 8 + 5,
1938 .vtotal = 272 + 8 + 5 + 3,
1939 .vrefresh = 60,
1940};
1941
1942static const struct panel_desc olimex_lcd_olinuxino_43ts = {
1943 .modes = &olimex_lcd_olinuxino_43ts_mode,
1944 .num_modes = 1,
1945 .size = {
30c6d7ab
JL		 1946 .width = 95,
1947 .height = 54,
cf5c9e6d 1948 },
5c2a7c6b 1949 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
cf5c9e6d
MR		 1950};
1951
e8b6f561
EA		 1952/*
1953 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
1954 * pixel clocks, but this is the timing that was being used in the Adafruit
1955 * installation instructions.
1956 */
1957static const struct drm_display_mode ontat_yx700wv03_mode = {
1958 .clock = 29500,
1959 .hdisplay = 800,
1960 .hsync_start = 824,
1961 .hsync_end = 896,
1962 .htotal = 992,
1963 .vdisplay = 480,
1964 .vsync_start = 483,
1965 .vsync_end = 493,
1966 .vtotal = 500,
1967 .vrefresh = 60,
1968 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1969};
1970
1971/*
1972 * Specification at:
1973 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
1974 */
1975static const struct panel_desc ontat_yx700wv03 = {
1976 .modes = &ontat_yx700wv03_mode,
1977 .num_modes = 1,
1978 .bpc = 8,
1979 .size = {
1980 .width = 154,
1981 .height = 83,
1982 },
5651e5e0 1983 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
e8b6f561
EA		 1984};
1985
725c9d40
PZ		 1986static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
1987 .clock = 25000,
1988 .hdisplay = 480,
1989 .hsync_start = 480 + 10,
1990 .hsync_end = 480 + 10 + 10,
1991 .htotal = 480 + 10 + 10 + 15,
1992 .vdisplay = 800,
1993 .vsync_start = 800 + 3,
1994 .vsync_end = 800 + 3 + 3,
1995 .vtotal = 800 + 3 + 3 + 3,
1996 .vrefresh = 60,
1997};
1998
1999static const struct panel_desc ortustech_com43h4m85ulc = {
2000 .modes = &ortustech_com43h4m85ulc_mode,
2001 .num_modes = 1,
2002 .bpc = 8,
2003 .size = {
2004 .width = 56,
2005 .height = 93,
2006 },
2007 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
e0932f9d 2008 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
725c9d40
PZ		 2009};
2010
d2a6f0f5
JW		 2011static const struct drm_display_mode qd43003c0_40_mode = {
2012 .clock = 9000,
2013 .hdisplay = 480,
2014 .hsync_start = 480 + 8,
2015 .hsync_end = 480 + 8 + 4,
2016 .htotal = 480 + 8 + 4 + 39,
2017 .vdisplay = 272,
2018 .vsync_start = 272 + 4,
2019 .vsync_end = 272 + 4 + 10,
2020 .vtotal = 272 + 4 + 10 + 2,
2021 .vrefresh = 60,
2022};
2023
2024static const struct panel_desc qd43003c0_40 = {
2025 .modes = &qd43003c0_40_mode,
2026 .num_modes = 1,
2027 .bpc = 8,
2028 .size = {
2029 .width = 95,
2030 .height = 53,
2031 },
2032 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2033};
2034
23167fa9
JT		 2035static const struct display_timing rocktech_rk070er9427_timing = {
2036 .pixelclock = { 26400000, 33300000, 46800000 },
2037 .hactive = { 800, 800, 800 },
2038 .hfront_porch = { 16, 210, 354 },
2039 .hback_porch = { 46, 46, 46 },
2040 .hsync_len = { 1, 1, 1 },
2041 .vactive = { 480, 480, 480 },
2042 .vfront_porch = { 7, 22, 147 },
2043 .vback_porch = { 23, 23, 23 },
2044 .vsync_len = { 1, 1, 1 },
2045 .flags = DISPLAY_FLAGS_DE_HIGH,
2046};
2047
2048static const struct panel_desc rocktech_rk070er9427 = {
2049 .timings = &rocktech_rk070er9427_timing,
2050 .num_timings = 1,
2051 .bpc = 6,
2052 .size = {
2053 .width = 154,
2054 .height = 86,
2055 },
2056 .delay = {
2057 .prepare = 41,
2058 .enable = 50,
2059 .unprepare = 41,
2060 .disable = 50,
2061 },
2062 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2063};
2064
0330eaf3
YY		 2065static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
2066 .clock = 271560,
2067 .hdisplay = 2560,
2068 .hsync_start = 2560 + 48,
2069 .hsync_end = 2560 + 48 + 32,
2070 .htotal = 2560 + 48 + 32 + 80,
2071 .vdisplay = 1600,
2072 .vsync_start = 1600 + 2,
2073 .vsync_end = 1600 + 2 + 5,
2074 .vtotal = 1600 + 2 + 5 + 57,
2075 .vrefresh = 60,
2076};
2077
2078static const struct panel_desc samsung_lsn122dl01_c01 = {
2079 .modes = &samsung_lsn122dl01_c01_mode,
2080 .num_modes = 1,
2081 .size = {
2082 .width = 263,
2083 .height = 164,
2084 },
2085};
2086
6d54e3d2
MD		 2087static const struct drm_display_mode samsung_ltn101nt05_mode = {
2088 .clock = 54030,
2089 .hdisplay = 1024,
2090 .hsync_start = 1024 + 24,
2091 .hsync_end = 1024 + 24 + 136,
2092 .htotal = 1024 + 24 + 136 + 160,
2093 .vdisplay = 600,
2094 .vsync_start = 600 + 3,
2095 .vsync_end = 600 + 3 + 6,
2096 .vtotal = 600 + 3 + 6 + 61,
2097 .vrefresh = 60,
2098};
2099
2100static const struct panel_desc samsung_ltn101nt05 = {
2101 .modes = &samsung_ltn101nt05_mode,
2102 .num_modes = 1,
0208d511 2103 .bpc = 6,
6d54e3d2 2104 .size = {
81598846
TR		 2105 .width = 223,
2106 .height = 125,
6d54e3d2
MD		 2107 },
2108};
2109
0c934306
SM		 2110static const struct drm_display_mode samsung_ltn140at29_301_mode = {
2111 .clock = 76300,
2112 .hdisplay = 1366,
2113 .hsync_start = 1366 + 64,
2114 .hsync_end = 1366 + 64 + 48,
2115 .htotal = 1366 + 64 + 48 + 128,
2116 .vdisplay = 768,
2117 .vsync_start = 768 + 2,
2118 .vsync_end = 768 + 2 + 5,
2119 .vtotal = 768 + 2 + 5 + 17,
2120 .vrefresh = 60,
2121};
2122
2123static const struct panel_desc samsung_ltn140at29_301 = {
2124 .modes = &samsung_ltn140at29_301_mode,
2125 .num_modes = 1,
2126 .bpc = 6,
2127 .size = {
2128 .width = 320,
2129 .height = 187,
2130 },
2131};
2132
03e3ec9a
VZ		 2133static const struct drm_display_mode sharp_lq035q7db03_mode = {
2134 .clock = 5500,
2135 .hdisplay = 240,
2136 .hsync_start = 240 + 16,
2137 .hsync_end = 240 + 16 + 7,
2138 .htotal = 240 + 16 + 7 + 5,
2139 .vdisplay = 320,
2140 .vsync_start = 320 + 9,
2141 .vsync_end = 320 + 9 + 1,
2142 .vtotal = 320 + 9 + 1 + 7,
2143 .vrefresh = 60,
2144};
2145
2146static const struct panel_desc sharp_lq035q7db03 = {
2147 .modes = &sharp_lq035q7db03_mode,
2148 .num_modes = 1,
2149 .bpc = 6,
2150 .size = {
2151 .width = 54,
2152 .height = 72,
2153 },
2154 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2155};
2156
592aa02b
JC		 2157static const struct display_timing sharp_lq101k1ly04_timing = {
2158 .pixelclock = { 60000000, 65000000, 80000000 },
2159 .hactive = { 1280, 1280, 1280 },
2160 .hfront_porch = { 20, 20, 20 },
2161 .hback_porch = { 20, 20, 20 },
2162 .hsync_len = { 10, 10, 10 },
2163 .vactive = { 800, 800, 800 },
2164 .vfront_porch = { 4, 4, 4 },
2165 .vback_porch = { 4, 4, 4 },
2166 .vsync_len = { 4, 4, 4 },
2167 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
2168};
2169
2170static const struct panel_desc sharp_lq101k1ly04 = {
2171 .timings = &sharp_lq101k1ly04_timing,
2172 .num_timings = 1,
2173 .bpc = 8,
2174 .size = {
2175 .width = 217,
2176 .height = 136,
2177 },
2178 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
2179};
2180
9f7bae2d
SP		 2181static const struct display_timing sharp_lq123p1jx31_timing = {
2182 .pixelclock = { 252750000, 252750000, 266604720 },
2183 .hactive = { 2400, 2400, 2400 },
2184 .hfront_porch = { 48, 48, 48 },
2185 .hback_porch = { 80, 80, 84 },
2186 .hsync_len = { 32, 32, 32 },
2187 .vactive = { 1600, 1600, 1600 },
2188 .vfront_porch = { 3, 3, 3 },
2189 .vback_porch = { 33, 33, 120 },
2190 .vsync_len = { 10, 10, 10 },
2191 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
739c7de9
YY		 2192};
2193
2194static const struct panel_desc sharp_lq123p1jx31 = {
9f7bae2d
SP		 2195 .timings = &sharp_lq123p1jx31_timing,
2196 .num_timings = 1,
5466a631 2197 .bpc = 8,
739c7de9
YY		 2198 .size = {
2199 .width = 259,
2200 .height = 173,
2201 },
a42f6e3f
YY		 2202 .delay = {
2203 .prepare = 110,
2204 .enable = 50,
2205 .unprepare = 550,
2206 },
739c7de9
YY		 2207};
2208
0f9cdd74
GL		 2209static const struct drm_display_mode sharp_lq150x1lg11_mode = {
2210 .clock = 71100,
2211 .hdisplay = 1024,
2212 .hsync_start = 1024 + 168,
2213 .hsync_end = 1024 + 168 + 64,
2214 .htotal = 1024 + 168 + 64 + 88,
2215 .vdisplay = 768,
2216 .vsync_start = 768 + 37,
2217 .vsync_end = 768 + 37 + 2,
2218 .vtotal = 768 + 37 + 2 + 8,
2219 .vrefresh = 60,
2220};
2221
2222static const struct panel_desc sharp_lq150x1lg11 = {
2223 .modes = &sharp_lq150x1lg11_mode,
2224 .num_modes = 1,
2225 .bpc = 6,
2226 .size = {
2227 .width = 304,
2228 .height = 228,
2229 },
2230 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
2231};
2232
9c6615bc
BB		 2233static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
2234 .clock = 33300,
2235 .hdisplay = 800,
2236 .hsync_start = 800 + 1,
2237 .hsync_end = 800 + 1 + 64,
2238 .htotal = 800 + 1 + 64 + 64,
2239 .vdisplay = 480,
2240 .vsync_start = 480 + 1,
2241 .vsync_end = 480 + 1 + 23,
2242 .vtotal = 480 + 1 + 23 + 22,
2243 .vrefresh = 60,
2244};
2245
2246static const struct panel_desc shelly_sca07010_bfn_lnn = {
2247 .modes = &shelly_sca07010_bfn_lnn_mode,
2248 .num_modes = 1,
2249 .size = {
2250 .width = 152,
2251 .height = 91,
2252 },
2253 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2254};
2255
9bb34c4c
DA		 2256static const struct drm_display_mode starry_kr122ea0sra_mode = {
2257 .clock = 147000,
2258 .hdisplay = 1920,
2259 .hsync_start = 1920 + 16,
2260 .hsync_end = 1920 + 16 + 16,
2261 .htotal = 1920 + 16 + 16 + 32,
2262 .vdisplay = 1200,
2263 .vsync_start = 1200 + 15,
2264 .vsync_end = 1200 + 15 + 2,
2265 .vtotal = 1200 + 15 + 2 + 18,
2266 .vrefresh = 60,
2267 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2268};
2269
2270static const struct panel_desc starry_kr122ea0sra = {
2271 .modes = &starry_kr122ea0sra_mode,
2272 .num_modes = 1,
2273 .size = {
2274 .width = 263,
2275 .height = 164,
2276 },
c46b924b
BN		 2277 .delay = {
2278 .prepare = 10 + 200,
2279 .enable = 50,
2280 .unprepare = 10 + 500,
2281 },
9bb34c4c
DA		 2282};
2283
adb973ef
GB		 2284static const struct display_timing tianma_tm070jdhg30_timing = {
2285 .pixelclock = { 62600000, 68200000, 78100000 },
2286 .hactive = { 1280, 1280, 1280 },
2287 .hfront_porch = { 15, 64, 159 },
2288 .hback_porch = { 5, 5, 5 },
2289 .hsync_len = { 1, 1, 256 },
2290 .vactive = { 800, 800, 800 },
2291 .vfront_porch = { 3, 40, 99 },
2292 .vback_porch = { 2, 2, 2 },
2293 .vsync_len = { 1, 1, 128 },
2294 .flags = DISPLAY_FLAGS_DE_HIGH,
2295};
2296
2297static const struct panel_desc tianma_tm070jdhg30 = {
2298 .timings = &tianma_tm070jdhg30_timing,
2299 .num_timings = 1,
2300 .bpc = 8,
2301 .size = {
2302 .width = 151,
2303 .height = 95,
2304 },
2305 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2306};
2307
870a0b12
LM		 2308static const struct display_timing tianma_tm070rvhg71_timing = {
2309 .pixelclock = { 27700000, 29200000, 39600000 },
2310 .hactive = { 800, 800, 800 },
2311 .hfront_porch = { 12, 40, 212 },
2312 .hback_porch = { 88, 88, 88 },
2313 .hsync_len = { 1, 1, 40 },
2314 .vactive = { 480, 480, 480 },
2315 .vfront_porch = { 1, 13, 88 },
2316 .vback_porch = { 32, 32, 32 },
2317 .vsync_len = { 1, 1, 3 },
2318 .flags = DISPLAY_FLAGS_DE_HIGH,
2319};
2320
2321static const struct panel_desc tianma_tm070rvhg71 = {
2322 .timings = &tianma_tm070rvhg71_timing,
2323 .num_timings = 1,
2324 .bpc = 8,
2325 .size = {
2326 .width = 154,
2327 .height = 86,
2328 },
2329 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2330};
2331
06e733e4
LS		 2332static const struct drm_display_mode toshiba_lt089ac29000_mode = {
2333 .clock = 79500,
2334 .hdisplay = 1280,
2335 .hsync_start = 1280 + 192,
2336 .hsync_end = 1280 + 192 + 128,
2337 .htotal = 1280 + 192 + 128 + 64,
2338 .vdisplay = 768,
2339 .vsync_start = 768 + 20,
2340 .vsync_end = 768 + 20 + 7,
2341 .vtotal = 768 + 20 + 7 + 3,
2342 .vrefresh = 60,
2343};
2344
2345static const struct panel_desc toshiba_lt089ac29000 = {
2346 .modes = &toshiba_lt089ac29000_mode,
2347 .num_modes = 1,
2348 .size = {
2349 .width = 194,
2350 .height = 116,
2351 },
2352 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2353 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
2354};
2355
227e4f40
BD		 2356static const struct drm_display_mode tpk_f07a_0102_mode = {
2357 .clock = 33260,
2358 .hdisplay = 800,
2359 .hsync_start = 800 + 40,
2360 .hsync_end = 800 + 40 + 128,
2361 .htotal = 800 + 40 + 128 + 88,
2362 .vdisplay = 480,
2363 .vsync_start = 480 + 10,
2364 .vsync_end = 480 + 10 + 2,
2365 .vtotal = 480 + 10 + 2 + 33,
2366 .vrefresh = 60,
2367};
2368
2369static const struct panel_desc tpk_f07a_0102 = {
2370 .modes = &tpk_f07a_0102_mode,
2371 .num_modes = 1,
2372 .size = {
2373 .width = 152,
2374 .height = 91,
2375 },
2376 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
2377};
2378
2379static const struct drm_display_mode tpk_f10a_0102_mode = {
2380 .clock = 45000,
2381 .hdisplay = 1024,
2382 .hsync_start = 1024 + 176,
2383 .hsync_end = 1024 + 176 + 5,
2384 .htotal = 1024 + 176 + 5 + 88,
2385 .vdisplay = 600,
2386 .vsync_start = 600 + 20,
2387 .vsync_end = 600 + 20 + 5,
2388 .vtotal = 600 + 20 + 5 + 25,
2389 .vrefresh = 60,
2390};
2391
2392static const struct panel_desc tpk_f10a_0102 = {
2393 .modes = &tpk_f10a_0102_mode,
2394 .num_modes = 1,
2395 .size = {
2396 .width = 223,
2397 .height = 125,
2398 },
2399};
2400
06a9dc65
MS		 2401static const struct display_timing urt_umsh_8596md_timing = {
2402 .pixelclock = { 33260000, 33260000, 33260000 },
2403 .hactive = { 800, 800, 800 },
2404 .hfront_porch = { 41, 41, 41 },
2405 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
2406 .hsync_len = { 71, 128, 128 },
2407 .vactive = { 480, 480, 480 },
2408 .vfront_porch = { 10, 10, 10 },
2409 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
2410 .vsync_len = { 2, 2, 2 },
2411 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
2412 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
2413};
2414
2415static const struct panel_desc urt_umsh_8596md_lvds = {
2416 .timings = &urt_umsh_8596md_timing,
2417 .num_timings = 1,
2418 .bpc = 6,
2419 .size = {
2420 .width = 152,
2421 .height = 91,
2422 },
2423 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2424};
2425
2426static const struct panel_desc urt_umsh_8596md_parallel = {
2427 .timings = &urt_umsh_8596md_timing,
2428 .num_timings = 1,
2429 .bpc = 6,
2430 .size = {
2431 .width = 152,
2432 .height = 91,
2433 },
2434 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2435};
2436
e4bac408
RG		 2437static const struct drm_display_mode winstar_wf35ltiacd_mode = {
2438 .clock = 6410,
2439 .hdisplay = 320,
2440 .hsync_start = 320 + 20,
2441 .hsync_end = 320 + 20 + 30,
2442 .htotal = 320 + 20 + 30 + 38,
2443 .vdisplay = 240,
2444 .vsync_start = 240 + 4,
2445 .vsync_end = 240 + 4 + 3,
2446 .vtotal = 240 + 4 + 3 + 15,
2447 .vrefresh = 60,
2448 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2449};
2450
2451static const struct panel_desc winstar_wf35ltiacd = {
2452 .modes = &winstar_wf35ltiacd_mode,
2453 .num_modes = 1,
2454 .bpc = 8,
2455 .size = {
2456 .width = 70,
2457 .height = 53,
2458 },
2459 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2460};
2461
fcec4163
LW		 2462static const struct drm_display_mode arm_rtsm_mode[] = {
2463 {
2464 .clock = 65000,
2465 .hdisplay = 1024,
2466 .hsync_start = 1024 + 24,
2467 .hsync_end = 1024 + 24 + 136,
2468 .htotal = 1024 + 24 + 136 + 160,
2469 .vdisplay = 768,
2470 .vsync_start = 768 + 3,
2471 .vsync_end = 768 + 3 + 6,
2472 .vtotal = 768 + 3 + 6 + 29,
2473 .vrefresh = 60,
2474 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2475 },
2476};
2477
2478static const struct panel_desc arm_rtsm = {
2479 .modes = arm_rtsm_mode,
2480 .num_modes = 1,
2481 .bpc = 8,
2482 .size = {
2483 .width = 400,
2484 .height = 300,
2485 },
2486 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2487};
2488
280921de
TR		 2489static const struct of_device_id platform_of_match[] = {
2490 {
966fea78
YF		 2491 .compatible = "ampire,am-480272h3tmqw-t01h",
2492 .data = &ampire_am_480272h3tmqw_t01h,
2493 }, {
1c550fa1
PZ		 2494 .compatible = "ampire,am800480r3tmqwa1h",
2495 .data = &ampire_am800480r3tmqwa1h,
fcec4163
LW		 2496 }, {
2497 .compatible = "arm,rtsm-display",
2498 .data = &arm_rtsm,
1c550fa1 2499 }, {
280921de
TR		 2500 .compatible = "auo,b101aw03",
2501 .data = &auo_b101aw03,
a531bc3d
HL		 2502 }, {
2503 .compatible = "auo,b101ean01",
2504 .data = &auo_b101ean01,
dac746e0
RC		 2505 }, {
2506 .compatible = "auo,b101xtn01",
2507 .data = &auo_b101xtn01,
e35e305e
AK		 2508 }, {
2509 .compatible = "auo,b116xw03",
2510 .data = &auo_b116xw03,
3e51d609
AK		 2511 }, {
2512 .compatible = "auo,b133htn01",
2513 .data = &auo_b133htn01,
a333f7ad
SM		 2514 }, {
2515 .compatible = "auo,b133xtn01",
2516 .data = &auo_b133xtn01,
bccfaffb
LM		 2517 }, {
2518 .compatible = "auo,g070vvn01",
2519 .data = &auo_g070vvn01,
4fb86404
AG		 2520 }, {
2521 .compatible = "auo,g101evn010",
2522 .data = &auo_g101evn010,
4451c287
CF		 2523 }, {
2524 .compatible = "auo,g104sn02",
2525 .data = &auo_g104sn02,
697035c6
LS		 2526 }, {
2527 .compatible = "auo,g133han01",
2528 .data = &auo_g133han01,
8c31f603
LS		 2529 }, {
2530 .compatible = "auo,g185han01",
2531 .data = &auo_g185han01,
70c0d5b7
LS		 2532 }, {
2533 .compatible = "auo,p320hvn03",
2534 .data = &auo_p320hvn03,
7ee933a1
HS		 2535 }, {
2536 .compatible = "auo,t215hvn01",
2537 .data = &auo_t215hvn01,
d47df633
PZ		 2538 }, {
2539 .compatible = "avic,tm070ddh03",
2540 .data = &avic_tm070ddh03,
7ad8b41c
CYT		 2541 }, {
2542 .compatible = "bananapi,s070wv20-ct16",
2543 .data = &bananapi_s070wv20_ct16,
ae8cf41b
AH		 2544 }, {
2545 .compatible = "boe,hv070wsa-100",
2546 .data = &boe_hv070wsa
cac1a411
CW		 2547 }, {
2548 .compatible = "boe,nv101wxmn51",
2549 .data = &boe_nv101wxmn51,
e58edce6
GB		 2550 }, {
2551 .compatible = "cdtech,s043wq26h-ct7",
2552 .data = &cdtech_s043wq26h_ct7,
982f944e
GB		 2553 }, {
2554 .compatible = "cdtech,s070wv95-ct16",
2555 .data = &cdtech_s070wv95_ct16,
2cb35c80
RL		 2556 }, {
2557 .compatible = "chunghwa,claa070wp03xg",
2558 .data = &chunghwa_claa070wp03xg,
4c930757
SW		 2559 }, {
2560 .compatible = "chunghwa,claa101wa01a",
2561 .data = &chunghwa_claa101wa01a
280921de
TR		 2562 }, {
2563 .compatible = "chunghwa,claa101wb01",
2564 .data = &chunghwa_claa101wb01
97ceb1fb
MV		 2565 }, {
2566 .compatible = "dataimage,scf0700c48ggu18",
2567 .data = &dataimage_scf0700c48ggu18,
0ca0c827
PZ		 2568 }, {
2569 .compatible = "dlc,dlc0700yzg-1",
2570 .data = &dlc_dlc0700yzg_1,
6cbe7cd1
MF		 2571 }, {
2572 .compatible = "dlc,dlc1010gig",
2573 .data = &dlc_dlc1010gig,
26ab0065
SA		 2574 }, {
2575 .compatible = "edt,et057090dhu",
2576 .data = &edt_et057090dhu,
fff5de45
PZ		 2577 }, {
2578 .compatible = "edt,et070080dh6",
2579 .data = &edt_etm0700g0dh6,
2580 }, {
2581 .compatible = "edt,etm0700g0dh6",
2582 .data = &edt_etm0700g0dh6,
aa7e6455
JT		 2583 }, {
2584 .compatible = "edt,etm0700g0bdh6",
2585 .data = &edt_etm0700g0bdh6,
aad34de2
JT		 2586 }, {
2587 .compatible = "edt,etm0700g0edh6",
2588 .data = &edt_etm0700g0bdh6,
102932b0
BB		 2589 }, {
2590 .compatible = "foxlink,fl500wvr00-a0t",
2591 .data = &foxlink_fl500wvr00_a0t,
d435a2af
PZ		 2592 }, {
2593 .compatible = "giantplus,gpg482739qs5",
2594 .data = &giantplus_gpg482739qs5
a853205e
PZ		 2595 }, {
2596 .compatible = "hannstar,hsd070pww1",
2597 .data = &hannstar_hsd070pww1,
c0d607e5
EN		 2598 }, {
2599 .compatible = "hannstar,hsd100pxn1",
2600 .data = &hannstar_hsd100pxn1,
61ac0bf8
LS		 2601 }, {
2602 .compatible = "hit,tx23d38vm0caa",
2603 .data = &hitachi_tx23d38vm0caa
41bcceb4
NF		 2604 }, {
2605 .compatible = "innolux,at043tn24",
2606 .data = &innolux_at043tn24,
4fc24ab3
RB		 2607 }, {
2608 .compatible = "innolux,at070tn92",
2609 .data = &innolux_at070tn92,
1e29b840 2610 }, {
a5d2ade6
CF		 2611 .compatible = "innolux,g070y2-l01",
2612 .data = &innolux_g070y2_l01,
2613 }, {
2614 .compatible = "innolux,g101ice-l01",
1e29b840 2615 .data = &innolux_g101ice_l01
d731f661 2616 }, {
a5d2ade6 2617 .compatible = "innolux,g121i1-l01",
d731f661 2618 .data = &innolux_g121i1_l01
f8fa17ba
AB		 2619 }, {
2620 .compatible = "innolux,g121x1-l03",
2621 .data = &innolux_g121x1_l03,
0a2288c0
TR		 2622 }, {
2623 .compatible = "innolux,n116bge",
2624 .data = &innolux_n116bge,
ea44739d
AB		 2625 }, {
2626 .compatible = "innolux,n156bge-l21",
2627 .data = &innolux_n156bge_l21,
da50bd42 2628 }, {
8f054b6f
DA		 2629 .compatible = "innolux,p120zdg-bf1",
2630 .data = &innolux_p120zdg_bf1,
bccac3f1
MG		 2631 }, {
2632 .compatible = "innolux,zj070na-01p",
2633 .data = &innolux_zj070na_01p,
8cfe8341
JT		 2634 }, {
2635 .compatible = "koe,tx31d200vm0baa",
2636 .data = &koe_tx31d200vm0baa,
8def22e5
LS		 2637 }, {
2638 .compatible = "kyo,tcg121xglp",
2639 .data = &kyo_tcg121xglp,
dd015002
HS		 2640 }, {
2641 .compatible = "lg,lb070wv8",
2642 .data = &lg_lb070wv8,
c5ece402
YY		 2643 }, {
2644 .compatible = "lg,lp079qx1-sp0v",
2645 .data = &lg_lp079qx1_sp0v,
0355dde2
YY		 2646 }, {
2647 .compatible = "lg,lp097qx1-spa1",
2648 .data = &lg_lp097qx1_spa1,
690d8fa7
JS		 2649 }, {
2650 .compatible = "lg,lp120up1",
2651 .data = &lg_lp120up1,
ec7c5653
TR		 2652 }, {
2653 .compatible = "lg,lp129qe",
2654 .data = &lg_lp129qe,
65c766ca
LM		 2655 }, {
2656 .compatible = "mitsubishi,aa070mc01-ca1",
2657 .data = &mitsubishi_aa070mc01,
01bacc13
LS		 2658 }, {
2659 .compatible = "nec,nl12880bc20-05",
2660 .data = &nec_nl12880bc20_05,
c6e87f91 2661 }, {
2662 .compatible = "nec,nl4827hc19-05b",
2663 .data = &nec_nl4827hc19_05b,
e6c2f066
MR		 2664 }, {
2665 .compatible = "netron-dy,e231732",
2666 .data = &netron_dy_e231732,
3b39ad7a
TV		 2667 }, {
2668 .compatible = "newhaven,nhd-4.3-480272ef-atxl",
2669 .data = &newhaven_nhd_43_480272ef_atxl,
4177fa66
LS		 2670 }, {
2671 .compatible = "nlt,nl192108ac18-02d",
2672 .data = &nlt_nl192108ac18_02d,
05ec0e45
FL		 2673 }, {
2674 .compatible = "nvd,9128",
2675 .data = &nvd_9128,
a99fb626
GB		 2676 }, {
2677 .compatible = "okaya,rs800480t-7x0gp",
2678 .data = &okaya_rs800480t_7x0gp,
cf5c9e6d
MR		 2679 }, {
2680 .compatible = "olimex,lcd-olinuxino-43-ts",
2681 .data = &olimex_lcd_olinuxino_43ts,
e8b6f561
EA		 2682 }, {
2683 .compatible = "ontat,yx700wv03",
2684 .data = &ontat_yx700wv03,
725c9d40
PZ		 2685 }, {
2686 .compatible = "ortustech,com43h4m85ulc",
2687 .data = &ortustech_com43h4m85ulc,
d2a6f0f5
JW		 2688 }, {
2689 .compatible = "qiaodian,qd43003c0-40",
2690 .data = &qd43003c0_40,
23167fa9
JT		 2691 }, {
2692 .compatible = "rocktech,rk070er9427",
2693 .data = &rocktech_rk070er9427,
0330eaf3
YY		 2694 }, {
2695 .compatible = "samsung,lsn122dl01-c01",
2696 .data = &samsung_lsn122dl01_c01,
6d54e3d2
MD		 2697 }, {
2698 .compatible = "samsung,ltn101nt05",
2699 .data = &samsung_ltn101nt05,
0c934306
SM		 2700 }, {
2701 .compatible = "samsung,ltn140at29-301",
2702 .data = &samsung_ltn140at29_301,
03e3ec9a
VZ		 2703 }, {
2704 .compatible = "sharp,lq035q7db03",
2705 .data = &sharp_lq035q7db03,
592aa02b
JC		 2706 }, {
2707 .compatible = "sharp,lq101k1ly04",
2708 .data = &sharp_lq101k1ly04,
739c7de9
YY		 2709 }, {
2710 .compatible = "sharp,lq123p1jx31",
2711 .data = &sharp_lq123p1jx31,
0f9cdd74
GL		 2712 }, {
2713 .compatible = "sharp,lq150x1lg11",
2714 .data = &sharp_lq150x1lg11,
9c6615bc
BB		 2715 }, {
2716 .compatible = "shelly,sca07010-bfn-lnn",
2717 .data = &shelly_sca07010_bfn_lnn,
9bb34c4c
DA		 2718 }, {
2719 .compatible = "starry,kr122ea0sra",
2720 .data = &starry_kr122ea0sra,
adb973ef
GB		 2721 }, {
2722 .compatible = "tianma,tm070jdhg30",
2723 .data = &tianma_tm070jdhg30,
870a0b12
LM		 2724 }, {
2725 .compatible = "tianma,tm070rvhg71",
2726 .data = &tianma_tm070rvhg71,
06e733e4
LS		 2727 }, {
2728 .compatible = "toshiba,lt089ac29000",
2729 .data = &toshiba_lt089ac29000,
227e4f40
BD		 2730 }, {
2731 .compatible = "tpk,f07a-0102",
2732 .data = &tpk_f07a_0102,
2733 }, {
2734 .compatible = "tpk,f10a-0102",
2735 .data = &tpk_f10a_0102,
06a9dc65
MS		 2736 }, {
2737 .compatible = "urt,umsh-8596md-t",
2738 .data = &urt_umsh_8596md_parallel,
2739 }, {
2740 .compatible = "urt,umsh-8596md-1t",
2741 .data = &urt_umsh_8596md_parallel,
2742 }, {
2743 .compatible = "urt,umsh-8596md-7t",
2744 .data = &urt_umsh_8596md_parallel,
2745 }, {
2746 .compatible = "urt,umsh-8596md-11t",
2747 .data = &urt_umsh_8596md_lvds,
2748 }, {
2749 .compatible = "urt,umsh-8596md-19t",
2750 .data = &urt_umsh_8596md_lvds,
2751 }, {
2752 .compatible = "urt,umsh-8596md-20t",
2753 .data = &urt_umsh_8596md_parallel,
e4bac408
RG		 2754 }, {
2755 .compatible = "winstar,wf35ltiacd",
2756 .data = &winstar_wf35ltiacd,
280921de
TR		 2757 }, {
2758 /* sentinel */
2759 }
2760};
2761MODULE_DEVICE_TABLE(of, platform_of_match);
2762
2763static int panel_simple_platform_probe(struct platform_device *pdev)
2764{
2765 const struct of_device_id *id;
2766
2767 id = of_match_node(platform_of_match, pdev->dev.of_node);
2768 if (!id)
2769 return -ENODEV;
2770
2771 return panel_simple_probe(&pdev->dev, id->data);
2772}
2773
2774static int panel_simple_platform_remove(struct platform_device *pdev)
2775{
2776 return panel_simple_remove(&pdev->dev);
2777}
2778
d02fd93e
TR		 2779static void panel_simple_platform_shutdown(struct platform_device *pdev)
2780{
2781 panel_simple_shutdown(&pdev->dev);
2782}
2783
280921de
TR		 2784static struct platform_driver panel_simple_platform_driver = {
2785 .driver = {
2786 .name = "panel-simple",
280921de
TR		 2787 .of_match_table = platform_of_match,
2788 },
2789 .probe = panel_simple_platform_probe,
2790 .remove = panel_simple_platform_remove,
d02fd93e 2791 .shutdown = panel_simple_platform_shutdown,
280921de
TR		 2792};
2793
210fcd9d
TR		 2794struct panel_desc_dsi {
2795 struct panel_desc desc;
2796
462658b8 2797 unsigned long flags;
210fcd9d
TR		 2798 enum mipi_dsi_pixel_format format;
2799 unsigned int lanes;
2800};
2801
d718d79e
TR		 2802static const struct drm_display_mode auo_b080uan01_mode = {
2803 .clock = 154500,
2804 .hdisplay = 1200,
2805 .hsync_start = 1200 + 62,
2806 .hsync_end = 1200 + 62 + 4,
2807 .htotal = 1200 + 62 + 4 + 62,
2808 .vdisplay = 1920,
2809 .vsync_start = 1920 + 9,
2810 .vsync_end = 1920 + 9 + 2,
2811 .vtotal = 1920 + 9 + 2 + 8,
2812 .vrefresh = 60,
2813};
2814
2815static const struct panel_desc_dsi auo_b080uan01 = {
2816 .desc = {
2817 .modes = &auo_b080uan01_mode,
2818 .num_modes = 1,
2819 .bpc = 8,
2820 .size = {
2821 .width = 108,
2822 .height = 272,
2823 },
2824 },
2825 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
2826 .format = MIPI_DSI_FMT_RGB888,
2827 .lanes = 4,
2828};
2829
c8521969
CZ		 2830static const struct drm_display_mode boe_tv080wum_nl0_mode = {
2831 .clock = 160000,
2832 .hdisplay = 1200,
2833 .hsync_start = 1200 + 120,
2834 .hsync_end = 1200 + 120 + 20,
2835 .htotal = 1200 + 120 + 20 + 21,
2836 .vdisplay = 1920,
2837 .vsync_start = 1920 + 21,
2838 .vsync_end = 1920 + 21 + 3,
2839 .vtotal = 1920 + 21 + 3 + 18,
2840 .vrefresh = 60,
2841 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2842};
2843
2844static const struct panel_desc_dsi boe_tv080wum_nl0 = {
2845 .desc = {
2846 .modes = &boe_tv080wum_nl0_mode,
2847 .num_modes = 1,
2848 .size = {
2849 .width = 107,
2850 .height = 172,
2851 },
2852 },
2853 .flags = MIPI_DSI_MODE_VIDEO |
2854 MIPI_DSI_MODE_VIDEO_BURST |
2855 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
2856 .format = MIPI_DSI_FMT_RGB888,
2857 .lanes = 4,
2858};
2859
712ac1ba
AC		 2860static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
2861 .clock = 71000,
2862 .hdisplay = 800,
2863 .hsync_start = 800 + 32,
2864 .hsync_end = 800 + 32 + 1,
2865 .htotal = 800 + 32 + 1 + 57,
2866 .vdisplay = 1280,
2867 .vsync_start = 1280 + 28,
2868 .vsync_end = 1280 + 28 + 1,
2869 .vtotal = 1280 + 28 + 1 + 14,
2870 .vrefresh = 60,
2871};
2872
2873static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
2874 .desc = {
2875 .modes = &lg_ld070wx3_sl01_mode,
2876 .num_modes = 1,
d7a839cd 2877 .bpc = 8,
712ac1ba
AC		 2878 .size = {
2879 .width = 94,
2880 .height = 151,
2881 },
2882 },
5e4cc278 2883 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
712ac1ba
AC		 2884 .format = MIPI_DSI_FMT_RGB888,
2885 .lanes = 4,
2886};
2887
499ce85a
AC		 2888static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
2889 .clock = 67000,
2890 .hdisplay = 720,
2891 .hsync_start = 720 + 12,
2892 .hsync_end = 720 + 12 + 4,
2893 .htotal = 720 + 12 + 4 + 112,
2894 .vdisplay = 1280,
2895 .vsync_start = 1280 + 8,
2896 .vsync_end = 1280 + 8 + 4,
2897 .vtotal = 1280 + 8 + 4 + 12,
2898 .vrefresh = 60,
2899};
2900
2901static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
2902 .desc = {
2903 .modes = &lg_lh500wx1_sd03_mode,
2904 .num_modes = 1,
d7a839cd 2905 .bpc = 8,
499ce85a
AC		 2906 .size = {
2907 .width = 62,
2908 .height = 110,
2909 },
2910 },
2911 .flags = MIPI_DSI_MODE_VIDEO,
2912 .format = MIPI_DSI_FMT_RGB888,
2913 .lanes = 4,
2914};
2915
280921de
TR		 2916static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
2917 .clock = 157200,
2918 .hdisplay = 1920,
2919 .hsync_start = 1920 + 154,
2920 .hsync_end = 1920 + 154 + 16,
2921 .htotal = 1920 + 154 + 16 + 32,
2922 .vdisplay = 1200,
2923 .vsync_start = 1200 + 17,
2924 .vsync_end = 1200 + 17 + 2,
2925 .vtotal = 1200 + 17 + 2 + 16,
2926 .vrefresh = 60,
2927};
2928
210fcd9d
TR		 2929static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
2930 .desc = {
2931 .modes = &panasonic_vvx10f004b00_mode,
2932 .num_modes = 1,
d7a839cd 2933 .bpc = 8,
210fcd9d
TR		 2934 .size = {
2935 .width = 217,
2936 .height = 136,
2937 },
280921de 2938 },
5e4cc278
AC		 2939 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
2940 MIPI_DSI_CLOCK_NON_CONTINUOUS,
210fcd9d
TR		 2941 .format = MIPI_DSI_FMT_RGB888,
2942 .lanes = 4,
2943};
2944
2945static const struct of_device_id dsi_of_match[] = {
2946 {
d718d79e
TR		 2947 .compatible = "auo,b080uan01",
2948 .data = &auo_b080uan01
c8521969
CZ		 2949 }, {
2950 .compatible = "boe,tv080wum-nl0",
2951 .data = &boe_tv080wum_nl0
d718d79e 2952 }, {
712ac1ba
AC		 2953 .compatible = "lg,ld070wx3-sl01",
2954 .data = &lg_ld070wx3_sl01
2955 }, {
499ce85a
AC		 2956 .compatible = "lg,lh500wx1-sd03",
2957 .data = &lg_lh500wx1_sd03
2958 }, {
210fcd9d
TR		 2959 .compatible = "panasonic,vvx10f004b00",
2960 .data = &panasonic_vvx10f004b00
2961 }, {
2962 /* sentinel */
2963 }
2964};
2965MODULE_DEVICE_TABLE(of, dsi_of_match);
2966
2967static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
2968{
2969 const struct panel_desc_dsi *desc;
2970 const struct of_device_id *id;
2971 int err;
2972
2973 id = of_match_node(dsi_of_match, dsi->dev.of_node);
2974 if (!id)
2975 return -ENODEV;
2976
2977 desc = id->data;
2978
2979 err = panel_simple_probe(&dsi->dev, &desc->desc);
2980 if (err < 0)
2981 return err;
2982
462658b8 2983 dsi->mode_flags = desc->flags;
210fcd9d
TR		 2984 dsi->format = desc->format;
2985 dsi->lanes = desc->lanes;
2986
2987 return mipi_dsi_attach(dsi);
2988}
2989
2990static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
2991{
2992 int err;
2993
2994 err = mipi_dsi_detach(dsi);
2995 if (err < 0)
2996 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
2997
2998 return panel_simple_remove(&dsi->dev);
2999}
3000
d02fd93e
TR		 3001static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
3002{
3003 panel_simple_shutdown(&dsi->dev);
3004}
3005
210fcd9d
TR		 3006static struct mipi_dsi_driver panel_simple_dsi_driver = {
3007 .driver = {
3008 .name = "panel-simple-dsi",
210fcd9d
TR		 3009 .of_match_table = dsi_of_match,
3010 },
3011 .probe = panel_simple_dsi_probe,
3012 .remove = panel_simple_dsi_remove,
d02fd93e 3013 .shutdown = panel_simple_dsi_shutdown,
280921de
TR		 3014};
3015
3016static int __init panel_simple_init(void)
3017{
210fcd9d
TR		 3018 int err;
3019
3020 err = platform_driver_register(&panel_simple_platform_driver);
3021 if (err < 0)
3022 return err;
3023
3024 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
3025 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
3026 if (err < 0)
3027 return err;
3028 }
3029
3030 return 0;
280921de
TR		 3031}
3032module_init(panel_simple_init);
3033
3034static void __exit panel_simple_exit(void)
3035{
210fcd9d
TR		 3036 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
3037 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
3038
280921de
TR		 3039 platform_driver_unregister(&panel_simple_platform_driver);
3040}
3041module_exit(panel_simple_exit);
3042
3043MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
3044MODULE_DESCRIPTION("DRM Driver for Simple Panels");
3045MODULE_LICENSE("GPL and additional rights");
Ubuntu Disco kernel mirror for Proxmox VE and PMG