[mirror_ubuntu-disco-kernel.git] / drivers / gpu / drm / rockchip / analogix_dp-rockchip.c

/*
 * Rockchip SoC DP (Display Port) interface driver.
 *
 * Copyright (C) Fuzhou Rockchip Electronics Co., Ltd.
 * Author: Andy Yan <andy.yan@rock-chips.com>
 *         Yakir Yang <ykk@rock-chips.com>
 *         Jeff Chen <jeff.chen@rock-chips.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 */

#include <linux/component.h>
#include <linux/mfd/syscon.h>
#include <linux/of_device.h>
#include <linux/of_graph.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/clk.h>

#include <drm/drmP.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_dp_helper.h>
#include <drm/drm_of.h>
#include <drm/drm_panel.h>

#include <video/of_videomode.h>
#include <video/videomode.h>

#include <drm/bridge/analogix_dp.h>

#include "rockchip_drm_drv.h"
#include "rockchip_drm_psr.h"
#include "rockchip_drm_vop.h"

#define RK3288_GRF_SOC_CON6		0x25c
#define RK3288_EDP_LCDC_SEL		BIT(5)
#define RK3399_GRF_SOC_CON20		0x6250
#define RK3399_EDP_LCDC_SEL		BIT(5)

#define HIWORD_UPDATE(val, mask)	(val | (mask) << 16)

#define PSR_WAIT_LINE_FLAG_TIMEOUT_MS	100

#define to_dp(nm)	container_of(nm, struct rockchip_dp_device, nm)

/**
 * struct rockchip_dp_chip_data - splite the grf setting of kind of chips
 * @lcdsel_grf_reg: grf register offset of lcdc select
 * @lcdsel_big: reg value of selecting vop big for eDP
 * @lcdsel_lit: reg value of selecting vop little for eDP
 * @chip_type: specific chip type
 */
struct rockchip_dp_chip_data {
	u32	lcdsel_grf_reg;
	u32	lcdsel_big;
	u32	lcdsel_lit;
	u32	chip_type;
};

struct rockchip_dp_device {
	struct drm_device        *drm_dev;
	struct device            *dev;
	struct drm_encoder       encoder;
	struct drm_display_mode  mode;

	struct clk               *pclk;
	struct clk               *grfclk;
	struct regmap            *grf;
	struct reset_control     *rst;

	const struct rockchip_dp_chip_data *data;

	struct analogix_dp_device *adp;
	struct analogix_dp_plat_data plat_data;
};

static int analogix_dp_psr_set(struct drm_encoder *encoder, bool enabled)
{
	struct rockchip_dp_device *dp = to_dp(encoder);
	int ret;

	if (!analogix_dp_psr_enabled(dp->adp))
		return 0;

	DRM_DEV_DEBUG(dp->dev, "%s PSR...\n", enabled ? "Entry" : "Exit");

	ret = rockchip_drm_wait_vact_end(dp->encoder.crtc,
					 PSR_WAIT_LINE_FLAG_TIMEOUT_MS);
	if (ret) {
		DRM_DEV_ERROR(dp->dev, "line flag interrupt did not arrive\n");
		return -ETIMEDOUT;
	}

	if (enabled)
		return analogix_dp_enable_psr(dp->adp);
	else
		return analogix_dp_disable_psr(dp->adp);
}

static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
{
	reset_control_assert(dp->rst);
	usleep_range(10, 20);
	reset_control_deassert(dp->rst);

	return 0;
}

static int rockchip_dp_poweron_start(struct analogix_dp_plat_data *plat_data)
{
	struct rockchip_dp_device *dp = to_dp(plat_data);
	int ret;

	ret = clk_prepare_enable(dp->pclk);
	if (ret < 0) {
		DRM_DEV_ERROR(dp->dev, "failed to enable pclk %d\n", ret);
		return ret;
	}

	ret = rockchip_dp_pre_init(dp);
	if (ret < 0) {
		DRM_DEV_ERROR(dp->dev, "failed to dp pre init %d\n", ret);
		clk_disable_unprepare(dp->pclk);
		return ret;
	}

	return ret;
}

static int rockchip_dp_poweron_end(struct analogix_dp_plat_data *plat_data)
{
	struct rockchip_dp_device *dp = to_dp(plat_data);

	return rockchip_drm_psr_inhibit_put(&dp->encoder);
}

static int rockchip_dp_powerdown(struct analogix_dp_plat_data *plat_data)
{
	struct rockchip_dp_device *dp = to_dp(plat_data);
	int ret;

	ret = rockchip_drm_psr_inhibit_get(&dp->encoder);
	if (ret != 0)
		return ret;

	clk_disable_unprepare(dp->pclk);

	return 0;
}

static int rockchip_dp_get_modes(struct analogix_dp_plat_data *plat_data,
				 struct drm_connector *connector)
{
	struct drm_display_info *di = &connector->display_info;
	/* VOP couldn't output YUV video format for eDP rightly */
	u32 mask = DRM_COLOR_FORMAT_YCRCB444 | DRM_COLOR_FORMAT_YCRCB422;

	if ((di->color_formats & mask)) {
		DRM_DEBUG_KMS("Swapping display color format from YUV to RGB\n");
		di->color_formats &= ~mask;
		di->color_formats |= DRM_COLOR_FORMAT_RGB444;
		di->bpc = 8;
	}

	return 0;
}

static bool
rockchip_dp_drm_encoder_mode_fixup(struct drm_encoder *encoder,
				   const struct drm_display_mode *mode,
				   struct drm_display_mode *adjusted_mode)
{
	/* do nothing */
	return true;
}

static void rockchip_dp_drm_encoder_mode_set(struct drm_encoder *encoder,
					     struct drm_display_mode *mode,
					     struct drm_display_mode *adjusted)
{
	/* do nothing */
}

static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder)
{
	struct rockchip_dp_device *dp = to_dp(encoder);
	int ret;
	u32 val;

	ret = drm_of_encoder_active_endpoint_id(dp->dev->of_node, encoder);
	if (ret < 0)
		return;

	if (ret)
		val = dp->data->lcdsel_lit;
	else
		val = dp->data->lcdsel_big;

	DRM_DEV_DEBUG(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG");

	ret = clk_prepare_enable(dp->grfclk);
	if (ret < 0) {
		DRM_DEV_ERROR(dp->dev, "failed to enable grfclk %d\n", ret);
		return;
	}

	ret = regmap_write(dp->grf, dp->data->lcdsel_grf_reg, val);
	if (ret != 0)
		DRM_DEV_ERROR(dp->dev, "Could not write to GRF: %d\n", ret);

	clk_disable_unprepare(dp->grfclk);
}

static void rockchip_dp_drm_encoder_nop(struct drm_encoder *encoder)
{
	/* do nothing */
}

static int
rockchip_dp_drm_encoder_atomic_check(struct drm_encoder *encoder,
				      struct drm_crtc_state *crtc_state,
				      struct drm_connector_state *conn_state)
{
	struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
	struct drm_display_info *di = &conn_state->connector->display_info;

	/*
	 * The hardware IC designed that VOP must output the RGB10 video
	 * format to eDP controller, and if eDP panel only support RGB8,
	 * then eDP controller should cut down the video data, not via VOP
	 * controller, that's why we need to hardcode the VOP output mode
	 * to RGA10 here.
	 */

	s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
	s->output_type = DRM_MODE_CONNECTOR_eDP;
	s->output_bpc = di->bpc;

	return 0;
}

static struct drm_encoder_helper_funcs rockchip_dp_encoder_helper_funcs = {
	.mode_fixup = rockchip_dp_drm_encoder_mode_fixup,
	.mode_set = rockchip_dp_drm_encoder_mode_set,
	.enable = rockchip_dp_drm_encoder_enable,
	.disable = rockchip_dp_drm_encoder_nop,
	.atomic_check = rockchip_dp_drm_encoder_atomic_check,
};

static struct drm_encoder_funcs rockchip_dp_encoder_funcs = {
	.destroy = drm_encoder_cleanup,
};

static int rockchip_dp_of_probe(struct rockchip_dp_device *dp)
{
	struct device *dev = dp->dev;
	struct device_node *np = dev->of_node;

	dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
	if (IS_ERR(dp->grf)) {
		DRM_DEV_ERROR(dev, "failed to get rockchip,grf property\n");
		return PTR_ERR(dp->grf);
	}

	dp->grfclk = devm_clk_get(dev, "grf");
	if (PTR_ERR(dp->grfclk) == -ENOENT) {
		dp->grfclk = NULL;
	} else if (PTR_ERR(dp->grfclk) == -EPROBE_DEFER) {
		return -EPROBE_DEFER;
	} else if (IS_ERR(dp->grfclk)) {
		DRM_DEV_ERROR(dev, "failed to get grf clock\n");
		return PTR_ERR(dp->grfclk);
	}

	dp->pclk = devm_clk_get(dev, "pclk");
	if (IS_ERR(dp->pclk)) {
		DRM_DEV_ERROR(dev, "failed to get pclk property\n");
		return PTR_ERR(dp->pclk);
	}

	dp->rst = devm_reset_control_get(dev, "dp");
	if (IS_ERR(dp->rst)) {
		DRM_DEV_ERROR(dev, "failed to get dp reset control\n");
		return PTR_ERR(dp->rst);
	}

	return 0;
}

static int rockchip_dp_drm_create_encoder(struct rockchip_dp_device *dp)
{
	struct drm_encoder *encoder = &dp->encoder;
	struct drm_device *drm_dev = dp->drm_dev;
	struct device *dev = dp->dev;
	int ret;

	encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
							     dev->of_node);
	DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);

	ret = drm_encoder_init(drm_dev, encoder, &rockchip_dp_encoder_funcs,
			       DRM_MODE_ENCODER_TMDS, NULL);
	if (ret) {
		DRM_ERROR("failed to initialize encoder with drm\n");
		return ret;
	}

	drm_encoder_helper_add(encoder, &rockchip_dp_encoder_helper_funcs);

	return 0;
}

static int rockchip_dp_bind(struct device *dev, struct device *master,
			    void *data)
{
	struct rockchip_dp_device *dp = dev_get_drvdata(dev);
	const struct rockchip_dp_chip_data *dp_data;
	struct drm_device *drm_dev = data;
	int ret;

	dp_data = of_device_get_match_data(dev);
	if (!dp_data)
		return -ENODEV;

	dp->data = dp_data;
	dp->drm_dev = drm_dev;

	ret = rockchip_dp_drm_create_encoder(dp);
	if (ret) {
		DRM_ERROR("failed to create drm encoder\n");
		return ret;
	}

	dp->plat_data.encoder = &dp->encoder;

	dp->plat_data.dev_type = dp->data->chip_type;
	dp->plat_data.power_on_start = rockchip_dp_poweron_start;
	dp->plat_data.power_on_end = rockchip_dp_poweron_end;
	dp->plat_data.power_off = rockchip_dp_powerdown;
	dp->plat_data.get_modes = rockchip_dp_get_modes;

	ret = rockchip_drm_psr_register(&dp->encoder, analogix_dp_psr_set);
	if (ret < 0)
		goto err_cleanup_encoder;

	dp->adp = analogix_dp_bind(dev, dp->drm_dev, &dp->plat_data);
	if (IS_ERR(dp->adp)) {
		ret = PTR_ERR(dp->adp);
		goto err_unreg_psr;
	}

	return 0;
err_unreg_psr:
	rockchip_drm_psr_unregister(&dp->encoder);
err_cleanup_encoder:
	dp->encoder.funcs->destroy(&dp->encoder);
	return ret;
}

static void rockchip_dp_unbind(struct device *dev, struct device *master,
			       void *data)
{
	struct rockchip_dp_device *dp = dev_get_drvdata(dev);

	analogix_dp_unbind(dp->adp);
	rockchip_drm_psr_unregister(&dp->encoder);
	dp->encoder.funcs->destroy(&dp->encoder);

	dp->adp = ERR_PTR(-ENODEV);
}

static const struct component_ops rockchip_dp_component_ops = {
	.bind = rockchip_dp_bind,
	.unbind = rockchip_dp_unbind,
};

static int rockchip_dp_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct drm_panel *panel = NULL;
	struct rockchip_dp_device *dp;
	int ret;

	ret = drm_of_find_panel_or_bridge(dev->of_node, 1, 0, &panel, NULL);
	if (ret < 0)
		return ret;

	dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
	if (!dp)
		return -ENOMEM;

	dp->dev = dev;
	dp->adp = ERR_PTR(-ENODEV);
	dp->plat_data.panel = panel;

	ret = rockchip_dp_of_probe(dp);
	if (ret < 0)
		return ret;

	platform_set_drvdata(pdev, dp);

	return component_add(dev, &rockchip_dp_component_ops);
}

static int rockchip_dp_remove(struct platform_device *pdev)
{
	component_del(&pdev->dev, &rockchip_dp_component_ops);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int rockchip_dp_suspend(struct device *dev)
{
	struct rockchip_dp_device *dp = dev_get_drvdata(dev);

	if (IS_ERR(dp->adp))
		return 0;

	return analogix_dp_suspend(dp->adp);
}

static int rockchip_dp_resume(struct device *dev)
{
	struct rockchip_dp_device *dp = dev_get_drvdata(dev);

	if (IS_ERR(dp->adp))
		return 0;

	return analogix_dp_resume(dp->adp);
}
#endif

static const struct dev_pm_ops rockchip_dp_pm_ops = {
#ifdef CONFIG_PM_SLEEP
	.suspend = rockchip_dp_suspend,
	.resume_early = rockchip_dp_resume,
#endif
};

static const struct rockchip_dp_chip_data rk3399_edp = {
	.lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
	.lcdsel_big = HIWORD_UPDATE(0, RK3399_EDP_LCDC_SEL),
	.lcdsel_lit = HIWORD_UPDATE(RK3399_EDP_LCDC_SEL, RK3399_EDP_LCDC_SEL),
	.chip_type = RK3399_EDP,
};

static const struct rockchip_dp_chip_data rk3288_dp = {
	.lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
	.lcdsel_big = HIWORD_UPDATE(0, RK3288_EDP_LCDC_SEL),
	.lcdsel_lit = HIWORD_UPDATE(RK3288_EDP_LCDC_SEL, RK3288_EDP_LCDC_SEL),
	.chip_type = RK3288_DP,
};

static const struct of_device_id rockchip_dp_dt_ids[] = {
	{.compatible = "rockchip,rk3288-dp", .data = &rk3288_dp },
	{.compatible = "rockchip,rk3399-edp", .data = &rk3399_edp },
	{}
};
MODULE_DEVICE_TABLE(of, rockchip_dp_dt_ids);

struct platform_driver rockchip_dp_driver = {
	.probe = rockchip_dp_probe,
	.remove = rockchip_dp_remove,
	.driver = {
		   .name = "rockchip-dp",
		   .pm = &rockchip_dp_pm_ops,
		   .of_match_table = of_match_ptr(rockchip_dp_dt_ids),
	},
};
Commit	Line	Data
9e32e16e YY	1	/*
	2	* Rockchip SoC DP (Display Port) interface driver.
	3	*
	4	* Copyright (C) Fuzhou Rockchip Electronics Co., Ltd.
	5	* Author: Andy Yan <andy.yan@rock-chips.com>
	6	* Yakir Yang <ykk@rock-chips.com>
	7	* Jeff Chen <jeff.chen@rock-chips.com>
	8	*
	9	* This program is free software; you can redistribute it and/or modify it
	10	* under the terms of the GNU General Public License as published by the
	11	* Free Software Foundation; either version 2 of the License, or (at your
	12	* option) any later version.
	13	*/
	14
	15	#include <linux/component.h>
	16	#include <linux/mfd/syscon.h>
d9c900b0	17	#include <linux/of_device.h>
9e32e16e YY	18	#include <linux/of_graph.h>
	19	#include <linux/regmap.h>
	20	#include <linux/reset.h>
	21	#include <linux/clk.h>
	22
	23	#include <drm/drmP.h>
	24	#include <drm/drm_crtc_helper.h>
	25	#include <drm/drm_dp_helper.h>
	26	#include <drm/drm_of.h>
	27	#include <drm/drm_panel.h>
	28
	29	#include <video/of_videomode.h>
	30	#include <video/videomode.h>
	31
	32	#include <drm/bridge/analogix_dp.h>
	33
	34	#include "rockchip_drm_drv.h"
8f0ac5c4	35	#include "rockchip_drm_psr.h"
9e32e16e YY	36	#include "rockchip_drm_vop.h"
9e32e16e YY	37
d9c900b0 YY	38	#define RK3288_GRF_SOC_CON6 0x25c
d9c900b0 YY	39	#define RK3288_EDP_LCDC_SEL BIT(5)
82872e42 YY	40	#define RK3399_GRF_SOC_CON20 0x6250
82872e42 YY	41	#define RK3399_EDP_LCDC_SEL BIT(5)
d9c900b0 YY	42
	43	#define HIWORD_UPDATE(val, mask) (val \| (mask) << 16)
	44
8f0ac5c4 YY	45	#define PSR_WAIT_LINE_FLAG_TIMEOUT_MS 100
8f0ac5c4 YY	46
9e32e16e YY	47	#define to_dp(nm) container_of(nm, struct rockchip_dp_device, nm)
9e32e16e YY	48
d9c900b0 YY	49	/**
	50	* struct rockchip_dp_chip_data - splite the grf setting of kind of chips
	51	* @lcdsel_grf_reg: grf register offset of lcdc select
	52	* @lcdsel_big: reg value of selecting vop big for eDP
	53	* @lcdsel_lit: reg value of selecting vop little for eDP
	54	* @chip_type: specific chip type
	55	*/
	56	struct rockchip_dp_chip_data {
	57	u32 lcdsel_grf_reg;
	58	u32 lcdsel_big;
	59	u32 lcdsel_lit;
	60	u32 chip_type;
	61	};
9e32e16e YY	62
	63	struct rockchip_dp_device {
	64	struct drm_device *drm_dev;
	65	struct device *dev;
	66	struct drm_encoder encoder;
	67	struct drm_display_mode mode;
	68
	69	struct clk *pclk;
dc1c93be	70	struct clk *grfclk;
9e32e16e YY	71	struct regmap *grf;
	72	struct reset_control *rst;
	73
d9c900b0 YY	74	const struct rockchip_dp_chip_data *data;
d9c900b0 YY	75
6b2d8fd9	76	struct analogix_dp_device *adp;
9e32e16e YY	77	struct analogix_dp_plat_data plat_data;
	78	};
	79
2a7b44c5	80	static int analogix_dp_psr_set(struct drm_encoder *encoder, bool enabled)
8f0ac5c4 YY	81	{
8f0ac5c4 YY	82	struct rockchip_dp_device *dp = to_dp(encoder);
baa2f024	83	int ret;
8f0ac5c4	84
243e398a	85	if (!analogix_dp_psr_enabled(dp->adp))
2a7b44c5	86	return 0;
0546d685	87
d8dd6804	88	DRM_DEV_DEBUG(dp->dev, "%s PSR...\n", enabled ? "Entry" : "Exit");
8f0ac5c4	89
459b086d JC	90	ret = rockchip_drm_wait_vact_end(dp->encoder.crtc,
459b086d JC	91	PSR_WAIT_LINE_FLAG_TIMEOUT_MS);
8f0ac5c4	92	if (ret) {
d8dd6804	93	DRM_DEV_ERROR(dp->dev, "line flag interrupt did not arrive\n");
2a7b44c5	94	return -ETIMEDOUT;
8f0ac5c4 YY	95	}
8f0ac5c4 YY	96
baa2f024	97	if (enabled)
2a7b44c5	98	return analogix_dp_enable_psr(dp->adp);
8f0ac5c4	99	else
2a7b44c5	100	return analogix_dp_disable_psr(dp->adp);
8f0ac5c4 YY	101	}
8f0ac5c4 YY	102
9e32e16e YY	103	static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
	104	{
	105	reset_control_assert(dp->rst);
	106	usleep_range(10, 20);
	107	reset_control_deassert(dp->rst);
	108
	109	return 0;
	110	}
	111
7bb3bb4d	112	static int rockchip_dp_poweron_start(struct analogix_dp_plat_data *plat_data)
9e32e16e YY	113	{
	114	struct rockchip_dp_device *dp = to_dp(plat_data);
	115	int ret;
	116
	117	ret = clk_prepare_enable(dp->pclk);
	118	if (ret < 0) {
d8dd6804	119	DRM_DEV_ERROR(dp->dev, "failed to enable pclk %d\n", ret);
9e32e16e YY	120	return ret;
	121	}
	122
	123	ret = rockchip_dp_pre_init(dp);
	124	if (ret < 0) {
d8dd6804	125	DRM_DEV_ERROR(dp->dev, "failed to dp pre init %d\n", ret);
3694c5c3	126	clk_disable_unprepare(dp->pclk);
9e32e16e YY	127	return ret;
	128	}
	129
7bb3bb4d DA	130	return ret;
	131	}
	132
	133	static int rockchip_dp_poweron_end(struct analogix_dp_plat_data *plat_data)
	134	{
	135	struct rockchip_dp_device *dp = to_dp(plat_data);
	136
6e6cf3e2	137	return rockchip_drm_psr_inhibit_put(&dp->encoder);
9e32e16e YY	138	}
	139
	140	static int rockchip_dp_powerdown(struct analogix_dp_plat_data *plat_data)
	141	{
	142	struct rockchip_dp_device *dp = to_dp(plat_data);
7f3c191b	143	int ret;
7f3c191b	144
6e6cf3e2	145	ret = rockchip_drm_psr_inhibit_get(&dp->encoder);
7f3c191b	146	if (ret != 0)
7f3c191b	147	return ret;
9e32e16e YY	148
	149	clk_disable_unprepare(dp->pclk);
	150
	151	return 0;
	152	}
	153
db8a9aed YY	154	static int rockchip_dp_get_modes(struct analogix_dp_plat_data *plat_data,
	155	struct drm_connector *connector)
	156	{
	157	struct drm_display_info *di = &connector->display_info;
	158	/* VOP couldn't output YUV video format for eDP rightly */
	159	u32 mask = DRM_COLOR_FORMAT_YCRCB444 \| DRM_COLOR_FORMAT_YCRCB422;
	160
	161	if ((di->color_formats & mask)) {
	162	DRM_DEBUG_KMS("Swapping display color format from YUV to RGB\n");
	163	di->color_formats &= ~mask;
	164	di->color_formats \|= DRM_COLOR_FORMAT_RGB444;
	165	di->bpc = 8;
	166	}
	167
	168	return 0;
	169	}
	170
9e32e16e YY	171	static bool
	172	rockchip_dp_drm_encoder_mode_fixup(struct drm_encoder *encoder,
	173	const struct drm_display_mode *mode,
	174	struct drm_display_mode *adjusted_mode)
	175	{
	176	/* do nothing */
	177	return true;
	178	}
	179
	180	static void rockchip_dp_drm_encoder_mode_set(struct drm_encoder *encoder,
	181	struct drm_display_mode *mode,
	182	struct drm_display_mode *adjusted)
	183	{
	184	/* do nothing */
	185	}
	186
	187	static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder)
	188	{
	189	struct rockchip_dp_device *dp = to_dp(encoder);
	190	int ret;
	191	u32 val;
	192
9e32e16e YY	193	ret = drm_of_encoder_active_endpoint_id(dp->dev->of_node, encoder);
	194	if (ret < 0)
	195	return;
	196
	197	if (ret)
d9c900b0	198	val = dp->data->lcdsel_lit;
9e32e16e	199	else
d9c900b0	200	val = dp->data->lcdsel_big;
9e32e16e	201
d8dd6804	202	DRM_DEV_DEBUG(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG");
9e32e16e	203
dc1c93be YY	204	ret = clk_prepare_enable(dp->grfclk);
dc1c93be YY	205	if (ret < 0) {
d8dd6804	206	DRM_DEV_ERROR(dp->dev, "failed to enable grfclk %d\n", ret);
9e32e16e YY	207	return;
9e32e16e YY	208	}
dc1c93be YY	209
	210	ret = regmap_write(dp->grf, dp->data->lcdsel_grf_reg, val);
	211	if (ret != 0)
d8dd6804	212	DRM_DEV_ERROR(dp->dev, "Could not write to GRF: %d\n", ret);
dc1c93be YY	213
dc1c93be YY	214	clk_disable_unprepare(dp->grfclk);
9e32e16e YY	215	}
	216
	217	static void rockchip_dp_drm_encoder_nop(struct drm_encoder *encoder)
	218	{
	219	/* do nothing */
	220	}
	221
4e257d9e MY	222	static int
	223	rockchip_dp_drm_encoder_atomic_check(struct drm_encoder *encoder,
	224	struct drm_crtc_state *crtc_state,
	225	struct drm_connector_state *conn_state)
	226	{
	227	struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
6bda8112	228	struct drm_display_info *di = &conn_state->connector->display_info;
4e257d9e MY	229
4e257d9e MY	230	/*
d698f0eb YY	231	* The hardware IC designed that VOP must output the RGB10 video
	232	* format to eDP controller, and if eDP panel only support RGB8,
	233	* then eDP controller should cut down the video data, not via VOP
	234	* controller, that's why we need to hardcode the VOP output mode
	235	* to RGA10 here.
4e257d9e	236	*/
82872e42	237
4e257d9e MY	238	s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
4e257d9e MY	239	s->output_type = DRM_MODE_CONNECTOR_eDP;
6bda8112	240	s->output_bpc = di->bpc;
4e257d9e MY	241
	242	return 0;
	243	}
	244
9e32e16e YY	245	static struct drm_encoder_helper_funcs rockchip_dp_encoder_helper_funcs = {
	246	.mode_fixup = rockchip_dp_drm_encoder_mode_fixup,
	247	.mode_set = rockchip_dp_drm_encoder_mode_set,
	248	.enable = rockchip_dp_drm_encoder_enable,
	249	.disable = rockchip_dp_drm_encoder_nop,
4e257d9e	250	.atomic_check = rockchip_dp_drm_encoder_atomic_check,
9e32e16e YY	251	};
9e32e16e YY	252
9e32e16e	253	static struct drm_encoder_funcs rockchip_dp_encoder_funcs = {
7fe201cd	254	.destroy = drm_encoder_cleanup,
9e32e16e YY	255	};
9e32e16e YY	256
102712a3	257	static int rockchip_dp_of_probe(struct rockchip_dp_device *dp)
9e32e16e YY	258	{
	259	struct device *dev = dp->dev;
	260	struct device_node *np = dev->of_node;
9e32e16e YY	261
	262	dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
	263	if (IS_ERR(dp->grf)) {
d8dd6804	264	DRM_DEV_ERROR(dev, "failed to get rockchip,grf property\n");
9e32e16e YY	265	return PTR_ERR(dp->grf);
	266	}
	267
dc1c93be YY	268	dp->grfclk = devm_clk_get(dev, "grf");
	269	if (PTR_ERR(dp->grfclk) == -ENOENT) {
	270	dp->grfclk = NULL;
	271	} else if (PTR_ERR(dp->grfclk) == -EPROBE_DEFER) {
	272	return -EPROBE_DEFER;
	273	} else if (IS_ERR(dp->grfclk)) {
d8dd6804	274	DRM_DEV_ERROR(dev, "failed to get grf clock\n");
dc1c93be YY	275	return PTR_ERR(dp->grfclk);
	276	}
	277
9e32e16e YY	278	dp->pclk = devm_clk_get(dev, "pclk");
9e32e16e YY	279	if (IS_ERR(dp->pclk)) {
d8dd6804	280	DRM_DEV_ERROR(dev, "failed to get pclk property\n");
9e32e16e YY	281	return PTR_ERR(dp->pclk);
	282	}
	283
	284	dp->rst = devm_reset_control_get(dev, "dp");
	285	if (IS_ERR(dp->rst)) {
d8dd6804	286	DRM_DEV_ERROR(dev, "failed to get dp reset control\n");
9e32e16e YY	287	return PTR_ERR(dp->rst);
	288	}
	289
9e32e16e YY	290	return 0;
	291	}
	292
	293	static int rockchip_dp_drm_create_encoder(struct rockchip_dp_device *dp)
	294	{
	295	struct drm_encoder *encoder = &dp->encoder;
	296	struct drm_device *drm_dev = dp->drm_dev;
	297	struct device *dev = dp->dev;
	298	int ret;
	299
	300	encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
	301	dev->of_node);
	302	DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
	303
	304	ret = drm_encoder_init(drm_dev, encoder, &rockchip_dp_encoder_funcs,
	305	DRM_MODE_ENCODER_TMDS, NULL);
	306	if (ret) {
	307	DRM_ERROR("failed to initialize encoder with drm\n");
	308	return ret;
	309	}
	310
	311	drm_encoder_helper_add(encoder, &rockchip_dp_encoder_helper_funcs);
	312
	313	return 0;
	314	}
	315
	316	static int rockchip_dp_bind(struct device dev, struct device master,
	317	void *data)
	318	{
	319	struct rockchip_dp_device *dp = dev_get_drvdata(dev);
d9c900b0	320	const struct rockchip_dp_chip_data *dp_data;
9e32e16e YY	321	struct drm_device *drm_dev = data;
	322	int ret;
	323
d9c900b0 YY	324	dp_data = of_device_get_match_data(dev);
	325	if (!dp_data)
	326	return -ENODEV;
	327
d9c900b0	328	dp->data = dp_data;
9e32e16e YY	329	dp->drm_dev = drm_dev;
	330
	331	ret = rockchip_dp_drm_create_encoder(dp);
	332	if (ret) {
	333	DRM_ERROR("failed to create drm encoder\n");
	334	return ret;
	335	}
	336
	337	dp->plat_data.encoder = &dp->encoder;
	338
d9c900b0	339	dp->plat_data.dev_type = dp->data->chip_type;
7bb3bb4d DA	340	dp->plat_data.power_on_start = rockchip_dp_poweron_start;
7bb3bb4d DA	341	dp->plat_data.power_on_end = rockchip_dp_poweron_end;
9e32e16e	342	dp->plat_data.power_off = rockchip_dp_powerdown;
db8a9aed	343	dp->plat_data.get_modes = rockchip_dp_get_modes;
9e32e16e	344
c8c04514 JC	345	ret = rockchip_drm_psr_register(&dp->encoder, analogix_dp_psr_set);
	346	if (ret < 0)
	347	goto err_cleanup_encoder;
8f0ac5c4	348
6b2d8fd9	349	dp->adp = analogix_dp_bind(dev, dp->drm_dev, &dp->plat_data);
7fe201cd	350	if (IS_ERR(dp->adp)) {
c8c04514 JC	351	ret = PTR_ERR(dp->adp);
c8c04514 JC	352	goto err_unreg_psr;
7fe201cd	353	}
6b2d8fd9 JC	354
6b2d8fd9 JC	355	return 0;
c8c04514 JC	356	err_unreg_psr:
	357	rockchip_drm_psr_unregister(&dp->encoder);
	358	err_cleanup_encoder:
	359	dp->encoder.funcs->destroy(&dp->encoder);
	360	return ret;
9e32e16e YY	361	}
	362
	363	static void rockchip_dp_unbind(struct device dev, struct device master,
	364	void *data)
	365	{
8f0ac5c4 YY	366	struct rockchip_dp_device *dp = dev_get_drvdata(dev);
8f0ac5c4 YY	367
6b2d8fd9	368	analogix_dp_unbind(dp->adp);
d8e7e73e	369	rockchip_drm_psr_unregister(&dp->encoder);
7fe201cd	370	dp->encoder.funcs->destroy(&dp->encoder);
a4169609 TF	371
a4169609 TF	372	dp->adp = ERR_PTR(-ENODEV);
9e32e16e YY	373	}
	374
	375	static const struct component_ops rockchip_dp_component_ops = {
	376	.bind = rockchip_dp_bind,
	377	.unbind = rockchip_dp_unbind,
	378	};
	379
	380	static int rockchip_dp_probe(struct platform_device *pdev)
	381	{
	382	struct device *dev = &pdev->dev;
eb87c91c	383	struct drm_panel *panel = NULL;
9e32e16e	384	struct rockchip_dp_device *dp;
ebc94461	385	int ret;
9e32e16e	386
ebc94461	387	ret = drm_of_find_panel_or_bridge(dev->of_node, 1, 0, &panel, NULL);
102712a3	388	if (ret < 0)
ebc94461	389	return ret;
9e32e16e	390
9e32e16e YY	391	dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
	392	if (!dp)
	393	return -ENOMEM;
	394
	395	dp->dev = dev;
a4169609	396	dp->adp = ERR_PTR(-ENODEV);
9e32e16e YY	397	dp->plat_data.panel = panel;
9e32e16e YY	398
102712a3 JC	399	ret = rockchip_dp_of_probe(dp);
	400	if (ret < 0)
	401	return ret;
	402
9e32e16e YY	403	platform_set_drvdata(pdev, dp);
	404
	405	return component_add(dev, &rockchip_dp_component_ops);
	406	}
	407
	408	static int rockchip_dp_remove(struct platform_device *pdev)
	409	{
	410	component_del(&pdev->dev, &rockchip_dp_component_ops);
	411
	412	return 0;
	413	}
	414
6b2d8fd9 JC	415	#ifdef CONFIG_PM_SLEEP
	416	static int rockchip_dp_suspend(struct device *dev)
	417	{
	418	struct rockchip_dp_device *dp = dev_get_drvdata(dev);
	419
a4169609 TF	420	if (IS_ERR(dp->adp))
	421	return 0;
	422
6b2d8fd9 JC	423	return analogix_dp_suspend(dp->adp);
	424	}
	425
	426	static int rockchip_dp_resume(struct device *dev)
	427	{
	428	struct rockchip_dp_device *dp = dev_get_drvdata(dev);
	429
a4169609 TF	430	if (IS_ERR(dp->adp))
	431	return 0;
	432
6b2d8fd9 JC	433	return analogix_dp_resume(dp->adp);
	434	}
	435	#endif
	436
fe64ba5c	437	static const struct dev_pm_ops rockchip_dp_pm_ops = {
9e32e16e	438	#ifdef CONFIG_PM_SLEEP
6b2d8fd9 JC	439	.suspend = rockchip_dp_suspend,
6b2d8fd9 JC	440	.resume_early = rockchip_dp_resume,
9e32e16e	441	#endif
9e32e16e YY	442	};
9e32e16e YY	443
82872e42 YY	444	static const struct rockchip_dp_chip_data rk3399_edp = {
	445	.lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
	446	.lcdsel_big = HIWORD_UPDATE(0, RK3399_EDP_LCDC_SEL),
	447	.lcdsel_lit = HIWORD_UPDATE(RK3399_EDP_LCDC_SEL, RK3399_EDP_LCDC_SEL),
	448	.chip_type = RK3399_EDP,
	449	};
	450
d9c900b0 YY	451	static const struct rockchip_dp_chip_data rk3288_dp = {
	452	.lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
	453	.lcdsel_big = HIWORD_UPDATE(0, RK3288_EDP_LCDC_SEL),
	454	.lcdsel_lit = HIWORD_UPDATE(RK3288_EDP_LCDC_SEL, RK3288_EDP_LCDC_SEL),
	455	.chip_type = RK3288_DP,
	456	};
	457
9e32e16e	458	static const struct of_device_id rockchip_dp_dt_ids[] = {
d9c900b0	459	{.compatible = "rockchip,rk3288-dp", .data = &rk3288_dp },
82872e42	460	{.compatible = "rockchip,rk3399-edp", .data = &rk3399_edp },
9e32e16e YY	461	{}
	462	};
	463	MODULE_DEVICE_TABLE(of, rockchip_dp_dt_ids);
	464
8820b68b	465	struct platform_driver rockchip_dp_driver = {
9e32e16e YY	466	.probe = rockchip_dp_probe,
	467	.remove = rockchip_dp_remove,
	468	.driver = {
	469	.name = "rockchip-dp",
9e32e16e YY	470	.pm = &rockchip_dp_pm_ops,
	471	.of_match_table = of_match_ptr(rockchip_dp_dt_ids),
	472	},
	473	};