[mirror_ubuntu-disco-kernel.git] / drivers / gpu / drm / rockchip / analogix_dp-rockchip.c

/*
 * Rockchip SoC DP (Display Port) interface driver.
 *
 * Copyright (C) Fuzhou Rockchip Electronics Co., Ltd.
 * Author: Andy Yan <andy.yan@rock-chips.com>
 *         Yakir Yang <ykk@rock-chips.com>
 *         Jeff Chen <jeff.chen@rock-chips.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 */

#include <linux/component.h>
#include <linux/mfd/syscon.h>
#include <linux/of_device.h>
#include <linux/of_graph.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/clk.h>

#include <drm/drmP.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_dp_helper.h>
#include <drm/drm_of.h>
#include <drm/drm_panel.h>

#include <video/of_videomode.h>
#include <video/videomode.h>

#include <drm/bridge/analogix_dp.h>

#include "rockchip_drm_drv.h"
#include "rockchip_drm_psr.h"
#include "rockchip_drm_vop.h"

#define RK3288_GRF_SOC_CON6		0x25c
#define RK3288_EDP_LCDC_SEL		BIT(5)
#define RK3399_GRF_SOC_CON20		0x6250
#define RK3399_EDP_LCDC_SEL		BIT(5)

#define HIWORD_UPDATE(val, mask)	(val | (mask) << 16)

#define PSR_WAIT_LINE_FLAG_TIMEOUT_MS	100

#define to_dp(nm)	container_of(nm, struct rockchip_dp_device, nm)

/**
 * struct rockchip_dp_chip_data - splite the grf setting of kind of chips
 * @lcdsel_grf_reg: grf register offset of lcdc select
 * @lcdsel_big: reg value of selecting vop big for eDP
 * @lcdsel_lit: reg value of selecting vop little for eDP
 * @chip_type: specific chip type
 */
struct rockchip_dp_chip_data {
	u32	lcdsel_grf_reg;
	u32	lcdsel_big;
	u32	lcdsel_lit;
	u32	chip_type;
};

struct rockchip_dp_device {
	struct drm_device        *drm_dev;
	struct device            *dev;
	struct drm_encoder       encoder;
	struct drm_display_mode  mode;

	struct clk               *pclk;
	struct clk               *grfclk;
	struct regmap            *grf;
	struct reset_control     *rst;

	struct work_struct	 psr_work;
	struct mutex             psr_lock;
	unsigned int             psr_state;

	const struct rockchip_dp_chip_data *data;

	struct analogix_dp_device *adp;
	struct analogix_dp_plat_data plat_data;
};

static void analogix_dp_psr_set(struct drm_encoder *encoder, bool enabled)
{
	struct rockchip_dp_device *dp = to_dp(encoder);

	if (!analogix_dp_psr_supported(dp->adp))
		return;

	DRM_DEV_DEBUG(dp->dev, "%s PSR...\n", enabled ? "Entry" : "Exit");

	mutex_lock(&dp->psr_lock);
	if (enabled)
		dp->psr_state = EDP_VSC_PSR_STATE_ACTIVE;
	else
		dp->psr_state = ~EDP_VSC_PSR_STATE_ACTIVE;

	schedule_work(&dp->psr_work);
	mutex_unlock(&dp->psr_lock);
}

static void analogix_dp_psr_work(struct work_struct *work)
{
	struct rockchip_dp_device *dp =
				container_of(work, typeof(*dp), psr_work);
	int ret;

	ret = rockchip_drm_wait_vact_end(dp->encoder.crtc,
					 PSR_WAIT_LINE_FLAG_TIMEOUT_MS);
	if (ret) {
		DRM_DEV_ERROR(dp->dev, "line flag interrupt did not arrive\n");
		return;
	}

	mutex_lock(&dp->psr_lock);
	if (dp->psr_state == EDP_VSC_PSR_STATE_ACTIVE)
		analogix_dp_enable_psr(dp->adp);
	else
		analogix_dp_disable_psr(dp->adp);
	mutex_unlock(&dp->psr_lock);
}

static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
{
	reset_control_assert(dp->rst);
	usleep_range(10, 20);
	reset_control_deassert(dp->rst);

	return 0;
}

static int rockchip_dp_poweron(struct analogix_dp_plat_data *plat_data)
{
	struct rockchip_dp_device *dp = to_dp(plat_data);
	int ret;

	cancel_work_sync(&dp->psr_work);

	ret = clk_prepare_enable(dp->pclk);
	if (ret < 0) {
		DRM_DEV_ERROR(dp->dev, "failed to enable pclk %d\n", ret);
		return ret;
	}

	ret = rockchip_dp_pre_init(dp);
	if (ret < 0) {
		DRM_DEV_ERROR(dp->dev, "failed to dp pre init %d\n", ret);
		clk_disable_unprepare(dp->pclk);
		return ret;
	}

	return rockchip_drm_psr_activate(&dp->encoder);
}

static int rockchip_dp_powerdown(struct analogix_dp_plat_data *plat_data)
{
	struct rockchip_dp_device *dp = to_dp(plat_data);
	int ret;

	ret = rockchip_drm_psr_deactivate(&dp->encoder);
	if (ret != 0)
		return ret;

	clk_disable_unprepare(dp->pclk);

	return 0;
}

static int rockchip_dp_get_modes(struct analogix_dp_plat_data *plat_data,
				 struct drm_connector *connector)
{
	struct drm_display_info *di = &connector->display_info;
	/* VOP couldn't output YUV video format for eDP rightly */
	u32 mask = DRM_COLOR_FORMAT_YCRCB444 | DRM_COLOR_FORMAT_YCRCB422;

	if ((di->color_formats & mask)) {
		DRM_DEBUG_KMS("Swapping display color format from YUV to RGB\n");
		di->color_formats &= ~mask;
		di->color_formats |= DRM_COLOR_FORMAT_RGB444;
		di->bpc = 8;
	}

	return 0;
}

static bool
rockchip_dp_drm_encoder_mode_fixup(struct drm_encoder *encoder,
				   const struct drm_display_mode *mode,
				   struct drm_display_mode *adjusted_mode)
{
	/* do nothing */
	return true;
}

static void rockchip_dp_drm_encoder_mode_set(struct drm_encoder *encoder,
					     struct drm_display_mode *mode,
					     struct drm_display_mode *adjusted)
{
	/* do nothing */
}

static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder)
{
	struct rockchip_dp_device *dp = to_dp(encoder);
	int ret;
	u32 val;

	ret = drm_of_encoder_active_endpoint_id(dp->dev->of_node, encoder);
	if (ret < 0)
		return;

	if (ret)
		val = dp->data->lcdsel_lit;
	else
		val = dp->data->lcdsel_big;

	DRM_DEV_DEBUG(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG");

	ret = clk_prepare_enable(dp->grfclk);
	if (ret < 0) {
		DRM_DEV_ERROR(dp->dev, "failed to enable grfclk %d\n", ret);
		return;
	}

	ret = regmap_write(dp->grf, dp->data->lcdsel_grf_reg, val);
	if (ret != 0)
		DRM_DEV_ERROR(dp->dev, "Could not write to GRF: %d\n", ret);

	clk_disable_unprepare(dp->grfclk);
}

static void rockchip_dp_drm_encoder_nop(struct drm_encoder *encoder)
{
	/* do nothing */
}

static int
rockchip_dp_drm_encoder_atomic_check(struct drm_encoder *encoder,
				      struct drm_crtc_state *crtc_state,
				      struct drm_connector_state *conn_state)
{
	struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);

	/*
	 * The hardware IC designed that VOP must output the RGB10 video
	 * format to eDP controller, and if eDP panel only support RGB8,
	 * then eDP controller should cut down the video data, not via VOP
	 * controller, that's why we need to hardcode the VOP output mode
	 * to RGA10 here.
	 */

	s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
	s->output_type = DRM_MODE_CONNECTOR_eDP;

	return 0;
}

static struct drm_encoder_helper_funcs rockchip_dp_encoder_helper_funcs = {
	.mode_fixup = rockchip_dp_drm_encoder_mode_fixup,
	.mode_set = rockchip_dp_drm_encoder_mode_set,
	.enable = rockchip_dp_drm_encoder_enable,
	.disable = rockchip_dp_drm_encoder_nop,
	.atomic_check = rockchip_dp_drm_encoder_atomic_check,
};

static struct drm_encoder_funcs rockchip_dp_encoder_funcs = {
	.destroy = drm_encoder_cleanup,
};

static int rockchip_dp_of_probe(struct rockchip_dp_device *dp)
{
	struct device *dev = dp->dev;
	struct device_node *np = dev->of_node;

	dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
	if (IS_ERR(dp->grf)) {
		DRM_DEV_ERROR(dev, "failed to get rockchip,grf property\n");
		return PTR_ERR(dp->grf);
	}

	dp->grfclk = devm_clk_get(dev, "grf");
	if (PTR_ERR(dp->grfclk) == -ENOENT) {
		dp->grfclk = NULL;
	} else if (PTR_ERR(dp->grfclk) == -EPROBE_DEFER) {
		return -EPROBE_DEFER;
	} else if (IS_ERR(dp->grfclk)) {
		DRM_DEV_ERROR(dev, "failed to get grf clock\n");
		return PTR_ERR(dp->grfclk);
	}

	dp->pclk = devm_clk_get(dev, "pclk");
	if (IS_ERR(dp->pclk)) {
		DRM_DEV_ERROR(dev, "failed to get pclk property\n");
		return PTR_ERR(dp->pclk);
	}

	dp->rst = devm_reset_control_get(dev, "dp");
	if (IS_ERR(dp->rst)) {
		DRM_DEV_ERROR(dev, "failed to get dp reset control\n");
		return PTR_ERR(dp->rst);
	}

	return 0;
}

static int rockchip_dp_drm_create_encoder(struct rockchip_dp_device *dp)
{
	struct drm_encoder *encoder = &dp->encoder;
	struct drm_device *drm_dev = dp->drm_dev;
	struct device *dev = dp->dev;
	int ret;

	encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
							     dev->of_node);
	DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);

	ret = drm_encoder_init(drm_dev, encoder, &rockchip_dp_encoder_funcs,
			       DRM_MODE_ENCODER_TMDS, NULL);
	if (ret) {
		DRM_ERROR("failed to initialize encoder with drm\n");
		return ret;
	}

	drm_encoder_helper_add(encoder, &rockchip_dp_encoder_helper_funcs);

	return 0;
}

static int rockchip_dp_bind(struct device *dev, struct device *master,
			    void *data)
{
	struct rockchip_dp_device *dp = dev_get_drvdata(dev);
	const struct rockchip_dp_chip_data *dp_data;
	struct drm_device *drm_dev = data;
	int ret;

	dp_data = of_device_get_match_data(dev);
	if (!dp_data)
		return -ENODEV;

	dp->data = dp_data;
	dp->drm_dev = drm_dev;

	ret = rockchip_dp_drm_create_encoder(dp);
	if (ret) {
		DRM_ERROR("failed to create drm encoder\n");
		return ret;
	}

	dp->plat_data.encoder = &dp->encoder;

	dp->plat_data.dev_type = dp->data->chip_type;
	dp->plat_data.power_on = rockchip_dp_poweron;
	dp->plat_data.power_off = rockchip_dp_powerdown;
	dp->plat_data.get_modes = rockchip_dp_get_modes;

	mutex_init(&dp->psr_lock);
	dp->psr_state = ~EDP_VSC_PSR_STATE_ACTIVE;
	INIT_WORK(&dp->psr_work, analogix_dp_psr_work);

	ret = rockchip_drm_psr_register(&dp->encoder, analogix_dp_psr_set);
	if (ret < 0)
		goto err_cleanup_encoder;

	dp->adp = analogix_dp_bind(dev, dp->drm_dev, &dp->plat_data);
	if (IS_ERR(dp->adp)) {
		ret = PTR_ERR(dp->adp);
		goto err_unreg_psr;
	}

	return 0;
err_unreg_psr:
	rockchip_drm_psr_unregister(&dp->encoder);
err_cleanup_encoder:
	dp->encoder.funcs->destroy(&dp->encoder);
	return ret;
}

static void rockchip_dp_unbind(struct device *dev, struct device *master,
			       void *data)
{
	struct rockchip_dp_device *dp = dev_get_drvdata(dev);

	analogix_dp_unbind(dp->adp);
	rockchip_drm_psr_unregister(&dp->encoder);
	dp->encoder.funcs->destroy(&dp->encoder);
}

static const struct component_ops rockchip_dp_component_ops = {
	.bind = rockchip_dp_bind,
	.unbind = rockchip_dp_unbind,
};

static int rockchip_dp_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct drm_panel *panel = NULL;
	struct rockchip_dp_device *dp;
	int ret;

	ret = drm_of_find_panel_or_bridge(dev->of_node, 1, 0, &panel, NULL);
	if (ret < 0)
		return ret;

	dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
	if (!dp)
		return -ENOMEM;

	dp->dev = dev;
	dp->plat_data.panel = panel;

	ret = rockchip_dp_of_probe(dp);
	if (ret < 0)
		return ret;

	platform_set_drvdata(pdev, dp);

	return component_add(dev, &rockchip_dp_component_ops);
}

static int rockchip_dp_remove(struct platform_device *pdev)
{
	component_del(&pdev->dev, &rockchip_dp_component_ops);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int rockchip_dp_suspend(struct device *dev)
{
	struct rockchip_dp_device *dp = dev_get_drvdata(dev);

	return analogix_dp_suspend(dp->adp);
}

static int rockchip_dp_resume(struct device *dev)
{
	struct rockchip_dp_device *dp = dev_get_drvdata(dev);

	return analogix_dp_resume(dp->adp);
}
#endif

static const struct dev_pm_ops rockchip_dp_pm_ops = {
#ifdef CONFIG_PM_SLEEP
	.suspend = rockchip_dp_suspend,
	.resume_early = rockchip_dp_resume,
#endif
};

static const struct rockchip_dp_chip_data rk3399_edp = {
	.lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
	.lcdsel_big = HIWORD_UPDATE(0, RK3399_EDP_LCDC_SEL),
	.lcdsel_lit = HIWORD_UPDATE(RK3399_EDP_LCDC_SEL, RK3399_EDP_LCDC_SEL),
	.chip_type = RK3399_EDP,
};

static const struct rockchip_dp_chip_data rk3288_dp = {
	.lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
	.lcdsel_big = HIWORD_UPDATE(0, RK3288_EDP_LCDC_SEL),
	.lcdsel_lit = HIWORD_UPDATE(RK3288_EDP_LCDC_SEL, RK3288_EDP_LCDC_SEL),
	.chip_type = RK3288_DP,
};

static const struct of_device_id rockchip_dp_dt_ids[] = {
	{.compatible = "rockchip,rk3288-dp", .data = &rk3288_dp },
	{.compatible = "rockchip,rk3399-edp", .data = &rk3399_edp },
	{}
};
MODULE_DEVICE_TABLE(of, rockchip_dp_dt_ids);

struct platform_driver rockchip_dp_driver = {
	.probe = rockchip_dp_probe,
	.remove = rockchip_dp_remove,
	.driver = {
		   .name = "rockchip-dp",
		   .pm = &rockchip_dp_pm_ops,
		   .of_match_table = of_match_ptr(rockchip_dp_dt_ids),
	},
};
Commit	Line	Data
9e32e16e YY	1	/*
	2	* Rockchip SoC DP (Display Port) interface driver.
	3	*
	4	* Copyright (C) Fuzhou Rockchip Electronics Co., Ltd.
	5	* Author: Andy Yan <andy.yan@rock-chips.com>
	6	* Yakir Yang <ykk@rock-chips.com>
	7	* Jeff Chen <jeff.chen@rock-chips.com>
	8	*
	9	* This program is free software; you can redistribute it and/or modify it
	10	* under the terms of the GNU General Public License as published by the
	11	* Free Software Foundation; either version 2 of the License, or (at your
	12	* option) any later version.
	13	*/
	14
	15	#include <linux/component.h>
	16	#include <linux/mfd/syscon.h>
d9c900b0	17	#include <linux/of_device.h>
9e32e16e YY	18	#include <linux/of_graph.h>
	19	#include <linux/regmap.h>
	20	#include <linux/reset.h>
	21	#include <linux/clk.h>
	22
	23	#include <drm/drmP.h>
	24	#include <drm/drm_crtc_helper.h>
	25	#include <drm/drm_dp_helper.h>
	26	#include <drm/drm_of.h>
	27	#include <drm/drm_panel.h>
	28
	29	#include <video/of_videomode.h>
	30	#include <video/videomode.h>
	31
	32	#include <drm/bridge/analogix_dp.h>
	33
	34	#include "rockchip_drm_drv.h"
8f0ac5c4	35	#include "rockchip_drm_psr.h"
9e32e16e YY	36	#include "rockchip_drm_vop.h"
9e32e16e YY	37
d9c900b0 YY	38	#define RK3288_GRF_SOC_CON6 0x25c
d9c900b0 YY	39	#define RK3288_EDP_LCDC_SEL BIT(5)
82872e42 YY	40	#define RK3399_GRF_SOC_CON20 0x6250
82872e42 YY	41	#define RK3399_EDP_LCDC_SEL BIT(5)
d9c900b0 YY	42
	43	#define HIWORD_UPDATE(val, mask) (val \| (mask) << 16)
	44
8f0ac5c4 YY	45	#define PSR_WAIT_LINE_FLAG_TIMEOUT_MS 100
8f0ac5c4 YY	46
9e32e16e YY	47	#define to_dp(nm) container_of(nm, struct rockchip_dp_device, nm)
9e32e16e YY	48
d9c900b0 YY	49	/**
	50	* struct rockchip_dp_chip_data - splite the grf setting of kind of chips
	51	* @lcdsel_grf_reg: grf register offset of lcdc select
	52	* @lcdsel_big: reg value of selecting vop big for eDP
	53	* @lcdsel_lit: reg value of selecting vop little for eDP
	54	* @chip_type: specific chip type
	55	*/
	56	struct rockchip_dp_chip_data {
	57	u32 lcdsel_grf_reg;
	58	u32 lcdsel_big;
	59	u32 lcdsel_lit;
	60	u32 chip_type;
	61	};
9e32e16e YY	62
	63	struct rockchip_dp_device {
	64	struct drm_device *drm_dev;
	65	struct device *dev;
	66	struct drm_encoder encoder;
	67	struct drm_display_mode mode;
	68
	69	struct clk *pclk;
dc1c93be	70	struct clk *grfclk;
9e32e16e YY	71	struct regmap *grf;
	72	struct reset_control *rst;
	73
d761b2df	74	struct work_struct psr_work;
44419ce7	75	struct mutex psr_lock;
8f0ac5c4 YY	76	unsigned int psr_state;
8f0ac5c4 YY	77
d9c900b0 YY	78	const struct rockchip_dp_chip_data *data;
d9c900b0 YY	79
6b2d8fd9	80	struct analogix_dp_device *adp;
9e32e16e YY	81	struct analogix_dp_plat_data plat_data;
	82	};
	83
8f0ac5c4 YY	84	static void analogix_dp_psr_set(struct drm_encoder *encoder, bool enabled)
	85	{
	86	struct rockchip_dp_device *dp = to_dp(encoder);
	87
6b2d8fd9	88	if (!analogix_dp_psr_supported(dp->adp))
0546d685 TV	89	return;
0546d685 TV	90
d8dd6804	91	DRM_DEV_DEBUG(dp->dev, "%s PSR...\n", enabled ? "Entry" : "Exit");
8f0ac5c4	92
44419ce7	93	mutex_lock(&dp->psr_lock);
8f0ac5c4 YY	94	if (enabled)
	95	dp->psr_state = EDP_VSC_PSR_STATE_ACTIVE;
	96	else
	97	dp->psr_state = ~EDP_VSC_PSR_STATE_ACTIVE;
	98
d761b2df	99	schedule_work(&dp->psr_work);
44419ce7	100	mutex_unlock(&dp->psr_lock);
8f0ac5c4 YY	101	}
	102
	103	static void analogix_dp_psr_work(struct work_struct *work)
	104	{
	105	struct rockchip_dp_device *dp =
d761b2df	106	container_of(work, typeof(*dp), psr_work);
8f0ac5c4 YY	107	int ret;
8f0ac5c4 YY	108
459b086d JC	109	ret = rockchip_drm_wait_vact_end(dp->encoder.crtc,
459b086d JC	110	PSR_WAIT_LINE_FLAG_TIMEOUT_MS);
8f0ac5c4	111	if (ret) {
d8dd6804	112	DRM_DEV_ERROR(dp->dev, "line flag interrupt did not arrive\n");
8f0ac5c4 YY	113	return;
	114	}
	115
44419ce7	116	mutex_lock(&dp->psr_lock);
aa5bfa40	117	if (dp->psr_state == EDP_VSC_PSR_STATE_ACTIVE)
6b2d8fd9	118	analogix_dp_enable_psr(dp->adp);
8f0ac5c4	119	else
6b2d8fd9	120	analogix_dp_disable_psr(dp->adp);
44419ce7	121	mutex_unlock(&dp->psr_lock);
8f0ac5c4 YY	122	}
8f0ac5c4 YY	123
9e32e16e YY	124	static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
	125	{
	126	reset_control_assert(dp->rst);
	127	usleep_range(10, 20);
	128	reset_control_deassert(dp->rst);
	129
	130	return 0;
	131	}
	132
	133	static int rockchip_dp_poweron(struct analogix_dp_plat_data *plat_data)
	134	{
	135	struct rockchip_dp_device *dp = to_dp(plat_data);
	136	int ret;
	137
d761b2df SP	138	cancel_work_sync(&dp->psr_work);
d761b2df SP	139
9e32e16e YY	140	ret = clk_prepare_enable(dp->pclk);
9e32e16e YY	141	if (ret < 0) {
d8dd6804	142	DRM_DEV_ERROR(dp->dev, "failed to enable pclk %d\n", ret);
9e32e16e YY	143	return ret;
	144	}
	145
	146	ret = rockchip_dp_pre_init(dp);
	147	if (ret < 0) {
d8dd6804	148	DRM_DEV_ERROR(dp->dev, "failed to dp pre init %d\n", ret);
3694c5c3	149	clk_disable_unprepare(dp->pclk);
9e32e16e YY	150	return ret;
	151	}
	152
7f3c191b	153	return rockchip_drm_psr_activate(&dp->encoder);
9e32e16e YY	154	}
	155
	156	static int rockchip_dp_powerdown(struct analogix_dp_plat_data *plat_data)
	157	{
	158	struct rockchip_dp_device *dp = to_dp(plat_data);
7f3c191b	159	int ret;
	160
	161	ret = rockchip_drm_psr_deactivate(&dp->encoder);
	162	if (ret != 0)
	163	return ret;
9e32e16e YY	164
	165	clk_disable_unprepare(dp->pclk);
	166
	167	return 0;
	168	}
	169
db8a9aed YY	170	static int rockchip_dp_get_modes(struct analogix_dp_plat_data *plat_data,
	171	struct drm_connector *connector)
	172	{
	173	struct drm_display_info *di = &connector->display_info;
	174	/* VOP couldn't output YUV video format for eDP rightly */
	175	u32 mask = DRM_COLOR_FORMAT_YCRCB444 \| DRM_COLOR_FORMAT_YCRCB422;
	176
	177	if ((di->color_formats & mask)) {
	178	DRM_DEBUG_KMS("Swapping display color format from YUV to RGB\n");
	179	di->color_formats &= ~mask;
	180	di->color_formats \|= DRM_COLOR_FORMAT_RGB444;
	181	di->bpc = 8;
	182	}
	183
	184	return 0;
	185	}
	186
9e32e16e YY	187	static bool
	188	rockchip_dp_drm_encoder_mode_fixup(struct drm_encoder *encoder,
	189	const struct drm_display_mode *mode,
	190	struct drm_display_mode *adjusted_mode)
	191	{
	192	/* do nothing */
	193	return true;
	194	}
	195
	196	static void rockchip_dp_drm_encoder_mode_set(struct drm_encoder *encoder,
	197	struct drm_display_mode *mode,
	198	struct drm_display_mode *adjusted)
	199	{
	200	/* do nothing */
	201	}
	202
	203	static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder)
	204	{
	205	struct rockchip_dp_device *dp = to_dp(encoder);
	206	int ret;
	207	u32 val;
	208
9e32e16e YY	209	ret = drm_of_encoder_active_endpoint_id(dp->dev->of_node, encoder);
	210	if (ret < 0)
	211	return;
	212
	213	if (ret)
d9c900b0	214	val = dp->data->lcdsel_lit;
9e32e16e	215	else
d9c900b0	216	val = dp->data->lcdsel_big;
9e32e16e	217
d8dd6804	218	DRM_DEV_DEBUG(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG");
9e32e16e	219
dc1c93be YY	220	ret = clk_prepare_enable(dp->grfclk);
dc1c93be YY	221	if (ret < 0) {
d8dd6804	222	DRM_DEV_ERROR(dp->dev, "failed to enable grfclk %d\n", ret);
9e32e16e YY	223	return;
9e32e16e YY	224	}
dc1c93be YY	225
	226	ret = regmap_write(dp->grf, dp->data->lcdsel_grf_reg, val);
	227	if (ret != 0)
d8dd6804	228	DRM_DEV_ERROR(dp->dev, "Could not write to GRF: %d\n", ret);
dc1c93be YY	229
dc1c93be YY	230	clk_disable_unprepare(dp->grfclk);
9e32e16e YY	231	}
	232
	233	static void rockchip_dp_drm_encoder_nop(struct drm_encoder *encoder)
	234	{
	235	/* do nothing */
	236	}
	237
4e257d9e MY	238	static int
	239	rockchip_dp_drm_encoder_atomic_check(struct drm_encoder *encoder,
	240	struct drm_crtc_state *crtc_state,
	241	struct drm_connector_state *conn_state)
	242	{
	243	struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
	244
	245	/*
d698f0eb YY	246	* The hardware IC designed that VOP must output the RGB10 video
	247	* format to eDP controller, and if eDP panel only support RGB8,
	248	* then eDP controller should cut down the video data, not via VOP
	249	* controller, that's why we need to hardcode the VOP output mode
	250	* to RGA10 here.
4e257d9e	251	*/
82872e42	252
4e257d9e MY	253	s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
	254	s->output_type = DRM_MODE_CONNECTOR_eDP;
	255
	256	return 0;
	257	}
	258
9e32e16e YY	259	static struct drm_encoder_helper_funcs rockchip_dp_encoder_helper_funcs = {
	260	.mode_fixup = rockchip_dp_drm_encoder_mode_fixup,
	261	.mode_set = rockchip_dp_drm_encoder_mode_set,
	262	.enable = rockchip_dp_drm_encoder_enable,
	263	.disable = rockchip_dp_drm_encoder_nop,
4e257d9e	264	.atomic_check = rockchip_dp_drm_encoder_atomic_check,
9e32e16e YY	265	};
9e32e16e YY	266
9e32e16e	267	static struct drm_encoder_funcs rockchip_dp_encoder_funcs = {
7fe201cd	268	.destroy = drm_encoder_cleanup,
9e32e16e YY	269	};
9e32e16e YY	270
102712a3	271	static int rockchip_dp_of_probe(struct rockchip_dp_device *dp)
9e32e16e YY	272	{
	273	struct device *dev = dp->dev;
	274	struct device_node *np = dev->of_node;
9e32e16e YY	275
	276	dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
	277	if (IS_ERR(dp->grf)) {
d8dd6804	278	DRM_DEV_ERROR(dev, "failed to get rockchip,grf property\n");
9e32e16e YY	279	return PTR_ERR(dp->grf);
	280	}
	281
dc1c93be YY	282	dp->grfclk = devm_clk_get(dev, "grf");
	283	if (PTR_ERR(dp->grfclk) == -ENOENT) {
	284	dp->grfclk = NULL;
	285	} else if (PTR_ERR(dp->grfclk) == -EPROBE_DEFER) {
	286	return -EPROBE_DEFER;
	287	} else if (IS_ERR(dp->grfclk)) {
d8dd6804	288	DRM_DEV_ERROR(dev, "failed to get grf clock\n");
dc1c93be YY	289	return PTR_ERR(dp->grfclk);
	290	}
	291
9e32e16e YY	292	dp->pclk = devm_clk_get(dev, "pclk");
9e32e16e YY	293	if (IS_ERR(dp->pclk)) {
d8dd6804	294	DRM_DEV_ERROR(dev, "failed to get pclk property\n");
9e32e16e YY	295	return PTR_ERR(dp->pclk);
	296	}
	297
	298	dp->rst = devm_reset_control_get(dev, "dp");
	299	if (IS_ERR(dp->rst)) {
d8dd6804	300	DRM_DEV_ERROR(dev, "failed to get dp reset control\n");
9e32e16e YY	301	return PTR_ERR(dp->rst);
	302	}
	303
9e32e16e YY	304	return 0;
	305	}
	306
	307	static int rockchip_dp_drm_create_encoder(struct rockchip_dp_device *dp)
	308	{
	309	struct drm_encoder *encoder = &dp->encoder;
	310	struct drm_device *drm_dev = dp->drm_dev;
	311	struct device *dev = dp->dev;
	312	int ret;
	313
	314	encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
	315	dev->of_node);
	316	DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
	317
	318	ret = drm_encoder_init(drm_dev, encoder, &rockchip_dp_encoder_funcs,
	319	DRM_MODE_ENCODER_TMDS, NULL);
	320	if (ret) {
	321	DRM_ERROR("failed to initialize encoder with drm\n");
	322	return ret;
	323	}
	324
	325	drm_encoder_helper_add(encoder, &rockchip_dp_encoder_helper_funcs);
	326
	327	return 0;
	328	}
	329
	330	static int rockchip_dp_bind(struct device dev, struct device master,
	331	void *data)
	332	{
	333	struct rockchip_dp_device *dp = dev_get_drvdata(dev);
d9c900b0	334	const struct rockchip_dp_chip_data *dp_data;
9e32e16e YY	335	struct drm_device *drm_dev = data;
	336	int ret;
	337
d9c900b0 YY	338	dp_data = of_device_get_match_data(dev);
	339	if (!dp_data)
	340	return -ENODEV;
	341
d9c900b0	342	dp->data = dp_data;
9e32e16e YY	343	dp->drm_dev = drm_dev;
	344
	345	ret = rockchip_dp_drm_create_encoder(dp);
	346	if (ret) {
	347	DRM_ERROR("failed to create drm encoder\n");
	348	return ret;
	349	}
	350
	351	dp->plat_data.encoder = &dp->encoder;
	352
d9c900b0	353	dp->plat_data.dev_type = dp->data->chip_type;
9e32e16e YY	354	dp->plat_data.power_on = rockchip_dp_poweron;
9e32e16e YY	355	dp->plat_data.power_off = rockchip_dp_powerdown;
db8a9aed	356	dp->plat_data.get_modes = rockchip_dp_get_modes;
9e32e16e	357
44419ce7	358	mutex_init(&dp->psr_lock);
8f0ac5c4	359	dp->psr_state = ~EDP_VSC_PSR_STATE_ACTIVE;
d761b2df	360	INIT_WORK(&dp->psr_work, analogix_dp_psr_work);
8f0ac5c4	361
c8c04514 JC	362	ret = rockchip_drm_psr_register(&dp->encoder, analogix_dp_psr_set);
	363	if (ret < 0)
	364	goto err_cleanup_encoder;
8f0ac5c4	365
6b2d8fd9	366	dp->adp = analogix_dp_bind(dev, dp->drm_dev, &dp->plat_data);
7fe201cd	367	if (IS_ERR(dp->adp)) {
c8c04514 JC	368	ret = PTR_ERR(dp->adp);
c8c04514 JC	369	goto err_unreg_psr;
7fe201cd	370	}
6b2d8fd9 JC	371
6b2d8fd9 JC	372	return 0;
c8c04514 JC	373	err_unreg_psr:
	374	rockchip_drm_psr_unregister(&dp->encoder);
	375	err_cleanup_encoder:
	376	dp->encoder.funcs->destroy(&dp->encoder);
	377	return ret;
9e32e16e YY	378	}
	379
	380	static void rockchip_dp_unbind(struct device dev, struct device master,
	381	void *data)
	382	{
8f0ac5c4 YY	383	struct rockchip_dp_device *dp = dev_get_drvdata(dev);
8f0ac5c4 YY	384
6b2d8fd9	385	analogix_dp_unbind(dp->adp);
d8e7e73e	386	rockchip_drm_psr_unregister(&dp->encoder);
7fe201cd	387	dp->encoder.funcs->destroy(&dp->encoder);
9e32e16e YY	388	}
	389
	390	static const struct component_ops rockchip_dp_component_ops = {
	391	.bind = rockchip_dp_bind,
	392	.unbind = rockchip_dp_unbind,
	393	};
	394
	395	static int rockchip_dp_probe(struct platform_device *pdev)
	396	{
	397	struct device *dev = &pdev->dev;
eb87c91c	398	struct drm_panel *panel = NULL;
9e32e16e	399	struct rockchip_dp_device *dp;
ebc94461	400	int ret;
9e32e16e	401
ebc94461	402	ret = drm_of_find_panel_or_bridge(dev->of_node, 1, 0, &panel, NULL);
102712a3	403	if (ret < 0)
ebc94461	404	return ret;
9e32e16e	405
9e32e16e YY	406	dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
	407	if (!dp)
	408	return -ENOMEM;
	409
	410	dp->dev = dev;
9e32e16e YY	411	dp->plat_data.panel = panel;
9e32e16e YY	412
102712a3 JC	413	ret = rockchip_dp_of_probe(dp);
	414	if (ret < 0)
	415	return ret;
	416
9e32e16e YY	417	platform_set_drvdata(pdev, dp);
	418
	419	return component_add(dev, &rockchip_dp_component_ops);
	420	}
	421
	422	static int rockchip_dp_remove(struct platform_device *pdev)
	423	{
	424	component_del(&pdev->dev, &rockchip_dp_component_ops);
	425
	426	return 0;
	427	}
	428
6b2d8fd9 JC	429	#ifdef CONFIG_PM_SLEEP
	430	static int rockchip_dp_suspend(struct device *dev)
	431	{
	432	struct rockchip_dp_device *dp = dev_get_drvdata(dev);
	433
	434	return analogix_dp_suspend(dp->adp);
	435	}
	436
	437	static int rockchip_dp_resume(struct device *dev)
	438	{
	439	struct rockchip_dp_device *dp = dev_get_drvdata(dev);
	440
	441	return analogix_dp_resume(dp->adp);
	442	}
	443	#endif
	444
fe64ba5c	445	static const struct dev_pm_ops rockchip_dp_pm_ops = {
9e32e16e	446	#ifdef CONFIG_PM_SLEEP
6b2d8fd9 JC	447	.suspend = rockchip_dp_suspend,
6b2d8fd9 JC	448	.resume_early = rockchip_dp_resume,
9e32e16e	449	#endif
9e32e16e YY	450	};
9e32e16e YY	451
82872e42 YY	452	static const struct rockchip_dp_chip_data rk3399_edp = {
	453	.lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
	454	.lcdsel_big = HIWORD_UPDATE(0, RK3399_EDP_LCDC_SEL),
	455	.lcdsel_lit = HIWORD_UPDATE(RK3399_EDP_LCDC_SEL, RK3399_EDP_LCDC_SEL),
	456	.chip_type = RK3399_EDP,
	457	};
	458
d9c900b0 YY	459	static const struct rockchip_dp_chip_data rk3288_dp = {
	460	.lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
	461	.lcdsel_big = HIWORD_UPDATE(0, RK3288_EDP_LCDC_SEL),
	462	.lcdsel_lit = HIWORD_UPDATE(RK3288_EDP_LCDC_SEL, RK3288_EDP_LCDC_SEL),
	463	.chip_type = RK3288_DP,
	464	};
	465
9e32e16e	466	static const struct of_device_id rockchip_dp_dt_ids[] = {
d9c900b0	467	{.compatible = "rockchip,rk3288-dp", .data = &rk3288_dp },
82872e42	468	{.compatible = "rockchip,rk3399-edp", .data = &rk3399_edp },
9e32e16e YY	469	{}
	470	};
	471	MODULE_DEVICE_TABLE(of, rockchip_dp_dt_ids);
	472
8820b68b	473	struct platform_driver rockchip_dp_driver = {
9e32e16e YY	474	.probe = rockchip_dp_probe,
	475	.remove = rockchip_dp_remove,
	476	.driver = {
	477	.name = "rockchip-dp",
9e32e16e YY	478	.pm = &rockchip_dp_pm_ops,
	479	.of_match_table = of_match_ptr(rockchip_dp_dt_ids),
	480	},
	481	};