]>
Commit | Line | Data |
---|---|---|
84e05408 CZ |
1 | /* |
2 | * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | */ | |
9 | #include <linux/clk.h> | |
10 | #include <linux/component.h> | |
11 | #include <linux/iopoll.h> | |
12 | #include <linux/math64.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/of_device.h> | |
80a9a059 | 15 | #include <linux/pm_runtime.h> |
84e05408 | 16 | #include <linux/regmap.h> |
f3b7a5b8 | 17 | #include <linux/reset.h> |
84e05408 CZ |
18 | #include <linux/mfd/syscon.h> |
19 | #include <drm/drm_atomic_helper.h> | |
20 | #include <drm/drm_crtc.h> | |
21 | #include <drm/drm_crtc_helper.h> | |
22 | #include <drm/drm_mipi_dsi.h> | |
23 | #include <drm/drm_of.h> | |
24 | #include <drm/drm_panel.h> | |
25 | #include <drm/drmP.h> | |
26 | #include <video/mipi_display.h> | |
27 | ||
28 | #include "rockchip_drm_drv.h" | |
29 | #include "rockchip_drm_vop.h" | |
30 | ||
31 | #define DRIVER_NAME "dw-mipi-dsi" | |
32 | ||
ef6eba19 CZ |
33 | #define RK3288_GRF_SOC_CON6 0x025c |
34 | #define RK3288_DSI0_SEL_VOP_LIT BIT(6) | |
35 | #define RK3288_DSI1_SEL_VOP_LIT BIT(9) | |
36 | ||
395eaaae | 37 | #define RK3399_GRF_SOC_CON20 0x6250 |
ef6eba19 CZ |
38 | #define RK3399_DSI0_SEL_VOP_LIT BIT(0) |
39 | #define RK3399_DSI1_SEL_VOP_LIT BIT(4) | |
40 | ||
41 | /* disable turnrequest, turndisable, forcetxstopmode, forcerxmode */ | |
42 | #define RK3399_GRF_SOC_CON22 0x6258 | |
43 | #define RK3399_GRF_DSI_MODE 0xffff0000 | |
84e05408 CZ |
44 | |
45 | #define DSI_VERSION 0x00 | |
46 | #define DSI_PWR_UP 0x04 | |
47 | #define RESET 0 | |
48 | #define POWERUP BIT(0) | |
49 | ||
50 | #define DSI_CLKMGR_CFG 0x08 | |
51 | #define TO_CLK_DIVIDSION(div) (((div) & 0xff) << 8) | |
52 | #define TX_ESC_CLK_DIVIDSION(div) (((div) & 0xff) << 0) | |
53 | ||
54 | #define DSI_DPI_VCID 0x0c | |
55 | #define DPI_VID(vid) (((vid) & 0x3) << 0) | |
56 | ||
57 | #define DSI_DPI_COLOR_CODING 0x10 | |
58 | #define EN18_LOOSELY BIT(8) | |
59 | #define DPI_COLOR_CODING_16BIT_1 0x0 | |
60 | #define DPI_COLOR_CODING_16BIT_2 0x1 | |
61 | #define DPI_COLOR_CODING_16BIT_3 0x2 | |
62 | #define DPI_COLOR_CODING_18BIT_1 0x3 | |
63 | #define DPI_COLOR_CODING_18BIT_2 0x4 | |
64 | #define DPI_COLOR_CODING_24BIT 0x5 | |
65 | ||
66 | #define DSI_DPI_CFG_POL 0x14 | |
67 | #define COLORM_ACTIVE_LOW BIT(4) | |
68 | #define SHUTD_ACTIVE_LOW BIT(3) | |
69 | #define HSYNC_ACTIVE_LOW BIT(2) | |
70 | #define VSYNC_ACTIVE_LOW BIT(1) | |
71 | #define DATAEN_ACTIVE_LOW BIT(0) | |
72 | ||
73 | #define DSI_DPI_LP_CMD_TIM 0x18 | |
74 | #define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16) | |
75 | #define INVACT_LPCMD_TIME(p) ((p) & 0xff) | |
76 | ||
77 | #define DSI_DBI_CFG 0x20 | |
78 | #define DSI_DBI_CMDSIZE 0x28 | |
79 | ||
80 | #define DSI_PCKHDL_CFG 0x2c | |
81 | #define EN_CRC_RX BIT(4) | |
82 | #define EN_ECC_RX BIT(3) | |
83 | #define EN_BTA BIT(2) | |
84 | #define EN_EOTP_RX BIT(1) | |
85 | #define EN_EOTP_TX BIT(0) | |
86 | ||
87 | #define DSI_MODE_CFG 0x34 | |
88 | #define ENABLE_VIDEO_MODE 0 | |
89 | #define ENABLE_CMD_MODE BIT(0) | |
90 | ||
91 | #define DSI_VID_MODE_CFG 0x38 | |
92 | #define FRAME_BTA_ACK BIT(14) | |
93 | #define ENABLE_LOW_POWER (0x3f << 8) | |
94 | #define ENABLE_LOW_POWER_MASK (0x3f << 8) | |
03a5832c JK |
95 | #define VID_MODE_TYPE_NON_BURST_SYNC_PULSES 0x0 |
96 | #define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS 0x1 | |
97 | #define VID_MODE_TYPE_BURST 0x2 | |
84e05408 CZ |
98 | #define VID_MODE_TYPE_MASK 0x3 |
99 | ||
100 | #define DSI_VID_PKT_SIZE 0x3c | |
101 | #define VID_PKT_SIZE(p) (((p) & 0x3fff) << 0) | |
102 | #define VID_PKT_MAX_SIZE 0x3fff | |
103 | ||
104 | #define DSI_VID_HSA_TIME 0x48 | |
105 | #define DSI_VID_HBP_TIME 0x4c | |
106 | #define DSI_VID_HLINE_TIME 0x50 | |
107 | #define DSI_VID_VSA_LINES 0x54 | |
108 | #define DSI_VID_VBP_LINES 0x58 | |
109 | #define DSI_VID_VFP_LINES 0x5c | |
110 | #define DSI_VID_VACTIVE_LINES 0x60 | |
111 | #define DSI_CMD_MODE_CFG 0x68 | |
112 | #define MAX_RD_PKT_SIZE_LP BIT(24) | |
113 | #define DCS_LW_TX_LP BIT(19) | |
114 | #define DCS_SR_0P_TX_LP BIT(18) | |
115 | #define DCS_SW_1P_TX_LP BIT(17) | |
116 | #define DCS_SW_0P_TX_LP BIT(16) | |
117 | #define GEN_LW_TX_LP BIT(14) | |
118 | #define GEN_SR_2P_TX_LP BIT(13) | |
119 | #define GEN_SR_1P_TX_LP BIT(12) | |
120 | #define GEN_SR_0P_TX_LP BIT(11) | |
121 | #define GEN_SW_2P_TX_LP BIT(10) | |
122 | #define GEN_SW_1P_TX_LP BIT(9) | |
123 | #define GEN_SW_0P_TX_LP BIT(8) | |
124 | #define EN_ACK_RQST BIT(1) | |
125 | #define EN_TEAR_FX BIT(0) | |
126 | ||
127 | #define CMD_MODE_ALL_LP (MAX_RD_PKT_SIZE_LP | \ | |
128 | DCS_LW_TX_LP | \ | |
129 | DCS_SR_0P_TX_LP | \ | |
130 | DCS_SW_1P_TX_LP | \ | |
131 | DCS_SW_0P_TX_LP | \ | |
132 | GEN_LW_TX_LP | \ | |
133 | GEN_SR_2P_TX_LP | \ | |
134 | GEN_SR_1P_TX_LP | \ | |
135 | GEN_SR_0P_TX_LP | \ | |
136 | GEN_SW_2P_TX_LP | \ | |
137 | GEN_SW_1P_TX_LP | \ | |
138 | GEN_SW_0P_TX_LP) | |
139 | ||
140 | #define DSI_GEN_HDR 0x6c | |
141 | #define GEN_HDATA(data) (((data) & 0xffff) << 8) | |
142 | #define GEN_HDATA_MASK (0xffff << 8) | |
143 | #define GEN_HTYPE(type) (((type) & 0xff) << 0) | |
144 | #define GEN_HTYPE_MASK 0xff | |
145 | ||
146 | #define DSI_GEN_PLD_DATA 0x70 | |
147 | ||
148 | #define DSI_CMD_PKT_STATUS 0x74 | |
149 | #define GEN_CMD_EMPTY BIT(0) | |
150 | #define GEN_CMD_FULL BIT(1) | |
151 | #define GEN_PLD_W_EMPTY BIT(2) | |
152 | #define GEN_PLD_W_FULL BIT(3) | |
153 | #define GEN_PLD_R_EMPTY BIT(4) | |
154 | #define GEN_PLD_R_FULL BIT(5) | |
155 | #define GEN_RD_CMD_BUSY BIT(6) | |
156 | ||
157 | #define DSI_TO_CNT_CFG 0x78 | |
158 | #define HSTX_TO_CNT(p) (((p) & 0xffff) << 16) | |
159 | #define LPRX_TO_CNT(p) ((p) & 0xffff) | |
160 | ||
161 | #define DSI_BTA_TO_CNT 0x8c | |
84e05408 CZ |
162 | #define DSI_LPCLK_CTRL 0x94 |
163 | #define AUTO_CLKLANE_CTRL BIT(1) | |
164 | #define PHY_TXREQUESTCLKHS BIT(0) | |
165 | ||
166 | #define DSI_PHY_TMR_LPCLK_CFG 0x98 | |
167 | #define PHY_CLKHS2LP_TIME(lbcc) (((lbcc) & 0x3ff) << 16) | |
168 | #define PHY_CLKLP2HS_TIME(lbcc) ((lbcc) & 0x3ff) | |
169 | ||
170 | #define DSI_PHY_TMR_CFG 0x9c | |
171 | #define PHY_HS2LP_TIME(lbcc) (((lbcc) & 0xff) << 24) | |
172 | #define PHY_LP2HS_TIME(lbcc) (((lbcc) & 0xff) << 16) | |
173 | #define MAX_RD_TIME(lbcc) ((lbcc) & 0x7fff) | |
174 | ||
175 | #define DSI_PHY_RSTZ 0xa0 | |
176 | #define PHY_DISFORCEPLL 0 | |
177 | #define PHY_ENFORCEPLL BIT(3) | |
178 | #define PHY_DISABLECLK 0 | |
179 | #define PHY_ENABLECLK BIT(2) | |
180 | #define PHY_RSTZ 0 | |
181 | #define PHY_UNRSTZ BIT(1) | |
182 | #define PHY_SHUTDOWNZ 0 | |
183 | #define PHY_UNSHUTDOWNZ BIT(0) | |
184 | ||
185 | #define DSI_PHY_IF_CFG 0xa4 | |
186 | #define N_LANES(n) ((((n) - 1) & 0x3) << 0) | |
187 | #define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8) | |
188 | ||
189 | #define DSI_PHY_STATUS 0xb0 | |
190 | #define LOCK BIT(0) | |
191 | #define STOP_STATE_CLK_LANE BIT(2) | |
192 | ||
193 | #define DSI_PHY_TST_CTRL0 0xb4 | |
194 | #define PHY_TESTCLK BIT(1) | |
195 | #define PHY_UNTESTCLK 0 | |
196 | #define PHY_TESTCLR BIT(0) | |
197 | #define PHY_UNTESTCLR 0 | |
198 | ||
199 | #define DSI_PHY_TST_CTRL1 0xb8 | |
200 | #define PHY_TESTEN BIT(16) | |
201 | #define PHY_UNTESTEN 0 | |
202 | #define PHY_TESTDOUT(n) (((n) & 0xff) << 8) | |
203 | #define PHY_TESTDIN(n) (((n) & 0xff) << 0) | |
204 | ||
205 | #define DSI_INT_ST0 0xbc | |
206 | #define DSI_INT_ST1 0xc0 | |
207 | #define DSI_INT_MSK0 0xc4 | |
208 | #define DSI_INT_MSK1 0xc8 | |
209 | ||
210 | #define PHY_STATUS_TIMEOUT_US 10000 | |
211 | #define CMD_PKT_STATUS_TIMEOUT_US 20000 | |
212 | ||
213 | #define BYPASS_VCO_RANGE BIT(7) | |
214 | #define VCO_RANGE_CON_SEL(val) (((val) & 0x7) << 3) | |
215 | #define VCO_IN_CAP_CON_DEFAULT (0x0 << 1) | |
216 | #define VCO_IN_CAP_CON_LOW (0x1 << 1) | |
217 | #define VCO_IN_CAP_CON_HIGH (0x2 << 1) | |
218 | #define REF_BIAS_CUR_SEL BIT(0) | |
219 | ||
220 | #define CP_CURRENT_3MA BIT(3) | |
221 | #define CP_PROGRAM_EN BIT(7) | |
222 | #define LPF_PROGRAM_EN BIT(6) | |
223 | #define LPF_RESISTORS_20_KOHM 0 | |
224 | ||
225 | #define HSFREQRANGE_SEL(val) (((val) & 0x3f) << 1) | |
226 | ||
a432e054 | 227 | #define INPUT_DIVIDER(val) (((val) - 1) & 0x7f) |
84e05408 CZ |
228 | #define LOW_PROGRAM_EN 0 |
229 | #define HIGH_PROGRAM_EN BIT(7) | |
a432e054 CZ |
230 | #define LOOP_DIV_LOW_SEL(val) (((val) - 1) & 0x1f) |
231 | #define LOOP_DIV_HIGH_SEL(val) ((((val) - 1) >> 5) & 0x1f) | |
84e05408 CZ |
232 | #define PLL_LOOP_DIV_EN BIT(5) |
233 | #define PLL_INPUT_DIV_EN BIT(4) | |
234 | ||
235 | #define POWER_CONTROL BIT(6) | |
236 | #define INTERNAL_REG_CURRENT BIT(3) | |
237 | #define BIAS_BLOCK_ON BIT(2) | |
238 | #define BANDGAP_ON BIT(0) | |
239 | ||
240 | #define TER_RESISTOR_HIGH BIT(7) | |
241 | #define TER_RESISTOR_LOW 0 | |
242 | #define LEVEL_SHIFTERS_ON BIT(6) | |
243 | #define TER_CAL_DONE BIT(5) | |
244 | #define SETRD_MAX (0x7 << 2) | |
245 | #define POWER_MANAGE BIT(1) | |
246 | #define TER_RESISTORS_ON BIT(0) | |
247 | ||
248 | #define BIASEXTR_SEL(val) ((val) & 0x7) | |
249 | #define BANDGAP_SEL(val) ((val) & 0x7) | |
250 | #define TLP_PROGRAM_EN BIT(7) | |
251 | #define THS_PRE_PROGRAM_EN BIT(7) | |
252 | #define THS_ZERO_PROGRAM_EN BIT(6) | |
253 | ||
25f0b120 | 254 | #define DW_MIPI_NEEDS_PHY_CFG_CLK BIT(0) |
5bc07b15 | 255 | #define DW_MIPI_NEEDS_GRF_CLK BIT(1) |
25f0b120 | 256 | |
84e05408 CZ |
257 | enum { |
258 | BANDGAP_97_07, | |
259 | BANDGAP_98_05, | |
260 | BANDGAP_99_02, | |
261 | BANDGAP_100_00, | |
262 | BANDGAP_93_17, | |
263 | BANDGAP_94_15, | |
264 | BANDGAP_95_12, | |
265 | BANDGAP_96_10, | |
266 | }; | |
267 | ||
268 | enum { | |
269 | BIASEXTR_87_1, | |
270 | BIASEXTR_91_5, | |
271 | BIASEXTR_95_9, | |
272 | BIASEXTR_100, | |
273 | BIASEXTR_105_94, | |
274 | BIASEXTR_111_88, | |
275 | BIASEXTR_118_8, | |
276 | BIASEXTR_127_7, | |
277 | }; | |
278 | ||
279 | struct dw_mipi_dsi_plat_data { | |
ef6eba19 CZ |
280 | u32 dsi0_en_bit; |
281 | u32 dsi1_en_bit; | |
282 | u32 grf_switch_reg; | |
283 | u32 grf_dsi0_mode; | |
284 | u32 grf_dsi0_mode_reg; | |
25f0b120 | 285 | unsigned int flags; |
84e05408 | 286 | unsigned int max_data_lanes; |
84e05408 CZ |
287 | }; |
288 | ||
289 | struct dw_mipi_dsi { | |
290 | struct drm_encoder encoder; | |
291 | struct drm_connector connector; | |
292 | struct mipi_dsi_host dsi_host; | |
293 | struct drm_panel *panel; | |
294 | struct device *dev; | |
295 | struct regmap *grf_regmap; | |
296 | void __iomem *base; | |
297 | ||
5bc07b15 | 298 | struct clk *grf_clk; |
84e05408 CZ |
299 | struct clk *pllref_clk; |
300 | struct clk *pclk; | |
ef6eba19 | 301 | struct clk *phy_cfg_clk; |
84e05408 | 302 | |
80a9a059 | 303 | int dpms_mode; |
84e05408 CZ |
304 | unsigned int lane_mbps; /* per lane */ |
305 | u32 channel; | |
306 | u32 lanes; | |
307 | u32 format; | |
308 | u16 input_div; | |
309 | u16 feedback_div; | |
03a5832c | 310 | unsigned long mode_flags; |
84e05408 CZ |
311 | |
312 | const struct dw_mipi_dsi_plat_data *pdata; | |
313 | }; | |
314 | ||
315 | enum dw_mipi_dsi_mode { | |
316 | DW_MIPI_DSI_CMD_MODE, | |
317 | DW_MIPI_DSI_VID_MODE, | |
318 | }; | |
319 | ||
320 | struct dphy_pll_testdin_map { | |
321 | unsigned int max_mbps; | |
322 | u8 testdin; | |
323 | }; | |
324 | ||
325 | /* The table is based on 27MHz DPHY pll reference clock. */ | |
326 | static const struct dphy_pll_testdin_map dptdin_map[] = { | |
327 | { 90, 0x00}, { 100, 0x10}, { 110, 0x20}, { 130, 0x01}, | |
328 | { 140, 0x11}, { 150, 0x21}, { 170, 0x02}, { 180, 0x12}, | |
329 | { 200, 0x22}, { 220, 0x03}, { 240, 0x13}, { 250, 0x23}, | |
330 | { 270, 0x04}, { 300, 0x14}, { 330, 0x05}, { 360, 0x15}, | |
331 | { 400, 0x25}, { 450, 0x06}, { 500, 0x16}, { 550, 0x07}, | |
332 | { 600, 0x17}, { 650, 0x08}, { 700, 0x18}, { 750, 0x09}, | |
333 | { 800, 0x19}, { 850, 0x29}, { 900, 0x39}, { 950, 0x0a}, | |
334 | {1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b}, | |
335 | {1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c}, | |
336 | {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c} | |
337 | }; | |
338 | ||
339 | static int max_mbps_to_testdin(unsigned int max_mbps) | |
340 | { | |
341 | int i; | |
342 | ||
343 | for (i = 0; i < ARRAY_SIZE(dptdin_map); i++) | |
344 | if (dptdin_map[i].max_mbps > max_mbps) | |
345 | return dptdin_map[i].testdin; | |
346 | ||
347 | return -EINVAL; | |
348 | } | |
349 | ||
350 | /* | |
351 | * The controller should generate 2 frames before | |
352 | * preparing the peripheral. | |
353 | */ | |
0f2c3ad5 | 354 | static void dw_mipi_dsi_wait_for_two_frames(struct drm_display_mode *mode) |
84e05408 CZ |
355 | { |
356 | int refresh, two_frames; | |
357 | ||
0f2c3ad5 | 358 | refresh = drm_mode_vrefresh(mode); |
84e05408 CZ |
359 | two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2; |
360 | msleep(two_frames); | |
361 | } | |
362 | ||
363 | static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host) | |
364 | { | |
365 | return container_of(host, struct dw_mipi_dsi, dsi_host); | |
366 | } | |
367 | ||
368 | static inline struct dw_mipi_dsi *con_to_dsi(struct drm_connector *con) | |
369 | { | |
370 | return container_of(con, struct dw_mipi_dsi, connector); | |
371 | } | |
372 | ||
373 | static inline struct dw_mipi_dsi *encoder_to_dsi(struct drm_encoder *encoder) | |
374 | { | |
375 | return container_of(encoder, struct dw_mipi_dsi, encoder); | |
376 | } | |
a432e054 | 377 | |
84e05408 CZ |
378 | static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val) |
379 | { | |
380 | writel(val, dsi->base + reg); | |
381 | } | |
382 | ||
383 | static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg) | |
384 | { | |
385 | return readl(dsi->base + reg); | |
386 | } | |
387 | ||
388 | static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi *dsi, u8 test_code, | |
a432e054 | 389 | u8 test_data) |
84e05408 CZ |
390 | { |
391 | /* | |
392 | * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content | |
393 | * is latched internally as the current test code. Test data is | |
394 | * programmed internally by rising edge on TESTCLK. | |
395 | */ | |
396 | dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); | |
397 | ||
398 | dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) | | |
399 | PHY_TESTDIN(test_code)); | |
400 | ||
401 | dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR); | |
402 | ||
403 | dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) | | |
404 | PHY_TESTDIN(test_data)); | |
405 | ||
406 | dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); | |
407 | } | |
408 | ||
3fdfb4f1 JK |
409 | /** |
410 | * ns2bc - Nanoseconds to byte clock cycles | |
411 | */ | |
412 | static inline unsigned int ns2bc(struct dw_mipi_dsi *dsi, int ns) | |
413 | { | |
414 | return DIV_ROUND_UP(ns * dsi->lane_mbps / 8, 1000); | |
415 | } | |
416 | ||
417 | /** | |
418 | * ns2ui - Nanoseconds to UI time periods | |
419 | */ | |
420 | static inline unsigned int ns2ui(struct dw_mipi_dsi *dsi, int ns) | |
421 | { | |
422 | return DIV_ROUND_UP(ns * dsi->lane_mbps, 1000); | |
423 | } | |
424 | ||
84e05408 CZ |
425 | static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi) |
426 | { | |
427 | int ret, testdin, vco, val; | |
428 | ||
429 | vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200; | |
430 | ||
431 | testdin = max_mbps_to_testdin(dsi->lane_mbps); | |
432 | if (testdin < 0) { | |
433 | dev_err(dsi->dev, | |
434 | "failed to get testdin for %dmbps lane clock\n", | |
435 | dsi->lane_mbps); | |
436 | return testdin; | |
437 | } | |
438 | ||
efe83cee JK |
439 | /* Start by clearing PHY state */ |
440 | dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR); | |
441 | dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR); | |
442 | dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR); | |
84e05408 | 443 | |
ef6eba19 CZ |
444 | ret = clk_prepare_enable(dsi->phy_cfg_clk); |
445 | if (ret) { | |
446 | dev_err(dsi->dev, "Failed to enable phy_cfg_clk\n"); | |
447 | return ret; | |
448 | } | |
449 | ||
84e05408 CZ |
450 | dw_mipi_dsi_phy_write(dsi, 0x10, BYPASS_VCO_RANGE | |
451 | VCO_RANGE_CON_SEL(vco) | | |
452 | VCO_IN_CAP_CON_LOW | | |
453 | REF_BIAS_CUR_SEL); | |
454 | ||
455 | dw_mipi_dsi_phy_write(dsi, 0x11, CP_CURRENT_3MA); | |
456 | dw_mipi_dsi_phy_write(dsi, 0x12, CP_PROGRAM_EN | LPF_PROGRAM_EN | | |
457 | LPF_RESISTORS_20_KOHM); | |
458 | ||
459 | dw_mipi_dsi_phy_write(dsi, 0x44, HSFREQRANGE_SEL(testdin)); | |
460 | ||
84e05408 CZ |
461 | dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->input_div)); |
462 | dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_LOW_SEL(dsi->feedback_div) | | |
463 | LOW_PROGRAM_EN); | |
464 | dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_HIGH_SEL(dsi->feedback_div) | | |
465 | HIGH_PROGRAM_EN); | |
d969c155 JK |
466 | dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN); |
467 | ||
468 | dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN | | |
469 | BIASEXTR_SEL(BIASEXTR_127_7)); | |
470 | dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN | | |
471 | BANDGAP_SEL(BANDGAP_96_10)); | |
84e05408 CZ |
472 | |
473 | dw_mipi_dsi_phy_write(dsi, 0x20, POWER_CONTROL | INTERNAL_REG_CURRENT | | |
474 | BIAS_BLOCK_ON | BANDGAP_ON); | |
475 | ||
476 | dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_LOW | TER_CAL_DONE | | |
477 | SETRD_MAX | TER_RESISTORS_ON); | |
478 | dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON | | |
479 | SETRD_MAX | POWER_MANAGE | | |
480 | TER_RESISTORS_ON); | |
481 | ||
3fdfb4f1 JK |
482 | dw_mipi_dsi_phy_write(dsi, 0x60, TLP_PROGRAM_EN | ns2bc(dsi, 500)); |
483 | dw_mipi_dsi_phy_write(dsi, 0x61, THS_PRE_PROGRAM_EN | ns2ui(dsi, 40)); | |
484 | dw_mipi_dsi_phy_write(dsi, 0x62, THS_ZERO_PROGRAM_EN | ns2bc(dsi, 300)); | |
485 | dw_mipi_dsi_phy_write(dsi, 0x63, THS_PRE_PROGRAM_EN | ns2ui(dsi, 100)); | |
486 | dw_mipi_dsi_phy_write(dsi, 0x64, BIT(5) | ns2bc(dsi, 100)); | |
487 | dw_mipi_dsi_phy_write(dsi, 0x65, BIT(5) | (ns2bc(dsi, 60) + 7)); | |
488 | ||
489 | dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | ns2bc(dsi, 500)); | |
490 | dw_mipi_dsi_phy_write(dsi, 0x71, | |
491 | THS_PRE_PROGRAM_EN | (ns2ui(dsi, 50) + 5)); | |
492 | dw_mipi_dsi_phy_write(dsi, 0x72, | |
493 | THS_ZERO_PROGRAM_EN | (ns2bc(dsi, 140) + 2)); | |
494 | dw_mipi_dsi_phy_write(dsi, 0x73, | |
495 | THS_PRE_PROGRAM_EN | (ns2ui(dsi, 60) + 8)); | |
496 | dw_mipi_dsi_phy_write(dsi, 0x74, BIT(5) | ns2bc(dsi, 100)); | |
84e05408 CZ |
497 | |
498 | dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK | | |
499 | PHY_UNRSTZ | PHY_UNSHUTDOWNZ); | |
500 | ||
44136971 | 501 | ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, |
84e05408 CZ |
502 | val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US); |
503 | if (ret < 0) { | |
504 | dev_err(dsi->dev, "failed to wait for phy lock state\n"); | |
ef6eba19 | 505 | goto phy_init_end; |
84e05408 CZ |
506 | } |
507 | ||
44136971 | 508 | ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, |
84e05408 CZ |
509 | val, val & STOP_STATE_CLK_LANE, 1000, |
510 | PHY_STATUS_TIMEOUT_US); | |
ef6eba19 | 511 | if (ret < 0) |
84e05408 CZ |
512 | dev_err(dsi->dev, |
513 | "failed to wait for phy clk lane stop state\n"); | |
ef6eba19 CZ |
514 | |
515 | phy_init_end: | |
516 | clk_disable_unprepare(dsi->phy_cfg_clk); | |
84e05408 CZ |
517 | |
518 | return ret; | |
519 | } | |
520 | ||
0f2c3ad5 JK |
521 | static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi, |
522 | struct drm_display_mode *mode) | |
84e05408 | 523 | { |
484bb6c9 | 524 | unsigned int i, pre; |
84e05408 CZ |
525 | unsigned long mpclk, pllref, tmp; |
526 | unsigned int m = 1, n = 1, target_mbps = 1000; | |
527 | unsigned int max_mbps = dptdin_map[ARRAY_SIZE(dptdin_map) - 1].max_mbps; | |
484bb6c9 | 528 | int bpp; |
84e05408 CZ |
529 | |
530 | bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); | |
531 | if (bpp < 0) { | |
532 | dev_err(dsi->dev, "failed to get bpp for pixel format %d\n", | |
533 | dsi->format); | |
534 | return bpp; | |
535 | } | |
536 | ||
0f2c3ad5 | 537 | mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC); |
84e05408 | 538 | if (mpclk) { |
ad1c974b CZ |
539 | /* take 1 / 0.8, since mbps must big than bandwidth of RGB */ |
540 | tmp = mpclk * (bpp / dsi->lanes) * 10 / 8; | |
84e05408 CZ |
541 | if (tmp < max_mbps) |
542 | target_mbps = tmp; | |
543 | else | |
544 | dev_err(dsi->dev, "DPHY clock frequency is out of range\n"); | |
545 | } | |
546 | ||
547 | pllref = DIV_ROUND_UP(clk_get_rate(dsi->pllref_clk), USEC_PER_SEC); | |
548 | tmp = pllref; | |
549 | ||
b0a45fec JK |
550 | /* |
551 | * The limits on the PLL divisor are: | |
552 | * | |
553 | * 5MHz <= (pllref / n) <= 40MHz | |
554 | * | |
555 | * we walk over these values in descreasing order so that if we hit | |
556 | * an exact match for target_mbps it is more likely that "m" will be | |
557 | * even. | |
558 | * | |
559 | * TODO: ensure that "m" is even after this loop. | |
560 | */ | |
561 | for (i = pllref / 5; i > (pllref / 40); i--) { | |
84e05408 CZ |
562 | pre = pllref / i; |
563 | if ((tmp > (target_mbps % pre)) && (target_mbps / pre < 512)) { | |
564 | tmp = target_mbps % pre; | |
565 | n = i; | |
566 | m = target_mbps / pre; | |
567 | } | |
568 | if (tmp == 0) | |
569 | break; | |
570 | } | |
571 | ||
572 | dsi->lane_mbps = pllref / n * m; | |
573 | dsi->input_div = n; | |
574 | dsi->feedback_div = m; | |
575 | ||
576 | return 0; | |
577 | } | |
578 | ||
579 | static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host, | |
580 | struct mipi_dsi_device *device) | |
581 | { | |
582 | struct dw_mipi_dsi *dsi = host_to_dsi(host); | |
583 | ||
584 | if (device->lanes > dsi->pdata->max_data_lanes) { | |
585 | dev_err(dsi->dev, "the number of data lanes(%u) is too many\n", | |
a432e054 | 586 | device->lanes); |
84e05408 CZ |
587 | return -EINVAL; |
588 | } | |
589 | ||
84e05408 CZ |
590 | dsi->lanes = device->lanes; |
591 | dsi->channel = device->channel; | |
592 | dsi->format = device->format; | |
03a5832c | 593 | dsi->mode_flags = device->mode_flags; |
84e05408 CZ |
594 | dsi->panel = of_drm_find_panel(device->dev.of_node); |
595 | if (dsi->panel) | |
596 | return drm_panel_attach(dsi->panel, &dsi->connector); | |
597 | ||
598 | return -EINVAL; | |
599 | } | |
600 | ||
601 | static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host, | |
602 | struct mipi_dsi_device *device) | |
603 | { | |
604 | struct dw_mipi_dsi *dsi = host_to_dsi(host); | |
605 | ||
606 | drm_panel_detach(dsi->panel); | |
607 | ||
608 | return 0; | |
609 | } | |
610 | ||
52c66e4f JK |
611 | static void dw_mipi_message_config(struct dw_mipi_dsi *dsi, |
612 | const struct mipi_dsi_msg *msg) | |
613 | { | |
7361c6f8 | 614 | bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM; |
52c66e4f JK |
615 | u32 val = 0; |
616 | ||
617 | if (msg->flags & MIPI_DSI_MSG_REQ_ACK) | |
618 | val |= EN_ACK_RQST; | |
7361c6f8 | 619 | if (lpm) |
52c66e4f JK |
620 | val |= CMD_MODE_ALL_LP; |
621 | ||
7361c6f8 | 622 | dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS); |
52c66e4f JK |
623 | dsi_write(dsi, DSI_CMD_MODE_CFG, val); |
624 | } | |
625 | ||
d3852c21 | 626 | static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val) |
84e05408 CZ |
627 | { |
628 | int ret; | |
480564a0 | 629 | u32 val, mask; |
84e05408 | 630 | |
44136971 | 631 | ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, |
84e05408 CZ |
632 | val, !(val & GEN_CMD_FULL), 1000, |
633 | CMD_PKT_STATUS_TIMEOUT_US); | |
634 | if (ret < 0) { | |
635 | dev_err(dsi->dev, "failed to get available command FIFO\n"); | |
636 | return ret; | |
637 | } | |
638 | ||
d3852c21 | 639 | dsi_write(dsi, DSI_GEN_HDR, hdr_val); |
84e05408 | 640 | |
480564a0 | 641 | mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY; |
44136971 | 642 | ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, |
480564a0 | 643 | val, (val & mask) == mask, |
84e05408 CZ |
644 | 1000, CMD_PKT_STATUS_TIMEOUT_US); |
645 | if (ret < 0) { | |
646 | dev_err(dsi->dev, "failed to write command FIFO\n"); | |
647 | return ret; | |
648 | } | |
649 | ||
650 | return 0; | |
651 | } | |
652 | ||
653 | static int dw_mipi_dsi_dcs_short_write(struct dw_mipi_dsi *dsi, | |
654 | const struct mipi_dsi_msg *msg) | |
655 | { | |
dad17ed0 JK |
656 | const u8 *tx_buf = msg->tx_buf; |
657 | u16 data = 0; | |
658 | u32 val; | |
659 | ||
660 | if (msg->tx_len > 0) | |
661 | data |= tx_buf[0]; | |
662 | if (msg->tx_len > 1) | |
663 | data |= tx_buf[1] << 8; | |
84e05408 CZ |
664 | |
665 | if (msg->tx_len > 2) { | |
666 | dev_err(dsi->dev, "too long tx buf length %zu for short write\n", | |
667 | msg->tx_len); | |
668 | return -EINVAL; | |
669 | } | |
670 | ||
dad17ed0 | 671 | val = GEN_HDATA(data) | GEN_HTYPE(msg->type); |
84e05408 CZ |
672 | return dw_mipi_dsi_gen_pkt_hdr_write(dsi, val); |
673 | } | |
674 | ||
675 | static int dw_mipi_dsi_dcs_long_write(struct dw_mipi_dsi *dsi, | |
676 | const struct mipi_dsi_msg *msg) | |
677 | { | |
1ed498b0 JK |
678 | const u8 *tx_buf = msg->tx_buf; |
679 | int len = msg->tx_len, pld_data_bytes = sizeof(u32), ret; | |
d3852c21 | 680 | u32 hdr_val = GEN_HDATA(msg->tx_len) | GEN_HTYPE(msg->type); |
1ed498b0 | 681 | u32 remainder; |
d3852c21 | 682 | u32 val; |
84e05408 CZ |
683 | |
684 | if (msg->tx_len < 3) { | |
685 | dev_err(dsi->dev, "wrong tx buf length %zu for long write\n", | |
686 | msg->tx_len); | |
687 | return -EINVAL; | |
688 | } | |
689 | ||
690 | while (DIV_ROUND_UP(len, pld_data_bytes)) { | |
691 | if (len < pld_data_bytes) { | |
1ed498b0 | 692 | remainder = 0; |
84e05408 CZ |
693 | memcpy(&remainder, tx_buf, len); |
694 | dsi_write(dsi, DSI_GEN_PLD_DATA, remainder); | |
695 | len = 0; | |
696 | } else { | |
1ed498b0 JK |
697 | memcpy(&remainder, tx_buf, pld_data_bytes); |
698 | dsi_write(dsi, DSI_GEN_PLD_DATA, remainder); | |
699 | tx_buf += pld_data_bytes; | |
84e05408 CZ |
700 | len -= pld_data_bytes; |
701 | } | |
702 | ||
44136971 | 703 | ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, |
84e05408 CZ |
704 | val, !(val & GEN_PLD_W_FULL), 1000, |
705 | CMD_PKT_STATUS_TIMEOUT_US); | |
706 | if (ret < 0) { | |
707 | dev_err(dsi->dev, | |
708 | "failed to get available write payload FIFO\n"); | |
709 | return ret; | |
710 | } | |
711 | } | |
712 | ||
d3852c21 | 713 | return dw_mipi_dsi_gen_pkt_hdr_write(dsi, hdr_val); |
84e05408 CZ |
714 | } |
715 | ||
716 | static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host, | |
717 | const struct mipi_dsi_msg *msg) | |
718 | { | |
719 | struct dw_mipi_dsi *dsi = host_to_dsi(host); | |
720 | int ret; | |
721 | ||
52c66e4f JK |
722 | dw_mipi_message_config(dsi, msg); |
723 | ||
84e05408 CZ |
724 | switch (msg->type) { |
725 | case MIPI_DSI_DCS_SHORT_WRITE: | |
726 | case MIPI_DSI_DCS_SHORT_WRITE_PARAM: | |
727 | case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE: | |
728 | ret = dw_mipi_dsi_dcs_short_write(dsi, msg); | |
729 | break; | |
730 | case MIPI_DSI_DCS_LONG_WRITE: | |
731 | ret = dw_mipi_dsi_dcs_long_write(dsi, msg); | |
732 | break; | |
733 | default: | |
028316fb JK |
734 | dev_err(dsi->dev, "unsupported message type 0x%02x\n", |
735 | msg->type); | |
84e05408 CZ |
736 | ret = -EINVAL; |
737 | } | |
738 | ||
739 | return ret; | |
740 | } | |
741 | ||
742 | static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = { | |
743 | .attach = dw_mipi_dsi_host_attach, | |
744 | .detach = dw_mipi_dsi_host_detach, | |
745 | .transfer = dw_mipi_dsi_host_transfer, | |
746 | }; | |
747 | ||
748 | static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi) | |
749 | { | |
750 | u32 val; | |
751 | ||
03a5832c JK |
752 | val = ENABLE_LOW_POWER; |
753 | ||
754 | if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) | |
755 | val |= VID_MODE_TYPE_BURST; | |
756 | else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) | |
757 | val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES; | |
758 | else | |
759 | val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS; | |
84e05408 CZ |
760 | |
761 | dsi_write(dsi, DSI_VID_MODE_CFG, val); | |
762 | } | |
763 | ||
764 | static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi, | |
765 | enum dw_mipi_dsi_mode mode) | |
766 | { | |
767 | if (mode == DW_MIPI_DSI_CMD_MODE) { | |
768 | dsi_write(dsi, DSI_PWR_UP, RESET); | |
769 | dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE); | |
770 | dsi_write(dsi, DSI_PWR_UP, POWERUP); | |
771 | } else { | |
772 | dsi_write(dsi, DSI_PWR_UP, RESET); | |
773 | dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE); | |
774 | dw_mipi_dsi_video_mode_config(dsi); | |
7361c6f8 | 775 | dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS); |
84e05408 CZ |
776 | dsi_write(dsi, DSI_PWR_UP, POWERUP); |
777 | } | |
778 | } | |
779 | ||
780 | static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi) | |
781 | { | |
782 | dsi_write(dsi, DSI_PWR_UP, RESET); | |
783 | dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ); | |
784 | } | |
785 | ||
786 | static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi) | |
787 | { | |
1bef24ba JK |
788 | /* |
789 | * The maximum permitted escape clock is 20MHz and it is derived from | |
790 | * lanebyteclk, which is running at "lane_mbps / 8". Thus we want: | |
791 | * | |
792 | * (lane_mbps >> 3) / esc_clk_division < 20 | |
793 | * which is: | |
794 | * (lane_mbps >> 3) / 20 > esc_clk_division | |
795 | */ | |
796 | u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1; | |
797 | ||
84e05408 CZ |
798 | dsi_write(dsi, DSI_PWR_UP, RESET); |
799 | dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK | |
800 | | PHY_RSTZ | PHY_SHUTDOWNZ); | |
801 | dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) | | |
1bef24ba | 802 | TX_ESC_CLK_DIVIDSION(esc_clk_division)); |
84e05408 CZ |
803 | } |
804 | ||
805 | static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi, | |
806 | struct drm_display_mode *mode) | |
807 | { | |
808 | u32 val = 0, color = 0; | |
809 | ||
810 | switch (dsi->format) { | |
811 | case MIPI_DSI_FMT_RGB888: | |
812 | color = DPI_COLOR_CODING_24BIT; | |
813 | break; | |
814 | case MIPI_DSI_FMT_RGB666: | |
815 | color = DPI_COLOR_CODING_18BIT_2 | EN18_LOOSELY; | |
816 | break; | |
817 | case MIPI_DSI_FMT_RGB666_PACKED: | |
818 | color = DPI_COLOR_CODING_18BIT_1; | |
819 | break; | |
820 | case MIPI_DSI_FMT_RGB565: | |
821 | color = DPI_COLOR_CODING_16BIT_1; | |
822 | break; | |
823 | } | |
824 | ||
2b0c4b70 | 825 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) |
84e05408 | 826 | val |= VSYNC_ACTIVE_LOW; |
2b0c4b70 | 827 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) |
84e05408 CZ |
828 | val |= HSYNC_ACTIVE_LOW; |
829 | ||
830 | dsi_write(dsi, DSI_DPI_VCID, DPI_VID(dsi->channel)); | |
831 | dsi_write(dsi, DSI_DPI_COLOR_CODING, color); | |
832 | dsi_write(dsi, DSI_DPI_CFG_POL, val); | |
833 | dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4) | |
834 | | INVACT_LPCMD_TIME(4)); | |
835 | } | |
836 | ||
837 | static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi) | |
838 | { | |
839 | dsi_write(dsi, DSI_PCKHDL_CFG, EN_CRC_RX | EN_ECC_RX | EN_BTA); | |
840 | } | |
841 | ||
842 | static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi, | |
843 | struct drm_display_mode *mode) | |
844 | { | |
845 | dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(mode->hdisplay)); | |
846 | } | |
847 | ||
848 | static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi) | |
849 | { | |
850 | dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000)); | |
851 | dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00); | |
84e05408 CZ |
852 | dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE); |
853 | } | |
854 | ||
855 | /* Get lane byte clock cycles. */ | |
856 | static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi, | |
0f2c3ad5 | 857 | struct drm_display_mode *mode, |
84e05408 CZ |
858 | u32 hcomponent) |
859 | { | |
860 | u32 frac, lbcc; | |
861 | ||
862 | lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8; | |
863 | ||
0f2c3ad5 JK |
864 | frac = lbcc % mode->clock; |
865 | lbcc = lbcc / mode->clock; | |
84e05408 CZ |
866 | if (frac) |
867 | lbcc++; | |
868 | ||
869 | return lbcc; | |
870 | } | |
871 | ||
0f2c3ad5 JK |
872 | static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi, |
873 | struct drm_display_mode *mode) | |
84e05408 CZ |
874 | { |
875 | u32 htotal, hsa, hbp, lbcc; | |
84e05408 CZ |
876 | |
877 | htotal = mode->htotal; | |
878 | hsa = mode->hsync_end - mode->hsync_start; | |
879 | hbp = mode->htotal - mode->hsync_end; | |
880 | ||
0f2c3ad5 | 881 | lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, htotal); |
84e05408 CZ |
882 | dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc); |
883 | ||
0f2c3ad5 | 884 | lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hsa); |
84e05408 CZ |
885 | dsi_write(dsi, DSI_VID_HSA_TIME, lbcc); |
886 | ||
0f2c3ad5 | 887 | lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hbp); |
84e05408 CZ |
888 | dsi_write(dsi, DSI_VID_HBP_TIME, lbcc); |
889 | } | |
890 | ||
0f2c3ad5 JK |
891 | static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi, |
892 | struct drm_display_mode *mode) | |
84e05408 CZ |
893 | { |
894 | u32 vactive, vsa, vfp, vbp; | |
84e05408 CZ |
895 | |
896 | vactive = mode->vdisplay; | |
897 | vsa = mode->vsync_end - mode->vsync_start; | |
898 | vfp = mode->vsync_start - mode->vdisplay; | |
899 | vbp = mode->vtotal - mode->vsync_end; | |
900 | ||
901 | dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive); | |
902 | dsi_write(dsi, DSI_VID_VSA_LINES, vsa); | |
903 | dsi_write(dsi, DSI_VID_VFP_LINES, vfp); | |
904 | dsi_write(dsi, DSI_VID_VBP_LINES, vbp); | |
905 | } | |
906 | ||
907 | static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi) | |
908 | { | |
909 | dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x40) | |
910 | | PHY_LP2HS_TIME(0x40) | MAX_RD_TIME(10000)); | |
911 | ||
912 | dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40) | |
913 | | PHY_CLKLP2HS_TIME(0x40)); | |
914 | } | |
915 | ||
916 | static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi) | |
917 | { | |
918 | dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) | | |
919 | N_LANES(dsi->lanes)); | |
920 | } | |
921 | ||
922 | static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi) | |
923 | { | |
924 | dsi_read(dsi, DSI_INT_ST0); | |
925 | dsi_read(dsi, DSI_INT_ST1); | |
926 | dsi_write(dsi, DSI_INT_MSK0, 0); | |
927 | dsi_write(dsi, DSI_INT_MSK1, 0); | |
928 | } | |
929 | ||
84e05408 CZ |
930 | static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder) |
931 | { | |
932 | struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder); | |
933 | ||
80a9a059 CZ |
934 | if (dsi->dpms_mode != DRM_MODE_DPMS_ON) |
935 | return; | |
936 | ||
84e05408 CZ |
937 | if (clk_prepare_enable(dsi->pclk)) { |
938 | dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__); | |
939 | return; | |
940 | } | |
941 | ||
96ad6f0b JK |
942 | drm_panel_disable(dsi->panel); |
943 | ||
84e05408 CZ |
944 | dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_CMD_MODE); |
945 | drm_panel_unprepare(dsi->panel); | |
84e05408 | 946 | |
84e05408 | 947 | dw_mipi_dsi_disable(dsi); |
80a9a059 | 948 | pm_runtime_put(dsi->dev); |
84e05408 | 949 | clk_disable_unprepare(dsi->pclk); |
80a9a059 | 950 | dsi->dpms_mode = DRM_MODE_DPMS_OFF; |
84e05408 CZ |
951 | } |
952 | ||
5e408d7a | 953 | static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder) |
84e05408 CZ |
954 | { |
955 | struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder); | |
2ba0f4a4 | 956 | struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; |
ef6eba19 | 957 | const struct dw_mipi_dsi_plat_data *pdata = dsi->pdata; |
16450616 | 958 | int mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, encoder); |
84e05408 | 959 | u32 val; |
5e408d7a JK |
960 | int ret; |
961 | ||
0f2c3ad5 | 962 | ret = dw_mipi_dsi_get_lane_bps(dsi, mode); |
5e408d7a JK |
963 | if (ret < 0) |
964 | return; | |
84e05408 | 965 | |
80a9a059 CZ |
966 | if (dsi->dpms_mode == DRM_MODE_DPMS_ON) |
967 | return; | |
968 | ||
84e05408 CZ |
969 | if (clk_prepare_enable(dsi->pclk)) { |
970 | dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__); | |
971 | return; | |
972 | } | |
973 | ||
80a9a059 | 974 | pm_runtime_get_sync(dsi->dev); |
5e408d7a | 975 | dw_mipi_dsi_init(dsi); |
0f2c3ad5 | 976 | dw_mipi_dsi_dpi_config(dsi, mode); |
5e408d7a JK |
977 | dw_mipi_dsi_packet_handler_config(dsi); |
978 | dw_mipi_dsi_video_mode_config(dsi); | |
0f2c3ad5 | 979 | dw_mipi_dsi_video_packet_config(dsi, mode); |
5e408d7a | 980 | dw_mipi_dsi_command_mode_config(dsi); |
0f2c3ad5 JK |
981 | dw_mipi_dsi_line_timer_config(dsi, mode); |
982 | dw_mipi_dsi_vertical_timing_config(dsi, mode); | |
5e408d7a JK |
983 | dw_mipi_dsi_dphy_timing_config(dsi); |
984 | dw_mipi_dsi_dphy_interface_config(dsi); | |
985 | dw_mipi_dsi_clear_err(dsi); | |
5e408d7a | 986 | |
5bc07b15 CZ |
987 | /* |
988 | * For the RK3399, the clk of grf must be enabled before writing grf | |
989 | * register. And for RK3288 or other soc, this grf_clk must be NULL, | |
990 | * the clk_prepare_enable return true directly. | |
991 | */ | |
992 | ret = clk_prepare_enable(dsi->grf_clk); | |
993 | if (ret) { | |
994 | dev_err(dsi->dev, "Failed to enable grf_clk: %d\n", ret); | |
995 | return; | |
996 | } | |
997 | ||
ef6eba19 CZ |
998 | if (pdata->grf_dsi0_mode_reg) |
999 | regmap_write(dsi->grf_regmap, pdata->grf_dsi0_mode_reg, | |
1000 | pdata->grf_dsi0_mode); | |
1001 | ||
84e05408 | 1002 | dw_mipi_dsi_phy_init(dsi); |
0f2c3ad5 | 1003 | dw_mipi_dsi_wait_for_two_frames(mode); |
84e05408 | 1004 | |
8a7df73f JK |
1005 | dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_CMD_MODE); |
1006 | if (drm_panel_prepare(dsi->panel)) | |
1007 | dev_err(dsi->dev, "failed to prepare panel\n"); | |
1008 | ||
84e05408 CZ |
1009 | dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_VID_MODE); |
1010 | drm_panel_enable(dsi->panel); | |
1011 | ||
1012 | clk_disable_unprepare(dsi->pclk); | |
1013 | ||
4e257d9e | 1014 | if (mux) |
ef6eba19 | 1015 | val = pdata->dsi0_en_bit | (pdata->dsi0_en_bit << 16); |
4e257d9e | 1016 | else |
ef6eba19 | 1017 | val = pdata->dsi0_en_bit << 16; |
4e257d9e | 1018 | |
ef6eba19 | 1019 | regmap_write(dsi->grf_regmap, pdata->grf_switch_reg, val); |
4e257d9e | 1020 | dev_dbg(dsi->dev, "vop %s output to dsi0\n", (mux) ? "LIT" : "BIG"); |
80a9a059 | 1021 | dsi->dpms_mode = DRM_MODE_DPMS_ON; |
5bc07b15 CZ |
1022 | |
1023 | clk_disable_unprepare(dsi->grf_clk); | |
4e257d9e MY |
1024 | } |
1025 | ||
1026 | static int | |
1027 | dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder, | |
1028 | struct drm_crtc_state *crtc_state, | |
1029 | struct drm_connector_state *conn_state) | |
1030 | { | |
1031 | struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); | |
1032 | struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder); | |
1033 | ||
84e05408 CZ |
1034 | switch (dsi->format) { |
1035 | case MIPI_DSI_FMT_RGB888: | |
4e257d9e | 1036 | s->output_mode = ROCKCHIP_OUT_MODE_P888; |
84e05408 CZ |
1037 | break; |
1038 | case MIPI_DSI_FMT_RGB666: | |
4e257d9e | 1039 | s->output_mode = ROCKCHIP_OUT_MODE_P666; |
84e05408 CZ |
1040 | break; |
1041 | case MIPI_DSI_FMT_RGB565: | |
4e257d9e | 1042 | s->output_mode = ROCKCHIP_OUT_MODE_P565; |
84e05408 CZ |
1043 | break; |
1044 | default: | |
1045 | WARN_ON(1); | |
4e257d9e | 1046 | return -EINVAL; |
84e05408 CZ |
1047 | } |
1048 | ||
4e257d9e | 1049 | s->output_type = DRM_MODE_CONNECTOR_DSI; |
84e05408 | 1050 | |
4e257d9e | 1051 | return 0; |
84e05408 CZ |
1052 | } |
1053 | ||
a432e054 | 1054 | static const struct drm_encoder_helper_funcs |
84e05408 | 1055 | dw_mipi_dsi_encoder_helper_funcs = { |
5e408d7a | 1056 | .enable = dw_mipi_dsi_encoder_enable, |
84e05408 | 1057 | .disable = dw_mipi_dsi_encoder_disable, |
4e257d9e | 1058 | .atomic_check = dw_mipi_dsi_encoder_atomic_check, |
84e05408 CZ |
1059 | }; |
1060 | ||
a432e054 | 1061 | static const struct drm_encoder_funcs dw_mipi_dsi_encoder_funcs = { |
84e05408 CZ |
1062 | .destroy = drm_encoder_cleanup, |
1063 | }; | |
1064 | ||
1065 | static int dw_mipi_dsi_connector_get_modes(struct drm_connector *connector) | |
1066 | { | |
1067 | struct dw_mipi_dsi *dsi = con_to_dsi(connector); | |
1068 | ||
1069 | return drm_panel_get_modes(dsi->panel); | |
1070 | } | |
1071 | ||
84e05408 CZ |
1072 | static struct drm_connector_helper_funcs dw_mipi_dsi_connector_helper_funcs = { |
1073 | .get_modes = dw_mipi_dsi_connector_get_modes, | |
84e05408 CZ |
1074 | }; |
1075 | ||
84e05408 CZ |
1076 | static void dw_mipi_dsi_drm_connector_destroy(struct drm_connector *connector) |
1077 | { | |
1078 | drm_connector_unregister(connector); | |
1079 | drm_connector_cleanup(connector); | |
1080 | } | |
1081 | ||
a432e054 | 1082 | static const struct drm_connector_funcs dw_mipi_dsi_atomic_connector_funcs = { |
84e05408 | 1083 | .fill_modes = drm_helper_probe_single_connector_modes, |
84e05408 CZ |
1084 | .destroy = dw_mipi_dsi_drm_connector_destroy, |
1085 | .reset = drm_atomic_helper_connector_reset, | |
1086 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, | |
1087 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, | |
1088 | }; | |
1089 | ||
1090 | static int dw_mipi_dsi_register(struct drm_device *drm, | |
a432e054 | 1091 | struct dw_mipi_dsi *dsi) |
84e05408 CZ |
1092 | { |
1093 | struct drm_encoder *encoder = &dsi->encoder; | |
1094 | struct drm_connector *connector = &dsi->connector; | |
1095 | struct device *dev = dsi->dev; | |
1096 | int ret; | |
1097 | ||
1098 | encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, | |
1099 | dev->of_node); | |
1100 | /* | |
1101 | * If we failed to find the CRTC(s) which this encoder is | |
1102 | * supposed to be connected to, it's because the CRTC has | |
1103 | * not been registered yet. Defer probing, and hope that | |
1104 | * the required CRTC is added later. | |
1105 | */ | |
1106 | if (encoder->possible_crtcs == 0) | |
1107 | return -EPROBE_DEFER; | |
1108 | ||
1109 | drm_encoder_helper_add(&dsi->encoder, | |
1110 | &dw_mipi_dsi_encoder_helper_funcs); | |
1111 | ret = drm_encoder_init(drm, &dsi->encoder, &dw_mipi_dsi_encoder_funcs, | |
a432e054 | 1112 | DRM_MODE_ENCODER_DSI, NULL); |
84e05408 CZ |
1113 | if (ret) { |
1114 | dev_err(dev, "Failed to initialize encoder with drm\n"); | |
1115 | return ret; | |
1116 | } | |
1117 | ||
1118 | drm_connector_helper_add(connector, | |
a432e054 | 1119 | &dw_mipi_dsi_connector_helper_funcs); |
84e05408 CZ |
1120 | |
1121 | drm_connector_init(drm, &dsi->connector, | |
1122 | &dw_mipi_dsi_atomic_connector_funcs, | |
1123 | DRM_MODE_CONNECTOR_DSI); | |
1124 | ||
1125 | drm_mode_connector_attach_encoder(connector, encoder); | |
1126 | ||
1127 | return 0; | |
1128 | } | |
1129 | ||
1130 | static int rockchip_mipi_parse_dt(struct dw_mipi_dsi *dsi) | |
1131 | { | |
1132 | struct device_node *np = dsi->dev->of_node; | |
1133 | ||
1134 | dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); | |
1135 | if (IS_ERR(dsi->grf_regmap)) { | |
1136 | dev_err(dsi->dev, "Unable to get rockchip,grf\n"); | |
1137 | return PTR_ERR(dsi->grf_regmap); | |
1138 | } | |
1139 | ||
1140 | return 0; | |
1141 | } | |
1142 | ||
84e05408 | 1143 | static struct dw_mipi_dsi_plat_data rk3288_mipi_dsi_drv_data = { |
ef6eba19 CZ |
1144 | .dsi0_en_bit = RK3288_DSI0_SEL_VOP_LIT, |
1145 | .dsi1_en_bit = RK3288_DSI1_SEL_VOP_LIT, | |
1146 | .grf_switch_reg = RK3288_GRF_SOC_CON6, | |
84e05408 | 1147 | .max_data_lanes = 4, |
84e05408 CZ |
1148 | }; |
1149 | ||
ef6eba19 CZ |
1150 | static struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_drv_data = { |
1151 | .dsi0_en_bit = RK3399_DSI0_SEL_VOP_LIT, | |
1152 | .dsi1_en_bit = RK3399_DSI1_SEL_VOP_LIT, | |
395eaaae | 1153 | .grf_switch_reg = RK3399_GRF_SOC_CON20, |
ef6eba19 CZ |
1154 | .grf_dsi0_mode = RK3399_GRF_DSI_MODE, |
1155 | .grf_dsi0_mode_reg = RK3399_GRF_SOC_CON22, | |
5bc07b15 | 1156 | .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK, |
ef6eba19 CZ |
1157 | .max_data_lanes = 4, |
1158 | }; | |
1159 | ||
84e05408 CZ |
1160 | static const struct of_device_id dw_mipi_dsi_dt_ids[] = { |
1161 | { | |
1162 | .compatible = "rockchip,rk3288-mipi-dsi", | |
1163 | .data = &rk3288_mipi_dsi_drv_data, | |
ef6eba19 CZ |
1164 | }, { |
1165 | .compatible = "rockchip,rk3399-mipi-dsi", | |
1166 | .data = &rk3399_mipi_dsi_drv_data, | |
84e05408 CZ |
1167 | }, |
1168 | { /* sentinel */ } | |
1169 | }; | |
1170 | MODULE_DEVICE_TABLE(of, dw_mipi_dsi_dt_ids); | |
1171 | ||
1172 | static int dw_mipi_dsi_bind(struct device *dev, struct device *master, | |
a432e054 | 1173 | void *data) |
84e05408 CZ |
1174 | { |
1175 | const struct of_device_id *of_id = | |
1176 | of_match_device(dw_mipi_dsi_dt_ids, dev); | |
1177 | const struct dw_mipi_dsi_plat_data *pdata = of_id->data; | |
1178 | struct platform_device *pdev = to_platform_device(dev); | |
f3b7a5b8 | 1179 | struct reset_control *apb_rst; |
84e05408 CZ |
1180 | struct drm_device *drm = data; |
1181 | struct dw_mipi_dsi *dsi; | |
1182 | struct resource *res; | |
1183 | int ret; | |
1184 | ||
1185 | dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); | |
1186 | if (!dsi) | |
1187 | return -ENOMEM; | |
1188 | ||
1189 | dsi->dev = dev; | |
1190 | dsi->pdata = pdata; | |
80a9a059 | 1191 | dsi->dpms_mode = DRM_MODE_DPMS_OFF; |
84e05408 CZ |
1192 | |
1193 | ret = rockchip_mipi_parse_dt(dsi); | |
1194 | if (ret) | |
1195 | return ret; | |
1196 | ||
1197 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1198 | if (!res) | |
1199 | return -ENODEV; | |
1200 | ||
1201 | dsi->base = devm_ioremap_resource(dev, res); | |
1202 | if (IS_ERR(dsi->base)) | |
1203 | return PTR_ERR(dsi->base); | |
1204 | ||
1205 | dsi->pllref_clk = devm_clk_get(dev, "ref"); | |
1206 | if (IS_ERR(dsi->pllref_clk)) { | |
1207 | ret = PTR_ERR(dsi->pllref_clk); | |
1208 | dev_err(dev, "Unable to get pll reference clock: %d\n", ret); | |
1209 | return ret; | |
1210 | } | |
1211 | ||
1212 | dsi->pclk = devm_clk_get(dev, "pclk"); | |
1213 | if (IS_ERR(dsi->pclk)) { | |
1214 | ret = PTR_ERR(dsi->pclk); | |
1215 | dev_err(dev, "Unable to get pclk: %d\n", ret); | |
1216 | return ret; | |
1217 | } | |
1218 | ||
f3b7a5b8 JK |
1219 | /* |
1220 | * Note that the reset was not defined in the initial device tree, so | |
1221 | * we have to be prepared for it not being found. | |
1222 | */ | |
1223 | apb_rst = devm_reset_control_get(dev, "apb"); | |
1224 | if (IS_ERR(apb_rst)) { | |
1225 | ret = PTR_ERR(apb_rst); | |
1226 | if (ret == -ENOENT) { | |
1227 | apb_rst = NULL; | |
1228 | } else { | |
1229 | dev_err(dev, "Unable to get reset control: %d\n", ret); | |
1230 | return ret; | |
1231 | } | |
1232 | } | |
1233 | ||
1234 | if (apb_rst) { | |
1235 | ret = clk_prepare_enable(dsi->pclk); | |
1236 | if (ret) { | |
1237 | dev_err(dev, "%s: Failed to enable pclk\n", __func__); | |
1238 | return ret; | |
1239 | } | |
1240 | ||
1241 | reset_control_assert(apb_rst); | |
1242 | usleep_range(10, 20); | |
1243 | reset_control_deassert(apb_rst); | |
1244 | ||
1245 | clk_disable_unprepare(dsi->pclk); | |
1246 | } | |
1247 | ||
25f0b120 CZ |
1248 | if (pdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) { |
1249 | dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg"); | |
1250 | if (IS_ERR(dsi->phy_cfg_clk)) { | |
1251 | ret = PTR_ERR(dsi->phy_cfg_clk); | |
ef6eba19 CZ |
1252 | dev_err(dev, "Unable to get phy_cfg_clk: %d\n", ret); |
1253 | return ret; | |
1254 | } | |
ef6eba19 CZ |
1255 | } |
1256 | ||
5bc07b15 CZ |
1257 | if (pdata->flags & DW_MIPI_NEEDS_GRF_CLK) { |
1258 | dsi->grf_clk = devm_clk_get(dev, "grf"); | |
1259 | if (IS_ERR(dsi->grf_clk)) { | |
1260 | ret = PTR_ERR(dsi->grf_clk); | |
1261 | dev_err(dev, "Unable to get grf_clk: %d\n", ret); | |
1262 | return ret; | |
1263 | } | |
1264 | } | |
1265 | ||
84e05408 CZ |
1266 | ret = clk_prepare_enable(dsi->pllref_clk); |
1267 | if (ret) { | |
1268 | dev_err(dev, "%s: Failed to enable pllref_clk\n", __func__); | |
1269 | return ret; | |
1270 | } | |
1271 | ||
1272 | ret = dw_mipi_dsi_register(drm, dsi); | |
1273 | if (ret) { | |
1274 | dev_err(dev, "Failed to register mipi_dsi: %d\n", ret); | |
1275 | goto err_pllref; | |
1276 | } | |
1277 | ||
84e05408 CZ |
1278 | dsi->dsi_host.ops = &dw_mipi_dsi_host_ops; |
1279 | dsi->dsi_host.dev = dev; | |
2f8f2d29 JK |
1280 | ret = mipi_dsi_host_register(&dsi->dsi_host); |
1281 | if (ret) { | |
1282 | dev_err(dev, "Failed to register MIPI host: %d\n", ret); | |
1283 | goto err_cleanup; | |
1284 | } | |
1285 | ||
1286 | if (!dsi->panel) { | |
1287 | ret = -EPROBE_DEFER; | |
1288 | goto err_mipi_dsi_host; | |
1289 | } | |
1290 | ||
1291 | dev_set_drvdata(dev, dsi); | |
517f5683 | 1292 | pm_runtime_enable(dev); |
2f8f2d29 | 1293 | return 0; |
84e05408 | 1294 | |
2f8f2d29 JK |
1295 | err_mipi_dsi_host: |
1296 | mipi_dsi_host_unregister(&dsi->dsi_host); | |
1297 | err_cleanup: | |
1298 | drm_encoder_cleanup(&dsi->encoder); | |
1299 | drm_connector_cleanup(&dsi->connector); | |
84e05408 CZ |
1300 | err_pllref: |
1301 | clk_disable_unprepare(dsi->pllref_clk); | |
1302 | return ret; | |
1303 | } | |
1304 | ||
1305 | static void dw_mipi_dsi_unbind(struct device *dev, struct device *master, | |
a432e054 | 1306 | void *data) |
84e05408 CZ |
1307 | { |
1308 | struct dw_mipi_dsi *dsi = dev_get_drvdata(dev); | |
1309 | ||
1310 | mipi_dsi_host_unregister(&dsi->dsi_host); | |
80a9a059 | 1311 | pm_runtime_disable(dev); |
84e05408 CZ |
1312 | clk_disable_unprepare(dsi->pllref_clk); |
1313 | } | |
1314 | ||
1315 | static const struct component_ops dw_mipi_dsi_ops = { | |
1316 | .bind = dw_mipi_dsi_bind, | |
1317 | .unbind = dw_mipi_dsi_unbind, | |
1318 | }; | |
1319 | ||
1320 | static int dw_mipi_dsi_probe(struct platform_device *pdev) | |
1321 | { | |
1322 | return component_add(&pdev->dev, &dw_mipi_dsi_ops); | |
1323 | } | |
1324 | ||
1325 | static int dw_mipi_dsi_remove(struct platform_device *pdev) | |
1326 | { | |
1327 | component_del(&pdev->dev, &dw_mipi_dsi_ops); | |
1328 | return 0; | |
1329 | } | |
1330 | ||
8820b68b | 1331 | struct platform_driver dw_mipi_dsi_driver = { |
84e05408 CZ |
1332 | .probe = dw_mipi_dsi_probe, |
1333 | .remove = dw_mipi_dsi_remove, | |
1334 | .driver = { | |
1335 | .of_match_table = dw_mipi_dsi_dt_ids, | |
1336 | .name = DRIVER_NAME, | |
1337 | }, | |
1338 | }; |