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a67719d1 MY |
1 | /* |
2 | * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd | |
3 | * Author:Mark Yao <mark.yao@rock-chips.com> | |
4 | * | |
5 | * This software is licensed under the terms of the GNU General Public | |
6 | * License version 2, as published by the Free Software Foundation, and | |
7 | * may be copied, distributed, and modified under those terms. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | */ | |
14 | ||
15 | #ifndef _ROCKCHIP_VOP_REG_H | |
16 | #define _ROCKCHIP_VOP_REG_H | |
17 | ||
f7673453 MY |
18 | /* rk3288 register definition */ |
19 | #define RK3288_REG_CFG_DONE 0x0000 | |
20 | #define RK3288_VERSION_INFO 0x0004 | |
21 | #define RK3288_SYS_CTRL 0x0008 | |
22 | #define RK3288_SYS_CTRL1 0x000c | |
23 | #define RK3288_DSP_CTRL0 0x0010 | |
24 | #define RK3288_DSP_CTRL1 0x0014 | |
25 | #define RK3288_DSP_BG 0x0018 | |
26 | #define RK3288_MCU_CTRL 0x001c | |
27 | #define RK3288_INTR_CTRL0 0x0020 | |
28 | #define RK3288_INTR_CTRL1 0x0024 | |
29 | #define RK3288_WIN0_CTRL0 0x0030 | |
30 | #define RK3288_WIN0_CTRL1 0x0034 | |
31 | #define RK3288_WIN0_COLOR_KEY 0x0038 | |
32 | #define RK3288_WIN0_VIR 0x003c | |
33 | #define RK3288_WIN0_YRGB_MST 0x0040 | |
34 | #define RK3288_WIN0_CBR_MST 0x0044 | |
35 | #define RK3288_WIN0_ACT_INFO 0x0048 | |
36 | #define RK3288_WIN0_DSP_INFO 0x004c | |
37 | #define RK3288_WIN0_DSP_ST 0x0050 | |
38 | #define RK3288_WIN0_SCL_FACTOR_YRGB 0x0054 | |
39 | #define RK3288_WIN0_SCL_FACTOR_CBR 0x0058 | |
40 | #define RK3288_WIN0_SCL_OFFSET 0x005c | |
41 | #define RK3288_WIN0_SRC_ALPHA_CTRL 0x0060 | |
42 | #define RK3288_WIN0_DST_ALPHA_CTRL 0x0064 | |
43 | #define RK3288_WIN0_FADING_CTRL 0x0068 | |
eb5cb6aa | 44 | #define RK3288_WIN0_CTRL2 0x006c |
f7673453 | 45 | |
a67719d1 | 46 | /* win1 register */ |
f7673453 MY |
47 | #define RK3288_WIN1_CTRL0 0x0070 |
48 | #define RK3288_WIN1_CTRL1 0x0074 | |
49 | #define RK3288_WIN1_COLOR_KEY 0x0078 | |
50 | #define RK3288_WIN1_VIR 0x007c | |
51 | #define RK3288_WIN1_YRGB_MST 0x0080 | |
52 | #define RK3288_WIN1_CBR_MST 0x0084 | |
53 | #define RK3288_WIN1_ACT_INFO 0x0088 | |
54 | #define RK3288_WIN1_DSP_INFO 0x008c | |
55 | #define RK3288_WIN1_DSP_ST 0x0090 | |
56 | #define RK3288_WIN1_SCL_FACTOR_YRGB 0x0094 | |
57 | #define RK3288_WIN1_SCL_FACTOR_CBR 0x0098 | |
58 | #define RK3288_WIN1_SCL_OFFSET 0x009c | |
59 | #define RK3288_WIN1_SRC_ALPHA_CTRL 0x00a0 | |
60 | #define RK3288_WIN1_DST_ALPHA_CTRL 0x00a4 | |
61 | #define RK3288_WIN1_FADING_CTRL 0x00a8 | |
a67719d1 | 62 | /* win2 register */ |
f7673453 MY |
63 | #define RK3288_WIN2_CTRL0 0x00b0 |
64 | #define RK3288_WIN2_CTRL1 0x00b4 | |
65 | #define RK3288_WIN2_VIR0_1 0x00b8 | |
66 | #define RK3288_WIN2_VIR2_3 0x00bc | |
67 | #define RK3288_WIN2_MST0 0x00c0 | |
68 | #define RK3288_WIN2_DSP_INFO0 0x00c4 | |
69 | #define RK3288_WIN2_DSP_ST0 0x00c8 | |
70 | #define RK3288_WIN2_COLOR_KEY 0x00cc | |
71 | #define RK3288_WIN2_MST1 0x00d0 | |
72 | #define RK3288_WIN2_DSP_INFO1 0x00d4 | |
73 | #define RK3288_WIN2_DSP_ST1 0x00d8 | |
74 | #define RK3288_WIN2_SRC_ALPHA_CTRL 0x00dc | |
75 | #define RK3288_WIN2_MST2 0x00e0 | |
76 | #define RK3288_WIN2_DSP_INFO2 0x00e4 | |
77 | #define RK3288_WIN2_DSP_ST2 0x00e8 | |
78 | #define RK3288_WIN2_DST_ALPHA_CTRL 0x00ec | |
79 | #define RK3288_WIN2_MST3 0x00f0 | |
80 | #define RK3288_WIN2_DSP_INFO3 0x00f4 | |
81 | #define RK3288_WIN2_DSP_ST3 0x00f8 | |
82 | #define RK3288_WIN2_FADING_CTRL 0x00fc | |
a67719d1 | 83 | /* win3 register */ |
f7673453 MY |
84 | #define RK3288_WIN3_CTRL0 0x0100 |
85 | #define RK3288_WIN3_CTRL1 0x0104 | |
86 | #define RK3288_WIN3_VIR0_1 0x0108 | |
87 | #define RK3288_WIN3_VIR2_3 0x010c | |
88 | #define RK3288_WIN3_MST0 0x0110 | |
89 | #define RK3288_WIN3_DSP_INFO0 0x0114 | |
90 | #define RK3288_WIN3_DSP_ST0 0x0118 | |
91 | #define RK3288_WIN3_COLOR_KEY 0x011c | |
92 | #define RK3288_WIN3_MST1 0x0120 | |
93 | #define RK3288_WIN3_DSP_INFO1 0x0124 | |
94 | #define RK3288_WIN3_DSP_ST1 0x0128 | |
95 | #define RK3288_WIN3_SRC_ALPHA_CTRL 0x012c | |
96 | #define RK3288_WIN3_MST2 0x0130 | |
97 | #define RK3288_WIN3_DSP_INFO2 0x0134 | |
98 | #define RK3288_WIN3_DSP_ST2 0x0138 | |
99 | #define RK3288_WIN3_DST_ALPHA_CTRL 0x013c | |
100 | #define RK3288_WIN3_MST3 0x0140 | |
101 | #define RK3288_WIN3_DSP_INFO3 0x0144 | |
102 | #define RK3288_WIN3_DSP_ST3 0x0148 | |
103 | #define RK3288_WIN3_FADING_CTRL 0x014c | |
a67719d1 | 104 | /* hwc register */ |
f7673453 MY |
105 | #define RK3288_HWC_CTRL0 0x0150 |
106 | #define RK3288_HWC_CTRL1 0x0154 | |
107 | #define RK3288_HWC_MST 0x0158 | |
108 | #define RK3288_HWC_DSP_ST 0x015c | |
109 | #define RK3288_HWC_SRC_ALPHA_CTRL 0x0160 | |
110 | #define RK3288_HWC_DST_ALPHA_CTRL 0x0164 | |
111 | #define RK3288_HWC_FADING_CTRL 0x0168 | |
a67719d1 | 112 | /* post process register */ |
f7673453 MY |
113 | #define RK3288_POST_DSP_HACT_INFO 0x0170 |
114 | #define RK3288_POST_DSP_VACT_INFO 0x0174 | |
115 | #define RK3288_POST_SCL_FACTOR_YRGB 0x0178 | |
116 | #define RK3288_POST_SCL_CTRL 0x0180 | |
117 | #define RK3288_POST_DSP_VACT_INFO_F1 0x0184 | |
118 | #define RK3288_DSP_HTOTAL_HS_END 0x0188 | |
119 | #define RK3288_DSP_HACT_ST_END 0x018c | |
120 | #define RK3288_DSP_VTOTAL_VS_END 0x0190 | |
121 | #define RK3288_DSP_VACT_ST_END 0x0194 | |
122 | #define RK3288_DSP_VS_ST_END_F1 0x0198 | |
123 | #define RK3288_DSP_VACT_ST_END_F1 0x019c | |
a67719d1 MY |
124 | /* register definition end */ |
125 | ||
eb5cb6aa MY |
126 | /* rk3368 register definition */ |
127 | #define RK3368_REG_CFG_DONE 0x0000 | |
128 | #define RK3368_VERSION_INFO 0x0004 | |
129 | #define RK3368_SYS_CTRL 0x0008 | |
130 | #define RK3368_SYS_CTRL1 0x000c | |
131 | #define RK3368_DSP_CTRL0 0x0010 | |
132 | #define RK3368_DSP_CTRL1 0x0014 | |
133 | #define RK3368_DSP_BG 0x0018 | |
134 | #define RK3368_MCU_CTRL 0x001c | |
135 | #define RK3368_LINE_FLAG 0x0020 | |
136 | #define RK3368_INTR_EN 0x0024 | |
137 | #define RK3368_INTR_CLEAR 0x0028 | |
138 | #define RK3368_INTR_STATUS 0x002c | |
139 | #define RK3368_WIN0_CTRL0 0x0030 | |
140 | #define RK3368_WIN0_CTRL1 0x0034 | |
141 | #define RK3368_WIN0_COLOR_KEY 0x0038 | |
142 | #define RK3368_WIN0_VIR 0x003c | |
143 | #define RK3368_WIN0_YRGB_MST 0x0040 | |
144 | #define RK3368_WIN0_CBR_MST 0x0044 | |
145 | #define RK3368_WIN0_ACT_INFO 0x0048 | |
146 | #define RK3368_WIN0_DSP_INFO 0x004c | |
147 | #define RK3368_WIN0_DSP_ST 0x0050 | |
148 | #define RK3368_WIN0_SCL_FACTOR_YRGB 0x0054 | |
149 | #define RK3368_WIN0_SCL_FACTOR_CBR 0x0058 | |
150 | #define RK3368_WIN0_SCL_OFFSET 0x005c | |
151 | #define RK3368_WIN0_SRC_ALPHA_CTRL 0x0060 | |
152 | #define RK3368_WIN0_DST_ALPHA_CTRL 0x0064 | |
153 | #define RK3368_WIN0_FADING_CTRL 0x0068 | |
154 | #define RK3368_WIN0_CTRL2 0x006c | |
155 | #define RK3368_WIN1_CTRL0 0x0070 | |
156 | #define RK3368_WIN1_CTRL1 0x0074 | |
157 | #define RK3368_WIN1_COLOR_KEY 0x0078 | |
158 | #define RK3368_WIN1_VIR 0x007c | |
159 | #define RK3368_WIN1_YRGB_MST 0x0080 | |
160 | #define RK3368_WIN1_CBR_MST 0x0084 | |
161 | #define RK3368_WIN1_ACT_INFO 0x0088 | |
162 | #define RK3368_WIN1_DSP_INFO 0x008c | |
163 | #define RK3368_WIN1_DSP_ST 0x0090 | |
164 | #define RK3368_WIN1_SCL_FACTOR_YRGB 0x0094 | |
165 | #define RK3368_WIN1_SCL_FACTOR_CBR 0x0098 | |
166 | #define RK3368_WIN1_SCL_OFFSET 0x009c | |
167 | #define RK3368_WIN1_SRC_ALPHA_CTRL 0x00a0 | |
168 | #define RK3368_WIN1_DST_ALPHA_CTRL 0x00a4 | |
169 | #define RK3368_WIN1_FADING_CTRL 0x00a8 | |
170 | #define RK3368_WIN1_CTRL2 0x00ac | |
171 | #define RK3368_WIN2_CTRL0 0x00b0 | |
172 | #define RK3368_WIN2_CTRL1 0x00b4 | |
173 | #define RK3368_WIN2_VIR0_1 0x00b8 | |
174 | #define RK3368_WIN2_VIR2_3 0x00bc | |
175 | #define RK3368_WIN2_MST0 0x00c0 | |
176 | #define RK3368_WIN2_DSP_INFO0 0x00c4 | |
177 | #define RK3368_WIN2_DSP_ST0 0x00c8 | |
178 | #define RK3368_WIN2_COLOR_KEY 0x00cc | |
179 | #define RK3368_WIN2_MST1 0x00d0 | |
180 | #define RK3368_WIN2_DSP_INFO1 0x00d4 | |
181 | #define RK3368_WIN2_DSP_ST1 0x00d8 | |
182 | #define RK3368_WIN2_SRC_ALPHA_CTRL 0x00dc | |
183 | #define RK3368_WIN2_MST2 0x00e0 | |
184 | #define RK3368_WIN2_DSP_INFO2 0x00e4 | |
185 | #define RK3368_WIN2_DSP_ST2 0x00e8 | |
186 | #define RK3368_WIN2_DST_ALPHA_CTRL 0x00ec | |
187 | #define RK3368_WIN2_MST3 0x00f0 | |
188 | #define RK3368_WIN2_DSP_INFO3 0x00f4 | |
189 | #define RK3368_WIN2_DSP_ST3 0x00f8 | |
190 | #define RK3368_WIN2_FADING_CTRL 0x00fc | |
191 | #define RK3368_WIN3_CTRL0 0x0100 | |
192 | #define RK3368_WIN3_CTRL1 0x0104 | |
193 | #define RK3368_WIN3_VIR0_1 0x0108 | |
194 | #define RK3368_WIN3_VIR2_3 0x010c | |
195 | #define RK3368_WIN3_MST0 0x0110 | |
196 | #define RK3368_WIN3_DSP_INFO0 0x0114 | |
197 | #define RK3368_WIN3_DSP_ST0 0x0118 | |
198 | #define RK3368_WIN3_COLOR_KEY 0x011c | |
199 | #define RK3368_WIN3_MST1 0x0120 | |
200 | #define RK3368_WIN3_DSP_INFO1 0x0124 | |
201 | #define RK3368_WIN3_DSP_ST1 0x0128 | |
202 | #define RK3368_WIN3_SRC_ALPHA_CTRL 0x012c | |
203 | #define RK3368_WIN3_MST2 0x0130 | |
204 | #define RK3368_WIN3_DSP_INFO2 0x0134 | |
205 | #define RK3368_WIN3_DSP_ST2 0x0138 | |
206 | #define RK3368_WIN3_DST_ALPHA_CTRL 0x013c | |
207 | #define RK3368_WIN3_MST3 0x0140 | |
208 | #define RK3368_WIN3_DSP_INFO3 0x0144 | |
209 | #define RK3368_WIN3_DSP_ST3 0x0148 | |
210 | #define RK3368_WIN3_FADING_CTRL 0x014c | |
211 | #define RK3368_HWC_CTRL0 0x0150 | |
212 | #define RK3368_HWC_CTRL1 0x0154 | |
213 | #define RK3368_HWC_MST 0x0158 | |
214 | #define RK3368_HWC_DSP_ST 0x015c | |
215 | #define RK3368_HWC_SRC_ALPHA_CTRL 0x0160 | |
216 | #define RK3368_HWC_DST_ALPHA_CTRL 0x0164 | |
217 | #define RK3368_HWC_FADING_CTRL 0x0168 | |
218 | #define RK3368_HWC_RESERVED1 0x016c | |
219 | #define RK3368_POST_DSP_HACT_INFO 0x0170 | |
220 | #define RK3368_POST_DSP_VACT_INFO 0x0174 | |
221 | #define RK3368_POST_SCL_FACTOR_YRGB 0x0178 | |
222 | #define RK3368_POST_RESERVED 0x017c | |
223 | #define RK3368_POST_SCL_CTRL 0x0180 | |
224 | #define RK3368_POST_DSP_VACT_INFO_F1 0x0184 | |
225 | #define RK3368_DSP_HTOTAL_HS_END 0x0188 | |
226 | #define RK3368_DSP_HACT_ST_END 0x018c | |
227 | #define RK3368_DSP_VTOTAL_VS_END 0x0190 | |
228 | #define RK3368_DSP_VACT_ST_END 0x0194 | |
229 | #define RK3368_DSP_VS_ST_END_F1 0x0198 | |
230 | #define RK3368_DSP_VACT_ST_END_F1 0x019c | |
231 | #define RK3368_PWM_CTRL 0x01a0 | |
232 | #define RK3368_PWM_PERIOD_HPR 0x01a4 | |
233 | #define RK3368_PWM_DUTY_LPR 0x01a8 | |
234 | #define RK3368_PWM_CNT 0x01ac | |
235 | #define RK3368_BCSH_COLOR_BAR 0x01b0 | |
236 | #define RK3368_BCSH_BCS 0x01b4 | |
237 | #define RK3368_BCSH_H 0x01b8 | |
238 | #define RK3368_BCSH_CTRL 0x01bc | |
239 | #define RK3368_CABC_CTRL0 0x01c0 | |
240 | #define RK3368_CABC_CTRL1 0x01c4 | |
241 | #define RK3368_CABC_CTRL2 0x01c8 | |
242 | #define RK3368_CABC_CTRL3 0x01cc | |
243 | #define RK3368_CABC_GAUSS_LINE0_0 0x01d0 | |
244 | #define RK3368_CABC_GAUSS_LINE0_1 0x01d4 | |
245 | #define RK3368_CABC_GAUSS_LINE1_0 0x01d8 | |
246 | #define RK3368_CABC_GAUSS_LINE1_1 0x01dc | |
247 | #define RK3368_CABC_GAUSS_LINE2_0 0x01e0 | |
248 | #define RK3368_CABC_GAUSS_LINE2_1 0x01e4 | |
249 | #define RK3368_FRC_LOWER01_0 0x01e8 | |
250 | #define RK3368_FRC_LOWER01_1 0x01ec | |
251 | #define RK3368_FRC_LOWER10_0 0x01f0 | |
252 | #define RK3368_FRC_LOWER10_1 0x01f4 | |
253 | #define RK3368_FRC_LOWER11_0 0x01f8 | |
254 | #define RK3368_FRC_LOWER11_1 0x01fc | |
255 | #define RK3368_IFBDC_CTRL 0x0200 | |
256 | #define RK3368_IFBDC_TILES_NUM 0x0204 | |
257 | #define RK3368_IFBDC_FRAME_RST_CYCLE 0x0208 | |
258 | #define RK3368_IFBDC_BASE_ADDR 0x020c | |
259 | #define RK3368_IFBDC_MB_SIZE 0x0210 | |
260 | #define RK3368_IFBDC_CMP_INDEX_INIT 0x0214 | |
261 | #define RK3368_IFBDC_VIR 0x0220 | |
262 | #define RK3368_IFBDC_DEBUG0 0x0230 | |
263 | #define RK3368_IFBDC_DEBUG1 0x0234 | |
264 | #define RK3368_LATENCY_CTRL0 0x0250 | |
265 | #define RK3368_RD_MAX_LATENCY_NUM0 0x0254 | |
266 | #define RK3368_RD_LATENCY_THR_NUM0 0x0258 | |
267 | #define RK3368_RD_LATENCY_SAMP_NUM0 0x025c | |
268 | #define RK3368_WIN0_DSP_BG 0x0260 | |
269 | #define RK3368_WIN1_DSP_BG 0x0264 | |
270 | #define RK3368_WIN2_DSP_BG 0x0268 | |
271 | #define RK3368_WIN3_DSP_BG 0x026c | |
272 | #define RK3368_SCAN_LINE_NUM 0x0270 | |
273 | #define RK3368_CABC_DEBUG0 0x0274 | |
274 | #define RK3368_CABC_DEBUG1 0x0278 | |
275 | #define RK3368_CABC_DEBUG2 0x027c | |
276 | #define RK3368_DBG_REG_000 0x0280 | |
277 | #define RK3368_DBG_REG_001 0x0284 | |
278 | #define RK3368_DBG_REG_002 0x0288 | |
279 | #define RK3368_DBG_REG_003 0x028c | |
280 | #define RK3368_DBG_REG_004 0x0290 | |
281 | #define RK3368_DBG_REG_005 0x0294 | |
282 | #define RK3368_DBG_REG_006 0x0298 | |
283 | #define RK3368_DBG_REG_007 0x029c | |
284 | #define RK3368_DBG_REG_008 0x02a0 | |
285 | #define RK3368_DBG_REG_016 0x02c0 | |
286 | #define RK3368_DBG_REG_017 0x02c4 | |
287 | #define RK3368_DBG_REG_018 0x02c8 | |
288 | #define RK3368_DBG_REG_019 0x02cc | |
289 | #define RK3368_DBG_REG_020 0x02d0 | |
290 | #define RK3368_DBG_REG_021 0x02d4 | |
291 | #define RK3368_DBG_REG_022 0x02d8 | |
292 | #define RK3368_DBG_REG_023 0x02dc | |
293 | #define RK3368_DBG_REG_028 0x02f0 | |
294 | #define RK3368_MMU_DTE_ADDR 0x0300 | |
295 | #define RK3368_MMU_STATUS 0x0304 | |
296 | #define RK3368_MMU_COMMAND 0x0308 | |
297 | #define RK3368_MMU_PAGE_FAULT_ADDR 0x030c | |
298 | #define RK3368_MMU_ZAP_ONE_LINE 0x0310 | |
299 | #define RK3368_MMU_INT_RAWSTAT 0x0314 | |
300 | #define RK3368_MMU_INT_CLEAR 0x0318 | |
301 | #define RK3368_MMU_INT_MASK 0x031c | |
302 | #define RK3368_MMU_INT_STATUS 0x0320 | |
303 | #define RK3368_MMU_AUTO_GATING 0x0324 | |
304 | #define RK3368_WIN2_LUT_ADDR 0x0400 | |
305 | #define RK3368_WIN3_LUT_ADDR 0x0800 | |
306 | #define RK3368_HWC_LUT_ADDR 0x0c00 | |
307 | #define RK3368_GAMMA_LUT_ADDR 0x1000 | |
308 | #define RK3368_CABC_GAMMA_LUT_ADDR 0x1800 | |
309 | #define RK3368_MCU_BYPASS_WPORT 0x2200 | |
310 | #define RK3368_MCU_BYPASS_RPORT 0x2300 | |
311 | /* rk3368 register definition end */ | |
312 | ||
313 | #define RK3366_REG_CFG_DONE 0x0000 | |
314 | #define RK3366_VERSION_INFO 0x0004 | |
315 | #define RK3366_SYS_CTRL 0x0008 | |
316 | #define RK3366_SYS_CTRL1 0x000c | |
317 | #define RK3366_DSP_CTRL0 0x0010 | |
318 | #define RK3366_DSP_CTRL1 0x0014 | |
319 | #define RK3366_DSP_BG 0x0018 | |
320 | #define RK3366_MCU_CTRL 0x001c | |
321 | #define RK3366_WB_CTRL0 0x0020 | |
322 | #define RK3366_WB_CTRL1 0x0024 | |
323 | #define RK3366_WB_YRGB_MST 0x0028 | |
324 | #define RK3366_WB_CBR_MST 0x002c | |
325 | #define RK3366_WIN0_CTRL0 0x0030 | |
326 | #define RK3366_WIN0_CTRL1 0x0034 | |
327 | #define RK3366_WIN0_COLOR_KEY 0x0038 | |
328 | #define RK3366_WIN0_VIR 0x003c | |
329 | #define RK3366_WIN0_YRGB_MST 0x0040 | |
330 | #define RK3366_WIN0_CBR_MST 0x0044 | |
331 | #define RK3366_WIN0_ACT_INFO 0x0048 | |
332 | #define RK3366_WIN0_DSP_INFO 0x004c | |
333 | #define RK3366_WIN0_DSP_ST 0x0050 | |
334 | #define RK3366_WIN0_SCL_FACTOR_YRGB 0x0054 | |
335 | #define RK3366_WIN0_SCL_FACTOR_CBR 0x0058 | |
336 | #define RK3366_WIN0_SCL_OFFSET 0x005c | |
337 | #define RK3366_WIN0_SRC_ALPHA_CTRL 0x0060 | |
338 | #define RK3366_WIN0_DST_ALPHA_CTRL 0x0064 | |
339 | #define RK3366_WIN0_FADING_CTRL 0x0068 | |
340 | #define RK3366_WIN0_CTRL2 0x006c | |
341 | #define RK3366_WIN1_CTRL0 0x0070 | |
342 | #define RK3366_WIN1_CTRL1 0x0074 | |
343 | #define RK3366_WIN1_COLOR_KEY 0x0078 | |
344 | #define RK3366_WIN1_VIR 0x007c | |
345 | #define RK3366_WIN1_YRGB_MST 0x0080 | |
346 | #define RK3366_WIN1_CBR_MST 0x0084 | |
347 | #define RK3366_WIN1_ACT_INFO 0x0088 | |
348 | #define RK3366_WIN1_DSP_INFO 0x008c | |
349 | #define RK3366_WIN1_DSP_ST 0x0090 | |
350 | #define RK3366_WIN1_SCL_FACTOR_YRGB 0x0094 | |
351 | #define RK3366_WIN1_SCL_FACTOR_CBR 0x0098 | |
352 | #define RK3366_WIN1_SCL_OFFSET 0x009c | |
353 | #define RK3366_WIN1_SRC_ALPHA_CTRL 0x00a0 | |
354 | #define RK3366_WIN1_DST_ALPHA_CTRL 0x00a4 | |
355 | #define RK3366_WIN1_FADING_CTRL 0x00a8 | |
356 | #define RK3366_WIN1_CTRL2 0x00ac | |
357 | #define RK3366_WIN2_CTRL0 0x00b0 | |
358 | #define RK3366_WIN2_CTRL1 0x00b4 | |
359 | #define RK3366_WIN2_VIR0_1 0x00b8 | |
360 | #define RK3366_WIN2_VIR2_3 0x00bc | |
361 | #define RK3366_WIN2_MST0 0x00c0 | |
362 | #define RK3366_WIN2_DSP_INFO0 0x00c4 | |
363 | #define RK3366_WIN2_DSP_ST0 0x00c8 | |
364 | #define RK3366_WIN2_COLOR_KEY 0x00cc | |
365 | #define RK3366_WIN2_MST1 0x00d0 | |
366 | #define RK3366_WIN2_DSP_INFO1 0x00d4 | |
367 | #define RK3366_WIN2_DSP_ST1 0x00d8 | |
368 | #define RK3366_WIN2_SRC_ALPHA_CTRL 0x00dc | |
369 | #define RK3366_WIN2_MST2 0x00e0 | |
370 | #define RK3366_WIN2_DSP_INFO2 0x00e4 | |
371 | #define RK3366_WIN2_DSP_ST2 0x00e8 | |
372 | #define RK3366_WIN2_DST_ALPHA_CTRL 0x00ec | |
373 | #define RK3366_WIN2_MST3 0x00f0 | |
374 | #define RK3366_WIN2_DSP_INFO3 0x00f4 | |
375 | #define RK3366_WIN2_DSP_ST3 0x00f8 | |
376 | #define RK3366_WIN2_FADING_CTRL 0x00fc | |
377 | #define RK3366_WIN3_CTRL0 0x0100 | |
378 | #define RK3366_WIN3_CTRL1 0x0104 | |
379 | #define RK3366_WIN3_VIR0_1 0x0108 | |
380 | #define RK3366_WIN3_VIR2_3 0x010c | |
381 | #define RK3366_WIN3_MST0 0x0110 | |
382 | #define RK3366_WIN3_DSP_INFO0 0x0114 | |
383 | #define RK3366_WIN3_DSP_ST0 0x0118 | |
384 | #define RK3366_WIN3_COLOR_KEY 0x011c | |
385 | #define RK3366_WIN3_MST1 0x0120 | |
386 | #define RK3366_WIN3_DSP_INFO1 0x0124 | |
387 | #define RK3366_WIN3_DSP_ST1 0x0128 | |
388 | #define RK3366_WIN3_SRC_ALPHA_CTRL 0x012c | |
389 | #define RK3366_WIN3_MST2 0x0130 | |
390 | #define RK3366_WIN3_DSP_INFO2 0x0134 | |
391 | #define RK3366_WIN3_DSP_ST2 0x0138 | |
392 | #define RK3366_WIN3_DST_ALPHA_CTRL 0x013c | |
393 | #define RK3366_WIN3_MST3 0x0140 | |
394 | #define RK3366_WIN3_DSP_INFO3 0x0144 | |
395 | #define RK3366_WIN3_DSP_ST3 0x0148 | |
396 | #define RK3366_WIN3_FADING_CTRL 0x014c | |
397 | #define RK3366_HWC_CTRL0 0x0150 | |
398 | #define RK3366_HWC_CTRL1 0x0154 | |
399 | #define RK3366_HWC_MST 0x0158 | |
400 | #define RK3366_HWC_DSP_ST 0x015c | |
401 | #define RK3366_HWC_SRC_ALPHA_CTRL 0x0160 | |
402 | #define RK3366_HWC_DST_ALPHA_CTRL 0x0164 | |
403 | #define RK3366_HWC_FADING_CTRL 0x0168 | |
404 | #define RK3366_HWC_RESERVED1 0x016c | |
405 | #define RK3366_POST_DSP_HACT_INFO 0x0170 | |
406 | #define RK3366_POST_DSP_VACT_INFO 0x0174 | |
407 | #define RK3366_POST_SCL_FACTOR_YRGB 0x0178 | |
408 | #define RK3366_POST_RESERVED 0x017c | |
409 | #define RK3366_POST_SCL_CTRL 0x0180 | |
410 | #define RK3366_POST_DSP_VACT_INFO_F1 0x0184 | |
411 | #define RK3366_DSP_HTOTAL_HS_END 0x0188 | |
412 | #define RK3366_DSP_HACT_ST_END 0x018c | |
413 | #define RK3366_DSP_VTOTAL_VS_END 0x0190 | |
414 | #define RK3366_DSP_VACT_ST_END 0x0194 | |
415 | #define RK3366_DSP_VS_ST_END_F1 0x0198 | |
416 | #define RK3366_DSP_VACT_ST_END_F1 0x019c | |
417 | #define RK3366_PWM_CTRL 0x01a0 | |
418 | #define RK3366_PWM_PERIOD_HPR 0x01a4 | |
419 | #define RK3366_PWM_DUTY_LPR 0x01a8 | |
420 | #define RK3366_PWM_CNT 0x01ac | |
421 | #define RK3366_BCSH_COLOR_BAR 0x01b0 | |
422 | #define RK3366_BCSH_BCS 0x01b4 | |
423 | #define RK3366_BCSH_H 0x01b8 | |
424 | #define RK3366_BCSH_CTRL 0x01bc | |
425 | #define RK3366_CABC_CTRL0 0x01c0 | |
426 | #define RK3366_CABC_CTRL1 0x01c4 | |
427 | #define RK3366_CABC_CTRL2 0x01c8 | |
428 | #define RK3366_CABC_CTRL3 0x01cc | |
429 | #define RK3366_CABC_GAUSS_LINE0_0 0x01d0 | |
430 | #define RK3366_CABC_GAUSS_LINE0_1 0x01d4 | |
431 | #define RK3366_CABC_GAUSS_LINE1_0 0x01d8 | |
432 | #define RK3366_CABC_GAUSS_LINE1_1 0x01dc | |
433 | #define RK3366_CABC_GAUSS_LINE2_0 0x01e0 | |
434 | #define RK3366_CABC_GAUSS_LINE2_1 0x01e4 | |
435 | #define RK3366_FRC_LOWER01_0 0x01e8 | |
436 | #define RK3366_FRC_LOWER01_1 0x01ec | |
437 | #define RK3366_FRC_LOWER10_0 0x01f0 | |
438 | #define RK3366_FRC_LOWER10_1 0x01f4 | |
439 | #define RK3366_FRC_LOWER11_0 0x01f8 | |
440 | #define RK3366_FRC_LOWER11_1 0x01fc | |
441 | #define RK3366_INTR_EN0 0x0280 | |
442 | #define RK3366_INTR_CLEAR0 0x0284 | |
443 | #define RK3366_INTR_STATUS0 0x0288 | |
444 | #define RK3366_INTR_RAW_STATUS0 0x028c | |
445 | #define RK3366_INTR_EN1 0x0290 | |
446 | #define RK3366_INTR_CLEAR1 0x0294 | |
447 | #define RK3366_INTR_STATUS1 0x0298 | |
448 | #define RK3366_INTR_RAW_STATUS1 0x029c | |
449 | #define RK3366_LINE_FLAG 0x02a0 | |
450 | #define RK3366_VOP_STATUS 0x02a4 | |
451 | #define RK3366_BLANKING_VALUE 0x02a8 | |
452 | #define RK3366_WIN0_DSP_BG 0x02b0 | |
453 | #define RK3366_WIN1_DSP_BG 0x02b4 | |
454 | #define RK3366_WIN2_DSP_BG 0x02b8 | |
455 | #define RK3366_WIN3_DSP_BG 0x02bc | |
456 | #define RK3366_WIN2_LUT_ADDR 0x0400 | |
457 | #define RK3366_WIN3_LUT_ADDR 0x0800 | |
458 | #define RK3366_HWC_LUT_ADDR 0x0c00 | |
459 | #define RK3366_GAMMA0_LUT_ADDR 0x1000 | |
460 | #define RK3366_GAMMA1_LUT_ADDR 0x1400 | |
461 | #define RK3366_CABC_GAMMA_LUT_ADDR 0x1800 | |
462 | #define RK3366_MCU_BYPASS_WPORT 0x2200 | |
463 | #define RK3366_MCU_BYPASS_RPORT 0x2300 | |
464 | #define RK3366_MMU_DTE_ADDR 0x2400 | |
465 | #define RK3366_MMU_STATUS 0x2404 | |
466 | #define RK3366_MMU_COMMAND 0x2408 | |
467 | #define RK3366_MMU_PAGE_FAULT_ADDR 0x240c | |
468 | #define RK3366_MMU_ZAP_ONE_LINE 0x2410 | |
469 | #define RK3366_MMU_INT_RAWSTAT 0x2414 | |
470 | #define RK3366_MMU_INT_CLEAR 0x2418 | |
471 | #define RK3366_MMU_INT_MASK 0x241c | |
472 | #define RK3366_MMU_INT_STATUS 0x2420 | |
473 | #define RK3366_MMU_AUTO_GATING 0x2424 | |
474 | ||
475 | /* rk3399 register definition */ | |
476 | #define RK3399_REG_CFG_DONE 0x0000 | |
477 | #define RK3399_VERSION_INFO 0x0004 | |
478 | #define RK3399_SYS_CTRL 0x0008 | |
479 | #define RK3399_SYS_CTRL1 0x000c | |
480 | #define RK3399_DSP_CTRL0 0x0010 | |
481 | #define RK3399_DSP_CTRL1 0x0014 | |
482 | #define RK3399_DSP_BG 0x0018 | |
483 | #define RK3399_MCU_CTRL 0x001c | |
484 | #define RK3399_WB_CTRL0 0x0020 | |
485 | #define RK3399_WB_CTRL1 0x0024 | |
486 | #define RK3399_WB_YRGB_MST 0x0028 | |
487 | #define RK3399_WB_CBR_MST 0x002c | |
488 | #define RK3399_WIN0_CTRL0 0x0030 | |
489 | #define RK3399_WIN0_CTRL1 0x0034 | |
490 | #define RK3399_WIN0_COLOR_KEY 0x0038 | |
491 | #define RK3399_WIN0_VIR 0x003c | |
492 | #define RK3399_WIN0_YRGB_MST 0x0040 | |
493 | #define RK3399_WIN0_CBR_MST 0x0044 | |
494 | #define RK3399_WIN0_ACT_INFO 0x0048 | |
495 | #define RK3399_WIN0_DSP_INFO 0x004c | |
496 | #define RK3399_WIN0_DSP_ST 0x0050 | |
497 | #define RK3399_WIN0_SCL_FACTOR_YRGB 0x0054 | |
498 | #define RK3399_WIN0_SCL_FACTOR_CBR 0x0058 | |
499 | #define RK3399_WIN0_SCL_OFFSET 0x005c | |
500 | #define RK3399_WIN0_SRC_ALPHA_CTRL 0x0060 | |
501 | #define RK3399_WIN0_DST_ALPHA_CTRL 0x0064 | |
502 | #define RK3399_WIN0_FADING_CTRL 0x0068 | |
503 | #define RK3399_WIN0_CTRL2 0x006c | |
504 | #define RK3399_WIN1_CTRL0 0x0070 | |
505 | #define RK3399_WIN1_CTRL1 0x0074 | |
506 | #define RK3399_WIN1_COLOR_KEY 0x0078 | |
507 | #define RK3399_WIN1_VIR 0x007c | |
508 | #define RK3399_WIN1_YRGB_MST 0x0080 | |
509 | #define RK3399_WIN1_CBR_MST 0x0084 | |
510 | #define RK3399_WIN1_ACT_INFO 0x0088 | |
511 | #define RK3399_WIN1_DSP_INFO 0x008c | |
512 | #define RK3399_WIN1_DSP_ST 0x0090 | |
513 | #define RK3399_WIN1_SCL_FACTOR_YRGB 0x0094 | |
514 | #define RK3399_WIN1_SCL_FACTOR_CBR 0x0098 | |
515 | #define RK3399_WIN1_SCL_OFFSET 0x009c | |
516 | #define RK3399_WIN1_SRC_ALPHA_CTRL 0x00a0 | |
517 | #define RK3399_WIN1_DST_ALPHA_CTRL 0x00a4 | |
518 | #define RK3399_WIN1_FADING_CTRL 0x00a8 | |
519 | #define RK3399_WIN1_CTRL2 0x00ac | |
520 | #define RK3399_WIN2_CTRL0 0x00b0 | |
521 | #define RK3399_WIN2_CTRL1 0x00b4 | |
522 | #define RK3399_WIN2_VIR0_1 0x00b8 | |
523 | #define RK3399_WIN2_VIR2_3 0x00bc | |
524 | #define RK3399_WIN2_MST0 0x00c0 | |
525 | #define RK3399_WIN2_DSP_INFO0 0x00c4 | |
526 | #define RK3399_WIN2_DSP_ST0 0x00c8 | |
527 | #define RK3399_WIN2_COLOR_KEY 0x00cc | |
528 | #define RK3399_WIN2_MST1 0x00d0 | |
529 | #define RK3399_WIN2_DSP_INFO1 0x00d4 | |
530 | #define RK3399_WIN2_DSP_ST1 0x00d8 | |
531 | #define RK3399_WIN2_SRC_ALPHA_CTRL 0x00dc | |
532 | #define RK3399_WIN2_MST2 0x00e0 | |
533 | #define RK3399_WIN2_DSP_INFO2 0x00e4 | |
534 | #define RK3399_WIN2_DSP_ST2 0x00e8 | |
535 | #define RK3399_WIN2_DST_ALPHA_CTRL 0x00ec | |
536 | #define RK3399_WIN2_MST3 0x00f0 | |
537 | #define RK3399_WIN2_DSP_INFO3 0x00f4 | |
538 | #define RK3399_WIN2_DSP_ST3 0x00f8 | |
539 | #define RK3399_WIN2_FADING_CTRL 0x00fc | |
540 | #define RK3399_WIN3_CTRL0 0x0100 | |
541 | #define RK3399_WIN3_CTRL1 0x0104 | |
542 | #define RK3399_WIN3_VIR0_1 0x0108 | |
543 | #define RK3399_WIN3_VIR2_3 0x010c | |
544 | #define RK3399_WIN3_MST0 0x0110 | |
545 | #define RK3399_WIN3_DSP_INFO0 0x0114 | |
546 | #define RK3399_WIN3_DSP_ST0 0x0118 | |
547 | #define RK3399_WIN3_COLOR_KEY 0x011c | |
548 | #define RK3399_WIN3_MST1 0x0120 | |
549 | #define RK3399_WIN3_DSP_INFO1 0x0124 | |
550 | #define RK3399_WIN3_DSP_ST1 0x0128 | |
551 | #define RK3399_WIN3_SRC_ALPHA_CTRL 0x012c | |
552 | #define RK3399_WIN3_MST2 0x0130 | |
553 | #define RK3399_WIN3_DSP_INFO2 0x0134 | |
554 | #define RK3399_WIN3_DSP_ST2 0x0138 | |
555 | #define RK3399_WIN3_DST_ALPHA_CTRL 0x013c | |
556 | #define RK3399_WIN3_MST3 0x0140 | |
557 | #define RK3399_WIN3_DSP_INFO3 0x0144 | |
558 | #define RK3399_WIN3_DSP_ST3 0x0148 | |
559 | #define RK3399_WIN3_FADING_CTRL 0x014c | |
560 | #define RK3399_HWC_CTRL0 0x0150 | |
561 | #define RK3399_HWC_CTRL1 0x0154 | |
562 | #define RK3399_HWC_MST 0x0158 | |
563 | #define RK3399_HWC_DSP_ST 0x015c | |
564 | #define RK3399_HWC_SRC_ALPHA_CTRL 0x0160 | |
565 | #define RK3399_HWC_DST_ALPHA_CTRL 0x0164 | |
566 | #define RK3399_HWC_FADING_CTRL 0x0168 | |
567 | #define RK3399_HWC_RESERVED1 0x016c | |
568 | #define RK3399_POST_DSP_HACT_INFO 0x0170 | |
569 | #define RK3399_POST_DSP_VACT_INFO 0x0174 | |
570 | #define RK3399_POST_SCL_FACTOR_YRGB 0x0178 | |
571 | #define RK3399_POST_RESERVED 0x017c | |
572 | #define RK3399_POST_SCL_CTRL 0x0180 | |
573 | #define RK3399_POST_DSP_VACT_INFO_F1 0x0184 | |
574 | #define RK3399_DSP_HTOTAL_HS_END 0x0188 | |
575 | #define RK3399_DSP_HACT_ST_END 0x018c | |
576 | #define RK3399_DSP_VTOTAL_VS_END 0x0190 | |
577 | #define RK3399_DSP_VACT_ST_END 0x0194 | |
578 | #define RK3399_DSP_VS_ST_END_F1 0x0198 | |
579 | #define RK3399_DSP_VACT_ST_END_F1 0x019c | |
580 | #define RK3399_PWM_CTRL 0x01a0 | |
581 | #define RK3399_PWM_PERIOD_HPR 0x01a4 | |
582 | #define RK3399_PWM_DUTY_LPR 0x01a8 | |
583 | #define RK3399_PWM_CNT 0x01ac | |
584 | #define RK3399_BCSH_COLOR_BAR 0x01b0 | |
585 | #define RK3399_BCSH_BCS 0x01b4 | |
586 | #define RK3399_BCSH_H 0x01b8 | |
587 | #define RK3399_BCSH_CTRL 0x01bc | |
588 | #define RK3399_CABC_CTRL0 0x01c0 | |
589 | #define RK3399_CABC_CTRL1 0x01c4 | |
590 | #define RK3399_CABC_CTRL2 0x01c8 | |
591 | #define RK3399_CABC_CTRL3 0x01cc | |
592 | #define RK3399_CABC_GAUSS_LINE0_0 0x01d0 | |
593 | #define RK3399_CABC_GAUSS_LINE0_1 0x01d4 | |
594 | #define RK3399_CABC_GAUSS_LINE1_0 0x01d8 | |
595 | #define RK3399_CABC_GAUSS_LINE1_1 0x01dc | |
596 | #define RK3399_CABC_GAUSS_LINE2_0 0x01e0 | |
597 | #define RK3399_CABC_GAUSS_LINE2_1 0x01e4 | |
598 | #define RK3399_FRC_LOWER01_0 0x01e8 | |
599 | #define RK3399_FRC_LOWER01_1 0x01ec | |
600 | #define RK3399_FRC_LOWER10_0 0x01f0 | |
601 | #define RK3399_FRC_LOWER10_1 0x01f4 | |
602 | #define RK3399_FRC_LOWER11_0 0x01f8 | |
603 | #define RK3399_FRC_LOWER11_1 0x01fc | |
604 | #define RK3399_AFBCD0_CTRL 0x0200 | |
605 | #define RK3399_AFBCD0_HDR_PTR 0x0204 | |
606 | #define RK3399_AFBCD0_PIC_SIZE 0x0208 | |
607 | #define RK3399_AFBCD0_STATUS 0x020c | |
608 | #define RK3399_AFBCD1_CTRL 0x0220 | |
609 | #define RK3399_AFBCD1_HDR_PTR 0x0224 | |
610 | #define RK3399_AFBCD1_PIC_SIZE 0x0228 | |
611 | #define RK3399_AFBCD1_STATUS 0x022c | |
612 | #define RK3399_AFBCD2_CTRL 0x0240 | |
613 | #define RK3399_AFBCD2_HDR_PTR 0x0244 | |
614 | #define RK3399_AFBCD2_PIC_SIZE 0x0248 | |
615 | #define RK3399_AFBCD2_STATUS 0x024c | |
616 | #define RK3399_AFBCD3_CTRL 0x0260 | |
617 | #define RK3399_AFBCD3_HDR_PTR 0x0264 | |
618 | #define RK3399_AFBCD3_PIC_SIZE 0x0268 | |
619 | #define RK3399_AFBCD3_STATUS 0x026c | |
620 | #define RK3399_INTR_EN0 0x0280 | |
621 | #define RK3399_INTR_CLEAR0 0x0284 | |
622 | #define RK3399_INTR_STATUS0 0x0288 | |
623 | #define RK3399_INTR_RAW_STATUS0 0x028c | |
624 | #define RK3399_INTR_EN1 0x0290 | |
625 | #define RK3399_INTR_CLEAR1 0x0294 | |
626 | #define RK3399_INTR_STATUS1 0x0298 | |
627 | #define RK3399_INTR_RAW_STATUS1 0x029c | |
628 | #define RK3399_LINE_FLAG 0x02a0 | |
629 | #define RK3399_VOP_STATUS 0x02a4 | |
630 | #define RK3399_BLANKING_VALUE 0x02a8 | |
631 | #define RK3399_MCU_BYPASS_PORT 0x02ac | |
632 | #define RK3399_WIN0_DSP_BG 0x02b0 | |
633 | #define RK3399_WIN1_DSP_BG 0x02b4 | |
634 | #define RK3399_WIN2_DSP_BG 0x02b8 | |
635 | #define RK3399_WIN3_DSP_BG 0x02bc | |
636 | #define RK3399_YUV2YUV_WIN 0x02c0 | |
637 | #define RK3399_YUV2YUV_POST 0x02c4 | |
638 | #define RK3399_AUTO_GATING_EN 0x02cc | |
639 | #define RK3399_WIN0_CSC_COE 0x03a0 | |
640 | #define RK3399_WIN1_CSC_COE 0x03c0 | |
641 | #define RK3399_WIN2_CSC_COE 0x03e0 | |
642 | #define RK3399_WIN3_CSC_COE 0x0400 | |
643 | #define RK3399_HWC_CSC_COE 0x0420 | |
644 | #define RK3399_BCSH_R2Y_CSC_COE 0x0440 | |
645 | #define RK3399_BCSH_Y2R_CSC_COE 0x0460 | |
646 | #define RK3399_POST_YUV2YUV_Y2R_COE 0x0480 | |
647 | #define RK3399_POST_YUV2YUV_3X3_COE 0x04a0 | |
648 | #define RK3399_POST_YUV2YUV_R2Y_COE 0x04c0 | |
649 | #define RK3399_WIN0_YUV2YUV_Y2R 0x04e0 | |
650 | #define RK3399_WIN0_YUV2YUV_3X3 0x0500 | |
651 | #define RK3399_WIN0_YUV2YUV_R2Y 0x0520 | |
652 | #define RK3399_WIN1_YUV2YUV_Y2R 0x0540 | |
653 | #define RK3399_WIN1_YUV2YUV_3X3 0x0560 | |
654 | #define RK3399_WIN1_YUV2YUV_R2Y 0x0580 | |
655 | #define RK3399_WIN2_YUV2YUV_Y2R 0x05a0 | |
656 | #define RK3399_WIN2_YUV2YUV_3X3 0x05c0 | |
657 | #define RK3399_WIN2_YUV2YUV_R2Y 0x05e0 | |
658 | #define RK3399_WIN3_YUV2YUV_Y2R 0x0600 | |
659 | #define RK3399_WIN3_YUV2YUV_3X3 0x0620 | |
660 | #define RK3399_WIN3_YUV2YUV_R2Y 0x0640 | |
661 | #define RK3399_WIN2_LUT_ADDR 0x1000 | |
662 | #define RK3399_WIN3_LUT_ADDR 0x1400 | |
663 | #define RK3399_HWC_LUT_ADDR 0x1800 | |
664 | #define RK3399_CABC_GAMMA_LUT_ADDR 0x1c00 | |
665 | #define RK3399_GAMMA_LUT_ADDR 0x2000 | |
666 | /* rk3399 register definition end */ | |
667 | ||
668 | /* rk3328 register definition end */ | |
669 | #define RK3328_REG_CFG_DONE 0x00000000 | |
670 | #define RK3328_VERSION_INFO 0x00000004 | |
671 | #define RK3328_SYS_CTRL 0x00000008 | |
672 | #define RK3328_SYS_CTRL1 0x0000000c | |
673 | #define RK3328_DSP_CTRL0 0x00000010 | |
674 | #define RK3328_DSP_CTRL1 0x00000014 | |
675 | #define RK3328_DSP_BG 0x00000018 | |
676 | #define RK3328_AUTO_GATING_EN 0x0000003c | |
677 | #define RK3328_LINE_FLAG 0x00000040 | |
678 | #define RK3328_VOP_STATUS 0x00000044 | |
679 | #define RK3328_BLANKING_VALUE 0x00000048 | |
680 | #define RK3328_WIN0_DSP_BG 0x00000050 | |
681 | #define RK3328_WIN1_DSP_BG 0x00000054 | |
682 | #define RK3328_DBG_PERF_LATENCY_CTRL0 0x000000c0 | |
683 | #define RK3328_DBG_PERF_RD_MAX_LATENCY_NUM0 0x000000c4 | |
684 | #define RK3328_DBG_PERF_RD_LATENCY_THR_NUM0 0x000000c8 | |
685 | #define RK3328_DBG_PERF_RD_LATENCY_SAMP_NUM0 0x000000cc | |
686 | #define RK3328_INTR_EN0 0x000000e0 | |
687 | #define RK3328_INTR_CLEAR0 0x000000e4 | |
688 | #define RK3328_INTR_STATUS0 0x000000e8 | |
689 | #define RK3328_INTR_RAW_STATUS0 0x000000ec | |
690 | #define RK3328_INTR_EN1 0x000000f0 | |
691 | #define RK3328_INTR_CLEAR1 0x000000f4 | |
692 | #define RK3328_INTR_STATUS1 0x000000f8 | |
693 | #define RK3328_INTR_RAW_STATUS1 0x000000fc | |
694 | #define RK3328_WIN0_CTRL0 0x00000100 | |
695 | #define RK3328_WIN0_CTRL1 0x00000104 | |
696 | #define RK3328_WIN0_COLOR_KEY 0x00000108 | |
697 | #define RK3328_WIN0_VIR 0x0000010c | |
698 | #define RK3328_WIN0_YRGB_MST 0x00000110 | |
699 | #define RK3328_WIN0_CBR_MST 0x00000114 | |
700 | #define RK3328_WIN0_ACT_INFO 0x00000118 | |
701 | #define RK3328_WIN0_DSP_INFO 0x0000011c | |
702 | #define RK3328_WIN0_DSP_ST 0x00000120 | |
703 | #define RK3328_WIN0_SCL_FACTOR_YRGB 0x00000124 | |
704 | #define RK3328_WIN0_SCL_FACTOR_CBR 0x00000128 | |
705 | #define RK3328_WIN0_SCL_OFFSET 0x0000012c | |
706 | #define RK3328_WIN0_SRC_ALPHA_CTRL 0x00000130 | |
707 | #define RK3328_WIN0_DST_ALPHA_CTRL 0x00000134 | |
708 | #define RK3328_WIN0_FADING_CTRL 0x00000138 | |
709 | #define RK3328_WIN0_CTRL2 0x0000013c | |
710 | #define RK3328_DBG_WIN0_REG0 0x000001f0 | |
711 | #define RK3328_DBG_WIN0_REG1 0x000001f4 | |
712 | #define RK3328_DBG_WIN0_REG2 0x000001f8 | |
713 | #define RK3328_DBG_WIN0_RESERVED 0x000001fc | |
714 | #define RK3328_WIN1_CTRL0 0x00000200 | |
715 | #define RK3328_WIN1_CTRL1 0x00000204 | |
716 | #define RK3328_WIN1_COLOR_KEY 0x00000208 | |
717 | #define RK3328_WIN1_VIR 0x0000020c | |
718 | #define RK3328_WIN1_YRGB_MST 0x00000210 | |
719 | #define RK3328_WIN1_CBR_MST 0x00000214 | |
720 | #define RK3328_WIN1_ACT_INFO 0x00000218 | |
721 | #define RK3328_WIN1_DSP_INFO 0x0000021c | |
722 | #define RK3328_WIN1_DSP_ST 0x00000220 | |
723 | #define RK3328_WIN1_SCL_FACTOR_YRGB 0x00000224 | |
724 | #define RK3328_WIN1_SCL_FACTOR_CBR 0x00000228 | |
725 | #define RK3328_WIN1_SCL_OFFSET 0x0000022c | |
726 | #define RK3328_WIN1_SRC_ALPHA_CTRL 0x00000230 | |
727 | #define RK3328_WIN1_DST_ALPHA_CTRL 0x00000234 | |
728 | #define RK3328_WIN1_FADING_CTRL 0x00000238 | |
729 | #define RK3328_WIN1_CTRL2 0x0000023c | |
730 | #define RK3328_DBG_WIN1_REG0 0x000002f0 | |
731 | #define RK3328_DBG_WIN1_REG1 0x000002f4 | |
732 | #define RK3328_DBG_WIN1_REG2 0x000002f8 | |
733 | #define RK3328_DBG_WIN1_RESERVED 0x000002fc | |
734 | #define RK3328_WIN2_CTRL0 0x00000300 | |
735 | #define RK3328_WIN2_CTRL1 0x00000304 | |
736 | #define RK3328_WIN2_COLOR_KEY 0x00000308 | |
737 | #define RK3328_WIN2_VIR 0x0000030c | |
738 | #define RK3328_WIN2_YRGB_MST 0x00000310 | |
739 | #define RK3328_WIN2_CBR_MST 0x00000314 | |
740 | #define RK3328_WIN2_ACT_INFO 0x00000318 | |
741 | #define RK3328_WIN2_DSP_INFO 0x0000031c | |
742 | #define RK3328_WIN2_DSP_ST 0x00000320 | |
743 | #define RK3328_WIN2_SCL_FACTOR_YRGB 0x00000324 | |
744 | #define RK3328_WIN2_SCL_FACTOR_CBR 0x00000328 | |
745 | #define RK3328_WIN2_SCL_OFFSET 0x0000032c | |
746 | #define RK3328_WIN2_SRC_ALPHA_CTRL 0x00000330 | |
747 | #define RK3328_WIN2_DST_ALPHA_CTRL 0x00000334 | |
748 | #define RK3328_WIN2_FADING_CTRL 0x00000338 | |
749 | #define RK3328_WIN2_CTRL2 0x0000033c | |
750 | #define RK3328_DBG_WIN2_REG0 0x000003f0 | |
751 | #define RK3328_DBG_WIN2_REG1 0x000003f4 | |
752 | #define RK3328_DBG_WIN2_REG2 0x000003f8 | |
753 | #define RK3328_DBG_WIN2_RESERVED 0x000003fc | |
754 | #define RK3328_WIN3_CTRL0 0x00000400 | |
755 | #define RK3328_WIN3_CTRL1 0x00000404 | |
756 | #define RK3328_WIN3_COLOR_KEY 0x00000408 | |
757 | #define RK3328_WIN3_VIR 0x0000040c | |
758 | #define RK3328_WIN3_YRGB_MST 0x00000410 | |
759 | #define RK3328_WIN3_CBR_MST 0x00000414 | |
760 | #define RK3328_WIN3_ACT_INFO 0x00000418 | |
761 | #define RK3328_WIN3_DSP_INFO 0x0000041c | |
762 | #define RK3328_WIN3_DSP_ST 0x00000420 | |
763 | #define RK3328_WIN3_SCL_FACTOR_YRGB 0x00000424 | |
764 | #define RK3328_WIN3_SCL_FACTOR_CBR 0x00000428 | |
765 | #define RK3328_WIN3_SCL_OFFSET 0x0000042c | |
766 | #define RK3328_WIN3_SRC_ALPHA_CTRL 0x00000430 | |
767 | #define RK3328_WIN3_DST_ALPHA_CTRL 0x00000434 | |
768 | #define RK3328_WIN3_FADING_CTRL 0x00000438 | |
769 | #define RK3328_WIN3_CTRL2 0x0000043c | |
770 | #define RK3328_DBG_WIN3_REG0 0x000004f0 | |
771 | #define RK3328_DBG_WIN3_REG1 0x000004f4 | |
772 | #define RK3328_DBG_WIN3_REG2 0x000004f8 | |
773 | #define RK3328_DBG_WIN3_RESERVED 0x000004fc | |
774 | ||
775 | #define RK3328_HWC_CTRL0 0x00000500 | |
776 | #define RK3328_HWC_CTRL1 0x00000504 | |
777 | #define RK3328_HWC_MST 0x00000508 | |
778 | #define RK3328_HWC_DSP_ST 0x0000050c | |
779 | #define RK3328_HWC_SRC_ALPHA_CTRL 0x00000510 | |
780 | #define RK3328_HWC_DST_ALPHA_CTRL 0x00000514 | |
781 | #define RK3328_HWC_FADING_CTRL 0x00000518 | |
782 | #define RK3328_HWC_RESERVED1 0x0000051c | |
783 | #define RK3328_POST_DSP_HACT_INFO 0x00000600 | |
784 | #define RK3328_POST_DSP_VACT_INFO 0x00000604 | |
785 | #define RK3328_POST_SCL_FACTOR_YRGB 0x00000608 | |
786 | #define RK3328_POST_RESERVED 0x0000060c | |
787 | #define RK3328_POST_SCL_CTRL 0x00000610 | |
788 | #define RK3328_POST_DSP_VACT_INFO_F1 0x00000614 | |
789 | #define RK3328_DSP_HTOTAL_HS_END 0x00000618 | |
790 | #define RK3328_DSP_HACT_ST_END 0x0000061c | |
791 | #define RK3328_DSP_VTOTAL_VS_END 0x00000620 | |
792 | #define RK3328_DSP_VACT_ST_END 0x00000624 | |
793 | #define RK3328_DSP_VS_ST_END_F1 0x00000628 | |
794 | #define RK3328_DSP_VACT_ST_END_F1 0x0000062c | |
795 | #define RK3328_BCSH_COLOR_BAR 0x00000640 | |
796 | #define RK3328_BCSH_BCS 0x00000644 | |
797 | #define RK3328_BCSH_H 0x00000648 | |
798 | #define RK3328_BCSH_CTRL 0x0000064c | |
799 | #define RK3328_FRC_LOWER01_0 0x00000678 | |
800 | #define RK3328_FRC_LOWER01_1 0x0000067c | |
801 | #define RK3328_FRC_LOWER10_0 0x00000680 | |
802 | #define RK3328_FRC_LOWER10_1 0x00000684 | |
803 | #define RK3328_FRC_LOWER11_0 0x00000688 | |
804 | #define RK3328_FRC_LOWER11_1 0x0000068c | |
805 | #define RK3328_DBG_POST_REG0 0x000006e8 | |
806 | #define RK3328_DBG_POST_RESERVED 0x000006ec | |
807 | #define RK3328_DBG_DATAO 0x000006f0 | |
808 | #define RK3328_DBG_DATAO_2 0x000006f4 | |
809 | ||
810 | /* sdr to hdr */ | |
811 | #define RK3328_SDR2HDR_CTRL 0x00000700 | |
812 | #define RK3328_EOTF_OETF_Y0 0x00000704 | |
813 | #define RK3328_RESERVED0001 0x00000708 | |
814 | #define RK3328_RESERVED0002 0x0000070c | |
815 | #define RK3328_EOTF_OETF_Y1 0x00000710 | |
816 | #define RK3328_EOTF_OETF_Y64 0x0000080c | |
817 | #define RK3328_OETF_DX_DXPOW1 0x00000810 | |
818 | #define RK3328_OETF_DX_DXPOW64 0x0000090c | |
819 | #define RK3328_OETF_XN1 0x00000910 | |
820 | #define RK3328_OETF_XN63 0x00000a08 | |
821 | ||
822 | /* hdr to sdr */ | |
823 | #define RK3328_HDR2SDR_CTRL 0x00000a10 | |
824 | #define RK3328_HDR2SDR_SRC_RANGE 0x00000a14 | |
825 | #define RK3328_HDR2SDR_NORMFACEETF 0x00000a18 | |
826 | #define RK3328_RESERVED0003 0x00000a1c | |
827 | #define RK3328_HDR2SDR_DST_RANGE 0x00000a20 | |
828 | #define RK3328_HDR2SDR_NORMFACCGAMMA 0x00000a24 | |
829 | #define RK3328_EETF_OETF_Y0 0x00000a28 | |
830 | #define RK3328_SAT_Y0 0x00000a2c | |
831 | #define RK3328_EETF_OETF_Y1 0x00000a30 | |
832 | #define RK3328_SAT_Y1 0x00000ab0 | |
833 | #define RK3328_SAT_Y8 0x00000acc | |
834 | ||
835 | #define RK3328_HWC_LUT_ADDR 0x00000c00 | |
836 | ||
f7673453 MY |
837 | /* rk3036 register definition */ |
838 | #define RK3036_SYS_CTRL 0x00 | |
839 | #define RK3036_DSP_CTRL0 0x04 | |
840 | #define RK3036_DSP_CTRL1 0x08 | |
841 | #define RK3036_INT_STATUS 0x10 | |
842 | #define RK3036_ALPHA_CTRL 0x14 | |
843 | #define RK3036_WIN0_COLOR_KEY 0x18 | |
844 | #define RK3036_WIN1_COLOR_KEY 0x1c | |
845 | #define RK3036_WIN0_YRGB_MST 0x20 | |
846 | #define RK3036_WIN0_CBR_MST 0x24 | |
847 | #define RK3036_WIN1_VIR 0x28 | |
848 | #define RK3036_AXI_BUS_CTRL 0x2c | |
849 | #define RK3036_WIN0_VIR 0x30 | |
850 | #define RK3036_WIN0_ACT_INFO 0x34 | |
851 | #define RK3036_WIN0_DSP_INFO 0x38 | |
852 | #define RK3036_WIN0_DSP_ST 0x3c | |
853 | #define RK3036_WIN0_SCL_FACTOR_YRGB 0x40 | |
854 | #define RK3036_WIN0_SCL_FACTOR_CBR 0x44 | |
855 | #define RK3036_WIN0_SCL_OFFSET 0x48 | |
856 | #define RK3036_HWC_MST 0x58 | |
857 | #define RK3036_HWC_DSP_ST 0x5c | |
858 | #define RK3036_DSP_HTOTAL_HS_END 0x6c | |
859 | #define RK3036_DSP_HACT_ST_END 0x70 | |
860 | #define RK3036_DSP_VTOTAL_VS_END 0x74 | |
861 | #define RK3036_DSP_VACT_ST_END 0x78 | |
862 | #define RK3036_DSP_VS_ST_END_F1 0x7c | |
863 | #define RK3036_DSP_VACT_ST_END_F1 0x80 | |
864 | #define RK3036_GATHER_TRANSFER 0x84 | |
865 | #define RK3036_VERSION_INFO 0x94 | |
866 | #define RK3036_REG_CFG_DONE 0x90 | |
867 | #define RK3036_WIN1_MST 0xa0 | |
868 | #define RK3036_WIN1_ACT_INFO 0xb4 | |
869 | #define RK3036_WIN1_DSP_INFO 0xb8 | |
870 | #define RK3036_WIN1_DSP_ST 0xbc | |
871 | #define RK3036_WIN1_SCL_FACTOR_YRGB 0xc0 | |
872 | #define RK3036_WIN1_SCL_OFFSET 0xc8 | |
873 | #define RK3036_BCSH_CTRL 0xd0 | |
874 | #define RK3036_BCSH_COLOR_BAR 0xd4 | |
875 | #define RK3036_BCSH_BCS 0xd8 | |
876 | #define RK3036_BCSH_H 0xdc | |
877 | #define RK3036_WIN1_LUT_ADDR 0x400 | |
878 | #define RK3036_HWC_LUT_ADDR 0x800 | |
879 | /* rk3036 register definition end */ | |
880 | ||
460c3b00 SH |
881 | /* rk3126 register definition */ |
882 | #define RK3126_WIN1_MST 0x4c | |
883 | #define RK3126_WIN1_DSP_INFO 0x50 | |
884 | #define RK3126_WIN1_DSP_ST 0x54 | |
885 | /* rk3126 register definition end */ | |
886 | ||
a67719d1 | 887 | #endif /* _ROCKCHIP_VOP_REG_H */ |