[mirror_ubuntu-bionic-kernel.git] / drivers / media / i2c / adv748x / adv748x.h

/*
 * Driver for Analog Devices ADV748X video decoder and HDMI receiver
 *
 * Copyright (C) 2017 Renesas Electronics Corp.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 * Authors:
 *	Koji Matsuoka <koji.matsuoka.xm@renesas.com>
 *	Niklas Söderlund <niklas.soderlund@ragnatech.se>
 *	Kieran Bingham <kieran.bingham@ideasonboard.com>
 *
 * The ADV748x range of receivers have the following configurations:
 *
 *                  Analog   HDMI  MHL  4-Lane  1-Lane
 *                    In      In         CSI     CSI
 *       ADV7480               X    X     X
 *       ADV7481      X        X    X     X       X
 *       ADV7482      X        X          X       X
 */

#include <linux/i2c.h>

#ifndef _ADV748X_H_
#define _ADV748X_H_

/* I2C slave addresses */
#define ADV748X_I2C_IO			0x70	/* IO Map */
#define ADV748X_I2C_DPLL		0x26	/* DPLL Map */
#define ADV748X_I2C_CP			0x22	/* CP Map */
#define ADV748X_I2C_HDMI		0x34	/* HDMI Map */
#define ADV748X_I2C_EDID		0x36	/* EDID Map */
#define ADV748X_I2C_REPEATER		0x32	/* HDMI RX Repeater Map */
#define ADV748X_I2C_INFOFRAME		0x31	/* HDMI RX InfoFrame Map */
#define ADV748X_I2C_CEC			0x41	/* CEC Map */
#define ADV748X_I2C_SDP			0x79	/* SDP Map */
#define ADV748X_I2C_TXB			0x48	/* CSI-TXB Map */
#define ADV748X_I2C_TXA			0x4a	/* CSI-TXA Map */

enum adv748x_page {
	ADV748X_PAGE_IO,
	ADV748X_PAGE_DPLL,
	ADV748X_PAGE_CP,
	ADV748X_PAGE_HDMI,
	ADV748X_PAGE_EDID,
	ADV748X_PAGE_REPEATER,
	ADV748X_PAGE_INFOFRAME,
	ADV748X_PAGE_CEC,
	ADV748X_PAGE_SDP,
	ADV748X_PAGE_TXB,
	ADV748X_PAGE_TXA,
	ADV748X_PAGE_MAX,

	/* Fake pages for register sequences */
	ADV748X_PAGE_WAIT,		/* Wait x msec */
	ADV748X_PAGE_EOR,		/* End Mark */
};

/**
 * enum adv748x_ports - Device tree port number definitions
 *
 * The ADV748X ports define the mapping between subdevices
 * and the device tree specification
 */
enum adv748x_ports {
	ADV748X_PORT_AIN0 = 0,
	ADV748X_PORT_AIN1 = 1,
	ADV748X_PORT_AIN2 = 2,
	ADV748X_PORT_AIN3 = 3,
	ADV748X_PORT_AIN4 = 4,
	ADV748X_PORT_AIN5 = 5,
	ADV748X_PORT_AIN6 = 6,
	ADV748X_PORT_AIN7 = 7,
	ADV748X_PORT_HDMI = 8,
	ADV748X_PORT_TTL = 9,
	ADV748X_PORT_TXA = 10,
	ADV748X_PORT_TXB = 11,
	ADV748X_PORT_MAX = 12,
};

enum adv748x_csi2_pads {
	ADV748X_CSI2_SINK,
	ADV748X_CSI2_SOURCE,
	ADV748X_CSI2_NR_PADS,
};

/* CSI2 transmitters can have 2 internal connections, HDMI/AFE */
#define ADV748X_CSI2_MAX_SUBDEVS 2

struct adv748x_csi2 {
	struct adv748x_state *state;
	struct v4l2_mbus_framefmt format;
	unsigned int page;
	unsigned int port;

	struct media_pad pads[ADV748X_CSI2_NR_PADS];
	struct v4l2_ctrl_handler ctrl_hdl;
	struct v4l2_subdev sd;
};

#define notifier_to_csi2(n) container_of(n, struct adv748x_csi2, notifier)
#define adv748x_sd_to_csi2(sd) container_of(sd, struct adv748x_csi2, sd)
#define is_tx_enabled(_tx) ((_tx)->state->endpoints[(_tx)->port] != NULL)

enum adv748x_hdmi_pads {
	ADV748X_HDMI_SINK,
	ADV748X_HDMI_SOURCE,
	ADV748X_HDMI_NR_PADS,
};

struct adv748x_hdmi {
	struct media_pad pads[ADV748X_HDMI_NR_PADS];
	struct v4l2_ctrl_handler ctrl_hdl;
	struct v4l2_subdev sd;
	struct v4l2_mbus_framefmt format;

	struct v4l2_dv_timings timings;
	struct v4l2_fract aspect_ratio;

	struct {
		u8 edid[512];
		u32 present;
		unsigned int blocks;
	} edid;
};

#define adv748x_ctrl_to_hdmi(ctrl) \
	container_of(ctrl->handler, struct adv748x_hdmi, ctrl_hdl)
#define adv748x_sd_to_hdmi(sd) container_of(sd, struct adv748x_hdmi, sd)

enum adv748x_afe_pads {
	ADV748X_AFE_SINK_AIN0,
	ADV748X_AFE_SINK_AIN1,
	ADV748X_AFE_SINK_AIN2,
	ADV748X_AFE_SINK_AIN3,
	ADV748X_AFE_SINK_AIN4,
	ADV748X_AFE_SINK_AIN5,
	ADV748X_AFE_SINK_AIN6,
	ADV748X_AFE_SINK_AIN7,
	ADV748X_AFE_SOURCE,
	ADV748X_AFE_NR_PADS,
};

struct adv748x_afe {
	struct media_pad pads[ADV748X_AFE_NR_PADS];
	struct v4l2_ctrl_handler ctrl_hdl;
	struct v4l2_subdev sd;
	struct v4l2_mbus_framefmt format;

	bool streaming;
	v4l2_std_id curr_norm;
	unsigned int input;
};

#define adv748x_ctrl_to_afe(ctrl) \
	container_of(ctrl->handler, struct adv748x_afe, ctrl_hdl)
#define adv748x_sd_to_afe(sd) container_of(sd, struct adv748x_afe, sd)

/**
 * struct adv748x_state - State of ADV748X
 * @dev:		(OF) device
 * @client:		I2C client
 * @mutex:		protect global state
 *
 * @endpoints:		parsed device node endpoints for each port
 *
 * @i2c_addresses	I2C Page addresses
 * @i2c_clients		I2C clients for the page accesses
 * @regmap		regmap configuration pages.
 *
 * @hdmi:		state of HDMI receiver context
 * @afe:		state of AFE receiver context
 * @txa:		state of TXA transmitter context
 * @txb:		state of TXB transmitter context
 */
struct adv748x_state {
	struct device *dev;
	struct i2c_client *client;
	struct mutex mutex;

	struct device_node *endpoints[ADV748X_PORT_MAX];

	struct i2c_client *i2c_clients[ADV748X_PAGE_MAX];
	struct regmap *regmap[ADV748X_PAGE_MAX];

	struct adv748x_hdmi hdmi;
	struct adv748x_afe afe;
	struct adv748x_csi2 txa;
	struct adv748x_csi2 txb;
};

#define adv748x_hdmi_to_state(h) container_of(h, struct adv748x_state, hdmi)
#define adv748x_afe_to_state(a) container_of(a, struct adv748x_state, afe)

#define adv_err(a, fmt, arg...)	dev_err(a->dev, fmt, ##arg)
#define adv_info(a, fmt, arg...) dev_info(a->dev, fmt, ##arg)
#define adv_dbg(a, fmt, arg...)	dev_dbg(a->dev, fmt, ##arg)

/* Register Mappings */

/* IO Map */
#define ADV748X_IO_PD			0x00	/* power down controls */
#define ADV748X_IO_PD_RX_EN		BIT(6)

#define ADV748X_IO_REG_04		0x04
#define ADV748X_IO_REG_04_FORCE_FR	BIT(0)	/* Force CP free-run */

#define ADV748X_IO_DATAPATH		0x03	/* datapath cntrl */
#define ADV748X_IO_DATAPATH_VFREQ_M	0x70
#define ADV748X_IO_DATAPATH_VFREQ_SHIFT	4

#define ADV748X_IO_VID_STD		0x05

#define ADV748X_IO_10			0x10	/* io_reg_10 */
#define ADV748X_IO_10_CSI4_EN		BIT(7)
#define ADV748X_IO_10_CSI1_EN		BIT(6)
#define ADV748X_IO_10_PIX_OUT_EN	BIT(5)

#define ADV748X_IO_CHIP_REV_ID_1	0xdf
#define ADV748X_IO_CHIP_REV_ID_2	0xe0

#define ADV748X_IO_SLAVE_ADDR_BASE	0xf2

/* HDMI RX Map */
#define ADV748X_HDMI_LW1		0x07	/* line width_1 */
#define ADV748X_HDMI_LW1_VERT_FILTER	BIT(7)
#define ADV748X_HDMI_LW1_DE_REGEN	BIT(5)
#define ADV748X_HDMI_LW1_WIDTH_MASK	0x1fff

#define ADV748X_HDMI_F0H1		0x09	/* field0 height_1 */
#define ADV748X_HDMI_F0H1_HEIGHT_MASK	0x1fff

#define ADV748X_HDMI_F1H1		0x0b	/* field1 height_1 */
#define ADV748X_HDMI_F1H1_INTERLACED	BIT(5)

#define ADV748X_HDMI_HFRONT_PORCH	0x20	/* hsync_front_porch_1 */
#define ADV748X_HDMI_HFRONT_PORCH_MASK	0x1fff

#define ADV748X_HDMI_HSYNC_WIDTH	0x22	/* hsync_pulse_width_1 */
#define ADV748X_HDMI_HSYNC_WIDTH_MASK	0x1fff

#define ADV748X_HDMI_HBACK_PORCH	0x24	/* hsync_back_porch_1 */
#define ADV748X_HDMI_HBACK_PORCH_MASK	0x1fff

#define ADV748X_HDMI_VFRONT_PORCH	0x2a	/* field0_vs_front_porch_1 */
#define ADV748X_HDMI_VFRONT_PORCH_MASK	0x3fff

#define ADV748X_HDMI_VSYNC_WIDTH	0x2e	/* field0_vs_pulse_width_1 */
#define ADV748X_HDMI_VSYNC_WIDTH_MASK	0x3fff

#define ADV748X_HDMI_VBACK_PORCH	0x32	/* field0_vs_back_porch_1 */
#define ADV748X_HDMI_VBACK_PORCH_MASK	0x3fff

#define ADV748X_HDMI_TMDS_1		0x51	/* hdmi_reg_51 */
#define ADV748X_HDMI_TMDS_2		0x52	/* hdmi_reg_52 */

/* HDMI RX Repeater Map */
#define ADV748X_REPEATER_EDID_SZ	0x70	/* primary_edid_size */
#define ADV748X_REPEATER_EDID_SZ_SHIFT	4

#define ADV748X_REPEATER_EDID_CTL	0x74	/* hdcp edid controls */
#define ADV748X_REPEATER_EDID_CTL_EN	BIT(0)	/* man_edid_a_enable */

/* SDP Main Map */
#define ADV748X_SDP_INSEL		0x00	/* user_map_rw_reg_00 */

#define ADV748X_SDP_VID_SEL		0x02	/* user_map_rw_reg_02 */
#define ADV748X_SDP_VID_SEL_MASK	0xf0
#define ADV748X_SDP_VID_SEL_SHIFT	4

/* Contrast - Unsigned*/
#define ADV748X_SDP_CON			0x08	/* user_map_rw_reg_08 */
#define ADV748X_SDP_CON_MIN		0
#define ADV748X_SDP_CON_DEF		128
#define ADV748X_SDP_CON_MAX		255

/* Brightness - Signed */
#define ADV748X_SDP_BRI			0x0a	/* user_map_rw_reg_0a */
#define ADV748X_SDP_BRI_MIN		-128
#define ADV748X_SDP_BRI_DEF		0
#define ADV748X_SDP_BRI_MAX		127

/* Hue - Signed, inverted*/
#define ADV748X_SDP_HUE			0x0b	/* user_map_rw_reg_0b */
#define ADV748X_SDP_HUE_MIN		-127
#define ADV748X_SDP_HUE_DEF		0
#define ADV748X_SDP_HUE_MAX		128

/* Test Patterns / Default Values */
#define ADV748X_SDP_DEF			0x0c	/* user_map_rw_reg_0c */
#define ADV748X_SDP_DEF_VAL_EN		BIT(0)	/* Force free run mode */
#define ADV748X_SDP_DEF_VAL_AUTO_EN	BIT(1)	/* Free run when no signal */

#define ADV748X_SDP_MAP_SEL		0x0e	/* user_map_rw_reg_0e */
#define ADV748X_SDP_MAP_SEL_RO_MAIN	1

/* Free run pattern select */
#define ADV748X_SDP_FRP			0x14
#define ADV748X_SDP_FRP_MASK		GENMASK(3, 1)

/* Saturation */
#define ADV748X_SDP_SD_SAT_U		0xe3	/* user_map_rw_reg_e3 */
#define ADV748X_SDP_SD_SAT_V		0xe4	/* user_map_rw_reg_e4 */
#define ADV748X_SDP_SAT_MIN		0
#define ADV748X_SDP_SAT_DEF		128
#define ADV748X_SDP_SAT_MAX		255

/* SDP RO Main Map */
#define ADV748X_SDP_RO_10		0x10
#define ADV748X_SDP_RO_10_IN_LOCK	BIT(0)

/* CP Map */
#define ADV748X_CP_PAT_GEN		0x37	/* int_pat_gen_1 */
#define ADV748X_CP_PAT_GEN_EN		BIT(7)

/* Contrast Control - Unsigned */
#define ADV748X_CP_CON			0x3a	/* contrast_cntrl */
#define ADV748X_CP_CON_MIN		0	/* Minimum contrast */
#define ADV748X_CP_CON_DEF		128	/* Default */
#define ADV748X_CP_CON_MAX		255	/* Maximum contrast */

/* Saturation Control - Unsigned */
#define ADV748X_CP_SAT			0x3b	/* saturation_cntrl */
#define ADV748X_CP_SAT_MIN		0	/* Minimum saturation */
#define ADV748X_CP_SAT_DEF		128	/* Default */
#define ADV748X_CP_SAT_MAX		255	/* Maximum saturation */

/* Brightness Control - Signed */
#define ADV748X_CP_BRI			0x3c	/* brightness_cntrl */
#define ADV748X_CP_BRI_MIN		-128	/* Luma is -512d */
#define ADV748X_CP_BRI_DEF		0	/* Luma is 0 */
#define ADV748X_CP_BRI_MAX		127	/* Luma is 508d */

/* Hue Control */
#define ADV748X_CP_HUE			0x3d	/* hue_cntrl */
#define ADV748X_CP_HUE_MIN		0	/* -90 degree */
#define ADV748X_CP_HUE_DEF		0	/* -90 degree */
#define ADV748X_CP_HUE_MAX		255	/* +90 degree */

#define ADV748X_CP_VID_ADJ		0x3e	/* vid_adj_0 */
#define ADV748X_CP_VID_ADJ_ENABLE	BIT(7)	/* Enable colour controls */

#define ADV748X_CP_DE_POS_HIGH		0x8b	/* de_pos_adj_6 */
#define ADV748X_CP_DE_POS_HIGH_SET	BIT(6)
#define ADV748X_CP_DE_POS_END_LOW	0x8c	/* de_pos_adj_7 */
#define ADV748X_CP_DE_POS_START_LOW	0x8d	/* de_pos_adj_8 */

#define ADV748X_CP_VID_ADJ_2			0x91
#define ADV748X_CP_VID_ADJ_2_INTERLACED		BIT(6)
#define ADV748X_CP_VID_ADJ_2_INTERLACED_3D	BIT(4)

#define ADV748X_CP_CLMP_POS		0xc9	/* clmp_pos_cntrl_4 */
#define ADV748X_CP_CLMP_POS_DIS_AUTO	BIT(0)	/* dis_auto_param_buff */

/* CSI : TXA/TXB Maps */
#define ADV748X_CSI_VC_REF		0x0d	/* csi_tx_top_reg_0d */
#define ADV748X_CSI_VC_REF_SHIFT	6

#define ADV748X_CSI_FS_AS_LS		0x1e	/* csi_tx_top_reg_1e */
#define ADV748X_CSI_FS_AS_LS_UNKNOWN	BIT(6)	/* Undocumented bit */

/* Register handling */

int adv748x_read(struct adv748x_state *state, u8 addr, u8 reg);
int adv748x_write(struct adv748x_state *state, u8 page, u8 reg, u8 value);
int adv748x_write_block(struct adv748x_state *state, int client_page,
			unsigned int init_reg, const void *val,
			size_t val_len);

#define io_read(s, r) adv748x_read(s, ADV748X_PAGE_IO, r)
#define io_write(s, r, v) adv748x_write(s, ADV748X_PAGE_IO, r, v)
#define io_clrset(s, r, m, v) io_write(s, r, (io_read(s, r) & ~(m)) | (v))

#define hdmi_read(s, r) adv748x_read(s, ADV748X_PAGE_HDMI, r)
#define hdmi_read16(s, r, m) (((hdmi_read(s, r) << 8) | hdmi_read(s, (r)+1)) & (m))
#define hdmi_write(s, r, v) adv748x_write(s, ADV748X_PAGE_HDMI, r, v)

#define repeater_read(s, r) adv748x_read(s, ADV748X_PAGE_REPEATER, r)
#define repeater_write(s, r, v) adv748x_write(s, ADV748X_PAGE_REPEATER, r, v)

#define sdp_read(s, r) adv748x_read(s, ADV748X_PAGE_SDP, r)
#define sdp_write(s, r, v) adv748x_write(s, ADV748X_PAGE_SDP, r, v)
#define sdp_clrset(s, r, m, v) sdp_write(s, r, (sdp_read(s, r) & ~(m)) | (v))

#define cp_read(s, r) adv748x_read(s, ADV748X_PAGE_CP, r)
#define cp_write(s, r, v) adv748x_write(s, ADV748X_PAGE_CP, r, v)
#define cp_clrset(s, r, m, v) cp_write(s, r, (cp_read(s, r) & ~(m)) | (v))

#define txa_read(s, r) adv748x_read(s, ADV748X_PAGE_TXA, r)
#define txb_read(s, r) adv748x_read(s, ADV748X_PAGE_TXB, r)

#define tx_read(t, r) adv748x_read(t->state, t->page, r)
#define tx_write(t, r, v) adv748x_write(t->state, t->page, r, v)

static inline struct v4l2_subdev *adv748x_get_remote_sd(struct media_pad *pad)
{
	pad = media_entity_remote_pad(pad);
	if (!pad)
		return NULL;

	return media_entity_to_v4l2_subdev(pad->entity);
}

void adv748x_subdev_init(struct v4l2_subdev *sd, struct adv748x_state *state,
			 const struct v4l2_subdev_ops *ops, u32 function,
			 const char *ident);

int adv748x_register_subdevs(struct adv748x_state *state,
			     struct v4l2_device *v4l2_dev);

int adv748x_txa_power(struct adv748x_state *state, bool on);
int adv748x_txb_power(struct adv748x_state *state, bool on);

int adv748x_afe_init(struct adv748x_afe *afe);
void adv748x_afe_cleanup(struct adv748x_afe *afe);

int adv748x_csi2_init(struct adv748x_state *state, struct adv748x_csi2 *tx);
void adv748x_csi2_cleanup(struct adv748x_csi2 *tx);
int adv748x_csi2_set_pixelrate(struct v4l2_subdev *sd, s64 rate);

int adv748x_hdmi_init(struct adv748x_hdmi *hdmi);
void adv748x_hdmi_cleanup(struct adv748x_hdmi *hdmi);

#endif /* _ADV748X_H_ */
Commit	Line	Data
3e89586a KB	1	/*
	2	* Driver for Analog Devices ADV748X video decoder and HDMI receiver
	3	*
	4	* Copyright (C) 2017 Renesas Electronics Corp.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
	10	*
	11	* Authors:
	12	* Koji Matsuoka <koji.matsuoka.xm@renesas.com>
	13	* Niklas Söderlund <niklas.soderlund@ragnatech.se>
	14	* Kieran Bingham <kieran.bingham@ideasonboard.com>
	15	*
	16	* The ADV748x range of receivers have the following configurations:
	17	*
	18	* Analog HDMI MHL 4-Lane 1-Lane
	19	* In In CSI CSI
	20	* ADV7480 X X X
	21	* ADV7481 X X X X X
	22	* ADV7482 X X X X
	23	*/
	24
	25	#include <linux/i2c.h>
	26
	27	#ifndef _ADV748X_H_
	28	#define _ADV748X_H_
	29
	30	/* I2C slave addresses */
	31	#define ADV748X_I2C_IO 0x70 /* IO Map */
	32	#define ADV748X_I2C_DPLL 0x26 /* DPLL Map */
	33	#define ADV748X_I2C_CP 0x22 /* CP Map */
	34	#define ADV748X_I2C_HDMI 0x34 /* HDMI Map */
	35	#define ADV748X_I2C_EDID 0x36 /* EDID Map */
	36	#define ADV748X_I2C_REPEATER 0x32 /* HDMI RX Repeater Map */
	37	#define ADV748X_I2C_INFOFRAME 0x31 /* HDMI RX InfoFrame Map */
	38	#define ADV748X_I2C_CEC 0x41 /* CEC Map */
	39	#define ADV748X_I2C_SDP 0x79 /* SDP Map */
	40	#define ADV748X_I2C_TXB 0x48 /* CSI-TXB Map */
	41	#define ADV748X_I2C_TXA 0x4a /* CSI-TXA Map */
	42
	43	enum adv748x_page {
	44	ADV748X_PAGE_IO,
	45	ADV748X_PAGE_DPLL,
	46	ADV748X_PAGE_CP,
	47	ADV748X_PAGE_HDMI,
	48	ADV748X_PAGE_EDID,
	49	ADV748X_PAGE_REPEATER,
	50	ADV748X_PAGE_INFOFRAME,
	51	ADV748X_PAGE_CEC,
	52	ADV748X_PAGE_SDP,
	53	ADV748X_PAGE_TXB,
	54	ADV748X_PAGE_TXA,
	55	ADV748X_PAGE_MAX,
	56
	57	/* Fake pages for register sequences */
	58	ADV748X_PAGE_WAIT, /* Wait x msec */
	59	ADV748X_PAGE_EOR, /* End Mark */
	60	};
	61
	62	/**
	63	* enum adv748x_ports - Device tree port number definitions
	64	*
65	* The ADV748X ports define the mapping between subdevices
66	* and the device tree specification
67	*/
68	enum adv748x_ports {
69	ADV748X_PORT_AIN0 = 0,
70	ADV748X_PORT_AIN1 = 1,
71	ADV748X_PORT_AIN2 = 2,
72	ADV748X_PORT_AIN3 = 3,
73	ADV748X_PORT_AIN4 = 4,
74	ADV748X_PORT_AIN5 = 5,
75	ADV748X_PORT_AIN6 = 6,
76	ADV748X_PORT_AIN7 = 7,
77	ADV748X_PORT_HDMI = 8,
78	ADV748X_PORT_TTL = 9,
79	ADV748X_PORT_TXA = 10,
80	ADV748X_PORT_TXB = 11,
81	ADV748X_PORT_MAX = 12,
82	};
83
84	enum adv748x_csi2_pads {
85	ADV748X_CSI2_SINK,
86	ADV748X_CSI2_SOURCE,
87	ADV748X_CSI2_NR_PADS,
88	};
89
90	/* CSI2 transmitters can have 2 internal connections, HDMI/AFE */
91	#define ADV748X_CSI2_MAX_SUBDEVS 2
92
93	struct adv748x_csi2 {
94	struct adv748x_state *state;
95	struct v4l2_mbus_framefmt format;
96	unsigned int page;
ea3f013d	97	unsigned int port;
3e89586a KB	98
	99	struct media_pad pads[ADV748X_CSI2_NR_PADS];
	100	struct v4l2_ctrl_handler ctrl_hdl;
	101	struct v4l2_subdev sd;
	102	};
	103
	104	#define notifier_to_csi2(n) container_of(n, struct adv748x_csi2, notifier)
	105	#define adv748x_sd_to_csi2(sd) container_of(sd, struct adv748x_csi2, sd)
ea3f013d	106	#define is_tx_enabled(_tx) ((_tx)->state->endpoints[(_tx)->port] != NULL)
3e89586a KB	107
	108	enum adv748x_hdmi_pads {
	109	ADV748X_HDMI_SINK,
	110	ADV748X_HDMI_SOURCE,
	111	ADV748X_HDMI_NR_PADS,
	112	};
	113
	114	struct adv748x_hdmi {
	115	struct media_pad pads[ADV748X_HDMI_NR_PADS];
	116	struct v4l2_ctrl_handler ctrl_hdl;
	117	struct v4l2_subdev sd;
	118	struct v4l2_mbus_framefmt format;
	119
	120	struct v4l2_dv_timings timings;
	121	struct v4l2_fract aspect_ratio;
	122
	123	struct {
	124	u8 edid[512];
	125	u32 present;
	126	unsigned int blocks;
	127	} edid;
	128	};
	129
	130	#define adv748x_ctrl_to_hdmi(ctrl) \
	131	container_of(ctrl->handler, struct adv748x_hdmi, ctrl_hdl)
	132	#define adv748x_sd_to_hdmi(sd) container_of(sd, struct adv748x_hdmi, sd)
	133
	134	enum adv748x_afe_pads {
	135	ADV748X_AFE_SINK_AIN0,
	136	ADV748X_AFE_SINK_AIN1,
	137	ADV748X_AFE_SINK_AIN2,
	138	ADV748X_AFE_SINK_AIN3,
	139	ADV748X_AFE_SINK_AIN4,
	140	ADV748X_AFE_SINK_AIN5,
	141	ADV748X_AFE_SINK_AIN6,
	142	ADV748X_AFE_SINK_AIN7,
	143	ADV748X_AFE_SOURCE,
	144	ADV748X_AFE_NR_PADS,
	145	};
	146
	147	struct adv748x_afe {
	148	struct media_pad pads[ADV748X_AFE_NR_PADS];
	149	struct v4l2_ctrl_handler ctrl_hdl;
	150	struct v4l2_subdev sd;
	151	struct v4l2_mbus_framefmt format;
	152
	153	bool streaming;
	154	v4l2_std_id curr_norm;
	155	unsigned int input;
	156	};
	157
	158	#define adv748x_ctrl_to_afe(ctrl) \
	159	container_of(ctrl->handler, struct adv748x_afe, ctrl_hdl)
	160	#define adv748x_sd_to_afe(sd) container_of(sd, struct adv748x_afe, sd)
	161
	162	/**
	163	* struct adv748x_state - State of ADV748X
	164	* @dev: (OF) device
	165	* @client: I2C client
	166	* @mutex: protect global state
	167	*
	168	* @endpoints: parsed device node endpoints for each port
	169	*
	170	* @i2c_addresses I2C Page addresses
171	* @i2c_clients I2C clients for the page accesses
172	* @regmap regmap configuration pages.
173	*
174	* @hdmi: state of HDMI receiver context
175	* @afe: state of AFE receiver context
176	* @txa: state of TXA transmitter context
177	* @txb: state of TXB transmitter context
178	*/
179	struct adv748x_state {
180	struct device *dev;
181	struct i2c_client *client;
182	struct mutex mutex;
183
184	struct device_node *endpoints[ADV748X_PORT_MAX];
185
186	struct i2c_client *i2c_clients[ADV748X_PAGE_MAX];
187	struct regmap *regmap[ADV748X_PAGE_MAX];
188
189	struct adv748x_hdmi hdmi;
190	struct adv748x_afe afe;
191	struct adv748x_csi2 txa;
192	struct adv748x_csi2 txb;
193	};
194
195	#define adv748x_hdmi_to_state(h) container_of(h, struct adv748x_state, hdmi)
196	#define adv748x_afe_to_state(a) container_of(a, struct adv748x_state, afe)
197
198	#define adv_err(a, fmt, arg...) dev_err(a->dev, fmt, ##arg)
199	#define adv_info(a, fmt, arg...) dev_info(a->dev, fmt, ##arg)
200	#define adv_dbg(a, fmt, arg...) dev_dbg(a->dev, fmt, ##arg)
201
202	/* Register Mappings */
203
204	/* IO Map */
205	#define ADV748X_IO_PD 0x00 /* power down controls */
206	#define ADV748X_IO_PD_RX_EN BIT(6)
207
208	#define ADV748X_IO_REG_04 0x04
209	#define ADV748X_IO_REG_04_FORCE_FR BIT(0) /* Force CP free-run */
210
211	#define ADV748X_IO_DATAPATH 0x03 /* datapath cntrl */
212	#define ADV748X_IO_DATAPATH_VFREQ_M 0x70
213	#define ADV748X_IO_DATAPATH_VFREQ_SHIFT 4
214
215	#define ADV748X_IO_VID_STD 0x05
216
217	#define ADV748X_IO_10 0x10 /* io_reg_10 */
218	#define ADV748X_IO_10_CSI4_EN BIT(7)
219	#define ADV748X_IO_10_CSI1_EN BIT(6)
220	#define ADV748X_IO_10_PIX_OUT_EN BIT(5)
221
222	#define ADV748X_IO_CHIP_REV_ID_1 0xdf
223	#define ADV748X_IO_CHIP_REV_ID_2 0xe0
224
225	#define ADV748X_IO_SLAVE_ADDR_BASE 0xf2
226
227	/* HDMI RX Map */
228	#define ADV748X_HDMI_LW1 0x07 /* line width_1 */
229	#define ADV748X_HDMI_LW1_VERT_FILTER BIT(7)
230	#define ADV748X_HDMI_LW1_DE_REGEN BIT(5)
231	#define ADV748X_HDMI_LW1_WIDTH_MASK 0x1fff
232
233	#define ADV748X_HDMI_F0H1 0x09 /* field0 height_1 */
234	#define ADV748X_HDMI_F0H1_HEIGHT_MASK 0x1fff
235
236	#define ADV748X_HDMI_F1H1 0x0b /* field1 height_1 */
237	#define ADV748X_HDMI_F1H1_INTERLACED BIT(5)
238
239	#define ADV748X_HDMI_HFRONT_PORCH 0x20 /* hsync_front_porch_1 */
240	#define ADV748X_HDMI_HFRONT_PORCH_MASK 0x1fff
241
242	#define ADV748X_HDMI_HSYNC_WIDTH 0x22 /* hsync_pulse_width_1 */
243	#define ADV748X_HDMI_HSYNC_WIDTH_MASK 0x1fff
244
245	#define ADV748X_HDMI_HBACK_PORCH 0x24 /* hsync_back_porch_1 */
246	#define ADV748X_HDMI_HBACK_PORCH_MASK 0x1fff
247
248	#define ADV748X_HDMI_VFRONT_PORCH 0x2a /* field0_vs_front_porch_1 */
249	#define ADV748X_HDMI_VFRONT_PORCH_MASK 0x3fff
250
251	#define ADV748X_HDMI_VSYNC_WIDTH 0x2e /* field0_vs_pulse_width_1 */
252	#define ADV748X_HDMI_VSYNC_WIDTH_MASK 0x3fff
253
254	#define ADV748X_HDMI_VBACK_PORCH 0x32 /* field0_vs_back_porch_1 */
255	#define ADV748X_HDMI_VBACK_PORCH_MASK 0x3fff
256
257	#define ADV748X_HDMI_TMDS_1 0x51 /* hdmi_reg_51 */
258	#define ADV748X_HDMI_TMDS_2 0x52 /* hdmi_reg_52 */
259
260	/* HDMI RX Repeater Map */
261	#define ADV748X_REPEATER_EDID_SZ 0x70 /* primary_edid_size */
262	#define ADV748X_REPEATER_EDID_SZ_SHIFT 4
263
264	#define ADV748X_REPEATER_EDID_CTL 0x74 /* hdcp edid controls */
265	#define ADV748X_REPEATER_EDID_CTL_EN BIT(0) /* man_edid_a_enable */
266
267	/* SDP Main Map */
268	#define ADV748X_SDP_INSEL 0x00 /* user_map_rw_reg_00 */
269
270	#define ADV748X_SDP_VID_SEL 0x02 /* user_map_rw_reg_02 */
271	#define ADV748X_SDP_VID_SEL_MASK 0xf0
272	#define ADV748X_SDP_VID_SEL_SHIFT 4
273
274	/* Contrast - Unsigned*/
275	#define ADV748X_SDP_CON 0x08 /* user_map_rw_reg_08 */
276	#define ADV748X_SDP_CON_MIN 0
277	#define ADV748X_SDP_CON_DEF 128
278	#define ADV748X_SDP_CON_MAX 255
279
280	/* Brightness - Signed */
281	#define ADV748X_SDP_BRI 0x0a /* user_map_rw_reg_0a */
282	#define ADV748X_SDP_BRI_MIN -128
283	#define ADV748X_SDP_BRI_DEF 0
284	#define ADV748X_SDP_BRI_MAX 127
285
286	/* Hue - Signed, inverted*/
287	#define ADV748X_SDP_HUE 0x0b /* user_map_rw_reg_0b */
288	#define ADV748X_SDP_HUE_MIN -127
289	#define ADV748X_SDP_HUE_DEF 0
290	#define ADV748X_SDP_HUE_MAX 128
291
292	/* Test Patterns / Default Values */
293	#define ADV748X_SDP_DEF 0x0c /* user_map_rw_reg_0c */
294	#define ADV748X_SDP_DEF_VAL_EN BIT(0) /* Force free run mode */
295	#define ADV748X_SDP_DEF_VAL_AUTO_EN BIT(1) /* Free run when no signal */
296
297	#define ADV748X_SDP_MAP_SEL 0x0e /* user_map_rw_reg_0e */
298	#define ADV748X_SDP_MAP_SEL_RO_MAIN 1
299
300	/* Free run pattern select */
301	#define ADV748X_SDP_FRP 0x14
302	#define ADV748X_SDP_FRP_MASK GENMASK(3, 1)
303
304	/* Saturation */
305	#define ADV748X_SDP_SD_SAT_U 0xe3 /* user_map_rw_reg_e3 */
306	#define ADV748X_SDP_SD_SAT_V 0xe4 /* user_map_rw_reg_e4 */
307	#define ADV748X_SDP_SAT_MIN 0
308	#define ADV748X_SDP_SAT_DEF 128
309	#define ADV748X_SDP_SAT_MAX 255
310
311	/* SDP RO Main Map */
312	#define ADV748X_SDP_RO_10 0x10
313	#define ADV748X_SDP_RO_10_IN_LOCK BIT(0)
314
315	/* CP Map */
316	#define ADV748X_CP_PAT_GEN 0x37 /* int_pat_gen_1 */
317	#define ADV748X_CP_PAT_GEN_EN BIT(7)
318
319	/* Contrast Control - Unsigned */
320	#define ADV748X_CP_CON 0x3a /* contrast_cntrl */
321	#define ADV748X_CP_CON_MIN 0 /* Minimum contrast */
322	#define ADV748X_CP_CON_DEF 128 /* Default */
323	#define ADV748X_CP_CON_MAX 255 /* Maximum contrast */
324
325	/* Saturation Control - Unsigned */
326	#define ADV748X_CP_SAT 0x3b /* saturation_cntrl */
327	#define ADV748X_CP_SAT_MIN 0 /* Minimum saturation */
328	#define ADV748X_CP_SAT_DEF 128 /* Default */
329	#define ADV748X_CP_SAT_MAX 255 /* Maximum saturation */
330
331	/* Brightness Control - Signed */
332	#define ADV748X_CP_BRI 0x3c /* brightness_cntrl */
333	#define ADV748X_CP_BRI_MIN -128 /* Luma is -512d */
334	#define ADV748X_CP_BRI_DEF 0 /* Luma is 0 */
335	#define ADV748X_CP_BRI_MAX 127 /* Luma is 508d */
336
337	/* Hue Control */
338	#define ADV748X_CP_HUE 0x3d /* hue_cntrl */
339	#define ADV748X_CP_HUE_MIN 0 /* -90 degree */
340	#define ADV748X_CP_HUE_DEF 0 /* -90 degree */
341	#define ADV748X_CP_HUE_MAX 255 /* +90 degree */
342
343	#define ADV748X_CP_VID_ADJ 0x3e /* vid_adj_0 */
344	#define ADV748X_CP_VID_ADJ_ENABLE BIT(7) /* Enable colour controls */
345
346	#define ADV748X_CP_DE_POS_HIGH 0x8b /* de_pos_adj_6 */
347	#define ADV748X_CP_DE_POS_HIGH_SET BIT(6)
348	#define ADV748X_CP_DE_POS_END_LOW 0x8c /* de_pos_adj_7 */
349	#define ADV748X_CP_DE_POS_START_LOW 0x8d /* de_pos_adj_8 */
350
351	#define ADV748X_CP_VID_ADJ_2 0x91
352	#define ADV748X_CP_VID_ADJ_2_INTERLACED BIT(6)
353	#define ADV748X_CP_VID_ADJ_2_INTERLACED_3D BIT(4)
354
355	#define ADV748X_CP_CLMP_POS 0xc9 /* clmp_pos_cntrl_4 */
356	#define ADV748X_CP_CLMP_POS_DIS_AUTO BIT(0) /* dis_auto_param_buff */
357
358	/* CSI : TXA/TXB Maps */
359	#define ADV748X_CSI_VC_REF 0x0d /* csi_tx_top_reg_0d */
360	#define ADV748X_CSI_VC_REF_SHIFT 6
361
362	#define ADV748X_CSI_FS_AS_LS 0x1e /* csi_tx_top_reg_1e */
363	#define ADV748X_CSI_FS_AS_LS_UNKNOWN BIT(6) /* Undocumented bit */
364
365	/* Register handling */
366
367	int adv748x_read(struct adv748x_state *state, u8 addr, u8 reg);
368	int adv748x_write(struct adv748x_state *state, u8 page, u8 reg, u8 value);
369	int adv748x_write_block(struct adv748x_state *state, int client_page,
370	unsigned int init_reg, const void *val,
371	size_t val_len);
372
373	#define io_read(s, r) adv748x_read(s, ADV748X_PAGE_IO, r)
374	#define io_write(s, r, v) adv748x_write(s, ADV748X_PAGE_IO, r, v)
19c7306f	375	#define io_clrset(s, r, m, v) io_write(s, r, (io_read(s, r) & ~(m)) \| (v))
3e89586a KB	376
3e89586a KB	377	#define hdmi_read(s, r) adv748x_read(s, ADV748X_PAGE_HDMI, r)
19c7306f	378	#define hdmi_read16(s, r, m) (((hdmi_read(s, r) << 8) \| hdmi_read(s, (r)+1)) & (m))
3e89586a KB	379	#define hdmi_write(s, r, v) adv748x_write(s, ADV748X_PAGE_HDMI, r, v)
	380
	381	#define repeater_read(s, r) adv748x_read(s, ADV748X_PAGE_REPEATER, r)
	382	#define repeater_write(s, r, v) adv748x_write(s, ADV748X_PAGE_REPEATER, r, v)
	383
	384	#define sdp_read(s, r) adv748x_read(s, ADV748X_PAGE_SDP, r)
	385	#define sdp_write(s, r, v) adv748x_write(s, ADV748X_PAGE_SDP, r, v)
19c7306f	386	#define sdp_clrset(s, r, m, v) sdp_write(s, r, (sdp_read(s, r) & ~(m)) \| (v))
3e89586a KB	387
	388	#define cp_read(s, r) adv748x_read(s, ADV748X_PAGE_CP, r)
	389	#define cp_write(s, r, v) adv748x_write(s, ADV748X_PAGE_CP, r, v)
19c7306f	390	#define cp_clrset(s, r, m, v) cp_write(s, r, (cp_read(s, r) & ~(m)) \| (v))
3e89586a KB	391
	392	#define txa_read(s, r) adv748x_read(s, ADV748X_PAGE_TXA, r)
	393	#define txb_read(s, r) adv748x_read(s, ADV748X_PAGE_TXB, r)
	394
	395	#define tx_read(t, r) adv748x_read(t->state, t->page, r)
	396	#define tx_write(t, r, v) adv748x_write(t->state, t->page, r, v)
	397
	398	static inline struct v4l2_subdev adv748x_get_remote_sd(struct media_pad pad)
	399	{
	400	pad = media_entity_remote_pad(pad);
	401	if (!pad)
	402	return NULL;
	403
	404	return media_entity_to_v4l2_subdev(pad->entity);
	405	}
	406
	407	void adv748x_subdev_init(struct v4l2_subdev sd, struct adv748x_state state,
	408	const struct v4l2_subdev_ops *ops, u32 function,
	409	const char *ident);
	410
	411	int adv748x_register_subdevs(struct adv748x_state *state,
	412	struct v4l2_device *v4l2_dev);
	413
	414	int adv748x_txa_power(struct adv748x_state *state, bool on);
	415	int adv748x_txb_power(struct adv748x_state *state, bool on);
	416
	417	int adv748x_afe_init(struct adv748x_afe *afe);
	418	void adv748x_afe_cleanup(struct adv748x_afe *afe);
	419
	420	int adv748x_csi2_init(struct adv748x_state state, struct adv748x_csi2 tx);
	421	void adv748x_csi2_cleanup(struct adv748x_csi2 *tx);
	422	int adv748x_csi2_set_pixelrate(struct v4l2_subdev *sd, s64 rate);
	423
	424	int adv748x_hdmi_init(struct adv748x_hdmi *hdmi);
	425	void adv748x_hdmi_cleanup(struct adv748x_hdmi *hdmi);
	426
	427	#endif /* _ADV748X_H_ */