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f2efa4ee WY |
1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* Copyright (C) 2020 Intel Corporation */ | |
3 | ||
4 | #ifndef IPU_PLATFORM_BUTTRESS_REGS_H | |
5 | #define IPU_PLATFORM_BUTTRESS_REGS_H | |
6 | ||
7 | /* IS_WORKPOINT_REQ */ | |
8 | #define IPU_BUTTRESS_REG_IS_FREQ_CTL 0x34 | |
9 | /* PS_WORKPOINT_REQ */ | |
10 | #define IPU_BUTTRESS_REG_PS_FREQ_CTL 0x38 | |
11 | ||
12 | #define IPU_BUTTRESS_IS_FREQ_RATIO_MASK 0xff | |
13 | #define IPU_BUTTRESS_PS_FREQ_RATIO_MASK 0xff | |
14 | ||
15 | #define IPU_IS_FREQ_MAX 533 | |
16 | #define IPU_IS_FREQ_MIN 200 | |
17 | #define IPU_PS_FREQ_MAX 450 | |
18 | #define IPU_IS_FREQ_RATIO_BASE 25 | |
19 | #define IPU_PS_FREQ_RATIO_BASE 25 | |
20 | #define IPU_BUTTRESS_IS_FREQ_CTL_DIVISOR_MASK 0xff | |
21 | #define IPU_BUTTRESS_PS_FREQ_CTL_DIVISOR_MASK 0xff | |
22 | ||
23 | /* should be tuned for real silicon */ | |
3ebd4441 WY |
24 | #define IPU_IS_FREQ_CTL_DEFAULT_RATIO 0x08 |
25 | #define IPU6SE_IS_FREQ_CTL_DEFAULT_RATIO 0x0a | |
26 | #define IPU_PS_FREQ_CTL_DEFAULT_RATIO 0x10 | |
f2efa4ee WY |
27 | |
28 | #define IPU_IS_FREQ_CTL_DEFAULT_QOS_FLOOR_RATIO 0x10 | |
29 | #define IPU_PS_FREQ_CTL_DEFAULT_QOS_FLOOR_RATIO 0x0708 | |
30 | ||
31 | #define IPU_BUTTRESS_PWR_STATE_IS_PWR_SHIFT 3 | |
32 | #define IPU_BUTTRESS_PWR_STATE_IS_PWR_MASK \ | |
33 | (0x3 << IPU_BUTTRESS_PWR_STATE_IS_PWR_SHIFT) | |
34 | ||
35 | #define IPU_BUTTRESS_PWR_STATE_PS_PWR_SHIFT 6 | |
36 | #define IPU_BUTTRESS_PWR_STATE_PS_PWR_MASK \ | |
37 | (0x3 << IPU_BUTTRESS_PWR_STATE_PS_PWR_SHIFT) | |
38 | ||
39 | #define IPU_BUTTRESS_PWR_STATE_DN_DONE 0x0 | |
40 | #define IPU_BUTTRESS_PWR_STATE_UP_PROCESS 0x1 | |
41 | #define IPU_BUTTRESS_PWR_STATE_DN_PROCESS 0x2 | |
42 | #define IPU_BUTTRESS_PWR_STATE_UP_DONE 0x3 | |
43 | ||
44 | #define IPU_BUTTRESS_REG_FPGA_SUPPORT_0 0x270 | |
45 | #define IPU_BUTTRESS_REG_FPGA_SUPPORT_1 0x274 | |
46 | #define IPU_BUTTRESS_REG_FPGA_SUPPORT_2 0x278 | |
47 | #define IPU_BUTTRESS_REG_FPGA_SUPPORT_3 0x27c | |
48 | #define IPU_BUTTRESS_REG_FPGA_SUPPORT_4 0x280 | |
49 | #define IPU_BUTTRESS_REG_FPGA_SUPPORT_5 0x284 | |
50 | #define IPU_BUTTRESS_REG_FPGA_SUPPORT_6 0x288 | |
51 | #define IPU_BUTTRESS_REG_FPGA_SUPPORT_7 0x28c | |
52 | ||
53 | #define BUTTRESS_REG_WDT 0x8 | |
54 | #define BUTTRESS_REG_BTRS_CTRL 0xc | |
55 | #define BUTTRESS_REG_BTRS_CTRL_STALL_MODE_VC0 BIT(0) | |
56 | #define BUTTRESS_REG_BTRS_CTRL_STALL_MODE_VC1 BIT(1) | |
57 | ||
58 | #define BUTTRESS_REG_FW_RESET_CTL 0x30 | |
59 | #define BUTTRESS_FW_RESET_CTL_START BIT(0) | |
60 | #define BUTTRESS_FW_RESET_CTL_DONE BIT(1) | |
61 | ||
62 | #define BUTTRESS_REG_IS_FREQ_CTL 0x34 | |
63 | ||
64 | #define BUTTRESS_IS_FREQ_CTL_DIVISOR_MASK 0xf | |
65 | ||
66 | #define BUTTRESS_REG_PS_FREQ_CTL 0x38 | |
67 | ||
68 | #define BUTTRESS_PS_FREQ_CTL_RATIO_MASK 0xff | |
69 | ||
70 | #define BUTTRESS_FREQ_CTL_START BIT(31) | |
71 | #define BUTTRESS_FREQ_CTL_START_SHIFT 31 | |
72 | #define BUTTRESS_FREQ_CTL_QOS_FLOOR_SHIFT 8 | |
3ebd4441 | 73 | #define BUTTRESS_FREQ_CTL_ICCMAX_LEVEL (GENMASK(19, 16)) |
f2efa4ee WY |
74 | #define BUTTRESS_FREQ_CTL_QOS_FLOOR_MASK (0xff << 8) |
75 | ||
76 | #define BUTTRESS_REG_PWR_STATE 0x5c | |
77 | ||
78 | #define BUTTRESS_PWR_STATE_IS_PWR_SHIFT 3 | |
79 | #define BUTTRESS_PWR_STATE_IS_PWR_MASK (0x3 << 3) | |
80 | ||
81 | #define BUTTRESS_PWR_STATE_PS_PWR_SHIFT 6 | |
82 | #define BUTTRESS_PWR_STATE_PS_PWR_MASK (0x3 << 6) | |
83 | ||
84 | #define BUTTRESS_PWR_STATE_RESET 0x0 | |
85 | #define BUTTRESS_PWR_STATE_PWR_ON_DONE 0x1 | |
86 | #define BUTTRESS_PWR_STATE_PWR_RDY 0x3 | |
87 | #define BUTTRESS_PWR_STATE_PWR_IDLE 0x4 | |
88 | ||
89 | #define BUTTRESS_PWR_STATE_HH_STATUS_SHIFT 11 | |
90 | #define BUTTRESS_PWR_STATE_HH_STATUS_MASK (0x3 << 11) | |
91 | ||
92 | enum { | |
93 | BUTTRESS_PWR_STATE_HH_STATE_IDLE, | |
94 | BUTTRESS_PWR_STATE_HH_STATE_IN_PRGS, | |
95 | BUTTRESS_PWR_STATE_HH_STATE_DONE, | |
96 | BUTTRESS_PWR_STATE_HH_STATE_ERR, | |
97 | }; | |
98 | ||
99 | #define BUTTRESS_PWR_STATE_IS_PWR_FSM_SHIFT 19 | |
100 | #define BUTTRESS_PWR_STATE_IS_PWR_FSM_MASK (0xf << 19) | |
101 | ||
102 | #define BUTTRESS_PWR_STATE_IS_PWR_FSM_IDLE 0x0 | |
103 | #define BUTTRESS_PWR_STATE_IS_PWR_FSM_WAIT_4_PLL_CMP 0x1 | |
104 | #define BUTTRESS_PWR_STATE_IS_PWR_FSM_WAIT_4_CLKACK 0x2 | |
105 | #define BUTTRESS_PWR_STATE_IS_PWR_FSM_WAIT_4_PG_ACK 0x3 | |
106 | #define BUTTRESS_PWR_STATE_IS_PWR_FSM_RST_ASSRT_CYCLES 0x4 | |
107 | #define BUTTRESS_PWR_STATE_IS_PWR_FSM_STOP_CLK_CYCLES1 0x5 | |
108 | #define BUTTRESS_PWR_STATE_IS_PWR_FSM_STOP_CLK_CYCLES2 0x6 | |
109 | #define BUTTRESS_PWR_STATE_IS_PWR_FSM_RST_DEASSRT_CYCLES 0x7 | |
110 | #define BUTTRESS_PWR_STATE_IS_PWR_FSM_WAIT_4_FUSE_WR_CMP 0x8 | |
111 | #define BUTTRESS_PWR_STATE_IS_PWR_FSM_BRK_POINT 0x9 | |
112 | #define BUTTRESS_PWR_STATE_IS_PWR_FSM_IS_RDY 0xa | |
113 | #define BUTTRESS_PWR_STATE_IS_PWR_FSM_HALT_HALTED 0xb | |
114 | #define BUTTRESS_PWR_STATE_IS_PWR_FSM_RST_DURATION_CNT3 0xc | |
115 | #define BUTTRESS_PWR_STATE_IS_PWR_FSM_WAIT_4_CLKACK_PD 0xd | |
116 | #define BUTTRESS_PWR_STATE_IS_PWR_FSM_PD_BRK_POINT 0xe | |
117 | #define BUTTRESS_PWR_STATE_IS_PWR_FSM_WAIT_4_PD_PG_ACK0 0xf | |
118 | ||
119 | #define BUTTRESS_PWR_STATE_PS_PWR_FSM_SHIFT 24 | |
120 | #define BUTTRESS_PWR_STATE_PS_PWR_FSM_MASK (0x1f << 24) | |
121 | ||
122 | #define BUTTRESS_PWR_STATE_PS_PWR_FSM_IDLE 0x0 | |
123 | #define BUTTRESS_PWR_STATE_PS_PWR_FSM_WAIT_PU_PLL_IP_RDY 0x1 | |
124 | #define BUTTRESS_PWR_STATE_PS_PWR_FSM_WAIT_RO_PRE_CNT_EXH 0x2 | |
125 | #define BUTTRESS_PWR_STATE_PS_PWR_FSM_WAIT_PU_VGI_PWRGOOD 0x3 | |
126 | #define BUTTRESS_PWR_STATE_PS_PWR_FSM_WAIT_RO_POST_CNT_EXH 0x4 | |
127 | #define BUTTRESS_PWR_STATE_PS_PWR_FSM_WR_PLL_RATIO 0x5 | |
128 | #define BUTTRESS_PWR_STATE_PS_PWR_FSM_WAIT_PU_PLL_CMP 0x6 | |
129 | #define BUTTRESS_PWR_STATE_PS_PWR_FSM_WAIT_PU_CLKACK 0x7 | |
130 | #define BUTTRESS_PWR_STATE_PS_PWR_FSM_RST_ASSRT_CYCLES 0x8 | |
131 | #define BUTTRESS_PWR_STATE_PS_PWR_FSM_STOP_CLK_CYCLES1 0x9 | |
132 | #define BUTTRESS_PWR_STATE_PS_PWR_FSM_STOP_CLK_CYCLES2 0xa | |
133 | #define BUTTRESS_PWR_STATE_PS_PWR_FSM_RST_DEASSRT_CYCLES 0xb | |
134 | #define BUTTRESS_PWR_STATE_PS_PWR_FSM_PU_BRK_PNT 0xc | |
135 | #define BUTTRESS_PWR_STATE_PS_PWR_FSM_WAIT_FUSE_ACCPT 0xd | |
136 | #define BUTTRESS_PWR_STATE_PS_PWR_FSM_PS_PWR_UP 0xf | |
137 | #define BUTTRESS_PWR_STATE_PS_PWR_FSM_WAIT_4_HALTED 0x10 | |
138 | #define BUTTRESS_PWR_STATE_PS_PWR_FSM_RESET_CNT3 0x11 | |
139 | #define BUTTRESS_PWR_STATE_PS_PWR_FSM_WAIT_PD_CLKACK 0x12 | |
140 | #define BUTTRESS_PWR_STATE_PS_PWR_FSM_WAIT_PD_OFF_IND 0x13 | |
141 | #define BUTTRESS_PWR_STATE_PS_PWR_FSM_WAIT_DVFS_PH4 0x14 | |
142 | #define BUTTRESS_PWR_STATE_PS_PWR_FSM_WAIT_DVFS_PLL_CMP 0x15 | |
143 | #define BUTTRESS_PWR_STATE_PS_PWR_FSM_WAIT_DVFS_CLKACK 0x16 | |
144 | ||
145 | #define BUTTRESS_REG_SECURITY_CTL 0x300 | |
146 | ||
147 | #define BUTTRESS_SECURITY_CTL_FW_SECURE_MODE BIT(16) | |
148 | #define BUTTRESS_SECURITY_CTL_FW_SETUP_SHIFT 0 | |
149 | #define BUTTRESS_SECURITY_CTL_FW_SETUP_MASK 0x1f | |
150 | ||
151 | #define BUTTRESS_SECURITY_CTL_FW_SETUP_DONE 0x1 | |
152 | #define BUTTRESS_SECURITY_CTL_AUTH_DONE 0x2 | |
153 | #define BUTTRESS_SECURITY_CTL_AUTH_FAILED 0x8 | |
154 | ||
155 | #define BUTTRESS_REG_SENSOR_FREQ_CTL 0x16c | |
156 | ||
157 | #define BUTTRESS_SENSOR_FREQ_CTL_OSC_OUT_FREQ_DEFAULT(i) \ | |
158 | (0x1b << ((i) * 10)) | |
159 | #define BUTTRESS_SENSOR_FREQ_CTL_OSC_OUT_FREQ_SHIFT(i) ((i) * 10) | |
160 | #define BUTTRESS_SENSOR_FREQ_CTL_OSC_OUT_FREQ_MASK(i) \ | |
161 | (0x1ff << ((i) * 10)) | |
162 | ||
163 | #define BUTTRESS_SENSOR_CLK_FREQ_6P75MHZ 0x176 | |
164 | #define BUTTRESS_SENSOR_CLK_FREQ_8MHZ 0x164 | |
165 | #define BUTTRESS_SENSOR_CLK_FREQ_9P6MHZ 0x2 | |
166 | #define BUTTRESS_SENSOR_CLK_FREQ_12MHZ 0x1b2 | |
167 | #define BUTTRESS_SENSOR_CLK_FREQ_13P6MHZ 0x1ac | |
168 | #define BUTTRESS_SENSOR_CLK_FREQ_14P4MHZ 0x1cc | |
169 | #define BUTTRESS_SENSOR_CLK_FREQ_15P8MHZ 0x1a6 | |
170 | #define BUTTRESS_SENSOR_CLK_FREQ_16P2MHZ 0xca | |
171 | #define BUTTRESS_SENSOR_CLK_FREQ_17P3MHZ 0x12e | |
172 | #define BUTTRESS_SENSOR_CLK_FREQ_18P6MHZ 0x1c0 | |
173 | #define BUTTRESS_SENSOR_CLK_FREQ_19P2MHZ 0x0 | |
174 | #define BUTTRESS_SENSOR_CLK_FREQ_24MHZ 0xb2 | |
175 | #define BUTTRESS_SENSOR_CLK_FREQ_26MHZ 0xae | |
176 | #define BUTTRESS_SENSOR_CLK_FREQ_27MHZ 0x196 | |
177 | ||
178 | #define BUTTRESS_SENSOR_FREQ_CTL_LJPLL_FB_RATIO_MASK 0xff | |
179 | #define BUTTRESS_SENSOR_FREQ_CTL_SEL_MIPICLK_A_SHIFT 8 | |
180 | #define BUTTRESS_SENSOR_FREQ_CTL_SEL_MIPICLK_A_MASK (0x2 << 8) | |
181 | #define BUTTRESS_SENSOR_FREQ_CTL_SEL_MIPICLK_C_SHIFT 10 | |
182 | #define BUTTRESS_SENSOR_FREQ_CTL_SEL_MIPICLK_C_MASK (0x2 << 10) | |
183 | #define BUTTRESS_SENSOR_FREQ_CTL_LJPLL_FORCE_OFF_SHIFT 12 | |
184 | #define BUTTRESS_SENSOR_FREQ_CTL_LJPLL_REF_RATIO_SHIFT 14 | |
185 | #define BUTTRESS_SENSOR_FREQ_CTL_LJPLL_REF_RATIO_MASK (0x2 << 14) | |
186 | #define BUTTRESS_SENSOR_FREQ_CTL_LJPLL_PVD_RATIO_SHIFT 16 | |
187 | #define BUTTRESS_SENSOR_FREQ_CTL_LJPLL_PVD_RATIO_MASK (0x2 << 16) | |
188 | #define BUTTRESS_SENSOR_FREQ_CTL_LJPLL_OUTPUT_RATIO_SHIFT 18 | |
189 | #define BUTTRESS_SENSOR_FREQ_CTL_LJPLL_OUTPUT_RATIO_MASK (0x2 << 18) | |
190 | #define BUTTRESS_SENSOR_FREQ_CTL_START_SHIFT 31 | |
191 | ||
192 | #define BUTTRESS_REG_SENSOR_CLK_CTL 0x170 | |
193 | ||
194 | /* 0 <= i <= 2 */ | |
195 | #define BUTTRESS_SENSOR_CLK_CTL_OSC_CLK_OUT_EN_SHIFT(i) ((i) * 2) | |
196 | #define BUTTRESS_SENSOR_CLK_CTL_OSC_CLK_OUT_SEL_SHIFT(i) ((i) * 2 + 1) | |
197 | ||
198 | #define BUTTRESS_REG_FW_SOURCE_BASE_LO 0x78 | |
199 | #define BUTTRESS_REG_FW_SOURCE_BASE_HI 0x7C | |
200 | #define BUTTRESS_REG_FW_SOURCE_SIZE 0x80 | |
201 | ||
202 | #define BUTTRESS_REG_ISR_STATUS 0x90 | |
203 | #define BUTTRESS_REG_ISR_ENABLED_STATUS 0x94 | |
204 | #define BUTTRESS_REG_ISR_ENABLE 0x98 | |
205 | #define BUTTRESS_REG_ISR_CLEAR 0x9C | |
206 | ||
207 | #define BUTTRESS_ISR_IS_IRQ BIT(0) | |
208 | #define BUTTRESS_ISR_PS_IRQ BIT(1) | |
209 | #define BUTTRESS_ISR_IPC_EXEC_DONE_BY_CSE BIT(2) | |
210 | #define BUTTRESS_ISR_IPC_EXEC_DONE_BY_ISH BIT(3) | |
211 | #define BUTTRESS_ISR_IPC_FROM_CSE_IS_WAITING BIT(4) | |
212 | #define BUTTRESS_ISR_IPC_FROM_ISH_IS_WAITING BIT(5) | |
213 | #define BUTTRESS_ISR_CSE_CSR_SET BIT(6) | |
214 | #define BUTTRESS_ISR_ISH_CSR_SET BIT(7) | |
215 | #define BUTTRESS_ISR_SPURIOUS_CMP BIT(8) | |
216 | #define BUTTRESS_ISR_WATCHDOG_EXPIRED BIT(9) | |
217 | #define BUTTRESS_ISR_PUNIT_2_IUNIT_IRQ BIT(10) | |
218 | #define BUTTRESS_ISR_SAI_VIOLATION BIT(11) | |
219 | #define BUTTRESS_ISR_HW_ASSERTION BIT(12) | |
220 | ||
221 | #define BUTTRESS_REG_IU2CSEDB0 0x100 | |
222 | ||
223 | #define BUTTRESS_IU2CSEDB0_BUSY BIT(31) | |
224 | #define BUTTRESS_IU2CSEDB0_SHORT_FORMAT_SHIFT 27 | |
225 | #define BUTTRESS_IU2CSEDB0_CLIENT_ID_SHIFT 10 | |
226 | #define BUTTRESS_IU2CSEDB0_IPC_CLIENT_ID_VAL 2 | |
227 | ||
228 | #define BUTTRESS_REG_IU2CSEDATA0 0x104 | |
229 | ||
230 | #define BUTTRESS_IU2CSEDATA0_IPC_BOOT_LOAD 1 | |
231 | #define BUTTRESS_IU2CSEDATA0_IPC_AUTH_RUN 2 | |
232 | #define BUTTRESS_IU2CSEDATA0_IPC_AUTH_REPLACE 3 | |
233 | #define BUTTRESS_IU2CSEDATA0_IPC_UPDATE_SECURE_TOUCH 16 | |
234 | ||
235 | #define BUTTRESS_CSE2IUDATA0_IPC_BOOT_LOAD_DONE 1 | |
236 | #define BUTTRESS_CSE2IUDATA0_IPC_AUTH_RUN_DONE 2 | |
237 | #define BUTTRESS_CSE2IUDATA0_IPC_AUTH_REPLACE_DONE 4 | |
238 | #define BUTTRESS_CSE2IUDATA0_IPC_UPDATE_SECURE_TOUCH_DONE 16 | |
239 | ||
240 | #define BUTTRESS_REG_IU2CSECSR 0x108 | |
241 | ||
242 | #define BUTTRESS_IU2CSECSR_IPC_PEER_COMP_ACTIONS_RST_PHASE1 BIT(0) | |
243 | #define BUTTRESS_IU2CSECSR_IPC_PEER_COMP_ACTIONS_RST_PHASE2 BIT(1) | |
244 | #define BUTTRESS_IU2CSECSR_IPC_PEER_QUERIED_IP_COMP_ACTIONS_RST_PHASE BIT(2) | |
245 | #define BUTTRESS_IU2CSECSR_IPC_PEER_ASSERTED_REG_VALID_REQ BIT(3) | |
246 | #define BUTTRESS_IU2CSECSR_IPC_PEER_ACKED_REG_VALID BIT(4) | |
247 | #define BUTTRESS_IU2CSECSR_IPC_PEER_DEASSERTED_REG_VALID_REQ BIT(5) | |
248 | ||
249 | #define BUTTRESS_REG_CSE2IUDB0 0x304 | |
250 | #define BUTTRESS_REG_CSE2IUCSR 0x30C | |
251 | #define BUTTRESS_REG_CSE2IUDATA0 0x308 | |
252 | ||
253 | /* 0x20 == NACK, 0xf == unknown command */ | |
254 | #define BUTTRESS_CSE2IUDATA0_IPC_NACK 0xf20 | |
255 | #define BUTTRESS_CSE2IUDATA0_IPC_NACK_MASK 0xffff | |
256 | ||
257 | #define BUTTRESS_REG_ISH2IUCSR 0x50 | |
258 | #define BUTTRESS_REG_ISH2IUDB0 0x54 | |
259 | #define BUTTRESS_REG_ISH2IUDATA0 0x58 | |
260 | ||
261 | #define BUTTRESS_REG_IU2ISHDB0 0x10C | |
262 | #define BUTTRESS_REG_IU2ISHDATA0 0x110 | |
263 | #define BUTTRESS_REG_IU2ISHDATA1 0x114 | |
264 | #define BUTTRESS_REG_IU2ISHCSR 0x118 | |
265 | ||
266 | #define BUTTRESS_REG_ISH_START_DETECT 0x198 | |
267 | #define BUTTRESS_REG_ISH_START_DETECT_MASK 0x19C | |
268 | ||
269 | #define BUTTRESS_REG_FABRIC_CMD 0x88 | |
270 | ||
271 | #define BUTTRESS_FABRIC_CMD_START_TSC_SYNC BIT(0) | |
272 | #define BUTTRESS_FABRIC_CMD_IS_DRAIN BIT(4) | |
273 | ||
274 | #define BUTTRESS_REG_TSW_CTL 0x120 | |
275 | #define BUTTRESS_TSW_CTL_SOFT_RESET BIT(8) | |
276 | ||
277 | #define BUTTRESS_REG_TSC_LO 0x164 | |
278 | #define BUTTRESS_REG_TSC_HI 0x168 | |
279 | ||
280 | #define BUTTRESS_REG_CSI2_PORT_CONFIG_AB 0x200 | |
281 | #define BUTTRESS_CSI2_PORT_CONFIG_AB_MUX_MASK 0x1f | |
282 | #define BUTTRESS_CSI2_PORT_CONFIG_AB_COMBO_SHIFT_B0 16 | |
283 | ||
284 | #define BUTTRESS_REG_PS_FREQ_CAPABILITIES 0xf7498 | |
285 | ||
286 | #define BUTTRESS_PS_FREQ_CAPABILITIES_LAST_RESOLVED_RATIO_SHIFT 24 | |
287 | #define BUTTRESS_PS_FREQ_CAPABILITIES_LAST_RESOLVED_RATIO_MASK (0xff << 24) | |
288 | #define BUTTRESS_PS_FREQ_CAPABILITIES_MAX_RATIO_SHIFT 16 | |
289 | #define BUTTRESS_PS_FREQ_CAPABILITIES_MAX_RATIO_MASK (0xff << 16) | |
290 | #define BUTTRESS_PS_FREQ_CAPABILITIES_EFFICIENT_RATIO_SHIFT 8 | |
291 | #define BUTTRESS_PS_FREQ_CAPABILITIES_EFFICIENT_RATIO_MASK (0xff << 8) | |
292 | #define BUTTRESS_PS_FREQ_CAPABILITIES_MIN_RATIO_SHIFT 0 | |
293 | #define BUTTRESS_PS_FREQ_CAPABILITIES_MIN_RATIO_MASK (0xff) | |
294 | ||
295 | #define BUTTRESS_IRQS (BUTTRESS_ISR_IPC_FROM_CSE_IS_WAITING | \ | |
296 | BUTTRESS_ISR_IPC_EXEC_DONE_BY_CSE | \ | |
297 | BUTTRESS_ISR_IS_IRQ | \ | |
298 | BUTTRESS_ISR_PS_IRQ) | |
299 | ||
300 | #define IPU6SE_ISYS_PHY_0_BASE 0x10000 | |
301 | ||
302 | /* only use BB0, BB2, BB4, and BB6 on PHY0 */ | |
303 | #define IPU6SE_ISYS_PHY_BB_NUM 4 | |
304 | ||
305 | /* offset from PHY base */ | |
306 | #define PHY_CSI_CFG 0xc0 | |
307 | #define PHY_CSI_RCOMP_CONTROL 0xc8 | |
308 | #define PHY_CSI_BSCAN_EXCLUDE 0xd8 | |
309 | ||
310 | #define PHY_CPHY_DLL_OVRD(x) (0x100 + 0x100 * (x)) | |
311 | #define PHY_DPHY_DLL_OVRD(x) (0x14c + 0x100 * (x)) | |
312 | #define PHY_CPHY_RX_CONTROL1(x) (0x110 + 0x100 * (x)) | |
313 | #define PHY_CPHY_RX_CONTROL2(x) (0x114 + 0x100 * (x)) | |
314 | #define PHY_DPHY_CFG(x) (0x148 + 0x100 * (x)) | |
315 | #define PHY_BB_AFE_CONFIG(x) (0x174 + 0x100 * (x)) | |
316 | ||
317 | #endif /* IPU_PLATFORM_BUTTRESS_REGS_H */ |