#include <media/v4l2-ctrls.h>
#include <media/v4l2-device.h>
#include <media/v4l2-fwnode.h>
+#include "pmic_dsc1.h"
#define HM11B1_LINK_FREQ_384MHZ 384000000ULL
#define HM11B1_SCLK 72000000LL
int link_freq_index;
int ret = 0;
+ pmic_dsc1_set_power(1);
link_freq_index = hm11b1->cur_mode->link_freq_index;
reg_list = &link_freq_configs[link_freq_index].reg_list;
ret = hm11b1_write_reg_list(hm11b1, reg_list);
if (hm11b1_write_reg(hm11b1, HM11B1_REG_MODE_SELECT, 1,
HM11B1_MODE_STANDBY))
dev_err(&client->dev, "failed to stop streaming");
+ pmic_dsc1_set_power(0);
}
static int hm11b1_set_stream(struct v4l2_subdev *sd, int enable)
return -ENOMEM;
v4l2_i2c_subdev_init(&hm11b1->sd, client, &hm11b1_subdev_ops);
+ pmic_dsc1_set_power(0);
+ pmic_dsc1_set_power(1);
ret = hm11b1_identify_module(hm11b1);
if (ret) {
dev_err(&client->dev, "failed to find sensor: %d", ret);
pm_runtime_enable(&client->dev);
pm_runtime_idle(&client->dev);
+ pmic_dsc1_set_power(0);
return 0;
probe_error_media_entity_cleanup:
#ifdef CONFIG_ACPI
static const struct acpi_device_id hm11b1_acpi_ids[] = {
- {"HM11B1"},
+ {"HIMX11B1"},
{}
};
#include <media/v4l2-ctrls.h>
#include <media/v4l2-device.h>
#include <media/v4l2-fwnode.h>
+#include "pmic_dsc1.h"
#define OV01A1S_LINK_FREQ_400MHZ 400000000ULL
#define OV01A1S_SCLK 40000000LL
int link_freq_index;
int ret = 0;
+ pmic_dsc1_set_power(1);
link_freq_index = ov01a1s->cur_mode->link_freq_index;
reg_list = &link_freq_configs[link_freq_index].reg_list;
ret = ov01a1s_write_reg_list(ov01a1s, reg_list);
OV01A1S_MODE_STANDBY);
if (ret)
dev_err(&client->dev, "failed to stop streaming");
+ pmic_dsc1_set_power(0);
}
static int ov01a1s_set_stream(struct v4l2_subdev *sd, int enable)
return -ENOMEM;
v4l2_i2c_subdev_init(&ov01a1s->sd, client, &ov01a1s_subdev_ops);
+ pmic_dsc1_set_power(0);
+ pmic_dsc1_set_power(1);
ret = ov01a1s_identify_module(ov01a1s);
if (ret) {
dev_err(&client->dev, "failed to find sensor: %d", ret);
pm_runtime_enable(&client->dev);
pm_runtime_idle(&client->dev);
+ pmic_dsc1_set_power(0);
return 0;
probe_error_media_entity_cleanup:
#ifdef CONFIG_ACPI
static const struct acpi_device_id ov01a1s_acpi_ids[] = {
- { "OVTI01AF" },
+ { "OVTI01AS" },
{}
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2020 Intel Corporation.
+
+#include <linux/delay.h>
+#include <linux/module.h>
+#include "pmic_dsc1.h"
+
+/* mcu gpio resources*/
+static const struct acpi_gpio_params camreset_gpio = { 0, 0, false };
+static const struct acpi_gpio_params campwdn_gpio = { 1, 0, false };
+static const struct acpi_gpio_params midmclken_gpio = { 2, 0, false };
+static const struct acpi_gpio_params led_gpio = { 3, 0, false };
+static const struct acpi_gpio_mapping dsc1_acpi_gpios[] = {
+ { "camreset-gpios", &camreset_gpio, 1 },
+ { "campwdn-gpios", &campwdn_gpio, 1 },
+ { "midmclken-gpios", &midmclken_gpio, 1 },
+ { "indled-gpios", &led_gpio, 1 },
+ { }
+};
+
+static const char * const pin_names[] = {
+ "camreset", "campwdn", "midmclken", "indled"
+};
+
+struct pmic_dsc1 pmic = {
+ .reset_gpio = NULL,
+ .powerdn_gpio = NULL,
+ .clocken_gpio = NULL,
+ .indled_gpio = NULL,
+ .power_on = false,
+ .gpio_ready = false,
+};
+
+static int get_gpio_pin(struct gpio_desc **pin_d, struct pci_dev *pdev, int idx)
+{
+ int count = PMIC_DSC1_PROBE_MAX_TRY;
+
+ do {
+ dev_dbg(&pdev->dev, "get %s:tried once\n", pin_names[idx]);
+ *pin_d = devm_gpiod_get(&pdev->dev, pin_names[idx],
+ GPIOD_OUT_LOW);
+ if (!IS_ERR(*pin_d))
+ return 0;
+ *pin_d = NULL;
+ msleep_interruptible(PMIC_DSC1_PROBE_TRY_GAP);
+ } while (--count > 0);
+
+ return -EBUSY;
+}
+
+static int pmic_dsc1_probe(struct pci_dev *pdev,
+ const struct pci_device_id *id)
+{
+ int ret;
+
+ if (!pdev) {
+ dev_err(&pdev->dev, "@%s: probed null pdev %x:%x\n",
+ __func__, PCI_BRG_VENDOR_ID, PCI_BRG_PRODUCT_ID);
+ return -ENODEV;
+ }
+ dev_dbg(&pdev->dev, "@%s, enter\n", __func__);
+
+ ret = devm_acpi_dev_add_driver_gpios(&pdev->dev, dsc1_acpi_gpios);
+ if (ret) {
+ dev_err(&pdev->dev, "@%s: fail to add gpio\n", __func__);
+ return -EBUSY;
+ }
+ ret = get_gpio_pin(&pmic.reset_gpio, pdev, 0);
+ if (ret)
+ goto pmic_dsc1_probe_end;
+ ret = get_gpio_pin(&pmic.powerdn_gpio, pdev, 1);
+ if (ret)
+ goto pmic_dsc1_probe_end;
+ ret = get_gpio_pin(&pmic.clocken_gpio, pdev, 2);
+ if (ret)
+ goto pmic_dsc1_probe_end;
+ ret = get_gpio_pin(&pmic.indled_gpio, pdev, 3);
+ if (ret)
+ goto pmic_dsc1_probe_end;
+
+ mutex_lock(&pmic.status_lock);
+ pmic.gpio_ready = true;
+ mutex_unlock(&pmic.status_lock);
+
+pmic_dsc1_probe_end:
+ dev_dbg(&pdev->dev, "@%s, exit\n", __func__);
+ return ret;
+}
+
+static void pmic_dsc1_remove(struct pci_dev *pdev)
+{
+ dev_dbg(&pdev->dev, "@%s, enter\n", __func__);
+ mutex_lock(&pmic.status_lock);
+ pmic.gpio_ready = false;
+ gpiod_set_value_cansleep(pmic.reset_gpio, 0);
+ gpiod_put(pmic.reset_gpio);
+ gpiod_set_value_cansleep(pmic.powerdn_gpio, 0);
+ gpiod_put(pmic.powerdn_gpio);
+ gpiod_set_value_cansleep(pmic.clocken_gpio, 0);
+ gpiod_put(pmic.clocken_gpio);
+ gpiod_set_value_cansleep(pmic.indled_gpio, 0);
+ gpiod_put(pmic.indled_gpio);
+ mutex_unlock(&pmic.status_lock);
+ dev_dbg(&pdev->dev, "@%s, exit\n", __func__);
+}
+
+static struct pci_device_id pmic_dsc1_ids[] = {
+ { PCI_DEVICE(PCI_BRG_VENDOR_ID, PCI_BRG_PRODUCT_ID) },
+ { 0, },
+};
+MODULE_DEVICE_TABLE(pci, pmic_dsc1_ids);
+
+static struct pci_driver pmic_dsc1_driver = {
+ .name = PMIC_DRV_NAME,
+ .id_table = pmic_dsc1_ids,
+ .probe = pmic_dsc1_probe,
+ .remove = pmic_dsc1_remove,
+};
+
+static int __init pmic_dsc1_init(void)
+{
+ mutex_init(&pmic.status_lock);
+ return pci_register_driver(&pmic_dsc1_driver);
+}
+
+static void __exit pmic_dsc1_exit(void)
+{
+ pci_unregister_driver(&pmic_dsc1_driver);
+}
+module_init(pmic_dsc1_init);
+module_exit(pmic_dsc1_exit);
+
+int pmic_dsc1_set_power(int on)
+{
+ mutex_lock(&pmic.status_lock);
+ if (!pmic.gpio_ready || on < 0 || on > 1) {
+ pr_debug("@%s,failed to set power, gpio_ready=%d, on=%d\n",
+ __func__, pmic.gpio_ready, on);
+ mutex_unlock(&pmic.status_lock);
+ return -EBUSY;
+ }
+ if (pmic.power_on != on) {
+ gpiod_set_value_cansleep(pmic.reset_gpio, on);
+ gpiod_set_value_cansleep(pmic.powerdn_gpio, on);
+ gpiod_set_value_cansleep(pmic.clocken_gpio, on);
+ gpiod_set_value_cansleep(pmic.indled_gpio, on);
+ pmic.power_on = on;
+ }
+ mutex_unlock(&pmic.status_lock);
+ return 0;
+}
+EXPORT_SYMBOL_GPL(pmic_dsc1_set_power);
+
+MODULE_AUTHOR("Bingbu Cao <bingbu.cao@intel.com>");
+MODULE_AUTHOR("Qiu, Tianshu <tian.shu.qiu@intel.com>");
+MODULE_AUTHOR("Xu, Chongyang <chongyang.xu@intel.com>");
+MODULE_DESCRIPTION("PMIC-CRDG DSC1 driver");
+MODULE_LICENSE("GPL v2");
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright (c) 2020 Intel Corporation. */
+
+#ifndef _PMIC_DSC1_H_
+#define _PMIC_DSC1_H_
+
+#include <linux/gpio/consumer.h>
+#include <linux/mutex.h>
+#include <linux/pci.h>
+
+/* pmic dsc1 pci id */
+#define PCI_BRG_VENDOR_ID 0x8086
+#define PCI_BRG_PRODUCT_ID 0x9a14
+
+#define PMIC_DRV_NAME "pmic_dsc1"
+#define PMIC_DSC1_PROBE_MAX_TRY 5
+#define PMIC_DSC1_PROBE_TRY_GAP 500 /* in millseconds */
+
+struct pmic_dsc1 {
+ /* gpio resource*/
+ struct gpio_desc *reset_gpio;
+ struct gpio_desc *powerdn_gpio;
+ struct gpio_desc *clocken_gpio;
+ struct gpio_desc *indled_gpio;
+ /* status */
+ struct mutex status_lock;
+ bool power_on;
+ bool gpio_ready;
+};
+
+/* exported function for extern module */
+int pmic_dsc1_set_power(int on);
+#endif
-config VIDEO_INTEL_IPU
+config VIDEO_INTEL_IPU6
tristate "Intel IPU driver"
depends on ACPI
depends on MEDIA_SUPPORT
depends on MEDIA_PCI_SUPPORT
+ depends on X86_64
select IOMMU_API
select IOMMU_IOVA
- select X86_DEV_DMA_OPS if X86
+ select X86_DEV_DMA_OPS
select VIDEOBUF2_DMA_CONTIG
select V4L2_FWNODE
select PHYS_ADDR_T_64BIT
This is the Intel imaging processing unit, found in Intel SoCs and
used for capturing images and video from a camera sensor.
- To compile this driver, say Y here!
-
-choice
- prompt "intel ipu generation type"
- depends on VIDEO_INTEL_IPU
- default VIDEO_INTEL_IPU6
-
-config VIDEO_INTEL_IPU6
- bool "Compile for IPU6 driver"
- help
- Sixth generation Intel imaging processing unit found in Intel
- SoCs.
-
- To compile this driver, say Y here!
-endchoice
+ To compile this driver, say Y here! It contains 3 modules -
+ intel_ipu6, intel_ipu6_isys and intel_ipu6_psys.
config VIDEO_INTEL_IPU_TPG
bool "Compile for TPG driver"
+ depends on VIDEO_INTEL_IPU6
help
If selected, TPG device nodes would be created.
If you want to the TPG devices exposed to user as media entity,
you must select this option, otherwise no.
-config VIDEO_INTEL_IPU_WERROR
- bool "Force GCC to throw an error instead of a warning when compiling"
- depends on VIDEO_INTEL_IPU
- depends on EXPERT
- depends on !COMPILE_TEST
- default n
- help
- Add -Werror to the build flags for (and only for) intel ipu module.
- Do not enable this unless you are writing code for the ipu module.
-
- Recommended for driver developers only.
-
- If in doubt, say "N".
-
source "drivers/media/pci/intel/ipu3/Kconfig"
subdir-ccflags-y += $(call cc-disable-warning, missing-field-initializers)
subdir-ccflags-$(CONFIG_VIDEO_INTEL_IPU_WERROR) += -Werror
-obj-$(CONFIG_VIDEO_IPU3_CIO2) += ipu3/
-#obj-$(CONFIG_VIDEO_INTEL_IPU4) += ipu4/
-#obj-$(CONFIG_VIDEO_INTEL_IPU4P) += ipu4/
+obj-$(CONFIG_VIDEO_IPU3_CIO2) += ipu3/
obj-$(CONFIG_VIDEO_INTEL_IPU6) += ipu6/
#define BUTTRESS_IPC_CMD_SEND_RETRY 1
-static const struct ipu_buttress_sensor_clk_freq sensor_clk_freqs[] = {
- {6750000, BUTTRESS_SENSOR_CLK_FREQ_6P75MHZ},
- {8000000, BUTTRESS_SENSOR_CLK_FREQ_8MHZ},
- {9600000, BUTTRESS_SENSOR_CLK_FREQ_9P6MHZ},
- {12000000, BUTTRESS_SENSOR_CLK_FREQ_12MHZ},
- {13600000, BUTTRESS_SENSOR_CLK_FREQ_13P6MHZ},
- {14400000, BUTTRESS_SENSOR_CLK_FREQ_14P4MHZ},
- {15800000, BUTTRESS_SENSOR_CLK_FREQ_15P8MHZ},
- {16200000, BUTTRESS_SENSOR_CLK_FREQ_16P2MHZ},
- {17300000, BUTTRESS_SENSOR_CLK_FREQ_17P3MHZ},
- {18600000, BUTTRESS_SENSOR_CLK_FREQ_18P6MHZ},
- {19200000, BUTTRESS_SENSOR_CLK_FREQ_19P2MHZ},
- {24000000, BUTTRESS_SENSOR_CLK_FREQ_24MHZ},
- {26000000, BUTTRESS_SENSOR_CLK_FREQ_26MHZ},
- {27000000, BUTTRESS_SENSOR_CLK_FREQ_27MHZ}
-};
-
static const u32 ipu_adev_irq_mask[] = {
BUTTRESS_ISR_IS_IRQ, BUTTRESS_ISR_PS_IRQ
};
int ipu_buttress_ipc_reset(struct ipu_device *isp, struct ipu_buttress_ipc *ipc)
{
struct ipu_buttress *b = &isp->buttress;
- unsigned int timeout = BUTTRESS_IPC_RESET_TIMEOUT;
+ unsigned int retries = BUTTRESS_IPC_RESET_TIMEOUT;
u32 val = 0, csr_in_clr;
if (!isp->secure_mode) {
BUTTRESS_IU2CSECSR_IPC_PEER_ACKED_REG_VALID |
BUTTRESS_IU2CSECSR_IPC_PEER_ASSERTED_REG_VALID_REQ | QUERY;
- while (timeout--) {
+ while (retries--) {
usleep_range(400, 500);
val = readl(isp->base + ipc->csr_in);
switch (val) {
writel(QUERY, isp->base + ipc->csr_out);
break;
case ENTRY:
- case ENTRY | QUERY:
+ case (ENTRY | QUERY):
dev_dbg(&isp->pdev->dev,
"%s:IPC_PEER_COMP_ACTIONS_RST_PHASE1\n",
__func__);
writel(ENTRY, isp->base + ipc->csr_out);
break;
case EXIT:
- case EXIT | QUERY:
+ case (EXIT | QUERY):
dev_dbg(&isp->pdev->dev,
"%s: IPC_PEER_COMP_ACTIONS_RST_PHASE2\n",
__func__);
} else {
val = BUTTRESS_FREQ_CTL_START |
ctrl->divisor << ctrl->divisor_shift |
- ctrl->qos_floor << BUTTRESS_FREQ_CTL_QOS_FLOOR_SHIFT;
+ ctrl->qos_floor << BUTTRESS_FREQ_CTL_QOS_FLOOR_SHIFT |
+ BUTTRESS_FREQ_CTL_ICCMAX_LEVEL;
pwr_sts = ctrl->pwr_sts_on << ctrl->pwr_sts_shift;
}
mutex_unlock(&isp->buttress.power_mutex);
}
+static void ipu_buttress_set_isys_ratio(struct ipu_device *isp,
+ unsigned int isys_divisor)
+{
+ struct ipu_buttress_ctrl *ctrl = isp->isys->ctrl;
+
+ mutex_lock(&isp->buttress.power_mutex);
+
+ if (ctrl->divisor == isys_divisor)
+ goto out_mutex_unlock;
+
+ ctrl->divisor = isys_divisor;
+
+ if (ctrl->started) {
+ writel(BUTTRESS_FREQ_CTL_START |
+ ctrl->qos_floor << BUTTRESS_FREQ_CTL_QOS_FLOOR_SHIFT |
+ isys_divisor, isp->base + BUTTRESS_REG_IS_FREQ_CTL);
+ }
+
+out_mutex_unlock:
+ mutex_unlock(&isp->buttress.power_mutex);
+}
+
static void ipu_buttress_set_psys_freq(struct ipu_device *isp,
unsigned int freq)
{
#define to_clk_ipu_sensor(_hw) container_of(_hw, struct clk_ipu_sensor, hw)
-static int ipu_buttress_clk_pll_prepare(struct clk_hw *hw)
-{
- struct clk_ipu_sensor *ck = to_clk_ipu_sensor(hw);
- int ret;
-
- /* Workaround needed to get sensor clock running in some cases */
- ret = pm_runtime_get_sync(&ck->isp->isys->dev);
- return ret >= 0 ? 0 : ret;
-}
-
-static void ipu_buttress_clk_pll_unprepare(struct clk_hw *hw)
-{
- struct clk_ipu_sensor *ck = to_clk_ipu_sensor(hw);
-
- /* Workaround needed to get sensor clock stopped in some cases */
- pm_runtime_put(&ck->isp->isys->dev);
-}
-
-static int ipu_buttress_clk_pll_enable(struct clk_hw *hw)
-{
- struct clk_ipu_sensor *ck = to_clk_ipu_sensor(hw);
- u32 val;
- unsigned int i;
-
- /*
- * Start bit behaves like master clock request towards ICLK.
- * It is needed regardless of the 24 MHz or per clock out pll
- * setting.
- */
- val = readl(ck->isp->base + BUTTRESS_REG_SENSOR_FREQ_CTL);
- val |= BUTTRESS_FREQ_CTL_START;
- val &= ~BUTTRESS_SENSOR_FREQ_CTL_OSC_OUT_FREQ_MASK(ck->id);
- for (i = 0; i < ARRAY_SIZE(sensor_clk_freqs); i++)
- if (sensor_clk_freqs[i].rate == ck->rate)
- break;
-
- if (i < ARRAY_SIZE(sensor_clk_freqs))
- val |= sensor_clk_freqs[i].val <<
- BUTTRESS_SENSOR_FREQ_CTL_OSC_OUT_FREQ_SHIFT(ck->id);
- else
- val |= BUTTRESS_SENSOR_FREQ_CTL_OSC_OUT_FREQ_DEFAULT(ck->id);
-
- writel(val, ck->isp->base + BUTTRESS_REG_SENSOR_FREQ_CTL);
-
- return 0;
-}
-
-static void ipu_buttress_clk_pll_disable(struct clk_hw *hw)
-{
- struct clk_ipu_sensor *ck = to_clk_ipu_sensor(hw);
- u32 val;
- int i;
-
- val = readl(ck->isp->base + BUTTRESS_REG_SENSOR_CLK_CTL);
- for (i = 0; i < IPU_BUTTRESS_NUM_OF_SENS_CKS; i++) {
- if (val &
- (1 << BUTTRESS_SENSOR_CLK_CTL_OSC_CLK_OUT_EN_SHIFT(i)))
- return;
- }
-
- /* See enable control above */
- val = readl(ck->isp->base + BUTTRESS_REG_SENSOR_FREQ_CTL);
- val &= ~BUTTRESS_FREQ_CTL_START;
- writel(val, ck->isp->base + BUTTRESS_REG_SENSOR_FREQ_CTL);
-}
-
-static int ipu_buttress_clk_enable(struct clk_hw *hw)
-{
- struct clk_ipu_sensor *ck = to_clk_ipu_sensor(hw);
- u32 val;
-
- val = readl(ck->isp->base + BUTTRESS_REG_SENSOR_CLK_CTL);
- val |= 1 << BUTTRESS_SENSOR_CLK_CTL_OSC_CLK_OUT_EN_SHIFT(ck->id);
-
- /* Enable dynamic sensor clock */
- val |= 1 << BUTTRESS_SENSOR_CLK_CTL_OSC_CLK_OUT_SEL_SHIFT(ck->id);
- writel(val, ck->isp->base + BUTTRESS_REG_SENSOR_CLK_CTL);
-
- return 0;
-}
-
-static void ipu_buttress_clk_disable(struct clk_hw *hw)
-{
- struct clk_ipu_sensor *ck = to_clk_ipu_sensor(hw);
- u32 val;
-
- val = readl(ck->isp->base + BUTTRESS_REG_SENSOR_CLK_CTL);
- val &= ~(1 << BUTTRESS_SENSOR_CLK_CTL_OSC_CLK_OUT_EN_SHIFT(ck->id));
- writel(val, ck->isp->base + BUTTRESS_REG_SENSOR_CLK_CTL);
-}
-
-static long ipu_buttress_clk_round_rate(struct clk_hw *hw,
- unsigned long rate,
- unsigned long *parent_rate)
-{
- unsigned long best = ULONG_MAX;
- unsigned long round_rate = 0;
- int i;
-
- for (i = 0; i < ARRAY_SIZE(sensor_clk_freqs); i++) {
- long diff = sensor_clk_freqs[i].rate - rate;
-
- if (diff == 0)
- return rate;
-
- diff = abs(diff);
- if (diff < best) {
- best = diff;
- round_rate = sensor_clk_freqs[i].rate;
- }
- }
-
- return round_rate;
-}
-
-static unsigned long
-ipu_buttress_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
-{
- struct clk_ipu_sensor *ck = to_clk_ipu_sensor(hw);
-
- return ck->rate;
-}
-
-static int ipu_buttress_clk_set_rate(struct clk_hw *hw,
- unsigned long rate,
- unsigned long parent_rate)
-{
- struct clk_ipu_sensor *ck = to_clk_ipu_sensor(hw);
-
- /*
- * R N P PVD PLLout
- * 1 45 128 2 6.75
- * 1 40 96 2 8
- * 1 40 80 2 9.6
- * 1 15 20 4 14.4
- * 1 40 32 2 24
- * 1 65 48 1 26
- *
- */
- ck->rate = rate;
-
- return 0;
-}
-
-static const struct clk_ops ipu_buttress_clk_sensor_ops = {
- .enable = ipu_buttress_clk_enable,
- .disable = ipu_buttress_clk_disable,
-};
-
-static const struct clk_ops ipu_buttress_clk_sensor_ops_parent = {
- .enable = ipu_buttress_clk_pll_enable,
- .disable = ipu_buttress_clk_pll_disable,
- .prepare = ipu_buttress_clk_pll_prepare,
- .unprepare = ipu_buttress_clk_pll_unprepare,
- .round_rate = ipu_buttress_clk_round_rate,
- .recalc_rate = ipu_buttress_clk_recalc_rate,
- .set_rate = ipu_buttress_clk_set_rate,
-};
-
int ipu_buttress_tsc_read(struct ipu_device *isp, u64 *val)
{
struct ipu_buttress *b = &isp->buttress;
return 0;
}
+int ipu_buttress_isys_freq_get(void *data, u64 *val)
+{
+ struct ipu_device *isp = data;
+ u32 reg_val;
+ int rval;
+
+ rval = pm_runtime_get_sync(&isp->isys->dev);
+ if (rval < 0) {
+ pm_runtime_put(&isp->isys->dev);
+ dev_err(&isp->pdev->dev, "Runtime PM failed (%d)\n", rval);
+ return rval;
+ }
+
+ reg_val = readl(isp->base + BUTTRESS_REG_IS_FREQ_CTL);
+
+ pm_runtime_put(&isp->isys->dev);
+
+ *val = IPU_IS_FREQ_RATIO_BASE *
+ (reg_val & IPU_BUTTRESS_IS_FREQ_CTL_DIVISOR_MASK);
+
+ return 0;
+}
+
+int ipu_buttress_isys_freq_set(void *data, u64 val)
+{
+ struct ipu_device *isp = data;
+ int rval;
+
+ if (val < BUTTRESS_MIN_FORCE_IS_FREQ ||
+ val > BUTTRESS_MAX_FORCE_IS_FREQ)
+ return -EINVAL;
+
+ rval = pm_runtime_get_sync(&isp->isys->dev);
+ if (rval < 0) {
+ pm_runtime_put(&isp->isys->dev);
+ dev_err(&isp->pdev->dev, "Runtime PM failed (%d)\n", rval);
+ return rval;
+ }
+
+ do_div(val, BUTTRESS_IS_FREQ_STEP);
+ if (val)
+ ipu_buttress_set_isys_ratio(isp, val);
+
+ pm_runtime_put(&isp->isys->dev);
+
+ return 0;
+}
+
DEFINE_SIMPLE_ATTRIBUTE(ipu_buttress_psys_force_freq_fops,
ipu_buttress_psys_force_freq_get,
ipu_buttress_psys_force_freq_set, "%llu\n");
ipu_buttress_psys_freq_get, NULL, "%llu\n");
DEFINE_SIMPLE_ATTRIBUTE(ipu_buttress_isys_freq_fops,
- ipu_buttress_isys_freq_get, NULL, "%llu\n");
+ ipu_buttress_isys_freq_get,
+ ipu_buttress_isys_freq_set, "%llu\n");
int ipu_buttress_debugfs_init(struct ipu_device *isp)
{
if (!file)
goto err;
- file = debugfs_create_file("isys_freq", 0400, dir, isp,
+ file = debugfs_create_file("isys_freq", 0700, dir, isp,
&ipu_buttress_isys_freq_fops);
if (!file)
goto err;
#define BUTTRESS_MIN_FORCE_PS_FREQ (BUTTRESS_PS_FREQ_STEP * 8)
#define BUTTRESS_MAX_FORCE_PS_FREQ (BUTTRESS_PS_FREQ_STEP * 32)
+#define BUTTRESS_IS_FREQ_STEP 25U
+#define BUTTRESS_MIN_FORCE_IS_FREQ (BUTTRESS_IS_FREQ_STEP * 8)
+#define BUTTRESS_MAX_FORCE_IS_FREQ (BUTTRESS_IS_FREQ_STEP * 16)
+
struct ipu_buttress_ctrl {
u32 freq_ctl, pwr_sts_shift, pwr_sts_mask, pwr_sts_on, pwr_sts_off;
union {
int ipu_buttress_restore(struct ipu_device *isp);
int ipu_buttress_psys_freq_get(void *data, u64 *val);
-int ipu_buttress_isys_freq_get(void *data, u64 *val);
#endif /* IPU_BUTTRESS_H */
#include <linux/iova.h>
#include <linux/module.h>
#include <linux/scatterlist.h>
+#include <linux/version.h>
#include <linux/vmalloc.h>
+#include <linux/dma-map-ops.h>
#include "ipu-dma.h"
#include "ipu-bus.h"
stream_cfg->output_pins[i].output_res.height);
dev_dbg(dev, "Stride %d\n", stream_cfg->output_pins[i].stride);
dev_dbg(dev, "Pin type %d\n", stream_cfg->output_pins[i].pt);
+ dev_dbg(dev, "Payload %d\n",
+ stream_cfg->output_pins[i].payload_buf_size);
dev_dbg(dev, "Ft %d\n", stream_cfg->output_pins[i].ft);
dev_dbg(dev, "Watermar in lines %d\n",
stream_cfg->output_pins[i].watermark_in_lines);
static const struct v4l2_subdev_core_ops csi2_be_soc_sd_core_ops = {
};
+static const struct v4l2_ctrl_config compression_ctrl_cfg = {
+ .ops = NULL,
+ .id = V4L2_CID_IPU_ISYS_COMPRESSION,
+ .name = "ISYS BE-SOC compression",
+ .type = V4L2_CTRL_TYPE_BOOLEAN,
+ .min = 0,
+ .max = 1,
+ .step = 1,
+ .def = 0,
+};
+
static int set_stream(struct v4l2_subdev *sd, int enable)
{
return 0;
{
v4l2_device_unregister_subdev(&csi2_be_soc->asd.sd);
ipu_isys_subdev_cleanup(&csi2_be_soc->asd);
+ v4l2_ctrl_handler_free(&csi2_be_soc->av.ctrl_handler);
ipu_isys_video_cleanup(&csi2_be_soc->av);
}
csi2_be_soc->av.aq.vbq.buf_struct_size =
sizeof(struct ipu_isys_video_buffer);
+ /* create v4l2 ctrl for be-soc video node */
+ rval = v4l2_ctrl_handler_init(&csi2_be_soc->av.ctrl_handler, 0);
+ if (rval) {
+ dev_err(&isys->adev->dev,
+ "failed to init v4l2 ctrl handler for be_soc\n");
+ goto fail;
+ }
+
+ csi2_be_soc->av.compression_ctrl =
+ v4l2_ctrl_new_custom(&csi2_be_soc->av.ctrl_handler,
+ &compression_ctrl_cfg, NULL);
+ if (!csi2_be_soc->av.compression_ctrl) {
+ dev_err(&isys->adev->dev,
+ "failed to create BE-SOC cmprs ctrl\n");
+ goto fail;
+ }
+ csi2_be_soc->av.compression = 0;
+ csi2_be_soc->av.vdev.ctrl_handler =
+ &csi2_be_soc->av.ctrl_handler;
+
rval = ipu_isys_video_init(&csi2_be_soc->av,
&csi2_be_soc->asd.sd.entity,
CSI2_BE_SOC_PAD_SOURCE,
static const struct v4l2_subdev_core_ops csi2_be_sd_core_ops = {
};
+static const struct v4l2_ctrl_config compression_ctrl_cfg = {
+ .ops = NULL,
+ .id = V4L2_CID_IPU_ISYS_COMPRESSION,
+ .name = "ISYS CSI-BE compression",
+ .type = V4L2_CTRL_TYPE_BOOLEAN,
+ .min = 0,
+ .max = 1,
+ .step = 1,
+ .def = 0,
+};
+
static int set_stream(struct v4l2_subdev *sd, int enable)
{
return 0;
void ipu_isys_csi2_be_cleanup(struct ipu_isys_csi2_be *csi2_be)
{
+ v4l2_ctrl_handler_free(&csi2_be->av.ctrl_handler);
v4l2_device_unregister_subdev(&csi2_be->asd.sd);
ipu_isys_subdev_cleanup(&csi2_be->asd);
ipu_isys_video_cleanup(&csi2_be->av);
csi2_be->av.aq.vbq.buf_struct_size =
sizeof(struct ipu_isys_video_buffer);
+ /* create v4l2 ctrl for csi-be video node */
+ rval = v4l2_ctrl_handler_init(&csi2_be->av.ctrl_handler, 0);
+ if (rval) {
+ dev_err(&isys->adev->dev,
+ "failed to init v4l2 ctrl handler for csi2_be\n");
+ goto fail;
+ }
+
+ csi2_be->av.compression_ctrl =
+ v4l2_ctrl_new_custom(&csi2_be->av.ctrl_handler,
+ &compression_ctrl_cfg, NULL);
+ if (!csi2_be->av.compression_ctrl) {
+ dev_err(&isys->adev->dev,
+ "failed to create CSI-BE cmprs ctrl\n");
+ goto fail;
+ }
+ csi2_be->av.compression = 0;
+ csi2_be->av.vdev.ctrl_handler = &csi2_be->av.ctrl_handler;
+
rval = ipu_isys_video_init(&csi2_be->av, &csi2_be->asd.sd.entity,
CSI2_BE_PAD_SOURCE, MEDIA_PAD_FL_SINK, 0);
if (rval) {
struct ipu_fw_isys_frame_buff_set_abi *set)
{
struct ipu_isys_queue *aq = vb2_queue_to_ipu_isys_queue(vb->vb2_queue);
+ struct ipu_isys_video *av = container_of(aq, struct ipu_isys_video, aq);
+
+ if (av->compression)
+ set->output_pins[aq->fw_output].compress = 1;
set->output_pins[aq->fw_output].addr =
vb2_dma_contig_plane_dma_addr(vb, 0);
if (rval)
goto out_power_down;
- rval = v4l2_pipeline_pm_use(&av->vdev.entity, 1);
+ rval = v4l2_pipeline_pm_get(&av->vdev.entity);
if (rval)
goto out_v4l2_fh_release;
out_lib_init:
isys->video_opened--;
mutex_unlock(&isys->mutex);
- v4l2_pipeline_pm_use(&av->vdev.entity, 0);
+ v4l2_pipeline_pm_put(&av->vdev.entity);
out_v4l2_fh_release:
v4l2_fh_release(file);
mutex_unlock(&av->isys->mutex);
- v4l2_pipeline_pm_use(&av->vdev.entity, 0);
+ v4l2_pipeline_pm_put(&av->vdev.entity);
if (av->isys->reset_needed)
pm_runtime_put_sync(&av->isys->adev->dev);
max(mpix->plane_fmt[0].bytesperline,
av->isys->pdata->ipdata->isys_dma_overshoot)), 1U);
+ if (av->compression_ctrl)
+ av->compression = v4l2_ctrl_g_ctrl(av->compression_ctrl);
+
+ /* overwrite bpl/height with compression alignment */
+ if (av->compression) {
+ u32 planar_tile_status_size, tile_status_size;
+
+ mpix->plane_fmt[0].bytesperline =
+ ALIGN(mpix->plane_fmt[0].bytesperline,
+ IPU_ISYS_COMPRESSION_LINE_ALIGN);
+ mpix->height = ALIGN(mpix->height,
+ IPU_ISYS_COMPRESSION_HEIGHT_ALIGN);
+
+ mpix->plane_fmt[0].sizeimage =
+ ALIGN(mpix->plane_fmt[0].bytesperline * mpix->height,
+ IPU_ISYS_COMPRESSION_PAGE_ALIGN);
+
+ /* ISYS compression only for RAW and single plannar */
+ planar_tile_status_size =
+ DIV_ROUND_UP_ULL((mpix->plane_fmt[0].bytesperline *
+ mpix->height /
+ IPU_ISYS_COMPRESSION_TILE_SIZE_BYTES) *
+ IPU_ISYS_COMPRESSION_TILE_STATUS_BITS,
+ BITS_PER_BYTE);
+ tile_status_size = ALIGN(planar_tile_status_size,
+ IPU_ISYS_COMPRESSION_PAGE_ALIGN);
+
+ /* tile status buffer offsets relative to buffer base address */
+ av->ts_offsets[0] = mpix->plane_fmt[0].sizeimage;
+ mpix->plane_fmt[0].sizeimage += tile_status_size;
+
+ dev_dbg(&av->isys->adev->dev,
+ "cmprs: bpl:%d, height:%d img size:%d, ts_sz:%d\n",
+ mpix->plane_fmt[0].bytesperline, mpix->height,
+ av->ts_offsets[0], tile_status_size);
+ }
+
memset(mpix->plane_fmt[0].reserved, 0,
sizeof(mpix->plane_fmt[0].reserved));
static void short_packet_queue_destroy(struct ipu_isys_pipeline *ip)
{
struct ipu_isys_video *av = container_of(ip, struct ipu_isys_video, ip);
- unsigned long attrs;
unsigned int i;
- attrs = DMA_ATTR_NON_CONSISTENT;
if (!ip->short_packet_bufs)
return;
for (i = 0; i < IPU_ISYS_SHORT_PACKET_BUFFER_NUM; i++) {
if (ip->short_packet_bufs[i].buffer)
- dma_free_attrs(&av->isys->adev->dev,
- ip->short_packet_buffer_size,
- ip->short_packet_bufs[i].buffer,
- ip->short_packet_bufs[i].dma_addr,
- attrs);
+ dma_free_noncoherent(&av->isys->adev->dev,
+ ip->short_packet_buffer_size,
+ ip->short_packet_bufs[i].buffer,
+ ip->short_packet_bufs[i].dma_addr,
+ DMA_BIDIRECTIONAL);
}
kfree(ip->short_packet_bufs);
ip->short_packet_bufs = NULL;
{
struct ipu_isys_video *av = container_of(ip, struct ipu_isys_video, ip);
struct v4l2_subdev_format source_fmt = { 0 };
- unsigned long attrs;
unsigned int i;
int rval;
size_t buf_size;
/* Initialize short packet queue. */
INIT_LIST_HEAD(&ip->short_packet_incoming);
INIT_LIST_HEAD(&ip->short_packet_active);
- attrs = DMA_ATTR_NON_CONSISTENT;
ip->short_packet_bufs =
kzalloc(sizeof(struct ipu_isys_private_buffer) *
buf->ip = ip;
buf->ib.type = IPU_ISYS_SHORT_PACKET_BUFFER;
buf->bytesused = buf_size;
- buf->buffer = dma_alloc_attrs(&av->isys->adev->dev, buf_size,
- &buf->dma_addr, GFP_KERNEL,
- attrs);
+ buf->buffer = dma_alloc_noncoherent(&av->isys->adev->dev,
+ buf_size,
+ &buf->dma_addr,
+ DMA_BIDIRECTIONAL,
+ GFP_KERNEL);
if (!buf->buffer) {
short_packet_queue_destroy(ip);
return -ENOMEM;
pin_info->snoopable = true;
pin_info->error_handling_enable = false;
break;
- /* snoopable sensor data to CPU */
- case IPU_FW_ISYS_PIN_TYPE_MIPI:
case IPU_FW_ISYS_PIN_TYPE_RAW_SOC:
+ if (av->compression) {
+ type_index = IPU_FW_ISYS_VC1_SENSOR_DATA;
+ pin_info->sensor_type
+ = isys->sensor_types[type_index]++;
+ pin_info->snoopable = false;
+ pin_info->error_handling_enable = false;
+ type = isys->sensor_types[type_index];
+ if (type > isys->sensor_info.vc1_data_end)
+ isys->sensor_types[type_index] =
+ isys->sensor_info.vc1_data_start;
+ } else {
+ type_index = IPU_FW_ISYS_VC0_SENSOR_DATA;
+ pin_info->sensor_type
+ = isys->sensor_types[type_index]++;
+ pin_info->snoopable = true;
+ pin_info->error_handling_enable = false;
+ type = isys->sensor_types[type_index];
+ if (type > isys->sensor_info.vc0_data_end)
+ isys->sensor_types[type_index] =
+ isys->sensor_info.vc0_data_start;
+ }
+ break;
+ case IPU_FW_ISYS_PIN_TYPE_MIPI:
type_index = IPU_FW_ISYS_VC0_SENSOR_DATA;
pin_info->sensor_type = isys->sensor_types[type_index]++;
pin_info->snoopable = true;
isys->sensor_info.vc0_data_start;
break;
+
default:
dev_err(&av->isys->adev->dev,
"Unknown pin type, use metadata type as default\n");
pin_info->snoopable = true;
pin_info->error_handling_enable = false;
}
+ if (av->compression) {
+ pin_info->payload_buf_size = av->mpix.plane_fmt[0].sizeimage;
+ pin_info->reserve_compression = av->compression;
+ pin_info->ts_offsets[0] = av->ts_offsets[0];
+ }
}
static unsigned int ipu_isys_get_compression_scheme(u32 code)
mutex_lock(&av->mutex);
- rval = video_register_device(&av->vdev, VFL_TYPE_GRABBER, -1);
+ rval = video_register_device(&av->vdev, VFL_TYPE_VIDEO, -1);
if (rval)
goto out_media_entity_cleanup;
struct ipu_isys_pipeline ip;
unsigned int streaming;
bool packed;
+ bool compression;
+ struct v4l2_ctrl_handler ctrl_handler;
+ struct v4l2_ctrl *compression_ctrl;
+ unsigned int ts_offsets[VIDEO_MAX_PLANES];
unsigned int line_header_length; /* bits */
unsigned int line_footer_length; /* bits */
rval = isys_notifier_init(isys);
if (rval)
goto out_isys_unregister_subdevices;
+
rval = v4l2_device_register_subdev_nodes(&isys->v4l2_dev);
if (rval)
goto out_isys_notifier_cleanup;
ipu_trace_restore(dev);
- pm_qos_update_request(&isys->pm_qos, ISYS_PM_QOS_VALUE);
+ cpu_latency_qos_update_request(&isys->pm_qos, ISYS_PM_QOS_VALUE);
ret = ipu_buttress_start_tsc_sync(isp);
if (ret)
isys->reset_needed = false;
mutex_unlock(&isys->mutex);
- pm_qos_update_request(&isys->pm_qos, PM_QOS_DEFAULT_VALUE);
+ cpu_latency_qos_update_request(&isys->pm_qos, PM_QOS_DEFAULT_VALUE);
ipu_mmu_hw_cleanup(adev->mmu);
ipu_trace_uninit(&adev->dev);
isys_notifier_cleanup(isys);
isys_unregister_devices(isys);
- pm_qos_remove_request(&isys->pm_qos);
+
+ cpu_latency_qos_remove_request(&isys->pm_qos);
if (!isp->secure_mode) {
ipu_cpd_free_pkg_dir(adev, isys->pkg_dir,
if (isys->short_packet_source == IPU_ISYS_SHORT_PACKET_FROM_TUNIT) {
u32 trace_size = IPU_ISYS_SHORT_PACKET_TRACE_BUFFER_SIZE;
- unsigned long attrs;
-
- attrs = DMA_ATTR_NON_CONSISTENT;
- dma_free_attrs(&adev->dev, trace_size,
- isys->short_packet_trace_buffer,
- isys->short_packet_trace_buffer_dma_addr, attrs);
+ dma_free_noncoherent(&adev->dev, trace_size,
+ isys->short_packet_trace_buffer,
+ isys->short_packet_trace_buffer_dma_addr,
+ DMA_BIDIRECTIONAL);
}
}
ipu_trace_init(adev->isp, isys->pdata->base, &adev->dev,
isys_trace_blocks);
- pm_qos_add_request(&isys->pm_qos, PM_QOS_CPU_DMA_LATENCY,
- PM_QOS_DEFAULT_VALUE);
+ cpu_latency_qos_add_request(&isys->pm_qos, PM_QOS_DEFAULT_VALUE);
alloc_fw_msg_bufs(isys, 20);
rval = isys_register_devices(isys);
}
EXPORT_SYMBOL(ipu_mmu_hw_init);
-struct ipu_mmu_info *ipu_mmu_alloc(struct ipu_device *isp)
+static struct ipu_mmu_info *ipu_mmu_alloc(struct ipu_device *isp)
{
struct ipu_mmu_info *mmu_info;
void *ptr;
<< ISP_PAGE_SHIFT;
}
-/**
+/*
* The following four functions are implemented based on iommu.c
* drivers/iommu/iommu.c/iommu_pgsize().
*/
if (compatible_arg) {
err = native_ioctl(file, cmd, (unsigned long)up);
} else {
- mm_segment_t old_fs = get_fs();
+ mm_segment_t old_fs = force_uaccess_begin();
- set_fs(KERNEL_DS);
err = native_ioctl(file, cmd, (unsigned long)&karg);
- set_fs(old_fs);
+ force_uaccess_end(old_fs);
}
if (err)
if (!pages)
goto free_sgt;
- down_read(¤t->mm->mmap_sem);
+ mmap_read_lock(current->mm);
vma = find_vma(current->mm, start);
if (!vma) {
ret = -EFAULT;
if (nr < npages)
goto error_up_read;
}
- up_read(¤t->mm->mmap_sem);
+ mmap_read_unlock(current->mm);
attach->pages = pages;
attach->npages = npages;
return 0;
error_up_read:
- up_read(¤t->mm->mmap_sem);
+ mmap_read_unlock(current->mm);
error:
if (!attach->vma_is_io)
while (nr > 0)
if (!ipu_attach || !ipu_attach->pages || !ipu_attach->npages)
return NULL;
- return vm_map_ram(ipu_attach->pages,
- ipu_attach->npages, 0, PAGE_KERNEL);
+ return vm_map_ram(ipu_attach->pages, ipu_attach->npages, 0);
}
static void ipu_dma_buf_vunmap(struct dma_buf *dmabuf, void *vaddr)
#include "ipu-platform-psys.h"
#define IPU_PSYS_PG_POOL_SIZE 16
-#define IPU_PSYS_PG_MAX_SIZE 2048
+#define IPU_PSYS_PG_MAX_SIZE 8192
#define IPU_MAX_PSYS_CMD_BUFFERS 32
#define IPU_PSYS_EVENT_CMD_COMPLETE IPU_FW_PSYS_EVENT_TYPE_SUCCESS
#define IPU_PSYS_EVENT_FRAGMENT_COMPLETE IPU_FW_PSYS_EVENT_TYPE_SUCCESS
if (!sys->memory.memory_buffer) {
sys->memory.memory_buffer =
- dma_alloc_attrs(dev, MEMORY_RING_BUFFER_SIZE +
- MEMORY_RING_BUFFER_GUARD,
- &sys->memory.dma_handle,
- GFP_KERNEL, DMA_ATTR_NON_CONSISTENT);
+ dma_alloc_noncoherent(dev,
+ MEMORY_RING_BUFFER_SIZE +
+ MEMORY_RING_BUFFER_GUARD,
+ &sys->memory.dma_handle,
+ DMA_BIDIRECTIONAL,
+ GFP_KERNEL);
}
if (!sys->memory.memory_buffer) {
mutex_lock(&trace->lock);
if (sys->memory.memory_buffer)
- dma_free_attrs(sys->dev,
- MEMORY_RING_BUFFER_SIZE +
- MEMORY_RING_BUFFER_GUARD,
- sys->memory.memory_buffer,
- sys->memory.dma_handle, DMA_ATTR_NON_CONSISTENT);
+ dma_free_noncoherent(sys->dev,
+ MEMORY_RING_BUFFER_SIZE + MEMORY_RING_BUFFER_GUARD,
+ sys->memory.memory_buffer,
+ sys->memory.dma_handle,
+ DMA_BIDIRECTIONAL);
sys->dev = NULL;
sys->memory.memory_buffer = NULL;
pdata->base = base;
pdata->ipdata = ipdata;
+ /* Use 250MHz for ipu6 se */
+ if (ipu_ver == IPU_VER_6SE)
+ ctrl->ratio = IPU6SE_IS_FREQ_CTL_DEFAULT_RATIO;
+
isys = ipu_bus_add_device(pdev, parent, pdata, ctrl,
IPU_ISYS_NAME, nr);
if (IS_ERR(isys))
return rval;
}
+ dma_set_max_seg_size(&pdev->dev, UINT_MAX);
+
rval = ipu_pci_config_setup(pdev);
if (rval)
return rval;
ipu6.o \
../ipu-fw-com.o
-obj-$(CONFIG_VIDEO_INTEL_IPU) += intel-ipu6.o
+obj-$(CONFIG_VIDEO_INTEL_IPU6) += intel-ipu6.o
intel-ipu6-isys-objs += ../ipu-isys.o \
../ipu-isys-csi2.o \
intel-ipu6-isys-objs += ../ipu-isys-tpg.o
endif
-obj-$(CONFIG_VIDEO_INTEL_IPU) += intel-ipu6-isys.o
+obj-$(CONFIG_VIDEO_INTEL_IPU6) += intel-ipu6-isys.o
intel-ipu6-psys-objs += ../ipu-psys.o \
ipu6-psys.o \
intel-ipu6-psys-objs += ../ipu-psys-compat32.o
endif
-obj-$(CONFIG_VIDEO_INTEL_IPU) += intel-ipu6-psys.o
+obj-$(CONFIG_VIDEO_INTEL_IPU6) += intel-ipu6-psys.o
ccflags-y += -I$(srcpath)/$(src)/../../../../../include/
ccflags-y += -I$(srcpath)/$(src)/../
#define IPU_BUTTRESS_PS_FREQ_CTL_DIVISOR_MASK 0xff
/* should be tuned for real silicon */
-#define IPU_IS_FREQ_CTL_DEFAULT_RATIO 0x08
-#define IPU_PS_FREQ_CTL_DEFAULT_RATIO 0x10
+#define IPU_IS_FREQ_CTL_DEFAULT_RATIO 0x08
+#define IPU6SE_IS_FREQ_CTL_DEFAULT_RATIO 0x0a
+#define IPU_PS_FREQ_CTL_DEFAULT_RATIO 0x10
#define IPU_IS_FREQ_CTL_DEFAULT_QOS_FLOOR_RATIO 0x10
#define IPU_PS_FREQ_CTL_DEFAULT_QOS_FLOOR_RATIO 0x0708
#define BUTTRESS_FREQ_CTL_START BIT(31)
#define BUTTRESS_FREQ_CTL_START_SHIFT 31
#define BUTTRESS_FREQ_CTL_QOS_FLOOR_SHIFT 8
+#define BUTTRESS_FREQ_CTL_ICCMAX_LEVEL (GENMASK(19, 16))
#define BUTTRESS_FREQ_CTL_QOS_FLOOR_MASK (0xff << 8)
#define BUTTRESS_REG_PWR_STATE 0x5c
IPU_ISYS_UNISPART_IRQ_CSI0 | \
IPU_ISYS_UNISPART_IRQ_CSI1)
+/* IPU6 ISYS compression alignment */
+#define IPU_ISYS_COMPRESSION_LINE_ALIGN 512
+#define IPU_ISYS_COMPRESSION_HEIGHT_ALIGN 1
+#define IPU_ISYS_COMPRESSION_TILE_SIZE_BYTES 512
+#define IPU_ISYS_COMPRESSION_PAGE_ALIGN 0x1000
+#define IPU_ISYS_COMPRESSION_TILE_STATUS_BITS 4
+#define IPU_ISYS_COMPRESSION_MAX 3
+
#endif
};
int ipu_psys_kcmd_start(struct ipu_psys *psys, struct ipu_psys_kcmd *kcmd);
-void ipu_psys_kcmd_complete(struct ipu_psys_ppg *kppg, struct ipu_psys_kcmd *kcmd,
+void ipu_psys_kcmd_complete(struct ipu_psys_ppg *kppg,
+ struct ipu_psys_kcmd *kcmd,
int error);
int ipu_psys_fh_init(struct ipu_psys_fh *fh);
int ipu_psys_fh_deinit(struct ipu_psys_fh *fh);
const u16 resource_req = pm->dev_chn_size[resource_id];
const u16 resource_offset_req = pm->dev_chn_offset[resource_id];
unsigned long retl;
- const struct ipu_fw_resource_definitions *res_defs;
if (resource_req <= 0)
return 0;
dev_err(dev, "out of resource handles\n");
return -ENOSPC;
}
- res_defs = get_res();
if (resource_offset_req != (u16)(-1))
retl = ipu_resource_alloc_with_pos
(resource,
/********** Generic resource handling **********/
-/*
- * Extension library gives byte offsets to its internal structures.
- * use those offsets to update fields. Without extension lib access
- * structures directly.
- */
-int ipu6_fw_psys_set_process_cell_id(struct ipu_fw_psys_process *ptr, u8 index,
- u8 value)
-{
- struct ipu_fw_psys_process_group *parent =
- (struct ipu_fw_psys_process_group *)((char *)ptr +
- ptr->parent_offset);
-
- ptr->cells[index] = value;
- parent->resource_bitmap |= 1 << value;
-
- return 0;
-}
-
int ipu6_fw_psys_set_proc_dev_chn(struct ipu_fw_psys_process *ptr, u16 offset,
u16 value)
{
u8 processes = pg->process_count;
u16 *process_offset_table = (u16 *)((char *)pg + pg->processes_offset);
unsigned int p, chn, mem, mem_id;
- int cell;
dev_dbg(&psys->adev->dev, "%s %s pgid %i has %i processes:\n",
__func__, note, pgid, processes);
struct ipu6_fw_psys_process_ext *pm_ext =
(struct ipu6_fw_psys_process_ext *)((u8 *)process
+ process->process_extension_offset);
- cell = process->cells[0];
dev_dbg(&psys->adev->dev, "\t process %i size=%u",
p, process->size);
if (!process->process_extension_offset)
IPU6SE_CSI_RX_ERROR_IRQ_MASK;
if (!enable) {
- ipu_isys_csi2_error(csi2);
+
writel(0, csi2->base + CSI_REG_CSI_FE_ENABLE);
writel(0, csi2->base + CSI_REG_PPI2CSI_ENABLE);
if (IS_ERR(file))
goto err;
- file = debugfs_create_u32("source", 0600, dir,
- &isys_gpcs->gpc[i].source);
- if (IS_ERR(file))
- goto err;
+ debugfs_create_u32("source", 0600, dir,
+ &isys_gpcs->gpc[i].source);
- file = debugfs_create_u32("route", 0600, dir,
- &isys_gpcs->gpc[i].route);
- if (IS_ERR(file))
- goto err;
+ debugfs_create_u32("route", 0600, dir,
+ &isys_gpcs->gpc[i].route);
- file = debugfs_create_u32("sense", 0600, dir,
- &isys_gpcs->gpc[i].sense);
- if (IS_ERR(file))
- goto err;
+ debugfs_create_u32("sense", 0600, dir,
+ &isys_gpcs->gpc[i].sense);
isys_gpcs->gpc[i].gpcindex = i;
isys_gpcs->gpc[i].prit = isys;
int ipu6_isys_phy_config(struct ipu_isys *isys)
{
- unsigned int phy_port, phy_id;
+ int phy_port;
+ unsigned int phy_id;
void __iomem *phy_base;
struct ipu_bus_device *adev = to_ipu_bus_device(&isys->adev->dev);
struct ipu_device *isp = adev->isp;
return 0;
}
-
-void __maybe_unused ipu6_isys_phy_dump_status(struct ipu_isys *isys,
- struct ipu_isys_csi2_config *cfg)
-{
- unsigned int port, phy_id, nlanes;
- struct ipu_bus_device *adev = to_ipu_bus_device(&isys->adev->dev);
- struct ipu_device *isp = adev->isp;
- void __iomem *isp_base = isp->base;
- void __iomem *cbbs1_base;
-
- port = cfg->port;
- phy_id = port / 4;
- nlanes = cfg->nlanes;
- cbbs1_base = isp_base + IPU6_ISYS_PHY_BASE(phy_id) + PHY_CBBS1_BASE;
-
- dev_dbg(&isys->adev->dev, "phy rcomp_status 0x%08x, cbb_status 0x%08x",
- readl(cbbs1_base + PHY_CBBS1_RCOMP_STATUS_REG_1),
- readl(cbbs1_base + PHY_CBBS1_CBB_STATUS_REG));
-
-}
static void ipu_psys_scheduler_ppg_sort(struct ipu_psys *psys, bool *stopping)
{
- struct ipu_psys_ppg *kppg;
+ struct ipu_psys_ppg *kppg, *tmp;
struct ipu_psys_scheduler *sched;
struct ipu_psys_fh *fh;
continue;
}
- list_for_each_entry(kppg, &sched->ppgs, list) {
+ list_for_each_entry_safe(kppg, tmp, &sched->ppgs, list) {
mutex_lock(&kppg->mutex);
if (kppg->state == PPG_STATE_START ||
kppg->state == PPG_STATE_RESUME) {
static void ipu_psys_scheduler_update_start_ppg_priority(void)
{
struct sched_list *sc_list = get_sc_list(SCHED_START_LIST);
- struct ipu_psys_ppg *kppg;
+ struct ipu_psys_ppg *kppg, *tmp;
mutex_lock(&sc_list->lock);
if (!list_empty(&sc_list->list))
- list_for_each_entry(kppg, &sc_list->list, sched_list)
+ list_for_each_entry_safe(kppg, tmp, &sc_list->list, sched_list)
kppg->pri_dynamic--;
mutex_unlock(&sc_list->lock);
}
static bool ipu_psys_scheduler_ppg_halt(struct ipu_psys *psys)
{
struct ipu_psys_scheduler *sched;
- struct ipu_psys_ppg *kppg;
+ struct ipu_psys_ppg *kppg, *tmp;
struct ipu_psys_fh *fh;
bool stopping_exit = false;
continue;
}
- list_for_each_entry(kppg, &sched->ppgs, list) {
+ list_for_each_entry_safe(kppg, tmp, &sched->ppgs, list) {
mutex_lock(&kppg->mutex);
if (kppg->state & PPG_STATE_STOP) {
ipu_psys_ppg_stop(kppg);
{
struct ipu_psys_kcmd *kcmd;
struct ipu_psys_scheduler *sched;
- struct ipu_psys_ppg *kppg;
+ struct ipu_psys_ppg *kppg, *tmp;
struct ipu_psys_fh *fh;
list_for_each_entry(fh, &psys->fhs, list) {
continue;
}
- list_for_each_entry(kppg, &sched->ppgs, list) {
+ list_for_each_entry_safe(kppg, tmp, &sched->ppgs, list) {
mutex_lock(&kppg->mutex);
if (list_empty(&kppg->kcmds_new_list)) {
mutex_unlock(&kppg->mutex);
static bool is_ready_to_enter_power_gating(struct ipu_psys *psys)
{
struct ipu_psys_scheduler *sched;
- struct ipu_psys_ppg *kppg;
+ struct ipu_psys_ppg *kppg, *tmp;
struct ipu_psys_fh *fh;
list_for_each_entry(fh, &psys->fhs, list) {
continue;
}
- list_for_each_entry(kppg, &sched->ppgs, list) {
+ list_for_each_entry_safe(kppg, tmp, &sched->ppgs, list) {
mutex_lock(&kppg->mutex);
if (!list_empty(&kppg->kcmds_new_list) ||
!list_empty(&kppg->kcmds_processing_list)) {
static bool has_pending_kcmd(struct ipu_psys *psys)
{
struct ipu_psys_scheduler *sched;
- struct ipu_psys_ppg *kppg;
+ struct ipu_psys_ppg *kppg, *tmp;
struct ipu_psys_fh *fh;
list_for_each_entry(fh, &psys->fhs, list) {
continue;
}
- list_for_each_entry(kppg, &sched->ppgs, list) {
+ list_for_each_entry_safe(kppg, tmp, &sched->ppgs, list) {
mutex_lock(&kppg->mutex);
if (!list_empty(&kppg->kcmds_new_list) ||
!list_empty(&kppg->kcmds_processing_list)) {
static bool ipu_psys_scheduler_enter_power_gating(struct ipu_psys *psys)
{
struct ipu_psys_scheduler *sched;
- struct ipu_psys_ppg *kppg;
+ struct ipu_psys_ppg *kppg, *tmp;
struct ipu_psys_fh *fh;
if (!enable_power_gating)
continue;
}
- list_for_each_entry(kppg, &sched->ppgs, list) {
+ list_for_each_entry_safe(kppg, tmp, &sched->ppgs, list) {
mutex_lock(&kppg->mutex);
if (kppg->state == PPG_STATE_RUNNING) {
kppg->state = PPG_STATE_SUSPEND;
{
struct ipu_psys *psys = kppg->fh->psys;
struct ipu_psys_buffer_set *kbuf_set;
- size_t buf_set_size;
unsigned int i;
int ret;
- buf_set_size = ipu_fw_psys_ppg_get_buffer_set_size(kcmd);
-
kbuf_set = ipu_psys_create_buffer_set(kcmd, kppg);
if (!kbuf_set) {
ret = -EINVAL;
mutex_lock(&kppg->mutex);
old_ppg_state = kppg->state;
if (kppg->state == PPG_STATE_STOPPING) {
- unsigned long flags;
struct ipu_psys_kcmd tmp_kcmd = {
.kpg = kppg->kpg,
};
queue_id = ipu_fw_psys_ppg_get_base_queue_id(&tmp_kcmd);
ipu_psys_free_cmd_queue_resource(&psys->resource_pool_running,
queue_id);
- spin_lock_irqsave(&psys->pgs_lock, flags);
- kppg->kpg->pg_size = 0;
- spin_unlock_irqrestore(&psys->pgs_lock, flags);
pm_runtime_put(&psys->adev->dev);
} else {
if (kppg->state == PPG_STATE_SUSPENDING) {
dev_err(&psys->adev->dev,
"ppg(%d) failed to resume\n", ppg_id);
} else if (kcmd != &kcmd_temp) {
- unsigned long flags;
-
ipu_psys_free_cmd_queue_resource(
&psys->resource_pool_running,
ipu_fw_psys_ppg_get_base_queue_id(kcmd));
ipu_psys_kcmd_complete(kppg, kcmd, 0);
- spin_lock_irqsave(&psys->pgs_lock, flags);
- kppg->kpg->pg_size = 0;
- spin_unlock_irqrestore(&psys->pgs_lock, flags);
dev_dbg(&psys->adev->dev,
"s_change:%s %p %d -> %d\n", __func__,
kppg, kppg->state, PPG_STATE_STOPPED);
pm_runtime_put(&psys->adev->dev);
kppg->state = PPG_STATE_STOPPED;
return 0;
+ } else {
+ return 0;
}
}
dev_dbg(&psys->adev->dev, "s_change:%s %p %d -> %d\n",
void ipu_psys_enter_power_gating(struct ipu_psys *psys)
{
struct ipu_psys_scheduler *sched;
- struct ipu_psys_ppg *kppg;
+ struct ipu_psys_ppg *kppg, *tmp;
struct ipu_psys_fh *fh;
int ret = 0;
continue;
}
- list_for_each_entry(kppg, &sched->ppgs, list) {
+ list_for_each_entry_safe(kppg, tmp, &sched->ppgs, list) {
mutex_lock(&kppg->mutex);
/* kppg has already power down */
if (kppg->state == PPG_STATE_STOPPED) {
void ipu_psys_exit_power_gating(struct ipu_psys *psys)
{
struct ipu_psys_scheduler *sched;
- struct ipu_psys_ppg *kppg;
+ struct ipu_psys_ppg *kppg, *tmp;
struct ipu_psys_fh *fh;
int ret = 0;
continue;
}
- list_for_each_entry(kppg, &sched->ppgs, list) {
+ list_for_each_entry_safe(kppg, tmp, &sched->ppgs, list) {
mutex_lock(&kppg->mutex);
/* kppg is not started and power up */
if (kppg->state == PPG_STATE_START ||
if (IS_ERR(file))
goto err;
- file = debugfs_create_u32("source", 0600, dir,
- &psys_gpcs->gpc[idx].source);
- if (IS_ERR(file))
- goto err;
+ debugfs_create_u32("source", 0600, dir,
+ &psys_gpcs->gpc[idx].source);
- file = debugfs_create_u32("route", 0600, dir,
- &psys_gpcs->gpc[idx].route);
- if (IS_ERR(file))
- goto err;
+ debugfs_create_u32("route", 0600, dir,
+ &psys_gpcs->gpc[idx].route);
- file = debugfs_create_u32("sense", 0600, dir,
- &psys_gpcs->gpc[idx].sense);
- if (IS_ERR(file))
- goto err;
+ debugfs_create_u32("sense", 0600, dir,
+ &psys_gpcs->gpc[idx].sense);
psys_gpcs->gpc[idx].gpcindex = idx;
psys_gpcs->gpc[idx].prit = psys;
static struct ipu_psys_ppg *ipu_psys_identify_kppg(struct ipu_psys_kcmd *kcmd)
{
struct ipu_psys_scheduler *sched = &kcmd->fh->sched;
- struct ipu_psys_ppg *kppg;
+ struct ipu_psys_ppg *kppg, *tmp;
mutex_lock(&kcmd->fh->mutex);
if (list_empty(&sched->ppgs))
goto not_found;
- list_for_each_entry(kppg, &sched->ppgs, list) {
+ list_for_each_entry_safe(kppg, tmp, &sched->ppgs, list) {
if (ipu_fw_psys_pg_get_token(kcmd)
!= kppg->token)
continue;
* Called to free up all resources associated with a kcmd.
* After this the kcmd doesn't anymore exist in the driver.
*/
-void ipu_psys_kcmd_free(struct ipu_psys_kcmd *kcmd)
+static void ipu_psys_kcmd_free(struct ipu_psys_kcmd *kcmd)
{
struct ipu_psys_ppg *kppg;
struct ipu_psys_scheduler *sched;
dma_addr_t pg_addr)
{
struct ipu_psys_scheduler *sched;
- struct ipu_psys_ppg *kppg;
+ struct ipu_psys_ppg *kppg, *tmp;
struct ipu_psys_fh *fh;
list_for_each_entry(fh, &psys->fhs, list) {
continue;
}
- list_for_each_entry(kppg, &sched->ppgs, list) {
+ list_for_each_entry_safe(kppg, tmp, &sched->ppgs, list) {
if (pg_addr != kppg->kpg->pg_dma_addr)
continue;
mutex_unlock(&fh->mutex);
id = ipu_fw_psys_ppg_get_base_queue_id(kcmd);
ipu_psys_free_cmd_queue_resource(rpr, id);
ipu_psys_kcmd_complete(kppg, kcmd, 0);
- spin_lock_irqsave(&psys->pgs_lock, flags);
- kppg->kpg->pg_size = 0;
- spin_unlock_irqrestore(&psys->pgs_lock, flags);
pm_runtime_put(&psys->adev->dev);
resche = false;
} else {
{
struct ipu_psys_fh *fh;
struct ipu_psys_kcmd *kcmd0;
- struct ipu_psys_ppg *kppg;
+ struct ipu_psys_ppg *kppg, *tmp;
struct ipu_psys_scheduler *sched;
list_for_each_entry(fh, &psys->fhs, list) {
mutex_unlock(&fh->mutex);
continue;
}
- list_for_each_entry(kppg, &sched->ppgs, list) {
+ list_for_each_entry_safe(kppg, tmp, &sched->ppgs, list) {
mutex_lock(&kppg->mutex);
list_for_each_entry(kcmd0,
&kppg->kcmds_processing_list,
mutex_lock(&fh->mutex);
if (!list_empty(&sched->ppgs)) {
list_for_each_entry_safe(kppg, kppg0, &sched->ppgs, list) {
- mutex_unlock(&fh->mutex);
+ unsigned long flags;
+
mutex_lock(&kppg->mutex);
if (!(kppg->state &
(PPG_STATE_STOPPED |
PPG_STATE_STOPPING))) {
- unsigned long flags;
struct ipu_psys_kcmd tmp = {
.kpg = kppg->kpg,
};
"s_change:%s %p %d -> %d\n", __func__,
kppg, kppg->state, PPG_STATE_STOPPED);
kppg->state = PPG_STATE_STOPPED;
- spin_lock_irqsave(&psys->pgs_lock, flags);
- kppg->kpg->pg_size = 0;
- spin_unlock_irqrestore(&psys->pgs_lock, flags);
if (psys->power_gating != PSYS_POWER_GATED)
pm_runtime_put(&psys->adev->dev);
}
+ list_del(&kppg->list);
mutex_unlock(&kppg->mutex);
list_for_each_entry_safe(kcmd, kcmd0,
&kppg->kcmds_new_list, list) {
kcmd->pg_user = NULL;
+ mutex_unlock(&fh->mutex);
ipu_psys_kcmd_free(kcmd);
+ mutex_lock(&fh->mutex);
}
list_for_each_entry_safe(kcmd, kcmd0,
&kppg->kcmds_processing_list,
list) {
kcmd->pg_user = NULL;
+ mutex_unlock(&fh->mutex);
ipu_psys_kcmd_free(kcmd);
+ mutex_lock(&fh->mutex);
}
list_for_each_entry_safe(kcmd, kcmd0,
&kppg->kcmds_finished_list,
list) {
kcmd->pg_user = NULL;
+ mutex_unlock(&fh->mutex);
ipu_psys_kcmd_free(kcmd);
+ mutex_lock(&fh->mutex);
}
- mutex_lock(&kppg->mutex);
- list_del(&kppg->list);
- mutex_unlock(&kppg->mutex);
+ spin_lock_irqsave(&psys->pgs_lock, flags);
+ kppg->kpg->pg_size = 0;
+ spin_unlock_irqrestore(&psys->pgs_lock, flags);
mutex_destroy(&kppg->mutex);
kfree(kppg->manifest);
kfree(kppg);
- mutex_lock(&fh->mutex);
}
}
mutex_unlock(&fh->mutex);
return 0;
}
-int ipu_buttress_isys_freq_get(void *data, u64 *val)
-{
- struct ipu_device *isp = data;
- u32 reg_val;
- int rval;
-
- rval = pm_runtime_get_sync(&isp->isys->dev);
- if (rval < 0) {
- pm_runtime_put(&isp->isys->dev);
- dev_err(&isp->pdev->dev, "Runtime PM failed (%d)\n", rval);
- return rval;
- }
-
- reg_val = readl(isp->base + BUTTRESS_REG_IS_FREQ_CTL);
-
- pm_runtime_put(&isp->isys->dev);
-
- *val = IPU_IS_FREQ_RATIO_BASE *
- (reg_val & IPU_BUTTRESS_IS_FREQ_CTL_DIVISOR_MASK);
-
- return 0;
-}
-
void ipu_internal_pdata_init(void)
{
if (ipu_ver == IPU_VER_6) {
u8 processes = pg->process_count;
u16 *process_offset_table = (u16 *)((char *)pg + pg->processes_offset);
unsigned int p, chn, mem, mem_id;
- int cell;
dev_dbg(&psys->adev->dev, "%s %s pgid %i has %i processes:\n",
__func__, note, pgid, processes);
struct ipu6se_fw_psys_process_ext *pm_ext =
(struct ipu6se_fw_psys_process_ext *)((u8 *)process
+ process->process_extension_offset);
- cell = process->cells[0];
dev_dbg(&psys->adev->dev, "\t process %i size=%u",
p, process->size);
if (!process->process_extension_offset)
#define V4L2_CID_IPU_BASE (V4L2_CID_USER_BASE + 0x1080)
#define V4L2_CID_IPU_STORE_CSI2_HEADER (V4L2_CID_IPU_BASE + 2)
+#define V4L2_CID_IPU_ISYS_COMPRESSION (V4L2_CID_IPU_BASE + 3)
#define VIDIOC_IPU_GET_DRIVER_VERSION \
_IOWR('v', BASE_VIDIOC_PRIVATE + 3, uint32_t)
projects / mirror_ubuntu-jammy-kernel.git / commitdiff