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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
522624f9 AL |
2 | #ifndef __SDHCI_PCI_H |
3 | #define __SDHCI_PCI_H | |
4 | ||
5 | /* | |
c949c907 | 6 | * PCI device IDs, sub IDs |
522624f9 AL |
7 | */ |
8 | ||
9 | #define PCI_DEVICE_ID_INTEL_PCH_SDIO0 0x8809 | |
10 | #define PCI_DEVICE_ID_INTEL_PCH_SDIO1 0x880a | |
11 | #define PCI_DEVICE_ID_INTEL_BYT_EMMC 0x0f14 | |
12 | #define PCI_DEVICE_ID_INTEL_BYT_SDIO 0x0f15 | |
13 | #define PCI_DEVICE_ID_INTEL_BYT_SD 0x0f16 | |
14 | #define PCI_DEVICE_ID_INTEL_BYT_EMMC2 0x0f50 | |
066173b6 AC |
15 | #define PCI_DEVICE_ID_INTEL_BSW_EMMC 0x2294 |
16 | #define PCI_DEVICE_ID_INTEL_BSW_SDIO 0x2295 | |
17 | #define PCI_DEVICE_ID_INTEL_BSW_SD 0x2296 | |
1f64cec2 | 18 | #define PCI_DEVICE_ID_INTEL_MRFLD_MMC 0x1190 |
522624f9 AL |
19 | #define PCI_DEVICE_ID_INTEL_CLV_SDIO0 0x08f9 |
20 | #define PCI_DEVICE_ID_INTEL_CLV_SDIO1 0x08fa | |
21 | #define PCI_DEVICE_ID_INTEL_CLV_SDIO2 0x08fb | |
22 | #define PCI_DEVICE_ID_INTEL_CLV_EMMC0 0x08e5 | |
23 | #define PCI_DEVICE_ID_INTEL_CLV_EMMC1 0x08e6 | |
43e968ce | 24 | #define PCI_DEVICE_ID_INTEL_QRK_SD 0x08A7 |
1f7f2652 AH |
25 | #define PCI_DEVICE_ID_INTEL_SPT_EMMC 0x9d2b |
26 | #define PCI_DEVICE_ID_INTEL_SPT_SDIO 0x9d2c | |
27 | #define PCI_DEVICE_ID_INTEL_SPT_SD 0x9d2d | |
06bf9c56 | 28 | #define PCI_DEVICE_ID_INTEL_DNV_EMMC 0x19db |
4fd4c065 AH |
29 | #define PCI_DEVICE_ID_INTEL_BXT_SD 0x0aca |
30 | #define PCI_DEVICE_ID_INTEL_BXT_EMMC 0x0acc | |
31 | #define PCI_DEVICE_ID_INTEL_BXT_SDIO 0x0ad0 | |
01d6b2a4 AH |
32 | #define PCI_DEVICE_ID_INTEL_BXTM_SD 0x1aca |
33 | #define PCI_DEVICE_ID_INTEL_BXTM_EMMC 0x1acc | |
34 | #define PCI_DEVICE_ID_INTEL_BXTM_SDIO 0x1ad0 | |
4fd4c065 AH |
35 | #define PCI_DEVICE_ID_INTEL_APL_SD 0x5aca |
36 | #define PCI_DEVICE_ID_INTEL_APL_EMMC 0x5acc | |
37 | #define PCI_DEVICE_ID_INTEL_APL_SDIO 0x5ad0 | |
2d1956d0 AH |
38 | #define PCI_DEVICE_ID_INTEL_GLK_SD 0x31ca |
39 | #define PCI_DEVICE_ID_INTEL_GLK_EMMC 0x31cc | |
40 | #define PCI_DEVICE_ID_INTEL_GLK_SDIO 0x31d0 | |
bc55dcd8 AH |
41 | #define PCI_DEVICE_ID_INTEL_CNP_EMMC 0x9dc4 |
42 | #define PCI_DEVICE_ID_INTEL_CNP_SD 0x9df5 | |
43 | #define PCI_DEVICE_ID_INTEL_CNPH_SD 0xa375 | |
522624f9 | 44 | |
c949c907 MK |
45 | #define PCI_DEVICE_ID_SYSKONNECT_8000 0x8000 |
46 | #define PCI_DEVICE_ID_VIA_95D0 0x95d0 | |
47 | #define PCI_DEVICE_ID_REALTEK_5250 0x5250 | |
48 | ||
49 | #define PCI_SUBDEVICE_ID_NI_7884 0x7884 | |
50 | ||
51 | /* | |
52 | * PCI device class and mask | |
53 | */ | |
54 | ||
55 | #define SYSTEM_SDHCI (PCI_CLASS_SYSTEM_SDHCI << 8) | |
56 | #define PCI_CLASS_MASK 0xFFFF00 | |
57 | ||
58 | /* | |
59 | * Macros for PCI device-description | |
60 | */ | |
61 | ||
62 | #define _PCI_VEND(vend) PCI_VENDOR_ID_##vend | |
63 | #define _PCI_DEV(vend, dev) PCI_DEVICE_ID_##vend##_##dev | |
64 | #define _PCI_SUBDEV(subvend, subdev) PCI_SUBDEVICE_ID_##subvend##_##subdev | |
65 | ||
66 | #define SDHCI_PCI_DEVICE(vend, dev, cfg) { \ | |
67 | .vendor = _PCI_VEND(vend), .device = _PCI_DEV(vend, dev), \ | |
68 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \ | |
69 | .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \ | |
70 | } | |
71 | ||
72 | #define SDHCI_PCI_SUBDEVICE(vend, dev, subvend, subdev, cfg) { \ | |
73 | .vendor = _PCI_VEND(vend), .device = _PCI_DEV(vend, dev), \ | |
74 | .subvendor = _PCI_VEND(subvend), \ | |
75 | .subdevice = _PCI_SUBDEV(subvend, subdev), \ | |
76 | .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \ | |
77 | } | |
78 | ||
79 | #define SDHCI_PCI_DEVICE_CLASS(vend, cl, cl_msk, cfg) { \ | |
80 | .vendor = _PCI_VEND(vend), .device = PCI_ANY_ID, \ | |
81 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \ | |
82 | .class = (cl), .class_mask = (cl_msk), \ | |
83 | .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \ | |
84 | } | |
85 | ||
522624f9 AL |
86 | /* |
87 | * PCI registers | |
88 | */ | |
89 | ||
90 | #define PCI_SDHCI_IFPIO 0x00 | |
91 | #define PCI_SDHCI_IFDMA 0x01 | |
92 | #define PCI_SDHCI_IFVENDOR 0x02 | |
93 | ||
94 | #define PCI_SLOT_INFO 0x40 /* 8 bits */ | |
95 | #define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7) | |
96 | #define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07 | |
97 | ||
98 | #define MAX_SLOTS 8 | |
99 | ||
100 | struct sdhci_pci_chip; | |
101 | struct sdhci_pci_slot; | |
102 | ||
103 | struct sdhci_pci_fixes { | |
104 | unsigned int quirks; | |
105 | unsigned int quirks2; | |
106 | bool allow_runtime_pm; | |
77a0122e | 107 | bool own_cd_for_runtime_pm; |
522624f9 AL |
108 | |
109 | int (*probe) (struct sdhci_pci_chip *); | |
110 | ||
111 | int (*probe_slot) (struct sdhci_pci_slot *); | |
61c951de | 112 | int (*add_host) (struct sdhci_pci_slot *); |
522624f9 AL |
113 | void (*remove_slot) (struct sdhci_pci_slot *, int); |
114 | ||
b7813f0f | 115 | #ifdef CONFIG_PM_SLEEP |
522624f9 AL |
116 | int (*suspend) (struct sdhci_pci_chip *); |
117 | int (*resume) (struct sdhci_pci_chip *); | |
b7813f0f | 118 | #endif |
966d696a AH |
119 | #ifdef CONFIG_PM |
120 | int (*runtime_suspend) (struct sdhci_pci_chip *); | |
121 | int (*runtime_resume) (struct sdhci_pci_chip *); | |
122 | #endif | |
6bc09063 AH |
123 | |
124 | const struct sdhci_ops *ops; | |
ac9f67b5 | 125 | size_t priv_size; |
522624f9 AL |
126 | }; |
127 | ||
128 | struct sdhci_pci_slot { | |
129 | struct sdhci_pci_chip *chip; | |
130 | struct sdhci_host *host; | |
131 | struct sdhci_pci_data *data; | |
132 | ||
522624f9 AL |
133 | int rst_n_gpio; |
134 | int cd_gpio; | |
135 | int cd_irq; | |
136 | ||
ff59c520 AH |
137 | int cd_idx; |
138 | bool cd_override_level; | |
139 | ||
522624f9 | 140 | void (*hw_reset)(struct sdhci_host *host); |
ac9f67b5 | 141 | unsigned long private[0] ____cacheline_aligned; |
522624f9 AL |
142 | }; |
143 | ||
144 | struct sdhci_pci_chip { | |
145 | struct pci_dev *pdev; | |
146 | ||
147 | unsigned int quirks; | |
148 | unsigned int quirks2; | |
149 | bool allow_runtime_pm; | |
d38dcad4 AH |
150 | bool pm_retune; |
151 | bool rpm_retune; | |
522624f9 AL |
152 | const struct sdhci_pci_fixes *fixes; |
153 | ||
154 | int num_slots; /* Slots on controller */ | |
155 | struct sdhci_pci_slot *slots[MAX_SLOTS]; /* Pointers to host slots */ | |
156 | }; | |
157 | ||
ac9f67b5 AH |
158 | static inline void *sdhci_pci_priv(struct sdhci_pci_slot *slot) |
159 | { | |
160 | return (void *)slot->private; | |
161 | } | |
162 | ||
30cf2803 AH |
163 | #ifdef CONFIG_PM_SLEEP |
164 | int sdhci_pci_resume_host(struct sdhci_pci_chip *chip); | |
165 | #endif | |
166 | ||
522624f9 | 167 | #endif /* __SDHCI_PCI_H */ |