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amd-xgbe: Fix initial mode when auto-negotiation is disabled
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / amd / xgbe / xgbe-mdio.c
CommitLineData
c5aa9e3b
LT		 1/*
2 * AMD 10Gb Ethernet driver
3 *
4 * This file is available to you under your choice of the following two
5 * licenses:
6 *
7 * License 1: GPLv2
8 *
9 * Copyright (c) 2014 Advanced Micro Devices, Inc.
10 *
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 *
24 * This file incorporates work covered by the following copyright and
25 * permission notice:
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
29 * and you.
30 *
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
40 *
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
43 *
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
55 *
56 *
57 * License 2: Modified BSD
58 *
59 * Copyright (c) 2014 Advanced Micro Devices, Inc.
60 * All rights reserved.
61 *
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions are met:
64 * * Redistributions of source code must retain the above copyright
65 * notice, this list of conditions and the following disclaimer.
66 * * Redistributions in binary form must reproduce the above copyright
67 * notice, this list of conditions and the following disclaimer in the
68 * documentation and/or other materials provided with the distribution.
69 * * Neither the name of Advanced Micro Devices, Inc. nor the
70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
72 *
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
83 *
84 * This file incorporates work covered by the following copyright and
85 * permission notice:
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
89 * and you.
90 *
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
100 *
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
103 *
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
115 */
116
117#include <linux/module.h>
118#include <linux/kmod.h>
c5aa9e3b
LT		 119#include <linux/mdio.h>
120#include <linux/phy.h>
121#include <linux/of.h>
7c12aa08
LT		 122#include <linux/bitops.h>
123#include <linux/jiffies.h>
c5aa9e3b
LT		 124
125#include "xgbe.h"
126#include "xgbe-common.h"
127
7c12aa08 128static void xgbe_an_enable_kr_training(struct xgbe_prv_data *pdata)
c5aa9e3b 129{
7c12aa08 130 unsigned int reg;
c5aa9e3b 131
7c12aa08 132 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
c5aa9e3b 133
7c12aa08
LT		 134 reg |= XGBE_KR_TRAINING_ENABLE;
135 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
136}
137
138static void xgbe_an_disable_kr_training(struct xgbe_prv_data *pdata)
139{
140 unsigned int reg;
141
142 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
143
144 reg &= ~XGBE_KR_TRAINING_ENABLE;
145 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
146}
147
148static void xgbe_pcs_power_cycle(struct xgbe_prv_data *pdata)
149{
150 unsigned int reg;
151
152 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
153
154 reg |= MDIO_CTRL1_LPOWER;
155 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
156
157 usleep_range(75, 100);
158
159 reg &= ~MDIO_CTRL1_LPOWER;
160 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
161}
162
163static void xgbe_serdes_start_ratechange(struct xgbe_prv_data *pdata)
164{
165 /* Assert Rx and Tx ratechange */
166 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, RATECHANGE, 1);
167}
168
169static void xgbe_serdes_complete_ratechange(struct xgbe_prv_data *pdata)
170{
171 unsigned int wait;
172 u16 status;
173
174 /* Release Rx and Tx ratechange */
175 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, RATECHANGE, 0);
176
177 /* Wait for Rx and Tx ready */
178 wait = XGBE_RATECHANGE_COUNT;
179 while (wait--) {
180 usleep_range(50, 75);
181
182 status = XSIR0_IOREAD(pdata, SIR0_STATUS);
183 if (XSIR_GET_BITS(status, SIR0_STATUS, RX_READY) &&
184 XSIR_GET_BITS(status, SIR0_STATUS, TX_READY))
185 goto rx_reset;
186 }
187
188 netdev_dbg(pdata->netdev, "SerDes rx/tx not ready (%#hx)\n",
189 status);
190
191rx_reset:
192 /* Perform Rx reset for the DFE changes */
193 XRXTX_IOWRITE_BITS(pdata, RXTX_REG6, RESETB_RXD, 0);
194 XRXTX_IOWRITE_BITS(pdata, RXTX_REG6, RESETB_RXD, 1);
195}
196
197static void xgbe_xgmii_mode(struct xgbe_prv_data *pdata)
198{
199 unsigned int reg;
200
201 /* Enable KR training */
202 xgbe_an_enable_kr_training(pdata);
203
204 /* Set MAC to 10G speed */
205 pdata->hw_if.set_xgmii_speed(pdata);
206
207 /* Set PCS to KR/10G speed */
208 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2);
209 reg &= ~MDIO_PCS_CTRL2_TYPE;
210 reg |= MDIO_PCS_CTRL2_10GBR;
211 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg);
212
213 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
214 reg &= ~MDIO_CTRL1_SPEEDSEL;
215 reg |= MDIO_CTRL1_SPEED10G;
216 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
217
218 xgbe_pcs_power_cycle(pdata);
219
220 /* Set SerDes to 10G speed */
221 xgbe_serdes_start_ratechange(pdata);
222
223 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, DATARATE, XGBE_SPEED_10000_RATE);
224 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, WORDMODE, XGBE_SPEED_10000_WORD);
225 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, PLLSEL, XGBE_SPEED_10000_PLL);
226
227 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, CDR_RATE,
228 pdata->serdes_cdr_rate[XGBE_SPEED_10000]);
229 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, TXAMP,
230 pdata->serdes_tx_amp[XGBE_SPEED_10000]);
231 XRXTX_IOWRITE_BITS(pdata, RXTX_REG20, BLWC_ENA,
232 pdata->serdes_blwc[XGBE_SPEED_10000]);
233 XRXTX_IOWRITE_BITS(pdata, RXTX_REG114, PQ_REG,
234 pdata->serdes_pq_skew[XGBE_SPEED_10000]);
235 XRXTX_IOWRITE_BITS(pdata, RXTX_REG129, RXDFE_CONFIG,
236 pdata->serdes_dfe_tap_cfg[XGBE_SPEED_10000]);
237 XRXTX_IOWRITE(pdata, RXTX_REG22,
238 pdata->serdes_dfe_tap_ena[XGBE_SPEED_10000]);
239
240 xgbe_serdes_complete_ratechange(pdata);
241}
242
243static void xgbe_gmii_2500_mode(struct xgbe_prv_data *pdata)
244{
245 unsigned int reg;
246
247 /* Disable KR training */
248 xgbe_an_disable_kr_training(pdata);
249
250 /* Set MAC to 2.5G speed */
251 pdata->hw_if.set_gmii_2500_speed(pdata);
252
253 /* Set PCS to KX/1G speed */
254 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2);
255 reg &= ~MDIO_PCS_CTRL2_TYPE;
256 reg |= MDIO_PCS_CTRL2_10GBX;
257 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg);
258
259 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
260 reg &= ~MDIO_CTRL1_SPEEDSEL;
261 reg |= MDIO_CTRL1_SPEED1G;
262 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
263
264 xgbe_pcs_power_cycle(pdata);
265
266 /* Set SerDes to 2.5G speed */
267 xgbe_serdes_start_ratechange(pdata);
268
269 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, DATARATE, XGBE_SPEED_2500_RATE);
270 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, WORDMODE, XGBE_SPEED_2500_WORD);
271 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, PLLSEL, XGBE_SPEED_2500_PLL);
272
273 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, CDR_RATE,
274 pdata->serdes_cdr_rate[XGBE_SPEED_2500]);
275 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, TXAMP,
276 pdata->serdes_tx_amp[XGBE_SPEED_2500]);
277 XRXTX_IOWRITE_BITS(pdata, RXTX_REG20, BLWC_ENA,
278 pdata->serdes_blwc[XGBE_SPEED_2500]);
279 XRXTX_IOWRITE_BITS(pdata, RXTX_REG114, PQ_REG,
280 pdata->serdes_pq_skew[XGBE_SPEED_2500]);
281 XRXTX_IOWRITE_BITS(pdata, RXTX_REG129, RXDFE_CONFIG,
282 pdata->serdes_dfe_tap_cfg[XGBE_SPEED_2500]);
283 XRXTX_IOWRITE(pdata, RXTX_REG22,
284 pdata->serdes_dfe_tap_ena[XGBE_SPEED_2500]);
285
286 xgbe_serdes_complete_ratechange(pdata);
287}
288
289static void xgbe_gmii_mode(struct xgbe_prv_data *pdata)
290{
291 unsigned int reg;
292
293 /* Disable KR training */
294 xgbe_an_disable_kr_training(pdata);
295
296 /* Set MAC to 1G speed */
297 pdata->hw_if.set_gmii_speed(pdata);
298
299 /* Set PCS to KX/1G speed */
300 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2);
301 reg &= ~MDIO_PCS_CTRL2_TYPE;
302 reg |= MDIO_PCS_CTRL2_10GBX;
303 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg);
304
305 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
306 reg &= ~MDIO_CTRL1_SPEEDSEL;
307 reg |= MDIO_CTRL1_SPEED1G;
308 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
309
310 xgbe_pcs_power_cycle(pdata);
311
312 /* Set SerDes to 1G speed */
313 xgbe_serdes_start_ratechange(pdata);
314
315 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, DATARATE, XGBE_SPEED_1000_RATE);
316 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, WORDMODE, XGBE_SPEED_1000_WORD);
317 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, PLLSEL, XGBE_SPEED_1000_PLL);
318
319 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, CDR_RATE,
320 pdata->serdes_cdr_rate[XGBE_SPEED_1000]);
321 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, TXAMP,
322 pdata->serdes_tx_amp[XGBE_SPEED_1000]);
323 XRXTX_IOWRITE_BITS(pdata, RXTX_REG20, BLWC_ENA,
324 pdata->serdes_blwc[XGBE_SPEED_1000]);
325 XRXTX_IOWRITE_BITS(pdata, RXTX_REG114, PQ_REG,
326 pdata->serdes_pq_skew[XGBE_SPEED_1000]);
327 XRXTX_IOWRITE_BITS(pdata, RXTX_REG129, RXDFE_CONFIG,
328 pdata->serdes_dfe_tap_cfg[XGBE_SPEED_1000]);
329 XRXTX_IOWRITE(pdata, RXTX_REG22,
330 pdata->serdes_dfe_tap_ena[XGBE_SPEED_1000]);
331
332 xgbe_serdes_complete_ratechange(pdata);
333}
334
335static void xgbe_cur_mode(struct xgbe_prv_data *pdata,
336 enum xgbe_mode *mode)
337{
338 unsigned int reg;
339
340 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2);
341 if ((reg & MDIO_PCS_CTRL2_TYPE) == MDIO_PCS_CTRL2_10GBR)
342 *mode = XGBE_MODE_KR;
343 else
344 *mode = XGBE_MODE_KX;
345}
346
347static bool xgbe_in_kr_mode(struct xgbe_prv_data *pdata)
348{
349 enum xgbe_mode mode;
350
351 xgbe_cur_mode(pdata, &mode);
352
353 return (mode == XGBE_MODE_KR);
354}
355
356static void xgbe_switch_mode(struct xgbe_prv_data *pdata)
357{
358 /* If we are in KR switch to KX, and vice-versa */
359 if (xgbe_in_kr_mode(pdata)) {
360 if (pdata->speed_set == XGBE_SPEEDSET_1000_10000)
361 xgbe_gmii_mode(pdata);
362 else
363 xgbe_gmii_2500_mode(pdata);
364 } else {
365 xgbe_xgmii_mode(pdata);
366 }
367}
368
369static void xgbe_set_mode(struct xgbe_prv_data *pdata,
370 enum xgbe_mode mode)
371{
372 enum xgbe_mode cur_mode;
373
374 xgbe_cur_mode(pdata, &cur_mode);
375 if (mode != cur_mode)
376 xgbe_switch_mode(pdata);
377}
378
471e14b2
LT		 379static bool xgbe_use_xgmii_mode(struct xgbe_prv_data *pdata)
380{
381 if (pdata->phy.autoneg == AUTONEG_ENABLE) {
382 if (pdata->phy.advertising & ADVERTISED_10000baseKR_Full)
383 return true;
384 } else {
385 if (pdata->phy.speed == SPEED_10000)
386 return true;
387 }
388
389 return false;
390}
391
392static bool xgbe_use_gmii_2500_mode(struct xgbe_prv_data *pdata)
393{
394 if (pdata->phy.autoneg == AUTONEG_ENABLE) {
395 if (pdata->phy.advertising & ADVERTISED_2500baseX_Full)
396 return true;
397 } else {
398 if (pdata->phy.speed == SPEED_2500)
399 return true;
400 }
401
402 return false;
403}
404
405static bool xgbe_use_gmii_mode(struct xgbe_prv_data *pdata)
406{
407 if (pdata->phy.autoneg == AUTONEG_ENABLE) {
408 if (pdata->phy.advertising & ADVERTISED_1000baseKX_Full)
409 return true;
410 } else {
411 if (pdata->phy.speed == SPEED_1000)
412 return true;
413 }
414
415 return false;
416}
417
7c12aa08
LT		 418static void xgbe_set_an(struct xgbe_prv_data *pdata, bool enable, bool restart)
419{
420 unsigned int reg;
421
422 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1);
423 reg &= ~MDIO_AN_CTRL1_ENABLE;
424
425 if (enable)
426 reg |= MDIO_AN_CTRL1_ENABLE;
427
428 if (restart)
429 reg |= MDIO_AN_CTRL1_RESTART;
430
431 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_CTRL1, reg);
432}
433
434static void xgbe_restart_an(struct xgbe_prv_data *pdata)
435{
436 xgbe_set_an(pdata, true, true);
437}
438
439static void xgbe_disable_an(struct xgbe_prv_data *pdata)
440{
441 xgbe_set_an(pdata, false, false);
442}
443
444static enum xgbe_an xgbe_an_tx_training(struct xgbe_prv_data *pdata,
445 enum xgbe_rx *state)
446{
447 unsigned int ad_reg, lp_reg, reg;
448
449 *state = XGBE_RX_COMPLETE;
450
451 /* If we're not in KR mode then we're done */
452 if (!xgbe_in_kr_mode(pdata))
453 return XGBE_AN_PAGE_RECEIVED;
454
455 /* Enable/Disable FEC */
456 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
457 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
458
459 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL);
460 reg &= ~(MDIO_PMA_10GBR_FECABLE_ABLE | MDIO_PMA_10GBR_FECABLE_ERRABLE);
461 if ((ad_reg & 0xc000) && (lp_reg & 0xc000))
462 reg |= pdata->fec_ability;
463
464 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL, reg);
465
466 /* Start KR training */
467 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
468 if (reg & XGBE_KR_TRAINING_ENABLE) {
469 XSIR0_IOWRITE_BITS(pdata, SIR0_KR_RT_1, RESET, 1);
470
471 reg |= XGBE_KR_TRAINING_START;
472 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL,
473 reg);
474
475 XSIR0_IOWRITE_BITS(pdata, SIR0_KR_RT_1, RESET, 0);
476 }
477
478 return XGBE_AN_PAGE_RECEIVED;
479}
480
481static enum xgbe_an xgbe_an_tx_xnp(struct xgbe_prv_data *pdata,
482 enum xgbe_rx *state)
483{
484 u16 msg;
485
486 *state = XGBE_RX_XNP;
487
488 msg = XGBE_XNP_MCF_NULL_MESSAGE;
489 msg |= XGBE_XNP_MP_FORMATTED;
490
491 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 2, 0);
492 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 1, 0);
493 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP, msg);
494
495 return XGBE_AN_PAGE_RECEIVED;
496}
497
498static enum xgbe_an xgbe_an_rx_bpa(struct xgbe_prv_data *pdata,
499 enum xgbe_rx *state)
500{
501 unsigned int link_support;
502 unsigned int reg, ad_reg, lp_reg;
503
504 /* Read Base Ability register 2 first */
505 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
506
507 /* Check for a supported mode, otherwise restart in a different one */
508 link_support = xgbe_in_kr_mode(pdata) ? 0x80 : 0x20;
509 if (!(reg & link_support))
510 return XGBE_AN_INCOMPAT_LINK;
511
512 /* Check Extended Next Page support */
513 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
514 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
515
516 return ((ad_reg & XGBE_XNP_NP_EXCHANGE) ||
517 (lp_reg & XGBE_XNP_NP_EXCHANGE))
518 ? xgbe_an_tx_xnp(pdata, state)
519 : xgbe_an_tx_training(pdata, state);
520}
521
522static enum xgbe_an xgbe_an_rx_xnp(struct xgbe_prv_data *pdata,
523 enum xgbe_rx *state)
524{
525 unsigned int ad_reg, lp_reg;
526
527 /* Check Extended Next Page support */
528 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_XNP);
529 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPX);
530
531 return ((ad_reg & XGBE_XNP_NP_EXCHANGE) ||
532 (lp_reg & XGBE_XNP_NP_EXCHANGE))
533 ? xgbe_an_tx_xnp(pdata, state)
534 : xgbe_an_tx_training(pdata, state);
535}
536
537static enum xgbe_an xgbe_an_page_received(struct xgbe_prv_data *pdata)
538{
539 enum xgbe_rx *state;
540 unsigned long an_timeout;
541 enum xgbe_an ret;
542
543 if (!pdata->an_start) {
544 pdata->an_start = jiffies;
545 } else {
546 an_timeout = pdata->an_start +
547 msecs_to_jiffies(XGBE_AN_MS_TIMEOUT);
548 if (time_after(jiffies, an_timeout)) {
549 /* Auto-negotiation timed out, reset state */
550 pdata->kr_state = XGBE_RX_BPA;
551 pdata->kx_state = XGBE_RX_BPA;
552
553 pdata->an_start = jiffies;
554 }
555 }
556
557 state = xgbe_in_kr_mode(pdata) ? &pdata->kr_state
558 : &pdata->kx_state;
559
560 switch (*state) {
561 case XGBE_RX_BPA:
562 ret = xgbe_an_rx_bpa(pdata, state);
563 break;
564
565 case XGBE_RX_XNP:
566 ret = xgbe_an_rx_xnp(pdata, state);
567 break;
568
569 default:
570 ret = XGBE_AN_ERROR;
571 }
572
573 return ret;
574}
575
576static enum xgbe_an xgbe_an_incompat_link(struct xgbe_prv_data *pdata)
577{
578 /* Be sure we aren't looping trying to negotiate */
579 if (xgbe_in_kr_mode(pdata)) {
580 pdata->kr_state = XGBE_RX_ERROR;
581
582 if (!(pdata->phy.advertising & ADVERTISED_1000baseKX_Full) &&
583 !(pdata->phy.advertising & ADVERTISED_2500baseX_Full))
584 return XGBE_AN_NO_LINK;
585
586 if (pdata->kx_state != XGBE_RX_BPA)
587 return XGBE_AN_NO_LINK;
588 } else {
589 pdata->kx_state = XGBE_RX_ERROR;
590
591 if (!(pdata->phy.advertising & ADVERTISED_10000baseKR_Full))
592 return XGBE_AN_NO_LINK;
593
594 if (pdata->kr_state != XGBE_RX_BPA)
595 return XGBE_AN_NO_LINK;
596 }
597
598 xgbe_disable_an(pdata);
599
600 xgbe_switch_mode(pdata);
601
602 xgbe_restart_an(pdata);
603
604 return XGBE_AN_INCOMPAT_LINK;
605}
606
607static irqreturn_t xgbe_an_isr(int irq, void *data)
608{
609 struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data;
610
611 /* Interrupt reason must be read and cleared outside of IRQ context */
612 disable_irq_nosync(pdata->an_irq);
613
614 queue_work(pdata->an_workqueue, &pdata->an_irq_work);
615
616 return IRQ_HANDLED;
617}
618
619static void xgbe_an_irq_work(struct work_struct *work)
620{
621 struct xgbe_prv_data *pdata = container_of(work,
622 struct xgbe_prv_data,
623 an_irq_work);
624
625 /* Avoid a race between enabling the IRQ and exiting the work by
626 * waiting for the work to finish and then queueing it
627 */
628 flush_work(&pdata->an_work);
629 queue_work(pdata->an_workqueue, &pdata->an_work);
630}
631
632static void xgbe_an_state_machine(struct work_struct *work)
633{
634 struct xgbe_prv_data *pdata = container_of(work,
635 struct xgbe_prv_data,
636 an_work);
637 enum xgbe_an cur_state = pdata->an_state;
638 unsigned int int_reg, int_mask;
639
640 mutex_lock(&pdata->an_mutex);
641
642 /* Read the interrupt */
643 int_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_INT);
644 if (!int_reg)
645 goto out;
646
647next_int:
648 if (int_reg & XGBE_AN_PG_RCV) {
649 pdata->an_state = XGBE_AN_PAGE_RECEIVED;
650 int_mask = XGBE_AN_PG_RCV;
651 } else if (int_reg & XGBE_AN_INC_LINK) {
652 pdata->an_state = XGBE_AN_INCOMPAT_LINK;
653 int_mask = XGBE_AN_INC_LINK;
654 } else if (int_reg & XGBE_AN_INT_CMPLT) {
655 pdata->an_state = XGBE_AN_COMPLETE;
656 int_mask = XGBE_AN_INT_CMPLT;
657 } else {
658 pdata->an_state = XGBE_AN_ERROR;
659 int_mask = 0;
660 }
661
662 /* Clear the interrupt to be processed */
663 int_reg &= ~int_mask;
664 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, int_reg);
665
666 pdata->an_result = pdata->an_state;
667
668again:
669 cur_state = pdata->an_state;
670
671 switch (pdata->an_state) {
672 case XGBE_AN_READY:
673 pdata->an_supported = 0;
674 break;
675
676 case XGBE_AN_PAGE_RECEIVED:
677 pdata->an_state = xgbe_an_page_received(pdata);
678 pdata->an_supported++;
679 break;
c5aa9e3b 680
7c12aa08
LT		 681 case XGBE_AN_INCOMPAT_LINK:
682 pdata->an_supported = 0;
683 pdata->parallel_detect = 0;
684 pdata->an_state = xgbe_an_incompat_link(pdata);
685 break;
c5aa9e3b 686
7c12aa08
LT		 687 case XGBE_AN_COMPLETE:
688 pdata->parallel_detect = pdata->an_supported ? 0 : 1;
689 netdev_dbg(pdata->netdev, "%s successful\n",
690 pdata->an_supported ? "Auto negotiation"
691 : "Parallel detection");
692 break;
693
694 case XGBE_AN_NO_LINK:
695 break;
696
697 default:
698 pdata->an_state = XGBE_AN_ERROR;
699 }
700
701 if (pdata->an_state == XGBE_AN_NO_LINK) {
702 int_reg = 0;
703 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0);
704 } else if (pdata->an_state == XGBE_AN_ERROR) {
705 netdev_err(pdata->netdev,
706 "error during auto-negotiation, state=%u\n",
707 cur_state);
708
709 int_reg = 0;
710 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0);
711 }
712
713 if (pdata->an_state >= XGBE_AN_COMPLETE) {
714 pdata->an_result = pdata->an_state;
715 pdata->an_state = XGBE_AN_READY;
716 pdata->kr_state = XGBE_RX_BPA;
717 pdata->kx_state = XGBE_RX_BPA;
718 pdata->an_start = 0;
719 }
720
721 if (cur_state != pdata->an_state)
722 goto again;
723
724 if (int_reg)
725 goto next_int;
726
727out:
728 enable_irq(pdata->an_irq);
729
730 mutex_unlock(&pdata->an_mutex);
c5aa9e3b
LT		 731}
732
7c12aa08 733static void xgbe_an_init(struct xgbe_prv_data *pdata)
c5aa9e3b 734{
7c12aa08
LT		 735 unsigned int reg;
736
737 /* Set up Advertisement register 3 first */
738 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
739 if (pdata->phy.advertising & ADVERTISED_10000baseR_FEC)
740 reg |= 0xc000;
741 else
742 reg &= ~0xc000;
743
744 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2, reg);
745
746 /* Set up Advertisement register 2 next */
747 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
748 if (pdata->phy.advertising & ADVERTISED_10000baseKR_Full)
749 reg |= 0x80;
750 else
751 reg &= ~0x80;
752
753 if ((pdata->phy.advertising & ADVERTISED_1000baseKX_Full) ||
754 (pdata->phy.advertising & ADVERTISED_2500baseX_Full))
755 reg |= 0x20;
756 else
757 reg &= ~0x20;
758
759 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1, reg);
c5aa9e3b 760
7c12aa08
LT		 761 /* Set up Advertisement register 1 last */
762 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
763 if (pdata->phy.advertising & ADVERTISED_Pause)
764 reg |= 0x400;
765 else
766 reg &= ~0x400;
c5aa9e3b 767
7c12aa08
LT		 768 if (pdata->phy.advertising & ADVERTISED_Asym_Pause)
769 reg |= 0x800;
770 else
771 reg &= ~0x800;
772
773 /* We don't intend to perform XNP */
774 reg &= ~XGBE_XNP_NP_EXCHANGE;
775
776 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE, reg);
777}
778
c1ce2f77
LT		 779static const char *xgbe_phy_fc_string(struct xgbe_prv_data *pdata)
780{
781 if (pdata->tx_pause && pdata->rx_pause)
782 return "rx/tx";
783 else if (pdata->rx_pause)
784 return "rx";
785 else if (pdata->tx_pause)
786 return "tx";
787 else
788 return "off";
789}
790
7c12aa08
LT		 791static const char *xgbe_phy_speed_string(int speed)
792{
793 switch (speed) {
794 case SPEED_1000:
795 return "1Gbps";
796 case SPEED_2500:
797 return "2.5Gbps";
798 case SPEED_10000:
799 return "10Gbps";
800 case SPEED_UNKNOWN:
801 return "Unknown";
802 default:
803 return "Unsupported";
804 }
805}
806
807static void xgbe_phy_print_status(struct xgbe_prv_data *pdata)
808{
809 if (pdata->phy.link)
810 netdev_info(pdata->netdev,
811 "Link is Up - %s/%s - flow control %s\n",
812 xgbe_phy_speed_string(pdata->phy.speed),
813 pdata->phy.duplex == DUPLEX_FULL ? "Full" : "Half",
c1ce2f77 814 xgbe_phy_fc_string(pdata));
7c12aa08
LT		 815 else
816 netdev_info(pdata->netdev, "Link is Down\n");
817}
818
819static void xgbe_phy_adjust_link(struct xgbe_prv_data *pdata)
820{
821 int new_state = 0;
822
823 if (pdata->phy.link) {
824 /* Flow control support */
c1ce2f77 825 pdata->pause_autoneg = pdata->phy.pause_autoneg;
7c12aa08 826
c1ce2f77
LT		 827 if (pdata->tx_pause != pdata->phy.tx_pause) {
828 new_state = 1;
7c12aa08 829 pdata->hw_if.config_tx_flow_control(pdata);
c1ce2f77 830 pdata->tx_pause = pdata->phy.tx_pause;
7c12aa08
LT		 831 }
832
c1ce2f77
LT		 833 if (pdata->rx_pause != pdata->phy.rx_pause) {
834 new_state = 1;
7c12aa08 835 pdata->hw_if.config_rx_flow_control(pdata);
c1ce2f77 836 pdata->rx_pause = pdata->phy.rx_pause;
7c12aa08
LT		 837 }
838
839 /* Speed support */
840 if (pdata->phy_speed != pdata->phy.speed) {
841 new_state = 1;
842 pdata->phy_speed = pdata->phy.speed;
843 }
844
845 if (pdata->phy_link != pdata->phy.link) {
846 new_state = 1;
847 pdata->phy_link = pdata->phy.link;
848 }
849 } else if (pdata->phy_link) {
850 new_state = 1;
851 pdata->phy_link = 0;
852 pdata->phy_speed = SPEED_UNKNOWN;
853 }
854
855 if (new_state && netif_msg_link(pdata))
856 xgbe_phy_print_status(pdata);
857}
858
859static int xgbe_phy_config_fixed(struct xgbe_prv_data *pdata)
860{
861 /* Disable auto-negotiation */
862 xgbe_disable_an(pdata);
863
864 /* Validate/Set specified speed */
865 switch (pdata->phy.speed) {
866 case SPEED_10000:
867 xgbe_set_mode(pdata, XGBE_MODE_KR);
868 break;
869
870 case SPEED_2500:
871 case SPEED_1000:
872 xgbe_set_mode(pdata, XGBE_MODE_KX);
873 break;
874
875 default:
876 return -EINVAL;
877 }
c5aa9e3b 878
7c12aa08
LT		 879 /* Validate duplex mode */
880 if (pdata->phy.duplex != DUPLEX_FULL)
881 return -EINVAL;
882
c5aa9e3b
LT		 883 return 0;
884}
885
7c12aa08
LT		 886static int __xgbe_phy_config_aneg(struct xgbe_prv_data *pdata)
887{
888 set_bit(XGBE_LINK_INIT, &pdata->dev_state);
889 pdata->link_check = jiffies;
890
891 if (pdata->phy.autoneg != AUTONEG_ENABLE)
892 return xgbe_phy_config_fixed(pdata);
893
894 /* Disable auto-negotiation interrupt */
895 disable_irq(pdata->an_irq);
896
897 /* Start auto-negotiation in a supported mode */
898 if (pdata->phy.advertising & ADVERTISED_10000baseKR_Full) {
899 xgbe_set_mode(pdata, XGBE_MODE_KR);
900 } else if ((pdata->phy.advertising & ADVERTISED_1000baseKX_Full) ||
901 (pdata->phy.advertising & ADVERTISED_2500baseX_Full)) {
902 xgbe_set_mode(pdata, XGBE_MODE_KX);
903 } else {
904 enable_irq(pdata->an_irq);
905 return -EINVAL;
906 }
907
908 /* Disable and stop any in progress auto-negotiation */
909 xgbe_disable_an(pdata);
910
911 /* Clear any auto-negotitation interrupts */
912 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0);
913
914 pdata->an_result = XGBE_AN_READY;
915 pdata->an_state = XGBE_AN_READY;
916 pdata->kr_state = XGBE_RX_BPA;
917 pdata->kx_state = XGBE_RX_BPA;
918
919 /* Re-enable auto-negotiation interrupt */
920 enable_irq(pdata->an_irq);
921
922 /* Set up advertisement registers based on current settings */
923 xgbe_an_init(pdata);
924
925 /* Enable and start auto-negotiation */
926 xgbe_restart_an(pdata);
927
928 return 0;
929}
930
931static int xgbe_phy_config_aneg(struct xgbe_prv_data *pdata)
932{
933 int ret;
934
935 mutex_lock(&pdata->an_mutex);
936
937 ret = __xgbe_phy_config_aneg(pdata);
938 if (ret)
939 set_bit(XGBE_LINK_ERR, &pdata->dev_state);
940 else
941 clear_bit(XGBE_LINK_ERR, &pdata->dev_state);
942
943 mutex_unlock(&pdata->an_mutex);
944
945 return ret;
946}
947
948static bool xgbe_phy_aneg_done(struct xgbe_prv_data *pdata)
949{
950 return (pdata->an_result == XGBE_AN_COMPLETE);
951}
952
953static void xgbe_check_link_timeout(struct xgbe_prv_data *pdata)
954{
955 unsigned long link_timeout;
956
957 link_timeout = pdata->link_check + (XGBE_LINK_TIMEOUT * HZ);
958 if (time_after(jiffies, link_timeout))
959 xgbe_phy_config_aneg(pdata);
960}
961
962static void xgbe_phy_status_force(struct xgbe_prv_data *pdata)
963{
964 if (xgbe_in_kr_mode(pdata)) {
965 pdata->phy.speed = SPEED_10000;
966 } else {
967 switch (pdata->speed_set) {
968 case XGBE_SPEEDSET_1000_10000:
969 pdata->phy.speed = SPEED_1000;
970 break;
971
972 case XGBE_SPEEDSET_2500_10000:
973 pdata->phy.speed = SPEED_2500;
974 break;
975 }
976 }
977 pdata->phy.duplex = DUPLEX_FULL;
7c12aa08
LT		 978}
979
980static void xgbe_phy_status_aneg(struct xgbe_prv_data *pdata)
981{
982 unsigned int ad_reg, lp_reg;
983
984 pdata->phy.lp_advertising = 0;
985
986 if ((pdata->phy.autoneg != AUTONEG_ENABLE) || pdata->parallel_detect)
987 return xgbe_phy_status_force(pdata);
988
989 pdata->phy.lp_advertising |= ADVERTISED_Autoneg;
990 pdata->phy.lp_advertising |= ADVERTISED_Backplane;
991
992 /* Compare Advertisement and Link Partner register 1 */
993 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
994 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
995 if (lp_reg & 0x400)
996 pdata->phy.lp_advertising |= ADVERTISED_Pause;
997 if (lp_reg & 0x800)
998 pdata->phy.lp_advertising |= ADVERTISED_Asym_Pause;
999
c1ce2f77
LT		 1000 if (pdata->phy.pause_autoneg) {
1001 /* Set flow control based on auto-negotiation result */
1002 pdata->phy.tx_pause = 0;
1003 pdata->phy.rx_pause = 0;
1004
1005 if (ad_reg & lp_reg & 0x400) {
1006 pdata->phy.tx_pause = 1;
1007 pdata->phy.rx_pause = 1;
1008 } else if (ad_reg & lp_reg & 0x800) {
1009 if (ad_reg & 0x400)
1010 pdata->phy.rx_pause = 1;
1011 else if (lp_reg & 0x400)
1012 pdata->phy.tx_pause = 1;
1013 }
1014 }
7c12aa08
LT		 1015
1016 /* Compare Advertisement and Link Partner register 2 */
1017 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
1018 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
1019 if (lp_reg & 0x80)
1020 pdata->phy.lp_advertising |= ADVERTISED_10000baseKR_Full;
1021 if (lp_reg & 0x20) {
1022 switch (pdata->speed_set) {
1023 case XGBE_SPEEDSET_1000_10000:
1024 pdata->phy.lp_advertising |= ADVERTISED_1000baseKX_Full;
1025 break;
1026 case XGBE_SPEEDSET_2500_10000:
1027 pdata->phy.lp_advertising |= ADVERTISED_2500baseX_Full;
1028 break;
1029 }
1030 }
1031
1032 ad_reg &= lp_reg;
1033 if (ad_reg & 0x80) {
1034 pdata->phy.speed = SPEED_10000;
1035 xgbe_set_mode(pdata, XGBE_MODE_KR);
1036 } else if (ad_reg & 0x20) {
1037 switch (pdata->speed_set) {
1038 case XGBE_SPEEDSET_1000_10000:
1039 pdata->phy.speed = SPEED_1000;
1040 break;
1041
1042 case XGBE_SPEEDSET_2500_10000:
1043 pdata->phy.speed = SPEED_2500;
1044 break;
1045 }
1046
1047 xgbe_set_mode(pdata, XGBE_MODE_KX);
1048 } else {
1049 pdata->phy.speed = SPEED_UNKNOWN;
1050 }
1051
1052 /* Compare Advertisement and Link Partner register 3 */
1053 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
1054 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
1055 if (lp_reg & 0xc000)
1056 pdata->phy.lp_advertising |= ADVERTISED_10000baseR_FEC;
1057
1058 pdata->phy.duplex = DUPLEX_FULL;
1059}
1060
1061static void xgbe_phy_status(struct xgbe_prv_data *pdata)
1062{
1063 unsigned int reg, link_aneg;
1064
1065 if (test_bit(XGBE_LINK_ERR, &pdata->dev_state)) {
1066 if (test_and_clear_bit(XGBE_LINK, &pdata->dev_state))
1067 netif_carrier_off(pdata->netdev);
1068
1069 pdata->phy.link = 0;
1070 goto adjust_link;
1071 }
1072
1073 link_aneg = (pdata->phy.autoneg == AUTONEG_ENABLE);
1074
1075 /* Get the link status. Link status is latched low, so read
1076 * once to clear and then read again to get current state
1077 */
1078 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
1079 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
1080 pdata->phy.link = (reg & MDIO_STAT1_LSTATUS) ? 1 : 0;
1081
1082 if (pdata->phy.link) {
1083 if (link_aneg && !xgbe_phy_aneg_done(pdata)) {
1084 xgbe_check_link_timeout(pdata);
1085 return;
1086 }
1087
1088 xgbe_phy_status_aneg(pdata);
1089
1090 if (test_bit(XGBE_LINK_INIT, &pdata->dev_state))
1091 clear_bit(XGBE_LINK_INIT, &pdata->dev_state);
1092
1093 if (!test_bit(XGBE_LINK, &pdata->dev_state)) {
1094 set_bit(XGBE_LINK, &pdata->dev_state);
1095 netif_carrier_on(pdata->netdev);
1096 }
1097 } else {
1098 if (test_bit(XGBE_LINK_INIT, &pdata->dev_state)) {
1099 xgbe_check_link_timeout(pdata);
1100
1101 if (link_aneg)
1102 return;
1103 }
1104
1105 xgbe_phy_status_aneg(pdata);
1106
1107 if (test_bit(XGBE_LINK, &pdata->dev_state)) {
1108 clear_bit(XGBE_LINK, &pdata->dev_state);
1109 netif_carrier_off(pdata->netdev);
1110 }
1111 }
1112
1113adjust_link:
1114 xgbe_phy_adjust_link(pdata);
1115}
1116
1117static void xgbe_phy_stop(struct xgbe_prv_data *pdata)
1118{
1119 /* Disable auto-negotiation */
1120 xgbe_disable_an(pdata);
1121
1122 /* Disable auto-negotiation interrupts */
1123 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 0);
1124
1125 devm_free_irq(pdata->dev, pdata->an_irq, pdata);
1126
1127 pdata->phy.link = 0;
1128 if (test_and_clear_bit(XGBE_LINK, &pdata->dev_state))
1129 netif_carrier_off(pdata->netdev);
1130
1131 xgbe_phy_adjust_link(pdata);
1132}
1133
1134static int xgbe_phy_start(struct xgbe_prv_data *pdata)
1135{
1136 struct net_device *netdev = pdata->netdev;
1137 int ret;
1138
1139 ret = devm_request_irq(pdata->dev, pdata->an_irq,
1140 xgbe_an_isr, 0, pdata->an_name,
1141 pdata);
1142 if (ret) {
1143 netdev_err(netdev, "phy irq request failed\n");
1144 return ret;
1145 }
1146
1147 /* Set initial mode - call the mode setting routines
1148 * directly to insure we are properly configured
1149 */
471e14b2 1150 if (xgbe_use_xgmii_mode(pdata)) {
7c12aa08 1151 xgbe_xgmii_mode(pdata);
471e14b2 1152 } else if (xgbe_use_gmii_mode(pdata)) {
7c12aa08 1153 xgbe_gmii_mode(pdata);
471e14b2 1154 } else if (xgbe_use_gmii_2500_mode(pdata)) {
7c12aa08
LT		 1155 xgbe_gmii_2500_mode(pdata);
1156 } else {
1157 ret = -EINVAL;
1158 goto err_irq;
1159 }
1160
1161 /* Set up advertisement registers based on current settings */
1162 xgbe_an_init(pdata);
1163
1164 /* Enable auto-negotiation interrupts */
1165 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 0x07);
1166
1167 return xgbe_phy_config_aneg(pdata);
1168
1169err_irq:
1170 devm_free_irq(pdata->dev, pdata->an_irq, pdata);
1171
1172 return ret;
1173}
1174
1175static int xgbe_phy_reset(struct xgbe_prv_data *pdata)
1176{
1177 unsigned int count, reg;
1178
1179 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
1180 reg |= MDIO_CTRL1_RESET;
1181 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
1182
1183 count = 50;
1184 do {
1185 msleep(20);
1186 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
1187 } while ((reg & MDIO_CTRL1_RESET) && --count);
1188
1189 if (reg & MDIO_CTRL1_RESET)
1190 return -ETIMEDOUT;
1191
1192 /* Disable auto-negotiation for now */
1193 xgbe_disable_an(pdata);
1194
1195 /* Clear auto-negotiation interrupts */
1196 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0);
1197
1198 return 0;
1199}
1200
1201static void xgbe_dump_phy_registers(struct xgbe_prv_data *pdata)
c5aa9e3b
LT		 1202{
1203 struct device *dev = pdata->dev;
c5aa9e3b 1204
34bf65df
LT		 1205 dev_dbg(dev, "\n************* PHY Reg dump **********************\n");
1206
1207 dev_dbg(dev, "PCS Control Reg (%#04x) = %#04x\n", MDIO_CTRL1,
1208 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1));
1209 dev_dbg(dev, "PCS Status Reg (%#04x) = %#04x\n", MDIO_STAT1,
1210 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1));
1211 dev_dbg(dev, "Phy Id (PHYS ID 1 %#04x)= %#04x\n", MDIO_DEVID1,
1212 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID1));
1213 dev_dbg(dev, "Phy Id (PHYS ID 2 %#04x)= %#04x\n", MDIO_DEVID2,
1214 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID2));
1215 dev_dbg(dev, "Devices in Package (%#04x)= %#04x\n", MDIO_DEVS1,
1216 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS1));
1217 dev_dbg(dev, "Devices in Package (%#04x)= %#04x\n", MDIO_DEVS2,
1218 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS2));
1219
1220 dev_dbg(dev, "Auto-Neg Control Reg (%#04x) = %#04x\n", MDIO_CTRL1,
1221 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1));
1222 dev_dbg(dev, "Auto-Neg Status Reg (%#04x) = %#04x\n", MDIO_STAT1,
1223 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_STAT1));
1224 dev_dbg(dev, "Auto-Neg Ad Reg 1 (%#04x) = %#04x\n",
1225 MDIO_AN_ADVERTISE,
1226 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE));
1227 dev_dbg(dev, "Auto-Neg Ad Reg 2 (%#04x) = %#04x\n",
1228 MDIO_AN_ADVERTISE + 1,
1229 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1));
1230 dev_dbg(dev, "Auto-Neg Ad Reg 3 (%#04x) = %#04x\n",
1231 MDIO_AN_ADVERTISE + 2,
1232 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2));
1233 dev_dbg(dev, "Auto-Neg Completion Reg (%#04x) = %#04x\n",
1234 MDIO_AN_COMP_STAT,
1235 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_COMP_STAT));
1236
34bf65df 1237 dev_dbg(dev, "\n*************************************************\n");
c5aa9e3b
LT		 1238}
1239
7c12aa08 1240static void xgbe_phy_init(struct xgbe_prv_data *pdata)
c5aa9e3b 1241{
7c12aa08
LT		 1242 mutex_init(&pdata->an_mutex);
1243 INIT_WORK(&pdata->an_irq_work, xgbe_an_irq_work);
1244 INIT_WORK(&pdata->an_work, xgbe_an_state_machine);
1245 pdata->mdio_mmd = MDIO_MMD_PCS;
c5aa9e3b 1246
7c12aa08
LT		 1247 /* Initialize supported features */
1248 pdata->phy.supported = SUPPORTED_Autoneg;
1249 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
1250 pdata->phy.supported |= SUPPORTED_Backplane;
1251 pdata->phy.supported |= SUPPORTED_10000baseKR_Full;
1252 switch (pdata->speed_set) {
1253 case XGBE_SPEEDSET_1000_10000:
1254 pdata->phy.supported |= SUPPORTED_1000baseKX_Full;
1255 break;
1256 case XGBE_SPEEDSET_2500_10000:
1257 pdata->phy.supported |= SUPPORTED_2500baseX_Full;
1258 break;
94c043e5 1259 }
c5aa9e3b 1260
7c12aa08
LT		 1261 pdata->fec_ability = XMDIO_READ(pdata, MDIO_MMD_PMAPMD,
1262 MDIO_PMA_10GBR_FECABLE);
1263 pdata->fec_ability &= (MDIO_PMA_10GBR_FECABLE_ABLE |
1264 MDIO_PMA_10GBR_FECABLE_ERRABLE);
1265 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
1266 pdata->phy.supported |= SUPPORTED_10000baseR_FEC;
c5aa9e3b 1267
7c12aa08 1268 pdata->phy.advertising = pdata->phy.supported;
c5aa9e3b 1269
7c12aa08 1270 pdata->phy.address = 0;
c5aa9e3b 1271
7c12aa08
LT		 1272 pdata->phy.autoneg = AUTONEG_ENABLE;
1273 pdata->phy.speed = SPEED_UNKNOWN;
1274 pdata->phy.duplex = DUPLEX_UNKNOWN;
c5aa9e3b 1275
7c12aa08 1276 pdata->phy.link = 0;
c5aa9e3b 1277
c1ce2f77
LT		 1278 pdata->phy.pause_autoneg = pdata->pause_autoneg;
1279 pdata->phy.tx_pause = pdata->tx_pause;
1280 pdata->phy.rx_pause = pdata->rx_pause;
1281
1282 /* Fix up Flow Control advertising */
1283 pdata->phy.advertising &= ~ADVERTISED_Pause;
1284 pdata->phy.advertising &= ~ADVERTISED_Asym_Pause;
1285
1286 if (pdata->rx_pause) {
1287 pdata->phy.advertising |= ADVERTISED_Pause;
1288 pdata->phy.advertising |= ADVERTISED_Asym_Pause;
1289 }
1290
1291 if (pdata->tx_pause)
1292 pdata->phy.advertising ^= ADVERTISED_Asym_Pause;
1293
34bf65df
LT		 1294 if (netif_msg_drv(pdata))
1295 xgbe_dump_phy_registers(pdata);
c5aa9e3b
LT		 1296}
1297
7c12aa08 1298void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *phy_if)
c5aa9e3b 1299{
7c12aa08 1300 phy_if->phy_init = xgbe_phy_init;
c5aa9e3b 1301
7c12aa08
LT		 1302 phy_if->phy_reset = xgbe_phy_reset;
1303 phy_if->phy_start = xgbe_phy_start;
1304 phy_if->phy_stop = xgbe_phy_stop;
c5aa9e3b 1305
7c12aa08
LT		 1306 phy_if->phy_status = xgbe_phy_status;
1307 phy_if->phy_config_aneg = xgbe_phy_config_aneg;
c5aa9e3b 1308}
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