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c5aa9e3b LT |
1 | /* |
2 | * AMD 10Gb Ethernet driver | |
3 | * | |
4 | * This file is available to you under your choice of the following two | |
5 | * licenses: | |
6 | * | |
7 | * License 1: GPLv2 | |
8 | * | |
ced3fcae | 9 | * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. |
c5aa9e3b LT |
10 | * |
11 | * This file is free software; you may copy, redistribute and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation, either version 2 of the License, or (at | |
14 | * your option) any later version. | |
15 | * | |
16 | * This file is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
19 | * General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
23 | * | |
24 | * This file incorporates work covered by the following copyright and | |
25 | * permission notice: | |
26 | * The Synopsys DWC ETHER XGMAC Software Driver and documentation | |
27 | * (hereinafter "Software") is an unsupported proprietary work of Synopsys, | |
28 | * Inc. unless otherwise expressly agreed to in writing between Synopsys | |
29 | * and you. | |
30 | * | |
31 | * The Software IS NOT an item of Licensed Software or Licensed Product | |
32 | * under any End User Software License Agreement or Agreement for Licensed | |
33 | * Product with Synopsys or any supplement thereto. Permission is hereby | |
34 | * granted, free of charge, to any person obtaining a copy of this software | |
35 | * annotated with this license and the Software, to deal in the Software | |
36 | * without restriction, including without limitation the rights to use, | |
37 | * copy, modify, merge, publish, distribute, sublicense, and/or sell copies | |
38 | * of the Software, and to permit persons to whom the Software is furnished | |
39 | * to do so, subject to the following conditions: | |
40 | * | |
41 | * The above copyright notice and this permission notice shall be included | |
42 | * in all copies or substantial portions of the Software. | |
43 | * | |
44 | * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" | |
45 | * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED | |
46 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A | |
47 | * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS | |
48 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
49 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
50 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
51 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
52 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
53 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF | |
54 | * THE POSSIBILITY OF SUCH DAMAGE. | |
55 | * | |
56 | * | |
57 | * License 2: Modified BSD | |
58 | * | |
ced3fcae | 59 | * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. |
c5aa9e3b LT |
60 | * All rights reserved. |
61 | * | |
62 | * Redistribution and use in source and binary forms, with or without | |
63 | * modification, are permitted provided that the following conditions are met: | |
64 | * * Redistributions of source code must retain the above copyright | |
65 | * notice, this list of conditions and the following disclaimer. | |
66 | * * Redistributions in binary form must reproduce the above copyright | |
67 | * notice, this list of conditions and the following disclaimer in the | |
68 | * documentation and/or other materials provided with the distribution. | |
69 | * * Neither the name of Advanced Micro Devices, Inc. nor the | |
70 | * names of its contributors may be used to endorse or promote products | |
71 | * derived from this software without specific prior written permission. | |
72 | * | |
73 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
74 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
75 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
76 | * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY | |
77 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
78 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
79 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
80 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
81 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
82 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
83 | * | |
84 | * This file incorporates work covered by the following copyright and | |
85 | * permission notice: | |
86 | * The Synopsys DWC ETHER XGMAC Software Driver and documentation | |
87 | * (hereinafter "Software") is an unsupported proprietary work of Synopsys, | |
88 | * Inc. unless otherwise expressly agreed to in writing between Synopsys | |
89 | * and you. | |
90 | * | |
91 | * The Software IS NOT an item of Licensed Software or Licensed Product | |
92 | * under any End User Software License Agreement or Agreement for Licensed | |
93 | * Product with Synopsys or any supplement thereto. Permission is hereby | |
94 | * granted, free of charge, to any person obtaining a copy of this software | |
95 | * annotated with this license and the Software, to deal in the Software | |
96 | * without restriction, including without limitation the rights to use, | |
97 | * copy, modify, merge, publish, distribute, sublicense, and/or sell copies | |
98 | * of the Software, and to permit persons to whom the Software is furnished | |
99 | * to do so, subject to the following conditions: | |
100 | * | |
101 | * The above copyright notice and this permission notice shall be included | |
102 | * in all copies or substantial portions of the Software. | |
103 | * | |
104 | * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" | |
105 | * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED | |
106 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A | |
107 | * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS | |
108 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
109 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
110 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
111 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
112 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
113 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF | |
114 | * THE POSSIBILITY OF SUCH DAMAGE. | |
115 | */ | |
116 | ||
282ccf6e | 117 | #include <linux/interrupt.h> |
c5aa9e3b LT |
118 | #include <linux/module.h> |
119 | #include <linux/kmod.h> | |
c5aa9e3b LT |
120 | #include <linux/mdio.h> |
121 | #include <linux/phy.h> | |
122 | #include <linux/of.h> | |
7c12aa08 LT |
123 | #include <linux/bitops.h> |
124 | #include <linux/jiffies.h> | |
c5aa9e3b LT |
125 | |
126 | #include "xgbe.h" | |
127 | #include "xgbe-common.h" | |
128 | ||
1bf40ada LT |
129 | static void xgbe_an37_clear_interrupts(struct xgbe_prv_data *pdata) |
130 | { | |
131 | int reg; | |
132 | ||
133 | reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT); | |
134 | reg &= ~XGBE_AN_CL37_INT_MASK; | |
135 | XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg); | |
136 | } | |
137 | ||
138 | static void xgbe_an37_disable_interrupts(struct xgbe_prv_data *pdata) | |
139 | { | |
140 | int reg; | |
141 | ||
142 | reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL); | |
143 | reg &= ~XGBE_AN_CL37_INT_MASK; | |
144 | XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg); | |
145 | ||
146 | reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL); | |
147 | reg &= ~XGBE_PCS_CL37_BP; | |
148 | XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL, reg); | |
149 | } | |
150 | ||
151 | static void xgbe_an37_enable_interrupts(struct xgbe_prv_data *pdata) | |
152 | { | |
153 | int reg; | |
154 | ||
155 | reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL); | |
156 | reg |= XGBE_PCS_CL37_BP; | |
157 | XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL, reg); | |
158 | ||
159 | reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL); | |
160 | reg |= XGBE_AN_CL37_INT_MASK; | |
161 | XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg); | |
162 | } | |
163 | ||
a64def41 LT |
164 | static void xgbe_an73_clear_interrupts(struct xgbe_prv_data *pdata) |
165 | { | |
166 | XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0); | |
167 | } | |
168 | ||
169 | static void xgbe_an73_disable_interrupts(struct xgbe_prv_data *pdata) | |
170 | { | |
171 | XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 0); | |
172 | } | |
173 | ||
174 | static void xgbe_an73_enable_interrupts(struct xgbe_prv_data *pdata) | |
175 | { | |
176 | XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, XGBE_AN_CL73_INT_MASK); | |
177 | } | |
178 | ||
179 | static void xgbe_an_enable_interrupts(struct xgbe_prv_data *pdata) | |
180 | { | |
181 | switch (pdata->an_mode) { | |
182 | case XGBE_AN_MODE_CL73: | |
d7445d1f | 183 | case XGBE_AN_MODE_CL73_REDRV: |
a64def41 LT |
184 | xgbe_an73_enable_interrupts(pdata); |
185 | break; | |
1bf40ada LT |
186 | case XGBE_AN_MODE_CL37: |
187 | case XGBE_AN_MODE_CL37_SGMII: | |
188 | xgbe_an37_enable_interrupts(pdata); | |
189 | break; | |
a64def41 LT |
190 | default: |
191 | break; | |
192 | } | |
193 | } | |
194 | ||
1bf40ada LT |
195 | static void xgbe_an_clear_interrupts_all(struct xgbe_prv_data *pdata) |
196 | { | |
197 | xgbe_an73_clear_interrupts(pdata); | |
198 | xgbe_an37_clear_interrupts(pdata); | |
199 | } | |
200 | ||
a64def41 | 201 | static void xgbe_an73_enable_kr_training(struct xgbe_prv_data *pdata) |
c5aa9e3b | 202 | { |
7c12aa08 | 203 | unsigned int reg; |
c5aa9e3b | 204 | |
7c12aa08 | 205 | reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL); |
c5aa9e3b | 206 | |
7c12aa08 LT |
207 | reg |= XGBE_KR_TRAINING_ENABLE; |
208 | XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg); | |
209 | } | |
210 | ||
a64def41 | 211 | static void xgbe_an73_disable_kr_training(struct xgbe_prv_data *pdata) |
7c12aa08 LT |
212 | { |
213 | unsigned int reg; | |
214 | ||
215 | reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL); | |
216 | ||
217 | reg &= ~XGBE_KR_TRAINING_ENABLE; | |
218 | XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg); | |
219 | } | |
220 | ||
e57f7a3f | 221 | static void xgbe_kr_mode(struct xgbe_prv_data *pdata) |
7c12aa08 | 222 | { |
7c12aa08 | 223 | /* Enable KR training */ |
a64def41 | 224 | xgbe_an73_enable_kr_training(pdata); |
7c12aa08 LT |
225 | |
226 | /* Set MAC to 10G speed */ | |
e57f7a3f LT |
227 | pdata->hw_if.set_speed(pdata, SPEED_10000); |
228 | ||
229 | /* Call PHY implementation support to complete rate change */ | |
230 | pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KR); | |
7c12aa08 LT |
231 | } |
232 | ||
e57f7a3f | 233 | static void xgbe_kx_2500_mode(struct xgbe_prv_data *pdata) |
7c12aa08 | 234 | { |
7c12aa08 | 235 | /* Disable KR training */ |
a64def41 | 236 | xgbe_an73_disable_kr_training(pdata); |
7c12aa08 LT |
237 | |
238 | /* Set MAC to 2.5G speed */ | |
e57f7a3f LT |
239 | pdata->hw_if.set_speed(pdata, SPEED_2500); |
240 | ||
241 | /* Call PHY implementation support to complete rate change */ | |
242 | pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KX_2500); | |
7c12aa08 LT |
243 | } |
244 | ||
e57f7a3f | 245 | static void xgbe_kx_1000_mode(struct xgbe_prv_data *pdata) |
7c12aa08 | 246 | { |
7c12aa08 | 247 | /* Disable KR training */ |
a64def41 | 248 | xgbe_an73_disable_kr_training(pdata); |
7c12aa08 LT |
249 | |
250 | /* Set MAC to 1G speed */ | |
e57f7a3f LT |
251 | pdata->hw_if.set_speed(pdata, SPEED_1000); |
252 | ||
253 | /* Call PHY implementation support to complete rate change */ | |
254 | pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KX_1000); | |
7c12aa08 LT |
255 | } |
256 | ||
abf0a1c2 LT |
257 | static void xgbe_sfi_mode(struct xgbe_prv_data *pdata) |
258 | { | |
d7445d1f LT |
259 | /* If a KR re-driver is present, change to KR mode instead */ |
260 | if (pdata->kr_redrv) | |
261 | return xgbe_kr_mode(pdata); | |
262 | ||
abf0a1c2 LT |
263 | /* Disable KR training */ |
264 | xgbe_an73_disable_kr_training(pdata); | |
265 | ||
266 | /* Set MAC to 10G speed */ | |
267 | pdata->hw_if.set_speed(pdata, SPEED_10000); | |
268 | ||
269 | /* Call PHY implementation support to complete rate change */ | |
270 | pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SFI); | |
271 | } | |
272 | ||
273 | static void xgbe_x_mode(struct xgbe_prv_data *pdata) | |
274 | { | |
275 | /* Disable KR training */ | |
276 | xgbe_an73_disable_kr_training(pdata); | |
277 | ||
278 | /* Set MAC to 1G speed */ | |
279 | pdata->hw_if.set_speed(pdata, SPEED_1000); | |
280 | ||
281 | /* Call PHY implementation support to complete rate change */ | |
282 | pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_X); | |
283 | } | |
284 | ||
285 | static void xgbe_sgmii_1000_mode(struct xgbe_prv_data *pdata) | |
286 | { | |
287 | /* Disable KR training */ | |
288 | xgbe_an73_disable_kr_training(pdata); | |
289 | ||
290 | /* Set MAC to 1G speed */ | |
291 | pdata->hw_if.set_speed(pdata, SPEED_1000); | |
292 | ||
293 | /* Call PHY implementation support to complete rate change */ | |
294 | pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SGMII_1000); | |
295 | } | |
296 | ||
297 | static void xgbe_sgmii_100_mode(struct xgbe_prv_data *pdata) | |
298 | { | |
299 | /* Disable KR training */ | |
300 | xgbe_an73_disable_kr_training(pdata); | |
301 | ||
302 | /* Set MAC to 1G speed */ | |
303 | pdata->hw_if.set_speed(pdata, SPEED_1000); | |
304 | ||
305 | /* Call PHY implementation support to complete rate change */ | |
306 | pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SGMII_100); | |
307 | } | |
308 | ||
e57f7a3f | 309 | static enum xgbe_mode xgbe_cur_mode(struct xgbe_prv_data *pdata) |
7c12aa08 | 310 | { |
e57f7a3f | 311 | return pdata->phy_if.phy_impl.cur_mode(pdata); |
7c12aa08 LT |
312 | } |
313 | ||
314 | static bool xgbe_in_kr_mode(struct xgbe_prv_data *pdata) | |
315 | { | |
e57f7a3f | 316 | return (xgbe_cur_mode(pdata) == XGBE_MODE_KR); |
7c12aa08 LT |
317 | } |
318 | ||
e57f7a3f LT |
319 | static void xgbe_change_mode(struct xgbe_prv_data *pdata, |
320 | enum xgbe_mode mode) | |
7c12aa08 | 321 | { |
e57f7a3f LT |
322 | switch (mode) { |
323 | case XGBE_MODE_KX_1000: | |
324 | xgbe_kx_1000_mode(pdata); | |
325 | break; | |
326 | case XGBE_MODE_KX_2500: | |
327 | xgbe_kx_2500_mode(pdata); | |
328 | break; | |
329 | case XGBE_MODE_KR: | |
330 | xgbe_kr_mode(pdata); | |
331 | break; | |
abf0a1c2 LT |
332 | case XGBE_MODE_SGMII_100: |
333 | xgbe_sgmii_100_mode(pdata); | |
334 | break; | |
335 | case XGBE_MODE_SGMII_1000: | |
336 | xgbe_sgmii_1000_mode(pdata); | |
337 | break; | |
338 | case XGBE_MODE_X: | |
339 | xgbe_x_mode(pdata); | |
340 | break; | |
341 | case XGBE_MODE_SFI: | |
342 | xgbe_sfi_mode(pdata); | |
343 | break; | |
e57f7a3f LT |
344 | case XGBE_MODE_UNKNOWN: |
345 | break; | |
346 | default: | |
347 | netif_dbg(pdata, link, pdata->netdev, | |
348 | "invalid operation mode requested (%u)\n", mode); | |
7c12aa08 LT |
349 | } |
350 | } | |
351 | ||
e57f7a3f | 352 | static void xgbe_switch_mode(struct xgbe_prv_data *pdata) |
471e14b2 | 353 | { |
e57f7a3f | 354 | xgbe_change_mode(pdata, pdata->phy_if.phy_impl.switch_mode(pdata)); |
471e14b2 LT |
355 | } |
356 | ||
e57f7a3f LT |
357 | static void xgbe_set_mode(struct xgbe_prv_data *pdata, |
358 | enum xgbe_mode mode) | |
471e14b2 | 359 | { |
e57f7a3f LT |
360 | if (mode == xgbe_cur_mode(pdata)) |
361 | return; | |
471e14b2 | 362 | |
e57f7a3f | 363 | xgbe_change_mode(pdata, mode); |
471e14b2 LT |
364 | } |
365 | ||
e57f7a3f LT |
366 | static bool xgbe_use_mode(struct xgbe_prv_data *pdata, |
367 | enum xgbe_mode mode) | |
471e14b2 | 368 | { |
e57f7a3f | 369 | return pdata->phy_if.phy_impl.use_mode(pdata, mode); |
471e14b2 LT |
370 | } |
371 | ||
1bf40ada LT |
372 | static void xgbe_an37_set(struct xgbe_prv_data *pdata, bool enable, |
373 | bool restart) | |
374 | { | |
375 | unsigned int reg; | |
376 | ||
377 | reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_CTRL1); | |
378 | reg &= ~MDIO_VEND2_CTRL1_AN_ENABLE; | |
379 | ||
380 | if (enable) | |
381 | reg |= MDIO_VEND2_CTRL1_AN_ENABLE; | |
382 | ||
383 | if (restart) | |
384 | reg |= MDIO_VEND2_CTRL1_AN_RESTART; | |
385 | ||
386 | XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_CTRL1, reg); | |
387 | } | |
388 | ||
389 | static void xgbe_an37_restart(struct xgbe_prv_data *pdata) | |
390 | { | |
391 | xgbe_an37_enable_interrupts(pdata); | |
392 | xgbe_an37_set(pdata, true, true); | |
393 | ||
394 | netif_dbg(pdata, link, pdata->netdev, "CL37 AN enabled/restarted\n"); | |
395 | } | |
396 | ||
397 | static void xgbe_an37_disable(struct xgbe_prv_data *pdata) | |
398 | { | |
399 | xgbe_an37_set(pdata, false, false); | |
400 | xgbe_an37_disable_interrupts(pdata); | |
401 | ||
402 | netif_dbg(pdata, link, pdata->netdev, "CL37 AN disabled\n"); | |
403 | } | |
404 | ||
a64def41 LT |
405 | static void xgbe_an73_set(struct xgbe_prv_data *pdata, bool enable, |
406 | bool restart) | |
7c12aa08 LT |
407 | { |
408 | unsigned int reg; | |
409 | ||
410 | reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1); | |
411 | reg &= ~MDIO_AN_CTRL1_ENABLE; | |
412 | ||
413 | if (enable) | |
414 | reg |= MDIO_AN_CTRL1_ENABLE; | |
415 | ||
416 | if (restart) | |
417 | reg |= MDIO_AN_CTRL1_RESTART; | |
418 | ||
419 | XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_CTRL1, reg); | |
420 | } | |
421 | ||
a64def41 | 422 | static void xgbe_an73_restart(struct xgbe_prv_data *pdata) |
7c12aa08 | 423 | { |
a64def41 LT |
424 | xgbe_an73_enable_interrupts(pdata); |
425 | xgbe_an73_set(pdata, true, true); | |
d5c78399 | 426 | |
a64def41 | 427 | netif_dbg(pdata, link, pdata->netdev, "CL73 AN enabled/restarted\n"); |
7c12aa08 LT |
428 | } |
429 | ||
a64def41 | 430 | static void xgbe_an73_disable(struct xgbe_prv_data *pdata) |
7c12aa08 | 431 | { |
a64def41 LT |
432 | xgbe_an73_set(pdata, false, false); |
433 | xgbe_an73_disable_interrupts(pdata); | |
d5c78399 | 434 | |
a64def41 | 435 | netif_dbg(pdata, link, pdata->netdev, "CL73 AN disabled\n"); |
7c12aa08 LT |
436 | } |
437 | ||
a64def41 LT |
438 | static void xgbe_an_restart(struct xgbe_prv_data *pdata) |
439 | { | |
440 | switch (pdata->an_mode) { | |
441 | case XGBE_AN_MODE_CL73: | |
d7445d1f | 442 | case XGBE_AN_MODE_CL73_REDRV: |
a64def41 LT |
443 | xgbe_an73_restart(pdata); |
444 | break; | |
1bf40ada LT |
445 | case XGBE_AN_MODE_CL37: |
446 | case XGBE_AN_MODE_CL37_SGMII: | |
447 | xgbe_an37_restart(pdata); | |
448 | break; | |
a64def41 LT |
449 | default: |
450 | break; | |
451 | } | |
452 | } | |
453 | ||
454 | static void xgbe_an_disable(struct xgbe_prv_data *pdata) | |
455 | { | |
456 | switch (pdata->an_mode) { | |
457 | case XGBE_AN_MODE_CL73: | |
d7445d1f | 458 | case XGBE_AN_MODE_CL73_REDRV: |
a64def41 LT |
459 | xgbe_an73_disable(pdata); |
460 | break; | |
1bf40ada LT |
461 | case XGBE_AN_MODE_CL37: |
462 | case XGBE_AN_MODE_CL37_SGMII: | |
463 | xgbe_an37_disable(pdata); | |
464 | break; | |
a64def41 LT |
465 | default: |
466 | break; | |
467 | } | |
468 | } | |
469 | ||
1bf40ada LT |
470 | static void xgbe_an_disable_all(struct xgbe_prv_data *pdata) |
471 | { | |
472 | xgbe_an73_disable(pdata); | |
473 | xgbe_an37_disable(pdata); | |
474 | } | |
475 | ||
a64def41 LT |
476 | static enum xgbe_an xgbe_an73_tx_training(struct xgbe_prv_data *pdata, |
477 | enum xgbe_rx *state) | |
7c12aa08 LT |
478 | { |
479 | unsigned int ad_reg, lp_reg, reg; | |
480 | ||
481 | *state = XGBE_RX_COMPLETE; | |
482 | ||
483 | /* If we're not in KR mode then we're done */ | |
484 | if (!xgbe_in_kr_mode(pdata)) | |
485 | return XGBE_AN_PAGE_RECEIVED; | |
486 | ||
487 | /* Enable/Disable FEC */ | |
488 | ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); | |
489 | lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); | |
490 | ||
491 | reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL); | |
492 | reg &= ~(MDIO_PMA_10GBR_FECABLE_ABLE | MDIO_PMA_10GBR_FECABLE_ERRABLE); | |
493 | if ((ad_reg & 0xc000) && (lp_reg & 0xc000)) | |
494 | reg |= pdata->fec_ability; | |
495 | ||
496 | XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL, reg); | |
497 | ||
498 | /* Start KR training */ | |
499 | reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL); | |
500 | if (reg & XGBE_KR_TRAINING_ENABLE) { | |
e57f7a3f LT |
501 | if (pdata->phy_if.phy_impl.kr_training_pre) |
502 | pdata->phy_if.phy_impl.kr_training_pre(pdata); | |
7c12aa08 LT |
503 | |
504 | reg |= XGBE_KR_TRAINING_START; | |
505 | XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, | |
506 | reg); | |
507 | ||
e57f7a3f LT |
508 | if (pdata->phy_if.phy_impl.kr_training_post) |
509 | pdata->phy_if.phy_impl.kr_training_post(pdata); | |
d5c78399 LT |
510 | |
511 | netif_dbg(pdata, link, pdata->netdev, | |
512 | "KR training initiated\n"); | |
7c12aa08 LT |
513 | } |
514 | ||
515 | return XGBE_AN_PAGE_RECEIVED; | |
516 | } | |
517 | ||
a64def41 LT |
518 | static enum xgbe_an xgbe_an73_tx_xnp(struct xgbe_prv_data *pdata, |
519 | enum xgbe_rx *state) | |
7c12aa08 LT |
520 | { |
521 | u16 msg; | |
522 | ||
523 | *state = XGBE_RX_XNP; | |
524 | ||
525 | msg = XGBE_XNP_MCF_NULL_MESSAGE; | |
526 | msg |= XGBE_XNP_MP_FORMATTED; | |
527 | ||
528 | XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 2, 0); | |
529 | XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 1, 0); | |
530 | XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP, msg); | |
531 | ||
532 | return XGBE_AN_PAGE_RECEIVED; | |
533 | } | |
534 | ||
a64def41 LT |
535 | static enum xgbe_an xgbe_an73_rx_bpa(struct xgbe_prv_data *pdata, |
536 | enum xgbe_rx *state) | |
7c12aa08 LT |
537 | { |
538 | unsigned int link_support; | |
539 | unsigned int reg, ad_reg, lp_reg; | |
540 | ||
541 | /* Read Base Ability register 2 first */ | |
542 | reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); | |
543 | ||
544 | /* Check for a supported mode, otherwise restart in a different one */ | |
545 | link_support = xgbe_in_kr_mode(pdata) ? 0x80 : 0x20; | |
546 | if (!(reg & link_support)) | |
547 | return XGBE_AN_INCOMPAT_LINK; | |
548 | ||
549 | /* Check Extended Next Page support */ | |
550 | ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); | |
551 | lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA); | |
552 | ||
553 | return ((ad_reg & XGBE_XNP_NP_EXCHANGE) || | |
554 | (lp_reg & XGBE_XNP_NP_EXCHANGE)) | |
a64def41 LT |
555 | ? xgbe_an73_tx_xnp(pdata, state) |
556 | : xgbe_an73_tx_training(pdata, state); | |
7c12aa08 LT |
557 | } |
558 | ||
a64def41 LT |
559 | static enum xgbe_an xgbe_an73_rx_xnp(struct xgbe_prv_data *pdata, |
560 | enum xgbe_rx *state) | |
7c12aa08 LT |
561 | { |
562 | unsigned int ad_reg, lp_reg; | |
563 | ||
564 | /* Check Extended Next Page support */ | |
565 | ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_XNP); | |
566 | lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPX); | |
567 | ||
568 | return ((ad_reg & XGBE_XNP_NP_EXCHANGE) || | |
569 | (lp_reg & XGBE_XNP_NP_EXCHANGE)) | |
a64def41 LT |
570 | ? xgbe_an73_tx_xnp(pdata, state) |
571 | : xgbe_an73_tx_training(pdata, state); | |
7c12aa08 LT |
572 | } |
573 | ||
a64def41 | 574 | static enum xgbe_an xgbe_an73_page_received(struct xgbe_prv_data *pdata) |
7c12aa08 LT |
575 | { |
576 | enum xgbe_rx *state; | |
577 | unsigned long an_timeout; | |
578 | enum xgbe_an ret; | |
579 | ||
580 | if (!pdata->an_start) { | |
581 | pdata->an_start = jiffies; | |
582 | } else { | |
583 | an_timeout = pdata->an_start + | |
584 | msecs_to_jiffies(XGBE_AN_MS_TIMEOUT); | |
585 | if (time_after(jiffies, an_timeout)) { | |
586 | /* Auto-negotiation timed out, reset state */ | |
587 | pdata->kr_state = XGBE_RX_BPA; | |
588 | pdata->kx_state = XGBE_RX_BPA; | |
589 | ||
590 | pdata->an_start = jiffies; | |
d5c78399 LT |
591 | |
592 | netif_dbg(pdata, link, pdata->netdev, | |
a64def41 | 593 | "CL73 AN timed out, resetting state\n"); |
7c12aa08 LT |
594 | } |
595 | } | |
596 | ||
597 | state = xgbe_in_kr_mode(pdata) ? &pdata->kr_state | |
e57f7a3f | 598 | : &pdata->kx_state; |
7c12aa08 LT |
599 | |
600 | switch (*state) { | |
601 | case XGBE_RX_BPA: | |
a64def41 | 602 | ret = xgbe_an73_rx_bpa(pdata, state); |
7c12aa08 LT |
603 | break; |
604 | ||
605 | case XGBE_RX_XNP: | |
a64def41 | 606 | ret = xgbe_an73_rx_xnp(pdata, state); |
7c12aa08 LT |
607 | break; |
608 | ||
609 | default: | |
610 | ret = XGBE_AN_ERROR; | |
611 | } | |
612 | ||
613 | return ret; | |
614 | } | |
615 | ||
a64def41 | 616 | static enum xgbe_an xgbe_an73_incompat_link(struct xgbe_prv_data *pdata) |
7c12aa08 LT |
617 | { |
618 | /* Be sure we aren't looping trying to negotiate */ | |
619 | if (xgbe_in_kr_mode(pdata)) { | |
620 | pdata->kr_state = XGBE_RX_ERROR; | |
621 | ||
622 | if (!(pdata->phy.advertising & ADVERTISED_1000baseKX_Full) && | |
623 | !(pdata->phy.advertising & ADVERTISED_2500baseX_Full)) | |
624 | return XGBE_AN_NO_LINK; | |
625 | ||
626 | if (pdata->kx_state != XGBE_RX_BPA) | |
627 | return XGBE_AN_NO_LINK; | |
628 | } else { | |
629 | pdata->kx_state = XGBE_RX_ERROR; | |
630 | ||
631 | if (!(pdata->phy.advertising & ADVERTISED_10000baseKR_Full)) | |
632 | return XGBE_AN_NO_LINK; | |
633 | ||
634 | if (pdata->kr_state != XGBE_RX_BPA) | |
635 | return XGBE_AN_NO_LINK; | |
636 | } | |
637 | ||
a64def41 | 638 | xgbe_an73_disable(pdata); |
7c12aa08 LT |
639 | |
640 | xgbe_switch_mode(pdata); | |
641 | ||
a64def41 | 642 | xgbe_an73_restart(pdata); |
7c12aa08 LT |
643 | |
644 | return XGBE_AN_INCOMPAT_LINK; | |
645 | } | |
646 | ||
1bf40ada LT |
647 | static void xgbe_an37_isr(struct xgbe_prv_data *pdata) |
648 | { | |
649 | unsigned int reg; | |
650 | ||
651 | /* Disable AN interrupts */ | |
652 | xgbe_an37_disable_interrupts(pdata); | |
653 | ||
654 | /* Save the interrupt(s) that fired */ | |
655 | reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT); | |
656 | pdata->an_int = reg & XGBE_AN_CL37_INT_MASK; | |
657 | pdata->an_status = reg & ~XGBE_AN_CL37_INT_MASK; | |
658 | ||
659 | if (pdata->an_int) { | |
660 | /* Clear the interrupt(s) that fired and process them */ | |
661 | reg &= ~XGBE_AN_CL37_INT_MASK; | |
662 | XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg); | |
663 | ||
664 | queue_work(pdata->an_workqueue, &pdata->an_irq_work); | |
665 | } else { | |
666 | /* Enable AN interrupts */ | |
667 | xgbe_an37_enable_interrupts(pdata); | |
85b85c85 LT |
668 | |
669 | /* Reissue interrupt if status is not clear */ | |
670 | if (pdata->vdata->irq_reissue_support) | |
671 | XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 3); | |
1bf40ada LT |
672 | } |
673 | } | |
674 | ||
a64def41 | 675 | static void xgbe_an73_isr(struct xgbe_prv_data *pdata) |
7c12aa08 | 676 | { |
ced3fcae | 677 | /* Disable AN interrupts */ |
a64def41 | 678 | xgbe_an73_disable_interrupts(pdata); |
7c12aa08 | 679 | |
ced3fcae LT |
680 | /* Save the interrupt(s) that fired */ |
681 | pdata->an_int = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_INT); | |
682 | ||
683 | if (pdata->an_int) { | |
684 | /* Clear the interrupt(s) that fired and process them */ | |
685 | XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, ~pdata->an_int); | |
686 | ||
687 | queue_work(pdata->an_workqueue, &pdata->an_irq_work); | |
688 | } else { | |
689 | /* Enable AN interrupts */ | |
a64def41 | 690 | xgbe_an73_enable_interrupts(pdata); |
85b85c85 LT |
691 | |
692 | /* Reissue interrupt if status is not clear */ | |
693 | if (pdata->vdata->irq_reissue_support) | |
694 | XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 3); | |
a64def41 LT |
695 | } |
696 | } | |
697 | ||
85b85c85 | 698 | static void xgbe_an_isr_task(unsigned long data) |
a64def41 LT |
699 | { |
700 | struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data; | |
701 | ||
702 | netif_dbg(pdata, intr, pdata->netdev, "AN interrupt received\n"); | |
703 | ||
704 | switch (pdata->an_mode) { | |
705 | case XGBE_AN_MODE_CL73: | |
d7445d1f | 706 | case XGBE_AN_MODE_CL73_REDRV: |
a64def41 LT |
707 | xgbe_an73_isr(pdata); |
708 | break; | |
1bf40ada LT |
709 | case XGBE_AN_MODE_CL37: |
710 | case XGBE_AN_MODE_CL37_SGMII: | |
711 | xgbe_an37_isr(pdata); | |
712 | break; | |
a64def41 LT |
713 | default: |
714 | break; | |
ced3fcae | 715 | } |
85b85c85 LT |
716 | } |
717 | ||
718 | static irqreturn_t xgbe_an_isr(int irq, void *data) | |
719 | { | |
720 | struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data; | |
721 | ||
722 | if (pdata->isr_as_tasklet) | |
723 | tasklet_schedule(&pdata->tasklet_an); | |
724 | else | |
725 | xgbe_an_isr_task((unsigned long)pdata); | |
7c12aa08 LT |
726 | |
727 | return IRQ_HANDLED; | |
728 | } | |
729 | ||
85b85c85 | 730 | static irqreturn_t xgbe_an_combined_isr(struct xgbe_prv_data *pdata) |
47f164de | 731 | { |
85b85c85 LT |
732 | xgbe_an_isr_task((unsigned long)pdata); |
733 | ||
734 | return IRQ_HANDLED; | |
47f164de LT |
735 | } |
736 | ||
7c12aa08 LT |
737 | static void xgbe_an_irq_work(struct work_struct *work) |
738 | { | |
739 | struct xgbe_prv_data *pdata = container_of(work, | |
740 | struct xgbe_prv_data, | |
741 | an_irq_work); | |
742 | ||
743 | /* Avoid a race between enabling the IRQ and exiting the work by | |
744 | * waiting for the work to finish and then queueing it | |
745 | */ | |
746 | flush_work(&pdata->an_work); | |
747 | queue_work(pdata->an_workqueue, &pdata->an_work); | |
748 | } | |
749 | ||
d5c78399 LT |
750 | static const char *xgbe_state_as_string(enum xgbe_an state) |
751 | { | |
752 | switch (state) { | |
753 | case XGBE_AN_READY: | |
754 | return "Ready"; | |
755 | case XGBE_AN_PAGE_RECEIVED: | |
756 | return "Page-Received"; | |
757 | case XGBE_AN_INCOMPAT_LINK: | |
758 | return "Incompatible-Link"; | |
759 | case XGBE_AN_COMPLETE: | |
760 | return "Complete"; | |
761 | case XGBE_AN_NO_LINK: | |
762 | return "No-Link"; | |
763 | case XGBE_AN_ERROR: | |
764 | return "Error"; | |
765 | default: | |
766 | return "Undefined"; | |
767 | } | |
768 | } | |
769 | ||
1bf40ada LT |
770 | static void xgbe_an37_state_machine(struct xgbe_prv_data *pdata) |
771 | { | |
772 | enum xgbe_an cur_state = pdata->an_state; | |
773 | ||
774 | if (!pdata->an_int) | |
775 | return; | |
776 | ||
777 | if (pdata->an_int & XGBE_AN_CL37_INT_CMPLT) { | |
778 | pdata->an_state = XGBE_AN_COMPLETE; | |
779 | pdata->an_int &= ~XGBE_AN_CL37_INT_CMPLT; | |
780 | ||
781 | /* If SGMII is enabled, check the link status */ | |
782 | if ((pdata->an_mode == XGBE_AN_MODE_CL37_SGMII) && | |
783 | !(pdata->an_status & XGBE_SGMII_AN_LINK_STATUS)) | |
784 | pdata->an_state = XGBE_AN_NO_LINK; | |
785 | } | |
786 | ||
787 | netif_dbg(pdata, link, pdata->netdev, "CL37 AN %s\n", | |
788 | xgbe_state_as_string(pdata->an_state)); | |
789 | ||
790 | cur_state = pdata->an_state; | |
791 | ||
792 | switch (pdata->an_state) { | |
793 | case XGBE_AN_READY: | |
794 | break; | |
795 | ||
796 | case XGBE_AN_COMPLETE: | |
797 | netif_dbg(pdata, link, pdata->netdev, | |
798 | "Auto negotiation successful\n"); | |
799 | break; | |
800 | ||
801 | case XGBE_AN_NO_LINK: | |
802 | break; | |
803 | ||
804 | default: | |
805 | pdata->an_state = XGBE_AN_ERROR; | |
806 | } | |
807 | ||
808 | if (pdata->an_state == XGBE_AN_ERROR) { | |
809 | netdev_err(pdata->netdev, | |
810 | "error during auto-negotiation, state=%u\n", | |
811 | cur_state); | |
812 | ||
813 | pdata->an_int = 0; | |
814 | xgbe_an37_clear_interrupts(pdata); | |
815 | } | |
816 | ||
817 | if (pdata->an_state >= XGBE_AN_COMPLETE) { | |
818 | pdata->an_result = pdata->an_state; | |
819 | pdata->an_state = XGBE_AN_READY; | |
820 | ||
821 | netif_dbg(pdata, link, pdata->netdev, "CL37 AN result: %s\n", | |
822 | xgbe_state_as_string(pdata->an_result)); | |
823 | } | |
824 | ||
825 | xgbe_an37_enable_interrupts(pdata); | |
826 | } | |
827 | ||
a64def41 | 828 | static void xgbe_an73_state_machine(struct xgbe_prv_data *pdata) |
7c12aa08 | 829 | { |
7c12aa08 | 830 | enum xgbe_an cur_state = pdata->an_state; |
7c12aa08 | 831 | |
ced3fcae | 832 | if (!pdata->an_int) |
a64def41 | 833 | return; |
7c12aa08 LT |
834 | |
835 | next_int: | |
a64def41 | 836 | if (pdata->an_int & XGBE_AN_CL73_PG_RCV) { |
7c12aa08 | 837 | pdata->an_state = XGBE_AN_PAGE_RECEIVED; |
a64def41 LT |
838 | pdata->an_int &= ~XGBE_AN_CL73_PG_RCV; |
839 | } else if (pdata->an_int & XGBE_AN_CL73_INC_LINK) { | |
7c12aa08 | 840 | pdata->an_state = XGBE_AN_INCOMPAT_LINK; |
a64def41 LT |
841 | pdata->an_int &= ~XGBE_AN_CL73_INC_LINK; |
842 | } else if (pdata->an_int & XGBE_AN_CL73_INT_CMPLT) { | |
7c12aa08 | 843 | pdata->an_state = XGBE_AN_COMPLETE; |
a64def41 | 844 | pdata->an_int &= ~XGBE_AN_CL73_INT_CMPLT; |
7c12aa08 LT |
845 | } else { |
846 | pdata->an_state = XGBE_AN_ERROR; | |
7c12aa08 LT |
847 | } |
848 | ||
7c12aa08 | 849 | again: |
a64def41 | 850 | netif_dbg(pdata, link, pdata->netdev, "CL73 AN %s\n", |
d5c78399 LT |
851 | xgbe_state_as_string(pdata->an_state)); |
852 | ||
7c12aa08 LT |
853 | cur_state = pdata->an_state; |
854 | ||
855 | switch (pdata->an_state) { | |
856 | case XGBE_AN_READY: | |
857 | pdata->an_supported = 0; | |
858 | break; | |
859 | ||
860 | case XGBE_AN_PAGE_RECEIVED: | |
a64def41 | 861 | pdata->an_state = xgbe_an73_page_received(pdata); |
7c12aa08 LT |
862 | pdata->an_supported++; |
863 | break; | |
c5aa9e3b | 864 | |
7c12aa08 LT |
865 | case XGBE_AN_INCOMPAT_LINK: |
866 | pdata->an_supported = 0; | |
867 | pdata->parallel_detect = 0; | |
a64def41 | 868 | pdata->an_state = xgbe_an73_incompat_link(pdata); |
7c12aa08 | 869 | break; |
c5aa9e3b | 870 | |
7c12aa08 LT |
871 | case XGBE_AN_COMPLETE: |
872 | pdata->parallel_detect = pdata->an_supported ? 0 : 1; | |
d5c78399 LT |
873 | netif_dbg(pdata, link, pdata->netdev, "%s successful\n", |
874 | pdata->an_supported ? "Auto negotiation" | |
875 | : "Parallel detection"); | |
7c12aa08 LT |
876 | break; |
877 | ||
878 | case XGBE_AN_NO_LINK: | |
879 | break; | |
880 | ||
881 | default: | |
882 | pdata->an_state = XGBE_AN_ERROR; | |
883 | } | |
884 | ||
885 | if (pdata->an_state == XGBE_AN_NO_LINK) { | |
ced3fcae | 886 | pdata->an_int = 0; |
a64def41 | 887 | xgbe_an73_clear_interrupts(pdata); |
7c12aa08 LT |
888 | } else if (pdata->an_state == XGBE_AN_ERROR) { |
889 | netdev_err(pdata->netdev, | |
890 | "error during auto-negotiation, state=%u\n", | |
891 | cur_state); | |
892 | ||
ced3fcae | 893 | pdata->an_int = 0; |
a64def41 | 894 | xgbe_an73_clear_interrupts(pdata); |
7c12aa08 LT |
895 | } |
896 | ||
897 | if (pdata->an_state >= XGBE_AN_COMPLETE) { | |
898 | pdata->an_result = pdata->an_state; | |
899 | pdata->an_state = XGBE_AN_READY; | |
900 | pdata->kr_state = XGBE_RX_BPA; | |
901 | pdata->kx_state = XGBE_RX_BPA; | |
902 | pdata->an_start = 0; | |
d5c78399 | 903 | |
a64def41 | 904 | netif_dbg(pdata, link, pdata->netdev, "CL73 AN result: %s\n", |
d5c78399 | 905 | xgbe_state_as_string(pdata->an_result)); |
7c12aa08 LT |
906 | } |
907 | ||
908 | if (cur_state != pdata->an_state) | |
909 | goto again; | |
910 | ||
ced3fcae | 911 | if (pdata->an_int) |
7c12aa08 LT |
912 | goto next_int; |
913 | ||
a64def41 LT |
914 | xgbe_an73_enable_interrupts(pdata); |
915 | } | |
916 | ||
917 | static void xgbe_an_state_machine(struct work_struct *work) | |
918 | { | |
919 | struct xgbe_prv_data *pdata = container_of(work, | |
920 | struct xgbe_prv_data, | |
921 | an_work); | |
922 | ||
923 | mutex_lock(&pdata->an_mutex); | |
924 | ||
925 | switch (pdata->an_mode) { | |
926 | case XGBE_AN_MODE_CL73: | |
d7445d1f | 927 | case XGBE_AN_MODE_CL73_REDRV: |
a64def41 LT |
928 | xgbe_an73_state_machine(pdata); |
929 | break; | |
1bf40ada LT |
930 | case XGBE_AN_MODE_CL37: |
931 | case XGBE_AN_MODE_CL37_SGMII: | |
932 | xgbe_an37_state_machine(pdata); | |
933 | break; | |
a64def41 LT |
934 | default: |
935 | break; | |
936 | } | |
7c12aa08 | 937 | |
85b85c85 LT |
938 | /* Reissue interrupt if status is not clear */ |
939 | if (pdata->vdata->irq_reissue_support) | |
940 | XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 3); | |
941 | ||
7c12aa08 | 942 | mutex_unlock(&pdata->an_mutex); |
c5aa9e3b LT |
943 | } |
944 | ||
1bf40ada LT |
945 | static void xgbe_an37_init(struct xgbe_prv_data *pdata) |
946 | { | |
d7445d1f LT |
947 | unsigned int advertising, reg; |
948 | ||
949 | advertising = pdata->phy_if.phy_impl.an_advertising(pdata); | |
1bf40ada LT |
950 | |
951 | /* Set up Advertisement register */ | |
952 | reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE); | |
d7445d1f | 953 | if (advertising & ADVERTISED_Pause) |
1bf40ada LT |
954 | reg |= 0x100; |
955 | else | |
956 | reg &= ~0x100; | |
957 | ||
d7445d1f | 958 | if (advertising & ADVERTISED_Asym_Pause) |
1bf40ada LT |
959 | reg |= 0x80; |
960 | else | |
961 | reg &= ~0x80; | |
962 | ||
963 | /* Full duplex, but not half */ | |
964 | reg |= XGBE_AN_CL37_FD_MASK; | |
965 | reg &= ~XGBE_AN_CL37_HD_MASK; | |
966 | ||
967 | XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE, reg); | |
968 | ||
969 | /* Set up the Control register */ | |
970 | reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL); | |
e6fbd47a LT |
971 | reg &= ~XGBE_AN_CL37_TX_CONFIG_MASK; |
972 | reg &= ~XGBE_AN_CL37_PCS_MODE_MASK; | |
1bf40ada LT |
973 | |
974 | switch (pdata->an_mode) { | |
975 | case XGBE_AN_MODE_CL37: | |
976 | reg |= XGBE_AN_CL37_PCS_MODE_BASEX; | |
977 | break; | |
978 | case XGBE_AN_MODE_CL37_SGMII: | |
979 | reg |= XGBE_AN_CL37_PCS_MODE_SGMII; | |
980 | break; | |
981 | default: | |
982 | break; | |
983 | } | |
984 | ||
985 | XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg); | |
986 | ||
987 | netif_dbg(pdata, link, pdata->netdev, "CL37 AN (%s) initialized\n", | |
988 | (pdata->an_mode == XGBE_AN_MODE_CL37) ? "BaseX" : "SGMII"); | |
989 | } | |
990 | ||
a64def41 | 991 | static void xgbe_an73_init(struct xgbe_prv_data *pdata) |
c5aa9e3b | 992 | { |
d7445d1f LT |
993 | unsigned int advertising, reg; |
994 | ||
995 | advertising = pdata->phy_if.phy_impl.an_advertising(pdata); | |
7c12aa08 LT |
996 | |
997 | /* Set up Advertisement register 3 first */ | |
998 | reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); | |
d7445d1f | 999 | if (advertising & ADVERTISED_10000baseR_FEC) |
7c12aa08 LT |
1000 | reg |= 0xc000; |
1001 | else | |
1002 | reg &= ~0xc000; | |
1003 | ||
1004 | XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2, reg); | |
1005 | ||
1006 | /* Set up Advertisement register 2 next */ | |
1007 | reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); | |
d7445d1f | 1008 | if (advertising & ADVERTISED_10000baseKR_Full) |
7c12aa08 LT |
1009 | reg |= 0x80; |
1010 | else | |
1011 | reg &= ~0x80; | |
1012 | ||
d7445d1f LT |
1013 | if ((advertising & ADVERTISED_1000baseKX_Full) || |
1014 | (advertising & ADVERTISED_2500baseX_Full)) | |
7c12aa08 LT |
1015 | reg |= 0x20; |
1016 | else | |
1017 | reg &= ~0x20; | |
1018 | ||
1019 | XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1, reg); | |
c5aa9e3b | 1020 | |
7c12aa08 LT |
1021 | /* Set up Advertisement register 1 last */ |
1022 | reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); | |
d7445d1f | 1023 | if (advertising & ADVERTISED_Pause) |
7c12aa08 LT |
1024 | reg |= 0x400; |
1025 | else | |
1026 | reg &= ~0x400; | |
c5aa9e3b | 1027 | |
d7445d1f | 1028 | if (advertising & ADVERTISED_Asym_Pause) |
7c12aa08 LT |
1029 | reg |= 0x800; |
1030 | else | |
1031 | reg &= ~0x800; | |
1032 | ||
1033 | /* We don't intend to perform XNP */ | |
1034 | reg &= ~XGBE_XNP_NP_EXCHANGE; | |
1035 | ||
1036 | XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE, reg); | |
d5c78399 | 1037 | |
a64def41 LT |
1038 | netif_dbg(pdata, link, pdata->netdev, "CL73 AN initialized\n"); |
1039 | } | |
1040 | ||
1041 | static void xgbe_an_init(struct xgbe_prv_data *pdata) | |
1042 | { | |
1043 | /* Set up advertisement registers based on current settings */ | |
1044 | pdata->an_mode = pdata->phy_if.phy_impl.an_mode(pdata); | |
1045 | switch (pdata->an_mode) { | |
1046 | case XGBE_AN_MODE_CL73: | |
d7445d1f | 1047 | case XGBE_AN_MODE_CL73_REDRV: |
a64def41 LT |
1048 | xgbe_an73_init(pdata); |
1049 | break; | |
1bf40ada LT |
1050 | case XGBE_AN_MODE_CL37: |
1051 | case XGBE_AN_MODE_CL37_SGMII: | |
1052 | xgbe_an37_init(pdata); | |
1053 | break; | |
a64def41 LT |
1054 | default: |
1055 | break; | |
1056 | } | |
7c12aa08 LT |
1057 | } |
1058 | ||
c1ce2f77 LT |
1059 | static const char *xgbe_phy_fc_string(struct xgbe_prv_data *pdata) |
1060 | { | |
1061 | if (pdata->tx_pause && pdata->rx_pause) | |
1062 | return "rx/tx"; | |
1063 | else if (pdata->rx_pause) | |
1064 | return "rx"; | |
1065 | else if (pdata->tx_pause) | |
1066 | return "tx"; | |
1067 | else | |
1068 | return "off"; | |
1069 | } | |
1070 | ||
7c12aa08 LT |
1071 | static const char *xgbe_phy_speed_string(int speed) |
1072 | { | |
1073 | switch (speed) { | |
abf0a1c2 LT |
1074 | case SPEED_100: |
1075 | return "100Mbps"; | |
7c12aa08 LT |
1076 | case SPEED_1000: |
1077 | return "1Gbps"; | |
1078 | case SPEED_2500: | |
1079 | return "2.5Gbps"; | |
1080 | case SPEED_10000: | |
1081 | return "10Gbps"; | |
1082 | case SPEED_UNKNOWN: | |
1083 | return "Unknown"; | |
1084 | default: | |
1085 | return "Unsupported"; | |
1086 | } | |
1087 | } | |
1088 | ||
1089 | static void xgbe_phy_print_status(struct xgbe_prv_data *pdata) | |
1090 | { | |
1091 | if (pdata->phy.link) | |
1092 | netdev_info(pdata->netdev, | |
1093 | "Link is Up - %s/%s - flow control %s\n", | |
1094 | xgbe_phy_speed_string(pdata->phy.speed), | |
1095 | pdata->phy.duplex == DUPLEX_FULL ? "Full" : "Half", | |
c1ce2f77 | 1096 | xgbe_phy_fc_string(pdata)); |
7c12aa08 LT |
1097 | else |
1098 | netdev_info(pdata->netdev, "Link is Down\n"); | |
1099 | } | |
1100 | ||
1101 | static void xgbe_phy_adjust_link(struct xgbe_prv_data *pdata) | |
1102 | { | |
1103 | int new_state = 0; | |
1104 | ||
1105 | if (pdata->phy.link) { | |
1106 | /* Flow control support */ | |
c1ce2f77 | 1107 | pdata->pause_autoneg = pdata->phy.pause_autoneg; |
7c12aa08 | 1108 | |
c1ce2f77 LT |
1109 | if (pdata->tx_pause != pdata->phy.tx_pause) { |
1110 | new_state = 1; | |
7c12aa08 | 1111 | pdata->hw_if.config_tx_flow_control(pdata); |
c1ce2f77 | 1112 | pdata->tx_pause = pdata->phy.tx_pause; |
7c12aa08 LT |
1113 | } |
1114 | ||
c1ce2f77 LT |
1115 | if (pdata->rx_pause != pdata->phy.rx_pause) { |
1116 | new_state = 1; | |
7c12aa08 | 1117 | pdata->hw_if.config_rx_flow_control(pdata); |
c1ce2f77 | 1118 | pdata->rx_pause = pdata->phy.rx_pause; |
7c12aa08 LT |
1119 | } |
1120 | ||
1121 | /* Speed support */ | |
1122 | if (pdata->phy_speed != pdata->phy.speed) { | |
1123 | new_state = 1; | |
1124 | pdata->phy_speed = pdata->phy.speed; | |
1125 | } | |
1126 | ||
1127 | if (pdata->phy_link != pdata->phy.link) { | |
1128 | new_state = 1; | |
1129 | pdata->phy_link = pdata->phy.link; | |
1130 | } | |
1131 | } else if (pdata->phy_link) { | |
1132 | new_state = 1; | |
1133 | pdata->phy_link = 0; | |
1134 | pdata->phy_speed = SPEED_UNKNOWN; | |
1135 | } | |
1136 | ||
1137 | if (new_state && netif_msg_link(pdata)) | |
1138 | xgbe_phy_print_status(pdata); | |
1139 | } | |
1140 | ||
e57f7a3f LT |
1141 | static bool xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed) |
1142 | { | |
1143 | return pdata->phy_if.phy_impl.valid_speed(pdata, speed); | |
1144 | } | |
1145 | ||
7c12aa08 LT |
1146 | static int xgbe_phy_config_fixed(struct xgbe_prv_data *pdata) |
1147 | { | |
e57f7a3f LT |
1148 | enum xgbe_mode mode; |
1149 | ||
d5c78399 LT |
1150 | netif_dbg(pdata, link, pdata->netdev, "fixed PHY configuration\n"); |
1151 | ||
7c12aa08 | 1152 | /* Disable auto-negotiation */ |
a64def41 | 1153 | xgbe_an_disable(pdata); |
7c12aa08 | 1154 | |
e57f7a3f LT |
1155 | /* Set specified mode for specified speed */ |
1156 | mode = pdata->phy_if.phy_impl.get_mode(pdata, pdata->phy.speed); | |
1157 | switch (mode) { | |
1158 | case XGBE_MODE_KX_1000: | |
1159 | case XGBE_MODE_KX_2500: | |
1160 | case XGBE_MODE_KR: | |
abf0a1c2 LT |
1161 | case XGBE_MODE_SGMII_100: |
1162 | case XGBE_MODE_SGMII_1000: | |
1163 | case XGBE_MODE_X: | |
1164 | case XGBE_MODE_SFI: | |
7c12aa08 | 1165 | break; |
e57f7a3f | 1166 | case XGBE_MODE_UNKNOWN: |
7c12aa08 LT |
1167 | default: |
1168 | return -EINVAL; | |
1169 | } | |
c5aa9e3b | 1170 | |
7c12aa08 LT |
1171 | /* Validate duplex mode */ |
1172 | if (pdata->phy.duplex != DUPLEX_FULL) | |
1173 | return -EINVAL; | |
1174 | ||
e57f7a3f LT |
1175 | xgbe_set_mode(pdata, mode); |
1176 | ||
c5aa9e3b LT |
1177 | return 0; |
1178 | } | |
1179 | ||
7c12aa08 LT |
1180 | static int __xgbe_phy_config_aneg(struct xgbe_prv_data *pdata) |
1181 | { | |
abf0a1c2 LT |
1182 | int ret; |
1183 | ||
7c12aa08 LT |
1184 | set_bit(XGBE_LINK_INIT, &pdata->dev_state); |
1185 | pdata->link_check = jiffies; | |
1186 | ||
abf0a1c2 LT |
1187 | ret = pdata->phy_if.phy_impl.an_config(pdata); |
1188 | if (ret) | |
1189 | return ret; | |
1190 | ||
d7445d1f LT |
1191 | if (pdata->phy.autoneg != AUTONEG_ENABLE) { |
1192 | ret = xgbe_phy_config_fixed(pdata); | |
1193 | if (ret || !pdata->kr_redrv) | |
1194 | return ret; | |
7c12aa08 | 1195 | |
d7445d1f LT |
1196 | netif_dbg(pdata, link, pdata->netdev, "AN redriver support\n"); |
1197 | } else { | |
1198 | netif_dbg(pdata, link, pdata->netdev, "AN PHY configuration\n"); | |
1199 | } | |
d5c78399 | 1200 | |
7c12aa08 LT |
1201 | /* Disable auto-negotiation interrupt */ |
1202 | disable_irq(pdata->an_irq); | |
1203 | ||
1204 | /* Start auto-negotiation in a supported mode */ | |
e57f7a3f | 1205 | if (xgbe_use_mode(pdata, XGBE_MODE_KR)) { |
7c12aa08 | 1206 | xgbe_set_mode(pdata, XGBE_MODE_KR); |
e57f7a3f LT |
1207 | } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_2500)) { |
1208 | xgbe_set_mode(pdata, XGBE_MODE_KX_2500); | |
1209 | } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_1000)) { | |
1210 | xgbe_set_mode(pdata, XGBE_MODE_KX_1000); | |
abf0a1c2 LT |
1211 | } else if (xgbe_use_mode(pdata, XGBE_MODE_SFI)) { |
1212 | xgbe_set_mode(pdata, XGBE_MODE_SFI); | |
1213 | } else if (xgbe_use_mode(pdata, XGBE_MODE_X)) { | |
1214 | xgbe_set_mode(pdata, XGBE_MODE_X); | |
1215 | } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_1000)) { | |
1216 | xgbe_set_mode(pdata, XGBE_MODE_SGMII_1000); | |
1217 | } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_100)) { | |
1218 | xgbe_set_mode(pdata, XGBE_MODE_SGMII_100); | |
7c12aa08 LT |
1219 | } else { |
1220 | enable_irq(pdata->an_irq); | |
1221 | return -EINVAL; | |
1222 | } | |
1223 | ||
1224 | /* Disable and stop any in progress auto-negotiation */ | |
1bf40ada | 1225 | xgbe_an_disable_all(pdata); |
7c12aa08 LT |
1226 | |
1227 | /* Clear any auto-negotitation interrupts */ | |
1bf40ada | 1228 | xgbe_an_clear_interrupts_all(pdata); |
7c12aa08 LT |
1229 | |
1230 | pdata->an_result = XGBE_AN_READY; | |
1231 | pdata->an_state = XGBE_AN_READY; | |
1232 | pdata->kr_state = XGBE_RX_BPA; | |
1233 | pdata->kx_state = XGBE_RX_BPA; | |
1234 | ||
1235 | /* Re-enable auto-negotiation interrupt */ | |
1236 | enable_irq(pdata->an_irq); | |
1237 | ||
7c12aa08 | 1238 | xgbe_an_init(pdata); |
a64def41 | 1239 | xgbe_an_restart(pdata); |
7c12aa08 LT |
1240 | |
1241 | return 0; | |
1242 | } | |
1243 | ||
1244 | static int xgbe_phy_config_aneg(struct xgbe_prv_data *pdata) | |
1245 | { | |
1246 | int ret; | |
1247 | ||
1248 | mutex_lock(&pdata->an_mutex); | |
1249 | ||
1250 | ret = __xgbe_phy_config_aneg(pdata); | |
1251 | if (ret) | |
1252 | set_bit(XGBE_LINK_ERR, &pdata->dev_state); | |
1253 | else | |
1254 | clear_bit(XGBE_LINK_ERR, &pdata->dev_state); | |
1255 | ||
1256 | mutex_unlock(&pdata->an_mutex); | |
1257 | ||
1258 | return ret; | |
1259 | } | |
1260 | ||
1261 | static bool xgbe_phy_aneg_done(struct xgbe_prv_data *pdata) | |
1262 | { | |
1263 | return (pdata->an_result == XGBE_AN_COMPLETE); | |
1264 | } | |
1265 | ||
1266 | static void xgbe_check_link_timeout(struct xgbe_prv_data *pdata) | |
1267 | { | |
1268 | unsigned long link_timeout; | |
1269 | ||
1270 | link_timeout = pdata->link_check + (XGBE_LINK_TIMEOUT * HZ); | |
d5c78399 LT |
1271 | if (time_after(jiffies, link_timeout)) { |
1272 | netif_dbg(pdata, link, pdata->netdev, "AN link timeout\n"); | |
7c12aa08 | 1273 | xgbe_phy_config_aneg(pdata); |
d5c78399 | 1274 | } |
7c12aa08 LT |
1275 | } |
1276 | ||
e57f7a3f | 1277 | static enum xgbe_mode xgbe_phy_status_aneg(struct xgbe_prv_data *pdata) |
7c12aa08 | 1278 | { |
e57f7a3f | 1279 | return pdata->phy_if.phy_impl.an_outcome(pdata); |
7c12aa08 LT |
1280 | } |
1281 | ||
e57f7a3f | 1282 | static void xgbe_phy_status_result(struct xgbe_prv_data *pdata) |
7c12aa08 | 1283 | { |
e57f7a3f | 1284 | enum xgbe_mode mode; |
7c12aa08 LT |
1285 | |
1286 | pdata->phy.lp_advertising = 0; | |
1287 | ||
1288 | if ((pdata->phy.autoneg != AUTONEG_ENABLE) || pdata->parallel_detect) | |
e57f7a3f LT |
1289 | mode = xgbe_cur_mode(pdata); |
1290 | else | |
1291 | mode = xgbe_phy_status_aneg(pdata); | |
7c12aa08 | 1292 | |
e57f7a3f | 1293 | switch (mode) { |
abf0a1c2 LT |
1294 | case XGBE_MODE_SGMII_100: |
1295 | pdata->phy.speed = SPEED_100; | |
1296 | break; | |
1297 | case XGBE_MODE_X: | |
e57f7a3f | 1298 | case XGBE_MODE_KX_1000: |
abf0a1c2 | 1299 | case XGBE_MODE_SGMII_1000: |
e57f7a3f LT |
1300 | pdata->phy.speed = SPEED_1000; |
1301 | break; | |
1302 | case XGBE_MODE_KX_2500: | |
1303 | pdata->phy.speed = SPEED_2500; | |
1304 | break; | |
1305 | case XGBE_MODE_KR: | |
abf0a1c2 | 1306 | case XGBE_MODE_SFI: |
7c12aa08 | 1307 | pdata->phy.speed = SPEED_10000; |
e57f7a3f LT |
1308 | break; |
1309 | case XGBE_MODE_UNKNOWN: | |
1310 | default: | |
7c12aa08 LT |
1311 | pdata->phy.speed = SPEED_UNKNOWN; |
1312 | } | |
1313 | ||
7c12aa08 | 1314 | pdata->phy.duplex = DUPLEX_FULL; |
e57f7a3f LT |
1315 | |
1316 | xgbe_set_mode(pdata, mode); | |
7c12aa08 LT |
1317 | } |
1318 | ||
1319 | static void xgbe_phy_status(struct xgbe_prv_data *pdata) | |
1320 | { | |
e57f7a3f | 1321 | unsigned int link_aneg; |
abf0a1c2 | 1322 | int an_restart; |
7c12aa08 LT |
1323 | |
1324 | if (test_bit(XGBE_LINK_ERR, &pdata->dev_state)) { | |
50789845 | 1325 | netif_carrier_off(pdata->netdev); |
7c12aa08 LT |
1326 | |
1327 | pdata->phy.link = 0; | |
1328 | goto adjust_link; | |
1329 | } | |
1330 | ||
1331 | link_aneg = (pdata->phy.autoneg == AUTONEG_ENABLE); | |
1332 | ||
abf0a1c2 LT |
1333 | pdata->phy.link = pdata->phy_if.phy_impl.link_status(pdata, |
1334 | &an_restart); | |
1335 | if (an_restart) { | |
1336 | xgbe_phy_config_aneg(pdata); | |
1337 | return; | |
1338 | } | |
1339 | ||
7c12aa08 LT |
1340 | if (pdata->phy.link) { |
1341 | if (link_aneg && !xgbe_phy_aneg_done(pdata)) { | |
1342 | xgbe_check_link_timeout(pdata); | |
1343 | return; | |
1344 | } | |
1345 | ||
e57f7a3f | 1346 | xgbe_phy_status_result(pdata); |
7c12aa08 LT |
1347 | |
1348 | if (test_bit(XGBE_LINK_INIT, &pdata->dev_state)) | |
1349 | clear_bit(XGBE_LINK_INIT, &pdata->dev_state); | |
1350 | ||
50789845 | 1351 | netif_carrier_on(pdata->netdev); |
7c12aa08 LT |
1352 | } else { |
1353 | if (test_bit(XGBE_LINK_INIT, &pdata->dev_state)) { | |
1354 | xgbe_check_link_timeout(pdata); | |
1355 | ||
1356 | if (link_aneg) | |
1357 | return; | |
1358 | } | |
1359 | ||
e57f7a3f | 1360 | xgbe_phy_status_result(pdata); |
7c12aa08 | 1361 | |
50789845 | 1362 | netif_carrier_off(pdata->netdev); |
7c12aa08 LT |
1363 | } |
1364 | ||
1365 | adjust_link: | |
1366 | xgbe_phy_adjust_link(pdata); | |
1367 | } | |
1368 | ||
1369 | static void xgbe_phy_stop(struct xgbe_prv_data *pdata) | |
1370 | { | |
d5c78399 LT |
1371 | netif_dbg(pdata, link, pdata->netdev, "stopping PHY\n"); |
1372 | ||
e57f7a3f LT |
1373 | if (!pdata->phy_started) |
1374 | return; | |
1375 | ||
1376 | /* Indicate the PHY is down */ | |
1377 | pdata->phy_started = 0; | |
1378 | ||
7c12aa08 | 1379 | /* Disable auto-negotiation */ |
1bf40ada | 1380 | xgbe_an_disable_all(pdata); |
7c12aa08 | 1381 | |
47f164de LT |
1382 | if (pdata->dev_irq != pdata->an_irq) |
1383 | devm_free_irq(pdata->dev, pdata->an_irq, pdata); | |
7c12aa08 | 1384 | |
e57f7a3f LT |
1385 | pdata->phy_if.phy_impl.stop(pdata); |
1386 | ||
7c12aa08 | 1387 | pdata->phy.link = 0; |
50789845 | 1388 | netif_carrier_off(pdata->netdev); |
7c12aa08 LT |
1389 | |
1390 | xgbe_phy_adjust_link(pdata); | |
1391 | } | |
1392 | ||
1393 | static int xgbe_phy_start(struct xgbe_prv_data *pdata) | |
1394 | { | |
1395 | struct net_device *netdev = pdata->netdev; | |
1396 | int ret; | |
1397 | ||
d5c78399 LT |
1398 | netif_dbg(pdata, link, pdata->netdev, "starting PHY\n"); |
1399 | ||
e57f7a3f LT |
1400 | ret = pdata->phy_if.phy_impl.start(pdata); |
1401 | if (ret) | |
1402 | return ret; | |
1403 | ||
47f164de LT |
1404 | /* If we have a separate AN irq, enable it */ |
1405 | if (pdata->dev_irq != pdata->an_irq) { | |
85b85c85 LT |
1406 | tasklet_init(&pdata->tasklet_an, xgbe_an_isr_task, |
1407 | (unsigned long)pdata); | |
1408 | ||
47f164de LT |
1409 | ret = devm_request_irq(pdata->dev, pdata->an_irq, |
1410 | xgbe_an_isr, 0, pdata->an_name, | |
1411 | pdata); | |
1412 | if (ret) { | |
1413 | netdev_err(netdev, "phy irq request failed\n"); | |
1414 | goto err_stop; | |
1415 | } | |
7c12aa08 LT |
1416 | } |
1417 | ||
1418 | /* Set initial mode - call the mode setting routines | |
1419 | * directly to insure we are properly configured | |
1420 | */ | |
e57f7a3f LT |
1421 | if (xgbe_use_mode(pdata, XGBE_MODE_KR)) { |
1422 | xgbe_kr_mode(pdata); | |
1423 | } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_2500)) { | |
1424 | xgbe_kx_2500_mode(pdata); | |
1425 | } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_1000)) { | |
1426 | xgbe_kx_1000_mode(pdata); | |
abf0a1c2 LT |
1427 | } else if (xgbe_use_mode(pdata, XGBE_MODE_SFI)) { |
1428 | xgbe_sfi_mode(pdata); | |
1429 | } else if (xgbe_use_mode(pdata, XGBE_MODE_X)) { | |
1430 | xgbe_x_mode(pdata); | |
1431 | } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_1000)) { | |
1432 | xgbe_sgmii_1000_mode(pdata); | |
1433 | } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_100)) { | |
1434 | xgbe_sgmii_100_mode(pdata); | |
7c12aa08 LT |
1435 | } else { |
1436 | ret = -EINVAL; | |
1437 | goto err_irq; | |
1438 | } | |
1439 | ||
e57f7a3f LT |
1440 | /* Indicate the PHY is up and running */ |
1441 | pdata->phy_started = 1; | |
1442 | ||
7c12aa08 | 1443 | xgbe_an_init(pdata); |
a64def41 | 1444 | xgbe_an_enable_interrupts(pdata); |
7c12aa08 LT |
1445 | |
1446 | return xgbe_phy_config_aneg(pdata); | |
1447 | ||
1448 | err_irq: | |
47f164de LT |
1449 | if (pdata->dev_irq != pdata->an_irq) |
1450 | devm_free_irq(pdata->dev, pdata->an_irq, pdata); | |
7c12aa08 | 1451 | |
e57f7a3f LT |
1452 | err_stop: |
1453 | pdata->phy_if.phy_impl.stop(pdata); | |
1454 | ||
7c12aa08 LT |
1455 | return ret; |
1456 | } | |
1457 | ||
1458 | static int xgbe_phy_reset(struct xgbe_prv_data *pdata) | |
1459 | { | |
e57f7a3f | 1460 | int ret; |
7c12aa08 | 1461 | |
e57f7a3f LT |
1462 | ret = pdata->phy_if.phy_impl.reset(pdata); |
1463 | if (ret) | |
1464 | return ret; | |
7c12aa08 LT |
1465 | |
1466 | /* Disable auto-negotiation for now */ | |
1bf40ada | 1467 | xgbe_an_disable_all(pdata); |
7c12aa08 LT |
1468 | |
1469 | /* Clear auto-negotiation interrupts */ | |
1bf40ada | 1470 | xgbe_an_clear_interrupts_all(pdata); |
7c12aa08 LT |
1471 | |
1472 | return 0; | |
1473 | } | |
1474 | ||
1475 | static void xgbe_dump_phy_registers(struct xgbe_prv_data *pdata) | |
c5aa9e3b LT |
1476 | { |
1477 | struct device *dev = pdata->dev; | |
c5aa9e3b | 1478 | |
34bf65df LT |
1479 | dev_dbg(dev, "\n************* PHY Reg dump **********************\n"); |
1480 | ||
d9682c90 | 1481 | dev_dbg(dev, "PCS Control Reg (%#06x) = %#06x\n", MDIO_CTRL1, |
34bf65df | 1482 | XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1)); |
d9682c90 | 1483 | dev_dbg(dev, "PCS Status Reg (%#06x) = %#06x\n", MDIO_STAT1, |
34bf65df | 1484 | XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1)); |
d9682c90 | 1485 | dev_dbg(dev, "Phy Id (PHYS ID 1 %#06x)= %#06x\n", MDIO_DEVID1, |
34bf65df | 1486 | XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID1)); |
d9682c90 | 1487 | dev_dbg(dev, "Phy Id (PHYS ID 2 %#06x)= %#06x\n", MDIO_DEVID2, |
34bf65df | 1488 | XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID2)); |
d9682c90 | 1489 | dev_dbg(dev, "Devices in Package (%#06x)= %#06x\n", MDIO_DEVS1, |
34bf65df | 1490 | XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS1)); |
d9682c90 | 1491 | dev_dbg(dev, "Devices in Package (%#06x)= %#06x\n", MDIO_DEVS2, |
34bf65df LT |
1492 | XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS2)); |
1493 | ||
d9682c90 | 1494 | dev_dbg(dev, "Auto-Neg Control Reg (%#06x) = %#06x\n", MDIO_CTRL1, |
34bf65df | 1495 | XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1)); |
d9682c90 | 1496 | dev_dbg(dev, "Auto-Neg Status Reg (%#06x) = %#06x\n", MDIO_STAT1, |
34bf65df | 1497 | XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_STAT1)); |
d9682c90 | 1498 | dev_dbg(dev, "Auto-Neg Ad Reg 1 (%#06x) = %#06x\n", |
34bf65df LT |
1499 | MDIO_AN_ADVERTISE, |
1500 | XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE)); | |
d9682c90 | 1501 | dev_dbg(dev, "Auto-Neg Ad Reg 2 (%#06x) = %#06x\n", |
34bf65df LT |
1502 | MDIO_AN_ADVERTISE + 1, |
1503 | XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1)); | |
d9682c90 | 1504 | dev_dbg(dev, "Auto-Neg Ad Reg 3 (%#06x) = %#06x\n", |
34bf65df LT |
1505 | MDIO_AN_ADVERTISE + 2, |
1506 | XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2)); | |
d9682c90 | 1507 | dev_dbg(dev, "Auto-Neg Completion Reg (%#06x) = %#06x\n", |
34bf65df LT |
1508 | MDIO_AN_COMP_STAT, |
1509 | XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_COMP_STAT)); | |
1510 | ||
34bf65df | 1511 | dev_dbg(dev, "\n*************************************************\n"); |
c5aa9e3b LT |
1512 | } |
1513 | ||
e57f7a3f LT |
1514 | static int xgbe_phy_best_advertised_speed(struct xgbe_prv_data *pdata) |
1515 | { | |
1516 | if (pdata->phy.advertising & ADVERTISED_10000baseKR_Full) | |
1517 | return SPEED_10000; | |
abf0a1c2 LT |
1518 | else if (pdata->phy.advertising & ADVERTISED_10000baseT_Full) |
1519 | return SPEED_10000; | |
e57f7a3f LT |
1520 | else if (pdata->phy.advertising & ADVERTISED_2500baseX_Full) |
1521 | return SPEED_2500; | |
1522 | else if (pdata->phy.advertising & ADVERTISED_1000baseKX_Full) | |
1523 | return SPEED_1000; | |
abf0a1c2 LT |
1524 | else if (pdata->phy.advertising & ADVERTISED_1000baseT_Full) |
1525 | return SPEED_1000; | |
1526 | else if (pdata->phy.advertising & ADVERTISED_100baseT_Full) | |
1527 | return SPEED_100; | |
e57f7a3f LT |
1528 | |
1529 | return SPEED_UNKNOWN; | |
1530 | } | |
1531 | ||
1532 | static void xgbe_phy_exit(struct xgbe_prv_data *pdata) | |
c5aa9e3b | 1533 | { |
e57f7a3f LT |
1534 | xgbe_phy_stop(pdata); |
1535 | ||
1536 | pdata->phy_if.phy_impl.exit(pdata); | |
1537 | } | |
1538 | ||
1539 | static int xgbe_phy_init(struct xgbe_prv_data *pdata) | |
1540 | { | |
1541 | int ret; | |
1542 | ||
7c12aa08 LT |
1543 | mutex_init(&pdata->an_mutex); |
1544 | INIT_WORK(&pdata->an_irq_work, xgbe_an_irq_work); | |
1545 | INIT_WORK(&pdata->an_work, xgbe_an_state_machine); | |
1546 | pdata->mdio_mmd = MDIO_MMD_PCS; | |
c5aa9e3b | 1547 | |
e57f7a3f | 1548 | /* Check for FEC support */ |
7c12aa08 LT |
1549 | pdata->fec_ability = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, |
1550 | MDIO_PMA_10GBR_FECABLE); | |
1551 | pdata->fec_ability &= (MDIO_PMA_10GBR_FECABLE_ABLE | | |
1552 | MDIO_PMA_10GBR_FECABLE_ERRABLE); | |
c5aa9e3b | 1553 | |
e57f7a3f LT |
1554 | /* Setup the phy (including supported features) */ |
1555 | ret = pdata->phy_if.phy_impl.init(pdata); | |
1556 | if (ret) | |
1557 | return ret; | |
7c12aa08 | 1558 | pdata->phy.advertising = pdata->phy.supported; |
c5aa9e3b | 1559 | |
7c12aa08 | 1560 | pdata->phy.address = 0; |
c5aa9e3b | 1561 | |
e57f7a3f LT |
1562 | if (pdata->phy.advertising & ADVERTISED_Autoneg) { |
1563 | pdata->phy.autoneg = AUTONEG_ENABLE; | |
1564 | pdata->phy.speed = SPEED_UNKNOWN; | |
1565 | pdata->phy.duplex = DUPLEX_UNKNOWN; | |
1566 | } else { | |
1567 | pdata->phy.autoneg = AUTONEG_DISABLE; | |
1568 | pdata->phy.speed = xgbe_phy_best_advertised_speed(pdata); | |
1569 | pdata->phy.duplex = DUPLEX_FULL; | |
1570 | } | |
c5aa9e3b | 1571 | |
7c12aa08 | 1572 | pdata->phy.link = 0; |
c5aa9e3b | 1573 | |
c1ce2f77 LT |
1574 | pdata->phy.pause_autoneg = pdata->pause_autoneg; |
1575 | pdata->phy.tx_pause = pdata->tx_pause; | |
1576 | pdata->phy.rx_pause = pdata->rx_pause; | |
1577 | ||
1578 | /* Fix up Flow Control advertising */ | |
1579 | pdata->phy.advertising &= ~ADVERTISED_Pause; | |
1580 | pdata->phy.advertising &= ~ADVERTISED_Asym_Pause; | |
1581 | ||
1582 | if (pdata->rx_pause) { | |
1583 | pdata->phy.advertising |= ADVERTISED_Pause; | |
1584 | pdata->phy.advertising |= ADVERTISED_Asym_Pause; | |
1585 | } | |
1586 | ||
1587 | if (pdata->tx_pause) | |
1588 | pdata->phy.advertising ^= ADVERTISED_Asym_Pause; | |
1589 | ||
34bf65df LT |
1590 | if (netif_msg_drv(pdata)) |
1591 | xgbe_dump_phy_registers(pdata); | |
e57f7a3f LT |
1592 | |
1593 | return 0; | |
c5aa9e3b LT |
1594 | } |
1595 | ||
7c12aa08 | 1596 | void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *phy_if) |
c5aa9e3b | 1597 | { |
7c12aa08 | 1598 | phy_if->phy_init = xgbe_phy_init; |
e57f7a3f | 1599 | phy_if->phy_exit = xgbe_phy_exit; |
c5aa9e3b | 1600 | |
7c12aa08 LT |
1601 | phy_if->phy_reset = xgbe_phy_reset; |
1602 | phy_if->phy_start = xgbe_phy_start; | |
1603 | phy_if->phy_stop = xgbe_phy_stop; | |
c5aa9e3b | 1604 | |
7c12aa08 LT |
1605 | phy_if->phy_status = xgbe_phy_status; |
1606 | phy_if->phy_config_aneg = xgbe_phy_config_aneg; | |
e57f7a3f LT |
1607 | |
1608 | phy_if->phy_valid_speed = xgbe_phy_valid_speed; | |
47f164de LT |
1609 | |
1610 | phy_if->an_isr = xgbe_an_combined_isr; | |
c5aa9e3b | 1611 | } |