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c5aa9e3b LT |
1 | /* |
2 | * AMD 10Gb Ethernet driver | |
3 | * | |
4 | * This file is available to you under your choice of the following two | |
5 | * licenses: | |
6 | * | |
7 | * License 1: GPLv2 | |
8 | * | |
ced3fcae | 9 | * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. |
c5aa9e3b LT |
10 | * |
11 | * This file is free software; you may copy, redistribute and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation, either version 2 of the License, or (at | |
14 | * your option) any later version. | |
15 | * | |
16 | * This file is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
19 | * General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
23 | * | |
24 | * This file incorporates work covered by the following copyright and | |
25 | * permission notice: | |
26 | * The Synopsys DWC ETHER XGMAC Software Driver and documentation | |
27 | * (hereinafter "Software") is an unsupported proprietary work of Synopsys, | |
28 | * Inc. unless otherwise expressly agreed to in writing between Synopsys | |
29 | * and you. | |
30 | * | |
31 | * The Software IS NOT an item of Licensed Software or Licensed Product | |
32 | * under any End User Software License Agreement or Agreement for Licensed | |
33 | * Product with Synopsys or any supplement thereto. Permission is hereby | |
34 | * granted, free of charge, to any person obtaining a copy of this software | |
35 | * annotated with this license and the Software, to deal in the Software | |
36 | * without restriction, including without limitation the rights to use, | |
37 | * copy, modify, merge, publish, distribute, sublicense, and/or sell copies | |
38 | * of the Software, and to permit persons to whom the Software is furnished | |
39 | * to do so, subject to the following conditions: | |
40 | * | |
41 | * The above copyright notice and this permission notice shall be included | |
42 | * in all copies or substantial portions of the Software. | |
43 | * | |
44 | * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" | |
45 | * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED | |
46 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A | |
47 | * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS | |
48 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
49 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
50 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
51 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
52 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
53 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF | |
54 | * THE POSSIBILITY OF SUCH DAMAGE. | |
55 | * | |
56 | * | |
57 | * License 2: Modified BSD | |
58 | * | |
ced3fcae | 59 | * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. |
c5aa9e3b LT |
60 | * All rights reserved. |
61 | * | |
62 | * Redistribution and use in source and binary forms, with or without | |
63 | * modification, are permitted provided that the following conditions are met: | |
64 | * * Redistributions of source code must retain the above copyright | |
65 | * notice, this list of conditions and the following disclaimer. | |
66 | * * Redistributions in binary form must reproduce the above copyright | |
67 | * notice, this list of conditions and the following disclaimer in the | |
68 | * documentation and/or other materials provided with the distribution. | |
69 | * * Neither the name of Advanced Micro Devices, Inc. nor the | |
70 | * names of its contributors may be used to endorse or promote products | |
71 | * derived from this software without specific prior written permission. | |
72 | * | |
73 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
74 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
75 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
76 | * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY | |
77 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
78 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
79 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
80 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
81 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
82 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
83 | * | |
84 | * This file incorporates work covered by the following copyright and | |
85 | * permission notice: | |
86 | * The Synopsys DWC ETHER XGMAC Software Driver and documentation | |
87 | * (hereinafter "Software") is an unsupported proprietary work of Synopsys, | |
88 | * Inc. unless otherwise expressly agreed to in writing between Synopsys | |
89 | * and you. | |
90 | * | |
91 | * The Software IS NOT an item of Licensed Software or Licensed Product | |
92 | * under any End User Software License Agreement or Agreement for Licensed | |
93 | * Product with Synopsys or any supplement thereto. Permission is hereby | |
94 | * granted, free of charge, to any person obtaining a copy of this software | |
95 | * annotated with this license and the Software, to deal in the Software | |
96 | * without restriction, including without limitation the rights to use, | |
97 | * copy, modify, merge, publish, distribute, sublicense, and/or sell copies | |
98 | * of the Software, and to permit persons to whom the Software is furnished | |
99 | * to do so, subject to the following conditions: | |
100 | * | |
101 | * The above copyright notice and this permission notice shall be included | |
102 | * in all copies or substantial portions of the Software. | |
103 | * | |
104 | * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" | |
105 | * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED | |
106 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A | |
107 | * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS | |
108 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
109 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
110 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
111 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
112 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
113 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF | |
114 | * THE POSSIBILITY OF SUCH DAMAGE. | |
115 | */ | |
116 | ||
117 | #include <linux/module.h> | |
118 | #include <linux/kmod.h> | |
c5aa9e3b LT |
119 | #include <linux/mdio.h> |
120 | #include <linux/phy.h> | |
121 | #include <linux/of.h> | |
7c12aa08 LT |
122 | #include <linux/bitops.h> |
123 | #include <linux/jiffies.h> | |
c5aa9e3b LT |
124 | |
125 | #include "xgbe.h" | |
126 | #include "xgbe-common.h" | |
127 | ||
1bf40ada LT |
128 | static void xgbe_an37_clear_interrupts(struct xgbe_prv_data *pdata) |
129 | { | |
130 | int reg; | |
131 | ||
132 | reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT); | |
133 | reg &= ~XGBE_AN_CL37_INT_MASK; | |
134 | XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg); | |
135 | } | |
136 | ||
137 | static void xgbe_an37_disable_interrupts(struct xgbe_prv_data *pdata) | |
138 | { | |
139 | int reg; | |
140 | ||
141 | reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL); | |
142 | reg &= ~XGBE_AN_CL37_INT_MASK; | |
143 | XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg); | |
144 | ||
145 | reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL); | |
146 | reg &= ~XGBE_PCS_CL37_BP; | |
147 | XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL, reg); | |
148 | } | |
149 | ||
150 | static void xgbe_an37_enable_interrupts(struct xgbe_prv_data *pdata) | |
151 | { | |
152 | int reg; | |
153 | ||
154 | reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL); | |
155 | reg |= XGBE_PCS_CL37_BP; | |
156 | XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL, reg); | |
157 | ||
158 | reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL); | |
159 | reg |= XGBE_AN_CL37_INT_MASK; | |
160 | XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg); | |
161 | } | |
162 | ||
a64def41 LT |
163 | static void xgbe_an73_clear_interrupts(struct xgbe_prv_data *pdata) |
164 | { | |
165 | XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0); | |
166 | } | |
167 | ||
168 | static void xgbe_an73_disable_interrupts(struct xgbe_prv_data *pdata) | |
169 | { | |
170 | XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 0); | |
171 | } | |
172 | ||
173 | static void xgbe_an73_enable_interrupts(struct xgbe_prv_data *pdata) | |
174 | { | |
175 | XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, XGBE_AN_CL73_INT_MASK); | |
176 | } | |
177 | ||
178 | static void xgbe_an_enable_interrupts(struct xgbe_prv_data *pdata) | |
179 | { | |
180 | switch (pdata->an_mode) { | |
181 | case XGBE_AN_MODE_CL73: | |
d7445d1f | 182 | case XGBE_AN_MODE_CL73_REDRV: |
a64def41 LT |
183 | xgbe_an73_enable_interrupts(pdata); |
184 | break; | |
1bf40ada LT |
185 | case XGBE_AN_MODE_CL37: |
186 | case XGBE_AN_MODE_CL37_SGMII: | |
187 | xgbe_an37_enable_interrupts(pdata); | |
188 | break; | |
a64def41 LT |
189 | default: |
190 | break; | |
191 | } | |
192 | } | |
193 | ||
1bf40ada LT |
194 | static void xgbe_an_clear_interrupts_all(struct xgbe_prv_data *pdata) |
195 | { | |
196 | xgbe_an73_clear_interrupts(pdata); | |
197 | xgbe_an37_clear_interrupts(pdata); | |
198 | } | |
199 | ||
a64def41 | 200 | static void xgbe_an73_enable_kr_training(struct xgbe_prv_data *pdata) |
c5aa9e3b | 201 | { |
7c12aa08 | 202 | unsigned int reg; |
c5aa9e3b | 203 | |
7c12aa08 | 204 | reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL); |
c5aa9e3b | 205 | |
7c12aa08 LT |
206 | reg |= XGBE_KR_TRAINING_ENABLE; |
207 | XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg); | |
208 | } | |
209 | ||
a64def41 | 210 | static void xgbe_an73_disable_kr_training(struct xgbe_prv_data *pdata) |
7c12aa08 LT |
211 | { |
212 | unsigned int reg; | |
213 | ||
214 | reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL); | |
215 | ||
216 | reg &= ~XGBE_KR_TRAINING_ENABLE; | |
217 | XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg); | |
218 | } | |
219 | ||
e57f7a3f | 220 | static void xgbe_kr_mode(struct xgbe_prv_data *pdata) |
7c12aa08 | 221 | { |
7c12aa08 | 222 | /* Enable KR training */ |
a64def41 | 223 | xgbe_an73_enable_kr_training(pdata); |
7c12aa08 LT |
224 | |
225 | /* Set MAC to 10G speed */ | |
e57f7a3f LT |
226 | pdata->hw_if.set_speed(pdata, SPEED_10000); |
227 | ||
228 | /* Call PHY implementation support to complete rate change */ | |
229 | pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KR); | |
7c12aa08 LT |
230 | } |
231 | ||
e57f7a3f | 232 | static void xgbe_kx_2500_mode(struct xgbe_prv_data *pdata) |
7c12aa08 | 233 | { |
7c12aa08 | 234 | /* Disable KR training */ |
a64def41 | 235 | xgbe_an73_disable_kr_training(pdata); |
7c12aa08 LT |
236 | |
237 | /* Set MAC to 2.5G speed */ | |
e57f7a3f LT |
238 | pdata->hw_if.set_speed(pdata, SPEED_2500); |
239 | ||
240 | /* Call PHY implementation support to complete rate change */ | |
241 | pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KX_2500); | |
7c12aa08 LT |
242 | } |
243 | ||
e57f7a3f | 244 | static void xgbe_kx_1000_mode(struct xgbe_prv_data *pdata) |
7c12aa08 | 245 | { |
7c12aa08 | 246 | /* Disable KR training */ |
a64def41 | 247 | xgbe_an73_disable_kr_training(pdata); |
7c12aa08 LT |
248 | |
249 | /* Set MAC to 1G speed */ | |
e57f7a3f LT |
250 | pdata->hw_if.set_speed(pdata, SPEED_1000); |
251 | ||
252 | /* Call PHY implementation support to complete rate change */ | |
253 | pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KX_1000); | |
7c12aa08 LT |
254 | } |
255 | ||
abf0a1c2 LT |
256 | static void xgbe_sfi_mode(struct xgbe_prv_data *pdata) |
257 | { | |
d7445d1f LT |
258 | /* If a KR re-driver is present, change to KR mode instead */ |
259 | if (pdata->kr_redrv) | |
260 | return xgbe_kr_mode(pdata); | |
261 | ||
abf0a1c2 LT |
262 | /* Disable KR training */ |
263 | xgbe_an73_disable_kr_training(pdata); | |
264 | ||
265 | /* Set MAC to 10G speed */ | |
266 | pdata->hw_if.set_speed(pdata, SPEED_10000); | |
267 | ||
268 | /* Call PHY implementation support to complete rate change */ | |
269 | pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SFI); | |
270 | } | |
271 | ||
272 | static void xgbe_x_mode(struct xgbe_prv_data *pdata) | |
273 | { | |
274 | /* Disable KR training */ | |
275 | xgbe_an73_disable_kr_training(pdata); | |
276 | ||
277 | /* Set MAC to 1G speed */ | |
278 | pdata->hw_if.set_speed(pdata, SPEED_1000); | |
279 | ||
280 | /* Call PHY implementation support to complete rate change */ | |
281 | pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_X); | |
282 | } | |
283 | ||
284 | static void xgbe_sgmii_1000_mode(struct xgbe_prv_data *pdata) | |
285 | { | |
286 | /* Disable KR training */ | |
287 | xgbe_an73_disable_kr_training(pdata); | |
288 | ||
289 | /* Set MAC to 1G speed */ | |
290 | pdata->hw_if.set_speed(pdata, SPEED_1000); | |
291 | ||
292 | /* Call PHY implementation support to complete rate change */ | |
293 | pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SGMII_1000); | |
294 | } | |
295 | ||
296 | static void xgbe_sgmii_100_mode(struct xgbe_prv_data *pdata) | |
297 | { | |
298 | /* Disable KR training */ | |
299 | xgbe_an73_disable_kr_training(pdata); | |
300 | ||
301 | /* Set MAC to 1G speed */ | |
302 | pdata->hw_if.set_speed(pdata, SPEED_1000); | |
303 | ||
304 | /* Call PHY implementation support to complete rate change */ | |
305 | pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SGMII_100); | |
306 | } | |
307 | ||
e57f7a3f | 308 | static enum xgbe_mode xgbe_cur_mode(struct xgbe_prv_data *pdata) |
7c12aa08 | 309 | { |
e57f7a3f | 310 | return pdata->phy_if.phy_impl.cur_mode(pdata); |
7c12aa08 LT |
311 | } |
312 | ||
313 | static bool xgbe_in_kr_mode(struct xgbe_prv_data *pdata) | |
314 | { | |
e57f7a3f | 315 | return (xgbe_cur_mode(pdata) == XGBE_MODE_KR); |
7c12aa08 LT |
316 | } |
317 | ||
e57f7a3f LT |
318 | static void xgbe_change_mode(struct xgbe_prv_data *pdata, |
319 | enum xgbe_mode mode) | |
7c12aa08 | 320 | { |
e57f7a3f LT |
321 | switch (mode) { |
322 | case XGBE_MODE_KX_1000: | |
323 | xgbe_kx_1000_mode(pdata); | |
324 | break; | |
325 | case XGBE_MODE_KX_2500: | |
326 | xgbe_kx_2500_mode(pdata); | |
327 | break; | |
328 | case XGBE_MODE_KR: | |
329 | xgbe_kr_mode(pdata); | |
330 | break; | |
abf0a1c2 LT |
331 | case XGBE_MODE_SGMII_100: |
332 | xgbe_sgmii_100_mode(pdata); | |
333 | break; | |
334 | case XGBE_MODE_SGMII_1000: | |
335 | xgbe_sgmii_1000_mode(pdata); | |
336 | break; | |
337 | case XGBE_MODE_X: | |
338 | xgbe_x_mode(pdata); | |
339 | break; | |
340 | case XGBE_MODE_SFI: | |
341 | xgbe_sfi_mode(pdata); | |
342 | break; | |
e57f7a3f LT |
343 | case XGBE_MODE_UNKNOWN: |
344 | break; | |
345 | default: | |
346 | netif_dbg(pdata, link, pdata->netdev, | |
347 | "invalid operation mode requested (%u)\n", mode); | |
7c12aa08 LT |
348 | } |
349 | } | |
350 | ||
e57f7a3f | 351 | static void xgbe_switch_mode(struct xgbe_prv_data *pdata) |
471e14b2 | 352 | { |
e57f7a3f | 353 | xgbe_change_mode(pdata, pdata->phy_if.phy_impl.switch_mode(pdata)); |
471e14b2 LT |
354 | } |
355 | ||
e57f7a3f LT |
356 | static void xgbe_set_mode(struct xgbe_prv_data *pdata, |
357 | enum xgbe_mode mode) | |
471e14b2 | 358 | { |
e57f7a3f LT |
359 | if (mode == xgbe_cur_mode(pdata)) |
360 | return; | |
471e14b2 | 361 | |
e57f7a3f | 362 | xgbe_change_mode(pdata, mode); |
471e14b2 LT |
363 | } |
364 | ||
e57f7a3f LT |
365 | static bool xgbe_use_mode(struct xgbe_prv_data *pdata, |
366 | enum xgbe_mode mode) | |
471e14b2 | 367 | { |
e57f7a3f | 368 | return pdata->phy_if.phy_impl.use_mode(pdata, mode); |
471e14b2 LT |
369 | } |
370 | ||
1bf40ada LT |
371 | static void xgbe_an37_set(struct xgbe_prv_data *pdata, bool enable, |
372 | bool restart) | |
373 | { | |
374 | unsigned int reg; | |
375 | ||
376 | reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_CTRL1); | |
377 | reg &= ~MDIO_VEND2_CTRL1_AN_ENABLE; | |
378 | ||
379 | if (enable) | |
380 | reg |= MDIO_VEND2_CTRL1_AN_ENABLE; | |
381 | ||
382 | if (restart) | |
383 | reg |= MDIO_VEND2_CTRL1_AN_RESTART; | |
384 | ||
385 | XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_CTRL1, reg); | |
386 | } | |
387 | ||
388 | static void xgbe_an37_restart(struct xgbe_prv_data *pdata) | |
389 | { | |
390 | xgbe_an37_enable_interrupts(pdata); | |
391 | xgbe_an37_set(pdata, true, true); | |
392 | ||
393 | netif_dbg(pdata, link, pdata->netdev, "CL37 AN enabled/restarted\n"); | |
394 | } | |
395 | ||
396 | static void xgbe_an37_disable(struct xgbe_prv_data *pdata) | |
397 | { | |
398 | xgbe_an37_set(pdata, false, false); | |
399 | xgbe_an37_disable_interrupts(pdata); | |
400 | ||
401 | netif_dbg(pdata, link, pdata->netdev, "CL37 AN disabled\n"); | |
402 | } | |
403 | ||
a64def41 LT |
404 | static void xgbe_an73_set(struct xgbe_prv_data *pdata, bool enable, |
405 | bool restart) | |
7c12aa08 LT |
406 | { |
407 | unsigned int reg; | |
408 | ||
409 | reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1); | |
410 | reg &= ~MDIO_AN_CTRL1_ENABLE; | |
411 | ||
412 | if (enable) | |
413 | reg |= MDIO_AN_CTRL1_ENABLE; | |
414 | ||
415 | if (restart) | |
416 | reg |= MDIO_AN_CTRL1_RESTART; | |
417 | ||
418 | XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_CTRL1, reg); | |
419 | } | |
420 | ||
a64def41 | 421 | static void xgbe_an73_restart(struct xgbe_prv_data *pdata) |
7c12aa08 | 422 | { |
a64def41 LT |
423 | xgbe_an73_enable_interrupts(pdata); |
424 | xgbe_an73_set(pdata, true, true); | |
d5c78399 | 425 | |
a64def41 | 426 | netif_dbg(pdata, link, pdata->netdev, "CL73 AN enabled/restarted\n"); |
7c12aa08 LT |
427 | } |
428 | ||
a64def41 | 429 | static void xgbe_an73_disable(struct xgbe_prv_data *pdata) |
7c12aa08 | 430 | { |
a64def41 LT |
431 | xgbe_an73_set(pdata, false, false); |
432 | xgbe_an73_disable_interrupts(pdata); | |
d5c78399 | 433 | |
a64def41 | 434 | netif_dbg(pdata, link, pdata->netdev, "CL73 AN disabled\n"); |
7c12aa08 LT |
435 | } |
436 | ||
a64def41 LT |
437 | static void xgbe_an_restart(struct xgbe_prv_data *pdata) |
438 | { | |
439 | switch (pdata->an_mode) { | |
440 | case XGBE_AN_MODE_CL73: | |
d7445d1f | 441 | case XGBE_AN_MODE_CL73_REDRV: |
a64def41 LT |
442 | xgbe_an73_restart(pdata); |
443 | break; | |
1bf40ada LT |
444 | case XGBE_AN_MODE_CL37: |
445 | case XGBE_AN_MODE_CL37_SGMII: | |
446 | xgbe_an37_restart(pdata); | |
447 | break; | |
a64def41 LT |
448 | default: |
449 | break; | |
450 | } | |
451 | } | |
452 | ||
453 | static void xgbe_an_disable(struct xgbe_prv_data *pdata) | |
454 | { | |
455 | switch (pdata->an_mode) { | |
456 | case XGBE_AN_MODE_CL73: | |
d7445d1f | 457 | case XGBE_AN_MODE_CL73_REDRV: |
a64def41 LT |
458 | xgbe_an73_disable(pdata); |
459 | break; | |
1bf40ada LT |
460 | case XGBE_AN_MODE_CL37: |
461 | case XGBE_AN_MODE_CL37_SGMII: | |
462 | xgbe_an37_disable(pdata); | |
463 | break; | |
a64def41 LT |
464 | default: |
465 | break; | |
466 | } | |
467 | } | |
468 | ||
1bf40ada LT |
469 | static void xgbe_an_disable_all(struct xgbe_prv_data *pdata) |
470 | { | |
471 | xgbe_an73_disable(pdata); | |
472 | xgbe_an37_disable(pdata); | |
473 | } | |
474 | ||
a64def41 LT |
475 | static enum xgbe_an xgbe_an73_tx_training(struct xgbe_prv_data *pdata, |
476 | enum xgbe_rx *state) | |
7c12aa08 LT |
477 | { |
478 | unsigned int ad_reg, lp_reg, reg; | |
479 | ||
480 | *state = XGBE_RX_COMPLETE; | |
481 | ||
482 | /* If we're not in KR mode then we're done */ | |
483 | if (!xgbe_in_kr_mode(pdata)) | |
484 | return XGBE_AN_PAGE_RECEIVED; | |
485 | ||
486 | /* Enable/Disable FEC */ | |
487 | ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); | |
488 | lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); | |
489 | ||
490 | reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL); | |
491 | reg &= ~(MDIO_PMA_10GBR_FECABLE_ABLE | MDIO_PMA_10GBR_FECABLE_ERRABLE); | |
492 | if ((ad_reg & 0xc000) && (lp_reg & 0xc000)) | |
493 | reg |= pdata->fec_ability; | |
494 | ||
495 | XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL, reg); | |
496 | ||
497 | /* Start KR training */ | |
498 | reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL); | |
499 | if (reg & XGBE_KR_TRAINING_ENABLE) { | |
e57f7a3f LT |
500 | if (pdata->phy_if.phy_impl.kr_training_pre) |
501 | pdata->phy_if.phy_impl.kr_training_pre(pdata); | |
7c12aa08 LT |
502 | |
503 | reg |= XGBE_KR_TRAINING_START; | |
504 | XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, | |
505 | reg); | |
506 | ||
e57f7a3f LT |
507 | if (pdata->phy_if.phy_impl.kr_training_post) |
508 | pdata->phy_if.phy_impl.kr_training_post(pdata); | |
d5c78399 LT |
509 | |
510 | netif_dbg(pdata, link, pdata->netdev, | |
511 | "KR training initiated\n"); | |
7c12aa08 LT |
512 | } |
513 | ||
514 | return XGBE_AN_PAGE_RECEIVED; | |
515 | } | |
516 | ||
a64def41 LT |
517 | static enum xgbe_an xgbe_an73_tx_xnp(struct xgbe_prv_data *pdata, |
518 | enum xgbe_rx *state) | |
7c12aa08 LT |
519 | { |
520 | u16 msg; | |
521 | ||
522 | *state = XGBE_RX_XNP; | |
523 | ||
524 | msg = XGBE_XNP_MCF_NULL_MESSAGE; | |
525 | msg |= XGBE_XNP_MP_FORMATTED; | |
526 | ||
527 | XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 2, 0); | |
528 | XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 1, 0); | |
529 | XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP, msg); | |
530 | ||
531 | return XGBE_AN_PAGE_RECEIVED; | |
532 | } | |
533 | ||
a64def41 LT |
534 | static enum xgbe_an xgbe_an73_rx_bpa(struct xgbe_prv_data *pdata, |
535 | enum xgbe_rx *state) | |
7c12aa08 LT |
536 | { |
537 | unsigned int link_support; | |
538 | unsigned int reg, ad_reg, lp_reg; | |
539 | ||
540 | /* Read Base Ability register 2 first */ | |
541 | reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); | |
542 | ||
543 | /* Check for a supported mode, otherwise restart in a different one */ | |
544 | link_support = xgbe_in_kr_mode(pdata) ? 0x80 : 0x20; | |
545 | if (!(reg & link_support)) | |
546 | return XGBE_AN_INCOMPAT_LINK; | |
547 | ||
548 | /* Check Extended Next Page support */ | |
549 | ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); | |
550 | lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA); | |
551 | ||
552 | return ((ad_reg & XGBE_XNP_NP_EXCHANGE) || | |
553 | (lp_reg & XGBE_XNP_NP_EXCHANGE)) | |
a64def41 LT |
554 | ? xgbe_an73_tx_xnp(pdata, state) |
555 | : xgbe_an73_tx_training(pdata, state); | |
7c12aa08 LT |
556 | } |
557 | ||
a64def41 LT |
558 | static enum xgbe_an xgbe_an73_rx_xnp(struct xgbe_prv_data *pdata, |
559 | enum xgbe_rx *state) | |
7c12aa08 LT |
560 | { |
561 | unsigned int ad_reg, lp_reg; | |
562 | ||
563 | /* Check Extended Next Page support */ | |
564 | ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_XNP); | |
565 | lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPX); | |
566 | ||
567 | return ((ad_reg & XGBE_XNP_NP_EXCHANGE) || | |
568 | (lp_reg & XGBE_XNP_NP_EXCHANGE)) | |
a64def41 LT |
569 | ? xgbe_an73_tx_xnp(pdata, state) |
570 | : xgbe_an73_tx_training(pdata, state); | |
7c12aa08 LT |
571 | } |
572 | ||
a64def41 | 573 | static enum xgbe_an xgbe_an73_page_received(struct xgbe_prv_data *pdata) |
7c12aa08 LT |
574 | { |
575 | enum xgbe_rx *state; | |
576 | unsigned long an_timeout; | |
577 | enum xgbe_an ret; | |
578 | ||
579 | if (!pdata->an_start) { | |
580 | pdata->an_start = jiffies; | |
581 | } else { | |
582 | an_timeout = pdata->an_start + | |
583 | msecs_to_jiffies(XGBE_AN_MS_TIMEOUT); | |
584 | if (time_after(jiffies, an_timeout)) { | |
585 | /* Auto-negotiation timed out, reset state */ | |
586 | pdata->kr_state = XGBE_RX_BPA; | |
587 | pdata->kx_state = XGBE_RX_BPA; | |
588 | ||
589 | pdata->an_start = jiffies; | |
d5c78399 LT |
590 | |
591 | netif_dbg(pdata, link, pdata->netdev, | |
a64def41 | 592 | "CL73 AN timed out, resetting state\n"); |
7c12aa08 LT |
593 | } |
594 | } | |
595 | ||
596 | state = xgbe_in_kr_mode(pdata) ? &pdata->kr_state | |
e57f7a3f | 597 | : &pdata->kx_state; |
7c12aa08 LT |
598 | |
599 | switch (*state) { | |
600 | case XGBE_RX_BPA: | |
a64def41 | 601 | ret = xgbe_an73_rx_bpa(pdata, state); |
7c12aa08 LT |
602 | break; |
603 | ||
604 | case XGBE_RX_XNP: | |
a64def41 | 605 | ret = xgbe_an73_rx_xnp(pdata, state); |
7c12aa08 LT |
606 | break; |
607 | ||
608 | default: | |
609 | ret = XGBE_AN_ERROR; | |
610 | } | |
611 | ||
612 | return ret; | |
613 | } | |
614 | ||
a64def41 | 615 | static enum xgbe_an xgbe_an73_incompat_link(struct xgbe_prv_data *pdata) |
7c12aa08 LT |
616 | { |
617 | /* Be sure we aren't looping trying to negotiate */ | |
618 | if (xgbe_in_kr_mode(pdata)) { | |
619 | pdata->kr_state = XGBE_RX_ERROR; | |
620 | ||
621 | if (!(pdata->phy.advertising & ADVERTISED_1000baseKX_Full) && | |
622 | !(pdata->phy.advertising & ADVERTISED_2500baseX_Full)) | |
623 | return XGBE_AN_NO_LINK; | |
624 | ||
625 | if (pdata->kx_state != XGBE_RX_BPA) | |
626 | return XGBE_AN_NO_LINK; | |
627 | } else { | |
628 | pdata->kx_state = XGBE_RX_ERROR; | |
629 | ||
630 | if (!(pdata->phy.advertising & ADVERTISED_10000baseKR_Full)) | |
631 | return XGBE_AN_NO_LINK; | |
632 | ||
633 | if (pdata->kr_state != XGBE_RX_BPA) | |
634 | return XGBE_AN_NO_LINK; | |
635 | } | |
636 | ||
a64def41 | 637 | xgbe_an73_disable(pdata); |
7c12aa08 LT |
638 | |
639 | xgbe_switch_mode(pdata); | |
640 | ||
a64def41 | 641 | xgbe_an73_restart(pdata); |
7c12aa08 LT |
642 | |
643 | return XGBE_AN_INCOMPAT_LINK; | |
644 | } | |
645 | ||
1bf40ada LT |
646 | static void xgbe_an37_isr(struct xgbe_prv_data *pdata) |
647 | { | |
648 | unsigned int reg; | |
649 | ||
650 | /* Disable AN interrupts */ | |
651 | xgbe_an37_disable_interrupts(pdata); | |
652 | ||
653 | /* Save the interrupt(s) that fired */ | |
654 | reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT); | |
655 | pdata->an_int = reg & XGBE_AN_CL37_INT_MASK; | |
656 | pdata->an_status = reg & ~XGBE_AN_CL37_INT_MASK; | |
657 | ||
658 | if (pdata->an_int) { | |
659 | /* Clear the interrupt(s) that fired and process them */ | |
660 | reg &= ~XGBE_AN_CL37_INT_MASK; | |
661 | XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg); | |
662 | ||
663 | queue_work(pdata->an_workqueue, &pdata->an_irq_work); | |
664 | } else { | |
665 | /* Enable AN interrupts */ | |
666 | xgbe_an37_enable_interrupts(pdata); | |
667 | } | |
668 | } | |
669 | ||
a64def41 | 670 | static void xgbe_an73_isr(struct xgbe_prv_data *pdata) |
7c12aa08 | 671 | { |
ced3fcae | 672 | /* Disable AN interrupts */ |
a64def41 | 673 | xgbe_an73_disable_interrupts(pdata); |
7c12aa08 | 674 | |
ced3fcae LT |
675 | /* Save the interrupt(s) that fired */ |
676 | pdata->an_int = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_INT); | |
677 | ||
678 | if (pdata->an_int) { | |
679 | /* Clear the interrupt(s) that fired and process them */ | |
680 | XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, ~pdata->an_int); | |
681 | ||
682 | queue_work(pdata->an_workqueue, &pdata->an_irq_work); | |
683 | } else { | |
684 | /* Enable AN interrupts */ | |
a64def41 LT |
685 | xgbe_an73_enable_interrupts(pdata); |
686 | } | |
687 | } | |
688 | ||
689 | static irqreturn_t xgbe_an_isr(int irq, void *data) | |
690 | { | |
691 | struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data; | |
692 | ||
693 | netif_dbg(pdata, intr, pdata->netdev, "AN interrupt received\n"); | |
694 | ||
695 | switch (pdata->an_mode) { | |
696 | case XGBE_AN_MODE_CL73: | |
d7445d1f | 697 | case XGBE_AN_MODE_CL73_REDRV: |
a64def41 LT |
698 | xgbe_an73_isr(pdata); |
699 | break; | |
1bf40ada LT |
700 | case XGBE_AN_MODE_CL37: |
701 | case XGBE_AN_MODE_CL37_SGMII: | |
702 | xgbe_an37_isr(pdata); | |
703 | break; | |
a64def41 LT |
704 | default: |
705 | break; | |
ced3fcae | 706 | } |
7c12aa08 LT |
707 | |
708 | return IRQ_HANDLED; | |
709 | } | |
710 | ||
47f164de LT |
711 | static irqreturn_t xgbe_an_combined_isr(int irq, struct xgbe_prv_data *pdata) |
712 | { | |
713 | return xgbe_an_isr(irq, pdata); | |
714 | } | |
715 | ||
7c12aa08 LT |
716 | static void xgbe_an_irq_work(struct work_struct *work) |
717 | { | |
718 | struct xgbe_prv_data *pdata = container_of(work, | |
719 | struct xgbe_prv_data, | |
720 | an_irq_work); | |
721 | ||
722 | /* Avoid a race between enabling the IRQ and exiting the work by | |
723 | * waiting for the work to finish and then queueing it | |
724 | */ | |
725 | flush_work(&pdata->an_work); | |
726 | queue_work(pdata->an_workqueue, &pdata->an_work); | |
727 | } | |
728 | ||
d5c78399 LT |
729 | static const char *xgbe_state_as_string(enum xgbe_an state) |
730 | { | |
731 | switch (state) { | |
732 | case XGBE_AN_READY: | |
733 | return "Ready"; | |
734 | case XGBE_AN_PAGE_RECEIVED: | |
735 | return "Page-Received"; | |
736 | case XGBE_AN_INCOMPAT_LINK: | |
737 | return "Incompatible-Link"; | |
738 | case XGBE_AN_COMPLETE: | |
739 | return "Complete"; | |
740 | case XGBE_AN_NO_LINK: | |
741 | return "No-Link"; | |
742 | case XGBE_AN_ERROR: | |
743 | return "Error"; | |
744 | default: | |
745 | return "Undefined"; | |
746 | } | |
747 | } | |
748 | ||
1bf40ada LT |
749 | static void xgbe_an37_state_machine(struct xgbe_prv_data *pdata) |
750 | { | |
751 | enum xgbe_an cur_state = pdata->an_state; | |
752 | ||
753 | if (!pdata->an_int) | |
754 | return; | |
755 | ||
756 | if (pdata->an_int & XGBE_AN_CL37_INT_CMPLT) { | |
757 | pdata->an_state = XGBE_AN_COMPLETE; | |
758 | pdata->an_int &= ~XGBE_AN_CL37_INT_CMPLT; | |
759 | ||
760 | /* If SGMII is enabled, check the link status */ | |
761 | if ((pdata->an_mode == XGBE_AN_MODE_CL37_SGMII) && | |
762 | !(pdata->an_status & XGBE_SGMII_AN_LINK_STATUS)) | |
763 | pdata->an_state = XGBE_AN_NO_LINK; | |
764 | } | |
765 | ||
766 | netif_dbg(pdata, link, pdata->netdev, "CL37 AN %s\n", | |
767 | xgbe_state_as_string(pdata->an_state)); | |
768 | ||
769 | cur_state = pdata->an_state; | |
770 | ||
771 | switch (pdata->an_state) { | |
772 | case XGBE_AN_READY: | |
773 | break; | |
774 | ||
775 | case XGBE_AN_COMPLETE: | |
776 | netif_dbg(pdata, link, pdata->netdev, | |
777 | "Auto negotiation successful\n"); | |
778 | break; | |
779 | ||
780 | case XGBE_AN_NO_LINK: | |
781 | break; | |
782 | ||
783 | default: | |
784 | pdata->an_state = XGBE_AN_ERROR; | |
785 | } | |
786 | ||
787 | if (pdata->an_state == XGBE_AN_ERROR) { | |
788 | netdev_err(pdata->netdev, | |
789 | "error during auto-negotiation, state=%u\n", | |
790 | cur_state); | |
791 | ||
792 | pdata->an_int = 0; | |
793 | xgbe_an37_clear_interrupts(pdata); | |
794 | } | |
795 | ||
796 | if (pdata->an_state >= XGBE_AN_COMPLETE) { | |
797 | pdata->an_result = pdata->an_state; | |
798 | pdata->an_state = XGBE_AN_READY; | |
799 | ||
800 | netif_dbg(pdata, link, pdata->netdev, "CL37 AN result: %s\n", | |
801 | xgbe_state_as_string(pdata->an_result)); | |
802 | } | |
803 | ||
804 | xgbe_an37_enable_interrupts(pdata); | |
805 | } | |
806 | ||
a64def41 | 807 | static void xgbe_an73_state_machine(struct xgbe_prv_data *pdata) |
7c12aa08 | 808 | { |
7c12aa08 | 809 | enum xgbe_an cur_state = pdata->an_state; |
7c12aa08 | 810 | |
ced3fcae | 811 | if (!pdata->an_int) |
a64def41 | 812 | return; |
7c12aa08 LT |
813 | |
814 | next_int: | |
a64def41 | 815 | if (pdata->an_int & XGBE_AN_CL73_PG_RCV) { |
7c12aa08 | 816 | pdata->an_state = XGBE_AN_PAGE_RECEIVED; |
a64def41 LT |
817 | pdata->an_int &= ~XGBE_AN_CL73_PG_RCV; |
818 | } else if (pdata->an_int & XGBE_AN_CL73_INC_LINK) { | |
7c12aa08 | 819 | pdata->an_state = XGBE_AN_INCOMPAT_LINK; |
a64def41 LT |
820 | pdata->an_int &= ~XGBE_AN_CL73_INC_LINK; |
821 | } else if (pdata->an_int & XGBE_AN_CL73_INT_CMPLT) { | |
7c12aa08 | 822 | pdata->an_state = XGBE_AN_COMPLETE; |
a64def41 | 823 | pdata->an_int &= ~XGBE_AN_CL73_INT_CMPLT; |
7c12aa08 LT |
824 | } else { |
825 | pdata->an_state = XGBE_AN_ERROR; | |
7c12aa08 LT |
826 | } |
827 | ||
7c12aa08 | 828 | again: |
a64def41 | 829 | netif_dbg(pdata, link, pdata->netdev, "CL73 AN %s\n", |
d5c78399 LT |
830 | xgbe_state_as_string(pdata->an_state)); |
831 | ||
7c12aa08 LT |
832 | cur_state = pdata->an_state; |
833 | ||
834 | switch (pdata->an_state) { | |
835 | case XGBE_AN_READY: | |
836 | pdata->an_supported = 0; | |
837 | break; | |
838 | ||
839 | case XGBE_AN_PAGE_RECEIVED: | |
a64def41 | 840 | pdata->an_state = xgbe_an73_page_received(pdata); |
7c12aa08 LT |
841 | pdata->an_supported++; |
842 | break; | |
c5aa9e3b | 843 | |
7c12aa08 LT |
844 | case XGBE_AN_INCOMPAT_LINK: |
845 | pdata->an_supported = 0; | |
846 | pdata->parallel_detect = 0; | |
a64def41 | 847 | pdata->an_state = xgbe_an73_incompat_link(pdata); |
7c12aa08 | 848 | break; |
c5aa9e3b | 849 | |
7c12aa08 LT |
850 | case XGBE_AN_COMPLETE: |
851 | pdata->parallel_detect = pdata->an_supported ? 0 : 1; | |
d5c78399 LT |
852 | netif_dbg(pdata, link, pdata->netdev, "%s successful\n", |
853 | pdata->an_supported ? "Auto negotiation" | |
854 | : "Parallel detection"); | |
7c12aa08 LT |
855 | break; |
856 | ||
857 | case XGBE_AN_NO_LINK: | |
858 | break; | |
859 | ||
860 | default: | |
861 | pdata->an_state = XGBE_AN_ERROR; | |
862 | } | |
863 | ||
864 | if (pdata->an_state == XGBE_AN_NO_LINK) { | |
ced3fcae | 865 | pdata->an_int = 0; |
a64def41 | 866 | xgbe_an73_clear_interrupts(pdata); |
7c12aa08 LT |
867 | } else if (pdata->an_state == XGBE_AN_ERROR) { |
868 | netdev_err(pdata->netdev, | |
869 | "error during auto-negotiation, state=%u\n", | |
870 | cur_state); | |
871 | ||
ced3fcae | 872 | pdata->an_int = 0; |
a64def41 | 873 | xgbe_an73_clear_interrupts(pdata); |
7c12aa08 LT |
874 | } |
875 | ||
876 | if (pdata->an_state >= XGBE_AN_COMPLETE) { | |
877 | pdata->an_result = pdata->an_state; | |
878 | pdata->an_state = XGBE_AN_READY; | |
879 | pdata->kr_state = XGBE_RX_BPA; | |
880 | pdata->kx_state = XGBE_RX_BPA; | |
881 | pdata->an_start = 0; | |
d5c78399 | 882 | |
a64def41 | 883 | netif_dbg(pdata, link, pdata->netdev, "CL73 AN result: %s\n", |
d5c78399 | 884 | xgbe_state_as_string(pdata->an_result)); |
7c12aa08 LT |
885 | } |
886 | ||
887 | if (cur_state != pdata->an_state) | |
888 | goto again; | |
889 | ||
ced3fcae | 890 | if (pdata->an_int) |
7c12aa08 LT |
891 | goto next_int; |
892 | ||
a64def41 LT |
893 | xgbe_an73_enable_interrupts(pdata); |
894 | } | |
895 | ||
896 | static void xgbe_an_state_machine(struct work_struct *work) | |
897 | { | |
898 | struct xgbe_prv_data *pdata = container_of(work, | |
899 | struct xgbe_prv_data, | |
900 | an_work); | |
901 | ||
902 | mutex_lock(&pdata->an_mutex); | |
903 | ||
904 | switch (pdata->an_mode) { | |
905 | case XGBE_AN_MODE_CL73: | |
d7445d1f | 906 | case XGBE_AN_MODE_CL73_REDRV: |
a64def41 LT |
907 | xgbe_an73_state_machine(pdata); |
908 | break; | |
1bf40ada LT |
909 | case XGBE_AN_MODE_CL37: |
910 | case XGBE_AN_MODE_CL37_SGMII: | |
911 | xgbe_an37_state_machine(pdata); | |
912 | break; | |
a64def41 LT |
913 | default: |
914 | break; | |
915 | } | |
7c12aa08 LT |
916 | |
917 | mutex_unlock(&pdata->an_mutex); | |
c5aa9e3b LT |
918 | } |
919 | ||
1bf40ada LT |
920 | static void xgbe_an37_init(struct xgbe_prv_data *pdata) |
921 | { | |
d7445d1f LT |
922 | unsigned int advertising, reg; |
923 | ||
924 | advertising = pdata->phy_if.phy_impl.an_advertising(pdata); | |
1bf40ada LT |
925 | |
926 | /* Set up Advertisement register */ | |
927 | reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE); | |
d7445d1f | 928 | if (advertising & ADVERTISED_Pause) |
1bf40ada LT |
929 | reg |= 0x100; |
930 | else | |
931 | reg &= ~0x100; | |
932 | ||
d7445d1f | 933 | if (advertising & ADVERTISED_Asym_Pause) |
1bf40ada LT |
934 | reg |= 0x80; |
935 | else | |
936 | reg &= ~0x80; | |
937 | ||
938 | /* Full duplex, but not half */ | |
939 | reg |= XGBE_AN_CL37_FD_MASK; | |
940 | reg &= ~XGBE_AN_CL37_HD_MASK; | |
941 | ||
942 | XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE, reg); | |
943 | ||
944 | /* Set up the Control register */ | |
945 | reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL); | |
e6fbd47a LT |
946 | reg &= ~XGBE_AN_CL37_TX_CONFIG_MASK; |
947 | reg &= ~XGBE_AN_CL37_PCS_MODE_MASK; | |
1bf40ada LT |
948 | |
949 | switch (pdata->an_mode) { | |
950 | case XGBE_AN_MODE_CL37: | |
951 | reg |= XGBE_AN_CL37_PCS_MODE_BASEX; | |
952 | break; | |
953 | case XGBE_AN_MODE_CL37_SGMII: | |
954 | reg |= XGBE_AN_CL37_PCS_MODE_SGMII; | |
955 | break; | |
956 | default: | |
957 | break; | |
958 | } | |
959 | ||
960 | XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg); | |
961 | ||
962 | netif_dbg(pdata, link, pdata->netdev, "CL37 AN (%s) initialized\n", | |
963 | (pdata->an_mode == XGBE_AN_MODE_CL37) ? "BaseX" : "SGMII"); | |
964 | } | |
965 | ||
a64def41 | 966 | static void xgbe_an73_init(struct xgbe_prv_data *pdata) |
c5aa9e3b | 967 | { |
d7445d1f LT |
968 | unsigned int advertising, reg; |
969 | ||
970 | advertising = pdata->phy_if.phy_impl.an_advertising(pdata); | |
7c12aa08 LT |
971 | |
972 | /* Set up Advertisement register 3 first */ | |
973 | reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); | |
d7445d1f | 974 | if (advertising & ADVERTISED_10000baseR_FEC) |
7c12aa08 LT |
975 | reg |= 0xc000; |
976 | else | |
977 | reg &= ~0xc000; | |
978 | ||
979 | XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2, reg); | |
980 | ||
981 | /* Set up Advertisement register 2 next */ | |
982 | reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); | |
d7445d1f | 983 | if (advertising & ADVERTISED_10000baseKR_Full) |
7c12aa08 LT |
984 | reg |= 0x80; |
985 | else | |
986 | reg &= ~0x80; | |
987 | ||
d7445d1f LT |
988 | if ((advertising & ADVERTISED_1000baseKX_Full) || |
989 | (advertising & ADVERTISED_2500baseX_Full)) | |
7c12aa08 LT |
990 | reg |= 0x20; |
991 | else | |
992 | reg &= ~0x20; | |
993 | ||
994 | XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1, reg); | |
c5aa9e3b | 995 | |
7c12aa08 LT |
996 | /* Set up Advertisement register 1 last */ |
997 | reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); | |
d7445d1f | 998 | if (advertising & ADVERTISED_Pause) |
7c12aa08 LT |
999 | reg |= 0x400; |
1000 | else | |
1001 | reg &= ~0x400; | |
c5aa9e3b | 1002 | |
d7445d1f | 1003 | if (advertising & ADVERTISED_Asym_Pause) |
7c12aa08 LT |
1004 | reg |= 0x800; |
1005 | else | |
1006 | reg &= ~0x800; | |
1007 | ||
1008 | /* We don't intend to perform XNP */ | |
1009 | reg &= ~XGBE_XNP_NP_EXCHANGE; | |
1010 | ||
1011 | XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE, reg); | |
d5c78399 | 1012 | |
a64def41 LT |
1013 | netif_dbg(pdata, link, pdata->netdev, "CL73 AN initialized\n"); |
1014 | } | |
1015 | ||
1016 | static void xgbe_an_init(struct xgbe_prv_data *pdata) | |
1017 | { | |
1018 | /* Set up advertisement registers based on current settings */ | |
1019 | pdata->an_mode = pdata->phy_if.phy_impl.an_mode(pdata); | |
1020 | switch (pdata->an_mode) { | |
1021 | case XGBE_AN_MODE_CL73: | |
d7445d1f | 1022 | case XGBE_AN_MODE_CL73_REDRV: |
a64def41 LT |
1023 | xgbe_an73_init(pdata); |
1024 | break; | |
1bf40ada LT |
1025 | case XGBE_AN_MODE_CL37: |
1026 | case XGBE_AN_MODE_CL37_SGMII: | |
1027 | xgbe_an37_init(pdata); | |
1028 | break; | |
a64def41 LT |
1029 | default: |
1030 | break; | |
1031 | } | |
7c12aa08 LT |
1032 | } |
1033 | ||
c1ce2f77 LT |
1034 | static const char *xgbe_phy_fc_string(struct xgbe_prv_data *pdata) |
1035 | { | |
1036 | if (pdata->tx_pause && pdata->rx_pause) | |
1037 | return "rx/tx"; | |
1038 | else if (pdata->rx_pause) | |
1039 | return "rx"; | |
1040 | else if (pdata->tx_pause) | |
1041 | return "tx"; | |
1042 | else | |
1043 | return "off"; | |
1044 | } | |
1045 | ||
7c12aa08 LT |
1046 | static const char *xgbe_phy_speed_string(int speed) |
1047 | { | |
1048 | switch (speed) { | |
abf0a1c2 LT |
1049 | case SPEED_100: |
1050 | return "100Mbps"; | |
7c12aa08 LT |
1051 | case SPEED_1000: |
1052 | return "1Gbps"; | |
1053 | case SPEED_2500: | |
1054 | return "2.5Gbps"; | |
1055 | case SPEED_10000: | |
1056 | return "10Gbps"; | |
1057 | case SPEED_UNKNOWN: | |
1058 | return "Unknown"; | |
1059 | default: | |
1060 | return "Unsupported"; | |
1061 | } | |
1062 | } | |
1063 | ||
1064 | static void xgbe_phy_print_status(struct xgbe_prv_data *pdata) | |
1065 | { | |
1066 | if (pdata->phy.link) | |
1067 | netdev_info(pdata->netdev, | |
1068 | "Link is Up - %s/%s - flow control %s\n", | |
1069 | xgbe_phy_speed_string(pdata->phy.speed), | |
1070 | pdata->phy.duplex == DUPLEX_FULL ? "Full" : "Half", | |
c1ce2f77 | 1071 | xgbe_phy_fc_string(pdata)); |
7c12aa08 LT |
1072 | else |
1073 | netdev_info(pdata->netdev, "Link is Down\n"); | |
1074 | } | |
1075 | ||
1076 | static void xgbe_phy_adjust_link(struct xgbe_prv_data *pdata) | |
1077 | { | |
1078 | int new_state = 0; | |
1079 | ||
1080 | if (pdata->phy.link) { | |
1081 | /* Flow control support */ | |
c1ce2f77 | 1082 | pdata->pause_autoneg = pdata->phy.pause_autoneg; |
7c12aa08 | 1083 | |
c1ce2f77 LT |
1084 | if (pdata->tx_pause != pdata->phy.tx_pause) { |
1085 | new_state = 1; | |
7c12aa08 | 1086 | pdata->hw_if.config_tx_flow_control(pdata); |
c1ce2f77 | 1087 | pdata->tx_pause = pdata->phy.tx_pause; |
7c12aa08 LT |
1088 | } |
1089 | ||
c1ce2f77 LT |
1090 | if (pdata->rx_pause != pdata->phy.rx_pause) { |
1091 | new_state = 1; | |
7c12aa08 | 1092 | pdata->hw_if.config_rx_flow_control(pdata); |
c1ce2f77 | 1093 | pdata->rx_pause = pdata->phy.rx_pause; |
7c12aa08 LT |
1094 | } |
1095 | ||
1096 | /* Speed support */ | |
1097 | if (pdata->phy_speed != pdata->phy.speed) { | |
1098 | new_state = 1; | |
1099 | pdata->phy_speed = pdata->phy.speed; | |
1100 | } | |
1101 | ||
1102 | if (pdata->phy_link != pdata->phy.link) { | |
1103 | new_state = 1; | |
1104 | pdata->phy_link = pdata->phy.link; | |
1105 | } | |
1106 | } else if (pdata->phy_link) { | |
1107 | new_state = 1; | |
1108 | pdata->phy_link = 0; | |
1109 | pdata->phy_speed = SPEED_UNKNOWN; | |
1110 | } | |
1111 | ||
1112 | if (new_state && netif_msg_link(pdata)) | |
1113 | xgbe_phy_print_status(pdata); | |
1114 | } | |
1115 | ||
e57f7a3f LT |
1116 | static bool xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed) |
1117 | { | |
1118 | return pdata->phy_if.phy_impl.valid_speed(pdata, speed); | |
1119 | } | |
1120 | ||
7c12aa08 LT |
1121 | static int xgbe_phy_config_fixed(struct xgbe_prv_data *pdata) |
1122 | { | |
e57f7a3f LT |
1123 | enum xgbe_mode mode; |
1124 | ||
d5c78399 LT |
1125 | netif_dbg(pdata, link, pdata->netdev, "fixed PHY configuration\n"); |
1126 | ||
7c12aa08 | 1127 | /* Disable auto-negotiation */ |
a64def41 | 1128 | xgbe_an_disable(pdata); |
7c12aa08 | 1129 | |
e57f7a3f LT |
1130 | /* Set specified mode for specified speed */ |
1131 | mode = pdata->phy_if.phy_impl.get_mode(pdata, pdata->phy.speed); | |
1132 | switch (mode) { | |
1133 | case XGBE_MODE_KX_1000: | |
1134 | case XGBE_MODE_KX_2500: | |
1135 | case XGBE_MODE_KR: | |
abf0a1c2 LT |
1136 | case XGBE_MODE_SGMII_100: |
1137 | case XGBE_MODE_SGMII_1000: | |
1138 | case XGBE_MODE_X: | |
1139 | case XGBE_MODE_SFI: | |
7c12aa08 | 1140 | break; |
e57f7a3f | 1141 | case XGBE_MODE_UNKNOWN: |
7c12aa08 LT |
1142 | default: |
1143 | return -EINVAL; | |
1144 | } | |
c5aa9e3b | 1145 | |
7c12aa08 LT |
1146 | /* Validate duplex mode */ |
1147 | if (pdata->phy.duplex != DUPLEX_FULL) | |
1148 | return -EINVAL; | |
1149 | ||
e57f7a3f LT |
1150 | xgbe_set_mode(pdata, mode); |
1151 | ||
c5aa9e3b LT |
1152 | return 0; |
1153 | } | |
1154 | ||
7c12aa08 LT |
1155 | static int __xgbe_phy_config_aneg(struct xgbe_prv_data *pdata) |
1156 | { | |
abf0a1c2 LT |
1157 | int ret; |
1158 | ||
7c12aa08 LT |
1159 | set_bit(XGBE_LINK_INIT, &pdata->dev_state); |
1160 | pdata->link_check = jiffies; | |
1161 | ||
abf0a1c2 LT |
1162 | ret = pdata->phy_if.phy_impl.an_config(pdata); |
1163 | if (ret) | |
1164 | return ret; | |
1165 | ||
d7445d1f LT |
1166 | if (pdata->phy.autoneg != AUTONEG_ENABLE) { |
1167 | ret = xgbe_phy_config_fixed(pdata); | |
1168 | if (ret || !pdata->kr_redrv) | |
1169 | return ret; | |
7c12aa08 | 1170 | |
d7445d1f LT |
1171 | netif_dbg(pdata, link, pdata->netdev, "AN redriver support\n"); |
1172 | } else { | |
1173 | netif_dbg(pdata, link, pdata->netdev, "AN PHY configuration\n"); | |
1174 | } | |
d5c78399 | 1175 | |
7c12aa08 LT |
1176 | /* Disable auto-negotiation interrupt */ |
1177 | disable_irq(pdata->an_irq); | |
1178 | ||
1179 | /* Start auto-negotiation in a supported mode */ | |
e57f7a3f | 1180 | if (xgbe_use_mode(pdata, XGBE_MODE_KR)) { |
7c12aa08 | 1181 | xgbe_set_mode(pdata, XGBE_MODE_KR); |
e57f7a3f LT |
1182 | } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_2500)) { |
1183 | xgbe_set_mode(pdata, XGBE_MODE_KX_2500); | |
1184 | } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_1000)) { | |
1185 | xgbe_set_mode(pdata, XGBE_MODE_KX_1000); | |
abf0a1c2 LT |
1186 | } else if (xgbe_use_mode(pdata, XGBE_MODE_SFI)) { |
1187 | xgbe_set_mode(pdata, XGBE_MODE_SFI); | |
1188 | } else if (xgbe_use_mode(pdata, XGBE_MODE_X)) { | |
1189 | xgbe_set_mode(pdata, XGBE_MODE_X); | |
1190 | } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_1000)) { | |
1191 | xgbe_set_mode(pdata, XGBE_MODE_SGMII_1000); | |
1192 | } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_100)) { | |
1193 | xgbe_set_mode(pdata, XGBE_MODE_SGMII_100); | |
7c12aa08 LT |
1194 | } else { |
1195 | enable_irq(pdata->an_irq); | |
1196 | return -EINVAL; | |
1197 | } | |
1198 | ||
1199 | /* Disable and stop any in progress auto-negotiation */ | |
1bf40ada | 1200 | xgbe_an_disable_all(pdata); |
7c12aa08 LT |
1201 | |
1202 | /* Clear any auto-negotitation interrupts */ | |
1bf40ada | 1203 | xgbe_an_clear_interrupts_all(pdata); |
7c12aa08 LT |
1204 | |
1205 | pdata->an_result = XGBE_AN_READY; | |
1206 | pdata->an_state = XGBE_AN_READY; | |
1207 | pdata->kr_state = XGBE_RX_BPA; | |
1208 | pdata->kx_state = XGBE_RX_BPA; | |
1209 | ||
1210 | /* Re-enable auto-negotiation interrupt */ | |
1211 | enable_irq(pdata->an_irq); | |
1212 | ||
7c12aa08 | 1213 | xgbe_an_init(pdata); |
a64def41 | 1214 | xgbe_an_restart(pdata); |
7c12aa08 LT |
1215 | |
1216 | return 0; | |
1217 | } | |
1218 | ||
1219 | static int xgbe_phy_config_aneg(struct xgbe_prv_data *pdata) | |
1220 | { | |
1221 | int ret; | |
1222 | ||
1223 | mutex_lock(&pdata->an_mutex); | |
1224 | ||
1225 | ret = __xgbe_phy_config_aneg(pdata); | |
1226 | if (ret) | |
1227 | set_bit(XGBE_LINK_ERR, &pdata->dev_state); | |
1228 | else | |
1229 | clear_bit(XGBE_LINK_ERR, &pdata->dev_state); | |
1230 | ||
1231 | mutex_unlock(&pdata->an_mutex); | |
1232 | ||
1233 | return ret; | |
1234 | } | |
1235 | ||
1236 | static bool xgbe_phy_aneg_done(struct xgbe_prv_data *pdata) | |
1237 | { | |
1238 | return (pdata->an_result == XGBE_AN_COMPLETE); | |
1239 | } | |
1240 | ||
1241 | static void xgbe_check_link_timeout(struct xgbe_prv_data *pdata) | |
1242 | { | |
1243 | unsigned long link_timeout; | |
1244 | ||
1245 | link_timeout = pdata->link_check + (XGBE_LINK_TIMEOUT * HZ); | |
d5c78399 LT |
1246 | if (time_after(jiffies, link_timeout)) { |
1247 | netif_dbg(pdata, link, pdata->netdev, "AN link timeout\n"); | |
7c12aa08 | 1248 | xgbe_phy_config_aneg(pdata); |
d5c78399 | 1249 | } |
7c12aa08 LT |
1250 | } |
1251 | ||
e57f7a3f | 1252 | static enum xgbe_mode xgbe_phy_status_aneg(struct xgbe_prv_data *pdata) |
7c12aa08 | 1253 | { |
e57f7a3f | 1254 | return pdata->phy_if.phy_impl.an_outcome(pdata); |
7c12aa08 LT |
1255 | } |
1256 | ||
e57f7a3f | 1257 | static void xgbe_phy_status_result(struct xgbe_prv_data *pdata) |
7c12aa08 | 1258 | { |
e57f7a3f | 1259 | enum xgbe_mode mode; |
7c12aa08 LT |
1260 | |
1261 | pdata->phy.lp_advertising = 0; | |
1262 | ||
1263 | if ((pdata->phy.autoneg != AUTONEG_ENABLE) || pdata->parallel_detect) | |
e57f7a3f LT |
1264 | mode = xgbe_cur_mode(pdata); |
1265 | else | |
1266 | mode = xgbe_phy_status_aneg(pdata); | |
7c12aa08 | 1267 | |
e57f7a3f | 1268 | switch (mode) { |
abf0a1c2 LT |
1269 | case XGBE_MODE_SGMII_100: |
1270 | pdata->phy.speed = SPEED_100; | |
1271 | break; | |
1272 | case XGBE_MODE_X: | |
e57f7a3f | 1273 | case XGBE_MODE_KX_1000: |
abf0a1c2 | 1274 | case XGBE_MODE_SGMII_1000: |
e57f7a3f LT |
1275 | pdata->phy.speed = SPEED_1000; |
1276 | break; | |
1277 | case XGBE_MODE_KX_2500: | |
1278 | pdata->phy.speed = SPEED_2500; | |
1279 | break; | |
1280 | case XGBE_MODE_KR: | |
abf0a1c2 | 1281 | case XGBE_MODE_SFI: |
7c12aa08 | 1282 | pdata->phy.speed = SPEED_10000; |
e57f7a3f LT |
1283 | break; |
1284 | case XGBE_MODE_UNKNOWN: | |
1285 | default: | |
7c12aa08 LT |
1286 | pdata->phy.speed = SPEED_UNKNOWN; |
1287 | } | |
1288 | ||
7c12aa08 | 1289 | pdata->phy.duplex = DUPLEX_FULL; |
e57f7a3f LT |
1290 | |
1291 | xgbe_set_mode(pdata, mode); | |
7c12aa08 LT |
1292 | } |
1293 | ||
1294 | static void xgbe_phy_status(struct xgbe_prv_data *pdata) | |
1295 | { | |
e57f7a3f | 1296 | unsigned int link_aneg; |
abf0a1c2 | 1297 | int an_restart; |
7c12aa08 LT |
1298 | |
1299 | if (test_bit(XGBE_LINK_ERR, &pdata->dev_state)) { | |
50789845 | 1300 | netif_carrier_off(pdata->netdev); |
7c12aa08 LT |
1301 | |
1302 | pdata->phy.link = 0; | |
1303 | goto adjust_link; | |
1304 | } | |
1305 | ||
1306 | link_aneg = (pdata->phy.autoneg == AUTONEG_ENABLE); | |
1307 | ||
abf0a1c2 LT |
1308 | pdata->phy.link = pdata->phy_if.phy_impl.link_status(pdata, |
1309 | &an_restart); | |
1310 | if (an_restart) { | |
1311 | xgbe_phy_config_aneg(pdata); | |
1312 | return; | |
1313 | } | |
1314 | ||
7c12aa08 LT |
1315 | if (pdata->phy.link) { |
1316 | if (link_aneg && !xgbe_phy_aneg_done(pdata)) { | |
1317 | xgbe_check_link_timeout(pdata); | |
1318 | return; | |
1319 | } | |
1320 | ||
e57f7a3f | 1321 | xgbe_phy_status_result(pdata); |
7c12aa08 LT |
1322 | |
1323 | if (test_bit(XGBE_LINK_INIT, &pdata->dev_state)) | |
1324 | clear_bit(XGBE_LINK_INIT, &pdata->dev_state); | |
1325 | ||
50789845 | 1326 | netif_carrier_on(pdata->netdev); |
7c12aa08 LT |
1327 | } else { |
1328 | if (test_bit(XGBE_LINK_INIT, &pdata->dev_state)) { | |
1329 | xgbe_check_link_timeout(pdata); | |
1330 | ||
1331 | if (link_aneg) | |
1332 | return; | |
1333 | } | |
1334 | ||
e57f7a3f | 1335 | xgbe_phy_status_result(pdata); |
7c12aa08 | 1336 | |
50789845 | 1337 | netif_carrier_off(pdata->netdev); |
7c12aa08 LT |
1338 | } |
1339 | ||
1340 | adjust_link: | |
1341 | xgbe_phy_adjust_link(pdata); | |
1342 | } | |
1343 | ||
1344 | static void xgbe_phy_stop(struct xgbe_prv_data *pdata) | |
1345 | { | |
d5c78399 LT |
1346 | netif_dbg(pdata, link, pdata->netdev, "stopping PHY\n"); |
1347 | ||
e57f7a3f LT |
1348 | if (!pdata->phy_started) |
1349 | return; | |
1350 | ||
1351 | /* Indicate the PHY is down */ | |
1352 | pdata->phy_started = 0; | |
1353 | ||
7c12aa08 | 1354 | /* Disable auto-negotiation */ |
1bf40ada | 1355 | xgbe_an_disable_all(pdata); |
7c12aa08 | 1356 | |
47f164de LT |
1357 | if (pdata->dev_irq != pdata->an_irq) |
1358 | devm_free_irq(pdata->dev, pdata->an_irq, pdata); | |
7c12aa08 | 1359 | |
e57f7a3f LT |
1360 | pdata->phy_if.phy_impl.stop(pdata); |
1361 | ||
7c12aa08 | 1362 | pdata->phy.link = 0; |
50789845 | 1363 | netif_carrier_off(pdata->netdev); |
7c12aa08 LT |
1364 | |
1365 | xgbe_phy_adjust_link(pdata); | |
1366 | } | |
1367 | ||
1368 | static int xgbe_phy_start(struct xgbe_prv_data *pdata) | |
1369 | { | |
1370 | struct net_device *netdev = pdata->netdev; | |
1371 | int ret; | |
1372 | ||
d5c78399 LT |
1373 | netif_dbg(pdata, link, pdata->netdev, "starting PHY\n"); |
1374 | ||
e57f7a3f LT |
1375 | ret = pdata->phy_if.phy_impl.start(pdata); |
1376 | if (ret) | |
1377 | return ret; | |
1378 | ||
47f164de LT |
1379 | /* If we have a separate AN irq, enable it */ |
1380 | if (pdata->dev_irq != pdata->an_irq) { | |
1381 | ret = devm_request_irq(pdata->dev, pdata->an_irq, | |
1382 | xgbe_an_isr, 0, pdata->an_name, | |
1383 | pdata); | |
1384 | if (ret) { | |
1385 | netdev_err(netdev, "phy irq request failed\n"); | |
1386 | goto err_stop; | |
1387 | } | |
7c12aa08 LT |
1388 | } |
1389 | ||
1390 | /* Set initial mode - call the mode setting routines | |
1391 | * directly to insure we are properly configured | |
1392 | */ | |
e57f7a3f LT |
1393 | if (xgbe_use_mode(pdata, XGBE_MODE_KR)) { |
1394 | xgbe_kr_mode(pdata); | |
1395 | } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_2500)) { | |
1396 | xgbe_kx_2500_mode(pdata); | |
1397 | } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_1000)) { | |
1398 | xgbe_kx_1000_mode(pdata); | |
abf0a1c2 LT |
1399 | } else if (xgbe_use_mode(pdata, XGBE_MODE_SFI)) { |
1400 | xgbe_sfi_mode(pdata); | |
1401 | } else if (xgbe_use_mode(pdata, XGBE_MODE_X)) { | |
1402 | xgbe_x_mode(pdata); | |
1403 | } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_1000)) { | |
1404 | xgbe_sgmii_1000_mode(pdata); | |
1405 | } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_100)) { | |
1406 | xgbe_sgmii_100_mode(pdata); | |
7c12aa08 LT |
1407 | } else { |
1408 | ret = -EINVAL; | |
1409 | goto err_irq; | |
1410 | } | |
1411 | ||
e57f7a3f LT |
1412 | /* Indicate the PHY is up and running */ |
1413 | pdata->phy_started = 1; | |
1414 | ||
7c12aa08 | 1415 | xgbe_an_init(pdata); |
a64def41 | 1416 | xgbe_an_enable_interrupts(pdata); |
7c12aa08 LT |
1417 | |
1418 | return xgbe_phy_config_aneg(pdata); | |
1419 | ||
1420 | err_irq: | |
47f164de LT |
1421 | if (pdata->dev_irq != pdata->an_irq) |
1422 | devm_free_irq(pdata->dev, pdata->an_irq, pdata); | |
7c12aa08 | 1423 | |
e57f7a3f LT |
1424 | err_stop: |
1425 | pdata->phy_if.phy_impl.stop(pdata); | |
1426 | ||
7c12aa08 LT |
1427 | return ret; |
1428 | } | |
1429 | ||
1430 | static int xgbe_phy_reset(struct xgbe_prv_data *pdata) | |
1431 | { | |
e57f7a3f | 1432 | int ret; |
7c12aa08 | 1433 | |
e57f7a3f LT |
1434 | ret = pdata->phy_if.phy_impl.reset(pdata); |
1435 | if (ret) | |
1436 | return ret; | |
7c12aa08 LT |
1437 | |
1438 | /* Disable auto-negotiation for now */ | |
1bf40ada | 1439 | xgbe_an_disable_all(pdata); |
7c12aa08 LT |
1440 | |
1441 | /* Clear auto-negotiation interrupts */ | |
1bf40ada | 1442 | xgbe_an_clear_interrupts_all(pdata); |
7c12aa08 LT |
1443 | |
1444 | return 0; | |
1445 | } | |
1446 | ||
1447 | static void xgbe_dump_phy_registers(struct xgbe_prv_data *pdata) | |
c5aa9e3b LT |
1448 | { |
1449 | struct device *dev = pdata->dev; | |
c5aa9e3b | 1450 | |
34bf65df LT |
1451 | dev_dbg(dev, "\n************* PHY Reg dump **********************\n"); |
1452 | ||
d9682c90 | 1453 | dev_dbg(dev, "PCS Control Reg (%#06x) = %#06x\n", MDIO_CTRL1, |
34bf65df | 1454 | XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1)); |
d9682c90 | 1455 | dev_dbg(dev, "PCS Status Reg (%#06x) = %#06x\n", MDIO_STAT1, |
34bf65df | 1456 | XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1)); |
d9682c90 | 1457 | dev_dbg(dev, "Phy Id (PHYS ID 1 %#06x)= %#06x\n", MDIO_DEVID1, |
34bf65df | 1458 | XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID1)); |
d9682c90 | 1459 | dev_dbg(dev, "Phy Id (PHYS ID 2 %#06x)= %#06x\n", MDIO_DEVID2, |
34bf65df | 1460 | XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID2)); |
d9682c90 | 1461 | dev_dbg(dev, "Devices in Package (%#06x)= %#06x\n", MDIO_DEVS1, |
34bf65df | 1462 | XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS1)); |
d9682c90 | 1463 | dev_dbg(dev, "Devices in Package (%#06x)= %#06x\n", MDIO_DEVS2, |
34bf65df LT |
1464 | XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS2)); |
1465 | ||
d9682c90 | 1466 | dev_dbg(dev, "Auto-Neg Control Reg (%#06x) = %#06x\n", MDIO_CTRL1, |
34bf65df | 1467 | XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1)); |
d9682c90 | 1468 | dev_dbg(dev, "Auto-Neg Status Reg (%#06x) = %#06x\n", MDIO_STAT1, |
34bf65df | 1469 | XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_STAT1)); |
d9682c90 | 1470 | dev_dbg(dev, "Auto-Neg Ad Reg 1 (%#06x) = %#06x\n", |
34bf65df LT |
1471 | MDIO_AN_ADVERTISE, |
1472 | XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE)); | |
d9682c90 | 1473 | dev_dbg(dev, "Auto-Neg Ad Reg 2 (%#06x) = %#06x\n", |
34bf65df LT |
1474 | MDIO_AN_ADVERTISE + 1, |
1475 | XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1)); | |
d9682c90 | 1476 | dev_dbg(dev, "Auto-Neg Ad Reg 3 (%#06x) = %#06x\n", |
34bf65df LT |
1477 | MDIO_AN_ADVERTISE + 2, |
1478 | XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2)); | |
d9682c90 | 1479 | dev_dbg(dev, "Auto-Neg Completion Reg (%#06x) = %#06x\n", |
34bf65df LT |
1480 | MDIO_AN_COMP_STAT, |
1481 | XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_COMP_STAT)); | |
1482 | ||
34bf65df | 1483 | dev_dbg(dev, "\n*************************************************\n"); |
c5aa9e3b LT |
1484 | } |
1485 | ||
e57f7a3f LT |
1486 | static int xgbe_phy_best_advertised_speed(struct xgbe_prv_data *pdata) |
1487 | { | |
1488 | if (pdata->phy.advertising & ADVERTISED_10000baseKR_Full) | |
1489 | return SPEED_10000; | |
abf0a1c2 LT |
1490 | else if (pdata->phy.advertising & ADVERTISED_10000baseT_Full) |
1491 | return SPEED_10000; | |
e57f7a3f LT |
1492 | else if (pdata->phy.advertising & ADVERTISED_2500baseX_Full) |
1493 | return SPEED_2500; | |
1494 | else if (pdata->phy.advertising & ADVERTISED_1000baseKX_Full) | |
1495 | return SPEED_1000; | |
abf0a1c2 LT |
1496 | else if (pdata->phy.advertising & ADVERTISED_1000baseT_Full) |
1497 | return SPEED_1000; | |
1498 | else if (pdata->phy.advertising & ADVERTISED_100baseT_Full) | |
1499 | return SPEED_100; | |
e57f7a3f LT |
1500 | |
1501 | return SPEED_UNKNOWN; | |
1502 | } | |
1503 | ||
1504 | static void xgbe_phy_exit(struct xgbe_prv_data *pdata) | |
c5aa9e3b | 1505 | { |
e57f7a3f LT |
1506 | xgbe_phy_stop(pdata); |
1507 | ||
1508 | pdata->phy_if.phy_impl.exit(pdata); | |
1509 | } | |
1510 | ||
1511 | static int xgbe_phy_init(struct xgbe_prv_data *pdata) | |
1512 | { | |
1513 | int ret; | |
1514 | ||
7c12aa08 LT |
1515 | mutex_init(&pdata->an_mutex); |
1516 | INIT_WORK(&pdata->an_irq_work, xgbe_an_irq_work); | |
1517 | INIT_WORK(&pdata->an_work, xgbe_an_state_machine); | |
1518 | pdata->mdio_mmd = MDIO_MMD_PCS; | |
c5aa9e3b | 1519 | |
e57f7a3f | 1520 | /* Check for FEC support */ |
7c12aa08 LT |
1521 | pdata->fec_ability = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, |
1522 | MDIO_PMA_10GBR_FECABLE); | |
1523 | pdata->fec_ability &= (MDIO_PMA_10GBR_FECABLE_ABLE | | |
1524 | MDIO_PMA_10GBR_FECABLE_ERRABLE); | |
c5aa9e3b | 1525 | |
e57f7a3f LT |
1526 | /* Setup the phy (including supported features) */ |
1527 | ret = pdata->phy_if.phy_impl.init(pdata); | |
1528 | if (ret) | |
1529 | return ret; | |
7c12aa08 | 1530 | pdata->phy.advertising = pdata->phy.supported; |
c5aa9e3b | 1531 | |
7c12aa08 | 1532 | pdata->phy.address = 0; |
c5aa9e3b | 1533 | |
e57f7a3f LT |
1534 | if (pdata->phy.advertising & ADVERTISED_Autoneg) { |
1535 | pdata->phy.autoneg = AUTONEG_ENABLE; | |
1536 | pdata->phy.speed = SPEED_UNKNOWN; | |
1537 | pdata->phy.duplex = DUPLEX_UNKNOWN; | |
1538 | } else { | |
1539 | pdata->phy.autoneg = AUTONEG_DISABLE; | |
1540 | pdata->phy.speed = xgbe_phy_best_advertised_speed(pdata); | |
1541 | pdata->phy.duplex = DUPLEX_FULL; | |
1542 | } | |
c5aa9e3b | 1543 | |
7c12aa08 | 1544 | pdata->phy.link = 0; |
c5aa9e3b | 1545 | |
c1ce2f77 LT |
1546 | pdata->phy.pause_autoneg = pdata->pause_autoneg; |
1547 | pdata->phy.tx_pause = pdata->tx_pause; | |
1548 | pdata->phy.rx_pause = pdata->rx_pause; | |
1549 | ||
1550 | /* Fix up Flow Control advertising */ | |
1551 | pdata->phy.advertising &= ~ADVERTISED_Pause; | |
1552 | pdata->phy.advertising &= ~ADVERTISED_Asym_Pause; | |
1553 | ||
1554 | if (pdata->rx_pause) { | |
1555 | pdata->phy.advertising |= ADVERTISED_Pause; | |
1556 | pdata->phy.advertising |= ADVERTISED_Asym_Pause; | |
1557 | } | |
1558 | ||
1559 | if (pdata->tx_pause) | |
1560 | pdata->phy.advertising ^= ADVERTISED_Asym_Pause; | |
1561 | ||
34bf65df LT |
1562 | if (netif_msg_drv(pdata)) |
1563 | xgbe_dump_phy_registers(pdata); | |
e57f7a3f LT |
1564 | |
1565 | return 0; | |
c5aa9e3b LT |
1566 | } |
1567 | ||
7c12aa08 | 1568 | void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *phy_if) |
c5aa9e3b | 1569 | { |
7c12aa08 | 1570 | phy_if->phy_init = xgbe_phy_init; |
e57f7a3f | 1571 | phy_if->phy_exit = xgbe_phy_exit; |
c5aa9e3b | 1572 | |
7c12aa08 LT |
1573 | phy_if->phy_reset = xgbe_phy_reset; |
1574 | phy_if->phy_start = xgbe_phy_start; | |
1575 | phy_if->phy_stop = xgbe_phy_stop; | |
c5aa9e3b | 1576 | |
7c12aa08 LT |
1577 | phy_if->phy_status = xgbe_phy_status; |
1578 | phy_if->phy_config_aneg = xgbe_phy_config_aneg; | |
e57f7a3f LT |
1579 | |
1580 | phy_if->phy_valid_speed = xgbe_phy_valid_speed; | |
47f164de LT |
1581 | |
1582 | phy_if->an_isr = xgbe_an_combined_isr; | |
c5aa9e3b | 1583 | } |