[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / hisilicon / hns3 / hns3_enet.h

// SPDX-License-Identifier: GPL-2.0+
// Copyright (c) 2016-2017 Hisilicon Limited.

#ifndef __HNS3_ENET_H
#define __HNS3_ENET_H

#include <linux/if_vlan.h>

#include "hnae3.h"

#define HNS3_MOD_VERSION "1.0"

extern const char hns3_driver_version[];

enum hns3_nic_state {
	HNS3_NIC_STATE_TESTING,
	HNS3_NIC_STATE_RESETTING,
	HNS3_NIC_STATE_INITED,
	HNS3_NIC_STATE_DOWN,
	HNS3_NIC_STATE_DISABLED,
	HNS3_NIC_STATE_REMOVING,
	HNS3_NIC_STATE_SERVICE_INITED,
	HNS3_NIC_STATE_SERVICE_SCHED,
	HNS3_NIC_STATE2_RESET_REQUESTED,
	HNS3_NIC_STATE_MAX
};

#define HNS3_RING_RX_RING_BASEADDR_L_REG	0x00000
#define HNS3_RING_RX_RING_BASEADDR_H_REG	0x00004
#define HNS3_RING_RX_RING_BD_NUM_REG		0x00008
#define HNS3_RING_RX_RING_BD_LEN_REG		0x0000C
#define HNS3_RING_RX_RING_TAIL_REG		0x00018
#define HNS3_RING_RX_RING_HEAD_REG		0x0001C
#define HNS3_RING_RX_RING_FBDNUM_REG		0x00020
#define HNS3_RING_RX_RING_PKTNUM_RECORD_REG	0x0002C

#define HNS3_RING_TX_RING_BASEADDR_L_REG	0x00040
#define HNS3_RING_TX_RING_BASEADDR_H_REG	0x00044
#define HNS3_RING_TX_RING_BD_NUM_REG		0x00048
#define HNS3_RING_TX_RING_TC_REG		0x00050
#define HNS3_RING_TX_RING_TAIL_REG		0x00058
#define HNS3_RING_TX_RING_HEAD_REG		0x0005C
#define HNS3_RING_TX_RING_FBDNUM_REG		0x00060
#define HNS3_RING_TX_RING_OFFSET_REG		0x00064
#define HNS3_RING_TX_RING_PKTNUM_RECORD_REG	0x0006C

#define HNS3_RING_PREFETCH_EN_REG		0x0007C
#define HNS3_RING_CFG_VF_NUM_REG		0x00080
#define HNS3_RING_ASID_REG			0x0008C
#define HNS3_RING_EN_REG			0x00090
#define HNS3_RING_T0_BE_RST			0x00094
#define HNS3_RING_COULD_BE_RST			0x00098
#define HNS3_RING_WRR_WEIGHT_REG		0x0009c

#define HNS3_RING_INTMSK_RXWL_REG		0x000A0
#define HNS3_RING_INTSTS_RX_RING_REG		0x000A4
#define HNS3_RX_RING_INT_STS_REG		0x000A8
#define HNS3_RING_INTMSK_TXWL_REG		0x000AC
#define HNS3_RING_INTSTS_TX_RING_REG		0x000B0
#define HNS3_TX_RING_INT_STS_REG		0x000B4
#define HNS3_RING_INTMSK_RX_OVERTIME_REG	0x000B8
#define HNS3_RING_INTSTS_RX_OVERTIME_REG	0x000BC
#define HNS3_RING_INTMSK_TX_OVERTIME_REG	0x000C4
#define HNS3_RING_INTSTS_TX_OVERTIME_REG	0x000C8

#define HNS3_RING_MB_CTRL_REG			0x00100
#define HNS3_RING_MB_DATA_BASE_REG		0x00200

#define HNS3_TX_REG_OFFSET			0x40

#define HNS3_RX_HEAD_SIZE			256

#define HNS3_TX_TIMEOUT (5 * HZ)
#define HNS3_RING_NAME_LEN			16
#define HNS3_BUFFER_SIZE_2048			2048
#define HNS3_RING_MAX_PENDING			32768
#define HNS3_RING_MIN_PENDING			8
#define HNS3_RING_BD_MULTIPLE			8
/* max frame size of mac */
#define HNS3_MAC_MAX_FRAME			9728
#define HNS3_MAX_MTU \
	(HNS3_MAC_MAX_FRAME - (ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN))

#define HNS3_BD_SIZE_512_TYPE			0
#define HNS3_BD_SIZE_1024_TYPE			1
#define HNS3_BD_SIZE_2048_TYPE			2
#define HNS3_BD_SIZE_4096_TYPE			3

#define HNS3_RX_FLAG_VLAN_PRESENT		0x1
#define HNS3_RX_FLAG_L3ID_IPV4			0x0
#define HNS3_RX_FLAG_L3ID_IPV6			0x1
#define HNS3_RX_FLAG_L4ID_UDP			0x0
#define HNS3_RX_FLAG_L4ID_TCP			0x1

#define HNS3_RXD_DMAC_S				0
#define HNS3_RXD_DMAC_M				(0x3 << HNS3_RXD_DMAC_S)
#define HNS3_RXD_VLAN_S				2
#define HNS3_RXD_VLAN_M				(0x3 << HNS3_RXD_VLAN_S)
#define HNS3_RXD_L3ID_S				4
#define HNS3_RXD_L3ID_M				(0xf << HNS3_RXD_L3ID_S)
#define HNS3_RXD_L4ID_S				8
#define HNS3_RXD_L4ID_M				(0xf << HNS3_RXD_L4ID_S)
#define HNS3_RXD_FRAG_B				12
#define HNS3_RXD_STRP_TAGP_S			13
#define HNS3_RXD_STRP_TAGP_M			(0x3 << HNS3_RXD_STRP_TAGP_S)

#define HNS3_RXD_L2E_B				16
#define HNS3_RXD_L3E_B				17
#define HNS3_RXD_L4E_B				18
#define HNS3_RXD_TRUNCAT_B			19
#define HNS3_RXD_HOI_B				20
#define HNS3_RXD_DOI_B				21
#define HNS3_RXD_OL3E_B				22
#define HNS3_RXD_OL4E_B				23
#define HNS3_RXD_GRO_COUNT_S			24
#define HNS3_RXD_GRO_COUNT_M			(0x3f << HNS3_RXD_GRO_COUNT_S)
#define HNS3_RXD_GRO_FIXID_B			30
#define HNS3_RXD_GRO_ECN_B			31

#define HNS3_RXD_ODMAC_S			0
#define HNS3_RXD_ODMAC_M			(0x3 << HNS3_RXD_ODMAC_S)
#define HNS3_RXD_OVLAN_S			2
#define HNS3_RXD_OVLAN_M			(0x3 << HNS3_RXD_OVLAN_S)
#define HNS3_RXD_OL3ID_S			4
#define HNS3_RXD_OL3ID_M			(0xf << HNS3_RXD_OL3ID_S)
#define HNS3_RXD_OL4ID_S			8
#define HNS3_RXD_OL4ID_M			(0xf << HNS3_RXD_OL4ID_S)
#define HNS3_RXD_FBHI_S				12
#define HNS3_RXD_FBHI_M				(0x3 << HNS3_RXD_FBHI_S)
#define HNS3_RXD_FBLI_S				14
#define HNS3_RXD_FBLI_M				(0x3 << HNS3_RXD_FBLI_S)

#define HNS3_RXD_BDTYPE_S			0
#define HNS3_RXD_BDTYPE_M			(0xf << HNS3_RXD_BDTYPE_S)
#define HNS3_RXD_VLD_B				4
#define HNS3_RXD_UDP0_B				5
#define HNS3_RXD_EXTEND_B			7
#define HNS3_RXD_FE_B				8
#define HNS3_RXD_LUM_B				9
#define HNS3_RXD_CRCP_B				10
#define HNS3_RXD_L3L4P_B			11
#define HNS3_RXD_TSIND_S			12
#define HNS3_RXD_TSIND_M			(0x7 << HNS3_RXD_TSIND_S)
#define HNS3_RXD_LKBK_B				15
#define HNS3_RXD_GRO_SIZE_S			16
#define HNS3_RXD_GRO_SIZE_M			(0x3ff << HNS3_RXD_GRO_SIZE_S)

#define HNS3_TXD_L3T_S				0
#define HNS3_TXD_L3T_M				(0x3 << HNS3_TXD_L3T_S)
#define HNS3_TXD_L4T_S				2
#define HNS3_TXD_L4T_M				(0x3 << HNS3_TXD_L4T_S)
#define HNS3_TXD_L3CS_B				4
#define HNS3_TXD_L4CS_B				5
#define HNS3_TXD_VLAN_B				6
#define HNS3_TXD_TSO_B				7

#define HNS3_TXD_L2LEN_S			8
#define HNS3_TXD_L2LEN_M			(0xff << HNS3_TXD_L2LEN_S)
#define HNS3_TXD_L3LEN_S			16
#define HNS3_TXD_L3LEN_M			(0xff << HNS3_TXD_L3LEN_S)
#define HNS3_TXD_L4LEN_S			24
#define HNS3_TXD_L4LEN_M			(0xff << HNS3_TXD_L4LEN_S)

#define HNS3_TXD_OL3T_S				0
#define HNS3_TXD_OL3T_M				(0x3 << HNS3_TXD_OL3T_S)
#define HNS3_TXD_OVLAN_B			2
#define HNS3_TXD_MACSEC_B			3
#define HNS3_TXD_TUNTYPE_S			4
#define HNS3_TXD_TUNTYPE_M			(0xf << HNS3_TXD_TUNTYPE_S)

#define HNS3_TXD_BDTYPE_S			0
#define HNS3_TXD_BDTYPE_M			(0xf << HNS3_TXD_BDTYPE_S)
#define HNS3_TXD_FE_B				4
#define HNS3_TXD_SC_S				5
#define HNS3_TXD_SC_M				(0x3 << HNS3_TXD_SC_S)
#define HNS3_TXD_EXTEND_B			7
#define HNS3_TXD_VLD_B				8
#define HNS3_TXD_RI_B				9
#define HNS3_TXD_RA_B				10
#define HNS3_TXD_TSYN_B				11
#define HNS3_TXD_DECTTL_S			12
#define HNS3_TXD_DECTTL_M			(0xf << HNS3_TXD_DECTTL_S)

#define HNS3_TXD_MSS_S				0
#define HNS3_TXD_MSS_M				(0x3fff << HNS3_TXD_MSS_S)

#define HNS3_VECTOR_TX_IRQ			BIT_ULL(0)
#define HNS3_VECTOR_RX_IRQ			BIT_ULL(1)

#define HNS3_VECTOR_NOT_INITED			0
#define HNS3_VECTOR_INITED			1

#define HNS3_MAX_BD_SIZE			65535
#define HNS3_MAX_BD_PER_FRAG			8
#define HNS3_MAX_BD_PER_PKT			MAX_SKB_FRAGS

#define HNS3_VECTOR_GL0_OFFSET			0x100
#define HNS3_VECTOR_GL1_OFFSET			0x200
#define HNS3_VECTOR_GL2_OFFSET			0x300
#define HNS3_VECTOR_RL_OFFSET			0x900
#define HNS3_VECTOR_RL_EN_B			6

#define HNS3_RING_EN_B				0

enum hns3_pkt_l3t_type {
	HNS3_L3T_NONE,
	HNS3_L3T_IPV6,
	HNS3_L3T_IPV4,
	HNS3_L3T_RESERVED
};

enum hns3_pkt_l4t_type {
	HNS3_L4T_UNKNOWN,
	HNS3_L4T_TCP,
	HNS3_L4T_UDP,
	HNS3_L4T_SCTP
};

enum hns3_pkt_ol3t_type {
	HNS3_OL3T_NONE,
	HNS3_OL3T_IPV6,
	HNS3_OL3T_IPV4_NO_CSUM,
	HNS3_OL3T_IPV4_CSUM
};

enum hns3_pkt_tun_type {
	HNS3_TUN_NONE,
	HNS3_TUN_MAC_IN_UDP,
	HNS3_TUN_NVGRE,
	HNS3_TUN_OTHER
};

/* hardware spec ring buffer format */
struct __packed hns3_desc {
	__le64 addr;
	union {
		struct {
			__le16 vlan_tag;
			__le16 send_size;
			union {
				__le32 type_cs_vlan_tso_len;
				struct {
					__u8 type_cs_vlan_tso;
					__u8 l2_len;
					__u8 l3_len;
					__u8 l4_len;
				};
			};
			__le16 outer_vlan_tag;
			__le16 tv;

		union {
			__le32 ol_type_vlan_len_msec;
			struct {
				__u8 ol_type_vlan_msec;
				__u8 ol2_len;
				__u8 ol3_len;
				__u8 ol4_len;
			};
		};

			__le32 paylen;
			__le16 bdtp_fe_sc_vld_ra_ri;
			__le16 mss;
		} tx;

		struct {
			__le32 l234_info;
			__le16 pkt_len;
			__le16 size;

			__le32 rss_hash;
			__le16 fd_id;
			__le16 vlan_tag;

			union {
				__le32 ol_info;
				struct {
					__le16 o_dm_vlan_id_fb;
					__le16 ot_vlan_tag;
				};
			};

			__le32 bd_base_info;
		} rx;
	};
};

struct hns3_desc_cb {
	dma_addr_t dma; /* dma address of this desc */
	void *buf;      /* cpu addr for a desc */

	/* priv data for the desc, e.g. skb when use with ip stack*/
	void *priv;
	u16 page_offset;
	u16 reuse_flag;

	u32 length;     /* length of the buffer */

       /* desc type, used by the ring user to mark the type of the priv data */
	u16 type;
};

enum hns3_pkt_l3type {
	HNS3_L3_TYPE_IPV4,
	HNS3_L3_TYPE_IPV6,
	HNS3_L3_TYPE_ARP,
	HNS3_L3_TYPE_RARP,
	HNS3_L3_TYPE_IPV4_OPT,
	HNS3_L3_TYPE_IPV6_EXT,
	HNS3_L3_TYPE_LLDP,
	HNS3_L3_TYPE_BPDU,
	HNS3_L3_TYPE_MAC_PAUSE,
	HNS3_L3_TYPE_PFC_PAUSE,/* 0x9*/

	/* reserved for 0xA~0xB*/

	HNS3_L3_TYPE_CNM = 0xc,

	/* reserved for 0xD~0xE*/

	HNS3_L3_TYPE_PARSE_FAIL	= 0xf /* must be last */
};

enum hns3_pkt_l4type {
	HNS3_L4_TYPE_UDP,
	HNS3_L4_TYPE_TCP,
	HNS3_L4_TYPE_GRE,
	HNS3_L4_TYPE_SCTP,
	HNS3_L4_TYPE_IGMP,
	HNS3_L4_TYPE_ICMP,

	/* reserved for 0x6~0xE */

	HNS3_L4_TYPE_PARSE_FAIL	= 0xf /* must be last */
};

enum hns3_pkt_ol3type {
	HNS3_OL3_TYPE_IPV4 = 0,
	HNS3_OL3_TYPE_IPV6,
	/* reserved for 0x2~0x3 */
	HNS3_OL3_TYPE_IPV4_OPT = 4,
	HNS3_OL3_TYPE_IPV6_EXT,

	/* reserved for 0x6~0xE*/

	HNS3_OL3_TYPE_PARSE_FAIL = 0xf	/* must be last */
};

enum hns3_pkt_ol4type {
	HNS3_OL4_TYPE_NO_TUN,
	HNS3_OL4_TYPE_MAC_IN_UDP,
	HNS3_OL4_TYPE_NVGRE,
	HNS3_OL4_TYPE_UNKNOWN
};

struct ring_stats {
	u64 io_err_cnt;
	u64 sw_err_cnt;
	u64 seg_pkt_cnt;
	union {
		struct {
			u64 tx_pkts;
			u64 tx_bytes;
			u64 tx_err_cnt;
			u64 restart_queue;
			u64 tx_busy;
		};
		struct {
			u64 rx_pkts;
			u64 rx_bytes;
			u64 rx_err_cnt;
			u64 reuse_pg_cnt;
			u64 err_pkt_len;
			u64 non_vld_descs;
			u64 err_bd_num;
			u64 l2_err;
			u64 l3l4_csum_err;
		};
	};
};

struct hns3_enet_ring {
	u8 __iomem *io_base; /* base io address for the ring */
	struct hns3_desc *desc; /* dma map address space */
	struct hns3_desc_cb *desc_cb;
	struct hns3_enet_ring *next;
	struct hns3_enet_tqp_vector *tqp_vector;
	struct hnae3_queue *tqp;
	char ring_name[HNS3_RING_NAME_LEN];
	struct device *dev; /* will be used for DMA mapping of descriptors */

	/* statistic */
	struct ring_stats stats;
	struct u64_stats_sync syncp;

	dma_addr_t desc_dma_addr;
	u32 buf_size;       /* size for hnae_desc->addr, preset by AE */
	u16 desc_num;       /* total number of desc */
	u16 max_desc_num_per_pkt;
	u16 max_raw_data_sz_per_desc;
	u16 max_pkt_size;
	int next_to_use;    /* idx of next spare desc */

	/* idx of lastest sent desc, the ring is empty when equal to
	 * next_to_use
	 */
	int next_to_clean;

	int pull_len; /* head length for current packet */
	u32 frag_num;
	unsigned char *va; /* first buffer address for current packet */

	u32 flag;          /* ring attribute */
	int irq_init_flag;

	int numa_node;
	cpumask_t affinity_mask;

	int pending_buf;
	struct sk_buff *skb;
	struct sk_buff *tail_skb;
};

struct hns_queue;

struct hns3_nic_ring_data {
	struct hns3_enet_ring *ring;
	struct napi_struct napi;
	int queue_index;
	int (*poll_one)(struct hns3_nic_ring_data *, int, void *);
	void (*ex_process)(struct hns3_nic_ring_data *, struct sk_buff *);
	void (*fini_process)(struct hns3_nic_ring_data *);
};

struct hns3_nic_ops {
	int (*fill_desc)(struct hns3_enet_ring *ring, void *priv,
			 int size, int frag_end, enum hns_desc_type type);
	int (*maybe_stop_tx)(struct sk_buff **out_skb,
			     int *bnum, struct hns3_enet_ring *ring);
	void (*get_rxd_bnum)(u32 bnum_flag, int *out_bnum);
};

enum hns3_flow_level_range {
	HNS3_FLOW_LOW = 0,
	HNS3_FLOW_MID = 1,
	HNS3_FLOW_HIGH = 2,
	HNS3_FLOW_ULTRA = 3,
};

enum hns3_link_mode_bits {
	HNS3_LM_FIBRE_BIT = BIT(0),
	HNS3_LM_AUTONEG_BIT = BIT(1),
	HNS3_LM_TP_BIT = BIT(2),
	HNS3_LM_PAUSE_BIT = BIT(3),
	HNS3_LM_BACKPLANE_BIT = BIT(4),
	HNS3_LM_10BASET_HALF_BIT = BIT(5),
	HNS3_LM_10BASET_FULL_BIT = BIT(6),
	HNS3_LM_100BASET_HALF_BIT = BIT(7),
	HNS3_LM_100BASET_FULL_BIT = BIT(8),
	HNS3_LM_1000BASET_FULL_BIT = BIT(9),
	HNS3_LM_10000BASEKR_FULL_BIT = BIT(10),
	HNS3_LM_25000BASEKR_FULL_BIT = BIT(11),
	HNS3_LM_40000BASELR4_FULL_BIT = BIT(12),
	HNS3_LM_50000BASEKR2_FULL_BIT = BIT(13),
	HNS3_LM_100000BASEKR4_FULL_BIT = BIT(14),
	HNS3_LM_COUNT = 15
};

#define HNS3_INT_GL_MAX			0x1FE0
#define HNS3_INT_GL_50K			0x0014
#define HNS3_INT_GL_20K			0x0032
#define HNS3_INT_GL_18K			0x0036
#define HNS3_INT_GL_8K			0x007C

#define HNS3_INT_RL_MAX			0x00EC
#define HNS3_INT_RL_ENABLE_MASK		0x40

struct hns3_enet_coalesce {
	u16 int_gl;
	u8 gl_adapt_enable;
	enum hns3_flow_level_range flow_level;
};

struct hns3_enet_ring_group {
	/* array of pointers to rings */
	struct hns3_enet_ring *ring;
	u64 total_bytes;	/* total bytes processed this group */
	u64 total_packets;	/* total packets processed this group */
	u16 count;
	struct hns3_enet_coalesce coal;
};

struct hns3_enet_tqp_vector {
	struct hnae3_handle *handle;
	u8 __iomem *mask_addr;
	int vector_irq;
	int irq_init_flag;

	u16 idx;		/* index in the TQP vector array per handle. */

	struct napi_struct napi;

	struct hns3_enet_ring_group rx_group;
	struct hns3_enet_ring_group tx_group;

	cpumask_t affinity_mask;
	u16 num_tqps;	/* total number of tqps in TQP vector */
	struct irq_affinity_notify affinity_notify;

	char name[HNAE3_INT_NAME_LEN];

	unsigned long last_jiffies;
} ____cacheline_internodealigned_in_smp;

enum hns3_udp_tnl_type {
	HNS3_UDP_TNL_VXLAN,
	HNS3_UDP_TNL_GENEVE,
	HNS3_UDP_TNL_MAX,
};

struct hns3_udp_tunnel {
	u16 dst_port;
	int used;
};

struct hns3_nic_priv {
	struct hnae3_handle *ae_handle;
	u32 enet_ver;
	u32 port_id;
	struct net_device *netdev;
	struct device *dev;
	struct hns3_nic_ops ops;

	/**
	 * the cb for nic to manage the ring buffer, the first half of the
	 * array is for tx_ring and vice versa for the second half
	 */
	struct hns3_nic_ring_data *ring_data;
	struct hns3_enet_tqp_vector *tqp_vector;
	u16 vector_num;

	/* The most recently read link state */
	int link;
	u64 tx_timeout_count;

	unsigned long state;

	struct timer_list service_timer;

	struct work_struct service_task;

	struct notifier_block notifier_block;
	/* Vxlan/Geneve information */
	struct hns3_udp_tunnel udp_tnl[HNS3_UDP_TNL_MAX];
	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
	struct hns3_enet_coalesce tx_coal;
	struct hns3_enet_coalesce rx_coal;
};

union l3_hdr_info {
	struct iphdr *v4;
	struct ipv6hdr *v6;
	unsigned char *hdr;
};

union l4_hdr_info {
	struct tcphdr *tcp;
	struct udphdr *udp;
	unsigned char *hdr;
};

/* the distance between [begin, end) in a ring buffer
 * note: there is a unuse slot between the begin and the end
 */
static inline int ring_dist(struct hns3_enet_ring *ring, int begin, int end)
{
	return (end - begin + ring->desc_num) % ring->desc_num;
}

static inline int ring_space(struct hns3_enet_ring *ring)
{
	return ring->desc_num -
		ring_dist(ring, ring->next_to_clean, ring->next_to_use) - 1;
}

static inline int is_ring_empty(struct hns3_enet_ring *ring)
{
	return ring->next_to_use == ring->next_to_clean;
}

static inline u32 hns3_read_reg(void __iomem *base, u32 reg)
{
	return readl(base + reg);
}

static inline void hns3_write_reg(void __iomem *base, u32 reg, u32 value)
{
	u8 __iomem *reg_addr = READ_ONCE(base);

	writel(value, reg_addr + reg);
}

static inline bool hns3_dev_ongoing_func_reset(struct hnae3_ae_dev *ae_dev)
{
	return (ae_dev && (ae_dev->reset_type == HNAE3_FUNC_RESET ||
			   ae_dev->reset_type == HNAE3_FLR_RESET ||
			   ae_dev->reset_type == HNAE3_VF_FUNC_RESET ||
			   ae_dev->reset_type == HNAE3_VF_FULL_RESET ||
			   ae_dev->reset_type == HNAE3_VF_PF_FUNC_RESET));
}

#define hns3_read_dev(a, reg) \
	hns3_read_reg((a)->io_base, (reg))

static inline bool hns3_nic_resetting(struct net_device *netdev)
{
	struct hns3_nic_priv *priv = netdev_priv(netdev);

	return test_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
}

#define hns3_write_dev(a, reg, value) \
	hns3_write_reg((a)->io_base, (reg), (value))

#define hnae3_queue_xmit(tqp, buf_num) writel_relaxed(buf_num, \
		(tqp)->io_base + HNS3_RING_TX_RING_TAIL_REG)

#define ring_to_dev(ring) (&(ring)->tqp->handle->pdev->dev)

#define ring_to_dma_dir(ring) (HNAE3_IS_TX_RING(ring) ? \
	DMA_TO_DEVICE : DMA_FROM_DEVICE)

#define tx_ring_data(priv, idx) ((priv)->ring_data[idx])

#define hnae3_buf_size(_ring) ((_ring)->buf_size)
#define hnae3_page_order(_ring) (get_order(hnae3_buf_size(_ring)))
#define hnae3_page_size(_ring) (PAGE_SIZE << hnae3_page_order(_ring))

/* iterator for handling rings in ring group */
#define hns3_for_each_ring(pos, head) \
	for (pos = (head).ring; pos; pos = pos->next)

#define hns3_get_handle(ndev) \
	(((struct hns3_nic_priv *)netdev_priv(ndev))->ae_handle)

#define hns3_gl_usec_to_reg(int_gl) (int_gl >> 1)
#define hns3_gl_round_down(int_gl) round_down(int_gl, 2)

#define hns3_rl_usec_to_reg(int_rl) (int_rl >> 2)
#define hns3_rl_round_down(int_rl) round_down(int_rl, 4)

void hns3_ethtool_set_ops(struct net_device *netdev);
int hns3_set_channels(struct net_device *netdev,
		      struct ethtool_channels *ch);

void hns3_clean_tx_ring(struct hns3_enet_ring *ring);
int hns3_init_all_ring(struct hns3_nic_priv *priv);
int hns3_uninit_all_ring(struct hns3_nic_priv *priv);
int hns3_nic_reset_all_ring(struct hnae3_handle *h);
netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev);
int hns3_clean_rx_ring(
		struct hns3_enet_ring *ring, int budget,
		void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *));

void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
				    u32 gl_value);
void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
				    u32 gl_value);
void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
				 u32 rl_value);

void hns3_enable_vlan_filter(struct net_device *netdev, bool enable);
int hns3_update_promisc_mode(struct net_device *netdev, u8 promisc_flags);

#ifdef CONFIG_HNS3_DCB
void hns3_dcbnl_setup(struct hnae3_handle *handle);
#else
static inline void hns3_dcbnl_setup(struct hnae3_handle *handle) {}
#endif

void hns3_dbg_init(struct hnae3_handle *handle);
void hns3_dbg_uninit(struct hnae3_handle *handle);
void hns3_dbg_register_debugfs(const char *debugfs_dir_name);
void hns3_dbg_unregister_debugfs(void);
#endif
Commit	Line	Data
ef57c40f JS	1	// SPDX-License-Identifier: GPL-2.0+
ef57c40f JS	2	// Copyright (c) 2016-2017 Hisilicon Limited.
76ad4f0e S	3
	4	#ifndef __HNS3_ENET_H
	5	#define __HNS3_ENET_H
	6
103ce052 YL	7	#include <linux/if_vlan.h>
103ce052 YL	8
76ad4f0e S	9	#include "hnae3.h"
76ad4f0e S	10
4786ad87 XW	11	#define HNS3_MOD_VERSION "1.0"
4786ad87 XW	12
76ad4f0e S	13	extern const char hns3_driver_version[];
	14
	15	enum hns3_nic_state {
	16	HNS3_NIC_STATE_TESTING,
	17	HNS3_NIC_STATE_RESETTING,
352285f1	18	HNS3_NIC_STATE_INITED,
76ad4f0e S	19	HNS3_NIC_STATE_DOWN,
	20	HNS3_NIC_STATE_DISABLED,
	21	HNS3_NIC_STATE_REMOVING,
	22	HNS3_NIC_STATE_SERVICE_INITED,
	23	HNS3_NIC_STATE_SERVICE_SCHED,
	24	HNS3_NIC_STATE2_RESET_REQUESTED,
	25	HNS3_NIC_STATE_MAX
	26	};
	27
	28	#define HNS3_RING_RX_RING_BASEADDR_L_REG 0x00000
	29	#define HNS3_RING_RX_RING_BASEADDR_H_REG 0x00004
	30	#define HNS3_RING_RX_RING_BD_NUM_REG 0x00008
	31	#define HNS3_RING_RX_RING_BD_LEN_REG 0x0000C
	32	#define HNS3_RING_RX_RING_TAIL_REG 0x00018
	33	#define HNS3_RING_RX_RING_HEAD_REG 0x0001C
	34	#define HNS3_RING_RX_RING_FBDNUM_REG 0x00020
	35	#define HNS3_RING_RX_RING_PKTNUM_RECORD_REG 0x0002C
	36
	37	#define HNS3_RING_TX_RING_BASEADDR_L_REG 0x00040
	38	#define HNS3_RING_TX_RING_BASEADDR_H_REG 0x00044
	39	#define HNS3_RING_TX_RING_BD_NUM_REG 0x00048
fe46c859	40	#define HNS3_RING_TX_RING_TC_REG 0x00050
76ad4f0e S	41	#define HNS3_RING_TX_RING_TAIL_REG 0x00058
	42	#define HNS3_RING_TX_RING_HEAD_REG 0x0005C
	43	#define HNS3_RING_TX_RING_FBDNUM_REG 0x00060
	44	#define HNS3_RING_TX_RING_OFFSET_REG 0x00064
	45	#define HNS3_RING_TX_RING_PKTNUM_RECORD_REG 0x0006C
	46
	47	#define HNS3_RING_PREFETCH_EN_REG 0x0007C
	48	#define HNS3_RING_CFG_VF_NUM_REG 0x00080
	49	#define HNS3_RING_ASID_REG 0x0008C
2b5251b7	50	#define HNS3_RING_EN_REG 0x00090
76ad4f0e S	51	#define HNS3_RING_T0_BE_RST 0x00094
	52	#define HNS3_RING_COULD_BE_RST 0x00098
	53	#define HNS3_RING_WRR_WEIGHT_REG 0x0009c
	54
	55	#define HNS3_RING_INTMSK_RXWL_REG 0x000A0
	56	#define HNS3_RING_INTSTS_RX_RING_REG 0x000A4
	57	#define HNS3_RX_RING_INT_STS_REG 0x000A8
	58	#define HNS3_RING_INTMSK_TXWL_REG 0x000AC
	59	#define HNS3_RING_INTSTS_TX_RING_REG 0x000B0
	60	#define HNS3_TX_RING_INT_STS_REG 0x000B4
	61	#define HNS3_RING_INTMSK_RX_OVERTIME_REG 0x000B8
	62	#define HNS3_RING_INTSTS_RX_OVERTIME_REG 0x000BC
	63	#define HNS3_RING_INTMSK_TX_OVERTIME_REG 0x000C4
	64	#define HNS3_RING_INTSTS_TX_OVERTIME_REG 0x000C8
	65
	66	#define HNS3_RING_MB_CTRL_REG 0x00100
	67	#define HNS3_RING_MB_DATA_BASE_REG 0x00200
	68
	69	#define HNS3_TX_REG_OFFSET 0x40
	70
	71	#define HNS3_RX_HEAD_SIZE 256
	72
	73	#define HNS3_TX_TIMEOUT (5 * HZ)
	74	#define HNS3_RING_NAME_LEN 16
	75	#define HNS3_BUFFER_SIZE_2048 2048
	76	#define HNS3_RING_MAX_PENDING 32768
5668abda L	77	#define HNS3_RING_MIN_PENDING 8
5668abda L	78	#define HNS3_RING_BD_MULTIPLE 8
4ee09281 YL	79	/* max frame size of mac */
	80	#define HNS3_MAC_MAX_FRAME 9728
	81	#define HNS3_MAX_MTU \
	82	(HNS3_MAC_MAX_FRAME - (ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN))
76ad4f0e S	83
	84	#define HNS3_BD_SIZE_512_TYPE 0
	85	#define HNS3_BD_SIZE_1024_TYPE 1
	86	#define HNS3_BD_SIZE_2048_TYPE 2
	87	#define HNS3_BD_SIZE_4096_TYPE 3
	88
	89	#define HNS3_RX_FLAG_VLAN_PRESENT 0x1
	90	#define HNS3_RX_FLAG_L3ID_IPV4 0x0
	91	#define HNS3_RX_FLAG_L3ID_IPV6 0x1
	92	#define HNS3_RX_FLAG_L4ID_UDP 0x0
	93	#define HNS3_RX_FLAG_L4ID_TCP 0x1
	94
	95	#define HNS3_RXD_DMAC_S 0
	96	#define HNS3_RXD_DMAC_M (0x3 << HNS3_RXD_DMAC_S)
	97	#define HNS3_RXD_VLAN_S 2
	98	#define HNS3_RXD_VLAN_M (0x3 << HNS3_RXD_VLAN_S)
	99	#define HNS3_RXD_L3ID_S 4
	100	#define HNS3_RXD_L3ID_M (0xf << HNS3_RXD_L3ID_S)
	101	#define HNS3_RXD_L4ID_S 8
	102	#define HNS3_RXD_L4ID_M (0xf << HNS3_RXD_L4ID_S)
	103	#define HNS3_RXD_FRAG_B 12
1e8f8bd3 PL	104	#define HNS3_RXD_STRP_TAGP_S 13
	105	#define HNS3_RXD_STRP_TAGP_M (0x3 << HNS3_RXD_STRP_TAGP_S)
	106
76ad4f0e S	107	#define HNS3_RXD_L2E_B 16
	108	#define HNS3_RXD_L3E_B 17
	109	#define HNS3_RXD_L4E_B 18
	110	#define HNS3_RXD_TRUNCAT_B 19
	111	#define HNS3_RXD_HOI_B 20
	112	#define HNS3_RXD_DOI_B 21
	113	#define HNS3_RXD_OL3E_B 22
	114	#define HNS3_RXD_OL4E_B 23
5337b725 PL	115	#define HNS3_RXD_GRO_COUNT_S 24
	116	#define HNS3_RXD_GRO_COUNT_M (0x3f << HNS3_RXD_GRO_COUNT_S)
	117	#define HNS3_RXD_GRO_FIXID_B 30
	118	#define HNS3_RXD_GRO_ECN_B 31
76ad4f0e S	119
	120	#define HNS3_RXD_ODMAC_S 0
	121	#define HNS3_RXD_ODMAC_M (0x3 << HNS3_RXD_ODMAC_S)
	122	#define HNS3_RXD_OVLAN_S 2
	123	#define HNS3_RXD_OVLAN_M (0x3 << HNS3_RXD_OVLAN_S)
	124	#define HNS3_RXD_OL3ID_S 4
	125	#define HNS3_RXD_OL3ID_M (0xf << HNS3_RXD_OL3ID_S)
	126	#define HNS3_RXD_OL4ID_S 8
	127	#define HNS3_RXD_OL4ID_M (0xf << HNS3_RXD_OL4ID_S)
	128	#define HNS3_RXD_FBHI_S 12
	129	#define HNS3_RXD_FBHI_M (0x3 << HNS3_RXD_FBHI_S)
	130	#define HNS3_RXD_FBLI_S 14
	131	#define HNS3_RXD_FBLI_M (0x3 << HNS3_RXD_FBLI_S)
	132
	133	#define HNS3_RXD_BDTYPE_S 0
	134	#define HNS3_RXD_BDTYPE_M (0xf << HNS3_RXD_BDTYPE_S)
	135	#define HNS3_RXD_VLD_B 4
	136	#define HNS3_RXD_UDP0_B 5
	137	#define HNS3_RXD_EXTEND_B 7
	138	#define HNS3_RXD_FE_B 8
	139	#define HNS3_RXD_LUM_B 9
	140	#define HNS3_RXD_CRCP_B 10
	141	#define HNS3_RXD_L3L4P_B 11
	142	#define HNS3_RXD_TSIND_S 12
	143	#define HNS3_RXD_TSIND_M (0x7 << HNS3_RXD_TSIND_S)
	144	#define HNS3_RXD_LKBK_B 15
5337b725 PL	145	#define HNS3_RXD_GRO_SIZE_S 16
5337b725 PL	146	#define HNS3_RXD_GRO_SIZE_M (0x3ff << HNS3_RXD_GRO_SIZE_S)
76ad4f0e S	147
	148	#define HNS3_TXD_L3T_S 0
	149	#define HNS3_TXD_L3T_M (0x3 << HNS3_TXD_L3T_S)
	150	#define HNS3_TXD_L4T_S 2
	151	#define HNS3_TXD_L4T_M (0x3 << HNS3_TXD_L4T_S)
	152	#define HNS3_TXD_L3CS_B 4
	153	#define HNS3_TXD_L4CS_B 5
	154	#define HNS3_TXD_VLAN_B 6
	155	#define HNS3_TXD_TSO_B 7
	156
	157	#define HNS3_TXD_L2LEN_S 8
	158	#define HNS3_TXD_L2LEN_M (0xff << HNS3_TXD_L2LEN_S)
	159	#define HNS3_TXD_L3LEN_S 16
	160	#define HNS3_TXD_L3LEN_M (0xff << HNS3_TXD_L3LEN_S)
	161	#define HNS3_TXD_L4LEN_S 24
	162	#define HNS3_TXD_L4LEN_M (0xff << HNS3_TXD_L4LEN_S)
	163
	164	#define HNS3_TXD_OL3T_S 0
	165	#define HNS3_TXD_OL3T_M (0x3 << HNS3_TXD_OL3T_S)
	166	#define HNS3_TXD_OVLAN_B 2
	167	#define HNS3_TXD_MACSEC_B 3
	168	#define HNS3_TXD_TUNTYPE_S 4
	169	#define HNS3_TXD_TUNTYPE_M (0xf << HNS3_TXD_TUNTYPE_S)
	170
	171	#define HNS3_TXD_BDTYPE_S 0
	172	#define HNS3_TXD_BDTYPE_M (0xf << HNS3_TXD_BDTYPE_S)
	173	#define HNS3_TXD_FE_B 4
	174	#define HNS3_TXD_SC_S 5
	175	#define HNS3_TXD_SC_M (0x3 << HNS3_TXD_SC_S)
	176	#define HNS3_TXD_EXTEND_B 7
	177	#define HNS3_TXD_VLD_B 8
	178	#define HNS3_TXD_RI_B 9
	179	#define HNS3_TXD_RA_B 10
	180	#define HNS3_TXD_TSYN_B 11
	181	#define HNS3_TXD_DECTTL_S 12
	182	#define HNS3_TXD_DECTTL_M (0xf << HNS3_TXD_DECTTL_S)
	183
	184	#define HNS3_TXD_MSS_S 0
	185	#define HNS3_TXD_MSS_M (0x3fff << HNS3_TXD_MSS_S)
	186
	187	#define HNS3_VECTOR_TX_IRQ BIT_ULL(0)
	188	#define HNS3_VECTOR_RX_IRQ BIT_ULL(1)
	189
	190	#define HNS3_VECTOR_NOT_INITED 0
	191	#define HNS3_VECTOR_INITED 1
	192
	193	#define HNS3_MAX_BD_SIZE 65535
	194	#define HNS3_MAX_BD_PER_FRAG 8
	195	#define HNS3_MAX_BD_PER_PKT MAX_SKB_FRAGS
	196
	197	#define HNS3_VECTOR_GL0_OFFSET 0x100
	198	#define HNS3_VECTOR_GL1_OFFSET 0x200
	199	#define HNS3_VECTOR_GL2_OFFSET 0x300
	200	#define HNS3_VECTOR_RL_OFFSET 0x900
	201	#define HNS3_VECTOR_RL_EN_B 6
	202
2b5251b7 HT	203	#define HNS3_RING_EN_B 0
2b5251b7 HT	204
76ad4f0e S	205	enum hns3_pkt_l3t_type {
	206	HNS3_L3T_NONE,
	207	HNS3_L3T_IPV6,
	208	HNS3_L3T_IPV4,
	209	HNS3_L3T_RESERVED
	210	};
	211
	212	enum hns3_pkt_l4t_type {
	213	HNS3_L4T_UNKNOWN,
	214	HNS3_L4T_TCP,
	215	HNS3_L4T_UDP,
	216	HNS3_L4T_SCTP
	217	};
	218
	219	enum hns3_pkt_ol3t_type {
	220	HNS3_OL3T_NONE,
	221	HNS3_OL3T_IPV6,
	222	HNS3_OL3T_IPV4_NO_CSUM,
	223	HNS3_OL3T_IPV4_CSUM
	224	};
	225
	226	enum hns3_pkt_tun_type {
	227	HNS3_TUN_NONE,
	228	HNS3_TUN_MAC_IN_UDP,
	229	HNS3_TUN_NVGRE,
	230	HNS3_TUN_OTHER
	231	};
	232
	233	/* hardware spec ring buffer format */
	234	struct __packed hns3_desc {
	235	__le64 addr;
	236	union {
	237	struct {
	238	__le16 vlan_tag;
	239	__le16 send_size;
	240	union {
	241	__le32 type_cs_vlan_tso_len;
	242	struct {
	243	__u8 type_cs_vlan_tso;
	244	__u8 l2_len;
	245	__u8 l3_len;
	246	__u8 l4_len;
	247	};
	248	};
	249	__le16 outer_vlan_tag;
	250	__le16 tv;
	251
	252	union {
	253	__le32 ol_type_vlan_len_msec;
	254	struct {
	255	__u8 ol_type_vlan_msec;
	256	__u8 ol2_len;
	257	__u8 ol3_len;
	258	__u8 ol4_len;
	259	};
	260	};
	261
	262	__le32 paylen;
	263	__le16 bdtp_fe_sc_vld_ra_ri;
	264	__le16 mss;
	265	} tx;
	266
	267	struct {
	268	__le32 l234_info;
269	__le16 pkt_len;
270	__le16 size;
271
272	__le32 rss_hash;
273	__le16 fd_id;
274	__le16 vlan_tag;
275
276	union {
277	__le32 ol_info;
278	struct {
279	__le16 o_dm_vlan_id_fb;
280	__le16 ot_vlan_tag;
281	};
282	};
283
284	__le32 bd_base_info;
285	} rx;
286	};
287	};
288
289	struct hns3_desc_cb {
290	dma_addr_t dma; /* dma address of this desc */
291	void buf; / cpu addr for a desc */
292
293	/* priv data for the desc, e.g. skb when use with ip stack*/
294	void *priv;
295	u16 page_offset;
296	u16 reuse_flag;
297
c8398c09	298	u32 length; /* length of the buffer */
76ad4f0e S	299
	300	/* desc type, used by the ring user to mark the type of the priv data */
	301	u16 type;
	302	};
	303
	304	enum hns3_pkt_l3type {
	305	HNS3_L3_TYPE_IPV4,
	306	HNS3_L3_TYPE_IPV6,
	307	HNS3_L3_TYPE_ARP,
	308	HNS3_L3_TYPE_RARP,
	309	HNS3_L3_TYPE_IPV4_OPT,
	310	HNS3_L3_TYPE_IPV6_EXT,
	311	HNS3_L3_TYPE_LLDP,
	312	HNS3_L3_TYPE_BPDU,
	313	HNS3_L3_TYPE_MAC_PAUSE,
	314	HNS3_L3_TYPE_PFC_PAUSE,/* 0x9*/
	315
	316	/* reserved for 0xA~0xB*/
	317
	318	HNS3_L3_TYPE_CNM = 0xc,
	319
	320	/* reserved for 0xD~0xE*/
	321
	322	HNS3_L3_TYPE_PARSE_FAIL = 0xf /* must be last */
	323	};
	324
	325	enum hns3_pkt_l4type {
	326	HNS3_L4_TYPE_UDP,
	327	HNS3_L4_TYPE_TCP,
	328	HNS3_L4_TYPE_GRE,
	329	HNS3_L4_TYPE_SCTP,
	330	HNS3_L4_TYPE_IGMP,
	331	HNS3_L4_TYPE_ICMP,
	332
	333	/* reserved for 0x6~0xE */
	334
	335	HNS3_L4_TYPE_PARSE_FAIL = 0xf /* must be last */
	336	};
	337
	338	enum hns3_pkt_ol3type {
	339	HNS3_OL3_TYPE_IPV4 = 0,
	340	HNS3_OL3_TYPE_IPV6,
	341	/* reserved for 0x2~0x3 */
	342	HNS3_OL3_TYPE_IPV4_OPT = 4,
	343	HNS3_OL3_TYPE_IPV6_EXT,
	344
	345	/* reserved for 0x6~0xE*/
	346
	347	HNS3_OL3_TYPE_PARSE_FAIL = 0xf /* must be last */
	348	};
	349
	350	enum hns3_pkt_ol4type {
	351	HNS3_OL4_TYPE_NO_TUN,
	352	HNS3_OL4_TYPE_MAC_IN_UDP,
	353	HNS3_OL4_TYPE_NVGRE,
	354	HNS3_OL4_TYPE_UNKNOWN
	355	};
	356
	357	struct ring_stats {
	358	u64 io_err_cnt;
	359	u64 sw_err_cnt;
	360	u64 seg_pkt_cnt;
	361	union {
	362	struct {
363	u64 tx_pkts;
364	u64 tx_bytes;
365	u64 tx_err_cnt;
366	u64 restart_queue;
367	u64 tx_busy;
368	};
369	struct {
370	u64 rx_pkts;
371	u64 rx_bytes;
372	u64 rx_err_cnt;
373	u64 reuse_pg_cnt;
374	u64 err_pkt_len;
375	u64 non_vld_descs;
376	u64 err_bd_num;
377	u64 l2_err;
378	u64 l3l4_csum_err;
379	};
380	};
381	};
382
383	struct hns3_enet_ring {
384	u8 __iomem io_base; / base io address for the ring */
385	struct hns3_desc desc; / dma map address space */
386	struct hns3_desc_cb *desc_cb;
387	struct hns3_enet_ring *next;
388	struct hns3_enet_tqp_vector *tqp_vector;
389	struct hnae3_queue *tqp;
390	char ring_name[HNS3_RING_NAME_LEN];
391	struct device dev; / will be used for DMA mapping of descriptors */
392
393	/* statistic */
394	struct ring_stats stats;
395	struct u64_stats_sync syncp;
396
397	dma_addr_t desc_dma_addr;
398	u32 buf_size; /* size for hnae_desc->addr, preset by AE */
399	u16 desc_num; /* total number of desc */
400	u16 max_desc_num_per_pkt;
401	u16 max_raw_data_sz_per_desc;
402	u16 max_pkt_size;
403	int next_to_use; /* idx of next spare desc */
404
405	/* idx of lastest sent desc, the ring is empty when equal to
406	* next_to_use
407	*/
408	int next_to_clean;
409
72b50a78	410	int pull_len; /* head length for current packet */
4110bcf6	411	u32 frag_num;
72b50a78 PL	412	unsigned char va; / first buffer address for current packet */
72b50a78 PL	413
76ad4f0e S	414	u32 flag; /* ring attribute */
	415	int irq_init_flag;
	416
	417	int numa_node;
	418	cpumask_t affinity_mask;
72b50a78 PL	419
	420	int pending_buf;
	421	struct sk_buff *skb;
4110bcf6	422	struct sk_buff *tail_skb;
76ad4f0e S	423	};
	424
	425	struct hns_queue;
	426
	427	struct hns3_nic_ring_data {
	428	struct hns3_enet_ring *ring;
	429	struct napi_struct napi;
	430	int queue_index;
	431	int (poll_one)(struct hns3_nic_ring_data , int, void *);
	432	void (ex_process)(struct hns3_nic_ring_data , struct sk_buff *);
	433	void (fini_process)(struct hns3_nic_ring_data );
	434	};
	435
	436	struct hns3_nic_ops {
	437	int (fill_desc)(struct hns3_enet_ring ring, void *priv,
91040825	438	int size, int frag_end, enum hns_desc_type type);
76ad4f0e S	439	int (maybe_stop_tx)(struct sk_buff *out_skb,
	440	int bnum, struct hns3_enet_ring ring);
	441	void (get_rxd_bnum)(u32 bnum_flag, int out_bnum);
	442	};
	443
	444	enum hns3_flow_level_range {
	445	HNS3_FLOW_LOW = 0,
	446	HNS3_FLOW_MID = 1,
	447	HNS3_FLOW_HIGH = 2,
	448	HNS3_FLOW_ULTRA = 3,
	449	};
	450
	451	enum hns3_link_mode_bits {
	452	HNS3_LM_FIBRE_BIT = BIT(0),
	453	HNS3_LM_AUTONEG_BIT = BIT(1),
	454	HNS3_LM_TP_BIT = BIT(2),
	455	HNS3_LM_PAUSE_BIT = BIT(3),
	456	HNS3_LM_BACKPLANE_BIT = BIT(4),
	457	HNS3_LM_10BASET_HALF_BIT = BIT(5),
	458	HNS3_LM_10BASET_FULL_BIT = BIT(6),
	459	HNS3_LM_100BASET_HALF_BIT = BIT(7),
	460	HNS3_LM_100BASET_FULL_BIT = BIT(8),
	461	HNS3_LM_1000BASET_FULL_BIT = BIT(9),
	462	HNS3_LM_10000BASEKR_FULL_BIT = BIT(10),
	463	HNS3_LM_25000BASEKR_FULL_BIT = BIT(11),
	464	HNS3_LM_40000BASELR4_FULL_BIT = BIT(12),
	465	HNS3_LM_50000BASEKR2_FULL_BIT = BIT(13),
	466	HNS3_LM_100000BASEKR4_FULL_BIT = BIT(14),
	467	HNS3_LM_COUNT = 15
	468	};
	469
5acd0356	470	#define HNS3_INT_GL_MAX 0x1FE0
fcff38e2 FL	471	#define HNS3_INT_GL_50K 0x0014
	472	#define HNS3_INT_GL_20K 0x0032
	473	#define HNS3_INT_GL_18K 0x0036
	474	#define HNS3_INT_GL_8K 0x007C
76ad4f0e	475
5acd0356 FL	476	#define HNS3_INT_RL_MAX 0x00EC
	477	#define HNS3_INT_RL_ENABLE_MASK 0x40
	478
d420d2de YL	479	struct hns3_enet_coalesce {
	480	u16 int_gl;
	481	u8 gl_adapt_enable;
	482	enum hns3_flow_level_range flow_level;
	483	};
	484
76ad4f0e S	485	struct hns3_enet_ring_group {
	486	/* array of pointers to rings */
	487	struct hns3_enet_ring *ring;
	488	u64 total_bytes; /* total bytes processed this group */
	489	u64 total_packets; /* total packets processed this group */
	490	u16 count;
d420d2de	491	struct hns3_enet_coalesce coal;
76ad4f0e S	492	};
	493
	494	struct hns3_enet_tqp_vector {
	495	struct hnae3_handle *handle;
	496	u8 __iomem *mask_addr;
	497	int vector_irq;
	498	int irq_init_flag;
	499
	500	u16 idx; /* index in the TQP vector array per handle. */
	501
	502	struct napi_struct napi;
	503
	504	struct hns3_enet_ring_group rx_group;
	505	struct hns3_enet_ring_group tx_group;
	506
15040788	507	cpumask_t affinity_mask;
76ad4f0e	508	u16 num_tqps; /* total number of tqps in TQP vector */
15040788	509	struct irq_affinity_notify affinity_notify;
76ad4f0e	510
76ad4f0e S	511	char name[HNAE3_INT_NAME_LEN];
76ad4f0e S	512
50477f37	513	unsigned long last_jiffies;
76ad4f0e S	514	} ____cacheline_internodealigned_in_smp;
	515
	516	enum hns3_udp_tnl_type {
	517	HNS3_UDP_TNL_VXLAN,
	518	HNS3_UDP_TNL_GENEVE,
	519	HNS3_UDP_TNL_MAX,
	520	};
	521
	522	struct hns3_udp_tunnel {
	523	u16 dst_port;
	524	int used;
	525	};
	526
	527	struct hns3_nic_priv {
	528	struct hnae3_handle *ae_handle;
	529	u32 enet_ver;
	530	u32 port_id;
	531	struct net_device *netdev;
	532	struct device *dev;
	533	struct hns3_nic_ops ops;
	534
	535	/**
	536	* the cb for nic to manage the ring buffer, the first half of the
	537	* array is for tx_ring and vice versa for the second half
	538	*/
	539	struct hns3_nic_ring_data *ring_data;
	540	struct hns3_enet_tqp_vector *tqp_vector;
	541	u16 vector_num;
	542
	543	/* The most recently read link state */
	544	int link;
	545	u64 tx_timeout_count;
	546
	547	unsigned long state;
	548
	549	struct timer_list service_timer;
	550
	551	struct work_struct service_task;
	552
	553	struct notifier_block notifier_block;
	554	/* Vxlan/Geneve information */
	555	struct hns3_udp_tunnel udp_tnl[HNS3_UDP_TNL_MAX];
103ce052	556	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
0378eccc HT	557	struct hns3_enet_coalesce tx_coal;
0378eccc HT	558	struct hns3_enet_coalesce rx_coal;
76ad4f0e S	559	};
	560
	561	union l3_hdr_info {
	562	struct iphdr *v4;
	563	struct ipv6hdr *v6;
	564	unsigned char *hdr;
	565	};
	566
	567	union l4_hdr_info {
	568	struct tcphdr *tcp;
	569	struct udphdr *udp;
	570	unsigned char *hdr;
	571	};
	572
	573	/* the distance between [begin, end) in a ring buffer
	574	* note: there is a unuse slot between the begin and the end
	575	*/
	576	static inline int ring_dist(struct hns3_enet_ring *ring, int begin, int end)
	577	{
	578	return (end - begin + ring->desc_num) % ring->desc_num;
	579	}
	580
	581	static inline int ring_space(struct hns3_enet_ring *ring)
	582	{
	583	return ring->desc_num -
	584	ring_dist(ring, ring->next_to_clean, ring->next_to_use) - 1;
	585	}
	586
	587	static inline int is_ring_empty(struct hns3_enet_ring *ring)
	588	{
	589	return ring->next_to_use == ring->next_to_clean;
	590	}
	591
2b5251b7 HT	592	static inline u32 hns3_read_reg(void __iomem *base, u32 reg)
	593	{
	594	return readl(base + reg);
	595	}
	596
76ad4f0e S	597	static inline void hns3_write_reg(void __iomem *base, u32 reg, u32 value)
	598	{
	599	u8 __iomem *reg_addr = READ_ONCE(base);
	600
	601	writel(value, reg_addr + reg);
	602	}
	603
7ce98982 JS	604	static inline bool hns3_dev_ongoing_func_reset(struct hnae3_ae_dev *ae_dev)
7ce98982 JS	605	{
1343c2f2	606	return (ae_dev && (ae_dev->reset_type == HNAE3_FUNC_RESET \|\|
26977990	607	ae_dev->reset_type == HNAE3_FLR_RESET \|\|
7885e906	608	ae_dev->reset_type == HNAE3_VF_FUNC_RESET \|\|
26977990	609	ae_dev->reset_type == HNAE3_VF_FULL_RESET \|\|
7885e906	610	ae_dev->reset_type == HNAE3_VF_PF_FUNC_RESET));
7ce98982 JS	611	}
7ce98982 JS	612
2b5251b7 HT	613	#define hns3_read_dev(a, reg) \
	614	hns3_read_reg((a)->io_base, (reg))
	615
3a11f446 HT	616	static inline bool hns3_nic_resetting(struct net_device *netdev)
	617	{
	618	struct hns3_nic_priv *priv = netdev_priv(netdev);
	619
	620	return test_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
	621	}
	622
76ad4f0e S	623	#define hns3_write_dev(a, reg, value) \
	624	hns3_write_reg((a)->io_base, (reg), (value))
	625
ccc23ef3	626	#define hnae3_queue_xmit(tqp, buf_num) writel_relaxed(buf_num, \
76ad4f0e S	627	(tqp)->io_base + HNS3_RING_TX_RING_TAIL_REG)
	628
	629	#define ring_to_dev(ring) (&(ring)->tqp->handle->pdev->dev)
	630
	631	#define ring_to_dma_dir(ring) (HNAE3_IS_TX_RING(ring) ? \
	632	DMA_TO_DEVICE : DMA_FROM_DEVICE)
	633
	634	#define tx_ring_data(priv, idx) ((priv)->ring_data[idx])
	635
ccc23ef3 PL	636	#define hnae3_buf_size(_ring) ((_ring)->buf_size)
	637	#define hnae3_page_order(_ring) (get_order(hnae3_buf_size(_ring)))
	638	#define hnae3_page_size(_ring) (PAGE_SIZE << hnae3_page_order(_ring))
76ad4f0e S	639
	640	/* iterator for handling rings in ring group */
	641	#define hns3_for_each_ring(pos, head) \
	642	for (pos = (head).ring; pos; pos = pos->next)
	643
9780cb97 YL	644	#define hns3_get_handle(ndev) \
	645	(((struct hns3_nic_priv *)netdev_priv(ndev))->ae_handle)
	646
5acd0356 FL	647	#define hns3_gl_usec_to_reg(int_gl) (int_gl >> 1)
	648	#define hns3_gl_round_down(int_gl) round_down(int_gl, 2)
	649
	650	#define hns3_rl_usec_to_reg(int_rl) (int_rl >> 2)
	651	#define hns3_rl_round_down(int_rl) round_down(int_rl, 4)
	652
76ad4f0e	653	void hns3_ethtool_set_ops(struct net_device *netdev);
f1f779ce PL	654	int hns3_set_channels(struct net_device *netdev,
f1f779ce PL	655	struct ethtool_channels *ch);
76ad4f0e	656
6a38a95f	657	void hns3_clean_tx_ring(struct hns3_enet_ring *ring);
5668abda L	658	int hns3_init_all_ring(struct hns3_nic_priv *priv);
5668abda L	659	int hns3_uninit_all_ring(struct hns3_nic_priv *priv);
e32a805a	660	int hns3_nic_reset_all_ring(struct hnae3_handle *h);
d43e5aca YL	661	netdev_tx_t hns3_nic_net_xmit(struct sk_buff skb, struct net_device netdev);
	662	int hns3_clean_rx_ring(
	663	struct hns3_enet_ring *ring, int budget,
	664	void (rx_fn)(struct hns3_enet_ring , struct sk_buff *));
986743db	665
5acd0356 FL	666	void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
	667	u32 gl_value);
	668	void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
	669	u32 gl_value);
	670	void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
	671	u32 rl_value);
	672
1e3653db	673	void hns3_enable_vlan_filter(struct net_device *netdev, bool enable);
abe62a63	674	int hns3_update_promisc_mode(struct net_device *netdev, u8 promisc_flags);
1e3653db	675
986743db YL	676	#ifdef CONFIG_HNS3_DCB
	677	void hns3_dcbnl_setup(struct hnae3_handle *handle);
	678	#else
	679	static inline void hns3_dcbnl_setup(struct hnae3_handle *handle) {}
	680	#endif
	681
a9556d8c	682	void hns3_dbg_init(struct hnae3_handle *handle);
	683	void hns3_dbg_uninit(struct hnae3_handle *handle);
	684	void hns3_dbg_register_debugfs(const char *debugfs_dir_name);
	685	void hns3_dbg_unregister_debugfs(void);
76ad4f0e	686	#endif