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igb: Add device support for flashless SKU of i210 device
[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / intel / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4b9ea462 4 Copyright(c) 2007-2013 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
876d2d6f
JK		 28#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
9d5c8243
AK		 30#include <linux/module.h>
31#include <linux/types.h>
32#include <linux/init.h>
b2cb09b1 33#include <linux/bitops.h>
9d5c8243
AK		 34#include <linux/vmalloc.h>
35#include <linux/pagemap.h>
36#include <linux/netdevice.h>
9d5c8243 37#include <linux/ipv6.h>
5a0e3ad6 38#include <linux/slab.h>
9d5c8243
AK		 39#include <net/checksum.h>
40#include <net/ip6_checksum.h>
c6cb090b 41#include <linux/net_tstamp.h>
9d5c8243
AK		 42#include <linux/mii.h>
43#include <linux/ethtool.h>
01789349 44#include <linux/if.h>
9d5c8243
AK		 45#include <linux/if_vlan.h>
46#include <linux/pci.h>
c54106bb 47#include <linux/pci-aspm.h>
9d5c8243
AK		 48#include <linux/delay.h>
49#include <linux/interrupt.h>
7d13a7d0
AD		 50#include <linux/ip.h>
51#include <linux/tcp.h>
52#include <linux/sctp.h>
9d5c8243 53#include <linux/if_ether.h>
40a914fa 54#include <linux/aer.h>
70c71606 55#include <linux/prefetch.h>
749ab2cd 56#include <linux/pm_runtime.h>
421e02f0 57#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 58#include <linux/dca.h>
59#endif
441fc6fd 60#include <linux/i2c.h>
9d5c8243
AK		 61#include "igb.h"
62
67b1b903
CW		 63#define MAJ 5
64#define MIN 0
65#define BUILD 3
0d1fe82d 66#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
929dd047 67__stringify(BUILD) "-k"
9d5c8243
AK		 68char igb_driver_name[] = "igb";
69char igb_driver_version[] = DRV_VERSION;
70static const char igb_driver_string[] =
71 "Intel(R) Gigabit Ethernet Network Driver";
4b9ea462
AA		 72static const char igb_copyright[] =
73 "Copyright (c) 2007-2013 Intel Corporation.";
9d5c8243 74
9d5c8243
AK		 75static const struct e1000_info *igb_info_tbl[] = {
76 [board_82575] = &e1000_82575_info,
77};
78
a3aa1884 79static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
ceb5f13b
CW		 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
f96a8a0b
CW		 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
53b87ce3
CW		 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
d2ba2ed8
AD		 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
55cac248
AD		 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
6493d24f 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
55cac248
AD		 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
308fb39a
JG		 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
1b5dda33
GJ		 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
2d064c06 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
b894fa26 110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
c8ea5ea9 111 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 112 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
113 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
114 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
115 /* required last entry */
116 {0, }
117};
118
119MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
120
121void igb_reset(struct igb_adapter *);
122static int igb_setup_all_tx_resources(struct igb_adapter *);
123static int igb_setup_all_rx_resources(struct igb_adapter *);
124static void igb_free_all_tx_resources(struct igb_adapter *);
125static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 126static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243 127static int igb_probe(struct pci_dev *, const struct pci_device_id *);
9f9a12f8 128static void igb_remove(struct pci_dev *pdev);
9d5c8243
AK		 129static int igb_sw_init(struct igb_adapter *);
130static int igb_open(struct net_device *);
131static int igb_close(struct net_device *);
53c7d064 132static void igb_configure(struct igb_adapter *);
9d5c8243
AK		 133static void igb_configure_tx(struct igb_adapter *);
134static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 135static void igb_clean_all_tx_rings(struct igb_adapter *);
136static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 137static void igb_clean_tx_ring(struct igb_ring *);
138static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 139static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 140static void igb_update_phy_info(unsigned long);
141static void igb_watchdog(unsigned long);
142static void igb_watchdog_task(struct work_struct *);
cd392f5c 143static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
12dcd86b
ED		 144static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
145 struct rtnl_link_stats64 *stats);
9d5c8243
AK		 146static int igb_change_mtu(struct net_device *, int);
147static int igb_set_mac(struct net_device *, void *);
68d480c4 148static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 149static irqreturn_t igb_intr(int irq, void *);
150static irqreturn_t igb_intr_msi(int irq, void *);
151static irqreturn_t igb_msix_other(int irq, void *);
047e0030 152static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 153#ifdef CONFIG_IGB_DCA
047e0030 154static void igb_update_dca(struct igb_q_vector *);
fe4506b6 155static void igb_setup_dca(struct igb_adapter *);
421e02f0 156#endif /* CONFIG_IGB_DCA */
661086df 157static int igb_poll(struct napi_struct *, int);
13fde97a 158static bool igb_clean_tx_irq(struct igb_q_vector *);
cd392f5c 159static bool igb_clean_rx_irq(struct igb_q_vector *, int);
9d5c8243
AK		 160static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
161static void igb_tx_timeout(struct net_device *);
162static void igb_reset_task(struct work_struct *);
c8f44aff 163static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features);
80d5c368
PM		 164static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
165static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
9d5c8243 166static void igb_restore_vlan(struct igb_adapter *);
26ad9178 167static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 168static void igb_ping_all_vfs(struct igb_adapter *);
169static void igb_msg_task(struct igb_adapter *);
4ae196df 170static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 171static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 172static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
8151d294
WM		 173static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
174static int igb_ndo_set_vf_vlan(struct net_device *netdev,
175 int vf, u16 vlan, u8 qos);
176static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
70ea4783
LL		 177static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
178 bool setting);
8151d294
WM		 179static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
180 struct ifla_vf_info *ivi);
17dc566c 181static void igb_check_vf_rate_limit(struct igb_adapter *);
46a01698
RL		 182
183#ifdef CONFIG_PCI_IOV
0224d663 184static int igb_vf_configure(struct igb_adapter *adapter, int vf);
46a01698 185#endif
9d5c8243 186
9d5c8243 187#ifdef CONFIG_PM
d9dd966d 188#ifdef CONFIG_PM_SLEEP
749ab2cd 189static int igb_suspend(struct device *);
d9dd966d 190#endif
749ab2cd
YZ		 191static int igb_resume(struct device *);
192#ifdef CONFIG_PM_RUNTIME
193static int igb_runtime_suspend(struct device *dev);
194static int igb_runtime_resume(struct device *dev);
195static int igb_runtime_idle(struct device *dev);
196#endif
197static const struct dev_pm_ops igb_pm_ops = {
198 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
199 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
200 igb_runtime_idle)
201};
9d5c8243
AK		 202#endif
203static void igb_shutdown(struct pci_dev *);
fa44f2f1 204static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
421e02f0 205#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 206static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
207static struct notifier_block dca_notifier = {
208 .notifier_call = igb_notify_dca,
209 .next = NULL,
210 .priority = 0
211};
212#endif
9d5c8243
AK		 213#ifdef CONFIG_NET_POLL_CONTROLLER
214/* for netdump / net console */
215static void igb_netpoll(struct net_device *);
216#endif
37680117 217#ifdef CONFIG_PCI_IOV
2a3abf6d
AD		 218static unsigned int max_vfs = 0;
219module_param(max_vfs, uint, 0);
220MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
221 "per physical function");
222#endif /* CONFIG_PCI_IOV */
223
9d5c8243
AK		 224static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
225 pci_channel_state_t);
226static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
227static void igb_io_resume(struct pci_dev *);
228
3646f0e5 229static const struct pci_error_handlers igb_err_handler = {
9d5c8243
AK		 230 .error_detected = igb_io_error_detected,
231 .slot_reset = igb_io_slot_reset,
232 .resume = igb_io_resume,
233};
234
b6e0c419 235static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
9d5c8243
AK		 236
237static struct pci_driver igb_driver = {
238 .name = igb_driver_name,
239 .id_table = igb_pci_tbl,
240 .probe = igb_probe,
9f9a12f8 241 .remove = igb_remove,
9d5c8243 242#ifdef CONFIG_PM
749ab2cd 243 .driver.pm = &igb_pm_ops,
9d5c8243
AK		 244#endif
245 .shutdown = igb_shutdown,
fa44f2f1 246 .sriov_configure = igb_pci_sriov_configure,
9d5c8243
AK		 247 .err_handler = &igb_err_handler
248};
249
250MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
251MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
252MODULE_LICENSE("GPL");
253MODULE_VERSION(DRV_VERSION);
254
b3f4d599 255#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
256static int debug = -1;
257module_param(debug, int, 0);
258MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
259
c97ec42a
TI		 260struct igb_reg_info {
261 u32 ofs;
262 char *name;
263};
264
265static const struct igb_reg_info igb_reg_info_tbl[] = {
266
267 /* General Registers */
268 {E1000_CTRL, "CTRL"},
269 {E1000_STATUS, "STATUS"},
270 {E1000_CTRL_EXT, "CTRL_EXT"},
271
272 /* Interrupt Registers */
273 {E1000_ICR, "ICR"},
274
275 /* RX Registers */
276 {E1000_RCTL, "RCTL"},
277 {E1000_RDLEN(0), "RDLEN"},
278 {E1000_RDH(0), "RDH"},
279 {E1000_RDT(0), "RDT"},
280 {E1000_RXDCTL(0), "RXDCTL"},
281 {E1000_RDBAL(0), "RDBAL"},
282 {E1000_RDBAH(0), "RDBAH"},
283
284 /* TX Registers */
285 {E1000_TCTL, "TCTL"},
286 {E1000_TDBAL(0), "TDBAL"},
287 {E1000_TDBAH(0), "TDBAH"},
288 {E1000_TDLEN(0), "TDLEN"},
289 {E1000_TDH(0), "TDH"},
290 {E1000_TDT(0), "TDT"},
291 {E1000_TXDCTL(0), "TXDCTL"},
292 {E1000_TDFH, "TDFH"},
293 {E1000_TDFT, "TDFT"},
294 {E1000_TDFHS, "TDFHS"},
295 {E1000_TDFPC, "TDFPC"},
296
297 /* List Terminator */
298 {}
299};
300
b980ac18 301/* igb_regdump - register printout routine */
c97ec42a
TI		 302static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
303{
304 int n = 0;
305 char rname[16];
306 u32 regs[8];
307
308 switch (reginfo->ofs) {
309 case E1000_RDLEN(0):
310 for (n = 0; n < 4; n++)
311 regs[n] = rd32(E1000_RDLEN(n));
312 break;
313 case E1000_RDH(0):
314 for (n = 0; n < 4; n++)
315 regs[n] = rd32(E1000_RDH(n));
316 break;
317 case E1000_RDT(0):
318 for (n = 0; n < 4; n++)
319 regs[n] = rd32(E1000_RDT(n));
320 break;
321 case E1000_RXDCTL(0):
322 for (n = 0; n < 4; n++)
323 regs[n] = rd32(E1000_RXDCTL(n));
324 break;
325 case E1000_RDBAL(0):
326 for (n = 0; n < 4; n++)
327 regs[n] = rd32(E1000_RDBAL(n));
328 break;
329 case E1000_RDBAH(0):
330 for (n = 0; n < 4; n++)
331 regs[n] = rd32(E1000_RDBAH(n));
332 break;
333 case E1000_TDBAL(0):
334 for (n = 0; n < 4; n++)
335 regs[n] = rd32(E1000_RDBAL(n));
336 break;
337 case E1000_TDBAH(0):
338 for (n = 0; n < 4; n++)
339 regs[n] = rd32(E1000_TDBAH(n));
340 break;
341 case E1000_TDLEN(0):
342 for (n = 0; n < 4; n++)
343 regs[n] = rd32(E1000_TDLEN(n));
344 break;
345 case E1000_TDH(0):
346 for (n = 0; n < 4; n++)
347 regs[n] = rd32(E1000_TDH(n));
348 break;
349 case E1000_TDT(0):
350 for (n = 0; n < 4; n++)
351 regs[n] = rd32(E1000_TDT(n));
352 break;
353 case E1000_TXDCTL(0):
354 for (n = 0; n < 4; n++)
355 regs[n] = rd32(E1000_TXDCTL(n));
356 break;
357 default:
876d2d6f 358 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
c97ec42a
TI		 359 return;
360 }
361
362 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
876d2d6f
JK		 363 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
364 regs[2], regs[3]);
c97ec42a
TI		 365}
366
b980ac18 367/* igb_dump - Print registers, Tx-rings and Rx-rings */
c97ec42a
TI		 368static void igb_dump(struct igb_adapter *adapter)
369{
370 struct net_device *netdev = adapter->netdev;
371 struct e1000_hw *hw = &adapter->hw;
372 struct igb_reg_info *reginfo;
c97ec42a
TI		 373 struct igb_ring *tx_ring;
374 union e1000_adv_tx_desc *tx_desc;
375 struct my_u0 { u64 a; u64 b; } *u0;
c97ec42a
TI		 376 struct igb_ring *rx_ring;
377 union e1000_adv_rx_desc *rx_desc;
378 u32 staterr;
6ad4edfc 379 u16 i, n;
c97ec42a
TI		 380
381 if (!netif_msg_hw(adapter))
382 return;
383
384 /* Print netdevice Info */
385 if (netdev) {
386 dev_info(&adapter->pdev->dev, "Net device Info\n");
876d2d6f
JK		 387 pr_info("Device Name state trans_start "
388 "last_rx\n");
389 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
390 netdev->state, netdev->trans_start, netdev->last_rx);
c97ec42a
TI		 391 }
392
393 /* Print Registers */
394 dev_info(&adapter->pdev->dev, "Register Dump\n");
876d2d6f 395 pr_info(" Register Name Value\n");
c97ec42a
TI		 396 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
397 reginfo->name; reginfo++) {
398 igb_regdump(hw, reginfo);
399 }
400
401 /* Print TX Ring Summary */
402 if (!netdev || !netif_running(netdev))
403 goto exit;
404
405 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
876d2d6f 406 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
c97ec42a 407 for (n = 0; n < adapter->num_tx_queues; n++) {
06034649 408 struct igb_tx_buffer *buffer_info;
c97ec42a 409 tx_ring = adapter->tx_ring[n];
06034649 410 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
876d2d6f
JK		 411 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
412 n, tx_ring->next_to_use, tx_ring->next_to_clean,
c9f14bf3
AD		 413 (u64)dma_unmap_addr(buffer_info, dma),
414 dma_unmap_len(buffer_info, len),
876d2d6f
JK		 415 buffer_info->next_to_watch,
416 (u64)buffer_info->time_stamp);
c97ec42a
TI		 417 }
418
419 /* Print TX Rings */
420 if (!netif_msg_tx_done(adapter))
421 goto rx_ring_summary;
422
423 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
424
425 /* Transmit Descriptor Formats
426 *
427 * Advanced Transmit Descriptor
428 * +--------------------------------------------------------------+
429 * 0 | Buffer Address [63:0] |
430 * +--------------------------------------------------------------+
431 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
432 * +--------------------------------------------------------------+
433 * 63 46 45 40 39 38 36 35 32 31 24 15 0
434 */
435
436 for (n = 0; n < adapter->num_tx_queues; n++) {
437 tx_ring = adapter->tx_ring[n];
876d2d6f
JK		 438 pr_info("------------------------------------\n");
439 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
440 pr_info("------------------------------------\n");
441 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] "
442 "[bi->dma ] leng ntw timestamp "
443 "bi->skb\n");
c97ec42a
TI		 444
445 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
876d2d6f 446 const char *next_desc;
06034649 447 struct igb_tx_buffer *buffer_info;
60136906 448 tx_desc = IGB_TX_DESC(tx_ring, i);
06034649 449 buffer_info = &tx_ring->tx_buffer_info[i];
c97ec42a 450 u0 = (struct my_u0 *)tx_desc;
876d2d6f
JK		 451 if (i == tx_ring->next_to_use &&
452 i == tx_ring->next_to_clean)
453 next_desc = " NTC/U";
454 else if (i == tx_ring->next_to_use)
455 next_desc = " NTU";
456 else if (i == tx_ring->next_to_clean)
457 next_desc = " NTC";
458 else
459 next_desc = "";
460
461 pr_info("T [0x%03X] %016llX %016llX %016llX"
462 " %04X %p %016llX %p%s\n", i,
c97ec42a
TI		 463 le64_to_cpu(u0->a),
464 le64_to_cpu(u0->b),
c9f14bf3
AD		 465 (u64)dma_unmap_addr(buffer_info, dma),
466 dma_unmap_len(buffer_info, len),
c97ec42a
TI		 467 buffer_info->next_to_watch,
468 (u64)buffer_info->time_stamp,
876d2d6f 469 buffer_info->skb, next_desc);
c97ec42a 470
b669588a 471 if (netif_msg_pktdata(adapter) && buffer_info->skb)
c97ec42a
TI		 472 print_hex_dump(KERN_INFO, "",
473 DUMP_PREFIX_ADDRESS,
b669588a 474 16, 1, buffer_info->skb->data,
c9f14bf3
AD		 475 dma_unmap_len(buffer_info, len),
476 true);
c97ec42a
TI		 477 }
478 }
479
480 /* Print RX Rings Summary */
481rx_ring_summary:
482 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
876d2d6f 483 pr_info("Queue [NTU] [NTC]\n");
c97ec42a
TI		 484 for (n = 0; n < adapter->num_rx_queues; n++) {
485 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 486 pr_info(" %5d %5X %5X\n",
487 n, rx_ring->next_to_use, rx_ring->next_to_clean);
c97ec42a
TI		 488 }
489
490 /* Print RX Rings */
491 if (!netif_msg_rx_status(adapter))
492 goto exit;
493
494 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
495
496 /* Advanced Receive Descriptor (Read) Format
497 * 63 1 0
498 * +-----------------------------------------------------+
499 * 0 | Packet Buffer Address [63:1] |A0/NSE|
500 * +----------------------------------------------+------+
501 * 8 | Header Buffer Address [63:1] | DD |
502 * +-----------------------------------------------------+
503 *
504 *
505 * Advanced Receive Descriptor (Write-Back) Format
506 *
507 * 63 48 47 32 31 30 21 20 17 16 4 3 0
508 * +------------------------------------------------------+
509 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
510 * | Checksum Ident | | | | Type | Type |
511 * +------------------------------------------------------+
512 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
513 * +------------------------------------------------------+
514 * 63 48 47 32 31 20 19 0
515 */
516
517 for (n = 0; n < adapter->num_rx_queues; n++) {
518 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 519 pr_info("------------------------------------\n");
520 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
521 pr_info("------------------------------------\n");
522 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] "
523 "[bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
524 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] -----"
525 "----------- [bi->skb] <-- Adv Rx Write-Back format\n");
c97ec42a
TI		 526
527 for (i = 0; i < rx_ring->count; i++) {
876d2d6f 528 const char *next_desc;
06034649
AD		 529 struct igb_rx_buffer *buffer_info;
530 buffer_info = &rx_ring->rx_buffer_info[i];
60136906 531 rx_desc = IGB_RX_DESC(rx_ring, i);
c97ec42a
TI		 532 u0 = (struct my_u0 *)rx_desc;
533 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
876d2d6f
JK		 534
535 if (i == rx_ring->next_to_use)
536 next_desc = " NTU";
537 else if (i == rx_ring->next_to_clean)
538 next_desc = " NTC";
539 else
540 next_desc = "";
541
c97ec42a
TI		 542 if (staterr & E1000_RXD_STAT_DD) {
543 /* Descriptor Done */
1a1c225b
AD		 544 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
545 "RWB", i,
c97ec42a
TI		 546 le64_to_cpu(u0->a),
547 le64_to_cpu(u0->b),
1a1c225b 548 next_desc);
c97ec42a 549 } else {
1a1c225b
AD		 550 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
551 "R ", i,
c97ec42a
TI		 552 le64_to_cpu(u0->a),
553 le64_to_cpu(u0->b),
554 (u64)buffer_info->dma,
1a1c225b 555 next_desc);
c97ec42a 556
b669588a 557 if (netif_msg_pktdata(adapter) &&
1a1c225b 558 buffer_info->dma && buffer_info->page) {
44390ca6
AD		 559 print_hex_dump(KERN_INFO, "",
560 DUMP_PREFIX_ADDRESS,
561 16, 1,
b669588a
ET		 562 page_address(buffer_info->page) +
563 buffer_info->page_offset,
de78d1f9 564 IGB_RX_BUFSZ, true);
c97ec42a
TI		 565 }
566 }
c97ec42a
TI		 567 }
568 }
569
570exit:
571 return;
572}
573
b980ac18
JK		 574/**
575 * igb_get_i2c_data - Reads the I2C SDA data bit
441fc6fd
CW		 576 * @hw: pointer to hardware structure
577 * @i2cctl: Current value of I2CCTL register
578 *
579 * Returns the I2C data bit value
b980ac18 580 **/
441fc6fd
CW		 581static int igb_get_i2c_data(void *data)
582{
583 struct igb_adapter *adapter = (struct igb_adapter *)data;
584 struct e1000_hw *hw = &adapter->hw;
585 s32 i2cctl = rd32(E1000_I2CPARAMS);
586
587 return ((i2cctl & E1000_I2C_DATA_IN) != 0);
588}
589
b980ac18
JK		 590/**
591 * igb_set_i2c_data - Sets the I2C data bit
441fc6fd
CW		 592 * @data: pointer to hardware structure
593 * @state: I2C data value (0 or 1) to set
594 *
595 * Sets the I2C data bit
b980ac18 596 **/
441fc6fd
CW		 597static void igb_set_i2c_data(void *data, int state)
598{
599 struct igb_adapter *adapter = (struct igb_adapter *)data;
600 struct e1000_hw *hw = &adapter->hw;
601 s32 i2cctl = rd32(E1000_I2CPARAMS);
602
603 if (state)
604 i2cctl |= E1000_I2C_DATA_OUT;
605 else
606 i2cctl &= ~E1000_I2C_DATA_OUT;
607
608 i2cctl &= ~E1000_I2C_DATA_OE_N;
609 i2cctl |= E1000_I2C_CLK_OE_N;
610 wr32(E1000_I2CPARAMS, i2cctl);
611 wrfl();
612
613}
614
b980ac18
JK		 615/**
616 * igb_set_i2c_clk - Sets the I2C SCL clock
441fc6fd
CW		 617 * @data: pointer to hardware structure
618 * @state: state to set clock
619 *
620 * Sets the I2C clock line to state
b980ac18 621 **/
441fc6fd
CW		 622static void igb_set_i2c_clk(void *data, int state)
623{
624 struct igb_adapter *adapter = (struct igb_adapter *)data;
625 struct e1000_hw *hw = &adapter->hw;
626 s32 i2cctl = rd32(E1000_I2CPARAMS);
627
628 if (state) {
629 i2cctl |= E1000_I2C_CLK_OUT;
630 i2cctl &= ~E1000_I2C_CLK_OE_N;
631 } else {
632 i2cctl &= ~E1000_I2C_CLK_OUT;
633 i2cctl &= ~E1000_I2C_CLK_OE_N;
634 }
635 wr32(E1000_I2CPARAMS, i2cctl);
636 wrfl();
637}
638
b980ac18
JK		 639/**
640 * igb_get_i2c_clk - Gets the I2C SCL clock state
441fc6fd
CW		 641 * @data: pointer to hardware structure
642 *
643 * Gets the I2C clock state
b980ac18 644 **/
441fc6fd
CW		 645static int igb_get_i2c_clk(void *data)
646{
647 struct igb_adapter *adapter = (struct igb_adapter *)data;
648 struct e1000_hw *hw = &adapter->hw;
649 s32 i2cctl = rd32(E1000_I2CPARAMS);
650
651 return ((i2cctl & E1000_I2C_CLK_IN) != 0);
652}
653
654static const struct i2c_algo_bit_data igb_i2c_algo = {
655 .setsda = igb_set_i2c_data,
656 .setscl = igb_set_i2c_clk,
657 .getsda = igb_get_i2c_data,
658 .getscl = igb_get_i2c_clk,
659 .udelay = 5,
660 .timeout = 20,
661};
662
9d5c8243 663/**
b980ac18
JK		 664 * igb_get_hw_dev - return device
665 * @hw: pointer to hardware structure
666 *
667 * used by hardware layer to print debugging information
9d5c8243 668 **/
c041076a 669struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
9d5c8243
AK		 670{
671 struct igb_adapter *adapter = hw->back;
c041076a 672 return adapter->netdev;
9d5c8243 673}
38c845c7 674
9d5c8243 675/**
b980ac18 676 * igb_init_module - Driver Registration Routine
9d5c8243 677 *
b980ac18
JK		 678 * igb_init_module is the first routine called when the driver is
679 * loaded. All it does is register with the PCI subsystem.
9d5c8243
AK		 680 **/
681static int __init igb_init_module(void)
682{
683 int ret;
876d2d6f 684 pr_info("%s - version %s\n",
9d5c8243
AK		 685 igb_driver_string, igb_driver_version);
686
876d2d6f 687 pr_info("%s\n", igb_copyright);
9d5c8243 688
421e02f0 689#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 690 dca_register_notify(&dca_notifier);
691#endif
bbd98fe4 692 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 693 return ret;
694}
695
696module_init(igb_init_module);
697
698/**
b980ac18 699 * igb_exit_module - Driver Exit Cleanup Routine
9d5c8243 700 *
b980ac18
JK		 701 * igb_exit_module is called just before the driver is removed
702 * from memory.
9d5c8243
AK		 703 **/
704static void __exit igb_exit_module(void)
705{
421e02f0 706#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 707 dca_unregister_notify(&dca_notifier);
708#endif
9d5c8243
AK		 709 pci_unregister_driver(&igb_driver);
710}
711
712module_exit(igb_exit_module);
713
26bc19ec
AD		 714#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
715/**
b980ac18
JK		 716 * igb_cache_ring_register - Descriptor ring to register mapping
717 * @adapter: board private structure to initialize
26bc19ec 718 *
b980ac18
JK		 719 * Once we know the feature-set enabled for the device, we'll cache
720 * the register offset the descriptor ring is assigned to.
26bc19ec
AD		 721 **/
722static void igb_cache_ring_register(struct igb_adapter *adapter)
723{
ee1b9f06 724 int i = 0, j = 0;
047e0030 725 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 726
727 switch (adapter->hw.mac.type) {
728 case e1000_82576:
729 /* The queues are allocated for virtualization such that VF 0
730 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
731 * In order to avoid collision we start at the first free queue
732 * and continue consuming queues in the same sequence
733 */
ee1b9f06 734 if (adapter->vfs_allocated_count) {
a99955fc 735 for (; i < adapter->rss_queues; i++)
3025a446 736 adapter->rx_ring[i]->reg_idx = rbase_offset +
b980ac18 737 Q_IDX_82576(i);
ee1b9f06 738 }
26bc19ec 739 case e1000_82575:
55cac248 740 case e1000_82580:
d2ba2ed8 741 case e1000_i350:
ceb5f13b 742 case e1000_i354:
f96a8a0b
CW		 743 case e1000_i210:
744 case e1000_i211:
26bc19ec 745 default:
ee1b9f06 746 for (; i < adapter->num_rx_queues; i++)
3025a446 747 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
ee1b9f06 748 for (; j < adapter->num_tx_queues; j++)
3025a446 749 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
26bc19ec
AD		 750 break;
751 }
752}
753
4be000c8
AD		 754/**
755 * igb_write_ivar - configure ivar for given MSI-X vector
756 * @hw: pointer to the HW structure
757 * @msix_vector: vector number we are allocating to a given ring
758 * @index: row index of IVAR register to write within IVAR table
759 * @offset: column offset of in IVAR, should be multiple of 8
760 *
761 * This function is intended to handle the writing of the IVAR register
762 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
763 * each containing an cause allocation for an Rx and Tx ring, and a
764 * variable number of rows depending on the number of queues supported.
765 **/
766static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
767 int index, int offset)
768{
769 u32 ivar = array_rd32(E1000_IVAR0, index);
770
771 /* clear any bits that are currently set */
772 ivar &= ~((u32)0xFF << offset);
773
774 /* write vector and valid bit */
775 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
776
777 array_wr32(E1000_IVAR0, index, ivar);
778}
779
9d5c8243 780#define IGB_N0_QUEUE -1
047e0030 781static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243 782{
047e0030 783 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 784 struct e1000_hw *hw = &adapter->hw;
047e0030
AD		 785 int rx_queue = IGB_N0_QUEUE;
786 int tx_queue = IGB_N0_QUEUE;
4be000c8 787 u32 msixbm = 0;
047e0030 788
0ba82994
AD		 789 if (q_vector->rx.ring)
790 rx_queue = q_vector->rx.ring->reg_idx;
791 if (q_vector->tx.ring)
792 tx_queue = q_vector->tx.ring->reg_idx;
2d064c06
AD		 793
794 switch (hw->mac.type) {
795 case e1000_82575:
9d5c8243 796 /* The 82575 assigns vectors using a bitmask, which matches the
b980ac18
JK		 797 * bitmask for the EICR/EIMS/EIMC registers. To assign one
798 * or more queues to a vector, we write the appropriate bits
799 * into the MSIXBM register for that vector.
800 */
047e0030 801 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 802 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 803 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 804 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
feeb2721
AD		 805 if (!adapter->msix_entries && msix_vector == 0)
806 msixbm |= E1000_EIMS_OTHER;
9d5c8243 807 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 808 q_vector->eims_value = msixbm;
2d064c06
AD		 809 break;
810 case e1000_82576:
b980ac18 811 /* 82576 uses a table that essentially consists of 2 columns
4be000c8
AD		 812 * with 8 rows. The ordering is column-major so we use the
813 * lower 3 bits as the row index, and the 4th bit as the
814 * column offset.
815 */
816 if (rx_queue > IGB_N0_QUEUE)
817 igb_write_ivar(hw, msix_vector,
818 rx_queue & 0x7,
819 (rx_queue & 0x8) << 1);
820 if (tx_queue > IGB_N0_QUEUE)
821 igb_write_ivar(hw, msix_vector,
822 tx_queue & 0x7,
823 ((tx_queue & 0x8) << 1) + 8);
047e0030 824 q_vector->eims_value = 1 << msix_vector;
2d064c06 825 break;
55cac248 826 case e1000_82580:
d2ba2ed8 827 case e1000_i350:
ceb5f13b 828 case e1000_i354:
f96a8a0b
CW		 829 case e1000_i210:
830 case e1000_i211:
b980ac18 831 /* On 82580 and newer adapters the scheme is similar to 82576
4be000c8
AD		 832 * however instead of ordering column-major we have things
833 * ordered row-major. So we traverse the table by using
834 * bit 0 as the column offset, and the remaining bits as the
835 * row index.
836 */
837 if (rx_queue > IGB_N0_QUEUE)
838 igb_write_ivar(hw, msix_vector,
839 rx_queue >> 1,
840 (rx_queue & 0x1) << 4);
841 if (tx_queue > IGB_N0_QUEUE)
842 igb_write_ivar(hw, msix_vector,
843 tx_queue >> 1,
844 ((tx_queue & 0x1) << 4) + 8);
55cac248
AD		 845 q_vector->eims_value = 1 << msix_vector;
846 break;
2d064c06
AD		 847 default:
848 BUG();
849 break;
850 }
26b39276
AD		 851
852 /* add q_vector eims value to global eims_enable_mask */
853 adapter->eims_enable_mask |= q_vector->eims_value;
854
855 /* configure q_vector to set itr on first interrupt */
856 q_vector->set_itr = 1;
9d5c8243
AK		 857}
858
859/**
b980ac18
JK		 860 * igb_configure_msix - Configure MSI-X hardware
861 * @adapter: board private structure to initialize
9d5c8243 862 *
b980ac18
JK		 863 * igb_configure_msix sets up the hardware to properly
864 * generate MSI-X interrupts.
9d5c8243
AK		 865 **/
866static void igb_configure_msix(struct igb_adapter *adapter)
867{
868 u32 tmp;
869 int i, vector = 0;
870 struct e1000_hw *hw = &adapter->hw;
871
872 adapter->eims_enable_mask = 0;
9d5c8243
AK		 873
874 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 875 switch (hw->mac.type) {
876 case e1000_82575:
9d5c8243
AK		 877 tmp = rd32(E1000_CTRL_EXT);
878 /* enable MSI-X PBA support*/
879 tmp |= E1000_CTRL_EXT_PBA_CLR;
880
881 /* Auto-Mask interrupts upon ICR read. */
882 tmp |= E1000_CTRL_EXT_EIAME;
883 tmp |= E1000_CTRL_EXT_IRCA;
884
885 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 886
887 /* enable msix_other interrupt */
b980ac18 888 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
844290e5 889 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 890
2d064c06
AD		 891 break;
892
893 case e1000_82576:
55cac248 894 case e1000_82580:
d2ba2ed8 895 case e1000_i350:
ceb5f13b 896 case e1000_i354:
f96a8a0b
CW		 897 case e1000_i210:
898 case e1000_i211:
047e0030 899 /* Turn on MSI-X capability first, or our settings
b980ac18
JK		 900 * won't stick. And it will take days to debug.
901 */
047e0030 902 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
b980ac18
JK		 903 E1000_GPIE_PBA | E1000_GPIE_EIAME |
904 E1000_GPIE_NSICR);
047e0030
AD		 905
906 /* enable msix_other interrupt */
907 adapter->eims_other = 1 << vector;
2d064c06 908 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 909
047e0030 910 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 911 break;
912 default:
913 /* do nothing, since nothing else supports MSI-X */
914 break;
915 } /* switch (hw->mac.type) */
047e0030
AD		 916
917 adapter->eims_enable_mask |= adapter->eims_other;
918
26b39276
AD		 919 for (i = 0; i < adapter->num_q_vectors; i++)
920 igb_assign_vector(adapter->q_vector[i], vector++);
047e0030 921
9d5c8243
AK		 922 wrfl();
923}
924
925/**
b980ac18
JK		 926 * igb_request_msix - Initialize MSI-X interrupts
927 * @adapter: board private structure to initialize
9d5c8243 928 *
b980ac18
JK		 929 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
930 * kernel.
9d5c8243
AK		 931 **/
932static int igb_request_msix(struct igb_adapter *adapter)
933{
934 struct net_device *netdev = adapter->netdev;
047e0030 935 struct e1000_hw *hw = &adapter->hw;
52285b76 936 int i, err = 0, vector = 0, free_vector = 0;
9d5c8243 937
047e0030 938 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18 939 igb_msix_other, 0, netdev->name, adapter);
047e0030 940 if (err)
52285b76 941 goto err_out;
047e0030
AD		 942
943 for (i = 0; i < adapter->num_q_vectors; i++) {
944 struct igb_q_vector *q_vector = adapter->q_vector[i];
945
52285b76
SA		 946 vector++;
947
047e0030
AD		 948 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
949
0ba82994 950 if (q_vector->rx.ring && q_vector->tx.ring)
047e0030 951 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
0ba82994
AD		 952 q_vector->rx.ring->queue_index);
953 else if (q_vector->tx.ring)
047e0030 954 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
0ba82994
AD		 955 q_vector->tx.ring->queue_index);
956 else if (q_vector->rx.ring)
047e0030 957 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
0ba82994 958 q_vector->rx.ring->queue_index);
9d5c8243 959 else
047e0030
AD		 960 sprintf(q_vector->name, "%s-unused", netdev->name);
961
9d5c8243 962 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18
JK		 963 igb_msix_ring, 0, q_vector->name,
964 q_vector);
9d5c8243 965 if (err)
52285b76 966 goto err_free;
9d5c8243
AK		 967 }
968
9d5c8243
AK		 969 igb_configure_msix(adapter);
970 return 0;
52285b76
SA		 971
972err_free:
973 /* free already assigned IRQs */
974 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
975
976 vector--;
977 for (i = 0; i < vector; i++) {
978 free_irq(adapter->msix_entries[free_vector++].vector,
979 adapter->q_vector[i]);
980 }
981err_out:
9d5c8243
AK		 982 return err;
983}
984
985static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
986{
987 if (adapter->msix_entries) {
988 pci_disable_msix(adapter->pdev);
989 kfree(adapter->msix_entries);
990 adapter->msix_entries = NULL;
047e0030 991 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 992 pci_disable_msi(adapter->pdev);
047e0030 993 }
9d5c8243
AK		 994}
995
5536d210 996/**
b980ac18
JK		 997 * igb_free_q_vector - Free memory allocated for specific interrupt vector
998 * @adapter: board private structure to initialize
999 * @v_idx: Index of vector to be freed
5536d210 1000 *
b980ac18
JK		 1001 * This function frees the memory allocated to the q_vector. In addition if
1002 * NAPI is enabled it will delete any references to the NAPI struct prior
1003 * to freeing the q_vector.
5536d210
AD		 1004 **/
1005static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
1006{
1007 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1008
1009 if (q_vector->tx.ring)
1010 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1011
1012 if (q_vector->rx.ring)
1013 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL;
1014
1015 adapter->q_vector[v_idx] = NULL;
1016 netif_napi_del(&q_vector->napi);
1017
7f90128e 1018 /* igb_get_stats64() might access the rings on this vector,
5536d210
AD		 1019 * we must wait a grace period before freeing it.
1020 */
1021 kfree_rcu(q_vector, rcu);
1022}
1023
047e0030 1024/**
b980ac18
JK		 1025 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1026 * @adapter: board private structure to initialize
047e0030 1027 *
b980ac18
JK		 1028 * This function frees the memory allocated to the q_vectors. In addition if
1029 * NAPI is enabled it will delete any references to the NAPI struct prior
1030 * to freeing the q_vector.
047e0030
AD		 1031 **/
1032static void igb_free_q_vectors(struct igb_adapter *adapter)
1033{
5536d210
AD		 1034 int v_idx = adapter->num_q_vectors;
1035
1036 adapter->num_tx_queues = 0;
1037 adapter->num_rx_queues = 0;
047e0030 1038 adapter->num_q_vectors = 0;
5536d210
AD		 1039
1040 while (v_idx--)
1041 igb_free_q_vector(adapter, v_idx);
047e0030
AD		 1042}
1043
1044/**
b980ac18
JK		 1045 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1046 * @adapter: board private structure to initialize
047e0030 1047 *
b980ac18
JK		 1048 * This function resets the device so that it has 0 Rx queues, Tx queues, and
1049 * MSI-X interrupts allocated.
047e0030
AD		 1050 */
1051static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1052{
047e0030
AD		 1053 igb_free_q_vectors(adapter);
1054 igb_reset_interrupt_capability(adapter);
1055}
9d5c8243
AK		 1056
1057/**
b980ac18
JK		 1058 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1059 * @adapter: board private structure to initialize
1060 * @msix: boolean value of MSIX capability
9d5c8243 1061 *
b980ac18
JK		 1062 * Attempt to configure interrupts using the best available
1063 * capabilities of the hardware and kernel.
9d5c8243 1064 **/
53c7d064 1065static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
9d5c8243
AK		 1066{
1067 int err;
1068 int numvecs, i;
1069
53c7d064
SA		 1070 if (!msix)
1071 goto msi_only;
1072
83b7180d 1073 /* Number of supported queues. */
a99955fc 1074 adapter->num_rx_queues = adapter->rss_queues;
5fa8517f
GR		 1075 if (adapter->vfs_allocated_count)
1076 adapter->num_tx_queues = 1;
1077 else
1078 adapter->num_tx_queues = adapter->rss_queues;
83b7180d 1079
b980ac18 1080 /* start with one vector for every Rx queue */
047e0030
AD		 1081 numvecs = adapter->num_rx_queues;
1082
b980ac18 1083 /* if Tx handler is separate add 1 for every Tx queue */
a99955fc
AD		 1084 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1085 numvecs += adapter->num_tx_queues;
047e0030
AD		 1086
1087 /* store the number of vectors reserved for queues */
1088 adapter->num_q_vectors = numvecs;
1089
1090 /* add 1 vector for link status interrupts */
1091 numvecs++;
9d5c8243
AK		 1092 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
1093 GFP_KERNEL);
f96a8a0b 1094
9d5c8243
AK		 1095 if (!adapter->msix_entries)
1096 goto msi_only;
1097
1098 for (i = 0; i < numvecs; i++)
1099 adapter->msix_entries[i].entry = i;
1100
1101 err = pci_enable_msix(adapter->pdev,
1102 adapter->msix_entries,
1103 numvecs);
1104 if (err == 0)
0c2cc02e 1105 return;
9d5c8243
AK		 1106
1107 igb_reset_interrupt_capability(adapter);
1108
1109 /* If we can't do MSI-X, try MSI */
1110msi_only:
2a3abf6d
AD		 1111#ifdef CONFIG_PCI_IOV
1112 /* disable SR-IOV for non MSI-X configurations */
1113 if (adapter->vf_data) {
1114 struct e1000_hw *hw = &adapter->hw;
1115 /* disable iov and allow time for transactions to clear */
1116 pci_disable_sriov(adapter->pdev);
1117 msleep(500);
1118
1119 kfree(adapter->vf_data);
1120 adapter->vf_data = NULL;
1121 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 1122 wrfl();
2a3abf6d
AD		 1123 msleep(100);
1124 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1125 }
1126#endif
4fc82adf 1127 adapter->vfs_allocated_count = 0;
a99955fc 1128 adapter->rss_queues = 1;
4fc82adf 1129 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 1130 adapter->num_rx_queues = 1;
661086df 1131 adapter->num_tx_queues = 1;
047e0030 1132 adapter->num_q_vectors = 1;
9d5c8243 1133 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1134 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1135}
1136
5536d210
AD		 1137static void igb_add_ring(struct igb_ring *ring,
1138 struct igb_ring_container *head)
1139{
1140 head->ring = ring;
1141 head->count++;
1142}
1143
047e0030 1144/**
b980ac18
JK		 1145 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1146 * @adapter: board private structure to initialize
1147 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1148 * @v_idx: index of vector in adapter struct
1149 * @txr_count: total number of Tx rings to allocate
1150 * @txr_idx: index of first Tx ring to allocate
1151 * @rxr_count: total number of Rx rings to allocate
1152 * @rxr_idx: index of first Rx ring to allocate
047e0030 1153 *
b980ac18 1154 * We allocate one q_vector. If allocation fails we return -ENOMEM.
047e0030 1155 **/
5536d210
AD		 1156static int igb_alloc_q_vector(struct igb_adapter *adapter,
1157 int v_count, int v_idx,
1158 int txr_count, int txr_idx,
1159 int rxr_count, int rxr_idx)
047e0030
AD		 1160{
1161 struct igb_q_vector *q_vector;
5536d210
AD		 1162 struct igb_ring *ring;
1163 int ring_count, size;
047e0030 1164
5536d210
AD		 1165 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1166 if (txr_count > 1 || rxr_count > 1)
1167 return -ENOMEM;
1168
1169 ring_count = txr_count + rxr_count;
1170 size = sizeof(struct igb_q_vector) +
1171 (sizeof(struct igb_ring) * ring_count);
1172
1173 /* allocate q_vector and rings */
1174 q_vector = kzalloc(size, GFP_KERNEL);
1175 if (!q_vector)
1176 return -ENOMEM;
1177
1178 /* initialize NAPI */
1179 netif_napi_add(adapter->netdev, &q_vector->napi,
1180 igb_poll, 64);
1181
1182 /* tie q_vector and adapter together */
1183 adapter->q_vector[v_idx] = q_vector;
1184 q_vector->adapter = adapter;
1185
1186 /* initialize work limits */
1187 q_vector->tx.work_limit = adapter->tx_work_limit;
1188
1189 /* initialize ITR configuration */
1190 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1191 q_vector->itr_val = IGB_START_ITR;
1192
1193 /* initialize pointer to rings */
1194 ring = q_vector->ring;
1195
4e227667
AD		 1196 /* intialize ITR */
1197 if (rxr_count) {
1198 /* rx or rx/tx vector */
1199 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1200 q_vector->itr_val = adapter->rx_itr_setting;
1201 } else {
1202 /* tx only vector */
1203 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1204 q_vector->itr_val = adapter->tx_itr_setting;
1205 }
1206
5536d210
AD		 1207 if (txr_count) {
1208 /* assign generic ring traits */
1209 ring->dev = &adapter->pdev->dev;
1210 ring->netdev = adapter->netdev;
1211
1212 /* configure backlink on ring */
1213 ring->q_vector = q_vector;
1214
1215 /* update q_vector Tx values */
1216 igb_add_ring(ring, &q_vector->tx);
1217
1218 /* For 82575, context index must be unique per ring. */
1219 if (adapter->hw.mac.type == e1000_82575)
1220 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1221
1222 /* apply Tx specific ring traits */
1223 ring->count = adapter->tx_ring_count;
1224 ring->queue_index = txr_idx;
1225
1226 /* assign ring to adapter */
1227 adapter->tx_ring[txr_idx] = ring;
1228
1229 /* push pointer to next ring */
1230 ring++;
047e0030 1231 }
81c2fc22 1232
5536d210
AD		 1233 if (rxr_count) {
1234 /* assign generic ring traits */
1235 ring->dev = &adapter->pdev->dev;
1236 ring->netdev = adapter->netdev;
047e0030 1237
5536d210
AD		 1238 /* configure backlink on ring */
1239 ring->q_vector = q_vector;
047e0030 1240
5536d210
AD		 1241 /* update q_vector Rx values */
1242 igb_add_ring(ring, &q_vector->rx);
047e0030 1243
5536d210
AD		 1244 /* set flag indicating ring supports SCTP checksum offload */
1245 if (adapter->hw.mac.type >= e1000_82576)
1246 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
047e0030 1247
ceb5f13b
CW		 1248 /*
1249 * On i350, i354, i210, and i211, loopback VLAN packets
5536d210 1250 * have the tag byte-swapped.
b980ac18 1251 */
5536d210
AD		 1252 if (adapter->hw.mac.type >= e1000_i350)
1253 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
047e0030 1254
5536d210
AD		 1255 /* apply Rx specific ring traits */
1256 ring->count = adapter->rx_ring_count;
1257 ring->queue_index = rxr_idx;
1258
1259 /* assign ring to adapter */
1260 adapter->rx_ring[rxr_idx] = ring;
1261 }
1262
1263 return 0;
047e0030
AD		 1264}
1265
5536d210 1266
047e0030 1267/**
b980ac18
JK		 1268 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1269 * @adapter: board private structure to initialize
047e0030 1270 *
b980ac18
JK		 1271 * We allocate one q_vector per queue interrupt. If allocation fails we
1272 * return -ENOMEM.
047e0030 1273 **/
5536d210 1274static int igb_alloc_q_vectors(struct igb_adapter *adapter)
047e0030 1275{
5536d210
AD		 1276 int q_vectors = adapter->num_q_vectors;
1277 int rxr_remaining = adapter->num_rx_queues;
1278 int txr_remaining = adapter->num_tx_queues;
1279 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1280 int err;
047e0030 1281
5536d210
AD		 1282 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1283 for (; rxr_remaining; v_idx++) {
1284 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1285 0, 0, 1, rxr_idx);
047e0030 1286
5536d210
AD		 1287 if (err)
1288 goto err_out;
1289
1290 /* update counts and index */
1291 rxr_remaining--;
1292 rxr_idx++;
047e0030 1293 }
047e0030 1294 }
5536d210
AD		 1295
1296 for (; v_idx < q_vectors; v_idx++) {
1297 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1298 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1299 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1300 tqpv, txr_idx, rqpv, rxr_idx);
1301
1302 if (err)
1303 goto err_out;
1304
1305 /* update counts and index */
1306 rxr_remaining -= rqpv;
1307 txr_remaining -= tqpv;
1308 rxr_idx++;
1309 txr_idx++;
1310 }
1311
047e0030 1312 return 0;
5536d210
AD		 1313
1314err_out:
1315 adapter->num_tx_queues = 0;
1316 adapter->num_rx_queues = 0;
1317 adapter->num_q_vectors = 0;
1318
1319 while (v_idx--)
1320 igb_free_q_vector(adapter, v_idx);
1321
1322 return -ENOMEM;
047e0030
AD		 1323}
1324
1325/**
b980ac18
JK		 1326 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1327 * @adapter: board private structure to initialize
1328 * @msix: boolean value of MSIX capability
047e0030 1329 *
b980ac18 1330 * This function initializes the interrupts and allocates all of the queues.
047e0030 1331 **/
53c7d064 1332static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
047e0030
AD		 1333{
1334 struct pci_dev *pdev = adapter->pdev;
1335 int err;
1336
53c7d064 1337 igb_set_interrupt_capability(adapter, msix);
047e0030
AD		 1338
1339 err = igb_alloc_q_vectors(adapter);
1340 if (err) {
1341 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1342 goto err_alloc_q_vectors;
1343 }
1344
5536d210 1345 igb_cache_ring_register(adapter);
047e0030
AD		 1346
1347 return 0;
5536d210 1348
047e0030
AD		 1349err_alloc_q_vectors:
1350 igb_reset_interrupt_capability(adapter);
1351 return err;
1352}
1353
9d5c8243 1354/**
b980ac18
JK		 1355 * igb_request_irq - initialize interrupts
1356 * @adapter: board private structure to initialize
9d5c8243 1357 *
b980ac18
JK		 1358 * Attempts to configure interrupts using the best available
1359 * capabilities of the hardware and kernel.
9d5c8243
AK		 1360 **/
1361static int igb_request_irq(struct igb_adapter *adapter)
1362{
1363 struct net_device *netdev = adapter->netdev;
047e0030 1364 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 1365 int err = 0;
1366
1367 if (adapter->msix_entries) {
1368 err = igb_request_msix(adapter);
844290e5 1369 if (!err)
9d5c8243 1370 goto request_done;
9d5c8243 1371 /* fall back to MSI */
5536d210
AD		 1372 igb_free_all_tx_resources(adapter);
1373 igb_free_all_rx_resources(adapter);
53c7d064 1374
047e0030 1375 igb_clear_interrupt_scheme(adapter);
53c7d064
SA		 1376 err = igb_init_interrupt_scheme(adapter, false);
1377 if (err)
047e0030 1378 goto request_done;
53c7d064 1379
047e0030
AD		 1380 igb_setup_all_tx_resources(adapter);
1381 igb_setup_all_rx_resources(adapter);
53c7d064 1382 igb_configure(adapter);
9d5c8243 1383 }
844290e5 1384
c74d588e
AD		 1385 igb_assign_vector(adapter->q_vector[0], 0);
1386
7dfc16fa 1387 if (adapter->flags & IGB_FLAG_HAS_MSI) {
c74d588e 1388 err = request_irq(pdev->irq, igb_intr_msi, 0,
047e0030 1389 netdev->name, adapter);
9d5c8243
AK		 1390 if (!err)
1391 goto request_done;
047e0030 1392
9d5c8243
AK		 1393 /* fall back to legacy interrupts */
1394 igb_reset_interrupt_capability(adapter);
7dfc16fa 1395 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1396 }
1397
c74d588e 1398 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
047e0030 1399 netdev->name, adapter);
9d5c8243 1400
6cb5e577 1401 if (err)
c74d588e 1402 dev_err(&pdev->dev, "Error %d getting interrupt\n",
9d5c8243 1403 err);
9d5c8243
AK		 1404
1405request_done:
1406 return err;
1407}
1408
1409static void igb_free_irq(struct igb_adapter *adapter)
1410{
9d5c8243
AK		 1411 if (adapter->msix_entries) {
1412 int vector = 0, i;
1413
047e0030 1414 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 1415
0d1ae7f4 1416 for (i = 0; i < adapter->num_q_vectors; i++)
047e0030 1417 free_irq(adapter->msix_entries[vector++].vector,
0d1ae7f4 1418 adapter->q_vector[i]);
047e0030
AD		 1419 } else {
1420 free_irq(adapter->pdev->irq, adapter);
9d5c8243 1421 }
9d5c8243
AK		 1422}
1423
1424/**
b980ac18
JK		 1425 * igb_irq_disable - Mask off interrupt generation on the NIC
1426 * @adapter: board private structure
9d5c8243
AK		 1427 **/
1428static void igb_irq_disable(struct igb_adapter *adapter)
1429{
1430 struct e1000_hw *hw = &adapter->hw;
1431
b980ac18 1432 /* we need to be careful when disabling interrupts. The VFs are also
25568a53
AD		 1433 * mapped into these registers and so clearing the bits can cause
1434 * issues on the VF drivers so we only need to clear what we set
1435 */
9d5c8243 1436 if (adapter->msix_entries) {
2dfd1212
AD		 1437 u32 regval = rd32(E1000_EIAM);
1438 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1439 wr32(E1000_EIMC, adapter->eims_enable_mask);
1440 regval = rd32(E1000_EIAC);
1441 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 1442 }
844290e5
PW		 1443
1444 wr32(E1000_IAM, 0);
9d5c8243
AK		 1445 wr32(E1000_IMC, ~0);
1446 wrfl();
81a61859
ET		 1447 if (adapter->msix_entries) {
1448 int i;
1449 for (i = 0; i < adapter->num_q_vectors; i++)
1450 synchronize_irq(adapter->msix_entries[i].vector);
1451 } else {
1452 synchronize_irq(adapter->pdev->irq);
1453 }
9d5c8243
AK		 1454}
1455
1456/**
b980ac18
JK		 1457 * igb_irq_enable - Enable default interrupt generation settings
1458 * @adapter: board private structure
9d5c8243
AK		 1459 **/
1460static void igb_irq_enable(struct igb_adapter *adapter)
1461{
1462 struct e1000_hw *hw = &adapter->hw;
1463
1464 if (adapter->msix_entries) {
06218a8d 1465 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
2dfd1212
AD		 1466 u32 regval = rd32(E1000_EIAC);
1467 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1468 regval = rd32(E1000_EIAM);
1469 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1470 wr32(E1000_EIMS, adapter->eims_enable_mask);
25568a53 1471 if (adapter->vfs_allocated_count) {
4ae196df 1472 wr32(E1000_MBVFIMR, 0xFF);
25568a53
AD		 1473 ims |= E1000_IMS_VMMB;
1474 }
1475 wr32(E1000_IMS, ims);
844290e5 1476 } else {
55cac248
AD		 1477 wr32(E1000_IMS, IMS_ENABLE_MASK |
1478 E1000_IMS_DRSTA);
1479 wr32(E1000_IAM, IMS_ENABLE_MASK |
1480 E1000_IMS_DRSTA);
844290e5 1481 }
9d5c8243
AK		 1482}
1483
1484static void igb_update_mng_vlan(struct igb_adapter *adapter)
1485{
51466239 1486 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1487 u16 vid = adapter->hw.mng_cookie.vlan_id;
1488 u16 old_vid = adapter->mng_vlan_id;
51466239
AD		 1489
1490 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1491 /* add VID to filter table */
1492 igb_vfta_set(hw, vid, true);
1493 adapter->mng_vlan_id = vid;
1494 } else {
1495 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1496 }
1497
1498 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1499 (vid != old_vid) &&
b2cb09b1 1500 !test_bit(old_vid, adapter->active_vlans)) {
51466239
AD		 1501 /* remove VID from filter table */
1502 igb_vfta_set(hw, old_vid, false);
9d5c8243
AK		 1503 }
1504}
1505
1506/**
b980ac18
JK		 1507 * igb_release_hw_control - release control of the h/w to f/w
1508 * @adapter: address of board private structure
9d5c8243 1509 *
b980ac18
JK		 1510 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1511 * For ASF and Pass Through versions of f/w this means that the
1512 * driver is no longer loaded.
9d5c8243
AK		 1513 **/
1514static void igb_release_hw_control(struct igb_adapter *adapter)
1515{
1516 struct e1000_hw *hw = &adapter->hw;
1517 u32 ctrl_ext;
1518
1519 /* Let firmware take over control of h/w */
1520 ctrl_ext = rd32(E1000_CTRL_EXT);
1521 wr32(E1000_CTRL_EXT,
1522 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1523}
1524
9d5c8243 1525/**
b980ac18
JK		 1526 * igb_get_hw_control - get control of the h/w from f/w
1527 * @adapter: address of board private structure
9d5c8243 1528 *
b980ac18
JK		 1529 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1530 * For ASF and Pass Through versions of f/w this means that
1531 * the driver is loaded.
9d5c8243
AK		 1532 **/
1533static void igb_get_hw_control(struct igb_adapter *adapter)
1534{
1535 struct e1000_hw *hw = &adapter->hw;
1536 u32 ctrl_ext;
1537
1538 /* Let firmware know the driver has taken over */
1539 ctrl_ext = rd32(E1000_CTRL_EXT);
1540 wr32(E1000_CTRL_EXT,
1541 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1542}
1543
9d5c8243 1544/**
b980ac18
JK		 1545 * igb_configure - configure the hardware for RX and TX
1546 * @adapter: private board structure
9d5c8243
AK		 1547 **/
1548static void igb_configure(struct igb_adapter *adapter)
1549{
1550 struct net_device *netdev = adapter->netdev;
1551 int i;
1552
1553 igb_get_hw_control(adapter);
ff41f8dc 1554 igb_set_rx_mode(netdev);
9d5c8243
AK		 1555
1556 igb_restore_vlan(adapter);
9d5c8243 1557
85b430b4 1558 igb_setup_tctl(adapter);
06cf2666 1559 igb_setup_mrqc(adapter);
9d5c8243 1560 igb_setup_rctl(adapter);
85b430b4
AD		 1561
1562 igb_configure_tx(adapter);
9d5c8243 1563 igb_configure_rx(adapter);
662d7205
AD		 1564
1565 igb_rx_fifo_flush_82575(&adapter->hw);
1566
c493ea45 1567 /* call igb_desc_unused which always leaves
9d5c8243 1568 * at least 1 descriptor unused to make sure
b980ac18
JK		 1569 * next_to_use != next_to_clean
1570 */
9d5c8243 1571 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 1572 struct igb_ring *ring = adapter->rx_ring[i];
cd392f5c 1573 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
9d5c8243 1574 }
9d5c8243
AK		 1575}
1576
88a268c1 1577/**
b980ac18
JK		 1578 * igb_power_up_link - Power up the phy/serdes link
1579 * @adapter: address of board private structure
88a268c1
NN		 1580 **/
1581void igb_power_up_link(struct igb_adapter *adapter)
1582{
76886596
AA		 1583 igb_reset_phy(&adapter->hw);
1584
88a268c1
NN		 1585 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1586 igb_power_up_phy_copper(&adapter->hw);
1587 else
1588 igb_power_up_serdes_link_82575(&adapter->hw);
1589}
1590
1591/**
b980ac18
JK		 1592 * igb_power_down_link - Power down the phy/serdes link
1593 * @adapter: address of board private structure
88a268c1
NN		 1594 */
1595static void igb_power_down_link(struct igb_adapter *adapter)
1596{
1597 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1598 igb_power_down_phy_copper_82575(&adapter->hw);
1599 else
1600 igb_shutdown_serdes_link_82575(&adapter->hw);
1601}
9d5c8243
AK		 1602
1603/**
b980ac18
JK		 1604 * igb_up - Open the interface and prepare it to handle traffic
1605 * @adapter: board private structure
9d5c8243 1606 **/
9d5c8243
AK		 1607int igb_up(struct igb_adapter *adapter)
1608{
1609 struct e1000_hw *hw = &adapter->hw;
1610 int i;
1611
1612 /* hardware has been reset, we need to reload some things */
1613 igb_configure(adapter);
1614
1615 clear_bit(__IGB_DOWN, &adapter->state);
1616
0d1ae7f4
AD		 1617 for (i = 0; i < adapter->num_q_vectors; i++)
1618 napi_enable(&(adapter->q_vector[i]->napi));
1619
844290e5 1620 if (adapter->msix_entries)
9d5c8243 1621 igb_configure_msix(adapter);
feeb2721
AD		 1622 else
1623 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243
AK		 1624
1625 /* Clear any pending interrupts. */
1626 rd32(E1000_ICR);
1627 igb_irq_enable(adapter);
1628
d4960307
AD		 1629 /* notify VFs that reset has been completed */
1630 if (adapter->vfs_allocated_count) {
1631 u32 reg_data = rd32(E1000_CTRL_EXT);
1632 reg_data |= E1000_CTRL_EXT_PFRSTD;
1633 wr32(E1000_CTRL_EXT, reg_data);
1634 }
1635
4cb9be7a
JB		 1636 netif_tx_start_all_queues(adapter->netdev);
1637
25568a53
AD		 1638 /* start the watchdog. */
1639 hw->mac.get_link_status = 1;
1640 schedule_work(&adapter->watchdog_task);
1641
9d5c8243
AK		 1642 return 0;
1643}
1644
1645void igb_down(struct igb_adapter *adapter)
1646{
9d5c8243 1647 struct net_device *netdev = adapter->netdev;
330a6d6a 1648 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1649 u32 tctl, rctl;
1650 int i;
1651
1652 /* signal that we're down so the interrupt handler does not
b980ac18
JK		 1653 * reschedule our watchdog timer
1654 */
9d5c8243
AK		 1655 set_bit(__IGB_DOWN, &adapter->state);
1656
1657 /* disable receives in the hardware */
1658 rctl = rd32(E1000_RCTL);
1659 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1660 /* flush and sleep below */
1661
fd2ea0a7 1662 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1663
1664 /* disable transmits in the hardware */
1665 tctl = rd32(E1000_TCTL);
1666 tctl &= ~E1000_TCTL_EN;
1667 wr32(E1000_TCTL, tctl);
1668 /* flush both disables and wait for them to finish */
1669 wrfl();
1670 msleep(10);
1671
41f149a2
CW		 1672 igb_irq_disable(adapter);
1673
1674 for (i = 0; i < adapter->num_q_vectors; i++) {
1675 napi_synchronize(&(adapter->q_vector[i]->napi));
0d1ae7f4 1676 napi_disable(&(adapter->q_vector[i]->napi));
41f149a2 1677 }
9d5c8243 1678
9d5c8243
AK		 1679
1680 del_timer_sync(&adapter->watchdog_timer);
1681 del_timer_sync(&adapter->phy_info_timer);
1682
9d5c8243 1683 netif_carrier_off(netdev);
04fe6358
AD		 1684
1685 /* record the stats before reset*/
12dcd86b
ED		 1686 spin_lock(&adapter->stats64_lock);
1687 igb_update_stats(adapter, &adapter->stats64);
1688 spin_unlock(&adapter->stats64_lock);
04fe6358 1689
9d5c8243
AK		 1690 adapter->link_speed = 0;
1691 adapter->link_duplex = 0;
1692
3023682e
JK		 1693 if (!pci_channel_offline(adapter->pdev))
1694 igb_reset(adapter);
9d5c8243
AK		 1695 igb_clean_all_tx_rings(adapter);
1696 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1697#ifdef CONFIG_IGB_DCA
1698
1699 /* since we reset the hardware DCA settings were cleared */
1700 igb_setup_dca(adapter);
1701#endif
9d5c8243
AK		 1702}
1703
1704void igb_reinit_locked(struct igb_adapter *adapter)
1705{
1706 WARN_ON(in_interrupt());
1707 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1708 msleep(1);
1709 igb_down(adapter);
1710 igb_up(adapter);
1711 clear_bit(__IGB_RESETTING, &adapter->state);
1712}
1713
1714void igb_reset(struct igb_adapter *adapter)
1715{
090b1795 1716 struct pci_dev *pdev = adapter->pdev;
9d5c8243 1717 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1718 struct e1000_mac_info *mac = &hw->mac;
1719 struct e1000_fc_info *fc = &hw->fc;
d48507fe 1720 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;
9d5c8243
AK		 1721
1722 /* Repartition Pba for greater than 9k mtu
1723 * To take effect CTRL.RST is required.
1724 */
fa4dfae0 1725 switch (mac->type) {
d2ba2ed8 1726 case e1000_i350:
ceb5f13b 1727 case e1000_i354:
55cac248
AD		 1728 case e1000_82580:
1729 pba = rd32(E1000_RXPBS);
1730 pba = igb_rxpbs_adjust_82580(pba);
1731 break;
fa4dfae0 1732 case e1000_82576:
d249be54
AD		 1733 pba = rd32(E1000_RXPBS);
1734 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1735 break;
1736 case e1000_82575:
f96a8a0b
CW		 1737 case e1000_i210:
1738 case e1000_i211:
fa4dfae0
AD		 1739 default:
1740 pba = E1000_PBA_34K;
1741 break;
2d064c06 1742 }
9d5c8243 1743
2d064c06
AD		 1744 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1745 (mac->type < e1000_82576)) {
9d5c8243
AK		 1746 /* adjust PBA for jumbo frames */
1747 wr32(E1000_PBA, pba);
1748
1749 /* To maintain wire speed transmits, the Tx FIFO should be
1750 * large enough to accommodate two full transmit packets,
1751 * rounded up to the next 1KB and expressed in KB. Likewise,
1752 * the Rx FIFO should be large enough to accommodate at least
1753 * one full receive packet and is similarly rounded up and
b980ac18
JK		 1754 * expressed in KB.
1755 */
9d5c8243
AK		 1756 pba = rd32(E1000_PBA);
1757 /* upper 16 bits has Tx packet buffer allocation size in KB */
1758 tx_space = pba >> 16;
1759 /* lower 16 bits has Rx packet buffer allocation size in KB */
1760 pba &= 0xffff;
b980ac18
JK		 1761 /* the Tx fifo also stores 16 bytes of information about the Tx
1762 * but don't include ethernet FCS because hardware appends it
1763 */
9d5c8243 1764 min_tx_space = (adapter->max_frame_size +
85e8d004 1765 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1766 ETH_FCS_LEN) * 2;
1767 min_tx_space = ALIGN(min_tx_space, 1024);
1768 min_tx_space >>= 10;
1769 /* software strips receive CRC, so leave room for it */
1770 min_rx_space = adapter->max_frame_size;
1771 min_rx_space = ALIGN(min_rx_space, 1024);
1772 min_rx_space >>= 10;
1773
1774 /* If current Tx allocation is less than the min Tx FIFO size,
1775 * and the min Tx FIFO size is less than the current Rx FIFO
b980ac18
JK		 1776 * allocation, take space away from current Rx allocation
1777 */
9d5c8243
AK		 1778 if (tx_space < min_tx_space &&
1779 ((min_tx_space - tx_space) < pba)) {
1780 pba = pba - (min_tx_space - tx_space);
1781
b980ac18
JK		 1782 /* if short on Rx space, Rx wins and must trump Tx
1783 * adjustment
1784 */
9d5c8243
AK		 1785 if (pba < min_rx_space)
1786 pba = min_rx_space;
1787 }
2d064c06 1788 wr32(E1000_PBA, pba);
9d5c8243 1789 }
9d5c8243
AK		 1790
1791 /* flow control settings */
1792 /* The high water mark must be low enough to fit one full frame
1793 * (or the size used for early receive) above it in the Rx FIFO.
1794 * Set it to the lower of:
1795 * - 90% of the Rx FIFO size, or
b980ac18
JK		 1796 * - the full Rx FIFO size minus one full frame
1797 */
9d5c8243 1798 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1799 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1800
d48507fe 1801 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
d405ea3e 1802 fc->low_water = fc->high_water - 16;
9d5c8243
AK		 1803 fc->pause_time = 0xFFFF;
1804 fc->send_xon = 1;
0cce119a 1805 fc->current_mode = fc->requested_mode;
9d5c8243 1806
4ae196df
AD		 1807 /* disable receive for all VFs and wait one second */
1808 if (adapter->vfs_allocated_count) {
1809 int i;
1810 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
8fa7e0f7 1811 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
4ae196df
AD		 1812
1813 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1814 igb_ping_all_vfs(adapter);
4ae196df
AD		 1815
1816 /* disable transmits and receives */
1817 wr32(E1000_VFRE, 0);
1818 wr32(E1000_VFTE, 0);
1819 }
1820
9d5c8243 1821 /* Allow time for pending master requests to run */
330a6d6a 1822 hw->mac.ops.reset_hw(hw);
9d5c8243
AK		 1823 wr32(E1000_WUC, 0);
1824
330a6d6a 1825 if (hw->mac.ops.init_hw(hw))
090b1795 1826 dev_err(&pdev->dev, "Hardware Error\n");
831ec0b4 1827
b980ac18 1828 /* Flow control settings reset on hardware reset, so guarantee flow
a27416bb
MV		 1829 * control is off when forcing speed.
1830 */
1831 if (!hw->mac.autoneg)
1832 igb_force_mac_fc(hw);
1833
b6e0c419 1834 igb_init_dmac(adapter, pba);
e428893b
CW		 1835#ifdef CONFIG_IGB_HWMON
1836 /* Re-initialize the thermal sensor on i350 devices. */
1837 if (!test_bit(__IGB_DOWN, &adapter->state)) {
1838 if (mac->type == e1000_i350 && hw->bus.func == 0) {
1839 /* If present, re-initialize the external thermal sensor
1840 * interface.
1841 */
1842 if (adapter->ets)
1843 mac->ops.init_thermal_sensor_thresh(hw);
1844 }
1845 }
1846#endif
88a268c1
NN		 1847 if (!netif_running(adapter->netdev))
1848 igb_power_down_link(adapter);
1849
9d5c8243
AK		 1850 igb_update_mng_vlan(adapter);
1851
1852 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1853 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1854
1f6e8178
MV		 1855 /* Re-enable PTP, where applicable. */
1856 igb_ptp_reset(adapter);
1f6e8178 1857
330a6d6a 1858 igb_get_phy_info(hw);
9d5c8243
AK		 1859}
1860
c8f44aff
MM		 1861static netdev_features_t igb_fix_features(struct net_device *netdev,
1862 netdev_features_t features)
b2cb09b1 1863{
b980ac18
JK		 1864 /* Since there is no support for separate Rx/Tx vlan accel
1865 * enable/disable make sure Tx flag is always in same state as Rx.
b2cb09b1 1866 */
f646968f
PM		 1867 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1868 features |= NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1 1869 else
f646968f 1870 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1
JP		 1871
1872 return features;
1873}
1874
c8f44aff
MM		 1875static int igb_set_features(struct net_device *netdev,
1876 netdev_features_t features)
ac52caa3 1877{
c8f44aff 1878 netdev_features_t changed = netdev->features ^ features;
89eaefb6 1879 struct igb_adapter *adapter = netdev_priv(netdev);
ac52caa3 1880
f646968f 1881 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
b2cb09b1
JP		 1882 igb_vlan_mode(netdev, features);
1883
89eaefb6
BG		 1884 if (!(changed & NETIF_F_RXALL))
1885 return 0;
1886
1887 netdev->features = features;
1888
1889 if (netif_running(netdev))
1890 igb_reinit_locked(adapter);
1891 else
1892 igb_reset(adapter);
1893
ac52caa3
MM		 1894 return 0;
1895}
1896
2e5c6922 1897static const struct net_device_ops igb_netdev_ops = {
559e9c49 1898 .ndo_open = igb_open,
2e5c6922 1899 .ndo_stop = igb_close,
cd392f5c 1900 .ndo_start_xmit = igb_xmit_frame,
12dcd86b 1901 .ndo_get_stats64 = igb_get_stats64,
ff41f8dc 1902 .ndo_set_rx_mode = igb_set_rx_mode,
2e5c6922
SH		 1903 .ndo_set_mac_address = igb_set_mac,
1904 .ndo_change_mtu = igb_change_mtu,
1905 .ndo_do_ioctl = igb_ioctl,
1906 .ndo_tx_timeout = igb_tx_timeout,
1907 .ndo_validate_addr = eth_validate_addr,
2e5c6922
SH		 1908 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1909 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
8151d294
WM		 1910 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
1911 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
1912 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw,
70ea4783 1913 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk,
8151d294 1914 .ndo_get_vf_config = igb_ndo_get_vf_config,
2e5c6922
SH		 1915#ifdef CONFIG_NET_POLL_CONTROLLER
1916 .ndo_poll_controller = igb_netpoll,
1917#endif
b2cb09b1
JP		 1918 .ndo_fix_features = igb_fix_features,
1919 .ndo_set_features = igb_set_features,
2e5c6922
SH		 1920};
1921
d67974f0
CW		 1922/**
1923 * igb_set_fw_version - Configure version string for ethtool
1924 * @adapter: adapter struct
d67974f0
CW		 1925 **/
1926void igb_set_fw_version(struct igb_adapter *adapter)
1927{
1928 struct e1000_hw *hw = &adapter->hw;
0b1a6f2e
CW		 1929 struct e1000_fw_version fw;
1930
1931 igb_get_fw_version(hw, &fw);
1932
1933 switch (hw->mac.type) {
1934 case e1000_i211:
d67974f0 1935 snprintf(adapter->fw_version, sizeof(adapter->fw_version),
0b1a6f2e
CW		 1936 "%2d.%2d-%d",
1937 fw.invm_major, fw.invm_minor, fw.invm_img_type);
1938 break;
1939
1940 default:
1941 /* if option is rom valid, display its version too */
1942 if (fw.or_valid) {
1943 snprintf(adapter->fw_version,
1944 sizeof(adapter->fw_version),
1945 "%d.%d, 0x%08x, %d.%d.%d",
1946 fw.eep_major, fw.eep_minor, fw.etrack_id,
1947 fw.or_major, fw.or_build, fw.or_patch);
1948 /* no option rom */
1949 } else {
1950 snprintf(adapter->fw_version,
1951 sizeof(adapter->fw_version),
1952 "%d.%d, 0x%08x",
1953 fw.eep_major, fw.eep_minor, fw.etrack_id);
1954 }
1955 break;
d67974f0 1956 }
d67974f0
CW		 1957 return;
1958}
1959
b980ac18
JK		 1960/**
1961 * igb_init_i2c - Init I2C interface
441fc6fd 1962 * @adapter: pointer to adapter structure
b980ac18 1963 **/
441fc6fd
CW		 1964static s32 igb_init_i2c(struct igb_adapter *adapter)
1965{
1966 s32 status = E1000_SUCCESS;
1967
1968 /* I2C interface supported on i350 devices */
1969 if (adapter->hw.mac.type != e1000_i350)
1970 return E1000_SUCCESS;
1971
1972 /* Initialize the i2c bus which is controlled by the registers.
1973 * This bus will use the i2c_algo_bit structue that implements
1974 * the protocol through toggling of the 4 bits in the register.
1975 */
1976 adapter->i2c_adap.owner = THIS_MODULE;
1977 adapter->i2c_algo = igb_i2c_algo;
1978 adapter->i2c_algo.data = adapter;
1979 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
1980 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
1981 strlcpy(adapter->i2c_adap.name, "igb BB",
1982 sizeof(adapter->i2c_adap.name));
1983 status = i2c_bit_add_bus(&adapter->i2c_adap);
1984 return status;
1985}
1986
9d5c8243 1987/**
b980ac18
JK		 1988 * igb_probe - Device Initialization Routine
1989 * @pdev: PCI device information struct
1990 * @ent: entry in igb_pci_tbl
9d5c8243 1991 *
b980ac18 1992 * Returns 0 on success, negative on failure
9d5c8243 1993 *
b980ac18
JK		 1994 * igb_probe initializes an adapter identified by a pci_dev structure.
1995 * The OS initialization, configuring of the adapter private structure,
1996 * and a hardware reset occur.
9d5c8243 1997 **/
1dd06ae8 1998static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9d5c8243
AK		 1999{
2000 struct net_device *netdev;
2001 struct igb_adapter *adapter;
2002 struct e1000_hw *hw;
4337e993 2003 u16 eeprom_data = 0;
9835fd73 2004 s32 ret_val;
4337e993 2005 static int global_quad_port_a; /* global quad port a indication */
9d5c8243
AK		 2006 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
2007 unsigned long mmio_start, mmio_len;
2d6a5e95 2008 int err, pci_using_dac;
9835fd73 2009 u8 part_str[E1000_PBANUM_LENGTH];
9d5c8243 2010
bded64a7
AG		 2011 /* Catch broken hardware that put the wrong VF device ID in
2012 * the PCIe SR-IOV capability.
2013 */
2014 if (pdev->is_virtfn) {
2015 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
f96a8a0b 2016 pci_name(pdev), pdev->vendor, pdev->device);
bded64a7
AG		 2017 return -EINVAL;
2018 }
2019
aed5dec3 2020 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 2021 if (err)
2022 return err;
2023
2024 pci_using_dac = 0;
59d71989 2025 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243 2026 if (!err) {
59d71989 2027 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243
AK		 2028 if (!err)
2029 pci_using_dac = 1;
2030 } else {
59d71989 2031 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243 2032 if (err) {
b980ac18
JK		 2033 err = dma_set_coherent_mask(&pdev->dev,
2034 DMA_BIT_MASK(32));
9d5c8243 2035 if (err) {
b980ac18
JK		 2036 dev_err(&pdev->dev,
2037 "No usable DMA configuration, aborting\n");
9d5c8243
AK		 2038 goto err_dma;
2039 }
2040 }
2041 }
2042
aed5dec3 2043 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
b980ac18
JK		 2044 IORESOURCE_MEM),
2045 igb_driver_name);
9d5c8243
AK		 2046 if (err)
2047 goto err_pci_reg;
2048
19d5afd4 2049 pci_enable_pcie_error_reporting(pdev);
40a914fa 2050
9d5c8243 2051 pci_set_master(pdev);
c682fc23 2052 pci_save_state(pdev);
9d5c8243
AK		 2053
2054 err = -ENOMEM;
1bfaf07b 2055 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1cc3bd87 2056 IGB_MAX_TX_QUEUES);
9d5c8243
AK		 2057 if (!netdev)
2058 goto err_alloc_etherdev;
2059
2060 SET_NETDEV_DEV(netdev, &pdev->dev);
2061
2062 pci_set_drvdata(pdev, netdev);
2063 adapter = netdev_priv(netdev);
2064 adapter->netdev = netdev;
2065 adapter->pdev = pdev;
2066 hw = &adapter->hw;
2067 hw->back = adapter;
b3f4d599 2068 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9d5c8243
AK		 2069
2070 mmio_start = pci_resource_start(pdev, 0);
2071 mmio_len = pci_resource_len(pdev, 0);
2072
2073 err = -EIO;
28b0759c
AD		 2074 hw->hw_addr = ioremap(mmio_start, mmio_len);
2075 if (!hw->hw_addr)
9d5c8243
AK		 2076 goto err_ioremap;
2077
2e5c6922 2078 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 2079 igb_set_ethtool_ops(netdev);
9d5c8243 2080 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 2081
2082 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2083
2084 netdev->mem_start = mmio_start;
2085 netdev->mem_end = mmio_start + mmio_len;
2086
9d5c8243
AK		 2087 /* PCI config space info */
2088 hw->vendor_id = pdev->vendor;
2089 hw->device_id = pdev->device;
2090 hw->revision_id = pdev->revision;
2091 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2092 hw->subsystem_device_id = pdev->subsystem_device;
2093
9d5c8243
AK		 2094 /* Copy the default MAC, PHY and NVM function pointers */
2095 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2096 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2097 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2098 /* Initialize skew-specific constants */
2099 err = ei->get_invariants(hw);
2100 if (err)
450c87c8 2101 goto err_sw_init;
9d5c8243 2102
450c87c8 2103 /* setup the private structure */
9d5c8243
AK		 2104 err = igb_sw_init(adapter);
2105 if (err)
2106 goto err_sw_init;
2107
2108 igb_get_bus_info_pcie(hw);
2109
2110 hw->phy.autoneg_wait_to_complete = false;
9d5c8243
AK		 2111
2112 /* Copper options */
2113 if (hw->phy.media_type == e1000_media_type_copper) {
2114 hw->phy.mdix = AUTO_ALL_MODES;
2115 hw->phy.disable_polarity_correction = false;
2116 hw->phy.ms_type = e1000_ms_hw_default;
2117 }
2118
2119 if (igb_check_reset_block(hw))
2120 dev_info(&pdev->dev,
2121 "PHY reset is blocked due to SOL/IDER session.\n");
2122
b980ac18 2123 /* features is initialized to 0 in allocation, it might have bits
077887c3
AD		 2124 * set by igb_sw_init so we should use an or instead of an
2125 * assignment.
2126 */
2127 netdev->features |= NETIF_F_SG |
2128 NETIF_F_IP_CSUM |
2129 NETIF_F_IPV6_CSUM |
2130 NETIF_F_TSO |
2131 NETIF_F_TSO6 |
2132 NETIF_F_RXHASH |
2133 NETIF_F_RXCSUM |
f646968f
PM		 2134 NETIF_F_HW_VLAN_CTAG_RX |
2135 NETIF_F_HW_VLAN_CTAG_TX;
077887c3
AD		 2136
2137 /* copy netdev features into list of user selectable features */
2138 netdev->hw_features |= netdev->features;
89eaefb6 2139 netdev->hw_features |= NETIF_F_RXALL;
077887c3
AD		 2140
2141 /* set this bit last since it cannot be part of hw_features */
f646968f 2142 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
077887c3
AD		 2143
2144 netdev->vlan_features |= NETIF_F_TSO |
2145 NETIF_F_TSO6 |
2146 NETIF_F_IP_CSUM |
2147 NETIF_F_IPV6_CSUM |
2148 NETIF_F_SG;
48f29ffc 2149
6b8f0922
BG		 2150 netdev->priv_flags |= IFF_SUPP_NOFCS;
2151
7b872a55 2152 if (pci_using_dac) {
9d5c8243 2153 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 2154 netdev->vlan_features |= NETIF_F_HIGHDMA;
2155 }
9d5c8243 2156
ac52caa3
MM		 2157 if (hw->mac.type >= e1000_82576) {
2158 netdev->hw_features |= NETIF_F_SCTP_CSUM;
b9473560 2159 netdev->features |= NETIF_F_SCTP_CSUM;
ac52caa3 2160 }
b9473560 2161
01789349
JP		 2162 netdev->priv_flags |= IFF_UNICAST_FLT;
2163
330a6d6a 2164 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
9d5c8243
AK		 2165
2166 /* before reading the NVM, reset the controller to put the device in a
b980ac18
JK		 2167 * known good starting state
2168 */
9d5c8243
AK		 2169 hw->mac.ops.reset_hw(hw);
2170
ef3a0092
CW		 2171 /* make sure the NVM is good , i211/i210 parts can have special NVM
2172 * that doesn't contain a checksum
f96a8a0b 2173 */
ef3a0092
CW		 2174 switch (hw->mac.type) {
2175 case e1000_i210:
2176 case e1000_i211:
2177 if (igb_get_flash_presence_i210(hw)) {
2178 if (hw->nvm.ops.validate(hw) < 0) {
2179 dev_err(&pdev->dev,
2180 "The NVM Checksum Is Not Valid\n");
2181 err = -EIO;
2182 goto err_eeprom;
2183 }
2184 }
2185 break;
2186 default:
f96a8a0b
CW		 2187 if (hw->nvm.ops.validate(hw) < 0) {
2188 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2189 err = -EIO;
2190 goto err_eeprom;
2191 }
ef3a0092 2192 break;
9d5c8243
AK		 2193 }
2194
2195 /* copy the MAC address out of the NVM */
2196 if (hw->mac.ops.read_mac_addr(hw))
2197 dev_err(&pdev->dev, "NVM Read Error\n");
2198
2199 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
9d5c8243 2200
aaeb6cdf 2201 if (!is_valid_ether_addr(netdev->dev_addr)) {
9d5c8243
AK		 2202 dev_err(&pdev->dev, "Invalid MAC Address\n");
2203 err = -EIO;
2204 goto err_eeprom;
2205 }
2206
d67974f0
CW		 2207 /* get firmware version for ethtool -i */
2208 igb_set_fw_version(adapter);
2209
c061b18d 2210 setup_timer(&adapter->watchdog_timer, igb_watchdog,
b980ac18 2211 (unsigned long) adapter);
c061b18d 2212 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
b980ac18 2213 (unsigned long) adapter);
9d5c8243
AK		 2214
2215 INIT_WORK(&adapter->reset_task, igb_reset_task);
2216 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2217
450c87c8 2218 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 2219 adapter->fc_autoneg = true;
2220 hw->mac.autoneg = true;
2221 hw->phy.autoneg_advertised = 0x2f;
2222
0cce119a
AD		 2223 hw->fc.requested_mode = e1000_fc_default;
2224 hw->fc.current_mode = e1000_fc_default;
9d5c8243 2225
9d5c8243
AK		 2226 igb_validate_mdi_setting(hw);
2227
63d4a8f9 2228 /* By default, support wake on port A */
a2cf8b6c 2229 if (hw->bus.func == 0)
63d4a8f9
MV		 2230 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2231
2232 /* Check the NVM for wake support on non-port A ports */
2233 if (hw->mac.type >= e1000_82580)
55cac248 2234 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
b980ac18
JK		 2235 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2236 &eeprom_data);
a2cf8b6c
AD		 2237 else if (hw->bus.func == 1)
2238 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243 2239
63d4a8f9
MV		 2240 if (eeprom_data & IGB_EEPROM_APME)
2241 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2242
2243 /* now that we have the eeprom settings, apply the special cases where
2244 * the eeprom may be wrong or the board simply won't support wake on
b980ac18
JK		 2245 * lan on a particular port
2246 */
9d5c8243
AK		 2247 switch (pdev->device) {
2248 case E1000_DEV_ID_82575GB_QUAD_COPPER:
63d4a8f9 2249 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2250 break;
2251 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 2252 case E1000_DEV_ID_82576_FIBER:
2253 case E1000_DEV_ID_82576_SERDES:
9d5c8243 2254 /* Wake events only supported on port A for dual fiber
b980ac18
JK		 2255 * regardless of eeprom setting
2256 */
9d5c8243 2257 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
63d4a8f9 2258 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243 2259 break;
c8ea5ea9 2260 case E1000_DEV_ID_82576_QUAD_COPPER:
d5aa2252 2261 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
c8ea5ea9
AD		 2262 /* if quad port adapter, disable WoL on all but port A */
2263 if (global_quad_port_a != 0)
63d4a8f9 2264 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
c8ea5ea9
AD		 2265 else
2266 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2267 /* Reset for multiple quad port adapters */
2268 if (++global_quad_port_a == 4)
2269 global_quad_port_a = 0;
2270 break;
63d4a8f9
MV		 2271 default:
2272 /* If the device can't wake, don't set software support */
2273 if (!device_can_wakeup(&adapter->pdev->dev))
2274 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2275 }
2276
2277 /* initialize the wol settings based on the eeprom settings */
63d4a8f9
MV		 2278 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2279 adapter->wol |= E1000_WUFC_MAG;
2280
2281 /* Some vendors want WoL disabled by default, but still supported */
2282 if ((hw->mac.type == e1000_i350) &&
2283 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2284 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2285 adapter->wol = 0;
2286 }
2287
2288 device_set_wakeup_enable(&adapter->pdev->dev,
2289 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
9d5c8243
AK		 2290
2291 /* reset the hardware with the new settings */
2292 igb_reset(adapter);
2293
441fc6fd
CW		 2294 /* Init the I2C interface */
2295 err = igb_init_i2c(adapter);
2296 if (err) {
2297 dev_err(&pdev->dev, "failed to init i2c interface\n");
2298 goto err_eeprom;
2299 }
2300
9d5c8243
AK		 2301 /* let the f/w know that the h/w is now under the control of the
2302 * driver. */
2303 igb_get_hw_control(adapter);
2304
9d5c8243
AK		 2305 strcpy(netdev->name, "eth%d");
2306 err = register_netdev(netdev);
2307 if (err)
2308 goto err_register;
2309
b168dfc5
JB		 2310 /* carrier off reporting is important to ethtool even BEFORE open */
2311 netif_carrier_off(netdev);
2312
421e02f0 2313#ifdef CONFIG_IGB_DCA
bbd98fe4 2314 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 2315 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 2316 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 2317 igb_setup_dca(adapter);
2318 }
fe4506b6 2319
38c845c7 2320#endif
e428893b
CW		 2321#ifdef CONFIG_IGB_HWMON
2322 /* Initialize the thermal sensor on i350 devices. */
2323 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2324 u16 ets_word;
3c89f6d0 2325
b980ac18 2326 /* Read the NVM to determine if this i350 device supports an
e428893b
CW		 2327 * external thermal sensor.
2328 */
2329 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2330 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2331 adapter->ets = true;
2332 else
2333 adapter->ets = false;
2334 if (igb_sysfs_init(adapter))
2335 dev_err(&pdev->dev,
2336 "failed to allocate sysfs resources\n");
2337 } else {
2338 adapter->ets = false;
2339 }
2340#endif
673b8b70 2341 /* do hw tstamp init after resetting */
7ebae817 2342 igb_ptp_init(adapter);
673b8b70 2343
9d5c8243 2344 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
ceb5f13b
CW		 2345 /* print bus type/speed/width info, not applicable to i354 */
2346 if (hw->mac.type != e1000_i354) {
2347 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2348 netdev->name,
2349 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2350 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2351 "unknown"),
2352 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
2353 "Width x4" :
2354 (hw->bus.width == e1000_bus_width_pcie_x2) ?
2355 "Width x2" :
2356 (hw->bus.width == e1000_bus_width_pcie_x1) ?
2357 "Width x1" : "unknown"), netdev->dev_addr);
2358 }
9d5c8243 2359
9835fd73
CW		 2360 ret_val = igb_read_part_string(hw, part_str, E1000_PBANUM_LENGTH);
2361 if (ret_val)
2362 strcpy(part_str, "Unknown");
2363 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
9d5c8243
AK		 2364 dev_info(&pdev->dev,
2365 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2366 adapter->msix_entries ? "MSI-X" :
7dfc16fa 2367 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243 2368 adapter->num_rx_queues, adapter->num_tx_queues);
09b068d4
CW		 2369 switch (hw->mac.type) {
2370 case e1000_i350:
f96a8a0b
CW		 2371 case e1000_i210:
2372 case e1000_i211:
09b068d4
CW		 2373 igb_set_eee_i350(hw);
2374 break;
ceb5f13b
CW		 2375 case e1000_i354:
2376 if (hw->phy.media_type == e1000_media_type_copper) {
2377 if ((rd32(E1000_CTRL_EXT) &
2378 E1000_CTRL_EXT_LINK_MODE_SGMII))
2379 igb_set_eee_i354(hw);
2380 }
2381 break;
09b068d4
CW		 2382 default:
2383 break;
2384 }
749ab2cd
YZ		 2385
2386 pm_runtime_put_noidle(&pdev->dev);
9d5c8243
AK		 2387 return 0;
2388
2389err_register:
2390 igb_release_hw_control(adapter);
441fc6fd 2391 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
9d5c8243
AK		 2392err_eeprom:
2393 if (!igb_check_reset_block(hw))
f5f4cf08 2394 igb_reset_phy(hw);
9d5c8243
AK		 2395
2396 if (hw->flash_address)
2397 iounmap(hw->flash_address);
9d5c8243 2398err_sw_init:
047e0030 2399 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 2400 iounmap(hw->hw_addr);
2401err_ioremap:
2402 free_netdev(netdev);
2403err_alloc_etherdev:
559e9c49 2404 pci_release_selected_regions(pdev,
b980ac18 2405 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2406err_pci_reg:
2407err_dma:
2408 pci_disable_device(pdev);
2409 return err;
2410}
2411
fa44f2f1
GR		 2412#ifdef CONFIG_PCI_IOV
2413static int igb_disable_sriov(struct pci_dev *pdev)
2414{
2415 struct net_device *netdev = pci_get_drvdata(pdev);
2416 struct igb_adapter *adapter = netdev_priv(netdev);
2417 struct e1000_hw *hw = &adapter->hw;
2418
2419 /* reclaim resources allocated to VFs */
2420 if (adapter->vf_data) {
2421 /* disable iov and allow time for transactions to clear */
b09186d2 2422 if (pci_vfs_assigned(pdev)) {
fa44f2f1
GR		 2423 dev_warn(&pdev->dev,
2424 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2425 return -EPERM;
2426 } else {
2427 pci_disable_sriov(pdev);
2428 msleep(500);
2429 }
2430
2431 kfree(adapter->vf_data);
2432 adapter->vf_data = NULL;
2433 adapter->vfs_allocated_count = 0;
2434 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2435 wrfl();
2436 msleep(100);
2437 dev_info(&pdev->dev, "IOV Disabled\n");
2438
2439 /* Re-enable DMA Coalescing flag since IOV is turned off */
2440 adapter->flags |= IGB_FLAG_DMAC;
2441 }
2442
2443 return 0;
2444}
2445
2446static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2447{
2448 struct net_device *netdev = pci_get_drvdata(pdev);
2449 struct igb_adapter *adapter = netdev_priv(netdev);
2450 int old_vfs = pci_num_vf(pdev);
2451 int err = 0;
2452 int i;
2453
50267196
MW		 2454 if (!adapter->msix_entries) {
2455 err = -EPERM;
2456 goto out;
2457 }
2458
fa44f2f1
GR		 2459 if (!num_vfs)
2460 goto out;
2461 else if (old_vfs && old_vfs == num_vfs)
2462 goto out;
2463 else if (old_vfs && old_vfs != num_vfs)
2464 err = igb_disable_sriov(pdev);
2465
2466 if (err)
2467 goto out;
2468
2469 if (num_vfs > 7) {
2470 err = -EPERM;
2471 goto out;
2472 }
2473
2474 adapter->vfs_allocated_count = num_vfs;
2475
2476 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2477 sizeof(struct vf_data_storage), GFP_KERNEL);
2478
2479 /* if allocation failed then we do not support SR-IOV */
2480 if (!adapter->vf_data) {
2481 adapter->vfs_allocated_count = 0;
2482 dev_err(&pdev->dev,
2483 "Unable to allocate memory for VF Data Storage\n");
2484 err = -ENOMEM;
2485 goto out;
2486 }
2487
2488 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2489 if (err)
2490 goto err_out;
2491
2492 dev_info(&pdev->dev, "%d VFs allocated\n",
2493 adapter->vfs_allocated_count);
2494 for (i = 0; i < adapter->vfs_allocated_count; i++)
2495 igb_vf_configure(adapter, i);
2496
2497 /* DMA Coalescing is not supported in IOV mode. */
2498 adapter->flags &= ~IGB_FLAG_DMAC;
2499 goto out;
2500
2501err_out:
2502 kfree(adapter->vf_data);
2503 adapter->vf_data = NULL;
2504 adapter->vfs_allocated_count = 0;
2505out:
2506 return err;
2507}
2508
2509#endif
b980ac18 2510/**
441fc6fd
CW		 2511 * igb_remove_i2c - Cleanup I2C interface
2512 * @adapter: pointer to adapter structure
b980ac18 2513 **/
441fc6fd
CW		 2514static void igb_remove_i2c(struct igb_adapter *adapter)
2515{
441fc6fd
CW		 2516 /* free the adapter bus structure */
2517 i2c_del_adapter(&adapter->i2c_adap);
2518}
2519
9d5c8243 2520/**
b980ac18
JK		 2521 * igb_remove - Device Removal Routine
2522 * @pdev: PCI device information struct
9d5c8243 2523 *
b980ac18
JK		 2524 * igb_remove is called by the PCI subsystem to alert the driver
2525 * that it should release a PCI device. The could be caused by a
2526 * Hot-Plug event, or because the driver is going to be removed from
2527 * memory.
9d5c8243 2528 **/
9f9a12f8 2529static void igb_remove(struct pci_dev *pdev)
9d5c8243
AK		 2530{
2531 struct net_device *netdev = pci_get_drvdata(pdev);
2532 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 2533 struct e1000_hw *hw = &adapter->hw;
9d5c8243 2534
749ab2cd 2535 pm_runtime_get_noresume(&pdev->dev);
e428893b
CW		 2536#ifdef CONFIG_IGB_HWMON
2537 igb_sysfs_exit(adapter);
2538#endif
441fc6fd 2539 igb_remove_i2c(adapter);
a79f4f88 2540 igb_ptp_stop(adapter);
b980ac18 2541 /* The watchdog timer may be rescheduled, so explicitly
760141a5
TH		 2542 * disable watchdog from being rescheduled.
2543 */
9d5c8243
AK		 2544 set_bit(__IGB_DOWN, &adapter->state);
2545 del_timer_sync(&adapter->watchdog_timer);
2546 del_timer_sync(&adapter->phy_info_timer);
2547
760141a5
TH		 2548 cancel_work_sync(&adapter->reset_task);
2549 cancel_work_sync(&adapter->watchdog_task);
9d5c8243 2550
421e02f0 2551#ifdef CONFIG_IGB_DCA
7dfc16fa 2552 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 2553 dev_info(&pdev->dev, "DCA disabled\n");
2554 dca_remove_requester(&pdev->dev);
7dfc16fa 2555 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 2556 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 2557 }
2558#endif
2559
9d5c8243 2560 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 2561 * would have already happened in close and is redundant.
2562 */
9d5c8243
AK		 2563 igb_release_hw_control(adapter);
2564
2565 unregister_netdev(netdev);
2566
047e0030 2567 igb_clear_interrupt_scheme(adapter);
9d5c8243 2568
37680117 2569#ifdef CONFIG_PCI_IOV
fa44f2f1 2570 igb_disable_sriov(pdev);
37680117 2571#endif
559e9c49 2572
28b0759c
AD		 2573 iounmap(hw->hw_addr);
2574 if (hw->flash_address)
2575 iounmap(hw->flash_address);
559e9c49 2576 pci_release_selected_regions(pdev,
b980ac18 2577 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243 2578
1128c756 2579 kfree(adapter->shadow_vfta);
9d5c8243
AK		 2580 free_netdev(netdev);
2581
19d5afd4 2582 pci_disable_pcie_error_reporting(pdev);
40a914fa 2583
9d5c8243
AK		 2584 pci_disable_device(pdev);
2585}
2586
a6b623e0 2587/**
b980ac18
JK		 2588 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2589 * @adapter: board private structure to initialize
a6b623e0 2590 *
b980ac18
JK		 2591 * This function initializes the vf specific data storage and then attempts to
2592 * allocate the VFs. The reason for ordering it this way is because it is much
2593 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2594 * the memory for the VFs.
a6b623e0 2595 **/
9f9a12f8 2596static void igb_probe_vfs(struct igb_adapter *adapter)
a6b623e0
AD		 2597{
2598#ifdef CONFIG_PCI_IOV
2599 struct pci_dev *pdev = adapter->pdev;
f96a8a0b 2600 struct e1000_hw *hw = &adapter->hw;
a6b623e0 2601
f96a8a0b
CW		 2602 /* Virtualization features not supported on i210 family. */
2603 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2604 return;
2605
fa44f2f1 2606 pci_sriov_set_totalvfs(pdev, 7);
d5e51a10 2607 igb_enable_sriov(pdev, max_vfs);
0224d663 2608
a6b623e0
AD		 2609#endif /* CONFIG_PCI_IOV */
2610}
2611
fa44f2f1 2612static void igb_init_queue_configuration(struct igb_adapter *adapter)
9d5c8243
AK		 2613{
2614 struct e1000_hw *hw = &adapter->hw;
374a542d 2615 u32 max_rss_queues;
9d5c8243 2616
374a542d 2617 /* Determine the maximum number of RSS queues supported. */
f96a8a0b 2618 switch (hw->mac.type) {
374a542d
MV		 2619 case e1000_i211:
2620 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2621 break;
2622 case e1000_82575:
f96a8a0b 2623 case e1000_i210:
374a542d
MV		 2624 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2625 break;
2626 case e1000_i350:
2627 /* I350 cannot do RSS and SR-IOV at the same time */
2628 if (!!adapter->vfs_allocated_count) {
2629 max_rss_queues = 1;
2630 break;
2631 }
2632 /* fall through */
2633 case e1000_82576:
2634 if (!!adapter->vfs_allocated_count) {
2635 max_rss_queues = 2;
2636 break;
2637 }
2638 /* fall through */
2639 case e1000_82580:
ceb5f13b 2640 case e1000_i354:
374a542d
MV		 2641 default:
2642 max_rss_queues = IGB_MAX_RX_QUEUES;
f96a8a0b 2643 break;
374a542d
MV		 2644 }
2645
2646 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2647
2648 /* Determine if we need to pair queues. */
2649 switch (hw->mac.type) {
2650 case e1000_82575:
f96a8a0b 2651 case e1000_i211:
374a542d 2652 /* Device supports enough interrupts without queue pairing. */
f96a8a0b 2653 break;
374a542d 2654 case e1000_82576:
b980ac18 2655 /* If VFs are going to be allocated with RSS queues then we
374a542d
MV		 2656 * should pair the queues in order to conserve interrupts due
2657 * to limited supply.
2658 */
2659 if ((adapter->rss_queues > 1) &&
2660 (adapter->vfs_allocated_count > 6))
2661 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2662 /* fall through */
2663 case e1000_82580:
2664 case e1000_i350:
ceb5f13b 2665 case e1000_i354:
374a542d 2666 case e1000_i210:
f96a8a0b 2667 default:
b980ac18 2668 /* If rss_queues > half of max_rss_queues, pair the queues in
374a542d
MV		 2669 * order to conserve interrupts due to limited supply.
2670 */
2671 if (adapter->rss_queues > (max_rss_queues / 2))
2672 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
f96a8a0b
CW		 2673 break;
2674 }
fa44f2f1
GR		 2675}
2676
2677/**
b980ac18
JK		 2678 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2679 * @adapter: board private structure to initialize
fa44f2f1 2680 *
b980ac18
JK		 2681 * igb_sw_init initializes the Adapter private data structure.
2682 * Fields are initialized based on PCI device information and
2683 * OS network device settings (MTU size).
fa44f2f1
GR		 2684 **/
2685static int igb_sw_init(struct igb_adapter *adapter)
2686{
2687 struct e1000_hw *hw = &adapter->hw;
2688 struct net_device *netdev = adapter->netdev;
2689 struct pci_dev *pdev = adapter->pdev;
2690
2691 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2692
2693 /* set default ring sizes */
2694 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2695 adapter->rx_ring_count = IGB_DEFAULT_RXD;
2696
2697 /* set default ITR values */
2698 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2699 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2700
2701 /* set default work limits */
2702 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2703
2704 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2705 VLAN_HLEN;
2706 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2707
2708 spin_lock_init(&adapter->stats64_lock);
2709#ifdef CONFIG_PCI_IOV
2710 switch (hw->mac.type) {
2711 case e1000_82576:
2712 case e1000_i350:
2713 if (max_vfs > 7) {
2714 dev_warn(&pdev->dev,
2715 "Maximum of 7 VFs per PF, using max\n");
d0f63acc 2716 max_vfs = adapter->vfs_allocated_count = 7;
fa44f2f1
GR		 2717 } else
2718 adapter->vfs_allocated_count = max_vfs;
2719 if (adapter->vfs_allocated_count)
2720 dev_warn(&pdev->dev,
2721 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2722 break;
2723 default:
2724 break;
2725 }
2726#endif /* CONFIG_PCI_IOV */
2727
2728 igb_init_queue_configuration(adapter);
a99955fc 2729
1128c756 2730 /* Setup and initialize a copy of the hw vlan table array */
b2adaca9
JP		 2731 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
2732 GFP_ATOMIC);
1128c756 2733
a6b623e0 2734 /* This call may decrease the number of queues */
53c7d064 2735 if (igb_init_interrupt_scheme(adapter, true)) {
9d5c8243
AK		 2736 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2737 return -ENOMEM;
2738 }
2739
a6b623e0
AD		 2740 igb_probe_vfs(adapter);
2741
9d5c8243
AK		 2742 /* Explicitly disable IRQ since the NIC can be in any state. */
2743 igb_irq_disable(adapter);
2744
f96a8a0b 2745 if (hw->mac.type >= e1000_i350)
831ec0b4
CW		 2746 adapter->flags &= ~IGB_FLAG_DMAC;
2747
9d5c8243
AK		 2748 set_bit(__IGB_DOWN, &adapter->state);
2749 return 0;
2750}
2751
2752/**
b980ac18
JK		 2753 * igb_open - Called when a network interface is made active
2754 * @netdev: network interface device structure
9d5c8243 2755 *
b980ac18 2756 * Returns 0 on success, negative value on failure
9d5c8243 2757 *
b980ac18
JK		 2758 * The open entry point is called when a network interface is made
2759 * active by the system (IFF_UP). At this point all resources needed
2760 * for transmit and receive operations are allocated, the interrupt
2761 * handler is registered with the OS, the watchdog timer is started,
2762 * and the stack is notified that the interface is ready.
9d5c8243 2763 **/
749ab2cd 2764static int __igb_open(struct net_device *netdev, bool resuming)
9d5c8243
AK		 2765{
2766 struct igb_adapter *adapter = netdev_priv(netdev);
2767 struct e1000_hw *hw = &adapter->hw;
749ab2cd 2768 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2769 int err;
2770 int i;
2771
2772 /* disallow open during test */
749ab2cd
YZ		 2773 if (test_bit(__IGB_TESTING, &adapter->state)) {
2774 WARN_ON(resuming);
9d5c8243 2775 return -EBUSY;
749ab2cd
YZ		 2776 }
2777
2778 if (!resuming)
2779 pm_runtime_get_sync(&pdev->dev);
9d5c8243 2780
b168dfc5
JB		 2781 netif_carrier_off(netdev);
2782
9d5c8243
AK		 2783 /* allocate transmit descriptors */
2784 err = igb_setup_all_tx_resources(adapter);
2785 if (err)
2786 goto err_setup_tx;
2787
2788 /* allocate receive descriptors */
2789 err = igb_setup_all_rx_resources(adapter);
2790 if (err)
2791 goto err_setup_rx;
2792
88a268c1 2793 igb_power_up_link(adapter);
9d5c8243 2794
9d5c8243
AK		 2795 /* before we allocate an interrupt, we must be ready to handle it.
2796 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
2797 * as soon as we call pci_request_irq, so we have to setup our
b980ac18
JK		 2798 * clean_rx handler before we do so.
2799 */
9d5c8243
AK		 2800 igb_configure(adapter);
2801
2802 err = igb_request_irq(adapter);
2803 if (err)
2804 goto err_req_irq;
2805
0c2cc02e
AD		 2806 /* Notify the stack of the actual queue counts. */
2807 err = netif_set_real_num_tx_queues(adapter->netdev,
2808 adapter->num_tx_queues);
2809 if (err)
2810 goto err_set_queues;
2811
2812 err = netif_set_real_num_rx_queues(adapter->netdev,
2813 adapter->num_rx_queues);
2814 if (err)
2815 goto err_set_queues;
2816
9d5c8243
AK		 2817 /* From here on the code is the same as igb_up() */
2818 clear_bit(__IGB_DOWN, &adapter->state);
2819
0d1ae7f4
AD		 2820 for (i = 0; i < adapter->num_q_vectors; i++)
2821 napi_enable(&(adapter->q_vector[i]->napi));
9d5c8243
AK		 2822
2823 /* Clear any pending interrupts. */
2824 rd32(E1000_ICR);
844290e5
PW		 2825
2826 igb_irq_enable(adapter);
2827
d4960307
AD		 2828 /* notify VFs that reset has been completed */
2829 if (adapter->vfs_allocated_count) {
2830 u32 reg_data = rd32(E1000_CTRL_EXT);
2831 reg_data |= E1000_CTRL_EXT_PFRSTD;
2832 wr32(E1000_CTRL_EXT, reg_data);
2833 }
2834
d55b53ff
JK		 2835 netif_tx_start_all_queues(netdev);
2836
749ab2cd
YZ		 2837 if (!resuming)
2838 pm_runtime_put(&pdev->dev);
2839
25568a53
AD		 2840 /* start the watchdog. */
2841 hw->mac.get_link_status = 1;
2842 schedule_work(&adapter->watchdog_task);
9d5c8243
AK		 2843
2844 return 0;
2845
0c2cc02e
AD		 2846err_set_queues:
2847 igb_free_irq(adapter);
9d5c8243
AK		 2848err_req_irq:
2849 igb_release_hw_control(adapter);
88a268c1 2850 igb_power_down_link(adapter);
9d5c8243
AK		 2851 igb_free_all_rx_resources(adapter);
2852err_setup_rx:
2853 igb_free_all_tx_resources(adapter);
2854err_setup_tx:
2855 igb_reset(adapter);
749ab2cd
YZ		 2856 if (!resuming)
2857 pm_runtime_put(&pdev->dev);
9d5c8243
AK		 2858
2859 return err;
2860}
2861
749ab2cd
YZ		 2862static int igb_open(struct net_device *netdev)
2863{
2864 return __igb_open(netdev, false);
2865}
2866
9d5c8243 2867/**
b980ac18
JK		 2868 * igb_close - Disables a network interface
2869 * @netdev: network interface device structure
9d5c8243 2870 *
b980ac18 2871 * Returns 0, this is not allowed to fail
9d5c8243 2872 *
b980ac18
JK		 2873 * The close entry point is called when an interface is de-activated
2874 * by the OS. The hardware is still under the driver's control, but
2875 * needs to be disabled. A global MAC reset is issued to stop the
2876 * hardware, and all transmit and receive resources are freed.
9d5c8243 2877 **/
749ab2cd 2878static int __igb_close(struct net_device *netdev, bool suspending)
9d5c8243
AK		 2879{
2880 struct igb_adapter *adapter = netdev_priv(netdev);
749ab2cd 2881 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2882
2883 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
9d5c8243 2884
749ab2cd
YZ		 2885 if (!suspending)
2886 pm_runtime_get_sync(&pdev->dev);
2887
2888 igb_down(adapter);
9d5c8243
AK		 2889 igb_free_irq(adapter);
2890
2891 igb_free_all_tx_resources(adapter);
2892 igb_free_all_rx_resources(adapter);
2893
749ab2cd
YZ		 2894 if (!suspending)
2895 pm_runtime_put_sync(&pdev->dev);
9d5c8243
AK		 2896 return 0;
2897}
2898
749ab2cd
YZ		 2899static int igb_close(struct net_device *netdev)
2900{
2901 return __igb_close(netdev, false);
2902}
2903
9d5c8243 2904/**
b980ac18
JK		 2905 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
2906 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9d5c8243 2907 *
b980ac18 2908 * Return 0 on success, negative on failure
9d5c8243 2909 **/
80785298 2910int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2911{
59d71989 2912 struct device *dev = tx_ring->dev;
9d5c8243
AK		 2913 int size;
2914
06034649 2915 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
f33005a6
AD		 2916
2917 tx_ring->tx_buffer_info = vzalloc(size);
06034649 2918 if (!tx_ring->tx_buffer_info)
9d5c8243 2919 goto err;
9d5c8243
AK		 2920
2921 /* round up to nearest 4K */
85e8d004 2922 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 2923 tx_ring->size = ALIGN(tx_ring->size, 4096);
2924
5536d210
AD		 2925 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
2926 &tx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 2927 if (!tx_ring->desc)
2928 goto err;
2929
9d5c8243
AK		 2930 tx_ring->next_to_use = 0;
2931 tx_ring->next_to_clean = 0;
81c2fc22 2932
9d5c8243
AK		 2933 return 0;
2934
2935err:
06034649 2936 vfree(tx_ring->tx_buffer_info);
f33005a6
AD		 2937 tx_ring->tx_buffer_info = NULL;
2938 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
9d5c8243
AK		 2939 return -ENOMEM;
2940}
2941
2942/**
b980ac18
JK		 2943 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
2944 * (Descriptors) for all queues
2945 * @adapter: board private structure
9d5c8243 2946 *
b980ac18 2947 * Return 0 on success, negative on failure
9d5c8243
AK		 2948 **/
2949static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
2950{
439705e1 2951 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2952 int i, err = 0;
2953
2954 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 2955 err = igb_setup_tx_resources(adapter->tx_ring[i]);
9d5c8243 2956 if (err) {
439705e1 2957 dev_err(&pdev->dev,
9d5c8243
AK		 2958 "Allocation for Tx Queue %u failed\n", i);
2959 for (i--; i >= 0; i--)
3025a446 2960 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 2961 break;
2962 }
2963 }
2964
2965 return err;
2966}
2967
2968/**
b980ac18
JK		 2969 * igb_setup_tctl - configure the transmit control registers
2970 * @adapter: Board private structure
9d5c8243 2971 **/
d7ee5b3a 2972void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 2973{
9d5c8243
AK		 2974 struct e1000_hw *hw = &adapter->hw;
2975 u32 tctl;
9d5c8243 2976
85b430b4
AD		 2977 /* disable queue 0 which is enabled by default on 82575 and 82576 */
2978 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 2979
2980 /* Program the Transmit Control Register */
9d5c8243
AK		 2981 tctl = rd32(E1000_TCTL);
2982 tctl &= ~E1000_TCTL_CT;
2983 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2984 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2985
2986 igb_config_collision_dist(hw);
2987
9d5c8243
AK		 2988 /* Enable transmits */
2989 tctl |= E1000_TCTL_EN;
2990
2991 wr32(E1000_TCTL, tctl);
2992}
2993
85b430b4 2994/**
b980ac18
JK		 2995 * igb_configure_tx_ring - Configure transmit ring after Reset
2996 * @adapter: board private structure
2997 * @ring: tx ring to configure
85b430b4 2998 *
b980ac18 2999 * Configure a transmit ring after a reset.
85b430b4 3000 **/
d7ee5b3a
AD		 3001void igb_configure_tx_ring(struct igb_adapter *adapter,
3002 struct igb_ring *ring)
85b430b4
AD		 3003{
3004 struct e1000_hw *hw = &adapter->hw;
a74420e0 3005 u32 txdctl = 0;
85b430b4
AD		 3006 u64 tdba = ring->dma;
3007 int reg_idx = ring->reg_idx;
3008
3009 /* disable the queue */
a74420e0 3010 wr32(E1000_TXDCTL(reg_idx), 0);
85b430b4
AD		 3011 wrfl();
3012 mdelay(10);
3013
3014 wr32(E1000_TDLEN(reg_idx),
b980ac18 3015 ring->count * sizeof(union e1000_adv_tx_desc));
85b430b4 3016 wr32(E1000_TDBAL(reg_idx),
b980ac18 3017 tdba & 0x00000000ffffffffULL);
85b430b4
AD		 3018 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
3019
fce99e34 3020 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
a74420e0 3021 wr32(E1000_TDH(reg_idx), 0);
fce99e34 3022 writel(0, ring->tail);
85b430b4
AD		 3023
3024 txdctl |= IGB_TX_PTHRESH;
3025 txdctl |= IGB_TX_HTHRESH << 8;
3026 txdctl |= IGB_TX_WTHRESH << 16;
3027
3028 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
3029 wr32(E1000_TXDCTL(reg_idx), txdctl);
3030}
3031
3032/**
b980ac18
JK		 3033 * igb_configure_tx - Configure transmit Unit after Reset
3034 * @adapter: board private structure
85b430b4 3035 *
b980ac18 3036 * Configure the Tx unit of the MAC after a reset.
85b430b4
AD		 3037 **/
3038static void igb_configure_tx(struct igb_adapter *adapter)
3039{
3040 int i;
3041
3042 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3043 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
85b430b4
AD		 3044}
3045
9d5c8243 3046/**
b980ac18
JK		 3047 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
3048 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
9d5c8243 3049 *
b980ac18 3050 * Returns 0 on success, negative on failure
9d5c8243 3051 **/
80785298 3052int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3053{
59d71989 3054 struct device *dev = rx_ring->dev;
f33005a6 3055 int size;
9d5c8243 3056
06034649 3057 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
f33005a6
AD		 3058
3059 rx_ring->rx_buffer_info = vzalloc(size);
06034649 3060 if (!rx_ring->rx_buffer_info)
9d5c8243 3061 goto err;
9d5c8243 3062
9d5c8243 3063 /* Round up to nearest 4K */
f33005a6 3064 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
9d5c8243
AK		 3065 rx_ring->size = ALIGN(rx_ring->size, 4096);
3066
5536d210
AD		 3067 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3068 &rx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3069 if (!rx_ring->desc)
3070 goto err;
3071
cbc8e55f 3072 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3073 rx_ring->next_to_clean = 0;
3074 rx_ring->next_to_use = 0;
9d5c8243 3075
9d5c8243
AK		 3076 return 0;
3077
3078err:
06034649
AD		 3079 vfree(rx_ring->rx_buffer_info);
3080 rx_ring->rx_buffer_info = NULL;
f33005a6 3081 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
9d5c8243
AK		 3082 return -ENOMEM;
3083}
3084
3085/**
b980ac18
JK		 3086 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3087 * (Descriptors) for all queues
3088 * @adapter: board private structure
9d5c8243 3089 *
b980ac18 3090 * Return 0 on success, negative on failure
9d5c8243
AK		 3091 **/
3092static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3093{
439705e1 3094 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3095 int i, err = 0;
3096
3097 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 3098 err = igb_setup_rx_resources(adapter->rx_ring[i]);
9d5c8243 3099 if (err) {
439705e1 3100 dev_err(&pdev->dev,
9d5c8243
AK		 3101 "Allocation for Rx Queue %u failed\n", i);
3102 for (i--; i >= 0; i--)
3025a446 3103 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3104 break;
3105 }
3106 }
3107
3108 return err;
3109}
3110
06cf2666 3111/**
b980ac18
JK		 3112 * igb_setup_mrqc - configure the multiple receive queue control registers
3113 * @adapter: Board private structure
06cf2666
AD		 3114 **/
3115static void igb_setup_mrqc(struct igb_adapter *adapter)
3116{
3117 struct e1000_hw *hw = &adapter->hw;
3118 u32 mrqc, rxcsum;
797fd4be 3119 u32 j, num_rx_queues, shift = 0;
a57fe23e
AD		 3120 static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741,
3121 0xB08FA343, 0xCB2BCAD0, 0xB4307BAE,
3122 0xA32DCB77, 0x0CF23080, 0x3BB7426A,
3123 0xFA01ACBE };
06cf2666
AD		 3124
3125 /* Fill out hash function seeds */
a57fe23e
AD		 3126 for (j = 0; j < 10; j++)
3127 wr32(E1000_RSSRK(j), rsskey[j]);
06cf2666 3128
a99955fc 3129 num_rx_queues = adapter->rss_queues;
06cf2666 3130
797fd4be
AD		 3131 switch (hw->mac.type) {
3132 case e1000_82575:
3133 shift = 6;
3134 break;
3135 case e1000_82576:
3136 /* 82576 supports 2 RSS queues for SR-IOV */
3137 if (adapter->vfs_allocated_count) {
06cf2666
AD		 3138 shift = 3;
3139 num_rx_queues = 2;
06cf2666 3140 }
797fd4be
AD		 3141 break;
3142 default:
3143 break;
06cf2666
AD		 3144 }
3145
b980ac18 3146 /* Populate the indirection table 4 entries at a time. To do this
797fd4be
AD		 3147 * we are generating the results for n and n+2 and then interleaving
3148 * those with the results with n+1 and n+3.
3149 */
3150 for (j = 0; j < 32; j++) {
3151 /* first pass generates n and n+2 */
3152 u32 base = ((j * 0x00040004) + 0x00020000) * num_rx_queues;
3153 u32 reta = (base & 0x07800780) >> (7 - shift);
3154
3155 /* second pass generates n+1 and n+3 */
3156 base += 0x00010001 * num_rx_queues;
3157 reta |= (base & 0x07800780) << (1 + shift);
3158
3159 wr32(E1000_RETA(j), reta);
06cf2666
AD		 3160 }
3161
b980ac18 3162 /* Disable raw packet checksumming so that RSS hash is placed in
06cf2666
AD		 3163 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3164 * offloads as they are enabled by default
3165 */
3166 rxcsum = rd32(E1000_RXCSUM);
3167 rxcsum |= E1000_RXCSUM_PCSD;
3168
3169 if (adapter->hw.mac.type >= e1000_82576)
3170 /* Enable Receive Checksum Offload for SCTP */
3171 rxcsum |= E1000_RXCSUM_CRCOFL;
3172
3173 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3174 wr32(E1000_RXCSUM, rxcsum);
f96a8a0b 3175
039454a8
AA		 3176 /* Generate RSS hash based on packet types, TCP/UDP
3177 * port numbers and/or IPv4/v6 src and dst addresses
3178 */
f96a8a0b
CW		 3179 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3180 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3181 E1000_MRQC_RSS_FIELD_IPV6 |
3182 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3183 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
06cf2666 3184
039454a8
AA		 3185 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3186 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3187 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3188 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3189
06cf2666
AD		 3190 /* If VMDq is enabled then we set the appropriate mode for that, else
3191 * we default to RSS so that an RSS hash is calculated per packet even
b980ac18
JK		 3192 * if we are only using one queue
3193 */
06cf2666
AD		 3194 if (adapter->vfs_allocated_count) {
3195 if (hw->mac.type > e1000_82575) {
3196 /* Set the default pool for the PF's first queue */
3197 u32 vtctl = rd32(E1000_VT_CTL);
3198 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3199 E1000_VT_CTL_DISABLE_DEF_POOL);
3200 vtctl |= adapter->vfs_allocated_count <<
3201 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3202 wr32(E1000_VT_CTL, vtctl);
3203 }
a99955fc 3204 if (adapter->rss_queues > 1)
f96a8a0b 3205 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
06cf2666 3206 else
f96a8a0b 3207 mrqc |= E1000_MRQC_ENABLE_VMDQ;
06cf2666 3208 } else {
f96a8a0b
CW		 3209 if (hw->mac.type != e1000_i211)
3210 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
06cf2666
AD		 3211 }
3212 igb_vmm_control(adapter);
3213
06cf2666
AD		 3214 wr32(E1000_MRQC, mrqc);
3215}
3216
9d5c8243 3217/**
b980ac18
JK		 3218 * igb_setup_rctl - configure the receive control registers
3219 * @adapter: Board private structure
9d5c8243 3220 **/
d7ee5b3a 3221void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 3222{
3223 struct e1000_hw *hw = &adapter->hw;
3224 u32 rctl;
9d5c8243
AK		 3225
3226 rctl = rd32(E1000_RCTL);
3227
3228 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 3229 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 3230
69d728ba 3231 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 3232 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 3233
b980ac18 3234 /* enable stripping of CRC. It's unlikely this will break BMC
87cb7e8c
AK		 3235 * redirection as it did with e1000. Newer features require
3236 * that the HW strips the CRC.
73cd78f1 3237 */
87cb7e8c 3238 rctl |= E1000_RCTL_SECRC;
9d5c8243 3239
559e9c49 3240 /* disable store bad packets and clear size bits. */
ec54d7d6 3241 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 3242
6ec43fe6
AD		 3243 /* enable LPE to prevent packets larger than max_frame_size */
3244 rctl |= E1000_RCTL_LPE;
9d5c8243 3245
952f72a8
AD		 3246 /* disable queue 0 to prevent tail write w/o re-config */
3247 wr32(E1000_RXDCTL(0), 0);
9d5c8243 3248
e1739522
AD		 3249 /* Attention!!! For SR-IOV PF driver operations you must enable
3250 * queue drop for all VF and PF queues to prevent head of line blocking
3251 * if an un-trusted VF does not provide descriptors to hardware.
3252 */
3253 if (adapter->vfs_allocated_count) {
e1739522
AD		 3254 /* set all queue drop enable bits */
3255 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 3256 }
3257
89eaefb6
BG		 3258 /* This is useful for sniffing bad packets. */
3259 if (adapter->netdev->features & NETIF_F_RXALL) {
3260 /* UPE and MPE will be handled by normal PROMISC logic
b980ac18
JK		 3261 * in e1000e_set_rx_mode
3262 */
89eaefb6
BG		 3263 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3264 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3265 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3266
3267 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3268 E1000_RCTL_DPF | /* Allow filtered pause */
3269 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3270 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3271 * and that breaks VLANs.
3272 */
3273 }
3274
9d5c8243
AK		 3275 wr32(E1000_RCTL, rctl);
3276}
3277
7d5753f0
AD		 3278static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
3279 int vfn)
3280{
3281 struct e1000_hw *hw = &adapter->hw;
3282 u32 vmolr;
3283
3284 /* if it isn't the PF check to see if VFs are enabled and
b980ac18
JK		 3285 * increase the size to support vlan tags
3286 */
7d5753f0
AD		 3287 if (vfn < adapter->vfs_allocated_count &&
3288 adapter->vf_data[vfn].vlans_enabled)
3289 size += VLAN_TAG_SIZE;
3290
3291 vmolr = rd32(E1000_VMOLR(vfn));
3292 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3293 vmolr |= size | E1000_VMOLR_LPE;
3294 wr32(E1000_VMOLR(vfn), vmolr);
3295
3296 return 0;
3297}
3298
e1739522 3299/**
b980ac18
JK		 3300 * igb_rlpml_set - set maximum receive packet size
3301 * @adapter: board private structure
e1739522 3302 *
b980ac18 3303 * Configure maximum receivable packet size.
e1739522
AD		 3304 **/
3305static void igb_rlpml_set(struct igb_adapter *adapter)
3306{
153285f9 3307 u32 max_frame_size = adapter->max_frame_size;
e1739522
AD		 3308 struct e1000_hw *hw = &adapter->hw;
3309 u16 pf_id = adapter->vfs_allocated_count;
3310
e1739522
AD		 3311 if (pf_id) {
3312 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
b980ac18 3313 /* If we're in VMDQ or SR-IOV mode, then set global RLPML
153285f9
AD		 3314 * to our max jumbo frame size, in case we need to enable
3315 * jumbo frames on one of the rings later.
3316 * This will not pass over-length frames into the default
3317 * queue because it's gated by the VMOLR.RLPML.
3318 */
7d5753f0 3319 max_frame_size = MAX_JUMBO_FRAME_SIZE;
e1739522
AD		 3320 }
3321
3322 wr32(E1000_RLPML, max_frame_size);
3323}
3324
8151d294
WM		 3325static inline void igb_set_vmolr(struct igb_adapter *adapter,
3326 int vfn, bool aupe)
7d5753f0
AD		 3327{
3328 struct e1000_hw *hw = &adapter->hw;
3329 u32 vmolr;
3330
b980ac18 3331 /* This register exists only on 82576 and newer so if we are older then
7d5753f0
AD		 3332 * we should exit and do nothing
3333 */
3334 if (hw->mac.type < e1000_82576)
3335 return;
3336
3337 vmolr = rd32(E1000_VMOLR(vfn));
b980ac18 3338 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
8151d294 3339 if (aupe)
b980ac18 3340 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
8151d294
WM		 3341 else
3342 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
7d5753f0
AD		 3343
3344 /* clear all bits that might not be set */
3345 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3346
a99955fc 3347 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
7d5753f0 3348 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
b980ac18 3349 /* for VMDq only allow the VFs and pool 0 to accept broadcast and
7d5753f0
AD		 3350 * multicast packets
3351 */
3352 if (vfn <= adapter->vfs_allocated_count)
b980ac18 3353 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
7d5753f0
AD		 3354
3355 wr32(E1000_VMOLR(vfn), vmolr);
3356}
3357
85b430b4 3358/**
b980ac18
JK		 3359 * igb_configure_rx_ring - Configure a receive ring after Reset
3360 * @adapter: board private structure
3361 * @ring: receive ring to be configured
85b430b4 3362 *
b980ac18 3363 * Configure the Rx unit of the MAC after a reset.
85b430b4 3364 **/
d7ee5b3a 3365void igb_configure_rx_ring(struct igb_adapter *adapter,
b980ac18 3366 struct igb_ring *ring)
85b430b4
AD		 3367{
3368 struct e1000_hw *hw = &adapter->hw;
3369 u64 rdba = ring->dma;
3370 int reg_idx = ring->reg_idx;
a74420e0 3371 u32 srrctl = 0, rxdctl = 0;
85b430b4
AD		 3372
3373 /* disable the queue */
a74420e0 3374 wr32(E1000_RXDCTL(reg_idx), 0);
85b430b4
AD		 3375
3376 /* Set DMA base address registers */
3377 wr32(E1000_RDBAL(reg_idx),
3378 rdba & 0x00000000ffffffffULL);
3379 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3380 wr32(E1000_RDLEN(reg_idx),
b980ac18 3381 ring->count * sizeof(union e1000_adv_rx_desc));
85b430b4
AD		 3382
3383 /* initialize head and tail */
fce99e34 3384 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
a74420e0 3385 wr32(E1000_RDH(reg_idx), 0);
fce99e34 3386 writel(0, ring->tail);
85b430b4 3387
952f72a8 3388 /* set descriptor configuration */
44390ca6 3389 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
de78d1f9 3390 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1a1c225b 3391 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
06218a8d 3392 if (hw->mac.type >= e1000_82580)
757b77e2 3393 srrctl |= E1000_SRRCTL_TIMESTAMP;
e6bdb6fe
NN		 3394 /* Only set Drop Enable if we are supporting multiple queues */
3395 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3396 srrctl |= E1000_SRRCTL_DROP_EN;
952f72a8
AD		 3397
3398 wr32(E1000_SRRCTL(reg_idx), srrctl);
3399
7d5753f0 3400 /* set filtering for VMDQ pools */
8151d294 3401 igb_set_vmolr(adapter, reg_idx & 0x7, true);
7d5753f0 3402
85b430b4
AD		 3403 rxdctl |= IGB_RX_PTHRESH;
3404 rxdctl |= IGB_RX_HTHRESH << 8;
3405 rxdctl |= IGB_RX_WTHRESH << 16;
a74420e0
AD		 3406
3407 /* enable receive descriptor fetching */
3408 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
85b430b4
AD		 3409 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3410}
3411
9d5c8243 3412/**
b980ac18
JK		 3413 * igb_configure_rx - Configure receive Unit after Reset
3414 * @adapter: board private structure
9d5c8243 3415 *
b980ac18 3416 * Configure the Rx unit of the MAC after a reset.
9d5c8243
AK		 3417 **/
3418static void igb_configure_rx(struct igb_adapter *adapter)
3419{
9107584e 3420 int i;
9d5c8243 3421
68d480c4
AD		 3422 /* set UTA to appropriate mode */
3423 igb_set_uta(adapter);
3424
26ad9178
AD		 3425 /* set the correct pool for the PF default MAC address in entry 0 */
3426 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
b980ac18 3427 adapter->vfs_allocated_count);
26ad9178 3428
06cf2666 3429 /* Setup the HW Rx Head and Tail Descriptor Pointers and
b980ac18
JK		 3430 * the Base and Length of the Rx Descriptor Ring
3431 */
f9d40f6a
AD		 3432 for (i = 0; i < adapter->num_rx_queues; i++)
3433 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
9d5c8243
AK		 3434}
3435
3436/**
b980ac18
JK		 3437 * igb_free_tx_resources - Free Tx Resources per Queue
3438 * @tx_ring: Tx descriptor ring for a specific queue
9d5c8243 3439 *
b980ac18 3440 * Free all transmit software resources
9d5c8243 3441 **/
68fd9910 3442void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3443{
3b644cf6 3444 igb_clean_tx_ring(tx_ring);
9d5c8243 3445
06034649
AD		 3446 vfree(tx_ring->tx_buffer_info);
3447 tx_ring->tx_buffer_info = NULL;
9d5c8243 3448
439705e1
AD		 3449 /* if not set, then don't free */
3450 if (!tx_ring->desc)
3451 return;
3452
59d71989
AD		 3453 dma_free_coherent(tx_ring->dev, tx_ring->size,
3454 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 3455
3456 tx_ring->desc = NULL;
3457}
3458
3459/**
b980ac18
JK		 3460 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3461 * @adapter: board private structure
9d5c8243 3462 *
b980ac18 3463 * Free all transmit software resources
9d5c8243
AK		 3464 **/
3465static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3466{
3467 int i;
3468
3469 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3470 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3471}
3472
ebe42d16
AD		 3473void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3474 struct igb_tx_buffer *tx_buffer)
3475{
3476 if (tx_buffer->skb) {
3477 dev_kfree_skb_any(tx_buffer->skb);
c9f14bf3 3478 if (dma_unmap_len(tx_buffer, len))
ebe42d16 3479 dma_unmap_single(ring->dev,
c9f14bf3
AD		 3480 dma_unmap_addr(tx_buffer, dma),
3481 dma_unmap_len(tx_buffer, len),
ebe42d16 3482 DMA_TO_DEVICE);
c9f14bf3 3483 } else if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 3484 dma_unmap_page(ring->dev,
c9f14bf3
AD		 3485 dma_unmap_addr(tx_buffer, dma),
3486 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 3487 DMA_TO_DEVICE);
3488 }
3489 tx_buffer->next_to_watch = NULL;
3490 tx_buffer->skb = NULL;
c9f14bf3 3491 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16 3492 /* buffer_info must be completely set up in the transmit path */
9d5c8243
AK		 3493}
3494
3495/**
b980ac18
JK		 3496 * igb_clean_tx_ring - Free Tx Buffers
3497 * @tx_ring: ring to be cleaned
9d5c8243 3498 **/
3b644cf6 3499static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 3500{
06034649 3501 struct igb_tx_buffer *buffer_info;
9d5c8243 3502 unsigned long size;
6ad4edfc 3503 u16 i;
9d5c8243 3504
06034649 3505 if (!tx_ring->tx_buffer_info)
9d5c8243
AK		 3506 return;
3507 /* Free all the Tx ring sk_buffs */
3508
3509 for (i = 0; i < tx_ring->count; i++) {
06034649 3510 buffer_info = &tx_ring->tx_buffer_info[i];
80785298 3511 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 3512 }
3513
dad8a3b3
JF		 3514 netdev_tx_reset_queue(txring_txq(tx_ring));
3515
06034649
AD		 3516 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3517 memset(tx_ring->tx_buffer_info, 0, size);
9d5c8243
AK		 3518
3519 /* Zero out the descriptor ring */
9d5c8243
AK		 3520 memset(tx_ring->desc, 0, tx_ring->size);
3521
3522 tx_ring->next_to_use = 0;
3523 tx_ring->next_to_clean = 0;
9d5c8243
AK		 3524}
3525
3526/**
b980ac18
JK		 3527 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3528 * @adapter: board private structure
9d5c8243
AK		 3529 **/
3530static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3531{
3532 int i;
3533
3534 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3535 igb_clean_tx_ring(adapter->tx_ring[i]);
9d5c8243
AK		 3536}
3537
3538/**
b980ac18
JK		 3539 * igb_free_rx_resources - Free Rx Resources
3540 * @rx_ring: ring to clean the resources from
9d5c8243 3541 *
b980ac18 3542 * Free all receive software resources
9d5c8243 3543 **/
68fd9910 3544void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3545{
3b644cf6 3546 igb_clean_rx_ring(rx_ring);
9d5c8243 3547
06034649
AD		 3548 vfree(rx_ring->rx_buffer_info);
3549 rx_ring->rx_buffer_info = NULL;
9d5c8243 3550
439705e1
AD		 3551 /* if not set, then don't free */
3552 if (!rx_ring->desc)
3553 return;
3554
59d71989
AD		 3555 dma_free_coherent(rx_ring->dev, rx_ring->size,
3556 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 3557
3558 rx_ring->desc = NULL;
3559}
3560
3561/**
b980ac18
JK		 3562 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3563 * @adapter: board private structure
9d5c8243 3564 *
b980ac18 3565 * Free all receive software resources
9d5c8243
AK		 3566 **/
3567static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3568{
3569 int i;
3570
3571 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3572 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3573}
3574
3575/**
b980ac18
JK		 3576 * igb_clean_rx_ring - Free Rx Buffers per Queue
3577 * @rx_ring: ring to free buffers from
9d5c8243 3578 **/
3b644cf6 3579static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 3580{
9d5c8243 3581 unsigned long size;
c023cd88 3582 u16 i;
9d5c8243 3583
1a1c225b
AD		 3584 if (rx_ring->skb)
3585 dev_kfree_skb(rx_ring->skb);
3586 rx_ring->skb = NULL;
3587
06034649 3588 if (!rx_ring->rx_buffer_info)
9d5c8243 3589 return;
439705e1 3590
9d5c8243
AK		 3591 /* Free all the Rx ring sk_buffs */
3592 for (i = 0; i < rx_ring->count; i++) {
06034649 3593 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
9d5c8243 3594
cbc8e55f
AD		 3595 if (!buffer_info->page)
3596 continue;
3597
3598 dma_unmap_page(rx_ring->dev,
3599 buffer_info->dma,
3600 PAGE_SIZE,
3601 DMA_FROM_DEVICE);
3602 __free_page(buffer_info->page);
3603
1a1c225b 3604 buffer_info->page = NULL;
9d5c8243
AK		 3605 }
3606
06034649
AD		 3607 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3608 memset(rx_ring->rx_buffer_info, 0, size);
9d5c8243
AK		 3609
3610 /* Zero out the descriptor ring */
3611 memset(rx_ring->desc, 0, rx_ring->size);
3612
cbc8e55f 3613 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3614 rx_ring->next_to_clean = 0;
3615 rx_ring->next_to_use = 0;
9d5c8243
AK		 3616}
3617
3618/**
b980ac18
JK		 3619 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3620 * @adapter: board private structure
9d5c8243
AK		 3621 **/
3622static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3623{
3624 int i;
3625
3626 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3627 igb_clean_rx_ring(adapter->rx_ring[i]);
9d5c8243
AK		 3628}
3629
3630/**
b980ac18
JK		 3631 * igb_set_mac - Change the Ethernet Address of the NIC
3632 * @netdev: network interface device structure
3633 * @p: pointer to an address structure
9d5c8243 3634 *
b980ac18 3635 * Returns 0 on success, negative on failure
9d5c8243
AK		 3636 **/
3637static int igb_set_mac(struct net_device *netdev, void *p)
3638{
3639 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 3640 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3641 struct sockaddr *addr = p;
3642
3643 if (!is_valid_ether_addr(addr->sa_data))
3644 return -EADDRNOTAVAIL;
3645
3646 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 3647 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 3648
26ad9178
AD		 3649 /* set the correct pool for the new PF MAC address in entry 0 */
3650 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
b980ac18 3651 adapter->vfs_allocated_count);
e1739522 3652
9d5c8243
AK		 3653 return 0;
3654}
3655
3656/**
b980ac18
JK		 3657 * igb_write_mc_addr_list - write multicast addresses to MTA
3658 * @netdev: network interface device structure
9d5c8243 3659 *
b980ac18
JK		 3660 * Writes multicast address list to the MTA hash table.
3661 * Returns: -ENOMEM on failure
3662 * 0 on no addresses written
3663 * X on writing X addresses to MTA
9d5c8243 3664 **/
68d480c4 3665static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 3666{
3667 struct igb_adapter *adapter = netdev_priv(netdev);
3668 struct e1000_hw *hw = &adapter->hw;
22bedad3 3669 struct netdev_hw_addr *ha;
68d480c4 3670 u8 *mta_list;
9d5c8243
AK		 3671 int i;
3672
4cd24eaf 3673 if (netdev_mc_empty(netdev)) {
68d480c4
AD		 3674 /* nothing to program, so clear mc list */
3675 igb_update_mc_addr_list(hw, NULL, 0);
3676 igb_restore_vf_multicasts(adapter);
3677 return 0;
3678 }
9d5c8243 3679
4cd24eaf 3680 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
68d480c4
AD		 3681 if (!mta_list)
3682 return -ENOMEM;
ff41f8dc 3683
68d480c4 3684 /* The shared function expects a packed array of only addresses. */
48e2f183 3685 i = 0;
22bedad3
JP		 3686 netdev_for_each_mc_addr(ha, netdev)
3687 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
68d480c4 3688
68d480c4
AD		 3689 igb_update_mc_addr_list(hw, mta_list, i);
3690 kfree(mta_list);
3691
4cd24eaf 3692 return netdev_mc_count(netdev);
68d480c4
AD		 3693}
3694
3695/**
b980ac18
JK		 3696 * igb_write_uc_addr_list - write unicast addresses to RAR table
3697 * @netdev: network interface device structure
68d480c4 3698 *
b980ac18
JK		 3699 * Writes unicast address list to the RAR table.
3700 * Returns: -ENOMEM on failure/insufficient address space
3701 * 0 on no addresses written
3702 * X on writing X addresses to the RAR table
68d480c4
AD		 3703 **/
3704static int igb_write_uc_addr_list(struct net_device *netdev)
3705{
3706 struct igb_adapter *adapter = netdev_priv(netdev);
3707 struct e1000_hw *hw = &adapter->hw;
3708 unsigned int vfn = adapter->vfs_allocated_count;
3709 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3710 int count = 0;
3711
3712 /* return ENOMEM indicating insufficient memory for addresses */
32e7bfc4 3713 if (netdev_uc_count(netdev) > rar_entries)
68d480c4 3714 return -ENOMEM;
9d5c8243 3715
32e7bfc4 3716 if (!netdev_uc_empty(netdev) && rar_entries) {
ff41f8dc 3717 struct netdev_hw_addr *ha;
32e7bfc4
JP		 3718
3719 netdev_for_each_uc_addr(ha, netdev) {
ff41f8dc
AD		 3720 if (!rar_entries)
3721 break;
26ad9178 3722 igb_rar_set_qsel(adapter, ha->addr,
b980ac18
JK		 3723 rar_entries--,
3724 vfn);
68d480c4 3725 count++;
ff41f8dc
AD		 3726 }
3727 }
3728 /* write the addresses in reverse order to avoid write combining */
3729 for (; rar_entries > 0 ; rar_entries--) {
3730 wr32(E1000_RAH(rar_entries), 0);
3731 wr32(E1000_RAL(rar_entries), 0);
3732 }
3733 wrfl();
3734
68d480c4
AD		 3735 return count;
3736}
3737
3738/**
b980ac18
JK		 3739 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3740 * @netdev: network interface device structure
68d480c4 3741 *
b980ac18
JK		 3742 * The set_rx_mode entry point is called whenever the unicast or multicast
3743 * address lists or the network interface flags are updated. This routine is
3744 * responsible for configuring the hardware for proper unicast, multicast,
3745 * promiscuous mode, and all-multi behavior.
68d480c4
AD		 3746 **/
3747static void igb_set_rx_mode(struct net_device *netdev)
3748{
3749 struct igb_adapter *adapter = netdev_priv(netdev);
3750 struct e1000_hw *hw = &adapter->hw;
3751 unsigned int vfn = adapter->vfs_allocated_count;
3752 u32 rctl, vmolr = 0;
3753 int count;
3754
3755 /* Check for Promiscuous and All Multicast modes */
3756 rctl = rd32(E1000_RCTL);
3757
3758 /* clear the effected bits */
3759 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
3760
3761 if (netdev->flags & IFF_PROMISC) {
6f3dc319 3762 /* retain VLAN HW filtering if in VT mode */
7e44892c 3763 if (adapter->vfs_allocated_count)
6f3dc319 3764 rctl |= E1000_RCTL_VFE;
68d480c4
AD		 3765 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3766 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
3767 } else {
3768 if (netdev->flags & IFF_ALLMULTI) {
3769 rctl |= E1000_RCTL_MPE;
3770 vmolr |= E1000_VMOLR_MPME;
3771 } else {
b980ac18 3772 /* Write addresses to the MTA, if the attempt fails
25985edc 3773 * then we should just turn on promiscuous mode so
68d480c4
AD		 3774 * that we can at least receive multicast traffic
3775 */
3776 count = igb_write_mc_addr_list(netdev);
3777 if (count < 0) {
3778 rctl |= E1000_RCTL_MPE;
3779 vmolr |= E1000_VMOLR_MPME;
3780 } else if (count) {
3781 vmolr |= E1000_VMOLR_ROMPE;
3782 }
3783 }
b980ac18 3784 /* Write addresses to available RAR registers, if there is not
68d480c4 3785 * sufficient space to store all the addresses then enable
25985edc 3786 * unicast promiscuous mode
68d480c4
AD		 3787 */
3788 count = igb_write_uc_addr_list(netdev);
3789 if (count < 0) {
3790 rctl |= E1000_RCTL_UPE;
3791 vmolr |= E1000_VMOLR_ROPE;
3792 }
3793 rctl |= E1000_RCTL_VFE;
28fc06f5 3794 }
68d480c4 3795 wr32(E1000_RCTL, rctl);
28fc06f5 3796
b980ac18 3797 /* In order to support SR-IOV and eventually VMDq it is necessary to set
68d480c4
AD		 3798 * the VMOLR to enable the appropriate modes. Without this workaround
3799 * we will have issues with VLAN tag stripping not being done for frames
3800 * that are only arriving because we are the default pool
3801 */
f96a8a0b 3802 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
28fc06f5 3803 return;
9d5c8243 3804
68d480c4 3805 vmolr |= rd32(E1000_VMOLR(vfn)) &
b980ac18 3806 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
68d480c4 3807 wr32(E1000_VMOLR(vfn), vmolr);
28fc06f5 3808 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 3809}
3810
13800469
GR		 3811static void igb_check_wvbr(struct igb_adapter *adapter)
3812{
3813 struct e1000_hw *hw = &adapter->hw;
3814 u32 wvbr = 0;
3815
3816 switch (hw->mac.type) {
3817 case e1000_82576:
3818 case e1000_i350:
3819 if (!(wvbr = rd32(E1000_WVBR)))
3820 return;
3821 break;
3822 default:
3823 break;
3824 }
3825
3826 adapter->wvbr |= wvbr;
3827}
3828
3829#define IGB_STAGGERED_QUEUE_OFFSET 8
3830
3831static void igb_spoof_check(struct igb_adapter *adapter)
3832{
3833 int j;
3834
3835 if (!adapter->wvbr)
3836 return;
3837
3838 for(j = 0; j < adapter->vfs_allocated_count; j++) {
3839 if (adapter->wvbr & (1 << j) ||
3840 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
3841 dev_warn(&adapter->pdev->dev,
3842 "Spoof event(s) detected on VF %d\n", j);
3843 adapter->wvbr &=
3844 ~((1 << j) |
3845 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
3846 }
3847 }
3848}
3849
9d5c8243 3850/* Need to wait a few seconds after link up to get diagnostic information from
b980ac18
JK		 3851 * the phy
3852 */
9d5c8243
AK		 3853static void igb_update_phy_info(unsigned long data)
3854{
3855 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 3856 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 3857}
3858
4d6b725e 3859/**
b980ac18
JK		 3860 * igb_has_link - check shared code for link and determine up/down
3861 * @adapter: pointer to driver private info
4d6b725e 3862 **/
3145535a 3863bool igb_has_link(struct igb_adapter *adapter)
4d6b725e
AD		 3864{
3865 struct e1000_hw *hw = &adapter->hw;
3866 bool link_active = false;
4d6b725e
AD		 3867
3868 /* get_link_status is set on LSC (link status) interrupt or
3869 * rx sequence error interrupt. get_link_status will stay
3870 * false until the e1000_check_for_link establishes link
3871 * for copper adapters ONLY
3872 */
3873 switch (hw->phy.media_type) {
3874 case e1000_media_type_copper:
e5c3370f
AA		 3875 if (!hw->mac.get_link_status)
3876 return true;
4d6b725e 3877 case e1000_media_type_internal_serdes:
e5c3370f
AA		 3878 hw->mac.ops.check_for_link(hw);
3879 link_active = !hw->mac.get_link_status;
4d6b725e
AD		 3880 break;
3881 default:
3882 case e1000_media_type_unknown:
3883 break;
3884 }
3885
3886 return link_active;
3887}
3888
563988dc
SA		 3889static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
3890{
3891 bool ret = false;
3892 u32 ctrl_ext, thstat;
3893
f96a8a0b 3894 /* check for thermal sensor event on i350 copper only */
563988dc
SA		 3895 if (hw->mac.type == e1000_i350) {
3896 thstat = rd32(E1000_THSTAT);
3897 ctrl_ext = rd32(E1000_CTRL_EXT);
3898
3899 if ((hw->phy.media_type == e1000_media_type_copper) &&
5c17a203 3900 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
563988dc 3901 ret = !!(thstat & event);
563988dc
SA		 3902 }
3903
3904 return ret;
3905}
3906
9d5c8243 3907/**
b980ac18
JK		 3908 * igb_watchdog - Timer Call-back
3909 * @data: pointer to adapter cast into an unsigned long
9d5c8243
AK		 3910 **/
3911static void igb_watchdog(unsigned long data)
3912{
3913 struct igb_adapter *adapter = (struct igb_adapter *)data;
3914 /* Do the rest outside of interrupt context */
3915 schedule_work(&adapter->watchdog_task);
3916}
3917
3918static void igb_watchdog_task(struct work_struct *work)
3919{
3920 struct igb_adapter *adapter = container_of(work,
b980ac18
JK		 3921 struct igb_adapter,
3922 watchdog_task);
9d5c8243 3923 struct e1000_hw *hw = &adapter->hw;
c0ba4778 3924 struct e1000_phy_info *phy = &hw->phy;
9d5c8243 3925 struct net_device *netdev = adapter->netdev;
563988dc 3926 u32 link;
7a6ea550 3927 int i;
9d5c8243 3928
4d6b725e 3929 link = igb_has_link(adapter);
9d5c8243 3930 if (link) {
749ab2cd
YZ		 3931 /* Cancel scheduled suspend requests. */
3932 pm_runtime_resume(netdev->dev.parent);
3933
9d5c8243
AK		 3934 if (!netif_carrier_ok(netdev)) {
3935 u32 ctrl;
330a6d6a 3936 hw->mac.ops.get_speed_and_duplex(hw,
b980ac18
JK		 3937 &adapter->link_speed,
3938 &adapter->link_duplex);
9d5c8243
AK		 3939
3940 ctrl = rd32(E1000_CTRL);
527d47c1 3941 /* Links status message must follow this format */
876d2d6f
JK		 3942 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s "
3943 "Duplex, Flow Control: %s\n",
559e9c49
AD		 3944 netdev->name,
3945 adapter->link_speed,
3946 adapter->link_duplex == FULL_DUPLEX ?
876d2d6f
JK		 3947 "Full" : "Half",
3948 (ctrl & E1000_CTRL_TFCE) &&
3949 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
3950 (ctrl & E1000_CTRL_RFCE) ? "RX" :
3951 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
9d5c8243 3952
c0ba4778
KS		 3953 /* check if SmartSpeed worked */
3954 igb_check_downshift(hw);
3955 if (phy->speed_downgraded)
3956 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
3957
563988dc 3958 /* check for thermal sensor event */
876d2d6f
JK		 3959 if (igb_thermal_sensor_event(hw,
3960 E1000_THSTAT_LINK_THROTTLE)) {
3961 netdev_info(netdev, "The network adapter link "
3962 "speed was downshifted because it "
3963 "overheated\n");
7ef5ed1c 3964 }
563988dc 3965
d07f3e37 3966 /* adjust timeout factor according to speed/duplex */
9d5c8243
AK		 3967 adapter->tx_timeout_factor = 1;
3968 switch (adapter->link_speed) {
3969 case SPEED_10:
9d5c8243
AK		 3970 adapter->tx_timeout_factor = 14;
3971 break;
3972 case SPEED_100:
9d5c8243
AK		 3973 /* maybe add some timeout factor ? */
3974 break;
3975 }
3976
3977 netif_carrier_on(netdev);
9d5c8243 3978
4ae196df 3979 igb_ping_all_vfs(adapter);
17dc566c 3980 igb_check_vf_rate_limit(adapter);
4ae196df 3981
4b1a9877 3982 /* link state has changed, schedule phy info update */
9d5c8243
AK		 3983 if (!test_bit(__IGB_DOWN, &adapter->state))
3984 mod_timer(&adapter->phy_info_timer,
3985 round_jiffies(jiffies + 2 * HZ));
3986 }
3987 } else {
3988 if (netif_carrier_ok(netdev)) {
3989 adapter->link_speed = 0;
3990 adapter->link_duplex = 0;
563988dc
SA		 3991
3992 /* check for thermal sensor event */
876d2d6f
JK		 3993 if (igb_thermal_sensor_event(hw,
3994 E1000_THSTAT_PWR_DOWN)) {
3995 netdev_err(netdev, "The network adapter was "
3996 "stopped because it overheated\n");
7ef5ed1c 3997 }
563988dc 3998
527d47c1
AD		 3999 /* Links status message must follow this format */
4000 printk(KERN_INFO "igb: %s NIC Link is Down\n",
4001 netdev->name);
9d5c8243 4002 netif_carrier_off(netdev);
4b1a9877 4003
4ae196df
AD		 4004 igb_ping_all_vfs(adapter);
4005
4b1a9877 4006 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4007 if (!test_bit(__IGB_DOWN, &adapter->state))
4008 mod_timer(&adapter->phy_info_timer,
4009 round_jiffies(jiffies + 2 * HZ));
749ab2cd
YZ		 4010
4011 pm_schedule_suspend(netdev->dev.parent,
4012 MSEC_PER_SEC * 5);
9d5c8243
AK		 4013 }
4014 }
4015
12dcd86b
ED		 4016 spin_lock(&adapter->stats64_lock);
4017 igb_update_stats(adapter, &adapter->stats64);
4018 spin_unlock(&adapter->stats64_lock);
9d5c8243 4019
dbabb065 4020 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4021 struct igb_ring *tx_ring = adapter->tx_ring[i];
dbabb065 4022 if (!netif_carrier_ok(netdev)) {
9d5c8243
AK		 4023 /* We've lost link, so the controller stops DMA,
4024 * but we've got queued Tx work that's never going
4025 * to get done, so reset controller to flush Tx.
b980ac18
JK		 4026 * (Do the reset outside of interrupt context).
4027 */
dbabb065
AD		 4028 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
4029 adapter->tx_timeout_count++;
4030 schedule_work(&adapter->reset_task);
4031 /* return immediately since reset is imminent */
4032 return;
4033 }
9d5c8243 4034 }
9d5c8243 4035
dbabb065 4036 /* Force detection of hung controller every watchdog period */
6d095fa8 4037 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
dbabb065 4038 }
f7ba205e 4039
b980ac18 4040 /* Cause software interrupt to ensure Rx ring is cleaned */
7a6ea550 4041 if (adapter->msix_entries) {
047e0030 4042 u32 eics = 0;
0d1ae7f4
AD		 4043 for (i = 0; i < adapter->num_q_vectors; i++)
4044 eics |= adapter->q_vector[i]->eims_value;
7a6ea550
AD		 4045 wr32(E1000_EICS, eics);
4046 } else {
4047 wr32(E1000_ICS, E1000_ICS_RXDMT0);
4048 }
9d5c8243 4049
13800469 4050 igb_spoof_check(adapter);
fc580751 4051 igb_ptp_rx_hang(adapter);
13800469 4052
9d5c8243
AK		 4053 /* Reset the timer */
4054 if (!test_bit(__IGB_DOWN, &adapter->state))
4055 mod_timer(&adapter->watchdog_timer,
4056 round_jiffies(jiffies + 2 * HZ));
4057}
4058
4059enum latency_range {
4060 lowest_latency = 0,
4061 low_latency = 1,
4062 bulk_latency = 2,
4063 latency_invalid = 255
4064};
4065
6eb5a7f1 4066/**
b980ac18
JK		 4067 * igb_update_ring_itr - update the dynamic ITR value based on packet size
4068 * @q_vector: pointer to q_vector
6eb5a7f1 4069 *
b980ac18
JK		 4070 * Stores a new ITR value based on strictly on packet size. This
4071 * algorithm is less sophisticated than that used in igb_update_itr,
4072 * due to the difficulty of synchronizing statistics across multiple
4073 * receive rings. The divisors and thresholds used by this function
4074 * were determined based on theoretical maximum wire speed and testing
4075 * data, in order to minimize response time while increasing bulk
4076 * throughput.
4077 * This functionality is controlled by the InterruptThrottleRate module
4078 * parameter (see igb_param.c)
4079 * NOTE: This function is called only when operating in a multiqueue
4080 * receive environment.
6eb5a7f1 4081 **/
047e0030 4082static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 4083{
047e0030 4084 int new_val = q_vector->itr_val;
6eb5a7f1 4085 int avg_wire_size = 0;
047e0030 4086 struct igb_adapter *adapter = q_vector->adapter;
12dcd86b 4087 unsigned int packets;
9d5c8243 4088
6eb5a7f1
AD		 4089 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4090 * ints/sec - ITR timer value of 120 ticks.
4091 */
4092 if (adapter->link_speed != SPEED_1000) {
0ba82994 4093 new_val = IGB_4K_ITR;
6eb5a7f1 4094 goto set_itr_val;
9d5c8243 4095 }
047e0030 4096
0ba82994
AD		 4097 packets = q_vector->rx.total_packets;
4098 if (packets)
4099 avg_wire_size = q_vector->rx.total_bytes / packets;
047e0030 4100
0ba82994
AD		 4101 packets = q_vector->tx.total_packets;
4102 if (packets)
4103 avg_wire_size = max_t(u32, avg_wire_size,
4104 q_vector->tx.total_bytes / packets);
047e0030
AD		 4105
4106 /* if avg_wire_size isn't set no work was done */
4107 if (!avg_wire_size)
4108 goto clear_counts;
9d5c8243 4109
6eb5a7f1
AD		 4110 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4111 avg_wire_size += 24;
4112
4113 /* Don't starve jumbo frames */
4114 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 4115
6eb5a7f1
AD		 4116 /* Give a little boost to mid-size frames */
4117 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4118 new_val = avg_wire_size / 3;
4119 else
4120 new_val = avg_wire_size / 2;
9d5c8243 4121
0ba82994
AD		 4122 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4123 if (new_val < IGB_20K_ITR &&
4124 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4125 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4126 new_val = IGB_20K_ITR;
abe1c363 4127
6eb5a7f1 4128set_itr_val:
047e0030
AD		 4129 if (new_val != q_vector->itr_val) {
4130 q_vector->itr_val = new_val;
4131 q_vector->set_itr = 1;
9d5c8243 4132 }
6eb5a7f1 4133clear_counts:
0ba82994
AD		 4134 q_vector->rx.total_bytes = 0;
4135 q_vector->rx.total_packets = 0;
4136 q_vector->tx.total_bytes = 0;
4137 q_vector->tx.total_packets = 0;
9d5c8243
AK		 4138}
4139
4140/**
b980ac18
JK		 4141 * igb_update_itr - update the dynamic ITR value based on statistics
4142 * @q_vector: pointer to q_vector
4143 * @ring_container: ring info to update the itr for
4144 *
4145 * Stores a new ITR value based on packets and byte
4146 * counts during the last interrupt. The advantage of per interrupt
4147 * computation is faster updates and more accurate ITR for the current
4148 * traffic pattern. Constants in this function were computed
4149 * based on theoretical maximum wire speed and thresholds were set based
4150 * on testing data as well as attempting to minimize response time
4151 * while increasing bulk throughput.
4152 * this functionality is controlled by the InterruptThrottleRate module
4153 * parameter (see igb_param.c)
4154 * NOTE: These calculations are only valid when operating in a single-
4155 * queue environment.
9d5c8243 4156 **/
0ba82994
AD		 4157static void igb_update_itr(struct igb_q_vector *q_vector,
4158 struct igb_ring_container *ring_container)
9d5c8243 4159{
0ba82994
AD		 4160 unsigned int packets = ring_container->total_packets;
4161 unsigned int bytes = ring_container->total_bytes;
4162 u8 itrval = ring_container->itr;
9d5c8243 4163
0ba82994 4164 /* no packets, exit with status unchanged */
9d5c8243 4165 if (packets == 0)
0ba82994 4166 return;
9d5c8243 4167
0ba82994 4168 switch (itrval) {
9d5c8243
AK		 4169 case lowest_latency:
4170 /* handle TSO and jumbo frames */
4171 if (bytes/packets > 8000)
0ba82994 4172 itrval = bulk_latency;
9d5c8243 4173 else if ((packets < 5) && (bytes > 512))
0ba82994 4174 itrval = low_latency;
9d5c8243
AK		 4175 break;
4176 case low_latency: /* 50 usec aka 20000 ints/s */
4177 if (bytes > 10000) {
4178 /* this if handles the TSO accounting */
4179 if (bytes/packets > 8000) {
0ba82994 4180 itrval = bulk_latency;
9d5c8243 4181 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
0ba82994 4182 itrval = bulk_latency;
9d5c8243 4183 } else if ((packets > 35)) {
0ba82994 4184 itrval = lowest_latency;
9d5c8243
AK		 4185 }
4186 } else if (bytes/packets > 2000) {
0ba82994 4187 itrval = bulk_latency;
9d5c8243 4188 } else if (packets <= 2 && bytes < 512) {
0ba82994 4189 itrval = lowest_latency;
9d5c8243
AK		 4190 }
4191 break;
4192 case bulk_latency: /* 250 usec aka 4000 ints/s */
4193 if (bytes > 25000) {
4194 if (packets > 35)
0ba82994 4195 itrval = low_latency;
1e5c3d21 4196 } else if (bytes < 1500) {
0ba82994 4197 itrval = low_latency;
9d5c8243
AK		 4198 }
4199 break;
4200 }
4201
0ba82994
AD		 4202 /* clear work counters since we have the values we need */
4203 ring_container->total_bytes = 0;
4204 ring_container->total_packets = 0;
4205
4206 /* write updated itr to ring container */
4207 ring_container->itr = itrval;
9d5c8243
AK		 4208}
4209
0ba82994 4210static void igb_set_itr(struct igb_q_vector *q_vector)
9d5c8243 4211{
0ba82994 4212 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4213 u32 new_itr = q_vector->itr_val;
0ba82994 4214 u8 current_itr = 0;
9d5c8243
AK		 4215
4216 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4217 if (adapter->link_speed != SPEED_1000) {
4218 current_itr = 0;
0ba82994 4219 new_itr = IGB_4K_ITR;
9d5c8243
AK		 4220 goto set_itr_now;
4221 }
4222
0ba82994
AD		 4223 igb_update_itr(q_vector, &q_vector->tx);
4224 igb_update_itr(q_vector, &q_vector->rx);
9d5c8243 4225
0ba82994 4226 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
9d5c8243 4227
6eb5a7f1 4228 /* conservative mode (itr 3) eliminates the lowest_latency setting */
0ba82994
AD		 4229 if (current_itr == lowest_latency &&
4230 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4231 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
6eb5a7f1
AD		 4232 current_itr = low_latency;
4233
9d5c8243
AK		 4234 switch (current_itr) {
4235 /* counts and packets in update_itr are dependent on these numbers */
4236 case lowest_latency:
0ba82994 4237 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
9d5c8243
AK		 4238 break;
4239 case low_latency:
0ba82994 4240 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
9d5c8243
AK		 4241 break;
4242 case bulk_latency:
0ba82994 4243 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
9d5c8243
AK		 4244 break;
4245 default:
4246 break;
4247 }
4248
4249set_itr_now:
047e0030 4250 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 4251 /* this attempts to bias the interrupt rate towards Bulk
4252 * by adding intermediate steps when interrupt rate is
b980ac18
JK		 4253 * increasing
4254 */
047e0030 4255 new_itr = new_itr > q_vector->itr_val ?
b980ac18
JK		 4256 max((new_itr * q_vector->itr_val) /
4257 (new_itr + (q_vector->itr_val >> 2)),
4258 new_itr) : new_itr;
9d5c8243
AK		 4259 /* Don't write the value here; it resets the adapter's
4260 * internal timer, and causes us to delay far longer than
4261 * we should between interrupts. Instead, we write the ITR
4262 * value at the beginning of the next interrupt so the timing
4263 * ends up being correct.
4264 */
047e0030
AD		 4265 q_vector->itr_val = new_itr;
4266 q_vector->set_itr = 1;
9d5c8243 4267 }
9d5c8243
AK		 4268}
4269
c50b52a0
SH		 4270static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4271 u32 type_tucmd, u32 mss_l4len_idx)
7d13a7d0
AD		 4272{
4273 struct e1000_adv_tx_context_desc *context_desc;
4274 u16 i = tx_ring->next_to_use;
4275
4276 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4277
4278 i++;
4279 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4280
4281 /* set bits to identify this as an advanced context descriptor */
4282 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4283
4284 /* For 82575, context index must be unique per ring. */
866cff06 4285 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
7d13a7d0
AD		 4286 mss_l4len_idx |= tx_ring->reg_idx << 4;
4287
4288 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4289 context_desc->seqnum_seed = 0;
4290 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4291 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4292}
4293
7af40ad9
AD		 4294static int igb_tso(struct igb_ring *tx_ring,
4295 struct igb_tx_buffer *first,
4296 u8 *hdr_len)
9d5c8243 4297{
7af40ad9 4298 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4299 u32 vlan_macip_lens, type_tucmd;
4300 u32 mss_l4len_idx, l4len;
4301
ed6aa105
AD		 4302 if (skb->ip_summed != CHECKSUM_PARTIAL)
4303 return 0;
4304
7d13a7d0
AD		 4305 if (!skb_is_gso(skb))
4306 return 0;
9d5c8243
AK		 4307
4308 if (skb_header_cloned(skb)) {
7af40ad9 4309 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
9d5c8243
AK		 4310 if (err)
4311 return err;
4312 }
4313
7d13a7d0
AD		 4314 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4315 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
9d5c8243 4316
7af40ad9 4317 if (first->protocol == __constant_htons(ETH_P_IP)) {
9d5c8243
AK		 4318 struct iphdr *iph = ip_hdr(skb);
4319 iph->tot_len = 0;
4320 iph->check = 0;
4321 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4322 iph->daddr, 0,
4323 IPPROTO_TCP,
4324 0);
7d13a7d0 4325 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
7af40ad9
AD		 4326 first->tx_flags |= IGB_TX_FLAGS_TSO |
4327 IGB_TX_FLAGS_CSUM |
4328 IGB_TX_FLAGS_IPV4;
8e1e8a47 4329 } else if (skb_is_gso_v6(skb)) {
9d5c8243
AK		 4330 ipv6_hdr(skb)->payload_len = 0;
4331 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4332 &ipv6_hdr(skb)->daddr,
4333 0, IPPROTO_TCP, 0);
7af40ad9
AD		 4334 first->tx_flags |= IGB_TX_FLAGS_TSO |
4335 IGB_TX_FLAGS_CSUM;
9d5c8243
AK		 4336 }
4337
7af40ad9 4338 /* compute header lengths */
7d13a7d0
AD		 4339 l4len = tcp_hdrlen(skb);
4340 *hdr_len = skb_transport_offset(skb) + l4len;
9d5c8243 4341
7af40ad9
AD		 4342 /* update gso size and bytecount with header size */
4343 first->gso_segs = skb_shinfo(skb)->gso_segs;
4344 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4345
9d5c8243 4346 /* MSS L4LEN IDX */
7d13a7d0
AD		 4347 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4348 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
9d5c8243 4349
7d13a7d0
AD		 4350 /* VLAN MACLEN IPLEN */
4351 vlan_macip_lens = skb_network_header_len(skb);
4352 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4353 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4354
7d13a7d0 4355 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243 4356
7d13a7d0 4357 return 1;
9d5c8243
AK		 4358}
4359
7af40ad9 4360static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
9d5c8243 4361{
7af40ad9 4362 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4363 u32 vlan_macip_lens = 0;
4364 u32 mss_l4len_idx = 0;
4365 u32 type_tucmd = 0;
9d5c8243 4366
7d13a7d0 4367 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7af40ad9
AD		 4368 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4369 return;
7d13a7d0
AD		 4370 } else {
4371 u8 l4_hdr = 0;
7af40ad9 4372 switch (first->protocol) {
7d13a7d0
AD		 4373 case __constant_htons(ETH_P_IP):
4374 vlan_macip_lens |= skb_network_header_len(skb);
4375 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4376 l4_hdr = ip_hdr(skb)->protocol;
4377 break;
4378 case __constant_htons(ETH_P_IPV6):
4379 vlan_macip_lens |= skb_network_header_len(skb);
4380 l4_hdr = ipv6_hdr(skb)->nexthdr;
4381 break;
4382 default:
4383 if (unlikely(net_ratelimit())) {
4384 dev_warn(tx_ring->dev,
b980ac18
JK		 4385 "partial checksum but proto=%x!\n",
4386 first->protocol);
fa4a7ef3 4387 }
7d13a7d0
AD		 4388 break;
4389 }
fa4a7ef3 4390
7d13a7d0
AD		 4391 switch (l4_hdr) {
4392 case IPPROTO_TCP:
4393 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4394 mss_l4len_idx = tcp_hdrlen(skb) <<
4395 E1000_ADVTXD_L4LEN_SHIFT;
4396 break;
4397 case IPPROTO_SCTP:
4398 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4399 mss_l4len_idx = sizeof(struct sctphdr) <<
4400 E1000_ADVTXD_L4LEN_SHIFT;
4401 break;
4402 case IPPROTO_UDP:
4403 mss_l4len_idx = sizeof(struct udphdr) <<
4404 E1000_ADVTXD_L4LEN_SHIFT;
4405 break;
4406 default:
4407 if (unlikely(net_ratelimit())) {
4408 dev_warn(tx_ring->dev,
b980ac18
JK		 4409 "partial checksum but l4 proto=%x!\n",
4410 l4_hdr);
44b0cda3 4411 }
7d13a7d0 4412 break;
9d5c8243 4413 }
7af40ad9
AD		 4414
4415 /* update TX checksum flag */
4416 first->tx_flags |= IGB_TX_FLAGS_CSUM;
7d13a7d0 4417 }
9d5c8243 4418
7d13a7d0 4419 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4420 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4421
7d13a7d0 4422 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243
AK		 4423}
4424
1d9daf45
AD		 4425#define IGB_SET_FLAG(_input, _flag, _result) \
4426 ((_flag <= _result) ? \
4427 ((u32)(_input & _flag) * (_result / _flag)) : \
4428 ((u32)(_input & _flag) / (_flag / _result)))
4429
4430static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
e032afc8
AD		 4431{
4432 /* set type for advanced descriptor with frame checksum insertion */
1d9daf45
AD		 4433 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4434 E1000_ADVTXD_DCMD_DEXT |
4435 E1000_ADVTXD_DCMD_IFCS;
e032afc8
AD		 4436
4437 /* set HW vlan bit if vlan is present */
1d9daf45
AD		 4438 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4439 (E1000_ADVTXD_DCMD_VLE));
4440
4441 /* set segmentation bits for TSO */
4442 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4443 (E1000_ADVTXD_DCMD_TSE));
e032afc8
AD		 4444
4445 /* set timestamp bit if present */
1d9daf45
AD		 4446 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4447 (E1000_ADVTXD_MAC_TSTAMP));
e032afc8 4448
1d9daf45
AD		 4449 /* insert frame checksum */
4450 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
e032afc8
AD		 4451
4452 return cmd_type;
4453}
4454
7af40ad9
AD		 4455static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4456 union e1000_adv_tx_desc *tx_desc,
4457 u32 tx_flags, unsigned int paylen)
e032afc8
AD		 4458{
4459 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4460
1d9daf45
AD		 4461 /* 82575 requires a unique index per ring */
4462 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
e032afc8
AD		 4463 olinfo_status |= tx_ring->reg_idx << 4;
4464
4465 /* insert L4 checksum */
1d9daf45
AD		 4466 olinfo_status |= IGB_SET_FLAG(tx_flags,
4467 IGB_TX_FLAGS_CSUM,
4468 (E1000_TXD_POPTS_TXSM << 8));
e032afc8 4469
1d9daf45
AD		 4470 /* insert IPv4 checksum */
4471 olinfo_status |= IGB_SET_FLAG(tx_flags,
4472 IGB_TX_FLAGS_IPV4,
4473 (E1000_TXD_POPTS_IXSM << 8));
e032afc8 4474
7af40ad9 4475 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
e032afc8
AD		 4476}
4477
7af40ad9
AD		 4478static void igb_tx_map(struct igb_ring *tx_ring,
4479 struct igb_tx_buffer *first,
ebe42d16 4480 const u8 hdr_len)
9d5c8243 4481{
7af40ad9 4482 struct sk_buff *skb = first->skb;
c9f14bf3 4483 struct igb_tx_buffer *tx_buffer;
ebe42d16 4484 union e1000_adv_tx_desc *tx_desc;
80d0759e 4485 struct skb_frag_struct *frag;
ebe42d16 4486 dma_addr_t dma;
80d0759e 4487 unsigned int data_len, size;
7af40ad9 4488 u32 tx_flags = first->tx_flags;
1d9daf45 4489 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
ebe42d16 4490 u16 i = tx_ring->next_to_use;
ebe42d16
AD		 4491
4492 tx_desc = IGB_TX_DESC(tx_ring, i);
4493
80d0759e
AD		 4494 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4495
4496 size = skb_headlen(skb);
4497 data_len = skb->data_len;
ebe42d16
AD		 4498
4499 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
9d5c8243 4500
80d0759e
AD		 4501 tx_buffer = first;
4502
4503 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4504 if (dma_mapping_error(tx_ring->dev, dma))
4505 goto dma_error;
4506
4507 /* record length, and DMA address */
4508 dma_unmap_len_set(tx_buffer, len, size);
4509 dma_unmap_addr_set(tx_buffer, dma, dma);
4510
4511 tx_desc->read.buffer_addr = cpu_to_le64(dma);
ebe42d16 4512
ebe42d16
AD		 4513 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4514 tx_desc->read.cmd_type_len =
1d9daf45 4515 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
ebe42d16
AD		 4516
4517 i++;
4518 tx_desc++;
4519 if (i == tx_ring->count) {
4520 tx_desc = IGB_TX_DESC(tx_ring, 0);
4521 i = 0;
4522 }
80d0759e 4523 tx_desc->read.olinfo_status = 0;
ebe42d16
AD		 4524
4525 dma += IGB_MAX_DATA_PER_TXD;
4526 size -= IGB_MAX_DATA_PER_TXD;
4527
ebe42d16
AD		 4528 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4529 }
4530
4531 if (likely(!data_len))
4532 break;
2bbfebe2 4533
1d9daf45 4534 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9d5c8243 4535
65689fef 4536 i++;
ebe42d16
AD		 4537 tx_desc++;
4538 if (i == tx_ring->count) {
4539 tx_desc = IGB_TX_DESC(tx_ring, 0);
65689fef 4540 i = 0;
ebe42d16 4541 }
80d0759e 4542 tx_desc->read.olinfo_status = 0;
65689fef 4543
9e903e08 4544 size = skb_frag_size(frag);
ebe42d16
AD		 4545 data_len -= size;
4546
4547 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
80d0759e 4548 size, DMA_TO_DEVICE);
6366ad33 4549
c9f14bf3 4550 tx_buffer = &tx_ring->tx_buffer_info[i];
9d5c8243
AK		 4551 }
4552
ebe42d16 4553 /* write last descriptor with RS and EOP bits */
1d9daf45
AD		 4554 cmd_type |= size | IGB_TXD_DCMD;
4555 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8542db05 4556
80d0759e
AD		 4557 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4558
8542db05
AD		 4559 /* set the timestamp */
4560 first->time_stamp = jiffies;
4561
b980ac18 4562 /* Force memory writes to complete before letting h/w know there
ebe42d16
AD		 4563 * are new descriptors to fetch. (Only applicable for weak-ordered
4564 * memory model archs, such as IA-64).
4565 *
4566 * We also need this memory barrier to make certain all of the
4567 * status bits have been updated before next_to_watch is written.
4568 */
4569 wmb();
4570
8542db05 4571 /* set next_to_watch value indicating a packet is present */
ebe42d16 4572 first->next_to_watch = tx_desc;
9d5c8243 4573
ebe42d16
AD		 4574 i++;
4575 if (i == tx_ring->count)
4576 i = 0;
6366ad33 4577
ebe42d16 4578 tx_ring->next_to_use = i;
6366ad33 4579
ebe42d16 4580 writel(i, tx_ring->tail);
6366ad33 4581
ebe42d16 4582 /* we need this if more than one processor can write to our tail
b980ac18
JK		 4583 * at a time, it synchronizes IO on IA64/Altix systems
4584 */
ebe42d16
AD		 4585 mmiowb();
4586
4587 return;
4588
4589dma_error:
4590 dev_err(tx_ring->dev, "TX DMA map failed\n");
4591
4592 /* clear dma mappings for failed tx_buffer_info map */
4593 for (;;) {
c9f14bf3
AD		 4594 tx_buffer = &tx_ring->tx_buffer_info[i];
4595 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4596 if (tx_buffer == first)
ebe42d16 4597 break;
a77ff709
NN		 4598 if (i == 0)
4599 i = tx_ring->count;
6366ad33 4600 i--;
6366ad33
AD		 4601 }
4602
9d5c8243 4603 tx_ring->next_to_use = i;
9d5c8243
AK		 4604}
4605
6ad4edfc 4606static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4607{
e694e964
AD		 4608 struct net_device *netdev = tx_ring->netdev;
4609
661086df 4610 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 4611
9d5c8243
AK		 4612 /* Herbert's original patch had:
4613 * smp_mb__after_netif_stop_queue();
b980ac18
JK		 4614 * but since that doesn't exist yet, just open code it.
4615 */
9d5c8243
AK		 4616 smp_mb();
4617
4618 /* We need to check again in a case another CPU has just
b980ac18
JK		 4619 * made room available.
4620 */
c493ea45 4621 if (igb_desc_unused(tx_ring) < size)
9d5c8243
AK		 4622 return -EBUSY;
4623
4624 /* A reprieve! */
661086df 4625 netif_wake_subqueue(netdev, tx_ring->queue_index);
12dcd86b
ED		 4626
4627 u64_stats_update_begin(&tx_ring->tx_syncp2);
4628 tx_ring->tx_stats.restart_queue2++;
4629 u64_stats_update_end(&tx_ring->tx_syncp2);
4630
9d5c8243
AK		 4631 return 0;
4632}
4633
6ad4edfc 4634static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4635{
c493ea45 4636 if (igb_desc_unused(tx_ring) >= size)
9d5c8243 4637 return 0;
e694e964 4638 return __igb_maybe_stop_tx(tx_ring, size);
9d5c8243
AK		 4639}
4640
cd392f5c
AD		 4641netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4642 struct igb_ring *tx_ring)
9d5c8243 4643{
8542db05 4644 struct igb_tx_buffer *first;
ebe42d16 4645 int tso;
91d4ee33 4646 u32 tx_flags = 0;
21ba6fe1 4647 u16 count = TXD_USE_COUNT(skb_headlen(skb));
31f6adbb 4648 __be16 protocol = vlan_get_protocol(skb);
91d4ee33 4649 u8 hdr_len = 0;
9d5c8243 4650
21ba6fe1
AD		 4651 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
4652 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
9d5c8243 4653 * + 2 desc gap to keep tail from touching head,
9d5c8243 4654 * + 1 desc for context descriptor,
21ba6fe1
AD		 4655 * otherwise try next time
4656 */
4657 if (NETDEV_FRAG_PAGE_MAX_SIZE > IGB_MAX_DATA_PER_TXD) {
4658 unsigned short f;
4659 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
4660 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
4661 } else {
4662 count += skb_shinfo(skb)->nr_frags;
4663 }
4664
4665 if (igb_maybe_stop_tx(tx_ring, count + 3)) {
9d5c8243 4666 /* this is a hard error */
9d5c8243
AK		 4667 return NETDEV_TX_BUSY;
4668 }
33af6bcc 4669
7af40ad9
AD		 4670 /* record the location of the first descriptor for this packet */
4671 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
4672 first->skb = skb;
4673 first->bytecount = skb->len;
4674 first->gso_segs = 1;
4675
b66e2397
MV		 4676 skb_tx_timestamp(skb);
4677
b646c22e
AD		 4678 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
4679 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
1f6e8178 4680
b646c22e
AD		 4681 if (!(adapter->ptp_tx_skb)) {
4682 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4683 tx_flags |= IGB_TX_FLAGS_TSTAMP;
4684
4685 adapter->ptp_tx_skb = skb_get(skb);
4686 adapter->ptp_tx_start = jiffies;
4687 if (adapter->hw.mac.type == e1000_82576)
4688 schedule_work(&adapter->ptp_tx_work);
4689 }
33af6bcc 4690 }
9d5c8243 4691
eab6d18d 4692 if (vlan_tx_tag_present(skb)) {
9d5c8243
AK		 4693 tx_flags |= IGB_TX_FLAGS_VLAN;
4694 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
4695 }
4696
7af40ad9
AD		 4697 /* record initial flags and protocol */
4698 first->tx_flags = tx_flags;
4699 first->protocol = protocol;
cdfd01fc 4700
7af40ad9
AD		 4701 tso = igb_tso(tx_ring, first, &hdr_len);
4702 if (tso < 0)
7d13a7d0 4703 goto out_drop;
7af40ad9
AD		 4704 else if (!tso)
4705 igb_tx_csum(tx_ring, first);
9d5c8243 4706
7af40ad9 4707 igb_tx_map(tx_ring, first, hdr_len);
85ad76b2
AD		 4708
4709 /* Make sure there is space in the ring for the next send. */
21ba6fe1 4710 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
85ad76b2 4711
9d5c8243 4712 return NETDEV_TX_OK;
7d13a7d0
AD		 4713
4714out_drop:
7af40ad9
AD		 4715 igb_unmap_and_free_tx_resource(tx_ring, first);
4716
7d13a7d0 4717 return NETDEV_TX_OK;
9d5c8243
AK		 4718}
4719
1cc3bd87
AD		 4720static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
4721 struct sk_buff *skb)
4722{
4723 unsigned int r_idx = skb->queue_mapping;
4724
4725 if (r_idx >= adapter->num_tx_queues)
4726 r_idx = r_idx % adapter->num_tx_queues;
4727
4728 return adapter->tx_ring[r_idx];
4729}
4730
cd392f5c
AD		 4731static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
4732 struct net_device *netdev)
9d5c8243
AK		 4733{
4734 struct igb_adapter *adapter = netdev_priv(netdev);
b1a436c3
AD		 4735
4736 if (test_bit(__IGB_DOWN, &adapter->state)) {
4737 dev_kfree_skb_any(skb);
4738 return NETDEV_TX_OK;
4739 }
4740
4741 if (skb->len <= 0) {
4742 dev_kfree_skb_any(skb);
4743 return NETDEV_TX_OK;
4744 }
4745
b980ac18 4746 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
1cc3bd87
AD		 4747 * in order to meet this minimum size requirement.
4748 */
ea5ceeab
TD		 4749 if (unlikely(skb->len < 17)) {
4750 if (skb_pad(skb, 17 - skb->len))
1cc3bd87
AD		 4751 return NETDEV_TX_OK;
4752 skb->len = 17;
ea5ceeab 4753 skb_set_tail_pointer(skb, 17);
1cc3bd87 4754 }
9d5c8243 4755
1cc3bd87 4756 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
9d5c8243
AK		 4757}
4758
4759/**
b980ac18
JK		 4760 * igb_tx_timeout - Respond to a Tx Hang
4761 * @netdev: network interface device structure
9d5c8243
AK		 4762 **/
4763static void igb_tx_timeout(struct net_device *netdev)
4764{
4765 struct igb_adapter *adapter = netdev_priv(netdev);
4766 struct e1000_hw *hw = &adapter->hw;
4767
4768 /* Do the reset outside of interrupt context */
4769 adapter->tx_timeout_count++;
f7ba205e 4770
06218a8d 4771 if (hw->mac.type >= e1000_82580)
55cac248
AD		 4772 hw->dev_spec._82575.global_device_reset = true;
4773
9d5c8243 4774 schedule_work(&adapter->reset_task);
265de409
AD		 4775 wr32(E1000_EICS,
4776 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 4777}
4778
4779static void igb_reset_task(struct work_struct *work)
4780{
4781 struct igb_adapter *adapter;
4782 adapter = container_of(work, struct igb_adapter, reset_task);
4783
c97ec42a
TI		 4784 igb_dump(adapter);
4785 netdev_err(adapter->netdev, "Reset adapter\n");
9d5c8243
AK		 4786 igb_reinit_locked(adapter);
4787}
4788
4789/**
b980ac18
JK		 4790 * igb_get_stats64 - Get System Network Statistics
4791 * @netdev: network interface device structure
4792 * @stats: rtnl_link_stats64 pointer
9d5c8243 4793 **/
12dcd86b 4794static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
b980ac18 4795 struct rtnl_link_stats64 *stats)
9d5c8243 4796{
12dcd86b
ED		 4797 struct igb_adapter *adapter = netdev_priv(netdev);
4798
4799 spin_lock(&adapter->stats64_lock);
4800 igb_update_stats(adapter, &adapter->stats64);
4801 memcpy(stats, &adapter->stats64, sizeof(*stats));
4802 spin_unlock(&adapter->stats64_lock);
4803
4804 return stats;
9d5c8243
AK		 4805}
4806
4807/**
b980ac18
JK		 4808 * igb_change_mtu - Change the Maximum Transfer Unit
4809 * @netdev: network interface device structure
4810 * @new_mtu: new value for maximum frame size
9d5c8243 4811 *
b980ac18 4812 * Returns 0 on success, negative on failure
9d5c8243
AK		 4813 **/
4814static int igb_change_mtu(struct net_device *netdev, int new_mtu)
4815{
4816 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 4817 struct pci_dev *pdev = adapter->pdev;
153285f9 4818 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
9d5c8243 4819
c809d227 4820 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
090b1795 4821 dev_err(&pdev->dev, "Invalid MTU setting\n");
9d5c8243
AK		 4822 return -EINVAL;
4823 }
4824
153285f9 4825#define MAX_STD_JUMBO_FRAME_SIZE 9238
9d5c8243 4826 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
090b1795 4827 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
9d5c8243
AK		 4828 return -EINVAL;
4829 }
4830
2ccd994c
AD		 4831 /* adjust max frame to be at least the size of a standard frame */
4832 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
4833 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
4834
9d5c8243
AK		 4835 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
4836 msleep(1);
73cd78f1 4837
9d5c8243
AK		 4838 /* igb_down has a dependency on max_frame_size */
4839 adapter->max_frame_size = max_frame;
559e9c49 4840
4c844851
AD		 4841 if (netif_running(netdev))
4842 igb_down(adapter);
9d5c8243 4843
090b1795 4844 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
9d5c8243
AK		 4845 netdev->mtu, new_mtu);
4846 netdev->mtu = new_mtu;
4847
4848 if (netif_running(netdev))
4849 igb_up(adapter);
4850 else
4851 igb_reset(adapter);
4852
4853 clear_bit(__IGB_RESETTING, &adapter->state);
4854
4855 return 0;
4856}
4857
4858/**
b980ac18
JK		 4859 * igb_update_stats - Update the board statistics counters
4860 * @adapter: board private structure
9d5c8243 4861 **/
12dcd86b
ED		 4862void igb_update_stats(struct igb_adapter *adapter,
4863 struct rtnl_link_stats64 *net_stats)
9d5c8243
AK		 4864{
4865 struct e1000_hw *hw = &adapter->hw;
4866 struct pci_dev *pdev = adapter->pdev;
fa3d9a6d 4867 u32 reg, mpc;
9d5c8243 4868 u16 phy_tmp;
3f9c0164
AD		 4869 int i;
4870 u64 bytes, packets;
12dcd86b
ED		 4871 unsigned int start;
4872 u64 _bytes, _packets;
9d5c8243
AK		 4873
4874#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
4875
b980ac18 4876 /* Prevent stats update while adapter is being reset, or if the pci
9d5c8243
AK		 4877 * connection is down.
4878 */
4879 if (adapter->link_speed == 0)
4880 return;
4881 if (pci_channel_offline(pdev))
4882 return;
4883
3f9c0164
AD		 4884 bytes = 0;
4885 packets = 0;
7f90128e
AA		 4886
4887 rcu_read_lock();
3f9c0164 4888 for (i = 0; i < adapter->num_rx_queues; i++) {
ae1c07a6 4889 u32 rqdpc = rd32(E1000_RQDPC(i));
3025a446 4890 struct igb_ring *ring = adapter->rx_ring[i];
12dcd86b 4891
ae1c07a6
AD		 4892 if (rqdpc) {
4893 ring->rx_stats.drops += rqdpc;
4894 net_stats->rx_fifo_errors += rqdpc;
4895 }
12dcd86b
ED		 4896
4897 do {
4898 start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
4899 _bytes = ring->rx_stats.bytes;
4900 _packets = ring->rx_stats.packets;
4901 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
4902 bytes += _bytes;
4903 packets += _packets;
3f9c0164
AD		 4904 }
4905
128e45eb
AD		 4906 net_stats->rx_bytes = bytes;
4907 net_stats->rx_packets = packets;
3f9c0164
AD		 4908
4909 bytes = 0;
4910 packets = 0;
4911 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4912 struct igb_ring *ring = adapter->tx_ring[i];
12dcd86b
ED		 4913 do {
4914 start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
4915 _bytes = ring->tx_stats.bytes;
4916 _packets = ring->tx_stats.packets;
4917 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
4918 bytes += _bytes;
4919 packets += _packets;
3f9c0164 4920 }
128e45eb
AD		 4921 net_stats->tx_bytes = bytes;
4922 net_stats->tx_packets = packets;
7f90128e 4923 rcu_read_unlock();
3f9c0164
AD		 4924
4925 /* read stats registers */
9d5c8243
AK		 4926 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
4927 adapter->stats.gprc += rd32(E1000_GPRC);
4928 adapter->stats.gorc += rd32(E1000_GORCL);
4929 rd32(E1000_GORCH); /* clear GORCL */
4930 adapter->stats.bprc += rd32(E1000_BPRC);
4931 adapter->stats.mprc += rd32(E1000_MPRC);
4932 adapter->stats.roc += rd32(E1000_ROC);
4933
4934 adapter->stats.prc64 += rd32(E1000_PRC64);
4935 adapter->stats.prc127 += rd32(E1000_PRC127);
4936 adapter->stats.prc255 += rd32(E1000_PRC255);
4937 adapter->stats.prc511 += rd32(E1000_PRC511);
4938 adapter->stats.prc1023 += rd32(E1000_PRC1023);
4939 adapter->stats.prc1522 += rd32(E1000_PRC1522);
4940 adapter->stats.symerrs += rd32(E1000_SYMERRS);
4941 adapter->stats.sec += rd32(E1000_SEC);
4942
fa3d9a6d
MW		 4943 mpc = rd32(E1000_MPC);
4944 adapter->stats.mpc += mpc;
4945 net_stats->rx_fifo_errors += mpc;
9d5c8243
AK		 4946 adapter->stats.scc += rd32(E1000_SCC);
4947 adapter->stats.ecol += rd32(E1000_ECOL);
4948 adapter->stats.mcc += rd32(E1000_MCC);
4949 adapter->stats.latecol += rd32(E1000_LATECOL);
4950 adapter->stats.dc += rd32(E1000_DC);
4951 adapter->stats.rlec += rd32(E1000_RLEC);
4952 adapter->stats.xonrxc += rd32(E1000_XONRXC);
4953 adapter->stats.xontxc += rd32(E1000_XONTXC);
4954 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
4955 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
4956 adapter->stats.fcruc += rd32(E1000_FCRUC);
4957 adapter->stats.gptc += rd32(E1000_GPTC);
4958 adapter->stats.gotc += rd32(E1000_GOTCL);
4959 rd32(E1000_GOTCH); /* clear GOTCL */
fa3d9a6d 4960 adapter->stats.rnbc += rd32(E1000_RNBC);
9d5c8243
AK		 4961 adapter->stats.ruc += rd32(E1000_RUC);
4962 adapter->stats.rfc += rd32(E1000_RFC);
4963 adapter->stats.rjc += rd32(E1000_RJC);
4964 adapter->stats.tor += rd32(E1000_TORH);
4965 adapter->stats.tot += rd32(E1000_TOTH);
4966 adapter->stats.tpr += rd32(E1000_TPR);
4967
4968 adapter->stats.ptc64 += rd32(E1000_PTC64);
4969 adapter->stats.ptc127 += rd32(E1000_PTC127);
4970 adapter->stats.ptc255 += rd32(E1000_PTC255);
4971 adapter->stats.ptc511 += rd32(E1000_PTC511);
4972 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
4973 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
4974
4975 adapter->stats.mptc += rd32(E1000_MPTC);
4976 adapter->stats.bptc += rd32(E1000_BPTC);
4977
2d0b0f69
NN		 4978 adapter->stats.tpt += rd32(E1000_TPT);
4979 adapter->stats.colc += rd32(E1000_COLC);
9d5c8243
AK		 4980
4981 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
43915c7c
NN		 4982 /* read internal phy specific stats */
4983 reg = rd32(E1000_CTRL_EXT);
4984 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
4985 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3dbdf969
CW		 4986
4987 /* this stat has invalid values on i210/i211 */
4988 if ((hw->mac.type != e1000_i210) &&
4989 (hw->mac.type != e1000_i211))
4990 adapter->stats.tncrs += rd32(E1000_TNCRS);
43915c7c
NN		 4991 }
4992
9d5c8243
AK		 4993 adapter->stats.tsctc += rd32(E1000_TSCTC);
4994 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
4995
4996 adapter->stats.iac += rd32(E1000_IAC);
4997 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
4998 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
4999 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
5000 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
5001 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
5002 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
5003 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
5004 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
5005
5006 /* Fill out the OS statistics structure */
128e45eb
AD		 5007 net_stats->multicast = adapter->stats.mprc;
5008 net_stats->collisions = adapter->stats.colc;
9d5c8243
AK		 5009
5010 /* Rx Errors */
5011
5012 /* RLEC on some newer hardware can be incorrect so build
b980ac18
JK		 5013 * our own version based on RUC and ROC
5014 */
128e45eb 5015 net_stats->rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 5016 adapter->stats.crcerrs + adapter->stats.algnerrc +
5017 adapter->stats.ruc + adapter->stats.roc +
5018 adapter->stats.cexterr;
128e45eb
AD		 5019 net_stats->rx_length_errors = adapter->stats.ruc +
5020 adapter->stats.roc;
5021 net_stats->rx_crc_errors = adapter->stats.crcerrs;
5022 net_stats->rx_frame_errors = adapter->stats.algnerrc;
5023 net_stats->rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 5024
5025 /* Tx Errors */
128e45eb
AD		 5026 net_stats->tx_errors = adapter->stats.ecol +
5027 adapter->stats.latecol;
5028 net_stats->tx_aborted_errors = adapter->stats.ecol;
5029 net_stats->tx_window_errors = adapter->stats.latecol;
5030 net_stats->tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 5031
5032 /* Tx Dropped needs to be maintained elsewhere */
5033
5034 /* Phy Stats */
5035 if (hw->phy.media_type == e1000_media_type_copper) {
5036 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 5037 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 5038 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
5039 adapter->phy_stats.idle_errors += phy_tmp;
5040 }
5041 }
5042
5043 /* Management Stats */
5044 adapter->stats.mgptc += rd32(E1000_MGTPTC);
5045 adapter->stats.mgprc += rd32(E1000_MGTPRC);
5046 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
0a915b95
CW		 5047
5048 /* OS2BMC Stats */
5049 reg = rd32(E1000_MANC);
5050 if (reg & E1000_MANC_EN_BMC2OS) {
5051 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5052 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5053 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5054 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5055 }
9d5c8243
AK		 5056}
5057
9d5c8243
AK		 5058static irqreturn_t igb_msix_other(int irq, void *data)
5059{
047e0030 5060 struct igb_adapter *adapter = data;
9d5c8243 5061 struct e1000_hw *hw = &adapter->hw;
844290e5 5062 u32 icr = rd32(E1000_ICR);
844290e5 5063 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 5064
7f081d40
AD		 5065 if (icr & E1000_ICR_DRSTA)
5066 schedule_work(&adapter->reset_task);
5067
047e0030 5068 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5069 /* HW is reporting DMA is out of sync */
5070 adapter->stats.doosync++;
13800469
GR		 5071 /* The DMA Out of Sync is also indication of a spoof event
5072 * in IOV mode. Check the Wrong VM Behavior register to
b980ac18
JK		 5073 * see if it is really a spoof event.
5074 */
13800469 5075 igb_check_wvbr(adapter);
dda0e083 5076 }
eebbbdba 5077
4ae196df
AD		 5078 /* Check for a mailbox event */
5079 if (icr & E1000_ICR_VMMB)
5080 igb_msg_task(adapter);
5081
5082 if (icr & E1000_ICR_LSC) {
5083 hw->mac.get_link_status = 1;
5084 /* guard against interrupt when we're going down */
5085 if (!test_bit(__IGB_DOWN, &adapter->state))
5086 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5087 }
5088
1f6e8178
MV		 5089 if (icr & E1000_ICR_TS) {
5090 u32 tsicr = rd32(E1000_TSICR);
5091
5092 if (tsicr & E1000_TSICR_TXTS) {
5093 /* acknowledge the interrupt */
5094 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5095 /* retrieve hardware timestamp */
5096 schedule_work(&adapter->ptp_tx_work);
5097 }
5098 }
1f6e8178 5099
844290e5 5100 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 5101
5102 return IRQ_HANDLED;
5103}
5104
047e0030 5105static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 5106{
26b39276 5107 struct igb_adapter *adapter = q_vector->adapter;
047e0030 5108 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 5109
047e0030
AD		 5110 if (!q_vector->set_itr)
5111 return;
73cd78f1 5112
047e0030
AD		 5113 if (!itr_val)
5114 itr_val = 0x4;
661086df 5115
26b39276
AD		 5116 if (adapter->hw.mac.type == e1000_82575)
5117 itr_val |= itr_val << 16;
661086df 5118 else
0ba82994 5119 itr_val |= E1000_EITR_CNT_IGNR;
661086df 5120
047e0030
AD		 5121 writel(itr_val, q_vector->itr_register);
5122 q_vector->set_itr = 0;
6eb5a7f1
AD		 5123}
5124
047e0030 5125static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 5126{
047e0030 5127 struct igb_q_vector *q_vector = data;
9d5c8243 5128
047e0030
AD		 5129 /* Write the ITR value calculated from the previous interrupt. */
5130 igb_write_itr(q_vector);
9d5c8243 5131
047e0030 5132 napi_schedule(&q_vector->napi);
844290e5 5133
047e0030 5134 return IRQ_HANDLED;
fe4506b6
JC		 5135}
5136
421e02f0 5137#ifdef CONFIG_IGB_DCA
6a05004a
AD		 5138static void igb_update_tx_dca(struct igb_adapter *adapter,
5139 struct igb_ring *tx_ring,
5140 int cpu)
5141{
5142 struct e1000_hw *hw = &adapter->hw;
5143 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5144
5145 if (hw->mac.type != e1000_82575)
5146 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5147
b980ac18 5148 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5149 * DCA is enabled. This is due to a known issue in some chipsets
5150 * which will cause the DCA tag to be cleared.
5151 */
5152 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5153 E1000_DCA_TXCTRL_DATA_RRO_EN |
5154 E1000_DCA_TXCTRL_DESC_DCA_EN;
5155
5156 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5157}
5158
5159static void igb_update_rx_dca(struct igb_adapter *adapter,
5160 struct igb_ring *rx_ring,
5161 int cpu)
5162{
5163 struct e1000_hw *hw = &adapter->hw;
5164 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5165
5166 if (hw->mac.type != e1000_82575)
5167 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5168
b980ac18 5169 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5170 * DCA is enabled. This is due to a known issue in some chipsets
5171 * which will cause the DCA tag to be cleared.
5172 */
5173 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5174 E1000_DCA_RXCTRL_DESC_DCA_EN;
5175
5176 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5177}
5178
047e0030 5179static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 5180{
047e0030 5181 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6 5182 int cpu = get_cpu();
fe4506b6 5183
047e0030
AD		 5184 if (q_vector->cpu == cpu)
5185 goto out_no_update;
5186
6a05004a
AD		 5187 if (q_vector->tx.ring)
5188 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5189
5190 if (q_vector->rx.ring)
5191 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5192
047e0030
AD		 5193 q_vector->cpu = cpu;
5194out_no_update:
fe4506b6
JC		 5195 put_cpu();
5196}
5197
5198static void igb_setup_dca(struct igb_adapter *adapter)
5199{
7e0e99ef 5200 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 5201 int i;
5202
7dfc16fa 5203 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 5204 return;
5205
7e0e99ef
AD		 5206 /* Always use CB2 mode, difference is masked in the CB driver. */
5207 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5208
047e0030 5209 for (i = 0; i < adapter->num_q_vectors; i++) {
26b39276
AD		 5210 adapter->q_vector[i]->cpu = -1;
5211 igb_update_dca(adapter->q_vector[i]);
fe4506b6
JC		 5212 }
5213}
5214
5215static int __igb_notify_dca(struct device *dev, void *data)
5216{
5217 struct net_device *netdev = dev_get_drvdata(dev);
5218 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5219 struct pci_dev *pdev = adapter->pdev;
fe4506b6
JC		 5220 struct e1000_hw *hw = &adapter->hw;
5221 unsigned long event = *(unsigned long *)data;
5222
5223 switch (event) {
5224 case DCA_PROVIDER_ADD:
5225 /* if already enabled, don't do it again */
7dfc16fa 5226 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 5227 break;
fe4506b6 5228 if (dca_add_requester(dev) == 0) {
bbd98fe4 5229 adapter->flags |= IGB_FLAG_DCA_ENABLED;
090b1795 5230 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 5231 igb_setup_dca(adapter);
5232 break;
5233 }
5234 /* Fall Through since DCA is disabled. */
5235 case DCA_PROVIDER_REMOVE:
7dfc16fa 5236 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 5237 /* without this a class_device is left
b980ac18
JK		 5238 * hanging around in the sysfs model
5239 */
fe4506b6 5240 dca_remove_requester(dev);
090b1795 5241 dev_info(&pdev->dev, "DCA disabled\n");
7dfc16fa 5242 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 5243 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 5244 }
5245 break;
5246 }
bbd98fe4 5247
fe4506b6 5248 return 0;
9d5c8243
AK		 5249}
5250
fe4506b6 5251static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
b980ac18 5252 void *p)
fe4506b6
JC		 5253{
5254 int ret_val;
5255
5256 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
b980ac18 5257 __igb_notify_dca);
fe4506b6
JC		 5258
5259 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5260}
421e02f0 5261#endif /* CONFIG_IGB_DCA */
9d5c8243 5262
0224d663
GR		 5263#ifdef CONFIG_PCI_IOV
5264static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5265{
5266 unsigned char mac_addr[ETH_ALEN];
0224d663 5267
5ac6f91d 5268 eth_zero_addr(mac_addr);
0224d663
GR		 5269 igb_set_vf_mac(adapter, vf, mac_addr);
5270
70ea4783
LL		 5271 /* By default spoof check is enabled for all VFs */
5272 adapter->vf_data[vf].spoofchk_enabled = true;
5273
f557147c 5274 return 0;
0224d663
GR		 5275}
5276
0224d663 5277#endif
4ae196df
AD		 5278static void igb_ping_all_vfs(struct igb_adapter *adapter)
5279{
5280 struct e1000_hw *hw = &adapter->hw;
5281 u32 ping;
5282 int i;
5283
5284 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5285 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 5286 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 5287 ping |= E1000_VT_MSGTYPE_CTS;
5288 igb_write_mbx(hw, &ping, 1, i);
5289 }
5290}
5291
7d5753f0
AD		 5292static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5293{
5294 struct e1000_hw *hw = &adapter->hw;
5295 u32 vmolr = rd32(E1000_VMOLR(vf));
5296 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5297
d85b9004 5298 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
b980ac18 5299 IGB_VF_FLAG_MULTI_PROMISC);
7d5753f0
AD		 5300 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5301
5302 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5303 vmolr |= E1000_VMOLR_MPME;
d85b9004 5304 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7d5753f0
AD		 5305 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5306 } else {
b980ac18 5307 /* if we have hashes and we are clearing a multicast promisc
7d5753f0
AD		 5308 * flag we need to write the hashes to the MTA as this step
5309 * was previously skipped
5310 */
5311 if (vf_data->num_vf_mc_hashes > 30) {
5312 vmolr |= E1000_VMOLR_MPME;
5313 } else if (vf_data->num_vf_mc_hashes) {
5314 int j;
5315 vmolr |= E1000_VMOLR_ROMPE;
5316 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5317 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5318 }
5319 }
5320
5321 wr32(E1000_VMOLR(vf), vmolr);
5322
5323 /* there are flags left unprocessed, likely not supported */
5324 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5325 return -EINVAL;
5326
5327 return 0;
7d5753f0
AD		 5328}
5329
4ae196df
AD		 5330static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5331 u32 *msgbuf, u32 vf)
5332{
5333 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5334 u16 *hash_list = (u16 *)&msgbuf[1];
5335 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5336 int i;
5337
7d5753f0 5338 /* salt away the number of multicast addresses assigned
4ae196df
AD		 5339 * to this VF for later use to restore when the PF multi cast
5340 * list changes
5341 */
5342 vf_data->num_vf_mc_hashes = n;
5343
7d5753f0
AD		 5344 /* only up to 30 hash values supported */
5345 if (n > 30)
5346 n = 30;
5347
5348 /* store the hashes for later use */
4ae196df 5349 for (i = 0; i < n; i++)
a419aef8 5350 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 5351
5352 /* Flush and reset the mta with the new values */
ff41f8dc 5353 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5354
5355 return 0;
5356}
5357
5358static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5359{
5360 struct e1000_hw *hw = &adapter->hw;
5361 struct vf_data_storage *vf_data;
5362 int i, j;
5363
5364 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0
AD		 5365 u32 vmolr = rd32(E1000_VMOLR(i));
5366 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5367
4ae196df 5368 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 5369
5370 if ((vf_data->num_vf_mc_hashes > 30) ||
5371 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5372 vmolr |= E1000_VMOLR_MPME;
5373 } else if (vf_data->num_vf_mc_hashes) {
5374 vmolr |= E1000_VMOLR_ROMPE;
5375 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5376 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5377 }
5378 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 5379 }
5380}
5381
5382static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5383{
5384 struct e1000_hw *hw = &adapter->hw;
5385 u32 pool_mask, reg, vid;
5386 int i;
5387
5388 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5389
5390 /* Find the vlan filter for this id */
5391 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5392 reg = rd32(E1000_VLVF(i));
5393
5394 /* remove the vf from the pool */
5395 reg &= ~pool_mask;
5396
5397 /* if pool is empty then remove entry from vfta */
5398 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5399 (reg & E1000_VLVF_VLANID_ENABLE)) {
5400 reg = 0;
5401 vid = reg & E1000_VLVF_VLANID_MASK;
5402 igb_vfta_set(hw, vid, false);
5403 }
5404
5405 wr32(E1000_VLVF(i), reg);
5406 }
ae641bdc
AD		 5407
5408 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 5409}
5410
5411static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5412{
5413 struct e1000_hw *hw = &adapter->hw;
5414 u32 reg, i;
5415
51466239
AD		 5416 /* The vlvf table only exists on 82576 hardware and newer */
5417 if (hw->mac.type < e1000_82576)
5418 return -1;
5419
5420 /* we only need to do this if VMDq is enabled */
4ae196df
AD		 5421 if (!adapter->vfs_allocated_count)
5422 return -1;
5423
5424 /* Find the vlan filter for this id */
5425 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5426 reg = rd32(E1000_VLVF(i));
5427 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5428 vid == (reg & E1000_VLVF_VLANID_MASK))
5429 break;
5430 }
5431
5432 if (add) {
5433 if (i == E1000_VLVF_ARRAY_SIZE) {
5434 /* Did not find a matching VLAN ID entry that was
5435 * enabled. Search for a free filter entry, i.e.
5436 * one without the enable bit set
5437 */
5438 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5439 reg = rd32(E1000_VLVF(i));
5440 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5441 break;
5442 }
5443 }
5444 if (i < E1000_VLVF_ARRAY_SIZE) {
5445 /* Found an enabled/available entry */
5446 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5447
5448 /* if !enabled we need to set this up in vfta */
5449 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
51466239
AD		 5450 /* add VID to filter table */
5451 igb_vfta_set(hw, vid, true);
4ae196df
AD		 5452 reg |= E1000_VLVF_VLANID_ENABLE;
5453 }
cad6d05f
AD		 5454 reg &= ~E1000_VLVF_VLANID_MASK;
5455 reg |= vid;
4ae196df 5456 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5457
5458 /* do not modify RLPML for PF devices */
5459 if (vf >= adapter->vfs_allocated_count)
5460 return 0;
5461
5462 if (!adapter->vf_data[vf].vlans_enabled) {
5463 u32 size;
5464 reg = rd32(E1000_VMOLR(vf));
5465 size = reg & E1000_VMOLR_RLPML_MASK;
5466 size += 4;
5467 reg &= ~E1000_VMOLR_RLPML_MASK;
5468 reg |= size;
5469 wr32(E1000_VMOLR(vf), reg);
5470 }
ae641bdc 5471
51466239 5472 adapter->vf_data[vf].vlans_enabled++;
4ae196df
AD		 5473 }
5474 } else {
5475 if (i < E1000_VLVF_ARRAY_SIZE) {
5476 /* remove vf from the pool */
5477 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5478 /* if pool is empty then remove entry from vfta */
5479 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5480 reg = 0;
5481 igb_vfta_set(hw, vid, false);
5482 }
5483 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5484
5485 /* do not modify RLPML for PF devices */
5486 if (vf >= adapter->vfs_allocated_count)
5487 return 0;
5488
5489 adapter->vf_data[vf].vlans_enabled--;
5490 if (!adapter->vf_data[vf].vlans_enabled) {
5491 u32 size;
5492 reg = rd32(E1000_VMOLR(vf));
5493 size = reg & E1000_VMOLR_RLPML_MASK;
5494 size -= 4;
5495 reg &= ~E1000_VMOLR_RLPML_MASK;
5496 reg |= size;
5497 wr32(E1000_VMOLR(vf), reg);
5498 }
4ae196df
AD		 5499 }
5500 }
8151d294
WM		 5501 return 0;
5502}
5503
5504static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5505{
5506 struct e1000_hw *hw = &adapter->hw;
5507
5508 if (vid)
5509 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5510 else
5511 wr32(E1000_VMVIR(vf), 0);
5512}
5513
5514static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5515 int vf, u16 vlan, u8 qos)
5516{
5517 int err = 0;
5518 struct igb_adapter *adapter = netdev_priv(netdev);
5519
5520 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5521 return -EINVAL;
5522 if (vlan || qos) {
5523 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5524 if (err)
5525 goto out;
5526 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5527 igb_set_vmolr(adapter, vf, !vlan);
5528 adapter->vf_data[vf].pf_vlan = vlan;
5529 adapter->vf_data[vf].pf_qos = qos;
5530 dev_info(&adapter->pdev->dev,
5531 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5532 if (test_bit(__IGB_DOWN, &adapter->state)) {
5533 dev_warn(&adapter->pdev->dev,
b980ac18 5534 "The VF VLAN has been set, but the PF device is not up.\n");
8151d294 5535 dev_warn(&adapter->pdev->dev,
b980ac18 5536 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 5537 }
5538 } else {
5539 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
b980ac18 5540 false, vf);
8151d294
WM		 5541 igb_set_vmvir(adapter, vlan, vf);
5542 igb_set_vmolr(adapter, vf, true);
5543 adapter->vf_data[vf].pf_vlan = 0;
5544 adapter->vf_data[vf].pf_qos = 0;
b980ac18 5545 }
8151d294 5546out:
b980ac18 5547 return err;
4ae196df
AD		 5548}
5549
6f3dc319
GR		 5550static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid)
5551{
5552 struct e1000_hw *hw = &adapter->hw;
5553 int i;
5554 u32 reg;
5555
5556 /* Find the vlan filter for this id */
5557 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5558 reg = rd32(E1000_VLVF(i));
5559 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5560 vid == (reg & E1000_VLVF_VLANID_MASK))
5561 break;
5562 }
5563
5564 if (i >= E1000_VLVF_ARRAY_SIZE)
5565 i = -1;
5566
5567 return i;
5568}
5569
4ae196df
AD		 5570static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5571{
6f3dc319 5572 struct e1000_hw *hw = &adapter->hw;
4ae196df
AD		 5573 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5574 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
6f3dc319 5575 int err = 0;
4ae196df 5576
6f3dc319
GR		 5577 /* If in promiscuous mode we need to make sure the PF also has
5578 * the VLAN filter set.
5579 */
5580 if (add && (adapter->netdev->flags & IFF_PROMISC))
5581 err = igb_vlvf_set(adapter, vid, add,
5582 adapter->vfs_allocated_count);
5583 if (err)
5584 goto out;
5585
5586 err = igb_vlvf_set(adapter, vid, add, vf);
5587
5588 if (err)
5589 goto out;
5590
5591 /* Go through all the checks to see if the VLAN filter should
5592 * be wiped completely.
5593 */
5594 if (!add && (adapter->netdev->flags & IFF_PROMISC)) {
5595 u32 vlvf, bits;
5596
5597 int regndx = igb_find_vlvf_entry(adapter, vid);
5598 if (regndx < 0)
5599 goto out;
5600 /* See if any other pools are set for this VLAN filter
5601 * entry other than the PF.
5602 */
5603 vlvf = bits = rd32(E1000_VLVF(regndx));
5604 bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT +
5605 adapter->vfs_allocated_count);
5606 /* If the filter was removed then ensure PF pool bit
5607 * is cleared if the PF only added itself to the pool
5608 * because the PF is in promiscuous mode.
5609 */
5610 if ((vlvf & VLAN_VID_MASK) == vid &&
5611 !test_bit(vid, adapter->active_vlans) &&
5612 !bits)
5613 igb_vlvf_set(adapter, vid, add,
5614 adapter->vfs_allocated_count);
5615 }
5616
5617out:
5618 return err;
4ae196df
AD		 5619}
5620
f2ca0dbe 5621static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
4ae196df 5622{
8fa7e0f7
GR		 5623 /* clear flags - except flag that indicates PF has set the MAC */
5624 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
f2ca0dbe 5625 adapter->vf_data[vf].last_nack = jiffies;
4ae196df
AD		 5626
5627 /* reset offloads to defaults */
8151d294 5628 igb_set_vmolr(adapter, vf, true);
4ae196df
AD		 5629
5630 /* reset vlans for device */
5631 igb_clear_vf_vfta(adapter, vf);
8151d294
WM		 5632 if (adapter->vf_data[vf].pf_vlan)
5633 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5634 adapter->vf_data[vf].pf_vlan,
5635 adapter->vf_data[vf].pf_qos);
5636 else
5637 igb_clear_vf_vfta(adapter, vf);
4ae196df
AD		 5638
5639 /* reset multicast table array for vf */
5640 adapter->vf_data[vf].num_vf_mc_hashes = 0;
5641
5642 /* Flush and reset the mta with the new values */
ff41f8dc 5643 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5644}
5645
f2ca0dbe
AD		 5646static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5647{
5648 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5649
5ac6f91d 5650 /* clear mac address as we were hotplug removed/added */
8151d294 5651 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5ac6f91d 5652 eth_zero_addr(vf_mac);
f2ca0dbe
AD		 5653
5654 /* process remaining reset events */
5655 igb_vf_reset(adapter, vf);
5656}
5657
5658static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 5659{
5660 struct e1000_hw *hw = &adapter->hw;
5661 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 5662 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 5663 u32 reg, msgbuf[3];
5664 u8 *addr = (u8 *)(&msgbuf[1]);
5665
5666 /* process all the same items cleared in a function level reset */
f2ca0dbe 5667 igb_vf_reset(adapter, vf);
4ae196df
AD		 5668
5669 /* set vf mac address */
26ad9178 5670 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 5671
5672 /* enable transmit and receive for vf */
5673 reg = rd32(E1000_VFTE);
5674 wr32(E1000_VFTE, reg | (1 << vf));
5675 reg = rd32(E1000_VFRE);
5676 wr32(E1000_VFRE, reg | (1 << vf));
5677
8fa7e0f7 5678 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
4ae196df
AD		 5679
5680 /* reply to reset with ack and vf mac address */
5681 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
5682 memcpy(addr, vf_mac, 6);
5683 igb_write_mbx(hw, msgbuf, 3, vf);
5684}
5685
5686static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
5687{
b980ac18 5688 /* The VF MAC Address is stored in a packed array of bytes
de42edde
GR		 5689 * starting at the second 32 bit word of the msg array
5690 */
f2ca0dbe
AD		 5691 unsigned char *addr = (char *)&msg[1];
5692 int err = -1;
4ae196df 5693
f2ca0dbe
AD		 5694 if (is_valid_ether_addr(addr))
5695 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 5696
f2ca0dbe 5697 return err;
4ae196df
AD		 5698}
5699
5700static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
5701{
5702 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5703 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5704 u32 msg = E1000_VT_MSGTYPE_NACK;
5705
5706 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 5707 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
5708 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 5709 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 5710 vf_data->last_nack = jiffies;
4ae196df
AD		 5711 }
5712}
5713
f2ca0dbe 5714static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 5715{
f2ca0dbe
AD		 5716 struct pci_dev *pdev = adapter->pdev;
5717 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 5718 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5719 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5720 s32 retval;
5721
f2ca0dbe 5722 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df 5723
fef45f4c
AD		 5724 if (retval) {
5725 /* if receive failed revoke VF CTS stats and restart init */
f2ca0dbe 5726 dev_err(&pdev->dev, "Error receiving message from VF\n");
fef45f4c
AD		 5727 vf_data->flags &= ~IGB_VF_FLAG_CTS;
5728 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5729 return;
5730 goto out;
5731 }
4ae196df
AD		 5732
5733 /* this is a message we already processed, do nothing */
5734 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 5735 return;
4ae196df 5736
b980ac18 5737 /* until the vf completes a reset it should not be
4ae196df
AD		 5738 * allowed to start any configuration.
5739 */
4ae196df
AD		 5740 if (msgbuf[0] == E1000_VF_RESET) {
5741 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 5742 return;
4ae196df
AD		 5743 }
5744
f2ca0dbe 5745 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
fef45f4c
AD		 5746 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5747 return;
5748 retval = -1;
5749 goto out;
4ae196df
AD		 5750 }
5751
5752 switch ((msgbuf[0] & 0xFFFF)) {
5753 case E1000_VF_SET_MAC_ADDR:
a6b5ea35
GR		 5754 retval = -EINVAL;
5755 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
5756 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
5757 else
5758 dev_warn(&pdev->dev,
b980ac18
JK		 5759 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
5760 vf);
4ae196df 5761 break;
7d5753f0
AD		 5762 case E1000_VF_SET_PROMISC:
5763 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
5764 break;
4ae196df
AD		 5765 case E1000_VF_SET_MULTICAST:
5766 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
5767 break;
5768 case E1000_VF_SET_LPE:
5769 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
5770 break;
5771 case E1000_VF_SET_VLAN:
a6b5ea35
GR		 5772 retval = -1;
5773 if (vf_data->pf_vlan)
5774 dev_warn(&pdev->dev,
b980ac18
JK		 5775 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
5776 vf);
8151d294
WM		 5777 else
5778 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4ae196df
AD		 5779 break;
5780 default:
090b1795 5781 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4ae196df
AD		 5782 retval = -1;
5783 break;
5784 }
5785
fef45f4c
AD		 5786 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
5787out:
4ae196df
AD		 5788 /* notify the VF of the results of what it sent us */
5789 if (retval)
5790 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
5791 else
5792 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
5793
4ae196df 5794 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 5795}
4ae196df 5796
f2ca0dbe
AD		 5797static void igb_msg_task(struct igb_adapter *adapter)
5798{
5799 struct e1000_hw *hw = &adapter->hw;
5800 u32 vf;
5801
5802 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
5803 /* process any reset requests */
5804 if (!igb_check_for_rst(hw, vf))
5805 igb_vf_reset_event(adapter, vf);
5806
5807 /* process any messages pending */
5808 if (!igb_check_for_msg(hw, vf))
5809 igb_rcv_msg_from_vf(adapter, vf);
5810
5811 /* process any acks */
5812 if (!igb_check_for_ack(hw, vf))
5813 igb_rcv_ack_from_vf(adapter, vf);
5814 }
4ae196df
AD		 5815}
5816
68d480c4
AD		 5817/**
5818 * igb_set_uta - Set unicast filter table address
5819 * @adapter: board private structure
5820 *
5821 * The unicast table address is a register array of 32-bit registers.
5822 * The table is meant to be used in a way similar to how the MTA is used
5823 * however due to certain limitations in the hardware it is necessary to
25985edc
LDM		 5824 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
5825 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
68d480c4
AD		 5826 **/
5827static void igb_set_uta(struct igb_adapter *adapter)
5828{
5829 struct e1000_hw *hw = &adapter->hw;
5830 int i;
5831
5832 /* The UTA table only exists on 82576 hardware and newer */
5833 if (hw->mac.type < e1000_82576)
5834 return;
5835
5836 /* we only need to do this if VMDq is enabled */
5837 if (!adapter->vfs_allocated_count)
5838 return;
5839
5840 for (i = 0; i < hw->mac.uta_reg_count; i++)
5841 array_wr32(E1000_UTA, i, ~0);
5842}
5843
9d5c8243 5844/**
b980ac18
JK		 5845 * igb_intr_msi - Interrupt Handler
5846 * @irq: interrupt number
5847 * @data: pointer to a network interface device structure
9d5c8243
AK		 5848 **/
5849static irqreturn_t igb_intr_msi(int irq, void *data)
5850{
047e0030
AD		 5851 struct igb_adapter *adapter = data;
5852 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5853 struct e1000_hw *hw = &adapter->hw;
5854 /* read ICR disables interrupts using IAM */
5855 u32 icr = rd32(E1000_ICR);
5856
047e0030 5857 igb_write_itr(q_vector);
9d5c8243 5858
7f081d40
AD		 5859 if (icr & E1000_ICR_DRSTA)
5860 schedule_work(&adapter->reset_task);
5861
047e0030 5862 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5863 /* HW is reporting DMA is out of sync */
5864 adapter->stats.doosync++;
5865 }
5866
9d5c8243
AK		 5867 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5868 hw->mac.get_link_status = 1;
5869 if (!test_bit(__IGB_DOWN, &adapter->state))
5870 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5871 }
5872
1f6e8178
MV		 5873 if (icr & E1000_ICR_TS) {
5874 u32 tsicr = rd32(E1000_TSICR);
5875
5876 if (tsicr & E1000_TSICR_TXTS) {
5877 /* acknowledge the interrupt */
5878 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5879 /* retrieve hardware timestamp */
5880 schedule_work(&adapter->ptp_tx_work);
5881 }
5882 }
1f6e8178 5883
047e0030 5884 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5885
5886 return IRQ_HANDLED;
5887}
5888
5889/**
b980ac18
JK		 5890 * igb_intr - Legacy Interrupt Handler
5891 * @irq: interrupt number
5892 * @data: pointer to a network interface device structure
9d5c8243
AK		 5893 **/
5894static irqreturn_t igb_intr(int irq, void *data)
5895{
047e0030
AD		 5896 struct igb_adapter *adapter = data;
5897 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5898 struct e1000_hw *hw = &adapter->hw;
5899 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
b980ac18
JK		 5900 * need for the IMC write
5901 */
9d5c8243 5902 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 5903
5904 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
b980ac18
JK		 5905 * not set, then the adapter didn't send an interrupt
5906 */
9d5c8243
AK		 5907 if (!(icr & E1000_ICR_INT_ASSERTED))
5908 return IRQ_NONE;
5909
0ba82994
AD		 5910 igb_write_itr(q_vector);
5911
7f081d40
AD		 5912 if (icr & E1000_ICR_DRSTA)
5913 schedule_work(&adapter->reset_task);
5914
047e0030 5915 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5916 /* HW is reporting DMA is out of sync */
5917 adapter->stats.doosync++;
5918 }
5919
9d5c8243
AK		 5920 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5921 hw->mac.get_link_status = 1;
5922 /* guard against interrupt when we're going down */
5923 if (!test_bit(__IGB_DOWN, &adapter->state))
5924 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5925 }
5926
1f6e8178
MV		 5927 if (icr & E1000_ICR_TS) {
5928 u32 tsicr = rd32(E1000_TSICR);
5929
5930 if (tsicr & E1000_TSICR_TXTS) {
5931 /* acknowledge the interrupt */
5932 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5933 /* retrieve hardware timestamp */
5934 schedule_work(&adapter->ptp_tx_work);
5935 }
5936 }
1f6e8178 5937
047e0030 5938 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5939
5940 return IRQ_HANDLED;
5941}
5942
c50b52a0 5943static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 5944{
047e0030 5945 struct igb_adapter *adapter = q_vector->adapter;
46544258 5946 struct e1000_hw *hw = &adapter->hw;
9d5c8243 5947
0ba82994
AD		 5948 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
5949 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
5950 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
5951 igb_set_itr(q_vector);
46544258 5952 else
047e0030 5953 igb_update_ring_itr(q_vector);
9d5c8243
AK		 5954 }
5955
46544258
AD		 5956 if (!test_bit(__IGB_DOWN, &adapter->state)) {
5957 if (adapter->msix_entries)
047e0030 5958 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 5959 else
5960 igb_irq_enable(adapter);
5961 }
9d5c8243
AK		 5962}
5963
46544258 5964/**
b980ac18
JK		 5965 * igb_poll - NAPI Rx polling callback
5966 * @napi: napi polling structure
5967 * @budget: count of how many packets we should handle
46544258
AD		 5968 **/
5969static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 5970{
047e0030 5971 struct igb_q_vector *q_vector = container_of(napi,
b980ac18
JK		 5972 struct igb_q_vector,
5973 napi);
16eb8815 5974 bool clean_complete = true;
9d5c8243 5975
421e02f0 5976#ifdef CONFIG_IGB_DCA
047e0030
AD		 5977 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
5978 igb_update_dca(q_vector);
fe4506b6 5979#endif
0ba82994 5980 if (q_vector->tx.ring)
13fde97a 5981 clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 5982
0ba82994 5983 if (q_vector->rx.ring)
cd392f5c 5984 clean_complete &= igb_clean_rx_irq(q_vector, budget);
047e0030 5985
16eb8815
AD		 5986 /* If all work not completed, return budget and keep polling */
5987 if (!clean_complete)
5988 return budget;
46544258 5989
9d5c8243 5990 /* If not enough Rx work done, exit the polling mode */
16eb8815
AD		 5991 napi_complete(napi);
5992 igb_ring_irq_enable(q_vector);
9d5c8243 5993
16eb8815 5994 return 0;
9d5c8243 5995}
6d8126f9 5996
9d5c8243 5997/**
b980ac18
JK		 5998 * igb_clean_tx_irq - Reclaim resources after transmit completes
5999 * @q_vector: pointer to q_vector containing needed info
49ce9c2c 6000 *
b980ac18 6001 * returns true if ring is completely cleaned
9d5c8243 6002 **/
047e0030 6003static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 6004{
047e0030 6005 struct igb_adapter *adapter = q_vector->adapter;
0ba82994 6006 struct igb_ring *tx_ring = q_vector->tx.ring;
06034649 6007 struct igb_tx_buffer *tx_buffer;
f4128785 6008 union e1000_adv_tx_desc *tx_desc;
9d5c8243 6009 unsigned int total_bytes = 0, total_packets = 0;
0ba82994 6010 unsigned int budget = q_vector->tx.work_limit;
8542db05 6011 unsigned int i = tx_ring->next_to_clean;
9d5c8243 6012
13fde97a
AD		 6013 if (test_bit(__IGB_DOWN, &adapter->state))
6014 return true;
0e014cb1 6015
06034649 6016 tx_buffer = &tx_ring->tx_buffer_info[i];
13fde97a 6017 tx_desc = IGB_TX_DESC(tx_ring, i);
8542db05 6018 i -= tx_ring->count;
9d5c8243 6019
f4128785
AD		 6020 do {
6021 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
8542db05
AD		 6022
6023 /* if next_to_watch is not set then there is no work pending */
6024 if (!eop_desc)
6025 break;
13fde97a 6026
f4128785 6027 /* prevent any other reads prior to eop_desc */
70d289bc 6028 read_barrier_depends();
f4128785 6029
13fde97a
AD		 6030 /* if DD is not set pending work has not been completed */
6031 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
6032 break;
6033
8542db05
AD		 6034 /* clear next_to_watch to prevent false hangs */
6035 tx_buffer->next_to_watch = NULL;
9d5c8243 6036
ebe42d16
AD		 6037 /* update the statistics for this packet */
6038 total_bytes += tx_buffer->bytecount;
6039 total_packets += tx_buffer->gso_segs;
13fde97a 6040
ebe42d16
AD		 6041 /* free the skb */
6042 dev_kfree_skb_any(tx_buffer->skb);
13fde97a 6043
ebe42d16
AD		 6044 /* unmap skb header data */
6045 dma_unmap_single(tx_ring->dev,
c9f14bf3
AD		 6046 dma_unmap_addr(tx_buffer, dma),
6047 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 6048 DMA_TO_DEVICE);
6049
c9f14bf3
AD		 6050 /* clear tx_buffer data */
6051 tx_buffer->skb = NULL;
6052 dma_unmap_len_set(tx_buffer, len, 0);
6053
ebe42d16
AD		 6054 /* clear last DMA location and unmap remaining buffers */
6055 while (tx_desc != eop_desc) {
13fde97a
AD		 6056 tx_buffer++;
6057 tx_desc++;
9d5c8243 6058 i++;
8542db05
AD		 6059 if (unlikely(!i)) {
6060 i -= tx_ring->count;
06034649 6061 tx_buffer = tx_ring->tx_buffer_info;
13fde97a
AD		 6062 tx_desc = IGB_TX_DESC(tx_ring, 0);
6063 }
ebe42d16
AD		 6064
6065 /* unmap any remaining paged data */
c9f14bf3 6066 if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 6067 dma_unmap_page(tx_ring->dev,
c9f14bf3
AD		 6068 dma_unmap_addr(tx_buffer, dma),
6069 dma_unmap_len(tx_buffer, len),
ebe42d16 6070 DMA_TO_DEVICE);
c9f14bf3 6071 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16
AD		 6072 }
6073 }
6074
ebe42d16
AD		 6075 /* move us one more past the eop_desc for start of next pkt */
6076 tx_buffer++;
6077 tx_desc++;
6078 i++;
6079 if (unlikely(!i)) {
6080 i -= tx_ring->count;
6081 tx_buffer = tx_ring->tx_buffer_info;
6082 tx_desc = IGB_TX_DESC(tx_ring, 0);
6083 }
f4128785
AD		 6084
6085 /* issue prefetch for next Tx descriptor */
6086 prefetch(tx_desc);
6087
6088 /* update budget accounting */
6089 budget--;
6090 } while (likely(budget));
0e014cb1 6091
bdbc0631
ED		 6092 netdev_tx_completed_queue(txring_txq(tx_ring),
6093 total_packets, total_bytes);
8542db05 6094 i += tx_ring->count;
9d5c8243 6095 tx_ring->next_to_clean = i;
13fde97a
AD		 6096 u64_stats_update_begin(&tx_ring->tx_syncp);
6097 tx_ring->tx_stats.bytes += total_bytes;
6098 tx_ring->tx_stats.packets += total_packets;
6099 u64_stats_update_end(&tx_ring->tx_syncp);
0ba82994
AD		 6100 q_vector->tx.total_bytes += total_bytes;
6101 q_vector->tx.total_packets += total_packets;
9d5c8243 6102
6d095fa8 6103 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
13fde97a 6104 struct e1000_hw *hw = &adapter->hw;
12dcd86b 6105
9d5c8243 6106 /* Detect a transmit hang in hardware, this serializes the
b980ac18
JK		 6107 * check with the clearing of time_stamp and movement of i
6108 */
6d095fa8 6109 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
f4128785 6110 if (tx_buffer->next_to_watch &&
8542db05 6111 time_after(jiffies, tx_buffer->time_stamp +
8e95a202
JP		 6112 (adapter->tx_timeout_factor * HZ)) &&
6113 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
9d5c8243 6114
9d5c8243 6115 /* detected Tx unit hang */
59d71989 6116 dev_err(tx_ring->dev,
9d5c8243 6117 "Detected Tx Unit Hang\n"
2d064c06 6118 " Tx Queue <%d>\n"
9d5c8243
AK		 6119 " TDH <%x>\n"
6120 " TDT <%x>\n"
6121 " next_to_use <%x>\n"
6122 " next_to_clean <%x>\n"
9d5c8243
AK		 6123 "buffer_info[next_to_clean]\n"
6124 " time_stamp <%lx>\n"
8542db05 6125 " next_to_watch <%p>\n"
9d5c8243
AK		 6126 " jiffies <%lx>\n"
6127 " desc.status <%x>\n",
2d064c06 6128 tx_ring->queue_index,
238ac817 6129 rd32(E1000_TDH(tx_ring->reg_idx)),
fce99e34 6130 readl(tx_ring->tail),
9d5c8243
AK		 6131 tx_ring->next_to_use,
6132 tx_ring->next_to_clean,
8542db05 6133 tx_buffer->time_stamp,
f4128785 6134 tx_buffer->next_to_watch,
9d5c8243 6135 jiffies,
f4128785 6136 tx_buffer->next_to_watch->wb.status);
13fde97a
AD		 6137 netif_stop_subqueue(tx_ring->netdev,
6138 tx_ring->queue_index);
6139
6140 /* we are about to reset, no point in enabling stuff */
6141 return true;
9d5c8243
AK		 6142 }
6143 }
13fde97a 6144
21ba6fe1 6145#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
13fde97a 6146 if (unlikely(total_packets &&
b980ac18
JK		 6147 netif_carrier_ok(tx_ring->netdev) &&
6148 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
13fde97a
AD		 6149 /* Make sure that anybody stopping the queue after this
6150 * sees the new next_to_clean.
6151 */
6152 smp_mb();
6153 if (__netif_subqueue_stopped(tx_ring->netdev,
6154 tx_ring->queue_index) &&
6155 !(test_bit(__IGB_DOWN, &adapter->state))) {
6156 netif_wake_subqueue(tx_ring->netdev,
6157 tx_ring->queue_index);
6158
6159 u64_stats_update_begin(&tx_ring->tx_syncp);
6160 tx_ring->tx_stats.restart_queue++;
6161 u64_stats_update_end(&tx_ring->tx_syncp);
6162 }
6163 }
6164
6165 return !!budget;
9d5c8243
AK		 6166}
6167
cbc8e55f 6168/**
b980ac18
JK		 6169 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6170 * @rx_ring: rx descriptor ring to store buffers on
6171 * @old_buff: donor buffer to have page reused
cbc8e55f 6172 *
b980ac18 6173 * Synchronizes page for reuse by the adapter
cbc8e55f
AD		 6174 **/
6175static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6176 struct igb_rx_buffer *old_buff)
6177{
6178 struct igb_rx_buffer *new_buff;
6179 u16 nta = rx_ring->next_to_alloc;
6180
6181 new_buff = &rx_ring->rx_buffer_info[nta];
6182
6183 /* update, and store next to alloc */
6184 nta++;
6185 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6186
6187 /* transfer page from old buffer to new buffer */
6188 memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer));
6189
6190 /* sync the buffer for use by the device */
6191 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6192 old_buff->page_offset,
de78d1f9 6193 IGB_RX_BUFSZ,
cbc8e55f
AD		 6194 DMA_FROM_DEVICE);
6195}
6196
74e238ea
AD		 6197static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6198 struct page *page,
6199 unsigned int truesize)
6200{
6201 /* avoid re-using remote pages */
6202 if (unlikely(page_to_nid(page) != numa_node_id()))
6203 return false;
6204
6205#if (PAGE_SIZE < 8192)
6206 /* if we are only owner of page we can reuse it */
6207 if (unlikely(page_count(page) != 1))
6208 return false;
6209
6210 /* flip page offset to other buffer */
6211 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
6212
6213 /* since we are the only owner of the page and we need to
6214 * increment it, just set the value to 2 in order to avoid
6215 * an unnecessary locked operation
6216 */
6217 atomic_set(&page->_count, 2);
6218#else
6219 /* move offset up to the next cache line */
6220 rx_buffer->page_offset += truesize;
6221
6222 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6223 return false;
6224
6225 /* bump ref count on page before it is given to the stack */
6226 get_page(page);
6227#endif
6228
6229 return true;
6230}
6231
cbc8e55f 6232/**
b980ac18
JK		 6233 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6234 * @rx_ring: rx descriptor ring to transact packets on
6235 * @rx_buffer: buffer containing page to add
6236 * @rx_desc: descriptor containing length of buffer written by hardware
6237 * @skb: sk_buff to place the data into
cbc8e55f 6238 *
b980ac18
JK		 6239 * This function will add the data contained in rx_buffer->page to the skb.
6240 * This is done either through a direct copy if the data in the buffer is
6241 * less than the skb header size, otherwise it will just attach the page as
6242 * a frag to the skb.
cbc8e55f 6243 *
b980ac18
JK		 6244 * The function will then update the page offset if necessary and return
6245 * true if the buffer can be reused by the adapter.
cbc8e55f
AD		 6246 **/
6247static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6248 struct igb_rx_buffer *rx_buffer,
6249 union e1000_adv_rx_desc *rx_desc,
6250 struct sk_buff *skb)
6251{
6252 struct page *page = rx_buffer->page;
6253 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
74e238ea
AD		 6254#if (PAGE_SIZE < 8192)
6255 unsigned int truesize = IGB_RX_BUFSZ;
6256#else
6257 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
6258#endif
cbc8e55f
AD		 6259
6260 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) {
6261 unsigned char *va = page_address(page) + rx_buffer->page_offset;
6262
cbc8e55f
AD		 6263 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6264 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6265 va += IGB_TS_HDR_LEN;
6266 size -= IGB_TS_HDR_LEN;
6267 }
6268
cbc8e55f
AD		 6269 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6270
6271 /* we can reuse buffer as-is, just make sure it is local */
6272 if (likely(page_to_nid(page) == numa_node_id()))
6273 return true;
6274
6275 /* this page cannot be reused so discard it */
6276 put_page(page);
6277 return false;
6278 }
6279
6280 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
74e238ea 6281 rx_buffer->page_offset, size, truesize);
cbc8e55f 6282
74e238ea
AD		 6283 return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6284}
cbc8e55f 6285
2e334eee
AD		 6286static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6287 union e1000_adv_rx_desc *rx_desc,
6288 struct sk_buff *skb)
6289{
6290 struct igb_rx_buffer *rx_buffer;
6291 struct page *page;
6292
6293 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
6294
2e334eee
AD		 6295 page = rx_buffer->page;
6296 prefetchw(page);
6297
6298 if (likely(!skb)) {
6299 void *page_addr = page_address(page) +
6300 rx_buffer->page_offset;
6301
6302 /* prefetch first cache line of first page */
6303 prefetch(page_addr);
6304#if L1_CACHE_BYTES < 128
6305 prefetch(page_addr + L1_CACHE_BYTES);
6306#endif
6307
6308 /* allocate a skb to store the frags */
6309 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
6310 IGB_RX_HDR_LEN);
6311 if (unlikely(!skb)) {
6312 rx_ring->rx_stats.alloc_failed++;
6313 return NULL;
6314 }
6315
b980ac18 6316 /* we will be copying header into skb->data in
2e334eee
AD		 6317 * pskb_may_pull so it is in our interest to prefetch
6318 * it now to avoid a possible cache miss
6319 */
6320 prefetchw(skb->data);
6321 }
6322
6323 /* we are reusing so sync this buffer for CPU use */
6324 dma_sync_single_range_for_cpu(rx_ring->dev,
6325 rx_buffer->dma,
6326 rx_buffer->page_offset,
de78d1f9 6327 IGB_RX_BUFSZ,
2e334eee
AD		 6328 DMA_FROM_DEVICE);
6329
6330 /* pull page into skb */
6331 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6332 /* hand second half of page back to the ring */
6333 igb_reuse_rx_page(rx_ring, rx_buffer);
6334 } else {
6335 /* we are not reusing the buffer so unmap it */
6336 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6337 PAGE_SIZE, DMA_FROM_DEVICE);
6338 }
6339
6340 /* clear contents of rx_buffer */
6341 rx_buffer->page = NULL;
6342
6343 return skb;
6344}
6345
cd392f5c 6346static inline void igb_rx_checksum(struct igb_ring *ring,
3ceb90fd
AD		 6347 union e1000_adv_rx_desc *rx_desc,
6348 struct sk_buff *skb)
9d5c8243 6349{
bc8acf2c 6350 skb_checksum_none_assert(skb);
9d5c8243 6351
294e7d78 6352 /* Ignore Checksum bit is set */
3ceb90fd 6353 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
294e7d78
AD		 6354 return;
6355
6356 /* Rx checksum disabled via ethtool */
6357 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9d5c8243 6358 return;
85ad76b2 6359
9d5c8243 6360 /* TCP/UDP checksum error bit is set */
3ceb90fd
AD		 6361 if (igb_test_staterr(rx_desc,
6362 E1000_RXDEXT_STATERR_TCPE |
6363 E1000_RXDEXT_STATERR_IPE)) {
b980ac18 6364 /* work around errata with sctp packets where the TCPE aka
b9473560
JB		 6365 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6366 * packets, (aka let the stack check the crc32c)
6367 */
866cff06
AD		 6368 if (!((skb->len == 60) &&
6369 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
12dcd86b 6370 u64_stats_update_begin(&ring->rx_syncp);
04a5fcaa 6371 ring->rx_stats.csum_err++;
12dcd86b
ED		 6372 u64_stats_update_end(&ring->rx_syncp);
6373 }
9d5c8243 6374 /* let the stack verify checksum errors */
9d5c8243
AK		 6375 return;
6376 }
6377 /* It must be a TCP or UDP packet with a valid checksum */
3ceb90fd
AD		 6378 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6379 E1000_RXD_STAT_UDPCS))
9d5c8243
AK		 6380 skb->ip_summed = CHECKSUM_UNNECESSARY;
6381
3ceb90fd
AD		 6382 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6383 le32_to_cpu(rx_desc->wb.upper.status_error));
9d5c8243
AK		 6384}
6385
077887c3
AD		 6386static inline void igb_rx_hash(struct igb_ring *ring,
6387 union e1000_adv_rx_desc *rx_desc,
6388 struct sk_buff *skb)
6389{
6390 if (ring->netdev->features & NETIF_F_RXHASH)
6391 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
6392}
6393
2e334eee 6394/**
b980ac18
JK		 6395 * igb_is_non_eop - process handling of non-EOP buffers
6396 * @rx_ring: Rx ring being processed
6397 * @rx_desc: Rx descriptor for current buffer
6398 * @skb: current socket buffer containing buffer in progress
2e334eee 6399 *
b980ac18
JK		 6400 * This function updates next to clean. If the buffer is an EOP buffer
6401 * this function exits returning false, otherwise it will place the
6402 * sk_buff in the next buffer to be chained and return true indicating
6403 * that this is in fact a non-EOP buffer.
2e334eee
AD		 6404 **/
6405static bool igb_is_non_eop(struct igb_ring *rx_ring,
6406 union e1000_adv_rx_desc *rx_desc)
6407{
6408 u32 ntc = rx_ring->next_to_clean + 1;
6409
6410 /* fetch, update, and store next to clean */
6411 ntc = (ntc < rx_ring->count) ? ntc : 0;
6412 rx_ring->next_to_clean = ntc;
6413
6414 prefetch(IGB_RX_DESC(rx_ring, ntc));
6415
6416 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6417 return false;
6418
6419 return true;
6420}
6421
1a1c225b 6422/**
b980ac18
JK		 6423 * igb_get_headlen - determine size of header for LRO/GRO
6424 * @data: pointer to the start of the headers
6425 * @max_len: total length of section to find headers in
1a1c225b 6426 *
b980ac18
JK		 6427 * This function is meant to determine the length of headers that will
6428 * be recognized by hardware for LRO, and GRO offloads. The main
6429 * motivation of doing this is to only perform one pull for IPv4 TCP
6430 * packets so that we can do basic things like calculating the gso_size
6431 * based on the average data per packet.
1a1c225b
AD		 6432 **/
6433static unsigned int igb_get_headlen(unsigned char *data,
6434 unsigned int max_len)
6435{
6436 union {
6437 unsigned char *network;
6438 /* l2 headers */
6439 struct ethhdr *eth;
6440 struct vlan_hdr *vlan;
6441 /* l3 headers */
6442 struct iphdr *ipv4;
6443 struct ipv6hdr *ipv6;
6444 } hdr;
6445 __be16 protocol;
6446 u8 nexthdr = 0; /* default to not TCP */
6447 u8 hlen;
6448
6449 /* this should never happen, but better safe than sorry */
6450 if (max_len < ETH_HLEN)
6451 return max_len;
6452
6453 /* initialize network frame pointer */
6454 hdr.network = data;
6455
6456 /* set first protocol and move network header forward */
6457 protocol = hdr.eth->h_proto;
6458 hdr.network += ETH_HLEN;
6459
6460 /* handle any vlan tag if present */
6461 if (protocol == __constant_htons(ETH_P_8021Q)) {
6462 if ((hdr.network - data) > (max_len - VLAN_HLEN))
6463 return max_len;
6464
6465 protocol = hdr.vlan->h_vlan_encapsulated_proto;
6466 hdr.network += VLAN_HLEN;
6467 }
6468
6469 /* handle L3 protocols */
6470 if (protocol == __constant_htons(ETH_P_IP)) {
6471 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
6472 return max_len;
6473
6474 /* access ihl as a u8 to avoid unaligned access on ia64 */
6475 hlen = (hdr.network[0] & 0x0F) << 2;
6476
6477 /* verify hlen meets minimum size requirements */
6478 if (hlen < sizeof(struct iphdr))
6479 return hdr.network - data;
6480
f2fb4ab2 6481 /* record next protocol if header is present */
b9555f66 6482 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET)))
f2fb4ab2 6483 nexthdr = hdr.ipv4->protocol;
1a1c225b
AD		 6484 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
6485 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
6486 return max_len;
6487
6488 /* record next protocol */
6489 nexthdr = hdr.ipv6->nexthdr;
f2fb4ab2 6490 hlen = sizeof(struct ipv6hdr);
1a1c225b
AD		 6491 } else {
6492 return hdr.network - data;
6493 }
6494
f2fb4ab2
AD		 6495 /* relocate pointer to start of L4 header */
6496 hdr.network += hlen;
6497
1a1c225b
AD		 6498 /* finally sort out TCP */
6499 if (nexthdr == IPPROTO_TCP) {
6500 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
6501 return max_len;
6502
6503 /* access doff as a u8 to avoid unaligned access on ia64 */
6504 hlen = (hdr.network[12] & 0xF0) >> 2;
6505
6506 /* verify hlen meets minimum size requirements */
6507 if (hlen < sizeof(struct tcphdr))
6508 return hdr.network - data;
6509
6510 hdr.network += hlen;
6511 } else if (nexthdr == IPPROTO_UDP) {
6512 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
6513 return max_len;
6514
6515 hdr.network += sizeof(struct udphdr);
6516 }
6517
b980ac18 6518 /* If everything has gone correctly hdr.network should be the
1a1c225b
AD		 6519 * data section of the packet and will be the end of the header.
6520 * If not then it probably represents the end of the last recognized
6521 * header.
6522 */
6523 if ((hdr.network - data) < max_len)
6524 return hdr.network - data;
6525 else
6526 return max_len;
6527}
6528
6529/**
b980ac18
JK		 6530 * igb_pull_tail - igb specific version of skb_pull_tail
6531 * @rx_ring: rx descriptor ring packet is being transacted on
6532 * @rx_desc: pointer to the EOP Rx descriptor
6533 * @skb: pointer to current skb being adjusted
1a1c225b 6534 *
b980ac18
JK		 6535 * This function is an igb specific version of __pskb_pull_tail. The
6536 * main difference between this version and the original function is that
6537 * this function can make several assumptions about the state of things
6538 * that allow for significant optimizations versus the standard function.
6539 * As a result we can do things like drop a frag and maintain an accurate
6540 * truesize for the skb.
1a1c225b
AD		 6541 */
6542static void igb_pull_tail(struct igb_ring *rx_ring,
6543 union e1000_adv_rx_desc *rx_desc,
6544 struct sk_buff *skb)
2d94d8ab 6545{
1a1c225b
AD		 6546 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6547 unsigned char *va;
6548 unsigned int pull_len;
6549
b980ac18 6550 /* it is valid to use page_address instead of kmap since we are
1a1c225b
AD		 6551 * working with pages allocated out of the lomem pool per
6552 * alloc_page(GFP_ATOMIC)
2d94d8ab 6553 */
1a1c225b
AD		 6554 va = skb_frag_address(frag);
6555
1a1c225b
AD		 6556 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6557 /* retrieve timestamp from buffer */
6558 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6559
6560 /* update pointers to remove timestamp header */
6561 skb_frag_size_sub(frag, IGB_TS_HDR_LEN);
6562 frag->page_offset += IGB_TS_HDR_LEN;
6563 skb->data_len -= IGB_TS_HDR_LEN;
6564 skb->len -= IGB_TS_HDR_LEN;
6565
6566 /* move va to start of packet data */
6567 va += IGB_TS_HDR_LEN;
6568 }
6569
b980ac18 6570 /* we need the header to contain the greater of either ETH_HLEN or
1a1c225b
AD		 6571 * 60 bytes if the skb->len is less than 60 for skb_pad.
6572 */
6573 pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN);
6574
6575 /* align pull length to size of long to optimize memcpy performance */
6576 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
6577
6578 /* update all of the pointers */
6579 skb_frag_size_sub(frag, pull_len);
6580 frag->page_offset += pull_len;
6581 skb->data_len -= pull_len;
6582 skb->tail += pull_len;
6583}
6584
6585/**
b980ac18
JK		 6586 * igb_cleanup_headers - Correct corrupted or empty headers
6587 * @rx_ring: rx descriptor ring packet is being transacted on
6588 * @rx_desc: pointer to the EOP Rx descriptor
6589 * @skb: pointer to current skb being fixed
1a1c225b 6590 *
b980ac18
JK		 6591 * Address the case where we are pulling data in on pages only
6592 * and as such no data is present in the skb header.
1a1c225b 6593 *
b980ac18
JK		 6594 * In addition if skb is not at least 60 bytes we need to pad it so that
6595 * it is large enough to qualify as a valid Ethernet frame.
1a1c225b 6596 *
b980ac18 6597 * Returns true if an error was encountered and skb was freed.
1a1c225b
AD		 6598 **/
6599static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6600 union e1000_adv_rx_desc *rx_desc,
6601 struct sk_buff *skb)
6602{
1a1c225b
AD		 6603 if (unlikely((igb_test_staterr(rx_desc,
6604 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6605 struct net_device *netdev = rx_ring->netdev;
6606 if (!(netdev->features & NETIF_F_RXALL)) {
6607 dev_kfree_skb_any(skb);
6608 return true;
6609 }
6610 }
6611
6612 /* place header in linear portion of buffer */
6613 if (skb_is_nonlinear(skb))
6614 igb_pull_tail(rx_ring, rx_desc, skb);
6615
6616 /* if skb_pad returns an error the skb was freed */
6617 if (unlikely(skb->len < 60)) {
6618 int pad_len = 60 - skb->len;
6619
6620 if (skb_pad(skb, pad_len))
6621 return true;
6622 __skb_put(skb, pad_len);
6623 }
6624
6625 return false;
2d94d8ab
AD		 6626}
6627
db2ee5bd 6628/**
b980ac18
JK		 6629 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6630 * @rx_ring: rx descriptor ring packet is being transacted on
6631 * @rx_desc: pointer to the EOP Rx descriptor
6632 * @skb: pointer to current skb being populated
db2ee5bd 6633 *
b980ac18
JK		 6634 * This function checks the ring, descriptor, and packet information in
6635 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6636 * other fields within the skb.
db2ee5bd
AD		 6637 **/
6638static void igb_process_skb_fields(struct igb_ring *rx_ring,
6639 union e1000_adv_rx_desc *rx_desc,
6640 struct sk_buff *skb)
6641{
6642 struct net_device *dev = rx_ring->netdev;
6643
6644 igb_rx_hash(rx_ring, rx_desc, skb);
6645
6646 igb_rx_checksum(rx_ring, rx_desc, skb);
6647
20a48412 6648 igb_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
db2ee5bd 6649
f646968f 6650 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
db2ee5bd
AD		 6651 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6652 u16 vid;
6653 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6654 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6655 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6656 else
6657 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6658
86a9bad3 6659 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
db2ee5bd
AD		 6660 }
6661
6662 skb_record_rx_queue(skb, rx_ring->queue_index);
6663
6664 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6665}
6666
2e334eee 6667static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
9d5c8243 6668{
0ba82994 6669 struct igb_ring *rx_ring = q_vector->rx.ring;
1a1c225b 6670 struct sk_buff *skb = rx_ring->skb;
9d5c8243 6671 unsigned int total_bytes = 0, total_packets = 0;
16eb8815 6672 u16 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243 6673
2e334eee
AD		 6674 do {
6675 union e1000_adv_rx_desc *rx_desc;
bf36c1a0 6676
2e334eee
AD		 6677 /* return some buffers to hardware, one at a time is too slow */
6678 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6679 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6680 cleaned_count = 0;
6681 }
bf36c1a0 6682
2e334eee 6683 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
16eb8815 6684
2e334eee
AD		 6685 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD))
6686 break;
9d5c8243 6687
74e238ea
AD		 6688 /* This memory barrier is needed to keep us from reading
6689 * any other fields out of the rx_desc until we know the
6690 * RXD_STAT_DD bit is set
6691 */
6692 rmb();
6693
2e334eee 6694 /* retrieve a buffer from the ring */
f9d40f6a 6695 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
9d5c8243 6696
2e334eee
AD		 6697 /* exit if we failed to retrieve a buffer */
6698 if (!skb)
6699 break;
1a1c225b 6700
2e334eee 6701 cleaned_count++;
1a1c225b 6702
2e334eee
AD		 6703 /* fetch next buffer in frame if non-eop */
6704 if (igb_is_non_eop(rx_ring, rx_desc))
6705 continue;
1a1c225b
AD		 6706
6707 /* verify the packet layout is correct */
6708 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
6709 skb = NULL;
6710 continue;
9d5c8243 6711 }
9d5c8243 6712
db2ee5bd 6713 /* probably a little skewed due to removing CRC */
3ceb90fd 6714 total_bytes += skb->len;
3ceb90fd 6715
db2ee5bd
AD		 6716 /* populate checksum, timestamp, VLAN, and protocol */
6717 igb_process_skb_fields(rx_ring, rx_desc, skb);
3ceb90fd 6718
b2cb09b1 6719 napi_gro_receive(&q_vector->napi, skb);
9d5c8243 6720
1a1c225b
AD		 6721 /* reset skb pointer */
6722 skb = NULL;
6723
2e334eee
AD		 6724 /* update budget accounting */
6725 total_packets++;
6726 } while (likely(total_packets < budget));
bf36c1a0 6727
1a1c225b
AD		 6728 /* place incomplete frames back on ring for completion */
6729 rx_ring->skb = skb;
6730
12dcd86b 6731 u64_stats_update_begin(&rx_ring->rx_syncp);
9d5c8243
AK		 6732 rx_ring->rx_stats.packets += total_packets;
6733 rx_ring->rx_stats.bytes += total_bytes;
12dcd86b 6734 u64_stats_update_end(&rx_ring->rx_syncp);
0ba82994
AD		 6735 q_vector->rx.total_packets += total_packets;
6736 q_vector->rx.total_bytes += total_bytes;
c023cd88
AD		 6737
6738 if (cleaned_count)
cd392f5c 6739 igb_alloc_rx_buffers(rx_ring, cleaned_count);
c023cd88 6740
2e334eee 6741 return (total_packets < budget);
9d5c8243
AK		 6742}
6743
c023cd88 6744static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
06034649 6745 struct igb_rx_buffer *bi)
c023cd88
AD		 6746{
6747 struct page *page = bi->page;
cbc8e55f 6748 dma_addr_t dma;
c023cd88 6749
cbc8e55f
AD		 6750 /* since we are recycling buffers we should seldom need to alloc */
6751 if (likely(page))
c023cd88
AD		 6752 return true;
6753
cbc8e55f
AD		 6754 /* alloc new page for storage */
6755 page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL);
6756 if (unlikely(!page)) {
6757 rx_ring->rx_stats.alloc_failed++;
6758 return false;
c023cd88
AD		 6759 }
6760
cbc8e55f
AD		 6761 /* map page for use */
6762 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
c023cd88 6763
b980ac18 6764 /* if mapping failed free memory back to system since
cbc8e55f
AD		 6765 * there isn't much point in holding memory we can't use
6766 */
1a1c225b 6767 if (dma_mapping_error(rx_ring->dev, dma)) {
cbc8e55f
AD		 6768 __free_page(page);
6769
c023cd88
AD		 6770 rx_ring->rx_stats.alloc_failed++;
6771 return false;
6772 }
6773
1a1c225b 6774 bi->dma = dma;
cbc8e55f
AD		 6775 bi->page = page;
6776 bi->page_offset = 0;
1a1c225b 6777
c023cd88
AD		 6778 return true;
6779}
6780
9d5c8243 6781/**
b980ac18
JK		 6782 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
6783 * @adapter: address of board private structure
9d5c8243 6784 **/
cd392f5c 6785void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
9d5c8243 6786{
9d5c8243 6787 union e1000_adv_rx_desc *rx_desc;
06034649 6788 struct igb_rx_buffer *bi;
c023cd88 6789 u16 i = rx_ring->next_to_use;
9d5c8243 6790
cbc8e55f
AD		 6791 /* nothing to do */
6792 if (!cleaned_count)
6793 return;
6794
60136906 6795 rx_desc = IGB_RX_DESC(rx_ring, i);
06034649 6796 bi = &rx_ring->rx_buffer_info[i];
c023cd88 6797 i -= rx_ring->count;
9d5c8243 6798
cbc8e55f 6799 do {
1a1c225b 6800 if (!igb_alloc_mapped_page(rx_ring, bi))
c023cd88 6801 break;
9d5c8243 6802
b980ac18 6803 /* Refresh the desc even if buffer_addrs didn't change
cbc8e55f
AD		 6804 * because each write-back erases this info.
6805 */
f9d40f6a 6806 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9d5c8243 6807
c023cd88
AD		 6808 rx_desc++;
6809 bi++;
9d5c8243 6810 i++;
c023cd88 6811 if (unlikely(!i)) {
60136906 6812 rx_desc = IGB_RX_DESC(rx_ring, 0);
06034649 6813 bi = rx_ring->rx_buffer_info;
c023cd88
AD		 6814 i -= rx_ring->count;
6815 }
6816
6817 /* clear the hdr_addr for the next_to_use descriptor */
6818 rx_desc->read.hdr_addr = 0;
cbc8e55f
AD		 6819
6820 cleaned_count--;
6821 } while (cleaned_count);
9d5c8243 6822
c023cd88
AD		 6823 i += rx_ring->count;
6824
9d5c8243 6825 if (rx_ring->next_to_use != i) {
cbc8e55f 6826 /* record the next descriptor to use */
9d5c8243 6827 rx_ring->next_to_use = i;
9d5c8243 6828
cbc8e55f
AD		 6829 /* update next to alloc since we have filled the ring */
6830 rx_ring->next_to_alloc = i;
6831
b980ac18 6832 /* Force memory writes to complete before letting h/w
9d5c8243
AK		 6833 * know there are new descriptors to fetch. (Only
6834 * applicable for weak-ordered memory model archs,
cbc8e55f
AD		 6835 * such as IA-64).
6836 */
9d5c8243 6837 wmb();
fce99e34 6838 writel(i, rx_ring->tail);
9d5c8243
AK		 6839 }
6840}
6841
6842/**
6843 * igb_mii_ioctl -
6844 * @netdev:
6845 * @ifreq:
6846 * @cmd:
6847 **/
6848static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6849{
6850 struct igb_adapter *adapter = netdev_priv(netdev);
6851 struct mii_ioctl_data *data = if_mii(ifr);
6852
6853 if (adapter->hw.phy.media_type != e1000_media_type_copper)
6854 return -EOPNOTSUPP;
6855
6856 switch (cmd) {
6857 case SIOCGMIIPHY:
6858 data->phy_id = adapter->hw.phy.addr;
6859 break;
6860 case SIOCGMIIREG:
f5f4cf08
AD		 6861 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
6862 &data->val_out))
9d5c8243
AK		 6863 return -EIO;
6864 break;
6865 case SIOCSMIIREG:
6866 default:
6867 return -EOPNOTSUPP;
6868 }
6869 return 0;
6870}
6871
6872/**
6873 * igb_ioctl -
6874 * @netdev:
6875 * @ifreq:
6876 * @cmd:
6877 **/
6878static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6879{
6880 switch (cmd) {
6881 case SIOCGMIIPHY:
6882 case SIOCGMIIREG:
6883 case SIOCSMIIREG:
6884 return igb_mii_ioctl(netdev, ifr, cmd);
c6cb090b 6885 case SIOCSHWTSTAMP:
a79f4f88 6886 return igb_ptp_hwtstamp_ioctl(netdev, ifr, cmd);
9d5c8243
AK		 6887 default:
6888 return -EOPNOTSUPP;
6889 }
6890}
6891
009bc06e
AD		 6892s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6893{
6894 struct igb_adapter *adapter = hw->back;
009bc06e 6895
23d028cc 6896 if (pcie_capability_read_word(adapter->pdev, reg, value))
009bc06e
AD		 6897 return -E1000_ERR_CONFIG;
6898
009bc06e
AD		 6899 return 0;
6900}
6901
6902s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6903{
6904 struct igb_adapter *adapter = hw->back;
009bc06e 6905
23d028cc 6906 if (pcie_capability_write_word(adapter->pdev, reg, *value))
009bc06e
AD		 6907 return -E1000_ERR_CONFIG;
6908
009bc06e
AD		 6909 return 0;
6910}
6911
c8f44aff 6912static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
9d5c8243
AK		 6913{
6914 struct igb_adapter *adapter = netdev_priv(netdev);
6915 struct e1000_hw *hw = &adapter->hw;
6916 u32 ctrl, rctl;
f646968f 6917 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
9d5c8243 6918
5faf030c 6919 if (enable) {
9d5c8243
AK		 6920 /* enable VLAN tag insert/strip */
6921 ctrl = rd32(E1000_CTRL);
6922 ctrl |= E1000_CTRL_VME;
6923 wr32(E1000_CTRL, ctrl);
6924
51466239 6925 /* Disable CFI check */
9d5c8243 6926 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 6927 rctl &= ~E1000_RCTL_CFIEN;
6928 wr32(E1000_RCTL, rctl);
9d5c8243
AK		 6929 } else {
6930 /* disable VLAN tag insert/strip */
6931 ctrl = rd32(E1000_CTRL);
6932 ctrl &= ~E1000_CTRL_VME;
6933 wr32(E1000_CTRL, ctrl);
9d5c8243
AK		 6934 }
6935
e1739522 6936 igb_rlpml_set(adapter);
9d5c8243
AK		 6937}
6938
80d5c368
PM		 6939static int igb_vlan_rx_add_vid(struct net_device *netdev,
6940 __be16 proto, u16 vid)
9d5c8243
AK		 6941{
6942 struct igb_adapter *adapter = netdev_priv(netdev);
6943 struct e1000_hw *hw = &adapter->hw;
4ae196df 6944 int pf_id = adapter->vfs_allocated_count;
9d5c8243 6945
51466239
AD		 6946 /* attempt to add filter to vlvf array */
6947 igb_vlvf_set(adapter, vid, true, pf_id);
4ae196df 6948
51466239
AD		 6949 /* add the filter since PF can receive vlans w/o entry in vlvf */
6950 igb_vfta_set(hw, vid, true);
b2cb09b1
JP		 6951
6952 set_bit(vid, adapter->active_vlans);
8e586137
JP		 6953
6954 return 0;
9d5c8243
AK		 6955}
6956
80d5c368
PM		 6957static int igb_vlan_rx_kill_vid(struct net_device *netdev,
6958 __be16 proto, u16 vid)
9d5c8243
AK		 6959{
6960 struct igb_adapter *adapter = netdev_priv(netdev);
6961 struct e1000_hw *hw = &adapter->hw;
4ae196df 6962 int pf_id = adapter->vfs_allocated_count;
51466239 6963 s32 err;
9d5c8243 6964
51466239
AD		 6965 /* remove vlan from VLVF table array */
6966 err = igb_vlvf_set(adapter, vid, false, pf_id);
9d5c8243 6967
51466239
AD		 6968 /* if vid was not present in VLVF just remove it from table */
6969 if (err)
4ae196df 6970 igb_vfta_set(hw, vid, false);
b2cb09b1
JP		 6971
6972 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 6973
6974 return 0;
9d5c8243
AK		 6975}
6976
6977static void igb_restore_vlan(struct igb_adapter *adapter)
6978{
b2cb09b1 6979 u16 vid;
9d5c8243 6980
5faf030c
AD		 6981 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
6982
b2cb09b1 6983 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 6984 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9d5c8243
AK		 6985}
6986
14ad2513 6987int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9d5c8243 6988{
090b1795 6989 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 6990 struct e1000_mac_info *mac = &adapter->hw.mac;
6991
6992 mac->autoneg = 0;
6993
14ad2513 6994 /* Make sure dplx is at most 1 bit and lsb of speed is not set
b980ac18
JK		 6995 * for the switch() below to work
6996 */
14ad2513
DD		 6997 if ((spd & 1) || (dplx & ~1))
6998 goto err_inval;
6999
f502ef7d
AA		 7000 /* Fiber NIC's only allow 1000 gbps Full duplex
7001 * and 100Mbps Full duplex for 100baseFx sfp
7002 */
7003 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
7004 switch (spd + dplx) {
7005 case SPEED_10 + DUPLEX_HALF:
7006 case SPEED_10 + DUPLEX_FULL:
7007 case SPEED_100 + DUPLEX_HALF:
7008 goto err_inval;
7009 default:
7010 break;
7011 }
7012 }
cd2638a8 7013
14ad2513 7014 switch (spd + dplx) {
9d5c8243
AK		 7015 case SPEED_10 + DUPLEX_HALF:
7016 mac->forced_speed_duplex = ADVERTISE_10_HALF;
7017 break;
7018 case SPEED_10 + DUPLEX_FULL:
7019 mac->forced_speed_duplex = ADVERTISE_10_FULL;
7020 break;
7021 case SPEED_100 + DUPLEX_HALF:
7022 mac->forced_speed_duplex = ADVERTISE_100_HALF;
7023 break;
7024 case SPEED_100 + DUPLEX_FULL:
7025 mac->forced_speed_duplex = ADVERTISE_100_FULL;
7026 break;
7027 case SPEED_1000 + DUPLEX_FULL:
7028 mac->autoneg = 1;
7029 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7030 break;
7031 case SPEED_1000 + DUPLEX_HALF: /* not supported */
7032 default:
14ad2513 7033 goto err_inval;
9d5c8243 7034 }
8376dad0
JB		 7035
7036 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7037 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7038
9d5c8243 7039 return 0;
14ad2513
DD		 7040
7041err_inval:
7042 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7043 return -EINVAL;
9d5c8243
AK		 7044}
7045
749ab2cd
YZ		 7046static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7047 bool runtime)
9d5c8243
AK		 7048{
7049 struct net_device *netdev = pci_get_drvdata(pdev);
7050 struct igb_adapter *adapter = netdev_priv(netdev);
7051 struct e1000_hw *hw = &adapter->hw;
2d064c06 7052 u32 ctrl, rctl, status;
749ab2cd 7053 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
9d5c8243
AK		 7054#ifdef CONFIG_PM
7055 int retval = 0;
7056#endif
7057
7058 netif_device_detach(netdev);
7059
a88f10ec 7060 if (netif_running(netdev))
749ab2cd 7061 __igb_close(netdev, true);
a88f10ec 7062
047e0030 7063 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 7064
7065#ifdef CONFIG_PM
7066 retval = pci_save_state(pdev);
7067 if (retval)
7068 return retval;
7069#endif
7070
7071 status = rd32(E1000_STATUS);
7072 if (status & E1000_STATUS_LU)
7073 wufc &= ~E1000_WUFC_LNKC;
7074
7075 if (wufc) {
7076 igb_setup_rctl(adapter);
ff41f8dc 7077 igb_set_rx_mode(netdev);
9d5c8243
AK		 7078
7079 /* turn on all-multi mode if wake on multicast is enabled */
7080 if (wufc & E1000_WUFC_MC) {
7081 rctl = rd32(E1000_RCTL);
7082 rctl |= E1000_RCTL_MPE;
7083 wr32(E1000_RCTL, rctl);
7084 }
7085
7086 ctrl = rd32(E1000_CTRL);
7087 /* advertise wake from D3Cold */
7088 #define E1000_CTRL_ADVD3WUC 0x00100000
7089 /* phy power management enable */
7090 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7091 ctrl |= E1000_CTRL_ADVD3WUC;
7092 wr32(E1000_CTRL, ctrl);
7093
9d5c8243 7094 /* Allow time for pending master requests to run */
330a6d6a 7095 igb_disable_pcie_master(hw);
9d5c8243
AK		 7096
7097 wr32(E1000_WUC, E1000_WUC_PME_EN);
7098 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 7099 } else {
7100 wr32(E1000_WUC, 0);
7101 wr32(E1000_WUFC, 0);
9d5c8243
AK		 7102 }
7103
3fe7c4c9
RW		 7104 *enable_wake = wufc || adapter->en_mng_pt;
7105 if (!*enable_wake)
88a268c1
NN		 7106 igb_power_down_link(adapter);
7107 else
7108 igb_power_up_link(adapter);
9d5c8243
AK		 7109
7110 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 7111 * would have already happened in close and is redundant.
7112 */
9d5c8243
AK		 7113 igb_release_hw_control(adapter);
7114
7115 pci_disable_device(pdev);
7116
9d5c8243
AK		 7117 return 0;
7118}
7119
7120#ifdef CONFIG_PM
d9dd966d 7121#ifdef CONFIG_PM_SLEEP
749ab2cd 7122static int igb_suspend(struct device *dev)
3fe7c4c9
RW		 7123{
7124 int retval;
7125 bool wake;
749ab2cd 7126 struct pci_dev *pdev = to_pci_dev(dev);
3fe7c4c9 7127
749ab2cd 7128 retval = __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7129 if (retval)
7130 return retval;
7131
7132 if (wake) {
7133 pci_prepare_to_sleep(pdev);
7134 } else {
7135 pci_wake_from_d3(pdev, false);
7136 pci_set_power_state(pdev, PCI_D3hot);
7137 }
7138
7139 return 0;
7140}
d9dd966d 7141#endif /* CONFIG_PM_SLEEP */
3fe7c4c9 7142
749ab2cd 7143static int igb_resume(struct device *dev)
9d5c8243 7144{
749ab2cd 7145 struct pci_dev *pdev = to_pci_dev(dev);
9d5c8243
AK		 7146 struct net_device *netdev = pci_get_drvdata(pdev);
7147 struct igb_adapter *adapter = netdev_priv(netdev);
7148 struct e1000_hw *hw = &adapter->hw;
7149 u32 err;
7150
7151 pci_set_power_state(pdev, PCI_D0);
7152 pci_restore_state(pdev);
b94f2d77 7153 pci_save_state(pdev);
42bfd33a 7154
aed5dec3 7155 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 7156 if (err) {
7157 dev_err(&pdev->dev,
7158 "igb: Cannot enable PCI device from suspend\n");
7159 return err;
7160 }
7161 pci_set_master(pdev);
7162
7163 pci_enable_wake(pdev, PCI_D3hot, 0);
7164 pci_enable_wake(pdev, PCI_D3cold, 0);
7165
53c7d064 7166 if (igb_init_interrupt_scheme(adapter, true)) {
a88f10ec
AD		 7167 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7168 return -ENOMEM;
9d5c8243
AK		 7169 }
7170
9d5c8243 7171 igb_reset(adapter);
a8564f03
AD		 7172
7173 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7174 * driver.
7175 */
a8564f03
AD		 7176 igb_get_hw_control(adapter);
7177
9d5c8243
AK		 7178 wr32(E1000_WUS, ~0);
7179
749ab2cd 7180 if (netdev->flags & IFF_UP) {
0c2cc02e 7181 rtnl_lock();
749ab2cd 7182 err = __igb_open(netdev, true);
0c2cc02e 7183 rtnl_unlock();
a88f10ec
AD		 7184 if (err)
7185 return err;
7186 }
9d5c8243
AK		 7187
7188 netif_device_attach(netdev);
749ab2cd
YZ		 7189 return 0;
7190}
7191
7192#ifdef CONFIG_PM_RUNTIME
7193static int igb_runtime_idle(struct device *dev)
7194{
7195 struct pci_dev *pdev = to_pci_dev(dev);
7196 struct net_device *netdev = pci_get_drvdata(pdev);
7197 struct igb_adapter *adapter = netdev_priv(netdev);
7198
7199 if (!igb_has_link(adapter))
7200 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7201
7202 return -EBUSY;
7203}
7204
7205static int igb_runtime_suspend(struct device *dev)
7206{
7207 struct pci_dev *pdev = to_pci_dev(dev);
7208 int retval;
7209 bool wake;
7210
7211 retval = __igb_shutdown(pdev, &wake, 1);
7212 if (retval)
7213 return retval;
7214
7215 if (wake) {
7216 pci_prepare_to_sleep(pdev);
7217 } else {
7218 pci_wake_from_d3(pdev, false);
7219 pci_set_power_state(pdev, PCI_D3hot);
7220 }
9d5c8243 7221
9d5c8243
AK		 7222 return 0;
7223}
749ab2cd
YZ		 7224
7225static int igb_runtime_resume(struct device *dev)
7226{
7227 return igb_resume(dev);
7228}
7229#endif /* CONFIG_PM_RUNTIME */
9d5c8243
AK		 7230#endif
7231
7232static void igb_shutdown(struct pci_dev *pdev)
7233{
3fe7c4c9
RW		 7234 bool wake;
7235
749ab2cd 7236 __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7237
7238 if (system_state == SYSTEM_POWER_OFF) {
7239 pci_wake_from_d3(pdev, wake);
7240 pci_set_power_state(pdev, PCI_D3hot);
7241 }
9d5c8243
AK		 7242}
7243
fa44f2f1
GR		 7244#ifdef CONFIG_PCI_IOV
7245static int igb_sriov_reinit(struct pci_dev *dev)
7246{
7247 struct net_device *netdev = pci_get_drvdata(dev);
7248 struct igb_adapter *adapter = netdev_priv(netdev);
7249 struct pci_dev *pdev = adapter->pdev;
7250
7251 rtnl_lock();
7252
7253 if (netif_running(netdev))
7254 igb_close(netdev);
7255
7256 igb_clear_interrupt_scheme(adapter);
7257
7258 igb_init_queue_configuration(adapter);
7259
7260 if (igb_init_interrupt_scheme(adapter, true)) {
7261 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7262 return -ENOMEM;
7263 }
7264
7265 if (netif_running(netdev))
7266 igb_open(netdev);
7267
7268 rtnl_unlock();
7269
7270 return 0;
7271}
7272
7273static int igb_pci_disable_sriov(struct pci_dev *dev)
7274{
7275 int err = igb_disable_sriov(dev);
7276
7277 if (!err)
7278 err = igb_sriov_reinit(dev);
7279
7280 return err;
7281}
7282
7283static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7284{
7285 int err = igb_enable_sriov(dev, num_vfs);
7286
7287 if (err)
7288 goto out;
7289
7290 err = igb_sriov_reinit(dev);
7291 if (!err)
7292 return num_vfs;
7293
7294out:
7295 return err;
7296}
7297
7298#endif
7299static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7300{
7301#ifdef CONFIG_PCI_IOV
7302 if (num_vfs == 0)
7303 return igb_pci_disable_sriov(dev);
7304 else
7305 return igb_pci_enable_sriov(dev, num_vfs);
7306#endif
7307 return 0;
7308}
7309
9d5c8243 7310#ifdef CONFIG_NET_POLL_CONTROLLER
b980ac18 7311/* Polling 'interrupt' - used by things like netconsole to send skbs
9d5c8243
AK		 7312 * without having to re-enable interrupts. It's not called while
7313 * the interrupt routine is executing.
7314 */
7315static void igb_netpoll(struct net_device *netdev)
7316{
7317 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 7318 struct e1000_hw *hw = &adapter->hw;
0d1ae7f4 7319 struct igb_q_vector *q_vector;
9d5c8243 7320 int i;
9d5c8243 7321
047e0030 7322 for (i = 0; i < adapter->num_q_vectors; i++) {
0d1ae7f4
AD		 7323 q_vector = adapter->q_vector[i];
7324 if (adapter->msix_entries)
7325 wr32(E1000_EIMC, q_vector->eims_value);
7326 else
7327 igb_irq_disable(adapter);
047e0030 7328 napi_schedule(&q_vector->napi);
eebbbdba 7329 }
9d5c8243
AK		 7330}
7331#endif /* CONFIG_NET_POLL_CONTROLLER */
7332
7333/**
b980ac18
JK		 7334 * igb_io_error_detected - called when PCI error is detected
7335 * @pdev: Pointer to PCI device
7336 * @state: The current pci connection state
9d5c8243 7337 *
b980ac18
JK		 7338 * This function is called after a PCI bus error affecting
7339 * this device has been detected.
7340 **/
9d5c8243
AK		 7341static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7342 pci_channel_state_t state)
7343{
7344 struct net_device *netdev = pci_get_drvdata(pdev);
7345 struct igb_adapter *adapter = netdev_priv(netdev);
7346
7347 netif_device_detach(netdev);
7348
59ed6eec
AD		 7349 if (state == pci_channel_io_perm_failure)
7350 return PCI_ERS_RESULT_DISCONNECT;
7351
9d5c8243
AK		 7352 if (netif_running(netdev))
7353 igb_down(adapter);
7354 pci_disable_device(pdev);
7355
7356 /* Request a slot slot reset. */
7357 return PCI_ERS_RESULT_NEED_RESET;
7358}
7359
7360/**
b980ac18
JK		 7361 * igb_io_slot_reset - called after the pci bus has been reset.
7362 * @pdev: Pointer to PCI device
9d5c8243 7363 *
b980ac18
JK		 7364 * Restart the card from scratch, as if from a cold-boot. Implementation
7365 * resembles the first-half of the igb_resume routine.
7366 **/
9d5c8243
AK		 7367static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7368{
7369 struct net_device *netdev = pci_get_drvdata(pdev);
7370 struct igb_adapter *adapter = netdev_priv(netdev);
7371 struct e1000_hw *hw = &adapter->hw;
40a914fa 7372 pci_ers_result_t result;
42bfd33a 7373 int err;
9d5c8243 7374
aed5dec3 7375 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 7376 dev_err(&pdev->dev,
7377 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 7378 result = PCI_ERS_RESULT_DISCONNECT;
7379 } else {
7380 pci_set_master(pdev);
7381 pci_restore_state(pdev);
b94f2d77 7382 pci_save_state(pdev);
9d5c8243 7383
40a914fa
AD		 7384 pci_enable_wake(pdev, PCI_D3hot, 0);
7385 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 7386
40a914fa
AD		 7387 igb_reset(adapter);
7388 wr32(E1000_WUS, ~0);
7389 result = PCI_ERS_RESULT_RECOVERED;
7390 }
9d5c8243 7391
ea943d41
JK		 7392 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7393 if (err) {
b980ac18
JK		 7394 dev_err(&pdev->dev,
7395 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7396 err);
ea943d41
JK		 7397 /* non-fatal, continue */
7398 }
40a914fa
AD		 7399
7400 return result;
9d5c8243
AK		 7401}
7402
7403/**
b980ac18
JK		 7404 * igb_io_resume - called when traffic can start flowing again.
7405 * @pdev: Pointer to PCI device
9d5c8243 7406 *
b980ac18
JK		 7407 * This callback is called when the error recovery driver tells us that
7408 * its OK to resume normal operation. Implementation resembles the
7409 * second-half of the igb_resume routine.
9d5c8243
AK		 7410 */
7411static void igb_io_resume(struct pci_dev *pdev)
7412{
7413 struct net_device *netdev = pci_get_drvdata(pdev);
7414 struct igb_adapter *adapter = netdev_priv(netdev);
7415
9d5c8243
AK		 7416 if (netif_running(netdev)) {
7417 if (igb_up(adapter)) {
7418 dev_err(&pdev->dev, "igb_up failed after reset\n");
7419 return;
7420 }
7421 }
7422
7423 netif_device_attach(netdev);
7424
7425 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7426 * driver.
7427 */
9d5c8243 7428 igb_get_hw_control(adapter);
9d5c8243
AK		 7429}
7430
26ad9178 7431static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
b980ac18 7432 u8 qsel)
26ad9178
AD		 7433{
7434 u32 rar_low, rar_high;
7435 struct e1000_hw *hw = &adapter->hw;
7436
7437 /* HW expects these in little endian so we reverse the byte order
7438 * from network order (big endian) to little endian
7439 */
7440 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
b980ac18 7441 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
26ad9178
AD		 7442 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7443
7444 /* Indicate to hardware the Address is Valid. */
7445 rar_high |= E1000_RAH_AV;
7446
7447 if (hw->mac.type == e1000_82575)
7448 rar_high |= E1000_RAH_POOL_1 * qsel;
7449 else
7450 rar_high |= E1000_RAH_POOL_1 << qsel;
7451
7452 wr32(E1000_RAL(index), rar_low);
7453 wrfl();
7454 wr32(E1000_RAH(index), rar_high);
7455 wrfl();
7456}
7457
4ae196df 7458static int igb_set_vf_mac(struct igb_adapter *adapter,
b980ac18 7459 int vf, unsigned char *mac_addr)
4ae196df
AD		 7460{
7461 struct e1000_hw *hw = &adapter->hw;
ff41f8dc 7462 /* VF MAC addresses start at end of receive addresses and moves
b980ac18
JK		 7463 * towards the first, as a result a collision should not be possible
7464 */
ff41f8dc 7465 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 7466
37680117 7467 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 7468
26ad9178 7469 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 7470
7471 return 0;
7472}
7473
8151d294
WM		 7474static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7475{
7476 struct igb_adapter *adapter = netdev_priv(netdev);
7477 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7478 return -EINVAL;
7479 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7480 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
b980ac18
JK		 7481 dev_info(&adapter->pdev->dev,
7482 "Reload the VF driver to make this change effective.");
8151d294 7483 if (test_bit(__IGB_DOWN, &adapter->state)) {
b980ac18
JK		 7484 dev_warn(&adapter->pdev->dev,
7485 "The VF MAC address has been set, but the PF device is not up.\n");
7486 dev_warn(&adapter->pdev->dev,
7487 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 7488 }
7489 return igb_set_vf_mac(adapter, vf, mac);
7490}
7491
17dc566c
LL		 7492static int igb_link_mbps(int internal_link_speed)
7493{
7494 switch (internal_link_speed) {
7495 case SPEED_100:
7496 return 100;
7497 case SPEED_1000:
7498 return 1000;
7499 default:
7500 return 0;
7501 }
7502}
7503
7504static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7505 int link_speed)
7506{
7507 int rf_dec, rf_int;
7508 u32 bcnrc_val;
7509
7510 if (tx_rate != 0) {
7511 /* Calculate the rate factor values to set */
7512 rf_int = link_speed / tx_rate;
7513 rf_dec = (link_speed - (rf_int * tx_rate));
b980ac18
JK		 7514 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) /
7515 tx_rate;
17dc566c
LL		 7516
7517 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
b980ac18
JK		 7518 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
7519 E1000_RTTBCNRC_RF_INT_MASK);
17dc566c
LL		 7520 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7521 } else {
7522 bcnrc_val = 0;
7523 }
7524
7525 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
b980ac18 7526 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
f00b0da7
LL		 7527 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7528 */
7529 wr32(E1000_RTTBCNRM, 0x14);
17dc566c
LL		 7530 wr32(E1000_RTTBCNRC, bcnrc_val);
7531}
7532
7533static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7534{
7535 int actual_link_speed, i;
7536 bool reset_rate = false;
7537
7538 /* VF TX rate limit was not set or not supported */
7539 if ((adapter->vf_rate_link_speed == 0) ||
7540 (adapter->hw.mac.type != e1000_82576))
7541 return;
7542
7543 actual_link_speed = igb_link_mbps(adapter->link_speed);
7544 if (actual_link_speed != adapter->vf_rate_link_speed) {
7545 reset_rate = true;
7546 adapter->vf_rate_link_speed = 0;
7547 dev_info(&adapter->pdev->dev,
b980ac18 7548 "Link speed has been changed. VF Transmit rate is disabled\n");
17dc566c
LL		 7549 }
7550
7551 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7552 if (reset_rate)
7553 adapter->vf_data[i].tx_rate = 0;
7554
7555 igb_set_vf_rate_limit(&adapter->hw, i,
b980ac18
JK		 7556 adapter->vf_data[i].tx_rate,
7557 actual_link_speed);
17dc566c
LL		 7558 }
7559}
7560
8151d294
WM		 7561static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
7562{
17dc566c
LL		 7563 struct igb_adapter *adapter = netdev_priv(netdev);
7564 struct e1000_hw *hw = &adapter->hw;
7565 int actual_link_speed;
7566
7567 if (hw->mac.type != e1000_82576)
7568 return -EOPNOTSUPP;
7569
7570 actual_link_speed = igb_link_mbps(adapter->link_speed);
7571 if ((vf >= adapter->vfs_allocated_count) ||
7572 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
7573 (tx_rate < 0) || (tx_rate > actual_link_speed))
7574 return -EINVAL;
7575
7576 adapter->vf_rate_link_speed = actual_link_speed;
7577 adapter->vf_data[vf].tx_rate = (u16)tx_rate;
7578 igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed);
7579
7580 return 0;
8151d294
WM		 7581}
7582
70ea4783
LL		 7583static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
7584 bool setting)
7585{
7586 struct igb_adapter *adapter = netdev_priv(netdev);
7587 struct e1000_hw *hw = &adapter->hw;
7588 u32 reg_val, reg_offset;
7589
7590 if (!adapter->vfs_allocated_count)
7591 return -EOPNOTSUPP;
7592
7593 if (vf >= adapter->vfs_allocated_count)
7594 return -EINVAL;
7595
7596 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
7597 reg_val = rd32(reg_offset);
7598 if (setting)
7599 reg_val |= ((1 << vf) |
7600 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7601 else
7602 reg_val &= ~((1 << vf) |
7603 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7604 wr32(reg_offset, reg_val);
7605
7606 adapter->vf_data[vf].spoofchk_enabled = setting;
7607 return E1000_SUCCESS;
7608}
7609
8151d294
WM		 7610static int igb_ndo_get_vf_config(struct net_device *netdev,
7611 int vf, struct ifla_vf_info *ivi)
7612{
7613 struct igb_adapter *adapter = netdev_priv(netdev);
7614 if (vf >= adapter->vfs_allocated_count)
7615 return -EINVAL;
7616 ivi->vf = vf;
7617 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
17dc566c 7618 ivi->tx_rate = adapter->vf_data[vf].tx_rate;
8151d294
WM		 7619 ivi->vlan = adapter->vf_data[vf].pf_vlan;
7620 ivi->qos = adapter->vf_data[vf].pf_qos;
70ea4783 7621 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
8151d294
WM		 7622 return 0;
7623}
7624
4ae196df
AD		 7625static void igb_vmm_control(struct igb_adapter *adapter)
7626{
7627 struct e1000_hw *hw = &adapter->hw;
10d8e907 7628 u32 reg;
4ae196df 7629
52a1dd4d
AD		 7630 switch (hw->mac.type) {
7631 case e1000_82575:
f96a8a0b
CW		 7632 case e1000_i210:
7633 case e1000_i211:
ceb5f13b 7634 case e1000_i354:
52a1dd4d
AD		 7635 default:
7636 /* replication is not supported for 82575 */
4ae196df 7637 return;
52a1dd4d
AD		 7638 case e1000_82576:
7639 /* notify HW that the MAC is adding vlan tags */
7640 reg = rd32(E1000_DTXCTL);
7641 reg |= E1000_DTXCTL_VLAN_ADDED;
7642 wr32(E1000_DTXCTL, reg);
7643 case e1000_82580:
7644 /* enable replication vlan tag stripping */
7645 reg = rd32(E1000_RPLOLR);
7646 reg |= E1000_RPLOLR_STRVLAN;
7647 wr32(E1000_RPLOLR, reg);
d2ba2ed8
AD		 7648 case e1000_i350:
7649 /* none of the above registers are supported by i350 */
52a1dd4d
AD		 7650 break;
7651 }
10d8e907 7652
d4960307
AD		 7653 if (adapter->vfs_allocated_count) {
7654 igb_vmdq_set_loopback_pf(hw, true);
7655 igb_vmdq_set_replication_pf(hw, true);
13800469 7656 igb_vmdq_set_anti_spoofing_pf(hw, true,
b980ac18 7657 adapter->vfs_allocated_count);
d4960307
AD		 7658 } else {
7659 igb_vmdq_set_loopback_pf(hw, false);
7660 igb_vmdq_set_replication_pf(hw, false);
7661 }
4ae196df
AD		 7662}
7663
b6e0c419
CW		 7664static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7665{
7666 struct e1000_hw *hw = &adapter->hw;
7667 u32 dmac_thr;
7668 u16 hwm;
7669
7670 if (hw->mac.type > e1000_82580) {
7671 if (adapter->flags & IGB_FLAG_DMAC) {
7672 u32 reg;
7673
7674 /* force threshold to 0. */
7675 wr32(E1000_DMCTXTH, 0);
7676
b980ac18 7677 /* DMA Coalescing high water mark needs to be greater
e8c626e9
MV		 7678 * than the Rx threshold. Set hwm to PBA - max frame
7679 * size in 16B units, capping it at PBA - 6KB.
b6e0c419 7680 */
e8c626e9
MV		 7681 hwm = 64 * pba - adapter->max_frame_size / 16;
7682 if (hwm < 64 * (pba - 6))
7683 hwm = 64 * (pba - 6);
7684 reg = rd32(E1000_FCRTC);
7685 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7686 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7687 & E1000_FCRTC_RTH_COAL_MASK);
7688 wr32(E1000_FCRTC, reg);
7689
b980ac18 7690 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
e8c626e9
MV		 7691 * frame size, capping it at PBA - 10KB.
7692 */
7693 dmac_thr = pba - adapter->max_frame_size / 512;
7694 if (dmac_thr < pba - 10)
7695 dmac_thr = pba - 10;
b6e0c419
CW		 7696 reg = rd32(E1000_DMACR);
7697 reg &= ~E1000_DMACR_DMACTHR_MASK;
b6e0c419
CW		 7698 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
7699 & E1000_DMACR_DMACTHR_MASK);
7700
7701 /* transition to L0x or L1 if available..*/
7702 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
7703
7704 /* watchdog timer= +-1000 usec in 32usec intervals */
7705 reg |= (1000 >> 5);
0c02dd98
MV		 7706
7707 /* Disable BMC-to-OS Watchdog Enable */
ceb5f13b
CW		 7708 if (hw->mac.type != e1000_i354)
7709 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
7710
b6e0c419
CW		 7711 wr32(E1000_DMACR, reg);
7712
b980ac18 7713 /* no lower threshold to disable
b6e0c419
CW		 7714 * coalescing(smart fifb)-UTRESH=0
7715 */
7716 wr32(E1000_DMCRTRH, 0);
b6e0c419
CW		 7717
7718 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
7719
7720 wr32(E1000_DMCTLX, reg);
7721
b980ac18 7722 /* free space in tx packet buffer to wake from
b6e0c419
CW		 7723 * DMA coal
7724 */
7725 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
7726 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
7727
b980ac18 7728 /* make low power state decision controlled
b6e0c419
CW		 7729 * by DMA coal
7730 */
7731 reg = rd32(E1000_PCIEMISC);
7732 reg &= ~E1000_PCIEMISC_LX_DECISION;
7733 wr32(E1000_PCIEMISC, reg);
7734 } /* endif adapter->dmac is not disabled */
7735 } else if (hw->mac.type == e1000_82580) {
7736 u32 reg = rd32(E1000_PCIEMISC);
7737 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
7738 wr32(E1000_DMACR, 0);
7739 }
7740}
7741
b980ac18
JK		 7742/**
7743 * igb_read_i2c_byte - Reads 8 bit word over I2C
441fc6fd
CW		 7744 * @hw: pointer to hardware structure
7745 * @byte_offset: byte offset to read
7746 * @dev_addr: device address
7747 * @data: value read
7748 *
7749 * Performs byte read operation over I2C interface at
7750 * a specified device address.
b980ac18 7751 **/
441fc6fd 7752s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 7753 u8 dev_addr, u8 *data)
441fc6fd
CW		 7754{
7755 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 7756 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 7757 s32 status;
7758 u16 swfw_mask = 0;
7759
7760 if (!this_client)
7761 return E1000_ERR_I2C;
7762
7763 swfw_mask = E1000_SWFW_PHY0_SM;
7764
7765 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
7766 != E1000_SUCCESS)
7767 return E1000_ERR_SWFW_SYNC;
7768
7769 status = i2c_smbus_read_byte_data(this_client, byte_offset);
7770 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
7771
7772 if (status < 0)
7773 return E1000_ERR_I2C;
7774 else {
7775 *data = status;
7776 return E1000_SUCCESS;
7777 }
7778}
7779
b980ac18
JK		 7780/**
7781 * igb_write_i2c_byte - Writes 8 bit word over I2C
441fc6fd
CW		 7782 * @hw: pointer to hardware structure
7783 * @byte_offset: byte offset to write
7784 * @dev_addr: device address
7785 * @data: value to write
7786 *
7787 * Performs byte write operation over I2C interface at
7788 * a specified device address.
b980ac18 7789 **/
441fc6fd 7790s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 7791 u8 dev_addr, u8 data)
441fc6fd
CW		 7792{
7793 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 7794 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 7795 s32 status;
7796 u16 swfw_mask = E1000_SWFW_PHY0_SM;
7797
7798 if (!this_client)
7799 return E1000_ERR_I2C;
7800
7801 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS)
7802 return E1000_ERR_SWFW_SYNC;
7803 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
7804 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
7805
7806 if (status)
7807 return E1000_ERR_I2C;
7808 else
7809 return E1000_SUCCESS;
7810
7811}
9d5c8243 7812/* igb_main.c */
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